Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
98d3f06f | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002 |
82efde3a | 3 | Free Software Foundation, Inc. |
252b5132 RH |
4 | Contributed by the OSF and Ralph Campbell. |
5 | Written by Keith Knowles and Ralph Campbell, working independently. | |
6 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
7 | Support. | |
8 | ||
9 | This file is part of GAS. | |
10 | ||
11 | GAS is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2, or (at your option) | |
14 | any later version. | |
15 | ||
16 | GAS is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with GAS; see the file COPYING. If not, write to the Free | |
23 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
24 | 02111-1307, USA. */ | |
25 | ||
26 | #include "as.h" | |
27 | #include "config.h" | |
28 | #include "subsegs.h" | |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 RH |
30 | |
31 | #ifdef USE_STDARG | |
32 | #include <stdarg.h> | |
33 | #endif | |
34 | #ifdef USE_VARARGS | |
35 | #include <varargs.h> | |
36 | #endif | |
37 | ||
38 | #include "opcode/mips.h" | |
39 | #include "itbl-ops.h" | |
c5dd6aab | 40 | #include "dwarf2dbg.h" |
252b5132 RH |
41 | |
42 | #ifdef DEBUG | |
43 | #define DBG(x) printf x | |
44 | #else | |
45 | #define DBG(x) | |
46 | #endif | |
47 | ||
48 | #ifdef OBJ_MAYBE_ELF | |
49 | /* Clean up namespace so we can include obj-elf.h too. */ | |
50 | static int mips_output_flavor PARAMS ((void)); | |
51 | static int mips_output_flavor () { return OUTPUT_FLAVOR; } | |
52 | #undef OBJ_PROCESS_STAB | |
53 | #undef OUTPUT_FLAVOR | |
54 | #undef S_GET_ALIGN | |
55 | #undef S_GET_SIZE | |
56 | #undef S_SET_ALIGN | |
57 | #undef S_SET_SIZE | |
252b5132 RH |
58 | #undef obj_frob_file |
59 | #undef obj_frob_file_after_relocs | |
60 | #undef obj_frob_symbol | |
61 | #undef obj_pop_insert | |
62 | #undef obj_sec_sym_ok_for_reloc | |
63 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
64 | ||
65 | #include "obj-elf.h" | |
66 | /* Fix any of them that we actually care about. */ | |
67 | #undef OUTPUT_FLAVOR | |
68 | #define OUTPUT_FLAVOR mips_output_flavor() | |
69 | #endif | |
70 | ||
71 | #if defined (OBJ_ELF) | |
72 | #include "elf/mips.h" | |
73 | #endif | |
74 | ||
75 | #ifndef ECOFF_DEBUGGING | |
76 | #define NO_ECOFF_DEBUGGING | |
77 | #define ECOFF_DEBUGGING 0 | |
78 | #endif | |
79 | ||
ecb4347a DJ |
80 | int mips_flag_mdebug = -1; |
81 | ||
252b5132 RH |
82 | #include "ecoff.h" |
83 | ||
84 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
85 | static char *mips_regmask_frag; | |
86 | #endif | |
87 | ||
85b51719 | 88 | #define ZERO 0 |
252b5132 RH |
89 | #define AT 1 |
90 | #define TREG 24 | |
91 | #define PIC_CALL_REG 25 | |
92 | #define KT0 26 | |
93 | #define KT1 27 | |
94 | #define GP 28 | |
95 | #define SP 29 | |
96 | #define FP 30 | |
97 | #define RA 31 | |
98 | ||
99 | #define ILLEGAL_REG (32) | |
100 | ||
101 | /* Allow override of standard little-endian ECOFF format. */ | |
102 | ||
103 | #ifndef ECOFF_LITTLE_FORMAT | |
104 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
105 | #endif | |
106 | ||
107 | extern int target_big_endian; | |
108 | ||
252b5132 RH |
109 | /* The name of the readonly data section. */ |
110 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \ | |
111 | ? ".data" \ | |
112 | : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ | |
113 | ? ".rdata" \ | |
056350c6 NC |
114 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
115 | ? ".rdata" \ | |
252b5132 RH |
116 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
117 | ? ".rodata" \ | |
118 | : (abort (), "")) | |
119 | ||
a325df1d TS |
120 | /* The ABI to use. */ |
121 | enum mips_abi_level | |
122 | { | |
123 | NO_ABI = 0, | |
124 | O32_ABI, | |
125 | O64_ABI, | |
126 | N32_ABI, | |
127 | N64_ABI, | |
128 | EABI_ABI | |
129 | }; | |
130 | ||
131 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 132 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 133 | |
252b5132 RH |
134 | /* This is the set of options which may be modified by the .set |
135 | pseudo-op. We use a struct so that .set push and .set pop are more | |
136 | reliable. */ | |
137 | ||
e972090a NC |
138 | struct mips_set_options |
139 | { | |
252b5132 RH |
140 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
141 | if it has not been initialized. Changed by `.set mipsN', and the | |
142 | -mipsN command line option, and the default CPU. */ | |
143 | int isa; | |
1f25f5d3 CD |
144 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
145 | if they have not been initialized. Changed by `.set <asename>', by | |
146 | command line options, and based on the default architecture. */ | |
147 | int ase_mips3d; | |
deec1734 | 148 | int ase_mdmx; |
252b5132 RH |
149 | /* Whether we are assembling for the mips16 processor. 0 if we are |
150 | not, 1 if we are, and -1 if the value has not been initialized. | |
151 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
152 | -nomips16 command line options, and the default CPU. */ | |
153 | int mips16; | |
154 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
155 | reorder' and `.set noreorder'. */ | |
156 | int noreorder; | |
157 | /* Non-zero if we should not permit the $at ($1) register to be used | |
158 | in instructions. Changed by `.set at' and `.set noat'. */ | |
159 | int noat; | |
160 | /* Non-zero if we should warn when a macro instruction expands into | |
161 | more than one machine instruction. Changed by `.set nomacro' and | |
162 | `.set macro'. */ | |
163 | int warn_about_macros; | |
164 | /* Non-zero if we should not move instructions. Changed by `.set | |
165 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
166 | int nomove; | |
167 | /* Non-zero if we should not optimize branches by moving the target | |
168 | of the branch into the delay slot. Actually, we don't perform | |
169 | this optimization anyhow. Changed by `.set bopt' and `.set | |
170 | nobopt'. */ | |
171 | int nobopt; | |
172 | /* Non-zero if we should not autoextend mips16 instructions. | |
173 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
174 | int noautoextend; | |
a325df1d TS |
175 | /* Restrict general purpose registers and floating point registers |
176 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
177 | is passed but can changed if the assembler code uses .set mipsN. */ | |
178 | int gp32; | |
179 | int fp32; | |
252b5132 RH |
180 | }; |
181 | ||
a325df1d | 182 | /* True if -mgp32 was passed. */ |
a8e8e863 | 183 | static int file_mips_gp32 = -1; |
a325df1d TS |
184 | |
185 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 186 | static int file_mips_fp32 = -1; |
a325df1d | 187 | |
252b5132 | 188 | /* This is the struct we use to hold the current set of options. Note |
a4672219 | 189 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to |
e7af610e | 190 | -1 to indicate that they have not been initialized. */ |
252b5132 | 191 | |
e972090a NC |
192 | static struct mips_set_options mips_opts = |
193 | { | |
316f5878 | 194 | ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0 |
e7af610e | 195 | }; |
252b5132 RH |
196 | |
197 | /* These variables are filled in with the masks of registers used. | |
198 | The object format code reads them and puts them in the appropriate | |
199 | place. */ | |
200 | unsigned long mips_gprmask; | |
201 | unsigned long mips_cprmask[4]; | |
202 | ||
203 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 204 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 205 | |
a4672219 TS |
206 | /* True if -mips16 was passed or implied by arguments passed on the |
207 | command line (e.g., by -march). */ | |
208 | static int file_ase_mips16; | |
209 | ||
1f25f5d3 CD |
210 | /* True if -mips3d was passed or implied by arguments passed on the |
211 | command line (e.g., by -march). */ | |
212 | static int file_ase_mips3d; | |
213 | ||
deec1734 CD |
214 | /* True if -mdmx was passed or implied by arguments passed on the |
215 | command line (e.g., by -march). */ | |
216 | static int file_ase_mdmx; | |
217 | ||
ec68c924 EC |
218 | /* The argument of the -march= flag. The architecture we are assembling. */ |
219 | static int mips_arch = CPU_UNKNOWN; | |
316f5878 RS |
220 | static const char *mips_arch_string; |
221 | static const struct mips_cpu_info *mips_arch_info; | |
ec68c924 EC |
222 | |
223 | /* The argument of the -mtune= flag. The architecture for which we | |
224 | are optimizing. */ | |
225 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 RS |
226 | static const char *mips_tune_string; |
227 | static const struct mips_cpu_info *mips_tune_info; | |
ec68c924 | 228 | |
316f5878 | 229 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
230 | static int mips_32bitmode = 0; |
231 | ||
9ce8a5dd GRK |
232 | /* Some ISA's have delay slots for instructions which read or write |
233 | from a coprocessor (eg. mips1-mips3); some don't (eg mips4). | |
bdaaa2e1 | 234 | Return true if instructions marked INSN_LOAD_COPROC_DELAY, |
9ce8a5dd GRK |
235 | INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a |
236 | delay slot in this ISA. The uses of this macro assume that any | |
237 | ISA that has delay slots for one of these, has them for all. They | |
238 | also assume that ISAs which don't have delays for these insns, don't | |
bdaaa2e1 | 239 | have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */ |
9ce8a5dd | 240 | #define ISA_HAS_COPROC_DELAYS(ISA) ( \ |
e7af610e NC |
241 | (ISA) == ISA_MIPS1 \ |
242 | || (ISA) == ISA_MIPS2 \ | |
243 | || (ISA) == ISA_MIPS3 \ | |
9ce8a5dd GRK |
244 | ) |
245 | ||
316f5878 RS |
246 | /* True if the given ABI requires 32-bit registers. */ |
247 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
248 | ||
249 | /* Likewise 64-bit registers. */ | |
250 | #define ABI_NEEDS_64BIT_REGS(ABI) \ | |
251 | ((ABI) == N32_ABI \ | |
252 | || (ABI) == N64_ABI \ | |
253 | || (ABI) == O64_ABI) | |
254 | ||
bdaaa2e1 | 255 | /* Return true if ISA supports 64 bit gp register instructions. */ |
9ce8a5dd | 256 | #define ISA_HAS_64BIT_REGS(ISA) ( \ |
e7af610e NC |
257 | (ISA) == ISA_MIPS3 \ |
258 | || (ISA) == ISA_MIPS4 \ | |
84ea6cf2 | 259 | || (ISA) == ISA_MIPS5 \ |
d1cf510e | 260 | || (ISA) == ISA_MIPS64 \ |
9ce8a5dd GRK |
261 | ) |
262 | ||
e013f690 | 263 | #define HAVE_32BIT_GPRS \ |
316f5878 | 264 | (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 265 | |
e013f690 | 266 | #define HAVE_32BIT_FPRS \ |
316f5878 | 267 | (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 RS |
268 | |
269 | #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS) | |
270 | #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS) | |
271 | ||
316f5878 | 272 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 273 | |
316f5878 | 274 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 TS |
275 | |
276 | /* We can only have 64bit addresses if the object file format | |
277 | supports it. */ | |
afdbd6d0 CD |
278 | #define HAVE_32BIT_ADDRESSES \ |
279 | (HAVE_32BIT_GPRS \ | |
280 | || ((bfd_arch_bits_per_address (stdoutput) == 32 \ | |
281 | || ! HAVE_64BIT_OBJECTS) \ | |
282 | && mips_pic != EMBEDDED_PIC)) | |
e013f690 TS |
283 | |
284 | #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES) | |
ca4e0257 | 285 | |
a4672219 | 286 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
287 | #define CPU_HAS_MIPS16(cpu) \ |
288 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
289 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 290 | |
1f25f5d3 CD |
291 | /* Return true if the given CPU supports the MIPS3D ASE. */ |
292 | #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \ | |
293 | ) | |
294 | ||
deec1734 | 295 | /* Return true if the given CPU supports the MDMX ASE. */ |
a4672219 | 296 | #define CPU_HAS_MDMX(cpu) (false \ |
deec1734 CD |
297 | ) |
298 | ||
bdaaa2e1 | 299 | /* Whether the processor uses hardware interlocks to protect |
252b5132 | 300 | reads from the HI and LO registers, and thus does not |
ec68c924 | 301 | require nops to be inserted. */ |
252b5132 | 302 | |
ec68c924 | 303 | #define hilo_interlocks (mips_arch == CPU_R4010 \ |
0a758a12 | 304 | || mips_arch == CPU_SB1 \ |
252b5132 RH |
305 | ) |
306 | ||
307 | /* Whether the processor uses hardware interlocks to protect reads | |
308 | from the GPRs, and thus does not require nops to be inserted. */ | |
309 | #define gpr_interlocks \ | |
e7af610e | 310 | (mips_opts.isa != ISA_MIPS1 \ |
ec68c924 | 311 | || mips_arch == CPU_R3900) |
252b5132 RH |
312 | |
313 | /* As with other "interlocks" this is used by hardware that has FP | |
314 | (co-processor) interlocks. */ | |
bdaaa2e1 | 315 | /* Itbl support may require additional care here. */ |
ec68c924 | 316 | #define cop_interlocks (mips_arch == CPU_R4300 \ |
0a758a12 | 317 | || mips_arch == CPU_SB1 \ |
252b5132 RH |
318 | ) |
319 | ||
6b76fefe CM |
320 | /* Is this a mfhi or mflo instruction? */ |
321 | #define MF_HILO_INSN(PINFO) \ | |
322 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) | |
323 | ||
252b5132 RH |
324 | /* MIPS PIC level. */ |
325 | ||
a161fe53 | 326 | enum mips_pic_level mips_pic; |
252b5132 | 327 | |
39c0a331 L |
328 | /* Warn about all NOPS that the assembler generates. */ |
329 | static int warn_nops = 0; | |
330 | ||
c9914766 | 331 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 332 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 333 | static int mips_big_got = 0; |
252b5132 RH |
334 | |
335 | /* 1 if trap instructions should used for overflow rather than break | |
336 | instructions. */ | |
c9914766 | 337 | static int mips_trap = 0; |
252b5132 | 338 | |
119d663a | 339 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 340 | by assembling two single width halves into two single width floating |
119d663a NC |
341 | point registers which just happen to alias the double width destination |
342 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 343 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
344 | automatically at assemble time. */ |
345 | static int mips_disable_float_construction; | |
346 | ||
252b5132 RH |
347 | /* Non-zero if any .set noreorder directives were used. */ |
348 | ||
349 | static int mips_any_noreorder; | |
350 | ||
6b76fefe CM |
351 | /* Non-zero if nops should be inserted when the register referenced in |
352 | an mfhi/mflo instruction is read in the next two instructions. */ | |
353 | static int mips_7000_hilo_fix; | |
354 | ||
252b5132 | 355 | /* The size of the small data section. */ |
156c2f8b | 356 | static unsigned int g_switch_value = 8; |
252b5132 RH |
357 | /* Whether the -G option was used. */ |
358 | static int g_switch_seen = 0; | |
359 | ||
360 | #define N_RMASK 0xc4 | |
361 | #define N_VFP 0xd4 | |
362 | ||
363 | /* If we can determine in advance that GP optimization won't be | |
364 | possible, we can skip the relaxation stuff that tries to produce | |
365 | GP-relative references. This makes delay slot optimization work | |
366 | better. | |
367 | ||
368 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
369 | gcc output. It needs to guess right for gcc, otherwise gcc |
370 | will put what it thinks is a GP-relative instruction in a branch | |
371 | delay slot. | |
252b5132 RH |
372 | |
373 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
374 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
375 | static int nopic_need_relax PARAMS ((symbolS *, int)); | |
376 | ||
377 | /* handle of the OPCODE hash table */ | |
378 | static struct hash_control *op_hash = NULL; | |
379 | ||
380 | /* The opcode hash table we use for the mips16. */ | |
381 | static struct hash_control *mips16_op_hash = NULL; | |
382 | ||
383 | /* This array holds the chars that always start a comment. If the | |
384 | pre-processor is disabled, these aren't very useful */ | |
385 | const char comment_chars[] = "#"; | |
386 | ||
387 | /* This array holds the chars that only start a comment at the beginning of | |
388 | a line. If the line seems to have the form '# 123 filename' | |
389 | .line and .file directives will appear in the pre-processed output */ | |
390 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
391 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 392 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
393 | /* Also note that C style comments are always supported. */ |
394 | const char line_comment_chars[] = "#"; | |
395 | ||
bdaaa2e1 | 396 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 397 | const char line_separator_chars[] = ";"; |
252b5132 RH |
398 | |
399 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
400 | const char EXP_CHARS[] = "eE"; | |
401 | ||
402 | /* Chars that mean this number is a floating point constant */ | |
403 | /* As in 0f12.456 */ | |
404 | /* or 0d1.2345e12 */ | |
405 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
406 | ||
407 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
408 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
409 | but nothing is ideal around here. | |
410 | */ | |
411 | ||
412 | static char *insn_error; | |
413 | ||
414 | static int auto_align = 1; | |
415 | ||
416 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
417 | offset in the stack frame from which to restore the $gp register. | |
418 | This is set by the .cprestore pseudo-op, and saved in this | |
419 | variable. */ | |
420 | static offsetT mips_cprestore_offset = -1; | |
421 | ||
6478892d TS |
422 | /* Similiar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
423 | more optimizations, it can use a register value instead of a memory-saved | |
956cd1d6 | 424 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
425 | static offsetT mips_cpreturn_offset = -1; |
426 | static int mips_cpreturn_register = -1; | |
427 | static int mips_gp_register = GP; | |
def2e0dd | 428 | static int mips_gprel_offset = 0; |
6478892d | 429 | |
7a621144 DJ |
430 | /* Whether mips_cprestore_offset has been set in the current function |
431 | (or whether it has already been warned about, if not). */ | |
432 | static int mips_cprestore_valid = 0; | |
433 | ||
252b5132 RH |
434 | /* This is the register which holds the stack frame, as set by the |
435 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
436 | static int mips_frame_reg = SP; | |
437 | ||
7a621144 DJ |
438 | /* Whether mips_frame_reg has been set in the current function |
439 | (or whether it has already been warned about, if not). */ | |
440 | static int mips_frame_reg_valid = 0; | |
441 | ||
252b5132 RH |
442 | /* To output NOP instructions correctly, we need to keep information |
443 | about the previous two instructions. */ | |
444 | ||
445 | /* Whether we are optimizing. The default value of 2 means to remove | |
446 | unneeded NOPs and swap branch instructions when possible. A value | |
447 | of 1 means to not swap branches. A value of 0 means to always | |
448 | insert NOPs. */ | |
449 | static int mips_optimize = 2; | |
450 | ||
451 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
452 | equivalent to seeing no -g option at all. */ | |
453 | static int mips_debug = 0; | |
454 | ||
455 | /* The previous instruction. */ | |
456 | static struct mips_cl_insn prev_insn; | |
457 | ||
458 | /* The instruction before prev_insn. */ | |
459 | static struct mips_cl_insn prev_prev_insn; | |
460 | ||
461 | /* If we don't want information for prev_insn or prev_prev_insn, we | |
462 | point the insn_mo field at this dummy integer. */ | |
43841e91 | 463 | static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 }; |
252b5132 RH |
464 | |
465 | /* Non-zero if prev_insn is valid. */ | |
466 | static int prev_insn_valid; | |
467 | ||
468 | /* The frag for the previous instruction. */ | |
469 | static struct frag *prev_insn_frag; | |
470 | ||
471 | /* The offset into prev_insn_frag for the previous instruction. */ | |
472 | static long prev_insn_where; | |
473 | ||
474 | /* The reloc type for the previous instruction, if any. */ | |
f6688943 | 475 | static bfd_reloc_code_real_type prev_insn_reloc_type[3]; |
252b5132 RH |
476 | |
477 | /* The reloc for the previous instruction, if any. */ | |
f6688943 | 478 | static fixS *prev_insn_fixp[3]; |
252b5132 RH |
479 | |
480 | /* Non-zero if the previous instruction was in a delay slot. */ | |
481 | static int prev_insn_is_delay_slot; | |
482 | ||
483 | /* Non-zero if the previous instruction was in a .set noreorder. */ | |
484 | static int prev_insn_unreordered; | |
485 | ||
486 | /* Non-zero if the previous instruction uses an extend opcode (if | |
487 | mips16). */ | |
488 | static int prev_insn_extended; | |
489 | ||
490 | /* Non-zero if the previous previous instruction was in a .set | |
491 | noreorder. */ | |
492 | static int prev_prev_insn_unreordered; | |
493 | ||
494 | /* If this is set, it points to a frag holding nop instructions which | |
495 | were inserted before the start of a noreorder section. If those | |
496 | nops turn out to be unnecessary, the size of the frag can be | |
497 | decreased. */ | |
498 | static fragS *prev_nop_frag; | |
499 | ||
500 | /* The number of nop instructions we created in prev_nop_frag. */ | |
501 | static int prev_nop_frag_holds; | |
502 | ||
503 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 504 | prev_nop_frag. */ |
252b5132 RH |
505 | static int prev_nop_frag_required; |
506 | ||
507 | /* The number of instructions we've seen since prev_nop_frag. */ | |
508 | static int prev_nop_frag_since; | |
509 | ||
510 | /* For ECOFF and ELF, relocations against symbols are done in two | |
511 | parts, with a HI relocation and a LO relocation. Each relocation | |
512 | has only 16 bits of space to store an addend. This means that in | |
513 | order for the linker to handle carries correctly, it must be able | |
514 | to locate both the HI and the LO relocation. This means that the | |
515 | relocations must appear in order in the relocation table. | |
516 | ||
517 | In order to implement this, we keep track of each unmatched HI | |
518 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 519 | corresponding LO relocation. */ |
252b5132 | 520 | |
e972090a NC |
521 | struct mips_hi_fixup |
522 | { | |
252b5132 RH |
523 | /* Next HI fixup. */ |
524 | struct mips_hi_fixup *next; | |
525 | /* This fixup. */ | |
526 | fixS *fixp; | |
527 | /* The section this fixup is in. */ | |
528 | segT seg; | |
529 | }; | |
530 | ||
531 | /* The list of unmatched HI relocs. */ | |
532 | ||
533 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
534 | ||
535 | /* Map normal MIPS register numbers to mips16 register numbers. */ | |
536 | ||
537 | #define X ILLEGAL_REG | |
e972090a NC |
538 | static const int mips32_to_16_reg_map[] = |
539 | { | |
252b5132 RH |
540 | X, X, 2, 3, 4, 5, 6, 7, |
541 | X, X, X, X, X, X, X, X, | |
542 | 0, 1, X, X, X, X, X, X, | |
543 | X, X, X, X, X, X, X, X | |
544 | }; | |
545 | #undef X | |
546 | ||
547 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
548 | ||
e972090a NC |
549 | static const unsigned int mips16_to_32_reg_map[] = |
550 | { | |
252b5132 RH |
551 | 16, 17, 2, 3, 4, 5, 6, 7 |
552 | }; | |
553 | \f | |
554 | /* Since the MIPS does not have multiple forms of PC relative | |
555 | instructions, we do not have to do relaxing as is done on other | |
556 | platforms. However, we do have to handle GP relative addressing | |
557 | correctly, which turns out to be a similar problem. | |
558 | ||
559 | Every macro that refers to a symbol can occur in (at least) two | |
560 | forms, one with GP relative addressing and one without. For | |
561 | example, loading a global variable into a register generally uses | |
562 | a macro instruction like this: | |
563 | lw $4,i | |
564 | If i can be addressed off the GP register (this is true if it is in | |
565 | the .sbss or .sdata section, or if it is known to be smaller than | |
566 | the -G argument) this will generate the following instruction: | |
567 | lw $4,i($gp) | |
568 | This instruction will use a GPREL reloc. If i can not be addressed | |
569 | off the GP register, the following instruction sequence will be used: | |
570 | lui $at,i | |
571 | lw $4,i($at) | |
572 | In this case the first instruction will have a HI16 reloc, and the | |
573 | second reloc will have a LO16 reloc. Both relocs will be against | |
574 | the symbol i. | |
575 | ||
576 | The issue here is that we may not know whether i is GP addressable | |
577 | until after we see the instruction that uses it. Therefore, we | |
578 | want to be able to choose the final instruction sequence only at | |
579 | the end of the assembly. This is similar to the way other | |
580 | platforms choose the size of a PC relative instruction only at the | |
581 | end of assembly. | |
582 | ||
583 | When generating position independent code we do not use GP | |
584 | addressing in quite the same way, but the issue still arises as | |
585 | external symbols and local symbols must be handled differently. | |
586 | ||
587 | We handle these issues by actually generating both possible | |
588 | instruction sequences. The longer one is put in a frag_var with | |
589 | type rs_machine_dependent. We encode what to do with the frag in | |
590 | the subtype field. We encode (1) the number of existing bytes to | |
591 | replace, (2) the number of new bytes to use, (3) the offset from | |
592 | the start of the existing bytes to the first reloc we must generate | |
593 | (that is, the offset is applied from the start of the existing | |
594 | bytes after they are replaced by the new bytes, if any), (4) the | |
595 | offset from the start of the existing bytes to the second reloc, | |
596 | (5) whether a third reloc is needed (the third reloc is always four | |
597 | bytes after the second reloc), and (6) whether to warn if this | |
598 | variant is used (this is sometimes needed if .set nomacro or .set | |
599 | noat is in effect). All these numbers are reasonably small. | |
600 | ||
601 | Generating two instruction sequences must be handled carefully to | |
602 | ensure that delay slots are handled correctly. Fortunately, there | |
603 | are a limited number of cases. When the second instruction | |
604 | sequence is generated, append_insn is directed to maintain the | |
605 | existing delay slot information, so it continues to apply to any | |
606 | code after the second instruction sequence. This means that the | |
607 | second instruction sequence must not impose any requirements not | |
608 | required by the first instruction sequence. | |
609 | ||
610 | These variant frags are then handled in functions called by the | |
611 | machine independent code. md_estimate_size_before_relax returns | |
612 | the final size of the frag. md_convert_frag sets up the final form | |
613 | of the frag. tc_gen_reloc adjust the first reloc and adds a second | |
614 | one if needed. */ | |
615 | #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \ | |
616 | ((relax_substateT) \ | |
617 | (((old) << 23) \ | |
618 | | ((new) << 16) \ | |
619 | | (((reloc1) + 64) << 9) \ | |
620 | | (((reloc2) + 64) << 2) \ | |
621 | | ((reloc3) ? (1 << 1) : 0) \ | |
622 | | ((warn) ? 1 : 0))) | |
623 | #define RELAX_OLD(i) (((i) >> 23) & 0x7f) | |
624 | #define RELAX_NEW(i) (((i) >> 16) & 0x7f) | |
9a41af64 TS |
625 | #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64) |
626 | #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64) | |
252b5132 RH |
627 | #define RELAX_RELOC3(i) (((i) >> 1) & 1) |
628 | #define RELAX_WARN(i) ((i) & 1) | |
629 | ||
630 | /* For mips16 code, we use an entirely different form of relaxation. | |
631 | mips16 supports two versions of most instructions which take | |
632 | immediate values: a small one which takes some small value, and a | |
633 | larger one which takes a 16 bit value. Since branches also follow | |
634 | this pattern, relaxing these values is required. | |
635 | ||
636 | We can assemble both mips16 and normal MIPS code in a single | |
637 | object. Therefore, we need to support this type of relaxation at | |
638 | the same time that we support the relaxation described above. We | |
639 | use the high bit of the subtype field to distinguish these cases. | |
640 | ||
641 | The information we store for this type of relaxation is the | |
642 | argument code found in the opcode file for this relocation, whether | |
643 | the user explicitly requested a small or extended form, and whether | |
644 | the relocation is in a jump or jal delay slot. That tells us the | |
645 | size of the value, and how it should be stored. We also store | |
646 | whether the fragment is considered to be extended or not. We also | |
647 | store whether this is known to be a branch to a different section, | |
648 | whether we have tried to relax this frag yet, and whether we have | |
649 | ever extended a PC relative fragment because of a shift count. */ | |
650 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
651 | (0x80000000 \ | |
652 | | ((type) & 0xff) \ | |
653 | | ((small) ? 0x100 : 0) \ | |
654 | | ((ext) ? 0x200 : 0) \ | |
655 | | ((dslot) ? 0x400 : 0) \ | |
656 | | ((jal_dslot) ? 0x800 : 0)) | |
657 | #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0) | |
658 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) | |
659 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
660 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
661 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
662 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
663 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
664 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
665 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
666 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
667 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
668 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 CD |
669 | |
670 | /* Is the given value a sign-extended 32-bit value? */ | |
671 | #define IS_SEXT_32BIT_NUM(x) \ | |
672 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
673 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
674 | ||
675 | /* Is the given value a sign-extended 16-bit value? */ | |
676 | #define IS_SEXT_16BIT_NUM(x) \ | |
677 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
678 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
679 | ||
252b5132 RH |
680 | \f |
681 | /* Prototypes for static functions. */ | |
682 | ||
683 | #ifdef __STDC__ | |
684 | #define internalError() \ | |
685 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) | |
686 | #else | |
687 | #define internalError() as_fatal (_("MIPS internal Error")); | |
688 | #endif | |
689 | ||
690 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
691 | ||
692 | static int insn_uses_reg PARAMS ((struct mips_cl_insn *ip, | |
693 | unsigned int reg, enum mips_regclass class)); | |
156c2f8b | 694 | static int reg_needs_delay PARAMS ((unsigned int)); |
252b5132 RH |
695 | static void mips16_mark_labels PARAMS ((void)); |
696 | static void append_insn PARAMS ((char *place, | |
697 | struct mips_cl_insn * ip, | |
698 | expressionS * p, | |
f6688943 | 699 | bfd_reloc_code_real_type *r, |
252b5132 RH |
700 | boolean)); |
701 | static void mips_no_prev_insn PARAMS ((int)); | |
702 | static void mips_emit_delays PARAMS ((boolean)); | |
703 | #ifdef USE_STDARG | |
704 | static void macro_build PARAMS ((char *place, int *counter, expressionS * ep, | |
705 | const char *name, const char *fmt, | |
706 | ...)); | |
707 | #else | |
708 | static void macro_build (); | |
709 | #endif | |
710 | static void mips16_macro_build PARAMS ((char *, int *, expressionS *, | |
711 | const char *, const char *, | |
712 | va_list)); | |
438c16b8 | 713 | static void macro_build_jalr PARAMS ((int, expressionS *)); |
252b5132 RH |
714 | static void macro_build_lui PARAMS ((char *place, int *counter, |
715 | expressionS * ep, int regnum)); | |
885add95 CD |
716 | static void macro_build_ldst_constoffset PARAMS ((char *place, int *counter, |
717 | expressionS * ep, const char *op, | |
718 | int valreg, int breg)); | |
252b5132 RH |
719 | static void set_at PARAMS ((int *counter, int reg, int unsignedp)); |
720 | static void check_absolute_expr PARAMS ((struct mips_cl_insn * ip, | |
721 | expressionS *)); | |
722 | static void load_register PARAMS ((int *, int, expressionS *, int)); | |
c9914766 | 723 | static void load_address PARAMS ((int *, int, expressionS *, int *)); |
ea1fb5dc | 724 | static void move_register PARAMS ((int *, int, int)); |
252b5132 RH |
725 | static void macro PARAMS ((struct mips_cl_insn * ip)); |
726 | static void mips16_macro PARAMS ((struct mips_cl_insn * ip)); | |
727 | #ifdef LOSING_COMPILER | |
728 | static void macro2 PARAMS ((struct mips_cl_insn * ip)); | |
729 | #endif | |
730 | static void mips_ip PARAMS ((char *str, struct mips_cl_insn * ip)); | |
731 | static void mips16_ip PARAMS ((char *str, struct mips_cl_insn * ip)); | |
732 | static void mips16_immed PARAMS ((char *, unsigned int, int, offsetT, boolean, | |
733 | boolean, boolean, unsigned long *, | |
734 | boolean *, unsigned short *)); | |
394f9b3a | 735 | static int my_getPercentOp PARAMS ((char **, unsigned int *, int *)); |
ad8d3bb3 TS |
736 | static int my_getSmallParser PARAMS ((char **, unsigned int *, int *)); |
737 | static int my_getSmallExpression PARAMS ((expressionS *, char *)); | |
738 | static void my_getExpression PARAMS ((expressionS *, char *)); | |
ae948b86 | 739 | #ifdef OBJ_ELF |
e013f690 | 740 | static int support_64bit_objects PARAMS((void)); |
ae948b86 | 741 | #endif |
316f5878 | 742 | static void mips_set_option_string PARAMS ((const char **, const char *)); |
252b5132 RH |
743 | static symbolS *get_symbol PARAMS ((void)); |
744 | static void mips_align PARAMS ((int to, int fill, symbolS *label)); | |
745 | static void s_align PARAMS ((int)); | |
746 | static void s_change_sec PARAMS ((int)); | |
cca86cc8 | 747 | static void s_change_section PARAMS ((int)); |
252b5132 RH |
748 | static void s_cons PARAMS ((int)); |
749 | static void s_float_cons PARAMS ((int)); | |
750 | static void s_mips_globl PARAMS ((int)); | |
751 | static void s_option PARAMS ((int)); | |
752 | static void s_mipsset PARAMS ((int)); | |
753 | static void s_abicalls PARAMS ((int)); | |
754 | static void s_cpload PARAMS ((int)); | |
6478892d TS |
755 | static void s_cpsetup PARAMS ((int)); |
756 | static void s_cplocal PARAMS ((int)); | |
252b5132 | 757 | static void s_cprestore PARAMS ((int)); |
6478892d TS |
758 | static void s_cpreturn PARAMS ((int)); |
759 | static void s_gpvalue PARAMS ((int)); | |
252b5132 RH |
760 | static void s_gpword PARAMS ((int)); |
761 | static void s_cpadd PARAMS ((int)); | |
762 | static void s_insn PARAMS ((int)); | |
763 | static void md_obj_begin PARAMS ((void)); | |
764 | static void md_obj_end PARAMS ((void)); | |
765 | static long get_number PARAMS ((void)); | |
766 | static void s_mips_ent PARAMS ((int)); | |
767 | static void s_mips_end PARAMS ((int)); | |
768 | static void s_mips_frame PARAMS ((int)); | |
769 | static void s_mips_mask PARAMS ((int)); | |
770 | static void s_mips_stab PARAMS ((int)); | |
771 | static void s_mips_weakext PARAMS ((int)); | |
c5dd6aab DJ |
772 | static void s_mips_file PARAMS ((int)); |
773 | static void s_mips_loc PARAMS ((int)); | |
252b5132 | 774 | static int mips16_extended_frag PARAMS ((fragS *, asection *, long)); |
252b5132 | 775 | static int validate_mips_insn PARAMS ((const struct mips_opcode *)); |
316f5878 | 776 | static void show PARAMS ((FILE *, const char *, int *, int *)); |
add55e1f RS |
777 | #ifdef OBJ_ELF |
778 | static int mips_need_elf_addend_fixup PARAMS ((fixS *)); | |
779 | #endif | |
e7af610e | 780 | |
ad8d3bb3 | 781 | /* Return values of my_getSmallExpression(). */ |
fb1b3232 | 782 | |
ad8d3bb3 | 783 | enum small_ex_type |
fb1b3232 TS |
784 | { |
785 | S_EX_NONE = 0, | |
ad8d3bb3 TS |
786 | S_EX_REGISTER, |
787 | ||
788 | /* Direct relocation creation by %percent_op(). */ | |
789 | S_EX_HALF, | |
fb1b3232 | 790 | S_EX_HI, |
ad8d3bb3 TS |
791 | S_EX_LO, |
792 | S_EX_GP_REL, | |
793 | S_EX_GOT, | |
794 | S_EX_CALL16, | |
795 | S_EX_GOT_DISP, | |
796 | S_EX_GOT_PAGE, | |
797 | S_EX_GOT_OFST, | |
798 | S_EX_GOT_HI, | |
799 | S_EX_GOT_LO, | |
800 | S_EX_NEG, | |
fb1b3232 TS |
801 | S_EX_HIGHER, |
802 | S_EX_HIGHEST, | |
ad8d3bb3 TS |
803 | S_EX_CALL_HI, |
804 | S_EX_CALL_LO | |
fb1b3232 TS |
805 | }; |
806 | ||
e7af610e NC |
807 | /* Table and functions used to map between CPU/ISA names, and |
808 | ISA levels, and CPU numbers. */ | |
809 | ||
e972090a NC |
810 | struct mips_cpu_info |
811 | { | |
e7af610e NC |
812 | const char *name; /* CPU or ISA name. */ |
813 | int is_isa; /* Is this an ISA? (If 0, a CPU.) */ | |
814 | int isa; /* ISA level. */ | |
815 | int cpu; /* CPU number (default CPU if ISA). */ | |
816 | }; | |
817 | ||
316f5878 RS |
818 | static void mips_set_architecture PARAMS ((const struct mips_cpu_info *)); |
819 | static void mips_set_tune PARAMS ((const struct mips_cpu_info *)); | |
820 | static boolean mips_strict_matching_cpu_name_p PARAMS ((const char *, | |
821 | const char *)); | |
822 | static boolean mips_matching_cpu_name_p PARAMS ((const char *, const char *)); | |
823 | static const struct mips_cpu_info *mips_parse_cpu PARAMS ((const char *, | |
824 | const char *)); | |
e7af610e | 825 | static const struct mips_cpu_info *mips_cpu_info_from_isa PARAMS ((int)); |
252b5132 RH |
826 | \f |
827 | /* Pseudo-op table. | |
828 | ||
829 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
830 | should be defined here, but are currently unsupported: .alias, | |
831 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
832 | ||
833 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
834 | specific to the type of debugging information being generated, and | |
835 | should be defined by the object format: .aent, .begin, .bend, | |
836 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
837 | .vreg. | |
838 | ||
839 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
840 | not MIPS CPU specific, but are also not specific to the object file | |
841 | format. This file is probably the best place to define them, but | |
842 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
843 | .struct. */ | |
844 | ||
e972090a NC |
845 | static const pseudo_typeS mips_pseudo_table[] = |
846 | { | |
beae10d5 | 847 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
848 | {"option", s_option, 0}, |
849 | {"set", s_mipsset, 0}, | |
850 | {"rdata", s_change_sec, 'r'}, | |
851 | {"sdata", s_change_sec, 's'}, | |
852 | {"livereg", s_ignore, 0}, | |
853 | {"abicalls", s_abicalls, 0}, | |
854 | {"cpload", s_cpload, 0}, | |
6478892d TS |
855 | {"cpsetup", s_cpsetup, 0}, |
856 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 857 | {"cprestore", s_cprestore, 0}, |
6478892d TS |
858 | {"cpreturn", s_cpreturn, 0}, |
859 | {"gpvalue", s_gpvalue, 0}, | |
252b5132 RH |
860 | {"gpword", s_gpword, 0}, |
861 | {"cpadd", s_cpadd, 0}, | |
862 | {"insn", s_insn, 0}, | |
863 | ||
beae10d5 | 864 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 RH |
865 | chips. */ |
866 | {"asciiz", stringer, 1}, | |
867 | {"bss", s_change_sec, 'b'}, | |
868 | {"err", s_err, 0}, | |
869 | {"half", s_cons, 1}, | |
870 | {"dword", s_cons, 3}, | |
871 | {"weakext", s_mips_weakext, 0}, | |
872 | ||
beae10d5 | 873 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
874 | here for one reason or another. */ |
875 | {"align", s_align, 0}, | |
876 | {"byte", s_cons, 0}, | |
877 | {"data", s_change_sec, 'd'}, | |
878 | {"double", s_float_cons, 'd'}, | |
879 | {"float", s_float_cons, 'f'}, | |
880 | {"globl", s_mips_globl, 0}, | |
881 | {"global", s_mips_globl, 0}, | |
882 | {"hword", s_cons, 1}, | |
883 | {"int", s_cons, 2}, | |
884 | {"long", s_cons, 2}, | |
885 | {"octa", s_cons, 4}, | |
886 | {"quad", s_cons, 3}, | |
cca86cc8 | 887 | {"section", s_change_section, 0}, |
252b5132 RH |
888 | {"short", s_cons, 1}, |
889 | {"single", s_float_cons, 'f'}, | |
890 | {"stabn", s_mips_stab, 'n'}, | |
891 | {"text", s_change_sec, 't'}, | |
892 | {"word", s_cons, 2}, | |
add56521 | 893 | |
add56521 | 894 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 895 | |
43841e91 | 896 | { NULL, NULL, 0 }, |
252b5132 RH |
897 | }; |
898 | ||
e972090a NC |
899 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
900 | { | |
beae10d5 KH |
901 | /* These pseudo-ops should be defined by the object file format. |
902 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
903 | {"aent", s_mips_ent, 1}, |
904 | {"bgnb", s_ignore, 0}, | |
905 | {"end", s_mips_end, 0}, | |
906 | {"endb", s_ignore, 0}, | |
907 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 908 | {"file", s_mips_file, 0}, |
252b5132 RH |
909 | {"fmask", s_mips_mask, 'F'}, |
910 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 911 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
912 | {"mask", s_mips_mask, 'R'}, |
913 | {"verstamp", s_ignore, 0}, | |
43841e91 | 914 | { NULL, NULL, 0 }, |
252b5132 RH |
915 | }; |
916 | ||
917 | extern void pop_insert PARAMS ((const pseudo_typeS *)); | |
918 | ||
919 | void | |
920 | mips_pop_insert () | |
921 | { | |
922 | pop_insert (mips_pseudo_table); | |
923 | if (! ECOFF_DEBUGGING) | |
924 | pop_insert (mips_nonecoff_pseudo_table); | |
925 | } | |
926 | \f | |
927 | /* Symbols labelling the current insn. */ | |
928 | ||
e972090a NC |
929 | struct insn_label_list |
930 | { | |
252b5132 RH |
931 | struct insn_label_list *next; |
932 | symbolS *label; | |
933 | }; | |
934 | ||
935 | static struct insn_label_list *insn_labels; | |
936 | static struct insn_label_list *free_insn_labels; | |
937 | ||
938 | static void mips_clear_insn_labels PARAMS ((void)); | |
939 | ||
940 | static inline void | |
941 | mips_clear_insn_labels () | |
942 | { | |
943 | register struct insn_label_list **pl; | |
944 | ||
945 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
946 | ; | |
947 | *pl = insn_labels; | |
948 | insn_labels = NULL; | |
949 | } | |
950 | \f | |
951 | static char *expr_end; | |
952 | ||
953 | /* Expressions which appear in instructions. These are set by | |
954 | mips_ip. */ | |
955 | ||
956 | static expressionS imm_expr; | |
957 | static expressionS offset_expr; | |
958 | ||
959 | /* Relocs associated with imm_expr and offset_expr. */ | |
960 | ||
f6688943 TS |
961 | static bfd_reloc_code_real_type imm_reloc[3] |
962 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
963 | static bfd_reloc_code_real_type offset_reloc[3] | |
964 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
965 | |
966 | /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */ | |
967 | ||
968 | static boolean imm_unmatched_hi; | |
969 | ||
970 | /* These are set by mips16_ip if an explicit extension is used. */ | |
971 | ||
972 | static boolean mips16_small, mips16_ext; | |
973 | ||
7ed4a06a | 974 | #ifdef OBJ_ELF |
ecb4347a DJ |
975 | /* The pdr segment for per procedure frame/regmask info. Not used for |
976 | ECOFF debugging. */ | |
252b5132 RH |
977 | |
978 | static segT pdr_seg; | |
7ed4a06a | 979 | #endif |
252b5132 | 980 | |
e013f690 TS |
981 | /* The default target format to use. */ |
982 | ||
983 | const char * | |
984 | mips_target_format () | |
985 | { | |
986 | switch (OUTPUT_FLAVOR) | |
987 | { | |
988 | case bfd_target_aout_flavour: | |
989 | return target_big_endian ? "a.out-mips-big" : "a.out-mips-little"; | |
990 | case bfd_target_ecoff_flavour: | |
991 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
992 | case bfd_target_coff_flavour: | |
993 | return "pe-mips"; | |
994 | case bfd_target_elf_flavour: | |
995 | #ifdef TE_TMIPS | |
cfe86eaa | 996 | /* This is traditional mips. */ |
e013f690 | 997 | return (target_big_endian |
cfe86eaa TS |
998 | ? (HAVE_64BIT_OBJECTS |
999 | ? "elf64-tradbigmips" | |
1000 | : (HAVE_NEWABI | |
1001 | ? "elf32-ntradbigmips" : "elf32-tradbigmips")) | |
1002 | : (HAVE_64BIT_OBJECTS | |
1003 | ? "elf64-tradlittlemips" | |
1004 | : (HAVE_NEWABI | |
1005 | ? "elf32-ntradlittlemips" : "elf32-tradlittlemips"))); | |
e013f690 TS |
1006 | #else |
1007 | return (target_big_endian | |
cfe86eaa TS |
1008 | ? (HAVE_64BIT_OBJECTS |
1009 | ? "elf64-bigmips" | |
1010 | : (HAVE_NEWABI | |
1011 | ? "elf32-nbigmips" : "elf32-bigmips")) | |
1012 | : (HAVE_64BIT_OBJECTS | |
1013 | ? "elf64-littlemips" | |
1014 | : (HAVE_NEWABI | |
1015 | ? "elf32-nlittlemips" : "elf32-littlemips"))); | |
e013f690 TS |
1016 | #endif |
1017 | default: | |
1018 | abort (); | |
1019 | return NULL; | |
1020 | } | |
1021 | } | |
1022 | ||
156c2f8b NC |
1023 | /* This function is called once, at assembler startup time. It should |
1024 | set up all the tables, etc. that the MD part of the assembler will need. */ | |
1025 | ||
252b5132 RH |
1026 | void |
1027 | md_begin () | |
1028 | { | |
252b5132 | 1029 | register const char *retval = NULL; |
156c2f8b | 1030 | int i = 0; |
252b5132 | 1031 | int broken = 0; |
1f25f5d3 | 1032 | |
ec68c924 | 1033 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, mips_arch)) |
252b5132 RH |
1034 | as_warn (_("Could not set architecture and machine")); |
1035 | ||
252b5132 RH |
1036 | op_hash = hash_new (); |
1037 | ||
1038 | for (i = 0; i < NUMOPCODES;) | |
1039 | { | |
1040 | const char *name = mips_opcodes[i].name; | |
1041 | ||
1042 | retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]); | |
1043 | if (retval != NULL) | |
1044 | { | |
1045 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
1046 | mips_opcodes[i].name, retval); | |
1047 | /* Probably a memory allocation problem? Give up now. */ | |
1048 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1049 | } | |
1050 | do | |
1051 | { | |
1052 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
1053 | { | |
1054 | if (!validate_mips_insn (&mips_opcodes[i])) | |
1055 | broken = 1; | |
1056 | } | |
1057 | ++i; | |
1058 | } | |
1059 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
1060 | } | |
1061 | ||
1062 | mips16_op_hash = hash_new (); | |
1063 | ||
1064 | i = 0; | |
1065 | while (i < bfd_mips16_num_opcodes) | |
1066 | { | |
1067 | const char *name = mips16_opcodes[i].name; | |
1068 | ||
1069 | retval = hash_insert (mips16_op_hash, name, (PTR) &mips16_opcodes[i]); | |
1070 | if (retval != NULL) | |
1071 | as_fatal (_("internal: can't hash `%s': %s"), | |
1072 | mips16_opcodes[i].name, retval); | |
1073 | do | |
1074 | { | |
1075 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1076 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1077 | != mips16_opcodes[i].match)) | |
1078 | { | |
1079 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
1080 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1081 | broken = 1; | |
1082 | } | |
1083 | ++i; | |
1084 | } | |
1085 | while (i < bfd_mips16_num_opcodes | |
1086 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1087 | } | |
1088 | ||
1089 | if (broken) | |
1090 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1091 | ||
1092 | /* We add all the general register names to the symbol table. This | |
1093 | helps us detect invalid uses of them. */ | |
1094 | for (i = 0; i < 32; i++) | |
1095 | { | |
1096 | char buf[5]; | |
1097 | ||
1098 | sprintf (buf, "$%d", i); | |
1099 | symbol_table_insert (symbol_new (buf, reg_section, i, | |
1100 | &zero_address_frag)); | |
1101 | } | |
76db943d TS |
1102 | symbol_table_insert (symbol_new ("$ra", reg_section, RA, |
1103 | &zero_address_frag)); | |
252b5132 RH |
1104 | symbol_table_insert (symbol_new ("$fp", reg_section, FP, |
1105 | &zero_address_frag)); | |
1106 | symbol_table_insert (symbol_new ("$sp", reg_section, SP, | |
1107 | &zero_address_frag)); | |
1108 | symbol_table_insert (symbol_new ("$gp", reg_section, GP, | |
1109 | &zero_address_frag)); | |
1110 | symbol_table_insert (symbol_new ("$at", reg_section, AT, | |
1111 | &zero_address_frag)); | |
1112 | symbol_table_insert (symbol_new ("$kt0", reg_section, KT0, | |
1113 | &zero_address_frag)); | |
1114 | symbol_table_insert (symbol_new ("$kt1", reg_section, KT1, | |
1115 | &zero_address_frag)); | |
85b51719 TS |
1116 | symbol_table_insert (symbol_new ("$zero", reg_section, ZERO, |
1117 | &zero_address_frag)); | |
252b5132 RH |
1118 | symbol_table_insert (symbol_new ("$pc", reg_section, -1, |
1119 | &zero_address_frag)); | |
1120 | ||
1121 | mips_no_prev_insn (false); | |
1122 | ||
1123 | mips_gprmask = 0; | |
1124 | mips_cprmask[0] = 0; | |
1125 | mips_cprmask[1] = 0; | |
1126 | mips_cprmask[2] = 0; | |
1127 | mips_cprmask[3] = 0; | |
1128 | ||
1129 | /* set the default alignment for the text section (2**2) */ | |
1130 | record_alignment (text_section, 2); | |
1131 | ||
1132 | if (USE_GLOBAL_POINTER_OPT) | |
1133 | bfd_set_gp_size (stdoutput, g_switch_value); | |
1134 | ||
1135 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1136 | { | |
1137 | /* On a native system, sections must be aligned to 16 byte | |
1138 | boundaries. When configured for an embedded ELF target, we | |
1139 | don't bother. */ | |
1140 | if (strcmp (TARGET_OS, "elf") != 0) | |
1141 | { | |
1142 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
1143 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
1144 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
1145 | } | |
1146 | ||
1147 | /* Create a .reginfo section for register masks and a .mdebug | |
1148 | section for debugging information. */ | |
1149 | { | |
1150 | segT seg; | |
1151 | subsegT subseg; | |
1152 | flagword flags; | |
1153 | segT sec; | |
1154 | ||
1155 | seg = now_seg; | |
1156 | subseg = now_subseg; | |
1157 | ||
1158 | /* The ABI says this section should be loaded so that the | |
1159 | running program can access it. However, we don't load it | |
1160 | if we are configured for an embedded target */ | |
1161 | flags = SEC_READONLY | SEC_DATA; | |
1162 | if (strcmp (TARGET_OS, "elf") != 0) | |
1163 | flags |= SEC_ALLOC | SEC_LOAD; | |
1164 | ||
316f5878 | 1165 | if (mips_abi != N64_ABI) |
252b5132 RH |
1166 | { |
1167 | sec = subseg_new (".reginfo", (subsegT) 0); | |
1168 | ||
195325d2 TS |
1169 | bfd_set_section_flags (stdoutput, sec, flags); |
1170 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 1171 | |
252b5132 RH |
1172 | #ifdef OBJ_ELF |
1173 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); | |
1174 | #endif | |
1175 | } | |
1176 | else | |
1177 | { | |
1178 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
1179 | .reginfo section. */ | |
1180 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
1181 | bfd_set_section_flags (stdoutput, sec, flags); |
1182 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 RH |
1183 | |
1184 | #ifdef OBJ_ELF | |
1185 | /* Set up the option header. */ | |
1186 | { | |
1187 | Elf_Internal_Options opthdr; | |
1188 | char *f; | |
1189 | ||
1190 | opthdr.kind = ODK_REGINFO; | |
1191 | opthdr.size = (sizeof (Elf_External_Options) | |
1192 | + sizeof (Elf64_External_RegInfo)); | |
1193 | opthdr.section = 0; | |
1194 | opthdr.info = 0; | |
1195 | f = frag_more (sizeof (Elf_External_Options)); | |
1196 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
1197 | (Elf_External_Options *) f); | |
1198 | ||
1199 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
1200 | } | |
1201 | #endif | |
1202 | } | |
1203 | ||
1204 | if (ECOFF_DEBUGGING) | |
1205 | { | |
1206 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1207 | (void) bfd_set_section_flags (stdoutput, sec, | |
1208 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1209 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1210 | } | |
ecb4347a DJ |
1211 | #ifdef OBJ_ELF |
1212 | else if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1213 | { | |
1214 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
1215 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
1216 | SEC_READONLY | SEC_RELOC | |
1217 | | SEC_DEBUGGING); | |
1218 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
1219 | } | |
252b5132 RH |
1220 | #endif |
1221 | ||
1222 | subseg_set (seg, subseg); | |
1223 | } | |
1224 | } | |
1225 | ||
1226 | if (! ECOFF_DEBUGGING) | |
1227 | md_obj_begin (); | |
1228 | } | |
1229 | ||
1230 | void | |
1231 | md_mips_end () | |
1232 | { | |
1233 | if (! ECOFF_DEBUGGING) | |
1234 | md_obj_end (); | |
1235 | } | |
1236 | ||
1237 | void | |
1238 | md_assemble (str) | |
1239 | char *str; | |
1240 | { | |
1241 | struct mips_cl_insn insn; | |
f6688943 TS |
1242 | bfd_reloc_code_real_type unused_reloc[3] |
1243 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
1244 | |
1245 | imm_expr.X_op = O_absent; | |
252b5132 RH |
1246 | imm_unmatched_hi = false; |
1247 | offset_expr.X_op = O_absent; | |
f6688943 TS |
1248 | imm_reloc[0] = BFD_RELOC_UNUSED; |
1249 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
1250 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
1251 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
1252 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
1253 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
1254 | |
1255 | if (mips_opts.mips16) | |
1256 | mips16_ip (str, &insn); | |
1257 | else | |
1258 | { | |
1259 | mips_ip (str, &insn); | |
beae10d5 KH |
1260 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
1261 | str, insn.insn_opcode)); | |
252b5132 RH |
1262 | } |
1263 | ||
1264 | if (insn_error) | |
1265 | { | |
1266 | as_bad ("%s `%s'", insn_error, str); | |
1267 | return; | |
1268 | } | |
1269 | ||
1270 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
1271 | { | |
1272 | if (mips_opts.mips16) | |
1273 | mips16_macro (&insn); | |
1274 | else | |
1275 | macro (&insn); | |
1276 | } | |
1277 | else | |
1278 | { | |
1279 | if (imm_expr.X_op != O_absent) | |
c4e7957c | 1280 | append_insn (NULL, &insn, &imm_expr, imm_reloc, imm_unmatched_hi); |
252b5132 | 1281 | else if (offset_expr.X_op != O_absent) |
c4e7957c | 1282 | append_insn (NULL, &insn, &offset_expr, offset_reloc, false); |
252b5132 | 1283 | else |
c4e7957c | 1284 | append_insn (NULL, &insn, NULL, unused_reloc, false); |
252b5132 RH |
1285 | } |
1286 | } | |
1287 | ||
1288 | /* See whether instruction IP reads register REG. CLASS is the type | |
1289 | of register. */ | |
1290 | ||
1291 | static int | |
1292 | insn_uses_reg (ip, reg, class) | |
1293 | struct mips_cl_insn *ip; | |
1294 | unsigned int reg; | |
1295 | enum mips_regclass class; | |
1296 | { | |
1297 | if (class == MIPS16_REG) | |
1298 | { | |
1299 | assert (mips_opts.mips16); | |
1300 | reg = mips16_to_32_reg_map[reg]; | |
1301 | class = MIPS_GR_REG; | |
1302 | } | |
1303 | ||
85b51719 TS |
1304 | /* Don't report on general register ZERO, since it never changes. */ |
1305 | if (class == MIPS_GR_REG && reg == ZERO) | |
252b5132 RH |
1306 | return 0; |
1307 | ||
1308 | if (class == MIPS_FP_REG) | |
1309 | { | |
1310 | assert (! mips_opts.mips16); | |
1311 | /* If we are called with either $f0 or $f1, we must check $f0. | |
1312 | This is not optimal, because it will introduce an unnecessary | |
1313 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
1314 | need to distinguish reading both $f0 and $f1 or just one of | |
1315 | them. Note that we don't have to check the other way, | |
1316 | because there is no instruction that sets both $f0 and $f1 | |
1317 | and requires a delay. */ | |
1318 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
1319 | && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1) | |
1320 | == (reg &~ (unsigned) 1))) | |
1321 | return 1; | |
1322 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
1323 | && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1) | |
1324 | == (reg &~ (unsigned) 1))) | |
1325 | return 1; | |
1326 | } | |
1327 | else if (! mips_opts.mips16) | |
1328 | { | |
1329 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
1330 | && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg) | |
1331 | return 1; | |
1332 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
1333 | && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg) | |
1334 | return 1; | |
1335 | } | |
1336 | else | |
1337 | { | |
1338 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
1339 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX) | |
1340 | & MIPS16OP_MASK_RX)] | |
1341 | == reg)) | |
1342 | return 1; | |
1343 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
1344 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY) | |
1345 | & MIPS16OP_MASK_RY)] | |
1346 | == reg)) | |
1347 | return 1; | |
1348 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
1349 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1350 | & MIPS16OP_MASK_MOVE32Z)] | |
1351 | == reg)) | |
1352 | return 1; | |
1353 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
1354 | return 1; | |
1355 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
1356 | return 1; | |
1357 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
1358 | return 1; | |
1359 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
1360 | && ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1361 | & MIPS16OP_MASK_REGR32) == reg) | |
1362 | return 1; | |
1363 | } | |
1364 | ||
1365 | return 0; | |
1366 | } | |
1367 | ||
1368 | /* This function returns true if modifying a register requires a | |
1369 | delay. */ | |
1370 | ||
1371 | static int | |
1372 | reg_needs_delay (reg) | |
156c2f8b | 1373 | unsigned int reg; |
252b5132 RH |
1374 | { |
1375 | unsigned long prev_pinfo; | |
1376 | ||
1377 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1378 | if (! mips_opts.noreorder | |
9ce8a5dd | 1379 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1380 | && ((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
1381 | || (! gpr_interlocks | |
1382 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
1383 | { | |
1384 | /* A load from a coprocessor or from memory. All load | |
1385 | delays delay the use of general register rt for one | |
1386 | instruction on the r3000. The r6000 and r4000 use | |
1387 | interlocks. */ | |
bdaaa2e1 | 1388 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1389 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1390 | if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)) | |
1391 | return 1; | |
1392 | } | |
1393 | ||
1394 | return 0; | |
1395 | } | |
1396 | ||
1397 | /* Mark instruction labels in mips16 mode. This permits the linker to | |
1398 | handle them specially, such as generating jalx instructions when | |
1399 | needed. We also make them odd for the duration of the assembly, in | |
1400 | order to generate the right sort of code. We will make them even | |
1401 | in the adjust_symtab routine, while leaving them marked. This is | |
1402 | convenient for the debugger and the disassembler. The linker knows | |
1403 | to make them odd again. */ | |
1404 | ||
1405 | static void | |
1406 | mips16_mark_labels () | |
1407 | { | |
1408 | if (mips_opts.mips16) | |
1409 | { | |
1410 | struct insn_label_list *l; | |
98aa84af | 1411 | valueT val; |
252b5132 RH |
1412 | |
1413 | for (l = insn_labels; l != NULL; l = l->next) | |
1414 | { | |
1415 | #ifdef OBJ_ELF | |
1416 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1417 | S_SET_OTHER (l->label, STO_MIPS16); | |
1418 | #endif | |
98aa84af AM |
1419 | val = S_GET_VALUE (l->label); |
1420 | if ((val & 1) == 0) | |
1421 | S_SET_VALUE (l->label, val + 1); | |
252b5132 RH |
1422 | } |
1423 | } | |
1424 | } | |
1425 | ||
1426 | /* Output an instruction. PLACE is where to put the instruction; if | |
1427 | it is NULL, this uses frag_more to get room. IP is the instruction | |
1428 | information. ADDRESS_EXPR is an operand of the instruction to be | |
1429 | used with RELOC_TYPE. */ | |
1430 | ||
1431 | static void | |
1432 | append_insn (place, ip, address_expr, reloc_type, unmatched_hi) | |
1433 | char *place; | |
1434 | struct mips_cl_insn *ip; | |
1435 | expressionS *address_expr; | |
f6688943 | 1436 | bfd_reloc_code_real_type *reloc_type; |
252b5132 RH |
1437 | boolean unmatched_hi; |
1438 | { | |
1439 | register unsigned long prev_pinfo, pinfo; | |
1440 | char *f; | |
f6688943 | 1441 | fixS *fixp[3]; |
252b5132 RH |
1442 | int nops = 0; |
1443 | ||
1444 | /* Mark instruction labels in mips16 mode. */ | |
f9419b05 | 1445 | mips16_mark_labels (); |
252b5132 RH |
1446 | |
1447 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1448 | pinfo = ip->insn_mo->pinfo; | |
1449 | ||
1450 | if (place == NULL && (! mips_opts.noreorder || prev_nop_frag != NULL)) | |
1451 | { | |
1452 | int prev_prev_nop; | |
1453 | ||
1454 | /* If the previous insn required any delay slots, see if we need | |
1455 | to insert a NOP or two. There are eight kinds of possible | |
1456 | hazards, of which an instruction can have at most one type. | |
1457 | (1) a load from memory delay | |
1458 | (2) a load from a coprocessor delay | |
1459 | (3) an unconditional branch delay | |
1460 | (4) a conditional branch delay | |
1461 | (5) a move to coprocessor register delay | |
1462 | (6) a load coprocessor register from memory delay | |
1463 | (7) a coprocessor condition code delay | |
1464 | (8) a HI/LO special register delay | |
1465 | ||
1466 | There are a lot of optimizations we could do that we don't. | |
1467 | In particular, we do not, in general, reorder instructions. | |
1468 | If you use gcc with optimization, it will reorder | |
1469 | instructions and generally do much more optimization then we | |
1470 | do here; repeating all that work in the assembler would only | |
1471 | benefit hand written assembly code, and does not seem worth | |
1472 | it. */ | |
1473 | ||
1474 | /* This is how a NOP is emitted. */ | |
1475 | #define emit_nop() \ | |
1476 | (mips_opts.mips16 \ | |
1477 | ? md_number_to_chars (frag_more (2), 0x6500, 2) \ | |
1478 | : md_number_to_chars (frag_more (4), 0, 4)) | |
1479 | ||
1480 | /* The previous insn might require a delay slot, depending upon | |
1481 | the contents of the current insn. */ | |
1482 | if (! mips_opts.mips16 | |
9ce8a5dd | 1483 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1484 | && (((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
1485 | && ! cop_interlocks) | |
1486 | || (! gpr_interlocks | |
1487 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
1488 | { | |
1489 | /* A load from a coprocessor or from memory. All load | |
1490 | delays delay the use of general register rt for one | |
1491 | instruction on the r3000. The r6000 and r4000 use | |
1492 | interlocks. */ | |
beae10d5 | 1493 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1494 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1495 | if (mips_optimize == 0 | |
1496 | || insn_uses_reg (ip, | |
1497 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1498 | & OP_MASK_RT), | |
1499 | MIPS_GR_REG)) | |
1500 | ++nops; | |
1501 | } | |
1502 | else if (! mips_opts.mips16 | |
9ce8a5dd | 1503 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 | 1504 | && (((prev_pinfo & INSN_COPROC_MOVE_DELAY) |
beae10d5 | 1505 | && ! cop_interlocks) |
e7af610e | 1506 | || (mips_opts.isa == ISA_MIPS1 |
252b5132 RH |
1507 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)))) |
1508 | { | |
1509 | /* A generic coprocessor delay. The previous instruction | |
1510 | modified a coprocessor general or control register. If | |
1511 | it modified a control register, we need to avoid any | |
1512 | coprocessor instruction (this is probably not always | |
1513 | required, but it sometimes is). If it modified a general | |
1514 | register, we avoid using that register. | |
1515 | ||
1516 | On the r6000 and r4000 loading a coprocessor register | |
1517 | from memory is interlocked, and does not require a delay. | |
1518 | ||
1519 | This case is not handled very well. There is no special | |
1520 | knowledge of CP0 handling, and the coprocessors other | |
1521 | than the floating point unit are not distinguished at | |
1522 | all. */ | |
1523 | /* Itbl support may require additional care here. FIXME! | |
bdaaa2e1 | 1524 | Need to modify this to include knowledge about |
252b5132 RH |
1525 | user specified delays! */ |
1526 | if (prev_pinfo & INSN_WRITE_FPR_T) | |
1527 | { | |
1528 | if (mips_optimize == 0 | |
1529 | || insn_uses_reg (ip, | |
1530 | ((prev_insn.insn_opcode >> OP_SH_FT) | |
1531 | & OP_MASK_FT), | |
1532 | MIPS_FP_REG)) | |
1533 | ++nops; | |
1534 | } | |
1535 | else if (prev_pinfo & INSN_WRITE_FPR_S) | |
1536 | { | |
1537 | if (mips_optimize == 0 | |
1538 | || insn_uses_reg (ip, | |
1539 | ((prev_insn.insn_opcode >> OP_SH_FS) | |
1540 | & OP_MASK_FS), | |
1541 | MIPS_FP_REG)) | |
1542 | ++nops; | |
1543 | } | |
1544 | else | |
1545 | { | |
1546 | /* We don't know exactly what the previous instruction | |
1547 | does. If the current instruction uses a coprocessor | |
1548 | register, we must insert a NOP. If previous | |
1549 | instruction may set the condition codes, and the | |
1550 | current instruction uses them, we must insert two | |
1551 | NOPS. */ | |
bdaaa2e1 | 1552 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1553 | if (mips_optimize == 0 |
1554 | || ((prev_pinfo & INSN_WRITE_COND_CODE) | |
1555 | && (pinfo & INSN_READ_COND_CODE))) | |
1556 | nops += 2; | |
1557 | else if (pinfo & INSN_COP) | |
1558 | ++nops; | |
1559 | } | |
1560 | } | |
1561 | else if (! mips_opts.mips16 | |
9ce8a5dd | 1562 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1563 | && (prev_pinfo & INSN_WRITE_COND_CODE) |
1564 | && ! cop_interlocks) | |
1565 | { | |
1566 | /* The previous instruction sets the coprocessor condition | |
1567 | codes, but does not require a general coprocessor delay | |
1568 | (this means it is a floating point comparison | |
1569 | instruction). If this instruction uses the condition | |
1570 | codes, we need to insert a single NOP. */ | |
beae10d5 | 1571 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1572 | if (mips_optimize == 0 |
1573 | || (pinfo & INSN_READ_COND_CODE)) | |
1574 | ++nops; | |
1575 | } | |
6b76fefe CM |
1576 | |
1577 | /* If we're fixing up mfhi/mflo for the r7000 and the | |
1578 | previous insn was an mfhi/mflo and the current insn | |
1579 | reads the register that the mfhi/mflo wrote to, then | |
1580 | insert two nops. */ | |
1581 | ||
1582 | else if (mips_7000_hilo_fix | |
1583 | && MF_HILO_INSN (prev_pinfo) | |
1584 | && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD) | |
beae10d5 KH |
1585 | & OP_MASK_RD), |
1586 | MIPS_GR_REG)) | |
6b76fefe CM |
1587 | { |
1588 | nops += 2; | |
1589 | } | |
1590 | ||
1591 | /* If we're fixing up mfhi/mflo for the r7000 and the | |
1592 | 2nd previous insn was an mfhi/mflo and the current insn | |
1593 | reads the register that the mfhi/mflo wrote to, then | |
1594 | insert one nop. */ | |
1595 | ||
1596 | else if (mips_7000_hilo_fix | |
1597 | && MF_HILO_INSN (prev_prev_insn.insn_opcode) | |
1598 | && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD) | |
1599 | & OP_MASK_RD), | |
1600 | MIPS_GR_REG)) | |
bdaaa2e1 | 1601 | |
6b76fefe | 1602 | { |
f9419b05 | 1603 | ++nops; |
6b76fefe | 1604 | } |
bdaaa2e1 | 1605 | |
252b5132 RH |
1606 | else if (prev_pinfo & INSN_READ_LO) |
1607 | { | |
1608 | /* The previous instruction reads the LO register; if the | |
1609 | current instruction writes to the LO register, we must | |
bdaaa2e1 KH |
1610 | insert two NOPS. Some newer processors have interlocks. |
1611 | Also the tx39's multiply instructions can be exectuted | |
252b5132 | 1612 | immediatly after a read from HI/LO (without the delay), |
bdaaa2e1 KH |
1613 | though the tx39's divide insns still do require the |
1614 | delay. */ | |
252b5132 | 1615 | if (! (hilo_interlocks |
ec68c924 | 1616 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
1617 | && (mips_optimize == 0 |
1618 | || (pinfo & INSN_WRITE_LO))) | |
1619 | nops += 2; | |
1620 | /* Most mips16 branch insns don't have a delay slot. | |
1621 | If a read from LO is immediately followed by a branch | |
1622 | to a write to LO we have a read followed by a write | |
1623 | less than 2 insns away. We assume the target of | |
1624 | a branch might be a write to LO, and insert a nop | |
bdaaa2e1 | 1625 | between a read and an immediately following branch. */ |
252b5132 RH |
1626 | else if (mips_opts.mips16 |
1627 | && (mips_optimize == 0 | |
1628 | || (pinfo & MIPS16_INSN_BRANCH))) | |
f9419b05 | 1629 | ++nops; |
252b5132 RH |
1630 | } |
1631 | else if (prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1632 | { | |
1633 | /* The previous instruction reads the HI register; if the | |
1634 | current instruction writes to the HI register, we must | |
1635 | insert a NOP. Some newer processors have interlocks. | |
bdaaa2e1 | 1636 | Also the note tx39's multiply above. */ |
252b5132 | 1637 | if (! (hilo_interlocks |
ec68c924 | 1638 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
1639 | && (mips_optimize == 0 |
1640 | || (pinfo & INSN_WRITE_HI))) | |
1641 | nops += 2; | |
1642 | /* Most mips16 branch insns don't have a delay slot. | |
1643 | If a read from HI is immediately followed by a branch | |
1644 | to a write to HI we have a read followed by a write | |
1645 | less than 2 insns away. We assume the target of | |
1646 | a branch might be a write to HI, and insert a nop | |
bdaaa2e1 | 1647 | between a read and an immediately following branch. */ |
252b5132 RH |
1648 | else if (mips_opts.mips16 |
1649 | && (mips_optimize == 0 | |
1650 | || (pinfo & MIPS16_INSN_BRANCH))) | |
f9419b05 | 1651 | ++nops; |
252b5132 RH |
1652 | } |
1653 | ||
1654 | /* If the previous instruction was in a noreorder section, then | |
1655 | we don't want to insert the nop after all. */ | |
bdaaa2e1 | 1656 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1657 | if (prev_insn_unreordered) |
1658 | nops = 0; | |
1659 | ||
1660 | /* There are two cases which require two intervening | |
1661 | instructions: 1) setting the condition codes using a move to | |
1662 | coprocessor instruction which requires a general coprocessor | |
1663 | delay and then reading the condition codes 2) reading the HI | |
1664 | or LO register and then writing to it (except on processors | |
1665 | which have interlocks). If we are not already emitting a NOP | |
1666 | instruction, we must check for these cases compared to the | |
1667 | instruction previous to the previous instruction. */ | |
1668 | if ((! mips_opts.mips16 | |
9ce8a5dd | 1669 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1670 | && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) |
1671 | && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) | |
1672 | && (pinfo & INSN_READ_COND_CODE) | |
1673 | && ! cop_interlocks) | |
1674 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO) | |
1675 | && (pinfo & INSN_WRITE_LO) | |
1676 | && ! (hilo_interlocks | |
ec68c924 | 1677 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))) |
252b5132 RH |
1678 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
1679 | && (pinfo & INSN_WRITE_HI) | |
1680 | && ! (hilo_interlocks | |
ec68c924 | 1681 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))))) |
252b5132 RH |
1682 | prev_prev_nop = 1; |
1683 | else | |
1684 | prev_prev_nop = 0; | |
1685 | ||
1686 | if (prev_prev_insn_unreordered) | |
1687 | prev_prev_nop = 0; | |
1688 | ||
1689 | if (prev_prev_nop && nops == 0) | |
1690 | ++nops; | |
1691 | ||
1692 | /* If we are being given a nop instruction, don't bother with | |
1693 | one of the nops we would otherwise output. This will only | |
1694 | happen when a nop instruction is used with mips_optimize set | |
1695 | to 0. */ | |
1696 | if (nops > 0 | |
1697 | && ! mips_opts.noreorder | |
156c2f8b | 1698 | && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0)) |
252b5132 RH |
1699 | --nops; |
1700 | ||
1701 | /* Now emit the right number of NOP instructions. */ | |
1702 | if (nops > 0 && ! mips_opts.noreorder) | |
1703 | { | |
1704 | fragS *old_frag; | |
1705 | unsigned long old_frag_offset; | |
1706 | int i; | |
1707 | struct insn_label_list *l; | |
1708 | ||
1709 | old_frag = frag_now; | |
1710 | old_frag_offset = frag_now_fix (); | |
1711 | ||
1712 | for (i = 0; i < nops; i++) | |
1713 | emit_nop (); | |
1714 | ||
1715 | if (listing) | |
1716 | { | |
1717 | listing_prev_line (); | |
1718 | /* We may be at the start of a variant frag. In case we | |
1719 | are, make sure there is enough space for the frag | |
1720 | after the frags created by listing_prev_line. The | |
1721 | argument to frag_grow here must be at least as large | |
1722 | as the argument to all other calls to frag_grow in | |
1723 | this file. We don't have to worry about being in the | |
1724 | middle of a variant frag, because the variants insert | |
1725 | all needed nop instructions themselves. */ | |
1726 | frag_grow (40); | |
1727 | } | |
1728 | ||
1729 | for (l = insn_labels; l != NULL; l = l->next) | |
1730 | { | |
98aa84af AM |
1731 | valueT val; |
1732 | ||
252b5132 | 1733 | assert (S_GET_SEGMENT (l->label) == now_seg); |
49309057 | 1734 | symbol_set_frag (l->label, frag_now); |
98aa84af | 1735 | val = (valueT) frag_now_fix (); |
252b5132 RH |
1736 | /* mips16 text labels are stored as odd. */ |
1737 | if (mips_opts.mips16) | |
f9419b05 | 1738 | ++val; |
98aa84af | 1739 | S_SET_VALUE (l->label, val); |
252b5132 RH |
1740 | } |
1741 | ||
1742 | #ifndef NO_ECOFF_DEBUGGING | |
1743 | if (ECOFF_DEBUGGING) | |
1744 | ecoff_fix_loc (old_frag, old_frag_offset); | |
1745 | #endif | |
1746 | } | |
1747 | else if (prev_nop_frag != NULL) | |
1748 | { | |
1749 | /* We have a frag holding nops we may be able to remove. If | |
1750 | we don't need any nops, we can decrease the size of | |
1751 | prev_nop_frag by the size of one instruction. If we do | |
bdaaa2e1 | 1752 | need some nops, we count them in prev_nops_required. */ |
252b5132 RH |
1753 | if (prev_nop_frag_since == 0) |
1754 | { | |
1755 | if (nops == 0) | |
1756 | { | |
1757 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
1758 | --prev_nop_frag_holds; | |
1759 | } | |
1760 | else | |
1761 | prev_nop_frag_required += nops; | |
1762 | } | |
1763 | else | |
1764 | { | |
1765 | if (prev_prev_nop == 0) | |
1766 | { | |
1767 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
1768 | --prev_nop_frag_holds; | |
1769 | } | |
1770 | else | |
1771 | ++prev_nop_frag_required; | |
1772 | } | |
1773 | ||
1774 | if (prev_nop_frag_holds <= prev_nop_frag_required) | |
1775 | prev_nop_frag = NULL; | |
1776 | ||
1777 | ++prev_nop_frag_since; | |
1778 | ||
1779 | /* Sanity check: by the time we reach the second instruction | |
1780 | after prev_nop_frag, we should have used up all the nops | |
1781 | one way or another. */ | |
1782 | assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL); | |
1783 | } | |
1784 | } | |
1785 | ||
f6688943 | 1786 | if (*reloc_type > BFD_RELOC_UNUSED) |
252b5132 RH |
1787 | { |
1788 | /* We need to set up a variant frag. */ | |
1789 | assert (mips_opts.mips16 && address_expr != NULL); | |
1790 | f = frag_var (rs_machine_dependent, 4, 0, | |
f6688943 | 1791 | RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED, |
252b5132 RH |
1792 | mips16_small, mips16_ext, |
1793 | (prev_pinfo | |
1794 | & INSN_UNCOND_BRANCH_DELAY), | |
f6688943 | 1795 | (*prev_insn_reloc_type |
252b5132 | 1796 | == BFD_RELOC_MIPS16_JMP)), |
c4e7957c | 1797 | make_expr_symbol (address_expr), 0, NULL); |
252b5132 RH |
1798 | } |
1799 | else if (place != NULL) | |
1800 | f = place; | |
1801 | else if (mips_opts.mips16 | |
1802 | && ! ip->use_extend | |
f6688943 | 1803 | && *reloc_type != BFD_RELOC_MIPS16_JMP) |
252b5132 RH |
1804 | { |
1805 | /* Make sure there is enough room to swap this instruction with | |
1806 | a following jump instruction. */ | |
1807 | frag_grow (6); | |
1808 | f = frag_more (2); | |
1809 | } | |
1810 | else | |
1811 | { | |
1812 | if (mips_opts.mips16 | |
1813 | && mips_opts.noreorder | |
1814 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
1815 | as_warn (_("extended instruction in delay slot")); | |
1816 | ||
1817 | f = frag_more (4); | |
1818 | } | |
1819 | ||
f6688943 TS |
1820 | fixp[0] = fixp[1] = fixp[2] = NULL; |
1821 | if (address_expr != NULL && *reloc_type < BFD_RELOC_UNUSED) | |
252b5132 RH |
1822 | { |
1823 | if (address_expr->X_op == O_constant) | |
1824 | { | |
4db1a35d | 1825 | valueT tmp; |
f6688943 TS |
1826 | |
1827 | switch (*reloc_type) | |
252b5132 RH |
1828 | { |
1829 | case BFD_RELOC_32: | |
1830 | ip->insn_opcode |= address_expr->X_add_number; | |
1831 | break; | |
1832 | ||
f6688943 TS |
1833 | case BFD_RELOC_MIPS_HIGHEST: |
1834 | tmp = (address_expr->X_add_number + 0x800080008000) >> 16; | |
1835 | tmp >>= 16; | |
1836 | ip->insn_opcode |= (tmp >> 16) & 0xffff; | |
1837 | break; | |
1838 | ||
1839 | case BFD_RELOC_MIPS_HIGHER: | |
1840 | tmp = (address_expr->X_add_number + 0x80008000) >> 16; | |
1841 | ip->insn_opcode |= (tmp >> 16) & 0xffff; | |
1842 | break; | |
1843 | ||
1844 | case BFD_RELOC_HI16_S: | |
1845 | ip->insn_opcode |= ((address_expr->X_add_number + 0x8000) | |
1846 | >> 16) & 0xffff; | |
1847 | break; | |
1848 | ||
1849 | case BFD_RELOC_HI16: | |
1850 | ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; | |
1851 | break; | |
1852 | ||
252b5132 | 1853 | case BFD_RELOC_LO16: |
ed6fb7bd | 1854 | case BFD_RELOC_MIPS_GOT_DISP: |
252b5132 RH |
1855 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
1856 | break; | |
1857 | ||
1858 | case BFD_RELOC_MIPS_JMP: | |
1859 | if ((address_expr->X_add_number & 3) != 0) | |
1860 | as_bad (_("jump to misaligned address (0x%lx)"), | |
1861 | (unsigned long) address_expr->X_add_number); | |
f3c0ec86 | 1862 | if (address_expr->X_add_number & ~0xfffffff) |
7496292d TS |
1863 | as_bad (_("jump address range overflow (0x%lx)"), |
1864 | (unsigned long) address_expr->X_add_number); | |
252b5132 RH |
1865 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; |
1866 | break; | |
1867 | ||
1868 | case BFD_RELOC_MIPS16_JMP: | |
1869 | if ((address_expr->X_add_number & 3) != 0) | |
1870 | as_bad (_("jump to misaligned address (0x%lx)"), | |
1871 | (unsigned long) address_expr->X_add_number); | |
f3c0ec86 | 1872 | if (address_expr->X_add_number & ~0xfffffff) |
7496292d TS |
1873 | as_bad (_("jump address range overflow (0x%lx)"), |
1874 | (unsigned long) address_expr->X_add_number); | |
252b5132 RH |
1875 | ip->insn_opcode |= |
1876 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
1877 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
1878 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
1879 | break; | |
1880 | ||
cb56d3d3 | 1881 | case BFD_RELOC_16_PCREL: |
233b8738 | 1882 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
cb56d3d3 TS |
1883 | break; |
1884 | ||
252b5132 RH |
1885 | case BFD_RELOC_16_PCREL_S2: |
1886 | goto need_reloc; | |
1887 | ||
1888 | default: | |
1889 | internalError (); | |
1890 | } | |
1891 | } | |
1892 | else | |
1893 | { | |
1894 | need_reloc: | |
f6688943 | 1895 | /* Don't generate a reloc if we are writing into a variant frag. */ |
252b5132 RH |
1896 | if (place == NULL) |
1897 | { | |
f6688943 TS |
1898 | fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal, 4, |
1899 | address_expr, | |
1900 | (*reloc_type == BFD_RELOC_16_PCREL | |
1901 | || *reloc_type == BFD_RELOC_16_PCREL_S2), | |
1902 | reloc_type[0]); | |
1903 | ||
b6ff326e | 1904 | /* These relocations can have an addend that won't fit in |
f6688943 TS |
1905 | 4 octets for 64bit assembly. */ |
1906 | if (HAVE_64BIT_GPRS && | |
1907 | (*reloc_type == BFD_RELOC_16 | |
98d3f06f KH |
1908 | || *reloc_type == BFD_RELOC_32 |
1909 | || *reloc_type == BFD_RELOC_MIPS_JMP | |
1910 | || *reloc_type == BFD_RELOC_HI16_S | |
1911 | || *reloc_type == BFD_RELOC_LO16 | |
1912 | || *reloc_type == BFD_RELOC_GPREL16 | |
1913 | || *reloc_type == BFD_RELOC_MIPS_LITERAL | |
1914 | || *reloc_type == BFD_RELOC_GPREL32 | |
1915 | || *reloc_type == BFD_RELOC_64 | |
1916 | || *reloc_type == BFD_RELOC_CTOR | |
1917 | || *reloc_type == BFD_RELOC_MIPS_SUB | |
1918 | || *reloc_type == BFD_RELOC_MIPS_HIGHEST | |
1919 | || *reloc_type == BFD_RELOC_MIPS_HIGHER | |
1920 | || *reloc_type == BFD_RELOC_MIPS_SCN_DISP | |
1921 | || *reloc_type == BFD_RELOC_MIPS_REL16 | |
1922 | || *reloc_type == BFD_RELOC_MIPS_RELGOT)) | |
f6688943 TS |
1923 | fixp[0]->fx_no_overflow = 1; |
1924 | ||
252b5132 RH |
1925 | if (unmatched_hi) |
1926 | { | |
1927 | struct mips_hi_fixup *hi_fixup; | |
1928 | ||
f6688943 | 1929 | assert (*reloc_type == BFD_RELOC_HI16_S); |
252b5132 RH |
1930 | hi_fixup = ((struct mips_hi_fixup *) |
1931 | xmalloc (sizeof (struct mips_hi_fixup))); | |
f6688943 | 1932 | hi_fixup->fixp = fixp[0]; |
252b5132 RH |
1933 | hi_fixup->seg = now_seg; |
1934 | hi_fixup->next = mips_hi_fixup_list; | |
1935 | mips_hi_fixup_list = hi_fixup; | |
1936 | } | |
f6688943 TS |
1937 | |
1938 | if (reloc_type[1] != BFD_RELOC_UNUSED) | |
1939 | { | |
1940 | /* FIXME: This symbol can be one of | |
1941 | RSS_UNDEF, RSS_GP, RSS_GP0, RSS_LOC. */ | |
1942 | address_expr->X_op = O_absent; | |
1943 | address_expr->X_add_symbol = 0; | |
1944 | address_expr->X_add_number = 0; | |
1945 | ||
1946 | fixp[1] = fix_new_exp (frag_now, f - frag_now->fr_literal, | |
1947 | 4, address_expr, false, | |
1948 | reloc_type[1]); | |
1949 | ||
b6ff326e | 1950 | /* These relocations can have an addend that won't fit in |
f6688943 TS |
1951 | 4 octets for 64bit assembly. */ |
1952 | if (HAVE_64BIT_GPRS && | |
1953 | (*reloc_type == BFD_RELOC_16 | |
1954 | || *reloc_type == BFD_RELOC_32 | |
1955 | || *reloc_type == BFD_RELOC_MIPS_JMP | |
1956 | || *reloc_type == BFD_RELOC_HI16_S | |
1957 | || *reloc_type == BFD_RELOC_LO16 | |
1958 | || *reloc_type == BFD_RELOC_GPREL16 | |
1959 | || *reloc_type == BFD_RELOC_MIPS_LITERAL | |
1960 | || *reloc_type == BFD_RELOC_GPREL32 | |
1961 | || *reloc_type == BFD_RELOC_64 | |
1962 | || *reloc_type == BFD_RELOC_CTOR | |
1963 | || *reloc_type == BFD_RELOC_MIPS_SUB | |
1964 | || *reloc_type == BFD_RELOC_MIPS_HIGHEST | |
1965 | || *reloc_type == BFD_RELOC_MIPS_HIGHER | |
1966 | || *reloc_type == BFD_RELOC_MIPS_SCN_DISP | |
1967 | || *reloc_type == BFD_RELOC_MIPS_REL16 | |
1968 | || *reloc_type == BFD_RELOC_MIPS_RELGOT)) | |
98d3f06f | 1969 | fixp[1]->fx_no_overflow = 1; |
f6688943 TS |
1970 | |
1971 | if (reloc_type[2] != BFD_RELOC_UNUSED) | |
1972 | { | |
1973 | address_expr->X_op = O_absent; | |
1974 | address_expr->X_add_symbol = 0; | |
1975 | address_expr->X_add_number = 0; | |
1976 | ||
1977 | fixp[2] = fix_new_exp (frag_now, | |
1978 | f - frag_now->fr_literal, 4, | |
1979 | address_expr, false, | |
1980 | reloc_type[2]); | |
1981 | ||
b6ff326e | 1982 | /* These relocations can have an addend that won't fit in |
f6688943 TS |
1983 | 4 octets for 64bit assembly. */ |
1984 | if (HAVE_64BIT_GPRS && | |
1985 | (*reloc_type == BFD_RELOC_16 | |
1986 | || *reloc_type == BFD_RELOC_32 | |
1987 | || *reloc_type == BFD_RELOC_MIPS_JMP | |
1988 | || *reloc_type == BFD_RELOC_HI16_S | |
1989 | || *reloc_type == BFD_RELOC_LO16 | |
1990 | || *reloc_type == BFD_RELOC_GPREL16 | |
1991 | || *reloc_type == BFD_RELOC_MIPS_LITERAL | |
1992 | || *reloc_type == BFD_RELOC_GPREL32 | |
1993 | || *reloc_type == BFD_RELOC_64 | |
1994 | || *reloc_type == BFD_RELOC_CTOR | |
1995 | || *reloc_type == BFD_RELOC_MIPS_SUB | |
1996 | || *reloc_type == BFD_RELOC_MIPS_HIGHEST | |
1997 | || *reloc_type == BFD_RELOC_MIPS_HIGHER | |
1998 | || *reloc_type == BFD_RELOC_MIPS_SCN_DISP | |
1999 | || *reloc_type == BFD_RELOC_MIPS_REL16 | |
2000 | || *reloc_type == BFD_RELOC_MIPS_RELGOT)) | |
98d3f06f | 2001 | fixp[2]->fx_no_overflow = 1; |
f6688943 TS |
2002 | } |
2003 | } | |
252b5132 RH |
2004 | } |
2005 | } | |
2006 | } | |
2007 | ||
2008 | if (! mips_opts.mips16) | |
c5dd6aab DJ |
2009 | { |
2010 | md_number_to_chars (f, ip->insn_opcode, 4); | |
2011 | #ifdef OBJ_ELF | |
2012 | dwarf2_emit_insn (4); | |
2013 | #endif | |
2014 | } | |
f6688943 | 2015 | else if (*reloc_type == BFD_RELOC_MIPS16_JMP) |
252b5132 RH |
2016 | { |
2017 | md_number_to_chars (f, ip->insn_opcode >> 16, 2); | |
2018 | md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2); | |
c5dd6aab DJ |
2019 | #ifdef OBJ_ELF |
2020 | dwarf2_emit_insn (4); | |
2021 | #endif | |
252b5132 RH |
2022 | } |
2023 | else | |
2024 | { | |
2025 | if (ip->use_extend) | |
2026 | { | |
2027 | md_number_to_chars (f, 0xf000 | ip->extend, 2); | |
2028 | f += 2; | |
2029 | } | |
2030 | md_number_to_chars (f, ip->insn_opcode, 2); | |
c5dd6aab DJ |
2031 | #ifdef OBJ_ELF |
2032 | dwarf2_emit_insn (ip->use_extend ? 4 : 2); | |
2033 | #endif | |
252b5132 RH |
2034 | } |
2035 | ||
2036 | /* Update the register mask information. */ | |
2037 | if (! mips_opts.mips16) | |
2038 | { | |
2039 | if (pinfo & INSN_WRITE_GPR_D) | |
2040 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD); | |
2041 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) | |
2042 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT); | |
2043 | if (pinfo & INSN_READ_GPR_S) | |
2044 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS); | |
2045 | if (pinfo & INSN_WRITE_GPR_31) | |
f9419b05 | 2046 | mips_gprmask |= 1 << RA; |
252b5132 RH |
2047 | if (pinfo & INSN_WRITE_FPR_D) |
2048 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD); | |
2049 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) | |
2050 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS); | |
2051 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) | |
2052 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT); | |
2053 | if ((pinfo & INSN_READ_FPR_R) != 0) | |
2054 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR); | |
2055 | if (pinfo & INSN_COP) | |
2056 | { | |
bdaaa2e1 KH |
2057 | /* We don't keep enough information to sort these cases out. |
2058 | The itbl support does keep this information however, although | |
2059 | we currently don't support itbl fprmats as part of the cop | |
2060 | instruction. May want to add this support in the future. */ | |
252b5132 RH |
2061 | } |
2062 | /* Never set the bit for $0, which is always zero. */ | |
beae10d5 | 2063 | mips_gprmask &= ~1 << 0; |
252b5132 RH |
2064 | } |
2065 | else | |
2066 | { | |
2067 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) | |
2068 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX) | |
2069 | & MIPS16OP_MASK_RX); | |
2070 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) | |
2071 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY) | |
2072 | & MIPS16OP_MASK_RY); | |
2073 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
2074 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ) | |
2075 | & MIPS16OP_MASK_RZ); | |
2076 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) | |
2077 | mips_gprmask |= 1 << TREG; | |
2078 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
2079 | mips_gprmask |= 1 << SP; | |
2080 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
2081 | mips_gprmask |= 1 << RA; | |
2082 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2083 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
2084 | if (pinfo & MIPS16_INSN_READ_Z) | |
2085 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
2086 | & MIPS16OP_MASK_MOVE32Z); | |
2087 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
2088 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
2089 | & MIPS16OP_MASK_REGR32); | |
2090 | } | |
2091 | ||
2092 | if (place == NULL && ! mips_opts.noreorder) | |
2093 | { | |
2094 | /* Filling the branch delay slot is more complex. We try to | |
2095 | switch the branch with the previous instruction, which we can | |
2096 | do if the previous instruction does not set up a condition | |
2097 | that the branch tests and if the branch is not itself the | |
2098 | target of any branch. */ | |
2099 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2100 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
2101 | { | |
2102 | if (mips_optimize < 2 | |
2103 | /* If we have seen .set volatile or .set nomove, don't | |
2104 | optimize. */ | |
2105 | || mips_opts.nomove != 0 | |
2106 | /* If we had to emit any NOP instructions, then we | |
2107 | already know we can not swap. */ | |
2108 | || nops != 0 | |
2109 | /* If we don't even know the previous insn, we can not | |
bdaaa2e1 | 2110 | swap. */ |
252b5132 RH |
2111 | || ! prev_insn_valid |
2112 | /* If the previous insn is already in a branch delay | |
2113 | slot, then we can not swap. */ | |
2114 | || prev_insn_is_delay_slot | |
2115 | /* If the previous previous insn was in a .set | |
2116 | noreorder, we can't swap. Actually, the MIPS | |
2117 | assembler will swap in this situation. However, gcc | |
2118 | configured -with-gnu-as will generate code like | |
2119 | .set noreorder | |
2120 | lw $4,XXX | |
2121 | .set reorder | |
2122 | INSN | |
2123 | bne $4,$0,foo | |
2124 | in which we can not swap the bne and INSN. If gcc is | |
2125 | not configured -with-gnu-as, it does not output the | |
2126 | .set pseudo-ops. We don't have to check | |
2127 | prev_insn_unreordered, because prev_insn_valid will | |
2128 | be 0 in that case. We don't want to use | |
2129 | prev_prev_insn_valid, because we do want to be able | |
2130 | to swap at the start of a function. */ | |
2131 | || prev_prev_insn_unreordered | |
2132 | /* If the branch is itself the target of a branch, we | |
2133 | can not swap. We cheat on this; all we check for is | |
2134 | whether there is a label on this instruction. If | |
2135 | there are any branches to anything other than a | |
2136 | label, users must use .set noreorder. */ | |
2137 | || insn_labels != NULL | |
2138 | /* If the previous instruction is in a variant frag, we | |
2139 | can not do the swap. This does not apply to the | |
2140 | mips16, which uses variant frags for different | |
2141 | purposes. */ | |
2142 | || (! mips_opts.mips16 | |
2143 | && prev_insn_frag->fr_type == rs_machine_dependent) | |
2144 | /* If the branch reads the condition codes, we don't | |
2145 | even try to swap, because in the sequence | |
2146 | ctc1 $X,$31 | |
2147 | INSN | |
2148 | INSN | |
2149 | bc1t LABEL | |
2150 | we can not swap, and I don't feel like handling that | |
2151 | case. */ | |
2152 | || (! mips_opts.mips16 | |
9ce8a5dd | 2153 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2154 | && (pinfo & INSN_READ_COND_CODE)) |
2155 | /* We can not swap with an instruction that requires a | |
2156 | delay slot, becase the target of the branch might | |
2157 | interfere with that instruction. */ | |
2158 | || (! mips_opts.mips16 | |
9ce8a5dd | 2159 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 | 2160 | && (prev_pinfo |
bdaaa2e1 | 2161 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2162 | & (INSN_LOAD_COPROC_DELAY |
2163 | | INSN_COPROC_MOVE_DELAY | |
2164 | | INSN_WRITE_COND_CODE))) | |
2165 | || (! (hilo_interlocks | |
ec68c924 | 2166 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
2167 | && (prev_pinfo |
2168 | & (INSN_READ_LO | |
2169 | | INSN_READ_HI))) | |
2170 | || (! mips_opts.mips16 | |
2171 | && ! gpr_interlocks | |
2172 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)) | |
2173 | || (! mips_opts.mips16 | |
e7af610e | 2174 | && mips_opts.isa == ISA_MIPS1 |
bdaaa2e1 | 2175 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2176 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)) |
2177 | /* We can not swap with a branch instruction. */ | |
2178 | || (prev_pinfo | |
2179 | & (INSN_UNCOND_BRANCH_DELAY | |
2180 | | INSN_COND_BRANCH_DELAY | |
2181 | | INSN_COND_BRANCH_LIKELY)) | |
2182 | /* We do not swap with a trap instruction, since it | |
2183 | complicates trap handlers to have the trap | |
2184 | instruction be in a delay slot. */ | |
2185 | || (prev_pinfo & INSN_TRAP) | |
2186 | /* If the branch reads a register that the previous | |
2187 | instruction sets, we can not swap. */ | |
2188 | || (! mips_opts.mips16 | |
2189 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2190 | && insn_uses_reg (ip, | |
2191 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
2192 | & OP_MASK_RT), | |
2193 | MIPS_GR_REG)) | |
2194 | || (! mips_opts.mips16 | |
2195 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2196 | && insn_uses_reg (ip, | |
2197 | ((prev_insn.insn_opcode >> OP_SH_RD) | |
2198 | & OP_MASK_RD), | |
2199 | MIPS_GR_REG)) | |
2200 | || (mips_opts.mips16 | |
2201 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
2202 | && insn_uses_reg (ip, | |
2203 | ((prev_insn.insn_opcode | |
2204 | >> MIPS16OP_SH_RX) | |
2205 | & MIPS16OP_MASK_RX), | |
2206 | MIPS16_REG)) | |
2207 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) | |
2208 | && insn_uses_reg (ip, | |
2209 | ((prev_insn.insn_opcode | |
2210 | >> MIPS16OP_SH_RY) | |
2211 | & MIPS16OP_MASK_RY), | |
2212 | MIPS16_REG)) | |
2213 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) | |
2214 | && insn_uses_reg (ip, | |
2215 | ((prev_insn.insn_opcode | |
2216 | >> MIPS16OP_SH_RZ) | |
2217 | & MIPS16OP_MASK_RZ), | |
2218 | MIPS16_REG)) | |
2219 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) | |
2220 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
2221 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2222 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
2223 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2224 | && insn_uses_reg (ip, | |
2225 | MIPS16OP_EXTRACT_REG32R (prev_insn. | |
2226 | insn_opcode), | |
2227 | MIPS_GR_REG)))) | |
2228 | /* If the branch writes a register that the previous | |
2229 | instruction sets, we can not swap (we know that | |
2230 | branches write only to RD or to $31). */ | |
2231 | || (! mips_opts.mips16 | |
2232 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2233 | && (((pinfo & INSN_WRITE_GPR_D) | |
2234 | && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT) | |
2235 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
2236 | || ((pinfo & INSN_WRITE_GPR_31) | |
2237 | && (((prev_insn.insn_opcode >> OP_SH_RT) | |
2238 | & OP_MASK_RT) | |
f9419b05 | 2239 | == RA)))) |
252b5132 RH |
2240 | || (! mips_opts.mips16 |
2241 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2242 | && (((pinfo & INSN_WRITE_GPR_D) | |
2243 | && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD) | |
2244 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
2245 | || ((pinfo & INSN_WRITE_GPR_31) | |
2246 | && (((prev_insn.insn_opcode >> OP_SH_RD) | |
2247 | & OP_MASK_RD) | |
f9419b05 | 2248 | == RA)))) |
252b5132 RH |
2249 | || (mips_opts.mips16 |
2250 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2251 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2252 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2253 | && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode) | |
2254 | == RA)))) | |
2255 | /* If the branch writes a register that the previous | |
2256 | instruction reads, we can not swap (we know that | |
2257 | branches only write to RD or to $31). */ | |
2258 | || (! mips_opts.mips16 | |
2259 | && (pinfo & INSN_WRITE_GPR_D) | |
2260 | && insn_uses_reg (&prev_insn, | |
2261 | ((ip->insn_opcode >> OP_SH_RD) | |
2262 | & OP_MASK_RD), | |
2263 | MIPS_GR_REG)) | |
2264 | || (! mips_opts.mips16 | |
2265 | && (pinfo & INSN_WRITE_GPR_31) | |
f9419b05 | 2266 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) |
252b5132 RH |
2267 | || (mips_opts.mips16 |
2268 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2269 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) | |
2270 | /* If we are generating embedded PIC code, the branch | |
2271 | might be expanded into a sequence which uses $at, so | |
2272 | we can't swap with an instruction which reads it. */ | |
2273 | || (mips_pic == EMBEDDED_PIC | |
2274 | && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG)) | |
2275 | /* If the previous previous instruction has a load | |
2276 | delay, and sets a register that the branch reads, we | |
2277 | can not swap. */ | |
2278 | || (! mips_opts.mips16 | |
9ce8a5dd | 2279 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
bdaaa2e1 | 2280 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2281 | && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) |
2282 | || (! gpr_interlocks | |
2283 | && (prev_prev_insn.insn_mo->pinfo | |
2284 | & INSN_LOAD_MEMORY_DELAY))) | |
2285 | && insn_uses_reg (ip, | |
2286 | ((prev_prev_insn.insn_opcode >> OP_SH_RT) | |
2287 | & OP_MASK_RT), | |
2288 | MIPS_GR_REG)) | |
2289 | /* If one instruction sets a condition code and the | |
2290 | other one uses a condition code, we can not swap. */ | |
2291 | || ((pinfo & INSN_READ_COND_CODE) | |
2292 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
2293 | || ((pinfo & INSN_WRITE_COND_CODE) | |
2294 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
2295 | /* If the previous instruction uses the PC, we can not | |
2296 | swap. */ | |
2297 | || (mips_opts.mips16 | |
2298 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
2299 | /* If the previous instruction was extended, we can not | |
2300 | swap. */ | |
2301 | || (mips_opts.mips16 && prev_insn_extended) | |
2302 | /* If the previous instruction had a fixup in mips16 | |
2303 | mode, we can not swap. This normally means that the | |
2304 | previous instruction was a 4 byte branch anyhow. */ | |
f6688943 | 2305 | || (mips_opts.mips16 && prev_insn_fixp[0]) |
bdaaa2e1 KH |
2306 | /* If the previous instruction is a sync, sync.l, or |
2307 | sync.p, we can not swap. */ | |
f173e82e | 2308 | || (prev_pinfo & INSN_SYNC)) |
252b5132 RH |
2309 | { |
2310 | /* We could do even better for unconditional branches to | |
2311 | portions of this object file; we could pick up the | |
2312 | instruction at the destination, put it in the delay | |
2313 | slot, and bump the destination address. */ | |
2314 | emit_nop (); | |
2315 | /* Update the previous insn information. */ | |
2316 | prev_prev_insn = *ip; | |
2317 | prev_insn.insn_mo = &dummy_opcode; | |
2318 | } | |
2319 | else | |
2320 | { | |
2321 | /* It looks like we can actually do the swap. */ | |
2322 | if (! mips_opts.mips16) | |
2323 | { | |
2324 | char *prev_f; | |
2325 | char temp[4]; | |
2326 | ||
2327 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
2328 | memcpy (temp, prev_f, 4); | |
2329 | memcpy (prev_f, f, 4); | |
2330 | memcpy (f, temp, 4); | |
f6688943 TS |
2331 | if (prev_insn_fixp[0]) |
2332 | { | |
2333 | prev_insn_fixp[0]->fx_frag = frag_now; | |
2334 | prev_insn_fixp[0]->fx_where = f - frag_now->fr_literal; | |
2335 | } | |
2336 | if (prev_insn_fixp[1]) | |
2337 | { | |
2338 | prev_insn_fixp[1]->fx_frag = frag_now; | |
2339 | prev_insn_fixp[1]->fx_where = f - frag_now->fr_literal; | |
2340 | } | |
2341 | if (prev_insn_fixp[2]) | |
252b5132 | 2342 | { |
f6688943 TS |
2343 | prev_insn_fixp[2]->fx_frag = frag_now; |
2344 | prev_insn_fixp[2]->fx_where = f - frag_now->fr_literal; | |
252b5132 | 2345 | } |
f6688943 | 2346 | if (fixp[0]) |
252b5132 | 2347 | { |
f6688943 TS |
2348 | fixp[0]->fx_frag = prev_insn_frag; |
2349 | fixp[0]->fx_where = prev_insn_where; | |
2350 | } | |
2351 | if (fixp[1]) | |
2352 | { | |
2353 | fixp[1]->fx_frag = prev_insn_frag; | |
2354 | fixp[1]->fx_where = prev_insn_where; | |
2355 | } | |
2356 | if (fixp[2]) | |
2357 | { | |
2358 | fixp[2]->fx_frag = prev_insn_frag; | |
2359 | fixp[2]->fx_where = prev_insn_where; | |
252b5132 RH |
2360 | } |
2361 | } | |
2362 | else | |
2363 | { | |
2364 | char *prev_f; | |
2365 | char temp[2]; | |
2366 | ||
f6688943 TS |
2367 | assert (prev_insn_fixp[0] == NULL); |
2368 | assert (prev_insn_fixp[1] == NULL); | |
2369 | assert (prev_insn_fixp[2] == NULL); | |
252b5132 RH |
2370 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; |
2371 | memcpy (temp, prev_f, 2); | |
2372 | memcpy (prev_f, f, 2); | |
f6688943 | 2373 | if (*reloc_type != BFD_RELOC_MIPS16_JMP) |
252b5132 | 2374 | { |
f6688943 | 2375 | assert (*reloc_type == BFD_RELOC_UNUSED); |
252b5132 RH |
2376 | memcpy (f, temp, 2); |
2377 | } | |
2378 | else | |
2379 | { | |
2380 | memcpy (f, f + 2, 2); | |
2381 | memcpy (f + 2, temp, 2); | |
2382 | } | |
f6688943 TS |
2383 | if (fixp[0]) |
2384 | { | |
2385 | fixp[0]->fx_frag = prev_insn_frag; | |
2386 | fixp[0]->fx_where = prev_insn_where; | |
2387 | } | |
2388 | if (fixp[1]) | |
2389 | { | |
2390 | fixp[1]->fx_frag = prev_insn_frag; | |
2391 | fixp[1]->fx_where = prev_insn_where; | |
2392 | } | |
2393 | if (fixp[2]) | |
252b5132 | 2394 | { |
f6688943 TS |
2395 | fixp[2]->fx_frag = prev_insn_frag; |
2396 | fixp[2]->fx_where = prev_insn_where; | |
252b5132 RH |
2397 | } |
2398 | } | |
2399 | ||
2400 | /* Update the previous insn information; leave prev_insn | |
2401 | unchanged. */ | |
2402 | prev_prev_insn = *ip; | |
2403 | } | |
2404 | prev_insn_is_delay_slot = 1; | |
2405 | ||
2406 | /* If that was an unconditional branch, forget the previous | |
2407 | insn information. */ | |
2408 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2409 | { | |
2410 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2411 | prev_insn.insn_mo = &dummy_opcode; | |
2412 | } | |
2413 | ||
f6688943 TS |
2414 | prev_insn_fixp[0] = NULL; |
2415 | prev_insn_fixp[1] = NULL; | |
2416 | prev_insn_fixp[2] = NULL; | |
2417 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; | |
2418 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2419 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2420 | prev_insn_extended = 0; |
2421 | } | |
2422 | else if (pinfo & INSN_COND_BRANCH_LIKELY) | |
2423 | { | |
2424 | /* We don't yet optimize a branch likely. What we should do | |
2425 | is look at the target, copy the instruction found there | |
2426 | into the delay slot, and increment the branch to jump to | |
2427 | the next instruction. */ | |
2428 | emit_nop (); | |
2429 | /* Update the previous insn information. */ | |
2430 | prev_prev_insn = *ip; | |
2431 | prev_insn.insn_mo = &dummy_opcode; | |
f6688943 TS |
2432 | prev_insn_fixp[0] = NULL; |
2433 | prev_insn_fixp[1] = NULL; | |
2434 | prev_insn_fixp[2] = NULL; | |
2435 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; | |
2436 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2437 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2438 | prev_insn_extended = 0; |
2439 | } | |
2440 | else | |
2441 | { | |
2442 | /* Update the previous insn information. */ | |
2443 | if (nops > 0) | |
2444 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2445 | else | |
2446 | prev_prev_insn = prev_insn; | |
2447 | prev_insn = *ip; | |
2448 | ||
2449 | /* Any time we see a branch, we always fill the delay slot | |
2450 | immediately; since this insn is not a branch, we know it | |
2451 | is not in a delay slot. */ | |
2452 | prev_insn_is_delay_slot = 0; | |
2453 | ||
f6688943 TS |
2454 | prev_insn_fixp[0] = fixp[0]; |
2455 | prev_insn_fixp[1] = fixp[1]; | |
2456 | prev_insn_fixp[2] = fixp[2]; | |
2457 | prev_insn_reloc_type[0] = reloc_type[0]; | |
2458 | prev_insn_reloc_type[1] = reloc_type[1]; | |
2459 | prev_insn_reloc_type[2] = reloc_type[2]; | |
252b5132 RH |
2460 | if (mips_opts.mips16) |
2461 | prev_insn_extended = (ip->use_extend | |
f6688943 | 2462 | || *reloc_type > BFD_RELOC_UNUSED); |
252b5132 RH |
2463 | } |
2464 | ||
2465 | prev_prev_insn_unreordered = prev_insn_unreordered; | |
2466 | prev_insn_unreordered = 0; | |
2467 | prev_insn_frag = frag_now; | |
2468 | prev_insn_where = f - frag_now->fr_literal; | |
2469 | prev_insn_valid = 1; | |
2470 | } | |
2471 | else if (place == NULL) | |
2472 | { | |
2473 | /* We need to record a bit of information even when we are not | |
2474 | reordering, in order to determine the base address for mips16 | |
2475 | PC relative relocs. */ | |
2476 | prev_prev_insn = prev_insn; | |
2477 | prev_insn = *ip; | |
f6688943 TS |
2478 | prev_insn_reloc_type[0] = reloc_type[0]; |
2479 | prev_insn_reloc_type[1] = reloc_type[1]; | |
2480 | prev_insn_reloc_type[2] = reloc_type[2]; | |
252b5132 RH |
2481 | prev_prev_insn_unreordered = prev_insn_unreordered; |
2482 | prev_insn_unreordered = 1; | |
2483 | } | |
2484 | ||
2485 | /* We just output an insn, so the next one doesn't have a label. */ | |
2486 | mips_clear_insn_labels (); | |
2487 | ||
2488 | /* We must ensure that a fixup associated with an unmatched %hi | |
2489 | reloc does not become a variant frag. Otherwise, the | |
2490 | rearrangement of %hi relocs in frob_file may confuse | |
2491 | tc_gen_reloc. */ | |
2492 | if (unmatched_hi) | |
2493 | { | |
2494 | frag_wane (frag_now); | |
2495 | frag_new (0); | |
2496 | } | |
2497 | } | |
2498 | ||
2499 | /* This function forgets that there was any previous instruction or | |
2500 | label. If PRESERVE is non-zero, it remembers enough information to | |
bdaaa2e1 | 2501 | know whether nops are needed before a noreorder section. */ |
252b5132 RH |
2502 | |
2503 | static void | |
2504 | mips_no_prev_insn (preserve) | |
2505 | int preserve; | |
2506 | { | |
2507 | if (! preserve) | |
2508 | { | |
2509 | prev_insn.insn_mo = &dummy_opcode; | |
2510 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2511 | prev_nop_frag = NULL; | |
2512 | prev_nop_frag_holds = 0; | |
2513 | prev_nop_frag_required = 0; | |
2514 | prev_nop_frag_since = 0; | |
2515 | } | |
2516 | prev_insn_valid = 0; | |
2517 | prev_insn_is_delay_slot = 0; | |
2518 | prev_insn_unreordered = 0; | |
2519 | prev_insn_extended = 0; | |
f6688943 TS |
2520 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; |
2521 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2522 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2523 | prev_prev_insn_unreordered = 0; |
2524 | mips_clear_insn_labels (); | |
2525 | } | |
2526 | ||
2527 | /* This function must be called whenever we turn on noreorder or emit | |
2528 | something other than instructions. It inserts any NOPS which might | |
2529 | be needed by the previous instruction, and clears the information | |
2530 | kept for the previous instructions. The INSNS parameter is true if | |
bdaaa2e1 | 2531 | instructions are to follow. */ |
252b5132 RH |
2532 | |
2533 | static void | |
2534 | mips_emit_delays (insns) | |
2535 | boolean insns; | |
2536 | { | |
2537 | if (! mips_opts.noreorder) | |
2538 | { | |
2539 | int nops; | |
2540 | ||
2541 | nops = 0; | |
2542 | if ((! mips_opts.mips16 | |
9ce8a5dd | 2543 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2544 | && (! cop_interlocks |
2545 | && (prev_insn.insn_mo->pinfo | |
2546 | & (INSN_LOAD_COPROC_DELAY | |
2547 | | INSN_COPROC_MOVE_DELAY | |
2548 | | INSN_WRITE_COND_CODE)))) | |
2549 | || (! hilo_interlocks | |
2550 | && (prev_insn.insn_mo->pinfo | |
2551 | & (INSN_READ_LO | |
2552 | | INSN_READ_HI))) | |
2553 | || (! mips_opts.mips16 | |
2554 | && ! gpr_interlocks | |
bdaaa2e1 | 2555 | && (prev_insn.insn_mo->pinfo |
252b5132 RH |
2556 | & INSN_LOAD_MEMORY_DELAY)) |
2557 | || (! mips_opts.mips16 | |
e7af610e | 2558 | && mips_opts.isa == ISA_MIPS1 |
252b5132 RH |
2559 | && (prev_insn.insn_mo->pinfo |
2560 | & INSN_COPROC_MEMORY_DELAY))) | |
2561 | { | |
beae10d5 | 2562 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2563 | ++nops; |
2564 | if ((! mips_opts.mips16 | |
9ce8a5dd | 2565 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2566 | && (! cop_interlocks |
2567 | && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
2568 | || (! hilo_interlocks | |
2569 | && ((prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
2570 | || (prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
2571 | ++nops; | |
2572 | ||
2573 | if (prev_insn_unreordered) | |
2574 | nops = 0; | |
2575 | } | |
2576 | else if ((! mips_opts.mips16 | |
9ce8a5dd | 2577 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2578 | && (! cop_interlocks |
2579 | && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
2580 | || (! hilo_interlocks | |
2581 | && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
2582 | || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
2583 | { | |
beae10d5 | 2584 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2585 | if (! prev_prev_insn_unreordered) |
2586 | ++nops; | |
2587 | } | |
2588 | ||
2589 | if (nops > 0) | |
2590 | { | |
2591 | struct insn_label_list *l; | |
2592 | ||
2593 | if (insns) | |
2594 | { | |
2595 | /* Record the frag which holds the nop instructions, so | |
2596 | that we can remove them if we don't need them. */ | |
2597 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); | |
2598 | prev_nop_frag = frag_now; | |
2599 | prev_nop_frag_holds = nops; | |
2600 | prev_nop_frag_required = 0; | |
2601 | prev_nop_frag_since = 0; | |
2602 | } | |
2603 | ||
2604 | for (; nops > 0; --nops) | |
2605 | emit_nop (); | |
2606 | ||
2607 | if (insns) | |
2608 | { | |
2609 | /* Move on to a new frag, so that it is safe to simply | |
bdaaa2e1 | 2610 | decrease the size of prev_nop_frag. */ |
252b5132 RH |
2611 | frag_wane (frag_now); |
2612 | frag_new (0); | |
2613 | } | |
2614 | ||
2615 | for (l = insn_labels; l != NULL; l = l->next) | |
2616 | { | |
98aa84af AM |
2617 | valueT val; |
2618 | ||
252b5132 | 2619 | assert (S_GET_SEGMENT (l->label) == now_seg); |
49309057 | 2620 | symbol_set_frag (l->label, frag_now); |
98aa84af | 2621 | val = (valueT) frag_now_fix (); |
252b5132 RH |
2622 | /* mips16 text labels are stored as odd. */ |
2623 | if (mips_opts.mips16) | |
f9419b05 | 2624 | ++val; |
98aa84af | 2625 | S_SET_VALUE (l->label, val); |
252b5132 RH |
2626 | } |
2627 | } | |
2628 | } | |
2629 | ||
2630 | /* Mark instruction labels in mips16 mode. */ | |
f9419b05 | 2631 | if (insns) |
252b5132 RH |
2632 | mips16_mark_labels (); |
2633 | ||
2634 | mips_no_prev_insn (insns); | |
2635 | } | |
2636 | ||
2637 | /* Build an instruction created by a macro expansion. This is passed | |
2638 | a pointer to the count of instructions created so far, an | |
2639 | expression, the name of the instruction to build, an operand format | |
2640 | string, and corresponding arguments. */ | |
2641 | ||
2642 | #ifdef USE_STDARG | |
2643 | static void | |
2644 | macro_build (char *place, | |
2645 | int *counter, | |
2646 | expressionS * ep, | |
2647 | const char *name, | |
2648 | const char *fmt, | |
2649 | ...) | |
2650 | #else | |
2651 | static void | |
2652 | macro_build (place, counter, ep, name, fmt, va_alist) | |
2653 | char *place; | |
2654 | int *counter; | |
2655 | expressionS *ep; | |
2656 | const char *name; | |
2657 | const char *fmt; | |
2658 | va_dcl | |
2659 | #endif | |
2660 | { | |
2661 | struct mips_cl_insn insn; | |
f6688943 | 2662 | bfd_reloc_code_real_type r[3]; |
252b5132 | 2663 | va_list args; |
252b5132 RH |
2664 | |
2665 | #ifdef USE_STDARG | |
2666 | va_start (args, fmt); | |
2667 | #else | |
2668 | va_start (args); | |
2669 | #endif | |
2670 | ||
2671 | /* | |
2672 | * If the macro is about to expand into a second instruction, | |
2673 | * print a warning if needed. We need to pass ip as a parameter | |
2674 | * to generate a better warning message here... | |
2675 | */ | |
2676 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) | |
2677 | as_warn (_("Macro instruction expanded into multiple instructions")); | |
2678 | ||
80cc45a5 EC |
2679 | /* |
2680 | * If the macro is about to expand into a second instruction, | |
2681 | * and it is in a delay slot, print a warning. | |
2682 | */ | |
2683 | if (place == NULL | |
2684 | && *counter == 1 | |
2685 | && mips_opts.noreorder | |
2686 | && (prev_prev_insn.insn_mo->pinfo | |
2687 | & (INSN_UNCOND_BRANCH_DELAY | INSN_COND_BRANCH_DELAY | |
2b2e39bf | 2688 | | INSN_COND_BRANCH_LIKELY)) != 0) |
80cc45a5 EC |
2689 | as_warn (_("Macro instruction expanded into multiple instructions in a branch delay slot")); |
2690 | ||
252b5132 | 2691 | if (place == NULL) |
f9419b05 | 2692 | ++*counter; /* bump instruction counter */ |
252b5132 RH |
2693 | |
2694 | if (mips_opts.mips16) | |
2695 | { | |
2696 | mips16_macro_build (place, counter, ep, name, fmt, args); | |
2697 | va_end (args); | |
2698 | return; | |
2699 | } | |
2700 | ||
f6688943 TS |
2701 | r[0] = BFD_RELOC_UNUSED; |
2702 | r[1] = BFD_RELOC_UNUSED; | |
2703 | r[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2704 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); |
2705 | assert (insn.insn_mo); | |
2706 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2707 | ||
2708 | /* Search until we get a match for NAME. */ | |
2709 | while (1) | |
2710 | { | |
deec1734 CD |
2711 | /* It is assumed here that macros will never generate |
2712 | MDMX or MIPS-3D instructions. */ | |
252b5132 RH |
2713 | if (strcmp (fmt, insn.insn_mo->args) == 0 |
2714 | && insn.insn_mo->pinfo != INSN_MACRO | |
aec421e0 TS |
2715 | && OPCODE_IS_MEMBER (insn.insn_mo, |
2716 | (mips_opts.isa | |
3396de36 | 2717 | | (file_ase_mips16 ? INSN_MIPS16 : 0)), |
aec421e0 | 2718 | mips_arch) |
ec68c924 | 2719 | && (mips_arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0)) |
252b5132 RH |
2720 | break; |
2721 | ||
2722 | ++insn.insn_mo; | |
2723 | assert (insn.insn_mo->name); | |
2724 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2725 | } | |
2726 | ||
2727 | insn.insn_opcode = insn.insn_mo->match; | |
2728 | for (;;) | |
2729 | { | |
2730 | switch (*fmt++) | |
2731 | { | |
2732 | case '\0': | |
2733 | break; | |
2734 | ||
2735 | case ',': | |
2736 | case '(': | |
2737 | case ')': | |
2738 | continue; | |
2739 | ||
2740 | case 't': | |
2741 | case 'w': | |
2742 | case 'E': | |
38487616 | 2743 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RT; |
252b5132 RH |
2744 | continue; |
2745 | ||
2746 | case 'c': | |
38487616 TS |
2747 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE; |
2748 | continue; | |
2749 | ||
252b5132 RH |
2750 | case 'T': |
2751 | case 'W': | |
38487616 | 2752 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FT; |
252b5132 RH |
2753 | continue; |
2754 | ||
2755 | case 'd': | |
2756 | case 'G': | |
38487616 | 2757 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RD; |
252b5132 RH |
2758 | continue; |
2759 | ||
4372b673 NC |
2760 | case 'U': |
2761 | { | |
2762 | int tmp = va_arg (args, int); | |
2763 | ||
38487616 TS |
2764 | insn.insn_opcode |= tmp << OP_SH_RT; |
2765 | insn.insn_opcode |= tmp << OP_SH_RD; | |
beae10d5 | 2766 | continue; |
4372b673 NC |
2767 | } |
2768 | ||
252b5132 RH |
2769 | case 'V': |
2770 | case 'S': | |
38487616 | 2771 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FS; |
252b5132 RH |
2772 | continue; |
2773 | ||
2774 | case 'z': | |
2775 | continue; | |
2776 | ||
2777 | case '<': | |
38487616 | 2778 | insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT; |
252b5132 RH |
2779 | continue; |
2780 | ||
2781 | case 'D': | |
38487616 | 2782 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FD; |
252b5132 RH |
2783 | continue; |
2784 | ||
2785 | case 'B': | |
38487616 | 2786 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20; |
252b5132 RH |
2787 | continue; |
2788 | ||
4372b673 | 2789 | case 'J': |
38487616 | 2790 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19; |
4372b673 NC |
2791 | continue; |
2792 | ||
252b5132 | 2793 | case 'q': |
38487616 | 2794 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2; |
252b5132 RH |
2795 | continue; |
2796 | ||
2797 | case 'b': | |
2798 | case 's': | |
2799 | case 'r': | |
2800 | case 'v': | |
38487616 | 2801 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RS; |
252b5132 RH |
2802 | continue; |
2803 | ||
2804 | case 'i': | |
2805 | case 'j': | |
2806 | case 'o': | |
f6688943 | 2807 | *r = (bfd_reloc_code_real_type) va_arg (args, int); |
cdf6fd85 | 2808 | assert (*r == BFD_RELOC_GPREL16 |
f6688943 TS |
2809 | || *r == BFD_RELOC_MIPS_LITERAL |
2810 | || *r == BFD_RELOC_MIPS_HIGHER | |
2811 | || *r == BFD_RELOC_HI16_S | |
2812 | || *r == BFD_RELOC_LO16 | |
2813 | || *r == BFD_RELOC_MIPS_GOT16 | |
2814 | || *r == BFD_RELOC_MIPS_CALL16 | |
438c16b8 TS |
2815 | || *r == BFD_RELOC_MIPS_GOT_DISP |
2816 | || *r == BFD_RELOC_MIPS_GOT_PAGE | |
2817 | || *r == BFD_RELOC_MIPS_GOT_OFST | |
f6688943 TS |
2818 | || *r == BFD_RELOC_MIPS_GOT_LO16 |
2819 | || *r == BFD_RELOC_MIPS_CALL_LO16 | |
252b5132 | 2820 | || (ep->X_op == O_subtract |
f6688943 | 2821 | && *r == BFD_RELOC_PCREL_LO16)); |
252b5132 RH |
2822 | continue; |
2823 | ||
2824 | case 'u': | |
f6688943 | 2825 | *r = (bfd_reloc_code_real_type) va_arg (args, int); |
252b5132 RH |
2826 | assert (ep != NULL |
2827 | && (ep->X_op == O_constant | |
2828 | || (ep->X_op == O_symbol | |
f6688943 TS |
2829 | && (*r == BFD_RELOC_MIPS_HIGHEST |
2830 | || *r == BFD_RELOC_HI16_S | |
2831 | || *r == BFD_RELOC_HI16 | |
2832 | || *r == BFD_RELOC_GPREL16 | |
2833 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
2834 | || *r == BFD_RELOC_MIPS_CALL_HI16)) | |
252b5132 | 2835 | || (ep->X_op == O_subtract |
f6688943 | 2836 | && *r == BFD_RELOC_PCREL_HI16_S))); |
252b5132 RH |
2837 | continue; |
2838 | ||
2839 | case 'p': | |
2840 | assert (ep != NULL); | |
2841 | /* | |
2842 | * This allows macro() to pass an immediate expression for | |
2843 | * creating short branches without creating a symbol. | |
2844 | * Note that the expression still might come from the assembly | |
2845 | * input, in which case the value is not checked for range nor | |
2846 | * is a relocation entry generated (yuck). | |
2847 | */ | |
2848 | if (ep->X_op == O_constant) | |
2849 | { | |
2850 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
2851 | ep = NULL; | |
2852 | } | |
2853 | else | |
cb56d3d3 | 2854 | if (mips_pic == EMBEDDED_PIC) |
f6688943 | 2855 | *r = BFD_RELOC_16_PCREL_S2; |
cb56d3d3 | 2856 | else |
f6688943 | 2857 | *r = BFD_RELOC_16_PCREL; |
252b5132 RH |
2858 | continue; |
2859 | ||
2860 | case 'a': | |
2861 | assert (ep != NULL); | |
f6688943 | 2862 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
2863 | continue; |
2864 | ||
2865 | case 'C': | |
2866 | insn.insn_opcode |= va_arg (args, unsigned long); | |
2867 | continue; | |
2868 | ||
2869 | default: | |
2870 | internalError (); | |
2871 | } | |
2872 | break; | |
2873 | } | |
2874 | va_end (args); | |
f6688943 | 2875 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 RH |
2876 | |
2877 | append_insn (place, &insn, ep, r, false); | |
2878 | } | |
2879 | ||
2880 | static void | |
2881 | mips16_macro_build (place, counter, ep, name, fmt, args) | |
2882 | char *place; | |
43841e91 | 2883 | int *counter ATTRIBUTE_UNUSED; |
252b5132 RH |
2884 | expressionS *ep; |
2885 | const char *name; | |
2886 | const char *fmt; | |
2887 | va_list args; | |
2888 | { | |
2889 | struct mips_cl_insn insn; | |
f6688943 TS |
2890 | bfd_reloc_code_real_type r[3] |
2891 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 2892 | |
252b5132 RH |
2893 | insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
2894 | assert (insn.insn_mo); | |
2895 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2896 | ||
2897 | while (strcmp (fmt, insn.insn_mo->args) != 0 | |
2898 | || insn.insn_mo->pinfo == INSN_MACRO) | |
2899 | { | |
2900 | ++insn.insn_mo; | |
2901 | assert (insn.insn_mo->name); | |
2902 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2903 | } | |
2904 | ||
2905 | insn.insn_opcode = insn.insn_mo->match; | |
2906 | insn.use_extend = false; | |
2907 | ||
2908 | for (;;) | |
2909 | { | |
2910 | int c; | |
2911 | ||
2912 | c = *fmt++; | |
2913 | switch (c) | |
2914 | { | |
2915 | case '\0': | |
2916 | break; | |
2917 | ||
2918 | case ',': | |
2919 | case '(': | |
2920 | case ')': | |
2921 | continue; | |
2922 | ||
2923 | case 'y': | |
2924 | case 'w': | |
2925 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY; | |
2926 | continue; | |
2927 | ||
2928 | case 'x': | |
2929 | case 'v': | |
2930 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX; | |
2931 | continue; | |
2932 | ||
2933 | case 'z': | |
2934 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ; | |
2935 | continue; | |
2936 | ||
2937 | case 'Z': | |
2938 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z; | |
2939 | continue; | |
2940 | ||
2941 | case '0': | |
2942 | case 'S': | |
2943 | case 'P': | |
2944 | case 'R': | |
2945 | continue; | |
2946 | ||
2947 | case 'X': | |
2948 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32; | |
2949 | continue; | |
2950 | ||
2951 | case 'Y': | |
2952 | { | |
2953 | int regno; | |
2954 | ||
2955 | regno = va_arg (args, int); | |
2956 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
2957 | insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
2958 | } | |
2959 | continue; | |
2960 | ||
2961 | case '<': | |
2962 | case '>': | |
2963 | case '4': | |
2964 | case '5': | |
2965 | case 'H': | |
2966 | case 'W': | |
2967 | case 'D': | |
2968 | case 'j': | |
2969 | case '8': | |
2970 | case 'V': | |
2971 | case 'C': | |
2972 | case 'U': | |
2973 | case 'k': | |
2974 | case 'K': | |
2975 | case 'p': | |
2976 | case 'q': | |
2977 | { | |
2978 | assert (ep != NULL); | |
2979 | ||
2980 | if (ep->X_op != O_constant) | |
874e8986 | 2981 | *r = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
2982 | else |
2983 | { | |
c4e7957c TS |
2984 | mips16_immed (NULL, 0, c, ep->X_add_number, false, false, |
2985 | false, &insn.insn_opcode, &insn.use_extend, | |
2986 | &insn.extend); | |
252b5132 | 2987 | ep = NULL; |
f6688943 | 2988 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
2989 | } |
2990 | } | |
2991 | continue; | |
2992 | ||
2993 | case '6': | |
2994 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6; | |
2995 | continue; | |
2996 | } | |
2997 | ||
2998 | break; | |
2999 | } | |
3000 | ||
f6688943 | 3001 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 RH |
3002 | |
3003 | append_insn (place, &insn, ep, r, false); | |
3004 | } | |
3005 | ||
438c16b8 TS |
3006 | /* |
3007 | * Generate a "jalr" instruction with a relocation hint to the called | |
3008 | * function. This occurs in NewABI PIC code. | |
3009 | */ | |
3010 | static void | |
3011 | macro_build_jalr (icnt, ep) | |
3012 | int icnt; | |
3013 | expressionS *ep; | |
3014 | { | |
f21f8242 AO |
3015 | char *f; |
3016 | ||
438c16b8 | 3017 | if (HAVE_NEWABI) |
f21f8242 AO |
3018 | { |
3019 | frag_grow (4); | |
3020 | f = frag_more (0); | |
3021 | } | |
438c16b8 TS |
3022 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", "d,s", |
3023 | RA, PIC_CALL_REG); | |
3024 | if (HAVE_NEWABI) | |
f21f8242 AO |
3025 | fix_new_exp (frag_now, f - frag_now->fr_literal, |
3026 | 0, ep, false, BFD_RELOC_MIPS_JALR); | |
438c16b8 TS |
3027 | } |
3028 | ||
252b5132 RH |
3029 | /* |
3030 | * Generate a "lui" instruction. | |
3031 | */ | |
3032 | static void | |
3033 | macro_build_lui (place, counter, ep, regnum) | |
3034 | char *place; | |
3035 | int *counter; | |
3036 | expressionS *ep; | |
3037 | int regnum; | |
3038 | { | |
3039 | expressionS high_expr; | |
3040 | struct mips_cl_insn insn; | |
f6688943 TS |
3041 | bfd_reloc_code_real_type r[3] |
3042 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
5a38dc70 AM |
3043 | const char *name = "lui"; |
3044 | const char *fmt = "t,u"; | |
252b5132 RH |
3045 | |
3046 | assert (! mips_opts.mips16); | |
3047 | ||
3048 | if (place == NULL) | |
3049 | high_expr = *ep; | |
3050 | else | |
3051 | { | |
3052 | high_expr.X_op = O_constant; | |
3053 | high_expr.X_add_number = ep->X_add_number; | |
3054 | } | |
3055 | ||
3056 | if (high_expr.X_op == O_constant) | |
3057 | { | |
3058 | /* we can compute the instruction now without a relocation entry */ | |
e7d556df TS |
3059 | high_expr.X_add_number = ((high_expr.X_add_number + 0x8000) |
3060 | >> 16) & 0xffff; | |
f6688943 | 3061 | *r = BFD_RELOC_UNUSED; |
252b5132 | 3062 | } |
f6688943 | 3063 | else if (! HAVE_NEWABI) |
252b5132 RH |
3064 | { |
3065 | assert (ep->X_op == O_symbol); | |
3066 | /* _gp_disp is a special case, used from s_cpload. */ | |
3067 | assert (mips_pic == NO_PIC | |
3068 | || strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0); | |
f6688943 | 3069 | *r = BFD_RELOC_HI16_S; |
252b5132 RH |
3070 | } |
3071 | ||
3072 | /* | |
3073 | * If the macro is about to expand into a second instruction, | |
3074 | * print a warning if needed. We need to pass ip as a parameter | |
3075 | * to generate a better warning message here... | |
3076 | */ | |
3077 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) | |
3078 | as_warn (_("Macro instruction expanded into multiple instructions")); | |
3079 | ||
3080 | if (place == NULL) | |
f9419b05 | 3081 | ++*counter; /* bump instruction counter */ |
252b5132 RH |
3082 | |
3083 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
3084 | assert (insn.insn_mo); | |
3085 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3086 | assert (strcmp (fmt, insn.insn_mo->args) == 0); | |
3087 | ||
3088 | insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT); | |
f6688943 | 3089 | if (*r == BFD_RELOC_UNUSED) |
252b5132 RH |
3090 | { |
3091 | insn.insn_opcode |= high_expr.X_add_number; | |
3092 | append_insn (place, &insn, NULL, r, false); | |
3093 | } | |
3094 | else | |
3095 | append_insn (place, &insn, &high_expr, r, false); | |
3096 | } | |
3097 | ||
885add95 CD |
3098 | /* Generate a sequence of instructions to do a load or store from a constant |
3099 | offset off of a base register (breg) into/from a target register (treg), | |
3100 | using AT if necessary. */ | |
3101 | static void | |
3102 | macro_build_ldst_constoffset (place, counter, ep, op, treg, breg) | |
3103 | char *place; | |
3104 | int *counter; | |
3105 | expressionS *ep; | |
3106 | const char *op; | |
3107 | int treg, breg; | |
3108 | { | |
3109 | assert (ep->X_op == O_constant); | |
3110 | ||
3111 | /* Right now, this routine can only handle signed 32-bit contants. */ | |
3112 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number)) | |
3113 | as_warn (_("operand overflow")); | |
3114 | ||
3115 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
3116 | { | |
3117 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
3118 | macro_build (place, counter, ep, op, "t,o(b)", treg, | |
3119 | (int) BFD_RELOC_LO16, breg); | |
3120 | } | |
3121 | else | |
3122 | { | |
3123 | /* 32-bit offset, need multiple instructions and AT, like: | |
3124 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
3125 | addu $tempreg,$tempreg,$breg | |
3126 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
3127 | to handle the complete offset. */ | |
3128 | macro_build_lui (place, counter, ep, AT); | |
3129 | if (place != NULL) | |
3130 | place += 4; | |
3131 | macro_build (place, counter, (expressionS *) NULL, | |
3132 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", | |
3133 | "d,v,t", AT, AT, breg); | |
3134 | if (place != NULL) | |
3135 | place += 4; | |
3136 | macro_build (place, counter, ep, op, "t,o(b)", treg, | |
3137 | (int) BFD_RELOC_LO16, AT); | |
3138 | ||
3139 | if (mips_opts.noat) | |
3140 | as_warn (_("Macro used $at after \".set noat\"")); | |
3141 | } | |
3142 | } | |
3143 | ||
252b5132 RH |
3144 | /* set_at() |
3145 | * Generates code to set the $at register to true (one) | |
3146 | * if reg is less than the immediate expression. | |
3147 | */ | |
3148 | static void | |
3149 | set_at (counter, reg, unsignedp) | |
3150 | int *counter; | |
3151 | int reg; | |
3152 | int unsignedp; | |
3153 | { | |
3154 | if (imm_expr.X_op == O_constant | |
3155 | && imm_expr.X_add_number >= -0x8000 | |
3156 | && imm_expr.X_add_number < 0x8000) | |
3157 | macro_build ((char *) NULL, counter, &imm_expr, | |
3158 | unsignedp ? "sltiu" : "slti", | |
3159 | "t,r,j", AT, reg, (int) BFD_RELOC_LO16); | |
3160 | else | |
3161 | { | |
4d34fb5f | 3162 | load_register (counter, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 | 3163 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
252b5132 RH |
3164 | unsignedp ? "sltu" : "slt", |
3165 | "d,v,t", AT, reg, AT); | |
3166 | } | |
3167 | } | |
3168 | ||
3169 | /* Warn if an expression is not a constant. */ | |
3170 | ||
3171 | static void | |
3172 | check_absolute_expr (ip, ex) | |
3173 | struct mips_cl_insn *ip; | |
3174 | expressionS *ex; | |
3175 | { | |
3176 | if (ex->X_op == O_big) | |
3177 | as_bad (_("unsupported large constant")); | |
3178 | else if (ex->X_op != O_constant) | |
3179 | as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name); | |
3180 | } | |
3181 | ||
3182 | /* Count the leading zeroes by performing a binary chop. This is a | |
3183 | bulky bit of source, but performance is a LOT better for the | |
3184 | majority of values than a simple loop to count the bits: | |
3185 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
3186 | if ((v) & (1 << (31 - lcnt))) | |
3187 | break; | |
3188 | However it is not code size friendly, and the gain will drop a bit | |
3189 | on certain cached systems. | |
3190 | */ | |
3191 | #define COUNT_TOP_ZEROES(v) \ | |
3192 | (((v) & ~0xffff) == 0 \ | |
3193 | ? ((v) & ~0xff) == 0 \ | |
3194 | ? ((v) & ~0xf) == 0 \ | |
3195 | ? ((v) & ~0x3) == 0 \ | |
3196 | ? ((v) & ~0x1) == 0 \ | |
3197 | ? !(v) \ | |
3198 | ? 32 \ | |
3199 | : 31 \ | |
3200 | : 30 \ | |
3201 | : ((v) & ~0x7) == 0 \ | |
3202 | ? 29 \ | |
3203 | : 28 \ | |
3204 | : ((v) & ~0x3f) == 0 \ | |
3205 | ? ((v) & ~0x1f) == 0 \ | |
3206 | ? 27 \ | |
3207 | : 26 \ | |
3208 | : ((v) & ~0x7f) == 0 \ | |
3209 | ? 25 \ | |
3210 | : 24 \ | |
3211 | : ((v) & ~0xfff) == 0 \ | |
3212 | ? ((v) & ~0x3ff) == 0 \ | |
3213 | ? ((v) & ~0x1ff) == 0 \ | |
3214 | ? 23 \ | |
3215 | : 22 \ | |
3216 | : ((v) & ~0x7ff) == 0 \ | |
3217 | ? 21 \ | |
3218 | : 20 \ | |
3219 | : ((v) & ~0x3fff) == 0 \ | |
3220 | ? ((v) & ~0x1fff) == 0 \ | |
3221 | ? 19 \ | |
3222 | : 18 \ | |
3223 | : ((v) & ~0x7fff) == 0 \ | |
3224 | ? 17 \ | |
3225 | : 16 \ | |
3226 | : ((v) & ~0xffffff) == 0 \ | |
3227 | ? ((v) & ~0xfffff) == 0 \ | |
3228 | ? ((v) & ~0x3ffff) == 0 \ | |
3229 | ? ((v) & ~0x1ffff) == 0 \ | |
3230 | ? 15 \ | |
3231 | : 14 \ | |
3232 | : ((v) & ~0x7ffff) == 0 \ | |
3233 | ? 13 \ | |
3234 | : 12 \ | |
3235 | : ((v) & ~0x3fffff) == 0 \ | |
3236 | ? ((v) & ~0x1fffff) == 0 \ | |
3237 | ? 11 \ | |
3238 | : 10 \ | |
3239 | : ((v) & ~0x7fffff) == 0 \ | |
3240 | ? 9 \ | |
3241 | : 8 \ | |
3242 | : ((v) & ~0xfffffff) == 0 \ | |
3243 | ? ((v) & ~0x3ffffff) == 0 \ | |
3244 | ? ((v) & ~0x1ffffff) == 0 \ | |
3245 | ? 7 \ | |
3246 | : 6 \ | |
3247 | : ((v) & ~0x7ffffff) == 0 \ | |
3248 | ? 5 \ | |
3249 | : 4 \ | |
3250 | : ((v) & ~0x3fffffff) == 0 \ | |
3251 | ? ((v) & ~0x1fffffff) == 0 \ | |
3252 | ? 3 \ | |
3253 | : 2 \ | |
3254 | : ((v) & ~0x7fffffff) == 0 \ | |
3255 | ? 1 \ | |
3256 | : 0) | |
3257 | ||
3258 | /* load_register() | |
3259 | * This routine generates the least number of instructions neccessary to load | |
3260 | * an absolute expression value into a register. | |
3261 | */ | |
3262 | static void | |
3263 | load_register (counter, reg, ep, dbl) | |
3264 | int *counter; | |
3265 | int reg; | |
3266 | expressionS *ep; | |
3267 | int dbl; | |
3268 | { | |
3269 | int freg; | |
3270 | expressionS hi32, lo32; | |
3271 | ||
3272 | if (ep->X_op != O_big) | |
3273 | { | |
3274 | assert (ep->X_op == O_constant); | |
3275 | if (ep->X_add_number < 0x8000 | |
3276 | && (ep->X_add_number >= 0 | |
3277 | || (ep->X_add_number >= -0x8000 | |
3278 | && (! dbl | |
3279 | || ! ep->X_unsigned | |
3280 | || sizeof (ep->X_add_number) > 4)))) | |
3281 | { | |
3282 | /* We can handle 16 bit signed values with an addiu to | |
3283 | $zero. No need to ever use daddiu here, since $zero and | |
3284 | the result are always correct in 32 bit mode. */ | |
3285 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, | |
3286 | (int) BFD_RELOC_LO16); | |
3287 | return; | |
3288 | } | |
3289 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
3290 | { | |
3291 | /* We can handle 16 bit unsigned values with an ori to | |
3292 | $zero. */ | |
3293 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0, | |
3294 | (int) BFD_RELOC_LO16); | |
3295 | return; | |
3296 | } | |
6373ee54 | 3297 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number) |
252b5132 RH |
3298 | && (! dbl |
3299 | || ! ep->X_unsigned | |
3300 | || sizeof (ep->X_add_number) > 4 | |
3301 | || (ep->X_add_number & 0x80000000) == 0)) | |
ca4e0257 | 3302 | || ((HAVE_32BIT_GPRS || ! dbl) |
252b5132 | 3303 | && (ep->X_add_number &~ (offsetT) 0xffffffff) == 0) |
ca4e0257 | 3304 | || (HAVE_32BIT_GPRS |
252b5132 RH |
3305 | && ! dbl |
3306 | && ((ep->X_add_number &~ (offsetT) 0xffffffff) | |
3307 | == ~ (offsetT) 0xffffffff))) | |
3308 | { | |
3309 | /* 32 bit values require an lui. */ | |
3310 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
3311 | (int) BFD_RELOC_HI16); | |
3312 | if ((ep->X_add_number & 0xffff) != 0) | |
3313 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg, | |
3314 | (int) BFD_RELOC_LO16); | |
3315 | return; | |
3316 | } | |
3317 | } | |
3318 | ||
3319 | /* The value is larger than 32 bits. */ | |
3320 | ||
ca4e0257 | 3321 | if (HAVE_32BIT_GPRS) |
252b5132 | 3322 | { |
956cd1d6 TS |
3323 | as_bad (_("Number (0x%lx) larger than 32 bits"), |
3324 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
3325 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, |
3326 | (int) BFD_RELOC_LO16); | |
3327 | return; | |
3328 | } | |
3329 | ||
3330 | if (ep->X_op != O_big) | |
3331 | { | |
3332 | hi32 = *ep; | |
3333 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3334 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3335 | hi32.X_add_number &= 0xffffffff; | |
3336 | lo32 = *ep; | |
3337 | lo32.X_add_number &= 0xffffffff; | |
3338 | } | |
3339 | else | |
3340 | { | |
3341 | assert (ep->X_add_number > 2); | |
3342 | if (ep->X_add_number == 3) | |
3343 | generic_bignum[3] = 0; | |
3344 | else if (ep->X_add_number > 4) | |
3345 | as_bad (_("Number larger than 64 bits")); | |
3346 | lo32.X_op = O_constant; | |
3347 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
3348 | hi32.X_op = O_constant; | |
3349 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
3350 | } | |
3351 | ||
3352 | if (hi32.X_add_number == 0) | |
3353 | freg = 0; | |
3354 | else | |
3355 | { | |
3356 | int shift, bit; | |
3357 | unsigned long hi, lo; | |
3358 | ||
956cd1d6 | 3359 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
3360 | { |
3361 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
3362 | { | |
3363 | macro_build ((char *) NULL, counter, &lo32, "addiu", "t,r,j", | |
252b5132 | 3364 | reg, 0, (int) BFD_RELOC_LO16); |
beae10d5 KH |
3365 | return; |
3366 | } | |
3367 | if (lo32.X_add_number & 0x80000000) | |
3368 | { | |
3369 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
3370 | (int) BFD_RELOC_HI16); | |
252b5132 RH |
3371 | if (lo32.X_add_number & 0xffff) |
3372 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", | |
3373 | reg, reg, (int) BFD_RELOC_LO16); | |
beae10d5 KH |
3374 | return; |
3375 | } | |
3376 | } | |
252b5132 RH |
3377 | |
3378 | /* Check for 16bit shifted constant. We know that hi32 is | |
3379 | non-zero, so start the mask on the first bit of the hi32 | |
3380 | value. */ | |
3381 | shift = 17; | |
3382 | do | |
beae10d5 KH |
3383 | { |
3384 | unsigned long himask, lomask; | |
3385 | ||
3386 | if (shift < 32) | |
3387 | { | |
3388 | himask = 0xffff >> (32 - shift); | |
3389 | lomask = (0xffff << shift) & 0xffffffff; | |
3390 | } | |
3391 | else | |
3392 | { | |
3393 | himask = 0xffff << (shift - 32); | |
3394 | lomask = 0; | |
3395 | } | |
3396 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
3397 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
3398 | { | |
3399 | expressionS tmp; | |
3400 | ||
3401 | tmp.X_op = O_constant; | |
3402 | if (shift < 32) | |
3403 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
3404 | | (lo32.X_add_number >> shift)); | |
3405 | else | |
3406 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
3407 | macro_build ((char *) NULL, counter, &tmp, | |
3408 | "ori", "t,r,i", reg, 0, | |
3409 | (int) BFD_RELOC_LO16); | |
2396cfb9 | 3410 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
beae10d5 KH |
3411 | (shift >= 32) ? "dsll32" : "dsll", |
3412 | "d,w,<", reg, reg, | |
3413 | (shift >= 32) ? shift - 32 : shift); | |
3414 | return; | |
3415 | } | |
f9419b05 | 3416 | ++shift; |
beae10d5 KH |
3417 | } |
3418 | while (shift <= (64 - 16)); | |
252b5132 RH |
3419 | |
3420 | /* Find the bit number of the lowest one bit, and store the | |
3421 | shifted value in hi/lo. */ | |
3422 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
3423 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
3424 | if (lo != 0) | |
3425 | { | |
3426 | bit = 0; | |
3427 | while ((lo & 1) == 0) | |
3428 | { | |
3429 | lo >>= 1; | |
3430 | ++bit; | |
3431 | } | |
3432 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
3433 | hi >>= bit; | |
3434 | } | |
3435 | else | |
3436 | { | |
3437 | bit = 32; | |
3438 | while ((hi & 1) == 0) | |
3439 | { | |
3440 | hi >>= 1; | |
3441 | ++bit; | |
3442 | } | |
3443 | lo = hi; | |
3444 | hi = 0; | |
3445 | } | |
3446 | ||
3447 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
3448 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
3449 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
3450 | { |
3451 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 3452 | if (shift != 0) |
beae10d5 | 3453 | { |
252b5132 RH |
3454 | expressionS tmp; |
3455 | ||
3456 | /* This instruction will set the register to be all | |
3457 | ones. */ | |
beae10d5 KH |
3458 | tmp.X_op = O_constant; |
3459 | tmp.X_add_number = (offsetT) -1; | |
3460 | macro_build ((char *) NULL, counter, &tmp, "addiu", "t,r,j", | |
252b5132 | 3461 | reg, 0, (int) BFD_RELOC_LO16); |
beae10d5 KH |
3462 | if (bit != 0) |
3463 | { | |
3464 | bit += shift; | |
2396cfb9 | 3465 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
beae10d5 KH |
3466 | (bit >= 32) ? "dsll32" : "dsll", |
3467 | "d,w,<", reg, reg, | |
3468 | (bit >= 32) ? bit - 32 : bit); | |
3469 | } | |
2396cfb9 | 3470 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
252b5132 | 3471 | (shift >= 32) ? "dsrl32" : "dsrl", |
beae10d5 | 3472 | "d,w,<", reg, reg, |
252b5132 | 3473 | (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
3474 | return; |
3475 | } | |
3476 | } | |
252b5132 RH |
3477 | |
3478 | /* Sign extend hi32 before calling load_register, because we can | |
3479 | generally get better code when we load a sign extended value. */ | |
3480 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 3481 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
252b5132 RH |
3482 | load_register (counter, reg, &hi32, 0); |
3483 | freg = reg; | |
3484 | } | |
3485 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
3486 | { | |
3487 | if (freg != 0) | |
3488 | { | |
2396cfb9 TS |
3489 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
3490 | "dsll32", "d,w,<", reg, freg, 0); | |
252b5132 RH |
3491 | freg = reg; |
3492 | } | |
3493 | } | |
3494 | else | |
3495 | { | |
3496 | expressionS mid16; | |
3497 | ||
956cd1d6 | 3498 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 3499 | { |
252b5132 RH |
3500 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, |
3501 | (int) BFD_RELOC_HI16); | |
956cd1d6 TS |
3502 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
3503 | "dsrl32", "d,w,<", reg, reg, 0); | |
beae10d5 KH |
3504 | return; |
3505 | } | |
252b5132 RH |
3506 | |
3507 | if (freg != 0) | |
3508 | { | |
956cd1d6 TS |
3509 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "dsll", |
3510 | "d,w,<", reg, freg, 16); | |
252b5132 RH |
3511 | freg = reg; |
3512 | } | |
3513 | mid16 = lo32; | |
3514 | mid16.X_add_number >>= 16; | |
3515 | macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg, | |
3516 | freg, (int) BFD_RELOC_LO16); | |
956cd1d6 TS |
3517 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "dsll", |
3518 | "d,w,<", reg, reg, 16); | |
252b5132 RH |
3519 | freg = reg; |
3520 | } | |
3521 | if ((lo32.X_add_number & 0xffff) != 0) | |
3522 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, freg, | |
3523 | (int) BFD_RELOC_LO16); | |
3524 | } | |
3525 | ||
3526 | /* Load an address into a register. */ | |
3527 | ||
3528 | static void | |
c9914766 | 3529 | load_address (counter, reg, ep, used_at) |
252b5132 RH |
3530 | int *counter; |
3531 | int reg; | |
3532 | expressionS *ep; | |
d6bc6245 | 3533 | int *used_at; |
252b5132 | 3534 | { |
f9419b05 | 3535 | char *p = NULL; |
252b5132 RH |
3536 | |
3537 | if (ep->X_op != O_constant | |
3538 | && ep->X_op != O_symbol) | |
3539 | { | |
3540 | as_bad (_("expression too complex")); | |
3541 | ep->X_op = O_constant; | |
3542 | } | |
3543 | ||
3544 | if (ep->X_op == O_constant) | |
3545 | { | |
c9914766 | 3546 | load_register (counter, reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
3547 | return; |
3548 | } | |
3549 | ||
3550 | if (mips_pic == NO_PIC) | |
3551 | { | |
3552 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 3553 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
3554 | Otherwise we want |
3555 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
3556 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 3557 | If we have an addend, we always use the latter form. |
76b3015f | 3558 | |
d6bc6245 TS |
3559 | With 64bit address space and a usable $at we want |
3560 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3561 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
3562 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3563 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
3564 | dsll32 $reg,0 | |
3a482fd5 | 3565 | daddu $reg,$reg,$at |
76b3015f | 3566 | |
d6bc6245 TS |
3567 | If $at is already in use, we use an path which is suboptimal |
3568 | on superscalar processors. | |
3569 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3570 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3571 | dsll $reg,16 | |
3572 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
3573 | dsll $reg,16 | |
3574 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
3575 | */ | |
c9914766 | 3576 | if (HAVE_64BIT_ADDRESSES) |
d6bc6245 | 3577 | { |
d6bc6245 TS |
3578 | /* We don't do GP optimization for now because RELAX_ENCODE can't |
3579 | hold the data for such large chunks. */ | |
3580 | ||
460597ba | 3581 | if (*used_at == 0 && ! mips_opts.noat) |
d6bc6245 TS |
3582 | { |
3583 | macro_build (p, counter, ep, "lui", "t,u", | |
3584 | reg, (int) BFD_RELOC_MIPS_HIGHEST); | |
3585 | macro_build (p, counter, ep, "lui", "t,u", | |
3586 | AT, (int) BFD_RELOC_HI16_S); | |
3587 | macro_build (p, counter, ep, "daddiu", "t,r,j", | |
3588 | reg, reg, (int) BFD_RELOC_MIPS_HIGHER); | |
3589 | macro_build (p, counter, ep, "daddiu", "t,r,j", | |
3590 | AT, AT, (int) BFD_RELOC_LO16); | |
2396cfb9 TS |
3591 | macro_build (p, counter, (expressionS *) NULL, "dsll32", |
3592 | "d,w,<", reg, reg, 0); | |
3a482fd5 | 3593 | macro_build (p, counter, (expressionS *) NULL, "daddu", |
2396cfb9 | 3594 | "d,v,t", reg, reg, AT); |
d6bc6245 TS |
3595 | *used_at = 1; |
3596 | } | |
3597 | else | |
3598 | { | |
3599 | macro_build (p, counter, ep, "lui", "t,u", | |
3600 | reg, (int) BFD_RELOC_MIPS_HIGHEST); | |
3601 | macro_build (p, counter, ep, "daddiu", "t,r,j", | |
3602 | reg, reg, (int) BFD_RELOC_MIPS_HIGHER); | |
2396cfb9 TS |
3603 | macro_build (p, counter, (expressionS *) NULL, "dsll", |
3604 | "d,w,<", reg, reg, 16); | |
d6bc6245 TS |
3605 | macro_build (p, counter, ep, "daddiu", "t,r,j", |
3606 | reg, reg, (int) BFD_RELOC_HI16_S); | |
2396cfb9 TS |
3607 | macro_build (p, counter, (expressionS *) NULL, "dsll", |
3608 | "d,w,<", reg, reg, 16); | |
d6bc6245 TS |
3609 | macro_build (p, counter, ep, "daddiu", "t,r,j", |
3610 | reg, reg, (int) BFD_RELOC_LO16); | |
3611 | } | |
3612 | } | |
252b5132 RH |
3613 | else |
3614 | { | |
d6bc6245 TS |
3615 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
3616 | && ! nopic_need_relax (ep->X_add_symbol, 1)) | |
3617 | { | |
3618 | frag_grow (20); | |
3619 | macro_build ((char *) NULL, counter, ep, | |
c9914766 TS |
3620 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j", |
3621 | reg, mips_gp_register, (int) BFD_RELOC_GPREL16); | |
d6bc6245 TS |
3622 | p = frag_var (rs_machine_dependent, 8, 0, |
3623 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
3624 | mips_opts.warn_about_macros), | |
956cd1d6 | 3625 | ep->X_add_symbol, 0, NULL); |
d6bc6245 TS |
3626 | } |
3627 | macro_build_lui (p, counter, ep, reg); | |
3628 | if (p != NULL) | |
3629 | p += 4; | |
c9914766 TS |
3630 | macro_build (p, counter, ep, |
3631 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", | |
d6bc6245 TS |
3632 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3633 | } | |
252b5132 RH |
3634 | } |
3635 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
3636 | { | |
3637 | expressionS ex; | |
3638 | ||
3639 | /* If this is a reference to an external symbol, we want | |
3640 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3641 | Otherwise we want | |
3642 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3643 | nop | |
3644 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
ed6fb7bd SC |
3645 | If we have NewABI, we want |
3646 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
252b5132 RH |
3647 | If there is a constant, it must be added in after. */ |
3648 | ex.X_add_number = ep->X_add_number; | |
3649 | ep->X_add_number = 0; | |
3650 | frag_grow (20); | |
ed6fb7bd SC |
3651 | if (HAVE_NEWABI) |
3652 | { | |
3653 | macro_build ((char *) NULL, counter, ep, | |
3654 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", reg, | |
3655 | (int) BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
3656 | } | |
3657 | else | |
3658 | { | |
3659 | macro_build ((char *) NULL, counter, ep, | |
3660 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", | |
3661 | reg, (int) BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
3662 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", ""); | |
3663 | p = frag_var (rs_machine_dependent, 4, 0, | |
3664 | RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts.warn_about_macros), | |
3665 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); | |
3666 | macro_build (p, counter, ep, | |
3667 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", | |
3668 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
3669 | } | |
3670 | ||
252b5132 RH |
3671 | if (ex.X_add_number != 0) |
3672 | { | |
3673 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3674 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3675 | ex.X_op = O_constant; | |
3676 | macro_build ((char *) NULL, counter, &ex, | |
ca4e0257 | 3677 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
3678 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3679 | } | |
3680 | } | |
3681 | else if (mips_pic == SVR4_PIC) | |
3682 | { | |
3683 | expressionS ex; | |
3684 | int off; | |
3685 | ||
3686 | /* This is the large GOT case. If this is a reference to an | |
3687 | external symbol, we want | |
3688 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3689 | addu $reg,$reg,$gp | |
3690 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
3691 | Otherwise, for a reference to a local symbol, we want | |
3692 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3693 | nop | |
3694 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
438c16b8 TS |
3695 | If we have NewABI, we want |
3696 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
3697 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
252b5132 RH |
3698 | If there is a constant, it must be added in after. */ |
3699 | ex.X_add_number = ep->X_add_number; | |
3700 | ep->X_add_number = 0; | |
438c16b8 TS |
3701 | if (HAVE_NEWABI) |
3702 | { | |
3703 | macro_build ((char *) NULL, counter, ep, | |
3704 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", reg, | |
3705 | (int) BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
3706 | macro_build (p, counter, ep, | |
3707 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j", | |
3708 | reg, reg, (int) BFD_RELOC_MIPS_GOT_OFST); | |
3709 | } | |
252b5132 | 3710 | else |
438c16b8 TS |
3711 | { |
3712 | if (reg_needs_delay (mips_gp_register)) | |
3713 | off = 4; | |
3714 | else | |
3715 | off = 0; | |
3716 | frag_grow (32); | |
3717 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
3718 | (int) BFD_RELOC_MIPS_GOT_HI16); | |
3719 | macro_build ((char *) NULL, counter, (expressionS *) NULL, | |
3720 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", "d,v,t", reg, | |
3721 | reg, mips_gp_register); | |
3722 | macro_build ((char *) NULL, counter, ep, | |
3723 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", | |
3724 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg); | |
3725 | p = frag_var (rs_machine_dependent, 12 + off, 0, | |
3726 | RELAX_ENCODE (12, 12 + off, off, 8 + off, 0, | |
3727 | mips_opts.warn_about_macros), | |
3728 | ep->X_add_symbol, 0, NULL); | |
3729 | if (off > 0) | |
3730 | { | |
3731 | /* We need a nop before loading from $gp. This special | |
3732 | check is required because the lui which starts the main | |
3733 | instruction stream does not refer to $gp, and so will not | |
3734 | insert the nop which may be required. */ | |
3735 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
3736 | p += 4; | |
3737 | } | |
3738 | macro_build (p, counter, ep, | |
3739 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", reg, | |
3740 | (int) BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
3741 | p += 4; | |
252b5132 RH |
3742 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); |
3743 | p += 4; | |
438c16b8 TS |
3744 | macro_build (p, counter, ep, |
3745 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", | |
3746 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
252b5132 | 3747 | } |
438c16b8 | 3748 | |
252b5132 RH |
3749 | if (ex.X_add_number != 0) |
3750 | { | |
3751 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3752 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3753 | ex.X_op = O_constant; | |
f7ea7ef2 TS |
3754 | macro_build ((char *) NULL, counter, &ex, |
3755 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", | |
252b5132 RH |
3756 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3757 | } | |
3758 | } | |
3759 | else if (mips_pic == EMBEDDED_PIC) | |
3760 | { | |
3761 | /* We always do | |
cdf6fd85 | 3762 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
c9914766 TS |
3763 | */ |
3764 | macro_build ((char *) NULL, counter, ep, | |
3765 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", | |
3766 | "t,r,j", reg, mips_gp_register, (int) BFD_RELOC_GPREL16); | |
252b5132 RH |
3767 | } |
3768 | else | |
3769 | abort (); | |
3770 | } | |
3771 | ||
ea1fb5dc RS |
3772 | /* Move the contents of register SOURCE into register DEST. */ |
3773 | ||
3774 | static void | |
3775 | move_register (counter, dest, source) | |
3776 | int *counter; | |
3777 | int dest; | |
3778 | int source; | |
3779 | { | |
3780 | macro_build ((char *) NULL, counter, (expressionS *) NULL, | |
3781 | HAVE_32BIT_GPRS ? "addu" : "daddu", | |
3782 | "d,v,t", dest, source, 0); | |
3783 | } | |
3784 | ||
252b5132 RH |
3785 | /* |
3786 | * Build macros | |
3787 | * This routine implements the seemingly endless macro or synthesized | |
3788 | * instructions and addressing modes in the mips assembly language. Many | |
3789 | * of these macros are simple and are similar to each other. These could | |
3790 | * probably be handled by some kind of table or grammer aproach instead of | |
3791 | * this verbose method. Others are not simple macros but are more like | |
3792 | * optimizing code generation. | |
3793 | * One interesting optimization is when several store macros appear | |
3794 | * consecutivly that would load AT with the upper half of the same address. | |
3795 | * The ensuing load upper instructions are ommited. This implies some kind | |
3796 | * of global optimization. We currently only optimize within a single macro. | |
3797 | * For many of the load and store macros if the address is specified as a | |
3798 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
3799 | * first load register 'at' with zero and use it as the base register. The | |
3800 | * mips assembler simply uses register $zero. Just one tiny optimization | |
3801 | * we're missing. | |
3802 | */ | |
3803 | static void | |
3804 | macro (ip) | |
3805 | struct mips_cl_insn *ip; | |
3806 | { | |
3807 | register int treg, sreg, dreg, breg; | |
3808 | int tempreg; | |
3809 | int mask; | |
3810 | int icnt = 0; | |
43841e91 | 3811 | int used_at = 0; |
252b5132 RH |
3812 | expressionS expr1; |
3813 | const char *s; | |
3814 | const char *s2; | |
3815 | const char *fmt; | |
3816 | int likely = 0; | |
3817 | int dbl = 0; | |
3818 | int coproc = 0; | |
3819 | int lr = 0; | |
3820 | int imm = 0; | |
3821 | offsetT maxnum; | |
3822 | int off; | |
3823 | bfd_reloc_code_real_type r; | |
252b5132 RH |
3824 | int hold_mips_optimize; |
3825 | ||
3826 | assert (! mips_opts.mips16); | |
3827 | ||
3828 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
3829 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
3830 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
3831 | mask = ip->insn_mo->mask; | |
3832 | ||
3833 | expr1.X_op = O_constant; | |
3834 | expr1.X_op_symbol = NULL; | |
3835 | expr1.X_add_symbol = NULL; | |
3836 | expr1.X_add_number = 1; | |
3837 | ||
3838 | switch (mask) | |
3839 | { | |
3840 | case M_DABS: | |
3841 | dbl = 1; | |
3842 | case M_ABS: | |
3843 | /* bgez $a0,.+12 | |
3844 | move v0,$a0 | |
3845 | sub v0,$zero,$a0 | |
3846 | */ | |
3847 | ||
3848 | mips_emit_delays (true); | |
3849 | ++mips_opts.noreorder; | |
3850 | mips_any_noreorder = 1; | |
3851 | ||
3852 | expr1.X_add_number = 8; | |
3853 | macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg); | |
3854 | if (dreg == sreg) | |
2396cfb9 TS |
3855 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "", |
3856 | 0); | |
252b5132 | 3857 | else |
ea1fb5dc | 3858 | move_register (&icnt, dreg, sreg); |
2396cfb9 | 3859 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 3860 | dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
3861 | |
3862 | --mips_opts.noreorder; | |
3863 | return; | |
3864 | ||
3865 | case M_ADD_I: | |
3866 | s = "addi"; | |
3867 | s2 = "add"; | |
3868 | goto do_addi; | |
3869 | case M_ADDU_I: | |
3870 | s = "addiu"; | |
3871 | s2 = "addu"; | |
3872 | goto do_addi; | |
3873 | case M_DADD_I: | |
3874 | dbl = 1; | |
3875 | s = "daddi"; | |
3876 | s2 = "dadd"; | |
3877 | goto do_addi; | |
3878 | case M_DADDU_I: | |
3879 | dbl = 1; | |
3880 | s = "daddiu"; | |
3881 | s2 = "daddu"; | |
3882 | do_addi: | |
3883 | if (imm_expr.X_op == O_constant | |
3884 | && imm_expr.X_add_number >= -0x8000 | |
3885 | && imm_expr.X_add_number < 0x8000) | |
3886 | { | |
3887 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg, | |
3888 | (int) BFD_RELOC_LO16); | |
3889 | return; | |
3890 | } | |
3891 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 TS |
3892 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d,v,t", |
3893 | treg, sreg, AT); | |
252b5132 RH |
3894 | break; |
3895 | ||
3896 | case M_AND_I: | |
3897 | s = "andi"; | |
3898 | s2 = "and"; | |
3899 | goto do_bit; | |
3900 | case M_OR_I: | |
3901 | s = "ori"; | |
3902 | s2 = "or"; | |
3903 | goto do_bit; | |
3904 | case M_NOR_I: | |
3905 | s = ""; | |
3906 | s2 = "nor"; | |
3907 | goto do_bit; | |
3908 | case M_XOR_I: | |
3909 | s = "xori"; | |
3910 | s2 = "xor"; | |
3911 | do_bit: | |
3912 | if (imm_expr.X_op == O_constant | |
3913 | && imm_expr.X_add_number >= 0 | |
3914 | && imm_expr.X_add_number < 0x10000) | |
3915 | { | |
3916 | if (mask != M_NOR_I) | |
3917 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg, | |
3918 | sreg, (int) BFD_RELOC_LO16); | |
3919 | else | |
3920 | { | |
3921 | macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i", | |
3922 | treg, sreg, (int) BFD_RELOC_LO16); | |
2396cfb9 TS |
3923 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nor", |
3924 | "d,v,t", treg, treg, 0); | |
252b5132 RH |
3925 | } |
3926 | return; | |
3927 | } | |
3928 | ||
d6bc6245 | 3929 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
3930 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d,v,t", |
3931 | treg, sreg, AT); | |
252b5132 RH |
3932 | break; |
3933 | ||
3934 | case M_BEQ_I: | |
3935 | s = "beq"; | |
3936 | goto beq_i; | |
3937 | case M_BEQL_I: | |
3938 | s = "beql"; | |
3939 | likely = 1; | |
3940 | goto beq_i; | |
3941 | case M_BNE_I: | |
3942 | s = "bne"; | |
3943 | goto beq_i; | |
3944 | case M_BNEL_I: | |
3945 | s = "bnel"; | |
3946 | likely = 1; | |
3947 | beq_i: | |
3948 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
3949 | { | |
3950 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, | |
3951 | 0); | |
3952 | return; | |
3953 | } | |
4d34fb5f | 3954 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
252b5132 RH |
3955 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT); |
3956 | break; | |
3957 | ||
3958 | case M_BGEL: | |
3959 | likely = 1; | |
3960 | case M_BGE: | |
3961 | if (treg == 0) | |
3962 | { | |
3963 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
2396cfb9 | 3964 | likely ? "bgezl" : "bgez", "s,p", sreg); |
252b5132 RH |
3965 | return; |
3966 | } | |
3967 | if (sreg == 0) | |
3968 | { | |
3969 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
2396cfb9 | 3970 | likely ? "blezl" : "blez", "s,p", treg); |
252b5132 RH |
3971 | return; |
3972 | } | |
2396cfb9 TS |
3973 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t", |
3974 | AT, sreg, treg); | |
252b5132 | 3975 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 3976 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
3977 | break; |
3978 | ||
3979 | case M_BGTL_I: | |
3980 | likely = 1; | |
3981 | case M_BGT_I: | |
3982 | /* check for > max integer */ | |
3983 | maxnum = 0x7fffffff; | |
ca4e0257 | 3984 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
3985 | { |
3986 | maxnum <<= 16; | |
3987 | maxnum |= 0xffff; | |
3988 | maxnum <<= 16; | |
3989 | maxnum |= 0xffff; | |
3990 | } | |
3991 | if (imm_expr.X_op == O_constant | |
3992 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 3993 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
3994 | { |
3995 | do_false: | |
3996 | /* result is always false */ | |
3997 | if (! likely) | |
3998 | { | |
39c0a331 L |
3999 | if (warn_nops) |
4000 | as_warn (_("Branch %s is always false (nop)"), | |
4001 | ip->insn_mo->name); | |
2396cfb9 TS |
4002 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", |
4003 | "", 0); | |
252b5132 RH |
4004 | } |
4005 | else | |
4006 | { | |
39c0a331 L |
4007 | if (warn_nops) |
4008 | as_warn (_("Branch likely %s is always false"), | |
4009 | ip->insn_mo->name); | |
252b5132 RH |
4010 | macro_build ((char *) NULL, &icnt, &offset_expr, "bnel", |
4011 | "s,t,p", 0, 0); | |
4012 | } | |
4013 | return; | |
4014 | } | |
4015 | if (imm_expr.X_op != O_constant) | |
4016 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4017 | ++imm_expr.X_add_number; |
252b5132 RH |
4018 | /* FALLTHROUGH */ |
4019 | case M_BGE_I: | |
4020 | case M_BGEL_I: | |
4021 | if (mask == M_BGEL_I) | |
4022 | likely = 1; | |
4023 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4024 | { | |
4025 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4026 | likely ? "bgezl" : "bgez", "s,p", sreg); |
252b5132 RH |
4027 | return; |
4028 | } | |
4029 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4030 | { | |
4031 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4032 | likely ? "bgtzl" : "bgtz", "s,p", sreg); |
252b5132 RH |
4033 | return; |
4034 | } | |
4035 | maxnum = 0x7fffffff; | |
ca4e0257 | 4036 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4037 | { |
4038 | maxnum <<= 16; | |
4039 | maxnum |= 0xffff; | |
4040 | maxnum <<= 16; | |
4041 | maxnum |= 0xffff; | |
4042 | } | |
4043 | maxnum = - maxnum - 1; | |
4044 | if (imm_expr.X_op == O_constant | |
4045 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 4046 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4047 | { |
4048 | do_true: | |
4049 | /* result is always true */ | |
4050 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
4051 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); | |
4052 | return; | |
4053 | } | |
4054 | set_at (&icnt, sreg, 0); | |
4055 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4056 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4057 | break; |
4058 | ||
4059 | case M_BGEUL: | |
4060 | likely = 1; | |
4061 | case M_BGEU: | |
4062 | if (treg == 0) | |
4063 | goto do_true; | |
4064 | if (sreg == 0) | |
4065 | { | |
4066 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4067 | likely ? "beql" : "beq", "s,t,p", 0, treg); |
252b5132 RH |
4068 | return; |
4069 | } | |
2396cfb9 TS |
4070 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
4071 | "d,v,t", AT, sreg, treg); | |
252b5132 | 4072 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4073 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4074 | break; |
4075 | ||
4076 | case M_BGTUL_I: | |
4077 | likely = 1; | |
4078 | case M_BGTU_I: | |
4079 | if (sreg == 0 | |
ca4e0257 | 4080 | || (HAVE_32BIT_GPRS |
252b5132 | 4081 | && imm_expr.X_op == O_constant |
956cd1d6 | 4082 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4083 | goto do_false; |
4084 | if (imm_expr.X_op != O_constant) | |
4085 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4086 | ++imm_expr.X_add_number; |
252b5132 RH |
4087 | /* FALLTHROUGH */ |
4088 | case M_BGEU_I: | |
4089 | case M_BGEUL_I: | |
4090 | if (mask == M_BGEUL_I) | |
4091 | likely = 1; | |
4092 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4093 | goto do_true; | |
4094 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4095 | { | |
4096 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4097 | likely ? "bnel" : "bne", "s,t,p", sreg, 0); |
252b5132 RH |
4098 | return; |
4099 | } | |
4100 | set_at (&icnt, sreg, 1); | |
4101 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4102 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4103 | break; |
4104 | ||
4105 | case M_BGTL: | |
4106 | likely = 1; | |
4107 | case M_BGT: | |
4108 | if (treg == 0) | |
4109 | { | |
4110 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4111 | likely ? "bgtzl" : "bgtz", "s,p", sreg); |
252b5132 RH |
4112 | return; |
4113 | } | |
4114 | if (sreg == 0) | |
4115 | { | |
4116 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4117 | likely ? "bltzl" : "bltz", "s,p", treg); |
252b5132 RH |
4118 | return; |
4119 | } | |
2396cfb9 TS |
4120 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t", |
4121 | AT, treg, sreg); | |
252b5132 | 4122 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4123 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4124 | break; |
4125 | ||
4126 | case M_BGTUL: | |
4127 | likely = 1; | |
4128 | case M_BGTU: | |
4129 | if (treg == 0) | |
4130 | { | |
4131 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4132 | likely ? "bnel" : "bne", "s,t,p", sreg, 0); |
252b5132 RH |
4133 | return; |
4134 | } | |
4135 | if (sreg == 0) | |
4136 | goto do_false; | |
2396cfb9 TS |
4137 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
4138 | "d,v,t", AT, treg, sreg); | |
252b5132 | 4139 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4140 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4141 | break; |
4142 | ||
4143 | case M_BLEL: | |
4144 | likely = 1; | |
4145 | case M_BLE: | |
4146 | if (treg == 0) | |
4147 | { | |
4148 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4149 | likely ? "blezl" : "blez", "s,p", sreg); |
252b5132 RH |
4150 | return; |
4151 | } | |
4152 | if (sreg == 0) | |
4153 | { | |
4154 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4155 | likely ? "bgezl" : "bgez", "s,p", treg); |
252b5132 RH |
4156 | return; |
4157 | } | |
2396cfb9 TS |
4158 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t", |
4159 | AT, treg, sreg); | |
252b5132 | 4160 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4161 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4162 | break; |
4163 | ||
4164 | case M_BLEL_I: | |
4165 | likely = 1; | |
4166 | case M_BLE_I: | |
4167 | maxnum = 0x7fffffff; | |
ca4e0257 | 4168 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4169 | { |
4170 | maxnum <<= 16; | |
4171 | maxnum |= 0xffff; | |
4172 | maxnum <<= 16; | |
4173 | maxnum |= 0xffff; | |
4174 | } | |
4175 | if (imm_expr.X_op == O_constant | |
4176 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4177 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4178 | goto do_true; |
4179 | if (imm_expr.X_op != O_constant) | |
4180 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4181 | ++imm_expr.X_add_number; |
252b5132 RH |
4182 | /* FALLTHROUGH */ |
4183 | case M_BLT_I: | |
4184 | case M_BLTL_I: | |
4185 | if (mask == M_BLTL_I) | |
4186 | likely = 1; | |
4187 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4188 | { | |
4189 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4190 | likely ? "bltzl" : "bltz", "s,p", sreg); |
252b5132 RH |
4191 | return; |
4192 | } | |
4193 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4194 | { | |
4195 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4196 | likely ? "blezl" : "blez", "s,p", sreg); |
252b5132 RH |
4197 | return; |
4198 | } | |
4199 | set_at (&icnt, sreg, 0); | |
4200 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4201 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4202 | break; |
4203 | ||
4204 | case M_BLEUL: | |
4205 | likely = 1; | |
4206 | case M_BLEU: | |
4207 | if (treg == 0) | |
4208 | { | |
4209 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4210 | likely ? "beql" : "beq", "s,t,p", sreg, 0); |
252b5132 RH |
4211 | return; |
4212 | } | |
4213 | if (sreg == 0) | |
4214 | goto do_true; | |
2396cfb9 TS |
4215 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
4216 | "d,v,t", AT, treg, sreg); | |
252b5132 | 4217 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4218 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
252b5132 RH |
4219 | break; |
4220 | ||
4221 | case M_BLEUL_I: | |
4222 | likely = 1; | |
4223 | case M_BLEU_I: | |
4224 | if (sreg == 0 | |
ca4e0257 | 4225 | || (HAVE_32BIT_GPRS |
252b5132 | 4226 | && imm_expr.X_op == O_constant |
956cd1d6 | 4227 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4228 | goto do_true; |
4229 | if (imm_expr.X_op != O_constant) | |
4230 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4231 | ++imm_expr.X_add_number; |
252b5132 RH |
4232 | /* FALLTHROUGH */ |
4233 | case M_BLTU_I: | |
4234 | case M_BLTUL_I: | |
4235 | if (mask == M_BLTUL_I) | |
4236 | likely = 1; | |
4237 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4238 | goto do_false; | |
4239 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4240 | { | |
4241 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4242 | likely ? "beql" : "beq", | |
4243 | "s,t,p", sreg, 0); | |
4244 | return; | |
4245 | } | |
4246 | set_at (&icnt, sreg, 1); | |
4247 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4248 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4249 | break; |
4250 | ||
4251 | case M_BLTL: | |
4252 | likely = 1; | |
4253 | case M_BLT: | |
4254 | if (treg == 0) | |
4255 | { | |
4256 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4257 | likely ? "bltzl" : "bltz", "s,p", sreg); |
252b5132 RH |
4258 | return; |
4259 | } | |
4260 | if (sreg == 0) | |
4261 | { | |
4262 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4263 | likely ? "bgtzl" : "bgtz", "s,p", treg); |
252b5132 RH |
4264 | return; |
4265 | } | |
2396cfb9 TS |
4266 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t", |
4267 | AT, sreg, treg); | |
252b5132 | 4268 | macro_build ((char *) NULL, &icnt, &offset_expr, |
9a41af64 | 4269 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4270 | break; |
4271 | ||
4272 | case M_BLTUL: | |
4273 | likely = 1; | |
4274 | case M_BLTU: | |
4275 | if (treg == 0) | |
4276 | goto do_false; | |
4277 | if (sreg == 0) | |
4278 | { | |
4279 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4280 | likely ? "bnel" : "bne", "s,t,p", 0, treg); |
252b5132 RH |
4281 | return; |
4282 | } | |
2396cfb9 TS |
4283 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
4284 | "d,v,t", AT, sreg, | |
252b5132 RH |
4285 | treg); |
4286 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
9a41af64 | 4287 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
252b5132 RH |
4288 | break; |
4289 | ||
4290 | case M_DDIV_3: | |
4291 | dbl = 1; | |
4292 | case M_DIV_3: | |
4293 | s = "mflo"; | |
4294 | goto do_div3; | |
4295 | case M_DREM_3: | |
4296 | dbl = 1; | |
4297 | case M_REM_3: | |
4298 | s = "mfhi"; | |
4299 | do_div3: | |
4300 | if (treg == 0) | |
4301 | { | |
4302 | as_warn (_("Divide by zero.")); | |
4303 | if (mips_trap) | |
2396cfb9 | 4304 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq", |
9bd7d936 | 4305 | "s,t,q", 0, 0, 7); |
252b5132 | 4306 | else |
2396cfb9 TS |
4307 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
4308 | "c", 7); | |
252b5132 RH |
4309 | return; |
4310 | } | |
4311 | ||
4312 | mips_emit_delays (true); | |
4313 | ++mips_opts.noreorder; | |
4314 | mips_any_noreorder = 1; | |
4315 | if (mips_trap) | |
4316 | { | |
2396cfb9 | 4317 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq", |
9bd7d936 | 4318 | "s,t,q", treg, 0, 7); |
2396cfb9 | 4319 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 4320 | dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
252b5132 RH |
4321 | } |
4322 | else | |
4323 | { | |
4324 | expr1.X_add_number = 8; | |
4325 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
2396cfb9 | 4326 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 4327 | dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
2396cfb9 TS |
4328 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
4329 | "c", 7); | |
252b5132 RH |
4330 | } |
4331 | expr1.X_add_number = -1; | |
4332 | macro_build ((char *) NULL, &icnt, &expr1, | |
4333 | dbl ? "daddiu" : "addiu", | |
4334 | "t,r,j", AT, 0, (int) BFD_RELOC_LO16); | |
4335 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); | |
4336 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT); | |
4337 | if (dbl) | |
4338 | { | |
4339 | expr1.X_add_number = 1; | |
4340 | macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0, | |
4341 | (int) BFD_RELOC_LO16); | |
2396cfb9 TS |
4342 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsll32", |
4343 | "d,w,<", AT, AT, 31); | |
252b5132 RH |
4344 | } |
4345 | else | |
4346 | { | |
4347 | expr1.X_add_number = 0x80000000; | |
4348 | macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT, | |
4349 | (int) BFD_RELOC_HI16); | |
4350 | } | |
4351 | if (mips_trap) | |
4352 | { | |
2396cfb9 | 4353 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq", |
9bd7d936 | 4354 | "s,t,q", sreg, AT, 6); |
252b5132 RH |
4355 | /* We want to close the noreorder block as soon as possible, so |
4356 | that later insns are available for delay slot filling. */ | |
4357 | --mips_opts.noreorder; | |
4358 | } | |
4359 | else | |
4360 | { | |
4361 | expr1.X_add_number = 8; | |
4362 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT); | |
2396cfb9 TS |
4363 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "", |
4364 | 0); | |
252b5132 RH |
4365 | |
4366 | /* We want to close the noreorder block as soon as possible, so | |
4367 | that later insns are available for delay slot filling. */ | |
4368 | --mips_opts.noreorder; | |
4369 | ||
2396cfb9 TS |
4370 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
4371 | "c", 6); | |
252b5132 | 4372 | } |
2396cfb9 | 4373 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d", dreg); |
252b5132 RH |
4374 | break; |
4375 | ||
4376 | case M_DIV_3I: | |
4377 | s = "div"; | |
4378 | s2 = "mflo"; | |
4379 | goto do_divi; | |
4380 | case M_DIVU_3I: | |
4381 | s = "divu"; | |
4382 | s2 = "mflo"; | |
4383 | goto do_divi; | |
4384 | case M_REM_3I: | |
4385 | s = "div"; | |
4386 | s2 = "mfhi"; | |
4387 | goto do_divi; | |
4388 | case M_REMU_3I: | |
4389 | s = "divu"; | |
4390 | s2 = "mfhi"; | |
4391 | goto do_divi; | |
4392 | case M_DDIV_3I: | |
4393 | dbl = 1; | |
4394 | s = "ddiv"; | |
4395 | s2 = "mflo"; | |
4396 | goto do_divi; | |
4397 | case M_DDIVU_3I: | |
4398 | dbl = 1; | |
4399 | s = "ddivu"; | |
4400 | s2 = "mflo"; | |
4401 | goto do_divi; | |
4402 | case M_DREM_3I: | |
4403 | dbl = 1; | |
4404 | s = "ddiv"; | |
4405 | s2 = "mfhi"; | |
4406 | goto do_divi; | |
4407 | case M_DREMU_3I: | |
4408 | dbl = 1; | |
4409 | s = "ddivu"; | |
4410 | s2 = "mfhi"; | |
4411 | do_divi: | |
4412 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4413 | { | |
4414 | as_warn (_("Divide by zero.")); | |
4415 | if (mips_trap) | |
2396cfb9 | 4416 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq", |
9bd7d936 | 4417 | "s,t,q", 0, 0, 7); |
252b5132 | 4418 | else |
2396cfb9 TS |
4419 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
4420 | "c", 7); | |
252b5132 RH |
4421 | return; |
4422 | } | |
4423 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4424 | { | |
4425 | if (strcmp (s2, "mflo") == 0) | |
ea1fb5dc | 4426 | move_register (&icnt, dreg, sreg); |
252b5132 | 4427 | else |
ea1fb5dc | 4428 | move_register (&icnt, dreg, 0); |
252b5132 RH |
4429 | return; |
4430 | } | |
4431 | if (imm_expr.X_op == O_constant | |
4432 | && imm_expr.X_add_number == -1 | |
4433 | && s[strlen (s) - 1] != 'u') | |
4434 | { | |
4435 | if (strcmp (s2, "mflo") == 0) | |
4436 | { | |
2396cfb9 TS |
4437 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4438 | dbl ? "dneg" : "neg", "d,w", dreg, sreg); | |
252b5132 RH |
4439 | } |
4440 | else | |
ea1fb5dc | 4441 | move_register (&icnt, dreg, 0); |
252b5132 RH |
4442 | return; |
4443 | } | |
4444 | ||
4445 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 TS |
4446 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t", |
4447 | sreg, AT); | |
4448 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d", dreg); | |
252b5132 RH |
4449 | break; |
4450 | ||
4451 | case M_DIVU_3: | |
4452 | s = "divu"; | |
4453 | s2 = "mflo"; | |
4454 | goto do_divu3; | |
4455 | case M_REMU_3: | |
4456 | s = "divu"; | |
4457 | s2 = "mfhi"; | |
4458 | goto do_divu3; | |
4459 | case M_DDIVU_3: | |
4460 | s = "ddivu"; | |
4461 | s2 = "mflo"; | |
4462 | goto do_divu3; | |
4463 | case M_DREMU_3: | |
4464 | s = "ddivu"; | |
4465 | s2 = "mfhi"; | |
4466 | do_divu3: | |
4467 | mips_emit_delays (true); | |
4468 | ++mips_opts.noreorder; | |
4469 | mips_any_noreorder = 1; | |
4470 | if (mips_trap) | |
4471 | { | |
2396cfb9 | 4472 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "teq", |
9bd7d936 | 4473 | "s,t,q", treg, 0, 7); |
2396cfb9 TS |
4474 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t", |
4475 | sreg, treg); | |
252b5132 RH |
4476 | /* We want to close the noreorder block as soon as possible, so |
4477 | that later insns are available for delay slot filling. */ | |
4478 | --mips_opts.noreorder; | |
4479 | } | |
4480 | else | |
4481 | { | |
4482 | expr1.X_add_number = 8; | |
4483 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
2396cfb9 TS |
4484 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "z,s,t", |
4485 | sreg, treg); | |
252b5132 RH |
4486 | |
4487 | /* We want to close the noreorder block as soon as possible, so | |
4488 | that later insns are available for delay slot filling. */ | |
4489 | --mips_opts.noreorder; | |
2396cfb9 TS |
4490 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
4491 | "c", 7); | |
252b5132 | 4492 | } |
2396cfb9 | 4493 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "d", dreg); |
252b5132 RH |
4494 | return; |
4495 | ||
4496 | case M_DLA_AB: | |
4497 | dbl = 1; | |
4498 | case M_LA_AB: | |
4499 | /* Load the address of a symbol into a register. If breg is not | |
4500 | zero, we then add a base register to it. */ | |
4501 | ||
3bec30a8 TS |
4502 | if (dbl && HAVE_32BIT_GPRS) |
4503 | as_warn (_("dla used to load 32-bit register")); | |
4504 | ||
c90bbe5b | 4505 | if (! dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
4506 | as_warn (_("la used to load 64-bit address")); |
4507 | ||
0c11417f MR |
4508 | if (offset_expr.X_op == O_constant |
4509 | && offset_expr.X_add_number >= -0x8000 | |
4510 | && offset_expr.X_add_number < 0x8000) | |
4511 | { | |
4512 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4513 | (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu", | |
4514 | "t,r,j", treg, sreg, (int) BFD_RELOC_LO16); | |
4515 | return; | |
4516 | } | |
4517 | ||
afdbd6d0 CD |
4518 | if (treg == breg) |
4519 | { | |
4520 | tempreg = AT; | |
4521 | used_at = 1; | |
4522 | } | |
4523 | else | |
4524 | { | |
4525 | tempreg = treg; | |
4526 | used_at = 0; | |
4527 | } | |
4528 | ||
252b5132 RH |
4529 | /* When generating embedded PIC code, we permit expressions of |
4530 | the form | |
afdbd6d0 CD |
4531 | la $treg,foo-bar |
4532 | la $treg,foo-bar($breg) | |
bb2d6cd7 | 4533 | where bar is an address in the current section. These are used |
252b5132 RH |
4534 | when getting the addresses of functions. We don't permit |
4535 | X_add_number to be non-zero, because if the symbol is | |
4536 | external the relaxing code needs to know that any addend is | |
4537 | purely the offset to X_op_symbol. */ | |
4538 | if (mips_pic == EMBEDDED_PIC | |
4539 | && offset_expr.X_op == O_subtract | |
49309057 | 4540 | && (symbol_constant_p (offset_expr.X_op_symbol) |
bb2d6cd7 | 4541 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg |
49309057 ILT |
4542 | : (symbol_equated_p (offset_expr.X_op_symbol) |
4543 | && (S_GET_SEGMENT | |
4544 | (symbol_get_value_expression (offset_expr.X_op_symbol) | |
4545 | ->X_add_symbol) | |
bb2d6cd7 | 4546 | == now_seg))) |
bb2d6cd7 GK |
4547 | && (offset_expr.X_add_number == 0 |
4548 | || OUTPUT_FLAVOR == bfd_target_elf_flavour)) | |
252b5132 | 4549 | { |
afdbd6d0 CD |
4550 | if (breg == 0) |
4551 | { | |
4552 | tempreg = treg; | |
4553 | used_at = 0; | |
4554 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4555 | tempreg, (int) BFD_RELOC_PCREL_HI16_S); | |
4556 | } | |
4557 | else | |
4558 | { | |
4559 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4560 | tempreg, (int) BFD_RELOC_PCREL_HI16_S); | |
4561 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4d34fb5f | 4562 | (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu", |
afdbd6d0 CD |
4563 | "d,v,t", tempreg, tempreg, breg); |
4564 | } | |
252b5132 | 4565 | macro_build ((char *) NULL, &icnt, &offset_expr, |
4d34fb5f | 4566 | (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu", |
afdbd6d0 CD |
4567 | "t,r,j", treg, tempreg, (int) BFD_RELOC_PCREL_LO16); |
4568 | if (! used_at) | |
4569 | return; | |
4570 | break; | |
252b5132 RH |
4571 | } |
4572 | ||
4573 | if (offset_expr.X_op != O_symbol | |
4574 | && offset_expr.X_op != O_constant) | |
4575 | { | |
4576 | as_bad (_("expression too complex")); | |
4577 | offset_expr.X_op = O_constant; | |
4578 | } | |
4579 | ||
252b5132 | 4580 | if (offset_expr.X_op == O_constant) |
4d34fb5f TS |
4581 | load_register (&icnt, tempreg, &offset_expr, |
4582 | ((mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC) | |
4583 | ? (dbl || HAVE_64BIT_ADDRESSES) | |
4584 | : HAVE_64BIT_ADDRESSES)); | |
252b5132 RH |
4585 | else if (mips_pic == NO_PIC) |
4586 | { | |
d6bc6245 | 4587 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 4588 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
4589 | Otherwise we want |
4590 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4591 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4592 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 4593 | so we may as well always use the latter form. |
76b3015f | 4594 | |
d6bc6245 TS |
4595 | With 64bit address space and a usable $at we want |
4596 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4597 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
4598 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4599 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
4600 | dsll32 $tempreg,0 | |
3a482fd5 | 4601 | daddu $tempreg,$tempreg,$at |
76b3015f | 4602 | |
d6bc6245 TS |
4603 | If $at is already in use, we use an path which is suboptimal |
4604 | on superscalar processors. | |
4605 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4606 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4607 | dsll $tempreg,16 | |
4608 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4609 | dsll $tempreg,16 | |
4610 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
4611 | */ | |
f9419b05 | 4612 | char *p = NULL; |
d6bc6245 | 4613 | if (HAVE_64BIT_ADDRESSES) |
252b5132 | 4614 | { |
d6bc6245 TS |
4615 | /* We don't do GP optimization for now because RELAX_ENCODE can't |
4616 | hold the data for such large chunks. */ | |
4617 | ||
460597ba | 4618 | if (used_at == 0 && ! mips_opts.noat) |
98d3f06f KH |
4619 | { |
4620 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
4621 | tempreg, (int) BFD_RELOC_MIPS_HIGHEST); | |
4622 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
4623 | AT, (int) BFD_RELOC_HI16_S); | |
4624 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
4625 | tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER); | |
4626 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
4627 | AT, AT, (int) BFD_RELOC_LO16); | |
4628 | macro_build (p, &icnt, (expressionS *) NULL, "dsll32", | |
4629 | "d,w,<", tempreg, tempreg, 0); | |
3a482fd5 MR |
4630 | macro_build (p, &icnt, (expressionS *) NULL, "daddu", |
4631 | "d,v,t", tempreg, tempreg, AT); | |
98d3f06f KH |
4632 | used_at = 1; |
4633 | } | |
4634 | else | |
4635 | { | |
4636 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
4637 | tempreg, (int) BFD_RELOC_MIPS_HIGHEST); | |
4638 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
4639 | tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER); | |
4640 | macro_build (p, &icnt, (expressionS *) NULL, "dsll", "d,w,<", | |
4641 | tempreg, tempreg, 16); | |
4642 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
4643 | tempreg, tempreg, (int) BFD_RELOC_HI16_S); | |
4644 | macro_build (p, &icnt, (expressionS *) NULL, "dsll", "d,w,<", | |
4645 | tempreg, tempreg, 16); | |
4646 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
4647 | tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4648 | } | |
4649 | } | |
4650 | else | |
4651 | { | |
4652 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
4653 | && ! nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
4654 | { | |
4655 | frag_grow (20); | |
4656 | macro_build ((char *) NULL, &icnt, &offset_expr, "addiu", | |
c9914766 TS |
4657 | "t,r,j", tempreg, mips_gp_register, |
4658 | (int) BFD_RELOC_GPREL16); | |
98d3f06f KH |
4659 | p = frag_var (rs_machine_dependent, 8, 0, |
4660 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
4661 | mips_opts.warn_about_macros), | |
4662 | offset_expr.X_add_symbol, 0, NULL); | |
4663 | } | |
4664 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4665 | if (p != NULL) | |
4666 | p += 4; | |
4667 | macro_build (p, &icnt, &offset_expr, "addiu", | |
4668 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4669 | } | |
252b5132 RH |
4670 | } |
4671 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
4672 | { | |
9117d219 NC |
4673 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
4674 | ||
252b5132 RH |
4675 | /* If this is a reference to an external symbol, and there |
4676 | is no constant, we want | |
4677 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9117d219 NC |
4678 | or if tempreg is PIC_CALL_REG |
4679 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
252b5132 RH |
4680 | For a local symbol, we want |
4681 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4682 | nop | |
4683 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4684 | ||
4685 | If we have a small constant, and this is a reference to | |
4686 | an external symbol, we want | |
4687 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4688 | nop | |
4689 | addiu $tempreg,$tempreg,<constant> | |
4690 | For a local symbol, we want the same instruction | |
4691 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
4692 | addiu instruction. | |
4693 | ||
4694 | If we have a large constant, and this is a reference to | |
4695 | an external symbol, we want | |
4696 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4697 | lui $at,<hiconstant> | |
4698 | addiu $at,$at,<loconstant> | |
4699 | addu $tempreg,$tempreg,$at | |
4700 | For a local symbol, we want the same instruction | |
4701 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd SC |
4702 | addiu instruction. |
4703 | ||
4704 | For NewABI, we want for local or external data addresses | |
4705 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
4706 | For a local function symbol, we want | |
4707 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
4708 | nop | |
4709 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
4710 | */ | |
4711 | ||
252b5132 RH |
4712 | expr1.X_add_number = offset_expr.X_add_number; |
4713 | offset_expr.X_add_number = 0; | |
4714 | frag_grow (32); | |
9117d219 NC |
4715 | if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG) |
4716 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; | |
ed6fb7bd SC |
4717 | else if (HAVE_NEWABI) |
4718 | lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_DISP; | |
4d34fb5f TS |
4719 | macro_build ((char *) NULL, &icnt, &offset_expr, |
4720 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", | |
c9914766 | 4721 | "t,o(b)", tempreg, lw_reloc_type, mips_gp_register); |
252b5132 RH |
4722 | if (expr1.X_add_number == 0) |
4723 | { | |
4724 | int off; | |
f9419b05 | 4725 | char *p; |
252b5132 RH |
4726 | |
4727 | if (breg == 0) | |
4728 | off = 0; | |
4729 | else | |
4730 | { | |
4731 | /* We're going to put in an addu instruction using | |
4732 | tempreg, so we may as well insert the nop right | |
4733 | now. */ | |
4734 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4735 | "nop", ""); | |
4736 | off = 4; | |
4737 | } | |
4738 | p = frag_var (rs_machine_dependent, 8 - off, 0, | |
4739 | RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0, | |
4740 | (breg == 0 | |
4741 | ? mips_opts.warn_about_macros | |
4742 | : 0)), | |
c4e7957c | 4743 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
4744 | if (breg == 0) |
4745 | { | |
4746 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4747 | p += 4; | |
4748 | } | |
4749 | macro_build (p, &icnt, &expr1, | |
ca4e0257 | 4750 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
4751 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4752 | /* FIXME: If breg == 0, and the next instruction uses | |
4753 | $tempreg, then if this variant case is used an extra | |
4754 | nop will be generated. */ | |
4755 | } | |
4756 | else if (expr1.X_add_number >= -0x8000 | |
4757 | && expr1.X_add_number < 0x8000) | |
4758 | { | |
4759 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4760 | "nop", ""); | |
4761 | macro_build ((char *) NULL, &icnt, &expr1, | |
ca4e0257 | 4762 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 | 4763 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
c4e7957c TS |
4764 | frag_var (rs_machine_dependent, 0, 0, |
4765 | RELAX_ENCODE (0, 0, -12, -4, 0, 0), | |
4766 | offset_expr.X_add_symbol, 0, NULL); | |
252b5132 RH |
4767 | } |
4768 | else | |
4769 | { | |
4770 | int off1; | |
4771 | ||
4772 | /* If we are going to add in a base register, and the | |
4773 | target register and the base register are the same, | |
4774 | then we are using AT as a temporary register. Since | |
4775 | we want to load the constant into AT, we add our | |
4776 | current AT (from the global offset table) and the | |
4777 | register into the register now, and pretend we were | |
4778 | not using a base register. */ | |
4779 | if (breg != treg) | |
4780 | off1 = 0; | |
4781 | else | |
4782 | { | |
4783 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4784 | "nop", ""); | |
4785 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 4786 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
4787 | "d,v,t", treg, AT, breg); |
4788 | breg = 0; | |
4789 | tempreg = treg; | |
4790 | off1 = -8; | |
4791 | } | |
4792 | ||
4793 | /* Set mips_optimize around the lui instruction to avoid | |
4794 | inserting an unnecessary nop after the lw. */ | |
4795 | hold_mips_optimize = mips_optimize; | |
4796 | mips_optimize = 2; | |
c4e7957c | 4797 | macro_build_lui (NULL, &icnt, &expr1, AT); |
252b5132 RH |
4798 | mips_optimize = hold_mips_optimize; |
4799 | ||
4800 | macro_build ((char *) NULL, &icnt, &expr1, | |
ca4e0257 | 4801 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
4802 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
4803 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 4804 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 | 4805 | "d,v,t", tempreg, tempreg, AT); |
c4e7957c TS |
4806 | frag_var (rs_machine_dependent, 0, 0, |
4807 | RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0), | |
4808 | offset_expr.X_add_symbol, 0, NULL); | |
252b5132 RH |
4809 | used_at = 1; |
4810 | } | |
4811 | } | |
4812 | else if (mips_pic == SVR4_PIC) | |
4813 | { | |
4814 | int gpdel; | |
f9419b05 | 4815 | char *p; |
9117d219 NC |
4816 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
4817 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 4818 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
4819 | |
4820 | /* This is the large GOT case. If this is a reference to an | |
4821 | external symbol, and there is no constant, we want | |
4822 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4823 | addu $tempreg,$tempreg,$gp | |
4824 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
9117d219 NC |
4825 | or if tempreg is PIC_CALL_REG |
4826 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
4827 | addu $tempreg,$tempreg,$gp | |
4828 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
4829 | For a local symbol, we want |
4830 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4831 | nop | |
4832 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4833 | ||
4834 | If we have a small constant, and this is a reference to | |
4835 | an external symbol, we want | |
4836 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4837 | addu $tempreg,$tempreg,$gp | |
4838 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4839 | nop | |
4840 | addiu $tempreg,$tempreg,<constant> | |
4841 | For a local symbol, we want | |
4842 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4843 | nop | |
4844 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
4845 | ||
4846 | If we have a large constant, and this is a reference to | |
4847 | an external symbol, we want | |
4848 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4849 | addu $tempreg,$tempreg,$gp | |
4850 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4851 | lui $at,<hiconstant> | |
4852 | addiu $at,$at,<loconstant> | |
4853 | addu $tempreg,$tempreg,$at | |
4854 | For a local symbol, we want | |
4855 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4856 | lui $at,<hiconstant> | |
4857 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
4858 | addu $tempreg,$tempreg,$at | |
438c16b8 | 4859 | |
ed6fb7bd SC |
4860 | For NewABI, we want for local data addresses |
4861 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
438c16b8 | 4862 | */ |
438c16b8 | 4863 | |
252b5132 RH |
4864 | expr1.X_add_number = offset_expr.X_add_number; |
4865 | offset_expr.X_add_number = 0; | |
4866 | frag_grow (52); | |
f7ea7ef2 | 4867 | if (reg_needs_delay (mips_gp_register)) |
252b5132 RH |
4868 | gpdel = 4; |
4869 | else | |
4870 | gpdel = 0; | |
9117d219 NC |
4871 | if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG) |
4872 | { | |
4873 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
4874 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
4875 | } | |
252b5132 | 4876 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", |
9117d219 | 4877 | tempreg, lui_reloc_type); |
252b5132 | 4878 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
ca4e0257 | 4879 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
c9914766 | 4880 | "d,v,t", tempreg, tempreg, mips_gp_register); |
252b5132 | 4881 | macro_build ((char *) NULL, &icnt, &offset_expr, |
4d34fb5f | 4882 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
9117d219 | 4883 | "t,o(b)", tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
4884 | if (expr1.X_add_number == 0) |
4885 | { | |
4886 | int off; | |
4887 | ||
4888 | if (breg == 0) | |
4889 | off = 0; | |
4890 | else | |
4891 | { | |
4892 | /* We're going to put in an addu instruction using | |
4893 | tempreg, so we may as well insert the nop right | |
4894 | now. */ | |
4895 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4896 | "nop", ""); | |
4897 | off = 4; | |
4898 | } | |
4899 | ||
4900 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4901 | RELAX_ENCODE (12 + off, 12 + gpdel, gpdel, | |
4902 | 8 + gpdel, 0, | |
4903 | (breg == 0 | |
4904 | ? mips_opts.warn_about_macros | |
4905 | : 0)), | |
c4e7957c | 4906 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
4907 | } |
4908 | else if (expr1.X_add_number >= -0x8000 | |
4909 | && expr1.X_add_number < 0x8000) | |
4910 | { | |
4911 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4912 | "nop", ""); | |
4913 | macro_build ((char *) NULL, &icnt, &expr1, | |
ca4e0257 | 4914 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
4915 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4916 | ||
4917 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4918 | RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0, | |
4919 | (breg == 0 | |
4920 | ? mips_opts.warn_about_macros | |
4921 | : 0)), | |
c4e7957c | 4922 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
4923 | } |
4924 | else | |
4925 | { | |
4926 | int adj, dreg; | |
4927 | ||
4928 | /* If we are going to add in a base register, and the | |
4929 | target register and the base register are the same, | |
4930 | then we are using AT as a temporary register. Since | |
4931 | we want to load the constant into AT, we add our | |
4932 | current AT (from the global offset table) and the | |
4933 | register into the register now, and pretend we were | |
4934 | not using a base register. */ | |
4935 | if (breg != treg) | |
4936 | { | |
4937 | adj = 0; | |
4938 | dreg = tempreg; | |
4939 | } | |
4940 | else | |
4941 | { | |
4942 | assert (tempreg == AT); | |
4943 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4944 | "nop", ""); | |
4945 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 4946 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
4947 | "d,v,t", treg, AT, breg); |
4948 | dreg = treg; | |
4949 | adj = 8; | |
4950 | } | |
4951 | ||
4952 | /* Set mips_optimize around the lui instruction to avoid | |
4953 | inserting an unnecessary nop after the lw. */ | |
4954 | hold_mips_optimize = mips_optimize; | |
4955 | mips_optimize = 2; | |
c4e7957c | 4956 | macro_build_lui (NULL, &icnt, &expr1, AT); |
252b5132 RH |
4957 | mips_optimize = hold_mips_optimize; |
4958 | ||
4959 | macro_build ((char *) NULL, &icnt, &expr1, | |
ca4e0257 | 4960 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
4961 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
4962 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 4963 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
4964 | "d,v,t", dreg, dreg, AT); |
4965 | ||
4966 | p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0, | |
4967 | RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel, | |
4968 | 8 + gpdel, 0, | |
4969 | (breg == 0 | |
4970 | ? mips_opts.warn_about_macros | |
4971 | : 0)), | |
c4e7957c | 4972 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
4973 | |
4974 | used_at = 1; | |
4975 | } | |
4976 | ||
4977 | if (gpdel > 0) | |
4978 | { | |
4979 | /* This is needed because this instruction uses $gp, but | |
4980 | the first instruction on the main stream does not. */ | |
4981 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4982 | p += 4; | |
4983 | } | |
ed6fb7bd SC |
4984 | |
4985 | if (HAVE_NEWABI) | |
4986 | local_reloc_type = (int) BFD_RELOC_MIPS_GOT_DISP; | |
252b5132 | 4987 | macro_build (p, &icnt, &offset_expr, |
4d34fb5f | 4988 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
ed6fb7bd SC |
4989 | "t,o(b)", tempreg, |
4990 | local_reloc_type, | |
c9914766 | 4991 | mips_gp_register); |
252b5132 | 4992 | p += 4; |
ed6fb7bd SC |
4993 | if (expr1.X_add_number == 0 && HAVE_NEWABI) |
4994 | { | |
4995 | /* BFD_RELOC_MIPS_GOT_DISP is sufficient for newabi */ | |
4996 | } | |
4997 | else | |
4998 | if (expr1.X_add_number >= -0x8000 | |
252b5132 RH |
4999 | && expr1.X_add_number < 0x8000) |
5000 | { | |
5001 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5002 | p += 4; | |
5003 | macro_build (p, &icnt, &expr1, | |
ca4e0257 | 5004 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
5005 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
5006 | /* FIXME: If add_number is 0, and there was no base | |
5007 | register, the external symbol case ended with a load, | |
5008 | so if the symbol turns out to not be external, and | |
5009 | the next instruction uses tempreg, an unnecessary nop | |
5010 | will be inserted. */ | |
5011 | } | |
5012 | else | |
5013 | { | |
5014 | if (breg == treg) | |
5015 | { | |
5016 | /* We must add in the base register now, as in the | |
5017 | external symbol case. */ | |
5018 | assert (tempreg == AT); | |
5019 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5020 | p += 4; | |
5021 | macro_build (p, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5022 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5023 | "d,v,t", treg, AT, breg); |
5024 | p += 4; | |
5025 | tempreg = treg; | |
5026 | /* We set breg to 0 because we have arranged to add | |
5027 | it in in both cases. */ | |
5028 | breg = 0; | |
5029 | } | |
5030 | ||
5031 | macro_build_lui (p, &icnt, &expr1, AT); | |
5032 | p += 4; | |
5033 | macro_build (p, &icnt, &expr1, | |
ca4e0257 | 5034 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
5035 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
5036 | p += 4; | |
5037 | macro_build (p, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5038 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5039 | "d,v,t", tempreg, tempreg, AT); |
5040 | p += 4; | |
5041 | } | |
5042 | } | |
5043 | else if (mips_pic == EMBEDDED_PIC) | |
5044 | { | |
5045 | /* We use | |
cdf6fd85 | 5046 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
5047 | */ |
5048 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
c9914766 TS |
5049 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j", |
5050 | tempreg, mips_gp_register, (int) BFD_RELOC_GPREL16); | |
252b5132 RH |
5051 | } |
5052 | else | |
5053 | abort (); | |
5054 | ||
5055 | if (breg != 0) | |
4d34fb5f TS |
5056 | { |
5057 | char *s; | |
5058 | ||
5059 | if (mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC) | |
5060 | s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu"; | |
5061 | else | |
5062 | s = HAVE_64BIT_ADDRESSES ? "daddu" : "addu"; | |
5063 | ||
5064 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, | |
5065 | "d,v,t", treg, tempreg, breg); | |
5066 | } | |
252b5132 RH |
5067 | |
5068 | if (! used_at) | |
5069 | return; | |
5070 | ||
5071 | break; | |
5072 | ||
5073 | case M_J_A: | |
5074 | /* The j instruction may not be used in PIC code, since it | |
5075 | requires an absolute address. We convert it to a b | |
5076 | instruction. */ | |
5077 | if (mips_pic == NO_PIC) | |
5078 | macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a"); | |
5079 | else | |
5080 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); | |
5081 | return; | |
5082 | ||
5083 | /* The jal instructions must be handled as macros because when | |
5084 | generating PIC code they expand to multi-instruction | |
5085 | sequences. Normally they are simple instructions. */ | |
5086 | case M_JAL_1: | |
5087 | dreg = RA; | |
5088 | /* Fall through. */ | |
5089 | case M_JAL_2: | |
5090 | if (mips_pic == NO_PIC | |
5091 | || mips_pic == EMBEDDED_PIC) | |
5092 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", | |
5093 | "d,s", dreg, sreg); | |
5094 | else if (mips_pic == SVR4_PIC) | |
5095 | { | |
5096 | if (sreg != PIC_CALL_REG) | |
5097 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 5098 | |
252b5132 RH |
5099 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", |
5100 | "d,s", dreg, sreg); | |
6478892d | 5101 | if (! HAVE_NEWABI) |
252b5132 | 5102 | { |
6478892d TS |
5103 | if (mips_cprestore_offset < 0) |
5104 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5105 | else | |
5106 | { | |
7a621144 DJ |
5107 | if (! mips_frame_reg_valid) |
5108 | { | |
5109 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5110 | /* Quiet this warning. */ | |
5111 | mips_frame_reg_valid = 1; | |
5112 | } | |
5113 | if (! mips_cprestore_valid) | |
5114 | { | |
5115 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5116 | /* Quiet this warning. */ | |
5117 | mips_cprestore_valid = 1; | |
5118 | } | |
6478892d | 5119 | expr1.X_add_number = mips_cprestore_offset; |
885add95 CD |
5120 | macro_build_ldst_constoffset ((char *) NULL, &icnt, &expr1, |
5121 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", | |
5122 | mips_gp_register, mips_frame_reg); | |
6478892d | 5123 | } |
252b5132 RH |
5124 | } |
5125 | } | |
5126 | else | |
5127 | abort (); | |
5128 | ||
5129 | return; | |
5130 | ||
5131 | case M_JAL_A: | |
5132 | if (mips_pic == NO_PIC) | |
5133 | macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a"); | |
5134 | else if (mips_pic == SVR4_PIC) | |
5135 | { | |
f9419b05 TS |
5136 | char *p; |
5137 | ||
252b5132 RH |
5138 | /* If this is a reference to an external symbol, and we are |
5139 | using a small GOT, we want | |
5140 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
5141 | nop | |
f9419b05 | 5142 | jalr $ra,$25 |
252b5132 RH |
5143 | nop |
5144 | lw $gp,cprestore($sp) | |
5145 | The cprestore value is set using the .cprestore | |
5146 | pseudo-op. If we are using a big GOT, we want | |
5147 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
5148 | addu $25,$25,$gp | |
5149 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
5150 | nop | |
f9419b05 | 5151 | jalr $ra,$25 |
252b5132 RH |
5152 | nop |
5153 | lw $gp,cprestore($sp) | |
5154 | If the symbol is not external, we want | |
5155 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5156 | nop | |
5157 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 5158 | jalr $ra,$25 |
252b5132 | 5159 | nop |
438c16b8 TS |
5160 | lw $gp,cprestore($sp) |
5161 | For NewABI, we want | |
5162 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5163 | jalr $ra,$25 (BFD_RELOC_MIPS_JALR) | |
5164 | */ | |
5165 | if (HAVE_NEWABI) | |
252b5132 RH |
5166 | { |
5167 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 5168 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 | 5169 | "t,o(b)", PIC_CALL_REG, |
438c16b8 TS |
5170 | (int) BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
5171 | macro_build_jalr (icnt, &offset_expr); | |
252b5132 RH |
5172 | } |
5173 | else | |
5174 | { | |
438c16b8 TS |
5175 | frag_grow (40); |
5176 | if (! mips_big_got) | |
5177 | { | |
5178 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
5179 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", | |
5180 | "t,o(b)", PIC_CALL_REG, | |
5181 | (int) BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
5182 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5183 | "nop", ""); | |
5184 | p = frag_var (rs_machine_dependent, 4, 0, | |
5185 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
5186 | offset_expr.X_add_symbol, 0, NULL); | |
5187 | } | |
252b5132 | 5188 | else |
252b5132 | 5189 | { |
438c16b8 TS |
5190 | int gpdel; |
5191 | ||
5192 | if (reg_needs_delay (mips_gp_register)) | |
5193 | gpdel = 4; | |
5194 | else | |
5195 | gpdel = 0; | |
5196 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", | |
5197 | "t,u", PIC_CALL_REG, | |
5198 | (int) BFD_RELOC_MIPS_CALL_HI16); | |
5199 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5200 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", | |
5201 | "d,v,t", PIC_CALL_REG, PIC_CALL_REG, | |
5202 | mips_gp_register); | |
5203 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
5204 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", | |
5205 | "t,o(b)", PIC_CALL_REG, | |
5206 | (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG); | |
5207 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5208 | "nop", ""); | |
5209 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
5210 | RELAX_ENCODE (16, 12 + gpdel, gpdel, | |
5211 | 8 + gpdel, 0, 0), | |
5212 | offset_expr.X_add_symbol, 0, NULL); | |
5213 | if (gpdel > 0) | |
5214 | { | |
5215 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5216 | p += 4; | |
5217 | } | |
5218 | macro_build (p, &icnt, &offset_expr, | |
5219 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", | |
5220 | "t,o(b)", PIC_CALL_REG, | |
5221 | (int) BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
5222 | p += 4; | |
252b5132 RH |
5223 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); |
5224 | p += 4; | |
5225 | } | |
5226 | macro_build (p, &icnt, &offset_expr, | |
438c16b8 TS |
5227 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
5228 | "t,r,j", PIC_CALL_REG, PIC_CALL_REG, | |
5229 | (int) BFD_RELOC_LO16); | |
5230 | macro_build_jalr (icnt, &offset_expr); | |
5231 | ||
6478892d TS |
5232 | if (mips_cprestore_offset < 0) |
5233 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5234 | else | |
5235 | { | |
7a621144 DJ |
5236 | if (! mips_frame_reg_valid) |
5237 | { | |
5238 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5239 | /* Quiet this warning. */ | |
5240 | mips_frame_reg_valid = 1; | |
5241 | } | |
5242 | if (! mips_cprestore_valid) | |
5243 | { | |
5244 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5245 | /* Quiet this warning. */ | |
5246 | mips_cprestore_valid = 1; | |
5247 | } | |
6478892d TS |
5248 | if (mips_opts.noreorder) |
5249 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
98d3f06f | 5250 | "nop", ""); |
6478892d | 5251 | expr1.X_add_number = mips_cprestore_offset; |
885add95 CD |
5252 | macro_build_ldst_constoffset ((char *) NULL, &icnt, &expr1, |
5253 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", | |
5254 | mips_gp_register, mips_frame_reg); | |
6478892d | 5255 | } |
252b5132 RH |
5256 | } |
5257 | } | |
5258 | else if (mips_pic == EMBEDDED_PIC) | |
5259 | { | |
5260 | macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p"); | |
5261 | /* The linker may expand the call to a longer sequence which | |
5262 | uses $at, so we must break rather than return. */ | |
5263 | break; | |
5264 | } | |
5265 | else | |
5266 | abort (); | |
5267 | ||
5268 | return; | |
5269 | ||
5270 | case M_LB_AB: | |
5271 | s = "lb"; | |
5272 | goto ld; | |
5273 | case M_LBU_AB: | |
5274 | s = "lbu"; | |
5275 | goto ld; | |
5276 | case M_LH_AB: | |
5277 | s = "lh"; | |
5278 | goto ld; | |
5279 | case M_LHU_AB: | |
5280 | s = "lhu"; | |
5281 | goto ld; | |
5282 | case M_LW_AB: | |
5283 | s = "lw"; | |
5284 | goto ld; | |
5285 | case M_LWC0_AB: | |
5286 | s = "lwc0"; | |
bdaaa2e1 | 5287 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5288 | coproc = 1; |
5289 | goto ld; | |
5290 | case M_LWC1_AB: | |
5291 | s = "lwc1"; | |
bdaaa2e1 | 5292 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5293 | coproc = 1; |
5294 | goto ld; | |
5295 | case M_LWC2_AB: | |
5296 | s = "lwc2"; | |
bdaaa2e1 | 5297 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5298 | coproc = 1; |
5299 | goto ld; | |
5300 | case M_LWC3_AB: | |
5301 | s = "lwc3"; | |
bdaaa2e1 | 5302 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5303 | coproc = 1; |
5304 | goto ld; | |
5305 | case M_LWL_AB: | |
5306 | s = "lwl"; | |
5307 | lr = 1; | |
5308 | goto ld; | |
5309 | case M_LWR_AB: | |
5310 | s = "lwr"; | |
5311 | lr = 1; | |
5312 | goto ld; | |
5313 | case M_LDC1_AB: | |
ec68c924 | 5314 | if (mips_arch == CPU_R4650) |
252b5132 RH |
5315 | { |
5316 | as_bad (_("opcode not supported on this processor")); | |
5317 | return; | |
5318 | } | |
5319 | s = "ldc1"; | |
bdaaa2e1 | 5320 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5321 | coproc = 1; |
5322 | goto ld; | |
5323 | case M_LDC2_AB: | |
5324 | s = "ldc2"; | |
bdaaa2e1 | 5325 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5326 | coproc = 1; |
5327 | goto ld; | |
5328 | case M_LDC3_AB: | |
5329 | s = "ldc3"; | |
bdaaa2e1 | 5330 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5331 | coproc = 1; |
5332 | goto ld; | |
5333 | case M_LDL_AB: | |
5334 | s = "ldl"; | |
5335 | lr = 1; | |
5336 | goto ld; | |
5337 | case M_LDR_AB: | |
5338 | s = "ldr"; | |
5339 | lr = 1; | |
5340 | goto ld; | |
5341 | case M_LL_AB: | |
5342 | s = "ll"; | |
5343 | goto ld; | |
5344 | case M_LLD_AB: | |
5345 | s = "lld"; | |
5346 | goto ld; | |
5347 | case M_LWU_AB: | |
5348 | s = "lwu"; | |
5349 | ld: | |
5350 | if (breg == treg || coproc || lr) | |
5351 | { | |
5352 | tempreg = AT; | |
5353 | used_at = 1; | |
5354 | } | |
5355 | else | |
5356 | { | |
5357 | tempreg = treg; | |
5358 | used_at = 0; | |
5359 | } | |
5360 | goto ld_st; | |
5361 | case M_SB_AB: | |
5362 | s = "sb"; | |
5363 | goto st; | |
5364 | case M_SH_AB: | |
5365 | s = "sh"; | |
5366 | goto st; | |
5367 | case M_SW_AB: | |
5368 | s = "sw"; | |
5369 | goto st; | |
5370 | case M_SWC0_AB: | |
5371 | s = "swc0"; | |
bdaaa2e1 | 5372 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5373 | coproc = 1; |
5374 | goto st; | |
5375 | case M_SWC1_AB: | |
5376 | s = "swc1"; | |
bdaaa2e1 | 5377 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5378 | coproc = 1; |
5379 | goto st; | |
5380 | case M_SWC2_AB: | |
5381 | s = "swc2"; | |
bdaaa2e1 | 5382 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5383 | coproc = 1; |
5384 | goto st; | |
5385 | case M_SWC3_AB: | |
5386 | s = "swc3"; | |
bdaaa2e1 | 5387 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5388 | coproc = 1; |
5389 | goto st; | |
5390 | case M_SWL_AB: | |
5391 | s = "swl"; | |
5392 | goto st; | |
5393 | case M_SWR_AB: | |
5394 | s = "swr"; | |
5395 | goto st; | |
5396 | case M_SC_AB: | |
5397 | s = "sc"; | |
5398 | goto st; | |
5399 | case M_SCD_AB: | |
5400 | s = "scd"; | |
5401 | goto st; | |
5402 | case M_SDC1_AB: | |
ec68c924 | 5403 | if (mips_arch == CPU_R4650) |
252b5132 RH |
5404 | { |
5405 | as_bad (_("opcode not supported on this processor")); | |
5406 | return; | |
5407 | } | |
5408 | s = "sdc1"; | |
5409 | coproc = 1; | |
bdaaa2e1 | 5410 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5411 | goto st; |
5412 | case M_SDC2_AB: | |
5413 | s = "sdc2"; | |
bdaaa2e1 | 5414 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5415 | coproc = 1; |
5416 | goto st; | |
5417 | case M_SDC3_AB: | |
5418 | s = "sdc3"; | |
bdaaa2e1 | 5419 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5420 | coproc = 1; |
5421 | goto st; | |
5422 | case M_SDL_AB: | |
5423 | s = "sdl"; | |
5424 | goto st; | |
5425 | case M_SDR_AB: | |
5426 | s = "sdr"; | |
5427 | st: | |
5428 | tempreg = AT; | |
5429 | used_at = 1; | |
5430 | ld_st: | |
bdaaa2e1 | 5431 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5432 | if (mask == M_LWC1_AB |
5433 | || mask == M_SWC1_AB | |
5434 | || mask == M_LDC1_AB | |
5435 | || mask == M_SDC1_AB | |
5436 | || mask == M_L_DAB | |
5437 | || mask == M_S_DAB) | |
5438 | fmt = "T,o(b)"; | |
5439 | else if (coproc) | |
5440 | fmt = "E,o(b)"; | |
5441 | else | |
5442 | fmt = "t,o(b)"; | |
5443 | ||
afdbd6d0 CD |
5444 | /* For embedded PIC, we allow loads where the offset is calculated |
5445 | by subtracting a symbol in the current segment from an unknown | |
5446 | symbol, relative to a base register, e.g.: | |
5447 | <op> $treg, <sym>-<localsym>($breg) | |
5448 | This is used by the compiler for switch statements. */ | |
76b3015f | 5449 | if (mips_pic == EMBEDDED_PIC |
afdbd6d0 CD |
5450 | && offset_expr.X_op == O_subtract |
5451 | && (symbol_constant_p (offset_expr.X_op_symbol) | |
5452 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg | |
5453 | : (symbol_equated_p (offset_expr.X_op_symbol) | |
5454 | && (S_GET_SEGMENT | |
5455 | (symbol_get_value_expression (offset_expr.X_op_symbol) | |
5456 | ->X_add_symbol) | |
5457 | == now_seg))) | |
5458 | && breg != 0 | |
5459 | && (offset_expr.X_add_number == 0 | |
5460 | || OUTPUT_FLAVOR == bfd_target_elf_flavour)) | |
5461 | { | |
5462 | /* For this case, we output the instructions: | |
5463 | lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S) | |
5464 | addiu $tempreg,$tempreg,$breg | |
5465 | <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16) | |
5466 | If the relocation would fit entirely in 16 bits, it would be | |
5467 | nice to emit: | |
5468 | <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16) | |
5469 | instead, but that seems quite difficult. */ | |
5470 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
5471 | tempreg, (int) BFD_RELOC_PCREL_HI16_S); | |
5472 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5473 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
5474 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
5475 | ? "addu" : "daddu"), | |
5476 | "d,v,t", tempreg, tempreg, breg); | |
5477 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, treg, | |
5478 | (int) BFD_RELOC_PCREL_LO16, tempreg); | |
5479 | if (! used_at) | |
5480 | return; | |
5481 | break; | |
5482 | } | |
5483 | ||
252b5132 RH |
5484 | if (offset_expr.X_op != O_constant |
5485 | && offset_expr.X_op != O_symbol) | |
5486 | { | |
5487 | as_bad (_("expression too complex")); | |
5488 | offset_expr.X_op = O_constant; | |
5489 | } | |
5490 | ||
5491 | /* A constant expression in PIC code can be handled just as it | |
5492 | is in non PIC code. */ | |
5493 | if (mips_pic == NO_PIC | |
5494 | || offset_expr.X_op == O_constant) | |
5495 | { | |
f9419b05 TS |
5496 | char *p; |
5497 | ||
252b5132 RH |
5498 | /* If this is a reference to a GP relative symbol, and there |
5499 | is no base register, we want | |
cdf6fd85 | 5500 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
5501 | Otherwise, if there is no base register, we want |
5502 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5503 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5504 | If we have a constant, we need two instructions anyhow, | |
5505 | so we always use the latter form. | |
5506 | ||
5507 | If we have a base register, and this is a reference to a | |
5508 | GP relative symbol, we want | |
5509 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 5510 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
5511 | Otherwise we want |
5512 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5513 | addu $tempreg,$tempreg,$breg | |
5514 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 5515 | With a constant we always use the latter case. |
76b3015f | 5516 | |
d6bc6245 TS |
5517 | With 64bit address space and no base register and $at usable, |
5518 | we want | |
5519 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5520 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5521 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5522 | dsll32 $tempreg,0 | |
5523 | daddu $tempreg,$at | |
5524 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5525 | If we have a base register, we want | |
5526 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5527 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5528 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5529 | daddu $at,$breg | |
5530 | dsll32 $tempreg,0 | |
5531 | daddu $tempreg,$at | |
5532 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5533 | ||
5534 | Without $at we can't generate the optimal path for superscalar | |
5535 | processors here since this would require two temporary registers. | |
5536 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5537 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5538 | dsll $tempreg,16 | |
5539 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5540 | dsll $tempreg,16 | |
5541 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5542 | If we have a base register, we want | |
5543 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5544 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5545 | dsll $tempreg,16 | |
5546 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5547 | dsll $tempreg,16 | |
5548 | daddu $tempreg,$tempreg,$breg | |
5549 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 CD |
5550 | |
5551 | If we have 64-bit addresses, as an optimization, for | |
5552 | addresses which are 32-bit constants (e.g. kseg0/kseg1 | |
5553 | addresses) we fall back to the 32-bit address generation | |
78d32a17 MR |
5554 | mechanism since it is more efficient. Note that due to |
5555 | the signed offset used by memory operations, the 32-bit | |
5556 | range is shifted down by 32768 here. This code should | |
6373ee54 CD |
5557 | probably attempt to generate 64-bit constants more |
5558 | efficiently in general. | |
d6bc6245 | 5559 | */ |
6373ee54 CD |
5560 | if (HAVE_64BIT_ADDRESSES |
5561 | && !(offset_expr.X_op == O_constant | |
78d32a17 | 5562 | && IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000))) |
d6bc6245 TS |
5563 | { |
5564 | p = NULL; | |
5565 | ||
5566 | /* We don't do GP optimization for now because RELAX_ENCODE can't | |
5567 | hold the data for such large chunks. */ | |
5568 | ||
460597ba | 5569 | if (used_at == 0 && ! mips_opts.noat) |
d6bc6245 TS |
5570 | { |
5571 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
5572 | tempreg, (int) BFD_RELOC_MIPS_HIGHEST); | |
5573 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
5574 | AT, (int) BFD_RELOC_HI16_S); | |
5575 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
5576 | tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER); | |
5577 | if (breg != 0) | |
2396cfb9 TS |
5578 | macro_build (p, &icnt, (expressionS *) NULL, "daddu", |
5579 | "d,v,t", AT, AT, breg); | |
5580 | macro_build (p, &icnt, (expressionS *) NULL, "dsll32", | |
5581 | "d,w,<", tempreg, tempreg, 0); | |
5582 | macro_build (p, &icnt, (expressionS *) NULL, "daddu", | |
5583 | "d,v,t", tempreg, tempreg, AT); | |
d6bc6245 TS |
5584 | macro_build (p, &icnt, &offset_expr, s, |
5585 | fmt, treg, (int) BFD_RELOC_LO16, tempreg); | |
5586 | used_at = 1; | |
5587 | } | |
5588 | else | |
5589 | { | |
5590 | macro_build (p, &icnt, &offset_expr, "lui", "t,u", | |
5591 | tempreg, (int) BFD_RELOC_MIPS_HIGHEST); | |
5592 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", | |
5593 | tempreg, tempreg, (int) BFD_RELOC_MIPS_HIGHER); | |
2396cfb9 TS |
5594 | macro_build (p, &icnt, (expressionS *) NULL, "dsll", |
5595 | "d,w,<", tempreg, tempreg, 16); | |
d6bc6245 TS |
5596 | macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j", |
5597 | tempreg, tempreg, (int) BFD_RELOC_HI16_S); | |
2396cfb9 TS |
5598 | macro_build (p, &icnt, (expressionS *) NULL, "dsll", |
5599 | "d,w,<", tempreg, tempreg, 16); | |
d6bc6245 | 5600 | if (breg != 0) |
2396cfb9 TS |
5601 | macro_build (p, &icnt, (expressionS *) NULL, "daddu", |
5602 | "d,v,t", tempreg, tempreg, breg); | |
d6bc6245 TS |
5603 | macro_build (p, &icnt, &offset_expr, s, |
5604 | fmt, treg, (int) BFD_RELOC_LO16, tempreg); | |
5605 | } | |
5606 | ||
5607 | return; | |
5608 | } | |
76b3015f | 5609 | |
252b5132 RH |
5610 | if (breg == 0) |
5611 | { | |
e7d556df | 5612 | if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET |
252b5132 RH |
5613 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
5614 | p = NULL; | |
5615 | else | |
5616 | { | |
5617 | frag_grow (20); | |
5618 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
c9914766 TS |
5619 | treg, (int) BFD_RELOC_GPREL16, |
5620 | mips_gp_register); | |
252b5132 RH |
5621 | p = frag_var (rs_machine_dependent, 8, 0, |
5622 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
5623 | (mips_opts.warn_about_macros | |
5624 | || (used_at | |
5625 | && mips_opts.noat))), | |
956cd1d6 | 5626 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
5627 | used_at = 0; |
5628 | } | |
5629 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
5630 | if (p != NULL) | |
5631 | p += 4; | |
5632 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
5633 | (int) BFD_RELOC_LO16, tempreg); | |
5634 | } | |
5635 | else | |
5636 | { | |
e7d556df | 5637 | if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET |
252b5132 RH |
5638 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
5639 | p = NULL; | |
5640 | else | |
5641 | { | |
5642 | frag_grow (28); | |
5643 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5644 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
c9914766 | 5645 | "d,v,t", tempreg, breg, mips_gp_register); |
252b5132 | 5646 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
cdf6fd85 | 5647 | treg, (int) BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
5648 | p = frag_var (rs_machine_dependent, 12, 0, |
5649 | RELAX_ENCODE (8, 12, 0, 8, 0, 0), | |
956cd1d6 | 5650 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
5651 | } |
5652 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
5653 | if (p != NULL) | |
5654 | p += 4; | |
5655 | macro_build (p, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5656 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5657 | "d,v,t", tempreg, tempreg, breg); |
5658 | if (p != NULL) | |
5659 | p += 4; | |
5660 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
5661 | (int) BFD_RELOC_LO16, tempreg); | |
5662 | } | |
5663 | } | |
5664 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
5665 | { | |
f9419b05 | 5666 | char *p; |
ed6fb7bd | 5667 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 5668 | |
252b5132 RH |
5669 | /* If this is a reference to an external symbol, we want |
5670 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5671 | nop | |
5672 | <op> $treg,0($tempreg) | |
5673 | Otherwise we want | |
5674 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5675 | nop | |
5676 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5677 | <op> $treg,0($tempreg) | |
ed6fb7bd SC |
5678 | If we have NewABI, we want |
5679 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
252b5132 RH |
5680 | If there is a base register, we add it to $tempreg before |
5681 | the <op>. If there is a constant, we stick it in the | |
5682 | <op> instruction. We don't handle constants larger than | |
5683 | 16 bits, because we have no way to load the upper 16 bits | |
5684 | (actually, we could handle them for the subset of cases | |
5685 | in which we are not using $at). */ | |
5686 | assert (offset_expr.X_op == O_symbol); | |
5687 | expr1.X_add_number = offset_expr.X_add_number; | |
5688 | offset_expr.X_add_number = 0; | |
ed6fb7bd SC |
5689 | if (HAVE_NEWABI) |
5690 | lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_DISP; | |
252b5132 RH |
5691 | if (expr1.X_add_number < -0x8000 |
5692 | || expr1.X_add_number >= 0x8000) | |
5693 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5694 | frag_grow (20); | |
5695 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
c9914766 | 5696 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", tempreg, |
ed6fb7bd | 5697 | (int) lw_reloc_type, mips_gp_register); |
252b5132 | 5698 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); |
bdaaa2e1 | 5699 | p = frag_var (rs_machine_dependent, 4, 0, |
252b5132 | 5700 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), |
c4e7957c | 5701 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 | 5702 | macro_build (p, &icnt, &offset_expr, |
ca4e0257 | 5703 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
5704 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
5705 | if (breg != 0) | |
5706 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5707 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5708 | "d,v,t", tempreg, tempreg, breg); |
5709 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, | |
5710 | (int) BFD_RELOC_LO16, tempreg); | |
5711 | } | |
5712 | else if (mips_pic == SVR4_PIC) | |
5713 | { | |
5714 | int gpdel; | |
f9419b05 | 5715 | char *p; |
252b5132 RH |
5716 | |
5717 | /* If this is a reference to an external symbol, we want | |
5718 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5719 | addu $tempreg,$tempreg,$gp | |
5720 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5721 | <op> $treg,0($tempreg) | |
5722 | Otherwise we want | |
5723 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5724 | nop | |
5725 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5726 | <op> $treg,0($tempreg) | |
5727 | If there is a base register, we add it to $tempreg before | |
5728 | the <op>. If there is a constant, we stick it in the | |
5729 | <op> instruction. We don't handle constants larger than | |
5730 | 16 bits, because we have no way to load the upper 16 bits | |
5731 | (actually, we could handle them for the subset of cases | |
438c16b8 TS |
5732 | in which we are not using $at). |
5733 | ||
5734 | For NewABI, we want | |
5735 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
5736 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
5737 | <op> $treg,0($tempreg) | |
5738 | */ | |
252b5132 RH |
5739 | assert (offset_expr.X_op == O_symbol); |
5740 | expr1.X_add_number = offset_expr.X_add_number; | |
5741 | offset_expr.X_add_number = 0; | |
5742 | if (expr1.X_add_number < -0x8000 | |
5743 | || expr1.X_add_number >= 0x8000) | |
5744 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
438c16b8 TS |
5745 | if (HAVE_NEWABI) |
5746 | { | |
5747 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
5748 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", | |
5749 | "t,o(b)", tempreg, BFD_RELOC_MIPS_GOT_PAGE, | |
5750 | mips_gp_register); | |
5751 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
5752 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", | |
5753 | "t,r,j", tempreg, tempreg, | |
5754 | BFD_RELOC_MIPS_GOT_OFST); | |
5755 | if (breg != 0) | |
5756 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5757 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", | |
5758 | "d,v,t", tempreg, tempreg, breg); | |
5759 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, | |
5760 | (int) BFD_RELOC_LO16, tempreg); | |
5761 | ||
5762 | if (! used_at) | |
5763 | return; | |
5764 | ||
5765 | break; | |
5766 | } | |
f7ea7ef2 | 5767 | if (reg_needs_delay (mips_gp_register)) |
252b5132 RH |
5768 | gpdel = 4; |
5769 | else | |
5770 | gpdel = 0; | |
5771 | frag_grow (36); | |
5772 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
5773 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
5774 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5775 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
c9914766 | 5776 | "d,v,t", tempreg, tempreg, mips_gp_register); |
252b5132 | 5777 | macro_build ((char *) NULL, &icnt, &offset_expr, |
ca4e0257 | 5778 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
5779 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, |
5780 | tempreg); | |
5781 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
5782 | RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0), | |
c4e7957c | 5783 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
5784 | if (gpdel > 0) |
5785 | { | |
5786 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5787 | p += 4; | |
5788 | } | |
5789 | macro_build (p, &icnt, &offset_expr, | |
ca4e0257 | 5790 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
c9914766 TS |
5791 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, |
5792 | mips_gp_register); | |
252b5132 RH |
5793 | p += 4; |
5794 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5795 | p += 4; | |
5796 | macro_build (p, &icnt, &offset_expr, | |
ca4e0257 | 5797 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
252b5132 RH |
5798 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
5799 | if (breg != 0) | |
5800 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5801 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
5802 | "d,v,t", tempreg, tempreg, breg); |
5803 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, | |
5804 | (int) BFD_RELOC_LO16, tempreg); | |
5805 | } | |
5806 | else if (mips_pic == EMBEDDED_PIC) | |
5807 | { | |
5808 | /* If there is no base register, we want | |
cdf6fd85 | 5809 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
5810 | If there is a base register, we want |
5811 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 5812 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
5813 | */ |
5814 | assert (offset_expr.X_op == O_symbol); | |
5815 | if (breg == 0) | |
5816 | { | |
5817 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
c9914766 | 5818 | treg, (int) BFD_RELOC_GPREL16, mips_gp_register); |
252b5132 RH |
5819 | used_at = 0; |
5820 | } | |
5821 | else | |
5822 | { | |
5823 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 5824 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
c9914766 | 5825 | "d,v,t", tempreg, breg, mips_gp_register); |
252b5132 | 5826 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
cdf6fd85 | 5827 | treg, (int) BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
5828 | } |
5829 | } | |
5830 | else | |
5831 | abort (); | |
5832 | ||
5833 | if (! used_at) | |
5834 | return; | |
5835 | ||
5836 | break; | |
5837 | ||
5838 | case M_LI: | |
5839 | case M_LI_S: | |
5840 | load_register (&icnt, treg, &imm_expr, 0); | |
5841 | return; | |
5842 | ||
5843 | case M_DLI: | |
5844 | load_register (&icnt, treg, &imm_expr, 1); | |
5845 | return; | |
5846 | ||
5847 | case M_LI_SS: | |
5848 | if (imm_expr.X_op == O_constant) | |
5849 | { | |
5850 | load_register (&icnt, AT, &imm_expr, 0); | |
5851 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5852 | "mtc1", "t,G", AT, treg); | |
5853 | break; | |
5854 | } | |
5855 | else | |
5856 | { | |
5857 | assert (offset_expr.X_op == O_symbol | |
5858 | && strcmp (segment_name (S_GET_SEGMENT | |
5859 | (offset_expr.X_add_symbol)), | |
5860 | ".lit4") == 0 | |
5861 | && offset_expr.X_add_number == 0); | |
5862 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", | |
c9914766 | 5863 | treg, (int) BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
252b5132 RH |
5864 | return; |
5865 | } | |
5866 | ||
5867 | case M_LI_D: | |
ca4e0257 RS |
5868 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
5869 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
5870 | order 32 bits of the value and the low order 32 bits are either | |
5871 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
5872 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
5873 | { | |
ca4e0257 | 5874 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
5875 | load_register (&icnt, treg, &imm_expr, 1); |
5876 | else | |
5877 | { | |
5878 | int hreg, lreg; | |
5879 | ||
5880 | if (target_big_endian) | |
5881 | { | |
5882 | hreg = treg; | |
5883 | lreg = treg + 1; | |
5884 | } | |
5885 | else | |
5886 | { | |
5887 | hreg = treg + 1; | |
5888 | lreg = treg; | |
5889 | } | |
5890 | ||
5891 | if (hreg <= 31) | |
5892 | load_register (&icnt, hreg, &imm_expr, 0); | |
5893 | if (lreg <= 31) | |
5894 | { | |
5895 | if (offset_expr.X_op == O_absent) | |
ea1fb5dc | 5896 | move_register (&icnt, lreg, 0); |
252b5132 RH |
5897 | else |
5898 | { | |
5899 | assert (offset_expr.X_op == O_constant); | |
5900 | load_register (&icnt, lreg, &offset_expr, 0); | |
5901 | } | |
5902 | } | |
5903 | } | |
5904 | return; | |
5905 | } | |
5906 | ||
5907 | /* We know that sym is in the .rdata section. First we get the | |
5908 | upper 16 bits of the address. */ | |
5909 | if (mips_pic == NO_PIC) | |
5910 | { | |
956cd1d6 | 5911 | macro_build_lui (NULL, &icnt, &offset_expr, AT); |
252b5132 RH |
5912 | } |
5913 | else if (mips_pic == SVR4_PIC) | |
5914 | { | |
5915 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 5916 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
c9914766 TS |
5917 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, |
5918 | mips_gp_register); | |
252b5132 RH |
5919 | } |
5920 | else if (mips_pic == EMBEDDED_PIC) | |
5921 | { | |
5922 | /* For embedded PIC we pick up the entire address off $gp in | |
5923 | a single instruction. */ | |
5924 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
c9914766 TS |
5925 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", "t,r,j", AT, |
5926 | mips_gp_register, (int) BFD_RELOC_GPREL16); | |
252b5132 RH |
5927 | offset_expr.X_op = O_constant; |
5928 | offset_expr.X_add_number = 0; | |
5929 | } | |
5930 | else | |
5931 | abort (); | |
bdaaa2e1 | 5932 | |
252b5132 | 5933 | /* Now we load the register(s). */ |
ca4e0257 | 5934 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
5935 | macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)", |
5936 | treg, (int) BFD_RELOC_LO16, AT); | |
5937 | else | |
5938 | { | |
5939 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", | |
5940 | treg, (int) BFD_RELOC_LO16, AT); | |
f9419b05 | 5941 | if (treg != RA) |
252b5132 RH |
5942 | { |
5943 | /* FIXME: How in the world do we deal with the possible | |
5944 | overflow here? */ | |
5945 | offset_expr.X_add_number += 4; | |
5946 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", | |
5947 | treg + 1, (int) BFD_RELOC_LO16, AT); | |
5948 | } | |
5949 | } | |
5950 | ||
5951 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
5952 | does not become a variant frag. */ | |
5953 | frag_wane (frag_now); | |
5954 | frag_new (0); | |
5955 | ||
5956 | break; | |
5957 | ||
5958 | case M_LI_DD: | |
ca4e0257 RS |
5959 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
5960 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
5961 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
5962 | the value and the low order 32 bits are either zero or in | |
5963 | OFFSET_EXPR. */ | |
252b5132 RH |
5964 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
5965 | { | |
ca4e0257 RS |
5966 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_FPRS); |
5967 | if (HAVE_64BIT_FPRS) | |
5968 | { | |
5969 | assert (HAVE_64BIT_GPRS); | |
5970 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5971 | "dmtc1", "t,S", AT, treg); | |
5972 | } | |
252b5132 RH |
5973 | else |
5974 | { | |
5975 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5976 | "mtc1", "t,G", AT, treg + 1); | |
5977 | if (offset_expr.X_op == O_absent) | |
5978 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5979 | "mtc1", "t,G", 0, treg); | |
5980 | else | |
5981 | { | |
5982 | assert (offset_expr.X_op == O_constant); | |
5983 | load_register (&icnt, AT, &offset_expr, 0); | |
5984 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5985 | "mtc1", "t,G", AT, treg); | |
5986 | } | |
5987 | } | |
5988 | break; | |
5989 | } | |
5990 | ||
5991 | assert (offset_expr.X_op == O_symbol | |
5992 | && offset_expr.X_add_number == 0); | |
5993 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
5994 | if (strcmp (s, ".lit8") == 0) | |
5995 | { | |
e7af610e | 5996 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
5997 | { |
5998 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
c9914766 TS |
5999 | "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL, |
6000 | mips_gp_register); | |
252b5132 RH |
6001 | return; |
6002 | } | |
c9914766 | 6003 | breg = mips_gp_register; |
252b5132 RH |
6004 | r = BFD_RELOC_MIPS_LITERAL; |
6005 | goto dob; | |
6006 | } | |
6007 | else | |
6008 | { | |
6009 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); | |
6010 | if (mips_pic == SVR4_PIC) | |
6011 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
ca4e0257 | 6012 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
c9914766 TS |
6013 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, |
6014 | mips_gp_register); | |
252b5132 RH |
6015 | else |
6016 | { | |
6017 | /* FIXME: This won't work for a 64 bit address. */ | |
956cd1d6 | 6018 | macro_build_lui (NULL, &icnt, &offset_expr, AT); |
252b5132 | 6019 | } |
bdaaa2e1 | 6020 | |
e7af610e | 6021 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6022 | { |
6023 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
6024 | "T,o(b)", treg, (int) BFD_RELOC_LO16, AT); | |
6025 | ||
6026 | /* To avoid confusion in tc_gen_reloc, we must ensure | |
6027 | that this does not become a variant frag. */ | |
6028 | frag_wane (frag_now); | |
6029 | frag_new (0); | |
6030 | ||
6031 | break; | |
6032 | } | |
6033 | breg = AT; | |
6034 | r = BFD_RELOC_LO16; | |
6035 | goto dob; | |
6036 | } | |
6037 | ||
6038 | case M_L_DOB: | |
ec68c924 | 6039 | if (mips_arch == CPU_R4650) |
252b5132 RH |
6040 | { |
6041 | as_bad (_("opcode not supported on this processor")); | |
6042 | return; | |
6043 | } | |
6044 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6045 | to adjust when loading from memory. */ | |
6046 | r = BFD_RELOC_LO16; | |
6047 | dob: | |
e7af610e | 6048 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
6049 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
6050 | target_big_endian ? treg + 1 : treg, | |
6051 | (int) r, breg); | |
6052 | /* FIXME: A possible overflow which I don't know how to deal | |
6053 | with. */ | |
6054 | offset_expr.X_add_number += 4; | |
6055 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", | |
6056 | target_big_endian ? treg : treg + 1, | |
6057 | (int) r, breg); | |
6058 | ||
6059 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
6060 | does not become a variant frag. */ | |
6061 | frag_wane (frag_now); | |
6062 | frag_new (0); | |
6063 | ||
6064 | if (breg != AT) | |
6065 | return; | |
6066 | break; | |
6067 | ||
6068 | case M_L_DAB: | |
6069 | /* | |
6070 | * The MIPS assembler seems to check for X_add_number not | |
6071 | * being double aligned and generating: | |
6072 | * lui at,%hi(foo+1) | |
6073 | * addu at,at,v1 | |
6074 | * addiu at,at,%lo(foo+1) | |
6075 | * lwc1 f2,0(at) | |
6076 | * lwc1 f3,4(at) | |
6077 | * But, the resulting address is the same after relocation so why | |
6078 | * generate the extra instruction? | |
6079 | */ | |
ec68c924 | 6080 | if (mips_arch == CPU_R4650) |
252b5132 RH |
6081 | { |
6082 | as_bad (_("opcode not supported on this processor")); | |
6083 | return; | |
6084 | } | |
bdaaa2e1 | 6085 | /* Itbl support may require additional care here. */ |
252b5132 | 6086 | coproc = 1; |
e7af610e | 6087 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6088 | { |
6089 | s = "ldc1"; | |
6090 | goto ld; | |
6091 | } | |
6092 | ||
6093 | s = "lwc1"; | |
6094 | fmt = "T,o(b)"; | |
6095 | goto ldd_std; | |
6096 | ||
6097 | case M_S_DAB: | |
ec68c924 | 6098 | if (mips_arch == CPU_R4650) |
252b5132 RH |
6099 | { |
6100 | as_bad (_("opcode not supported on this processor")); | |
6101 | return; | |
6102 | } | |
6103 | ||
e7af610e | 6104 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6105 | { |
6106 | s = "sdc1"; | |
6107 | goto st; | |
6108 | } | |
6109 | ||
6110 | s = "swc1"; | |
6111 | fmt = "T,o(b)"; | |
bdaaa2e1 | 6112 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6113 | coproc = 1; |
6114 | goto ldd_std; | |
6115 | ||
6116 | case M_LD_AB: | |
ca4e0257 | 6117 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6118 | { |
6119 | s = "ld"; | |
6120 | goto ld; | |
6121 | } | |
6122 | ||
6123 | s = "lw"; | |
6124 | fmt = "t,o(b)"; | |
6125 | goto ldd_std; | |
6126 | ||
6127 | case M_SD_AB: | |
ca4e0257 | 6128 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6129 | { |
6130 | s = "sd"; | |
6131 | goto st; | |
6132 | } | |
6133 | ||
6134 | s = "sw"; | |
6135 | fmt = "t,o(b)"; | |
6136 | ||
6137 | ldd_std: | |
afdbd6d0 CD |
6138 | /* We do _not_ bother to allow embedded PIC (symbol-local_symbol) |
6139 | loads for the case of doing a pair of loads to simulate an 'ld'. | |
6140 | This is not currently done by the compiler, and assembly coders | |
6141 | writing embedded-pic code can cope. */ | |
6142 | ||
252b5132 RH |
6143 | if (offset_expr.X_op != O_symbol |
6144 | && offset_expr.X_op != O_constant) | |
6145 | { | |
6146 | as_bad (_("expression too complex")); | |
6147 | offset_expr.X_op = O_constant; | |
6148 | } | |
6149 | ||
6150 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6151 | to adjust when loading from memory. We set coproc if we must | |
6152 | load $fn+1 first. */ | |
bdaaa2e1 | 6153 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6154 | if (! target_big_endian) |
6155 | coproc = 0; | |
6156 | ||
6157 | if (mips_pic == NO_PIC | |
6158 | || offset_expr.X_op == O_constant) | |
6159 | { | |
f9419b05 TS |
6160 | char *p; |
6161 | ||
252b5132 | 6162 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 TS |
6163 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
6164 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6165 | If we have a base register, we use this |
6166 | addu $at,$breg,$gp | |
cdf6fd85 TS |
6167 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
6168 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6169 | If this is not a GP relative symbol, we want |
6170 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6171 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6172 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6173 | If there is a base register, we add it to $at after the | |
6174 | lui instruction. If there is a constant, we always use | |
6175 | the last case. */ | |
e7d556df | 6176 | if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET |
252b5132 RH |
6177 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
6178 | { | |
6179 | p = NULL; | |
6180 | used_at = 1; | |
6181 | } | |
6182 | else | |
6183 | { | |
6184 | int off; | |
6185 | ||
6186 | if (breg == 0) | |
6187 | { | |
6188 | frag_grow (28); | |
c9914766 | 6189 | tempreg = mips_gp_register; |
252b5132 RH |
6190 | off = 0; |
6191 | used_at = 0; | |
6192 | } | |
6193 | else | |
6194 | { | |
6195 | frag_grow (36); | |
6196 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6197 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
c9914766 | 6198 | "d,v,t", AT, breg, mips_gp_register); |
252b5132 RH |
6199 | tempreg = AT; |
6200 | off = 4; | |
6201 | used_at = 1; | |
6202 | } | |
6203 | ||
beae10d5 | 6204 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6205 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
6206 | coproc ? treg + 1 : treg, | |
cdf6fd85 | 6207 | (int) BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6208 | offset_expr.X_add_number += 4; |
6209 | ||
6210 | /* Set mips_optimize to 2 to avoid inserting an | |
6211 | undesired nop. */ | |
6212 | hold_mips_optimize = mips_optimize; | |
6213 | mips_optimize = 2; | |
beae10d5 | 6214 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6215 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
6216 | coproc ? treg : treg + 1, | |
cdf6fd85 | 6217 | (int) BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6218 | mips_optimize = hold_mips_optimize; |
6219 | ||
6220 | p = frag_var (rs_machine_dependent, 12 + off, 0, | |
6221 | RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1, | |
6222 | used_at && mips_opts.noat), | |
956cd1d6 | 6223 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
6224 | |
6225 | /* We just generated two relocs. When tc_gen_reloc | |
6226 | handles this case, it will skip the first reloc and | |
6227 | handle the second. The second reloc already has an | |
6228 | extra addend of 4, which we added above. We must | |
6229 | subtract it out, and then subtract another 4 to make | |
6230 | the first reloc come out right. The second reloc | |
6231 | will come out right because we are going to add 4 to | |
6232 | offset_expr when we build its instruction below. | |
6233 | ||
6234 | If we have a symbol, then we don't want to include | |
6235 | the offset, because it will wind up being included | |
6236 | when we generate the reloc. */ | |
6237 | ||
6238 | if (offset_expr.X_op == O_constant) | |
6239 | offset_expr.X_add_number -= 8; | |
6240 | else | |
6241 | { | |
6242 | offset_expr.X_add_number = -4; | |
6243 | offset_expr.X_op = O_constant; | |
6244 | } | |
6245 | } | |
6246 | macro_build_lui (p, &icnt, &offset_expr, AT); | |
6247 | if (p != NULL) | |
6248 | p += 4; | |
6249 | if (breg != 0) | |
6250 | { | |
6251 | macro_build (p, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6252 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
6253 | "d,v,t", AT, breg, AT); |
6254 | if (p != NULL) | |
6255 | p += 4; | |
6256 | } | |
beae10d5 | 6257 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6258 | macro_build (p, &icnt, &offset_expr, s, fmt, |
6259 | coproc ? treg + 1 : treg, | |
6260 | (int) BFD_RELOC_LO16, AT); | |
6261 | if (p != NULL) | |
6262 | p += 4; | |
6263 | /* FIXME: How do we handle overflow here? */ | |
6264 | offset_expr.X_add_number += 4; | |
beae10d5 | 6265 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6266 | macro_build (p, &icnt, &offset_expr, s, fmt, |
6267 | coproc ? treg : treg + 1, | |
6268 | (int) BFD_RELOC_LO16, AT); | |
bdaaa2e1 | 6269 | } |
252b5132 RH |
6270 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
6271 | { | |
6272 | int off; | |
6273 | ||
6274 | /* If this is a reference to an external symbol, we want | |
6275 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6276 | nop | |
6277 | <op> $treg,0($at) | |
6278 | <op> $treg+1,4($at) | |
6279 | Otherwise we want | |
6280 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6281 | nop | |
6282 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6283 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6284 | If there is a base register we add it to $at before the | |
6285 | lwc1 instructions. If there is a constant we include it | |
6286 | in the lwc1 instructions. */ | |
6287 | used_at = 1; | |
6288 | expr1.X_add_number = offset_expr.X_add_number; | |
6289 | offset_expr.X_add_number = 0; | |
6290 | if (expr1.X_add_number < -0x8000 | |
6291 | || expr1.X_add_number >= 0x8000 - 4) | |
6292 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6293 | if (breg == 0) | |
6294 | off = 0; | |
6295 | else | |
6296 | off = 4; | |
6297 | frag_grow (24 + off); | |
6298 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
c9914766 TS |
6299 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", "t,o(b)", AT, |
6300 | (int) BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
6301 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); |
6302 | if (breg != 0) | |
6303 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6304 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 | 6305 | "d,v,t", AT, breg, AT); |
beae10d5 | 6306 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6307 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
6308 | coproc ? treg + 1 : treg, | |
6309 | (int) BFD_RELOC_LO16, AT); | |
6310 | expr1.X_add_number += 4; | |
6311 | ||
6312 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6313 | nop. */ | |
6314 | hold_mips_optimize = mips_optimize; | |
6315 | mips_optimize = 2; | |
beae10d5 | 6316 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6317 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
6318 | coproc ? treg : treg + 1, | |
6319 | (int) BFD_RELOC_LO16, AT); | |
6320 | mips_optimize = hold_mips_optimize; | |
6321 | ||
6322 | (void) frag_var (rs_machine_dependent, 0, 0, | |
6323 | RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0), | |
c4e7957c | 6324 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
6325 | } |
6326 | else if (mips_pic == SVR4_PIC) | |
6327 | { | |
6328 | int gpdel, off; | |
f9419b05 | 6329 | char *p; |
252b5132 RH |
6330 | |
6331 | /* If this is a reference to an external symbol, we want | |
6332 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6333 | addu $at,$at,$gp | |
6334 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
6335 | nop | |
6336 | <op> $treg,0($at) | |
6337 | <op> $treg+1,4($at) | |
6338 | Otherwise we want | |
6339 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6340 | nop | |
6341 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6342 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6343 | If there is a base register we add it to $at before the | |
6344 | lwc1 instructions. If there is a constant we include it | |
6345 | in the lwc1 instructions. */ | |
6346 | used_at = 1; | |
6347 | expr1.X_add_number = offset_expr.X_add_number; | |
6348 | offset_expr.X_add_number = 0; | |
6349 | if (expr1.X_add_number < -0x8000 | |
6350 | || expr1.X_add_number >= 0x8000 - 4) | |
6351 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
c9914766 | 6352 | if (reg_needs_delay (mips_gp_register)) |
252b5132 RH |
6353 | gpdel = 4; |
6354 | else | |
6355 | gpdel = 0; | |
6356 | if (breg == 0) | |
6357 | off = 0; | |
6358 | else | |
6359 | off = 4; | |
6360 | frag_grow (56); | |
6361 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
6362 | AT, (int) BFD_RELOC_MIPS_GOT_HI16); | |
6363 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6364 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
c9914766 | 6365 | "d,v,t", AT, AT, mips_gp_register); |
252b5132 | 6366 | macro_build ((char *) NULL, &icnt, &offset_expr, |
ca4e0257 | 6367 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
252b5132 RH |
6368 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT); |
6369 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
6370 | if (breg != 0) | |
6371 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6372 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 | 6373 | "d,v,t", AT, breg, AT); |
beae10d5 | 6374 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6375 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
6376 | coproc ? treg + 1 : treg, | |
6377 | (int) BFD_RELOC_LO16, AT); | |
6378 | expr1.X_add_number += 4; | |
6379 | ||
6380 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6381 | nop. */ | |
6382 | hold_mips_optimize = mips_optimize; | |
6383 | mips_optimize = 2; | |
beae10d5 | 6384 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6385 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
6386 | coproc ? treg : treg + 1, | |
6387 | (int) BFD_RELOC_LO16, AT); | |
6388 | mips_optimize = hold_mips_optimize; | |
6389 | expr1.X_add_number -= 4; | |
6390 | ||
6391 | p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0, | |
6392 | RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel, | |
6393 | 8 + gpdel + off, 1, 0), | |
c4e7957c | 6394 | offset_expr.X_add_symbol, 0, NULL); |
252b5132 RH |
6395 | if (gpdel > 0) |
6396 | { | |
6397 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
6398 | p += 4; | |
6399 | } | |
6400 | macro_build (p, &icnt, &offset_expr, | |
ca4e0257 | 6401 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
c9914766 TS |
6402 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, |
6403 | mips_gp_register); | |
252b5132 RH |
6404 | p += 4; |
6405 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
6406 | p += 4; | |
6407 | if (breg != 0) | |
6408 | { | |
6409 | macro_build (p, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6410 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
6411 | "d,v,t", AT, breg, AT); |
6412 | p += 4; | |
6413 | } | |
beae10d5 | 6414 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6415 | macro_build (p, &icnt, &expr1, s, fmt, |
6416 | coproc ? treg + 1 : treg, | |
6417 | (int) BFD_RELOC_LO16, AT); | |
6418 | p += 4; | |
6419 | expr1.X_add_number += 4; | |
6420 | ||
6421 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6422 | nop. */ | |
6423 | hold_mips_optimize = mips_optimize; | |
6424 | mips_optimize = 2; | |
beae10d5 | 6425 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6426 | macro_build (p, &icnt, &expr1, s, fmt, |
6427 | coproc ? treg : treg + 1, | |
6428 | (int) BFD_RELOC_LO16, AT); | |
6429 | mips_optimize = hold_mips_optimize; | |
6430 | } | |
6431 | else if (mips_pic == EMBEDDED_PIC) | |
6432 | { | |
6433 | /* If there is no base register, we use | |
cdf6fd85 TS |
6434 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
6435 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6436 | If we have a base register, we use |
6437 | addu $at,$breg,$gp | |
cdf6fd85 TS |
6438 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
6439 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6440 | */ |
6441 | if (breg == 0) | |
6442 | { | |
c9914766 | 6443 | tempreg = mips_gp_register; |
252b5132 RH |
6444 | used_at = 0; |
6445 | } | |
6446 | else | |
6447 | { | |
6448 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 6449 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
c9914766 | 6450 | "d,v,t", AT, breg, mips_gp_register); |
252b5132 RH |
6451 | tempreg = AT; |
6452 | used_at = 1; | |
6453 | } | |
6454 | ||
beae10d5 | 6455 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6456 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
6457 | coproc ? treg + 1 : treg, | |
cdf6fd85 | 6458 | (int) BFD_RELOC_GPREL16, tempreg); |
252b5132 | 6459 | offset_expr.X_add_number += 4; |
beae10d5 | 6460 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6461 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
6462 | coproc ? treg : treg + 1, | |
cdf6fd85 | 6463 | (int) BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6464 | } |
6465 | else | |
6466 | abort (); | |
6467 | ||
6468 | if (! used_at) | |
6469 | return; | |
6470 | ||
6471 | break; | |
6472 | ||
6473 | case M_LD_OB: | |
6474 | s = "lw"; | |
6475 | goto sd_ob; | |
6476 | case M_SD_OB: | |
6477 | s = "sw"; | |
6478 | sd_ob: | |
ca4e0257 | 6479 | assert (HAVE_32BIT_ADDRESSES); |
252b5132 RH |
6480 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
6481 | (int) BFD_RELOC_LO16, breg); | |
6482 | offset_expr.X_add_number += 4; | |
6483 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1, | |
6484 | (int) BFD_RELOC_LO16, breg); | |
6485 | return; | |
6486 | ||
6487 | /* New code added to support COPZ instructions. | |
6488 | This code builds table entries out of the macros in mip_opcodes. | |
6489 | R4000 uses interlocks to handle coproc delays. | |
6490 | Other chips (like the R3000) require nops to be inserted for delays. | |
6491 | ||
f72c8c98 | 6492 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
6493 | In order to fill delay slots for non-interlocked chips, |
6494 | we must have a way to specify delays based on the coprocessor. | |
6495 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
6496 | What are the side-effects of the cop instruction? | |
6497 | What cache support might we have and what are its effects? | |
6498 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 6499 | What registers are read/set/modified? |
252b5132 RH |
6500 | |
6501 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 6502 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
6503 | |
6504 | case M_COP0: | |
6505 | s = "c0"; | |
6506 | goto copz; | |
6507 | case M_COP1: | |
6508 | s = "c1"; | |
6509 | goto copz; | |
6510 | case M_COP2: | |
6511 | s = "c2"; | |
6512 | goto copz; | |
6513 | case M_COP3: | |
6514 | s = "c3"; | |
6515 | copz: | |
6516 | /* For now we just do C (same as Cz). The parameter will be | |
6517 | stored in insn_opcode by mips_ip. */ | |
6518 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "C", | |
6519 | ip->insn_opcode); | |
6520 | return; | |
6521 | ||
ea1fb5dc RS |
6522 | case M_MOVE: |
6523 | move_register (&icnt, dreg, sreg); | |
6524 | return; | |
6525 | ||
252b5132 RH |
6526 | #ifdef LOSING_COMPILER |
6527 | default: | |
6528 | /* Try and see if this is a new itbl instruction. | |
6529 | This code builds table entries out of the macros in mip_opcodes. | |
6530 | FIXME: For now we just assemble the expression and pass it's | |
6531 | value along as a 32-bit immediate. | |
bdaaa2e1 | 6532 | We may want to have the assembler assemble this value, |
252b5132 RH |
6533 | so that we gain the assembler's knowledge of delay slots, |
6534 | symbols, etc. | |
6535 | Would it be more efficient to use mask (id) here? */ | |
bdaaa2e1 | 6536 | if (itbl_have_entries |
252b5132 | 6537 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
beae10d5 | 6538 | { |
252b5132 RH |
6539 | s = ip->insn_mo->name; |
6540 | s2 = "cop3"; | |
6541 | coproc = ITBL_DECODE_PNUM (immed_expr);; | |
6542 | macro_build ((char *) NULL, &icnt, &immed_expr, s, "C"); | |
6543 | return; | |
beae10d5 | 6544 | } |
252b5132 RH |
6545 | macro2 (ip); |
6546 | return; | |
6547 | } | |
6548 | if (mips_opts.noat) | |
6549 | as_warn (_("Macro used $at after \".set noat\"")); | |
6550 | } | |
bdaaa2e1 | 6551 | |
252b5132 RH |
6552 | static void |
6553 | macro2 (ip) | |
6554 | struct mips_cl_insn *ip; | |
6555 | { | |
6556 | register int treg, sreg, dreg, breg; | |
6557 | int tempreg; | |
6558 | int mask; | |
6559 | int icnt = 0; | |
6560 | int used_at; | |
6561 | expressionS expr1; | |
6562 | const char *s; | |
6563 | const char *s2; | |
6564 | const char *fmt; | |
6565 | int likely = 0; | |
6566 | int dbl = 0; | |
6567 | int coproc = 0; | |
6568 | int lr = 0; | |
6569 | int imm = 0; | |
6570 | int off; | |
6571 | offsetT maxnum; | |
6572 | bfd_reloc_code_real_type r; | |
6573 | char *p; | |
bdaaa2e1 | 6574 | |
252b5132 RH |
6575 | treg = (ip->insn_opcode >> 16) & 0x1f; |
6576 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
6577 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
6578 | mask = ip->insn_mo->mask; | |
bdaaa2e1 | 6579 | |
252b5132 RH |
6580 | expr1.X_op = O_constant; |
6581 | expr1.X_op_symbol = NULL; | |
6582 | expr1.X_add_symbol = NULL; | |
6583 | expr1.X_add_number = 1; | |
bdaaa2e1 | 6584 | |
252b5132 RH |
6585 | switch (mask) |
6586 | { | |
6587 | #endif /* LOSING_COMPILER */ | |
6588 | ||
6589 | case M_DMUL: | |
6590 | dbl = 1; | |
6591 | case M_MUL: | |
2396cfb9 TS |
6592 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
6593 | dbl ? "dmultu" : "multu", "s,t", sreg, treg); | |
6594 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", | |
6595 | dreg); | |
252b5132 RH |
6596 | return; |
6597 | ||
6598 | case M_DMUL_I: | |
6599 | dbl = 1; | |
6600 | case M_MUL_I: | |
6601 | /* The MIPS assembler some times generates shifts and adds. I'm | |
6602 | not trying to be that fancy. GCC should do this for us | |
6603 | anyway. */ | |
6604 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 | 6605 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 6606 | dbl ? "dmult" : "mult", "s,t", sreg, AT); |
2396cfb9 TS |
6607 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", |
6608 | dreg); | |
252b5132 RH |
6609 | break; |
6610 | ||
6611 | case M_DMULO_I: | |
6612 | dbl = 1; | |
6613 | case M_MULO_I: | |
6614 | imm = 1; | |
6615 | goto do_mulo; | |
6616 | ||
6617 | case M_DMULO: | |
6618 | dbl = 1; | |
6619 | case M_MULO: | |
6620 | do_mulo: | |
6621 | mips_emit_delays (true); | |
6622 | ++mips_opts.noreorder; | |
6623 | mips_any_noreorder = 1; | |
6624 | if (imm) | |
6625 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 | 6626 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 6627 | dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); |
2396cfb9 TS |
6628 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", |
6629 | dreg); | |
6630 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
f9419b05 | 6631 | dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA); |
2396cfb9 TS |
6632 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mfhi", "d", |
6633 | AT); | |
252b5132 | 6634 | if (mips_trap) |
9bd7d936 MR |
6635 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "tne", |
6636 | "s,t,q", dreg, AT, 6); | |
252b5132 RH |
6637 | else |
6638 | { | |
6639 | expr1.X_add_number = 8; | |
2396cfb9 TS |
6640 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg, |
6641 | AT); | |
6642 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "", | |
6643 | 0); | |
6644 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", | |
6645 | "c", 6); | |
252b5132 RH |
6646 | } |
6647 | --mips_opts.noreorder; | |
2396cfb9 | 6648 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", dreg); |
252b5132 RH |
6649 | break; |
6650 | ||
6651 | case M_DMULOU_I: | |
6652 | dbl = 1; | |
6653 | case M_MULOU_I: | |
6654 | imm = 1; | |
6655 | goto do_mulou; | |
6656 | ||
6657 | case M_DMULOU: | |
6658 | dbl = 1; | |
6659 | case M_MULOU: | |
6660 | do_mulou: | |
6661 | mips_emit_delays (true); | |
6662 | ++mips_opts.noreorder; | |
6663 | mips_any_noreorder = 1; | |
6664 | if (imm) | |
6665 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 | 6666 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
252b5132 RH |
6667 | dbl ? "dmultu" : "multu", |
6668 | "s,t", sreg, imm ? AT : treg); | |
2396cfb9 TS |
6669 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mfhi", "d", |
6670 | AT); | |
6671 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "d", | |
6672 | dreg); | |
252b5132 | 6673 | if (mips_trap) |
9bd7d936 MR |
6674 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "tne", |
6675 | "s,t,q", AT, 0, 6); | |
252b5132 RH |
6676 | else |
6677 | { | |
6678 | expr1.X_add_number = 8; | |
6679 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0); | |
2396cfb9 TS |
6680 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "", |
6681 | 0); | |
6682 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", | |
6683 | "c", 6); | |
252b5132 RH |
6684 | } |
6685 | --mips_opts.noreorder; | |
6686 | break; | |
6687 | ||
771c7ce4 TS |
6688 | case M_DROL: |
6689 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu", | |
6690 | "d,v,t", AT, 0, treg); | |
6691 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv", | |
6692 | "d,t,s", AT, sreg, AT); | |
6693 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv", | |
6694 | "d,t,s", dreg, sreg, treg); | |
6695 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
6696 | "d,v,t", dreg, dreg, AT); | |
6697 | break; | |
6698 | ||
252b5132 | 6699 | case M_ROL: |
2396cfb9 TS |
6700 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu", |
6701 | "d,v,t", AT, 0, treg); | |
6702 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srlv", | |
6703 | "d,t,s", AT, sreg, AT); | |
6704 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sllv", | |
6705 | "d,t,s", dreg, sreg, treg); | |
6706 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
6707 | "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
6708 | break; |
6709 | ||
771c7ce4 TS |
6710 | case M_DROL_I: |
6711 | { | |
6712 | unsigned int rot; | |
771c7ce4 TS |
6713 | |
6714 | if (imm_expr.X_op != O_constant) | |
6715 | as_bad (_("rotate count too large")); | |
6716 | rot = imm_expr.X_add_number & 0x3f; | |
483fc7cd RS |
6717 | if (rot == 0) |
6718 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrl", | |
6719 | "d,w,<", dreg, sreg, 0); | |
6720 | else | |
6721 | { | |
6722 | char *l, *r; | |
6723 | ||
6724 | l = (rot < 0x20) ? "dsll" : "dsll32"; | |
6725 | r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; | |
6726 | rot &= 0x1f; | |
6727 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l, | |
6728 | "d,w,<", AT, sreg, rot); | |
6729 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r, | |
6730 | "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
6731 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
6732 | "d,v,t", dreg, dreg, AT); | |
6733 | } | |
771c7ce4 TS |
6734 | } |
6735 | break; | |
6736 | ||
252b5132 | 6737 | case M_ROL_I: |
771c7ce4 TS |
6738 | { |
6739 | unsigned int rot; | |
6740 | ||
6741 | if (imm_expr.X_op != O_constant) | |
6742 | as_bad (_("rotate count too large")); | |
6743 | rot = imm_expr.X_add_number & 0x1f; | |
483fc7cd RS |
6744 | if (rot == 0) |
6745 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", | |
6746 | "d,w,<", dreg, sreg, 0); | |
6747 | else | |
6748 | { | |
6749 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", | |
6750 | "d,w,<", AT, sreg, rot); | |
6751 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", | |
6752 | "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
6753 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
6754 | "d,v,t", dreg, dreg, AT); | |
6755 | } | |
771c7ce4 TS |
6756 | } |
6757 | break; | |
6758 | ||
6759 | case M_DROR: | |
6760 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsubu", | |
6761 | "d,v,t", AT, 0, treg); | |
6762 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsllv", | |
6763 | "d,t,s", AT, sreg, AT); | |
6764 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrlv", | |
6765 | "d,t,s", dreg, sreg, treg); | |
6766 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
6767 | "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
6768 | break; |
6769 | ||
6770 | case M_ROR: | |
2396cfb9 TS |
6771 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "subu", |
6772 | "d,v,t", AT, 0, treg); | |
6773 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sllv", | |
6774 | "d,t,s", AT, sreg, AT); | |
6775 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srlv", | |
6776 | "d,t,s", dreg, sreg, treg); | |
6777 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
6778 | "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
6779 | break; |
6780 | ||
771c7ce4 TS |
6781 | case M_DROR_I: |
6782 | { | |
6783 | unsigned int rot; | |
771c7ce4 TS |
6784 | |
6785 | if (imm_expr.X_op != O_constant) | |
6786 | as_bad (_("rotate count too large")); | |
6787 | rot = imm_expr.X_add_number & 0x3f; | |
483fc7cd RS |
6788 | if (rot == 0) |
6789 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrl", | |
6790 | "d,w,<", dreg, sreg, 0); | |
6791 | else | |
6792 | { | |
6793 | char *l, *r; | |
6794 | ||
6795 | r = (rot < 0x20) ? "dsrl" : "dsrl32"; | |
6796 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; | |
6797 | rot &= 0x1f; | |
6798 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r, | |
6799 | "d,w,<", AT, sreg, rot); | |
6800 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l, | |
6801 | "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
6802 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
6803 | "d,v,t", dreg, dreg, AT); | |
6804 | } | |
771c7ce4 TS |
6805 | } |
6806 | break; | |
6807 | ||
252b5132 | 6808 | case M_ROR_I: |
771c7ce4 TS |
6809 | { |
6810 | unsigned int rot; | |
6811 | ||
6812 | if (imm_expr.X_op != O_constant) | |
6813 | as_bad (_("rotate count too large")); | |
6814 | rot = imm_expr.X_add_number & 0x1f; | |
483fc7cd RS |
6815 | if (rot == 0) |
6816 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", | |
6817 | "d,w,<", dreg, sreg, 0); | |
6818 | else | |
6819 | { | |
6820 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", | |
6821 | "d,w,<", AT, sreg, rot); | |
6822 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", | |
6823 | "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
6824 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", | |
6825 | "d,v,t", dreg, dreg, AT); | |
6826 | } | |
771c7ce4 | 6827 | } |
252b5132 RH |
6828 | break; |
6829 | ||
6830 | case M_S_DOB: | |
ec68c924 | 6831 | if (mips_arch == CPU_R4650) |
252b5132 RH |
6832 | { |
6833 | as_bad (_("opcode not supported on this processor")); | |
6834 | return; | |
6835 | } | |
e7af610e | 6836 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
6837 | /* Even on a big endian machine $fn comes before $fn+1. We have |
6838 | to adjust when storing to memory. */ | |
6839 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", | |
6840 | target_big_endian ? treg + 1 : treg, | |
6841 | (int) BFD_RELOC_LO16, breg); | |
6842 | offset_expr.X_add_number += 4; | |
6843 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", | |
6844 | target_big_endian ? treg : treg + 1, | |
6845 | (int) BFD_RELOC_LO16, breg); | |
6846 | return; | |
6847 | ||
6848 | case M_SEQ: | |
6849 | if (sreg == 0) | |
6850 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
6851 | treg, (int) BFD_RELOC_LO16); | |
6852 | else if (treg == 0) | |
6853 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
6854 | sreg, (int) BFD_RELOC_LO16); | |
6855 | else | |
6856 | { | |
2396cfb9 TS |
6857 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor", |
6858 | "d,v,t", dreg, sreg, treg); | |
252b5132 RH |
6859 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
6860 | dreg, (int) BFD_RELOC_LO16); | |
6861 | } | |
6862 | return; | |
6863 | ||
6864 | case M_SEQ_I: | |
6865 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6866 | { | |
6867 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
6868 | sreg, (int) BFD_RELOC_LO16); | |
6869 | return; | |
6870 | } | |
6871 | if (sreg == 0) | |
6872 | { | |
6873 | as_warn (_("Instruction %s: result is always false"), | |
6874 | ip->insn_mo->name); | |
ea1fb5dc | 6875 | move_register (&icnt, dreg, 0); |
252b5132 RH |
6876 | return; |
6877 | } | |
6878 | if (imm_expr.X_op == O_constant | |
6879 | && imm_expr.X_add_number >= 0 | |
6880 | && imm_expr.X_add_number < 0x10000) | |
6881 | { | |
6882 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, | |
6883 | sreg, (int) BFD_RELOC_LO16); | |
6884 | used_at = 0; | |
6885 | } | |
6886 | else if (imm_expr.X_op == O_constant | |
6887 | && imm_expr.X_add_number > -0x8000 | |
6888 | && imm_expr.X_add_number < 0) | |
6889 | { | |
6890 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
6891 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
ca4e0257 | 6892 | HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
252b5132 RH |
6893 | "t,r,j", dreg, sreg, |
6894 | (int) BFD_RELOC_LO16); | |
6895 | used_at = 0; | |
6896 | } | |
6897 | else | |
6898 | { | |
4d34fb5f | 6899 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
6900 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor", |
6901 | "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
6902 | used_at = 1; |
6903 | } | |
6904 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg, | |
6905 | (int) BFD_RELOC_LO16); | |
6906 | if (used_at) | |
6907 | break; | |
6908 | return; | |
6909 | ||
6910 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
6911 | s = "slt"; | |
6912 | goto sge; | |
6913 | case M_SGEU: | |
6914 | s = "sltu"; | |
6915 | sge: | |
2396cfb9 TS |
6916 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t", |
6917 | dreg, sreg, treg); | |
252b5132 RH |
6918 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
6919 | (int) BFD_RELOC_LO16); | |
6920 | return; | |
6921 | ||
6922 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
6923 | case M_SGEU_I: | |
6924 | if (imm_expr.X_op == O_constant | |
6925 | && imm_expr.X_add_number >= -0x8000 | |
6926 | && imm_expr.X_add_number < 0x8000) | |
6927 | { | |
6928 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
6929 | mask == M_SGE_I ? "slti" : "sltiu", | |
6930 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); | |
6931 | used_at = 0; | |
6932 | } | |
6933 | else | |
6934 | { | |
4d34fb5f | 6935 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
6936 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
6937 | mask == M_SGE_I ? "slt" : "sltu", "d,v,t", dreg, sreg, | |
6938 | AT); | |
252b5132 RH |
6939 | used_at = 1; |
6940 | } | |
6941 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
6942 | (int) BFD_RELOC_LO16); | |
6943 | if (used_at) | |
6944 | break; | |
6945 | return; | |
6946 | ||
6947 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
6948 | s = "slt"; | |
6949 | goto sgt; | |
6950 | case M_SGTU: | |
6951 | s = "sltu"; | |
6952 | sgt: | |
2396cfb9 TS |
6953 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t", |
6954 | dreg, treg, sreg); | |
252b5132 RH |
6955 | return; |
6956 | ||
6957 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
6958 | s = "slt"; | |
6959 | goto sgti; | |
6960 | case M_SGTU_I: | |
6961 | s = "sltu"; | |
6962 | sgti: | |
4d34fb5f | 6963 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
6964 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t", |
6965 | dreg, AT, sreg); | |
252b5132 RH |
6966 | break; |
6967 | ||
2396cfb9 | 6968 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
6969 | s = "slt"; |
6970 | goto sle; | |
6971 | case M_SLEU: | |
6972 | s = "sltu"; | |
6973 | sle: | |
2396cfb9 TS |
6974 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t", |
6975 | dreg, treg, sreg); | |
252b5132 RH |
6976 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
6977 | (int) BFD_RELOC_LO16); | |
6978 | return; | |
6979 | ||
2396cfb9 | 6980 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
6981 | s = "slt"; |
6982 | goto slei; | |
6983 | case M_SLEU_I: | |
6984 | s = "sltu"; | |
6985 | slei: | |
4d34fb5f | 6986 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
6987 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "d,v,t", |
6988 | dreg, AT, sreg); | |
252b5132 RH |
6989 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
6990 | (int) BFD_RELOC_LO16); | |
6991 | break; | |
6992 | ||
6993 | case M_SLT_I: | |
6994 | if (imm_expr.X_op == O_constant | |
6995 | && imm_expr.X_add_number >= -0x8000 | |
6996 | && imm_expr.X_add_number < 0x8000) | |
6997 | { | |
6998 | macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j", | |
6999 | dreg, sreg, (int) BFD_RELOC_LO16); | |
7000 | return; | |
7001 | } | |
4d34fb5f | 7002 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
7003 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "slt", "d,v,t", |
7004 | dreg, sreg, AT); | |
252b5132 RH |
7005 | break; |
7006 | ||
7007 | case M_SLTU_I: | |
7008 | if (imm_expr.X_op == O_constant | |
7009 | && imm_expr.X_add_number >= -0x8000 | |
7010 | && imm_expr.X_add_number < 0x8000) | |
7011 | { | |
7012 | macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j", | |
7013 | dreg, sreg, (int) BFD_RELOC_LO16); | |
7014 | return; | |
7015 | } | |
4d34fb5f | 7016 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
7017 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
7018 | "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7019 | break; |
7020 | ||
7021 | case M_SNE: | |
7022 | if (sreg == 0) | |
2396cfb9 TS |
7023 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
7024 | "d,v,t", dreg, 0, treg); | |
252b5132 | 7025 | else if (treg == 0) |
2396cfb9 TS |
7026 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
7027 | "d,v,t", dreg, 0, sreg); | |
252b5132 RH |
7028 | else |
7029 | { | |
2396cfb9 TS |
7030 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor", |
7031 | "d,v,t", dreg, sreg, treg); | |
7032 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", | |
7033 | "d,v,t", dreg, 0, dreg); | |
252b5132 RH |
7034 | } |
7035 | return; | |
7036 | ||
7037 | case M_SNE_I: | |
7038 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7039 | { | |
2396cfb9 TS |
7040 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
7041 | "d,v,t", dreg, 0, sreg); | |
252b5132 RH |
7042 | return; |
7043 | } | |
7044 | if (sreg == 0) | |
7045 | { | |
7046 | as_warn (_("Instruction %s: result is always true"), | |
7047 | ip->insn_mo->name); | |
7048 | macro_build ((char *) NULL, &icnt, &expr1, | |
ca4e0257 | 7049 | HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
252b5132 RH |
7050 | "t,r,j", dreg, 0, (int) BFD_RELOC_LO16); |
7051 | return; | |
7052 | } | |
7053 | if (imm_expr.X_op == O_constant | |
7054 | && imm_expr.X_add_number >= 0 | |
7055 | && imm_expr.X_add_number < 0x10000) | |
7056 | { | |
7057 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", | |
7058 | dreg, sreg, (int) BFD_RELOC_LO16); | |
7059 | used_at = 0; | |
7060 | } | |
7061 | else if (imm_expr.X_op == O_constant | |
7062 | && imm_expr.X_add_number > -0x8000 | |
7063 | && imm_expr.X_add_number < 0) | |
7064 | { | |
7065 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
7066 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
ca4e0257 | 7067 | HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
252b5132 RH |
7068 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
7069 | used_at = 0; | |
7070 | } | |
7071 | else | |
7072 | { | |
4d34fb5f | 7073 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
7074 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "xor", |
7075 | "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7076 | used_at = 1; |
7077 | } | |
2396cfb9 TS |
7078 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sltu", |
7079 | "d,v,t", dreg, 0, dreg); | |
252b5132 RH |
7080 | if (used_at) |
7081 | break; | |
7082 | return; | |
7083 | ||
7084 | case M_DSUB_I: | |
7085 | dbl = 1; | |
7086 | case M_SUB_I: | |
7087 | if (imm_expr.X_op == O_constant | |
7088 | && imm_expr.X_add_number > -0x8000 | |
7089 | && imm_expr.X_add_number <= 0x8000) | |
7090 | { | |
7091 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
7092 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
7093 | dbl ? "daddi" : "addi", | |
7094 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); | |
7095 | return; | |
7096 | } | |
7097 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 | 7098 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 7099 | dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT); |
252b5132 RH |
7100 | break; |
7101 | ||
7102 | case M_DSUBU_I: | |
7103 | dbl = 1; | |
7104 | case M_SUBU_I: | |
7105 | if (imm_expr.X_op == O_constant | |
7106 | && imm_expr.X_add_number > -0x8000 | |
7107 | && imm_expr.X_add_number <= 0x8000) | |
7108 | { | |
7109 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
7110 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
7111 | dbl ? "daddiu" : "addiu", | |
7112 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); | |
7113 | return; | |
7114 | } | |
7115 | load_register (&icnt, AT, &imm_expr, dbl); | |
2396cfb9 | 7116 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 7117 | dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT); |
252b5132 RH |
7118 | break; |
7119 | ||
7120 | case M_TEQ_I: | |
7121 | s = "teq"; | |
7122 | goto trap; | |
7123 | case M_TGE_I: | |
7124 | s = "tge"; | |
7125 | goto trap; | |
7126 | case M_TGEU_I: | |
7127 | s = "tgeu"; | |
7128 | goto trap; | |
7129 | case M_TLT_I: | |
7130 | s = "tlt"; | |
7131 | goto trap; | |
7132 | case M_TLTU_I: | |
7133 | s = "tltu"; | |
7134 | goto trap; | |
7135 | case M_TNE_I: | |
7136 | s = "tne"; | |
7137 | trap: | |
4d34fb5f | 7138 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS); |
2396cfb9 TS |
7139 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "s,t", sreg, |
7140 | AT); | |
252b5132 RH |
7141 | break; |
7142 | ||
252b5132 | 7143 | case M_TRUNCWS: |
43841e91 | 7144 | case M_TRUNCWD: |
e7af610e | 7145 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
7146 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
7147 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
7148 | ||
7149 | /* | |
7150 | * Is the double cfc1 instruction a bug in the mips assembler; | |
7151 | * or is there a reason for it? | |
7152 | */ | |
7153 | mips_emit_delays (true); | |
7154 | ++mips_opts.noreorder; | |
7155 | mips_any_noreorder = 1; | |
2396cfb9 | 7156 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "cfc1", "t,G", |
f9419b05 | 7157 | treg, RA); |
2396cfb9 | 7158 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "cfc1", "t,G", |
f9419b05 | 7159 | treg, RA); |
2396cfb9 | 7160 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); |
252b5132 RH |
7161 | expr1.X_add_number = 3; |
7162 | macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg, | |
7163 | (int) BFD_RELOC_LO16); | |
7164 | expr1.X_add_number = 2; | |
7165 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT, | |
7166 | (int) BFD_RELOC_LO16); | |
2396cfb9 | 7167 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "ctc1", "t,G", |
f9419b05 | 7168 | AT, RA); |
2396cfb9 TS |
7169 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); |
7170 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
252b5132 | 7171 | mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg); |
2396cfb9 | 7172 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "ctc1", "t,G", |
f9419b05 | 7173 | treg, RA); |
2396cfb9 | 7174 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); |
252b5132 RH |
7175 | --mips_opts.noreorder; |
7176 | break; | |
7177 | ||
7178 | case M_ULH: | |
7179 | s = "lb"; | |
7180 | goto ulh; | |
7181 | case M_ULHU: | |
7182 | s = "lbu"; | |
7183 | ulh: | |
7184 | if (offset_expr.X_add_number >= 0x7fff) | |
7185 | as_bad (_("operand overflow")); | |
7186 | /* avoid load delay */ | |
7187 | if (! target_big_endian) | |
f9419b05 | 7188 | ++offset_expr.X_add_number; |
252b5132 RH |
7189 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
7190 | (int) BFD_RELOC_LO16, breg); | |
7191 | if (! target_big_endian) | |
f9419b05 | 7192 | --offset_expr.X_add_number; |
252b5132 | 7193 | else |
f9419b05 | 7194 | ++offset_expr.X_add_number; |
252b5132 RH |
7195 | macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT, |
7196 | (int) BFD_RELOC_LO16, breg); | |
2396cfb9 TS |
7197 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<", |
7198 | treg, treg, 8); | |
7199 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t", | |
7200 | treg, treg, AT); | |
252b5132 RH |
7201 | break; |
7202 | ||
7203 | case M_ULD: | |
7204 | s = "ldl"; | |
7205 | s2 = "ldr"; | |
7206 | off = 7; | |
7207 | goto ulw; | |
7208 | case M_ULW: | |
7209 | s = "lwl"; | |
7210 | s2 = "lwr"; | |
7211 | off = 3; | |
7212 | ulw: | |
7213 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7214 | as_bad (_("operand overflow")); | |
7215 | if (! target_big_endian) | |
7216 | offset_expr.X_add_number += off; | |
7217 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
7218 | (int) BFD_RELOC_LO16, breg); | |
7219 | if (! target_big_endian) | |
7220 | offset_expr.X_add_number -= off; | |
7221 | else | |
7222 | offset_expr.X_add_number += off; | |
7223 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
7224 | (int) BFD_RELOC_LO16, breg); | |
7225 | return; | |
7226 | ||
7227 | case M_ULD_A: | |
7228 | s = "ldl"; | |
7229 | s2 = "ldr"; | |
7230 | off = 7; | |
7231 | goto ulwa; | |
7232 | case M_ULW_A: | |
7233 | s = "lwl"; | |
7234 | s2 = "lwr"; | |
7235 | off = 3; | |
7236 | ulwa: | |
d6bc6245 | 7237 | used_at = 1; |
c9914766 | 7238 | load_address (&icnt, AT, &offset_expr, &used_at); |
252b5132 RH |
7239 | if (breg != 0) |
7240 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 7241 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
7242 | "d,v,t", AT, AT, breg); |
7243 | if (! target_big_endian) | |
7244 | expr1.X_add_number = off; | |
7245 | else | |
7246 | expr1.X_add_number = 0; | |
7247 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
7248 | (int) BFD_RELOC_LO16, AT); | |
7249 | if (! target_big_endian) | |
7250 | expr1.X_add_number = 0; | |
7251 | else | |
7252 | expr1.X_add_number = off; | |
7253 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
7254 | (int) BFD_RELOC_LO16, AT); | |
7255 | break; | |
7256 | ||
7257 | case M_ULH_A: | |
7258 | case M_ULHU_A: | |
d6bc6245 | 7259 | used_at = 1; |
c9914766 | 7260 | load_address (&icnt, AT, &offset_expr, &used_at); |
252b5132 RH |
7261 | if (breg != 0) |
7262 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 7263 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
7264 | "d,v,t", AT, AT, breg); |
7265 | if (target_big_endian) | |
7266 | expr1.X_add_number = 0; | |
7267 | macro_build ((char *) NULL, &icnt, &expr1, | |
7268 | mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg, | |
7269 | (int) BFD_RELOC_LO16, AT); | |
7270 | if (target_big_endian) | |
7271 | expr1.X_add_number = 1; | |
7272 | else | |
7273 | expr1.X_add_number = 0; | |
7274 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
7275 | (int) BFD_RELOC_LO16, AT); | |
2396cfb9 TS |
7276 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<", |
7277 | treg, treg, 8); | |
7278 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t", | |
7279 | treg, treg, AT); | |
252b5132 RH |
7280 | break; |
7281 | ||
7282 | case M_USH: | |
7283 | if (offset_expr.X_add_number >= 0x7fff) | |
7284 | as_bad (_("operand overflow")); | |
7285 | if (target_big_endian) | |
f9419b05 | 7286 | ++offset_expr.X_add_number; |
252b5132 RH |
7287 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg, |
7288 | (int) BFD_RELOC_LO16, breg); | |
2396cfb9 TS |
7289 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<", |
7290 | AT, treg, 8); | |
252b5132 | 7291 | if (target_big_endian) |
f9419b05 | 7292 | --offset_expr.X_add_number; |
252b5132 | 7293 | else |
f9419b05 | 7294 | ++offset_expr.X_add_number; |
252b5132 RH |
7295 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT, |
7296 | (int) BFD_RELOC_LO16, breg); | |
7297 | break; | |
7298 | ||
7299 | case M_USD: | |
7300 | s = "sdl"; | |
7301 | s2 = "sdr"; | |
7302 | off = 7; | |
7303 | goto usw; | |
7304 | case M_USW: | |
7305 | s = "swl"; | |
7306 | s2 = "swr"; | |
7307 | off = 3; | |
7308 | usw: | |
7309 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7310 | as_bad (_("operand overflow")); | |
7311 | if (! target_big_endian) | |
7312 | offset_expr.X_add_number += off; | |
7313 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
7314 | (int) BFD_RELOC_LO16, breg); | |
7315 | if (! target_big_endian) | |
7316 | offset_expr.X_add_number -= off; | |
7317 | else | |
7318 | offset_expr.X_add_number += off; | |
7319 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
7320 | (int) BFD_RELOC_LO16, breg); | |
7321 | return; | |
7322 | ||
7323 | case M_USD_A: | |
7324 | s = "sdl"; | |
7325 | s2 = "sdr"; | |
7326 | off = 7; | |
7327 | goto uswa; | |
7328 | case M_USW_A: | |
7329 | s = "swl"; | |
7330 | s2 = "swr"; | |
7331 | off = 3; | |
7332 | uswa: | |
d6bc6245 | 7333 | used_at = 1; |
c9914766 | 7334 | load_address (&icnt, AT, &offset_expr, &used_at); |
252b5132 RH |
7335 | if (breg != 0) |
7336 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 7337 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
7338 | "d,v,t", AT, AT, breg); |
7339 | if (! target_big_endian) | |
7340 | expr1.X_add_number = off; | |
7341 | else | |
7342 | expr1.X_add_number = 0; | |
7343 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
7344 | (int) BFD_RELOC_LO16, AT); | |
7345 | if (! target_big_endian) | |
7346 | expr1.X_add_number = 0; | |
7347 | else | |
7348 | expr1.X_add_number = off; | |
7349 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
7350 | (int) BFD_RELOC_LO16, AT); | |
7351 | break; | |
7352 | ||
7353 | case M_USH_A: | |
d6bc6245 | 7354 | used_at = 1; |
c9914766 | 7355 | load_address (&icnt, AT, &offset_expr, &used_at); |
252b5132 RH |
7356 | if (breg != 0) |
7357 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 7358 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
252b5132 RH |
7359 | "d,v,t", AT, AT, breg); |
7360 | if (! target_big_endian) | |
7361 | expr1.X_add_number = 0; | |
7362 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
7363 | (int) BFD_RELOC_LO16, AT); | |
2396cfb9 TS |
7364 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<", |
7365 | treg, treg, 8); | |
252b5132 RH |
7366 | if (! target_big_endian) |
7367 | expr1.X_add_number = 1; | |
7368 | else | |
7369 | expr1.X_add_number = 0; | |
7370 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
7371 | (int) BFD_RELOC_LO16, AT); | |
7372 | if (! target_big_endian) | |
7373 | expr1.X_add_number = 0; | |
7374 | else | |
7375 | expr1.X_add_number = 1; | |
7376 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
7377 | (int) BFD_RELOC_LO16, AT); | |
2396cfb9 TS |
7378 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<", |
7379 | treg, treg, 8); | |
7380 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t", | |
7381 | treg, treg, AT); | |
252b5132 RH |
7382 | break; |
7383 | ||
7384 | default: | |
7385 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 7386 | are added dynamically. */ |
252b5132 RH |
7387 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
7388 | break; | |
7389 | } | |
7390 | if (mips_opts.noat) | |
7391 | as_warn (_("Macro used $at after \".set noat\"")); | |
7392 | } | |
7393 | ||
7394 | /* Implement macros in mips16 mode. */ | |
7395 | ||
7396 | static void | |
7397 | mips16_macro (ip) | |
7398 | struct mips_cl_insn *ip; | |
7399 | { | |
7400 | int mask; | |
7401 | int xreg, yreg, zreg, tmp; | |
7402 | int icnt; | |
7403 | expressionS expr1; | |
7404 | int dbl; | |
7405 | const char *s, *s2, *s3; | |
7406 | ||
7407 | mask = ip->insn_mo->mask; | |
7408 | ||
7409 | xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; | |
7410 | yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY; | |
7411 | zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; | |
7412 | ||
7413 | icnt = 0; | |
7414 | ||
7415 | expr1.X_op = O_constant; | |
7416 | expr1.X_op_symbol = NULL; | |
7417 | expr1.X_add_symbol = NULL; | |
7418 | expr1.X_add_number = 1; | |
7419 | ||
7420 | dbl = 0; | |
7421 | ||
7422 | switch (mask) | |
7423 | { | |
7424 | default: | |
7425 | internalError (); | |
7426 | ||
7427 | case M_DDIV_3: | |
7428 | dbl = 1; | |
7429 | case M_DIV_3: | |
7430 | s = "mflo"; | |
7431 | goto do_div3; | |
7432 | case M_DREM_3: | |
7433 | dbl = 1; | |
7434 | case M_REM_3: | |
7435 | s = "mfhi"; | |
7436 | do_div3: | |
7437 | mips_emit_delays (true); | |
7438 | ++mips_opts.noreorder; | |
7439 | mips_any_noreorder = 1; | |
2396cfb9 | 7440 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
252b5132 RH |
7441 | dbl ? "ddiv" : "div", |
7442 | "0,x,y", xreg, yreg); | |
7443 | expr1.X_add_number = 2; | |
7444 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); | |
2396cfb9 TS |
7445 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", "6", |
7446 | 7); | |
bdaaa2e1 | 7447 | |
252b5132 RH |
7448 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
7449 | since that causes an overflow. We should do that as well, | |
7450 | but I don't see how to do the comparisons without a temporary | |
7451 | register. */ | |
7452 | --mips_opts.noreorder; | |
2396cfb9 | 7453 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x", zreg); |
252b5132 RH |
7454 | break; |
7455 | ||
7456 | case M_DIVU_3: | |
7457 | s = "divu"; | |
7458 | s2 = "mflo"; | |
7459 | goto do_divu3; | |
7460 | case M_REMU_3: | |
7461 | s = "divu"; | |
7462 | s2 = "mfhi"; | |
7463 | goto do_divu3; | |
7464 | case M_DDIVU_3: | |
7465 | s = "ddivu"; | |
7466 | s2 = "mflo"; | |
7467 | goto do_divu3; | |
7468 | case M_DREMU_3: | |
7469 | s = "ddivu"; | |
7470 | s2 = "mfhi"; | |
7471 | do_divu3: | |
7472 | mips_emit_delays (true); | |
7473 | ++mips_opts.noreorder; | |
7474 | mips_any_noreorder = 1; | |
2396cfb9 TS |
7475 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "0,x,y", |
7476 | xreg, yreg); | |
252b5132 RH |
7477 | expr1.X_add_number = 2; |
7478 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); | |
98d3f06f KH |
7479 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "break", |
7480 | "6", 7); | |
252b5132 | 7481 | --mips_opts.noreorder; |
2396cfb9 | 7482 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s2, "x", zreg); |
252b5132 RH |
7483 | break; |
7484 | ||
7485 | case M_DMUL: | |
7486 | dbl = 1; | |
7487 | case M_MUL: | |
2396cfb9 | 7488 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
9a41af64 | 7489 | dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
2396cfb9 TS |
7490 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "mflo", "x", |
7491 | zreg); | |
252b5132 RH |
7492 | return; |
7493 | ||
7494 | case M_DSUBU_I: | |
7495 | dbl = 1; | |
7496 | goto do_subu; | |
7497 | case M_SUBU_I: | |
7498 | do_subu: | |
7499 | if (imm_expr.X_op != O_constant) | |
7500 | as_bad (_("Unsupported large constant")); | |
7501 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
7502 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
9a41af64 | 7503 | dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
7504 | break; |
7505 | ||
7506 | case M_SUBU_I_2: | |
7507 | if (imm_expr.X_op != O_constant) | |
7508 | as_bad (_("Unsupported large constant")); | |
7509 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
7510 | macro_build ((char *) NULL, &icnt, &imm_expr, "addiu", | |
7511 | "x,k", xreg); | |
7512 | break; | |
7513 | ||
7514 | case M_DSUBU_I_2: | |
7515 | if (imm_expr.X_op != O_constant) | |
7516 | as_bad (_("Unsupported large constant")); | |
7517 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
7518 | macro_build ((char *) NULL, &icnt, &imm_expr, "daddiu", | |
7519 | "y,j", yreg); | |
7520 | break; | |
7521 | ||
7522 | case M_BEQ: | |
7523 | s = "cmp"; | |
7524 | s2 = "bteqz"; | |
7525 | goto do_branch; | |
7526 | case M_BNE: | |
7527 | s = "cmp"; | |
7528 | s2 = "btnez"; | |
7529 | goto do_branch; | |
7530 | case M_BLT: | |
7531 | s = "slt"; | |
7532 | s2 = "btnez"; | |
7533 | goto do_branch; | |
7534 | case M_BLTU: | |
7535 | s = "sltu"; | |
7536 | s2 = "btnez"; | |
7537 | goto do_branch; | |
7538 | case M_BLE: | |
7539 | s = "slt"; | |
7540 | s2 = "bteqz"; | |
7541 | goto do_reverse_branch; | |
7542 | case M_BLEU: | |
7543 | s = "sltu"; | |
7544 | s2 = "bteqz"; | |
7545 | goto do_reverse_branch; | |
7546 | case M_BGE: | |
7547 | s = "slt"; | |
7548 | s2 = "bteqz"; | |
7549 | goto do_branch; | |
7550 | case M_BGEU: | |
7551 | s = "sltu"; | |
7552 | s2 = "bteqz"; | |
7553 | goto do_branch; | |
7554 | case M_BGT: | |
7555 | s = "slt"; | |
7556 | s2 = "btnez"; | |
7557 | goto do_reverse_branch; | |
7558 | case M_BGTU: | |
7559 | s = "sltu"; | |
7560 | s2 = "btnez"; | |
7561 | ||
7562 | do_reverse_branch: | |
7563 | tmp = xreg; | |
7564 | xreg = yreg; | |
7565 | yreg = tmp; | |
7566 | ||
7567 | do_branch: | |
7568 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x,y", | |
7569 | xreg, yreg); | |
7570 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
7571 | break; | |
7572 | ||
7573 | case M_BEQ_I: | |
7574 | s = "cmpi"; | |
7575 | s2 = "bteqz"; | |
7576 | s3 = "x,U"; | |
7577 | goto do_branch_i; | |
7578 | case M_BNE_I: | |
7579 | s = "cmpi"; | |
7580 | s2 = "btnez"; | |
7581 | s3 = "x,U"; | |
7582 | goto do_branch_i; | |
7583 | case M_BLT_I: | |
7584 | s = "slti"; | |
7585 | s2 = "btnez"; | |
7586 | s3 = "x,8"; | |
7587 | goto do_branch_i; | |
7588 | case M_BLTU_I: | |
7589 | s = "sltiu"; | |
7590 | s2 = "btnez"; | |
7591 | s3 = "x,8"; | |
7592 | goto do_branch_i; | |
7593 | case M_BLE_I: | |
7594 | s = "slti"; | |
7595 | s2 = "btnez"; | |
7596 | s3 = "x,8"; | |
7597 | goto do_addone_branch_i; | |
7598 | case M_BLEU_I: | |
7599 | s = "sltiu"; | |
7600 | s2 = "btnez"; | |
7601 | s3 = "x,8"; | |
7602 | goto do_addone_branch_i; | |
7603 | case M_BGE_I: | |
7604 | s = "slti"; | |
7605 | s2 = "bteqz"; | |
7606 | s3 = "x,8"; | |
7607 | goto do_branch_i; | |
7608 | case M_BGEU_I: | |
7609 | s = "sltiu"; | |
7610 | s2 = "bteqz"; | |
7611 | s3 = "x,8"; | |
7612 | goto do_branch_i; | |
7613 | case M_BGT_I: | |
7614 | s = "slti"; | |
7615 | s2 = "bteqz"; | |
7616 | s3 = "x,8"; | |
7617 | goto do_addone_branch_i; | |
7618 | case M_BGTU_I: | |
7619 | s = "sltiu"; | |
7620 | s2 = "bteqz"; | |
7621 | s3 = "x,8"; | |
7622 | ||
7623 | do_addone_branch_i: | |
7624 | if (imm_expr.X_op != O_constant) | |
7625 | as_bad (_("Unsupported large constant")); | |
7626 | ++imm_expr.X_add_number; | |
7627 | ||
7628 | do_branch_i: | |
7629 | macro_build ((char *) NULL, &icnt, &imm_expr, s, s3, xreg); | |
7630 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
7631 | break; | |
7632 | ||
7633 | case M_ABS: | |
7634 | expr1.X_add_number = 0; | |
98d3f06f | 7635 | macro_build ((char *) NULL, &icnt, &expr1, "slti", "x,8", yreg); |
252b5132 | 7636 | if (xreg != yreg) |
ea1fb5dc | 7637 | move_register (&icnt, xreg, yreg); |
252b5132 RH |
7638 | expr1.X_add_number = 2; |
7639 | macro_build ((char *) NULL, &icnt, &expr1, "bteqz", "p"); | |
7640 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
7641 | "neg", "x,w", xreg, xreg); | |
7642 | } | |
7643 | } | |
7644 | ||
7645 | /* For consistency checking, verify that all bits are specified either | |
7646 | by the match/mask part of the instruction definition, or by the | |
7647 | operand list. */ | |
7648 | static int | |
7649 | validate_mips_insn (opc) | |
7650 | const struct mips_opcode *opc; | |
7651 | { | |
7652 | const char *p = opc->args; | |
7653 | char c; | |
7654 | unsigned long used_bits = opc->mask; | |
7655 | ||
7656 | if ((used_bits & opc->match) != opc->match) | |
7657 | { | |
7658 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
7659 | opc->name, opc->args); | |
7660 | return 0; | |
7661 | } | |
7662 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
7663 | while (*p) | |
7664 | switch (c = *p++) | |
7665 | { | |
7666 | case ',': break; | |
7667 | case '(': break; | |
7668 | case ')': break; | |
7669 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
7670 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
7671 | case 'A': break; | |
4372b673 | 7672 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
7673 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
7674 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
7675 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7676 | case 'F': break; | |
7677 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 7678 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 7679 | case 'I': break; |
e972090a | 7680 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
252b5132 RH |
7681 | case 'L': break; |
7682 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
7683 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
7684 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
7685 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
7686 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
7687 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
7688 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7689 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
7690 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7691 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
7692 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
7693 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7694 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
7695 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
7696 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7697 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
7698 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
7699 | case 'f': break; | |
7700 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
7701 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
7702 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7703 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
7704 | case 'l': break; | |
7705 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7706 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7707 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
7708 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7709 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7710 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7711 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
7712 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7713 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7714 | case 'x': break; | |
7715 | case 'z': break; | |
7716 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
7717 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
7718 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
252b5132 RH |
7719 | default: |
7720 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
7721 | c, opc->name, opc->args); | |
7722 | return 0; | |
7723 | } | |
7724 | #undef USE_BITS | |
7725 | if (used_bits != 0xffffffff) | |
7726 | { | |
7727 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
7728 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
7729 | return 0; | |
7730 | } | |
7731 | return 1; | |
7732 | } | |
7733 | ||
7734 | /* This routine assembles an instruction into its binary format. As a | |
7735 | side effect, it sets one of the global variables imm_reloc or | |
7736 | offset_reloc to the type of relocation to do if one of the operands | |
7737 | is an address expression. */ | |
7738 | ||
7739 | static void | |
7740 | mips_ip (str, ip) | |
7741 | char *str; | |
7742 | struct mips_cl_insn *ip; | |
7743 | { | |
7744 | char *s; | |
7745 | const char *args; | |
43841e91 | 7746 | char c = 0; |
252b5132 RH |
7747 | struct mips_opcode *insn; |
7748 | char *argsStart; | |
7749 | unsigned int regno; | |
7750 | unsigned int lastregno = 0; | |
7751 | char *s_reset; | |
7752 | char save_c = 0; | |
252b5132 RH |
7753 | |
7754 | insn_error = NULL; | |
7755 | ||
7756 | /* If the instruction contains a '.', we first try to match an instruction | |
7757 | including the '.'. Then we try again without the '.'. */ | |
7758 | insn = NULL; | |
3882b010 | 7759 | for (s = str; *s != '\0' && !ISSPACE (*s); ++s) |
252b5132 RH |
7760 | continue; |
7761 | ||
7762 | /* If we stopped on whitespace, then replace the whitespace with null for | |
7763 | the call to hash_find. Save the character we replaced just in case we | |
7764 | have to re-parse the instruction. */ | |
3882b010 | 7765 | if (ISSPACE (*s)) |
252b5132 RH |
7766 | { |
7767 | save_c = *s; | |
7768 | *s++ = '\0'; | |
7769 | } | |
bdaaa2e1 | 7770 | |
252b5132 RH |
7771 | insn = (struct mips_opcode *) hash_find (op_hash, str); |
7772 | ||
7773 | /* If we didn't find the instruction in the opcode table, try again, but | |
7774 | this time with just the instruction up to, but not including the | |
7775 | first '.'. */ | |
7776 | if (insn == NULL) | |
7777 | { | |
bdaaa2e1 | 7778 | /* Restore the character we overwrite above (if any). */ |
252b5132 RH |
7779 | if (save_c) |
7780 | *(--s) = save_c; | |
7781 | ||
7782 | /* Scan up to the first '.' or whitespace. */ | |
3882b010 L |
7783 | for (s = str; |
7784 | *s != '\0' && *s != '.' && !ISSPACE (*s); | |
7785 | ++s) | |
252b5132 RH |
7786 | continue; |
7787 | ||
7788 | /* If we did not find a '.', then we can quit now. */ | |
7789 | if (*s != '.') | |
7790 | { | |
7791 | insn_error = "unrecognized opcode"; | |
7792 | return; | |
7793 | } | |
7794 | ||
7795 | /* Lookup the instruction in the hash table. */ | |
7796 | *s++ = '\0'; | |
7797 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
7798 | { | |
7799 | insn_error = "unrecognized opcode"; | |
7800 | return; | |
7801 | } | |
252b5132 RH |
7802 | } |
7803 | ||
7804 | argsStart = s; | |
7805 | for (;;) | |
7806 | { | |
252b5132 RH |
7807 | boolean ok; |
7808 | ||
7809 | assert (strcmp (insn->name, str) == 0); | |
7810 | ||
1f25f5d3 CD |
7811 | if (OPCODE_IS_MEMBER (insn, |
7812 | (mips_opts.isa | |
3396de36 | 7813 | | (file_ase_mips16 ? INSN_MIPS16 : 0) |
deec1734 | 7814 | | (mips_opts.ase_mdmx ? INSN_MDMX : 0) |
98d3f06f | 7815 | | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)), |
1f25f5d3 | 7816 | mips_arch)) |
252b5132 | 7817 | ok = true; |
bdaaa2e1 | 7818 | else |
252b5132 | 7819 | ok = false; |
bdaaa2e1 | 7820 | |
252b5132 RH |
7821 | if (insn->pinfo != INSN_MACRO) |
7822 | { | |
ec68c924 | 7823 | if (mips_arch == CPU_R4650 && (insn->pinfo & FP_D) != 0) |
252b5132 RH |
7824 | ok = false; |
7825 | } | |
7826 | ||
7827 | if (! ok) | |
7828 | { | |
7829 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
7830 | && strcmp (insn->name, insn[1].name) == 0) | |
7831 | { | |
7832 | ++insn; | |
7833 | continue; | |
7834 | } | |
252b5132 | 7835 | else |
beae10d5 | 7836 | { |
268f6bed L |
7837 | if (!insn_error) |
7838 | { | |
7839 | static char buf[100]; | |
316f5878 RS |
7840 | if (mips_arch_info->is_isa) |
7841 | sprintf (buf, | |
7842 | _("opcode not supported at this ISA level (%s)"), | |
7843 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
7844 | else | |
7845 | sprintf (buf, | |
7846 | _("opcode not supported on this processor: %s (%s)"), | |
7847 | mips_arch_info->name, | |
7848 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
268f6bed L |
7849 | insn_error = buf; |
7850 | } | |
7851 | if (save_c) | |
7852 | *(--s) = save_c; | |
2bd7f1f3 | 7853 | return; |
252b5132 | 7854 | } |
252b5132 RH |
7855 | } |
7856 | ||
7857 | ip->insn_mo = insn; | |
7858 | ip->insn_opcode = insn->match; | |
268f6bed | 7859 | insn_error = NULL; |
252b5132 RH |
7860 | for (args = insn->args;; ++args) |
7861 | { | |
deec1734 CD |
7862 | int is_mdmx; |
7863 | ||
ad8d3bb3 | 7864 | s += strspn (s, " \t"); |
deec1734 | 7865 | is_mdmx = 0; |
252b5132 RH |
7866 | switch (*args) |
7867 | { | |
7868 | case '\0': /* end of args */ | |
7869 | if (*s == '\0') | |
7870 | return; | |
7871 | break; | |
7872 | ||
7873 | case ',': | |
7874 | if (*s++ == *args) | |
7875 | continue; | |
7876 | s--; | |
7877 | switch (*++args) | |
7878 | { | |
7879 | case 'r': | |
7880 | case 'v': | |
38487616 | 7881 | ip->insn_opcode |= lastregno << OP_SH_RS; |
252b5132 RH |
7882 | continue; |
7883 | ||
7884 | case 'w': | |
38487616 TS |
7885 | ip->insn_opcode |= lastregno << OP_SH_RT; |
7886 | continue; | |
7887 | ||
252b5132 | 7888 | case 'W': |
38487616 | 7889 | ip->insn_opcode |= lastregno << OP_SH_FT; |
252b5132 RH |
7890 | continue; |
7891 | ||
7892 | case 'V': | |
38487616 | 7893 | ip->insn_opcode |= lastregno << OP_SH_FS; |
252b5132 RH |
7894 | continue; |
7895 | } | |
7896 | break; | |
7897 | ||
7898 | case '(': | |
7899 | /* Handle optional base register. | |
7900 | Either the base register is omitted or | |
bdaaa2e1 | 7901 | we must have a left paren. */ |
252b5132 RH |
7902 | /* This is dependent on the next operand specifier |
7903 | is a base register specification. */ | |
7904 | assert (args[1] == 'b' || args[1] == '5' | |
7905 | || args[1] == '-' || args[1] == '4'); | |
7906 | if (*s == '\0') | |
7907 | return; | |
7908 | ||
7909 | case ')': /* these must match exactly */ | |
7910 | if (*s++ == *args) | |
7911 | continue; | |
7912 | break; | |
7913 | ||
7914 | case '<': /* must be at least one digit */ | |
7915 | /* | |
7916 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
7917 | * than 31 or less than 0, then the shift amount should be |
7918 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
7919 | * We issue a warning and mask out all but the low 5 bits. |
7920 | */ | |
7921 | my_getExpression (&imm_expr, s); | |
7922 | check_absolute_expr (ip, &imm_expr); | |
7923 | if ((unsigned long) imm_expr.X_add_number > 31) | |
7924 | { | |
793b27f4 TS |
7925 | as_warn (_("Improper shift amount (%lu)"), |
7926 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 7927 | imm_expr.X_add_number &= OP_MASK_SHAMT; |
252b5132 | 7928 | } |
38487616 | 7929 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT; |
252b5132 RH |
7930 | imm_expr.X_op = O_absent; |
7931 | s = expr_end; | |
7932 | continue; | |
7933 | ||
7934 | case '>': /* shift amount minus 32 */ | |
7935 | my_getExpression (&imm_expr, s); | |
7936 | check_absolute_expr (ip, &imm_expr); | |
7937 | if ((unsigned long) imm_expr.X_add_number < 32 | |
7938 | || (unsigned long) imm_expr.X_add_number > 63) | |
7939 | break; | |
38487616 | 7940 | ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT; |
252b5132 RH |
7941 | imm_expr.X_op = O_absent; |
7942 | s = expr_end; | |
7943 | continue; | |
7944 | ||
252b5132 RH |
7945 | case 'k': /* cache code */ |
7946 | case 'h': /* prefx code */ | |
7947 | my_getExpression (&imm_expr, s); | |
7948 | check_absolute_expr (ip, &imm_expr); | |
7949 | if ((unsigned long) imm_expr.X_add_number > 31) | |
7950 | { | |
7951 | as_warn (_("Invalid value for `%s' (%lu)"), | |
7952 | ip->insn_mo->name, | |
7953 | (unsigned long) imm_expr.X_add_number); | |
7954 | imm_expr.X_add_number &= 0x1f; | |
7955 | } | |
7956 | if (*args == 'k') | |
7957 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE; | |
7958 | else | |
7959 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX; | |
7960 | imm_expr.X_op = O_absent; | |
7961 | s = expr_end; | |
7962 | continue; | |
7963 | ||
7964 | case 'c': /* break code */ | |
7965 | my_getExpression (&imm_expr, s); | |
7966 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 7967 | if ((unsigned long) imm_expr.X_add_number > 1023) |
252b5132 | 7968 | { |
793b27f4 TS |
7969 | as_warn (_("Illegal break code (%lu)"), |
7970 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 7971 | imm_expr.X_add_number &= OP_MASK_CODE; |
252b5132 | 7972 | } |
38487616 | 7973 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE; |
252b5132 RH |
7974 | imm_expr.X_op = O_absent; |
7975 | s = expr_end; | |
7976 | continue; | |
7977 | ||
7978 | case 'q': /* lower break code */ | |
7979 | my_getExpression (&imm_expr, s); | |
7980 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 7981 | if ((unsigned long) imm_expr.X_add_number > 1023) |
252b5132 | 7982 | { |
793b27f4 TS |
7983 | as_warn (_("Illegal lower break code (%lu)"), |
7984 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 7985 | imm_expr.X_add_number &= OP_MASK_CODE2; |
252b5132 | 7986 | } |
38487616 | 7987 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2; |
252b5132 RH |
7988 | imm_expr.X_op = O_absent; |
7989 | s = expr_end; | |
7990 | continue; | |
7991 | ||
4372b673 | 7992 | case 'B': /* 20-bit syscall/break code. */ |
156c2f8b | 7993 | my_getExpression (&imm_expr, s); |
156c2f8b | 7994 | check_absolute_expr (ip, &imm_expr); |
793b27f4 TS |
7995 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20) |
7996 | as_warn (_("Illegal 20-bit code (%lu)"), | |
7997 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 7998 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20; |
252b5132 RH |
7999 | imm_expr.X_op = O_absent; |
8000 | s = expr_end; | |
8001 | continue; | |
8002 | ||
98d3f06f | 8003 | case 'C': /* Coprocessor code */ |
beae10d5 | 8004 | my_getExpression (&imm_expr, s); |
252b5132 | 8005 | check_absolute_expr (ip, &imm_expr); |
98d3f06f | 8006 | if ((unsigned long) imm_expr.X_add_number >= (1 << 25)) |
252b5132 | 8007 | { |
793b27f4 TS |
8008 | as_warn (_("Coproccesor code > 25 bits (%lu)"), |
8009 | (unsigned long) imm_expr.X_add_number); | |
98d3f06f | 8010 | imm_expr.X_add_number &= ((1 << 25) - 1); |
252b5132 | 8011 | } |
beae10d5 KH |
8012 | ip->insn_opcode |= imm_expr.X_add_number; |
8013 | imm_expr.X_op = O_absent; | |
8014 | s = expr_end; | |
8015 | continue; | |
252b5132 | 8016 | |
4372b673 NC |
8017 | case 'J': /* 19-bit wait code. */ |
8018 | my_getExpression (&imm_expr, s); | |
8019 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 TS |
8020 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
8021 | as_warn (_("Illegal 19-bit code (%lu)"), | |
8022 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8023 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19; |
4372b673 NC |
8024 | imm_expr.X_op = O_absent; |
8025 | s = expr_end; | |
8026 | continue; | |
8027 | ||
252b5132 | 8028 | case 'P': /* Performance register */ |
beae10d5 | 8029 | my_getExpression (&imm_expr, s); |
252b5132 | 8030 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 8031 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
252b5132 | 8032 | { |
793b27f4 TS |
8033 | as_warn (_("Invalid performance register (%lu)"), |
8034 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8035 | imm_expr.X_add_number &= OP_MASK_PERFREG; |
252b5132 | 8036 | } |
38487616 | 8037 | ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG); |
beae10d5 KH |
8038 | imm_expr.X_op = O_absent; |
8039 | s = expr_end; | |
8040 | continue; | |
252b5132 RH |
8041 | |
8042 | case 'b': /* base register */ | |
8043 | case 'd': /* destination register */ | |
8044 | case 's': /* source register */ | |
8045 | case 't': /* target register */ | |
8046 | case 'r': /* both target and source */ | |
8047 | case 'v': /* both dest and source */ | |
8048 | case 'w': /* both dest and target */ | |
8049 | case 'E': /* coprocessor target register */ | |
8050 | case 'G': /* coprocessor destination register */ | |
8051 | case 'x': /* ignore register name */ | |
8052 | case 'z': /* must be zero register */ | |
4372b673 | 8053 | case 'U': /* destination register (clo/clz). */ |
252b5132 RH |
8054 | s_reset = s; |
8055 | if (s[0] == '$') | |
8056 | { | |
8057 | ||
3882b010 | 8058 | if (ISDIGIT (s[1])) |
252b5132 RH |
8059 | { |
8060 | ++s; | |
8061 | regno = 0; | |
8062 | do | |
8063 | { | |
8064 | regno *= 10; | |
8065 | regno += *s - '0'; | |
8066 | ++s; | |
8067 | } | |
3882b010 | 8068 | while (ISDIGIT (*s)); |
252b5132 RH |
8069 | if (regno > 31) |
8070 | as_bad (_("Invalid register number (%d)"), regno); | |
8071 | } | |
8072 | else if (*args == 'E' || *args == 'G') | |
8073 | goto notreg; | |
8074 | else | |
8075 | { | |
76db943d TS |
8076 | if (s[1] == 'r' && s[2] == 'a') |
8077 | { | |
8078 | s += 3; | |
8079 | regno = RA; | |
8080 | } | |
8081 | else if (s[1] == 'f' && s[2] == 'p') | |
252b5132 RH |
8082 | { |
8083 | s += 3; | |
8084 | regno = FP; | |
8085 | } | |
8086 | else if (s[1] == 's' && s[2] == 'p') | |
8087 | { | |
8088 | s += 3; | |
8089 | regno = SP; | |
8090 | } | |
8091 | else if (s[1] == 'g' && s[2] == 'p') | |
8092 | { | |
8093 | s += 3; | |
8094 | regno = GP; | |
8095 | } | |
8096 | else if (s[1] == 'a' && s[2] == 't') | |
8097 | { | |
8098 | s += 3; | |
8099 | regno = AT; | |
8100 | } | |
8101 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
8102 | { | |
8103 | s += 4; | |
8104 | regno = KT0; | |
8105 | } | |
8106 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
8107 | { | |
8108 | s += 4; | |
8109 | regno = KT1; | |
8110 | } | |
85b51719 TS |
8111 | else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o') |
8112 | { | |
8113 | s += 5; | |
8114 | regno = ZERO; | |
8115 | } | |
252b5132 RH |
8116 | else if (itbl_have_entries) |
8117 | { | |
8118 | char *p, *n; | |
d7ba4a77 | 8119 | unsigned long r; |
252b5132 | 8120 | |
d7ba4a77 | 8121 | p = s + 1; /* advance past '$' */ |
252b5132 RH |
8122 | n = itbl_get_field (&p); /* n is name */ |
8123 | ||
d7ba4a77 ILT |
8124 | /* See if this is a register defined in an |
8125 | itbl entry. */ | |
8126 | if (itbl_get_reg_val (n, &r)) | |
252b5132 RH |
8127 | { |
8128 | /* Get_field advances to the start of | |
8129 | the next field, so we need to back | |
d7ba4a77 | 8130 | rack to the end of the last field. */ |
bdaaa2e1 | 8131 | if (p) |
252b5132 | 8132 | s = p - 1; |
bdaaa2e1 | 8133 | else |
d7ba4a77 | 8134 | s = strchr (s, '\0'); |
252b5132 RH |
8135 | regno = r; |
8136 | } | |
8137 | else | |
8138 | goto notreg; | |
beae10d5 | 8139 | } |
252b5132 RH |
8140 | else |
8141 | goto notreg; | |
8142 | } | |
8143 | if (regno == AT | |
8144 | && ! mips_opts.noat | |
8145 | && *args != 'E' | |
8146 | && *args != 'G') | |
8147 | as_warn (_("Used $at without \".set noat\"")); | |
8148 | c = *args; | |
8149 | if (*s == ' ') | |
f9419b05 | 8150 | ++s; |
252b5132 RH |
8151 | if (args[1] != *s) |
8152 | { | |
8153 | if (c == 'r' || c == 'v' || c == 'w') | |
8154 | { | |
8155 | regno = lastregno; | |
8156 | s = s_reset; | |
f9419b05 | 8157 | ++args; |
252b5132 RH |
8158 | } |
8159 | } | |
8160 | /* 'z' only matches $0. */ | |
8161 | if (c == 'z' && regno != 0) | |
8162 | break; | |
8163 | ||
bdaaa2e1 KH |
8164 | /* Now that we have assembled one operand, we use the args string |
8165 | * to figure out where it goes in the instruction. */ | |
252b5132 RH |
8166 | switch (c) |
8167 | { | |
8168 | case 'r': | |
8169 | case 's': | |
8170 | case 'v': | |
8171 | case 'b': | |
38487616 | 8172 | ip->insn_opcode |= regno << OP_SH_RS; |
252b5132 RH |
8173 | break; |
8174 | case 'd': | |
8175 | case 'G': | |
38487616 | 8176 | ip->insn_opcode |= regno << OP_SH_RD; |
252b5132 | 8177 | break; |
4372b673 | 8178 | case 'U': |
38487616 TS |
8179 | ip->insn_opcode |= regno << OP_SH_RD; |
8180 | ip->insn_opcode |= regno << OP_SH_RT; | |
4372b673 | 8181 | break; |
252b5132 RH |
8182 | case 'w': |
8183 | case 't': | |
8184 | case 'E': | |
38487616 | 8185 | ip->insn_opcode |= regno << OP_SH_RT; |
252b5132 RH |
8186 | break; |
8187 | case 'x': | |
8188 | /* This case exists because on the r3000 trunc | |
8189 | expands into a macro which requires a gp | |
8190 | register. On the r6000 or r4000 it is | |
8191 | assembled into a single instruction which | |
8192 | ignores the register. Thus the insn version | |
8193 | is MIPS_ISA2 and uses 'x', and the macro | |
8194 | version is MIPS_ISA1 and uses 't'. */ | |
8195 | break; | |
8196 | case 'z': | |
8197 | /* This case is for the div instruction, which | |
8198 | acts differently if the destination argument | |
8199 | is $0. This only matches $0, and is checked | |
8200 | outside the switch. */ | |
8201 | break; | |
8202 | case 'D': | |
8203 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
8204 | break; | |
8205 | /* What about all other operands like 'i', which | |
8206 | can be specified in the opcode table? */ | |
8207 | } | |
8208 | lastregno = regno; | |
8209 | continue; | |
8210 | } | |
8211 | notreg: | |
8212 | switch (*args++) | |
8213 | { | |
8214 | case 'r': | |
8215 | case 'v': | |
38487616 | 8216 | ip->insn_opcode |= lastregno << OP_SH_RS; |
252b5132 RH |
8217 | continue; |
8218 | case 'w': | |
38487616 | 8219 | ip->insn_opcode |= lastregno << OP_SH_RT; |
252b5132 RH |
8220 | continue; |
8221 | } | |
8222 | break; | |
8223 | ||
deec1734 CD |
8224 | case 'O': /* MDMX alignment immediate constant. */ |
8225 | my_getExpression (&imm_expr, s); | |
8226 | check_absolute_expr (ip, &imm_expr); | |
8227 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
8228 | { | |
8229 | as_warn ("Improper align amount (%ld), using low bits", | |
8230 | (long) imm_expr.X_add_number); | |
8231 | imm_expr.X_add_number &= OP_MASK_ALN; | |
8232 | } | |
8233 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_ALN; | |
8234 | imm_expr.X_op = O_absent; | |
8235 | s = expr_end; | |
8236 | continue; | |
8237 | ||
8238 | case 'Q': /* MDMX vector, element sel, or const. */ | |
8239 | if (s[0] != '$') | |
8240 | { | |
8241 | /* MDMX Immediate. */ | |
8242 | my_getExpression (&imm_expr, s); | |
8243 | check_absolute_expr (ip, &imm_expr); | |
8244 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
8245 | { | |
8246 | as_warn (_("Invalid MDMX Immediate (%ld)"), | |
8247 | (long) imm_expr.X_add_number); | |
8248 | imm_expr.X_add_number &= OP_MASK_FT; | |
8249 | } | |
8250 | imm_expr.X_add_number &= OP_MASK_FT; | |
8251 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
8252 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
8253 | else | |
8254 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
8255 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_FT; | |
8256 | imm_expr.X_op = O_absent; | |
8257 | s = expr_end; | |
8258 | continue; | |
8259 | } | |
8260 | /* Not MDMX Immediate. Fall through. */ | |
8261 | case 'X': /* MDMX destination register. */ | |
8262 | case 'Y': /* MDMX source register. */ | |
8263 | case 'Z': /* MDMX target register. */ | |
8264 | is_mdmx = 1; | |
252b5132 RH |
8265 | case 'D': /* floating point destination register */ |
8266 | case 'S': /* floating point source register */ | |
8267 | case 'T': /* floating point target register */ | |
8268 | case 'R': /* floating point source register */ | |
8269 | case 'V': | |
8270 | case 'W': | |
8271 | s_reset = s; | |
deec1734 CD |
8272 | /* Accept $fN for FP and MDMX register numbers, and in |
8273 | addition accept $vN for MDMX register numbers. */ | |
8274 | if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2])) | |
8275 | || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v' | |
8276 | && ISDIGIT (s[2]))) | |
252b5132 RH |
8277 | { |
8278 | s += 2; | |
8279 | regno = 0; | |
8280 | do | |
8281 | { | |
8282 | regno *= 10; | |
8283 | regno += *s - '0'; | |
8284 | ++s; | |
8285 | } | |
3882b010 | 8286 | while (ISDIGIT (*s)); |
252b5132 RH |
8287 | |
8288 | if (regno > 31) | |
8289 | as_bad (_("Invalid float register number (%d)"), regno); | |
8290 | ||
8291 | if ((regno & 1) != 0 | |
ca4e0257 | 8292 | && HAVE_32BIT_FPRS |
252b5132 RH |
8293 | && ! (strcmp (str, "mtc1") == 0 |
8294 | || strcmp (str, "mfc1") == 0 | |
8295 | || strcmp (str, "lwc1") == 0 | |
8296 | || strcmp (str, "swc1") == 0 | |
8297 | || strcmp (str, "l.s") == 0 | |
8298 | || strcmp (str, "s.s") == 0)) | |
8299 | as_warn (_("Float register should be even, was %d"), | |
8300 | regno); | |
8301 | ||
8302 | c = *args; | |
8303 | if (*s == ' ') | |
f9419b05 | 8304 | ++s; |
252b5132 RH |
8305 | if (args[1] != *s) |
8306 | { | |
8307 | if (c == 'V' || c == 'W') | |
8308 | { | |
8309 | regno = lastregno; | |
8310 | s = s_reset; | |
f9419b05 | 8311 | ++args; |
252b5132 RH |
8312 | } |
8313 | } | |
8314 | switch (c) | |
8315 | { | |
8316 | case 'D': | |
deec1734 | 8317 | case 'X': |
38487616 | 8318 | ip->insn_opcode |= regno << OP_SH_FD; |
252b5132 RH |
8319 | break; |
8320 | case 'V': | |
8321 | case 'S': | |
deec1734 | 8322 | case 'Y': |
38487616 | 8323 | ip->insn_opcode |= regno << OP_SH_FS; |
252b5132 | 8324 | break; |
deec1734 CD |
8325 | case 'Q': |
8326 | /* This is like 'Z', but also needs to fix the MDMX | |
8327 | vector/scalar select bits. Note that the | |
8328 | scalar immediate case is handled above. */ | |
8329 | if (*s == '[') | |
8330 | { | |
8331 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
8332 | int max_el = (is_qh ? 3 : 7); | |
8333 | s++; | |
8334 | my_getExpression(&imm_expr, s); | |
8335 | check_absolute_expr (ip, &imm_expr); | |
8336 | s = expr_end; | |
8337 | if (imm_expr.X_add_number > max_el) | |
8338 | as_bad(_("Bad element selector %ld"), | |
8339 | (long) imm_expr.X_add_number); | |
8340 | imm_expr.X_add_number &= max_el; | |
8341 | ip->insn_opcode |= (imm_expr.X_add_number | |
8342 | << (OP_SH_VSEL + | |
8343 | (is_qh ? 2 : 1))); | |
8344 | if (*s != ']') | |
8345 | as_warn(_("Expecting ']' found '%s'"), s); | |
8346 | else | |
8347 | s++; | |
8348 | } | |
8349 | else | |
8350 | { | |
8351 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
8352 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
8353 | << OP_SH_VSEL); | |
8354 | else | |
8355 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
8356 | OP_SH_VSEL); | |
8357 | } | |
8358 | /* Fall through */ | |
252b5132 RH |
8359 | case 'W': |
8360 | case 'T': | |
deec1734 | 8361 | case 'Z': |
38487616 | 8362 | ip->insn_opcode |= regno << OP_SH_FT; |
252b5132 RH |
8363 | break; |
8364 | case 'R': | |
38487616 | 8365 | ip->insn_opcode |= regno << OP_SH_FR; |
252b5132 RH |
8366 | break; |
8367 | } | |
8368 | lastregno = regno; | |
8369 | continue; | |
8370 | } | |
8371 | ||
252b5132 RH |
8372 | switch (*args++) |
8373 | { | |
8374 | case 'V': | |
38487616 | 8375 | ip->insn_opcode |= lastregno << OP_SH_FS; |
252b5132 RH |
8376 | continue; |
8377 | case 'W': | |
38487616 | 8378 | ip->insn_opcode |= lastregno << OP_SH_FT; |
252b5132 RH |
8379 | continue; |
8380 | } | |
8381 | break; | |
8382 | ||
8383 | case 'I': | |
8384 | my_getExpression (&imm_expr, s); | |
8385 | if (imm_expr.X_op != O_big | |
8386 | && imm_expr.X_op != O_constant) | |
8387 | insn_error = _("absolute expression required"); | |
8388 | s = expr_end; | |
8389 | continue; | |
8390 | ||
8391 | case 'A': | |
8392 | my_getExpression (&offset_expr, s); | |
f6688943 | 8393 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
8394 | s = expr_end; |
8395 | continue; | |
8396 | ||
8397 | case 'F': | |
8398 | case 'L': | |
8399 | case 'f': | |
8400 | case 'l': | |
8401 | { | |
8402 | int f64; | |
ca4e0257 | 8403 | int using_gprs; |
252b5132 RH |
8404 | char *save_in; |
8405 | char *err; | |
8406 | unsigned char temp[8]; | |
8407 | int len; | |
8408 | unsigned int length; | |
8409 | segT seg; | |
8410 | subsegT subseg; | |
8411 | char *p; | |
8412 | ||
8413 | /* These only appear as the last operand in an | |
8414 | instruction, and every instruction that accepts | |
8415 | them in any variant accepts them in all variants. | |
8416 | This means we don't have to worry about backing out | |
8417 | any changes if the instruction does not match. | |
8418 | ||
8419 | The difference between them is the size of the | |
8420 | floating point constant and where it goes. For 'F' | |
8421 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
8422 | is 32 bits. Where the constant is placed is based | |
8423 | on how the MIPS assembler does things: | |
8424 | F -- .rdata | |
8425 | L -- .lit8 | |
8426 | f -- immediate value | |
8427 | l -- .lit4 | |
8428 | ||
8429 | The .lit4 and .lit8 sections are only used if | |
8430 | permitted by the -G argument. | |
8431 | ||
8432 | When generating embedded PIC code, we use the | |
8433 | .lit8 section but not the .lit4 section (we can do | |
8434 | .lit4 inline easily; we need to put .lit8 | |
8435 | somewhere in the data segment, and using .lit8 | |
8436 | permits the linker to eventually combine identical | |
ca4e0257 RS |
8437 | .lit8 entries). |
8438 | ||
8439 | The code below needs to know whether the target register | |
8440 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
8441 | 'F' are used with GPR-based instructions and 'l' and | |
8442 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
8443 | |
8444 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 8445 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
8446 | |
8447 | save_in = input_line_pointer; | |
8448 | input_line_pointer = s; | |
8449 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
8450 | length = len; | |
8451 | s = input_line_pointer; | |
8452 | input_line_pointer = save_in; | |
8453 | if (err != NULL && *err != '\0') | |
8454 | { | |
8455 | as_bad (_("Bad floating point constant: %s"), err); | |
8456 | memset (temp, '\0', sizeof temp); | |
8457 | length = f64 ? 8 : 4; | |
8458 | } | |
8459 | ||
156c2f8b | 8460 | assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
8461 | |
8462 | if (*args == 'f' | |
8463 | || (*args == 'l' | |
8464 | && (! USE_GLOBAL_POINTER_OPT | |
8465 | || mips_pic == EMBEDDED_PIC | |
8466 | || g_switch_value < 4 | |
8467 | || (temp[0] == 0 && temp[1] == 0) | |
8468 | || (temp[2] == 0 && temp[3] == 0)))) | |
8469 | { | |
8470 | imm_expr.X_op = O_constant; | |
8471 | if (! target_big_endian) | |
8472 | imm_expr.X_add_number = bfd_getl32 (temp); | |
8473 | else | |
8474 | imm_expr.X_add_number = bfd_getb32 (temp); | |
8475 | } | |
8476 | else if (length > 4 | |
119d663a | 8477 | && ! mips_disable_float_construction |
ca4e0257 RS |
8478 | /* Constants can only be constructed in GPRs and |
8479 | copied to FPRs if the GPRs are at least as wide | |
8480 | as the FPRs. Force the constant into memory if | |
8481 | we are using 64-bit FPRs but the GPRs are only | |
8482 | 32 bits wide. */ | |
8483 | && (using_gprs | |
8484 | || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) | |
252b5132 RH |
8485 | && ((temp[0] == 0 && temp[1] == 0) |
8486 | || (temp[2] == 0 && temp[3] == 0)) | |
8487 | && ((temp[4] == 0 && temp[5] == 0) | |
8488 | || (temp[6] == 0 && temp[7] == 0))) | |
8489 | { | |
ca4e0257 RS |
8490 | /* The value is simple enough to load with a couple of |
8491 | instructions. If using 32-bit registers, set | |
8492 | imm_expr to the high order 32 bits and offset_expr to | |
8493 | the low order 32 bits. Otherwise, set imm_expr to | |
8494 | the entire 64 bit constant. */ | |
8495 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) | |
252b5132 RH |
8496 | { |
8497 | imm_expr.X_op = O_constant; | |
8498 | offset_expr.X_op = O_constant; | |
8499 | if (! target_big_endian) | |
8500 | { | |
8501 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
8502 | offset_expr.X_add_number = bfd_getl32 (temp); | |
8503 | } | |
8504 | else | |
8505 | { | |
8506 | imm_expr.X_add_number = bfd_getb32 (temp); | |
8507 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
8508 | } | |
8509 | if (offset_expr.X_add_number == 0) | |
8510 | offset_expr.X_op = O_absent; | |
8511 | } | |
8512 | else if (sizeof (imm_expr.X_add_number) > 4) | |
8513 | { | |
8514 | imm_expr.X_op = O_constant; | |
8515 | if (! target_big_endian) | |
8516 | imm_expr.X_add_number = bfd_getl64 (temp); | |
8517 | else | |
8518 | imm_expr.X_add_number = bfd_getb64 (temp); | |
8519 | } | |
8520 | else | |
8521 | { | |
8522 | imm_expr.X_op = O_big; | |
8523 | imm_expr.X_add_number = 4; | |
8524 | if (! target_big_endian) | |
8525 | { | |
8526 | generic_bignum[0] = bfd_getl16 (temp); | |
8527 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
8528 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
8529 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
8530 | } | |
8531 | else | |
8532 | { | |
8533 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
8534 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
8535 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
8536 | generic_bignum[3] = bfd_getb16 (temp); | |
8537 | } | |
8538 | } | |
8539 | } | |
8540 | else | |
8541 | { | |
8542 | const char *newname; | |
8543 | segT new_seg; | |
8544 | ||
8545 | /* Switch to the right section. */ | |
8546 | seg = now_seg; | |
8547 | subseg = now_subseg; | |
8548 | switch (*args) | |
8549 | { | |
8550 | default: /* unused default case avoids warnings. */ | |
8551 | case 'L': | |
8552 | newname = RDATA_SECTION_NAME; | |
bb2d6cd7 GK |
8553 | if ((USE_GLOBAL_POINTER_OPT && g_switch_value >= 8) |
8554 | || mips_pic == EMBEDDED_PIC) | |
252b5132 RH |
8555 | newname = ".lit8"; |
8556 | break; | |
8557 | case 'F': | |
bb2d6cd7 GK |
8558 | if (mips_pic == EMBEDDED_PIC) |
8559 | newname = ".lit8"; | |
8560 | else | |
8561 | newname = RDATA_SECTION_NAME; | |
252b5132 RH |
8562 | break; |
8563 | case 'l': | |
8564 | assert (!USE_GLOBAL_POINTER_OPT | |
8565 | || g_switch_value >= 4); | |
8566 | newname = ".lit4"; | |
8567 | break; | |
8568 | } | |
8569 | new_seg = subseg_new (newname, (subsegT) 0); | |
8570 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
8571 | bfd_set_section_flags (stdoutput, new_seg, | |
8572 | (SEC_ALLOC | |
8573 | | SEC_LOAD | |
8574 | | SEC_READONLY | |
8575 | | SEC_DATA)); | |
8576 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
8577 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
8578 | && strcmp (TARGET_OS, "elf") != 0) | |
8579 | record_alignment (new_seg, 4); | |
8580 | else | |
8581 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
8582 | if (seg == now_seg) | |
8583 | as_bad (_("Can't use floating point insn in this section")); | |
8584 | ||
8585 | /* Set the argument to the current address in the | |
8586 | section. */ | |
8587 | offset_expr.X_op = O_symbol; | |
8588 | offset_expr.X_add_symbol = | |
8589 | symbol_new ("L0\001", now_seg, | |
8590 | (valueT) frag_now_fix (), frag_now); | |
8591 | offset_expr.X_add_number = 0; | |
8592 | ||
8593 | /* Put the floating point number into the section. */ | |
8594 | p = frag_more ((int) length); | |
8595 | memcpy (p, temp, length); | |
8596 | ||
8597 | /* Switch back to the original section. */ | |
8598 | subseg_set (seg, subseg); | |
8599 | } | |
8600 | } | |
8601 | continue; | |
8602 | ||
8603 | case 'i': /* 16 bit unsigned immediate */ | |
8604 | case 'j': /* 16 bit signed immediate */ | |
f6688943 | 8605 | *imm_reloc = BFD_RELOC_LO16; |
252b5132 | 8606 | c = my_getSmallExpression (&imm_expr, s); |
fb1b3232 | 8607 | if (c != S_EX_NONE) |
252b5132 | 8608 | { |
fb1b3232 | 8609 | if (c != S_EX_LO) |
252b5132 | 8610 | { |
fdb987ee RS |
8611 | if (c == S_EX_HI) |
8612 | { | |
8613 | *imm_reloc = BFD_RELOC_HI16_S; | |
8614 | imm_unmatched_hi = true; | |
8615 | } | |
ad8d3bb3 | 8616 | #ifdef OBJ_ELF |
fb1b3232 | 8617 | else if (c == S_EX_HIGHEST) |
98d3f06f | 8618 | *imm_reloc = BFD_RELOC_MIPS_HIGHEST; |
fb1b3232 | 8619 | else if (c == S_EX_HIGHER) |
98d3f06f | 8620 | *imm_reloc = BFD_RELOC_MIPS_HIGHER; |
ad8d3bb3 TS |
8621 | else if (c == S_EX_GP_REL) |
8622 | { | |
8623 | /* This occurs in NewABI only. */ | |
8624 | c = my_getSmallExpression (&imm_expr, s); | |
8625 | if (c != S_EX_NEG) | |
8626 | as_bad (_("bad composition of relocations")); | |
8627 | else | |
8628 | { | |
8629 | c = my_getSmallExpression (&imm_expr, s); | |
8630 | if (c != S_EX_LO) | |
8631 | as_bad (_("bad composition of relocations")); | |
8632 | else | |
8633 | { | |
8634 | imm_reloc[0] = BFD_RELOC_GPREL16; | |
8635 | imm_reloc[1] = BFD_RELOC_MIPS_SUB; | |
8636 | imm_reloc[2] = BFD_RELOC_LO16; | |
8637 | } | |
8638 | } | |
8639 | } | |
8640 | #endif | |
252b5132 | 8641 | else |
f6688943 | 8642 | *imm_reloc = BFD_RELOC_HI16; |
252b5132 RH |
8643 | } |
8644 | else if (imm_expr.X_op == O_constant) | |
8645 | imm_expr.X_add_number &= 0xffff; | |
8646 | } | |
8647 | if (*args == 'i') | |
8648 | { | |
fb1b3232 | 8649 | if ((c == S_EX_NONE && imm_expr.X_op != O_constant) |
252b5132 | 8650 | || ((imm_expr.X_add_number < 0 |
beae10d5 KH |
8651 | || imm_expr.X_add_number >= 0x10000) |
8652 | && imm_expr.X_op == O_constant)) | |
252b5132 RH |
8653 | { |
8654 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
8655 | !strcmp (insn->name, insn[1].name)) | |
8656 | break; | |
2ae7e77b AH |
8657 | if (imm_expr.X_op == O_constant |
8658 | || imm_expr.X_op == O_big) | |
252b5132 RH |
8659 | as_bad (_("16 bit expression not in range 0..65535")); |
8660 | } | |
8661 | } | |
8662 | else | |
8663 | { | |
8664 | int more; | |
8665 | offsetT max; | |
8666 | ||
8667 | /* The upper bound should be 0x8000, but | |
8668 | unfortunately the MIPS assembler accepts numbers | |
8669 | from 0x8000 to 0xffff and sign extends them, and | |
8670 | we want to be compatible. We only permit this | |
8671 | extended range for an instruction which does not | |
8672 | provide any further alternates, since those | |
8673 | alternates may handle other cases. People should | |
8674 | use the numbers they mean, rather than relying on | |
8675 | a mysterious sign extension. */ | |
8676 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
8677 | strcmp (insn->name, insn[1].name) == 0); | |
8678 | if (more) | |
8679 | max = 0x8000; | |
8680 | else | |
8681 | max = 0x10000; | |
fb1b3232 | 8682 | if ((c == S_EX_NONE && imm_expr.X_op != O_constant) |
252b5132 | 8683 | || ((imm_expr.X_add_number < -0x8000 |
beae10d5 KH |
8684 | || imm_expr.X_add_number >= max) |
8685 | && imm_expr.X_op == O_constant) | |
252b5132 RH |
8686 | || (more |
8687 | && imm_expr.X_add_number < 0 | |
ca4e0257 | 8688 | && HAVE_64BIT_GPRS |
252b5132 RH |
8689 | && imm_expr.X_unsigned |
8690 | && sizeof (imm_expr.X_add_number) <= 4)) | |
8691 | { | |
8692 | if (more) | |
8693 | break; | |
2ae7e77b AH |
8694 | if (imm_expr.X_op == O_constant |
8695 | || imm_expr.X_op == O_big) | |
252b5132 RH |
8696 | as_bad (_("16 bit expression not in range -32768..32767")); |
8697 | } | |
8698 | } | |
8699 | s = expr_end; | |
8700 | continue; | |
8701 | ||
8702 | case 'o': /* 16 bit offset */ | |
8703 | c = my_getSmallExpression (&offset_expr, s); | |
8704 | ||
8705 | /* If this value won't fit into a 16 bit offset, then go | |
8706 | find a macro that will generate the 32 bit offset | |
afdbd6d0 | 8707 | code pattern. */ |
fb1b3232 | 8708 | if (c == S_EX_NONE |
252b5132 RH |
8709 | && (offset_expr.X_op != O_constant |
8710 | || offset_expr.X_add_number >= 0x8000 | |
afdbd6d0 | 8711 | || offset_expr.X_add_number < -0x8000)) |
252b5132 RH |
8712 | break; |
8713 | ||
fb1b3232 | 8714 | if (c == S_EX_HI) |
252b5132 RH |
8715 | { |
8716 | if (offset_expr.X_op != O_constant) | |
8717 | break; | |
8718 | offset_expr.X_add_number = | |
8719 | (offset_expr.X_add_number >> 16) & 0xffff; | |
8720 | } | |
f6688943 | 8721 | *offset_reloc = BFD_RELOC_LO16; |
252b5132 RH |
8722 | s = expr_end; |
8723 | continue; | |
8724 | ||
8725 | case 'p': /* pc relative offset */ | |
cb56d3d3 | 8726 | if (mips_pic == EMBEDDED_PIC) |
f6688943 | 8727 | *offset_reloc = BFD_RELOC_16_PCREL_S2; |
cb56d3d3 | 8728 | else |
f6688943 | 8729 | *offset_reloc = BFD_RELOC_16_PCREL; |
252b5132 RH |
8730 | my_getExpression (&offset_expr, s); |
8731 | s = expr_end; | |
8732 | continue; | |
8733 | ||
8734 | case 'u': /* upper 16 bits */ | |
8735 | c = my_getSmallExpression (&imm_expr, s); | |
f6688943 | 8736 | *imm_reloc = BFD_RELOC_LO16; |
e7d556df | 8737 | if (c != S_EX_NONE) |
252b5132 | 8738 | { |
fb1b3232 | 8739 | if (c != S_EX_LO) |
252b5132 | 8740 | { |
fdb987ee | 8741 | if (c == S_EX_HI) |
252b5132 | 8742 | { |
f6688943 | 8743 | *imm_reloc = BFD_RELOC_HI16_S; |
252b5132 RH |
8744 | imm_unmatched_hi = true; |
8745 | } | |
645dc66c TS |
8746 | #ifdef OBJ_ELF |
8747 | else if (c == S_EX_HIGHEST) | |
98d3f06f | 8748 | *imm_reloc = BFD_RELOC_MIPS_HIGHEST; |
ad8d3bb3 TS |
8749 | else if (c == S_EX_GP_REL) |
8750 | { | |
8751 | /* This occurs in NewABI only. */ | |
8752 | c = my_getSmallExpression (&imm_expr, s); | |
8753 | if (c != S_EX_NEG) | |
8754 | as_bad (_("bad composition of relocations")); | |
8755 | else | |
8756 | { | |
8757 | c = my_getSmallExpression (&imm_expr, s); | |
8758 | if (c != S_EX_HI) | |
8759 | as_bad (_("bad composition of relocations")); | |
8760 | else | |
8761 | { | |
8762 | imm_reloc[0] = BFD_RELOC_GPREL16; | |
8763 | imm_reloc[1] = BFD_RELOC_MIPS_SUB; | |
8764 | imm_reloc[2] = BFD_RELOC_HI16_S; | |
8765 | } | |
8766 | } | |
8767 | } | |
8768 | #endif | |
252b5132 | 8769 | else |
f6688943 | 8770 | *imm_reloc = BFD_RELOC_HI16; |
252b5132 RH |
8771 | } |
8772 | else if (imm_expr.X_op == O_constant) | |
8773 | imm_expr.X_add_number &= 0xffff; | |
8774 | } | |
fdb987ee RS |
8775 | else if (imm_expr.X_op == O_constant |
8776 | && (imm_expr.X_add_number < 0 | |
8777 | || imm_expr.X_add_number >= 0x10000)) | |
252b5132 RH |
8778 | as_bad (_("lui expression not in range 0..65535")); |
8779 | s = expr_end; | |
8780 | continue; | |
8781 | ||
8782 | case 'a': /* 26 bit address */ | |
8783 | my_getExpression (&offset_expr, s); | |
8784 | s = expr_end; | |
f6688943 | 8785 | *offset_reloc = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
8786 | continue; |
8787 | ||
8788 | case 'N': /* 3 bit branch condition code */ | |
8789 | case 'M': /* 3 bit compare condition code */ | |
8790 | if (strncmp (s, "$fcc", 4) != 0) | |
8791 | break; | |
8792 | s += 4; | |
8793 | regno = 0; | |
8794 | do | |
8795 | { | |
8796 | regno *= 10; | |
8797 | regno += *s - '0'; | |
8798 | ++s; | |
8799 | } | |
3882b010 | 8800 | while (ISDIGIT (*s)); |
252b5132 RH |
8801 | if (regno > 7) |
8802 | as_bad (_("invalid condition code register $fcc%d"), regno); | |
8803 | if (*args == 'N') | |
8804 | ip->insn_opcode |= regno << OP_SH_BCC; | |
8805 | else | |
8806 | ip->insn_opcode |= regno << OP_SH_CCC; | |
beae10d5 | 8807 | continue; |
252b5132 | 8808 | |
156c2f8b NC |
8809 | case 'H': |
8810 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
8811 | s += 2; | |
3882b010 | 8812 | if (ISDIGIT (*s)) |
156c2f8b NC |
8813 | { |
8814 | c = 0; | |
8815 | do | |
8816 | { | |
8817 | c *= 10; | |
8818 | c += *s - '0'; | |
8819 | ++s; | |
8820 | } | |
3882b010 | 8821 | while (ISDIGIT (*s)); |
156c2f8b NC |
8822 | } |
8823 | else | |
8824 | c = 8; /* Invalid sel value. */ | |
8825 | ||
8826 | if (c > 7) | |
8827 | as_bad (_("invalid coprocessor sub-selection value (0-7)")); | |
8828 | ip->insn_opcode |= c; | |
8829 | continue; | |
8830 | ||
252b5132 RH |
8831 | default: |
8832 | as_bad (_("bad char = '%c'\n"), *args); | |
8833 | internalError (); | |
8834 | } | |
8835 | break; | |
8836 | } | |
8837 | /* Args don't match. */ | |
8838 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
8839 | !strcmp (insn->name, insn[1].name)) | |
8840 | { | |
8841 | ++insn; | |
8842 | s = argsStart; | |
268f6bed | 8843 | insn_error = _("illegal operands"); |
252b5132 RH |
8844 | continue; |
8845 | } | |
268f6bed L |
8846 | if (save_c) |
8847 | *(--s) = save_c; | |
252b5132 RH |
8848 | insn_error = _("illegal operands"); |
8849 | return; | |
8850 | } | |
8851 | } | |
8852 | ||
8853 | /* This routine assembles an instruction into its binary format when | |
8854 | assembling for the mips16. As a side effect, it sets one of the | |
8855 | global variables imm_reloc or offset_reloc to the type of | |
8856 | relocation to do if one of the operands is an address expression. | |
8857 | It also sets mips16_small and mips16_ext if the user explicitly | |
8858 | requested a small or extended instruction. */ | |
8859 | ||
8860 | static void | |
8861 | mips16_ip (str, ip) | |
8862 | char *str; | |
8863 | struct mips_cl_insn *ip; | |
8864 | { | |
8865 | char *s; | |
8866 | const char *args; | |
8867 | struct mips_opcode *insn; | |
8868 | char *argsstart; | |
8869 | unsigned int regno; | |
8870 | unsigned int lastregno = 0; | |
8871 | char *s_reset; | |
8872 | ||
8873 | insn_error = NULL; | |
8874 | ||
8875 | mips16_small = false; | |
8876 | mips16_ext = false; | |
8877 | ||
3882b010 | 8878 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
8879 | ; |
8880 | switch (*s) | |
8881 | { | |
8882 | case '\0': | |
8883 | break; | |
8884 | ||
8885 | case ' ': | |
8886 | *s++ = '\0'; | |
8887 | break; | |
8888 | ||
8889 | case '.': | |
8890 | if (s[1] == 't' && s[2] == ' ') | |
8891 | { | |
8892 | *s = '\0'; | |
8893 | mips16_small = true; | |
8894 | s += 3; | |
8895 | break; | |
8896 | } | |
8897 | else if (s[1] == 'e' && s[2] == ' ') | |
8898 | { | |
8899 | *s = '\0'; | |
8900 | mips16_ext = true; | |
8901 | s += 3; | |
8902 | break; | |
8903 | } | |
8904 | /* Fall through. */ | |
8905 | default: | |
8906 | insn_error = _("unknown opcode"); | |
8907 | return; | |
8908 | } | |
8909 | ||
8910 | if (mips_opts.noautoextend && ! mips16_ext) | |
8911 | mips16_small = true; | |
8912 | ||
8913 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
8914 | { | |
8915 | insn_error = _("unrecognized opcode"); | |
8916 | return; | |
8917 | } | |
8918 | ||
8919 | argsstart = s; | |
8920 | for (;;) | |
8921 | { | |
8922 | assert (strcmp (insn->name, str) == 0); | |
8923 | ||
8924 | ip->insn_mo = insn; | |
8925 | ip->insn_opcode = insn->match; | |
8926 | ip->use_extend = false; | |
8927 | imm_expr.X_op = O_absent; | |
f6688943 TS |
8928 | imm_reloc[0] = BFD_RELOC_UNUSED; |
8929 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
8930 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 | 8931 | offset_expr.X_op = O_absent; |
f6688943 TS |
8932 | offset_reloc[0] = BFD_RELOC_UNUSED; |
8933 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
8934 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
8935 | for (args = insn->args; 1; ++args) |
8936 | { | |
8937 | int c; | |
8938 | ||
8939 | if (*s == ' ') | |
8940 | ++s; | |
8941 | ||
8942 | /* In this switch statement we call break if we did not find | |
8943 | a match, continue if we did find a match, or return if we | |
8944 | are done. */ | |
8945 | ||
8946 | c = *args; | |
8947 | switch (c) | |
8948 | { | |
8949 | case '\0': | |
8950 | if (*s == '\0') | |
8951 | { | |
8952 | /* Stuff the immediate value in now, if we can. */ | |
8953 | if (imm_expr.X_op == O_constant | |
f6688943 | 8954 | && *imm_reloc > BFD_RELOC_UNUSED |
252b5132 RH |
8955 | && insn->pinfo != INSN_MACRO) |
8956 | { | |
c4e7957c | 8957 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
252b5132 RH |
8958 | imm_expr.X_add_number, true, mips16_small, |
8959 | mips16_ext, &ip->insn_opcode, | |
8960 | &ip->use_extend, &ip->extend); | |
8961 | imm_expr.X_op = O_absent; | |
f6688943 | 8962 | *imm_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
8963 | } |
8964 | ||
8965 | return; | |
8966 | } | |
8967 | break; | |
8968 | ||
8969 | case ',': | |
8970 | if (*s++ == c) | |
8971 | continue; | |
8972 | s--; | |
8973 | switch (*++args) | |
8974 | { | |
8975 | case 'v': | |
8976 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
8977 | continue; | |
8978 | case 'w': | |
8979 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
8980 | continue; | |
8981 | } | |
8982 | break; | |
8983 | ||
8984 | case '(': | |
8985 | case ')': | |
8986 | if (*s++ == c) | |
8987 | continue; | |
8988 | break; | |
8989 | ||
8990 | case 'v': | |
8991 | case 'w': | |
8992 | if (s[0] != '$') | |
8993 | { | |
8994 | if (c == 'v') | |
8995 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
8996 | else | |
8997 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
8998 | ++args; | |
8999 | continue; | |
9000 | } | |
9001 | /* Fall through. */ | |
9002 | case 'x': | |
9003 | case 'y': | |
9004 | case 'z': | |
9005 | case 'Z': | |
9006 | case '0': | |
9007 | case 'S': | |
9008 | case 'R': | |
9009 | case 'X': | |
9010 | case 'Y': | |
9011 | if (s[0] != '$') | |
9012 | break; | |
9013 | s_reset = s; | |
3882b010 | 9014 | if (ISDIGIT (s[1])) |
252b5132 RH |
9015 | { |
9016 | ++s; | |
9017 | regno = 0; | |
9018 | do | |
9019 | { | |
9020 | regno *= 10; | |
9021 | regno += *s - '0'; | |
9022 | ++s; | |
9023 | } | |
3882b010 | 9024 | while (ISDIGIT (*s)); |
252b5132 RH |
9025 | if (regno > 31) |
9026 | { | |
9027 | as_bad (_("invalid register number (%d)"), regno); | |
9028 | regno = 2; | |
9029 | } | |
9030 | } | |
9031 | else | |
9032 | { | |
76db943d TS |
9033 | if (s[1] == 'r' && s[2] == 'a') |
9034 | { | |
9035 | s += 3; | |
9036 | regno = RA; | |
9037 | } | |
9038 | else if (s[1] == 'f' && s[2] == 'p') | |
252b5132 RH |
9039 | { |
9040 | s += 3; | |
9041 | regno = FP; | |
9042 | } | |
9043 | else if (s[1] == 's' && s[2] == 'p') | |
9044 | { | |
9045 | s += 3; | |
9046 | regno = SP; | |
9047 | } | |
9048 | else if (s[1] == 'g' && s[2] == 'p') | |
9049 | { | |
9050 | s += 3; | |
9051 | regno = GP; | |
9052 | } | |
9053 | else if (s[1] == 'a' && s[2] == 't') | |
9054 | { | |
9055 | s += 3; | |
9056 | regno = AT; | |
9057 | } | |
9058 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
9059 | { | |
9060 | s += 4; | |
9061 | regno = KT0; | |
9062 | } | |
9063 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
9064 | { | |
9065 | s += 4; | |
9066 | regno = KT1; | |
9067 | } | |
85b51719 TS |
9068 | else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o') |
9069 | { | |
9070 | s += 5; | |
9071 | regno = ZERO; | |
9072 | } | |
252b5132 RH |
9073 | else |
9074 | break; | |
9075 | } | |
9076 | ||
9077 | if (*s == ' ') | |
9078 | ++s; | |
9079 | if (args[1] != *s) | |
9080 | { | |
9081 | if (c == 'v' || c == 'w') | |
9082 | { | |
9083 | regno = mips16_to_32_reg_map[lastregno]; | |
9084 | s = s_reset; | |
f9419b05 | 9085 | ++args; |
252b5132 RH |
9086 | } |
9087 | } | |
9088 | ||
9089 | switch (c) | |
9090 | { | |
9091 | case 'x': | |
9092 | case 'y': | |
9093 | case 'z': | |
9094 | case 'v': | |
9095 | case 'w': | |
9096 | case 'Z': | |
9097 | regno = mips32_to_16_reg_map[regno]; | |
9098 | break; | |
9099 | ||
9100 | case '0': | |
9101 | if (regno != 0) | |
9102 | regno = ILLEGAL_REG; | |
9103 | break; | |
9104 | ||
9105 | case 'S': | |
9106 | if (regno != SP) | |
9107 | regno = ILLEGAL_REG; | |
9108 | break; | |
9109 | ||
9110 | case 'R': | |
9111 | if (regno != RA) | |
9112 | regno = ILLEGAL_REG; | |
9113 | break; | |
9114 | ||
9115 | case 'X': | |
9116 | case 'Y': | |
9117 | if (regno == AT && ! mips_opts.noat) | |
9118 | as_warn (_("used $at without \".set noat\"")); | |
9119 | break; | |
9120 | ||
9121 | default: | |
9122 | internalError (); | |
9123 | } | |
9124 | ||
9125 | if (regno == ILLEGAL_REG) | |
9126 | break; | |
9127 | ||
9128 | switch (c) | |
9129 | { | |
9130 | case 'x': | |
9131 | case 'v': | |
9132 | ip->insn_opcode |= regno << MIPS16OP_SH_RX; | |
9133 | break; | |
9134 | case 'y': | |
9135 | case 'w': | |
9136 | ip->insn_opcode |= regno << MIPS16OP_SH_RY; | |
9137 | break; | |
9138 | case 'z': | |
9139 | ip->insn_opcode |= regno << MIPS16OP_SH_RZ; | |
9140 | break; | |
9141 | case 'Z': | |
9142 | ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z; | |
9143 | case '0': | |
9144 | case 'S': | |
9145 | case 'R': | |
9146 | break; | |
9147 | case 'X': | |
9148 | ip->insn_opcode |= regno << MIPS16OP_SH_REGR32; | |
9149 | break; | |
9150 | case 'Y': | |
9151 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
9152 | ip->insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
9153 | break; | |
9154 | default: | |
9155 | internalError (); | |
9156 | } | |
9157 | ||
9158 | lastregno = regno; | |
9159 | continue; | |
9160 | ||
9161 | case 'P': | |
9162 | if (strncmp (s, "$pc", 3) == 0) | |
9163 | { | |
9164 | s += 3; | |
9165 | continue; | |
9166 | } | |
9167 | break; | |
9168 | ||
9169 | case '<': | |
9170 | case '>': | |
9171 | case '[': | |
9172 | case ']': | |
9173 | case '4': | |
9174 | case '5': | |
9175 | case 'H': | |
9176 | case 'W': | |
9177 | case 'D': | |
9178 | case 'j': | |
9179 | case '8': | |
9180 | case 'V': | |
9181 | case 'C': | |
9182 | case 'U': | |
9183 | case 'k': | |
9184 | case 'K': | |
9185 | if (s[0] == '%' | |
9186 | && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0) | |
9187 | { | |
9188 | /* This is %gprel(SYMBOL). We need to read SYMBOL, | |
9189 | and generate the appropriate reloc. If the text | |
9190 | inside %gprel is not a symbol name with an | |
9191 | optional offset, then we generate a normal reloc | |
9192 | and will probably fail later. */ | |
9193 | my_getExpression (&imm_expr, s + sizeof "%gprel" - 1); | |
9194 | if (imm_expr.X_op == O_symbol) | |
9195 | { | |
9196 | mips16_ext = true; | |
f6688943 | 9197 | *imm_reloc = BFD_RELOC_MIPS16_GPREL; |
252b5132 RH |
9198 | s = expr_end; |
9199 | ip->use_extend = true; | |
9200 | ip->extend = 0; | |
9201 | continue; | |
9202 | } | |
9203 | } | |
9204 | else | |
9205 | { | |
9206 | /* Just pick up a normal expression. */ | |
9207 | my_getExpression (&imm_expr, s); | |
9208 | } | |
9209 | ||
9210 | if (imm_expr.X_op == O_register) | |
9211 | { | |
9212 | /* What we thought was an expression turned out to | |
9213 | be a register. */ | |
9214 | ||
9215 | if (s[0] == '(' && args[1] == '(') | |
9216 | { | |
9217 | /* It looks like the expression was omitted | |
9218 | before a register indirection, which means | |
9219 | that the expression is implicitly zero. We | |
9220 | still set up imm_expr, so that we handle | |
9221 | explicit extensions correctly. */ | |
9222 | imm_expr.X_op = O_constant; | |
9223 | imm_expr.X_add_number = 0; | |
f6688943 | 9224 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9225 | continue; |
9226 | } | |
9227 | ||
9228 | break; | |
9229 | } | |
9230 | ||
9231 | /* We need to relax this instruction. */ | |
f6688943 | 9232 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9233 | s = expr_end; |
9234 | continue; | |
9235 | ||
9236 | case 'p': | |
9237 | case 'q': | |
9238 | case 'A': | |
9239 | case 'B': | |
9240 | case 'E': | |
9241 | /* We use offset_reloc rather than imm_reloc for the PC | |
9242 | relative operands. This lets macros with both | |
9243 | immediate and address operands work correctly. */ | |
9244 | my_getExpression (&offset_expr, s); | |
9245 | ||
9246 | if (offset_expr.X_op == O_register) | |
9247 | break; | |
9248 | ||
9249 | /* We need to relax this instruction. */ | |
f6688943 | 9250 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9251 | s = expr_end; |
9252 | continue; | |
9253 | ||
9254 | case '6': /* break code */ | |
9255 | my_getExpression (&imm_expr, s); | |
9256 | check_absolute_expr (ip, &imm_expr); | |
9257 | if ((unsigned long) imm_expr.X_add_number > 63) | |
9258 | { | |
9259 | as_warn (_("Invalid value for `%s' (%lu)"), | |
9260 | ip->insn_mo->name, | |
9261 | (unsigned long) imm_expr.X_add_number); | |
9262 | imm_expr.X_add_number &= 0x3f; | |
9263 | } | |
9264 | ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6; | |
9265 | imm_expr.X_op = O_absent; | |
9266 | s = expr_end; | |
9267 | continue; | |
9268 | ||
9269 | case 'a': /* 26 bit address */ | |
9270 | my_getExpression (&offset_expr, s); | |
9271 | s = expr_end; | |
f6688943 | 9272 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
9273 | ip->insn_opcode <<= 16; |
9274 | continue; | |
9275 | ||
9276 | case 'l': /* register list for entry macro */ | |
9277 | case 'L': /* register list for exit macro */ | |
9278 | { | |
9279 | int mask; | |
9280 | ||
9281 | if (c == 'l') | |
9282 | mask = 0; | |
9283 | else | |
9284 | mask = 7 << 3; | |
9285 | while (*s != '\0') | |
9286 | { | |
9287 | int freg, reg1, reg2; | |
9288 | ||
9289 | while (*s == ' ' || *s == ',') | |
9290 | ++s; | |
9291 | if (*s != '$') | |
9292 | { | |
9293 | as_bad (_("can't parse register list")); | |
9294 | break; | |
9295 | } | |
9296 | ++s; | |
9297 | if (*s != 'f') | |
9298 | freg = 0; | |
9299 | else | |
9300 | { | |
9301 | freg = 1; | |
9302 | ++s; | |
9303 | } | |
9304 | reg1 = 0; | |
3882b010 | 9305 | while (ISDIGIT (*s)) |
252b5132 RH |
9306 | { |
9307 | reg1 *= 10; | |
9308 | reg1 += *s - '0'; | |
9309 | ++s; | |
9310 | } | |
9311 | if (*s == ' ') | |
9312 | ++s; | |
9313 | if (*s != '-') | |
9314 | reg2 = reg1; | |
9315 | else | |
9316 | { | |
9317 | ++s; | |
9318 | if (*s != '$') | |
9319 | break; | |
9320 | ++s; | |
9321 | if (freg) | |
9322 | { | |
9323 | if (*s == 'f') | |
9324 | ++s; | |
9325 | else | |
9326 | { | |
9327 | as_bad (_("invalid register list")); | |
9328 | break; | |
9329 | } | |
9330 | } | |
9331 | reg2 = 0; | |
3882b010 | 9332 | while (ISDIGIT (*s)) |
252b5132 RH |
9333 | { |
9334 | reg2 *= 10; | |
9335 | reg2 += *s - '0'; | |
9336 | ++s; | |
9337 | } | |
9338 | } | |
9339 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
9340 | { | |
9341 | mask &= ~ (7 << 3); | |
9342 | mask |= 5 << 3; | |
9343 | } | |
9344 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
9345 | { | |
9346 | mask &= ~ (7 << 3); | |
9347 | mask |= 6 << 3; | |
9348 | } | |
9349 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
9350 | mask |= (reg2 - 3) << 3; | |
9351 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
9352 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 9353 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
9354 | mask |= 1; |
9355 | else | |
9356 | { | |
9357 | as_bad (_("invalid register list")); | |
9358 | break; | |
9359 | } | |
9360 | } | |
9361 | /* The mask is filled in in the opcode table for the | |
9362 | benefit of the disassembler. We remove it before | |
9363 | applying the actual mask. */ | |
9364 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
9365 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
9366 | } | |
9367 | continue; | |
9368 | ||
9369 | case 'e': /* extend code */ | |
9370 | my_getExpression (&imm_expr, s); | |
9371 | check_absolute_expr (ip, &imm_expr); | |
9372 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
9373 | { | |
9374 | as_warn (_("Invalid value for `%s' (%lu)"), | |
9375 | ip->insn_mo->name, | |
9376 | (unsigned long) imm_expr.X_add_number); | |
9377 | imm_expr.X_add_number &= 0x7ff; | |
9378 | } | |
9379 | ip->insn_opcode |= imm_expr.X_add_number; | |
9380 | imm_expr.X_op = O_absent; | |
9381 | s = expr_end; | |
9382 | continue; | |
9383 | ||
9384 | default: | |
9385 | internalError (); | |
9386 | } | |
9387 | break; | |
9388 | } | |
9389 | ||
9390 | /* Args don't match. */ | |
9391 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
9392 | strcmp (insn->name, insn[1].name) == 0) | |
9393 | { | |
9394 | ++insn; | |
9395 | s = argsstart; | |
9396 | continue; | |
9397 | } | |
9398 | ||
9399 | insn_error = _("illegal operands"); | |
9400 | ||
9401 | return; | |
9402 | } | |
9403 | } | |
9404 | ||
9405 | /* This structure holds information we know about a mips16 immediate | |
9406 | argument type. */ | |
9407 | ||
e972090a NC |
9408 | struct mips16_immed_operand |
9409 | { | |
252b5132 RH |
9410 | /* The type code used in the argument string in the opcode table. */ |
9411 | int type; | |
9412 | /* The number of bits in the short form of the opcode. */ | |
9413 | int nbits; | |
9414 | /* The number of bits in the extended form of the opcode. */ | |
9415 | int extbits; | |
9416 | /* The amount by which the short form is shifted when it is used; | |
9417 | for example, the sw instruction has a shift count of 2. */ | |
9418 | int shift; | |
9419 | /* The amount by which the short form is shifted when it is stored | |
9420 | into the instruction code. */ | |
9421 | int op_shift; | |
9422 | /* Non-zero if the short form is unsigned. */ | |
9423 | int unsp; | |
9424 | /* Non-zero if the extended form is unsigned. */ | |
9425 | int extu; | |
9426 | /* Non-zero if the value is PC relative. */ | |
9427 | int pcrel; | |
9428 | }; | |
9429 | ||
9430 | /* The mips16 immediate operand types. */ | |
9431 | ||
9432 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
9433 | { | |
9434 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
9435 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
9436 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
9437 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
9438 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
9439 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9440 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9441 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9442 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9443 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
9444 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9445 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9446 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9447 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
9448 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
9449 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
9450 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
9451 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
9452 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
9453 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
9454 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
9455 | }; | |
9456 | ||
9457 | #define MIPS16_NUM_IMMED \ | |
9458 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
9459 | ||
9460 | /* Handle a mips16 instruction with an immediate value. This or's the | |
9461 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
9462 | whether an extended value is needed; if one is needed, it sets | |
9463 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
9464 | If SMALL is true, an unextended opcode was explicitly requested. | |
9465 | If EXT is true, an extended opcode was explicitly requested. If | |
9466 | WARN is true, warn if EXT does not match reality. */ | |
9467 | ||
9468 | static void | |
9469 | mips16_immed (file, line, type, val, warn, small, ext, insn, use_extend, | |
9470 | extend) | |
9471 | char *file; | |
9472 | unsigned int line; | |
9473 | int type; | |
9474 | offsetT val; | |
9475 | boolean warn; | |
9476 | boolean small; | |
9477 | boolean ext; | |
9478 | unsigned long *insn; | |
9479 | boolean *use_extend; | |
9480 | unsigned short *extend; | |
9481 | { | |
9482 | register const struct mips16_immed_operand *op; | |
9483 | int mintiny, maxtiny; | |
9484 | boolean needext; | |
9485 | ||
9486 | op = mips16_immed_operands; | |
9487 | while (op->type != type) | |
9488 | { | |
9489 | ++op; | |
9490 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
9491 | } | |
9492 | ||
9493 | if (op->unsp) | |
9494 | { | |
9495 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
9496 | { | |
9497 | mintiny = 1; | |
9498 | maxtiny = 1 << op->nbits; | |
9499 | } | |
9500 | else | |
9501 | { | |
9502 | mintiny = 0; | |
9503 | maxtiny = (1 << op->nbits) - 1; | |
9504 | } | |
9505 | } | |
9506 | else | |
9507 | { | |
9508 | mintiny = - (1 << (op->nbits - 1)); | |
9509 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
9510 | } | |
9511 | ||
9512 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
9513 | if (type == 'p' || type == 'q') | |
9514 | val /= 2; | |
9515 | ||
9516 | if ((val & ((1 << op->shift) - 1)) != 0 | |
9517 | || val < (mintiny << op->shift) | |
9518 | || val > (maxtiny << op->shift)) | |
9519 | needext = true; | |
9520 | else | |
9521 | needext = false; | |
9522 | ||
9523 | if (warn && ext && ! needext) | |
beae10d5 KH |
9524 | as_warn_where (file, line, |
9525 | _("extended operand requested but not required")); | |
252b5132 RH |
9526 | if (small && needext) |
9527 | as_bad_where (file, line, _("invalid unextended operand value")); | |
9528 | ||
9529 | if (small || (! ext && ! needext)) | |
9530 | { | |
9531 | int insnval; | |
9532 | ||
9533 | *use_extend = false; | |
9534 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); | |
9535 | insnval <<= op->op_shift; | |
9536 | *insn |= insnval; | |
9537 | } | |
9538 | else | |
9539 | { | |
9540 | long minext, maxext; | |
9541 | int extval; | |
9542 | ||
9543 | if (op->extu) | |
9544 | { | |
9545 | minext = 0; | |
9546 | maxext = (1 << op->extbits) - 1; | |
9547 | } | |
9548 | else | |
9549 | { | |
9550 | minext = - (1 << (op->extbits - 1)); | |
9551 | maxext = (1 << (op->extbits - 1)) - 1; | |
9552 | } | |
9553 | if (val < minext || val > maxext) | |
9554 | as_bad_where (file, line, | |
9555 | _("operand value out of range for instruction")); | |
9556 | ||
9557 | *use_extend = true; | |
9558 | if (op->extbits == 16) | |
9559 | { | |
9560 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
9561 | val &= 0x1f; | |
9562 | } | |
9563 | else if (op->extbits == 15) | |
9564 | { | |
9565 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
9566 | val &= 0xf; | |
9567 | } | |
9568 | else | |
9569 | { | |
9570 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
9571 | val = 0; | |
9572 | } | |
9573 | ||
9574 | *extend = (unsigned short) extval; | |
9575 | *insn |= val; | |
9576 | } | |
9577 | } | |
9578 | \f | |
ad8d3bb3 TS |
9579 | static struct percent_op_match |
9580 | { | |
9581 | const char *str; | |
9582 | const enum small_ex_type type; | |
9583 | } percent_op[] = | |
9584 | { | |
ad8d3bb3 TS |
9585 | {"%lo", S_EX_LO}, |
9586 | #ifdef OBJ_ELF | |
394f9b3a TS |
9587 | {"%call_hi", S_EX_CALL_HI}, |
9588 | {"%call_lo", S_EX_CALL_LO}, | |
ad8d3bb3 TS |
9589 | {"%call16", S_EX_CALL16}, |
9590 | {"%got_disp", S_EX_GOT_DISP}, | |
9591 | {"%got_page", S_EX_GOT_PAGE}, | |
9592 | {"%got_ofst", S_EX_GOT_OFST}, | |
9593 | {"%got_hi", S_EX_GOT_HI}, | |
9594 | {"%got_lo", S_EX_GOT_LO}, | |
394f9b3a TS |
9595 | {"%got", S_EX_GOT}, |
9596 | {"%gp_rel", S_EX_GP_REL}, | |
9597 | {"%half", S_EX_HALF}, | |
ad8d3bb3 | 9598 | {"%highest", S_EX_HIGHEST}, |
394f9b3a TS |
9599 | {"%higher", S_EX_HIGHER}, |
9600 | {"%neg", S_EX_NEG}, | |
ad8d3bb3 | 9601 | #endif |
394f9b3a | 9602 | {"%hi", S_EX_HI} |
ad8d3bb3 TS |
9603 | }; |
9604 | ||
9605 | /* Parse small expression input. STR gets adjusted to eat up whitespace. | |
9606 | It detects valid "%percent_op(...)" and "($reg)" strings. Percent_op's | |
9607 | can be nested, this is handled by blanking the innermost, parsing the | |
9608 | rest by subsequent calls. */ | |
252b5132 RH |
9609 | |
9610 | static int | |
ad8d3bb3 TS |
9611 | my_getSmallParser (str, len, nestlevel) |
9612 | char **str; | |
9613 | unsigned int *len; | |
9614 | int *nestlevel; | |
252b5132 | 9615 | { |
ad8d3bb3 TS |
9616 | *len = 0; |
9617 | *str += strspn (*str, " \t"); | |
394f9b3a | 9618 | /* Check for expression in parentheses. */ |
ad8d3bb3 | 9619 | if (**str == '(') |
252b5132 | 9620 | { |
ad8d3bb3 TS |
9621 | char *b = *str + 1 + strspn (*str + 1, " \t"); |
9622 | char *e; | |
9623 | ||
9624 | /* Check for base register. */ | |
9625 | if (b[0] == '$') | |
9626 | { | |
9627 | if (strchr (b, ')') | |
9628 | && (e = b + strcspn (b, ") \t")) | |
9629 | && e - b > 1 && e - b < 4) | |
9630 | { | |
98d3f06f KH |
9631 | if ((e - b == 3 |
9632 | && ((b[1] == 'f' && b[2] == 'p') | |
9633 | || (b[1] == 's' && b[2] == 'p') | |
9634 | || (b[1] == 'g' && b[2] == 'p') | |
9635 | || (b[1] == 'a' && b[2] == 't') | |
9636 | || (ISDIGIT (b[1]) | |
9637 | && ISDIGIT (b[2])))) | |
9638 | || (ISDIGIT (b[1]))) | |
9639 | { | |
9640 | *len = strcspn (*str, ")") + 1; | |
9641 | return S_EX_REGISTER; | |
9642 | } | |
ad8d3bb3 TS |
9643 | } |
9644 | } | |
394f9b3a | 9645 | /* Check for percent_op (in parentheses). */ |
ad8d3bb3 TS |
9646 | else if (b[0] == '%') |
9647 | { | |
9648 | *str = b; | |
394f9b3a | 9649 | return my_getPercentOp (str, len, nestlevel); |
ad8d3bb3 | 9650 | } |
76b3015f | 9651 | |
394f9b3a TS |
9652 | /* Some other expression in the parentheses, which can contain |
9653 | parentheses itself. Attempt to find the matching one. */ | |
9654 | { | |
9655 | int pcnt = 1; | |
9656 | char *s; | |
9657 | ||
9658 | *len = 1; | |
9659 | for (s = *str + 1; *s && pcnt; s++, (*len)++) | |
9660 | { | |
9661 | if (*s == '(') | |
f9419b05 | 9662 | ++pcnt; |
394f9b3a | 9663 | else if (*s == ')') |
f9419b05 | 9664 | --pcnt; |
394f9b3a TS |
9665 | } |
9666 | } | |
fb1b3232 | 9667 | } |
394f9b3a | 9668 | /* Check for percent_op (outside of parentheses). */ |
ad8d3bb3 | 9669 | else if (*str[0] == '%') |
394f9b3a TS |
9670 | return my_getPercentOp (str, len, nestlevel); |
9671 | ||
9672 | /* Any other expression. */ | |
9673 | return S_EX_NONE; | |
9674 | } | |
ad8d3bb3 | 9675 | |
394f9b3a TS |
9676 | static int |
9677 | my_getPercentOp (str, len, nestlevel) | |
9678 | char **str; | |
9679 | unsigned int *len; | |
9680 | int *nestlevel; | |
9681 | { | |
9682 | char *tmp = *str + 1; | |
9683 | unsigned int i = 0; | |
ad8d3bb3 | 9684 | |
394f9b3a TS |
9685 | while (ISALPHA (*tmp) || *tmp == '_') |
9686 | { | |
9687 | *tmp = TOLOWER (*tmp); | |
9688 | tmp++; | |
9689 | } | |
9690 | while (i < (sizeof (percent_op) / sizeof (struct percent_op_match))) | |
9691 | { | |
9692 | if (strncmp (*str, percent_op[i].str, strlen (percent_op[i].str))) | |
98d3f06f | 9693 | i++; |
394f9b3a | 9694 | else |
ad8d3bb3 | 9695 | { |
394f9b3a | 9696 | int type = percent_op[i].type; |
ad8d3bb3 | 9697 | |
394f9b3a TS |
9698 | /* Only %hi and %lo are allowed for OldABI. */ |
9699 | if (! HAVE_NEWABI && type != S_EX_HI && type != S_EX_LO) | |
9700 | return S_EX_NONE; | |
ad8d3bb3 | 9701 | |
394f9b3a | 9702 | *len = strlen (percent_op[i].str); |
f9419b05 | 9703 | ++(*nestlevel); |
394f9b3a | 9704 | return type; |
ad8d3bb3 | 9705 | } |
fb1b3232 | 9706 | } |
ad8d3bb3 TS |
9707 | return S_EX_NONE; |
9708 | } | |
9709 | ||
9710 | static int | |
9711 | my_getSmallExpression (ep, str) | |
9712 | expressionS *ep; | |
9713 | char *str; | |
9714 | { | |
9715 | static char *oldstr = NULL; | |
9716 | int c = S_EX_NONE; | |
9717 | int oldc; | |
394f9b3a | 9718 | int nestlevel = -1; |
ad8d3bb3 TS |
9719 | unsigned int len; |
9720 | ||
394f9b3a TS |
9721 | /* Don't update oldstr if the last call had nested percent_op's. We need |
9722 | it to parse the outer ones later. */ | |
ad8d3bb3 TS |
9723 | if (! oldstr) |
9724 | oldstr = str; | |
76b3015f | 9725 | |
ad8d3bb3 | 9726 | do |
fb1b3232 | 9727 | { |
ad8d3bb3 | 9728 | oldc = c; |
394f9b3a | 9729 | c = my_getSmallParser (&str, &len, &nestlevel); |
ad8d3bb3 TS |
9730 | if (c != S_EX_NONE && c != S_EX_REGISTER) |
9731 | str += len; | |
fb1b3232 | 9732 | } |
ad8d3bb3 TS |
9733 | while (c != S_EX_NONE && c != S_EX_REGISTER); |
9734 | ||
394f9b3a | 9735 | if (nestlevel >= 0) |
fb1b3232 | 9736 | { |
394f9b3a TS |
9737 | /* A percent_op was encountered. Don't try to get an expression if |
9738 | it is already blanked out. */ | |
ad8d3bb3 TS |
9739 | if (*(str + strspn (str + 1, " )")) != ')') |
9740 | { | |
9741 | char save; | |
9742 | ||
394f9b3a | 9743 | /* Let my_getExpression() stop at the closing parenthesis. */ |
ad8d3bb3 TS |
9744 | save = *(str + len); |
9745 | *(str + len) = '\0'; | |
9746 | my_getExpression (ep, str); | |
9747 | *(str + len) = save; | |
9748 | } | |
394f9b3a | 9749 | if (nestlevel > 0) |
ad8d3bb3 | 9750 | { |
394f9b3a TS |
9751 | /* Blank out including the % sign and the proper matching |
9752 | parenthesis. */ | |
9753 | int pcnt = 1; | |
9754 | char *s = strrchr (oldstr, '%'); | |
9755 | char *end; | |
9756 | ||
9757 | for (end = strchr (s, '(') + 1; *end && pcnt; end++) | |
9758 | { | |
9759 | if (*end == '(') | |
f9419b05 | 9760 | ++pcnt; |
394f9b3a | 9761 | else if (*end == ')') |
f9419b05 | 9762 | --pcnt; |
394f9b3a TS |
9763 | } |
9764 | ||
9765 | memset (s, ' ', end - s); | |
ad8d3bb3 TS |
9766 | str = oldstr; |
9767 | } | |
9768 | else | |
394f9b3a TS |
9769 | expr_end = str + len; |
9770 | ||
ad8d3bb3 | 9771 | c = oldc; |
fb1b3232 | 9772 | } |
ad8d3bb3 | 9773 | else if (c == S_EX_NONE) |
fb1b3232 | 9774 | { |
ad8d3bb3 | 9775 | my_getExpression (ep, str); |
fb1b3232 | 9776 | } |
ad8d3bb3 | 9777 | else if (c == S_EX_REGISTER) |
fb1b3232 | 9778 | { |
ad8d3bb3 TS |
9779 | ep->X_op = O_constant; |
9780 | expr_end = str; | |
9781 | ep->X_add_symbol = NULL; | |
9782 | ep->X_op_symbol = NULL; | |
9783 | ep->X_add_number = 0; | |
fb1b3232 | 9784 | } |
fb1b3232 TS |
9785 | else |
9786 | { | |
98d3f06f | 9787 | as_fatal (_("internal error")); |
fb1b3232 | 9788 | } |
252b5132 | 9789 | |
394f9b3a TS |
9790 | if (nestlevel <= 0) |
9791 | /* All percent_op's have been handled. */ | |
ad8d3bb3 | 9792 | oldstr = NULL; |
fb1b3232 | 9793 | |
fb1b3232 | 9794 | return c; |
252b5132 RH |
9795 | } |
9796 | ||
9797 | static void | |
9798 | my_getExpression (ep, str) | |
9799 | expressionS *ep; | |
9800 | char *str; | |
9801 | { | |
9802 | char *save_in; | |
98aa84af | 9803 | valueT val; |
252b5132 RH |
9804 | |
9805 | save_in = input_line_pointer; | |
9806 | input_line_pointer = str; | |
9807 | expression (ep); | |
9808 | expr_end = input_line_pointer; | |
9809 | input_line_pointer = save_in; | |
9810 | ||
9811 | /* If we are in mips16 mode, and this is an expression based on `.', | |
9812 | then we bump the value of the symbol by 1 since that is how other | |
9813 | text symbols are handled. We don't bother to handle complex | |
9814 | expressions, just `.' plus or minus a constant. */ | |
9815 | if (mips_opts.mips16 | |
9816 | && ep->X_op == O_symbol | |
9817 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
9818 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
49309057 ILT |
9819 | && symbol_get_frag (ep->X_add_symbol) == frag_now |
9820 | && symbol_constant_p (ep->X_add_symbol) | |
98aa84af AM |
9821 | && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ()) |
9822 | S_SET_VALUE (ep->X_add_symbol, val + 1); | |
252b5132 RH |
9823 | } |
9824 | ||
9825 | /* Turn a string in input_line_pointer into a floating point constant | |
bc0d738a NC |
9826 | of type TYPE, and store the appropriate bytes in *LITP. The number |
9827 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
252b5132 RH |
9828 | returned, or NULL on OK. */ |
9829 | ||
9830 | char * | |
9831 | md_atof (type, litP, sizeP) | |
9832 | int type; | |
9833 | char *litP; | |
9834 | int *sizeP; | |
9835 | { | |
9836 | int prec; | |
9837 | LITTLENUM_TYPE words[4]; | |
9838 | char *t; | |
9839 | int i; | |
9840 | ||
9841 | switch (type) | |
9842 | { | |
9843 | case 'f': | |
9844 | prec = 2; | |
9845 | break; | |
9846 | ||
9847 | case 'd': | |
9848 | prec = 4; | |
9849 | break; | |
9850 | ||
9851 | default: | |
9852 | *sizeP = 0; | |
9853 | return _("bad call to md_atof"); | |
9854 | } | |
9855 | ||
9856 | t = atof_ieee (input_line_pointer, type, words); | |
9857 | if (t) | |
9858 | input_line_pointer = t; | |
9859 | ||
9860 | *sizeP = prec * 2; | |
9861 | ||
9862 | if (! target_big_endian) | |
9863 | { | |
9864 | for (i = prec - 1; i >= 0; i--) | |
9865 | { | |
9866 | md_number_to_chars (litP, (valueT) words[i], 2); | |
9867 | litP += 2; | |
9868 | } | |
9869 | } | |
9870 | else | |
9871 | { | |
9872 | for (i = 0; i < prec; i++) | |
9873 | { | |
9874 | md_number_to_chars (litP, (valueT) words[i], 2); | |
9875 | litP += 2; | |
9876 | } | |
9877 | } | |
bdaaa2e1 | 9878 | |
252b5132 RH |
9879 | return NULL; |
9880 | } | |
9881 | ||
9882 | void | |
9883 | md_number_to_chars (buf, val, n) | |
9884 | char *buf; | |
9885 | valueT val; | |
9886 | int n; | |
9887 | { | |
9888 | if (target_big_endian) | |
9889 | number_to_chars_bigendian (buf, val, n); | |
9890 | else | |
9891 | number_to_chars_littleendian (buf, val, n); | |
9892 | } | |
9893 | \f | |
ae948b86 | 9894 | #ifdef OBJ_ELF |
e013f690 TS |
9895 | static int support_64bit_objects(void) |
9896 | { | |
9897 | const char **list, **l; | |
9898 | ||
9899 | list = bfd_target_list (); | |
9900 | for (l = list; *l != NULL; l++) | |
9901 | #ifdef TE_TMIPS | |
9902 | /* This is traditional mips */ | |
9903 | if (strcmp (*l, "elf64-tradbigmips") == 0 | |
9904 | || strcmp (*l, "elf64-tradlittlemips") == 0) | |
9905 | #else | |
9906 | if (strcmp (*l, "elf64-bigmips") == 0 | |
9907 | || strcmp (*l, "elf64-littlemips") == 0) | |
9908 | #endif | |
9909 | break; | |
9910 | free (list); | |
9911 | return (*l != NULL); | |
9912 | } | |
ae948b86 | 9913 | #endif /* OBJ_ELF */ |
e013f690 | 9914 | |
5a38dc70 | 9915 | const char *md_shortopts = "nO::g::G:"; |
252b5132 | 9916 | |
e972090a NC |
9917 | struct option md_longopts[] = |
9918 | { | |
252b5132 RH |
9919 | #define OPTION_MIPS1 (OPTION_MD_BASE + 1) |
9920 | {"mips0", no_argument, NULL, OPTION_MIPS1}, | |
9921 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
9922 | #define OPTION_MIPS2 (OPTION_MD_BASE + 2) | |
9923 | {"mips2", no_argument, NULL, OPTION_MIPS2}, | |
9924 | #define OPTION_MIPS3 (OPTION_MD_BASE + 3) | |
9925 | {"mips3", no_argument, NULL, OPTION_MIPS3}, | |
9926 | #define OPTION_MIPS4 (OPTION_MD_BASE + 4) | |
9927 | {"mips4", no_argument, NULL, OPTION_MIPS4}, | |
ae948b86 TS |
9928 | #define OPTION_MIPS5 (OPTION_MD_BASE + 5) |
9929 | {"mips5", no_argument, NULL, OPTION_MIPS5}, | |
9930 | #define OPTION_MIPS32 (OPTION_MD_BASE + 6) | |
9931 | {"mips32", no_argument, NULL, OPTION_MIPS32}, | |
9932 | #define OPTION_MIPS64 (OPTION_MD_BASE + 7) | |
9933 | {"mips64", no_argument, NULL, OPTION_MIPS64}, | |
9934 | #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 8) | |
252b5132 | 9935 | {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC}, |
ae948b86 | 9936 | #define OPTION_TRAP (OPTION_MD_BASE + 9) |
252b5132 RH |
9937 | {"trap", no_argument, NULL, OPTION_TRAP}, |
9938 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
ae948b86 | 9939 | #define OPTION_BREAK (OPTION_MD_BASE + 10) |
252b5132 RH |
9940 | {"break", no_argument, NULL, OPTION_BREAK}, |
9941 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
ae948b86 | 9942 | #define OPTION_EB (OPTION_MD_BASE + 11) |
252b5132 | 9943 | {"EB", no_argument, NULL, OPTION_EB}, |
ae948b86 | 9944 | #define OPTION_EL (OPTION_MD_BASE + 12) |
252b5132 | 9945 | {"EL", no_argument, NULL, OPTION_EL}, |
ae948b86 | 9946 | #define OPTION_MIPS16 (OPTION_MD_BASE + 13) |
252b5132 | 9947 | {"mips16", no_argument, NULL, OPTION_MIPS16}, |
ae948b86 | 9948 | #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 14) |
252b5132 | 9949 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, |
ae948b86 | 9950 | #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 15) |
6b76fefe | 9951 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, |
9ee72ff1 TS |
9952 | #define OPTION_MNO_7000_HILO_FIX (OPTION_MD_BASE + 16) |
9953 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
9954 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
ae948b86 TS |
9955 | #define OPTION_FP32 (OPTION_MD_BASE + 17) |
9956 | {"mfp32", no_argument, NULL, OPTION_FP32}, | |
9957 | #define OPTION_GP32 (OPTION_MD_BASE + 18) | |
c97ef257 | 9958 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
ae948b86 | 9959 | #define OPTION_CONSTRUCT_FLOATS (OPTION_MD_BASE + 19) |
119d663a | 9960 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
ae948b86 | 9961 | #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 20) |
119d663a | 9962 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
ae948b86 | 9963 | #define OPTION_MARCH (OPTION_MD_BASE + 21) |
ec68c924 | 9964 | {"march", required_argument, NULL, OPTION_MARCH}, |
ae948b86 | 9965 | #define OPTION_MTUNE (OPTION_MD_BASE + 22) |
ec68c924 | 9966 | {"mtune", required_argument, NULL, OPTION_MTUNE}, |
316f5878 RS |
9967 | #define OPTION_FP64 (OPTION_MD_BASE + 23) |
9968 | {"mfp64", no_argument, NULL, OPTION_FP64}, | |
ae948b86 TS |
9969 | #define OPTION_M4650 (OPTION_MD_BASE + 24) |
9970 | {"m4650", no_argument, NULL, OPTION_M4650}, | |
9971 | #define OPTION_NO_M4650 (OPTION_MD_BASE + 25) | |
9972 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, | |
9973 | #define OPTION_M4010 (OPTION_MD_BASE + 26) | |
9974 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
9975 | #define OPTION_NO_M4010 (OPTION_MD_BASE + 27) | |
9976 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
9977 | #define OPTION_M4100 (OPTION_MD_BASE + 28) | |
9978 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
9979 | #define OPTION_NO_M4100 (OPTION_MD_BASE + 29) | |
9980 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
9981 | #define OPTION_M3900 (OPTION_MD_BASE + 30) | |
9982 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
9983 | #define OPTION_NO_M3900 (OPTION_MD_BASE + 31) | |
9984 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
9985 | #define OPTION_GP64 (OPTION_MD_BASE + 32) | |
9986 | {"mgp64", no_argument, NULL, OPTION_GP64}, | |
1f25f5d3 CD |
9987 | #define OPTION_MIPS3D (OPTION_MD_BASE + 33) |
9988 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, | |
9989 | #define OPTION_NO_MIPS3D (OPTION_MD_BASE + 34) | |
9990 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, | |
deec1734 CD |
9991 | #define OPTION_MDMX (OPTION_MD_BASE + 35) |
9992 | {"mdmx", no_argument, NULL, OPTION_MDMX}, | |
9993 | #define OPTION_NO_MDMX (OPTION_MD_BASE + 36) | |
9994 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, | |
156c2f8b | 9995 | #ifdef OBJ_ELF |
deec1734 | 9996 | #define OPTION_ELF_BASE (OPTION_MD_BASE + 37) |
156c2f8b | 9997 | #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0) |
156c2f8b NC |
9998 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
9999 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
ae948b86 | 10000 | #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1) |
156c2f8b | 10001 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
ae948b86 | 10002 | #define OPTION_XGOT (OPTION_ELF_BASE + 2) |
156c2f8b | 10003 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
ae948b86 TS |
10004 | #define OPTION_MABI (OPTION_ELF_BASE + 3) |
10005 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
10006 | #define OPTION_32 (OPTION_ELF_BASE + 4) | |
156c2f8b | 10007 | {"32", no_argument, NULL, OPTION_32}, |
ae948b86 | 10008 | #define OPTION_N32 (OPTION_ELF_BASE + 5) |
e013f690 | 10009 | {"n32", no_argument, NULL, OPTION_N32}, |
ae948b86 | 10010 | #define OPTION_64 (OPTION_ELF_BASE + 6) |
156c2f8b | 10011 | {"64", no_argument, NULL, OPTION_64}, |
ecb4347a DJ |
10012 | #define OPTION_MDEBUG (OPTION_ELF_BASE + 7) |
10013 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, | |
10014 | #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8) | |
10015 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, | |
ae948b86 | 10016 | #endif /* OBJ_ELF */ |
252b5132 RH |
10017 | {NULL, no_argument, NULL, 0} |
10018 | }; | |
156c2f8b | 10019 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 10020 | |
316f5878 RS |
10021 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
10022 | NEW_VALUE. Warn if another value was already specified. Note: | |
10023 | we have to defer parsing the -march and -mtune arguments in order | |
10024 | to handle 'from-abi' correctly, since the ABI might be specified | |
10025 | in a later argument. */ | |
10026 | ||
10027 | static void | |
10028 | mips_set_option_string (string_ptr, new_value) | |
10029 | const char **string_ptr, *new_value; | |
10030 | { | |
10031 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
10032 | as_warn (_("A different %s was already specified, is now %s"), | |
10033 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
10034 | new_value); | |
10035 | ||
10036 | *string_ptr = new_value; | |
10037 | } | |
10038 | ||
252b5132 RH |
10039 | int |
10040 | md_parse_option (c, arg) | |
10041 | int c; | |
10042 | char *arg; | |
10043 | { | |
10044 | switch (c) | |
10045 | { | |
119d663a NC |
10046 | case OPTION_CONSTRUCT_FLOATS: |
10047 | mips_disable_float_construction = 0; | |
10048 | break; | |
bdaaa2e1 | 10049 | |
119d663a NC |
10050 | case OPTION_NO_CONSTRUCT_FLOATS: |
10051 | mips_disable_float_construction = 1; | |
10052 | break; | |
bdaaa2e1 | 10053 | |
252b5132 RH |
10054 | case OPTION_TRAP: |
10055 | mips_trap = 1; | |
10056 | break; | |
10057 | ||
10058 | case OPTION_BREAK: | |
10059 | mips_trap = 0; | |
10060 | break; | |
10061 | ||
10062 | case OPTION_EB: | |
10063 | target_big_endian = 1; | |
10064 | break; | |
10065 | ||
10066 | case OPTION_EL: | |
10067 | target_big_endian = 0; | |
10068 | break; | |
10069 | ||
39c0a331 L |
10070 | case 'n': |
10071 | warn_nops = 1; | |
10072 | break; | |
10073 | ||
252b5132 RH |
10074 | case 'O': |
10075 | if (arg && arg[1] == '0') | |
10076 | mips_optimize = 1; | |
10077 | else | |
10078 | mips_optimize = 2; | |
10079 | break; | |
10080 | ||
10081 | case 'g': | |
10082 | if (arg == NULL) | |
10083 | mips_debug = 2; | |
10084 | else | |
10085 | mips_debug = atoi (arg); | |
10086 | /* When the MIPS assembler sees -g or -g2, it does not do | |
10087 | optimizations which limit full symbolic debugging. We take | |
10088 | that to be equivalent to -O0. */ | |
10089 | if (mips_debug == 2) | |
10090 | mips_optimize = 1; | |
10091 | break; | |
10092 | ||
10093 | case OPTION_MIPS1: | |
316f5878 | 10094 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
10095 | break; |
10096 | ||
10097 | case OPTION_MIPS2: | |
316f5878 | 10098 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
10099 | break; |
10100 | ||
10101 | case OPTION_MIPS3: | |
316f5878 | 10102 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
10103 | break; |
10104 | ||
10105 | case OPTION_MIPS4: | |
316f5878 | 10106 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
10107 | break; |
10108 | ||
84ea6cf2 | 10109 | case OPTION_MIPS5: |
316f5878 | 10110 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
10111 | break; |
10112 | ||
e7af610e | 10113 | case OPTION_MIPS32: |
316f5878 | 10114 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
10115 | break; |
10116 | ||
84ea6cf2 | 10117 | case OPTION_MIPS64: |
316f5878 | 10118 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
10119 | break; |
10120 | ||
ec68c924 | 10121 | case OPTION_MTUNE: |
316f5878 RS |
10122 | mips_set_option_string (&mips_tune_string, arg); |
10123 | break; | |
ec68c924 | 10124 | |
316f5878 RS |
10125 | case OPTION_MARCH: |
10126 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
10127 | break; |
10128 | ||
10129 | case OPTION_M4650: | |
316f5878 RS |
10130 | mips_set_option_string (&mips_arch_string, "4650"); |
10131 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
10132 | break; |
10133 | ||
10134 | case OPTION_NO_M4650: | |
10135 | break; | |
10136 | ||
10137 | case OPTION_M4010: | |
316f5878 RS |
10138 | mips_set_option_string (&mips_arch_string, "4010"); |
10139 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
10140 | break; |
10141 | ||
10142 | case OPTION_NO_M4010: | |
10143 | break; | |
10144 | ||
10145 | case OPTION_M4100: | |
316f5878 RS |
10146 | mips_set_option_string (&mips_arch_string, "4100"); |
10147 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
10148 | break; |
10149 | ||
10150 | case OPTION_NO_M4100: | |
10151 | break; | |
10152 | ||
252b5132 | 10153 | case OPTION_M3900: |
316f5878 RS |
10154 | mips_set_option_string (&mips_arch_string, "3900"); |
10155 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 10156 | break; |
bdaaa2e1 | 10157 | |
252b5132 RH |
10158 | case OPTION_NO_M3900: |
10159 | break; | |
10160 | ||
deec1734 CD |
10161 | case OPTION_MDMX: |
10162 | mips_opts.ase_mdmx = 1; | |
10163 | break; | |
10164 | ||
10165 | case OPTION_NO_MDMX: | |
10166 | mips_opts.ase_mdmx = 0; | |
10167 | break; | |
10168 | ||
252b5132 RH |
10169 | case OPTION_MIPS16: |
10170 | mips_opts.mips16 = 1; | |
10171 | mips_no_prev_insn (false); | |
10172 | break; | |
10173 | ||
10174 | case OPTION_NO_MIPS16: | |
10175 | mips_opts.mips16 = 0; | |
10176 | mips_no_prev_insn (false); | |
10177 | break; | |
10178 | ||
1f25f5d3 CD |
10179 | case OPTION_MIPS3D: |
10180 | mips_opts.ase_mips3d = 1; | |
10181 | break; | |
10182 | ||
10183 | case OPTION_NO_MIPS3D: | |
10184 | mips_opts.ase_mips3d = 0; | |
10185 | break; | |
10186 | ||
252b5132 RH |
10187 | case OPTION_MEMBEDDED_PIC: |
10188 | mips_pic = EMBEDDED_PIC; | |
10189 | if (USE_GLOBAL_POINTER_OPT && g_switch_seen) | |
10190 | { | |
10191 | as_bad (_("-G may not be used with embedded PIC code")); | |
10192 | return 0; | |
10193 | } | |
10194 | g_switch_value = 0x7fffffff; | |
10195 | break; | |
10196 | ||
0f074f60 | 10197 | #ifdef OBJ_ELF |
252b5132 RH |
10198 | /* When generating ELF code, we permit -KPIC and -call_shared to |
10199 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
10200 | intended to be compatible with Irix 5. */ | |
10201 | case OPTION_CALL_SHARED: | |
10202 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10203 | { | |
10204 | as_bad (_("-call_shared is supported only for ELF format")); | |
10205 | return 0; | |
10206 | } | |
10207 | mips_pic = SVR4_PIC; | |
10208 | if (g_switch_seen && g_switch_value != 0) | |
10209 | { | |
10210 | as_bad (_("-G may not be used with SVR4 PIC code")); | |
10211 | return 0; | |
10212 | } | |
10213 | g_switch_value = 0; | |
10214 | break; | |
10215 | ||
10216 | case OPTION_NON_SHARED: | |
10217 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10218 | { | |
10219 | as_bad (_("-non_shared is supported only for ELF format")); | |
10220 | return 0; | |
10221 | } | |
10222 | mips_pic = NO_PIC; | |
10223 | break; | |
10224 | ||
10225 | /* The -xgot option tells the assembler to use 32 offsets when | |
10226 | accessing the got in SVR4_PIC mode. It is for Irix | |
10227 | compatibility. */ | |
10228 | case OPTION_XGOT: | |
10229 | mips_big_got = 1; | |
10230 | break; | |
0f074f60 | 10231 | #endif /* OBJ_ELF */ |
252b5132 RH |
10232 | |
10233 | case 'G': | |
10234 | if (! USE_GLOBAL_POINTER_OPT) | |
10235 | { | |
10236 | as_bad (_("-G is not supported for this configuration")); | |
10237 | return 0; | |
10238 | } | |
10239 | else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC) | |
10240 | { | |
10241 | as_bad (_("-G may not be used with SVR4 or embedded PIC code")); | |
10242 | return 0; | |
10243 | } | |
10244 | else | |
10245 | g_switch_value = atoi (arg); | |
10246 | g_switch_seen = 1; | |
10247 | break; | |
10248 | ||
0f074f60 | 10249 | #ifdef OBJ_ELF |
34ba82a8 TS |
10250 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
10251 | and -mabi=64. */ | |
252b5132 | 10252 | case OPTION_32: |
34ba82a8 TS |
10253 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10254 | { | |
10255 | as_bad (_("-32 is supported for ELF format only")); | |
10256 | return 0; | |
10257 | } | |
316f5878 | 10258 | mips_abi = O32_ABI; |
252b5132 RH |
10259 | break; |
10260 | ||
e013f690 | 10261 | case OPTION_N32: |
34ba82a8 TS |
10262 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10263 | { | |
10264 | as_bad (_("-n32 is supported for ELF format only")); | |
10265 | return 0; | |
10266 | } | |
316f5878 | 10267 | mips_abi = N32_ABI; |
e013f690 | 10268 | break; |
252b5132 | 10269 | |
e013f690 | 10270 | case OPTION_64: |
34ba82a8 TS |
10271 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10272 | { | |
10273 | as_bad (_("-64 is supported for ELF format only")); | |
10274 | return 0; | |
10275 | } | |
316f5878 | 10276 | mips_abi = N64_ABI; |
e013f690 TS |
10277 | if (! support_64bit_objects()) |
10278 | as_fatal (_("No compiled in support for 64 bit object file format")); | |
252b5132 | 10279 | break; |
ae948b86 | 10280 | #endif /* OBJ_ELF */ |
252b5132 | 10281 | |
c97ef257 | 10282 | case OPTION_GP32: |
a325df1d | 10283 | file_mips_gp32 = 1; |
c97ef257 AH |
10284 | break; |
10285 | ||
10286 | case OPTION_GP64: | |
a325df1d | 10287 | file_mips_gp32 = 0; |
c97ef257 | 10288 | break; |
252b5132 | 10289 | |
ca4e0257 | 10290 | case OPTION_FP32: |
a325df1d | 10291 | file_mips_fp32 = 1; |
316f5878 RS |
10292 | break; |
10293 | ||
10294 | case OPTION_FP64: | |
10295 | file_mips_fp32 = 0; | |
ca4e0257 RS |
10296 | break; |
10297 | ||
ae948b86 | 10298 | #ifdef OBJ_ELF |
252b5132 | 10299 | case OPTION_MABI: |
34ba82a8 TS |
10300 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10301 | { | |
10302 | as_bad (_("-mabi is supported for ELF format only")); | |
10303 | return 0; | |
10304 | } | |
e013f690 | 10305 | if (strcmp (arg, "32") == 0) |
316f5878 | 10306 | mips_abi = O32_ABI; |
e013f690 | 10307 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 10308 | mips_abi = O64_ABI; |
e013f690 | 10309 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 10310 | mips_abi = N32_ABI; |
e013f690 TS |
10311 | else if (strcmp (arg, "64") == 0) |
10312 | { | |
316f5878 | 10313 | mips_abi = N64_ABI; |
e013f690 TS |
10314 | if (! support_64bit_objects()) |
10315 | as_fatal (_("No compiled in support for 64 bit object file " | |
10316 | "format")); | |
10317 | } | |
10318 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 10319 | mips_abi = EABI_ABI; |
e013f690 | 10320 | else |
da0e507f TS |
10321 | { |
10322 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
10323 | return 0; | |
10324 | } | |
252b5132 | 10325 | break; |
e013f690 | 10326 | #endif /* OBJ_ELF */ |
252b5132 | 10327 | |
6b76fefe CM |
10328 | case OPTION_M7000_HILO_FIX: |
10329 | mips_7000_hilo_fix = true; | |
10330 | break; | |
10331 | ||
9ee72ff1 | 10332 | case OPTION_MNO_7000_HILO_FIX: |
6b76fefe CM |
10333 | mips_7000_hilo_fix = false; |
10334 | break; | |
10335 | ||
ecb4347a DJ |
10336 | #ifdef OBJ_ELF |
10337 | case OPTION_MDEBUG: | |
10338 | mips_flag_mdebug = true; | |
10339 | break; | |
10340 | ||
10341 | case OPTION_NO_MDEBUG: | |
10342 | mips_flag_mdebug = false; | |
10343 | break; | |
10344 | #endif /* OBJ_ELF */ | |
10345 | ||
252b5132 RH |
10346 | default: |
10347 | return 0; | |
10348 | } | |
10349 | ||
10350 | return 1; | |
10351 | } | |
316f5878 RS |
10352 | \f |
10353 | /* Set up globals to generate code for the ISA or processor | |
10354 | described by INFO. */ | |
252b5132 | 10355 | |
252b5132 | 10356 | static void |
316f5878 RS |
10357 | mips_set_architecture (info) |
10358 | const struct mips_cpu_info *info; | |
252b5132 | 10359 | { |
316f5878 | 10360 | if (info != 0) |
252b5132 | 10361 | { |
316f5878 RS |
10362 | mips_arch_info = info; |
10363 | mips_arch = info->cpu; | |
10364 | mips_opts.isa = info->isa; | |
252b5132 | 10365 | } |
252b5132 RH |
10366 | } |
10367 | ||
252b5132 | 10368 | |
316f5878 | 10369 | /* Likewise for tuning. */ |
252b5132 | 10370 | |
316f5878 RS |
10371 | static void |
10372 | mips_set_tune (info) | |
10373 | const struct mips_cpu_info *info; | |
10374 | { | |
10375 | if (info != 0) | |
10376 | { | |
10377 | mips_tune_info = info; | |
10378 | mips_tune = info->cpu; | |
10379 | } | |
10380 | } | |
80cc45a5 | 10381 | |
34ba82a8 | 10382 | |
252b5132 | 10383 | void |
e9670677 MR |
10384 | mips_after_parse_args () |
10385 | { | |
e9670677 MR |
10386 | /* GP relative stuff not working for PE */ |
10387 | if (strncmp (TARGET_OS, "pe", 2) == 0 | |
10388 | && g_switch_value != 0) | |
10389 | { | |
10390 | if (g_switch_seen) | |
10391 | as_bad (_("-G not supported in this configuration.")); | |
10392 | g_switch_value = 0; | |
10393 | } | |
10394 | ||
22923709 RS |
10395 | /* The following code determines the architecture and register size. |
10396 | Similar code was added to GCC 3.3 (see override_options() in | |
10397 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
10398 | as much as possible. */ | |
e9670677 | 10399 | |
316f5878 RS |
10400 | if (mips_arch_string != 0) |
10401 | mips_set_architecture (mips_parse_cpu ("-march", mips_arch_string)); | |
e9670677 | 10402 | |
316f5878 RS |
10403 | if (mips_tune_string != 0) |
10404 | mips_set_tune (mips_parse_cpu ("-mtune", mips_tune_string)); | |
e9670677 | 10405 | |
316f5878 | 10406 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 10407 | { |
316f5878 RS |
10408 | /* Handle -mipsN. At this point, file_mips_isa contains the |
10409 | ISA level specified by -mipsN, while mips_opts.isa contains | |
10410 | the -march selection (if any). */ | |
10411 | if (mips_arch_info != 0) | |
e9670677 | 10412 | { |
316f5878 RS |
10413 | /* -march takes precedence over -mipsN, since it is more descriptive. |
10414 | There's no harm in specifying both as long as the ISA levels | |
10415 | are the same. */ | |
10416 | if (file_mips_isa != mips_opts.isa) | |
10417 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), | |
10418 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
10419 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
e9670677 | 10420 | } |
316f5878 RS |
10421 | else |
10422 | mips_set_architecture (mips_cpu_info_from_isa (file_mips_isa)); | |
e9670677 MR |
10423 | } |
10424 | ||
316f5878 RS |
10425 | if (mips_arch_info == 0) |
10426 | mips_set_architecture (mips_parse_cpu ("default CPU", | |
10427 | MIPS_CPU_STRING_DEFAULT)); | |
e9670677 | 10428 | |
316f5878 RS |
10429 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (mips_opts.isa)) |
10430 | as_bad ("-march=%s is not compatible with the selected ABI", | |
10431 | mips_arch_info->name); | |
e9670677 | 10432 | |
316f5878 RS |
10433 | /* Optimize for mips_arch, unless -mtune selects a different processor. */ |
10434 | if (mips_tune_info == 0) | |
10435 | mips_set_tune (mips_arch_info); | |
e9670677 | 10436 | |
316f5878 | 10437 | if (file_mips_gp32 >= 0) |
e9670677 | 10438 | { |
316f5878 RS |
10439 | /* The user specified the size of the integer registers. Make sure |
10440 | it agrees with the ABI and ISA. */ | |
10441 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
10442 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
10443 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
10444 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
10445 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
10446 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
10447 | } |
10448 | else | |
10449 | { | |
316f5878 RS |
10450 | /* Infer the integer register size from the ABI and processor. |
10451 | Restrict ourselves to 32-bit registers if that's all the | |
10452 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
10453 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
10454 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
10455 | } |
10456 | ||
316f5878 RS |
10457 | /* ??? GAS treats single-float processors as though they had 64-bit |
10458 | float registers (although it complains when double-precision | |
10459 | instructions are used). As things stand, saying they have 32-bit | |
10460 | registers would lead to spurious "register must be even" messages. | |
10461 | So here we assume float registers are always the same size as | |
10462 | integer ones, unless the user says otherwise. */ | |
10463 | if (file_mips_fp32 < 0) | |
10464 | file_mips_fp32 = file_mips_gp32; | |
e9670677 | 10465 | |
316f5878 | 10466 | /* End of GCC-shared inference code. */ |
e9670677 | 10467 | |
316f5878 RS |
10468 | /* ??? When do we want this flag to be set? Who uses it? */ |
10469 | if (file_mips_gp32 == 1 | |
10470 | && mips_abi == NO_ABI | |
10471 | && ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
10472 | mips_32bitmode = 1; | |
e9670677 MR |
10473 | |
10474 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
10475 | as_bad (_("trap exception not supported at ISA 1")); | |
10476 | ||
e9670677 MR |
10477 | /* If the selected architecture includes support for ASEs, enable |
10478 | generation of code for them. */ | |
a4672219 TS |
10479 | if (mips_opts.mips16 == -1) |
10480 | mips_opts.mips16 = (CPU_HAS_MIPS16 (mips_arch)) ? 1 : 0; | |
ffdefa66 | 10481 | if (mips_opts.ase_mips3d == -1) |
a4672219 | 10482 | mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (mips_arch)) ? 1 : 0; |
ffdefa66 | 10483 | if (mips_opts.ase_mdmx == -1) |
a4672219 | 10484 | mips_opts.ase_mdmx = (CPU_HAS_MDMX (mips_arch)) ? 1 : 0; |
e9670677 | 10485 | |
e9670677 | 10486 | file_mips_isa = mips_opts.isa; |
a4672219 | 10487 | file_ase_mips16 = mips_opts.mips16; |
e9670677 MR |
10488 | file_ase_mips3d = mips_opts.ase_mips3d; |
10489 | file_ase_mdmx = mips_opts.ase_mdmx; | |
10490 | mips_opts.gp32 = file_mips_gp32; | |
10491 | mips_opts.fp32 = file_mips_fp32; | |
10492 | ||
ecb4347a DJ |
10493 | if (mips_flag_mdebug < 0) |
10494 | { | |
10495 | #ifdef OBJ_MAYBE_ECOFF | |
10496 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) | |
10497 | mips_flag_mdebug = 1; | |
10498 | else | |
10499 | #endif /* OBJ_MAYBE_ECOFF */ | |
10500 | mips_flag_mdebug = 0; | |
10501 | } | |
e9670677 MR |
10502 | } |
10503 | \f | |
10504 | void | |
252b5132 RH |
10505 | mips_init_after_args () |
10506 | { | |
10507 | /* initialize opcodes */ | |
10508 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 10509 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
10510 | } |
10511 | ||
10512 | long | |
10513 | md_pcrel_from (fixP) | |
10514 | fixS *fixP; | |
10515 | { | |
10516 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour | |
10517 | && fixP->fx_addsy != (symbolS *) NULL | |
10518 | && ! S_IS_DEFINED (fixP->fx_addsy)) | |
10519 | { | |
6478892d TS |
10520 | /* This makes a branch to an undefined symbol be a branch to the |
10521 | current location. */ | |
cb56d3d3 | 10522 | if (mips_pic == EMBEDDED_PIC) |
6478892d | 10523 | return 4; |
cb56d3d3 | 10524 | else |
6478892d | 10525 | return 1; |
252b5132 RH |
10526 | } |
10527 | ||
c9914766 | 10528 | /* Return the address of the delay slot. */ |
252b5132 RH |
10529 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; |
10530 | } | |
10531 | ||
252b5132 RH |
10532 | /* This is called before the symbol table is processed. In order to |
10533 | work with gcc when using mips-tfile, we must keep all local labels. | |
10534 | However, in other cases, we want to discard them. If we were | |
10535 | called with -g, but we didn't see any debugging information, it may | |
10536 | mean that gcc is smuggling debugging information through to | |
10537 | mips-tfile, in which case we must generate all local labels. */ | |
10538 | ||
10539 | void | |
10540 | mips_frob_file_before_adjust () | |
10541 | { | |
10542 | #ifndef NO_ECOFF_DEBUGGING | |
10543 | if (ECOFF_DEBUGGING | |
10544 | && mips_debug != 0 | |
10545 | && ! ecoff_debugging_seen) | |
10546 | flag_keep_locals = 1; | |
10547 | #endif | |
10548 | } | |
10549 | ||
10550 | /* Sort any unmatched HI16_S relocs so that they immediately precede | |
94f592af | 10551 | the corresponding LO reloc. This is called before md_apply_fix3 and |
252b5132 RH |
10552 | tc_gen_reloc. Unmatched HI16_S relocs can only be generated by |
10553 | explicit use of the %hi modifier. */ | |
10554 | ||
10555 | void | |
10556 | mips_frob_file () | |
10557 | { | |
10558 | struct mips_hi_fixup *l; | |
10559 | ||
10560 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
10561 | { | |
10562 | segment_info_type *seginfo; | |
10563 | int pass; | |
10564 | ||
10565 | assert (l->fixp->fx_r_type == BFD_RELOC_HI16_S); | |
10566 | ||
10567 | /* Check quickly whether the next fixup happens to be a matching | |
10568 | %lo. */ | |
10569 | if (l->fixp->fx_next != NULL | |
10570 | && l->fixp->fx_next->fx_r_type == BFD_RELOC_LO16 | |
10571 | && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy | |
10572 | && l->fixp->fx_offset == l->fixp->fx_next->fx_offset) | |
10573 | continue; | |
10574 | ||
10575 | /* Look through the fixups for this segment for a matching %lo. | |
10576 | When we find one, move the %hi just in front of it. We do | |
10577 | this in two passes. In the first pass, we try to find a | |
10578 | unique %lo. In the second pass, we permit multiple %hi | |
10579 | relocs for a single %lo (this is a GNU extension). */ | |
10580 | seginfo = seg_info (l->seg); | |
10581 | for (pass = 0; pass < 2; pass++) | |
10582 | { | |
10583 | fixS *f, *prev; | |
10584 | ||
10585 | prev = NULL; | |
10586 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) | |
10587 | { | |
10588 | /* Check whether this is a %lo fixup which matches l->fixp. */ | |
10589 | if (f->fx_r_type == BFD_RELOC_LO16 | |
10590 | && f->fx_addsy == l->fixp->fx_addsy | |
10591 | && f->fx_offset == l->fixp->fx_offset | |
10592 | && (pass == 1 | |
10593 | || prev == NULL | |
10594 | || prev->fx_r_type != BFD_RELOC_HI16_S | |
10595 | || prev->fx_addsy != f->fx_addsy | |
10596 | || prev->fx_offset != f->fx_offset)) | |
10597 | { | |
10598 | fixS **pf; | |
10599 | ||
10600 | /* Move l->fixp before f. */ | |
10601 | for (pf = &seginfo->fix_root; | |
10602 | *pf != l->fixp; | |
10603 | pf = &(*pf)->fx_next) | |
10604 | assert (*pf != NULL); | |
10605 | ||
10606 | *pf = l->fixp->fx_next; | |
10607 | ||
10608 | l->fixp->fx_next = f; | |
10609 | if (prev == NULL) | |
10610 | seginfo->fix_root = l->fixp; | |
10611 | else | |
10612 | prev->fx_next = l->fixp; | |
10613 | ||
10614 | break; | |
10615 | } | |
10616 | ||
10617 | prev = f; | |
10618 | } | |
10619 | ||
10620 | if (f != NULL) | |
10621 | break; | |
10622 | ||
10623 | #if 0 /* GCC code motion plus incomplete dead code elimination | |
10624 | can leave a %hi without a %lo. */ | |
10625 | if (pass == 1) | |
10626 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, | |
10627 | _("Unmatched %%hi reloc")); | |
10628 | #endif | |
10629 | } | |
10630 | } | |
10631 | } | |
10632 | ||
10633 | /* When generating embedded PIC code we need to use a special | |
10634 | relocation to represent the difference of two symbols in the .text | |
10635 | section (switch tables use a difference of this sort). See | |
10636 | include/coff/mips.h for details. This macro checks whether this | |
10637 | fixup requires the special reloc. */ | |
10638 | #define SWITCH_TABLE(fixp) \ | |
10639 | ((fixp)->fx_r_type == BFD_RELOC_32 \ | |
bb2d6cd7 | 10640 | && OUTPUT_FLAVOR != bfd_target_elf_flavour \ |
252b5132 RH |
10641 | && (fixp)->fx_addsy != NULL \ |
10642 | && (fixp)->fx_subsy != NULL \ | |
10643 | && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \ | |
10644 | && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section) | |
10645 | ||
10646 | /* When generating embedded PIC code we must keep all PC relative | |
10647 | relocations, in case the linker has to relax a call. We also need | |
f6688943 TS |
10648 | to keep relocations for switch table entries. |
10649 | ||
10650 | We may have combined relocations without symbols in the N32/N64 ABI. | |
10651 | We have to prevent gas from dropping them. */ | |
252b5132 | 10652 | |
252b5132 RH |
10653 | int |
10654 | mips_force_relocation (fixp) | |
10655 | fixS *fixp; | |
10656 | { | |
10657 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
a161fe53 AM |
10658 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY |
10659 | || S_FORCE_RELOC (fixp->fx_addsy)) | |
252b5132 RH |
10660 | return 1; |
10661 | ||
f6688943 TS |
10662 | if (HAVE_NEWABI |
10663 | && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr | |
10664 | && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB | |
10665 | || fixp->fx_r_type == BFD_RELOC_HI16_S | |
10666 | || fixp->fx_r_type == BFD_RELOC_LO16)) | |
10667 | return 1; | |
10668 | ||
252b5132 RH |
10669 | return (mips_pic == EMBEDDED_PIC |
10670 | && (fixp->fx_pcrel | |
10671 | || SWITCH_TABLE (fixp) | |
10672 | || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S | |
10673 | || fixp->fx_r_type == BFD_RELOC_PCREL_LO16)); | |
10674 | } | |
10675 | ||
add55e1f RS |
10676 | #ifdef OBJ_ELF |
10677 | static int | |
10678 | mips_need_elf_addend_fixup (fixP) | |
10679 | fixS *fixP; | |
10680 | { | |
2d2bf3e0 CD |
10681 | if (S_GET_OTHER (fixP->fx_addsy) == STO_MIPS16) |
10682 | return 1; | |
b25a253c CD |
10683 | if (mips_pic == EMBEDDED_PIC |
10684 | && S_IS_WEAK (fixP->fx_addsy)) | |
10685 | return 1; | |
10686 | if (mips_pic != EMBEDDED_PIC | |
10687 | && (S_IS_WEAK (fixP->fx_addsy) | |
bad9ca53 | 10688 | || S_IS_EXTERNAL (fixP->fx_addsy)) |
2d2bf3e0 CD |
10689 | && !S_IS_COMMON (fixP->fx_addsy)) |
10690 | return 1; | |
10691 | if (symbol_used_in_reloc_p (fixP->fx_addsy) | |
10692 | && (((bfd_get_section_flags (stdoutput, | |
10693 | S_GET_SEGMENT (fixP->fx_addsy)) | |
10694 | & SEC_LINK_ONCE) != 0) | |
10695 | || !strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)), | |
10696 | ".gnu.linkonce", | |
10697 | sizeof (".gnu.linkonce") - 1))) | |
10698 | return 1; | |
10699 | return 0; | |
add55e1f RS |
10700 | } |
10701 | #endif | |
10702 | ||
252b5132 RH |
10703 | /* Apply a fixup to the object file. */ |
10704 | ||
94f592af NC |
10705 | void |
10706 | md_apply_fix3 (fixP, valP, seg) | |
252b5132 | 10707 | fixS *fixP; |
98d3f06f | 10708 | valueT *valP; |
94f592af | 10709 | segT seg ATTRIBUTE_UNUSED; |
252b5132 | 10710 | { |
874e8986 | 10711 | bfd_byte *buf; |
98aa84af AM |
10712 | long insn; |
10713 | valueT value; | |
ed6fb7bd | 10714 | static int previous_fx_r_type = 0; |
252b5132 | 10715 | |
65551fa4 CD |
10716 | /* FIXME: Maybe just return for all reloc types not listed below? |
10717 | Eric Christopher says: "This is stupid, please rewrite md_apply_fix3. */ | |
10718 | if (fixP->fx_r_type == BFD_RELOC_8) | |
10719 | return; | |
10720 | ||
252b5132 RH |
10721 | assert (fixP->fx_size == 4 |
10722 | || fixP->fx_r_type == BFD_RELOC_16 | |
f6688943 TS |
10723 | || fixP->fx_r_type == BFD_RELOC_32 |
10724 | || fixP->fx_r_type == BFD_RELOC_MIPS_JMP | |
10725 | || fixP->fx_r_type == BFD_RELOC_HI16_S | |
10726 | || fixP->fx_r_type == BFD_RELOC_LO16 | |
10727 | || fixP->fx_r_type == BFD_RELOC_GPREL16 | |
76b3015f | 10728 | || fixP->fx_r_type == BFD_RELOC_MIPS_LITERAL |
f6688943 | 10729 | || fixP->fx_r_type == BFD_RELOC_GPREL32 |
252b5132 | 10730 | || fixP->fx_r_type == BFD_RELOC_64 |
f6688943 TS |
10731 | || fixP->fx_r_type == BFD_RELOC_CTOR |
10732 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
10733 | || fixP->fx_r_type == BFD_RELOC_MIPS_HIGHEST | |
10734 | || fixP->fx_r_type == BFD_RELOC_MIPS_HIGHER | |
10735 | || fixP->fx_r_type == BFD_RELOC_MIPS_SCN_DISP | |
10736 | || fixP->fx_r_type == BFD_RELOC_MIPS_REL16 | |
10737 | || fixP->fx_r_type == BFD_RELOC_MIPS_RELGOT | |
252b5132 | 10738 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
438c16b8 TS |
10739 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY |
10740 | || fixP->fx_r_type == BFD_RELOC_MIPS_JALR); | |
252b5132 | 10741 | |
98d3f06f | 10742 | value = *valP; |
252b5132 RH |
10743 | |
10744 | /* If we aren't adjusting this fixup to be against the section | |
10745 | symbol, we need to adjust the value. */ | |
10746 | #ifdef OBJ_ELF | |
10747 | if (fixP->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
bb2d6cd7 | 10748 | { |
add55e1f | 10749 | if (mips_need_elf_addend_fixup (fixP)) |
98aa84af | 10750 | { |
d6e9d61a | 10751 | reloc_howto_type *howto; |
98aa84af | 10752 | valueT symval = S_GET_VALUE (fixP->fx_addsy); |
94f592af | 10753 | |
98aa84af | 10754 | value -= symval; |
d6e9d61a MR |
10755 | |
10756 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
10757 | if (value != 0 && howto->partial_inplace && ! fixP->fx_pcrel) | |
98aa84af AM |
10758 | { |
10759 | /* In this case, the bfd_install_relocation routine will | |
10760 | incorrectly add the symbol value back in. We just want | |
7461da6e | 10761 | the addend to appear in the object file. */ |
98aa84af | 10762 | value -= symval; |
7461da6e RS |
10763 | |
10764 | /* Make sure the addend is still non-zero. If it became zero | |
10765 | after the last operation, set it to a spurious value and | |
10766 | subtract the same value from the object file's contents. */ | |
10767 | if (value == 0) | |
10768 | { | |
10769 | value = 8; | |
10770 | ||
10771 | /* The in-place addends for LO16 relocations are signed; | |
10772 | leave the matching HI16 in-place addends as zero. */ | |
10773 | if (fixP->fx_r_type != BFD_RELOC_HI16_S) | |
10774 | { | |
7461da6e RS |
10775 | bfd_vma contents, mask, field; |
10776 | ||
7461da6e RS |
10777 | contents = bfd_get_bits (fixP->fx_frag->fr_literal |
10778 | + fixP->fx_where, | |
10779 | fixP->fx_size * 8, | |
10780 | target_big_endian); | |
10781 | ||
10782 | /* MASK has bits set where the relocation should go. | |
10783 | FIELD is -value, shifted into the appropriate place | |
10784 | for this relocation. */ | |
10785 | mask = 1 << (howto->bitsize - 1); | |
10786 | mask = (((mask - 1) << 1) | 1) << howto->bitpos; | |
10787 | field = (-value >> howto->rightshift) << howto->bitpos; | |
10788 | ||
10789 | bfd_put_bits ((field & mask) | (contents & ~mask), | |
10790 | fixP->fx_frag->fr_literal + fixP->fx_where, | |
10791 | fixP->fx_size * 8, | |
10792 | target_big_endian); | |
10793 | } | |
10794 | } | |
98aa84af AM |
10795 | } |
10796 | } | |
252b5132 | 10797 | |
bb2d6cd7 GK |
10798 | /* This code was generated using trial and error and so is |
10799 | fragile and not trustworthy. If you change it, you should | |
10800 | rerun the elf-rel, elf-rel2, and empic testcases and ensure | |
10801 | they still pass. */ | |
10802 | if (fixP->fx_pcrel || fixP->fx_subsy != NULL) | |
10803 | { | |
10804 | value += fixP->fx_frag->fr_address + fixP->fx_where; | |
10805 | ||
10806 | /* BFD's REL handling, for MIPS, is _very_ weird. | |
10807 | This gives the right results, but it can't possibly | |
10808 | be the way things are supposed to work. */ | |
cb56d3d3 TS |
10809 | if ((fixP->fx_r_type != BFD_RELOC_16_PCREL |
10810 | && fixP->fx_r_type != BFD_RELOC_16_PCREL_S2) | |
bb2d6cd7 GK |
10811 | || S_GET_SEGMENT (fixP->fx_addsy) != undefined_section) |
10812 | value += fixP->fx_frag->fr_address + fixP->fx_where; | |
10813 | } | |
10814 | } | |
10815 | #endif | |
252b5132 | 10816 | |
94f592af | 10817 | fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc. */ |
252b5132 | 10818 | |
ed6fb7bd SC |
10819 | /* We are not done if this is a composite relocation to set up gp. */ |
10820 | if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel | |
10821 | && !(fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
10822 | || (previous_fx_r_type == BFD_RELOC_MIPS_SUB | |
10823 | && (fixP->fx_r_type == BFD_RELOC_HI16_S | |
10824 | || fixP->fx_r_type == BFD_RELOC_LO16)))) | |
252b5132 | 10825 | fixP->fx_done = 1; |
ed6fb7bd | 10826 | previous_fx_r_type = fixP->fx_r_type; |
252b5132 RH |
10827 | |
10828 | switch (fixP->fx_r_type) | |
10829 | { | |
10830 | case BFD_RELOC_MIPS_JMP: | |
e369bcce TS |
10831 | case BFD_RELOC_MIPS_SHIFT5: |
10832 | case BFD_RELOC_MIPS_SHIFT6: | |
10833 | case BFD_RELOC_MIPS_GOT_DISP: | |
10834 | case BFD_RELOC_MIPS_GOT_PAGE: | |
10835 | case BFD_RELOC_MIPS_GOT_OFST: | |
10836 | case BFD_RELOC_MIPS_SUB: | |
10837 | case BFD_RELOC_MIPS_INSERT_A: | |
10838 | case BFD_RELOC_MIPS_INSERT_B: | |
10839 | case BFD_RELOC_MIPS_DELETE: | |
10840 | case BFD_RELOC_MIPS_HIGHEST: | |
10841 | case BFD_RELOC_MIPS_HIGHER: | |
10842 | case BFD_RELOC_MIPS_SCN_DISP: | |
10843 | case BFD_RELOC_MIPS_REL16: | |
10844 | case BFD_RELOC_MIPS_RELGOT: | |
10845 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
10846 | case BFD_RELOC_HI16: |
10847 | case BFD_RELOC_HI16_S: | |
cdf6fd85 | 10848 | case BFD_RELOC_GPREL16: |
252b5132 RH |
10849 | case BFD_RELOC_MIPS_LITERAL: |
10850 | case BFD_RELOC_MIPS_CALL16: | |
10851 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 10852 | case BFD_RELOC_GPREL32: |
252b5132 RH |
10853 | case BFD_RELOC_MIPS_GOT_HI16: |
10854 | case BFD_RELOC_MIPS_GOT_LO16: | |
10855 | case BFD_RELOC_MIPS_CALL_HI16: | |
10856 | case BFD_RELOC_MIPS_CALL_LO16: | |
10857 | case BFD_RELOC_MIPS16_GPREL: | |
10858 | if (fixP->fx_pcrel) | |
10859 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10860 | _("Invalid PC relative reloc")); | |
10861 | /* Nothing needed to do. The value comes from the reloc entry */ | |
10862 | break; | |
10863 | ||
10864 | case BFD_RELOC_MIPS16_JMP: | |
10865 | /* We currently always generate a reloc against a symbol, which | |
10866 | means that we don't want an addend even if the symbol is | |
10867 | defined. */ | |
10868 | fixP->fx_addnumber = 0; | |
10869 | break; | |
10870 | ||
10871 | case BFD_RELOC_PCREL_HI16_S: | |
10872 | /* The addend for this is tricky if it is internal, so we just | |
10873 | do everything here rather than in bfd_install_relocation. */ | |
bdaaa2e1 | 10874 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
bb2d6cd7 GK |
10875 | && !fixP->fx_done |
10876 | && value != 0) | |
10877 | break; | |
10878 | if (fixP->fx_addsy | |
10879 | && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0) | |
252b5132 RH |
10880 | { |
10881 | /* For an external symbol adjust by the address to make it | |
10882 | pcrel_offset. We use the address of the RELLO reloc | |
10883 | which follows this one. */ | |
10884 | value += (fixP->fx_next->fx_frag->fr_address | |
10885 | + fixP->fx_next->fx_where); | |
10886 | } | |
e7d556df | 10887 | value = ((value + 0x8000) >> 16) & 0xffff; |
874e8986 | 10888 | buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where; |
252b5132 RH |
10889 | if (target_big_endian) |
10890 | buf += 2; | |
874e8986 | 10891 | md_number_to_chars ((char *) buf, value, 2); |
252b5132 RH |
10892 | break; |
10893 | ||
10894 | case BFD_RELOC_PCREL_LO16: | |
10895 | /* The addend for this is tricky if it is internal, so we just | |
10896 | do everything here rather than in bfd_install_relocation. */ | |
bdaaa2e1 | 10897 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
bb2d6cd7 GK |
10898 | && !fixP->fx_done |
10899 | && value != 0) | |
10900 | break; | |
10901 | if (fixP->fx_addsy | |
10902 | && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0) | |
252b5132 | 10903 | value += fixP->fx_frag->fr_address + fixP->fx_where; |
874e8986 | 10904 | buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where; |
252b5132 RH |
10905 | if (target_big_endian) |
10906 | buf += 2; | |
874e8986 | 10907 | md_number_to_chars ((char *) buf, value, 2); |
252b5132 RH |
10908 | break; |
10909 | ||
10910 | case BFD_RELOC_64: | |
10911 | /* This is handled like BFD_RELOC_32, but we output a sign | |
10912 | extended value if we are only 32 bits. */ | |
10913 | if (fixP->fx_done | |
10914 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
10915 | { | |
10916 | if (8 <= sizeof (valueT)) | |
10917 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
10918 | value, 8); | |
10919 | else | |
10920 | { | |
10921 | long w1, w2; | |
10922 | long hiv; | |
10923 | ||
10924 | w1 = w2 = fixP->fx_where; | |
10925 | if (target_big_endian) | |
10926 | w1 += 4; | |
10927 | else | |
10928 | w2 += 4; | |
10929 | md_number_to_chars (fixP->fx_frag->fr_literal + w1, value, 4); | |
10930 | if ((value & 0x80000000) != 0) | |
10931 | hiv = 0xffffffff; | |
10932 | else | |
10933 | hiv = 0; | |
10934 | md_number_to_chars (fixP->fx_frag->fr_literal + w2, hiv, 4); | |
10935 | } | |
10936 | } | |
10937 | break; | |
10938 | ||
056350c6 | 10939 | case BFD_RELOC_RVA: |
252b5132 RH |
10940 | case BFD_RELOC_32: |
10941 | /* If we are deleting this reloc entry, we must fill in the | |
10942 | value now. This can happen if we have a .word which is not | |
10943 | resolved when it appears but is later defined. We also need | |
10944 | to fill in the value if this is an embedded PIC switch table | |
10945 | entry. */ | |
10946 | if (fixP->fx_done | |
10947 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
10948 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
10949 | value, 4); | |
10950 | break; | |
10951 | ||
10952 | case BFD_RELOC_16: | |
10953 | /* If we are deleting this reloc entry, we must fill in the | |
10954 | value now. */ | |
10955 | assert (fixP->fx_size == 2); | |
10956 | if (fixP->fx_done) | |
10957 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
10958 | value, 2); | |
10959 | break; | |
10960 | ||
10961 | case BFD_RELOC_LO16: | |
10962 | /* When handling an embedded PIC switch statement, we can wind | |
10963 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
10964 | if (fixP->fx_done) | |
10965 | { | |
98aa84af | 10966 | if (value + 0x8000 > 0xffff) |
252b5132 RH |
10967 | as_bad_where (fixP->fx_file, fixP->fx_line, |
10968 | _("relocation overflow")); | |
874e8986 | 10969 | buf = (bfd_byte *) fixP->fx_frag->fr_literal + fixP->fx_where; |
252b5132 RH |
10970 | if (target_big_endian) |
10971 | buf += 2; | |
874e8986 | 10972 | md_number_to_chars ((char *) buf, value, 2); |
252b5132 RH |
10973 | } |
10974 | break; | |
10975 | ||
10976 | case BFD_RELOC_16_PCREL_S2: | |
cb56d3d3 TS |
10977 | if ((value & 0x3) != 0) |
10978 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10979 | _("Branch to odd address (%lx)"), (long) value); | |
10980 | ||
10981 | /* Fall through. */ | |
10982 | ||
10983 | case BFD_RELOC_16_PCREL: | |
252b5132 RH |
10984 | /* |
10985 | * We need to save the bits in the instruction since fixup_segment() | |
10986 | * might be deleting the relocation entry (i.e., a branch within | |
10987 | * the current segment). | |
10988 | */ | |
bb2d6cd7 GK |
10989 | if (!fixP->fx_done && value != 0) |
10990 | break; | |
10991 | /* If 'value' is zero, the remaining reloc code won't actually | |
10992 | do the store, so it must be done here. This is probably | |
10993 | a bug somewhere. */ | |
b25a253c CD |
10994 | if (!fixP->fx_done |
10995 | && (fixP->fx_r_type != BFD_RELOC_16_PCREL_S2 | |
10996 | || fixP->fx_addsy == NULL /* ??? */ | |
10997 | || ! S_IS_DEFINED (fixP->fx_addsy))) | |
bb2d6cd7 | 10998 | value -= fixP->fx_frag->fr_address + fixP->fx_where; |
bdaaa2e1 | 10999 | |
98aa84af | 11000 | value = (offsetT) value >> 2; |
252b5132 RH |
11001 | |
11002 | /* update old instruction data */ | |
874e8986 | 11003 | buf = (bfd_byte *) (fixP->fx_where + fixP->fx_frag->fr_literal); |
252b5132 RH |
11004 | if (target_big_endian) |
11005 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
11006 | else | |
11007 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
11008 | ||
98aa84af | 11009 | if (value + 0x8000 <= 0xffff) |
252b5132 RH |
11010 | insn |= value & 0xffff; |
11011 | else | |
11012 | { | |
11013 | /* The branch offset is too large. If this is an | |
11014 | unconditional branch, and we are not generating PIC code, | |
11015 | we can convert it to an absolute jump instruction. */ | |
11016 | if (mips_pic == NO_PIC | |
11017 | && fixP->fx_done | |
11018 | && fixP->fx_frag->fr_address >= text_section->vma | |
11019 | && (fixP->fx_frag->fr_address | |
11020 | < text_section->vma + text_section->_raw_size) | |
11021 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
11022 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
11023 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
11024 | { | |
11025 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ | |
11026 | insn = 0x0c000000; /* jal */ | |
11027 | else | |
11028 | insn = 0x08000000; /* j */ | |
11029 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
11030 | fixP->fx_done = 0; | |
11031 | fixP->fx_addsy = section_symbol (text_section); | |
11032 | fixP->fx_addnumber = (value << 2) + md_pcrel_from (fixP); | |
11033 | } | |
11034 | else | |
11035 | { | |
11036 | /* FIXME. It would be possible in principle to handle | |
11037 | conditional branches which overflow. They could be | |
11038 | transformed into a branch around a jump. This would | |
11039 | require setting up variant frags for each different | |
11040 | branch type. The native MIPS assembler attempts to | |
11041 | handle these cases, but it appears to do it | |
11042 | incorrectly. */ | |
11043 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11044 | _("Branch out of range")); | |
11045 | } | |
11046 | } | |
11047 | ||
11048 | md_number_to_chars ((char *) buf, (valueT) insn, 4); | |
11049 | break; | |
11050 | ||
11051 | case BFD_RELOC_VTABLE_INHERIT: | |
11052 | fixP->fx_done = 0; | |
11053 | if (fixP->fx_addsy | |
11054 | && !S_IS_DEFINED (fixP->fx_addsy) | |
11055 | && !S_IS_WEAK (fixP->fx_addsy)) | |
11056 | S_SET_WEAK (fixP->fx_addsy); | |
11057 | break; | |
11058 | ||
11059 | case BFD_RELOC_VTABLE_ENTRY: | |
11060 | fixP->fx_done = 0; | |
11061 | break; | |
11062 | ||
11063 | default: | |
11064 | internalError (); | |
11065 | } | |
252b5132 RH |
11066 | } |
11067 | ||
11068 | #if 0 | |
11069 | void | |
11070 | printInsn (oc) | |
11071 | unsigned long oc; | |
11072 | { | |
11073 | const struct mips_opcode *p; | |
11074 | int treg, sreg, dreg, shamt; | |
11075 | short imm; | |
11076 | const char *args; | |
11077 | int i; | |
11078 | ||
11079 | for (i = 0; i < NUMOPCODES; ++i) | |
11080 | { | |
11081 | p = &mips_opcodes[i]; | |
11082 | if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO)) | |
11083 | { | |
11084 | printf ("%08lx %s\t", oc, p->name); | |
11085 | treg = (oc >> 16) & 0x1f; | |
11086 | sreg = (oc >> 21) & 0x1f; | |
11087 | dreg = (oc >> 11) & 0x1f; | |
11088 | shamt = (oc >> 6) & 0x1f; | |
11089 | imm = oc; | |
11090 | for (args = p->args;; ++args) | |
11091 | { | |
11092 | switch (*args) | |
11093 | { | |
11094 | case '\0': | |
11095 | printf ("\n"); | |
11096 | break; | |
11097 | ||
11098 | case ',': | |
11099 | case '(': | |
11100 | case ')': | |
11101 | printf ("%c", *args); | |
11102 | continue; | |
11103 | ||
11104 | case 'r': | |
11105 | assert (treg == sreg); | |
11106 | printf ("$%d,$%d", treg, sreg); | |
11107 | continue; | |
11108 | ||
11109 | case 'd': | |
11110 | case 'G': | |
11111 | printf ("$%d", dreg); | |
11112 | continue; | |
11113 | ||
11114 | case 't': | |
11115 | case 'E': | |
11116 | printf ("$%d", treg); | |
11117 | continue; | |
11118 | ||
11119 | case 'k': | |
11120 | printf ("0x%x", treg); | |
11121 | continue; | |
11122 | ||
11123 | case 'b': | |
11124 | case 's': | |
11125 | printf ("$%d", sreg); | |
11126 | continue; | |
11127 | ||
11128 | case 'a': | |
11129 | printf ("0x%08lx", oc & 0x1ffffff); | |
11130 | continue; | |
11131 | ||
11132 | case 'i': | |
11133 | case 'j': | |
11134 | case 'o': | |
11135 | case 'u': | |
11136 | printf ("%d", imm); | |
11137 | continue; | |
11138 | ||
11139 | case '<': | |
11140 | case '>': | |
11141 | printf ("$%d", shamt); | |
11142 | continue; | |
11143 | ||
11144 | default: | |
11145 | internalError (); | |
11146 | } | |
11147 | break; | |
11148 | } | |
11149 | return; | |
11150 | } | |
11151 | } | |
11152 | printf (_("%08lx UNDEFINED\n"), oc); | |
11153 | } | |
11154 | #endif | |
11155 | ||
11156 | static symbolS * | |
11157 | get_symbol () | |
11158 | { | |
11159 | int c; | |
11160 | char *name; | |
11161 | symbolS *p; | |
11162 | ||
11163 | name = input_line_pointer; | |
11164 | c = get_symbol_end (); | |
11165 | p = (symbolS *) symbol_find_or_make (name); | |
11166 | *input_line_pointer = c; | |
11167 | return p; | |
11168 | } | |
11169 | ||
11170 | /* Align the current frag to a given power of two. The MIPS assembler | |
11171 | also automatically adjusts any preceding label. */ | |
11172 | ||
11173 | static void | |
11174 | mips_align (to, fill, label) | |
11175 | int to; | |
11176 | int fill; | |
11177 | symbolS *label; | |
11178 | { | |
11179 | mips_emit_delays (false); | |
11180 | frag_align (to, fill, 0); | |
11181 | record_alignment (now_seg, to); | |
11182 | if (label != NULL) | |
11183 | { | |
11184 | assert (S_GET_SEGMENT (label) == now_seg); | |
49309057 | 11185 | symbol_set_frag (label, frag_now); |
252b5132 RH |
11186 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
11187 | } | |
11188 | } | |
11189 | ||
11190 | /* Align to a given power of two. .align 0 turns off the automatic | |
11191 | alignment used by the data creating pseudo-ops. */ | |
11192 | ||
11193 | static void | |
11194 | s_align (x) | |
43841e91 | 11195 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
11196 | { |
11197 | register int temp; | |
11198 | register long temp_fill; | |
11199 | long max_alignment = 15; | |
11200 | ||
11201 | /* | |
11202 | ||
11203 | o Note that the assembler pulls down any immediately preceeding label | |
11204 | to the aligned address. | |
11205 | o It's not documented but auto alignment is reinstated by | |
11206 | a .align pseudo instruction. | |
11207 | o Note also that after auto alignment is turned off the mips assembler | |
11208 | issues an error on attempt to assemble an improperly aligned data item. | |
11209 | We don't. | |
11210 | ||
11211 | */ | |
11212 | ||
11213 | temp = get_absolute_expression (); | |
11214 | if (temp > max_alignment) | |
11215 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
11216 | else if (temp < 0) | |
11217 | { | |
11218 | as_warn (_("Alignment negative: 0 assumed.")); | |
11219 | temp = 0; | |
11220 | } | |
11221 | if (*input_line_pointer == ',') | |
11222 | { | |
f9419b05 | 11223 | ++input_line_pointer; |
252b5132 RH |
11224 | temp_fill = get_absolute_expression (); |
11225 | } | |
11226 | else | |
11227 | temp_fill = 0; | |
11228 | if (temp) | |
11229 | { | |
11230 | auto_align = 1; | |
11231 | mips_align (temp, (int) temp_fill, | |
11232 | insn_labels != NULL ? insn_labels->label : NULL); | |
11233 | } | |
11234 | else | |
11235 | { | |
11236 | auto_align = 0; | |
11237 | } | |
11238 | ||
11239 | demand_empty_rest_of_line (); | |
11240 | } | |
11241 | ||
11242 | void | |
11243 | mips_flush_pending_output () | |
11244 | { | |
11245 | mips_emit_delays (false); | |
11246 | mips_clear_insn_labels (); | |
11247 | } | |
11248 | ||
11249 | static void | |
11250 | s_change_sec (sec) | |
11251 | int sec; | |
11252 | { | |
11253 | segT seg; | |
11254 | ||
11255 | /* When generating embedded PIC code, we only use the .text, .lit8, | |
11256 | .sdata and .sbss sections. We change the .data and .rdata | |
11257 | pseudo-ops to use .sdata. */ | |
11258 | if (mips_pic == EMBEDDED_PIC | |
11259 | && (sec == 'd' || sec == 'r')) | |
11260 | sec = 's'; | |
11261 | ||
11262 | #ifdef OBJ_ELF | |
11263 | /* The ELF backend needs to know that we are changing sections, so | |
11264 | that .previous works correctly. We could do something like check | |
b6ff326e | 11265 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
11266 | as it would not be appropriate to use it in the section changing |
11267 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
11268 | This should be cleaner, somehow. */ | |
11269 | obj_elf_section_change_hook (); | |
11270 | #endif | |
11271 | ||
11272 | mips_emit_delays (false); | |
11273 | switch (sec) | |
11274 | { | |
11275 | case 't': | |
11276 | s_text (0); | |
11277 | break; | |
11278 | case 'd': | |
11279 | s_data (0); | |
11280 | break; | |
11281 | case 'b': | |
11282 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
11283 | demand_empty_rest_of_line (); | |
11284 | break; | |
11285 | ||
11286 | case 'r': | |
11287 | if (USE_GLOBAL_POINTER_OPT) | |
11288 | { | |
11289 | seg = subseg_new (RDATA_SECTION_NAME, | |
11290 | (subsegT) get_absolute_expression ()); | |
11291 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
11292 | { | |
11293 | bfd_set_section_flags (stdoutput, seg, | |
11294 | (SEC_ALLOC | |
11295 | | SEC_LOAD | |
11296 | | SEC_READONLY | |
11297 | | SEC_RELOC | |
11298 | | SEC_DATA)); | |
11299 | if (strcmp (TARGET_OS, "elf") != 0) | |
e799a695 | 11300 | record_alignment (seg, 4); |
252b5132 RH |
11301 | } |
11302 | demand_empty_rest_of_line (); | |
11303 | } | |
11304 | else | |
11305 | { | |
11306 | as_bad (_("No read only data section in this object file format")); | |
11307 | demand_empty_rest_of_line (); | |
11308 | return; | |
11309 | } | |
11310 | break; | |
11311 | ||
11312 | case 's': | |
11313 | if (USE_GLOBAL_POINTER_OPT) | |
11314 | { | |
11315 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); | |
11316 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
11317 | { | |
11318 | bfd_set_section_flags (stdoutput, seg, | |
11319 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | |
11320 | | SEC_DATA); | |
11321 | if (strcmp (TARGET_OS, "elf") != 0) | |
e799a695 | 11322 | record_alignment (seg, 4); |
252b5132 RH |
11323 | } |
11324 | demand_empty_rest_of_line (); | |
11325 | break; | |
11326 | } | |
11327 | else | |
11328 | { | |
11329 | as_bad (_("Global pointers not supported; recompile -G 0")); | |
11330 | demand_empty_rest_of_line (); | |
11331 | return; | |
11332 | } | |
11333 | } | |
11334 | ||
11335 | auto_align = 1; | |
11336 | } | |
cca86cc8 SC |
11337 | |
11338 | void | |
11339 | s_change_section (ignore) | |
11340 | int ignore ATTRIBUTE_UNUSED; | |
11341 | { | |
7ed4a06a | 11342 | #ifdef OBJ_ELF |
cca86cc8 SC |
11343 | char *section_name; |
11344 | char c; | |
4cf0dd0d | 11345 | char next_c; |
cca86cc8 SC |
11346 | int section_type; |
11347 | int section_flag; | |
11348 | int section_entry_size; | |
11349 | int section_alignment; | |
cca86cc8 | 11350 | |
7ed4a06a TS |
11351 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
11352 | return; | |
11353 | ||
cca86cc8 SC |
11354 | section_name = input_line_pointer; |
11355 | c = get_symbol_end (); | |
4cf0dd0d | 11356 | next_c = *(input_line_pointer + 1); |
cca86cc8 | 11357 | |
4cf0dd0d TS |
11358 | /* Do we have .section Name<,"flags">? */ |
11359 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 11360 | { |
4cf0dd0d TS |
11361 | /* just after name is now '\0'. */ |
11362 | *input_line_pointer = c; | |
cca86cc8 SC |
11363 | input_line_pointer = section_name; |
11364 | obj_elf_section (ignore); | |
11365 | return; | |
11366 | } | |
11367 | input_line_pointer++; | |
11368 | ||
11369 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
11370 | if (c == ',') | |
11371 | section_type = get_absolute_expression (); | |
11372 | else | |
11373 | section_type = 0; | |
11374 | if (*input_line_pointer++ == ',') | |
11375 | section_flag = get_absolute_expression (); | |
11376 | else | |
11377 | section_flag = 0; | |
11378 | if (*input_line_pointer++ == ',') | |
11379 | section_entry_size = get_absolute_expression (); | |
11380 | else | |
11381 | section_entry_size = 0; | |
11382 | if (*input_line_pointer++ == ',') | |
11383 | section_alignment = get_absolute_expression (); | |
11384 | else | |
11385 | section_alignment = 0; | |
11386 | ||
11387 | obj_elf_change_section (section_name, section_type, section_flag, | |
11388 | section_entry_size, 0, 0, 0); | |
7ed4a06a | 11389 | #endif /* OBJ_ELF */ |
cca86cc8 | 11390 | } |
252b5132 RH |
11391 | |
11392 | void | |
11393 | mips_enable_auto_align () | |
11394 | { | |
11395 | auto_align = 1; | |
11396 | } | |
11397 | ||
11398 | static void | |
11399 | s_cons (log_size) | |
11400 | int log_size; | |
11401 | { | |
11402 | symbolS *label; | |
11403 | ||
11404 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
11405 | mips_emit_delays (false); | |
11406 | if (log_size > 0 && auto_align) | |
11407 | mips_align (log_size, 0, label); | |
11408 | mips_clear_insn_labels (); | |
11409 | cons (1 << log_size); | |
11410 | } | |
11411 | ||
11412 | static void | |
11413 | s_float_cons (type) | |
11414 | int type; | |
11415 | { | |
11416 | symbolS *label; | |
11417 | ||
11418 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
11419 | ||
11420 | mips_emit_delays (false); | |
11421 | ||
11422 | if (auto_align) | |
49309057 ILT |
11423 | { |
11424 | if (type == 'd') | |
11425 | mips_align (3, 0, label); | |
11426 | else | |
11427 | mips_align (2, 0, label); | |
11428 | } | |
252b5132 RH |
11429 | |
11430 | mips_clear_insn_labels (); | |
11431 | ||
11432 | float_cons (type); | |
11433 | } | |
11434 | ||
11435 | /* Handle .globl. We need to override it because on Irix 5 you are | |
11436 | permitted to say | |
11437 | .globl foo .text | |
11438 | where foo is an undefined symbol, to mean that foo should be | |
11439 | considered to be the address of a function. */ | |
11440 | ||
11441 | static void | |
11442 | s_mips_globl (x) | |
43841e91 | 11443 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
11444 | { |
11445 | char *name; | |
11446 | int c; | |
11447 | symbolS *symbolP; | |
11448 | flagword flag; | |
11449 | ||
11450 | name = input_line_pointer; | |
11451 | c = get_symbol_end (); | |
11452 | symbolP = symbol_find_or_make (name); | |
11453 | *input_line_pointer = c; | |
11454 | SKIP_WHITESPACE (); | |
11455 | ||
11456 | /* On Irix 5, every global symbol that is not explicitly labelled as | |
11457 | being a function is apparently labelled as being an object. */ | |
11458 | flag = BSF_OBJECT; | |
11459 | ||
11460 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
11461 | { | |
11462 | char *secname; | |
11463 | asection *sec; | |
11464 | ||
11465 | secname = input_line_pointer; | |
11466 | c = get_symbol_end (); | |
11467 | sec = bfd_get_section_by_name (stdoutput, secname); | |
11468 | if (sec == NULL) | |
11469 | as_bad (_("%s: no such section"), secname); | |
11470 | *input_line_pointer = c; | |
11471 | ||
11472 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
11473 | flag = BSF_FUNCTION; | |
11474 | } | |
11475 | ||
49309057 | 11476 | symbol_get_bfdsym (symbolP)->flags |= flag; |
252b5132 RH |
11477 | |
11478 | S_SET_EXTERNAL (symbolP); | |
11479 | demand_empty_rest_of_line (); | |
11480 | } | |
11481 | ||
11482 | static void | |
11483 | s_option (x) | |
43841e91 | 11484 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
11485 | { |
11486 | char *opt; | |
11487 | char c; | |
11488 | ||
11489 | opt = input_line_pointer; | |
11490 | c = get_symbol_end (); | |
11491 | ||
11492 | if (*opt == 'O') | |
11493 | { | |
11494 | /* FIXME: What does this mean? */ | |
11495 | } | |
11496 | else if (strncmp (opt, "pic", 3) == 0) | |
11497 | { | |
11498 | int i; | |
11499 | ||
11500 | i = atoi (opt + 3); | |
11501 | if (i == 0) | |
11502 | mips_pic = NO_PIC; | |
11503 | else if (i == 2) | |
11504 | mips_pic = SVR4_PIC; | |
11505 | else | |
11506 | as_bad (_(".option pic%d not supported"), i); | |
11507 | ||
11508 | if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC) | |
11509 | { | |
11510 | if (g_switch_seen && g_switch_value != 0) | |
11511 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
11512 | g_switch_value = 0; | |
11513 | bfd_set_gp_size (stdoutput, 0); | |
11514 | } | |
11515 | } | |
11516 | else | |
11517 | as_warn (_("Unrecognized option \"%s\""), opt); | |
11518 | ||
11519 | *input_line_pointer = c; | |
11520 | demand_empty_rest_of_line (); | |
11521 | } | |
11522 | ||
11523 | /* This structure is used to hold a stack of .set values. */ | |
11524 | ||
e972090a NC |
11525 | struct mips_option_stack |
11526 | { | |
252b5132 RH |
11527 | struct mips_option_stack *next; |
11528 | struct mips_set_options options; | |
11529 | }; | |
11530 | ||
11531 | static struct mips_option_stack *mips_opts_stack; | |
11532 | ||
11533 | /* Handle the .set pseudo-op. */ | |
11534 | ||
11535 | static void | |
11536 | s_mipsset (x) | |
43841e91 | 11537 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
11538 | { |
11539 | char *name = input_line_pointer, ch; | |
11540 | ||
11541 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 11542 | ++input_line_pointer; |
252b5132 RH |
11543 | ch = *input_line_pointer; |
11544 | *input_line_pointer = '\0'; | |
11545 | ||
11546 | if (strcmp (name, "reorder") == 0) | |
11547 | { | |
11548 | if (mips_opts.noreorder && prev_nop_frag != NULL) | |
11549 | { | |
11550 | /* If we still have pending nops, we can discard them. The | |
11551 | usual nop handling will insert any that are still | |
bdaaa2e1 | 11552 | needed. */ |
252b5132 RH |
11553 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds |
11554 | * (mips_opts.mips16 ? 2 : 4)); | |
11555 | prev_nop_frag = NULL; | |
11556 | } | |
11557 | mips_opts.noreorder = 0; | |
11558 | } | |
11559 | else if (strcmp (name, "noreorder") == 0) | |
11560 | { | |
11561 | mips_emit_delays (true); | |
11562 | mips_opts.noreorder = 1; | |
11563 | mips_any_noreorder = 1; | |
11564 | } | |
11565 | else if (strcmp (name, "at") == 0) | |
11566 | { | |
11567 | mips_opts.noat = 0; | |
11568 | } | |
11569 | else if (strcmp (name, "noat") == 0) | |
11570 | { | |
11571 | mips_opts.noat = 1; | |
11572 | } | |
11573 | else if (strcmp (name, "macro") == 0) | |
11574 | { | |
11575 | mips_opts.warn_about_macros = 0; | |
11576 | } | |
11577 | else if (strcmp (name, "nomacro") == 0) | |
11578 | { | |
11579 | if (mips_opts.noreorder == 0) | |
11580 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
11581 | mips_opts.warn_about_macros = 1; | |
11582 | } | |
11583 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
11584 | { | |
11585 | mips_opts.nomove = 0; | |
11586 | } | |
11587 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
11588 | { | |
11589 | mips_opts.nomove = 1; | |
11590 | } | |
11591 | else if (strcmp (name, "bopt") == 0) | |
11592 | { | |
11593 | mips_opts.nobopt = 0; | |
11594 | } | |
11595 | else if (strcmp (name, "nobopt") == 0) | |
11596 | { | |
11597 | mips_opts.nobopt = 1; | |
11598 | } | |
11599 | else if (strcmp (name, "mips16") == 0 | |
11600 | || strcmp (name, "MIPS-16") == 0) | |
11601 | mips_opts.mips16 = 1; | |
11602 | else if (strcmp (name, "nomips16") == 0 | |
11603 | || strcmp (name, "noMIPS-16") == 0) | |
11604 | mips_opts.mips16 = 0; | |
1f25f5d3 CD |
11605 | else if (strcmp (name, "mips3d") == 0) |
11606 | mips_opts.ase_mips3d = 1; | |
11607 | else if (strcmp (name, "nomips3d") == 0) | |
11608 | mips_opts.ase_mips3d = 0; | |
a4672219 TS |
11609 | else if (strcmp (name, "mdmx") == 0) |
11610 | mips_opts.ase_mdmx = 1; | |
11611 | else if (strcmp (name, "nomdmx") == 0) | |
11612 | mips_opts.ase_mdmx = 0; | |
252b5132 RH |
11613 | else if (strncmp (name, "mips", 4) == 0) |
11614 | { | |
11615 | int isa; | |
11616 | ||
11617 | /* Permit the user to change the ISA on the fly. Needless to | |
11618 | say, misuse can cause serious problems. */ | |
11619 | isa = atoi (name + 4); | |
553178e4 | 11620 | switch (isa) |
98d3f06f KH |
11621 | { |
11622 | case 0: | |
11623 | mips_opts.gp32 = file_mips_gp32; | |
11624 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f KH |
11625 | break; |
11626 | case 1: | |
11627 | case 2: | |
11628 | case 32: | |
11629 | mips_opts.gp32 = 1; | |
11630 | mips_opts.fp32 = 1; | |
11631 | break; | |
11632 | case 3: | |
11633 | case 4: | |
11634 | case 5: | |
11635 | case 64: | |
98d3f06f KH |
11636 | mips_opts.gp32 = 0; |
11637 | mips_opts.fp32 = 0; | |
11638 | break; | |
11639 | default: | |
11640 | as_bad (_("unknown ISA level %s"), name + 4); | |
11641 | break; | |
11642 | } | |
553178e4 | 11643 | |
e7af610e | 11644 | switch (isa) |
98d3f06f KH |
11645 | { |
11646 | case 0: mips_opts.isa = file_mips_isa; break; | |
11647 | case 1: mips_opts.isa = ISA_MIPS1; break; | |
11648 | case 2: mips_opts.isa = ISA_MIPS2; break; | |
11649 | case 3: mips_opts.isa = ISA_MIPS3; break; | |
11650 | case 4: mips_opts.isa = ISA_MIPS4; break; | |
11651 | case 5: mips_opts.isa = ISA_MIPS5; break; | |
11652 | case 32: mips_opts.isa = ISA_MIPS32; break; | |
11653 | case 64: mips_opts.isa = ISA_MIPS64; break; | |
11654 | default: as_bad (_("unknown ISA level %s"), name + 4); break; | |
11655 | } | |
252b5132 RH |
11656 | } |
11657 | else if (strcmp (name, "autoextend") == 0) | |
11658 | mips_opts.noautoextend = 0; | |
11659 | else if (strcmp (name, "noautoextend") == 0) | |
11660 | mips_opts.noautoextend = 1; | |
11661 | else if (strcmp (name, "push") == 0) | |
11662 | { | |
11663 | struct mips_option_stack *s; | |
11664 | ||
11665 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
11666 | s->next = mips_opts_stack; | |
11667 | s->options = mips_opts; | |
11668 | mips_opts_stack = s; | |
11669 | } | |
11670 | else if (strcmp (name, "pop") == 0) | |
11671 | { | |
11672 | struct mips_option_stack *s; | |
11673 | ||
11674 | s = mips_opts_stack; | |
11675 | if (s == NULL) | |
11676 | as_bad (_(".set pop with no .set push")); | |
11677 | else | |
11678 | { | |
11679 | /* If we're changing the reorder mode we need to handle | |
11680 | delay slots correctly. */ | |
11681 | if (s->options.noreorder && ! mips_opts.noreorder) | |
11682 | mips_emit_delays (true); | |
11683 | else if (! s->options.noreorder && mips_opts.noreorder) | |
11684 | { | |
11685 | if (prev_nop_frag != NULL) | |
11686 | { | |
11687 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds | |
11688 | * (mips_opts.mips16 ? 2 : 4)); | |
11689 | prev_nop_frag = NULL; | |
11690 | } | |
11691 | } | |
11692 | ||
11693 | mips_opts = s->options; | |
11694 | mips_opts_stack = s->next; | |
11695 | free (s); | |
11696 | } | |
11697 | } | |
11698 | else | |
11699 | { | |
11700 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
11701 | } | |
11702 | *input_line_pointer = ch; | |
11703 | demand_empty_rest_of_line (); | |
11704 | } | |
11705 | ||
11706 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
11707 | .option pic2. It means to generate SVR4 PIC calls. */ | |
11708 | ||
11709 | static void | |
11710 | s_abicalls (ignore) | |
43841e91 | 11711 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
11712 | { |
11713 | mips_pic = SVR4_PIC; | |
11714 | if (USE_GLOBAL_POINTER_OPT) | |
11715 | { | |
11716 | if (g_switch_seen && g_switch_value != 0) | |
11717 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
11718 | g_switch_value = 0; | |
11719 | } | |
11720 | bfd_set_gp_size (stdoutput, 0); | |
11721 | demand_empty_rest_of_line (); | |
11722 | } | |
11723 | ||
11724 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
11725 | PIC code. It sets the $gp register for the function based on the | |
11726 | function address, which is in the register named in the argument. | |
11727 | This uses a relocation against _gp_disp, which is handled specially | |
11728 | by the linker. The result is: | |
11729 | lui $gp,%hi(_gp_disp) | |
11730 | addiu $gp,$gp,%lo(_gp_disp) | |
11731 | addu $gp,$gp,.cpload argument | |
11732 | The .cpload argument is normally $25 == $t9. */ | |
11733 | ||
11734 | static void | |
11735 | s_cpload (ignore) | |
43841e91 | 11736 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
11737 | { |
11738 | expressionS ex; | |
11739 | int icnt = 0; | |
11740 | ||
6478892d TS |
11741 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
11742 | .cpload is ignored. */ | |
11743 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
11744 | { |
11745 | s_ignore (0); | |
11746 | return; | |
11747 | } | |
11748 | ||
d3ecfc59 | 11749 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
11750 | if (mips_opts.noreorder == 0) |
11751 | as_warn (_(".cpload not in noreorder section")); | |
11752 | ||
11753 | ex.X_op = O_symbol; | |
11754 | ex.X_add_symbol = symbol_find_or_make ("_gp_disp"); | |
11755 | ex.X_op_symbol = NULL; | |
11756 | ex.X_add_number = 0; | |
11757 | ||
11758 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 11759 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 11760 | |
c9914766 TS |
11761 | macro_build_lui (NULL, &icnt, &ex, mips_gp_register); |
11762 | macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j", | |
11763 | mips_gp_register, mips_gp_register, (int) BFD_RELOC_LO16); | |
252b5132 RH |
11764 | |
11765 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t", | |
c9914766 | 11766 | mips_gp_register, mips_gp_register, tc_get_register (0)); |
252b5132 RH |
11767 | |
11768 | demand_empty_rest_of_line (); | |
11769 | } | |
11770 | ||
6478892d TS |
11771 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
11772 | .cpsetup $reg1, offset|$reg2, label | |
11773 | ||
11774 | If offset is given, this results in: | |
11775 | sd $gp, offset($sp) | |
956cd1d6 | 11776 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
11777 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
11778 | daddu $gp, $gp, $reg1 | |
6478892d TS |
11779 | |
11780 | If $reg2 is given, this results in: | |
11781 | daddu $reg2, $gp, $0 | |
956cd1d6 | 11782 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
11783 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
11784 | daddu $gp, $gp, $reg1 | |
11785 | $reg1 is normally $25 == $t9. */ | |
6478892d TS |
11786 | static void |
11787 | s_cpsetup (ignore) | |
11788 | int ignore ATTRIBUTE_UNUSED; | |
11789 | { | |
11790 | expressionS ex_off; | |
11791 | expressionS ex_sym; | |
11792 | int reg1; | |
11793 | int icnt = 0; | |
f21f8242 | 11794 | char *f; |
6478892d | 11795 | |
8586fc66 | 11796 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
11797 | We also need NewABI support. */ |
11798 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11799 | { | |
11800 | s_ignore (0); | |
11801 | return; | |
11802 | } | |
11803 | ||
11804 | reg1 = tc_get_register (0); | |
11805 | SKIP_WHITESPACE (); | |
11806 | if (*input_line_pointer != ',') | |
11807 | { | |
11808 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
11809 | return; | |
11810 | } | |
11811 | else | |
80245285 | 11812 | ++input_line_pointer; |
6478892d TS |
11813 | SKIP_WHITESPACE (); |
11814 | if (*input_line_pointer == '$') | |
80245285 TS |
11815 | { |
11816 | mips_cpreturn_register = tc_get_register (0); | |
11817 | mips_cpreturn_offset = -1; | |
11818 | } | |
6478892d | 11819 | else |
80245285 TS |
11820 | { |
11821 | mips_cpreturn_offset = get_absolute_expression (); | |
11822 | mips_cpreturn_register = -1; | |
11823 | } | |
6478892d TS |
11824 | SKIP_WHITESPACE (); |
11825 | if (*input_line_pointer != ',') | |
11826 | { | |
11827 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
11828 | return; | |
11829 | } | |
11830 | else | |
f9419b05 | 11831 | ++input_line_pointer; |
6478892d | 11832 | SKIP_WHITESPACE (); |
f21f8242 | 11833 | expression (&ex_sym); |
6478892d TS |
11834 | |
11835 | if (mips_cpreturn_register == -1) | |
11836 | { | |
11837 | ex_off.X_op = O_constant; | |
11838 | ex_off.X_add_symbol = NULL; | |
11839 | ex_off.X_op_symbol = NULL; | |
11840 | ex_off.X_add_number = mips_cpreturn_offset; | |
11841 | ||
11842 | macro_build ((char *) NULL, &icnt, &ex_off, "sd", "t,o(b)", | |
11843 | mips_gp_register, (int) BFD_RELOC_LO16, SP); | |
11844 | } | |
11845 | else | |
11846 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "daddu", | |
11847 | "d,v,t", mips_cpreturn_register, mips_gp_register, 0); | |
11848 | ||
f21f8242 AO |
11849 | /* Ensure there's room for the next two instructions, so that `f' |
11850 | doesn't end up with an address in the wrong frag. */ | |
11851 | frag_grow (8); | |
11852 | f = frag_more (0); | |
6478892d TS |
11853 | macro_build ((char *) NULL, &icnt, &ex_sym, "lui", "t,u", mips_gp_register, |
11854 | (int) BFD_RELOC_GPREL16); | |
f21f8242 AO |
11855 | fix_new (frag_now, f - frag_now->fr_literal, |
11856 | 0, NULL, 0, 0, BFD_RELOC_MIPS_SUB); | |
11857 | fix_new (frag_now, f - frag_now->fr_literal, | |
11858 | 0, NULL, 0, 0, BFD_RELOC_HI16_S); | |
11859 | ||
11860 | f = frag_more (0); | |
6478892d TS |
11861 | macro_build ((char *) NULL, &icnt, &ex_sym, "addiu", "t,r,j", |
11862 | mips_gp_register, mips_gp_register, (int) BFD_RELOC_GPREL16); | |
f21f8242 AO |
11863 | fix_new (frag_now, f - frag_now->fr_literal, |
11864 | 0, NULL, 0, 0, BFD_RELOC_MIPS_SUB); | |
11865 | fix_new (frag_now, f - frag_now->fr_literal, | |
11866 | 0, NULL, 0, 0, BFD_RELOC_LO16); | |
11867 | ||
8586fc66 TS |
11868 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
11869 | HAVE_64BIT_ADDRESSES ? "daddu" : "addu", "d,v,t", | |
11870 | mips_gp_register, mips_gp_register, reg1); | |
6478892d TS |
11871 | |
11872 | demand_empty_rest_of_line (); | |
11873 | } | |
11874 | ||
11875 | static void | |
11876 | s_cplocal (ignore) | |
11877 | int ignore ATTRIBUTE_UNUSED; | |
11878 | { | |
11879 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
11880 | .cplocal is ignored. */ | |
11881 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11882 | { | |
11883 | s_ignore (0); | |
11884 | return; | |
11885 | } | |
11886 | ||
11887 | mips_gp_register = tc_get_register (0); | |
85b51719 | 11888 | demand_empty_rest_of_line (); |
6478892d TS |
11889 | } |
11890 | ||
252b5132 RH |
11891 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
11892 | offset from $sp. The offset is remembered, and after making a PIC | |
11893 | call $gp is restored from that location. */ | |
11894 | ||
11895 | static void | |
11896 | s_cprestore (ignore) | |
43841e91 | 11897 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
11898 | { |
11899 | expressionS ex; | |
11900 | int icnt = 0; | |
11901 | ||
6478892d | 11902 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 11903 | .cprestore is ignored. */ |
6478892d | 11904 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
11905 | { |
11906 | s_ignore (0); | |
11907 | return; | |
11908 | } | |
11909 | ||
11910 | mips_cprestore_offset = get_absolute_expression (); | |
7a621144 | 11911 | mips_cprestore_valid = 1; |
252b5132 RH |
11912 | |
11913 | ex.X_op = O_constant; | |
11914 | ex.X_add_symbol = NULL; | |
11915 | ex.X_op_symbol = NULL; | |
11916 | ex.X_add_number = mips_cprestore_offset; | |
11917 | ||
885add95 CD |
11918 | macro_build_ldst_constoffset ((char *) NULL, &icnt, &ex, |
11919 | HAVE_32BIT_ADDRESSES ? "sw" : "sd", | |
11920 | mips_gp_register, SP); | |
252b5132 RH |
11921 | |
11922 | demand_empty_rest_of_line (); | |
11923 | } | |
11924 | ||
6478892d TS |
11925 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
11926 | was given in the preceeding .gpsetup, it results in: | |
11927 | ld $gp, offset($sp) | |
76b3015f | 11928 | |
6478892d TS |
11929 | If a register $reg2 was given there, it results in: |
11930 | daddiu $gp, $gp, $reg2 | |
11931 | */ | |
11932 | static void | |
11933 | s_cpreturn (ignore) | |
11934 | int ignore ATTRIBUTE_UNUSED; | |
11935 | { | |
11936 | expressionS ex; | |
11937 | int icnt = 0; | |
11938 | ||
11939 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
11940 | We also need NewABI support. */ | |
11941 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11942 | { | |
11943 | s_ignore (0); | |
11944 | return; | |
11945 | } | |
11946 | ||
11947 | if (mips_cpreturn_register == -1) | |
11948 | { | |
11949 | ex.X_op = O_constant; | |
11950 | ex.X_add_symbol = NULL; | |
11951 | ex.X_op_symbol = NULL; | |
11952 | ex.X_add_number = mips_cpreturn_offset; | |
11953 | ||
11954 | macro_build ((char *) NULL, &icnt, &ex, "ld", "t,o(b)", | |
11955 | mips_gp_register, (int) BFD_RELOC_LO16, SP); | |
11956 | } | |
11957 | else | |
11958 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "daddu", | |
11959 | "d,v,t", mips_gp_register, mips_cpreturn_register, 0); | |
11960 | ||
11961 | demand_empty_rest_of_line (); | |
11962 | } | |
11963 | ||
11964 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC | |
11965 | code. It sets the offset to use in gp_rel relocations. */ | |
11966 | ||
11967 | static void | |
11968 | s_gpvalue (ignore) | |
11969 | int ignore ATTRIBUTE_UNUSED; | |
11970 | { | |
11971 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
11972 | We also need NewABI support. */ | |
11973 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11974 | { | |
11975 | s_ignore (0); | |
11976 | return; | |
11977 | } | |
11978 | ||
def2e0dd | 11979 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
11980 | |
11981 | demand_empty_rest_of_line (); | |
11982 | } | |
11983 | ||
252b5132 RH |
11984 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
11985 | code. It generates a 32 bit GP relative reloc. */ | |
11986 | ||
11987 | static void | |
11988 | s_gpword (ignore) | |
43841e91 | 11989 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
11990 | { |
11991 | symbolS *label; | |
11992 | expressionS ex; | |
11993 | char *p; | |
11994 | ||
11995 | /* When not generating PIC code, this is treated as .word. */ | |
11996 | if (mips_pic != SVR4_PIC) | |
11997 | { | |
11998 | s_cons (2); | |
11999 | return; | |
12000 | } | |
12001 | ||
12002 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
12003 | mips_emit_delays (true); | |
12004 | if (auto_align) | |
12005 | mips_align (2, 0, label); | |
12006 | mips_clear_insn_labels (); | |
12007 | ||
12008 | expression (&ex); | |
12009 | ||
12010 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
12011 | { | |
12012 | as_bad (_("Unsupported use of .gpword")); | |
12013 | ignore_rest_of_line (); | |
12014 | } | |
12015 | ||
12016 | p = frag_more (4); | |
12017 | md_number_to_chars (p, (valueT) 0, 4); | |
c9914766 | 12018 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, false, |
cdf6fd85 | 12019 | BFD_RELOC_GPREL32); |
252b5132 RH |
12020 | |
12021 | demand_empty_rest_of_line (); | |
12022 | } | |
12023 | ||
12024 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch | |
12025 | tables in SVR4 PIC code. */ | |
12026 | ||
12027 | static void | |
12028 | s_cpadd (ignore) | |
43841e91 | 12029 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
12030 | { |
12031 | int icnt = 0; | |
12032 | int reg; | |
12033 | ||
6478892d TS |
12034 | /* This is ignored when not generating SVR4 PIC code or if this is NewABI |
12035 | code. */ | |
12036 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
12037 | { |
12038 | s_ignore (0); | |
12039 | return; | |
12040 | } | |
12041 | ||
12042 | /* Add $gp to the register named as an argument. */ | |
12043 | reg = tc_get_register (0); | |
12044 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
ca4e0257 | 12045 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
c9914766 | 12046 | "d,v,t", reg, reg, mips_gp_register); |
252b5132 | 12047 | |
bdaaa2e1 | 12048 | demand_empty_rest_of_line (); |
252b5132 RH |
12049 | } |
12050 | ||
12051 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
12052 | mips16 mode. This permits the linker to handle them specially, | |
12053 | such as generating jalx instructions when needed. We also make | |
12054 | them odd for the duration of the assembly, in order to generate the | |
12055 | right sort of code. We will make them even in the adjust_symtab | |
12056 | routine, while leaving them marked. This is convenient for the | |
12057 | debugger and the disassembler. The linker knows to make them odd | |
12058 | again. */ | |
12059 | ||
12060 | static void | |
12061 | s_insn (ignore) | |
43841e91 | 12062 | int ignore ATTRIBUTE_UNUSED; |
252b5132 | 12063 | { |
f9419b05 | 12064 | mips16_mark_labels (); |
252b5132 RH |
12065 | |
12066 | demand_empty_rest_of_line (); | |
12067 | } | |
12068 | ||
12069 | /* Handle a .stabn directive. We need these in order to mark a label | |
12070 | as being a mips16 text label correctly. Sometimes the compiler | |
12071 | will emit a label, followed by a .stabn, and then switch sections. | |
12072 | If the label and .stabn are in mips16 mode, then the label is | |
12073 | really a mips16 text label. */ | |
12074 | ||
12075 | static void | |
12076 | s_mips_stab (type) | |
12077 | int type; | |
12078 | { | |
f9419b05 | 12079 | if (type == 'n') |
252b5132 RH |
12080 | mips16_mark_labels (); |
12081 | ||
12082 | s_stab (type); | |
12083 | } | |
12084 | ||
12085 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. | |
12086 | */ | |
12087 | ||
12088 | static void | |
12089 | s_mips_weakext (ignore) | |
43841e91 | 12090 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
12091 | { |
12092 | char *name; | |
12093 | int c; | |
12094 | symbolS *symbolP; | |
12095 | expressionS exp; | |
12096 | ||
12097 | name = input_line_pointer; | |
12098 | c = get_symbol_end (); | |
12099 | symbolP = symbol_find_or_make (name); | |
12100 | S_SET_WEAK (symbolP); | |
12101 | *input_line_pointer = c; | |
12102 | ||
12103 | SKIP_WHITESPACE (); | |
12104 | ||
12105 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
12106 | { | |
12107 | if (S_IS_DEFINED (symbolP)) | |
12108 | { | |
956cd1d6 | 12109 | as_bad ("ignoring attempt to redefine symbol %s", |
252b5132 RH |
12110 | S_GET_NAME (symbolP)); |
12111 | ignore_rest_of_line (); | |
12112 | return; | |
12113 | } | |
bdaaa2e1 | 12114 | |
252b5132 RH |
12115 | if (*input_line_pointer == ',') |
12116 | { | |
12117 | ++input_line_pointer; | |
12118 | SKIP_WHITESPACE (); | |
12119 | } | |
bdaaa2e1 | 12120 | |
252b5132 RH |
12121 | expression (&exp); |
12122 | if (exp.X_op != O_symbol) | |
12123 | { | |
12124 | as_bad ("bad .weakext directive"); | |
98d3f06f | 12125 | ignore_rest_of_line (); |
252b5132 RH |
12126 | return; |
12127 | } | |
49309057 | 12128 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
12129 | } |
12130 | ||
12131 | demand_empty_rest_of_line (); | |
12132 | } | |
12133 | ||
12134 | /* Parse a register string into a number. Called from the ECOFF code | |
12135 | to parse .frame. The argument is non-zero if this is the frame | |
12136 | register, so that we can record it in mips_frame_reg. */ | |
12137 | ||
12138 | int | |
12139 | tc_get_register (frame) | |
12140 | int frame; | |
12141 | { | |
12142 | int reg; | |
12143 | ||
12144 | SKIP_WHITESPACE (); | |
12145 | if (*input_line_pointer++ != '$') | |
12146 | { | |
12147 | as_warn (_("expected `$'")); | |
85b51719 | 12148 | reg = ZERO; |
252b5132 | 12149 | } |
3882b010 | 12150 | else if (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
12151 | { |
12152 | reg = get_absolute_expression (); | |
12153 | if (reg < 0 || reg >= 32) | |
12154 | { | |
12155 | as_warn (_("Bad register number")); | |
85b51719 | 12156 | reg = ZERO; |
252b5132 RH |
12157 | } |
12158 | } | |
12159 | else | |
12160 | { | |
76db943d | 12161 | if (strncmp (input_line_pointer, "ra", 2) == 0) |
85b51719 TS |
12162 | { |
12163 | reg = RA; | |
12164 | input_line_pointer += 2; | |
12165 | } | |
76db943d | 12166 | else if (strncmp (input_line_pointer, "fp", 2) == 0) |
85b51719 TS |
12167 | { |
12168 | reg = FP; | |
12169 | input_line_pointer += 2; | |
12170 | } | |
252b5132 | 12171 | else if (strncmp (input_line_pointer, "sp", 2) == 0) |
85b51719 TS |
12172 | { |
12173 | reg = SP; | |
12174 | input_line_pointer += 2; | |
12175 | } | |
252b5132 | 12176 | else if (strncmp (input_line_pointer, "gp", 2) == 0) |
85b51719 TS |
12177 | { |
12178 | reg = GP; | |
12179 | input_line_pointer += 2; | |
12180 | } | |
252b5132 | 12181 | else if (strncmp (input_line_pointer, "at", 2) == 0) |
85b51719 TS |
12182 | { |
12183 | reg = AT; | |
12184 | input_line_pointer += 2; | |
12185 | } | |
12186 | else if (strncmp (input_line_pointer, "kt0", 3) == 0) | |
12187 | { | |
12188 | reg = KT0; | |
12189 | input_line_pointer += 3; | |
12190 | } | |
12191 | else if (strncmp (input_line_pointer, "kt1", 3) == 0) | |
12192 | { | |
12193 | reg = KT1; | |
12194 | input_line_pointer += 3; | |
12195 | } | |
12196 | else if (strncmp (input_line_pointer, "zero", 4) == 0) | |
12197 | { | |
12198 | reg = ZERO; | |
12199 | input_line_pointer += 4; | |
12200 | } | |
252b5132 RH |
12201 | else |
12202 | { | |
12203 | as_warn (_("Unrecognized register name")); | |
85b51719 TS |
12204 | reg = ZERO; |
12205 | while (ISALNUM(*input_line_pointer)) | |
12206 | input_line_pointer++; | |
252b5132 | 12207 | } |
252b5132 RH |
12208 | } |
12209 | if (frame) | |
7a621144 DJ |
12210 | { |
12211 | mips_frame_reg = reg != 0 ? reg : SP; | |
12212 | mips_frame_reg_valid = 1; | |
12213 | mips_cprestore_valid = 0; | |
12214 | } | |
252b5132 RH |
12215 | return reg; |
12216 | } | |
12217 | ||
12218 | valueT | |
12219 | md_section_align (seg, addr) | |
12220 | asection *seg; | |
12221 | valueT addr; | |
12222 | { | |
12223 | int align = bfd_get_section_alignment (stdoutput, seg); | |
12224 | ||
12225 | #ifdef OBJ_ELF | |
12226 | /* We don't need to align ELF sections to the full alignment. | |
12227 | However, Irix 5 may prefer that we align them at least to a 16 | |
12228 | byte boundary. We don't bother to align the sections if we are | |
12229 | targeted for an embedded system. */ | |
12230 | if (strcmp (TARGET_OS, "elf") == 0) | |
12231 | return addr; | |
12232 | if (align > 4) | |
12233 | align = 4; | |
12234 | #endif | |
12235 | ||
12236 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
12237 | } | |
12238 | ||
12239 | /* Utility routine, called from above as well. If called while the | |
12240 | input file is still being read, it's only an approximation. (For | |
12241 | example, a symbol may later become defined which appeared to be | |
12242 | undefined earlier.) */ | |
12243 | ||
12244 | static int | |
12245 | nopic_need_relax (sym, before_relaxing) | |
12246 | symbolS *sym; | |
12247 | int before_relaxing; | |
12248 | { | |
12249 | if (sym == 0) | |
12250 | return 0; | |
12251 | ||
6478892d | 12252 | if (USE_GLOBAL_POINTER_OPT && g_switch_value > 0) |
252b5132 RH |
12253 | { |
12254 | const char *symname; | |
12255 | int change; | |
12256 | ||
c9914766 | 12257 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
12258 | register. It can be if it is smaller than the -G size or if |
12259 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 12260 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
12261 | they can. */ |
12262 | symname = S_GET_NAME (sym); | |
12263 | if (symname != (const char *) NULL | |
12264 | && (strcmp (symname, "eprol") == 0 | |
12265 | || strcmp (symname, "etext") == 0 | |
12266 | || strcmp (symname, "_gp") == 0 | |
12267 | || strcmp (symname, "edata") == 0 | |
12268 | || strcmp (symname, "_fbss") == 0 | |
12269 | || strcmp (symname, "_fdata") == 0 | |
12270 | || strcmp (symname, "_ftext") == 0 | |
12271 | || strcmp (symname, "end") == 0 | |
12272 | || strcmp (symname, "_gp_disp") == 0)) | |
12273 | change = 1; | |
12274 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
12275 | && (0 | |
12276 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
12277 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
12278 | && (symbol_get_obj (sym)->ecoff_extern_size | |
12279 | <= g_switch_value)) | |
252b5132 RH |
12280 | #endif |
12281 | /* We must defer this decision until after the whole | |
12282 | file has been read, since there might be a .extern | |
12283 | after the first use of this symbol. */ | |
12284 | || (before_relaxing | |
12285 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 12286 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
12287 | #endif |
12288 | && S_GET_VALUE (sym) == 0) | |
12289 | || (S_GET_VALUE (sym) != 0 | |
12290 | && S_GET_VALUE (sym) <= g_switch_value))) | |
12291 | change = 0; | |
12292 | else | |
12293 | { | |
12294 | const char *segname; | |
12295 | ||
12296 | segname = segment_name (S_GET_SEGMENT (sym)); | |
12297 | assert (strcmp (segname, ".lit8") != 0 | |
12298 | && strcmp (segname, ".lit4") != 0); | |
12299 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
12300 | && strcmp (segname, ".sbss") != 0 |
12301 | && strncmp (segname, ".sdata.", 7) != 0 | |
12302 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); | |
252b5132 RH |
12303 | } |
12304 | return change; | |
12305 | } | |
12306 | else | |
c9914766 | 12307 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
12308 | return 1; |
12309 | } | |
12310 | ||
12311 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an | |
12312 | extended opcode. SEC is the section the frag is in. */ | |
12313 | ||
12314 | static int | |
12315 | mips16_extended_frag (fragp, sec, stretch) | |
12316 | fragS *fragp; | |
12317 | asection *sec; | |
12318 | long stretch; | |
12319 | { | |
12320 | int type; | |
12321 | register const struct mips16_immed_operand *op; | |
12322 | offsetT val; | |
12323 | int mintiny, maxtiny; | |
12324 | segT symsec; | |
98aa84af | 12325 | fragS *sym_frag; |
252b5132 RH |
12326 | |
12327 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
12328 | return 0; | |
12329 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
12330 | return 1; | |
12331 | ||
12332 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
12333 | op = mips16_immed_operands; | |
12334 | while (op->type != type) | |
12335 | { | |
12336 | ++op; | |
12337 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
12338 | } | |
12339 | ||
12340 | if (op->unsp) | |
12341 | { | |
12342 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
12343 | { | |
12344 | mintiny = 1; | |
12345 | maxtiny = 1 << op->nbits; | |
12346 | } | |
12347 | else | |
12348 | { | |
12349 | mintiny = 0; | |
12350 | maxtiny = (1 << op->nbits) - 1; | |
12351 | } | |
12352 | } | |
12353 | else | |
12354 | { | |
12355 | mintiny = - (1 << (op->nbits - 1)); | |
12356 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
12357 | } | |
12358 | ||
98aa84af | 12359 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 12360 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 12361 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
12362 | |
12363 | if (op->pcrel) | |
12364 | { | |
12365 | addressT addr; | |
12366 | ||
12367 | /* We won't have the section when we are called from | |
12368 | mips_relax_frag. However, we will always have been called | |
12369 | from md_estimate_size_before_relax first. If this is a | |
12370 | branch to a different section, we mark it as such. If SEC is | |
12371 | NULL, and the frag is not marked, then it must be a branch to | |
12372 | the same section. */ | |
12373 | if (sec == NULL) | |
12374 | { | |
12375 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
12376 | return 1; | |
12377 | } | |
12378 | else | |
12379 | { | |
98aa84af | 12380 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
12381 | if (symsec != sec) |
12382 | { | |
12383 | fragp->fr_subtype = | |
12384 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12385 | ||
12386 | /* FIXME: We should support this, and let the linker | |
12387 | catch branches and loads that are out of range. */ | |
12388 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
12389 | _("unsupported PC relative reference to different section")); | |
12390 | ||
12391 | return 1; | |
12392 | } | |
98aa84af AM |
12393 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
12394 | /* Assume non-extended on the first relaxation pass. | |
12395 | The address we have calculated will be bogus if this is | |
12396 | a forward branch to another frag, as the forward frag | |
12397 | will have fr_address == 0. */ | |
12398 | return 0; | |
252b5132 RH |
12399 | } |
12400 | ||
12401 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
12402 | the same section. If the relax_marker of the symbol fragment |
12403 | differs from the relax_marker of this fragment, we have not | |
12404 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
12405 | in STRETCH in order to get a better estimate of the address. |
12406 | This particularly matters because of the shift bits. */ | |
12407 | if (stretch != 0 | |
98aa84af | 12408 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
12409 | { |
12410 | fragS *f; | |
12411 | ||
12412 | /* Adjust stretch for any alignment frag. Note that if have | |
12413 | been expanding the earlier code, the symbol may be | |
12414 | defined in what appears to be an earlier frag. FIXME: | |
12415 | This doesn't handle the fr_subtype field, which specifies | |
12416 | a maximum number of bytes to skip when doing an | |
12417 | alignment. */ | |
98aa84af | 12418 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
12419 | { |
12420 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
12421 | { | |
12422 | if (stretch < 0) | |
12423 | stretch = - ((- stretch) | |
12424 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
12425 | else | |
12426 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
12427 | if (stretch == 0) | |
12428 | break; | |
12429 | } | |
12430 | } | |
12431 | if (f != NULL) | |
12432 | val += stretch; | |
12433 | } | |
12434 | ||
12435 | addr = fragp->fr_address + fragp->fr_fix; | |
12436 | ||
12437 | /* The base address rules are complicated. The base address of | |
12438 | a branch is the following instruction. The base address of a | |
12439 | PC relative load or add is the instruction itself, but if it | |
12440 | is in a delay slot (in which case it can not be extended) use | |
12441 | the address of the instruction whose delay slot it is in. */ | |
12442 | if (type == 'p' || type == 'q') | |
12443 | { | |
12444 | addr += 2; | |
12445 | ||
12446 | /* If we are currently assuming that this frag should be | |
12447 | extended, then, the current address is two bytes | |
bdaaa2e1 | 12448 | higher. */ |
252b5132 RH |
12449 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
12450 | addr += 2; | |
12451 | ||
12452 | /* Ignore the low bit in the target, since it will be set | |
12453 | for a text label. */ | |
12454 | if ((val & 1) != 0) | |
12455 | --val; | |
12456 | } | |
12457 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
12458 | addr -= 4; | |
12459 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
12460 | addr -= 2; | |
12461 | ||
12462 | val -= addr & ~ ((1 << op->shift) - 1); | |
12463 | ||
12464 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
12465 | if (type == 'p' || type == 'q') | |
12466 | val /= 2; | |
12467 | ||
12468 | /* If any of the shifted bits are set, we must use an extended | |
12469 | opcode. If the address depends on the size of this | |
12470 | instruction, this can lead to a loop, so we arrange to always | |
12471 | use an extended opcode. We only check this when we are in | |
12472 | the main relaxation loop, when SEC is NULL. */ | |
12473 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
12474 | { | |
12475 | fragp->fr_subtype = | |
12476 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12477 | return 1; | |
12478 | } | |
12479 | ||
12480 | /* If we are about to mark a frag as extended because the value | |
12481 | is precisely maxtiny + 1, then there is a chance of an | |
12482 | infinite loop as in the following code: | |
12483 | la $4,foo | |
12484 | .skip 1020 | |
12485 | .align 2 | |
12486 | foo: | |
12487 | In this case when the la is extended, foo is 0x3fc bytes | |
12488 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
12489 | the la must be extended. To avoid this loop, we mark the | |
12490 | frag as extended if it was small, and is about to become | |
12491 | extended with a value of maxtiny + 1. */ | |
12492 | if (val == ((maxtiny + 1) << op->shift) | |
12493 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
12494 | && sec == NULL) | |
12495 | { | |
12496 | fragp->fr_subtype = | |
12497 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12498 | return 1; | |
12499 | } | |
12500 | } | |
12501 | else if (symsec != absolute_section && sec != NULL) | |
12502 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
12503 | ||
12504 | if ((val & ((1 << op->shift) - 1)) != 0 | |
12505 | || val < (mintiny << op->shift) | |
12506 | || val > (maxtiny << op->shift)) | |
12507 | return 1; | |
12508 | else | |
12509 | return 0; | |
12510 | } | |
12511 | ||
12512 | /* Estimate the size of a frag before relaxing. Unless this is the | |
12513 | mips16, we are not really relaxing here, and the final size is | |
12514 | encoded in the subtype information. For the mips16, we have to | |
12515 | decide whether we are using an extended opcode or not. */ | |
12516 | ||
252b5132 RH |
12517 | int |
12518 | md_estimate_size_before_relax (fragp, segtype) | |
12519 | fragS *fragp; | |
12520 | asection *segtype; | |
12521 | { | |
43841e91 | 12522 | int change = 0; |
8614eeee | 12523 | boolean linkonce = false; |
252b5132 RH |
12524 | |
12525 | if (RELAX_MIPS16_P (fragp->fr_subtype)) | |
177b4a6a AO |
12526 | /* We don't want to modify the EXTENDED bit here; it might get us |
12527 | into infinite loops. We change it only in mips_relax_frag(). */ | |
12528 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 RH |
12529 | |
12530 | if (mips_pic == NO_PIC) | |
12531 | { | |
12532 | change = nopic_need_relax (fragp->fr_symbol, 0); | |
12533 | } | |
12534 | else if (mips_pic == SVR4_PIC) | |
12535 | { | |
12536 | symbolS *sym; | |
12537 | asection *symsec; | |
12538 | ||
12539 | sym = fragp->fr_symbol; | |
12540 | ||
12541 | /* Handle the case of a symbol equated to another symbol. */ | |
e0890092 | 12542 | while (symbol_equated_reloc_p (sym)) |
252b5132 RH |
12543 | { |
12544 | symbolS *n; | |
12545 | ||
12546 | /* It's possible to get a loop here in a badly written | |
12547 | program. */ | |
49309057 | 12548 | n = symbol_get_value_expression (sym)->X_add_symbol; |
252b5132 RH |
12549 | if (n == sym) |
12550 | break; | |
12551 | sym = n; | |
12552 | } | |
12553 | ||
12554 | symsec = S_GET_SEGMENT (sym); | |
12555 | ||
8614eeee UC |
12556 | /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */ |
12557 | if (symsec != segtype && ! S_IS_LOCAL (sym)) | |
beae10d5 KH |
12558 | { |
12559 | if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE) | |
12560 | != 0) | |
12561 | linkonce = true; | |
12562 | ||
12563 | /* The GNU toolchain uses an extension for ELF: a section | |
12564 | beginning with the magic string .gnu.linkonce is a linkonce | |
12565 | section. */ | |
12566 | if (strncmp (segment_name (symsec), ".gnu.linkonce", | |
12567 | sizeof ".gnu.linkonce" - 1) == 0) | |
12568 | linkonce = true; | |
12569 | } | |
8614eeee | 12570 | |
252b5132 RH |
12571 | /* This must duplicate the test in adjust_reloc_syms. */ |
12572 | change = (symsec != &bfd_und_section | |
12573 | && symsec != &bfd_abs_section | |
426b0403 | 12574 | && ! bfd_is_com_section (symsec) |
8614eeee | 12575 | && !linkonce |
426b0403 | 12576 | #ifdef OBJ_ELF |
ea4ff978 | 12577 | /* A global or weak symbol is treated as external. */ |
9151e8bf | 12578 | && (OUTPUT_FLAVOR != bfd_target_elf_flavour |
b25a253c | 12579 | || (! S_IS_WEAK (sym) |
bad9ca53 TS |
12580 | && (! S_IS_EXTERNAL (sym) |
12581 | || mips_pic == EMBEDDED_PIC))) | |
426b0403 AM |
12582 | #endif |
12583 | ); | |
252b5132 RH |
12584 | } |
12585 | else | |
12586 | abort (); | |
12587 | ||
12588 | if (change) | |
12589 | { | |
12590 | /* Record the offset to the first reloc in the fr_opcode field. | |
12591 | This lets md_convert_frag and tc_gen_reloc know that the code | |
12592 | must be expanded. */ | |
12593 | fragp->fr_opcode = (fragp->fr_literal | |
12594 | + fragp->fr_fix | |
12595 | - RELAX_OLD (fragp->fr_subtype) | |
12596 | + RELAX_RELOC1 (fragp->fr_subtype)); | |
12597 | /* FIXME: This really needs as_warn_where. */ | |
12598 | if (RELAX_WARN (fragp->fr_subtype)) | |
9a41af64 TS |
12599 | as_warn (_("AT used after \".set noat\" or macro used after " |
12600 | "\".set nomacro\"")); | |
12601 | ||
12602 | return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype); | |
252b5132 RH |
12603 | } |
12604 | ||
9a41af64 | 12605 | return 0; |
252b5132 RH |
12606 | } |
12607 | ||
12608 | /* This is called to see whether a reloc against a defined symbol | |
12609 | should be converted into a reloc against a section. Don't adjust | |
12610 | MIPS16 jump relocations, so we don't have to worry about the format | |
12611 | of the offset in the .o file. Don't adjust relocations against | |
12612 | mips16 symbols, so that the linker can find them if it needs to set | |
12613 | up a stub. */ | |
12614 | ||
12615 | int | |
12616 | mips_fix_adjustable (fixp) | |
12617 | fixS *fixp; | |
12618 | { | |
12619 | if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) | |
12620 | return 0; | |
a161fe53 | 12621 | |
252b5132 RH |
12622 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
12623 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
12624 | return 0; | |
a161fe53 | 12625 | |
252b5132 RH |
12626 | if (fixp->fx_addsy == NULL) |
12627 | return 1; | |
a161fe53 | 12628 | |
252b5132 RH |
12629 | #ifdef OBJ_ELF |
12630 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
12631 | && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 | |
12632 | && fixp->fx_subsy == NULL) | |
12633 | return 0; | |
12634 | #endif | |
a161fe53 | 12635 | |
252b5132 RH |
12636 | return 1; |
12637 | } | |
12638 | ||
12639 | /* Translate internal representation of relocation info to BFD target | |
12640 | format. */ | |
12641 | ||
12642 | arelent ** | |
12643 | tc_gen_reloc (section, fixp) | |
43841e91 | 12644 | asection *section ATTRIBUTE_UNUSED; |
252b5132 RH |
12645 | fixS *fixp; |
12646 | { | |
12647 | static arelent *retval[4]; | |
12648 | arelent *reloc; | |
12649 | bfd_reloc_code_real_type code; | |
12650 | ||
12651 | reloc = retval[0] = (arelent *) xmalloc (sizeof (arelent)); | |
12652 | retval[1] = NULL; | |
12653 | ||
49309057 ILT |
12654 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
12655 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
12656 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
12657 | ||
12658 | if (mips_pic == EMBEDDED_PIC | |
12659 | && SWITCH_TABLE (fixp)) | |
12660 | { | |
12661 | /* For a switch table entry we use a special reloc. The addend | |
12662 | is actually the difference between the reloc address and the | |
12663 | subtrahend. */ | |
12664 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
12665 | if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour) | |
12666 | as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc")); | |
12667 | fixp->fx_r_type = BFD_RELOC_GPREL32; | |
12668 | } | |
12669 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16) | |
12670 | { | |
4514d474 CD |
12671 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
12672 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 12673 | else |
4514d474 CD |
12674 | { |
12675 | /* We use a special addend for an internal RELLO reloc. */ | |
12676 | if (symbol_section_p (fixp->fx_addsy)) | |
12677 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
12678 | else | |
12679 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
12680 | } | |
252b5132 RH |
12681 | } |
12682 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S) | |
12683 | { | |
12684 | assert (fixp->fx_next != NULL | |
12685 | && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16); | |
4514d474 CD |
12686 | |
12687 | /* The reloc is relative to the RELLO; adjust the addend | |
252b5132 | 12688 | accordingly. */ |
4514d474 CD |
12689 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
12690 | reloc->addend = fixp->fx_next->fx_addnumber; | |
252b5132 | 12691 | else |
4514d474 CD |
12692 | { |
12693 | /* We use a special addend for an internal RELHI reloc. */ | |
12694 | if (symbol_section_p (fixp->fx_addsy)) | |
12695 | reloc->addend = (fixp->fx_next->fx_frag->fr_address | |
12696 | + fixp->fx_next->fx_where | |
12697 | - S_GET_VALUE (fixp->fx_subsy)); | |
12698 | else | |
12699 | reloc->addend = (fixp->fx_addnumber | |
12700 | + fixp->fx_next->fx_frag->fr_address | |
12701 | + fixp->fx_next->fx_where); | |
12702 | } | |
252b5132 | 12703 | } |
4514d474 CD |
12704 | else if (fixp->fx_pcrel == 0 || OUTPUT_FLAVOR == bfd_target_elf_flavour) |
12705 | reloc->addend = fixp->fx_addnumber; | |
252b5132 RH |
12706 | else |
12707 | { | |
12708 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour) | |
12709 | /* A gruesome hack which is a result of the gruesome gas reloc | |
12710 | handling. */ | |
12711 | reloc->addend = reloc->address; | |
12712 | else | |
12713 | reloc->addend = -reloc->address; | |
12714 | } | |
12715 | ||
12716 | /* If this is a variant frag, we may need to adjust the existing | |
12717 | reloc and generate a new one. */ | |
12718 | if (fixp->fx_frag->fr_opcode != NULL | |
ed6fb7bd SC |
12719 | && ((fixp->fx_r_type == BFD_RELOC_GPREL16 |
12720 | && ! HAVE_NEWABI) | |
252b5132 RH |
12721 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 |
12722 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16 | |
12723 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
12724 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16 | |
12725 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
6478892d | 12726 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16) |
ed6fb7bd | 12727 | ) |
252b5132 RH |
12728 | { |
12729 | arelent *reloc2; | |
12730 | ||
12731 | assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype)); | |
12732 | ||
12733 | /* If this is not the last reloc in this frag, then we have two | |
12734 | GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a | |
12735 | CALL_HI16/CALL_LO16, both of which are being replaced. Let | |
12736 | the second one handle all of them. */ | |
12737 | if (fixp->fx_next != NULL | |
12738 | && fixp->fx_frag == fixp->fx_next->fx_frag) | |
12739 | { | |
cdf6fd85 TS |
12740 | assert ((fixp->fx_r_type == BFD_RELOC_GPREL16 |
12741 | && fixp->fx_next->fx_r_type == BFD_RELOC_GPREL16) | |
252b5132 RH |
12742 | || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 |
12743 | && (fixp->fx_next->fx_r_type | |
12744 | == BFD_RELOC_MIPS_GOT_LO16)) | |
12745 | || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
12746 | && (fixp->fx_next->fx_r_type | |
12747 | == BFD_RELOC_MIPS_CALL_LO16))); | |
12748 | retval[0] = NULL; | |
12749 | return retval; | |
12750 | } | |
12751 | ||
12752 | fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal; | |
12753 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
12754 | reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent)); | |
12755 | retval[2] = NULL; | |
49309057 ILT |
12756 | reloc2->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
12757 | *reloc2->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
12758 | reloc2->address = (reloc->address |
12759 | + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype) | |
12760 | - RELAX_RELOC1 (fixp->fx_frag->fr_subtype))); | |
12761 | reloc2->addend = fixp->fx_addnumber; | |
12762 | reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16); | |
12763 | assert (reloc2->howto != NULL); | |
12764 | ||
12765 | if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype)) | |
12766 | { | |
12767 | arelent *reloc3; | |
12768 | ||
12769 | reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent)); | |
12770 | retval[3] = NULL; | |
12771 | *reloc3 = *reloc2; | |
12772 | reloc3->address += 4; | |
12773 | } | |
12774 | ||
12775 | if (mips_pic == NO_PIC) | |
12776 | { | |
cdf6fd85 | 12777 | assert (fixp->fx_r_type == BFD_RELOC_GPREL16); |
252b5132 RH |
12778 | fixp->fx_r_type = BFD_RELOC_HI16_S; |
12779 | } | |
12780 | else if (mips_pic == SVR4_PIC) | |
12781 | { | |
12782 | switch (fixp->fx_r_type) | |
12783 | { | |
12784 | default: | |
12785 | abort (); | |
12786 | case BFD_RELOC_MIPS_GOT16: | |
12787 | break; | |
252b5132 RH |
12788 | case BFD_RELOC_MIPS_GOT_LO16: |
12789 | case BFD_RELOC_MIPS_CALL_LO16: | |
12790 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT16; | |
12791 | break; | |
ed6fb7bd SC |
12792 | case BFD_RELOC_MIPS_CALL16: |
12793 | if (HAVE_NEWABI) | |
12794 | { | |
12795 | /* BFD_RELOC_MIPS_GOT16;*/ | |
12796 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT_PAGE; | |
12797 | reloc2->howto = bfd_reloc_type_lookup | |
12798 | (stdoutput, BFD_RELOC_MIPS_GOT_OFST); | |
12799 | } | |
12800 | else | |
12801 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT16; | |
12802 | break; | |
252b5132 RH |
12803 | } |
12804 | } | |
12805 | else | |
12806 | abort (); | |
ed6fb7bd SC |
12807 | |
12808 | /* newabi uses R_MIPS_GOT_DISP for local symbols */ | |
12809 | if (HAVE_NEWABI && BFD_RELOC_MIPS_GOT_LO16) | |
12810 | { | |
12811 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT_DISP; | |
12812 | retval[1] = NULL; | |
12813 | } | |
252b5132 RH |
12814 | } |
12815 | ||
438c16b8 TS |
12816 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
12817 | entry to be used in the relocation's section offset. */ | |
12818 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
12819 | { |
12820 | reloc->address = reloc->addend; | |
12821 | reloc->addend = 0; | |
12822 | } | |
12823 | ||
12824 | /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that | |
12825 | fixup_segment converted a non-PC relative reloc into a PC | |
12826 | relative reloc. In such a case, we need to convert the reloc | |
12827 | code. */ | |
12828 | code = fixp->fx_r_type; | |
12829 | if (fixp->fx_pcrel) | |
12830 | { | |
12831 | switch (code) | |
12832 | { | |
12833 | case BFD_RELOC_8: | |
12834 | code = BFD_RELOC_8_PCREL; | |
12835 | break; | |
12836 | case BFD_RELOC_16: | |
12837 | code = BFD_RELOC_16_PCREL; | |
12838 | break; | |
12839 | case BFD_RELOC_32: | |
12840 | code = BFD_RELOC_32_PCREL; | |
12841 | break; | |
12842 | case BFD_RELOC_64: | |
12843 | code = BFD_RELOC_64_PCREL; | |
12844 | break; | |
12845 | case BFD_RELOC_8_PCREL: | |
12846 | case BFD_RELOC_16_PCREL: | |
12847 | case BFD_RELOC_32_PCREL: | |
12848 | case BFD_RELOC_64_PCREL: | |
12849 | case BFD_RELOC_16_PCREL_S2: | |
12850 | case BFD_RELOC_PCREL_HI16_S: | |
12851 | case BFD_RELOC_PCREL_LO16: | |
12852 | break; | |
12853 | default: | |
12854 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
12855 | _("Cannot make %s relocation PC relative"), | |
12856 | bfd_get_reloc_code_name (code)); | |
12857 | } | |
12858 | } | |
12859 | ||
add55e1f RS |
12860 | #ifdef OBJ_ELF |
12861 | /* md_apply_fix3 has a double-subtraction hack to get | |
12862 | bfd_install_relocation to behave nicely. GPREL relocations are | |
12863 | handled correctly without this hack, so undo it here. We can't | |
12864 | stop md_apply_fix3 from subtracting twice in the first place since | |
12865 | the fake addend is required for variant frags above. */ | |
12866 | if (fixp->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour | |
98605598 | 12867 | && (code == BFD_RELOC_GPREL16 || code == BFD_RELOC_MIPS16_GPREL) |
add55e1f RS |
12868 | && reloc->addend != 0 |
12869 | && mips_need_elf_addend_fixup (fixp)) | |
12870 | reloc->addend += S_GET_VALUE (fixp->fx_addsy); | |
12871 | #endif | |
12872 | ||
252b5132 RH |
12873 | /* To support a PC relative reloc when generating embedded PIC code |
12874 | for ECOFF, we use a Cygnus extension. We check for that here to | |
12875 | make sure that we don't let such a reloc escape normally. */ | |
bb2d6cd7 GK |
12876 | if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
12877 | || OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
252b5132 RH |
12878 | && code == BFD_RELOC_16_PCREL_S2 |
12879 | && mips_pic != EMBEDDED_PIC) | |
12880 | reloc->howto = NULL; | |
12881 | else | |
12882 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
12883 | ||
12884 | if (reloc->howto == NULL) | |
12885 | { | |
12886 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
12887 | _("Can not represent %s relocation in this object file format"), | |
12888 | bfd_get_reloc_code_name (code)); | |
12889 | retval[0] = NULL; | |
12890 | } | |
12891 | ||
12892 | return retval; | |
12893 | } | |
12894 | ||
12895 | /* Relax a machine dependent frag. This returns the amount by which | |
12896 | the current size of the frag should change. */ | |
12897 | ||
12898 | int | |
12899 | mips_relax_frag (fragp, stretch) | |
12900 | fragS *fragp; | |
12901 | long stretch; | |
12902 | { | |
12903 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) | |
12904 | return 0; | |
12905 | ||
c4e7957c | 12906 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
12907 | { |
12908 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
12909 | return 0; | |
12910 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
12911 | return 2; | |
12912 | } | |
12913 | else | |
12914 | { | |
12915 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
12916 | return 0; | |
12917 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
12918 | return -2; | |
12919 | } | |
12920 | ||
12921 | return 0; | |
12922 | } | |
12923 | ||
12924 | /* Convert a machine dependent frag. */ | |
12925 | ||
12926 | void | |
12927 | md_convert_frag (abfd, asec, fragp) | |
43841e91 | 12928 | bfd *abfd ATTRIBUTE_UNUSED; |
252b5132 RH |
12929 | segT asec; |
12930 | fragS *fragp; | |
12931 | { | |
12932 | int old, new; | |
12933 | char *fixptr; | |
12934 | ||
12935 | if (RELAX_MIPS16_P (fragp->fr_subtype)) | |
12936 | { | |
12937 | int type; | |
12938 | register const struct mips16_immed_operand *op; | |
12939 | boolean small, ext; | |
12940 | offsetT val; | |
12941 | bfd_byte *buf; | |
12942 | unsigned long insn; | |
12943 | boolean use_extend; | |
12944 | unsigned short extend; | |
12945 | ||
12946 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
12947 | op = mips16_immed_operands; | |
12948 | while (op->type != type) | |
12949 | ++op; | |
12950 | ||
12951 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
12952 | { | |
12953 | small = false; | |
12954 | ext = true; | |
12955 | } | |
12956 | else | |
12957 | { | |
12958 | small = true; | |
12959 | ext = false; | |
12960 | } | |
12961 | ||
6386f3a7 | 12962 | resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
12963 | val = S_GET_VALUE (fragp->fr_symbol); |
12964 | if (op->pcrel) | |
12965 | { | |
12966 | addressT addr; | |
12967 | ||
12968 | addr = fragp->fr_address + fragp->fr_fix; | |
12969 | ||
12970 | /* The rules for the base address of a PC relative reloc are | |
12971 | complicated; see mips16_extended_frag. */ | |
12972 | if (type == 'p' || type == 'q') | |
12973 | { | |
12974 | addr += 2; | |
12975 | if (ext) | |
12976 | addr += 2; | |
12977 | /* Ignore the low bit in the target, since it will be | |
12978 | set for a text label. */ | |
12979 | if ((val & 1) != 0) | |
12980 | --val; | |
12981 | } | |
12982 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
12983 | addr -= 4; | |
12984 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
12985 | addr -= 2; | |
12986 | ||
12987 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
12988 | val -= addr; | |
12989 | ||
12990 | /* Make sure the section winds up with the alignment we have | |
12991 | assumed. */ | |
12992 | if (op->shift > 0) | |
12993 | record_alignment (asec, op->shift); | |
12994 | } | |
12995 | ||
12996 | if (ext | |
12997 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
12998 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
12999 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
13000 | _("extended instruction in delay slot")); | |
13001 | ||
13002 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
13003 | ||
13004 | if (target_big_endian) | |
13005 | insn = bfd_getb16 (buf); | |
13006 | else | |
13007 | insn = bfd_getl16 (buf); | |
13008 | ||
13009 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
13010 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
13011 | small, ext, &insn, &use_extend, &extend); | |
13012 | ||
13013 | if (use_extend) | |
13014 | { | |
874e8986 | 13015 | md_number_to_chars ((char *) buf, 0xf000 | extend, 2); |
252b5132 RH |
13016 | fragp->fr_fix += 2; |
13017 | buf += 2; | |
13018 | } | |
13019 | ||
874e8986 | 13020 | md_number_to_chars ((char *) buf, insn, 2); |
252b5132 RH |
13021 | fragp->fr_fix += 2; |
13022 | buf += 2; | |
13023 | } | |
13024 | else | |
13025 | { | |
13026 | if (fragp->fr_opcode == NULL) | |
13027 | return; | |
13028 | ||
13029 | old = RELAX_OLD (fragp->fr_subtype); | |
13030 | new = RELAX_NEW (fragp->fr_subtype); | |
13031 | fixptr = fragp->fr_literal + fragp->fr_fix; | |
13032 | ||
13033 | if (new > 0) | |
13034 | memcpy (fixptr - old, fixptr, new); | |
13035 | ||
13036 | fragp->fr_fix += new - old; | |
13037 | } | |
13038 | } | |
13039 | ||
13040 | #ifdef OBJ_ELF | |
13041 | ||
13042 | /* This function is called after the relocs have been generated. | |
13043 | We've been storing mips16 text labels as odd. Here we convert them | |
13044 | back to even for the convenience of the debugger. */ | |
13045 | ||
13046 | void | |
13047 | mips_frob_file_after_relocs () | |
13048 | { | |
13049 | asymbol **syms; | |
13050 | unsigned int count, i; | |
13051 | ||
13052 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
13053 | return; | |
13054 | ||
13055 | syms = bfd_get_outsymbols (stdoutput); | |
13056 | count = bfd_get_symcount (stdoutput); | |
13057 | for (i = 0; i < count; i++, syms++) | |
13058 | { | |
13059 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
13060 | && ((*syms)->value & 1) != 0) | |
13061 | { | |
13062 | (*syms)->value &= ~1; | |
13063 | /* If the symbol has an odd size, it was probably computed | |
13064 | incorrectly, so adjust that as well. */ | |
13065 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
13066 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
13067 | } | |
13068 | } | |
13069 | } | |
13070 | ||
13071 | #endif | |
13072 | ||
13073 | /* This function is called whenever a label is defined. It is used | |
13074 | when handling branch delays; if a branch has a label, we assume we | |
13075 | can not move it. */ | |
13076 | ||
13077 | void | |
13078 | mips_define_label (sym) | |
13079 | symbolS *sym; | |
13080 | { | |
13081 | struct insn_label_list *l; | |
13082 | ||
13083 | if (free_insn_labels == NULL) | |
13084 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
13085 | else | |
13086 | { | |
13087 | l = free_insn_labels; | |
13088 | free_insn_labels = l->next; | |
13089 | } | |
13090 | ||
13091 | l->label = sym; | |
13092 | l->next = insn_labels; | |
13093 | insn_labels = l; | |
13094 | } | |
13095 | \f | |
13096 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
13097 | ||
13098 | /* Some special processing for a MIPS ELF file. */ | |
13099 | ||
13100 | void | |
13101 | mips_elf_final_processing () | |
13102 | { | |
13103 | /* Write out the register information. */ | |
316f5878 | 13104 | if (mips_abi != N64_ABI) |
252b5132 RH |
13105 | { |
13106 | Elf32_RegInfo s; | |
13107 | ||
13108 | s.ri_gprmask = mips_gprmask; | |
13109 | s.ri_cprmask[0] = mips_cprmask[0]; | |
13110 | s.ri_cprmask[1] = mips_cprmask[1]; | |
13111 | s.ri_cprmask[2] = mips_cprmask[2]; | |
13112 | s.ri_cprmask[3] = mips_cprmask[3]; | |
13113 | /* The gp_value field is set by the MIPS ELF backend. */ | |
13114 | ||
13115 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
13116 | ((Elf32_External_RegInfo *) | |
13117 | mips_regmask_frag)); | |
13118 | } | |
13119 | else | |
13120 | { | |
13121 | Elf64_Internal_RegInfo s; | |
13122 | ||
13123 | s.ri_gprmask = mips_gprmask; | |
13124 | s.ri_pad = 0; | |
13125 | s.ri_cprmask[0] = mips_cprmask[0]; | |
13126 | s.ri_cprmask[1] = mips_cprmask[1]; | |
13127 | s.ri_cprmask[2] = mips_cprmask[2]; | |
13128 | s.ri_cprmask[3] = mips_cprmask[3]; | |
13129 | /* The gp_value field is set by the MIPS ELF backend. */ | |
13130 | ||
13131 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
13132 | ((Elf64_External_RegInfo *) | |
13133 | mips_regmask_frag)); | |
13134 | } | |
13135 | ||
13136 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
13137 | sort of BFD interface for this. */ | |
13138 | if (mips_any_noreorder) | |
13139 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
13140 | if (mips_pic != NO_PIC) | |
13141 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; | |
13142 | ||
98d3f06f | 13143 | /* Set MIPS ELF flags for ASEs. */ |
a4672219 TS |
13144 | if (file_ase_mips16) |
13145 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
1f25f5d3 CD |
13146 | #if 0 /* XXX FIXME */ |
13147 | if (file_ase_mips3d) | |
13148 | elf_elfheader (stdoutput)->e_flags |= ???; | |
13149 | #endif | |
deec1734 CD |
13150 | if (file_ase_mdmx) |
13151 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; | |
1f25f5d3 | 13152 | |
bdaaa2e1 | 13153 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 13154 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 13155 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 13156 | else if (mips_abi == O64_ABI) |
252b5132 | 13157 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 13158 | else if (mips_abi == EABI_ABI) |
252b5132 | 13159 | { |
316f5878 | 13160 | if (!file_mips_gp32) |
252b5132 RH |
13161 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
13162 | else | |
13163 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
13164 | } | |
316f5878 | 13165 | else if (mips_abi == N32_ABI) |
be00bddd TS |
13166 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
13167 | ||
c9914766 | 13168 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
13169 | |
13170 | if (mips_32bitmode) | |
13171 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
13172 | } | |
13173 | ||
13174 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
13175 | \f | |
beae10d5 KH |
13176 | typedef struct proc { |
13177 | symbolS *isym; | |
13178 | unsigned long reg_mask; | |
13179 | unsigned long reg_offset; | |
13180 | unsigned long fpreg_mask; | |
13181 | unsigned long fpreg_offset; | |
13182 | unsigned long frame_offset; | |
13183 | unsigned long frame_reg; | |
13184 | unsigned long pc_reg; | |
13185 | } procS; | |
252b5132 RH |
13186 | |
13187 | static procS cur_proc; | |
13188 | static procS *cur_proc_ptr; | |
13189 | static int numprocs; | |
13190 | ||
0a9ef439 | 13191 | /* Fill in an rs_align_code fragment. */ |
a19d8eb0 | 13192 | |
0a9ef439 RH |
13193 | void |
13194 | mips_handle_align (fragp) | |
13195 | fragS *fragp; | |
a19d8eb0 | 13196 | { |
0a9ef439 RH |
13197 | if (fragp->fr_type != rs_align_code) |
13198 | return; | |
13199 | ||
13200 | if (mips_opts.mips16) | |
a19d8eb0 CP |
13201 | { |
13202 | static const unsigned char be_nop[] = { 0x65, 0x00 }; | |
13203 | static const unsigned char le_nop[] = { 0x00, 0x65 }; | |
13204 | ||
0a9ef439 RH |
13205 | int bytes; |
13206 | char *p; | |
a19d8eb0 | 13207 | |
0a9ef439 RH |
13208 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
13209 | p = fragp->fr_literal + fragp->fr_fix; | |
13210 | ||
13211 | if (bytes & 1) | |
13212 | { | |
13213 | *p++ = 0; | |
f9419b05 | 13214 | fragp->fr_fix++; |
0a9ef439 RH |
13215 | } |
13216 | ||
13217 | memcpy (p, (target_big_endian ? be_nop : le_nop), 2); | |
13218 | fragp->fr_var = 2; | |
a19d8eb0 CP |
13219 | } |
13220 | ||
0a9ef439 | 13221 | /* For mips32, a nop is a zero, which we trivially get by doing nothing. */ |
a19d8eb0 CP |
13222 | } |
13223 | ||
252b5132 RH |
13224 | static void |
13225 | md_obj_begin () | |
13226 | { | |
13227 | } | |
13228 | ||
13229 | static void | |
13230 | md_obj_end () | |
13231 | { | |
13232 | /* check for premature end, nesting errors, etc */ | |
13233 | if (cur_proc_ptr) | |
9a41af64 | 13234 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
13235 | } |
13236 | ||
13237 | static long | |
13238 | get_number () | |
13239 | { | |
13240 | int negative = 0; | |
13241 | long val = 0; | |
13242 | ||
13243 | if (*input_line_pointer == '-') | |
13244 | { | |
13245 | ++input_line_pointer; | |
13246 | negative = 1; | |
13247 | } | |
3882b010 | 13248 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 13249 | as_bad (_("expected simple number")); |
252b5132 RH |
13250 | if (input_line_pointer[0] == '0') |
13251 | { | |
13252 | if (input_line_pointer[1] == 'x') | |
13253 | { | |
13254 | input_line_pointer += 2; | |
3882b010 | 13255 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
13256 | { |
13257 | val <<= 4; | |
13258 | val |= hex_value (*input_line_pointer++); | |
13259 | } | |
13260 | return negative ? -val : val; | |
13261 | } | |
13262 | else | |
13263 | { | |
13264 | ++input_line_pointer; | |
3882b010 | 13265 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13266 | { |
13267 | val <<= 3; | |
13268 | val |= *input_line_pointer++ - '0'; | |
13269 | } | |
13270 | return negative ? -val : val; | |
13271 | } | |
13272 | } | |
3882b010 | 13273 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13274 | { |
13275 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
13276 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 13277 | as_warn (_("invalid number")); |
252b5132 RH |
13278 | return -1; |
13279 | } | |
3882b010 | 13280 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13281 | { |
13282 | val *= 10; | |
13283 | val += *input_line_pointer++ - '0'; | |
13284 | } | |
13285 | return negative ? -val : val; | |
13286 | } | |
13287 | ||
13288 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
13289 | is an initial number which is the ECOFF file index. In the non-ECOFF |
13290 | case .file implies DWARF-2. */ | |
13291 | ||
13292 | static void | |
13293 | s_mips_file (x) | |
13294 | int x ATTRIBUTE_UNUSED; | |
13295 | { | |
ecb4347a DJ |
13296 | static int first_file_directive = 0; |
13297 | ||
c5dd6aab DJ |
13298 | if (ECOFF_DEBUGGING) |
13299 | { | |
13300 | get_number (); | |
13301 | s_app_file (0); | |
13302 | } | |
13303 | else | |
ecb4347a DJ |
13304 | { |
13305 | char *filename; | |
13306 | ||
13307 | filename = dwarf2_directive_file (0); | |
13308 | ||
13309 | /* Versions of GCC up to 3.1 start files with a ".file" | |
13310 | directive even for stabs output. Make sure that this | |
13311 | ".file" is handled. Note that you need a version of GCC | |
13312 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
13313 | if (filename != NULL && ! first_file_directive) | |
13314 | { | |
13315 | (void) new_logical_line (filename, -1); | |
13316 | s_app_file_string (filename); | |
13317 | } | |
13318 | first_file_directive = 1; | |
13319 | } | |
c5dd6aab DJ |
13320 | } |
13321 | ||
13322 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
13323 | |
13324 | static void | |
c5dd6aab | 13325 | s_mips_loc (x) |
43841e91 | 13326 | int x ATTRIBUTE_UNUSED; |
252b5132 | 13327 | { |
c5dd6aab DJ |
13328 | if (!ECOFF_DEBUGGING) |
13329 | dwarf2_directive_loc (0); | |
252b5132 RH |
13330 | } |
13331 | ||
252b5132 RH |
13332 | /* The .end directive. */ |
13333 | ||
13334 | static void | |
13335 | s_mips_end (x) | |
43841e91 | 13336 | int x ATTRIBUTE_UNUSED; |
252b5132 RH |
13337 | { |
13338 | symbolS *p; | |
13339 | int maybe_text; | |
13340 | ||
7a621144 DJ |
13341 | /* Following functions need their own .frame and .cprestore directives. */ |
13342 | mips_frame_reg_valid = 0; | |
13343 | mips_cprestore_valid = 0; | |
13344 | ||
252b5132 RH |
13345 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
13346 | { | |
13347 | p = get_symbol (); | |
13348 | demand_empty_rest_of_line (); | |
13349 | } | |
13350 | else | |
13351 | p = NULL; | |
13352 | ||
13353 | #ifdef BFD_ASSEMBLER | |
13354 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
13355 | maybe_text = 1; | |
13356 | else | |
13357 | maybe_text = 0; | |
13358 | #else | |
13359 | if (now_seg != data_section && now_seg != bss_section) | |
13360 | maybe_text = 1; | |
13361 | else | |
13362 | maybe_text = 0; | |
13363 | #endif | |
13364 | ||
13365 | if (!maybe_text) | |
13366 | as_warn (_(".end not in text section")); | |
13367 | ||
13368 | if (!cur_proc_ptr) | |
13369 | { | |
13370 | as_warn (_(".end directive without a preceding .ent directive.")); | |
13371 | demand_empty_rest_of_line (); | |
13372 | return; | |
13373 | } | |
13374 | ||
13375 | if (p != NULL) | |
13376 | { | |
13377 | assert (S_GET_NAME (p)); | |
13378 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym))) | |
13379 | as_warn (_(".end symbol does not match .ent symbol.")); | |
ecb4347a DJ |
13380 | |
13381 | if (debug_type == DEBUG_STABS) | |
13382 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
13383 | S_GET_NAME (p)); | |
252b5132 RH |
13384 | } |
13385 | else | |
13386 | as_warn (_(".end directive missing or unknown symbol")); | |
13387 | ||
ecb4347a DJ |
13388 | #ifdef OBJ_ELF |
13389 | /* Generate a .pdr section. */ | |
13390 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
13391 | { | |
13392 | segT saved_seg = now_seg; | |
13393 | subsegT saved_subseg = now_subseg; | |
13394 | valueT dot; | |
13395 | expressionS exp; | |
13396 | char *fragp; | |
252b5132 | 13397 | |
ecb4347a | 13398 | dot = frag_now_fix (); |
252b5132 RH |
13399 | |
13400 | #ifdef md_flush_pending_output | |
ecb4347a | 13401 | md_flush_pending_output (); |
252b5132 RH |
13402 | #endif |
13403 | ||
ecb4347a DJ |
13404 | assert (pdr_seg); |
13405 | subseg_set (pdr_seg, 0); | |
252b5132 | 13406 | |
ecb4347a DJ |
13407 | /* Write the symbol. */ |
13408 | exp.X_op = O_symbol; | |
13409 | exp.X_add_symbol = p; | |
13410 | exp.X_add_number = 0; | |
13411 | emit_expr (&exp, 4); | |
252b5132 | 13412 | |
ecb4347a | 13413 | fragp = frag_more (7 * 4); |
252b5132 | 13414 | |
ecb4347a DJ |
13415 | md_number_to_chars (fragp, (valueT) cur_proc_ptr->reg_mask, 4); |
13416 | md_number_to_chars (fragp + 4, (valueT) cur_proc_ptr->reg_offset, 4); | |
13417 | md_number_to_chars (fragp + 8, (valueT) cur_proc_ptr->fpreg_mask, 4); | |
13418 | md_number_to_chars (fragp + 12, (valueT) cur_proc_ptr->fpreg_offset, 4); | |
13419 | md_number_to_chars (fragp + 16, (valueT) cur_proc_ptr->frame_offset, 4); | |
13420 | md_number_to_chars (fragp + 20, (valueT) cur_proc_ptr->frame_reg, 4); | |
13421 | md_number_to_chars (fragp + 24, (valueT) cur_proc_ptr->pc_reg, 4); | |
252b5132 | 13422 | |
ecb4347a DJ |
13423 | subseg_set (saved_seg, saved_subseg); |
13424 | } | |
13425 | #endif /* OBJ_ELF */ | |
252b5132 RH |
13426 | |
13427 | cur_proc_ptr = NULL; | |
13428 | } | |
13429 | ||
13430 | /* The .aent and .ent directives. */ | |
13431 | ||
13432 | static void | |
13433 | s_mips_ent (aent) | |
13434 | int aent; | |
13435 | { | |
252b5132 RH |
13436 | symbolS *symbolP; |
13437 | int maybe_text; | |
13438 | ||
13439 | symbolP = get_symbol (); | |
13440 | if (*input_line_pointer == ',') | |
f9419b05 | 13441 | ++input_line_pointer; |
252b5132 | 13442 | SKIP_WHITESPACE (); |
3882b010 | 13443 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 13444 | || *input_line_pointer == '-') |
874e8986 | 13445 | get_number (); |
252b5132 RH |
13446 | |
13447 | #ifdef BFD_ASSEMBLER | |
13448 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
13449 | maybe_text = 1; | |
13450 | else | |
13451 | maybe_text = 0; | |
13452 | #else | |
13453 | if (now_seg != data_section && now_seg != bss_section) | |
13454 | maybe_text = 1; | |
13455 | else | |
13456 | maybe_text = 0; | |
13457 | #endif | |
13458 | ||
13459 | if (!maybe_text) | |
13460 | as_warn (_(".ent or .aent not in text section.")); | |
13461 | ||
13462 | if (!aent && cur_proc_ptr) | |
9a41af64 | 13463 | as_warn (_("missing .end")); |
252b5132 RH |
13464 | |
13465 | if (!aent) | |
13466 | { | |
7a621144 DJ |
13467 | /* This function needs its own .frame and .cprestore directives. */ |
13468 | mips_frame_reg_valid = 0; | |
13469 | mips_cprestore_valid = 0; | |
13470 | ||
252b5132 RH |
13471 | cur_proc_ptr = &cur_proc; |
13472 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
13473 | ||
13474 | cur_proc_ptr->isym = symbolP; | |
13475 | ||
49309057 | 13476 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
252b5132 | 13477 | |
f9419b05 | 13478 | ++numprocs; |
ecb4347a DJ |
13479 | |
13480 | if (debug_type == DEBUG_STABS) | |
13481 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
13482 | S_GET_NAME (symbolP)); | |
252b5132 RH |
13483 | } |
13484 | ||
13485 | demand_empty_rest_of_line (); | |
13486 | } | |
13487 | ||
13488 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 13489 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 13490 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 13491 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
13492 | symbol table (in the mdebug section). */ |
13493 | ||
13494 | static void | |
13495 | s_mips_frame (ignore) | |
2b3c5a5d | 13496 | int ignore ATTRIBUTE_UNUSED; |
252b5132 | 13497 | { |
ecb4347a DJ |
13498 | #ifdef OBJ_ELF |
13499 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
13500 | { | |
13501 | long val; | |
252b5132 | 13502 | |
ecb4347a DJ |
13503 | if (cur_proc_ptr == (procS *) NULL) |
13504 | { | |
13505 | as_warn (_(".frame outside of .ent")); | |
13506 | demand_empty_rest_of_line (); | |
13507 | return; | |
13508 | } | |
252b5132 | 13509 | |
ecb4347a DJ |
13510 | cur_proc_ptr->frame_reg = tc_get_register (1); |
13511 | ||
13512 | SKIP_WHITESPACE (); | |
13513 | if (*input_line_pointer++ != ',' | |
13514 | || get_absolute_expression_and_terminator (&val) != ',') | |
13515 | { | |
13516 | as_warn (_("Bad .frame directive")); | |
13517 | --input_line_pointer; | |
13518 | demand_empty_rest_of_line (); | |
13519 | return; | |
13520 | } | |
252b5132 | 13521 | |
ecb4347a DJ |
13522 | cur_proc_ptr->frame_offset = val; |
13523 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 13524 | |
252b5132 | 13525 | demand_empty_rest_of_line (); |
252b5132 | 13526 | } |
ecb4347a DJ |
13527 | else |
13528 | #endif /* OBJ_ELF */ | |
13529 | s_ignore (ignore); | |
252b5132 RH |
13530 | } |
13531 | ||
bdaaa2e1 KH |
13532 | /* The .fmask and .mask directives. If the mdebug section is present |
13533 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 13534 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 13535 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
13536 | make reference to the ecoff symbol table (in the mdebug section). */ |
13537 | ||
13538 | static void | |
13539 | s_mips_mask (reg_type) | |
13540 | char reg_type; | |
13541 | { | |
ecb4347a DJ |
13542 | #ifdef OBJ_ELF |
13543 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
252b5132 | 13544 | { |
ecb4347a | 13545 | long mask, off; |
252b5132 | 13546 | |
ecb4347a DJ |
13547 | if (cur_proc_ptr == (procS *) NULL) |
13548 | { | |
13549 | as_warn (_(".mask/.fmask outside of .ent")); | |
13550 | demand_empty_rest_of_line (); | |
13551 | return; | |
13552 | } | |
252b5132 | 13553 | |
ecb4347a DJ |
13554 | if (get_absolute_expression_and_terminator (&mask) != ',') |
13555 | { | |
13556 | as_warn (_("Bad .mask/.fmask directive")); | |
13557 | --input_line_pointer; | |
13558 | demand_empty_rest_of_line (); | |
13559 | return; | |
13560 | } | |
252b5132 | 13561 | |
ecb4347a DJ |
13562 | off = get_absolute_expression (); |
13563 | ||
13564 | if (reg_type == 'F') | |
13565 | { | |
13566 | cur_proc_ptr->fpreg_mask = mask; | |
13567 | cur_proc_ptr->fpreg_offset = off; | |
13568 | } | |
13569 | else | |
13570 | { | |
13571 | cur_proc_ptr->reg_mask = mask; | |
13572 | cur_proc_ptr->reg_offset = off; | |
13573 | } | |
13574 | ||
13575 | demand_empty_rest_of_line (); | |
252b5132 RH |
13576 | } |
13577 | else | |
ecb4347a DJ |
13578 | #endif /* OBJ_ELF */ |
13579 | s_ignore (reg_type); | |
252b5132 RH |
13580 | } |
13581 | ||
13582 | /* The .loc directive. */ | |
13583 | ||
13584 | #if 0 | |
13585 | static void | |
13586 | s_loc (x) | |
13587 | int x; | |
13588 | { | |
13589 | symbolS *symbolP; | |
13590 | int lineno; | |
13591 | int addroff; | |
13592 | ||
13593 | assert (now_seg == text_section); | |
13594 | ||
13595 | lineno = get_number (); | |
13596 | addroff = frag_now_fix (); | |
13597 | ||
13598 | symbolP = symbol_new ("", N_SLINE, addroff, frag_now); | |
13599 | S_SET_TYPE (symbolP, N_SLINE); | |
13600 | S_SET_OTHER (symbolP, 0); | |
13601 | S_SET_DESC (symbolP, lineno); | |
13602 | symbolP->sy_segment = now_seg; | |
13603 | } | |
13604 | #endif | |
e7af610e | 13605 | |
316f5878 RS |
13606 | /* A table describing all the processors gas knows about. Names are |
13607 | matched in the order listed. | |
e7af610e | 13608 | |
316f5878 RS |
13609 | To ease comparison, please keep this table in the same order as |
13610 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
13611 | static const struct mips_cpu_info mips_cpu_info_table[] = |
13612 | { | |
316f5878 RS |
13613 | /* Entries for generic ISAs */ |
13614 | { "mips1", 1, ISA_MIPS1, CPU_R3000 }, | |
13615 | { "mips2", 1, ISA_MIPS2, CPU_R6000 }, | |
13616 | { "mips3", 1, ISA_MIPS3, CPU_R4000 }, | |
13617 | { "mips4", 1, ISA_MIPS4, CPU_R8000 }, | |
13618 | { "mips5", 1, ISA_MIPS5, CPU_MIPS5 }, | |
13619 | { "mips32", 1, ISA_MIPS32, CPU_MIPS32 }, | |
13620 | { "mips64", 1, ISA_MIPS64, CPU_MIPS64 }, | |
13621 | ||
13622 | /* MIPS I */ | |
13623 | { "r3000", 0, ISA_MIPS1, CPU_R3000 }, | |
13624 | { "r2000", 0, ISA_MIPS1, CPU_R3000 }, | |
13625 | { "r3900", 0, ISA_MIPS1, CPU_R3900 }, | |
13626 | ||
13627 | /* MIPS II */ | |
13628 | { "r6000", 0, ISA_MIPS2, CPU_R6000 }, | |
13629 | ||
13630 | /* MIPS III */ | |
13631 | { "r4000", 0, ISA_MIPS3, CPU_R4000 }, | |
13632 | { "r4010", 0, ISA_MIPS2, CPU_R4010 }, | |
13633 | { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, | |
13634 | { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, | |
13635 | { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, | |
13636 | { "r4400", 0, ISA_MIPS3, CPU_R4400 }, | |
13637 | { "r4600", 0, ISA_MIPS3, CPU_R4600 }, | |
13638 | { "orion", 0, ISA_MIPS3, CPU_R4600 }, | |
13639 | { "r4650", 0, ISA_MIPS3, CPU_R4650 }, | |
13640 | ||
13641 | /* MIPS IV */ | |
13642 | { "r8000", 0, ISA_MIPS4, CPU_R8000 }, | |
13643 | { "r10000", 0, ISA_MIPS4, CPU_R10000 }, | |
13644 | { "r12000", 0, ISA_MIPS4, CPU_R12000 }, | |
13645 | { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, | |
13646 | { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, | |
13647 | { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, | |
13648 | { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, | |
13649 | { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, | |
13650 | { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, | |
13651 | { "r7000", 0, ISA_MIPS4, CPU_R5000 }, | |
13652 | ||
13653 | /* MIPS 32 */ | |
13654 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32, }, | |
13655 | { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, | |
13656 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, | |
e7af610e | 13657 | |
316f5878 RS |
13658 | /* MIPS 64 */ |
13659 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, | |
13660 | { "20kc", 0, ISA_MIPS64, CPU_MIPS64 }, | |
e7af610e | 13661 | |
c7a23324 | 13662 | /* Broadcom SB-1 CPU core */ |
316f5878 | 13663 | { "sb1", 0, ISA_MIPS64, CPU_SB1 }, |
e7af610e | 13664 | |
316f5878 RS |
13665 | /* End marker */ |
13666 | { NULL, 0, 0, 0 } | |
13667 | }; | |
e7af610e | 13668 | |
84ea6cf2 | 13669 | |
316f5878 RS |
13670 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
13671 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 13672 | |
316f5878 | 13673 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 13674 | |
316f5878 RS |
13675 | static boolean |
13676 | mips_strict_matching_cpu_name_p (canonical, given) | |
13677 | const char *canonical, *given; | |
13678 | { | |
13679 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
13680 | given++, canonical++; | |
13681 | ||
13682 | return ((*given == 0 && *canonical == 0) | |
13683 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
13684 | } | |
13685 | ||
13686 | ||
13687 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
13688 | CPU name. We've traditionally allowed a lot of variation here. | |
13689 | ||
13690 | Note: this function is shared between GCC and GAS. */ | |
13691 | ||
13692 | static boolean | |
13693 | mips_matching_cpu_name_p (canonical, given) | |
13694 | const char *canonical, *given; | |
13695 | { | |
13696 | /* First see if the name matches exactly, or with a final "000" | |
13697 | turned into "k". */ | |
13698 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
13699 | return true; | |
13700 | ||
13701 | /* If not, try comparing based on numerical designation alone. | |
13702 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
13703 | if (TOLOWER (*given) == 'r') | |
13704 | given++; | |
13705 | if (!ISDIGIT (*given)) | |
13706 | return false; | |
13707 | ||
13708 | /* Skip over some well-known prefixes in the canonical name, | |
13709 | hoping to find a number there too. */ | |
13710 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
13711 | canonical += 2; | |
13712 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
13713 | canonical += 2; | |
13714 | else if (TOLOWER (canonical[0]) == 'r') | |
13715 | canonical += 1; | |
13716 | ||
13717 | return mips_strict_matching_cpu_name_p (canonical, given); | |
13718 | } | |
13719 | ||
13720 | ||
13721 | /* Parse an option that takes the name of a processor as its argument. | |
13722 | OPTION is the name of the option and CPU_STRING is the argument. | |
13723 | Return the corresponding processor enumeration if the CPU_STRING is | |
13724 | recognized, otherwise report an error and return null. | |
13725 | ||
13726 | A similar function exists in GCC. */ | |
e7af610e NC |
13727 | |
13728 | static const struct mips_cpu_info * | |
316f5878 RS |
13729 | mips_parse_cpu (option, cpu_string) |
13730 | const char *option, *cpu_string; | |
e7af610e | 13731 | { |
316f5878 | 13732 | const struct mips_cpu_info *p; |
e7af610e | 13733 | |
316f5878 RS |
13734 | /* 'from-abi' selects the most compatible architecture for the given |
13735 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
13736 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
13737 | version. Look first at the -mgp options, if given, otherwise base | |
13738 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 13739 | |
316f5878 RS |
13740 | Treat NO_ABI like the EABIs. One reason to do this is that the |
13741 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
13742 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
13743 | 'mips64', just as we did in the days before 'from-abi'. */ | |
13744 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
13745 | { | |
13746 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
13747 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
13748 | ||
13749 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
13750 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
13751 | ||
13752 | if (file_mips_gp32 >= 0) | |
13753 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
13754 | ||
13755 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
13756 | ? ISA_MIPS3 | |
13757 | : ISA_MIPS1); | |
13758 | } | |
13759 | ||
13760 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
13761 | if (strcasecmp (cpu_string, "default") == 0) | |
13762 | return 0; | |
13763 | ||
13764 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
13765 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
13766 | return p; | |
13767 | ||
13768 | as_bad ("Bad value (%s) for %s", cpu_string, option); | |
13769 | return 0; | |
e7af610e NC |
13770 | } |
13771 | ||
316f5878 RS |
13772 | /* Return the canonical processor information for ISA (a member of the |
13773 | ISA_MIPS* enumeration). */ | |
13774 | ||
e7af610e NC |
13775 | static const struct mips_cpu_info * |
13776 | mips_cpu_info_from_isa (isa) | |
13777 | int isa; | |
13778 | { | |
13779 | int i; | |
13780 | ||
13781 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
13782 | if (mips_cpu_info_table[i].is_isa | |
316f5878 | 13783 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
13784 | return (&mips_cpu_info_table[i]); |
13785 | ||
e972090a | 13786 | return NULL; |
e7af610e | 13787 | } |
316f5878 RS |
13788 | \f |
13789 | static void | |
13790 | show (stream, string, col_p, first_p) | |
13791 | FILE *stream; | |
13792 | const char *string; | |
13793 | int *col_p; | |
13794 | int *first_p; | |
13795 | { | |
13796 | if (*first_p) | |
13797 | { | |
13798 | fprintf (stream, "%24s", ""); | |
13799 | *col_p = 24; | |
13800 | } | |
13801 | else | |
13802 | { | |
13803 | fprintf (stream, ", "); | |
13804 | *col_p += 2; | |
13805 | } | |
e7af610e | 13806 | |
316f5878 RS |
13807 | if (*col_p + strlen (string) > 72) |
13808 | { | |
13809 | fprintf (stream, "\n%24s", ""); | |
13810 | *col_p = 24; | |
13811 | } | |
13812 | ||
13813 | fprintf (stream, "%s", string); | |
13814 | *col_p += strlen (string); | |
13815 | ||
13816 | *first_p = 0; | |
13817 | } | |
13818 | ||
13819 | void | |
13820 | md_show_usage (stream) | |
13821 | FILE *stream; | |
e7af610e | 13822 | { |
316f5878 RS |
13823 | int column, first; |
13824 | size_t i; | |
13825 | ||
13826 | fprintf (stream, _("\ | |
13827 | MIPS options:\n\ | |
13828 | -membedded-pic generate embedded position independent code\n\ | |
13829 | -EB generate big endian output\n\ | |
13830 | -EL generate little endian output\n\ | |
13831 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
13832 | -G NUM allow referencing objects up to NUM bytes\n\ | |
13833 | implicitly with the gp register [default 8]\n")); | |
13834 | fprintf (stream, _("\ | |
13835 | -mips1 generate MIPS ISA I instructions\n\ | |
13836 | -mips2 generate MIPS ISA II instructions\n\ | |
13837 | -mips3 generate MIPS ISA III instructions\n\ | |
13838 | -mips4 generate MIPS ISA IV instructions\n\ | |
13839 | -mips5 generate MIPS ISA V instructions\n\ | |
13840 | -mips32 generate MIPS32 ISA instructions\n\ | |
13841 | -mips64 generate MIPS64 ISA instructions\n\ | |
13842 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); | |
13843 | ||
13844 | first = 1; | |
e7af610e NC |
13845 | |
13846 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
13847 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
13848 | show (stream, "from-abi", &column, &first); | |
13849 | fputc ('\n', stream); | |
e7af610e | 13850 | |
316f5878 RS |
13851 | fprintf (stream, _("\ |
13852 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
13853 | -no-mCPU don't generate code specific to CPU.\n\ | |
13854 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
13855 | ||
13856 | first = 1; | |
13857 | ||
13858 | show (stream, "3900", &column, &first); | |
13859 | show (stream, "4010", &column, &first); | |
13860 | show (stream, "4100", &column, &first); | |
13861 | show (stream, "4650", &column, &first); | |
13862 | fputc ('\n', stream); | |
13863 | ||
13864 | fprintf (stream, _("\ | |
13865 | -mips16 generate mips16 instructions\n\ | |
13866 | -no-mips16 do not generate mips16 instructions\n")); | |
13867 | fprintf (stream, _("\ | |
13868 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ | |
13869 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
13870 | -O0 remove unneeded NOPs, do not swap branches\n\ | |
13871 | -O remove unneeded NOPs and swap branches\n\ | |
13872 | -n warn about NOPs generated from macros\n\ | |
13873 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ | |
13874 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ | |
13875 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
13876 | #ifdef OBJ_ELF | |
13877 | fprintf (stream, _("\ | |
13878 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
13879 | -non_shared do not generate position independent code\n\ | |
13880 | -xgot assume a 32 bit GOT\n\ | |
13881 | -mabi=ABI create ABI conformant object file for:\n")); | |
13882 | ||
13883 | first = 1; | |
13884 | ||
13885 | show (stream, "32", &column, &first); | |
13886 | show (stream, "o64", &column, &first); | |
13887 | show (stream, "n32", &column, &first); | |
13888 | show (stream, "64", &column, &first); | |
13889 | show (stream, "eabi", &column, &first); | |
13890 | ||
13891 | fputc ('\n', stream); | |
13892 | ||
13893 | fprintf (stream, _("\ | |
13894 | -32 create o32 ABI object file (default)\n\ | |
13895 | -n32 create n32 ABI object file\n\ | |
13896 | -64 create 64 ABI object file\n")); | |
13897 | #endif | |
e7af610e | 13898 | } |