Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
81912461 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
c67a084a NC |
3 | 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 |
4 | Free Software Foundation, Inc. | |
252b5132 RH |
5 | Contributed by the OSF and Ralph Campbell. |
6 | Written by Keith Knowles and Ralph Campbell, working independently. | |
7 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
8 | Support. | |
9 | ||
10 | This file is part of GAS. | |
11 | ||
12 | GAS is free software; you can redistribute it and/or modify | |
13 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 14 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
15 | any later version. |
16 | ||
17 | GAS is distributed in the hope that it will be useful, | |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
21 | ||
22 | You should have received a copy of the GNU General Public License | |
23 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
24 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
25 | 02110-1301, USA. */ | |
252b5132 RH |
26 | |
27 | #include "as.h" | |
28 | #include "config.h" | |
29 | #include "subsegs.h" | |
3882b010 | 30 | #include "safe-ctype.h" |
252b5132 | 31 | |
252b5132 RH |
32 | #include "opcode/mips.h" |
33 | #include "itbl-ops.h" | |
c5dd6aab | 34 | #include "dwarf2dbg.h" |
5862107c | 35 | #include "dw2gencfi.h" |
252b5132 RH |
36 | |
37 | #ifdef DEBUG | |
38 | #define DBG(x) printf x | |
39 | #else | |
40 | #define DBG(x) | |
41 | #endif | |
42 | ||
43 | #ifdef OBJ_MAYBE_ELF | |
44 | /* Clean up namespace so we can include obj-elf.h too. */ | |
17a2f251 TS |
45 | static int mips_output_flavor (void); |
46 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
47 | #undef OBJ_PROCESS_STAB |
48 | #undef OUTPUT_FLAVOR | |
49 | #undef S_GET_ALIGN | |
50 | #undef S_GET_SIZE | |
51 | #undef S_SET_ALIGN | |
52 | #undef S_SET_SIZE | |
252b5132 RH |
53 | #undef obj_frob_file |
54 | #undef obj_frob_file_after_relocs | |
55 | #undef obj_frob_symbol | |
56 | #undef obj_pop_insert | |
57 | #undef obj_sec_sym_ok_for_reloc | |
58 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
59 | ||
60 | #include "obj-elf.h" | |
61 | /* Fix any of them that we actually care about. */ | |
62 | #undef OUTPUT_FLAVOR | |
63 | #define OUTPUT_FLAVOR mips_output_flavor() | |
64 | #endif | |
65 | ||
66 | #if defined (OBJ_ELF) | |
67 | #include "elf/mips.h" | |
68 | #endif | |
69 | ||
70 | #ifndef ECOFF_DEBUGGING | |
71 | #define NO_ECOFF_DEBUGGING | |
72 | #define ECOFF_DEBUGGING 0 | |
73 | #endif | |
74 | ||
ecb4347a DJ |
75 | int mips_flag_mdebug = -1; |
76 | ||
dcd410fe RO |
77 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
78 | linker doesn't know about and discards them, but relocations against them | |
79 | remain, leading to rld crashes. */ | |
80 | #ifdef TE_IRIX | |
81 | int mips_flag_pdr = FALSE; | |
82 | #else | |
83 | int mips_flag_pdr = TRUE; | |
84 | #endif | |
85 | ||
252b5132 RH |
86 | #include "ecoff.h" |
87 | ||
88 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
89 | static char *mips_regmask_frag; | |
90 | #endif | |
91 | ||
85b51719 | 92 | #define ZERO 0 |
741fe287 | 93 | #define ATREG 1 |
df58fc94 RS |
94 | #define S0 16 |
95 | #define S7 23 | |
252b5132 RH |
96 | #define TREG 24 |
97 | #define PIC_CALL_REG 25 | |
98 | #define KT0 26 | |
99 | #define KT1 27 | |
100 | #define GP 28 | |
101 | #define SP 29 | |
102 | #define FP 30 | |
103 | #define RA 31 | |
104 | ||
105 | #define ILLEGAL_REG (32) | |
106 | ||
741fe287 MR |
107 | #define AT mips_opts.at |
108 | ||
252b5132 RH |
109 | /* Allow override of standard little-endian ECOFF format. */ |
110 | ||
111 | #ifndef ECOFF_LITTLE_FORMAT | |
112 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
113 | #endif | |
114 | ||
115 | extern int target_big_endian; | |
116 | ||
252b5132 | 117 | /* The name of the readonly data section. */ |
4d0d148d | 118 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ |
252b5132 | 119 | ? ".rdata" \ |
056350c6 NC |
120 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
121 | ? ".rdata" \ | |
252b5132 RH |
122 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
123 | ? ".rodata" \ | |
124 | : (abort (), "")) | |
125 | ||
a4e06468 RS |
126 | /* Ways in which an instruction can be "appended" to the output. */ |
127 | enum append_method { | |
128 | /* Just add it normally. */ | |
129 | APPEND_ADD, | |
130 | ||
131 | /* Add it normally and then add a nop. */ | |
132 | APPEND_ADD_WITH_NOP, | |
133 | ||
134 | /* Turn an instruction with a delay slot into a "compact" version. */ | |
135 | APPEND_ADD_COMPACT, | |
136 | ||
137 | /* Insert the instruction before the last one. */ | |
138 | APPEND_SWAP | |
139 | }; | |
140 | ||
47e39b9d RS |
141 | /* Information about an instruction, including its format, operands |
142 | and fixups. */ | |
143 | struct mips_cl_insn | |
144 | { | |
145 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ | |
146 | const struct mips_opcode *insn_mo; | |
147 | ||
148 | /* True if this is a mips16 instruction and if we want the extended | |
149 | form of INSN_MO. */ | |
150 | bfd_boolean use_extend; | |
151 | ||
152 | /* The 16-bit extension instruction to use when USE_EXTEND is true. */ | |
153 | unsigned short extend; | |
154 | ||
155 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is | |
156 | a copy of INSN_MO->match with the operands filled in. */ | |
157 | unsigned long insn_opcode; | |
158 | ||
159 | /* The frag that contains the instruction. */ | |
160 | struct frag *frag; | |
161 | ||
162 | /* The offset into FRAG of the first instruction byte. */ | |
163 | long where; | |
164 | ||
165 | /* The relocs associated with the instruction, if any. */ | |
166 | fixS *fixp[3]; | |
167 | ||
a38419a5 RS |
168 | /* True if this entry cannot be moved from its current position. */ |
169 | unsigned int fixed_p : 1; | |
47e39b9d | 170 | |
708587a4 | 171 | /* True if this instruction occurred in a .set noreorder block. */ |
47e39b9d RS |
172 | unsigned int noreorder_p : 1; |
173 | ||
2fa15973 RS |
174 | /* True for mips16 instructions that jump to an absolute address. */ |
175 | unsigned int mips16_absolute_jump_p : 1; | |
15be625d CM |
176 | |
177 | /* True if this instruction is complete. */ | |
178 | unsigned int complete_p : 1; | |
47e39b9d RS |
179 | }; |
180 | ||
a325df1d TS |
181 | /* The ABI to use. */ |
182 | enum mips_abi_level | |
183 | { | |
184 | NO_ABI = 0, | |
185 | O32_ABI, | |
186 | O64_ABI, | |
187 | N32_ABI, | |
188 | N64_ABI, | |
189 | EABI_ABI | |
190 | }; | |
191 | ||
192 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 193 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 194 | |
143d77c5 EC |
195 | /* Whether or not we have code that can call pic code. */ |
196 | int mips_abicalls = FALSE; | |
197 | ||
aa6975fb ILT |
198 | /* Whether or not we have code which can be put into a shared |
199 | library. */ | |
200 | static bfd_boolean mips_in_shared = TRUE; | |
201 | ||
252b5132 RH |
202 | /* This is the set of options which may be modified by the .set |
203 | pseudo-op. We use a struct so that .set push and .set pop are more | |
204 | reliable. */ | |
205 | ||
e972090a NC |
206 | struct mips_set_options |
207 | { | |
252b5132 RH |
208 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
209 | if it has not been initialized. Changed by `.set mipsN', and the | |
210 | -mipsN command line option, and the default CPU. */ | |
211 | int isa; | |
1f25f5d3 CD |
212 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
213 | if they have not been initialized. Changed by `.set <asename>', by | |
214 | command line options, and based on the default architecture. */ | |
215 | int ase_mips3d; | |
deec1734 | 216 | int ase_mdmx; |
e16bfa71 | 217 | int ase_smartmips; |
74cd071d | 218 | int ase_dsp; |
8b082fb1 | 219 | int ase_dspr2; |
ef2e4d86 | 220 | int ase_mt; |
252b5132 RH |
221 | /* Whether we are assembling for the mips16 processor. 0 if we are |
222 | not, 1 if we are, and -1 if the value has not been initialized. | |
223 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
224 | -nomips16 command line options, and the default CPU. */ | |
225 | int mips16; | |
df58fc94 RS |
226 | /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not, |
227 | 1 if we are, and -1 if the value has not been initialized. Changed | |
228 | by `.set micromips' and `.set nomicromips', and the -mmicromips | |
229 | and -mno-micromips command line options, and the default CPU. */ | |
230 | int micromips; | |
252b5132 RH |
231 | /* Non-zero if we should not reorder instructions. Changed by `.set |
232 | reorder' and `.set noreorder'. */ | |
233 | int noreorder; | |
741fe287 MR |
234 | /* Non-zero if we should not permit the register designated "assembler |
235 | temporary" to be used in instructions. The value is the register | |
236 | number, normally $at ($1). Changed by `.set at=REG', `.set noat' | |
237 | (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */ | |
238 | unsigned int at; | |
252b5132 RH |
239 | /* Non-zero if we should warn when a macro instruction expands into |
240 | more than one machine instruction. Changed by `.set nomacro' and | |
241 | `.set macro'. */ | |
242 | int warn_about_macros; | |
243 | /* Non-zero if we should not move instructions. Changed by `.set | |
244 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
245 | int nomove; | |
246 | /* Non-zero if we should not optimize branches by moving the target | |
247 | of the branch into the delay slot. Actually, we don't perform | |
248 | this optimization anyhow. Changed by `.set bopt' and `.set | |
249 | nobopt'. */ | |
250 | int nobopt; | |
251 | /* Non-zero if we should not autoextend mips16 instructions. | |
252 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
253 | int noautoextend; | |
a325df1d TS |
254 | /* Restrict general purpose registers and floating point registers |
255 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
256 | is passed but can changed if the assembler code uses .set mipsN. */ | |
257 | int gp32; | |
258 | int fp32; | |
fef14a42 TS |
259 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
260 | command line option, and the default CPU. */ | |
261 | int arch; | |
aed1a261 RS |
262 | /* True if ".set sym32" is in effect. */ |
263 | bfd_boolean sym32; | |
037b32b9 AN |
264 | /* True if floating-point operations are not allowed. Changed by .set |
265 | softfloat or .set hardfloat, by command line options -msoft-float or | |
266 | -mhard-float. The default is false. */ | |
267 | bfd_boolean soft_float; | |
268 | ||
269 | /* True if only single-precision floating-point operations are allowed. | |
270 | Changed by .set singlefloat or .set doublefloat, command-line options | |
271 | -msingle-float or -mdouble-float. The default is false. */ | |
272 | bfd_boolean single_float; | |
252b5132 RH |
273 | }; |
274 | ||
037b32b9 AN |
275 | /* This is the struct we use to hold the current set of options. Note |
276 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to | |
277 | -1 to indicate that they have not been initialized. */ | |
278 | ||
a325df1d | 279 | /* True if -mgp32 was passed. */ |
a8e8e863 | 280 | static int file_mips_gp32 = -1; |
a325df1d TS |
281 | |
282 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 283 | static int file_mips_fp32 = -1; |
a325df1d | 284 | |
037b32b9 AN |
285 | /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */ |
286 | static int file_mips_soft_float = 0; | |
287 | ||
288 | /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */ | |
289 | static int file_mips_single_float = 0; | |
252b5132 | 290 | |
e972090a NC |
291 | static struct mips_set_options mips_opts = |
292 | { | |
037b32b9 AN |
293 | /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1, |
294 | /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1, | |
df58fc94 | 295 | /* mips16 */ -1, /* micromips */ -1, /* noreorder */ 0, /* at */ ATREG, |
037b32b9 AN |
296 | /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0, |
297 | /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN, | |
298 | /* sym32 */ FALSE, /* soft_float */ FALSE, /* single_float */ FALSE | |
e7af610e | 299 | }; |
252b5132 RH |
300 | |
301 | /* These variables are filled in with the masks of registers used. | |
302 | The object format code reads them and puts them in the appropriate | |
303 | place. */ | |
304 | unsigned long mips_gprmask; | |
305 | unsigned long mips_cprmask[4]; | |
306 | ||
307 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 308 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 309 | |
738f4d98 | 310 | /* True if any MIPS16 code was produced. */ |
a4672219 TS |
311 | static int file_ase_mips16; |
312 | ||
3994f87e TS |
313 | #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \ |
314 | || mips_opts.isa == ISA_MIPS32R2 \ | |
315 | || mips_opts.isa == ISA_MIPS64 \ | |
316 | || mips_opts.isa == ISA_MIPS64R2) | |
317 | ||
df58fc94 RS |
318 | /* True if any microMIPS code was produced. */ |
319 | static int file_ase_micromips; | |
320 | ||
b12dd2e4 CF |
321 | /* True if we want to create R_MIPS_JALR for jalr $25. */ |
322 | #ifdef TE_IRIX | |
1180b5a4 | 323 | #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI |
b12dd2e4 | 324 | #else |
1180b5a4 RS |
325 | /* As a GNU extension, we use R_MIPS_JALR for o32 too. However, |
326 | because there's no place for any addend, the only acceptable | |
327 | expression is a bare symbol. */ | |
328 | #define MIPS_JALR_HINT_P(EXPR) \ | |
329 | (!HAVE_IN_PLACE_ADDENDS \ | |
330 | || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0)) | |
b12dd2e4 CF |
331 | #endif |
332 | ||
1f25f5d3 CD |
333 | /* True if -mips3d was passed or implied by arguments passed on the |
334 | command line (e.g., by -march). */ | |
335 | static int file_ase_mips3d; | |
336 | ||
deec1734 CD |
337 | /* True if -mdmx was passed or implied by arguments passed on the |
338 | command line (e.g., by -march). */ | |
339 | static int file_ase_mdmx; | |
340 | ||
e16bfa71 TS |
341 | /* True if -msmartmips was passed or implied by arguments passed on the |
342 | command line (e.g., by -march). */ | |
343 | static int file_ase_smartmips; | |
344 | ||
ad3fea08 TS |
345 | #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \ |
346 | || mips_opts.isa == ISA_MIPS32R2) | |
e16bfa71 | 347 | |
74cd071d CF |
348 | /* True if -mdsp was passed or implied by arguments passed on the |
349 | command line (e.g., by -march). */ | |
350 | static int file_ase_dsp; | |
351 | ||
ad3fea08 TS |
352 | #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
353 | || mips_opts.isa == ISA_MIPS64R2) | |
354 | ||
65263ce3 TS |
355 | #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2) |
356 | ||
8b082fb1 TS |
357 | /* True if -mdspr2 was passed or implied by arguments passed on the |
358 | command line (e.g., by -march). */ | |
359 | static int file_ase_dspr2; | |
360 | ||
361 | #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \ | |
362 | || mips_opts.isa == ISA_MIPS64R2) | |
363 | ||
ef2e4d86 CF |
364 | /* True if -mmt was passed or implied by arguments passed on the |
365 | command line (e.g., by -march). */ | |
366 | static int file_ase_mt; | |
367 | ||
ad3fea08 TS |
368 | #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
369 | || mips_opts.isa == ISA_MIPS64R2) | |
370 | ||
ec68c924 | 371 | /* The argument of the -march= flag. The architecture we are assembling. */ |
fef14a42 | 372 | static int file_mips_arch = CPU_UNKNOWN; |
316f5878 | 373 | static const char *mips_arch_string; |
ec68c924 EC |
374 | |
375 | /* The argument of the -mtune= flag. The architecture for which we | |
376 | are optimizing. */ | |
377 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 378 | static const char *mips_tune_string; |
ec68c924 | 379 | |
316f5878 | 380 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
381 | static int mips_32bitmode = 0; |
382 | ||
316f5878 RS |
383 | /* True if the given ABI requires 32-bit registers. */ |
384 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
385 | ||
386 | /* Likewise 64-bit registers. */ | |
707bfff6 TS |
387 | #define ABI_NEEDS_64BIT_REGS(ABI) \ |
388 | ((ABI) == N32_ABI \ | |
389 | || (ABI) == N64_ABI \ | |
316f5878 RS |
390 | || (ABI) == O64_ABI) |
391 | ||
ad3fea08 | 392 | /* Return true if ISA supports 64 bit wide gp registers. */ |
707bfff6 TS |
393 | #define ISA_HAS_64BIT_REGS(ISA) \ |
394 | ((ISA) == ISA_MIPS3 \ | |
395 | || (ISA) == ISA_MIPS4 \ | |
396 | || (ISA) == ISA_MIPS5 \ | |
397 | || (ISA) == ISA_MIPS64 \ | |
398 | || (ISA) == ISA_MIPS64R2) | |
9ce8a5dd | 399 | |
ad3fea08 TS |
400 | /* Return true if ISA supports 64 bit wide float registers. */ |
401 | #define ISA_HAS_64BIT_FPRS(ISA) \ | |
402 | ((ISA) == ISA_MIPS3 \ | |
403 | || (ISA) == ISA_MIPS4 \ | |
404 | || (ISA) == ISA_MIPS5 \ | |
405 | || (ISA) == ISA_MIPS32R2 \ | |
406 | || (ISA) == ISA_MIPS64 \ | |
407 | || (ISA) == ISA_MIPS64R2) | |
408 | ||
af7ee8bf CD |
409 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
410 | instructions. */ | |
707bfff6 | 411 | #define ISA_HAS_DROR(ISA) \ |
df58fc94 RS |
412 | ((ISA) == ISA_MIPS64R2 \ |
413 | || (mips_opts.micromips \ | |
414 | && ISA_HAS_64BIT_REGS (ISA)) \ | |
415 | ) | |
af7ee8bf CD |
416 | |
417 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
418 | instructions. */ | |
707bfff6 TS |
419 | #define ISA_HAS_ROR(ISA) \ |
420 | ((ISA) == ISA_MIPS32R2 \ | |
421 | || (ISA) == ISA_MIPS64R2 \ | |
df58fc94 RS |
422 | || mips_opts.ase_smartmips \ |
423 | || mips_opts.micromips \ | |
424 | ) | |
707bfff6 | 425 | |
7455baf8 TS |
426 | /* Return true if ISA supports single-precision floats in odd registers. */ |
427 | #define ISA_HAS_ODD_SINGLE_FPR(ISA) \ | |
428 | ((ISA) == ISA_MIPS32 \ | |
429 | || (ISA) == ISA_MIPS32R2 \ | |
430 | || (ISA) == ISA_MIPS64 \ | |
431 | || (ISA) == ISA_MIPS64R2) | |
af7ee8bf | 432 | |
ad3fea08 TS |
433 | /* Return true if ISA supports move to/from high part of a 64-bit |
434 | floating-point register. */ | |
435 | #define ISA_HAS_MXHC1(ISA) \ | |
436 | ((ISA) == ISA_MIPS32R2 \ | |
437 | || (ISA) == ISA_MIPS64R2) | |
438 | ||
e013f690 | 439 | #define HAVE_32BIT_GPRS \ |
ad3fea08 | 440 | (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 441 | |
e013f690 | 442 | #define HAVE_32BIT_FPRS \ |
ad3fea08 | 443 | (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa)) |
ca4e0257 | 444 | |
ad3fea08 TS |
445 | #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS) |
446 | #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS) | |
ca4e0257 | 447 | |
316f5878 | 448 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 449 | |
316f5878 | 450 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 451 | |
3b91255e RS |
452 | /* True if relocations are stored in-place. */ |
453 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
454 | ||
aed1a261 RS |
455 | /* The ABI-derived address size. */ |
456 | #define HAVE_64BIT_ADDRESSES \ | |
457 | (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) | |
458 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) | |
e013f690 | 459 | |
aed1a261 RS |
460 | /* The size of symbolic constants (i.e., expressions of the form |
461 | "SYMBOL" or "SYMBOL + OFFSET"). */ | |
462 | #define HAVE_32BIT_SYMBOLS \ | |
463 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) | |
464 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) | |
ca4e0257 | 465 | |
b7c7d6c1 TS |
466 | /* Addresses are loaded in different ways, depending on the address size |
467 | in use. The n32 ABI Documentation also mandates the use of additions | |
468 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 469 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 470 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
471 | |
472 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 473 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
474 | |
475 | #define ADDRESS_LOAD_INSN \ | |
476 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
477 | ||
478 | #define ADDRESS_STORE_INSN \ | |
479 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
480 | ||
a4672219 | 481 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
482 | #define CPU_HAS_MIPS16(cpu) \ |
483 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
484 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 485 | |
2309ddf2 | 486 | /* Return true if the given CPU supports the microMIPS ASE. */ |
df58fc94 RS |
487 | #define CPU_HAS_MICROMIPS(cpu) 0 |
488 | ||
60b63b72 RS |
489 | /* True if CPU has a dror instruction. */ |
490 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
491 | ||
492 | /* True if CPU has a ror instruction. */ | |
493 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
494 | ||
dd3cbb7e NC |
495 | /* True if CPU has seq/sne and seqi/snei instructions. */ |
496 | #define CPU_HAS_SEQ(CPU) ((CPU) == CPU_OCTEON) | |
497 | ||
b19e8a9b AN |
498 | /* True if CPU does not implement the all the coprocessor insns. For these |
499 | CPUs only those COP insns are accepted that are explicitly marked to be | |
500 | available on the CPU. ISA membership for COP insns is ignored. */ | |
501 | #define NO_ISA_COP(CPU) ((CPU) == CPU_OCTEON) | |
502 | ||
c8978940 CD |
503 | /* True if mflo and mfhi can be immediately followed by instructions |
504 | which write to the HI and LO registers. | |
505 | ||
506 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
507 | (at least) two instructions between the reads of HI/LO and | |
508 | instructions which write them, and later ISAs do not. Contradicting | |
509 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
510 | the UM for the NEC Vr5000) document needing the instructions between | |
511 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
512 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
513 | earlier-ISA CPUs for which CPU documentation declares that the | |
514 | instructions are really interlocked. */ | |
515 | #define hilo_interlocks \ | |
516 | (mips_opts.isa == ISA_MIPS32 \ | |
517 | || mips_opts.isa == ISA_MIPS32R2 \ | |
518 | || mips_opts.isa == ISA_MIPS64 \ | |
519 | || mips_opts.isa == ISA_MIPS64R2 \ | |
520 | || mips_opts.arch == CPU_R4010 \ | |
521 | || mips_opts.arch == CPU_R10000 \ | |
522 | || mips_opts.arch == CPU_R12000 \ | |
3aa3176b TS |
523 | || mips_opts.arch == CPU_R14000 \ |
524 | || mips_opts.arch == CPU_R16000 \ | |
c8978940 | 525 | || mips_opts.arch == CPU_RM7000 \ |
c8978940 | 526 | || mips_opts.arch == CPU_VR5500 \ |
df58fc94 | 527 | || mips_opts.micromips \ |
c8978940 | 528 | ) |
252b5132 RH |
529 | |
530 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
531 | from the GPRs after they are loaded from memory, and thus does not |
532 | require nops to be inserted. This applies to instructions marked | |
533 | INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA | |
df58fc94 RS |
534 | level I and microMIPS mode instructions are always interlocked. */ |
535 | #define gpr_interlocks \ | |
536 | (mips_opts.isa != ISA_MIPS1 \ | |
537 | || mips_opts.arch == CPU_R3900 \ | |
538 | || mips_opts.micromips \ | |
539 | ) | |
252b5132 | 540 | |
81912461 ILT |
541 | /* Whether the processor uses hardware interlocks to avoid delays |
542 | required by coprocessor instructions, and thus does not require | |
543 | nops to be inserted. This applies to instructions marked | |
544 | INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays | |
545 | between instructions marked INSN_WRITE_COND_CODE and ones marked | |
546 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA | |
df58fc94 RS |
547 | levels I, II, and III and microMIPS mode instructions are always |
548 | interlocked. */ | |
bdaaa2e1 | 549 | /* Itbl support may require additional care here. */ |
81912461 ILT |
550 | #define cop_interlocks \ |
551 | ((mips_opts.isa != ISA_MIPS1 \ | |
552 | && mips_opts.isa != ISA_MIPS2 \ | |
553 | && mips_opts.isa != ISA_MIPS3) \ | |
554 | || mips_opts.arch == CPU_R4300 \ | |
df58fc94 | 555 | || mips_opts.micromips \ |
81912461 ILT |
556 | ) |
557 | ||
558 | /* Whether the processor uses hardware interlocks to protect reads | |
559 | from coprocessor registers after they are loaded from memory, and | |
560 | thus does not require nops to be inserted. This applies to | |
561 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
df58fc94 RS |
562 | requires at MIPS ISA level I and microMIPS mode instructions are |
563 | always interlocked. */ | |
564 | #define cop_mem_interlocks \ | |
565 | (mips_opts.isa != ISA_MIPS1 \ | |
566 | || mips_opts.micromips \ | |
567 | ) | |
252b5132 | 568 | |
6b76fefe CM |
569 | /* Is this a mfhi or mflo instruction? */ |
570 | #define MF_HILO_INSN(PINFO) \ | |
b19e8a9b AN |
571 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) |
572 | ||
573 | /* Returns true for a (non floating-point) coprocessor instruction. Reading | |
574 | or writing the condition code is only possible on the coprocessors and | |
575 | these insns are not marked with INSN_COP. Thus for these insns use the | |
a242dc0d | 576 | condition-code flags. */ |
b19e8a9b AN |
577 | #define COP_INSN(PINFO) \ |
578 | (PINFO != INSN_MACRO \ | |
a242dc0d AN |
579 | && ((PINFO) & (FP_S | FP_D)) == 0 \ |
580 | && ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE))) | |
6b76fefe | 581 | |
df58fc94 RS |
582 | /* Whether code compression (either of the MIPS16 or the microMIPS ASEs) |
583 | has been selected. This implies, in particular, that addresses of text | |
584 | labels have their LSB set. */ | |
585 | #define HAVE_CODE_COMPRESSION \ | |
586 | ((mips_opts.mips16 | mips_opts.micromips) != 0) | |
587 | ||
252b5132 RH |
588 | /* MIPS PIC level. */ |
589 | ||
a161fe53 | 590 | enum mips_pic_level mips_pic; |
252b5132 | 591 | |
c9914766 | 592 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 593 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 594 | static int mips_big_got = 0; |
252b5132 RH |
595 | |
596 | /* 1 if trap instructions should used for overflow rather than break | |
597 | instructions. */ | |
c9914766 | 598 | static int mips_trap = 0; |
252b5132 | 599 | |
119d663a | 600 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 601 | by assembling two single width halves into two single width floating |
119d663a NC |
602 | point registers which just happen to alias the double width destination |
603 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 604 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
605 | automatically at assemble time. */ |
606 | static int mips_disable_float_construction; | |
607 | ||
252b5132 RH |
608 | /* Non-zero if any .set noreorder directives were used. */ |
609 | ||
610 | static int mips_any_noreorder; | |
611 | ||
6b76fefe CM |
612 | /* Non-zero if nops should be inserted when the register referenced in |
613 | an mfhi/mflo instruction is read in the next two instructions. */ | |
614 | static int mips_7000_hilo_fix; | |
615 | ||
02ffd3e4 | 616 | /* The size of objects in the small data section. */ |
156c2f8b | 617 | static unsigned int g_switch_value = 8; |
252b5132 RH |
618 | /* Whether the -G option was used. */ |
619 | static int g_switch_seen = 0; | |
620 | ||
621 | #define N_RMASK 0xc4 | |
622 | #define N_VFP 0xd4 | |
623 | ||
624 | /* If we can determine in advance that GP optimization won't be | |
625 | possible, we can skip the relaxation stuff that tries to produce | |
626 | GP-relative references. This makes delay slot optimization work | |
627 | better. | |
628 | ||
629 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
630 | gcc output. It needs to guess right for gcc, otherwise gcc |
631 | will put what it thinks is a GP-relative instruction in a branch | |
632 | delay slot. | |
252b5132 RH |
633 | |
634 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
635 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 636 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
637 | |
638 | /* handle of the OPCODE hash table */ | |
639 | static struct hash_control *op_hash = NULL; | |
640 | ||
641 | /* The opcode hash table we use for the mips16. */ | |
642 | static struct hash_control *mips16_op_hash = NULL; | |
643 | ||
df58fc94 RS |
644 | /* The opcode hash table we use for the microMIPS ASE. */ |
645 | static struct hash_control *micromips_op_hash = NULL; | |
646 | ||
252b5132 RH |
647 | /* This array holds the chars that always start a comment. If the |
648 | pre-processor is disabled, these aren't very useful */ | |
649 | const char comment_chars[] = "#"; | |
650 | ||
651 | /* This array holds the chars that only start a comment at the beginning of | |
652 | a line. If the line seems to have the form '# 123 filename' | |
653 | .line and .file directives will appear in the pre-processed output */ | |
654 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
655 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 656 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
657 | /* Also note that C style comments are always supported. */ |
658 | const char line_comment_chars[] = "#"; | |
659 | ||
bdaaa2e1 | 660 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 661 | const char line_separator_chars[] = ";"; |
252b5132 RH |
662 | |
663 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
664 | const char EXP_CHARS[] = "eE"; | |
665 | ||
666 | /* Chars that mean this number is a floating point constant */ | |
667 | /* As in 0f12.456 */ | |
668 | /* or 0d1.2345e12 */ | |
669 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
670 | ||
671 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
672 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
673 | but nothing is ideal around here. | |
674 | */ | |
675 | ||
676 | static char *insn_error; | |
677 | ||
678 | static int auto_align = 1; | |
679 | ||
680 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
681 | offset in the stack frame from which to restore the $gp register. | |
682 | This is set by the .cprestore pseudo-op, and saved in this | |
683 | variable. */ | |
684 | static offsetT mips_cprestore_offset = -1; | |
685 | ||
67c1ffbe | 686 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 687 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 688 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
689 | static offsetT mips_cpreturn_offset = -1; |
690 | static int mips_cpreturn_register = -1; | |
691 | static int mips_gp_register = GP; | |
def2e0dd | 692 | static int mips_gprel_offset = 0; |
6478892d | 693 | |
7a621144 DJ |
694 | /* Whether mips_cprestore_offset has been set in the current function |
695 | (or whether it has already been warned about, if not). */ | |
696 | static int mips_cprestore_valid = 0; | |
697 | ||
252b5132 RH |
698 | /* This is the register which holds the stack frame, as set by the |
699 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
700 | static int mips_frame_reg = SP; | |
701 | ||
7a621144 DJ |
702 | /* Whether mips_frame_reg has been set in the current function |
703 | (or whether it has already been warned about, if not). */ | |
704 | static int mips_frame_reg_valid = 0; | |
705 | ||
252b5132 RH |
706 | /* To output NOP instructions correctly, we need to keep information |
707 | about the previous two instructions. */ | |
708 | ||
709 | /* Whether we are optimizing. The default value of 2 means to remove | |
710 | unneeded NOPs and swap branch instructions when possible. A value | |
711 | of 1 means to not swap branches. A value of 0 means to always | |
712 | insert NOPs. */ | |
713 | static int mips_optimize = 2; | |
714 | ||
715 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
716 | equivalent to seeing no -g option at all. */ | |
717 | static int mips_debug = 0; | |
718 | ||
7d8e00cf RS |
719 | /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ |
720 | #define MAX_VR4130_NOPS 4 | |
721 | ||
722 | /* The maximum number of NOPs needed to fill delay slots. */ | |
723 | #define MAX_DELAY_NOPS 2 | |
724 | ||
725 | /* The maximum number of NOPs needed for any purpose. */ | |
726 | #define MAX_NOPS 4 | |
71400594 RS |
727 | |
728 | /* A list of previous instructions, with index 0 being the most recent. | |
729 | We need to look back MAX_NOPS instructions when filling delay slots | |
730 | or working around processor errata. We need to look back one | |
731 | instruction further if we're thinking about using history[0] to | |
732 | fill a branch delay slot. */ | |
733 | static struct mips_cl_insn history[1 + MAX_NOPS]; | |
252b5132 | 734 | |
1e915849 | 735 | /* Nop instructions used by emit_nop. */ |
df58fc94 RS |
736 | static struct mips_cl_insn nop_insn; |
737 | static struct mips_cl_insn mips16_nop_insn; | |
738 | static struct mips_cl_insn micromips_nop16_insn; | |
739 | static struct mips_cl_insn micromips_nop32_insn; | |
1e915849 RS |
740 | |
741 | /* The appropriate nop for the current mode. */ | |
df58fc94 RS |
742 | #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn \ |
743 | : (mips_opts.micromips ? µmips_nop16_insn : &nop_insn)) | |
744 | ||
745 | /* The size of NOP_INSN in bytes. */ | |
746 | #define NOP_INSN_SIZE (HAVE_CODE_COMPRESSION ? 2 : 4) | |
252b5132 | 747 | |
252b5132 RH |
748 | /* If this is set, it points to a frag holding nop instructions which |
749 | were inserted before the start of a noreorder section. If those | |
750 | nops turn out to be unnecessary, the size of the frag can be | |
751 | decreased. */ | |
752 | static fragS *prev_nop_frag; | |
753 | ||
754 | /* The number of nop instructions we created in prev_nop_frag. */ | |
755 | static int prev_nop_frag_holds; | |
756 | ||
757 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 758 | prev_nop_frag. */ |
252b5132 RH |
759 | static int prev_nop_frag_required; |
760 | ||
761 | /* The number of instructions we've seen since prev_nop_frag. */ | |
762 | static int prev_nop_frag_since; | |
763 | ||
764 | /* For ECOFF and ELF, relocations against symbols are done in two | |
765 | parts, with a HI relocation and a LO relocation. Each relocation | |
766 | has only 16 bits of space to store an addend. This means that in | |
767 | order for the linker to handle carries correctly, it must be able | |
768 | to locate both the HI and the LO relocation. This means that the | |
769 | relocations must appear in order in the relocation table. | |
770 | ||
771 | In order to implement this, we keep track of each unmatched HI | |
772 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 773 | corresponding LO relocation. */ |
252b5132 | 774 | |
e972090a NC |
775 | struct mips_hi_fixup |
776 | { | |
252b5132 RH |
777 | /* Next HI fixup. */ |
778 | struct mips_hi_fixup *next; | |
779 | /* This fixup. */ | |
780 | fixS *fixp; | |
781 | /* The section this fixup is in. */ | |
782 | segT seg; | |
783 | }; | |
784 | ||
785 | /* The list of unmatched HI relocs. */ | |
786 | ||
787 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
788 | ||
64bdfcaf RS |
789 | /* The frag containing the last explicit relocation operator. |
790 | Null if explicit relocations have not been used. */ | |
791 | ||
792 | static fragS *prev_reloc_op_frag; | |
793 | ||
252b5132 RH |
794 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
795 | ||
796 | #define X ILLEGAL_REG | |
e972090a NC |
797 | static const int mips32_to_16_reg_map[] = |
798 | { | |
252b5132 RH |
799 | X, X, 2, 3, 4, 5, 6, 7, |
800 | X, X, X, X, X, X, X, X, | |
801 | 0, 1, X, X, X, X, X, X, | |
802 | X, X, X, X, X, X, X, X | |
803 | }; | |
804 | #undef X | |
805 | ||
806 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
807 | ||
e972090a NC |
808 | static const unsigned int mips16_to_32_reg_map[] = |
809 | { | |
252b5132 RH |
810 | 16, 17, 2, 3, 4, 5, 6, 7 |
811 | }; | |
60b63b72 | 812 | |
df58fc94 RS |
813 | /* Map normal MIPS register numbers to microMIPS register numbers. */ |
814 | ||
815 | #define mips32_to_micromips_reg_b_map mips32_to_16_reg_map | |
816 | #define mips32_to_micromips_reg_c_map mips32_to_16_reg_map | |
817 | #define mips32_to_micromips_reg_d_map mips32_to_16_reg_map | |
818 | #define mips32_to_micromips_reg_e_map mips32_to_16_reg_map | |
819 | #define mips32_to_micromips_reg_f_map mips32_to_16_reg_map | |
820 | #define mips32_to_micromips_reg_g_map mips32_to_16_reg_map | |
821 | #define mips32_to_micromips_reg_l_map mips32_to_16_reg_map | |
822 | ||
823 | #define X ILLEGAL_REG | |
824 | /* reg type h: 4, 5, 6. */ | |
825 | static const int mips32_to_micromips_reg_h_map[] = | |
826 | { | |
827 | X, X, X, X, 4, 5, 6, X, | |
828 | X, X, X, X, X, X, X, X, | |
829 | X, X, X, X, X, X, X, X, | |
830 | X, X, X, X, X, X, X, X | |
831 | }; | |
832 | ||
833 | /* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */ | |
834 | static const int mips32_to_micromips_reg_m_map[] = | |
835 | { | |
836 | 0, X, 2, 3, X, X, X, X, | |
837 | X, X, X, X, X, X, X, X, | |
838 | 4, 1, 5, 6, 7, X, X, X, | |
839 | X, X, X, X, X, X, X, X | |
840 | }; | |
841 | ||
842 | /* reg type q: 0, 2-7. 17. */ | |
843 | static const int mips32_to_micromips_reg_q_map[] = | |
844 | { | |
845 | 0, X, 2, 3, 4, 5, 6, 7, | |
846 | X, X, X, X, X, X, X, X, | |
847 | X, 1, X, X, X, X, X, X, | |
848 | X, X, X, X, X, X, X, X | |
849 | }; | |
850 | ||
851 | #define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map | |
852 | #undef X | |
853 | ||
854 | /* Map microMIPS register numbers to normal MIPS register numbers. */ | |
855 | ||
856 | #define micromips_to_32_reg_b_map mips16_to_32_reg_map | |
857 | #define micromips_to_32_reg_c_map mips16_to_32_reg_map | |
858 | #define micromips_to_32_reg_d_map mips16_to_32_reg_map | |
859 | #define micromips_to_32_reg_e_map mips16_to_32_reg_map | |
860 | #define micromips_to_32_reg_f_map mips16_to_32_reg_map | |
861 | #define micromips_to_32_reg_g_map mips16_to_32_reg_map | |
862 | ||
863 | /* The microMIPS registers with type h. */ | |
864 | static const unsigned int micromips_to_32_reg_h_map[] = | |
865 | { | |
866 | 5, 5, 6, 4, 4, 4, 4, 4 | |
867 | }; | |
868 | ||
869 | /* The microMIPS registers with type i. */ | |
870 | static const unsigned int micromips_to_32_reg_i_map[] = | |
871 | { | |
872 | 6, 7, 7, 21, 22, 5, 6, 7 | |
873 | }; | |
874 | ||
875 | #define micromips_to_32_reg_l_map mips16_to_32_reg_map | |
876 | ||
877 | /* The microMIPS registers with type m. */ | |
878 | static const unsigned int micromips_to_32_reg_m_map[] = | |
879 | { | |
880 | 0, 17, 2, 3, 16, 18, 19, 20 | |
881 | }; | |
882 | ||
883 | #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map | |
884 | ||
885 | /* The microMIPS registers with type q. */ | |
886 | static const unsigned int micromips_to_32_reg_q_map[] = | |
887 | { | |
888 | 0, 17, 2, 3, 4, 5, 6, 7 | |
889 | }; | |
890 | ||
891 | /* microMIPS imm type B. */ | |
892 | static const int micromips_imm_b_map[] = | |
893 | { | |
894 | 1, 4, 8, 12, 16, 20, 24, -1 | |
895 | }; | |
896 | ||
897 | /* microMIPS imm type C. */ | |
898 | static const int micromips_imm_c_map[] = | |
899 | { | |
900 | 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535 | |
901 | }; | |
902 | ||
71400594 RS |
903 | /* Classifies the kind of instructions we're interested in when |
904 | implementing -mfix-vr4120. */ | |
c67a084a NC |
905 | enum fix_vr4120_class |
906 | { | |
71400594 RS |
907 | FIX_VR4120_MACC, |
908 | FIX_VR4120_DMACC, | |
909 | FIX_VR4120_MULT, | |
910 | FIX_VR4120_DMULT, | |
911 | FIX_VR4120_DIV, | |
912 | FIX_VR4120_MTHILO, | |
913 | NUM_FIX_VR4120_CLASSES | |
914 | }; | |
915 | ||
c67a084a NC |
916 | /* ...likewise -mfix-loongson2f-jump. */ |
917 | static bfd_boolean mips_fix_loongson2f_jump; | |
918 | ||
919 | /* ...likewise -mfix-loongson2f-nop. */ | |
920 | static bfd_boolean mips_fix_loongson2f_nop; | |
921 | ||
922 | /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */ | |
923 | static bfd_boolean mips_fix_loongson2f; | |
924 | ||
71400594 RS |
925 | /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if |
926 | there must be at least one other instruction between an instruction | |
927 | of type X and an instruction of type Y. */ | |
928 | static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; | |
929 | ||
930 | /* True if -mfix-vr4120 is in force. */ | |
d766e8ec | 931 | static int mips_fix_vr4120; |
4a6a3df4 | 932 | |
7d8e00cf RS |
933 | /* ...likewise -mfix-vr4130. */ |
934 | static int mips_fix_vr4130; | |
935 | ||
6a32d874 CM |
936 | /* ...likewise -mfix-24k. */ |
937 | static int mips_fix_24k; | |
938 | ||
d954098f DD |
939 | /* ...likewise -mfix-cn63xxp1 */ |
940 | static bfd_boolean mips_fix_cn63xxp1; | |
941 | ||
4a6a3df4 AO |
942 | /* We don't relax branches by default, since this causes us to expand |
943 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
944 | fail to compute the offset before expanding the macro to the most | |
945 | efficient expansion. */ | |
946 | ||
947 | static int mips_relax_branch; | |
252b5132 | 948 | \f |
4d7206a2 RS |
949 | /* The expansion of many macros depends on the type of symbol that |
950 | they refer to. For example, when generating position-dependent code, | |
951 | a macro that refers to a symbol may have two different expansions, | |
952 | one which uses GP-relative addresses and one which uses absolute | |
953 | addresses. When generating SVR4-style PIC, a macro may have | |
954 | different expansions for local and global symbols. | |
955 | ||
956 | We handle these situations by generating both sequences and putting | |
957 | them in variant frags. In position-dependent code, the first sequence | |
958 | will be the GP-relative one and the second sequence will be the | |
959 | absolute one. In SVR4 PIC, the first sequence will be for global | |
960 | symbols and the second will be for local symbols. | |
961 | ||
584892a6 RS |
962 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
963 | SECOND are the lengths of the two sequences in bytes. These fields | |
964 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
965 | the subtype has the following flags: | |
4d7206a2 | 966 | |
584892a6 RS |
967 | RELAX_USE_SECOND |
968 | Set if it has been decided that we should use the second | |
969 | sequence instead of the first. | |
970 | ||
971 | RELAX_SECOND_LONGER | |
972 | Set in the first variant frag if the macro's second implementation | |
973 | is longer than its first. This refers to the macro as a whole, | |
974 | not an individual relaxation. | |
975 | ||
976 | RELAX_NOMACRO | |
977 | Set in the first variant frag if the macro appeared in a .set nomacro | |
978 | block and if one alternative requires a warning but the other does not. | |
979 | ||
980 | RELAX_DELAY_SLOT | |
981 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
982 | delay slot. | |
4d7206a2 | 983 | |
df58fc94 RS |
984 | RELAX_DELAY_SLOT_16BIT |
985 | Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a | |
986 | 16-bit instruction. | |
987 | ||
988 | RELAX_DELAY_SLOT_SIZE_FIRST | |
989 | Like RELAX_DELAY_SLOT, but indicates that the first implementation of | |
990 | the macro is of the wrong size for the branch delay slot. | |
991 | ||
992 | RELAX_DELAY_SLOT_SIZE_SECOND | |
993 | Like RELAX_DELAY_SLOT, but indicates that the second implementation of | |
994 | the macro is of the wrong size for the branch delay slot. | |
995 | ||
4d7206a2 RS |
996 | The frag's "opcode" points to the first fixup for relaxable code. |
997 | ||
998 | Relaxable macros are generated using a sequence such as: | |
999 | ||
1000 | relax_start (SYMBOL); | |
1001 | ... generate first expansion ... | |
1002 | relax_switch (); | |
1003 | ... generate second expansion ... | |
1004 | relax_end (); | |
1005 | ||
1006 | The code and fixups for the unwanted alternative are discarded | |
1007 | by md_convert_frag. */ | |
584892a6 | 1008 | #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) |
4d7206a2 | 1009 | |
584892a6 RS |
1010 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
1011 | #define RELAX_SECOND(X) ((X) & 0xff) | |
1012 | #define RELAX_USE_SECOND 0x10000 | |
1013 | #define RELAX_SECOND_LONGER 0x20000 | |
1014 | #define RELAX_NOMACRO 0x40000 | |
1015 | #define RELAX_DELAY_SLOT 0x80000 | |
df58fc94 RS |
1016 | #define RELAX_DELAY_SLOT_16BIT 0x100000 |
1017 | #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000 | |
1018 | #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000 | |
252b5132 | 1019 | |
4a6a3df4 AO |
1020 | /* Branch without likely bit. If label is out of range, we turn: |
1021 | ||
1022 | beq reg1, reg2, label | |
1023 | delay slot | |
1024 | ||
1025 | into | |
1026 | ||
1027 | bne reg1, reg2, 0f | |
1028 | nop | |
1029 | j label | |
1030 | 0: delay slot | |
1031 | ||
1032 | with the following opcode replacements: | |
1033 | ||
1034 | beq <-> bne | |
1035 | blez <-> bgtz | |
1036 | bltz <-> bgez | |
1037 | bc1f <-> bc1t | |
1038 | ||
1039 | bltzal <-> bgezal (with jal label instead of j label) | |
1040 | ||
1041 | Even though keeping the delay slot instruction in the delay slot of | |
1042 | the branch would be more efficient, it would be very tricky to do | |
1043 | correctly, because we'd have to introduce a variable frag *after* | |
1044 | the delay slot instruction, and expand that instead. Let's do it | |
1045 | the easy way for now, even if the branch-not-taken case now costs | |
1046 | one additional instruction. Out-of-range branches are not supposed | |
1047 | to be common, anyway. | |
1048 | ||
1049 | Branch likely. If label is out of range, we turn: | |
1050 | ||
1051 | beql reg1, reg2, label | |
1052 | delay slot (annulled if branch not taken) | |
1053 | ||
1054 | into | |
1055 | ||
1056 | beql reg1, reg2, 1f | |
1057 | nop | |
1058 | beql $0, $0, 2f | |
1059 | nop | |
1060 | 1: j[al] label | |
1061 | delay slot (executed only if branch taken) | |
1062 | 2: | |
1063 | ||
1064 | It would be possible to generate a shorter sequence by losing the | |
1065 | likely bit, generating something like: | |
b34976b6 | 1066 | |
4a6a3df4 AO |
1067 | bne reg1, reg2, 0f |
1068 | nop | |
1069 | j[al] label | |
1070 | delay slot (executed only if branch taken) | |
1071 | 0: | |
1072 | ||
1073 | beql -> bne | |
1074 | bnel -> beq | |
1075 | blezl -> bgtz | |
1076 | bgtzl -> blez | |
1077 | bltzl -> bgez | |
1078 | bgezl -> bltz | |
1079 | bc1fl -> bc1t | |
1080 | bc1tl -> bc1f | |
1081 | ||
1082 | bltzall -> bgezal (with jal label instead of j label) | |
1083 | bgezall -> bltzal (ditto) | |
1084 | ||
1085 | ||
1086 | but it's not clear that it would actually improve performance. */ | |
66b3e8da MR |
1087 | #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \ |
1088 | ((relax_substateT) \ | |
1089 | (0xc0000000 \ | |
1090 | | ((at) & 0x1f) \ | |
1091 | | ((toofar) ? 0x20 : 0) \ | |
1092 | | ((link) ? 0x40 : 0) \ | |
1093 | | ((likely) ? 0x80 : 0) \ | |
1094 | | ((uncond) ? 0x100 : 0))) | |
4a6a3df4 | 1095 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
66b3e8da MR |
1096 | #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0) |
1097 | #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0) | |
1098 | #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0) | |
1099 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0) | |
1100 | #define RELAX_BRANCH_AT(i) ((i) & 0x1f) | |
4a6a3df4 | 1101 | |
252b5132 RH |
1102 | /* For mips16 code, we use an entirely different form of relaxation. |
1103 | mips16 supports two versions of most instructions which take | |
1104 | immediate values: a small one which takes some small value, and a | |
1105 | larger one which takes a 16 bit value. Since branches also follow | |
1106 | this pattern, relaxing these values is required. | |
1107 | ||
1108 | We can assemble both mips16 and normal MIPS code in a single | |
1109 | object. Therefore, we need to support this type of relaxation at | |
1110 | the same time that we support the relaxation described above. We | |
1111 | use the high bit of the subtype field to distinguish these cases. | |
1112 | ||
1113 | The information we store for this type of relaxation is the | |
1114 | argument code found in the opcode file for this relocation, whether | |
1115 | the user explicitly requested a small or extended form, and whether | |
1116 | the relocation is in a jump or jal delay slot. That tells us the | |
1117 | size of the value, and how it should be stored. We also store | |
1118 | whether the fragment is considered to be extended or not. We also | |
1119 | store whether this is known to be a branch to a different section, | |
1120 | whether we have tried to relax this frag yet, and whether we have | |
1121 | ever extended a PC relative fragment because of a shift count. */ | |
1122 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
1123 | (0x80000000 \ | |
1124 | | ((type) & 0xff) \ | |
1125 | | ((small) ? 0x100 : 0) \ | |
1126 | | ((ext) ? 0x200 : 0) \ | |
1127 | | ((dslot) ? 0x400 : 0) \ | |
1128 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 1129 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
1130 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
1131 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
1132 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
1133 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
1134 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
1135 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
1136 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
1137 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
1138 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
1139 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
1140 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 | 1141 | |
df58fc94 RS |
1142 | /* For microMIPS code, we use relaxation similar to one we use for |
1143 | MIPS16 code. Some instructions that take immediate values support | |
1144 | two encodings: a small one which takes some small value, and a | |
1145 | larger one which takes a 16 bit value. As some branches also follow | |
1146 | this pattern, relaxing these values is required. | |
1147 | ||
1148 | We can assemble both microMIPS and normal MIPS code in a single | |
1149 | object. Therefore, we need to support this type of relaxation at | |
1150 | the same time that we support the relaxation described above. We | |
1151 | use one of the high bits of the subtype field to distinguish these | |
1152 | cases. | |
1153 | ||
1154 | The information we store for this type of relaxation is the argument | |
1155 | code found in the opcode file for this relocation, the register | |
40209cad MR |
1156 | selected as the assembler temporary, whether the branch is |
1157 | unconditional, whether it is compact, whether it stores the link | |
1158 | address implicitly in $ra, whether relaxation of out-of-range 32-bit | |
1159 | branches to a sequence of instructions is enabled, and whether the | |
1160 | displacement of a branch is too large to fit as an immediate argument | |
1161 | of a 16-bit and a 32-bit branch, respectively. */ | |
1162 | #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \ | |
1163 | relax32, toofar16, toofar32) \ | |
1164 | (0x40000000 \ | |
1165 | | ((type) & 0xff) \ | |
1166 | | (((at) & 0x1f) << 8) \ | |
1167 | | ((uncond) ? 0x2000 : 0) \ | |
1168 | | ((compact) ? 0x4000 : 0) \ | |
1169 | | ((link) ? 0x8000 : 0) \ | |
1170 | | ((relax32) ? 0x10000 : 0) \ | |
1171 | | ((toofar16) ? 0x20000 : 0) \ | |
1172 | | ((toofar32) ? 0x40000 : 0)) | |
df58fc94 RS |
1173 | #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000) |
1174 | #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff) | |
1175 | #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f) | |
40209cad MR |
1176 | #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0) |
1177 | #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0) | |
1178 | #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0) | |
1179 | #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0) | |
1180 | ||
1181 | #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0) | |
1182 | #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000) | |
1183 | #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000) | |
1184 | #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0) | |
1185 | #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000) | |
1186 | #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000) | |
df58fc94 | 1187 | |
885add95 CD |
1188 | /* Is the given value a sign-extended 32-bit value? */ |
1189 | #define IS_SEXT_32BIT_NUM(x) \ | |
1190 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
1191 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
1192 | ||
1193 | /* Is the given value a sign-extended 16-bit value? */ | |
1194 | #define IS_SEXT_16BIT_NUM(x) \ | |
1195 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
1196 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
1197 | ||
df58fc94 RS |
1198 | /* Is the given value a sign-extended 12-bit value? */ |
1199 | #define IS_SEXT_12BIT_NUM(x) \ | |
1200 | (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x)) | |
1201 | ||
2051e8c4 MR |
1202 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ |
1203 | #define IS_ZEXT_32BIT_NUM(x) \ | |
1204 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
1205 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
1206 | ||
bf12938e RS |
1207 | /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in |
1208 | VALUE << SHIFT. VALUE is evaluated exactly once. */ | |
1209 | #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \ | |
1210 | (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \ | |
1211 | | (((VALUE) & (MASK)) << (SHIFT))) | |
1212 | ||
1213 | /* Extract bits MASK << SHIFT from STRUCT and shift them right | |
1214 | SHIFT places. */ | |
1215 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
1216 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
1217 | ||
1218 | /* Change INSN's opcode so that the operand given by FIELD has value VALUE. | |
1219 | INSN is a mips_cl_insn structure and VALUE is evaluated exactly once. | |
1220 | ||
1221 | include/opcode/mips.h specifies operand fields using the macros | |
1222 | OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start | |
1223 | with "MIPS16OP" instead of "OP". */ | |
df58fc94 RS |
1224 | #define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \ |
1225 | do \ | |
1226 | if (!(MICROMIPS)) \ | |
1227 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1228 | OP_MASK_##FIELD, OP_SH_##FIELD); \ | |
1229 | else \ | |
1230 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1231 | MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \ | |
1232 | while (0) | |
bf12938e RS |
1233 | #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \ |
1234 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1235 | MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD) | |
1236 | ||
1237 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ | |
df58fc94 RS |
1238 | #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \ |
1239 | (!(MICROMIPS) \ | |
1240 | ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \ | |
1241 | : EXTRACT_BITS ((INSN).insn_opcode, \ | |
1242 | MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD)) | |
bf12938e RS |
1243 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ |
1244 | EXTRACT_BITS ((INSN).insn_opcode, \ | |
1245 | MIPS16OP_MASK_##FIELD, \ | |
1246 | MIPS16OP_SH_##FIELD) | |
4d7206a2 | 1247 | \f |
df58fc94 RS |
1248 | /* Whether or not we are emitting a branch-likely macro. */ |
1249 | static bfd_boolean emit_branch_likely_macro = FALSE; | |
1250 | ||
4d7206a2 RS |
1251 | /* Global variables used when generating relaxable macros. See the |
1252 | comment above RELAX_ENCODE for more details about how relaxation | |
1253 | is used. */ | |
1254 | static struct { | |
1255 | /* 0 if we're not emitting a relaxable macro. | |
1256 | 1 if we're emitting the first of the two relaxation alternatives. | |
1257 | 2 if we're emitting the second alternative. */ | |
1258 | int sequence; | |
1259 | ||
1260 | /* The first relaxable fixup in the current frag. (In other words, | |
1261 | the first fixup that refers to relaxable code.) */ | |
1262 | fixS *first_fixup; | |
1263 | ||
1264 | /* sizes[0] says how many bytes of the first alternative are stored in | |
1265 | the current frag. Likewise sizes[1] for the second alternative. */ | |
1266 | unsigned int sizes[2]; | |
1267 | ||
1268 | /* The symbol on which the choice of sequence depends. */ | |
1269 | symbolS *symbol; | |
1270 | } mips_relax; | |
252b5132 | 1271 | \f |
584892a6 RS |
1272 | /* Global variables used to decide whether a macro needs a warning. */ |
1273 | static struct { | |
1274 | /* True if the macro is in a branch delay slot. */ | |
1275 | bfd_boolean delay_slot_p; | |
1276 | ||
df58fc94 RS |
1277 | /* Set to the length in bytes required if the macro is in a delay slot |
1278 | that requires a specific length of instruction, otherwise zero. */ | |
1279 | unsigned int delay_slot_length; | |
1280 | ||
584892a6 RS |
1281 | /* For relaxable macros, sizes[0] is the length of the first alternative |
1282 | in bytes and sizes[1] is the length of the second alternative. | |
1283 | For non-relaxable macros, both elements give the length of the | |
1284 | macro in bytes. */ | |
1285 | unsigned int sizes[2]; | |
1286 | ||
df58fc94 RS |
1287 | /* For relaxable macros, first_insn_sizes[0] is the length of the first |
1288 | instruction of the first alternative in bytes and first_insn_sizes[1] | |
1289 | is the length of the first instruction of the second alternative. | |
1290 | For non-relaxable macros, both elements give the length of the first | |
1291 | instruction in bytes. | |
1292 | ||
1293 | Set to zero if we haven't yet seen the first instruction. */ | |
1294 | unsigned int first_insn_sizes[2]; | |
1295 | ||
1296 | /* For relaxable macros, insns[0] is the number of instructions for the | |
1297 | first alternative and insns[1] is the number of instructions for the | |
1298 | second alternative. | |
1299 | ||
1300 | For non-relaxable macros, both elements give the number of | |
1301 | instructions for the macro. */ | |
1302 | unsigned int insns[2]; | |
1303 | ||
584892a6 RS |
1304 | /* The first variant frag for this macro. */ |
1305 | fragS *first_frag; | |
1306 | } mips_macro_warning; | |
1307 | \f | |
252b5132 RH |
1308 | /* Prototypes for static functions. */ |
1309 | ||
17a2f251 | 1310 | #define internalError() \ |
252b5132 | 1311 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) |
252b5132 RH |
1312 | |
1313 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
1314 | ||
b34976b6 | 1315 | static void append_insn |
df58fc94 RS |
1316 | (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *, |
1317 | bfd_boolean expansionp); | |
7d10b47d | 1318 | static void mips_no_prev_insn (void); |
c67a084a | 1319 | static void macro_build (expressionS *, const char *, const char *, ...); |
b34976b6 | 1320 | static void mips16_macro_build |
03ea81db | 1321 | (expressionS *, const char *, const char *, va_list *); |
67c0d1eb | 1322 | static void load_register (int, expressionS *, int); |
584892a6 RS |
1323 | static void macro_start (void); |
1324 | static void macro_end (void); | |
17a2f251 TS |
1325 | static void macro (struct mips_cl_insn * ip); |
1326 | static void mips16_macro (struct mips_cl_insn * ip); | |
17a2f251 TS |
1327 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
1328 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 1329 | static void mips16_immed |
17a2f251 TS |
1330 | (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean, |
1331 | unsigned long *, bfd_boolean *, unsigned short *); | |
5e0116d5 | 1332 | static size_t my_getSmallExpression |
17a2f251 TS |
1333 | (expressionS *, bfd_reloc_code_real_type *, char *); |
1334 | static void my_getExpression (expressionS *, char *); | |
1335 | static void s_align (int); | |
1336 | static void s_change_sec (int); | |
1337 | static void s_change_section (int); | |
1338 | static void s_cons (int); | |
1339 | static void s_float_cons (int); | |
1340 | static void s_mips_globl (int); | |
1341 | static void s_option (int); | |
1342 | static void s_mipsset (int); | |
1343 | static void s_abicalls (int); | |
1344 | static void s_cpload (int); | |
1345 | static void s_cpsetup (int); | |
1346 | static void s_cplocal (int); | |
1347 | static void s_cprestore (int); | |
1348 | static void s_cpreturn (int); | |
741d6ea8 JM |
1349 | static void s_dtprelword (int); |
1350 | static void s_dtpreldword (int); | |
17a2f251 TS |
1351 | static void s_gpvalue (int); |
1352 | static void s_gpword (int); | |
1353 | static void s_gpdword (int); | |
1354 | static void s_cpadd (int); | |
1355 | static void s_insn (int); | |
1356 | static void md_obj_begin (void); | |
1357 | static void md_obj_end (void); | |
1358 | static void s_mips_ent (int); | |
1359 | static void s_mips_end (int); | |
1360 | static void s_mips_frame (int); | |
1361 | static void s_mips_mask (int reg_type); | |
1362 | static void s_mips_stab (int); | |
1363 | static void s_mips_weakext (int); | |
1364 | static void s_mips_file (int); | |
1365 | static void s_mips_loc (int); | |
1366 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 1367 | static int relaxed_branch_length (fragS *, asection *, int); |
17a2f251 | 1368 | static int validate_mips_insn (const struct mips_opcode *); |
df58fc94 RS |
1369 | static int validate_micromips_insn (const struct mips_opcode *); |
1370 | static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int); | |
1371 | static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int); | |
e7af610e NC |
1372 | |
1373 | /* Table and functions used to map between CPU/ISA names, and | |
1374 | ISA levels, and CPU numbers. */ | |
1375 | ||
e972090a NC |
1376 | struct mips_cpu_info |
1377 | { | |
e7af610e | 1378 | const char *name; /* CPU or ISA name. */ |
ad3fea08 | 1379 | int flags; /* ASEs available, or ISA flag. */ |
e7af610e NC |
1380 | int isa; /* ISA level. */ |
1381 | int cpu; /* CPU number (default CPU if ISA). */ | |
1382 | }; | |
1383 | ||
ad3fea08 TS |
1384 | #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ |
1385 | #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */ | |
1386 | #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */ | |
1387 | #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */ | |
1388 | #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */ | |
1389 | #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */ | |
8b082fb1 | 1390 | #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */ |
ad3fea08 | 1391 | |
17a2f251 TS |
1392 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
1393 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
1394 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 RH |
1395 | \f |
1396 | /* Pseudo-op table. | |
1397 | ||
1398 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
1399 | should be defined here, but are currently unsupported: .alias, | |
1400 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
1401 | ||
1402 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1403 | specific to the type of debugging information being generated, and | |
1404 | should be defined by the object format: .aent, .begin, .bend, | |
1405 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
1406 | .vreg. | |
1407 | ||
1408 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1409 | not MIPS CPU specific, but are also not specific to the object file | |
1410 | format. This file is probably the best place to define them, but | |
d84bcf09 | 1411 | they are not currently supported: .asm0, .endr, .lab, .struct. */ |
252b5132 | 1412 | |
e972090a NC |
1413 | static const pseudo_typeS mips_pseudo_table[] = |
1414 | { | |
beae10d5 | 1415 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1416 | {"option", s_option, 0}, |
1417 | {"set", s_mipsset, 0}, | |
1418 | {"rdata", s_change_sec, 'r'}, | |
1419 | {"sdata", s_change_sec, 's'}, | |
1420 | {"livereg", s_ignore, 0}, | |
1421 | {"abicalls", s_abicalls, 0}, | |
1422 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1423 | {"cpsetup", s_cpsetup, 0}, |
1424 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1425 | {"cprestore", s_cprestore, 0}, |
6478892d | 1426 | {"cpreturn", s_cpreturn, 0}, |
741d6ea8 JM |
1427 | {"dtprelword", s_dtprelword, 0}, |
1428 | {"dtpreldword", s_dtpreldword, 0}, | |
6478892d | 1429 | {"gpvalue", s_gpvalue, 0}, |
252b5132 | 1430 | {"gpword", s_gpword, 0}, |
10181a0d | 1431 | {"gpdword", s_gpdword, 0}, |
252b5132 RH |
1432 | {"cpadd", s_cpadd, 0}, |
1433 | {"insn", s_insn, 0}, | |
1434 | ||
beae10d5 | 1435 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 | 1436 | chips. */ |
38a57ae7 | 1437 | {"asciiz", stringer, 8 + 1}, |
252b5132 RH |
1438 | {"bss", s_change_sec, 'b'}, |
1439 | {"err", s_err, 0}, | |
1440 | {"half", s_cons, 1}, | |
1441 | {"dword", s_cons, 3}, | |
1442 | {"weakext", s_mips_weakext, 0}, | |
7c752c2a TS |
1443 | {"origin", s_org, 0}, |
1444 | {"repeat", s_rept, 0}, | |
252b5132 | 1445 | |
998b3c36 MR |
1446 | /* For MIPS this is non-standard, but we define it for consistency. */ |
1447 | {"sbss", s_change_sec, 'B'}, | |
1448 | ||
beae10d5 | 1449 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1450 | here for one reason or another. */ |
1451 | {"align", s_align, 0}, | |
1452 | {"byte", s_cons, 0}, | |
1453 | {"data", s_change_sec, 'd'}, | |
1454 | {"double", s_float_cons, 'd'}, | |
1455 | {"float", s_float_cons, 'f'}, | |
1456 | {"globl", s_mips_globl, 0}, | |
1457 | {"global", s_mips_globl, 0}, | |
1458 | {"hword", s_cons, 1}, | |
1459 | {"int", s_cons, 2}, | |
1460 | {"long", s_cons, 2}, | |
1461 | {"octa", s_cons, 4}, | |
1462 | {"quad", s_cons, 3}, | |
cca86cc8 | 1463 | {"section", s_change_section, 0}, |
252b5132 RH |
1464 | {"short", s_cons, 1}, |
1465 | {"single", s_float_cons, 'f'}, | |
1466 | {"stabn", s_mips_stab, 'n'}, | |
1467 | {"text", s_change_sec, 't'}, | |
1468 | {"word", s_cons, 2}, | |
add56521 | 1469 | |
add56521 | 1470 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1471 | |
43841e91 | 1472 | { NULL, NULL, 0 }, |
252b5132 RH |
1473 | }; |
1474 | ||
e972090a NC |
1475 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1476 | { | |
beae10d5 KH |
1477 | /* These pseudo-ops should be defined by the object file format. |
1478 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1479 | {"aent", s_mips_ent, 1}, |
1480 | {"bgnb", s_ignore, 0}, | |
1481 | {"end", s_mips_end, 0}, | |
1482 | {"endb", s_ignore, 0}, | |
1483 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1484 | {"file", s_mips_file, 0}, |
252b5132 RH |
1485 | {"fmask", s_mips_mask, 'F'}, |
1486 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1487 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1488 | {"mask", s_mips_mask, 'R'}, |
1489 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1490 | { NULL, NULL, 0 }, |
252b5132 RH |
1491 | }; |
1492 | ||
3ae8dd8d MR |
1493 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
1494 | purpose of the `.dc.a' internal pseudo-op. */ | |
1495 | ||
1496 | int | |
1497 | mips_address_bytes (void) | |
1498 | { | |
1499 | return HAVE_64BIT_ADDRESSES ? 8 : 4; | |
1500 | } | |
1501 | ||
17a2f251 | 1502 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1503 | |
1504 | void | |
17a2f251 | 1505 | mips_pop_insert (void) |
252b5132 RH |
1506 | { |
1507 | pop_insert (mips_pseudo_table); | |
1508 | if (! ECOFF_DEBUGGING) | |
1509 | pop_insert (mips_nonecoff_pseudo_table); | |
1510 | } | |
1511 | \f | |
1512 | /* Symbols labelling the current insn. */ | |
1513 | ||
e972090a NC |
1514 | struct insn_label_list |
1515 | { | |
252b5132 RH |
1516 | struct insn_label_list *next; |
1517 | symbolS *label; | |
1518 | }; | |
1519 | ||
252b5132 | 1520 | static struct insn_label_list *free_insn_labels; |
742a56fe | 1521 | #define label_list tc_segment_info_data.labels |
252b5132 | 1522 | |
17a2f251 | 1523 | static void mips_clear_insn_labels (void); |
df58fc94 RS |
1524 | static void mips_mark_labels (void); |
1525 | static void mips_compressed_mark_labels (void); | |
252b5132 RH |
1526 | |
1527 | static inline void | |
17a2f251 | 1528 | mips_clear_insn_labels (void) |
252b5132 RH |
1529 | { |
1530 | register struct insn_label_list **pl; | |
a8dbcb85 | 1531 | segment_info_type *si; |
252b5132 | 1532 | |
a8dbcb85 TS |
1533 | if (now_seg) |
1534 | { | |
1535 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1536 | ; | |
1537 | ||
1538 | si = seg_info (now_seg); | |
1539 | *pl = si->label_list; | |
1540 | si->label_list = NULL; | |
1541 | } | |
252b5132 | 1542 | } |
a8dbcb85 | 1543 | |
df58fc94 RS |
1544 | /* Mark instruction labels in MIPS16/microMIPS mode. */ |
1545 | ||
1546 | static inline void | |
1547 | mips_mark_labels (void) | |
1548 | { | |
1549 | if (HAVE_CODE_COMPRESSION) | |
1550 | mips_compressed_mark_labels (); | |
1551 | } | |
252b5132 RH |
1552 | \f |
1553 | static char *expr_end; | |
1554 | ||
1555 | /* Expressions which appear in instructions. These are set by | |
1556 | mips_ip. */ | |
1557 | ||
1558 | static expressionS imm_expr; | |
5f74bc13 | 1559 | static expressionS imm2_expr; |
252b5132 RH |
1560 | static expressionS offset_expr; |
1561 | ||
1562 | /* Relocs associated with imm_expr and offset_expr. */ | |
1563 | ||
f6688943 TS |
1564 | static bfd_reloc_code_real_type imm_reloc[3] |
1565 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1566 | static bfd_reloc_code_real_type offset_reloc[3] | |
1567 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1568 | |
df58fc94 RS |
1569 | /* This is set to the resulting size of the instruction to be produced |
1570 | by mips16_ip if an explicit extension is used or by mips_ip if an | |
1571 | explicit size is supplied. */ | |
252b5132 | 1572 | |
df58fc94 | 1573 | static unsigned int forced_insn_length; |
252b5132 | 1574 | |
7ed4a06a | 1575 | #ifdef OBJ_ELF |
ecb4347a DJ |
1576 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1577 | ECOFF debugging. */ | |
252b5132 RH |
1578 | |
1579 | static segT pdr_seg; | |
7ed4a06a | 1580 | #endif |
252b5132 | 1581 | |
e013f690 TS |
1582 | /* The default target format to use. */ |
1583 | ||
aeffff67 RS |
1584 | #if defined (TE_FreeBSD) |
1585 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd" | |
1586 | #elif defined (TE_TMIPS) | |
1587 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips" | |
1588 | #else | |
1589 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips" | |
1590 | #endif | |
1591 | ||
e013f690 | 1592 | const char * |
17a2f251 | 1593 | mips_target_format (void) |
e013f690 TS |
1594 | { |
1595 | switch (OUTPUT_FLAVOR) | |
1596 | { | |
e013f690 TS |
1597 | case bfd_target_ecoff_flavour: |
1598 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1599 | case bfd_target_coff_flavour: | |
1600 | return "pe-mips"; | |
1601 | case bfd_target_elf_flavour: | |
0a44bf69 RS |
1602 | #ifdef TE_VXWORKS |
1603 | if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI) | |
1604 | return (target_big_endian | |
1605 | ? "elf32-bigmips-vxworks" | |
1606 | : "elf32-littlemips-vxworks"); | |
1607 | #endif | |
e013f690 | 1608 | return (target_big_endian |
cfe86eaa | 1609 | ? (HAVE_64BIT_OBJECTS |
aeffff67 | 1610 | ? ELF_TARGET ("elf64-", "big") |
cfe86eaa | 1611 | : (HAVE_NEWABI |
aeffff67 RS |
1612 | ? ELF_TARGET ("elf32-n", "big") |
1613 | : ELF_TARGET ("elf32-", "big"))) | |
cfe86eaa | 1614 | : (HAVE_64BIT_OBJECTS |
aeffff67 | 1615 | ? ELF_TARGET ("elf64-", "little") |
cfe86eaa | 1616 | : (HAVE_NEWABI |
aeffff67 RS |
1617 | ? ELF_TARGET ("elf32-n", "little") |
1618 | : ELF_TARGET ("elf32-", "little")))); | |
e013f690 TS |
1619 | default: |
1620 | abort (); | |
1621 | return NULL; | |
1622 | } | |
1623 | } | |
1624 | ||
df58fc94 RS |
1625 | /* Return the length of a microMIPS instruction in bytes. If bits of |
1626 | the mask beyond the low 16 are 0, then it is a 16-bit instruction. | |
1627 | Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f | |
1628 | major opcode) will require further modifications to the opcode | |
1629 | table. */ | |
1630 | ||
1631 | static inline unsigned int | |
1632 | micromips_insn_length (const struct mips_opcode *mo) | |
1633 | { | |
1634 | return (mo->mask >> 16) == 0 ? 2 : 4; | |
1635 | } | |
1636 | ||
1e915849 RS |
1637 | /* Return the length of instruction INSN. */ |
1638 | ||
1639 | static inline unsigned int | |
1640 | insn_length (const struct mips_cl_insn *insn) | |
1641 | { | |
df58fc94 RS |
1642 | if (mips_opts.micromips) |
1643 | return micromips_insn_length (insn->insn_mo); | |
1644 | else if (mips_opts.mips16) | |
1645 | return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2; | |
1646 | else | |
1e915849 | 1647 | return 4; |
1e915849 RS |
1648 | } |
1649 | ||
1650 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
1651 | ||
1652 | static void | |
1653 | create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) | |
1654 | { | |
1655 | size_t i; | |
1656 | ||
1657 | insn->insn_mo = mo; | |
1658 | insn->use_extend = FALSE; | |
1659 | insn->extend = 0; | |
1660 | insn->insn_opcode = mo->match; | |
1661 | insn->frag = NULL; | |
1662 | insn->where = 0; | |
1663 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1664 | insn->fixp[i] = NULL; | |
1665 | insn->fixed_p = (mips_opts.noreorder > 0); | |
1666 | insn->noreorder_p = (mips_opts.noreorder > 0); | |
1667 | insn->mips16_absolute_jump_p = 0; | |
15be625d | 1668 | insn->complete_p = 0; |
1e915849 RS |
1669 | } |
1670 | ||
df58fc94 | 1671 | /* Record the current MIPS16/microMIPS mode in now_seg. */ |
742a56fe RS |
1672 | |
1673 | static void | |
df58fc94 | 1674 | mips_record_compressed_mode (void) |
742a56fe RS |
1675 | { |
1676 | segment_info_type *si; | |
1677 | ||
1678 | si = seg_info (now_seg); | |
1679 | if (si->tc_segment_info_data.mips16 != mips_opts.mips16) | |
1680 | si->tc_segment_info_data.mips16 = mips_opts.mips16; | |
df58fc94 RS |
1681 | if (si->tc_segment_info_data.micromips != mips_opts.micromips) |
1682 | si->tc_segment_info_data.micromips = mips_opts.micromips; | |
742a56fe RS |
1683 | } |
1684 | ||
1e915849 RS |
1685 | /* Install INSN at the location specified by its "frag" and "where" fields. */ |
1686 | ||
1687 | static void | |
1688 | install_insn (const struct mips_cl_insn *insn) | |
1689 | { | |
1690 | char *f = insn->frag->fr_literal + insn->where; | |
df58fc94 | 1691 | if (!HAVE_CODE_COMPRESSION) |
1e915849 | 1692 | md_number_to_chars (f, insn->insn_opcode, 4); |
df58fc94 RS |
1693 | else if (mips_opts.micromips) |
1694 | { | |
1695 | unsigned int length = insn_length (insn); | |
1696 | if (length == 2) | |
1697 | md_number_to_chars (f, insn->insn_opcode, 2); | |
1698 | else if (length == 4) | |
1699 | { | |
1700 | md_number_to_chars (f, insn->insn_opcode >> 16, 2); | |
1701 | f += 2; | |
1702 | md_number_to_chars (f, insn->insn_opcode & 0xffff, 2); | |
1703 | } | |
1704 | else | |
1705 | as_bad (_("48-bit microMIPS instructions are not supported")); | |
1706 | } | |
1e915849 RS |
1707 | else if (insn->mips16_absolute_jump_p) |
1708 | { | |
1709 | md_number_to_chars (f, insn->insn_opcode >> 16, 2); | |
1710 | md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2); | |
1711 | } | |
1712 | else | |
1713 | { | |
1714 | if (insn->use_extend) | |
1715 | { | |
1716 | md_number_to_chars (f, 0xf000 | insn->extend, 2); | |
1717 | f += 2; | |
1718 | } | |
1719 | md_number_to_chars (f, insn->insn_opcode, 2); | |
1720 | } | |
df58fc94 | 1721 | mips_record_compressed_mode (); |
1e915849 RS |
1722 | } |
1723 | ||
1724 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
1725 | and install the opcode in the new location. */ | |
1726 | ||
1727 | static void | |
1728 | move_insn (struct mips_cl_insn *insn, fragS *frag, long where) | |
1729 | { | |
1730 | size_t i; | |
1731 | ||
1732 | insn->frag = frag; | |
1733 | insn->where = where; | |
1734 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1735 | if (insn->fixp[i] != NULL) | |
1736 | { | |
1737 | insn->fixp[i]->fx_frag = frag; | |
1738 | insn->fixp[i]->fx_where = where; | |
1739 | } | |
1740 | install_insn (insn); | |
1741 | } | |
1742 | ||
1743 | /* Add INSN to the end of the output. */ | |
1744 | ||
1745 | static void | |
1746 | add_fixed_insn (struct mips_cl_insn *insn) | |
1747 | { | |
1748 | char *f = frag_more (insn_length (insn)); | |
1749 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
1750 | } | |
1751 | ||
1752 | /* Start a variant frag and move INSN to the start of the variant part, | |
1753 | marking it as fixed. The other arguments are as for frag_var. */ | |
1754 | ||
1755 | static void | |
1756 | add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, | |
1757 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
1758 | { | |
1759 | frag_grow (max_chars); | |
1760 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
1761 | insn->fixed_p = 1; | |
1762 | frag_var (rs_machine_dependent, max_chars, var, | |
1763 | subtype, symbol, offset, NULL); | |
1764 | } | |
1765 | ||
1766 | /* Insert N copies of INSN into the history buffer, starting at | |
1767 | position FIRST. Neither FIRST nor N need to be clipped. */ | |
1768 | ||
1769 | static void | |
1770 | insert_into_history (unsigned int first, unsigned int n, | |
1771 | const struct mips_cl_insn *insn) | |
1772 | { | |
1773 | if (mips_relax.sequence != 2) | |
1774 | { | |
1775 | unsigned int i; | |
1776 | ||
1777 | for (i = ARRAY_SIZE (history); i-- > first;) | |
1778 | if (i >= first + n) | |
1779 | history[i] = history[i - n]; | |
1780 | else | |
1781 | history[i] = *insn; | |
1782 | } | |
1783 | } | |
1784 | ||
71400594 RS |
1785 | /* Initialize vr4120_conflicts. There is a bit of duplication here: |
1786 | the idea is to make it obvious at a glance that each errata is | |
1787 | included. */ | |
1788 | ||
1789 | static void | |
1790 | init_vr4120_conflicts (void) | |
1791 | { | |
1792 | #define CONFLICT(FIRST, SECOND) \ | |
1793 | vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND | |
1794 | ||
1795 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
1796 | CONFLICT (MACC, DIV); | |
1797 | CONFLICT (DMACC, DIV); | |
1798 | ||
1799 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ | |
1800 | CONFLICT (DMULT, DMULT); | |
1801 | CONFLICT (DMULT, DMACC); | |
1802 | CONFLICT (DMACC, DMULT); | |
1803 | CONFLICT (DMACC, DMACC); | |
1804 | ||
1805 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
1806 | CONFLICT (MACC, MTHILO); | |
1807 | CONFLICT (DMACC, MTHILO); | |
1808 | ||
1809 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU | |
1810 | instruction is executed immediately after a MACC or DMACC | |
1811 | instruction, the result of [either instruction] is incorrect." */ | |
1812 | CONFLICT (MACC, MULT); | |
1813 | CONFLICT (MACC, DMULT); | |
1814 | CONFLICT (DMACC, MULT); | |
1815 | CONFLICT (DMACC, DMULT); | |
1816 | ||
1817 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
1818 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
1819 | DDIV or DDIVU instruction, the result of the MACC or | |
1820 | DMACC instruction is incorrect.". */ | |
1821 | CONFLICT (DMULT, MACC); | |
1822 | CONFLICT (DMULT, DMACC); | |
1823 | CONFLICT (DIV, MACC); | |
1824 | CONFLICT (DIV, DMACC); | |
1825 | ||
1826 | #undef CONFLICT | |
1827 | } | |
1828 | ||
707bfff6 TS |
1829 | struct regname { |
1830 | const char *name; | |
1831 | unsigned int num; | |
1832 | }; | |
1833 | ||
1834 | #define RTYPE_MASK 0x1ff00 | |
1835 | #define RTYPE_NUM 0x00100 | |
1836 | #define RTYPE_FPU 0x00200 | |
1837 | #define RTYPE_FCC 0x00400 | |
1838 | #define RTYPE_VEC 0x00800 | |
1839 | #define RTYPE_GP 0x01000 | |
1840 | #define RTYPE_CP0 0x02000 | |
1841 | #define RTYPE_PC 0x04000 | |
1842 | #define RTYPE_ACC 0x08000 | |
1843 | #define RTYPE_CCC 0x10000 | |
1844 | #define RNUM_MASK 0x000ff | |
1845 | #define RWARN 0x80000 | |
1846 | ||
1847 | #define GENERIC_REGISTER_NUMBERS \ | |
1848 | {"$0", RTYPE_NUM | 0}, \ | |
1849 | {"$1", RTYPE_NUM | 1}, \ | |
1850 | {"$2", RTYPE_NUM | 2}, \ | |
1851 | {"$3", RTYPE_NUM | 3}, \ | |
1852 | {"$4", RTYPE_NUM | 4}, \ | |
1853 | {"$5", RTYPE_NUM | 5}, \ | |
1854 | {"$6", RTYPE_NUM | 6}, \ | |
1855 | {"$7", RTYPE_NUM | 7}, \ | |
1856 | {"$8", RTYPE_NUM | 8}, \ | |
1857 | {"$9", RTYPE_NUM | 9}, \ | |
1858 | {"$10", RTYPE_NUM | 10}, \ | |
1859 | {"$11", RTYPE_NUM | 11}, \ | |
1860 | {"$12", RTYPE_NUM | 12}, \ | |
1861 | {"$13", RTYPE_NUM | 13}, \ | |
1862 | {"$14", RTYPE_NUM | 14}, \ | |
1863 | {"$15", RTYPE_NUM | 15}, \ | |
1864 | {"$16", RTYPE_NUM | 16}, \ | |
1865 | {"$17", RTYPE_NUM | 17}, \ | |
1866 | {"$18", RTYPE_NUM | 18}, \ | |
1867 | {"$19", RTYPE_NUM | 19}, \ | |
1868 | {"$20", RTYPE_NUM | 20}, \ | |
1869 | {"$21", RTYPE_NUM | 21}, \ | |
1870 | {"$22", RTYPE_NUM | 22}, \ | |
1871 | {"$23", RTYPE_NUM | 23}, \ | |
1872 | {"$24", RTYPE_NUM | 24}, \ | |
1873 | {"$25", RTYPE_NUM | 25}, \ | |
1874 | {"$26", RTYPE_NUM | 26}, \ | |
1875 | {"$27", RTYPE_NUM | 27}, \ | |
1876 | {"$28", RTYPE_NUM | 28}, \ | |
1877 | {"$29", RTYPE_NUM | 29}, \ | |
1878 | {"$30", RTYPE_NUM | 30}, \ | |
1879 | {"$31", RTYPE_NUM | 31} | |
1880 | ||
1881 | #define FPU_REGISTER_NAMES \ | |
1882 | {"$f0", RTYPE_FPU | 0}, \ | |
1883 | {"$f1", RTYPE_FPU | 1}, \ | |
1884 | {"$f2", RTYPE_FPU | 2}, \ | |
1885 | {"$f3", RTYPE_FPU | 3}, \ | |
1886 | {"$f4", RTYPE_FPU | 4}, \ | |
1887 | {"$f5", RTYPE_FPU | 5}, \ | |
1888 | {"$f6", RTYPE_FPU | 6}, \ | |
1889 | {"$f7", RTYPE_FPU | 7}, \ | |
1890 | {"$f8", RTYPE_FPU | 8}, \ | |
1891 | {"$f9", RTYPE_FPU | 9}, \ | |
1892 | {"$f10", RTYPE_FPU | 10}, \ | |
1893 | {"$f11", RTYPE_FPU | 11}, \ | |
1894 | {"$f12", RTYPE_FPU | 12}, \ | |
1895 | {"$f13", RTYPE_FPU | 13}, \ | |
1896 | {"$f14", RTYPE_FPU | 14}, \ | |
1897 | {"$f15", RTYPE_FPU | 15}, \ | |
1898 | {"$f16", RTYPE_FPU | 16}, \ | |
1899 | {"$f17", RTYPE_FPU | 17}, \ | |
1900 | {"$f18", RTYPE_FPU | 18}, \ | |
1901 | {"$f19", RTYPE_FPU | 19}, \ | |
1902 | {"$f20", RTYPE_FPU | 20}, \ | |
1903 | {"$f21", RTYPE_FPU | 21}, \ | |
1904 | {"$f22", RTYPE_FPU | 22}, \ | |
1905 | {"$f23", RTYPE_FPU | 23}, \ | |
1906 | {"$f24", RTYPE_FPU | 24}, \ | |
1907 | {"$f25", RTYPE_FPU | 25}, \ | |
1908 | {"$f26", RTYPE_FPU | 26}, \ | |
1909 | {"$f27", RTYPE_FPU | 27}, \ | |
1910 | {"$f28", RTYPE_FPU | 28}, \ | |
1911 | {"$f29", RTYPE_FPU | 29}, \ | |
1912 | {"$f30", RTYPE_FPU | 30}, \ | |
1913 | {"$f31", RTYPE_FPU | 31} | |
1914 | ||
1915 | #define FPU_CONDITION_CODE_NAMES \ | |
1916 | {"$fcc0", RTYPE_FCC | 0}, \ | |
1917 | {"$fcc1", RTYPE_FCC | 1}, \ | |
1918 | {"$fcc2", RTYPE_FCC | 2}, \ | |
1919 | {"$fcc3", RTYPE_FCC | 3}, \ | |
1920 | {"$fcc4", RTYPE_FCC | 4}, \ | |
1921 | {"$fcc5", RTYPE_FCC | 5}, \ | |
1922 | {"$fcc6", RTYPE_FCC | 6}, \ | |
1923 | {"$fcc7", RTYPE_FCC | 7} | |
1924 | ||
1925 | #define COPROC_CONDITION_CODE_NAMES \ | |
1926 | {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \ | |
1927 | {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \ | |
1928 | {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \ | |
1929 | {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \ | |
1930 | {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \ | |
1931 | {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \ | |
1932 | {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \ | |
1933 | {"$cc7", RTYPE_FCC | RTYPE_CCC | 7} | |
1934 | ||
1935 | #define N32N64_SYMBOLIC_REGISTER_NAMES \ | |
1936 | {"$a4", RTYPE_GP | 8}, \ | |
1937 | {"$a5", RTYPE_GP | 9}, \ | |
1938 | {"$a6", RTYPE_GP | 10}, \ | |
1939 | {"$a7", RTYPE_GP | 11}, \ | |
1940 | {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \ | |
1941 | {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \ | |
1942 | {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \ | |
1943 | {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \ | |
1944 | {"$t0", RTYPE_GP | 12}, \ | |
1945 | {"$t1", RTYPE_GP | 13}, \ | |
1946 | {"$t2", RTYPE_GP | 14}, \ | |
1947 | {"$t3", RTYPE_GP | 15} | |
1948 | ||
1949 | #define O32_SYMBOLIC_REGISTER_NAMES \ | |
1950 | {"$t0", RTYPE_GP | 8}, \ | |
1951 | {"$t1", RTYPE_GP | 9}, \ | |
1952 | {"$t2", RTYPE_GP | 10}, \ | |
1953 | {"$t3", RTYPE_GP | 11}, \ | |
1954 | {"$t4", RTYPE_GP | 12}, \ | |
1955 | {"$t5", RTYPE_GP | 13}, \ | |
1956 | {"$t6", RTYPE_GP | 14}, \ | |
1957 | {"$t7", RTYPE_GP | 15}, \ | |
1958 | {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \ | |
1959 | {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \ | |
1960 | {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \ | |
1961 | {"$ta3", RTYPE_GP | 15} /* alias for $t7 */ | |
1962 | ||
1963 | /* Remaining symbolic register names */ | |
1964 | #define SYMBOLIC_REGISTER_NAMES \ | |
1965 | {"$zero", RTYPE_GP | 0}, \ | |
1966 | {"$at", RTYPE_GP | 1}, \ | |
1967 | {"$AT", RTYPE_GP | 1}, \ | |
1968 | {"$v0", RTYPE_GP | 2}, \ | |
1969 | {"$v1", RTYPE_GP | 3}, \ | |
1970 | {"$a0", RTYPE_GP | 4}, \ | |
1971 | {"$a1", RTYPE_GP | 5}, \ | |
1972 | {"$a2", RTYPE_GP | 6}, \ | |
1973 | {"$a3", RTYPE_GP | 7}, \ | |
1974 | {"$s0", RTYPE_GP | 16}, \ | |
1975 | {"$s1", RTYPE_GP | 17}, \ | |
1976 | {"$s2", RTYPE_GP | 18}, \ | |
1977 | {"$s3", RTYPE_GP | 19}, \ | |
1978 | {"$s4", RTYPE_GP | 20}, \ | |
1979 | {"$s5", RTYPE_GP | 21}, \ | |
1980 | {"$s6", RTYPE_GP | 22}, \ | |
1981 | {"$s7", RTYPE_GP | 23}, \ | |
1982 | {"$t8", RTYPE_GP | 24}, \ | |
1983 | {"$t9", RTYPE_GP | 25}, \ | |
1984 | {"$k0", RTYPE_GP | 26}, \ | |
1985 | {"$kt0", RTYPE_GP | 26}, \ | |
1986 | {"$k1", RTYPE_GP | 27}, \ | |
1987 | {"$kt1", RTYPE_GP | 27}, \ | |
1988 | {"$gp", RTYPE_GP | 28}, \ | |
1989 | {"$sp", RTYPE_GP | 29}, \ | |
1990 | {"$s8", RTYPE_GP | 30}, \ | |
1991 | {"$fp", RTYPE_GP | 30}, \ | |
1992 | {"$ra", RTYPE_GP | 31} | |
1993 | ||
1994 | #define MIPS16_SPECIAL_REGISTER_NAMES \ | |
1995 | {"$pc", RTYPE_PC | 0} | |
1996 | ||
1997 | #define MDMX_VECTOR_REGISTER_NAMES \ | |
1998 | /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \ | |
1999 | /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \ | |
2000 | {"$v2", RTYPE_VEC | 2}, \ | |
2001 | {"$v3", RTYPE_VEC | 3}, \ | |
2002 | {"$v4", RTYPE_VEC | 4}, \ | |
2003 | {"$v5", RTYPE_VEC | 5}, \ | |
2004 | {"$v6", RTYPE_VEC | 6}, \ | |
2005 | {"$v7", RTYPE_VEC | 7}, \ | |
2006 | {"$v8", RTYPE_VEC | 8}, \ | |
2007 | {"$v9", RTYPE_VEC | 9}, \ | |
2008 | {"$v10", RTYPE_VEC | 10}, \ | |
2009 | {"$v11", RTYPE_VEC | 11}, \ | |
2010 | {"$v12", RTYPE_VEC | 12}, \ | |
2011 | {"$v13", RTYPE_VEC | 13}, \ | |
2012 | {"$v14", RTYPE_VEC | 14}, \ | |
2013 | {"$v15", RTYPE_VEC | 15}, \ | |
2014 | {"$v16", RTYPE_VEC | 16}, \ | |
2015 | {"$v17", RTYPE_VEC | 17}, \ | |
2016 | {"$v18", RTYPE_VEC | 18}, \ | |
2017 | {"$v19", RTYPE_VEC | 19}, \ | |
2018 | {"$v20", RTYPE_VEC | 20}, \ | |
2019 | {"$v21", RTYPE_VEC | 21}, \ | |
2020 | {"$v22", RTYPE_VEC | 22}, \ | |
2021 | {"$v23", RTYPE_VEC | 23}, \ | |
2022 | {"$v24", RTYPE_VEC | 24}, \ | |
2023 | {"$v25", RTYPE_VEC | 25}, \ | |
2024 | {"$v26", RTYPE_VEC | 26}, \ | |
2025 | {"$v27", RTYPE_VEC | 27}, \ | |
2026 | {"$v28", RTYPE_VEC | 28}, \ | |
2027 | {"$v29", RTYPE_VEC | 29}, \ | |
2028 | {"$v30", RTYPE_VEC | 30}, \ | |
2029 | {"$v31", RTYPE_VEC | 31} | |
2030 | ||
2031 | #define MIPS_DSP_ACCUMULATOR_NAMES \ | |
2032 | {"$ac0", RTYPE_ACC | 0}, \ | |
2033 | {"$ac1", RTYPE_ACC | 1}, \ | |
2034 | {"$ac2", RTYPE_ACC | 2}, \ | |
2035 | {"$ac3", RTYPE_ACC | 3} | |
2036 | ||
2037 | static const struct regname reg_names[] = { | |
2038 | GENERIC_REGISTER_NUMBERS, | |
2039 | FPU_REGISTER_NAMES, | |
2040 | FPU_CONDITION_CODE_NAMES, | |
2041 | COPROC_CONDITION_CODE_NAMES, | |
2042 | ||
2043 | /* The $txx registers depends on the abi, | |
2044 | these will be added later into the symbol table from | |
2045 | one of the tables below once mips_abi is set after | |
2046 | parsing of arguments from the command line. */ | |
2047 | SYMBOLIC_REGISTER_NAMES, | |
2048 | ||
2049 | MIPS16_SPECIAL_REGISTER_NAMES, | |
2050 | MDMX_VECTOR_REGISTER_NAMES, | |
2051 | MIPS_DSP_ACCUMULATOR_NAMES, | |
2052 | {0, 0} | |
2053 | }; | |
2054 | ||
2055 | static const struct regname reg_names_o32[] = { | |
2056 | O32_SYMBOLIC_REGISTER_NAMES, | |
2057 | {0, 0} | |
2058 | }; | |
2059 | ||
2060 | static const struct regname reg_names_n32n64[] = { | |
2061 | N32N64_SYMBOLIC_REGISTER_NAMES, | |
2062 | {0, 0} | |
2063 | }; | |
2064 | ||
df58fc94 RS |
2065 | /* Check if S points at a valid register specifier according to TYPES. |
2066 | If so, then return 1, advance S to consume the specifier and store | |
2067 | the register's number in REGNOP, otherwise return 0. */ | |
2068 | ||
707bfff6 TS |
2069 | static int |
2070 | reg_lookup (char **s, unsigned int types, unsigned int *regnop) | |
2071 | { | |
2072 | symbolS *symbolP; | |
2073 | char *e; | |
2074 | char save_c; | |
2075 | int reg = -1; | |
2076 | ||
2077 | /* Find end of name. */ | |
2078 | e = *s; | |
2079 | if (is_name_beginner (*e)) | |
2080 | ++e; | |
2081 | while (is_part_of_name (*e)) | |
2082 | ++e; | |
2083 | ||
2084 | /* Terminate name. */ | |
2085 | save_c = *e; | |
2086 | *e = '\0'; | |
2087 | ||
2088 | /* Look for a register symbol. */ | |
2089 | if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section) | |
2090 | { | |
2091 | int r = S_GET_VALUE (symbolP); | |
2092 | if (r & types) | |
2093 | reg = r & RNUM_MASK; | |
2094 | else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2)) | |
2095 | /* Convert GP reg $v0/1 to MDMX reg $v0/1! */ | |
2096 | reg = (r & RNUM_MASK) - 2; | |
2097 | } | |
2098 | /* Else see if this is a register defined in an itbl entry. */ | |
2099 | else if ((types & RTYPE_GP) && itbl_have_entries) | |
2100 | { | |
2101 | char *n = *s; | |
2102 | unsigned long r; | |
2103 | ||
2104 | if (*n == '$') | |
2105 | ++n; | |
2106 | if (itbl_get_reg_val (n, &r)) | |
2107 | reg = r & RNUM_MASK; | |
2108 | } | |
2109 | ||
2110 | /* Advance to next token if a register was recognised. */ | |
2111 | if (reg >= 0) | |
2112 | *s = e; | |
2113 | else if (types & RWARN) | |
20203fb9 | 2114 | as_warn (_("Unrecognized register name `%s'"), *s); |
707bfff6 TS |
2115 | |
2116 | *e = save_c; | |
2117 | if (regnop) | |
2118 | *regnop = reg; | |
2119 | return reg >= 0; | |
2120 | } | |
2121 | ||
df58fc94 RS |
2122 | /* Check if S points at a valid register list according to TYPES. |
2123 | If so, then return 1, advance S to consume the list and store | |
2124 | the registers present on the list as a bitmask of ones in REGLISTP, | |
2125 | otherwise return 0. A valid list comprises a comma-separated | |
2126 | enumeration of valid single registers and/or dash-separated | |
2127 | contiguous register ranges as determined by their numbers. | |
2128 | ||
2129 | As a special exception if one of s0-s7 registers is specified as | |
2130 | the range's lower delimiter and s8 (fp) is its upper one, then no | |
2131 | registers whose numbers place them between s7 and s8 (i.e. $24-$29) | |
2309ddf2 | 2132 | are selected; they have to be listed separately if needed. */ |
df58fc94 RS |
2133 | |
2134 | static int | |
2135 | reglist_lookup (char **s, unsigned int types, unsigned int *reglistp) | |
2136 | { | |
2137 | unsigned int reglist = 0; | |
2138 | unsigned int lastregno; | |
2139 | bfd_boolean ok = TRUE; | |
2140 | unsigned int regmask; | |
2309ddf2 | 2141 | char *s_endlist = *s; |
df58fc94 | 2142 | char *s_reset = *s; |
2309ddf2 | 2143 | unsigned int regno; |
df58fc94 RS |
2144 | |
2145 | while (reg_lookup (s, types, ®no)) | |
2146 | { | |
2147 | lastregno = regno; | |
2148 | if (**s == '-') | |
2149 | { | |
2150 | (*s)++; | |
2151 | ok = reg_lookup (s, types, &lastregno); | |
2152 | if (ok && lastregno < regno) | |
2153 | ok = FALSE; | |
2154 | if (!ok) | |
2155 | break; | |
2156 | } | |
2157 | ||
2158 | if (lastregno == FP && regno >= S0 && regno <= S7) | |
2159 | { | |
2160 | lastregno = S7; | |
2161 | reglist |= 1 << FP; | |
2162 | } | |
2163 | regmask = 1 << lastregno; | |
2164 | regmask = (regmask << 1) - 1; | |
2165 | regmask ^= (1 << regno) - 1; | |
2166 | reglist |= regmask; | |
2167 | ||
2309ddf2 | 2168 | s_endlist = *s; |
df58fc94 RS |
2169 | if (**s != ',') |
2170 | break; | |
2171 | (*s)++; | |
2172 | } | |
2173 | ||
2174 | if (ok) | |
2309ddf2 | 2175 | *s = s_endlist; |
df58fc94 RS |
2176 | else |
2177 | *s = s_reset; | |
2178 | if (reglistp) | |
2179 | *reglistp = reglist; | |
2180 | return ok && reglist != 0; | |
2181 | } | |
2182 | ||
037b32b9 | 2183 | /* Return TRUE if opcode MO is valid on the currently selected ISA and |
f79e2745 | 2184 | architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */ |
037b32b9 AN |
2185 | |
2186 | static bfd_boolean | |
f79e2745 | 2187 | is_opcode_valid (const struct mips_opcode *mo) |
037b32b9 AN |
2188 | { |
2189 | int isa = mips_opts.isa; | |
2190 | int fp_s, fp_d; | |
2191 | ||
2192 | if (mips_opts.ase_mdmx) | |
2193 | isa |= INSN_MDMX; | |
2194 | if (mips_opts.ase_dsp) | |
2195 | isa |= INSN_DSP; | |
2196 | if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE) | |
2197 | isa |= INSN_DSP64; | |
2198 | if (mips_opts.ase_dspr2) | |
2199 | isa |= INSN_DSPR2; | |
2200 | if (mips_opts.ase_mt) | |
2201 | isa |= INSN_MT; | |
2202 | if (mips_opts.ase_mips3d) | |
2203 | isa |= INSN_MIPS3D; | |
2204 | if (mips_opts.ase_smartmips) | |
2205 | isa |= INSN_SMARTMIPS; | |
2206 | ||
b19e8a9b AN |
2207 | /* Don't accept instructions based on the ISA if the CPU does not implement |
2208 | all the coprocessor insns. */ | |
2209 | if (NO_ISA_COP (mips_opts.arch) | |
2210 | && COP_INSN (mo->pinfo)) | |
2211 | isa = 0; | |
2212 | ||
037b32b9 AN |
2213 | if (!OPCODE_IS_MEMBER (mo, isa, mips_opts.arch)) |
2214 | return FALSE; | |
2215 | ||
2216 | /* Check whether the instruction or macro requires single-precision or | |
2217 | double-precision floating-point support. Note that this information is | |
2218 | stored differently in the opcode table for insns and macros. */ | |
2219 | if (mo->pinfo == INSN_MACRO) | |
2220 | { | |
2221 | fp_s = mo->pinfo2 & INSN2_M_FP_S; | |
2222 | fp_d = mo->pinfo2 & INSN2_M_FP_D; | |
2223 | } | |
2224 | else | |
2225 | { | |
2226 | fp_s = mo->pinfo & FP_S; | |
2227 | fp_d = mo->pinfo & FP_D; | |
2228 | } | |
2229 | ||
2230 | if (fp_d && (mips_opts.soft_float || mips_opts.single_float)) | |
2231 | return FALSE; | |
2232 | ||
2233 | if (fp_s && mips_opts.soft_float) | |
2234 | return FALSE; | |
2235 | ||
2236 | return TRUE; | |
2237 | } | |
2238 | ||
2239 | /* Return TRUE if the MIPS16 opcode MO is valid on the currently | |
2240 | selected ISA and architecture. */ | |
2241 | ||
2242 | static bfd_boolean | |
2243 | is_opcode_valid_16 (const struct mips_opcode *mo) | |
2244 | { | |
2245 | return OPCODE_IS_MEMBER (mo, mips_opts.isa, mips_opts.arch) ? TRUE : FALSE; | |
2246 | } | |
2247 | ||
df58fc94 RS |
2248 | /* Return TRUE if the size of the microMIPS opcode MO matches one |
2249 | explicitly requested. Always TRUE in the standard MIPS mode. */ | |
2250 | ||
2251 | static bfd_boolean | |
2252 | is_size_valid (const struct mips_opcode *mo) | |
2253 | { | |
2254 | if (!mips_opts.micromips) | |
2255 | return TRUE; | |
2256 | ||
2257 | if (!forced_insn_length) | |
2258 | return TRUE; | |
2259 | if (mo->pinfo == INSN_MACRO) | |
2260 | return FALSE; | |
2261 | return forced_insn_length == micromips_insn_length (mo); | |
2262 | } | |
2263 | ||
2264 | /* Return TRUE if the microMIPS opcode MO is valid for the delay slot | |
2265 | of the preceding instruction. Always TRUE in the standard MIPS mode. */ | |
2266 | ||
2267 | static bfd_boolean | |
2268 | is_delay_slot_valid (const struct mips_opcode *mo) | |
2269 | { | |
2270 | if (!mips_opts.micromips) | |
2271 | return TRUE; | |
2272 | ||
2273 | if (mo->pinfo == INSN_MACRO) | |
2274 | return TRUE; | |
2275 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 | |
2276 | && micromips_insn_length (mo) != 4) | |
2277 | return FALSE; | |
2278 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 | |
2279 | && micromips_insn_length (mo) != 2) | |
2280 | return FALSE; | |
2281 | ||
2282 | return TRUE; | |
2283 | } | |
2284 | ||
707bfff6 TS |
2285 | /* This function is called once, at assembler startup time. It should set up |
2286 | all the tables, etc. that the MD part of the assembler will need. */ | |
156c2f8b | 2287 | |
252b5132 | 2288 | void |
17a2f251 | 2289 | md_begin (void) |
252b5132 | 2290 | { |
3994f87e | 2291 | const char *retval = NULL; |
156c2f8b | 2292 | int i = 0; |
252b5132 | 2293 | int broken = 0; |
1f25f5d3 | 2294 | |
0a44bf69 RS |
2295 | if (mips_pic != NO_PIC) |
2296 | { | |
2297 | if (g_switch_seen && g_switch_value != 0) | |
2298 | as_bad (_("-G may not be used in position-independent code")); | |
2299 | g_switch_value = 0; | |
2300 | } | |
2301 | ||
fef14a42 | 2302 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) |
252b5132 RH |
2303 | as_warn (_("Could not set architecture and machine")); |
2304 | ||
252b5132 RH |
2305 | op_hash = hash_new (); |
2306 | ||
2307 | for (i = 0; i < NUMOPCODES;) | |
2308 | { | |
2309 | const char *name = mips_opcodes[i].name; | |
2310 | ||
17a2f251 | 2311 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
2312 | if (retval != NULL) |
2313 | { | |
2314 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
2315 | mips_opcodes[i].name, retval); | |
2316 | /* Probably a memory allocation problem? Give up now. */ | |
2317 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
2318 | } | |
2319 | do | |
2320 | { | |
2321 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
2322 | { | |
2323 | if (!validate_mips_insn (&mips_opcodes[i])) | |
2324 | broken = 1; | |
1e915849 RS |
2325 | if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
2326 | { | |
2327 | create_insn (&nop_insn, mips_opcodes + i); | |
c67a084a NC |
2328 | if (mips_fix_loongson2f_nop) |
2329 | nop_insn.insn_opcode = LOONGSON2F_NOP_INSN; | |
1e915849 RS |
2330 | nop_insn.fixed_p = 1; |
2331 | } | |
252b5132 RH |
2332 | } |
2333 | ++i; | |
2334 | } | |
2335 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
2336 | } | |
2337 | ||
2338 | mips16_op_hash = hash_new (); | |
2339 | ||
2340 | i = 0; | |
2341 | while (i < bfd_mips16_num_opcodes) | |
2342 | { | |
2343 | const char *name = mips16_opcodes[i].name; | |
2344 | ||
17a2f251 | 2345 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
2346 | if (retval != NULL) |
2347 | as_fatal (_("internal: can't hash `%s': %s"), | |
2348 | mips16_opcodes[i].name, retval); | |
2349 | do | |
2350 | { | |
2351 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
2352 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
2353 | != mips16_opcodes[i].match)) | |
2354 | { | |
2355 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
2356 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
2357 | broken = 1; | |
2358 | } | |
1e915849 RS |
2359 | if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
2360 | { | |
2361 | create_insn (&mips16_nop_insn, mips16_opcodes + i); | |
2362 | mips16_nop_insn.fixed_p = 1; | |
2363 | } | |
252b5132 RH |
2364 | ++i; |
2365 | } | |
2366 | while (i < bfd_mips16_num_opcodes | |
2367 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
2368 | } | |
2369 | ||
df58fc94 RS |
2370 | micromips_op_hash = hash_new (); |
2371 | ||
2372 | i = 0; | |
2373 | while (i < bfd_micromips_num_opcodes) | |
2374 | { | |
2375 | const char *name = micromips_opcodes[i].name; | |
2376 | ||
2377 | retval = hash_insert (micromips_op_hash, name, | |
2378 | (void *) µmips_opcodes[i]); | |
2379 | if (retval != NULL) | |
2380 | as_fatal (_("internal: can't hash `%s': %s"), | |
2381 | micromips_opcodes[i].name, retval); | |
2382 | do | |
2383 | if (micromips_opcodes[i].pinfo != INSN_MACRO) | |
2384 | { | |
2385 | struct mips_cl_insn *micromips_nop_insn; | |
2386 | ||
2387 | if (!validate_micromips_insn (µmips_opcodes[i])) | |
2388 | broken = 1; | |
2389 | ||
2390 | if (micromips_insn_length (micromips_opcodes + i) == 2) | |
2391 | micromips_nop_insn = µmips_nop16_insn; | |
2392 | else if (micromips_insn_length (micromips_opcodes + i) == 4) | |
2393 | micromips_nop_insn = µmips_nop32_insn; | |
2394 | else | |
2395 | continue; | |
2396 | ||
2397 | if (micromips_nop_insn->insn_mo == NULL | |
2398 | && strcmp (name, "nop") == 0) | |
2399 | { | |
2400 | create_insn (micromips_nop_insn, micromips_opcodes + i); | |
2401 | micromips_nop_insn->fixed_p = 1; | |
2402 | } | |
2403 | } | |
2404 | while (++i < bfd_micromips_num_opcodes | |
2405 | && strcmp (micromips_opcodes[i].name, name) == 0); | |
2406 | } | |
2407 | ||
252b5132 RH |
2408 | if (broken) |
2409 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
2410 | ||
2411 | /* We add all the general register names to the symbol table. This | |
2412 | helps us detect invalid uses of them. */ | |
707bfff6 TS |
2413 | for (i = 0; reg_names[i].name; i++) |
2414 | symbol_table_insert (symbol_new (reg_names[i].name, reg_section, | |
8fc4ee9b | 2415 | reg_names[i].num, /* & RNUM_MASK, */ |
707bfff6 TS |
2416 | &zero_address_frag)); |
2417 | if (HAVE_NEWABI) | |
2418 | for (i = 0; reg_names_n32n64[i].name; i++) | |
2419 | symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section, | |
8fc4ee9b | 2420 | reg_names_n32n64[i].num, /* & RNUM_MASK, */ |
252b5132 | 2421 | &zero_address_frag)); |
707bfff6 TS |
2422 | else |
2423 | for (i = 0; reg_names_o32[i].name; i++) | |
2424 | symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section, | |
8fc4ee9b | 2425 | reg_names_o32[i].num, /* & RNUM_MASK, */ |
6047c971 | 2426 | &zero_address_frag)); |
6047c971 | 2427 | |
7d10b47d | 2428 | mips_no_prev_insn (); |
252b5132 RH |
2429 | |
2430 | mips_gprmask = 0; | |
2431 | mips_cprmask[0] = 0; | |
2432 | mips_cprmask[1] = 0; | |
2433 | mips_cprmask[2] = 0; | |
2434 | mips_cprmask[3] = 0; | |
2435 | ||
2436 | /* set the default alignment for the text section (2**2) */ | |
2437 | record_alignment (text_section, 2); | |
2438 | ||
4d0d148d | 2439 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 | 2440 | |
707bfff6 | 2441 | #ifdef OBJ_ELF |
f43abd2b | 2442 | if (IS_ELF) |
252b5132 | 2443 | { |
0a44bf69 RS |
2444 | /* On a native system other than VxWorks, sections must be aligned |
2445 | to 16 byte boundaries. When configured for an embedded ELF | |
2446 | target, we don't bother. */ | |
c41e87e3 CF |
2447 | if (strncmp (TARGET_OS, "elf", 3) != 0 |
2448 | && strncmp (TARGET_OS, "vxworks", 7) != 0) | |
252b5132 RH |
2449 | { |
2450 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
2451 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
2452 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
2453 | } | |
2454 | ||
2455 | /* Create a .reginfo section for register masks and a .mdebug | |
2456 | section for debugging information. */ | |
2457 | { | |
2458 | segT seg; | |
2459 | subsegT subseg; | |
2460 | flagword flags; | |
2461 | segT sec; | |
2462 | ||
2463 | seg = now_seg; | |
2464 | subseg = now_subseg; | |
2465 | ||
2466 | /* The ABI says this section should be loaded so that the | |
2467 | running program can access it. However, we don't load it | |
2468 | if we are configured for an embedded target */ | |
2469 | flags = SEC_READONLY | SEC_DATA; | |
c41e87e3 | 2470 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
252b5132 RH |
2471 | flags |= SEC_ALLOC | SEC_LOAD; |
2472 | ||
316f5878 | 2473 | if (mips_abi != N64_ABI) |
252b5132 RH |
2474 | { |
2475 | sec = subseg_new (".reginfo", (subsegT) 0); | |
2476 | ||
195325d2 TS |
2477 | bfd_set_section_flags (stdoutput, sec, flags); |
2478 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 2479 | |
252b5132 | 2480 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
252b5132 RH |
2481 | } |
2482 | else | |
2483 | { | |
2484 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
2485 | .reginfo section. */ | |
2486 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
2487 | bfd_set_section_flags (stdoutput, sec, flags); |
2488 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 | 2489 | |
252b5132 RH |
2490 | /* Set up the option header. */ |
2491 | { | |
2492 | Elf_Internal_Options opthdr; | |
2493 | char *f; | |
2494 | ||
2495 | opthdr.kind = ODK_REGINFO; | |
2496 | opthdr.size = (sizeof (Elf_External_Options) | |
2497 | + sizeof (Elf64_External_RegInfo)); | |
2498 | opthdr.section = 0; | |
2499 | opthdr.info = 0; | |
2500 | f = frag_more (sizeof (Elf_External_Options)); | |
2501 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
2502 | (Elf_External_Options *) f); | |
2503 | ||
2504 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
2505 | } | |
252b5132 RH |
2506 | } |
2507 | ||
2508 | if (ECOFF_DEBUGGING) | |
2509 | { | |
2510 | sec = subseg_new (".mdebug", (subsegT) 0); | |
2511 | (void) bfd_set_section_flags (stdoutput, sec, | |
2512 | SEC_HAS_CONTENTS | SEC_READONLY); | |
2513 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
2514 | } | |
f43abd2b | 2515 | else if (mips_flag_pdr) |
ecb4347a DJ |
2516 | { |
2517 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
2518 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
2519 | SEC_READONLY | SEC_RELOC | |
2520 | | SEC_DEBUGGING); | |
2521 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
2522 | } | |
252b5132 RH |
2523 | |
2524 | subseg_set (seg, subseg); | |
2525 | } | |
2526 | } | |
707bfff6 | 2527 | #endif /* OBJ_ELF */ |
252b5132 RH |
2528 | |
2529 | if (! ECOFF_DEBUGGING) | |
2530 | md_obj_begin (); | |
71400594 RS |
2531 | |
2532 | if (mips_fix_vr4120) | |
2533 | init_vr4120_conflicts (); | |
252b5132 RH |
2534 | } |
2535 | ||
2536 | void | |
17a2f251 | 2537 | md_mips_end (void) |
252b5132 | 2538 | { |
02b1ab82 | 2539 | mips_emit_delays (); |
252b5132 RH |
2540 | if (! ECOFF_DEBUGGING) |
2541 | md_obj_end (); | |
2542 | } | |
2543 | ||
2544 | void | |
17a2f251 | 2545 | md_assemble (char *str) |
252b5132 RH |
2546 | { |
2547 | struct mips_cl_insn insn; | |
f6688943 TS |
2548 | bfd_reloc_code_real_type unused_reloc[3] |
2549 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
2550 | |
2551 | imm_expr.X_op = O_absent; | |
5f74bc13 | 2552 | imm2_expr.X_op = O_absent; |
252b5132 | 2553 | offset_expr.X_op = O_absent; |
f6688943 TS |
2554 | imm_reloc[0] = BFD_RELOC_UNUSED; |
2555 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
2556 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
2557 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
2558 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
2559 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2560 | |
2561 | if (mips_opts.mips16) | |
2562 | mips16_ip (str, &insn); | |
2563 | else | |
2564 | { | |
2565 | mips_ip (str, &insn); | |
beae10d5 KH |
2566 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
2567 | str, insn.insn_opcode)); | |
252b5132 RH |
2568 | } |
2569 | ||
2570 | if (insn_error) | |
2571 | { | |
2572 | as_bad ("%s `%s'", insn_error, str); | |
2573 | return; | |
2574 | } | |
2575 | ||
2576 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
2577 | { | |
584892a6 | 2578 | macro_start (); |
252b5132 RH |
2579 | if (mips_opts.mips16) |
2580 | mips16_macro (&insn); | |
2581 | else | |
2582 | macro (&insn); | |
584892a6 | 2583 | macro_end (); |
252b5132 RH |
2584 | } |
2585 | else | |
2586 | { | |
2587 | if (imm_expr.X_op != O_absent) | |
df58fc94 | 2588 | append_insn (&insn, &imm_expr, imm_reloc, FALSE); |
252b5132 | 2589 | else if (offset_expr.X_op != O_absent) |
df58fc94 | 2590 | append_insn (&insn, &offset_expr, offset_reloc, FALSE); |
252b5132 | 2591 | else |
df58fc94 | 2592 | append_insn (&insn, NULL, unused_reloc, FALSE); |
252b5132 RH |
2593 | } |
2594 | } | |
2595 | ||
738e5348 RS |
2596 | /* Convenience functions for abstracting away the differences between |
2597 | MIPS16 and non-MIPS16 relocations. */ | |
2598 | ||
2599 | static inline bfd_boolean | |
2600 | mips16_reloc_p (bfd_reloc_code_real_type reloc) | |
2601 | { | |
2602 | switch (reloc) | |
2603 | { | |
2604 | case BFD_RELOC_MIPS16_JMP: | |
2605 | case BFD_RELOC_MIPS16_GPREL: | |
2606 | case BFD_RELOC_MIPS16_GOT16: | |
2607 | case BFD_RELOC_MIPS16_CALL16: | |
2608 | case BFD_RELOC_MIPS16_HI16_S: | |
2609 | case BFD_RELOC_MIPS16_HI16: | |
2610 | case BFD_RELOC_MIPS16_LO16: | |
2611 | return TRUE; | |
2612 | ||
2613 | default: | |
2614 | return FALSE; | |
2615 | } | |
2616 | } | |
2617 | ||
df58fc94 RS |
2618 | static inline bfd_boolean |
2619 | micromips_reloc_p (bfd_reloc_code_real_type reloc) | |
2620 | { | |
2621 | switch (reloc) | |
2622 | { | |
2623 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: | |
2624 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
2625 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
2626 | case BFD_RELOC_MICROMIPS_GPREL16: | |
2627 | case BFD_RELOC_MICROMIPS_JMP: | |
2628 | case BFD_RELOC_MICROMIPS_HI16: | |
2629 | case BFD_RELOC_MICROMIPS_HI16_S: | |
2630 | case BFD_RELOC_MICROMIPS_LO16: | |
2631 | case BFD_RELOC_MICROMIPS_LITERAL: | |
2632 | case BFD_RELOC_MICROMIPS_GOT16: | |
2633 | case BFD_RELOC_MICROMIPS_CALL16: | |
2634 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
2635 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
2636 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
2637 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
2638 | case BFD_RELOC_MICROMIPS_SUB: | |
2639 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
2640 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
2641 | case BFD_RELOC_MICROMIPS_GOT_DISP: | |
2642 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
2643 | case BFD_RELOC_MICROMIPS_HIGHER: | |
2644 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
2645 | case BFD_RELOC_MICROMIPS_JALR: | |
2646 | return TRUE; | |
2647 | ||
2648 | default: | |
2649 | return FALSE; | |
2650 | } | |
2651 | } | |
2652 | ||
2309ddf2 MR |
2653 | static inline bfd_boolean |
2654 | jmp_reloc_p (bfd_reloc_code_real_type reloc) | |
2655 | { | |
2656 | return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP; | |
2657 | } | |
2658 | ||
738e5348 RS |
2659 | static inline bfd_boolean |
2660 | got16_reloc_p (bfd_reloc_code_real_type reloc) | |
2661 | { | |
2309ddf2 | 2662 | return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16 |
df58fc94 | 2663 | || reloc == BFD_RELOC_MICROMIPS_GOT16); |
738e5348 RS |
2664 | } |
2665 | ||
2666 | static inline bfd_boolean | |
2667 | hi16_reloc_p (bfd_reloc_code_real_type reloc) | |
2668 | { | |
2309ddf2 | 2669 | return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S |
df58fc94 | 2670 | || reloc == BFD_RELOC_MICROMIPS_HI16_S); |
738e5348 RS |
2671 | } |
2672 | ||
2673 | static inline bfd_boolean | |
2674 | lo16_reloc_p (bfd_reloc_code_real_type reloc) | |
2675 | { | |
2309ddf2 | 2676 | return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16 |
df58fc94 RS |
2677 | || reloc == BFD_RELOC_MICROMIPS_LO16); |
2678 | } | |
2679 | ||
df58fc94 RS |
2680 | static inline bfd_boolean |
2681 | jalr_reloc_p (bfd_reloc_code_real_type reloc) | |
2682 | { | |
2309ddf2 | 2683 | return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR; |
738e5348 RS |
2684 | } |
2685 | ||
5919d012 | 2686 | /* Return true if the given relocation might need a matching %lo(). |
0a44bf69 RS |
2687 | This is only "might" because SVR4 R_MIPS_GOT16 relocations only |
2688 | need a matching %lo() when applied to local symbols. */ | |
5919d012 RS |
2689 | |
2690 | static inline bfd_boolean | |
17a2f251 | 2691 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 2692 | { |
3b91255e | 2693 | return (HAVE_IN_PLACE_ADDENDS |
738e5348 | 2694 | && (hi16_reloc_p (reloc) |
0a44bf69 RS |
2695 | /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo(); |
2696 | all GOT16 relocations evaluate to "G". */ | |
738e5348 RS |
2697 | || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC))); |
2698 | } | |
2699 | ||
2700 | /* Return the type of %lo() reloc needed by RELOC, given that | |
2701 | reloc_needs_lo_p. */ | |
2702 | ||
2703 | static inline bfd_reloc_code_real_type | |
2704 | matching_lo_reloc (bfd_reloc_code_real_type reloc) | |
2705 | { | |
df58fc94 RS |
2706 | return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 |
2707 | : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16 | |
2708 | : BFD_RELOC_LO16)); | |
5919d012 RS |
2709 | } |
2710 | ||
2711 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
2712 | relocation. */ | |
2713 | ||
2714 | static inline bfd_boolean | |
17a2f251 | 2715 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
2716 | { |
2717 | return (fixp->fx_next != NULL | |
738e5348 | 2718 | && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type) |
5919d012 RS |
2719 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
2720 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
2721 | } | |
2722 | ||
252b5132 RH |
2723 | /* This function returns true if modifying a register requires a |
2724 | delay. */ | |
2725 | ||
2726 | static int | |
17a2f251 | 2727 | reg_needs_delay (unsigned int reg) |
252b5132 RH |
2728 | { |
2729 | unsigned long prev_pinfo; | |
2730 | ||
47e39b9d | 2731 | prev_pinfo = history[0].insn_mo->pinfo; |
252b5132 | 2732 | if (! mips_opts.noreorder |
81912461 ILT |
2733 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
2734 | && ! gpr_interlocks) | |
2735 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
2736 | && ! cop_interlocks))) | |
252b5132 | 2737 | { |
81912461 ILT |
2738 | /* A load from a coprocessor or from memory. All load delays |
2739 | delay the use of general register rt for one instruction. */ | |
bdaaa2e1 | 2740 | /* Itbl support may require additional care here. */ |
252b5132 | 2741 | know (prev_pinfo & INSN_WRITE_GPR_T); |
df58fc94 | 2742 | if (reg == EXTRACT_OPERAND (mips_opts.micromips, RT, history[0])) |
252b5132 RH |
2743 | return 1; |
2744 | } | |
2745 | ||
2746 | return 0; | |
2747 | } | |
2748 | ||
404a8071 RS |
2749 | /* Move all labels in insn_labels to the current insertion point. */ |
2750 | ||
2751 | static void | |
2752 | mips_move_labels (void) | |
2753 | { | |
a8dbcb85 | 2754 | segment_info_type *si = seg_info (now_seg); |
404a8071 RS |
2755 | struct insn_label_list *l; |
2756 | valueT val; | |
2757 | ||
a8dbcb85 | 2758 | for (l = si->label_list; l != NULL; l = l->next) |
404a8071 | 2759 | { |
9c2799c2 | 2760 | gas_assert (S_GET_SEGMENT (l->label) == now_seg); |
404a8071 RS |
2761 | symbol_set_frag (l->label, frag_now); |
2762 | val = (valueT) frag_now_fix (); | |
df58fc94 RS |
2763 | /* MIPS16/microMIPS text labels are stored as odd. */ |
2764 | if (HAVE_CODE_COMPRESSION) | |
404a8071 RS |
2765 | ++val; |
2766 | S_SET_VALUE (l->label, val); | |
2767 | } | |
2768 | } | |
2769 | ||
5f0fe04b TS |
2770 | static bfd_boolean |
2771 | s_is_linkonce (symbolS *sym, segT from_seg) | |
2772 | { | |
2773 | bfd_boolean linkonce = FALSE; | |
2774 | segT symseg = S_GET_SEGMENT (sym); | |
2775 | ||
2776 | if (symseg != from_seg && !S_IS_LOCAL (sym)) | |
2777 | { | |
2778 | if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE)) | |
2779 | linkonce = TRUE; | |
2780 | #ifdef OBJ_ELF | |
2781 | /* The GNU toolchain uses an extension for ELF: a section | |
2782 | beginning with the magic string .gnu.linkonce is a | |
2783 | linkonce section. */ | |
2784 | if (strncmp (segment_name (symseg), ".gnu.linkonce", | |
2785 | sizeof ".gnu.linkonce" - 1) == 0) | |
2786 | linkonce = TRUE; | |
2787 | #endif | |
2788 | } | |
2789 | return linkonce; | |
2790 | } | |
2791 | ||
df58fc94 RS |
2792 | /* Mark instruction labels in MIPS16/microMIPS mode. This permits the |
2793 | linker to handle them specially, such as generating jalx instructions | |
2794 | when needed. We also make them odd for the duration of the assembly, | |
2795 | in order to generate the right sort of code. We will make them even | |
252b5132 RH |
2796 | in the adjust_symtab routine, while leaving them marked. This is |
2797 | convenient for the debugger and the disassembler. The linker knows | |
2798 | to make them odd again. */ | |
2799 | ||
2800 | static void | |
df58fc94 | 2801 | mips_compressed_mark_labels (void) |
252b5132 | 2802 | { |
a8dbcb85 TS |
2803 | segment_info_type *si = seg_info (now_seg); |
2804 | struct insn_label_list *l; | |
252b5132 | 2805 | |
df58fc94 | 2806 | gas_assert (HAVE_CODE_COMPRESSION); |
a8dbcb85 TS |
2807 | |
2808 | for (l = si->label_list; l != NULL; l = l->next) | |
2809 | { | |
2810 | symbolS *label = l->label; | |
2811 | ||
2812 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) | |
f43abd2b | 2813 | if (IS_ELF) |
df58fc94 RS |
2814 | { |
2815 | if (mips_opts.mips16) | |
2816 | S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label))); | |
2817 | else | |
2818 | S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label))); | |
2819 | } | |
252b5132 | 2820 | #endif |
5f0fe04b TS |
2821 | if ((S_GET_VALUE (label) & 1) == 0 |
2822 | /* Don't adjust the address if the label is global or weak, or | |
2823 | in a link-once section, since we'll be emitting symbol reloc | |
2824 | references to it which will be patched up by the linker, and | |
df58fc94 | 2825 | the final value of the symbol may or may not be MIPS16/microMIPS. */ |
5f0fe04b TS |
2826 | && ! S_IS_WEAK (label) |
2827 | && ! S_IS_EXTERNAL (label) | |
2828 | && ! s_is_linkonce (label, now_seg)) | |
a8dbcb85 | 2829 | S_SET_VALUE (label, S_GET_VALUE (label) | 1); |
252b5132 RH |
2830 | } |
2831 | } | |
2832 | ||
4d7206a2 RS |
2833 | /* End the current frag. Make it a variant frag and record the |
2834 | relaxation info. */ | |
2835 | ||
2836 | static void | |
2837 | relax_close_frag (void) | |
2838 | { | |
584892a6 | 2839 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 2840 | frag_var (rs_machine_dependent, 0, 0, |
584892a6 | 2841 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), |
4d7206a2 RS |
2842 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
2843 | ||
2844 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
2845 | mips_relax.first_fixup = 0; | |
2846 | } | |
2847 | ||
2848 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
2849 | See the comment above RELAX_ENCODE for more details. */ | |
2850 | ||
2851 | static void | |
2852 | relax_start (symbolS *symbol) | |
2853 | { | |
9c2799c2 | 2854 | gas_assert (mips_relax.sequence == 0); |
4d7206a2 RS |
2855 | mips_relax.sequence = 1; |
2856 | mips_relax.symbol = symbol; | |
2857 | } | |
2858 | ||
2859 | /* Start generating the second version of a relaxable sequence. | |
2860 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
2861 | |
2862 | static void | |
4d7206a2 RS |
2863 | relax_switch (void) |
2864 | { | |
9c2799c2 | 2865 | gas_assert (mips_relax.sequence == 1); |
4d7206a2 RS |
2866 | mips_relax.sequence = 2; |
2867 | } | |
2868 | ||
2869 | /* End the current relaxable sequence. */ | |
2870 | ||
2871 | static void | |
2872 | relax_end (void) | |
2873 | { | |
9c2799c2 | 2874 | gas_assert (mips_relax.sequence == 2); |
4d7206a2 RS |
2875 | relax_close_frag (); |
2876 | mips_relax.sequence = 0; | |
2877 | } | |
2878 | ||
11625dd8 RS |
2879 | /* Return true if IP is a delayed branch or jump. */ |
2880 | ||
2881 | static inline bfd_boolean | |
2882 | delayed_branch_p (const struct mips_cl_insn *ip) | |
2883 | { | |
2884 | return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY | |
2885 | | INSN_COND_BRANCH_DELAY | |
2886 | | INSN_COND_BRANCH_LIKELY)) != 0; | |
2887 | } | |
2888 | ||
2889 | /* Return true if IP is a compact branch or jump. */ | |
2890 | ||
2891 | static inline bfd_boolean | |
2892 | compact_branch_p (const struct mips_cl_insn *ip) | |
2893 | { | |
2894 | if (mips_opts.mips16) | |
2895 | return (ip->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH | |
2896 | | MIPS16_INSN_COND_BRANCH)) != 0; | |
2897 | else | |
2898 | return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH | |
2899 | | INSN2_COND_BRANCH)) != 0; | |
2900 | } | |
2901 | ||
2902 | /* Return true if IP is an unconditional branch or jump. */ | |
2903 | ||
2904 | static inline bfd_boolean | |
2905 | uncond_branch_p (const struct mips_cl_insn *ip) | |
2906 | { | |
2907 | return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0 | |
2908 | || (mips_opts.mips16 | |
2909 | ? (ip->insn_mo->pinfo & MIPS16_INSN_UNCOND_BRANCH) != 0 | |
2910 | : (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0)); | |
2911 | } | |
2912 | ||
2913 | /* Return true if IP is a branch-likely instruction. */ | |
2914 | ||
2915 | static inline bfd_boolean | |
2916 | branch_likely_p (const struct mips_cl_insn *ip) | |
2917 | { | |
2918 | return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0; | |
2919 | } | |
2920 | ||
14fe068b RS |
2921 | /* Return the type of nop that should be used to fill the delay slot |
2922 | of delayed branch IP. */ | |
2923 | ||
2924 | static struct mips_cl_insn * | |
2925 | get_delay_slot_nop (const struct mips_cl_insn *ip) | |
2926 | { | |
2927 | if (mips_opts.micromips | |
2928 | && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
2929 | return µmips_nop32_insn; | |
2930 | return NOP_INSN; | |
2931 | } | |
2932 | ||
2309ddf2 | 2933 | /* Return the mask of core registers that IP reads or writes. */ |
df58fc94 RS |
2934 | |
2935 | static unsigned int | |
2936 | gpr_mod_mask (const struct mips_cl_insn *ip) | |
2937 | { | |
2309ddf2 | 2938 | unsigned long pinfo2; |
df58fc94 RS |
2939 | unsigned int mask; |
2940 | ||
2941 | mask = 0; | |
df58fc94 RS |
2942 | pinfo2 = ip->insn_mo->pinfo2; |
2943 | if (mips_opts.micromips) | |
2944 | { | |
2945 | if (pinfo2 & INSN2_MOD_GPR_MB) | |
2946 | mask |= 1 << micromips_to_32_reg_b_map[EXTRACT_OPERAND (1, MB, *ip)]; | |
2947 | if (pinfo2 & INSN2_MOD_GPR_MC) | |
2948 | mask |= 1 << micromips_to_32_reg_c_map[EXTRACT_OPERAND (1, MC, *ip)]; | |
2949 | if (pinfo2 & INSN2_MOD_GPR_MD) | |
2950 | mask |= 1 << micromips_to_32_reg_d_map[EXTRACT_OPERAND (1, MD, *ip)]; | |
2951 | if (pinfo2 & INSN2_MOD_GPR_ME) | |
2952 | mask |= 1 << micromips_to_32_reg_e_map[EXTRACT_OPERAND (1, ME, *ip)]; | |
2953 | if (pinfo2 & INSN2_MOD_GPR_MF) | |
2954 | mask |= 1 << micromips_to_32_reg_f_map[EXTRACT_OPERAND (1, MF, *ip)]; | |
2955 | if (pinfo2 & INSN2_MOD_GPR_MG) | |
2956 | mask |= 1 << micromips_to_32_reg_g_map[EXTRACT_OPERAND (1, MG, *ip)]; | |
2957 | if (pinfo2 & INSN2_MOD_GPR_MHI) | |
2958 | { | |
2959 | mask |= 1 << micromips_to_32_reg_h_map[EXTRACT_OPERAND (1, MH, *ip)]; | |
2960 | mask |= 1 << micromips_to_32_reg_i_map[EXTRACT_OPERAND (1, MI, *ip)]; | |
2961 | } | |
2962 | if (pinfo2 & INSN2_MOD_GPR_MJ) | |
2963 | mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip); | |
2964 | if (pinfo2 & INSN2_MOD_GPR_MM) | |
2965 | mask |= 1 << micromips_to_32_reg_m_map[EXTRACT_OPERAND (1, MM, *ip)]; | |
2966 | if (pinfo2 & INSN2_MOD_GPR_MN) | |
2967 | mask |= 1 << micromips_to_32_reg_n_map[EXTRACT_OPERAND (1, MN, *ip)]; | |
2968 | if (pinfo2 & INSN2_MOD_GPR_MP) | |
2969 | mask |= 1 << EXTRACT_OPERAND (1, MP, *ip); | |
2970 | if (pinfo2 & INSN2_MOD_GPR_MQ) | |
2971 | mask |= 1 << micromips_to_32_reg_q_map[EXTRACT_OPERAND (1, MQ, *ip)]; | |
2972 | if (pinfo2 & INSN2_MOD_SP) | |
2973 | mask |= 1 << SP; | |
2974 | } | |
2975 | return mask; | |
2976 | } | |
2977 | ||
4c260379 RS |
2978 | /* Return the mask of core registers that IP reads. */ |
2979 | ||
2980 | static unsigned int | |
2981 | gpr_read_mask (const struct mips_cl_insn *ip) | |
2982 | { | |
2983 | unsigned long pinfo, pinfo2; | |
2984 | unsigned int mask; | |
2985 | ||
df58fc94 | 2986 | mask = gpr_mod_mask (ip); |
4c260379 RS |
2987 | pinfo = ip->insn_mo->pinfo; |
2988 | pinfo2 = ip->insn_mo->pinfo2; | |
2989 | if (mips_opts.mips16) | |
2990 | { | |
2991 | if (pinfo & MIPS16_INSN_READ_X) | |
2992 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)]; | |
2993 | if (pinfo & MIPS16_INSN_READ_Y) | |
2994 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)]; | |
2995 | if (pinfo & MIPS16_INSN_READ_T) | |
2996 | mask |= 1 << TREG; | |
2997 | if (pinfo & MIPS16_INSN_READ_SP) | |
2998 | mask |= 1 << SP; | |
2999 | if (pinfo & MIPS16_INSN_READ_31) | |
3000 | mask |= 1 << RA; | |
3001 | if (pinfo & MIPS16_INSN_READ_Z) | |
3002 | mask |= 1 << (mips16_to_32_reg_map | |
3003 | [MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]); | |
3004 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
3005 | mask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip); | |
3006 | } | |
3007 | else | |
3008 | { | |
3009 | if (pinfo2 & INSN2_READ_GPR_D) | |
2309ddf2 | 3010 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); |
4c260379 | 3011 | if (pinfo & INSN_READ_GPR_T) |
2309ddf2 | 3012 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); |
4c260379 | 3013 | if (pinfo & INSN_READ_GPR_S) |
2309ddf2 MR |
3014 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); |
3015 | if (pinfo2 & INSN2_READ_GP) | |
3016 | mask |= 1 << GP; | |
3017 | if (pinfo2 & INSN2_READ_GPR_31) | |
3018 | mask |= 1 << RA; | |
4c260379 | 3019 | if (pinfo2 & INSN2_READ_GPR_Z) |
2309ddf2 | 3020 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip); |
4c260379 | 3021 | } |
fe35f09f RS |
3022 | /* Don't include register 0. */ |
3023 | return mask & ~1; | |
4c260379 RS |
3024 | } |
3025 | ||
3026 | /* Return the mask of core registers that IP writes. */ | |
3027 | ||
3028 | static unsigned int | |
3029 | gpr_write_mask (const struct mips_cl_insn *ip) | |
3030 | { | |
3031 | unsigned long pinfo, pinfo2; | |
3032 | unsigned int mask; | |
3033 | ||
df58fc94 | 3034 | mask = gpr_mod_mask (ip); |
4c260379 RS |
3035 | pinfo = ip->insn_mo->pinfo; |
3036 | pinfo2 = ip->insn_mo->pinfo2; | |
3037 | if (mips_opts.mips16) | |
3038 | { | |
3039 | if (pinfo & MIPS16_INSN_WRITE_X) | |
3040 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)]; | |
3041 | if (pinfo & MIPS16_INSN_WRITE_Y) | |
3042 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)]; | |
3043 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
3044 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RZ, *ip)]; | |
3045 | if (pinfo & MIPS16_INSN_WRITE_T) | |
3046 | mask |= 1 << TREG; | |
3047 | if (pinfo & MIPS16_INSN_WRITE_SP) | |
3048 | mask |= 1 << SP; | |
3049 | if (pinfo & MIPS16_INSN_WRITE_31) | |
3050 | mask |= 1 << RA; | |
3051 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
3052 | mask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
3053 | } | |
3054 | else | |
3055 | { | |
3056 | if (pinfo & INSN_WRITE_GPR_D) | |
df58fc94 | 3057 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); |
4c260379 | 3058 | if (pinfo & INSN_WRITE_GPR_T) |
df58fc94 | 3059 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); |
2309ddf2 MR |
3060 | if (pinfo2 & INSN2_WRITE_GPR_S) |
3061 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); | |
4c260379 RS |
3062 | if (pinfo & INSN_WRITE_GPR_31) |
3063 | mask |= 1 << RA; | |
3064 | if (pinfo2 & INSN2_WRITE_GPR_Z) | |
df58fc94 | 3065 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip); |
4c260379 | 3066 | } |
fe35f09f RS |
3067 | /* Don't include register 0. */ |
3068 | return mask & ~1; | |
4c260379 RS |
3069 | } |
3070 | ||
3071 | /* Return the mask of floating-point registers that IP reads. */ | |
3072 | ||
3073 | static unsigned int | |
3074 | fpr_read_mask (const struct mips_cl_insn *ip) | |
3075 | { | |
3076 | unsigned long pinfo, pinfo2; | |
3077 | unsigned int mask; | |
3078 | ||
3079 | mask = 0; | |
3080 | pinfo = ip->insn_mo->pinfo; | |
3081 | pinfo2 = ip->insn_mo->pinfo2; | |
2309ddf2 | 3082 | if (!mips_opts.mips16) |
df58fc94 RS |
3083 | { |
3084 | if (pinfo2 & INSN2_READ_FPR_D) | |
2309ddf2 | 3085 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip); |
4c260379 | 3086 | if (pinfo & INSN_READ_FPR_S) |
df58fc94 | 3087 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip); |
4c260379 | 3088 | if (pinfo & INSN_READ_FPR_T) |
df58fc94 | 3089 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip); |
4c260379 | 3090 | if (pinfo & INSN_READ_FPR_R) |
df58fc94 | 3091 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FR, *ip); |
4c260379 | 3092 | if (pinfo2 & INSN2_READ_FPR_Z) |
df58fc94 | 3093 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip); |
4c260379 RS |
3094 | } |
3095 | /* Conservatively treat all operands to an FP_D instruction are doubles. | |
3096 | (This is overly pessimistic for things like cvt.d.s.) */ | |
3097 | if (HAVE_32BIT_FPRS && (pinfo & FP_D)) | |
3098 | mask |= mask << 1; | |
3099 | return mask; | |
3100 | } | |
3101 | ||
3102 | /* Return the mask of floating-point registers that IP writes. */ | |
3103 | ||
3104 | static unsigned int | |
3105 | fpr_write_mask (const struct mips_cl_insn *ip) | |
3106 | { | |
3107 | unsigned long pinfo, pinfo2; | |
3108 | unsigned int mask; | |
3109 | ||
3110 | mask = 0; | |
3111 | pinfo = ip->insn_mo->pinfo; | |
3112 | pinfo2 = ip->insn_mo->pinfo2; | |
2309ddf2 | 3113 | if (!mips_opts.mips16) |
4c260379 RS |
3114 | { |
3115 | if (pinfo & INSN_WRITE_FPR_D) | |
df58fc94 | 3116 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip); |
4c260379 | 3117 | if (pinfo & INSN_WRITE_FPR_S) |
df58fc94 | 3118 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip); |
4c260379 | 3119 | if (pinfo & INSN_WRITE_FPR_T) |
df58fc94 | 3120 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip); |
4c260379 | 3121 | if (pinfo2 & INSN2_WRITE_FPR_Z) |
df58fc94 | 3122 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip); |
4c260379 RS |
3123 | } |
3124 | /* Conservatively treat all operands to an FP_D instruction are doubles. | |
3125 | (This is overly pessimistic for things like cvt.s.d.) */ | |
3126 | if (HAVE_32BIT_FPRS && (pinfo & FP_D)) | |
3127 | mask |= mask << 1; | |
3128 | return mask; | |
3129 | } | |
3130 | ||
71400594 RS |
3131 | /* Classify an instruction according to the FIX_VR4120_* enumeration. |
3132 | Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected | |
3133 | by VR4120 errata. */ | |
4d7206a2 | 3134 | |
71400594 RS |
3135 | static unsigned int |
3136 | classify_vr4120_insn (const char *name) | |
252b5132 | 3137 | { |
71400594 RS |
3138 | if (strncmp (name, "macc", 4) == 0) |
3139 | return FIX_VR4120_MACC; | |
3140 | if (strncmp (name, "dmacc", 5) == 0) | |
3141 | return FIX_VR4120_DMACC; | |
3142 | if (strncmp (name, "mult", 4) == 0) | |
3143 | return FIX_VR4120_MULT; | |
3144 | if (strncmp (name, "dmult", 5) == 0) | |
3145 | return FIX_VR4120_DMULT; | |
3146 | if (strstr (name, "div")) | |
3147 | return FIX_VR4120_DIV; | |
3148 | if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) | |
3149 | return FIX_VR4120_MTHILO; | |
3150 | return NUM_FIX_VR4120_CLASSES; | |
3151 | } | |
252b5132 | 3152 | |
ff239038 CM |
3153 | #define INSN_ERET 0x42000018 |
3154 | #define INSN_DERET 0x4200001f | |
3155 | ||
71400594 RS |
3156 | /* Return the number of instructions that must separate INSN1 and INSN2, |
3157 | where INSN1 is the earlier instruction. Return the worst-case value | |
3158 | for any INSN2 if INSN2 is null. */ | |
252b5132 | 3159 | |
71400594 RS |
3160 | static unsigned int |
3161 | insns_between (const struct mips_cl_insn *insn1, | |
3162 | const struct mips_cl_insn *insn2) | |
3163 | { | |
3164 | unsigned long pinfo1, pinfo2; | |
4c260379 | 3165 | unsigned int mask; |
71400594 RS |
3166 | |
3167 | /* This function needs to know which pinfo flags are set for INSN2 | |
3168 | and which registers INSN2 uses. The former is stored in PINFO2 and | |
4c260379 RS |
3169 | the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2 |
3170 | will have every flag set and INSN2_USES_GPR will always return true. */ | |
71400594 RS |
3171 | pinfo1 = insn1->insn_mo->pinfo; |
3172 | pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; | |
252b5132 | 3173 | |
4c260379 RS |
3174 | #define INSN2_USES_GPR(REG) \ |
3175 | (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0) | |
71400594 RS |
3176 | |
3177 | /* For most targets, write-after-read dependencies on the HI and LO | |
3178 | registers must be separated by at least two instructions. */ | |
3179 | if (!hilo_interlocks) | |
252b5132 | 3180 | { |
71400594 RS |
3181 | if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) |
3182 | return 2; | |
3183 | if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) | |
3184 | return 2; | |
3185 | } | |
3186 | ||
3187 | /* If we're working around r7000 errata, there must be two instructions | |
3188 | between an mfhi or mflo and any instruction that uses the result. */ | |
3189 | if (mips_7000_hilo_fix | |
df58fc94 | 3190 | && !mips_opts.micromips |
71400594 | 3191 | && MF_HILO_INSN (pinfo1) |
df58fc94 | 3192 | && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD, *insn1))) |
71400594 RS |
3193 | return 2; |
3194 | ||
ff239038 CM |
3195 | /* If we're working around 24K errata, one instruction is required |
3196 | if an ERET or DERET is followed by a branch instruction. */ | |
df58fc94 | 3197 | if (mips_fix_24k && !mips_opts.micromips) |
ff239038 CM |
3198 | { |
3199 | if (insn1->insn_opcode == INSN_ERET | |
3200 | || insn1->insn_opcode == INSN_DERET) | |
3201 | { | |
3202 | if (insn2 == NULL | |
3203 | || insn2->insn_opcode == INSN_ERET | |
3204 | || insn2->insn_opcode == INSN_DERET | |
11625dd8 | 3205 | || delayed_branch_p (insn2)) |
ff239038 CM |
3206 | return 1; |
3207 | } | |
3208 | } | |
3209 | ||
71400594 RS |
3210 | /* If working around VR4120 errata, check for combinations that need |
3211 | a single intervening instruction. */ | |
df58fc94 | 3212 | if (mips_fix_vr4120 && !mips_opts.micromips) |
71400594 RS |
3213 | { |
3214 | unsigned int class1, class2; | |
252b5132 | 3215 | |
71400594 RS |
3216 | class1 = classify_vr4120_insn (insn1->insn_mo->name); |
3217 | if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) | |
252b5132 | 3218 | { |
71400594 RS |
3219 | if (insn2 == NULL) |
3220 | return 1; | |
3221 | class2 = classify_vr4120_insn (insn2->insn_mo->name); | |
3222 | if (vr4120_conflicts[class1] & (1 << class2)) | |
3223 | return 1; | |
252b5132 | 3224 | } |
71400594 RS |
3225 | } |
3226 | ||
df58fc94 | 3227 | if (!HAVE_CODE_COMPRESSION) |
71400594 RS |
3228 | { |
3229 | /* Check for GPR or coprocessor load delays. All such delays | |
3230 | are on the RT register. */ | |
3231 | /* Itbl support may require additional care here. */ | |
3232 | if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY)) | |
3233 | || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY))) | |
252b5132 | 3234 | { |
71400594 | 3235 | know (pinfo1 & INSN_WRITE_GPR_T); |
df58fc94 | 3236 | if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT, *insn1))) |
71400594 RS |
3237 | return 1; |
3238 | } | |
3239 | ||
3240 | /* Check for generic coprocessor hazards. | |
3241 | ||
3242 | This case is not handled very well. There is no special | |
3243 | knowledge of CP0 handling, and the coprocessors other than | |
3244 | the floating point unit are not distinguished at all. */ | |
3245 | /* Itbl support may require additional care here. FIXME! | |
3246 | Need to modify this to include knowledge about | |
3247 | user specified delays! */ | |
3248 | else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY)) | |
3249 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) | |
3250 | { | |
3251 | /* Handle cases where INSN1 writes to a known general coprocessor | |
3252 | register. There must be a one instruction delay before INSN2 | |
3253 | if INSN2 reads that register, otherwise no delay is needed. */ | |
4c260379 RS |
3254 | mask = fpr_write_mask (insn1); |
3255 | if (mask != 0) | |
252b5132 | 3256 | { |
4c260379 | 3257 | if (!insn2 || (mask & fpr_read_mask (insn2)) != 0) |
71400594 | 3258 | return 1; |
252b5132 RH |
3259 | } |
3260 | else | |
3261 | { | |
71400594 RS |
3262 | /* Read-after-write dependencies on the control registers |
3263 | require a two-instruction gap. */ | |
3264 | if ((pinfo1 & INSN_WRITE_COND_CODE) | |
3265 | && (pinfo2 & INSN_READ_COND_CODE)) | |
3266 | return 2; | |
3267 | ||
3268 | /* We don't know exactly what INSN1 does. If INSN2 is | |
3269 | also a coprocessor instruction, assume there must be | |
3270 | a one instruction gap. */ | |
3271 | if (pinfo2 & INSN_COP) | |
3272 | return 1; | |
252b5132 RH |
3273 | } |
3274 | } | |
6b76fefe | 3275 | |
71400594 RS |
3276 | /* Check for read-after-write dependencies on the coprocessor |
3277 | control registers in cases where INSN1 does not need a general | |
3278 | coprocessor delay. This means that INSN1 is a floating point | |
3279 | comparison instruction. */ | |
3280 | /* Itbl support may require additional care here. */ | |
3281 | else if (!cop_interlocks | |
3282 | && (pinfo1 & INSN_WRITE_COND_CODE) | |
3283 | && (pinfo2 & INSN_READ_COND_CODE)) | |
3284 | return 1; | |
3285 | } | |
6b76fefe | 3286 | |
4c260379 | 3287 | #undef INSN2_USES_GPR |
6b76fefe | 3288 | |
71400594 RS |
3289 | return 0; |
3290 | } | |
6b76fefe | 3291 | |
7d8e00cf RS |
3292 | /* Return the number of nops that would be needed to work around the |
3293 | VR4130 mflo/mfhi errata if instruction INSN immediately followed | |
932d1a1b RS |
3294 | the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards |
3295 | that are contained within the first IGNORE instructions of HIST. */ | |
7d8e00cf RS |
3296 | |
3297 | static int | |
932d1a1b | 3298 | nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist, |
7d8e00cf RS |
3299 | const struct mips_cl_insn *insn) |
3300 | { | |
4c260379 RS |
3301 | int i, j; |
3302 | unsigned int mask; | |
7d8e00cf RS |
3303 | |
3304 | /* Check if the instruction writes to HI or LO. MTHI and MTLO | |
3305 | are not affected by the errata. */ | |
3306 | if (insn != 0 | |
3307 | && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 | |
3308 | || strcmp (insn->insn_mo->name, "mtlo") == 0 | |
3309 | || strcmp (insn->insn_mo->name, "mthi") == 0)) | |
3310 | return 0; | |
3311 | ||
3312 | /* Search for the first MFLO or MFHI. */ | |
3313 | for (i = 0; i < MAX_VR4130_NOPS; i++) | |
91d6fa6a | 3314 | if (MF_HILO_INSN (hist[i].insn_mo->pinfo)) |
7d8e00cf RS |
3315 | { |
3316 | /* Extract the destination register. */ | |
4c260379 | 3317 | mask = gpr_write_mask (&hist[i]); |
7d8e00cf RS |
3318 | |
3319 | /* No nops are needed if INSN reads that register. */ | |
4c260379 | 3320 | if (insn != NULL && (gpr_read_mask (insn) & mask) != 0) |
7d8e00cf RS |
3321 | return 0; |
3322 | ||
3323 | /* ...or if any of the intervening instructions do. */ | |
3324 | for (j = 0; j < i; j++) | |
4c260379 | 3325 | if (gpr_read_mask (&hist[j]) & mask) |
7d8e00cf RS |
3326 | return 0; |
3327 | ||
932d1a1b RS |
3328 | if (i >= ignore) |
3329 | return MAX_VR4130_NOPS - i; | |
7d8e00cf RS |
3330 | } |
3331 | return 0; | |
3332 | } | |
3333 | ||
15be625d CM |
3334 | #define BASE_REG_EQ(INSN1, INSN2) \ |
3335 | ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \ | |
3336 | == (((INSN2) >> OP_SH_RS) & OP_MASK_RS)) | |
3337 | ||
3338 | /* Return the minimum alignment for this store instruction. */ | |
3339 | ||
3340 | static int | |
3341 | fix_24k_align_to (const struct mips_opcode *mo) | |
3342 | { | |
3343 | if (strcmp (mo->name, "sh") == 0) | |
3344 | return 2; | |
3345 | ||
3346 | if (strcmp (mo->name, "swc1") == 0 | |
3347 | || strcmp (mo->name, "swc2") == 0 | |
3348 | || strcmp (mo->name, "sw") == 0 | |
3349 | || strcmp (mo->name, "sc") == 0 | |
3350 | || strcmp (mo->name, "s.s") == 0) | |
3351 | return 4; | |
3352 | ||
3353 | if (strcmp (mo->name, "sdc1") == 0 | |
3354 | || strcmp (mo->name, "sdc2") == 0 | |
3355 | || strcmp (mo->name, "s.d") == 0) | |
3356 | return 8; | |
3357 | ||
3358 | /* sb, swl, swr */ | |
3359 | return 1; | |
3360 | } | |
3361 | ||
3362 | struct fix_24k_store_info | |
3363 | { | |
3364 | /* Immediate offset, if any, for this store instruction. */ | |
3365 | short off; | |
3366 | /* Alignment required by this store instruction. */ | |
3367 | int align_to; | |
3368 | /* True for register offsets. */ | |
3369 | int register_offset; | |
3370 | }; | |
3371 | ||
3372 | /* Comparison function used by qsort. */ | |
3373 | ||
3374 | static int | |
3375 | fix_24k_sort (const void *a, const void *b) | |
3376 | { | |
3377 | const struct fix_24k_store_info *pos1 = a; | |
3378 | const struct fix_24k_store_info *pos2 = b; | |
3379 | ||
3380 | return (pos1->off - pos2->off); | |
3381 | } | |
3382 | ||
3383 | /* INSN is a store instruction. Try to record the store information | |
3384 | in STINFO. Return false if the information isn't known. */ | |
3385 | ||
3386 | static bfd_boolean | |
3387 | fix_24k_record_store_info (struct fix_24k_store_info *stinfo, | |
ab9794cf | 3388 | const struct mips_cl_insn *insn) |
15be625d CM |
3389 | { |
3390 | /* The instruction must have a known offset. */ | |
3391 | if (!insn->complete_p || !strstr (insn->insn_mo->args, "o(")) | |
3392 | return FALSE; | |
3393 | ||
3394 | stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE; | |
3395 | stinfo->align_to = fix_24k_align_to (insn->insn_mo); | |
3396 | return TRUE; | |
3397 | } | |
3398 | ||
932d1a1b RS |
3399 | /* Return the number of nops that would be needed to work around the 24k |
3400 | "lost data on stores during refill" errata if instruction INSN | |
3401 | immediately followed the 2 instructions described by HIST. | |
3402 | Ignore hazards that are contained within the first IGNORE | |
3403 | instructions of HIST. | |
3404 | ||
3405 | Problem: The FSB (fetch store buffer) acts as an intermediate buffer | |
3406 | for the data cache refills and store data. The following describes | |
3407 | the scenario where the store data could be lost. | |
3408 | ||
3409 | * A data cache miss, due to either a load or a store, causing fill | |
3410 | data to be supplied by the memory subsystem | |
3411 | * The first three doublewords of fill data are returned and written | |
3412 | into the cache | |
3413 | * A sequence of four stores occurs in consecutive cycles around the | |
3414 | final doubleword of the fill: | |
3415 | * Store A | |
3416 | * Store B | |
3417 | * Store C | |
3418 | * Zero, One or more instructions | |
3419 | * Store D | |
3420 | ||
3421 | The four stores A-D must be to different doublewords of the line that | |
3422 | is being filled. The fourth instruction in the sequence above permits | |
3423 | the fill of the final doubleword to be transferred from the FSB into | |
3424 | the cache. In the sequence above, the stores may be either integer | |
3425 | (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2, | |
3426 | swxc1, sdxc1, suxc1) stores, as long as the four stores are to | |
3427 | different doublewords on the line. If the floating point unit is | |
3428 | running in 1:2 mode, it is not possible to create the sequence above | |
3429 | using only floating point store instructions. | |
15be625d CM |
3430 | |
3431 | In this case, the cache line being filled is incorrectly marked | |
3432 | invalid, thereby losing the data from any store to the line that | |
3433 | occurs between the original miss and the completion of the five | |
3434 | cycle sequence shown above. | |
3435 | ||
932d1a1b | 3436 | The workarounds are: |
15be625d | 3437 | |
932d1a1b RS |
3438 | * Run the data cache in write-through mode. |
3439 | * Insert a non-store instruction between | |
3440 | Store A and Store B or Store B and Store C. */ | |
15be625d CM |
3441 | |
3442 | static int | |
932d1a1b | 3443 | nops_for_24k (int ignore, const struct mips_cl_insn *hist, |
15be625d CM |
3444 | const struct mips_cl_insn *insn) |
3445 | { | |
3446 | struct fix_24k_store_info pos[3]; | |
3447 | int align, i, base_offset; | |
3448 | ||
932d1a1b RS |
3449 | if (ignore >= 2) |
3450 | return 0; | |
3451 | ||
ab9794cf RS |
3452 | /* If the previous instruction wasn't a store, there's nothing to |
3453 | worry about. */ | |
15be625d CM |
3454 | if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) |
3455 | return 0; | |
3456 | ||
ab9794cf RS |
3457 | /* If the instructions after the previous one are unknown, we have |
3458 | to assume the worst. */ | |
3459 | if (!insn) | |
15be625d CM |
3460 | return 1; |
3461 | ||
ab9794cf RS |
3462 | /* Check whether we are dealing with three consecutive stores. */ |
3463 | if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0 | |
3464 | || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) | |
15be625d CM |
3465 | return 0; |
3466 | ||
3467 | /* If we don't know the relationship between the store addresses, | |
3468 | assume the worst. */ | |
ab9794cf | 3469 | if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode) |
15be625d CM |
3470 | || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode)) |
3471 | return 1; | |
3472 | ||
3473 | if (!fix_24k_record_store_info (&pos[0], insn) | |
3474 | || !fix_24k_record_store_info (&pos[1], &hist[0]) | |
3475 | || !fix_24k_record_store_info (&pos[2], &hist[1])) | |
3476 | return 1; | |
3477 | ||
3478 | qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort); | |
3479 | ||
3480 | /* Pick a value of ALIGN and X such that all offsets are adjusted by | |
3481 | X bytes and such that the base register + X is known to be aligned | |
3482 | to align bytes. */ | |
3483 | ||
3484 | if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP) | |
3485 | align = 8; | |
3486 | else | |
3487 | { | |
3488 | align = pos[0].align_to; | |
3489 | base_offset = pos[0].off; | |
3490 | for (i = 1; i < 3; i++) | |
3491 | if (align < pos[i].align_to) | |
3492 | { | |
3493 | align = pos[i].align_to; | |
3494 | base_offset = pos[i].off; | |
3495 | } | |
3496 | for (i = 0; i < 3; i++) | |
3497 | pos[i].off -= base_offset; | |
3498 | } | |
3499 | ||
3500 | pos[0].off &= ~align + 1; | |
3501 | pos[1].off &= ~align + 1; | |
3502 | pos[2].off &= ~align + 1; | |
3503 | ||
3504 | /* If any two stores write to the same chunk, they also write to the | |
3505 | same doubleword. The offsets are still sorted at this point. */ | |
3506 | if (pos[0].off == pos[1].off || pos[1].off == pos[2].off) | |
3507 | return 0; | |
3508 | ||
3509 | /* A range of at least 9 bytes is needed for the stores to be in | |
3510 | non-overlapping doublewords. */ | |
3511 | if (pos[2].off - pos[0].off <= 8) | |
3512 | return 0; | |
3513 | ||
3514 | if (pos[2].off - pos[1].off >= 24 | |
3515 | || pos[1].off - pos[0].off >= 24 | |
3516 | || pos[2].off - pos[0].off >= 32) | |
3517 | return 0; | |
3518 | ||
3519 | return 1; | |
3520 | } | |
3521 | ||
71400594 | 3522 | /* Return the number of nops that would be needed if instruction INSN |
91d6fa6a | 3523 | immediately followed the MAX_NOPS instructions given by HIST, |
932d1a1b RS |
3524 | where HIST[0] is the most recent instruction. Ignore hazards |
3525 | between INSN and the first IGNORE instructions in HIST. | |
3526 | ||
3527 | If INSN is null, return the worse-case number of nops for any | |
3528 | instruction. */ | |
bdaaa2e1 | 3529 | |
71400594 | 3530 | static int |
932d1a1b | 3531 | nops_for_insn (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
3532 | const struct mips_cl_insn *insn) |
3533 | { | |
3534 | int i, nops, tmp_nops; | |
bdaaa2e1 | 3535 | |
71400594 | 3536 | nops = 0; |
932d1a1b | 3537 | for (i = ignore; i < MAX_DELAY_NOPS; i++) |
65b02341 | 3538 | { |
91d6fa6a | 3539 | tmp_nops = insns_between (hist + i, insn) - i; |
65b02341 RS |
3540 | if (tmp_nops > nops) |
3541 | nops = tmp_nops; | |
3542 | } | |
7d8e00cf | 3543 | |
df58fc94 | 3544 | if (mips_fix_vr4130 && !mips_opts.micromips) |
7d8e00cf | 3545 | { |
932d1a1b | 3546 | tmp_nops = nops_for_vr4130 (ignore, hist, insn); |
7d8e00cf RS |
3547 | if (tmp_nops > nops) |
3548 | nops = tmp_nops; | |
3549 | } | |
3550 | ||
df58fc94 | 3551 | if (mips_fix_24k && !mips_opts.micromips) |
15be625d | 3552 | { |
932d1a1b | 3553 | tmp_nops = nops_for_24k (ignore, hist, insn); |
15be625d CM |
3554 | if (tmp_nops > nops) |
3555 | nops = tmp_nops; | |
3556 | } | |
3557 | ||
71400594 RS |
3558 | return nops; |
3559 | } | |
252b5132 | 3560 | |
71400594 | 3561 | /* The variable arguments provide NUM_INSNS extra instructions that |
91d6fa6a | 3562 | might be added to HIST. Return the largest number of nops that |
932d1a1b RS |
3563 | would be needed after the extended sequence, ignoring hazards |
3564 | in the first IGNORE instructions. */ | |
252b5132 | 3565 | |
71400594 | 3566 | static int |
932d1a1b RS |
3567 | nops_for_sequence (int num_insns, int ignore, |
3568 | const struct mips_cl_insn *hist, ...) | |
71400594 RS |
3569 | { |
3570 | va_list args; | |
3571 | struct mips_cl_insn buffer[MAX_NOPS]; | |
3572 | struct mips_cl_insn *cursor; | |
3573 | int nops; | |
3574 | ||
91d6fa6a | 3575 | va_start (args, hist); |
71400594 | 3576 | cursor = buffer + num_insns; |
91d6fa6a | 3577 | memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor)); |
71400594 RS |
3578 | while (cursor > buffer) |
3579 | *--cursor = *va_arg (args, const struct mips_cl_insn *); | |
3580 | ||
932d1a1b | 3581 | nops = nops_for_insn (ignore, buffer, NULL); |
71400594 RS |
3582 | va_end (args); |
3583 | return nops; | |
3584 | } | |
252b5132 | 3585 | |
71400594 RS |
3586 | /* Like nops_for_insn, but if INSN is a branch, take into account the |
3587 | worst-case delay for the branch target. */ | |
252b5132 | 3588 | |
71400594 | 3589 | static int |
932d1a1b | 3590 | nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
3591 | const struct mips_cl_insn *insn) |
3592 | { | |
3593 | int nops, tmp_nops; | |
60b63b72 | 3594 | |
932d1a1b | 3595 | nops = nops_for_insn (ignore, hist, insn); |
11625dd8 | 3596 | if (delayed_branch_p (insn)) |
71400594 | 3597 | { |
932d1a1b | 3598 | tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0, |
14fe068b | 3599 | hist, insn, get_delay_slot_nop (insn)); |
71400594 RS |
3600 | if (tmp_nops > nops) |
3601 | nops = tmp_nops; | |
3602 | } | |
11625dd8 | 3603 | else if (compact_branch_p (insn)) |
71400594 | 3604 | { |
932d1a1b | 3605 | tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn); |
71400594 RS |
3606 | if (tmp_nops > nops) |
3607 | nops = tmp_nops; | |
3608 | } | |
3609 | return nops; | |
3610 | } | |
3611 | ||
c67a084a NC |
3612 | /* Fix NOP issue: Replace nops by "or at,at,zero". */ |
3613 | ||
3614 | static void | |
3615 | fix_loongson2f_nop (struct mips_cl_insn * ip) | |
3616 | { | |
df58fc94 | 3617 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
3618 | if (strcmp (ip->insn_mo->name, "nop") == 0) |
3619 | ip->insn_opcode = LOONGSON2F_NOP_INSN; | |
3620 | } | |
3621 | ||
3622 | /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region | |
3623 | jr target pc &= 'hffff_ffff_cfff_ffff. */ | |
3624 | ||
3625 | static void | |
3626 | fix_loongson2f_jump (struct mips_cl_insn * ip) | |
3627 | { | |
df58fc94 | 3628 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
3629 | if (strcmp (ip->insn_mo->name, "j") == 0 |
3630 | || strcmp (ip->insn_mo->name, "jr") == 0 | |
3631 | || strcmp (ip->insn_mo->name, "jalr") == 0) | |
3632 | { | |
3633 | int sreg; | |
3634 | expressionS ep; | |
3635 | ||
3636 | if (! mips_opts.at) | |
3637 | return; | |
3638 | ||
df58fc94 | 3639 | sreg = EXTRACT_OPERAND (0, RS, *ip); |
c67a084a NC |
3640 | if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG) |
3641 | return; | |
3642 | ||
3643 | ep.X_op = O_constant; | |
3644 | ep.X_add_number = 0xcfff0000; | |
3645 | macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16); | |
3646 | ep.X_add_number = 0xffff; | |
3647 | macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16); | |
3648 | macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG); | |
3649 | } | |
3650 | } | |
3651 | ||
3652 | static void | |
3653 | fix_loongson2f (struct mips_cl_insn * ip) | |
3654 | { | |
3655 | if (mips_fix_loongson2f_nop) | |
3656 | fix_loongson2f_nop (ip); | |
3657 | ||
3658 | if (mips_fix_loongson2f_jump) | |
3659 | fix_loongson2f_jump (ip); | |
3660 | } | |
3661 | ||
a4e06468 RS |
3662 | /* IP is a branch that has a delay slot, and we need to fill it |
3663 | automatically. Return true if we can do that by swapping IP | |
3664 | with the previous instruction. */ | |
3665 | ||
3666 | static bfd_boolean | |
3667 | can_swap_branch_p (struct mips_cl_insn *ip) | |
3668 | { | |
df58fc94 | 3669 | unsigned long pinfo, pinfo2, prev_pinfo; |
a4e06468 RS |
3670 | unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write; |
3671 | ||
df58fc94 RS |
3672 | /* For microMIPS, disable reordering. */ |
3673 | if (mips_opts.micromips) | |
3674 | return FALSE; | |
3675 | ||
a4e06468 RS |
3676 | /* -O2 and above is required for this optimization. */ |
3677 | if (mips_optimize < 2) | |
3678 | return FALSE; | |
3679 | ||
3680 | /* If we have seen .set volatile or .set nomove, don't optimize. */ | |
3681 | if (mips_opts.nomove) | |
3682 | return FALSE; | |
3683 | ||
3684 | /* We can't swap if the previous instruction's position is fixed. */ | |
3685 | if (history[0].fixed_p) | |
3686 | return FALSE; | |
3687 | ||
3688 | /* If the previous previous insn was in a .set noreorder, we can't | |
3689 | swap. Actually, the MIPS assembler will swap in this situation. | |
3690 | However, gcc configured -with-gnu-as will generate code like | |
3691 | ||
3692 | .set noreorder | |
3693 | lw $4,XXX | |
3694 | .set reorder | |
3695 | INSN | |
3696 | bne $4,$0,foo | |
3697 | ||
3698 | in which we can not swap the bne and INSN. If gcc is not configured | |
3699 | -with-gnu-as, it does not output the .set pseudo-ops. */ | |
3700 | if (history[1].noreorder_p) | |
3701 | return FALSE; | |
3702 | ||
3703 | /* If the previous instruction had a fixup in mips16 mode, we can not | |
3704 | swap. This normally means that the previous instruction was a 4 | |
3705 | byte branch anyhow. */ | |
3706 | if (mips_opts.mips16 && history[0].fixp[0]) | |
3707 | return FALSE; | |
3708 | ||
3709 | /* If the branch is itself the target of a branch, we can not swap. | |
3710 | We cheat on this; all we check for is whether there is a label on | |
3711 | this instruction. If there are any branches to anything other than | |
3712 | a label, users must use .set noreorder. */ | |
3713 | if (seg_info (now_seg)->label_list) | |
3714 | return FALSE; | |
3715 | ||
3716 | /* If the previous instruction is in a variant frag other than this | |
2309ddf2 MR |
3717 | branch's one, we cannot do the swap. This does not apply to |
3718 | MIPS16/microMIPS code, which uses variant frags for different | |
3719 | purposes. */ | |
df58fc94 | 3720 | if (!HAVE_CODE_COMPRESSION |
a4e06468 RS |
3721 | && history[0].frag |
3722 | && history[0].frag->fr_type == rs_machine_dependent) | |
3723 | return FALSE; | |
3724 | ||
bcd530a7 RS |
3725 | /* We do not swap with instructions that cannot architecturally |
3726 | be placed in a branch delay slot, such as SYNC or ERET. We | |
3727 | also refrain from swapping with a trap instruction, since it | |
3728 | complicates trap handlers to have the trap instruction be in | |
3729 | a delay slot. */ | |
a4e06468 | 3730 | prev_pinfo = history[0].insn_mo->pinfo; |
bcd530a7 | 3731 | if (prev_pinfo & INSN_NO_DELAY_SLOT) |
a4e06468 RS |
3732 | return FALSE; |
3733 | ||
3734 | /* Check for conflicts between the branch and the instructions | |
3735 | before the candidate delay slot. */ | |
3736 | if (nops_for_insn (0, history + 1, ip) > 0) | |
3737 | return FALSE; | |
3738 | ||
3739 | /* Check for conflicts between the swapped sequence and the | |
3740 | target of the branch. */ | |
3741 | if (nops_for_sequence (2, 0, history + 1, ip, history) > 0) | |
3742 | return FALSE; | |
3743 | ||
3744 | /* If the branch reads a register that the previous | |
3745 | instruction sets, we can not swap. */ | |
3746 | gpr_read = gpr_read_mask (ip); | |
3747 | prev_gpr_write = gpr_write_mask (&history[0]); | |
3748 | if (gpr_read & prev_gpr_write) | |
3749 | return FALSE; | |
3750 | ||
3751 | /* If the branch writes a register that the previous | |
3752 | instruction sets, we can not swap. */ | |
3753 | gpr_write = gpr_write_mask (ip); | |
3754 | if (gpr_write & prev_gpr_write) | |
3755 | return FALSE; | |
3756 | ||
3757 | /* If the branch writes a register that the previous | |
3758 | instruction reads, we can not swap. */ | |
3759 | prev_gpr_read = gpr_read_mask (&history[0]); | |
3760 | if (gpr_write & prev_gpr_read) | |
3761 | return FALSE; | |
3762 | ||
3763 | /* If one instruction sets a condition code and the | |
3764 | other one uses a condition code, we can not swap. */ | |
3765 | pinfo = ip->insn_mo->pinfo; | |
3766 | if ((pinfo & INSN_READ_COND_CODE) | |
3767 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
3768 | return FALSE; | |
3769 | if ((pinfo & INSN_WRITE_COND_CODE) | |
3770 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
3771 | return FALSE; | |
3772 | ||
3773 | /* If the previous instruction uses the PC, we can not swap. */ | |
3774 | if (mips_opts.mips16 && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
3775 | return FALSE; | |
3776 | ||
df58fc94 RS |
3777 | /* If the previous instruction has an incorrect size for a fixed |
3778 | branch delay slot in microMIPS mode, we cannot swap. */ | |
2309ddf2 MR |
3779 | pinfo2 = ip->insn_mo->pinfo2; |
3780 | if (mips_opts.micromips | |
3781 | && (pinfo2 & INSN2_BRANCH_DELAY_16BIT) | |
3782 | && insn_length (history) != 2) | |
3783 | return FALSE; | |
3784 | if (mips_opts.micromips | |
3785 | && (pinfo2 & INSN2_BRANCH_DELAY_32BIT) | |
3786 | && insn_length (history) != 4) | |
3787 | return FALSE; | |
3788 | ||
a4e06468 RS |
3789 | return TRUE; |
3790 | } | |
3791 | ||
3792 | /* Decide how we should add IP to the instruction stream. */ | |
3793 | ||
3794 | static enum append_method | |
3795 | get_append_method (struct mips_cl_insn *ip) | |
3796 | { | |
3797 | unsigned long pinfo; | |
3798 | ||
3799 | /* The relaxed version of a macro sequence must be inherently | |
3800 | hazard-free. */ | |
3801 | if (mips_relax.sequence == 2) | |
3802 | return APPEND_ADD; | |
3803 | ||
3804 | /* We must not dabble with instructions in a ".set norerorder" block. */ | |
3805 | if (mips_opts.noreorder) | |
3806 | return APPEND_ADD; | |
3807 | ||
3808 | /* Otherwise, it's our responsibility to fill branch delay slots. */ | |
11625dd8 | 3809 | if (delayed_branch_p (ip)) |
a4e06468 | 3810 | { |
11625dd8 | 3811 | if (!branch_likely_p (ip) && can_swap_branch_p (ip)) |
a4e06468 RS |
3812 | return APPEND_SWAP; |
3813 | ||
11625dd8 | 3814 | pinfo = ip->insn_mo->pinfo; |
a4e06468 RS |
3815 | if (mips_opts.mips16 |
3816 | && ISA_SUPPORTS_MIPS16E | |
a4e06468 RS |
3817 | && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31))) |
3818 | return APPEND_ADD_COMPACT; | |
3819 | ||
3820 | return APPEND_ADD_WITH_NOP; | |
3821 | } | |
3822 | ||
a4e06468 RS |
3823 | return APPEND_ADD; |
3824 | } | |
3825 | ||
ceb94aa5 RS |
3826 | /* IP is a MIPS16 instruction whose opcode we have just changed. |
3827 | Point IP->insn_mo to the new opcode's definition. */ | |
3828 | ||
3829 | static void | |
3830 | find_altered_mips16_opcode (struct mips_cl_insn *ip) | |
3831 | { | |
3832 | const struct mips_opcode *mo, *end; | |
3833 | ||
3834 | end = &mips16_opcodes[bfd_mips16_num_opcodes]; | |
3835 | for (mo = ip->insn_mo; mo < end; mo++) | |
3836 | if ((ip->insn_opcode & mo->mask) == mo->match) | |
3837 | { | |
3838 | ip->insn_mo = mo; | |
3839 | return; | |
3840 | } | |
3841 | abort (); | |
3842 | } | |
3843 | ||
df58fc94 RS |
3844 | /* For microMIPS macros, we need to generate a local number label |
3845 | as the target of branches. */ | |
3846 | #define MICROMIPS_LABEL_CHAR '\037' | |
3847 | static unsigned long micromips_target_label; | |
3848 | static char micromips_target_name[32]; | |
3849 | ||
3850 | static char * | |
3851 | micromips_label_name (void) | |
3852 | { | |
3853 | char *p = micromips_target_name; | |
3854 | char symbol_name_temporary[24]; | |
3855 | unsigned long l; | |
3856 | int i; | |
3857 | ||
3858 | if (*p) | |
3859 | return p; | |
3860 | ||
3861 | i = 0; | |
3862 | l = micromips_target_label; | |
3863 | #ifdef LOCAL_LABEL_PREFIX | |
3864 | *p++ = LOCAL_LABEL_PREFIX; | |
3865 | #endif | |
3866 | *p++ = 'L'; | |
3867 | *p++ = MICROMIPS_LABEL_CHAR; | |
3868 | do | |
3869 | { | |
3870 | symbol_name_temporary[i++] = l % 10 + '0'; | |
3871 | l /= 10; | |
3872 | } | |
3873 | while (l != 0); | |
3874 | while (i > 0) | |
3875 | *p++ = symbol_name_temporary[--i]; | |
3876 | *p = '\0'; | |
3877 | ||
3878 | return micromips_target_name; | |
3879 | } | |
3880 | ||
3881 | static void | |
3882 | micromips_label_expr (expressionS *label_expr) | |
3883 | { | |
3884 | label_expr->X_op = O_symbol; | |
3885 | label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ()); | |
3886 | label_expr->X_add_number = 0; | |
3887 | } | |
3888 | ||
3889 | static void | |
3890 | micromips_label_inc (void) | |
3891 | { | |
3892 | micromips_target_label++; | |
3893 | *micromips_target_name = '\0'; | |
3894 | } | |
3895 | ||
3896 | static void | |
3897 | micromips_add_label (void) | |
3898 | { | |
3899 | symbolS *s; | |
3900 | ||
3901 | s = colon (micromips_label_name ()); | |
3902 | micromips_label_inc (); | |
3903 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) | |
3904 | if (IS_ELF) | |
3905 | S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s))); | |
3906 | #endif | |
3907 | } | |
3908 | ||
3909 | /* If assembling microMIPS code, then return the microMIPS reloc | |
3910 | corresponding to the requested one if any. Otherwise return | |
3911 | the reloc unchanged. */ | |
3912 | ||
3913 | static bfd_reloc_code_real_type | |
3914 | micromips_map_reloc (bfd_reloc_code_real_type reloc) | |
3915 | { | |
3916 | static const bfd_reloc_code_real_type relocs[][2] = | |
3917 | { | |
3918 | /* Keep sorted incrementally by the left-hand key. */ | |
3919 | { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 }, | |
3920 | { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 }, | |
3921 | { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP }, | |
3922 | { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 }, | |
3923 | { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S }, | |
3924 | { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 }, | |
3925 | { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL }, | |
3926 | { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 }, | |
3927 | { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 }, | |
3928 | { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 }, | |
3929 | { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 }, | |
3930 | { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 }, | |
3931 | { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 }, | |
3932 | { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB }, | |
3933 | { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE }, | |
3934 | { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST }, | |
3935 | { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP }, | |
3936 | { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST }, | |
3937 | { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER }, | |
3938 | { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP }, | |
3939 | { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD }, | |
3940 | { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM }, | |
3941 | { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 }, | |
3942 | { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 }, | |
3943 | { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL }, | |
3944 | { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 }, | |
3945 | { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 } | |
3946 | }; | |
3947 | bfd_reloc_code_real_type r; | |
3948 | size_t i; | |
3949 | ||
3950 | if (!mips_opts.micromips) | |
3951 | return reloc; | |
3952 | for (i = 0; i < ARRAY_SIZE (relocs); i++) | |
3953 | { | |
3954 | r = relocs[i][0]; | |
3955 | if (r > reloc) | |
3956 | return reloc; | |
3957 | if (r == reloc) | |
3958 | return relocs[i][1]; | |
3959 | } | |
3960 | return reloc; | |
3961 | } | |
3962 | ||
71400594 RS |
3963 | /* Output an instruction. IP is the instruction information. |
3964 | ADDRESS_EXPR is an operand of the instruction to be used with | |
df58fc94 RS |
3965 | RELOC_TYPE. EXPANSIONP is true if the instruction is part of |
3966 | a macro expansion. */ | |
71400594 RS |
3967 | |
3968 | static void | |
3969 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
df58fc94 | 3970 | bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp) |
71400594 | 3971 | { |
14fe068b | 3972 | unsigned long prev_pinfo2, pinfo; |
71400594 | 3973 | bfd_boolean relaxed_branch = FALSE; |
a4e06468 | 3974 | enum append_method method; |
2309ddf2 | 3975 | bfd_boolean relax32; |
71400594 | 3976 | |
2309ddf2 | 3977 | if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION) |
c67a084a NC |
3978 | fix_loongson2f (ip); |
3979 | ||
df58fc94 | 3980 | mips_mark_labels (); |
71400594 | 3981 | |
738f4d98 | 3982 | file_ase_mips16 |= mips_opts.mips16; |
df58fc94 | 3983 | file_ase_micromips |= mips_opts.micromips; |
738f4d98 | 3984 | |
df58fc94 | 3985 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
71400594 | 3986 | pinfo = ip->insn_mo->pinfo; |
df58fc94 RS |
3987 | |
3988 | if (mips_opts.micromips | |
3989 | && !expansionp | |
3990 | && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 | |
3991 | && micromips_insn_length (ip->insn_mo) != 2) | |
3992 | || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 | |
3993 | && micromips_insn_length (ip->insn_mo) != 4))) | |
3994 | as_warn (_("Wrong size instruction in a %u-bit branch delay slot"), | |
3995 | (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32); | |
71400594 | 3996 | |
15be625d CM |
3997 | if (address_expr == NULL) |
3998 | ip->complete_p = 1; | |
3999 | else if (*reloc_type <= BFD_RELOC_UNUSED | |
4000 | && address_expr->X_op == O_constant) | |
4001 | { | |
4002 | unsigned int tmp; | |
4003 | ||
4004 | ip->complete_p = 1; | |
4005 | switch (*reloc_type) | |
4006 | { | |
4007 | case BFD_RELOC_32: | |
4008 | ip->insn_opcode |= address_expr->X_add_number; | |
4009 | break; | |
4010 | ||
4011 | case BFD_RELOC_MIPS_HIGHEST: | |
4012 | tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48; | |
4013 | ip->insn_opcode |= tmp & 0xffff; | |
4014 | break; | |
4015 | ||
4016 | case BFD_RELOC_MIPS_HIGHER: | |
4017 | tmp = (address_expr->X_add_number + 0x80008000ull) >> 32; | |
4018 | ip->insn_opcode |= tmp & 0xffff; | |
4019 | break; | |
4020 | ||
4021 | case BFD_RELOC_HI16_S: | |
4022 | tmp = (address_expr->X_add_number + 0x8000) >> 16; | |
4023 | ip->insn_opcode |= tmp & 0xffff; | |
4024 | break; | |
4025 | ||
4026 | case BFD_RELOC_HI16: | |
4027 | ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; | |
4028 | break; | |
4029 | ||
4030 | case BFD_RELOC_UNUSED: | |
4031 | case BFD_RELOC_LO16: | |
4032 | case BFD_RELOC_MIPS_GOT_DISP: | |
4033 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; | |
4034 | break; | |
4035 | ||
4036 | case BFD_RELOC_MIPS_JMP: | |
df58fc94 RS |
4037 | { |
4038 | int shift; | |
4039 | ||
4040 | shift = mips_opts.micromips ? 1 : 2; | |
4041 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
4042 | as_bad (_("jump to misaligned address (0x%lx)"), | |
4043 | (unsigned long) address_expr->X_add_number); | |
4044 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
4045 | & 0x3ffffff); | |
4046 | ip->complete_p = 0; | |
4047 | } | |
15be625d CM |
4048 | break; |
4049 | ||
4050 | case BFD_RELOC_MIPS16_JMP: | |
4051 | if ((address_expr->X_add_number & 3) != 0) | |
4052 | as_bad (_("jump to misaligned address (0x%lx)"), | |
4053 | (unsigned long) address_expr->X_add_number); | |
4054 | ip->insn_opcode |= | |
4055 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
4056 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
4057 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
4058 | ip->complete_p = 0; | |
4059 | break; | |
4060 | ||
4061 | case BFD_RELOC_16_PCREL_S2: | |
df58fc94 RS |
4062 | { |
4063 | int shift; | |
4064 | ||
4065 | shift = mips_opts.micromips ? 1 : 2; | |
4066 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
4067 | as_bad (_("branch to misaligned address (0x%lx)"), | |
4068 | (unsigned long) address_expr->X_add_number); | |
4069 | if (!mips_relax_branch) | |
4070 | { | |
4071 | if ((address_expr->X_add_number + (1 << (shift + 15))) | |
4072 | & ~((1 << (shift + 16)) - 1)) | |
4073 | as_bad (_("branch address range overflow (0x%lx)"), | |
4074 | (unsigned long) address_expr->X_add_number); | |
4075 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
4076 | & 0xffff); | |
4077 | } | |
4078 | ip->complete_p = 0; | |
4079 | } | |
15be625d CM |
4080 | break; |
4081 | ||
4082 | default: | |
4083 | internalError (); | |
4084 | } | |
4085 | } | |
4086 | ||
71400594 RS |
4087 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
4088 | { | |
4089 | /* There are a lot of optimizations we could do that we don't. | |
4090 | In particular, we do not, in general, reorder instructions. | |
4091 | If you use gcc with optimization, it will reorder | |
4092 | instructions and generally do much more optimization then we | |
4093 | do here; repeating all that work in the assembler would only | |
4094 | benefit hand written assembly code, and does not seem worth | |
4095 | it. */ | |
4096 | int nops = (mips_optimize == 0 | |
932d1a1b RS |
4097 | ? nops_for_insn (0, history, NULL) |
4098 | : nops_for_insn_or_target (0, history, ip)); | |
71400594 | 4099 | if (nops > 0) |
252b5132 RH |
4100 | { |
4101 | fragS *old_frag; | |
4102 | unsigned long old_frag_offset; | |
4103 | int i; | |
252b5132 RH |
4104 | |
4105 | old_frag = frag_now; | |
4106 | old_frag_offset = frag_now_fix (); | |
4107 | ||
4108 | for (i = 0; i < nops; i++) | |
14fe068b RS |
4109 | add_fixed_insn (NOP_INSN); |
4110 | insert_into_history (0, nops, NOP_INSN); | |
252b5132 RH |
4111 | |
4112 | if (listing) | |
4113 | { | |
4114 | listing_prev_line (); | |
4115 | /* We may be at the start of a variant frag. In case we | |
4116 | are, make sure there is enough space for the frag | |
4117 | after the frags created by listing_prev_line. The | |
4118 | argument to frag_grow here must be at least as large | |
4119 | as the argument to all other calls to frag_grow in | |
4120 | this file. We don't have to worry about being in the | |
4121 | middle of a variant frag, because the variants insert | |
4122 | all needed nop instructions themselves. */ | |
4123 | frag_grow (40); | |
4124 | } | |
4125 | ||
404a8071 | 4126 | mips_move_labels (); |
252b5132 RH |
4127 | |
4128 | #ifndef NO_ECOFF_DEBUGGING | |
4129 | if (ECOFF_DEBUGGING) | |
4130 | ecoff_fix_loc (old_frag, old_frag_offset); | |
4131 | #endif | |
4132 | } | |
71400594 RS |
4133 | } |
4134 | else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) | |
4135 | { | |
932d1a1b RS |
4136 | int nops; |
4137 | ||
4138 | /* Work out how many nops in prev_nop_frag are needed by IP, | |
4139 | ignoring hazards generated by the first prev_nop_frag_since | |
4140 | instructions. */ | |
4141 | nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip); | |
9c2799c2 | 4142 | gas_assert (nops <= prev_nop_frag_holds); |
252b5132 | 4143 | |
71400594 RS |
4144 | /* Enforce NOPS as a minimum. */ |
4145 | if (nops > prev_nop_frag_required) | |
4146 | prev_nop_frag_required = nops; | |
252b5132 | 4147 | |
71400594 RS |
4148 | if (prev_nop_frag_holds == prev_nop_frag_required) |
4149 | { | |
4150 | /* Settle for the current number of nops. Update the history | |
4151 | accordingly (for the benefit of any future .set reorder code). */ | |
4152 | prev_nop_frag = NULL; | |
4153 | insert_into_history (prev_nop_frag_since, | |
4154 | prev_nop_frag_holds, NOP_INSN); | |
4155 | } | |
4156 | else | |
4157 | { | |
4158 | /* Allow this instruction to replace one of the nops that was | |
4159 | tentatively added to prev_nop_frag. */ | |
df58fc94 | 4160 | prev_nop_frag->fr_fix -= NOP_INSN_SIZE; |
71400594 RS |
4161 | prev_nop_frag_holds--; |
4162 | prev_nop_frag_since++; | |
252b5132 RH |
4163 | } |
4164 | } | |
4165 | ||
a4e06468 RS |
4166 | method = get_append_method (ip); |
4167 | ||
58e2ea4d MR |
4168 | #ifdef OBJ_ELF |
4169 | /* The value passed to dwarf2_emit_insn is the distance between | |
4170 | the beginning of the current instruction and the address that | |
e3a82c8e MR |
4171 | should be recorded in the debug tables. This is normally the |
4172 | current address. | |
4173 | ||
df58fc94 RS |
4174 | For MIPS16/microMIPS debug info we want to use ISA-encoded |
4175 | addresses, so we use -1 for an address higher by one than the | |
4176 | current one. | |
e3a82c8e MR |
4177 | |
4178 | If the instruction produced is a branch that we will swap with | |
4179 | the preceding instruction, then we add the displacement by which | |
4180 | the branch will be moved backwards. This is more appropriate | |
2309ddf2 MR |
4181 | and for MIPS16/microMIPS code also prevents a debugger from |
4182 | placing a breakpoint in the middle of the branch (and corrupting | |
4183 | code if software breakpoints are used). */ | |
df58fc94 | 4184 | dwarf2_emit_insn ((HAVE_CODE_COMPRESSION ? -1 : 0) |
e3a82c8e | 4185 | + (method == APPEND_SWAP ? insn_length (history) : 0)); |
58e2ea4d MR |
4186 | #endif |
4187 | ||
df58fc94 RS |
4188 | relax32 = (mips_relax_branch |
4189 | /* Don't try branch relaxation within .set nomacro, or within | |
4190 | .set noat if we use $at for PIC computations. If it turns | |
4191 | out that the branch was out-of-range, we'll get an error. */ | |
4192 | && !mips_opts.warn_about_macros | |
4193 | && (mips_opts.at || mips_pic == NO_PIC) | |
4194 | /* Don't relax BPOSGE32/64 as they have no complementing | |
4195 | branches. */ | |
40209cad | 4196 | && !(ip->insn_mo->membership & (INSN_DSP64 | INSN_DSP))); |
df58fc94 RS |
4197 | |
4198 | if (!HAVE_CODE_COMPRESSION | |
4199 | && address_expr | |
4200 | && relax32 | |
0b25d3e6 | 4201 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
11625dd8 | 4202 | && delayed_branch_p (ip)) |
4a6a3df4 | 4203 | { |
895921c9 | 4204 | relaxed_branch = TRUE; |
1e915849 RS |
4205 | add_relaxed_insn (ip, (relaxed_branch_length |
4206 | (NULL, NULL, | |
11625dd8 RS |
4207 | uncond_branch_p (ip) ? -1 |
4208 | : branch_likely_p (ip) ? 1 | |
1e915849 RS |
4209 | : 0)), 4, |
4210 | RELAX_BRANCH_ENCODE | |
66b3e8da | 4211 | (AT, |
11625dd8 RS |
4212 | uncond_branch_p (ip), |
4213 | branch_likely_p (ip), | |
1e915849 RS |
4214 | pinfo & INSN_WRITE_GPR_31, |
4215 | 0), | |
4216 | address_expr->X_add_symbol, | |
4217 | address_expr->X_add_number); | |
4a6a3df4 AO |
4218 | *reloc_type = BFD_RELOC_UNUSED; |
4219 | } | |
df58fc94 RS |
4220 | else if (mips_opts.micromips |
4221 | && address_expr | |
4222 | && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2) | |
4223 | || *reloc_type > BFD_RELOC_UNUSED) | |
40209cad MR |
4224 | && (delayed_branch_p (ip) || compact_branch_p (ip)) |
4225 | /* Don't try branch relaxation when users specify | |
4226 | 16-bit/32-bit instructions. */ | |
4227 | && !forced_insn_length) | |
df58fc94 RS |
4228 | { |
4229 | bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED; | |
4230 | int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0; | |
11625dd8 RS |
4231 | int uncond = uncond_branch_p (ip) ? -1 : 0; |
4232 | int compact = compact_branch_p (ip); | |
df58fc94 RS |
4233 | int al = pinfo & INSN_WRITE_GPR_31; |
4234 | int length32; | |
4235 | ||
4236 | gas_assert (address_expr != NULL); | |
4237 | gas_assert (!mips_relax.sequence); | |
4238 | ||
4239 | length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond); | |
4240 | add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4, | |
40209cad MR |
4241 | RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al, |
4242 | relax32, 0, 0), | |
df58fc94 RS |
4243 | address_expr->X_add_symbol, |
4244 | address_expr->X_add_number); | |
4245 | *reloc_type = BFD_RELOC_UNUSED; | |
4246 | } | |
4247 | else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
4248 | { |
4249 | /* We need to set up a variant frag. */ | |
df58fc94 | 4250 | gas_assert (address_expr != NULL); |
1e915849 RS |
4251 | add_relaxed_insn (ip, 4, 0, |
4252 | RELAX_MIPS16_ENCODE | |
4253 | (*reloc_type - BFD_RELOC_UNUSED, | |
df58fc94 | 4254 | forced_insn_length == 2, forced_insn_length == 4, |
11625dd8 | 4255 | delayed_branch_p (&history[0]), |
1e915849 RS |
4256 | history[0].mips16_absolute_jump_p), |
4257 | make_expr_symbol (address_expr), 0); | |
252b5132 | 4258 | } |
252b5132 RH |
4259 | else if (mips_opts.mips16 |
4260 | && ! ip->use_extend | |
f6688943 | 4261 | && *reloc_type != BFD_RELOC_MIPS16_JMP) |
9497f5ac | 4262 | { |
11625dd8 | 4263 | if (!delayed_branch_p (ip)) |
b8ee1a6e DU |
4264 | /* Make sure there is enough room to swap this instruction with |
4265 | a following jump instruction. */ | |
4266 | frag_grow (6); | |
1e915849 | 4267 | add_fixed_insn (ip); |
252b5132 RH |
4268 | } |
4269 | else | |
4270 | { | |
4271 | if (mips_opts.mips16 | |
4272 | && mips_opts.noreorder | |
11625dd8 | 4273 | && delayed_branch_p (&history[0])) |
252b5132 RH |
4274 | as_warn (_("extended instruction in delay slot")); |
4275 | ||
4d7206a2 RS |
4276 | if (mips_relax.sequence) |
4277 | { | |
4278 | /* If we've reached the end of this frag, turn it into a variant | |
4279 | frag and record the information for the instructions we've | |
4280 | written so far. */ | |
4281 | if (frag_room () < 4) | |
4282 | relax_close_frag (); | |
df58fc94 | 4283 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip); |
4d7206a2 RS |
4284 | } |
4285 | ||
584892a6 | 4286 | if (mips_relax.sequence != 2) |
df58fc94 RS |
4287 | { |
4288 | if (mips_macro_warning.first_insn_sizes[0] == 0) | |
4289 | mips_macro_warning.first_insn_sizes[0] = insn_length (ip); | |
4290 | mips_macro_warning.sizes[0] += insn_length (ip); | |
4291 | mips_macro_warning.insns[0]++; | |
4292 | } | |
584892a6 | 4293 | if (mips_relax.sequence != 1) |
df58fc94 RS |
4294 | { |
4295 | if (mips_macro_warning.first_insn_sizes[1] == 0) | |
4296 | mips_macro_warning.first_insn_sizes[1] = insn_length (ip); | |
4297 | mips_macro_warning.sizes[1] += insn_length (ip); | |
4298 | mips_macro_warning.insns[1]++; | |
4299 | } | |
584892a6 | 4300 | |
1e915849 RS |
4301 | if (mips_opts.mips16) |
4302 | { | |
4303 | ip->fixed_p = 1; | |
4304 | ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); | |
4305 | } | |
4306 | add_fixed_insn (ip); | |
252b5132 RH |
4307 | } |
4308 | ||
9fe77896 | 4309 | if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 4310 | { |
df58fc94 | 4311 | bfd_reloc_code_real_type final_type[3]; |
2309ddf2 | 4312 | reloc_howto_type *howto0; |
9fe77896 RS |
4313 | reloc_howto_type *howto; |
4314 | int i; | |
34ce925e | 4315 | |
df58fc94 RS |
4316 | /* Perform any necessary conversion to microMIPS relocations |
4317 | and find out how many relocations there actually are. */ | |
4318 | for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++) | |
4319 | final_type[i] = micromips_map_reloc (reloc_type[i]); | |
4320 | ||
9fe77896 RS |
4321 | /* In a compound relocation, it is the final (outermost) |
4322 | operator that determines the relocated field. */ | |
2309ddf2 MR |
4323 | howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]); |
4324 | ||
9fe77896 RS |
4325 | if (howto == NULL) |
4326 | { | |
4327 | /* To reproduce this failure try assembling gas/testsuites/ | |
4328 | gas/mips/mips16-intermix.s with a mips-ecoff targeted | |
4329 | assembler. */ | |
df58fc94 RS |
4330 | as_bad (_("Unsupported MIPS relocation number %d"), |
4331 | final_type[i - 1]); | |
9fe77896 RS |
4332 | howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16); |
4333 | } | |
2309ddf2 MR |
4334 | |
4335 | if (i > 1) | |
4336 | howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]); | |
9fe77896 RS |
4337 | ip->fixp[0] = fix_new_exp (ip->frag, ip->where, |
4338 | bfd_get_reloc_size (howto), | |
4339 | address_expr, | |
2309ddf2 MR |
4340 | howto0 && howto0->pc_relative, |
4341 | final_type[0]); | |
9fe77896 RS |
4342 | |
4343 | /* Tag symbols that have a R_MIPS16_26 relocation against them. */ | |
2309ddf2 | 4344 | if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy) |
9fe77896 RS |
4345 | *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1; |
4346 | ||
4347 | /* These relocations can have an addend that won't fit in | |
4348 | 4 octets for 64bit assembly. */ | |
4349 | if (HAVE_64BIT_GPRS | |
4350 | && ! howto->partial_inplace | |
4351 | && (reloc_type[0] == BFD_RELOC_16 | |
4352 | || reloc_type[0] == BFD_RELOC_32 | |
4353 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
4354 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
4355 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
4356 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
4357 | || reloc_type[0] == BFD_RELOC_64 | |
4358 | || reloc_type[0] == BFD_RELOC_CTOR | |
4359 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
4360 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
4361 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
4362 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
4363 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
4364 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT | |
4365 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
4366 | || hi16_reloc_p (reloc_type[0]) | |
4367 | || lo16_reloc_p (reloc_type[0]))) | |
4368 | ip->fixp[0]->fx_no_overflow = 1; | |
4369 | ||
4370 | if (mips_relax.sequence) | |
4371 | { | |
4372 | if (mips_relax.first_fixup == 0) | |
4373 | mips_relax.first_fixup = ip->fixp[0]; | |
4374 | } | |
4375 | else if (reloc_needs_lo_p (*reloc_type)) | |
4376 | { | |
4377 | struct mips_hi_fixup *hi_fixup; | |
4378 | ||
4379 | /* Reuse the last entry if it already has a matching %lo. */ | |
4380 | hi_fixup = mips_hi_fixup_list; | |
4381 | if (hi_fixup == 0 | |
4382 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
4d7206a2 | 4383 | { |
9fe77896 RS |
4384 | hi_fixup = ((struct mips_hi_fixup *) |
4385 | xmalloc (sizeof (struct mips_hi_fixup))); | |
4386 | hi_fixup->next = mips_hi_fixup_list; | |
4387 | mips_hi_fixup_list = hi_fixup; | |
4d7206a2 | 4388 | } |
9fe77896 RS |
4389 | hi_fixup->fixp = ip->fixp[0]; |
4390 | hi_fixup->seg = now_seg; | |
4391 | } | |
252b5132 | 4392 | |
9fe77896 RS |
4393 | /* Add fixups for the second and third relocations, if given. |
4394 | Note that the ABI allows the second relocation to be | |
4395 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
4396 | moment we only use RSS_UNDEF, but we could add support | |
4397 | for the others if it ever becomes necessary. */ | |
4398 | for (i = 1; i < 3; i++) | |
4399 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
4400 | { | |
4401 | ip->fixp[i] = fix_new (ip->frag, ip->where, | |
4402 | ip->fixp[0]->fx_size, NULL, 0, | |
df58fc94 | 4403 | FALSE, final_type[i]); |
f6688943 | 4404 | |
9fe77896 RS |
4405 | /* Use fx_tcbit to mark compound relocs. */ |
4406 | ip->fixp[0]->fx_tcbit = 1; | |
4407 | ip->fixp[i]->fx_tcbit = 1; | |
4408 | } | |
252b5132 | 4409 | } |
1e915849 | 4410 | install_insn (ip); |
252b5132 RH |
4411 | |
4412 | /* Update the register mask information. */ | |
4c260379 RS |
4413 | mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip); |
4414 | mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip); | |
252b5132 | 4415 | |
a4e06468 | 4416 | switch (method) |
252b5132 | 4417 | { |
a4e06468 RS |
4418 | case APPEND_ADD: |
4419 | insert_into_history (0, 1, ip); | |
4420 | break; | |
4421 | ||
4422 | case APPEND_ADD_WITH_NOP: | |
14fe068b RS |
4423 | { |
4424 | struct mips_cl_insn *nop; | |
4425 | ||
4426 | insert_into_history (0, 1, ip); | |
4427 | nop = get_delay_slot_nop (ip); | |
4428 | add_fixed_insn (nop); | |
4429 | insert_into_history (0, 1, nop); | |
4430 | if (mips_relax.sequence) | |
4431 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop); | |
4432 | } | |
a4e06468 RS |
4433 | break; |
4434 | ||
4435 | case APPEND_ADD_COMPACT: | |
4436 | /* Convert MIPS16 jr/jalr into a "compact" jump. */ | |
4437 | gas_assert (mips_opts.mips16); | |
4438 | ip->insn_opcode |= 0x0080; | |
4439 | find_altered_mips16_opcode (ip); | |
4440 | install_insn (ip); | |
4441 | insert_into_history (0, 1, ip); | |
4442 | break; | |
4443 | ||
4444 | case APPEND_SWAP: | |
4445 | { | |
4446 | struct mips_cl_insn delay = history[0]; | |
4447 | if (mips_opts.mips16) | |
4448 | { | |
4449 | know (delay.frag == ip->frag); | |
4450 | move_insn (ip, delay.frag, delay.where); | |
4451 | move_insn (&delay, ip->frag, ip->where + insn_length (ip)); | |
4452 | } | |
df58fc94 RS |
4453 | else if (mips_opts.micromips) |
4454 | { | |
4455 | /* We don't reorder for micromips. */ | |
4456 | abort (); | |
4457 | } | |
a4e06468 RS |
4458 | else if (relaxed_branch) |
4459 | { | |
4460 | /* Add the delay slot instruction to the end of the | |
4461 | current frag and shrink the fixed part of the | |
4462 | original frag. If the branch occupies the tail of | |
4463 | the latter, move it backwards to cover the gap. */ | |
4464 | delay.frag->fr_fix -= 4; | |
4465 | if (delay.frag == ip->frag) | |
4466 | move_insn (ip, ip->frag, ip->where - 4); | |
4467 | add_fixed_insn (&delay); | |
4468 | } | |
4469 | else | |
4470 | { | |
4471 | move_insn (&delay, ip->frag, ip->where); | |
4472 | move_insn (ip, history[0].frag, history[0].where); | |
4473 | } | |
4474 | history[0] = *ip; | |
4475 | delay.fixed_p = 1; | |
4476 | insert_into_history (0, 1, &delay); | |
4477 | } | |
4478 | break; | |
252b5132 RH |
4479 | } |
4480 | ||
13408f1e | 4481 | /* If we have just completed an unconditional branch, clear the history. */ |
11625dd8 RS |
4482 | if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1])) |
4483 | || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0]))) | |
13408f1e RS |
4484 | mips_no_prev_insn (); |
4485 | ||
df58fc94 RS |
4486 | /* We need to emit a label at the end of branch-likely macros. */ |
4487 | if (emit_branch_likely_macro) | |
4488 | { | |
4489 | emit_branch_likely_macro = FALSE; | |
4490 | micromips_add_label (); | |
4491 | } | |
4492 | ||
252b5132 RH |
4493 | /* We just output an insn, so the next one doesn't have a label. */ |
4494 | mips_clear_insn_labels (); | |
252b5132 RH |
4495 | } |
4496 | ||
7d10b47d | 4497 | /* Forget that there was any previous instruction or label. */ |
252b5132 RH |
4498 | |
4499 | static void | |
7d10b47d | 4500 | mips_no_prev_insn (void) |
252b5132 | 4501 | { |
7d10b47d RS |
4502 | prev_nop_frag = NULL; |
4503 | insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); | |
252b5132 RH |
4504 | mips_clear_insn_labels (); |
4505 | } | |
4506 | ||
7d10b47d RS |
4507 | /* This function must be called before we emit something other than |
4508 | instructions. It is like mips_no_prev_insn except that it inserts | |
4509 | any NOPS that might be needed by previous instructions. */ | |
252b5132 | 4510 | |
7d10b47d RS |
4511 | void |
4512 | mips_emit_delays (void) | |
252b5132 RH |
4513 | { |
4514 | if (! mips_opts.noreorder) | |
4515 | { | |
932d1a1b | 4516 | int nops = nops_for_insn (0, history, NULL); |
252b5132 RH |
4517 | if (nops > 0) |
4518 | { | |
7d10b47d RS |
4519 | while (nops-- > 0) |
4520 | add_fixed_insn (NOP_INSN); | |
4521 | mips_move_labels (); | |
4522 | } | |
4523 | } | |
4524 | mips_no_prev_insn (); | |
4525 | } | |
4526 | ||
4527 | /* Start a (possibly nested) noreorder block. */ | |
4528 | ||
4529 | static void | |
4530 | start_noreorder (void) | |
4531 | { | |
4532 | if (mips_opts.noreorder == 0) | |
4533 | { | |
4534 | unsigned int i; | |
4535 | int nops; | |
4536 | ||
4537 | /* None of the instructions before the .set noreorder can be moved. */ | |
4538 | for (i = 0; i < ARRAY_SIZE (history); i++) | |
4539 | history[i].fixed_p = 1; | |
4540 | ||
4541 | /* Insert any nops that might be needed between the .set noreorder | |
4542 | block and the previous instructions. We will later remove any | |
4543 | nops that turn out not to be needed. */ | |
932d1a1b | 4544 | nops = nops_for_insn (0, history, NULL); |
7d10b47d RS |
4545 | if (nops > 0) |
4546 | { | |
4547 | if (mips_optimize != 0) | |
252b5132 RH |
4548 | { |
4549 | /* Record the frag which holds the nop instructions, so | |
4550 | that we can remove them if we don't need them. */ | |
df58fc94 | 4551 | frag_grow (nops * NOP_INSN_SIZE); |
252b5132 RH |
4552 | prev_nop_frag = frag_now; |
4553 | prev_nop_frag_holds = nops; | |
4554 | prev_nop_frag_required = 0; | |
4555 | prev_nop_frag_since = 0; | |
4556 | } | |
4557 | ||
4558 | for (; nops > 0; --nops) | |
1e915849 | 4559 | add_fixed_insn (NOP_INSN); |
252b5132 | 4560 | |
7d10b47d RS |
4561 | /* Move on to a new frag, so that it is safe to simply |
4562 | decrease the size of prev_nop_frag. */ | |
4563 | frag_wane (frag_now); | |
4564 | frag_new (0); | |
404a8071 | 4565 | mips_move_labels (); |
252b5132 | 4566 | } |
df58fc94 | 4567 | mips_mark_labels (); |
7d10b47d | 4568 | mips_clear_insn_labels (); |
252b5132 | 4569 | } |
7d10b47d RS |
4570 | mips_opts.noreorder++; |
4571 | mips_any_noreorder = 1; | |
4572 | } | |
252b5132 | 4573 | |
7d10b47d | 4574 | /* End a nested noreorder block. */ |
252b5132 | 4575 | |
7d10b47d RS |
4576 | static void |
4577 | end_noreorder (void) | |
4578 | { | |
6a32d874 | 4579 | |
7d10b47d RS |
4580 | mips_opts.noreorder--; |
4581 | if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) | |
4582 | { | |
4583 | /* Commit to inserting prev_nop_frag_required nops and go back to | |
4584 | handling nop insertion the .set reorder way. */ | |
4585 | prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) | |
df58fc94 | 4586 | * NOP_INSN_SIZE); |
7d10b47d RS |
4587 | insert_into_history (prev_nop_frag_since, |
4588 | prev_nop_frag_required, NOP_INSN); | |
4589 | prev_nop_frag = NULL; | |
4590 | } | |
252b5132 RH |
4591 | } |
4592 | ||
584892a6 RS |
4593 | /* Set up global variables for the start of a new macro. */ |
4594 | ||
4595 | static void | |
4596 | macro_start (void) | |
4597 | { | |
4598 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
df58fc94 RS |
4599 | memset (&mips_macro_warning.first_insn_sizes, 0, |
4600 | sizeof (mips_macro_warning.first_insn_sizes)); | |
4601 | memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns)); | |
584892a6 | 4602 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder |
11625dd8 | 4603 | && delayed_branch_p (&history[0])); |
df58fc94 RS |
4604 | switch (history[0].insn_mo->pinfo2 |
4605 | & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT)) | |
4606 | { | |
4607 | case INSN2_BRANCH_DELAY_32BIT: | |
4608 | mips_macro_warning.delay_slot_length = 4; | |
4609 | break; | |
4610 | case INSN2_BRANCH_DELAY_16BIT: | |
4611 | mips_macro_warning.delay_slot_length = 2; | |
4612 | break; | |
4613 | default: | |
4614 | mips_macro_warning.delay_slot_length = 0; | |
4615 | break; | |
4616 | } | |
4617 | mips_macro_warning.first_frag = NULL; | |
584892a6 RS |
4618 | } |
4619 | ||
df58fc94 RS |
4620 | /* Given that a macro is longer than one instruction or of the wrong size, |
4621 | return the appropriate warning for it. Return null if no warning is | |
4622 | needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT, | |
4623 | RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND, | |
4624 | and RELAX_NOMACRO. */ | |
584892a6 RS |
4625 | |
4626 | static const char * | |
4627 | macro_warning (relax_substateT subtype) | |
4628 | { | |
4629 | if (subtype & RELAX_DELAY_SLOT) | |
4630 | return _("Macro instruction expanded into multiple instructions" | |
4631 | " in a branch delay slot"); | |
4632 | else if (subtype & RELAX_NOMACRO) | |
4633 | return _("Macro instruction expanded into multiple instructions"); | |
df58fc94 RS |
4634 | else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST |
4635 | | RELAX_DELAY_SLOT_SIZE_SECOND)) | |
4636 | return ((subtype & RELAX_DELAY_SLOT_16BIT) | |
4637 | ? _("Macro instruction expanded into a wrong size instruction" | |
4638 | " in a 16-bit branch delay slot") | |
4639 | : _("Macro instruction expanded into a wrong size instruction" | |
4640 | " in a 32-bit branch delay slot")); | |
584892a6 RS |
4641 | else |
4642 | return 0; | |
4643 | } | |
4644 | ||
4645 | /* Finish up a macro. Emit warnings as appropriate. */ | |
4646 | ||
4647 | static void | |
4648 | macro_end (void) | |
4649 | { | |
df58fc94 RS |
4650 | /* Relaxation warning flags. */ |
4651 | relax_substateT subtype = 0; | |
4652 | ||
4653 | /* Check delay slot size requirements. */ | |
4654 | if (mips_macro_warning.delay_slot_length == 2) | |
4655 | subtype |= RELAX_DELAY_SLOT_16BIT; | |
4656 | if (mips_macro_warning.delay_slot_length != 0) | |
584892a6 | 4657 | { |
df58fc94 RS |
4658 | if (mips_macro_warning.delay_slot_length |
4659 | != mips_macro_warning.first_insn_sizes[0]) | |
4660 | subtype |= RELAX_DELAY_SLOT_SIZE_FIRST; | |
4661 | if (mips_macro_warning.delay_slot_length | |
4662 | != mips_macro_warning.first_insn_sizes[1]) | |
4663 | subtype |= RELAX_DELAY_SLOT_SIZE_SECOND; | |
4664 | } | |
584892a6 | 4665 | |
df58fc94 RS |
4666 | /* Check instruction count requirements. */ |
4667 | if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1) | |
4668 | { | |
4669 | if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0]) | |
584892a6 RS |
4670 | subtype |= RELAX_SECOND_LONGER; |
4671 | if (mips_opts.warn_about_macros) | |
4672 | subtype |= RELAX_NOMACRO; | |
4673 | if (mips_macro_warning.delay_slot_p) | |
4674 | subtype |= RELAX_DELAY_SLOT; | |
df58fc94 | 4675 | } |
584892a6 | 4676 | |
df58fc94 RS |
4677 | /* If both alternatives fail to fill a delay slot correctly, |
4678 | emit the warning now. */ | |
4679 | if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0 | |
4680 | && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0) | |
4681 | { | |
4682 | relax_substateT s; | |
4683 | const char *msg; | |
4684 | ||
4685 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
4686 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
4687 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
4688 | msg = macro_warning (s); | |
4689 | if (msg != NULL) | |
4690 | as_warn ("%s", msg); | |
4691 | subtype &= ~s; | |
4692 | } | |
4693 | ||
4694 | /* If both implementations are longer than 1 instruction, then emit the | |
4695 | warning now. */ | |
4696 | if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1) | |
4697 | { | |
4698 | relax_substateT s; | |
4699 | const char *msg; | |
4700 | ||
4701 | s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT); | |
4702 | msg = macro_warning (s); | |
4703 | if (msg != NULL) | |
4704 | as_warn ("%s", msg); | |
4705 | subtype &= ~s; | |
584892a6 | 4706 | } |
df58fc94 RS |
4707 | |
4708 | /* If any flags still set, then one implementation might need a warning | |
4709 | and the other either will need one of a different kind or none at all. | |
4710 | Pass any remaining flags over to relaxation. */ | |
4711 | if (mips_macro_warning.first_frag != NULL) | |
4712 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
584892a6 RS |
4713 | } |
4714 | ||
df58fc94 RS |
4715 | /* Instruction operand formats used in macros that vary between |
4716 | standard MIPS and microMIPS code. */ | |
4717 | ||
4718 | static const char * const brk_fmt[2] = { "c", "mF" }; | |
4719 | static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" }; | |
4720 | static const char * const jalr_fmt[2] = { "d,s", "t,s" }; | |
4721 | static const char * const lui_fmt[2] = { "t,u", "s,u" }; | |
4722 | static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" }; | |
4723 | static const char * const mfhl_fmt[2] = { "d", "mj" }; | |
4724 | static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" }; | |
4725 | static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" }; | |
4726 | ||
4727 | #define BRK_FMT (brk_fmt[mips_opts.micromips]) | |
4728 | #define COP12_FMT (cop12_fmt[mips_opts.micromips]) | |
4729 | #define JALR_FMT (jalr_fmt[mips_opts.micromips]) | |
4730 | #define LUI_FMT (lui_fmt[mips_opts.micromips]) | |
4731 | #define MEM12_FMT (mem12_fmt[mips_opts.micromips]) | |
4732 | #define MFHL_FMT (mfhl_fmt[mips_opts.micromips]) | |
4733 | #define SHFT_FMT (shft_fmt[mips_opts.micromips]) | |
4734 | #define TRAP_FMT (trap_fmt[mips_opts.micromips]) | |
4735 | ||
6e1304d8 RS |
4736 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
4737 | The first argument in *ARGS will be either the code for a single | |
4738 | relocation or -1 followed by the three codes that make up a | |
4739 | composite relocation. */ | |
4740 | ||
4741 | static void | |
4742 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
4743 | { | |
4744 | int i, next; | |
4745 | ||
4746 | next = va_arg (*args, int); | |
4747 | if (next >= 0) | |
4748 | r[0] = (bfd_reloc_code_real_type) next; | |
4749 | else | |
4750 | for (i = 0; i < 3; i++) | |
4751 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
4752 | } | |
4753 | ||
252b5132 RH |
4754 | /* Build an instruction created by a macro expansion. This is passed |
4755 | a pointer to the count of instructions created so far, an | |
4756 | expression, the name of the instruction to build, an operand format | |
4757 | string, and corresponding arguments. */ | |
4758 | ||
252b5132 | 4759 | static void |
67c0d1eb | 4760 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 | 4761 | { |
df58fc94 | 4762 | const struct mips_opcode *mo = NULL; |
f6688943 | 4763 | bfd_reloc_code_real_type r[3]; |
df58fc94 RS |
4764 | const struct mips_opcode *amo; |
4765 | struct hash_control *hash; | |
4766 | struct mips_cl_insn insn; | |
252b5132 | 4767 | va_list args; |
252b5132 | 4768 | |
252b5132 | 4769 | va_start (args, fmt); |
252b5132 | 4770 | |
252b5132 RH |
4771 | if (mips_opts.mips16) |
4772 | { | |
03ea81db | 4773 | mips16_macro_build (ep, name, fmt, &args); |
252b5132 RH |
4774 | va_end (args); |
4775 | return; | |
4776 | } | |
4777 | ||
f6688943 TS |
4778 | r[0] = BFD_RELOC_UNUSED; |
4779 | r[1] = BFD_RELOC_UNUSED; | |
4780 | r[2] = BFD_RELOC_UNUSED; | |
df58fc94 RS |
4781 | hash = mips_opts.micromips ? micromips_op_hash : op_hash; |
4782 | amo = (struct mips_opcode *) hash_find (hash, name); | |
4783 | gas_assert (amo); | |
4784 | gas_assert (strcmp (name, amo->name) == 0); | |
1e915849 | 4785 | |
df58fc94 | 4786 | do |
8b082fb1 TS |
4787 | { |
4788 | /* Search until we get a match for NAME. It is assumed here that | |
df58fc94 RS |
4789 | macros will never generate MDMX, MIPS-3D, or MT instructions. |
4790 | We try to match an instruction that fulfils the branch delay | |
4791 | slot instruction length requirement (if any) of the previous | |
4792 | instruction. While doing this we record the first instruction | |
4793 | seen that matches all the other conditions and use it anyway | |
4794 | if the requirement cannot be met; we will issue an appropriate | |
4795 | warning later on. */ | |
4796 | if (strcmp (fmt, amo->args) == 0 | |
4797 | && amo->pinfo != INSN_MACRO | |
4798 | && is_opcode_valid (amo) | |
4799 | && is_size_valid (amo)) | |
4800 | { | |
4801 | if (is_delay_slot_valid (amo)) | |
4802 | { | |
4803 | mo = amo; | |
4804 | break; | |
4805 | } | |
4806 | else if (!mo) | |
4807 | mo = amo; | |
4808 | } | |
8b082fb1 | 4809 | |
df58fc94 RS |
4810 | ++amo; |
4811 | gas_assert (amo->name); | |
252b5132 | 4812 | } |
df58fc94 | 4813 | while (strcmp (name, amo->name) == 0); |
252b5132 | 4814 | |
df58fc94 | 4815 | gas_assert (mo); |
1e915849 | 4816 | create_insn (&insn, mo); |
252b5132 RH |
4817 | for (;;) |
4818 | { | |
4819 | switch (*fmt++) | |
4820 | { | |
4821 | case '\0': | |
4822 | break; | |
4823 | ||
4824 | case ',': | |
4825 | case '(': | |
4826 | case ')': | |
4827 | continue; | |
4828 | ||
5f74bc13 CD |
4829 | case '+': |
4830 | switch (*fmt++) | |
4831 | { | |
4832 | case 'A': | |
4833 | case 'E': | |
df58fc94 RS |
4834 | INSERT_OPERAND (mips_opts.micromips, |
4835 | EXTLSB, insn, va_arg (args, int)); | |
5f74bc13 CD |
4836 | continue; |
4837 | ||
4838 | case 'B': | |
4839 | case 'F': | |
4840 | /* Note that in the macro case, these arguments are already | |
4841 | in MSB form. (When handling the instruction in the | |
4842 | non-macro case, these arguments are sizes from which | |
4843 | MSB values must be calculated.) */ | |
df58fc94 RS |
4844 | INSERT_OPERAND (mips_opts.micromips, |
4845 | INSMSB, insn, va_arg (args, int)); | |
5f74bc13 CD |
4846 | continue; |
4847 | ||
4848 | case 'C': | |
4849 | case 'G': | |
4850 | case 'H': | |
4851 | /* Note that in the macro case, these arguments are already | |
4852 | in MSBD form. (When handling the instruction in the | |
4853 | non-macro case, these arguments are sizes from which | |
4854 | MSBD values must be calculated.) */ | |
df58fc94 RS |
4855 | INSERT_OPERAND (mips_opts.micromips, |
4856 | EXTMSBD, insn, va_arg (args, int)); | |
5f74bc13 CD |
4857 | continue; |
4858 | ||
dd3cbb7e | 4859 | case 'Q': |
df58fc94 RS |
4860 | gas_assert (!mips_opts.micromips); |
4861 | INSERT_OPERAND (0, SEQI, insn, va_arg (args, int)); | |
dd3cbb7e NC |
4862 | continue; |
4863 | ||
5f74bc13 CD |
4864 | default: |
4865 | internalError (); | |
4866 | } | |
4867 | continue; | |
4868 | ||
8b082fb1 | 4869 | case '2': |
df58fc94 RS |
4870 | gas_assert (!mips_opts.micromips); |
4871 | INSERT_OPERAND (0, BP, insn, va_arg (args, int)); | |
8b082fb1 TS |
4872 | continue; |
4873 | ||
df58fc94 RS |
4874 | case 'n': |
4875 | gas_assert (mips_opts.micromips); | |
252b5132 RH |
4876 | case 't': |
4877 | case 'w': | |
4878 | case 'E': | |
df58fc94 | 4879 | INSERT_OPERAND (mips_opts.micromips, RT, insn, va_arg (args, int)); |
252b5132 RH |
4880 | continue; |
4881 | ||
4882 | case 'c': | |
df58fc94 RS |
4883 | gas_assert (!mips_opts.micromips); |
4884 | INSERT_OPERAND (0, CODE, insn, va_arg (args, int)); | |
38487616 TS |
4885 | continue; |
4886 | ||
252b5132 | 4887 | case 'W': |
df58fc94 RS |
4888 | gas_assert (!mips_opts.micromips); |
4889 | case 'T': | |
4890 | INSERT_OPERAND (mips_opts.micromips, FT, insn, va_arg (args, int)); | |
252b5132 RH |
4891 | continue; |
4892 | ||
252b5132 | 4893 | case 'G': |
df58fc94 RS |
4894 | if (mips_opts.micromips) |
4895 | INSERT_OPERAND (1, RS, insn, va_arg (args, int)); | |
4896 | else | |
4897 | INSERT_OPERAND (0, RD, insn, va_arg (args, int)); | |
4898 | continue; | |
4899 | ||
af7ee8bf | 4900 | case 'K': |
df58fc94 RS |
4901 | gas_assert (!mips_opts.micromips); |
4902 | case 'd': | |
4903 | INSERT_OPERAND (mips_opts.micromips, RD, insn, va_arg (args, int)); | |
252b5132 RH |
4904 | continue; |
4905 | ||
4372b673 | 4906 | case 'U': |
df58fc94 | 4907 | gas_assert (!mips_opts.micromips); |
4372b673 NC |
4908 | { |
4909 | int tmp = va_arg (args, int); | |
4910 | ||
df58fc94 RS |
4911 | INSERT_OPERAND (0, RT, insn, tmp); |
4912 | INSERT_OPERAND (0, RD, insn, tmp); | |
4372b673 | 4913 | } |
df58fc94 | 4914 | continue; |
4372b673 | 4915 | |
252b5132 RH |
4916 | case 'V': |
4917 | case 'S': | |
df58fc94 RS |
4918 | gas_assert (!mips_opts.micromips); |
4919 | INSERT_OPERAND (0, FS, insn, va_arg (args, int)); | |
252b5132 RH |
4920 | continue; |
4921 | ||
4922 | case 'z': | |
4923 | continue; | |
4924 | ||
4925 | case '<': | |
df58fc94 RS |
4926 | INSERT_OPERAND (mips_opts.micromips, |
4927 | SHAMT, insn, va_arg (args, int)); | |
252b5132 RH |
4928 | continue; |
4929 | ||
4930 | case 'D': | |
df58fc94 RS |
4931 | gas_assert (!mips_opts.micromips); |
4932 | INSERT_OPERAND (0, FD, insn, va_arg (args, int)); | |
252b5132 RH |
4933 | continue; |
4934 | ||
4935 | case 'B': | |
df58fc94 RS |
4936 | gas_assert (!mips_opts.micromips); |
4937 | INSERT_OPERAND (0, CODE20, insn, va_arg (args, int)); | |
252b5132 RH |
4938 | continue; |
4939 | ||
4372b673 | 4940 | case 'J': |
df58fc94 RS |
4941 | gas_assert (!mips_opts.micromips); |
4942 | INSERT_OPERAND (0, CODE19, insn, va_arg (args, int)); | |
4372b673 NC |
4943 | continue; |
4944 | ||
252b5132 | 4945 | case 'q': |
df58fc94 RS |
4946 | gas_assert (!mips_opts.micromips); |
4947 | INSERT_OPERAND (0, CODE2, insn, va_arg (args, int)); | |
252b5132 RH |
4948 | continue; |
4949 | ||
4950 | case 'b': | |
4951 | case 's': | |
4952 | case 'r': | |
4953 | case 'v': | |
df58fc94 | 4954 | INSERT_OPERAND (mips_opts.micromips, RS, insn, va_arg (args, int)); |
252b5132 RH |
4955 | continue; |
4956 | ||
4957 | case 'i': | |
4958 | case 'j': | |
6e1304d8 | 4959 | macro_read_relocs (&args, r); |
9c2799c2 | 4960 | gas_assert (*r == BFD_RELOC_GPREL16 |
e391c024 RS |
4961 | || *r == BFD_RELOC_MIPS_HIGHER |
4962 | || *r == BFD_RELOC_HI16_S | |
4963 | || *r == BFD_RELOC_LO16 | |
4964 | || *r == BFD_RELOC_MIPS_GOT_OFST); | |
4965 | continue; | |
4966 | ||
4967 | case 'o': | |
4968 | macro_read_relocs (&args, r); | |
252b5132 RH |
4969 | continue; |
4970 | ||
4971 | case 'u': | |
6e1304d8 | 4972 | macro_read_relocs (&args, r); |
9c2799c2 | 4973 | gas_assert (ep != NULL |
90ecf173 MR |
4974 | && (ep->X_op == O_constant |
4975 | || (ep->X_op == O_symbol | |
4976 | && (*r == BFD_RELOC_MIPS_HIGHEST | |
4977 | || *r == BFD_RELOC_HI16_S | |
4978 | || *r == BFD_RELOC_HI16 | |
4979 | || *r == BFD_RELOC_GPREL16 | |
4980 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
4981 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); | |
252b5132 RH |
4982 | continue; |
4983 | ||
4984 | case 'p': | |
9c2799c2 | 4985 | gas_assert (ep != NULL); |
bad36eac | 4986 | |
252b5132 RH |
4987 | /* |
4988 | * This allows macro() to pass an immediate expression for | |
4989 | * creating short branches without creating a symbol. | |
bad36eac DJ |
4990 | * |
4991 | * We don't allow branch relaxation for these branches, as | |
4992 | * they should only appear in ".set nomacro" anyway. | |
252b5132 RH |
4993 | */ |
4994 | if (ep->X_op == O_constant) | |
4995 | { | |
df58fc94 RS |
4996 | /* For microMIPS we always use relocations for branches. |
4997 | So we should not resolve immediate values. */ | |
4998 | gas_assert (!mips_opts.micromips); | |
4999 | ||
bad36eac DJ |
5000 | if ((ep->X_add_number & 3) != 0) |
5001 | as_bad (_("branch to misaligned address (0x%lx)"), | |
5002 | (unsigned long) ep->X_add_number); | |
5003 | if ((ep->X_add_number + 0x20000) & ~0x3ffff) | |
5004 | as_bad (_("branch address range overflow (0x%lx)"), | |
5005 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
5006 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; |
5007 | ep = NULL; | |
5008 | } | |
5009 | else | |
0b25d3e6 | 5010 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
5011 | continue; |
5012 | ||
5013 | case 'a': | |
9c2799c2 | 5014 | gas_assert (ep != NULL); |
f6688943 | 5015 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
5016 | continue; |
5017 | ||
5018 | case 'C': | |
df58fc94 RS |
5019 | gas_assert (!mips_opts.micromips); |
5020 | INSERT_OPERAND (0, COPZ, insn, va_arg (args, unsigned long)); | |
252b5132 RH |
5021 | continue; |
5022 | ||
d43b4baf | 5023 | case 'k': |
df58fc94 RS |
5024 | INSERT_OPERAND (mips_opts.micromips, |
5025 | CACHE, insn, va_arg (args, unsigned long)); | |
5026 | continue; | |
5027 | ||
5028 | case '|': | |
5029 | gas_assert (mips_opts.micromips); | |
5030 | INSERT_OPERAND (1, TRAP, insn, va_arg (args, int)); | |
5031 | continue; | |
5032 | ||
5033 | case '.': | |
5034 | gas_assert (mips_opts.micromips); | |
5035 | INSERT_OPERAND (1, OFFSET10, insn, va_arg (args, int)); | |
5036 | continue; | |
5037 | ||
5038 | case '~': | |
5039 | gas_assert (mips_opts.micromips); | |
5040 | INSERT_OPERAND (1, OFFSET12, insn, va_arg (args, unsigned long)); | |
5041 | continue; | |
5042 | ||
5043 | case 'N': | |
5044 | gas_assert (mips_opts.micromips); | |
5045 | INSERT_OPERAND (1, BCC, insn, va_arg (args, int)); | |
5046 | continue; | |
5047 | ||
5048 | case 'm': /* Opcode extension character. */ | |
5049 | gas_assert (mips_opts.micromips); | |
5050 | switch (*fmt++) | |
5051 | { | |
5052 | case 'j': | |
5053 | INSERT_OPERAND (1, MJ, insn, va_arg (args, int)); | |
5054 | break; | |
5055 | ||
5056 | case 'p': | |
5057 | INSERT_OPERAND (1, MP, insn, va_arg (args, int)); | |
5058 | break; | |
5059 | ||
5060 | case 'F': | |
5061 | INSERT_OPERAND (1, IMMF, insn, va_arg (args, int)); | |
5062 | break; | |
5063 | ||
5064 | default: | |
5065 | internalError (); | |
5066 | } | |
d43b4baf TS |
5067 | continue; |
5068 | ||
252b5132 RH |
5069 | default: |
5070 | internalError (); | |
5071 | } | |
5072 | break; | |
5073 | } | |
5074 | va_end (args); | |
9c2799c2 | 5075 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 5076 | |
df58fc94 | 5077 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
5078 | } |
5079 | ||
5080 | static void | |
67c0d1eb | 5081 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
03ea81db | 5082 | va_list *args) |
252b5132 | 5083 | { |
1e915849 | 5084 | struct mips_opcode *mo; |
252b5132 | 5085 | struct mips_cl_insn insn; |
f6688943 TS |
5086 | bfd_reloc_code_real_type r[3] |
5087 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 5088 | |
1e915849 | 5089 | mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
9c2799c2 NC |
5090 | gas_assert (mo); |
5091 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 | 5092 | |
1e915849 | 5093 | while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) |
252b5132 | 5094 | { |
1e915849 | 5095 | ++mo; |
9c2799c2 NC |
5096 | gas_assert (mo->name); |
5097 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
5098 | } |
5099 | ||
1e915849 | 5100 | create_insn (&insn, mo); |
252b5132 RH |
5101 | for (;;) |
5102 | { | |
5103 | int c; | |
5104 | ||
5105 | c = *fmt++; | |
5106 | switch (c) | |
5107 | { | |
5108 | case '\0': | |
5109 | break; | |
5110 | ||
5111 | case ',': | |
5112 | case '(': | |
5113 | case ')': | |
5114 | continue; | |
5115 | ||
5116 | case 'y': | |
5117 | case 'w': | |
03ea81db | 5118 | MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int)); |
252b5132 RH |
5119 | continue; |
5120 | ||
5121 | case 'x': | |
5122 | case 'v': | |
03ea81db | 5123 | MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int)); |
252b5132 RH |
5124 | continue; |
5125 | ||
5126 | case 'z': | |
03ea81db | 5127 | MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int)); |
252b5132 RH |
5128 | continue; |
5129 | ||
5130 | case 'Z': | |
03ea81db | 5131 | MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int)); |
252b5132 RH |
5132 | continue; |
5133 | ||
5134 | case '0': | |
5135 | case 'S': | |
5136 | case 'P': | |
5137 | case 'R': | |
5138 | continue; | |
5139 | ||
5140 | case 'X': | |
03ea81db | 5141 | MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int)); |
252b5132 RH |
5142 | continue; |
5143 | ||
5144 | case 'Y': | |
5145 | { | |
5146 | int regno; | |
5147 | ||
03ea81db | 5148 | regno = va_arg (*args, int); |
252b5132 | 5149 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); |
a9e24354 | 5150 | MIPS16_INSERT_OPERAND (REG32R, insn, regno); |
252b5132 RH |
5151 | } |
5152 | continue; | |
5153 | ||
5154 | case '<': | |
5155 | case '>': | |
5156 | case '4': | |
5157 | case '5': | |
5158 | case 'H': | |
5159 | case 'W': | |
5160 | case 'D': | |
5161 | case 'j': | |
5162 | case '8': | |
5163 | case 'V': | |
5164 | case 'C': | |
5165 | case 'U': | |
5166 | case 'k': | |
5167 | case 'K': | |
5168 | case 'p': | |
5169 | case 'q': | |
5170 | { | |
9c2799c2 | 5171 | gas_assert (ep != NULL); |
252b5132 RH |
5172 | |
5173 | if (ep->X_op != O_constant) | |
874e8986 | 5174 | *r = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
5175 | else |
5176 | { | |
b34976b6 AM |
5177 | mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE, |
5178 | FALSE, &insn.insn_opcode, &insn.use_extend, | |
c4e7957c | 5179 | &insn.extend); |
252b5132 | 5180 | ep = NULL; |
f6688943 | 5181 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
5182 | } |
5183 | } | |
5184 | continue; | |
5185 | ||
5186 | case '6': | |
03ea81db | 5187 | MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int)); |
252b5132 RH |
5188 | continue; |
5189 | } | |
5190 | ||
5191 | break; | |
5192 | } | |
5193 | ||
9c2799c2 | 5194 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 5195 | |
df58fc94 | 5196 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
5197 | } |
5198 | ||
2051e8c4 MR |
5199 | /* |
5200 | * Sign-extend 32-bit mode constants that have bit 31 set and all | |
5201 | * higher bits unset. | |
5202 | */ | |
9f872bbe | 5203 | static void |
2051e8c4 MR |
5204 | normalize_constant_expr (expressionS *ex) |
5205 | { | |
9ee2a2d4 | 5206 | if (ex->X_op == O_constant |
2051e8c4 MR |
5207 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) |
5208 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
5209 | - 0x80000000); | |
5210 | } | |
5211 | ||
5212 | /* | |
5213 | * Sign-extend 32-bit mode address offsets that have bit 31 set and | |
5214 | * all higher bits unset. | |
5215 | */ | |
5216 | static void | |
5217 | normalize_address_expr (expressionS *ex) | |
5218 | { | |
5219 | if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) | |
5220 | || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) | |
5221 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
5222 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
5223 | - 0x80000000); | |
5224 | } | |
5225 | ||
438c16b8 TS |
5226 | /* |
5227 | * Generate a "jalr" instruction with a relocation hint to the called | |
5228 | * function. This occurs in NewABI PIC code. | |
5229 | */ | |
5230 | static void | |
df58fc94 | 5231 | macro_build_jalr (expressionS *ep, int cprestore) |
438c16b8 | 5232 | { |
df58fc94 RS |
5233 | static const bfd_reloc_code_real_type jalr_relocs[2] |
5234 | = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR }; | |
5235 | bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips]; | |
5236 | const char *jalr; | |
685736be | 5237 | char *f = NULL; |
b34976b6 | 5238 | |
1180b5a4 | 5239 | if (MIPS_JALR_HINT_P (ep)) |
f21f8242 | 5240 | { |
cc3d92a5 | 5241 | frag_grow (8); |
f21f8242 AO |
5242 | f = frag_more (0); |
5243 | } | |
df58fc94 RS |
5244 | if (!mips_opts.micromips) |
5245 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); | |
5246 | else | |
5247 | { | |
5248 | jalr = mips_opts.noreorder && !cprestore ? "jalr" : "jalrs"; | |
5249 | if (MIPS_JALR_HINT_P (ep)) | |
5250 | macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG); | |
5251 | else | |
5252 | macro_build (NULL, jalr, "mj", PIC_CALL_REG); | |
5253 | } | |
1180b5a4 | 5254 | if (MIPS_JALR_HINT_P (ep)) |
df58fc94 | 5255 | fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc); |
438c16b8 TS |
5256 | } |
5257 | ||
252b5132 RH |
5258 | /* |
5259 | * Generate a "lui" instruction. | |
5260 | */ | |
5261 | static void | |
67c0d1eb | 5262 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 | 5263 | { |
9c2799c2 | 5264 | gas_assert (! mips_opts.mips16); |
252b5132 | 5265 | |
df58fc94 | 5266 | if (ep->X_op != O_constant) |
252b5132 | 5267 | { |
9c2799c2 | 5268 | gas_assert (ep->X_op == O_symbol); |
bbe506e8 TS |
5269 | /* _gp_disp is a special case, used from s_cpload. |
5270 | __gnu_local_gp is used if mips_no_shared. */ | |
9c2799c2 | 5271 | gas_assert (mips_pic == NO_PIC |
78e1bb40 | 5272 | || (! HAVE_NEWABI |
aa6975fb ILT |
5273 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
5274 | || (! mips_in_shared | |
bbe506e8 TS |
5275 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
5276 | "__gnu_local_gp") == 0)); | |
252b5132 RH |
5277 | } |
5278 | ||
df58fc94 | 5279 | macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S); |
252b5132 RH |
5280 | } |
5281 | ||
885add95 CD |
5282 | /* Generate a sequence of instructions to do a load or store from a constant |
5283 | offset off of a base register (breg) into/from a target register (treg), | |
5284 | using AT if necessary. */ | |
5285 | static void | |
67c0d1eb RS |
5286 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
5287 | int treg, int breg, int dbl) | |
885add95 | 5288 | { |
9c2799c2 | 5289 | gas_assert (ep->X_op == O_constant); |
885add95 | 5290 | |
256ab948 | 5291 | /* Sign-extending 32-bit constants makes their handling easier. */ |
2051e8c4 MR |
5292 | if (!dbl) |
5293 | normalize_constant_expr (ep); | |
256ab948 | 5294 | |
67c1ffbe | 5295 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 5296 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
5297 | as_warn (_("operand overflow")); |
5298 | ||
5299 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
5300 | { | |
5301 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 5302 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
5303 | } |
5304 | else | |
5305 | { | |
5306 | /* 32-bit offset, need multiple instructions and AT, like: | |
5307 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
5308 | addu $tempreg,$tempreg,$breg | |
5309 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
5310 | to handle the complete offset. */ | |
67c0d1eb RS |
5311 | macro_build_lui (ep, AT); |
5312 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
5313 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 | 5314 | |
741fe287 | 5315 | if (!mips_opts.at) |
8fc2e39e | 5316 | as_bad (_("Macro used $at after \".set noat\"")); |
885add95 CD |
5317 | } |
5318 | } | |
5319 | ||
252b5132 RH |
5320 | /* set_at() |
5321 | * Generates code to set the $at register to true (one) | |
5322 | * if reg is less than the immediate expression. | |
5323 | */ | |
5324 | static void | |
67c0d1eb | 5325 | set_at (int reg, int unsignedp) |
252b5132 RH |
5326 | { |
5327 | if (imm_expr.X_op == O_constant | |
5328 | && imm_expr.X_add_number >= -0x8000 | |
5329 | && imm_expr.X_add_number < 0x8000) | |
67c0d1eb RS |
5330 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
5331 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
5332 | else |
5333 | { | |
67c0d1eb RS |
5334 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
5335 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); | |
252b5132 RH |
5336 | } |
5337 | } | |
5338 | ||
5339 | /* Warn if an expression is not a constant. */ | |
5340 | ||
5341 | static void | |
17a2f251 | 5342 | check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) |
252b5132 RH |
5343 | { |
5344 | if (ex->X_op == O_big) | |
5345 | as_bad (_("unsupported large constant")); | |
5346 | else if (ex->X_op != O_constant) | |
9ee2a2d4 MR |
5347 | as_bad (_("Instruction %s requires absolute expression"), |
5348 | ip->insn_mo->name); | |
13757d0c | 5349 | |
9ee2a2d4 MR |
5350 | if (HAVE_32BIT_GPRS) |
5351 | normalize_constant_expr (ex); | |
252b5132 RH |
5352 | } |
5353 | ||
5354 | /* Count the leading zeroes by performing a binary chop. This is a | |
5355 | bulky bit of source, but performance is a LOT better for the | |
5356 | majority of values than a simple loop to count the bits: | |
5357 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
5358 | if ((v) & (1 << (31 - lcnt))) | |
5359 | break; | |
5360 | However it is not code size friendly, and the gain will drop a bit | |
5361 | on certain cached systems. | |
5362 | */ | |
5363 | #define COUNT_TOP_ZEROES(v) \ | |
5364 | (((v) & ~0xffff) == 0 \ | |
5365 | ? ((v) & ~0xff) == 0 \ | |
5366 | ? ((v) & ~0xf) == 0 \ | |
5367 | ? ((v) & ~0x3) == 0 \ | |
5368 | ? ((v) & ~0x1) == 0 \ | |
5369 | ? !(v) \ | |
5370 | ? 32 \ | |
5371 | : 31 \ | |
5372 | : 30 \ | |
5373 | : ((v) & ~0x7) == 0 \ | |
5374 | ? 29 \ | |
5375 | : 28 \ | |
5376 | : ((v) & ~0x3f) == 0 \ | |
5377 | ? ((v) & ~0x1f) == 0 \ | |
5378 | ? 27 \ | |
5379 | : 26 \ | |
5380 | : ((v) & ~0x7f) == 0 \ | |
5381 | ? 25 \ | |
5382 | : 24 \ | |
5383 | : ((v) & ~0xfff) == 0 \ | |
5384 | ? ((v) & ~0x3ff) == 0 \ | |
5385 | ? ((v) & ~0x1ff) == 0 \ | |
5386 | ? 23 \ | |
5387 | : 22 \ | |
5388 | : ((v) & ~0x7ff) == 0 \ | |
5389 | ? 21 \ | |
5390 | : 20 \ | |
5391 | : ((v) & ~0x3fff) == 0 \ | |
5392 | ? ((v) & ~0x1fff) == 0 \ | |
5393 | ? 19 \ | |
5394 | : 18 \ | |
5395 | : ((v) & ~0x7fff) == 0 \ | |
5396 | ? 17 \ | |
5397 | : 16 \ | |
5398 | : ((v) & ~0xffffff) == 0 \ | |
5399 | ? ((v) & ~0xfffff) == 0 \ | |
5400 | ? ((v) & ~0x3ffff) == 0 \ | |
5401 | ? ((v) & ~0x1ffff) == 0 \ | |
5402 | ? 15 \ | |
5403 | : 14 \ | |
5404 | : ((v) & ~0x7ffff) == 0 \ | |
5405 | ? 13 \ | |
5406 | : 12 \ | |
5407 | : ((v) & ~0x3fffff) == 0 \ | |
5408 | ? ((v) & ~0x1fffff) == 0 \ | |
5409 | ? 11 \ | |
5410 | : 10 \ | |
5411 | : ((v) & ~0x7fffff) == 0 \ | |
5412 | ? 9 \ | |
5413 | : 8 \ | |
5414 | : ((v) & ~0xfffffff) == 0 \ | |
5415 | ? ((v) & ~0x3ffffff) == 0 \ | |
5416 | ? ((v) & ~0x1ffffff) == 0 \ | |
5417 | ? 7 \ | |
5418 | : 6 \ | |
5419 | : ((v) & ~0x7ffffff) == 0 \ | |
5420 | ? 5 \ | |
5421 | : 4 \ | |
5422 | : ((v) & ~0x3fffffff) == 0 \ | |
5423 | ? ((v) & ~0x1fffffff) == 0 \ | |
5424 | ? 3 \ | |
5425 | : 2 \ | |
5426 | : ((v) & ~0x7fffffff) == 0 \ | |
5427 | ? 1 \ | |
5428 | : 0) | |
5429 | ||
5430 | /* load_register() | |
67c1ffbe | 5431 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
5432 | * an absolute expression value into a register. |
5433 | */ | |
5434 | static void | |
67c0d1eb | 5435 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
5436 | { |
5437 | int freg; | |
5438 | expressionS hi32, lo32; | |
5439 | ||
5440 | if (ep->X_op != O_big) | |
5441 | { | |
9c2799c2 | 5442 | gas_assert (ep->X_op == O_constant); |
256ab948 TS |
5443 | |
5444 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
2051e8c4 MR |
5445 | if (!dbl) |
5446 | normalize_constant_expr (ep); | |
256ab948 TS |
5447 | |
5448 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
5449 | { |
5450 | /* We can handle 16 bit signed values with an addiu to | |
5451 | $zero. No need to ever use daddiu here, since $zero and | |
5452 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 5453 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
5454 | return; |
5455 | } | |
5456 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
5457 | { | |
5458 | /* We can handle 16 bit unsigned values with an ori to | |
5459 | $zero. */ | |
67c0d1eb | 5460 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
5461 | return; |
5462 | } | |
256ab948 | 5463 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
5464 | { |
5465 | /* 32 bit values require an lui. */ | |
df58fc94 | 5466 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 5467 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 5468 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
5469 | return; |
5470 | } | |
5471 | } | |
5472 | ||
5473 | /* The value is larger than 32 bits. */ | |
5474 | ||
2051e8c4 | 5475 | if (!dbl || HAVE_32BIT_GPRS) |
252b5132 | 5476 | { |
55e08f71 NC |
5477 | char value[32]; |
5478 | ||
5479 | sprintf_vma (value, ep->X_add_number); | |
20e1fcfd | 5480 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
67c0d1eb | 5481 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
5482 | return; |
5483 | } | |
5484 | ||
5485 | if (ep->X_op != O_big) | |
5486 | { | |
5487 | hi32 = *ep; | |
5488 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
5489 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
5490 | hi32.X_add_number &= 0xffffffff; | |
5491 | lo32 = *ep; | |
5492 | lo32.X_add_number &= 0xffffffff; | |
5493 | } | |
5494 | else | |
5495 | { | |
9c2799c2 | 5496 | gas_assert (ep->X_add_number > 2); |
252b5132 RH |
5497 | if (ep->X_add_number == 3) |
5498 | generic_bignum[3] = 0; | |
5499 | else if (ep->X_add_number > 4) | |
5500 | as_bad (_("Number larger than 64 bits")); | |
5501 | lo32.X_op = O_constant; | |
5502 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
5503 | hi32.X_op = O_constant; | |
5504 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
5505 | } | |
5506 | ||
5507 | if (hi32.X_add_number == 0) | |
5508 | freg = 0; | |
5509 | else | |
5510 | { | |
5511 | int shift, bit; | |
5512 | unsigned long hi, lo; | |
5513 | ||
956cd1d6 | 5514 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
5515 | { |
5516 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
5517 | { | |
67c0d1eb | 5518 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
5519 | return; |
5520 | } | |
5521 | if (lo32.X_add_number & 0x80000000) | |
5522 | { | |
df58fc94 | 5523 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 5524 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 5525 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
5526 | return; |
5527 | } | |
5528 | } | |
252b5132 RH |
5529 | |
5530 | /* Check for 16bit shifted constant. We know that hi32 is | |
5531 | non-zero, so start the mask on the first bit of the hi32 | |
5532 | value. */ | |
5533 | shift = 17; | |
5534 | do | |
beae10d5 KH |
5535 | { |
5536 | unsigned long himask, lomask; | |
5537 | ||
5538 | if (shift < 32) | |
5539 | { | |
5540 | himask = 0xffff >> (32 - shift); | |
5541 | lomask = (0xffff << shift) & 0xffffffff; | |
5542 | } | |
5543 | else | |
5544 | { | |
5545 | himask = 0xffff << (shift - 32); | |
5546 | lomask = 0; | |
5547 | } | |
5548 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
5549 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
5550 | { | |
5551 | expressionS tmp; | |
5552 | ||
5553 | tmp.X_op = O_constant; | |
5554 | if (shift < 32) | |
5555 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
5556 | | (lo32.X_add_number >> shift)); | |
5557 | else | |
5558 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb | 5559 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
df58fc94 | 5560 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 5561 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
5562 | return; |
5563 | } | |
f9419b05 | 5564 | ++shift; |
beae10d5 KH |
5565 | } |
5566 | while (shift <= (64 - 16)); | |
252b5132 RH |
5567 | |
5568 | /* Find the bit number of the lowest one bit, and store the | |
5569 | shifted value in hi/lo. */ | |
5570 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
5571 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
5572 | if (lo != 0) | |
5573 | { | |
5574 | bit = 0; | |
5575 | while ((lo & 1) == 0) | |
5576 | { | |
5577 | lo >>= 1; | |
5578 | ++bit; | |
5579 | } | |
5580 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
5581 | hi >>= bit; | |
5582 | } | |
5583 | else | |
5584 | { | |
5585 | bit = 32; | |
5586 | while ((hi & 1) == 0) | |
5587 | { | |
5588 | hi >>= 1; | |
5589 | ++bit; | |
5590 | } | |
5591 | lo = hi; | |
5592 | hi = 0; | |
5593 | } | |
5594 | ||
5595 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
5596 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
5597 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
5598 | { |
5599 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 5600 | if (shift != 0) |
beae10d5 | 5601 | { |
252b5132 RH |
5602 | expressionS tmp; |
5603 | ||
5604 | /* This instruction will set the register to be all | |
5605 | ones. */ | |
beae10d5 KH |
5606 | tmp.X_op = O_constant; |
5607 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 5608 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
5609 | if (bit != 0) |
5610 | { | |
5611 | bit += shift; | |
df58fc94 | 5612 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 5613 | reg, reg, (bit >= 32) ? bit - 32 : bit); |
beae10d5 | 5614 | } |
df58fc94 | 5615 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT, |
67c0d1eb | 5616 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
5617 | return; |
5618 | } | |
5619 | } | |
252b5132 RH |
5620 | |
5621 | /* Sign extend hi32 before calling load_register, because we can | |
5622 | generally get better code when we load a sign extended value. */ | |
5623 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 5624 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 5625 | load_register (reg, &hi32, 0); |
252b5132 RH |
5626 | freg = reg; |
5627 | } | |
5628 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
5629 | { | |
5630 | if (freg != 0) | |
5631 | { | |
df58fc94 | 5632 | macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0); |
252b5132 RH |
5633 | freg = reg; |
5634 | } | |
5635 | } | |
5636 | else | |
5637 | { | |
5638 | expressionS mid16; | |
5639 | ||
956cd1d6 | 5640 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 5641 | { |
df58fc94 RS |
5642 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
5643 | macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0); | |
beae10d5 KH |
5644 | return; |
5645 | } | |
252b5132 RH |
5646 | |
5647 | if (freg != 0) | |
5648 | { | |
df58fc94 | 5649 | macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16); |
252b5132 RH |
5650 | freg = reg; |
5651 | } | |
5652 | mid16 = lo32; | |
5653 | mid16.X_add_number >>= 16; | |
67c0d1eb | 5654 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
df58fc94 | 5655 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
252b5132 RH |
5656 | freg = reg; |
5657 | } | |
5658 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 5659 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
5660 | } |
5661 | ||
269137b2 TS |
5662 | static inline void |
5663 | load_delay_nop (void) | |
5664 | { | |
5665 | if (!gpr_interlocks) | |
5666 | macro_build (NULL, "nop", ""); | |
5667 | } | |
5668 | ||
252b5132 RH |
5669 | /* Load an address into a register. */ |
5670 | ||
5671 | static void | |
67c0d1eb | 5672 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 5673 | { |
252b5132 RH |
5674 | if (ep->X_op != O_constant |
5675 | && ep->X_op != O_symbol) | |
5676 | { | |
5677 | as_bad (_("expression too complex")); | |
5678 | ep->X_op = O_constant; | |
5679 | } | |
5680 | ||
5681 | if (ep->X_op == O_constant) | |
5682 | { | |
67c0d1eb | 5683 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
5684 | return; |
5685 | } | |
5686 | ||
5687 | if (mips_pic == NO_PIC) | |
5688 | { | |
5689 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 5690 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
5691 | Otherwise we want |
5692 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
5693 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 5694 | If we have an addend, we always use the latter form. |
76b3015f | 5695 | |
d6bc6245 TS |
5696 | With 64bit address space and a usable $at we want |
5697 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5698 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5699 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5700 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
5701 | dsll32 $reg,0 | |
3a482fd5 | 5702 | daddu $reg,$reg,$at |
76b3015f | 5703 | |
c03099e6 | 5704 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
5705 | on superscalar processors. |
5706 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5707 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5708 | dsll $reg,16 | |
5709 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
5710 | dsll $reg,16 | |
5711 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
6caf9ef4 TS |
5712 | |
5713 | For GP relative symbols in 64bit address space we can use | |
5714 | the same sequence as in 32bit address space. */ | |
aed1a261 | 5715 | if (HAVE_64BIT_SYMBOLS) |
d6bc6245 | 5716 | { |
6caf9ef4 TS |
5717 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
5718 | && !nopic_need_relax (ep->X_add_symbol, 1)) | |
5719 | { | |
5720 | relax_start (ep->X_add_symbol); | |
5721 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
5722 | mips_gp_register, BFD_RELOC_GPREL16); | |
5723 | relax_switch (); | |
5724 | } | |
d6bc6245 | 5725 | |
741fe287 | 5726 | if (*used_at == 0 && mips_opts.at) |
d6bc6245 | 5727 | { |
df58fc94 RS |
5728 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
5729 | macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S); | |
67c0d1eb RS |
5730 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
5731 | BFD_RELOC_MIPS_HIGHER); | |
5732 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
df58fc94 | 5733 | macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0); |
67c0d1eb | 5734 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); |
d6bc6245 TS |
5735 | *used_at = 1; |
5736 | } | |
5737 | else | |
5738 | { | |
df58fc94 | 5739 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb RS |
5740 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
5741 | BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 5742 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 5743 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); |
df58fc94 | 5744 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 5745 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); |
d6bc6245 | 5746 | } |
6caf9ef4 TS |
5747 | |
5748 | if (mips_relax.sequence) | |
5749 | relax_end (); | |
d6bc6245 | 5750 | } |
252b5132 RH |
5751 | else |
5752 | { | |
d6bc6245 | 5753 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 5754 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
d6bc6245 | 5755 | { |
4d7206a2 | 5756 | relax_start (ep->X_add_symbol); |
67c0d1eb | 5757 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 5758 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 5759 | relax_switch (); |
d6bc6245 | 5760 | } |
67c0d1eb RS |
5761 | macro_build_lui (ep, reg); |
5762 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
5763 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
5764 | if (mips_relax.sequence) |
5765 | relax_end (); | |
d6bc6245 | 5766 | } |
252b5132 | 5767 | } |
0a44bf69 | 5768 | else if (!mips_big_got) |
252b5132 RH |
5769 | { |
5770 | expressionS ex; | |
5771 | ||
5772 | /* If this is a reference to an external symbol, we want | |
5773 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5774 | Otherwise we want | |
5775 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5776 | nop | |
5777 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
5778 | If there is a constant, it must be added in after. |
5779 | ||
ed6fb7bd | 5780 | If we have NewABI, we want |
f5040a92 AO |
5781 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
5782 | unless we're referencing a global symbol with a non-zero | |
5783 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
5784 | if (HAVE_NEWABI) |
5785 | { | |
f5040a92 AO |
5786 | if (ep->X_add_number) |
5787 | { | |
4d7206a2 | 5788 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 5789 | ep->X_add_number = 0; |
4d7206a2 | 5790 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
5791 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
5792 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5793 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
5794 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5795 | ex.X_op = O_constant; | |
67c0d1eb | 5796 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5797 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 5798 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 5799 | relax_switch (); |
f5040a92 | 5800 | } |
67c0d1eb | 5801 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 5802 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
5803 | if (mips_relax.sequence) |
5804 | relax_end (); | |
ed6fb7bd SC |
5805 | } |
5806 | else | |
5807 | { | |
f5040a92 AO |
5808 | ex.X_add_number = ep->X_add_number; |
5809 | ep->X_add_number = 0; | |
67c0d1eb RS |
5810 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
5811 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 5812 | load_delay_nop (); |
4d7206a2 RS |
5813 | relax_start (ep->X_add_symbol); |
5814 | relax_switch (); | |
67c0d1eb | 5815 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 5816 | BFD_RELOC_LO16); |
4d7206a2 | 5817 | relax_end (); |
ed6fb7bd | 5818 | |
f5040a92 AO |
5819 | if (ex.X_add_number != 0) |
5820 | { | |
5821 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
5822 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5823 | ex.X_op = O_constant; | |
67c0d1eb | 5824 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5825 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 5826 | } |
252b5132 RH |
5827 | } |
5828 | } | |
0a44bf69 | 5829 | else if (mips_big_got) |
252b5132 RH |
5830 | { |
5831 | expressionS ex; | |
252b5132 RH |
5832 | |
5833 | /* This is the large GOT case. If this is a reference to an | |
5834 | external symbol, we want | |
5835 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5836 | addu $reg,$reg,$gp | |
5837 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
5838 | |
5839 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
5840 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
5841 | nop | |
5842 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 5843 | If there is a constant, it must be added in after. |
f5040a92 AO |
5844 | |
5845 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
5846 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
5847 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 5848 | */ |
438c16b8 TS |
5849 | if (HAVE_NEWABI) |
5850 | { | |
4d7206a2 | 5851 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 5852 | ep->X_add_number = 0; |
4d7206a2 | 5853 | relax_start (ep->X_add_symbol); |
df58fc94 | 5854 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
5855 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
5856 | reg, reg, mips_gp_register); | |
5857 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
5858 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
5859 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
5860 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5861 | else if (ex.X_add_number) | |
5862 | { | |
5863 | ex.X_op = O_constant; | |
67c0d1eb RS |
5864 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
5865 | BFD_RELOC_LO16); | |
f5040a92 AO |
5866 | } |
5867 | ||
5868 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 5869 | relax_switch (); |
67c0d1eb | 5870 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 5871 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
5872 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
5873 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 5874 | relax_end (); |
438c16b8 | 5875 | } |
252b5132 | 5876 | else |
438c16b8 | 5877 | { |
f5040a92 AO |
5878 | ex.X_add_number = ep->X_add_number; |
5879 | ep->X_add_number = 0; | |
4d7206a2 | 5880 | relax_start (ep->X_add_symbol); |
df58fc94 | 5881 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
5882 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
5883 | reg, reg, mips_gp_register); | |
5884 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
5885 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
5886 | relax_switch (); |
5887 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
5888 | { |
5889 | /* We need a nop before loading from $gp. This special | |
5890 | check is required because the lui which starts the main | |
5891 | instruction stream does not refer to $gp, and so will not | |
5892 | insert the nop which may be required. */ | |
67c0d1eb | 5893 | macro_build (NULL, "nop", ""); |
438c16b8 | 5894 | } |
67c0d1eb | 5895 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 5896 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 5897 | load_delay_nop (); |
67c0d1eb | 5898 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 5899 | BFD_RELOC_LO16); |
4d7206a2 | 5900 | relax_end (); |
438c16b8 | 5901 | |
f5040a92 AO |
5902 | if (ex.X_add_number != 0) |
5903 | { | |
5904 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
5905 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5906 | ex.X_op = O_constant; | |
67c0d1eb RS |
5907 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
5908 | BFD_RELOC_LO16); | |
f5040a92 | 5909 | } |
252b5132 RH |
5910 | } |
5911 | } | |
252b5132 RH |
5912 | else |
5913 | abort (); | |
8fc2e39e | 5914 | |
741fe287 | 5915 | if (!mips_opts.at && *used_at == 1) |
8fc2e39e | 5916 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
5917 | } |
5918 | ||
ea1fb5dc RS |
5919 | /* Move the contents of register SOURCE into register DEST. */ |
5920 | ||
5921 | static void | |
67c0d1eb | 5922 | move_register (int dest, int source) |
ea1fb5dc | 5923 | { |
df58fc94 RS |
5924 | /* Prefer to use a 16-bit microMIPS instruction unless the previous |
5925 | instruction specifically requires a 32-bit one. */ | |
5926 | if (mips_opts.micromips | |
5927 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
5928 | macro_build (NULL, "move", "mp,mj", dest, source ); | |
5929 | else | |
5930 | macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", | |
5931 | dest, source, 0); | |
ea1fb5dc RS |
5932 | } |
5933 | ||
4d7206a2 | 5934 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
5935 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
5936 | The two alternatives are: | |
4d7206a2 RS |
5937 | |
5938 | Global symbol Local sybmol | |
5939 | ------------- ------------ | |
5940 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
5941 | ... ... | |
5942 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
5943 | ||
5944 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
5945 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
5946 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
5947 | |
5948 | static void | |
67c0d1eb | 5949 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
5950 | { |
5951 | expressionS global; | |
5952 | ||
5953 | global = *local; | |
5954 | global.X_add_number = 0; | |
5955 | ||
5956 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
5957 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
5958 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 5959 | relax_switch (); |
67c0d1eb RS |
5960 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
5961 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
5962 | relax_end (); |
5963 | } | |
5964 | ||
5965 | static void | |
67c0d1eb | 5966 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
5967 | { |
5968 | expressionS global; | |
5969 | ||
5970 | global.X_op = O_constant; | |
5971 | global.X_op_symbol = NULL; | |
5972 | global.X_add_symbol = NULL; | |
5973 | global.X_add_number = local->X_add_number; | |
5974 | ||
5975 | relax_start (local->X_add_symbol); | |
67c0d1eb | 5976 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
5977 | dest, dest, BFD_RELOC_LO16); |
5978 | relax_switch (); | |
67c0d1eb | 5979 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
5980 | relax_end (); |
5981 | } | |
5982 | ||
f6a22291 MR |
5983 | static void |
5984 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
5985 | { | |
5986 | expressionS global; | |
5987 | int hold_mips_optimize; | |
5988 | ||
5989 | global.X_op = O_constant; | |
5990 | global.X_op_symbol = NULL; | |
5991 | global.X_add_symbol = NULL; | |
5992 | global.X_add_number = local->X_add_number; | |
5993 | ||
5994 | relax_start (local->X_add_symbol); | |
5995 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
5996 | relax_switch (); | |
5997 | /* Set mips_optimize around the lui instruction to avoid | |
5998 | inserting an unnecessary nop after the lw. */ | |
5999 | hold_mips_optimize = mips_optimize; | |
6000 | mips_optimize = 2; | |
6001 | macro_build_lui (&global, tmp); | |
6002 | mips_optimize = hold_mips_optimize; | |
6003 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
6004 | relax_end (); | |
6005 | ||
6006 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
6007 | } | |
6008 | ||
df58fc94 RS |
6009 | /* Emit a sequence of instructions to emulate a branch likely operation. |
6010 | BR is an ordinary branch corresponding to one to be emulated. BRNEG | |
6011 | is its complementing branch with the original condition negated. | |
6012 | CALL is set if the original branch specified the link operation. | |
6013 | EP, FMT, SREG and TREG specify the usual macro_build() parameters. | |
6014 | ||
6015 | Code like this is produced in the noreorder mode: | |
6016 | ||
6017 | BRNEG <args>, 1f | |
6018 | nop | |
6019 | b <sym> | |
6020 | delay slot (executed only if branch taken) | |
6021 | 1: | |
6022 | ||
6023 | or, if CALL is set: | |
6024 | ||
6025 | BRNEG <args>, 1f | |
6026 | nop | |
6027 | bal <sym> | |
6028 | delay slot (executed only if branch taken) | |
6029 | 1: | |
6030 | ||
6031 | In the reorder mode the delay slot would be filled with a nop anyway, | |
6032 | so code produced is simply: | |
6033 | ||
6034 | BR <args>, <sym> | |
6035 | nop | |
6036 | ||
6037 | This function is used when producing code for the microMIPS ASE that | |
6038 | does not implement branch likely instructions in hardware. */ | |
6039 | ||
6040 | static void | |
6041 | macro_build_branch_likely (const char *br, const char *brneg, | |
6042 | int call, expressionS *ep, const char *fmt, | |
6043 | unsigned int sreg, unsigned int treg) | |
6044 | { | |
6045 | int noreorder = mips_opts.noreorder; | |
6046 | expressionS expr1; | |
6047 | ||
6048 | gas_assert (mips_opts.micromips); | |
6049 | start_noreorder (); | |
6050 | if (noreorder) | |
6051 | { | |
6052 | micromips_label_expr (&expr1); | |
6053 | macro_build (&expr1, brneg, fmt, sreg, treg); | |
6054 | macro_build (NULL, "nop", ""); | |
6055 | macro_build (ep, call ? "bal" : "b", "p"); | |
6056 | ||
6057 | /* Set to true so that append_insn adds a label. */ | |
6058 | emit_branch_likely_macro = TRUE; | |
6059 | } | |
6060 | else | |
6061 | { | |
6062 | macro_build (ep, br, fmt, sreg, treg); | |
6063 | macro_build (NULL, "nop", ""); | |
6064 | } | |
6065 | end_noreorder (); | |
6066 | } | |
6067 | ||
6068 | /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as | |
6069 | the condition code tested. EP specifies the branch target. */ | |
6070 | ||
6071 | static void | |
6072 | macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc) | |
6073 | { | |
6074 | const int call = 0; | |
6075 | const char *brneg; | |
6076 | const char *br; | |
6077 | ||
6078 | switch (type) | |
6079 | { | |
6080 | case M_BC1FL: | |
6081 | br = "bc1f"; | |
6082 | brneg = "bc1t"; | |
6083 | break; | |
6084 | case M_BC1TL: | |
6085 | br = "bc1t"; | |
6086 | brneg = "bc1f"; | |
6087 | break; | |
6088 | case M_BC2FL: | |
6089 | br = "bc2f"; | |
6090 | brneg = "bc2t"; | |
6091 | break; | |
6092 | case M_BC2TL: | |
6093 | br = "bc2t"; | |
6094 | brneg = "bc2f"; | |
6095 | break; | |
6096 | default: | |
6097 | abort (); | |
6098 | } | |
6099 | macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO); | |
6100 | } | |
6101 | ||
6102 | /* Emit a two-argument branch macro specified by TYPE, using SREG as | |
6103 | the register tested. EP specifies the branch target. */ | |
6104 | ||
6105 | static void | |
6106 | macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg) | |
6107 | { | |
6108 | const char *brneg = NULL; | |
6109 | const char *br; | |
6110 | int call = 0; | |
6111 | ||
6112 | switch (type) | |
6113 | { | |
6114 | case M_BGEZ: | |
6115 | br = "bgez"; | |
6116 | break; | |
6117 | case M_BGEZL: | |
6118 | br = mips_opts.micromips ? "bgez" : "bgezl"; | |
6119 | brneg = "bltz"; | |
6120 | break; | |
6121 | case M_BGEZALL: | |
6122 | gas_assert (mips_opts.micromips); | |
6123 | br = "bgezals"; | |
6124 | brneg = "bltz"; | |
6125 | call = 1; | |
6126 | break; | |
6127 | case M_BGTZ: | |
6128 | br = "bgtz"; | |
6129 | break; | |
6130 | case M_BGTZL: | |
6131 | br = mips_opts.micromips ? "bgtz" : "bgtzl"; | |
6132 | brneg = "blez"; | |
6133 | break; | |
6134 | case M_BLEZ: | |
6135 | br = "blez"; | |
6136 | break; | |
6137 | case M_BLEZL: | |
6138 | br = mips_opts.micromips ? "blez" : "blezl"; | |
6139 | brneg = "bgtz"; | |
6140 | break; | |
6141 | case M_BLTZ: | |
6142 | br = "bltz"; | |
6143 | break; | |
6144 | case M_BLTZL: | |
6145 | br = mips_opts.micromips ? "bltz" : "bltzl"; | |
6146 | brneg = "bgez"; | |
6147 | break; | |
6148 | case M_BLTZALL: | |
6149 | gas_assert (mips_opts.micromips); | |
6150 | br = "bltzals"; | |
6151 | brneg = "bgez"; | |
6152 | call = 1; | |
6153 | break; | |
6154 | default: | |
6155 | abort (); | |
6156 | } | |
6157 | if (mips_opts.micromips && brneg) | |
6158 | macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO); | |
6159 | else | |
6160 | macro_build (ep, br, "s,p", sreg); | |
6161 | } | |
6162 | ||
6163 | /* Emit a three-argument branch macro specified by TYPE, using SREG and | |
6164 | TREG as the registers tested. EP specifies the branch target. */ | |
6165 | ||
6166 | static void | |
6167 | macro_build_branch_rsrt (int type, expressionS *ep, | |
6168 | unsigned int sreg, unsigned int treg) | |
6169 | { | |
6170 | const char *brneg = NULL; | |
6171 | const int call = 0; | |
6172 | const char *br; | |
6173 | ||
6174 | switch (type) | |
6175 | { | |
6176 | case M_BEQ: | |
6177 | case M_BEQ_I: | |
6178 | br = "beq"; | |
6179 | break; | |
6180 | case M_BEQL: | |
6181 | case M_BEQL_I: | |
6182 | br = mips_opts.micromips ? "beq" : "beql"; | |
6183 | brneg = "bne"; | |
6184 | break; | |
6185 | case M_BNE: | |
6186 | case M_BNE_I: | |
6187 | br = "bne"; | |
6188 | break; | |
6189 | case M_BNEL: | |
6190 | case M_BNEL_I: | |
6191 | br = mips_opts.micromips ? "bne" : "bnel"; | |
6192 | brneg = "beq"; | |
6193 | break; | |
6194 | default: | |
6195 | abort (); | |
6196 | } | |
6197 | if (mips_opts.micromips && brneg) | |
6198 | macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg); | |
6199 | else | |
6200 | macro_build (ep, br, "s,t,p", sreg, treg); | |
6201 | } | |
6202 | ||
252b5132 RH |
6203 | /* |
6204 | * Build macros | |
6205 | * This routine implements the seemingly endless macro or synthesized | |
6206 | * instructions and addressing modes in the mips assembly language. Many | |
6207 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 6208 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
6209 | * this verbose method. Others are not simple macros but are more like |
6210 | * optimizing code generation. | |
6211 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 6212 | * consecutively that would load AT with the upper half of the same address. |
252b5132 RH |
6213 | * The ensuing load upper instructions are ommited. This implies some kind |
6214 | * of global optimization. We currently only optimize within a single macro. | |
6215 | * For many of the load and store macros if the address is specified as a | |
6216 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
6217 | * first load register 'at' with zero and use it as the base register. The | |
6218 | * mips assembler simply uses register $zero. Just one tiny optimization | |
6219 | * we're missing. | |
6220 | */ | |
6221 | static void | |
17a2f251 | 6222 | macro (struct mips_cl_insn *ip) |
252b5132 | 6223 | { |
741fe287 MR |
6224 | unsigned int treg, sreg, dreg, breg; |
6225 | unsigned int tempreg; | |
252b5132 | 6226 | int mask; |
43841e91 | 6227 | int used_at = 0; |
df58fc94 | 6228 | expressionS label_expr; |
252b5132 | 6229 | expressionS expr1; |
df58fc94 | 6230 | expressionS *ep; |
252b5132 RH |
6231 | const char *s; |
6232 | const char *s2; | |
6233 | const char *fmt; | |
6234 | int likely = 0; | |
252b5132 | 6235 | int coproc = 0; |
df58fc94 | 6236 | int off12 = 0; |
1abe91b1 | 6237 | int call = 0; |
df58fc94 RS |
6238 | int jals = 0; |
6239 | int dbl = 0; | |
6240 | int imm = 0; | |
6241 | int ust = 0; | |
6242 | int lp = 0; | |
6243 | int ab = 0; | |
252b5132 | 6244 | int off; |
67c0d1eb | 6245 | offsetT maxnum; |
252b5132 | 6246 | bfd_reloc_code_real_type r; |
252b5132 RH |
6247 | int hold_mips_optimize; |
6248 | ||
9c2799c2 | 6249 | gas_assert (! mips_opts.mips16); |
252b5132 | 6250 | |
df58fc94 RS |
6251 | treg = EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); |
6252 | dreg = EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); | |
6253 | sreg = breg = EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); | |
252b5132 RH |
6254 | mask = ip->insn_mo->mask; |
6255 | ||
df58fc94 RS |
6256 | label_expr.X_op = O_constant; |
6257 | label_expr.X_op_symbol = NULL; | |
6258 | label_expr.X_add_symbol = NULL; | |
6259 | label_expr.X_add_number = 0; | |
6260 | ||
252b5132 RH |
6261 | expr1.X_op = O_constant; |
6262 | expr1.X_op_symbol = NULL; | |
6263 | expr1.X_add_symbol = NULL; | |
6264 | expr1.X_add_number = 1; | |
6265 | ||
6266 | switch (mask) | |
6267 | { | |
6268 | case M_DABS: | |
6269 | dbl = 1; | |
6270 | case M_ABS: | |
df58fc94 RS |
6271 | /* bgez $a0,1f |
6272 | move v0,$a0 | |
6273 | sub v0,$zero,$a0 | |
6274 | 1: | |
6275 | */ | |
252b5132 | 6276 | |
7d10b47d | 6277 | start_noreorder (); |
252b5132 | 6278 | |
df58fc94 RS |
6279 | if (mips_opts.micromips) |
6280 | micromips_label_expr (&label_expr); | |
6281 | else | |
6282 | label_expr.X_add_number = 8; | |
6283 | macro_build (&label_expr, "bgez", "s,p", sreg); | |
252b5132 | 6284 | if (dreg == sreg) |
a605d2b3 | 6285 | macro_build (NULL, "nop", ""); |
252b5132 | 6286 | else |
67c0d1eb RS |
6287 | move_register (dreg, sreg); |
6288 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); | |
df58fc94 RS |
6289 | if (mips_opts.micromips) |
6290 | micromips_add_label (); | |
252b5132 | 6291 | |
7d10b47d | 6292 | end_noreorder (); |
8fc2e39e | 6293 | break; |
252b5132 RH |
6294 | |
6295 | case M_ADD_I: | |
6296 | s = "addi"; | |
6297 | s2 = "add"; | |
6298 | goto do_addi; | |
6299 | case M_ADDU_I: | |
6300 | s = "addiu"; | |
6301 | s2 = "addu"; | |
6302 | goto do_addi; | |
6303 | case M_DADD_I: | |
6304 | dbl = 1; | |
6305 | s = "daddi"; | |
6306 | s2 = "dadd"; | |
df58fc94 RS |
6307 | if (!mips_opts.micromips) |
6308 | goto do_addi; | |
6309 | if (imm_expr.X_op == O_constant | |
6310 | && imm_expr.X_add_number >= -0x200 | |
6311 | && imm_expr.X_add_number < 0x200) | |
6312 | { | |
6313 | macro_build (NULL, s, "t,r,.", treg, sreg, imm_expr.X_add_number); | |
6314 | break; | |
6315 | } | |
6316 | goto do_addi_i; | |
252b5132 RH |
6317 | case M_DADDU_I: |
6318 | dbl = 1; | |
6319 | s = "daddiu"; | |
6320 | s2 = "daddu"; | |
6321 | do_addi: | |
6322 | if (imm_expr.X_op == O_constant | |
6323 | && imm_expr.X_add_number >= -0x8000 | |
6324 | && imm_expr.X_add_number < 0x8000) | |
6325 | { | |
67c0d1eb | 6326 | macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 6327 | break; |
252b5132 | 6328 | } |
df58fc94 | 6329 | do_addi_i: |
8fc2e39e | 6330 | used_at = 1; |
67c0d1eb RS |
6331 | load_register (AT, &imm_expr, dbl); |
6332 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
6333 | break; |
6334 | ||
6335 | case M_AND_I: | |
6336 | s = "andi"; | |
6337 | s2 = "and"; | |
6338 | goto do_bit; | |
6339 | case M_OR_I: | |
6340 | s = "ori"; | |
6341 | s2 = "or"; | |
6342 | goto do_bit; | |
6343 | case M_NOR_I: | |
6344 | s = ""; | |
6345 | s2 = "nor"; | |
6346 | goto do_bit; | |
6347 | case M_XOR_I: | |
6348 | s = "xori"; | |
6349 | s2 = "xor"; | |
6350 | do_bit: | |
6351 | if (imm_expr.X_op == O_constant | |
6352 | && imm_expr.X_add_number >= 0 | |
6353 | && imm_expr.X_add_number < 0x10000) | |
6354 | { | |
6355 | if (mask != M_NOR_I) | |
67c0d1eb | 6356 | macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
6357 | else |
6358 | { | |
67c0d1eb RS |
6359 | macro_build (&imm_expr, "ori", "t,r,i", |
6360 | treg, sreg, BFD_RELOC_LO16); | |
6361 | macro_build (NULL, "nor", "d,v,t", treg, treg, 0); | |
252b5132 | 6362 | } |
8fc2e39e | 6363 | break; |
252b5132 RH |
6364 | } |
6365 | ||
8fc2e39e | 6366 | used_at = 1; |
67c0d1eb RS |
6367 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
6368 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
6369 | break; |
6370 | ||
8b082fb1 TS |
6371 | case M_BALIGN: |
6372 | switch (imm_expr.X_add_number) | |
6373 | { | |
6374 | case 0: | |
6375 | macro_build (NULL, "nop", ""); | |
6376 | break; | |
6377 | case 2: | |
6378 | macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg); | |
6379 | break; | |
6380 | default: | |
6381 | macro_build (NULL, "balign", "t,s,2", treg, sreg, | |
90ecf173 | 6382 | (int) imm_expr.X_add_number); |
8b082fb1 TS |
6383 | break; |
6384 | } | |
6385 | break; | |
6386 | ||
df58fc94 RS |
6387 | case M_BC1FL: |
6388 | case M_BC1TL: | |
6389 | case M_BC2FL: | |
6390 | case M_BC2TL: | |
6391 | gas_assert (mips_opts.micromips); | |
6392 | macro_build_branch_ccl (mask, &offset_expr, | |
6393 | EXTRACT_OPERAND (1, BCC, *ip)); | |
6394 | break; | |
6395 | ||
252b5132 | 6396 | case M_BEQ_I: |
252b5132 | 6397 | case M_BEQL_I: |
252b5132 | 6398 | case M_BNE_I: |
252b5132 | 6399 | case M_BNEL_I: |
252b5132 | 6400 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
df58fc94 RS |
6401 | treg = 0; |
6402 | else | |
252b5132 | 6403 | { |
df58fc94 RS |
6404 | treg = AT; |
6405 | used_at = 1; | |
6406 | load_register (treg, &imm_expr, HAVE_64BIT_GPRS); | |
252b5132 | 6407 | } |
df58fc94 RS |
6408 | /* Fall through. */ |
6409 | case M_BEQL: | |
6410 | case M_BNEL: | |
6411 | macro_build_branch_rsrt (mask, &offset_expr, sreg, treg); | |
252b5132 RH |
6412 | break; |
6413 | ||
6414 | case M_BGEL: | |
6415 | likely = 1; | |
6416 | case M_BGE: | |
6417 | if (treg == 0) | |
df58fc94 RS |
6418 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, sreg); |
6419 | else if (sreg == 0) | |
6420 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, treg); | |
6421 | else | |
252b5132 | 6422 | { |
df58fc94 RS |
6423 | used_at = 1; |
6424 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); | |
6425 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6426 | &offset_expr, AT, ZERO); | |
252b5132 | 6427 | } |
df58fc94 RS |
6428 | break; |
6429 | ||
6430 | case M_BGEZL: | |
6431 | case M_BGEZALL: | |
6432 | case M_BGTZL: | |
6433 | case M_BLEZL: | |
6434 | case M_BLTZL: | |
6435 | case M_BLTZALL: | |
6436 | macro_build_branch_rs (mask, &offset_expr, sreg); | |
252b5132 RH |
6437 | break; |
6438 | ||
6439 | case M_BGTL_I: | |
6440 | likely = 1; | |
6441 | case M_BGT_I: | |
90ecf173 | 6442 | /* Check for > max integer. */ |
252b5132 | 6443 | maxnum = 0x7fffffff; |
ca4e0257 | 6444 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
6445 | { |
6446 | maxnum <<= 16; | |
6447 | maxnum |= 0xffff; | |
6448 | maxnum <<= 16; | |
6449 | maxnum |= 0xffff; | |
6450 | } | |
6451 | if (imm_expr.X_op == O_constant | |
6452 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 6453 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
6454 | { |
6455 | do_false: | |
90ecf173 | 6456 | /* Result is always false. */ |
252b5132 | 6457 | if (! likely) |
a605d2b3 | 6458 | macro_build (NULL, "nop", ""); |
252b5132 | 6459 | else |
df58fc94 | 6460 | macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO); |
8fc2e39e | 6461 | break; |
252b5132 RH |
6462 | } |
6463 | if (imm_expr.X_op != O_constant) | |
6464 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 6465 | ++imm_expr.X_add_number; |
252b5132 RH |
6466 | /* FALLTHROUGH */ |
6467 | case M_BGE_I: | |
6468 | case M_BGEL_I: | |
6469 | if (mask == M_BGEL_I) | |
6470 | likely = 1; | |
6471 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6472 | { | |
df58fc94 RS |
6473 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, |
6474 | &offset_expr, sreg); | |
8fc2e39e | 6475 | break; |
252b5132 RH |
6476 | } |
6477 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
6478 | { | |
df58fc94 RS |
6479 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, |
6480 | &offset_expr, sreg); | |
8fc2e39e | 6481 | break; |
252b5132 RH |
6482 | } |
6483 | maxnum = 0x7fffffff; | |
ca4e0257 | 6484 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
6485 | { |
6486 | maxnum <<= 16; | |
6487 | maxnum |= 0xffff; | |
6488 | maxnum <<= 16; | |
6489 | maxnum |= 0xffff; | |
6490 | } | |
6491 | maxnum = - maxnum - 1; | |
6492 | if (imm_expr.X_op == O_constant | |
6493 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 6494 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
6495 | { |
6496 | do_true: | |
6497 | /* result is always true */ | |
6498 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
67c0d1eb | 6499 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 6500 | break; |
252b5132 | 6501 | } |
8fc2e39e | 6502 | used_at = 1; |
67c0d1eb | 6503 | set_at (sreg, 0); |
df58fc94 RS |
6504 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
6505 | &offset_expr, AT, ZERO); | |
252b5132 RH |
6506 | break; |
6507 | ||
6508 | case M_BGEUL: | |
6509 | likely = 1; | |
6510 | case M_BGEU: | |
6511 | if (treg == 0) | |
6512 | goto do_true; | |
df58fc94 RS |
6513 | else if (sreg == 0) |
6514 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6515 | &offset_expr, ZERO, treg); | |
6516 | else | |
252b5132 | 6517 | { |
df58fc94 RS |
6518 | used_at = 1; |
6519 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); | |
6520 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6521 | &offset_expr, AT, ZERO); | |
252b5132 | 6522 | } |
252b5132 RH |
6523 | break; |
6524 | ||
6525 | case M_BGTUL_I: | |
6526 | likely = 1; | |
6527 | case M_BGTU_I: | |
6528 | if (sreg == 0 | |
ca4e0257 | 6529 | || (HAVE_32BIT_GPRS |
252b5132 | 6530 | && imm_expr.X_op == O_constant |
f01dc953 | 6531 | && imm_expr.X_add_number == -1)) |
252b5132 RH |
6532 | goto do_false; |
6533 | if (imm_expr.X_op != O_constant) | |
6534 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 6535 | ++imm_expr.X_add_number; |
252b5132 RH |
6536 | /* FALLTHROUGH */ |
6537 | case M_BGEU_I: | |
6538 | case M_BGEUL_I: | |
6539 | if (mask == M_BGEUL_I) | |
6540 | likely = 1; | |
6541 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6542 | goto do_true; | |
df58fc94 RS |
6543 | else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
6544 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6545 | &offset_expr, sreg, ZERO); | |
6546 | else | |
252b5132 | 6547 | { |
df58fc94 RS |
6548 | used_at = 1; |
6549 | set_at (sreg, 1); | |
6550 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6551 | &offset_expr, AT, ZERO); | |
252b5132 | 6552 | } |
252b5132 RH |
6553 | break; |
6554 | ||
6555 | case M_BGTL: | |
6556 | likely = 1; | |
6557 | case M_BGT: | |
6558 | if (treg == 0) | |
df58fc94 RS |
6559 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, sreg); |
6560 | else if (sreg == 0) | |
6561 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, treg); | |
6562 | else | |
252b5132 | 6563 | { |
df58fc94 RS |
6564 | used_at = 1; |
6565 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); | |
6566 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6567 | &offset_expr, AT, ZERO); | |
252b5132 | 6568 | } |
252b5132 RH |
6569 | break; |
6570 | ||
6571 | case M_BGTUL: | |
6572 | likely = 1; | |
6573 | case M_BGTU: | |
6574 | if (treg == 0) | |
df58fc94 RS |
6575 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
6576 | &offset_expr, sreg, ZERO); | |
6577 | else if (sreg == 0) | |
6578 | goto do_false; | |
6579 | else | |
252b5132 | 6580 | { |
df58fc94 RS |
6581 | used_at = 1; |
6582 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); | |
6583 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6584 | &offset_expr, AT, ZERO); | |
252b5132 | 6585 | } |
252b5132 RH |
6586 | break; |
6587 | ||
6588 | case M_BLEL: | |
6589 | likely = 1; | |
6590 | case M_BLE: | |
6591 | if (treg == 0) | |
df58fc94 RS |
6592 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg); |
6593 | else if (sreg == 0) | |
6594 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, treg); | |
6595 | else | |
252b5132 | 6596 | { |
df58fc94 RS |
6597 | used_at = 1; |
6598 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); | |
6599 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6600 | &offset_expr, AT, ZERO); | |
252b5132 | 6601 | } |
252b5132 RH |
6602 | break; |
6603 | ||
6604 | case M_BLEL_I: | |
6605 | likely = 1; | |
6606 | case M_BLE_I: | |
6607 | maxnum = 0x7fffffff; | |
ca4e0257 | 6608 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
6609 | { |
6610 | maxnum <<= 16; | |
6611 | maxnum |= 0xffff; | |
6612 | maxnum <<= 16; | |
6613 | maxnum |= 0xffff; | |
6614 | } | |
6615 | if (imm_expr.X_op == O_constant | |
6616 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 6617 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
6618 | goto do_true; |
6619 | if (imm_expr.X_op != O_constant) | |
6620 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 6621 | ++imm_expr.X_add_number; |
252b5132 RH |
6622 | /* FALLTHROUGH */ |
6623 | case M_BLT_I: | |
6624 | case M_BLTL_I: | |
6625 | if (mask == M_BLTL_I) | |
6626 | likely = 1; | |
6627 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
df58fc94 RS |
6628 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg); |
6629 | else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
6630 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg); | |
6631 | else | |
252b5132 | 6632 | { |
df58fc94 RS |
6633 | used_at = 1; |
6634 | set_at (sreg, 0); | |
6635 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6636 | &offset_expr, AT, ZERO); | |
252b5132 | 6637 | } |
252b5132 RH |
6638 | break; |
6639 | ||
6640 | case M_BLEUL: | |
6641 | likely = 1; | |
6642 | case M_BLEU: | |
6643 | if (treg == 0) | |
df58fc94 RS |
6644 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
6645 | &offset_expr, sreg, ZERO); | |
6646 | else if (sreg == 0) | |
6647 | goto do_true; | |
6648 | else | |
252b5132 | 6649 | { |
df58fc94 RS |
6650 | used_at = 1; |
6651 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); | |
6652 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6653 | &offset_expr, AT, ZERO); | |
252b5132 | 6654 | } |
252b5132 RH |
6655 | break; |
6656 | ||
6657 | case M_BLEUL_I: | |
6658 | likely = 1; | |
6659 | case M_BLEU_I: | |
6660 | if (sreg == 0 | |
ca4e0257 | 6661 | || (HAVE_32BIT_GPRS |
252b5132 | 6662 | && imm_expr.X_op == O_constant |
f01dc953 | 6663 | && imm_expr.X_add_number == -1)) |
252b5132 RH |
6664 | goto do_true; |
6665 | if (imm_expr.X_op != O_constant) | |
6666 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 6667 | ++imm_expr.X_add_number; |
252b5132 RH |
6668 | /* FALLTHROUGH */ |
6669 | case M_BLTU_I: | |
6670 | case M_BLTUL_I: | |
6671 | if (mask == M_BLTUL_I) | |
6672 | likely = 1; | |
6673 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6674 | goto do_false; | |
df58fc94 RS |
6675 | else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
6676 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6677 | &offset_expr, sreg, ZERO); | |
6678 | else | |
252b5132 | 6679 | { |
df58fc94 RS |
6680 | used_at = 1; |
6681 | set_at (sreg, 1); | |
6682 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6683 | &offset_expr, AT, ZERO); | |
252b5132 | 6684 | } |
252b5132 RH |
6685 | break; |
6686 | ||
6687 | case M_BLTL: | |
6688 | likely = 1; | |
6689 | case M_BLT: | |
6690 | if (treg == 0) | |
df58fc94 RS |
6691 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg); |
6692 | else if (sreg == 0) | |
6693 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, treg); | |
6694 | else | |
252b5132 | 6695 | { |
df58fc94 RS |
6696 | used_at = 1; |
6697 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); | |
6698 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6699 | &offset_expr, AT, ZERO); | |
252b5132 | 6700 | } |
252b5132 RH |
6701 | break; |
6702 | ||
6703 | case M_BLTUL: | |
6704 | likely = 1; | |
6705 | case M_BLTU: | |
6706 | if (treg == 0) | |
6707 | goto do_false; | |
df58fc94 RS |
6708 | else if (sreg == 0) |
6709 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6710 | &offset_expr, ZERO, treg); | |
6711 | else | |
252b5132 | 6712 | { |
df58fc94 RS |
6713 | used_at = 1; |
6714 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); | |
6715 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6716 | &offset_expr, AT, ZERO); | |
252b5132 | 6717 | } |
252b5132 RH |
6718 | break; |
6719 | ||
5f74bc13 CD |
6720 | case M_DEXT: |
6721 | { | |
d5818fca MR |
6722 | /* Use unsigned arithmetic. */ |
6723 | addressT pos; | |
6724 | addressT size; | |
5f74bc13 | 6725 | |
90ecf173 | 6726 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) |
5f74bc13 CD |
6727 | { |
6728 | as_bad (_("Unsupported large constant")); | |
6729 | pos = size = 1; | |
6730 | } | |
6731 | else | |
6732 | { | |
d5818fca MR |
6733 | pos = imm_expr.X_add_number; |
6734 | size = imm2_expr.X_add_number; | |
5f74bc13 CD |
6735 | } |
6736 | ||
6737 | if (pos > 63) | |
6738 | { | |
d5818fca | 6739 | as_bad (_("Improper position (%lu)"), (unsigned long) pos); |
5f74bc13 CD |
6740 | pos = 1; |
6741 | } | |
90ecf173 | 6742 | if (size == 0 || size > 64 || (pos + size - 1) > 63) |
5f74bc13 CD |
6743 | { |
6744 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
d5818fca | 6745 | (unsigned long) size, (unsigned long) pos); |
5f74bc13 CD |
6746 | size = 1; |
6747 | } | |
6748 | ||
6749 | if (size <= 32 && pos < 32) | |
6750 | { | |
6751 | s = "dext"; | |
6752 | fmt = "t,r,+A,+C"; | |
6753 | } | |
6754 | else if (size <= 32) | |
6755 | { | |
6756 | s = "dextu"; | |
6757 | fmt = "t,r,+E,+H"; | |
6758 | } | |
6759 | else | |
6760 | { | |
6761 | s = "dextm"; | |
6762 | fmt = "t,r,+A,+G"; | |
6763 | } | |
d5818fca MR |
6764 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos, |
6765 | (int) (size - 1)); | |
5f74bc13 | 6766 | } |
8fc2e39e | 6767 | break; |
5f74bc13 CD |
6768 | |
6769 | case M_DINS: | |
6770 | { | |
d5818fca MR |
6771 | /* Use unsigned arithmetic. */ |
6772 | addressT pos; | |
6773 | addressT size; | |
5f74bc13 | 6774 | |
90ecf173 | 6775 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) |
5f74bc13 CD |
6776 | { |
6777 | as_bad (_("Unsupported large constant")); | |
6778 | pos = size = 1; | |
6779 | } | |
6780 | else | |
6781 | { | |
d5818fca MR |
6782 | pos = imm_expr.X_add_number; |
6783 | size = imm2_expr.X_add_number; | |
5f74bc13 CD |
6784 | } |
6785 | ||
6786 | if (pos > 63) | |
6787 | { | |
d5818fca | 6788 | as_bad (_("Improper position (%lu)"), (unsigned long) pos); |
5f74bc13 CD |
6789 | pos = 1; |
6790 | } | |
90ecf173 | 6791 | if (size == 0 || size > 64 || (pos + size - 1) > 63) |
5f74bc13 CD |
6792 | { |
6793 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
d5818fca | 6794 | (unsigned long) size, (unsigned long) pos); |
5f74bc13 CD |
6795 | size = 1; |
6796 | } | |
6797 | ||
6798 | if (pos < 32 && (pos + size - 1) < 32) | |
6799 | { | |
6800 | s = "dins"; | |
6801 | fmt = "t,r,+A,+B"; | |
6802 | } | |
6803 | else if (pos >= 32) | |
6804 | { | |
6805 | s = "dinsu"; | |
6806 | fmt = "t,r,+E,+F"; | |
6807 | } | |
6808 | else | |
6809 | { | |
6810 | s = "dinsm"; | |
6811 | fmt = "t,r,+A,+F"; | |
6812 | } | |
750bdd57 AS |
6813 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos, |
6814 | (int) (pos + size - 1)); | |
5f74bc13 | 6815 | } |
8fc2e39e | 6816 | break; |
5f74bc13 | 6817 | |
252b5132 RH |
6818 | case M_DDIV_3: |
6819 | dbl = 1; | |
6820 | case M_DIV_3: | |
6821 | s = "mflo"; | |
6822 | goto do_div3; | |
6823 | case M_DREM_3: | |
6824 | dbl = 1; | |
6825 | case M_REM_3: | |
6826 | s = "mfhi"; | |
6827 | do_div3: | |
6828 | if (treg == 0) | |
6829 | { | |
6830 | as_warn (_("Divide by zero.")); | |
6831 | if (mips_trap) | |
df58fc94 | 6832 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 6833 | else |
df58fc94 | 6834 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 6835 | break; |
252b5132 RH |
6836 | } |
6837 | ||
7d10b47d | 6838 | start_noreorder (); |
252b5132 RH |
6839 | if (mips_trap) |
6840 | { | |
df58fc94 | 6841 | macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7); |
67c0d1eb | 6842 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
252b5132 RH |
6843 | } |
6844 | else | |
6845 | { | |
df58fc94 RS |
6846 | if (mips_opts.micromips) |
6847 | micromips_label_expr (&label_expr); | |
6848 | else | |
6849 | label_expr.X_add_number = 8; | |
6850 | macro_build (&label_expr, "bne", "s,t,p", treg, ZERO); | |
67c0d1eb | 6851 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
df58fc94 RS |
6852 | macro_build (NULL, "break", BRK_FMT, 7); |
6853 | if (mips_opts.micromips) | |
6854 | micromips_add_label (); | |
252b5132 RH |
6855 | } |
6856 | expr1.X_add_number = -1; | |
8fc2e39e | 6857 | used_at = 1; |
f6a22291 | 6858 | load_register (AT, &expr1, dbl); |
df58fc94 RS |
6859 | if (mips_opts.micromips) |
6860 | micromips_label_expr (&label_expr); | |
6861 | else | |
6862 | label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); | |
6863 | macro_build (&label_expr, "bne", "s,t,p", treg, AT); | |
252b5132 RH |
6864 | if (dbl) |
6865 | { | |
6866 | expr1.X_add_number = 1; | |
f6a22291 | 6867 | load_register (AT, &expr1, dbl); |
df58fc94 | 6868 | macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31); |
252b5132 RH |
6869 | } |
6870 | else | |
6871 | { | |
6872 | expr1.X_add_number = 0x80000000; | |
df58fc94 | 6873 | macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16); |
252b5132 RH |
6874 | } |
6875 | if (mips_trap) | |
6876 | { | |
df58fc94 | 6877 | macro_build (NULL, "teq", TRAP_FMT, sreg, AT, 6); |
252b5132 RH |
6878 | /* We want to close the noreorder block as soon as possible, so |
6879 | that later insns are available for delay slot filling. */ | |
7d10b47d | 6880 | end_noreorder (); |
252b5132 RH |
6881 | } |
6882 | else | |
6883 | { | |
df58fc94 RS |
6884 | if (mips_opts.micromips) |
6885 | micromips_label_expr (&label_expr); | |
6886 | else | |
6887 | label_expr.X_add_number = 8; | |
6888 | macro_build (&label_expr, "bne", "s,t,p", sreg, AT); | |
a605d2b3 | 6889 | macro_build (NULL, "nop", ""); |
252b5132 RH |
6890 | |
6891 | /* We want to close the noreorder block as soon as possible, so | |
6892 | that later insns are available for delay slot filling. */ | |
7d10b47d | 6893 | end_noreorder (); |
252b5132 | 6894 | |
df58fc94 | 6895 | macro_build (NULL, "break", BRK_FMT, 6); |
252b5132 | 6896 | } |
df58fc94 RS |
6897 | if (mips_opts.micromips) |
6898 | micromips_add_label (); | |
6899 | macro_build (NULL, s, MFHL_FMT, dreg); | |
252b5132 RH |
6900 | break; |
6901 | ||
6902 | case M_DIV_3I: | |
6903 | s = "div"; | |
6904 | s2 = "mflo"; | |
6905 | goto do_divi; | |
6906 | case M_DIVU_3I: | |
6907 | s = "divu"; | |
6908 | s2 = "mflo"; | |
6909 | goto do_divi; | |
6910 | case M_REM_3I: | |
6911 | s = "div"; | |
6912 | s2 = "mfhi"; | |
6913 | goto do_divi; | |
6914 | case M_REMU_3I: | |
6915 | s = "divu"; | |
6916 | s2 = "mfhi"; | |
6917 | goto do_divi; | |
6918 | case M_DDIV_3I: | |
6919 | dbl = 1; | |
6920 | s = "ddiv"; | |
6921 | s2 = "mflo"; | |
6922 | goto do_divi; | |
6923 | case M_DDIVU_3I: | |
6924 | dbl = 1; | |
6925 | s = "ddivu"; | |
6926 | s2 = "mflo"; | |
6927 | goto do_divi; | |
6928 | case M_DREM_3I: | |
6929 | dbl = 1; | |
6930 | s = "ddiv"; | |
6931 | s2 = "mfhi"; | |
6932 | goto do_divi; | |
6933 | case M_DREMU_3I: | |
6934 | dbl = 1; | |
6935 | s = "ddivu"; | |
6936 | s2 = "mfhi"; | |
6937 | do_divi: | |
6938 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6939 | { | |
6940 | as_warn (_("Divide by zero.")); | |
6941 | if (mips_trap) | |
df58fc94 | 6942 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 6943 | else |
df58fc94 | 6944 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 6945 | break; |
252b5132 RH |
6946 | } |
6947 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
6948 | { | |
6949 | if (strcmp (s2, "mflo") == 0) | |
67c0d1eb | 6950 | move_register (dreg, sreg); |
252b5132 | 6951 | else |
c80c840e | 6952 | move_register (dreg, ZERO); |
8fc2e39e | 6953 | break; |
252b5132 RH |
6954 | } |
6955 | if (imm_expr.X_op == O_constant | |
6956 | && imm_expr.X_add_number == -1 | |
6957 | && s[strlen (s) - 1] != 'u') | |
6958 | { | |
6959 | if (strcmp (s2, "mflo") == 0) | |
6960 | { | |
67c0d1eb | 6961 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg); |
252b5132 RH |
6962 | } |
6963 | else | |
c80c840e | 6964 | move_register (dreg, ZERO); |
8fc2e39e | 6965 | break; |
252b5132 RH |
6966 | } |
6967 | ||
8fc2e39e | 6968 | used_at = 1; |
67c0d1eb RS |
6969 | load_register (AT, &imm_expr, dbl); |
6970 | macro_build (NULL, s, "z,s,t", sreg, AT); | |
df58fc94 | 6971 | macro_build (NULL, s2, MFHL_FMT, dreg); |
252b5132 RH |
6972 | break; |
6973 | ||
6974 | case M_DIVU_3: | |
6975 | s = "divu"; | |
6976 | s2 = "mflo"; | |
6977 | goto do_divu3; | |
6978 | case M_REMU_3: | |
6979 | s = "divu"; | |
6980 | s2 = "mfhi"; | |
6981 | goto do_divu3; | |
6982 | case M_DDIVU_3: | |
6983 | s = "ddivu"; | |
6984 | s2 = "mflo"; | |
6985 | goto do_divu3; | |
6986 | case M_DREMU_3: | |
6987 | s = "ddivu"; | |
6988 | s2 = "mfhi"; | |
6989 | do_divu3: | |
7d10b47d | 6990 | start_noreorder (); |
252b5132 RH |
6991 | if (mips_trap) |
6992 | { | |
df58fc94 | 6993 | macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7); |
67c0d1eb | 6994 | macro_build (NULL, s, "z,s,t", sreg, treg); |
252b5132 RH |
6995 | /* We want to close the noreorder block as soon as possible, so |
6996 | that later insns are available for delay slot filling. */ | |
7d10b47d | 6997 | end_noreorder (); |
252b5132 RH |
6998 | } |
6999 | else | |
7000 | { | |
df58fc94 RS |
7001 | if (mips_opts.micromips) |
7002 | micromips_label_expr (&label_expr); | |
7003 | else | |
7004 | label_expr.X_add_number = 8; | |
7005 | macro_build (&label_expr, "bne", "s,t,p", treg, ZERO); | |
67c0d1eb | 7006 | macro_build (NULL, s, "z,s,t", sreg, treg); |
252b5132 RH |
7007 | |
7008 | /* We want to close the noreorder block as soon as possible, so | |
7009 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7010 | end_noreorder (); |
df58fc94 RS |
7011 | macro_build (NULL, "break", BRK_FMT, 7); |
7012 | if (mips_opts.micromips) | |
7013 | micromips_add_label (); | |
252b5132 | 7014 | } |
df58fc94 | 7015 | macro_build (NULL, s2, MFHL_FMT, dreg); |
8fc2e39e | 7016 | break; |
252b5132 | 7017 | |
1abe91b1 MR |
7018 | case M_DLCA_AB: |
7019 | dbl = 1; | |
7020 | case M_LCA_AB: | |
7021 | call = 1; | |
7022 | goto do_la; | |
252b5132 RH |
7023 | case M_DLA_AB: |
7024 | dbl = 1; | |
7025 | case M_LA_AB: | |
1abe91b1 | 7026 | do_la: |
252b5132 RH |
7027 | /* Load the address of a symbol into a register. If breg is not |
7028 | zero, we then add a base register to it. */ | |
7029 | ||
3bec30a8 TS |
7030 | if (dbl && HAVE_32BIT_GPRS) |
7031 | as_warn (_("dla used to load 32-bit register")); | |
7032 | ||
90ecf173 | 7033 | if (!dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
7034 | as_warn (_("la used to load 64-bit address")); |
7035 | ||
0c11417f MR |
7036 | if (offset_expr.X_op == O_constant |
7037 | && offset_expr.X_add_number >= -0x8000 | |
7038 | && offset_expr.X_add_number < 0x8000) | |
7039 | { | |
aed1a261 | 7040 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
17a2f251 | 7041 | "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7042 | break; |
0c11417f MR |
7043 | } |
7044 | ||
741fe287 | 7045 | if (mips_opts.at && (treg == breg)) |
afdbd6d0 CD |
7046 | { |
7047 | tempreg = AT; | |
7048 | used_at = 1; | |
7049 | } | |
7050 | else | |
7051 | { | |
7052 | tempreg = treg; | |
afdbd6d0 CD |
7053 | } |
7054 | ||
252b5132 RH |
7055 | if (offset_expr.X_op != O_symbol |
7056 | && offset_expr.X_op != O_constant) | |
7057 | { | |
f71d0d44 | 7058 | as_bad (_("Expression too complex")); |
252b5132 RH |
7059 | offset_expr.X_op = O_constant; |
7060 | } | |
7061 | ||
252b5132 | 7062 | if (offset_expr.X_op == O_constant) |
aed1a261 | 7063 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
7064 | else if (mips_pic == NO_PIC) |
7065 | { | |
d6bc6245 | 7066 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 7067 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
7068 | Otherwise we want |
7069 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
7070 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7071 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 7072 | so we may as well always use the latter form. |
76b3015f | 7073 | |
6caf9ef4 TS |
7074 | With 64bit address space and a usable $at we want |
7075 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
7076 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
7077 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
7078 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
7079 | dsll32 $tempreg,0 | |
7080 | daddu $tempreg,$tempreg,$at | |
7081 | ||
7082 | If $at is already in use, we use a path which is suboptimal | |
7083 | on superscalar processors. | |
7084 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
7085 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
7086 | dsll $tempreg,16 | |
7087 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
7088 | dsll $tempreg,16 | |
7089 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
7090 | ||
7091 | For GP relative symbols in 64bit address space we can use | |
7092 | the same sequence as in 32bit address space. */ | |
aed1a261 | 7093 | if (HAVE_64BIT_SYMBOLS) |
252b5132 | 7094 | { |
6caf9ef4 TS |
7095 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
7096 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
7097 | { | |
7098 | relax_start (offset_expr.X_add_symbol); | |
7099 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
7100 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
7101 | relax_switch (); | |
7102 | } | |
d6bc6245 | 7103 | |
741fe287 | 7104 | if (used_at == 0 && mips_opts.at) |
98d3f06f | 7105 | { |
df58fc94 | 7106 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 7107 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 7108 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 7109 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 7110 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7111 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 7112 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7113 | AT, AT, BFD_RELOC_LO16); |
df58fc94 | 7114 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb | 7115 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
98d3f06f KH |
7116 | used_at = 1; |
7117 | } | |
7118 | else | |
7119 | { | |
df58fc94 | 7120 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 7121 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 7122 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7123 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
df58fc94 | 7124 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 7125 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7126 | tempreg, tempreg, BFD_RELOC_HI16_S); |
df58fc94 | 7127 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 7128 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7129 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 7130 | } |
6caf9ef4 TS |
7131 | |
7132 | if (mips_relax.sequence) | |
7133 | relax_end (); | |
98d3f06f KH |
7134 | } |
7135 | else | |
7136 | { | |
7137 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 7138 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
98d3f06f | 7139 | { |
4d7206a2 | 7140 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7141 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7142 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 7143 | relax_switch (); |
98d3f06f | 7144 | } |
6943caf0 | 7145 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
f71d0d44 | 7146 | as_bad (_("Offset too large")); |
67c0d1eb RS |
7147 | macro_build_lui (&offset_expr, tempreg); |
7148 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
7149 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
7150 | if (mips_relax.sequence) |
7151 | relax_end (); | |
98d3f06f | 7152 | } |
252b5132 | 7153 | } |
0a44bf69 | 7154 | else if (!mips_big_got && !HAVE_NEWABI) |
252b5132 | 7155 | { |
9117d219 NC |
7156 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
7157 | ||
252b5132 RH |
7158 | /* If this is a reference to an external symbol, and there |
7159 | is no constant, we want | |
7160 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 7161 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 7162 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
7163 | For a local symbol, we want |
7164 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7165 | nop | |
7166 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7167 | ||
7168 | If we have a small constant, and this is a reference to | |
7169 | an external symbol, we want | |
7170 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7171 | nop | |
7172 | addiu $tempreg,$tempreg,<constant> | |
7173 | For a local symbol, we want the same instruction | |
7174 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
7175 | addiu instruction. | |
7176 | ||
7177 | If we have a large constant, and this is a reference to | |
7178 | an external symbol, we want | |
7179 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7180 | lui $at,<hiconstant> | |
7181 | addiu $at,$at,<loconstant> | |
7182 | addu $tempreg,$tempreg,$at | |
7183 | For a local symbol, we want the same instruction | |
7184 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 7185 | addiu instruction. |
ed6fb7bd SC |
7186 | */ |
7187 | ||
4d7206a2 | 7188 | if (offset_expr.X_add_number == 0) |
252b5132 | 7189 | { |
0a44bf69 RS |
7190 | if (mips_pic == SVR4_PIC |
7191 | && breg == 0 | |
7192 | && (call || tempreg == PIC_CALL_REG)) | |
4d7206a2 RS |
7193 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; |
7194 | ||
7195 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
7196 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7197 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 7198 | if (breg != 0) |
252b5132 RH |
7199 | { |
7200 | /* We're going to put in an addu instruction using | |
7201 | tempreg, so we may as well insert the nop right | |
7202 | now. */ | |
269137b2 | 7203 | load_delay_nop (); |
252b5132 | 7204 | } |
4d7206a2 | 7205 | relax_switch (); |
67c0d1eb RS |
7206 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7207 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 7208 | load_delay_nop (); |
67c0d1eb RS |
7209 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7210 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 7211 | relax_end (); |
252b5132 RH |
7212 | /* FIXME: If breg == 0, and the next instruction uses |
7213 | $tempreg, then if this variant case is used an extra | |
7214 | nop will be generated. */ | |
7215 | } | |
4d7206a2 RS |
7216 | else if (offset_expr.X_add_number >= -0x8000 |
7217 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 7218 | { |
67c0d1eb | 7219 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 7220 | load_delay_nop (); |
67c0d1eb | 7221 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
7222 | } |
7223 | else | |
7224 | { | |
4d7206a2 RS |
7225 | expr1.X_add_number = offset_expr.X_add_number; |
7226 | offset_expr.X_add_number = | |
7227 | ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
67c0d1eb | 7228 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 7229 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
7230 | /* If we are going to add in a base register, and the |
7231 | target register and the base register are the same, | |
7232 | then we are using AT as a temporary register. Since | |
7233 | we want to load the constant into AT, we add our | |
7234 | current AT (from the global offset table) and the | |
7235 | register into the register now, and pretend we were | |
7236 | not using a base register. */ | |
67c0d1eb | 7237 | if (breg == treg) |
252b5132 | 7238 | { |
269137b2 | 7239 | load_delay_nop (); |
67c0d1eb | 7240 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7241 | treg, AT, breg); |
252b5132 RH |
7242 | breg = 0; |
7243 | tempreg = treg; | |
252b5132 | 7244 | } |
f6a22291 | 7245 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
7246 | used_at = 1; |
7247 | } | |
7248 | } | |
0a44bf69 | 7249 | else if (!mips_big_got && HAVE_NEWABI) |
f5040a92 | 7250 | { |
67c0d1eb | 7251 | int add_breg_early = 0; |
f5040a92 AO |
7252 | |
7253 | /* If this is a reference to an external, and there is no | |
7254 | constant, or local symbol (*), with or without a | |
7255 | constant, we want | |
7256 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 7257 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
7258 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
7259 | ||
7260 | If we have a small constant, and this is a reference to | |
7261 | an external symbol, we want | |
7262 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
7263 | addiu $tempreg,$tempreg,<constant> | |
7264 | ||
7265 | If we have a large constant, and this is a reference to | |
7266 | an external symbol, we want | |
7267 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
7268 | lui $at,<hiconstant> | |
7269 | addiu $at,$at,<loconstant> | |
7270 | addu $tempreg,$tempreg,$at | |
7271 | ||
7272 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
7273 | local symbols, even though it introduces an additional | |
7274 | instruction. */ | |
7275 | ||
f5040a92 AO |
7276 | if (offset_expr.X_add_number) |
7277 | { | |
4d7206a2 | 7278 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
7279 | offset_expr.X_add_number = 0; |
7280 | ||
4d7206a2 | 7281 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7282 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7283 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
7284 | |
7285 | if (expr1.X_add_number >= -0x8000 | |
7286 | && expr1.X_add_number < 0x8000) | |
7287 | { | |
67c0d1eb RS |
7288 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
7289 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 7290 | } |
ecd13cd3 | 7291 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 7292 | { |
f5040a92 AO |
7293 | /* If we are going to add in a base register, and the |
7294 | target register and the base register are the same, | |
7295 | then we are using AT as a temporary register. Since | |
7296 | we want to load the constant into AT, we add our | |
7297 | current AT (from the global offset table) and the | |
7298 | register into the register now, and pretend we were | |
7299 | not using a base register. */ | |
7300 | if (breg != treg) | |
7301 | dreg = tempreg; | |
7302 | else | |
7303 | { | |
9c2799c2 | 7304 | gas_assert (tempreg == AT); |
67c0d1eb RS |
7305 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
7306 | treg, AT, breg); | |
f5040a92 | 7307 | dreg = treg; |
67c0d1eb | 7308 | add_breg_early = 1; |
f5040a92 AO |
7309 | } |
7310 | ||
f6a22291 | 7311 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 7312 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7313 | dreg, dreg, AT); |
f5040a92 | 7314 | |
f5040a92 AO |
7315 | used_at = 1; |
7316 | } | |
7317 | else | |
7318 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
7319 | ||
4d7206a2 | 7320 | relax_switch (); |
f5040a92 AO |
7321 | offset_expr.X_add_number = expr1.X_add_number; |
7322 | ||
67c0d1eb RS |
7323 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7324 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
7325 | if (add_breg_early) | |
f5040a92 | 7326 | { |
67c0d1eb | 7327 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
f899b4b8 | 7328 | treg, tempreg, breg); |
f5040a92 AO |
7329 | breg = 0; |
7330 | tempreg = treg; | |
7331 | } | |
4d7206a2 | 7332 | relax_end (); |
f5040a92 | 7333 | } |
4d7206a2 | 7334 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 7335 | { |
4d7206a2 | 7336 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7337 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7338 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 7339 | relax_switch (); |
67c0d1eb RS |
7340 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7341 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 7342 | relax_end (); |
f5040a92 | 7343 | } |
4d7206a2 | 7344 | else |
f5040a92 | 7345 | { |
67c0d1eb RS |
7346 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7347 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
7348 | } |
7349 | } | |
0a44bf69 | 7350 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 7351 | { |
67c0d1eb | 7352 | int gpdelay; |
9117d219 NC |
7353 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
7354 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 7355 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
7356 | |
7357 | /* This is the large GOT case. If this is a reference to an | |
7358 | external symbol, and there is no constant, we want | |
7359 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7360 | addu $tempreg,$tempreg,$gp | |
7361 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 7362 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
7363 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
7364 | addu $tempreg,$tempreg,$gp | |
7365 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
7366 | For a local symbol, we want |
7367 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7368 | nop | |
7369 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7370 | ||
7371 | If we have a small constant, and this is a reference to | |
7372 | an external symbol, we want | |
7373 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7374 | addu $tempreg,$tempreg,$gp | |
7375 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7376 | nop | |
7377 | addiu $tempreg,$tempreg,<constant> | |
7378 | For a local symbol, we want | |
7379 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7380 | nop | |
7381 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
7382 | ||
7383 | If we have a large constant, and this is a reference to | |
7384 | an external symbol, we want | |
7385 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7386 | addu $tempreg,$tempreg,$gp | |
7387 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7388 | lui $at,<hiconstant> | |
7389 | addiu $at,$at,<loconstant> | |
7390 | addu $tempreg,$tempreg,$at | |
7391 | For a local symbol, we want | |
7392 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7393 | lui $at,<hiconstant> | |
7394 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
7395 | addu $tempreg,$tempreg,$at | |
f5040a92 | 7396 | */ |
438c16b8 | 7397 | |
252b5132 RH |
7398 | expr1.X_add_number = offset_expr.X_add_number; |
7399 | offset_expr.X_add_number = 0; | |
4d7206a2 | 7400 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 7401 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
7402 | if (expr1.X_add_number == 0 && breg == 0 |
7403 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
7404 | { |
7405 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
7406 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
7407 | } | |
df58fc94 | 7408 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 7409 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7410 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 7411 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 7412 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
7413 | if (expr1.X_add_number == 0) |
7414 | { | |
67c0d1eb | 7415 | if (breg != 0) |
252b5132 RH |
7416 | { |
7417 | /* We're going to put in an addu instruction using | |
7418 | tempreg, so we may as well insert the nop right | |
7419 | now. */ | |
269137b2 | 7420 | load_delay_nop (); |
252b5132 | 7421 | } |
252b5132 RH |
7422 | } |
7423 | else if (expr1.X_add_number >= -0x8000 | |
7424 | && expr1.X_add_number < 0x8000) | |
7425 | { | |
269137b2 | 7426 | load_delay_nop (); |
67c0d1eb | 7427 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 7428 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
7429 | } |
7430 | else | |
7431 | { | |
252b5132 RH |
7432 | /* If we are going to add in a base register, and the |
7433 | target register and the base register are the same, | |
7434 | then we are using AT as a temporary register. Since | |
7435 | we want to load the constant into AT, we add our | |
7436 | current AT (from the global offset table) and the | |
7437 | register into the register now, and pretend we were | |
7438 | not using a base register. */ | |
7439 | if (breg != treg) | |
67c0d1eb | 7440 | dreg = tempreg; |
252b5132 RH |
7441 | else |
7442 | { | |
9c2799c2 | 7443 | gas_assert (tempreg == AT); |
269137b2 | 7444 | load_delay_nop (); |
67c0d1eb | 7445 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7446 | treg, AT, breg); |
252b5132 | 7447 | dreg = treg; |
252b5132 RH |
7448 | } |
7449 | ||
f6a22291 | 7450 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 7451 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 7452 | |
252b5132 RH |
7453 | used_at = 1; |
7454 | } | |
4d7206a2 RS |
7455 | offset_expr.X_add_number = |
7456 | ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
7457 | relax_switch (); | |
252b5132 | 7458 | |
67c0d1eb | 7459 | if (gpdelay) |
252b5132 RH |
7460 | { |
7461 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 7462 | the first instruction on the main stream does not. */ |
67c0d1eb | 7463 | macro_build (NULL, "nop", ""); |
252b5132 | 7464 | } |
ed6fb7bd | 7465 | |
67c0d1eb RS |
7466 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7467 | local_reloc_type, mips_gp_register); | |
f5040a92 | 7468 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
7469 | && expr1.X_add_number < 0x8000) |
7470 | { | |
269137b2 | 7471 | load_delay_nop (); |
67c0d1eb RS |
7472 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7473 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 7474 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
7475 | register, the external symbol case ended with a load, |
7476 | so if the symbol turns out to not be external, and | |
7477 | the next instruction uses tempreg, an unnecessary nop | |
7478 | will be inserted. */ | |
252b5132 RH |
7479 | } |
7480 | else | |
7481 | { | |
7482 | if (breg == treg) | |
7483 | { | |
7484 | /* We must add in the base register now, as in the | |
f5040a92 | 7485 | external symbol case. */ |
9c2799c2 | 7486 | gas_assert (tempreg == AT); |
269137b2 | 7487 | load_delay_nop (); |
67c0d1eb | 7488 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7489 | treg, AT, breg); |
252b5132 RH |
7490 | tempreg = treg; |
7491 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 7492 | it in in both cases. */ |
252b5132 RH |
7493 | breg = 0; |
7494 | } | |
7495 | ||
67c0d1eb RS |
7496 | macro_build_lui (&expr1, AT); |
7497 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 7498 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 7499 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7500 | tempreg, tempreg, AT); |
8fc2e39e | 7501 | used_at = 1; |
252b5132 | 7502 | } |
4d7206a2 | 7503 | relax_end (); |
252b5132 | 7504 | } |
0a44bf69 | 7505 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 7506 | { |
f5040a92 AO |
7507 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
7508 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 7509 | int add_breg_early = 0; |
f5040a92 AO |
7510 | |
7511 | /* This is the large GOT case. If this is a reference to an | |
7512 | external symbol, and there is no constant, we want | |
7513 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7514 | add $tempreg,$tempreg,$gp | |
7515 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 7516 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
7517 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
7518 | add $tempreg,$tempreg,$gp | |
7519 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
7520 | ||
7521 | If we have a small constant, and this is a reference to | |
7522 | an external symbol, we want | |
7523 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7524 | add $tempreg,$tempreg,$gp | |
7525 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7526 | addi $tempreg,$tempreg,<constant> | |
7527 | ||
7528 | If we have a large constant, and this is a reference to | |
7529 | an external symbol, we want | |
7530 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7531 | addu $tempreg,$tempreg,$gp | |
7532 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7533 | lui $at,<hiconstant> | |
7534 | addi $at,$at,<loconstant> | |
7535 | add $tempreg,$tempreg,$at | |
7536 | ||
7537 | If we have NewABI, and we know it's a local symbol, we want | |
7538 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
7539 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
7540 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
7541 | ||
4d7206a2 | 7542 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 7543 | |
4d7206a2 | 7544 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
7545 | offset_expr.X_add_number = 0; |
7546 | ||
1abe91b1 MR |
7547 | if (expr1.X_add_number == 0 && breg == 0 |
7548 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
7549 | { |
7550 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
7551 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
7552 | } | |
df58fc94 | 7553 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 7554 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7555 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
7556 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7557 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
7558 | |
7559 | if (expr1.X_add_number == 0) | |
4d7206a2 | 7560 | ; |
f5040a92 AO |
7561 | else if (expr1.X_add_number >= -0x8000 |
7562 | && expr1.X_add_number < 0x8000) | |
7563 | { | |
67c0d1eb | 7564 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 7565 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 7566 | } |
ecd13cd3 | 7567 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 7568 | { |
f5040a92 AO |
7569 | /* If we are going to add in a base register, and the |
7570 | target register and the base register are the same, | |
7571 | then we are using AT as a temporary register. Since | |
7572 | we want to load the constant into AT, we add our | |
7573 | current AT (from the global offset table) and the | |
7574 | register into the register now, and pretend we were | |
7575 | not using a base register. */ | |
7576 | if (breg != treg) | |
7577 | dreg = tempreg; | |
7578 | else | |
7579 | { | |
9c2799c2 | 7580 | gas_assert (tempreg == AT); |
67c0d1eb | 7581 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7582 | treg, AT, breg); |
f5040a92 | 7583 | dreg = treg; |
67c0d1eb | 7584 | add_breg_early = 1; |
f5040a92 AO |
7585 | } |
7586 | ||
f6a22291 | 7587 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 7588 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 7589 | |
f5040a92 AO |
7590 | used_at = 1; |
7591 | } | |
7592 | else | |
7593 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
7594 | ||
4d7206a2 | 7595 | relax_switch (); |
f5040a92 | 7596 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
7597 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7598 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
7599 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
7600 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
7601 | if (add_breg_early) | |
f5040a92 | 7602 | { |
67c0d1eb | 7603 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7604 | treg, tempreg, breg); |
f5040a92 AO |
7605 | breg = 0; |
7606 | tempreg = treg; | |
7607 | } | |
4d7206a2 | 7608 | relax_end (); |
f5040a92 | 7609 | } |
252b5132 RH |
7610 | else |
7611 | abort (); | |
7612 | ||
7613 | if (breg != 0) | |
aed1a261 | 7614 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg); |
252b5132 RH |
7615 | break; |
7616 | ||
52b6b6b9 | 7617 | case M_MSGSND: |
df58fc94 | 7618 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
7619 | { |
7620 | unsigned long temp = (treg << 16) | (0x01); | |
7621 | macro_build (NULL, "c2", "C", temp); | |
7622 | } | |
c7af4273 | 7623 | break; |
52b6b6b9 JM |
7624 | |
7625 | case M_MSGLD: | |
df58fc94 | 7626 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
7627 | { |
7628 | unsigned long temp = (0x02); | |
7629 | macro_build (NULL, "c2", "C", temp); | |
7630 | } | |
c7af4273 | 7631 | break; |
52b6b6b9 JM |
7632 | |
7633 | case M_MSGLD_T: | |
df58fc94 | 7634 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
7635 | { |
7636 | unsigned long temp = (treg << 16) | (0x02); | |
7637 | macro_build (NULL, "c2", "C", temp); | |
7638 | } | |
c7af4273 | 7639 | break; |
52b6b6b9 JM |
7640 | |
7641 | case M_MSGWAIT: | |
df58fc94 | 7642 | gas_assert (!mips_opts.micromips); |
52b6b6b9 | 7643 | macro_build (NULL, "c2", "C", 3); |
c7af4273 | 7644 | break; |
52b6b6b9 JM |
7645 | |
7646 | case M_MSGWAIT_T: | |
df58fc94 | 7647 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
7648 | { |
7649 | unsigned long temp = (treg << 16) | 0x03; | |
7650 | macro_build (NULL, "c2", "C", temp); | |
7651 | } | |
c7af4273 | 7652 | break; |
52b6b6b9 | 7653 | |
252b5132 RH |
7654 | case M_J_A: |
7655 | /* The j instruction may not be used in PIC code, since it | |
7656 | requires an absolute address. We convert it to a b | |
7657 | instruction. */ | |
7658 | if (mips_pic == NO_PIC) | |
67c0d1eb | 7659 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 7660 | else |
67c0d1eb | 7661 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 7662 | break; |
252b5132 RH |
7663 | |
7664 | /* The jal instructions must be handled as macros because when | |
7665 | generating PIC code they expand to multi-instruction | |
7666 | sequences. Normally they are simple instructions. */ | |
df58fc94 RS |
7667 | case M_JALS_1: |
7668 | dreg = RA; | |
7669 | /* Fall through. */ | |
7670 | case M_JALS_2: | |
7671 | gas_assert (mips_opts.micromips); | |
7672 | jals = 1; | |
7673 | goto jal; | |
252b5132 RH |
7674 | case M_JAL_1: |
7675 | dreg = RA; | |
7676 | /* Fall through. */ | |
7677 | case M_JAL_2: | |
df58fc94 | 7678 | jal: |
3e722fb5 | 7679 | if (mips_pic == NO_PIC) |
df58fc94 RS |
7680 | { |
7681 | s = jals ? "jalrs" : "jalr"; | |
7682 | if (mips_opts.micromips && dreg == RA) | |
7683 | macro_build (NULL, s, "mj", sreg); | |
7684 | else | |
7685 | macro_build (NULL, s, JALR_FMT, dreg, sreg); | |
7686 | } | |
0a44bf69 | 7687 | else |
252b5132 | 7688 | { |
df58fc94 RS |
7689 | int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI |
7690 | && mips_cprestore_offset >= 0); | |
7691 | ||
252b5132 RH |
7692 | if (sreg != PIC_CALL_REG) |
7693 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 7694 | |
df58fc94 RS |
7695 | s = (mips_opts.micromips && (!mips_opts.noreorder || cprestore) |
7696 | ? "jalrs" : "jalr"); | |
7697 | if (mips_opts.micromips && dreg == RA) | |
7698 | macro_build (NULL, s, "mj", sreg); | |
7699 | else | |
7700 | macro_build (NULL, s, JALR_FMT, dreg, sreg); | |
0a44bf69 | 7701 | if (mips_pic == SVR4_PIC && !HAVE_NEWABI) |
252b5132 | 7702 | { |
6478892d TS |
7703 | if (mips_cprestore_offset < 0) |
7704 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
7705 | else | |
7706 | { | |
90ecf173 | 7707 | if (!mips_frame_reg_valid) |
7a621144 DJ |
7708 | { |
7709 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
7710 | /* Quiet this warning. */ | |
7711 | mips_frame_reg_valid = 1; | |
7712 | } | |
90ecf173 | 7713 | if (!mips_cprestore_valid) |
7a621144 DJ |
7714 | { |
7715 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
7716 | /* Quiet this warning. */ | |
7717 | mips_cprestore_valid = 1; | |
7718 | } | |
d3fca0b5 MR |
7719 | if (mips_opts.noreorder) |
7720 | macro_build (NULL, "nop", ""); | |
6478892d | 7721 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 7722 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 7723 | mips_gp_register, |
256ab948 TS |
7724 | mips_frame_reg, |
7725 | HAVE_64BIT_ADDRESSES); | |
6478892d | 7726 | } |
252b5132 RH |
7727 | } |
7728 | } | |
252b5132 | 7729 | |
8fc2e39e | 7730 | break; |
252b5132 | 7731 | |
df58fc94 RS |
7732 | case M_JALS_A: |
7733 | gas_assert (mips_opts.micromips); | |
7734 | jals = 1; | |
7735 | /* Fall through. */ | |
252b5132 RH |
7736 | case M_JAL_A: |
7737 | if (mips_pic == NO_PIC) | |
df58fc94 | 7738 | macro_build (&offset_expr, jals ? "jals" : "jal", "a"); |
252b5132 RH |
7739 | else if (mips_pic == SVR4_PIC) |
7740 | { | |
7741 | /* If this is a reference to an external symbol, and we are | |
7742 | using a small GOT, we want | |
7743 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
7744 | nop | |
f9419b05 | 7745 | jalr $ra,$25 |
252b5132 RH |
7746 | nop |
7747 | lw $gp,cprestore($sp) | |
7748 | The cprestore value is set using the .cprestore | |
7749 | pseudo-op. If we are using a big GOT, we want | |
7750 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
7751 | addu $25,$25,$gp | |
7752 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
7753 | nop | |
f9419b05 | 7754 | jalr $ra,$25 |
252b5132 RH |
7755 | nop |
7756 | lw $gp,cprestore($sp) | |
7757 | If the symbol is not external, we want | |
7758 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7759 | nop | |
7760 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 7761 | jalr $ra,$25 |
252b5132 | 7762 | nop |
438c16b8 | 7763 | lw $gp,cprestore($sp) |
f5040a92 AO |
7764 | |
7765 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
7766 | sequences above, minus nops, unless the symbol is local, | |
7767 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
7768 | GOT_DISP. */ | |
438c16b8 | 7769 | if (HAVE_NEWABI) |
252b5132 | 7770 | { |
90ecf173 | 7771 | if (!mips_big_got) |
f5040a92 | 7772 | { |
4d7206a2 | 7773 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7774 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7775 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 7776 | mips_gp_register); |
4d7206a2 | 7777 | relax_switch (); |
67c0d1eb RS |
7778 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7779 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
7780 | mips_gp_register); |
7781 | relax_end (); | |
f5040a92 AO |
7782 | } |
7783 | else | |
7784 | { | |
4d7206a2 | 7785 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 7786 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
7787 | BFD_RELOC_MIPS_CALL_HI16); |
7788 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
7789 | PIC_CALL_REG, mips_gp_register); | |
7790 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
7791 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
7792 | PIC_CALL_REG); | |
4d7206a2 | 7793 | relax_switch (); |
67c0d1eb RS |
7794 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7795 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
7796 | mips_gp_register); | |
7797 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
7798 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 7799 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 7800 | relax_end (); |
f5040a92 | 7801 | } |
684022ea | 7802 | |
df58fc94 | 7803 | macro_build_jalr (&offset_expr, 0); |
252b5132 RH |
7804 | } |
7805 | else | |
7806 | { | |
4d7206a2 | 7807 | relax_start (offset_expr.X_add_symbol); |
90ecf173 | 7808 | if (!mips_big_got) |
438c16b8 | 7809 | { |
67c0d1eb RS |
7810 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7811 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 7812 | mips_gp_register); |
269137b2 | 7813 | load_delay_nop (); |
4d7206a2 | 7814 | relax_switch (); |
438c16b8 | 7815 | } |
252b5132 | 7816 | else |
252b5132 | 7817 | { |
67c0d1eb RS |
7818 | int gpdelay; |
7819 | ||
7820 | gpdelay = reg_needs_delay (mips_gp_register); | |
df58fc94 | 7821 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
7822 | BFD_RELOC_MIPS_CALL_HI16); |
7823 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
7824 | PIC_CALL_REG, mips_gp_register); | |
7825 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
7826 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
7827 | PIC_CALL_REG); | |
269137b2 | 7828 | load_delay_nop (); |
4d7206a2 | 7829 | relax_switch (); |
67c0d1eb RS |
7830 | if (gpdelay) |
7831 | macro_build (NULL, "nop", ""); | |
252b5132 | 7832 | } |
67c0d1eb RS |
7833 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7834 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 7835 | mips_gp_register); |
269137b2 | 7836 | load_delay_nop (); |
67c0d1eb RS |
7837 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7838 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 7839 | relax_end (); |
df58fc94 | 7840 | macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0); |
438c16b8 | 7841 | |
6478892d TS |
7842 | if (mips_cprestore_offset < 0) |
7843 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
7844 | else | |
7845 | { | |
90ecf173 | 7846 | if (!mips_frame_reg_valid) |
7a621144 DJ |
7847 | { |
7848 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
7849 | /* Quiet this warning. */ | |
7850 | mips_frame_reg_valid = 1; | |
7851 | } | |
90ecf173 | 7852 | if (!mips_cprestore_valid) |
7a621144 DJ |
7853 | { |
7854 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
7855 | /* Quiet this warning. */ | |
7856 | mips_cprestore_valid = 1; | |
7857 | } | |
6478892d | 7858 | if (mips_opts.noreorder) |
67c0d1eb | 7859 | macro_build (NULL, "nop", ""); |
6478892d | 7860 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 7861 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 7862 | mips_gp_register, |
256ab948 TS |
7863 | mips_frame_reg, |
7864 | HAVE_64BIT_ADDRESSES); | |
6478892d | 7865 | } |
252b5132 RH |
7866 | } |
7867 | } | |
0a44bf69 RS |
7868 | else if (mips_pic == VXWORKS_PIC) |
7869 | as_bad (_("Non-PIC jump used in PIC library")); | |
252b5132 RH |
7870 | else |
7871 | abort (); | |
7872 | ||
8fc2e39e | 7873 | break; |
252b5132 RH |
7874 | |
7875 | case M_LB_AB: | |
df58fc94 | 7876 | ab = 1; |
252b5132 | 7877 | s = "lb"; |
df58fc94 | 7878 | fmt = "t,o(b)"; |
252b5132 RH |
7879 | goto ld; |
7880 | case M_LBU_AB: | |
df58fc94 | 7881 | ab = 1; |
252b5132 | 7882 | s = "lbu"; |
df58fc94 | 7883 | fmt = "t,o(b)"; |
252b5132 RH |
7884 | goto ld; |
7885 | case M_LH_AB: | |
df58fc94 | 7886 | ab = 1; |
252b5132 | 7887 | s = "lh"; |
df58fc94 | 7888 | fmt = "t,o(b)"; |
252b5132 RH |
7889 | goto ld; |
7890 | case M_LHU_AB: | |
df58fc94 | 7891 | ab = 1; |
252b5132 | 7892 | s = "lhu"; |
df58fc94 | 7893 | fmt = "t,o(b)"; |
252b5132 RH |
7894 | goto ld; |
7895 | case M_LW_AB: | |
df58fc94 | 7896 | ab = 1; |
252b5132 | 7897 | s = "lw"; |
df58fc94 | 7898 | fmt = "t,o(b)"; |
252b5132 RH |
7899 | goto ld; |
7900 | case M_LWC0_AB: | |
df58fc94 RS |
7901 | ab = 1; |
7902 | gas_assert (!mips_opts.micromips); | |
252b5132 | 7903 | s = "lwc0"; |
df58fc94 | 7904 | fmt = "E,o(b)"; |
bdaaa2e1 | 7905 | /* Itbl support may require additional care here. */ |
252b5132 | 7906 | coproc = 1; |
df58fc94 | 7907 | goto ld_st; |
252b5132 | 7908 | case M_LWC1_AB: |
df58fc94 | 7909 | ab = 1; |
252b5132 | 7910 | s = "lwc1"; |
df58fc94 | 7911 | fmt = "T,o(b)"; |
bdaaa2e1 | 7912 | /* Itbl support may require additional care here. */ |
252b5132 | 7913 | coproc = 1; |
df58fc94 | 7914 | goto ld_st; |
252b5132 | 7915 | case M_LWC2_AB: |
df58fc94 RS |
7916 | ab = 1; |
7917 | case M_LWC2_OB: | |
252b5132 | 7918 | s = "lwc2"; |
df58fc94 RS |
7919 | fmt = COP12_FMT; |
7920 | off12 = mips_opts.micromips; | |
bdaaa2e1 | 7921 | /* Itbl support may require additional care here. */ |
252b5132 | 7922 | coproc = 1; |
df58fc94 | 7923 | goto ld_st; |
252b5132 | 7924 | case M_LWC3_AB: |
df58fc94 RS |
7925 | ab = 1; |
7926 | gas_assert (!mips_opts.micromips); | |
252b5132 | 7927 | s = "lwc3"; |
df58fc94 | 7928 | fmt = "E,o(b)"; |
bdaaa2e1 | 7929 | /* Itbl support may require additional care here. */ |
252b5132 | 7930 | coproc = 1; |
df58fc94 | 7931 | goto ld_st; |
252b5132 | 7932 | case M_LWL_AB: |
df58fc94 RS |
7933 | ab = 1; |
7934 | case M_LWL_OB: | |
252b5132 | 7935 | s = "lwl"; |
df58fc94 RS |
7936 | fmt = MEM12_FMT; |
7937 | off12 = mips_opts.micromips; | |
7938 | goto ld_st; | |
252b5132 | 7939 | case M_LWR_AB: |
df58fc94 RS |
7940 | ab = 1; |
7941 | case M_LWR_OB: | |
252b5132 | 7942 | s = "lwr"; |
df58fc94 RS |
7943 | fmt = MEM12_FMT; |
7944 | off12 = mips_opts.micromips; | |
7945 | goto ld_st; | |
252b5132 | 7946 | case M_LDC1_AB: |
df58fc94 | 7947 | ab = 1; |
252b5132 | 7948 | s = "ldc1"; |
df58fc94 | 7949 | fmt = "T,o(b)"; |
bdaaa2e1 | 7950 | /* Itbl support may require additional care here. */ |
252b5132 | 7951 | coproc = 1; |
df58fc94 | 7952 | goto ld_st; |
252b5132 | 7953 | case M_LDC2_AB: |
df58fc94 RS |
7954 | ab = 1; |
7955 | case M_LDC2_OB: | |
252b5132 | 7956 | s = "ldc2"; |
df58fc94 RS |
7957 | fmt = COP12_FMT; |
7958 | off12 = mips_opts.micromips; | |
bdaaa2e1 | 7959 | /* Itbl support may require additional care here. */ |
252b5132 | 7960 | coproc = 1; |
df58fc94 | 7961 | goto ld_st; |
252b5132 | 7962 | case M_LDC3_AB: |
df58fc94 | 7963 | ab = 1; |
252b5132 | 7964 | s = "ldc3"; |
df58fc94 | 7965 | fmt = "E,o(b)"; |
bdaaa2e1 | 7966 | /* Itbl support may require additional care here. */ |
252b5132 | 7967 | coproc = 1; |
df58fc94 | 7968 | goto ld_st; |
252b5132 | 7969 | case M_LDL_AB: |
df58fc94 RS |
7970 | ab = 1; |
7971 | case M_LDL_OB: | |
252b5132 | 7972 | s = "ldl"; |
df58fc94 RS |
7973 | fmt = MEM12_FMT; |
7974 | off12 = mips_opts.micromips; | |
7975 | goto ld_st; | |
252b5132 | 7976 | case M_LDR_AB: |
df58fc94 RS |
7977 | ab = 1; |
7978 | case M_LDR_OB: | |
252b5132 | 7979 | s = "ldr"; |
df58fc94 RS |
7980 | fmt = MEM12_FMT; |
7981 | off12 = mips_opts.micromips; | |
7982 | goto ld_st; | |
252b5132 | 7983 | case M_LL_AB: |
df58fc94 RS |
7984 | ab = 1; |
7985 | case M_LL_OB: | |
252b5132 | 7986 | s = "ll"; |
df58fc94 RS |
7987 | fmt = MEM12_FMT; |
7988 | off12 = mips_opts.micromips; | |
252b5132 RH |
7989 | goto ld; |
7990 | case M_LLD_AB: | |
df58fc94 RS |
7991 | ab = 1; |
7992 | case M_LLD_OB: | |
252b5132 | 7993 | s = "lld"; |
df58fc94 RS |
7994 | fmt = MEM12_FMT; |
7995 | off12 = mips_opts.micromips; | |
252b5132 RH |
7996 | goto ld; |
7997 | case M_LWU_AB: | |
df58fc94 RS |
7998 | ab = 1; |
7999 | case M_LWU_OB: | |
252b5132 | 8000 | s = "lwu"; |
df58fc94 RS |
8001 | fmt = MEM12_FMT; |
8002 | off12 = mips_opts.micromips; | |
8003 | goto ld; | |
8004 | case M_LWP_AB: | |
8005 | ab = 1; | |
8006 | case M_LWP_OB: | |
8007 | gas_assert (mips_opts.micromips); | |
8008 | s = "lwp"; | |
8009 | fmt = "t,~(b)"; | |
8010 | off12 = 1; | |
8011 | lp = 1; | |
8012 | goto ld; | |
8013 | case M_LDP_AB: | |
8014 | ab = 1; | |
8015 | case M_LDP_OB: | |
8016 | gas_assert (mips_opts.micromips); | |
8017 | s = "ldp"; | |
8018 | fmt = "t,~(b)"; | |
8019 | off12 = 1; | |
8020 | lp = 1; | |
8021 | goto ld; | |
8022 | case M_LWM_AB: | |
8023 | ab = 1; | |
8024 | case M_LWM_OB: | |
8025 | gas_assert (mips_opts.micromips); | |
8026 | s = "lwm"; | |
8027 | fmt = "n,~(b)"; | |
8028 | off12 = 1; | |
8029 | goto ld_st; | |
8030 | case M_LDM_AB: | |
8031 | ab = 1; | |
8032 | case M_LDM_OB: | |
8033 | gas_assert (mips_opts.micromips); | |
8034 | s = "ldm"; | |
8035 | fmt = "n,~(b)"; | |
8036 | off12 = 1; | |
8037 | goto ld_st; | |
8038 | ||
252b5132 | 8039 | ld: |
df58fc94 RS |
8040 | if (breg == treg + lp) |
8041 | goto ld_st; | |
252b5132 | 8042 | else |
df58fc94 RS |
8043 | tempreg = treg + lp; |
8044 | goto ld_noat; | |
8045 | ||
252b5132 | 8046 | case M_SB_AB: |
df58fc94 | 8047 | ab = 1; |
252b5132 | 8048 | s = "sb"; |
df58fc94 RS |
8049 | fmt = "t,o(b)"; |
8050 | goto ld_st; | |
252b5132 | 8051 | case M_SH_AB: |
df58fc94 | 8052 | ab = 1; |
252b5132 | 8053 | s = "sh"; |
df58fc94 RS |
8054 | fmt = "t,o(b)"; |
8055 | goto ld_st; | |
252b5132 | 8056 | case M_SW_AB: |
df58fc94 | 8057 | ab = 1; |
252b5132 | 8058 | s = "sw"; |
df58fc94 RS |
8059 | fmt = "t,o(b)"; |
8060 | goto ld_st; | |
252b5132 | 8061 | case M_SWC0_AB: |
df58fc94 RS |
8062 | ab = 1; |
8063 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8064 | s = "swc0"; |
df58fc94 | 8065 | fmt = "E,o(b)"; |
bdaaa2e1 | 8066 | /* Itbl support may require additional care here. */ |
252b5132 | 8067 | coproc = 1; |
df58fc94 | 8068 | goto ld_st; |
252b5132 | 8069 | case M_SWC1_AB: |
df58fc94 | 8070 | ab = 1; |
252b5132 | 8071 | s = "swc1"; |
df58fc94 | 8072 | fmt = "T,o(b)"; |
bdaaa2e1 | 8073 | /* Itbl support may require additional care here. */ |
252b5132 | 8074 | coproc = 1; |
df58fc94 | 8075 | goto ld_st; |
252b5132 | 8076 | case M_SWC2_AB: |
df58fc94 RS |
8077 | ab = 1; |
8078 | case M_SWC2_OB: | |
252b5132 | 8079 | s = "swc2"; |
df58fc94 RS |
8080 | fmt = COP12_FMT; |
8081 | off12 = mips_opts.micromips; | |
bdaaa2e1 | 8082 | /* Itbl support may require additional care here. */ |
252b5132 | 8083 | coproc = 1; |
df58fc94 | 8084 | goto ld_st; |
252b5132 | 8085 | case M_SWC3_AB: |
df58fc94 RS |
8086 | ab = 1; |
8087 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8088 | s = "swc3"; |
df58fc94 | 8089 | fmt = "E,o(b)"; |
bdaaa2e1 | 8090 | /* Itbl support may require additional care here. */ |
252b5132 | 8091 | coproc = 1; |
df58fc94 | 8092 | goto ld_st; |
252b5132 | 8093 | case M_SWL_AB: |
df58fc94 RS |
8094 | ab = 1; |
8095 | case M_SWL_OB: | |
252b5132 | 8096 | s = "swl"; |
df58fc94 RS |
8097 | fmt = MEM12_FMT; |
8098 | off12 = mips_opts.micromips; | |
8099 | goto ld_st; | |
252b5132 | 8100 | case M_SWR_AB: |
df58fc94 RS |
8101 | ab = 1; |
8102 | case M_SWR_OB: | |
252b5132 | 8103 | s = "swr"; |
df58fc94 RS |
8104 | fmt = MEM12_FMT; |
8105 | off12 = mips_opts.micromips; | |
8106 | goto ld_st; | |
252b5132 | 8107 | case M_SC_AB: |
df58fc94 RS |
8108 | ab = 1; |
8109 | case M_SC_OB: | |
252b5132 | 8110 | s = "sc"; |
df58fc94 RS |
8111 | fmt = MEM12_FMT; |
8112 | off12 = mips_opts.micromips; | |
8113 | goto ld_st; | |
252b5132 | 8114 | case M_SCD_AB: |
df58fc94 RS |
8115 | ab = 1; |
8116 | case M_SCD_OB: | |
252b5132 | 8117 | s = "scd"; |
df58fc94 RS |
8118 | fmt = MEM12_FMT; |
8119 | off12 = mips_opts.micromips; | |
8120 | goto ld_st; | |
d43b4baf | 8121 | case M_CACHE_AB: |
df58fc94 RS |
8122 | ab = 1; |
8123 | case M_CACHE_OB: | |
d43b4baf | 8124 | s = "cache"; |
df58fc94 RS |
8125 | fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)"; |
8126 | off12 = mips_opts.micromips; | |
8127 | goto ld_st; | |
3eebd5eb | 8128 | case M_PREF_AB: |
df58fc94 RS |
8129 | ab = 1; |
8130 | case M_PREF_OB: | |
3eebd5eb | 8131 | s = "pref"; |
df58fc94 RS |
8132 | fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)"; |
8133 | off12 = mips_opts.micromips; | |
8134 | goto ld_st; | |
252b5132 | 8135 | case M_SDC1_AB: |
df58fc94 | 8136 | ab = 1; |
252b5132 | 8137 | s = "sdc1"; |
df58fc94 | 8138 | fmt = "T,o(b)"; |
252b5132 | 8139 | coproc = 1; |
bdaaa2e1 | 8140 | /* Itbl support may require additional care here. */ |
df58fc94 | 8141 | goto ld_st; |
252b5132 | 8142 | case M_SDC2_AB: |
df58fc94 RS |
8143 | ab = 1; |
8144 | case M_SDC2_OB: | |
252b5132 | 8145 | s = "sdc2"; |
df58fc94 RS |
8146 | fmt = COP12_FMT; |
8147 | off12 = mips_opts.micromips; | |
bdaaa2e1 | 8148 | /* Itbl support may require additional care here. */ |
252b5132 | 8149 | coproc = 1; |
df58fc94 | 8150 | goto ld_st; |
252b5132 | 8151 | case M_SDC3_AB: |
df58fc94 RS |
8152 | ab = 1; |
8153 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8154 | s = "sdc3"; |
df58fc94 | 8155 | fmt = "E,o(b)"; |
bdaaa2e1 | 8156 | /* Itbl support may require additional care here. */ |
252b5132 | 8157 | coproc = 1; |
df58fc94 | 8158 | goto ld_st; |
252b5132 | 8159 | case M_SDL_AB: |
df58fc94 RS |
8160 | ab = 1; |
8161 | case M_SDL_OB: | |
252b5132 | 8162 | s = "sdl"; |
df58fc94 RS |
8163 | fmt = MEM12_FMT; |
8164 | off12 = mips_opts.micromips; | |
8165 | goto ld_st; | |
252b5132 | 8166 | case M_SDR_AB: |
df58fc94 RS |
8167 | ab = 1; |
8168 | case M_SDR_OB: | |
252b5132 | 8169 | s = "sdr"; |
df58fc94 RS |
8170 | fmt = MEM12_FMT; |
8171 | off12 = mips_opts.micromips; | |
8172 | goto ld_st; | |
8173 | case M_SWP_AB: | |
8174 | ab = 1; | |
8175 | case M_SWP_OB: | |
8176 | gas_assert (mips_opts.micromips); | |
8177 | s = "swp"; | |
8178 | fmt = "t,~(b)"; | |
8179 | off12 = 1; | |
8180 | goto ld_st; | |
8181 | case M_SDP_AB: | |
8182 | ab = 1; | |
8183 | case M_SDP_OB: | |
8184 | gas_assert (mips_opts.micromips); | |
8185 | s = "sdp"; | |
8186 | fmt = "t,~(b)"; | |
8187 | off12 = 1; | |
8188 | goto ld_st; | |
8189 | case M_SWM_AB: | |
8190 | ab = 1; | |
8191 | case M_SWM_OB: | |
8192 | gas_assert (mips_opts.micromips); | |
8193 | s = "swm"; | |
8194 | fmt = "n,~(b)"; | |
8195 | off12 = 1; | |
8196 | goto ld_st; | |
8197 | case M_SDM_AB: | |
8198 | ab = 1; | |
8199 | case M_SDM_OB: | |
8200 | gas_assert (mips_opts.micromips); | |
8201 | s = "sdm"; | |
8202 | fmt = "n,~(b)"; | |
8203 | off12 = 1; | |
8204 | ||
8205 | ld_st: | |
8fc2e39e TS |
8206 | tempreg = AT; |
8207 | used_at = 1; | |
df58fc94 | 8208 | ld_noat: |
b19e8a9b AN |
8209 | if (coproc |
8210 | && NO_ISA_COP (mips_opts.arch) | |
8211 | && (ip->insn_mo->pinfo2 & (INSN2_M_FP_S | INSN2_M_FP_D)) == 0) | |
8212 | { | |
f71d0d44 | 8213 | as_bad (_("Opcode not supported on this processor: %s"), |
b19e8a9b AN |
8214 | mips_cpu_info_from_arch (mips_opts.arch)->name); |
8215 | break; | |
8216 | } | |
8217 | ||
252b5132 RH |
8218 | if (offset_expr.X_op != O_constant |
8219 | && offset_expr.X_op != O_symbol) | |
8220 | { | |
f71d0d44 | 8221 | as_bad (_("Expression too complex")); |
252b5132 RH |
8222 | offset_expr.X_op = O_constant; |
8223 | } | |
8224 | ||
2051e8c4 MR |
8225 | if (HAVE_32BIT_ADDRESSES |
8226 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
8227 | { |
8228 | char value [32]; | |
8229 | ||
8230 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 8231 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 8232 | } |
2051e8c4 | 8233 | |
252b5132 RH |
8234 | /* A constant expression in PIC code can be handled just as it |
8235 | is in non PIC code. */ | |
aed1a261 RS |
8236 | if (offset_expr.X_op == O_constant) |
8237 | { | |
df58fc94 RS |
8238 | int hipart = 0; |
8239 | ||
842f8b2a | 8240 | expr1.X_add_number = offset_expr.X_add_number; |
2051e8c4 | 8241 | normalize_address_expr (&expr1); |
df58fc94 | 8242 | if (!off12 && !IS_SEXT_16BIT_NUM (expr1.X_add_number)) |
842f8b2a MR |
8243 | { |
8244 | expr1.X_add_number = ((expr1.X_add_number + 0x8000) | |
8245 | & ~(bfd_vma) 0xffff); | |
df58fc94 RS |
8246 | hipart = 1; |
8247 | } | |
8248 | else if (off12 && !IS_SEXT_12BIT_NUM (expr1.X_add_number)) | |
8249 | { | |
8250 | expr1.X_add_number = ((expr1.X_add_number + 0x800) | |
8251 | & ~(bfd_vma) 0xfff); | |
8252 | hipart = 1; | |
8253 | } | |
8254 | if (hipart) | |
8255 | { | |
842f8b2a MR |
8256 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); |
8257 | if (breg != 0) | |
8258 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
8259 | tempreg, tempreg, breg); | |
8260 | breg = tempreg; | |
8261 | } | |
df58fc94 RS |
8262 | if (!off12) |
8263 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg); | |
8264 | else | |
8265 | macro_build (NULL, s, fmt, | |
8266 | treg, (unsigned long) offset_expr.X_add_number, breg); | |
8267 | } | |
8268 | else if (off12) | |
8269 | { | |
8270 | /* A 12-bit offset field is too narrow to be used for a low-part | |
8271 | relocation, so load the whole address into the auxillary | |
8272 | register. In the case of "A(b)" addresses, we first load | |
8273 | absolute address "A" into the register and then add base | |
8274 | register "b". In the case of "o(b)" addresses, we simply | |
8275 | need to add 16-bit offset "o" to base register "b", and | |
8276 | offset_reloc already contains the relocations associated | |
8277 | with "o". */ | |
8278 | if (ab) | |
8279 | { | |
8280 | load_address (tempreg, &offset_expr, &used_at); | |
8281 | if (breg != 0) | |
8282 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
8283 | tempreg, tempreg, breg); | |
8284 | } | |
8285 | else | |
8286 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
8287 | tempreg, breg, -1, | |
8288 | offset_reloc[0], offset_reloc[1], offset_reloc[2]); | |
8289 | expr1.X_add_number = 0; | |
8290 | macro_build (NULL, s, fmt, | |
8291 | treg, (unsigned long) expr1.X_add_number, tempreg); | |
aed1a261 RS |
8292 | } |
8293 | else if (mips_pic == NO_PIC) | |
252b5132 RH |
8294 | { |
8295 | /* If this is a reference to a GP relative symbol, and there | |
8296 | is no base register, we want | |
cdf6fd85 | 8297 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
8298 | Otherwise, if there is no base register, we want |
8299 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8300 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8301 | If we have a constant, we need two instructions anyhow, | |
8302 | so we always use the latter form. | |
8303 | ||
8304 | If we have a base register, and this is a reference to a | |
8305 | GP relative symbol, we want | |
8306 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 8307 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
8308 | Otherwise we want |
8309 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8310 | addu $tempreg,$tempreg,$breg | |
8311 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 8312 | With a constant we always use the latter case. |
76b3015f | 8313 | |
d6bc6245 TS |
8314 | With 64bit address space and no base register and $at usable, |
8315 | we want | |
8316 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8317 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
8318 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8319 | dsll32 $tempreg,0 | |
8320 | daddu $tempreg,$at | |
8321 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8322 | If we have a base register, we want | |
8323 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8324 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
8325 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8326 | daddu $at,$breg | |
8327 | dsll32 $tempreg,0 | |
8328 | daddu $tempreg,$at | |
8329 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8330 | ||
8331 | Without $at we can't generate the optimal path for superscalar | |
8332 | processors here since this would require two temporary registers. | |
8333 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8334 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8335 | dsll $tempreg,16 | |
8336 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8337 | dsll $tempreg,16 | |
8338 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8339 | If we have a base register, we want | |
8340 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8341 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8342 | dsll $tempreg,16 | |
8343 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8344 | dsll $tempreg,16 | |
8345 | daddu $tempreg,$tempreg,$breg | |
8346 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 | 8347 | |
6caf9ef4 | 8348 | For GP relative symbols in 64bit address space we can use |
aed1a261 RS |
8349 | the same sequence as in 32bit address space. */ |
8350 | if (HAVE_64BIT_SYMBOLS) | |
d6bc6245 | 8351 | { |
aed1a261 | 8352 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 TS |
8353 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
8354 | { | |
8355 | relax_start (offset_expr.X_add_symbol); | |
8356 | if (breg == 0) | |
8357 | { | |
8358 | macro_build (&offset_expr, s, fmt, treg, | |
8359 | BFD_RELOC_GPREL16, mips_gp_register); | |
8360 | } | |
8361 | else | |
8362 | { | |
8363 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
8364 | tempreg, breg, mips_gp_register); | |
8365 | macro_build (&offset_expr, s, fmt, treg, | |
8366 | BFD_RELOC_GPREL16, tempreg); | |
8367 | } | |
8368 | relax_switch (); | |
8369 | } | |
d6bc6245 | 8370 | |
741fe287 | 8371 | if (used_at == 0 && mips_opts.at) |
d6bc6245 | 8372 | { |
df58fc94 | 8373 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb | 8374 | BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 8375 | macro_build (&offset_expr, "lui", LUI_FMT, AT, |
67c0d1eb RS |
8376 | BFD_RELOC_HI16_S); |
8377 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
8378 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 8379 | if (breg != 0) |
67c0d1eb | 8380 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
df58fc94 | 8381 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb RS |
8382 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
8383 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, | |
8384 | tempreg); | |
d6bc6245 TS |
8385 | used_at = 1; |
8386 | } | |
8387 | else | |
8388 | { | |
df58fc94 | 8389 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb RS |
8390 | BFD_RELOC_MIPS_HIGHEST); |
8391 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
8392 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 8393 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb RS |
8394 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, |
8395 | tempreg, BFD_RELOC_HI16_S); | |
df58fc94 | 8396 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
d6bc6245 | 8397 | if (breg != 0) |
67c0d1eb | 8398 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 8399 | tempreg, tempreg, breg); |
67c0d1eb | 8400 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8401 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 8402 | } |
6caf9ef4 TS |
8403 | |
8404 | if (mips_relax.sequence) | |
8405 | relax_end (); | |
8fc2e39e | 8406 | break; |
d6bc6245 | 8407 | } |
256ab948 | 8408 | |
252b5132 RH |
8409 | if (breg == 0) |
8410 | { | |
67c0d1eb | 8411 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 8412 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 8413 | { |
4d7206a2 | 8414 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
8415 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, |
8416 | mips_gp_register); | |
4d7206a2 | 8417 | relax_switch (); |
252b5132 | 8418 | } |
67c0d1eb RS |
8419 | macro_build_lui (&offset_expr, tempreg); |
8420 | macro_build (&offset_expr, s, fmt, treg, | |
17a2f251 | 8421 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
8422 | if (mips_relax.sequence) |
8423 | relax_end (); | |
252b5132 RH |
8424 | } |
8425 | else | |
8426 | { | |
67c0d1eb | 8427 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 8428 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 8429 | { |
4d7206a2 | 8430 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 8431 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8432 | tempreg, breg, mips_gp_register); |
67c0d1eb | 8433 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8434 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 8435 | relax_switch (); |
252b5132 | 8436 | } |
67c0d1eb RS |
8437 | macro_build_lui (&offset_expr, tempreg); |
8438 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 8439 | tempreg, tempreg, breg); |
67c0d1eb | 8440 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8441 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
8442 | if (mips_relax.sequence) |
8443 | relax_end (); | |
252b5132 RH |
8444 | } |
8445 | } | |
0a44bf69 | 8446 | else if (!mips_big_got) |
252b5132 | 8447 | { |
ed6fb7bd | 8448 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 8449 | |
252b5132 RH |
8450 | /* If this is a reference to an external symbol, we want |
8451 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
8452 | nop | |
8453 | <op> $treg,0($tempreg) | |
8454 | Otherwise we want | |
8455 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
8456 | nop | |
8457 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
8458 | <op> $treg,0($tempreg) | |
f5040a92 AO |
8459 | |
8460 | For NewABI, we want | |
8461 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
8462 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
8463 | ||
252b5132 RH |
8464 | If there is a base register, we add it to $tempreg before |
8465 | the <op>. If there is a constant, we stick it in the | |
8466 | <op> instruction. We don't handle constants larger than | |
8467 | 16 bits, because we have no way to load the upper 16 bits | |
8468 | (actually, we could handle them for the subset of cases | |
8469 | in which we are not using $at). */ | |
9c2799c2 | 8470 | gas_assert (offset_expr.X_op == O_symbol); |
f5040a92 AO |
8471 | if (HAVE_NEWABI) |
8472 | { | |
67c0d1eb RS |
8473 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
8474 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 8475 | if (breg != 0) |
67c0d1eb | 8476 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8477 | tempreg, tempreg, breg); |
67c0d1eb | 8478 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8479 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
8480 | break; |
8481 | } | |
252b5132 RH |
8482 | expr1.X_add_number = offset_expr.X_add_number; |
8483 | offset_expr.X_add_number = 0; | |
8484 | if (expr1.X_add_number < -0x8000 | |
8485 | || expr1.X_add_number >= 0x8000) | |
8486 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
8487 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
8488 | lw_reloc_type, mips_gp_register); | |
269137b2 | 8489 | load_delay_nop (); |
4d7206a2 RS |
8490 | relax_start (offset_expr.X_add_symbol); |
8491 | relax_switch (); | |
67c0d1eb RS |
8492 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
8493 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 8494 | relax_end (); |
252b5132 | 8495 | if (breg != 0) |
67c0d1eb | 8496 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8497 | tempreg, tempreg, breg); |
67c0d1eb | 8498 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 8499 | } |
0a44bf69 | 8500 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 8501 | { |
67c0d1eb | 8502 | int gpdelay; |
252b5132 RH |
8503 | |
8504 | /* If this is a reference to an external symbol, we want | |
8505 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
8506 | addu $tempreg,$tempreg,$gp | |
8507 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
8508 | <op> $treg,0($tempreg) | |
8509 | Otherwise we want | |
8510 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
8511 | nop | |
8512 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
8513 | <op> $treg,0($tempreg) | |
8514 | If there is a base register, we add it to $tempreg before | |
8515 | the <op>. If there is a constant, we stick it in the | |
8516 | <op> instruction. We don't handle constants larger than | |
8517 | 16 bits, because we have no way to load the upper 16 bits | |
8518 | (actually, we could handle them for the subset of cases | |
f5040a92 | 8519 | in which we are not using $at). */ |
9c2799c2 | 8520 | gas_assert (offset_expr.X_op == O_symbol); |
252b5132 RH |
8521 | expr1.X_add_number = offset_expr.X_add_number; |
8522 | offset_expr.X_add_number = 0; | |
8523 | if (expr1.X_add_number < -0x8000 | |
8524 | || expr1.X_add_number >= 0x8000) | |
8525 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 8526 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 8527 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 8528 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 8529 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
8530 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
8531 | mips_gp_register); | |
8532 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
8533 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 8534 | relax_switch (); |
67c0d1eb RS |
8535 | if (gpdelay) |
8536 | macro_build (NULL, "nop", ""); | |
8537 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
8538 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 8539 | load_delay_nop (); |
67c0d1eb RS |
8540 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
8541 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
8542 | relax_end (); |
8543 | ||
252b5132 | 8544 | if (breg != 0) |
67c0d1eb | 8545 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8546 | tempreg, tempreg, breg); |
67c0d1eb | 8547 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 8548 | } |
0a44bf69 | 8549 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 8550 | { |
f5040a92 AO |
8551 | /* If this is a reference to an external symbol, we want |
8552 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
8553 | add $tempreg,$tempreg,$gp | |
8554 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
8555 | <op> $treg,<ofst>($tempreg) | |
8556 | Otherwise, for local symbols, we want: | |
8557 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
8558 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
9c2799c2 | 8559 | gas_assert (offset_expr.X_op == O_symbol); |
4d7206a2 | 8560 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
8561 | offset_expr.X_add_number = 0; |
8562 | if (expr1.X_add_number < -0x8000 | |
8563 | || expr1.X_add_number >= 0x8000) | |
8564 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 8565 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 8566 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 8567 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
8568 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
8569 | mips_gp_register); | |
8570 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
8571 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 8572 | if (breg != 0) |
67c0d1eb | 8573 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8574 | tempreg, tempreg, breg); |
67c0d1eb | 8575 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
684022ea | 8576 | |
4d7206a2 | 8577 | relax_switch (); |
f5040a92 | 8578 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
8579 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
8580 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 8581 | if (breg != 0) |
67c0d1eb | 8582 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8583 | tempreg, tempreg, breg); |
67c0d1eb | 8584 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8585 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 8586 | relax_end (); |
f5040a92 | 8587 | } |
252b5132 RH |
8588 | else |
8589 | abort (); | |
8590 | ||
252b5132 RH |
8591 | break; |
8592 | ||
8593 | case M_LI: | |
8594 | case M_LI_S: | |
67c0d1eb | 8595 | load_register (treg, &imm_expr, 0); |
8fc2e39e | 8596 | break; |
252b5132 RH |
8597 | |
8598 | case M_DLI: | |
67c0d1eb | 8599 | load_register (treg, &imm_expr, 1); |
8fc2e39e | 8600 | break; |
252b5132 RH |
8601 | |
8602 | case M_LI_SS: | |
8603 | if (imm_expr.X_op == O_constant) | |
8604 | { | |
8fc2e39e | 8605 | used_at = 1; |
67c0d1eb RS |
8606 | load_register (AT, &imm_expr, 0); |
8607 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
8608 | break; |
8609 | } | |
8610 | else | |
8611 | { | |
9c2799c2 | 8612 | gas_assert (offset_expr.X_op == O_symbol |
90ecf173 MR |
8613 | && strcmp (segment_name (S_GET_SEGMENT |
8614 | (offset_expr.X_add_symbol)), | |
8615 | ".lit4") == 0 | |
8616 | && offset_expr.X_add_number == 0); | |
67c0d1eb | 8617 | macro_build (&offset_expr, "lwc1", "T,o(b)", treg, |
17a2f251 | 8618 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 8619 | break; |
252b5132 RH |
8620 | } |
8621 | ||
8622 | case M_LI_D: | |
ca4e0257 RS |
8623 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
8624 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
8625 | order 32 bits of the value and the low order 32 bits are either | |
8626 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
8627 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
8628 | { | |
ca4e0257 | 8629 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 8630 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
8631 | else |
8632 | { | |
8633 | int hreg, lreg; | |
8634 | ||
8635 | if (target_big_endian) | |
8636 | { | |
8637 | hreg = treg; | |
8638 | lreg = treg + 1; | |
8639 | } | |
8640 | else | |
8641 | { | |
8642 | hreg = treg + 1; | |
8643 | lreg = treg; | |
8644 | } | |
8645 | ||
8646 | if (hreg <= 31) | |
67c0d1eb | 8647 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
8648 | if (lreg <= 31) |
8649 | { | |
8650 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 8651 | move_register (lreg, 0); |
252b5132 RH |
8652 | else |
8653 | { | |
9c2799c2 | 8654 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb | 8655 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
8656 | } |
8657 | } | |
8658 | } | |
8fc2e39e | 8659 | break; |
252b5132 RH |
8660 | } |
8661 | ||
8662 | /* We know that sym is in the .rdata section. First we get the | |
8663 | upper 16 bits of the address. */ | |
8664 | if (mips_pic == NO_PIC) | |
8665 | { | |
67c0d1eb | 8666 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 8667 | used_at = 1; |
252b5132 | 8668 | } |
0a44bf69 | 8669 | else |
252b5132 | 8670 | { |
67c0d1eb RS |
8671 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
8672 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 8673 | used_at = 1; |
252b5132 | 8674 | } |
bdaaa2e1 | 8675 | |
252b5132 | 8676 | /* Now we load the register(s). */ |
ca4e0257 | 8677 | if (HAVE_64BIT_GPRS) |
8fc2e39e TS |
8678 | { |
8679 | used_at = 1; | |
8680 | macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
8681 | } | |
252b5132 RH |
8682 | else |
8683 | { | |
8fc2e39e | 8684 | used_at = 1; |
67c0d1eb | 8685 | macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
f9419b05 | 8686 | if (treg != RA) |
252b5132 RH |
8687 | { |
8688 | /* FIXME: How in the world do we deal with the possible | |
8689 | overflow here? */ | |
8690 | offset_expr.X_add_number += 4; | |
67c0d1eb | 8691 | macro_build (&offset_expr, "lw", "t,o(b)", |
17a2f251 | 8692 | treg + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
8693 | } |
8694 | } | |
252b5132 RH |
8695 | break; |
8696 | ||
8697 | case M_LI_DD: | |
ca4e0257 RS |
8698 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
8699 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
8700 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
8701 | the value and the low order 32 bits are either zero or in | |
8702 | OFFSET_EXPR. */ | |
252b5132 RH |
8703 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
8704 | { | |
8fc2e39e | 8705 | used_at = 1; |
67c0d1eb | 8706 | load_register (AT, &imm_expr, HAVE_64BIT_FPRS); |
ca4e0257 RS |
8707 | if (HAVE_64BIT_FPRS) |
8708 | { | |
9c2799c2 | 8709 | gas_assert (HAVE_64BIT_GPRS); |
67c0d1eb | 8710 | macro_build (NULL, "dmtc1", "t,S", AT, treg); |
ca4e0257 | 8711 | } |
252b5132 RH |
8712 | else |
8713 | { | |
67c0d1eb | 8714 | macro_build (NULL, "mtc1", "t,G", AT, treg + 1); |
252b5132 | 8715 | if (offset_expr.X_op == O_absent) |
67c0d1eb | 8716 | macro_build (NULL, "mtc1", "t,G", 0, treg); |
252b5132 RH |
8717 | else |
8718 | { | |
9c2799c2 | 8719 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb RS |
8720 | load_register (AT, &offset_expr, 0); |
8721 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
8722 | } |
8723 | } | |
8724 | break; | |
8725 | } | |
8726 | ||
9c2799c2 | 8727 | gas_assert (offset_expr.X_op == O_symbol |
90ecf173 | 8728 | && offset_expr.X_add_number == 0); |
252b5132 RH |
8729 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); |
8730 | if (strcmp (s, ".lit8") == 0) | |
8731 | { | |
df58fc94 | 8732 | if (mips_opts.isa != ISA_MIPS1 || mips_opts.micromips) |
252b5132 | 8733 | { |
67c0d1eb | 8734 | macro_build (&offset_expr, "ldc1", "T,o(b)", treg, |
17a2f251 | 8735 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 8736 | break; |
252b5132 | 8737 | } |
c9914766 | 8738 | breg = mips_gp_register; |
252b5132 RH |
8739 | r = BFD_RELOC_MIPS_LITERAL; |
8740 | goto dob; | |
8741 | } | |
8742 | else | |
8743 | { | |
9c2799c2 | 8744 | gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
8fc2e39e | 8745 | used_at = 1; |
0a44bf69 | 8746 | if (mips_pic != NO_PIC) |
67c0d1eb RS |
8747 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
8748 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
8749 | else |
8750 | { | |
8751 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 8752 | macro_build_lui (&offset_expr, AT); |
252b5132 | 8753 | } |
bdaaa2e1 | 8754 | |
df58fc94 | 8755 | if (mips_opts.isa != ISA_MIPS1 || mips_opts.micromips) |
252b5132 | 8756 | { |
67c0d1eb RS |
8757 | macro_build (&offset_expr, "ldc1", "T,o(b)", |
8758 | treg, BFD_RELOC_LO16, AT); | |
252b5132 RH |
8759 | break; |
8760 | } | |
8761 | breg = AT; | |
8762 | r = BFD_RELOC_LO16; | |
8763 | goto dob; | |
8764 | } | |
8765 | ||
8766 | case M_L_DOB: | |
252b5132 RH |
8767 | /* Even on a big endian machine $fn comes before $fn+1. We have |
8768 | to adjust when loading from memory. */ | |
8769 | r = BFD_RELOC_LO16; | |
8770 | dob: | |
df58fc94 | 8771 | gas_assert (!mips_opts.micromips); |
9c2799c2 | 8772 | gas_assert (mips_opts.isa == ISA_MIPS1); |
67c0d1eb | 8773 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 8774 | target_big_endian ? treg + 1 : treg, r, breg); |
252b5132 RH |
8775 | /* FIXME: A possible overflow which I don't know how to deal |
8776 | with. */ | |
8777 | offset_expr.X_add_number += 4; | |
67c0d1eb | 8778 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 8779 | target_big_endian ? treg : treg + 1, r, breg); |
252b5132 RH |
8780 | break; |
8781 | ||
c4a68bea | 8782 | case M_S_DOB: |
df58fc94 | 8783 | gas_assert (!mips_opts.micromips); |
c4a68bea MR |
8784 | gas_assert (mips_opts.isa == ISA_MIPS1); |
8785 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
8786 | to adjust when storing to memory. */ | |
8787 | macro_build (&offset_expr, "swc1", "T,o(b)", | |
8788 | target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg); | |
8789 | offset_expr.X_add_number += 4; | |
8790 | macro_build (&offset_expr, "swc1", "T,o(b)", | |
8791 | target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg); | |
8792 | break; | |
8793 | ||
252b5132 | 8794 | case M_L_DAB: |
df58fc94 | 8795 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
8796 | /* |
8797 | * The MIPS assembler seems to check for X_add_number not | |
8798 | * being double aligned and generating: | |
8799 | * lui at,%hi(foo+1) | |
8800 | * addu at,at,v1 | |
8801 | * addiu at,at,%lo(foo+1) | |
8802 | * lwc1 f2,0(at) | |
8803 | * lwc1 f3,4(at) | |
8804 | * But, the resulting address is the same after relocation so why | |
8805 | * generate the extra instruction? | |
8806 | */ | |
bdaaa2e1 | 8807 | /* Itbl support may require additional care here. */ |
252b5132 | 8808 | coproc = 1; |
df58fc94 | 8809 | fmt = "T,o(b)"; |
e7af610e | 8810 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
8811 | { |
8812 | s = "ldc1"; | |
df58fc94 | 8813 | goto ld_st; |
252b5132 | 8814 | } |
252b5132 | 8815 | s = "lwc1"; |
252b5132 RH |
8816 | goto ldd_std; |
8817 | ||
8818 | case M_S_DAB: | |
df58fc94 RS |
8819 | gas_assert (!mips_opts.micromips); |
8820 | /* Itbl support may require additional care here. */ | |
8821 | coproc = 1; | |
8822 | fmt = "T,o(b)"; | |
e7af610e | 8823 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
8824 | { |
8825 | s = "sdc1"; | |
df58fc94 | 8826 | goto ld_st; |
252b5132 | 8827 | } |
252b5132 | 8828 | s = "swc1"; |
252b5132 RH |
8829 | goto ldd_std; |
8830 | ||
8831 | case M_LD_AB: | |
df58fc94 | 8832 | fmt = "t,o(b)"; |
ca4e0257 | 8833 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
8834 | { |
8835 | s = "ld"; | |
8836 | goto ld; | |
8837 | } | |
252b5132 | 8838 | s = "lw"; |
252b5132 RH |
8839 | goto ldd_std; |
8840 | ||
8841 | case M_SD_AB: | |
df58fc94 | 8842 | fmt = "t,o(b)"; |
ca4e0257 | 8843 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
8844 | { |
8845 | s = "sd"; | |
df58fc94 | 8846 | goto ld_st; |
252b5132 | 8847 | } |
252b5132 | 8848 | s = "sw"; |
252b5132 RH |
8849 | |
8850 | ldd_std: | |
8851 | if (offset_expr.X_op != O_symbol | |
8852 | && offset_expr.X_op != O_constant) | |
8853 | { | |
f71d0d44 | 8854 | as_bad (_("Expression too complex")); |
252b5132 RH |
8855 | offset_expr.X_op = O_constant; |
8856 | } | |
8857 | ||
2051e8c4 MR |
8858 | if (HAVE_32BIT_ADDRESSES |
8859 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
8860 | { |
8861 | char value [32]; | |
8862 | ||
8863 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 8864 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 8865 | } |
2051e8c4 | 8866 | |
252b5132 RH |
8867 | /* Even on a big endian machine $fn comes before $fn+1. We have |
8868 | to adjust when loading from memory. We set coproc if we must | |
8869 | load $fn+1 first. */ | |
bdaaa2e1 | 8870 | /* Itbl support may require additional care here. */ |
90ecf173 | 8871 | if (!target_big_endian) |
252b5132 RH |
8872 | coproc = 0; |
8873 | ||
90ecf173 | 8874 | if (mips_pic == NO_PIC || offset_expr.X_op == O_constant) |
252b5132 RH |
8875 | { |
8876 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 TS |
8877 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
8878 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
8879 | If we have a base register, we use this |
8880 | addu $at,$breg,$gp | |
cdf6fd85 TS |
8881 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
8882 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
8883 | If this is not a GP relative symbol, we want |
8884 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
8885 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
8886 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
8887 | If there is a base register, we add it to $at after the | |
8888 | lui instruction. If there is a constant, we always use | |
8889 | the last case. */ | |
39a59cf8 MR |
8890 | if (offset_expr.X_op == O_symbol |
8891 | && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 8892 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 8893 | { |
4d7206a2 | 8894 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
8895 | if (breg == 0) |
8896 | { | |
c9914766 | 8897 | tempreg = mips_gp_register; |
252b5132 RH |
8898 | } |
8899 | else | |
8900 | { | |
67c0d1eb | 8901 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8902 | AT, breg, mips_gp_register); |
252b5132 | 8903 | tempreg = AT; |
252b5132 RH |
8904 | used_at = 1; |
8905 | } | |
8906 | ||
beae10d5 | 8907 | /* Itbl support may require additional care here. */ |
67c0d1eb | 8908 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 8909 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
8910 | offset_expr.X_add_number += 4; |
8911 | ||
8912 | /* Set mips_optimize to 2 to avoid inserting an | |
8913 | undesired nop. */ | |
8914 | hold_mips_optimize = mips_optimize; | |
8915 | mips_optimize = 2; | |
beae10d5 | 8916 | /* Itbl support may require additional care here. */ |
67c0d1eb | 8917 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 8918 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
8919 | mips_optimize = hold_mips_optimize; |
8920 | ||
4d7206a2 | 8921 | relax_switch (); |
252b5132 | 8922 | |
0970e49e | 8923 | offset_expr.X_add_number -= 4; |
252b5132 | 8924 | } |
8fc2e39e | 8925 | used_at = 1; |
67c0d1eb | 8926 | macro_build_lui (&offset_expr, AT); |
252b5132 | 8927 | if (breg != 0) |
67c0d1eb | 8928 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 8929 | /* Itbl support may require additional care here. */ |
67c0d1eb | 8930 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 8931 | BFD_RELOC_LO16, AT); |
252b5132 RH |
8932 | /* FIXME: How do we handle overflow here? */ |
8933 | offset_expr.X_add_number += 4; | |
beae10d5 | 8934 | /* Itbl support may require additional care here. */ |
67c0d1eb | 8935 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 8936 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
8937 | if (mips_relax.sequence) |
8938 | relax_end (); | |
bdaaa2e1 | 8939 | } |
0a44bf69 | 8940 | else if (!mips_big_got) |
252b5132 | 8941 | { |
252b5132 RH |
8942 | /* If this is a reference to an external symbol, we want |
8943 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
8944 | nop | |
8945 | <op> $treg,0($at) | |
8946 | <op> $treg+1,4($at) | |
8947 | Otherwise we want | |
8948 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
8949 | nop | |
8950 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
8951 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
8952 | If there is a base register we add it to $at before the | |
8953 | lwc1 instructions. If there is a constant we include it | |
8954 | in the lwc1 instructions. */ | |
8955 | used_at = 1; | |
8956 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
8957 | if (expr1.X_add_number < -0x8000 |
8958 | || expr1.X_add_number >= 0x8000 - 4) | |
8959 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 8960 | load_got_offset (AT, &offset_expr); |
269137b2 | 8961 | load_delay_nop (); |
252b5132 | 8962 | if (breg != 0) |
67c0d1eb | 8963 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
8964 | |
8965 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
8966 | nop. */ | |
8967 | hold_mips_optimize = mips_optimize; | |
8968 | mips_optimize = 2; | |
4d7206a2 | 8969 | |
beae10d5 | 8970 | /* Itbl support may require additional care here. */ |
4d7206a2 | 8971 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
8972 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
8973 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 8974 | expr1.X_add_number += 4; |
67c0d1eb RS |
8975 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
8976 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 8977 | relax_switch (); |
67c0d1eb RS |
8978 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
8979 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 8980 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
8981 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
8982 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 8983 | relax_end (); |
252b5132 | 8984 | |
4d7206a2 | 8985 | mips_optimize = hold_mips_optimize; |
252b5132 | 8986 | } |
0a44bf69 | 8987 | else if (mips_big_got) |
252b5132 | 8988 | { |
67c0d1eb | 8989 | int gpdelay; |
252b5132 RH |
8990 | |
8991 | /* If this is a reference to an external symbol, we want | |
8992 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
8993 | addu $at,$at,$gp | |
8994 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
8995 | nop | |
8996 | <op> $treg,0($at) | |
8997 | <op> $treg+1,4($at) | |
8998 | Otherwise we want | |
8999 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9000 | nop | |
9001 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
9002 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
9003 | If there is a base register we add it to $at before the | |
9004 | lwc1 instructions. If there is a constant we include it | |
9005 | in the lwc1 instructions. */ | |
9006 | used_at = 1; | |
9007 | expr1.X_add_number = offset_expr.X_add_number; | |
9008 | offset_expr.X_add_number = 0; | |
9009 | if (expr1.X_add_number < -0x8000 | |
9010 | || expr1.X_add_number >= 0x8000 - 4) | |
9011 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 9012 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 9013 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 9014 | macro_build (&offset_expr, "lui", LUI_FMT, |
67c0d1eb RS |
9015 | AT, BFD_RELOC_MIPS_GOT_HI16); |
9016 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 9017 | AT, AT, mips_gp_register); |
67c0d1eb | 9018 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 9019 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 9020 | load_delay_nop (); |
252b5132 | 9021 | if (breg != 0) |
67c0d1eb | 9022 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 9023 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9024 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 9025 | BFD_RELOC_LO16, AT); |
252b5132 RH |
9026 | expr1.X_add_number += 4; |
9027 | ||
9028 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
9029 | nop. */ | |
9030 | hold_mips_optimize = mips_optimize; | |
9031 | mips_optimize = 2; | |
beae10d5 | 9032 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9033 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 9034 | BFD_RELOC_LO16, AT); |
252b5132 RH |
9035 | mips_optimize = hold_mips_optimize; |
9036 | expr1.X_add_number -= 4; | |
9037 | ||
4d7206a2 RS |
9038 | relax_switch (); |
9039 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
9040 | if (gpdelay) |
9041 | macro_build (NULL, "nop", ""); | |
9042 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
9043 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 9044 | load_delay_nop (); |
252b5132 | 9045 | if (breg != 0) |
67c0d1eb | 9046 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 9047 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
9048 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
9049 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9050 | offset_expr.X_add_number += 4; |
252b5132 RH |
9051 | |
9052 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
9053 | nop. */ | |
9054 | hold_mips_optimize = mips_optimize; | |
9055 | mips_optimize = 2; | |
beae10d5 | 9056 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
9057 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
9058 | BFD_RELOC_LO16, AT); | |
252b5132 | 9059 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 9060 | relax_end (); |
252b5132 | 9061 | } |
252b5132 RH |
9062 | else |
9063 | abort (); | |
9064 | ||
252b5132 RH |
9065 | break; |
9066 | ||
9067 | case M_LD_OB: | |
704897fb | 9068 | s = HAVE_64BIT_GPRS ? "ld" : "lw"; |
252b5132 RH |
9069 | goto sd_ob; |
9070 | case M_SD_OB: | |
704897fb | 9071 | s = HAVE_64BIT_GPRS ? "sd" : "sw"; |
252b5132 | 9072 | sd_ob: |
4614d845 MR |
9073 | macro_build (&offset_expr, s, "t,o(b)", treg, |
9074 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2], | |
9075 | breg); | |
704897fb MR |
9076 | if (!HAVE_64BIT_GPRS) |
9077 | { | |
9078 | offset_expr.X_add_number += 4; | |
9079 | macro_build (&offset_expr, s, "t,o(b)", treg + 1, | |
4614d845 MR |
9080 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2], |
9081 | breg); | |
704897fb | 9082 | } |
8fc2e39e | 9083 | break; |
252b5132 RH |
9084 | |
9085 | /* New code added to support COPZ instructions. | |
9086 | This code builds table entries out of the macros in mip_opcodes. | |
9087 | R4000 uses interlocks to handle coproc delays. | |
9088 | Other chips (like the R3000) require nops to be inserted for delays. | |
9089 | ||
f72c8c98 | 9090 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
9091 | In order to fill delay slots for non-interlocked chips, |
9092 | we must have a way to specify delays based on the coprocessor. | |
9093 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
9094 | What are the side-effects of the cop instruction? | |
9095 | What cache support might we have and what are its effects? | |
9096 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 9097 | What registers are read/set/modified? |
252b5132 RH |
9098 | |
9099 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 9100 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
9101 | |
9102 | case M_COP0: | |
9103 | s = "c0"; | |
9104 | goto copz; | |
9105 | case M_COP1: | |
9106 | s = "c1"; | |
9107 | goto copz; | |
9108 | case M_COP2: | |
9109 | s = "c2"; | |
9110 | goto copz; | |
9111 | case M_COP3: | |
9112 | s = "c3"; | |
9113 | copz: | |
df58fc94 | 9114 | gas_assert (!mips_opts.micromips); |
b19e8a9b AN |
9115 | if (NO_ISA_COP (mips_opts.arch) |
9116 | && (ip->insn_mo->pinfo2 & INSN2_M_FP_S) == 0) | |
9117 | { | |
9118 | as_bad (_("opcode not supported on this processor: %s"), | |
9119 | mips_cpu_info_from_arch (mips_opts.arch)->name); | |
9120 | break; | |
9121 | } | |
9122 | ||
252b5132 RH |
9123 | /* For now we just do C (same as Cz). The parameter will be |
9124 | stored in insn_opcode by mips_ip. */ | |
67c0d1eb | 9125 | macro_build (NULL, s, "C", ip->insn_opcode); |
8fc2e39e | 9126 | break; |
252b5132 | 9127 | |
ea1fb5dc | 9128 | case M_MOVE: |
67c0d1eb | 9129 | move_register (dreg, sreg); |
8fc2e39e | 9130 | break; |
ea1fb5dc | 9131 | |
252b5132 RH |
9132 | case M_DMUL: |
9133 | dbl = 1; | |
9134 | case M_MUL: | |
67c0d1eb | 9135 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg); |
df58fc94 | 9136 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
8fc2e39e | 9137 | break; |
252b5132 RH |
9138 | |
9139 | case M_DMUL_I: | |
9140 | dbl = 1; | |
9141 | case M_MUL_I: | |
9142 | /* The MIPS assembler some times generates shifts and adds. I'm | |
9143 | not trying to be that fancy. GCC should do this for us | |
9144 | anyway. */ | |
8fc2e39e | 9145 | used_at = 1; |
67c0d1eb RS |
9146 | load_register (AT, &imm_expr, dbl); |
9147 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT); | |
df58fc94 | 9148 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
252b5132 RH |
9149 | break; |
9150 | ||
9151 | case M_DMULO_I: | |
9152 | dbl = 1; | |
9153 | case M_MULO_I: | |
9154 | imm = 1; | |
9155 | goto do_mulo; | |
9156 | ||
9157 | case M_DMULO: | |
9158 | dbl = 1; | |
9159 | case M_MULO: | |
9160 | do_mulo: | |
7d10b47d | 9161 | start_noreorder (); |
8fc2e39e | 9162 | used_at = 1; |
252b5132 | 9163 | if (imm) |
67c0d1eb RS |
9164 | load_register (AT, &imm_expr, dbl); |
9165 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); | |
df58fc94 RS |
9166 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
9167 | macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, dreg, dreg, RA); | |
9168 | macro_build (NULL, "mfhi", MFHL_FMT, AT); | |
252b5132 | 9169 | if (mips_trap) |
df58fc94 | 9170 | macro_build (NULL, "tne", TRAP_FMT, dreg, AT, 6); |
252b5132 RH |
9171 | else |
9172 | { | |
df58fc94 RS |
9173 | if (mips_opts.micromips) |
9174 | micromips_label_expr (&label_expr); | |
9175 | else | |
9176 | label_expr.X_add_number = 8; | |
9177 | macro_build (&label_expr, "beq", "s,t,p", dreg, AT); | |
a605d2b3 | 9178 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
9179 | macro_build (NULL, "break", BRK_FMT, 6); |
9180 | if (mips_opts.micromips) | |
9181 | micromips_add_label (); | |
252b5132 | 9182 | } |
7d10b47d | 9183 | end_noreorder (); |
df58fc94 | 9184 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
252b5132 RH |
9185 | break; |
9186 | ||
9187 | case M_DMULOU_I: | |
9188 | dbl = 1; | |
9189 | case M_MULOU_I: | |
9190 | imm = 1; | |
9191 | goto do_mulou; | |
9192 | ||
9193 | case M_DMULOU: | |
9194 | dbl = 1; | |
9195 | case M_MULOU: | |
9196 | do_mulou: | |
7d10b47d | 9197 | start_noreorder (); |
8fc2e39e | 9198 | used_at = 1; |
252b5132 | 9199 | if (imm) |
67c0d1eb RS |
9200 | load_register (AT, &imm_expr, dbl); |
9201 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
17a2f251 | 9202 | sreg, imm ? AT : treg); |
df58fc94 RS |
9203 | macro_build (NULL, "mfhi", MFHL_FMT, AT); |
9204 | macro_build (NULL, "mflo", MFHL_FMT, dreg); | |
252b5132 | 9205 | if (mips_trap) |
df58fc94 | 9206 | macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6); |
252b5132 RH |
9207 | else |
9208 | { | |
df58fc94 RS |
9209 | if (mips_opts.micromips) |
9210 | micromips_label_expr (&label_expr); | |
9211 | else | |
9212 | label_expr.X_add_number = 8; | |
9213 | macro_build (&label_expr, "beq", "s,t,p", AT, ZERO); | |
a605d2b3 | 9214 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
9215 | macro_build (NULL, "break", BRK_FMT, 6); |
9216 | if (mips_opts.micromips) | |
9217 | micromips_add_label (); | |
252b5132 | 9218 | } |
7d10b47d | 9219 | end_noreorder (); |
252b5132 RH |
9220 | break; |
9221 | ||
771c7ce4 | 9222 | case M_DROL: |
fef14a42 | 9223 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
9224 | { |
9225 | if (dreg == sreg) | |
9226 | { | |
9227 | tempreg = AT; | |
9228 | used_at = 1; | |
9229 | } | |
9230 | else | |
9231 | { | |
9232 | tempreg = dreg; | |
82dd0097 | 9233 | } |
67c0d1eb RS |
9234 | macro_build (NULL, "dnegu", "d,w", tempreg, treg); |
9235 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 9236 | break; |
82dd0097 | 9237 | } |
8fc2e39e | 9238 | used_at = 1; |
c80c840e | 9239 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9240 | macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT); |
9241 | macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg); | |
9242 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
9243 | break; |
9244 | ||
252b5132 | 9245 | case M_ROL: |
fef14a42 | 9246 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 CD |
9247 | { |
9248 | if (dreg == sreg) | |
9249 | { | |
9250 | tempreg = AT; | |
9251 | used_at = 1; | |
9252 | } | |
9253 | else | |
9254 | { | |
9255 | tempreg = dreg; | |
82dd0097 | 9256 | } |
67c0d1eb RS |
9257 | macro_build (NULL, "negu", "d,w", tempreg, treg); |
9258 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 9259 | break; |
82dd0097 | 9260 | } |
8fc2e39e | 9261 | used_at = 1; |
c80c840e | 9262 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9263 | macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT); |
9264 | macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg); | |
9265 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
9266 | break; |
9267 | ||
771c7ce4 TS |
9268 | case M_DROL_I: |
9269 | { | |
9270 | unsigned int rot; | |
91d6fa6a NC |
9271 | char *l; |
9272 | char *rr; | |
771c7ce4 TS |
9273 | |
9274 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9275 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9276 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 9277 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
9278 | { |
9279 | rot = (64 - rot) & 0x3f; | |
9280 | if (rot >= 32) | |
df58fc94 | 9281 | macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32); |
60b63b72 | 9282 | else |
df58fc94 | 9283 | macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot); |
8fc2e39e | 9284 | break; |
60b63b72 | 9285 | } |
483fc7cd | 9286 | if (rot == 0) |
483fc7cd | 9287 | { |
df58fc94 | 9288 | macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9289 | break; |
483fc7cd | 9290 | } |
82dd0097 | 9291 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
91d6fa6a | 9292 | rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 | 9293 | rot &= 0x1f; |
8fc2e39e | 9294 | used_at = 1; |
df58fc94 RS |
9295 | macro_build (NULL, l, SHFT_FMT, AT, sreg, rot); |
9296 | macro_build (NULL, rr, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9297 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
9298 | } |
9299 | break; | |
9300 | ||
252b5132 | 9301 | case M_ROL_I: |
771c7ce4 TS |
9302 | { |
9303 | unsigned int rot; | |
9304 | ||
9305 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9306 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9307 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 9308 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 9309 | { |
df58fc94 | 9310 | macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, (32 - rot) & 0x1f); |
8fc2e39e | 9311 | break; |
60b63b72 | 9312 | } |
483fc7cd | 9313 | if (rot == 0) |
483fc7cd | 9314 | { |
df58fc94 | 9315 | macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9316 | break; |
483fc7cd | 9317 | } |
8fc2e39e | 9318 | used_at = 1; |
df58fc94 RS |
9319 | macro_build (NULL, "sll", SHFT_FMT, AT, sreg, rot); |
9320 | macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9321 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
9322 | } |
9323 | break; | |
9324 | ||
9325 | case M_DROR: | |
fef14a42 | 9326 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 9327 | { |
67c0d1eb | 9328 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 9329 | break; |
82dd0097 | 9330 | } |
8fc2e39e | 9331 | used_at = 1; |
c80c840e | 9332 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9333 | macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT); |
9334 | macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg); | |
9335 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
9336 | break; |
9337 | ||
9338 | case M_ROR: | |
fef14a42 | 9339 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 9340 | { |
67c0d1eb | 9341 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 9342 | break; |
82dd0097 | 9343 | } |
8fc2e39e | 9344 | used_at = 1; |
c80c840e | 9345 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9346 | macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT); |
9347 | macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg); | |
9348 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
9349 | break; |
9350 | ||
771c7ce4 TS |
9351 | case M_DROR_I: |
9352 | { | |
9353 | unsigned int rot; | |
91d6fa6a NC |
9354 | char *l; |
9355 | char *rr; | |
771c7ce4 TS |
9356 | |
9357 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9358 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9359 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 9360 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
9361 | { |
9362 | if (rot >= 32) | |
df58fc94 | 9363 | macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32); |
82dd0097 | 9364 | else |
df58fc94 | 9365 | macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot); |
8fc2e39e | 9366 | break; |
82dd0097 | 9367 | } |
483fc7cd | 9368 | if (rot == 0) |
483fc7cd | 9369 | { |
df58fc94 | 9370 | macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9371 | break; |
483fc7cd | 9372 | } |
91d6fa6a | 9373 | rr = (rot < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 CD |
9374 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; |
9375 | rot &= 0x1f; | |
8fc2e39e | 9376 | used_at = 1; |
df58fc94 RS |
9377 | macro_build (NULL, rr, SHFT_FMT, AT, sreg, rot); |
9378 | macro_build (NULL, l, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9379 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
9380 | } |
9381 | break; | |
9382 | ||
252b5132 | 9383 | case M_ROR_I: |
771c7ce4 TS |
9384 | { |
9385 | unsigned int rot; | |
9386 | ||
9387 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9388 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9389 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 9390 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 9391 | { |
df58fc94 | 9392 | macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, rot); |
8fc2e39e | 9393 | break; |
82dd0097 | 9394 | } |
483fc7cd | 9395 | if (rot == 0) |
483fc7cd | 9396 | { |
df58fc94 | 9397 | macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9398 | break; |
483fc7cd | 9399 | } |
8fc2e39e | 9400 | used_at = 1; |
df58fc94 RS |
9401 | macro_build (NULL, "srl", SHFT_FMT, AT, sreg, rot); |
9402 | macro_build (NULL, "sll", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9403 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 | 9404 | } |
252b5132 RH |
9405 | break; |
9406 | ||
252b5132 RH |
9407 | case M_SEQ: |
9408 | if (sreg == 0) | |
67c0d1eb | 9409 | macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16); |
252b5132 | 9410 | else if (treg == 0) |
67c0d1eb | 9411 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
9412 | else |
9413 | { | |
67c0d1eb RS |
9414 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
9415 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 | 9416 | } |
8fc2e39e | 9417 | break; |
252b5132 RH |
9418 | |
9419 | case M_SEQ_I: | |
9420 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
9421 | { | |
67c0d1eb | 9422 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 9423 | break; |
252b5132 RH |
9424 | } |
9425 | if (sreg == 0) | |
9426 | { | |
9427 | as_warn (_("Instruction %s: result is always false"), | |
9428 | ip->insn_mo->name); | |
67c0d1eb | 9429 | move_register (dreg, 0); |
8fc2e39e | 9430 | break; |
252b5132 | 9431 | } |
dd3cbb7e NC |
9432 | if (CPU_HAS_SEQ (mips_opts.arch) |
9433 | && -512 <= imm_expr.X_add_number | |
9434 | && imm_expr.X_add_number < 512) | |
9435 | { | |
9436 | macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg, | |
750bdd57 | 9437 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
9438 | break; |
9439 | } | |
252b5132 RH |
9440 | if (imm_expr.X_op == O_constant |
9441 | && imm_expr.X_add_number >= 0 | |
9442 | && imm_expr.X_add_number < 0x10000) | |
9443 | { | |
67c0d1eb | 9444 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
9445 | } |
9446 | else if (imm_expr.X_op == O_constant | |
9447 | && imm_expr.X_add_number > -0x8000 | |
9448 | && imm_expr.X_add_number < 0) | |
9449 | { | |
9450 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 9451 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 9452 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 | 9453 | } |
dd3cbb7e NC |
9454 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
9455 | { | |
9456 | used_at = 1; | |
9457 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); | |
9458 | macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT); | |
9459 | break; | |
9460 | } | |
252b5132 RH |
9461 | else |
9462 | { | |
67c0d1eb RS |
9463 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9464 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
9465 | used_at = 1; |
9466 | } | |
67c0d1eb | 9467 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 9468 | break; |
252b5132 RH |
9469 | |
9470 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
9471 | s = "slt"; | |
9472 | goto sge; | |
9473 | case M_SGEU: | |
9474 | s = "sltu"; | |
9475 | sge: | |
67c0d1eb RS |
9476 | macro_build (NULL, s, "d,v,t", dreg, sreg, treg); |
9477 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 9478 | break; |
252b5132 RH |
9479 | |
9480 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
9481 | case M_SGEU_I: | |
9482 | if (imm_expr.X_op == O_constant | |
9483 | && imm_expr.X_add_number >= -0x8000 | |
9484 | && imm_expr.X_add_number < 0x8000) | |
9485 | { | |
67c0d1eb RS |
9486 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
9487 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
9488 | } |
9489 | else | |
9490 | { | |
67c0d1eb RS |
9491 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9492 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", | |
9493 | dreg, sreg, AT); | |
252b5132 RH |
9494 | used_at = 1; |
9495 | } | |
67c0d1eb | 9496 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 9497 | break; |
252b5132 RH |
9498 | |
9499 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
9500 | s = "slt"; | |
9501 | goto sgt; | |
9502 | case M_SGTU: | |
9503 | s = "sltu"; | |
9504 | sgt: | |
67c0d1eb | 9505 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
8fc2e39e | 9506 | break; |
252b5132 RH |
9507 | |
9508 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
9509 | s = "slt"; | |
9510 | goto sgti; | |
9511 | case M_SGTU_I: | |
9512 | s = "sltu"; | |
9513 | sgti: | |
8fc2e39e | 9514 | used_at = 1; |
67c0d1eb RS |
9515 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9516 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
252b5132 RH |
9517 | break; |
9518 | ||
2396cfb9 | 9519 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
9520 | s = "slt"; |
9521 | goto sle; | |
9522 | case M_SLEU: | |
9523 | s = "sltu"; | |
9524 | sle: | |
67c0d1eb RS |
9525 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
9526 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 9527 | break; |
252b5132 | 9528 | |
2396cfb9 | 9529 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
9530 | s = "slt"; |
9531 | goto slei; | |
9532 | case M_SLEU_I: | |
9533 | s = "sltu"; | |
9534 | slei: | |
8fc2e39e | 9535 | used_at = 1; |
67c0d1eb RS |
9536 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9537 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
9538 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
9539 | break; |
9540 | ||
9541 | case M_SLT_I: | |
9542 | if (imm_expr.X_op == O_constant | |
9543 | && imm_expr.X_add_number >= -0x8000 | |
9544 | && imm_expr.X_add_number < 0x8000) | |
9545 | { | |
67c0d1eb | 9546 | macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 9547 | break; |
252b5132 | 9548 | } |
8fc2e39e | 9549 | used_at = 1; |
67c0d1eb RS |
9550 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9551 | macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
9552 | break; |
9553 | ||
9554 | case M_SLTU_I: | |
9555 | if (imm_expr.X_op == O_constant | |
9556 | && imm_expr.X_add_number >= -0x8000 | |
9557 | && imm_expr.X_add_number < 0x8000) | |
9558 | { | |
67c0d1eb | 9559 | macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg, |
17a2f251 | 9560 | BFD_RELOC_LO16); |
8fc2e39e | 9561 | break; |
252b5132 | 9562 | } |
8fc2e39e | 9563 | used_at = 1; |
67c0d1eb RS |
9564 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9565 | macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
9566 | break; |
9567 | ||
9568 | case M_SNE: | |
9569 | if (sreg == 0) | |
67c0d1eb | 9570 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg); |
252b5132 | 9571 | else if (treg == 0) |
67c0d1eb | 9572 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
9573 | else |
9574 | { | |
67c0d1eb RS |
9575 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
9576 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
252b5132 | 9577 | } |
8fc2e39e | 9578 | break; |
252b5132 RH |
9579 | |
9580 | case M_SNE_I: | |
9581 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
9582 | { | |
67c0d1eb | 9583 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
8fc2e39e | 9584 | break; |
252b5132 RH |
9585 | } |
9586 | if (sreg == 0) | |
9587 | { | |
9588 | as_warn (_("Instruction %s: result is always true"), | |
9589 | ip->insn_mo->name); | |
67c0d1eb RS |
9590 | macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", |
9591 | dreg, 0, BFD_RELOC_LO16); | |
8fc2e39e | 9592 | break; |
252b5132 | 9593 | } |
dd3cbb7e NC |
9594 | if (CPU_HAS_SEQ (mips_opts.arch) |
9595 | && -512 <= imm_expr.X_add_number | |
9596 | && imm_expr.X_add_number < 512) | |
9597 | { | |
9598 | macro_build (NULL, "snei", "t,r,+Q", dreg, sreg, | |
750bdd57 | 9599 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
9600 | break; |
9601 | } | |
252b5132 RH |
9602 | if (imm_expr.X_op == O_constant |
9603 | && imm_expr.X_add_number >= 0 | |
9604 | && imm_expr.X_add_number < 0x10000) | |
9605 | { | |
67c0d1eb | 9606 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
9607 | } |
9608 | else if (imm_expr.X_op == O_constant | |
9609 | && imm_expr.X_add_number > -0x8000 | |
9610 | && imm_expr.X_add_number < 0) | |
9611 | { | |
9612 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 9613 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 9614 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 | 9615 | } |
dd3cbb7e NC |
9616 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
9617 | { | |
9618 | used_at = 1; | |
9619 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); | |
9620 | macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT); | |
9621 | break; | |
9622 | } | |
252b5132 RH |
9623 | else |
9624 | { | |
67c0d1eb RS |
9625 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9626 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
9627 | used_at = 1; |
9628 | } | |
67c0d1eb | 9629 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); |
8fc2e39e | 9630 | break; |
252b5132 | 9631 | |
df58fc94 RS |
9632 | case M_SUB_I: |
9633 | s = "addi"; | |
9634 | s2 = "sub"; | |
9635 | goto do_subi; | |
9636 | case M_SUBU_I: | |
9637 | s = "addiu"; | |
9638 | s2 = "subu"; | |
9639 | goto do_subi; | |
252b5132 RH |
9640 | case M_DSUB_I: |
9641 | dbl = 1; | |
df58fc94 RS |
9642 | s = "daddi"; |
9643 | s2 = "dsub"; | |
9644 | if (!mips_opts.micromips) | |
9645 | goto do_subi; | |
252b5132 | 9646 | if (imm_expr.X_op == O_constant |
df58fc94 RS |
9647 | && imm_expr.X_add_number > -0x200 |
9648 | && imm_expr.X_add_number <= 0x200) | |
252b5132 | 9649 | { |
df58fc94 | 9650 | macro_build (NULL, s, "t,r,.", dreg, sreg, -imm_expr.X_add_number); |
8fc2e39e | 9651 | break; |
252b5132 | 9652 | } |
df58fc94 | 9653 | goto do_subi_i; |
252b5132 RH |
9654 | case M_DSUBU_I: |
9655 | dbl = 1; | |
df58fc94 RS |
9656 | s = "daddiu"; |
9657 | s2 = "dsubu"; | |
9658 | do_subi: | |
252b5132 RH |
9659 | if (imm_expr.X_op == O_constant |
9660 | && imm_expr.X_add_number > -0x8000 | |
9661 | && imm_expr.X_add_number <= 0x8000) | |
9662 | { | |
9663 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
df58fc94 | 9664 | macro_build (&imm_expr, s, "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 9665 | break; |
252b5132 | 9666 | } |
df58fc94 | 9667 | do_subi_i: |
8fc2e39e | 9668 | used_at = 1; |
67c0d1eb | 9669 | load_register (AT, &imm_expr, dbl); |
df58fc94 | 9670 | macro_build (NULL, s2, "d,v,t", dreg, sreg, AT); |
252b5132 RH |
9671 | break; |
9672 | ||
9673 | case M_TEQ_I: | |
9674 | s = "teq"; | |
9675 | goto trap; | |
9676 | case M_TGE_I: | |
9677 | s = "tge"; | |
9678 | goto trap; | |
9679 | case M_TGEU_I: | |
9680 | s = "tgeu"; | |
9681 | goto trap; | |
9682 | case M_TLT_I: | |
9683 | s = "tlt"; | |
9684 | goto trap; | |
9685 | case M_TLTU_I: | |
9686 | s = "tltu"; | |
9687 | goto trap; | |
9688 | case M_TNE_I: | |
9689 | s = "tne"; | |
9690 | trap: | |
8fc2e39e | 9691 | used_at = 1; |
67c0d1eb RS |
9692 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9693 | macro_build (NULL, s, "s,t", sreg, AT); | |
252b5132 RH |
9694 | break; |
9695 | ||
252b5132 | 9696 | case M_TRUNCWS: |
43841e91 | 9697 | case M_TRUNCWD: |
df58fc94 | 9698 | gas_assert (!mips_opts.micromips); |
9c2799c2 | 9699 | gas_assert (mips_opts.isa == ISA_MIPS1); |
8fc2e39e | 9700 | used_at = 1; |
252b5132 RH |
9701 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
9702 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
9703 | ||
9704 | /* | |
9705 | * Is the double cfc1 instruction a bug in the mips assembler; | |
9706 | * or is there a reason for it? | |
9707 | */ | |
7d10b47d | 9708 | start_noreorder (); |
67c0d1eb RS |
9709 | macro_build (NULL, "cfc1", "t,G", treg, RA); |
9710 | macro_build (NULL, "cfc1", "t,G", treg, RA); | |
9711 | macro_build (NULL, "nop", ""); | |
252b5132 | 9712 | expr1.X_add_number = 3; |
67c0d1eb | 9713 | macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16); |
252b5132 | 9714 | expr1.X_add_number = 2; |
67c0d1eb RS |
9715 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
9716 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
9717 | macro_build (NULL, "nop", ""); | |
9718 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
9719 | dreg, sreg); | |
9720 | macro_build (NULL, "ctc1", "t,G", treg, RA); | |
9721 | macro_build (NULL, "nop", ""); | |
7d10b47d | 9722 | end_noreorder (); |
252b5132 RH |
9723 | break; |
9724 | ||
df58fc94 RS |
9725 | case M_ULH_A: |
9726 | ab = 1; | |
252b5132 RH |
9727 | case M_ULH: |
9728 | s = "lb"; | |
df58fc94 RS |
9729 | s2 = "lbu"; |
9730 | off = 1; | |
9731 | goto uld_st; | |
9732 | case M_ULHU_A: | |
9733 | ab = 1; | |
252b5132 RH |
9734 | case M_ULHU: |
9735 | s = "lbu"; | |
df58fc94 RS |
9736 | s2 = "lbu"; |
9737 | off = 1; | |
9738 | goto uld_st; | |
9739 | case M_ULW_A: | |
9740 | ab = 1; | |
9741 | case M_ULW: | |
9742 | s = "lwl"; | |
9743 | s2 = "lwr"; | |
9744 | off12 = mips_opts.micromips; | |
9745 | off = 3; | |
9746 | goto uld_st; | |
9747 | case M_ULD_A: | |
9748 | ab = 1; | |
252b5132 RH |
9749 | case M_ULD: |
9750 | s = "ldl"; | |
9751 | s2 = "ldr"; | |
df58fc94 | 9752 | off12 = mips_opts.micromips; |
252b5132 | 9753 | off = 7; |
df58fc94 RS |
9754 | goto uld_st; |
9755 | case M_USH_A: | |
9756 | ab = 1; | |
9757 | case M_USH: | |
9758 | s = "sb"; | |
9759 | s2 = "sb"; | |
9760 | off = 1; | |
9761 | ust = 1; | |
9762 | goto uld_st; | |
9763 | case M_USW_A: | |
9764 | ab = 1; | |
9765 | case M_USW: | |
9766 | s = "swl"; | |
9767 | s2 = "swr"; | |
9768 | off12 = mips_opts.micromips; | |
252b5132 | 9769 | off = 3; |
df58fc94 RS |
9770 | ust = 1; |
9771 | goto uld_st; | |
9772 | case M_USD_A: | |
9773 | ab = 1; | |
9774 | case M_USD: | |
9775 | s = "sdl"; | |
9776 | s2 = "sdr"; | |
9777 | off12 = mips_opts.micromips; | |
9778 | off = 7; | |
9779 | ust = 1; | |
9780 | ||
9781 | uld_st: | |
9782 | if (!ab && offset_expr.X_add_number >= 0x8000 - off) | |
f71d0d44 | 9783 | as_bad (_("Operand overflow")); |
df58fc94 RS |
9784 | |
9785 | ep = &offset_expr; | |
9786 | expr1.X_add_number = 0; | |
9787 | if (ab) | |
9788 | { | |
9789 | used_at = 1; | |
9790 | tempreg = AT; | |
9791 | load_address (tempreg, ep, &used_at); | |
9792 | if (breg != 0) | |
9793 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
9794 | tempreg, tempreg, breg); | |
9795 | breg = tempreg; | |
9796 | tempreg = treg; | |
9797 | ep = &expr1; | |
9798 | } | |
9799 | else if (off12 | |
9800 | && (offset_expr.X_op != O_constant | |
9801 | || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number) | |
9802 | || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number + off))) | |
9803 | { | |
9804 | used_at = 1; | |
9805 | tempreg = AT; | |
9806 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, | |
9807 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]); | |
9808 | breg = tempreg; | |
9809 | tempreg = treg; | |
9810 | ep = &expr1; | |
9811 | } | |
9812 | else if (!ust && treg == breg) | |
8fc2e39e TS |
9813 | { |
9814 | used_at = 1; | |
9815 | tempreg = AT; | |
9816 | } | |
252b5132 | 9817 | else |
df58fc94 | 9818 | tempreg = treg; |
af22f5b2 | 9819 | |
df58fc94 RS |
9820 | if (off == 1) |
9821 | goto ulh_sh; | |
252b5132 | 9822 | |
90ecf173 | 9823 | if (!target_big_endian) |
df58fc94 RS |
9824 | ep->X_add_number += off; |
9825 | if (!off12) | |
9826 | macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); | |
252b5132 | 9827 | else |
df58fc94 RS |
9828 | macro_build (NULL, s, "t,~(b)", |
9829 | tempreg, (unsigned long) ep->X_add_number, breg); | |
9830 | ||
90ecf173 | 9831 | if (!target_big_endian) |
df58fc94 | 9832 | ep->X_add_number -= off; |
252b5132 | 9833 | else |
df58fc94 RS |
9834 | ep->X_add_number += off; |
9835 | if (!off12) | |
9836 | macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); | |
9837 | else | |
9838 | macro_build (NULL, s2, "t,~(b)", | |
9839 | tempreg, (unsigned long) ep->X_add_number, breg); | |
252b5132 | 9840 | |
df58fc94 RS |
9841 | /* If necessary, move the result in tempreg to the final destination. */ |
9842 | if (!ust && treg != tempreg) | |
9843 | { | |
9844 | /* Protect second load's delay slot. */ | |
9845 | load_delay_nop (); | |
9846 | move_register (treg, tempreg); | |
9847 | } | |
8fc2e39e | 9848 | break; |
252b5132 | 9849 | |
df58fc94 | 9850 | ulh_sh: |
d6bc6245 | 9851 | used_at = 1; |
df58fc94 RS |
9852 | if (target_big_endian == ust) |
9853 | ep->X_add_number += off; | |
9854 | tempreg = ust || ab ? treg : AT; | |
9855 | macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); | |
9856 | ||
9857 | /* For halfword transfers we need a temporary register to shuffle | |
9858 | bytes. Unfortunately for M_USH_A we have none available before | |
9859 | the next store as AT holds the base address. We deal with this | |
9860 | case by clobbering TREG and then restoring it as with ULH. */ | |
9861 | tempreg = ust == ab ? treg : AT; | |
9862 | if (ust) | |
9863 | macro_build (NULL, "srl", SHFT_FMT, tempreg, treg, 8); | |
9864 | ||
9865 | if (target_big_endian == ust) | |
9866 | ep->X_add_number -= off; | |
252b5132 | 9867 | else |
df58fc94 RS |
9868 | ep->X_add_number += off; |
9869 | macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); | |
252b5132 | 9870 | |
df58fc94 RS |
9871 | /* For M_USH_A re-retrieve the LSB. */ |
9872 | if (ust && ab) | |
9873 | { | |
9874 | if (target_big_endian) | |
9875 | ep->X_add_number += off; | |
9876 | else | |
9877 | ep->X_add_number -= off; | |
9878 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); | |
9879 | } | |
9880 | /* For ULH and M_USH_A OR the LSB in. */ | |
9881 | if (!ust || ab) | |
9882 | { | |
9883 | tempreg = !ab ? AT : treg; | |
9884 | macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8); | |
9885 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
9886 | } | |
252b5132 RH |
9887 | break; |
9888 | ||
9889 | default: | |
9890 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 9891 | are added dynamically. */ |
252b5132 RH |
9892 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
9893 | break; | |
9894 | } | |
741fe287 | 9895 | if (!mips_opts.at && used_at) |
8fc2e39e | 9896 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
9897 | } |
9898 | ||
9899 | /* Implement macros in mips16 mode. */ | |
9900 | ||
9901 | static void | |
17a2f251 | 9902 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 RH |
9903 | { |
9904 | int mask; | |
9905 | int xreg, yreg, zreg, tmp; | |
252b5132 RH |
9906 | expressionS expr1; |
9907 | int dbl; | |
9908 | const char *s, *s2, *s3; | |
9909 | ||
9910 | mask = ip->insn_mo->mask; | |
9911 | ||
bf12938e RS |
9912 | xreg = MIPS16_EXTRACT_OPERAND (RX, *ip); |
9913 | yreg = MIPS16_EXTRACT_OPERAND (RY, *ip); | |
9914 | zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip); | |
252b5132 | 9915 | |
252b5132 RH |
9916 | expr1.X_op = O_constant; |
9917 | expr1.X_op_symbol = NULL; | |
9918 | expr1.X_add_symbol = NULL; | |
9919 | expr1.X_add_number = 1; | |
9920 | ||
9921 | dbl = 0; | |
9922 | ||
9923 | switch (mask) | |
9924 | { | |
9925 | default: | |
9926 | internalError (); | |
9927 | ||
9928 | case M_DDIV_3: | |
9929 | dbl = 1; | |
9930 | case M_DIV_3: | |
9931 | s = "mflo"; | |
9932 | goto do_div3; | |
9933 | case M_DREM_3: | |
9934 | dbl = 1; | |
9935 | case M_REM_3: | |
9936 | s = "mfhi"; | |
9937 | do_div3: | |
7d10b47d | 9938 | start_noreorder (); |
67c0d1eb | 9939 | macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg); |
252b5132 | 9940 | expr1.X_add_number = 2; |
67c0d1eb RS |
9941 | macro_build (&expr1, "bnez", "x,p", yreg); |
9942 | macro_build (NULL, "break", "6", 7); | |
bdaaa2e1 | 9943 | |
252b5132 RH |
9944 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
9945 | since that causes an overflow. We should do that as well, | |
9946 | but I don't see how to do the comparisons without a temporary | |
9947 | register. */ | |
7d10b47d | 9948 | end_noreorder (); |
67c0d1eb | 9949 | macro_build (NULL, s, "x", zreg); |
252b5132 RH |
9950 | break; |
9951 | ||
9952 | case M_DIVU_3: | |
9953 | s = "divu"; | |
9954 | s2 = "mflo"; | |
9955 | goto do_divu3; | |
9956 | case M_REMU_3: | |
9957 | s = "divu"; | |
9958 | s2 = "mfhi"; | |
9959 | goto do_divu3; | |
9960 | case M_DDIVU_3: | |
9961 | s = "ddivu"; | |
9962 | s2 = "mflo"; | |
9963 | goto do_divu3; | |
9964 | case M_DREMU_3: | |
9965 | s = "ddivu"; | |
9966 | s2 = "mfhi"; | |
9967 | do_divu3: | |
7d10b47d | 9968 | start_noreorder (); |
67c0d1eb | 9969 | macro_build (NULL, s, "0,x,y", xreg, yreg); |
252b5132 | 9970 | expr1.X_add_number = 2; |
67c0d1eb RS |
9971 | macro_build (&expr1, "bnez", "x,p", yreg); |
9972 | macro_build (NULL, "break", "6", 7); | |
7d10b47d | 9973 | end_noreorder (); |
67c0d1eb | 9974 | macro_build (NULL, s2, "x", zreg); |
252b5132 RH |
9975 | break; |
9976 | ||
9977 | case M_DMUL: | |
9978 | dbl = 1; | |
9979 | case M_MUL: | |
67c0d1eb RS |
9980 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
9981 | macro_build (NULL, "mflo", "x", zreg); | |
8fc2e39e | 9982 | break; |
252b5132 RH |
9983 | |
9984 | case M_DSUBU_I: | |
9985 | dbl = 1; | |
9986 | goto do_subu; | |
9987 | case M_SUBU_I: | |
9988 | do_subu: | |
9989 | if (imm_expr.X_op != O_constant) | |
9990 | as_bad (_("Unsupported large constant")); | |
9991 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 9992 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
9993 | break; |
9994 | ||
9995 | case M_SUBU_I_2: | |
9996 | if (imm_expr.X_op != O_constant) | |
9997 | as_bad (_("Unsupported large constant")); | |
9998 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 9999 | macro_build (&imm_expr, "addiu", "x,k", xreg); |
252b5132 RH |
10000 | break; |
10001 | ||
10002 | case M_DSUBU_I_2: | |
10003 | if (imm_expr.X_op != O_constant) | |
10004 | as_bad (_("Unsupported large constant")); | |
10005 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10006 | macro_build (&imm_expr, "daddiu", "y,j", yreg); |
252b5132 RH |
10007 | break; |
10008 | ||
10009 | case M_BEQ: | |
10010 | s = "cmp"; | |
10011 | s2 = "bteqz"; | |
10012 | goto do_branch; | |
10013 | case M_BNE: | |
10014 | s = "cmp"; | |
10015 | s2 = "btnez"; | |
10016 | goto do_branch; | |
10017 | case M_BLT: | |
10018 | s = "slt"; | |
10019 | s2 = "btnez"; | |
10020 | goto do_branch; | |
10021 | case M_BLTU: | |
10022 | s = "sltu"; | |
10023 | s2 = "btnez"; | |
10024 | goto do_branch; | |
10025 | case M_BLE: | |
10026 | s = "slt"; | |
10027 | s2 = "bteqz"; | |
10028 | goto do_reverse_branch; | |
10029 | case M_BLEU: | |
10030 | s = "sltu"; | |
10031 | s2 = "bteqz"; | |
10032 | goto do_reverse_branch; | |
10033 | case M_BGE: | |
10034 | s = "slt"; | |
10035 | s2 = "bteqz"; | |
10036 | goto do_branch; | |
10037 | case M_BGEU: | |
10038 | s = "sltu"; | |
10039 | s2 = "bteqz"; | |
10040 | goto do_branch; | |
10041 | case M_BGT: | |
10042 | s = "slt"; | |
10043 | s2 = "btnez"; | |
10044 | goto do_reverse_branch; | |
10045 | case M_BGTU: | |
10046 | s = "sltu"; | |
10047 | s2 = "btnez"; | |
10048 | ||
10049 | do_reverse_branch: | |
10050 | tmp = xreg; | |
10051 | xreg = yreg; | |
10052 | yreg = tmp; | |
10053 | ||
10054 | do_branch: | |
67c0d1eb RS |
10055 | macro_build (NULL, s, "x,y", xreg, yreg); |
10056 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
10057 | break; |
10058 | ||
10059 | case M_BEQ_I: | |
10060 | s = "cmpi"; | |
10061 | s2 = "bteqz"; | |
10062 | s3 = "x,U"; | |
10063 | goto do_branch_i; | |
10064 | case M_BNE_I: | |
10065 | s = "cmpi"; | |
10066 | s2 = "btnez"; | |
10067 | s3 = "x,U"; | |
10068 | goto do_branch_i; | |
10069 | case M_BLT_I: | |
10070 | s = "slti"; | |
10071 | s2 = "btnez"; | |
10072 | s3 = "x,8"; | |
10073 | goto do_branch_i; | |
10074 | case M_BLTU_I: | |
10075 | s = "sltiu"; | |
10076 | s2 = "btnez"; | |
10077 | s3 = "x,8"; | |
10078 | goto do_branch_i; | |
10079 | case M_BLE_I: | |
10080 | s = "slti"; | |
10081 | s2 = "btnez"; | |
10082 | s3 = "x,8"; | |
10083 | goto do_addone_branch_i; | |
10084 | case M_BLEU_I: | |
10085 | s = "sltiu"; | |
10086 | s2 = "btnez"; | |
10087 | s3 = "x,8"; | |
10088 | goto do_addone_branch_i; | |
10089 | case M_BGE_I: | |
10090 | s = "slti"; | |
10091 | s2 = "bteqz"; | |
10092 | s3 = "x,8"; | |
10093 | goto do_branch_i; | |
10094 | case M_BGEU_I: | |
10095 | s = "sltiu"; | |
10096 | s2 = "bteqz"; | |
10097 | s3 = "x,8"; | |
10098 | goto do_branch_i; | |
10099 | case M_BGT_I: | |
10100 | s = "slti"; | |
10101 | s2 = "bteqz"; | |
10102 | s3 = "x,8"; | |
10103 | goto do_addone_branch_i; | |
10104 | case M_BGTU_I: | |
10105 | s = "sltiu"; | |
10106 | s2 = "bteqz"; | |
10107 | s3 = "x,8"; | |
10108 | ||
10109 | do_addone_branch_i: | |
10110 | if (imm_expr.X_op != O_constant) | |
10111 | as_bad (_("Unsupported large constant")); | |
10112 | ++imm_expr.X_add_number; | |
10113 | ||
10114 | do_branch_i: | |
67c0d1eb RS |
10115 | macro_build (&imm_expr, s, s3, xreg); |
10116 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
10117 | break; |
10118 | ||
10119 | case M_ABS: | |
10120 | expr1.X_add_number = 0; | |
67c0d1eb | 10121 | macro_build (&expr1, "slti", "x,8", yreg); |
252b5132 | 10122 | if (xreg != yreg) |
67c0d1eb | 10123 | move_register (xreg, yreg); |
252b5132 | 10124 | expr1.X_add_number = 2; |
67c0d1eb RS |
10125 | macro_build (&expr1, "bteqz", "p"); |
10126 | macro_build (NULL, "neg", "x,w", xreg, xreg); | |
252b5132 RH |
10127 | } |
10128 | } | |
10129 | ||
10130 | /* For consistency checking, verify that all bits are specified either | |
10131 | by the match/mask part of the instruction definition, or by the | |
10132 | operand list. */ | |
10133 | static int | |
17a2f251 | 10134 | validate_mips_insn (const struct mips_opcode *opc) |
252b5132 RH |
10135 | { |
10136 | const char *p = opc->args; | |
10137 | char c; | |
10138 | unsigned long used_bits = opc->mask; | |
10139 | ||
10140 | if ((used_bits & opc->match) != opc->match) | |
10141 | { | |
10142 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
10143 | opc->name, opc->args); | |
10144 | return 0; | |
10145 | } | |
10146 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
10147 | while (*p) | |
10148 | switch (c = *p++) | |
10149 | { | |
10150 | case ',': break; | |
10151 | case '(': break; | |
10152 | case ')': break; | |
af7ee8bf CD |
10153 | case '+': |
10154 | switch (c = *p++) | |
10155 | { | |
9bcd4f99 TS |
10156 | case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break; |
10157 | case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break; | |
10158 | case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break; | |
10159 | case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break; | |
af7ee8bf CD |
10160 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
10161 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
10162 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
bbcc0807 CD |
10163 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); |
10164 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
5f74bc13 CD |
10165 | case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
10166 | case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
10167 | case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
10168 | case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
10169 | case 'I': break; | |
ef2e4d86 CF |
10170 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; |
10171 | case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT); | |
10172 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
bb35fb24 NC |
10173 | case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; |
10174 | case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; | |
10175 | case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; | |
10176 | case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; | |
dd3cbb7e | 10177 | case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break; |
bb35fb24 NC |
10178 | case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break; |
10179 | case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break; | |
98675402 RS |
10180 | case 'z': USE_BITS (OP_MASK_RZ, OP_SH_RZ); break; |
10181 | case 'Z': USE_BITS (OP_MASK_FZ, OP_SH_FZ); break; | |
10182 | case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break; | |
10183 | case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break; | |
10184 | case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break; | |
bb35fb24 | 10185 | |
af7ee8bf CD |
10186 | default: |
10187 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
10188 | c, opc->name, opc->args); | |
10189 | return 0; | |
10190 | } | |
10191 | break; | |
252b5132 RH |
10192 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
10193 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
10194 | case 'A': break; | |
4372b673 | 10195 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
10196 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
10197 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
10198 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
10199 | case 'F': break; | |
10200 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 10201 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 10202 | case 'I': break; |
e972090a | 10203 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 10204 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
10205 | case 'L': break; |
10206 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
10207 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
10208 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
10209 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
10210 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
10211 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
10212 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
10213 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
10214 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
10215 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
10216 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
10217 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
10218 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
10219 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
10220 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10221 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
10222 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
10223 | case 'f': break; | |
10224 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
10225 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
10226 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
10227 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
10228 | case 'l': break; | |
10229 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
10230 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
10231 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
10232 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10233 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10234 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
10235 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
10236 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10237 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
10238 | case 'x': break; | |
10239 | case 'z': break; | |
10240 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
10241 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
10242 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
10243 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
10244 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
10245 | case '[': break; | |
10246 | case ']': break; | |
620edafd | 10247 | case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8b082fb1 | 10248 | case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break; |
74cd071d CF |
10249 | case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break; |
10250 | case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break; | |
10251 | case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break; | |
10252 | case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10253 | case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break; | |
10254 | case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break; | |
10255 | case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break; | |
10256 | case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break; | |
10257 | case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break; | |
10258 | case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break; | |
10259 | case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break; | |
ef2e4d86 CF |
10260 | case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break; |
10261 | case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break; | |
10262 | case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break; | |
10263 | case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break; | |
10264 | case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
252b5132 RH |
10265 | default: |
10266 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
10267 | c, opc->name, opc->args); | |
10268 | return 0; | |
10269 | } | |
10270 | #undef USE_BITS | |
10271 | if (used_bits != 0xffffffff) | |
10272 | { | |
10273 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
10274 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
10275 | return 0; | |
10276 | } | |
10277 | return 1; | |
10278 | } | |
10279 | ||
df58fc94 RS |
10280 | /* For consistency checking, verify that the length implied matches the |
10281 | major opcode and that all bits are specified either by the match/mask | |
10282 | part of the instruction definition, or by the operand list. */ | |
10283 | ||
10284 | static int | |
10285 | validate_micromips_insn (const struct mips_opcode *opc) | |
10286 | { | |
10287 | unsigned long match = opc->match; | |
10288 | unsigned long mask = opc->mask; | |
10289 | const char *p = opc->args; | |
10290 | unsigned long insn_bits; | |
10291 | unsigned long used_bits; | |
10292 | unsigned long major; | |
10293 | unsigned int length; | |
10294 | char e; | |
10295 | char c; | |
10296 | ||
10297 | if ((mask & match) != match) | |
10298 | { | |
10299 | as_bad (_("Internal error: bad microMIPS opcode (mask error): %s %s"), | |
10300 | opc->name, opc->args); | |
10301 | return 0; | |
10302 | } | |
10303 | length = micromips_insn_length (opc); | |
10304 | if (length != 2 && length != 4) | |
10305 | { | |
10306 | as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): " | |
10307 | "%s %s"), length, opc->name, opc->args); | |
10308 | return 0; | |
10309 | } | |
10310 | major = match >> (10 + 8 * (length - 2)); | |
10311 | if ((length == 2 && (major & 7) != 1 && (major & 6) != 2) | |
10312 | || (length == 4 && (major & 7) != 0 && (major & 4) != 4)) | |
10313 | { | |
10314 | as_bad (_("Internal error: bad microMIPS opcode " | |
10315 | "(opcode/length mismatch): %s %s"), opc->name, opc->args); | |
10316 | return 0; | |
10317 | } | |
10318 | ||
10319 | /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */ | |
10320 | insn_bits = 1 << 4 * length; | |
10321 | insn_bits <<= 4 * length; | |
10322 | insn_bits -= 1; | |
10323 | used_bits = mask; | |
10324 | #define USE_BITS(field) \ | |
10325 | (used_bits |= MICROMIPSOP_MASK_##field << MICROMIPSOP_SH_##field) | |
10326 | while (*p) | |
10327 | switch (c = *p++) | |
10328 | { | |
10329 | case ',': break; | |
10330 | case '(': break; | |
10331 | case ')': break; | |
10332 | case '+': | |
10333 | e = c; | |
10334 | switch (c = *p++) | |
10335 | { | |
10336 | case 'A': USE_BITS (EXTLSB); break; | |
10337 | case 'B': USE_BITS (INSMSB); break; | |
10338 | case 'C': USE_BITS (EXTMSBD); break; | |
10339 | case 'D': USE_BITS (RS); USE_BITS (SEL); break; | |
10340 | case 'E': USE_BITS (EXTLSB); break; | |
10341 | case 'F': USE_BITS (INSMSB); break; | |
10342 | case 'G': USE_BITS (EXTMSBD); break; | |
10343 | case 'H': USE_BITS (EXTMSBD); break; | |
10344 | default: | |
10345 | as_bad (_("Internal error: bad mips opcode " | |
10346 | "(unknown extension operand type `%c%c'): %s %s"), | |
10347 | e, c, opc->name, opc->args); | |
10348 | return 0; | |
10349 | } | |
10350 | break; | |
10351 | case 'm': | |
10352 | e = c; | |
10353 | switch (c = *p++) | |
10354 | { | |
10355 | case 'A': USE_BITS (IMMA); break; | |
10356 | case 'B': USE_BITS (IMMB); break; | |
10357 | case 'C': USE_BITS (IMMC); break; | |
10358 | case 'D': USE_BITS (IMMD); break; | |
10359 | case 'E': USE_BITS (IMME); break; | |
10360 | case 'F': USE_BITS (IMMF); break; | |
10361 | case 'G': USE_BITS (IMMG); break; | |
10362 | case 'H': USE_BITS (IMMH); break; | |
10363 | case 'I': USE_BITS (IMMI); break; | |
10364 | case 'J': USE_BITS (IMMJ); break; | |
10365 | case 'L': USE_BITS (IMML); break; | |
10366 | case 'M': USE_BITS (IMMM); break; | |
10367 | case 'N': USE_BITS (IMMN); break; | |
10368 | case 'O': USE_BITS (IMMO); break; | |
10369 | case 'P': USE_BITS (IMMP); break; | |
10370 | case 'Q': USE_BITS (IMMQ); break; | |
10371 | case 'U': USE_BITS (IMMU); break; | |
10372 | case 'W': USE_BITS (IMMW); break; | |
10373 | case 'X': USE_BITS (IMMX); break; | |
10374 | case 'Y': USE_BITS (IMMY); break; | |
10375 | case 'Z': break; | |
10376 | case 'a': break; | |
10377 | case 'b': USE_BITS (MB); break; | |
10378 | case 'c': USE_BITS (MC); break; | |
10379 | case 'd': USE_BITS (MD); break; | |
10380 | case 'e': USE_BITS (ME); break; | |
10381 | case 'f': USE_BITS (MF); break; | |
10382 | case 'g': USE_BITS (MG); break; | |
10383 | case 'h': USE_BITS (MH); break; | |
10384 | case 'i': USE_BITS (MI); break; | |
10385 | case 'j': USE_BITS (MJ); break; | |
10386 | case 'l': USE_BITS (ML); break; | |
10387 | case 'm': USE_BITS (MM); break; | |
10388 | case 'n': USE_BITS (MN); break; | |
10389 | case 'p': USE_BITS (MP); break; | |
10390 | case 'q': USE_BITS (MQ); break; | |
10391 | case 'r': break; | |
10392 | case 's': break; | |
10393 | case 't': break; | |
10394 | case 'x': break; | |
10395 | case 'y': break; | |
10396 | case 'z': break; | |
10397 | default: | |
10398 | as_bad (_("Internal error: bad mips opcode " | |
10399 | "(unknown extension operand type `%c%c'): %s %s"), | |
10400 | e, c, opc->name, opc->args); | |
10401 | return 0; | |
10402 | } | |
10403 | break; | |
10404 | case '.': USE_BITS (OFFSET10); break; | |
10405 | case '1': USE_BITS (STYPE); break; | |
10406 | case '<': USE_BITS (SHAMT); break; | |
10407 | case '>': USE_BITS (SHAMT); break; | |
10408 | case 'B': USE_BITS (CODE10); break; | |
10409 | case 'C': USE_BITS (COPZ); break; | |
10410 | case 'D': USE_BITS (FD); break; | |
10411 | case 'E': USE_BITS (RT); break; | |
10412 | case 'G': USE_BITS (RS); break; | |
10413 | case 'H': USE_BITS (SEL); break; | |
10414 | case 'K': USE_BITS (RS); break; | |
10415 | case 'M': USE_BITS (CCC); break; | |
10416 | case 'N': USE_BITS (BCC); break; | |
10417 | case 'R': USE_BITS (FR); break; | |
10418 | case 'S': USE_BITS (FS); break; | |
10419 | case 'T': USE_BITS (FT); break; | |
10420 | case 'V': USE_BITS (FS); break; | |
10421 | case 'a': USE_BITS (TARGET); break; | |
10422 | case 'b': USE_BITS (RS); break; | |
10423 | case 'c': USE_BITS (CODE); break; | |
10424 | case 'd': USE_BITS (RD); break; | |
10425 | case 'h': USE_BITS (PREFX); break; | |
10426 | case 'i': USE_BITS (IMMEDIATE); break; | |
10427 | case 'j': USE_BITS (DELTA); break; | |
10428 | case 'k': USE_BITS (CACHE); break; | |
10429 | case 'n': USE_BITS (RT); break; | |
10430 | case 'o': USE_BITS (DELTA); break; | |
10431 | case 'p': USE_BITS (DELTA); break; | |
10432 | case 'q': USE_BITS (CODE2); break; | |
10433 | case 'r': USE_BITS (RS); break; | |
10434 | case 's': USE_BITS (RS); break; | |
10435 | case 't': USE_BITS (RT); break; | |
10436 | case 'u': USE_BITS (IMMEDIATE); break; | |
10437 | case 'v': USE_BITS (RS); break; | |
10438 | case 'w': USE_BITS (RT); break; | |
10439 | case 'y': USE_BITS (RS3); break; | |
10440 | case 'z': break; | |
10441 | case '|': USE_BITS (TRAP); break; | |
10442 | case '~': USE_BITS (OFFSET12); break; | |
10443 | default: | |
10444 | as_bad (_("Internal error: bad microMIPS opcode " | |
10445 | "(unknown operand type `%c'): %s %s"), | |
10446 | c, opc->name, opc->args); | |
10447 | return 0; | |
10448 | } | |
10449 | #undef USE_BITS | |
10450 | if (used_bits != insn_bits) | |
10451 | { | |
10452 | if (~used_bits & insn_bits) | |
10453 | as_bad (_("Internal error: bad microMIPS opcode " | |
10454 | "(bits 0x%lx undefined): %s %s"), | |
10455 | ~used_bits & insn_bits, opc->name, opc->args); | |
10456 | if (used_bits & ~insn_bits) | |
10457 | as_bad (_("Internal error: bad microMIPS opcode " | |
10458 | "(bits 0x%lx defined): %s %s"), | |
10459 | used_bits & ~insn_bits, opc->name, opc->args); | |
10460 | return 0; | |
10461 | } | |
10462 | return 1; | |
10463 | } | |
10464 | ||
9bcd4f99 TS |
10465 | /* UDI immediates. */ |
10466 | struct mips_immed { | |
10467 | char type; | |
10468 | unsigned int shift; | |
10469 | unsigned long mask; | |
10470 | const char * desc; | |
10471 | }; | |
10472 | ||
10473 | static const struct mips_immed mips_immed[] = { | |
10474 | { '1', OP_SH_UDI1, OP_MASK_UDI1, 0}, | |
10475 | { '2', OP_SH_UDI2, OP_MASK_UDI2, 0}, | |
10476 | { '3', OP_SH_UDI3, OP_MASK_UDI3, 0}, | |
10477 | { '4', OP_SH_UDI4, OP_MASK_UDI4, 0}, | |
10478 | { 0,0,0,0 } | |
10479 | }; | |
10480 | ||
7455baf8 TS |
10481 | /* Check whether an odd floating-point register is allowed. */ |
10482 | static int | |
10483 | mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum) | |
10484 | { | |
10485 | const char *s = insn->name; | |
10486 | ||
10487 | if (insn->pinfo == INSN_MACRO) | |
10488 | /* Let a macro pass, we'll catch it later when it is expanded. */ | |
10489 | return 1; | |
10490 | ||
10491 | if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa)) | |
10492 | { | |
10493 | /* Allow odd registers for single-precision ops. */ | |
10494 | switch (insn->pinfo & (FP_S | FP_D)) | |
10495 | { | |
10496 | case FP_S: | |
10497 | case 0: | |
10498 | return 1; /* both single precision - ok */ | |
10499 | case FP_D: | |
10500 | return 0; /* both double precision - fail */ | |
10501 | default: | |
10502 | break; | |
10503 | } | |
10504 | ||
10505 | /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ | |
10506 | s = strchr (insn->name, '.'); | |
10507 | if (argnum == 2) | |
10508 | s = s != NULL ? strchr (s + 1, '.') : NULL; | |
10509 | return (s != NULL && (s[1] == 'w' || s[1] == 's')); | |
10510 | } | |
10511 | ||
10512 | /* Single-precision coprocessor loads and moves are OK too. */ | |
10513 | if ((insn->pinfo & FP_S) | |
10514 | && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY | |
10515 | | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY))) | |
10516 | return 1; | |
10517 | ||
10518 | return 0; | |
10519 | } | |
10520 | ||
df58fc94 RS |
10521 | /* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive) |
10522 | taking bits from BIT up. */ | |
10523 | static int | |
10524 | expr_const_in_range (expressionS *ep, offsetT min, offsetT max, int bit) | |
10525 | { | |
10526 | return (ep->X_op == O_constant | |
10527 | && (ep->X_add_number & ((1 << bit) - 1)) == 0 | |
10528 | && ep->X_add_number >= min << bit | |
10529 | && ep->X_add_number < max << bit); | |
10530 | } | |
10531 | ||
252b5132 RH |
10532 | /* This routine assembles an instruction into its binary format. As a |
10533 | side effect, it sets one of the global variables imm_reloc or | |
10534 | offset_reloc to the type of relocation to do if one of the operands | |
10535 | is an address expression. */ | |
10536 | ||
10537 | static void | |
17a2f251 | 10538 | mips_ip (char *str, struct mips_cl_insn *ip) |
252b5132 | 10539 | { |
df58fc94 RS |
10540 | bfd_boolean wrong_delay_slot_insns = FALSE; |
10541 | bfd_boolean need_delay_slot_ok = TRUE; | |
10542 | struct mips_opcode *firstinsn = NULL; | |
10543 | const struct mips_opcode *past; | |
10544 | struct hash_control *hash; | |
252b5132 RH |
10545 | char *s; |
10546 | const char *args; | |
43841e91 | 10547 | char c = 0; |
252b5132 RH |
10548 | struct mips_opcode *insn; |
10549 | char *argsStart; | |
10550 | unsigned int regno; | |
34224acf | 10551 | unsigned int lastregno; |
df58fc94 | 10552 | unsigned int destregno = 0; |
af7ee8bf | 10553 | unsigned int lastpos = 0; |
071742cf | 10554 | unsigned int limlo, limhi; |
252b5132 | 10555 | char *s_reset; |
74cd071d | 10556 | offsetT min_range, max_range; |
df58fc94 | 10557 | long opend; |
a40bc9dd | 10558 | char *name; |
707bfff6 TS |
10559 | int argnum; |
10560 | unsigned int rtype; | |
df58fc94 | 10561 | char *dot; |
a40bc9dd | 10562 | long end; |
252b5132 RH |
10563 | |
10564 | insn_error = NULL; | |
10565 | ||
df58fc94 RS |
10566 | if (mips_opts.micromips) |
10567 | { | |
10568 | hash = micromips_op_hash; | |
10569 | past = µmips_opcodes[bfd_micromips_num_opcodes]; | |
10570 | } | |
10571 | else | |
10572 | { | |
10573 | hash = op_hash; | |
10574 | past = &mips_opcodes[NUMOPCODES]; | |
10575 | } | |
10576 | forced_insn_length = 0; | |
252b5132 | 10577 | insn = NULL; |
252b5132 | 10578 | |
df58fc94 | 10579 | /* We first try to match an instruction up to a space or to the end. */ |
a40bc9dd RS |
10580 | for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++) |
10581 | continue; | |
bdaaa2e1 | 10582 | |
a40bc9dd RS |
10583 | /* Make a copy of the instruction so that we can fiddle with it. */ |
10584 | name = alloca (end + 1); | |
10585 | memcpy (name, str, end); | |
10586 | name[end] = '\0'; | |
252b5132 | 10587 | |
df58fc94 RS |
10588 | for (;;) |
10589 | { | |
10590 | insn = (struct mips_opcode *) hash_find (hash, name); | |
10591 | ||
10592 | if (insn != NULL || !mips_opts.micromips) | |
10593 | break; | |
10594 | if (forced_insn_length) | |
10595 | break; | |
10596 | ||
10597 | /* See if there's an instruction size override suffix, | |
10598 | either `16' or `32', at the end of the mnemonic proper, | |
10599 | that defines the operation, i.e. before the first `.' | |
10600 | character if any. Strip it and retry. */ | |
10601 | dot = strchr (name, '.'); | |
10602 | opend = dot != NULL ? dot - name : end; | |
10603 | if (opend < 3) | |
10604 | break; | |
10605 | if (name[opend - 2] == '1' && name[opend - 1] == '6') | |
10606 | forced_insn_length = 2; | |
10607 | else if (name[opend - 2] == '3' && name[opend - 1] == '2') | |
10608 | forced_insn_length = 4; | |
10609 | else | |
10610 | break; | |
10611 | memcpy (name + opend - 2, name + opend, end - opend + 1); | |
10612 | } | |
252b5132 RH |
10613 | if (insn == NULL) |
10614 | { | |
a40bc9dd RS |
10615 | insn_error = _("Unrecognized opcode"); |
10616 | return; | |
252b5132 RH |
10617 | } |
10618 | ||
df58fc94 RS |
10619 | /* For microMIPS instructions placed in a fixed-length branch delay slot |
10620 | we make up to two passes over the relevant fragment of the opcode | |
10621 | table. First we try instructions that meet the delay slot's length | |
10622 | requirement. If none matched, then we retry with the remaining ones | |
10623 | and if one matches, then we use it and then issue an appropriate | |
10624 | warning later on. */ | |
a40bc9dd | 10625 | argsStart = s = str + end; |
252b5132 RH |
10626 | for (;;) |
10627 | { | |
df58fc94 RS |
10628 | bfd_boolean delay_slot_ok; |
10629 | bfd_boolean size_ok; | |
b34976b6 | 10630 | bfd_boolean ok; |
252b5132 | 10631 | |
a40bc9dd | 10632 | gas_assert (strcmp (insn->name, name) == 0); |
252b5132 | 10633 | |
f79e2745 | 10634 | ok = is_opcode_valid (insn); |
df58fc94 RS |
10635 | size_ok = is_size_valid (insn); |
10636 | delay_slot_ok = is_delay_slot_valid (insn); | |
10637 | if (!delay_slot_ok && !wrong_delay_slot_insns) | |
252b5132 | 10638 | { |
df58fc94 RS |
10639 | firstinsn = insn; |
10640 | wrong_delay_slot_insns = TRUE; | |
10641 | } | |
10642 | if (!ok || !size_ok || delay_slot_ok != need_delay_slot_ok) | |
10643 | { | |
10644 | static char buf[256]; | |
10645 | ||
10646 | if (insn + 1 < past && strcmp (insn->name, insn[1].name) == 0) | |
252b5132 RH |
10647 | { |
10648 | ++insn; | |
10649 | continue; | |
10650 | } | |
df58fc94 | 10651 | if (wrong_delay_slot_insns && need_delay_slot_ok) |
beae10d5 | 10652 | { |
df58fc94 RS |
10653 | gas_assert (firstinsn); |
10654 | need_delay_slot_ok = FALSE; | |
10655 | past = insn + 1; | |
10656 | insn = firstinsn; | |
10657 | continue; | |
252b5132 | 10658 | } |
df58fc94 RS |
10659 | |
10660 | if (insn_error) | |
10661 | return; | |
10662 | ||
10663 | if (!ok) | |
10664 | sprintf (buf, _("opcode not supported on this processor: %s (%s)"), | |
10665 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
10666 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
10667 | else | |
10668 | sprintf (buf, _("Unrecognized %u-bit version of microMIPS opcode"), | |
10669 | 8 * forced_insn_length); | |
10670 | insn_error = buf; | |
10671 | ||
10672 | return; | |
252b5132 RH |
10673 | } |
10674 | ||
1e915849 | 10675 | create_insn (ip, insn); |
268f6bed | 10676 | insn_error = NULL; |
707bfff6 | 10677 | argnum = 1; |
24864476 | 10678 | lastregno = 0xffffffff; |
252b5132 RH |
10679 | for (args = insn->args;; ++args) |
10680 | { | |
deec1734 CD |
10681 | int is_mdmx; |
10682 | ||
ad8d3bb3 | 10683 | s += strspn (s, " \t"); |
deec1734 | 10684 | is_mdmx = 0; |
252b5132 RH |
10685 | switch (*args) |
10686 | { | |
10687 | case '\0': /* end of args */ | |
10688 | if (*s == '\0') | |
10689 | return; | |
10690 | break; | |
10691 | ||
90ecf173 | 10692 | case '2': /* DSP 2-bit unsigned immediate in bit 11. */ |
df58fc94 | 10693 | gas_assert (!mips_opts.micromips); |
8b082fb1 TS |
10694 | my_getExpression (&imm_expr, s); |
10695 | check_absolute_expr (ip, &imm_expr); | |
10696 | if ((unsigned long) imm_expr.X_add_number != 1 | |
10697 | && (unsigned long) imm_expr.X_add_number != 3) | |
10698 | { | |
10699 | as_bad (_("BALIGN immediate not 1 or 3 (%lu)"), | |
10700 | (unsigned long) imm_expr.X_add_number); | |
10701 | } | |
df58fc94 | 10702 | INSERT_OPERAND (0, BP, *ip, imm_expr.X_add_number); |
8b082fb1 TS |
10703 | imm_expr.X_op = O_absent; |
10704 | s = expr_end; | |
10705 | continue; | |
10706 | ||
90ecf173 | 10707 | case '3': /* DSP 3-bit unsigned immediate in bit 21. */ |
df58fc94 | 10708 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10709 | my_getExpression (&imm_expr, s); |
10710 | check_absolute_expr (ip, &imm_expr); | |
10711 | if (imm_expr.X_add_number & ~OP_MASK_SA3) | |
10712 | { | |
a9e24354 TS |
10713 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
10714 | OP_MASK_SA3, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 10715 | } |
df58fc94 | 10716 | INSERT_OPERAND (0, SA3, *ip, imm_expr.X_add_number); |
74cd071d CF |
10717 | imm_expr.X_op = O_absent; |
10718 | s = expr_end; | |
10719 | continue; | |
10720 | ||
90ecf173 | 10721 | case '4': /* DSP 4-bit unsigned immediate in bit 21. */ |
df58fc94 | 10722 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10723 | my_getExpression (&imm_expr, s); |
10724 | check_absolute_expr (ip, &imm_expr); | |
10725 | if (imm_expr.X_add_number & ~OP_MASK_SA4) | |
10726 | { | |
a9e24354 TS |
10727 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
10728 | OP_MASK_SA4, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 10729 | } |
df58fc94 | 10730 | INSERT_OPERAND (0, SA4, *ip, imm_expr.X_add_number); |
74cd071d CF |
10731 | imm_expr.X_op = O_absent; |
10732 | s = expr_end; | |
10733 | continue; | |
10734 | ||
90ecf173 | 10735 | case '5': /* DSP 8-bit unsigned immediate in bit 16. */ |
df58fc94 | 10736 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10737 | my_getExpression (&imm_expr, s); |
10738 | check_absolute_expr (ip, &imm_expr); | |
10739 | if (imm_expr.X_add_number & ~OP_MASK_IMM8) | |
10740 | { | |
a9e24354 TS |
10741 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
10742 | OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 10743 | } |
df58fc94 | 10744 | INSERT_OPERAND (0, IMM8, *ip, imm_expr.X_add_number); |
74cd071d CF |
10745 | imm_expr.X_op = O_absent; |
10746 | s = expr_end; | |
10747 | continue; | |
10748 | ||
90ecf173 | 10749 | case '6': /* DSP 5-bit unsigned immediate in bit 21. */ |
df58fc94 | 10750 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10751 | my_getExpression (&imm_expr, s); |
10752 | check_absolute_expr (ip, &imm_expr); | |
10753 | if (imm_expr.X_add_number & ~OP_MASK_RS) | |
10754 | { | |
a9e24354 TS |
10755 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
10756 | OP_MASK_RS, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 10757 | } |
df58fc94 | 10758 | INSERT_OPERAND (0, RS, *ip, imm_expr.X_add_number); |
74cd071d CF |
10759 | imm_expr.X_op = O_absent; |
10760 | s = expr_end; | |
10761 | continue; | |
10762 | ||
90ecf173 | 10763 | case '7': /* Four DSP accumulators in bits 11,12. */ |
df58fc94 | 10764 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10765 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
10766 | s[3] >= '0' && s[3] <= '3') | |
10767 | { | |
10768 | regno = s[3] - '0'; | |
10769 | s += 4; | |
df58fc94 | 10770 | INSERT_OPERAND (0, DSPACC, *ip, regno); |
74cd071d CF |
10771 | continue; |
10772 | } | |
10773 | else | |
10774 | as_bad (_("Invalid dsp acc register")); | |
10775 | break; | |
10776 | ||
90ecf173 | 10777 | case '8': /* DSP 6-bit unsigned immediate in bit 11. */ |
df58fc94 | 10778 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10779 | my_getExpression (&imm_expr, s); |
10780 | check_absolute_expr (ip, &imm_expr); | |
10781 | if (imm_expr.X_add_number & ~OP_MASK_WRDSP) | |
10782 | { | |
a9e24354 TS |
10783 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
10784 | OP_MASK_WRDSP, | |
10785 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 10786 | } |
df58fc94 | 10787 | INSERT_OPERAND (0, WRDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
10788 | imm_expr.X_op = O_absent; |
10789 | s = expr_end; | |
10790 | continue; | |
10791 | ||
90ecf173 | 10792 | case '9': /* Four DSP accumulators in bits 21,22. */ |
df58fc94 | 10793 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10794 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
10795 | s[3] >= '0' && s[3] <= '3') | |
10796 | { | |
10797 | regno = s[3] - '0'; | |
10798 | s += 4; | |
df58fc94 | 10799 | INSERT_OPERAND (0, DSPACC_S, *ip, regno); |
74cd071d CF |
10800 | continue; |
10801 | } | |
10802 | else | |
10803 | as_bad (_("Invalid dsp acc register")); | |
10804 | break; | |
10805 | ||
90ecf173 | 10806 | case '0': /* DSP 6-bit signed immediate in bit 20. */ |
df58fc94 | 10807 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10808 | my_getExpression (&imm_expr, s); |
10809 | check_absolute_expr (ip, &imm_expr); | |
10810 | min_range = -((OP_MASK_DSPSFT + 1) >> 1); | |
10811 | max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1; | |
10812 | if (imm_expr.X_add_number < min_range || | |
10813 | imm_expr.X_add_number > max_range) | |
10814 | { | |
a9e24354 TS |
10815 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
10816 | (long) min_range, (long) max_range, | |
10817 | (long) imm_expr.X_add_number); | |
74cd071d | 10818 | } |
df58fc94 | 10819 | INSERT_OPERAND (0, DSPSFT, *ip, imm_expr.X_add_number); |
74cd071d CF |
10820 | imm_expr.X_op = O_absent; |
10821 | s = expr_end; | |
10822 | continue; | |
10823 | ||
90ecf173 | 10824 | case '\'': /* DSP 6-bit unsigned immediate in bit 16. */ |
df58fc94 | 10825 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10826 | my_getExpression (&imm_expr, s); |
10827 | check_absolute_expr (ip, &imm_expr); | |
10828 | if (imm_expr.X_add_number & ~OP_MASK_RDDSP) | |
10829 | { | |
a9e24354 TS |
10830 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
10831 | OP_MASK_RDDSP, | |
10832 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 10833 | } |
df58fc94 | 10834 | INSERT_OPERAND (0, RDDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
10835 | imm_expr.X_op = O_absent; |
10836 | s = expr_end; | |
10837 | continue; | |
10838 | ||
90ecf173 | 10839 | case ':': /* DSP 7-bit signed immediate in bit 19. */ |
df58fc94 | 10840 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10841 | my_getExpression (&imm_expr, s); |
10842 | check_absolute_expr (ip, &imm_expr); | |
10843 | min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1); | |
10844 | max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1; | |
10845 | if (imm_expr.X_add_number < min_range || | |
10846 | imm_expr.X_add_number > max_range) | |
10847 | { | |
a9e24354 TS |
10848 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
10849 | (long) min_range, (long) max_range, | |
10850 | (long) imm_expr.X_add_number); | |
74cd071d | 10851 | } |
df58fc94 | 10852 | INSERT_OPERAND (0, DSPSFT_7, *ip, imm_expr.X_add_number); |
74cd071d CF |
10853 | imm_expr.X_op = O_absent; |
10854 | s = expr_end; | |
10855 | continue; | |
10856 | ||
90ecf173 | 10857 | case '@': /* DSP 10-bit signed immediate in bit 16. */ |
df58fc94 | 10858 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10859 | my_getExpression (&imm_expr, s); |
10860 | check_absolute_expr (ip, &imm_expr); | |
10861 | min_range = -((OP_MASK_IMM10 + 1) >> 1); | |
10862 | max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1; | |
10863 | if (imm_expr.X_add_number < min_range || | |
10864 | imm_expr.X_add_number > max_range) | |
10865 | { | |
a9e24354 TS |
10866 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
10867 | (long) min_range, (long) max_range, | |
10868 | (long) imm_expr.X_add_number); | |
74cd071d | 10869 | } |
df58fc94 | 10870 | INSERT_OPERAND (0, IMM10, *ip, imm_expr.X_add_number); |
74cd071d CF |
10871 | imm_expr.X_op = O_absent; |
10872 | s = expr_end; | |
10873 | continue; | |
10874 | ||
a9e24354 | 10875 | case '!': /* MT usermode flag bit. */ |
df58fc94 | 10876 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
10877 | my_getExpression (&imm_expr, s); |
10878 | check_absolute_expr (ip, &imm_expr); | |
10879 | if (imm_expr.X_add_number & ~OP_MASK_MT_U) | |
a9e24354 TS |
10880 | as_bad (_("MT usermode bit not 0 or 1 (%lu)"), |
10881 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 10882 | INSERT_OPERAND (0, MT_U, *ip, imm_expr.X_add_number); |
ef2e4d86 CF |
10883 | imm_expr.X_op = O_absent; |
10884 | s = expr_end; | |
10885 | continue; | |
10886 | ||
a9e24354 | 10887 | case '$': /* MT load high flag bit. */ |
df58fc94 | 10888 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
10889 | my_getExpression (&imm_expr, s); |
10890 | check_absolute_expr (ip, &imm_expr); | |
10891 | if (imm_expr.X_add_number & ~OP_MASK_MT_H) | |
a9e24354 TS |
10892 | as_bad (_("MT load high bit not 0 or 1 (%lu)"), |
10893 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 10894 | INSERT_OPERAND (0, MT_H, *ip, imm_expr.X_add_number); |
ef2e4d86 CF |
10895 | imm_expr.X_op = O_absent; |
10896 | s = expr_end; | |
10897 | continue; | |
10898 | ||
90ecf173 | 10899 | case '*': /* Four DSP accumulators in bits 18,19. */ |
df58fc94 | 10900 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
10901 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
10902 | s[3] >= '0' && s[3] <= '3') | |
10903 | { | |
10904 | regno = s[3] - '0'; | |
10905 | s += 4; | |
df58fc94 | 10906 | INSERT_OPERAND (0, MTACC_T, *ip, regno); |
ef2e4d86 CF |
10907 | continue; |
10908 | } | |
10909 | else | |
10910 | as_bad (_("Invalid dsp/smartmips acc register")); | |
10911 | break; | |
10912 | ||
90ecf173 | 10913 | case '&': /* Four DSP accumulators in bits 13,14. */ |
df58fc94 | 10914 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
10915 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
10916 | s[3] >= '0' && s[3] <= '3') | |
10917 | { | |
10918 | regno = s[3] - '0'; | |
10919 | s += 4; | |
df58fc94 | 10920 | INSERT_OPERAND (0, MTACC_D, *ip, regno); |
ef2e4d86 CF |
10921 | continue; |
10922 | } | |
10923 | else | |
10924 | as_bad (_("Invalid dsp/smartmips acc register")); | |
10925 | break; | |
10926 | ||
252b5132 | 10927 | case ',': |
a339155f | 10928 | ++argnum; |
252b5132 RH |
10929 | if (*s++ == *args) |
10930 | continue; | |
10931 | s--; | |
10932 | switch (*++args) | |
10933 | { | |
10934 | case 'r': | |
10935 | case 'v': | |
df58fc94 | 10936 | INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno); |
252b5132 RH |
10937 | continue; |
10938 | ||
10939 | case 'w': | |
df58fc94 | 10940 | INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno); |
38487616 TS |
10941 | continue; |
10942 | ||
252b5132 | 10943 | case 'W': |
df58fc94 RS |
10944 | gas_assert (!mips_opts.micromips); |
10945 | INSERT_OPERAND (0, FT, *ip, lastregno); | |
252b5132 RH |
10946 | continue; |
10947 | ||
10948 | case 'V': | |
df58fc94 | 10949 | INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno); |
252b5132 RH |
10950 | continue; |
10951 | } | |
10952 | break; | |
10953 | ||
10954 | case '(': | |
10955 | /* Handle optional base register. | |
10956 | Either the base register is omitted or | |
bdaaa2e1 | 10957 | we must have a left paren. */ |
252b5132 RH |
10958 | /* This is dependent on the next operand specifier |
10959 | is a base register specification. */ | |
df58fc94 RS |
10960 | gas_assert (args[1] == 'b' |
10961 | || (mips_opts.micromips | |
10962 | && args[1] == 'm' | |
10963 | && (args[2] == 'l' || args[2] == 'n' | |
10964 | || args[2] == 's' || args[2] == 'a'))); | |
10965 | if (*s == '\0' && args[1] == 'b') | |
252b5132 | 10966 | return; |
df58fc94 | 10967 | /* Fall through. */ |
252b5132 | 10968 | |
90ecf173 | 10969 | case ')': /* These must match exactly. */ |
df58fc94 RS |
10970 | if (*s++ == *args) |
10971 | continue; | |
10972 | break; | |
10973 | ||
10974 | case '[': /* These must match exactly. */ | |
60b63b72 | 10975 | case ']': |
df58fc94 | 10976 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
10977 | if (*s++ == *args) |
10978 | continue; | |
10979 | break; | |
10980 | ||
af7ee8bf CD |
10981 | case '+': /* Opcode extension character. */ |
10982 | switch (*++args) | |
10983 | { | |
9bcd4f99 TS |
10984 | case '1': /* UDI immediates. */ |
10985 | case '2': | |
10986 | case '3': | |
10987 | case '4': | |
df58fc94 | 10988 | gas_assert (!mips_opts.micromips); |
9bcd4f99 TS |
10989 | { |
10990 | const struct mips_immed *imm = mips_immed; | |
10991 | ||
10992 | while (imm->type && imm->type != *args) | |
10993 | ++imm; | |
10994 | if (! imm->type) | |
10995 | internalError (); | |
10996 | my_getExpression (&imm_expr, s); | |
10997 | check_absolute_expr (ip, &imm_expr); | |
10998 | if ((unsigned long) imm_expr.X_add_number & ~imm->mask) | |
10999 | { | |
11000 | as_warn (_("Illegal %s number (%lu, 0x%lx)"), | |
11001 | imm->desc ? imm->desc : ip->insn_mo->name, | |
11002 | (unsigned long) imm_expr.X_add_number, | |
11003 | (unsigned long) imm_expr.X_add_number); | |
90ecf173 | 11004 | imm_expr.X_add_number &= imm->mask; |
9bcd4f99 TS |
11005 | } |
11006 | ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number | |
11007 | << imm->shift); | |
11008 | imm_expr.X_op = O_absent; | |
11009 | s = expr_end; | |
11010 | } | |
11011 | continue; | |
90ecf173 | 11012 | |
071742cf CD |
11013 | case 'A': /* ins/ext position, becomes LSB. */ |
11014 | limlo = 0; | |
11015 | limhi = 31; | |
5f74bc13 CD |
11016 | goto do_lsb; |
11017 | case 'E': | |
11018 | limlo = 32; | |
11019 | limhi = 63; | |
11020 | goto do_lsb; | |
90ecf173 | 11021 | do_lsb: |
071742cf CD |
11022 | my_getExpression (&imm_expr, s); |
11023 | check_absolute_expr (ip, &imm_expr); | |
11024 | if ((unsigned long) imm_expr.X_add_number < limlo | |
11025 | || (unsigned long) imm_expr.X_add_number > limhi) | |
11026 | { | |
11027 | as_bad (_("Improper position (%lu)"), | |
11028 | (unsigned long) imm_expr.X_add_number); | |
11029 | imm_expr.X_add_number = limlo; | |
11030 | } | |
11031 | lastpos = imm_expr.X_add_number; | |
df58fc94 RS |
11032 | INSERT_OPERAND (mips_opts.micromips, |
11033 | EXTLSB, *ip, imm_expr.X_add_number); | |
071742cf CD |
11034 | imm_expr.X_op = O_absent; |
11035 | s = expr_end; | |
11036 | continue; | |
11037 | ||
11038 | case 'B': /* ins size, becomes MSB. */ | |
11039 | limlo = 1; | |
11040 | limhi = 32; | |
5f74bc13 CD |
11041 | goto do_msb; |
11042 | case 'F': | |
11043 | limlo = 33; | |
11044 | limhi = 64; | |
11045 | goto do_msb; | |
90ecf173 | 11046 | do_msb: |
071742cf CD |
11047 | my_getExpression (&imm_expr, s); |
11048 | check_absolute_expr (ip, &imm_expr); | |
11049 | /* Check for negative input so that small negative numbers | |
11050 | will not succeed incorrectly. The checks against | |
11051 | (pos+size) transitively check "size" itself, | |
11052 | assuming that "pos" is reasonable. */ | |
11053 | if ((long) imm_expr.X_add_number < 0 | |
11054 | || ((unsigned long) imm_expr.X_add_number | |
11055 | + lastpos) < limlo | |
11056 | || ((unsigned long) imm_expr.X_add_number | |
11057 | + lastpos) > limhi) | |
11058 | { | |
11059 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
11060 | (unsigned long) imm_expr.X_add_number, | |
11061 | (unsigned long) lastpos); | |
11062 | imm_expr.X_add_number = limlo - lastpos; | |
11063 | } | |
df58fc94 RS |
11064 | INSERT_OPERAND (mips_opts.micromips, INSMSB, *ip, |
11065 | lastpos + imm_expr.X_add_number - 1); | |
071742cf CD |
11066 | imm_expr.X_op = O_absent; |
11067 | s = expr_end; | |
11068 | continue; | |
11069 | ||
11070 | case 'C': /* ext size, becomes MSBD. */ | |
11071 | limlo = 1; | |
11072 | limhi = 32; | |
5f74bc13 CD |
11073 | goto do_msbd; |
11074 | case 'G': | |
11075 | limlo = 33; | |
11076 | limhi = 64; | |
11077 | goto do_msbd; | |
11078 | case 'H': | |
11079 | limlo = 33; | |
11080 | limhi = 64; | |
11081 | goto do_msbd; | |
90ecf173 | 11082 | do_msbd: |
071742cf CD |
11083 | my_getExpression (&imm_expr, s); |
11084 | check_absolute_expr (ip, &imm_expr); | |
11085 | /* Check for negative input so that small negative numbers | |
11086 | will not succeed incorrectly. The checks against | |
11087 | (pos+size) transitively check "size" itself, | |
11088 | assuming that "pos" is reasonable. */ | |
11089 | if ((long) imm_expr.X_add_number < 0 | |
11090 | || ((unsigned long) imm_expr.X_add_number | |
11091 | + lastpos) < limlo | |
11092 | || ((unsigned long) imm_expr.X_add_number | |
11093 | + lastpos) > limhi) | |
11094 | { | |
11095 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
11096 | (unsigned long) imm_expr.X_add_number, | |
11097 | (unsigned long) lastpos); | |
11098 | imm_expr.X_add_number = limlo - lastpos; | |
11099 | } | |
df58fc94 RS |
11100 | INSERT_OPERAND (mips_opts.micromips, |
11101 | EXTMSBD, *ip, imm_expr.X_add_number - 1); | |
071742cf CD |
11102 | imm_expr.X_op = O_absent; |
11103 | s = expr_end; | |
11104 | continue; | |
af7ee8bf | 11105 | |
bbcc0807 CD |
11106 | case 'D': |
11107 | /* +D is for disassembly only; never match. */ | |
11108 | break; | |
11109 | ||
5f74bc13 CD |
11110 | case 'I': |
11111 | /* "+I" is like "I", except that imm2_expr is used. */ | |
11112 | my_getExpression (&imm2_expr, s); | |
11113 | if (imm2_expr.X_op != O_big | |
11114 | && imm2_expr.X_op != O_constant) | |
11115 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
11116 | if (HAVE_32BIT_GPRS) |
11117 | normalize_constant_expr (&imm2_expr); | |
5f74bc13 CD |
11118 | s = expr_end; |
11119 | continue; | |
11120 | ||
707bfff6 | 11121 | case 'T': /* Coprocessor register. */ |
df58fc94 | 11122 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11123 | /* +T is for disassembly only; never match. */ |
11124 | break; | |
11125 | ||
707bfff6 | 11126 | case 't': /* Coprocessor register number. */ |
df58fc94 | 11127 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11128 | if (s[0] == '$' && ISDIGIT (s[1])) |
11129 | { | |
11130 | ++s; | |
11131 | regno = 0; | |
11132 | do | |
11133 | { | |
11134 | regno *= 10; | |
11135 | regno += *s - '0'; | |
11136 | ++s; | |
11137 | } | |
11138 | while (ISDIGIT (*s)); | |
11139 | if (regno > 31) | |
11140 | as_bad (_("Invalid register number (%d)"), regno); | |
11141 | else | |
11142 | { | |
df58fc94 | 11143 | INSERT_OPERAND (0, RT, *ip, regno); |
ef2e4d86 CF |
11144 | continue; |
11145 | } | |
11146 | } | |
11147 | else | |
11148 | as_bad (_("Invalid coprocessor 0 register number")); | |
11149 | break; | |
11150 | ||
bb35fb24 NC |
11151 | case 'x': |
11152 | /* bbit[01] and bbit[01]32 bit index. Give error if index | |
11153 | is not in the valid range. */ | |
df58fc94 | 11154 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11155 | my_getExpression (&imm_expr, s); |
11156 | check_absolute_expr (ip, &imm_expr); | |
11157 | if ((unsigned) imm_expr.X_add_number > 31) | |
11158 | { | |
11159 | as_bad (_("Improper bit index (%lu)"), | |
11160 | (unsigned long) imm_expr.X_add_number); | |
11161 | imm_expr.X_add_number = 0; | |
11162 | } | |
df58fc94 | 11163 | INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11164 | imm_expr.X_op = O_absent; |
11165 | s = expr_end; | |
11166 | continue; | |
11167 | ||
11168 | case 'X': | |
11169 | /* bbit[01] bit index when bbit is used but we generate | |
11170 | bbit[01]32 because the index is over 32. Move to the | |
11171 | next candidate if index is not in the valid range. */ | |
df58fc94 | 11172 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11173 | my_getExpression (&imm_expr, s); |
11174 | check_absolute_expr (ip, &imm_expr); | |
11175 | if ((unsigned) imm_expr.X_add_number < 32 | |
11176 | || (unsigned) imm_expr.X_add_number > 63) | |
11177 | break; | |
df58fc94 | 11178 | INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number - 32); |
bb35fb24 NC |
11179 | imm_expr.X_op = O_absent; |
11180 | s = expr_end; | |
11181 | continue; | |
11182 | ||
11183 | case 'p': | |
11184 | /* cins, cins32, exts and exts32 position field. Give error | |
11185 | if it's not in the valid range. */ | |
df58fc94 | 11186 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11187 | my_getExpression (&imm_expr, s); |
11188 | check_absolute_expr (ip, &imm_expr); | |
11189 | if ((unsigned) imm_expr.X_add_number > 31) | |
11190 | { | |
11191 | as_bad (_("Improper position (%lu)"), | |
11192 | (unsigned long) imm_expr.X_add_number); | |
11193 | imm_expr.X_add_number = 0; | |
11194 | } | |
11195 | /* Make the pos explicit to simplify +S. */ | |
11196 | lastpos = imm_expr.X_add_number + 32; | |
df58fc94 | 11197 | INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11198 | imm_expr.X_op = O_absent; |
11199 | s = expr_end; | |
11200 | continue; | |
11201 | ||
11202 | case 'P': | |
11203 | /* cins, cins32, exts and exts32 position field. Move to | |
11204 | the next candidate if it's not in the valid range. */ | |
df58fc94 | 11205 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11206 | my_getExpression (&imm_expr, s); |
11207 | check_absolute_expr (ip, &imm_expr); | |
11208 | if ((unsigned) imm_expr.X_add_number < 32 | |
11209 | || (unsigned) imm_expr.X_add_number > 63) | |
11210 | break; | |
11211 | lastpos = imm_expr.X_add_number; | |
df58fc94 | 11212 | INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number - 32); |
bb35fb24 NC |
11213 | imm_expr.X_op = O_absent; |
11214 | s = expr_end; | |
11215 | continue; | |
11216 | ||
11217 | case 's': | |
11218 | /* cins and exts length-minus-one field. */ | |
df58fc94 | 11219 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11220 | my_getExpression (&imm_expr, s); |
11221 | check_absolute_expr (ip, &imm_expr); | |
11222 | if ((unsigned long) imm_expr.X_add_number > 31) | |
11223 | { | |
11224 | as_bad (_("Improper size (%lu)"), | |
11225 | (unsigned long) imm_expr.X_add_number); | |
11226 | imm_expr.X_add_number = 0; | |
11227 | } | |
df58fc94 | 11228 | INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11229 | imm_expr.X_op = O_absent; |
11230 | s = expr_end; | |
11231 | continue; | |
11232 | ||
11233 | case 'S': | |
11234 | /* cins32/exts32 and cins/exts aliasing cint32/exts32 | |
11235 | length-minus-one field. */ | |
df58fc94 | 11236 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11237 | my_getExpression (&imm_expr, s); |
11238 | check_absolute_expr (ip, &imm_expr); | |
11239 | if ((long) imm_expr.X_add_number < 0 | |
11240 | || (unsigned long) imm_expr.X_add_number + lastpos > 63) | |
11241 | { | |
11242 | as_bad (_("Improper size (%lu)"), | |
11243 | (unsigned long) imm_expr.X_add_number); | |
11244 | imm_expr.X_add_number = 0; | |
11245 | } | |
df58fc94 | 11246 | INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11247 | imm_expr.X_op = O_absent; |
11248 | s = expr_end; | |
11249 | continue; | |
11250 | ||
dd3cbb7e NC |
11251 | case 'Q': |
11252 | /* seqi/snei immediate field. */ | |
df58fc94 | 11253 | gas_assert (!mips_opts.micromips); |
dd3cbb7e NC |
11254 | my_getExpression (&imm_expr, s); |
11255 | check_absolute_expr (ip, &imm_expr); | |
11256 | if ((long) imm_expr.X_add_number < -512 | |
11257 | || (long) imm_expr.X_add_number >= 512) | |
11258 | { | |
11259 | as_bad (_("Improper immediate (%ld)"), | |
11260 | (long) imm_expr.X_add_number); | |
11261 | imm_expr.X_add_number = 0; | |
11262 | } | |
df58fc94 | 11263 | INSERT_OPERAND (0, SEQI, *ip, imm_expr.X_add_number); |
dd3cbb7e NC |
11264 | imm_expr.X_op = O_absent; |
11265 | s = expr_end; | |
11266 | continue; | |
11267 | ||
98675402 | 11268 | case 'a': /* 8-bit signed offset in bit 6 */ |
df58fc94 | 11269 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11270 | my_getExpression (&imm_expr, s); |
11271 | check_absolute_expr (ip, &imm_expr); | |
11272 | min_range = -((OP_MASK_OFFSET_A + 1) >> 1); | |
11273 | max_range = ((OP_MASK_OFFSET_A + 1) >> 1) - 1; | |
11274 | if (imm_expr.X_add_number < min_range | |
11275 | || imm_expr.X_add_number > max_range) | |
11276 | { | |
c95354ed | 11277 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
11278 | (long) min_range, (long) max_range, |
11279 | (long) imm_expr.X_add_number); | |
11280 | } | |
df58fc94 | 11281 | INSERT_OPERAND (0, OFFSET_A, *ip, imm_expr.X_add_number); |
98675402 RS |
11282 | imm_expr.X_op = O_absent; |
11283 | s = expr_end; | |
11284 | continue; | |
11285 | ||
11286 | case 'b': /* 8-bit signed offset in bit 3 */ | |
df58fc94 | 11287 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11288 | my_getExpression (&imm_expr, s); |
11289 | check_absolute_expr (ip, &imm_expr); | |
11290 | min_range = -((OP_MASK_OFFSET_B + 1) >> 1); | |
11291 | max_range = ((OP_MASK_OFFSET_B + 1) >> 1) - 1; | |
11292 | if (imm_expr.X_add_number < min_range | |
11293 | || imm_expr.X_add_number > max_range) | |
11294 | { | |
c95354ed | 11295 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
11296 | (long) min_range, (long) max_range, |
11297 | (long) imm_expr.X_add_number); | |
11298 | } | |
df58fc94 | 11299 | INSERT_OPERAND (0, OFFSET_B, *ip, imm_expr.X_add_number); |
98675402 RS |
11300 | imm_expr.X_op = O_absent; |
11301 | s = expr_end; | |
11302 | continue; | |
11303 | ||
11304 | case 'c': /* 9-bit signed offset in bit 6 */ | |
df58fc94 | 11305 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11306 | my_getExpression (&imm_expr, s); |
11307 | check_absolute_expr (ip, &imm_expr); | |
11308 | min_range = -((OP_MASK_OFFSET_C + 1) >> 1); | |
11309 | max_range = ((OP_MASK_OFFSET_C + 1) >> 1) - 1; | |
c95354ed MX |
11310 | /* We check the offset range before adjusted. */ |
11311 | min_range <<= 4; | |
11312 | max_range <<= 4; | |
98675402 RS |
11313 | if (imm_expr.X_add_number < min_range |
11314 | || imm_expr.X_add_number > max_range) | |
11315 | { | |
c95354ed | 11316 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
11317 | (long) min_range, (long) max_range, |
11318 | (long) imm_expr.X_add_number); | |
11319 | } | |
c95354ed MX |
11320 | if (imm_expr.X_add_number & 0xf) |
11321 | { | |
11322 | as_bad (_("Offset not 16 bytes alignment (%ld)"), | |
11323 | (long) imm_expr.X_add_number); | |
11324 | } | |
11325 | /* Right shift 4 bits to adjust the offset operand. */ | |
df58fc94 RS |
11326 | INSERT_OPERAND (0, OFFSET_C, *ip, |
11327 | imm_expr.X_add_number >> 4); | |
98675402 RS |
11328 | imm_expr.X_op = O_absent; |
11329 | s = expr_end; | |
11330 | continue; | |
11331 | ||
11332 | case 'z': | |
df58fc94 | 11333 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11334 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) |
11335 | break; | |
11336 | if (regno == AT && mips_opts.at) | |
11337 | { | |
11338 | if (mips_opts.at == ATREG) | |
11339 | as_warn (_("used $at without \".set noat\"")); | |
11340 | else | |
11341 | as_warn (_("used $%u with \".set at=$%u\""), | |
11342 | regno, mips_opts.at); | |
11343 | } | |
df58fc94 | 11344 | INSERT_OPERAND (0, RZ, *ip, regno); |
98675402 RS |
11345 | continue; |
11346 | ||
11347 | case 'Z': | |
df58fc94 | 11348 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11349 | if (!reg_lookup (&s, RTYPE_FPU, ®no)) |
11350 | break; | |
df58fc94 | 11351 | INSERT_OPERAND (0, FZ, *ip, regno); |
98675402 RS |
11352 | continue; |
11353 | ||
af7ee8bf | 11354 | default: |
df58fc94 | 11355 | as_bad (_("Internal error: bad %s opcode " |
90ecf173 | 11356 | "(unknown extension operand type `+%c'): %s %s"), |
df58fc94 | 11357 | mips_opts.micromips ? "microMIPS" : "MIPS", |
90ecf173 | 11358 | *args, insn->name, insn->args); |
af7ee8bf CD |
11359 | /* Further processing is fruitless. */ |
11360 | return; | |
11361 | } | |
11362 | break; | |
11363 | ||
df58fc94 RS |
11364 | case '.': /* 10-bit offset. */ |
11365 | case '~': /* 12-bit offset. */ | |
11366 | gas_assert (mips_opts.micromips); | |
11367 | { | |
11368 | int shift = *args == '.' ? 9 : 11; | |
11369 | size_t i; | |
11370 | ||
11371 | /* Check whether there is only a single bracketed expression | |
11372 | left. If so, it must be the base register and the | |
11373 | constant must be zero. */ | |
11374 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
11375 | continue; | |
11376 | ||
11377 | /* If this value won't fit into the offset, then go find | |
11378 | a macro that will generate a 16- or 32-bit offset code | |
11379 | pattern. */ | |
11380 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); | |
11381 | if ((i == 0 && (imm_expr.X_op != O_constant | |
11382 | || imm_expr.X_add_number >= 1 << shift | |
11383 | || imm_expr.X_add_number < -1 << shift)) | |
11384 | || i > 0) | |
11385 | { | |
11386 | imm_expr.X_op = O_absent; | |
11387 | break; | |
11388 | } | |
11389 | if (shift == 9) | |
11390 | INSERT_OPERAND (1, OFFSET10, *ip, imm_expr.X_add_number); | |
11391 | else | |
11392 | INSERT_OPERAND (1, OFFSET12, *ip, imm_expr.X_add_number); | |
11393 | imm_expr.X_op = O_absent; | |
11394 | s = expr_end; | |
11395 | } | |
11396 | continue; | |
11397 | ||
252b5132 RH |
11398 | case '<': /* must be at least one digit */ |
11399 | /* | |
11400 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
11401 | * than 31 or less than 0, then the shift amount should be |
11402 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
11403 | * We issue a warning and mask out all but the low 5 bits. |
11404 | */ | |
11405 | my_getExpression (&imm_expr, s); | |
11406 | check_absolute_expr (ip, &imm_expr); | |
11407 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
11408 | as_warn (_("Improper shift amount (%lu)"), |
11409 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 RS |
11410 | INSERT_OPERAND (mips_opts.micromips, |
11411 | SHAMT, *ip, imm_expr.X_add_number); | |
252b5132 RH |
11412 | imm_expr.X_op = O_absent; |
11413 | s = expr_end; | |
11414 | continue; | |
11415 | ||
11416 | case '>': /* shift amount minus 32 */ | |
11417 | my_getExpression (&imm_expr, s); | |
11418 | check_absolute_expr (ip, &imm_expr); | |
11419 | if ((unsigned long) imm_expr.X_add_number < 32 | |
11420 | || (unsigned long) imm_expr.X_add_number > 63) | |
11421 | break; | |
df58fc94 RS |
11422 | INSERT_OPERAND (mips_opts.micromips, |
11423 | SHAMT, *ip, imm_expr.X_add_number - 32); | |
252b5132 RH |
11424 | imm_expr.X_op = O_absent; |
11425 | s = expr_end; | |
11426 | continue; | |
11427 | ||
90ecf173 MR |
11428 | case 'k': /* CACHE code. */ |
11429 | case 'h': /* PREFX code. */ | |
11430 | case '1': /* SYNC type. */ | |
252b5132 RH |
11431 | my_getExpression (&imm_expr, s); |
11432 | check_absolute_expr (ip, &imm_expr); | |
11433 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
11434 | as_warn (_("Invalid value for `%s' (%lu)"), |
11435 | ip->insn_mo->name, | |
11436 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 11437 | switch (*args) |
d954098f | 11438 | { |
df58fc94 RS |
11439 | case 'k': |
11440 | if (mips_fix_cn63xxp1 | |
11441 | && !mips_opts.micromips | |
11442 | && strcmp ("pref", insn->name) == 0) | |
d954098f DD |
11443 | switch (imm_expr.X_add_number) |
11444 | { | |
11445 | case 5: | |
11446 | case 25: | |
11447 | case 26: | |
11448 | case 27: | |
11449 | case 28: | |
11450 | case 29: | |
11451 | case 30: | |
11452 | case 31: /* These are ok. */ | |
11453 | break; | |
11454 | ||
11455 | default: /* The rest must be changed to 28. */ | |
11456 | imm_expr.X_add_number = 28; | |
11457 | break; | |
11458 | } | |
df58fc94 RS |
11459 | INSERT_OPERAND (mips_opts.micromips, |
11460 | CACHE, *ip, imm_expr.X_add_number); | |
11461 | break; | |
11462 | case 'h': | |
11463 | INSERT_OPERAND (mips_opts.micromips, | |
11464 | PREFX, *ip, imm_expr.X_add_number); | |
11465 | break; | |
11466 | case '1': | |
11467 | INSERT_OPERAND (mips_opts.micromips, | |
11468 | STYPE, *ip, imm_expr.X_add_number); | |
11469 | break; | |
d954098f | 11470 | } |
252b5132 RH |
11471 | imm_expr.X_op = O_absent; |
11472 | s = expr_end; | |
11473 | continue; | |
11474 | ||
90ecf173 | 11475 | case 'c': /* BREAK code. */ |
df58fc94 RS |
11476 | { |
11477 | unsigned long mask = (mips_opts.micromips | |
11478 | ? MICROMIPSOP_MASK_CODE | |
11479 | : OP_MASK_CODE); | |
11480 | ||
11481 | my_getExpression (&imm_expr, s); | |
11482 | check_absolute_expr (ip, &imm_expr); | |
11483 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11484 | as_warn (_("Code for %s not in range 0..%lu (%lu)"), | |
11485 | ip->insn_mo->name, | |
11486 | mask, (unsigned long) imm_expr.X_add_number); | |
11487 | INSERT_OPERAND (mips_opts.micromips, | |
11488 | CODE, *ip, imm_expr.X_add_number); | |
11489 | imm_expr.X_op = O_absent; | |
11490 | s = expr_end; | |
11491 | } | |
252b5132 RH |
11492 | continue; |
11493 | ||
90ecf173 | 11494 | case 'q': /* Lower BREAK code. */ |
df58fc94 RS |
11495 | { |
11496 | unsigned long mask = (mips_opts.micromips | |
11497 | ? MICROMIPSOP_MASK_CODE2 | |
11498 | : OP_MASK_CODE2); | |
11499 | ||
11500 | my_getExpression (&imm_expr, s); | |
11501 | check_absolute_expr (ip, &imm_expr); | |
11502 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11503 | as_warn (_("Lower code for %s not in range 0..%lu (%lu)"), | |
11504 | ip->insn_mo->name, | |
11505 | mask, (unsigned long) imm_expr.X_add_number); | |
11506 | INSERT_OPERAND (mips_opts.micromips, | |
11507 | CODE2, *ip, imm_expr.X_add_number); | |
11508 | imm_expr.X_op = O_absent; | |
11509 | s = expr_end; | |
11510 | } | |
252b5132 RH |
11511 | continue; |
11512 | ||
df58fc94 RS |
11513 | case 'B': /* 20- or 10-bit syscall/break/wait code. */ |
11514 | { | |
11515 | unsigned long mask = (mips_opts.micromips | |
11516 | ? MICROMIPSOP_MASK_CODE10 | |
11517 | : OP_MASK_CODE20); | |
11518 | ||
11519 | my_getExpression (&imm_expr, s); | |
11520 | check_absolute_expr (ip, &imm_expr); | |
11521 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11522 | as_warn (_("Code for %s not in range 0..%lu (%lu)"), | |
11523 | ip->insn_mo->name, | |
11524 | mask, (unsigned long) imm_expr.X_add_number); | |
11525 | if (mips_opts.micromips) | |
11526 | INSERT_OPERAND (1, CODE10, *ip, imm_expr.X_add_number); | |
11527 | else | |
11528 | INSERT_OPERAND (0, CODE20, *ip, imm_expr.X_add_number); | |
11529 | imm_expr.X_op = O_absent; | |
11530 | s = expr_end; | |
11531 | } | |
252b5132 RH |
11532 | continue; |
11533 | ||
df58fc94 RS |
11534 | case 'C': /* 25- or 23-bit coprocessor code. */ |
11535 | { | |
11536 | unsigned long mask = (mips_opts.micromips | |
11537 | ? MICROMIPSOP_MASK_COPZ | |
11538 | : OP_MASK_COPZ); | |
11539 | ||
11540 | my_getExpression (&imm_expr, s); | |
11541 | check_absolute_expr (ip, &imm_expr); | |
11542 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11543 | as_warn (_("Coproccesor code > %u bits (%lu)"), | |
11544 | mips_opts.micromips ? 23U : 25U, | |
793b27f4 | 11545 | (unsigned long) imm_expr.X_add_number); |
df58fc94 RS |
11546 | INSERT_OPERAND (mips_opts.micromips, |
11547 | COPZ, *ip, imm_expr.X_add_number); | |
11548 | imm_expr.X_op = O_absent; | |
11549 | s = expr_end; | |
11550 | } | |
beae10d5 | 11551 | continue; |
252b5132 | 11552 | |
df58fc94 RS |
11553 | case 'J': /* 19-bit WAIT code. */ |
11554 | gas_assert (!mips_opts.micromips); | |
4372b673 NC |
11555 | my_getExpression (&imm_expr, s); |
11556 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 11557 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
df58fc94 RS |
11558 | { |
11559 | as_warn (_("Illegal 19-bit code (%lu)"), | |
a9e24354 | 11560 | (unsigned long) imm_expr.X_add_number); |
df58fc94 RS |
11561 | imm_expr.X_add_number &= OP_MASK_CODE19; |
11562 | } | |
11563 | INSERT_OPERAND (0, CODE19, *ip, imm_expr.X_add_number); | |
4372b673 NC |
11564 | imm_expr.X_op = O_absent; |
11565 | s = expr_end; | |
11566 | continue; | |
11567 | ||
707bfff6 | 11568 | case 'P': /* Performance register. */ |
df58fc94 | 11569 | gas_assert (!mips_opts.micromips); |
beae10d5 | 11570 | my_getExpression (&imm_expr, s); |
252b5132 | 11571 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 11572 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
bf12938e RS |
11573 | as_warn (_("Invalid performance register (%lu)"), |
11574 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 11575 | INSERT_OPERAND (0, PERFREG, *ip, imm_expr.X_add_number); |
beae10d5 KH |
11576 | imm_expr.X_op = O_absent; |
11577 | s = expr_end; | |
11578 | continue; | |
252b5132 | 11579 | |
707bfff6 | 11580 | case 'G': /* Coprocessor destination register. */ |
df58fc94 RS |
11581 | { |
11582 | unsigned long opcode = ip->insn_opcode; | |
11583 | unsigned long mask; | |
11584 | unsigned int types; | |
11585 | int cop0; | |
11586 | ||
11587 | if (mips_opts.micromips) | |
11588 | { | |
11589 | mask = ~((MICROMIPSOP_MASK_RT << MICROMIPSOP_SH_RT) | |
11590 | | (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS) | |
11591 | | (MICROMIPSOP_MASK_SEL << MICROMIPSOP_SH_SEL)); | |
11592 | opcode &= mask; | |
11593 | switch (opcode) | |
11594 | { | |
11595 | case 0x000000fc: /* mfc0 */ | |
11596 | case 0x000002fc: /* mtc0 */ | |
11597 | case 0x580000fc: /* dmfc0 */ | |
11598 | case 0x580002fc: /* dmtc0 */ | |
11599 | cop0 = 1; | |
11600 | break; | |
11601 | default: | |
11602 | cop0 = 0; | |
11603 | break; | |
11604 | } | |
11605 | } | |
11606 | else | |
11607 | { | |
11608 | opcode = (opcode >> OP_SH_OP) & OP_MASK_OP; | |
11609 | cop0 = opcode == OP_OP_COP0; | |
11610 | } | |
11611 | types = RTYPE_NUM | (cop0 ? RTYPE_CP0 : RTYPE_GP); | |
11612 | ok = reg_lookup (&s, types, ®no); | |
11613 | if (mips_opts.micromips) | |
11614 | INSERT_OPERAND (1, RS, *ip, regno); | |
11615 | else | |
11616 | INSERT_OPERAND (0, RD, *ip, regno); | |
11617 | if (ok) | |
11618 | { | |
11619 | lastregno = regno; | |
11620 | continue; | |
11621 | } | |
11622 | } | |
11623 | break; | |
707bfff6 | 11624 | |
df58fc94 RS |
11625 | case 'y': /* ALNV.PS source register. */ |
11626 | gas_assert (mips_opts.micromips); | |
11627 | goto do_reg; | |
11628 | case 'x': /* Ignore register name. */ | |
11629 | case 'U': /* Destination register (CLO/CLZ). */ | |
11630 | case 'g': /* Coprocessor destination register. */ | |
11631 | gas_assert (!mips_opts.micromips); | |
90ecf173 MR |
11632 | case 'b': /* Base register. */ |
11633 | case 'd': /* Destination register. */ | |
11634 | case 's': /* Source register. */ | |
11635 | case 't': /* Target register. */ | |
11636 | case 'r': /* Both target and source. */ | |
11637 | case 'v': /* Both dest and source. */ | |
11638 | case 'w': /* Both dest and target. */ | |
11639 | case 'E': /* Coprocessor target register. */ | |
11640 | case 'K': /* RDHWR destination register. */ | |
90ecf173 | 11641 | case 'z': /* Must be zero register. */ |
df58fc94 | 11642 | do_reg: |
90ecf173 | 11643 | s_reset = s; |
707bfff6 TS |
11644 | if (*args == 'E' || *args == 'K') |
11645 | ok = reg_lookup (&s, RTYPE_NUM, ®no); | |
11646 | else | |
11647 | { | |
11648 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
741fe287 MR |
11649 | if (regno == AT && mips_opts.at) |
11650 | { | |
11651 | if (mips_opts.at == ATREG) | |
f71d0d44 | 11652 | as_warn (_("Used $at without \".set noat\"")); |
741fe287 | 11653 | else |
f71d0d44 | 11654 | as_warn (_("Used $%u with \".set at=$%u\""), |
741fe287 MR |
11655 | regno, mips_opts.at); |
11656 | } | |
707bfff6 TS |
11657 | } |
11658 | if (ok) | |
252b5132 | 11659 | { |
252b5132 RH |
11660 | c = *args; |
11661 | if (*s == ' ') | |
f9419b05 | 11662 | ++s; |
252b5132 RH |
11663 | if (args[1] != *s) |
11664 | { | |
11665 | if (c == 'r' || c == 'v' || c == 'w') | |
11666 | { | |
11667 | regno = lastregno; | |
11668 | s = s_reset; | |
f9419b05 | 11669 | ++args; |
252b5132 RH |
11670 | } |
11671 | } | |
11672 | /* 'z' only matches $0. */ | |
11673 | if (c == 'z' && regno != 0) | |
11674 | break; | |
11675 | ||
24864476 | 11676 | if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4)) |
e7c604dd CM |
11677 | { |
11678 | if (regno == lastregno) | |
90ecf173 MR |
11679 | { |
11680 | insn_error | |
f71d0d44 | 11681 | = _("Source and destination must be different"); |
e7c604dd | 11682 | continue; |
90ecf173 | 11683 | } |
24864476 | 11684 | if (regno == 31 && lastregno == 0xffffffff) |
90ecf173 MR |
11685 | { |
11686 | insn_error | |
f71d0d44 | 11687 | = _("A destination register must be supplied"); |
e7c604dd | 11688 | continue; |
90ecf173 | 11689 | } |
e7c604dd | 11690 | } |
90ecf173 MR |
11691 | /* Now that we have assembled one operand, we use the args |
11692 | string to figure out where it goes in the instruction. */ | |
252b5132 RH |
11693 | switch (c) |
11694 | { | |
11695 | case 'r': | |
11696 | case 's': | |
11697 | case 'v': | |
11698 | case 'b': | |
df58fc94 | 11699 | INSERT_OPERAND (mips_opts.micromips, RS, *ip, regno); |
252b5132 | 11700 | break; |
df58fc94 | 11701 | |
af7ee8bf | 11702 | case 'K': |
df58fc94 RS |
11703 | if (mips_opts.micromips) |
11704 | INSERT_OPERAND (1, RS, *ip, regno); | |
11705 | else | |
11706 | INSERT_OPERAND (0, RD, *ip, regno); | |
11707 | break; | |
11708 | ||
11709 | case 'd': | |
ef2e4d86 | 11710 | case 'g': |
df58fc94 | 11711 | INSERT_OPERAND (mips_opts.micromips, RD, *ip, regno); |
252b5132 | 11712 | break; |
df58fc94 | 11713 | |
4372b673 | 11714 | case 'U': |
df58fc94 RS |
11715 | gas_assert (!mips_opts.micromips); |
11716 | INSERT_OPERAND (0, RD, *ip, regno); | |
11717 | INSERT_OPERAND (0, RT, *ip, regno); | |
4372b673 | 11718 | break; |
df58fc94 | 11719 | |
252b5132 RH |
11720 | case 'w': |
11721 | case 't': | |
11722 | case 'E': | |
df58fc94 RS |
11723 | INSERT_OPERAND (mips_opts.micromips, RT, *ip, regno); |
11724 | break; | |
11725 | ||
11726 | case 'y': | |
11727 | gas_assert (mips_opts.micromips); | |
11728 | INSERT_OPERAND (1, RS3, *ip, regno); | |
252b5132 | 11729 | break; |
df58fc94 | 11730 | |
252b5132 RH |
11731 | case 'x': |
11732 | /* This case exists because on the r3000 trunc | |
11733 | expands into a macro which requires a gp | |
11734 | register. On the r6000 or r4000 it is | |
11735 | assembled into a single instruction which | |
11736 | ignores the register. Thus the insn version | |
11737 | is MIPS_ISA2 and uses 'x', and the macro | |
11738 | version is MIPS_ISA1 and uses 't'. */ | |
11739 | break; | |
df58fc94 | 11740 | |
252b5132 RH |
11741 | case 'z': |
11742 | /* This case is for the div instruction, which | |
11743 | acts differently if the destination argument | |
11744 | is $0. This only matches $0, and is checked | |
11745 | outside the switch. */ | |
11746 | break; | |
252b5132 RH |
11747 | } |
11748 | lastregno = regno; | |
11749 | continue; | |
11750 | } | |
252b5132 RH |
11751 | switch (*args++) |
11752 | { | |
11753 | case 'r': | |
11754 | case 'v': | |
df58fc94 | 11755 | INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno); |
252b5132 | 11756 | continue; |
df58fc94 | 11757 | |
252b5132 | 11758 | case 'w': |
df58fc94 | 11759 | INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno); |
252b5132 RH |
11760 | continue; |
11761 | } | |
11762 | break; | |
11763 | ||
deec1734 | 11764 | case 'O': /* MDMX alignment immediate constant. */ |
df58fc94 | 11765 | gas_assert (!mips_opts.micromips); |
deec1734 CD |
11766 | my_getExpression (&imm_expr, s); |
11767 | check_absolute_expr (ip, &imm_expr); | |
11768 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
20203fb9 | 11769 | as_warn (_("Improper align amount (%ld), using low bits"), |
bf12938e | 11770 | (long) imm_expr.X_add_number); |
df58fc94 | 11771 | INSERT_OPERAND (0, ALN, *ip, imm_expr.X_add_number); |
deec1734 CD |
11772 | imm_expr.X_op = O_absent; |
11773 | s = expr_end; | |
11774 | continue; | |
11775 | ||
11776 | case 'Q': /* MDMX vector, element sel, or const. */ | |
11777 | if (s[0] != '$') | |
11778 | { | |
11779 | /* MDMX Immediate. */ | |
df58fc94 | 11780 | gas_assert (!mips_opts.micromips); |
deec1734 CD |
11781 | my_getExpression (&imm_expr, s); |
11782 | check_absolute_expr (ip, &imm_expr); | |
11783 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
bf12938e RS |
11784 | as_warn (_("Invalid MDMX Immediate (%ld)"), |
11785 | (long) imm_expr.X_add_number); | |
df58fc94 | 11786 | INSERT_OPERAND (0, FT, *ip, imm_expr.X_add_number); |
deec1734 CD |
11787 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) |
11788 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
11789 | else | |
11790 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
deec1734 CD |
11791 | imm_expr.X_op = O_absent; |
11792 | s = expr_end; | |
11793 | continue; | |
11794 | } | |
11795 | /* Not MDMX Immediate. Fall through. */ | |
11796 | case 'X': /* MDMX destination register. */ | |
11797 | case 'Y': /* MDMX source register. */ | |
11798 | case 'Z': /* MDMX target register. */ | |
11799 | is_mdmx = 1; | |
df58fc94 RS |
11800 | case 'W': |
11801 | gas_assert (!mips_opts.micromips); | |
90ecf173 MR |
11802 | case 'D': /* Floating point destination register. */ |
11803 | case 'S': /* Floating point source register. */ | |
11804 | case 'T': /* Floating point target register. */ | |
11805 | case 'R': /* Floating point source register. */ | |
252b5132 | 11806 | case 'V': |
707bfff6 TS |
11807 | rtype = RTYPE_FPU; |
11808 | if (is_mdmx | |
11809 | || (mips_opts.ase_mdmx | |
11810 | && (ip->insn_mo->pinfo & FP_D) | |
11811 | && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY | |
11812 | | INSN_COPROC_MEMORY_DELAY | |
11813 | | INSN_LOAD_COPROC_DELAY | |
11814 | | INSN_LOAD_MEMORY_DELAY | |
11815 | | INSN_STORE_MEMORY)))) | |
11816 | rtype |= RTYPE_VEC; | |
252b5132 | 11817 | s_reset = s; |
707bfff6 | 11818 | if (reg_lookup (&s, rtype, ®no)) |
252b5132 | 11819 | { |
252b5132 | 11820 | if ((regno & 1) != 0 |
ca4e0257 | 11821 | && HAVE_32BIT_FPRS |
90ecf173 | 11822 | && !mips_oddfpreg_ok (ip->insn_mo, argnum)) |
252b5132 RH |
11823 | as_warn (_("Float register should be even, was %d"), |
11824 | regno); | |
11825 | ||
11826 | c = *args; | |
11827 | if (*s == ' ') | |
f9419b05 | 11828 | ++s; |
252b5132 RH |
11829 | if (args[1] != *s) |
11830 | { | |
11831 | if (c == 'V' || c == 'W') | |
11832 | { | |
11833 | regno = lastregno; | |
11834 | s = s_reset; | |
f9419b05 | 11835 | ++args; |
252b5132 RH |
11836 | } |
11837 | } | |
11838 | switch (c) | |
11839 | { | |
11840 | case 'D': | |
deec1734 | 11841 | case 'X': |
df58fc94 | 11842 | INSERT_OPERAND (mips_opts.micromips, FD, *ip, regno); |
252b5132 | 11843 | break; |
df58fc94 | 11844 | |
252b5132 RH |
11845 | case 'V': |
11846 | case 'S': | |
deec1734 | 11847 | case 'Y': |
df58fc94 | 11848 | INSERT_OPERAND (mips_opts.micromips, FS, *ip, regno); |
252b5132 | 11849 | break; |
df58fc94 | 11850 | |
deec1734 CD |
11851 | case 'Q': |
11852 | /* This is like 'Z', but also needs to fix the MDMX | |
11853 | vector/scalar select bits. Note that the | |
11854 | scalar immediate case is handled above. */ | |
11855 | if (*s == '[') | |
11856 | { | |
11857 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
11858 | int max_el = (is_qh ? 3 : 7); | |
11859 | s++; | |
11860 | my_getExpression(&imm_expr, s); | |
11861 | check_absolute_expr (ip, &imm_expr); | |
11862 | s = expr_end; | |
11863 | if (imm_expr.X_add_number > max_el) | |
20203fb9 NC |
11864 | as_bad (_("Bad element selector %ld"), |
11865 | (long) imm_expr.X_add_number); | |
deec1734 CD |
11866 | imm_expr.X_add_number &= max_el; |
11867 | ip->insn_opcode |= (imm_expr.X_add_number | |
11868 | << (OP_SH_VSEL + | |
11869 | (is_qh ? 2 : 1))); | |
01a3f561 | 11870 | imm_expr.X_op = O_absent; |
deec1734 | 11871 | if (*s != ']') |
20203fb9 | 11872 | as_warn (_("Expecting ']' found '%s'"), s); |
deec1734 CD |
11873 | else |
11874 | s++; | |
11875 | } | |
11876 | else | |
11877 | { | |
11878 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
11879 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
11880 | << OP_SH_VSEL); | |
11881 | else | |
11882 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
11883 | OP_SH_VSEL); | |
11884 | } | |
90ecf173 | 11885 | /* Fall through. */ |
252b5132 RH |
11886 | case 'W': |
11887 | case 'T': | |
deec1734 | 11888 | case 'Z': |
df58fc94 | 11889 | INSERT_OPERAND (mips_opts.micromips, FT, *ip, regno); |
252b5132 | 11890 | break; |
df58fc94 | 11891 | |
252b5132 | 11892 | case 'R': |
df58fc94 | 11893 | INSERT_OPERAND (mips_opts.micromips, FR, *ip, regno); |
252b5132 RH |
11894 | break; |
11895 | } | |
11896 | lastregno = regno; | |
11897 | continue; | |
11898 | } | |
11899 | ||
252b5132 RH |
11900 | switch (*args++) |
11901 | { | |
11902 | case 'V': | |
df58fc94 | 11903 | INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno); |
252b5132 | 11904 | continue; |
df58fc94 | 11905 | |
252b5132 | 11906 | case 'W': |
df58fc94 | 11907 | INSERT_OPERAND (mips_opts.micromips, FT, *ip, lastregno); |
252b5132 RH |
11908 | continue; |
11909 | } | |
11910 | break; | |
11911 | ||
11912 | case 'I': | |
11913 | my_getExpression (&imm_expr, s); | |
11914 | if (imm_expr.X_op != O_big | |
11915 | && imm_expr.X_op != O_constant) | |
11916 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
11917 | if (HAVE_32BIT_GPRS) |
11918 | normalize_constant_expr (&imm_expr); | |
252b5132 RH |
11919 | s = expr_end; |
11920 | continue; | |
11921 | ||
11922 | case 'A': | |
11923 | my_getExpression (&offset_expr, s); | |
2051e8c4 | 11924 | normalize_address_expr (&offset_expr); |
f6688943 | 11925 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
11926 | s = expr_end; |
11927 | continue; | |
11928 | ||
11929 | case 'F': | |
11930 | case 'L': | |
11931 | case 'f': | |
11932 | case 'l': | |
11933 | { | |
11934 | int f64; | |
ca4e0257 | 11935 | int using_gprs; |
252b5132 RH |
11936 | char *save_in; |
11937 | char *err; | |
11938 | unsigned char temp[8]; | |
11939 | int len; | |
11940 | unsigned int length; | |
11941 | segT seg; | |
11942 | subsegT subseg; | |
11943 | char *p; | |
11944 | ||
11945 | /* These only appear as the last operand in an | |
11946 | instruction, and every instruction that accepts | |
11947 | them in any variant accepts them in all variants. | |
11948 | This means we don't have to worry about backing out | |
11949 | any changes if the instruction does not match. | |
11950 | ||
11951 | The difference between them is the size of the | |
11952 | floating point constant and where it goes. For 'F' | |
11953 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
11954 | is 32 bits. Where the constant is placed is based | |
11955 | on how the MIPS assembler does things: | |
11956 | F -- .rdata | |
11957 | L -- .lit8 | |
11958 | f -- immediate value | |
11959 | l -- .lit4 | |
11960 | ||
11961 | The .lit4 and .lit8 sections are only used if | |
11962 | permitted by the -G argument. | |
11963 | ||
ca4e0257 RS |
11964 | The code below needs to know whether the target register |
11965 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
11966 | 'F' are used with GPR-based instructions and 'l' and | |
11967 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
11968 | |
11969 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 11970 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
11971 | |
11972 | save_in = input_line_pointer; | |
11973 | input_line_pointer = s; | |
11974 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
11975 | length = len; | |
11976 | s = input_line_pointer; | |
11977 | input_line_pointer = save_in; | |
11978 | if (err != NULL && *err != '\0') | |
11979 | { | |
11980 | as_bad (_("Bad floating point constant: %s"), err); | |
11981 | memset (temp, '\0', sizeof temp); | |
11982 | length = f64 ? 8 : 4; | |
11983 | } | |
11984 | ||
9c2799c2 | 11985 | gas_assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
11986 | |
11987 | if (*args == 'f' | |
11988 | || (*args == 'l' | |
3e722fb5 | 11989 | && (g_switch_value < 4 |
252b5132 RH |
11990 | || (temp[0] == 0 && temp[1] == 0) |
11991 | || (temp[2] == 0 && temp[3] == 0)))) | |
11992 | { | |
11993 | imm_expr.X_op = O_constant; | |
90ecf173 | 11994 | if (!target_big_endian) |
252b5132 RH |
11995 | imm_expr.X_add_number = bfd_getl32 (temp); |
11996 | else | |
11997 | imm_expr.X_add_number = bfd_getb32 (temp); | |
11998 | } | |
11999 | else if (length > 4 | |
90ecf173 | 12000 | && !mips_disable_float_construction |
ca4e0257 RS |
12001 | /* Constants can only be constructed in GPRs and |
12002 | copied to FPRs if the GPRs are at least as wide | |
12003 | as the FPRs. Force the constant into memory if | |
12004 | we are using 64-bit FPRs but the GPRs are only | |
12005 | 32 bits wide. */ | |
12006 | && (using_gprs | |
90ecf173 | 12007 | || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) |
252b5132 RH |
12008 | && ((temp[0] == 0 && temp[1] == 0) |
12009 | || (temp[2] == 0 && temp[3] == 0)) | |
12010 | && ((temp[4] == 0 && temp[5] == 0) | |
12011 | || (temp[6] == 0 && temp[7] == 0))) | |
12012 | { | |
ca4e0257 | 12013 | /* The value is simple enough to load with a couple of |
90ecf173 MR |
12014 | instructions. If using 32-bit registers, set |
12015 | imm_expr to the high order 32 bits and offset_expr to | |
12016 | the low order 32 bits. Otherwise, set imm_expr to | |
12017 | the entire 64 bit constant. */ | |
ca4e0257 | 12018 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) |
252b5132 RH |
12019 | { |
12020 | imm_expr.X_op = O_constant; | |
12021 | offset_expr.X_op = O_constant; | |
90ecf173 | 12022 | if (!target_big_endian) |
252b5132 RH |
12023 | { |
12024 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
12025 | offset_expr.X_add_number = bfd_getl32 (temp); | |
12026 | } | |
12027 | else | |
12028 | { | |
12029 | imm_expr.X_add_number = bfd_getb32 (temp); | |
12030 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
12031 | } | |
12032 | if (offset_expr.X_add_number == 0) | |
12033 | offset_expr.X_op = O_absent; | |
12034 | } | |
12035 | else if (sizeof (imm_expr.X_add_number) > 4) | |
12036 | { | |
12037 | imm_expr.X_op = O_constant; | |
90ecf173 | 12038 | if (!target_big_endian) |
252b5132 RH |
12039 | imm_expr.X_add_number = bfd_getl64 (temp); |
12040 | else | |
12041 | imm_expr.X_add_number = bfd_getb64 (temp); | |
12042 | } | |
12043 | else | |
12044 | { | |
12045 | imm_expr.X_op = O_big; | |
12046 | imm_expr.X_add_number = 4; | |
90ecf173 | 12047 | if (!target_big_endian) |
252b5132 RH |
12048 | { |
12049 | generic_bignum[0] = bfd_getl16 (temp); | |
12050 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
12051 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
12052 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
12053 | } | |
12054 | else | |
12055 | { | |
12056 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
12057 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
12058 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
12059 | generic_bignum[3] = bfd_getb16 (temp); | |
12060 | } | |
12061 | } | |
12062 | } | |
12063 | else | |
12064 | { | |
12065 | const char *newname; | |
12066 | segT new_seg; | |
12067 | ||
12068 | /* Switch to the right section. */ | |
12069 | seg = now_seg; | |
12070 | subseg = now_subseg; | |
12071 | switch (*args) | |
12072 | { | |
12073 | default: /* unused default case avoids warnings. */ | |
12074 | case 'L': | |
12075 | newname = RDATA_SECTION_NAME; | |
3e722fb5 | 12076 | if (g_switch_value >= 8) |
252b5132 RH |
12077 | newname = ".lit8"; |
12078 | break; | |
12079 | case 'F': | |
3e722fb5 | 12080 | newname = RDATA_SECTION_NAME; |
252b5132 RH |
12081 | break; |
12082 | case 'l': | |
9c2799c2 | 12083 | gas_assert (g_switch_value >= 4); |
252b5132 RH |
12084 | newname = ".lit4"; |
12085 | break; | |
12086 | } | |
12087 | new_seg = subseg_new (newname, (subsegT) 0); | |
f43abd2b | 12088 | if (IS_ELF) |
252b5132 RH |
12089 | bfd_set_section_flags (stdoutput, new_seg, |
12090 | (SEC_ALLOC | |
12091 | | SEC_LOAD | |
12092 | | SEC_READONLY | |
12093 | | SEC_DATA)); | |
12094 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
c41e87e3 | 12095 | if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0) |
252b5132 RH |
12096 | record_alignment (new_seg, 4); |
12097 | else | |
12098 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
12099 | if (seg == now_seg) | |
12100 | as_bad (_("Can't use floating point insn in this section")); | |
12101 | ||
df58fc94 RS |
12102 | /* Set the argument to the current address in the |
12103 | section. */ | |
12104 | offset_expr.X_op = O_symbol; | |
12105 | offset_expr.X_add_symbol = symbol_temp_new_now (); | |
12106 | offset_expr.X_add_number = 0; | |
12107 | ||
12108 | /* Put the floating point number into the section. */ | |
12109 | p = frag_more ((int) length); | |
12110 | memcpy (p, temp, length); | |
12111 | ||
12112 | /* Switch back to the original section. */ | |
12113 | subseg_set (seg, subseg); | |
12114 | } | |
12115 | } | |
12116 | continue; | |
12117 | ||
12118 | case 'i': /* 16-bit unsigned immediate. */ | |
12119 | case 'j': /* 16-bit signed immediate. */ | |
12120 | *imm_reloc = BFD_RELOC_LO16; | |
12121 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) | |
12122 | { | |
12123 | int more; | |
12124 | offsetT minval, maxval; | |
12125 | ||
12126 | more = (insn + 1 < past | |
12127 | && strcmp (insn->name, insn[1].name) == 0); | |
12128 | ||
12129 | /* If the expression was written as an unsigned number, | |
12130 | only treat it as signed if there are no more | |
12131 | alternatives. */ | |
12132 | if (more | |
12133 | && *args == 'j' | |
12134 | && sizeof (imm_expr.X_add_number) <= 4 | |
12135 | && imm_expr.X_op == O_constant | |
12136 | && imm_expr.X_add_number < 0 | |
12137 | && imm_expr.X_unsigned | |
12138 | && HAVE_64BIT_GPRS) | |
12139 | break; | |
12140 | ||
12141 | /* For compatibility with older assemblers, we accept | |
12142 | 0x8000-0xffff as signed 16-bit numbers when only | |
12143 | signed numbers are allowed. */ | |
12144 | if (*args == 'i') | |
12145 | minval = 0, maxval = 0xffff; | |
12146 | else if (more) | |
12147 | minval = -0x8000, maxval = 0x7fff; | |
12148 | else | |
12149 | minval = -0x8000, maxval = 0xffff; | |
12150 | ||
12151 | if (imm_expr.X_op != O_constant | |
12152 | || imm_expr.X_add_number < minval | |
12153 | || imm_expr.X_add_number > maxval) | |
12154 | { | |
12155 | if (more) | |
12156 | break; | |
12157 | if (imm_expr.X_op == O_constant | |
12158 | || imm_expr.X_op == O_big) | |
12159 | as_bad (_("Expression out of range")); | |
12160 | } | |
12161 | } | |
12162 | s = expr_end; | |
12163 | continue; | |
12164 | ||
12165 | case 'o': /* 16-bit offset. */ | |
12166 | offset_reloc[0] = BFD_RELOC_LO16; | |
12167 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
12168 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
12169 | ||
12170 | /* Check whether there is only a single bracketed expression | |
12171 | left. If so, it must be the base register and the | |
12172 | constant must be zero. */ | |
12173 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12174 | { | |
12175 | offset_expr.X_op = O_constant; | |
12176 | offset_expr.X_add_number = 0; | |
12177 | continue; | |
12178 | } | |
12179 | ||
12180 | /* If this value won't fit into a 16 bit offset, then go | |
12181 | find a macro that will generate the 32 bit offset | |
12182 | code pattern. */ | |
12183 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 | |
12184 | && (offset_expr.X_op != O_constant | |
12185 | || offset_expr.X_add_number >= 0x8000 | |
12186 | || offset_expr.X_add_number < -0x8000)) | |
12187 | break; | |
12188 | ||
12189 | s = expr_end; | |
12190 | continue; | |
12191 | ||
12192 | case 'p': /* PC-relative offset. */ | |
12193 | *offset_reloc = BFD_RELOC_16_PCREL_S2; | |
12194 | my_getExpression (&offset_expr, s); | |
12195 | s = expr_end; | |
12196 | continue; | |
12197 | ||
12198 | case 'u': /* Upper 16 bits. */ | |
12199 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 | |
12200 | && imm_expr.X_op == O_constant | |
12201 | && (imm_expr.X_add_number < 0 | |
12202 | || imm_expr.X_add_number >= 0x10000)) | |
12203 | as_bad (_("lui expression (%lu) not in range 0..65535"), | |
12204 | (unsigned long) imm_expr.X_add_number); | |
12205 | s = expr_end; | |
12206 | continue; | |
12207 | ||
12208 | case 'a': /* 26-bit address. */ | |
12209 | *offset_reloc = BFD_RELOC_MIPS_JMP; | |
12210 | my_getExpression (&offset_expr, s); | |
12211 | s = expr_end; | |
12212 | continue; | |
12213 | ||
12214 | case 'N': /* 3-bit branch condition code. */ | |
12215 | case 'M': /* 3-bit compare condition code. */ | |
12216 | rtype = RTYPE_CCC; | |
12217 | if (ip->insn_mo->pinfo & (FP_D | FP_S)) | |
12218 | rtype |= RTYPE_FCC; | |
12219 | if (!reg_lookup (&s, rtype, ®no)) | |
12220 | break; | |
12221 | if ((strcmp (str + strlen (str) - 3, ".ps") == 0 | |
12222 | || strcmp (str + strlen (str) - 5, "any2f") == 0 | |
12223 | || strcmp (str + strlen (str) - 5, "any2t") == 0) | |
12224 | && (regno & 1) != 0) | |
12225 | as_warn (_("Condition code register should be even for %s, " | |
12226 | "was %d"), | |
12227 | str, regno); | |
12228 | if ((strcmp (str + strlen (str) - 5, "any4f") == 0 | |
12229 | || strcmp (str + strlen (str) - 5, "any4t") == 0) | |
12230 | && (regno & 3) != 0) | |
12231 | as_warn (_("Condition code register should be 0 or 4 for %s, " | |
12232 | "was %d"), | |
12233 | str, regno); | |
12234 | if (*args == 'N') | |
12235 | INSERT_OPERAND (mips_opts.micromips, BCC, *ip, regno); | |
12236 | else | |
12237 | INSERT_OPERAND (mips_opts.micromips, CCC, *ip, regno); | |
12238 | continue; | |
12239 | ||
12240 | case 'H': | |
12241 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
12242 | s += 2; | |
12243 | if (ISDIGIT (*s)) | |
12244 | { | |
12245 | c = 0; | |
12246 | do | |
12247 | { | |
12248 | c *= 10; | |
12249 | c += *s - '0'; | |
12250 | ++s; | |
12251 | } | |
12252 | while (ISDIGIT (*s)); | |
12253 | } | |
12254 | else | |
12255 | c = 8; /* Invalid sel value. */ | |
12256 | ||
12257 | if (c > 7) | |
12258 | as_bad (_("Invalid coprocessor sub-selection value (0-7)")); | |
12259 | INSERT_OPERAND (mips_opts.micromips, SEL, *ip, c); | |
12260 | continue; | |
12261 | ||
12262 | case 'e': | |
12263 | gas_assert (!mips_opts.micromips); | |
12264 | /* Must be at least one digit. */ | |
12265 | my_getExpression (&imm_expr, s); | |
12266 | check_absolute_expr (ip, &imm_expr); | |
12267 | ||
12268 | if ((unsigned long) imm_expr.X_add_number | |
12269 | > (unsigned long) OP_MASK_VECBYTE) | |
12270 | { | |
12271 | as_bad (_("bad byte vector index (%ld)"), | |
12272 | (long) imm_expr.X_add_number); | |
12273 | imm_expr.X_add_number = 0; | |
12274 | } | |
12275 | ||
12276 | INSERT_OPERAND (0, VECBYTE, *ip, imm_expr.X_add_number); | |
12277 | imm_expr.X_op = O_absent; | |
12278 | s = expr_end; | |
12279 | continue; | |
12280 | ||
12281 | case '%': | |
12282 | gas_assert (!mips_opts.micromips); | |
12283 | my_getExpression (&imm_expr, s); | |
12284 | check_absolute_expr (ip, &imm_expr); | |
12285 | ||
12286 | if ((unsigned long) imm_expr.X_add_number | |
12287 | > (unsigned long) OP_MASK_VECALIGN) | |
12288 | { | |
12289 | as_bad (_("bad byte vector index (%ld)"), | |
12290 | (long) imm_expr.X_add_number); | |
12291 | imm_expr.X_add_number = 0; | |
12292 | } | |
12293 | ||
12294 | INSERT_OPERAND (0, VECALIGN, *ip, imm_expr.X_add_number); | |
12295 | imm_expr.X_op = O_absent; | |
12296 | s = expr_end; | |
12297 | continue; | |
12298 | ||
12299 | case 'm': /* Opcode extension character. */ | |
12300 | gas_assert (mips_opts.micromips); | |
12301 | c = *++args; | |
12302 | switch (c) | |
12303 | { | |
12304 | case 'r': | |
12305 | if (strncmp (s, "$pc", 3) == 0) | |
12306 | { | |
12307 | s += 3; | |
12308 | continue; | |
12309 | } | |
12310 | break; | |
12311 | ||
12312 | case 'a': | |
12313 | case 'b': | |
12314 | case 'c': | |
12315 | case 'd': | |
12316 | case 'e': | |
12317 | case 'f': | |
12318 | case 'g': | |
12319 | case 'h': | |
12320 | case 'i': | |
12321 | case 'j': | |
12322 | case 'l': | |
12323 | case 'm': | |
12324 | case 'n': | |
12325 | case 'p': | |
12326 | case 'q': | |
12327 | case 's': | |
12328 | case 't': | |
12329 | case 'x': | |
12330 | case 'y': | |
12331 | case 'z': | |
12332 | s_reset = s; | |
12333 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
12334 | if (regno == AT && mips_opts.at) | |
12335 | { | |
12336 | if (mips_opts.at == ATREG) | |
12337 | as_warn (_("Used $at without \".set noat\"")); | |
12338 | else | |
12339 | as_warn (_("Used $%u with \".set at=$%u\""), | |
12340 | regno, mips_opts.at); | |
12341 | } | |
12342 | if (!ok) | |
12343 | { | |
12344 | if (c == 'c') | |
12345 | { | |
12346 | gas_assert (args[1] == ','); | |
12347 | regno = lastregno; | |
12348 | ++args; | |
12349 | } | |
12350 | else if (c == 't') | |
12351 | { | |
12352 | gas_assert (args[1] == ','); | |
12353 | ++args; | |
12354 | continue; /* Nothing to do. */ | |
12355 | } | |
12356 | else | |
12357 | break; | |
12358 | } | |
12359 | ||
12360 | if (c == 'j' && !strncmp (ip->insn_mo->name, "jalr", 4)) | |
12361 | { | |
12362 | if (regno == lastregno) | |
12363 | { | |
12364 | insn_error | |
12365 | = _("Source and destination must be different"); | |
12366 | continue; | |
12367 | } | |
12368 | if (regno == 31 && lastregno == 0xffffffff) | |
12369 | { | |
12370 | insn_error | |
12371 | = _("A destination register must be supplied"); | |
12372 | continue; | |
12373 | } | |
12374 | } | |
12375 | ||
12376 | if (*s == ' ') | |
12377 | ++s; | |
12378 | if (args[1] != *s) | |
12379 | { | |
12380 | if (c == 'e') | |
12381 | { | |
12382 | gas_assert (args[1] == ','); | |
12383 | regno = lastregno; | |
12384 | s = s_reset; | |
12385 | ++args; | |
12386 | } | |
12387 | else if (c == 't') | |
12388 | { | |
12389 | gas_assert (args[1] == ','); | |
12390 | s = s_reset; | |
12391 | ++args; | |
12392 | continue; /* Nothing to do. */ | |
12393 | } | |
12394 | } | |
12395 | ||
12396 | /* Make sure regno is the same as lastregno. */ | |
12397 | if (c == 't' && regno != lastregno) | |
12398 | break; | |
12399 | ||
12400 | /* Make sure regno is the same as destregno. */ | |
12401 | if (c == 'x' && regno != destregno) | |
12402 | break; | |
12403 | ||
12404 | /* We need to save regno, before regno maps to the | |
12405 | microMIPS register encoding. */ | |
12406 | lastregno = regno; | |
12407 | ||
12408 | if (c == 'f') | |
12409 | destregno = regno; | |
12410 | ||
12411 | switch (c) | |
12412 | { | |
12413 | case 'a': | |
12414 | if (regno != GP) | |
12415 | regno = ILLEGAL_REG; | |
12416 | break; | |
12417 | ||
12418 | case 'b': | |
12419 | regno = mips32_to_micromips_reg_b_map[regno]; | |
12420 | break; | |
12421 | ||
12422 | case 'c': | |
12423 | regno = mips32_to_micromips_reg_c_map[regno]; | |
12424 | break; | |
12425 | ||
12426 | case 'd': | |
12427 | regno = mips32_to_micromips_reg_d_map[regno]; | |
12428 | break; | |
12429 | ||
12430 | case 'e': | |
12431 | regno = mips32_to_micromips_reg_e_map[regno]; | |
12432 | break; | |
12433 | ||
12434 | case 'f': | |
12435 | regno = mips32_to_micromips_reg_f_map[regno]; | |
12436 | break; | |
12437 | ||
12438 | case 'g': | |
12439 | regno = mips32_to_micromips_reg_g_map[regno]; | |
12440 | break; | |
12441 | ||
12442 | case 'h': | |
12443 | regno = mips32_to_micromips_reg_h_map[regno]; | |
12444 | break; | |
12445 | ||
12446 | case 'i': | |
12447 | switch (EXTRACT_OPERAND (1, MI, *ip)) | |
12448 | { | |
12449 | case 4: | |
12450 | if (regno == 21) | |
12451 | regno = 3; | |
12452 | else if (regno == 22) | |
12453 | regno = 4; | |
12454 | else if (regno == 5) | |
12455 | regno = 5; | |
12456 | else if (regno == 6) | |
12457 | regno = 6; | |
12458 | else if (regno == 7) | |
12459 | regno = 7; | |
12460 | else | |
12461 | regno = ILLEGAL_REG; | |
12462 | break; | |
12463 | ||
12464 | case 5: | |
12465 | if (regno == 6) | |
12466 | regno = 0; | |
12467 | else if (regno == 7) | |
12468 | regno = 1; | |
12469 | else | |
12470 | regno = ILLEGAL_REG; | |
12471 | break; | |
12472 | ||
12473 | case 6: | |
12474 | if (regno == 7) | |
12475 | regno = 2; | |
12476 | else | |
12477 | regno = ILLEGAL_REG; | |
12478 | break; | |
12479 | ||
12480 | default: | |
12481 | regno = ILLEGAL_REG; | |
12482 | break; | |
12483 | } | |
12484 | break; | |
12485 | ||
12486 | case 'l': | |
12487 | regno = mips32_to_micromips_reg_l_map[regno]; | |
12488 | break; | |
12489 | ||
12490 | case 'm': | |
12491 | regno = mips32_to_micromips_reg_m_map[regno]; | |
12492 | break; | |
12493 | ||
12494 | case 'n': | |
12495 | regno = mips32_to_micromips_reg_n_map[regno]; | |
12496 | break; | |
12497 | ||
12498 | case 'q': | |
12499 | regno = mips32_to_micromips_reg_q_map[regno]; | |
12500 | break; | |
12501 | ||
12502 | case 's': | |
12503 | if (regno != SP) | |
12504 | regno = ILLEGAL_REG; | |
12505 | break; | |
12506 | ||
12507 | case 'y': | |
12508 | if (regno != 31) | |
12509 | regno = ILLEGAL_REG; | |
12510 | break; | |
12511 | ||
12512 | case 'z': | |
12513 | if (regno != ZERO) | |
12514 | regno = ILLEGAL_REG; | |
12515 | break; | |
12516 | ||
12517 | case 'j': /* Do nothing. */ | |
12518 | case 'p': | |
12519 | case 't': | |
12520 | case 'x': | |
12521 | break; | |
12522 | ||
12523 | default: | |
12524 | internalError (); | |
12525 | } | |
12526 | ||
12527 | if (regno == ILLEGAL_REG) | |
12528 | break; | |
12529 | ||
12530 | switch (c) | |
12531 | { | |
12532 | case 'b': | |
12533 | INSERT_OPERAND (1, MB, *ip, regno); | |
12534 | break; | |
12535 | ||
12536 | case 'c': | |
12537 | INSERT_OPERAND (1, MC, *ip, regno); | |
12538 | break; | |
12539 | ||
12540 | case 'd': | |
12541 | INSERT_OPERAND (1, MD, *ip, regno); | |
12542 | break; | |
12543 | ||
12544 | case 'e': | |
12545 | INSERT_OPERAND (1, ME, *ip, regno); | |
12546 | break; | |
12547 | ||
12548 | case 'f': | |
12549 | INSERT_OPERAND (1, MF, *ip, regno); | |
12550 | break; | |
12551 | ||
12552 | case 'g': | |
12553 | INSERT_OPERAND (1, MG, *ip, regno); | |
12554 | break; | |
12555 | ||
12556 | case 'h': | |
12557 | INSERT_OPERAND (1, MH, *ip, regno); | |
12558 | break; | |
12559 | ||
12560 | case 'i': | |
12561 | INSERT_OPERAND (1, MI, *ip, regno); | |
12562 | break; | |
12563 | ||
12564 | case 'j': | |
12565 | INSERT_OPERAND (1, MJ, *ip, regno); | |
12566 | break; | |
12567 | ||
12568 | case 'l': | |
12569 | INSERT_OPERAND (1, ML, *ip, regno); | |
12570 | break; | |
12571 | ||
12572 | case 'm': | |
12573 | INSERT_OPERAND (1, MM, *ip, regno); | |
12574 | break; | |
12575 | ||
12576 | case 'n': | |
12577 | INSERT_OPERAND (1, MN, *ip, regno); | |
12578 | break; | |
12579 | ||
12580 | case 'p': | |
12581 | INSERT_OPERAND (1, MP, *ip, regno); | |
12582 | break; | |
12583 | ||
12584 | case 'q': | |
12585 | INSERT_OPERAND (1, MQ, *ip, regno); | |
12586 | break; | |
12587 | ||
12588 | case 'a': /* Do nothing. */ | |
12589 | case 's': /* Do nothing. */ | |
12590 | case 't': /* Do nothing. */ | |
12591 | case 'x': /* Do nothing. */ | |
12592 | case 'y': /* Do nothing. */ | |
12593 | case 'z': /* Do nothing. */ | |
12594 | break; | |
12595 | ||
12596 | default: | |
12597 | internalError (); | |
12598 | } | |
12599 | continue; | |
12600 | ||
12601 | case 'A': | |
12602 | { | |
12603 | bfd_reloc_code_real_type r[3]; | |
12604 | expressionS ep; | |
12605 | int imm; | |
12606 | ||
12607 | /* Check whether there is only a single bracketed | |
12608 | expression left. If so, it must be the base register | |
12609 | and the constant must be zero. */ | |
12610 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12611 | { | |
12612 | INSERT_OPERAND (1, IMMA, *ip, 0); | |
12613 | continue; | |
12614 | } | |
12615 | ||
12616 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12617 | || !expr_const_in_range (&ep, -64, 64, 2)) | |
12618 | break; | |
12619 | ||
12620 | imm = ep.X_add_number >> 2; | |
12621 | INSERT_OPERAND (1, IMMA, *ip, imm); | |
12622 | } | |
12623 | s = expr_end; | |
12624 | continue; | |
12625 | ||
12626 | case 'B': | |
12627 | { | |
12628 | bfd_reloc_code_real_type r[3]; | |
12629 | expressionS ep; | |
12630 | int imm; | |
12631 | ||
12632 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12633 | || ep.X_op != O_constant) | |
12634 | break; | |
12635 | ||
12636 | for (imm = 0; imm < 8; imm++) | |
12637 | if (micromips_imm_b_map[imm] == ep.X_add_number) | |
12638 | break; | |
12639 | if (imm >= 8) | |
12640 | break; | |
12641 | ||
12642 | INSERT_OPERAND (1, IMMB, *ip, imm); | |
12643 | } | |
12644 | s = expr_end; | |
12645 | continue; | |
12646 | ||
12647 | case 'C': | |
12648 | { | |
12649 | bfd_reloc_code_real_type r[3]; | |
12650 | expressionS ep; | |
12651 | int imm; | |
12652 | ||
12653 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12654 | || ep.X_op != O_constant) | |
12655 | break; | |
12656 | ||
12657 | for (imm = 0; imm < 16; imm++) | |
12658 | if (micromips_imm_c_map[imm] == ep.X_add_number) | |
12659 | break; | |
12660 | if (imm >= 16) | |
12661 | break; | |
12662 | ||
12663 | INSERT_OPERAND (1, IMMC, *ip, imm); | |
12664 | } | |
12665 | s = expr_end; | |
12666 | continue; | |
12667 | ||
12668 | case 'D': /* pc relative offset */ | |
12669 | case 'E': /* pc relative offset */ | |
12670 | my_getExpression (&offset_expr, s); | |
12671 | if (offset_expr.X_op == O_register) | |
12672 | break; | |
12673 | ||
40209cad MR |
12674 | if (!forced_insn_length) |
12675 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; | |
12676 | else if (c == 'D') | |
12677 | *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1; | |
12678 | else | |
12679 | *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1; | |
df58fc94 RS |
12680 | s = expr_end; |
12681 | continue; | |
12682 | ||
12683 | case 'F': | |
12684 | { | |
12685 | bfd_reloc_code_real_type r[3]; | |
12686 | expressionS ep; | |
12687 | int imm; | |
12688 | ||
12689 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12690 | || !expr_const_in_range (&ep, 0, 16, 0)) | |
12691 | break; | |
12692 | ||
12693 | imm = ep.X_add_number; | |
12694 | INSERT_OPERAND (1, IMMF, *ip, imm); | |
12695 | } | |
12696 | s = expr_end; | |
12697 | continue; | |
12698 | ||
12699 | case 'G': | |
12700 | { | |
12701 | bfd_reloc_code_real_type r[3]; | |
12702 | expressionS ep; | |
12703 | int imm; | |
12704 | ||
12705 | /* Check whether there is only a single bracketed | |
12706 | expression left. If so, it must be the base register | |
12707 | and the constant must be zero. */ | |
12708 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12709 | { | |
12710 | INSERT_OPERAND (1, IMMG, *ip, 0); | |
12711 | continue; | |
12712 | } | |
12713 | ||
12714 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12715 | || !expr_const_in_range (&ep, -1, 15, 0)) | |
12716 | break; | |
12717 | ||
12718 | imm = ep.X_add_number & 15; | |
12719 | INSERT_OPERAND (1, IMMG, *ip, imm); | |
12720 | } | |
12721 | s = expr_end; | |
12722 | continue; | |
12723 | ||
12724 | case 'H': | |
12725 | { | |
12726 | bfd_reloc_code_real_type r[3]; | |
12727 | expressionS ep; | |
12728 | int imm; | |
12729 | ||
12730 | /* Check whether there is only a single bracketed | |
12731 | expression left. If so, it must be the base register | |
12732 | and the constant must be zero. */ | |
12733 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12734 | { | |
12735 | INSERT_OPERAND (1, IMMH, *ip, 0); | |
12736 | continue; | |
12737 | } | |
12738 | ||
12739 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12740 | || !expr_const_in_range (&ep, 0, 16, 1)) | |
12741 | break; | |
12742 | ||
12743 | imm = ep.X_add_number >> 1; | |
12744 | INSERT_OPERAND (1, IMMH, *ip, imm); | |
12745 | } | |
12746 | s = expr_end; | |
12747 | continue; | |
12748 | ||
12749 | case 'I': | |
12750 | { | |
12751 | bfd_reloc_code_real_type r[3]; | |
12752 | expressionS ep; | |
12753 | int imm; | |
12754 | ||
12755 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12756 | || !expr_const_in_range (&ep, -1, 127, 0)) | |
12757 | break; | |
12758 | ||
12759 | imm = ep.X_add_number & 127; | |
12760 | INSERT_OPERAND (1, IMMI, *ip, imm); | |
12761 | } | |
12762 | s = expr_end; | |
12763 | continue; | |
12764 | ||
12765 | case 'J': | |
12766 | { | |
12767 | bfd_reloc_code_real_type r[3]; | |
12768 | expressionS ep; | |
12769 | int imm; | |
12770 | ||
12771 | /* Check whether there is only a single bracketed | |
12772 | expression left. If so, it must be the base register | |
12773 | and the constant must be zero. */ | |
12774 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12775 | { | |
12776 | INSERT_OPERAND (1, IMMJ, *ip, 0); | |
12777 | continue; | |
12778 | } | |
12779 | ||
12780 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12781 | || !expr_const_in_range (&ep, 0, 16, 2)) | |
12782 | break; | |
12783 | ||
12784 | imm = ep.X_add_number >> 2; | |
12785 | INSERT_OPERAND (1, IMMJ, *ip, imm); | |
12786 | } | |
12787 | s = expr_end; | |
12788 | continue; | |
12789 | ||
12790 | case 'L': | |
12791 | { | |
12792 | bfd_reloc_code_real_type r[3]; | |
12793 | expressionS ep; | |
12794 | int imm; | |
12795 | ||
12796 | /* Check whether there is only a single bracketed | |
12797 | expression left. If so, it must be the base register | |
12798 | and the constant must be zero. */ | |
12799 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12800 | { | |
12801 | INSERT_OPERAND (1, IMML, *ip, 0); | |
12802 | continue; | |
12803 | } | |
12804 | ||
12805 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12806 | || !expr_const_in_range (&ep, 0, 16, 0)) | |
12807 | break; | |
12808 | ||
12809 | imm = ep.X_add_number; | |
12810 | INSERT_OPERAND (1, IMML, *ip, imm); | |
12811 | } | |
12812 | s = expr_end; | |
12813 | continue; | |
12814 | ||
12815 | case 'M': | |
12816 | { | |
12817 | bfd_reloc_code_real_type r[3]; | |
12818 | expressionS ep; | |
12819 | int imm; | |
12820 | ||
12821 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12822 | || !expr_const_in_range (&ep, 1, 9, 0)) | |
12823 | break; | |
12824 | ||
12825 | imm = ep.X_add_number & 7; | |
12826 | INSERT_OPERAND (1, IMMM, *ip, imm); | |
12827 | } | |
12828 | s = expr_end; | |
12829 | continue; | |
12830 | ||
12831 | case 'N': /* Register list for lwm and swm. */ | |
12832 | { | |
12833 | /* A comma-separated list of registers and/or | |
12834 | dash-separated contiguous ranges including | |
12835 | both ra and a set of one or more registers | |
12836 | starting at s0 up to s3 which have to be | |
12837 | consecutive, e.g.: | |
12838 | ||
12839 | s0, ra | |
12840 | s0, s1, ra, s2, s3 | |
12841 | s0-s2, ra | |
12842 | ||
12843 | and any permutations of these. */ | |
12844 | unsigned int reglist; | |
12845 | int imm; | |
12846 | ||
12847 | if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list)) | |
12848 | break; | |
12849 | ||
12850 | if ((reglist & 0xfff1ffff) != 0x80010000) | |
12851 | break; | |
12852 | ||
12853 | reglist = (reglist >> 17) & 7; | |
12854 | reglist += 1; | |
12855 | if ((reglist & -reglist) != reglist) | |
12856 | break; | |
252b5132 | 12857 | |
df58fc94 RS |
12858 | imm = ffs (reglist) - 1; |
12859 | INSERT_OPERAND (1, IMMN, *ip, imm); | |
12860 | } | |
12861 | continue; | |
252b5132 | 12862 | |
df58fc94 RS |
12863 | case 'O': /* sdbbp 4-bit code. */ |
12864 | { | |
12865 | bfd_reloc_code_real_type r[3]; | |
12866 | expressionS ep; | |
12867 | int imm; | |
12868 | ||
12869 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12870 | || !expr_const_in_range (&ep, 0, 16, 0)) | |
12871 | break; | |
12872 | ||
12873 | imm = ep.X_add_number; | |
12874 | INSERT_OPERAND (1, IMMO, *ip, imm); | |
252b5132 | 12875 | } |
df58fc94 RS |
12876 | s = expr_end; |
12877 | continue; | |
252b5132 | 12878 | |
df58fc94 RS |
12879 | case 'P': |
12880 | { | |
12881 | bfd_reloc_code_real_type r[3]; | |
12882 | expressionS ep; | |
12883 | int imm; | |
5e0116d5 | 12884 | |
df58fc94 RS |
12885 | if (my_getSmallExpression (&ep, r, s) > 0 |
12886 | || !expr_const_in_range (&ep, 0, 32, 2)) | |
12887 | break; | |
5e0116d5 | 12888 | |
df58fc94 RS |
12889 | imm = ep.X_add_number >> 2; |
12890 | INSERT_OPERAND (1, IMMP, *ip, imm); | |
12891 | } | |
12892 | s = expr_end; | |
12893 | continue; | |
5e0116d5 | 12894 | |
df58fc94 RS |
12895 | case 'Q': |
12896 | { | |
12897 | bfd_reloc_code_real_type r[3]; | |
12898 | expressionS ep; | |
12899 | int imm; | |
5e0116d5 | 12900 | |
df58fc94 RS |
12901 | if (my_getSmallExpression (&ep, r, s) > 0 |
12902 | || !expr_const_in_range (&ep, -0x400000, 0x400000, 2)) | |
12903 | break; | |
252b5132 | 12904 | |
df58fc94 RS |
12905 | imm = ep.X_add_number >> 2; |
12906 | INSERT_OPERAND (1, IMMQ, *ip, imm); | |
12907 | } | |
12908 | s = expr_end; | |
12909 | continue; | |
4614d845 | 12910 | |
df58fc94 RS |
12911 | case 'U': |
12912 | { | |
12913 | bfd_reloc_code_real_type r[3]; | |
12914 | expressionS ep; | |
12915 | int imm; | |
12916 | ||
12917 | /* Check whether there is only a single bracketed | |
12918 | expression left. If so, it must be the base register | |
12919 | and the constant must be zero. */ | |
12920 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12921 | { | |
12922 | INSERT_OPERAND (1, IMMU, *ip, 0); | |
12923 | continue; | |
12924 | } | |
12925 | ||
12926 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12927 | || !expr_const_in_range (&ep, 0, 32, 2)) | |
12928 | break; | |
12929 | ||
12930 | imm = ep.X_add_number >> 2; | |
12931 | INSERT_OPERAND (1, IMMU, *ip, imm); | |
12932 | } | |
12933 | s = expr_end; | |
5e0116d5 | 12934 | continue; |
252b5132 | 12935 | |
df58fc94 RS |
12936 | case 'W': |
12937 | { | |
12938 | bfd_reloc_code_real_type r[3]; | |
12939 | expressionS ep; | |
12940 | int imm; | |
252b5132 | 12941 | |
df58fc94 RS |
12942 | if (my_getSmallExpression (&ep, r, s) > 0 |
12943 | || !expr_const_in_range (&ep, 0, 64, 2)) | |
12944 | break; | |
252b5132 | 12945 | |
df58fc94 RS |
12946 | imm = ep.X_add_number >> 2; |
12947 | INSERT_OPERAND (1, IMMW, *ip, imm); | |
12948 | } | |
12949 | s = expr_end; | |
12950 | continue; | |
252b5132 | 12951 | |
df58fc94 RS |
12952 | case 'X': |
12953 | { | |
12954 | bfd_reloc_code_real_type r[3]; | |
12955 | expressionS ep; | |
12956 | int imm; | |
252b5132 | 12957 | |
df58fc94 RS |
12958 | if (my_getSmallExpression (&ep, r, s) > 0 |
12959 | || !expr_const_in_range (&ep, -8, 8, 0)) | |
12960 | break; | |
252b5132 | 12961 | |
df58fc94 RS |
12962 | imm = ep.X_add_number; |
12963 | INSERT_OPERAND (1, IMMX, *ip, imm); | |
12964 | } | |
12965 | s = expr_end; | |
12966 | continue; | |
252b5132 | 12967 | |
df58fc94 RS |
12968 | case 'Y': |
12969 | { | |
12970 | bfd_reloc_code_real_type r[3]; | |
12971 | expressionS ep; | |
12972 | int imm; | |
156c2f8b | 12973 | |
df58fc94 RS |
12974 | if (my_getSmallExpression (&ep, r, s) > 0 |
12975 | || expr_const_in_range (&ep, -2, 2, 2) | |
12976 | || !expr_const_in_range (&ep, -258, 258, 2)) | |
12977 | break; | |
156c2f8b | 12978 | |
df58fc94 RS |
12979 | imm = ep.X_add_number >> 2; |
12980 | imm = ((imm >> 1) & ~0xff) | (imm & 0xff); | |
12981 | INSERT_OPERAND (1, IMMY, *ip, imm); | |
12982 | } | |
12983 | s = expr_end; | |
12984 | continue; | |
60b63b72 | 12985 | |
df58fc94 RS |
12986 | case 'Z': |
12987 | { | |
12988 | bfd_reloc_code_real_type r[3]; | |
12989 | expressionS ep; | |
12990 | ||
12991 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12992 | || !expr_const_in_range (&ep, 0, 1, 0)) | |
12993 | break; | |
12994 | } | |
12995 | s = expr_end; | |
12996 | continue; | |
12997 | ||
12998 | default: | |
12999 | as_bad (_("Internal error: bad microMIPS opcode " | |
13000 | "(unknown extension operand type `m%c'): %s %s"), | |
13001 | *args, insn->name, insn->args); | |
13002 | /* Further processing is fruitless. */ | |
13003 | return; | |
60b63b72 | 13004 | } |
df58fc94 | 13005 | break; |
60b63b72 | 13006 | |
df58fc94 RS |
13007 | case 'n': /* Register list for 32-bit lwm and swm. */ |
13008 | gas_assert (mips_opts.micromips); | |
13009 | { | |
13010 | /* A comma-separated list of registers and/or | |
13011 | dash-separated contiguous ranges including | |
13012 | at least one of ra and a set of one or more | |
13013 | registers starting at s0 up to s7 and then | |
13014 | s8 which have to be consecutive, e.g.: | |
13015 | ||
13016 | ra | |
13017 | s0 | |
13018 | ra, s0, s1, s2 | |
13019 | s0-s8 | |
13020 | s0-s5, ra | |
13021 | ||
13022 | and any permutations of these. */ | |
13023 | unsigned int reglist; | |
13024 | int imm; | |
13025 | int ra; | |
13026 | ||
13027 | if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list)) | |
13028 | break; | |
13029 | ||
13030 | if ((reglist & 0x3f00ffff) != 0) | |
13031 | break; | |
13032 | ||
13033 | ra = (reglist >> 27) & 0x10; | |
13034 | reglist = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff); | |
13035 | reglist += 1; | |
13036 | if ((reglist & -reglist) != reglist) | |
13037 | break; | |
13038 | ||
13039 | imm = (ffs (reglist) - 1) | ra; | |
13040 | INSERT_OPERAND (1, RT, *ip, imm); | |
13041 | imm_expr.X_op = O_absent; | |
13042 | } | |
60b63b72 RS |
13043 | continue; |
13044 | ||
df58fc94 RS |
13045 | case '|': /* 4-bit trap code. */ |
13046 | gas_assert (mips_opts.micromips); | |
60b63b72 RS |
13047 | my_getExpression (&imm_expr, s); |
13048 | check_absolute_expr (ip, &imm_expr); | |
60b63b72 | 13049 | if ((unsigned long) imm_expr.X_add_number |
df58fc94 RS |
13050 | > MICROMIPSOP_MASK_TRAP) |
13051 | as_bad (_("Trap code (%lu) for %s not in 0..15 range"), | |
13052 | (unsigned long) imm_expr.X_add_number, | |
13053 | ip->insn_mo->name); | |
13054 | INSERT_OPERAND (1, TRAP, *ip, imm_expr.X_add_number); | |
60b63b72 RS |
13055 | imm_expr.X_op = O_absent; |
13056 | s = expr_end; | |
13057 | continue; | |
13058 | ||
252b5132 | 13059 | default: |
f71d0d44 | 13060 | as_bad (_("Bad char = '%c'\n"), *args); |
252b5132 RH |
13061 | internalError (); |
13062 | } | |
13063 | break; | |
13064 | } | |
13065 | /* Args don't match. */ | |
df58fc94 RS |
13066 | s = argsStart; |
13067 | insn_error = _("Illegal operands"); | |
13068 | if (insn + 1 < past && !strcmp (insn->name, insn[1].name)) | |
252b5132 RH |
13069 | { |
13070 | ++insn; | |
252b5132 RH |
13071 | continue; |
13072 | } | |
df58fc94 RS |
13073 | else if (wrong_delay_slot_insns && need_delay_slot_ok) |
13074 | { | |
13075 | gas_assert (firstinsn); | |
13076 | need_delay_slot_ok = FALSE; | |
13077 | past = insn + 1; | |
13078 | insn = firstinsn; | |
13079 | continue; | |
13080 | } | |
252b5132 RH |
13081 | return; |
13082 | } | |
13083 | } | |
13084 | ||
0499d65b TS |
13085 | #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); } |
13086 | ||
252b5132 RH |
13087 | /* This routine assembles an instruction into its binary format when |
13088 | assembling for the mips16. As a side effect, it sets one of the | |
df58fc94 RS |
13089 | global variables imm_reloc or offset_reloc to the type of relocation |
13090 | to do if one of the operands is an address expression. It also sets | |
13091 | forced_insn_length to the resulting instruction size in bytes if the | |
13092 | user explicitly requested a small or extended instruction. */ | |
252b5132 RH |
13093 | |
13094 | static void | |
17a2f251 | 13095 | mips16_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
13096 | { |
13097 | char *s; | |
13098 | const char *args; | |
13099 | struct mips_opcode *insn; | |
13100 | char *argsstart; | |
13101 | unsigned int regno; | |
13102 | unsigned int lastregno = 0; | |
13103 | char *s_reset; | |
d6f16593 | 13104 | size_t i; |
252b5132 RH |
13105 | |
13106 | insn_error = NULL; | |
13107 | ||
df58fc94 | 13108 | forced_insn_length = 0; |
252b5132 | 13109 | |
3882b010 | 13110 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
13111 | ; |
13112 | switch (*s) | |
13113 | { | |
13114 | case '\0': | |
13115 | break; | |
13116 | ||
13117 | case ' ': | |
13118 | *s++ = '\0'; | |
13119 | break; | |
13120 | ||
13121 | case '.': | |
13122 | if (s[1] == 't' && s[2] == ' ') | |
13123 | { | |
13124 | *s = '\0'; | |
df58fc94 | 13125 | forced_insn_length = 2; |
252b5132 RH |
13126 | s += 3; |
13127 | break; | |
13128 | } | |
13129 | else if (s[1] == 'e' && s[2] == ' ') | |
13130 | { | |
13131 | *s = '\0'; | |
df58fc94 | 13132 | forced_insn_length = 4; |
252b5132 RH |
13133 | s += 3; |
13134 | break; | |
13135 | } | |
13136 | /* Fall through. */ | |
13137 | default: | |
13138 | insn_error = _("unknown opcode"); | |
13139 | return; | |
13140 | } | |
13141 | ||
df58fc94 RS |
13142 | if (mips_opts.noautoextend && !forced_insn_length) |
13143 | forced_insn_length = 2; | |
252b5132 RH |
13144 | |
13145 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
13146 | { | |
13147 | insn_error = _("unrecognized opcode"); | |
13148 | return; | |
13149 | } | |
13150 | ||
13151 | argsstart = s; | |
13152 | for (;;) | |
13153 | { | |
9b3f89ee TS |
13154 | bfd_boolean ok; |
13155 | ||
9c2799c2 | 13156 | gas_assert (strcmp (insn->name, str) == 0); |
252b5132 | 13157 | |
037b32b9 | 13158 | ok = is_opcode_valid_16 (insn); |
9b3f89ee TS |
13159 | if (! ok) |
13160 | { | |
13161 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] | |
13162 | && strcmp (insn->name, insn[1].name) == 0) | |
13163 | { | |
13164 | ++insn; | |
13165 | continue; | |
13166 | } | |
13167 | else | |
13168 | { | |
13169 | if (!insn_error) | |
13170 | { | |
13171 | static char buf[100]; | |
13172 | sprintf (buf, | |
13173 | _("opcode not supported on this processor: %s (%s)"), | |
13174 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
13175 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
13176 | insn_error = buf; | |
13177 | } | |
13178 | return; | |
13179 | } | |
13180 | } | |
13181 | ||
1e915849 | 13182 | create_insn (ip, insn); |
252b5132 | 13183 | imm_expr.X_op = O_absent; |
f6688943 TS |
13184 | imm_reloc[0] = BFD_RELOC_UNUSED; |
13185 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
13186 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
5f74bc13 | 13187 | imm2_expr.X_op = O_absent; |
252b5132 | 13188 | offset_expr.X_op = O_absent; |
f6688943 TS |
13189 | offset_reloc[0] = BFD_RELOC_UNUSED; |
13190 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
13191 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
13192 | for (args = insn->args; 1; ++args) |
13193 | { | |
13194 | int c; | |
13195 | ||
13196 | if (*s == ' ') | |
13197 | ++s; | |
13198 | ||
13199 | /* In this switch statement we call break if we did not find | |
13200 | a match, continue if we did find a match, or return if we | |
13201 | are done. */ | |
13202 | ||
13203 | c = *args; | |
13204 | switch (c) | |
13205 | { | |
13206 | case '\0': | |
13207 | if (*s == '\0') | |
13208 | { | |
13209 | /* Stuff the immediate value in now, if we can. */ | |
13210 | if (imm_expr.X_op == O_constant | |
f6688943 | 13211 | && *imm_reloc > BFD_RELOC_UNUSED |
738e5348 RS |
13212 | && *imm_reloc != BFD_RELOC_MIPS16_GOT16 |
13213 | && *imm_reloc != BFD_RELOC_MIPS16_CALL16 | |
252b5132 RH |
13214 | && insn->pinfo != INSN_MACRO) |
13215 | { | |
d6f16593 MR |
13216 | valueT tmp; |
13217 | ||
13218 | switch (*offset_reloc) | |
13219 | { | |
13220 | case BFD_RELOC_MIPS16_HI16_S: | |
13221 | tmp = (imm_expr.X_add_number + 0x8000) >> 16; | |
13222 | break; | |
13223 | ||
13224 | case BFD_RELOC_MIPS16_HI16: | |
13225 | tmp = imm_expr.X_add_number >> 16; | |
13226 | break; | |
13227 | ||
13228 | case BFD_RELOC_MIPS16_LO16: | |
13229 | tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff) | |
13230 | - 0x8000; | |
13231 | break; | |
13232 | ||
13233 | case BFD_RELOC_UNUSED: | |
13234 | tmp = imm_expr.X_add_number; | |
13235 | break; | |
13236 | ||
13237 | default: | |
13238 | internalError (); | |
13239 | } | |
13240 | *offset_reloc = BFD_RELOC_UNUSED; | |
13241 | ||
c4e7957c | 13242 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
df58fc94 RS |
13243 | tmp, TRUE, forced_insn_length == 2, |
13244 | forced_insn_length == 4, &ip->insn_opcode, | |
252b5132 RH |
13245 | &ip->use_extend, &ip->extend); |
13246 | imm_expr.X_op = O_absent; | |
f6688943 | 13247 | *imm_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
13248 | } |
13249 | ||
13250 | return; | |
13251 | } | |
13252 | break; | |
13253 | ||
13254 | case ',': | |
13255 | if (*s++ == c) | |
13256 | continue; | |
13257 | s--; | |
13258 | switch (*++args) | |
13259 | { | |
13260 | case 'v': | |
bf12938e | 13261 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 RH |
13262 | continue; |
13263 | case 'w': | |
bf12938e | 13264 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
13265 | continue; |
13266 | } | |
13267 | break; | |
13268 | ||
13269 | case '(': | |
13270 | case ')': | |
13271 | if (*s++ == c) | |
13272 | continue; | |
13273 | break; | |
13274 | ||
13275 | case 'v': | |
13276 | case 'w': | |
13277 | if (s[0] != '$') | |
13278 | { | |
13279 | if (c == 'v') | |
bf12938e | 13280 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 | 13281 | else |
bf12938e | 13282 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
13283 | ++args; |
13284 | continue; | |
13285 | } | |
13286 | /* Fall through. */ | |
13287 | case 'x': | |
13288 | case 'y': | |
13289 | case 'z': | |
13290 | case 'Z': | |
13291 | case '0': | |
13292 | case 'S': | |
13293 | case 'R': | |
13294 | case 'X': | |
13295 | case 'Y': | |
707bfff6 TS |
13296 | s_reset = s; |
13297 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) | |
252b5132 | 13298 | { |
707bfff6 | 13299 | if (c == 'v' || c == 'w') |
85b51719 | 13300 | { |
707bfff6 | 13301 | if (c == 'v') |
a9e24354 | 13302 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
707bfff6 | 13303 | else |
a9e24354 | 13304 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
707bfff6 TS |
13305 | ++args; |
13306 | continue; | |
85b51719 | 13307 | } |
707bfff6 | 13308 | break; |
252b5132 RH |
13309 | } |
13310 | ||
13311 | if (*s == ' ') | |
13312 | ++s; | |
13313 | if (args[1] != *s) | |
13314 | { | |
13315 | if (c == 'v' || c == 'w') | |
13316 | { | |
13317 | regno = mips16_to_32_reg_map[lastregno]; | |
13318 | s = s_reset; | |
f9419b05 | 13319 | ++args; |
252b5132 RH |
13320 | } |
13321 | } | |
13322 | ||
13323 | switch (c) | |
13324 | { | |
13325 | case 'x': | |
13326 | case 'y': | |
13327 | case 'z': | |
13328 | case 'v': | |
13329 | case 'w': | |
13330 | case 'Z': | |
13331 | regno = mips32_to_16_reg_map[regno]; | |
13332 | break; | |
13333 | ||
13334 | case '0': | |
13335 | if (regno != 0) | |
13336 | regno = ILLEGAL_REG; | |
13337 | break; | |
13338 | ||
13339 | case 'S': | |
13340 | if (regno != SP) | |
13341 | regno = ILLEGAL_REG; | |
13342 | break; | |
13343 | ||
13344 | case 'R': | |
13345 | if (regno != RA) | |
13346 | regno = ILLEGAL_REG; | |
13347 | break; | |
13348 | ||
13349 | case 'X': | |
13350 | case 'Y': | |
741fe287 MR |
13351 | if (regno == AT && mips_opts.at) |
13352 | { | |
13353 | if (mips_opts.at == ATREG) | |
13354 | as_warn (_("used $at without \".set noat\"")); | |
13355 | else | |
13356 | as_warn (_("used $%u with \".set at=$%u\""), | |
13357 | regno, mips_opts.at); | |
13358 | } | |
252b5132 RH |
13359 | break; |
13360 | ||
13361 | default: | |
13362 | internalError (); | |
13363 | } | |
13364 | ||
13365 | if (regno == ILLEGAL_REG) | |
13366 | break; | |
13367 | ||
13368 | switch (c) | |
13369 | { | |
13370 | case 'x': | |
13371 | case 'v': | |
bf12938e | 13372 | MIPS16_INSERT_OPERAND (RX, *ip, regno); |
252b5132 RH |
13373 | break; |
13374 | case 'y': | |
13375 | case 'w': | |
bf12938e | 13376 | MIPS16_INSERT_OPERAND (RY, *ip, regno); |
252b5132 RH |
13377 | break; |
13378 | case 'z': | |
bf12938e | 13379 | MIPS16_INSERT_OPERAND (RZ, *ip, regno); |
252b5132 RH |
13380 | break; |
13381 | case 'Z': | |
bf12938e | 13382 | MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno); |
252b5132 RH |
13383 | case '0': |
13384 | case 'S': | |
13385 | case 'R': | |
13386 | break; | |
13387 | case 'X': | |
bf12938e | 13388 | MIPS16_INSERT_OPERAND (REGR32, *ip, regno); |
252b5132 RH |
13389 | break; |
13390 | case 'Y': | |
13391 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
bf12938e | 13392 | MIPS16_INSERT_OPERAND (REG32R, *ip, regno); |
252b5132 RH |
13393 | break; |
13394 | default: | |
13395 | internalError (); | |
13396 | } | |
13397 | ||
13398 | lastregno = regno; | |
13399 | continue; | |
13400 | ||
13401 | case 'P': | |
13402 | if (strncmp (s, "$pc", 3) == 0) | |
13403 | { | |
13404 | s += 3; | |
13405 | continue; | |
13406 | } | |
13407 | break; | |
13408 | ||
252b5132 RH |
13409 | case '5': |
13410 | case 'H': | |
13411 | case 'W': | |
13412 | case 'D': | |
13413 | case 'j': | |
252b5132 RH |
13414 | case 'V': |
13415 | case 'C': | |
13416 | case 'U': | |
13417 | case 'k': | |
13418 | case 'K': | |
d6f16593 MR |
13419 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); |
13420 | if (i > 0) | |
252b5132 | 13421 | { |
d6f16593 | 13422 | if (imm_expr.X_op != O_constant) |
252b5132 | 13423 | { |
df58fc94 | 13424 | forced_insn_length = 4; |
b34976b6 | 13425 | ip->use_extend = TRUE; |
252b5132 | 13426 | ip->extend = 0; |
252b5132 | 13427 | } |
d6f16593 MR |
13428 | else |
13429 | { | |
13430 | /* We need to relax this instruction. */ | |
13431 | *offset_reloc = *imm_reloc; | |
13432 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
13433 | } | |
13434 | s = expr_end; | |
13435 | continue; | |
252b5132 | 13436 | } |
d6f16593 MR |
13437 | *imm_reloc = BFD_RELOC_UNUSED; |
13438 | /* Fall through. */ | |
13439 | case '<': | |
13440 | case '>': | |
13441 | case '[': | |
13442 | case ']': | |
13443 | case '4': | |
13444 | case '8': | |
13445 | my_getExpression (&imm_expr, s); | |
252b5132 RH |
13446 | if (imm_expr.X_op == O_register) |
13447 | { | |
13448 | /* What we thought was an expression turned out to | |
13449 | be a register. */ | |
13450 | ||
13451 | if (s[0] == '(' && args[1] == '(') | |
13452 | { | |
13453 | /* It looks like the expression was omitted | |
13454 | before a register indirection, which means | |
13455 | that the expression is implicitly zero. We | |
13456 | still set up imm_expr, so that we handle | |
13457 | explicit extensions correctly. */ | |
13458 | imm_expr.X_op = O_constant; | |
13459 | imm_expr.X_add_number = 0; | |
f6688943 | 13460 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
13461 | continue; |
13462 | } | |
13463 | ||
13464 | break; | |
13465 | } | |
13466 | ||
13467 | /* We need to relax this instruction. */ | |
f6688943 | 13468 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
13469 | s = expr_end; |
13470 | continue; | |
13471 | ||
13472 | case 'p': | |
13473 | case 'q': | |
13474 | case 'A': | |
13475 | case 'B': | |
13476 | case 'E': | |
13477 | /* We use offset_reloc rather than imm_reloc for the PC | |
13478 | relative operands. This lets macros with both | |
13479 | immediate and address operands work correctly. */ | |
13480 | my_getExpression (&offset_expr, s); | |
13481 | ||
13482 | if (offset_expr.X_op == O_register) | |
13483 | break; | |
13484 | ||
13485 | /* We need to relax this instruction. */ | |
f6688943 | 13486 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
13487 | s = expr_end; |
13488 | continue; | |
13489 | ||
13490 | case '6': /* break code */ | |
13491 | my_getExpression (&imm_expr, s); | |
13492 | check_absolute_expr (ip, &imm_expr); | |
13493 | if ((unsigned long) imm_expr.X_add_number > 63) | |
bf12938e RS |
13494 | as_warn (_("Invalid value for `%s' (%lu)"), |
13495 | ip->insn_mo->name, | |
13496 | (unsigned long) imm_expr.X_add_number); | |
13497 | MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number); | |
252b5132 RH |
13498 | imm_expr.X_op = O_absent; |
13499 | s = expr_end; | |
13500 | continue; | |
13501 | ||
13502 | case 'a': /* 26 bit address */ | |
13503 | my_getExpression (&offset_expr, s); | |
13504 | s = expr_end; | |
f6688943 | 13505 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
13506 | ip->insn_opcode <<= 16; |
13507 | continue; | |
13508 | ||
13509 | case 'l': /* register list for entry macro */ | |
13510 | case 'L': /* register list for exit macro */ | |
13511 | { | |
13512 | int mask; | |
13513 | ||
13514 | if (c == 'l') | |
13515 | mask = 0; | |
13516 | else | |
13517 | mask = 7 << 3; | |
13518 | while (*s != '\0') | |
13519 | { | |
707bfff6 | 13520 | unsigned int freg, reg1, reg2; |
252b5132 RH |
13521 | |
13522 | while (*s == ' ' || *s == ',') | |
13523 | ++s; | |
707bfff6 | 13524 | if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
252b5132 | 13525 | freg = 0; |
707bfff6 TS |
13526 | else if (reg_lookup (&s, RTYPE_FPU, ®1)) |
13527 | freg = 1; | |
252b5132 RH |
13528 | else |
13529 | { | |
707bfff6 TS |
13530 | as_bad (_("can't parse register list")); |
13531 | break; | |
252b5132 RH |
13532 | } |
13533 | if (*s == ' ') | |
13534 | ++s; | |
13535 | if (*s != '-') | |
13536 | reg2 = reg1; | |
13537 | else | |
13538 | { | |
13539 | ++s; | |
707bfff6 TS |
13540 | if (!reg_lookup (&s, freg ? RTYPE_FPU |
13541 | : (RTYPE_GP | RTYPE_NUM), ®2)) | |
252b5132 | 13542 | { |
707bfff6 TS |
13543 | as_bad (_("invalid register list")); |
13544 | break; | |
252b5132 RH |
13545 | } |
13546 | } | |
13547 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
13548 | { | |
13549 | mask &= ~ (7 << 3); | |
13550 | mask |= 5 << 3; | |
13551 | } | |
13552 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
13553 | { | |
13554 | mask &= ~ (7 << 3); | |
13555 | mask |= 6 << 3; | |
13556 | } | |
13557 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
13558 | mask |= (reg2 - 3) << 3; | |
13559 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
13560 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 13561 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
13562 | mask |= 1; |
13563 | else | |
13564 | { | |
13565 | as_bad (_("invalid register list")); | |
13566 | break; | |
13567 | } | |
13568 | } | |
13569 | /* The mask is filled in in the opcode table for the | |
13570 | benefit of the disassembler. We remove it before | |
13571 | applying the actual mask. */ | |
13572 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
13573 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
13574 | } | |
13575 | continue; | |
13576 | ||
0499d65b TS |
13577 | case 'm': /* Register list for save insn. */ |
13578 | case 'M': /* Register list for restore insn. */ | |
13579 | { | |
13580 | int opcode = 0; | |
13581 | int framesz = 0, seen_framesz = 0; | |
91d6fa6a | 13582 | int nargs = 0, statics = 0, sregs = 0; |
0499d65b TS |
13583 | |
13584 | while (*s != '\0') | |
13585 | { | |
13586 | unsigned int reg1, reg2; | |
13587 | ||
13588 | SKIP_SPACE_TABS (s); | |
13589 | while (*s == ',') | |
13590 | ++s; | |
13591 | SKIP_SPACE_TABS (s); | |
13592 | ||
13593 | my_getExpression (&imm_expr, s); | |
13594 | if (imm_expr.X_op == O_constant) | |
13595 | { | |
13596 | /* Handle the frame size. */ | |
13597 | if (seen_framesz) | |
13598 | { | |
13599 | as_bad (_("more than one frame size in list")); | |
13600 | break; | |
13601 | } | |
13602 | seen_framesz = 1; | |
13603 | framesz = imm_expr.X_add_number; | |
13604 | imm_expr.X_op = O_absent; | |
13605 | s = expr_end; | |
13606 | continue; | |
13607 | } | |
13608 | ||
707bfff6 | 13609 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
0499d65b TS |
13610 | { |
13611 | as_bad (_("can't parse register list")); | |
13612 | break; | |
13613 | } | |
0499d65b | 13614 | |
707bfff6 TS |
13615 | while (*s == ' ') |
13616 | ++s; | |
13617 | ||
0499d65b TS |
13618 | if (*s != '-') |
13619 | reg2 = reg1; | |
13620 | else | |
13621 | { | |
13622 | ++s; | |
707bfff6 TS |
13623 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2) |
13624 | || reg2 < reg1) | |
0499d65b TS |
13625 | { |
13626 | as_bad (_("can't parse register list")); | |
13627 | break; | |
13628 | } | |
0499d65b TS |
13629 | } |
13630 | ||
13631 | while (reg1 <= reg2) | |
13632 | { | |
13633 | if (reg1 >= 4 && reg1 <= 7) | |
13634 | { | |
3a93f742 | 13635 | if (!seen_framesz) |
0499d65b | 13636 | /* args $a0-$a3 */ |
91d6fa6a | 13637 | nargs |= 1 << (reg1 - 4); |
0499d65b TS |
13638 | else |
13639 | /* statics $a0-$a3 */ | |
13640 | statics |= 1 << (reg1 - 4); | |
13641 | } | |
13642 | else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30) | |
13643 | { | |
13644 | /* $s0-$s8 */ | |
13645 | sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16)); | |
13646 | } | |
13647 | else if (reg1 == 31) | |
13648 | { | |
13649 | /* Add $ra to insn. */ | |
13650 | opcode |= 0x40; | |
13651 | } | |
13652 | else | |
13653 | { | |
13654 | as_bad (_("unexpected register in list")); | |
13655 | break; | |
13656 | } | |
13657 | if (++reg1 == 24) | |
13658 | reg1 = 30; | |
13659 | } | |
13660 | } | |
13661 | ||
13662 | /* Encode args/statics combination. */ | |
91d6fa6a | 13663 | if (nargs & statics) |
0499d65b | 13664 | as_bad (_("arg/static registers overlap")); |
91d6fa6a | 13665 | else if (nargs == 0xf) |
0499d65b TS |
13666 | /* All $a0-$a3 are args. */ |
13667 | opcode |= MIPS16_ALL_ARGS << 16; | |
13668 | else if (statics == 0xf) | |
13669 | /* All $a0-$a3 are statics. */ | |
13670 | opcode |= MIPS16_ALL_STATICS << 16; | |
13671 | else | |
13672 | { | |
13673 | int narg = 0, nstat = 0; | |
13674 | ||
13675 | /* Count arg registers. */ | |
91d6fa6a | 13676 | while (nargs & 0x1) |
0499d65b | 13677 | { |
91d6fa6a | 13678 | nargs >>= 1; |
0499d65b TS |
13679 | narg++; |
13680 | } | |
91d6fa6a | 13681 | if (nargs != 0) |
0499d65b TS |
13682 | as_bad (_("invalid arg register list")); |
13683 | ||
13684 | /* Count static registers. */ | |
13685 | while (statics & 0x8) | |
13686 | { | |
13687 | statics = (statics << 1) & 0xf; | |
13688 | nstat++; | |
13689 | } | |
13690 | if (statics != 0) | |
13691 | as_bad (_("invalid static register list")); | |
13692 | ||
13693 | /* Encode args/statics. */ | |
13694 | opcode |= ((narg << 2) | nstat) << 16; | |
13695 | } | |
13696 | ||
13697 | /* Encode $s0/$s1. */ | |
13698 | if (sregs & (1 << 0)) /* $s0 */ | |
13699 | opcode |= 0x20; | |
13700 | if (sregs & (1 << 1)) /* $s1 */ | |
13701 | opcode |= 0x10; | |
13702 | sregs >>= 2; | |
13703 | ||
13704 | if (sregs != 0) | |
13705 | { | |
13706 | /* Count regs $s2-$s8. */ | |
13707 | int nsreg = 0; | |
13708 | while (sregs & 1) | |
13709 | { | |
13710 | sregs >>= 1; | |
13711 | nsreg++; | |
13712 | } | |
13713 | if (sregs != 0) | |
13714 | as_bad (_("invalid static register list")); | |
13715 | /* Encode $s2-$s8. */ | |
13716 | opcode |= nsreg << 24; | |
13717 | } | |
13718 | ||
13719 | /* Encode frame size. */ | |
13720 | if (!seen_framesz) | |
13721 | as_bad (_("missing frame size")); | |
13722 | else if ((framesz & 7) != 0 || framesz < 0 | |
13723 | || framesz > 0xff * 8) | |
13724 | as_bad (_("invalid frame size")); | |
13725 | else if (framesz != 128 || (opcode >> 16) != 0) | |
13726 | { | |
13727 | framesz /= 8; | |
13728 | opcode |= (((framesz & 0xf0) << 16) | |
13729 | | (framesz & 0x0f)); | |
13730 | } | |
13731 | ||
13732 | /* Finally build the instruction. */ | |
13733 | if ((opcode >> 16) != 0 || framesz == 0) | |
13734 | { | |
13735 | ip->use_extend = TRUE; | |
13736 | ip->extend = opcode >> 16; | |
13737 | } | |
13738 | ip->insn_opcode |= opcode & 0x7f; | |
13739 | } | |
13740 | continue; | |
13741 | ||
252b5132 RH |
13742 | case 'e': /* extend code */ |
13743 | my_getExpression (&imm_expr, s); | |
13744 | check_absolute_expr (ip, &imm_expr); | |
13745 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
13746 | { | |
13747 | as_warn (_("Invalid value for `%s' (%lu)"), | |
13748 | ip->insn_mo->name, | |
13749 | (unsigned long) imm_expr.X_add_number); | |
13750 | imm_expr.X_add_number &= 0x7ff; | |
13751 | } | |
13752 | ip->insn_opcode |= imm_expr.X_add_number; | |
13753 | imm_expr.X_op = O_absent; | |
13754 | s = expr_end; | |
13755 | continue; | |
13756 | ||
13757 | default: | |
13758 | internalError (); | |
13759 | } | |
13760 | break; | |
13761 | } | |
13762 | ||
13763 | /* Args don't match. */ | |
13764 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
13765 | strcmp (insn->name, insn[1].name) == 0) | |
13766 | { | |
13767 | ++insn; | |
13768 | s = argsstart; | |
13769 | continue; | |
13770 | } | |
13771 | ||
13772 | insn_error = _("illegal operands"); | |
13773 | ||
13774 | return; | |
13775 | } | |
13776 | } | |
13777 | ||
13778 | /* This structure holds information we know about a mips16 immediate | |
13779 | argument type. */ | |
13780 | ||
e972090a NC |
13781 | struct mips16_immed_operand |
13782 | { | |
252b5132 RH |
13783 | /* The type code used in the argument string in the opcode table. */ |
13784 | int type; | |
13785 | /* The number of bits in the short form of the opcode. */ | |
13786 | int nbits; | |
13787 | /* The number of bits in the extended form of the opcode. */ | |
13788 | int extbits; | |
13789 | /* The amount by which the short form is shifted when it is used; | |
13790 | for example, the sw instruction has a shift count of 2. */ | |
13791 | int shift; | |
13792 | /* The amount by which the short form is shifted when it is stored | |
13793 | into the instruction code. */ | |
13794 | int op_shift; | |
13795 | /* Non-zero if the short form is unsigned. */ | |
13796 | int unsp; | |
13797 | /* Non-zero if the extended form is unsigned. */ | |
13798 | int extu; | |
13799 | /* Non-zero if the value is PC relative. */ | |
13800 | int pcrel; | |
13801 | }; | |
13802 | ||
13803 | /* The mips16 immediate operand types. */ | |
13804 | ||
13805 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
13806 | { | |
13807 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
13808 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
13809 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
13810 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
13811 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
13812 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
13813 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
13814 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
13815 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
13816 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
13817 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
13818 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
13819 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
13820 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
13821 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
13822 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
13823 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
13824 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
13825 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
13826 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
13827 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
13828 | }; | |
13829 | ||
13830 | #define MIPS16_NUM_IMMED \ | |
13831 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
13832 | ||
13833 | /* Handle a mips16 instruction with an immediate value. This or's the | |
13834 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
13835 | whether an extended value is needed; if one is needed, it sets | |
13836 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
13837 | If SMALL is true, an unextended opcode was explicitly requested. | |
13838 | If EXT is true, an extended opcode was explicitly requested. If | |
13839 | WARN is true, warn if EXT does not match reality. */ | |
13840 | ||
13841 | static void | |
17a2f251 TS |
13842 | mips16_immed (char *file, unsigned int line, int type, offsetT val, |
13843 | bfd_boolean warn, bfd_boolean small, bfd_boolean ext, | |
13844 | unsigned long *insn, bfd_boolean *use_extend, | |
13845 | unsigned short *extend) | |
252b5132 | 13846 | { |
3994f87e | 13847 | const struct mips16_immed_operand *op; |
252b5132 | 13848 | int mintiny, maxtiny; |
b34976b6 | 13849 | bfd_boolean needext; |
252b5132 RH |
13850 | |
13851 | op = mips16_immed_operands; | |
13852 | while (op->type != type) | |
13853 | { | |
13854 | ++op; | |
9c2799c2 | 13855 | gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
252b5132 RH |
13856 | } |
13857 | ||
13858 | if (op->unsp) | |
13859 | { | |
13860 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
13861 | { | |
13862 | mintiny = 1; | |
13863 | maxtiny = 1 << op->nbits; | |
13864 | } | |
13865 | else | |
13866 | { | |
13867 | mintiny = 0; | |
13868 | maxtiny = (1 << op->nbits) - 1; | |
13869 | } | |
13870 | } | |
13871 | else | |
13872 | { | |
13873 | mintiny = - (1 << (op->nbits - 1)); | |
13874 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
13875 | } | |
13876 | ||
13877 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
13878 | if (type == 'p' || type == 'q') | |
13879 | val /= 2; | |
13880 | ||
13881 | if ((val & ((1 << op->shift) - 1)) != 0 | |
13882 | || val < (mintiny << op->shift) | |
13883 | || val > (maxtiny << op->shift)) | |
b34976b6 | 13884 | needext = TRUE; |
252b5132 | 13885 | else |
b34976b6 | 13886 | needext = FALSE; |
252b5132 RH |
13887 | |
13888 | if (warn && ext && ! needext) | |
beae10d5 KH |
13889 | as_warn_where (file, line, |
13890 | _("extended operand requested but not required")); | |
252b5132 RH |
13891 | if (small && needext) |
13892 | as_bad_where (file, line, _("invalid unextended operand value")); | |
13893 | ||
13894 | if (small || (! ext && ! needext)) | |
13895 | { | |
13896 | int insnval; | |
13897 | ||
b34976b6 | 13898 | *use_extend = FALSE; |
252b5132 RH |
13899 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
13900 | insnval <<= op->op_shift; | |
13901 | *insn |= insnval; | |
13902 | } | |
13903 | else | |
13904 | { | |
13905 | long minext, maxext; | |
13906 | int extval; | |
13907 | ||
13908 | if (op->extu) | |
13909 | { | |
13910 | minext = 0; | |
13911 | maxext = (1 << op->extbits) - 1; | |
13912 | } | |
13913 | else | |
13914 | { | |
13915 | minext = - (1 << (op->extbits - 1)); | |
13916 | maxext = (1 << (op->extbits - 1)) - 1; | |
13917 | } | |
13918 | if (val < minext || val > maxext) | |
13919 | as_bad_where (file, line, | |
13920 | _("operand value out of range for instruction")); | |
13921 | ||
b34976b6 | 13922 | *use_extend = TRUE; |
252b5132 RH |
13923 | if (op->extbits == 16) |
13924 | { | |
13925 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
13926 | val &= 0x1f; | |
13927 | } | |
13928 | else if (op->extbits == 15) | |
13929 | { | |
13930 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
13931 | val &= 0xf; | |
13932 | } | |
13933 | else | |
13934 | { | |
13935 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
13936 | val = 0; | |
13937 | } | |
13938 | ||
13939 | *extend = (unsigned short) extval; | |
13940 | *insn |= val; | |
13941 | } | |
13942 | } | |
13943 | \f | |
d6f16593 | 13944 | struct percent_op_match |
ad8d3bb3 | 13945 | { |
5e0116d5 RS |
13946 | const char *str; |
13947 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
13948 | }; |
13949 | ||
13950 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 13951 | { |
5e0116d5 | 13952 | {"%lo", BFD_RELOC_LO16}, |
ad8d3bb3 | 13953 | #ifdef OBJ_ELF |
5e0116d5 RS |
13954 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
13955 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
13956 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
13957 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
13958 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
13959 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
13960 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
13961 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
13962 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
13963 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
13964 | {"%half", BFD_RELOC_16}, | |
13965 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
13966 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
13967 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
13968 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
13969 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
13970 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
13971 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
13972 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
13973 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
13974 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
ad8d3bb3 | 13975 | #endif |
5e0116d5 | 13976 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
13977 | }; |
13978 | ||
d6f16593 MR |
13979 | static const struct percent_op_match mips16_percent_op[] = |
13980 | { | |
13981 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
13982 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, | |
738e5348 RS |
13983 | {"%got", BFD_RELOC_MIPS16_GOT16}, |
13984 | {"%call16", BFD_RELOC_MIPS16_CALL16}, | |
d6f16593 MR |
13985 | {"%hi", BFD_RELOC_MIPS16_HI16_S} |
13986 | }; | |
13987 | ||
252b5132 | 13988 | |
5e0116d5 RS |
13989 | /* Return true if *STR points to a relocation operator. When returning true, |
13990 | move *STR over the operator and store its relocation code in *RELOC. | |
13991 | Leave both *STR and *RELOC alone when returning false. */ | |
13992 | ||
13993 | static bfd_boolean | |
17a2f251 | 13994 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 13995 | { |
d6f16593 MR |
13996 | const struct percent_op_match *percent_op; |
13997 | size_t limit, i; | |
13998 | ||
13999 | if (mips_opts.mips16) | |
14000 | { | |
14001 | percent_op = mips16_percent_op; | |
14002 | limit = ARRAY_SIZE (mips16_percent_op); | |
14003 | } | |
14004 | else | |
14005 | { | |
14006 | percent_op = mips_percent_op; | |
14007 | limit = ARRAY_SIZE (mips_percent_op); | |
14008 | } | |
76b3015f | 14009 | |
d6f16593 | 14010 | for (i = 0; i < limit; i++) |
5e0116d5 | 14011 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 14012 | { |
3f98094e DJ |
14013 | int len = strlen (percent_op[i].str); |
14014 | ||
14015 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
14016 | continue; | |
14017 | ||
5e0116d5 RS |
14018 | *str += strlen (percent_op[i].str); |
14019 | *reloc = percent_op[i].reloc; | |
394f9b3a | 14020 | |
5e0116d5 RS |
14021 | /* Check whether the output BFD supports this relocation. |
14022 | If not, issue an error and fall back on something safe. */ | |
14023 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 14024 | { |
20203fb9 | 14025 | as_bad (_("relocation %s isn't supported by the current ABI"), |
5e0116d5 | 14026 | percent_op[i].str); |
01a3f561 | 14027 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 14028 | } |
5e0116d5 | 14029 | return TRUE; |
394f9b3a | 14030 | } |
5e0116d5 | 14031 | return FALSE; |
394f9b3a | 14032 | } |
ad8d3bb3 | 14033 | |
ad8d3bb3 | 14034 | |
5e0116d5 RS |
14035 | /* Parse string STR as a 16-bit relocatable operand. Store the |
14036 | expression in *EP and the relocations in the array starting | |
14037 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 14038 | |
01a3f561 | 14039 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 14040 | |
5e0116d5 | 14041 | static size_t |
17a2f251 TS |
14042 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
14043 | char *str) | |
ad8d3bb3 | 14044 | { |
5e0116d5 RS |
14045 | bfd_reloc_code_real_type reversed_reloc[3]; |
14046 | size_t reloc_index, i; | |
09b8f35a RS |
14047 | int crux_depth, str_depth; |
14048 | char *crux; | |
5e0116d5 RS |
14049 | |
14050 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
14051 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
14052 | of the main expression and with CRUX_DEPTH containing the number | |
14053 | of open brackets at that point. */ | |
14054 | reloc_index = -1; | |
14055 | str_depth = 0; | |
14056 | do | |
fb1b3232 | 14057 | { |
09b8f35a RS |
14058 | reloc_index++; |
14059 | crux = str; | |
14060 | crux_depth = str_depth; | |
14061 | ||
14062 | /* Skip over whitespace and brackets, keeping count of the number | |
14063 | of brackets. */ | |
14064 | while (*str == ' ' || *str == '\t' || *str == '(') | |
14065 | if (*str++ == '(') | |
14066 | str_depth++; | |
5e0116d5 | 14067 | } |
09b8f35a RS |
14068 | while (*str == '%' |
14069 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
14070 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 14071 | |
09b8f35a | 14072 | my_getExpression (ep, crux); |
5e0116d5 | 14073 | str = expr_end; |
394f9b3a | 14074 | |
5e0116d5 | 14075 | /* Match every open bracket. */ |
09b8f35a | 14076 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 14077 | if (*str++ == ')') |
09b8f35a | 14078 | crux_depth--; |
394f9b3a | 14079 | |
09b8f35a | 14080 | if (crux_depth > 0) |
20203fb9 | 14081 | as_bad (_("unclosed '('")); |
394f9b3a | 14082 | |
5e0116d5 | 14083 | expr_end = str; |
252b5132 | 14084 | |
01a3f561 | 14085 | if (reloc_index != 0) |
64bdfcaf RS |
14086 | { |
14087 | prev_reloc_op_frag = frag_now; | |
14088 | for (i = 0; i < reloc_index; i++) | |
14089 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
14090 | } | |
fb1b3232 | 14091 | |
5e0116d5 | 14092 | return reloc_index; |
252b5132 RH |
14093 | } |
14094 | ||
14095 | static void | |
17a2f251 | 14096 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
14097 | { |
14098 | char *save_in; | |
14099 | ||
14100 | save_in = input_line_pointer; | |
14101 | input_line_pointer = str; | |
14102 | expression (ep); | |
14103 | expr_end = input_line_pointer; | |
14104 | input_line_pointer = save_in; | |
252b5132 RH |
14105 | } |
14106 | ||
252b5132 | 14107 | char * |
17a2f251 | 14108 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 14109 | { |
499ac353 | 14110 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
252b5132 RH |
14111 | } |
14112 | ||
14113 | void | |
17a2f251 | 14114 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
14115 | { |
14116 | if (target_big_endian) | |
14117 | number_to_chars_bigendian (buf, val, n); | |
14118 | else | |
14119 | number_to_chars_littleendian (buf, val, n); | |
14120 | } | |
14121 | \f | |
ae948b86 | 14122 | #ifdef OBJ_ELF |
e013f690 TS |
14123 | static int support_64bit_objects(void) |
14124 | { | |
14125 | const char **list, **l; | |
aa3d8fdf | 14126 | int yes; |
e013f690 TS |
14127 | |
14128 | list = bfd_target_list (); | |
14129 | for (l = list; *l != NULL; l++) | |
aeffff67 RS |
14130 | if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0 |
14131 | || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0) | |
e013f690 | 14132 | break; |
aa3d8fdf | 14133 | yes = (*l != NULL); |
e013f690 | 14134 | free (list); |
aa3d8fdf | 14135 | return yes; |
e013f690 | 14136 | } |
ae948b86 | 14137 | #endif /* OBJ_ELF */ |
e013f690 | 14138 | |
78849248 | 14139 | const char *md_shortopts = "O::g::G:"; |
252b5132 | 14140 | |
23fce1e3 NC |
14141 | enum options |
14142 | { | |
14143 | OPTION_MARCH = OPTION_MD_BASE, | |
14144 | OPTION_MTUNE, | |
14145 | OPTION_MIPS1, | |
14146 | OPTION_MIPS2, | |
14147 | OPTION_MIPS3, | |
14148 | OPTION_MIPS4, | |
14149 | OPTION_MIPS5, | |
14150 | OPTION_MIPS32, | |
14151 | OPTION_MIPS64, | |
14152 | OPTION_MIPS32R2, | |
14153 | OPTION_MIPS64R2, | |
14154 | OPTION_MIPS16, | |
14155 | OPTION_NO_MIPS16, | |
14156 | OPTION_MIPS3D, | |
14157 | OPTION_NO_MIPS3D, | |
14158 | OPTION_MDMX, | |
14159 | OPTION_NO_MDMX, | |
14160 | OPTION_DSP, | |
14161 | OPTION_NO_DSP, | |
14162 | OPTION_MT, | |
14163 | OPTION_NO_MT, | |
14164 | OPTION_SMARTMIPS, | |
14165 | OPTION_NO_SMARTMIPS, | |
14166 | OPTION_DSPR2, | |
14167 | OPTION_NO_DSPR2, | |
df58fc94 RS |
14168 | OPTION_MICROMIPS, |
14169 | OPTION_NO_MICROMIPS, | |
23fce1e3 NC |
14170 | OPTION_COMPAT_ARCH_BASE, |
14171 | OPTION_M4650, | |
14172 | OPTION_NO_M4650, | |
14173 | OPTION_M4010, | |
14174 | OPTION_NO_M4010, | |
14175 | OPTION_M4100, | |
14176 | OPTION_NO_M4100, | |
14177 | OPTION_M3900, | |
14178 | OPTION_NO_M3900, | |
14179 | OPTION_M7000_HILO_FIX, | |
6a32d874 CM |
14180 | OPTION_MNO_7000_HILO_FIX, |
14181 | OPTION_FIX_24K, | |
14182 | OPTION_NO_FIX_24K, | |
c67a084a NC |
14183 | OPTION_FIX_LOONGSON2F_JUMP, |
14184 | OPTION_NO_FIX_LOONGSON2F_JUMP, | |
14185 | OPTION_FIX_LOONGSON2F_NOP, | |
14186 | OPTION_NO_FIX_LOONGSON2F_NOP, | |
23fce1e3 NC |
14187 | OPTION_FIX_VR4120, |
14188 | OPTION_NO_FIX_VR4120, | |
14189 | OPTION_FIX_VR4130, | |
14190 | OPTION_NO_FIX_VR4130, | |
d954098f DD |
14191 | OPTION_FIX_CN63XXP1, |
14192 | OPTION_NO_FIX_CN63XXP1, | |
23fce1e3 NC |
14193 | OPTION_TRAP, |
14194 | OPTION_BREAK, | |
14195 | OPTION_EB, | |
14196 | OPTION_EL, | |
14197 | OPTION_FP32, | |
14198 | OPTION_GP32, | |
14199 | OPTION_CONSTRUCT_FLOATS, | |
14200 | OPTION_NO_CONSTRUCT_FLOATS, | |
14201 | OPTION_FP64, | |
14202 | OPTION_GP64, | |
14203 | OPTION_RELAX_BRANCH, | |
14204 | OPTION_NO_RELAX_BRANCH, | |
14205 | OPTION_MSHARED, | |
14206 | OPTION_MNO_SHARED, | |
14207 | OPTION_MSYM32, | |
14208 | OPTION_MNO_SYM32, | |
14209 | OPTION_SOFT_FLOAT, | |
14210 | OPTION_HARD_FLOAT, | |
14211 | OPTION_SINGLE_FLOAT, | |
14212 | OPTION_DOUBLE_FLOAT, | |
14213 | OPTION_32, | |
14214 | #ifdef OBJ_ELF | |
14215 | OPTION_CALL_SHARED, | |
14216 | OPTION_CALL_NONPIC, | |
14217 | OPTION_NON_SHARED, | |
14218 | OPTION_XGOT, | |
14219 | OPTION_MABI, | |
14220 | OPTION_N32, | |
14221 | OPTION_64, | |
14222 | OPTION_MDEBUG, | |
14223 | OPTION_NO_MDEBUG, | |
14224 | OPTION_PDR, | |
14225 | OPTION_NO_PDR, | |
14226 | OPTION_MVXWORKS_PIC, | |
14227 | #endif /* OBJ_ELF */ | |
14228 | OPTION_END_OF_ENUM | |
14229 | }; | |
14230 | ||
e972090a NC |
14231 | struct option md_longopts[] = |
14232 | { | |
f9b4148d | 14233 | /* Options which specify architecture. */ |
f9b4148d | 14234 | {"march", required_argument, NULL, OPTION_MARCH}, |
f9b4148d | 14235 | {"mtune", required_argument, NULL, OPTION_MTUNE}, |
252b5132 RH |
14236 | {"mips0", no_argument, NULL, OPTION_MIPS1}, |
14237 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
252b5132 | 14238 | {"mips2", no_argument, NULL, OPTION_MIPS2}, |
252b5132 | 14239 | {"mips3", no_argument, NULL, OPTION_MIPS3}, |
252b5132 | 14240 | {"mips4", no_argument, NULL, OPTION_MIPS4}, |
ae948b86 | 14241 | {"mips5", no_argument, NULL, OPTION_MIPS5}, |
ae948b86 | 14242 | {"mips32", no_argument, NULL, OPTION_MIPS32}, |
ae948b86 | 14243 | {"mips64", no_argument, NULL, OPTION_MIPS64}, |
f9b4148d | 14244 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, |
5f74bc13 | 14245 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, |
f9b4148d CD |
14246 | |
14247 | /* Options which specify Application Specific Extensions (ASEs). */ | |
f9b4148d | 14248 | {"mips16", no_argument, NULL, OPTION_MIPS16}, |
f9b4148d | 14249 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, |
f9b4148d | 14250 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, |
f9b4148d | 14251 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, |
f9b4148d | 14252 | {"mdmx", no_argument, NULL, OPTION_MDMX}, |
f9b4148d | 14253 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, |
74cd071d | 14254 | {"mdsp", no_argument, NULL, OPTION_DSP}, |
74cd071d | 14255 | {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, |
ef2e4d86 | 14256 | {"mmt", no_argument, NULL, OPTION_MT}, |
ef2e4d86 | 14257 | {"mno-mt", no_argument, NULL, OPTION_NO_MT}, |
e16bfa71 | 14258 | {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS}, |
e16bfa71 | 14259 | {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS}, |
8b082fb1 | 14260 | {"mdspr2", no_argument, NULL, OPTION_DSPR2}, |
8b082fb1 | 14261 | {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2}, |
df58fc94 RS |
14262 | {"mmicromips", no_argument, NULL, OPTION_MICROMIPS}, |
14263 | {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS}, | |
f9b4148d CD |
14264 | |
14265 | /* Old-style architecture options. Don't add more of these. */ | |
f9b4148d | 14266 | {"m4650", no_argument, NULL, OPTION_M4650}, |
f9b4148d | 14267 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, |
f9b4148d | 14268 | {"m4010", no_argument, NULL, OPTION_M4010}, |
f9b4148d | 14269 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, |
f9b4148d | 14270 | {"m4100", no_argument, NULL, OPTION_M4100}, |
f9b4148d | 14271 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, |
f9b4148d | 14272 | {"m3900", no_argument, NULL, OPTION_M3900}, |
f9b4148d CD |
14273 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, |
14274 | ||
14275 | /* Options which enable bug fixes. */ | |
f9b4148d | 14276 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, |
f9b4148d CD |
14277 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, |
14278 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
c67a084a NC |
14279 | {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP}, |
14280 | {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP}, | |
14281 | {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP}, | |
14282 | {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP}, | |
d766e8ec RS |
14283 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, |
14284 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
7d8e00cf RS |
14285 | {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, |
14286 | {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, | |
6a32d874 CM |
14287 | {"mfix-24k", no_argument, NULL, OPTION_FIX_24K}, |
14288 | {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K}, | |
d954098f DD |
14289 | {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1}, |
14290 | {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1}, | |
f9b4148d CD |
14291 | |
14292 | /* Miscellaneous options. */ | |
252b5132 RH |
14293 | {"trap", no_argument, NULL, OPTION_TRAP}, |
14294 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
252b5132 RH |
14295 | {"break", no_argument, NULL, OPTION_BREAK}, |
14296 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
252b5132 | 14297 | {"EB", no_argument, NULL, OPTION_EB}, |
252b5132 | 14298 | {"EL", no_argument, NULL, OPTION_EL}, |
ae948b86 | 14299 | {"mfp32", no_argument, NULL, OPTION_FP32}, |
c97ef257 | 14300 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
119d663a | 14301 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
119d663a | 14302 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
316f5878 | 14303 | {"mfp64", no_argument, NULL, OPTION_FP64}, |
ae948b86 | 14304 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
4a6a3df4 AO |
14305 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, |
14306 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
aa6975fb ILT |
14307 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
14308 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
aed1a261 RS |
14309 | {"msym32", no_argument, NULL, OPTION_MSYM32}, |
14310 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, | |
037b32b9 AN |
14311 | {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT}, |
14312 | {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT}, | |
037b32b9 AN |
14313 | {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT}, |
14314 | {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT}, | |
23fce1e3 NC |
14315 | |
14316 | /* Strictly speaking this next option is ELF specific, | |
14317 | but we allow it for other ports as well in order to | |
14318 | make testing easier. */ | |
14319 | {"32", no_argument, NULL, OPTION_32}, | |
037b32b9 | 14320 | |
f9b4148d | 14321 | /* ELF-specific options. */ |
156c2f8b | 14322 | #ifdef OBJ_ELF |
156c2f8b NC |
14323 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
14324 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
861fb55a | 14325 | {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC}, |
156c2f8b NC |
14326 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
14327 | {"xgot", no_argument, NULL, OPTION_XGOT}, | |
ae948b86 | 14328 | {"mabi", required_argument, NULL, OPTION_MABI}, |
e013f690 | 14329 | {"n32", no_argument, NULL, OPTION_N32}, |
156c2f8b | 14330 | {"64", no_argument, NULL, OPTION_64}, |
ecb4347a | 14331 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, |
ecb4347a | 14332 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, |
dcd410fe | 14333 | {"mpdr", no_argument, NULL, OPTION_PDR}, |
dcd410fe | 14334 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, |
0a44bf69 | 14335 | {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, |
ae948b86 | 14336 | #endif /* OBJ_ELF */ |
f9b4148d | 14337 | |
252b5132 RH |
14338 | {NULL, no_argument, NULL, 0} |
14339 | }; | |
156c2f8b | 14340 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 14341 | |
316f5878 RS |
14342 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
14343 | NEW_VALUE. Warn if another value was already specified. Note: | |
14344 | we have to defer parsing the -march and -mtune arguments in order | |
14345 | to handle 'from-abi' correctly, since the ABI might be specified | |
14346 | in a later argument. */ | |
14347 | ||
14348 | static void | |
17a2f251 | 14349 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
14350 | { |
14351 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
14352 | as_warn (_("A different %s was already specified, is now %s"), | |
14353 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
14354 | new_value); | |
14355 | ||
14356 | *string_ptr = new_value; | |
14357 | } | |
14358 | ||
252b5132 | 14359 | int |
17a2f251 | 14360 | md_parse_option (int c, char *arg) |
252b5132 RH |
14361 | { |
14362 | switch (c) | |
14363 | { | |
119d663a NC |
14364 | case OPTION_CONSTRUCT_FLOATS: |
14365 | mips_disable_float_construction = 0; | |
14366 | break; | |
bdaaa2e1 | 14367 | |
119d663a NC |
14368 | case OPTION_NO_CONSTRUCT_FLOATS: |
14369 | mips_disable_float_construction = 1; | |
14370 | break; | |
bdaaa2e1 | 14371 | |
252b5132 RH |
14372 | case OPTION_TRAP: |
14373 | mips_trap = 1; | |
14374 | break; | |
14375 | ||
14376 | case OPTION_BREAK: | |
14377 | mips_trap = 0; | |
14378 | break; | |
14379 | ||
14380 | case OPTION_EB: | |
14381 | target_big_endian = 1; | |
14382 | break; | |
14383 | ||
14384 | case OPTION_EL: | |
14385 | target_big_endian = 0; | |
14386 | break; | |
14387 | ||
14388 | case 'O': | |
4ffff32f TS |
14389 | if (arg == NULL) |
14390 | mips_optimize = 1; | |
14391 | else if (arg[0] == '0') | |
14392 | mips_optimize = 0; | |
14393 | else if (arg[0] == '1') | |
252b5132 RH |
14394 | mips_optimize = 1; |
14395 | else | |
14396 | mips_optimize = 2; | |
14397 | break; | |
14398 | ||
14399 | case 'g': | |
14400 | if (arg == NULL) | |
14401 | mips_debug = 2; | |
14402 | else | |
14403 | mips_debug = atoi (arg); | |
252b5132 RH |
14404 | break; |
14405 | ||
14406 | case OPTION_MIPS1: | |
316f5878 | 14407 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
14408 | break; |
14409 | ||
14410 | case OPTION_MIPS2: | |
316f5878 | 14411 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
14412 | break; |
14413 | ||
14414 | case OPTION_MIPS3: | |
316f5878 | 14415 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
14416 | break; |
14417 | ||
14418 | case OPTION_MIPS4: | |
316f5878 | 14419 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
14420 | break; |
14421 | ||
84ea6cf2 | 14422 | case OPTION_MIPS5: |
316f5878 | 14423 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
14424 | break; |
14425 | ||
e7af610e | 14426 | case OPTION_MIPS32: |
316f5878 | 14427 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
14428 | break; |
14429 | ||
af7ee8bf CD |
14430 | case OPTION_MIPS32R2: |
14431 | file_mips_isa = ISA_MIPS32R2; | |
14432 | break; | |
14433 | ||
5f74bc13 CD |
14434 | case OPTION_MIPS64R2: |
14435 | file_mips_isa = ISA_MIPS64R2; | |
14436 | break; | |
14437 | ||
84ea6cf2 | 14438 | case OPTION_MIPS64: |
316f5878 | 14439 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
14440 | break; |
14441 | ||
ec68c924 | 14442 | case OPTION_MTUNE: |
316f5878 RS |
14443 | mips_set_option_string (&mips_tune_string, arg); |
14444 | break; | |
ec68c924 | 14445 | |
316f5878 RS |
14446 | case OPTION_MARCH: |
14447 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
14448 | break; |
14449 | ||
14450 | case OPTION_M4650: | |
316f5878 RS |
14451 | mips_set_option_string (&mips_arch_string, "4650"); |
14452 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
14453 | break; |
14454 | ||
14455 | case OPTION_NO_M4650: | |
14456 | break; | |
14457 | ||
14458 | case OPTION_M4010: | |
316f5878 RS |
14459 | mips_set_option_string (&mips_arch_string, "4010"); |
14460 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
14461 | break; |
14462 | ||
14463 | case OPTION_NO_M4010: | |
14464 | break; | |
14465 | ||
14466 | case OPTION_M4100: | |
316f5878 RS |
14467 | mips_set_option_string (&mips_arch_string, "4100"); |
14468 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
14469 | break; |
14470 | ||
14471 | case OPTION_NO_M4100: | |
14472 | break; | |
14473 | ||
252b5132 | 14474 | case OPTION_M3900: |
316f5878 RS |
14475 | mips_set_option_string (&mips_arch_string, "3900"); |
14476 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 14477 | break; |
bdaaa2e1 | 14478 | |
252b5132 RH |
14479 | case OPTION_NO_M3900: |
14480 | break; | |
14481 | ||
deec1734 CD |
14482 | case OPTION_MDMX: |
14483 | mips_opts.ase_mdmx = 1; | |
14484 | break; | |
14485 | ||
14486 | case OPTION_NO_MDMX: | |
14487 | mips_opts.ase_mdmx = 0; | |
14488 | break; | |
14489 | ||
74cd071d CF |
14490 | case OPTION_DSP: |
14491 | mips_opts.ase_dsp = 1; | |
8b082fb1 | 14492 | mips_opts.ase_dspr2 = 0; |
74cd071d CF |
14493 | break; |
14494 | ||
14495 | case OPTION_NO_DSP: | |
8b082fb1 TS |
14496 | mips_opts.ase_dsp = 0; |
14497 | mips_opts.ase_dspr2 = 0; | |
14498 | break; | |
14499 | ||
14500 | case OPTION_DSPR2: | |
14501 | mips_opts.ase_dspr2 = 1; | |
14502 | mips_opts.ase_dsp = 1; | |
14503 | break; | |
14504 | ||
14505 | case OPTION_NO_DSPR2: | |
14506 | mips_opts.ase_dspr2 = 0; | |
74cd071d CF |
14507 | mips_opts.ase_dsp = 0; |
14508 | break; | |
14509 | ||
ef2e4d86 CF |
14510 | case OPTION_MT: |
14511 | mips_opts.ase_mt = 1; | |
14512 | break; | |
14513 | ||
14514 | case OPTION_NO_MT: | |
14515 | mips_opts.ase_mt = 0; | |
14516 | break; | |
14517 | ||
df58fc94 RS |
14518 | case OPTION_MICROMIPS: |
14519 | if (mips_opts.mips16 == 1) | |
14520 | { | |
14521 | as_bad (_("-mmicromips cannot be used with -mips16")); | |
14522 | return 0; | |
14523 | } | |
14524 | mips_opts.micromips = 1; | |
14525 | mips_no_prev_insn (); | |
14526 | break; | |
14527 | ||
14528 | case OPTION_NO_MICROMIPS: | |
14529 | mips_opts.micromips = 0; | |
14530 | mips_no_prev_insn (); | |
14531 | break; | |
14532 | ||
252b5132 | 14533 | case OPTION_MIPS16: |
df58fc94 RS |
14534 | if (mips_opts.micromips == 1) |
14535 | { | |
14536 | as_bad (_("-mips16 cannot be used with -micromips")); | |
14537 | return 0; | |
14538 | } | |
252b5132 | 14539 | mips_opts.mips16 = 1; |
7d10b47d | 14540 | mips_no_prev_insn (); |
252b5132 RH |
14541 | break; |
14542 | ||
14543 | case OPTION_NO_MIPS16: | |
14544 | mips_opts.mips16 = 0; | |
7d10b47d | 14545 | mips_no_prev_insn (); |
252b5132 RH |
14546 | break; |
14547 | ||
1f25f5d3 CD |
14548 | case OPTION_MIPS3D: |
14549 | mips_opts.ase_mips3d = 1; | |
14550 | break; | |
14551 | ||
14552 | case OPTION_NO_MIPS3D: | |
14553 | mips_opts.ase_mips3d = 0; | |
14554 | break; | |
14555 | ||
e16bfa71 TS |
14556 | case OPTION_SMARTMIPS: |
14557 | mips_opts.ase_smartmips = 1; | |
14558 | break; | |
14559 | ||
14560 | case OPTION_NO_SMARTMIPS: | |
14561 | mips_opts.ase_smartmips = 0; | |
14562 | break; | |
14563 | ||
6a32d874 CM |
14564 | case OPTION_FIX_24K: |
14565 | mips_fix_24k = 1; | |
14566 | break; | |
14567 | ||
14568 | case OPTION_NO_FIX_24K: | |
14569 | mips_fix_24k = 0; | |
14570 | break; | |
14571 | ||
c67a084a NC |
14572 | case OPTION_FIX_LOONGSON2F_JUMP: |
14573 | mips_fix_loongson2f_jump = TRUE; | |
14574 | break; | |
14575 | ||
14576 | case OPTION_NO_FIX_LOONGSON2F_JUMP: | |
14577 | mips_fix_loongson2f_jump = FALSE; | |
14578 | break; | |
14579 | ||
14580 | case OPTION_FIX_LOONGSON2F_NOP: | |
14581 | mips_fix_loongson2f_nop = TRUE; | |
14582 | break; | |
14583 | ||
14584 | case OPTION_NO_FIX_LOONGSON2F_NOP: | |
14585 | mips_fix_loongson2f_nop = FALSE; | |
14586 | break; | |
14587 | ||
d766e8ec RS |
14588 | case OPTION_FIX_VR4120: |
14589 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
14590 | break; |
14591 | ||
d766e8ec RS |
14592 | case OPTION_NO_FIX_VR4120: |
14593 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
14594 | break; |
14595 | ||
7d8e00cf RS |
14596 | case OPTION_FIX_VR4130: |
14597 | mips_fix_vr4130 = 1; | |
14598 | break; | |
14599 | ||
14600 | case OPTION_NO_FIX_VR4130: | |
14601 | mips_fix_vr4130 = 0; | |
14602 | break; | |
14603 | ||
d954098f DD |
14604 | case OPTION_FIX_CN63XXP1: |
14605 | mips_fix_cn63xxp1 = TRUE; | |
14606 | break; | |
14607 | ||
14608 | case OPTION_NO_FIX_CN63XXP1: | |
14609 | mips_fix_cn63xxp1 = FALSE; | |
14610 | break; | |
14611 | ||
4a6a3df4 AO |
14612 | case OPTION_RELAX_BRANCH: |
14613 | mips_relax_branch = 1; | |
14614 | break; | |
14615 | ||
14616 | case OPTION_NO_RELAX_BRANCH: | |
14617 | mips_relax_branch = 0; | |
14618 | break; | |
14619 | ||
aa6975fb ILT |
14620 | case OPTION_MSHARED: |
14621 | mips_in_shared = TRUE; | |
14622 | break; | |
14623 | ||
14624 | case OPTION_MNO_SHARED: | |
14625 | mips_in_shared = FALSE; | |
14626 | break; | |
14627 | ||
aed1a261 RS |
14628 | case OPTION_MSYM32: |
14629 | mips_opts.sym32 = TRUE; | |
14630 | break; | |
14631 | ||
14632 | case OPTION_MNO_SYM32: | |
14633 | mips_opts.sym32 = FALSE; | |
14634 | break; | |
14635 | ||
0f074f60 | 14636 | #ifdef OBJ_ELF |
252b5132 RH |
14637 | /* When generating ELF code, we permit -KPIC and -call_shared to |
14638 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
14639 | intended to be compatible with Irix 5. */ | |
14640 | case OPTION_CALL_SHARED: | |
f43abd2b | 14641 | if (!IS_ELF) |
252b5132 RH |
14642 | { |
14643 | as_bad (_("-call_shared is supported only for ELF format")); | |
14644 | return 0; | |
14645 | } | |
14646 | mips_pic = SVR4_PIC; | |
143d77c5 | 14647 | mips_abicalls = TRUE; |
252b5132 RH |
14648 | break; |
14649 | ||
861fb55a DJ |
14650 | case OPTION_CALL_NONPIC: |
14651 | if (!IS_ELF) | |
14652 | { | |
14653 | as_bad (_("-call_nonpic is supported only for ELF format")); | |
14654 | return 0; | |
14655 | } | |
14656 | mips_pic = NO_PIC; | |
14657 | mips_abicalls = TRUE; | |
14658 | break; | |
14659 | ||
252b5132 | 14660 | case OPTION_NON_SHARED: |
f43abd2b | 14661 | if (!IS_ELF) |
252b5132 RH |
14662 | { |
14663 | as_bad (_("-non_shared is supported only for ELF format")); | |
14664 | return 0; | |
14665 | } | |
14666 | mips_pic = NO_PIC; | |
143d77c5 | 14667 | mips_abicalls = FALSE; |
252b5132 RH |
14668 | break; |
14669 | ||
44075ae2 TS |
14670 | /* The -xgot option tells the assembler to use 32 bit offsets |
14671 | when accessing the got in SVR4_PIC mode. It is for Irix | |
252b5132 RH |
14672 | compatibility. */ |
14673 | case OPTION_XGOT: | |
14674 | mips_big_got = 1; | |
14675 | break; | |
0f074f60 | 14676 | #endif /* OBJ_ELF */ |
252b5132 RH |
14677 | |
14678 | case 'G': | |
6caf9ef4 TS |
14679 | g_switch_value = atoi (arg); |
14680 | g_switch_seen = 1; | |
252b5132 RH |
14681 | break; |
14682 | ||
34ba82a8 TS |
14683 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
14684 | and -mabi=64. */ | |
252b5132 | 14685 | case OPTION_32: |
23fce1e3 NC |
14686 | if (IS_ELF) |
14687 | mips_abi = O32_ABI; | |
14688 | /* We silently ignore -32 for non-ELF targets. This greatly | |
14689 | simplifies the construction of the MIPS GAS test cases. */ | |
252b5132 RH |
14690 | break; |
14691 | ||
23fce1e3 | 14692 | #ifdef OBJ_ELF |
e013f690 | 14693 | case OPTION_N32: |
f43abd2b | 14694 | if (!IS_ELF) |
34ba82a8 TS |
14695 | { |
14696 | as_bad (_("-n32 is supported for ELF format only")); | |
14697 | return 0; | |
14698 | } | |
316f5878 | 14699 | mips_abi = N32_ABI; |
e013f690 | 14700 | break; |
252b5132 | 14701 | |
e013f690 | 14702 | case OPTION_64: |
f43abd2b | 14703 | if (!IS_ELF) |
34ba82a8 TS |
14704 | { |
14705 | as_bad (_("-64 is supported for ELF format only")); | |
14706 | return 0; | |
14707 | } | |
316f5878 | 14708 | mips_abi = N64_ABI; |
f43abd2b | 14709 | if (!support_64bit_objects()) |
e013f690 | 14710 | as_fatal (_("No compiled in support for 64 bit object file format")); |
252b5132 | 14711 | break; |
ae948b86 | 14712 | #endif /* OBJ_ELF */ |
252b5132 | 14713 | |
c97ef257 | 14714 | case OPTION_GP32: |
a325df1d | 14715 | file_mips_gp32 = 1; |
c97ef257 AH |
14716 | break; |
14717 | ||
14718 | case OPTION_GP64: | |
a325df1d | 14719 | file_mips_gp32 = 0; |
c97ef257 | 14720 | break; |
252b5132 | 14721 | |
ca4e0257 | 14722 | case OPTION_FP32: |
a325df1d | 14723 | file_mips_fp32 = 1; |
316f5878 RS |
14724 | break; |
14725 | ||
14726 | case OPTION_FP64: | |
14727 | file_mips_fp32 = 0; | |
ca4e0257 RS |
14728 | break; |
14729 | ||
037b32b9 AN |
14730 | case OPTION_SINGLE_FLOAT: |
14731 | file_mips_single_float = 1; | |
14732 | break; | |
14733 | ||
14734 | case OPTION_DOUBLE_FLOAT: | |
14735 | file_mips_single_float = 0; | |
14736 | break; | |
14737 | ||
14738 | case OPTION_SOFT_FLOAT: | |
14739 | file_mips_soft_float = 1; | |
14740 | break; | |
14741 | ||
14742 | case OPTION_HARD_FLOAT: | |
14743 | file_mips_soft_float = 0; | |
14744 | break; | |
14745 | ||
ae948b86 | 14746 | #ifdef OBJ_ELF |
252b5132 | 14747 | case OPTION_MABI: |
f43abd2b | 14748 | if (!IS_ELF) |
34ba82a8 TS |
14749 | { |
14750 | as_bad (_("-mabi is supported for ELF format only")); | |
14751 | return 0; | |
14752 | } | |
e013f690 | 14753 | if (strcmp (arg, "32") == 0) |
316f5878 | 14754 | mips_abi = O32_ABI; |
e013f690 | 14755 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 14756 | mips_abi = O64_ABI; |
e013f690 | 14757 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 14758 | mips_abi = N32_ABI; |
e013f690 TS |
14759 | else if (strcmp (arg, "64") == 0) |
14760 | { | |
316f5878 | 14761 | mips_abi = N64_ABI; |
e013f690 TS |
14762 | if (! support_64bit_objects()) |
14763 | as_fatal (_("No compiled in support for 64 bit object file " | |
14764 | "format")); | |
14765 | } | |
14766 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 14767 | mips_abi = EABI_ABI; |
e013f690 | 14768 | else |
da0e507f TS |
14769 | { |
14770 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
14771 | return 0; | |
14772 | } | |
252b5132 | 14773 | break; |
e013f690 | 14774 | #endif /* OBJ_ELF */ |
252b5132 | 14775 | |
6b76fefe | 14776 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 14777 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
14778 | break; |
14779 | ||
9ee72ff1 | 14780 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 14781 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
14782 | break; |
14783 | ||
ecb4347a DJ |
14784 | #ifdef OBJ_ELF |
14785 | case OPTION_MDEBUG: | |
b34976b6 | 14786 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
14787 | break; |
14788 | ||
14789 | case OPTION_NO_MDEBUG: | |
b34976b6 | 14790 | mips_flag_mdebug = FALSE; |
ecb4347a | 14791 | break; |
dcd410fe RO |
14792 | |
14793 | case OPTION_PDR: | |
14794 | mips_flag_pdr = TRUE; | |
14795 | break; | |
14796 | ||
14797 | case OPTION_NO_PDR: | |
14798 | mips_flag_pdr = FALSE; | |
14799 | break; | |
0a44bf69 RS |
14800 | |
14801 | case OPTION_MVXWORKS_PIC: | |
14802 | mips_pic = VXWORKS_PIC; | |
14803 | break; | |
ecb4347a DJ |
14804 | #endif /* OBJ_ELF */ |
14805 | ||
252b5132 RH |
14806 | default: |
14807 | return 0; | |
14808 | } | |
14809 | ||
c67a084a NC |
14810 | mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump; |
14811 | ||
252b5132 RH |
14812 | return 1; |
14813 | } | |
316f5878 RS |
14814 | \f |
14815 | /* Set up globals to generate code for the ISA or processor | |
14816 | described by INFO. */ | |
252b5132 | 14817 | |
252b5132 | 14818 | static void |
17a2f251 | 14819 | mips_set_architecture (const struct mips_cpu_info *info) |
252b5132 | 14820 | { |
316f5878 | 14821 | if (info != 0) |
252b5132 | 14822 | { |
fef14a42 TS |
14823 | file_mips_arch = info->cpu; |
14824 | mips_opts.arch = info->cpu; | |
316f5878 | 14825 | mips_opts.isa = info->isa; |
252b5132 | 14826 | } |
252b5132 RH |
14827 | } |
14828 | ||
252b5132 | 14829 | |
316f5878 | 14830 | /* Likewise for tuning. */ |
252b5132 | 14831 | |
316f5878 | 14832 | static void |
17a2f251 | 14833 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
14834 | { |
14835 | if (info != 0) | |
fef14a42 | 14836 | mips_tune = info->cpu; |
316f5878 | 14837 | } |
80cc45a5 | 14838 | |
34ba82a8 | 14839 | |
252b5132 | 14840 | void |
17a2f251 | 14841 | mips_after_parse_args (void) |
e9670677 | 14842 | { |
fef14a42 TS |
14843 | const struct mips_cpu_info *arch_info = 0; |
14844 | const struct mips_cpu_info *tune_info = 0; | |
14845 | ||
e9670677 | 14846 | /* GP relative stuff not working for PE */ |
6caf9ef4 | 14847 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
e9670677 | 14848 | { |
6caf9ef4 | 14849 | if (g_switch_seen && g_switch_value != 0) |
e9670677 MR |
14850 | as_bad (_("-G not supported in this configuration.")); |
14851 | g_switch_value = 0; | |
14852 | } | |
14853 | ||
cac012d6 AO |
14854 | if (mips_abi == NO_ABI) |
14855 | mips_abi = MIPS_DEFAULT_ABI; | |
14856 | ||
22923709 RS |
14857 | /* The following code determines the architecture and register size. |
14858 | Similar code was added to GCC 3.3 (see override_options() in | |
14859 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
14860 | as much as possible. */ | |
e9670677 | 14861 | |
316f5878 | 14862 | if (mips_arch_string != 0) |
fef14a42 | 14863 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 14864 | |
316f5878 | 14865 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 14866 | { |
316f5878 | 14867 | /* Handle -mipsN. At this point, file_mips_isa contains the |
fef14a42 | 14868 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 14869 | the -march selection (if any). */ |
fef14a42 | 14870 | if (arch_info != 0) |
e9670677 | 14871 | { |
316f5878 RS |
14872 | /* -march takes precedence over -mipsN, since it is more descriptive. |
14873 | There's no harm in specifying both as long as the ISA levels | |
14874 | are the same. */ | |
fef14a42 | 14875 | if (file_mips_isa != arch_info->isa) |
316f5878 RS |
14876 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), |
14877 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
fef14a42 | 14878 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 14879 | } |
316f5878 | 14880 | else |
fef14a42 | 14881 | arch_info = mips_cpu_info_from_isa (file_mips_isa); |
e9670677 MR |
14882 | } |
14883 | ||
fef14a42 TS |
14884 | if (arch_info == 0) |
14885 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
e9670677 | 14886 | |
fef14a42 | 14887 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
20203fb9 | 14888 | as_bad (_("-march=%s is not compatible with the selected ABI"), |
fef14a42 TS |
14889 | arch_info->name); |
14890 | ||
14891 | mips_set_architecture (arch_info); | |
14892 | ||
14893 | /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ | |
14894 | if (mips_tune_string != 0) | |
14895 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 14896 | |
fef14a42 TS |
14897 | if (tune_info == 0) |
14898 | mips_set_tune (arch_info); | |
14899 | else | |
14900 | mips_set_tune (tune_info); | |
e9670677 | 14901 | |
316f5878 | 14902 | if (file_mips_gp32 >= 0) |
e9670677 | 14903 | { |
316f5878 RS |
14904 | /* The user specified the size of the integer registers. Make sure |
14905 | it agrees with the ABI and ISA. */ | |
14906 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
14907 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
14908 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
14909 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
14910 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
14911 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
14912 | } |
14913 | else | |
14914 | { | |
316f5878 RS |
14915 | /* Infer the integer register size from the ABI and processor. |
14916 | Restrict ourselves to 32-bit registers if that's all the | |
14917 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
14918 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
14919 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
14920 | } |
14921 | ||
ad3fea08 TS |
14922 | switch (file_mips_fp32) |
14923 | { | |
14924 | default: | |
14925 | case -1: | |
14926 | /* No user specified float register size. | |
14927 | ??? GAS treats single-float processors as though they had 64-bit | |
14928 | float registers (although it complains when double-precision | |
14929 | instructions are used). As things stand, saying they have 32-bit | |
14930 | registers would lead to spurious "register must be even" messages. | |
14931 | So here we assume float registers are never smaller than the | |
14932 | integer ones. */ | |
14933 | if (file_mips_gp32 == 0) | |
14934 | /* 64-bit integer registers implies 64-bit float registers. */ | |
14935 | file_mips_fp32 = 0; | |
14936 | else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0) | |
14937 | && ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
14938 | /* -mips3d and -mdmx imply 64-bit float registers, if possible. */ | |
14939 | file_mips_fp32 = 0; | |
14940 | else | |
14941 | /* 32-bit float registers. */ | |
14942 | file_mips_fp32 = 1; | |
14943 | break; | |
14944 | ||
14945 | /* The user specified the size of the float registers. Check if it | |
14946 | agrees with the ABI and ISA. */ | |
14947 | case 0: | |
14948 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
14949 | as_bad (_("-mfp64 used with a 32-bit fpu")); | |
14950 | else if (ABI_NEEDS_32BIT_REGS (mips_abi) | |
14951 | && !ISA_HAS_MXHC1 (mips_opts.isa)) | |
14952 | as_warn (_("-mfp64 used with a 32-bit ABI")); | |
14953 | break; | |
14954 | case 1: | |
14955 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
14956 | as_warn (_("-mfp32 used with a 64-bit ABI")); | |
14957 | break; | |
14958 | } | |
e9670677 | 14959 | |
316f5878 | 14960 | /* End of GCC-shared inference code. */ |
e9670677 | 14961 | |
17a2f251 TS |
14962 | /* This flag is set when we have a 64-bit capable CPU but use only |
14963 | 32-bit wide registers. Note that EABI does not use it. */ | |
14964 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) | |
14965 | && ((mips_abi == NO_ABI && file_mips_gp32 == 1) | |
14966 | || mips_abi == O32_ABI)) | |
316f5878 | 14967 | mips_32bitmode = 1; |
e9670677 MR |
14968 | |
14969 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
14970 | as_bad (_("trap exception not supported at ISA 1")); | |
14971 | ||
e9670677 MR |
14972 | /* If the selected architecture includes support for ASEs, enable |
14973 | generation of code for them. */ | |
a4672219 | 14974 | if (mips_opts.mips16 == -1) |
fef14a42 | 14975 | mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; |
df58fc94 RS |
14976 | if (mips_opts.micromips == -1) |
14977 | mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0; | |
ffdefa66 | 14978 | if (mips_opts.ase_mips3d == -1) |
65263ce3 | 14979 | mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D) |
ad3fea08 TS |
14980 | && file_mips_fp32 == 0) ? 1 : 0; |
14981 | if (mips_opts.ase_mips3d && file_mips_fp32 == 1) | |
14982 | as_bad (_("-mfp32 used with -mips3d")); | |
14983 | ||
ffdefa66 | 14984 | if (mips_opts.ase_mdmx == -1) |
65263ce3 | 14985 | mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX) |
ad3fea08 TS |
14986 | && file_mips_fp32 == 0) ? 1 : 0; |
14987 | if (mips_opts.ase_mdmx && file_mips_fp32 == 1) | |
14988 | as_bad (_("-mfp32 used with -mdmx")); | |
14989 | ||
14990 | if (mips_opts.ase_smartmips == -1) | |
14991 | mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0; | |
14992 | if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS) | |
20203fb9 NC |
14993 | as_warn (_("%s ISA does not support SmartMIPS"), |
14994 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
ad3fea08 | 14995 | |
74cd071d | 14996 | if (mips_opts.ase_dsp == -1) |
ad3fea08 TS |
14997 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; |
14998 | if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE) | |
20203fb9 NC |
14999 | as_warn (_("%s ISA does not support DSP ASE"), |
15000 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
ad3fea08 | 15001 | |
8b082fb1 TS |
15002 | if (mips_opts.ase_dspr2 == -1) |
15003 | { | |
15004 | mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0; | |
15005 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; | |
15006 | } | |
15007 | if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE) | |
20203fb9 NC |
15008 | as_warn (_("%s ISA does not support DSP R2 ASE"), |
15009 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
8b082fb1 | 15010 | |
ef2e4d86 | 15011 | if (mips_opts.ase_mt == -1) |
ad3fea08 TS |
15012 | mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0; |
15013 | if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE) | |
20203fb9 NC |
15014 | as_warn (_("%s ISA does not support MT ASE"), |
15015 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
e9670677 | 15016 | |
e9670677 | 15017 | file_mips_isa = mips_opts.isa; |
e9670677 MR |
15018 | file_ase_mips3d = mips_opts.ase_mips3d; |
15019 | file_ase_mdmx = mips_opts.ase_mdmx; | |
e16bfa71 | 15020 | file_ase_smartmips = mips_opts.ase_smartmips; |
74cd071d | 15021 | file_ase_dsp = mips_opts.ase_dsp; |
8b082fb1 | 15022 | file_ase_dspr2 = mips_opts.ase_dspr2; |
ef2e4d86 | 15023 | file_ase_mt = mips_opts.ase_mt; |
e9670677 MR |
15024 | mips_opts.gp32 = file_mips_gp32; |
15025 | mips_opts.fp32 = file_mips_fp32; | |
037b32b9 AN |
15026 | mips_opts.soft_float = file_mips_soft_float; |
15027 | mips_opts.single_float = file_mips_single_float; | |
e9670677 | 15028 | |
ecb4347a DJ |
15029 | if (mips_flag_mdebug < 0) |
15030 | { | |
15031 | #ifdef OBJ_MAYBE_ECOFF | |
15032 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) | |
15033 | mips_flag_mdebug = 1; | |
15034 | else | |
15035 | #endif /* OBJ_MAYBE_ECOFF */ | |
15036 | mips_flag_mdebug = 0; | |
15037 | } | |
e9670677 MR |
15038 | } |
15039 | \f | |
15040 | void | |
17a2f251 | 15041 | mips_init_after_args (void) |
252b5132 RH |
15042 | { |
15043 | /* initialize opcodes */ | |
15044 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 15045 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
15046 | } |
15047 | ||
15048 | long | |
17a2f251 | 15049 | md_pcrel_from (fixS *fixP) |
252b5132 | 15050 | { |
a7ebbfdf TS |
15051 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
15052 | switch (fixP->fx_r_type) | |
15053 | { | |
df58fc94 RS |
15054 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15055 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15056 | /* Return the address of the delay slot. */ | |
15057 | return addr + 2; | |
15058 | ||
15059 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15060 | case BFD_RELOC_MICROMIPS_JMP: | |
a7ebbfdf TS |
15061 | case BFD_RELOC_16_PCREL_S2: |
15062 | case BFD_RELOC_MIPS_JMP: | |
15063 | /* Return the address of the delay slot. */ | |
15064 | return addr + 4; | |
df58fc94 | 15065 | |
a7ebbfdf | 15066 | default: |
58ea3d6a | 15067 | /* We have no relocation type for PC relative MIPS16 instructions. */ |
64817874 TS |
15068 | if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg) |
15069 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15070 | _("PC relative MIPS16 instruction references a different section")); | |
a7ebbfdf TS |
15071 | return addr; |
15072 | } | |
252b5132 RH |
15073 | } |
15074 | ||
252b5132 RH |
15075 | /* This is called before the symbol table is processed. In order to |
15076 | work with gcc when using mips-tfile, we must keep all local labels. | |
15077 | However, in other cases, we want to discard them. If we were | |
15078 | called with -g, but we didn't see any debugging information, it may | |
15079 | mean that gcc is smuggling debugging information through to | |
15080 | mips-tfile, in which case we must generate all local labels. */ | |
15081 | ||
15082 | void | |
17a2f251 | 15083 | mips_frob_file_before_adjust (void) |
252b5132 RH |
15084 | { |
15085 | #ifndef NO_ECOFF_DEBUGGING | |
15086 | if (ECOFF_DEBUGGING | |
15087 | && mips_debug != 0 | |
15088 | && ! ecoff_debugging_seen) | |
15089 | flag_keep_locals = 1; | |
15090 | #endif | |
15091 | } | |
15092 | ||
3b91255e | 15093 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
55cf6793 | 15094 | the corresponding LO16 reloc. This is called before md_apply_fix and |
3b91255e RS |
15095 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit |
15096 | relocation operators. | |
15097 | ||
15098 | For our purposes, a %lo() expression matches a %got() or %hi() | |
15099 | expression if: | |
15100 | ||
15101 | (a) it refers to the same symbol; and | |
15102 | (b) the offset applied in the %lo() expression is no lower than | |
15103 | the offset applied in the %got() or %hi(). | |
15104 | ||
15105 | (b) allows us to cope with code like: | |
15106 | ||
15107 | lui $4,%hi(foo) | |
15108 | lh $4,%lo(foo+2)($4) | |
15109 | ||
15110 | ...which is legal on RELA targets, and has a well-defined behaviour | |
15111 | if the user knows that adding 2 to "foo" will not induce a carry to | |
15112 | the high 16 bits. | |
15113 | ||
15114 | When several %lo()s match a particular %got() or %hi(), we use the | |
15115 | following rules to distinguish them: | |
15116 | ||
15117 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
15118 | higher offsets. | |
15119 | ||
15120 | (2) %lo()s with no matching %got() or %hi() are better than those | |
15121 | that already have a matching %got() or %hi(). | |
15122 | ||
15123 | (3) later %lo()s are better than earlier %lo()s. | |
15124 | ||
15125 | These rules are applied in order. | |
15126 | ||
15127 | (1) means, among other things, that %lo()s with identical offsets are | |
15128 | chosen if they exist. | |
15129 | ||
15130 | (2) means that we won't associate several high-part relocations with | |
15131 | the same low-part relocation unless there's no alternative. Having | |
15132 | several high parts for the same low part is a GNU extension; this rule | |
15133 | allows careful users to avoid it. | |
15134 | ||
15135 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
15136 | with the last high-part relocation being at the front of the list. | |
15137 | It therefore makes sense to choose the last matching low-part | |
15138 | relocation, all other things being equal. It's also easier | |
15139 | to code that way. */ | |
252b5132 RH |
15140 | |
15141 | void | |
17a2f251 | 15142 | mips_frob_file (void) |
252b5132 RH |
15143 | { |
15144 | struct mips_hi_fixup *l; | |
35903be0 | 15145 | bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED; |
252b5132 RH |
15146 | |
15147 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
15148 | { | |
15149 | segment_info_type *seginfo; | |
3b91255e RS |
15150 | bfd_boolean matched_lo_p; |
15151 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 15152 | |
9c2799c2 | 15153 | gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 15154 | |
5919d012 RS |
15155 | /* If a GOT16 relocation turns out to be against a global symbol, |
15156 | there isn't supposed to be a matching LO. */ | |
738e5348 | 15157 | if (got16_reloc_p (l->fixp->fx_r_type) |
5919d012 RS |
15158 | && !pic_need_relax (l->fixp->fx_addsy, l->seg)) |
15159 | continue; | |
15160 | ||
15161 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
15162 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
15163 | continue; |
15164 | ||
252b5132 | 15165 | seginfo = seg_info (l->seg); |
252b5132 | 15166 | |
3b91255e RS |
15167 | /* Set HI_POS to the position of this relocation in the chain. |
15168 | Set LO_POS to the position of the chosen low-part relocation. | |
15169 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
15170 | relocation that matches an immediately-preceding high-part | |
15171 | relocation. */ | |
15172 | hi_pos = NULL; | |
15173 | lo_pos = NULL; | |
15174 | matched_lo_p = FALSE; | |
738e5348 | 15175 | looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type); |
35903be0 | 15176 | |
3b91255e RS |
15177 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) |
15178 | { | |
15179 | if (*pos == l->fixp) | |
15180 | hi_pos = pos; | |
15181 | ||
35903be0 | 15182 | if ((*pos)->fx_r_type == looking_for_rtype |
30cfc97a | 15183 | && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy) |
3b91255e RS |
15184 | && (*pos)->fx_offset >= l->fixp->fx_offset |
15185 | && (lo_pos == NULL | |
15186 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
15187 | || (!matched_lo_p | |
15188 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
15189 | lo_pos = pos; | |
15190 | ||
15191 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
15192 | && fixup_has_matching_lo_p (*pos)); | |
15193 | } | |
15194 | ||
15195 | /* If we found a match, remove the high-part relocation from its | |
15196 | current position and insert it before the low-part relocation. | |
15197 | Make the offsets match so that fixup_has_matching_lo_p() | |
15198 | will return true. | |
15199 | ||
15200 | We don't warn about unmatched high-part relocations since some | |
15201 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
15202 | instructions. */ | |
15203 | if (lo_pos != NULL) | |
15204 | { | |
15205 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
15206 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 15207 | { |
3b91255e RS |
15208 | *hi_pos = l->fixp->fx_next; |
15209 | l->fixp->fx_next = *lo_pos; | |
15210 | *lo_pos = l->fixp; | |
252b5132 | 15211 | } |
252b5132 RH |
15212 | } |
15213 | } | |
15214 | } | |
15215 | ||
3e722fb5 | 15216 | /* We may have combined relocations without symbols in the N32/N64 ABI. |
f6688943 | 15217 | We have to prevent gas from dropping them. */ |
252b5132 | 15218 | |
252b5132 | 15219 | int |
17a2f251 | 15220 | mips_force_relocation (fixS *fixp) |
252b5132 | 15221 | { |
ae6063d4 | 15222 | if (generic_force_reloc (fixp)) |
252b5132 RH |
15223 | return 1; |
15224 | ||
df58fc94 RS |
15225 | /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation, |
15226 | so that the linker relaxation can update targets. */ | |
15227 | if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
15228 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
15229 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1) | |
15230 | return 1; | |
15231 | ||
f6688943 TS |
15232 | if (HAVE_NEWABI |
15233 | && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr | |
15234 | && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB | |
738e5348 RS |
15235 | || hi16_reloc_p (fixp->fx_r_type) |
15236 | || lo16_reloc_p (fixp->fx_r_type))) | |
f6688943 TS |
15237 | return 1; |
15238 | ||
3e722fb5 | 15239 | return 0; |
252b5132 RH |
15240 | } |
15241 | ||
15242 | /* Apply a fixup to the object file. */ | |
15243 | ||
94f592af | 15244 | void |
55cf6793 | 15245 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 15246 | { |
874e8986 | 15247 | bfd_byte *buf; |
98aa84af | 15248 | long insn; |
a7ebbfdf | 15249 | reloc_howto_type *howto; |
252b5132 | 15250 | |
a7ebbfdf TS |
15251 | /* We ignore generic BFD relocations we don't know about. */ |
15252 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
15253 | if (! howto) | |
15254 | return; | |
65551fa4 | 15255 | |
df58fc94 RS |
15256 | gas_assert (fixP->fx_size == 2 |
15257 | || fixP->fx_size == 4 | |
90ecf173 MR |
15258 | || fixP->fx_r_type == BFD_RELOC_16 |
15259 | || fixP->fx_r_type == BFD_RELOC_64 | |
15260 | || fixP->fx_r_type == BFD_RELOC_CTOR | |
15261 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
df58fc94 | 15262 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB |
90ecf173 MR |
15263 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
15264 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY | |
15265 | || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64); | |
252b5132 | 15266 | |
a7ebbfdf | 15267 | buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); |
252b5132 | 15268 | |
df58fc94 RS |
15269 | gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2 |
15270 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
15271 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
15272 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
b1dca8ee RS |
15273 | |
15274 | /* Don't treat parts of a composite relocation as done. There are two | |
15275 | reasons for this: | |
15276 | ||
15277 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
15278 | should nevertheless be emitted if the first part is. | |
15279 | ||
15280 | (2) In normal usage, composite relocations are never assembly-time | |
15281 | constants. The easiest way of dealing with the pathological | |
15282 | exceptions is to generate a relocation against STN_UNDEF and | |
15283 | leave everything up to the linker. */ | |
3994f87e | 15284 | if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0) |
252b5132 RH |
15285 | fixP->fx_done = 1; |
15286 | ||
15287 | switch (fixP->fx_r_type) | |
15288 | { | |
3f98094e DJ |
15289 | case BFD_RELOC_MIPS_TLS_GD: |
15290 | case BFD_RELOC_MIPS_TLS_LDM: | |
741d6ea8 JM |
15291 | case BFD_RELOC_MIPS_TLS_DTPREL32: |
15292 | case BFD_RELOC_MIPS_TLS_DTPREL64: | |
3f98094e DJ |
15293 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: |
15294 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
15295 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
15296 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: | |
15297 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
df58fc94 RS |
15298 | case BFD_RELOC_MICROMIPS_TLS_GD: |
15299 | case BFD_RELOC_MICROMIPS_TLS_LDM: | |
15300 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16: | |
15301 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16: | |
15302 | case BFD_RELOC_MICROMIPS_TLS_GOTTPREL: | |
15303 | case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16: | |
15304 | case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16: | |
3f98094e DJ |
15305 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
15306 | /* fall through */ | |
15307 | ||
252b5132 | 15308 | case BFD_RELOC_MIPS_JMP: |
e369bcce TS |
15309 | case BFD_RELOC_MIPS_SHIFT5: |
15310 | case BFD_RELOC_MIPS_SHIFT6: | |
15311 | case BFD_RELOC_MIPS_GOT_DISP: | |
15312 | case BFD_RELOC_MIPS_GOT_PAGE: | |
15313 | case BFD_RELOC_MIPS_GOT_OFST: | |
15314 | case BFD_RELOC_MIPS_SUB: | |
15315 | case BFD_RELOC_MIPS_INSERT_A: | |
15316 | case BFD_RELOC_MIPS_INSERT_B: | |
15317 | case BFD_RELOC_MIPS_DELETE: | |
15318 | case BFD_RELOC_MIPS_HIGHEST: | |
15319 | case BFD_RELOC_MIPS_HIGHER: | |
15320 | case BFD_RELOC_MIPS_SCN_DISP: | |
15321 | case BFD_RELOC_MIPS_REL16: | |
15322 | case BFD_RELOC_MIPS_RELGOT: | |
15323 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
15324 | case BFD_RELOC_HI16: |
15325 | case BFD_RELOC_HI16_S: | |
cdf6fd85 | 15326 | case BFD_RELOC_GPREL16: |
252b5132 RH |
15327 | case BFD_RELOC_MIPS_LITERAL: |
15328 | case BFD_RELOC_MIPS_CALL16: | |
15329 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 15330 | case BFD_RELOC_GPREL32: |
252b5132 RH |
15331 | case BFD_RELOC_MIPS_GOT_HI16: |
15332 | case BFD_RELOC_MIPS_GOT_LO16: | |
15333 | case BFD_RELOC_MIPS_CALL_HI16: | |
15334 | case BFD_RELOC_MIPS_CALL_LO16: | |
15335 | case BFD_RELOC_MIPS16_GPREL: | |
738e5348 RS |
15336 | case BFD_RELOC_MIPS16_GOT16: |
15337 | case BFD_RELOC_MIPS16_CALL16: | |
d6f16593 MR |
15338 | case BFD_RELOC_MIPS16_HI16: |
15339 | case BFD_RELOC_MIPS16_HI16_S: | |
252b5132 | 15340 | case BFD_RELOC_MIPS16_JMP: |
df58fc94 RS |
15341 | case BFD_RELOC_MICROMIPS_JMP: |
15342 | case BFD_RELOC_MICROMIPS_GOT_DISP: | |
15343 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
15344 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
15345 | case BFD_RELOC_MICROMIPS_SUB: | |
15346 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
15347 | case BFD_RELOC_MICROMIPS_HIGHER: | |
15348 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
15349 | case BFD_RELOC_MICROMIPS_JALR: | |
15350 | case BFD_RELOC_MICROMIPS_HI16: | |
15351 | case BFD_RELOC_MICROMIPS_HI16_S: | |
15352 | case BFD_RELOC_MICROMIPS_GPREL16: | |
15353 | case BFD_RELOC_MICROMIPS_LITERAL: | |
15354 | case BFD_RELOC_MICROMIPS_CALL16: | |
15355 | case BFD_RELOC_MICROMIPS_GOT16: | |
15356 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
15357 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
15358 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
15359 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
54f4ddb3 | 15360 | /* Nothing needed to do. The value comes from the reloc entry. */ |
252b5132 RH |
15361 | break; |
15362 | ||
252b5132 RH |
15363 | case BFD_RELOC_64: |
15364 | /* This is handled like BFD_RELOC_32, but we output a sign | |
15365 | extended value if we are only 32 bits. */ | |
3e722fb5 | 15366 | if (fixP->fx_done) |
252b5132 RH |
15367 | { |
15368 | if (8 <= sizeof (valueT)) | |
2132e3a3 | 15369 | md_number_to_chars ((char *) buf, *valP, 8); |
252b5132 RH |
15370 | else |
15371 | { | |
a7ebbfdf | 15372 | valueT hiv; |
252b5132 | 15373 | |
a7ebbfdf | 15374 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
15375 | hiv = 0xffffffff; |
15376 | else | |
15377 | hiv = 0; | |
b215186b | 15378 | md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)), |
a7ebbfdf | 15379 | *valP, 4); |
b215186b | 15380 | md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)), |
a7ebbfdf | 15381 | hiv, 4); |
252b5132 RH |
15382 | } |
15383 | } | |
15384 | break; | |
15385 | ||
056350c6 | 15386 | case BFD_RELOC_RVA: |
252b5132 | 15387 | case BFD_RELOC_32: |
252b5132 RH |
15388 | case BFD_RELOC_16: |
15389 | /* If we are deleting this reloc entry, we must fill in the | |
54f4ddb3 TS |
15390 | value now. This can happen if we have a .word which is not |
15391 | resolved when it appears but is later defined. */ | |
252b5132 | 15392 | if (fixP->fx_done) |
54f4ddb3 | 15393 | md_number_to_chars ((char *) buf, *valP, fixP->fx_size); |
252b5132 RH |
15394 | break; |
15395 | ||
15396 | case BFD_RELOC_LO16: | |
d6f16593 | 15397 | case BFD_RELOC_MIPS16_LO16: |
df58fc94 | 15398 | case BFD_RELOC_MICROMIPS_LO16: |
3e722fb5 CD |
15399 | /* FIXME: Now that embedded-PIC is gone, some of this code/comment |
15400 | may be safe to remove, but if so it's not obvious. */ | |
252b5132 RH |
15401 | /* When handling an embedded PIC switch statement, we can wind |
15402 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
15403 | if (fixP->fx_done) | |
15404 | { | |
a7ebbfdf | 15405 | if (*valP + 0x8000 > 0xffff) |
252b5132 RH |
15406 | as_bad_where (fixP->fx_file, fixP->fx_line, |
15407 | _("relocation overflow")); | |
df58fc94 RS |
15408 | /* 32-bit microMIPS instructions are divided into two halfwords. |
15409 | Relocations always refer to the second halfword, regardless | |
15410 | of endianness. */ | |
15411 | if (target_big_endian || fixP->fx_r_type == BFD_RELOC_MICROMIPS_LO16) | |
252b5132 | 15412 | buf += 2; |
2132e3a3 | 15413 | md_number_to_chars ((char *) buf, *valP, 2); |
252b5132 RH |
15414 | } |
15415 | break; | |
15416 | ||
15417 | case BFD_RELOC_16_PCREL_S2: | |
a7ebbfdf | 15418 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 15419 | as_bad_where (fixP->fx_file, fixP->fx_line, |
bad36eac | 15420 | _("Branch to misaligned address (%lx)"), (long) *valP); |
cb56d3d3 | 15421 | |
54f4ddb3 TS |
15422 | /* We need to save the bits in the instruction since fixup_segment() |
15423 | might be deleting the relocation entry (i.e., a branch within | |
15424 | the current segment). */ | |
a7ebbfdf | 15425 | if (! fixP->fx_done) |
bb2d6cd7 | 15426 | break; |
252b5132 | 15427 | |
54f4ddb3 | 15428 | /* Update old instruction data. */ |
252b5132 RH |
15429 | if (target_big_endian) |
15430 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
15431 | else | |
15432 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
15433 | ||
a7ebbfdf TS |
15434 | if (*valP + 0x20000 <= 0x3ffff) |
15435 | { | |
15436 | insn |= (*valP >> 2) & 0xffff; | |
2132e3a3 | 15437 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
15438 | } |
15439 | else if (mips_pic == NO_PIC | |
15440 | && fixP->fx_done | |
15441 | && fixP->fx_frag->fr_address >= text_section->vma | |
15442 | && (fixP->fx_frag->fr_address | |
587aac4e | 15443 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
15444 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
15445 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
15446 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
15447 | { |
15448 | /* The branch offset is too large. If this is an | |
15449 | unconditional branch, and we are not generating PIC code, | |
15450 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
15451 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
15452 | insn = 0x0c000000; /* jal */ | |
252b5132 | 15453 | else |
a7ebbfdf TS |
15454 | insn = 0x08000000; /* j */ |
15455 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
15456 | fixP->fx_done = 0; | |
15457 | fixP->fx_addsy = section_symbol (text_section); | |
15458 | *valP += md_pcrel_from (fixP); | |
2132e3a3 | 15459 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
15460 | } |
15461 | else | |
15462 | { | |
15463 | /* If we got here, we have branch-relaxation disabled, | |
15464 | and there's nothing we can do to fix this instruction | |
15465 | without turning it into a longer sequence. */ | |
15466 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15467 | _("Branch out of range")); | |
252b5132 | 15468 | } |
252b5132 RH |
15469 | break; |
15470 | ||
df58fc94 RS |
15471 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15472 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15473 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15474 | /* We adjust the offset back to even. */ | |
15475 | if ((*valP & 0x1) != 0) | |
15476 | --(*valP); | |
15477 | ||
15478 | if (! fixP->fx_done) | |
15479 | break; | |
15480 | ||
15481 | /* Should never visit here, because we keep the relocation. */ | |
15482 | abort (); | |
15483 | break; | |
15484 | ||
252b5132 RH |
15485 | case BFD_RELOC_VTABLE_INHERIT: |
15486 | fixP->fx_done = 0; | |
15487 | if (fixP->fx_addsy | |
15488 | && !S_IS_DEFINED (fixP->fx_addsy) | |
15489 | && !S_IS_WEAK (fixP->fx_addsy)) | |
15490 | S_SET_WEAK (fixP->fx_addsy); | |
15491 | break; | |
15492 | ||
15493 | case BFD_RELOC_VTABLE_ENTRY: | |
15494 | fixP->fx_done = 0; | |
15495 | break; | |
15496 | ||
15497 | default: | |
15498 | internalError (); | |
15499 | } | |
a7ebbfdf TS |
15500 | |
15501 | /* Remember value for tc_gen_reloc. */ | |
15502 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
15503 | } |
15504 | ||
252b5132 | 15505 | static symbolS * |
17a2f251 | 15506 | get_symbol (void) |
252b5132 RH |
15507 | { |
15508 | int c; | |
15509 | char *name; | |
15510 | symbolS *p; | |
15511 | ||
15512 | name = input_line_pointer; | |
15513 | c = get_symbol_end (); | |
15514 | p = (symbolS *) symbol_find_or_make (name); | |
15515 | *input_line_pointer = c; | |
15516 | return p; | |
15517 | } | |
15518 | ||
742a56fe RS |
15519 | /* Align the current frag to a given power of two. If a particular |
15520 | fill byte should be used, FILL points to an integer that contains | |
15521 | that byte, otherwise FILL is null. | |
15522 | ||
15523 | The MIPS assembler also automatically adjusts any preceding | |
15524 | label. */ | |
252b5132 RH |
15525 | |
15526 | static void | |
742a56fe | 15527 | mips_align (int to, int *fill, symbolS *label) |
252b5132 | 15528 | { |
7d10b47d | 15529 | mips_emit_delays (); |
df58fc94 | 15530 | mips_record_compressed_mode (); |
742a56fe RS |
15531 | if (fill == NULL && subseg_text_p (now_seg)) |
15532 | frag_align_code (to, 0); | |
15533 | else | |
15534 | frag_align (to, fill ? *fill : 0, 0); | |
252b5132 RH |
15535 | record_alignment (now_seg, to); |
15536 | if (label != NULL) | |
15537 | { | |
9c2799c2 | 15538 | gas_assert (S_GET_SEGMENT (label) == now_seg); |
49309057 | 15539 | symbol_set_frag (label, frag_now); |
252b5132 RH |
15540 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
15541 | } | |
15542 | } | |
15543 | ||
15544 | /* Align to a given power of two. .align 0 turns off the automatic | |
15545 | alignment used by the data creating pseudo-ops. */ | |
15546 | ||
15547 | static void | |
17a2f251 | 15548 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 | 15549 | { |
742a56fe | 15550 | int temp, fill_value, *fill_ptr; |
49954fb4 | 15551 | long max_alignment = 28; |
252b5132 | 15552 | |
54f4ddb3 | 15553 | /* o Note that the assembler pulls down any immediately preceding label |
252b5132 | 15554 | to the aligned address. |
54f4ddb3 | 15555 | o It's not documented but auto alignment is reinstated by |
252b5132 | 15556 | a .align pseudo instruction. |
54f4ddb3 | 15557 | o Note also that after auto alignment is turned off the mips assembler |
252b5132 | 15558 | issues an error on attempt to assemble an improperly aligned data item. |
54f4ddb3 | 15559 | We don't. */ |
252b5132 RH |
15560 | |
15561 | temp = get_absolute_expression (); | |
15562 | if (temp > max_alignment) | |
15563 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
15564 | else if (temp < 0) | |
15565 | { | |
15566 | as_warn (_("Alignment negative: 0 assumed.")); | |
15567 | temp = 0; | |
15568 | } | |
15569 | if (*input_line_pointer == ',') | |
15570 | { | |
f9419b05 | 15571 | ++input_line_pointer; |
742a56fe RS |
15572 | fill_value = get_absolute_expression (); |
15573 | fill_ptr = &fill_value; | |
252b5132 RH |
15574 | } |
15575 | else | |
742a56fe | 15576 | fill_ptr = 0; |
252b5132 RH |
15577 | if (temp) |
15578 | { | |
a8dbcb85 TS |
15579 | segment_info_type *si = seg_info (now_seg); |
15580 | struct insn_label_list *l = si->label_list; | |
54f4ddb3 | 15581 | /* Auto alignment should be switched on by next section change. */ |
252b5132 | 15582 | auto_align = 1; |
742a56fe | 15583 | mips_align (temp, fill_ptr, l != NULL ? l->label : NULL); |
252b5132 RH |
15584 | } |
15585 | else | |
15586 | { | |
15587 | auto_align = 0; | |
15588 | } | |
15589 | ||
15590 | demand_empty_rest_of_line (); | |
15591 | } | |
15592 | ||
252b5132 | 15593 | static void |
17a2f251 | 15594 | s_change_sec (int sec) |
252b5132 RH |
15595 | { |
15596 | segT seg; | |
15597 | ||
252b5132 RH |
15598 | #ifdef OBJ_ELF |
15599 | /* The ELF backend needs to know that we are changing sections, so | |
15600 | that .previous works correctly. We could do something like check | |
b6ff326e | 15601 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
15602 | as it would not be appropriate to use it in the section changing |
15603 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
15604 | This should be cleaner, somehow. */ | |
f43abd2b TS |
15605 | if (IS_ELF) |
15606 | obj_elf_section_change_hook (); | |
252b5132 RH |
15607 | #endif |
15608 | ||
7d10b47d | 15609 | mips_emit_delays (); |
6a32d874 | 15610 | |
252b5132 RH |
15611 | switch (sec) |
15612 | { | |
15613 | case 't': | |
15614 | s_text (0); | |
15615 | break; | |
15616 | case 'd': | |
15617 | s_data (0); | |
15618 | break; | |
15619 | case 'b': | |
15620 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
15621 | demand_empty_rest_of_line (); | |
15622 | break; | |
15623 | ||
15624 | case 'r': | |
4d0d148d TS |
15625 | seg = subseg_new (RDATA_SECTION_NAME, |
15626 | (subsegT) get_absolute_expression ()); | |
f43abd2b | 15627 | if (IS_ELF) |
252b5132 | 15628 | { |
4d0d148d TS |
15629 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
15630 | | SEC_READONLY | SEC_RELOC | |
15631 | | SEC_DATA)); | |
c41e87e3 | 15632 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
4d0d148d | 15633 | record_alignment (seg, 4); |
252b5132 | 15634 | } |
4d0d148d | 15635 | demand_empty_rest_of_line (); |
252b5132 RH |
15636 | break; |
15637 | ||
15638 | case 's': | |
4d0d148d | 15639 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
f43abd2b | 15640 | if (IS_ELF) |
252b5132 | 15641 | { |
4d0d148d TS |
15642 | bfd_set_section_flags (stdoutput, seg, |
15643 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
c41e87e3 | 15644 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
4d0d148d | 15645 | record_alignment (seg, 4); |
252b5132 | 15646 | } |
4d0d148d TS |
15647 | demand_empty_rest_of_line (); |
15648 | break; | |
998b3c36 MR |
15649 | |
15650 | case 'B': | |
15651 | seg = subseg_new (".sbss", (subsegT) get_absolute_expression ()); | |
15652 | if (IS_ELF) | |
15653 | { | |
15654 | bfd_set_section_flags (stdoutput, seg, SEC_ALLOC); | |
15655 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
15656 | record_alignment (seg, 4); | |
15657 | } | |
15658 | demand_empty_rest_of_line (); | |
15659 | break; | |
252b5132 RH |
15660 | } |
15661 | ||
15662 | auto_align = 1; | |
15663 | } | |
b34976b6 | 15664 | |
cca86cc8 | 15665 | void |
17a2f251 | 15666 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 15667 | { |
7ed4a06a | 15668 | #ifdef OBJ_ELF |
cca86cc8 SC |
15669 | char *section_name; |
15670 | char c; | |
684022ea | 15671 | char next_c = 0; |
cca86cc8 SC |
15672 | int section_type; |
15673 | int section_flag; | |
15674 | int section_entry_size; | |
15675 | int section_alignment; | |
b34976b6 | 15676 | |
f43abd2b | 15677 | if (!IS_ELF) |
7ed4a06a TS |
15678 | return; |
15679 | ||
cca86cc8 SC |
15680 | section_name = input_line_pointer; |
15681 | c = get_symbol_end (); | |
a816d1ed AO |
15682 | if (c) |
15683 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 15684 | |
4cf0dd0d TS |
15685 | /* Do we have .section Name<,"flags">? */ |
15686 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 15687 | { |
4cf0dd0d TS |
15688 | /* just after name is now '\0'. */ |
15689 | *input_line_pointer = c; | |
cca86cc8 SC |
15690 | input_line_pointer = section_name; |
15691 | obj_elf_section (ignore); | |
15692 | return; | |
15693 | } | |
15694 | input_line_pointer++; | |
15695 | ||
15696 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
15697 | if (c == ',') | |
15698 | section_type = get_absolute_expression (); | |
15699 | else | |
15700 | section_type = 0; | |
15701 | if (*input_line_pointer++ == ',') | |
15702 | section_flag = get_absolute_expression (); | |
15703 | else | |
15704 | section_flag = 0; | |
15705 | if (*input_line_pointer++ == ',') | |
15706 | section_entry_size = get_absolute_expression (); | |
15707 | else | |
15708 | section_entry_size = 0; | |
15709 | if (*input_line_pointer++ == ',') | |
15710 | section_alignment = get_absolute_expression (); | |
15711 | else | |
15712 | section_alignment = 0; | |
87975d2a AM |
15713 | /* FIXME: really ignore? */ |
15714 | (void) section_alignment; | |
cca86cc8 | 15715 | |
a816d1ed AO |
15716 | section_name = xstrdup (section_name); |
15717 | ||
8ab8a5c8 RS |
15718 | /* When using the generic form of .section (as implemented by obj-elf.c), |
15719 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
15720 | traditionally had to fall back on the more common @progbits instead. | |
15721 | ||
15722 | There's nothing really harmful in this, since bfd will correct | |
15723 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
708587a4 | 15724 | means that, for backwards compatibility, the special_section entries |
8ab8a5c8 RS |
15725 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. |
15726 | ||
15727 | Even so, we shouldn't force users of the MIPS .section syntax to | |
15728 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
15729 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
15730 | generic type-checking code. */ | |
15731 | if (section_type == SHT_MIPS_DWARF) | |
15732 | section_type = SHT_PROGBITS; | |
15733 | ||
cca86cc8 SC |
15734 | obj_elf_change_section (section_name, section_type, section_flag, |
15735 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
15736 | |
15737 | if (now_seg->name != section_name) | |
15738 | free (section_name); | |
7ed4a06a | 15739 | #endif /* OBJ_ELF */ |
cca86cc8 | 15740 | } |
252b5132 RH |
15741 | |
15742 | void | |
17a2f251 | 15743 | mips_enable_auto_align (void) |
252b5132 RH |
15744 | { |
15745 | auto_align = 1; | |
15746 | } | |
15747 | ||
15748 | static void | |
17a2f251 | 15749 | s_cons (int log_size) |
252b5132 | 15750 | { |
a8dbcb85 TS |
15751 | segment_info_type *si = seg_info (now_seg); |
15752 | struct insn_label_list *l = si->label_list; | |
252b5132 RH |
15753 | symbolS *label; |
15754 | ||
a8dbcb85 | 15755 | label = l != NULL ? l->label : NULL; |
7d10b47d | 15756 | mips_emit_delays (); |
252b5132 RH |
15757 | if (log_size > 0 && auto_align) |
15758 | mips_align (log_size, 0, label); | |
252b5132 | 15759 | cons (1 << log_size); |
a1facbec | 15760 | mips_clear_insn_labels (); |
252b5132 RH |
15761 | } |
15762 | ||
15763 | static void | |
17a2f251 | 15764 | s_float_cons (int type) |
252b5132 | 15765 | { |
a8dbcb85 TS |
15766 | segment_info_type *si = seg_info (now_seg); |
15767 | struct insn_label_list *l = si->label_list; | |
252b5132 RH |
15768 | symbolS *label; |
15769 | ||
a8dbcb85 | 15770 | label = l != NULL ? l->label : NULL; |
252b5132 | 15771 | |
7d10b47d | 15772 | mips_emit_delays (); |
252b5132 RH |
15773 | |
15774 | if (auto_align) | |
49309057 ILT |
15775 | { |
15776 | if (type == 'd') | |
15777 | mips_align (3, 0, label); | |
15778 | else | |
15779 | mips_align (2, 0, label); | |
15780 | } | |
252b5132 | 15781 | |
252b5132 | 15782 | float_cons (type); |
a1facbec | 15783 | mips_clear_insn_labels (); |
252b5132 RH |
15784 | } |
15785 | ||
15786 | /* Handle .globl. We need to override it because on Irix 5 you are | |
15787 | permitted to say | |
15788 | .globl foo .text | |
15789 | where foo is an undefined symbol, to mean that foo should be | |
15790 | considered to be the address of a function. */ | |
15791 | ||
15792 | static void | |
17a2f251 | 15793 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
15794 | { |
15795 | char *name; | |
15796 | int c; | |
15797 | symbolS *symbolP; | |
15798 | flagword flag; | |
15799 | ||
8a06b769 | 15800 | do |
252b5132 | 15801 | { |
8a06b769 | 15802 | name = input_line_pointer; |
252b5132 | 15803 | c = get_symbol_end (); |
8a06b769 TS |
15804 | symbolP = symbol_find_or_make (name); |
15805 | S_SET_EXTERNAL (symbolP); | |
15806 | ||
252b5132 | 15807 | *input_line_pointer = c; |
8a06b769 | 15808 | SKIP_WHITESPACE (); |
252b5132 | 15809 | |
8a06b769 TS |
15810 | /* On Irix 5, every global symbol that is not explicitly labelled as |
15811 | being a function is apparently labelled as being an object. */ | |
15812 | flag = BSF_OBJECT; | |
252b5132 | 15813 | |
8a06b769 TS |
15814 | if (!is_end_of_line[(unsigned char) *input_line_pointer] |
15815 | && (*input_line_pointer != ',')) | |
15816 | { | |
15817 | char *secname; | |
15818 | asection *sec; | |
15819 | ||
15820 | secname = input_line_pointer; | |
15821 | c = get_symbol_end (); | |
15822 | sec = bfd_get_section_by_name (stdoutput, secname); | |
15823 | if (sec == NULL) | |
15824 | as_bad (_("%s: no such section"), secname); | |
15825 | *input_line_pointer = c; | |
15826 | ||
15827 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
15828 | flag = BSF_FUNCTION; | |
15829 | } | |
15830 | ||
15831 | symbol_get_bfdsym (symbolP)->flags |= flag; | |
15832 | ||
15833 | c = *input_line_pointer; | |
15834 | if (c == ',') | |
15835 | { | |
15836 | input_line_pointer++; | |
15837 | SKIP_WHITESPACE (); | |
15838 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
15839 | c = '\n'; | |
15840 | } | |
15841 | } | |
15842 | while (c == ','); | |
252b5132 | 15843 | |
252b5132 RH |
15844 | demand_empty_rest_of_line (); |
15845 | } | |
15846 | ||
15847 | static void | |
17a2f251 | 15848 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
15849 | { |
15850 | char *opt; | |
15851 | char c; | |
15852 | ||
15853 | opt = input_line_pointer; | |
15854 | c = get_symbol_end (); | |
15855 | ||
15856 | if (*opt == 'O') | |
15857 | { | |
15858 | /* FIXME: What does this mean? */ | |
15859 | } | |
15860 | else if (strncmp (opt, "pic", 3) == 0) | |
15861 | { | |
15862 | int i; | |
15863 | ||
15864 | i = atoi (opt + 3); | |
15865 | if (i == 0) | |
15866 | mips_pic = NO_PIC; | |
15867 | else if (i == 2) | |
143d77c5 | 15868 | { |
252b5132 | 15869 | mips_pic = SVR4_PIC; |
143d77c5 EC |
15870 | mips_abicalls = TRUE; |
15871 | } | |
252b5132 RH |
15872 | else |
15873 | as_bad (_(".option pic%d not supported"), i); | |
15874 | ||
4d0d148d | 15875 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
15876 | { |
15877 | if (g_switch_seen && g_switch_value != 0) | |
15878 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
15879 | g_switch_value = 0; | |
15880 | bfd_set_gp_size (stdoutput, 0); | |
15881 | } | |
15882 | } | |
15883 | else | |
15884 | as_warn (_("Unrecognized option \"%s\""), opt); | |
15885 | ||
15886 | *input_line_pointer = c; | |
15887 | demand_empty_rest_of_line (); | |
15888 | } | |
15889 | ||
15890 | /* This structure is used to hold a stack of .set values. */ | |
15891 | ||
e972090a NC |
15892 | struct mips_option_stack |
15893 | { | |
252b5132 RH |
15894 | struct mips_option_stack *next; |
15895 | struct mips_set_options options; | |
15896 | }; | |
15897 | ||
15898 | static struct mips_option_stack *mips_opts_stack; | |
15899 | ||
15900 | /* Handle the .set pseudo-op. */ | |
15901 | ||
15902 | static void | |
17a2f251 | 15903 | s_mipsset (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
15904 | { |
15905 | char *name = input_line_pointer, ch; | |
15906 | ||
15907 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 15908 | ++input_line_pointer; |
252b5132 RH |
15909 | ch = *input_line_pointer; |
15910 | *input_line_pointer = '\0'; | |
15911 | ||
15912 | if (strcmp (name, "reorder") == 0) | |
15913 | { | |
7d10b47d RS |
15914 | if (mips_opts.noreorder) |
15915 | end_noreorder (); | |
252b5132 RH |
15916 | } |
15917 | else if (strcmp (name, "noreorder") == 0) | |
15918 | { | |
7d10b47d RS |
15919 | if (!mips_opts.noreorder) |
15920 | start_noreorder (); | |
252b5132 | 15921 | } |
741fe287 MR |
15922 | else if (strncmp (name, "at=", 3) == 0) |
15923 | { | |
15924 | char *s = name + 3; | |
15925 | ||
15926 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at)) | |
15927 | as_bad (_("Unrecognized register name `%s'"), s); | |
15928 | } | |
252b5132 RH |
15929 | else if (strcmp (name, "at") == 0) |
15930 | { | |
741fe287 | 15931 | mips_opts.at = ATREG; |
252b5132 RH |
15932 | } |
15933 | else if (strcmp (name, "noat") == 0) | |
15934 | { | |
741fe287 | 15935 | mips_opts.at = ZERO; |
252b5132 RH |
15936 | } |
15937 | else if (strcmp (name, "macro") == 0) | |
15938 | { | |
15939 | mips_opts.warn_about_macros = 0; | |
15940 | } | |
15941 | else if (strcmp (name, "nomacro") == 0) | |
15942 | { | |
15943 | if (mips_opts.noreorder == 0) | |
15944 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
15945 | mips_opts.warn_about_macros = 1; | |
15946 | } | |
15947 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
15948 | { | |
15949 | mips_opts.nomove = 0; | |
15950 | } | |
15951 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
15952 | { | |
15953 | mips_opts.nomove = 1; | |
15954 | } | |
15955 | else if (strcmp (name, "bopt") == 0) | |
15956 | { | |
15957 | mips_opts.nobopt = 0; | |
15958 | } | |
15959 | else if (strcmp (name, "nobopt") == 0) | |
15960 | { | |
15961 | mips_opts.nobopt = 1; | |
15962 | } | |
ad3fea08 TS |
15963 | else if (strcmp (name, "gp=default") == 0) |
15964 | mips_opts.gp32 = file_mips_gp32; | |
15965 | else if (strcmp (name, "gp=32") == 0) | |
15966 | mips_opts.gp32 = 1; | |
15967 | else if (strcmp (name, "gp=64") == 0) | |
15968 | { | |
15969 | if (!ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
20203fb9 | 15970 | as_warn (_("%s isa does not support 64-bit registers"), |
ad3fea08 TS |
15971 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
15972 | mips_opts.gp32 = 0; | |
15973 | } | |
15974 | else if (strcmp (name, "fp=default") == 0) | |
15975 | mips_opts.fp32 = file_mips_fp32; | |
15976 | else if (strcmp (name, "fp=32") == 0) | |
15977 | mips_opts.fp32 = 1; | |
15978 | else if (strcmp (name, "fp=64") == 0) | |
15979 | { | |
15980 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
20203fb9 | 15981 | as_warn (_("%s isa does not support 64-bit floating point registers"), |
ad3fea08 TS |
15982 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
15983 | mips_opts.fp32 = 0; | |
15984 | } | |
037b32b9 AN |
15985 | else if (strcmp (name, "softfloat") == 0) |
15986 | mips_opts.soft_float = 1; | |
15987 | else if (strcmp (name, "hardfloat") == 0) | |
15988 | mips_opts.soft_float = 0; | |
15989 | else if (strcmp (name, "singlefloat") == 0) | |
15990 | mips_opts.single_float = 1; | |
15991 | else if (strcmp (name, "doublefloat") == 0) | |
15992 | mips_opts.single_float = 0; | |
252b5132 RH |
15993 | else if (strcmp (name, "mips16") == 0 |
15994 | || strcmp (name, "MIPS-16") == 0) | |
df58fc94 RS |
15995 | { |
15996 | if (mips_opts.micromips == 1) | |
15997 | as_fatal (_("`mips16' cannot be used with `micromips'")); | |
15998 | mips_opts.mips16 = 1; | |
15999 | } | |
252b5132 RH |
16000 | else if (strcmp (name, "nomips16") == 0 |
16001 | || strcmp (name, "noMIPS-16") == 0) | |
16002 | mips_opts.mips16 = 0; | |
df58fc94 RS |
16003 | else if (strcmp (name, "micromips") == 0) |
16004 | { | |
16005 | if (mips_opts.mips16 == 1) | |
16006 | as_fatal (_("`micromips' cannot be used with `mips16'")); | |
16007 | mips_opts.micromips = 1; | |
16008 | } | |
16009 | else if (strcmp (name, "nomicromips") == 0) | |
16010 | mips_opts.micromips = 0; | |
e16bfa71 TS |
16011 | else if (strcmp (name, "smartmips") == 0) |
16012 | { | |
ad3fea08 | 16013 | if (!ISA_SUPPORTS_SMARTMIPS) |
20203fb9 | 16014 | as_warn (_("%s ISA does not support SmartMIPS ASE"), |
e16bfa71 TS |
16015 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16016 | mips_opts.ase_smartmips = 1; | |
16017 | } | |
16018 | else if (strcmp (name, "nosmartmips") == 0) | |
16019 | mips_opts.ase_smartmips = 0; | |
1f25f5d3 CD |
16020 | else if (strcmp (name, "mips3d") == 0) |
16021 | mips_opts.ase_mips3d = 1; | |
16022 | else if (strcmp (name, "nomips3d") == 0) | |
16023 | mips_opts.ase_mips3d = 0; | |
a4672219 TS |
16024 | else if (strcmp (name, "mdmx") == 0) |
16025 | mips_opts.ase_mdmx = 1; | |
16026 | else if (strcmp (name, "nomdmx") == 0) | |
16027 | mips_opts.ase_mdmx = 0; | |
74cd071d | 16028 | else if (strcmp (name, "dsp") == 0) |
ad3fea08 TS |
16029 | { |
16030 | if (!ISA_SUPPORTS_DSP_ASE) | |
20203fb9 | 16031 | as_warn (_("%s ISA does not support DSP ASE"), |
ad3fea08 TS |
16032 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16033 | mips_opts.ase_dsp = 1; | |
8b082fb1 | 16034 | mips_opts.ase_dspr2 = 0; |
ad3fea08 | 16035 | } |
74cd071d | 16036 | else if (strcmp (name, "nodsp") == 0) |
8b082fb1 TS |
16037 | { |
16038 | mips_opts.ase_dsp = 0; | |
16039 | mips_opts.ase_dspr2 = 0; | |
16040 | } | |
16041 | else if (strcmp (name, "dspr2") == 0) | |
16042 | { | |
16043 | if (!ISA_SUPPORTS_DSPR2_ASE) | |
20203fb9 | 16044 | as_warn (_("%s ISA does not support DSP R2 ASE"), |
8b082fb1 TS |
16045 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16046 | mips_opts.ase_dspr2 = 1; | |
16047 | mips_opts.ase_dsp = 1; | |
16048 | } | |
16049 | else if (strcmp (name, "nodspr2") == 0) | |
16050 | { | |
16051 | mips_opts.ase_dspr2 = 0; | |
16052 | mips_opts.ase_dsp = 0; | |
16053 | } | |
ef2e4d86 | 16054 | else if (strcmp (name, "mt") == 0) |
ad3fea08 TS |
16055 | { |
16056 | if (!ISA_SUPPORTS_MT_ASE) | |
20203fb9 | 16057 | as_warn (_("%s ISA does not support MT ASE"), |
ad3fea08 TS |
16058 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16059 | mips_opts.ase_mt = 1; | |
16060 | } | |
ef2e4d86 CF |
16061 | else if (strcmp (name, "nomt") == 0) |
16062 | mips_opts.ase_mt = 0; | |
1a2c1fad | 16063 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 16064 | { |
af7ee8bf | 16065 | int reset = 0; |
252b5132 | 16066 | |
1a2c1fad CD |
16067 | /* Permit the user to change the ISA and architecture on the fly. |
16068 | Needless to say, misuse can cause serious problems. */ | |
81a21e38 | 16069 | if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) |
af7ee8bf CD |
16070 | { |
16071 | reset = 1; | |
16072 | mips_opts.isa = file_mips_isa; | |
1a2c1fad | 16073 | mips_opts.arch = file_mips_arch; |
1a2c1fad CD |
16074 | } |
16075 | else if (strncmp (name, "arch=", 5) == 0) | |
16076 | { | |
16077 | const struct mips_cpu_info *p; | |
16078 | ||
16079 | p = mips_parse_cpu("internal use", name + 5); | |
16080 | if (!p) | |
16081 | as_bad (_("unknown architecture %s"), name + 5); | |
16082 | else | |
16083 | { | |
16084 | mips_opts.arch = p->cpu; | |
16085 | mips_opts.isa = p->isa; | |
16086 | } | |
16087 | } | |
81a21e38 TS |
16088 | else if (strncmp (name, "mips", 4) == 0) |
16089 | { | |
16090 | const struct mips_cpu_info *p; | |
16091 | ||
16092 | p = mips_parse_cpu("internal use", name); | |
16093 | if (!p) | |
16094 | as_bad (_("unknown ISA level %s"), name + 4); | |
16095 | else | |
16096 | { | |
16097 | mips_opts.arch = p->cpu; | |
16098 | mips_opts.isa = p->isa; | |
16099 | } | |
16100 | } | |
af7ee8bf | 16101 | else |
81a21e38 | 16102 | as_bad (_("unknown ISA or architecture %s"), name); |
af7ee8bf CD |
16103 | |
16104 | switch (mips_opts.isa) | |
98d3f06f KH |
16105 | { |
16106 | case 0: | |
98d3f06f | 16107 | break; |
af7ee8bf CD |
16108 | case ISA_MIPS1: |
16109 | case ISA_MIPS2: | |
16110 | case ISA_MIPS32: | |
16111 | case ISA_MIPS32R2: | |
98d3f06f KH |
16112 | mips_opts.gp32 = 1; |
16113 | mips_opts.fp32 = 1; | |
16114 | break; | |
af7ee8bf CD |
16115 | case ISA_MIPS3: |
16116 | case ISA_MIPS4: | |
16117 | case ISA_MIPS5: | |
16118 | case ISA_MIPS64: | |
5f74bc13 | 16119 | case ISA_MIPS64R2: |
98d3f06f KH |
16120 | mips_opts.gp32 = 0; |
16121 | mips_opts.fp32 = 0; | |
16122 | break; | |
16123 | default: | |
16124 | as_bad (_("unknown ISA level %s"), name + 4); | |
16125 | break; | |
16126 | } | |
af7ee8bf | 16127 | if (reset) |
98d3f06f | 16128 | { |
af7ee8bf CD |
16129 | mips_opts.gp32 = file_mips_gp32; |
16130 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 16131 | } |
252b5132 RH |
16132 | } |
16133 | else if (strcmp (name, "autoextend") == 0) | |
16134 | mips_opts.noautoextend = 0; | |
16135 | else if (strcmp (name, "noautoextend") == 0) | |
16136 | mips_opts.noautoextend = 1; | |
16137 | else if (strcmp (name, "push") == 0) | |
16138 | { | |
16139 | struct mips_option_stack *s; | |
16140 | ||
16141 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
16142 | s->next = mips_opts_stack; | |
16143 | s->options = mips_opts; | |
16144 | mips_opts_stack = s; | |
16145 | } | |
16146 | else if (strcmp (name, "pop") == 0) | |
16147 | { | |
16148 | struct mips_option_stack *s; | |
16149 | ||
16150 | s = mips_opts_stack; | |
16151 | if (s == NULL) | |
16152 | as_bad (_(".set pop with no .set push")); | |
16153 | else | |
16154 | { | |
16155 | /* If we're changing the reorder mode we need to handle | |
16156 | delay slots correctly. */ | |
16157 | if (s->options.noreorder && ! mips_opts.noreorder) | |
7d10b47d | 16158 | start_noreorder (); |
252b5132 | 16159 | else if (! s->options.noreorder && mips_opts.noreorder) |
7d10b47d | 16160 | end_noreorder (); |
252b5132 RH |
16161 | |
16162 | mips_opts = s->options; | |
16163 | mips_opts_stack = s->next; | |
16164 | free (s); | |
16165 | } | |
16166 | } | |
aed1a261 RS |
16167 | else if (strcmp (name, "sym32") == 0) |
16168 | mips_opts.sym32 = TRUE; | |
16169 | else if (strcmp (name, "nosym32") == 0) | |
16170 | mips_opts.sym32 = FALSE; | |
e6559e01 JM |
16171 | else if (strchr (name, ',')) |
16172 | { | |
16173 | /* Generic ".set" directive; use the generic handler. */ | |
16174 | *input_line_pointer = ch; | |
16175 | input_line_pointer = name; | |
16176 | s_set (0); | |
16177 | return; | |
16178 | } | |
252b5132 RH |
16179 | else |
16180 | { | |
16181 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
16182 | } | |
16183 | *input_line_pointer = ch; | |
16184 | demand_empty_rest_of_line (); | |
16185 | } | |
16186 | ||
16187 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
16188 | .option pic2. It means to generate SVR4 PIC calls. */ | |
16189 | ||
16190 | static void | |
17a2f251 | 16191 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16192 | { |
16193 | mips_pic = SVR4_PIC; | |
143d77c5 | 16194 | mips_abicalls = TRUE; |
4d0d148d TS |
16195 | |
16196 | if (g_switch_seen && g_switch_value != 0) | |
16197 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
16198 | g_switch_value = 0; | |
16199 | ||
252b5132 RH |
16200 | bfd_set_gp_size (stdoutput, 0); |
16201 | demand_empty_rest_of_line (); | |
16202 | } | |
16203 | ||
16204 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
16205 | PIC code. It sets the $gp register for the function based on the | |
16206 | function address, which is in the register named in the argument. | |
16207 | This uses a relocation against _gp_disp, which is handled specially | |
16208 | by the linker. The result is: | |
16209 | lui $gp,%hi(_gp_disp) | |
16210 | addiu $gp,$gp,%lo(_gp_disp) | |
16211 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
16212 | The .cpload argument is normally $25 == $t9. |
16213 | ||
16214 | The -mno-shared option changes this to: | |
bbe506e8 TS |
16215 | lui $gp,%hi(__gnu_local_gp) |
16216 | addiu $gp,$gp,%lo(__gnu_local_gp) | |
aa6975fb ILT |
16217 | and the argument is ignored. This saves an instruction, but the |
16218 | resulting code is not position independent; it uses an absolute | |
bbe506e8 TS |
16219 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
16220 | can go into an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
16221 | |
16222 | static void | |
17a2f251 | 16223 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16224 | { |
16225 | expressionS ex; | |
aa6975fb ILT |
16226 | int reg; |
16227 | int in_shared; | |
252b5132 | 16228 | |
6478892d TS |
16229 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
16230 | .cpload is ignored. */ | |
16231 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
16232 | { |
16233 | s_ignore (0); | |
16234 | return; | |
16235 | } | |
16236 | ||
d3ecfc59 | 16237 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
16238 | if (mips_opts.noreorder == 0) |
16239 | as_warn (_(".cpload not in noreorder section")); | |
16240 | ||
aa6975fb ILT |
16241 | reg = tc_get_register (0); |
16242 | ||
16243 | /* If we need to produce a 64-bit address, we are better off using | |
16244 | the default instruction sequence. */ | |
aed1a261 | 16245 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
aa6975fb | 16246 | |
252b5132 | 16247 | ex.X_op = O_symbol; |
bbe506e8 TS |
16248 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
16249 | "__gnu_local_gp"); | |
252b5132 RH |
16250 | ex.X_op_symbol = NULL; |
16251 | ex.X_add_number = 0; | |
16252 | ||
16253 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 16254 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 16255 | |
584892a6 | 16256 | macro_start (); |
67c0d1eb RS |
16257 | macro_build_lui (&ex, mips_gp_register); |
16258 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 16259 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
16260 | if (in_shared) |
16261 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
16262 | mips_gp_register, reg); | |
584892a6 | 16263 | macro_end (); |
252b5132 RH |
16264 | |
16265 | demand_empty_rest_of_line (); | |
16266 | } | |
16267 | ||
6478892d TS |
16268 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
16269 | .cpsetup $reg1, offset|$reg2, label | |
16270 | ||
16271 | If offset is given, this results in: | |
16272 | sd $gp, offset($sp) | |
956cd1d6 | 16273 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
16274 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
16275 | daddu $gp, $gp, $reg1 | |
6478892d TS |
16276 | |
16277 | If $reg2 is given, this results in: | |
16278 | daddu $reg2, $gp, $0 | |
956cd1d6 | 16279 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
16280 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
16281 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
16282 | $reg1 is normally $25 == $t9. |
16283 | ||
16284 | The -mno-shared option replaces the last three instructions with | |
16285 | lui $gp,%hi(_gp) | |
54f4ddb3 | 16286 | addiu $gp,$gp,%lo(_gp) */ |
aa6975fb | 16287 | |
6478892d | 16288 | static void |
17a2f251 | 16289 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16290 | { |
16291 | expressionS ex_off; | |
16292 | expressionS ex_sym; | |
16293 | int reg1; | |
6478892d | 16294 | |
8586fc66 | 16295 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
16296 | We also need NewABI support. */ |
16297 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16298 | { | |
16299 | s_ignore (0); | |
16300 | return; | |
16301 | } | |
16302 | ||
16303 | reg1 = tc_get_register (0); | |
16304 | SKIP_WHITESPACE (); | |
16305 | if (*input_line_pointer != ',') | |
16306 | { | |
16307 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
16308 | return; | |
16309 | } | |
16310 | else | |
80245285 | 16311 | ++input_line_pointer; |
6478892d TS |
16312 | SKIP_WHITESPACE (); |
16313 | if (*input_line_pointer == '$') | |
80245285 TS |
16314 | { |
16315 | mips_cpreturn_register = tc_get_register (0); | |
16316 | mips_cpreturn_offset = -1; | |
16317 | } | |
6478892d | 16318 | else |
80245285 TS |
16319 | { |
16320 | mips_cpreturn_offset = get_absolute_expression (); | |
16321 | mips_cpreturn_register = -1; | |
16322 | } | |
6478892d TS |
16323 | SKIP_WHITESPACE (); |
16324 | if (*input_line_pointer != ',') | |
16325 | { | |
16326 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
16327 | return; | |
16328 | } | |
16329 | else | |
f9419b05 | 16330 | ++input_line_pointer; |
6478892d | 16331 | SKIP_WHITESPACE (); |
f21f8242 | 16332 | expression (&ex_sym); |
6478892d | 16333 | |
584892a6 | 16334 | macro_start (); |
6478892d TS |
16335 | if (mips_cpreturn_register == -1) |
16336 | { | |
16337 | ex_off.X_op = O_constant; | |
16338 | ex_off.X_add_symbol = NULL; | |
16339 | ex_off.X_op_symbol = NULL; | |
16340 | ex_off.X_add_number = mips_cpreturn_offset; | |
16341 | ||
67c0d1eb | 16342 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 16343 | BFD_RELOC_LO16, SP); |
6478892d TS |
16344 | } |
16345 | else | |
67c0d1eb | 16346 | macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, |
17a2f251 | 16347 | mips_gp_register, 0); |
6478892d | 16348 | |
aed1a261 | 16349 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
aa6975fb | 16350 | { |
df58fc94 | 16351 | macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register, |
aa6975fb ILT |
16352 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, |
16353 | BFD_RELOC_HI16_S); | |
16354 | ||
16355 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
16356 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
16357 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
16358 | ||
16359 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
16360 | mips_gp_register, reg1); | |
16361 | } | |
16362 | else | |
16363 | { | |
16364 | expressionS ex; | |
16365 | ||
16366 | ex.X_op = O_symbol; | |
4184909a | 16367 | ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); |
aa6975fb ILT |
16368 | ex.X_op_symbol = NULL; |
16369 | ex.X_add_number = 0; | |
6e1304d8 | 16370 | |
aa6975fb ILT |
16371 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
16372 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
16373 | ||
16374 | macro_build_lui (&ex, mips_gp_register); | |
16375 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
16376 | mips_gp_register, BFD_RELOC_LO16); | |
16377 | } | |
f21f8242 | 16378 | |
584892a6 | 16379 | macro_end (); |
6478892d TS |
16380 | |
16381 | demand_empty_rest_of_line (); | |
16382 | } | |
16383 | ||
16384 | static void | |
17a2f251 | 16385 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16386 | { |
16387 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
54f4ddb3 | 16388 | .cplocal is ignored. */ |
6478892d TS |
16389 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) |
16390 | { | |
16391 | s_ignore (0); | |
16392 | return; | |
16393 | } | |
16394 | ||
16395 | mips_gp_register = tc_get_register (0); | |
85b51719 | 16396 | demand_empty_rest_of_line (); |
6478892d TS |
16397 | } |
16398 | ||
252b5132 RH |
16399 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
16400 | offset from $sp. The offset is remembered, and after making a PIC | |
16401 | call $gp is restored from that location. */ | |
16402 | ||
16403 | static void | |
17a2f251 | 16404 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16405 | { |
16406 | expressionS ex; | |
252b5132 | 16407 | |
6478892d | 16408 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 16409 | .cprestore is ignored. */ |
6478892d | 16410 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
16411 | { |
16412 | s_ignore (0); | |
16413 | return; | |
16414 | } | |
16415 | ||
16416 | mips_cprestore_offset = get_absolute_expression (); | |
7a621144 | 16417 | mips_cprestore_valid = 1; |
252b5132 RH |
16418 | |
16419 | ex.X_op = O_constant; | |
16420 | ex.X_add_symbol = NULL; | |
16421 | ex.X_op_symbol = NULL; | |
16422 | ex.X_add_number = mips_cprestore_offset; | |
16423 | ||
584892a6 | 16424 | macro_start (); |
67c0d1eb RS |
16425 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
16426 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 16427 | macro_end (); |
252b5132 RH |
16428 | |
16429 | demand_empty_rest_of_line (); | |
16430 | } | |
16431 | ||
6478892d | 16432 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 16433 | was given in the preceding .cpsetup, it results in: |
6478892d | 16434 | ld $gp, offset($sp) |
76b3015f | 16435 | |
6478892d | 16436 | If a register $reg2 was given there, it results in: |
54f4ddb3 TS |
16437 | daddu $gp, $reg2, $0 */ |
16438 | ||
6478892d | 16439 | static void |
17a2f251 | 16440 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16441 | { |
16442 | expressionS ex; | |
6478892d TS |
16443 | |
16444 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
16445 | We also need NewABI support. */ | |
16446 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16447 | { | |
16448 | s_ignore (0); | |
16449 | return; | |
16450 | } | |
16451 | ||
584892a6 | 16452 | macro_start (); |
6478892d TS |
16453 | if (mips_cpreturn_register == -1) |
16454 | { | |
16455 | ex.X_op = O_constant; | |
16456 | ex.X_add_symbol = NULL; | |
16457 | ex.X_op_symbol = NULL; | |
16458 | ex.X_add_number = mips_cpreturn_offset; | |
16459 | ||
67c0d1eb | 16460 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
16461 | } |
16462 | else | |
67c0d1eb | 16463 | macro_build (NULL, "daddu", "d,v,t", mips_gp_register, |
17a2f251 | 16464 | mips_cpreturn_register, 0); |
584892a6 | 16465 | macro_end (); |
6478892d TS |
16466 | |
16467 | demand_empty_rest_of_line (); | |
16468 | } | |
16469 | ||
741d6ea8 JM |
16470 | /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate |
16471 | a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for | |
16472 | use in DWARF debug information. */ | |
16473 | ||
16474 | static void | |
16475 | s_dtprel_internal (size_t bytes) | |
16476 | { | |
16477 | expressionS ex; | |
16478 | char *p; | |
16479 | ||
16480 | expression (&ex); | |
16481 | ||
16482 | if (ex.X_op != O_symbol) | |
16483 | { | |
16484 | as_bad (_("Unsupported use of %s"), (bytes == 8 | |
16485 | ? ".dtpreldword" | |
16486 | : ".dtprelword")); | |
16487 | ignore_rest_of_line (); | |
16488 | } | |
16489 | ||
16490 | p = frag_more (bytes); | |
16491 | md_number_to_chars (p, 0, bytes); | |
16492 | fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, | |
16493 | (bytes == 8 | |
16494 | ? BFD_RELOC_MIPS_TLS_DTPREL64 | |
16495 | : BFD_RELOC_MIPS_TLS_DTPREL32)); | |
16496 | ||
16497 | demand_empty_rest_of_line (); | |
16498 | } | |
16499 | ||
16500 | /* Handle .dtprelword. */ | |
16501 | ||
16502 | static void | |
16503 | s_dtprelword (int ignore ATTRIBUTE_UNUSED) | |
16504 | { | |
16505 | s_dtprel_internal (4); | |
16506 | } | |
16507 | ||
16508 | /* Handle .dtpreldword. */ | |
16509 | ||
16510 | static void | |
16511 | s_dtpreldword (int ignore ATTRIBUTE_UNUSED) | |
16512 | { | |
16513 | s_dtprel_internal (8); | |
16514 | } | |
16515 | ||
6478892d TS |
16516 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC |
16517 | code. It sets the offset to use in gp_rel relocations. */ | |
16518 | ||
16519 | static void | |
17a2f251 | 16520 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16521 | { |
16522 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
16523 | We also need NewABI support. */ | |
16524 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16525 | { | |
16526 | s_ignore (0); | |
16527 | return; | |
16528 | } | |
16529 | ||
def2e0dd | 16530 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
16531 | |
16532 | demand_empty_rest_of_line (); | |
16533 | } | |
16534 | ||
252b5132 RH |
16535 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
16536 | code. It generates a 32 bit GP relative reloc. */ | |
16537 | ||
16538 | static void | |
17a2f251 | 16539 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 16540 | { |
a8dbcb85 TS |
16541 | segment_info_type *si; |
16542 | struct insn_label_list *l; | |
252b5132 RH |
16543 | symbolS *label; |
16544 | expressionS ex; | |
16545 | char *p; | |
16546 | ||
16547 | /* When not generating PIC code, this is treated as .word. */ | |
16548 | if (mips_pic != SVR4_PIC) | |
16549 | { | |
16550 | s_cons (2); | |
16551 | return; | |
16552 | } | |
16553 | ||
a8dbcb85 TS |
16554 | si = seg_info (now_seg); |
16555 | l = si->label_list; | |
16556 | label = l != NULL ? l->label : NULL; | |
7d10b47d | 16557 | mips_emit_delays (); |
252b5132 RH |
16558 | if (auto_align) |
16559 | mips_align (2, 0, label); | |
252b5132 RH |
16560 | |
16561 | expression (&ex); | |
a1facbec | 16562 | mips_clear_insn_labels (); |
252b5132 RH |
16563 | |
16564 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
16565 | { | |
16566 | as_bad (_("Unsupported use of .gpword")); | |
16567 | ignore_rest_of_line (); | |
16568 | } | |
16569 | ||
16570 | p = frag_more (4); | |
17a2f251 | 16571 | md_number_to_chars (p, 0, 4); |
b34976b6 | 16572 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 16573 | BFD_RELOC_GPREL32); |
252b5132 RH |
16574 | |
16575 | demand_empty_rest_of_line (); | |
16576 | } | |
16577 | ||
10181a0d | 16578 | static void |
17a2f251 | 16579 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d | 16580 | { |
a8dbcb85 TS |
16581 | segment_info_type *si; |
16582 | struct insn_label_list *l; | |
10181a0d AO |
16583 | symbolS *label; |
16584 | expressionS ex; | |
16585 | char *p; | |
16586 | ||
16587 | /* When not generating PIC code, this is treated as .dword. */ | |
16588 | if (mips_pic != SVR4_PIC) | |
16589 | { | |
16590 | s_cons (3); | |
16591 | return; | |
16592 | } | |
16593 | ||
a8dbcb85 TS |
16594 | si = seg_info (now_seg); |
16595 | l = si->label_list; | |
16596 | label = l != NULL ? l->label : NULL; | |
7d10b47d | 16597 | mips_emit_delays (); |
10181a0d AO |
16598 | if (auto_align) |
16599 | mips_align (3, 0, label); | |
10181a0d AO |
16600 | |
16601 | expression (&ex); | |
a1facbec | 16602 | mips_clear_insn_labels (); |
10181a0d AO |
16603 | |
16604 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
16605 | { | |
16606 | as_bad (_("Unsupported use of .gpdword")); | |
16607 | ignore_rest_of_line (); | |
16608 | } | |
16609 | ||
16610 | p = frag_more (8); | |
17a2f251 | 16611 | md_number_to_chars (p, 0, 8); |
a105a300 | 16612 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 16613 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
16614 | |
16615 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
16616 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
16617 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
16618 | |
16619 | demand_empty_rest_of_line (); | |
16620 | } | |
16621 | ||
252b5132 RH |
16622 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
16623 | tables in SVR4 PIC code. */ | |
16624 | ||
16625 | static void | |
17a2f251 | 16626 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 16627 | { |
252b5132 RH |
16628 | int reg; |
16629 | ||
10181a0d AO |
16630 | /* This is ignored when not generating SVR4 PIC code. */ |
16631 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
16632 | { |
16633 | s_ignore (0); | |
16634 | return; | |
16635 | } | |
16636 | ||
16637 | /* Add $gp to the register named as an argument. */ | |
584892a6 | 16638 | macro_start (); |
252b5132 | 16639 | reg = tc_get_register (0); |
67c0d1eb | 16640 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 16641 | macro_end (); |
252b5132 | 16642 | |
bdaaa2e1 | 16643 | demand_empty_rest_of_line (); |
252b5132 RH |
16644 | } |
16645 | ||
16646 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
df58fc94 | 16647 | mips16/micromips mode. This permits the linker to handle them specially, |
252b5132 RH |
16648 | such as generating jalx instructions when needed. We also make |
16649 | them odd for the duration of the assembly, in order to generate the | |
16650 | right sort of code. We will make them even in the adjust_symtab | |
16651 | routine, while leaving them marked. This is convenient for the | |
16652 | debugger and the disassembler. The linker knows to make them odd | |
16653 | again. */ | |
16654 | ||
16655 | static void | |
17a2f251 | 16656 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 16657 | { |
df58fc94 | 16658 | mips_mark_labels (); |
252b5132 RH |
16659 | |
16660 | demand_empty_rest_of_line (); | |
16661 | } | |
16662 | ||
16663 | /* Handle a .stabn directive. We need these in order to mark a label | |
16664 | as being a mips16 text label correctly. Sometimes the compiler | |
16665 | will emit a label, followed by a .stabn, and then switch sections. | |
16666 | If the label and .stabn are in mips16 mode, then the label is | |
16667 | really a mips16 text label. */ | |
16668 | ||
16669 | static void | |
17a2f251 | 16670 | s_mips_stab (int type) |
252b5132 | 16671 | { |
f9419b05 | 16672 | if (type == 'n') |
df58fc94 | 16673 | mips_mark_labels (); |
252b5132 RH |
16674 | |
16675 | s_stab (type); | |
16676 | } | |
16677 | ||
54f4ddb3 | 16678 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */ |
252b5132 RH |
16679 | |
16680 | static void | |
17a2f251 | 16681 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16682 | { |
16683 | char *name; | |
16684 | int c; | |
16685 | symbolS *symbolP; | |
16686 | expressionS exp; | |
16687 | ||
16688 | name = input_line_pointer; | |
16689 | c = get_symbol_end (); | |
16690 | symbolP = symbol_find_or_make (name); | |
16691 | S_SET_WEAK (symbolP); | |
16692 | *input_line_pointer = c; | |
16693 | ||
16694 | SKIP_WHITESPACE (); | |
16695 | ||
16696 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
16697 | { | |
16698 | if (S_IS_DEFINED (symbolP)) | |
16699 | { | |
20203fb9 | 16700 | as_bad (_("ignoring attempt to redefine symbol %s"), |
252b5132 RH |
16701 | S_GET_NAME (symbolP)); |
16702 | ignore_rest_of_line (); | |
16703 | return; | |
16704 | } | |
bdaaa2e1 | 16705 | |
252b5132 RH |
16706 | if (*input_line_pointer == ',') |
16707 | { | |
16708 | ++input_line_pointer; | |
16709 | SKIP_WHITESPACE (); | |
16710 | } | |
bdaaa2e1 | 16711 | |
252b5132 RH |
16712 | expression (&exp); |
16713 | if (exp.X_op != O_symbol) | |
16714 | { | |
20203fb9 | 16715 | as_bad (_("bad .weakext directive")); |
98d3f06f | 16716 | ignore_rest_of_line (); |
252b5132 RH |
16717 | return; |
16718 | } | |
49309057 | 16719 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
16720 | } |
16721 | ||
16722 | demand_empty_rest_of_line (); | |
16723 | } | |
16724 | ||
16725 | /* Parse a register string into a number. Called from the ECOFF code | |
16726 | to parse .frame. The argument is non-zero if this is the frame | |
16727 | register, so that we can record it in mips_frame_reg. */ | |
16728 | ||
16729 | int | |
17a2f251 | 16730 | tc_get_register (int frame) |
252b5132 | 16731 | { |
707bfff6 | 16732 | unsigned int reg; |
252b5132 RH |
16733 | |
16734 | SKIP_WHITESPACE (); | |
707bfff6 TS |
16735 | if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®)) |
16736 | reg = 0; | |
252b5132 | 16737 | if (frame) |
7a621144 DJ |
16738 | { |
16739 | mips_frame_reg = reg != 0 ? reg : SP; | |
16740 | mips_frame_reg_valid = 1; | |
16741 | mips_cprestore_valid = 0; | |
16742 | } | |
252b5132 RH |
16743 | return reg; |
16744 | } | |
16745 | ||
16746 | valueT | |
17a2f251 | 16747 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
16748 | { |
16749 | int align = bfd_get_section_alignment (stdoutput, seg); | |
16750 | ||
b4c71f56 TS |
16751 | if (IS_ELF) |
16752 | { | |
16753 | /* We don't need to align ELF sections to the full alignment. | |
16754 | However, Irix 5 may prefer that we align them at least to a 16 | |
16755 | byte boundary. We don't bother to align the sections if we | |
16756 | are targeted for an embedded system. */ | |
c41e87e3 | 16757 | if (strncmp (TARGET_OS, "elf", 3) == 0) |
b4c71f56 TS |
16758 | return addr; |
16759 | if (align > 4) | |
16760 | align = 4; | |
16761 | } | |
252b5132 RH |
16762 | |
16763 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
16764 | } | |
16765 | ||
16766 | /* Utility routine, called from above as well. If called while the | |
16767 | input file is still being read, it's only an approximation. (For | |
16768 | example, a symbol may later become defined which appeared to be | |
16769 | undefined earlier.) */ | |
16770 | ||
16771 | static int | |
17a2f251 | 16772 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
16773 | { |
16774 | if (sym == 0) | |
16775 | return 0; | |
16776 | ||
4d0d148d | 16777 | if (g_switch_value > 0) |
252b5132 RH |
16778 | { |
16779 | const char *symname; | |
16780 | int change; | |
16781 | ||
c9914766 | 16782 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
16783 | register. It can be if it is smaller than the -G size or if |
16784 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 16785 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
16786 | they can. */ |
16787 | symname = S_GET_NAME (sym); | |
16788 | if (symname != (const char *) NULL | |
16789 | && (strcmp (symname, "eprol") == 0 | |
16790 | || strcmp (symname, "etext") == 0 | |
16791 | || strcmp (symname, "_gp") == 0 | |
16792 | || strcmp (symname, "edata") == 0 | |
16793 | || strcmp (symname, "_fbss") == 0 | |
16794 | || strcmp (symname, "_fdata") == 0 | |
16795 | || strcmp (symname, "_ftext") == 0 | |
16796 | || strcmp (symname, "end") == 0 | |
16797 | || strcmp (symname, "_gp_disp") == 0)) | |
16798 | change = 1; | |
16799 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
16800 | && (0 | |
16801 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
16802 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
16803 | && (symbol_get_obj (sym)->ecoff_extern_size | |
16804 | <= g_switch_value)) | |
252b5132 RH |
16805 | #endif |
16806 | /* We must defer this decision until after the whole | |
16807 | file has been read, since there might be a .extern | |
16808 | after the first use of this symbol. */ | |
16809 | || (before_relaxing | |
16810 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 16811 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
16812 | #endif |
16813 | && S_GET_VALUE (sym) == 0) | |
16814 | || (S_GET_VALUE (sym) != 0 | |
16815 | && S_GET_VALUE (sym) <= g_switch_value))) | |
16816 | change = 0; | |
16817 | else | |
16818 | { | |
16819 | const char *segname; | |
16820 | ||
16821 | segname = segment_name (S_GET_SEGMENT (sym)); | |
9c2799c2 | 16822 | gas_assert (strcmp (segname, ".lit8") != 0 |
252b5132 RH |
16823 | && strcmp (segname, ".lit4") != 0); |
16824 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
16825 | && strcmp (segname, ".sbss") != 0 |
16826 | && strncmp (segname, ".sdata.", 7) != 0 | |
d4dc2f22 TS |
16827 | && strncmp (segname, ".sbss.", 6) != 0 |
16828 | && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0 | |
fba2b7f9 | 16829 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); |
252b5132 RH |
16830 | } |
16831 | return change; | |
16832 | } | |
16833 | else | |
c9914766 | 16834 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
16835 | return 1; |
16836 | } | |
16837 | ||
5919d012 RS |
16838 | |
16839 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
16840 | ||
16841 | static bfd_boolean | |
17a2f251 | 16842 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
16843 | { |
16844 | asection *symsec; | |
5919d012 RS |
16845 | |
16846 | /* Handle the case of a symbol equated to another symbol. */ | |
16847 | while (symbol_equated_reloc_p (sym)) | |
16848 | { | |
16849 | symbolS *n; | |
16850 | ||
5f0fe04b | 16851 | /* It's possible to get a loop here in a badly written program. */ |
5919d012 RS |
16852 | n = symbol_get_value_expression (sym)->X_add_symbol; |
16853 | if (n == sym) | |
16854 | break; | |
16855 | sym = n; | |
16856 | } | |
16857 | ||
df1f3cda DD |
16858 | if (symbol_section_p (sym)) |
16859 | return TRUE; | |
16860 | ||
5919d012 RS |
16861 | symsec = S_GET_SEGMENT (sym); |
16862 | ||
5919d012 RS |
16863 | /* This must duplicate the test in adjust_reloc_syms. */ |
16864 | return (symsec != &bfd_und_section | |
16865 | && symsec != &bfd_abs_section | |
5f0fe04b TS |
16866 | && !bfd_is_com_section (symsec) |
16867 | && !s_is_linkonce (sym, segtype) | |
5919d012 RS |
16868 | #ifdef OBJ_ELF |
16869 | /* A global or weak symbol is treated as external. */ | |
f43abd2b | 16870 | && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym))) |
5919d012 RS |
16871 | #endif |
16872 | ); | |
16873 | } | |
16874 | ||
16875 | ||
252b5132 RH |
16876 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
16877 | extended opcode. SEC is the section the frag is in. */ | |
16878 | ||
16879 | static int | |
17a2f251 | 16880 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
16881 | { |
16882 | int type; | |
3994f87e | 16883 | const struct mips16_immed_operand *op; |
252b5132 RH |
16884 | offsetT val; |
16885 | int mintiny, maxtiny; | |
16886 | segT symsec; | |
98aa84af | 16887 | fragS *sym_frag; |
252b5132 RH |
16888 | |
16889 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
16890 | return 0; | |
16891 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
16892 | return 1; | |
16893 | ||
16894 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
16895 | op = mips16_immed_operands; | |
16896 | while (op->type != type) | |
16897 | { | |
16898 | ++op; | |
9c2799c2 | 16899 | gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
252b5132 RH |
16900 | } |
16901 | ||
16902 | if (op->unsp) | |
16903 | { | |
16904 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
16905 | { | |
16906 | mintiny = 1; | |
16907 | maxtiny = 1 << op->nbits; | |
16908 | } | |
16909 | else | |
16910 | { | |
16911 | mintiny = 0; | |
16912 | maxtiny = (1 << op->nbits) - 1; | |
16913 | } | |
16914 | } | |
16915 | else | |
16916 | { | |
16917 | mintiny = - (1 << (op->nbits - 1)); | |
16918 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
16919 | } | |
16920 | ||
98aa84af | 16921 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 16922 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 16923 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
16924 | |
16925 | if (op->pcrel) | |
16926 | { | |
16927 | addressT addr; | |
16928 | ||
16929 | /* We won't have the section when we are called from | |
16930 | mips_relax_frag. However, we will always have been called | |
16931 | from md_estimate_size_before_relax first. If this is a | |
16932 | branch to a different section, we mark it as such. If SEC is | |
16933 | NULL, and the frag is not marked, then it must be a branch to | |
16934 | the same section. */ | |
16935 | if (sec == NULL) | |
16936 | { | |
16937 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
16938 | return 1; | |
16939 | } | |
16940 | else | |
16941 | { | |
98aa84af | 16942 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
16943 | if (symsec != sec) |
16944 | { | |
16945 | fragp->fr_subtype = | |
16946 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
16947 | ||
16948 | /* FIXME: We should support this, and let the linker | |
16949 | catch branches and loads that are out of range. */ | |
16950 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
16951 | _("unsupported PC relative reference to different section")); | |
16952 | ||
16953 | return 1; | |
16954 | } | |
98aa84af AM |
16955 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
16956 | /* Assume non-extended on the first relaxation pass. | |
16957 | The address we have calculated will be bogus if this is | |
16958 | a forward branch to another frag, as the forward frag | |
16959 | will have fr_address == 0. */ | |
16960 | return 0; | |
252b5132 RH |
16961 | } |
16962 | ||
16963 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
16964 | the same section. If the relax_marker of the symbol fragment |
16965 | differs from the relax_marker of this fragment, we have not | |
16966 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
16967 | in STRETCH in order to get a better estimate of the address. |
16968 | This particularly matters because of the shift bits. */ | |
16969 | if (stretch != 0 | |
98aa84af | 16970 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
16971 | { |
16972 | fragS *f; | |
16973 | ||
16974 | /* Adjust stretch for any alignment frag. Note that if have | |
16975 | been expanding the earlier code, the symbol may be | |
16976 | defined in what appears to be an earlier frag. FIXME: | |
16977 | This doesn't handle the fr_subtype field, which specifies | |
16978 | a maximum number of bytes to skip when doing an | |
16979 | alignment. */ | |
98aa84af | 16980 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
16981 | { |
16982 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
16983 | { | |
16984 | if (stretch < 0) | |
16985 | stretch = - ((- stretch) | |
16986 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
16987 | else | |
16988 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
16989 | if (stretch == 0) | |
16990 | break; | |
16991 | } | |
16992 | } | |
16993 | if (f != NULL) | |
16994 | val += stretch; | |
16995 | } | |
16996 | ||
16997 | addr = fragp->fr_address + fragp->fr_fix; | |
16998 | ||
16999 | /* The base address rules are complicated. The base address of | |
17000 | a branch is the following instruction. The base address of a | |
17001 | PC relative load or add is the instruction itself, but if it | |
17002 | is in a delay slot (in which case it can not be extended) use | |
17003 | the address of the instruction whose delay slot it is in. */ | |
17004 | if (type == 'p' || type == 'q') | |
17005 | { | |
17006 | addr += 2; | |
17007 | ||
17008 | /* If we are currently assuming that this frag should be | |
17009 | extended, then, the current address is two bytes | |
bdaaa2e1 | 17010 | higher. */ |
252b5132 RH |
17011 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
17012 | addr += 2; | |
17013 | ||
17014 | /* Ignore the low bit in the target, since it will be set | |
17015 | for a text label. */ | |
17016 | if ((val & 1) != 0) | |
17017 | --val; | |
17018 | } | |
17019 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
17020 | addr -= 4; | |
17021 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
17022 | addr -= 2; | |
17023 | ||
17024 | val -= addr & ~ ((1 << op->shift) - 1); | |
17025 | ||
17026 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
17027 | if (type == 'p' || type == 'q') | |
17028 | val /= 2; | |
17029 | ||
17030 | /* If any of the shifted bits are set, we must use an extended | |
17031 | opcode. If the address depends on the size of this | |
17032 | instruction, this can lead to a loop, so we arrange to always | |
17033 | use an extended opcode. We only check this when we are in | |
17034 | the main relaxation loop, when SEC is NULL. */ | |
17035 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
17036 | { | |
17037 | fragp->fr_subtype = | |
17038 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
17039 | return 1; | |
17040 | } | |
17041 | ||
17042 | /* If we are about to mark a frag as extended because the value | |
17043 | is precisely maxtiny + 1, then there is a chance of an | |
17044 | infinite loop as in the following code: | |
17045 | la $4,foo | |
17046 | .skip 1020 | |
17047 | .align 2 | |
17048 | foo: | |
17049 | In this case when the la is extended, foo is 0x3fc bytes | |
17050 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
17051 | the la must be extended. To avoid this loop, we mark the | |
17052 | frag as extended if it was small, and is about to become | |
17053 | extended with a value of maxtiny + 1. */ | |
17054 | if (val == ((maxtiny + 1) << op->shift) | |
17055 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
17056 | && sec == NULL) | |
17057 | { | |
17058 | fragp->fr_subtype = | |
17059 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
17060 | return 1; | |
17061 | } | |
17062 | } | |
17063 | else if (symsec != absolute_section && sec != NULL) | |
17064 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
17065 | ||
17066 | if ((val & ((1 << op->shift) - 1)) != 0 | |
17067 | || val < (mintiny << op->shift) | |
17068 | || val > (maxtiny << op->shift)) | |
17069 | return 1; | |
17070 | else | |
17071 | return 0; | |
17072 | } | |
17073 | ||
4a6a3df4 AO |
17074 | /* Compute the length of a branch sequence, and adjust the |
17075 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
17076 | worst-case length is computed, with UPDATE being used to indicate | |
17077 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
17078 | branch is to be computed. */ | |
17079 | static int | |
17a2f251 | 17080 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 17081 | { |
b34976b6 | 17082 | bfd_boolean toofar; |
4a6a3df4 AO |
17083 | int length; |
17084 | ||
17085 | if (fragp | |
17086 | && S_IS_DEFINED (fragp->fr_symbol) | |
17087 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
17088 | { | |
17089 | addressT addr; | |
17090 | offsetT val; | |
17091 | ||
17092 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17093 | ||
17094 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
17095 | ||
17096 | val -= addr; | |
17097 | ||
17098 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
17099 | } | |
17100 | else if (fragp) | |
17101 | /* If the symbol is not defined or it's in a different segment, | |
17102 | assume the user knows what's going on and emit a short | |
17103 | branch. */ | |
b34976b6 | 17104 | toofar = FALSE; |
4a6a3df4 | 17105 | else |
b34976b6 | 17106 | toofar = TRUE; |
4a6a3df4 AO |
17107 | |
17108 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
17109 | fragp->fr_subtype | |
66b3e8da MR |
17110 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype), |
17111 | RELAX_BRANCH_UNCOND (fragp->fr_subtype), | |
4a6a3df4 AO |
17112 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
17113 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
17114 | toofar); | |
17115 | ||
17116 | length = 4; | |
17117 | if (toofar) | |
17118 | { | |
17119 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
17120 | length += 8; | |
17121 | ||
17122 | if (mips_pic != NO_PIC) | |
17123 | { | |
17124 | /* Additional space for PIC loading of target address. */ | |
17125 | length += 8; | |
17126 | if (mips_opts.isa == ISA_MIPS1) | |
17127 | /* Additional space for $at-stabilizing nop. */ | |
17128 | length += 4; | |
17129 | } | |
17130 | ||
17131 | /* If branch is conditional. */ | |
17132 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
17133 | length += 8; | |
17134 | } | |
b34976b6 | 17135 | |
4a6a3df4 AO |
17136 | return length; |
17137 | } | |
17138 | ||
df58fc94 RS |
17139 | /* Compute the length of a branch sequence, and adjust the |
17140 | RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the | |
17141 | worst-case length is computed, with UPDATE being used to indicate | |
17142 | whether an unconditional (-1), or regular (0) branch is to be | |
17143 | computed. */ | |
17144 | ||
17145 | static int | |
17146 | relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update) | |
17147 | { | |
17148 | bfd_boolean toofar; | |
17149 | int length; | |
17150 | ||
17151 | if (fragp | |
17152 | && S_IS_DEFINED (fragp->fr_symbol) | |
17153 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
17154 | { | |
17155 | addressT addr; | |
17156 | offsetT val; | |
17157 | ||
17158 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17159 | /* Ignore the low bit in the target, since it will be set | |
17160 | for a text label. */ | |
17161 | if ((val & 1) != 0) | |
17162 | --val; | |
17163 | ||
17164 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
17165 | ||
17166 | val -= addr; | |
17167 | ||
17168 | toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1); | |
17169 | } | |
17170 | else if (fragp) | |
17171 | /* If the symbol is not defined or it's in a different segment, | |
17172 | assume the user knows what's going on and emit a short | |
17173 | branch. */ | |
17174 | toofar = FALSE; | |
17175 | else | |
17176 | toofar = TRUE; | |
17177 | ||
17178 | if (fragp && update | |
17179 | && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
17180 | fragp->fr_subtype = (toofar | |
17181 | ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype) | |
17182 | : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype)); | |
17183 | ||
17184 | length = 4; | |
17185 | if (toofar) | |
17186 | { | |
17187 | bfd_boolean compact_known = fragp != NULL; | |
17188 | bfd_boolean compact = FALSE; | |
17189 | bfd_boolean uncond; | |
17190 | ||
17191 | if (compact_known) | |
17192 | compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); | |
17193 | if (fragp) | |
17194 | uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype); | |
17195 | else | |
17196 | uncond = update < 0; | |
17197 | ||
17198 | /* If label is out of range, we turn branch <br>: | |
17199 | ||
17200 | <br> label # 4 bytes | |
17201 | 0: | |
17202 | ||
17203 | into: | |
17204 | ||
17205 | j label # 4 bytes | |
17206 | nop # 2 bytes if compact && !PIC | |
17207 | 0: | |
17208 | */ | |
17209 | if (mips_pic == NO_PIC && (!compact_known || compact)) | |
17210 | length += 2; | |
17211 | ||
17212 | /* If assembling PIC code, we further turn: | |
17213 | ||
17214 | j label # 4 bytes | |
17215 | ||
17216 | into: | |
17217 | ||
17218 | lw/ld at, %got(label)(gp) # 4 bytes | |
17219 | d/addiu at, %lo(label) # 4 bytes | |
17220 | jr/c at # 2 bytes | |
17221 | */ | |
17222 | if (mips_pic != NO_PIC) | |
17223 | length += 6; | |
17224 | ||
17225 | /* If branch <br> is conditional, we prepend negated branch <brneg>: | |
17226 | ||
17227 | <brneg> 0f # 4 bytes | |
17228 | nop # 2 bytes if !compact | |
17229 | */ | |
17230 | if (!uncond) | |
17231 | length += (compact_known && compact) ? 4 : 6; | |
17232 | } | |
17233 | ||
17234 | return length; | |
17235 | } | |
17236 | ||
17237 | /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16 | |
17238 | bit accordingly. */ | |
17239 | ||
17240 | static int | |
17241 | relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update) | |
17242 | { | |
17243 | bfd_boolean toofar; | |
17244 | ||
df58fc94 RS |
17245 | if (fragp |
17246 | && S_IS_DEFINED (fragp->fr_symbol) | |
17247 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
17248 | { | |
17249 | addressT addr; | |
17250 | offsetT val; | |
17251 | int type; | |
17252 | ||
17253 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17254 | /* Ignore the low bit in the target, since it will be set | |
17255 | for a text label. */ | |
17256 | if ((val & 1) != 0) | |
17257 | --val; | |
17258 | ||
17259 | /* Assume this is a 2-byte branch. */ | |
17260 | addr = fragp->fr_address + fragp->fr_fix + 2; | |
17261 | ||
17262 | /* We try to avoid the infinite loop by not adding 2 more bytes for | |
17263 | long branches. */ | |
17264 | ||
17265 | val -= addr; | |
17266 | ||
17267 | type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
17268 | if (type == 'D') | |
17269 | toofar = val < - (0x200 << 1) || val >= (0x200 << 1); | |
17270 | else if (type == 'E') | |
17271 | toofar = val < - (0x40 << 1) || val >= (0x40 << 1); | |
17272 | else | |
17273 | abort (); | |
17274 | } | |
17275 | else | |
17276 | /* If the symbol is not defined or it's in a different segment, | |
17277 | we emit a normal 32-bit branch. */ | |
17278 | toofar = TRUE; | |
17279 | ||
17280 | if (fragp && update | |
17281 | && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
17282 | fragp->fr_subtype | |
17283 | = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype) | |
17284 | : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype); | |
17285 | ||
17286 | if (toofar) | |
17287 | return 4; | |
17288 | ||
17289 | return 2; | |
17290 | } | |
17291 | ||
252b5132 RH |
17292 | /* Estimate the size of a frag before relaxing. Unless this is the |
17293 | mips16, we are not really relaxing here, and the final size is | |
17294 | encoded in the subtype information. For the mips16, we have to | |
17295 | decide whether we are using an extended opcode or not. */ | |
17296 | ||
252b5132 | 17297 | int |
17a2f251 | 17298 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 17299 | { |
5919d012 | 17300 | int change; |
252b5132 | 17301 | |
4a6a3df4 AO |
17302 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
17303 | { | |
17304 | ||
b34976b6 AM |
17305 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
17306 | ||
4a6a3df4 AO |
17307 | return fragp->fr_var; |
17308 | } | |
17309 | ||
252b5132 | 17310 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
17311 | /* We don't want to modify the EXTENDED bit here; it might get us |
17312 | into infinite loops. We change it only in mips_relax_frag(). */ | |
17313 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 | 17314 | |
df58fc94 RS |
17315 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
17316 | { | |
17317 | int length = 4; | |
17318 | ||
17319 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
17320 | length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE); | |
17321 | if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
17322 | length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE); | |
17323 | fragp->fr_var = length; | |
17324 | ||
17325 | return length; | |
17326 | } | |
17327 | ||
252b5132 | 17328 | if (mips_pic == NO_PIC) |
5919d012 | 17329 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 17330 | else if (mips_pic == SVR4_PIC) |
5919d012 | 17331 | change = pic_need_relax (fragp->fr_symbol, segtype); |
0a44bf69 RS |
17332 | else if (mips_pic == VXWORKS_PIC) |
17333 | /* For vxworks, GOT16 relocations never have a corresponding LO16. */ | |
17334 | change = 0; | |
252b5132 RH |
17335 | else |
17336 | abort (); | |
17337 | ||
17338 | if (change) | |
17339 | { | |
4d7206a2 | 17340 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 17341 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 17342 | } |
4d7206a2 RS |
17343 | else |
17344 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
17345 | } |
17346 | ||
17347 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 17348 | should be converted into a reloc against a section. */ |
252b5132 RH |
17349 | |
17350 | int | |
17a2f251 | 17351 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 17352 | { |
252b5132 RH |
17353 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
17354 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
17355 | return 0; | |
a161fe53 | 17356 | |
252b5132 RH |
17357 | if (fixp->fx_addsy == NULL) |
17358 | return 1; | |
a161fe53 | 17359 | |
de7e6852 RS |
17360 | /* If symbol SYM is in a mergeable section, relocations of the form |
17361 | SYM + 0 can usually be made section-relative. The mergeable data | |
17362 | is then identified by the section offset rather than by the symbol. | |
17363 | ||
17364 | However, if we're generating REL LO16 relocations, the offset is split | |
17365 | between the LO16 and parterning high part relocation. The linker will | |
17366 | need to recalculate the complete offset in order to correctly identify | |
17367 | the merge data. | |
17368 | ||
17369 | The linker has traditionally not looked for the parterning high part | |
17370 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be | |
17371 | placed anywhere. Rather than break backwards compatibility by changing | |
17372 | this, it seems better not to force the issue, and instead keep the | |
17373 | original symbol. This will work with either linker behavior. */ | |
738e5348 | 17374 | if ((lo16_reloc_p (fixp->fx_r_type) |
704803a9 | 17375 | || reloc_needs_lo_p (fixp->fx_r_type)) |
de7e6852 RS |
17376 | && HAVE_IN_PLACE_ADDENDS |
17377 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
17378 | return 0; | |
17379 | ||
ce70d90a MR |
17380 | /* There is no place to store an in-place offset for JALR relocations. |
17381 | Likewise an in-range offset of PC-relative relocations may overflow | |
17382 | the in-place relocatable field if recalculated against the start | |
17383 | address of the symbol's containing section. */ | |
17384 | if (HAVE_IN_PLACE_ADDENDS | |
df58fc94 | 17385 | && (fixp->fx_pcrel || jalr_reloc_p (fixp->fx_r_type))) |
1180b5a4 RS |
17386 | return 0; |
17387 | ||
252b5132 | 17388 | #ifdef OBJ_ELF |
b314ec0e RS |
17389 | /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve |
17390 | to a floating-point stub. The same is true for non-R_MIPS16_26 | |
17391 | relocations against MIPS16 functions; in this case, the stub becomes | |
17392 | the function's canonical address. | |
17393 | ||
17394 | Floating-point stubs are stored in unique .mips16.call.* or | |
17395 | .mips16.fn.* sections. If a stub T for function F is in section S, | |
17396 | the first relocation in section S must be against F; this is how the | |
17397 | linker determines the target function. All relocations that might | |
17398 | resolve to T must also be against F. We therefore have the following | |
17399 | restrictions, which are given in an intentionally-redundant way: | |
17400 | ||
17401 | 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16 | |
17402 | symbols. | |
17403 | ||
17404 | 2. We cannot reduce a stub's relocations against non-MIPS16 symbols | |
17405 | if that stub might be used. | |
17406 | ||
17407 | 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16 | |
17408 | symbols. | |
17409 | ||
17410 | 4. We cannot reduce a stub's relocations against MIPS16 symbols if | |
17411 | that stub might be used. | |
17412 | ||
17413 | There is a further restriction: | |
17414 | ||
df58fc94 RS |
17415 | 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or |
17416 | R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on | |
17417 | targets with in-place addends; the relocation field cannot | |
b314ec0e RS |
17418 | encode the low bit. |
17419 | ||
df58fc94 RS |
17420 | For simplicity, we deal with (3)-(4) by not reducing _any_ relocation |
17421 | against a MIPS16 symbol. We deal with (5) by by not reducing any | |
17422 | such relocations on REL targets. | |
b314ec0e RS |
17423 | |
17424 | We deal with (1)-(2) by saying that, if there's a R_MIPS16_26 | |
17425 | relocation against some symbol R, no relocation against R may be | |
17426 | reduced. (Note that this deals with (2) as well as (1) because | |
17427 | relocations against global symbols will never be reduced on ELF | |
17428 | targets.) This approach is a little simpler than trying to detect | |
17429 | stub sections, and gives the "all or nothing" per-symbol consistency | |
17430 | that we have for MIPS16 symbols. */ | |
f43abd2b | 17431 | if (IS_ELF |
b314ec0e | 17432 | && fixp->fx_subsy == NULL |
30c09090 | 17433 | && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy)) |
df58fc94 RS |
17434 | || *symbol_get_tc (fixp->fx_addsy) |
17435 | || (HAVE_IN_PLACE_ADDENDS | |
17436 | && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy)) | |
17437 | && jmp_reloc_p (fixp->fx_r_type)))) | |
252b5132 RH |
17438 | return 0; |
17439 | #endif | |
a161fe53 | 17440 | |
252b5132 RH |
17441 | return 1; |
17442 | } | |
17443 | ||
17444 | /* Translate internal representation of relocation info to BFD target | |
17445 | format. */ | |
17446 | ||
17447 | arelent ** | |
17a2f251 | 17448 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
17449 | { |
17450 | static arelent *retval[4]; | |
17451 | arelent *reloc; | |
17452 | bfd_reloc_code_real_type code; | |
17453 | ||
4b0cff4e TS |
17454 | memset (retval, 0, sizeof(retval)); |
17455 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
17456 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
17457 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
17458 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
17459 | ||
bad36eac DJ |
17460 | if (fixp->fx_pcrel) |
17461 | { | |
df58fc94 RS |
17462 | gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 |
17463 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
17464 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
17465 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
bad36eac DJ |
17466 | |
17467 | /* At this point, fx_addnumber is "symbol offset - pcrel address". | |
17468 | Relocations want only the symbol offset. */ | |
17469 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
f43abd2b | 17470 | if (!IS_ELF) |
bad36eac DJ |
17471 | { |
17472 | /* A gruesome hack which is a result of the gruesome gas | |
17473 | reloc handling. What's worse, for COFF (as opposed to | |
17474 | ECOFF), we might need yet another copy of reloc->address. | |
17475 | See bfd_install_relocation. */ | |
17476 | reloc->addend += reloc->address; | |
17477 | } | |
17478 | } | |
17479 | else | |
17480 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 17481 | |
438c16b8 TS |
17482 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
17483 | entry to be used in the relocation's section offset. */ | |
17484 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
17485 | { |
17486 | reloc->address = reloc->addend; | |
17487 | reloc->addend = 0; | |
17488 | } | |
17489 | ||
252b5132 | 17490 | code = fixp->fx_r_type; |
252b5132 | 17491 | |
bad36eac | 17492 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
252b5132 RH |
17493 | if (reloc->howto == NULL) |
17494 | { | |
17495 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
17496 | _("Can not represent %s relocation in this object file format"), | |
17497 | bfd_get_reloc_code_name (code)); | |
17498 | retval[0] = NULL; | |
17499 | } | |
17500 | ||
17501 | return retval; | |
17502 | } | |
17503 | ||
17504 | /* Relax a machine dependent frag. This returns the amount by which | |
17505 | the current size of the frag should change. */ | |
17506 | ||
17507 | int | |
17a2f251 | 17508 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 17509 | { |
4a6a3df4 AO |
17510 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
17511 | { | |
17512 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
17513 | |
17514 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
17515 | |
17516 | return fragp->fr_var - old_var; | |
17517 | } | |
17518 | ||
df58fc94 RS |
17519 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
17520 | { | |
17521 | offsetT old_var = fragp->fr_var; | |
17522 | offsetT new_var = 4; | |
17523 | ||
17524 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
17525 | new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE); | |
17526 | if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
17527 | new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE); | |
17528 | fragp->fr_var = new_var; | |
17529 | ||
17530 | return new_var - old_var; | |
17531 | } | |
17532 | ||
252b5132 RH |
17533 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
17534 | return 0; | |
17535 | ||
c4e7957c | 17536 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
17537 | { |
17538 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
17539 | return 0; | |
17540 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
17541 | return 2; | |
17542 | } | |
17543 | else | |
17544 | { | |
17545 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
17546 | return 0; | |
17547 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
17548 | return -2; | |
17549 | } | |
17550 | ||
17551 | return 0; | |
17552 | } | |
17553 | ||
17554 | /* Convert a machine dependent frag. */ | |
17555 | ||
17556 | void | |
17a2f251 | 17557 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 17558 | { |
4a6a3df4 AO |
17559 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
17560 | { | |
17561 | bfd_byte *buf; | |
17562 | unsigned long insn; | |
17563 | expressionS exp; | |
17564 | fixS *fixp; | |
b34976b6 | 17565 | |
4a6a3df4 AO |
17566 | buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; |
17567 | ||
17568 | if (target_big_endian) | |
17569 | insn = bfd_getb32 (buf); | |
17570 | else | |
17571 | insn = bfd_getl32 (buf); | |
b34976b6 | 17572 | |
4a6a3df4 AO |
17573 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
17574 | { | |
17575 | /* We generate a fixup instead of applying it right now | |
17576 | because, if there are linker relaxations, we're going to | |
17577 | need the relocations. */ | |
17578 | exp.X_op = O_symbol; | |
17579 | exp.X_add_symbol = fragp->fr_symbol; | |
17580 | exp.X_add_number = fragp->fr_offset; | |
17581 | ||
17582 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 17583 | 4, &exp, TRUE, BFD_RELOC_16_PCREL_S2); |
4a6a3df4 AO |
17584 | fixp->fx_file = fragp->fr_file; |
17585 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 17586 | |
2132e3a3 | 17587 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
17588 | buf += 4; |
17589 | } | |
17590 | else | |
17591 | { | |
17592 | int i; | |
17593 | ||
17594 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
5c4f07ba | 17595 | _("Relaxed out-of-range branch into a jump")); |
4a6a3df4 AO |
17596 | |
17597 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
17598 | goto uncond; | |
17599 | ||
17600 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
17601 | { | |
17602 | /* Reverse the branch. */ | |
17603 | switch ((insn >> 28) & 0xf) | |
17604 | { | |
17605 | case 4: | |
17606 | /* bc[0-3][tf]l? and bc1any[24][ft] instructions can | |
17607 | have the condition reversed by tweaking a single | |
17608 | bit, and their opcodes all have 0x4???????. */ | |
9c2799c2 | 17609 | gas_assert ((insn & 0xf1000000) == 0x41000000); |
4a6a3df4 AO |
17610 | insn ^= 0x00010000; |
17611 | break; | |
17612 | ||
17613 | case 0: | |
17614 | /* bltz 0x04000000 bgez 0x04010000 | |
54f4ddb3 | 17615 | bltzal 0x04100000 bgezal 0x04110000 */ |
9c2799c2 | 17616 | gas_assert ((insn & 0xfc0e0000) == 0x04000000); |
4a6a3df4 AO |
17617 | insn ^= 0x00010000; |
17618 | break; | |
b34976b6 | 17619 | |
4a6a3df4 AO |
17620 | case 1: |
17621 | /* beq 0x10000000 bne 0x14000000 | |
54f4ddb3 | 17622 | blez 0x18000000 bgtz 0x1c000000 */ |
4a6a3df4 AO |
17623 | insn ^= 0x04000000; |
17624 | break; | |
17625 | ||
17626 | default: | |
17627 | abort (); | |
17628 | } | |
17629 | } | |
17630 | ||
17631 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
17632 | { | |
17633 | /* Clear the and-link bit. */ | |
9c2799c2 | 17634 | gas_assert ((insn & 0xfc1c0000) == 0x04100000); |
4a6a3df4 | 17635 | |
54f4ddb3 TS |
17636 | /* bltzal 0x04100000 bgezal 0x04110000 |
17637 | bltzall 0x04120000 bgezall 0x04130000 */ | |
4a6a3df4 AO |
17638 | insn &= ~0x00100000; |
17639 | } | |
17640 | ||
17641 | /* Branch over the branch (if the branch was likely) or the | |
17642 | full jump (not likely case). Compute the offset from the | |
17643 | current instruction to branch to. */ | |
17644 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
17645 | i = 16; | |
17646 | else | |
17647 | { | |
17648 | /* How many bytes in instructions we've already emitted? */ | |
17649 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
17650 | /* How many bytes in instructions from here to the end? */ | |
17651 | i = fragp->fr_var - i; | |
17652 | } | |
17653 | /* Convert to instruction count. */ | |
17654 | i >>= 2; | |
17655 | /* Branch counts from the next instruction. */ | |
b34976b6 | 17656 | i--; |
4a6a3df4 AO |
17657 | insn |= i; |
17658 | /* Branch over the jump. */ | |
2132e3a3 | 17659 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
17660 | buf += 4; |
17661 | ||
54f4ddb3 | 17662 | /* nop */ |
2132e3a3 | 17663 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
17664 | buf += 4; |
17665 | ||
17666 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
17667 | { | |
17668 | /* beql $0, $0, 2f */ | |
17669 | insn = 0x50000000; | |
17670 | /* Compute the PC offset from the current instruction to | |
17671 | the end of the variable frag. */ | |
17672 | /* How many bytes in instructions we've already emitted? */ | |
17673 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
17674 | /* How many bytes in instructions from here to the end? */ | |
17675 | i = fragp->fr_var - i; | |
17676 | /* Convert to instruction count. */ | |
17677 | i >>= 2; | |
17678 | /* Don't decrement i, because we want to branch over the | |
17679 | delay slot. */ | |
17680 | ||
17681 | insn |= i; | |
2132e3a3 | 17682 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
17683 | buf += 4; |
17684 | ||
2132e3a3 | 17685 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
17686 | buf += 4; |
17687 | } | |
17688 | ||
17689 | uncond: | |
17690 | if (mips_pic == NO_PIC) | |
17691 | { | |
17692 | /* j or jal. */ | |
17693 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
17694 | ? 0x0c000000 : 0x08000000); | |
17695 | exp.X_op = O_symbol; | |
17696 | exp.X_add_symbol = fragp->fr_symbol; | |
17697 | exp.X_add_number = fragp->fr_offset; | |
17698 | ||
17699 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 17700 | 4, &exp, FALSE, BFD_RELOC_MIPS_JMP); |
4a6a3df4 AO |
17701 | fixp->fx_file = fragp->fr_file; |
17702 | fixp->fx_line = fragp->fr_line; | |
17703 | ||
2132e3a3 | 17704 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
17705 | buf += 4; |
17706 | } | |
17707 | else | |
17708 | { | |
66b3e8da MR |
17709 | unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype); |
17710 | ||
4a6a3df4 | 17711 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ |
66b3e8da MR |
17712 | insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000; |
17713 | insn |= at << OP_SH_RT; | |
4a6a3df4 AO |
17714 | exp.X_op = O_symbol; |
17715 | exp.X_add_symbol = fragp->fr_symbol; | |
17716 | exp.X_add_number = fragp->fr_offset; | |
17717 | ||
17718 | if (fragp->fr_offset) | |
17719 | { | |
17720 | exp.X_add_symbol = make_expr_symbol (&exp); | |
17721 | exp.X_add_number = 0; | |
17722 | } | |
17723 | ||
17724 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 17725 | 4, &exp, FALSE, BFD_RELOC_MIPS_GOT16); |
4a6a3df4 AO |
17726 | fixp->fx_file = fragp->fr_file; |
17727 | fixp->fx_line = fragp->fr_line; | |
17728 | ||
2132e3a3 | 17729 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 | 17730 | buf += 4; |
b34976b6 | 17731 | |
4a6a3df4 AO |
17732 | if (mips_opts.isa == ISA_MIPS1) |
17733 | { | |
17734 | /* nop */ | |
2132e3a3 | 17735 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
17736 | buf += 4; |
17737 | } | |
17738 | ||
17739 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
66b3e8da MR |
17740 | insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000; |
17741 | insn |= at << OP_SH_RS | at << OP_SH_RT; | |
4a6a3df4 AO |
17742 | |
17743 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 17744 | 4, &exp, FALSE, BFD_RELOC_LO16); |
4a6a3df4 AO |
17745 | fixp->fx_file = fragp->fr_file; |
17746 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 17747 | |
2132e3a3 | 17748 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
17749 | buf += 4; |
17750 | ||
17751 | /* j(al)r $at. */ | |
17752 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
66b3e8da | 17753 | insn = 0x0000f809; |
4a6a3df4 | 17754 | else |
66b3e8da MR |
17755 | insn = 0x00000008; |
17756 | insn |= at << OP_SH_RS; | |
4a6a3df4 | 17757 | |
2132e3a3 | 17758 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
17759 | buf += 4; |
17760 | } | |
17761 | } | |
17762 | ||
9c2799c2 | 17763 | gas_assert (buf == (bfd_byte *)fragp->fr_literal |
4a6a3df4 AO |
17764 | + fragp->fr_fix + fragp->fr_var); |
17765 | ||
17766 | fragp->fr_fix += fragp->fr_var; | |
17767 | ||
17768 | return; | |
17769 | } | |
17770 | ||
df58fc94 RS |
17771 | /* Relax microMIPS branches. */ |
17772 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) | |
17773 | { | |
17774 | bfd_byte *buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
17775 | bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); | |
17776 | bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype); | |
17777 | int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
2309ddf2 | 17778 | bfd_boolean short_ds; |
df58fc94 RS |
17779 | unsigned long insn; |
17780 | expressionS exp; | |
17781 | fixS *fixp; | |
17782 | ||
17783 | exp.X_op = O_symbol; | |
17784 | exp.X_add_symbol = fragp->fr_symbol; | |
17785 | exp.X_add_number = fragp->fr_offset; | |
17786 | ||
17787 | fragp->fr_fix += fragp->fr_var; | |
17788 | ||
17789 | /* Handle 16-bit branches that fit or are forced to fit. */ | |
17790 | if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
17791 | { | |
17792 | /* We generate a fixup instead of applying it right now, | |
17793 | because if there is linker relaxation, we're going to | |
17794 | need the relocations. */ | |
17795 | if (type == 'D') | |
17796 | fixp = fix_new_exp (fragp, | |
17797 | buf - (bfd_byte *) fragp->fr_literal, | |
17798 | 2, &exp, TRUE, | |
17799 | BFD_RELOC_MICROMIPS_10_PCREL_S1); | |
17800 | else if (type == 'E') | |
17801 | fixp = fix_new_exp (fragp, | |
17802 | buf - (bfd_byte *) fragp->fr_literal, | |
17803 | 2, &exp, TRUE, | |
17804 | BFD_RELOC_MICROMIPS_7_PCREL_S1); | |
17805 | else | |
17806 | abort (); | |
17807 | ||
17808 | fixp->fx_file = fragp->fr_file; | |
17809 | fixp->fx_line = fragp->fr_line; | |
17810 | ||
17811 | /* These relocations can have an addend that won't fit in | |
17812 | 2 octets. */ | |
17813 | fixp->fx_no_overflow = 1; | |
17814 | ||
17815 | return; | |
17816 | } | |
17817 | ||
2309ddf2 | 17818 | /* Handle 32-bit branches that fit or are forced to fit. */ |
df58fc94 RS |
17819 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) |
17820 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
17821 | { | |
17822 | /* We generate a fixup instead of applying it right now, | |
17823 | because if there is linker relaxation, we're going to | |
17824 | need the relocations. */ | |
17825 | fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal, | |
17826 | 4, &exp, TRUE, BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
17827 | fixp->fx_file = fragp->fr_file; | |
17828 | fixp->fx_line = fragp->fr_line; | |
17829 | ||
17830 | if (type == 0) | |
17831 | return; | |
17832 | } | |
17833 | ||
17834 | /* Relax 16-bit branches to 32-bit branches. */ | |
17835 | if (type != 0) | |
17836 | { | |
17837 | if (target_big_endian) | |
17838 | insn = bfd_getb16 (buf); | |
17839 | else | |
17840 | insn = bfd_getl16 (buf); | |
17841 | ||
17842 | if ((insn & 0xfc00) == 0xcc00) /* b16 */ | |
17843 | insn = 0x94000000; /* beq */ | |
17844 | else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */ | |
17845 | { | |
17846 | unsigned long regno; | |
17847 | ||
17848 | regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD; | |
17849 | regno = micromips_to_32_reg_d_map [regno]; | |
17850 | insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */ | |
17851 | insn |= regno << MICROMIPSOP_SH_RS; | |
17852 | } | |
17853 | else | |
17854 | abort (); | |
17855 | ||
17856 | /* Nothing else to do, just write it out. */ | |
17857 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) | |
17858 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
17859 | { | |
17860 | md_number_to_chars ((char *) buf, insn >> 16, 2); | |
17861 | buf += 2; | |
17862 | md_number_to_chars ((char *) buf, insn & 0xffff, 2); | |
17863 | buf += 2; | |
17864 | ||
17865 | gas_assert (buf == ((bfd_byte *) fragp->fr_literal | |
17866 | + fragp->fr_fix)); | |
17867 | return; | |
17868 | } | |
17869 | } | |
17870 | else | |
17871 | { | |
17872 | unsigned long next; | |
17873 | ||
17874 | if (target_big_endian) | |
17875 | { | |
17876 | insn = bfd_getb16 (buf); | |
17877 | next = bfd_getb16 (buf + 2); | |
17878 | } | |
17879 | else | |
17880 | { | |
17881 | insn = bfd_getl16 (buf); | |
17882 | next = bfd_getl16 (buf + 2); | |
17883 | } | |
17884 | insn = (insn << 16) | next; | |
17885 | } | |
17886 | ||
17887 | /* Relax 32-bit branches to a sequence of instructions. */ | |
17888 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
17889 | _("Relaxed out-of-range branch into a jump")); | |
17890 | ||
2309ddf2 MR |
17891 | /* Set the short-delay-slot bit. */ |
17892 | short_ds = al && (insn & 0x02000000) != 0; | |
df58fc94 RS |
17893 | |
17894 | if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype)) | |
17895 | { | |
17896 | symbolS *l; | |
17897 | ||
17898 | /* Reverse the branch. */ | |
17899 | if ((insn & 0xfc000000) == 0x94000000 /* beq */ | |
17900 | || (insn & 0xfc000000) == 0xb4000000) /* bne */ | |
17901 | insn ^= 0x20000000; | |
17902 | else if ((insn & 0xffe00000) == 0x40000000 /* bltz */ | |
17903 | || (insn & 0xffe00000) == 0x40400000 /* bgez */ | |
17904 | || (insn & 0xffe00000) == 0x40800000 /* blez */ | |
17905 | || (insn & 0xffe00000) == 0x40c00000 /* bgtz */ | |
17906 | || (insn & 0xffe00000) == 0x40a00000 /* bnezc */ | |
17907 | || (insn & 0xffe00000) == 0x40e00000 /* beqzc */ | |
17908 | || (insn & 0xffe00000) == 0x40200000 /* bltzal */ | |
17909 | || (insn & 0xffe00000) == 0x40600000 /* bgezal */ | |
17910 | || (insn & 0xffe00000) == 0x42200000 /* bltzals */ | |
17911 | || (insn & 0xffe00000) == 0x42600000) /* bgezals */ | |
17912 | insn ^= 0x00400000; | |
17913 | else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */ | |
17914 | || (insn & 0xffe30000) == 0x43a00000 /* bc1t */ | |
17915 | || (insn & 0xffe30000) == 0x42800000 /* bc2f */ | |
17916 | || (insn & 0xffe30000) == 0x42a00000) /* bc2t */ | |
17917 | insn ^= 0x00200000; | |
17918 | else | |
17919 | abort (); | |
17920 | ||
17921 | if (al) | |
17922 | { | |
17923 | /* Clear the and-link and short-delay-slot bits. */ | |
17924 | gas_assert ((insn & 0xfda00000) == 0x40200000); | |
17925 | ||
17926 | /* bltzal 0x40200000 bgezal 0x40600000 */ | |
17927 | /* bltzals 0x42200000 bgezals 0x42600000 */ | |
17928 | insn &= ~0x02200000; | |
17929 | } | |
17930 | ||
17931 | /* Make a label at the end for use with the branch. */ | |
17932 | l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp); | |
17933 | micromips_label_inc (); | |
17934 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) | |
17935 | if (IS_ELF) | |
17936 | S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l))); | |
17937 | #endif | |
17938 | ||
17939 | /* Refer to it. */ | |
17940 | fixp = fix_new (fragp, buf - (bfd_byte *) fragp->fr_literal, | |
17941 | 4, l, 0, TRUE, BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
17942 | fixp->fx_file = fragp->fr_file; | |
17943 | fixp->fx_line = fragp->fr_line; | |
17944 | ||
17945 | /* Branch over the jump. */ | |
17946 | md_number_to_chars ((char *) buf, insn >> 16, 2); | |
17947 | buf += 2; | |
17948 | md_number_to_chars ((char *) buf, insn & 0xffff, 2); | |
17949 | buf += 2; | |
17950 | ||
17951 | if (!compact) | |
17952 | { | |
17953 | /* nop */ | |
17954 | insn = 0x0c00; | |
17955 | md_number_to_chars ((char *) buf, insn, 2); | |
17956 | buf += 2; | |
17957 | } | |
17958 | } | |
17959 | ||
17960 | if (mips_pic == NO_PIC) | |
17961 | { | |
2309ddf2 MR |
17962 | unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */ |
17963 | ||
df58fc94 RS |
17964 | /* j/jal/jals <sym> R_MICROMIPS_26_S1 */ |
17965 | insn = al ? jal : 0xd4000000; | |
17966 | ||
17967 | fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal, | |
17968 | 4, &exp, FALSE, BFD_RELOC_MICROMIPS_JMP); | |
17969 | fixp->fx_file = fragp->fr_file; | |
17970 | fixp->fx_line = fragp->fr_line; | |
17971 | ||
17972 | md_number_to_chars ((char *) buf, insn >> 16, 2); | |
17973 | buf += 2; | |
17974 | md_number_to_chars ((char *) buf, insn & 0xffff, 2); | |
17975 | buf += 2; | |
17976 | ||
17977 | if (compact) | |
17978 | { | |
17979 | /* nop */ | |
17980 | insn = 0x0c00; | |
17981 | md_number_to_chars ((char *) buf, insn, 2); | |
17982 | buf += 2; | |
17983 | } | |
17984 | } | |
17985 | else | |
17986 | { | |
17987 | unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype); | |
2309ddf2 MR |
17988 | unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */ |
17989 | unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */ | |
df58fc94 RS |
17990 | |
17991 | /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */ | |
17992 | insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000; | |
17993 | insn |= at << MICROMIPSOP_SH_RT; | |
17994 | ||
17995 | if (exp.X_add_number) | |
17996 | { | |
17997 | exp.X_add_symbol = make_expr_symbol (&exp); | |
17998 | exp.X_add_number = 0; | |
17999 | } | |
18000 | ||
18001 | fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal, | |
18002 | 4, &exp, FALSE, BFD_RELOC_MICROMIPS_GOT16); | |
18003 | fixp->fx_file = fragp->fr_file; | |
18004 | fixp->fx_line = fragp->fr_line; | |
18005 | ||
18006 | md_number_to_chars ((char *) buf, insn >> 16, 2); | |
18007 | buf += 2; | |
18008 | md_number_to_chars ((char *) buf, insn & 0xffff, 2); | |
18009 | buf += 2; | |
18010 | ||
18011 | /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */ | |
18012 | insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000; | |
18013 | insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS; | |
18014 | ||
18015 | fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal, | |
18016 | 4, &exp, FALSE, BFD_RELOC_MICROMIPS_LO16); | |
18017 | fixp->fx_file = fragp->fr_file; | |
18018 | fixp->fx_line = fragp->fr_line; | |
18019 | ||
18020 | md_number_to_chars ((char *) buf, insn >> 16, 2); | |
18021 | buf += 2; | |
18022 | md_number_to_chars ((char *) buf, insn & 0xffff, 2); | |
18023 | buf += 2; | |
18024 | ||
18025 | /* jr/jrc/jalr/jalrs $at */ | |
18026 | insn = al ? jalr : jr; | |
18027 | insn |= at << MICROMIPSOP_SH_MJ; | |
18028 | ||
18029 | md_number_to_chars ((char *) buf, insn & 0xffff, 2); | |
18030 | buf += 2; | |
18031 | } | |
18032 | ||
18033 | gas_assert (buf == (bfd_byte *) fragp->fr_literal + fragp->fr_fix); | |
18034 | return; | |
18035 | } | |
18036 | ||
252b5132 RH |
18037 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
18038 | { | |
18039 | int type; | |
3994f87e | 18040 | const struct mips16_immed_operand *op; |
b34976b6 | 18041 | bfd_boolean small, ext; |
252b5132 RH |
18042 | offsetT val; |
18043 | bfd_byte *buf; | |
18044 | unsigned long insn; | |
b34976b6 | 18045 | bfd_boolean use_extend; |
252b5132 RH |
18046 | unsigned short extend; |
18047 | ||
18048 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
18049 | op = mips16_immed_operands; | |
18050 | while (op->type != type) | |
18051 | ++op; | |
18052 | ||
18053 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
18054 | { | |
b34976b6 AM |
18055 | small = FALSE; |
18056 | ext = TRUE; | |
252b5132 RH |
18057 | } |
18058 | else | |
18059 | { | |
b34976b6 AM |
18060 | small = TRUE; |
18061 | ext = FALSE; | |
252b5132 RH |
18062 | } |
18063 | ||
5f5f22c0 | 18064 | val = resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
18065 | if (op->pcrel) |
18066 | { | |
18067 | addressT addr; | |
18068 | ||
18069 | addr = fragp->fr_address + fragp->fr_fix; | |
18070 | ||
18071 | /* The rules for the base address of a PC relative reloc are | |
18072 | complicated; see mips16_extended_frag. */ | |
18073 | if (type == 'p' || type == 'q') | |
18074 | { | |
18075 | addr += 2; | |
18076 | if (ext) | |
18077 | addr += 2; | |
18078 | /* Ignore the low bit in the target, since it will be | |
18079 | set for a text label. */ | |
18080 | if ((val & 1) != 0) | |
18081 | --val; | |
18082 | } | |
18083 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
18084 | addr -= 4; | |
18085 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
18086 | addr -= 2; | |
18087 | ||
18088 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
18089 | val -= addr; | |
18090 | ||
18091 | /* Make sure the section winds up with the alignment we have | |
18092 | assumed. */ | |
18093 | if (op->shift > 0) | |
18094 | record_alignment (asec, op->shift); | |
18095 | } | |
18096 | ||
18097 | if (ext | |
18098 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
18099 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
18100 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
18101 | _("extended instruction in delay slot")); | |
18102 | ||
18103 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
18104 | ||
18105 | if (target_big_endian) | |
18106 | insn = bfd_getb16 (buf); | |
18107 | else | |
18108 | insn = bfd_getl16 (buf); | |
18109 | ||
18110 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
18111 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
18112 | small, ext, &insn, &use_extend, &extend); | |
18113 | ||
18114 | if (use_extend) | |
18115 | { | |
2132e3a3 | 18116 | md_number_to_chars ((char *) buf, 0xf000 | extend, 2); |
252b5132 RH |
18117 | fragp->fr_fix += 2; |
18118 | buf += 2; | |
18119 | } | |
18120 | ||
2132e3a3 | 18121 | md_number_to_chars ((char *) buf, insn, 2); |
252b5132 RH |
18122 | fragp->fr_fix += 2; |
18123 | buf += 2; | |
18124 | } | |
18125 | else | |
18126 | { | |
df58fc94 RS |
18127 | relax_substateT subtype = fragp->fr_subtype; |
18128 | bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0; | |
18129 | bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0; | |
4d7206a2 RS |
18130 | int first, second; |
18131 | fixS *fixp; | |
252b5132 | 18132 | |
df58fc94 RS |
18133 | first = RELAX_FIRST (subtype); |
18134 | second = RELAX_SECOND (subtype); | |
4d7206a2 | 18135 | fixp = (fixS *) fragp->fr_opcode; |
252b5132 | 18136 | |
df58fc94 RS |
18137 | /* If the delay slot chosen does not match the size of the instruction, |
18138 | then emit a warning. */ | |
18139 | if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0) | |
18140 | || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)) | |
18141 | { | |
18142 | relax_substateT s; | |
18143 | const char *msg; | |
18144 | ||
18145 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
18146 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
18147 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
18148 | msg = macro_warning (s); | |
18149 | if (msg != NULL) | |
18150 | as_warn_where (fragp->fr_file, fragp->fr_line, msg); | |
18151 | subtype &= ~s; | |
18152 | } | |
18153 | ||
584892a6 | 18154 | /* Possibly emit a warning if we've chosen the longer option. */ |
df58fc94 | 18155 | if (use_second == second_longer) |
584892a6 | 18156 | { |
df58fc94 RS |
18157 | relax_substateT s; |
18158 | const char *msg; | |
18159 | ||
18160 | s = (subtype | |
18161 | & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT)); | |
18162 | msg = macro_warning (s); | |
18163 | if (msg != NULL) | |
18164 | as_warn_where (fragp->fr_file, fragp->fr_line, msg); | |
18165 | subtype &= ~s; | |
584892a6 RS |
18166 | } |
18167 | ||
4d7206a2 RS |
18168 | /* Go through all the fixups for the first sequence. Disable them |
18169 | (by marking them as done) if we're going to use the second | |
18170 | sequence instead. */ | |
18171 | while (fixp | |
18172 | && fixp->fx_frag == fragp | |
18173 | && fixp->fx_where < fragp->fr_fix - second) | |
18174 | { | |
df58fc94 | 18175 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18176 | fixp->fx_done = 1; |
18177 | fixp = fixp->fx_next; | |
18178 | } | |
252b5132 | 18179 | |
4d7206a2 RS |
18180 | /* Go through the fixups for the second sequence. Disable them if |
18181 | we're going to use the first sequence, otherwise adjust their | |
18182 | addresses to account for the relaxation. */ | |
18183 | while (fixp && fixp->fx_frag == fragp) | |
18184 | { | |
df58fc94 | 18185 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18186 | fixp->fx_where -= first; |
18187 | else | |
18188 | fixp->fx_done = 1; | |
18189 | fixp = fixp->fx_next; | |
18190 | } | |
18191 | ||
18192 | /* Now modify the frag contents. */ | |
df58fc94 | 18193 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18194 | { |
18195 | char *start; | |
18196 | ||
18197 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
18198 | memmove (start, start + first, second); | |
18199 | fragp->fr_fix -= first; | |
18200 | } | |
18201 | else | |
18202 | fragp->fr_fix -= second; | |
252b5132 RH |
18203 | } |
18204 | } | |
18205 | ||
18206 | #ifdef OBJ_ELF | |
18207 | ||
18208 | /* This function is called after the relocs have been generated. | |
18209 | We've been storing mips16 text labels as odd. Here we convert them | |
18210 | back to even for the convenience of the debugger. */ | |
18211 | ||
18212 | void | |
17a2f251 | 18213 | mips_frob_file_after_relocs (void) |
252b5132 RH |
18214 | { |
18215 | asymbol **syms; | |
18216 | unsigned int count, i; | |
18217 | ||
f43abd2b | 18218 | if (!IS_ELF) |
252b5132 RH |
18219 | return; |
18220 | ||
18221 | syms = bfd_get_outsymbols (stdoutput); | |
18222 | count = bfd_get_symcount (stdoutput); | |
18223 | for (i = 0; i < count; i++, syms++) | |
df58fc94 RS |
18224 | if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other) |
18225 | && ((*syms)->value & 1) != 0) | |
18226 | { | |
18227 | (*syms)->value &= ~1; | |
18228 | /* If the symbol has an odd size, it was probably computed | |
18229 | incorrectly, so adjust that as well. */ | |
18230 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
18231 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
18232 | } | |
252b5132 RH |
18233 | } |
18234 | ||
18235 | #endif | |
18236 | ||
a1facbec MR |
18237 | /* This function is called whenever a label is defined, including fake |
18238 | labels instantiated off the dot special symbol. It is used when | |
18239 | handling branch delays; if a branch has a label, we assume we cannot | |
18240 | move it. This also bumps the value of the symbol by 1 in compressed | |
18241 | code. */ | |
252b5132 RH |
18242 | |
18243 | void | |
a1facbec | 18244 | mips_record_label (symbolS *sym) |
252b5132 | 18245 | { |
a8dbcb85 | 18246 | segment_info_type *si = seg_info (now_seg); |
252b5132 RH |
18247 | struct insn_label_list *l; |
18248 | ||
18249 | if (free_insn_labels == NULL) | |
18250 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
18251 | else | |
18252 | { | |
18253 | l = free_insn_labels; | |
18254 | free_insn_labels = l->next; | |
18255 | } | |
18256 | ||
18257 | l->label = sym; | |
a8dbcb85 TS |
18258 | l->next = si->label_list; |
18259 | si->label_list = l; | |
a1facbec | 18260 | } |
07a53e5c | 18261 | |
a1facbec MR |
18262 | /* This function is called as tc_frob_label() whenever a label is defined |
18263 | and adds a DWARF-2 record we only want for true labels. */ | |
18264 | ||
18265 | void | |
18266 | mips_define_label (symbolS *sym) | |
18267 | { | |
18268 | mips_record_label (sym); | |
07a53e5c RH |
18269 | #ifdef OBJ_ELF |
18270 | dwarf2_emit_label (sym); | |
18271 | #endif | |
252b5132 RH |
18272 | } |
18273 | \f | |
18274 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
18275 | ||
18276 | /* Some special processing for a MIPS ELF file. */ | |
18277 | ||
18278 | void | |
17a2f251 | 18279 | mips_elf_final_processing (void) |
252b5132 RH |
18280 | { |
18281 | /* Write out the register information. */ | |
316f5878 | 18282 | if (mips_abi != N64_ABI) |
252b5132 RH |
18283 | { |
18284 | Elf32_RegInfo s; | |
18285 | ||
18286 | s.ri_gprmask = mips_gprmask; | |
18287 | s.ri_cprmask[0] = mips_cprmask[0]; | |
18288 | s.ri_cprmask[1] = mips_cprmask[1]; | |
18289 | s.ri_cprmask[2] = mips_cprmask[2]; | |
18290 | s.ri_cprmask[3] = mips_cprmask[3]; | |
18291 | /* The gp_value field is set by the MIPS ELF backend. */ | |
18292 | ||
18293 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
18294 | ((Elf32_External_RegInfo *) | |
18295 | mips_regmask_frag)); | |
18296 | } | |
18297 | else | |
18298 | { | |
18299 | Elf64_Internal_RegInfo s; | |
18300 | ||
18301 | s.ri_gprmask = mips_gprmask; | |
18302 | s.ri_pad = 0; | |
18303 | s.ri_cprmask[0] = mips_cprmask[0]; | |
18304 | s.ri_cprmask[1] = mips_cprmask[1]; | |
18305 | s.ri_cprmask[2] = mips_cprmask[2]; | |
18306 | s.ri_cprmask[3] = mips_cprmask[3]; | |
18307 | /* The gp_value field is set by the MIPS ELF backend. */ | |
18308 | ||
18309 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
18310 | ((Elf64_External_RegInfo *) | |
18311 | mips_regmask_frag)); | |
18312 | } | |
18313 | ||
18314 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
18315 | sort of BFD interface for this. */ | |
18316 | if (mips_any_noreorder) | |
18317 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
18318 | if (mips_pic != NO_PIC) | |
143d77c5 | 18319 | { |
252b5132 | 18320 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
18321 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
18322 | } | |
18323 | if (mips_abicalls) | |
18324 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 18325 | |
98d3f06f | 18326 | /* Set MIPS ELF flags for ASEs. */ |
74cd071d CF |
18327 | /* We may need to define a new flag for DSP ASE, and set this flag when |
18328 | file_ase_dsp is true. */ | |
8b082fb1 | 18329 | /* Same for DSP R2. */ |
ef2e4d86 CF |
18330 | /* We may need to define a new flag for MT ASE, and set this flag when |
18331 | file_ase_mt is true. */ | |
a4672219 TS |
18332 | if (file_ase_mips16) |
18333 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
df58fc94 RS |
18334 | if (file_ase_micromips) |
18335 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS; | |
1f25f5d3 CD |
18336 | #if 0 /* XXX FIXME */ |
18337 | if (file_ase_mips3d) | |
18338 | elf_elfheader (stdoutput)->e_flags |= ???; | |
18339 | #endif | |
deec1734 CD |
18340 | if (file_ase_mdmx) |
18341 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; | |
1f25f5d3 | 18342 | |
bdaaa2e1 | 18343 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 18344 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 18345 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 18346 | else if (mips_abi == O64_ABI) |
252b5132 | 18347 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 18348 | else if (mips_abi == EABI_ABI) |
252b5132 | 18349 | { |
316f5878 | 18350 | if (!file_mips_gp32) |
252b5132 RH |
18351 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
18352 | else | |
18353 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
18354 | } | |
316f5878 | 18355 | else if (mips_abi == N32_ABI) |
be00bddd TS |
18356 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
18357 | ||
c9914766 | 18358 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
18359 | |
18360 | if (mips_32bitmode) | |
18361 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
ad3fea08 TS |
18362 | |
18363 | #if 0 /* XXX FIXME */ | |
18364 | /* 32 bit code with 64 bit FP registers. */ | |
18365 | if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
18366 | elf_elfheader (stdoutput)->e_flags |= ???; | |
18367 | #endif | |
252b5132 RH |
18368 | } |
18369 | ||
18370 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
18371 | \f | |
beae10d5 | 18372 | typedef struct proc { |
9b2f1d35 EC |
18373 | symbolS *func_sym; |
18374 | symbolS *func_end_sym; | |
beae10d5 KH |
18375 | unsigned long reg_mask; |
18376 | unsigned long reg_offset; | |
18377 | unsigned long fpreg_mask; | |
18378 | unsigned long fpreg_offset; | |
18379 | unsigned long frame_offset; | |
18380 | unsigned long frame_reg; | |
18381 | unsigned long pc_reg; | |
18382 | } procS; | |
252b5132 RH |
18383 | |
18384 | static procS cur_proc; | |
18385 | static procS *cur_proc_ptr; | |
18386 | static int numprocs; | |
18387 | ||
df58fc94 RS |
18388 | /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop |
18389 | as "2", and a normal nop as "0". */ | |
18390 | ||
18391 | #define NOP_OPCODE_MIPS 0 | |
18392 | #define NOP_OPCODE_MIPS16 1 | |
18393 | #define NOP_OPCODE_MICROMIPS 2 | |
742a56fe RS |
18394 | |
18395 | char | |
18396 | mips_nop_opcode (void) | |
18397 | { | |
df58fc94 RS |
18398 | if (seg_info (now_seg)->tc_segment_info_data.micromips) |
18399 | return NOP_OPCODE_MICROMIPS; | |
18400 | else if (seg_info (now_seg)->tc_segment_info_data.mips16) | |
18401 | return NOP_OPCODE_MIPS16; | |
18402 | else | |
18403 | return NOP_OPCODE_MIPS; | |
742a56fe RS |
18404 | } |
18405 | ||
df58fc94 RS |
18406 | /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use |
18407 | 32-bit microMIPS NOPs here (if applicable). */ | |
a19d8eb0 | 18408 | |
0a9ef439 | 18409 | void |
17a2f251 | 18410 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 18411 | { |
df58fc94 | 18412 | char nop_opcode; |
742a56fe | 18413 | char *p; |
c67a084a NC |
18414 | int bytes, size, excess; |
18415 | valueT opcode; | |
742a56fe | 18416 | |
0a9ef439 RH |
18417 | if (fragp->fr_type != rs_align_code) |
18418 | return; | |
18419 | ||
742a56fe | 18420 | p = fragp->fr_literal + fragp->fr_fix; |
df58fc94 RS |
18421 | nop_opcode = *p; |
18422 | switch (nop_opcode) | |
a19d8eb0 | 18423 | { |
df58fc94 RS |
18424 | case NOP_OPCODE_MICROMIPS: |
18425 | opcode = micromips_nop32_insn.insn_opcode; | |
18426 | size = 4; | |
18427 | break; | |
18428 | case NOP_OPCODE_MIPS16: | |
c67a084a NC |
18429 | opcode = mips16_nop_insn.insn_opcode; |
18430 | size = 2; | |
df58fc94 RS |
18431 | break; |
18432 | case NOP_OPCODE_MIPS: | |
18433 | default: | |
c67a084a NC |
18434 | opcode = nop_insn.insn_opcode; |
18435 | size = 4; | |
df58fc94 | 18436 | break; |
c67a084a | 18437 | } |
a19d8eb0 | 18438 | |
c67a084a NC |
18439 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
18440 | excess = bytes % size; | |
df58fc94 RS |
18441 | |
18442 | /* Handle the leading part if we're not inserting a whole number of | |
18443 | instructions, and make it the end of the fixed part of the frag. | |
18444 | Try to fit in a short microMIPS NOP if applicable and possible, | |
18445 | and use zeroes otherwise. */ | |
18446 | gas_assert (excess < 4); | |
18447 | fragp->fr_fix += excess; | |
18448 | switch (excess) | |
c67a084a | 18449 | { |
df58fc94 RS |
18450 | case 3: |
18451 | *p++ = '\0'; | |
18452 | /* Fall through. */ | |
18453 | case 2: | |
18454 | if (nop_opcode == NOP_OPCODE_MICROMIPS) | |
18455 | { | |
18456 | md_number_to_chars (p, micromips_nop16_insn.insn_opcode, 2); | |
18457 | p += 2; | |
18458 | break; | |
18459 | } | |
18460 | *p++ = '\0'; | |
18461 | /* Fall through. */ | |
18462 | case 1: | |
18463 | *p++ = '\0'; | |
18464 | /* Fall through. */ | |
18465 | case 0: | |
18466 | break; | |
a19d8eb0 | 18467 | } |
c67a084a NC |
18468 | |
18469 | md_number_to_chars (p, opcode, size); | |
18470 | fragp->fr_var = size; | |
a19d8eb0 CP |
18471 | } |
18472 | ||
252b5132 | 18473 | static void |
17a2f251 | 18474 | md_obj_begin (void) |
252b5132 RH |
18475 | { |
18476 | } | |
18477 | ||
18478 | static void | |
17a2f251 | 18479 | md_obj_end (void) |
252b5132 | 18480 | { |
54f4ddb3 | 18481 | /* Check for premature end, nesting errors, etc. */ |
252b5132 | 18482 | if (cur_proc_ptr) |
9a41af64 | 18483 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
18484 | } |
18485 | ||
18486 | static long | |
17a2f251 | 18487 | get_number (void) |
252b5132 RH |
18488 | { |
18489 | int negative = 0; | |
18490 | long val = 0; | |
18491 | ||
18492 | if (*input_line_pointer == '-') | |
18493 | { | |
18494 | ++input_line_pointer; | |
18495 | negative = 1; | |
18496 | } | |
3882b010 | 18497 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 18498 | as_bad (_("expected simple number")); |
252b5132 RH |
18499 | if (input_line_pointer[0] == '0') |
18500 | { | |
18501 | if (input_line_pointer[1] == 'x') | |
18502 | { | |
18503 | input_line_pointer += 2; | |
3882b010 | 18504 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
18505 | { |
18506 | val <<= 4; | |
18507 | val |= hex_value (*input_line_pointer++); | |
18508 | } | |
18509 | return negative ? -val : val; | |
18510 | } | |
18511 | else | |
18512 | { | |
18513 | ++input_line_pointer; | |
3882b010 | 18514 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
18515 | { |
18516 | val <<= 3; | |
18517 | val |= *input_line_pointer++ - '0'; | |
18518 | } | |
18519 | return negative ? -val : val; | |
18520 | } | |
18521 | } | |
3882b010 | 18522 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
18523 | { |
18524 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
18525 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 18526 | as_warn (_("invalid number")); |
252b5132 RH |
18527 | return -1; |
18528 | } | |
3882b010 | 18529 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
18530 | { |
18531 | val *= 10; | |
18532 | val += *input_line_pointer++ - '0'; | |
18533 | } | |
18534 | return negative ? -val : val; | |
18535 | } | |
18536 | ||
18537 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
18538 | is an initial number which is the ECOFF file index. In the non-ECOFF |
18539 | case .file implies DWARF-2. */ | |
18540 | ||
18541 | static void | |
17a2f251 | 18542 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 18543 | { |
ecb4347a DJ |
18544 | static int first_file_directive = 0; |
18545 | ||
c5dd6aab DJ |
18546 | if (ECOFF_DEBUGGING) |
18547 | { | |
18548 | get_number (); | |
18549 | s_app_file (0); | |
18550 | } | |
18551 | else | |
ecb4347a DJ |
18552 | { |
18553 | char *filename; | |
18554 | ||
18555 | filename = dwarf2_directive_file (0); | |
18556 | ||
18557 | /* Versions of GCC up to 3.1 start files with a ".file" | |
18558 | directive even for stabs output. Make sure that this | |
18559 | ".file" is handled. Note that you need a version of GCC | |
18560 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
18561 | if (filename != NULL && ! first_file_directive) | |
18562 | { | |
18563 | (void) new_logical_line (filename, -1); | |
c04f5787 | 18564 | s_app_file_string (filename, 0); |
ecb4347a DJ |
18565 | } |
18566 | first_file_directive = 1; | |
18567 | } | |
c5dd6aab DJ |
18568 | } |
18569 | ||
18570 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
18571 | |
18572 | static void | |
17a2f251 | 18573 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 18574 | { |
c5dd6aab DJ |
18575 | if (!ECOFF_DEBUGGING) |
18576 | dwarf2_directive_loc (0); | |
252b5132 RH |
18577 | } |
18578 | ||
252b5132 RH |
18579 | /* The .end directive. */ |
18580 | ||
18581 | static void | |
17a2f251 | 18582 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
18583 | { |
18584 | symbolS *p; | |
252b5132 | 18585 | |
7a621144 DJ |
18586 | /* Following functions need their own .frame and .cprestore directives. */ |
18587 | mips_frame_reg_valid = 0; | |
18588 | mips_cprestore_valid = 0; | |
18589 | ||
252b5132 RH |
18590 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
18591 | { | |
18592 | p = get_symbol (); | |
18593 | demand_empty_rest_of_line (); | |
18594 | } | |
18595 | else | |
18596 | p = NULL; | |
18597 | ||
14949570 | 18598 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
18599 | as_warn (_(".end not in text section")); |
18600 | ||
18601 | if (!cur_proc_ptr) | |
18602 | { | |
18603 | as_warn (_(".end directive without a preceding .ent directive.")); | |
18604 | demand_empty_rest_of_line (); | |
18605 | return; | |
18606 | } | |
18607 | ||
18608 | if (p != NULL) | |
18609 | { | |
9c2799c2 | 18610 | gas_assert (S_GET_NAME (p)); |
9b2f1d35 | 18611 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
252b5132 | 18612 | as_warn (_(".end symbol does not match .ent symbol.")); |
ecb4347a DJ |
18613 | |
18614 | if (debug_type == DEBUG_STABS) | |
18615 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
18616 | S_GET_NAME (p)); | |
252b5132 RH |
18617 | } |
18618 | else | |
18619 | as_warn (_(".end directive missing or unknown symbol")); | |
18620 | ||
2132e3a3 | 18621 | #ifdef OBJ_ELF |
9b2f1d35 EC |
18622 | /* Create an expression to calculate the size of the function. */ |
18623 | if (p && cur_proc_ptr) | |
18624 | { | |
18625 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
18626 | expressionS *exp = xmalloc (sizeof (expressionS)); | |
18627 | ||
18628 | obj->size = exp; | |
18629 | exp->X_op = O_subtract; | |
18630 | exp->X_add_symbol = symbol_temp_new_now (); | |
18631 | exp->X_op_symbol = p; | |
18632 | exp->X_add_number = 0; | |
18633 | ||
18634 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
18635 | } | |
18636 | ||
ecb4347a | 18637 | /* Generate a .pdr section. */ |
f43abd2b | 18638 | if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr) |
ecb4347a DJ |
18639 | { |
18640 | segT saved_seg = now_seg; | |
18641 | subsegT saved_subseg = now_subseg; | |
ecb4347a DJ |
18642 | expressionS exp; |
18643 | char *fragp; | |
252b5132 | 18644 | |
252b5132 | 18645 | #ifdef md_flush_pending_output |
ecb4347a | 18646 | md_flush_pending_output (); |
252b5132 RH |
18647 | #endif |
18648 | ||
9c2799c2 | 18649 | gas_assert (pdr_seg); |
ecb4347a | 18650 | subseg_set (pdr_seg, 0); |
252b5132 | 18651 | |
ecb4347a DJ |
18652 | /* Write the symbol. */ |
18653 | exp.X_op = O_symbol; | |
18654 | exp.X_add_symbol = p; | |
18655 | exp.X_add_number = 0; | |
18656 | emit_expr (&exp, 4); | |
252b5132 | 18657 | |
ecb4347a | 18658 | fragp = frag_more (7 * 4); |
252b5132 | 18659 | |
17a2f251 TS |
18660 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
18661 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
18662 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
18663 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
18664 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
18665 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
18666 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 18667 | |
ecb4347a DJ |
18668 | subseg_set (saved_seg, saved_subseg); |
18669 | } | |
18670 | #endif /* OBJ_ELF */ | |
252b5132 RH |
18671 | |
18672 | cur_proc_ptr = NULL; | |
18673 | } | |
18674 | ||
18675 | /* The .aent and .ent directives. */ | |
18676 | ||
18677 | static void | |
17a2f251 | 18678 | s_mips_ent (int aent) |
252b5132 | 18679 | { |
252b5132 | 18680 | symbolS *symbolP; |
252b5132 RH |
18681 | |
18682 | symbolP = get_symbol (); | |
18683 | if (*input_line_pointer == ',') | |
f9419b05 | 18684 | ++input_line_pointer; |
252b5132 | 18685 | SKIP_WHITESPACE (); |
3882b010 | 18686 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 18687 | || *input_line_pointer == '-') |
874e8986 | 18688 | get_number (); |
252b5132 | 18689 | |
14949570 | 18690 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
18691 | as_warn (_(".ent or .aent not in text section.")); |
18692 | ||
18693 | if (!aent && cur_proc_ptr) | |
9a41af64 | 18694 | as_warn (_("missing .end")); |
252b5132 RH |
18695 | |
18696 | if (!aent) | |
18697 | { | |
7a621144 DJ |
18698 | /* This function needs its own .frame and .cprestore directives. */ |
18699 | mips_frame_reg_valid = 0; | |
18700 | mips_cprestore_valid = 0; | |
18701 | ||
252b5132 RH |
18702 | cur_proc_ptr = &cur_proc; |
18703 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
18704 | ||
9b2f1d35 | 18705 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 18706 | |
f9419b05 | 18707 | ++numprocs; |
ecb4347a DJ |
18708 | |
18709 | if (debug_type == DEBUG_STABS) | |
18710 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
18711 | S_GET_NAME (symbolP)); | |
252b5132 RH |
18712 | } |
18713 | ||
7c0fc524 MR |
18714 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
18715 | ||
252b5132 RH |
18716 | demand_empty_rest_of_line (); |
18717 | } | |
18718 | ||
18719 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 18720 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 18721 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 18722 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
18723 | symbol table (in the mdebug section). */ |
18724 | ||
18725 | static void | |
17a2f251 | 18726 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 18727 | { |
ecb4347a | 18728 | #ifdef OBJ_ELF |
f43abd2b | 18729 | if (IS_ELF && !ECOFF_DEBUGGING) |
ecb4347a DJ |
18730 | { |
18731 | long val; | |
252b5132 | 18732 | |
ecb4347a DJ |
18733 | if (cur_proc_ptr == (procS *) NULL) |
18734 | { | |
18735 | as_warn (_(".frame outside of .ent")); | |
18736 | demand_empty_rest_of_line (); | |
18737 | return; | |
18738 | } | |
252b5132 | 18739 | |
ecb4347a DJ |
18740 | cur_proc_ptr->frame_reg = tc_get_register (1); |
18741 | ||
18742 | SKIP_WHITESPACE (); | |
18743 | if (*input_line_pointer++ != ',' | |
18744 | || get_absolute_expression_and_terminator (&val) != ',') | |
18745 | { | |
18746 | as_warn (_("Bad .frame directive")); | |
18747 | --input_line_pointer; | |
18748 | demand_empty_rest_of_line (); | |
18749 | return; | |
18750 | } | |
252b5132 | 18751 | |
ecb4347a DJ |
18752 | cur_proc_ptr->frame_offset = val; |
18753 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 18754 | |
252b5132 | 18755 | demand_empty_rest_of_line (); |
252b5132 | 18756 | } |
ecb4347a DJ |
18757 | else |
18758 | #endif /* OBJ_ELF */ | |
18759 | s_ignore (ignore); | |
252b5132 RH |
18760 | } |
18761 | ||
bdaaa2e1 KH |
18762 | /* The .fmask and .mask directives. If the mdebug section is present |
18763 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 18764 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 18765 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
18766 | make reference to the ecoff symbol table (in the mdebug section). */ |
18767 | ||
18768 | static void | |
17a2f251 | 18769 | s_mips_mask (int reg_type) |
252b5132 | 18770 | { |
ecb4347a | 18771 | #ifdef OBJ_ELF |
f43abd2b | 18772 | if (IS_ELF && !ECOFF_DEBUGGING) |
252b5132 | 18773 | { |
ecb4347a | 18774 | long mask, off; |
252b5132 | 18775 | |
ecb4347a DJ |
18776 | if (cur_proc_ptr == (procS *) NULL) |
18777 | { | |
18778 | as_warn (_(".mask/.fmask outside of .ent")); | |
18779 | demand_empty_rest_of_line (); | |
18780 | return; | |
18781 | } | |
252b5132 | 18782 | |
ecb4347a DJ |
18783 | if (get_absolute_expression_and_terminator (&mask) != ',') |
18784 | { | |
18785 | as_warn (_("Bad .mask/.fmask directive")); | |
18786 | --input_line_pointer; | |
18787 | demand_empty_rest_of_line (); | |
18788 | return; | |
18789 | } | |
252b5132 | 18790 | |
ecb4347a DJ |
18791 | off = get_absolute_expression (); |
18792 | ||
18793 | if (reg_type == 'F') | |
18794 | { | |
18795 | cur_proc_ptr->fpreg_mask = mask; | |
18796 | cur_proc_ptr->fpreg_offset = off; | |
18797 | } | |
18798 | else | |
18799 | { | |
18800 | cur_proc_ptr->reg_mask = mask; | |
18801 | cur_proc_ptr->reg_offset = off; | |
18802 | } | |
18803 | ||
18804 | demand_empty_rest_of_line (); | |
252b5132 RH |
18805 | } |
18806 | else | |
ecb4347a DJ |
18807 | #endif /* OBJ_ELF */ |
18808 | s_ignore (reg_type); | |
252b5132 RH |
18809 | } |
18810 | ||
316f5878 RS |
18811 | /* A table describing all the processors gas knows about. Names are |
18812 | matched in the order listed. | |
e7af610e | 18813 | |
316f5878 RS |
18814 | To ease comparison, please keep this table in the same order as |
18815 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
18816 | static const struct mips_cpu_info mips_cpu_info_table[] = |
18817 | { | |
316f5878 | 18818 | /* Entries for generic ISAs */ |
ad3fea08 TS |
18819 | { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 }, |
18820 | { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 }, | |
18821 | { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 }, | |
18822 | { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 }, | |
18823 | { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 }, | |
18824 | { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 }, | |
18825 | { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18826 | { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 }, | |
18827 | { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 }, | |
316f5878 RS |
18828 | |
18829 | /* MIPS I */ | |
ad3fea08 TS |
18830 | { "r3000", 0, ISA_MIPS1, CPU_R3000 }, |
18831 | { "r2000", 0, ISA_MIPS1, CPU_R3000 }, | |
18832 | { "r3900", 0, ISA_MIPS1, CPU_R3900 }, | |
316f5878 RS |
18833 | |
18834 | /* MIPS II */ | |
ad3fea08 | 18835 | { "r6000", 0, ISA_MIPS2, CPU_R6000 }, |
316f5878 RS |
18836 | |
18837 | /* MIPS III */ | |
ad3fea08 TS |
18838 | { "r4000", 0, ISA_MIPS3, CPU_R4000 }, |
18839 | { "r4010", 0, ISA_MIPS2, CPU_R4010 }, | |
18840 | { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, | |
18841 | { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, | |
18842 | { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, | |
18843 | { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, | |
18844 | { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, | |
18845 | { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, | |
18846 | { "r4400", 0, ISA_MIPS3, CPU_R4400 }, | |
18847 | { "r4600", 0, ISA_MIPS3, CPU_R4600 }, | |
18848 | { "orion", 0, ISA_MIPS3, CPU_R4600 }, | |
18849 | { "r4650", 0, ISA_MIPS3, CPU_R4650 }, | |
b15591bb AN |
18850 | /* ST Microelectronics Loongson 2E and 2F cores */ |
18851 | { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E }, | |
18852 | { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F }, | |
316f5878 RS |
18853 | |
18854 | /* MIPS IV */ | |
ad3fea08 TS |
18855 | { "r8000", 0, ISA_MIPS4, CPU_R8000 }, |
18856 | { "r10000", 0, ISA_MIPS4, CPU_R10000 }, | |
18857 | { "r12000", 0, ISA_MIPS4, CPU_R12000 }, | |
3aa3176b TS |
18858 | { "r14000", 0, ISA_MIPS4, CPU_R14000 }, |
18859 | { "r16000", 0, ISA_MIPS4, CPU_R16000 }, | |
ad3fea08 TS |
18860 | { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, |
18861 | { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, | |
18862 | { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, | |
18863 | { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, | |
18864 | { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, | |
18865 | { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, | |
18866 | { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, | |
18867 | { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, | |
18868 | { "rm7000", 0, ISA_MIPS4, CPU_RM7000 }, | |
18869 | { "rm9000", 0, ISA_MIPS4, CPU_RM9000 }, | |
316f5878 RS |
18870 | |
18871 | /* MIPS 32 */ | |
ad3fea08 TS |
18872 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32 }, |
18873 | { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, | |
18874 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, | |
18875 | { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 }, | |
18876 | ||
18877 | /* MIPS 32 Release 2 */ | |
18878 | { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18879 | { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18880 | { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18881 | { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18882 | { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18883 | { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ad3fea08 | 18884 | { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 | 18885 | { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
ad3fea08 | 18886 | { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 RS |
18887 | { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
18888 | /* Deprecated forms of the above. */ | |
18889 | { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ad3fea08 | 18890 | { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 18891 | /* 24KE is a 24K with DSP ASE, other ASEs are optional. */ |
ad3fea08 | 18892 | { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 | 18893 | { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
ad3fea08 | 18894 | { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 RS |
18895 | { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
18896 | /* Deprecated forms of the above. */ | |
18897 | { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
65263ce3 | 18898 | { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 18899 | /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */ |
a360e743 TS |
18900 | { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
18901 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
18902 | { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
18903 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
a360e743 TS |
18904 | { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
18905 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
18906 | { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
18907 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18908 | /* Deprecated forms of the above. */ | |
18909 | { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
18910 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
a360e743 TS |
18911 | { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
18912 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
18913 | /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */ |
18914 | { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
18915 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
18916 | { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
18917 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
18918 | { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
18919 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
18920 | { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
18921 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18922 | { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
18923 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18924 | /* Deprecated forms of the above. */ | |
18925 | { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
18926 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
18927 | { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
18928 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
30f8113a SL |
18929 | /* 1004K cores are multiprocessor versions of the 34K. */ |
18930 | { "1004kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
18931 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18932 | { "1004kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
18933 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18934 | { "1004kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
18935 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18936 | { "1004kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
18937 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
32b26a03 | 18938 | |
316f5878 | 18939 | /* MIPS 64 */ |
ad3fea08 TS |
18940 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, |
18941 | { "5kf", 0, ISA_MIPS64, CPU_MIPS64 }, | |
18942 | { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
7764b395 | 18943 | { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, |
ad3fea08 | 18944 | |
c7a23324 | 18945 | /* Broadcom SB-1 CPU core */ |
65263ce3 TS |
18946 | { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, |
18947 | ISA_MIPS64, CPU_SB1 }, | |
1e85aad8 JW |
18948 | /* Broadcom SB-1A CPU core */ |
18949 | { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, | |
18950 | ISA_MIPS64, CPU_SB1 }, | |
d051516a NC |
18951 | |
18952 | { "loongson3a", 0, ISA_MIPS64, CPU_LOONGSON_3A }, | |
e7af610e | 18953 | |
ed163775 MR |
18954 | /* MIPS 64 Release 2 */ |
18955 | ||
967344c6 AN |
18956 | /* Cavium Networks Octeon CPU core */ |
18957 | { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON }, | |
18958 | ||
52b6b6b9 JM |
18959 | /* RMI Xlr */ |
18960 | { "xlr", 0, ISA_MIPS64, CPU_XLR }, | |
18961 | ||
316f5878 RS |
18962 | /* End marker */ |
18963 | { NULL, 0, 0, 0 } | |
18964 | }; | |
e7af610e | 18965 | |
84ea6cf2 | 18966 | |
316f5878 RS |
18967 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
18968 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 18969 | |
316f5878 | 18970 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 18971 | |
b34976b6 | 18972 | static bfd_boolean |
17a2f251 | 18973 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
18974 | { |
18975 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
18976 | given++, canonical++; | |
18977 | ||
18978 | return ((*given == 0 && *canonical == 0) | |
18979 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
18980 | } | |
18981 | ||
18982 | ||
18983 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
18984 | CPU name. We've traditionally allowed a lot of variation here. | |
18985 | ||
18986 | Note: this function is shared between GCC and GAS. */ | |
18987 | ||
b34976b6 | 18988 | static bfd_boolean |
17a2f251 | 18989 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
18990 | { |
18991 | /* First see if the name matches exactly, or with a final "000" | |
18992 | turned into "k". */ | |
18993 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 18994 | return TRUE; |
316f5878 RS |
18995 | |
18996 | /* If not, try comparing based on numerical designation alone. | |
18997 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
18998 | if (TOLOWER (*given) == 'r') | |
18999 | given++; | |
19000 | if (!ISDIGIT (*given)) | |
b34976b6 | 19001 | return FALSE; |
316f5878 RS |
19002 | |
19003 | /* Skip over some well-known prefixes in the canonical name, | |
19004 | hoping to find a number there too. */ | |
19005 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
19006 | canonical += 2; | |
19007 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
19008 | canonical += 2; | |
19009 | else if (TOLOWER (canonical[0]) == 'r') | |
19010 | canonical += 1; | |
19011 | ||
19012 | return mips_strict_matching_cpu_name_p (canonical, given); | |
19013 | } | |
19014 | ||
19015 | ||
19016 | /* Parse an option that takes the name of a processor as its argument. | |
19017 | OPTION is the name of the option and CPU_STRING is the argument. | |
19018 | Return the corresponding processor enumeration if the CPU_STRING is | |
19019 | recognized, otherwise report an error and return null. | |
19020 | ||
19021 | A similar function exists in GCC. */ | |
e7af610e NC |
19022 | |
19023 | static const struct mips_cpu_info * | |
17a2f251 | 19024 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 19025 | { |
316f5878 | 19026 | const struct mips_cpu_info *p; |
e7af610e | 19027 | |
316f5878 RS |
19028 | /* 'from-abi' selects the most compatible architecture for the given |
19029 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
19030 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
19031 | version. Look first at the -mgp options, if given, otherwise base | |
19032 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 19033 | |
316f5878 RS |
19034 | Treat NO_ABI like the EABIs. One reason to do this is that the |
19035 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
19036 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
19037 | 'mips64', just as we did in the days before 'from-abi'. */ | |
19038 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
19039 | { | |
19040 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
19041 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
19042 | ||
19043 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
19044 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
19045 | ||
19046 | if (file_mips_gp32 >= 0) | |
19047 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
19048 | ||
19049 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
19050 | ? ISA_MIPS3 | |
19051 | : ISA_MIPS1); | |
19052 | } | |
19053 | ||
19054 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
19055 | if (strcasecmp (cpu_string, "default") == 0) | |
19056 | return 0; | |
19057 | ||
19058 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
19059 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
19060 | return p; | |
19061 | ||
20203fb9 | 19062 | as_bad (_("Bad value (%s) for %s"), cpu_string, option); |
316f5878 | 19063 | return 0; |
e7af610e NC |
19064 | } |
19065 | ||
316f5878 RS |
19066 | /* Return the canonical processor information for ISA (a member of the |
19067 | ISA_MIPS* enumeration). */ | |
19068 | ||
e7af610e | 19069 | static const struct mips_cpu_info * |
17a2f251 | 19070 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
19071 | { |
19072 | int i; | |
19073 | ||
19074 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
ad3fea08 | 19075 | if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA) |
316f5878 | 19076 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
19077 | return (&mips_cpu_info_table[i]); |
19078 | ||
e972090a | 19079 | return NULL; |
e7af610e | 19080 | } |
fef14a42 TS |
19081 | |
19082 | static const struct mips_cpu_info * | |
17a2f251 | 19083 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
19084 | { |
19085 | int i; | |
19086 | ||
19087 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
19088 | if (arch == mips_cpu_info_table[i].cpu) | |
19089 | return (&mips_cpu_info_table[i]); | |
19090 | ||
19091 | return NULL; | |
19092 | } | |
316f5878 RS |
19093 | \f |
19094 | static void | |
17a2f251 | 19095 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
19096 | { |
19097 | if (*first_p) | |
19098 | { | |
19099 | fprintf (stream, "%24s", ""); | |
19100 | *col_p = 24; | |
19101 | } | |
19102 | else | |
19103 | { | |
19104 | fprintf (stream, ", "); | |
19105 | *col_p += 2; | |
19106 | } | |
e7af610e | 19107 | |
316f5878 RS |
19108 | if (*col_p + strlen (string) > 72) |
19109 | { | |
19110 | fprintf (stream, "\n%24s", ""); | |
19111 | *col_p = 24; | |
19112 | } | |
19113 | ||
19114 | fprintf (stream, "%s", string); | |
19115 | *col_p += strlen (string); | |
19116 | ||
19117 | *first_p = 0; | |
19118 | } | |
19119 | ||
19120 | void | |
17a2f251 | 19121 | md_show_usage (FILE *stream) |
e7af610e | 19122 | { |
316f5878 RS |
19123 | int column, first; |
19124 | size_t i; | |
19125 | ||
19126 | fprintf (stream, _("\ | |
19127 | MIPS options:\n\ | |
316f5878 RS |
19128 | -EB generate big endian output\n\ |
19129 | -EL generate little endian output\n\ | |
19130 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
19131 | -G NUM allow referencing objects up to NUM bytes\n\ | |
19132 | implicitly with the gp register [default 8]\n")); | |
19133 | fprintf (stream, _("\ | |
19134 | -mips1 generate MIPS ISA I instructions\n\ | |
19135 | -mips2 generate MIPS ISA II instructions\n\ | |
19136 | -mips3 generate MIPS ISA III instructions\n\ | |
19137 | -mips4 generate MIPS ISA IV instructions\n\ | |
19138 | -mips5 generate MIPS ISA V instructions\n\ | |
19139 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 19140 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 | 19141 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 19142 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
316f5878 RS |
19143 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
19144 | ||
19145 | first = 1; | |
e7af610e NC |
19146 | |
19147 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
19148 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
19149 | show (stream, "from-abi", &column, &first); | |
19150 | fputc ('\n', stream); | |
e7af610e | 19151 | |
316f5878 RS |
19152 | fprintf (stream, _("\ |
19153 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
19154 | -no-mCPU don't generate code specific to CPU.\n\ | |
19155 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
19156 | ||
19157 | first = 1; | |
19158 | ||
19159 | show (stream, "3900", &column, &first); | |
19160 | show (stream, "4010", &column, &first); | |
19161 | show (stream, "4100", &column, &first); | |
19162 | show (stream, "4650", &column, &first); | |
19163 | fputc ('\n', stream); | |
19164 | ||
19165 | fprintf (stream, _("\ | |
19166 | -mips16 generate mips16 instructions\n\ | |
19167 | -no-mips16 do not generate mips16 instructions\n")); | |
19168 | fprintf (stream, _("\ | |
df58fc94 RS |
19169 | -mmicromips generate microMIPS instructions\n\ |
19170 | -mno-micromips do not generate microMIPS instructions\n")); | |
19171 | fprintf (stream, _("\ | |
e16bfa71 TS |
19172 | -msmartmips generate smartmips instructions\n\ |
19173 | -mno-smartmips do not generate smartmips instructions\n")); | |
19174 | fprintf (stream, _("\ | |
74cd071d CF |
19175 | -mdsp generate DSP instructions\n\ |
19176 | -mno-dsp do not generate DSP instructions\n")); | |
19177 | fprintf (stream, _("\ | |
8b082fb1 TS |
19178 | -mdspr2 generate DSP R2 instructions\n\ |
19179 | -mno-dspr2 do not generate DSP R2 instructions\n")); | |
19180 | fprintf (stream, _("\ | |
ef2e4d86 CF |
19181 | -mmt generate MT instructions\n\ |
19182 | -mno-mt do not generate MT instructions\n")); | |
19183 | fprintf (stream, _("\ | |
c67a084a NC |
19184 | -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\ |
19185 | -mfix-loongson2f-nop work around Loongson2F NOP errata\n\ | |
d766e8ec | 19186 | -mfix-vr4120 work around certain VR4120 errata\n\ |
7d8e00cf | 19187 | -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ |
6a32d874 | 19188 | -mfix-24k insert a nop after ERET and DERET instructions\n\ |
d954098f | 19189 | -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\ |
316f5878 RS |
19190 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
19191 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
aed1a261 | 19192 | -msym32 assume all symbols have 32-bit values\n\ |
316f5878 RS |
19193 | -O0 remove unneeded NOPs, do not swap branches\n\ |
19194 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
19195 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ |
19196 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
037b32b9 AN |
19197 | fprintf (stream, _("\ |
19198 | -mhard-float allow floating-point instructions\n\ | |
19199 | -msoft-float do not allow floating-point instructions\n\ | |
19200 | -msingle-float only allow 32-bit floating-point operations\n\ | |
19201 | -mdouble-float allow 32-bit and 64-bit floating-point operations\n\ | |
19202 | --[no-]construct-floats [dis]allow floating point values to be constructed\n" | |
19203 | )); | |
316f5878 RS |
19204 | #ifdef OBJ_ELF |
19205 | fprintf (stream, _("\ | |
19206 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
861fb55a | 19207 | -call_nonpic generate non-PIC code that can operate with DSOs\n\ |
0c000745 | 19208 | -mvxworks-pic generate VxWorks position independent code\n\ |
861fb55a | 19209 | -non_shared do not generate code that can operate with DSOs\n\ |
316f5878 | 19210 | -xgot assume a 32 bit GOT\n\ |
dcd410fe | 19211 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
bbe506e8 | 19212 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
d821e36b | 19213 | position dependent (non shared) code\n\ |
316f5878 RS |
19214 | -mabi=ABI create ABI conformant object file for:\n")); |
19215 | ||
19216 | first = 1; | |
19217 | ||
19218 | show (stream, "32", &column, &first); | |
19219 | show (stream, "o64", &column, &first); | |
19220 | show (stream, "n32", &column, &first); | |
19221 | show (stream, "64", &column, &first); | |
19222 | show (stream, "eabi", &column, &first); | |
19223 | ||
19224 | fputc ('\n', stream); | |
19225 | ||
19226 | fprintf (stream, _("\ | |
19227 | -32 create o32 ABI object file (default)\n\ | |
19228 | -n32 create n32 ABI object file\n\ | |
19229 | -64 create 64 ABI object file\n")); | |
19230 | #endif | |
e7af610e | 19231 | } |
14e777e0 | 19232 | |
1575952e | 19233 | #ifdef TE_IRIX |
14e777e0 | 19234 | enum dwarf2_format |
413a266c | 19235 | mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED) |
14e777e0 | 19236 | { |
369943fe | 19237 | if (HAVE_64BIT_SYMBOLS) |
1575952e | 19238 | return dwarf2_format_64bit_irix; |
14e777e0 KB |
19239 | else |
19240 | return dwarf2_format_32bit; | |
19241 | } | |
1575952e | 19242 | #endif |
73369e65 EC |
19243 | |
19244 | int | |
19245 | mips_dwarf2_addr_size (void) | |
19246 | { | |
6b6b3450 | 19247 | if (HAVE_64BIT_OBJECTS) |
73369e65 | 19248 | return 8; |
73369e65 EC |
19249 | else |
19250 | return 4; | |
19251 | } | |
5862107c EC |
19252 | |
19253 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
19254 | void | |
19255 | mips_cfi_frame_initial_instructions (void) | |
19256 | { | |
19257 | cfi_add_CFA_def_cfa_register (SP); | |
19258 | } | |
19259 | ||
707bfff6 TS |
19260 | int |
19261 | tc_mips_regname_to_dw2regnum (char *regname) | |
19262 | { | |
19263 | unsigned int regnum = -1; | |
19264 | unsigned int reg; | |
19265 | ||
19266 | if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®)) | |
19267 | regnum = reg; | |
19268 | ||
19269 | return regnum; | |
19270 | } |