Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
81912461 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
db9b2be4 | 3 | 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011 |
c67a084a | 4 | Free Software Foundation, Inc. |
252b5132 RH |
5 | Contributed by the OSF and Ralph Campbell. |
6 | Written by Keith Knowles and Ralph Campbell, working independently. | |
7 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
8 | Support. | |
9 | ||
10 | This file is part of GAS. | |
11 | ||
12 | GAS is free software; you can redistribute it and/or modify | |
13 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 14 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
15 | any later version. |
16 | ||
17 | GAS is distributed in the hope that it will be useful, | |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
21 | ||
22 | You should have received a copy of the GNU General Public License | |
23 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
24 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
25 | 02110-1301, USA. */ | |
252b5132 RH |
26 | |
27 | #include "as.h" | |
28 | #include "config.h" | |
29 | #include "subsegs.h" | |
3882b010 | 30 | #include "safe-ctype.h" |
252b5132 | 31 | |
252b5132 RH |
32 | #include "opcode/mips.h" |
33 | #include "itbl-ops.h" | |
c5dd6aab | 34 | #include "dwarf2dbg.h" |
5862107c | 35 | #include "dw2gencfi.h" |
252b5132 RH |
36 | |
37 | #ifdef DEBUG | |
38 | #define DBG(x) printf x | |
39 | #else | |
40 | #define DBG(x) | |
41 | #endif | |
42 | ||
43 | #ifdef OBJ_MAYBE_ELF | |
44 | /* Clean up namespace so we can include obj-elf.h too. */ | |
17a2f251 TS |
45 | static int mips_output_flavor (void); |
46 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
47 | #undef OBJ_PROCESS_STAB |
48 | #undef OUTPUT_FLAVOR | |
49 | #undef S_GET_ALIGN | |
50 | #undef S_GET_SIZE | |
51 | #undef S_SET_ALIGN | |
52 | #undef S_SET_SIZE | |
252b5132 RH |
53 | #undef obj_frob_file |
54 | #undef obj_frob_file_after_relocs | |
55 | #undef obj_frob_symbol | |
56 | #undef obj_pop_insert | |
57 | #undef obj_sec_sym_ok_for_reloc | |
58 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
59 | ||
60 | #include "obj-elf.h" | |
61 | /* Fix any of them that we actually care about. */ | |
62 | #undef OUTPUT_FLAVOR | |
63 | #define OUTPUT_FLAVOR mips_output_flavor() | |
64 | #endif | |
65 | ||
66 | #if defined (OBJ_ELF) | |
67 | #include "elf/mips.h" | |
68 | #endif | |
69 | ||
70 | #ifndef ECOFF_DEBUGGING | |
71 | #define NO_ECOFF_DEBUGGING | |
72 | #define ECOFF_DEBUGGING 0 | |
73 | #endif | |
74 | ||
ecb4347a DJ |
75 | int mips_flag_mdebug = -1; |
76 | ||
dcd410fe RO |
77 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
78 | linker doesn't know about and discards them, but relocations against them | |
79 | remain, leading to rld crashes. */ | |
80 | #ifdef TE_IRIX | |
81 | int mips_flag_pdr = FALSE; | |
82 | #else | |
83 | int mips_flag_pdr = TRUE; | |
84 | #endif | |
85 | ||
252b5132 RH |
86 | #include "ecoff.h" |
87 | ||
88 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
89 | static char *mips_regmask_frag; | |
90 | #endif | |
91 | ||
85b51719 | 92 | #define ZERO 0 |
741fe287 | 93 | #define ATREG 1 |
df58fc94 RS |
94 | #define S0 16 |
95 | #define S7 23 | |
252b5132 RH |
96 | #define TREG 24 |
97 | #define PIC_CALL_REG 25 | |
98 | #define KT0 26 | |
99 | #define KT1 27 | |
100 | #define GP 28 | |
101 | #define SP 29 | |
102 | #define FP 30 | |
103 | #define RA 31 | |
104 | ||
105 | #define ILLEGAL_REG (32) | |
106 | ||
741fe287 MR |
107 | #define AT mips_opts.at |
108 | ||
252b5132 RH |
109 | /* Allow override of standard little-endian ECOFF format. */ |
110 | ||
111 | #ifndef ECOFF_LITTLE_FORMAT | |
112 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
113 | #endif | |
114 | ||
115 | extern int target_big_endian; | |
116 | ||
252b5132 | 117 | /* The name of the readonly data section. */ |
4d0d148d | 118 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ |
252b5132 | 119 | ? ".rdata" \ |
056350c6 NC |
120 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
121 | ? ".rdata" \ | |
252b5132 RH |
122 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
123 | ? ".rodata" \ | |
124 | : (abort (), "")) | |
125 | ||
a4e06468 RS |
126 | /* Ways in which an instruction can be "appended" to the output. */ |
127 | enum append_method { | |
128 | /* Just add it normally. */ | |
129 | APPEND_ADD, | |
130 | ||
131 | /* Add it normally and then add a nop. */ | |
132 | APPEND_ADD_WITH_NOP, | |
133 | ||
134 | /* Turn an instruction with a delay slot into a "compact" version. */ | |
135 | APPEND_ADD_COMPACT, | |
136 | ||
137 | /* Insert the instruction before the last one. */ | |
138 | APPEND_SWAP | |
139 | }; | |
140 | ||
47e39b9d RS |
141 | /* Information about an instruction, including its format, operands |
142 | and fixups. */ | |
143 | struct mips_cl_insn | |
144 | { | |
145 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ | |
146 | const struct mips_opcode *insn_mo; | |
147 | ||
148 | /* True if this is a mips16 instruction and if we want the extended | |
149 | form of INSN_MO. */ | |
150 | bfd_boolean use_extend; | |
151 | ||
152 | /* The 16-bit extension instruction to use when USE_EXTEND is true. */ | |
153 | unsigned short extend; | |
154 | ||
155 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is | |
156 | a copy of INSN_MO->match with the operands filled in. */ | |
157 | unsigned long insn_opcode; | |
158 | ||
159 | /* The frag that contains the instruction. */ | |
160 | struct frag *frag; | |
161 | ||
162 | /* The offset into FRAG of the first instruction byte. */ | |
163 | long where; | |
164 | ||
165 | /* The relocs associated with the instruction, if any. */ | |
166 | fixS *fixp[3]; | |
167 | ||
a38419a5 RS |
168 | /* True if this entry cannot be moved from its current position. */ |
169 | unsigned int fixed_p : 1; | |
47e39b9d | 170 | |
708587a4 | 171 | /* True if this instruction occurred in a .set noreorder block. */ |
47e39b9d RS |
172 | unsigned int noreorder_p : 1; |
173 | ||
2fa15973 RS |
174 | /* True for mips16 instructions that jump to an absolute address. */ |
175 | unsigned int mips16_absolute_jump_p : 1; | |
15be625d CM |
176 | |
177 | /* True if this instruction is complete. */ | |
178 | unsigned int complete_p : 1; | |
47e39b9d RS |
179 | }; |
180 | ||
a325df1d TS |
181 | /* The ABI to use. */ |
182 | enum mips_abi_level | |
183 | { | |
184 | NO_ABI = 0, | |
185 | O32_ABI, | |
186 | O64_ABI, | |
187 | N32_ABI, | |
188 | N64_ABI, | |
189 | EABI_ABI | |
190 | }; | |
191 | ||
192 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 193 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 194 | |
143d77c5 EC |
195 | /* Whether or not we have code that can call pic code. */ |
196 | int mips_abicalls = FALSE; | |
197 | ||
aa6975fb ILT |
198 | /* Whether or not we have code which can be put into a shared |
199 | library. */ | |
200 | static bfd_boolean mips_in_shared = TRUE; | |
201 | ||
252b5132 RH |
202 | /* This is the set of options which may be modified by the .set |
203 | pseudo-op. We use a struct so that .set push and .set pop are more | |
204 | reliable. */ | |
205 | ||
e972090a NC |
206 | struct mips_set_options |
207 | { | |
252b5132 RH |
208 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
209 | if it has not been initialized. Changed by `.set mipsN', and the | |
210 | -mipsN command line option, and the default CPU. */ | |
211 | int isa; | |
1f25f5d3 CD |
212 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
213 | if they have not been initialized. Changed by `.set <asename>', by | |
214 | command line options, and based on the default architecture. */ | |
215 | int ase_mips3d; | |
deec1734 | 216 | int ase_mdmx; |
e16bfa71 | 217 | int ase_smartmips; |
74cd071d | 218 | int ase_dsp; |
8b082fb1 | 219 | int ase_dspr2; |
ef2e4d86 | 220 | int ase_mt; |
dec0624d | 221 | int ase_mcu; |
252b5132 RH |
222 | /* Whether we are assembling for the mips16 processor. 0 if we are |
223 | not, 1 if we are, and -1 if the value has not been initialized. | |
224 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
225 | -nomips16 command line options, and the default CPU. */ | |
226 | int mips16; | |
df58fc94 RS |
227 | /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not, |
228 | 1 if we are, and -1 if the value has not been initialized. Changed | |
229 | by `.set micromips' and `.set nomicromips', and the -mmicromips | |
230 | and -mno-micromips command line options, and the default CPU. */ | |
231 | int micromips; | |
252b5132 RH |
232 | /* Non-zero if we should not reorder instructions. Changed by `.set |
233 | reorder' and `.set noreorder'. */ | |
234 | int noreorder; | |
741fe287 MR |
235 | /* Non-zero if we should not permit the register designated "assembler |
236 | temporary" to be used in instructions. The value is the register | |
237 | number, normally $at ($1). Changed by `.set at=REG', `.set noat' | |
238 | (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */ | |
239 | unsigned int at; | |
252b5132 RH |
240 | /* Non-zero if we should warn when a macro instruction expands into |
241 | more than one machine instruction. Changed by `.set nomacro' and | |
242 | `.set macro'. */ | |
243 | int warn_about_macros; | |
244 | /* Non-zero if we should not move instructions. Changed by `.set | |
245 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
246 | int nomove; | |
247 | /* Non-zero if we should not optimize branches by moving the target | |
248 | of the branch into the delay slot. Actually, we don't perform | |
249 | this optimization anyhow. Changed by `.set bopt' and `.set | |
250 | nobopt'. */ | |
251 | int nobopt; | |
252 | /* Non-zero if we should not autoextend mips16 instructions. | |
253 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
254 | int noautoextend; | |
a325df1d TS |
255 | /* Restrict general purpose registers and floating point registers |
256 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
257 | is passed but can changed if the assembler code uses .set mipsN. */ | |
258 | int gp32; | |
259 | int fp32; | |
fef14a42 TS |
260 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
261 | command line option, and the default CPU. */ | |
262 | int arch; | |
aed1a261 RS |
263 | /* True if ".set sym32" is in effect. */ |
264 | bfd_boolean sym32; | |
037b32b9 AN |
265 | /* True if floating-point operations are not allowed. Changed by .set |
266 | softfloat or .set hardfloat, by command line options -msoft-float or | |
267 | -mhard-float. The default is false. */ | |
268 | bfd_boolean soft_float; | |
269 | ||
270 | /* True if only single-precision floating-point operations are allowed. | |
271 | Changed by .set singlefloat or .set doublefloat, command-line options | |
272 | -msingle-float or -mdouble-float. The default is false. */ | |
273 | bfd_boolean single_float; | |
252b5132 RH |
274 | }; |
275 | ||
037b32b9 AN |
276 | /* This is the struct we use to hold the current set of options. Note |
277 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to | |
278 | -1 to indicate that they have not been initialized. */ | |
279 | ||
a325df1d | 280 | /* True if -mgp32 was passed. */ |
a8e8e863 | 281 | static int file_mips_gp32 = -1; |
a325df1d TS |
282 | |
283 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 284 | static int file_mips_fp32 = -1; |
a325df1d | 285 | |
037b32b9 AN |
286 | /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */ |
287 | static int file_mips_soft_float = 0; | |
288 | ||
289 | /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */ | |
290 | static int file_mips_single_float = 0; | |
252b5132 | 291 | |
e972090a NC |
292 | static struct mips_set_options mips_opts = |
293 | { | |
037b32b9 AN |
294 | /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1, |
295 | /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1, | |
dec0624d MR |
296 | /* ase_mcu */ -1, /* mips16 */ -1, /* micromips */ -1, /* noreorder */ 0, |
297 | /* at */ ATREG, /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0, | |
037b32b9 AN |
298 | /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN, |
299 | /* sym32 */ FALSE, /* soft_float */ FALSE, /* single_float */ FALSE | |
e7af610e | 300 | }; |
252b5132 RH |
301 | |
302 | /* These variables are filled in with the masks of registers used. | |
303 | The object format code reads them and puts them in the appropriate | |
304 | place. */ | |
305 | unsigned long mips_gprmask; | |
306 | unsigned long mips_cprmask[4]; | |
307 | ||
308 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 309 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 310 | |
738f4d98 | 311 | /* True if any MIPS16 code was produced. */ |
a4672219 TS |
312 | static int file_ase_mips16; |
313 | ||
3994f87e TS |
314 | #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \ |
315 | || mips_opts.isa == ISA_MIPS32R2 \ | |
316 | || mips_opts.isa == ISA_MIPS64 \ | |
317 | || mips_opts.isa == ISA_MIPS64R2) | |
318 | ||
df58fc94 RS |
319 | /* True if any microMIPS code was produced. */ |
320 | static int file_ase_micromips; | |
321 | ||
b12dd2e4 CF |
322 | /* True if we want to create R_MIPS_JALR for jalr $25. */ |
323 | #ifdef TE_IRIX | |
1180b5a4 | 324 | #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI |
b12dd2e4 | 325 | #else |
1180b5a4 RS |
326 | /* As a GNU extension, we use R_MIPS_JALR for o32 too. However, |
327 | because there's no place for any addend, the only acceptable | |
328 | expression is a bare symbol. */ | |
329 | #define MIPS_JALR_HINT_P(EXPR) \ | |
330 | (!HAVE_IN_PLACE_ADDENDS \ | |
331 | || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0)) | |
b12dd2e4 CF |
332 | #endif |
333 | ||
1f25f5d3 CD |
334 | /* True if -mips3d was passed or implied by arguments passed on the |
335 | command line (e.g., by -march). */ | |
336 | static int file_ase_mips3d; | |
337 | ||
deec1734 CD |
338 | /* True if -mdmx was passed or implied by arguments passed on the |
339 | command line (e.g., by -march). */ | |
340 | static int file_ase_mdmx; | |
341 | ||
e16bfa71 TS |
342 | /* True if -msmartmips was passed or implied by arguments passed on the |
343 | command line (e.g., by -march). */ | |
344 | static int file_ase_smartmips; | |
345 | ||
ad3fea08 TS |
346 | #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \ |
347 | || mips_opts.isa == ISA_MIPS32R2) | |
e16bfa71 | 348 | |
74cd071d CF |
349 | /* True if -mdsp was passed or implied by arguments passed on the |
350 | command line (e.g., by -march). */ | |
351 | static int file_ase_dsp; | |
352 | ||
ad3fea08 TS |
353 | #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
354 | || mips_opts.isa == ISA_MIPS64R2) | |
355 | ||
65263ce3 TS |
356 | #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2) |
357 | ||
8b082fb1 TS |
358 | /* True if -mdspr2 was passed or implied by arguments passed on the |
359 | command line (e.g., by -march). */ | |
360 | static int file_ase_dspr2; | |
361 | ||
362 | #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \ | |
363 | || mips_opts.isa == ISA_MIPS64R2) | |
364 | ||
ef2e4d86 CF |
365 | /* True if -mmt was passed or implied by arguments passed on the |
366 | command line (e.g., by -march). */ | |
367 | static int file_ase_mt; | |
368 | ||
ad3fea08 TS |
369 | #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
370 | || mips_opts.isa == ISA_MIPS64R2) | |
371 | ||
dec0624d MR |
372 | #define ISA_SUPPORTS_MCU_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
373 | || mips_opts.isa == ISA_MIPS64R2) | |
374 | ||
ec68c924 | 375 | /* The argument of the -march= flag. The architecture we are assembling. */ |
fef14a42 | 376 | static int file_mips_arch = CPU_UNKNOWN; |
316f5878 | 377 | static const char *mips_arch_string; |
ec68c924 EC |
378 | |
379 | /* The argument of the -mtune= flag. The architecture for which we | |
380 | are optimizing. */ | |
381 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 382 | static const char *mips_tune_string; |
ec68c924 | 383 | |
316f5878 | 384 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
385 | static int mips_32bitmode = 0; |
386 | ||
316f5878 RS |
387 | /* True if the given ABI requires 32-bit registers. */ |
388 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
389 | ||
390 | /* Likewise 64-bit registers. */ | |
707bfff6 TS |
391 | #define ABI_NEEDS_64BIT_REGS(ABI) \ |
392 | ((ABI) == N32_ABI \ | |
393 | || (ABI) == N64_ABI \ | |
316f5878 RS |
394 | || (ABI) == O64_ABI) |
395 | ||
ad3fea08 | 396 | /* Return true if ISA supports 64 bit wide gp registers. */ |
707bfff6 TS |
397 | #define ISA_HAS_64BIT_REGS(ISA) \ |
398 | ((ISA) == ISA_MIPS3 \ | |
399 | || (ISA) == ISA_MIPS4 \ | |
400 | || (ISA) == ISA_MIPS5 \ | |
401 | || (ISA) == ISA_MIPS64 \ | |
402 | || (ISA) == ISA_MIPS64R2) | |
9ce8a5dd | 403 | |
ad3fea08 TS |
404 | /* Return true if ISA supports 64 bit wide float registers. */ |
405 | #define ISA_HAS_64BIT_FPRS(ISA) \ | |
406 | ((ISA) == ISA_MIPS3 \ | |
407 | || (ISA) == ISA_MIPS4 \ | |
408 | || (ISA) == ISA_MIPS5 \ | |
409 | || (ISA) == ISA_MIPS32R2 \ | |
410 | || (ISA) == ISA_MIPS64 \ | |
411 | || (ISA) == ISA_MIPS64R2) | |
412 | ||
af7ee8bf CD |
413 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
414 | instructions. */ | |
707bfff6 | 415 | #define ISA_HAS_DROR(ISA) \ |
df58fc94 RS |
416 | ((ISA) == ISA_MIPS64R2 \ |
417 | || (mips_opts.micromips \ | |
418 | && ISA_HAS_64BIT_REGS (ISA)) \ | |
419 | ) | |
af7ee8bf CD |
420 | |
421 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
422 | instructions. */ | |
707bfff6 TS |
423 | #define ISA_HAS_ROR(ISA) \ |
424 | ((ISA) == ISA_MIPS32R2 \ | |
425 | || (ISA) == ISA_MIPS64R2 \ | |
df58fc94 RS |
426 | || mips_opts.ase_smartmips \ |
427 | || mips_opts.micromips \ | |
428 | ) | |
707bfff6 | 429 | |
7455baf8 TS |
430 | /* Return true if ISA supports single-precision floats in odd registers. */ |
431 | #define ISA_HAS_ODD_SINGLE_FPR(ISA) \ | |
432 | ((ISA) == ISA_MIPS32 \ | |
433 | || (ISA) == ISA_MIPS32R2 \ | |
434 | || (ISA) == ISA_MIPS64 \ | |
435 | || (ISA) == ISA_MIPS64R2) | |
af7ee8bf | 436 | |
ad3fea08 TS |
437 | /* Return true if ISA supports move to/from high part of a 64-bit |
438 | floating-point register. */ | |
439 | #define ISA_HAS_MXHC1(ISA) \ | |
440 | ((ISA) == ISA_MIPS32R2 \ | |
441 | || (ISA) == ISA_MIPS64R2) | |
442 | ||
e013f690 | 443 | #define HAVE_32BIT_GPRS \ |
ad3fea08 | 444 | (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 445 | |
e013f690 | 446 | #define HAVE_32BIT_FPRS \ |
ad3fea08 | 447 | (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa)) |
ca4e0257 | 448 | |
ad3fea08 TS |
449 | #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS) |
450 | #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS) | |
ca4e0257 | 451 | |
316f5878 | 452 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 453 | |
316f5878 | 454 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 455 | |
3b91255e RS |
456 | /* True if relocations are stored in-place. */ |
457 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
458 | ||
aed1a261 RS |
459 | /* The ABI-derived address size. */ |
460 | #define HAVE_64BIT_ADDRESSES \ | |
461 | (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) | |
462 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) | |
e013f690 | 463 | |
aed1a261 RS |
464 | /* The size of symbolic constants (i.e., expressions of the form |
465 | "SYMBOL" or "SYMBOL + OFFSET"). */ | |
466 | #define HAVE_32BIT_SYMBOLS \ | |
467 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) | |
468 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) | |
ca4e0257 | 469 | |
b7c7d6c1 TS |
470 | /* Addresses are loaded in different ways, depending on the address size |
471 | in use. The n32 ABI Documentation also mandates the use of additions | |
472 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 473 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 474 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
475 | |
476 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 477 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
478 | |
479 | #define ADDRESS_LOAD_INSN \ | |
480 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
481 | ||
482 | #define ADDRESS_STORE_INSN \ | |
483 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
484 | ||
a4672219 | 485 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
486 | #define CPU_HAS_MIPS16(cpu) \ |
487 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
488 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 489 | |
2309ddf2 | 490 | /* Return true if the given CPU supports the microMIPS ASE. */ |
df58fc94 RS |
491 | #define CPU_HAS_MICROMIPS(cpu) 0 |
492 | ||
60b63b72 RS |
493 | /* True if CPU has a dror instruction. */ |
494 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
495 | ||
496 | /* True if CPU has a ror instruction. */ | |
497 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
498 | ||
dd3cbb7e NC |
499 | /* True if CPU has seq/sne and seqi/snei instructions. */ |
500 | #define CPU_HAS_SEQ(CPU) ((CPU) == CPU_OCTEON) | |
501 | ||
b19e8a9b AN |
502 | /* True if CPU does not implement the all the coprocessor insns. For these |
503 | CPUs only those COP insns are accepted that are explicitly marked to be | |
504 | available on the CPU. ISA membership for COP insns is ignored. */ | |
505 | #define NO_ISA_COP(CPU) ((CPU) == CPU_OCTEON) | |
506 | ||
c8978940 CD |
507 | /* True if mflo and mfhi can be immediately followed by instructions |
508 | which write to the HI and LO registers. | |
509 | ||
510 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
511 | (at least) two instructions between the reads of HI/LO and | |
512 | instructions which write them, and later ISAs do not. Contradicting | |
513 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
514 | the UM for the NEC Vr5000) document needing the instructions between | |
515 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
516 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
517 | earlier-ISA CPUs for which CPU documentation declares that the | |
518 | instructions are really interlocked. */ | |
519 | #define hilo_interlocks \ | |
520 | (mips_opts.isa == ISA_MIPS32 \ | |
521 | || mips_opts.isa == ISA_MIPS32R2 \ | |
522 | || mips_opts.isa == ISA_MIPS64 \ | |
523 | || mips_opts.isa == ISA_MIPS64R2 \ | |
524 | || mips_opts.arch == CPU_R4010 \ | |
525 | || mips_opts.arch == CPU_R10000 \ | |
526 | || mips_opts.arch == CPU_R12000 \ | |
3aa3176b TS |
527 | || mips_opts.arch == CPU_R14000 \ |
528 | || mips_opts.arch == CPU_R16000 \ | |
c8978940 | 529 | || mips_opts.arch == CPU_RM7000 \ |
c8978940 | 530 | || mips_opts.arch == CPU_VR5500 \ |
df58fc94 | 531 | || mips_opts.micromips \ |
c8978940 | 532 | ) |
252b5132 RH |
533 | |
534 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
535 | from the GPRs after they are loaded from memory, and thus does not |
536 | require nops to be inserted. This applies to instructions marked | |
537 | INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA | |
df58fc94 RS |
538 | level I and microMIPS mode instructions are always interlocked. */ |
539 | #define gpr_interlocks \ | |
540 | (mips_opts.isa != ISA_MIPS1 \ | |
541 | || mips_opts.arch == CPU_R3900 \ | |
542 | || mips_opts.micromips \ | |
543 | ) | |
252b5132 | 544 | |
81912461 ILT |
545 | /* Whether the processor uses hardware interlocks to avoid delays |
546 | required by coprocessor instructions, and thus does not require | |
547 | nops to be inserted. This applies to instructions marked | |
548 | INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays | |
549 | between instructions marked INSN_WRITE_COND_CODE and ones marked | |
550 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA | |
df58fc94 RS |
551 | levels I, II, and III and microMIPS mode instructions are always |
552 | interlocked. */ | |
bdaaa2e1 | 553 | /* Itbl support may require additional care here. */ |
81912461 ILT |
554 | #define cop_interlocks \ |
555 | ((mips_opts.isa != ISA_MIPS1 \ | |
556 | && mips_opts.isa != ISA_MIPS2 \ | |
557 | && mips_opts.isa != ISA_MIPS3) \ | |
558 | || mips_opts.arch == CPU_R4300 \ | |
df58fc94 | 559 | || mips_opts.micromips \ |
81912461 ILT |
560 | ) |
561 | ||
562 | /* Whether the processor uses hardware interlocks to protect reads | |
563 | from coprocessor registers after they are loaded from memory, and | |
564 | thus does not require nops to be inserted. This applies to | |
565 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
df58fc94 RS |
566 | requires at MIPS ISA level I and microMIPS mode instructions are |
567 | always interlocked. */ | |
568 | #define cop_mem_interlocks \ | |
569 | (mips_opts.isa != ISA_MIPS1 \ | |
570 | || mips_opts.micromips \ | |
571 | ) | |
252b5132 | 572 | |
6b76fefe CM |
573 | /* Is this a mfhi or mflo instruction? */ |
574 | #define MF_HILO_INSN(PINFO) \ | |
b19e8a9b AN |
575 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) |
576 | ||
577 | /* Returns true for a (non floating-point) coprocessor instruction. Reading | |
578 | or writing the condition code is only possible on the coprocessors and | |
579 | these insns are not marked with INSN_COP. Thus for these insns use the | |
a242dc0d | 580 | condition-code flags. */ |
b19e8a9b AN |
581 | #define COP_INSN(PINFO) \ |
582 | (PINFO != INSN_MACRO \ | |
a242dc0d AN |
583 | && ((PINFO) & (FP_S | FP_D)) == 0 \ |
584 | && ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE))) | |
6b76fefe | 585 | |
df58fc94 RS |
586 | /* Whether code compression (either of the MIPS16 or the microMIPS ASEs) |
587 | has been selected. This implies, in particular, that addresses of text | |
588 | labels have their LSB set. */ | |
589 | #define HAVE_CODE_COMPRESSION \ | |
590 | ((mips_opts.mips16 | mips_opts.micromips) != 0) | |
591 | ||
252b5132 RH |
592 | /* MIPS PIC level. */ |
593 | ||
a161fe53 | 594 | enum mips_pic_level mips_pic; |
252b5132 | 595 | |
c9914766 | 596 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 597 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 598 | static int mips_big_got = 0; |
252b5132 RH |
599 | |
600 | /* 1 if trap instructions should used for overflow rather than break | |
601 | instructions. */ | |
c9914766 | 602 | static int mips_trap = 0; |
252b5132 | 603 | |
119d663a | 604 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 605 | by assembling two single width halves into two single width floating |
119d663a NC |
606 | point registers which just happen to alias the double width destination |
607 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 608 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
609 | automatically at assemble time. */ |
610 | static int mips_disable_float_construction; | |
611 | ||
252b5132 RH |
612 | /* Non-zero if any .set noreorder directives were used. */ |
613 | ||
614 | static int mips_any_noreorder; | |
615 | ||
6b76fefe CM |
616 | /* Non-zero if nops should be inserted when the register referenced in |
617 | an mfhi/mflo instruction is read in the next two instructions. */ | |
618 | static int mips_7000_hilo_fix; | |
619 | ||
02ffd3e4 | 620 | /* The size of objects in the small data section. */ |
156c2f8b | 621 | static unsigned int g_switch_value = 8; |
252b5132 RH |
622 | /* Whether the -G option was used. */ |
623 | static int g_switch_seen = 0; | |
624 | ||
625 | #define N_RMASK 0xc4 | |
626 | #define N_VFP 0xd4 | |
627 | ||
628 | /* If we can determine in advance that GP optimization won't be | |
629 | possible, we can skip the relaxation stuff that tries to produce | |
630 | GP-relative references. This makes delay slot optimization work | |
631 | better. | |
632 | ||
633 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
634 | gcc output. It needs to guess right for gcc, otherwise gcc |
635 | will put what it thinks is a GP-relative instruction in a branch | |
636 | delay slot. | |
252b5132 RH |
637 | |
638 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
639 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 640 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
641 | |
642 | /* handle of the OPCODE hash table */ | |
643 | static struct hash_control *op_hash = NULL; | |
644 | ||
645 | /* The opcode hash table we use for the mips16. */ | |
646 | static struct hash_control *mips16_op_hash = NULL; | |
647 | ||
df58fc94 RS |
648 | /* The opcode hash table we use for the microMIPS ASE. */ |
649 | static struct hash_control *micromips_op_hash = NULL; | |
650 | ||
252b5132 RH |
651 | /* This array holds the chars that always start a comment. If the |
652 | pre-processor is disabled, these aren't very useful */ | |
653 | const char comment_chars[] = "#"; | |
654 | ||
655 | /* This array holds the chars that only start a comment at the beginning of | |
656 | a line. If the line seems to have the form '# 123 filename' | |
657 | .line and .file directives will appear in the pre-processed output */ | |
658 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
659 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 660 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
661 | /* Also note that C style comments are always supported. */ |
662 | const char line_comment_chars[] = "#"; | |
663 | ||
bdaaa2e1 | 664 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 665 | const char line_separator_chars[] = ";"; |
252b5132 RH |
666 | |
667 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
668 | const char EXP_CHARS[] = "eE"; | |
669 | ||
670 | /* Chars that mean this number is a floating point constant */ | |
671 | /* As in 0f12.456 */ | |
672 | /* or 0d1.2345e12 */ | |
673 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
674 | ||
675 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
676 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
677 | but nothing is ideal around here. | |
678 | */ | |
679 | ||
680 | static char *insn_error; | |
681 | ||
682 | static int auto_align = 1; | |
683 | ||
684 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
685 | offset in the stack frame from which to restore the $gp register. | |
686 | This is set by the .cprestore pseudo-op, and saved in this | |
687 | variable. */ | |
688 | static offsetT mips_cprestore_offset = -1; | |
689 | ||
67c1ffbe | 690 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 691 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 692 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
693 | static offsetT mips_cpreturn_offset = -1; |
694 | static int mips_cpreturn_register = -1; | |
695 | static int mips_gp_register = GP; | |
def2e0dd | 696 | static int mips_gprel_offset = 0; |
6478892d | 697 | |
7a621144 DJ |
698 | /* Whether mips_cprestore_offset has been set in the current function |
699 | (or whether it has already been warned about, if not). */ | |
700 | static int mips_cprestore_valid = 0; | |
701 | ||
252b5132 RH |
702 | /* This is the register which holds the stack frame, as set by the |
703 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
704 | static int mips_frame_reg = SP; | |
705 | ||
7a621144 DJ |
706 | /* Whether mips_frame_reg has been set in the current function |
707 | (or whether it has already been warned about, if not). */ | |
708 | static int mips_frame_reg_valid = 0; | |
709 | ||
252b5132 RH |
710 | /* To output NOP instructions correctly, we need to keep information |
711 | about the previous two instructions. */ | |
712 | ||
713 | /* Whether we are optimizing. The default value of 2 means to remove | |
714 | unneeded NOPs and swap branch instructions when possible. A value | |
715 | of 1 means to not swap branches. A value of 0 means to always | |
716 | insert NOPs. */ | |
717 | static int mips_optimize = 2; | |
718 | ||
719 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
720 | equivalent to seeing no -g option at all. */ | |
721 | static int mips_debug = 0; | |
722 | ||
7d8e00cf RS |
723 | /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ |
724 | #define MAX_VR4130_NOPS 4 | |
725 | ||
726 | /* The maximum number of NOPs needed to fill delay slots. */ | |
727 | #define MAX_DELAY_NOPS 2 | |
728 | ||
729 | /* The maximum number of NOPs needed for any purpose. */ | |
730 | #define MAX_NOPS 4 | |
71400594 RS |
731 | |
732 | /* A list of previous instructions, with index 0 being the most recent. | |
733 | We need to look back MAX_NOPS instructions when filling delay slots | |
734 | or working around processor errata. We need to look back one | |
735 | instruction further if we're thinking about using history[0] to | |
736 | fill a branch delay slot. */ | |
737 | static struct mips_cl_insn history[1 + MAX_NOPS]; | |
252b5132 | 738 | |
1e915849 | 739 | /* Nop instructions used by emit_nop. */ |
df58fc94 RS |
740 | static struct mips_cl_insn nop_insn; |
741 | static struct mips_cl_insn mips16_nop_insn; | |
742 | static struct mips_cl_insn micromips_nop16_insn; | |
743 | static struct mips_cl_insn micromips_nop32_insn; | |
1e915849 RS |
744 | |
745 | /* The appropriate nop for the current mode. */ | |
df58fc94 RS |
746 | #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn \ |
747 | : (mips_opts.micromips ? µmips_nop16_insn : &nop_insn)) | |
748 | ||
749 | /* The size of NOP_INSN in bytes. */ | |
750 | #define NOP_INSN_SIZE (HAVE_CODE_COMPRESSION ? 2 : 4) | |
252b5132 | 751 | |
252b5132 RH |
752 | /* If this is set, it points to a frag holding nop instructions which |
753 | were inserted before the start of a noreorder section. If those | |
754 | nops turn out to be unnecessary, the size of the frag can be | |
755 | decreased. */ | |
756 | static fragS *prev_nop_frag; | |
757 | ||
758 | /* The number of nop instructions we created in prev_nop_frag. */ | |
759 | static int prev_nop_frag_holds; | |
760 | ||
761 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 762 | prev_nop_frag. */ |
252b5132 RH |
763 | static int prev_nop_frag_required; |
764 | ||
765 | /* The number of instructions we've seen since prev_nop_frag. */ | |
766 | static int prev_nop_frag_since; | |
767 | ||
768 | /* For ECOFF and ELF, relocations against symbols are done in two | |
769 | parts, with a HI relocation and a LO relocation. Each relocation | |
770 | has only 16 bits of space to store an addend. This means that in | |
771 | order for the linker to handle carries correctly, it must be able | |
772 | to locate both the HI and the LO relocation. This means that the | |
773 | relocations must appear in order in the relocation table. | |
774 | ||
775 | In order to implement this, we keep track of each unmatched HI | |
776 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 777 | corresponding LO relocation. */ |
252b5132 | 778 | |
e972090a NC |
779 | struct mips_hi_fixup |
780 | { | |
252b5132 RH |
781 | /* Next HI fixup. */ |
782 | struct mips_hi_fixup *next; | |
783 | /* This fixup. */ | |
784 | fixS *fixp; | |
785 | /* The section this fixup is in. */ | |
786 | segT seg; | |
787 | }; | |
788 | ||
789 | /* The list of unmatched HI relocs. */ | |
790 | ||
791 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
792 | ||
64bdfcaf RS |
793 | /* The frag containing the last explicit relocation operator. |
794 | Null if explicit relocations have not been used. */ | |
795 | ||
796 | static fragS *prev_reloc_op_frag; | |
797 | ||
252b5132 RH |
798 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
799 | ||
800 | #define X ILLEGAL_REG | |
e972090a NC |
801 | static const int mips32_to_16_reg_map[] = |
802 | { | |
252b5132 RH |
803 | X, X, 2, 3, 4, 5, 6, 7, |
804 | X, X, X, X, X, X, X, X, | |
805 | 0, 1, X, X, X, X, X, X, | |
806 | X, X, X, X, X, X, X, X | |
807 | }; | |
808 | #undef X | |
809 | ||
810 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
811 | ||
e972090a NC |
812 | static const unsigned int mips16_to_32_reg_map[] = |
813 | { | |
252b5132 RH |
814 | 16, 17, 2, 3, 4, 5, 6, 7 |
815 | }; | |
60b63b72 | 816 | |
df58fc94 RS |
817 | /* Map normal MIPS register numbers to microMIPS register numbers. */ |
818 | ||
819 | #define mips32_to_micromips_reg_b_map mips32_to_16_reg_map | |
820 | #define mips32_to_micromips_reg_c_map mips32_to_16_reg_map | |
821 | #define mips32_to_micromips_reg_d_map mips32_to_16_reg_map | |
822 | #define mips32_to_micromips_reg_e_map mips32_to_16_reg_map | |
823 | #define mips32_to_micromips_reg_f_map mips32_to_16_reg_map | |
824 | #define mips32_to_micromips_reg_g_map mips32_to_16_reg_map | |
825 | #define mips32_to_micromips_reg_l_map mips32_to_16_reg_map | |
826 | ||
827 | #define X ILLEGAL_REG | |
828 | /* reg type h: 4, 5, 6. */ | |
829 | static const int mips32_to_micromips_reg_h_map[] = | |
830 | { | |
831 | X, X, X, X, 4, 5, 6, X, | |
832 | X, X, X, X, X, X, X, X, | |
833 | X, X, X, X, X, X, X, X, | |
834 | X, X, X, X, X, X, X, X | |
835 | }; | |
836 | ||
837 | /* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */ | |
838 | static const int mips32_to_micromips_reg_m_map[] = | |
839 | { | |
840 | 0, X, 2, 3, X, X, X, X, | |
841 | X, X, X, X, X, X, X, X, | |
842 | 4, 1, 5, 6, 7, X, X, X, | |
843 | X, X, X, X, X, X, X, X | |
844 | }; | |
845 | ||
846 | /* reg type q: 0, 2-7. 17. */ | |
847 | static const int mips32_to_micromips_reg_q_map[] = | |
848 | { | |
849 | 0, X, 2, 3, 4, 5, 6, 7, | |
850 | X, X, X, X, X, X, X, X, | |
851 | X, 1, X, X, X, X, X, X, | |
852 | X, X, X, X, X, X, X, X | |
853 | }; | |
854 | ||
855 | #define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map | |
856 | #undef X | |
857 | ||
858 | /* Map microMIPS register numbers to normal MIPS register numbers. */ | |
859 | ||
860 | #define micromips_to_32_reg_b_map mips16_to_32_reg_map | |
861 | #define micromips_to_32_reg_c_map mips16_to_32_reg_map | |
862 | #define micromips_to_32_reg_d_map mips16_to_32_reg_map | |
863 | #define micromips_to_32_reg_e_map mips16_to_32_reg_map | |
864 | #define micromips_to_32_reg_f_map mips16_to_32_reg_map | |
865 | #define micromips_to_32_reg_g_map mips16_to_32_reg_map | |
866 | ||
867 | /* The microMIPS registers with type h. */ | |
868 | static const unsigned int micromips_to_32_reg_h_map[] = | |
869 | { | |
870 | 5, 5, 6, 4, 4, 4, 4, 4 | |
871 | }; | |
872 | ||
873 | /* The microMIPS registers with type i. */ | |
874 | static const unsigned int micromips_to_32_reg_i_map[] = | |
875 | { | |
876 | 6, 7, 7, 21, 22, 5, 6, 7 | |
877 | }; | |
878 | ||
879 | #define micromips_to_32_reg_l_map mips16_to_32_reg_map | |
880 | ||
881 | /* The microMIPS registers with type m. */ | |
882 | static const unsigned int micromips_to_32_reg_m_map[] = | |
883 | { | |
884 | 0, 17, 2, 3, 16, 18, 19, 20 | |
885 | }; | |
886 | ||
887 | #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map | |
888 | ||
889 | /* The microMIPS registers with type q. */ | |
890 | static const unsigned int micromips_to_32_reg_q_map[] = | |
891 | { | |
892 | 0, 17, 2, 3, 4, 5, 6, 7 | |
893 | }; | |
894 | ||
895 | /* microMIPS imm type B. */ | |
896 | static const int micromips_imm_b_map[] = | |
897 | { | |
898 | 1, 4, 8, 12, 16, 20, 24, -1 | |
899 | }; | |
900 | ||
901 | /* microMIPS imm type C. */ | |
902 | static const int micromips_imm_c_map[] = | |
903 | { | |
904 | 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535 | |
905 | }; | |
906 | ||
71400594 RS |
907 | /* Classifies the kind of instructions we're interested in when |
908 | implementing -mfix-vr4120. */ | |
c67a084a NC |
909 | enum fix_vr4120_class |
910 | { | |
71400594 RS |
911 | FIX_VR4120_MACC, |
912 | FIX_VR4120_DMACC, | |
913 | FIX_VR4120_MULT, | |
914 | FIX_VR4120_DMULT, | |
915 | FIX_VR4120_DIV, | |
916 | FIX_VR4120_MTHILO, | |
917 | NUM_FIX_VR4120_CLASSES | |
918 | }; | |
919 | ||
c67a084a NC |
920 | /* ...likewise -mfix-loongson2f-jump. */ |
921 | static bfd_boolean mips_fix_loongson2f_jump; | |
922 | ||
923 | /* ...likewise -mfix-loongson2f-nop. */ | |
924 | static bfd_boolean mips_fix_loongson2f_nop; | |
925 | ||
926 | /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */ | |
927 | static bfd_boolean mips_fix_loongson2f; | |
928 | ||
71400594 RS |
929 | /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if |
930 | there must be at least one other instruction between an instruction | |
931 | of type X and an instruction of type Y. */ | |
932 | static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; | |
933 | ||
934 | /* True if -mfix-vr4120 is in force. */ | |
d766e8ec | 935 | static int mips_fix_vr4120; |
4a6a3df4 | 936 | |
7d8e00cf RS |
937 | /* ...likewise -mfix-vr4130. */ |
938 | static int mips_fix_vr4130; | |
939 | ||
6a32d874 CM |
940 | /* ...likewise -mfix-24k. */ |
941 | static int mips_fix_24k; | |
942 | ||
d954098f DD |
943 | /* ...likewise -mfix-cn63xxp1 */ |
944 | static bfd_boolean mips_fix_cn63xxp1; | |
945 | ||
4a6a3df4 AO |
946 | /* We don't relax branches by default, since this causes us to expand |
947 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
948 | fail to compute the offset before expanding the macro to the most | |
949 | efficient expansion. */ | |
950 | ||
951 | static int mips_relax_branch; | |
252b5132 | 952 | \f |
4d7206a2 RS |
953 | /* The expansion of many macros depends on the type of symbol that |
954 | they refer to. For example, when generating position-dependent code, | |
955 | a macro that refers to a symbol may have two different expansions, | |
956 | one which uses GP-relative addresses and one which uses absolute | |
957 | addresses. When generating SVR4-style PIC, a macro may have | |
958 | different expansions for local and global symbols. | |
959 | ||
960 | We handle these situations by generating both sequences and putting | |
961 | them in variant frags. In position-dependent code, the first sequence | |
962 | will be the GP-relative one and the second sequence will be the | |
963 | absolute one. In SVR4 PIC, the first sequence will be for global | |
964 | symbols and the second will be for local symbols. | |
965 | ||
584892a6 RS |
966 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
967 | SECOND are the lengths of the two sequences in bytes. These fields | |
968 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
969 | the subtype has the following flags: | |
4d7206a2 | 970 | |
584892a6 RS |
971 | RELAX_USE_SECOND |
972 | Set if it has been decided that we should use the second | |
973 | sequence instead of the first. | |
974 | ||
975 | RELAX_SECOND_LONGER | |
976 | Set in the first variant frag if the macro's second implementation | |
977 | is longer than its first. This refers to the macro as a whole, | |
978 | not an individual relaxation. | |
979 | ||
980 | RELAX_NOMACRO | |
981 | Set in the first variant frag if the macro appeared in a .set nomacro | |
982 | block and if one alternative requires a warning but the other does not. | |
983 | ||
984 | RELAX_DELAY_SLOT | |
985 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
986 | delay slot. | |
4d7206a2 | 987 | |
df58fc94 RS |
988 | RELAX_DELAY_SLOT_16BIT |
989 | Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a | |
990 | 16-bit instruction. | |
991 | ||
992 | RELAX_DELAY_SLOT_SIZE_FIRST | |
993 | Like RELAX_DELAY_SLOT, but indicates that the first implementation of | |
994 | the macro is of the wrong size for the branch delay slot. | |
995 | ||
996 | RELAX_DELAY_SLOT_SIZE_SECOND | |
997 | Like RELAX_DELAY_SLOT, but indicates that the second implementation of | |
998 | the macro is of the wrong size for the branch delay slot. | |
999 | ||
4d7206a2 RS |
1000 | The frag's "opcode" points to the first fixup for relaxable code. |
1001 | ||
1002 | Relaxable macros are generated using a sequence such as: | |
1003 | ||
1004 | relax_start (SYMBOL); | |
1005 | ... generate first expansion ... | |
1006 | relax_switch (); | |
1007 | ... generate second expansion ... | |
1008 | relax_end (); | |
1009 | ||
1010 | The code and fixups for the unwanted alternative are discarded | |
1011 | by md_convert_frag. */ | |
584892a6 | 1012 | #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) |
4d7206a2 | 1013 | |
584892a6 RS |
1014 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
1015 | #define RELAX_SECOND(X) ((X) & 0xff) | |
1016 | #define RELAX_USE_SECOND 0x10000 | |
1017 | #define RELAX_SECOND_LONGER 0x20000 | |
1018 | #define RELAX_NOMACRO 0x40000 | |
1019 | #define RELAX_DELAY_SLOT 0x80000 | |
df58fc94 RS |
1020 | #define RELAX_DELAY_SLOT_16BIT 0x100000 |
1021 | #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000 | |
1022 | #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000 | |
252b5132 | 1023 | |
4a6a3df4 AO |
1024 | /* Branch without likely bit. If label is out of range, we turn: |
1025 | ||
1026 | beq reg1, reg2, label | |
1027 | delay slot | |
1028 | ||
1029 | into | |
1030 | ||
1031 | bne reg1, reg2, 0f | |
1032 | nop | |
1033 | j label | |
1034 | 0: delay slot | |
1035 | ||
1036 | with the following opcode replacements: | |
1037 | ||
1038 | beq <-> bne | |
1039 | blez <-> bgtz | |
1040 | bltz <-> bgez | |
1041 | bc1f <-> bc1t | |
1042 | ||
1043 | bltzal <-> bgezal (with jal label instead of j label) | |
1044 | ||
1045 | Even though keeping the delay slot instruction in the delay slot of | |
1046 | the branch would be more efficient, it would be very tricky to do | |
1047 | correctly, because we'd have to introduce a variable frag *after* | |
1048 | the delay slot instruction, and expand that instead. Let's do it | |
1049 | the easy way for now, even if the branch-not-taken case now costs | |
1050 | one additional instruction. Out-of-range branches are not supposed | |
1051 | to be common, anyway. | |
1052 | ||
1053 | Branch likely. If label is out of range, we turn: | |
1054 | ||
1055 | beql reg1, reg2, label | |
1056 | delay slot (annulled if branch not taken) | |
1057 | ||
1058 | into | |
1059 | ||
1060 | beql reg1, reg2, 1f | |
1061 | nop | |
1062 | beql $0, $0, 2f | |
1063 | nop | |
1064 | 1: j[al] label | |
1065 | delay slot (executed only if branch taken) | |
1066 | 2: | |
1067 | ||
1068 | It would be possible to generate a shorter sequence by losing the | |
1069 | likely bit, generating something like: | |
b34976b6 | 1070 | |
4a6a3df4 AO |
1071 | bne reg1, reg2, 0f |
1072 | nop | |
1073 | j[al] label | |
1074 | delay slot (executed only if branch taken) | |
1075 | 0: | |
1076 | ||
1077 | beql -> bne | |
1078 | bnel -> beq | |
1079 | blezl -> bgtz | |
1080 | bgtzl -> blez | |
1081 | bltzl -> bgez | |
1082 | bgezl -> bltz | |
1083 | bc1fl -> bc1t | |
1084 | bc1tl -> bc1f | |
1085 | ||
1086 | bltzall -> bgezal (with jal label instead of j label) | |
1087 | bgezall -> bltzal (ditto) | |
1088 | ||
1089 | ||
1090 | but it's not clear that it would actually improve performance. */ | |
66b3e8da MR |
1091 | #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \ |
1092 | ((relax_substateT) \ | |
1093 | (0xc0000000 \ | |
1094 | | ((at) & 0x1f) \ | |
1095 | | ((toofar) ? 0x20 : 0) \ | |
1096 | | ((link) ? 0x40 : 0) \ | |
1097 | | ((likely) ? 0x80 : 0) \ | |
1098 | | ((uncond) ? 0x100 : 0))) | |
4a6a3df4 | 1099 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
66b3e8da MR |
1100 | #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0) |
1101 | #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0) | |
1102 | #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0) | |
1103 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0) | |
1104 | #define RELAX_BRANCH_AT(i) ((i) & 0x1f) | |
4a6a3df4 | 1105 | |
252b5132 RH |
1106 | /* For mips16 code, we use an entirely different form of relaxation. |
1107 | mips16 supports two versions of most instructions which take | |
1108 | immediate values: a small one which takes some small value, and a | |
1109 | larger one which takes a 16 bit value. Since branches also follow | |
1110 | this pattern, relaxing these values is required. | |
1111 | ||
1112 | We can assemble both mips16 and normal MIPS code in a single | |
1113 | object. Therefore, we need to support this type of relaxation at | |
1114 | the same time that we support the relaxation described above. We | |
1115 | use the high bit of the subtype field to distinguish these cases. | |
1116 | ||
1117 | The information we store for this type of relaxation is the | |
1118 | argument code found in the opcode file for this relocation, whether | |
1119 | the user explicitly requested a small or extended form, and whether | |
1120 | the relocation is in a jump or jal delay slot. That tells us the | |
1121 | size of the value, and how it should be stored. We also store | |
1122 | whether the fragment is considered to be extended or not. We also | |
1123 | store whether this is known to be a branch to a different section, | |
1124 | whether we have tried to relax this frag yet, and whether we have | |
1125 | ever extended a PC relative fragment because of a shift count. */ | |
1126 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
1127 | (0x80000000 \ | |
1128 | | ((type) & 0xff) \ | |
1129 | | ((small) ? 0x100 : 0) \ | |
1130 | | ((ext) ? 0x200 : 0) \ | |
1131 | | ((dslot) ? 0x400 : 0) \ | |
1132 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 1133 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
1134 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
1135 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
1136 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
1137 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
1138 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
1139 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
1140 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
1141 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
1142 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
1143 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
1144 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 | 1145 | |
df58fc94 RS |
1146 | /* For microMIPS code, we use relaxation similar to one we use for |
1147 | MIPS16 code. Some instructions that take immediate values support | |
1148 | two encodings: a small one which takes some small value, and a | |
1149 | larger one which takes a 16 bit value. As some branches also follow | |
1150 | this pattern, relaxing these values is required. | |
1151 | ||
1152 | We can assemble both microMIPS and normal MIPS code in a single | |
1153 | object. Therefore, we need to support this type of relaxation at | |
1154 | the same time that we support the relaxation described above. We | |
1155 | use one of the high bits of the subtype field to distinguish these | |
1156 | cases. | |
1157 | ||
1158 | The information we store for this type of relaxation is the argument | |
1159 | code found in the opcode file for this relocation, the register | |
40209cad MR |
1160 | selected as the assembler temporary, whether the branch is |
1161 | unconditional, whether it is compact, whether it stores the link | |
1162 | address implicitly in $ra, whether relaxation of out-of-range 32-bit | |
1163 | branches to a sequence of instructions is enabled, and whether the | |
1164 | displacement of a branch is too large to fit as an immediate argument | |
1165 | of a 16-bit and a 32-bit branch, respectively. */ | |
1166 | #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \ | |
1167 | relax32, toofar16, toofar32) \ | |
1168 | (0x40000000 \ | |
1169 | | ((type) & 0xff) \ | |
1170 | | (((at) & 0x1f) << 8) \ | |
1171 | | ((uncond) ? 0x2000 : 0) \ | |
1172 | | ((compact) ? 0x4000 : 0) \ | |
1173 | | ((link) ? 0x8000 : 0) \ | |
1174 | | ((relax32) ? 0x10000 : 0) \ | |
1175 | | ((toofar16) ? 0x20000 : 0) \ | |
1176 | | ((toofar32) ? 0x40000 : 0)) | |
df58fc94 RS |
1177 | #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000) |
1178 | #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff) | |
1179 | #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f) | |
40209cad MR |
1180 | #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0) |
1181 | #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0) | |
1182 | #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0) | |
1183 | #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0) | |
1184 | ||
1185 | #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0) | |
1186 | #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000) | |
1187 | #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000) | |
1188 | #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0) | |
1189 | #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000) | |
1190 | #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000) | |
df58fc94 | 1191 | |
885add95 CD |
1192 | /* Is the given value a sign-extended 32-bit value? */ |
1193 | #define IS_SEXT_32BIT_NUM(x) \ | |
1194 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
1195 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
1196 | ||
1197 | /* Is the given value a sign-extended 16-bit value? */ | |
1198 | #define IS_SEXT_16BIT_NUM(x) \ | |
1199 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
1200 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
1201 | ||
df58fc94 RS |
1202 | /* Is the given value a sign-extended 12-bit value? */ |
1203 | #define IS_SEXT_12BIT_NUM(x) \ | |
1204 | (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x)) | |
1205 | ||
2051e8c4 MR |
1206 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ |
1207 | #define IS_ZEXT_32BIT_NUM(x) \ | |
1208 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
1209 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
1210 | ||
bf12938e RS |
1211 | /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in |
1212 | VALUE << SHIFT. VALUE is evaluated exactly once. */ | |
1213 | #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \ | |
1214 | (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \ | |
1215 | | (((VALUE) & (MASK)) << (SHIFT))) | |
1216 | ||
1217 | /* Extract bits MASK << SHIFT from STRUCT and shift them right | |
1218 | SHIFT places. */ | |
1219 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
1220 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
1221 | ||
1222 | /* Change INSN's opcode so that the operand given by FIELD has value VALUE. | |
1223 | INSN is a mips_cl_insn structure and VALUE is evaluated exactly once. | |
1224 | ||
1225 | include/opcode/mips.h specifies operand fields using the macros | |
1226 | OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start | |
1227 | with "MIPS16OP" instead of "OP". */ | |
df58fc94 RS |
1228 | #define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \ |
1229 | do \ | |
1230 | if (!(MICROMIPS)) \ | |
1231 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1232 | OP_MASK_##FIELD, OP_SH_##FIELD); \ | |
1233 | else \ | |
1234 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1235 | MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \ | |
1236 | while (0) | |
bf12938e RS |
1237 | #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \ |
1238 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1239 | MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD) | |
1240 | ||
1241 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ | |
df58fc94 RS |
1242 | #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \ |
1243 | (!(MICROMIPS) \ | |
1244 | ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \ | |
1245 | : EXTRACT_BITS ((INSN).insn_opcode, \ | |
1246 | MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD)) | |
bf12938e RS |
1247 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ |
1248 | EXTRACT_BITS ((INSN).insn_opcode, \ | |
1249 | MIPS16OP_MASK_##FIELD, \ | |
1250 | MIPS16OP_SH_##FIELD) | |
4d7206a2 | 1251 | \f |
df58fc94 RS |
1252 | /* Whether or not we are emitting a branch-likely macro. */ |
1253 | static bfd_boolean emit_branch_likely_macro = FALSE; | |
1254 | ||
4d7206a2 RS |
1255 | /* Global variables used when generating relaxable macros. See the |
1256 | comment above RELAX_ENCODE for more details about how relaxation | |
1257 | is used. */ | |
1258 | static struct { | |
1259 | /* 0 if we're not emitting a relaxable macro. | |
1260 | 1 if we're emitting the first of the two relaxation alternatives. | |
1261 | 2 if we're emitting the second alternative. */ | |
1262 | int sequence; | |
1263 | ||
1264 | /* The first relaxable fixup in the current frag. (In other words, | |
1265 | the first fixup that refers to relaxable code.) */ | |
1266 | fixS *first_fixup; | |
1267 | ||
1268 | /* sizes[0] says how many bytes of the first alternative are stored in | |
1269 | the current frag. Likewise sizes[1] for the second alternative. */ | |
1270 | unsigned int sizes[2]; | |
1271 | ||
1272 | /* The symbol on which the choice of sequence depends. */ | |
1273 | symbolS *symbol; | |
1274 | } mips_relax; | |
252b5132 | 1275 | \f |
584892a6 RS |
1276 | /* Global variables used to decide whether a macro needs a warning. */ |
1277 | static struct { | |
1278 | /* True if the macro is in a branch delay slot. */ | |
1279 | bfd_boolean delay_slot_p; | |
1280 | ||
df58fc94 RS |
1281 | /* Set to the length in bytes required if the macro is in a delay slot |
1282 | that requires a specific length of instruction, otherwise zero. */ | |
1283 | unsigned int delay_slot_length; | |
1284 | ||
584892a6 RS |
1285 | /* For relaxable macros, sizes[0] is the length of the first alternative |
1286 | in bytes and sizes[1] is the length of the second alternative. | |
1287 | For non-relaxable macros, both elements give the length of the | |
1288 | macro in bytes. */ | |
1289 | unsigned int sizes[2]; | |
1290 | ||
df58fc94 RS |
1291 | /* For relaxable macros, first_insn_sizes[0] is the length of the first |
1292 | instruction of the first alternative in bytes and first_insn_sizes[1] | |
1293 | is the length of the first instruction of the second alternative. | |
1294 | For non-relaxable macros, both elements give the length of the first | |
1295 | instruction in bytes. | |
1296 | ||
1297 | Set to zero if we haven't yet seen the first instruction. */ | |
1298 | unsigned int first_insn_sizes[2]; | |
1299 | ||
1300 | /* For relaxable macros, insns[0] is the number of instructions for the | |
1301 | first alternative and insns[1] is the number of instructions for the | |
1302 | second alternative. | |
1303 | ||
1304 | For non-relaxable macros, both elements give the number of | |
1305 | instructions for the macro. */ | |
1306 | unsigned int insns[2]; | |
1307 | ||
584892a6 RS |
1308 | /* The first variant frag for this macro. */ |
1309 | fragS *first_frag; | |
1310 | } mips_macro_warning; | |
1311 | \f | |
252b5132 RH |
1312 | /* Prototypes for static functions. */ |
1313 | ||
17a2f251 | 1314 | #define internalError() \ |
252b5132 | 1315 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) |
252b5132 RH |
1316 | |
1317 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
1318 | ||
b34976b6 | 1319 | static void append_insn |
df58fc94 RS |
1320 | (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *, |
1321 | bfd_boolean expansionp); | |
7d10b47d | 1322 | static void mips_no_prev_insn (void); |
c67a084a | 1323 | static void macro_build (expressionS *, const char *, const char *, ...); |
b34976b6 | 1324 | static void mips16_macro_build |
03ea81db | 1325 | (expressionS *, const char *, const char *, va_list *); |
67c0d1eb | 1326 | static void load_register (int, expressionS *, int); |
584892a6 RS |
1327 | static void macro_start (void); |
1328 | static void macro_end (void); | |
17a2f251 TS |
1329 | static void macro (struct mips_cl_insn * ip); |
1330 | static void mips16_macro (struct mips_cl_insn * ip); | |
17a2f251 TS |
1331 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
1332 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 1333 | static void mips16_immed |
17a2f251 TS |
1334 | (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean, |
1335 | unsigned long *, bfd_boolean *, unsigned short *); | |
5e0116d5 | 1336 | static size_t my_getSmallExpression |
17a2f251 TS |
1337 | (expressionS *, bfd_reloc_code_real_type *, char *); |
1338 | static void my_getExpression (expressionS *, char *); | |
1339 | static void s_align (int); | |
1340 | static void s_change_sec (int); | |
1341 | static void s_change_section (int); | |
1342 | static void s_cons (int); | |
1343 | static void s_float_cons (int); | |
1344 | static void s_mips_globl (int); | |
1345 | static void s_option (int); | |
1346 | static void s_mipsset (int); | |
1347 | static void s_abicalls (int); | |
1348 | static void s_cpload (int); | |
1349 | static void s_cpsetup (int); | |
1350 | static void s_cplocal (int); | |
1351 | static void s_cprestore (int); | |
1352 | static void s_cpreturn (int); | |
741d6ea8 JM |
1353 | static void s_dtprelword (int); |
1354 | static void s_dtpreldword (int); | |
17a2f251 TS |
1355 | static void s_gpvalue (int); |
1356 | static void s_gpword (int); | |
1357 | static void s_gpdword (int); | |
1358 | static void s_cpadd (int); | |
1359 | static void s_insn (int); | |
1360 | static void md_obj_begin (void); | |
1361 | static void md_obj_end (void); | |
1362 | static void s_mips_ent (int); | |
1363 | static void s_mips_end (int); | |
1364 | static void s_mips_frame (int); | |
1365 | static void s_mips_mask (int reg_type); | |
1366 | static void s_mips_stab (int); | |
1367 | static void s_mips_weakext (int); | |
1368 | static void s_mips_file (int); | |
1369 | static void s_mips_loc (int); | |
1370 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 1371 | static int relaxed_branch_length (fragS *, asection *, int); |
17a2f251 | 1372 | static int validate_mips_insn (const struct mips_opcode *); |
df58fc94 RS |
1373 | static int validate_micromips_insn (const struct mips_opcode *); |
1374 | static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int); | |
1375 | static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int); | |
e7af610e NC |
1376 | |
1377 | /* Table and functions used to map between CPU/ISA names, and | |
1378 | ISA levels, and CPU numbers. */ | |
1379 | ||
e972090a NC |
1380 | struct mips_cpu_info |
1381 | { | |
e7af610e | 1382 | const char *name; /* CPU or ISA name. */ |
ad3fea08 | 1383 | int flags; /* ASEs available, or ISA flag. */ |
e7af610e NC |
1384 | int isa; /* ISA level. */ |
1385 | int cpu; /* CPU number (default CPU if ISA). */ | |
1386 | }; | |
1387 | ||
ad3fea08 TS |
1388 | #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ |
1389 | #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */ | |
1390 | #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */ | |
1391 | #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */ | |
1392 | #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */ | |
1393 | #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */ | |
8b082fb1 | 1394 | #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */ |
dec0624d | 1395 | #define MIPS_CPU_ASE_MCU 0x0080 /* CPU implements MCU ASE */ |
ad3fea08 | 1396 | |
17a2f251 TS |
1397 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
1398 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
1399 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 RH |
1400 | \f |
1401 | /* Pseudo-op table. | |
1402 | ||
1403 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
1404 | should be defined here, but are currently unsupported: .alias, | |
1405 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
1406 | ||
1407 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1408 | specific to the type of debugging information being generated, and | |
1409 | should be defined by the object format: .aent, .begin, .bend, | |
1410 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
1411 | .vreg. | |
1412 | ||
1413 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1414 | not MIPS CPU specific, but are also not specific to the object file | |
1415 | format. This file is probably the best place to define them, but | |
d84bcf09 | 1416 | they are not currently supported: .asm0, .endr, .lab, .struct. */ |
252b5132 | 1417 | |
e972090a NC |
1418 | static const pseudo_typeS mips_pseudo_table[] = |
1419 | { | |
beae10d5 | 1420 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1421 | {"option", s_option, 0}, |
1422 | {"set", s_mipsset, 0}, | |
1423 | {"rdata", s_change_sec, 'r'}, | |
1424 | {"sdata", s_change_sec, 's'}, | |
1425 | {"livereg", s_ignore, 0}, | |
1426 | {"abicalls", s_abicalls, 0}, | |
1427 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1428 | {"cpsetup", s_cpsetup, 0}, |
1429 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1430 | {"cprestore", s_cprestore, 0}, |
6478892d | 1431 | {"cpreturn", s_cpreturn, 0}, |
741d6ea8 JM |
1432 | {"dtprelword", s_dtprelword, 0}, |
1433 | {"dtpreldword", s_dtpreldword, 0}, | |
6478892d | 1434 | {"gpvalue", s_gpvalue, 0}, |
252b5132 | 1435 | {"gpword", s_gpword, 0}, |
10181a0d | 1436 | {"gpdword", s_gpdword, 0}, |
252b5132 RH |
1437 | {"cpadd", s_cpadd, 0}, |
1438 | {"insn", s_insn, 0}, | |
1439 | ||
beae10d5 | 1440 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 | 1441 | chips. */ |
38a57ae7 | 1442 | {"asciiz", stringer, 8 + 1}, |
252b5132 RH |
1443 | {"bss", s_change_sec, 'b'}, |
1444 | {"err", s_err, 0}, | |
1445 | {"half", s_cons, 1}, | |
1446 | {"dword", s_cons, 3}, | |
1447 | {"weakext", s_mips_weakext, 0}, | |
7c752c2a TS |
1448 | {"origin", s_org, 0}, |
1449 | {"repeat", s_rept, 0}, | |
252b5132 | 1450 | |
998b3c36 MR |
1451 | /* For MIPS this is non-standard, but we define it for consistency. */ |
1452 | {"sbss", s_change_sec, 'B'}, | |
1453 | ||
beae10d5 | 1454 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1455 | here for one reason or another. */ |
1456 | {"align", s_align, 0}, | |
1457 | {"byte", s_cons, 0}, | |
1458 | {"data", s_change_sec, 'd'}, | |
1459 | {"double", s_float_cons, 'd'}, | |
1460 | {"float", s_float_cons, 'f'}, | |
1461 | {"globl", s_mips_globl, 0}, | |
1462 | {"global", s_mips_globl, 0}, | |
1463 | {"hword", s_cons, 1}, | |
1464 | {"int", s_cons, 2}, | |
1465 | {"long", s_cons, 2}, | |
1466 | {"octa", s_cons, 4}, | |
1467 | {"quad", s_cons, 3}, | |
cca86cc8 | 1468 | {"section", s_change_section, 0}, |
252b5132 RH |
1469 | {"short", s_cons, 1}, |
1470 | {"single", s_float_cons, 'f'}, | |
1471 | {"stabn", s_mips_stab, 'n'}, | |
1472 | {"text", s_change_sec, 't'}, | |
1473 | {"word", s_cons, 2}, | |
add56521 | 1474 | |
add56521 | 1475 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1476 | |
43841e91 | 1477 | { NULL, NULL, 0 }, |
252b5132 RH |
1478 | }; |
1479 | ||
e972090a NC |
1480 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1481 | { | |
beae10d5 KH |
1482 | /* These pseudo-ops should be defined by the object file format. |
1483 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1484 | {"aent", s_mips_ent, 1}, |
1485 | {"bgnb", s_ignore, 0}, | |
1486 | {"end", s_mips_end, 0}, | |
1487 | {"endb", s_ignore, 0}, | |
1488 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1489 | {"file", s_mips_file, 0}, |
252b5132 RH |
1490 | {"fmask", s_mips_mask, 'F'}, |
1491 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1492 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1493 | {"mask", s_mips_mask, 'R'}, |
1494 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1495 | { NULL, NULL, 0 }, |
252b5132 RH |
1496 | }; |
1497 | ||
3ae8dd8d MR |
1498 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
1499 | purpose of the `.dc.a' internal pseudo-op. */ | |
1500 | ||
1501 | int | |
1502 | mips_address_bytes (void) | |
1503 | { | |
1504 | return HAVE_64BIT_ADDRESSES ? 8 : 4; | |
1505 | } | |
1506 | ||
17a2f251 | 1507 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1508 | |
1509 | void | |
17a2f251 | 1510 | mips_pop_insert (void) |
252b5132 RH |
1511 | { |
1512 | pop_insert (mips_pseudo_table); | |
1513 | if (! ECOFF_DEBUGGING) | |
1514 | pop_insert (mips_nonecoff_pseudo_table); | |
1515 | } | |
1516 | \f | |
1517 | /* Symbols labelling the current insn. */ | |
1518 | ||
e972090a NC |
1519 | struct insn_label_list |
1520 | { | |
252b5132 RH |
1521 | struct insn_label_list *next; |
1522 | symbolS *label; | |
1523 | }; | |
1524 | ||
252b5132 | 1525 | static struct insn_label_list *free_insn_labels; |
742a56fe | 1526 | #define label_list tc_segment_info_data.labels |
252b5132 | 1527 | |
17a2f251 | 1528 | static void mips_clear_insn_labels (void); |
df58fc94 RS |
1529 | static void mips_mark_labels (void); |
1530 | static void mips_compressed_mark_labels (void); | |
252b5132 RH |
1531 | |
1532 | static inline void | |
17a2f251 | 1533 | mips_clear_insn_labels (void) |
252b5132 RH |
1534 | { |
1535 | register struct insn_label_list **pl; | |
a8dbcb85 | 1536 | segment_info_type *si; |
252b5132 | 1537 | |
a8dbcb85 TS |
1538 | if (now_seg) |
1539 | { | |
1540 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1541 | ; | |
1542 | ||
1543 | si = seg_info (now_seg); | |
1544 | *pl = si->label_list; | |
1545 | si->label_list = NULL; | |
1546 | } | |
252b5132 | 1547 | } |
a8dbcb85 | 1548 | |
df58fc94 RS |
1549 | /* Mark instruction labels in MIPS16/microMIPS mode. */ |
1550 | ||
1551 | static inline void | |
1552 | mips_mark_labels (void) | |
1553 | { | |
1554 | if (HAVE_CODE_COMPRESSION) | |
1555 | mips_compressed_mark_labels (); | |
1556 | } | |
252b5132 RH |
1557 | \f |
1558 | static char *expr_end; | |
1559 | ||
1560 | /* Expressions which appear in instructions. These are set by | |
1561 | mips_ip. */ | |
1562 | ||
1563 | static expressionS imm_expr; | |
5f74bc13 | 1564 | static expressionS imm2_expr; |
252b5132 RH |
1565 | static expressionS offset_expr; |
1566 | ||
1567 | /* Relocs associated with imm_expr and offset_expr. */ | |
1568 | ||
f6688943 TS |
1569 | static bfd_reloc_code_real_type imm_reloc[3] |
1570 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1571 | static bfd_reloc_code_real_type offset_reloc[3] | |
1572 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1573 | |
df58fc94 RS |
1574 | /* This is set to the resulting size of the instruction to be produced |
1575 | by mips16_ip if an explicit extension is used or by mips_ip if an | |
1576 | explicit size is supplied. */ | |
252b5132 | 1577 | |
df58fc94 | 1578 | static unsigned int forced_insn_length; |
252b5132 | 1579 | |
7ed4a06a | 1580 | #ifdef OBJ_ELF |
ecb4347a DJ |
1581 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1582 | ECOFF debugging. */ | |
252b5132 RH |
1583 | |
1584 | static segT pdr_seg; | |
7ed4a06a | 1585 | #endif |
252b5132 | 1586 | |
e013f690 TS |
1587 | /* The default target format to use. */ |
1588 | ||
aeffff67 RS |
1589 | #if defined (TE_FreeBSD) |
1590 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd" | |
1591 | #elif defined (TE_TMIPS) | |
1592 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips" | |
1593 | #else | |
1594 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips" | |
1595 | #endif | |
1596 | ||
e013f690 | 1597 | const char * |
17a2f251 | 1598 | mips_target_format (void) |
e013f690 TS |
1599 | { |
1600 | switch (OUTPUT_FLAVOR) | |
1601 | { | |
e013f690 TS |
1602 | case bfd_target_ecoff_flavour: |
1603 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1604 | case bfd_target_coff_flavour: | |
1605 | return "pe-mips"; | |
1606 | case bfd_target_elf_flavour: | |
0a44bf69 RS |
1607 | #ifdef TE_VXWORKS |
1608 | if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI) | |
1609 | return (target_big_endian | |
1610 | ? "elf32-bigmips-vxworks" | |
1611 | : "elf32-littlemips-vxworks"); | |
1612 | #endif | |
e013f690 | 1613 | return (target_big_endian |
cfe86eaa | 1614 | ? (HAVE_64BIT_OBJECTS |
aeffff67 | 1615 | ? ELF_TARGET ("elf64-", "big") |
cfe86eaa | 1616 | : (HAVE_NEWABI |
aeffff67 RS |
1617 | ? ELF_TARGET ("elf32-n", "big") |
1618 | : ELF_TARGET ("elf32-", "big"))) | |
cfe86eaa | 1619 | : (HAVE_64BIT_OBJECTS |
aeffff67 | 1620 | ? ELF_TARGET ("elf64-", "little") |
cfe86eaa | 1621 | : (HAVE_NEWABI |
aeffff67 RS |
1622 | ? ELF_TARGET ("elf32-n", "little") |
1623 | : ELF_TARGET ("elf32-", "little")))); | |
e013f690 TS |
1624 | default: |
1625 | abort (); | |
1626 | return NULL; | |
1627 | } | |
1628 | } | |
1629 | ||
df58fc94 RS |
1630 | /* Return the length of a microMIPS instruction in bytes. If bits of |
1631 | the mask beyond the low 16 are 0, then it is a 16-bit instruction. | |
1632 | Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f | |
1633 | major opcode) will require further modifications to the opcode | |
1634 | table. */ | |
1635 | ||
1636 | static inline unsigned int | |
1637 | micromips_insn_length (const struct mips_opcode *mo) | |
1638 | { | |
1639 | return (mo->mask >> 16) == 0 ? 2 : 4; | |
1640 | } | |
1641 | ||
1e915849 RS |
1642 | /* Return the length of instruction INSN. */ |
1643 | ||
1644 | static inline unsigned int | |
1645 | insn_length (const struct mips_cl_insn *insn) | |
1646 | { | |
df58fc94 RS |
1647 | if (mips_opts.micromips) |
1648 | return micromips_insn_length (insn->insn_mo); | |
1649 | else if (mips_opts.mips16) | |
1650 | return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2; | |
1651 | else | |
1e915849 | 1652 | return 4; |
1e915849 RS |
1653 | } |
1654 | ||
1655 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
1656 | ||
1657 | static void | |
1658 | create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) | |
1659 | { | |
1660 | size_t i; | |
1661 | ||
1662 | insn->insn_mo = mo; | |
1663 | insn->use_extend = FALSE; | |
1664 | insn->extend = 0; | |
1665 | insn->insn_opcode = mo->match; | |
1666 | insn->frag = NULL; | |
1667 | insn->where = 0; | |
1668 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1669 | insn->fixp[i] = NULL; | |
1670 | insn->fixed_p = (mips_opts.noreorder > 0); | |
1671 | insn->noreorder_p = (mips_opts.noreorder > 0); | |
1672 | insn->mips16_absolute_jump_p = 0; | |
15be625d | 1673 | insn->complete_p = 0; |
1e915849 RS |
1674 | } |
1675 | ||
df58fc94 | 1676 | /* Record the current MIPS16/microMIPS mode in now_seg. */ |
742a56fe RS |
1677 | |
1678 | static void | |
df58fc94 | 1679 | mips_record_compressed_mode (void) |
742a56fe RS |
1680 | { |
1681 | segment_info_type *si; | |
1682 | ||
1683 | si = seg_info (now_seg); | |
1684 | if (si->tc_segment_info_data.mips16 != mips_opts.mips16) | |
1685 | si->tc_segment_info_data.mips16 = mips_opts.mips16; | |
df58fc94 RS |
1686 | if (si->tc_segment_info_data.micromips != mips_opts.micromips) |
1687 | si->tc_segment_info_data.micromips = mips_opts.micromips; | |
742a56fe RS |
1688 | } |
1689 | ||
1e915849 RS |
1690 | /* Install INSN at the location specified by its "frag" and "where" fields. */ |
1691 | ||
1692 | static void | |
1693 | install_insn (const struct mips_cl_insn *insn) | |
1694 | { | |
1695 | char *f = insn->frag->fr_literal + insn->where; | |
df58fc94 | 1696 | if (!HAVE_CODE_COMPRESSION) |
1e915849 | 1697 | md_number_to_chars (f, insn->insn_opcode, 4); |
df58fc94 RS |
1698 | else if (mips_opts.micromips) |
1699 | { | |
1700 | unsigned int length = insn_length (insn); | |
1701 | if (length == 2) | |
1702 | md_number_to_chars (f, insn->insn_opcode, 2); | |
1703 | else if (length == 4) | |
1704 | { | |
1705 | md_number_to_chars (f, insn->insn_opcode >> 16, 2); | |
1706 | f += 2; | |
1707 | md_number_to_chars (f, insn->insn_opcode & 0xffff, 2); | |
1708 | } | |
1709 | else | |
1710 | as_bad (_("48-bit microMIPS instructions are not supported")); | |
1711 | } | |
1e915849 RS |
1712 | else if (insn->mips16_absolute_jump_p) |
1713 | { | |
1714 | md_number_to_chars (f, insn->insn_opcode >> 16, 2); | |
1715 | md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2); | |
1716 | } | |
1717 | else | |
1718 | { | |
1719 | if (insn->use_extend) | |
1720 | { | |
1721 | md_number_to_chars (f, 0xf000 | insn->extend, 2); | |
1722 | f += 2; | |
1723 | } | |
1724 | md_number_to_chars (f, insn->insn_opcode, 2); | |
1725 | } | |
df58fc94 | 1726 | mips_record_compressed_mode (); |
1e915849 RS |
1727 | } |
1728 | ||
1729 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
1730 | and install the opcode in the new location. */ | |
1731 | ||
1732 | static void | |
1733 | move_insn (struct mips_cl_insn *insn, fragS *frag, long where) | |
1734 | { | |
1735 | size_t i; | |
1736 | ||
1737 | insn->frag = frag; | |
1738 | insn->where = where; | |
1739 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1740 | if (insn->fixp[i] != NULL) | |
1741 | { | |
1742 | insn->fixp[i]->fx_frag = frag; | |
1743 | insn->fixp[i]->fx_where = where; | |
1744 | } | |
1745 | install_insn (insn); | |
1746 | } | |
1747 | ||
1748 | /* Add INSN to the end of the output. */ | |
1749 | ||
1750 | static void | |
1751 | add_fixed_insn (struct mips_cl_insn *insn) | |
1752 | { | |
1753 | char *f = frag_more (insn_length (insn)); | |
1754 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
1755 | } | |
1756 | ||
1757 | /* Start a variant frag and move INSN to the start of the variant part, | |
1758 | marking it as fixed. The other arguments are as for frag_var. */ | |
1759 | ||
1760 | static void | |
1761 | add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, | |
1762 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
1763 | { | |
1764 | frag_grow (max_chars); | |
1765 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
1766 | insn->fixed_p = 1; | |
1767 | frag_var (rs_machine_dependent, max_chars, var, | |
1768 | subtype, symbol, offset, NULL); | |
1769 | } | |
1770 | ||
1771 | /* Insert N copies of INSN into the history buffer, starting at | |
1772 | position FIRST. Neither FIRST nor N need to be clipped. */ | |
1773 | ||
1774 | static void | |
1775 | insert_into_history (unsigned int first, unsigned int n, | |
1776 | const struct mips_cl_insn *insn) | |
1777 | { | |
1778 | if (mips_relax.sequence != 2) | |
1779 | { | |
1780 | unsigned int i; | |
1781 | ||
1782 | for (i = ARRAY_SIZE (history); i-- > first;) | |
1783 | if (i >= first + n) | |
1784 | history[i] = history[i - n]; | |
1785 | else | |
1786 | history[i] = *insn; | |
1787 | } | |
1788 | } | |
1789 | ||
71400594 RS |
1790 | /* Initialize vr4120_conflicts. There is a bit of duplication here: |
1791 | the idea is to make it obvious at a glance that each errata is | |
1792 | included. */ | |
1793 | ||
1794 | static void | |
1795 | init_vr4120_conflicts (void) | |
1796 | { | |
1797 | #define CONFLICT(FIRST, SECOND) \ | |
1798 | vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND | |
1799 | ||
1800 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
1801 | CONFLICT (MACC, DIV); | |
1802 | CONFLICT (DMACC, DIV); | |
1803 | ||
1804 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ | |
1805 | CONFLICT (DMULT, DMULT); | |
1806 | CONFLICT (DMULT, DMACC); | |
1807 | CONFLICT (DMACC, DMULT); | |
1808 | CONFLICT (DMACC, DMACC); | |
1809 | ||
1810 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
1811 | CONFLICT (MACC, MTHILO); | |
1812 | CONFLICT (DMACC, MTHILO); | |
1813 | ||
1814 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU | |
1815 | instruction is executed immediately after a MACC or DMACC | |
1816 | instruction, the result of [either instruction] is incorrect." */ | |
1817 | CONFLICT (MACC, MULT); | |
1818 | CONFLICT (MACC, DMULT); | |
1819 | CONFLICT (DMACC, MULT); | |
1820 | CONFLICT (DMACC, DMULT); | |
1821 | ||
1822 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
1823 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
1824 | DDIV or DDIVU instruction, the result of the MACC or | |
1825 | DMACC instruction is incorrect.". */ | |
1826 | CONFLICT (DMULT, MACC); | |
1827 | CONFLICT (DMULT, DMACC); | |
1828 | CONFLICT (DIV, MACC); | |
1829 | CONFLICT (DIV, DMACC); | |
1830 | ||
1831 | #undef CONFLICT | |
1832 | } | |
1833 | ||
707bfff6 TS |
1834 | struct regname { |
1835 | const char *name; | |
1836 | unsigned int num; | |
1837 | }; | |
1838 | ||
1839 | #define RTYPE_MASK 0x1ff00 | |
1840 | #define RTYPE_NUM 0x00100 | |
1841 | #define RTYPE_FPU 0x00200 | |
1842 | #define RTYPE_FCC 0x00400 | |
1843 | #define RTYPE_VEC 0x00800 | |
1844 | #define RTYPE_GP 0x01000 | |
1845 | #define RTYPE_CP0 0x02000 | |
1846 | #define RTYPE_PC 0x04000 | |
1847 | #define RTYPE_ACC 0x08000 | |
1848 | #define RTYPE_CCC 0x10000 | |
1849 | #define RNUM_MASK 0x000ff | |
1850 | #define RWARN 0x80000 | |
1851 | ||
1852 | #define GENERIC_REGISTER_NUMBERS \ | |
1853 | {"$0", RTYPE_NUM | 0}, \ | |
1854 | {"$1", RTYPE_NUM | 1}, \ | |
1855 | {"$2", RTYPE_NUM | 2}, \ | |
1856 | {"$3", RTYPE_NUM | 3}, \ | |
1857 | {"$4", RTYPE_NUM | 4}, \ | |
1858 | {"$5", RTYPE_NUM | 5}, \ | |
1859 | {"$6", RTYPE_NUM | 6}, \ | |
1860 | {"$7", RTYPE_NUM | 7}, \ | |
1861 | {"$8", RTYPE_NUM | 8}, \ | |
1862 | {"$9", RTYPE_NUM | 9}, \ | |
1863 | {"$10", RTYPE_NUM | 10}, \ | |
1864 | {"$11", RTYPE_NUM | 11}, \ | |
1865 | {"$12", RTYPE_NUM | 12}, \ | |
1866 | {"$13", RTYPE_NUM | 13}, \ | |
1867 | {"$14", RTYPE_NUM | 14}, \ | |
1868 | {"$15", RTYPE_NUM | 15}, \ | |
1869 | {"$16", RTYPE_NUM | 16}, \ | |
1870 | {"$17", RTYPE_NUM | 17}, \ | |
1871 | {"$18", RTYPE_NUM | 18}, \ | |
1872 | {"$19", RTYPE_NUM | 19}, \ | |
1873 | {"$20", RTYPE_NUM | 20}, \ | |
1874 | {"$21", RTYPE_NUM | 21}, \ | |
1875 | {"$22", RTYPE_NUM | 22}, \ | |
1876 | {"$23", RTYPE_NUM | 23}, \ | |
1877 | {"$24", RTYPE_NUM | 24}, \ | |
1878 | {"$25", RTYPE_NUM | 25}, \ | |
1879 | {"$26", RTYPE_NUM | 26}, \ | |
1880 | {"$27", RTYPE_NUM | 27}, \ | |
1881 | {"$28", RTYPE_NUM | 28}, \ | |
1882 | {"$29", RTYPE_NUM | 29}, \ | |
1883 | {"$30", RTYPE_NUM | 30}, \ | |
1884 | {"$31", RTYPE_NUM | 31} | |
1885 | ||
1886 | #define FPU_REGISTER_NAMES \ | |
1887 | {"$f0", RTYPE_FPU | 0}, \ | |
1888 | {"$f1", RTYPE_FPU | 1}, \ | |
1889 | {"$f2", RTYPE_FPU | 2}, \ | |
1890 | {"$f3", RTYPE_FPU | 3}, \ | |
1891 | {"$f4", RTYPE_FPU | 4}, \ | |
1892 | {"$f5", RTYPE_FPU | 5}, \ | |
1893 | {"$f6", RTYPE_FPU | 6}, \ | |
1894 | {"$f7", RTYPE_FPU | 7}, \ | |
1895 | {"$f8", RTYPE_FPU | 8}, \ | |
1896 | {"$f9", RTYPE_FPU | 9}, \ | |
1897 | {"$f10", RTYPE_FPU | 10}, \ | |
1898 | {"$f11", RTYPE_FPU | 11}, \ | |
1899 | {"$f12", RTYPE_FPU | 12}, \ | |
1900 | {"$f13", RTYPE_FPU | 13}, \ | |
1901 | {"$f14", RTYPE_FPU | 14}, \ | |
1902 | {"$f15", RTYPE_FPU | 15}, \ | |
1903 | {"$f16", RTYPE_FPU | 16}, \ | |
1904 | {"$f17", RTYPE_FPU | 17}, \ | |
1905 | {"$f18", RTYPE_FPU | 18}, \ | |
1906 | {"$f19", RTYPE_FPU | 19}, \ | |
1907 | {"$f20", RTYPE_FPU | 20}, \ | |
1908 | {"$f21", RTYPE_FPU | 21}, \ | |
1909 | {"$f22", RTYPE_FPU | 22}, \ | |
1910 | {"$f23", RTYPE_FPU | 23}, \ | |
1911 | {"$f24", RTYPE_FPU | 24}, \ | |
1912 | {"$f25", RTYPE_FPU | 25}, \ | |
1913 | {"$f26", RTYPE_FPU | 26}, \ | |
1914 | {"$f27", RTYPE_FPU | 27}, \ | |
1915 | {"$f28", RTYPE_FPU | 28}, \ | |
1916 | {"$f29", RTYPE_FPU | 29}, \ | |
1917 | {"$f30", RTYPE_FPU | 30}, \ | |
1918 | {"$f31", RTYPE_FPU | 31} | |
1919 | ||
1920 | #define FPU_CONDITION_CODE_NAMES \ | |
1921 | {"$fcc0", RTYPE_FCC | 0}, \ | |
1922 | {"$fcc1", RTYPE_FCC | 1}, \ | |
1923 | {"$fcc2", RTYPE_FCC | 2}, \ | |
1924 | {"$fcc3", RTYPE_FCC | 3}, \ | |
1925 | {"$fcc4", RTYPE_FCC | 4}, \ | |
1926 | {"$fcc5", RTYPE_FCC | 5}, \ | |
1927 | {"$fcc6", RTYPE_FCC | 6}, \ | |
1928 | {"$fcc7", RTYPE_FCC | 7} | |
1929 | ||
1930 | #define COPROC_CONDITION_CODE_NAMES \ | |
1931 | {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \ | |
1932 | {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \ | |
1933 | {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \ | |
1934 | {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \ | |
1935 | {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \ | |
1936 | {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \ | |
1937 | {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \ | |
1938 | {"$cc7", RTYPE_FCC | RTYPE_CCC | 7} | |
1939 | ||
1940 | #define N32N64_SYMBOLIC_REGISTER_NAMES \ | |
1941 | {"$a4", RTYPE_GP | 8}, \ | |
1942 | {"$a5", RTYPE_GP | 9}, \ | |
1943 | {"$a6", RTYPE_GP | 10}, \ | |
1944 | {"$a7", RTYPE_GP | 11}, \ | |
1945 | {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \ | |
1946 | {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \ | |
1947 | {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \ | |
1948 | {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \ | |
1949 | {"$t0", RTYPE_GP | 12}, \ | |
1950 | {"$t1", RTYPE_GP | 13}, \ | |
1951 | {"$t2", RTYPE_GP | 14}, \ | |
1952 | {"$t3", RTYPE_GP | 15} | |
1953 | ||
1954 | #define O32_SYMBOLIC_REGISTER_NAMES \ | |
1955 | {"$t0", RTYPE_GP | 8}, \ | |
1956 | {"$t1", RTYPE_GP | 9}, \ | |
1957 | {"$t2", RTYPE_GP | 10}, \ | |
1958 | {"$t3", RTYPE_GP | 11}, \ | |
1959 | {"$t4", RTYPE_GP | 12}, \ | |
1960 | {"$t5", RTYPE_GP | 13}, \ | |
1961 | {"$t6", RTYPE_GP | 14}, \ | |
1962 | {"$t7", RTYPE_GP | 15}, \ | |
1963 | {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \ | |
1964 | {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \ | |
1965 | {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \ | |
1966 | {"$ta3", RTYPE_GP | 15} /* alias for $t7 */ | |
1967 | ||
1968 | /* Remaining symbolic register names */ | |
1969 | #define SYMBOLIC_REGISTER_NAMES \ | |
1970 | {"$zero", RTYPE_GP | 0}, \ | |
1971 | {"$at", RTYPE_GP | 1}, \ | |
1972 | {"$AT", RTYPE_GP | 1}, \ | |
1973 | {"$v0", RTYPE_GP | 2}, \ | |
1974 | {"$v1", RTYPE_GP | 3}, \ | |
1975 | {"$a0", RTYPE_GP | 4}, \ | |
1976 | {"$a1", RTYPE_GP | 5}, \ | |
1977 | {"$a2", RTYPE_GP | 6}, \ | |
1978 | {"$a3", RTYPE_GP | 7}, \ | |
1979 | {"$s0", RTYPE_GP | 16}, \ | |
1980 | {"$s1", RTYPE_GP | 17}, \ | |
1981 | {"$s2", RTYPE_GP | 18}, \ | |
1982 | {"$s3", RTYPE_GP | 19}, \ | |
1983 | {"$s4", RTYPE_GP | 20}, \ | |
1984 | {"$s5", RTYPE_GP | 21}, \ | |
1985 | {"$s6", RTYPE_GP | 22}, \ | |
1986 | {"$s7", RTYPE_GP | 23}, \ | |
1987 | {"$t8", RTYPE_GP | 24}, \ | |
1988 | {"$t9", RTYPE_GP | 25}, \ | |
1989 | {"$k0", RTYPE_GP | 26}, \ | |
1990 | {"$kt0", RTYPE_GP | 26}, \ | |
1991 | {"$k1", RTYPE_GP | 27}, \ | |
1992 | {"$kt1", RTYPE_GP | 27}, \ | |
1993 | {"$gp", RTYPE_GP | 28}, \ | |
1994 | {"$sp", RTYPE_GP | 29}, \ | |
1995 | {"$s8", RTYPE_GP | 30}, \ | |
1996 | {"$fp", RTYPE_GP | 30}, \ | |
1997 | {"$ra", RTYPE_GP | 31} | |
1998 | ||
1999 | #define MIPS16_SPECIAL_REGISTER_NAMES \ | |
2000 | {"$pc", RTYPE_PC | 0} | |
2001 | ||
2002 | #define MDMX_VECTOR_REGISTER_NAMES \ | |
2003 | /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \ | |
2004 | /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \ | |
2005 | {"$v2", RTYPE_VEC | 2}, \ | |
2006 | {"$v3", RTYPE_VEC | 3}, \ | |
2007 | {"$v4", RTYPE_VEC | 4}, \ | |
2008 | {"$v5", RTYPE_VEC | 5}, \ | |
2009 | {"$v6", RTYPE_VEC | 6}, \ | |
2010 | {"$v7", RTYPE_VEC | 7}, \ | |
2011 | {"$v8", RTYPE_VEC | 8}, \ | |
2012 | {"$v9", RTYPE_VEC | 9}, \ | |
2013 | {"$v10", RTYPE_VEC | 10}, \ | |
2014 | {"$v11", RTYPE_VEC | 11}, \ | |
2015 | {"$v12", RTYPE_VEC | 12}, \ | |
2016 | {"$v13", RTYPE_VEC | 13}, \ | |
2017 | {"$v14", RTYPE_VEC | 14}, \ | |
2018 | {"$v15", RTYPE_VEC | 15}, \ | |
2019 | {"$v16", RTYPE_VEC | 16}, \ | |
2020 | {"$v17", RTYPE_VEC | 17}, \ | |
2021 | {"$v18", RTYPE_VEC | 18}, \ | |
2022 | {"$v19", RTYPE_VEC | 19}, \ | |
2023 | {"$v20", RTYPE_VEC | 20}, \ | |
2024 | {"$v21", RTYPE_VEC | 21}, \ | |
2025 | {"$v22", RTYPE_VEC | 22}, \ | |
2026 | {"$v23", RTYPE_VEC | 23}, \ | |
2027 | {"$v24", RTYPE_VEC | 24}, \ | |
2028 | {"$v25", RTYPE_VEC | 25}, \ | |
2029 | {"$v26", RTYPE_VEC | 26}, \ | |
2030 | {"$v27", RTYPE_VEC | 27}, \ | |
2031 | {"$v28", RTYPE_VEC | 28}, \ | |
2032 | {"$v29", RTYPE_VEC | 29}, \ | |
2033 | {"$v30", RTYPE_VEC | 30}, \ | |
2034 | {"$v31", RTYPE_VEC | 31} | |
2035 | ||
2036 | #define MIPS_DSP_ACCUMULATOR_NAMES \ | |
2037 | {"$ac0", RTYPE_ACC | 0}, \ | |
2038 | {"$ac1", RTYPE_ACC | 1}, \ | |
2039 | {"$ac2", RTYPE_ACC | 2}, \ | |
2040 | {"$ac3", RTYPE_ACC | 3} | |
2041 | ||
2042 | static const struct regname reg_names[] = { | |
2043 | GENERIC_REGISTER_NUMBERS, | |
2044 | FPU_REGISTER_NAMES, | |
2045 | FPU_CONDITION_CODE_NAMES, | |
2046 | COPROC_CONDITION_CODE_NAMES, | |
2047 | ||
2048 | /* The $txx registers depends on the abi, | |
2049 | these will be added later into the symbol table from | |
2050 | one of the tables below once mips_abi is set after | |
2051 | parsing of arguments from the command line. */ | |
2052 | SYMBOLIC_REGISTER_NAMES, | |
2053 | ||
2054 | MIPS16_SPECIAL_REGISTER_NAMES, | |
2055 | MDMX_VECTOR_REGISTER_NAMES, | |
2056 | MIPS_DSP_ACCUMULATOR_NAMES, | |
2057 | {0, 0} | |
2058 | }; | |
2059 | ||
2060 | static const struct regname reg_names_o32[] = { | |
2061 | O32_SYMBOLIC_REGISTER_NAMES, | |
2062 | {0, 0} | |
2063 | }; | |
2064 | ||
2065 | static const struct regname reg_names_n32n64[] = { | |
2066 | N32N64_SYMBOLIC_REGISTER_NAMES, | |
2067 | {0, 0} | |
2068 | }; | |
2069 | ||
df58fc94 RS |
2070 | /* Check if S points at a valid register specifier according to TYPES. |
2071 | If so, then return 1, advance S to consume the specifier and store | |
2072 | the register's number in REGNOP, otherwise return 0. */ | |
2073 | ||
707bfff6 TS |
2074 | static int |
2075 | reg_lookup (char **s, unsigned int types, unsigned int *regnop) | |
2076 | { | |
2077 | symbolS *symbolP; | |
2078 | char *e; | |
2079 | char save_c; | |
2080 | int reg = -1; | |
2081 | ||
2082 | /* Find end of name. */ | |
2083 | e = *s; | |
2084 | if (is_name_beginner (*e)) | |
2085 | ++e; | |
2086 | while (is_part_of_name (*e)) | |
2087 | ++e; | |
2088 | ||
2089 | /* Terminate name. */ | |
2090 | save_c = *e; | |
2091 | *e = '\0'; | |
2092 | ||
2093 | /* Look for a register symbol. */ | |
2094 | if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section) | |
2095 | { | |
2096 | int r = S_GET_VALUE (symbolP); | |
2097 | if (r & types) | |
2098 | reg = r & RNUM_MASK; | |
2099 | else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2)) | |
2100 | /* Convert GP reg $v0/1 to MDMX reg $v0/1! */ | |
2101 | reg = (r & RNUM_MASK) - 2; | |
2102 | } | |
2103 | /* Else see if this is a register defined in an itbl entry. */ | |
2104 | else if ((types & RTYPE_GP) && itbl_have_entries) | |
2105 | { | |
2106 | char *n = *s; | |
2107 | unsigned long r; | |
2108 | ||
2109 | if (*n == '$') | |
2110 | ++n; | |
2111 | if (itbl_get_reg_val (n, &r)) | |
2112 | reg = r & RNUM_MASK; | |
2113 | } | |
2114 | ||
2115 | /* Advance to next token if a register was recognised. */ | |
2116 | if (reg >= 0) | |
2117 | *s = e; | |
2118 | else if (types & RWARN) | |
20203fb9 | 2119 | as_warn (_("Unrecognized register name `%s'"), *s); |
707bfff6 TS |
2120 | |
2121 | *e = save_c; | |
2122 | if (regnop) | |
2123 | *regnop = reg; | |
2124 | return reg >= 0; | |
2125 | } | |
2126 | ||
df58fc94 RS |
2127 | /* Check if S points at a valid register list according to TYPES. |
2128 | If so, then return 1, advance S to consume the list and store | |
2129 | the registers present on the list as a bitmask of ones in REGLISTP, | |
2130 | otherwise return 0. A valid list comprises a comma-separated | |
2131 | enumeration of valid single registers and/or dash-separated | |
2132 | contiguous register ranges as determined by their numbers. | |
2133 | ||
2134 | As a special exception if one of s0-s7 registers is specified as | |
2135 | the range's lower delimiter and s8 (fp) is its upper one, then no | |
2136 | registers whose numbers place them between s7 and s8 (i.e. $24-$29) | |
2309ddf2 | 2137 | are selected; they have to be listed separately if needed. */ |
df58fc94 RS |
2138 | |
2139 | static int | |
2140 | reglist_lookup (char **s, unsigned int types, unsigned int *reglistp) | |
2141 | { | |
2142 | unsigned int reglist = 0; | |
2143 | unsigned int lastregno; | |
2144 | bfd_boolean ok = TRUE; | |
2145 | unsigned int regmask; | |
2309ddf2 | 2146 | char *s_endlist = *s; |
df58fc94 | 2147 | char *s_reset = *s; |
2309ddf2 | 2148 | unsigned int regno; |
df58fc94 RS |
2149 | |
2150 | while (reg_lookup (s, types, ®no)) | |
2151 | { | |
2152 | lastregno = regno; | |
2153 | if (**s == '-') | |
2154 | { | |
2155 | (*s)++; | |
2156 | ok = reg_lookup (s, types, &lastregno); | |
2157 | if (ok && lastregno < regno) | |
2158 | ok = FALSE; | |
2159 | if (!ok) | |
2160 | break; | |
2161 | } | |
2162 | ||
2163 | if (lastregno == FP && regno >= S0 && regno <= S7) | |
2164 | { | |
2165 | lastregno = S7; | |
2166 | reglist |= 1 << FP; | |
2167 | } | |
2168 | regmask = 1 << lastregno; | |
2169 | regmask = (regmask << 1) - 1; | |
2170 | regmask ^= (1 << regno) - 1; | |
2171 | reglist |= regmask; | |
2172 | ||
2309ddf2 | 2173 | s_endlist = *s; |
df58fc94 RS |
2174 | if (**s != ',') |
2175 | break; | |
2176 | (*s)++; | |
2177 | } | |
2178 | ||
2179 | if (ok) | |
2309ddf2 | 2180 | *s = s_endlist; |
df58fc94 RS |
2181 | else |
2182 | *s = s_reset; | |
2183 | if (reglistp) | |
2184 | *reglistp = reglist; | |
2185 | return ok && reglist != 0; | |
2186 | } | |
2187 | ||
037b32b9 | 2188 | /* Return TRUE if opcode MO is valid on the currently selected ISA and |
f79e2745 | 2189 | architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */ |
037b32b9 AN |
2190 | |
2191 | static bfd_boolean | |
f79e2745 | 2192 | is_opcode_valid (const struct mips_opcode *mo) |
037b32b9 AN |
2193 | { |
2194 | int isa = mips_opts.isa; | |
2195 | int fp_s, fp_d; | |
2196 | ||
2197 | if (mips_opts.ase_mdmx) | |
2198 | isa |= INSN_MDMX; | |
2199 | if (mips_opts.ase_dsp) | |
2200 | isa |= INSN_DSP; | |
2201 | if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE) | |
2202 | isa |= INSN_DSP64; | |
2203 | if (mips_opts.ase_dspr2) | |
2204 | isa |= INSN_DSPR2; | |
2205 | if (mips_opts.ase_mt) | |
2206 | isa |= INSN_MT; | |
2207 | if (mips_opts.ase_mips3d) | |
2208 | isa |= INSN_MIPS3D; | |
2209 | if (mips_opts.ase_smartmips) | |
2210 | isa |= INSN_SMARTMIPS; | |
dec0624d MR |
2211 | if (mips_opts.ase_mcu) |
2212 | isa |= INSN_MCU; | |
037b32b9 | 2213 | |
b19e8a9b AN |
2214 | /* Don't accept instructions based on the ISA if the CPU does not implement |
2215 | all the coprocessor insns. */ | |
2216 | if (NO_ISA_COP (mips_opts.arch) | |
2217 | && COP_INSN (mo->pinfo)) | |
2218 | isa = 0; | |
2219 | ||
037b32b9 AN |
2220 | if (!OPCODE_IS_MEMBER (mo, isa, mips_opts.arch)) |
2221 | return FALSE; | |
2222 | ||
2223 | /* Check whether the instruction or macro requires single-precision or | |
2224 | double-precision floating-point support. Note that this information is | |
2225 | stored differently in the opcode table for insns and macros. */ | |
2226 | if (mo->pinfo == INSN_MACRO) | |
2227 | { | |
2228 | fp_s = mo->pinfo2 & INSN2_M_FP_S; | |
2229 | fp_d = mo->pinfo2 & INSN2_M_FP_D; | |
2230 | } | |
2231 | else | |
2232 | { | |
2233 | fp_s = mo->pinfo & FP_S; | |
2234 | fp_d = mo->pinfo & FP_D; | |
2235 | } | |
2236 | ||
2237 | if (fp_d && (mips_opts.soft_float || mips_opts.single_float)) | |
2238 | return FALSE; | |
2239 | ||
2240 | if (fp_s && mips_opts.soft_float) | |
2241 | return FALSE; | |
2242 | ||
2243 | return TRUE; | |
2244 | } | |
2245 | ||
2246 | /* Return TRUE if the MIPS16 opcode MO is valid on the currently | |
2247 | selected ISA and architecture. */ | |
2248 | ||
2249 | static bfd_boolean | |
2250 | is_opcode_valid_16 (const struct mips_opcode *mo) | |
2251 | { | |
2252 | return OPCODE_IS_MEMBER (mo, mips_opts.isa, mips_opts.arch) ? TRUE : FALSE; | |
2253 | } | |
2254 | ||
df58fc94 RS |
2255 | /* Return TRUE if the size of the microMIPS opcode MO matches one |
2256 | explicitly requested. Always TRUE in the standard MIPS mode. */ | |
2257 | ||
2258 | static bfd_boolean | |
2259 | is_size_valid (const struct mips_opcode *mo) | |
2260 | { | |
2261 | if (!mips_opts.micromips) | |
2262 | return TRUE; | |
2263 | ||
2264 | if (!forced_insn_length) | |
2265 | return TRUE; | |
2266 | if (mo->pinfo == INSN_MACRO) | |
2267 | return FALSE; | |
2268 | return forced_insn_length == micromips_insn_length (mo); | |
2269 | } | |
2270 | ||
2271 | /* Return TRUE if the microMIPS opcode MO is valid for the delay slot | |
2272 | of the preceding instruction. Always TRUE in the standard MIPS mode. */ | |
2273 | ||
2274 | static bfd_boolean | |
2275 | is_delay_slot_valid (const struct mips_opcode *mo) | |
2276 | { | |
2277 | if (!mips_opts.micromips) | |
2278 | return TRUE; | |
2279 | ||
2280 | if (mo->pinfo == INSN_MACRO) | |
2281 | return TRUE; | |
2282 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 | |
2283 | && micromips_insn_length (mo) != 4) | |
2284 | return FALSE; | |
2285 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 | |
2286 | && micromips_insn_length (mo) != 2) | |
2287 | return FALSE; | |
2288 | ||
2289 | return TRUE; | |
2290 | } | |
2291 | ||
707bfff6 TS |
2292 | /* This function is called once, at assembler startup time. It should set up |
2293 | all the tables, etc. that the MD part of the assembler will need. */ | |
156c2f8b | 2294 | |
252b5132 | 2295 | void |
17a2f251 | 2296 | md_begin (void) |
252b5132 | 2297 | { |
3994f87e | 2298 | const char *retval = NULL; |
156c2f8b | 2299 | int i = 0; |
252b5132 | 2300 | int broken = 0; |
1f25f5d3 | 2301 | |
0a44bf69 RS |
2302 | if (mips_pic != NO_PIC) |
2303 | { | |
2304 | if (g_switch_seen && g_switch_value != 0) | |
2305 | as_bad (_("-G may not be used in position-independent code")); | |
2306 | g_switch_value = 0; | |
2307 | } | |
2308 | ||
fef14a42 | 2309 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) |
252b5132 RH |
2310 | as_warn (_("Could not set architecture and machine")); |
2311 | ||
252b5132 RH |
2312 | op_hash = hash_new (); |
2313 | ||
2314 | for (i = 0; i < NUMOPCODES;) | |
2315 | { | |
2316 | const char *name = mips_opcodes[i].name; | |
2317 | ||
17a2f251 | 2318 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
2319 | if (retval != NULL) |
2320 | { | |
2321 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
2322 | mips_opcodes[i].name, retval); | |
2323 | /* Probably a memory allocation problem? Give up now. */ | |
2324 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
2325 | } | |
2326 | do | |
2327 | { | |
2328 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
2329 | { | |
2330 | if (!validate_mips_insn (&mips_opcodes[i])) | |
2331 | broken = 1; | |
1e915849 RS |
2332 | if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
2333 | { | |
2334 | create_insn (&nop_insn, mips_opcodes + i); | |
c67a084a NC |
2335 | if (mips_fix_loongson2f_nop) |
2336 | nop_insn.insn_opcode = LOONGSON2F_NOP_INSN; | |
1e915849 RS |
2337 | nop_insn.fixed_p = 1; |
2338 | } | |
252b5132 RH |
2339 | } |
2340 | ++i; | |
2341 | } | |
2342 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
2343 | } | |
2344 | ||
2345 | mips16_op_hash = hash_new (); | |
2346 | ||
2347 | i = 0; | |
2348 | while (i < bfd_mips16_num_opcodes) | |
2349 | { | |
2350 | const char *name = mips16_opcodes[i].name; | |
2351 | ||
17a2f251 | 2352 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
2353 | if (retval != NULL) |
2354 | as_fatal (_("internal: can't hash `%s': %s"), | |
2355 | mips16_opcodes[i].name, retval); | |
2356 | do | |
2357 | { | |
2358 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
2359 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
2360 | != mips16_opcodes[i].match)) | |
2361 | { | |
2362 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
2363 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
2364 | broken = 1; | |
2365 | } | |
1e915849 RS |
2366 | if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
2367 | { | |
2368 | create_insn (&mips16_nop_insn, mips16_opcodes + i); | |
2369 | mips16_nop_insn.fixed_p = 1; | |
2370 | } | |
252b5132 RH |
2371 | ++i; |
2372 | } | |
2373 | while (i < bfd_mips16_num_opcodes | |
2374 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
2375 | } | |
2376 | ||
df58fc94 RS |
2377 | micromips_op_hash = hash_new (); |
2378 | ||
2379 | i = 0; | |
2380 | while (i < bfd_micromips_num_opcodes) | |
2381 | { | |
2382 | const char *name = micromips_opcodes[i].name; | |
2383 | ||
2384 | retval = hash_insert (micromips_op_hash, name, | |
2385 | (void *) µmips_opcodes[i]); | |
2386 | if (retval != NULL) | |
2387 | as_fatal (_("internal: can't hash `%s': %s"), | |
2388 | micromips_opcodes[i].name, retval); | |
2389 | do | |
2390 | if (micromips_opcodes[i].pinfo != INSN_MACRO) | |
2391 | { | |
2392 | struct mips_cl_insn *micromips_nop_insn; | |
2393 | ||
2394 | if (!validate_micromips_insn (µmips_opcodes[i])) | |
2395 | broken = 1; | |
2396 | ||
2397 | if (micromips_insn_length (micromips_opcodes + i) == 2) | |
2398 | micromips_nop_insn = µmips_nop16_insn; | |
2399 | else if (micromips_insn_length (micromips_opcodes + i) == 4) | |
2400 | micromips_nop_insn = µmips_nop32_insn; | |
2401 | else | |
2402 | continue; | |
2403 | ||
2404 | if (micromips_nop_insn->insn_mo == NULL | |
2405 | && strcmp (name, "nop") == 0) | |
2406 | { | |
2407 | create_insn (micromips_nop_insn, micromips_opcodes + i); | |
2408 | micromips_nop_insn->fixed_p = 1; | |
2409 | } | |
2410 | } | |
2411 | while (++i < bfd_micromips_num_opcodes | |
2412 | && strcmp (micromips_opcodes[i].name, name) == 0); | |
2413 | } | |
2414 | ||
252b5132 RH |
2415 | if (broken) |
2416 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
2417 | ||
2418 | /* We add all the general register names to the symbol table. This | |
2419 | helps us detect invalid uses of them. */ | |
707bfff6 TS |
2420 | for (i = 0; reg_names[i].name; i++) |
2421 | symbol_table_insert (symbol_new (reg_names[i].name, reg_section, | |
8fc4ee9b | 2422 | reg_names[i].num, /* & RNUM_MASK, */ |
707bfff6 TS |
2423 | &zero_address_frag)); |
2424 | if (HAVE_NEWABI) | |
2425 | for (i = 0; reg_names_n32n64[i].name; i++) | |
2426 | symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section, | |
8fc4ee9b | 2427 | reg_names_n32n64[i].num, /* & RNUM_MASK, */ |
252b5132 | 2428 | &zero_address_frag)); |
707bfff6 TS |
2429 | else |
2430 | for (i = 0; reg_names_o32[i].name; i++) | |
2431 | symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section, | |
8fc4ee9b | 2432 | reg_names_o32[i].num, /* & RNUM_MASK, */ |
6047c971 | 2433 | &zero_address_frag)); |
6047c971 | 2434 | |
7d10b47d | 2435 | mips_no_prev_insn (); |
252b5132 RH |
2436 | |
2437 | mips_gprmask = 0; | |
2438 | mips_cprmask[0] = 0; | |
2439 | mips_cprmask[1] = 0; | |
2440 | mips_cprmask[2] = 0; | |
2441 | mips_cprmask[3] = 0; | |
2442 | ||
2443 | /* set the default alignment for the text section (2**2) */ | |
2444 | record_alignment (text_section, 2); | |
2445 | ||
4d0d148d | 2446 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 | 2447 | |
707bfff6 | 2448 | #ifdef OBJ_ELF |
f43abd2b | 2449 | if (IS_ELF) |
252b5132 | 2450 | { |
0a44bf69 RS |
2451 | /* On a native system other than VxWorks, sections must be aligned |
2452 | to 16 byte boundaries. When configured for an embedded ELF | |
2453 | target, we don't bother. */ | |
c41e87e3 CF |
2454 | if (strncmp (TARGET_OS, "elf", 3) != 0 |
2455 | && strncmp (TARGET_OS, "vxworks", 7) != 0) | |
252b5132 RH |
2456 | { |
2457 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
2458 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
2459 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
2460 | } | |
2461 | ||
2462 | /* Create a .reginfo section for register masks and a .mdebug | |
2463 | section for debugging information. */ | |
2464 | { | |
2465 | segT seg; | |
2466 | subsegT subseg; | |
2467 | flagword flags; | |
2468 | segT sec; | |
2469 | ||
2470 | seg = now_seg; | |
2471 | subseg = now_subseg; | |
2472 | ||
2473 | /* The ABI says this section should be loaded so that the | |
2474 | running program can access it. However, we don't load it | |
2475 | if we are configured for an embedded target */ | |
2476 | flags = SEC_READONLY | SEC_DATA; | |
c41e87e3 | 2477 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
252b5132 RH |
2478 | flags |= SEC_ALLOC | SEC_LOAD; |
2479 | ||
316f5878 | 2480 | if (mips_abi != N64_ABI) |
252b5132 RH |
2481 | { |
2482 | sec = subseg_new (".reginfo", (subsegT) 0); | |
2483 | ||
195325d2 TS |
2484 | bfd_set_section_flags (stdoutput, sec, flags); |
2485 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 2486 | |
252b5132 | 2487 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
252b5132 RH |
2488 | } |
2489 | else | |
2490 | { | |
2491 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
2492 | .reginfo section. */ | |
2493 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
2494 | bfd_set_section_flags (stdoutput, sec, flags); |
2495 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 | 2496 | |
252b5132 RH |
2497 | /* Set up the option header. */ |
2498 | { | |
2499 | Elf_Internal_Options opthdr; | |
2500 | char *f; | |
2501 | ||
2502 | opthdr.kind = ODK_REGINFO; | |
2503 | opthdr.size = (sizeof (Elf_External_Options) | |
2504 | + sizeof (Elf64_External_RegInfo)); | |
2505 | opthdr.section = 0; | |
2506 | opthdr.info = 0; | |
2507 | f = frag_more (sizeof (Elf_External_Options)); | |
2508 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
2509 | (Elf_External_Options *) f); | |
2510 | ||
2511 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
2512 | } | |
252b5132 RH |
2513 | } |
2514 | ||
2515 | if (ECOFF_DEBUGGING) | |
2516 | { | |
2517 | sec = subseg_new (".mdebug", (subsegT) 0); | |
2518 | (void) bfd_set_section_flags (stdoutput, sec, | |
2519 | SEC_HAS_CONTENTS | SEC_READONLY); | |
2520 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
2521 | } | |
f43abd2b | 2522 | else if (mips_flag_pdr) |
ecb4347a DJ |
2523 | { |
2524 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
2525 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
2526 | SEC_READONLY | SEC_RELOC | |
2527 | | SEC_DEBUGGING); | |
2528 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
2529 | } | |
252b5132 RH |
2530 | |
2531 | subseg_set (seg, subseg); | |
2532 | } | |
2533 | } | |
707bfff6 | 2534 | #endif /* OBJ_ELF */ |
252b5132 RH |
2535 | |
2536 | if (! ECOFF_DEBUGGING) | |
2537 | md_obj_begin (); | |
71400594 RS |
2538 | |
2539 | if (mips_fix_vr4120) | |
2540 | init_vr4120_conflicts (); | |
252b5132 RH |
2541 | } |
2542 | ||
2543 | void | |
17a2f251 | 2544 | md_mips_end (void) |
252b5132 | 2545 | { |
02b1ab82 | 2546 | mips_emit_delays (); |
252b5132 RH |
2547 | if (! ECOFF_DEBUGGING) |
2548 | md_obj_end (); | |
2549 | } | |
2550 | ||
2551 | void | |
17a2f251 | 2552 | md_assemble (char *str) |
252b5132 RH |
2553 | { |
2554 | struct mips_cl_insn insn; | |
f6688943 TS |
2555 | bfd_reloc_code_real_type unused_reloc[3] |
2556 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
2557 | |
2558 | imm_expr.X_op = O_absent; | |
5f74bc13 | 2559 | imm2_expr.X_op = O_absent; |
252b5132 | 2560 | offset_expr.X_op = O_absent; |
f6688943 TS |
2561 | imm_reloc[0] = BFD_RELOC_UNUSED; |
2562 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
2563 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
2564 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
2565 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
2566 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2567 | |
2568 | if (mips_opts.mips16) | |
2569 | mips16_ip (str, &insn); | |
2570 | else | |
2571 | { | |
2572 | mips_ip (str, &insn); | |
beae10d5 KH |
2573 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
2574 | str, insn.insn_opcode)); | |
252b5132 RH |
2575 | } |
2576 | ||
2577 | if (insn_error) | |
2578 | { | |
2579 | as_bad ("%s `%s'", insn_error, str); | |
2580 | return; | |
2581 | } | |
2582 | ||
2583 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
2584 | { | |
584892a6 | 2585 | macro_start (); |
252b5132 RH |
2586 | if (mips_opts.mips16) |
2587 | mips16_macro (&insn); | |
2588 | else | |
2589 | macro (&insn); | |
584892a6 | 2590 | macro_end (); |
252b5132 RH |
2591 | } |
2592 | else | |
2593 | { | |
2594 | if (imm_expr.X_op != O_absent) | |
df58fc94 | 2595 | append_insn (&insn, &imm_expr, imm_reloc, FALSE); |
252b5132 | 2596 | else if (offset_expr.X_op != O_absent) |
df58fc94 | 2597 | append_insn (&insn, &offset_expr, offset_reloc, FALSE); |
252b5132 | 2598 | else |
df58fc94 | 2599 | append_insn (&insn, NULL, unused_reloc, FALSE); |
252b5132 RH |
2600 | } |
2601 | } | |
2602 | ||
738e5348 RS |
2603 | /* Convenience functions for abstracting away the differences between |
2604 | MIPS16 and non-MIPS16 relocations. */ | |
2605 | ||
2606 | static inline bfd_boolean | |
2607 | mips16_reloc_p (bfd_reloc_code_real_type reloc) | |
2608 | { | |
2609 | switch (reloc) | |
2610 | { | |
2611 | case BFD_RELOC_MIPS16_JMP: | |
2612 | case BFD_RELOC_MIPS16_GPREL: | |
2613 | case BFD_RELOC_MIPS16_GOT16: | |
2614 | case BFD_RELOC_MIPS16_CALL16: | |
2615 | case BFD_RELOC_MIPS16_HI16_S: | |
2616 | case BFD_RELOC_MIPS16_HI16: | |
2617 | case BFD_RELOC_MIPS16_LO16: | |
2618 | return TRUE; | |
2619 | ||
2620 | default: | |
2621 | return FALSE; | |
2622 | } | |
2623 | } | |
2624 | ||
df58fc94 RS |
2625 | static inline bfd_boolean |
2626 | micromips_reloc_p (bfd_reloc_code_real_type reloc) | |
2627 | { | |
2628 | switch (reloc) | |
2629 | { | |
2630 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: | |
2631 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
2632 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
2633 | case BFD_RELOC_MICROMIPS_GPREL16: | |
2634 | case BFD_RELOC_MICROMIPS_JMP: | |
2635 | case BFD_RELOC_MICROMIPS_HI16: | |
2636 | case BFD_RELOC_MICROMIPS_HI16_S: | |
2637 | case BFD_RELOC_MICROMIPS_LO16: | |
2638 | case BFD_RELOC_MICROMIPS_LITERAL: | |
2639 | case BFD_RELOC_MICROMIPS_GOT16: | |
2640 | case BFD_RELOC_MICROMIPS_CALL16: | |
2641 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
2642 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
2643 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
2644 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
2645 | case BFD_RELOC_MICROMIPS_SUB: | |
2646 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
2647 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
2648 | case BFD_RELOC_MICROMIPS_GOT_DISP: | |
2649 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
2650 | case BFD_RELOC_MICROMIPS_HIGHER: | |
2651 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
2652 | case BFD_RELOC_MICROMIPS_JALR: | |
2653 | return TRUE; | |
2654 | ||
2655 | default: | |
2656 | return FALSE; | |
2657 | } | |
2658 | } | |
2659 | ||
2309ddf2 MR |
2660 | static inline bfd_boolean |
2661 | jmp_reloc_p (bfd_reloc_code_real_type reloc) | |
2662 | { | |
2663 | return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP; | |
2664 | } | |
2665 | ||
738e5348 RS |
2666 | static inline bfd_boolean |
2667 | got16_reloc_p (bfd_reloc_code_real_type reloc) | |
2668 | { | |
2309ddf2 | 2669 | return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16 |
df58fc94 | 2670 | || reloc == BFD_RELOC_MICROMIPS_GOT16); |
738e5348 RS |
2671 | } |
2672 | ||
2673 | static inline bfd_boolean | |
2674 | hi16_reloc_p (bfd_reloc_code_real_type reloc) | |
2675 | { | |
2309ddf2 | 2676 | return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S |
df58fc94 | 2677 | || reloc == BFD_RELOC_MICROMIPS_HI16_S); |
738e5348 RS |
2678 | } |
2679 | ||
2680 | static inline bfd_boolean | |
2681 | lo16_reloc_p (bfd_reloc_code_real_type reloc) | |
2682 | { | |
2309ddf2 | 2683 | return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16 |
df58fc94 RS |
2684 | || reloc == BFD_RELOC_MICROMIPS_LO16); |
2685 | } | |
2686 | ||
df58fc94 RS |
2687 | static inline bfd_boolean |
2688 | jalr_reloc_p (bfd_reloc_code_real_type reloc) | |
2689 | { | |
2309ddf2 | 2690 | return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR; |
738e5348 RS |
2691 | } |
2692 | ||
5919d012 | 2693 | /* Return true if the given relocation might need a matching %lo(). |
0a44bf69 RS |
2694 | This is only "might" because SVR4 R_MIPS_GOT16 relocations only |
2695 | need a matching %lo() when applied to local symbols. */ | |
5919d012 RS |
2696 | |
2697 | static inline bfd_boolean | |
17a2f251 | 2698 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 2699 | { |
3b91255e | 2700 | return (HAVE_IN_PLACE_ADDENDS |
738e5348 | 2701 | && (hi16_reloc_p (reloc) |
0a44bf69 RS |
2702 | /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo(); |
2703 | all GOT16 relocations evaluate to "G". */ | |
738e5348 RS |
2704 | || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC))); |
2705 | } | |
2706 | ||
2707 | /* Return the type of %lo() reloc needed by RELOC, given that | |
2708 | reloc_needs_lo_p. */ | |
2709 | ||
2710 | static inline bfd_reloc_code_real_type | |
2711 | matching_lo_reloc (bfd_reloc_code_real_type reloc) | |
2712 | { | |
df58fc94 RS |
2713 | return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 |
2714 | : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16 | |
2715 | : BFD_RELOC_LO16)); | |
5919d012 RS |
2716 | } |
2717 | ||
2718 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
2719 | relocation. */ | |
2720 | ||
2721 | static inline bfd_boolean | |
17a2f251 | 2722 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
2723 | { |
2724 | return (fixp->fx_next != NULL | |
738e5348 | 2725 | && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type) |
5919d012 RS |
2726 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
2727 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
2728 | } | |
2729 | ||
252b5132 RH |
2730 | /* This function returns true if modifying a register requires a |
2731 | delay. */ | |
2732 | ||
2733 | static int | |
17a2f251 | 2734 | reg_needs_delay (unsigned int reg) |
252b5132 RH |
2735 | { |
2736 | unsigned long prev_pinfo; | |
2737 | ||
47e39b9d | 2738 | prev_pinfo = history[0].insn_mo->pinfo; |
252b5132 | 2739 | if (! mips_opts.noreorder |
81912461 ILT |
2740 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
2741 | && ! gpr_interlocks) | |
2742 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
2743 | && ! cop_interlocks))) | |
252b5132 | 2744 | { |
81912461 ILT |
2745 | /* A load from a coprocessor or from memory. All load delays |
2746 | delay the use of general register rt for one instruction. */ | |
bdaaa2e1 | 2747 | /* Itbl support may require additional care here. */ |
252b5132 | 2748 | know (prev_pinfo & INSN_WRITE_GPR_T); |
df58fc94 | 2749 | if (reg == EXTRACT_OPERAND (mips_opts.micromips, RT, history[0])) |
252b5132 RH |
2750 | return 1; |
2751 | } | |
2752 | ||
2753 | return 0; | |
2754 | } | |
2755 | ||
404a8071 RS |
2756 | /* Move all labels in insn_labels to the current insertion point. */ |
2757 | ||
2758 | static void | |
2759 | mips_move_labels (void) | |
2760 | { | |
a8dbcb85 | 2761 | segment_info_type *si = seg_info (now_seg); |
404a8071 RS |
2762 | struct insn_label_list *l; |
2763 | valueT val; | |
2764 | ||
a8dbcb85 | 2765 | for (l = si->label_list; l != NULL; l = l->next) |
404a8071 | 2766 | { |
9c2799c2 | 2767 | gas_assert (S_GET_SEGMENT (l->label) == now_seg); |
404a8071 RS |
2768 | symbol_set_frag (l->label, frag_now); |
2769 | val = (valueT) frag_now_fix (); | |
df58fc94 RS |
2770 | /* MIPS16/microMIPS text labels are stored as odd. */ |
2771 | if (HAVE_CODE_COMPRESSION) | |
404a8071 RS |
2772 | ++val; |
2773 | S_SET_VALUE (l->label, val); | |
2774 | } | |
2775 | } | |
2776 | ||
5f0fe04b TS |
2777 | static bfd_boolean |
2778 | s_is_linkonce (symbolS *sym, segT from_seg) | |
2779 | { | |
2780 | bfd_boolean linkonce = FALSE; | |
2781 | segT symseg = S_GET_SEGMENT (sym); | |
2782 | ||
2783 | if (symseg != from_seg && !S_IS_LOCAL (sym)) | |
2784 | { | |
2785 | if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE)) | |
2786 | linkonce = TRUE; | |
2787 | #ifdef OBJ_ELF | |
2788 | /* The GNU toolchain uses an extension for ELF: a section | |
2789 | beginning with the magic string .gnu.linkonce is a | |
2790 | linkonce section. */ | |
2791 | if (strncmp (segment_name (symseg), ".gnu.linkonce", | |
2792 | sizeof ".gnu.linkonce" - 1) == 0) | |
2793 | linkonce = TRUE; | |
2794 | #endif | |
2795 | } | |
2796 | return linkonce; | |
2797 | } | |
2798 | ||
df58fc94 RS |
2799 | /* Mark instruction labels in MIPS16/microMIPS mode. This permits the |
2800 | linker to handle them specially, such as generating jalx instructions | |
2801 | when needed. We also make them odd for the duration of the assembly, | |
2802 | in order to generate the right sort of code. We will make them even | |
252b5132 RH |
2803 | in the adjust_symtab routine, while leaving them marked. This is |
2804 | convenient for the debugger and the disassembler. The linker knows | |
2805 | to make them odd again. */ | |
2806 | ||
2807 | static void | |
df58fc94 | 2808 | mips_compressed_mark_labels (void) |
252b5132 | 2809 | { |
a8dbcb85 TS |
2810 | segment_info_type *si = seg_info (now_seg); |
2811 | struct insn_label_list *l; | |
252b5132 | 2812 | |
df58fc94 | 2813 | gas_assert (HAVE_CODE_COMPRESSION); |
a8dbcb85 TS |
2814 | |
2815 | for (l = si->label_list; l != NULL; l = l->next) | |
2816 | { | |
2817 | symbolS *label = l->label; | |
2818 | ||
2819 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) | |
f43abd2b | 2820 | if (IS_ELF) |
df58fc94 RS |
2821 | { |
2822 | if (mips_opts.mips16) | |
2823 | S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label))); | |
2824 | else | |
2825 | S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label))); | |
2826 | } | |
252b5132 | 2827 | #endif |
5f0fe04b TS |
2828 | if ((S_GET_VALUE (label) & 1) == 0 |
2829 | /* Don't adjust the address if the label is global or weak, or | |
2830 | in a link-once section, since we'll be emitting symbol reloc | |
2831 | references to it which will be patched up by the linker, and | |
df58fc94 | 2832 | the final value of the symbol may or may not be MIPS16/microMIPS. */ |
5f0fe04b TS |
2833 | && ! S_IS_WEAK (label) |
2834 | && ! S_IS_EXTERNAL (label) | |
2835 | && ! s_is_linkonce (label, now_seg)) | |
a8dbcb85 | 2836 | S_SET_VALUE (label, S_GET_VALUE (label) | 1); |
252b5132 RH |
2837 | } |
2838 | } | |
2839 | ||
4d7206a2 RS |
2840 | /* End the current frag. Make it a variant frag and record the |
2841 | relaxation info. */ | |
2842 | ||
2843 | static void | |
2844 | relax_close_frag (void) | |
2845 | { | |
584892a6 | 2846 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 2847 | frag_var (rs_machine_dependent, 0, 0, |
584892a6 | 2848 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), |
4d7206a2 RS |
2849 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
2850 | ||
2851 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
2852 | mips_relax.first_fixup = 0; | |
2853 | } | |
2854 | ||
2855 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
2856 | See the comment above RELAX_ENCODE for more details. */ | |
2857 | ||
2858 | static void | |
2859 | relax_start (symbolS *symbol) | |
2860 | { | |
9c2799c2 | 2861 | gas_assert (mips_relax.sequence == 0); |
4d7206a2 RS |
2862 | mips_relax.sequence = 1; |
2863 | mips_relax.symbol = symbol; | |
2864 | } | |
2865 | ||
2866 | /* Start generating the second version of a relaxable sequence. | |
2867 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
2868 | |
2869 | static void | |
4d7206a2 RS |
2870 | relax_switch (void) |
2871 | { | |
9c2799c2 | 2872 | gas_assert (mips_relax.sequence == 1); |
4d7206a2 RS |
2873 | mips_relax.sequence = 2; |
2874 | } | |
2875 | ||
2876 | /* End the current relaxable sequence. */ | |
2877 | ||
2878 | static void | |
2879 | relax_end (void) | |
2880 | { | |
9c2799c2 | 2881 | gas_assert (mips_relax.sequence == 2); |
4d7206a2 RS |
2882 | relax_close_frag (); |
2883 | mips_relax.sequence = 0; | |
2884 | } | |
2885 | ||
11625dd8 RS |
2886 | /* Return true if IP is a delayed branch or jump. */ |
2887 | ||
2888 | static inline bfd_boolean | |
2889 | delayed_branch_p (const struct mips_cl_insn *ip) | |
2890 | { | |
2891 | return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY | |
2892 | | INSN_COND_BRANCH_DELAY | |
2893 | | INSN_COND_BRANCH_LIKELY)) != 0; | |
2894 | } | |
2895 | ||
2896 | /* Return true if IP is a compact branch or jump. */ | |
2897 | ||
2898 | static inline bfd_boolean | |
2899 | compact_branch_p (const struct mips_cl_insn *ip) | |
2900 | { | |
2901 | if (mips_opts.mips16) | |
2902 | return (ip->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH | |
2903 | | MIPS16_INSN_COND_BRANCH)) != 0; | |
2904 | else | |
2905 | return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH | |
2906 | | INSN2_COND_BRANCH)) != 0; | |
2907 | } | |
2908 | ||
2909 | /* Return true if IP is an unconditional branch or jump. */ | |
2910 | ||
2911 | static inline bfd_boolean | |
2912 | uncond_branch_p (const struct mips_cl_insn *ip) | |
2913 | { | |
2914 | return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0 | |
2915 | || (mips_opts.mips16 | |
2916 | ? (ip->insn_mo->pinfo & MIPS16_INSN_UNCOND_BRANCH) != 0 | |
2917 | : (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0)); | |
2918 | } | |
2919 | ||
2920 | /* Return true if IP is a branch-likely instruction. */ | |
2921 | ||
2922 | static inline bfd_boolean | |
2923 | branch_likely_p (const struct mips_cl_insn *ip) | |
2924 | { | |
2925 | return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0; | |
2926 | } | |
2927 | ||
14fe068b RS |
2928 | /* Return the type of nop that should be used to fill the delay slot |
2929 | of delayed branch IP. */ | |
2930 | ||
2931 | static struct mips_cl_insn * | |
2932 | get_delay_slot_nop (const struct mips_cl_insn *ip) | |
2933 | { | |
2934 | if (mips_opts.micromips | |
2935 | && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
2936 | return µmips_nop32_insn; | |
2937 | return NOP_INSN; | |
2938 | } | |
2939 | ||
2309ddf2 | 2940 | /* Return the mask of core registers that IP reads or writes. */ |
df58fc94 RS |
2941 | |
2942 | static unsigned int | |
2943 | gpr_mod_mask (const struct mips_cl_insn *ip) | |
2944 | { | |
2309ddf2 | 2945 | unsigned long pinfo2; |
df58fc94 RS |
2946 | unsigned int mask; |
2947 | ||
2948 | mask = 0; | |
df58fc94 RS |
2949 | pinfo2 = ip->insn_mo->pinfo2; |
2950 | if (mips_opts.micromips) | |
2951 | { | |
df58fc94 RS |
2952 | if (pinfo2 & INSN2_MOD_GPR_MD) |
2953 | mask |= 1 << micromips_to_32_reg_d_map[EXTRACT_OPERAND (1, MD, *ip)]; | |
df58fc94 RS |
2954 | if (pinfo2 & INSN2_MOD_GPR_MF) |
2955 | mask |= 1 << micromips_to_32_reg_f_map[EXTRACT_OPERAND (1, MF, *ip)]; | |
df58fc94 RS |
2956 | if (pinfo2 & INSN2_MOD_SP) |
2957 | mask |= 1 << SP; | |
2958 | } | |
2959 | return mask; | |
2960 | } | |
2961 | ||
4c260379 RS |
2962 | /* Return the mask of core registers that IP reads. */ |
2963 | ||
2964 | static unsigned int | |
2965 | gpr_read_mask (const struct mips_cl_insn *ip) | |
2966 | { | |
2967 | unsigned long pinfo, pinfo2; | |
2968 | unsigned int mask; | |
2969 | ||
df58fc94 | 2970 | mask = gpr_mod_mask (ip); |
4c260379 RS |
2971 | pinfo = ip->insn_mo->pinfo; |
2972 | pinfo2 = ip->insn_mo->pinfo2; | |
2973 | if (mips_opts.mips16) | |
2974 | { | |
2975 | if (pinfo & MIPS16_INSN_READ_X) | |
2976 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)]; | |
2977 | if (pinfo & MIPS16_INSN_READ_Y) | |
2978 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)]; | |
2979 | if (pinfo & MIPS16_INSN_READ_T) | |
2980 | mask |= 1 << TREG; | |
2981 | if (pinfo & MIPS16_INSN_READ_SP) | |
2982 | mask |= 1 << SP; | |
2983 | if (pinfo & MIPS16_INSN_READ_31) | |
2984 | mask |= 1 << RA; | |
2985 | if (pinfo & MIPS16_INSN_READ_Z) | |
2986 | mask |= 1 << (mips16_to_32_reg_map | |
2987 | [MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]); | |
2988 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
2989 | mask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip); | |
2990 | } | |
2991 | else | |
2992 | { | |
2993 | if (pinfo2 & INSN2_READ_GPR_D) | |
2309ddf2 | 2994 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); |
4c260379 | 2995 | if (pinfo & INSN_READ_GPR_T) |
2309ddf2 | 2996 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); |
4c260379 | 2997 | if (pinfo & INSN_READ_GPR_S) |
2309ddf2 MR |
2998 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); |
2999 | if (pinfo2 & INSN2_READ_GP) | |
3000 | mask |= 1 << GP; | |
3001 | if (pinfo2 & INSN2_READ_GPR_31) | |
3002 | mask |= 1 << RA; | |
4c260379 | 3003 | if (pinfo2 & INSN2_READ_GPR_Z) |
2309ddf2 | 3004 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip); |
4c260379 | 3005 | } |
2b0c8b40 MR |
3006 | if (mips_opts.micromips) |
3007 | { | |
3008 | if (pinfo2 & INSN2_READ_GPR_MC) | |
3009 | mask |= 1 << micromips_to_32_reg_c_map[EXTRACT_OPERAND (1, MC, *ip)]; | |
3010 | if (pinfo2 & INSN2_READ_GPR_ME) | |
3011 | mask |= 1 << micromips_to_32_reg_e_map[EXTRACT_OPERAND (1, ME, *ip)]; | |
3012 | if (pinfo2 & INSN2_READ_GPR_MG) | |
3013 | mask |= 1 << micromips_to_32_reg_g_map[EXTRACT_OPERAND (1, MG, *ip)]; | |
3014 | if (pinfo2 & INSN2_READ_GPR_MJ) | |
3015 | mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip); | |
3016 | if (pinfo2 & INSN2_READ_GPR_MMN) | |
3017 | { | |
3018 | mask |= 1 << micromips_to_32_reg_m_map[EXTRACT_OPERAND (1, MM, *ip)]; | |
3019 | mask |= 1 << micromips_to_32_reg_n_map[EXTRACT_OPERAND (1, MN, *ip)]; | |
3020 | } | |
3021 | if (pinfo2 & INSN2_READ_GPR_MP) | |
3022 | mask |= 1 << EXTRACT_OPERAND (1, MP, *ip); | |
3023 | if (pinfo2 & INSN2_READ_GPR_MQ) | |
3024 | mask |= 1 << micromips_to_32_reg_q_map[EXTRACT_OPERAND (1, MQ, *ip)]; | |
3025 | } | |
fe35f09f RS |
3026 | /* Don't include register 0. */ |
3027 | return mask & ~1; | |
4c260379 RS |
3028 | } |
3029 | ||
3030 | /* Return the mask of core registers that IP writes. */ | |
3031 | ||
3032 | static unsigned int | |
3033 | gpr_write_mask (const struct mips_cl_insn *ip) | |
3034 | { | |
3035 | unsigned long pinfo, pinfo2; | |
3036 | unsigned int mask; | |
3037 | ||
df58fc94 | 3038 | mask = gpr_mod_mask (ip); |
4c260379 RS |
3039 | pinfo = ip->insn_mo->pinfo; |
3040 | pinfo2 = ip->insn_mo->pinfo2; | |
3041 | if (mips_opts.mips16) | |
3042 | { | |
3043 | if (pinfo & MIPS16_INSN_WRITE_X) | |
3044 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)]; | |
3045 | if (pinfo & MIPS16_INSN_WRITE_Y) | |
3046 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)]; | |
3047 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
3048 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RZ, *ip)]; | |
3049 | if (pinfo & MIPS16_INSN_WRITE_T) | |
3050 | mask |= 1 << TREG; | |
3051 | if (pinfo & MIPS16_INSN_WRITE_SP) | |
3052 | mask |= 1 << SP; | |
3053 | if (pinfo & MIPS16_INSN_WRITE_31) | |
3054 | mask |= 1 << RA; | |
3055 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
3056 | mask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
3057 | } | |
3058 | else | |
3059 | { | |
3060 | if (pinfo & INSN_WRITE_GPR_D) | |
df58fc94 | 3061 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); |
4c260379 | 3062 | if (pinfo & INSN_WRITE_GPR_T) |
df58fc94 | 3063 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); |
2b0c8b40 | 3064 | if (pinfo & INSN_WRITE_GPR_S) |
2309ddf2 | 3065 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); |
4c260379 RS |
3066 | if (pinfo & INSN_WRITE_GPR_31) |
3067 | mask |= 1 << RA; | |
3068 | if (pinfo2 & INSN2_WRITE_GPR_Z) | |
df58fc94 | 3069 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip); |
4c260379 | 3070 | } |
2b0c8b40 MR |
3071 | if (mips_opts.micromips) |
3072 | { | |
3073 | if (pinfo2 & INSN2_WRITE_GPR_MB) | |
3074 | mask |= 1 << micromips_to_32_reg_b_map[EXTRACT_OPERAND (1, MB, *ip)]; | |
3075 | if (pinfo2 & INSN2_WRITE_GPR_MHI) | |
3076 | { | |
3077 | mask |= 1 << micromips_to_32_reg_h_map[EXTRACT_OPERAND (1, MH, *ip)]; | |
3078 | mask |= 1 << micromips_to_32_reg_i_map[EXTRACT_OPERAND (1, MI, *ip)]; | |
3079 | } | |
3080 | if (pinfo2 & INSN2_WRITE_GPR_MJ) | |
3081 | mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip); | |
3082 | if (pinfo2 & INSN2_WRITE_GPR_MP) | |
3083 | mask |= 1 << EXTRACT_OPERAND (1, MP, *ip); | |
3084 | } | |
fe35f09f RS |
3085 | /* Don't include register 0. */ |
3086 | return mask & ~1; | |
4c260379 RS |
3087 | } |
3088 | ||
3089 | /* Return the mask of floating-point registers that IP reads. */ | |
3090 | ||
3091 | static unsigned int | |
3092 | fpr_read_mask (const struct mips_cl_insn *ip) | |
3093 | { | |
3094 | unsigned long pinfo, pinfo2; | |
3095 | unsigned int mask; | |
3096 | ||
3097 | mask = 0; | |
3098 | pinfo = ip->insn_mo->pinfo; | |
3099 | pinfo2 = ip->insn_mo->pinfo2; | |
2309ddf2 | 3100 | if (!mips_opts.mips16) |
df58fc94 RS |
3101 | { |
3102 | if (pinfo2 & INSN2_READ_FPR_D) | |
2309ddf2 | 3103 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip); |
4c260379 | 3104 | if (pinfo & INSN_READ_FPR_S) |
df58fc94 | 3105 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip); |
4c260379 | 3106 | if (pinfo & INSN_READ_FPR_T) |
df58fc94 | 3107 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip); |
4c260379 | 3108 | if (pinfo & INSN_READ_FPR_R) |
df58fc94 | 3109 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FR, *ip); |
4c260379 | 3110 | if (pinfo2 & INSN2_READ_FPR_Z) |
df58fc94 | 3111 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip); |
4c260379 RS |
3112 | } |
3113 | /* Conservatively treat all operands to an FP_D instruction are doubles. | |
3114 | (This is overly pessimistic for things like cvt.d.s.) */ | |
3115 | if (HAVE_32BIT_FPRS && (pinfo & FP_D)) | |
3116 | mask |= mask << 1; | |
3117 | return mask; | |
3118 | } | |
3119 | ||
3120 | /* Return the mask of floating-point registers that IP writes. */ | |
3121 | ||
3122 | static unsigned int | |
3123 | fpr_write_mask (const struct mips_cl_insn *ip) | |
3124 | { | |
3125 | unsigned long pinfo, pinfo2; | |
3126 | unsigned int mask; | |
3127 | ||
3128 | mask = 0; | |
3129 | pinfo = ip->insn_mo->pinfo; | |
3130 | pinfo2 = ip->insn_mo->pinfo2; | |
2309ddf2 | 3131 | if (!mips_opts.mips16) |
4c260379 RS |
3132 | { |
3133 | if (pinfo & INSN_WRITE_FPR_D) | |
df58fc94 | 3134 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip); |
4c260379 | 3135 | if (pinfo & INSN_WRITE_FPR_S) |
df58fc94 | 3136 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip); |
4c260379 | 3137 | if (pinfo & INSN_WRITE_FPR_T) |
df58fc94 | 3138 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip); |
4c260379 | 3139 | if (pinfo2 & INSN2_WRITE_FPR_Z) |
df58fc94 | 3140 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip); |
4c260379 RS |
3141 | } |
3142 | /* Conservatively treat all operands to an FP_D instruction are doubles. | |
3143 | (This is overly pessimistic for things like cvt.s.d.) */ | |
3144 | if (HAVE_32BIT_FPRS && (pinfo & FP_D)) | |
3145 | mask |= mask << 1; | |
3146 | return mask; | |
3147 | } | |
3148 | ||
71400594 RS |
3149 | /* Classify an instruction according to the FIX_VR4120_* enumeration. |
3150 | Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected | |
3151 | by VR4120 errata. */ | |
4d7206a2 | 3152 | |
71400594 RS |
3153 | static unsigned int |
3154 | classify_vr4120_insn (const char *name) | |
252b5132 | 3155 | { |
71400594 RS |
3156 | if (strncmp (name, "macc", 4) == 0) |
3157 | return FIX_VR4120_MACC; | |
3158 | if (strncmp (name, "dmacc", 5) == 0) | |
3159 | return FIX_VR4120_DMACC; | |
3160 | if (strncmp (name, "mult", 4) == 0) | |
3161 | return FIX_VR4120_MULT; | |
3162 | if (strncmp (name, "dmult", 5) == 0) | |
3163 | return FIX_VR4120_DMULT; | |
3164 | if (strstr (name, "div")) | |
3165 | return FIX_VR4120_DIV; | |
3166 | if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) | |
3167 | return FIX_VR4120_MTHILO; | |
3168 | return NUM_FIX_VR4120_CLASSES; | |
3169 | } | |
252b5132 | 3170 | |
ff239038 CM |
3171 | #define INSN_ERET 0x42000018 |
3172 | #define INSN_DERET 0x4200001f | |
3173 | ||
71400594 RS |
3174 | /* Return the number of instructions that must separate INSN1 and INSN2, |
3175 | where INSN1 is the earlier instruction. Return the worst-case value | |
3176 | for any INSN2 if INSN2 is null. */ | |
252b5132 | 3177 | |
71400594 RS |
3178 | static unsigned int |
3179 | insns_between (const struct mips_cl_insn *insn1, | |
3180 | const struct mips_cl_insn *insn2) | |
3181 | { | |
3182 | unsigned long pinfo1, pinfo2; | |
4c260379 | 3183 | unsigned int mask; |
71400594 RS |
3184 | |
3185 | /* This function needs to know which pinfo flags are set for INSN2 | |
3186 | and which registers INSN2 uses. The former is stored in PINFO2 and | |
4c260379 RS |
3187 | the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2 |
3188 | will have every flag set and INSN2_USES_GPR will always return true. */ | |
71400594 RS |
3189 | pinfo1 = insn1->insn_mo->pinfo; |
3190 | pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; | |
252b5132 | 3191 | |
4c260379 RS |
3192 | #define INSN2_USES_GPR(REG) \ |
3193 | (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0) | |
71400594 RS |
3194 | |
3195 | /* For most targets, write-after-read dependencies on the HI and LO | |
3196 | registers must be separated by at least two instructions. */ | |
3197 | if (!hilo_interlocks) | |
252b5132 | 3198 | { |
71400594 RS |
3199 | if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) |
3200 | return 2; | |
3201 | if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) | |
3202 | return 2; | |
3203 | } | |
3204 | ||
3205 | /* If we're working around r7000 errata, there must be two instructions | |
3206 | between an mfhi or mflo and any instruction that uses the result. */ | |
3207 | if (mips_7000_hilo_fix | |
df58fc94 | 3208 | && !mips_opts.micromips |
71400594 | 3209 | && MF_HILO_INSN (pinfo1) |
df58fc94 | 3210 | && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD, *insn1))) |
71400594 RS |
3211 | return 2; |
3212 | ||
ff239038 CM |
3213 | /* If we're working around 24K errata, one instruction is required |
3214 | if an ERET or DERET is followed by a branch instruction. */ | |
df58fc94 | 3215 | if (mips_fix_24k && !mips_opts.micromips) |
ff239038 CM |
3216 | { |
3217 | if (insn1->insn_opcode == INSN_ERET | |
3218 | || insn1->insn_opcode == INSN_DERET) | |
3219 | { | |
3220 | if (insn2 == NULL | |
3221 | || insn2->insn_opcode == INSN_ERET | |
3222 | || insn2->insn_opcode == INSN_DERET | |
11625dd8 | 3223 | || delayed_branch_p (insn2)) |
ff239038 CM |
3224 | return 1; |
3225 | } | |
3226 | } | |
3227 | ||
71400594 RS |
3228 | /* If working around VR4120 errata, check for combinations that need |
3229 | a single intervening instruction. */ | |
df58fc94 | 3230 | if (mips_fix_vr4120 && !mips_opts.micromips) |
71400594 RS |
3231 | { |
3232 | unsigned int class1, class2; | |
252b5132 | 3233 | |
71400594 RS |
3234 | class1 = classify_vr4120_insn (insn1->insn_mo->name); |
3235 | if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) | |
252b5132 | 3236 | { |
71400594 RS |
3237 | if (insn2 == NULL) |
3238 | return 1; | |
3239 | class2 = classify_vr4120_insn (insn2->insn_mo->name); | |
3240 | if (vr4120_conflicts[class1] & (1 << class2)) | |
3241 | return 1; | |
252b5132 | 3242 | } |
71400594 RS |
3243 | } |
3244 | ||
df58fc94 | 3245 | if (!HAVE_CODE_COMPRESSION) |
71400594 RS |
3246 | { |
3247 | /* Check for GPR or coprocessor load delays. All such delays | |
3248 | are on the RT register. */ | |
3249 | /* Itbl support may require additional care here. */ | |
3250 | if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY)) | |
3251 | || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY))) | |
252b5132 | 3252 | { |
71400594 | 3253 | know (pinfo1 & INSN_WRITE_GPR_T); |
df58fc94 | 3254 | if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT, *insn1))) |
71400594 RS |
3255 | return 1; |
3256 | } | |
3257 | ||
3258 | /* Check for generic coprocessor hazards. | |
3259 | ||
3260 | This case is not handled very well. There is no special | |
3261 | knowledge of CP0 handling, and the coprocessors other than | |
3262 | the floating point unit are not distinguished at all. */ | |
3263 | /* Itbl support may require additional care here. FIXME! | |
3264 | Need to modify this to include knowledge about | |
3265 | user specified delays! */ | |
3266 | else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY)) | |
3267 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) | |
3268 | { | |
3269 | /* Handle cases where INSN1 writes to a known general coprocessor | |
3270 | register. There must be a one instruction delay before INSN2 | |
3271 | if INSN2 reads that register, otherwise no delay is needed. */ | |
4c260379 RS |
3272 | mask = fpr_write_mask (insn1); |
3273 | if (mask != 0) | |
252b5132 | 3274 | { |
4c260379 | 3275 | if (!insn2 || (mask & fpr_read_mask (insn2)) != 0) |
71400594 | 3276 | return 1; |
252b5132 RH |
3277 | } |
3278 | else | |
3279 | { | |
71400594 RS |
3280 | /* Read-after-write dependencies on the control registers |
3281 | require a two-instruction gap. */ | |
3282 | if ((pinfo1 & INSN_WRITE_COND_CODE) | |
3283 | && (pinfo2 & INSN_READ_COND_CODE)) | |
3284 | return 2; | |
3285 | ||
3286 | /* We don't know exactly what INSN1 does. If INSN2 is | |
3287 | also a coprocessor instruction, assume there must be | |
3288 | a one instruction gap. */ | |
3289 | if (pinfo2 & INSN_COP) | |
3290 | return 1; | |
252b5132 RH |
3291 | } |
3292 | } | |
6b76fefe | 3293 | |
71400594 RS |
3294 | /* Check for read-after-write dependencies on the coprocessor |
3295 | control registers in cases where INSN1 does not need a general | |
3296 | coprocessor delay. This means that INSN1 is a floating point | |
3297 | comparison instruction. */ | |
3298 | /* Itbl support may require additional care here. */ | |
3299 | else if (!cop_interlocks | |
3300 | && (pinfo1 & INSN_WRITE_COND_CODE) | |
3301 | && (pinfo2 & INSN_READ_COND_CODE)) | |
3302 | return 1; | |
3303 | } | |
6b76fefe | 3304 | |
4c260379 | 3305 | #undef INSN2_USES_GPR |
6b76fefe | 3306 | |
71400594 RS |
3307 | return 0; |
3308 | } | |
6b76fefe | 3309 | |
7d8e00cf RS |
3310 | /* Return the number of nops that would be needed to work around the |
3311 | VR4130 mflo/mfhi errata if instruction INSN immediately followed | |
932d1a1b RS |
3312 | the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards |
3313 | that are contained within the first IGNORE instructions of HIST. */ | |
7d8e00cf RS |
3314 | |
3315 | static int | |
932d1a1b | 3316 | nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist, |
7d8e00cf RS |
3317 | const struct mips_cl_insn *insn) |
3318 | { | |
4c260379 RS |
3319 | int i, j; |
3320 | unsigned int mask; | |
7d8e00cf RS |
3321 | |
3322 | /* Check if the instruction writes to HI or LO. MTHI and MTLO | |
3323 | are not affected by the errata. */ | |
3324 | if (insn != 0 | |
3325 | && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 | |
3326 | || strcmp (insn->insn_mo->name, "mtlo") == 0 | |
3327 | || strcmp (insn->insn_mo->name, "mthi") == 0)) | |
3328 | return 0; | |
3329 | ||
3330 | /* Search for the first MFLO or MFHI. */ | |
3331 | for (i = 0; i < MAX_VR4130_NOPS; i++) | |
91d6fa6a | 3332 | if (MF_HILO_INSN (hist[i].insn_mo->pinfo)) |
7d8e00cf RS |
3333 | { |
3334 | /* Extract the destination register. */ | |
4c260379 | 3335 | mask = gpr_write_mask (&hist[i]); |
7d8e00cf RS |
3336 | |
3337 | /* No nops are needed if INSN reads that register. */ | |
4c260379 | 3338 | if (insn != NULL && (gpr_read_mask (insn) & mask) != 0) |
7d8e00cf RS |
3339 | return 0; |
3340 | ||
3341 | /* ...or if any of the intervening instructions do. */ | |
3342 | for (j = 0; j < i; j++) | |
4c260379 | 3343 | if (gpr_read_mask (&hist[j]) & mask) |
7d8e00cf RS |
3344 | return 0; |
3345 | ||
932d1a1b RS |
3346 | if (i >= ignore) |
3347 | return MAX_VR4130_NOPS - i; | |
7d8e00cf RS |
3348 | } |
3349 | return 0; | |
3350 | } | |
3351 | ||
15be625d CM |
3352 | #define BASE_REG_EQ(INSN1, INSN2) \ |
3353 | ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \ | |
3354 | == (((INSN2) >> OP_SH_RS) & OP_MASK_RS)) | |
3355 | ||
3356 | /* Return the minimum alignment for this store instruction. */ | |
3357 | ||
3358 | static int | |
3359 | fix_24k_align_to (const struct mips_opcode *mo) | |
3360 | { | |
3361 | if (strcmp (mo->name, "sh") == 0) | |
3362 | return 2; | |
3363 | ||
3364 | if (strcmp (mo->name, "swc1") == 0 | |
3365 | || strcmp (mo->name, "swc2") == 0 | |
3366 | || strcmp (mo->name, "sw") == 0 | |
3367 | || strcmp (mo->name, "sc") == 0 | |
3368 | || strcmp (mo->name, "s.s") == 0) | |
3369 | return 4; | |
3370 | ||
3371 | if (strcmp (mo->name, "sdc1") == 0 | |
3372 | || strcmp (mo->name, "sdc2") == 0 | |
3373 | || strcmp (mo->name, "s.d") == 0) | |
3374 | return 8; | |
3375 | ||
3376 | /* sb, swl, swr */ | |
3377 | return 1; | |
3378 | } | |
3379 | ||
3380 | struct fix_24k_store_info | |
3381 | { | |
3382 | /* Immediate offset, if any, for this store instruction. */ | |
3383 | short off; | |
3384 | /* Alignment required by this store instruction. */ | |
3385 | int align_to; | |
3386 | /* True for register offsets. */ | |
3387 | int register_offset; | |
3388 | }; | |
3389 | ||
3390 | /* Comparison function used by qsort. */ | |
3391 | ||
3392 | static int | |
3393 | fix_24k_sort (const void *a, const void *b) | |
3394 | { | |
3395 | const struct fix_24k_store_info *pos1 = a; | |
3396 | const struct fix_24k_store_info *pos2 = b; | |
3397 | ||
3398 | return (pos1->off - pos2->off); | |
3399 | } | |
3400 | ||
3401 | /* INSN is a store instruction. Try to record the store information | |
3402 | in STINFO. Return false if the information isn't known. */ | |
3403 | ||
3404 | static bfd_boolean | |
3405 | fix_24k_record_store_info (struct fix_24k_store_info *stinfo, | |
ab9794cf | 3406 | const struct mips_cl_insn *insn) |
15be625d CM |
3407 | { |
3408 | /* The instruction must have a known offset. */ | |
3409 | if (!insn->complete_p || !strstr (insn->insn_mo->args, "o(")) | |
3410 | return FALSE; | |
3411 | ||
3412 | stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE; | |
3413 | stinfo->align_to = fix_24k_align_to (insn->insn_mo); | |
3414 | return TRUE; | |
3415 | } | |
3416 | ||
932d1a1b RS |
3417 | /* Return the number of nops that would be needed to work around the 24k |
3418 | "lost data on stores during refill" errata if instruction INSN | |
3419 | immediately followed the 2 instructions described by HIST. | |
3420 | Ignore hazards that are contained within the first IGNORE | |
3421 | instructions of HIST. | |
3422 | ||
3423 | Problem: The FSB (fetch store buffer) acts as an intermediate buffer | |
3424 | for the data cache refills and store data. The following describes | |
3425 | the scenario where the store data could be lost. | |
3426 | ||
3427 | * A data cache miss, due to either a load or a store, causing fill | |
3428 | data to be supplied by the memory subsystem | |
3429 | * The first three doublewords of fill data are returned and written | |
3430 | into the cache | |
3431 | * A sequence of four stores occurs in consecutive cycles around the | |
3432 | final doubleword of the fill: | |
3433 | * Store A | |
3434 | * Store B | |
3435 | * Store C | |
3436 | * Zero, One or more instructions | |
3437 | * Store D | |
3438 | ||
3439 | The four stores A-D must be to different doublewords of the line that | |
3440 | is being filled. The fourth instruction in the sequence above permits | |
3441 | the fill of the final doubleword to be transferred from the FSB into | |
3442 | the cache. In the sequence above, the stores may be either integer | |
3443 | (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2, | |
3444 | swxc1, sdxc1, suxc1) stores, as long as the four stores are to | |
3445 | different doublewords on the line. If the floating point unit is | |
3446 | running in 1:2 mode, it is not possible to create the sequence above | |
3447 | using only floating point store instructions. | |
15be625d CM |
3448 | |
3449 | In this case, the cache line being filled is incorrectly marked | |
3450 | invalid, thereby losing the data from any store to the line that | |
3451 | occurs between the original miss and the completion of the five | |
3452 | cycle sequence shown above. | |
3453 | ||
932d1a1b | 3454 | The workarounds are: |
15be625d | 3455 | |
932d1a1b RS |
3456 | * Run the data cache in write-through mode. |
3457 | * Insert a non-store instruction between | |
3458 | Store A and Store B or Store B and Store C. */ | |
15be625d CM |
3459 | |
3460 | static int | |
932d1a1b | 3461 | nops_for_24k (int ignore, const struct mips_cl_insn *hist, |
15be625d CM |
3462 | const struct mips_cl_insn *insn) |
3463 | { | |
3464 | struct fix_24k_store_info pos[3]; | |
3465 | int align, i, base_offset; | |
3466 | ||
932d1a1b RS |
3467 | if (ignore >= 2) |
3468 | return 0; | |
3469 | ||
ab9794cf RS |
3470 | /* If the previous instruction wasn't a store, there's nothing to |
3471 | worry about. */ | |
15be625d CM |
3472 | if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) |
3473 | return 0; | |
3474 | ||
ab9794cf RS |
3475 | /* If the instructions after the previous one are unknown, we have |
3476 | to assume the worst. */ | |
3477 | if (!insn) | |
15be625d CM |
3478 | return 1; |
3479 | ||
ab9794cf RS |
3480 | /* Check whether we are dealing with three consecutive stores. */ |
3481 | if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0 | |
3482 | || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) | |
15be625d CM |
3483 | return 0; |
3484 | ||
3485 | /* If we don't know the relationship between the store addresses, | |
3486 | assume the worst. */ | |
ab9794cf | 3487 | if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode) |
15be625d CM |
3488 | || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode)) |
3489 | return 1; | |
3490 | ||
3491 | if (!fix_24k_record_store_info (&pos[0], insn) | |
3492 | || !fix_24k_record_store_info (&pos[1], &hist[0]) | |
3493 | || !fix_24k_record_store_info (&pos[2], &hist[1])) | |
3494 | return 1; | |
3495 | ||
3496 | qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort); | |
3497 | ||
3498 | /* Pick a value of ALIGN and X such that all offsets are adjusted by | |
3499 | X bytes and such that the base register + X is known to be aligned | |
3500 | to align bytes. */ | |
3501 | ||
3502 | if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP) | |
3503 | align = 8; | |
3504 | else | |
3505 | { | |
3506 | align = pos[0].align_to; | |
3507 | base_offset = pos[0].off; | |
3508 | for (i = 1; i < 3; i++) | |
3509 | if (align < pos[i].align_to) | |
3510 | { | |
3511 | align = pos[i].align_to; | |
3512 | base_offset = pos[i].off; | |
3513 | } | |
3514 | for (i = 0; i < 3; i++) | |
3515 | pos[i].off -= base_offset; | |
3516 | } | |
3517 | ||
3518 | pos[0].off &= ~align + 1; | |
3519 | pos[1].off &= ~align + 1; | |
3520 | pos[2].off &= ~align + 1; | |
3521 | ||
3522 | /* If any two stores write to the same chunk, they also write to the | |
3523 | same doubleword. The offsets are still sorted at this point. */ | |
3524 | if (pos[0].off == pos[1].off || pos[1].off == pos[2].off) | |
3525 | return 0; | |
3526 | ||
3527 | /* A range of at least 9 bytes is needed for the stores to be in | |
3528 | non-overlapping doublewords. */ | |
3529 | if (pos[2].off - pos[0].off <= 8) | |
3530 | return 0; | |
3531 | ||
3532 | if (pos[2].off - pos[1].off >= 24 | |
3533 | || pos[1].off - pos[0].off >= 24 | |
3534 | || pos[2].off - pos[0].off >= 32) | |
3535 | return 0; | |
3536 | ||
3537 | return 1; | |
3538 | } | |
3539 | ||
71400594 | 3540 | /* Return the number of nops that would be needed if instruction INSN |
91d6fa6a | 3541 | immediately followed the MAX_NOPS instructions given by HIST, |
932d1a1b RS |
3542 | where HIST[0] is the most recent instruction. Ignore hazards |
3543 | between INSN and the first IGNORE instructions in HIST. | |
3544 | ||
3545 | If INSN is null, return the worse-case number of nops for any | |
3546 | instruction. */ | |
bdaaa2e1 | 3547 | |
71400594 | 3548 | static int |
932d1a1b | 3549 | nops_for_insn (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
3550 | const struct mips_cl_insn *insn) |
3551 | { | |
3552 | int i, nops, tmp_nops; | |
bdaaa2e1 | 3553 | |
71400594 | 3554 | nops = 0; |
932d1a1b | 3555 | for (i = ignore; i < MAX_DELAY_NOPS; i++) |
65b02341 | 3556 | { |
91d6fa6a | 3557 | tmp_nops = insns_between (hist + i, insn) - i; |
65b02341 RS |
3558 | if (tmp_nops > nops) |
3559 | nops = tmp_nops; | |
3560 | } | |
7d8e00cf | 3561 | |
df58fc94 | 3562 | if (mips_fix_vr4130 && !mips_opts.micromips) |
7d8e00cf | 3563 | { |
932d1a1b | 3564 | tmp_nops = nops_for_vr4130 (ignore, hist, insn); |
7d8e00cf RS |
3565 | if (tmp_nops > nops) |
3566 | nops = tmp_nops; | |
3567 | } | |
3568 | ||
df58fc94 | 3569 | if (mips_fix_24k && !mips_opts.micromips) |
15be625d | 3570 | { |
932d1a1b | 3571 | tmp_nops = nops_for_24k (ignore, hist, insn); |
15be625d CM |
3572 | if (tmp_nops > nops) |
3573 | nops = tmp_nops; | |
3574 | } | |
3575 | ||
71400594 RS |
3576 | return nops; |
3577 | } | |
252b5132 | 3578 | |
71400594 | 3579 | /* The variable arguments provide NUM_INSNS extra instructions that |
91d6fa6a | 3580 | might be added to HIST. Return the largest number of nops that |
932d1a1b RS |
3581 | would be needed after the extended sequence, ignoring hazards |
3582 | in the first IGNORE instructions. */ | |
252b5132 | 3583 | |
71400594 | 3584 | static int |
932d1a1b RS |
3585 | nops_for_sequence (int num_insns, int ignore, |
3586 | const struct mips_cl_insn *hist, ...) | |
71400594 RS |
3587 | { |
3588 | va_list args; | |
3589 | struct mips_cl_insn buffer[MAX_NOPS]; | |
3590 | struct mips_cl_insn *cursor; | |
3591 | int nops; | |
3592 | ||
91d6fa6a | 3593 | va_start (args, hist); |
71400594 | 3594 | cursor = buffer + num_insns; |
91d6fa6a | 3595 | memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor)); |
71400594 RS |
3596 | while (cursor > buffer) |
3597 | *--cursor = *va_arg (args, const struct mips_cl_insn *); | |
3598 | ||
932d1a1b | 3599 | nops = nops_for_insn (ignore, buffer, NULL); |
71400594 RS |
3600 | va_end (args); |
3601 | return nops; | |
3602 | } | |
252b5132 | 3603 | |
71400594 RS |
3604 | /* Like nops_for_insn, but if INSN is a branch, take into account the |
3605 | worst-case delay for the branch target. */ | |
252b5132 | 3606 | |
71400594 | 3607 | static int |
932d1a1b | 3608 | nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
3609 | const struct mips_cl_insn *insn) |
3610 | { | |
3611 | int nops, tmp_nops; | |
60b63b72 | 3612 | |
932d1a1b | 3613 | nops = nops_for_insn (ignore, hist, insn); |
11625dd8 | 3614 | if (delayed_branch_p (insn)) |
71400594 | 3615 | { |
932d1a1b | 3616 | tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0, |
14fe068b | 3617 | hist, insn, get_delay_slot_nop (insn)); |
71400594 RS |
3618 | if (tmp_nops > nops) |
3619 | nops = tmp_nops; | |
3620 | } | |
11625dd8 | 3621 | else if (compact_branch_p (insn)) |
71400594 | 3622 | { |
932d1a1b | 3623 | tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn); |
71400594 RS |
3624 | if (tmp_nops > nops) |
3625 | nops = tmp_nops; | |
3626 | } | |
3627 | return nops; | |
3628 | } | |
3629 | ||
c67a084a NC |
3630 | /* Fix NOP issue: Replace nops by "or at,at,zero". */ |
3631 | ||
3632 | static void | |
3633 | fix_loongson2f_nop (struct mips_cl_insn * ip) | |
3634 | { | |
df58fc94 | 3635 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
3636 | if (strcmp (ip->insn_mo->name, "nop") == 0) |
3637 | ip->insn_opcode = LOONGSON2F_NOP_INSN; | |
3638 | } | |
3639 | ||
3640 | /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region | |
3641 | jr target pc &= 'hffff_ffff_cfff_ffff. */ | |
3642 | ||
3643 | static void | |
3644 | fix_loongson2f_jump (struct mips_cl_insn * ip) | |
3645 | { | |
df58fc94 | 3646 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
3647 | if (strcmp (ip->insn_mo->name, "j") == 0 |
3648 | || strcmp (ip->insn_mo->name, "jr") == 0 | |
3649 | || strcmp (ip->insn_mo->name, "jalr") == 0) | |
3650 | { | |
3651 | int sreg; | |
3652 | expressionS ep; | |
3653 | ||
3654 | if (! mips_opts.at) | |
3655 | return; | |
3656 | ||
df58fc94 | 3657 | sreg = EXTRACT_OPERAND (0, RS, *ip); |
c67a084a NC |
3658 | if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG) |
3659 | return; | |
3660 | ||
3661 | ep.X_op = O_constant; | |
3662 | ep.X_add_number = 0xcfff0000; | |
3663 | macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16); | |
3664 | ep.X_add_number = 0xffff; | |
3665 | macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16); | |
3666 | macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG); | |
3667 | } | |
3668 | } | |
3669 | ||
3670 | static void | |
3671 | fix_loongson2f (struct mips_cl_insn * ip) | |
3672 | { | |
3673 | if (mips_fix_loongson2f_nop) | |
3674 | fix_loongson2f_nop (ip); | |
3675 | ||
3676 | if (mips_fix_loongson2f_jump) | |
3677 | fix_loongson2f_jump (ip); | |
3678 | } | |
3679 | ||
a4e06468 RS |
3680 | /* IP is a branch that has a delay slot, and we need to fill it |
3681 | automatically. Return true if we can do that by swapping IP | |
3682 | with the previous instruction. */ | |
3683 | ||
3684 | static bfd_boolean | |
3685 | can_swap_branch_p (struct mips_cl_insn *ip) | |
3686 | { | |
2b0c8b40 | 3687 | unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2; |
a4e06468 RS |
3688 | unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write; |
3689 | ||
df58fc94 | 3690 | |
a4e06468 RS |
3691 | /* -O2 and above is required for this optimization. */ |
3692 | if (mips_optimize < 2) | |
3693 | return FALSE; | |
3694 | ||
3695 | /* If we have seen .set volatile or .set nomove, don't optimize. */ | |
3696 | if (mips_opts.nomove) | |
3697 | return FALSE; | |
3698 | ||
3699 | /* We can't swap if the previous instruction's position is fixed. */ | |
3700 | if (history[0].fixed_p) | |
3701 | return FALSE; | |
3702 | ||
3703 | /* If the previous previous insn was in a .set noreorder, we can't | |
3704 | swap. Actually, the MIPS assembler will swap in this situation. | |
3705 | However, gcc configured -with-gnu-as will generate code like | |
3706 | ||
3707 | .set noreorder | |
3708 | lw $4,XXX | |
3709 | .set reorder | |
3710 | INSN | |
3711 | bne $4,$0,foo | |
3712 | ||
3713 | in which we can not swap the bne and INSN. If gcc is not configured | |
3714 | -with-gnu-as, it does not output the .set pseudo-ops. */ | |
3715 | if (history[1].noreorder_p) | |
3716 | return FALSE; | |
3717 | ||
87333bb7 MR |
3718 | /* If the previous instruction had a fixup in mips16 mode, we can not swap. |
3719 | This means that the previous instruction was a 4-byte one anyhow. */ | |
a4e06468 RS |
3720 | if (mips_opts.mips16 && history[0].fixp[0]) |
3721 | return FALSE; | |
3722 | ||
3723 | /* If the branch is itself the target of a branch, we can not swap. | |
3724 | We cheat on this; all we check for is whether there is a label on | |
3725 | this instruction. If there are any branches to anything other than | |
3726 | a label, users must use .set noreorder. */ | |
3727 | if (seg_info (now_seg)->label_list) | |
3728 | return FALSE; | |
3729 | ||
3730 | /* If the previous instruction is in a variant frag other than this | |
2309ddf2 MR |
3731 | branch's one, we cannot do the swap. This does not apply to |
3732 | MIPS16/microMIPS code, which uses variant frags for different | |
3733 | purposes. */ | |
df58fc94 | 3734 | if (!HAVE_CODE_COMPRESSION |
a4e06468 RS |
3735 | && history[0].frag |
3736 | && history[0].frag->fr_type == rs_machine_dependent) | |
3737 | return FALSE; | |
3738 | ||
bcd530a7 RS |
3739 | /* We do not swap with instructions that cannot architecturally |
3740 | be placed in a branch delay slot, such as SYNC or ERET. We | |
3741 | also refrain from swapping with a trap instruction, since it | |
3742 | complicates trap handlers to have the trap instruction be in | |
3743 | a delay slot. */ | |
a4e06468 | 3744 | prev_pinfo = history[0].insn_mo->pinfo; |
bcd530a7 | 3745 | if (prev_pinfo & INSN_NO_DELAY_SLOT) |
a4e06468 RS |
3746 | return FALSE; |
3747 | ||
3748 | /* Check for conflicts between the branch and the instructions | |
3749 | before the candidate delay slot. */ | |
3750 | if (nops_for_insn (0, history + 1, ip) > 0) | |
3751 | return FALSE; | |
3752 | ||
3753 | /* Check for conflicts between the swapped sequence and the | |
3754 | target of the branch. */ | |
3755 | if (nops_for_sequence (2, 0, history + 1, ip, history) > 0) | |
3756 | return FALSE; | |
3757 | ||
3758 | /* If the branch reads a register that the previous | |
3759 | instruction sets, we can not swap. */ | |
3760 | gpr_read = gpr_read_mask (ip); | |
3761 | prev_gpr_write = gpr_write_mask (&history[0]); | |
3762 | if (gpr_read & prev_gpr_write) | |
3763 | return FALSE; | |
3764 | ||
3765 | /* If the branch writes a register that the previous | |
3766 | instruction sets, we can not swap. */ | |
3767 | gpr_write = gpr_write_mask (ip); | |
3768 | if (gpr_write & prev_gpr_write) | |
3769 | return FALSE; | |
3770 | ||
3771 | /* If the branch writes a register that the previous | |
3772 | instruction reads, we can not swap. */ | |
3773 | prev_gpr_read = gpr_read_mask (&history[0]); | |
3774 | if (gpr_write & prev_gpr_read) | |
3775 | return FALSE; | |
3776 | ||
3777 | /* If one instruction sets a condition code and the | |
3778 | other one uses a condition code, we can not swap. */ | |
3779 | pinfo = ip->insn_mo->pinfo; | |
3780 | if ((pinfo & INSN_READ_COND_CODE) | |
3781 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
3782 | return FALSE; | |
3783 | if ((pinfo & INSN_WRITE_COND_CODE) | |
3784 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
3785 | return FALSE; | |
3786 | ||
3787 | /* If the previous instruction uses the PC, we can not swap. */ | |
2b0c8b40 | 3788 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
a4e06468 RS |
3789 | if (mips_opts.mips16 && (prev_pinfo & MIPS16_INSN_READ_PC)) |
3790 | return FALSE; | |
2b0c8b40 MR |
3791 | if (mips_opts.micromips && (prev_pinfo2 & INSN2_READ_PC)) |
3792 | return FALSE; | |
a4e06468 | 3793 | |
df58fc94 RS |
3794 | /* If the previous instruction has an incorrect size for a fixed |
3795 | branch delay slot in microMIPS mode, we cannot swap. */ | |
2309ddf2 MR |
3796 | pinfo2 = ip->insn_mo->pinfo2; |
3797 | if (mips_opts.micromips | |
3798 | && (pinfo2 & INSN2_BRANCH_DELAY_16BIT) | |
3799 | && insn_length (history) != 2) | |
3800 | return FALSE; | |
3801 | if (mips_opts.micromips | |
3802 | && (pinfo2 & INSN2_BRANCH_DELAY_32BIT) | |
3803 | && insn_length (history) != 4) | |
3804 | return FALSE; | |
3805 | ||
a4e06468 RS |
3806 | return TRUE; |
3807 | } | |
3808 | ||
3809 | /* Decide how we should add IP to the instruction stream. */ | |
3810 | ||
3811 | static enum append_method | |
3812 | get_append_method (struct mips_cl_insn *ip) | |
3813 | { | |
3814 | unsigned long pinfo; | |
3815 | ||
3816 | /* The relaxed version of a macro sequence must be inherently | |
3817 | hazard-free. */ | |
3818 | if (mips_relax.sequence == 2) | |
3819 | return APPEND_ADD; | |
3820 | ||
3821 | /* We must not dabble with instructions in a ".set norerorder" block. */ | |
3822 | if (mips_opts.noreorder) | |
3823 | return APPEND_ADD; | |
3824 | ||
3825 | /* Otherwise, it's our responsibility to fill branch delay slots. */ | |
11625dd8 | 3826 | if (delayed_branch_p (ip)) |
a4e06468 | 3827 | { |
11625dd8 | 3828 | if (!branch_likely_p (ip) && can_swap_branch_p (ip)) |
a4e06468 RS |
3829 | return APPEND_SWAP; |
3830 | ||
11625dd8 | 3831 | pinfo = ip->insn_mo->pinfo; |
a4e06468 RS |
3832 | if (mips_opts.mips16 |
3833 | && ISA_SUPPORTS_MIPS16E | |
a4e06468 RS |
3834 | && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31))) |
3835 | return APPEND_ADD_COMPACT; | |
3836 | ||
3837 | return APPEND_ADD_WITH_NOP; | |
3838 | } | |
3839 | ||
a4e06468 RS |
3840 | return APPEND_ADD; |
3841 | } | |
3842 | ||
ceb94aa5 RS |
3843 | /* IP is a MIPS16 instruction whose opcode we have just changed. |
3844 | Point IP->insn_mo to the new opcode's definition. */ | |
3845 | ||
3846 | static void | |
3847 | find_altered_mips16_opcode (struct mips_cl_insn *ip) | |
3848 | { | |
3849 | const struct mips_opcode *mo, *end; | |
3850 | ||
3851 | end = &mips16_opcodes[bfd_mips16_num_opcodes]; | |
3852 | for (mo = ip->insn_mo; mo < end; mo++) | |
3853 | if ((ip->insn_opcode & mo->mask) == mo->match) | |
3854 | { | |
3855 | ip->insn_mo = mo; | |
3856 | return; | |
3857 | } | |
3858 | abort (); | |
3859 | } | |
3860 | ||
df58fc94 RS |
3861 | /* For microMIPS macros, we need to generate a local number label |
3862 | as the target of branches. */ | |
3863 | #define MICROMIPS_LABEL_CHAR '\037' | |
3864 | static unsigned long micromips_target_label; | |
3865 | static char micromips_target_name[32]; | |
3866 | ||
3867 | static char * | |
3868 | micromips_label_name (void) | |
3869 | { | |
3870 | char *p = micromips_target_name; | |
3871 | char symbol_name_temporary[24]; | |
3872 | unsigned long l; | |
3873 | int i; | |
3874 | ||
3875 | if (*p) | |
3876 | return p; | |
3877 | ||
3878 | i = 0; | |
3879 | l = micromips_target_label; | |
3880 | #ifdef LOCAL_LABEL_PREFIX | |
3881 | *p++ = LOCAL_LABEL_PREFIX; | |
3882 | #endif | |
3883 | *p++ = 'L'; | |
3884 | *p++ = MICROMIPS_LABEL_CHAR; | |
3885 | do | |
3886 | { | |
3887 | symbol_name_temporary[i++] = l % 10 + '0'; | |
3888 | l /= 10; | |
3889 | } | |
3890 | while (l != 0); | |
3891 | while (i > 0) | |
3892 | *p++ = symbol_name_temporary[--i]; | |
3893 | *p = '\0'; | |
3894 | ||
3895 | return micromips_target_name; | |
3896 | } | |
3897 | ||
3898 | static void | |
3899 | micromips_label_expr (expressionS *label_expr) | |
3900 | { | |
3901 | label_expr->X_op = O_symbol; | |
3902 | label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ()); | |
3903 | label_expr->X_add_number = 0; | |
3904 | } | |
3905 | ||
3906 | static void | |
3907 | micromips_label_inc (void) | |
3908 | { | |
3909 | micromips_target_label++; | |
3910 | *micromips_target_name = '\0'; | |
3911 | } | |
3912 | ||
3913 | static void | |
3914 | micromips_add_label (void) | |
3915 | { | |
3916 | symbolS *s; | |
3917 | ||
3918 | s = colon (micromips_label_name ()); | |
3919 | micromips_label_inc (); | |
3920 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) | |
3921 | if (IS_ELF) | |
3922 | S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s))); | |
db9b2be4 AM |
3923 | #else |
3924 | (void) s; | |
df58fc94 RS |
3925 | #endif |
3926 | } | |
3927 | ||
3928 | /* If assembling microMIPS code, then return the microMIPS reloc | |
3929 | corresponding to the requested one if any. Otherwise return | |
3930 | the reloc unchanged. */ | |
3931 | ||
3932 | static bfd_reloc_code_real_type | |
3933 | micromips_map_reloc (bfd_reloc_code_real_type reloc) | |
3934 | { | |
3935 | static const bfd_reloc_code_real_type relocs[][2] = | |
3936 | { | |
3937 | /* Keep sorted incrementally by the left-hand key. */ | |
3938 | { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 }, | |
3939 | { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 }, | |
3940 | { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP }, | |
3941 | { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 }, | |
3942 | { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S }, | |
3943 | { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 }, | |
3944 | { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL }, | |
3945 | { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 }, | |
3946 | { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 }, | |
3947 | { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 }, | |
3948 | { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 }, | |
3949 | { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 }, | |
3950 | { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 }, | |
3951 | { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB }, | |
3952 | { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE }, | |
3953 | { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST }, | |
3954 | { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP }, | |
3955 | { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST }, | |
3956 | { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER }, | |
3957 | { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP }, | |
3958 | { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD }, | |
3959 | { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM }, | |
3960 | { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 }, | |
3961 | { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 }, | |
3962 | { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL }, | |
3963 | { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 }, | |
3964 | { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 } | |
3965 | }; | |
3966 | bfd_reloc_code_real_type r; | |
3967 | size_t i; | |
3968 | ||
3969 | if (!mips_opts.micromips) | |
3970 | return reloc; | |
3971 | for (i = 0; i < ARRAY_SIZE (relocs); i++) | |
3972 | { | |
3973 | r = relocs[i][0]; | |
3974 | if (r > reloc) | |
3975 | return reloc; | |
3976 | if (r == reloc) | |
3977 | return relocs[i][1]; | |
3978 | } | |
3979 | return reloc; | |
3980 | } | |
3981 | ||
71400594 RS |
3982 | /* Output an instruction. IP is the instruction information. |
3983 | ADDRESS_EXPR is an operand of the instruction to be used with | |
df58fc94 RS |
3984 | RELOC_TYPE. EXPANSIONP is true if the instruction is part of |
3985 | a macro expansion. */ | |
71400594 RS |
3986 | |
3987 | static void | |
3988 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
df58fc94 | 3989 | bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp) |
71400594 | 3990 | { |
14fe068b | 3991 | unsigned long prev_pinfo2, pinfo; |
71400594 | 3992 | bfd_boolean relaxed_branch = FALSE; |
a4e06468 | 3993 | enum append_method method; |
2309ddf2 | 3994 | bfd_boolean relax32; |
2b0c8b40 | 3995 | int branch_disp; |
71400594 | 3996 | |
2309ddf2 | 3997 | if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION) |
c67a084a NC |
3998 | fix_loongson2f (ip); |
3999 | ||
df58fc94 | 4000 | mips_mark_labels (); |
71400594 | 4001 | |
738f4d98 | 4002 | file_ase_mips16 |= mips_opts.mips16; |
df58fc94 | 4003 | file_ase_micromips |= mips_opts.micromips; |
738f4d98 | 4004 | |
df58fc94 | 4005 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
71400594 | 4006 | pinfo = ip->insn_mo->pinfo; |
df58fc94 RS |
4007 | |
4008 | if (mips_opts.micromips | |
4009 | && !expansionp | |
4010 | && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 | |
4011 | && micromips_insn_length (ip->insn_mo) != 2) | |
4012 | || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 | |
4013 | && micromips_insn_length (ip->insn_mo) != 4))) | |
4014 | as_warn (_("Wrong size instruction in a %u-bit branch delay slot"), | |
4015 | (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32); | |
71400594 | 4016 | |
15be625d CM |
4017 | if (address_expr == NULL) |
4018 | ip->complete_p = 1; | |
4019 | else if (*reloc_type <= BFD_RELOC_UNUSED | |
4020 | && address_expr->X_op == O_constant) | |
4021 | { | |
4022 | unsigned int tmp; | |
4023 | ||
4024 | ip->complete_p = 1; | |
4025 | switch (*reloc_type) | |
4026 | { | |
4027 | case BFD_RELOC_32: | |
4028 | ip->insn_opcode |= address_expr->X_add_number; | |
4029 | break; | |
4030 | ||
4031 | case BFD_RELOC_MIPS_HIGHEST: | |
4032 | tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48; | |
4033 | ip->insn_opcode |= tmp & 0xffff; | |
4034 | break; | |
4035 | ||
4036 | case BFD_RELOC_MIPS_HIGHER: | |
4037 | tmp = (address_expr->X_add_number + 0x80008000ull) >> 32; | |
4038 | ip->insn_opcode |= tmp & 0xffff; | |
4039 | break; | |
4040 | ||
4041 | case BFD_RELOC_HI16_S: | |
4042 | tmp = (address_expr->X_add_number + 0x8000) >> 16; | |
4043 | ip->insn_opcode |= tmp & 0xffff; | |
4044 | break; | |
4045 | ||
4046 | case BFD_RELOC_HI16: | |
4047 | ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; | |
4048 | break; | |
4049 | ||
4050 | case BFD_RELOC_UNUSED: | |
4051 | case BFD_RELOC_LO16: | |
4052 | case BFD_RELOC_MIPS_GOT_DISP: | |
4053 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; | |
4054 | break; | |
4055 | ||
4056 | case BFD_RELOC_MIPS_JMP: | |
df58fc94 RS |
4057 | { |
4058 | int shift; | |
4059 | ||
4060 | shift = mips_opts.micromips ? 1 : 2; | |
4061 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
4062 | as_bad (_("jump to misaligned address (0x%lx)"), | |
4063 | (unsigned long) address_expr->X_add_number); | |
4064 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
4065 | & 0x3ffffff); | |
4066 | ip->complete_p = 0; | |
4067 | } | |
15be625d CM |
4068 | break; |
4069 | ||
4070 | case BFD_RELOC_MIPS16_JMP: | |
4071 | if ((address_expr->X_add_number & 3) != 0) | |
4072 | as_bad (_("jump to misaligned address (0x%lx)"), | |
4073 | (unsigned long) address_expr->X_add_number); | |
4074 | ip->insn_opcode |= | |
4075 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
4076 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
4077 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
4078 | ip->complete_p = 0; | |
4079 | break; | |
4080 | ||
4081 | case BFD_RELOC_16_PCREL_S2: | |
df58fc94 RS |
4082 | { |
4083 | int shift; | |
4084 | ||
4085 | shift = mips_opts.micromips ? 1 : 2; | |
4086 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
4087 | as_bad (_("branch to misaligned address (0x%lx)"), | |
4088 | (unsigned long) address_expr->X_add_number); | |
4089 | if (!mips_relax_branch) | |
4090 | { | |
4091 | if ((address_expr->X_add_number + (1 << (shift + 15))) | |
4092 | & ~((1 << (shift + 16)) - 1)) | |
4093 | as_bad (_("branch address range overflow (0x%lx)"), | |
4094 | (unsigned long) address_expr->X_add_number); | |
4095 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
4096 | & 0xffff); | |
4097 | } | |
4098 | ip->complete_p = 0; | |
4099 | } | |
15be625d CM |
4100 | break; |
4101 | ||
4102 | default: | |
4103 | internalError (); | |
4104 | } | |
4105 | } | |
4106 | ||
71400594 RS |
4107 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
4108 | { | |
4109 | /* There are a lot of optimizations we could do that we don't. | |
4110 | In particular, we do not, in general, reorder instructions. | |
4111 | If you use gcc with optimization, it will reorder | |
4112 | instructions and generally do much more optimization then we | |
4113 | do here; repeating all that work in the assembler would only | |
4114 | benefit hand written assembly code, and does not seem worth | |
4115 | it. */ | |
4116 | int nops = (mips_optimize == 0 | |
932d1a1b RS |
4117 | ? nops_for_insn (0, history, NULL) |
4118 | : nops_for_insn_or_target (0, history, ip)); | |
71400594 | 4119 | if (nops > 0) |
252b5132 RH |
4120 | { |
4121 | fragS *old_frag; | |
4122 | unsigned long old_frag_offset; | |
4123 | int i; | |
252b5132 RH |
4124 | |
4125 | old_frag = frag_now; | |
4126 | old_frag_offset = frag_now_fix (); | |
4127 | ||
4128 | for (i = 0; i < nops; i++) | |
14fe068b RS |
4129 | add_fixed_insn (NOP_INSN); |
4130 | insert_into_history (0, nops, NOP_INSN); | |
252b5132 RH |
4131 | |
4132 | if (listing) | |
4133 | { | |
4134 | listing_prev_line (); | |
4135 | /* We may be at the start of a variant frag. In case we | |
4136 | are, make sure there is enough space for the frag | |
4137 | after the frags created by listing_prev_line. The | |
4138 | argument to frag_grow here must be at least as large | |
4139 | as the argument to all other calls to frag_grow in | |
4140 | this file. We don't have to worry about being in the | |
4141 | middle of a variant frag, because the variants insert | |
4142 | all needed nop instructions themselves. */ | |
4143 | frag_grow (40); | |
4144 | } | |
4145 | ||
404a8071 | 4146 | mips_move_labels (); |
252b5132 RH |
4147 | |
4148 | #ifndef NO_ECOFF_DEBUGGING | |
4149 | if (ECOFF_DEBUGGING) | |
4150 | ecoff_fix_loc (old_frag, old_frag_offset); | |
4151 | #endif | |
4152 | } | |
71400594 RS |
4153 | } |
4154 | else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) | |
4155 | { | |
932d1a1b RS |
4156 | int nops; |
4157 | ||
4158 | /* Work out how many nops in prev_nop_frag are needed by IP, | |
4159 | ignoring hazards generated by the first prev_nop_frag_since | |
4160 | instructions. */ | |
4161 | nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip); | |
9c2799c2 | 4162 | gas_assert (nops <= prev_nop_frag_holds); |
252b5132 | 4163 | |
71400594 RS |
4164 | /* Enforce NOPS as a minimum. */ |
4165 | if (nops > prev_nop_frag_required) | |
4166 | prev_nop_frag_required = nops; | |
252b5132 | 4167 | |
71400594 RS |
4168 | if (prev_nop_frag_holds == prev_nop_frag_required) |
4169 | { | |
4170 | /* Settle for the current number of nops. Update the history | |
4171 | accordingly (for the benefit of any future .set reorder code). */ | |
4172 | prev_nop_frag = NULL; | |
4173 | insert_into_history (prev_nop_frag_since, | |
4174 | prev_nop_frag_holds, NOP_INSN); | |
4175 | } | |
4176 | else | |
4177 | { | |
4178 | /* Allow this instruction to replace one of the nops that was | |
4179 | tentatively added to prev_nop_frag. */ | |
df58fc94 | 4180 | prev_nop_frag->fr_fix -= NOP_INSN_SIZE; |
71400594 RS |
4181 | prev_nop_frag_holds--; |
4182 | prev_nop_frag_since++; | |
252b5132 RH |
4183 | } |
4184 | } | |
4185 | ||
a4e06468 | 4186 | method = get_append_method (ip); |
2b0c8b40 | 4187 | branch_disp = method == APPEND_SWAP ? insn_length (history) : 0; |
a4e06468 | 4188 | |
58e2ea4d MR |
4189 | #ifdef OBJ_ELF |
4190 | /* The value passed to dwarf2_emit_insn is the distance between | |
4191 | the beginning of the current instruction and the address that | |
e3a82c8e MR |
4192 | should be recorded in the debug tables. This is normally the |
4193 | current address. | |
4194 | ||
df58fc94 RS |
4195 | For MIPS16/microMIPS debug info we want to use ISA-encoded |
4196 | addresses, so we use -1 for an address higher by one than the | |
4197 | current one. | |
e3a82c8e MR |
4198 | |
4199 | If the instruction produced is a branch that we will swap with | |
4200 | the preceding instruction, then we add the displacement by which | |
4201 | the branch will be moved backwards. This is more appropriate | |
2309ddf2 MR |
4202 | and for MIPS16/microMIPS code also prevents a debugger from |
4203 | placing a breakpoint in the middle of the branch (and corrupting | |
4204 | code if software breakpoints are used). */ | |
2b0c8b40 | 4205 | dwarf2_emit_insn ((HAVE_CODE_COMPRESSION ? -1 : 0) + branch_disp); |
58e2ea4d MR |
4206 | #endif |
4207 | ||
df58fc94 RS |
4208 | relax32 = (mips_relax_branch |
4209 | /* Don't try branch relaxation within .set nomacro, or within | |
4210 | .set noat if we use $at for PIC computations. If it turns | |
4211 | out that the branch was out-of-range, we'll get an error. */ | |
4212 | && !mips_opts.warn_about_macros | |
4213 | && (mips_opts.at || mips_pic == NO_PIC) | |
4214 | /* Don't relax BPOSGE32/64 as they have no complementing | |
4215 | branches. */ | |
40209cad | 4216 | && !(ip->insn_mo->membership & (INSN_DSP64 | INSN_DSP))); |
df58fc94 RS |
4217 | |
4218 | if (!HAVE_CODE_COMPRESSION | |
4219 | && address_expr | |
4220 | && relax32 | |
0b25d3e6 | 4221 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
11625dd8 | 4222 | && delayed_branch_p (ip)) |
4a6a3df4 | 4223 | { |
895921c9 | 4224 | relaxed_branch = TRUE; |
1e915849 RS |
4225 | add_relaxed_insn (ip, (relaxed_branch_length |
4226 | (NULL, NULL, | |
11625dd8 RS |
4227 | uncond_branch_p (ip) ? -1 |
4228 | : branch_likely_p (ip) ? 1 | |
1e915849 RS |
4229 | : 0)), 4, |
4230 | RELAX_BRANCH_ENCODE | |
66b3e8da | 4231 | (AT, |
11625dd8 RS |
4232 | uncond_branch_p (ip), |
4233 | branch_likely_p (ip), | |
1e915849 RS |
4234 | pinfo & INSN_WRITE_GPR_31, |
4235 | 0), | |
4236 | address_expr->X_add_symbol, | |
4237 | address_expr->X_add_number); | |
4a6a3df4 AO |
4238 | *reloc_type = BFD_RELOC_UNUSED; |
4239 | } | |
df58fc94 RS |
4240 | else if (mips_opts.micromips |
4241 | && address_expr | |
4242 | && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2) | |
4243 | || *reloc_type > BFD_RELOC_UNUSED) | |
40209cad MR |
4244 | && (delayed_branch_p (ip) || compact_branch_p (ip)) |
4245 | /* Don't try branch relaxation when users specify | |
4246 | 16-bit/32-bit instructions. */ | |
4247 | && !forced_insn_length) | |
df58fc94 RS |
4248 | { |
4249 | bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED; | |
4250 | int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0; | |
11625dd8 RS |
4251 | int uncond = uncond_branch_p (ip) ? -1 : 0; |
4252 | int compact = compact_branch_p (ip); | |
df58fc94 RS |
4253 | int al = pinfo & INSN_WRITE_GPR_31; |
4254 | int length32; | |
4255 | ||
4256 | gas_assert (address_expr != NULL); | |
4257 | gas_assert (!mips_relax.sequence); | |
4258 | ||
2b0c8b40 | 4259 | relaxed_branch = TRUE; |
df58fc94 RS |
4260 | length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond); |
4261 | add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4, | |
40209cad MR |
4262 | RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al, |
4263 | relax32, 0, 0), | |
df58fc94 RS |
4264 | address_expr->X_add_symbol, |
4265 | address_expr->X_add_number); | |
4266 | *reloc_type = BFD_RELOC_UNUSED; | |
4267 | } | |
4268 | else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
4269 | { |
4270 | /* We need to set up a variant frag. */ | |
df58fc94 | 4271 | gas_assert (address_expr != NULL); |
1e915849 RS |
4272 | add_relaxed_insn (ip, 4, 0, |
4273 | RELAX_MIPS16_ENCODE | |
4274 | (*reloc_type - BFD_RELOC_UNUSED, | |
df58fc94 | 4275 | forced_insn_length == 2, forced_insn_length == 4, |
11625dd8 | 4276 | delayed_branch_p (&history[0]), |
1e915849 RS |
4277 | history[0].mips16_absolute_jump_p), |
4278 | make_expr_symbol (address_expr), 0); | |
252b5132 | 4279 | } |
252b5132 RH |
4280 | else if (mips_opts.mips16 |
4281 | && ! ip->use_extend | |
f6688943 | 4282 | && *reloc_type != BFD_RELOC_MIPS16_JMP) |
9497f5ac | 4283 | { |
11625dd8 | 4284 | if (!delayed_branch_p (ip)) |
b8ee1a6e DU |
4285 | /* Make sure there is enough room to swap this instruction with |
4286 | a following jump instruction. */ | |
4287 | frag_grow (6); | |
1e915849 | 4288 | add_fixed_insn (ip); |
252b5132 RH |
4289 | } |
4290 | else | |
4291 | { | |
4292 | if (mips_opts.mips16 | |
4293 | && mips_opts.noreorder | |
11625dd8 | 4294 | && delayed_branch_p (&history[0])) |
252b5132 RH |
4295 | as_warn (_("extended instruction in delay slot")); |
4296 | ||
4d7206a2 RS |
4297 | if (mips_relax.sequence) |
4298 | { | |
4299 | /* If we've reached the end of this frag, turn it into a variant | |
4300 | frag and record the information for the instructions we've | |
4301 | written so far. */ | |
4302 | if (frag_room () < 4) | |
4303 | relax_close_frag (); | |
df58fc94 | 4304 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip); |
4d7206a2 RS |
4305 | } |
4306 | ||
584892a6 | 4307 | if (mips_relax.sequence != 2) |
df58fc94 RS |
4308 | { |
4309 | if (mips_macro_warning.first_insn_sizes[0] == 0) | |
4310 | mips_macro_warning.first_insn_sizes[0] = insn_length (ip); | |
4311 | mips_macro_warning.sizes[0] += insn_length (ip); | |
4312 | mips_macro_warning.insns[0]++; | |
4313 | } | |
584892a6 | 4314 | if (mips_relax.sequence != 1) |
df58fc94 RS |
4315 | { |
4316 | if (mips_macro_warning.first_insn_sizes[1] == 0) | |
4317 | mips_macro_warning.first_insn_sizes[1] = insn_length (ip); | |
4318 | mips_macro_warning.sizes[1] += insn_length (ip); | |
4319 | mips_macro_warning.insns[1]++; | |
4320 | } | |
584892a6 | 4321 | |
1e915849 RS |
4322 | if (mips_opts.mips16) |
4323 | { | |
4324 | ip->fixed_p = 1; | |
4325 | ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); | |
4326 | } | |
4327 | add_fixed_insn (ip); | |
252b5132 RH |
4328 | } |
4329 | ||
9fe77896 | 4330 | if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 4331 | { |
df58fc94 | 4332 | bfd_reloc_code_real_type final_type[3]; |
2309ddf2 | 4333 | reloc_howto_type *howto0; |
9fe77896 RS |
4334 | reloc_howto_type *howto; |
4335 | int i; | |
34ce925e | 4336 | |
df58fc94 RS |
4337 | /* Perform any necessary conversion to microMIPS relocations |
4338 | and find out how many relocations there actually are. */ | |
4339 | for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++) | |
4340 | final_type[i] = micromips_map_reloc (reloc_type[i]); | |
4341 | ||
9fe77896 RS |
4342 | /* In a compound relocation, it is the final (outermost) |
4343 | operator that determines the relocated field. */ | |
2309ddf2 MR |
4344 | howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]); |
4345 | ||
9fe77896 RS |
4346 | if (howto == NULL) |
4347 | { | |
4348 | /* To reproduce this failure try assembling gas/testsuites/ | |
4349 | gas/mips/mips16-intermix.s with a mips-ecoff targeted | |
4350 | assembler. */ | |
df58fc94 RS |
4351 | as_bad (_("Unsupported MIPS relocation number %d"), |
4352 | final_type[i - 1]); | |
9fe77896 RS |
4353 | howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16); |
4354 | } | |
2309ddf2 MR |
4355 | |
4356 | if (i > 1) | |
4357 | howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]); | |
9fe77896 RS |
4358 | ip->fixp[0] = fix_new_exp (ip->frag, ip->where, |
4359 | bfd_get_reloc_size (howto), | |
4360 | address_expr, | |
2309ddf2 MR |
4361 | howto0 && howto0->pc_relative, |
4362 | final_type[0]); | |
9fe77896 RS |
4363 | |
4364 | /* Tag symbols that have a R_MIPS16_26 relocation against them. */ | |
2309ddf2 | 4365 | if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy) |
9fe77896 RS |
4366 | *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1; |
4367 | ||
4368 | /* These relocations can have an addend that won't fit in | |
4369 | 4 octets for 64bit assembly. */ | |
4370 | if (HAVE_64BIT_GPRS | |
4371 | && ! howto->partial_inplace | |
4372 | && (reloc_type[0] == BFD_RELOC_16 | |
4373 | || reloc_type[0] == BFD_RELOC_32 | |
4374 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
4375 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
4376 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
4377 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
4378 | || reloc_type[0] == BFD_RELOC_64 | |
4379 | || reloc_type[0] == BFD_RELOC_CTOR | |
4380 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
4381 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
4382 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
4383 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
4384 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
4385 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT | |
4386 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
4387 | || hi16_reloc_p (reloc_type[0]) | |
4388 | || lo16_reloc_p (reloc_type[0]))) | |
4389 | ip->fixp[0]->fx_no_overflow = 1; | |
4390 | ||
4391 | if (mips_relax.sequence) | |
4392 | { | |
4393 | if (mips_relax.first_fixup == 0) | |
4394 | mips_relax.first_fixup = ip->fixp[0]; | |
4395 | } | |
4396 | else if (reloc_needs_lo_p (*reloc_type)) | |
4397 | { | |
4398 | struct mips_hi_fixup *hi_fixup; | |
4399 | ||
4400 | /* Reuse the last entry if it already has a matching %lo. */ | |
4401 | hi_fixup = mips_hi_fixup_list; | |
4402 | if (hi_fixup == 0 | |
4403 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
4d7206a2 | 4404 | { |
9fe77896 RS |
4405 | hi_fixup = ((struct mips_hi_fixup *) |
4406 | xmalloc (sizeof (struct mips_hi_fixup))); | |
4407 | hi_fixup->next = mips_hi_fixup_list; | |
4408 | mips_hi_fixup_list = hi_fixup; | |
4d7206a2 | 4409 | } |
9fe77896 RS |
4410 | hi_fixup->fixp = ip->fixp[0]; |
4411 | hi_fixup->seg = now_seg; | |
4412 | } | |
252b5132 | 4413 | |
9fe77896 RS |
4414 | /* Add fixups for the second and third relocations, if given. |
4415 | Note that the ABI allows the second relocation to be | |
4416 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
4417 | moment we only use RSS_UNDEF, but we could add support | |
4418 | for the others if it ever becomes necessary. */ | |
4419 | for (i = 1; i < 3; i++) | |
4420 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
4421 | { | |
4422 | ip->fixp[i] = fix_new (ip->frag, ip->where, | |
4423 | ip->fixp[0]->fx_size, NULL, 0, | |
df58fc94 | 4424 | FALSE, final_type[i]); |
f6688943 | 4425 | |
9fe77896 RS |
4426 | /* Use fx_tcbit to mark compound relocs. */ |
4427 | ip->fixp[0]->fx_tcbit = 1; | |
4428 | ip->fixp[i]->fx_tcbit = 1; | |
4429 | } | |
252b5132 | 4430 | } |
1e915849 | 4431 | install_insn (ip); |
252b5132 RH |
4432 | |
4433 | /* Update the register mask information. */ | |
4c260379 RS |
4434 | mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip); |
4435 | mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip); | |
252b5132 | 4436 | |
a4e06468 | 4437 | switch (method) |
252b5132 | 4438 | { |
a4e06468 RS |
4439 | case APPEND_ADD: |
4440 | insert_into_history (0, 1, ip); | |
4441 | break; | |
4442 | ||
4443 | case APPEND_ADD_WITH_NOP: | |
14fe068b RS |
4444 | { |
4445 | struct mips_cl_insn *nop; | |
4446 | ||
4447 | insert_into_history (0, 1, ip); | |
4448 | nop = get_delay_slot_nop (ip); | |
4449 | add_fixed_insn (nop); | |
4450 | insert_into_history (0, 1, nop); | |
4451 | if (mips_relax.sequence) | |
4452 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop); | |
4453 | } | |
a4e06468 RS |
4454 | break; |
4455 | ||
4456 | case APPEND_ADD_COMPACT: | |
4457 | /* Convert MIPS16 jr/jalr into a "compact" jump. */ | |
4458 | gas_assert (mips_opts.mips16); | |
4459 | ip->insn_opcode |= 0x0080; | |
4460 | find_altered_mips16_opcode (ip); | |
4461 | install_insn (ip); | |
4462 | insert_into_history (0, 1, ip); | |
4463 | break; | |
4464 | ||
4465 | case APPEND_SWAP: | |
4466 | { | |
4467 | struct mips_cl_insn delay = history[0]; | |
4468 | if (mips_opts.mips16) | |
4469 | { | |
4470 | know (delay.frag == ip->frag); | |
4471 | move_insn (ip, delay.frag, delay.where); | |
4472 | move_insn (&delay, ip->frag, ip->where + insn_length (ip)); | |
4473 | } | |
4474 | else if (relaxed_branch) | |
4475 | { | |
4476 | /* Add the delay slot instruction to the end of the | |
4477 | current frag and shrink the fixed part of the | |
4478 | original frag. If the branch occupies the tail of | |
4479 | the latter, move it backwards to cover the gap. */ | |
2b0c8b40 | 4480 | delay.frag->fr_fix -= branch_disp; |
a4e06468 | 4481 | if (delay.frag == ip->frag) |
2b0c8b40 | 4482 | move_insn (ip, ip->frag, ip->where - branch_disp); |
a4e06468 RS |
4483 | add_fixed_insn (&delay); |
4484 | } | |
4485 | else | |
4486 | { | |
2b0c8b40 MR |
4487 | move_insn (&delay, ip->frag, |
4488 | ip->where - branch_disp + insn_length (ip)); | |
a4e06468 RS |
4489 | move_insn (ip, history[0].frag, history[0].where); |
4490 | } | |
4491 | history[0] = *ip; | |
4492 | delay.fixed_p = 1; | |
4493 | insert_into_history (0, 1, &delay); | |
4494 | } | |
4495 | break; | |
252b5132 RH |
4496 | } |
4497 | ||
13408f1e | 4498 | /* If we have just completed an unconditional branch, clear the history. */ |
11625dd8 RS |
4499 | if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1])) |
4500 | || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0]))) | |
13408f1e RS |
4501 | mips_no_prev_insn (); |
4502 | ||
df58fc94 RS |
4503 | /* We need to emit a label at the end of branch-likely macros. */ |
4504 | if (emit_branch_likely_macro) | |
4505 | { | |
4506 | emit_branch_likely_macro = FALSE; | |
4507 | micromips_add_label (); | |
4508 | } | |
4509 | ||
252b5132 RH |
4510 | /* We just output an insn, so the next one doesn't have a label. */ |
4511 | mips_clear_insn_labels (); | |
252b5132 RH |
4512 | } |
4513 | ||
7d10b47d | 4514 | /* Forget that there was any previous instruction or label. */ |
252b5132 RH |
4515 | |
4516 | static void | |
7d10b47d | 4517 | mips_no_prev_insn (void) |
252b5132 | 4518 | { |
7d10b47d RS |
4519 | prev_nop_frag = NULL; |
4520 | insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); | |
252b5132 RH |
4521 | mips_clear_insn_labels (); |
4522 | } | |
4523 | ||
7d10b47d RS |
4524 | /* This function must be called before we emit something other than |
4525 | instructions. It is like mips_no_prev_insn except that it inserts | |
4526 | any NOPS that might be needed by previous instructions. */ | |
252b5132 | 4527 | |
7d10b47d RS |
4528 | void |
4529 | mips_emit_delays (void) | |
252b5132 RH |
4530 | { |
4531 | if (! mips_opts.noreorder) | |
4532 | { | |
932d1a1b | 4533 | int nops = nops_for_insn (0, history, NULL); |
252b5132 RH |
4534 | if (nops > 0) |
4535 | { | |
7d10b47d RS |
4536 | while (nops-- > 0) |
4537 | add_fixed_insn (NOP_INSN); | |
4538 | mips_move_labels (); | |
4539 | } | |
4540 | } | |
4541 | mips_no_prev_insn (); | |
4542 | } | |
4543 | ||
4544 | /* Start a (possibly nested) noreorder block. */ | |
4545 | ||
4546 | static void | |
4547 | start_noreorder (void) | |
4548 | { | |
4549 | if (mips_opts.noreorder == 0) | |
4550 | { | |
4551 | unsigned int i; | |
4552 | int nops; | |
4553 | ||
4554 | /* None of the instructions before the .set noreorder can be moved. */ | |
4555 | for (i = 0; i < ARRAY_SIZE (history); i++) | |
4556 | history[i].fixed_p = 1; | |
4557 | ||
4558 | /* Insert any nops that might be needed between the .set noreorder | |
4559 | block and the previous instructions. We will later remove any | |
4560 | nops that turn out not to be needed. */ | |
932d1a1b | 4561 | nops = nops_for_insn (0, history, NULL); |
7d10b47d RS |
4562 | if (nops > 0) |
4563 | { | |
4564 | if (mips_optimize != 0) | |
252b5132 RH |
4565 | { |
4566 | /* Record the frag which holds the nop instructions, so | |
4567 | that we can remove them if we don't need them. */ | |
df58fc94 | 4568 | frag_grow (nops * NOP_INSN_SIZE); |
252b5132 RH |
4569 | prev_nop_frag = frag_now; |
4570 | prev_nop_frag_holds = nops; | |
4571 | prev_nop_frag_required = 0; | |
4572 | prev_nop_frag_since = 0; | |
4573 | } | |
4574 | ||
4575 | for (; nops > 0; --nops) | |
1e915849 | 4576 | add_fixed_insn (NOP_INSN); |
252b5132 | 4577 | |
7d10b47d RS |
4578 | /* Move on to a new frag, so that it is safe to simply |
4579 | decrease the size of prev_nop_frag. */ | |
4580 | frag_wane (frag_now); | |
4581 | frag_new (0); | |
404a8071 | 4582 | mips_move_labels (); |
252b5132 | 4583 | } |
df58fc94 | 4584 | mips_mark_labels (); |
7d10b47d | 4585 | mips_clear_insn_labels (); |
252b5132 | 4586 | } |
7d10b47d RS |
4587 | mips_opts.noreorder++; |
4588 | mips_any_noreorder = 1; | |
4589 | } | |
252b5132 | 4590 | |
7d10b47d | 4591 | /* End a nested noreorder block. */ |
252b5132 | 4592 | |
7d10b47d RS |
4593 | static void |
4594 | end_noreorder (void) | |
4595 | { | |
6a32d874 | 4596 | |
7d10b47d RS |
4597 | mips_opts.noreorder--; |
4598 | if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) | |
4599 | { | |
4600 | /* Commit to inserting prev_nop_frag_required nops and go back to | |
4601 | handling nop insertion the .set reorder way. */ | |
4602 | prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) | |
df58fc94 | 4603 | * NOP_INSN_SIZE); |
7d10b47d RS |
4604 | insert_into_history (prev_nop_frag_since, |
4605 | prev_nop_frag_required, NOP_INSN); | |
4606 | prev_nop_frag = NULL; | |
4607 | } | |
252b5132 RH |
4608 | } |
4609 | ||
584892a6 RS |
4610 | /* Set up global variables for the start of a new macro. */ |
4611 | ||
4612 | static void | |
4613 | macro_start (void) | |
4614 | { | |
4615 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
df58fc94 RS |
4616 | memset (&mips_macro_warning.first_insn_sizes, 0, |
4617 | sizeof (mips_macro_warning.first_insn_sizes)); | |
4618 | memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns)); | |
584892a6 | 4619 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder |
11625dd8 | 4620 | && delayed_branch_p (&history[0])); |
df58fc94 RS |
4621 | switch (history[0].insn_mo->pinfo2 |
4622 | & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT)) | |
4623 | { | |
4624 | case INSN2_BRANCH_DELAY_32BIT: | |
4625 | mips_macro_warning.delay_slot_length = 4; | |
4626 | break; | |
4627 | case INSN2_BRANCH_DELAY_16BIT: | |
4628 | mips_macro_warning.delay_slot_length = 2; | |
4629 | break; | |
4630 | default: | |
4631 | mips_macro_warning.delay_slot_length = 0; | |
4632 | break; | |
4633 | } | |
4634 | mips_macro_warning.first_frag = NULL; | |
584892a6 RS |
4635 | } |
4636 | ||
df58fc94 RS |
4637 | /* Given that a macro is longer than one instruction or of the wrong size, |
4638 | return the appropriate warning for it. Return null if no warning is | |
4639 | needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT, | |
4640 | RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND, | |
4641 | and RELAX_NOMACRO. */ | |
584892a6 RS |
4642 | |
4643 | static const char * | |
4644 | macro_warning (relax_substateT subtype) | |
4645 | { | |
4646 | if (subtype & RELAX_DELAY_SLOT) | |
4647 | return _("Macro instruction expanded into multiple instructions" | |
4648 | " in a branch delay slot"); | |
4649 | else if (subtype & RELAX_NOMACRO) | |
4650 | return _("Macro instruction expanded into multiple instructions"); | |
df58fc94 RS |
4651 | else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST |
4652 | | RELAX_DELAY_SLOT_SIZE_SECOND)) | |
4653 | return ((subtype & RELAX_DELAY_SLOT_16BIT) | |
4654 | ? _("Macro instruction expanded into a wrong size instruction" | |
4655 | " in a 16-bit branch delay slot") | |
4656 | : _("Macro instruction expanded into a wrong size instruction" | |
4657 | " in a 32-bit branch delay slot")); | |
584892a6 RS |
4658 | else |
4659 | return 0; | |
4660 | } | |
4661 | ||
4662 | /* Finish up a macro. Emit warnings as appropriate. */ | |
4663 | ||
4664 | static void | |
4665 | macro_end (void) | |
4666 | { | |
df58fc94 RS |
4667 | /* Relaxation warning flags. */ |
4668 | relax_substateT subtype = 0; | |
4669 | ||
4670 | /* Check delay slot size requirements. */ | |
4671 | if (mips_macro_warning.delay_slot_length == 2) | |
4672 | subtype |= RELAX_DELAY_SLOT_16BIT; | |
4673 | if (mips_macro_warning.delay_slot_length != 0) | |
584892a6 | 4674 | { |
df58fc94 RS |
4675 | if (mips_macro_warning.delay_slot_length |
4676 | != mips_macro_warning.first_insn_sizes[0]) | |
4677 | subtype |= RELAX_DELAY_SLOT_SIZE_FIRST; | |
4678 | if (mips_macro_warning.delay_slot_length | |
4679 | != mips_macro_warning.first_insn_sizes[1]) | |
4680 | subtype |= RELAX_DELAY_SLOT_SIZE_SECOND; | |
4681 | } | |
584892a6 | 4682 | |
df58fc94 RS |
4683 | /* Check instruction count requirements. */ |
4684 | if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1) | |
4685 | { | |
4686 | if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0]) | |
584892a6 RS |
4687 | subtype |= RELAX_SECOND_LONGER; |
4688 | if (mips_opts.warn_about_macros) | |
4689 | subtype |= RELAX_NOMACRO; | |
4690 | if (mips_macro_warning.delay_slot_p) | |
4691 | subtype |= RELAX_DELAY_SLOT; | |
df58fc94 | 4692 | } |
584892a6 | 4693 | |
df58fc94 RS |
4694 | /* If both alternatives fail to fill a delay slot correctly, |
4695 | emit the warning now. */ | |
4696 | if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0 | |
4697 | && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0) | |
4698 | { | |
4699 | relax_substateT s; | |
4700 | const char *msg; | |
4701 | ||
4702 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
4703 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
4704 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
4705 | msg = macro_warning (s); | |
4706 | if (msg != NULL) | |
4707 | as_warn ("%s", msg); | |
4708 | subtype &= ~s; | |
4709 | } | |
4710 | ||
4711 | /* If both implementations are longer than 1 instruction, then emit the | |
4712 | warning now. */ | |
4713 | if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1) | |
4714 | { | |
4715 | relax_substateT s; | |
4716 | const char *msg; | |
4717 | ||
4718 | s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT); | |
4719 | msg = macro_warning (s); | |
4720 | if (msg != NULL) | |
4721 | as_warn ("%s", msg); | |
4722 | subtype &= ~s; | |
584892a6 | 4723 | } |
df58fc94 RS |
4724 | |
4725 | /* If any flags still set, then one implementation might need a warning | |
4726 | and the other either will need one of a different kind or none at all. | |
4727 | Pass any remaining flags over to relaxation. */ | |
4728 | if (mips_macro_warning.first_frag != NULL) | |
4729 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
584892a6 RS |
4730 | } |
4731 | ||
df58fc94 RS |
4732 | /* Instruction operand formats used in macros that vary between |
4733 | standard MIPS and microMIPS code. */ | |
4734 | ||
4735 | static const char * const brk_fmt[2] = { "c", "mF" }; | |
4736 | static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" }; | |
4737 | static const char * const jalr_fmt[2] = { "d,s", "t,s" }; | |
4738 | static const char * const lui_fmt[2] = { "t,u", "s,u" }; | |
4739 | static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" }; | |
4740 | static const char * const mfhl_fmt[2] = { "d", "mj" }; | |
4741 | static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" }; | |
4742 | static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" }; | |
4743 | ||
4744 | #define BRK_FMT (brk_fmt[mips_opts.micromips]) | |
4745 | #define COP12_FMT (cop12_fmt[mips_opts.micromips]) | |
4746 | #define JALR_FMT (jalr_fmt[mips_opts.micromips]) | |
4747 | #define LUI_FMT (lui_fmt[mips_opts.micromips]) | |
4748 | #define MEM12_FMT (mem12_fmt[mips_opts.micromips]) | |
4749 | #define MFHL_FMT (mfhl_fmt[mips_opts.micromips]) | |
4750 | #define SHFT_FMT (shft_fmt[mips_opts.micromips]) | |
4751 | #define TRAP_FMT (trap_fmt[mips_opts.micromips]) | |
4752 | ||
6e1304d8 RS |
4753 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
4754 | The first argument in *ARGS will be either the code for a single | |
4755 | relocation or -1 followed by the three codes that make up a | |
4756 | composite relocation. */ | |
4757 | ||
4758 | static void | |
4759 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
4760 | { | |
4761 | int i, next; | |
4762 | ||
4763 | next = va_arg (*args, int); | |
4764 | if (next >= 0) | |
4765 | r[0] = (bfd_reloc_code_real_type) next; | |
4766 | else | |
4767 | for (i = 0; i < 3; i++) | |
4768 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
4769 | } | |
4770 | ||
252b5132 RH |
4771 | /* Build an instruction created by a macro expansion. This is passed |
4772 | a pointer to the count of instructions created so far, an | |
4773 | expression, the name of the instruction to build, an operand format | |
4774 | string, and corresponding arguments. */ | |
4775 | ||
252b5132 | 4776 | static void |
67c0d1eb | 4777 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 | 4778 | { |
df58fc94 | 4779 | const struct mips_opcode *mo = NULL; |
f6688943 | 4780 | bfd_reloc_code_real_type r[3]; |
df58fc94 RS |
4781 | const struct mips_opcode *amo; |
4782 | struct hash_control *hash; | |
4783 | struct mips_cl_insn insn; | |
252b5132 | 4784 | va_list args; |
252b5132 | 4785 | |
252b5132 | 4786 | va_start (args, fmt); |
252b5132 | 4787 | |
252b5132 RH |
4788 | if (mips_opts.mips16) |
4789 | { | |
03ea81db | 4790 | mips16_macro_build (ep, name, fmt, &args); |
252b5132 RH |
4791 | va_end (args); |
4792 | return; | |
4793 | } | |
4794 | ||
f6688943 TS |
4795 | r[0] = BFD_RELOC_UNUSED; |
4796 | r[1] = BFD_RELOC_UNUSED; | |
4797 | r[2] = BFD_RELOC_UNUSED; | |
df58fc94 RS |
4798 | hash = mips_opts.micromips ? micromips_op_hash : op_hash; |
4799 | amo = (struct mips_opcode *) hash_find (hash, name); | |
4800 | gas_assert (amo); | |
4801 | gas_assert (strcmp (name, amo->name) == 0); | |
1e915849 | 4802 | |
df58fc94 | 4803 | do |
8b082fb1 TS |
4804 | { |
4805 | /* Search until we get a match for NAME. It is assumed here that | |
df58fc94 RS |
4806 | macros will never generate MDMX, MIPS-3D, or MT instructions. |
4807 | We try to match an instruction that fulfils the branch delay | |
4808 | slot instruction length requirement (if any) of the previous | |
4809 | instruction. While doing this we record the first instruction | |
4810 | seen that matches all the other conditions and use it anyway | |
4811 | if the requirement cannot be met; we will issue an appropriate | |
4812 | warning later on. */ | |
4813 | if (strcmp (fmt, amo->args) == 0 | |
4814 | && amo->pinfo != INSN_MACRO | |
4815 | && is_opcode_valid (amo) | |
4816 | && is_size_valid (amo)) | |
4817 | { | |
4818 | if (is_delay_slot_valid (amo)) | |
4819 | { | |
4820 | mo = amo; | |
4821 | break; | |
4822 | } | |
4823 | else if (!mo) | |
4824 | mo = amo; | |
4825 | } | |
8b082fb1 | 4826 | |
df58fc94 RS |
4827 | ++amo; |
4828 | gas_assert (amo->name); | |
252b5132 | 4829 | } |
df58fc94 | 4830 | while (strcmp (name, amo->name) == 0); |
252b5132 | 4831 | |
df58fc94 | 4832 | gas_assert (mo); |
1e915849 | 4833 | create_insn (&insn, mo); |
252b5132 RH |
4834 | for (;;) |
4835 | { | |
4836 | switch (*fmt++) | |
4837 | { | |
4838 | case '\0': | |
4839 | break; | |
4840 | ||
4841 | case ',': | |
4842 | case '(': | |
4843 | case ')': | |
4844 | continue; | |
4845 | ||
5f74bc13 CD |
4846 | case '+': |
4847 | switch (*fmt++) | |
4848 | { | |
4849 | case 'A': | |
4850 | case 'E': | |
df58fc94 RS |
4851 | INSERT_OPERAND (mips_opts.micromips, |
4852 | EXTLSB, insn, va_arg (args, int)); | |
5f74bc13 CD |
4853 | continue; |
4854 | ||
4855 | case 'B': | |
4856 | case 'F': | |
4857 | /* Note that in the macro case, these arguments are already | |
4858 | in MSB form. (When handling the instruction in the | |
4859 | non-macro case, these arguments are sizes from which | |
4860 | MSB values must be calculated.) */ | |
df58fc94 RS |
4861 | INSERT_OPERAND (mips_opts.micromips, |
4862 | INSMSB, insn, va_arg (args, int)); | |
5f74bc13 CD |
4863 | continue; |
4864 | ||
4865 | case 'C': | |
4866 | case 'G': | |
4867 | case 'H': | |
4868 | /* Note that in the macro case, these arguments are already | |
4869 | in MSBD form. (When handling the instruction in the | |
4870 | non-macro case, these arguments are sizes from which | |
4871 | MSBD values must be calculated.) */ | |
df58fc94 RS |
4872 | INSERT_OPERAND (mips_opts.micromips, |
4873 | EXTMSBD, insn, va_arg (args, int)); | |
5f74bc13 CD |
4874 | continue; |
4875 | ||
dd3cbb7e | 4876 | case 'Q': |
df58fc94 RS |
4877 | gas_assert (!mips_opts.micromips); |
4878 | INSERT_OPERAND (0, SEQI, insn, va_arg (args, int)); | |
dd3cbb7e NC |
4879 | continue; |
4880 | ||
5f74bc13 CD |
4881 | default: |
4882 | internalError (); | |
4883 | } | |
4884 | continue; | |
4885 | ||
8b082fb1 | 4886 | case '2': |
df58fc94 RS |
4887 | gas_assert (!mips_opts.micromips); |
4888 | INSERT_OPERAND (0, BP, insn, va_arg (args, int)); | |
8b082fb1 TS |
4889 | continue; |
4890 | ||
df58fc94 RS |
4891 | case 'n': |
4892 | gas_assert (mips_opts.micromips); | |
252b5132 RH |
4893 | case 't': |
4894 | case 'w': | |
4895 | case 'E': | |
df58fc94 | 4896 | INSERT_OPERAND (mips_opts.micromips, RT, insn, va_arg (args, int)); |
252b5132 RH |
4897 | continue; |
4898 | ||
4899 | case 'c': | |
df58fc94 RS |
4900 | gas_assert (!mips_opts.micromips); |
4901 | INSERT_OPERAND (0, CODE, insn, va_arg (args, int)); | |
38487616 TS |
4902 | continue; |
4903 | ||
252b5132 | 4904 | case 'W': |
df58fc94 RS |
4905 | gas_assert (!mips_opts.micromips); |
4906 | case 'T': | |
4907 | INSERT_OPERAND (mips_opts.micromips, FT, insn, va_arg (args, int)); | |
252b5132 RH |
4908 | continue; |
4909 | ||
252b5132 | 4910 | case 'G': |
df58fc94 RS |
4911 | if (mips_opts.micromips) |
4912 | INSERT_OPERAND (1, RS, insn, va_arg (args, int)); | |
4913 | else | |
4914 | INSERT_OPERAND (0, RD, insn, va_arg (args, int)); | |
4915 | continue; | |
4916 | ||
af7ee8bf | 4917 | case 'K': |
df58fc94 RS |
4918 | gas_assert (!mips_opts.micromips); |
4919 | case 'd': | |
4920 | INSERT_OPERAND (mips_opts.micromips, RD, insn, va_arg (args, int)); | |
252b5132 RH |
4921 | continue; |
4922 | ||
4372b673 | 4923 | case 'U': |
df58fc94 | 4924 | gas_assert (!mips_opts.micromips); |
4372b673 NC |
4925 | { |
4926 | int tmp = va_arg (args, int); | |
4927 | ||
df58fc94 RS |
4928 | INSERT_OPERAND (0, RT, insn, tmp); |
4929 | INSERT_OPERAND (0, RD, insn, tmp); | |
4372b673 | 4930 | } |
df58fc94 | 4931 | continue; |
4372b673 | 4932 | |
252b5132 RH |
4933 | case 'V': |
4934 | case 'S': | |
df58fc94 RS |
4935 | gas_assert (!mips_opts.micromips); |
4936 | INSERT_OPERAND (0, FS, insn, va_arg (args, int)); | |
252b5132 RH |
4937 | continue; |
4938 | ||
4939 | case 'z': | |
4940 | continue; | |
4941 | ||
4942 | case '<': | |
df58fc94 RS |
4943 | INSERT_OPERAND (mips_opts.micromips, |
4944 | SHAMT, insn, va_arg (args, int)); | |
252b5132 RH |
4945 | continue; |
4946 | ||
4947 | case 'D': | |
df58fc94 RS |
4948 | gas_assert (!mips_opts.micromips); |
4949 | INSERT_OPERAND (0, FD, insn, va_arg (args, int)); | |
252b5132 RH |
4950 | continue; |
4951 | ||
4952 | case 'B': | |
df58fc94 RS |
4953 | gas_assert (!mips_opts.micromips); |
4954 | INSERT_OPERAND (0, CODE20, insn, va_arg (args, int)); | |
252b5132 RH |
4955 | continue; |
4956 | ||
4372b673 | 4957 | case 'J': |
df58fc94 RS |
4958 | gas_assert (!mips_opts.micromips); |
4959 | INSERT_OPERAND (0, CODE19, insn, va_arg (args, int)); | |
4372b673 NC |
4960 | continue; |
4961 | ||
252b5132 | 4962 | case 'q': |
df58fc94 RS |
4963 | gas_assert (!mips_opts.micromips); |
4964 | INSERT_OPERAND (0, CODE2, insn, va_arg (args, int)); | |
252b5132 RH |
4965 | continue; |
4966 | ||
4967 | case 'b': | |
4968 | case 's': | |
4969 | case 'r': | |
4970 | case 'v': | |
df58fc94 | 4971 | INSERT_OPERAND (mips_opts.micromips, RS, insn, va_arg (args, int)); |
252b5132 RH |
4972 | continue; |
4973 | ||
4974 | case 'i': | |
4975 | case 'j': | |
6e1304d8 | 4976 | macro_read_relocs (&args, r); |
9c2799c2 | 4977 | gas_assert (*r == BFD_RELOC_GPREL16 |
e391c024 RS |
4978 | || *r == BFD_RELOC_MIPS_HIGHER |
4979 | || *r == BFD_RELOC_HI16_S | |
4980 | || *r == BFD_RELOC_LO16 | |
4981 | || *r == BFD_RELOC_MIPS_GOT_OFST); | |
4982 | continue; | |
4983 | ||
4984 | case 'o': | |
4985 | macro_read_relocs (&args, r); | |
252b5132 RH |
4986 | continue; |
4987 | ||
4988 | case 'u': | |
6e1304d8 | 4989 | macro_read_relocs (&args, r); |
9c2799c2 | 4990 | gas_assert (ep != NULL |
90ecf173 MR |
4991 | && (ep->X_op == O_constant |
4992 | || (ep->X_op == O_symbol | |
4993 | && (*r == BFD_RELOC_MIPS_HIGHEST | |
4994 | || *r == BFD_RELOC_HI16_S | |
4995 | || *r == BFD_RELOC_HI16 | |
4996 | || *r == BFD_RELOC_GPREL16 | |
4997 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
4998 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); | |
252b5132 RH |
4999 | continue; |
5000 | ||
5001 | case 'p': | |
9c2799c2 | 5002 | gas_assert (ep != NULL); |
bad36eac | 5003 | |
252b5132 RH |
5004 | /* |
5005 | * This allows macro() to pass an immediate expression for | |
5006 | * creating short branches without creating a symbol. | |
bad36eac DJ |
5007 | * |
5008 | * We don't allow branch relaxation for these branches, as | |
5009 | * they should only appear in ".set nomacro" anyway. | |
252b5132 RH |
5010 | */ |
5011 | if (ep->X_op == O_constant) | |
5012 | { | |
df58fc94 RS |
5013 | /* For microMIPS we always use relocations for branches. |
5014 | So we should not resolve immediate values. */ | |
5015 | gas_assert (!mips_opts.micromips); | |
5016 | ||
bad36eac DJ |
5017 | if ((ep->X_add_number & 3) != 0) |
5018 | as_bad (_("branch to misaligned address (0x%lx)"), | |
5019 | (unsigned long) ep->X_add_number); | |
5020 | if ((ep->X_add_number + 0x20000) & ~0x3ffff) | |
5021 | as_bad (_("branch address range overflow (0x%lx)"), | |
5022 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
5023 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; |
5024 | ep = NULL; | |
5025 | } | |
5026 | else | |
0b25d3e6 | 5027 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
5028 | continue; |
5029 | ||
5030 | case 'a': | |
9c2799c2 | 5031 | gas_assert (ep != NULL); |
f6688943 | 5032 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
5033 | continue; |
5034 | ||
5035 | case 'C': | |
df58fc94 RS |
5036 | gas_assert (!mips_opts.micromips); |
5037 | INSERT_OPERAND (0, COPZ, insn, va_arg (args, unsigned long)); | |
252b5132 RH |
5038 | continue; |
5039 | ||
d43b4baf | 5040 | case 'k': |
df58fc94 RS |
5041 | INSERT_OPERAND (mips_opts.micromips, |
5042 | CACHE, insn, va_arg (args, unsigned long)); | |
5043 | continue; | |
5044 | ||
5045 | case '|': | |
5046 | gas_assert (mips_opts.micromips); | |
5047 | INSERT_OPERAND (1, TRAP, insn, va_arg (args, int)); | |
5048 | continue; | |
5049 | ||
5050 | case '.': | |
5051 | gas_assert (mips_opts.micromips); | |
5052 | INSERT_OPERAND (1, OFFSET10, insn, va_arg (args, int)); | |
5053 | continue; | |
5054 | ||
dec0624d MR |
5055 | case '\\': |
5056 | INSERT_OPERAND (mips_opts.micromips, | |
5057 | 3BITPOS, insn, va_arg (args, unsigned int)); | |
5058 | continue; | |
5059 | ||
df58fc94 | 5060 | case '~': |
dec0624d MR |
5061 | INSERT_OPERAND (mips_opts.micromips, |
5062 | OFFSET12, insn, va_arg (args, unsigned long)); | |
df58fc94 RS |
5063 | continue; |
5064 | ||
5065 | case 'N': | |
5066 | gas_assert (mips_opts.micromips); | |
5067 | INSERT_OPERAND (1, BCC, insn, va_arg (args, int)); | |
5068 | continue; | |
5069 | ||
5070 | case 'm': /* Opcode extension character. */ | |
5071 | gas_assert (mips_opts.micromips); | |
5072 | switch (*fmt++) | |
5073 | { | |
5074 | case 'j': | |
5075 | INSERT_OPERAND (1, MJ, insn, va_arg (args, int)); | |
5076 | break; | |
5077 | ||
5078 | case 'p': | |
5079 | INSERT_OPERAND (1, MP, insn, va_arg (args, int)); | |
5080 | break; | |
5081 | ||
5082 | case 'F': | |
5083 | INSERT_OPERAND (1, IMMF, insn, va_arg (args, int)); | |
5084 | break; | |
5085 | ||
5086 | default: | |
5087 | internalError (); | |
5088 | } | |
d43b4baf TS |
5089 | continue; |
5090 | ||
252b5132 RH |
5091 | default: |
5092 | internalError (); | |
5093 | } | |
5094 | break; | |
5095 | } | |
5096 | va_end (args); | |
9c2799c2 | 5097 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 5098 | |
df58fc94 | 5099 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
5100 | } |
5101 | ||
5102 | static void | |
67c0d1eb | 5103 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
03ea81db | 5104 | va_list *args) |
252b5132 | 5105 | { |
1e915849 | 5106 | struct mips_opcode *mo; |
252b5132 | 5107 | struct mips_cl_insn insn; |
f6688943 TS |
5108 | bfd_reloc_code_real_type r[3] |
5109 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 5110 | |
1e915849 | 5111 | mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
9c2799c2 NC |
5112 | gas_assert (mo); |
5113 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 | 5114 | |
1e915849 | 5115 | while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) |
252b5132 | 5116 | { |
1e915849 | 5117 | ++mo; |
9c2799c2 NC |
5118 | gas_assert (mo->name); |
5119 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
5120 | } |
5121 | ||
1e915849 | 5122 | create_insn (&insn, mo); |
252b5132 RH |
5123 | for (;;) |
5124 | { | |
5125 | int c; | |
5126 | ||
5127 | c = *fmt++; | |
5128 | switch (c) | |
5129 | { | |
5130 | case '\0': | |
5131 | break; | |
5132 | ||
5133 | case ',': | |
5134 | case '(': | |
5135 | case ')': | |
5136 | continue; | |
5137 | ||
5138 | case 'y': | |
5139 | case 'w': | |
03ea81db | 5140 | MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int)); |
252b5132 RH |
5141 | continue; |
5142 | ||
5143 | case 'x': | |
5144 | case 'v': | |
03ea81db | 5145 | MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int)); |
252b5132 RH |
5146 | continue; |
5147 | ||
5148 | case 'z': | |
03ea81db | 5149 | MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int)); |
252b5132 RH |
5150 | continue; |
5151 | ||
5152 | case 'Z': | |
03ea81db | 5153 | MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int)); |
252b5132 RH |
5154 | continue; |
5155 | ||
5156 | case '0': | |
5157 | case 'S': | |
5158 | case 'P': | |
5159 | case 'R': | |
5160 | continue; | |
5161 | ||
5162 | case 'X': | |
03ea81db | 5163 | MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int)); |
252b5132 RH |
5164 | continue; |
5165 | ||
5166 | case 'Y': | |
5167 | { | |
5168 | int regno; | |
5169 | ||
03ea81db | 5170 | regno = va_arg (*args, int); |
252b5132 | 5171 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); |
a9e24354 | 5172 | MIPS16_INSERT_OPERAND (REG32R, insn, regno); |
252b5132 RH |
5173 | } |
5174 | continue; | |
5175 | ||
5176 | case '<': | |
5177 | case '>': | |
5178 | case '4': | |
5179 | case '5': | |
5180 | case 'H': | |
5181 | case 'W': | |
5182 | case 'D': | |
5183 | case 'j': | |
5184 | case '8': | |
5185 | case 'V': | |
5186 | case 'C': | |
5187 | case 'U': | |
5188 | case 'k': | |
5189 | case 'K': | |
5190 | case 'p': | |
5191 | case 'q': | |
5192 | { | |
9c2799c2 | 5193 | gas_assert (ep != NULL); |
252b5132 RH |
5194 | |
5195 | if (ep->X_op != O_constant) | |
874e8986 | 5196 | *r = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
5197 | else |
5198 | { | |
b34976b6 AM |
5199 | mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE, |
5200 | FALSE, &insn.insn_opcode, &insn.use_extend, | |
c4e7957c | 5201 | &insn.extend); |
252b5132 | 5202 | ep = NULL; |
f6688943 | 5203 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
5204 | } |
5205 | } | |
5206 | continue; | |
5207 | ||
5208 | case '6': | |
03ea81db | 5209 | MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int)); |
252b5132 RH |
5210 | continue; |
5211 | } | |
5212 | ||
5213 | break; | |
5214 | } | |
5215 | ||
9c2799c2 | 5216 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 5217 | |
df58fc94 | 5218 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
5219 | } |
5220 | ||
2051e8c4 MR |
5221 | /* |
5222 | * Sign-extend 32-bit mode constants that have bit 31 set and all | |
5223 | * higher bits unset. | |
5224 | */ | |
9f872bbe | 5225 | static void |
2051e8c4 MR |
5226 | normalize_constant_expr (expressionS *ex) |
5227 | { | |
9ee2a2d4 | 5228 | if (ex->X_op == O_constant |
2051e8c4 MR |
5229 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) |
5230 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
5231 | - 0x80000000); | |
5232 | } | |
5233 | ||
5234 | /* | |
5235 | * Sign-extend 32-bit mode address offsets that have bit 31 set and | |
5236 | * all higher bits unset. | |
5237 | */ | |
5238 | static void | |
5239 | normalize_address_expr (expressionS *ex) | |
5240 | { | |
5241 | if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) | |
5242 | || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) | |
5243 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
5244 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
5245 | - 0x80000000); | |
5246 | } | |
5247 | ||
438c16b8 TS |
5248 | /* |
5249 | * Generate a "jalr" instruction with a relocation hint to the called | |
5250 | * function. This occurs in NewABI PIC code. | |
5251 | */ | |
5252 | static void | |
df58fc94 | 5253 | macro_build_jalr (expressionS *ep, int cprestore) |
438c16b8 | 5254 | { |
df58fc94 RS |
5255 | static const bfd_reloc_code_real_type jalr_relocs[2] |
5256 | = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR }; | |
5257 | bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips]; | |
5258 | const char *jalr; | |
685736be | 5259 | char *f = NULL; |
b34976b6 | 5260 | |
1180b5a4 | 5261 | if (MIPS_JALR_HINT_P (ep)) |
f21f8242 | 5262 | { |
cc3d92a5 | 5263 | frag_grow (8); |
f21f8242 AO |
5264 | f = frag_more (0); |
5265 | } | |
df58fc94 RS |
5266 | if (!mips_opts.micromips) |
5267 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); | |
5268 | else | |
5269 | { | |
5270 | jalr = mips_opts.noreorder && !cprestore ? "jalr" : "jalrs"; | |
5271 | if (MIPS_JALR_HINT_P (ep)) | |
5272 | macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG); | |
5273 | else | |
5274 | macro_build (NULL, jalr, "mj", PIC_CALL_REG); | |
5275 | } | |
1180b5a4 | 5276 | if (MIPS_JALR_HINT_P (ep)) |
df58fc94 | 5277 | fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc); |
438c16b8 TS |
5278 | } |
5279 | ||
252b5132 RH |
5280 | /* |
5281 | * Generate a "lui" instruction. | |
5282 | */ | |
5283 | static void | |
67c0d1eb | 5284 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 | 5285 | { |
9c2799c2 | 5286 | gas_assert (! mips_opts.mips16); |
252b5132 | 5287 | |
df58fc94 | 5288 | if (ep->X_op != O_constant) |
252b5132 | 5289 | { |
9c2799c2 | 5290 | gas_assert (ep->X_op == O_symbol); |
bbe506e8 TS |
5291 | /* _gp_disp is a special case, used from s_cpload. |
5292 | __gnu_local_gp is used if mips_no_shared. */ | |
9c2799c2 | 5293 | gas_assert (mips_pic == NO_PIC |
78e1bb40 | 5294 | || (! HAVE_NEWABI |
aa6975fb ILT |
5295 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
5296 | || (! mips_in_shared | |
bbe506e8 TS |
5297 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
5298 | "__gnu_local_gp") == 0)); | |
252b5132 RH |
5299 | } |
5300 | ||
df58fc94 | 5301 | macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S); |
252b5132 RH |
5302 | } |
5303 | ||
885add95 CD |
5304 | /* Generate a sequence of instructions to do a load or store from a constant |
5305 | offset off of a base register (breg) into/from a target register (treg), | |
5306 | using AT if necessary. */ | |
5307 | static void | |
67c0d1eb RS |
5308 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
5309 | int treg, int breg, int dbl) | |
885add95 | 5310 | { |
9c2799c2 | 5311 | gas_assert (ep->X_op == O_constant); |
885add95 | 5312 | |
256ab948 | 5313 | /* Sign-extending 32-bit constants makes their handling easier. */ |
2051e8c4 MR |
5314 | if (!dbl) |
5315 | normalize_constant_expr (ep); | |
256ab948 | 5316 | |
67c1ffbe | 5317 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 5318 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
5319 | as_warn (_("operand overflow")); |
5320 | ||
5321 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
5322 | { | |
5323 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 5324 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
5325 | } |
5326 | else | |
5327 | { | |
5328 | /* 32-bit offset, need multiple instructions and AT, like: | |
5329 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
5330 | addu $tempreg,$tempreg,$breg | |
5331 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
5332 | to handle the complete offset. */ | |
67c0d1eb RS |
5333 | macro_build_lui (ep, AT); |
5334 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
5335 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 | 5336 | |
741fe287 | 5337 | if (!mips_opts.at) |
8fc2e39e | 5338 | as_bad (_("Macro used $at after \".set noat\"")); |
885add95 CD |
5339 | } |
5340 | } | |
5341 | ||
252b5132 RH |
5342 | /* set_at() |
5343 | * Generates code to set the $at register to true (one) | |
5344 | * if reg is less than the immediate expression. | |
5345 | */ | |
5346 | static void | |
67c0d1eb | 5347 | set_at (int reg, int unsignedp) |
252b5132 RH |
5348 | { |
5349 | if (imm_expr.X_op == O_constant | |
5350 | && imm_expr.X_add_number >= -0x8000 | |
5351 | && imm_expr.X_add_number < 0x8000) | |
67c0d1eb RS |
5352 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
5353 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
5354 | else |
5355 | { | |
67c0d1eb RS |
5356 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
5357 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); | |
252b5132 RH |
5358 | } |
5359 | } | |
5360 | ||
5361 | /* Warn if an expression is not a constant. */ | |
5362 | ||
5363 | static void | |
17a2f251 | 5364 | check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) |
252b5132 RH |
5365 | { |
5366 | if (ex->X_op == O_big) | |
5367 | as_bad (_("unsupported large constant")); | |
5368 | else if (ex->X_op != O_constant) | |
9ee2a2d4 MR |
5369 | as_bad (_("Instruction %s requires absolute expression"), |
5370 | ip->insn_mo->name); | |
13757d0c | 5371 | |
9ee2a2d4 MR |
5372 | if (HAVE_32BIT_GPRS) |
5373 | normalize_constant_expr (ex); | |
252b5132 RH |
5374 | } |
5375 | ||
5376 | /* Count the leading zeroes by performing a binary chop. This is a | |
5377 | bulky bit of source, but performance is a LOT better for the | |
5378 | majority of values than a simple loop to count the bits: | |
5379 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
5380 | if ((v) & (1 << (31 - lcnt))) | |
5381 | break; | |
5382 | However it is not code size friendly, and the gain will drop a bit | |
5383 | on certain cached systems. | |
5384 | */ | |
5385 | #define COUNT_TOP_ZEROES(v) \ | |
5386 | (((v) & ~0xffff) == 0 \ | |
5387 | ? ((v) & ~0xff) == 0 \ | |
5388 | ? ((v) & ~0xf) == 0 \ | |
5389 | ? ((v) & ~0x3) == 0 \ | |
5390 | ? ((v) & ~0x1) == 0 \ | |
5391 | ? !(v) \ | |
5392 | ? 32 \ | |
5393 | : 31 \ | |
5394 | : 30 \ | |
5395 | : ((v) & ~0x7) == 0 \ | |
5396 | ? 29 \ | |
5397 | : 28 \ | |
5398 | : ((v) & ~0x3f) == 0 \ | |
5399 | ? ((v) & ~0x1f) == 0 \ | |
5400 | ? 27 \ | |
5401 | : 26 \ | |
5402 | : ((v) & ~0x7f) == 0 \ | |
5403 | ? 25 \ | |
5404 | : 24 \ | |
5405 | : ((v) & ~0xfff) == 0 \ | |
5406 | ? ((v) & ~0x3ff) == 0 \ | |
5407 | ? ((v) & ~0x1ff) == 0 \ | |
5408 | ? 23 \ | |
5409 | : 22 \ | |
5410 | : ((v) & ~0x7ff) == 0 \ | |
5411 | ? 21 \ | |
5412 | : 20 \ | |
5413 | : ((v) & ~0x3fff) == 0 \ | |
5414 | ? ((v) & ~0x1fff) == 0 \ | |
5415 | ? 19 \ | |
5416 | : 18 \ | |
5417 | : ((v) & ~0x7fff) == 0 \ | |
5418 | ? 17 \ | |
5419 | : 16 \ | |
5420 | : ((v) & ~0xffffff) == 0 \ | |
5421 | ? ((v) & ~0xfffff) == 0 \ | |
5422 | ? ((v) & ~0x3ffff) == 0 \ | |
5423 | ? ((v) & ~0x1ffff) == 0 \ | |
5424 | ? 15 \ | |
5425 | : 14 \ | |
5426 | : ((v) & ~0x7ffff) == 0 \ | |
5427 | ? 13 \ | |
5428 | : 12 \ | |
5429 | : ((v) & ~0x3fffff) == 0 \ | |
5430 | ? ((v) & ~0x1fffff) == 0 \ | |
5431 | ? 11 \ | |
5432 | : 10 \ | |
5433 | : ((v) & ~0x7fffff) == 0 \ | |
5434 | ? 9 \ | |
5435 | : 8 \ | |
5436 | : ((v) & ~0xfffffff) == 0 \ | |
5437 | ? ((v) & ~0x3ffffff) == 0 \ | |
5438 | ? ((v) & ~0x1ffffff) == 0 \ | |
5439 | ? 7 \ | |
5440 | : 6 \ | |
5441 | : ((v) & ~0x7ffffff) == 0 \ | |
5442 | ? 5 \ | |
5443 | : 4 \ | |
5444 | : ((v) & ~0x3fffffff) == 0 \ | |
5445 | ? ((v) & ~0x1fffffff) == 0 \ | |
5446 | ? 3 \ | |
5447 | : 2 \ | |
5448 | : ((v) & ~0x7fffffff) == 0 \ | |
5449 | ? 1 \ | |
5450 | : 0) | |
5451 | ||
5452 | /* load_register() | |
67c1ffbe | 5453 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
5454 | * an absolute expression value into a register. |
5455 | */ | |
5456 | static void | |
67c0d1eb | 5457 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
5458 | { |
5459 | int freg; | |
5460 | expressionS hi32, lo32; | |
5461 | ||
5462 | if (ep->X_op != O_big) | |
5463 | { | |
9c2799c2 | 5464 | gas_assert (ep->X_op == O_constant); |
256ab948 TS |
5465 | |
5466 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
2051e8c4 MR |
5467 | if (!dbl) |
5468 | normalize_constant_expr (ep); | |
256ab948 TS |
5469 | |
5470 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
5471 | { |
5472 | /* We can handle 16 bit signed values with an addiu to | |
5473 | $zero. No need to ever use daddiu here, since $zero and | |
5474 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 5475 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
5476 | return; |
5477 | } | |
5478 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
5479 | { | |
5480 | /* We can handle 16 bit unsigned values with an ori to | |
5481 | $zero. */ | |
67c0d1eb | 5482 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
5483 | return; |
5484 | } | |
256ab948 | 5485 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
5486 | { |
5487 | /* 32 bit values require an lui. */ | |
df58fc94 | 5488 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 5489 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 5490 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
5491 | return; |
5492 | } | |
5493 | } | |
5494 | ||
5495 | /* The value is larger than 32 bits. */ | |
5496 | ||
2051e8c4 | 5497 | if (!dbl || HAVE_32BIT_GPRS) |
252b5132 | 5498 | { |
55e08f71 NC |
5499 | char value[32]; |
5500 | ||
5501 | sprintf_vma (value, ep->X_add_number); | |
20e1fcfd | 5502 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
67c0d1eb | 5503 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
5504 | return; |
5505 | } | |
5506 | ||
5507 | if (ep->X_op != O_big) | |
5508 | { | |
5509 | hi32 = *ep; | |
5510 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
5511 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
5512 | hi32.X_add_number &= 0xffffffff; | |
5513 | lo32 = *ep; | |
5514 | lo32.X_add_number &= 0xffffffff; | |
5515 | } | |
5516 | else | |
5517 | { | |
9c2799c2 | 5518 | gas_assert (ep->X_add_number > 2); |
252b5132 RH |
5519 | if (ep->X_add_number == 3) |
5520 | generic_bignum[3] = 0; | |
5521 | else if (ep->X_add_number > 4) | |
5522 | as_bad (_("Number larger than 64 bits")); | |
5523 | lo32.X_op = O_constant; | |
5524 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
5525 | hi32.X_op = O_constant; | |
5526 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
5527 | } | |
5528 | ||
5529 | if (hi32.X_add_number == 0) | |
5530 | freg = 0; | |
5531 | else | |
5532 | { | |
5533 | int shift, bit; | |
5534 | unsigned long hi, lo; | |
5535 | ||
956cd1d6 | 5536 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
5537 | { |
5538 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
5539 | { | |
67c0d1eb | 5540 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
5541 | return; |
5542 | } | |
5543 | if (lo32.X_add_number & 0x80000000) | |
5544 | { | |
df58fc94 | 5545 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 5546 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 5547 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
5548 | return; |
5549 | } | |
5550 | } | |
252b5132 RH |
5551 | |
5552 | /* Check for 16bit shifted constant. We know that hi32 is | |
5553 | non-zero, so start the mask on the first bit of the hi32 | |
5554 | value. */ | |
5555 | shift = 17; | |
5556 | do | |
beae10d5 KH |
5557 | { |
5558 | unsigned long himask, lomask; | |
5559 | ||
5560 | if (shift < 32) | |
5561 | { | |
5562 | himask = 0xffff >> (32 - shift); | |
5563 | lomask = (0xffff << shift) & 0xffffffff; | |
5564 | } | |
5565 | else | |
5566 | { | |
5567 | himask = 0xffff << (shift - 32); | |
5568 | lomask = 0; | |
5569 | } | |
5570 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
5571 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
5572 | { | |
5573 | expressionS tmp; | |
5574 | ||
5575 | tmp.X_op = O_constant; | |
5576 | if (shift < 32) | |
5577 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
5578 | | (lo32.X_add_number >> shift)); | |
5579 | else | |
5580 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb | 5581 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
df58fc94 | 5582 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 5583 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
5584 | return; |
5585 | } | |
f9419b05 | 5586 | ++shift; |
beae10d5 KH |
5587 | } |
5588 | while (shift <= (64 - 16)); | |
252b5132 RH |
5589 | |
5590 | /* Find the bit number of the lowest one bit, and store the | |
5591 | shifted value in hi/lo. */ | |
5592 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
5593 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
5594 | if (lo != 0) | |
5595 | { | |
5596 | bit = 0; | |
5597 | while ((lo & 1) == 0) | |
5598 | { | |
5599 | lo >>= 1; | |
5600 | ++bit; | |
5601 | } | |
5602 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
5603 | hi >>= bit; | |
5604 | } | |
5605 | else | |
5606 | { | |
5607 | bit = 32; | |
5608 | while ((hi & 1) == 0) | |
5609 | { | |
5610 | hi >>= 1; | |
5611 | ++bit; | |
5612 | } | |
5613 | lo = hi; | |
5614 | hi = 0; | |
5615 | } | |
5616 | ||
5617 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
5618 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
5619 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
5620 | { |
5621 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 5622 | if (shift != 0) |
beae10d5 | 5623 | { |
252b5132 RH |
5624 | expressionS tmp; |
5625 | ||
5626 | /* This instruction will set the register to be all | |
5627 | ones. */ | |
beae10d5 KH |
5628 | tmp.X_op = O_constant; |
5629 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 5630 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
5631 | if (bit != 0) |
5632 | { | |
5633 | bit += shift; | |
df58fc94 | 5634 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 5635 | reg, reg, (bit >= 32) ? bit - 32 : bit); |
beae10d5 | 5636 | } |
df58fc94 | 5637 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT, |
67c0d1eb | 5638 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
5639 | return; |
5640 | } | |
5641 | } | |
252b5132 RH |
5642 | |
5643 | /* Sign extend hi32 before calling load_register, because we can | |
5644 | generally get better code when we load a sign extended value. */ | |
5645 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 5646 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 5647 | load_register (reg, &hi32, 0); |
252b5132 RH |
5648 | freg = reg; |
5649 | } | |
5650 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
5651 | { | |
5652 | if (freg != 0) | |
5653 | { | |
df58fc94 | 5654 | macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0); |
252b5132 RH |
5655 | freg = reg; |
5656 | } | |
5657 | } | |
5658 | else | |
5659 | { | |
5660 | expressionS mid16; | |
5661 | ||
956cd1d6 | 5662 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 5663 | { |
df58fc94 RS |
5664 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
5665 | macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0); | |
beae10d5 KH |
5666 | return; |
5667 | } | |
252b5132 RH |
5668 | |
5669 | if (freg != 0) | |
5670 | { | |
df58fc94 | 5671 | macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16); |
252b5132 RH |
5672 | freg = reg; |
5673 | } | |
5674 | mid16 = lo32; | |
5675 | mid16.X_add_number >>= 16; | |
67c0d1eb | 5676 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
df58fc94 | 5677 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
252b5132 RH |
5678 | freg = reg; |
5679 | } | |
5680 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 5681 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
5682 | } |
5683 | ||
269137b2 TS |
5684 | static inline void |
5685 | load_delay_nop (void) | |
5686 | { | |
5687 | if (!gpr_interlocks) | |
5688 | macro_build (NULL, "nop", ""); | |
5689 | } | |
5690 | ||
252b5132 RH |
5691 | /* Load an address into a register. */ |
5692 | ||
5693 | static void | |
67c0d1eb | 5694 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 5695 | { |
252b5132 RH |
5696 | if (ep->X_op != O_constant |
5697 | && ep->X_op != O_symbol) | |
5698 | { | |
5699 | as_bad (_("expression too complex")); | |
5700 | ep->X_op = O_constant; | |
5701 | } | |
5702 | ||
5703 | if (ep->X_op == O_constant) | |
5704 | { | |
67c0d1eb | 5705 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
5706 | return; |
5707 | } | |
5708 | ||
5709 | if (mips_pic == NO_PIC) | |
5710 | { | |
5711 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 5712 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
5713 | Otherwise we want |
5714 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
5715 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 5716 | If we have an addend, we always use the latter form. |
76b3015f | 5717 | |
d6bc6245 TS |
5718 | With 64bit address space and a usable $at we want |
5719 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5720 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5721 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5722 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
5723 | dsll32 $reg,0 | |
3a482fd5 | 5724 | daddu $reg,$reg,$at |
76b3015f | 5725 | |
c03099e6 | 5726 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
5727 | on superscalar processors. |
5728 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5729 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5730 | dsll $reg,16 | |
5731 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
5732 | dsll $reg,16 | |
5733 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
6caf9ef4 TS |
5734 | |
5735 | For GP relative symbols in 64bit address space we can use | |
5736 | the same sequence as in 32bit address space. */ | |
aed1a261 | 5737 | if (HAVE_64BIT_SYMBOLS) |
d6bc6245 | 5738 | { |
6caf9ef4 TS |
5739 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
5740 | && !nopic_need_relax (ep->X_add_symbol, 1)) | |
5741 | { | |
5742 | relax_start (ep->X_add_symbol); | |
5743 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
5744 | mips_gp_register, BFD_RELOC_GPREL16); | |
5745 | relax_switch (); | |
5746 | } | |
d6bc6245 | 5747 | |
741fe287 | 5748 | if (*used_at == 0 && mips_opts.at) |
d6bc6245 | 5749 | { |
df58fc94 RS |
5750 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
5751 | macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S); | |
67c0d1eb RS |
5752 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
5753 | BFD_RELOC_MIPS_HIGHER); | |
5754 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
df58fc94 | 5755 | macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0); |
67c0d1eb | 5756 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); |
d6bc6245 TS |
5757 | *used_at = 1; |
5758 | } | |
5759 | else | |
5760 | { | |
df58fc94 | 5761 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb RS |
5762 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
5763 | BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 5764 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 5765 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); |
df58fc94 | 5766 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 5767 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); |
d6bc6245 | 5768 | } |
6caf9ef4 TS |
5769 | |
5770 | if (mips_relax.sequence) | |
5771 | relax_end (); | |
d6bc6245 | 5772 | } |
252b5132 RH |
5773 | else |
5774 | { | |
d6bc6245 | 5775 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 5776 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
d6bc6245 | 5777 | { |
4d7206a2 | 5778 | relax_start (ep->X_add_symbol); |
67c0d1eb | 5779 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 5780 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 5781 | relax_switch (); |
d6bc6245 | 5782 | } |
67c0d1eb RS |
5783 | macro_build_lui (ep, reg); |
5784 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
5785 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
5786 | if (mips_relax.sequence) |
5787 | relax_end (); | |
d6bc6245 | 5788 | } |
252b5132 | 5789 | } |
0a44bf69 | 5790 | else if (!mips_big_got) |
252b5132 RH |
5791 | { |
5792 | expressionS ex; | |
5793 | ||
5794 | /* If this is a reference to an external symbol, we want | |
5795 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5796 | Otherwise we want | |
5797 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5798 | nop | |
5799 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
5800 | If there is a constant, it must be added in after. |
5801 | ||
ed6fb7bd | 5802 | If we have NewABI, we want |
f5040a92 AO |
5803 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
5804 | unless we're referencing a global symbol with a non-zero | |
5805 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
5806 | if (HAVE_NEWABI) |
5807 | { | |
f5040a92 AO |
5808 | if (ep->X_add_number) |
5809 | { | |
4d7206a2 | 5810 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 5811 | ep->X_add_number = 0; |
4d7206a2 | 5812 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
5813 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
5814 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5815 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
5816 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5817 | ex.X_op = O_constant; | |
67c0d1eb | 5818 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5819 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 5820 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 5821 | relax_switch (); |
f5040a92 | 5822 | } |
67c0d1eb | 5823 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 5824 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
5825 | if (mips_relax.sequence) |
5826 | relax_end (); | |
ed6fb7bd SC |
5827 | } |
5828 | else | |
5829 | { | |
f5040a92 AO |
5830 | ex.X_add_number = ep->X_add_number; |
5831 | ep->X_add_number = 0; | |
67c0d1eb RS |
5832 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
5833 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 5834 | load_delay_nop (); |
4d7206a2 RS |
5835 | relax_start (ep->X_add_symbol); |
5836 | relax_switch (); | |
67c0d1eb | 5837 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 5838 | BFD_RELOC_LO16); |
4d7206a2 | 5839 | relax_end (); |
ed6fb7bd | 5840 | |
f5040a92 AO |
5841 | if (ex.X_add_number != 0) |
5842 | { | |
5843 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
5844 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5845 | ex.X_op = O_constant; | |
67c0d1eb | 5846 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5847 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 5848 | } |
252b5132 RH |
5849 | } |
5850 | } | |
0a44bf69 | 5851 | else if (mips_big_got) |
252b5132 RH |
5852 | { |
5853 | expressionS ex; | |
252b5132 RH |
5854 | |
5855 | /* This is the large GOT case. If this is a reference to an | |
5856 | external symbol, we want | |
5857 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5858 | addu $reg,$reg,$gp | |
5859 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
5860 | |
5861 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
5862 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
5863 | nop | |
5864 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 5865 | If there is a constant, it must be added in after. |
f5040a92 AO |
5866 | |
5867 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
5868 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
5869 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 5870 | */ |
438c16b8 TS |
5871 | if (HAVE_NEWABI) |
5872 | { | |
4d7206a2 | 5873 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 5874 | ep->X_add_number = 0; |
4d7206a2 | 5875 | relax_start (ep->X_add_symbol); |
df58fc94 | 5876 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
5877 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
5878 | reg, reg, mips_gp_register); | |
5879 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
5880 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
5881 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
5882 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5883 | else if (ex.X_add_number) | |
5884 | { | |
5885 | ex.X_op = O_constant; | |
67c0d1eb RS |
5886 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
5887 | BFD_RELOC_LO16); | |
f5040a92 AO |
5888 | } |
5889 | ||
5890 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 5891 | relax_switch (); |
67c0d1eb | 5892 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 5893 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
5894 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
5895 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 5896 | relax_end (); |
438c16b8 | 5897 | } |
252b5132 | 5898 | else |
438c16b8 | 5899 | { |
f5040a92 AO |
5900 | ex.X_add_number = ep->X_add_number; |
5901 | ep->X_add_number = 0; | |
4d7206a2 | 5902 | relax_start (ep->X_add_symbol); |
df58fc94 | 5903 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
5904 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
5905 | reg, reg, mips_gp_register); | |
5906 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
5907 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
5908 | relax_switch (); |
5909 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
5910 | { |
5911 | /* We need a nop before loading from $gp. This special | |
5912 | check is required because the lui which starts the main | |
5913 | instruction stream does not refer to $gp, and so will not | |
5914 | insert the nop which may be required. */ | |
67c0d1eb | 5915 | macro_build (NULL, "nop", ""); |
438c16b8 | 5916 | } |
67c0d1eb | 5917 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 5918 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 5919 | load_delay_nop (); |
67c0d1eb | 5920 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 5921 | BFD_RELOC_LO16); |
4d7206a2 | 5922 | relax_end (); |
438c16b8 | 5923 | |
f5040a92 AO |
5924 | if (ex.X_add_number != 0) |
5925 | { | |
5926 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
5927 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5928 | ex.X_op = O_constant; | |
67c0d1eb RS |
5929 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
5930 | BFD_RELOC_LO16); | |
f5040a92 | 5931 | } |
252b5132 RH |
5932 | } |
5933 | } | |
252b5132 RH |
5934 | else |
5935 | abort (); | |
8fc2e39e | 5936 | |
741fe287 | 5937 | if (!mips_opts.at && *used_at == 1) |
8fc2e39e | 5938 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
5939 | } |
5940 | ||
ea1fb5dc RS |
5941 | /* Move the contents of register SOURCE into register DEST. */ |
5942 | ||
5943 | static void | |
67c0d1eb | 5944 | move_register (int dest, int source) |
ea1fb5dc | 5945 | { |
df58fc94 RS |
5946 | /* Prefer to use a 16-bit microMIPS instruction unless the previous |
5947 | instruction specifically requires a 32-bit one. */ | |
5948 | if (mips_opts.micromips | |
5949 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
5950 | macro_build (NULL, "move", "mp,mj", dest, source ); | |
5951 | else | |
5952 | macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", | |
5953 | dest, source, 0); | |
ea1fb5dc RS |
5954 | } |
5955 | ||
4d7206a2 | 5956 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
5957 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
5958 | The two alternatives are: | |
4d7206a2 RS |
5959 | |
5960 | Global symbol Local sybmol | |
5961 | ------------- ------------ | |
5962 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
5963 | ... ... | |
5964 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
5965 | ||
5966 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
5967 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
5968 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
5969 | |
5970 | static void | |
67c0d1eb | 5971 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
5972 | { |
5973 | expressionS global; | |
5974 | ||
5975 | global = *local; | |
5976 | global.X_add_number = 0; | |
5977 | ||
5978 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
5979 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
5980 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 5981 | relax_switch (); |
67c0d1eb RS |
5982 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
5983 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
5984 | relax_end (); |
5985 | } | |
5986 | ||
5987 | static void | |
67c0d1eb | 5988 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
5989 | { |
5990 | expressionS global; | |
5991 | ||
5992 | global.X_op = O_constant; | |
5993 | global.X_op_symbol = NULL; | |
5994 | global.X_add_symbol = NULL; | |
5995 | global.X_add_number = local->X_add_number; | |
5996 | ||
5997 | relax_start (local->X_add_symbol); | |
67c0d1eb | 5998 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
5999 | dest, dest, BFD_RELOC_LO16); |
6000 | relax_switch (); | |
67c0d1eb | 6001 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
6002 | relax_end (); |
6003 | } | |
6004 | ||
f6a22291 MR |
6005 | static void |
6006 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
6007 | { | |
6008 | expressionS global; | |
6009 | int hold_mips_optimize; | |
6010 | ||
6011 | global.X_op = O_constant; | |
6012 | global.X_op_symbol = NULL; | |
6013 | global.X_add_symbol = NULL; | |
6014 | global.X_add_number = local->X_add_number; | |
6015 | ||
6016 | relax_start (local->X_add_symbol); | |
6017 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
6018 | relax_switch (); | |
6019 | /* Set mips_optimize around the lui instruction to avoid | |
6020 | inserting an unnecessary nop after the lw. */ | |
6021 | hold_mips_optimize = mips_optimize; | |
6022 | mips_optimize = 2; | |
6023 | macro_build_lui (&global, tmp); | |
6024 | mips_optimize = hold_mips_optimize; | |
6025 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
6026 | relax_end (); | |
6027 | ||
6028 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
6029 | } | |
6030 | ||
df58fc94 RS |
6031 | /* Emit a sequence of instructions to emulate a branch likely operation. |
6032 | BR is an ordinary branch corresponding to one to be emulated. BRNEG | |
6033 | is its complementing branch with the original condition negated. | |
6034 | CALL is set if the original branch specified the link operation. | |
6035 | EP, FMT, SREG and TREG specify the usual macro_build() parameters. | |
6036 | ||
6037 | Code like this is produced in the noreorder mode: | |
6038 | ||
6039 | BRNEG <args>, 1f | |
6040 | nop | |
6041 | b <sym> | |
6042 | delay slot (executed only if branch taken) | |
6043 | 1: | |
6044 | ||
6045 | or, if CALL is set: | |
6046 | ||
6047 | BRNEG <args>, 1f | |
6048 | nop | |
6049 | bal <sym> | |
6050 | delay slot (executed only if branch taken) | |
6051 | 1: | |
6052 | ||
6053 | In the reorder mode the delay slot would be filled with a nop anyway, | |
6054 | so code produced is simply: | |
6055 | ||
6056 | BR <args>, <sym> | |
6057 | nop | |
6058 | ||
6059 | This function is used when producing code for the microMIPS ASE that | |
6060 | does not implement branch likely instructions in hardware. */ | |
6061 | ||
6062 | static void | |
6063 | macro_build_branch_likely (const char *br, const char *brneg, | |
6064 | int call, expressionS *ep, const char *fmt, | |
6065 | unsigned int sreg, unsigned int treg) | |
6066 | { | |
6067 | int noreorder = mips_opts.noreorder; | |
6068 | expressionS expr1; | |
6069 | ||
6070 | gas_assert (mips_opts.micromips); | |
6071 | start_noreorder (); | |
6072 | if (noreorder) | |
6073 | { | |
6074 | micromips_label_expr (&expr1); | |
6075 | macro_build (&expr1, brneg, fmt, sreg, treg); | |
6076 | macro_build (NULL, "nop", ""); | |
6077 | macro_build (ep, call ? "bal" : "b", "p"); | |
6078 | ||
6079 | /* Set to true so that append_insn adds a label. */ | |
6080 | emit_branch_likely_macro = TRUE; | |
6081 | } | |
6082 | else | |
6083 | { | |
6084 | macro_build (ep, br, fmt, sreg, treg); | |
6085 | macro_build (NULL, "nop", ""); | |
6086 | } | |
6087 | end_noreorder (); | |
6088 | } | |
6089 | ||
6090 | /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as | |
6091 | the condition code tested. EP specifies the branch target. */ | |
6092 | ||
6093 | static void | |
6094 | macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc) | |
6095 | { | |
6096 | const int call = 0; | |
6097 | const char *brneg; | |
6098 | const char *br; | |
6099 | ||
6100 | switch (type) | |
6101 | { | |
6102 | case M_BC1FL: | |
6103 | br = "bc1f"; | |
6104 | brneg = "bc1t"; | |
6105 | break; | |
6106 | case M_BC1TL: | |
6107 | br = "bc1t"; | |
6108 | brneg = "bc1f"; | |
6109 | break; | |
6110 | case M_BC2FL: | |
6111 | br = "bc2f"; | |
6112 | brneg = "bc2t"; | |
6113 | break; | |
6114 | case M_BC2TL: | |
6115 | br = "bc2t"; | |
6116 | brneg = "bc2f"; | |
6117 | break; | |
6118 | default: | |
6119 | abort (); | |
6120 | } | |
6121 | macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO); | |
6122 | } | |
6123 | ||
6124 | /* Emit a two-argument branch macro specified by TYPE, using SREG as | |
6125 | the register tested. EP specifies the branch target. */ | |
6126 | ||
6127 | static void | |
6128 | macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg) | |
6129 | { | |
6130 | const char *brneg = NULL; | |
6131 | const char *br; | |
6132 | int call = 0; | |
6133 | ||
6134 | switch (type) | |
6135 | { | |
6136 | case M_BGEZ: | |
6137 | br = "bgez"; | |
6138 | break; | |
6139 | case M_BGEZL: | |
6140 | br = mips_opts.micromips ? "bgez" : "bgezl"; | |
6141 | brneg = "bltz"; | |
6142 | break; | |
6143 | case M_BGEZALL: | |
6144 | gas_assert (mips_opts.micromips); | |
6145 | br = "bgezals"; | |
6146 | brneg = "bltz"; | |
6147 | call = 1; | |
6148 | break; | |
6149 | case M_BGTZ: | |
6150 | br = "bgtz"; | |
6151 | break; | |
6152 | case M_BGTZL: | |
6153 | br = mips_opts.micromips ? "bgtz" : "bgtzl"; | |
6154 | brneg = "blez"; | |
6155 | break; | |
6156 | case M_BLEZ: | |
6157 | br = "blez"; | |
6158 | break; | |
6159 | case M_BLEZL: | |
6160 | br = mips_opts.micromips ? "blez" : "blezl"; | |
6161 | brneg = "bgtz"; | |
6162 | break; | |
6163 | case M_BLTZ: | |
6164 | br = "bltz"; | |
6165 | break; | |
6166 | case M_BLTZL: | |
6167 | br = mips_opts.micromips ? "bltz" : "bltzl"; | |
6168 | brneg = "bgez"; | |
6169 | break; | |
6170 | case M_BLTZALL: | |
6171 | gas_assert (mips_opts.micromips); | |
6172 | br = "bltzals"; | |
6173 | brneg = "bgez"; | |
6174 | call = 1; | |
6175 | break; | |
6176 | default: | |
6177 | abort (); | |
6178 | } | |
6179 | if (mips_opts.micromips && brneg) | |
6180 | macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO); | |
6181 | else | |
6182 | macro_build (ep, br, "s,p", sreg); | |
6183 | } | |
6184 | ||
6185 | /* Emit a three-argument branch macro specified by TYPE, using SREG and | |
6186 | TREG as the registers tested. EP specifies the branch target. */ | |
6187 | ||
6188 | static void | |
6189 | macro_build_branch_rsrt (int type, expressionS *ep, | |
6190 | unsigned int sreg, unsigned int treg) | |
6191 | { | |
6192 | const char *brneg = NULL; | |
6193 | const int call = 0; | |
6194 | const char *br; | |
6195 | ||
6196 | switch (type) | |
6197 | { | |
6198 | case M_BEQ: | |
6199 | case M_BEQ_I: | |
6200 | br = "beq"; | |
6201 | break; | |
6202 | case M_BEQL: | |
6203 | case M_BEQL_I: | |
6204 | br = mips_opts.micromips ? "beq" : "beql"; | |
6205 | brneg = "bne"; | |
6206 | break; | |
6207 | case M_BNE: | |
6208 | case M_BNE_I: | |
6209 | br = "bne"; | |
6210 | break; | |
6211 | case M_BNEL: | |
6212 | case M_BNEL_I: | |
6213 | br = mips_opts.micromips ? "bne" : "bnel"; | |
6214 | brneg = "beq"; | |
6215 | break; | |
6216 | default: | |
6217 | abort (); | |
6218 | } | |
6219 | if (mips_opts.micromips && brneg) | |
6220 | macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg); | |
6221 | else | |
6222 | macro_build (ep, br, "s,t,p", sreg, treg); | |
6223 | } | |
6224 | ||
252b5132 RH |
6225 | /* |
6226 | * Build macros | |
6227 | * This routine implements the seemingly endless macro or synthesized | |
6228 | * instructions and addressing modes in the mips assembly language. Many | |
6229 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 6230 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
6231 | * this verbose method. Others are not simple macros but are more like |
6232 | * optimizing code generation. | |
6233 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 6234 | * consecutively that would load AT with the upper half of the same address. |
252b5132 RH |
6235 | * The ensuing load upper instructions are ommited. This implies some kind |
6236 | * of global optimization. We currently only optimize within a single macro. | |
6237 | * For many of the load and store macros if the address is specified as a | |
6238 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
6239 | * first load register 'at' with zero and use it as the base register. The | |
6240 | * mips assembler simply uses register $zero. Just one tiny optimization | |
6241 | * we're missing. | |
6242 | */ | |
6243 | static void | |
17a2f251 | 6244 | macro (struct mips_cl_insn *ip) |
252b5132 | 6245 | { |
741fe287 MR |
6246 | unsigned int treg, sreg, dreg, breg; |
6247 | unsigned int tempreg; | |
252b5132 | 6248 | int mask; |
43841e91 | 6249 | int used_at = 0; |
df58fc94 | 6250 | expressionS label_expr; |
252b5132 | 6251 | expressionS expr1; |
df58fc94 | 6252 | expressionS *ep; |
252b5132 RH |
6253 | const char *s; |
6254 | const char *s2; | |
6255 | const char *fmt; | |
6256 | int likely = 0; | |
252b5132 | 6257 | int coproc = 0; |
df58fc94 | 6258 | int off12 = 0; |
1abe91b1 | 6259 | int call = 0; |
df58fc94 RS |
6260 | int jals = 0; |
6261 | int dbl = 0; | |
6262 | int imm = 0; | |
6263 | int ust = 0; | |
6264 | int lp = 0; | |
6265 | int ab = 0; | |
252b5132 | 6266 | int off; |
67c0d1eb | 6267 | offsetT maxnum; |
252b5132 | 6268 | bfd_reloc_code_real_type r; |
252b5132 RH |
6269 | int hold_mips_optimize; |
6270 | ||
9c2799c2 | 6271 | gas_assert (! mips_opts.mips16); |
252b5132 | 6272 | |
df58fc94 RS |
6273 | treg = EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); |
6274 | dreg = EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); | |
6275 | sreg = breg = EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); | |
252b5132 RH |
6276 | mask = ip->insn_mo->mask; |
6277 | ||
df58fc94 RS |
6278 | label_expr.X_op = O_constant; |
6279 | label_expr.X_op_symbol = NULL; | |
6280 | label_expr.X_add_symbol = NULL; | |
6281 | label_expr.X_add_number = 0; | |
6282 | ||
252b5132 RH |
6283 | expr1.X_op = O_constant; |
6284 | expr1.X_op_symbol = NULL; | |
6285 | expr1.X_add_symbol = NULL; | |
6286 | expr1.X_add_number = 1; | |
6287 | ||
6288 | switch (mask) | |
6289 | { | |
6290 | case M_DABS: | |
6291 | dbl = 1; | |
6292 | case M_ABS: | |
df58fc94 RS |
6293 | /* bgez $a0,1f |
6294 | move v0,$a0 | |
6295 | sub v0,$zero,$a0 | |
6296 | 1: | |
6297 | */ | |
252b5132 | 6298 | |
7d10b47d | 6299 | start_noreorder (); |
252b5132 | 6300 | |
df58fc94 RS |
6301 | if (mips_opts.micromips) |
6302 | micromips_label_expr (&label_expr); | |
6303 | else | |
6304 | label_expr.X_add_number = 8; | |
6305 | macro_build (&label_expr, "bgez", "s,p", sreg); | |
252b5132 | 6306 | if (dreg == sreg) |
a605d2b3 | 6307 | macro_build (NULL, "nop", ""); |
252b5132 | 6308 | else |
67c0d1eb RS |
6309 | move_register (dreg, sreg); |
6310 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); | |
df58fc94 RS |
6311 | if (mips_opts.micromips) |
6312 | micromips_add_label (); | |
252b5132 | 6313 | |
7d10b47d | 6314 | end_noreorder (); |
8fc2e39e | 6315 | break; |
252b5132 RH |
6316 | |
6317 | case M_ADD_I: | |
6318 | s = "addi"; | |
6319 | s2 = "add"; | |
6320 | goto do_addi; | |
6321 | case M_ADDU_I: | |
6322 | s = "addiu"; | |
6323 | s2 = "addu"; | |
6324 | goto do_addi; | |
6325 | case M_DADD_I: | |
6326 | dbl = 1; | |
6327 | s = "daddi"; | |
6328 | s2 = "dadd"; | |
df58fc94 RS |
6329 | if (!mips_opts.micromips) |
6330 | goto do_addi; | |
6331 | if (imm_expr.X_op == O_constant | |
6332 | && imm_expr.X_add_number >= -0x200 | |
6333 | && imm_expr.X_add_number < 0x200) | |
6334 | { | |
6335 | macro_build (NULL, s, "t,r,.", treg, sreg, imm_expr.X_add_number); | |
6336 | break; | |
6337 | } | |
6338 | goto do_addi_i; | |
252b5132 RH |
6339 | case M_DADDU_I: |
6340 | dbl = 1; | |
6341 | s = "daddiu"; | |
6342 | s2 = "daddu"; | |
6343 | do_addi: | |
6344 | if (imm_expr.X_op == O_constant | |
6345 | && imm_expr.X_add_number >= -0x8000 | |
6346 | && imm_expr.X_add_number < 0x8000) | |
6347 | { | |
67c0d1eb | 6348 | macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 6349 | break; |
252b5132 | 6350 | } |
df58fc94 | 6351 | do_addi_i: |
8fc2e39e | 6352 | used_at = 1; |
67c0d1eb RS |
6353 | load_register (AT, &imm_expr, dbl); |
6354 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
6355 | break; |
6356 | ||
6357 | case M_AND_I: | |
6358 | s = "andi"; | |
6359 | s2 = "and"; | |
6360 | goto do_bit; | |
6361 | case M_OR_I: | |
6362 | s = "ori"; | |
6363 | s2 = "or"; | |
6364 | goto do_bit; | |
6365 | case M_NOR_I: | |
6366 | s = ""; | |
6367 | s2 = "nor"; | |
6368 | goto do_bit; | |
6369 | case M_XOR_I: | |
6370 | s = "xori"; | |
6371 | s2 = "xor"; | |
6372 | do_bit: | |
6373 | if (imm_expr.X_op == O_constant | |
6374 | && imm_expr.X_add_number >= 0 | |
6375 | && imm_expr.X_add_number < 0x10000) | |
6376 | { | |
6377 | if (mask != M_NOR_I) | |
67c0d1eb | 6378 | macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
6379 | else |
6380 | { | |
67c0d1eb RS |
6381 | macro_build (&imm_expr, "ori", "t,r,i", |
6382 | treg, sreg, BFD_RELOC_LO16); | |
6383 | macro_build (NULL, "nor", "d,v,t", treg, treg, 0); | |
252b5132 | 6384 | } |
8fc2e39e | 6385 | break; |
252b5132 RH |
6386 | } |
6387 | ||
8fc2e39e | 6388 | used_at = 1; |
67c0d1eb RS |
6389 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
6390 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
6391 | break; |
6392 | ||
8b082fb1 TS |
6393 | case M_BALIGN: |
6394 | switch (imm_expr.X_add_number) | |
6395 | { | |
6396 | case 0: | |
6397 | macro_build (NULL, "nop", ""); | |
6398 | break; | |
6399 | case 2: | |
6400 | macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg); | |
6401 | break; | |
6402 | default: | |
6403 | macro_build (NULL, "balign", "t,s,2", treg, sreg, | |
90ecf173 | 6404 | (int) imm_expr.X_add_number); |
8b082fb1 TS |
6405 | break; |
6406 | } | |
6407 | break; | |
6408 | ||
df58fc94 RS |
6409 | case M_BC1FL: |
6410 | case M_BC1TL: | |
6411 | case M_BC2FL: | |
6412 | case M_BC2TL: | |
6413 | gas_assert (mips_opts.micromips); | |
6414 | macro_build_branch_ccl (mask, &offset_expr, | |
6415 | EXTRACT_OPERAND (1, BCC, *ip)); | |
6416 | break; | |
6417 | ||
252b5132 | 6418 | case M_BEQ_I: |
252b5132 | 6419 | case M_BEQL_I: |
252b5132 | 6420 | case M_BNE_I: |
252b5132 | 6421 | case M_BNEL_I: |
252b5132 | 6422 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
df58fc94 RS |
6423 | treg = 0; |
6424 | else | |
252b5132 | 6425 | { |
df58fc94 RS |
6426 | treg = AT; |
6427 | used_at = 1; | |
6428 | load_register (treg, &imm_expr, HAVE_64BIT_GPRS); | |
252b5132 | 6429 | } |
df58fc94 RS |
6430 | /* Fall through. */ |
6431 | case M_BEQL: | |
6432 | case M_BNEL: | |
6433 | macro_build_branch_rsrt (mask, &offset_expr, sreg, treg); | |
252b5132 RH |
6434 | break; |
6435 | ||
6436 | case M_BGEL: | |
6437 | likely = 1; | |
6438 | case M_BGE: | |
6439 | if (treg == 0) | |
df58fc94 RS |
6440 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, sreg); |
6441 | else if (sreg == 0) | |
6442 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, treg); | |
6443 | else | |
252b5132 | 6444 | { |
df58fc94 RS |
6445 | used_at = 1; |
6446 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); | |
6447 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6448 | &offset_expr, AT, ZERO); | |
252b5132 | 6449 | } |
df58fc94 RS |
6450 | break; |
6451 | ||
6452 | case M_BGEZL: | |
6453 | case M_BGEZALL: | |
6454 | case M_BGTZL: | |
6455 | case M_BLEZL: | |
6456 | case M_BLTZL: | |
6457 | case M_BLTZALL: | |
6458 | macro_build_branch_rs (mask, &offset_expr, sreg); | |
252b5132 RH |
6459 | break; |
6460 | ||
6461 | case M_BGTL_I: | |
6462 | likely = 1; | |
6463 | case M_BGT_I: | |
90ecf173 | 6464 | /* Check for > max integer. */ |
252b5132 | 6465 | maxnum = 0x7fffffff; |
ca4e0257 | 6466 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
6467 | { |
6468 | maxnum <<= 16; | |
6469 | maxnum |= 0xffff; | |
6470 | maxnum <<= 16; | |
6471 | maxnum |= 0xffff; | |
6472 | } | |
6473 | if (imm_expr.X_op == O_constant | |
6474 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 6475 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
6476 | { |
6477 | do_false: | |
90ecf173 | 6478 | /* Result is always false. */ |
252b5132 | 6479 | if (! likely) |
a605d2b3 | 6480 | macro_build (NULL, "nop", ""); |
252b5132 | 6481 | else |
df58fc94 | 6482 | macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO); |
8fc2e39e | 6483 | break; |
252b5132 RH |
6484 | } |
6485 | if (imm_expr.X_op != O_constant) | |
6486 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 6487 | ++imm_expr.X_add_number; |
252b5132 RH |
6488 | /* FALLTHROUGH */ |
6489 | case M_BGE_I: | |
6490 | case M_BGEL_I: | |
6491 | if (mask == M_BGEL_I) | |
6492 | likely = 1; | |
6493 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6494 | { | |
df58fc94 RS |
6495 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, |
6496 | &offset_expr, sreg); | |
8fc2e39e | 6497 | break; |
252b5132 RH |
6498 | } |
6499 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
6500 | { | |
df58fc94 RS |
6501 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, |
6502 | &offset_expr, sreg); | |
8fc2e39e | 6503 | break; |
252b5132 RH |
6504 | } |
6505 | maxnum = 0x7fffffff; | |
ca4e0257 | 6506 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
6507 | { |
6508 | maxnum <<= 16; | |
6509 | maxnum |= 0xffff; | |
6510 | maxnum <<= 16; | |
6511 | maxnum |= 0xffff; | |
6512 | } | |
6513 | maxnum = - maxnum - 1; | |
6514 | if (imm_expr.X_op == O_constant | |
6515 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 6516 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
6517 | { |
6518 | do_true: | |
6519 | /* result is always true */ | |
6520 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
67c0d1eb | 6521 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 6522 | break; |
252b5132 | 6523 | } |
8fc2e39e | 6524 | used_at = 1; |
67c0d1eb | 6525 | set_at (sreg, 0); |
df58fc94 RS |
6526 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
6527 | &offset_expr, AT, ZERO); | |
252b5132 RH |
6528 | break; |
6529 | ||
6530 | case M_BGEUL: | |
6531 | likely = 1; | |
6532 | case M_BGEU: | |
6533 | if (treg == 0) | |
6534 | goto do_true; | |
df58fc94 RS |
6535 | else if (sreg == 0) |
6536 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6537 | &offset_expr, ZERO, treg); | |
6538 | else | |
252b5132 | 6539 | { |
df58fc94 RS |
6540 | used_at = 1; |
6541 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); | |
6542 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6543 | &offset_expr, AT, ZERO); | |
252b5132 | 6544 | } |
252b5132 RH |
6545 | break; |
6546 | ||
6547 | case M_BGTUL_I: | |
6548 | likely = 1; | |
6549 | case M_BGTU_I: | |
6550 | if (sreg == 0 | |
ca4e0257 | 6551 | || (HAVE_32BIT_GPRS |
252b5132 | 6552 | && imm_expr.X_op == O_constant |
f01dc953 | 6553 | && imm_expr.X_add_number == -1)) |
252b5132 RH |
6554 | goto do_false; |
6555 | if (imm_expr.X_op != O_constant) | |
6556 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 6557 | ++imm_expr.X_add_number; |
252b5132 RH |
6558 | /* FALLTHROUGH */ |
6559 | case M_BGEU_I: | |
6560 | case M_BGEUL_I: | |
6561 | if (mask == M_BGEUL_I) | |
6562 | likely = 1; | |
6563 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6564 | goto do_true; | |
df58fc94 RS |
6565 | else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
6566 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6567 | &offset_expr, sreg, ZERO); | |
6568 | else | |
252b5132 | 6569 | { |
df58fc94 RS |
6570 | used_at = 1; |
6571 | set_at (sreg, 1); | |
6572 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6573 | &offset_expr, AT, ZERO); | |
252b5132 | 6574 | } |
252b5132 RH |
6575 | break; |
6576 | ||
6577 | case M_BGTL: | |
6578 | likely = 1; | |
6579 | case M_BGT: | |
6580 | if (treg == 0) | |
df58fc94 RS |
6581 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, sreg); |
6582 | else if (sreg == 0) | |
6583 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, treg); | |
6584 | else | |
252b5132 | 6585 | { |
df58fc94 RS |
6586 | used_at = 1; |
6587 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); | |
6588 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6589 | &offset_expr, AT, ZERO); | |
252b5132 | 6590 | } |
252b5132 RH |
6591 | break; |
6592 | ||
6593 | case M_BGTUL: | |
6594 | likely = 1; | |
6595 | case M_BGTU: | |
6596 | if (treg == 0) | |
df58fc94 RS |
6597 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
6598 | &offset_expr, sreg, ZERO); | |
6599 | else if (sreg == 0) | |
6600 | goto do_false; | |
6601 | else | |
252b5132 | 6602 | { |
df58fc94 RS |
6603 | used_at = 1; |
6604 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); | |
6605 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6606 | &offset_expr, AT, ZERO); | |
252b5132 | 6607 | } |
252b5132 RH |
6608 | break; |
6609 | ||
6610 | case M_BLEL: | |
6611 | likely = 1; | |
6612 | case M_BLE: | |
6613 | if (treg == 0) | |
df58fc94 RS |
6614 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg); |
6615 | else if (sreg == 0) | |
6616 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, treg); | |
6617 | else | |
252b5132 | 6618 | { |
df58fc94 RS |
6619 | used_at = 1; |
6620 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); | |
6621 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6622 | &offset_expr, AT, ZERO); | |
252b5132 | 6623 | } |
252b5132 RH |
6624 | break; |
6625 | ||
6626 | case M_BLEL_I: | |
6627 | likely = 1; | |
6628 | case M_BLE_I: | |
6629 | maxnum = 0x7fffffff; | |
ca4e0257 | 6630 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
6631 | { |
6632 | maxnum <<= 16; | |
6633 | maxnum |= 0xffff; | |
6634 | maxnum <<= 16; | |
6635 | maxnum |= 0xffff; | |
6636 | } | |
6637 | if (imm_expr.X_op == O_constant | |
6638 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 6639 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
6640 | goto do_true; |
6641 | if (imm_expr.X_op != O_constant) | |
6642 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 6643 | ++imm_expr.X_add_number; |
252b5132 RH |
6644 | /* FALLTHROUGH */ |
6645 | case M_BLT_I: | |
6646 | case M_BLTL_I: | |
6647 | if (mask == M_BLTL_I) | |
6648 | likely = 1; | |
6649 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
df58fc94 RS |
6650 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg); |
6651 | else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
6652 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg); | |
6653 | else | |
252b5132 | 6654 | { |
df58fc94 RS |
6655 | used_at = 1; |
6656 | set_at (sreg, 0); | |
6657 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6658 | &offset_expr, AT, ZERO); | |
252b5132 | 6659 | } |
252b5132 RH |
6660 | break; |
6661 | ||
6662 | case M_BLEUL: | |
6663 | likely = 1; | |
6664 | case M_BLEU: | |
6665 | if (treg == 0) | |
df58fc94 RS |
6666 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
6667 | &offset_expr, sreg, ZERO); | |
6668 | else if (sreg == 0) | |
6669 | goto do_true; | |
6670 | else | |
252b5132 | 6671 | { |
df58fc94 RS |
6672 | used_at = 1; |
6673 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); | |
6674 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6675 | &offset_expr, AT, ZERO); | |
252b5132 | 6676 | } |
252b5132 RH |
6677 | break; |
6678 | ||
6679 | case M_BLEUL_I: | |
6680 | likely = 1; | |
6681 | case M_BLEU_I: | |
6682 | if (sreg == 0 | |
ca4e0257 | 6683 | || (HAVE_32BIT_GPRS |
252b5132 | 6684 | && imm_expr.X_op == O_constant |
f01dc953 | 6685 | && imm_expr.X_add_number == -1)) |
252b5132 RH |
6686 | goto do_true; |
6687 | if (imm_expr.X_op != O_constant) | |
6688 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 6689 | ++imm_expr.X_add_number; |
252b5132 RH |
6690 | /* FALLTHROUGH */ |
6691 | case M_BLTU_I: | |
6692 | case M_BLTUL_I: | |
6693 | if (mask == M_BLTUL_I) | |
6694 | likely = 1; | |
6695 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6696 | goto do_false; | |
df58fc94 RS |
6697 | else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
6698 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
6699 | &offset_expr, sreg, ZERO); | |
6700 | else | |
252b5132 | 6701 | { |
df58fc94 RS |
6702 | used_at = 1; |
6703 | set_at (sreg, 1); | |
6704 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6705 | &offset_expr, AT, ZERO); | |
252b5132 | 6706 | } |
252b5132 RH |
6707 | break; |
6708 | ||
6709 | case M_BLTL: | |
6710 | likely = 1; | |
6711 | case M_BLT: | |
6712 | if (treg == 0) | |
df58fc94 RS |
6713 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg); |
6714 | else if (sreg == 0) | |
6715 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, treg); | |
6716 | else | |
252b5132 | 6717 | { |
df58fc94 RS |
6718 | used_at = 1; |
6719 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); | |
6720 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6721 | &offset_expr, AT, ZERO); | |
252b5132 | 6722 | } |
252b5132 RH |
6723 | break; |
6724 | ||
6725 | case M_BLTUL: | |
6726 | likely = 1; | |
6727 | case M_BLTU: | |
6728 | if (treg == 0) | |
6729 | goto do_false; | |
df58fc94 RS |
6730 | else if (sreg == 0) |
6731 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6732 | &offset_expr, ZERO, treg); | |
6733 | else | |
252b5132 | 6734 | { |
df58fc94 RS |
6735 | used_at = 1; |
6736 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); | |
6737 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
6738 | &offset_expr, AT, ZERO); | |
252b5132 | 6739 | } |
252b5132 RH |
6740 | break; |
6741 | ||
5f74bc13 CD |
6742 | case M_DEXT: |
6743 | { | |
d5818fca MR |
6744 | /* Use unsigned arithmetic. */ |
6745 | addressT pos; | |
6746 | addressT size; | |
5f74bc13 | 6747 | |
90ecf173 | 6748 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) |
5f74bc13 CD |
6749 | { |
6750 | as_bad (_("Unsupported large constant")); | |
6751 | pos = size = 1; | |
6752 | } | |
6753 | else | |
6754 | { | |
d5818fca MR |
6755 | pos = imm_expr.X_add_number; |
6756 | size = imm2_expr.X_add_number; | |
5f74bc13 CD |
6757 | } |
6758 | ||
6759 | if (pos > 63) | |
6760 | { | |
d5818fca | 6761 | as_bad (_("Improper position (%lu)"), (unsigned long) pos); |
5f74bc13 CD |
6762 | pos = 1; |
6763 | } | |
90ecf173 | 6764 | if (size == 0 || size > 64 || (pos + size - 1) > 63) |
5f74bc13 CD |
6765 | { |
6766 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
d5818fca | 6767 | (unsigned long) size, (unsigned long) pos); |
5f74bc13 CD |
6768 | size = 1; |
6769 | } | |
6770 | ||
6771 | if (size <= 32 && pos < 32) | |
6772 | { | |
6773 | s = "dext"; | |
6774 | fmt = "t,r,+A,+C"; | |
6775 | } | |
6776 | else if (size <= 32) | |
6777 | { | |
6778 | s = "dextu"; | |
6779 | fmt = "t,r,+E,+H"; | |
6780 | } | |
6781 | else | |
6782 | { | |
6783 | s = "dextm"; | |
6784 | fmt = "t,r,+A,+G"; | |
6785 | } | |
d5818fca MR |
6786 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos, |
6787 | (int) (size - 1)); | |
5f74bc13 | 6788 | } |
8fc2e39e | 6789 | break; |
5f74bc13 CD |
6790 | |
6791 | case M_DINS: | |
6792 | { | |
d5818fca MR |
6793 | /* Use unsigned arithmetic. */ |
6794 | addressT pos; | |
6795 | addressT size; | |
5f74bc13 | 6796 | |
90ecf173 | 6797 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) |
5f74bc13 CD |
6798 | { |
6799 | as_bad (_("Unsupported large constant")); | |
6800 | pos = size = 1; | |
6801 | } | |
6802 | else | |
6803 | { | |
d5818fca MR |
6804 | pos = imm_expr.X_add_number; |
6805 | size = imm2_expr.X_add_number; | |
5f74bc13 CD |
6806 | } |
6807 | ||
6808 | if (pos > 63) | |
6809 | { | |
d5818fca | 6810 | as_bad (_("Improper position (%lu)"), (unsigned long) pos); |
5f74bc13 CD |
6811 | pos = 1; |
6812 | } | |
90ecf173 | 6813 | if (size == 0 || size > 64 || (pos + size - 1) > 63) |
5f74bc13 CD |
6814 | { |
6815 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
d5818fca | 6816 | (unsigned long) size, (unsigned long) pos); |
5f74bc13 CD |
6817 | size = 1; |
6818 | } | |
6819 | ||
6820 | if (pos < 32 && (pos + size - 1) < 32) | |
6821 | { | |
6822 | s = "dins"; | |
6823 | fmt = "t,r,+A,+B"; | |
6824 | } | |
6825 | else if (pos >= 32) | |
6826 | { | |
6827 | s = "dinsu"; | |
6828 | fmt = "t,r,+E,+F"; | |
6829 | } | |
6830 | else | |
6831 | { | |
6832 | s = "dinsm"; | |
6833 | fmt = "t,r,+A,+F"; | |
6834 | } | |
750bdd57 AS |
6835 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos, |
6836 | (int) (pos + size - 1)); | |
5f74bc13 | 6837 | } |
8fc2e39e | 6838 | break; |
5f74bc13 | 6839 | |
252b5132 RH |
6840 | case M_DDIV_3: |
6841 | dbl = 1; | |
6842 | case M_DIV_3: | |
6843 | s = "mflo"; | |
6844 | goto do_div3; | |
6845 | case M_DREM_3: | |
6846 | dbl = 1; | |
6847 | case M_REM_3: | |
6848 | s = "mfhi"; | |
6849 | do_div3: | |
6850 | if (treg == 0) | |
6851 | { | |
6852 | as_warn (_("Divide by zero.")); | |
6853 | if (mips_trap) | |
df58fc94 | 6854 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 6855 | else |
df58fc94 | 6856 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 6857 | break; |
252b5132 RH |
6858 | } |
6859 | ||
7d10b47d | 6860 | start_noreorder (); |
252b5132 RH |
6861 | if (mips_trap) |
6862 | { | |
df58fc94 | 6863 | macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7); |
67c0d1eb | 6864 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
252b5132 RH |
6865 | } |
6866 | else | |
6867 | { | |
df58fc94 RS |
6868 | if (mips_opts.micromips) |
6869 | micromips_label_expr (&label_expr); | |
6870 | else | |
6871 | label_expr.X_add_number = 8; | |
6872 | macro_build (&label_expr, "bne", "s,t,p", treg, ZERO); | |
67c0d1eb | 6873 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
df58fc94 RS |
6874 | macro_build (NULL, "break", BRK_FMT, 7); |
6875 | if (mips_opts.micromips) | |
6876 | micromips_add_label (); | |
252b5132 RH |
6877 | } |
6878 | expr1.X_add_number = -1; | |
8fc2e39e | 6879 | used_at = 1; |
f6a22291 | 6880 | load_register (AT, &expr1, dbl); |
df58fc94 RS |
6881 | if (mips_opts.micromips) |
6882 | micromips_label_expr (&label_expr); | |
6883 | else | |
6884 | label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); | |
6885 | macro_build (&label_expr, "bne", "s,t,p", treg, AT); | |
252b5132 RH |
6886 | if (dbl) |
6887 | { | |
6888 | expr1.X_add_number = 1; | |
f6a22291 | 6889 | load_register (AT, &expr1, dbl); |
df58fc94 | 6890 | macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31); |
252b5132 RH |
6891 | } |
6892 | else | |
6893 | { | |
6894 | expr1.X_add_number = 0x80000000; | |
df58fc94 | 6895 | macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16); |
252b5132 RH |
6896 | } |
6897 | if (mips_trap) | |
6898 | { | |
df58fc94 | 6899 | macro_build (NULL, "teq", TRAP_FMT, sreg, AT, 6); |
252b5132 RH |
6900 | /* We want to close the noreorder block as soon as possible, so |
6901 | that later insns are available for delay slot filling. */ | |
7d10b47d | 6902 | end_noreorder (); |
252b5132 RH |
6903 | } |
6904 | else | |
6905 | { | |
df58fc94 RS |
6906 | if (mips_opts.micromips) |
6907 | micromips_label_expr (&label_expr); | |
6908 | else | |
6909 | label_expr.X_add_number = 8; | |
6910 | macro_build (&label_expr, "bne", "s,t,p", sreg, AT); | |
a605d2b3 | 6911 | macro_build (NULL, "nop", ""); |
252b5132 RH |
6912 | |
6913 | /* We want to close the noreorder block as soon as possible, so | |
6914 | that later insns are available for delay slot filling. */ | |
7d10b47d | 6915 | end_noreorder (); |
252b5132 | 6916 | |
df58fc94 | 6917 | macro_build (NULL, "break", BRK_FMT, 6); |
252b5132 | 6918 | } |
df58fc94 RS |
6919 | if (mips_opts.micromips) |
6920 | micromips_add_label (); | |
6921 | macro_build (NULL, s, MFHL_FMT, dreg); | |
252b5132 RH |
6922 | break; |
6923 | ||
6924 | case M_DIV_3I: | |
6925 | s = "div"; | |
6926 | s2 = "mflo"; | |
6927 | goto do_divi; | |
6928 | case M_DIVU_3I: | |
6929 | s = "divu"; | |
6930 | s2 = "mflo"; | |
6931 | goto do_divi; | |
6932 | case M_REM_3I: | |
6933 | s = "div"; | |
6934 | s2 = "mfhi"; | |
6935 | goto do_divi; | |
6936 | case M_REMU_3I: | |
6937 | s = "divu"; | |
6938 | s2 = "mfhi"; | |
6939 | goto do_divi; | |
6940 | case M_DDIV_3I: | |
6941 | dbl = 1; | |
6942 | s = "ddiv"; | |
6943 | s2 = "mflo"; | |
6944 | goto do_divi; | |
6945 | case M_DDIVU_3I: | |
6946 | dbl = 1; | |
6947 | s = "ddivu"; | |
6948 | s2 = "mflo"; | |
6949 | goto do_divi; | |
6950 | case M_DREM_3I: | |
6951 | dbl = 1; | |
6952 | s = "ddiv"; | |
6953 | s2 = "mfhi"; | |
6954 | goto do_divi; | |
6955 | case M_DREMU_3I: | |
6956 | dbl = 1; | |
6957 | s = "ddivu"; | |
6958 | s2 = "mfhi"; | |
6959 | do_divi: | |
6960 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6961 | { | |
6962 | as_warn (_("Divide by zero.")); | |
6963 | if (mips_trap) | |
df58fc94 | 6964 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 6965 | else |
df58fc94 | 6966 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 6967 | break; |
252b5132 RH |
6968 | } |
6969 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
6970 | { | |
6971 | if (strcmp (s2, "mflo") == 0) | |
67c0d1eb | 6972 | move_register (dreg, sreg); |
252b5132 | 6973 | else |
c80c840e | 6974 | move_register (dreg, ZERO); |
8fc2e39e | 6975 | break; |
252b5132 RH |
6976 | } |
6977 | if (imm_expr.X_op == O_constant | |
6978 | && imm_expr.X_add_number == -1 | |
6979 | && s[strlen (s) - 1] != 'u') | |
6980 | { | |
6981 | if (strcmp (s2, "mflo") == 0) | |
6982 | { | |
67c0d1eb | 6983 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg); |
252b5132 RH |
6984 | } |
6985 | else | |
c80c840e | 6986 | move_register (dreg, ZERO); |
8fc2e39e | 6987 | break; |
252b5132 RH |
6988 | } |
6989 | ||
8fc2e39e | 6990 | used_at = 1; |
67c0d1eb RS |
6991 | load_register (AT, &imm_expr, dbl); |
6992 | macro_build (NULL, s, "z,s,t", sreg, AT); | |
df58fc94 | 6993 | macro_build (NULL, s2, MFHL_FMT, dreg); |
252b5132 RH |
6994 | break; |
6995 | ||
6996 | case M_DIVU_3: | |
6997 | s = "divu"; | |
6998 | s2 = "mflo"; | |
6999 | goto do_divu3; | |
7000 | case M_REMU_3: | |
7001 | s = "divu"; | |
7002 | s2 = "mfhi"; | |
7003 | goto do_divu3; | |
7004 | case M_DDIVU_3: | |
7005 | s = "ddivu"; | |
7006 | s2 = "mflo"; | |
7007 | goto do_divu3; | |
7008 | case M_DREMU_3: | |
7009 | s = "ddivu"; | |
7010 | s2 = "mfhi"; | |
7011 | do_divu3: | |
7d10b47d | 7012 | start_noreorder (); |
252b5132 RH |
7013 | if (mips_trap) |
7014 | { | |
df58fc94 | 7015 | macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7); |
67c0d1eb | 7016 | macro_build (NULL, s, "z,s,t", sreg, treg); |
252b5132 RH |
7017 | /* We want to close the noreorder block as soon as possible, so |
7018 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7019 | end_noreorder (); |
252b5132 RH |
7020 | } |
7021 | else | |
7022 | { | |
df58fc94 RS |
7023 | if (mips_opts.micromips) |
7024 | micromips_label_expr (&label_expr); | |
7025 | else | |
7026 | label_expr.X_add_number = 8; | |
7027 | macro_build (&label_expr, "bne", "s,t,p", treg, ZERO); | |
67c0d1eb | 7028 | macro_build (NULL, s, "z,s,t", sreg, treg); |
252b5132 RH |
7029 | |
7030 | /* We want to close the noreorder block as soon as possible, so | |
7031 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7032 | end_noreorder (); |
df58fc94 RS |
7033 | macro_build (NULL, "break", BRK_FMT, 7); |
7034 | if (mips_opts.micromips) | |
7035 | micromips_add_label (); | |
252b5132 | 7036 | } |
df58fc94 | 7037 | macro_build (NULL, s2, MFHL_FMT, dreg); |
8fc2e39e | 7038 | break; |
252b5132 | 7039 | |
1abe91b1 MR |
7040 | case M_DLCA_AB: |
7041 | dbl = 1; | |
7042 | case M_LCA_AB: | |
7043 | call = 1; | |
7044 | goto do_la; | |
252b5132 RH |
7045 | case M_DLA_AB: |
7046 | dbl = 1; | |
7047 | case M_LA_AB: | |
1abe91b1 | 7048 | do_la: |
252b5132 RH |
7049 | /* Load the address of a symbol into a register. If breg is not |
7050 | zero, we then add a base register to it. */ | |
7051 | ||
3bec30a8 TS |
7052 | if (dbl && HAVE_32BIT_GPRS) |
7053 | as_warn (_("dla used to load 32-bit register")); | |
7054 | ||
90ecf173 | 7055 | if (!dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
7056 | as_warn (_("la used to load 64-bit address")); |
7057 | ||
0c11417f MR |
7058 | if (offset_expr.X_op == O_constant |
7059 | && offset_expr.X_add_number >= -0x8000 | |
7060 | && offset_expr.X_add_number < 0x8000) | |
7061 | { | |
aed1a261 | 7062 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
17a2f251 | 7063 | "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7064 | break; |
0c11417f MR |
7065 | } |
7066 | ||
741fe287 | 7067 | if (mips_opts.at && (treg == breg)) |
afdbd6d0 CD |
7068 | { |
7069 | tempreg = AT; | |
7070 | used_at = 1; | |
7071 | } | |
7072 | else | |
7073 | { | |
7074 | tempreg = treg; | |
afdbd6d0 CD |
7075 | } |
7076 | ||
252b5132 RH |
7077 | if (offset_expr.X_op != O_symbol |
7078 | && offset_expr.X_op != O_constant) | |
7079 | { | |
f71d0d44 | 7080 | as_bad (_("Expression too complex")); |
252b5132 RH |
7081 | offset_expr.X_op = O_constant; |
7082 | } | |
7083 | ||
252b5132 | 7084 | if (offset_expr.X_op == O_constant) |
aed1a261 | 7085 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
7086 | else if (mips_pic == NO_PIC) |
7087 | { | |
d6bc6245 | 7088 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 7089 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
7090 | Otherwise we want |
7091 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
7092 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7093 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 7094 | so we may as well always use the latter form. |
76b3015f | 7095 | |
6caf9ef4 TS |
7096 | With 64bit address space and a usable $at we want |
7097 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
7098 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
7099 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
7100 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
7101 | dsll32 $tempreg,0 | |
7102 | daddu $tempreg,$tempreg,$at | |
7103 | ||
7104 | If $at is already in use, we use a path which is suboptimal | |
7105 | on superscalar processors. | |
7106 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
7107 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
7108 | dsll $tempreg,16 | |
7109 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
7110 | dsll $tempreg,16 | |
7111 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
7112 | ||
7113 | For GP relative symbols in 64bit address space we can use | |
7114 | the same sequence as in 32bit address space. */ | |
aed1a261 | 7115 | if (HAVE_64BIT_SYMBOLS) |
252b5132 | 7116 | { |
6caf9ef4 TS |
7117 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
7118 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
7119 | { | |
7120 | relax_start (offset_expr.X_add_symbol); | |
7121 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
7122 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
7123 | relax_switch (); | |
7124 | } | |
d6bc6245 | 7125 | |
741fe287 | 7126 | if (used_at == 0 && mips_opts.at) |
98d3f06f | 7127 | { |
df58fc94 | 7128 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 7129 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 7130 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 7131 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 7132 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7133 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 7134 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7135 | AT, AT, BFD_RELOC_LO16); |
df58fc94 | 7136 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb | 7137 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
98d3f06f KH |
7138 | used_at = 1; |
7139 | } | |
7140 | else | |
7141 | { | |
df58fc94 | 7142 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 7143 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 7144 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7145 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
df58fc94 | 7146 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 7147 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7148 | tempreg, tempreg, BFD_RELOC_HI16_S); |
df58fc94 | 7149 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 7150 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7151 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 7152 | } |
6caf9ef4 TS |
7153 | |
7154 | if (mips_relax.sequence) | |
7155 | relax_end (); | |
98d3f06f KH |
7156 | } |
7157 | else | |
7158 | { | |
7159 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 7160 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
98d3f06f | 7161 | { |
4d7206a2 | 7162 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7163 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7164 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 7165 | relax_switch (); |
98d3f06f | 7166 | } |
6943caf0 | 7167 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
f71d0d44 | 7168 | as_bad (_("Offset too large")); |
67c0d1eb RS |
7169 | macro_build_lui (&offset_expr, tempreg); |
7170 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
7171 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
7172 | if (mips_relax.sequence) |
7173 | relax_end (); | |
98d3f06f | 7174 | } |
252b5132 | 7175 | } |
0a44bf69 | 7176 | else if (!mips_big_got && !HAVE_NEWABI) |
252b5132 | 7177 | { |
9117d219 NC |
7178 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
7179 | ||
252b5132 RH |
7180 | /* If this is a reference to an external symbol, and there |
7181 | is no constant, we want | |
7182 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 7183 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 7184 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
7185 | For a local symbol, we want |
7186 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7187 | nop | |
7188 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7189 | ||
7190 | If we have a small constant, and this is a reference to | |
7191 | an external symbol, we want | |
7192 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7193 | nop | |
7194 | addiu $tempreg,$tempreg,<constant> | |
7195 | For a local symbol, we want the same instruction | |
7196 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
7197 | addiu instruction. | |
7198 | ||
7199 | If we have a large constant, and this is a reference to | |
7200 | an external symbol, we want | |
7201 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7202 | lui $at,<hiconstant> | |
7203 | addiu $at,$at,<loconstant> | |
7204 | addu $tempreg,$tempreg,$at | |
7205 | For a local symbol, we want the same instruction | |
7206 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 7207 | addiu instruction. |
ed6fb7bd SC |
7208 | */ |
7209 | ||
4d7206a2 | 7210 | if (offset_expr.X_add_number == 0) |
252b5132 | 7211 | { |
0a44bf69 RS |
7212 | if (mips_pic == SVR4_PIC |
7213 | && breg == 0 | |
7214 | && (call || tempreg == PIC_CALL_REG)) | |
4d7206a2 RS |
7215 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; |
7216 | ||
7217 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
7218 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7219 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 7220 | if (breg != 0) |
252b5132 RH |
7221 | { |
7222 | /* We're going to put in an addu instruction using | |
7223 | tempreg, so we may as well insert the nop right | |
7224 | now. */ | |
269137b2 | 7225 | load_delay_nop (); |
252b5132 | 7226 | } |
4d7206a2 | 7227 | relax_switch (); |
67c0d1eb RS |
7228 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7229 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 7230 | load_delay_nop (); |
67c0d1eb RS |
7231 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7232 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 7233 | relax_end (); |
252b5132 RH |
7234 | /* FIXME: If breg == 0, and the next instruction uses |
7235 | $tempreg, then if this variant case is used an extra | |
7236 | nop will be generated. */ | |
7237 | } | |
4d7206a2 RS |
7238 | else if (offset_expr.X_add_number >= -0x8000 |
7239 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 7240 | { |
67c0d1eb | 7241 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 7242 | load_delay_nop (); |
67c0d1eb | 7243 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
7244 | } |
7245 | else | |
7246 | { | |
4d7206a2 RS |
7247 | expr1.X_add_number = offset_expr.X_add_number; |
7248 | offset_expr.X_add_number = | |
7249 | ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
67c0d1eb | 7250 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 7251 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
7252 | /* If we are going to add in a base register, and the |
7253 | target register and the base register are the same, | |
7254 | then we are using AT as a temporary register. Since | |
7255 | we want to load the constant into AT, we add our | |
7256 | current AT (from the global offset table) and the | |
7257 | register into the register now, and pretend we were | |
7258 | not using a base register. */ | |
67c0d1eb | 7259 | if (breg == treg) |
252b5132 | 7260 | { |
269137b2 | 7261 | load_delay_nop (); |
67c0d1eb | 7262 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7263 | treg, AT, breg); |
252b5132 RH |
7264 | breg = 0; |
7265 | tempreg = treg; | |
252b5132 | 7266 | } |
f6a22291 | 7267 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
7268 | used_at = 1; |
7269 | } | |
7270 | } | |
0a44bf69 | 7271 | else if (!mips_big_got && HAVE_NEWABI) |
f5040a92 | 7272 | { |
67c0d1eb | 7273 | int add_breg_early = 0; |
f5040a92 AO |
7274 | |
7275 | /* If this is a reference to an external, and there is no | |
7276 | constant, or local symbol (*), with or without a | |
7277 | constant, we want | |
7278 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 7279 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
7280 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
7281 | ||
7282 | If we have a small constant, and this is a reference to | |
7283 | an external symbol, we want | |
7284 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
7285 | addiu $tempreg,$tempreg,<constant> | |
7286 | ||
7287 | If we have a large constant, and this is a reference to | |
7288 | an external symbol, we want | |
7289 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
7290 | lui $at,<hiconstant> | |
7291 | addiu $at,$at,<loconstant> | |
7292 | addu $tempreg,$tempreg,$at | |
7293 | ||
7294 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
7295 | local symbols, even though it introduces an additional | |
7296 | instruction. */ | |
7297 | ||
f5040a92 AO |
7298 | if (offset_expr.X_add_number) |
7299 | { | |
4d7206a2 | 7300 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
7301 | offset_expr.X_add_number = 0; |
7302 | ||
4d7206a2 | 7303 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7304 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7305 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
7306 | |
7307 | if (expr1.X_add_number >= -0x8000 | |
7308 | && expr1.X_add_number < 0x8000) | |
7309 | { | |
67c0d1eb RS |
7310 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
7311 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 7312 | } |
ecd13cd3 | 7313 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 7314 | { |
f5040a92 AO |
7315 | /* If we are going to add in a base register, and the |
7316 | target register and the base register are the same, | |
7317 | then we are using AT as a temporary register. Since | |
7318 | we want to load the constant into AT, we add our | |
7319 | current AT (from the global offset table) and the | |
7320 | register into the register now, and pretend we were | |
7321 | not using a base register. */ | |
7322 | if (breg != treg) | |
7323 | dreg = tempreg; | |
7324 | else | |
7325 | { | |
9c2799c2 | 7326 | gas_assert (tempreg == AT); |
67c0d1eb RS |
7327 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
7328 | treg, AT, breg); | |
f5040a92 | 7329 | dreg = treg; |
67c0d1eb | 7330 | add_breg_early = 1; |
f5040a92 AO |
7331 | } |
7332 | ||
f6a22291 | 7333 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 7334 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7335 | dreg, dreg, AT); |
f5040a92 | 7336 | |
f5040a92 AO |
7337 | used_at = 1; |
7338 | } | |
7339 | else | |
7340 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
7341 | ||
4d7206a2 | 7342 | relax_switch (); |
f5040a92 AO |
7343 | offset_expr.X_add_number = expr1.X_add_number; |
7344 | ||
67c0d1eb RS |
7345 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7346 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
7347 | if (add_breg_early) | |
f5040a92 | 7348 | { |
67c0d1eb | 7349 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
f899b4b8 | 7350 | treg, tempreg, breg); |
f5040a92 AO |
7351 | breg = 0; |
7352 | tempreg = treg; | |
7353 | } | |
4d7206a2 | 7354 | relax_end (); |
f5040a92 | 7355 | } |
4d7206a2 | 7356 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 7357 | { |
4d7206a2 | 7358 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7359 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7360 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 7361 | relax_switch (); |
67c0d1eb RS |
7362 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7363 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 7364 | relax_end (); |
f5040a92 | 7365 | } |
4d7206a2 | 7366 | else |
f5040a92 | 7367 | { |
67c0d1eb RS |
7368 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7369 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
7370 | } |
7371 | } | |
0a44bf69 | 7372 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 7373 | { |
67c0d1eb | 7374 | int gpdelay; |
9117d219 NC |
7375 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
7376 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 7377 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
7378 | |
7379 | /* This is the large GOT case. If this is a reference to an | |
7380 | external symbol, and there is no constant, we want | |
7381 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7382 | addu $tempreg,$tempreg,$gp | |
7383 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 7384 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
7385 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
7386 | addu $tempreg,$tempreg,$gp | |
7387 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
7388 | For a local symbol, we want |
7389 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7390 | nop | |
7391 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7392 | ||
7393 | If we have a small constant, and this is a reference to | |
7394 | an external symbol, we want | |
7395 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7396 | addu $tempreg,$tempreg,$gp | |
7397 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7398 | nop | |
7399 | addiu $tempreg,$tempreg,<constant> | |
7400 | For a local symbol, we want | |
7401 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7402 | nop | |
7403 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
7404 | ||
7405 | If we have a large constant, and this is a reference to | |
7406 | an external symbol, we want | |
7407 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7408 | addu $tempreg,$tempreg,$gp | |
7409 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7410 | lui $at,<hiconstant> | |
7411 | addiu $at,$at,<loconstant> | |
7412 | addu $tempreg,$tempreg,$at | |
7413 | For a local symbol, we want | |
7414 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7415 | lui $at,<hiconstant> | |
7416 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
7417 | addu $tempreg,$tempreg,$at | |
f5040a92 | 7418 | */ |
438c16b8 | 7419 | |
252b5132 RH |
7420 | expr1.X_add_number = offset_expr.X_add_number; |
7421 | offset_expr.X_add_number = 0; | |
4d7206a2 | 7422 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 7423 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
7424 | if (expr1.X_add_number == 0 && breg == 0 |
7425 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
7426 | { |
7427 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
7428 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
7429 | } | |
df58fc94 | 7430 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 7431 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7432 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 7433 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 7434 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
7435 | if (expr1.X_add_number == 0) |
7436 | { | |
67c0d1eb | 7437 | if (breg != 0) |
252b5132 RH |
7438 | { |
7439 | /* We're going to put in an addu instruction using | |
7440 | tempreg, so we may as well insert the nop right | |
7441 | now. */ | |
269137b2 | 7442 | load_delay_nop (); |
252b5132 | 7443 | } |
252b5132 RH |
7444 | } |
7445 | else if (expr1.X_add_number >= -0x8000 | |
7446 | && expr1.X_add_number < 0x8000) | |
7447 | { | |
269137b2 | 7448 | load_delay_nop (); |
67c0d1eb | 7449 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 7450 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
7451 | } |
7452 | else | |
7453 | { | |
252b5132 RH |
7454 | /* If we are going to add in a base register, and the |
7455 | target register and the base register are the same, | |
7456 | then we are using AT as a temporary register. Since | |
7457 | we want to load the constant into AT, we add our | |
7458 | current AT (from the global offset table) and the | |
7459 | register into the register now, and pretend we were | |
7460 | not using a base register. */ | |
7461 | if (breg != treg) | |
67c0d1eb | 7462 | dreg = tempreg; |
252b5132 RH |
7463 | else |
7464 | { | |
9c2799c2 | 7465 | gas_assert (tempreg == AT); |
269137b2 | 7466 | load_delay_nop (); |
67c0d1eb | 7467 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7468 | treg, AT, breg); |
252b5132 | 7469 | dreg = treg; |
252b5132 RH |
7470 | } |
7471 | ||
f6a22291 | 7472 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 7473 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 7474 | |
252b5132 RH |
7475 | used_at = 1; |
7476 | } | |
4d7206a2 RS |
7477 | offset_expr.X_add_number = |
7478 | ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
7479 | relax_switch (); | |
252b5132 | 7480 | |
67c0d1eb | 7481 | if (gpdelay) |
252b5132 RH |
7482 | { |
7483 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 7484 | the first instruction on the main stream does not. */ |
67c0d1eb | 7485 | macro_build (NULL, "nop", ""); |
252b5132 | 7486 | } |
ed6fb7bd | 7487 | |
67c0d1eb RS |
7488 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7489 | local_reloc_type, mips_gp_register); | |
f5040a92 | 7490 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
7491 | && expr1.X_add_number < 0x8000) |
7492 | { | |
269137b2 | 7493 | load_delay_nop (); |
67c0d1eb RS |
7494 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7495 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 7496 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
7497 | register, the external symbol case ended with a load, |
7498 | so if the symbol turns out to not be external, and | |
7499 | the next instruction uses tempreg, an unnecessary nop | |
7500 | will be inserted. */ | |
252b5132 RH |
7501 | } |
7502 | else | |
7503 | { | |
7504 | if (breg == treg) | |
7505 | { | |
7506 | /* We must add in the base register now, as in the | |
f5040a92 | 7507 | external symbol case. */ |
9c2799c2 | 7508 | gas_assert (tempreg == AT); |
269137b2 | 7509 | load_delay_nop (); |
67c0d1eb | 7510 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7511 | treg, AT, breg); |
252b5132 RH |
7512 | tempreg = treg; |
7513 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 7514 | it in in both cases. */ |
252b5132 RH |
7515 | breg = 0; |
7516 | } | |
7517 | ||
67c0d1eb RS |
7518 | macro_build_lui (&expr1, AT); |
7519 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 7520 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 7521 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7522 | tempreg, tempreg, AT); |
8fc2e39e | 7523 | used_at = 1; |
252b5132 | 7524 | } |
4d7206a2 | 7525 | relax_end (); |
252b5132 | 7526 | } |
0a44bf69 | 7527 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 7528 | { |
f5040a92 AO |
7529 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
7530 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 7531 | int add_breg_early = 0; |
f5040a92 AO |
7532 | |
7533 | /* This is the large GOT case. If this is a reference to an | |
7534 | external symbol, and there is no constant, we want | |
7535 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7536 | add $tempreg,$tempreg,$gp | |
7537 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 7538 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
7539 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
7540 | add $tempreg,$tempreg,$gp | |
7541 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
7542 | ||
7543 | If we have a small constant, and this is a reference to | |
7544 | an external symbol, we want | |
7545 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7546 | add $tempreg,$tempreg,$gp | |
7547 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7548 | addi $tempreg,$tempreg,<constant> | |
7549 | ||
7550 | If we have a large constant, and this is a reference to | |
7551 | an external symbol, we want | |
7552 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7553 | addu $tempreg,$tempreg,$gp | |
7554 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7555 | lui $at,<hiconstant> | |
7556 | addi $at,$at,<loconstant> | |
7557 | add $tempreg,$tempreg,$at | |
7558 | ||
7559 | If we have NewABI, and we know it's a local symbol, we want | |
7560 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
7561 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
7562 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
7563 | ||
4d7206a2 | 7564 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 7565 | |
4d7206a2 | 7566 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
7567 | offset_expr.X_add_number = 0; |
7568 | ||
1abe91b1 MR |
7569 | if (expr1.X_add_number == 0 && breg == 0 |
7570 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
7571 | { |
7572 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
7573 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
7574 | } | |
df58fc94 | 7575 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 7576 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7577 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
7578 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7579 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
7580 | |
7581 | if (expr1.X_add_number == 0) | |
4d7206a2 | 7582 | ; |
f5040a92 AO |
7583 | else if (expr1.X_add_number >= -0x8000 |
7584 | && expr1.X_add_number < 0x8000) | |
7585 | { | |
67c0d1eb | 7586 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 7587 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 7588 | } |
ecd13cd3 | 7589 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 7590 | { |
f5040a92 AO |
7591 | /* If we are going to add in a base register, and the |
7592 | target register and the base register are the same, | |
7593 | then we are using AT as a temporary register. Since | |
7594 | we want to load the constant into AT, we add our | |
7595 | current AT (from the global offset table) and the | |
7596 | register into the register now, and pretend we were | |
7597 | not using a base register. */ | |
7598 | if (breg != treg) | |
7599 | dreg = tempreg; | |
7600 | else | |
7601 | { | |
9c2799c2 | 7602 | gas_assert (tempreg == AT); |
67c0d1eb | 7603 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7604 | treg, AT, breg); |
f5040a92 | 7605 | dreg = treg; |
67c0d1eb | 7606 | add_breg_early = 1; |
f5040a92 AO |
7607 | } |
7608 | ||
f6a22291 | 7609 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 7610 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 7611 | |
f5040a92 AO |
7612 | used_at = 1; |
7613 | } | |
7614 | else | |
7615 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
7616 | ||
4d7206a2 | 7617 | relax_switch (); |
f5040a92 | 7618 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
7619 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7620 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
7621 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
7622 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
7623 | if (add_breg_early) | |
f5040a92 | 7624 | { |
67c0d1eb | 7625 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7626 | treg, tempreg, breg); |
f5040a92 AO |
7627 | breg = 0; |
7628 | tempreg = treg; | |
7629 | } | |
4d7206a2 | 7630 | relax_end (); |
f5040a92 | 7631 | } |
252b5132 RH |
7632 | else |
7633 | abort (); | |
7634 | ||
7635 | if (breg != 0) | |
aed1a261 | 7636 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg); |
252b5132 RH |
7637 | break; |
7638 | ||
52b6b6b9 | 7639 | case M_MSGSND: |
df58fc94 | 7640 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
7641 | { |
7642 | unsigned long temp = (treg << 16) | (0x01); | |
7643 | macro_build (NULL, "c2", "C", temp); | |
7644 | } | |
c7af4273 | 7645 | break; |
52b6b6b9 JM |
7646 | |
7647 | case M_MSGLD: | |
df58fc94 | 7648 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
7649 | { |
7650 | unsigned long temp = (0x02); | |
7651 | macro_build (NULL, "c2", "C", temp); | |
7652 | } | |
c7af4273 | 7653 | break; |
52b6b6b9 JM |
7654 | |
7655 | case M_MSGLD_T: | |
df58fc94 | 7656 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
7657 | { |
7658 | unsigned long temp = (treg << 16) | (0x02); | |
7659 | macro_build (NULL, "c2", "C", temp); | |
7660 | } | |
c7af4273 | 7661 | break; |
52b6b6b9 JM |
7662 | |
7663 | case M_MSGWAIT: | |
df58fc94 | 7664 | gas_assert (!mips_opts.micromips); |
52b6b6b9 | 7665 | macro_build (NULL, "c2", "C", 3); |
c7af4273 | 7666 | break; |
52b6b6b9 JM |
7667 | |
7668 | case M_MSGWAIT_T: | |
df58fc94 | 7669 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
7670 | { |
7671 | unsigned long temp = (treg << 16) | 0x03; | |
7672 | macro_build (NULL, "c2", "C", temp); | |
7673 | } | |
c7af4273 | 7674 | break; |
52b6b6b9 | 7675 | |
252b5132 RH |
7676 | case M_J_A: |
7677 | /* The j instruction may not be used in PIC code, since it | |
7678 | requires an absolute address. We convert it to a b | |
7679 | instruction. */ | |
7680 | if (mips_pic == NO_PIC) | |
67c0d1eb | 7681 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 7682 | else |
67c0d1eb | 7683 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 7684 | break; |
252b5132 RH |
7685 | |
7686 | /* The jal instructions must be handled as macros because when | |
7687 | generating PIC code they expand to multi-instruction | |
7688 | sequences. Normally they are simple instructions. */ | |
df58fc94 RS |
7689 | case M_JALS_1: |
7690 | dreg = RA; | |
7691 | /* Fall through. */ | |
7692 | case M_JALS_2: | |
7693 | gas_assert (mips_opts.micromips); | |
7694 | jals = 1; | |
7695 | goto jal; | |
252b5132 RH |
7696 | case M_JAL_1: |
7697 | dreg = RA; | |
7698 | /* Fall through. */ | |
7699 | case M_JAL_2: | |
df58fc94 | 7700 | jal: |
3e722fb5 | 7701 | if (mips_pic == NO_PIC) |
df58fc94 RS |
7702 | { |
7703 | s = jals ? "jalrs" : "jalr"; | |
7704 | if (mips_opts.micromips && dreg == RA) | |
7705 | macro_build (NULL, s, "mj", sreg); | |
7706 | else | |
7707 | macro_build (NULL, s, JALR_FMT, dreg, sreg); | |
7708 | } | |
0a44bf69 | 7709 | else |
252b5132 | 7710 | { |
df58fc94 RS |
7711 | int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI |
7712 | && mips_cprestore_offset >= 0); | |
7713 | ||
252b5132 RH |
7714 | if (sreg != PIC_CALL_REG) |
7715 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 7716 | |
df58fc94 RS |
7717 | s = (mips_opts.micromips && (!mips_opts.noreorder || cprestore) |
7718 | ? "jalrs" : "jalr"); | |
7719 | if (mips_opts.micromips && dreg == RA) | |
7720 | macro_build (NULL, s, "mj", sreg); | |
7721 | else | |
7722 | macro_build (NULL, s, JALR_FMT, dreg, sreg); | |
0a44bf69 | 7723 | if (mips_pic == SVR4_PIC && !HAVE_NEWABI) |
252b5132 | 7724 | { |
6478892d TS |
7725 | if (mips_cprestore_offset < 0) |
7726 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
7727 | else | |
7728 | { | |
90ecf173 | 7729 | if (!mips_frame_reg_valid) |
7a621144 DJ |
7730 | { |
7731 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
7732 | /* Quiet this warning. */ | |
7733 | mips_frame_reg_valid = 1; | |
7734 | } | |
90ecf173 | 7735 | if (!mips_cprestore_valid) |
7a621144 DJ |
7736 | { |
7737 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
7738 | /* Quiet this warning. */ | |
7739 | mips_cprestore_valid = 1; | |
7740 | } | |
d3fca0b5 MR |
7741 | if (mips_opts.noreorder) |
7742 | macro_build (NULL, "nop", ""); | |
6478892d | 7743 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 7744 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 7745 | mips_gp_register, |
256ab948 TS |
7746 | mips_frame_reg, |
7747 | HAVE_64BIT_ADDRESSES); | |
6478892d | 7748 | } |
252b5132 RH |
7749 | } |
7750 | } | |
252b5132 | 7751 | |
8fc2e39e | 7752 | break; |
252b5132 | 7753 | |
df58fc94 RS |
7754 | case M_JALS_A: |
7755 | gas_assert (mips_opts.micromips); | |
7756 | jals = 1; | |
7757 | /* Fall through. */ | |
252b5132 RH |
7758 | case M_JAL_A: |
7759 | if (mips_pic == NO_PIC) | |
df58fc94 | 7760 | macro_build (&offset_expr, jals ? "jals" : "jal", "a"); |
252b5132 RH |
7761 | else if (mips_pic == SVR4_PIC) |
7762 | { | |
7763 | /* If this is a reference to an external symbol, and we are | |
7764 | using a small GOT, we want | |
7765 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
7766 | nop | |
f9419b05 | 7767 | jalr $ra,$25 |
252b5132 RH |
7768 | nop |
7769 | lw $gp,cprestore($sp) | |
7770 | The cprestore value is set using the .cprestore | |
7771 | pseudo-op. If we are using a big GOT, we want | |
7772 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
7773 | addu $25,$25,$gp | |
7774 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
7775 | nop | |
f9419b05 | 7776 | jalr $ra,$25 |
252b5132 RH |
7777 | nop |
7778 | lw $gp,cprestore($sp) | |
7779 | If the symbol is not external, we want | |
7780 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7781 | nop | |
7782 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 7783 | jalr $ra,$25 |
252b5132 | 7784 | nop |
438c16b8 | 7785 | lw $gp,cprestore($sp) |
f5040a92 AO |
7786 | |
7787 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
7788 | sequences above, minus nops, unless the symbol is local, | |
7789 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
7790 | GOT_DISP. */ | |
438c16b8 | 7791 | if (HAVE_NEWABI) |
252b5132 | 7792 | { |
90ecf173 | 7793 | if (!mips_big_got) |
f5040a92 | 7794 | { |
4d7206a2 | 7795 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7796 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7797 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 7798 | mips_gp_register); |
4d7206a2 | 7799 | relax_switch (); |
67c0d1eb RS |
7800 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7801 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
7802 | mips_gp_register); |
7803 | relax_end (); | |
f5040a92 AO |
7804 | } |
7805 | else | |
7806 | { | |
4d7206a2 | 7807 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 7808 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
7809 | BFD_RELOC_MIPS_CALL_HI16); |
7810 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
7811 | PIC_CALL_REG, mips_gp_register); | |
7812 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
7813 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
7814 | PIC_CALL_REG); | |
4d7206a2 | 7815 | relax_switch (); |
67c0d1eb RS |
7816 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7817 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
7818 | mips_gp_register); | |
7819 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
7820 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 7821 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 7822 | relax_end (); |
f5040a92 | 7823 | } |
684022ea | 7824 | |
df58fc94 | 7825 | macro_build_jalr (&offset_expr, 0); |
252b5132 RH |
7826 | } |
7827 | else | |
7828 | { | |
4d7206a2 | 7829 | relax_start (offset_expr.X_add_symbol); |
90ecf173 | 7830 | if (!mips_big_got) |
438c16b8 | 7831 | { |
67c0d1eb RS |
7832 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7833 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 7834 | mips_gp_register); |
269137b2 | 7835 | load_delay_nop (); |
4d7206a2 | 7836 | relax_switch (); |
438c16b8 | 7837 | } |
252b5132 | 7838 | else |
252b5132 | 7839 | { |
67c0d1eb RS |
7840 | int gpdelay; |
7841 | ||
7842 | gpdelay = reg_needs_delay (mips_gp_register); | |
df58fc94 | 7843 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
7844 | BFD_RELOC_MIPS_CALL_HI16); |
7845 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
7846 | PIC_CALL_REG, mips_gp_register); | |
7847 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
7848 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
7849 | PIC_CALL_REG); | |
269137b2 | 7850 | load_delay_nop (); |
4d7206a2 | 7851 | relax_switch (); |
67c0d1eb RS |
7852 | if (gpdelay) |
7853 | macro_build (NULL, "nop", ""); | |
252b5132 | 7854 | } |
67c0d1eb RS |
7855 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7856 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 7857 | mips_gp_register); |
269137b2 | 7858 | load_delay_nop (); |
67c0d1eb RS |
7859 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7860 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 7861 | relax_end (); |
df58fc94 | 7862 | macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0); |
438c16b8 | 7863 | |
6478892d TS |
7864 | if (mips_cprestore_offset < 0) |
7865 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
7866 | else | |
7867 | { | |
90ecf173 | 7868 | if (!mips_frame_reg_valid) |
7a621144 DJ |
7869 | { |
7870 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
7871 | /* Quiet this warning. */ | |
7872 | mips_frame_reg_valid = 1; | |
7873 | } | |
90ecf173 | 7874 | if (!mips_cprestore_valid) |
7a621144 DJ |
7875 | { |
7876 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
7877 | /* Quiet this warning. */ | |
7878 | mips_cprestore_valid = 1; | |
7879 | } | |
6478892d | 7880 | if (mips_opts.noreorder) |
67c0d1eb | 7881 | macro_build (NULL, "nop", ""); |
6478892d | 7882 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 7883 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 7884 | mips_gp_register, |
256ab948 TS |
7885 | mips_frame_reg, |
7886 | HAVE_64BIT_ADDRESSES); | |
6478892d | 7887 | } |
252b5132 RH |
7888 | } |
7889 | } | |
0a44bf69 RS |
7890 | else if (mips_pic == VXWORKS_PIC) |
7891 | as_bad (_("Non-PIC jump used in PIC library")); | |
252b5132 RH |
7892 | else |
7893 | abort (); | |
7894 | ||
8fc2e39e | 7895 | break; |
252b5132 | 7896 | |
dec0624d MR |
7897 | case M_ACLR_AB: |
7898 | ab = 1; | |
7899 | case M_ACLR_OB: | |
7900 | s = "aclr"; | |
7901 | treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip); | |
7902 | fmt = "\\,~(b)"; | |
7903 | off12 = 1; | |
7904 | goto ld_st; | |
7905 | case M_ASET_AB: | |
7906 | ab = 1; | |
7907 | case M_ASET_OB: | |
7908 | s = "aset"; | |
7909 | treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip); | |
7910 | fmt = "\\,~(b)"; | |
7911 | off12 = 1; | |
7912 | goto ld_st; | |
252b5132 | 7913 | case M_LB_AB: |
df58fc94 | 7914 | ab = 1; |
252b5132 | 7915 | s = "lb"; |
df58fc94 | 7916 | fmt = "t,o(b)"; |
252b5132 RH |
7917 | goto ld; |
7918 | case M_LBU_AB: | |
df58fc94 | 7919 | ab = 1; |
252b5132 | 7920 | s = "lbu"; |
df58fc94 | 7921 | fmt = "t,o(b)"; |
252b5132 RH |
7922 | goto ld; |
7923 | case M_LH_AB: | |
df58fc94 | 7924 | ab = 1; |
252b5132 | 7925 | s = "lh"; |
df58fc94 | 7926 | fmt = "t,o(b)"; |
252b5132 RH |
7927 | goto ld; |
7928 | case M_LHU_AB: | |
df58fc94 | 7929 | ab = 1; |
252b5132 | 7930 | s = "lhu"; |
df58fc94 | 7931 | fmt = "t,o(b)"; |
252b5132 RH |
7932 | goto ld; |
7933 | case M_LW_AB: | |
df58fc94 | 7934 | ab = 1; |
252b5132 | 7935 | s = "lw"; |
df58fc94 | 7936 | fmt = "t,o(b)"; |
252b5132 RH |
7937 | goto ld; |
7938 | case M_LWC0_AB: | |
df58fc94 RS |
7939 | ab = 1; |
7940 | gas_assert (!mips_opts.micromips); | |
252b5132 | 7941 | s = "lwc0"; |
df58fc94 | 7942 | fmt = "E,o(b)"; |
bdaaa2e1 | 7943 | /* Itbl support may require additional care here. */ |
252b5132 | 7944 | coproc = 1; |
df58fc94 | 7945 | goto ld_st; |
252b5132 | 7946 | case M_LWC1_AB: |
df58fc94 | 7947 | ab = 1; |
252b5132 | 7948 | s = "lwc1"; |
df58fc94 | 7949 | fmt = "T,o(b)"; |
bdaaa2e1 | 7950 | /* Itbl support may require additional care here. */ |
252b5132 | 7951 | coproc = 1; |
df58fc94 | 7952 | goto ld_st; |
252b5132 | 7953 | case M_LWC2_AB: |
df58fc94 RS |
7954 | ab = 1; |
7955 | case M_LWC2_OB: | |
252b5132 | 7956 | s = "lwc2"; |
df58fc94 RS |
7957 | fmt = COP12_FMT; |
7958 | off12 = mips_opts.micromips; | |
bdaaa2e1 | 7959 | /* Itbl support may require additional care here. */ |
252b5132 | 7960 | coproc = 1; |
df58fc94 | 7961 | goto ld_st; |
252b5132 | 7962 | case M_LWC3_AB: |
df58fc94 RS |
7963 | ab = 1; |
7964 | gas_assert (!mips_opts.micromips); | |
252b5132 | 7965 | s = "lwc3"; |
df58fc94 | 7966 | fmt = "E,o(b)"; |
bdaaa2e1 | 7967 | /* Itbl support may require additional care here. */ |
252b5132 | 7968 | coproc = 1; |
df58fc94 | 7969 | goto ld_st; |
252b5132 | 7970 | case M_LWL_AB: |
df58fc94 RS |
7971 | ab = 1; |
7972 | case M_LWL_OB: | |
252b5132 | 7973 | s = "lwl"; |
df58fc94 RS |
7974 | fmt = MEM12_FMT; |
7975 | off12 = mips_opts.micromips; | |
7976 | goto ld_st; | |
252b5132 | 7977 | case M_LWR_AB: |
df58fc94 RS |
7978 | ab = 1; |
7979 | case M_LWR_OB: | |
252b5132 | 7980 | s = "lwr"; |
df58fc94 RS |
7981 | fmt = MEM12_FMT; |
7982 | off12 = mips_opts.micromips; | |
7983 | goto ld_st; | |
252b5132 | 7984 | case M_LDC1_AB: |
df58fc94 | 7985 | ab = 1; |
252b5132 | 7986 | s = "ldc1"; |
df58fc94 | 7987 | fmt = "T,o(b)"; |
bdaaa2e1 | 7988 | /* Itbl support may require additional care here. */ |
252b5132 | 7989 | coproc = 1; |
df58fc94 | 7990 | goto ld_st; |
252b5132 | 7991 | case M_LDC2_AB: |
df58fc94 RS |
7992 | ab = 1; |
7993 | case M_LDC2_OB: | |
252b5132 | 7994 | s = "ldc2"; |
df58fc94 RS |
7995 | fmt = COP12_FMT; |
7996 | off12 = mips_opts.micromips; | |
bdaaa2e1 | 7997 | /* Itbl support may require additional care here. */ |
252b5132 | 7998 | coproc = 1; |
df58fc94 | 7999 | goto ld_st; |
252b5132 | 8000 | case M_LDC3_AB: |
df58fc94 | 8001 | ab = 1; |
252b5132 | 8002 | s = "ldc3"; |
df58fc94 | 8003 | fmt = "E,o(b)"; |
bdaaa2e1 | 8004 | /* Itbl support may require additional care here. */ |
252b5132 | 8005 | coproc = 1; |
df58fc94 | 8006 | goto ld_st; |
252b5132 | 8007 | case M_LDL_AB: |
df58fc94 RS |
8008 | ab = 1; |
8009 | case M_LDL_OB: | |
252b5132 | 8010 | s = "ldl"; |
df58fc94 RS |
8011 | fmt = MEM12_FMT; |
8012 | off12 = mips_opts.micromips; | |
8013 | goto ld_st; | |
252b5132 | 8014 | case M_LDR_AB: |
df58fc94 RS |
8015 | ab = 1; |
8016 | case M_LDR_OB: | |
252b5132 | 8017 | s = "ldr"; |
df58fc94 RS |
8018 | fmt = MEM12_FMT; |
8019 | off12 = mips_opts.micromips; | |
8020 | goto ld_st; | |
252b5132 | 8021 | case M_LL_AB: |
df58fc94 RS |
8022 | ab = 1; |
8023 | case M_LL_OB: | |
252b5132 | 8024 | s = "ll"; |
df58fc94 RS |
8025 | fmt = MEM12_FMT; |
8026 | off12 = mips_opts.micromips; | |
252b5132 RH |
8027 | goto ld; |
8028 | case M_LLD_AB: | |
df58fc94 RS |
8029 | ab = 1; |
8030 | case M_LLD_OB: | |
252b5132 | 8031 | s = "lld"; |
df58fc94 RS |
8032 | fmt = MEM12_FMT; |
8033 | off12 = mips_opts.micromips; | |
252b5132 RH |
8034 | goto ld; |
8035 | case M_LWU_AB: | |
df58fc94 RS |
8036 | ab = 1; |
8037 | case M_LWU_OB: | |
252b5132 | 8038 | s = "lwu"; |
df58fc94 RS |
8039 | fmt = MEM12_FMT; |
8040 | off12 = mips_opts.micromips; | |
8041 | goto ld; | |
8042 | case M_LWP_AB: | |
8043 | ab = 1; | |
8044 | case M_LWP_OB: | |
8045 | gas_assert (mips_opts.micromips); | |
8046 | s = "lwp"; | |
8047 | fmt = "t,~(b)"; | |
8048 | off12 = 1; | |
8049 | lp = 1; | |
8050 | goto ld; | |
8051 | case M_LDP_AB: | |
8052 | ab = 1; | |
8053 | case M_LDP_OB: | |
8054 | gas_assert (mips_opts.micromips); | |
8055 | s = "ldp"; | |
8056 | fmt = "t,~(b)"; | |
8057 | off12 = 1; | |
8058 | lp = 1; | |
8059 | goto ld; | |
8060 | case M_LWM_AB: | |
8061 | ab = 1; | |
8062 | case M_LWM_OB: | |
8063 | gas_assert (mips_opts.micromips); | |
8064 | s = "lwm"; | |
8065 | fmt = "n,~(b)"; | |
8066 | off12 = 1; | |
8067 | goto ld_st; | |
8068 | case M_LDM_AB: | |
8069 | ab = 1; | |
8070 | case M_LDM_OB: | |
8071 | gas_assert (mips_opts.micromips); | |
8072 | s = "ldm"; | |
8073 | fmt = "n,~(b)"; | |
8074 | off12 = 1; | |
8075 | goto ld_st; | |
8076 | ||
252b5132 | 8077 | ld: |
df58fc94 RS |
8078 | if (breg == treg + lp) |
8079 | goto ld_st; | |
252b5132 | 8080 | else |
df58fc94 RS |
8081 | tempreg = treg + lp; |
8082 | goto ld_noat; | |
8083 | ||
252b5132 | 8084 | case M_SB_AB: |
df58fc94 | 8085 | ab = 1; |
252b5132 | 8086 | s = "sb"; |
df58fc94 RS |
8087 | fmt = "t,o(b)"; |
8088 | goto ld_st; | |
252b5132 | 8089 | case M_SH_AB: |
df58fc94 | 8090 | ab = 1; |
252b5132 | 8091 | s = "sh"; |
df58fc94 RS |
8092 | fmt = "t,o(b)"; |
8093 | goto ld_st; | |
252b5132 | 8094 | case M_SW_AB: |
df58fc94 | 8095 | ab = 1; |
252b5132 | 8096 | s = "sw"; |
df58fc94 RS |
8097 | fmt = "t,o(b)"; |
8098 | goto ld_st; | |
252b5132 | 8099 | case M_SWC0_AB: |
df58fc94 RS |
8100 | ab = 1; |
8101 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8102 | s = "swc0"; |
df58fc94 | 8103 | fmt = "E,o(b)"; |
bdaaa2e1 | 8104 | /* Itbl support may require additional care here. */ |
252b5132 | 8105 | coproc = 1; |
df58fc94 | 8106 | goto ld_st; |
252b5132 | 8107 | case M_SWC1_AB: |
df58fc94 | 8108 | ab = 1; |
252b5132 | 8109 | s = "swc1"; |
df58fc94 | 8110 | fmt = "T,o(b)"; |
bdaaa2e1 | 8111 | /* Itbl support may require additional care here. */ |
252b5132 | 8112 | coproc = 1; |
df58fc94 | 8113 | goto ld_st; |
252b5132 | 8114 | case M_SWC2_AB: |
df58fc94 RS |
8115 | ab = 1; |
8116 | case M_SWC2_OB: | |
252b5132 | 8117 | s = "swc2"; |
df58fc94 RS |
8118 | fmt = COP12_FMT; |
8119 | off12 = mips_opts.micromips; | |
bdaaa2e1 | 8120 | /* Itbl support may require additional care here. */ |
252b5132 | 8121 | coproc = 1; |
df58fc94 | 8122 | goto ld_st; |
252b5132 | 8123 | case M_SWC3_AB: |
df58fc94 RS |
8124 | ab = 1; |
8125 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8126 | s = "swc3"; |
df58fc94 | 8127 | fmt = "E,o(b)"; |
bdaaa2e1 | 8128 | /* Itbl support may require additional care here. */ |
252b5132 | 8129 | coproc = 1; |
df58fc94 | 8130 | goto ld_st; |
252b5132 | 8131 | case M_SWL_AB: |
df58fc94 RS |
8132 | ab = 1; |
8133 | case M_SWL_OB: | |
252b5132 | 8134 | s = "swl"; |
df58fc94 RS |
8135 | fmt = MEM12_FMT; |
8136 | off12 = mips_opts.micromips; | |
8137 | goto ld_st; | |
252b5132 | 8138 | case M_SWR_AB: |
df58fc94 RS |
8139 | ab = 1; |
8140 | case M_SWR_OB: | |
252b5132 | 8141 | s = "swr"; |
df58fc94 RS |
8142 | fmt = MEM12_FMT; |
8143 | off12 = mips_opts.micromips; | |
8144 | goto ld_st; | |
252b5132 | 8145 | case M_SC_AB: |
df58fc94 RS |
8146 | ab = 1; |
8147 | case M_SC_OB: | |
252b5132 | 8148 | s = "sc"; |
df58fc94 RS |
8149 | fmt = MEM12_FMT; |
8150 | off12 = mips_opts.micromips; | |
8151 | goto ld_st; | |
252b5132 | 8152 | case M_SCD_AB: |
df58fc94 RS |
8153 | ab = 1; |
8154 | case M_SCD_OB: | |
252b5132 | 8155 | s = "scd"; |
df58fc94 RS |
8156 | fmt = MEM12_FMT; |
8157 | off12 = mips_opts.micromips; | |
8158 | goto ld_st; | |
d43b4baf | 8159 | case M_CACHE_AB: |
df58fc94 RS |
8160 | ab = 1; |
8161 | case M_CACHE_OB: | |
d43b4baf | 8162 | s = "cache"; |
df58fc94 RS |
8163 | fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)"; |
8164 | off12 = mips_opts.micromips; | |
8165 | goto ld_st; | |
3eebd5eb | 8166 | case M_PREF_AB: |
df58fc94 RS |
8167 | ab = 1; |
8168 | case M_PREF_OB: | |
3eebd5eb | 8169 | s = "pref"; |
df58fc94 RS |
8170 | fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)"; |
8171 | off12 = mips_opts.micromips; | |
8172 | goto ld_st; | |
252b5132 | 8173 | case M_SDC1_AB: |
df58fc94 | 8174 | ab = 1; |
252b5132 | 8175 | s = "sdc1"; |
df58fc94 | 8176 | fmt = "T,o(b)"; |
252b5132 | 8177 | coproc = 1; |
bdaaa2e1 | 8178 | /* Itbl support may require additional care here. */ |
df58fc94 | 8179 | goto ld_st; |
252b5132 | 8180 | case M_SDC2_AB: |
df58fc94 RS |
8181 | ab = 1; |
8182 | case M_SDC2_OB: | |
252b5132 | 8183 | s = "sdc2"; |
df58fc94 RS |
8184 | fmt = COP12_FMT; |
8185 | off12 = mips_opts.micromips; | |
bdaaa2e1 | 8186 | /* Itbl support may require additional care here. */ |
252b5132 | 8187 | coproc = 1; |
df58fc94 | 8188 | goto ld_st; |
252b5132 | 8189 | case M_SDC3_AB: |
df58fc94 RS |
8190 | ab = 1; |
8191 | gas_assert (!mips_opts.micromips); | |
252b5132 | 8192 | s = "sdc3"; |
df58fc94 | 8193 | fmt = "E,o(b)"; |
bdaaa2e1 | 8194 | /* Itbl support may require additional care here. */ |
252b5132 | 8195 | coproc = 1; |
df58fc94 | 8196 | goto ld_st; |
252b5132 | 8197 | case M_SDL_AB: |
df58fc94 RS |
8198 | ab = 1; |
8199 | case M_SDL_OB: | |
252b5132 | 8200 | s = "sdl"; |
df58fc94 RS |
8201 | fmt = MEM12_FMT; |
8202 | off12 = mips_opts.micromips; | |
8203 | goto ld_st; | |
252b5132 | 8204 | case M_SDR_AB: |
df58fc94 RS |
8205 | ab = 1; |
8206 | case M_SDR_OB: | |
252b5132 | 8207 | s = "sdr"; |
df58fc94 RS |
8208 | fmt = MEM12_FMT; |
8209 | off12 = mips_opts.micromips; | |
8210 | goto ld_st; | |
8211 | case M_SWP_AB: | |
8212 | ab = 1; | |
8213 | case M_SWP_OB: | |
8214 | gas_assert (mips_opts.micromips); | |
8215 | s = "swp"; | |
8216 | fmt = "t,~(b)"; | |
8217 | off12 = 1; | |
8218 | goto ld_st; | |
8219 | case M_SDP_AB: | |
8220 | ab = 1; | |
8221 | case M_SDP_OB: | |
8222 | gas_assert (mips_opts.micromips); | |
8223 | s = "sdp"; | |
8224 | fmt = "t,~(b)"; | |
8225 | off12 = 1; | |
8226 | goto ld_st; | |
8227 | case M_SWM_AB: | |
8228 | ab = 1; | |
8229 | case M_SWM_OB: | |
8230 | gas_assert (mips_opts.micromips); | |
8231 | s = "swm"; | |
8232 | fmt = "n,~(b)"; | |
8233 | off12 = 1; | |
8234 | goto ld_st; | |
8235 | case M_SDM_AB: | |
8236 | ab = 1; | |
8237 | case M_SDM_OB: | |
8238 | gas_assert (mips_opts.micromips); | |
8239 | s = "sdm"; | |
8240 | fmt = "n,~(b)"; | |
8241 | off12 = 1; | |
8242 | ||
8243 | ld_st: | |
8fc2e39e TS |
8244 | tempreg = AT; |
8245 | used_at = 1; | |
df58fc94 | 8246 | ld_noat: |
b19e8a9b AN |
8247 | if (coproc |
8248 | && NO_ISA_COP (mips_opts.arch) | |
8249 | && (ip->insn_mo->pinfo2 & (INSN2_M_FP_S | INSN2_M_FP_D)) == 0) | |
8250 | { | |
f71d0d44 | 8251 | as_bad (_("Opcode not supported on this processor: %s"), |
b19e8a9b AN |
8252 | mips_cpu_info_from_arch (mips_opts.arch)->name); |
8253 | break; | |
8254 | } | |
8255 | ||
252b5132 RH |
8256 | if (offset_expr.X_op != O_constant |
8257 | && offset_expr.X_op != O_symbol) | |
8258 | { | |
f71d0d44 | 8259 | as_bad (_("Expression too complex")); |
252b5132 RH |
8260 | offset_expr.X_op = O_constant; |
8261 | } | |
8262 | ||
2051e8c4 MR |
8263 | if (HAVE_32BIT_ADDRESSES |
8264 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
8265 | { |
8266 | char value [32]; | |
8267 | ||
8268 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 8269 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 8270 | } |
2051e8c4 | 8271 | |
252b5132 RH |
8272 | /* A constant expression in PIC code can be handled just as it |
8273 | is in non PIC code. */ | |
aed1a261 RS |
8274 | if (offset_expr.X_op == O_constant) |
8275 | { | |
df58fc94 RS |
8276 | int hipart = 0; |
8277 | ||
842f8b2a | 8278 | expr1.X_add_number = offset_expr.X_add_number; |
2051e8c4 | 8279 | normalize_address_expr (&expr1); |
df58fc94 | 8280 | if (!off12 && !IS_SEXT_16BIT_NUM (expr1.X_add_number)) |
842f8b2a MR |
8281 | { |
8282 | expr1.X_add_number = ((expr1.X_add_number + 0x8000) | |
8283 | & ~(bfd_vma) 0xffff); | |
df58fc94 RS |
8284 | hipart = 1; |
8285 | } | |
8286 | else if (off12 && !IS_SEXT_12BIT_NUM (expr1.X_add_number)) | |
8287 | { | |
8288 | expr1.X_add_number = ((expr1.X_add_number + 0x800) | |
8289 | & ~(bfd_vma) 0xfff); | |
8290 | hipart = 1; | |
8291 | } | |
8292 | if (hipart) | |
8293 | { | |
842f8b2a MR |
8294 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); |
8295 | if (breg != 0) | |
8296 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
8297 | tempreg, tempreg, breg); | |
8298 | breg = tempreg; | |
8299 | } | |
df58fc94 RS |
8300 | if (!off12) |
8301 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg); | |
8302 | else | |
8303 | macro_build (NULL, s, fmt, | |
8304 | treg, (unsigned long) offset_expr.X_add_number, breg); | |
8305 | } | |
8306 | else if (off12) | |
8307 | { | |
8308 | /* A 12-bit offset field is too narrow to be used for a low-part | |
8309 | relocation, so load the whole address into the auxillary | |
8310 | register. In the case of "A(b)" addresses, we first load | |
8311 | absolute address "A" into the register and then add base | |
8312 | register "b". In the case of "o(b)" addresses, we simply | |
8313 | need to add 16-bit offset "o" to base register "b", and | |
8314 | offset_reloc already contains the relocations associated | |
8315 | with "o". */ | |
8316 | if (ab) | |
8317 | { | |
8318 | load_address (tempreg, &offset_expr, &used_at); | |
8319 | if (breg != 0) | |
8320 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
8321 | tempreg, tempreg, breg); | |
8322 | } | |
8323 | else | |
8324 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
8325 | tempreg, breg, -1, | |
8326 | offset_reloc[0], offset_reloc[1], offset_reloc[2]); | |
8327 | expr1.X_add_number = 0; | |
8328 | macro_build (NULL, s, fmt, | |
8329 | treg, (unsigned long) expr1.X_add_number, tempreg); | |
aed1a261 RS |
8330 | } |
8331 | else if (mips_pic == NO_PIC) | |
252b5132 RH |
8332 | { |
8333 | /* If this is a reference to a GP relative symbol, and there | |
8334 | is no base register, we want | |
cdf6fd85 | 8335 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
8336 | Otherwise, if there is no base register, we want |
8337 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8338 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8339 | If we have a constant, we need two instructions anyhow, | |
8340 | so we always use the latter form. | |
8341 | ||
8342 | If we have a base register, and this is a reference to a | |
8343 | GP relative symbol, we want | |
8344 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 8345 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
8346 | Otherwise we want |
8347 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8348 | addu $tempreg,$tempreg,$breg | |
8349 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 8350 | With a constant we always use the latter case. |
76b3015f | 8351 | |
d6bc6245 TS |
8352 | With 64bit address space and no base register and $at usable, |
8353 | we want | |
8354 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8355 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
8356 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8357 | dsll32 $tempreg,0 | |
8358 | daddu $tempreg,$at | |
8359 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8360 | If we have a base register, we want | |
8361 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8362 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
8363 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8364 | daddu $at,$breg | |
8365 | dsll32 $tempreg,0 | |
8366 | daddu $tempreg,$at | |
8367 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8368 | ||
8369 | Without $at we can't generate the optimal path for superscalar | |
8370 | processors here since this would require two temporary registers. | |
8371 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8372 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8373 | dsll $tempreg,16 | |
8374 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8375 | dsll $tempreg,16 | |
8376 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8377 | If we have a base register, we want | |
8378 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8379 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8380 | dsll $tempreg,16 | |
8381 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8382 | dsll $tempreg,16 | |
8383 | daddu $tempreg,$tempreg,$breg | |
8384 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 | 8385 | |
6caf9ef4 | 8386 | For GP relative symbols in 64bit address space we can use |
aed1a261 RS |
8387 | the same sequence as in 32bit address space. */ |
8388 | if (HAVE_64BIT_SYMBOLS) | |
d6bc6245 | 8389 | { |
aed1a261 | 8390 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 TS |
8391 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
8392 | { | |
8393 | relax_start (offset_expr.X_add_symbol); | |
8394 | if (breg == 0) | |
8395 | { | |
8396 | macro_build (&offset_expr, s, fmt, treg, | |
8397 | BFD_RELOC_GPREL16, mips_gp_register); | |
8398 | } | |
8399 | else | |
8400 | { | |
8401 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
8402 | tempreg, breg, mips_gp_register); | |
8403 | macro_build (&offset_expr, s, fmt, treg, | |
8404 | BFD_RELOC_GPREL16, tempreg); | |
8405 | } | |
8406 | relax_switch (); | |
8407 | } | |
d6bc6245 | 8408 | |
741fe287 | 8409 | if (used_at == 0 && mips_opts.at) |
d6bc6245 | 8410 | { |
df58fc94 | 8411 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb | 8412 | BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 8413 | macro_build (&offset_expr, "lui", LUI_FMT, AT, |
67c0d1eb RS |
8414 | BFD_RELOC_HI16_S); |
8415 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
8416 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 8417 | if (breg != 0) |
67c0d1eb | 8418 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
df58fc94 | 8419 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb RS |
8420 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
8421 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, | |
8422 | tempreg); | |
d6bc6245 TS |
8423 | used_at = 1; |
8424 | } | |
8425 | else | |
8426 | { | |
df58fc94 | 8427 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb RS |
8428 | BFD_RELOC_MIPS_HIGHEST); |
8429 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
8430 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 8431 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb RS |
8432 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, |
8433 | tempreg, BFD_RELOC_HI16_S); | |
df58fc94 | 8434 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
d6bc6245 | 8435 | if (breg != 0) |
67c0d1eb | 8436 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 8437 | tempreg, tempreg, breg); |
67c0d1eb | 8438 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8439 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 8440 | } |
6caf9ef4 TS |
8441 | |
8442 | if (mips_relax.sequence) | |
8443 | relax_end (); | |
8fc2e39e | 8444 | break; |
d6bc6245 | 8445 | } |
256ab948 | 8446 | |
252b5132 RH |
8447 | if (breg == 0) |
8448 | { | |
67c0d1eb | 8449 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 8450 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 8451 | { |
4d7206a2 | 8452 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
8453 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, |
8454 | mips_gp_register); | |
4d7206a2 | 8455 | relax_switch (); |
252b5132 | 8456 | } |
67c0d1eb RS |
8457 | macro_build_lui (&offset_expr, tempreg); |
8458 | macro_build (&offset_expr, s, fmt, treg, | |
17a2f251 | 8459 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
8460 | if (mips_relax.sequence) |
8461 | relax_end (); | |
252b5132 RH |
8462 | } |
8463 | else | |
8464 | { | |
67c0d1eb | 8465 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 8466 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 8467 | { |
4d7206a2 | 8468 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 8469 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8470 | tempreg, breg, mips_gp_register); |
67c0d1eb | 8471 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8472 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 8473 | relax_switch (); |
252b5132 | 8474 | } |
67c0d1eb RS |
8475 | macro_build_lui (&offset_expr, tempreg); |
8476 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 8477 | tempreg, tempreg, breg); |
67c0d1eb | 8478 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8479 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
8480 | if (mips_relax.sequence) |
8481 | relax_end (); | |
252b5132 RH |
8482 | } |
8483 | } | |
0a44bf69 | 8484 | else if (!mips_big_got) |
252b5132 | 8485 | { |
ed6fb7bd | 8486 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 8487 | |
252b5132 RH |
8488 | /* If this is a reference to an external symbol, we want |
8489 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
8490 | nop | |
8491 | <op> $treg,0($tempreg) | |
8492 | Otherwise we want | |
8493 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
8494 | nop | |
8495 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
8496 | <op> $treg,0($tempreg) | |
f5040a92 AO |
8497 | |
8498 | For NewABI, we want | |
8499 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
8500 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
8501 | ||
252b5132 RH |
8502 | If there is a base register, we add it to $tempreg before |
8503 | the <op>. If there is a constant, we stick it in the | |
8504 | <op> instruction. We don't handle constants larger than | |
8505 | 16 bits, because we have no way to load the upper 16 bits | |
8506 | (actually, we could handle them for the subset of cases | |
8507 | in which we are not using $at). */ | |
9c2799c2 | 8508 | gas_assert (offset_expr.X_op == O_symbol); |
f5040a92 AO |
8509 | if (HAVE_NEWABI) |
8510 | { | |
67c0d1eb RS |
8511 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
8512 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 8513 | if (breg != 0) |
67c0d1eb | 8514 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8515 | tempreg, tempreg, breg); |
67c0d1eb | 8516 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8517 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
8518 | break; |
8519 | } | |
252b5132 RH |
8520 | expr1.X_add_number = offset_expr.X_add_number; |
8521 | offset_expr.X_add_number = 0; | |
8522 | if (expr1.X_add_number < -0x8000 | |
8523 | || expr1.X_add_number >= 0x8000) | |
8524 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
8525 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
8526 | lw_reloc_type, mips_gp_register); | |
269137b2 | 8527 | load_delay_nop (); |
4d7206a2 RS |
8528 | relax_start (offset_expr.X_add_symbol); |
8529 | relax_switch (); | |
67c0d1eb RS |
8530 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
8531 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 8532 | relax_end (); |
252b5132 | 8533 | if (breg != 0) |
67c0d1eb | 8534 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8535 | tempreg, tempreg, breg); |
67c0d1eb | 8536 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 8537 | } |
0a44bf69 | 8538 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 8539 | { |
67c0d1eb | 8540 | int gpdelay; |
252b5132 RH |
8541 | |
8542 | /* If this is a reference to an external symbol, we want | |
8543 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
8544 | addu $tempreg,$tempreg,$gp | |
8545 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
8546 | <op> $treg,0($tempreg) | |
8547 | Otherwise we want | |
8548 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
8549 | nop | |
8550 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
8551 | <op> $treg,0($tempreg) | |
8552 | If there is a base register, we add it to $tempreg before | |
8553 | the <op>. If there is a constant, we stick it in the | |
8554 | <op> instruction. We don't handle constants larger than | |
8555 | 16 bits, because we have no way to load the upper 16 bits | |
8556 | (actually, we could handle them for the subset of cases | |
f5040a92 | 8557 | in which we are not using $at). */ |
9c2799c2 | 8558 | gas_assert (offset_expr.X_op == O_symbol); |
252b5132 RH |
8559 | expr1.X_add_number = offset_expr.X_add_number; |
8560 | offset_expr.X_add_number = 0; | |
8561 | if (expr1.X_add_number < -0x8000 | |
8562 | || expr1.X_add_number >= 0x8000) | |
8563 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 8564 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 8565 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 8566 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 8567 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
8568 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
8569 | mips_gp_register); | |
8570 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
8571 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 8572 | relax_switch (); |
67c0d1eb RS |
8573 | if (gpdelay) |
8574 | macro_build (NULL, "nop", ""); | |
8575 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
8576 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 8577 | load_delay_nop (); |
67c0d1eb RS |
8578 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
8579 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
8580 | relax_end (); |
8581 | ||
252b5132 | 8582 | if (breg != 0) |
67c0d1eb | 8583 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8584 | tempreg, tempreg, breg); |
67c0d1eb | 8585 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 8586 | } |
0a44bf69 | 8587 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 8588 | { |
f5040a92 AO |
8589 | /* If this is a reference to an external symbol, we want |
8590 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
8591 | add $tempreg,$tempreg,$gp | |
8592 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
8593 | <op> $treg,<ofst>($tempreg) | |
8594 | Otherwise, for local symbols, we want: | |
8595 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
8596 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
9c2799c2 | 8597 | gas_assert (offset_expr.X_op == O_symbol); |
4d7206a2 | 8598 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
8599 | offset_expr.X_add_number = 0; |
8600 | if (expr1.X_add_number < -0x8000 | |
8601 | || expr1.X_add_number >= 0x8000) | |
8602 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 8603 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 8604 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 8605 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
8606 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
8607 | mips_gp_register); | |
8608 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
8609 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 8610 | if (breg != 0) |
67c0d1eb | 8611 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8612 | tempreg, tempreg, breg); |
67c0d1eb | 8613 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
684022ea | 8614 | |
4d7206a2 | 8615 | relax_switch (); |
f5040a92 | 8616 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
8617 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
8618 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 8619 | if (breg != 0) |
67c0d1eb | 8620 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8621 | tempreg, tempreg, breg); |
67c0d1eb | 8622 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 8623 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 8624 | relax_end (); |
f5040a92 | 8625 | } |
252b5132 RH |
8626 | else |
8627 | abort (); | |
8628 | ||
252b5132 RH |
8629 | break; |
8630 | ||
8631 | case M_LI: | |
8632 | case M_LI_S: | |
67c0d1eb | 8633 | load_register (treg, &imm_expr, 0); |
8fc2e39e | 8634 | break; |
252b5132 RH |
8635 | |
8636 | case M_DLI: | |
67c0d1eb | 8637 | load_register (treg, &imm_expr, 1); |
8fc2e39e | 8638 | break; |
252b5132 RH |
8639 | |
8640 | case M_LI_SS: | |
8641 | if (imm_expr.X_op == O_constant) | |
8642 | { | |
8fc2e39e | 8643 | used_at = 1; |
67c0d1eb RS |
8644 | load_register (AT, &imm_expr, 0); |
8645 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
8646 | break; |
8647 | } | |
8648 | else | |
8649 | { | |
9c2799c2 | 8650 | gas_assert (offset_expr.X_op == O_symbol |
90ecf173 MR |
8651 | && strcmp (segment_name (S_GET_SEGMENT |
8652 | (offset_expr.X_add_symbol)), | |
8653 | ".lit4") == 0 | |
8654 | && offset_expr.X_add_number == 0); | |
67c0d1eb | 8655 | macro_build (&offset_expr, "lwc1", "T,o(b)", treg, |
17a2f251 | 8656 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 8657 | break; |
252b5132 RH |
8658 | } |
8659 | ||
8660 | case M_LI_D: | |
ca4e0257 RS |
8661 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
8662 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
8663 | order 32 bits of the value and the low order 32 bits are either | |
8664 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
8665 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
8666 | { | |
ca4e0257 | 8667 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 8668 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
8669 | else |
8670 | { | |
8671 | int hreg, lreg; | |
8672 | ||
8673 | if (target_big_endian) | |
8674 | { | |
8675 | hreg = treg; | |
8676 | lreg = treg + 1; | |
8677 | } | |
8678 | else | |
8679 | { | |
8680 | hreg = treg + 1; | |
8681 | lreg = treg; | |
8682 | } | |
8683 | ||
8684 | if (hreg <= 31) | |
67c0d1eb | 8685 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
8686 | if (lreg <= 31) |
8687 | { | |
8688 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 8689 | move_register (lreg, 0); |
252b5132 RH |
8690 | else |
8691 | { | |
9c2799c2 | 8692 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb | 8693 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
8694 | } |
8695 | } | |
8696 | } | |
8fc2e39e | 8697 | break; |
252b5132 RH |
8698 | } |
8699 | ||
8700 | /* We know that sym is in the .rdata section. First we get the | |
8701 | upper 16 bits of the address. */ | |
8702 | if (mips_pic == NO_PIC) | |
8703 | { | |
67c0d1eb | 8704 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 8705 | used_at = 1; |
252b5132 | 8706 | } |
0a44bf69 | 8707 | else |
252b5132 | 8708 | { |
67c0d1eb RS |
8709 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
8710 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 8711 | used_at = 1; |
252b5132 | 8712 | } |
bdaaa2e1 | 8713 | |
252b5132 | 8714 | /* Now we load the register(s). */ |
ca4e0257 | 8715 | if (HAVE_64BIT_GPRS) |
8fc2e39e TS |
8716 | { |
8717 | used_at = 1; | |
8718 | macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
8719 | } | |
252b5132 RH |
8720 | else |
8721 | { | |
8fc2e39e | 8722 | used_at = 1; |
67c0d1eb | 8723 | macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
f9419b05 | 8724 | if (treg != RA) |
252b5132 RH |
8725 | { |
8726 | /* FIXME: How in the world do we deal with the possible | |
8727 | overflow here? */ | |
8728 | offset_expr.X_add_number += 4; | |
67c0d1eb | 8729 | macro_build (&offset_expr, "lw", "t,o(b)", |
17a2f251 | 8730 | treg + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
8731 | } |
8732 | } | |
252b5132 RH |
8733 | break; |
8734 | ||
8735 | case M_LI_DD: | |
ca4e0257 RS |
8736 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
8737 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
8738 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
8739 | the value and the low order 32 bits are either zero or in | |
8740 | OFFSET_EXPR. */ | |
252b5132 RH |
8741 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
8742 | { | |
8fc2e39e | 8743 | used_at = 1; |
67c0d1eb | 8744 | load_register (AT, &imm_expr, HAVE_64BIT_FPRS); |
ca4e0257 RS |
8745 | if (HAVE_64BIT_FPRS) |
8746 | { | |
9c2799c2 | 8747 | gas_assert (HAVE_64BIT_GPRS); |
67c0d1eb | 8748 | macro_build (NULL, "dmtc1", "t,S", AT, treg); |
ca4e0257 | 8749 | } |
252b5132 RH |
8750 | else |
8751 | { | |
67c0d1eb | 8752 | macro_build (NULL, "mtc1", "t,G", AT, treg + 1); |
252b5132 | 8753 | if (offset_expr.X_op == O_absent) |
67c0d1eb | 8754 | macro_build (NULL, "mtc1", "t,G", 0, treg); |
252b5132 RH |
8755 | else |
8756 | { | |
9c2799c2 | 8757 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb RS |
8758 | load_register (AT, &offset_expr, 0); |
8759 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
8760 | } |
8761 | } | |
8762 | break; | |
8763 | } | |
8764 | ||
9c2799c2 | 8765 | gas_assert (offset_expr.X_op == O_symbol |
90ecf173 | 8766 | && offset_expr.X_add_number == 0); |
252b5132 RH |
8767 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); |
8768 | if (strcmp (s, ".lit8") == 0) | |
8769 | { | |
df58fc94 | 8770 | if (mips_opts.isa != ISA_MIPS1 || mips_opts.micromips) |
252b5132 | 8771 | { |
67c0d1eb | 8772 | macro_build (&offset_expr, "ldc1", "T,o(b)", treg, |
17a2f251 | 8773 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 8774 | break; |
252b5132 | 8775 | } |
c9914766 | 8776 | breg = mips_gp_register; |
252b5132 RH |
8777 | r = BFD_RELOC_MIPS_LITERAL; |
8778 | goto dob; | |
8779 | } | |
8780 | else | |
8781 | { | |
9c2799c2 | 8782 | gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
8fc2e39e | 8783 | used_at = 1; |
0a44bf69 | 8784 | if (mips_pic != NO_PIC) |
67c0d1eb RS |
8785 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
8786 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
8787 | else |
8788 | { | |
8789 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 8790 | macro_build_lui (&offset_expr, AT); |
252b5132 | 8791 | } |
bdaaa2e1 | 8792 | |
df58fc94 | 8793 | if (mips_opts.isa != ISA_MIPS1 || mips_opts.micromips) |
252b5132 | 8794 | { |
67c0d1eb RS |
8795 | macro_build (&offset_expr, "ldc1", "T,o(b)", |
8796 | treg, BFD_RELOC_LO16, AT); | |
252b5132 RH |
8797 | break; |
8798 | } | |
8799 | breg = AT; | |
8800 | r = BFD_RELOC_LO16; | |
8801 | goto dob; | |
8802 | } | |
8803 | ||
8804 | case M_L_DOB: | |
252b5132 RH |
8805 | /* Even on a big endian machine $fn comes before $fn+1. We have |
8806 | to adjust when loading from memory. */ | |
8807 | r = BFD_RELOC_LO16; | |
8808 | dob: | |
df58fc94 | 8809 | gas_assert (!mips_opts.micromips); |
9c2799c2 | 8810 | gas_assert (mips_opts.isa == ISA_MIPS1); |
67c0d1eb | 8811 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 8812 | target_big_endian ? treg + 1 : treg, r, breg); |
252b5132 RH |
8813 | /* FIXME: A possible overflow which I don't know how to deal |
8814 | with. */ | |
8815 | offset_expr.X_add_number += 4; | |
67c0d1eb | 8816 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 8817 | target_big_endian ? treg : treg + 1, r, breg); |
252b5132 RH |
8818 | break; |
8819 | ||
c4a68bea | 8820 | case M_S_DOB: |
df58fc94 | 8821 | gas_assert (!mips_opts.micromips); |
c4a68bea MR |
8822 | gas_assert (mips_opts.isa == ISA_MIPS1); |
8823 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
8824 | to adjust when storing to memory. */ | |
8825 | macro_build (&offset_expr, "swc1", "T,o(b)", | |
8826 | target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg); | |
8827 | offset_expr.X_add_number += 4; | |
8828 | macro_build (&offset_expr, "swc1", "T,o(b)", | |
8829 | target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg); | |
8830 | break; | |
8831 | ||
252b5132 | 8832 | case M_L_DAB: |
df58fc94 | 8833 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
8834 | /* |
8835 | * The MIPS assembler seems to check for X_add_number not | |
8836 | * being double aligned and generating: | |
8837 | * lui at,%hi(foo+1) | |
8838 | * addu at,at,v1 | |
8839 | * addiu at,at,%lo(foo+1) | |
8840 | * lwc1 f2,0(at) | |
8841 | * lwc1 f3,4(at) | |
8842 | * But, the resulting address is the same after relocation so why | |
8843 | * generate the extra instruction? | |
8844 | */ | |
bdaaa2e1 | 8845 | /* Itbl support may require additional care here. */ |
252b5132 | 8846 | coproc = 1; |
df58fc94 | 8847 | fmt = "T,o(b)"; |
e7af610e | 8848 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
8849 | { |
8850 | s = "ldc1"; | |
df58fc94 | 8851 | goto ld_st; |
252b5132 | 8852 | } |
252b5132 | 8853 | s = "lwc1"; |
252b5132 RH |
8854 | goto ldd_std; |
8855 | ||
8856 | case M_S_DAB: | |
df58fc94 RS |
8857 | gas_assert (!mips_opts.micromips); |
8858 | /* Itbl support may require additional care here. */ | |
8859 | coproc = 1; | |
8860 | fmt = "T,o(b)"; | |
e7af610e | 8861 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
8862 | { |
8863 | s = "sdc1"; | |
df58fc94 | 8864 | goto ld_st; |
252b5132 | 8865 | } |
252b5132 | 8866 | s = "swc1"; |
252b5132 RH |
8867 | goto ldd_std; |
8868 | ||
8869 | case M_LD_AB: | |
df58fc94 | 8870 | fmt = "t,o(b)"; |
ca4e0257 | 8871 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
8872 | { |
8873 | s = "ld"; | |
8874 | goto ld; | |
8875 | } | |
252b5132 | 8876 | s = "lw"; |
252b5132 RH |
8877 | goto ldd_std; |
8878 | ||
8879 | case M_SD_AB: | |
df58fc94 | 8880 | fmt = "t,o(b)"; |
ca4e0257 | 8881 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
8882 | { |
8883 | s = "sd"; | |
df58fc94 | 8884 | goto ld_st; |
252b5132 | 8885 | } |
252b5132 | 8886 | s = "sw"; |
252b5132 RH |
8887 | |
8888 | ldd_std: | |
8889 | if (offset_expr.X_op != O_symbol | |
8890 | && offset_expr.X_op != O_constant) | |
8891 | { | |
f71d0d44 | 8892 | as_bad (_("Expression too complex")); |
252b5132 RH |
8893 | offset_expr.X_op = O_constant; |
8894 | } | |
8895 | ||
2051e8c4 MR |
8896 | if (HAVE_32BIT_ADDRESSES |
8897 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
8898 | { |
8899 | char value [32]; | |
8900 | ||
8901 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 8902 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 8903 | } |
2051e8c4 | 8904 | |
252b5132 RH |
8905 | /* Even on a big endian machine $fn comes before $fn+1. We have |
8906 | to adjust when loading from memory. We set coproc if we must | |
8907 | load $fn+1 first. */ | |
bdaaa2e1 | 8908 | /* Itbl support may require additional care here. */ |
90ecf173 | 8909 | if (!target_big_endian) |
252b5132 RH |
8910 | coproc = 0; |
8911 | ||
90ecf173 | 8912 | if (mips_pic == NO_PIC || offset_expr.X_op == O_constant) |
252b5132 RH |
8913 | { |
8914 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 TS |
8915 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
8916 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
8917 | If we have a base register, we use this |
8918 | addu $at,$breg,$gp | |
cdf6fd85 TS |
8919 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
8920 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
8921 | If this is not a GP relative symbol, we want |
8922 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
8923 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
8924 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
8925 | If there is a base register, we add it to $at after the | |
8926 | lui instruction. If there is a constant, we always use | |
8927 | the last case. */ | |
39a59cf8 MR |
8928 | if (offset_expr.X_op == O_symbol |
8929 | && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 8930 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 8931 | { |
4d7206a2 | 8932 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
8933 | if (breg == 0) |
8934 | { | |
c9914766 | 8935 | tempreg = mips_gp_register; |
252b5132 RH |
8936 | } |
8937 | else | |
8938 | { | |
67c0d1eb | 8939 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8940 | AT, breg, mips_gp_register); |
252b5132 | 8941 | tempreg = AT; |
252b5132 RH |
8942 | used_at = 1; |
8943 | } | |
8944 | ||
beae10d5 | 8945 | /* Itbl support may require additional care here. */ |
67c0d1eb | 8946 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 8947 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
8948 | offset_expr.X_add_number += 4; |
8949 | ||
8950 | /* Set mips_optimize to 2 to avoid inserting an | |
8951 | undesired nop. */ | |
8952 | hold_mips_optimize = mips_optimize; | |
8953 | mips_optimize = 2; | |
beae10d5 | 8954 | /* Itbl support may require additional care here. */ |
67c0d1eb | 8955 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 8956 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
8957 | mips_optimize = hold_mips_optimize; |
8958 | ||
4d7206a2 | 8959 | relax_switch (); |
252b5132 | 8960 | |
0970e49e | 8961 | offset_expr.X_add_number -= 4; |
252b5132 | 8962 | } |
8fc2e39e | 8963 | used_at = 1; |
67c0d1eb | 8964 | macro_build_lui (&offset_expr, AT); |
252b5132 | 8965 | if (breg != 0) |
67c0d1eb | 8966 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 8967 | /* Itbl support may require additional care here. */ |
67c0d1eb | 8968 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 8969 | BFD_RELOC_LO16, AT); |
252b5132 RH |
8970 | /* FIXME: How do we handle overflow here? */ |
8971 | offset_expr.X_add_number += 4; | |
beae10d5 | 8972 | /* Itbl support may require additional care here. */ |
67c0d1eb | 8973 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 8974 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
8975 | if (mips_relax.sequence) |
8976 | relax_end (); | |
bdaaa2e1 | 8977 | } |
0a44bf69 | 8978 | else if (!mips_big_got) |
252b5132 | 8979 | { |
252b5132 RH |
8980 | /* If this is a reference to an external symbol, we want |
8981 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
8982 | nop | |
8983 | <op> $treg,0($at) | |
8984 | <op> $treg+1,4($at) | |
8985 | Otherwise we want | |
8986 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
8987 | nop | |
8988 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
8989 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
8990 | If there is a base register we add it to $at before the | |
8991 | lwc1 instructions. If there is a constant we include it | |
8992 | in the lwc1 instructions. */ | |
8993 | used_at = 1; | |
8994 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
8995 | if (expr1.X_add_number < -0x8000 |
8996 | || expr1.X_add_number >= 0x8000 - 4) | |
8997 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 8998 | load_got_offset (AT, &offset_expr); |
269137b2 | 8999 | load_delay_nop (); |
252b5132 | 9000 | if (breg != 0) |
67c0d1eb | 9001 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
9002 | |
9003 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
9004 | nop. */ | |
9005 | hold_mips_optimize = mips_optimize; | |
9006 | mips_optimize = 2; | |
4d7206a2 | 9007 | |
beae10d5 | 9008 | /* Itbl support may require additional care here. */ |
4d7206a2 | 9009 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
9010 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
9011 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9012 | expr1.X_add_number += 4; |
67c0d1eb RS |
9013 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
9014 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9015 | relax_switch (); |
67c0d1eb RS |
9016 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
9017 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9018 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
9019 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
9020 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9021 | relax_end (); |
252b5132 | 9022 | |
4d7206a2 | 9023 | mips_optimize = hold_mips_optimize; |
252b5132 | 9024 | } |
0a44bf69 | 9025 | else if (mips_big_got) |
252b5132 | 9026 | { |
67c0d1eb | 9027 | int gpdelay; |
252b5132 RH |
9028 | |
9029 | /* If this is a reference to an external symbol, we want | |
9030 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
9031 | addu $at,$at,$gp | |
9032 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
9033 | nop | |
9034 | <op> $treg,0($at) | |
9035 | <op> $treg+1,4($at) | |
9036 | Otherwise we want | |
9037 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9038 | nop | |
9039 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
9040 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
9041 | If there is a base register we add it to $at before the | |
9042 | lwc1 instructions. If there is a constant we include it | |
9043 | in the lwc1 instructions. */ | |
9044 | used_at = 1; | |
9045 | expr1.X_add_number = offset_expr.X_add_number; | |
9046 | offset_expr.X_add_number = 0; | |
9047 | if (expr1.X_add_number < -0x8000 | |
9048 | || expr1.X_add_number >= 0x8000 - 4) | |
9049 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 9050 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 9051 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 9052 | macro_build (&offset_expr, "lui", LUI_FMT, |
67c0d1eb RS |
9053 | AT, BFD_RELOC_MIPS_GOT_HI16); |
9054 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 9055 | AT, AT, mips_gp_register); |
67c0d1eb | 9056 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 9057 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 9058 | load_delay_nop (); |
252b5132 | 9059 | if (breg != 0) |
67c0d1eb | 9060 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 9061 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9062 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 9063 | BFD_RELOC_LO16, AT); |
252b5132 RH |
9064 | expr1.X_add_number += 4; |
9065 | ||
9066 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
9067 | nop. */ | |
9068 | hold_mips_optimize = mips_optimize; | |
9069 | mips_optimize = 2; | |
beae10d5 | 9070 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9071 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 9072 | BFD_RELOC_LO16, AT); |
252b5132 RH |
9073 | mips_optimize = hold_mips_optimize; |
9074 | expr1.X_add_number -= 4; | |
9075 | ||
4d7206a2 RS |
9076 | relax_switch (); |
9077 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
9078 | if (gpdelay) |
9079 | macro_build (NULL, "nop", ""); | |
9080 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
9081 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 9082 | load_delay_nop (); |
252b5132 | 9083 | if (breg != 0) |
67c0d1eb | 9084 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 9085 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
9086 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
9087 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9088 | offset_expr.X_add_number += 4; |
252b5132 RH |
9089 | |
9090 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
9091 | nop. */ | |
9092 | hold_mips_optimize = mips_optimize; | |
9093 | mips_optimize = 2; | |
beae10d5 | 9094 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
9095 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
9096 | BFD_RELOC_LO16, AT); | |
252b5132 | 9097 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 9098 | relax_end (); |
252b5132 | 9099 | } |
252b5132 RH |
9100 | else |
9101 | abort (); | |
9102 | ||
252b5132 RH |
9103 | break; |
9104 | ||
9105 | case M_LD_OB: | |
704897fb | 9106 | s = HAVE_64BIT_GPRS ? "ld" : "lw"; |
252b5132 RH |
9107 | goto sd_ob; |
9108 | case M_SD_OB: | |
704897fb | 9109 | s = HAVE_64BIT_GPRS ? "sd" : "sw"; |
252b5132 | 9110 | sd_ob: |
4614d845 MR |
9111 | macro_build (&offset_expr, s, "t,o(b)", treg, |
9112 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2], | |
9113 | breg); | |
704897fb MR |
9114 | if (!HAVE_64BIT_GPRS) |
9115 | { | |
9116 | offset_expr.X_add_number += 4; | |
9117 | macro_build (&offset_expr, s, "t,o(b)", treg + 1, | |
4614d845 MR |
9118 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2], |
9119 | breg); | |
704897fb | 9120 | } |
8fc2e39e | 9121 | break; |
252b5132 RH |
9122 | |
9123 | /* New code added to support COPZ instructions. | |
9124 | This code builds table entries out of the macros in mip_opcodes. | |
9125 | R4000 uses interlocks to handle coproc delays. | |
9126 | Other chips (like the R3000) require nops to be inserted for delays. | |
9127 | ||
f72c8c98 | 9128 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
9129 | In order to fill delay slots for non-interlocked chips, |
9130 | we must have a way to specify delays based on the coprocessor. | |
9131 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
9132 | What are the side-effects of the cop instruction? | |
9133 | What cache support might we have and what are its effects? | |
9134 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 9135 | What registers are read/set/modified? |
252b5132 RH |
9136 | |
9137 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 9138 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
9139 | |
9140 | case M_COP0: | |
9141 | s = "c0"; | |
9142 | goto copz; | |
9143 | case M_COP1: | |
9144 | s = "c1"; | |
9145 | goto copz; | |
9146 | case M_COP2: | |
9147 | s = "c2"; | |
9148 | goto copz; | |
9149 | case M_COP3: | |
9150 | s = "c3"; | |
9151 | copz: | |
df58fc94 | 9152 | gas_assert (!mips_opts.micromips); |
b19e8a9b AN |
9153 | if (NO_ISA_COP (mips_opts.arch) |
9154 | && (ip->insn_mo->pinfo2 & INSN2_M_FP_S) == 0) | |
9155 | { | |
9156 | as_bad (_("opcode not supported on this processor: %s"), | |
9157 | mips_cpu_info_from_arch (mips_opts.arch)->name); | |
9158 | break; | |
9159 | } | |
9160 | ||
252b5132 RH |
9161 | /* For now we just do C (same as Cz). The parameter will be |
9162 | stored in insn_opcode by mips_ip. */ | |
67c0d1eb | 9163 | macro_build (NULL, s, "C", ip->insn_opcode); |
8fc2e39e | 9164 | break; |
252b5132 | 9165 | |
ea1fb5dc | 9166 | case M_MOVE: |
67c0d1eb | 9167 | move_register (dreg, sreg); |
8fc2e39e | 9168 | break; |
ea1fb5dc | 9169 | |
252b5132 RH |
9170 | case M_DMUL: |
9171 | dbl = 1; | |
9172 | case M_MUL: | |
67c0d1eb | 9173 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg); |
df58fc94 | 9174 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
8fc2e39e | 9175 | break; |
252b5132 RH |
9176 | |
9177 | case M_DMUL_I: | |
9178 | dbl = 1; | |
9179 | case M_MUL_I: | |
9180 | /* The MIPS assembler some times generates shifts and adds. I'm | |
9181 | not trying to be that fancy. GCC should do this for us | |
9182 | anyway. */ | |
8fc2e39e | 9183 | used_at = 1; |
67c0d1eb RS |
9184 | load_register (AT, &imm_expr, dbl); |
9185 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT); | |
df58fc94 | 9186 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
252b5132 RH |
9187 | break; |
9188 | ||
9189 | case M_DMULO_I: | |
9190 | dbl = 1; | |
9191 | case M_MULO_I: | |
9192 | imm = 1; | |
9193 | goto do_mulo; | |
9194 | ||
9195 | case M_DMULO: | |
9196 | dbl = 1; | |
9197 | case M_MULO: | |
9198 | do_mulo: | |
7d10b47d | 9199 | start_noreorder (); |
8fc2e39e | 9200 | used_at = 1; |
252b5132 | 9201 | if (imm) |
67c0d1eb RS |
9202 | load_register (AT, &imm_expr, dbl); |
9203 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); | |
df58fc94 RS |
9204 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
9205 | macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, dreg, dreg, RA); | |
9206 | macro_build (NULL, "mfhi", MFHL_FMT, AT); | |
252b5132 | 9207 | if (mips_trap) |
df58fc94 | 9208 | macro_build (NULL, "tne", TRAP_FMT, dreg, AT, 6); |
252b5132 RH |
9209 | else |
9210 | { | |
df58fc94 RS |
9211 | if (mips_opts.micromips) |
9212 | micromips_label_expr (&label_expr); | |
9213 | else | |
9214 | label_expr.X_add_number = 8; | |
9215 | macro_build (&label_expr, "beq", "s,t,p", dreg, AT); | |
a605d2b3 | 9216 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
9217 | macro_build (NULL, "break", BRK_FMT, 6); |
9218 | if (mips_opts.micromips) | |
9219 | micromips_add_label (); | |
252b5132 | 9220 | } |
7d10b47d | 9221 | end_noreorder (); |
df58fc94 | 9222 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
252b5132 RH |
9223 | break; |
9224 | ||
9225 | case M_DMULOU_I: | |
9226 | dbl = 1; | |
9227 | case M_MULOU_I: | |
9228 | imm = 1; | |
9229 | goto do_mulou; | |
9230 | ||
9231 | case M_DMULOU: | |
9232 | dbl = 1; | |
9233 | case M_MULOU: | |
9234 | do_mulou: | |
7d10b47d | 9235 | start_noreorder (); |
8fc2e39e | 9236 | used_at = 1; |
252b5132 | 9237 | if (imm) |
67c0d1eb RS |
9238 | load_register (AT, &imm_expr, dbl); |
9239 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
17a2f251 | 9240 | sreg, imm ? AT : treg); |
df58fc94 RS |
9241 | macro_build (NULL, "mfhi", MFHL_FMT, AT); |
9242 | macro_build (NULL, "mflo", MFHL_FMT, dreg); | |
252b5132 | 9243 | if (mips_trap) |
df58fc94 | 9244 | macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6); |
252b5132 RH |
9245 | else |
9246 | { | |
df58fc94 RS |
9247 | if (mips_opts.micromips) |
9248 | micromips_label_expr (&label_expr); | |
9249 | else | |
9250 | label_expr.X_add_number = 8; | |
9251 | macro_build (&label_expr, "beq", "s,t,p", AT, ZERO); | |
a605d2b3 | 9252 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
9253 | macro_build (NULL, "break", BRK_FMT, 6); |
9254 | if (mips_opts.micromips) | |
9255 | micromips_add_label (); | |
252b5132 | 9256 | } |
7d10b47d | 9257 | end_noreorder (); |
252b5132 RH |
9258 | break; |
9259 | ||
771c7ce4 | 9260 | case M_DROL: |
fef14a42 | 9261 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
9262 | { |
9263 | if (dreg == sreg) | |
9264 | { | |
9265 | tempreg = AT; | |
9266 | used_at = 1; | |
9267 | } | |
9268 | else | |
9269 | { | |
9270 | tempreg = dreg; | |
82dd0097 | 9271 | } |
67c0d1eb RS |
9272 | macro_build (NULL, "dnegu", "d,w", tempreg, treg); |
9273 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 9274 | break; |
82dd0097 | 9275 | } |
8fc2e39e | 9276 | used_at = 1; |
c80c840e | 9277 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9278 | macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT); |
9279 | macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg); | |
9280 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
9281 | break; |
9282 | ||
252b5132 | 9283 | case M_ROL: |
fef14a42 | 9284 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 CD |
9285 | { |
9286 | if (dreg == sreg) | |
9287 | { | |
9288 | tempreg = AT; | |
9289 | used_at = 1; | |
9290 | } | |
9291 | else | |
9292 | { | |
9293 | tempreg = dreg; | |
82dd0097 | 9294 | } |
67c0d1eb RS |
9295 | macro_build (NULL, "negu", "d,w", tempreg, treg); |
9296 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 9297 | break; |
82dd0097 | 9298 | } |
8fc2e39e | 9299 | used_at = 1; |
c80c840e | 9300 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9301 | macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT); |
9302 | macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg); | |
9303 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
9304 | break; |
9305 | ||
771c7ce4 TS |
9306 | case M_DROL_I: |
9307 | { | |
9308 | unsigned int rot; | |
91d6fa6a NC |
9309 | char *l; |
9310 | char *rr; | |
771c7ce4 TS |
9311 | |
9312 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9313 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9314 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 9315 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
9316 | { |
9317 | rot = (64 - rot) & 0x3f; | |
9318 | if (rot >= 32) | |
df58fc94 | 9319 | macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32); |
60b63b72 | 9320 | else |
df58fc94 | 9321 | macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot); |
8fc2e39e | 9322 | break; |
60b63b72 | 9323 | } |
483fc7cd | 9324 | if (rot == 0) |
483fc7cd | 9325 | { |
df58fc94 | 9326 | macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9327 | break; |
483fc7cd | 9328 | } |
82dd0097 | 9329 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
91d6fa6a | 9330 | rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 | 9331 | rot &= 0x1f; |
8fc2e39e | 9332 | used_at = 1; |
df58fc94 RS |
9333 | macro_build (NULL, l, SHFT_FMT, AT, sreg, rot); |
9334 | macro_build (NULL, rr, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9335 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
9336 | } |
9337 | break; | |
9338 | ||
252b5132 | 9339 | case M_ROL_I: |
771c7ce4 TS |
9340 | { |
9341 | unsigned int rot; | |
9342 | ||
9343 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9344 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9345 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 9346 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 9347 | { |
df58fc94 | 9348 | macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, (32 - rot) & 0x1f); |
8fc2e39e | 9349 | break; |
60b63b72 | 9350 | } |
483fc7cd | 9351 | if (rot == 0) |
483fc7cd | 9352 | { |
df58fc94 | 9353 | macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9354 | break; |
483fc7cd | 9355 | } |
8fc2e39e | 9356 | used_at = 1; |
df58fc94 RS |
9357 | macro_build (NULL, "sll", SHFT_FMT, AT, sreg, rot); |
9358 | macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9359 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
9360 | } |
9361 | break; | |
9362 | ||
9363 | case M_DROR: | |
fef14a42 | 9364 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 9365 | { |
67c0d1eb | 9366 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 9367 | break; |
82dd0097 | 9368 | } |
8fc2e39e | 9369 | used_at = 1; |
c80c840e | 9370 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9371 | macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT); |
9372 | macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg); | |
9373 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
9374 | break; |
9375 | ||
9376 | case M_ROR: | |
fef14a42 | 9377 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 9378 | { |
67c0d1eb | 9379 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 9380 | break; |
82dd0097 | 9381 | } |
8fc2e39e | 9382 | used_at = 1; |
c80c840e | 9383 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9384 | macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT); |
9385 | macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg); | |
9386 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
9387 | break; |
9388 | ||
771c7ce4 TS |
9389 | case M_DROR_I: |
9390 | { | |
9391 | unsigned int rot; | |
91d6fa6a NC |
9392 | char *l; |
9393 | char *rr; | |
771c7ce4 TS |
9394 | |
9395 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9396 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9397 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 9398 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
9399 | { |
9400 | if (rot >= 32) | |
df58fc94 | 9401 | macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32); |
82dd0097 | 9402 | else |
df58fc94 | 9403 | macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot); |
8fc2e39e | 9404 | break; |
82dd0097 | 9405 | } |
483fc7cd | 9406 | if (rot == 0) |
483fc7cd | 9407 | { |
df58fc94 | 9408 | macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9409 | break; |
483fc7cd | 9410 | } |
91d6fa6a | 9411 | rr = (rot < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 CD |
9412 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; |
9413 | rot &= 0x1f; | |
8fc2e39e | 9414 | used_at = 1; |
df58fc94 RS |
9415 | macro_build (NULL, rr, SHFT_FMT, AT, sreg, rot); |
9416 | macro_build (NULL, l, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9417 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
9418 | } |
9419 | break; | |
9420 | ||
252b5132 | 9421 | case M_ROR_I: |
771c7ce4 TS |
9422 | { |
9423 | unsigned int rot; | |
9424 | ||
9425 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9426 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9427 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 9428 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 9429 | { |
df58fc94 | 9430 | macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, rot); |
8fc2e39e | 9431 | break; |
82dd0097 | 9432 | } |
483fc7cd | 9433 | if (rot == 0) |
483fc7cd | 9434 | { |
df58fc94 | 9435 | macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9436 | break; |
483fc7cd | 9437 | } |
8fc2e39e | 9438 | used_at = 1; |
df58fc94 RS |
9439 | macro_build (NULL, "srl", SHFT_FMT, AT, sreg, rot); |
9440 | macro_build (NULL, "sll", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9441 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 | 9442 | } |
252b5132 RH |
9443 | break; |
9444 | ||
252b5132 RH |
9445 | case M_SEQ: |
9446 | if (sreg == 0) | |
67c0d1eb | 9447 | macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16); |
252b5132 | 9448 | else if (treg == 0) |
67c0d1eb | 9449 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
9450 | else |
9451 | { | |
67c0d1eb RS |
9452 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
9453 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 | 9454 | } |
8fc2e39e | 9455 | break; |
252b5132 RH |
9456 | |
9457 | case M_SEQ_I: | |
9458 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
9459 | { | |
67c0d1eb | 9460 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 9461 | break; |
252b5132 RH |
9462 | } |
9463 | if (sreg == 0) | |
9464 | { | |
9465 | as_warn (_("Instruction %s: result is always false"), | |
9466 | ip->insn_mo->name); | |
67c0d1eb | 9467 | move_register (dreg, 0); |
8fc2e39e | 9468 | break; |
252b5132 | 9469 | } |
dd3cbb7e NC |
9470 | if (CPU_HAS_SEQ (mips_opts.arch) |
9471 | && -512 <= imm_expr.X_add_number | |
9472 | && imm_expr.X_add_number < 512) | |
9473 | { | |
9474 | macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg, | |
750bdd57 | 9475 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
9476 | break; |
9477 | } | |
252b5132 RH |
9478 | if (imm_expr.X_op == O_constant |
9479 | && imm_expr.X_add_number >= 0 | |
9480 | && imm_expr.X_add_number < 0x10000) | |
9481 | { | |
67c0d1eb | 9482 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
9483 | } |
9484 | else if (imm_expr.X_op == O_constant | |
9485 | && imm_expr.X_add_number > -0x8000 | |
9486 | && imm_expr.X_add_number < 0) | |
9487 | { | |
9488 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 9489 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 9490 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 | 9491 | } |
dd3cbb7e NC |
9492 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
9493 | { | |
9494 | used_at = 1; | |
9495 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); | |
9496 | macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT); | |
9497 | break; | |
9498 | } | |
252b5132 RH |
9499 | else |
9500 | { | |
67c0d1eb RS |
9501 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9502 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
9503 | used_at = 1; |
9504 | } | |
67c0d1eb | 9505 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 9506 | break; |
252b5132 RH |
9507 | |
9508 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
9509 | s = "slt"; | |
9510 | goto sge; | |
9511 | case M_SGEU: | |
9512 | s = "sltu"; | |
9513 | sge: | |
67c0d1eb RS |
9514 | macro_build (NULL, s, "d,v,t", dreg, sreg, treg); |
9515 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 9516 | break; |
252b5132 RH |
9517 | |
9518 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
9519 | case M_SGEU_I: | |
9520 | if (imm_expr.X_op == O_constant | |
9521 | && imm_expr.X_add_number >= -0x8000 | |
9522 | && imm_expr.X_add_number < 0x8000) | |
9523 | { | |
67c0d1eb RS |
9524 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
9525 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
9526 | } |
9527 | else | |
9528 | { | |
67c0d1eb RS |
9529 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9530 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", | |
9531 | dreg, sreg, AT); | |
252b5132 RH |
9532 | used_at = 1; |
9533 | } | |
67c0d1eb | 9534 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 9535 | break; |
252b5132 RH |
9536 | |
9537 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
9538 | s = "slt"; | |
9539 | goto sgt; | |
9540 | case M_SGTU: | |
9541 | s = "sltu"; | |
9542 | sgt: | |
67c0d1eb | 9543 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
8fc2e39e | 9544 | break; |
252b5132 RH |
9545 | |
9546 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
9547 | s = "slt"; | |
9548 | goto sgti; | |
9549 | case M_SGTU_I: | |
9550 | s = "sltu"; | |
9551 | sgti: | |
8fc2e39e | 9552 | used_at = 1; |
67c0d1eb RS |
9553 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9554 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
252b5132 RH |
9555 | break; |
9556 | ||
2396cfb9 | 9557 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
9558 | s = "slt"; |
9559 | goto sle; | |
9560 | case M_SLEU: | |
9561 | s = "sltu"; | |
9562 | sle: | |
67c0d1eb RS |
9563 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
9564 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 9565 | break; |
252b5132 | 9566 | |
2396cfb9 | 9567 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
9568 | s = "slt"; |
9569 | goto slei; | |
9570 | case M_SLEU_I: | |
9571 | s = "sltu"; | |
9572 | slei: | |
8fc2e39e | 9573 | used_at = 1; |
67c0d1eb RS |
9574 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9575 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
9576 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
9577 | break; |
9578 | ||
9579 | case M_SLT_I: | |
9580 | if (imm_expr.X_op == O_constant | |
9581 | && imm_expr.X_add_number >= -0x8000 | |
9582 | && imm_expr.X_add_number < 0x8000) | |
9583 | { | |
67c0d1eb | 9584 | macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 9585 | break; |
252b5132 | 9586 | } |
8fc2e39e | 9587 | used_at = 1; |
67c0d1eb RS |
9588 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9589 | macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
9590 | break; |
9591 | ||
9592 | case M_SLTU_I: | |
9593 | if (imm_expr.X_op == O_constant | |
9594 | && imm_expr.X_add_number >= -0x8000 | |
9595 | && imm_expr.X_add_number < 0x8000) | |
9596 | { | |
67c0d1eb | 9597 | macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg, |
17a2f251 | 9598 | BFD_RELOC_LO16); |
8fc2e39e | 9599 | break; |
252b5132 | 9600 | } |
8fc2e39e | 9601 | used_at = 1; |
67c0d1eb RS |
9602 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9603 | macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
9604 | break; |
9605 | ||
9606 | case M_SNE: | |
9607 | if (sreg == 0) | |
67c0d1eb | 9608 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg); |
252b5132 | 9609 | else if (treg == 0) |
67c0d1eb | 9610 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
9611 | else |
9612 | { | |
67c0d1eb RS |
9613 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
9614 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
252b5132 | 9615 | } |
8fc2e39e | 9616 | break; |
252b5132 RH |
9617 | |
9618 | case M_SNE_I: | |
9619 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
9620 | { | |
67c0d1eb | 9621 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
8fc2e39e | 9622 | break; |
252b5132 RH |
9623 | } |
9624 | if (sreg == 0) | |
9625 | { | |
9626 | as_warn (_("Instruction %s: result is always true"), | |
9627 | ip->insn_mo->name); | |
67c0d1eb RS |
9628 | macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", |
9629 | dreg, 0, BFD_RELOC_LO16); | |
8fc2e39e | 9630 | break; |
252b5132 | 9631 | } |
dd3cbb7e NC |
9632 | if (CPU_HAS_SEQ (mips_opts.arch) |
9633 | && -512 <= imm_expr.X_add_number | |
9634 | && imm_expr.X_add_number < 512) | |
9635 | { | |
9636 | macro_build (NULL, "snei", "t,r,+Q", dreg, sreg, | |
750bdd57 | 9637 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
9638 | break; |
9639 | } | |
252b5132 RH |
9640 | if (imm_expr.X_op == O_constant |
9641 | && imm_expr.X_add_number >= 0 | |
9642 | && imm_expr.X_add_number < 0x10000) | |
9643 | { | |
67c0d1eb | 9644 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
9645 | } |
9646 | else if (imm_expr.X_op == O_constant | |
9647 | && imm_expr.X_add_number > -0x8000 | |
9648 | && imm_expr.X_add_number < 0) | |
9649 | { | |
9650 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 9651 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 9652 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 | 9653 | } |
dd3cbb7e NC |
9654 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
9655 | { | |
9656 | used_at = 1; | |
9657 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); | |
9658 | macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT); | |
9659 | break; | |
9660 | } | |
252b5132 RH |
9661 | else |
9662 | { | |
67c0d1eb RS |
9663 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9664 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
9665 | used_at = 1; |
9666 | } | |
67c0d1eb | 9667 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); |
8fc2e39e | 9668 | break; |
252b5132 | 9669 | |
df58fc94 RS |
9670 | case M_SUB_I: |
9671 | s = "addi"; | |
9672 | s2 = "sub"; | |
9673 | goto do_subi; | |
9674 | case M_SUBU_I: | |
9675 | s = "addiu"; | |
9676 | s2 = "subu"; | |
9677 | goto do_subi; | |
252b5132 RH |
9678 | case M_DSUB_I: |
9679 | dbl = 1; | |
df58fc94 RS |
9680 | s = "daddi"; |
9681 | s2 = "dsub"; | |
9682 | if (!mips_opts.micromips) | |
9683 | goto do_subi; | |
252b5132 | 9684 | if (imm_expr.X_op == O_constant |
df58fc94 RS |
9685 | && imm_expr.X_add_number > -0x200 |
9686 | && imm_expr.X_add_number <= 0x200) | |
252b5132 | 9687 | { |
df58fc94 | 9688 | macro_build (NULL, s, "t,r,.", dreg, sreg, -imm_expr.X_add_number); |
8fc2e39e | 9689 | break; |
252b5132 | 9690 | } |
df58fc94 | 9691 | goto do_subi_i; |
252b5132 RH |
9692 | case M_DSUBU_I: |
9693 | dbl = 1; | |
df58fc94 RS |
9694 | s = "daddiu"; |
9695 | s2 = "dsubu"; | |
9696 | do_subi: | |
252b5132 RH |
9697 | if (imm_expr.X_op == O_constant |
9698 | && imm_expr.X_add_number > -0x8000 | |
9699 | && imm_expr.X_add_number <= 0x8000) | |
9700 | { | |
9701 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
df58fc94 | 9702 | macro_build (&imm_expr, s, "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 9703 | break; |
252b5132 | 9704 | } |
df58fc94 | 9705 | do_subi_i: |
8fc2e39e | 9706 | used_at = 1; |
67c0d1eb | 9707 | load_register (AT, &imm_expr, dbl); |
df58fc94 | 9708 | macro_build (NULL, s2, "d,v,t", dreg, sreg, AT); |
252b5132 RH |
9709 | break; |
9710 | ||
9711 | case M_TEQ_I: | |
9712 | s = "teq"; | |
9713 | goto trap; | |
9714 | case M_TGE_I: | |
9715 | s = "tge"; | |
9716 | goto trap; | |
9717 | case M_TGEU_I: | |
9718 | s = "tgeu"; | |
9719 | goto trap; | |
9720 | case M_TLT_I: | |
9721 | s = "tlt"; | |
9722 | goto trap; | |
9723 | case M_TLTU_I: | |
9724 | s = "tltu"; | |
9725 | goto trap; | |
9726 | case M_TNE_I: | |
9727 | s = "tne"; | |
9728 | trap: | |
8fc2e39e | 9729 | used_at = 1; |
67c0d1eb RS |
9730 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
9731 | macro_build (NULL, s, "s,t", sreg, AT); | |
252b5132 RH |
9732 | break; |
9733 | ||
252b5132 | 9734 | case M_TRUNCWS: |
43841e91 | 9735 | case M_TRUNCWD: |
df58fc94 | 9736 | gas_assert (!mips_opts.micromips); |
9c2799c2 | 9737 | gas_assert (mips_opts.isa == ISA_MIPS1); |
8fc2e39e | 9738 | used_at = 1; |
252b5132 RH |
9739 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
9740 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
9741 | ||
9742 | /* | |
9743 | * Is the double cfc1 instruction a bug in the mips assembler; | |
9744 | * or is there a reason for it? | |
9745 | */ | |
7d10b47d | 9746 | start_noreorder (); |
67c0d1eb RS |
9747 | macro_build (NULL, "cfc1", "t,G", treg, RA); |
9748 | macro_build (NULL, "cfc1", "t,G", treg, RA); | |
9749 | macro_build (NULL, "nop", ""); | |
252b5132 | 9750 | expr1.X_add_number = 3; |
67c0d1eb | 9751 | macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16); |
252b5132 | 9752 | expr1.X_add_number = 2; |
67c0d1eb RS |
9753 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
9754 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
9755 | macro_build (NULL, "nop", ""); | |
9756 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
9757 | dreg, sreg); | |
9758 | macro_build (NULL, "ctc1", "t,G", treg, RA); | |
9759 | macro_build (NULL, "nop", ""); | |
7d10b47d | 9760 | end_noreorder (); |
252b5132 RH |
9761 | break; |
9762 | ||
df58fc94 RS |
9763 | case M_ULH_A: |
9764 | ab = 1; | |
252b5132 RH |
9765 | case M_ULH: |
9766 | s = "lb"; | |
df58fc94 RS |
9767 | s2 = "lbu"; |
9768 | off = 1; | |
9769 | goto uld_st; | |
9770 | case M_ULHU_A: | |
9771 | ab = 1; | |
252b5132 RH |
9772 | case M_ULHU: |
9773 | s = "lbu"; | |
df58fc94 RS |
9774 | s2 = "lbu"; |
9775 | off = 1; | |
9776 | goto uld_st; | |
9777 | case M_ULW_A: | |
9778 | ab = 1; | |
9779 | case M_ULW: | |
9780 | s = "lwl"; | |
9781 | s2 = "lwr"; | |
9782 | off12 = mips_opts.micromips; | |
9783 | off = 3; | |
9784 | goto uld_st; | |
9785 | case M_ULD_A: | |
9786 | ab = 1; | |
252b5132 RH |
9787 | case M_ULD: |
9788 | s = "ldl"; | |
9789 | s2 = "ldr"; | |
df58fc94 | 9790 | off12 = mips_opts.micromips; |
252b5132 | 9791 | off = 7; |
df58fc94 RS |
9792 | goto uld_st; |
9793 | case M_USH_A: | |
9794 | ab = 1; | |
9795 | case M_USH: | |
9796 | s = "sb"; | |
9797 | s2 = "sb"; | |
9798 | off = 1; | |
9799 | ust = 1; | |
9800 | goto uld_st; | |
9801 | case M_USW_A: | |
9802 | ab = 1; | |
9803 | case M_USW: | |
9804 | s = "swl"; | |
9805 | s2 = "swr"; | |
9806 | off12 = mips_opts.micromips; | |
252b5132 | 9807 | off = 3; |
df58fc94 RS |
9808 | ust = 1; |
9809 | goto uld_st; | |
9810 | case M_USD_A: | |
9811 | ab = 1; | |
9812 | case M_USD: | |
9813 | s = "sdl"; | |
9814 | s2 = "sdr"; | |
9815 | off12 = mips_opts.micromips; | |
9816 | off = 7; | |
9817 | ust = 1; | |
9818 | ||
9819 | uld_st: | |
9820 | if (!ab && offset_expr.X_add_number >= 0x8000 - off) | |
f71d0d44 | 9821 | as_bad (_("Operand overflow")); |
df58fc94 RS |
9822 | |
9823 | ep = &offset_expr; | |
9824 | expr1.X_add_number = 0; | |
9825 | if (ab) | |
9826 | { | |
9827 | used_at = 1; | |
9828 | tempreg = AT; | |
9829 | load_address (tempreg, ep, &used_at); | |
9830 | if (breg != 0) | |
9831 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
9832 | tempreg, tempreg, breg); | |
9833 | breg = tempreg; | |
9834 | tempreg = treg; | |
9835 | ep = &expr1; | |
9836 | } | |
9837 | else if (off12 | |
9838 | && (offset_expr.X_op != O_constant | |
9839 | || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number) | |
9840 | || !IS_SEXT_12BIT_NUM (offset_expr.X_add_number + off))) | |
9841 | { | |
9842 | used_at = 1; | |
9843 | tempreg = AT; | |
9844 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, | |
9845 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]); | |
9846 | breg = tempreg; | |
9847 | tempreg = treg; | |
9848 | ep = &expr1; | |
9849 | } | |
9850 | else if (!ust && treg == breg) | |
8fc2e39e TS |
9851 | { |
9852 | used_at = 1; | |
9853 | tempreg = AT; | |
9854 | } | |
252b5132 | 9855 | else |
df58fc94 | 9856 | tempreg = treg; |
af22f5b2 | 9857 | |
df58fc94 RS |
9858 | if (off == 1) |
9859 | goto ulh_sh; | |
252b5132 | 9860 | |
90ecf173 | 9861 | if (!target_big_endian) |
df58fc94 RS |
9862 | ep->X_add_number += off; |
9863 | if (!off12) | |
9864 | macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); | |
252b5132 | 9865 | else |
df58fc94 RS |
9866 | macro_build (NULL, s, "t,~(b)", |
9867 | tempreg, (unsigned long) ep->X_add_number, breg); | |
9868 | ||
90ecf173 | 9869 | if (!target_big_endian) |
df58fc94 | 9870 | ep->X_add_number -= off; |
252b5132 | 9871 | else |
df58fc94 RS |
9872 | ep->X_add_number += off; |
9873 | if (!off12) | |
9874 | macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); | |
9875 | else | |
9876 | macro_build (NULL, s2, "t,~(b)", | |
9877 | tempreg, (unsigned long) ep->X_add_number, breg); | |
252b5132 | 9878 | |
df58fc94 RS |
9879 | /* If necessary, move the result in tempreg to the final destination. */ |
9880 | if (!ust && treg != tempreg) | |
9881 | { | |
9882 | /* Protect second load's delay slot. */ | |
9883 | load_delay_nop (); | |
9884 | move_register (treg, tempreg); | |
9885 | } | |
8fc2e39e | 9886 | break; |
252b5132 | 9887 | |
df58fc94 | 9888 | ulh_sh: |
d6bc6245 | 9889 | used_at = 1; |
df58fc94 RS |
9890 | if (target_big_endian == ust) |
9891 | ep->X_add_number += off; | |
9892 | tempreg = ust || ab ? treg : AT; | |
9893 | macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); | |
9894 | ||
9895 | /* For halfword transfers we need a temporary register to shuffle | |
9896 | bytes. Unfortunately for M_USH_A we have none available before | |
9897 | the next store as AT holds the base address. We deal with this | |
9898 | case by clobbering TREG and then restoring it as with ULH. */ | |
9899 | tempreg = ust == ab ? treg : AT; | |
9900 | if (ust) | |
9901 | macro_build (NULL, "srl", SHFT_FMT, tempreg, treg, 8); | |
9902 | ||
9903 | if (target_big_endian == ust) | |
9904 | ep->X_add_number -= off; | |
252b5132 | 9905 | else |
df58fc94 RS |
9906 | ep->X_add_number += off; |
9907 | macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); | |
252b5132 | 9908 | |
df58fc94 RS |
9909 | /* For M_USH_A re-retrieve the LSB. */ |
9910 | if (ust && ab) | |
9911 | { | |
9912 | if (target_big_endian) | |
9913 | ep->X_add_number += off; | |
9914 | else | |
9915 | ep->X_add_number -= off; | |
9916 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); | |
9917 | } | |
9918 | /* For ULH and M_USH_A OR the LSB in. */ | |
9919 | if (!ust || ab) | |
9920 | { | |
9921 | tempreg = !ab ? AT : treg; | |
9922 | macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8); | |
9923 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
9924 | } | |
252b5132 RH |
9925 | break; |
9926 | ||
9927 | default: | |
9928 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 9929 | are added dynamically. */ |
252b5132 RH |
9930 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
9931 | break; | |
9932 | } | |
741fe287 | 9933 | if (!mips_opts.at && used_at) |
8fc2e39e | 9934 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
9935 | } |
9936 | ||
9937 | /* Implement macros in mips16 mode. */ | |
9938 | ||
9939 | static void | |
17a2f251 | 9940 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 RH |
9941 | { |
9942 | int mask; | |
9943 | int xreg, yreg, zreg, tmp; | |
252b5132 RH |
9944 | expressionS expr1; |
9945 | int dbl; | |
9946 | const char *s, *s2, *s3; | |
9947 | ||
9948 | mask = ip->insn_mo->mask; | |
9949 | ||
bf12938e RS |
9950 | xreg = MIPS16_EXTRACT_OPERAND (RX, *ip); |
9951 | yreg = MIPS16_EXTRACT_OPERAND (RY, *ip); | |
9952 | zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip); | |
252b5132 | 9953 | |
252b5132 RH |
9954 | expr1.X_op = O_constant; |
9955 | expr1.X_op_symbol = NULL; | |
9956 | expr1.X_add_symbol = NULL; | |
9957 | expr1.X_add_number = 1; | |
9958 | ||
9959 | dbl = 0; | |
9960 | ||
9961 | switch (mask) | |
9962 | { | |
9963 | default: | |
9964 | internalError (); | |
9965 | ||
9966 | case M_DDIV_3: | |
9967 | dbl = 1; | |
9968 | case M_DIV_3: | |
9969 | s = "mflo"; | |
9970 | goto do_div3; | |
9971 | case M_DREM_3: | |
9972 | dbl = 1; | |
9973 | case M_REM_3: | |
9974 | s = "mfhi"; | |
9975 | do_div3: | |
7d10b47d | 9976 | start_noreorder (); |
67c0d1eb | 9977 | macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg); |
252b5132 | 9978 | expr1.X_add_number = 2; |
67c0d1eb RS |
9979 | macro_build (&expr1, "bnez", "x,p", yreg); |
9980 | macro_build (NULL, "break", "6", 7); | |
bdaaa2e1 | 9981 | |
252b5132 RH |
9982 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
9983 | since that causes an overflow. We should do that as well, | |
9984 | but I don't see how to do the comparisons without a temporary | |
9985 | register. */ | |
7d10b47d | 9986 | end_noreorder (); |
67c0d1eb | 9987 | macro_build (NULL, s, "x", zreg); |
252b5132 RH |
9988 | break; |
9989 | ||
9990 | case M_DIVU_3: | |
9991 | s = "divu"; | |
9992 | s2 = "mflo"; | |
9993 | goto do_divu3; | |
9994 | case M_REMU_3: | |
9995 | s = "divu"; | |
9996 | s2 = "mfhi"; | |
9997 | goto do_divu3; | |
9998 | case M_DDIVU_3: | |
9999 | s = "ddivu"; | |
10000 | s2 = "mflo"; | |
10001 | goto do_divu3; | |
10002 | case M_DREMU_3: | |
10003 | s = "ddivu"; | |
10004 | s2 = "mfhi"; | |
10005 | do_divu3: | |
7d10b47d | 10006 | start_noreorder (); |
67c0d1eb | 10007 | macro_build (NULL, s, "0,x,y", xreg, yreg); |
252b5132 | 10008 | expr1.X_add_number = 2; |
67c0d1eb RS |
10009 | macro_build (&expr1, "bnez", "x,p", yreg); |
10010 | macro_build (NULL, "break", "6", 7); | |
7d10b47d | 10011 | end_noreorder (); |
67c0d1eb | 10012 | macro_build (NULL, s2, "x", zreg); |
252b5132 RH |
10013 | break; |
10014 | ||
10015 | case M_DMUL: | |
10016 | dbl = 1; | |
10017 | case M_MUL: | |
67c0d1eb RS |
10018 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
10019 | macro_build (NULL, "mflo", "x", zreg); | |
8fc2e39e | 10020 | break; |
252b5132 RH |
10021 | |
10022 | case M_DSUBU_I: | |
10023 | dbl = 1; | |
10024 | goto do_subu; | |
10025 | case M_SUBU_I: | |
10026 | do_subu: | |
10027 | if (imm_expr.X_op != O_constant) | |
10028 | as_bad (_("Unsupported large constant")); | |
10029 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10030 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
10031 | break; |
10032 | ||
10033 | case M_SUBU_I_2: | |
10034 | if (imm_expr.X_op != O_constant) | |
10035 | as_bad (_("Unsupported large constant")); | |
10036 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10037 | macro_build (&imm_expr, "addiu", "x,k", xreg); |
252b5132 RH |
10038 | break; |
10039 | ||
10040 | case M_DSUBU_I_2: | |
10041 | if (imm_expr.X_op != O_constant) | |
10042 | as_bad (_("Unsupported large constant")); | |
10043 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10044 | macro_build (&imm_expr, "daddiu", "y,j", yreg); |
252b5132 RH |
10045 | break; |
10046 | ||
10047 | case M_BEQ: | |
10048 | s = "cmp"; | |
10049 | s2 = "bteqz"; | |
10050 | goto do_branch; | |
10051 | case M_BNE: | |
10052 | s = "cmp"; | |
10053 | s2 = "btnez"; | |
10054 | goto do_branch; | |
10055 | case M_BLT: | |
10056 | s = "slt"; | |
10057 | s2 = "btnez"; | |
10058 | goto do_branch; | |
10059 | case M_BLTU: | |
10060 | s = "sltu"; | |
10061 | s2 = "btnez"; | |
10062 | goto do_branch; | |
10063 | case M_BLE: | |
10064 | s = "slt"; | |
10065 | s2 = "bteqz"; | |
10066 | goto do_reverse_branch; | |
10067 | case M_BLEU: | |
10068 | s = "sltu"; | |
10069 | s2 = "bteqz"; | |
10070 | goto do_reverse_branch; | |
10071 | case M_BGE: | |
10072 | s = "slt"; | |
10073 | s2 = "bteqz"; | |
10074 | goto do_branch; | |
10075 | case M_BGEU: | |
10076 | s = "sltu"; | |
10077 | s2 = "bteqz"; | |
10078 | goto do_branch; | |
10079 | case M_BGT: | |
10080 | s = "slt"; | |
10081 | s2 = "btnez"; | |
10082 | goto do_reverse_branch; | |
10083 | case M_BGTU: | |
10084 | s = "sltu"; | |
10085 | s2 = "btnez"; | |
10086 | ||
10087 | do_reverse_branch: | |
10088 | tmp = xreg; | |
10089 | xreg = yreg; | |
10090 | yreg = tmp; | |
10091 | ||
10092 | do_branch: | |
67c0d1eb RS |
10093 | macro_build (NULL, s, "x,y", xreg, yreg); |
10094 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
10095 | break; |
10096 | ||
10097 | case M_BEQ_I: | |
10098 | s = "cmpi"; | |
10099 | s2 = "bteqz"; | |
10100 | s3 = "x,U"; | |
10101 | goto do_branch_i; | |
10102 | case M_BNE_I: | |
10103 | s = "cmpi"; | |
10104 | s2 = "btnez"; | |
10105 | s3 = "x,U"; | |
10106 | goto do_branch_i; | |
10107 | case M_BLT_I: | |
10108 | s = "slti"; | |
10109 | s2 = "btnez"; | |
10110 | s3 = "x,8"; | |
10111 | goto do_branch_i; | |
10112 | case M_BLTU_I: | |
10113 | s = "sltiu"; | |
10114 | s2 = "btnez"; | |
10115 | s3 = "x,8"; | |
10116 | goto do_branch_i; | |
10117 | case M_BLE_I: | |
10118 | s = "slti"; | |
10119 | s2 = "btnez"; | |
10120 | s3 = "x,8"; | |
10121 | goto do_addone_branch_i; | |
10122 | case M_BLEU_I: | |
10123 | s = "sltiu"; | |
10124 | s2 = "btnez"; | |
10125 | s3 = "x,8"; | |
10126 | goto do_addone_branch_i; | |
10127 | case M_BGE_I: | |
10128 | s = "slti"; | |
10129 | s2 = "bteqz"; | |
10130 | s3 = "x,8"; | |
10131 | goto do_branch_i; | |
10132 | case M_BGEU_I: | |
10133 | s = "sltiu"; | |
10134 | s2 = "bteqz"; | |
10135 | s3 = "x,8"; | |
10136 | goto do_branch_i; | |
10137 | case M_BGT_I: | |
10138 | s = "slti"; | |
10139 | s2 = "bteqz"; | |
10140 | s3 = "x,8"; | |
10141 | goto do_addone_branch_i; | |
10142 | case M_BGTU_I: | |
10143 | s = "sltiu"; | |
10144 | s2 = "bteqz"; | |
10145 | s3 = "x,8"; | |
10146 | ||
10147 | do_addone_branch_i: | |
10148 | if (imm_expr.X_op != O_constant) | |
10149 | as_bad (_("Unsupported large constant")); | |
10150 | ++imm_expr.X_add_number; | |
10151 | ||
10152 | do_branch_i: | |
67c0d1eb RS |
10153 | macro_build (&imm_expr, s, s3, xreg); |
10154 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
10155 | break; |
10156 | ||
10157 | case M_ABS: | |
10158 | expr1.X_add_number = 0; | |
67c0d1eb | 10159 | macro_build (&expr1, "slti", "x,8", yreg); |
252b5132 | 10160 | if (xreg != yreg) |
67c0d1eb | 10161 | move_register (xreg, yreg); |
252b5132 | 10162 | expr1.X_add_number = 2; |
67c0d1eb RS |
10163 | macro_build (&expr1, "bteqz", "p"); |
10164 | macro_build (NULL, "neg", "x,w", xreg, xreg); | |
252b5132 RH |
10165 | } |
10166 | } | |
10167 | ||
10168 | /* For consistency checking, verify that all bits are specified either | |
10169 | by the match/mask part of the instruction definition, or by the | |
10170 | operand list. */ | |
10171 | static int | |
17a2f251 | 10172 | validate_mips_insn (const struct mips_opcode *opc) |
252b5132 RH |
10173 | { |
10174 | const char *p = opc->args; | |
10175 | char c; | |
10176 | unsigned long used_bits = opc->mask; | |
10177 | ||
10178 | if ((used_bits & opc->match) != opc->match) | |
10179 | { | |
10180 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
10181 | opc->name, opc->args); | |
10182 | return 0; | |
10183 | } | |
10184 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
10185 | while (*p) | |
10186 | switch (c = *p++) | |
10187 | { | |
10188 | case ',': break; | |
10189 | case '(': break; | |
10190 | case ')': break; | |
af7ee8bf CD |
10191 | case '+': |
10192 | switch (c = *p++) | |
10193 | { | |
9bcd4f99 TS |
10194 | case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break; |
10195 | case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break; | |
10196 | case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break; | |
10197 | case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break; | |
af7ee8bf CD |
10198 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
10199 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
10200 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
bbcc0807 CD |
10201 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); |
10202 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
5f74bc13 CD |
10203 | case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
10204 | case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
10205 | case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
10206 | case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
10207 | case 'I': break; | |
ef2e4d86 CF |
10208 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; |
10209 | case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT); | |
10210 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
bb35fb24 NC |
10211 | case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; |
10212 | case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; | |
10213 | case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; | |
10214 | case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; | |
dd3cbb7e | 10215 | case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break; |
bb35fb24 NC |
10216 | case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break; |
10217 | case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break; | |
98675402 RS |
10218 | case 'z': USE_BITS (OP_MASK_RZ, OP_SH_RZ); break; |
10219 | case 'Z': USE_BITS (OP_MASK_FZ, OP_SH_FZ); break; | |
10220 | case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break; | |
10221 | case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break; | |
10222 | case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break; | |
bb35fb24 | 10223 | |
af7ee8bf CD |
10224 | default: |
10225 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
10226 | c, opc->name, opc->args); | |
10227 | return 0; | |
10228 | } | |
10229 | break; | |
252b5132 RH |
10230 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
10231 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
10232 | case 'A': break; | |
4372b673 | 10233 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
10234 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
10235 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
10236 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
10237 | case 'F': break; | |
10238 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 10239 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 10240 | case 'I': break; |
e972090a | 10241 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 10242 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
10243 | case 'L': break; |
10244 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
10245 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
10246 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
10247 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
10248 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
10249 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
10250 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
10251 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
10252 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
10253 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
10254 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
10255 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
10256 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
10257 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
10258 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10259 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
10260 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
10261 | case 'f': break; | |
10262 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
10263 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
10264 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
10265 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
10266 | case 'l': break; | |
10267 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
10268 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
10269 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
10270 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10271 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10272 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
10273 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
10274 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10275 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
10276 | case 'x': break; | |
10277 | case 'z': break; | |
10278 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
10279 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
10280 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
10281 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
10282 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
10283 | case '[': break; | |
10284 | case ']': break; | |
620edafd | 10285 | case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8b082fb1 | 10286 | case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break; |
74cd071d CF |
10287 | case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break; |
10288 | case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break; | |
10289 | case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break; | |
10290 | case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10291 | case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break; | |
10292 | case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break; | |
10293 | case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break; | |
10294 | case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break; | |
10295 | case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break; | |
10296 | case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break; | |
10297 | case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break; | |
ef2e4d86 CF |
10298 | case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break; |
10299 | case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break; | |
10300 | case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break; | |
10301 | case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break; | |
dec0624d MR |
10302 | case '\\': USE_BITS (OP_MASK_3BITPOS, OP_SH_3BITPOS); break; |
10303 | case '~': USE_BITS (OP_MASK_OFFSET12, OP_SH_OFFSET12); break; | |
ef2e4d86 | 10304 | case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
10305 | default: |
10306 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
10307 | c, opc->name, opc->args); | |
10308 | return 0; | |
10309 | } | |
10310 | #undef USE_BITS | |
10311 | if (used_bits != 0xffffffff) | |
10312 | { | |
10313 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
10314 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
10315 | return 0; | |
10316 | } | |
10317 | return 1; | |
10318 | } | |
10319 | ||
df58fc94 RS |
10320 | /* For consistency checking, verify that the length implied matches the |
10321 | major opcode and that all bits are specified either by the match/mask | |
10322 | part of the instruction definition, or by the operand list. */ | |
10323 | ||
10324 | static int | |
10325 | validate_micromips_insn (const struct mips_opcode *opc) | |
10326 | { | |
10327 | unsigned long match = opc->match; | |
10328 | unsigned long mask = opc->mask; | |
10329 | const char *p = opc->args; | |
10330 | unsigned long insn_bits; | |
10331 | unsigned long used_bits; | |
10332 | unsigned long major; | |
10333 | unsigned int length; | |
10334 | char e; | |
10335 | char c; | |
10336 | ||
10337 | if ((mask & match) != match) | |
10338 | { | |
10339 | as_bad (_("Internal error: bad microMIPS opcode (mask error): %s %s"), | |
10340 | opc->name, opc->args); | |
10341 | return 0; | |
10342 | } | |
10343 | length = micromips_insn_length (opc); | |
10344 | if (length != 2 && length != 4) | |
10345 | { | |
10346 | as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): " | |
10347 | "%s %s"), length, opc->name, opc->args); | |
10348 | return 0; | |
10349 | } | |
10350 | major = match >> (10 + 8 * (length - 2)); | |
10351 | if ((length == 2 && (major & 7) != 1 && (major & 6) != 2) | |
10352 | || (length == 4 && (major & 7) != 0 && (major & 4) != 4)) | |
10353 | { | |
10354 | as_bad (_("Internal error: bad microMIPS opcode " | |
10355 | "(opcode/length mismatch): %s %s"), opc->name, opc->args); | |
10356 | return 0; | |
10357 | } | |
10358 | ||
10359 | /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */ | |
10360 | insn_bits = 1 << 4 * length; | |
10361 | insn_bits <<= 4 * length; | |
10362 | insn_bits -= 1; | |
10363 | used_bits = mask; | |
10364 | #define USE_BITS(field) \ | |
10365 | (used_bits |= MICROMIPSOP_MASK_##field << MICROMIPSOP_SH_##field) | |
10366 | while (*p) | |
10367 | switch (c = *p++) | |
10368 | { | |
10369 | case ',': break; | |
10370 | case '(': break; | |
10371 | case ')': break; | |
10372 | case '+': | |
10373 | e = c; | |
10374 | switch (c = *p++) | |
10375 | { | |
10376 | case 'A': USE_BITS (EXTLSB); break; | |
10377 | case 'B': USE_BITS (INSMSB); break; | |
10378 | case 'C': USE_BITS (EXTMSBD); break; | |
10379 | case 'D': USE_BITS (RS); USE_BITS (SEL); break; | |
10380 | case 'E': USE_BITS (EXTLSB); break; | |
10381 | case 'F': USE_BITS (INSMSB); break; | |
10382 | case 'G': USE_BITS (EXTMSBD); break; | |
10383 | case 'H': USE_BITS (EXTMSBD); break; | |
10384 | default: | |
10385 | as_bad (_("Internal error: bad mips opcode " | |
10386 | "(unknown extension operand type `%c%c'): %s %s"), | |
10387 | e, c, opc->name, opc->args); | |
10388 | return 0; | |
10389 | } | |
10390 | break; | |
10391 | case 'm': | |
10392 | e = c; | |
10393 | switch (c = *p++) | |
10394 | { | |
10395 | case 'A': USE_BITS (IMMA); break; | |
10396 | case 'B': USE_BITS (IMMB); break; | |
10397 | case 'C': USE_BITS (IMMC); break; | |
10398 | case 'D': USE_BITS (IMMD); break; | |
10399 | case 'E': USE_BITS (IMME); break; | |
10400 | case 'F': USE_BITS (IMMF); break; | |
10401 | case 'G': USE_BITS (IMMG); break; | |
10402 | case 'H': USE_BITS (IMMH); break; | |
10403 | case 'I': USE_BITS (IMMI); break; | |
10404 | case 'J': USE_BITS (IMMJ); break; | |
10405 | case 'L': USE_BITS (IMML); break; | |
10406 | case 'M': USE_BITS (IMMM); break; | |
10407 | case 'N': USE_BITS (IMMN); break; | |
10408 | case 'O': USE_BITS (IMMO); break; | |
10409 | case 'P': USE_BITS (IMMP); break; | |
10410 | case 'Q': USE_BITS (IMMQ); break; | |
10411 | case 'U': USE_BITS (IMMU); break; | |
10412 | case 'W': USE_BITS (IMMW); break; | |
10413 | case 'X': USE_BITS (IMMX); break; | |
10414 | case 'Y': USE_BITS (IMMY); break; | |
10415 | case 'Z': break; | |
10416 | case 'a': break; | |
10417 | case 'b': USE_BITS (MB); break; | |
10418 | case 'c': USE_BITS (MC); break; | |
10419 | case 'd': USE_BITS (MD); break; | |
10420 | case 'e': USE_BITS (ME); break; | |
10421 | case 'f': USE_BITS (MF); break; | |
10422 | case 'g': USE_BITS (MG); break; | |
10423 | case 'h': USE_BITS (MH); break; | |
10424 | case 'i': USE_BITS (MI); break; | |
10425 | case 'j': USE_BITS (MJ); break; | |
10426 | case 'l': USE_BITS (ML); break; | |
10427 | case 'm': USE_BITS (MM); break; | |
10428 | case 'n': USE_BITS (MN); break; | |
10429 | case 'p': USE_BITS (MP); break; | |
10430 | case 'q': USE_BITS (MQ); break; | |
10431 | case 'r': break; | |
10432 | case 's': break; | |
10433 | case 't': break; | |
10434 | case 'x': break; | |
10435 | case 'y': break; | |
10436 | case 'z': break; | |
10437 | default: | |
10438 | as_bad (_("Internal error: bad mips opcode " | |
10439 | "(unknown extension operand type `%c%c'): %s %s"), | |
10440 | e, c, opc->name, opc->args); | |
10441 | return 0; | |
10442 | } | |
10443 | break; | |
10444 | case '.': USE_BITS (OFFSET10); break; | |
10445 | case '1': USE_BITS (STYPE); break; | |
10446 | case '<': USE_BITS (SHAMT); break; | |
10447 | case '>': USE_BITS (SHAMT); break; | |
10448 | case 'B': USE_BITS (CODE10); break; | |
10449 | case 'C': USE_BITS (COPZ); break; | |
10450 | case 'D': USE_BITS (FD); break; | |
10451 | case 'E': USE_BITS (RT); break; | |
10452 | case 'G': USE_BITS (RS); break; | |
444d75be | 10453 | case 'H': USE_BITS (SEL); break; |
df58fc94 RS |
10454 | case 'K': USE_BITS (RS); break; |
10455 | case 'M': USE_BITS (CCC); break; | |
10456 | case 'N': USE_BITS (BCC); break; | |
10457 | case 'R': USE_BITS (FR); break; | |
10458 | case 'S': USE_BITS (FS); break; | |
10459 | case 'T': USE_BITS (FT); break; | |
10460 | case 'V': USE_BITS (FS); break; | |
dec0624d | 10461 | case '\\': USE_BITS (3BITPOS); break; |
df58fc94 RS |
10462 | case 'a': USE_BITS (TARGET); break; |
10463 | case 'b': USE_BITS (RS); break; | |
10464 | case 'c': USE_BITS (CODE); break; | |
10465 | case 'd': USE_BITS (RD); break; | |
10466 | case 'h': USE_BITS (PREFX); break; | |
10467 | case 'i': USE_BITS (IMMEDIATE); break; | |
10468 | case 'j': USE_BITS (DELTA); break; | |
10469 | case 'k': USE_BITS (CACHE); break; | |
10470 | case 'n': USE_BITS (RT); break; | |
10471 | case 'o': USE_BITS (DELTA); break; | |
10472 | case 'p': USE_BITS (DELTA); break; | |
10473 | case 'q': USE_BITS (CODE2); break; | |
10474 | case 'r': USE_BITS (RS); break; | |
10475 | case 's': USE_BITS (RS); break; | |
10476 | case 't': USE_BITS (RT); break; | |
10477 | case 'u': USE_BITS (IMMEDIATE); break; | |
10478 | case 'v': USE_BITS (RS); break; | |
10479 | case 'w': USE_BITS (RT); break; | |
10480 | case 'y': USE_BITS (RS3); break; | |
10481 | case 'z': break; | |
10482 | case '|': USE_BITS (TRAP); break; | |
10483 | case '~': USE_BITS (OFFSET12); break; | |
10484 | default: | |
10485 | as_bad (_("Internal error: bad microMIPS opcode " | |
10486 | "(unknown operand type `%c'): %s %s"), | |
10487 | c, opc->name, opc->args); | |
10488 | return 0; | |
10489 | } | |
10490 | #undef USE_BITS | |
10491 | if (used_bits != insn_bits) | |
10492 | { | |
10493 | if (~used_bits & insn_bits) | |
10494 | as_bad (_("Internal error: bad microMIPS opcode " | |
10495 | "(bits 0x%lx undefined): %s %s"), | |
10496 | ~used_bits & insn_bits, opc->name, opc->args); | |
10497 | if (used_bits & ~insn_bits) | |
10498 | as_bad (_("Internal error: bad microMIPS opcode " | |
10499 | "(bits 0x%lx defined): %s %s"), | |
10500 | used_bits & ~insn_bits, opc->name, opc->args); | |
10501 | return 0; | |
10502 | } | |
10503 | return 1; | |
10504 | } | |
10505 | ||
9bcd4f99 TS |
10506 | /* UDI immediates. */ |
10507 | struct mips_immed { | |
10508 | char type; | |
10509 | unsigned int shift; | |
10510 | unsigned long mask; | |
10511 | const char * desc; | |
10512 | }; | |
10513 | ||
10514 | static const struct mips_immed mips_immed[] = { | |
10515 | { '1', OP_SH_UDI1, OP_MASK_UDI1, 0}, | |
10516 | { '2', OP_SH_UDI2, OP_MASK_UDI2, 0}, | |
10517 | { '3', OP_SH_UDI3, OP_MASK_UDI3, 0}, | |
10518 | { '4', OP_SH_UDI4, OP_MASK_UDI4, 0}, | |
10519 | { 0,0,0,0 } | |
10520 | }; | |
10521 | ||
7455baf8 TS |
10522 | /* Check whether an odd floating-point register is allowed. */ |
10523 | static int | |
10524 | mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum) | |
10525 | { | |
10526 | const char *s = insn->name; | |
10527 | ||
10528 | if (insn->pinfo == INSN_MACRO) | |
10529 | /* Let a macro pass, we'll catch it later when it is expanded. */ | |
10530 | return 1; | |
10531 | ||
10532 | if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa)) | |
10533 | { | |
10534 | /* Allow odd registers for single-precision ops. */ | |
10535 | switch (insn->pinfo & (FP_S | FP_D)) | |
10536 | { | |
10537 | case FP_S: | |
10538 | case 0: | |
10539 | return 1; /* both single precision - ok */ | |
10540 | case FP_D: | |
10541 | return 0; /* both double precision - fail */ | |
10542 | default: | |
10543 | break; | |
10544 | } | |
10545 | ||
10546 | /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ | |
10547 | s = strchr (insn->name, '.'); | |
10548 | if (argnum == 2) | |
10549 | s = s != NULL ? strchr (s + 1, '.') : NULL; | |
10550 | return (s != NULL && (s[1] == 'w' || s[1] == 's')); | |
10551 | } | |
10552 | ||
10553 | /* Single-precision coprocessor loads and moves are OK too. */ | |
10554 | if ((insn->pinfo & FP_S) | |
10555 | && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY | |
10556 | | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY))) | |
10557 | return 1; | |
10558 | ||
10559 | return 0; | |
10560 | } | |
10561 | ||
df58fc94 RS |
10562 | /* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive) |
10563 | taking bits from BIT up. */ | |
10564 | static int | |
10565 | expr_const_in_range (expressionS *ep, offsetT min, offsetT max, int bit) | |
10566 | { | |
10567 | return (ep->X_op == O_constant | |
10568 | && (ep->X_add_number & ((1 << bit) - 1)) == 0 | |
10569 | && ep->X_add_number >= min << bit | |
10570 | && ep->X_add_number < max << bit); | |
10571 | } | |
10572 | ||
252b5132 RH |
10573 | /* This routine assembles an instruction into its binary format. As a |
10574 | side effect, it sets one of the global variables imm_reloc or | |
10575 | offset_reloc to the type of relocation to do if one of the operands | |
10576 | is an address expression. */ | |
10577 | ||
10578 | static void | |
17a2f251 | 10579 | mips_ip (char *str, struct mips_cl_insn *ip) |
252b5132 | 10580 | { |
df58fc94 RS |
10581 | bfd_boolean wrong_delay_slot_insns = FALSE; |
10582 | bfd_boolean need_delay_slot_ok = TRUE; | |
10583 | struct mips_opcode *firstinsn = NULL; | |
10584 | const struct mips_opcode *past; | |
10585 | struct hash_control *hash; | |
252b5132 RH |
10586 | char *s; |
10587 | const char *args; | |
43841e91 | 10588 | char c = 0; |
252b5132 RH |
10589 | struct mips_opcode *insn; |
10590 | char *argsStart; | |
10591 | unsigned int regno; | |
34224acf | 10592 | unsigned int lastregno; |
df58fc94 | 10593 | unsigned int destregno = 0; |
af7ee8bf | 10594 | unsigned int lastpos = 0; |
071742cf | 10595 | unsigned int limlo, limhi; |
252b5132 | 10596 | char *s_reset; |
74cd071d | 10597 | offsetT min_range, max_range; |
df58fc94 | 10598 | long opend; |
a40bc9dd | 10599 | char *name; |
707bfff6 TS |
10600 | int argnum; |
10601 | unsigned int rtype; | |
df58fc94 | 10602 | char *dot; |
a40bc9dd | 10603 | long end; |
252b5132 RH |
10604 | |
10605 | insn_error = NULL; | |
10606 | ||
df58fc94 RS |
10607 | if (mips_opts.micromips) |
10608 | { | |
10609 | hash = micromips_op_hash; | |
10610 | past = µmips_opcodes[bfd_micromips_num_opcodes]; | |
10611 | } | |
10612 | else | |
10613 | { | |
10614 | hash = op_hash; | |
10615 | past = &mips_opcodes[NUMOPCODES]; | |
10616 | } | |
10617 | forced_insn_length = 0; | |
252b5132 | 10618 | insn = NULL; |
252b5132 | 10619 | |
df58fc94 | 10620 | /* We first try to match an instruction up to a space or to the end. */ |
a40bc9dd RS |
10621 | for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++) |
10622 | continue; | |
bdaaa2e1 | 10623 | |
a40bc9dd RS |
10624 | /* Make a copy of the instruction so that we can fiddle with it. */ |
10625 | name = alloca (end + 1); | |
10626 | memcpy (name, str, end); | |
10627 | name[end] = '\0'; | |
252b5132 | 10628 | |
df58fc94 RS |
10629 | for (;;) |
10630 | { | |
10631 | insn = (struct mips_opcode *) hash_find (hash, name); | |
10632 | ||
10633 | if (insn != NULL || !mips_opts.micromips) | |
10634 | break; | |
10635 | if (forced_insn_length) | |
10636 | break; | |
10637 | ||
10638 | /* See if there's an instruction size override suffix, | |
10639 | either `16' or `32', at the end of the mnemonic proper, | |
10640 | that defines the operation, i.e. before the first `.' | |
10641 | character if any. Strip it and retry. */ | |
10642 | dot = strchr (name, '.'); | |
10643 | opend = dot != NULL ? dot - name : end; | |
10644 | if (opend < 3) | |
10645 | break; | |
10646 | if (name[opend - 2] == '1' && name[opend - 1] == '6') | |
10647 | forced_insn_length = 2; | |
10648 | else if (name[opend - 2] == '3' && name[opend - 1] == '2') | |
10649 | forced_insn_length = 4; | |
10650 | else | |
10651 | break; | |
10652 | memcpy (name + opend - 2, name + opend, end - opend + 1); | |
10653 | } | |
252b5132 RH |
10654 | if (insn == NULL) |
10655 | { | |
a40bc9dd RS |
10656 | insn_error = _("Unrecognized opcode"); |
10657 | return; | |
252b5132 RH |
10658 | } |
10659 | ||
df58fc94 RS |
10660 | /* For microMIPS instructions placed in a fixed-length branch delay slot |
10661 | we make up to two passes over the relevant fragment of the opcode | |
10662 | table. First we try instructions that meet the delay slot's length | |
10663 | requirement. If none matched, then we retry with the remaining ones | |
10664 | and if one matches, then we use it and then issue an appropriate | |
10665 | warning later on. */ | |
a40bc9dd | 10666 | argsStart = s = str + end; |
252b5132 RH |
10667 | for (;;) |
10668 | { | |
df58fc94 RS |
10669 | bfd_boolean delay_slot_ok; |
10670 | bfd_boolean size_ok; | |
b34976b6 | 10671 | bfd_boolean ok; |
252b5132 | 10672 | |
a40bc9dd | 10673 | gas_assert (strcmp (insn->name, name) == 0); |
252b5132 | 10674 | |
f79e2745 | 10675 | ok = is_opcode_valid (insn); |
df58fc94 RS |
10676 | size_ok = is_size_valid (insn); |
10677 | delay_slot_ok = is_delay_slot_valid (insn); | |
10678 | if (!delay_slot_ok && !wrong_delay_slot_insns) | |
252b5132 | 10679 | { |
df58fc94 RS |
10680 | firstinsn = insn; |
10681 | wrong_delay_slot_insns = TRUE; | |
10682 | } | |
10683 | if (!ok || !size_ok || delay_slot_ok != need_delay_slot_ok) | |
10684 | { | |
10685 | static char buf[256]; | |
10686 | ||
10687 | if (insn + 1 < past && strcmp (insn->name, insn[1].name) == 0) | |
252b5132 RH |
10688 | { |
10689 | ++insn; | |
10690 | continue; | |
10691 | } | |
df58fc94 | 10692 | if (wrong_delay_slot_insns && need_delay_slot_ok) |
beae10d5 | 10693 | { |
df58fc94 RS |
10694 | gas_assert (firstinsn); |
10695 | need_delay_slot_ok = FALSE; | |
10696 | past = insn + 1; | |
10697 | insn = firstinsn; | |
10698 | continue; | |
252b5132 | 10699 | } |
df58fc94 RS |
10700 | |
10701 | if (insn_error) | |
10702 | return; | |
10703 | ||
10704 | if (!ok) | |
10705 | sprintf (buf, _("opcode not supported on this processor: %s (%s)"), | |
10706 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
10707 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
10708 | else | |
10709 | sprintf (buf, _("Unrecognized %u-bit version of microMIPS opcode"), | |
10710 | 8 * forced_insn_length); | |
10711 | insn_error = buf; | |
10712 | ||
10713 | return; | |
252b5132 RH |
10714 | } |
10715 | ||
1e915849 | 10716 | create_insn (ip, insn); |
268f6bed | 10717 | insn_error = NULL; |
707bfff6 | 10718 | argnum = 1; |
24864476 | 10719 | lastregno = 0xffffffff; |
252b5132 RH |
10720 | for (args = insn->args;; ++args) |
10721 | { | |
deec1734 CD |
10722 | int is_mdmx; |
10723 | ||
ad8d3bb3 | 10724 | s += strspn (s, " \t"); |
deec1734 | 10725 | is_mdmx = 0; |
252b5132 RH |
10726 | switch (*args) |
10727 | { | |
10728 | case '\0': /* end of args */ | |
10729 | if (*s == '\0') | |
10730 | return; | |
10731 | break; | |
10732 | ||
90ecf173 | 10733 | case '2': /* DSP 2-bit unsigned immediate in bit 11. */ |
df58fc94 | 10734 | gas_assert (!mips_opts.micromips); |
8b082fb1 TS |
10735 | my_getExpression (&imm_expr, s); |
10736 | check_absolute_expr (ip, &imm_expr); | |
10737 | if ((unsigned long) imm_expr.X_add_number != 1 | |
10738 | && (unsigned long) imm_expr.X_add_number != 3) | |
10739 | { | |
10740 | as_bad (_("BALIGN immediate not 1 or 3 (%lu)"), | |
10741 | (unsigned long) imm_expr.X_add_number); | |
10742 | } | |
df58fc94 | 10743 | INSERT_OPERAND (0, BP, *ip, imm_expr.X_add_number); |
8b082fb1 TS |
10744 | imm_expr.X_op = O_absent; |
10745 | s = expr_end; | |
10746 | continue; | |
10747 | ||
90ecf173 | 10748 | case '3': /* DSP 3-bit unsigned immediate in bit 21. */ |
df58fc94 | 10749 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10750 | my_getExpression (&imm_expr, s); |
10751 | check_absolute_expr (ip, &imm_expr); | |
10752 | if (imm_expr.X_add_number & ~OP_MASK_SA3) | |
10753 | { | |
a9e24354 TS |
10754 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
10755 | OP_MASK_SA3, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 10756 | } |
df58fc94 | 10757 | INSERT_OPERAND (0, SA3, *ip, imm_expr.X_add_number); |
74cd071d CF |
10758 | imm_expr.X_op = O_absent; |
10759 | s = expr_end; | |
10760 | continue; | |
10761 | ||
90ecf173 | 10762 | case '4': /* DSP 4-bit unsigned immediate in bit 21. */ |
df58fc94 | 10763 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10764 | my_getExpression (&imm_expr, s); |
10765 | check_absolute_expr (ip, &imm_expr); | |
10766 | if (imm_expr.X_add_number & ~OP_MASK_SA4) | |
10767 | { | |
a9e24354 TS |
10768 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
10769 | OP_MASK_SA4, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 10770 | } |
df58fc94 | 10771 | INSERT_OPERAND (0, SA4, *ip, imm_expr.X_add_number); |
74cd071d CF |
10772 | imm_expr.X_op = O_absent; |
10773 | s = expr_end; | |
10774 | continue; | |
10775 | ||
90ecf173 | 10776 | case '5': /* DSP 8-bit unsigned immediate in bit 16. */ |
df58fc94 | 10777 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10778 | my_getExpression (&imm_expr, s); |
10779 | check_absolute_expr (ip, &imm_expr); | |
10780 | if (imm_expr.X_add_number & ~OP_MASK_IMM8) | |
10781 | { | |
a9e24354 TS |
10782 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
10783 | OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 10784 | } |
df58fc94 | 10785 | INSERT_OPERAND (0, IMM8, *ip, imm_expr.X_add_number); |
74cd071d CF |
10786 | imm_expr.X_op = O_absent; |
10787 | s = expr_end; | |
10788 | continue; | |
10789 | ||
90ecf173 | 10790 | case '6': /* DSP 5-bit unsigned immediate in bit 21. */ |
df58fc94 | 10791 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10792 | my_getExpression (&imm_expr, s); |
10793 | check_absolute_expr (ip, &imm_expr); | |
10794 | if (imm_expr.X_add_number & ~OP_MASK_RS) | |
10795 | { | |
a9e24354 TS |
10796 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
10797 | OP_MASK_RS, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 10798 | } |
df58fc94 | 10799 | INSERT_OPERAND (0, RS, *ip, imm_expr.X_add_number); |
74cd071d CF |
10800 | imm_expr.X_op = O_absent; |
10801 | s = expr_end; | |
10802 | continue; | |
10803 | ||
90ecf173 | 10804 | case '7': /* Four DSP accumulators in bits 11,12. */ |
df58fc94 | 10805 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10806 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
10807 | s[3] >= '0' && s[3] <= '3') | |
10808 | { | |
10809 | regno = s[3] - '0'; | |
10810 | s += 4; | |
df58fc94 | 10811 | INSERT_OPERAND (0, DSPACC, *ip, regno); |
74cd071d CF |
10812 | continue; |
10813 | } | |
10814 | else | |
10815 | as_bad (_("Invalid dsp acc register")); | |
10816 | break; | |
10817 | ||
90ecf173 | 10818 | case '8': /* DSP 6-bit unsigned immediate in bit 11. */ |
df58fc94 | 10819 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10820 | my_getExpression (&imm_expr, s); |
10821 | check_absolute_expr (ip, &imm_expr); | |
10822 | if (imm_expr.X_add_number & ~OP_MASK_WRDSP) | |
10823 | { | |
a9e24354 TS |
10824 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
10825 | OP_MASK_WRDSP, | |
10826 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 10827 | } |
df58fc94 | 10828 | INSERT_OPERAND (0, WRDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
10829 | imm_expr.X_op = O_absent; |
10830 | s = expr_end; | |
10831 | continue; | |
10832 | ||
90ecf173 | 10833 | case '9': /* Four DSP accumulators in bits 21,22. */ |
df58fc94 | 10834 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10835 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
10836 | s[3] >= '0' && s[3] <= '3') | |
10837 | { | |
10838 | regno = s[3] - '0'; | |
10839 | s += 4; | |
df58fc94 | 10840 | INSERT_OPERAND (0, DSPACC_S, *ip, regno); |
74cd071d CF |
10841 | continue; |
10842 | } | |
10843 | else | |
10844 | as_bad (_("Invalid dsp acc register")); | |
10845 | break; | |
10846 | ||
90ecf173 | 10847 | case '0': /* DSP 6-bit signed immediate in bit 20. */ |
df58fc94 | 10848 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10849 | my_getExpression (&imm_expr, s); |
10850 | check_absolute_expr (ip, &imm_expr); | |
10851 | min_range = -((OP_MASK_DSPSFT + 1) >> 1); | |
10852 | max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1; | |
10853 | if (imm_expr.X_add_number < min_range || | |
10854 | imm_expr.X_add_number > max_range) | |
10855 | { | |
a9e24354 TS |
10856 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
10857 | (long) min_range, (long) max_range, | |
10858 | (long) imm_expr.X_add_number); | |
74cd071d | 10859 | } |
df58fc94 | 10860 | INSERT_OPERAND (0, DSPSFT, *ip, imm_expr.X_add_number); |
74cd071d CF |
10861 | imm_expr.X_op = O_absent; |
10862 | s = expr_end; | |
10863 | continue; | |
10864 | ||
90ecf173 | 10865 | case '\'': /* DSP 6-bit unsigned immediate in bit 16. */ |
df58fc94 | 10866 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10867 | my_getExpression (&imm_expr, s); |
10868 | check_absolute_expr (ip, &imm_expr); | |
10869 | if (imm_expr.X_add_number & ~OP_MASK_RDDSP) | |
10870 | { | |
a9e24354 TS |
10871 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
10872 | OP_MASK_RDDSP, | |
10873 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 10874 | } |
df58fc94 | 10875 | INSERT_OPERAND (0, RDDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
10876 | imm_expr.X_op = O_absent; |
10877 | s = expr_end; | |
10878 | continue; | |
10879 | ||
90ecf173 | 10880 | case ':': /* DSP 7-bit signed immediate in bit 19. */ |
df58fc94 | 10881 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10882 | my_getExpression (&imm_expr, s); |
10883 | check_absolute_expr (ip, &imm_expr); | |
10884 | min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1); | |
10885 | max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1; | |
10886 | if (imm_expr.X_add_number < min_range || | |
10887 | imm_expr.X_add_number > max_range) | |
10888 | { | |
a9e24354 TS |
10889 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
10890 | (long) min_range, (long) max_range, | |
10891 | (long) imm_expr.X_add_number); | |
74cd071d | 10892 | } |
df58fc94 | 10893 | INSERT_OPERAND (0, DSPSFT_7, *ip, imm_expr.X_add_number); |
74cd071d CF |
10894 | imm_expr.X_op = O_absent; |
10895 | s = expr_end; | |
10896 | continue; | |
10897 | ||
90ecf173 | 10898 | case '@': /* DSP 10-bit signed immediate in bit 16. */ |
df58fc94 | 10899 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
10900 | my_getExpression (&imm_expr, s); |
10901 | check_absolute_expr (ip, &imm_expr); | |
10902 | min_range = -((OP_MASK_IMM10 + 1) >> 1); | |
10903 | max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1; | |
10904 | if (imm_expr.X_add_number < min_range || | |
10905 | imm_expr.X_add_number > max_range) | |
10906 | { | |
a9e24354 TS |
10907 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
10908 | (long) min_range, (long) max_range, | |
10909 | (long) imm_expr.X_add_number); | |
74cd071d | 10910 | } |
df58fc94 | 10911 | INSERT_OPERAND (0, IMM10, *ip, imm_expr.X_add_number); |
74cd071d CF |
10912 | imm_expr.X_op = O_absent; |
10913 | s = expr_end; | |
10914 | continue; | |
10915 | ||
a9e24354 | 10916 | case '!': /* MT usermode flag bit. */ |
df58fc94 | 10917 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
10918 | my_getExpression (&imm_expr, s); |
10919 | check_absolute_expr (ip, &imm_expr); | |
10920 | if (imm_expr.X_add_number & ~OP_MASK_MT_U) | |
a9e24354 TS |
10921 | as_bad (_("MT usermode bit not 0 or 1 (%lu)"), |
10922 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 10923 | INSERT_OPERAND (0, MT_U, *ip, imm_expr.X_add_number); |
ef2e4d86 CF |
10924 | imm_expr.X_op = O_absent; |
10925 | s = expr_end; | |
10926 | continue; | |
10927 | ||
a9e24354 | 10928 | case '$': /* MT load high flag bit. */ |
df58fc94 | 10929 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
10930 | my_getExpression (&imm_expr, s); |
10931 | check_absolute_expr (ip, &imm_expr); | |
10932 | if (imm_expr.X_add_number & ~OP_MASK_MT_H) | |
a9e24354 TS |
10933 | as_bad (_("MT load high bit not 0 or 1 (%lu)"), |
10934 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 10935 | INSERT_OPERAND (0, MT_H, *ip, imm_expr.X_add_number); |
ef2e4d86 CF |
10936 | imm_expr.X_op = O_absent; |
10937 | s = expr_end; | |
10938 | continue; | |
10939 | ||
90ecf173 | 10940 | case '*': /* Four DSP accumulators in bits 18,19. */ |
df58fc94 | 10941 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
10942 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
10943 | s[3] >= '0' && s[3] <= '3') | |
10944 | { | |
10945 | regno = s[3] - '0'; | |
10946 | s += 4; | |
df58fc94 | 10947 | INSERT_OPERAND (0, MTACC_T, *ip, regno); |
ef2e4d86 CF |
10948 | continue; |
10949 | } | |
10950 | else | |
10951 | as_bad (_("Invalid dsp/smartmips acc register")); | |
10952 | break; | |
10953 | ||
90ecf173 | 10954 | case '&': /* Four DSP accumulators in bits 13,14. */ |
df58fc94 | 10955 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
10956 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
10957 | s[3] >= '0' && s[3] <= '3') | |
10958 | { | |
10959 | regno = s[3] - '0'; | |
10960 | s += 4; | |
df58fc94 | 10961 | INSERT_OPERAND (0, MTACC_D, *ip, regno); |
ef2e4d86 CF |
10962 | continue; |
10963 | } | |
10964 | else | |
10965 | as_bad (_("Invalid dsp/smartmips acc register")); | |
10966 | break; | |
10967 | ||
dec0624d MR |
10968 | case '\\': /* 3-bit bit position. */ |
10969 | { | |
10970 | unsigned long mask = (!mips_opts.micromips | |
10971 | ? OP_MASK_3BITPOS | |
10972 | : MICROMIPSOP_MASK_3BITPOS); | |
10973 | ||
10974 | my_getExpression (&imm_expr, s); | |
10975 | check_absolute_expr (ip, &imm_expr); | |
10976 | if ((unsigned long) imm_expr.X_add_number > mask) | |
10977 | as_warn (_("Bit position for %s not in range 0..%lu (%lu)"), | |
10978 | ip->insn_mo->name, | |
10979 | mask, (unsigned long) imm_expr.X_add_number); | |
10980 | INSERT_OPERAND (mips_opts.micromips, | |
10981 | 3BITPOS, *ip, imm_expr.X_add_number); | |
10982 | imm_expr.X_op = O_absent; | |
10983 | s = expr_end; | |
10984 | } | |
10985 | continue; | |
10986 | ||
252b5132 | 10987 | case ',': |
a339155f | 10988 | ++argnum; |
252b5132 RH |
10989 | if (*s++ == *args) |
10990 | continue; | |
10991 | s--; | |
10992 | switch (*++args) | |
10993 | { | |
10994 | case 'r': | |
10995 | case 'v': | |
df58fc94 | 10996 | INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno); |
252b5132 RH |
10997 | continue; |
10998 | ||
10999 | case 'w': | |
df58fc94 | 11000 | INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno); |
38487616 TS |
11001 | continue; |
11002 | ||
252b5132 | 11003 | case 'W': |
df58fc94 RS |
11004 | gas_assert (!mips_opts.micromips); |
11005 | INSERT_OPERAND (0, FT, *ip, lastregno); | |
252b5132 RH |
11006 | continue; |
11007 | ||
11008 | case 'V': | |
df58fc94 | 11009 | INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno); |
252b5132 RH |
11010 | continue; |
11011 | } | |
11012 | break; | |
11013 | ||
11014 | case '(': | |
11015 | /* Handle optional base register. | |
11016 | Either the base register is omitted or | |
bdaaa2e1 | 11017 | we must have a left paren. */ |
252b5132 RH |
11018 | /* This is dependent on the next operand specifier |
11019 | is a base register specification. */ | |
df58fc94 RS |
11020 | gas_assert (args[1] == 'b' |
11021 | || (mips_opts.micromips | |
11022 | && args[1] == 'm' | |
11023 | && (args[2] == 'l' || args[2] == 'n' | |
11024 | || args[2] == 's' || args[2] == 'a'))); | |
11025 | if (*s == '\0' && args[1] == 'b') | |
252b5132 | 11026 | return; |
df58fc94 | 11027 | /* Fall through. */ |
252b5132 | 11028 | |
90ecf173 | 11029 | case ')': /* These must match exactly. */ |
df58fc94 RS |
11030 | if (*s++ == *args) |
11031 | continue; | |
11032 | break; | |
11033 | ||
11034 | case '[': /* These must match exactly. */ | |
60b63b72 | 11035 | case ']': |
df58fc94 | 11036 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
11037 | if (*s++ == *args) |
11038 | continue; | |
11039 | break; | |
11040 | ||
af7ee8bf CD |
11041 | case '+': /* Opcode extension character. */ |
11042 | switch (*++args) | |
11043 | { | |
9bcd4f99 TS |
11044 | case '1': /* UDI immediates. */ |
11045 | case '2': | |
11046 | case '3': | |
11047 | case '4': | |
df58fc94 | 11048 | gas_assert (!mips_opts.micromips); |
9bcd4f99 TS |
11049 | { |
11050 | const struct mips_immed *imm = mips_immed; | |
11051 | ||
11052 | while (imm->type && imm->type != *args) | |
11053 | ++imm; | |
11054 | if (! imm->type) | |
11055 | internalError (); | |
11056 | my_getExpression (&imm_expr, s); | |
11057 | check_absolute_expr (ip, &imm_expr); | |
11058 | if ((unsigned long) imm_expr.X_add_number & ~imm->mask) | |
11059 | { | |
11060 | as_warn (_("Illegal %s number (%lu, 0x%lx)"), | |
11061 | imm->desc ? imm->desc : ip->insn_mo->name, | |
11062 | (unsigned long) imm_expr.X_add_number, | |
11063 | (unsigned long) imm_expr.X_add_number); | |
90ecf173 | 11064 | imm_expr.X_add_number &= imm->mask; |
9bcd4f99 TS |
11065 | } |
11066 | ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number | |
11067 | << imm->shift); | |
11068 | imm_expr.X_op = O_absent; | |
11069 | s = expr_end; | |
11070 | } | |
11071 | continue; | |
90ecf173 | 11072 | |
071742cf CD |
11073 | case 'A': /* ins/ext position, becomes LSB. */ |
11074 | limlo = 0; | |
11075 | limhi = 31; | |
5f74bc13 CD |
11076 | goto do_lsb; |
11077 | case 'E': | |
11078 | limlo = 32; | |
11079 | limhi = 63; | |
11080 | goto do_lsb; | |
90ecf173 | 11081 | do_lsb: |
071742cf CD |
11082 | my_getExpression (&imm_expr, s); |
11083 | check_absolute_expr (ip, &imm_expr); | |
11084 | if ((unsigned long) imm_expr.X_add_number < limlo | |
11085 | || (unsigned long) imm_expr.X_add_number > limhi) | |
11086 | { | |
11087 | as_bad (_("Improper position (%lu)"), | |
11088 | (unsigned long) imm_expr.X_add_number); | |
11089 | imm_expr.X_add_number = limlo; | |
11090 | } | |
11091 | lastpos = imm_expr.X_add_number; | |
df58fc94 RS |
11092 | INSERT_OPERAND (mips_opts.micromips, |
11093 | EXTLSB, *ip, imm_expr.X_add_number); | |
071742cf CD |
11094 | imm_expr.X_op = O_absent; |
11095 | s = expr_end; | |
11096 | continue; | |
11097 | ||
11098 | case 'B': /* ins size, becomes MSB. */ | |
11099 | limlo = 1; | |
11100 | limhi = 32; | |
5f74bc13 CD |
11101 | goto do_msb; |
11102 | case 'F': | |
11103 | limlo = 33; | |
11104 | limhi = 64; | |
11105 | goto do_msb; | |
90ecf173 | 11106 | do_msb: |
071742cf CD |
11107 | my_getExpression (&imm_expr, s); |
11108 | check_absolute_expr (ip, &imm_expr); | |
11109 | /* Check for negative input so that small negative numbers | |
11110 | will not succeed incorrectly. The checks against | |
11111 | (pos+size) transitively check "size" itself, | |
11112 | assuming that "pos" is reasonable. */ | |
11113 | if ((long) imm_expr.X_add_number < 0 | |
11114 | || ((unsigned long) imm_expr.X_add_number | |
11115 | + lastpos) < limlo | |
11116 | || ((unsigned long) imm_expr.X_add_number | |
11117 | + lastpos) > limhi) | |
11118 | { | |
11119 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
11120 | (unsigned long) imm_expr.X_add_number, | |
11121 | (unsigned long) lastpos); | |
11122 | imm_expr.X_add_number = limlo - lastpos; | |
11123 | } | |
df58fc94 RS |
11124 | INSERT_OPERAND (mips_opts.micromips, INSMSB, *ip, |
11125 | lastpos + imm_expr.X_add_number - 1); | |
071742cf CD |
11126 | imm_expr.X_op = O_absent; |
11127 | s = expr_end; | |
11128 | continue; | |
11129 | ||
11130 | case 'C': /* ext size, becomes MSBD. */ | |
11131 | limlo = 1; | |
11132 | limhi = 32; | |
5f74bc13 CD |
11133 | goto do_msbd; |
11134 | case 'G': | |
11135 | limlo = 33; | |
11136 | limhi = 64; | |
11137 | goto do_msbd; | |
11138 | case 'H': | |
11139 | limlo = 33; | |
11140 | limhi = 64; | |
11141 | goto do_msbd; | |
90ecf173 | 11142 | do_msbd: |
071742cf CD |
11143 | my_getExpression (&imm_expr, s); |
11144 | check_absolute_expr (ip, &imm_expr); | |
11145 | /* Check for negative input so that small negative numbers | |
11146 | will not succeed incorrectly. The checks against | |
11147 | (pos+size) transitively check "size" itself, | |
11148 | assuming that "pos" is reasonable. */ | |
11149 | if ((long) imm_expr.X_add_number < 0 | |
11150 | || ((unsigned long) imm_expr.X_add_number | |
11151 | + lastpos) < limlo | |
11152 | || ((unsigned long) imm_expr.X_add_number | |
11153 | + lastpos) > limhi) | |
11154 | { | |
11155 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
11156 | (unsigned long) imm_expr.X_add_number, | |
11157 | (unsigned long) lastpos); | |
11158 | imm_expr.X_add_number = limlo - lastpos; | |
11159 | } | |
df58fc94 RS |
11160 | INSERT_OPERAND (mips_opts.micromips, |
11161 | EXTMSBD, *ip, imm_expr.X_add_number - 1); | |
071742cf CD |
11162 | imm_expr.X_op = O_absent; |
11163 | s = expr_end; | |
11164 | continue; | |
af7ee8bf | 11165 | |
bbcc0807 CD |
11166 | case 'D': |
11167 | /* +D is for disassembly only; never match. */ | |
11168 | break; | |
11169 | ||
5f74bc13 CD |
11170 | case 'I': |
11171 | /* "+I" is like "I", except that imm2_expr is used. */ | |
11172 | my_getExpression (&imm2_expr, s); | |
11173 | if (imm2_expr.X_op != O_big | |
11174 | && imm2_expr.X_op != O_constant) | |
11175 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
11176 | if (HAVE_32BIT_GPRS) |
11177 | normalize_constant_expr (&imm2_expr); | |
5f74bc13 CD |
11178 | s = expr_end; |
11179 | continue; | |
11180 | ||
707bfff6 | 11181 | case 'T': /* Coprocessor register. */ |
df58fc94 | 11182 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11183 | /* +T is for disassembly only; never match. */ |
11184 | break; | |
11185 | ||
707bfff6 | 11186 | case 't': /* Coprocessor register number. */ |
df58fc94 | 11187 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11188 | if (s[0] == '$' && ISDIGIT (s[1])) |
11189 | { | |
11190 | ++s; | |
11191 | regno = 0; | |
11192 | do | |
11193 | { | |
11194 | regno *= 10; | |
11195 | regno += *s - '0'; | |
11196 | ++s; | |
11197 | } | |
11198 | while (ISDIGIT (*s)); | |
11199 | if (regno > 31) | |
11200 | as_bad (_("Invalid register number (%d)"), regno); | |
11201 | else | |
11202 | { | |
df58fc94 | 11203 | INSERT_OPERAND (0, RT, *ip, regno); |
ef2e4d86 CF |
11204 | continue; |
11205 | } | |
11206 | } | |
11207 | else | |
11208 | as_bad (_("Invalid coprocessor 0 register number")); | |
11209 | break; | |
11210 | ||
bb35fb24 NC |
11211 | case 'x': |
11212 | /* bbit[01] and bbit[01]32 bit index. Give error if index | |
11213 | is not in the valid range. */ | |
df58fc94 | 11214 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11215 | my_getExpression (&imm_expr, s); |
11216 | check_absolute_expr (ip, &imm_expr); | |
11217 | if ((unsigned) imm_expr.X_add_number > 31) | |
11218 | { | |
11219 | as_bad (_("Improper bit index (%lu)"), | |
11220 | (unsigned long) imm_expr.X_add_number); | |
11221 | imm_expr.X_add_number = 0; | |
11222 | } | |
df58fc94 | 11223 | INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11224 | imm_expr.X_op = O_absent; |
11225 | s = expr_end; | |
11226 | continue; | |
11227 | ||
11228 | case 'X': | |
11229 | /* bbit[01] bit index when bbit is used but we generate | |
11230 | bbit[01]32 because the index is over 32. Move to the | |
11231 | next candidate if index is not in the valid range. */ | |
df58fc94 | 11232 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11233 | my_getExpression (&imm_expr, s); |
11234 | check_absolute_expr (ip, &imm_expr); | |
11235 | if ((unsigned) imm_expr.X_add_number < 32 | |
11236 | || (unsigned) imm_expr.X_add_number > 63) | |
11237 | break; | |
df58fc94 | 11238 | INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number - 32); |
bb35fb24 NC |
11239 | imm_expr.X_op = O_absent; |
11240 | s = expr_end; | |
11241 | continue; | |
11242 | ||
11243 | case 'p': | |
11244 | /* cins, cins32, exts and exts32 position field. Give error | |
11245 | if it's not in the valid range. */ | |
df58fc94 | 11246 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11247 | my_getExpression (&imm_expr, s); |
11248 | check_absolute_expr (ip, &imm_expr); | |
11249 | if ((unsigned) imm_expr.X_add_number > 31) | |
11250 | { | |
11251 | as_bad (_("Improper position (%lu)"), | |
11252 | (unsigned long) imm_expr.X_add_number); | |
11253 | imm_expr.X_add_number = 0; | |
11254 | } | |
11255 | /* Make the pos explicit to simplify +S. */ | |
11256 | lastpos = imm_expr.X_add_number + 32; | |
df58fc94 | 11257 | INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11258 | imm_expr.X_op = O_absent; |
11259 | s = expr_end; | |
11260 | continue; | |
11261 | ||
11262 | case 'P': | |
11263 | /* cins, cins32, exts and exts32 position field. Move to | |
11264 | the next candidate if it's not in the valid range. */ | |
df58fc94 | 11265 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11266 | my_getExpression (&imm_expr, s); |
11267 | check_absolute_expr (ip, &imm_expr); | |
11268 | if ((unsigned) imm_expr.X_add_number < 32 | |
11269 | || (unsigned) imm_expr.X_add_number > 63) | |
11270 | break; | |
11271 | lastpos = imm_expr.X_add_number; | |
df58fc94 | 11272 | INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number - 32); |
bb35fb24 NC |
11273 | imm_expr.X_op = O_absent; |
11274 | s = expr_end; | |
11275 | continue; | |
11276 | ||
11277 | case 's': | |
11278 | /* cins and exts length-minus-one field. */ | |
df58fc94 | 11279 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11280 | my_getExpression (&imm_expr, s); |
11281 | check_absolute_expr (ip, &imm_expr); | |
11282 | if ((unsigned long) imm_expr.X_add_number > 31) | |
11283 | { | |
11284 | as_bad (_("Improper size (%lu)"), | |
11285 | (unsigned long) imm_expr.X_add_number); | |
11286 | imm_expr.X_add_number = 0; | |
11287 | } | |
df58fc94 | 11288 | INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11289 | imm_expr.X_op = O_absent; |
11290 | s = expr_end; | |
11291 | continue; | |
11292 | ||
11293 | case 'S': | |
11294 | /* cins32/exts32 and cins/exts aliasing cint32/exts32 | |
11295 | length-minus-one field. */ | |
df58fc94 | 11296 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11297 | my_getExpression (&imm_expr, s); |
11298 | check_absolute_expr (ip, &imm_expr); | |
11299 | if ((long) imm_expr.X_add_number < 0 | |
11300 | || (unsigned long) imm_expr.X_add_number + lastpos > 63) | |
11301 | { | |
11302 | as_bad (_("Improper size (%lu)"), | |
11303 | (unsigned long) imm_expr.X_add_number); | |
11304 | imm_expr.X_add_number = 0; | |
11305 | } | |
df58fc94 | 11306 | INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11307 | imm_expr.X_op = O_absent; |
11308 | s = expr_end; | |
11309 | continue; | |
11310 | ||
dd3cbb7e NC |
11311 | case 'Q': |
11312 | /* seqi/snei immediate field. */ | |
df58fc94 | 11313 | gas_assert (!mips_opts.micromips); |
dd3cbb7e NC |
11314 | my_getExpression (&imm_expr, s); |
11315 | check_absolute_expr (ip, &imm_expr); | |
11316 | if ((long) imm_expr.X_add_number < -512 | |
11317 | || (long) imm_expr.X_add_number >= 512) | |
11318 | { | |
11319 | as_bad (_("Improper immediate (%ld)"), | |
11320 | (long) imm_expr.X_add_number); | |
11321 | imm_expr.X_add_number = 0; | |
11322 | } | |
df58fc94 | 11323 | INSERT_OPERAND (0, SEQI, *ip, imm_expr.X_add_number); |
dd3cbb7e NC |
11324 | imm_expr.X_op = O_absent; |
11325 | s = expr_end; | |
11326 | continue; | |
11327 | ||
98675402 | 11328 | case 'a': /* 8-bit signed offset in bit 6 */ |
df58fc94 | 11329 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11330 | my_getExpression (&imm_expr, s); |
11331 | check_absolute_expr (ip, &imm_expr); | |
11332 | min_range = -((OP_MASK_OFFSET_A + 1) >> 1); | |
11333 | max_range = ((OP_MASK_OFFSET_A + 1) >> 1) - 1; | |
11334 | if (imm_expr.X_add_number < min_range | |
11335 | || imm_expr.X_add_number > max_range) | |
11336 | { | |
c95354ed | 11337 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
11338 | (long) min_range, (long) max_range, |
11339 | (long) imm_expr.X_add_number); | |
11340 | } | |
df58fc94 | 11341 | INSERT_OPERAND (0, OFFSET_A, *ip, imm_expr.X_add_number); |
98675402 RS |
11342 | imm_expr.X_op = O_absent; |
11343 | s = expr_end; | |
11344 | continue; | |
11345 | ||
11346 | case 'b': /* 8-bit signed offset in bit 3 */ | |
df58fc94 | 11347 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11348 | my_getExpression (&imm_expr, s); |
11349 | check_absolute_expr (ip, &imm_expr); | |
11350 | min_range = -((OP_MASK_OFFSET_B + 1) >> 1); | |
11351 | max_range = ((OP_MASK_OFFSET_B + 1) >> 1) - 1; | |
11352 | if (imm_expr.X_add_number < min_range | |
11353 | || imm_expr.X_add_number > max_range) | |
11354 | { | |
c95354ed | 11355 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
11356 | (long) min_range, (long) max_range, |
11357 | (long) imm_expr.X_add_number); | |
11358 | } | |
df58fc94 | 11359 | INSERT_OPERAND (0, OFFSET_B, *ip, imm_expr.X_add_number); |
98675402 RS |
11360 | imm_expr.X_op = O_absent; |
11361 | s = expr_end; | |
11362 | continue; | |
11363 | ||
11364 | case 'c': /* 9-bit signed offset in bit 6 */ | |
df58fc94 | 11365 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11366 | my_getExpression (&imm_expr, s); |
11367 | check_absolute_expr (ip, &imm_expr); | |
11368 | min_range = -((OP_MASK_OFFSET_C + 1) >> 1); | |
11369 | max_range = ((OP_MASK_OFFSET_C + 1) >> 1) - 1; | |
c95354ed MX |
11370 | /* We check the offset range before adjusted. */ |
11371 | min_range <<= 4; | |
11372 | max_range <<= 4; | |
98675402 RS |
11373 | if (imm_expr.X_add_number < min_range |
11374 | || imm_expr.X_add_number > max_range) | |
11375 | { | |
c95354ed | 11376 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
11377 | (long) min_range, (long) max_range, |
11378 | (long) imm_expr.X_add_number); | |
11379 | } | |
c95354ed MX |
11380 | if (imm_expr.X_add_number & 0xf) |
11381 | { | |
11382 | as_bad (_("Offset not 16 bytes alignment (%ld)"), | |
11383 | (long) imm_expr.X_add_number); | |
11384 | } | |
11385 | /* Right shift 4 bits to adjust the offset operand. */ | |
df58fc94 RS |
11386 | INSERT_OPERAND (0, OFFSET_C, *ip, |
11387 | imm_expr.X_add_number >> 4); | |
98675402 RS |
11388 | imm_expr.X_op = O_absent; |
11389 | s = expr_end; | |
11390 | continue; | |
11391 | ||
11392 | case 'z': | |
df58fc94 | 11393 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11394 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) |
11395 | break; | |
11396 | if (regno == AT && mips_opts.at) | |
11397 | { | |
11398 | if (mips_opts.at == ATREG) | |
11399 | as_warn (_("used $at without \".set noat\"")); | |
11400 | else | |
11401 | as_warn (_("used $%u with \".set at=$%u\""), | |
11402 | regno, mips_opts.at); | |
11403 | } | |
df58fc94 | 11404 | INSERT_OPERAND (0, RZ, *ip, regno); |
98675402 RS |
11405 | continue; |
11406 | ||
11407 | case 'Z': | |
df58fc94 | 11408 | gas_assert (!mips_opts.micromips); |
98675402 RS |
11409 | if (!reg_lookup (&s, RTYPE_FPU, ®no)) |
11410 | break; | |
df58fc94 | 11411 | INSERT_OPERAND (0, FZ, *ip, regno); |
98675402 RS |
11412 | continue; |
11413 | ||
af7ee8bf | 11414 | default: |
df58fc94 | 11415 | as_bad (_("Internal error: bad %s opcode " |
90ecf173 | 11416 | "(unknown extension operand type `+%c'): %s %s"), |
df58fc94 | 11417 | mips_opts.micromips ? "microMIPS" : "MIPS", |
90ecf173 | 11418 | *args, insn->name, insn->args); |
af7ee8bf CD |
11419 | /* Further processing is fruitless. */ |
11420 | return; | |
11421 | } | |
11422 | break; | |
11423 | ||
df58fc94 | 11424 | case '.': /* 10-bit offset. */ |
df58fc94 | 11425 | gas_assert (mips_opts.micromips); |
dec0624d | 11426 | case '~': /* 12-bit offset. */ |
df58fc94 RS |
11427 | { |
11428 | int shift = *args == '.' ? 9 : 11; | |
11429 | size_t i; | |
11430 | ||
11431 | /* Check whether there is only a single bracketed expression | |
11432 | left. If so, it must be the base register and the | |
11433 | constant must be zero. */ | |
11434 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
11435 | continue; | |
11436 | ||
11437 | /* If this value won't fit into the offset, then go find | |
11438 | a macro that will generate a 16- or 32-bit offset code | |
11439 | pattern. */ | |
11440 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); | |
11441 | if ((i == 0 && (imm_expr.X_op != O_constant | |
11442 | || imm_expr.X_add_number >= 1 << shift | |
11443 | || imm_expr.X_add_number < -1 << shift)) | |
11444 | || i > 0) | |
11445 | { | |
11446 | imm_expr.X_op = O_absent; | |
11447 | break; | |
11448 | } | |
11449 | if (shift == 9) | |
11450 | INSERT_OPERAND (1, OFFSET10, *ip, imm_expr.X_add_number); | |
11451 | else | |
dec0624d MR |
11452 | INSERT_OPERAND (mips_opts.micromips, |
11453 | OFFSET12, *ip, imm_expr.X_add_number); | |
df58fc94 RS |
11454 | imm_expr.X_op = O_absent; |
11455 | s = expr_end; | |
11456 | } | |
11457 | continue; | |
11458 | ||
252b5132 RH |
11459 | case '<': /* must be at least one digit */ |
11460 | /* | |
11461 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
11462 | * than 31 or less than 0, then the shift amount should be |
11463 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
11464 | * We issue a warning and mask out all but the low 5 bits. |
11465 | */ | |
11466 | my_getExpression (&imm_expr, s); | |
11467 | check_absolute_expr (ip, &imm_expr); | |
11468 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
11469 | as_warn (_("Improper shift amount (%lu)"), |
11470 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 RS |
11471 | INSERT_OPERAND (mips_opts.micromips, |
11472 | SHAMT, *ip, imm_expr.X_add_number); | |
252b5132 RH |
11473 | imm_expr.X_op = O_absent; |
11474 | s = expr_end; | |
11475 | continue; | |
11476 | ||
11477 | case '>': /* shift amount minus 32 */ | |
11478 | my_getExpression (&imm_expr, s); | |
11479 | check_absolute_expr (ip, &imm_expr); | |
11480 | if ((unsigned long) imm_expr.X_add_number < 32 | |
11481 | || (unsigned long) imm_expr.X_add_number > 63) | |
11482 | break; | |
df58fc94 RS |
11483 | INSERT_OPERAND (mips_opts.micromips, |
11484 | SHAMT, *ip, imm_expr.X_add_number - 32); | |
252b5132 RH |
11485 | imm_expr.X_op = O_absent; |
11486 | s = expr_end; | |
11487 | continue; | |
11488 | ||
90ecf173 MR |
11489 | case 'k': /* CACHE code. */ |
11490 | case 'h': /* PREFX code. */ | |
11491 | case '1': /* SYNC type. */ | |
252b5132 RH |
11492 | my_getExpression (&imm_expr, s); |
11493 | check_absolute_expr (ip, &imm_expr); | |
11494 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
11495 | as_warn (_("Invalid value for `%s' (%lu)"), |
11496 | ip->insn_mo->name, | |
11497 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 11498 | switch (*args) |
d954098f | 11499 | { |
df58fc94 RS |
11500 | case 'k': |
11501 | if (mips_fix_cn63xxp1 | |
11502 | && !mips_opts.micromips | |
11503 | && strcmp ("pref", insn->name) == 0) | |
d954098f DD |
11504 | switch (imm_expr.X_add_number) |
11505 | { | |
11506 | case 5: | |
11507 | case 25: | |
11508 | case 26: | |
11509 | case 27: | |
11510 | case 28: | |
11511 | case 29: | |
11512 | case 30: | |
11513 | case 31: /* These are ok. */ | |
11514 | break; | |
11515 | ||
11516 | default: /* The rest must be changed to 28. */ | |
11517 | imm_expr.X_add_number = 28; | |
11518 | break; | |
11519 | } | |
df58fc94 RS |
11520 | INSERT_OPERAND (mips_opts.micromips, |
11521 | CACHE, *ip, imm_expr.X_add_number); | |
11522 | break; | |
11523 | case 'h': | |
11524 | INSERT_OPERAND (mips_opts.micromips, | |
11525 | PREFX, *ip, imm_expr.X_add_number); | |
11526 | break; | |
11527 | case '1': | |
11528 | INSERT_OPERAND (mips_opts.micromips, | |
11529 | STYPE, *ip, imm_expr.X_add_number); | |
11530 | break; | |
d954098f | 11531 | } |
252b5132 RH |
11532 | imm_expr.X_op = O_absent; |
11533 | s = expr_end; | |
11534 | continue; | |
11535 | ||
90ecf173 | 11536 | case 'c': /* BREAK code. */ |
df58fc94 RS |
11537 | { |
11538 | unsigned long mask = (mips_opts.micromips | |
11539 | ? MICROMIPSOP_MASK_CODE | |
11540 | : OP_MASK_CODE); | |
11541 | ||
11542 | my_getExpression (&imm_expr, s); | |
11543 | check_absolute_expr (ip, &imm_expr); | |
11544 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11545 | as_warn (_("Code for %s not in range 0..%lu (%lu)"), | |
11546 | ip->insn_mo->name, | |
11547 | mask, (unsigned long) imm_expr.X_add_number); | |
11548 | INSERT_OPERAND (mips_opts.micromips, | |
11549 | CODE, *ip, imm_expr.X_add_number); | |
11550 | imm_expr.X_op = O_absent; | |
11551 | s = expr_end; | |
11552 | } | |
252b5132 RH |
11553 | continue; |
11554 | ||
90ecf173 | 11555 | case 'q': /* Lower BREAK code. */ |
df58fc94 RS |
11556 | { |
11557 | unsigned long mask = (mips_opts.micromips | |
11558 | ? MICROMIPSOP_MASK_CODE2 | |
11559 | : OP_MASK_CODE2); | |
11560 | ||
11561 | my_getExpression (&imm_expr, s); | |
11562 | check_absolute_expr (ip, &imm_expr); | |
11563 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11564 | as_warn (_("Lower code for %s not in range 0..%lu (%lu)"), | |
11565 | ip->insn_mo->name, | |
11566 | mask, (unsigned long) imm_expr.X_add_number); | |
11567 | INSERT_OPERAND (mips_opts.micromips, | |
11568 | CODE2, *ip, imm_expr.X_add_number); | |
11569 | imm_expr.X_op = O_absent; | |
11570 | s = expr_end; | |
11571 | } | |
252b5132 RH |
11572 | continue; |
11573 | ||
df58fc94 RS |
11574 | case 'B': /* 20- or 10-bit syscall/break/wait code. */ |
11575 | { | |
11576 | unsigned long mask = (mips_opts.micromips | |
11577 | ? MICROMIPSOP_MASK_CODE10 | |
11578 | : OP_MASK_CODE20); | |
11579 | ||
11580 | my_getExpression (&imm_expr, s); | |
11581 | check_absolute_expr (ip, &imm_expr); | |
11582 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11583 | as_warn (_("Code for %s not in range 0..%lu (%lu)"), | |
11584 | ip->insn_mo->name, | |
11585 | mask, (unsigned long) imm_expr.X_add_number); | |
11586 | if (mips_opts.micromips) | |
11587 | INSERT_OPERAND (1, CODE10, *ip, imm_expr.X_add_number); | |
11588 | else | |
11589 | INSERT_OPERAND (0, CODE20, *ip, imm_expr.X_add_number); | |
11590 | imm_expr.X_op = O_absent; | |
11591 | s = expr_end; | |
11592 | } | |
252b5132 RH |
11593 | continue; |
11594 | ||
df58fc94 RS |
11595 | case 'C': /* 25- or 23-bit coprocessor code. */ |
11596 | { | |
11597 | unsigned long mask = (mips_opts.micromips | |
11598 | ? MICROMIPSOP_MASK_COPZ | |
11599 | : OP_MASK_COPZ); | |
11600 | ||
11601 | my_getExpression (&imm_expr, s); | |
11602 | check_absolute_expr (ip, &imm_expr); | |
11603 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11604 | as_warn (_("Coproccesor code > %u bits (%lu)"), | |
11605 | mips_opts.micromips ? 23U : 25U, | |
793b27f4 | 11606 | (unsigned long) imm_expr.X_add_number); |
df58fc94 RS |
11607 | INSERT_OPERAND (mips_opts.micromips, |
11608 | COPZ, *ip, imm_expr.X_add_number); | |
11609 | imm_expr.X_op = O_absent; | |
11610 | s = expr_end; | |
11611 | } | |
beae10d5 | 11612 | continue; |
252b5132 | 11613 | |
df58fc94 RS |
11614 | case 'J': /* 19-bit WAIT code. */ |
11615 | gas_assert (!mips_opts.micromips); | |
4372b673 NC |
11616 | my_getExpression (&imm_expr, s); |
11617 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 11618 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
df58fc94 RS |
11619 | { |
11620 | as_warn (_("Illegal 19-bit code (%lu)"), | |
a9e24354 | 11621 | (unsigned long) imm_expr.X_add_number); |
df58fc94 RS |
11622 | imm_expr.X_add_number &= OP_MASK_CODE19; |
11623 | } | |
11624 | INSERT_OPERAND (0, CODE19, *ip, imm_expr.X_add_number); | |
4372b673 NC |
11625 | imm_expr.X_op = O_absent; |
11626 | s = expr_end; | |
11627 | continue; | |
11628 | ||
707bfff6 | 11629 | case 'P': /* Performance register. */ |
df58fc94 | 11630 | gas_assert (!mips_opts.micromips); |
beae10d5 | 11631 | my_getExpression (&imm_expr, s); |
252b5132 | 11632 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 11633 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
bf12938e RS |
11634 | as_warn (_("Invalid performance register (%lu)"), |
11635 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 11636 | INSERT_OPERAND (0, PERFREG, *ip, imm_expr.X_add_number); |
beae10d5 KH |
11637 | imm_expr.X_op = O_absent; |
11638 | s = expr_end; | |
11639 | continue; | |
252b5132 | 11640 | |
707bfff6 | 11641 | case 'G': /* Coprocessor destination register. */ |
df58fc94 RS |
11642 | { |
11643 | unsigned long opcode = ip->insn_opcode; | |
11644 | unsigned long mask; | |
11645 | unsigned int types; | |
11646 | int cop0; | |
11647 | ||
11648 | if (mips_opts.micromips) | |
11649 | { | |
11650 | mask = ~((MICROMIPSOP_MASK_RT << MICROMIPSOP_SH_RT) | |
11651 | | (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS) | |
11652 | | (MICROMIPSOP_MASK_SEL << MICROMIPSOP_SH_SEL)); | |
11653 | opcode &= mask; | |
11654 | switch (opcode) | |
11655 | { | |
11656 | case 0x000000fc: /* mfc0 */ | |
11657 | case 0x000002fc: /* mtc0 */ | |
11658 | case 0x580000fc: /* dmfc0 */ | |
11659 | case 0x580002fc: /* dmtc0 */ | |
11660 | cop0 = 1; | |
11661 | break; | |
11662 | default: | |
11663 | cop0 = 0; | |
11664 | break; | |
11665 | } | |
11666 | } | |
11667 | else | |
11668 | { | |
11669 | opcode = (opcode >> OP_SH_OP) & OP_MASK_OP; | |
11670 | cop0 = opcode == OP_OP_COP0; | |
11671 | } | |
11672 | types = RTYPE_NUM | (cop0 ? RTYPE_CP0 : RTYPE_GP); | |
11673 | ok = reg_lookup (&s, types, ®no); | |
11674 | if (mips_opts.micromips) | |
11675 | INSERT_OPERAND (1, RS, *ip, regno); | |
11676 | else | |
11677 | INSERT_OPERAND (0, RD, *ip, regno); | |
11678 | if (ok) | |
11679 | { | |
11680 | lastregno = regno; | |
11681 | continue; | |
11682 | } | |
11683 | } | |
11684 | break; | |
707bfff6 | 11685 | |
df58fc94 RS |
11686 | case 'y': /* ALNV.PS source register. */ |
11687 | gas_assert (mips_opts.micromips); | |
11688 | goto do_reg; | |
11689 | case 'x': /* Ignore register name. */ | |
11690 | case 'U': /* Destination register (CLO/CLZ). */ | |
11691 | case 'g': /* Coprocessor destination register. */ | |
11692 | gas_assert (!mips_opts.micromips); | |
90ecf173 MR |
11693 | case 'b': /* Base register. */ |
11694 | case 'd': /* Destination register. */ | |
11695 | case 's': /* Source register. */ | |
11696 | case 't': /* Target register. */ | |
11697 | case 'r': /* Both target and source. */ | |
11698 | case 'v': /* Both dest and source. */ | |
11699 | case 'w': /* Both dest and target. */ | |
11700 | case 'E': /* Coprocessor target register. */ | |
11701 | case 'K': /* RDHWR destination register. */ | |
90ecf173 | 11702 | case 'z': /* Must be zero register. */ |
df58fc94 | 11703 | do_reg: |
90ecf173 | 11704 | s_reset = s; |
707bfff6 TS |
11705 | if (*args == 'E' || *args == 'K') |
11706 | ok = reg_lookup (&s, RTYPE_NUM, ®no); | |
11707 | else | |
11708 | { | |
11709 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
741fe287 MR |
11710 | if (regno == AT && mips_opts.at) |
11711 | { | |
11712 | if (mips_opts.at == ATREG) | |
f71d0d44 | 11713 | as_warn (_("Used $at without \".set noat\"")); |
741fe287 | 11714 | else |
f71d0d44 | 11715 | as_warn (_("Used $%u with \".set at=$%u\""), |
741fe287 MR |
11716 | regno, mips_opts.at); |
11717 | } | |
707bfff6 TS |
11718 | } |
11719 | if (ok) | |
252b5132 | 11720 | { |
252b5132 RH |
11721 | c = *args; |
11722 | if (*s == ' ') | |
f9419b05 | 11723 | ++s; |
252b5132 RH |
11724 | if (args[1] != *s) |
11725 | { | |
11726 | if (c == 'r' || c == 'v' || c == 'w') | |
11727 | { | |
11728 | regno = lastregno; | |
11729 | s = s_reset; | |
f9419b05 | 11730 | ++args; |
252b5132 RH |
11731 | } |
11732 | } | |
11733 | /* 'z' only matches $0. */ | |
11734 | if (c == 'z' && regno != 0) | |
11735 | break; | |
11736 | ||
24864476 | 11737 | if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4)) |
e7c604dd CM |
11738 | { |
11739 | if (regno == lastregno) | |
90ecf173 MR |
11740 | { |
11741 | insn_error | |
f71d0d44 | 11742 | = _("Source and destination must be different"); |
e7c604dd | 11743 | continue; |
90ecf173 | 11744 | } |
24864476 | 11745 | if (regno == 31 && lastregno == 0xffffffff) |
90ecf173 MR |
11746 | { |
11747 | insn_error | |
f71d0d44 | 11748 | = _("A destination register must be supplied"); |
e7c604dd | 11749 | continue; |
90ecf173 | 11750 | } |
e7c604dd | 11751 | } |
90ecf173 MR |
11752 | /* Now that we have assembled one operand, we use the args |
11753 | string to figure out where it goes in the instruction. */ | |
252b5132 RH |
11754 | switch (c) |
11755 | { | |
11756 | case 'r': | |
11757 | case 's': | |
11758 | case 'v': | |
11759 | case 'b': | |
df58fc94 | 11760 | INSERT_OPERAND (mips_opts.micromips, RS, *ip, regno); |
252b5132 | 11761 | break; |
df58fc94 | 11762 | |
af7ee8bf | 11763 | case 'K': |
df58fc94 RS |
11764 | if (mips_opts.micromips) |
11765 | INSERT_OPERAND (1, RS, *ip, regno); | |
11766 | else | |
11767 | INSERT_OPERAND (0, RD, *ip, regno); | |
11768 | break; | |
11769 | ||
11770 | case 'd': | |
ef2e4d86 | 11771 | case 'g': |
df58fc94 | 11772 | INSERT_OPERAND (mips_opts.micromips, RD, *ip, regno); |
252b5132 | 11773 | break; |
df58fc94 | 11774 | |
4372b673 | 11775 | case 'U': |
df58fc94 RS |
11776 | gas_assert (!mips_opts.micromips); |
11777 | INSERT_OPERAND (0, RD, *ip, regno); | |
11778 | INSERT_OPERAND (0, RT, *ip, regno); | |
4372b673 | 11779 | break; |
df58fc94 | 11780 | |
252b5132 RH |
11781 | case 'w': |
11782 | case 't': | |
11783 | case 'E': | |
df58fc94 RS |
11784 | INSERT_OPERAND (mips_opts.micromips, RT, *ip, regno); |
11785 | break; | |
11786 | ||
11787 | case 'y': | |
11788 | gas_assert (mips_opts.micromips); | |
11789 | INSERT_OPERAND (1, RS3, *ip, regno); | |
252b5132 | 11790 | break; |
df58fc94 | 11791 | |
252b5132 RH |
11792 | case 'x': |
11793 | /* This case exists because on the r3000 trunc | |
11794 | expands into a macro which requires a gp | |
11795 | register. On the r6000 or r4000 it is | |
11796 | assembled into a single instruction which | |
11797 | ignores the register. Thus the insn version | |
11798 | is MIPS_ISA2 and uses 'x', and the macro | |
11799 | version is MIPS_ISA1 and uses 't'. */ | |
11800 | break; | |
df58fc94 | 11801 | |
252b5132 RH |
11802 | case 'z': |
11803 | /* This case is for the div instruction, which | |
11804 | acts differently if the destination argument | |
11805 | is $0. This only matches $0, and is checked | |
11806 | outside the switch. */ | |
11807 | break; | |
252b5132 RH |
11808 | } |
11809 | lastregno = regno; | |
11810 | continue; | |
11811 | } | |
252b5132 RH |
11812 | switch (*args++) |
11813 | { | |
11814 | case 'r': | |
11815 | case 'v': | |
df58fc94 | 11816 | INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno); |
252b5132 | 11817 | continue; |
df58fc94 | 11818 | |
252b5132 | 11819 | case 'w': |
df58fc94 | 11820 | INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno); |
252b5132 RH |
11821 | continue; |
11822 | } | |
11823 | break; | |
11824 | ||
deec1734 | 11825 | case 'O': /* MDMX alignment immediate constant. */ |
df58fc94 | 11826 | gas_assert (!mips_opts.micromips); |
deec1734 CD |
11827 | my_getExpression (&imm_expr, s); |
11828 | check_absolute_expr (ip, &imm_expr); | |
11829 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
20203fb9 | 11830 | as_warn (_("Improper align amount (%ld), using low bits"), |
bf12938e | 11831 | (long) imm_expr.X_add_number); |
df58fc94 | 11832 | INSERT_OPERAND (0, ALN, *ip, imm_expr.X_add_number); |
deec1734 CD |
11833 | imm_expr.X_op = O_absent; |
11834 | s = expr_end; | |
11835 | continue; | |
11836 | ||
11837 | case 'Q': /* MDMX vector, element sel, or const. */ | |
11838 | if (s[0] != '$') | |
11839 | { | |
11840 | /* MDMX Immediate. */ | |
df58fc94 | 11841 | gas_assert (!mips_opts.micromips); |
deec1734 CD |
11842 | my_getExpression (&imm_expr, s); |
11843 | check_absolute_expr (ip, &imm_expr); | |
11844 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
bf12938e RS |
11845 | as_warn (_("Invalid MDMX Immediate (%ld)"), |
11846 | (long) imm_expr.X_add_number); | |
df58fc94 | 11847 | INSERT_OPERAND (0, FT, *ip, imm_expr.X_add_number); |
deec1734 CD |
11848 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) |
11849 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
11850 | else | |
11851 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
deec1734 CD |
11852 | imm_expr.X_op = O_absent; |
11853 | s = expr_end; | |
11854 | continue; | |
11855 | } | |
11856 | /* Not MDMX Immediate. Fall through. */ | |
11857 | case 'X': /* MDMX destination register. */ | |
11858 | case 'Y': /* MDMX source register. */ | |
11859 | case 'Z': /* MDMX target register. */ | |
11860 | is_mdmx = 1; | |
df58fc94 RS |
11861 | case 'W': |
11862 | gas_assert (!mips_opts.micromips); | |
90ecf173 MR |
11863 | case 'D': /* Floating point destination register. */ |
11864 | case 'S': /* Floating point source register. */ | |
11865 | case 'T': /* Floating point target register. */ | |
11866 | case 'R': /* Floating point source register. */ | |
252b5132 | 11867 | case 'V': |
707bfff6 TS |
11868 | rtype = RTYPE_FPU; |
11869 | if (is_mdmx | |
11870 | || (mips_opts.ase_mdmx | |
11871 | && (ip->insn_mo->pinfo & FP_D) | |
11872 | && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY | |
11873 | | INSN_COPROC_MEMORY_DELAY | |
11874 | | INSN_LOAD_COPROC_DELAY | |
11875 | | INSN_LOAD_MEMORY_DELAY | |
11876 | | INSN_STORE_MEMORY)))) | |
11877 | rtype |= RTYPE_VEC; | |
252b5132 | 11878 | s_reset = s; |
707bfff6 | 11879 | if (reg_lookup (&s, rtype, ®no)) |
252b5132 | 11880 | { |
252b5132 | 11881 | if ((regno & 1) != 0 |
ca4e0257 | 11882 | && HAVE_32BIT_FPRS |
90ecf173 | 11883 | && !mips_oddfpreg_ok (ip->insn_mo, argnum)) |
252b5132 RH |
11884 | as_warn (_("Float register should be even, was %d"), |
11885 | regno); | |
11886 | ||
11887 | c = *args; | |
11888 | if (*s == ' ') | |
f9419b05 | 11889 | ++s; |
252b5132 RH |
11890 | if (args[1] != *s) |
11891 | { | |
11892 | if (c == 'V' || c == 'W') | |
11893 | { | |
11894 | regno = lastregno; | |
11895 | s = s_reset; | |
f9419b05 | 11896 | ++args; |
252b5132 RH |
11897 | } |
11898 | } | |
11899 | switch (c) | |
11900 | { | |
11901 | case 'D': | |
deec1734 | 11902 | case 'X': |
df58fc94 | 11903 | INSERT_OPERAND (mips_opts.micromips, FD, *ip, regno); |
252b5132 | 11904 | break; |
df58fc94 | 11905 | |
252b5132 RH |
11906 | case 'V': |
11907 | case 'S': | |
deec1734 | 11908 | case 'Y': |
df58fc94 | 11909 | INSERT_OPERAND (mips_opts.micromips, FS, *ip, regno); |
252b5132 | 11910 | break; |
df58fc94 | 11911 | |
deec1734 CD |
11912 | case 'Q': |
11913 | /* This is like 'Z', but also needs to fix the MDMX | |
11914 | vector/scalar select bits. Note that the | |
11915 | scalar immediate case is handled above. */ | |
11916 | if (*s == '[') | |
11917 | { | |
11918 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
11919 | int max_el = (is_qh ? 3 : 7); | |
11920 | s++; | |
11921 | my_getExpression(&imm_expr, s); | |
11922 | check_absolute_expr (ip, &imm_expr); | |
11923 | s = expr_end; | |
11924 | if (imm_expr.X_add_number > max_el) | |
20203fb9 NC |
11925 | as_bad (_("Bad element selector %ld"), |
11926 | (long) imm_expr.X_add_number); | |
deec1734 CD |
11927 | imm_expr.X_add_number &= max_el; |
11928 | ip->insn_opcode |= (imm_expr.X_add_number | |
11929 | << (OP_SH_VSEL + | |
11930 | (is_qh ? 2 : 1))); | |
01a3f561 | 11931 | imm_expr.X_op = O_absent; |
deec1734 | 11932 | if (*s != ']') |
20203fb9 | 11933 | as_warn (_("Expecting ']' found '%s'"), s); |
deec1734 CD |
11934 | else |
11935 | s++; | |
11936 | } | |
11937 | else | |
11938 | { | |
11939 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
11940 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
11941 | << OP_SH_VSEL); | |
11942 | else | |
11943 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
11944 | OP_SH_VSEL); | |
11945 | } | |
90ecf173 | 11946 | /* Fall through. */ |
252b5132 RH |
11947 | case 'W': |
11948 | case 'T': | |
deec1734 | 11949 | case 'Z': |
df58fc94 | 11950 | INSERT_OPERAND (mips_opts.micromips, FT, *ip, regno); |
252b5132 | 11951 | break; |
df58fc94 | 11952 | |
252b5132 | 11953 | case 'R': |
df58fc94 | 11954 | INSERT_OPERAND (mips_opts.micromips, FR, *ip, regno); |
252b5132 RH |
11955 | break; |
11956 | } | |
11957 | lastregno = regno; | |
11958 | continue; | |
11959 | } | |
11960 | ||
252b5132 RH |
11961 | switch (*args++) |
11962 | { | |
11963 | case 'V': | |
df58fc94 | 11964 | INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno); |
252b5132 | 11965 | continue; |
df58fc94 | 11966 | |
252b5132 | 11967 | case 'W': |
df58fc94 | 11968 | INSERT_OPERAND (mips_opts.micromips, FT, *ip, lastregno); |
252b5132 RH |
11969 | continue; |
11970 | } | |
11971 | break; | |
11972 | ||
11973 | case 'I': | |
11974 | my_getExpression (&imm_expr, s); | |
11975 | if (imm_expr.X_op != O_big | |
11976 | && imm_expr.X_op != O_constant) | |
11977 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
11978 | if (HAVE_32BIT_GPRS) |
11979 | normalize_constant_expr (&imm_expr); | |
252b5132 RH |
11980 | s = expr_end; |
11981 | continue; | |
11982 | ||
11983 | case 'A': | |
11984 | my_getExpression (&offset_expr, s); | |
2051e8c4 | 11985 | normalize_address_expr (&offset_expr); |
f6688943 | 11986 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
11987 | s = expr_end; |
11988 | continue; | |
11989 | ||
11990 | case 'F': | |
11991 | case 'L': | |
11992 | case 'f': | |
11993 | case 'l': | |
11994 | { | |
11995 | int f64; | |
ca4e0257 | 11996 | int using_gprs; |
252b5132 RH |
11997 | char *save_in; |
11998 | char *err; | |
11999 | unsigned char temp[8]; | |
12000 | int len; | |
12001 | unsigned int length; | |
12002 | segT seg; | |
12003 | subsegT subseg; | |
12004 | char *p; | |
12005 | ||
12006 | /* These only appear as the last operand in an | |
12007 | instruction, and every instruction that accepts | |
12008 | them in any variant accepts them in all variants. | |
12009 | This means we don't have to worry about backing out | |
12010 | any changes if the instruction does not match. | |
12011 | ||
12012 | The difference between them is the size of the | |
12013 | floating point constant and where it goes. For 'F' | |
12014 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
12015 | is 32 bits. Where the constant is placed is based | |
12016 | on how the MIPS assembler does things: | |
12017 | F -- .rdata | |
12018 | L -- .lit8 | |
12019 | f -- immediate value | |
12020 | l -- .lit4 | |
12021 | ||
12022 | The .lit4 and .lit8 sections are only used if | |
12023 | permitted by the -G argument. | |
12024 | ||
ca4e0257 RS |
12025 | The code below needs to know whether the target register |
12026 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
12027 | 'F' are used with GPR-based instructions and 'l' and | |
12028 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
12029 | |
12030 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 12031 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
12032 | |
12033 | save_in = input_line_pointer; | |
12034 | input_line_pointer = s; | |
12035 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
12036 | length = len; | |
12037 | s = input_line_pointer; | |
12038 | input_line_pointer = save_in; | |
12039 | if (err != NULL && *err != '\0') | |
12040 | { | |
12041 | as_bad (_("Bad floating point constant: %s"), err); | |
12042 | memset (temp, '\0', sizeof temp); | |
12043 | length = f64 ? 8 : 4; | |
12044 | } | |
12045 | ||
9c2799c2 | 12046 | gas_assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
12047 | |
12048 | if (*args == 'f' | |
12049 | || (*args == 'l' | |
3e722fb5 | 12050 | && (g_switch_value < 4 |
252b5132 RH |
12051 | || (temp[0] == 0 && temp[1] == 0) |
12052 | || (temp[2] == 0 && temp[3] == 0)))) | |
12053 | { | |
12054 | imm_expr.X_op = O_constant; | |
90ecf173 | 12055 | if (!target_big_endian) |
252b5132 RH |
12056 | imm_expr.X_add_number = bfd_getl32 (temp); |
12057 | else | |
12058 | imm_expr.X_add_number = bfd_getb32 (temp); | |
12059 | } | |
12060 | else if (length > 4 | |
90ecf173 | 12061 | && !mips_disable_float_construction |
ca4e0257 RS |
12062 | /* Constants can only be constructed in GPRs and |
12063 | copied to FPRs if the GPRs are at least as wide | |
12064 | as the FPRs. Force the constant into memory if | |
12065 | we are using 64-bit FPRs but the GPRs are only | |
12066 | 32 bits wide. */ | |
12067 | && (using_gprs | |
90ecf173 | 12068 | || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) |
252b5132 RH |
12069 | && ((temp[0] == 0 && temp[1] == 0) |
12070 | || (temp[2] == 0 && temp[3] == 0)) | |
12071 | && ((temp[4] == 0 && temp[5] == 0) | |
12072 | || (temp[6] == 0 && temp[7] == 0))) | |
12073 | { | |
ca4e0257 | 12074 | /* The value is simple enough to load with a couple of |
90ecf173 MR |
12075 | instructions. If using 32-bit registers, set |
12076 | imm_expr to the high order 32 bits and offset_expr to | |
12077 | the low order 32 bits. Otherwise, set imm_expr to | |
12078 | the entire 64 bit constant. */ | |
ca4e0257 | 12079 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) |
252b5132 RH |
12080 | { |
12081 | imm_expr.X_op = O_constant; | |
12082 | offset_expr.X_op = O_constant; | |
90ecf173 | 12083 | if (!target_big_endian) |
252b5132 RH |
12084 | { |
12085 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
12086 | offset_expr.X_add_number = bfd_getl32 (temp); | |
12087 | } | |
12088 | else | |
12089 | { | |
12090 | imm_expr.X_add_number = bfd_getb32 (temp); | |
12091 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
12092 | } | |
12093 | if (offset_expr.X_add_number == 0) | |
12094 | offset_expr.X_op = O_absent; | |
12095 | } | |
12096 | else if (sizeof (imm_expr.X_add_number) > 4) | |
12097 | { | |
12098 | imm_expr.X_op = O_constant; | |
90ecf173 | 12099 | if (!target_big_endian) |
252b5132 RH |
12100 | imm_expr.X_add_number = bfd_getl64 (temp); |
12101 | else | |
12102 | imm_expr.X_add_number = bfd_getb64 (temp); | |
12103 | } | |
12104 | else | |
12105 | { | |
12106 | imm_expr.X_op = O_big; | |
12107 | imm_expr.X_add_number = 4; | |
90ecf173 | 12108 | if (!target_big_endian) |
252b5132 RH |
12109 | { |
12110 | generic_bignum[0] = bfd_getl16 (temp); | |
12111 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
12112 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
12113 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
12114 | } | |
12115 | else | |
12116 | { | |
12117 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
12118 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
12119 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
12120 | generic_bignum[3] = bfd_getb16 (temp); | |
12121 | } | |
12122 | } | |
12123 | } | |
12124 | else | |
12125 | { | |
12126 | const char *newname; | |
12127 | segT new_seg; | |
12128 | ||
12129 | /* Switch to the right section. */ | |
12130 | seg = now_seg; | |
12131 | subseg = now_subseg; | |
12132 | switch (*args) | |
12133 | { | |
12134 | default: /* unused default case avoids warnings. */ | |
12135 | case 'L': | |
12136 | newname = RDATA_SECTION_NAME; | |
3e722fb5 | 12137 | if (g_switch_value >= 8) |
252b5132 RH |
12138 | newname = ".lit8"; |
12139 | break; | |
12140 | case 'F': | |
3e722fb5 | 12141 | newname = RDATA_SECTION_NAME; |
252b5132 RH |
12142 | break; |
12143 | case 'l': | |
9c2799c2 | 12144 | gas_assert (g_switch_value >= 4); |
252b5132 RH |
12145 | newname = ".lit4"; |
12146 | break; | |
12147 | } | |
12148 | new_seg = subseg_new (newname, (subsegT) 0); | |
f43abd2b | 12149 | if (IS_ELF) |
252b5132 RH |
12150 | bfd_set_section_flags (stdoutput, new_seg, |
12151 | (SEC_ALLOC | |
12152 | | SEC_LOAD | |
12153 | | SEC_READONLY | |
12154 | | SEC_DATA)); | |
12155 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
c41e87e3 | 12156 | if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0) |
252b5132 RH |
12157 | record_alignment (new_seg, 4); |
12158 | else | |
12159 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
12160 | if (seg == now_seg) | |
12161 | as_bad (_("Can't use floating point insn in this section")); | |
12162 | ||
df58fc94 RS |
12163 | /* Set the argument to the current address in the |
12164 | section. */ | |
12165 | offset_expr.X_op = O_symbol; | |
12166 | offset_expr.X_add_symbol = symbol_temp_new_now (); | |
12167 | offset_expr.X_add_number = 0; | |
12168 | ||
12169 | /* Put the floating point number into the section. */ | |
12170 | p = frag_more ((int) length); | |
12171 | memcpy (p, temp, length); | |
12172 | ||
12173 | /* Switch back to the original section. */ | |
12174 | subseg_set (seg, subseg); | |
12175 | } | |
12176 | } | |
12177 | continue; | |
12178 | ||
12179 | case 'i': /* 16-bit unsigned immediate. */ | |
12180 | case 'j': /* 16-bit signed immediate. */ | |
12181 | *imm_reloc = BFD_RELOC_LO16; | |
12182 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) | |
12183 | { | |
12184 | int more; | |
12185 | offsetT minval, maxval; | |
12186 | ||
12187 | more = (insn + 1 < past | |
12188 | && strcmp (insn->name, insn[1].name) == 0); | |
12189 | ||
12190 | /* If the expression was written as an unsigned number, | |
12191 | only treat it as signed if there are no more | |
12192 | alternatives. */ | |
12193 | if (more | |
12194 | && *args == 'j' | |
12195 | && sizeof (imm_expr.X_add_number) <= 4 | |
12196 | && imm_expr.X_op == O_constant | |
12197 | && imm_expr.X_add_number < 0 | |
12198 | && imm_expr.X_unsigned | |
12199 | && HAVE_64BIT_GPRS) | |
12200 | break; | |
12201 | ||
12202 | /* For compatibility with older assemblers, we accept | |
12203 | 0x8000-0xffff as signed 16-bit numbers when only | |
12204 | signed numbers are allowed. */ | |
12205 | if (*args == 'i') | |
12206 | minval = 0, maxval = 0xffff; | |
12207 | else if (more) | |
12208 | minval = -0x8000, maxval = 0x7fff; | |
12209 | else | |
12210 | minval = -0x8000, maxval = 0xffff; | |
12211 | ||
12212 | if (imm_expr.X_op != O_constant | |
12213 | || imm_expr.X_add_number < minval | |
12214 | || imm_expr.X_add_number > maxval) | |
12215 | { | |
12216 | if (more) | |
12217 | break; | |
12218 | if (imm_expr.X_op == O_constant | |
12219 | || imm_expr.X_op == O_big) | |
12220 | as_bad (_("Expression out of range")); | |
12221 | } | |
12222 | } | |
12223 | s = expr_end; | |
12224 | continue; | |
12225 | ||
12226 | case 'o': /* 16-bit offset. */ | |
12227 | offset_reloc[0] = BFD_RELOC_LO16; | |
12228 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
12229 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
12230 | ||
12231 | /* Check whether there is only a single bracketed expression | |
12232 | left. If so, it must be the base register and the | |
12233 | constant must be zero. */ | |
12234 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12235 | { | |
12236 | offset_expr.X_op = O_constant; | |
12237 | offset_expr.X_add_number = 0; | |
12238 | continue; | |
12239 | } | |
12240 | ||
12241 | /* If this value won't fit into a 16 bit offset, then go | |
12242 | find a macro that will generate the 32 bit offset | |
12243 | code pattern. */ | |
12244 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 | |
12245 | && (offset_expr.X_op != O_constant | |
12246 | || offset_expr.X_add_number >= 0x8000 | |
12247 | || offset_expr.X_add_number < -0x8000)) | |
12248 | break; | |
12249 | ||
12250 | s = expr_end; | |
12251 | continue; | |
12252 | ||
12253 | case 'p': /* PC-relative offset. */ | |
12254 | *offset_reloc = BFD_RELOC_16_PCREL_S2; | |
12255 | my_getExpression (&offset_expr, s); | |
12256 | s = expr_end; | |
12257 | continue; | |
12258 | ||
12259 | case 'u': /* Upper 16 bits. */ | |
12260 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 | |
12261 | && imm_expr.X_op == O_constant | |
12262 | && (imm_expr.X_add_number < 0 | |
12263 | || imm_expr.X_add_number >= 0x10000)) | |
12264 | as_bad (_("lui expression (%lu) not in range 0..65535"), | |
12265 | (unsigned long) imm_expr.X_add_number); | |
12266 | s = expr_end; | |
12267 | continue; | |
12268 | ||
12269 | case 'a': /* 26-bit address. */ | |
12270 | *offset_reloc = BFD_RELOC_MIPS_JMP; | |
12271 | my_getExpression (&offset_expr, s); | |
12272 | s = expr_end; | |
12273 | continue; | |
12274 | ||
12275 | case 'N': /* 3-bit branch condition code. */ | |
12276 | case 'M': /* 3-bit compare condition code. */ | |
12277 | rtype = RTYPE_CCC; | |
12278 | if (ip->insn_mo->pinfo & (FP_D | FP_S)) | |
12279 | rtype |= RTYPE_FCC; | |
12280 | if (!reg_lookup (&s, rtype, ®no)) | |
12281 | break; | |
12282 | if ((strcmp (str + strlen (str) - 3, ".ps") == 0 | |
12283 | || strcmp (str + strlen (str) - 5, "any2f") == 0 | |
12284 | || strcmp (str + strlen (str) - 5, "any2t") == 0) | |
12285 | && (regno & 1) != 0) | |
12286 | as_warn (_("Condition code register should be even for %s, " | |
12287 | "was %d"), | |
12288 | str, regno); | |
12289 | if ((strcmp (str + strlen (str) - 5, "any4f") == 0 | |
12290 | || strcmp (str + strlen (str) - 5, "any4t") == 0) | |
12291 | && (regno & 3) != 0) | |
12292 | as_warn (_("Condition code register should be 0 or 4 for %s, " | |
12293 | "was %d"), | |
12294 | str, regno); | |
12295 | if (*args == 'N') | |
12296 | INSERT_OPERAND (mips_opts.micromips, BCC, *ip, regno); | |
12297 | else | |
12298 | INSERT_OPERAND (mips_opts.micromips, CCC, *ip, regno); | |
12299 | continue; | |
12300 | ||
12301 | case 'H': | |
12302 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
12303 | s += 2; | |
12304 | if (ISDIGIT (*s)) | |
12305 | { | |
12306 | c = 0; | |
12307 | do | |
12308 | { | |
12309 | c *= 10; | |
12310 | c += *s - '0'; | |
12311 | ++s; | |
12312 | } | |
12313 | while (ISDIGIT (*s)); | |
12314 | } | |
12315 | else | |
12316 | c = 8; /* Invalid sel value. */ | |
12317 | ||
12318 | if (c > 7) | |
12319 | as_bad (_("Invalid coprocessor sub-selection value (0-7)")); | |
12320 | INSERT_OPERAND (mips_opts.micromips, SEL, *ip, c); | |
12321 | continue; | |
12322 | ||
12323 | case 'e': | |
12324 | gas_assert (!mips_opts.micromips); | |
12325 | /* Must be at least one digit. */ | |
12326 | my_getExpression (&imm_expr, s); | |
12327 | check_absolute_expr (ip, &imm_expr); | |
12328 | ||
12329 | if ((unsigned long) imm_expr.X_add_number | |
12330 | > (unsigned long) OP_MASK_VECBYTE) | |
12331 | { | |
12332 | as_bad (_("bad byte vector index (%ld)"), | |
12333 | (long) imm_expr.X_add_number); | |
12334 | imm_expr.X_add_number = 0; | |
12335 | } | |
12336 | ||
12337 | INSERT_OPERAND (0, VECBYTE, *ip, imm_expr.X_add_number); | |
12338 | imm_expr.X_op = O_absent; | |
12339 | s = expr_end; | |
12340 | continue; | |
12341 | ||
12342 | case '%': | |
12343 | gas_assert (!mips_opts.micromips); | |
12344 | my_getExpression (&imm_expr, s); | |
12345 | check_absolute_expr (ip, &imm_expr); | |
12346 | ||
12347 | if ((unsigned long) imm_expr.X_add_number | |
12348 | > (unsigned long) OP_MASK_VECALIGN) | |
12349 | { | |
12350 | as_bad (_("bad byte vector index (%ld)"), | |
12351 | (long) imm_expr.X_add_number); | |
12352 | imm_expr.X_add_number = 0; | |
12353 | } | |
12354 | ||
12355 | INSERT_OPERAND (0, VECALIGN, *ip, imm_expr.X_add_number); | |
12356 | imm_expr.X_op = O_absent; | |
12357 | s = expr_end; | |
12358 | continue; | |
12359 | ||
12360 | case 'm': /* Opcode extension character. */ | |
12361 | gas_assert (mips_opts.micromips); | |
12362 | c = *++args; | |
12363 | switch (c) | |
12364 | { | |
12365 | case 'r': | |
12366 | if (strncmp (s, "$pc", 3) == 0) | |
12367 | { | |
12368 | s += 3; | |
12369 | continue; | |
12370 | } | |
12371 | break; | |
12372 | ||
12373 | case 'a': | |
12374 | case 'b': | |
12375 | case 'c': | |
12376 | case 'd': | |
12377 | case 'e': | |
12378 | case 'f': | |
12379 | case 'g': | |
12380 | case 'h': | |
12381 | case 'i': | |
12382 | case 'j': | |
12383 | case 'l': | |
12384 | case 'm': | |
12385 | case 'n': | |
12386 | case 'p': | |
12387 | case 'q': | |
12388 | case 's': | |
12389 | case 't': | |
12390 | case 'x': | |
12391 | case 'y': | |
12392 | case 'z': | |
12393 | s_reset = s; | |
12394 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
12395 | if (regno == AT && mips_opts.at) | |
12396 | { | |
12397 | if (mips_opts.at == ATREG) | |
12398 | as_warn (_("Used $at without \".set noat\"")); | |
12399 | else | |
12400 | as_warn (_("Used $%u with \".set at=$%u\""), | |
12401 | regno, mips_opts.at); | |
12402 | } | |
12403 | if (!ok) | |
12404 | { | |
12405 | if (c == 'c') | |
12406 | { | |
12407 | gas_assert (args[1] == ','); | |
12408 | regno = lastregno; | |
12409 | ++args; | |
12410 | } | |
12411 | else if (c == 't') | |
12412 | { | |
12413 | gas_assert (args[1] == ','); | |
12414 | ++args; | |
12415 | continue; /* Nothing to do. */ | |
12416 | } | |
12417 | else | |
12418 | break; | |
12419 | } | |
12420 | ||
12421 | if (c == 'j' && !strncmp (ip->insn_mo->name, "jalr", 4)) | |
12422 | { | |
12423 | if (regno == lastregno) | |
12424 | { | |
12425 | insn_error | |
12426 | = _("Source and destination must be different"); | |
12427 | continue; | |
12428 | } | |
12429 | if (regno == 31 && lastregno == 0xffffffff) | |
12430 | { | |
12431 | insn_error | |
12432 | = _("A destination register must be supplied"); | |
12433 | continue; | |
12434 | } | |
12435 | } | |
12436 | ||
12437 | if (*s == ' ') | |
12438 | ++s; | |
12439 | if (args[1] != *s) | |
12440 | { | |
12441 | if (c == 'e') | |
12442 | { | |
12443 | gas_assert (args[1] == ','); | |
12444 | regno = lastregno; | |
12445 | s = s_reset; | |
12446 | ++args; | |
12447 | } | |
12448 | else if (c == 't') | |
12449 | { | |
12450 | gas_assert (args[1] == ','); | |
12451 | s = s_reset; | |
12452 | ++args; | |
12453 | continue; /* Nothing to do. */ | |
12454 | } | |
12455 | } | |
12456 | ||
12457 | /* Make sure regno is the same as lastregno. */ | |
12458 | if (c == 't' && regno != lastregno) | |
12459 | break; | |
12460 | ||
12461 | /* Make sure regno is the same as destregno. */ | |
12462 | if (c == 'x' && regno != destregno) | |
12463 | break; | |
12464 | ||
12465 | /* We need to save regno, before regno maps to the | |
12466 | microMIPS register encoding. */ | |
12467 | lastregno = regno; | |
12468 | ||
12469 | if (c == 'f') | |
12470 | destregno = regno; | |
12471 | ||
12472 | switch (c) | |
12473 | { | |
12474 | case 'a': | |
12475 | if (regno != GP) | |
12476 | regno = ILLEGAL_REG; | |
12477 | break; | |
12478 | ||
12479 | case 'b': | |
12480 | regno = mips32_to_micromips_reg_b_map[regno]; | |
12481 | break; | |
12482 | ||
12483 | case 'c': | |
12484 | regno = mips32_to_micromips_reg_c_map[regno]; | |
12485 | break; | |
12486 | ||
12487 | case 'd': | |
12488 | regno = mips32_to_micromips_reg_d_map[regno]; | |
12489 | break; | |
12490 | ||
12491 | case 'e': | |
12492 | regno = mips32_to_micromips_reg_e_map[regno]; | |
12493 | break; | |
12494 | ||
12495 | case 'f': | |
12496 | regno = mips32_to_micromips_reg_f_map[regno]; | |
12497 | break; | |
12498 | ||
12499 | case 'g': | |
12500 | regno = mips32_to_micromips_reg_g_map[regno]; | |
12501 | break; | |
12502 | ||
12503 | case 'h': | |
12504 | regno = mips32_to_micromips_reg_h_map[regno]; | |
12505 | break; | |
12506 | ||
12507 | case 'i': | |
12508 | switch (EXTRACT_OPERAND (1, MI, *ip)) | |
12509 | { | |
12510 | case 4: | |
12511 | if (regno == 21) | |
12512 | regno = 3; | |
12513 | else if (regno == 22) | |
12514 | regno = 4; | |
12515 | else if (regno == 5) | |
12516 | regno = 5; | |
12517 | else if (regno == 6) | |
12518 | regno = 6; | |
12519 | else if (regno == 7) | |
12520 | regno = 7; | |
12521 | else | |
12522 | regno = ILLEGAL_REG; | |
12523 | break; | |
12524 | ||
12525 | case 5: | |
12526 | if (regno == 6) | |
12527 | regno = 0; | |
12528 | else if (regno == 7) | |
12529 | regno = 1; | |
12530 | else | |
12531 | regno = ILLEGAL_REG; | |
12532 | break; | |
12533 | ||
12534 | case 6: | |
12535 | if (regno == 7) | |
12536 | regno = 2; | |
12537 | else | |
12538 | regno = ILLEGAL_REG; | |
12539 | break; | |
12540 | ||
12541 | default: | |
12542 | regno = ILLEGAL_REG; | |
12543 | break; | |
12544 | } | |
12545 | break; | |
12546 | ||
12547 | case 'l': | |
12548 | regno = mips32_to_micromips_reg_l_map[regno]; | |
12549 | break; | |
12550 | ||
12551 | case 'm': | |
12552 | regno = mips32_to_micromips_reg_m_map[regno]; | |
12553 | break; | |
12554 | ||
12555 | case 'n': | |
12556 | regno = mips32_to_micromips_reg_n_map[regno]; | |
12557 | break; | |
12558 | ||
12559 | case 'q': | |
12560 | regno = mips32_to_micromips_reg_q_map[regno]; | |
12561 | break; | |
12562 | ||
12563 | case 's': | |
12564 | if (regno != SP) | |
12565 | regno = ILLEGAL_REG; | |
12566 | break; | |
12567 | ||
12568 | case 'y': | |
12569 | if (regno != 31) | |
12570 | regno = ILLEGAL_REG; | |
12571 | break; | |
12572 | ||
12573 | case 'z': | |
12574 | if (regno != ZERO) | |
12575 | regno = ILLEGAL_REG; | |
12576 | break; | |
12577 | ||
12578 | case 'j': /* Do nothing. */ | |
12579 | case 'p': | |
12580 | case 't': | |
12581 | case 'x': | |
12582 | break; | |
12583 | ||
12584 | default: | |
12585 | internalError (); | |
12586 | } | |
12587 | ||
12588 | if (regno == ILLEGAL_REG) | |
12589 | break; | |
12590 | ||
12591 | switch (c) | |
12592 | { | |
12593 | case 'b': | |
12594 | INSERT_OPERAND (1, MB, *ip, regno); | |
12595 | break; | |
12596 | ||
12597 | case 'c': | |
12598 | INSERT_OPERAND (1, MC, *ip, regno); | |
12599 | break; | |
12600 | ||
12601 | case 'd': | |
12602 | INSERT_OPERAND (1, MD, *ip, regno); | |
12603 | break; | |
12604 | ||
12605 | case 'e': | |
12606 | INSERT_OPERAND (1, ME, *ip, regno); | |
12607 | break; | |
12608 | ||
12609 | case 'f': | |
12610 | INSERT_OPERAND (1, MF, *ip, regno); | |
12611 | break; | |
12612 | ||
12613 | case 'g': | |
12614 | INSERT_OPERAND (1, MG, *ip, regno); | |
12615 | break; | |
12616 | ||
12617 | case 'h': | |
12618 | INSERT_OPERAND (1, MH, *ip, regno); | |
12619 | break; | |
12620 | ||
12621 | case 'i': | |
12622 | INSERT_OPERAND (1, MI, *ip, regno); | |
12623 | break; | |
12624 | ||
12625 | case 'j': | |
12626 | INSERT_OPERAND (1, MJ, *ip, regno); | |
12627 | break; | |
12628 | ||
12629 | case 'l': | |
12630 | INSERT_OPERAND (1, ML, *ip, regno); | |
12631 | break; | |
12632 | ||
12633 | case 'm': | |
12634 | INSERT_OPERAND (1, MM, *ip, regno); | |
12635 | break; | |
12636 | ||
12637 | case 'n': | |
12638 | INSERT_OPERAND (1, MN, *ip, regno); | |
12639 | break; | |
12640 | ||
12641 | case 'p': | |
12642 | INSERT_OPERAND (1, MP, *ip, regno); | |
12643 | break; | |
12644 | ||
12645 | case 'q': | |
12646 | INSERT_OPERAND (1, MQ, *ip, regno); | |
12647 | break; | |
12648 | ||
12649 | case 'a': /* Do nothing. */ | |
12650 | case 's': /* Do nothing. */ | |
12651 | case 't': /* Do nothing. */ | |
12652 | case 'x': /* Do nothing. */ | |
12653 | case 'y': /* Do nothing. */ | |
12654 | case 'z': /* Do nothing. */ | |
12655 | break; | |
12656 | ||
12657 | default: | |
12658 | internalError (); | |
12659 | } | |
12660 | continue; | |
12661 | ||
12662 | case 'A': | |
12663 | { | |
12664 | bfd_reloc_code_real_type r[3]; | |
12665 | expressionS ep; | |
12666 | int imm; | |
12667 | ||
12668 | /* Check whether there is only a single bracketed | |
12669 | expression left. If so, it must be the base register | |
12670 | and the constant must be zero. */ | |
12671 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12672 | { | |
12673 | INSERT_OPERAND (1, IMMA, *ip, 0); | |
12674 | continue; | |
12675 | } | |
12676 | ||
12677 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12678 | || !expr_const_in_range (&ep, -64, 64, 2)) | |
12679 | break; | |
12680 | ||
12681 | imm = ep.X_add_number >> 2; | |
12682 | INSERT_OPERAND (1, IMMA, *ip, imm); | |
12683 | } | |
12684 | s = expr_end; | |
12685 | continue; | |
12686 | ||
12687 | case 'B': | |
12688 | { | |
12689 | bfd_reloc_code_real_type r[3]; | |
12690 | expressionS ep; | |
12691 | int imm; | |
12692 | ||
12693 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12694 | || ep.X_op != O_constant) | |
12695 | break; | |
12696 | ||
12697 | for (imm = 0; imm < 8; imm++) | |
12698 | if (micromips_imm_b_map[imm] == ep.X_add_number) | |
12699 | break; | |
12700 | if (imm >= 8) | |
12701 | break; | |
12702 | ||
12703 | INSERT_OPERAND (1, IMMB, *ip, imm); | |
12704 | } | |
12705 | s = expr_end; | |
12706 | continue; | |
12707 | ||
12708 | case 'C': | |
12709 | { | |
12710 | bfd_reloc_code_real_type r[3]; | |
12711 | expressionS ep; | |
12712 | int imm; | |
12713 | ||
12714 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12715 | || ep.X_op != O_constant) | |
12716 | break; | |
12717 | ||
12718 | for (imm = 0; imm < 16; imm++) | |
12719 | if (micromips_imm_c_map[imm] == ep.X_add_number) | |
12720 | break; | |
12721 | if (imm >= 16) | |
12722 | break; | |
12723 | ||
12724 | INSERT_OPERAND (1, IMMC, *ip, imm); | |
12725 | } | |
12726 | s = expr_end; | |
12727 | continue; | |
12728 | ||
12729 | case 'D': /* pc relative offset */ | |
12730 | case 'E': /* pc relative offset */ | |
12731 | my_getExpression (&offset_expr, s); | |
12732 | if (offset_expr.X_op == O_register) | |
12733 | break; | |
12734 | ||
40209cad MR |
12735 | if (!forced_insn_length) |
12736 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; | |
12737 | else if (c == 'D') | |
12738 | *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1; | |
12739 | else | |
12740 | *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1; | |
df58fc94 RS |
12741 | s = expr_end; |
12742 | continue; | |
12743 | ||
12744 | case 'F': | |
12745 | { | |
12746 | bfd_reloc_code_real_type r[3]; | |
12747 | expressionS ep; | |
12748 | int imm; | |
12749 | ||
12750 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12751 | || !expr_const_in_range (&ep, 0, 16, 0)) | |
12752 | break; | |
12753 | ||
12754 | imm = ep.X_add_number; | |
12755 | INSERT_OPERAND (1, IMMF, *ip, imm); | |
12756 | } | |
12757 | s = expr_end; | |
12758 | continue; | |
12759 | ||
12760 | case 'G': | |
12761 | { | |
12762 | bfd_reloc_code_real_type r[3]; | |
12763 | expressionS ep; | |
12764 | int imm; | |
12765 | ||
12766 | /* Check whether there is only a single bracketed | |
12767 | expression left. If so, it must be the base register | |
12768 | and the constant must be zero. */ | |
12769 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12770 | { | |
12771 | INSERT_OPERAND (1, IMMG, *ip, 0); | |
12772 | continue; | |
12773 | } | |
12774 | ||
12775 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12776 | || !expr_const_in_range (&ep, -1, 15, 0)) | |
12777 | break; | |
12778 | ||
12779 | imm = ep.X_add_number & 15; | |
12780 | INSERT_OPERAND (1, IMMG, *ip, imm); | |
12781 | } | |
12782 | s = expr_end; | |
12783 | continue; | |
12784 | ||
12785 | case 'H': | |
12786 | { | |
12787 | bfd_reloc_code_real_type r[3]; | |
12788 | expressionS ep; | |
12789 | int imm; | |
12790 | ||
12791 | /* Check whether there is only a single bracketed | |
12792 | expression left. If so, it must be the base register | |
12793 | and the constant must be zero. */ | |
12794 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12795 | { | |
12796 | INSERT_OPERAND (1, IMMH, *ip, 0); | |
12797 | continue; | |
12798 | } | |
12799 | ||
12800 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12801 | || !expr_const_in_range (&ep, 0, 16, 1)) | |
12802 | break; | |
12803 | ||
12804 | imm = ep.X_add_number >> 1; | |
12805 | INSERT_OPERAND (1, IMMH, *ip, imm); | |
12806 | } | |
12807 | s = expr_end; | |
12808 | continue; | |
12809 | ||
12810 | case 'I': | |
12811 | { | |
12812 | bfd_reloc_code_real_type r[3]; | |
12813 | expressionS ep; | |
12814 | int imm; | |
12815 | ||
12816 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12817 | || !expr_const_in_range (&ep, -1, 127, 0)) | |
12818 | break; | |
12819 | ||
12820 | imm = ep.X_add_number & 127; | |
12821 | INSERT_OPERAND (1, IMMI, *ip, imm); | |
12822 | } | |
12823 | s = expr_end; | |
12824 | continue; | |
12825 | ||
12826 | case 'J': | |
12827 | { | |
12828 | bfd_reloc_code_real_type r[3]; | |
12829 | expressionS ep; | |
12830 | int imm; | |
12831 | ||
12832 | /* Check whether there is only a single bracketed | |
12833 | expression left. If so, it must be the base register | |
12834 | and the constant must be zero. */ | |
12835 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12836 | { | |
12837 | INSERT_OPERAND (1, IMMJ, *ip, 0); | |
12838 | continue; | |
12839 | } | |
12840 | ||
12841 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12842 | || !expr_const_in_range (&ep, 0, 16, 2)) | |
12843 | break; | |
12844 | ||
12845 | imm = ep.X_add_number >> 2; | |
12846 | INSERT_OPERAND (1, IMMJ, *ip, imm); | |
12847 | } | |
12848 | s = expr_end; | |
12849 | continue; | |
12850 | ||
12851 | case 'L': | |
12852 | { | |
12853 | bfd_reloc_code_real_type r[3]; | |
12854 | expressionS ep; | |
12855 | int imm; | |
12856 | ||
12857 | /* Check whether there is only a single bracketed | |
12858 | expression left. If so, it must be the base register | |
12859 | and the constant must be zero. */ | |
12860 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12861 | { | |
12862 | INSERT_OPERAND (1, IMML, *ip, 0); | |
12863 | continue; | |
12864 | } | |
12865 | ||
12866 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12867 | || !expr_const_in_range (&ep, 0, 16, 0)) | |
12868 | break; | |
12869 | ||
12870 | imm = ep.X_add_number; | |
12871 | INSERT_OPERAND (1, IMML, *ip, imm); | |
12872 | } | |
12873 | s = expr_end; | |
12874 | continue; | |
12875 | ||
12876 | case 'M': | |
12877 | { | |
12878 | bfd_reloc_code_real_type r[3]; | |
12879 | expressionS ep; | |
12880 | int imm; | |
12881 | ||
12882 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12883 | || !expr_const_in_range (&ep, 1, 9, 0)) | |
12884 | break; | |
12885 | ||
12886 | imm = ep.X_add_number & 7; | |
12887 | INSERT_OPERAND (1, IMMM, *ip, imm); | |
12888 | } | |
12889 | s = expr_end; | |
12890 | continue; | |
12891 | ||
12892 | case 'N': /* Register list for lwm and swm. */ | |
12893 | { | |
12894 | /* A comma-separated list of registers and/or | |
12895 | dash-separated contiguous ranges including | |
12896 | both ra and a set of one or more registers | |
12897 | starting at s0 up to s3 which have to be | |
12898 | consecutive, e.g.: | |
12899 | ||
12900 | s0, ra | |
12901 | s0, s1, ra, s2, s3 | |
12902 | s0-s2, ra | |
12903 | ||
12904 | and any permutations of these. */ | |
12905 | unsigned int reglist; | |
12906 | int imm; | |
12907 | ||
12908 | if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list)) | |
12909 | break; | |
12910 | ||
12911 | if ((reglist & 0xfff1ffff) != 0x80010000) | |
12912 | break; | |
12913 | ||
12914 | reglist = (reglist >> 17) & 7; | |
12915 | reglist += 1; | |
12916 | if ((reglist & -reglist) != reglist) | |
12917 | break; | |
252b5132 | 12918 | |
df58fc94 RS |
12919 | imm = ffs (reglist) - 1; |
12920 | INSERT_OPERAND (1, IMMN, *ip, imm); | |
12921 | } | |
12922 | continue; | |
252b5132 | 12923 | |
df58fc94 RS |
12924 | case 'O': /* sdbbp 4-bit code. */ |
12925 | { | |
12926 | bfd_reloc_code_real_type r[3]; | |
12927 | expressionS ep; | |
12928 | int imm; | |
12929 | ||
12930 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12931 | || !expr_const_in_range (&ep, 0, 16, 0)) | |
12932 | break; | |
12933 | ||
12934 | imm = ep.X_add_number; | |
12935 | INSERT_OPERAND (1, IMMO, *ip, imm); | |
252b5132 | 12936 | } |
df58fc94 RS |
12937 | s = expr_end; |
12938 | continue; | |
252b5132 | 12939 | |
df58fc94 RS |
12940 | case 'P': |
12941 | { | |
12942 | bfd_reloc_code_real_type r[3]; | |
12943 | expressionS ep; | |
12944 | int imm; | |
5e0116d5 | 12945 | |
df58fc94 RS |
12946 | if (my_getSmallExpression (&ep, r, s) > 0 |
12947 | || !expr_const_in_range (&ep, 0, 32, 2)) | |
12948 | break; | |
5e0116d5 | 12949 | |
df58fc94 RS |
12950 | imm = ep.X_add_number >> 2; |
12951 | INSERT_OPERAND (1, IMMP, *ip, imm); | |
12952 | } | |
12953 | s = expr_end; | |
12954 | continue; | |
5e0116d5 | 12955 | |
df58fc94 RS |
12956 | case 'Q': |
12957 | { | |
12958 | bfd_reloc_code_real_type r[3]; | |
12959 | expressionS ep; | |
12960 | int imm; | |
5e0116d5 | 12961 | |
df58fc94 RS |
12962 | if (my_getSmallExpression (&ep, r, s) > 0 |
12963 | || !expr_const_in_range (&ep, -0x400000, 0x400000, 2)) | |
12964 | break; | |
252b5132 | 12965 | |
df58fc94 RS |
12966 | imm = ep.X_add_number >> 2; |
12967 | INSERT_OPERAND (1, IMMQ, *ip, imm); | |
12968 | } | |
12969 | s = expr_end; | |
12970 | continue; | |
4614d845 | 12971 | |
df58fc94 RS |
12972 | case 'U': |
12973 | { | |
12974 | bfd_reloc_code_real_type r[3]; | |
12975 | expressionS ep; | |
12976 | int imm; | |
12977 | ||
12978 | /* Check whether there is only a single bracketed | |
12979 | expression left. If so, it must be the base register | |
12980 | and the constant must be zero. */ | |
12981 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12982 | { | |
12983 | INSERT_OPERAND (1, IMMU, *ip, 0); | |
12984 | continue; | |
12985 | } | |
12986 | ||
12987 | if (my_getSmallExpression (&ep, r, s) > 0 | |
12988 | || !expr_const_in_range (&ep, 0, 32, 2)) | |
12989 | break; | |
12990 | ||
12991 | imm = ep.X_add_number >> 2; | |
12992 | INSERT_OPERAND (1, IMMU, *ip, imm); | |
12993 | } | |
12994 | s = expr_end; | |
5e0116d5 | 12995 | continue; |
252b5132 | 12996 | |
df58fc94 RS |
12997 | case 'W': |
12998 | { | |
12999 | bfd_reloc_code_real_type r[3]; | |
13000 | expressionS ep; | |
13001 | int imm; | |
252b5132 | 13002 | |
df58fc94 RS |
13003 | if (my_getSmallExpression (&ep, r, s) > 0 |
13004 | || !expr_const_in_range (&ep, 0, 64, 2)) | |
13005 | break; | |
252b5132 | 13006 | |
df58fc94 RS |
13007 | imm = ep.X_add_number >> 2; |
13008 | INSERT_OPERAND (1, IMMW, *ip, imm); | |
13009 | } | |
13010 | s = expr_end; | |
13011 | continue; | |
252b5132 | 13012 | |
df58fc94 RS |
13013 | case 'X': |
13014 | { | |
13015 | bfd_reloc_code_real_type r[3]; | |
13016 | expressionS ep; | |
13017 | int imm; | |
252b5132 | 13018 | |
df58fc94 RS |
13019 | if (my_getSmallExpression (&ep, r, s) > 0 |
13020 | || !expr_const_in_range (&ep, -8, 8, 0)) | |
13021 | break; | |
252b5132 | 13022 | |
df58fc94 RS |
13023 | imm = ep.X_add_number; |
13024 | INSERT_OPERAND (1, IMMX, *ip, imm); | |
13025 | } | |
13026 | s = expr_end; | |
13027 | continue; | |
252b5132 | 13028 | |
df58fc94 RS |
13029 | case 'Y': |
13030 | { | |
13031 | bfd_reloc_code_real_type r[3]; | |
13032 | expressionS ep; | |
13033 | int imm; | |
156c2f8b | 13034 | |
df58fc94 RS |
13035 | if (my_getSmallExpression (&ep, r, s) > 0 |
13036 | || expr_const_in_range (&ep, -2, 2, 2) | |
13037 | || !expr_const_in_range (&ep, -258, 258, 2)) | |
13038 | break; | |
156c2f8b | 13039 | |
df58fc94 RS |
13040 | imm = ep.X_add_number >> 2; |
13041 | imm = ((imm >> 1) & ~0xff) | (imm & 0xff); | |
13042 | INSERT_OPERAND (1, IMMY, *ip, imm); | |
13043 | } | |
13044 | s = expr_end; | |
13045 | continue; | |
60b63b72 | 13046 | |
df58fc94 RS |
13047 | case 'Z': |
13048 | { | |
13049 | bfd_reloc_code_real_type r[3]; | |
13050 | expressionS ep; | |
13051 | ||
13052 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13053 | || !expr_const_in_range (&ep, 0, 1, 0)) | |
13054 | break; | |
13055 | } | |
13056 | s = expr_end; | |
13057 | continue; | |
13058 | ||
13059 | default: | |
13060 | as_bad (_("Internal error: bad microMIPS opcode " | |
13061 | "(unknown extension operand type `m%c'): %s %s"), | |
13062 | *args, insn->name, insn->args); | |
13063 | /* Further processing is fruitless. */ | |
13064 | return; | |
60b63b72 | 13065 | } |
df58fc94 | 13066 | break; |
60b63b72 | 13067 | |
df58fc94 RS |
13068 | case 'n': /* Register list for 32-bit lwm and swm. */ |
13069 | gas_assert (mips_opts.micromips); | |
13070 | { | |
13071 | /* A comma-separated list of registers and/or | |
13072 | dash-separated contiguous ranges including | |
13073 | at least one of ra and a set of one or more | |
13074 | registers starting at s0 up to s7 and then | |
13075 | s8 which have to be consecutive, e.g.: | |
13076 | ||
13077 | ra | |
13078 | s0 | |
13079 | ra, s0, s1, s2 | |
13080 | s0-s8 | |
13081 | s0-s5, ra | |
13082 | ||
13083 | and any permutations of these. */ | |
13084 | unsigned int reglist; | |
13085 | int imm; | |
13086 | int ra; | |
13087 | ||
13088 | if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list)) | |
13089 | break; | |
13090 | ||
13091 | if ((reglist & 0x3f00ffff) != 0) | |
13092 | break; | |
13093 | ||
13094 | ra = (reglist >> 27) & 0x10; | |
13095 | reglist = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff); | |
13096 | reglist += 1; | |
13097 | if ((reglist & -reglist) != reglist) | |
13098 | break; | |
13099 | ||
13100 | imm = (ffs (reglist) - 1) | ra; | |
13101 | INSERT_OPERAND (1, RT, *ip, imm); | |
13102 | imm_expr.X_op = O_absent; | |
13103 | } | |
60b63b72 RS |
13104 | continue; |
13105 | ||
df58fc94 RS |
13106 | case '|': /* 4-bit trap code. */ |
13107 | gas_assert (mips_opts.micromips); | |
60b63b72 RS |
13108 | my_getExpression (&imm_expr, s); |
13109 | check_absolute_expr (ip, &imm_expr); | |
60b63b72 | 13110 | if ((unsigned long) imm_expr.X_add_number |
df58fc94 RS |
13111 | > MICROMIPSOP_MASK_TRAP) |
13112 | as_bad (_("Trap code (%lu) for %s not in 0..15 range"), | |
13113 | (unsigned long) imm_expr.X_add_number, | |
13114 | ip->insn_mo->name); | |
13115 | INSERT_OPERAND (1, TRAP, *ip, imm_expr.X_add_number); | |
60b63b72 RS |
13116 | imm_expr.X_op = O_absent; |
13117 | s = expr_end; | |
13118 | continue; | |
13119 | ||
252b5132 | 13120 | default: |
f71d0d44 | 13121 | as_bad (_("Bad char = '%c'\n"), *args); |
252b5132 RH |
13122 | internalError (); |
13123 | } | |
13124 | break; | |
13125 | } | |
13126 | /* Args don't match. */ | |
df58fc94 RS |
13127 | s = argsStart; |
13128 | insn_error = _("Illegal operands"); | |
13129 | if (insn + 1 < past && !strcmp (insn->name, insn[1].name)) | |
252b5132 RH |
13130 | { |
13131 | ++insn; | |
252b5132 RH |
13132 | continue; |
13133 | } | |
df58fc94 RS |
13134 | else if (wrong_delay_slot_insns && need_delay_slot_ok) |
13135 | { | |
13136 | gas_assert (firstinsn); | |
13137 | need_delay_slot_ok = FALSE; | |
13138 | past = insn + 1; | |
13139 | insn = firstinsn; | |
13140 | continue; | |
13141 | } | |
252b5132 RH |
13142 | return; |
13143 | } | |
13144 | } | |
13145 | ||
0499d65b TS |
13146 | #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); } |
13147 | ||
252b5132 RH |
13148 | /* This routine assembles an instruction into its binary format when |
13149 | assembling for the mips16. As a side effect, it sets one of the | |
df58fc94 RS |
13150 | global variables imm_reloc or offset_reloc to the type of relocation |
13151 | to do if one of the operands is an address expression. It also sets | |
13152 | forced_insn_length to the resulting instruction size in bytes if the | |
13153 | user explicitly requested a small or extended instruction. */ | |
252b5132 RH |
13154 | |
13155 | static void | |
17a2f251 | 13156 | mips16_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
13157 | { |
13158 | char *s; | |
13159 | const char *args; | |
13160 | struct mips_opcode *insn; | |
13161 | char *argsstart; | |
13162 | unsigned int regno; | |
13163 | unsigned int lastregno = 0; | |
13164 | char *s_reset; | |
d6f16593 | 13165 | size_t i; |
252b5132 RH |
13166 | |
13167 | insn_error = NULL; | |
13168 | ||
df58fc94 | 13169 | forced_insn_length = 0; |
252b5132 | 13170 | |
3882b010 | 13171 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
13172 | ; |
13173 | switch (*s) | |
13174 | { | |
13175 | case '\0': | |
13176 | break; | |
13177 | ||
13178 | case ' ': | |
13179 | *s++ = '\0'; | |
13180 | break; | |
13181 | ||
13182 | case '.': | |
13183 | if (s[1] == 't' && s[2] == ' ') | |
13184 | { | |
13185 | *s = '\0'; | |
df58fc94 | 13186 | forced_insn_length = 2; |
252b5132 RH |
13187 | s += 3; |
13188 | break; | |
13189 | } | |
13190 | else if (s[1] == 'e' && s[2] == ' ') | |
13191 | { | |
13192 | *s = '\0'; | |
df58fc94 | 13193 | forced_insn_length = 4; |
252b5132 RH |
13194 | s += 3; |
13195 | break; | |
13196 | } | |
13197 | /* Fall through. */ | |
13198 | default: | |
13199 | insn_error = _("unknown opcode"); | |
13200 | return; | |
13201 | } | |
13202 | ||
df58fc94 RS |
13203 | if (mips_opts.noautoextend && !forced_insn_length) |
13204 | forced_insn_length = 2; | |
252b5132 RH |
13205 | |
13206 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
13207 | { | |
13208 | insn_error = _("unrecognized opcode"); | |
13209 | return; | |
13210 | } | |
13211 | ||
13212 | argsstart = s; | |
13213 | for (;;) | |
13214 | { | |
9b3f89ee TS |
13215 | bfd_boolean ok; |
13216 | ||
9c2799c2 | 13217 | gas_assert (strcmp (insn->name, str) == 0); |
252b5132 | 13218 | |
037b32b9 | 13219 | ok = is_opcode_valid_16 (insn); |
9b3f89ee TS |
13220 | if (! ok) |
13221 | { | |
13222 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] | |
13223 | && strcmp (insn->name, insn[1].name) == 0) | |
13224 | { | |
13225 | ++insn; | |
13226 | continue; | |
13227 | } | |
13228 | else | |
13229 | { | |
13230 | if (!insn_error) | |
13231 | { | |
13232 | static char buf[100]; | |
13233 | sprintf (buf, | |
13234 | _("opcode not supported on this processor: %s (%s)"), | |
13235 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
13236 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
13237 | insn_error = buf; | |
13238 | } | |
13239 | return; | |
13240 | } | |
13241 | } | |
13242 | ||
1e915849 | 13243 | create_insn (ip, insn); |
252b5132 | 13244 | imm_expr.X_op = O_absent; |
f6688943 TS |
13245 | imm_reloc[0] = BFD_RELOC_UNUSED; |
13246 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
13247 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
5f74bc13 | 13248 | imm2_expr.X_op = O_absent; |
252b5132 | 13249 | offset_expr.X_op = O_absent; |
f6688943 TS |
13250 | offset_reloc[0] = BFD_RELOC_UNUSED; |
13251 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
13252 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
13253 | for (args = insn->args; 1; ++args) |
13254 | { | |
13255 | int c; | |
13256 | ||
13257 | if (*s == ' ') | |
13258 | ++s; | |
13259 | ||
13260 | /* In this switch statement we call break if we did not find | |
13261 | a match, continue if we did find a match, or return if we | |
13262 | are done. */ | |
13263 | ||
13264 | c = *args; | |
13265 | switch (c) | |
13266 | { | |
13267 | case '\0': | |
13268 | if (*s == '\0') | |
13269 | { | |
13270 | /* Stuff the immediate value in now, if we can. */ | |
13271 | if (imm_expr.X_op == O_constant | |
f6688943 | 13272 | && *imm_reloc > BFD_RELOC_UNUSED |
738e5348 RS |
13273 | && *imm_reloc != BFD_RELOC_MIPS16_GOT16 |
13274 | && *imm_reloc != BFD_RELOC_MIPS16_CALL16 | |
252b5132 RH |
13275 | && insn->pinfo != INSN_MACRO) |
13276 | { | |
d6f16593 MR |
13277 | valueT tmp; |
13278 | ||
13279 | switch (*offset_reloc) | |
13280 | { | |
13281 | case BFD_RELOC_MIPS16_HI16_S: | |
13282 | tmp = (imm_expr.X_add_number + 0x8000) >> 16; | |
13283 | break; | |
13284 | ||
13285 | case BFD_RELOC_MIPS16_HI16: | |
13286 | tmp = imm_expr.X_add_number >> 16; | |
13287 | break; | |
13288 | ||
13289 | case BFD_RELOC_MIPS16_LO16: | |
13290 | tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff) | |
13291 | - 0x8000; | |
13292 | break; | |
13293 | ||
13294 | case BFD_RELOC_UNUSED: | |
13295 | tmp = imm_expr.X_add_number; | |
13296 | break; | |
13297 | ||
13298 | default: | |
13299 | internalError (); | |
13300 | } | |
13301 | *offset_reloc = BFD_RELOC_UNUSED; | |
13302 | ||
c4e7957c | 13303 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
df58fc94 RS |
13304 | tmp, TRUE, forced_insn_length == 2, |
13305 | forced_insn_length == 4, &ip->insn_opcode, | |
252b5132 RH |
13306 | &ip->use_extend, &ip->extend); |
13307 | imm_expr.X_op = O_absent; | |
f6688943 | 13308 | *imm_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
13309 | } |
13310 | ||
13311 | return; | |
13312 | } | |
13313 | break; | |
13314 | ||
13315 | case ',': | |
13316 | if (*s++ == c) | |
13317 | continue; | |
13318 | s--; | |
13319 | switch (*++args) | |
13320 | { | |
13321 | case 'v': | |
bf12938e | 13322 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 RH |
13323 | continue; |
13324 | case 'w': | |
bf12938e | 13325 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
13326 | continue; |
13327 | } | |
13328 | break; | |
13329 | ||
13330 | case '(': | |
13331 | case ')': | |
13332 | if (*s++ == c) | |
13333 | continue; | |
13334 | break; | |
13335 | ||
13336 | case 'v': | |
13337 | case 'w': | |
13338 | if (s[0] != '$') | |
13339 | { | |
13340 | if (c == 'v') | |
bf12938e | 13341 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 | 13342 | else |
bf12938e | 13343 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
13344 | ++args; |
13345 | continue; | |
13346 | } | |
13347 | /* Fall through. */ | |
13348 | case 'x': | |
13349 | case 'y': | |
13350 | case 'z': | |
13351 | case 'Z': | |
13352 | case '0': | |
13353 | case 'S': | |
13354 | case 'R': | |
13355 | case 'X': | |
13356 | case 'Y': | |
707bfff6 TS |
13357 | s_reset = s; |
13358 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) | |
252b5132 | 13359 | { |
707bfff6 | 13360 | if (c == 'v' || c == 'w') |
85b51719 | 13361 | { |
707bfff6 | 13362 | if (c == 'v') |
a9e24354 | 13363 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
707bfff6 | 13364 | else |
a9e24354 | 13365 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
707bfff6 TS |
13366 | ++args; |
13367 | continue; | |
85b51719 | 13368 | } |
707bfff6 | 13369 | break; |
252b5132 RH |
13370 | } |
13371 | ||
13372 | if (*s == ' ') | |
13373 | ++s; | |
13374 | if (args[1] != *s) | |
13375 | { | |
13376 | if (c == 'v' || c == 'w') | |
13377 | { | |
13378 | regno = mips16_to_32_reg_map[lastregno]; | |
13379 | s = s_reset; | |
f9419b05 | 13380 | ++args; |
252b5132 RH |
13381 | } |
13382 | } | |
13383 | ||
13384 | switch (c) | |
13385 | { | |
13386 | case 'x': | |
13387 | case 'y': | |
13388 | case 'z': | |
13389 | case 'v': | |
13390 | case 'w': | |
13391 | case 'Z': | |
13392 | regno = mips32_to_16_reg_map[regno]; | |
13393 | break; | |
13394 | ||
13395 | case '0': | |
13396 | if (regno != 0) | |
13397 | regno = ILLEGAL_REG; | |
13398 | break; | |
13399 | ||
13400 | case 'S': | |
13401 | if (regno != SP) | |
13402 | regno = ILLEGAL_REG; | |
13403 | break; | |
13404 | ||
13405 | case 'R': | |
13406 | if (regno != RA) | |
13407 | regno = ILLEGAL_REG; | |
13408 | break; | |
13409 | ||
13410 | case 'X': | |
13411 | case 'Y': | |
741fe287 MR |
13412 | if (regno == AT && mips_opts.at) |
13413 | { | |
13414 | if (mips_opts.at == ATREG) | |
13415 | as_warn (_("used $at without \".set noat\"")); | |
13416 | else | |
13417 | as_warn (_("used $%u with \".set at=$%u\""), | |
13418 | regno, mips_opts.at); | |
13419 | } | |
252b5132 RH |
13420 | break; |
13421 | ||
13422 | default: | |
13423 | internalError (); | |
13424 | } | |
13425 | ||
13426 | if (regno == ILLEGAL_REG) | |
13427 | break; | |
13428 | ||
13429 | switch (c) | |
13430 | { | |
13431 | case 'x': | |
13432 | case 'v': | |
bf12938e | 13433 | MIPS16_INSERT_OPERAND (RX, *ip, regno); |
252b5132 RH |
13434 | break; |
13435 | case 'y': | |
13436 | case 'w': | |
bf12938e | 13437 | MIPS16_INSERT_OPERAND (RY, *ip, regno); |
252b5132 RH |
13438 | break; |
13439 | case 'z': | |
bf12938e | 13440 | MIPS16_INSERT_OPERAND (RZ, *ip, regno); |
252b5132 RH |
13441 | break; |
13442 | case 'Z': | |
bf12938e | 13443 | MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno); |
252b5132 RH |
13444 | case '0': |
13445 | case 'S': | |
13446 | case 'R': | |
13447 | break; | |
13448 | case 'X': | |
bf12938e | 13449 | MIPS16_INSERT_OPERAND (REGR32, *ip, regno); |
252b5132 RH |
13450 | break; |
13451 | case 'Y': | |
13452 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
bf12938e | 13453 | MIPS16_INSERT_OPERAND (REG32R, *ip, regno); |
252b5132 RH |
13454 | break; |
13455 | default: | |
13456 | internalError (); | |
13457 | } | |
13458 | ||
13459 | lastregno = regno; | |
13460 | continue; | |
13461 | ||
13462 | case 'P': | |
13463 | if (strncmp (s, "$pc", 3) == 0) | |
13464 | { | |
13465 | s += 3; | |
13466 | continue; | |
13467 | } | |
13468 | break; | |
13469 | ||
252b5132 RH |
13470 | case '5': |
13471 | case 'H': | |
13472 | case 'W': | |
13473 | case 'D': | |
13474 | case 'j': | |
252b5132 RH |
13475 | case 'V': |
13476 | case 'C': | |
13477 | case 'U': | |
13478 | case 'k': | |
13479 | case 'K': | |
d6f16593 MR |
13480 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); |
13481 | if (i > 0) | |
252b5132 | 13482 | { |
d6f16593 | 13483 | if (imm_expr.X_op != O_constant) |
252b5132 | 13484 | { |
df58fc94 | 13485 | forced_insn_length = 4; |
b34976b6 | 13486 | ip->use_extend = TRUE; |
252b5132 | 13487 | ip->extend = 0; |
252b5132 | 13488 | } |
d6f16593 MR |
13489 | else |
13490 | { | |
13491 | /* We need to relax this instruction. */ | |
13492 | *offset_reloc = *imm_reloc; | |
13493 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
13494 | } | |
13495 | s = expr_end; | |
13496 | continue; | |
252b5132 | 13497 | } |
d6f16593 MR |
13498 | *imm_reloc = BFD_RELOC_UNUSED; |
13499 | /* Fall through. */ | |
13500 | case '<': | |
13501 | case '>': | |
13502 | case '[': | |
13503 | case ']': | |
13504 | case '4': | |
13505 | case '8': | |
13506 | my_getExpression (&imm_expr, s); | |
252b5132 RH |
13507 | if (imm_expr.X_op == O_register) |
13508 | { | |
13509 | /* What we thought was an expression turned out to | |
13510 | be a register. */ | |
13511 | ||
13512 | if (s[0] == '(' && args[1] == '(') | |
13513 | { | |
13514 | /* It looks like the expression was omitted | |
13515 | before a register indirection, which means | |
13516 | that the expression is implicitly zero. We | |
13517 | still set up imm_expr, so that we handle | |
13518 | explicit extensions correctly. */ | |
13519 | imm_expr.X_op = O_constant; | |
13520 | imm_expr.X_add_number = 0; | |
f6688943 | 13521 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
13522 | continue; |
13523 | } | |
13524 | ||
13525 | break; | |
13526 | } | |
13527 | ||
13528 | /* We need to relax this instruction. */ | |
f6688943 | 13529 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
13530 | s = expr_end; |
13531 | continue; | |
13532 | ||
13533 | case 'p': | |
13534 | case 'q': | |
13535 | case 'A': | |
13536 | case 'B': | |
13537 | case 'E': | |
13538 | /* We use offset_reloc rather than imm_reloc for the PC | |
13539 | relative operands. This lets macros with both | |
13540 | immediate and address operands work correctly. */ | |
13541 | my_getExpression (&offset_expr, s); | |
13542 | ||
13543 | if (offset_expr.X_op == O_register) | |
13544 | break; | |
13545 | ||
13546 | /* We need to relax this instruction. */ | |
f6688943 | 13547 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
13548 | s = expr_end; |
13549 | continue; | |
13550 | ||
13551 | case '6': /* break code */ | |
13552 | my_getExpression (&imm_expr, s); | |
13553 | check_absolute_expr (ip, &imm_expr); | |
13554 | if ((unsigned long) imm_expr.X_add_number > 63) | |
bf12938e RS |
13555 | as_warn (_("Invalid value for `%s' (%lu)"), |
13556 | ip->insn_mo->name, | |
13557 | (unsigned long) imm_expr.X_add_number); | |
13558 | MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number); | |
252b5132 RH |
13559 | imm_expr.X_op = O_absent; |
13560 | s = expr_end; | |
13561 | continue; | |
13562 | ||
13563 | case 'a': /* 26 bit address */ | |
13564 | my_getExpression (&offset_expr, s); | |
13565 | s = expr_end; | |
f6688943 | 13566 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
13567 | ip->insn_opcode <<= 16; |
13568 | continue; | |
13569 | ||
13570 | case 'l': /* register list for entry macro */ | |
13571 | case 'L': /* register list for exit macro */ | |
13572 | { | |
13573 | int mask; | |
13574 | ||
13575 | if (c == 'l') | |
13576 | mask = 0; | |
13577 | else | |
13578 | mask = 7 << 3; | |
13579 | while (*s != '\0') | |
13580 | { | |
707bfff6 | 13581 | unsigned int freg, reg1, reg2; |
252b5132 RH |
13582 | |
13583 | while (*s == ' ' || *s == ',') | |
13584 | ++s; | |
707bfff6 | 13585 | if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
252b5132 | 13586 | freg = 0; |
707bfff6 TS |
13587 | else if (reg_lookup (&s, RTYPE_FPU, ®1)) |
13588 | freg = 1; | |
252b5132 RH |
13589 | else |
13590 | { | |
707bfff6 TS |
13591 | as_bad (_("can't parse register list")); |
13592 | break; | |
252b5132 RH |
13593 | } |
13594 | if (*s == ' ') | |
13595 | ++s; | |
13596 | if (*s != '-') | |
13597 | reg2 = reg1; | |
13598 | else | |
13599 | { | |
13600 | ++s; | |
707bfff6 TS |
13601 | if (!reg_lookup (&s, freg ? RTYPE_FPU |
13602 | : (RTYPE_GP | RTYPE_NUM), ®2)) | |
252b5132 | 13603 | { |
707bfff6 TS |
13604 | as_bad (_("invalid register list")); |
13605 | break; | |
252b5132 RH |
13606 | } |
13607 | } | |
13608 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
13609 | { | |
13610 | mask &= ~ (7 << 3); | |
13611 | mask |= 5 << 3; | |
13612 | } | |
13613 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
13614 | { | |
13615 | mask &= ~ (7 << 3); | |
13616 | mask |= 6 << 3; | |
13617 | } | |
13618 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
13619 | mask |= (reg2 - 3) << 3; | |
13620 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
13621 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 13622 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
13623 | mask |= 1; |
13624 | else | |
13625 | { | |
13626 | as_bad (_("invalid register list")); | |
13627 | break; | |
13628 | } | |
13629 | } | |
13630 | /* The mask is filled in in the opcode table for the | |
13631 | benefit of the disassembler. We remove it before | |
13632 | applying the actual mask. */ | |
13633 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
13634 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
13635 | } | |
13636 | continue; | |
13637 | ||
0499d65b TS |
13638 | case 'm': /* Register list for save insn. */ |
13639 | case 'M': /* Register list for restore insn. */ | |
13640 | { | |
13641 | int opcode = 0; | |
13642 | int framesz = 0, seen_framesz = 0; | |
91d6fa6a | 13643 | int nargs = 0, statics = 0, sregs = 0; |
0499d65b TS |
13644 | |
13645 | while (*s != '\0') | |
13646 | { | |
13647 | unsigned int reg1, reg2; | |
13648 | ||
13649 | SKIP_SPACE_TABS (s); | |
13650 | while (*s == ',') | |
13651 | ++s; | |
13652 | SKIP_SPACE_TABS (s); | |
13653 | ||
13654 | my_getExpression (&imm_expr, s); | |
13655 | if (imm_expr.X_op == O_constant) | |
13656 | { | |
13657 | /* Handle the frame size. */ | |
13658 | if (seen_framesz) | |
13659 | { | |
13660 | as_bad (_("more than one frame size in list")); | |
13661 | break; | |
13662 | } | |
13663 | seen_framesz = 1; | |
13664 | framesz = imm_expr.X_add_number; | |
13665 | imm_expr.X_op = O_absent; | |
13666 | s = expr_end; | |
13667 | continue; | |
13668 | } | |
13669 | ||
707bfff6 | 13670 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
0499d65b TS |
13671 | { |
13672 | as_bad (_("can't parse register list")); | |
13673 | break; | |
13674 | } | |
0499d65b | 13675 | |
707bfff6 TS |
13676 | while (*s == ' ') |
13677 | ++s; | |
13678 | ||
0499d65b TS |
13679 | if (*s != '-') |
13680 | reg2 = reg1; | |
13681 | else | |
13682 | { | |
13683 | ++s; | |
707bfff6 TS |
13684 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2) |
13685 | || reg2 < reg1) | |
0499d65b TS |
13686 | { |
13687 | as_bad (_("can't parse register list")); | |
13688 | break; | |
13689 | } | |
0499d65b TS |
13690 | } |
13691 | ||
13692 | while (reg1 <= reg2) | |
13693 | { | |
13694 | if (reg1 >= 4 && reg1 <= 7) | |
13695 | { | |
3a93f742 | 13696 | if (!seen_framesz) |
0499d65b | 13697 | /* args $a0-$a3 */ |
91d6fa6a | 13698 | nargs |= 1 << (reg1 - 4); |
0499d65b TS |
13699 | else |
13700 | /* statics $a0-$a3 */ | |
13701 | statics |= 1 << (reg1 - 4); | |
13702 | } | |
13703 | else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30) | |
13704 | { | |
13705 | /* $s0-$s8 */ | |
13706 | sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16)); | |
13707 | } | |
13708 | else if (reg1 == 31) | |
13709 | { | |
13710 | /* Add $ra to insn. */ | |
13711 | opcode |= 0x40; | |
13712 | } | |
13713 | else | |
13714 | { | |
13715 | as_bad (_("unexpected register in list")); | |
13716 | break; | |
13717 | } | |
13718 | if (++reg1 == 24) | |
13719 | reg1 = 30; | |
13720 | } | |
13721 | } | |
13722 | ||
13723 | /* Encode args/statics combination. */ | |
91d6fa6a | 13724 | if (nargs & statics) |
0499d65b | 13725 | as_bad (_("arg/static registers overlap")); |
91d6fa6a | 13726 | else if (nargs == 0xf) |
0499d65b TS |
13727 | /* All $a0-$a3 are args. */ |
13728 | opcode |= MIPS16_ALL_ARGS << 16; | |
13729 | else if (statics == 0xf) | |
13730 | /* All $a0-$a3 are statics. */ | |
13731 | opcode |= MIPS16_ALL_STATICS << 16; | |
13732 | else | |
13733 | { | |
13734 | int narg = 0, nstat = 0; | |
13735 | ||
13736 | /* Count arg registers. */ | |
91d6fa6a | 13737 | while (nargs & 0x1) |
0499d65b | 13738 | { |
91d6fa6a | 13739 | nargs >>= 1; |
0499d65b TS |
13740 | narg++; |
13741 | } | |
91d6fa6a | 13742 | if (nargs != 0) |
0499d65b TS |
13743 | as_bad (_("invalid arg register list")); |
13744 | ||
13745 | /* Count static registers. */ | |
13746 | while (statics & 0x8) | |
13747 | { | |
13748 | statics = (statics << 1) & 0xf; | |
13749 | nstat++; | |
13750 | } | |
13751 | if (statics != 0) | |
13752 | as_bad (_("invalid static register list")); | |
13753 | ||
13754 | /* Encode args/statics. */ | |
13755 | opcode |= ((narg << 2) | nstat) << 16; | |
13756 | } | |
13757 | ||
13758 | /* Encode $s0/$s1. */ | |
13759 | if (sregs & (1 << 0)) /* $s0 */ | |
13760 | opcode |= 0x20; | |
13761 | if (sregs & (1 << 1)) /* $s1 */ | |
13762 | opcode |= 0x10; | |
13763 | sregs >>= 2; | |
13764 | ||
13765 | if (sregs != 0) | |
13766 | { | |
13767 | /* Count regs $s2-$s8. */ | |
13768 | int nsreg = 0; | |
13769 | while (sregs & 1) | |
13770 | { | |
13771 | sregs >>= 1; | |
13772 | nsreg++; | |
13773 | } | |
13774 | if (sregs != 0) | |
13775 | as_bad (_("invalid static register list")); | |
13776 | /* Encode $s2-$s8. */ | |
13777 | opcode |= nsreg << 24; | |
13778 | } | |
13779 | ||
13780 | /* Encode frame size. */ | |
13781 | if (!seen_framesz) | |
13782 | as_bad (_("missing frame size")); | |
13783 | else if ((framesz & 7) != 0 || framesz < 0 | |
13784 | || framesz > 0xff * 8) | |
13785 | as_bad (_("invalid frame size")); | |
13786 | else if (framesz != 128 || (opcode >> 16) != 0) | |
13787 | { | |
13788 | framesz /= 8; | |
13789 | opcode |= (((framesz & 0xf0) << 16) | |
13790 | | (framesz & 0x0f)); | |
13791 | } | |
13792 | ||
13793 | /* Finally build the instruction. */ | |
13794 | if ((opcode >> 16) != 0 || framesz == 0) | |
13795 | { | |
13796 | ip->use_extend = TRUE; | |
13797 | ip->extend = opcode >> 16; | |
13798 | } | |
13799 | ip->insn_opcode |= opcode & 0x7f; | |
13800 | } | |
13801 | continue; | |
13802 | ||
252b5132 RH |
13803 | case 'e': /* extend code */ |
13804 | my_getExpression (&imm_expr, s); | |
13805 | check_absolute_expr (ip, &imm_expr); | |
13806 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
13807 | { | |
13808 | as_warn (_("Invalid value for `%s' (%lu)"), | |
13809 | ip->insn_mo->name, | |
13810 | (unsigned long) imm_expr.X_add_number); | |
13811 | imm_expr.X_add_number &= 0x7ff; | |
13812 | } | |
13813 | ip->insn_opcode |= imm_expr.X_add_number; | |
13814 | imm_expr.X_op = O_absent; | |
13815 | s = expr_end; | |
13816 | continue; | |
13817 | ||
13818 | default: | |
13819 | internalError (); | |
13820 | } | |
13821 | break; | |
13822 | } | |
13823 | ||
13824 | /* Args don't match. */ | |
13825 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
13826 | strcmp (insn->name, insn[1].name) == 0) | |
13827 | { | |
13828 | ++insn; | |
13829 | s = argsstart; | |
13830 | continue; | |
13831 | } | |
13832 | ||
13833 | insn_error = _("illegal operands"); | |
13834 | ||
13835 | return; | |
13836 | } | |
13837 | } | |
13838 | ||
13839 | /* This structure holds information we know about a mips16 immediate | |
13840 | argument type. */ | |
13841 | ||
e972090a NC |
13842 | struct mips16_immed_operand |
13843 | { | |
252b5132 RH |
13844 | /* The type code used in the argument string in the opcode table. */ |
13845 | int type; | |
13846 | /* The number of bits in the short form of the opcode. */ | |
13847 | int nbits; | |
13848 | /* The number of bits in the extended form of the opcode. */ | |
13849 | int extbits; | |
13850 | /* The amount by which the short form is shifted when it is used; | |
13851 | for example, the sw instruction has a shift count of 2. */ | |
13852 | int shift; | |
13853 | /* The amount by which the short form is shifted when it is stored | |
13854 | into the instruction code. */ | |
13855 | int op_shift; | |
13856 | /* Non-zero if the short form is unsigned. */ | |
13857 | int unsp; | |
13858 | /* Non-zero if the extended form is unsigned. */ | |
13859 | int extu; | |
13860 | /* Non-zero if the value is PC relative. */ | |
13861 | int pcrel; | |
13862 | }; | |
13863 | ||
13864 | /* The mips16 immediate operand types. */ | |
13865 | ||
13866 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
13867 | { | |
13868 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
13869 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
13870 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
13871 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
13872 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
13873 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
13874 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
13875 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
13876 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
13877 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
13878 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
13879 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
13880 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
13881 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
13882 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
13883 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
13884 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
13885 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
13886 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
13887 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
13888 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
13889 | }; | |
13890 | ||
13891 | #define MIPS16_NUM_IMMED \ | |
13892 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
13893 | ||
13894 | /* Handle a mips16 instruction with an immediate value. This or's the | |
13895 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
13896 | whether an extended value is needed; if one is needed, it sets | |
13897 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
13898 | If SMALL is true, an unextended opcode was explicitly requested. | |
13899 | If EXT is true, an extended opcode was explicitly requested. If | |
13900 | WARN is true, warn if EXT does not match reality. */ | |
13901 | ||
13902 | static void | |
17a2f251 TS |
13903 | mips16_immed (char *file, unsigned int line, int type, offsetT val, |
13904 | bfd_boolean warn, bfd_boolean small, bfd_boolean ext, | |
13905 | unsigned long *insn, bfd_boolean *use_extend, | |
13906 | unsigned short *extend) | |
252b5132 | 13907 | { |
3994f87e | 13908 | const struct mips16_immed_operand *op; |
252b5132 | 13909 | int mintiny, maxtiny; |
b34976b6 | 13910 | bfd_boolean needext; |
252b5132 RH |
13911 | |
13912 | op = mips16_immed_operands; | |
13913 | while (op->type != type) | |
13914 | { | |
13915 | ++op; | |
9c2799c2 | 13916 | gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
252b5132 RH |
13917 | } |
13918 | ||
13919 | if (op->unsp) | |
13920 | { | |
13921 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
13922 | { | |
13923 | mintiny = 1; | |
13924 | maxtiny = 1 << op->nbits; | |
13925 | } | |
13926 | else | |
13927 | { | |
13928 | mintiny = 0; | |
13929 | maxtiny = (1 << op->nbits) - 1; | |
13930 | } | |
13931 | } | |
13932 | else | |
13933 | { | |
13934 | mintiny = - (1 << (op->nbits - 1)); | |
13935 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
13936 | } | |
13937 | ||
13938 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
13939 | if (type == 'p' || type == 'q') | |
13940 | val /= 2; | |
13941 | ||
13942 | if ((val & ((1 << op->shift) - 1)) != 0 | |
13943 | || val < (mintiny << op->shift) | |
13944 | || val > (maxtiny << op->shift)) | |
b34976b6 | 13945 | needext = TRUE; |
252b5132 | 13946 | else |
b34976b6 | 13947 | needext = FALSE; |
252b5132 RH |
13948 | |
13949 | if (warn && ext && ! needext) | |
beae10d5 KH |
13950 | as_warn_where (file, line, |
13951 | _("extended operand requested but not required")); | |
252b5132 RH |
13952 | if (small && needext) |
13953 | as_bad_where (file, line, _("invalid unextended operand value")); | |
13954 | ||
13955 | if (small || (! ext && ! needext)) | |
13956 | { | |
13957 | int insnval; | |
13958 | ||
b34976b6 | 13959 | *use_extend = FALSE; |
252b5132 RH |
13960 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
13961 | insnval <<= op->op_shift; | |
13962 | *insn |= insnval; | |
13963 | } | |
13964 | else | |
13965 | { | |
13966 | long minext, maxext; | |
13967 | int extval; | |
13968 | ||
13969 | if (op->extu) | |
13970 | { | |
13971 | minext = 0; | |
13972 | maxext = (1 << op->extbits) - 1; | |
13973 | } | |
13974 | else | |
13975 | { | |
13976 | minext = - (1 << (op->extbits - 1)); | |
13977 | maxext = (1 << (op->extbits - 1)) - 1; | |
13978 | } | |
13979 | if (val < minext || val > maxext) | |
13980 | as_bad_where (file, line, | |
13981 | _("operand value out of range for instruction")); | |
13982 | ||
b34976b6 | 13983 | *use_extend = TRUE; |
252b5132 RH |
13984 | if (op->extbits == 16) |
13985 | { | |
13986 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
13987 | val &= 0x1f; | |
13988 | } | |
13989 | else if (op->extbits == 15) | |
13990 | { | |
13991 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
13992 | val &= 0xf; | |
13993 | } | |
13994 | else | |
13995 | { | |
13996 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
13997 | val = 0; | |
13998 | } | |
13999 | ||
14000 | *extend = (unsigned short) extval; | |
14001 | *insn |= val; | |
14002 | } | |
14003 | } | |
14004 | \f | |
d6f16593 | 14005 | struct percent_op_match |
ad8d3bb3 | 14006 | { |
5e0116d5 RS |
14007 | const char *str; |
14008 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
14009 | }; |
14010 | ||
14011 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 14012 | { |
5e0116d5 | 14013 | {"%lo", BFD_RELOC_LO16}, |
ad8d3bb3 | 14014 | #ifdef OBJ_ELF |
5e0116d5 RS |
14015 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
14016 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
14017 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
14018 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
14019 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
14020 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
14021 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
14022 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
14023 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
14024 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
14025 | {"%half", BFD_RELOC_16}, | |
14026 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
14027 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
14028 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
14029 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
14030 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
14031 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
14032 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
14033 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
14034 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
14035 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
ad8d3bb3 | 14036 | #endif |
5e0116d5 | 14037 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
14038 | }; |
14039 | ||
d6f16593 MR |
14040 | static const struct percent_op_match mips16_percent_op[] = |
14041 | { | |
14042 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
14043 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, | |
738e5348 RS |
14044 | {"%got", BFD_RELOC_MIPS16_GOT16}, |
14045 | {"%call16", BFD_RELOC_MIPS16_CALL16}, | |
d6f16593 MR |
14046 | {"%hi", BFD_RELOC_MIPS16_HI16_S} |
14047 | }; | |
14048 | ||
252b5132 | 14049 | |
5e0116d5 RS |
14050 | /* Return true if *STR points to a relocation operator. When returning true, |
14051 | move *STR over the operator and store its relocation code in *RELOC. | |
14052 | Leave both *STR and *RELOC alone when returning false. */ | |
14053 | ||
14054 | static bfd_boolean | |
17a2f251 | 14055 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 14056 | { |
d6f16593 MR |
14057 | const struct percent_op_match *percent_op; |
14058 | size_t limit, i; | |
14059 | ||
14060 | if (mips_opts.mips16) | |
14061 | { | |
14062 | percent_op = mips16_percent_op; | |
14063 | limit = ARRAY_SIZE (mips16_percent_op); | |
14064 | } | |
14065 | else | |
14066 | { | |
14067 | percent_op = mips_percent_op; | |
14068 | limit = ARRAY_SIZE (mips_percent_op); | |
14069 | } | |
76b3015f | 14070 | |
d6f16593 | 14071 | for (i = 0; i < limit; i++) |
5e0116d5 | 14072 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 14073 | { |
3f98094e DJ |
14074 | int len = strlen (percent_op[i].str); |
14075 | ||
14076 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
14077 | continue; | |
14078 | ||
5e0116d5 RS |
14079 | *str += strlen (percent_op[i].str); |
14080 | *reloc = percent_op[i].reloc; | |
394f9b3a | 14081 | |
5e0116d5 RS |
14082 | /* Check whether the output BFD supports this relocation. |
14083 | If not, issue an error and fall back on something safe. */ | |
14084 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 14085 | { |
20203fb9 | 14086 | as_bad (_("relocation %s isn't supported by the current ABI"), |
5e0116d5 | 14087 | percent_op[i].str); |
01a3f561 | 14088 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 14089 | } |
5e0116d5 | 14090 | return TRUE; |
394f9b3a | 14091 | } |
5e0116d5 | 14092 | return FALSE; |
394f9b3a | 14093 | } |
ad8d3bb3 | 14094 | |
ad8d3bb3 | 14095 | |
5e0116d5 RS |
14096 | /* Parse string STR as a 16-bit relocatable operand. Store the |
14097 | expression in *EP and the relocations in the array starting | |
14098 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 14099 | |
01a3f561 | 14100 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 14101 | |
5e0116d5 | 14102 | static size_t |
17a2f251 TS |
14103 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
14104 | char *str) | |
ad8d3bb3 | 14105 | { |
5e0116d5 RS |
14106 | bfd_reloc_code_real_type reversed_reloc[3]; |
14107 | size_t reloc_index, i; | |
09b8f35a RS |
14108 | int crux_depth, str_depth; |
14109 | char *crux; | |
5e0116d5 RS |
14110 | |
14111 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
14112 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
14113 | of the main expression and with CRUX_DEPTH containing the number | |
14114 | of open brackets at that point. */ | |
14115 | reloc_index = -1; | |
14116 | str_depth = 0; | |
14117 | do | |
fb1b3232 | 14118 | { |
09b8f35a RS |
14119 | reloc_index++; |
14120 | crux = str; | |
14121 | crux_depth = str_depth; | |
14122 | ||
14123 | /* Skip over whitespace and brackets, keeping count of the number | |
14124 | of brackets. */ | |
14125 | while (*str == ' ' || *str == '\t' || *str == '(') | |
14126 | if (*str++ == '(') | |
14127 | str_depth++; | |
5e0116d5 | 14128 | } |
09b8f35a RS |
14129 | while (*str == '%' |
14130 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
14131 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 14132 | |
09b8f35a | 14133 | my_getExpression (ep, crux); |
5e0116d5 | 14134 | str = expr_end; |
394f9b3a | 14135 | |
5e0116d5 | 14136 | /* Match every open bracket. */ |
09b8f35a | 14137 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 14138 | if (*str++ == ')') |
09b8f35a | 14139 | crux_depth--; |
394f9b3a | 14140 | |
09b8f35a | 14141 | if (crux_depth > 0) |
20203fb9 | 14142 | as_bad (_("unclosed '('")); |
394f9b3a | 14143 | |
5e0116d5 | 14144 | expr_end = str; |
252b5132 | 14145 | |
01a3f561 | 14146 | if (reloc_index != 0) |
64bdfcaf RS |
14147 | { |
14148 | prev_reloc_op_frag = frag_now; | |
14149 | for (i = 0; i < reloc_index; i++) | |
14150 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
14151 | } | |
fb1b3232 | 14152 | |
5e0116d5 | 14153 | return reloc_index; |
252b5132 RH |
14154 | } |
14155 | ||
14156 | static void | |
17a2f251 | 14157 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
14158 | { |
14159 | char *save_in; | |
14160 | ||
14161 | save_in = input_line_pointer; | |
14162 | input_line_pointer = str; | |
14163 | expression (ep); | |
14164 | expr_end = input_line_pointer; | |
14165 | input_line_pointer = save_in; | |
252b5132 RH |
14166 | } |
14167 | ||
252b5132 | 14168 | char * |
17a2f251 | 14169 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 14170 | { |
499ac353 | 14171 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
252b5132 RH |
14172 | } |
14173 | ||
14174 | void | |
17a2f251 | 14175 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
14176 | { |
14177 | if (target_big_endian) | |
14178 | number_to_chars_bigendian (buf, val, n); | |
14179 | else | |
14180 | number_to_chars_littleendian (buf, val, n); | |
14181 | } | |
14182 | \f | |
ae948b86 | 14183 | #ifdef OBJ_ELF |
e013f690 TS |
14184 | static int support_64bit_objects(void) |
14185 | { | |
14186 | const char **list, **l; | |
aa3d8fdf | 14187 | int yes; |
e013f690 TS |
14188 | |
14189 | list = bfd_target_list (); | |
14190 | for (l = list; *l != NULL; l++) | |
aeffff67 RS |
14191 | if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0 |
14192 | || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0) | |
e013f690 | 14193 | break; |
aa3d8fdf | 14194 | yes = (*l != NULL); |
e013f690 | 14195 | free (list); |
aa3d8fdf | 14196 | return yes; |
e013f690 | 14197 | } |
ae948b86 | 14198 | #endif /* OBJ_ELF */ |
e013f690 | 14199 | |
78849248 | 14200 | const char *md_shortopts = "O::g::G:"; |
252b5132 | 14201 | |
23fce1e3 NC |
14202 | enum options |
14203 | { | |
14204 | OPTION_MARCH = OPTION_MD_BASE, | |
14205 | OPTION_MTUNE, | |
14206 | OPTION_MIPS1, | |
14207 | OPTION_MIPS2, | |
14208 | OPTION_MIPS3, | |
14209 | OPTION_MIPS4, | |
14210 | OPTION_MIPS5, | |
14211 | OPTION_MIPS32, | |
14212 | OPTION_MIPS64, | |
14213 | OPTION_MIPS32R2, | |
14214 | OPTION_MIPS64R2, | |
14215 | OPTION_MIPS16, | |
14216 | OPTION_NO_MIPS16, | |
14217 | OPTION_MIPS3D, | |
14218 | OPTION_NO_MIPS3D, | |
14219 | OPTION_MDMX, | |
14220 | OPTION_NO_MDMX, | |
14221 | OPTION_DSP, | |
14222 | OPTION_NO_DSP, | |
14223 | OPTION_MT, | |
14224 | OPTION_NO_MT, | |
14225 | OPTION_SMARTMIPS, | |
14226 | OPTION_NO_SMARTMIPS, | |
14227 | OPTION_DSPR2, | |
14228 | OPTION_NO_DSPR2, | |
df58fc94 RS |
14229 | OPTION_MICROMIPS, |
14230 | OPTION_NO_MICROMIPS, | |
dec0624d MR |
14231 | OPTION_MCU, |
14232 | OPTION_NO_MCU, | |
23fce1e3 NC |
14233 | OPTION_COMPAT_ARCH_BASE, |
14234 | OPTION_M4650, | |
14235 | OPTION_NO_M4650, | |
14236 | OPTION_M4010, | |
14237 | OPTION_NO_M4010, | |
14238 | OPTION_M4100, | |
14239 | OPTION_NO_M4100, | |
14240 | OPTION_M3900, | |
14241 | OPTION_NO_M3900, | |
14242 | OPTION_M7000_HILO_FIX, | |
6a32d874 CM |
14243 | OPTION_MNO_7000_HILO_FIX, |
14244 | OPTION_FIX_24K, | |
14245 | OPTION_NO_FIX_24K, | |
c67a084a NC |
14246 | OPTION_FIX_LOONGSON2F_JUMP, |
14247 | OPTION_NO_FIX_LOONGSON2F_JUMP, | |
14248 | OPTION_FIX_LOONGSON2F_NOP, | |
14249 | OPTION_NO_FIX_LOONGSON2F_NOP, | |
23fce1e3 NC |
14250 | OPTION_FIX_VR4120, |
14251 | OPTION_NO_FIX_VR4120, | |
14252 | OPTION_FIX_VR4130, | |
14253 | OPTION_NO_FIX_VR4130, | |
d954098f DD |
14254 | OPTION_FIX_CN63XXP1, |
14255 | OPTION_NO_FIX_CN63XXP1, | |
23fce1e3 NC |
14256 | OPTION_TRAP, |
14257 | OPTION_BREAK, | |
14258 | OPTION_EB, | |
14259 | OPTION_EL, | |
14260 | OPTION_FP32, | |
14261 | OPTION_GP32, | |
14262 | OPTION_CONSTRUCT_FLOATS, | |
14263 | OPTION_NO_CONSTRUCT_FLOATS, | |
14264 | OPTION_FP64, | |
14265 | OPTION_GP64, | |
14266 | OPTION_RELAX_BRANCH, | |
14267 | OPTION_NO_RELAX_BRANCH, | |
14268 | OPTION_MSHARED, | |
14269 | OPTION_MNO_SHARED, | |
14270 | OPTION_MSYM32, | |
14271 | OPTION_MNO_SYM32, | |
14272 | OPTION_SOFT_FLOAT, | |
14273 | OPTION_HARD_FLOAT, | |
14274 | OPTION_SINGLE_FLOAT, | |
14275 | OPTION_DOUBLE_FLOAT, | |
14276 | OPTION_32, | |
14277 | #ifdef OBJ_ELF | |
14278 | OPTION_CALL_SHARED, | |
14279 | OPTION_CALL_NONPIC, | |
14280 | OPTION_NON_SHARED, | |
14281 | OPTION_XGOT, | |
14282 | OPTION_MABI, | |
14283 | OPTION_N32, | |
14284 | OPTION_64, | |
14285 | OPTION_MDEBUG, | |
14286 | OPTION_NO_MDEBUG, | |
14287 | OPTION_PDR, | |
14288 | OPTION_NO_PDR, | |
14289 | OPTION_MVXWORKS_PIC, | |
14290 | #endif /* OBJ_ELF */ | |
14291 | OPTION_END_OF_ENUM | |
14292 | }; | |
14293 | ||
e972090a NC |
14294 | struct option md_longopts[] = |
14295 | { | |
f9b4148d | 14296 | /* Options which specify architecture. */ |
f9b4148d | 14297 | {"march", required_argument, NULL, OPTION_MARCH}, |
f9b4148d | 14298 | {"mtune", required_argument, NULL, OPTION_MTUNE}, |
252b5132 RH |
14299 | {"mips0", no_argument, NULL, OPTION_MIPS1}, |
14300 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
252b5132 | 14301 | {"mips2", no_argument, NULL, OPTION_MIPS2}, |
252b5132 | 14302 | {"mips3", no_argument, NULL, OPTION_MIPS3}, |
252b5132 | 14303 | {"mips4", no_argument, NULL, OPTION_MIPS4}, |
ae948b86 | 14304 | {"mips5", no_argument, NULL, OPTION_MIPS5}, |
ae948b86 | 14305 | {"mips32", no_argument, NULL, OPTION_MIPS32}, |
ae948b86 | 14306 | {"mips64", no_argument, NULL, OPTION_MIPS64}, |
f9b4148d | 14307 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, |
5f74bc13 | 14308 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, |
f9b4148d CD |
14309 | |
14310 | /* Options which specify Application Specific Extensions (ASEs). */ | |
f9b4148d | 14311 | {"mips16", no_argument, NULL, OPTION_MIPS16}, |
f9b4148d | 14312 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, |
f9b4148d | 14313 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, |
f9b4148d | 14314 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, |
f9b4148d | 14315 | {"mdmx", no_argument, NULL, OPTION_MDMX}, |
f9b4148d | 14316 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, |
74cd071d | 14317 | {"mdsp", no_argument, NULL, OPTION_DSP}, |
74cd071d | 14318 | {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, |
ef2e4d86 | 14319 | {"mmt", no_argument, NULL, OPTION_MT}, |
ef2e4d86 | 14320 | {"mno-mt", no_argument, NULL, OPTION_NO_MT}, |
e16bfa71 | 14321 | {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS}, |
e16bfa71 | 14322 | {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS}, |
8b082fb1 | 14323 | {"mdspr2", no_argument, NULL, OPTION_DSPR2}, |
8b082fb1 | 14324 | {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2}, |
df58fc94 RS |
14325 | {"mmicromips", no_argument, NULL, OPTION_MICROMIPS}, |
14326 | {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS}, | |
dec0624d MR |
14327 | {"mmcu", no_argument, NULL, OPTION_MCU}, |
14328 | {"mno-mcu", no_argument, NULL, OPTION_NO_MCU}, | |
f9b4148d CD |
14329 | |
14330 | /* Old-style architecture options. Don't add more of these. */ | |
f9b4148d | 14331 | {"m4650", no_argument, NULL, OPTION_M4650}, |
f9b4148d | 14332 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, |
f9b4148d | 14333 | {"m4010", no_argument, NULL, OPTION_M4010}, |
f9b4148d | 14334 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, |
f9b4148d | 14335 | {"m4100", no_argument, NULL, OPTION_M4100}, |
f9b4148d | 14336 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, |
f9b4148d | 14337 | {"m3900", no_argument, NULL, OPTION_M3900}, |
f9b4148d CD |
14338 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, |
14339 | ||
14340 | /* Options which enable bug fixes. */ | |
f9b4148d | 14341 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, |
f9b4148d CD |
14342 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, |
14343 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
c67a084a NC |
14344 | {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP}, |
14345 | {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP}, | |
14346 | {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP}, | |
14347 | {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP}, | |
d766e8ec RS |
14348 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, |
14349 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
7d8e00cf RS |
14350 | {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, |
14351 | {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, | |
6a32d874 CM |
14352 | {"mfix-24k", no_argument, NULL, OPTION_FIX_24K}, |
14353 | {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K}, | |
d954098f DD |
14354 | {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1}, |
14355 | {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1}, | |
f9b4148d CD |
14356 | |
14357 | /* Miscellaneous options. */ | |
252b5132 RH |
14358 | {"trap", no_argument, NULL, OPTION_TRAP}, |
14359 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
252b5132 RH |
14360 | {"break", no_argument, NULL, OPTION_BREAK}, |
14361 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
252b5132 | 14362 | {"EB", no_argument, NULL, OPTION_EB}, |
252b5132 | 14363 | {"EL", no_argument, NULL, OPTION_EL}, |
ae948b86 | 14364 | {"mfp32", no_argument, NULL, OPTION_FP32}, |
c97ef257 | 14365 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
119d663a | 14366 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
119d663a | 14367 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
316f5878 | 14368 | {"mfp64", no_argument, NULL, OPTION_FP64}, |
ae948b86 | 14369 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
4a6a3df4 AO |
14370 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, |
14371 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
aa6975fb ILT |
14372 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
14373 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
aed1a261 RS |
14374 | {"msym32", no_argument, NULL, OPTION_MSYM32}, |
14375 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, | |
037b32b9 AN |
14376 | {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT}, |
14377 | {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT}, | |
037b32b9 AN |
14378 | {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT}, |
14379 | {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT}, | |
23fce1e3 NC |
14380 | |
14381 | /* Strictly speaking this next option is ELF specific, | |
14382 | but we allow it for other ports as well in order to | |
14383 | make testing easier. */ | |
14384 | {"32", no_argument, NULL, OPTION_32}, | |
037b32b9 | 14385 | |
f9b4148d | 14386 | /* ELF-specific options. */ |
156c2f8b | 14387 | #ifdef OBJ_ELF |
156c2f8b NC |
14388 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
14389 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
861fb55a | 14390 | {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC}, |
156c2f8b NC |
14391 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
14392 | {"xgot", no_argument, NULL, OPTION_XGOT}, | |
ae948b86 | 14393 | {"mabi", required_argument, NULL, OPTION_MABI}, |
e013f690 | 14394 | {"n32", no_argument, NULL, OPTION_N32}, |
156c2f8b | 14395 | {"64", no_argument, NULL, OPTION_64}, |
ecb4347a | 14396 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, |
ecb4347a | 14397 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, |
dcd410fe | 14398 | {"mpdr", no_argument, NULL, OPTION_PDR}, |
dcd410fe | 14399 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, |
0a44bf69 | 14400 | {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, |
ae948b86 | 14401 | #endif /* OBJ_ELF */ |
f9b4148d | 14402 | |
252b5132 RH |
14403 | {NULL, no_argument, NULL, 0} |
14404 | }; | |
156c2f8b | 14405 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 14406 | |
316f5878 RS |
14407 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
14408 | NEW_VALUE. Warn if another value was already specified. Note: | |
14409 | we have to defer parsing the -march and -mtune arguments in order | |
14410 | to handle 'from-abi' correctly, since the ABI might be specified | |
14411 | in a later argument. */ | |
14412 | ||
14413 | static void | |
17a2f251 | 14414 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
14415 | { |
14416 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
14417 | as_warn (_("A different %s was already specified, is now %s"), | |
14418 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
14419 | new_value); | |
14420 | ||
14421 | *string_ptr = new_value; | |
14422 | } | |
14423 | ||
252b5132 | 14424 | int |
17a2f251 | 14425 | md_parse_option (int c, char *arg) |
252b5132 RH |
14426 | { |
14427 | switch (c) | |
14428 | { | |
119d663a NC |
14429 | case OPTION_CONSTRUCT_FLOATS: |
14430 | mips_disable_float_construction = 0; | |
14431 | break; | |
bdaaa2e1 | 14432 | |
119d663a NC |
14433 | case OPTION_NO_CONSTRUCT_FLOATS: |
14434 | mips_disable_float_construction = 1; | |
14435 | break; | |
bdaaa2e1 | 14436 | |
252b5132 RH |
14437 | case OPTION_TRAP: |
14438 | mips_trap = 1; | |
14439 | break; | |
14440 | ||
14441 | case OPTION_BREAK: | |
14442 | mips_trap = 0; | |
14443 | break; | |
14444 | ||
14445 | case OPTION_EB: | |
14446 | target_big_endian = 1; | |
14447 | break; | |
14448 | ||
14449 | case OPTION_EL: | |
14450 | target_big_endian = 0; | |
14451 | break; | |
14452 | ||
14453 | case 'O': | |
4ffff32f TS |
14454 | if (arg == NULL) |
14455 | mips_optimize = 1; | |
14456 | else if (arg[0] == '0') | |
14457 | mips_optimize = 0; | |
14458 | else if (arg[0] == '1') | |
252b5132 RH |
14459 | mips_optimize = 1; |
14460 | else | |
14461 | mips_optimize = 2; | |
14462 | break; | |
14463 | ||
14464 | case 'g': | |
14465 | if (arg == NULL) | |
14466 | mips_debug = 2; | |
14467 | else | |
14468 | mips_debug = atoi (arg); | |
252b5132 RH |
14469 | break; |
14470 | ||
14471 | case OPTION_MIPS1: | |
316f5878 | 14472 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
14473 | break; |
14474 | ||
14475 | case OPTION_MIPS2: | |
316f5878 | 14476 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
14477 | break; |
14478 | ||
14479 | case OPTION_MIPS3: | |
316f5878 | 14480 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
14481 | break; |
14482 | ||
14483 | case OPTION_MIPS4: | |
316f5878 | 14484 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
14485 | break; |
14486 | ||
84ea6cf2 | 14487 | case OPTION_MIPS5: |
316f5878 | 14488 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
14489 | break; |
14490 | ||
e7af610e | 14491 | case OPTION_MIPS32: |
316f5878 | 14492 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
14493 | break; |
14494 | ||
af7ee8bf CD |
14495 | case OPTION_MIPS32R2: |
14496 | file_mips_isa = ISA_MIPS32R2; | |
14497 | break; | |
14498 | ||
5f74bc13 CD |
14499 | case OPTION_MIPS64R2: |
14500 | file_mips_isa = ISA_MIPS64R2; | |
14501 | break; | |
14502 | ||
84ea6cf2 | 14503 | case OPTION_MIPS64: |
316f5878 | 14504 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
14505 | break; |
14506 | ||
ec68c924 | 14507 | case OPTION_MTUNE: |
316f5878 RS |
14508 | mips_set_option_string (&mips_tune_string, arg); |
14509 | break; | |
ec68c924 | 14510 | |
316f5878 RS |
14511 | case OPTION_MARCH: |
14512 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
14513 | break; |
14514 | ||
14515 | case OPTION_M4650: | |
316f5878 RS |
14516 | mips_set_option_string (&mips_arch_string, "4650"); |
14517 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
14518 | break; |
14519 | ||
14520 | case OPTION_NO_M4650: | |
14521 | break; | |
14522 | ||
14523 | case OPTION_M4010: | |
316f5878 RS |
14524 | mips_set_option_string (&mips_arch_string, "4010"); |
14525 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
14526 | break; |
14527 | ||
14528 | case OPTION_NO_M4010: | |
14529 | break; | |
14530 | ||
14531 | case OPTION_M4100: | |
316f5878 RS |
14532 | mips_set_option_string (&mips_arch_string, "4100"); |
14533 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
14534 | break; |
14535 | ||
14536 | case OPTION_NO_M4100: | |
14537 | break; | |
14538 | ||
252b5132 | 14539 | case OPTION_M3900: |
316f5878 RS |
14540 | mips_set_option_string (&mips_arch_string, "3900"); |
14541 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 14542 | break; |
bdaaa2e1 | 14543 | |
252b5132 RH |
14544 | case OPTION_NO_M3900: |
14545 | break; | |
14546 | ||
deec1734 CD |
14547 | case OPTION_MDMX: |
14548 | mips_opts.ase_mdmx = 1; | |
14549 | break; | |
14550 | ||
14551 | case OPTION_NO_MDMX: | |
14552 | mips_opts.ase_mdmx = 0; | |
14553 | break; | |
14554 | ||
74cd071d CF |
14555 | case OPTION_DSP: |
14556 | mips_opts.ase_dsp = 1; | |
8b082fb1 | 14557 | mips_opts.ase_dspr2 = 0; |
74cd071d CF |
14558 | break; |
14559 | ||
14560 | case OPTION_NO_DSP: | |
8b082fb1 TS |
14561 | mips_opts.ase_dsp = 0; |
14562 | mips_opts.ase_dspr2 = 0; | |
14563 | break; | |
14564 | ||
14565 | case OPTION_DSPR2: | |
14566 | mips_opts.ase_dspr2 = 1; | |
14567 | mips_opts.ase_dsp = 1; | |
14568 | break; | |
14569 | ||
14570 | case OPTION_NO_DSPR2: | |
14571 | mips_opts.ase_dspr2 = 0; | |
74cd071d CF |
14572 | mips_opts.ase_dsp = 0; |
14573 | break; | |
14574 | ||
ef2e4d86 CF |
14575 | case OPTION_MT: |
14576 | mips_opts.ase_mt = 1; | |
14577 | break; | |
14578 | ||
14579 | case OPTION_NO_MT: | |
14580 | mips_opts.ase_mt = 0; | |
14581 | break; | |
14582 | ||
dec0624d MR |
14583 | case OPTION_MCU: |
14584 | mips_opts.ase_mcu = 1; | |
14585 | break; | |
14586 | ||
14587 | case OPTION_NO_MCU: | |
14588 | mips_opts.ase_mcu = 0; | |
14589 | break; | |
14590 | ||
df58fc94 RS |
14591 | case OPTION_MICROMIPS: |
14592 | if (mips_opts.mips16 == 1) | |
14593 | { | |
14594 | as_bad (_("-mmicromips cannot be used with -mips16")); | |
14595 | return 0; | |
14596 | } | |
14597 | mips_opts.micromips = 1; | |
14598 | mips_no_prev_insn (); | |
14599 | break; | |
14600 | ||
14601 | case OPTION_NO_MICROMIPS: | |
14602 | mips_opts.micromips = 0; | |
14603 | mips_no_prev_insn (); | |
14604 | break; | |
14605 | ||
252b5132 | 14606 | case OPTION_MIPS16: |
df58fc94 RS |
14607 | if (mips_opts.micromips == 1) |
14608 | { | |
14609 | as_bad (_("-mips16 cannot be used with -micromips")); | |
14610 | return 0; | |
14611 | } | |
252b5132 | 14612 | mips_opts.mips16 = 1; |
7d10b47d | 14613 | mips_no_prev_insn (); |
252b5132 RH |
14614 | break; |
14615 | ||
14616 | case OPTION_NO_MIPS16: | |
14617 | mips_opts.mips16 = 0; | |
7d10b47d | 14618 | mips_no_prev_insn (); |
252b5132 RH |
14619 | break; |
14620 | ||
1f25f5d3 CD |
14621 | case OPTION_MIPS3D: |
14622 | mips_opts.ase_mips3d = 1; | |
14623 | break; | |
14624 | ||
14625 | case OPTION_NO_MIPS3D: | |
14626 | mips_opts.ase_mips3d = 0; | |
14627 | break; | |
14628 | ||
e16bfa71 TS |
14629 | case OPTION_SMARTMIPS: |
14630 | mips_opts.ase_smartmips = 1; | |
14631 | break; | |
14632 | ||
14633 | case OPTION_NO_SMARTMIPS: | |
14634 | mips_opts.ase_smartmips = 0; | |
14635 | break; | |
14636 | ||
6a32d874 CM |
14637 | case OPTION_FIX_24K: |
14638 | mips_fix_24k = 1; | |
14639 | break; | |
14640 | ||
14641 | case OPTION_NO_FIX_24K: | |
14642 | mips_fix_24k = 0; | |
14643 | break; | |
14644 | ||
c67a084a NC |
14645 | case OPTION_FIX_LOONGSON2F_JUMP: |
14646 | mips_fix_loongson2f_jump = TRUE; | |
14647 | break; | |
14648 | ||
14649 | case OPTION_NO_FIX_LOONGSON2F_JUMP: | |
14650 | mips_fix_loongson2f_jump = FALSE; | |
14651 | break; | |
14652 | ||
14653 | case OPTION_FIX_LOONGSON2F_NOP: | |
14654 | mips_fix_loongson2f_nop = TRUE; | |
14655 | break; | |
14656 | ||
14657 | case OPTION_NO_FIX_LOONGSON2F_NOP: | |
14658 | mips_fix_loongson2f_nop = FALSE; | |
14659 | break; | |
14660 | ||
d766e8ec RS |
14661 | case OPTION_FIX_VR4120: |
14662 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
14663 | break; |
14664 | ||
d766e8ec RS |
14665 | case OPTION_NO_FIX_VR4120: |
14666 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
14667 | break; |
14668 | ||
7d8e00cf RS |
14669 | case OPTION_FIX_VR4130: |
14670 | mips_fix_vr4130 = 1; | |
14671 | break; | |
14672 | ||
14673 | case OPTION_NO_FIX_VR4130: | |
14674 | mips_fix_vr4130 = 0; | |
14675 | break; | |
14676 | ||
d954098f DD |
14677 | case OPTION_FIX_CN63XXP1: |
14678 | mips_fix_cn63xxp1 = TRUE; | |
14679 | break; | |
14680 | ||
14681 | case OPTION_NO_FIX_CN63XXP1: | |
14682 | mips_fix_cn63xxp1 = FALSE; | |
14683 | break; | |
14684 | ||
4a6a3df4 AO |
14685 | case OPTION_RELAX_BRANCH: |
14686 | mips_relax_branch = 1; | |
14687 | break; | |
14688 | ||
14689 | case OPTION_NO_RELAX_BRANCH: | |
14690 | mips_relax_branch = 0; | |
14691 | break; | |
14692 | ||
aa6975fb ILT |
14693 | case OPTION_MSHARED: |
14694 | mips_in_shared = TRUE; | |
14695 | break; | |
14696 | ||
14697 | case OPTION_MNO_SHARED: | |
14698 | mips_in_shared = FALSE; | |
14699 | break; | |
14700 | ||
aed1a261 RS |
14701 | case OPTION_MSYM32: |
14702 | mips_opts.sym32 = TRUE; | |
14703 | break; | |
14704 | ||
14705 | case OPTION_MNO_SYM32: | |
14706 | mips_opts.sym32 = FALSE; | |
14707 | break; | |
14708 | ||
0f074f60 | 14709 | #ifdef OBJ_ELF |
252b5132 RH |
14710 | /* When generating ELF code, we permit -KPIC and -call_shared to |
14711 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
14712 | intended to be compatible with Irix 5. */ | |
14713 | case OPTION_CALL_SHARED: | |
f43abd2b | 14714 | if (!IS_ELF) |
252b5132 RH |
14715 | { |
14716 | as_bad (_("-call_shared is supported only for ELF format")); | |
14717 | return 0; | |
14718 | } | |
14719 | mips_pic = SVR4_PIC; | |
143d77c5 | 14720 | mips_abicalls = TRUE; |
252b5132 RH |
14721 | break; |
14722 | ||
861fb55a DJ |
14723 | case OPTION_CALL_NONPIC: |
14724 | if (!IS_ELF) | |
14725 | { | |
14726 | as_bad (_("-call_nonpic is supported only for ELF format")); | |
14727 | return 0; | |
14728 | } | |
14729 | mips_pic = NO_PIC; | |
14730 | mips_abicalls = TRUE; | |
14731 | break; | |
14732 | ||
252b5132 | 14733 | case OPTION_NON_SHARED: |
f43abd2b | 14734 | if (!IS_ELF) |
252b5132 RH |
14735 | { |
14736 | as_bad (_("-non_shared is supported only for ELF format")); | |
14737 | return 0; | |
14738 | } | |
14739 | mips_pic = NO_PIC; | |
143d77c5 | 14740 | mips_abicalls = FALSE; |
252b5132 RH |
14741 | break; |
14742 | ||
44075ae2 TS |
14743 | /* The -xgot option tells the assembler to use 32 bit offsets |
14744 | when accessing the got in SVR4_PIC mode. It is for Irix | |
252b5132 RH |
14745 | compatibility. */ |
14746 | case OPTION_XGOT: | |
14747 | mips_big_got = 1; | |
14748 | break; | |
0f074f60 | 14749 | #endif /* OBJ_ELF */ |
252b5132 RH |
14750 | |
14751 | case 'G': | |
6caf9ef4 TS |
14752 | g_switch_value = atoi (arg); |
14753 | g_switch_seen = 1; | |
252b5132 RH |
14754 | break; |
14755 | ||
34ba82a8 TS |
14756 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
14757 | and -mabi=64. */ | |
252b5132 | 14758 | case OPTION_32: |
23fce1e3 NC |
14759 | if (IS_ELF) |
14760 | mips_abi = O32_ABI; | |
14761 | /* We silently ignore -32 for non-ELF targets. This greatly | |
14762 | simplifies the construction of the MIPS GAS test cases. */ | |
252b5132 RH |
14763 | break; |
14764 | ||
23fce1e3 | 14765 | #ifdef OBJ_ELF |
e013f690 | 14766 | case OPTION_N32: |
f43abd2b | 14767 | if (!IS_ELF) |
34ba82a8 TS |
14768 | { |
14769 | as_bad (_("-n32 is supported for ELF format only")); | |
14770 | return 0; | |
14771 | } | |
316f5878 | 14772 | mips_abi = N32_ABI; |
e013f690 | 14773 | break; |
252b5132 | 14774 | |
e013f690 | 14775 | case OPTION_64: |
f43abd2b | 14776 | if (!IS_ELF) |
34ba82a8 TS |
14777 | { |
14778 | as_bad (_("-64 is supported for ELF format only")); | |
14779 | return 0; | |
14780 | } | |
316f5878 | 14781 | mips_abi = N64_ABI; |
f43abd2b | 14782 | if (!support_64bit_objects()) |
e013f690 | 14783 | as_fatal (_("No compiled in support for 64 bit object file format")); |
252b5132 | 14784 | break; |
ae948b86 | 14785 | #endif /* OBJ_ELF */ |
252b5132 | 14786 | |
c97ef257 | 14787 | case OPTION_GP32: |
a325df1d | 14788 | file_mips_gp32 = 1; |
c97ef257 AH |
14789 | break; |
14790 | ||
14791 | case OPTION_GP64: | |
a325df1d | 14792 | file_mips_gp32 = 0; |
c97ef257 | 14793 | break; |
252b5132 | 14794 | |
ca4e0257 | 14795 | case OPTION_FP32: |
a325df1d | 14796 | file_mips_fp32 = 1; |
316f5878 RS |
14797 | break; |
14798 | ||
14799 | case OPTION_FP64: | |
14800 | file_mips_fp32 = 0; | |
ca4e0257 RS |
14801 | break; |
14802 | ||
037b32b9 AN |
14803 | case OPTION_SINGLE_FLOAT: |
14804 | file_mips_single_float = 1; | |
14805 | break; | |
14806 | ||
14807 | case OPTION_DOUBLE_FLOAT: | |
14808 | file_mips_single_float = 0; | |
14809 | break; | |
14810 | ||
14811 | case OPTION_SOFT_FLOAT: | |
14812 | file_mips_soft_float = 1; | |
14813 | break; | |
14814 | ||
14815 | case OPTION_HARD_FLOAT: | |
14816 | file_mips_soft_float = 0; | |
14817 | break; | |
14818 | ||
ae948b86 | 14819 | #ifdef OBJ_ELF |
252b5132 | 14820 | case OPTION_MABI: |
f43abd2b | 14821 | if (!IS_ELF) |
34ba82a8 TS |
14822 | { |
14823 | as_bad (_("-mabi is supported for ELF format only")); | |
14824 | return 0; | |
14825 | } | |
e013f690 | 14826 | if (strcmp (arg, "32") == 0) |
316f5878 | 14827 | mips_abi = O32_ABI; |
e013f690 | 14828 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 14829 | mips_abi = O64_ABI; |
e013f690 | 14830 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 14831 | mips_abi = N32_ABI; |
e013f690 TS |
14832 | else if (strcmp (arg, "64") == 0) |
14833 | { | |
316f5878 | 14834 | mips_abi = N64_ABI; |
e013f690 TS |
14835 | if (! support_64bit_objects()) |
14836 | as_fatal (_("No compiled in support for 64 bit object file " | |
14837 | "format")); | |
14838 | } | |
14839 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 14840 | mips_abi = EABI_ABI; |
e013f690 | 14841 | else |
da0e507f TS |
14842 | { |
14843 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
14844 | return 0; | |
14845 | } | |
252b5132 | 14846 | break; |
e013f690 | 14847 | #endif /* OBJ_ELF */ |
252b5132 | 14848 | |
6b76fefe | 14849 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 14850 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
14851 | break; |
14852 | ||
9ee72ff1 | 14853 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 14854 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
14855 | break; |
14856 | ||
ecb4347a DJ |
14857 | #ifdef OBJ_ELF |
14858 | case OPTION_MDEBUG: | |
b34976b6 | 14859 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
14860 | break; |
14861 | ||
14862 | case OPTION_NO_MDEBUG: | |
b34976b6 | 14863 | mips_flag_mdebug = FALSE; |
ecb4347a | 14864 | break; |
dcd410fe RO |
14865 | |
14866 | case OPTION_PDR: | |
14867 | mips_flag_pdr = TRUE; | |
14868 | break; | |
14869 | ||
14870 | case OPTION_NO_PDR: | |
14871 | mips_flag_pdr = FALSE; | |
14872 | break; | |
0a44bf69 RS |
14873 | |
14874 | case OPTION_MVXWORKS_PIC: | |
14875 | mips_pic = VXWORKS_PIC; | |
14876 | break; | |
ecb4347a DJ |
14877 | #endif /* OBJ_ELF */ |
14878 | ||
252b5132 RH |
14879 | default: |
14880 | return 0; | |
14881 | } | |
14882 | ||
c67a084a NC |
14883 | mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump; |
14884 | ||
252b5132 RH |
14885 | return 1; |
14886 | } | |
316f5878 RS |
14887 | \f |
14888 | /* Set up globals to generate code for the ISA or processor | |
14889 | described by INFO. */ | |
252b5132 | 14890 | |
252b5132 | 14891 | static void |
17a2f251 | 14892 | mips_set_architecture (const struct mips_cpu_info *info) |
252b5132 | 14893 | { |
316f5878 | 14894 | if (info != 0) |
252b5132 | 14895 | { |
fef14a42 TS |
14896 | file_mips_arch = info->cpu; |
14897 | mips_opts.arch = info->cpu; | |
316f5878 | 14898 | mips_opts.isa = info->isa; |
252b5132 | 14899 | } |
252b5132 RH |
14900 | } |
14901 | ||
252b5132 | 14902 | |
316f5878 | 14903 | /* Likewise for tuning. */ |
252b5132 | 14904 | |
316f5878 | 14905 | static void |
17a2f251 | 14906 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
14907 | { |
14908 | if (info != 0) | |
fef14a42 | 14909 | mips_tune = info->cpu; |
316f5878 | 14910 | } |
80cc45a5 | 14911 | |
34ba82a8 | 14912 | |
252b5132 | 14913 | void |
17a2f251 | 14914 | mips_after_parse_args (void) |
e9670677 | 14915 | { |
fef14a42 TS |
14916 | const struct mips_cpu_info *arch_info = 0; |
14917 | const struct mips_cpu_info *tune_info = 0; | |
14918 | ||
e9670677 | 14919 | /* GP relative stuff not working for PE */ |
6caf9ef4 | 14920 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
e9670677 | 14921 | { |
6caf9ef4 | 14922 | if (g_switch_seen && g_switch_value != 0) |
e9670677 MR |
14923 | as_bad (_("-G not supported in this configuration.")); |
14924 | g_switch_value = 0; | |
14925 | } | |
14926 | ||
cac012d6 AO |
14927 | if (mips_abi == NO_ABI) |
14928 | mips_abi = MIPS_DEFAULT_ABI; | |
14929 | ||
22923709 RS |
14930 | /* The following code determines the architecture and register size. |
14931 | Similar code was added to GCC 3.3 (see override_options() in | |
14932 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
14933 | as much as possible. */ | |
e9670677 | 14934 | |
316f5878 | 14935 | if (mips_arch_string != 0) |
fef14a42 | 14936 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 14937 | |
316f5878 | 14938 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 14939 | { |
316f5878 | 14940 | /* Handle -mipsN. At this point, file_mips_isa contains the |
fef14a42 | 14941 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 14942 | the -march selection (if any). */ |
fef14a42 | 14943 | if (arch_info != 0) |
e9670677 | 14944 | { |
316f5878 RS |
14945 | /* -march takes precedence over -mipsN, since it is more descriptive. |
14946 | There's no harm in specifying both as long as the ISA levels | |
14947 | are the same. */ | |
fef14a42 | 14948 | if (file_mips_isa != arch_info->isa) |
316f5878 RS |
14949 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), |
14950 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
fef14a42 | 14951 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 14952 | } |
316f5878 | 14953 | else |
fef14a42 | 14954 | arch_info = mips_cpu_info_from_isa (file_mips_isa); |
e9670677 MR |
14955 | } |
14956 | ||
fef14a42 TS |
14957 | if (arch_info == 0) |
14958 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
e9670677 | 14959 | |
fef14a42 | 14960 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
20203fb9 | 14961 | as_bad (_("-march=%s is not compatible with the selected ABI"), |
fef14a42 TS |
14962 | arch_info->name); |
14963 | ||
14964 | mips_set_architecture (arch_info); | |
14965 | ||
14966 | /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ | |
14967 | if (mips_tune_string != 0) | |
14968 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 14969 | |
fef14a42 TS |
14970 | if (tune_info == 0) |
14971 | mips_set_tune (arch_info); | |
14972 | else | |
14973 | mips_set_tune (tune_info); | |
e9670677 | 14974 | |
316f5878 | 14975 | if (file_mips_gp32 >= 0) |
e9670677 | 14976 | { |
316f5878 RS |
14977 | /* The user specified the size of the integer registers. Make sure |
14978 | it agrees with the ABI and ISA. */ | |
14979 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
14980 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
14981 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
14982 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
14983 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
14984 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
14985 | } |
14986 | else | |
14987 | { | |
316f5878 RS |
14988 | /* Infer the integer register size from the ABI and processor. |
14989 | Restrict ourselves to 32-bit registers if that's all the | |
14990 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
14991 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
14992 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
14993 | } |
14994 | ||
ad3fea08 TS |
14995 | switch (file_mips_fp32) |
14996 | { | |
14997 | default: | |
14998 | case -1: | |
14999 | /* No user specified float register size. | |
15000 | ??? GAS treats single-float processors as though they had 64-bit | |
15001 | float registers (although it complains when double-precision | |
15002 | instructions are used). As things stand, saying they have 32-bit | |
15003 | registers would lead to spurious "register must be even" messages. | |
15004 | So here we assume float registers are never smaller than the | |
15005 | integer ones. */ | |
15006 | if (file_mips_gp32 == 0) | |
15007 | /* 64-bit integer registers implies 64-bit float registers. */ | |
15008 | file_mips_fp32 = 0; | |
15009 | else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0) | |
15010 | && ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
15011 | /* -mips3d and -mdmx imply 64-bit float registers, if possible. */ | |
15012 | file_mips_fp32 = 0; | |
15013 | else | |
15014 | /* 32-bit float registers. */ | |
15015 | file_mips_fp32 = 1; | |
15016 | break; | |
15017 | ||
15018 | /* The user specified the size of the float registers. Check if it | |
15019 | agrees with the ABI and ISA. */ | |
15020 | case 0: | |
15021 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
15022 | as_bad (_("-mfp64 used with a 32-bit fpu")); | |
15023 | else if (ABI_NEEDS_32BIT_REGS (mips_abi) | |
15024 | && !ISA_HAS_MXHC1 (mips_opts.isa)) | |
15025 | as_warn (_("-mfp64 used with a 32-bit ABI")); | |
15026 | break; | |
15027 | case 1: | |
15028 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
15029 | as_warn (_("-mfp32 used with a 64-bit ABI")); | |
15030 | break; | |
15031 | } | |
e9670677 | 15032 | |
316f5878 | 15033 | /* End of GCC-shared inference code. */ |
e9670677 | 15034 | |
17a2f251 TS |
15035 | /* This flag is set when we have a 64-bit capable CPU but use only |
15036 | 32-bit wide registers. Note that EABI does not use it. */ | |
15037 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) | |
15038 | && ((mips_abi == NO_ABI && file_mips_gp32 == 1) | |
15039 | || mips_abi == O32_ABI)) | |
316f5878 | 15040 | mips_32bitmode = 1; |
e9670677 MR |
15041 | |
15042 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
15043 | as_bad (_("trap exception not supported at ISA 1")); | |
15044 | ||
e9670677 MR |
15045 | /* If the selected architecture includes support for ASEs, enable |
15046 | generation of code for them. */ | |
a4672219 | 15047 | if (mips_opts.mips16 == -1) |
fef14a42 | 15048 | mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; |
df58fc94 RS |
15049 | if (mips_opts.micromips == -1) |
15050 | mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0; | |
ffdefa66 | 15051 | if (mips_opts.ase_mips3d == -1) |
65263ce3 | 15052 | mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D) |
ad3fea08 TS |
15053 | && file_mips_fp32 == 0) ? 1 : 0; |
15054 | if (mips_opts.ase_mips3d && file_mips_fp32 == 1) | |
15055 | as_bad (_("-mfp32 used with -mips3d")); | |
15056 | ||
ffdefa66 | 15057 | if (mips_opts.ase_mdmx == -1) |
65263ce3 | 15058 | mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX) |
ad3fea08 TS |
15059 | && file_mips_fp32 == 0) ? 1 : 0; |
15060 | if (mips_opts.ase_mdmx && file_mips_fp32 == 1) | |
15061 | as_bad (_("-mfp32 used with -mdmx")); | |
15062 | ||
15063 | if (mips_opts.ase_smartmips == -1) | |
15064 | mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0; | |
15065 | if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS) | |
20203fb9 NC |
15066 | as_warn (_("%s ISA does not support SmartMIPS"), |
15067 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
ad3fea08 | 15068 | |
74cd071d | 15069 | if (mips_opts.ase_dsp == -1) |
ad3fea08 TS |
15070 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; |
15071 | if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE) | |
20203fb9 NC |
15072 | as_warn (_("%s ISA does not support DSP ASE"), |
15073 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
ad3fea08 | 15074 | |
8b082fb1 TS |
15075 | if (mips_opts.ase_dspr2 == -1) |
15076 | { | |
15077 | mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0; | |
15078 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; | |
15079 | } | |
15080 | if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE) | |
20203fb9 NC |
15081 | as_warn (_("%s ISA does not support DSP R2 ASE"), |
15082 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
8b082fb1 | 15083 | |
ef2e4d86 | 15084 | if (mips_opts.ase_mt == -1) |
ad3fea08 TS |
15085 | mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0; |
15086 | if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE) | |
20203fb9 NC |
15087 | as_warn (_("%s ISA does not support MT ASE"), |
15088 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
e9670677 | 15089 | |
dec0624d MR |
15090 | if (mips_opts.ase_mcu == -1) |
15091 | mips_opts.ase_mcu = (arch_info->flags & MIPS_CPU_ASE_MCU) ? 1 : 0; | |
15092 | if (mips_opts.ase_mcu && !ISA_SUPPORTS_MCU_ASE) | |
15093 | as_warn (_("%s ISA does not support MCU ASE"), | |
15094 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
15095 | ||
e9670677 | 15096 | file_mips_isa = mips_opts.isa; |
e9670677 MR |
15097 | file_ase_mips3d = mips_opts.ase_mips3d; |
15098 | file_ase_mdmx = mips_opts.ase_mdmx; | |
e16bfa71 | 15099 | file_ase_smartmips = mips_opts.ase_smartmips; |
74cd071d | 15100 | file_ase_dsp = mips_opts.ase_dsp; |
8b082fb1 | 15101 | file_ase_dspr2 = mips_opts.ase_dspr2; |
ef2e4d86 | 15102 | file_ase_mt = mips_opts.ase_mt; |
e9670677 MR |
15103 | mips_opts.gp32 = file_mips_gp32; |
15104 | mips_opts.fp32 = file_mips_fp32; | |
037b32b9 AN |
15105 | mips_opts.soft_float = file_mips_soft_float; |
15106 | mips_opts.single_float = file_mips_single_float; | |
e9670677 | 15107 | |
ecb4347a DJ |
15108 | if (mips_flag_mdebug < 0) |
15109 | { | |
15110 | #ifdef OBJ_MAYBE_ECOFF | |
15111 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) | |
15112 | mips_flag_mdebug = 1; | |
15113 | else | |
15114 | #endif /* OBJ_MAYBE_ECOFF */ | |
15115 | mips_flag_mdebug = 0; | |
15116 | } | |
e9670677 MR |
15117 | } |
15118 | \f | |
15119 | void | |
17a2f251 | 15120 | mips_init_after_args (void) |
252b5132 RH |
15121 | { |
15122 | /* initialize opcodes */ | |
15123 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 15124 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
15125 | } |
15126 | ||
15127 | long | |
17a2f251 | 15128 | md_pcrel_from (fixS *fixP) |
252b5132 | 15129 | { |
a7ebbfdf TS |
15130 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
15131 | switch (fixP->fx_r_type) | |
15132 | { | |
df58fc94 RS |
15133 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15134 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15135 | /* Return the address of the delay slot. */ | |
15136 | return addr + 2; | |
15137 | ||
15138 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15139 | case BFD_RELOC_MICROMIPS_JMP: | |
a7ebbfdf TS |
15140 | case BFD_RELOC_16_PCREL_S2: |
15141 | case BFD_RELOC_MIPS_JMP: | |
15142 | /* Return the address of the delay slot. */ | |
15143 | return addr + 4; | |
df58fc94 | 15144 | |
a7ebbfdf | 15145 | default: |
58ea3d6a | 15146 | /* We have no relocation type for PC relative MIPS16 instructions. */ |
64817874 TS |
15147 | if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg) |
15148 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15149 | _("PC relative MIPS16 instruction references a different section")); | |
a7ebbfdf TS |
15150 | return addr; |
15151 | } | |
252b5132 RH |
15152 | } |
15153 | ||
252b5132 RH |
15154 | /* This is called before the symbol table is processed. In order to |
15155 | work with gcc when using mips-tfile, we must keep all local labels. | |
15156 | However, in other cases, we want to discard them. If we were | |
15157 | called with -g, but we didn't see any debugging information, it may | |
15158 | mean that gcc is smuggling debugging information through to | |
15159 | mips-tfile, in which case we must generate all local labels. */ | |
15160 | ||
15161 | void | |
17a2f251 | 15162 | mips_frob_file_before_adjust (void) |
252b5132 RH |
15163 | { |
15164 | #ifndef NO_ECOFF_DEBUGGING | |
15165 | if (ECOFF_DEBUGGING | |
15166 | && mips_debug != 0 | |
15167 | && ! ecoff_debugging_seen) | |
15168 | flag_keep_locals = 1; | |
15169 | #endif | |
15170 | } | |
15171 | ||
3b91255e | 15172 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
55cf6793 | 15173 | the corresponding LO16 reloc. This is called before md_apply_fix and |
3b91255e RS |
15174 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit |
15175 | relocation operators. | |
15176 | ||
15177 | For our purposes, a %lo() expression matches a %got() or %hi() | |
15178 | expression if: | |
15179 | ||
15180 | (a) it refers to the same symbol; and | |
15181 | (b) the offset applied in the %lo() expression is no lower than | |
15182 | the offset applied in the %got() or %hi(). | |
15183 | ||
15184 | (b) allows us to cope with code like: | |
15185 | ||
15186 | lui $4,%hi(foo) | |
15187 | lh $4,%lo(foo+2)($4) | |
15188 | ||
15189 | ...which is legal on RELA targets, and has a well-defined behaviour | |
15190 | if the user knows that adding 2 to "foo" will not induce a carry to | |
15191 | the high 16 bits. | |
15192 | ||
15193 | When several %lo()s match a particular %got() or %hi(), we use the | |
15194 | following rules to distinguish them: | |
15195 | ||
15196 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
15197 | higher offsets. | |
15198 | ||
15199 | (2) %lo()s with no matching %got() or %hi() are better than those | |
15200 | that already have a matching %got() or %hi(). | |
15201 | ||
15202 | (3) later %lo()s are better than earlier %lo()s. | |
15203 | ||
15204 | These rules are applied in order. | |
15205 | ||
15206 | (1) means, among other things, that %lo()s with identical offsets are | |
15207 | chosen if they exist. | |
15208 | ||
15209 | (2) means that we won't associate several high-part relocations with | |
15210 | the same low-part relocation unless there's no alternative. Having | |
15211 | several high parts for the same low part is a GNU extension; this rule | |
15212 | allows careful users to avoid it. | |
15213 | ||
15214 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
15215 | with the last high-part relocation being at the front of the list. | |
15216 | It therefore makes sense to choose the last matching low-part | |
15217 | relocation, all other things being equal. It's also easier | |
15218 | to code that way. */ | |
252b5132 RH |
15219 | |
15220 | void | |
17a2f251 | 15221 | mips_frob_file (void) |
252b5132 RH |
15222 | { |
15223 | struct mips_hi_fixup *l; | |
35903be0 | 15224 | bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED; |
252b5132 RH |
15225 | |
15226 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
15227 | { | |
15228 | segment_info_type *seginfo; | |
3b91255e RS |
15229 | bfd_boolean matched_lo_p; |
15230 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 15231 | |
9c2799c2 | 15232 | gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 15233 | |
5919d012 RS |
15234 | /* If a GOT16 relocation turns out to be against a global symbol, |
15235 | there isn't supposed to be a matching LO. */ | |
738e5348 | 15236 | if (got16_reloc_p (l->fixp->fx_r_type) |
5919d012 RS |
15237 | && !pic_need_relax (l->fixp->fx_addsy, l->seg)) |
15238 | continue; | |
15239 | ||
15240 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
15241 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
15242 | continue; |
15243 | ||
252b5132 | 15244 | seginfo = seg_info (l->seg); |
252b5132 | 15245 | |
3b91255e RS |
15246 | /* Set HI_POS to the position of this relocation in the chain. |
15247 | Set LO_POS to the position of the chosen low-part relocation. | |
15248 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
15249 | relocation that matches an immediately-preceding high-part | |
15250 | relocation. */ | |
15251 | hi_pos = NULL; | |
15252 | lo_pos = NULL; | |
15253 | matched_lo_p = FALSE; | |
738e5348 | 15254 | looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type); |
35903be0 | 15255 | |
3b91255e RS |
15256 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) |
15257 | { | |
15258 | if (*pos == l->fixp) | |
15259 | hi_pos = pos; | |
15260 | ||
35903be0 | 15261 | if ((*pos)->fx_r_type == looking_for_rtype |
30cfc97a | 15262 | && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy) |
3b91255e RS |
15263 | && (*pos)->fx_offset >= l->fixp->fx_offset |
15264 | && (lo_pos == NULL | |
15265 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
15266 | || (!matched_lo_p | |
15267 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
15268 | lo_pos = pos; | |
15269 | ||
15270 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
15271 | && fixup_has_matching_lo_p (*pos)); | |
15272 | } | |
15273 | ||
15274 | /* If we found a match, remove the high-part relocation from its | |
15275 | current position and insert it before the low-part relocation. | |
15276 | Make the offsets match so that fixup_has_matching_lo_p() | |
15277 | will return true. | |
15278 | ||
15279 | We don't warn about unmatched high-part relocations since some | |
15280 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
15281 | instructions. */ | |
15282 | if (lo_pos != NULL) | |
15283 | { | |
15284 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
15285 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 15286 | { |
3b91255e RS |
15287 | *hi_pos = l->fixp->fx_next; |
15288 | l->fixp->fx_next = *lo_pos; | |
15289 | *lo_pos = l->fixp; | |
252b5132 | 15290 | } |
252b5132 RH |
15291 | } |
15292 | } | |
15293 | } | |
15294 | ||
3e722fb5 | 15295 | /* We may have combined relocations without symbols in the N32/N64 ABI. |
f6688943 | 15296 | We have to prevent gas from dropping them. */ |
252b5132 | 15297 | |
252b5132 | 15298 | int |
17a2f251 | 15299 | mips_force_relocation (fixS *fixp) |
252b5132 | 15300 | { |
ae6063d4 | 15301 | if (generic_force_reloc (fixp)) |
252b5132 RH |
15302 | return 1; |
15303 | ||
df58fc94 RS |
15304 | /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation, |
15305 | so that the linker relaxation can update targets. */ | |
15306 | if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
15307 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
15308 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1) | |
15309 | return 1; | |
15310 | ||
f6688943 TS |
15311 | if (HAVE_NEWABI |
15312 | && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr | |
15313 | && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB | |
738e5348 RS |
15314 | || hi16_reloc_p (fixp->fx_r_type) |
15315 | || lo16_reloc_p (fixp->fx_r_type))) | |
f6688943 TS |
15316 | return 1; |
15317 | ||
3e722fb5 | 15318 | return 0; |
252b5132 RH |
15319 | } |
15320 | ||
15321 | /* Apply a fixup to the object file. */ | |
15322 | ||
94f592af | 15323 | void |
55cf6793 | 15324 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 15325 | { |
874e8986 | 15326 | bfd_byte *buf; |
98aa84af | 15327 | long insn; |
a7ebbfdf | 15328 | reloc_howto_type *howto; |
252b5132 | 15329 | |
a7ebbfdf TS |
15330 | /* We ignore generic BFD relocations we don't know about. */ |
15331 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
15332 | if (! howto) | |
15333 | return; | |
65551fa4 | 15334 | |
df58fc94 RS |
15335 | gas_assert (fixP->fx_size == 2 |
15336 | || fixP->fx_size == 4 | |
90ecf173 MR |
15337 | || fixP->fx_r_type == BFD_RELOC_16 |
15338 | || fixP->fx_r_type == BFD_RELOC_64 | |
15339 | || fixP->fx_r_type == BFD_RELOC_CTOR | |
15340 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
df58fc94 | 15341 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB |
90ecf173 MR |
15342 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
15343 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY | |
15344 | || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64); | |
252b5132 | 15345 | |
a7ebbfdf | 15346 | buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); |
252b5132 | 15347 | |
df58fc94 RS |
15348 | gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2 |
15349 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
15350 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
15351 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
b1dca8ee RS |
15352 | |
15353 | /* Don't treat parts of a composite relocation as done. There are two | |
15354 | reasons for this: | |
15355 | ||
15356 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
15357 | should nevertheless be emitted if the first part is. | |
15358 | ||
15359 | (2) In normal usage, composite relocations are never assembly-time | |
15360 | constants. The easiest way of dealing with the pathological | |
15361 | exceptions is to generate a relocation against STN_UNDEF and | |
15362 | leave everything up to the linker. */ | |
3994f87e | 15363 | if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0) |
252b5132 RH |
15364 | fixP->fx_done = 1; |
15365 | ||
15366 | switch (fixP->fx_r_type) | |
15367 | { | |
3f98094e DJ |
15368 | case BFD_RELOC_MIPS_TLS_GD: |
15369 | case BFD_RELOC_MIPS_TLS_LDM: | |
741d6ea8 JM |
15370 | case BFD_RELOC_MIPS_TLS_DTPREL32: |
15371 | case BFD_RELOC_MIPS_TLS_DTPREL64: | |
3f98094e DJ |
15372 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: |
15373 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
15374 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
15375 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: | |
15376 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
df58fc94 RS |
15377 | case BFD_RELOC_MICROMIPS_TLS_GD: |
15378 | case BFD_RELOC_MICROMIPS_TLS_LDM: | |
15379 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16: | |
15380 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16: | |
15381 | case BFD_RELOC_MICROMIPS_TLS_GOTTPREL: | |
15382 | case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16: | |
15383 | case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16: | |
3f98094e DJ |
15384 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
15385 | /* fall through */ | |
15386 | ||
252b5132 | 15387 | case BFD_RELOC_MIPS_JMP: |
e369bcce TS |
15388 | case BFD_RELOC_MIPS_SHIFT5: |
15389 | case BFD_RELOC_MIPS_SHIFT6: | |
15390 | case BFD_RELOC_MIPS_GOT_DISP: | |
15391 | case BFD_RELOC_MIPS_GOT_PAGE: | |
15392 | case BFD_RELOC_MIPS_GOT_OFST: | |
15393 | case BFD_RELOC_MIPS_SUB: | |
15394 | case BFD_RELOC_MIPS_INSERT_A: | |
15395 | case BFD_RELOC_MIPS_INSERT_B: | |
15396 | case BFD_RELOC_MIPS_DELETE: | |
15397 | case BFD_RELOC_MIPS_HIGHEST: | |
15398 | case BFD_RELOC_MIPS_HIGHER: | |
15399 | case BFD_RELOC_MIPS_SCN_DISP: | |
15400 | case BFD_RELOC_MIPS_REL16: | |
15401 | case BFD_RELOC_MIPS_RELGOT: | |
15402 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
15403 | case BFD_RELOC_HI16: |
15404 | case BFD_RELOC_HI16_S: | |
cdf6fd85 | 15405 | case BFD_RELOC_GPREL16: |
252b5132 RH |
15406 | case BFD_RELOC_MIPS_LITERAL: |
15407 | case BFD_RELOC_MIPS_CALL16: | |
15408 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 15409 | case BFD_RELOC_GPREL32: |
252b5132 RH |
15410 | case BFD_RELOC_MIPS_GOT_HI16: |
15411 | case BFD_RELOC_MIPS_GOT_LO16: | |
15412 | case BFD_RELOC_MIPS_CALL_HI16: | |
15413 | case BFD_RELOC_MIPS_CALL_LO16: | |
15414 | case BFD_RELOC_MIPS16_GPREL: | |
738e5348 RS |
15415 | case BFD_RELOC_MIPS16_GOT16: |
15416 | case BFD_RELOC_MIPS16_CALL16: | |
d6f16593 MR |
15417 | case BFD_RELOC_MIPS16_HI16: |
15418 | case BFD_RELOC_MIPS16_HI16_S: | |
252b5132 | 15419 | case BFD_RELOC_MIPS16_JMP: |
df58fc94 RS |
15420 | case BFD_RELOC_MICROMIPS_JMP: |
15421 | case BFD_RELOC_MICROMIPS_GOT_DISP: | |
15422 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
15423 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
15424 | case BFD_RELOC_MICROMIPS_SUB: | |
15425 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
15426 | case BFD_RELOC_MICROMIPS_HIGHER: | |
15427 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
15428 | case BFD_RELOC_MICROMIPS_JALR: | |
15429 | case BFD_RELOC_MICROMIPS_HI16: | |
15430 | case BFD_RELOC_MICROMIPS_HI16_S: | |
15431 | case BFD_RELOC_MICROMIPS_GPREL16: | |
15432 | case BFD_RELOC_MICROMIPS_LITERAL: | |
15433 | case BFD_RELOC_MICROMIPS_CALL16: | |
15434 | case BFD_RELOC_MICROMIPS_GOT16: | |
15435 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
15436 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
15437 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
15438 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
54f4ddb3 | 15439 | /* Nothing needed to do. The value comes from the reloc entry. */ |
252b5132 RH |
15440 | break; |
15441 | ||
252b5132 RH |
15442 | case BFD_RELOC_64: |
15443 | /* This is handled like BFD_RELOC_32, but we output a sign | |
15444 | extended value if we are only 32 bits. */ | |
3e722fb5 | 15445 | if (fixP->fx_done) |
252b5132 RH |
15446 | { |
15447 | if (8 <= sizeof (valueT)) | |
2132e3a3 | 15448 | md_number_to_chars ((char *) buf, *valP, 8); |
252b5132 RH |
15449 | else |
15450 | { | |
a7ebbfdf | 15451 | valueT hiv; |
252b5132 | 15452 | |
a7ebbfdf | 15453 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
15454 | hiv = 0xffffffff; |
15455 | else | |
15456 | hiv = 0; | |
b215186b | 15457 | md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)), |
a7ebbfdf | 15458 | *valP, 4); |
b215186b | 15459 | md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)), |
a7ebbfdf | 15460 | hiv, 4); |
252b5132 RH |
15461 | } |
15462 | } | |
15463 | break; | |
15464 | ||
056350c6 | 15465 | case BFD_RELOC_RVA: |
252b5132 | 15466 | case BFD_RELOC_32: |
252b5132 RH |
15467 | case BFD_RELOC_16: |
15468 | /* If we are deleting this reloc entry, we must fill in the | |
54f4ddb3 TS |
15469 | value now. This can happen if we have a .word which is not |
15470 | resolved when it appears but is later defined. */ | |
252b5132 | 15471 | if (fixP->fx_done) |
54f4ddb3 | 15472 | md_number_to_chars ((char *) buf, *valP, fixP->fx_size); |
252b5132 RH |
15473 | break; |
15474 | ||
15475 | case BFD_RELOC_LO16: | |
d6f16593 | 15476 | case BFD_RELOC_MIPS16_LO16: |
df58fc94 | 15477 | case BFD_RELOC_MICROMIPS_LO16: |
3e722fb5 CD |
15478 | /* FIXME: Now that embedded-PIC is gone, some of this code/comment |
15479 | may be safe to remove, but if so it's not obvious. */ | |
252b5132 RH |
15480 | /* When handling an embedded PIC switch statement, we can wind |
15481 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
15482 | if (fixP->fx_done) | |
15483 | { | |
a7ebbfdf | 15484 | if (*valP + 0x8000 > 0xffff) |
252b5132 RH |
15485 | as_bad_where (fixP->fx_file, fixP->fx_line, |
15486 | _("relocation overflow")); | |
df58fc94 RS |
15487 | /* 32-bit microMIPS instructions are divided into two halfwords. |
15488 | Relocations always refer to the second halfword, regardless | |
15489 | of endianness. */ | |
15490 | if (target_big_endian || fixP->fx_r_type == BFD_RELOC_MICROMIPS_LO16) | |
252b5132 | 15491 | buf += 2; |
2132e3a3 | 15492 | md_number_to_chars ((char *) buf, *valP, 2); |
252b5132 RH |
15493 | } |
15494 | break; | |
15495 | ||
15496 | case BFD_RELOC_16_PCREL_S2: | |
a7ebbfdf | 15497 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 15498 | as_bad_where (fixP->fx_file, fixP->fx_line, |
bad36eac | 15499 | _("Branch to misaligned address (%lx)"), (long) *valP); |
cb56d3d3 | 15500 | |
54f4ddb3 TS |
15501 | /* We need to save the bits in the instruction since fixup_segment() |
15502 | might be deleting the relocation entry (i.e., a branch within | |
15503 | the current segment). */ | |
a7ebbfdf | 15504 | if (! fixP->fx_done) |
bb2d6cd7 | 15505 | break; |
252b5132 | 15506 | |
54f4ddb3 | 15507 | /* Update old instruction data. */ |
252b5132 RH |
15508 | if (target_big_endian) |
15509 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
15510 | else | |
15511 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
15512 | ||
a7ebbfdf TS |
15513 | if (*valP + 0x20000 <= 0x3ffff) |
15514 | { | |
15515 | insn |= (*valP >> 2) & 0xffff; | |
2132e3a3 | 15516 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
15517 | } |
15518 | else if (mips_pic == NO_PIC | |
15519 | && fixP->fx_done | |
15520 | && fixP->fx_frag->fr_address >= text_section->vma | |
15521 | && (fixP->fx_frag->fr_address | |
587aac4e | 15522 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
15523 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
15524 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
15525 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
15526 | { |
15527 | /* The branch offset is too large. If this is an | |
15528 | unconditional branch, and we are not generating PIC code, | |
15529 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
15530 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
15531 | insn = 0x0c000000; /* jal */ | |
252b5132 | 15532 | else |
a7ebbfdf TS |
15533 | insn = 0x08000000; /* j */ |
15534 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
15535 | fixP->fx_done = 0; | |
15536 | fixP->fx_addsy = section_symbol (text_section); | |
15537 | *valP += md_pcrel_from (fixP); | |
2132e3a3 | 15538 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
15539 | } |
15540 | else | |
15541 | { | |
15542 | /* If we got here, we have branch-relaxation disabled, | |
15543 | and there's nothing we can do to fix this instruction | |
15544 | without turning it into a longer sequence. */ | |
15545 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15546 | _("Branch out of range")); | |
252b5132 | 15547 | } |
252b5132 RH |
15548 | break; |
15549 | ||
df58fc94 RS |
15550 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15551 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15552 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15553 | /* We adjust the offset back to even. */ | |
15554 | if ((*valP & 0x1) != 0) | |
15555 | --(*valP); | |
15556 | ||
15557 | if (! fixP->fx_done) | |
15558 | break; | |
15559 | ||
15560 | /* Should never visit here, because we keep the relocation. */ | |
15561 | abort (); | |
15562 | break; | |
15563 | ||
252b5132 RH |
15564 | case BFD_RELOC_VTABLE_INHERIT: |
15565 | fixP->fx_done = 0; | |
15566 | if (fixP->fx_addsy | |
15567 | && !S_IS_DEFINED (fixP->fx_addsy) | |
15568 | && !S_IS_WEAK (fixP->fx_addsy)) | |
15569 | S_SET_WEAK (fixP->fx_addsy); | |
15570 | break; | |
15571 | ||
15572 | case BFD_RELOC_VTABLE_ENTRY: | |
15573 | fixP->fx_done = 0; | |
15574 | break; | |
15575 | ||
15576 | default: | |
15577 | internalError (); | |
15578 | } | |
a7ebbfdf TS |
15579 | |
15580 | /* Remember value for tc_gen_reloc. */ | |
15581 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
15582 | } |
15583 | ||
252b5132 | 15584 | static symbolS * |
17a2f251 | 15585 | get_symbol (void) |
252b5132 RH |
15586 | { |
15587 | int c; | |
15588 | char *name; | |
15589 | symbolS *p; | |
15590 | ||
15591 | name = input_line_pointer; | |
15592 | c = get_symbol_end (); | |
15593 | p = (symbolS *) symbol_find_or_make (name); | |
15594 | *input_line_pointer = c; | |
15595 | return p; | |
15596 | } | |
15597 | ||
742a56fe RS |
15598 | /* Align the current frag to a given power of two. If a particular |
15599 | fill byte should be used, FILL points to an integer that contains | |
15600 | that byte, otherwise FILL is null. | |
15601 | ||
15602 | The MIPS assembler also automatically adjusts any preceding | |
15603 | label. */ | |
252b5132 RH |
15604 | |
15605 | static void | |
742a56fe | 15606 | mips_align (int to, int *fill, symbolS *label) |
252b5132 | 15607 | { |
7d10b47d | 15608 | mips_emit_delays (); |
df58fc94 | 15609 | mips_record_compressed_mode (); |
742a56fe RS |
15610 | if (fill == NULL && subseg_text_p (now_seg)) |
15611 | frag_align_code (to, 0); | |
15612 | else | |
15613 | frag_align (to, fill ? *fill : 0, 0); | |
252b5132 RH |
15614 | record_alignment (now_seg, to); |
15615 | if (label != NULL) | |
15616 | { | |
9c2799c2 | 15617 | gas_assert (S_GET_SEGMENT (label) == now_seg); |
49309057 | 15618 | symbol_set_frag (label, frag_now); |
252b5132 RH |
15619 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
15620 | } | |
15621 | } | |
15622 | ||
15623 | /* Align to a given power of two. .align 0 turns off the automatic | |
15624 | alignment used by the data creating pseudo-ops. */ | |
15625 | ||
15626 | static void | |
17a2f251 | 15627 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 | 15628 | { |
742a56fe | 15629 | int temp, fill_value, *fill_ptr; |
49954fb4 | 15630 | long max_alignment = 28; |
252b5132 | 15631 | |
54f4ddb3 | 15632 | /* o Note that the assembler pulls down any immediately preceding label |
252b5132 | 15633 | to the aligned address. |
54f4ddb3 | 15634 | o It's not documented but auto alignment is reinstated by |
252b5132 | 15635 | a .align pseudo instruction. |
54f4ddb3 | 15636 | o Note also that after auto alignment is turned off the mips assembler |
252b5132 | 15637 | issues an error on attempt to assemble an improperly aligned data item. |
54f4ddb3 | 15638 | We don't. */ |
252b5132 RH |
15639 | |
15640 | temp = get_absolute_expression (); | |
15641 | if (temp > max_alignment) | |
15642 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
15643 | else if (temp < 0) | |
15644 | { | |
15645 | as_warn (_("Alignment negative: 0 assumed.")); | |
15646 | temp = 0; | |
15647 | } | |
15648 | if (*input_line_pointer == ',') | |
15649 | { | |
f9419b05 | 15650 | ++input_line_pointer; |
742a56fe RS |
15651 | fill_value = get_absolute_expression (); |
15652 | fill_ptr = &fill_value; | |
252b5132 RH |
15653 | } |
15654 | else | |
742a56fe | 15655 | fill_ptr = 0; |
252b5132 RH |
15656 | if (temp) |
15657 | { | |
a8dbcb85 TS |
15658 | segment_info_type *si = seg_info (now_seg); |
15659 | struct insn_label_list *l = si->label_list; | |
54f4ddb3 | 15660 | /* Auto alignment should be switched on by next section change. */ |
252b5132 | 15661 | auto_align = 1; |
742a56fe | 15662 | mips_align (temp, fill_ptr, l != NULL ? l->label : NULL); |
252b5132 RH |
15663 | } |
15664 | else | |
15665 | { | |
15666 | auto_align = 0; | |
15667 | } | |
15668 | ||
15669 | demand_empty_rest_of_line (); | |
15670 | } | |
15671 | ||
252b5132 | 15672 | static void |
17a2f251 | 15673 | s_change_sec (int sec) |
252b5132 RH |
15674 | { |
15675 | segT seg; | |
15676 | ||
252b5132 RH |
15677 | #ifdef OBJ_ELF |
15678 | /* The ELF backend needs to know that we are changing sections, so | |
15679 | that .previous works correctly. We could do something like check | |
b6ff326e | 15680 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
15681 | as it would not be appropriate to use it in the section changing |
15682 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
15683 | This should be cleaner, somehow. */ | |
f43abd2b TS |
15684 | if (IS_ELF) |
15685 | obj_elf_section_change_hook (); | |
252b5132 RH |
15686 | #endif |
15687 | ||
7d10b47d | 15688 | mips_emit_delays (); |
6a32d874 | 15689 | |
252b5132 RH |
15690 | switch (sec) |
15691 | { | |
15692 | case 't': | |
15693 | s_text (0); | |
15694 | break; | |
15695 | case 'd': | |
15696 | s_data (0); | |
15697 | break; | |
15698 | case 'b': | |
15699 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
15700 | demand_empty_rest_of_line (); | |
15701 | break; | |
15702 | ||
15703 | case 'r': | |
4d0d148d TS |
15704 | seg = subseg_new (RDATA_SECTION_NAME, |
15705 | (subsegT) get_absolute_expression ()); | |
f43abd2b | 15706 | if (IS_ELF) |
252b5132 | 15707 | { |
4d0d148d TS |
15708 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
15709 | | SEC_READONLY | SEC_RELOC | |
15710 | | SEC_DATA)); | |
c41e87e3 | 15711 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
4d0d148d | 15712 | record_alignment (seg, 4); |
252b5132 | 15713 | } |
4d0d148d | 15714 | demand_empty_rest_of_line (); |
252b5132 RH |
15715 | break; |
15716 | ||
15717 | case 's': | |
4d0d148d | 15718 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
f43abd2b | 15719 | if (IS_ELF) |
252b5132 | 15720 | { |
4d0d148d TS |
15721 | bfd_set_section_flags (stdoutput, seg, |
15722 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
c41e87e3 | 15723 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
4d0d148d | 15724 | record_alignment (seg, 4); |
252b5132 | 15725 | } |
4d0d148d TS |
15726 | demand_empty_rest_of_line (); |
15727 | break; | |
998b3c36 MR |
15728 | |
15729 | case 'B': | |
15730 | seg = subseg_new (".sbss", (subsegT) get_absolute_expression ()); | |
15731 | if (IS_ELF) | |
15732 | { | |
15733 | bfd_set_section_flags (stdoutput, seg, SEC_ALLOC); | |
15734 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
15735 | record_alignment (seg, 4); | |
15736 | } | |
15737 | demand_empty_rest_of_line (); | |
15738 | break; | |
252b5132 RH |
15739 | } |
15740 | ||
15741 | auto_align = 1; | |
15742 | } | |
b34976b6 | 15743 | |
cca86cc8 | 15744 | void |
17a2f251 | 15745 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 15746 | { |
7ed4a06a | 15747 | #ifdef OBJ_ELF |
cca86cc8 SC |
15748 | char *section_name; |
15749 | char c; | |
684022ea | 15750 | char next_c = 0; |
cca86cc8 SC |
15751 | int section_type; |
15752 | int section_flag; | |
15753 | int section_entry_size; | |
15754 | int section_alignment; | |
b34976b6 | 15755 | |
f43abd2b | 15756 | if (!IS_ELF) |
7ed4a06a TS |
15757 | return; |
15758 | ||
cca86cc8 SC |
15759 | section_name = input_line_pointer; |
15760 | c = get_symbol_end (); | |
a816d1ed AO |
15761 | if (c) |
15762 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 15763 | |
4cf0dd0d TS |
15764 | /* Do we have .section Name<,"flags">? */ |
15765 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 15766 | { |
4cf0dd0d TS |
15767 | /* just after name is now '\0'. */ |
15768 | *input_line_pointer = c; | |
cca86cc8 SC |
15769 | input_line_pointer = section_name; |
15770 | obj_elf_section (ignore); | |
15771 | return; | |
15772 | } | |
15773 | input_line_pointer++; | |
15774 | ||
15775 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
15776 | if (c == ',') | |
15777 | section_type = get_absolute_expression (); | |
15778 | else | |
15779 | section_type = 0; | |
15780 | if (*input_line_pointer++ == ',') | |
15781 | section_flag = get_absolute_expression (); | |
15782 | else | |
15783 | section_flag = 0; | |
15784 | if (*input_line_pointer++ == ',') | |
15785 | section_entry_size = get_absolute_expression (); | |
15786 | else | |
15787 | section_entry_size = 0; | |
15788 | if (*input_line_pointer++ == ',') | |
15789 | section_alignment = get_absolute_expression (); | |
15790 | else | |
15791 | section_alignment = 0; | |
87975d2a AM |
15792 | /* FIXME: really ignore? */ |
15793 | (void) section_alignment; | |
cca86cc8 | 15794 | |
a816d1ed AO |
15795 | section_name = xstrdup (section_name); |
15796 | ||
8ab8a5c8 RS |
15797 | /* When using the generic form of .section (as implemented by obj-elf.c), |
15798 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
15799 | traditionally had to fall back on the more common @progbits instead. | |
15800 | ||
15801 | There's nothing really harmful in this, since bfd will correct | |
15802 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
708587a4 | 15803 | means that, for backwards compatibility, the special_section entries |
8ab8a5c8 RS |
15804 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. |
15805 | ||
15806 | Even so, we shouldn't force users of the MIPS .section syntax to | |
15807 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
15808 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
15809 | generic type-checking code. */ | |
15810 | if (section_type == SHT_MIPS_DWARF) | |
15811 | section_type = SHT_PROGBITS; | |
15812 | ||
cca86cc8 SC |
15813 | obj_elf_change_section (section_name, section_type, section_flag, |
15814 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
15815 | |
15816 | if (now_seg->name != section_name) | |
15817 | free (section_name); | |
7ed4a06a | 15818 | #endif /* OBJ_ELF */ |
cca86cc8 | 15819 | } |
252b5132 RH |
15820 | |
15821 | void | |
17a2f251 | 15822 | mips_enable_auto_align (void) |
252b5132 RH |
15823 | { |
15824 | auto_align = 1; | |
15825 | } | |
15826 | ||
15827 | static void | |
17a2f251 | 15828 | s_cons (int log_size) |
252b5132 | 15829 | { |
a8dbcb85 TS |
15830 | segment_info_type *si = seg_info (now_seg); |
15831 | struct insn_label_list *l = si->label_list; | |
252b5132 RH |
15832 | symbolS *label; |
15833 | ||
a8dbcb85 | 15834 | label = l != NULL ? l->label : NULL; |
7d10b47d | 15835 | mips_emit_delays (); |
252b5132 RH |
15836 | if (log_size > 0 && auto_align) |
15837 | mips_align (log_size, 0, label); | |
252b5132 | 15838 | cons (1 << log_size); |
a1facbec | 15839 | mips_clear_insn_labels (); |
252b5132 RH |
15840 | } |
15841 | ||
15842 | static void | |
17a2f251 | 15843 | s_float_cons (int type) |
252b5132 | 15844 | { |
a8dbcb85 TS |
15845 | segment_info_type *si = seg_info (now_seg); |
15846 | struct insn_label_list *l = si->label_list; | |
252b5132 RH |
15847 | symbolS *label; |
15848 | ||
a8dbcb85 | 15849 | label = l != NULL ? l->label : NULL; |
252b5132 | 15850 | |
7d10b47d | 15851 | mips_emit_delays (); |
252b5132 RH |
15852 | |
15853 | if (auto_align) | |
49309057 ILT |
15854 | { |
15855 | if (type == 'd') | |
15856 | mips_align (3, 0, label); | |
15857 | else | |
15858 | mips_align (2, 0, label); | |
15859 | } | |
252b5132 | 15860 | |
252b5132 | 15861 | float_cons (type); |
a1facbec | 15862 | mips_clear_insn_labels (); |
252b5132 RH |
15863 | } |
15864 | ||
15865 | /* Handle .globl. We need to override it because on Irix 5 you are | |
15866 | permitted to say | |
15867 | .globl foo .text | |
15868 | where foo is an undefined symbol, to mean that foo should be | |
15869 | considered to be the address of a function. */ | |
15870 | ||
15871 | static void | |
17a2f251 | 15872 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
15873 | { |
15874 | char *name; | |
15875 | int c; | |
15876 | symbolS *symbolP; | |
15877 | flagword flag; | |
15878 | ||
8a06b769 | 15879 | do |
252b5132 | 15880 | { |
8a06b769 | 15881 | name = input_line_pointer; |
252b5132 | 15882 | c = get_symbol_end (); |
8a06b769 TS |
15883 | symbolP = symbol_find_or_make (name); |
15884 | S_SET_EXTERNAL (symbolP); | |
15885 | ||
252b5132 | 15886 | *input_line_pointer = c; |
8a06b769 | 15887 | SKIP_WHITESPACE (); |
252b5132 | 15888 | |
8a06b769 TS |
15889 | /* On Irix 5, every global symbol that is not explicitly labelled as |
15890 | being a function is apparently labelled as being an object. */ | |
15891 | flag = BSF_OBJECT; | |
252b5132 | 15892 | |
8a06b769 TS |
15893 | if (!is_end_of_line[(unsigned char) *input_line_pointer] |
15894 | && (*input_line_pointer != ',')) | |
15895 | { | |
15896 | char *secname; | |
15897 | asection *sec; | |
15898 | ||
15899 | secname = input_line_pointer; | |
15900 | c = get_symbol_end (); | |
15901 | sec = bfd_get_section_by_name (stdoutput, secname); | |
15902 | if (sec == NULL) | |
15903 | as_bad (_("%s: no such section"), secname); | |
15904 | *input_line_pointer = c; | |
15905 | ||
15906 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
15907 | flag = BSF_FUNCTION; | |
15908 | } | |
15909 | ||
15910 | symbol_get_bfdsym (symbolP)->flags |= flag; | |
15911 | ||
15912 | c = *input_line_pointer; | |
15913 | if (c == ',') | |
15914 | { | |
15915 | input_line_pointer++; | |
15916 | SKIP_WHITESPACE (); | |
15917 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
15918 | c = '\n'; | |
15919 | } | |
15920 | } | |
15921 | while (c == ','); | |
252b5132 | 15922 | |
252b5132 RH |
15923 | demand_empty_rest_of_line (); |
15924 | } | |
15925 | ||
15926 | static void | |
17a2f251 | 15927 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
15928 | { |
15929 | char *opt; | |
15930 | char c; | |
15931 | ||
15932 | opt = input_line_pointer; | |
15933 | c = get_symbol_end (); | |
15934 | ||
15935 | if (*opt == 'O') | |
15936 | { | |
15937 | /* FIXME: What does this mean? */ | |
15938 | } | |
15939 | else if (strncmp (opt, "pic", 3) == 0) | |
15940 | { | |
15941 | int i; | |
15942 | ||
15943 | i = atoi (opt + 3); | |
15944 | if (i == 0) | |
15945 | mips_pic = NO_PIC; | |
15946 | else if (i == 2) | |
143d77c5 | 15947 | { |
252b5132 | 15948 | mips_pic = SVR4_PIC; |
143d77c5 EC |
15949 | mips_abicalls = TRUE; |
15950 | } | |
252b5132 RH |
15951 | else |
15952 | as_bad (_(".option pic%d not supported"), i); | |
15953 | ||
4d0d148d | 15954 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
15955 | { |
15956 | if (g_switch_seen && g_switch_value != 0) | |
15957 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
15958 | g_switch_value = 0; | |
15959 | bfd_set_gp_size (stdoutput, 0); | |
15960 | } | |
15961 | } | |
15962 | else | |
15963 | as_warn (_("Unrecognized option \"%s\""), opt); | |
15964 | ||
15965 | *input_line_pointer = c; | |
15966 | demand_empty_rest_of_line (); | |
15967 | } | |
15968 | ||
15969 | /* This structure is used to hold a stack of .set values. */ | |
15970 | ||
e972090a NC |
15971 | struct mips_option_stack |
15972 | { | |
252b5132 RH |
15973 | struct mips_option_stack *next; |
15974 | struct mips_set_options options; | |
15975 | }; | |
15976 | ||
15977 | static struct mips_option_stack *mips_opts_stack; | |
15978 | ||
15979 | /* Handle the .set pseudo-op. */ | |
15980 | ||
15981 | static void | |
17a2f251 | 15982 | s_mipsset (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
15983 | { |
15984 | char *name = input_line_pointer, ch; | |
15985 | ||
15986 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 15987 | ++input_line_pointer; |
252b5132 RH |
15988 | ch = *input_line_pointer; |
15989 | *input_line_pointer = '\0'; | |
15990 | ||
15991 | if (strcmp (name, "reorder") == 0) | |
15992 | { | |
7d10b47d RS |
15993 | if (mips_opts.noreorder) |
15994 | end_noreorder (); | |
252b5132 RH |
15995 | } |
15996 | else if (strcmp (name, "noreorder") == 0) | |
15997 | { | |
7d10b47d RS |
15998 | if (!mips_opts.noreorder) |
15999 | start_noreorder (); | |
252b5132 | 16000 | } |
741fe287 MR |
16001 | else if (strncmp (name, "at=", 3) == 0) |
16002 | { | |
16003 | char *s = name + 3; | |
16004 | ||
16005 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at)) | |
16006 | as_bad (_("Unrecognized register name `%s'"), s); | |
16007 | } | |
252b5132 RH |
16008 | else if (strcmp (name, "at") == 0) |
16009 | { | |
741fe287 | 16010 | mips_opts.at = ATREG; |
252b5132 RH |
16011 | } |
16012 | else if (strcmp (name, "noat") == 0) | |
16013 | { | |
741fe287 | 16014 | mips_opts.at = ZERO; |
252b5132 RH |
16015 | } |
16016 | else if (strcmp (name, "macro") == 0) | |
16017 | { | |
16018 | mips_opts.warn_about_macros = 0; | |
16019 | } | |
16020 | else if (strcmp (name, "nomacro") == 0) | |
16021 | { | |
16022 | if (mips_opts.noreorder == 0) | |
16023 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
16024 | mips_opts.warn_about_macros = 1; | |
16025 | } | |
16026 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
16027 | { | |
16028 | mips_opts.nomove = 0; | |
16029 | } | |
16030 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
16031 | { | |
16032 | mips_opts.nomove = 1; | |
16033 | } | |
16034 | else if (strcmp (name, "bopt") == 0) | |
16035 | { | |
16036 | mips_opts.nobopt = 0; | |
16037 | } | |
16038 | else if (strcmp (name, "nobopt") == 0) | |
16039 | { | |
16040 | mips_opts.nobopt = 1; | |
16041 | } | |
ad3fea08 TS |
16042 | else if (strcmp (name, "gp=default") == 0) |
16043 | mips_opts.gp32 = file_mips_gp32; | |
16044 | else if (strcmp (name, "gp=32") == 0) | |
16045 | mips_opts.gp32 = 1; | |
16046 | else if (strcmp (name, "gp=64") == 0) | |
16047 | { | |
16048 | if (!ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
20203fb9 | 16049 | as_warn (_("%s isa does not support 64-bit registers"), |
ad3fea08 TS |
16050 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16051 | mips_opts.gp32 = 0; | |
16052 | } | |
16053 | else if (strcmp (name, "fp=default") == 0) | |
16054 | mips_opts.fp32 = file_mips_fp32; | |
16055 | else if (strcmp (name, "fp=32") == 0) | |
16056 | mips_opts.fp32 = 1; | |
16057 | else if (strcmp (name, "fp=64") == 0) | |
16058 | { | |
16059 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
20203fb9 | 16060 | as_warn (_("%s isa does not support 64-bit floating point registers"), |
ad3fea08 TS |
16061 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16062 | mips_opts.fp32 = 0; | |
16063 | } | |
037b32b9 AN |
16064 | else if (strcmp (name, "softfloat") == 0) |
16065 | mips_opts.soft_float = 1; | |
16066 | else if (strcmp (name, "hardfloat") == 0) | |
16067 | mips_opts.soft_float = 0; | |
16068 | else if (strcmp (name, "singlefloat") == 0) | |
16069 | mips_opts.single_float = 1; | |
16070 | else if (strcmp (name, "doublefloat") == 0) | |
16071 | mips_opts.single_float = 0; | |
252b5132 RH |
16072 | else if (strcmp (name, "mips16") == 0 |
16073 | || strcmp (name, "MIPS-16") == 0) | |
df58fc94 RS |
16074 | { |
16075 | if (mips_opts.micromips == 1) | |
16076 | as_fatal (_("`mips16' cannot be used with `micromips'")); | |
16077 | mips_opts.mips16 = 1; | |
16078 | } | |
252b5132 RH |
16079 | else if (strcmp (name, "nomips16") == 0 |
16080 | || strcmp (name, "noMIPS-16") == 0) | |
16081 | mips_opts.mips16 = 0; | |
df58fc94 RS |
16082 | else if (strcmp (name, "micromips") == 0) |
16083 | { | |
16084 | if (mips_opts.mips16 == 1) | |
16085 | as_fatal (_("`micromips' cannot be used with `mips16'")); | |
16086 | mips_opts.micromips = 1; | |
16087 | } | |
16088 | else if (strcmp (name, "nomicromips") == 0) | |
16089 | mips_opts.micromips = 0; | |
e16bfa71 TS |
16090 | else if (strcmp (name, "smartmips") == 0) |
16091 | { | |
ad3fea08 | 16092 | if (!ISA_SUPPORTS_SMARTMIPS) |
20203fb9 | 16093 | as_warn (_("%s ISA does not support SmartMIPS ASE"), |
e16bfa71 TS |
16094 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16095 | mips_opts.ase_smartmips = 1; | |
16096 | } | |
16097 | else if (strcmp (name, "nosmartmips") == 0) | |
16098 | mips_opts.ase_smartmips = 0; | |
1f25f5d3 CD |
16099 | else if (strcmp (name, "mips3d") == 0) |
16100 | mips_opts.ase_mips3d = 1; | |
16101 | else if (strcmp (name, "nomips3d") == 0) | |
16102 | mips_opts.ase_mips3d = 0; | |
a4672219 TS |
16103 | else if (strcmp (name, "mdmx") == 0) |
16104 | mips_opts.ase_mdmx = 1; | |
16105 | else if (strcmp (name, "nomdmx") == 0) | |
16106 | mips_opts.ase_mdmx = 0; | |
74cd071d | 16107 | else if (strcmp (name, "dsp") == 0) |
ad3fea08 TS |
16108 | { |
16109 | if (!ISA_SUPPORTS_DSP_ASE) | |
20203fb9 | 16110 | as_warn (_("%s ISA does not support DSP ASE"), |
ad3fea08 TS |
16111 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16112 | mips_opts.ase_dsp = 1; | |
8b082fb1 | 16113 | mips_opts.ase_dspr2 = 0; |
ad3fea08 | 16114 | } |
74cd071d | 16115 | else if (strcmp (name, "nodsp") == 0) |
8b082fb1 TS |
16116 | { |
16117 | mips_opts.ase_dsp = 0; | |
16118 | mips_opts.ase_dspr2 = 0; | |
16119 | } | |
16120 | else if (strcmp (name, "dspr2") == 0) | |
16121 | { | |
16122 | if (!ISA_SUPPORTS_DSPR2_ASE) | |
20203fb9 | 16123 | as_warn (_("%s ISA does not support DSP R2 ASE"), |
8b082fb1 TS |
16124 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16125 | mips_opts.ase_dspr2 = 1; | |
16126 | mips_opts.ase_dsp = 1; | |
16127 | } | |
16128 | else if (strcmp (name, "nodspr2") == 0) | |
16129 | { | |
16130 | mips_opts.ase_dspr2 = 0; | |
16131 | mips_opts.ase_dsp = 0; | |
16132 | } | |
ef2e4d86 | 16133 | else if (strcmp (name, "mt") == 0) |
ad3fea08 TS |
16134 | { |
16135 | if (!ISA_SUPPORTS_MT_ASE) | |
20203fb9 | 16136 | as_warn (_("%s ISA does not support MT ASE"), |
ad3fea08 TS |
16137 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16138 | mips_opts.ase_mt = 1; | |
16139 | } | |
ef2e4d86 CF |
16140 | else if (strcmp (name, "nomt") == 0) |
16141 | mips_opts.ase_mt = 0; | |
dec0624d MR |
16142 | else if (strcmp (name, "mcu") == 0) |
16143 | mips_opts.ase_mcu = 1; | |
16144 | else if (strcmp (name, "nomcu") == 0) | |
16145 | mips_opts.ase_mcu = 0; | |
1a2c1fad | 16146 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 16147 | { |
af7ee8bf | 16148 | int reset = 0; |
252b5132 | 16149 | |
1a2c1fad CD |
16150 | /* Permit the user to change the ISA and architecture on the fly. |
16151 | Needless to say, misuse can cause serious problems. */ | |
81a21e38 | 16152 | if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) |
af7ee8bf CD |
16153 | { |
16154 | reset = 1; | |
16155 | mips_opts.isa = file_mips_isa; | |
1a2c1fad | 16156 | mips_opts.arch = file_mips_arch; |
1a2c1fad CD |
16157 | } |
16158 | else if (strncmp (name, "arch=", 5) == 0) | |
16159 | { | |
16160 | const struct mips_cpu_info *p; | |
16161 | ||
16162 | p = mips_parse_cpu("internal use", name + 5); | |
16163 | if (!p) | |
16164 | as_bad (_("unknown architecture %s"), name + 5); | |
16165 | else | |
16166 | { | |
16167 | mips_opts.arch = p->cpu; | |
16168 | mips_opts.isa = p->isa; | |
16169 | } | |
16170 | } | |
81a21e38 TS |
16171 | else if (strncmp (name, "mips", 4) == 0) |
16172 | { | |
16173 | const struct mips_cpu_info *p; | |
16174 | ||
16175 | p = mips_parse_cpu("internal use", name); | |
16176 | if (!p) | |
16177 | as_bad (_("unknown ISA level %s"), name + 4); | |
16178 | else | |
16179 | { | |
16180 | mips_opts.arch = p->cpu; | |
16181 | mips_opts.isa = p->isa; | |
16182 | } | |
16183 | } | |
af7ee8bf | 16184 | else |
81a21e38 | 16185 | as_bad (_("unknown ISA or architecture %s"), name); |
af7ee8bf CD |
16186 | |
16187 | switch (mips_opts.isa) | |
98d3f06f KH |
16188 | { |
16189 | case 0: | |
98d3f06f | 16190 | break; |
af7ee8bf CD |
16191 | case ISA_MIPS1: |
16192 | case ISA_MIPS2: | |
16193 | case ISA_MIPS32: | |
16194 | case ISA_MIPS32R2: | |
98d3f06f KH |
16195 | mips_opts.gp32 = 1; |
16196 | mips_opts.fp32 = 1; | |
16197 | break; | |
af7ee8bf CD |
16198 | case ISA_MIPS3: |
16199 | case ISA_MIPS4: | |
16200 | case ISA_MIPS5: | |
16201 | case ISA_MIPS64: | |
5f74bc13 | 16202 | case ISA_MIPS64R2: |
98d3f06f KH |
16203 | mips_opts.gp32 = 0; |
16204 | mips_opts.fp32 = 0; | |
16205 | break; | |
16206 | default: | |
16207 | as_bad (_("unknown ISA level %s"), name + 4); | |
16208 | break; | |
16209 | } | |
af7ee8bf | 16210 | if (reset) |
98d3f06f | 16211 | { |
af7ee8bf CD |
16212 | mips_opts.gp32 = file_mips_gp32; |
16213 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 16214 | } |
252b5132 RH |
16215 | } |
16216 | else if (strcmp (name, "autoextend") == 0) | |
16217 | mips_opts.noautoextend = 0; | |
16218 | else if (strcmp (name, "noautoextend") == 0) | |
16219 | mips_opts.noautoextend = 1; | |
16220 | else if (strcmp (name, "push") == 0) | |
16221 | { | |
16222 | struct mips_option_stack *s; | |
16223 | ||
16224 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
16225 | s->next = mips_opts_stack; | |
16226 | s->options = mips_opts; | |
16227 | mips_opts_stack = s; | |
16228 | } | |
16229 | else if (strcmp (name, "pop") == 0) | |
16230 | { | |
16231 | struct mips_option_stack *s; | |
16232 | ||
16233 | s = mips_opts_stack; | |
16234 | if (s == NULL) | |
16235 | as_bad (_(".set pop with no .set push")); | |
16236 | else | |
16237 | { | |
16238 | /* If we're changing the reorder mode we need to handle | |
16239 | delay slots correctly. */ | |
16240 | if (s->options.noreorder && ! mips_opts.noreorder) | |
7d10b47d | 16241 | start_noreorder (); |
252b5132 | 16242 | else if (! s->options.noreorder && mips_opts.noreorder) |
7d10b47d | 16243 | end_noreorder (); |
252b5132 RH |
16244 | |
16245 | mips_opts = s->options; | |
16246 | mips_opts_stack = s->next; | |
16247 | free (s); | |
16248 | } | |
16249 | } | |
aed1a261 RS |
16250 | else if (strcmp (name, "sym32") == 0) |
16251 | mips_opts.sym32 = TRUE; | |
16252 | else if (strcmp (name, "nosym32") == 0) | |
16253 | mips_opts.sym32 = FALSE; | |
e6559e01 JM |
16254 | else if (strchr (name, ',')) |
16255 | { | |
16256 | /* Generic ".set" directive; use the generic handler. */ | |
16257 | *input_line_pointer = ch; | |
16258 | input_line_pointer = name; | |
16259 | s_set (0); | |
16260 | return; | |
16261 | } | |
252b5132 RH |
16262 | else |
16263 | { | |
16264 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
16265 | } | |
16266 | *input_line_pointer = ch; | |
16267 | demand_empty_rest_of_line (); | |
16268 | } | |
16269 | ||
16270 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
16271 | .option pic2. It means to generate SVR4 PIC calls. */ | |
16272 | ||
16273 | static void | |
17a2f251 | 16274 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16275 | { |
16276 | mips_pic = SVR4_PIC; | |
143d77c5 | 16277 | mips_abicalls = TRUE; |
4d0d148d TS |
16278 | |
16279 | if (g_switch_seen && g_switch_value != 0) | |
16280 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
16281 | g_switch_value = 0; | |
16282 | ||
252b5132 RH |
16283 | bfd_set_gp_size (stdoutput, 0); |
16284 | demand_empty_rest_of_line (); | |
16285 | } | |
16286 | ||
16287 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
16288 | PIC code. It sets the $gp register for the function based on the | |
16289 | function address, which is in the register named in the argument. | |
16290 | This uses a relocation against _gp_disp, which is handled specially | |
16291 | by the linker. The result is: | |
16292 | lui $gp,%hi(_gp_disp) | |
16293 | addiu $gp,$gp,%lo(_gp_disp) | |
16294 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
16295 | The .cpload argument is normally $25 == $t9. |
16296 | ||
16297 | The -mno-shared option changes this to: | |
bbe506e8 TS |
16298 | lui $gp,%hi(__gnu_local_gp) |
16299 | addiu $gp,$gp,%lo(__gnu_local_gp) | |
aa6975fb ILT |
16300 | and the argument is ignored. This saves an instruction, but the |
16301 | resulting code is not position independent; it uses an absolute | |
bbe506e8 TS |
16302 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
16303 | can go into an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
16304 | |
16305 | static void | |
17a2f251 | 16306 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16307 | { |
16308 | expressionS ex; | |
aa6975fb ILT |
16309 | int reg; |
16310 | int in_shared; | |
252b5132 | 16311 | |
6478892d TS |
16312 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
16313 | .cpload is ignored. */ | |
16314 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
16315 | { |
16316 | s_ignore (0); | |
16317 | return; | |
16318 | } | |
16319 | ||
d3ecfc59 | 16320 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
16321 | if (mips_opts.noreorder == 0) |
16322 | as_warn (_(".cpload not in noreorder section")); | |
16323 | ||
aa6975fb ILT |
16324 | reg = tc_get_register (0); |
16325 | ||
16326 | /* If we need to produce a 64-bit address, we are better off using | |
16327 | the default instruction sequence. */ | |
aed1a261 | 16328 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
aa6975fb | 16329 | |
252b5132 | 16330 | ex.X_op = O_symbol; |
bbe506e8 TS |
16331 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
16332 | "__gnu_local_gp"); | |
252b5132 RH |
16333 | ex.X_op_symbol = NULL; |
16334 | ex.X_add_number = 0; | |
16335 | ||
16336 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 16337 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 16338 | |
584892a6 | 16339 | macro_start (); |
67c0d1eb RS |
16340 | macro_build_lui (&ex, mips_gp_register); |
16341 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 16342 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
16343 | if (in_shared) |
16344 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
16345 | mips_gp_register, reg); | |
584892a6 | 16346 | macro_end (); |
252b5132 RH |
16347 | |
16348 | demand_empty_rest_of_line (); | |
16349 | } | |
16350 | ||
6478892d TS |
16351 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
16352 | .cpsetup $reg1, offset|$reg2, label | |
16353 | ||
16354 | If offset is given, this results in: | |
16355 | sd $gp, offset($sp) | |
956cd1d6 | 16356 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
16357 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
16358 | daddu $gp, $gp, $reg1 | |
6478892d TS |
16359 | |
16360 | If $reg2 is given, this results in: | |
16361 | daddu $reg2, $gp, $0 | |
956cd1d6 | 16362 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
16363 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
16364 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
16365 | $reg1 is normally $25 == $t9. |
16366 | ||
16367 | The -mno-shared option replaces the last three instructions with | |
16368 | lui $gp,%hi(_gp) | |
54f4ddb3 | 16369 | addiu $gp,$gp,%lo(_gp) */ |
aa6975fb | 16370 | |
6478892d | 16371 | static void |
17a2f251 | 16372 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16373 | { |
16374 | expressionS ex_off; | |
16375 | expressionS ex_sym; | |
16376 | int reg1; | |
6478892d | 16377 | |
8586fc66 | 16378 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
16379 | We also need NewABI support. */ |
16380 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16381 | { | |
16382 | s_ignore (0); | |
16383 | return; | |
16384 | } | |
16385 | ||
16386 | reg1 = tc_get_register (0); | |
16387 | SKIP_WHITESPACE (); | |
16388 | if (*input_line_pointer != ',') | |
16389 | { | |
16390 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
16391 | return; | |
16392 | } | |
16393 | else | |
80245285 | 16394 | ++input_line_pointer; |
6478892d TS |
16395 | SKIP_WHITESPACE (); |
16396 | if (*input_line_pointer == '$') | |
80245285 TS |
16397 | { |
16398 | mips_cpreturn_register = tc_get_register (0); | |
16399 | mips_cpreturn_offset = -1; | |
16400 | } | |
6478892d | 16401 | else |
80245285 TS |
16402 | { |
16403 | mips_cpreturn_offset = get_absolute_expression (); | |
16404 | mips_cpreturn_register = -1; | |
16405 | } | |
6478892d TS |
16406 | SKIP_WHITESPACE (); |
16407 | if (*input_line_pointer != ',') | |
16408 | { | |
16409 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
16410 | return; | |
16411 | } | |
16412 | else | |
f9419b05 | 16413 | ++input_line_pointer; |
6478892d | 16414 | SKIP_WHITESPACE (); |
f21f8242 | 16415 | expression (&ex_sym); |
6478892d | 16416 | |
584892a6 | 16417 | macro_start (); |
6478892d TS |
16418 | if (mips_cpreturn_register == -1) |
16419 | { | |
16420 | ex_off.X_op = O_constant; | |
16421 | ex_off.X_add_symbol = NULL; | |
16422 | ex_off.X_op_symbol = NULL; | |
16423 | ex_off.X_add_number = mips_cpreturn_offset; | |
16424 | ||
67c0d1eb | 16425 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 16426 | BFD_RELOC_LO16, SP); |
6478892d TS |
16427 | } |
16428 | else | |
67c0d1eb | 16429 | macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, |
17a2f251 | 16430 | mips_gp_register, 0); |
6478892d | 16431 | |
aed1a261 | 16432 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
aa6975fb | 16433 | { |
df58fc94 | 16434 | macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register, |
aa6975fb ILT |
16435 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, |
16436 | BFD_RELOC_HI16_S); | |
16437 | ||
16438 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
16439 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
16440 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
16441 | ||
16442 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
16443 | mips_gp_register, reg1); | |
16444 | } | |
16445 | else | |
16446 | { | |
16447 | expressionS ex; | |
16448 | ||
16449 | ex.X_op = O_symbol; | |
4184909a | 16450 | ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); |
aa6975fb ILT |
16451 | ex.X_op_symbol = NULL; |
16452 | ex.X_add_number = 0; | |
6e1304d8 | 16453 | |
aa6975fb ILT |
16454 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
16455 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
16456 | ||
16457 | macro_build_lui (&ex, mips_gp_register); | |
16458 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
16459 | mips_gp_register, BFD_RELOC_LO16); | |
16460 | } | |
f21f8242 | 16461 | |
584892a6 | 16462 | macro_end (); |
6478892d TS |
16463 | |
16464 | demand_empty_rest_of_line (); | |
16465 | } | |
16466 | ||
16467 | static void | |
17a2f251 | 16468 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16469 | { |
16470 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
54f4ddb3 | 16471 | .cplocal is ignored. */ |
6478892d TS |
16472 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) |
16473 | { | |
16474 | s_ignore (0); | |
16475 | return; | |
16476 | } | |
16477 | ||
16478 | mips_gp_register = tc_get_register (0); | |
85b51719 | 16479 | demand_empty_rest_of_line (); |
6478892d TS |
16480 | } |
16481 | ||
252b5132 RH |
16482 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
16483 | offset from $sp. The offset is remembered, and after making a PIC | |
16484 | call $gp is restored from that location. */ | |
16485 | ||
16486 | static void | |
17a2f251 | 16487 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16488 | { |
16489 | expressionS ex; | |
252b5132 | 16490 | |
6478892d | 16491 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 16492 | .cprestore is ignored. */ |
6478892d | 16493 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
16494 | { |
16495 | s_ignore (0); | |
16496 | return; | |
16497 | } | |
16498 | ||
16499 | mips_cprestore_offset = get_absolute_expression (); | |
7a621144 | 16500 | mips_cprestore_valid = 1; |
252b5132 RH |
16501 | |
16502 | ex.X_op = O_constant; | |
16503 | ex.X_add_symbol = NULL; | |
16504 | ex.X_op_symbol = NULL; | |
16505 | ex.X_add_number = mips_cprestore_offset; | |
16506 | ||
584892a6 | 16507 | macro_start (); |
67c0d1eb RS |
16508 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
16509 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 16510 | macro_end (); |
252b5132 RH |
16511 | |
16512 | demand_empty_rest_of_line (); | |
16513 | } | |
16514 | ||
6478892d | 16515 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 16516 | was given in the preceding .cpsetup, it results in: |
6478892d | 16517 | ld $gp, offset($sp) |
76b3015f | 16518 | |
6478892d | 16519 | If a register $reg2 was given there, it results in: |
54f4ddb3 TS |
16520 | daddu $gp, $reg2, $0 */ |
16521 | ||
6478892d | 16522 | static void |
17a2f251 | 16523 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16524 | { |
16525 | expressionS ex; | |
6478892d TS |
16526 | |
16527 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
16528 | We also need NewABI support. */ | |
16529 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16530 | { | |
16531 | s_ignore (0); | |
16532 | return; | |
16533 | } | |
16534 | ||
584892a6 | 16535 | macro_start (); |
6478892d TS |
16536 | if (mips_cpreturn_register == -1) |
16537 | { | |
16538 | ex.X_op = O_constant; | |
16539 | ex.X_add_symbol = NULL; | |
16540 | ex.X_op_symbol = NULL; | |
16541 | ex.X_add_number = mips_cpreturn_offset; | |
16542 | ||
67c0d1eb | 16543 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
16544 | } |
16545 | else | |
67c0d1eb | 16546 | macro_build (NULL, "daddu", "d,v,t", mips_gp_register, |
17a2f251 | 16547 | mips_cpreturn_register, 0); |
584892a6 | 16548 | macro_end (); |
6478892d TS |
16549 | |
16550 | demand_empty_rest_of_line (); | |
16551 | } | |
16552 | ||
741d6ea8 JM |
16553 | /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate |
16554 | a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for | |
16555 | use in DWARF debug information. */ | |
16556 | ||
16557 | static void | |
16558 | s_dtprel_internal (size_t bytes) | |
16559 | { | |
16560 | expressionS ex; | |
16561 | char *p; | |
16562 | ||
16563 | expression (&ex); | |
16564 | ||
16565 | if (ex.X_op != O_symbol) | |
16566 | { | |
16567 | as_bad (_("Unsupported use of %s"), (bytes == 8 | |
16568 | ? ".dtpreldword" | |
16569 | : ".dtprelword")); | |
16570 | ignore_rest_of_line (); | |
16571 | } | |
16572 | ||
16573 | p = frag_more (bytes); | |
16574 | md_number_to_chars (p, 0, bytes); | |
16575 | fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, | |
16576 | (bytes == 8 | |
16577 | ? BFD_RELOC_MIPS_TLS_DTPREL64 | |
16578 | : BFD_RELOC_MIPS_TLS_DTPREL32)); | |
16579 | ||
16580 | demand_empty_rest_of_line (); | |
16581 | } | |
16582 | ||
16583 | /* Handle .dtprelword. */ | |
16584 | ||
16585 | static void | |
16586 | s_dtprelword (int ignore ATTRIBUTE_UNUSED) | |
16587 | { | |
16588 | s_dtprel_internal (4); | |
16589 | } | |
16590 | ||
16591 | /* Handle .dtpreldword. */ | |
16592 | ||
16593 | static void | |
16594 | s_dtpreldword (int ignore ATTRIBUTE_UNUSED) | |
16595 | { | |
16596 | s_dtprel_internal (8); | |
16597 | } | |
16598 | ||
6478892d TS |
16599 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC |
16600 | code. It sets the offset to use in gp_rel relocations. */ | |
16601 | ||
16602 | static void | |
17a2f251 | 16603 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16604 | { |
16605 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
16606 | We also need NewABI support. */ | |
16607 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16608 | { | |
16609 | s_ignore (0); | |
16610 | return; | |
16611 | } | |
16612 | ||
def2e0dd | 16613 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
16614 | |
16615 | demand_empty_rest_of_line (); | |
16616 | } | |
16617 | ||
252b5132 RH |
16618 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
16619 | code. It generates a 32 bit GP relative reloc. */ | |
16620 | ||
16621 | static void | |
17a2f251 | 16622 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 16623 | { |
a8dbcb85 TS |
16624 | segment_info_type *si; |
16625 | struct insn_label_list *l; | |
252b5132 RH |
16626 | symbolS *label; |
16627 | expressionS ex; | |
16628 | char *p; | |
16629 | ||
16630 | /* When not generating PIC code, this is treated as .word. */ | |
16631 | if (mips_pic != SVR4_PIC) | |
16632 | { | |
16633 | s_cons (2); | |
16634 | return; | |
16635 | } | |
16636 | ||
a8dbcb85 TS |
16637 | si = seg_info (now_seg); |
16638 | l = si->label_list; | |
16639 | label = l != NULL ? l->label : NULL; | |
7d10b47d | 16640 | mips_emit_delays (); |
252b5132 RH |
16641 | if (auto_align) |
16642 | mips_align (2, 0, label); | |
252b5132 RH |
16643 | |
16644 | expression (&ex); | |
a1facbec | 16645 | mips_clear_insn_labels (); |
252b5132 RH |
16646 | |
16647 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
16648 | { | |
16649 | as_bad (_("Unsupported use of .gpword")); | |
16650 | ignore_rest_of_line (); | |
16651 | } | |
16652 | ||
16653 | p = frag_more (4); | |
17a2f251 | 16654 | md_number_to_chars (p, 0, 4); |
b34976b6 | 16655 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 16656 | BFD_RELOC_GPREL32); |
252b5132 RH |
16657 | |
16658 | demand_empty_rest_of_line (); | |
16659 | } | |
16660 | ||
10181a0d | 16661 | static void |
17a2f251 | 16662 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d | 16663 | { |
a8dbcb85 TS |
16664 | segment_info_type *si; |
16665 | struct insn_label_list *l; | |
10181a0d AO |
16666 | symbolS *label; |
16667 | expressionS ex; | |
16668 | char *p; | |
16669 | ||
16670 | /* When not generating PIC code, this is treated as .dword. */ | |
16671 | if (mips_pic != SVR4_PIC) | |
16672 | { | |
16673 | s_cons (3); | |
16674 | return; | |
16675 | } | |
16676 | ||
a8dbcb85 TS |
16677 | si = seg_info (now_seg); |
16678 | l = si->label_list; | |
16679 | label = l != NULL ? l->label : NULL; | |
7d10b47d | 16680 | mips_emit_delays (); |
10181a0d AO |
16681 | if (auto_align) |
16682 | mips_align (3, 0, label); | |
10181a0d AO |
16683 | |
16684 | expression (&ex); | |
a1facbec | 16685 | mips_clear_insn_labels (); |
10181a0d AO |
16686 | |
16687 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
16688 | { | |
16689 | as_bad (_("Unsupported use of .gpdword")); | |
16690 | ignore_rest_of_line (); | |
16691 | } | |
16692 | ||
16693 | p = frag_more (8); | |
17a2f251 | 16694 | md_number_to_chars (p, 0, 8); |
a105a300 | 16695 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 16696 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
16697 | |
16698 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
16699 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
16700 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
16701 | |
16702 | demand_empty_rest_of_line (); | |
16703 | } | |
16704 | ||
252b5132 RH |
16705 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
16706 | tables in SVR4 PIC code. */ | |
16707 | ||
16708 | static void | |
17a2f251 | 16709 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 16710 | { |
252b5132 RH |
16711 | int reg; |
16712 | ||
10181a0d AO |
16713 | /* This is ignored when not generating SVR4 PIC code. */ |
16714 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
16715 | { |
16716 | s_ignore (0); | |
16717 | return; | |
16718 | } | |
16719 | ||
16720 | /* Add $gp to the register named as an argument. */ | |
584892a6 | 16721 | macro_start (); |
252b5132 | 16722 | reg = tc_get_register (0); |
67c0d1eb | 16723 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 16724 | macro_end (); |
252b5132 | 16725 | |
bdaaa2e1 | 16726 | demand_empty_rest_of_line (); |
252b5132 RH |
16727 | } |
16728 | ||
16729 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
df58fc94 | 16730 | mips16/micromips mode. This permits the linker to handle them specially, |
252b5132 RH |
16731 | such as generating jalx instructions when needed. We also make |
16732 | them odd for the duration of the assembly, in order to generate the | |
16733 | right sort of code. We will make them even in the adjust_symtab | |
16734 | routine, while leaving them marked. This is convenient for the | |
16735 | debugger and the disassembler. The linker knows to make them odd | |
16736 | again. */ | |
16737 | ||
16738 | static void | |
17a2f251 | 16739 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 16740 | { |
df58fc94 | 16741 | mips_mark_labels (); |
252b5132 RH |
16742 | |
16743 | demand_empty_rest_of_line (); | |
16744 | } | |
16745 | ||
16746 | /* Handle a .stabn directive. We need these in order to mark a label | |
16747 | as being a mips16 text label correctly. Sometimes the compiler | |
16748 | will emit a label, followed by a .stabn, and then switch sections. | |
16749 | If the label and .stabn are in mips16 mode, then the label is | |
16750 | really a mips16 text label. */ | |
16751 | ||
16752 | static void | |
17a2f251 | 16753 | s_mips_stab (int type) |
252b5132 | 16754 | { |
f9419b05 | 16755 | if (type == 'n') |
df58fc94 | 16756 | mips_mark_labels (); |
252b5132 RH |
16757 | |
16758 | s_stab (type); | |
16759 | } | |
16760 | ||
54f4ddb3 | 16761 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */ |
252b5132 RH |
16762 | |
16763 | static void | |
17a2f251 | 16764 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16765 | { |
16766 | char *name; | |
16767 | int c; | |
16768 | symbolS *symbolP; | |
16769 | expressionS exp; | |
16770 | ||
16771 | name = input_line_pointer; | |
16772 | c = get_symbol_end (); | |
16773 | symbolP = symbol_find_or_make (name); | |
16774 | S_SET_WEAK (symbolP); | |
16775 | *input_line_pointer = c; | |
16776 | ||
16777 | SKIP_WHITESPACE (); | |
16778 | ||
16779 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
16780 | { | |
16781 | if (S_IS_DEFINED (symbolP)) | |
16782 | { | |
20203fb9 | 16783 | as_bad (_("ignoring attempt to redefine symbol %s"), |
252b5132 RH |
16784 | S_GET_NAME (symbolP)); |
16785 | ignore_rest_of_line (); | |
16786 | return; | |
16787 | } | |
bdaaa2e1 | 16788 | |
252b5132 RH |
16789 | if (*input_line_pointer == ',') |
16790 | { | |
16791 | ++input_line_pointer; | |
16792 | SKIP_WHITESPACE (); | |
16793 | } | |
bdaaa2e1 | 16794 | |
252b5132 RH |
16795 | expression (&exp); |
16796 | if (exp.X_op != O_symbol) | |
16797 | { | |
20203fb9 | 16798 | as_bad (_("bad .weakext directive")); |
98d3f06f | 16799 | ignore_rest_of_line (); |
252b5132 RH |
16800 | return; |
16801 | } | |
49309057 | 16802 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
16803 | } |
16804 | ||
16805 | demand_empty_rest_of_line (); | |
16806 | } | |
16807 | ||
16808 | /* Parse a register string into a number. Called from the ECOFF code | |
16809 | to parse .frame. The argument is non-zero if this is the frame | |
16810 | register, so that we can record it in mips_frame_reg. */ | |
16811 | ||
16812 | int | |
17a2f251 | 16813 | tc_get_register (int frame) |
252b5132 | 16814 | { |
707bfff6 | 16815 | unsigned int reg; |
252b5132 RH |
16816 | |
16817 | SKIP_WHITESPACE (); | |
707bfff6 TS |
16818 | if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®)) |
16819 | reg = 0; | |
252b5132 | 16820 | if (frame) |
7a621144 DJ |
16821 | { |
16822 | mips_frame_reg = reg != 0 ? reg : SP; | |
16823 | mips_frame_reg_valid = 1; | |
16824 | mips_cprestore_valid = 0; | |
16825 | } | |
252b5132 RH |
16826 | return reg; |
16827 | } | |
16828 | ||
16829 | valueT | |
17a2f251 | 16830 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
16831 | { |
16832 | int align = bfd_get_section_alignment (stdoutput, seg); | |
16833 | ||
b4c71f56 TS |
16834 | if (IS_ELF) |
16835 | { | |
16836 | /* We don't need to align ELF sections to the full alignment. | |
16837 | However, Irix 5 may prefer that we align them at least to a 16 | |
16838 | byte boundary. We don't bother to align the sections if we | |
16839 | are targeted for an embedded system. */ | |
c41e87e3 | 16840 | if (strncmp (TARGET_OS, "elf", 3) == 0) |
b4c71f56 TS |
16841 | return addr; |
16842 | if (align > 4) | |
16843 | align = 4; | |
16844 | } | |
252b5132 RH |
16845 | |
16846 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
16847 | } | |
16848 | ||
16849 | /* Utility routine, called from above as well. If called while the | |
16850 | input file is still being read, it's only an approximation. (For | |
16851 | example, a symbol may later become defined which appeared to be | |
16852 | undefined earlier.) */ | |
16853 | ||
16854 | static int | |
17a2f251 | 16855 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
16856 | { |
16857 | if (sym == 0) | |
16858 | return 0; | |
16859 | ||
4d0d148d | 16860 | if (g_switch_value > 0) |
252b5132 RH |
16861 | { |
16862 | const char *symname; | |
16863 | int change; | |
16864 | ||
c9914766 | 16865 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
16866 | register. It can be if it is smaller than the -G size or if |
16867 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 16868 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
16869 | they can. */ |
16870 | symname = S_GET_NAME (sym); | |
16871 | if (symname != (const char *) NULL | |
16872 | && (strcmp (symname, "eprol") == 0 | |
16873 | || strcmp (symname, "etext") == 0 | |
16874 | || strcmp (symname, "_gp") == 0 | |
16875 | || strcmp (symname, "edata") == 0 | |
16876 | || strcmp (symname, "_fbss") == 0 | |
16877 | || strcmp (symname, "_fdata") == 0 | |
16878 | || strcmp (symname, "_ftext") == 0 | |
16879 | || strcmp (symname, "end") == 0 | |
16880 | || strcmp (symname, "_gp_disp") == 0)) | |
16881 | change = 1; | |
16882 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
16883 | && (0 | |
16884 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
16885 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
16886 | && (symbol_get_obj (sym)->ecoff_extern_size | |
16887 | <= g_switch_value)) | |
252b5132 RH |
16888 | #endif |
16889 | /* We must defer this decision until after the whole | |
16890 | file has been read, since there might be a .extern | |
16891 | after the first use of this symbol. */ | |
16892 | || (before_relaxing | |
16893 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 16894 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
16895 | #endif |
16896 | && S_GET_VALUE (sym) == 0) | |
16897 | || (S_GET_VALUE (sym) != 0 | |
16898 | && S_GET_VALUE (sym) <= g_switch_value))) | |
16899 | change = 0; | |
16900 | else | |
16901 | { | |
16902 | const char *segname; | |
16903 | ||
16904 | segname = segment_name (S_GET_SEGMENT (sym)); | |
9c2799c2 | 16905 | gas_assert (strcmp (segname, ".lit8") != 0 |
252b5132 RH |
16906 | && strcmp (segname, ".lit4") != 0); |
16907 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
16908 | && strcmp (segname, ".sbss") != 0 |
16909 | && strncmp (segname, ".sdata.", 7) != 0 | |
d4dc2f22 TS |
16910 | && strncmp (segname, ".sbss.", 6) != 0 |
16911 | && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0 | |
fba2b7f9 | 16912 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); |
252b5132 RH |
16913 | } |
16914 | return change; | |
16915 | } | |
16916 | else | |
c9914766 | 16917 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
16918 | return 1; |
16919 | } | |
16920 | ||
5919d012 RS |
16921 | |
16922 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
16923 | ||
16924 | static bfd_boolean | |
17a2f251 | 16925 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
16926 | { |
16927 | asection *symsec; | |
5919d012 RS |
16928 | |
16929 | /* Handle the case of a symbol equated to another symbol. */ | |
16930 | while (symbol_equated_reloc_p (sym)) | |
16931 | { | |
16932 | symbolS *n; | |
16933 | ||
5f0fe04b | 16934 | /* It's possible to get a loop here in a badly written program. */ |
5919d012 RS |
16935 | n = symbol_get_value_expression (sym)->X_add_symbol; |
16936 | if (n == sym) | |
16937 | break; | |
16938 | sym = n; | |
16939 | } | |
16940 | ||
df1f3cda DD |
16941 | if (symbol_section_p (sym)) |
16942 | return TRUE; | |
16943 | ||
5919d012 RS |
16944 | symsec = S_GET_SEGMENT (sym); |
16945 | ||
5919d012 RS |
16946 | /* This must duplicate the test in adjust_reloc_syms. */ |
16947 | return (symsec != &bfd_und_section | |
16948 | && symsec != &bfd_abs_section | |
5f0fe04b TS |
16949 | && !bfd_is_com_section (symsec) |
16950 | && !s_is_linkonce (sym, segtype) | |
5919d012 RS |
16951 | #ifdef OBJ_ELF |
16952 | /* A global or weak symbol is treated as external. */ | |
f43abd2b | 16953 | && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym))) |
5919d012 RS |
16954 | #endif |
16955 | ); | |
16956 | } | |
16957 | ||
16958 | ||
252b5132 RH |
16959 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
16960 | extended opcode. SEC is the section the frag is in. */ | |
16961 | ||
16962 | static int | |
17a2f251 | 16963 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
16964 | { |
16965 | int type; | |
3994f87e | 16966 | const struct mips16_immed_operand *op; |
252b5132 RH |
16967 | offsetT val; |
16968 | int mintiny, maxtiny; | |
16969 | segT symsec; | |
98aa84af | 16970 | fragS *sym_frag; |
252b5132 RH |
16971 | |
16972 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
16973 | return 0; | |
16974 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
16975 | return 1; | |
16976 | ||
16977 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
16978 | op = mips16_immed_operands; | |
16979 | while (op->type != type) | |
16980 | { | |
16981 | ++op; | |
9c2799c2 | 16982 | gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
252b5132 RH |
16983 | } |
16984 | ||
16985 | if (op->unsp) | |
16986 | { | |
16987 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
16988 | { | |
16989 | mintiny = 1; | |
16990 | maxtiny = 1 << op->nbits; | |
16991 | } | |
16992 | else | |
16993 | { | |
16994 | mintiny = 0; | |
16995 | maxtiny = (1 << op->nbits) - 1; | |
16996 | } | |
16997 | } | |
16998 | else | |
16999 | { | |
17000 | mintiny = - (1 << (op->nbits - 1)); | |
17001 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
17002 | } | |
17003 | ||
98aa84af | 17004 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 17005 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 17006 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
17007 | |
17008 | if (op->pcrel) | |
17009 | { | |
17010 | addressT addr; | |
17011 | ||
17012 | /* We won't have the section when we are called from | |
17013 | mips_relax_frag. However, we will always have been called | |
17014 | from md_estimate_size_before_relax first. If this is a | |
17015 | branch to a different section, we mark it as such. If SEC is | |
17016 | NULL, and the frag is not marked, then it must be a branch to | |
17017 | the same section. */ | |
17018 | if (sec == NULL) | |
17019 | { | |
17020 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
17021 | return 1; | |
17022 | } | |
17023 | else | |
17024 | { | |
98aa84af | 17025 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
17026 | if (symsec != sec) |
17027 | { | |
17028 | fragp->fr_subtype = | |
17029 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
17030 | ||
17031 | /* FIXME: We should support this, and let the linker | |
17032 | catch branches and loads that are out of range. */ | |
17033 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
17034 | _("unsupported PC relative reference to different section")); | |
17035 | ||
17036 | return 1; | |
17037 | } | |
98aa84af AM |
17038 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
17039 | /* Assume non-extended on the first relaxation pass. | |
17040 | The address we have calculated will be bogus if this is | |
17041 | a forward branch to another frag, as the forward frag | |
17042 | will have fr_address == 0. */ | |
17043 | return 0; | |
252b5132 RH |
17044 | } |
17045 | ||
17046 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
17047 | the same section. If the relax_marker of the symbol fragment |
17048 | differs from the relax_marker of this fragment, we have not | |
17049 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
17050 | in STRETCH in order to get a better estimate of the address. |
17051 | This particularly matters because of the shift bits. */ | |
17052 | if (stretch != 0 | |
98aa84af | 17053 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
17054 | { |
17055 | fragS *f; | |
17056 | ||
17057 | /* Adjust stretch for any alignment frag. Note that if have | |
17058 | been expanding the earlier code, the symbol may be | |
17059 | defined in what appears to be an earlier frag. FIXME: | |
17060 | This doesn't handle the fr_subtype field, which specifies | |
17061 | a maximum number of bytes to skip when doing an | |
17062 | alignment. */ | |
98aa84af | 17063 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
17064 | { |
17065 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
17066 | { | |
17067 | if (stretch < 0) | |
17068 | stretch = - ((- stretch) | |
17069 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
17070 | else | |
17071 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
17072 | if (stretch == 0) | |
17073 | break; | |
17074 | } | |
17075 | } | |
17076 | if (f != NULL) | |
17077 | val += stretch; | |
17078 | } | |
17079 | ||
17080 | addr = fragp->fr_address + fragp->fr_fix; | |
17081 | ||
17082 | /* The base address rules are complicated. The base address of | |
17083 | a branch is the following instruction. The base address of a | |
17084 | PC relative load or add is the instruction itself, but if it | |
17085 | is in a delay slot (in which case it can not be extended) use | |
17086 | the address of the instruction whose delay slot it is in. */ | |
17087 | if (type == 'p' || type == 'q') | |
17088 | { | |
17089 | addr += 2; | |
17090 | ||
17091 | /* If we are currently assuming that this frag should be | |
17092 | extended, then, the current address is two bytes | |
bdaaa2e1 | 17093 | higher. */ |
252b5132 RH |
17094 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
17095 | addr += 2; | |
17096 | ||
17097 | /* Ignore the low bit in the target, since it will be set | |
17098 | for a text label. */ | |
17099 | if ((val & 1) != 0) | |
17100 | --val; | |
17101 | } | |
17102 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
17103 | addr -= 4; | |
17104 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
17105 | addr -= 2; | |
17106 | ||
17107 | val -= addr & ~ ((1 << op->shift) - 1); | |
17108 | ||
17109 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
17110 | if (type == 'p' || type == 'q') | |
17111 | val /= 2; | |
17112 | ||
17113 | /* If any of the shifted bits are set, we must use an extended | |
17114 | opcode. If the address depends on the size of this | |
17115 | instruction, this can lead to a loop, so we arrange to always | |
17116 | use an extended opcode. We only check this when we are in | |
17117 | the main relaxation loop, when SEC is NULL. */ | |
17118 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
17119 | { | |
17120 | fragp->fr_subtype = | |
17121 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
17122 | return 1; | |
17123 | } | |
17124 | ||
17125 | /* If we are about to mark a frag as extended because the value | |
17126 | is precisely maxtiny + 1, then there is a chance of an | |
17127 | infinite loop as in the following code: | |
17128 | la $4,foo | |
17129 | .skip 1020 | |
17130 | .align 2 | |
17131 | foo: | |
17132 | In this case when the la is extended, foo is 0x3fc bytes | |
17133 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
17134 | the la must be extended. To avoid this loop, we mark the | |
17135 | frag as extended if it was small, and is about to become | |
17136 | extended with a value of maxtiny + 1. */ | |
17137 | if (val == ((maxtiny + 1) << op->shift) | |
17138 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
17139 | && sec == NULL) | |
17140 | { | |
17141 | fragp->fr_subtype = | |
17142 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
17143 | return 1; | |
17144 | } | |
17145 | } | |
17146 | else if (symsec != absolute_section && sec != NULL) | |
17147 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
17148 | ||
17149 | if ((val & ((1 << op->shift) - 1)) != 0 | |
17150 | || val < (mintiny << op->shift) | |
17151 | || val > (maxtiny << op->shift)) | |
17152 | return 1; | |
17153 | else | |
17154 | return 0; | |
17155 | } | |
17156 | ||
4a6a3df4 AO |
17157 | /* Compute the length of a branch sequence, and adjust the |
17158 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
17159 | worst-case length is computed, with UPDATE being used to indicate | |
17160 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
17161 | branch is to be computed. */ | |
17162 | static int | |
17a2f251 | 17163 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 17164 | { |
b34976b6 | 17165 | bfd_boolean toofar; |
4a6a3df4 AO |
17166 | int length; |
17167 | ||
17168 | if (fragp | |
17169 | && S_IS_DEFINED (fragp->fr_symbol) | |
17170 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
17171 | { | |
17172 | addressT addr; | |
17173 | offsetT val; | |
17174 | ||
17175 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17176 | ||
17177 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
17178 | ||
17179 | val -= addr; | |
17180 | ||
17181 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
17182 | } | |
17183 | else if (fragp) | |
17184 | /* If the symbol is not defined or it's in a different segment, | |
17185 | assume the user knows what's going on and emit a short | |
17186 | branch. */ | |
b34976b6 | 17187 | toofar = FALSE; |
4a6a3df4 | 17188 | else |
b34976b6 | 17189 | toofar = TRUE; |
4a6a3df4 AO |
17190 | |
17191 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
17192 | fragp->fr_subtype | |
66b3e8da MR |
17193 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype), |
17194 | RELAX_BRANCH_UNCOND (fragp->fr_subtype), | |
4a6a3df4 AO |
17195 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
17196 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
17197 | toofar); | |
17198 | ||
17199 | length = 4; | |
17200 | if (toofar) | |
17201 | { | |
17202 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
17203 | length += 8; | |
17204 | ||
17205 | if (mips_pic != NO_PIC) | |
17206 | { | |
17207 | /* Additional space for PIC loading of target address. */ | |
17208 | length += 8; | |
17209 | if (mips_opts.isa == ISA_MIPS1) | |
17210 | /* Additional space for $at-stabilizing nop. */ | |
17211 | length += 4; | |
17212 | } | |
17213 | ||
17214 | /* If branch is conditional. */ | |
17215 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
17216 | length += 8; | |
17217 | } | |
b34976b6 | 17218 | |
4a6a3df4 AO |
17219 | return length; |
17220 | } | |
17221 | ||
df58fc94 RS |
17222 | /* Compute the length of a branch sequence, and adjust the |
17223 | RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the | |
17224 | worst-case length is computed, with UPDATE being used to indicate | |
17225 | whether an unconditional (-1), or regular (0) branch is to be | |
17226 | computed. */ | |
17227 | ||
17228 | static int | |
17229 | relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update) | |
17230 | { | |
17231 | bfd_boolean toofar; | |
17232 | int length; | |
17233 | ||
17234 | if (fragp | |
17235 | && S_IS_DEFINED (fragp->fr_symbol) | |
17236 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
17237 | { | |
17238 | addressT addr; | |
17239 | offsetT val; | |
17240 | ||
17241 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17242 | /* Ignore the low bit in the target, since it will be set | |
17243 | for a text label. */ | |
17244 | if ((val & 1) != 0) | |
17245 | --val; | |
17246 | ||
17247 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
17248 | ||
17249 | val -= addr; | |
17250 | ||
17251 | toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1); | |
17252 | } | |
17253 | else if (fragp) | |
17254 | /* If the symbol is not defined or it's in a different segment, | |
17255 | assume the user knows what's going on and emit a short | |
17256 | branch. */ | |
17257 | toofar = FALSE; | |
17258 | else | |
17259 | toofar = TRUE; | |
17260 | ||
17261 | if (fragp && update | |
17262 | && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
17263 | fragp->fr_subtype = (toofar | |
17264 | ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype) | |
17265 | : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype)); | |
17266 | ||
17267 | length = 4; | |
17268 | if (toofar) | |
17269 | { | |
17270 | bfd_boolean compact_known = fragp != NULL; | |
17271 | bfd_boolean compact = FALSE; | |
17272 | bfd_boolean uncond; | |
17273 | ||
17274 | if (compact_known) | |
17275 | compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); | |
17276 | if (fragp) | |
17277 | uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype); | |
17278 | else | |
17279 | uncond = update < 0; | |
17280 | ||
17281 | /* If label is out of range, we turn branch <br>: | |
17282 | ||
17283 | <br> label # 4 bytes | |
17284 | 0: | |
17285 | ||
17286 | into: | |
17287 | ||
17288 | j label # 4 bytes | |
17289 | nop # 2 bytes if compact && !PIC | |
17290 | 0: | |
17291 | */ | |
17292 | if (mips_pic == NO_PIC && (!compact_known || compact)) | |
17293 | length += 2; | |
17294 | ||
17295 | /* If assembling PIC code, we further turn: | |
17296 | ||
17297 | j label # 4 bytes | |
17298 | ||
17299 | into: | |
17300 | ||
17301 | lw/ld at, %got(label)(gp) # 4 bytes | |
17302 | d/addiu at, %lo(label) # 4 bytes | |
17303 | jr/c at # 2 bytes | |
17304 | */ | |
17305 | if (mips_pic != NO_PIC) | |
17306 | length += 6; | |
17307 | ||
17308 | /* If branch <br> is conditional, we prepend negated branch <brneg>: | |
17309 | ||
17310 | <brneg> 0f # 4 bytes | |
17311 | nop # 2 bytes if !compact | |
17312 | */ | |
17313 | if (!uncond) | |
17314 | length += (compact_known && compact) ? 4 : 6; | |
17315 | } | |
17316 | ||
17317 | return length; | |
17318 | } | |
17319 | ||
17320 | /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16 | |
17321 | bit accordingly. */ | |
17322 | ||
17323 | static int | |
17324 | relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update) | |
17325 | { | |
17326 | bfd_boolean toofar; | |
17327 | ||
df58fc94 RS |
17328 | if (fragp |
17329 | && S_IS_DEFINED (fragp->fr_symbol) | |
17330 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
17331 | { | |
17332 | addressT addr; | |
17333 | offsetT val; | |
17334 | int type; | |
17335 | ||
17336 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17337 | /* Ignore the low bit in the target, since it will be set | |
17338 | for a text label. */ | |
17339 | if ((val & 1) != 0) | |
17340 | --val; | |
17341 | ||
17342 | /* Assume this is a 2-byte branch. */ | |
17343 | addr = fragp->fr_address + fragp->fr_fix + 2; | |
17344 | ||
17345 | /* We try to avoid the infinite loop by not adding 2 more bytes for | |
17346 | long branches. */ | |
17347 | ||
17348 | val -= addr; | |
17349 | ||
17350 | type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
17351 | if (type == 'D') | |
17352 | toofar = val < - (0x200 << 1) || val >= (0x200 << 1); | |
17353 | else if (type == 'E') | |
17354 | toofar = val < - (0x40 << 1) || val >= (0x40 << 1); | |
17355 | else | |
17356 | abort (); | |
17357 | } | |
17358 | else | |
17359 | /* If the symbol is not defined or it's in a different segment, | |
17360 | we emit a normal 32-bit branch. */ | |
17361 | toofar = TRUE; | |
17362 | ||
17363 | if (fragp && update | |
17364 | && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
17365 | fragp->fr_subtype | |
17366 | = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype) | |
17367 | : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype); | |
17368 | ||
17369 | if (toofar) | |
17370 | return 4; | |
17371 | ||
17372 | return 2; | |
17373 | } | |
17374 | ||
252b5132 RH |
17375 | /* Estimate the size of a frag before relaxing. Unless this is the |
17376 | mips16, we are not really relaxing here, and the final size is | |
17377 | encoded in the subtype information. For the mips16, we have to | |
17378 | decide whether we are using an extended opcode or not. */ | |
17379 | ||
252b5132 | 17380 | int |
17a2f251 | 17381 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 17382 | { |
5919d012 | 17383 | int change; |
252b5132 | 17384 | |
4a6a3df4 AO |
17385 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
17386 | { | |
17387 | ||
b34976b6 AM |
17388 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
17389 | ||
4a6a3df4 AO |
17390 | return fragp->fr_var; |
17391 | } | |
17392 | ||
252b5132 | 17393 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
17394 | /* We don't want to modify the EXTENDED bit here; it might get us |
17395 | into infinite loops. We change it only in mips_relax_frag(). */ | |
17396 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 | 17397 | |
df58fc94 RS |
17398 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
17399 | { | |
17400 | int length = 4; | |
17401 | ||
17402 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
17403 | length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE); | |
17404 | if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
17405 | length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE); | |
17406 | fragp->fr_var = length; | |
17407 | ||
17408 | return length; | |
17409 | } | |
17410 | ||
252b5132 | 17411 | if (mips_pic == NO_PIC) |
5919d012 | 17412 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 17413 | else if (mips_pic == SVR4_PIC) |
5919d012 | 17414 | change = pic_need_relax (fragp->fr_symbol, segtype); |
0a44bf69 RS |
17415 | else if (mips_pic == VXWORKS_PIC) |
17416 | /* For vxworks, GOT16 relocations never have a corresponding LO16. */ | |
17417 | change = 0; | |
252b5132 RH |
17418 | else |
17419 | abort (); | |
17420 | ||
17421 | if (change) | |
17422 | { | |
4d7206a2 | 17423 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 17424 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 17425 | } |
4d7206a2 RS |
17426 | else |
17427 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
17428 | } |
17429 | ||
17430 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 17431 | should be converted into a reloc against a section. */ |
252b5132 RH |
17432 | |
17433 | int | |
17a2f251 | 17434 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 17435 | { |
252b5132 RH |
17436 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
17437 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
17438 | return 0; | |
a161fe53 | 17439 | |
252b5132 RH |
17440 | if (fixp->fx_addsy == NULL) |
17441 | return 1; | |
a161fe53 | 17442 | |
de7e6852 RS |
17443 | /* If symbol SYM is in a mergeable section, relocations of the form |
17444 | SYM + 0 can usually be made section-relative. The mergeable data | |
17445 | is then identified by the section offset rather than by the symbol. | |
17446 | ||
17447 | However, if we're generating REL LO16 relocations, the offset is split | |
17448 | between the LO16 and parterning high part relocation. The linker will | |
17449 | need to recalculate the complete offset in order to correctly identify | |
17450 | the merge data. | |
17451 | ||
17452 | The linker has traditionally not looked for the parterning high part | |
17453 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be | |
17454 | placed anywhere. Rather than break backwards compatibility by changing | |
17455 | this, it seems better not to force the issue, and instead keep the | |
17456 | original symbol. This will work with either linker behavior. */ | |
738e5348 | 17457 | if ((lo16_reloc_p (fixp->fx_r_type) |
704803a9 | 17458 | || reloc_needs_lo_p (fixp->fx_r_type)) |
de7e6852 RS |
17459 | && HAVE_IN_PLACE_ADDENDS |
17460 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
17461 | return 0; | |
17462 | ||
ce70d90a MR |
17463 | /* There is no place to store an in-place offset for JALR relocations. |
17464 | Likewise an in-range offset of PC-relative relocations may overflow | |
17465 | the in-place relocatable field if recalculated against the start | |
17466 | address of the symbol's containing section. */ | |
17467 | if (HAVE_IN_PLACE_ADDENDS | |
df58fc94 | 17468 | && (fixp->fx_pcrel || jalr_reloc_p (fixp->fx_r_type))) |
1180b5a4 RS |
17469 | return 0; |
17470 | ||
252b5132 | 17471 | #ifdef OBJ_ELF |
b314ec0e RS |
17472 | /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve |
17473 | to a floating-point stub. The same is true for non-R_MIPS16_26 | |
17474 | relocations against MIPS16 functions; in this case, the stub becomes | |
17475 | the function's canonical address. | |
17476 | ||
17477 | Floating-point stubs are stored in unique .mips16.call.* or | |
17478 | .mips16.fn.* sections. If a stub T for function F is in section S, | |
17479 | the first relocation in section S must be against F; this is how the | |
17480 | linker determines the target function. All relocations that might | |
17481 | resolve to T must also be against F. We therefore have the following | |
17482 | restrictions, which are given in an intentionally-redundant way: | |
17483 | ||
17484 | 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16 | |
17485 | symbols. | |
17486 | ||
17487 | 2. We cannot reduce a stub's relocations against non-MIPS16 symbols | |
17488 | if that stub might be used. | |
17489 | ||
17490 | 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16 | |
17491 | symbols. | |
17492 | ||
17493 | 4. We cannot reduce a stub's relocations against MIPS16 symbols if | |
17494 | that stub might be used. | |
17495 | ||
17496 | There is a further restriction: | |
17497 | ||
df58fc94 RS |
17498 | 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or |
17499 | R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on | |
17500 | targets with in-place addends; the relocation field cannot | |
b314ec0e RS |
17501 | encode the low bit. |
17502 | ||
df58fc94 RS |
17503 | For simplicity, we deal with (3)-(4) by not reducing _any_ relocation |
17504 | against a MIPS16 symbol. We deal with (5) by by not reducing any | |
17505 | such relocations on REL targets. | |
b314ec0e RS |
17506 | |
17507 | We deal with (1)-(2) by saying that, if there's a R_MIPS16_26 | |
17508 | relocation against some symbol R, no relocation against R may be | |
17509 | reduced. (Note that this deals with (2) as well as (1) because | |
17510 | relocations against global symbols will never be reduced on ELF | |
17511 | targets.) This approach is a little simpler than trying to detect | |
17512 | stub sections, and gives the "all or nothing" per-symbol consistency | |
17513 | that we have for MIPS16 symbols. */ | |
f43abd2b | 17514 | if (IS_ELF |
b314ec0e | 17515 | && fixp->fx_subsy == NULL |
30c09090 | 17516 | && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy)) |
df58fc94 RS |
17517 | || *symbol_get_tc (fixp->fx_addsy) |
17518 | || (HAVE_IN_PLACE_ADDENDS | |
17519 | && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy)) | |
17520 | && jmp_reloc_p (fixp->fx_r_type)))) | |
252b5132 RH |
17521 | return 0; |
17522 | #endif | |
a161fe53 | 17523 | |
252b5132 RH |
17524 | return 1; |
17525 | } | |
17526 | ||
17527 | /* Translate internal representation of relocation info to BFD target | |
17528 | format. */ | |
17529 | ||
17530 | arelent ** | |
17a2f251 | 17531 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
17532 | { |
17533 | static arelent *retval[4]; | |
17534 | arelent *reloc; | |
17535 | bfd_reloc_code_real_type code; | |
17536 | ||
4b0cff4e TS |
17537 | memset (retval, 0, sizeof(retval)); |
17538 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
17539 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
17540 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
17541 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
17542 | ||
bad36eac DJ |
17543 | if (fixp->fx_pcrel) |
17544 | { | |
df58fc94 RS |
17545 | gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 |
17546 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
17547 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
17548 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
bad36eac DJ |
17549 | |
17550 | /* At this point, fx_addnumber is "symbol offset - pcrel address". | |
17551 | Relocations want only the symbol offset. */ | |
17552 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
f43abd2b | 17553 | if (!IS_ELF) |
bad36eac DJ |
17554 | { |
17555 | /* A gruesome hack which is a result of the gruesome gas | |
17556 | reloc handling. What's worse, for COFF (as opposed to | |
17557 | ECOFF), we might need yet another copy of reloc->address. | |
17558 | See bfd_install_relocation. */ | |
17559 | reloc->addend += reloc->address; | |
17560 | } | |
17561 | } | |
17562 | else | |
17563 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 17564 | |
438c16b8 TS |
17565 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
17566 | entry to be used in the relocation's section offset. */ | |
17567 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
17568 | { |
17569 | reloc->address = reloc->addend; | |
17570 | reloc->addend = 0; | |
17571 | } | |
17572 | ||
252b5132 | 17573 | code = fixp->fx_r_type; |
252b5132 | 17574 | |
bad36eac | 17575 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
252b5132 RH |
17576 | if (reloc->howto == NULL) |
17577 | { | |
17578 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
17579 | _("Can not represent %s relocation in this object file format"), | |
17580 | bfd_get_reloc_code_name (code)); | |
17581 | retval[0] = NULL; | |
17582 | } | |
17583 | ||
17584 | return retval; | |
17585 | } | |
17586 | ||
17587 | /* Relax a machine dependent frag. This returns the amount by which | |
17588 | the current size of the frag should change. */ | |
17589 | ||
17590 | int | |
17a2f251 | 17591 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 17592 | { |
4a6a3df4 AO |
17593 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
17594 | { | |
17595 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
17596 | |
17597 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
17598 | |
17599 | return fragp->fr_var - old_var; | |
17600 | } | |
17601 | ||
df58fc94 RS |
17602 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
17603 | { | |
17604 | offsetT old_var = fragp->fr_var; | |
17605 | offsetT new_var = 4; | |
17606 | ||
17607 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
17608 | new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE); | |
17609 | if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
17610 | new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE); | |
17611 | fragp->fr_var = new_var; | |
17612 | ||
17613 | return new_var - old_var; | |
17614 | } | |
17615 | ||
252b5132 RH |
17616 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
17617 | return 0; | |
17618 | ||
c4e7957c | 17619 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
17620 | { |
17621 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
17622 | return 0; | |
17623 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
17624 | return 2; | |
17625 | } | |
17626 | else | |
17627 | { | |
17628 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
17629 | return 0; | |
17630 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
17631 | return -2; | |
17632 | } | |
17633 | ||
17634 | return 0; | |
17635 | } | |
17636 | ||
17637 | /* Convert a machine dependent frag. */ | |
17638 | ||
17639 | void | |
17a2f251 | 17640 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 17641 | { |
4a6a3df4 AO |
17642 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
17643 | { | |
17644 | bfd_byte *buf; | |
17645 | unsigned long insn; | |
17646 | expressionS exp; | |
17647 | fixS *fixp; | |
b34976b6 | 17648 | |
4a6a3df4 AO |
17649 | buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; |
17650 | ||
17651 | if (target_big_endian) | |
17652 | insn = bfd_getb32 (buf); | |
17653 | else | |
17654 | insn = bfd_getl32 (buf); | |
b34976b6 | 17655 | |
4a6a3df4 AO |
17656 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
17657 | { | |
17658 | /* We generate a fixup instead of applying it right now | |
17659 | because, if there are linker relaxations, we're going to | |
17660 | need the relocations. */ | |
17661 | exp.X_op = O_symbol; | |
17662 | exp.X_add_symbol = fragp->fr_symbol; | |
17663 | exp.X_add_number = fragp->fr_offset; | |
17664 | ||
17665 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 17666 | 4, &exp, TRUE, BFD_RELOC_16_PCREL_S2); |
4a6a3df4 AO |
17667 | fixp->fx_file = fragp->fr_file; |
17668 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 17669 | |
2132e3a3 | 17670 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
17671 | buf += 4; |
17672 | } | |
17673 | else | |
17674 | { | |
17675 | int i; | |
17676 | ||
17677 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
5c4f07ba | 17678 | _("Relaxed out-of-range branch into a jump")); |
4a6a3df4 AO |
17679 | |
17680 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
17681 | goto uncond; | |
17682 | ||
17683 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
17684 | { | |
17685 | /* Reverse the branch. */ | |
17686 | switch ((insn >> 28) & 0xf) | |
17687 | { | |
17688 | case 4: | |
17689 | /* bc[0-3][tf]l? and bc1any[24][ft] instructions can | |
17690 | have the condition reversed by tweaking a single | |
17691 | bit, and their opcodes all have 0x4???????. */ | |
9c2799c2 | 17692 | gas_assert ((insn & 0xf1000000) == 0x41000000); |
4a6a3df4 AO |
17693 | insn ^= 0x00010000; |
17694 | break; | |
17695 | ||
17696 | case 0: | |
17697 | /* bltz 0x04000000 bgez 0x04010000 | |
54f4ddb3 | 17698 | bltzal 0x04100000 bgezal 0x04110000 */ |
9c2799c2 | 17699 | gas_assert ((insn & 0xfc0e0000) == 0x04000000); |
4a6a3df4 AO |
17700 | insn ^= 0x00010000; |
17701 | break; | |
b34976b6 | 17702 | |
4a6a3df4 AO |
17703 | case 1: |
17704 | /* beq 0x10000000 bne 0x14000000 | |
54f4ddb3 | 17705 | blez 0x18000000 bgtz 0x1c000000 */ |
4a6a3df4 AO |
17706 | insn ^= 0x04000000; |
17707 | break; | |
17708 | ||
17709 | default: | |
17710 | abort (); | |
17711 | } | |
17712 | } | |
17713 | ||
17714 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
17715 | { | |
17716 | /* Clear the and-link bit. */ | |
9c2799c2 | 17717 | gas_assert ((insn & 0xfc1c0000) == 0x04100000); |
4a6a3df4 | 17718 | |
54f4ddb3 TS |
17719 | /* bltzal 0x04100000 bgezal 0x04110000 |
17720 | bltzall 0x04120000 bgezall 0x04130000 */ | |
4a6a3df4 AO |
17721 | insn &= ~0x00100000; |
17722 | } | |
17723 | ||
17724 | /* Branch over the branch (if the branch was likely) or the | |
17725 | full jump (not likely case). Compute the offset from the | |
17726 | current instruction to branch to. */ | |
17727 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
17728 | i = 16; | |
17729 | else | |
17730 | { | |
17731 | /* How many bytes in instructions we've already emitted? */ | |
17732 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
17733 | /* How many bytes in instructions from here to the end? */ | |
17734 | i = fragp->fr_var - i; | |
17735 | } | |
17736 | /* Convert to instruction count. */ | |
17737 | i >>= 2; | |
17738 | /* Branch counts from the next instruction. */ | |
b34976b6 | 17739 | i--; |
4a6a3df4 AO |
17740 | insn |= i; |
17741 | /* Branch over the jump. */ | |
2132e3a3 | 17742 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
17743 | buf += 4; |
17744 | ||
54f4ddb3 | 17745 | /* nop */ |
2132e3a3 | 17746 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
17747 | buf += 4; |
17748 | ||
17749 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
17750 | { | |
17751 | /* beql $0, $0, 2f */ | |
17752 | insn = 0x50000000; | |
17753 | /* Compute the PC offset from the current instruction to | |
17754 | the end of the variable frag. */ | |
17755 | /* How many bytes in instructions we've already emitted? */ | |
17756 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
17757 | /* How many bytes in instructions from here to the end? */ | |
17758 | i = fragp->fr_var - i; | |
17759 | /* Convert to instruction count. */ | |
17760 | i >>= 2; | |
17761 | /* Don't decrement i, because we want to branch over the | |
17762 | delay slot. */ | |
17763 | ||
17764 | insn |= i; | |
2132e3a3 | 17765 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
17766 | buf += 4; |
17767 | ||
2132e3a3 | 17768 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
17769 | buf += 4; |
17770 | } | |
17771 | ||
17772 | uncond: | |
17773 | if (mips_pic == NO_PIC) | |
17774 | { | |
17775 | /* j or jal. */ | |
17776 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
17777 | ? 0x0c000000 : 0x08000000); | |
17778 | exp.X_op = O_symbol; | |
17779 | exp.X_add_symbol = fragp->fr_symbol; | |
17780 | exp.X_add_number = fragp->fr_offset; | |
17781 | ||
17782 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 17783 | 4, &exp, FALSE, BFD_RELOC_MIPS_JMP); |
4a6a3df4 AO |
17784 | fixp->fx_file = fragp->fr_file; |
17785 | fixp->fx_line = fragp->fr_line; | |
17786 | ||
2132e3a3 | 17787 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
17788 | buf += 4; |
17789 | } | |
17790 | else | |
17791 | { | |
66b3e8da MR |
17792 | unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype); |
17793 | ||
4a6a3df4 | 17794 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ |
66b3e8da MR |
17795 | insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000; |
17796 | insn |= at << OP_SH_RT; | |
4a6a3df4 AO |
17797 | exp.X_op = O_symbol; |
17798 | exp.X_add_symbol = fragp->fr_symbol; | |
17799 | exp.X_add_number = fragp->fr_offset; | |
17800 | ||
17801 | if (fragp->fr_offset) | |
17802 | { | |
17803 | exp.X_add_symbol = make_expr_symbol (&exp); | |
17804 | exp.X_add_number = 0; | |
17805 | } | |
17806 | ||
17807 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 17808 | 4, &exp, FALSE, BFD_RELOC_MIPS_GOT16); |
4a6a3df4 AO |
17809 | fixp->fx_file = fragp->fr_file; |
17810 | fixp->fx_line = fragp->fr_line; | |
17811 | ||
2132e3a3 | 17812 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 | 17813 | buf += 4; |
b34976b6 | 17814 | |
4a6a3df4 AO |
17815 | if (mips_opts.isa == ISA_MIPS1) |
17816 | { | |
17817 | /* nop */ | |
2132e3a3 | 17818 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
17819 | buf += 4; |
17820 | } | |
17821 | ||
17822 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
66b3e8da MR |
17823 | insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000; |
17824 | insn |= at << OP_SH_RS | at << OP_SH_RT; | |
4a6a3df4 AO |
17825 | |
17826 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 17827 | 4, &exp, FALSE, BFD_RELOC_LO16); |
4a6a3df4 AO |
17828 | fixp->fx_file = fragp->fr_file; |
17829 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 17830 | |
2132e3a3 | 17831 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
17832 | buf += 4; |
17833 | ||
17834 | /* j(al)r $at. */ | |
17835 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
66b3e8da | 17836 | insn = 0x0000f809; |
4a6a3df4 | 17837 | else |
66b3e8da MR |
17838 | insn = 0x00000008; |
17839 | insn |= at << OP_SH_RS; | |
4a6a3df4 | 17840 | |
2132e3a3 | 17841 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
17842 | buf += 4; |
17843 | } | |
17844 | } | |
17845 | ||
9c2799c2 | 17846 | gas_assert (buf == (bfd_byte *)fragp->fr_literal |
4a6a3df4 AO |
17847 | + fragp->fr_fix + fragp->fr_var); |
17848 | ||
17849 | fragp->fr_fix += fragp->fr_var; | |
17850 | ||
17851 | return; | |
17852 | } | |
17853 | ||
df58fc94 RS |
17854 | /* Relax microMIPS branches. */ |
17855 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) | |
17856 | { | |
17857 | bfd_byte *buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
17858 | bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); | |
17859 | bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype); | |
17860 | int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
2309ddf2 | 17861 | bfd_boolean short_ds; |
df58fc94 RS |
17862 | unsigned long insn; |
17863 | expressionS exp; | |
17864 | fixS *fixp; | |
17865 | ||
17866 | exp.X_op = O_symbol; | |
17867 | exp.X_add_symbol = fragp->fr_symbol; | |
17868 | exp.X_add_number = fragp->fr_offset; | |
17869 | ||
17870 | fragp->fr_fix += fragp->fr_var; | |
17871 | ||
17872 | /* Handle 16-bit branches that fit or are forced to fit. */ | |
17873 | if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
17874 | { | |
17875 | /* We generate a fixup instead of applying it right now, | |
17876 | because if there is linker relaxation, we're going to | |
17877 | need the relocations. */ | |
17878 | if (type == 'D') | |
17879 | fixp = fix_new_exp (fragp, | |
17880 | buf - (bfd_byte *) fragp->fr_literal, | |
17881 | 2, &exp, TRUE, | |
17882 | BFD_RELOC_MICROMIPS_10_PCREL_S1); | |
17883 | else if (type == 'E') | |
17884 | fixp = fix_new_exp (fragp, | |
17885 | buf - (bfd_byte *) fragp->fr_literal, | |
17886 | 2, &exp, TRUE, | |
17887 | BFD_RELOC_MICROMIPS_7_PCREL_S1); | |
17888 | else | |
17889 | abort (); | |
17890 | ||
17891 | fixp->fx_file = fragp->fr_file; | |
17892 | fixp->fx_line = fragp->fr_line; | |
17893 | ||
17894 | /* These relocations can have an addend that won't fit in | |
17895 | 2 octets. */ | |
17896 | fixp->fx_no_overflow = 1; | |
17897 | ||
17898 | return; | |
17899 | } | |
17900 | ||
2309ddf2 | 17901 | /* Handle 32-bit branches that fit or are forced to fit. */ |
df58fc94 RS |
17902 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) |
17903 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
17904 | { | |
17905 | /* We generate a fixup instead of applying it right now, | |
17906 | because if there is linker relaxation, we're going to | |
17907 | need the relocations. */ | |
17908 | fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal, | |
17909 | 4, &exp, TRUE, BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
17910 | fixp->fx_file = fragp->fr_file; | |
17911 | fixp->fx_line = fragp->fr_line; | |
17912 | ||
17913 | if (type == 0) | |
17914 | return; | |
17915 | } | |
17916 | ||
17917 | /* Relax 16-bit branches to 32-bit branches. */ | |
17918 | if (type != 0) | |
17919 | { | |
17920 | if (target_big_endian) | |
17921 | insn = bfd_getb16 (buf); | |
17922 | else | |
17923 | insn = bfd_getl16 (buf); | |
17924 | ||
17925 | if ((insn & 0xfc00) == 0xcc00) /* b16 */ | |
17926 | insn = 0x94000000; /* beq */ | |
17927 | else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */ | |
17928 | { | |
17929 | unsigned long regno; | |
17930 | ||
17931 | regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD; | |
17932 | regno = micromips_to_32_reg_d_map [regno]; | |
17933 | insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */ | |
17934 | insn |= regno << MICROMIPSOP_SH_RS; | |
17935 | } | |
17936 | else | |
17937 | abort (); | |
17938 | ||
17939 | /* Nothing else to do, just write it out. */ | |
17940 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) | |
17941 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
17942 | { | |
17943 | md_number_to_chars ((char *) buf, insn >> 16, 2); | |
17944 | buf += 2; | |
17945 | md_number_to_chars ((char *) buf, insn & 0xffff, 2); | |
17946 | buf += 2; | |
17947 | ||
17948 | gas_assert (buf == ((bfd_byte *) fragp->fr_literal | |
17949 | + fragp->fr_fix)); | |
17950 | return; | |
17951 | } | |
17952 | } | |
17953 | else | |
17954 | { | |
17955 | unsigned long next; | |
17956 | ||
17957 | if (target_big_endian) | |
17958 | { | |
17959 | insn = bfd_getb16 (buf); | |
17960 | next = bfd_getb16 (buf + 2); | |
17961 | } | |
17962 | else | |
17963 | { | |
17964 | insn = bfd_getl16 (buf); | |
17965 | next = bfd_getl16 (buf + 2); | |
17966 | } | |
17967 | insn = (insn << 16) | next; | |
17968 | } | |
17969 | ||
17970 | /* Relax 32-bit branches to a sequence of instructions. */ | |
17971 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
17972 | _("Relaxed out-of-range branch into a jump")); | |
17973 | ||
2309ddf2 MR |
17974 | /* Set the short-delay-slot bit. */ |
17975 | short_ds = al && (insn & 0x02000000) != 0; | |
df58fc94 RS |
17976 | |
17977 | if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype)) | |
17978 | { | |
17979 | symbolS *l; | |
17980 | ||
17981 | /* Reverse the branch. */ | |
17982 | if ((insn & 0xfc000000) == 0x94000000 /* beq */ | |
17983 | || (insn & 0xfc000000) == 0xb4000000) /* bne */ | |
17984 | insn ^= 0x20000000; | |
17985 | else if ((insn & 0xffe00000) == 0x40000000 /* bltz */ | |
17986 | || (insn & 0xffe00000) == 0x40400000 /* bgez */ | |
17987 | || (insn & 0xffe00000) == 0x40800000 /* blez */ | |
17988 | || (insn & 0xffe00000) == 0x40c00000 /* bgtz */ | |
17989 | || (insn & 0xffe00000) == 0x40a00000 /* bnezc */ | |
17990 | || (insn & 0xffe00000) == 0x40e00000 /* beqzc */ | |
17991 | || (insn & 0xffe00000) == 0x40200000 /* bltzal */ | |
17992 | || (insn & 0xffe00000) == 0x40600000 /* bgezal */ | |
17993 | || (insn & 0xffe00000) == 0x42200000 /* bltzals */ | |
17994 | || (insn & 0xffe00000) == 0x42600000) /* bgezals */ | |
17995 | insn ^= 0x00400000; | |
17996 | else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */ | |
17997 | || (insn & 0xffe30000) == 0x43a00000 /* bc1t */ | |
17998 | || (insn & 0xffe30000) == 0x42800000 /* bc2f */ | |
17999 | || (insn & 0xffe30000) == 0x42a00000) /* bc2t */ | |
18000 | insn ^= 0x00200000; | |
18001 | else | |
18002 | abort (); | |
18003 | ||
18004 | if (al) | |
18005 | { | |
18006 | /* Clear the and-link and short-delay-slot bits. */ | |
18007 | gas_assert ((insn & 0xfda00000) == 0x40200000); | |
18008 | ||
18009 | /* bltzal 0x40200000 bgezal 0x40600000 */ | |
18010 | /* bltzals 0x42200000 bgezals 0x42600000 */ | |
18011 | insn &= ~0x02200000; | |
18012 | } | |
18013 | ||
18014 | /* Make a label at the end for use with the branch. */ | |
18015 | l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp); | |
18016 | micromips_label_inc (); | |
18017 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) | |
18018 | if (IS_ELF) | |
18019 | S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l))); | |
18020 | #endif | |
18021 | ||
18022 | /* Refer to it. */ | |
18023 | fixp = fix_new (fragp, buf - (bfd_byte *) fragp->fr_literal, | |
18024 | 4, l, 0, TRUE, BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
18025 | fixp->fx_file = fragp->fr_file; | |
18026 | fixp->fx_line = fragp->fr_line; | |
18027 | ||
18028 | /* Branch over the jump. */ | |
18029 | md_number_to_chars ((char *) buf, insn >> 16, 2); | |
18030 | buf += 2; | |
18031 | md_number_to_chars ((char *) buf, insn & 0xffff, 2); | |
18032 | buf += 2; | |
18033 | ||
18034 | if (!compact) | |
18035 | { | |
18036 | /* nop */ | |
18037 | insn = 0x0c00; | |
18038 | md_number_to_chars ((char *) buf, insn, 2); | |
18039 | buf += 2; | |
18040 | } | |
18041 | } | |
18042 | ||
18043 | if (mips_pic == NO_PIC) | |
18044 | { | |
2309ddf2 MR |
18045 | unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */ |
18046 | ||
df58fc94 RS |
18047 | /* j/jal/jals <sym> R_MICROMIPS_26_S1 */ |
18048 | insn = al ? jal : 0xd4000000; | |
18049 | ||
18050 | fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal, | |
18051 | 4, &exp, FALSE, BFD_RELOC_MICROMIPS_JMP); | |
18052 | fixp->fx_file = fragp->fr_file; | |
18053 | fixp->fx_line = fragp->fr_line; | |
18054 | ||
18055 | md_number_to_chars ((char *) buf, insn >> 16, 2); | |
18056 | buf += 2; | |
18057 | md_number_to_chars ((char *) buf, insn & 0xffff, 2); | |
18058 | buf += 2; | |
18059 | ||
18060 | if (compact) | |
18061 | { | |
18062 | /* nop */ | |
18063 | insn = 0x0c00; | |
18064 | md_number_to_chars ((char *) buf, insn, 2); | |
18065 | buf += 2; | |
18066 | } | |
18067 | } | |
18068 | else | |
18069 | { | |
18070 | unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype); | |
2309ddf2 MR |
18071 | unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */ |
18072 | unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */ | |
df58fc94 RS |
18073 | |
18074 | /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */ | |
18075 | insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000; | |
18076 | insn |= at << MICROMIPSOP_SH_RT; | |
18077 | ||
18078 | if (exp.X_add_number) | |
18079 | { | |
18080 | exp.X_add_symbol = make_expr_symbol (&exp); | |
18081 | exp.X_add_number = 0; | |
18082 | } | |
18083 | ||
18084 | fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal, | |
18085 | 4, &exp, FALSE, BFD_RELOC_MICROMIPS_GOT16); | |
18086 | fixp->fx_file = fragp->fr_file; | |
18087 | fixp->fx_line = fragp->fr_line; | |
18088 | ||
18089 | md_number_to_chars ((char *) buf, insn >> 16, 2); | |
18090 | buf += 2; | |
18091 | md_number_to_chars ((char *) buf, insn & 0xffff, 2); | |
18092 | buf += 2; | |
18093 | ||
18094 | /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */ | |
18095 | insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000; | |
18096 | insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS; | |
18097 | ||
18098 | fixp = fix_new_exp (fragp, buf - (bfd_byte *) fragp->fr_literal, | |
18099 | 4, &exp, FALSE, BFD_RELOC_MICROMIPS_LO16); | |
18100 | fixp->fx_file = fragp->fr_file; | |
18101 | fixp->fx_line = fragp->fr_line; | |
18102 | ||
18103 | md_number_to_chars ((char *) buf, insn >> 16, 2); | |
18104 | buf += 2; | |
18105 | md_number_to_chars ((char *) buf, insn & 0xffff, 2); | |
18106 | buf += 2; | |
18107 | ||
18108 | /* jr/jrc/jalr/jalrs $at */ | |
18109 | insn = al ? jalr : jr; | |
18110 | insn |= at << MICROMIPSOP_SH_MJ; | |
18111 | ||
18112 | md_number_to_chars ((char *) buf, insn & 0xffff, 2); | |
18113 | buf += 2; | |
18114 | } | |
18115 | ||
18116 | gas_assert (buf == (bfd_byte *) fragp->fr_literal + fragp->fr_fix); | |
18117 | return; | |
18118 | } | |
18119 | ||
252b5132 RH |
18120 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
18121 | { | |
18122 | int type; | |
3994f87e | 18123 | const struct mips16_immed_operand *op; |
b34976b6 | 18124 | bfd_boolean small, ext; |
252b5132 RH |
18125 | offsetT val; |
18126 | bfd_byte *buf; | |
18127 | unsigned long insn; | |
b34976b6 | 18128 | bfd_boolean use_extend; |
252b5132 RH |
18129 | unsigned short extend; |
18130 | ||
18131 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
18132 | op = mips16_immed_operands; | |
18133 | while (op->type != type) | |
18134 | ++op; | |
18135 | ||
18136 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
18137 | { | |
b34976b6 AM |
18138 | small = FALSE; |
18139 | ext = TRUE; | |
252b5132 RH |
18140 | } |
18141 | else | |
18142 | { | |
b34976b6 AM |
18143 | small = TRUE; |
18144 | ext = FALSE; | |
252b5132 RH |
18145 | } |
18146 | ||
5f5f22c0 | 18147 | val = resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
18148 | if (op->pcrel) |
18149 | { | |
18150 | addressT addr; | |
18151 | ||
18152 | addr = fragp->fr_address + fragp->fr_fix; | |
18153 | ||
18154 | /* The rules for the base address of a PC relative reloc are | |
18155 | complicated; see mips16_extended_frag. */ | |
18156 | if (type == 'p' || type == 'q') | |
18157 | { | |
18158 | addr += 2; | |
18159 | if (ext) | |
18160 | addr += 2; | |
18161 | /* Ignore the low bit in the target, since it will be | |
18162 | set for a text label. */ | |
18163 | if ((val & 1) != 0) | |
18164 | --val; | |
18165 | } | |
18166 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
18167 | addr -= 4; | |
18168 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
18169 | addr -= 2; | |
18170 | ||
18171 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
18172 | val -= addr; | |
18173 | ||
18174 | /* Make sure the section winds up with the alignment we have | |
18175 | assumed. */ | |
18176 | if (op->shift > 0) | |
18177 | record_alignment (asec, op->shift); | |
18178 | } | |
18179 | ||
18180 | if (ext | |
18181 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
18182 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
18183 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
18184 | _("extended instruction in delay slot")); | |
18185 | ||
18186 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
18187 | ||
18188 | if (target_big_endian) | |
18189 | insn = bfd_getb16 (buf); | |
18190 | else | |
18191 | insn = bfd_getl16 (buf); | |
18192 | ||
18193 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
18194 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
18195 | small, ext, &insn, &use_extend, &extend); | |
18196 | ||
18197 | if (use_extend) | |
18198 | { | |
2132e3a3 | 18199 | md_number_to_chars ((char *) buf, 0xf000 | extend, 2); |
252b5132 RH |
18200 | fragp->fr_fix += 2; |
18201 | buf += 2; | |
18202 | } | |
18203 | ||
2132e3a3 | 18204 | md_number_to_chars ((char *) buf, insn, 2); |
252b5132 RH |
18205 | fragp->fr_fix += 2; |
18206 | buf += 2; | |
18207 | } | |
18208 | else | |
18209 | { | |
df58fc94 RS |
18210 | relax_substateT subtype = fragp->fr_subtype; |
18211 | bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0; | |
18212 | bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0; | |
4d7206a2 RS |
18213 | int first, second; |
18214 | fixS *fixp; | |
252b5132 | 18215 | |
df58fc94 RS |
18216 | first = RELAX_FIRST (subtype); |
18217 | second = RELAX_SECOND (subtype); | |
4d7206a2 | 18218 | fixp = (fixS *) fragp->fr_opcode; |
252b5132 | 18219 | |
df58fc94 RS |
18220 | /* If the delay slot chosen does not match the size of the instruction, |
18221 | then emit a warning. */ | |
18222 | if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0) | |
18223 | || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)) | |
18224 | { | |
18225 | relax_substateT s; | |
18226 | const char *msg; | |
18227 | ||
18228 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
18229 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
18230 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
18231 | msg = macro_warning (s); | |
18232 | if (msg != NULL) | |
db9b2be4 | 18233 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
df58fc94 RS |
18234 | subtype &= ~s; |
18235 | } | |
18236 | ||
584892a6 | 18237 | /* Possibly emit a warning if we've chosen the longer option. */ |
df58fc94 | 18238 | if (use_second == second_longer) |
584892a6 | 18239 | { |
df58fc94 RS |
18240 | relax_substateT s; |
18241 | const char *msg; | |
18242 | ||
18243 | s = (subtype | |
18244 | & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT)); | |
18245 | msg = macro_warning (s); | |
18246 | if (msg != NULL) | |
db9b2be4 | 18247 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
df58fc94 | 18248 | subtype &= ~s; |
584892a6 RS |
18249 | } |
18250 | ||
4d7206a2 RS |
18251 | /* Go through all the fixups for the first sequence. Disable them |
18252 | (by marking them as done) if we're going to use the second | |
18253 | sequence instead. */ | |
18254 | while (fixp | |
18255 | && fixp->fx_frag == fragp | |
18256 | && fixp->fx_where < fragp->fr_fix - second) | |
18257 | { | |
df58fc94 | 18258 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18259 | fixp->fx_done = 1; |
18260 | fixp = fixp->fx_next; | |
18261 | } | |
252b5132 | 18262 | |
4d7206a2 RS |
18263 | /* Go through the fixups for the second sequence. Disable them if |
18264 | we're going to use the first sequence, otherwise adjust their | |
18265 | addresses to account for the relaxation. */ | |
18266 | while (fixp && fixp->fx_frag == fragp) | |
18267 | { | |
df58fc94 | 18268 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18269 | fixp->fx_where -= first; |
18270 | else | |
18271 | fixp->fx_done = 1; | |
18272 | fixp = fixp->fx_next; | |
18273 | } | |
18274 | ||
18275 | /* Now modify the frag contents. */ | |
df58fc94 | 18276 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18277 | { |
18278 | char *start; | |
18279 | ||
18280 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
18281 | memmove (start, start + first, second); | |
18282 | fragp->fr_fix -= first; | |
18283 | } | |
18284 | else | |
18285 | fragp->fr_fix -= second; | |
252b5132 RH |
18286 | } |
18287 | } | |
18288 | ||
18289 | #ifdef OBJ_ELF | |
18290 | ||
18291 | /* This function is called after the relocs have been generated. | |
18292 | We've been storing mips16 text labels as odd. Here we convert them | |
18293 | back to even for the convenience of the debugger. */ | |
18294 | ||
18295 | void | |
17a2f251 | 18296 | mips_frob_file_after_relocs (void) |
252b5132 RH |
18297 | { |
18298 | asymbol **syms; | |
18299 | unsigned int count, i; | |
18300 | ||
f43abd2b | 18301 | if (!IS_ELF) |
252b5132 RH |
18302 | return; |
18303 | ||
18304 | syms = bfd_get_outsymbols (stdoutput); | |
18305 | count = bfd_get_symcount (stdoutput); | |
18306 | for (i = 0; i < count; i++, syms++) | |
df58fc94 RS |
18307 | if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other) |
18308 | && ((*syms)->value & 1) != 0) | |
18309 | { | |
18310 | (*syms)->value &= ~1; | |
18311 | /* If the symbol has an odd size, it was probably computed | |
18312 | incorrectly, so adjust that as well. */ | |
18313 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
18314 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
18315 | } | |
252b5132 RH |
18316 | } |
18317 | ||
18318 | #endif | |
18319 | ||
a1facbec MR |
18320 | /* This function is called whenever a label is defined, including fake |
18321 | labels instantiated off the dot special symbol. It is used when | |
18322 | handling branch delays; if a branch has a label, we assume we cannot | |
18323 | move it. This also bumps the value of the symbol by 1 in compressed | |
18324 | code. */ | |
252b5132 RH |
18325 | |
18326 | void | |
a1facbec | 18327 | mips_record_label (symbolS *sym) |
252b5132 | 18328 | { |
a8dbcb85 | 18329 | segment_info_type *si = seg_info (now_seg); |
252b5132 RH |
18330 | struct insn_label_list *l; |
18331 | ||
18332 | if (free_insn_labels == NULL) | |
18333 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
18334 | else | |
18335 | { | |
18336 | l = free_insn_labels; | |
18337 | free_insn_labels = l->next; | |
18338 | } | |
18339 | ||
18340 | l->label = sym; | |
a8dbcb85 TS |
18341 | l->next = si->label_list; |
18342 | si->label_list = l; | |
a1facbec | 18343 | } |
07a53e5c | 18344 | |
a1facbec MR |
18345 | /* This function is called as tc_frob_label() whenever a label is defined |
18346 | and adds a DWARF-2 record we only want for true labels. */ | |
18347 | ||
18348 | void | |
18349 | mips_define_label (symbolS *sym) | |
18350 | { | |
18351 | mips_record_label (sym); | |
07a53e5c RH |
18352 | #ifdef OBJ_ELF |
18353 | dwarf2_emit_label (sym); | |
18354 | #endif | |
252b5132 RH |
18355 | } |
18356 | \f | |
18357 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
18358 | ||
18359 | /* Some special processing for a MIPS ELF file. */ | |
18360 | ||
18361 | void | |
17a2f251 | 18362 | mips_elf_final_processing (void) |
252b5132 RH |
18363 | { |
18364 | /* Write out the register information. */ | |
316f5878 | 18365 | if (mips_abi != N64_ABI) |
252b5132 RH |
18366 | { |
18367 | Elf32_RegInfo s; | |
18368 | ||
18369 | s.ri_gprmask = mips_gprmask; | |
18370 | s.ri_cprmask[0] = mips_cprmask[0]; | |
18371 | s.ri_cprmask[1] = mips_cprmask[1]; | |
18372 | s.ri_cprmask[2] = mips_cprmask[2]; | |
18373 | s.ri_cprmask[3] = mips_cprmask[3]; | |
18374 | /* The gp_value field is set by the MIPS ELF backend. */ | |
18375 | ||
18376 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
18377 | ((Elf32_External_RegInfo *) | |
18378 | mips_regmask_frag)); | |
18379 | } | |
18380 | else | |
18381 | { | |
18382 | Elf64_Internal_RegInfo s; | |
18383 | ||
18384 | s.ri_gprmask = mips_gprmask; | |
18385 | s.ri_pad = 0; | |
18386 | s.ri_cprmask[0] = mips_cprmask[0]; | |
18387 | s.ri_cprmask[1] = mips_cprmask[1]; | |
18388 | s.ri_cprmask[2] = mips_cprmask[2]; | |
18389 | s.ri_cprmask[3] = mips_cprmask[3]; | |
18390 | /* The gp_value field is set by the MIPS ELF backend. */ | |
18391 | ||
18392 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
18393 | ((Elf64_External_RegInfo *) | |
18394 | mips_regmask_frag)); | |
18395 | } | |
18396 | ||
18397 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
18398 | sort of BFD interface for this. */ | |
18399 | if (mips_any_noreorder) | |
18400 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
18401 | if (mips_pic != NO_PIC) | |
143d77c5 | 18402 | { |
252b5132 | 18403 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
18404 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
18405 | } | |
18406 | if (mips_abicalls) | |
18407 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 18408 | |
98d3f06f | 18409 | /* Set MIPS ELF flags for ASEs. */ |
74cd071d CF |
18410 | /* We may need to define a new flag for DSP ASE, and set this flag when |
18411 | file_ase_dsp is true. */ | |
8b082fb1 | 18412 | /* Same for DSP R2. */ |
ef2e4d86 CF |
18413 | /* We may need to define a new flag for MT ASE, and set this flag when |
18414 | file_ase_mt is true. */ | |
a4672219 TS |
18415 | if (file_ase_mips16) |
18416 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
df58fc94 RS |
18417 | if (file_ase_micromips) |
18418 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS; | |
1f25f5d3 CD |
18419 | #if 0 /* XXX FIXME */ |
18420 | if (file_ase_mips3d) | |
18421 | elf_elfheader (stdoutput)->e_flags |= ???; | |
18422 | #endif | |
deec1734 CD |
18423 | if (file_ase_mdmx) |
18424 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; | |
1f25f5d3 | 18425 | |
bdaaa2e1 | 18426 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 18427 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 18428 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 18429 | else if (mips_abi == O64_ABI) |
252b5132 | 18430 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 18431 | else if (mips_abi == EABI_ABI) |
252b5132 | 18432 | { |
316f5878 | 18433 | if (!file_mips_gp32) |
252b5132 RH |
18434 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
18435 | else | |
18436 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
18437 | } | |
316f5878 | 18438 | else if (mips_abi == N32_ABI) |
be00bddd TS |
18439 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
18440 | ||
c9914766 | 18441 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
18442 | |
18443 | if (mips_32bitmode) | |
18444 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
ad3fea08 TS |
18445 | |
18446 | #if 0 /* XXX FIXME */ | |
18447 | /* 32 bit code with 64 bit FP registers. */ | |
18448 | if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
18449 | elf_elfheader (stdoutput)->e_flags |= ???; | |
18450 | #endif | |
252b5132 RH |
18451 | } |
18452 | ||
18453 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
18454 | \f | |
beae10d5 | 18455 | typedef struct proc { |
9b2f1d35 EC |
18456 | symbolS *func_sym; |
18457 | symbolS *func_end_sym; | |
beae10d5 KH |
18458 | unsigned long reg_mask; |
18459 | unsigned long reg_offset; | |
18460 | unsigned long fpreg_mask; | |
18461 | unsigned long fpreg_offset; | |
18462 | unsigned long frame_offset; | |
18463 | unsigned long frame_reg; | |
18464 | unsigned long pc_reg; | |
18465 | } procS; | |
252b5132 RH |
18466 | |
18467 | static procS cur_proc; | |
18468 | static procS *cur_proc_ptr; | |
18469 | static int numprocs; | |
18470 | ||
df58fc94 RS |
18471 | /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop |
18472 | as "2", and a normal nop as "0". */ | |
18473 | ||
18474 | #define NOP_OPCODE_MIPS 0 | |
18475 | #define NOP_OPCODE_MIPS16 1 | |
18476 | #define NOP_OPCODE_MICROMIPS 2 | |
742a56fe RS |
18477 | |
18478 | char | |
18479 | mips_nop_opcode (void) | |
18480 | { | |
df58fc94 RS |
18481 | if (seg_info (now_seg)->tc_segment_info_data.micromips) |
18482 | return NOP_OPCODE_MICROMIPS; | |
18483 | else if (seg_info (now_seg)->tc_segment_info_data.mips16) | |
18484 | return NOP_OPCODE_MIPS16; | |
18485 | else | |
18486 | return NOP_OPCODE_MIPS; | |
742a56fe RS |
18487 | } |
18488 | ||
df58fc94 RS |
18489 | /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use |
18490 | 32-bit microMIPS NOPs here (if applicable). */ | |
a19d8eb0 | 18491 | |
0a9ef439 | 18492 | void |
17a2f251 | 18493 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 18494 | { |
df58fc94 | 18495 | char nop_opcode; |
742a56fe | 18496 | char *p; |
c67a084a NC |
18497 | int bytes, size, excess; |
18498 | valueT opcode; | |
742a56fe | 18499 | |
0a9ef439 RH |
18500 | if (fragp->fr_type != rs_align_code) |
18501 | return; | |
18502 | ||
742a56fe | 18503 | p = fragp->fr_literal + fragp->fr_fix; |
df58fc94 RS |
18504 | nop_opcode = *p; |
18505 | switch (nop_opcode) | |
a19d8eb0 | 18506 | { |
df58fc94 RS |
18507 | case NOP_OPCODE_MICROMIPS: |
18508 | opcode = micromips_nop32_insn.insn_opcode; | |
18509 | size = 4; | |
18510 | break; | |
18511 | case NOP_OPCODE_MIPS16: | |
c67a084a NC |
18512 | opcode = mips16_nop_insn.insn_opcode; |
18513 | size = 2; | |
df58fc94 RS |
18514 | break; |
18515 | case NOP_OPCODE_MIPS: | |
18516 | default: | |
c67a084a NC |
18517 | opcode = nop_insn.insn_opcode; |
18518 | size = 4; | |
df58fc94 | 18519 | break; |
c67a084a | 18520 | } |
a19d8eb0 | 18521 | |
c67a084a NC |
18522 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
18523 | excess = bytes % size; | |
df58fc94 RS |
18524 | |
18525 | /* Handle the leading part if we're not inserting a whole number of | |
18526 | instructions, and make it the end of the fixed part of the frag. | |
18527 | Try to fit in a short microMIPS NOP if applicable and possible, | |
18528 | and use zeroes otherwise. */ | |
18529 | gas_assert (excess < 4); | |
18530 | fragp->fr_fix += excess; | |
18531 | switch (excess) | |
c67a084a | 18532 | { |
df58fc94 RS |
18533 | case 3: |
18534 | *p++ = '\0'; | |
18535 | /* Fall through. */ | |
18536 | case 2: | |
18537 | if (nop_opcode == NOP_OPCODE_MICROMIPS) | |
18538 | { | |
18539 | md_number_to_chars (p, micromips_nop16_insn.insn_opcode, 2); | |
18540 | p += 2; | |
18541 | break; | |
18542 | } | |
18543 | *p++ = '\0'; | |
18544 | /* Fall through. */ | |
18545 | case 1: | |
18546 | *p++ = '\0'; | |
18547 | /* Fall through. */ | |
18548 | case 0: | |
18549 | break; | |
a19d8eb0 | 18550 | } |
c67a084a NC |
18551 | |
18552 | md_number_to_chars (p, opcode, size); | |
18553 | fragp->fr_var = size; | |
a19d8eb0 CP |
18554 | } |
18555 | ||
252b5132 | 18556 | static void |
17a2f251 | 18557 | md_obj_begin (void) |
252b5132 RH |
18558 | { |
18559 | } | |
18560 | ||
18561 | static void | |
17a2f251 | 18562 | md_obj_end (void) |
252b5132 | 18563 | { |
54f4ddb3 | 18564 | /* Check for premature end, nesting errors, etc. */ |
252b5132 | 18565 | if (cur_proc_ptr) |
9a41af64 | 18566 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
18567 | } |
18568 | ||
18569 | static long | |
17a2f251 | 18570 | get_number (void) |
252b5132 RH |
18571 | { |
18572 | int negative = 0; | |
18573 | long val = 0; | |
18574 | ||
18575 | if (*input_line_pointer == '-') | |
18576 | { | |
18577 | ++input_line_pointer; | |
18578 | negative = 1; | |
18579 | } | |
3882b010 | 18580 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 18581 | as_bad (_("expected simple number")); |
252b5132 RH |
18582 | if (input_line_pointer[0] == '0') |
18583 | { | |
18584 | if (input_line_pointer[1] == 'x') | |
18585 | { | |
18586 | input_line_pointer += 2; | |
3882b010 | 18587 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
18588 | { |
18589 | val <<= 4; | |
18590 | val |= hex_value (*input_line_pointer++); | |
18591 | } | |
18592 | return negative ? -val : val; | |
18593 | } | |
18594 | else | |
18595 | { | |
18596 | ++input_line_pointer; | |
3882b010 | 18597 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
18598 | { |
18599 | val <<= 3; | |
18600 | val |= *input_line_pointer++ - '0'; | |
18601 | } | |
18602 | return negative ? -val : val; | |
18603 | } | |
18604 | } | |
3882b010 | 18605 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
18606 | { |
18607 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
18608 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 18609 | as_warn (_("invalid number")); |
252b5132 RH |
18610 | return -1; |
18611 | } | |
3882b010 | 18612 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
18613 | { |
18614 | val *= 10; | |
18615 | val += *input_line_pointer++ - '0'; | |
18616 | } | |
18617 | return negative ? -val : val; | |
18618 | } | |
18619 | ||
18620 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
18621 | is an initial number which is the ECOFF file index. In the non-ECOFF |
18622 | case .file implies DWARF-2. */ | |
18623 | ||
18624 | static void | |
17a2f251 | 18625 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 18626 | { |
ecb4347a DJ |
18627 | static int first_file_directive = 0; |
18628 | ||
c5dd6aab DJ |
18629 | if (ECOFF_DEBUGGING) |
18630 | { | |
18631 | get_number (); | |
18632 | s_app_file (0); | |
18633 | } | |
18634 | else | |
ecb4347a DJ |
18635 | { |
18636 | char *filename; | |
18637 | ||
18638 | filename = dwarf2_directive_file (0); | |
18639 | ||
18640 | /* Versions of GCC up to 3.1 start files with a ".file" | |
18641 | directive even for stabs output. Make sure that this | |
18642 | ".file" is handled. Note that you need a version of GCC | |
18643 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
18644 | if (filename != NULL && ! first_file_directive) | |
18645 | { | |
18646 | (void) new_logical_line (filename, -1); | |
c04f5787 | 18647 | s_app_file_string (filename, 0); |
ecb4347a DJ |
18648 | } |
18649 | first_file_directive = 1; | |
18650 | } | |
c5dd6aab DJ |
18651 | } |
18652 | ||
18653 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
18654 | |
18655 | static void | |
17a2f251 | 18656 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 18657 | { |
c5dd6aab DJ |
18658 | if (!ECOFF_DEBUGGING) |
18659 | dwarf2_directive_loc (0); | |
252b5132 RH |
18660 | } |
18661 | ||
252b5132 RH |
18662 | /* The .end directive. */ |
18663 | ||
18664 | static void | |
17a2f251 | 18665 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
18666 | { |
18667 | symbolS *p; | |
252b5132 | 18668 | |
7a621144 DJ |
18669 | /* Following functions need their own .frame and .cprestore directives. */ |
18670 | mips_frame_reg_valid = 0; | |
18671 | mips_cprestore_valid = 0; | |
18672 | ||
252b5132 RH |
18673 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
18674 | { | |
18675 | p = get_symbol (); | |
18676 | demand_empty_rest_of_line (); | |
18677 | } | |
18678 | else | |
18679 | p = NULL; | |
18680 | ||
14949570 | 18681 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
18682 | as_warn (_(".end not in text section")); |
18683 | ||
18684 | if (!cur_proc_ptr) | |
18685 | { | |
18686 | as_warn (_(".end directive without a preceding .ent directive.")); | |
18687 | demand_empty_rest_of_line (); | |
18688 | return; | |
18689 | } | |
18690 | ||
18691 | if (p != NULL) | |
18692 | { | |
9c2799c2 | 18693 | gas_assert (S_GET_NAME (p)); |
9b2f1d35 | 18694 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
252b5132 | 18695 | as_warn (_(".end symbol does not match .ent symbol.")); |
ecb4347a DJ |
18696 | |
18697 | if (debug_type == DEBUG_STABS) | |
18698 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
18699 | S_GET_NAME (p)); | |
252b5132 RH |
18700 | } |
18701 | else | |
18702 | as_warn (_(".end directive missing or unknown symbol")); | |
18703 | ||
2132e3a3 | 18704 | #ifdef OBJ_ELF |
9b2f1d35 EC |
18705 | /* Create an expression to calculate the size of the function. */ |
18706 | if (p && cur_proc_ptr) | |
18707 | { | |
18708 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
18709 | expressionS *exp = xmalloc (sizeof (expressionS)); | |
18710 | ||
18711 | obj->size = exp; | |
18712 | exp->X_op = O_subtract; | |
18713 | exp->X_add_symbol = symbol_temp_new_now (); | |
18714 | exp->X_op_symbol = p; | |
18715 | exp->X_add_number = 0; | |
18716 | ||
18717 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
18718 | } | |
18719 | ||
ecb4347a | 18720 | /* Generate a .pdr section. */ |
f43abd2b | 18721 | if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr) |
ecb4347a DJ |
18722 | { |
18723 | segT saved_seg = now_seg; | |
18724 | subsegT saved_subseg = now_subseg; | |
ecb4347a DJ |
18725 | expressionS exp; |
18726 | char *fragp; | |
252b5132 | 18727 | |
252b5132 | 18728 | #ifdef md_flush_pending_output |
ecb4347a | 18729 | md_flush_pending_output (); |
252b5132 RH |
18730 | #endif |
18731 | ||
9c2799c2 | 18732 | gas_assert (pdr_seg); |
ecb4347a | 18733 | subseg_set (pdr_seg, 0); |
252b5132 | 18734 | |
ecb4347a DJ |
18735 | /* Write the symbol. */ |
18736 | exp.X_op = O_symbol; | |
18737 | exp.X_add_symbol = p; | |
18738 | exp.X_add_number = 0; | |
18739 | emit_expr (&exp, 4); | |
252b5132 | 18740 | |
ecb4347a | 18741 | fragp = frag_more (7 * 4); |
252b5132 | 18742 | |
17a2f251 TS |
18743 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
18744 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
18745 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
18746 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
18747 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
18748 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
18749 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 18750 | |
ecb4347a DJ |
18751 | subseg_set (saved_seg, saved_subseg); |
18752 | } | |
18753 | #endif /* OBJ_ELF */ | |
252b5132 RH |
18754 | |
18755 | cur_proc_ptr = NULL; | |
18756 | } | |
18757 | ||
18758 | /* The .aent and .ent directives. */ | |
18759 | ||
18760 | static void | |
17a2f251 | 18761 | s_mips_ent (int aent) |
252b5132 | 18762 | { |
252b5132 | 18763 | symbolS *symbolP; |
252b5132 RH |
18764 | |
18765 | symbolP = get_symbol (); | |
18766 | if (*input_line_pointer == ',') | |
f9419b05 | 18767 | ++input_line_pointer; |
252b5132 | 18768 | SKIP_WHITESPACE (); |
3882b010 | 18769 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 18770 | || *input_line_pointer == '-') |
874e8986 | 18771 | get_number (); |
252b5132 | 18772 | |
14949570 | 18773 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
18774 | as_warn (_(".ent or .aent not in text section.")); |
18775 | ||
18776 | if (!aent && cur_proc_ptr) | |
9a41af64 | 18777 | as_warn (_("missing .end")); |
252b5132 RH |
18778 | |
18779 | if (!aent) | |
18780 | { | |
7a621144 DJ |
18781 | /* This function needs its own .frame and .cprestore directives. */ |
18782 | mips_frame_reg_valid = 0; | |
18783 | mips_cprestore_valid = 0; | |
18784 | ||
252b5132 RH |
18785 | cur_proc_ptr = &cur_proc; |
18786 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
18787 | ||
9b2f1d35 | 18788 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 18789 | |
f9419b05 | 18790 | ++numprocs; |
ecb4347a DJ |
18791 | |
18792 | if (debug_type == DEBUG_STABS) | |
18793 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
18794 | S_GET_NAME (symbolP)); | |
252b5132 RH |
18795 | } |
18796 | ||
7c0fc524 MR |
18797 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
18798 | ||
252b5132 RH |
18799 | demand_empty_rest_of_line (); |
18800 | } | |
18801 | ||
18802 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 18803 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 18804 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 18805 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
18806 | symbol table (in the mdebug section). */ |
18807 | ||
18808 | static void | |
17a2f251 | 18809 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 18810 | { |
ecb4347a | 18811 | #ifdef OBJ_ELF |
f43abd2b | 18812 | if (IS_ELF && !ECOFF_DEBUGGING) |
ecb4347a DJ |
18813 | { |
18814 | long val; | |
252b5132 | 18815 | |
ecb4347a DJ |
18816 | if (cur_proc_ptr == (procS *) NULL) |
18817 | { | |
18818 | as_warn (_(".frame outside of .ent")); | |
18819 | demand_empty_rest_of_line (); | |
18820 | return; | |
18821 | } | |
252b5132 | 18822 | |
ecb4347a DJ |
18823 | cur_proc_ptr->frame_reg = tc_get_register (1); |
18824 | ||
18825 | SKIP_WHITESPACE (); | |
18826 | if (*input_line_pointer++ != ',' | |
18827 | || get_absolute_expression_and_terminator (&val) != ',') | |
18828 | { | |
18829 | as_warn (_("Bad .frame directive")); | |
18830 | --input_line_pointer; | |
18831 | demand_empty_rest_of_line (); | |
18832 | return; | |
18833 | } | |
252b5132 | 18834 | |
ecb4347a DJ |
18835 | cur_proc_ptr->frame_offset = val; |
18836 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 18837 | |
252b5132 | 18838 | demand_empty_rest_of_line (); |
252b5132 | 18839 | } |
ecb4347a DJ |
18840 | else |
18841 | #endif /* OBJ_ELF */ | |
18842 | s_ignore (ignore); | |
252b5132 RH |
18843 | } |
18844 | ||
bdaaa2e1 KH |
18845 | /* The .fmask and .mask directives. If the mdebug section is present |
18846 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 18847 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 18848 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
18849 | make reference to the ecoff symbol table (in the mdebug section). */ |
18850 | ||
18851 | static void | |
17a2f251 | 18852 | s_mips_mask (int reg_type) |
252b5132 | 18853 | { |
ecb4347a | 18854 | #ifdef OBJ_ELF |
f43abd2b | 18855 | if (IS_ELF && !ECOFF_DEBUGGING) |
252b5132 | 18856 | { |
ecb4347a | 18857 | long mask, off; |
252b5132 | 18858 | |
ecb4347a DJ |
18859 | if (cur_proc_ptr == (procS *) NULL) |
18860 | { | |
18861 | as_warn (_(".mask/.fmask outside of .ent")); | |
18862 | demand_empty_rest_of_line (); | |
18863 | return; | |
18864 | } | |
252b5132 | 18865 | |
ecb4347a DJ |
18866 | if (get_absolute_expression_and_terminator (&mask) != ',') |
18867 | { | |
18868 | as_warn (_("Bad .mask/.fmask directive")); | |
18869 | --input_line_pointer; | |
18870 | demand_empty_rest_of_line (); | |
18871 | return; | |
18872 | } | |
252b5132 | 18873 | |
ecb4347a DJ |
18874 | off = get_absolute_expression (); |
18875 | ||
18876 | if (reg_type == 'F') | |
18877 | { | |
18878 | cur_proc_ptr->fpreg_mask = mask; | |
18879 | cur_proc_ptr->fpreg_offset = off; | |
18880 | } | |
18881 | else | |
18882 | { | |
18883 | cur_proc_ptr->reg_mask = mask; | |
18884 | cur_proc_ptr->reg_offset = off; | |
18885 | } | |
18886 | ||
18887 | demand_empty_rest_of_line (); | |
252b5132 RH |
18888 | } |
18889 | else | |
ecb4347a DJ |
18890 | #endif /* OBJ_ELF */ |
18891 | s_ignore (reg_type); | |
252b5132 RH |
18892 | } |
18893 | ||
316f5878 RS |
18894 | /* A table describing all the processors gas knows about. Names are |
18895 | matched in the order listed. | |
e7af610e | 18896 | |
316f5878 RS |
18897 | To ease comparison, please keep this table in the same order as |
18898 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
18899 | static const struct mips_cpu_info mips_cpu_info_table[] = |
18900 | { | |
316f5878 | 18901 | /* Entries for generic ISAs */ |
ad3fea08 TS |
18902 | { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 }, |
18903 | { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 }, | |
18904 | { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 }, | |
18905 | { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 }, | |
18906 | { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 }, | |
18907 | { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 }, | |
18908 | { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18909 | { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 }, | |
18910 | { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 }, | |
316f5878 RS |
18911 | |
18912 | /* MIPS I */ | |
ad3fea08 TS |
18913 | { "r3000", 0, ISA_MIPS1, CPU_R3000 }, |
18914 | { "r2000", 0, ISA_MIPS1, CPU_R3000 }, | |
18915 | { "r3900", 0, ISA_MIPS1, CPU_R3900 }, | |
316f5878 RS |
18916 | |
18917 | /* MIPS II */ | |
ad3fea08 | 18918 | { "r6000", 0, ISA_MIPS2, CPU_R6000 }, |
316f5878 RS |
18919 | |
18920 | /* MIPS III */ | |
ad3fea08 TS |
18921 | { "r4000", 0, ISA_MIPS3, CPU_R4000 }, |
18922 | { "r4010", 0, ISA_MIPS2, CPU_R4010 }, | |
18923 | { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, | |
18924 | { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, | |
18925 | { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, | |
18926 | { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, | |
18927 | { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, | |
18928 | { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, | |
18929 | { "r4400", 0, ISA_MIPS3, CPU_R4400 }, | |
18930 | { "r4600", 0, ISA_MIPS3, CPU_R4600 }, | |
18931 | { "orion", 0, ISA_MIPS3, CPU_R4600 }, | |
18932 | { "r4650", 0, ISA_MIPS3, CPU_R4650 }, | |
b15591bb AN |
18933 | /* ST Microelectronics Loongson 2E and 2F cores */ |
18934 | { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E }, | |
18935 | { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F }, | |
316f5878 RS |
18936 | |
18937 | /* MIPS IV */ | |
ad3fea08 TS |
18938 | { "r8000", 0, ISA_MIPS4, CPU_R8000 }, |
18939 | { "r10000", 0, ISA_MIPS4, CPU_R10000 }, | |
18940 | { "r12000", 0, ISA_MIPS4, CPU_R12000 }, | |
3aa3176b TS |
18941 | { "r14000", 0, ISA_MIPS4, CPU_R14000 }, |
18942 | { "r16000", 0, ISA_MIPS4, CPU_R16000 }, | |
ad3fea08 TS |
18943 | { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, |
18944 | { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, | |
18945 | { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, | |
18946 | { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, | |
18947 | { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, | |
18948 | { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, | |
18949 | { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, | |
18950 | { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, | |
18951 | { "rm7000", 0, ISA_MIPS4, CPU_RM7000 }, | |
18952 | { "rm9000", 0, ISA_MIPS4, CPU_RM9000 }, | |
316f5878 RS |
18953 | |
18954 | /* MIPS 32 */ | |
ad3fea08 TS |
18955 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32 }, |
18956 | { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, | |
18957 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, | |
18958 | { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 }, | |
18959 | ||
18960 | /* MIPS 32 Release 2 */ | |
18961 | { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18962 | { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18963 | { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18964 | { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18965 | { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18966 | { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
b5503c7b MR |
18967 | { "m14k", MIPS_CPU_ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, |
18968 | { "m14kc", MIPS_CPU_ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ad3fea08 | 18969 | { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 | 18970 | { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
ad3fea08 | 18971 | { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 RS |
18972 | { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
18973 | /* Deprecated forms of the above. */ | |
18974 | { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ad3fea08 | 18975 | { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 18976 | /* 24KE is a 24K with DSP ASE, other ASEs are optional. */ |
ad3fea08 | 18977 | { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 | 18978 | { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
ad3fea08 | 18979 | { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 RS |
18980 | { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
18981 | /* Deprecated forms of the above. */ | |
18982 | { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
65263ce3 | 18983 | { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 18984 | /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */ |
a360e743 TS |
18985 | { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
18986 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
18987 | { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
18988 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
a360e743 TS |
18989 | { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
18990 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
18991 | { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
18992 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
18993 | /* Deprecated forms of the above. */ | |
18994 | { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
18995 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
a360e743 TS |
18996 | { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
18997 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
18998 | /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */ |
18999 | { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
19000 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
19001 | { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
19002 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
19003 | { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
19004 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
19005 | { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
19006 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19007 | { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
19008 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19009 | /* Deprecated forms of the above. */ | |
19010 | { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
19011 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
19012 | { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
19013 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
30f8113a SL |
19014 | /* 1004K cores are multiprocessor versions of the 34K. */ |
19015 | { "1004kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
19016 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19017 | { "1004kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
19018 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19019 | { "1004kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
19020 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19021 | { "1004kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
19022 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
32b26a03 | 19023 | |
316f5878 | 19024 | /* MIPS 64 */ |
ad3fea08 TS |
19025 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, |
19026 | { "5kf", 0, ISA_MIPS64, CPU_MIPS64 }, | |
19027 | { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
7764b395 | 19028 | { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, |
ad3fea08 | 19029 | |
c7a23324 | 19030 | /* Broadcom SB-1 CPU core */ |
65263ce3 TS |
19031 | { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, |
19032 | ISA_MIPS64, CPU_SB1 }, | |
1e85aad8 JW |
19033 | /* Broadcom SB-1A CPU core */ |
19034 | { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, | |
19035 | ISA_MIPS64, CPU_SB1 }, | |
d051516a NC |
19036 | |
19037 | { "loongson3a", 0, ISA_MIPS64, CPU_LOONGSON_3A }, | |
e7af610e | 19038 | |
ed163775 MR |
19039 | /* MIPS 64 Release 2 */ |
19040 | ||
967344c6 AN |
19041 | /* Cavium Networks Octeon CPU core */ |
19042 | { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON }, | |
19043 | ||
52b6b6b9 JM |
19044 | /* RMI Xlr */ |
19045 | { "xlr", 0, ISA_MIPS64, CPU_XLR }, | |
19046 | ||
316f5878 RS |
19047 | /* End marker */ |
19048 | { NULL, 0, 0, 0 } | |
19049 | }; | |
e7af610e | 19050 | |
84ea6cf2 | 19051 | |
316f5878 RS |
19052 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
19053 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 19054 | |
316f5878 | 19055 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 19056 | |
b34976b6 | 19057 | static bfd_boolean |
17a2f251 | 19058 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
19059 | { |
19060 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
19061 | given++, canonical++; | |
19062 | ||
19063 | return ((*given == 0 && *canonical == 0) | |
19064 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
19065 | } | |
19066 | ||
19067 | ||
19068 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
19069 | CPU name. We've traditionally allowed a lot of variation here. | |
19070 | ||
19071 | Note: this function is shared between GCC and GAS. */ | |
19072 | ||
b34976b6 | 19073 | static bfd_boolean |
17a2f251 | 19074 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
19075 | { |
19076 | /* First see if the name matches exactly, or with a final "000" | |
19077 | turned into "k". */ | |
19078 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 19079 | return TRUE; |
316f5878 RS |
19080 | |
19081 | /* If not, try comparing based on numerical designation alone. | |
19082 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
19083 | if (TOLOWER (*given) == 'r') | |
19084 | given++; | |
19085 | if (!ISDIGIT (*given)) | |
b34976b6 | 19086 | return FALSE; |
316f5878 RS |
19087 | |
19088 | /* Skip over some well-known prefixes in the canonical name, | |
19089 | hoping to find a number there too. */ | |
19090 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
19091 | canonical += 2; | |
19092 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
19093 | canonical += 2; | |
19094 | else if (TOLOWER (canonical[0]) == 'r') | |
19095 | canonical += 1; | |
19096 | ||
19097 | return mips_strict_matching_cpu_name_p (canonical, given); | |
19098 | } | |
19099 | ||
19100 | ||
19101 | /* Parse an option that takes the name of a processor as its argument. | |
19102 | OPTION is the name of the option and CPU_STRING is the argument. | |
19103 | Return the corresponding processor enumeration if the CPU_STRING is | |
19104 | recognized, otherwise report an error and return null. | |
19105 | ||
19106 | A similar function exists in GCC. */ | |
e7af610e NC |
19107 | |
19108 | static const struct mips_cpu_info * | |
17a2f251 | 19109 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 19110 | { |
316f5878 | 19111 | const struct mips_cpu_info *p; |
e7af610e | 19112 | |
316f5878 RS |
19113 | /* 'from-abi' selects the most compatible architecture for the given |
19114 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
19115 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
19116 | version. Look first at the -mgp options, if given, otherwise base | |
19117 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 19118 | |
316f5878 RS |
19119 | Treat NO_ABI like the EABIs. One reason to do this is that the |
19120 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
19121 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
19122 | 'mips64', just as we did in the days before 'from-abi'. */ | |
19123 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
19124 | { | |
19125 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
19126 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
19127 | ||
19128 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
19129 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
19130 | ||
19131 | if (file_mips_gp32 >= 0) | |
19132 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
19133 | ||
19134 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
19135 | ? ISA_MIPS3 | |
19136 | : ISA_MIPS1); | |
19137 | } | |
19138 | ||
19139 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
19140 | if (strcasecmp (cpu_string, "default") == 0) | |
19141 | return 0; | |
19142 | ||
19143 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
19144 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
19145 | return p; | |
19146 | ||
20203fb9 | 19147 | as_bad (_("Bad value (%s) for %s"), cpu_string, option); |
316f5878 | 19148 | return 0; |
e7af610e NC |
19149 | } |
19150 | ||
316f5878 RS |
19151 | /* Return the canonical processor information for ISA (a member of the |
19152 | ISA_MIPS* enumeration). */ | |
19153 | ||
e7af610e | 19154 | static const struct mips_cpu_info * |
17a2f251 | 19155 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
19156 | { |
19157 | int i; | |
19158 | ||
19159 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
ad3fea08 | 19160 | if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA) |
316f5878 | 19161 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
19162 | return (&mips_cpu_info_table[i]); |
19163 | ||
e972090a | 19164 | return NULL; |
e7af610e | 19165 | } |
fef14a42 TS |
19166 | |
19167 | static const struct mips_cpu_info * | |
17a2f251 | 19168 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
19169 | { |
19170 | int i; | |
19171 | ||
19172 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
19173 | if (arch == mips_cpu_info_table[i].cpu) | |
19174 | return (&mips_cpu_info_table[i]); | |
19175 | ||
19176 | return NULL; | |
19177 | } | |
316f5878 RS |
19178 | \f |
19179 | static void | |
17a2f251 | 19180 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
19181 | { |
19182 | if (*first_p) | |
19183 | { | |
19184 | fprintf (stream, "%24s", ""); | |
19185 | *col_p = 24; | |
19186 | } | |
19187 | else | |
19188 | { | |
19189 | fprintf (stream, ", "); | |
19190 | *col_p += 2; | |
19191 | } | |
e7af610e | 19192 | |
316f5878 RS |
19193 | if (*col_p + strlen (string) > 72) |
19194 | { | |
19195 | fprintf (stream, "\n%24s", ""); | |
19196 | *col_p = 24; | |
19197 | } | |
19198 | ||
19199 | fprintf (stream, "%s", string); | |
19200 | *col_p += strlen (string); | |
19201 | ||
19202 | *first_p = 0; | |
19203 | } | |
19204 | ||
19205 | void | |
17a2f251 | 19206 | md_show_usage (FILE *stream) |
e7af610e | 19207 | { |
316f5878 RS |
19208 | int column, first; |
19209 | size_t i; | |
19210 | ||
19211 | fprintf (stream, _("\ | |
19212 | MIPS options:\n\ | |
316f5878 RS |
19213 | -EB generate big endian output\n\ |
19214 | -EL generate little endian output\n\ | |
19215 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
19216 | -G NUM allow referencing objects up to NUM bytes\n\ | |
19217 | implicitly with the gp register [default 8]\n")); | |
19218 | fprintf (stream, _("\ | |
19219 | -mips1 generate MIPS ISA I instructions\n\ | |
19220 | -mips2 generate MIPS ISA II instructions\n\ | |
19221 | -mips3 generate MIPS ISA III instructions\n\ | |
19222 | -mips4 generate MIPS ISA IV instructions\n\ | |
19223 | -mips5 generate MIPS ISA V instructions\n\ | |
19224 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 19225 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 | 19226 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 19227 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
316f5878 RS |
19228 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
19229 | ||
19230 | first = 1; | |
e7af610e NC |
19231 | |
19232 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
19233 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
19234 | show (stream, "from-abi", &column, &first); | |
19235 | fputc ('\n', stream); | |
e7af610e | 19236 | |
316f5878 RS |
19237 | fprintf (stream, _("\ |
19238 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
19239 | -no-mCPU don't generate code specific to CPU.\n\ | |
19240 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
19241 | ||
19242 | first = 1; | |
19243 | ||
19244 | show (stream, "3900", &column, &first); | |
19245 | show (stream, "4010", &column, &first); | |
19246 | show (stream, "4100", &column, &first); | |
19247 | show (stream, "4650", &column, &first); | |
19248 | fputc ('\n', stream); | |
19249 | ||
19250 | fprintf (stream, _("\ | |
19251 | -mips16 generate mips16 instructions\n\ | |
19252 | -no-mips16 do not generate mips16 instructions\n")); | |
19253 | fprintf (stream, _("\ | |
df58fc94 RS |
19254 | -mmicromips generate microMIPS instructions\n\ |
19255 | -mno-micromips do not generate microMIPS instructions\n")); | |
19256 | fprintf (stream, _("\ | |
e16bfa71 TS |
19257 | -msmartmips generate smartmips instructions\n\ |
19258 | -mno-smartmips do not generate smartmips instructions\n")); | |
19259 | fprintf (stream, _("\ | |
74cd071d CF |
19260 | -mdsp generate DSP instructions\n\ |
19261 | -mno-dsp do not generate DSP instructions\n")); | |
19262 | fprintf (stream, _("\ | |
8b082fb1 TS |
19263 | -mdspr2 generate DSP R2 instructions\n\ |
19264 | -mno-dspr2 do not generate DSP R2 instructions\n")); | |
19265 | fprintf (stream, _("\ | |
ef2e4d86 CF |
19266 | -mmt generate MT instructions\n\ |
19267 | -mno-mt do not generate MT instructions\n")); | |
19268 | fprintf (stream, _("\ | |
dec0624d MR |
19269 | -mmcu generate MCU instructions\n\ |
19270 | -mno-mcu do not generate MCU instructions\n")); | |
19271 | fprintf (stream, _("\ | |
c67a084a NC |
19272 | -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\ |
19273 | -mfix-loongson2f-nop work around Loongson2F NOP errata\n\ | |
d766e8ec | 19274 | -mfix-vr4120 work around certain VR4120 errata\n\ |
7d8e00cf | 19275 | -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ |
6a32d874 | 19276 | -mfix-24k insert a nop after ERET and DERET instructions\n\ |
d954098f | 19277 | -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\ |
316f5878 RS |
19278 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
19279 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
aed1a261 | 19280 | -msym32 assume all symbols have 32-bit values\n\ |
316f5878 RS |
19281 | -O0 remove unneeded NOPs, do not swap branches\n\ |
19282 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
19283 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ |
19284 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
037b32b9 AN |
19285 | fprintf (stream, _("\ |
19286 | -mhard-float allow floating-point instructions\n\ | |
19287 | -msoft-float do not allow floating-point instructions\n\ | |
19288 | -msingle-float only allow 32-bit floating-point operations\n\ | |
19289 | -mdouble-float allow 32-bit and 64-bit floating-point operations\n\ | |
19290 | --[no-]construct-floats [dis]allow floating point values to be constructed\n" | |
19291 | )); | |
316f5878 RS |
19292 | #ifdef OBJ_ELF |
19293 | fprintf (stream, _("\ | |
19294 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
861fb55a | 19295 | -call_nonpic generate non-PIC code that can operate with DSOs\n\ |
0c000745 | 19296 | -mvxworks-pic generate VxWorks position independent code\n\ |
861fb55a | 19297 | -non_shared do not generate code that can operate with DSOs\n\ |
316f5878 | 19298 | -xgot assume a 32 bit GOT\n\ |
dcd410fe | 19299 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
bbe506e8 | 19300 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
d821e36b | 19301 | position dependent (non shared) code\n\ |
316f5878 RS |
19302 | -mabi=ABI create ABI conformant object file for:\n")); |
19303 | ||
19304 | first = 1; | |
19305 | ||
19306 | show (stream, "32", &column, &first); | |
19307 | show (stream, "o64", &column, &first); | |
19308 | show (stream, "n32", &column, &first); | |
19309 | show (stream, "64", &column, &first); | |
19310 | show (stream, "eabi", &column, &first); | |
19311 | ||
19312 | fputc ('\n', stream); | |
19313 | ||
19314 | fprintf (stream, _("\ | |
19315 | -32 create o32 ABI object file (default)\n\ | |
19316 | -n32 create n32 ABI object file\n\ | |
19317 | -64 create 64 ABI object file\n")); | |
19318 | #endif | |
e7af610e | 19319 | } |
14e777e0 | 19320 | |
1575952e | 19321 | #ifdef TE_IRIX |
14e777e0 | 19322 | enum dwarf2_format |
413a266c | 19323 | mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED) |
14e777e0 | 19324 | { |
369943fe | 19325 | if (HAVE_64BIT_SYMBOLS) |
1575952e | 19326 | return dwarf2_format_64bit_irix; |
14e777e0 KB |
19327 | else |
19328 | return dwarf2_format_32bit; | |
19329 | } | |
1575952e | 19330 | #endif |
73369e65 EC |
19331 | |
19332 | int | |
19333 | mips_dwarf2_addr_size (void) | |
19334 | { | |
6b6b3450 | 19335 | if (HAVE_64BIT_OBJECTS) |
73369e65 | 19336 | return 8; |
73369e65 EC |
19337 | else |
19338 | return 4; | |
19339 | } | |
5862107c EC |
19340 | |
19341 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
19342 | void | |
19343 | mips_cfi_frame_initial_instructions (void) | |
19344 | { | |
19345 | cfi_add_CFA_def_cfa_register (SP); | |
19346 | } | |
19347 | ||
707bfff6 TS |
19348 | int |
19349 | tc_mips_regname_to_dw2regnum (char *regname) | |
19350 | { | |
19351 | unsigned int regnum = -1; | |
19352 | unsigned int reg; | |
19353 | ||
19354 | if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®)) | |
19355 | regnum = reg; | |
19356 | ||
19357 | return regnum; | |
19358 | } |