Commit | Line | Data |
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252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
81912461 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
ec2655a6 | 3 | 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc. |
252b5132 RH |
4 | Contributed by the OSF and Ralph Campbell. |
5 | Written by Keith Knowles and Ralph Campbell, working independently. | |
6 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
7 | Support. | |
8 | ||
9 | This file is part of GAS. | |
10 | ||
11 | GAS is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 13 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
14 | any later version. |
15 | ||
16 | GAS is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
23 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
24 | 02110-1301, USA. */ | |
252b5132 RH |
25 | |
26 | #include "as.h" | |
27 | #include "config.h" | |
28 | #include "subsegs.h" | |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | |
252b5132 RH |
31 | #include "opcode/mips.h" |
32 | #include "itbl-ops.h" | |
c5dd6aab | 33 | #include "dwarf2dbg.h" |
5862107c | 34 | #include "dw2gencfi.h" |
252b5132 RH |
35 | |
36 | #ifdef DEBUG | |
37 | #define DBG(x) printf x | |
38 | #else | |
39 | #define DBG(x) | |
40 | #endif | |
41 | ||
42 | #ifdef OBJ_MAYBE_ELF | |
43 | /* Clean up namespace so we can include obj-elf.h too. */ | |
17a2f251 TS |
44 | static int mips_output_flavor (void); |
45 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
46 | #undef OBJ_PROCESS_STAB |
47 | #undef OUTPUT_FLAVOR | |
48 | #undef S_GET_ALIGN | |
49 | #undef S_GET_SIZE | |
50 | #undef S_SET_ALIGN | |
51 | #undef S_SET_SIZE | |
252b5132 RH |
52 | #undef obj_frob_file |
53 | #undef obj_frob_file_after_relocs | |
54 | #undef obj_frob_symbol | |
55 | #undef obj_pop_insert | |
56 | #undef obj_sec_sym_ok_for_reloc | |
57 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
58 | ||
59 | #include "obj-elf.h" | |
60 | /* Fix any of them that we actually care about. */ | |
61 | #undef OUTPUT_FLAVOR | |
62 | #define OUTPUT_FLAVOR mips_output_flavor() | |
63 | #endif | |
64 | ||
65 | #if defined (OBJ_ELF) | |
66 | #include "elf/mips.h" | |
67 | #endif | |
68 | ||
69 | #ifndef ECOFF_DEBUGGING | |
70 | #define NO_ECOFF_DEBUGGING | |
71 | #define ECOFF_DEBUGGING 0 | |
72 | #endif | |
73 | ||
ecb4347a DJ |
74 | int mips_flag_mdebug = -1; |
75 | ||
dcd410fe RO |
76 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
77 | linker doesn't know about and discards them, but relocations against them | |
78 | remain, leading to rld crashes. */ | |
79 | #ifdef TE_IRIX | |
80 | int mips_flag_pdr = FALSE; | |
81 | #else | |
82 | int mips_flag_pdr = TRUE; | |
83 | #endif | |
84 | ||
252b5132 RH |
85 | #include "ecoff.h" |
86 | ||
87 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
88 | static char *mips_regmask_frag; | |
89 | #endif | |
90 | ||
85b51719 | 91 | #define ZERO 0 |
252b5132 RH |
92 | #define AT 1 |
93 | #define TREG 24 | |
94 | #define PIC_CALL_REG 25 | |
95 | #define KT0 26 | |
96 | #define KT1 27 | |
97 | #define GP 28 | |
98 | #define SP 29 | |
99 | #define FP 30 | |
100 | #define RA 31 | |
101 | ||
102 | #define ILLEGAL_REG (32) | |
103 | ||
104 | /* Allow override of standard little-endian ECOFF format. */ | |
105 | ||
106 | #ifndef ECOFF_LITTLE_FORMAT | |
107 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
108 | #endif | |
109 | ||
110 | extern int target_big_endian; | |
111 | ||
252b5132 | 112 | /* The name of the readonly data section. */ |
4d0d148d | 113 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ |
252b5132 | 114 | ? ".rdata" \ |
056350c6 NC |
115 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
116 | ? ".rdata" \ | |
252b5132 RH |
117 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
118 | ? ".rodata" \ | |
119 | : (abort (), "")) | |
120 | ||
47e39b9d RS |
121 | /* Information about an instruction, including its format, operands |
122 | and fixups. */ | |
123 | struct mips_cl_insn | |
124 | { | |
125 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ | |
126 | const struct mips_opcode *insn_mo; | |
127 | ||
128 | /* True if this is a mips16 instruction and if we want the extended | |
129 | form of INSN_MO. */ | |
130 | bfd_boolean use_extend; | |
131 | ||
132 | /* The 16-bit extension instruction to use when USE_EXTEND is true. */ | |
133 | unsigned short extend; | |
134 | ||
135 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is | |
136 | a copy of INSN_MO->match with the operands filled in. */ | |
137 | unsigned long insn_opcode; | |
138 | ||
139 | /* The frag that contains the instruction. */ | |
140 | struct frag *frag; | |
141 | ||
142 | /* The offset into FRAG of the first instruction byte. */ | |
143 | long where; | |
144 | ||
145 | /* The relocs associated with the instruction, if any. */ | |
146 | fixS *fixp[3]; | |
147 | ||
a38419a5 RS |
148 | /* True if this entry cannot be moved from its current position. */ |
149 | unsigned int fixed_p : 1; | |
47e39b9d | 150 | |
708587a4 | 151 | /* True if this instruction occurred in a .set noreorder block. */ |
47e39b9d RS |
152 | unsigned int noreorder_p : 1; |
153 | ||
2fa15973 RS |
154 | /* True for mips16 instructions that jump to an absolute address. */ |
155 | unsigned int mips16_absolute_jump_p : 1; | |
47e39b9d RS |
156 | }; |
157 | ||
a325df1d TS |
158 | /* The ABI to use. */ |
159 | enum mips_abi_level | |
160 | { | |
161 | NO_ABI = 0, | |
162 | O32_ABI, | |
163 | O64_ABI, | |
164 | N32_ABI, | |
165 | N64_ABI, | |
166 | EABI_ABI | |
167 | }; | |
168 | ||
169 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 170 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 171 | |
143d77c5 EC |
172 | /* Whether or not we have code that can call pic code. */ |
173 | int mips_abicalls = FALSE; | |
174 | ||
aa6975fb ILT |
175 | /* Whether or not we have code which can be put into a shared |
176 | library. */ | |
177 | static bfd_boolean mips_in_shared = TRUE; | |
178 | ||
252b5132 RH |
179 | /* This is the set of options which may be modified by the .set |
180 | pseudo-op. We use a struct so that .set push and .set pop are more | |
181 | reliable. */ | |
182 | ||
e972090a NC |
183 | struct mips_set_options |
184 | { | |
252b5132 RH |
185 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
186 | if it has not been initialized. Changed by `.set mipsN', and the | |
187 | -mipsN command line option, and the default CPU. */ | |
188 | int isa; | |
1f25f5d3 CD |
189 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
190 | if they have not been initialized. Changed by `.set <asename>', by | |
191 | command line options, and based on the default architecture. */ | |
192 | int ase_mips3d; | |
deec1734 | 193 | int ase_mdmx; |
e16bfa71 | 194 | int ase_smartmips; |
74cd071d | 195 | int ase_dsp; |
8b082fb1 | 196 | int ase_dspr2; |
ef2e4d86 | 197 | int ase_mt; |
252b5132 RH |
198 | /* Whether we are assembling for the mips16 processor. 0 if we are |
199 | not, 1 if we are, and -1 if the value has not been initialized. | |
200 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
201 | -nomips16 command line options, and the default CPU. */ | |
202 | int mips16; | |
203 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
204 | reorder' and `.set noreorder'. */ | |
205 | int noreorder; | |
206 | /* Non-zero if we should not permit the $at ($1) register to be used | |
207 | in instructions. Changed by `.set at' and `.set noat'. */ | |
208 | int noat; | |
209 | /* Non-zero if we should warn when a macro instruction expands into | |
210 | more than one machine instruction. Changed by `.set nomacro' and | |
211 | `.set macro'. */ | |
212 | int warn_about_macros; | |
213 | /* Non-zero if we should not move instructions. Changed by `.set | |
214 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
215 | int nomove; | |
216 | /* Non-zero if we should not optimize branches by moving the target | |
217 | of the branch into the delay slot. Actually, we don't perform | |
218 | this optimization anyhow. Changed by `.set bopt' and `.set | |
219 | nobopt'. */ | |
220 | int nobopt; | |
221 | /* Non-zero if we should not autoextend mips16 instructions. | |
222 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
223 | int noautoextend; | |
a325df1d TS |
224 | /* Restrict general purpose registers and floating point registers |
225 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
226 | is passed but can changed if the assembler code uses .set mipsN. */ | |
227 | int gp32; | |
228 | int fp32; | |
fef14a42 TS |
229 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
230 | command line option, and the default CPU. */ | |
231 | int arch; | |
aed1a261 RS |
232 | /* True if ".set sym32" is in effect. */ |
233 | bfd_boolean sym32; | |
252b5132 RH |
234 | }; |
235 | ||
a325df1d | 236 | /* True if -mgp32 was passed. */ |
a8e8e863 | 237 | static int file_mips_gp32 = -1; |
a325df1d TS |
238 | |
239 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 240 | static int file_mips_fp32 = -1; |
a325df1d | 241 | |
252b5132 | 242 | /* This is the struct we use to hold the current set of options. Note |
a4672219 | 243 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to |
e7af610e | 244 | -1 to indicate that they have not been initialized. */ |
252b5132 | 245 | |
e972090a NC |
246 | static struct mips_set_options mips_opts = |
247 | { | |
8b082fb1 | 248 | ISA_UNKNOWN, -1, -1, 0, -1, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN, FALSE |
e7af610e | 249 | }; |
252b5132 RH |
250 | |
251 | /* These variables are filled in with the masks of registers used. | |
252 | The object format code reads them and puts them in the appropriate | |
253 | place. */ | |
254 | unsigned long mips_gprmask; | |
255 | unsigned long mips_cprmask[4]; | |
256 | ||
257 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 258 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 259 | |
a4672219 TS |
260 | /* True if -mips16 was passed or implied by arguments passed on the |
261 | command line (e.g., by -march). */ | |
262 | static int file_ase_mips16; | |
263 | ||
3994f87e TS |
264 | #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \ |
265 | || mips_opts.isa == ISA_MIPS32R2 \ | |
266 | || mips_opts.isa == ISA_MIPS64 \ | |
267 | || mips_opts.isa == ISA_MIPS64R2) | |
268 | ||
1f25f5d3 CD |
269 | /* True if -mips3d was passed or implied by arguments passed on the |
270 | command line (e.g., by -march). */ | |
271 | static int file_ase_mips3d; | |
272 | ||
deec1734 CD |
273 | /* True if -mdmx was passed or implied by arguments passed on the |
274 | command line (e.g., by -march). */ | |
275 | static int file_ase_mdmx; | |
276 | ||
e16bfa71 TS |
277 | /* True if -msmartmips was passed or implied by arguments passed on the |
278 | command line (e.g., by -march). */ | |
279 | static int file_ase_smartmips; | |
280 | ||
ad3fea08 TS |
281 | #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \ |
282 | || mips_opts.isa == ISA_MIPS32R2) | |
e16bfa71 | 283 | |
74cd071d CF |
284 | /* True if -mdsp was passed or implied by arguments passed on the |
285 | command line (e.g., by -march). */ | |
286 | static int file_ase_dsp; | |
287 | ||
ad3fea08 TS |
288 | #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
289 | || mips_opts.isa == ISA_MIPS64R2) | |
290 | ||
65263ce3 TS |
291 | #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2) |
292 | ||
8b082fb1 TS |
293 | /* True if -mdspr2 was passed or implied by arguments passed on the |
294 | command line (e.g., by -march). */ | |
295 | static int file_ase_dspr2; | |
296 | ||
297 | #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \ | |
298 | || mips_opts.isa == ISA_MIPS64R2) | |
299 | ||
ef2e4d86 CF |
300 | /* True if -mmt was passed or implied by arguments passed on the |
301 | command line (e.g., by -march). */ | |
302 | static int file_ase_mt; | |
303 | ||
ad3fea08 TS |
304 | #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
305 | || mips_opts.isa == ISA_MIPS64R2) | |
306 | ||
ec68c924 | 307 | /* The argument of the -march= flag. The architecture we are assembling. */ |
fef14a42 | 308 | static int file_mips_arch = CPU_UNKNOWN; |
316f5878 | 309 | static const char *mips_arch_string; |
ec68c924 EC |
310 | |
311 | /* The argument of the -mtune= flag. The architecture for which we | |
312 | are optimizing. */ | |
313 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 314 | static const char *mips_tune_string; |
ec68c924 | 315 | |
316f5878 | 316 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
317 | static int mips_32bitmode = 0; |
318 | ||
316f5878 RS |
319 | /* True if the given ABI requires 32-bit registers. */ |
320 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
321 | ||
322 | /* Likewise 64-bit registers. */ | |
707bfff6 TS |
323 | #define ABI_NEEDS_64BIT_REGS(ABI) \ |
324 | ((ABI) == N32_ABI \ | |
325 | || (ABI) == N64_ABI \ | |
316f5878 RS |
326 | || (ABI) == O64_ABI) |
327 | ||
ad3fea08 | 328 | /* Return true if ISA supports 64 bit wide gp registers. */ |
707bfff6 TS |
329 | #define ISA_HAS_64BIT_REGS(ISA) \ |
330 | ((ISA) == ISA_MIPS3 \ | |
331 | || (ISA) == ISA_MIPS4 \ | |
332 | || (ISA) == ISA_MIPS5 \ | |
333 | || (ISA) == ISA_MIPS64 \ | |
334 | || (ISA) == ISA_MIPS64R2) | |
9ce8a5dd | 335 | |
ad3fea08 TS |
336 | /* Return true if ISA supports 64 bit wide float registers. */ |
337 | #define ISA_HAS_64BIT_FPRS(ISA) \ | |
338 | ((ISA) == ISA_MIPS3 \ | |
339 | || (ISA) == ISA_MIPS4 \ | |
340 | || (ISA) == ISA_MIPS5 \ | |
341 | || (ISA) == ISA_MIPS32R2 \ | |
342 | || (ISA) == ISA_MIPS64 \ | |
343 | || (ISA) == ISA_MIPS64R2) | |
344 | ||
af7ee8bf CD |
345 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
346 | instructions. */ | |
707bfff6 TS |
347 | #define ISA_HAS_DROR(ISA) \ |
348 | ((ISA) == ISA_MIPS64R2) | |
af7ee8bf CD |
349 | |
350 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
351 | instructions. */ | |
707bfff6 TS |
352 | #define ISA_HAS_ROR(ISA) \ |
353 | ((ISA) == ISA_MIPS32R2 \ | |
354 | || (ISA) == ISA_MIPS64R2 \ | |
355 | || mips_opts.ase_smartmips) | |
356 | ||
7455baf8 TS |
357 | /* Return true if ISA supports single-precision floats in odd registers. */ |
358 | #define ISA_HAS_ODD_SINGLE_FPR(ISA) \ | |
359 | ((ISA) == ISA_MIPS32 \ | |
360 | || (ISA) == ISA_MIPS32R2 \ | |
361 | || (ISA) == ISA_MIPS64 \ | |
362 | || (ISA) == ISA_MIPS64R2) | |
af7ee8bf | 363 | |
ad3fea08 TS |
364 | /* Return true if ISA supports move to/from high part of a 64-bit |
365 | floating-point register. */ | |
366 | #define ISA_HAS_MXHC1(ISA) \ | |
367 | ((ISA) == ISA_MIPS32R2 \ | |
368 | || (ISA) == ISA_MIPS64R2) | |
369 | ||
e013f690 | 370 | #define HAVE_32BIT_GPRS \ |
ad3fea08 | 371 | (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 372 | |
e013f690 | 373 | #define HAVE_32BIT_FPRS \ |
ad3fea08 | 374 | (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa)) |
ca4e0257 | 375 | |
ad3fea08 TS |
376 | #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS) |
377 | #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS) | |
ca4e0257 | 378 | |
316f5878 | 379 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 380 | |
316f5878 | 381 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 382 | |
3b91255e RS |
383 | /* True if relocations are stored in-place. */ |
384 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
385 | ||
aed1a261 RS |
386 | /* The ABI-derived address size. */ |
387 | #define HAVE_64BIT_ADDRESSES \ | |
388 | (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) | |
389 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) | |
e013f690 | 390 | |
aed1a261 RS |
391 | /* The size of symbolic constants (i.e., expressions of the form |
392 | "SYMBOL" or "SYMBOL + OFFSET"). */ | |
393 | #define HAVE_32BIT_SYMBOLS \ | |
394 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) | |
395 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) | |
ca4e0257 | 396 | |
b7c7d6c1 TS |
397 | /* Addresses are loaded in different ways, depending on the address size |
398 | in use. The n32 ABI Documentation also mandates the use of additions | |
399 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 400 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 401 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
402 | |
403 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 404 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
405 | |
406 | #define ADDRESS_LOAD_INSN \ | |
407 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
408 | ||
409 | #define ADDRESS_STORE_INSN \ | |
410 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
411 | ||
a4672219 | 412 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
413 | #define CPU_HAS_MIPS16(cpu) \ |
414 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
415 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 416 | |
60b63b72 RS |
417 | /* True if CPU has a dror instruction. */ |
418 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
419 | ||
420 | /* True if CPU has a ror instruction. */ | |
421 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
422 | ||
c8978940 CD |
423 | /* True if mflo and mfhi can be immediately followed by instructions |
424 | which write to the HI and LO registers. | |
425 | ||
426 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
427 | (at least) two instructions between the reads of HI/LO and | |
428 | instructions which write them, and later ISAs do not. Contradicting | |
429 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
430 | the UM for the NEC Vr5000) document needing the instructions between | |
431 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
432 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
433 | earlier-ISA CPUs for which CPU documentation declares that the | |
434 | instructions are really interlocked. */ | |
435 | #define hilo_interlocks \ | |
436 | (mips_opts.isa == ISA_MIPS32 \ | |
437 | || mips_opts.isa == ISA_MIPS32R2 \ | |
438 | || mips_opts.isa == ISA_MIPS64 \ | |
439 | || mips_opts.isa == ISA_MIPS64R2 \ | |
440 | || mips_opts.arch == CPU_R4010 \ | |
441 | || mips_opts.arch == CPU_R10000 \ | |
442 | || mips_opts.arch == CPU_R12000 \ | |
443 | || mips_opts.arch == CPU_RM7000 \ | |
c8978940 CD |
444 | || mips_opts.arch == CPU_VR5500 \ |
445 | ) | |
252b5132 RH |
446 | |
447 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
448 | from the GPRs after they are loaded from memory, and thus does not |
449 | require nops to be inserted. This applies to instructions marked | |
450 | INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA | |
451 | level I. */ | |
252b5132 | 452 | #define gpr_interlocks \ |
e7af610e | 453 | (mips_opts.isa != ISA_MIPS1 \ |
fef14a42 | 454 | || mips_opts.arch == CPU_R3900) |
252b5132 | 455 | |
81912461 ILT |
456 | /* Whether the processor uses hardware interlocks to avoid delays |
457 | required by coprocessor instructions, and thus does not require | |
458 | nops to be inserted. This applies to instructions marked | |
459 | INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays | |
460 | between instructions marked INSN_WRITE_COND_CODE and ones marked | |
461 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA | |
462 | levels I, II, and III. */ | |
bdaaa2e1 | 463 | /* Itbl support may require additional care here. */ |
81912461 ILT |
464 | #define cop_interlocks \ |
465 | ((mips_opts.isa != ISA_MIPS1 \ | |
466 | && mips_opts.isa != ISA_MIPS2 \ | |
467 | && mips_opts.isa != ISA_MIPS3) \ | |
468 | || mips_opts.arch == CPU_R4300 \ | |
81912461 ILT |
469 | ) |
470 | ||
471 | /* Whether the processor uses hardware interlocks to protect reads | |
472 | from coprocessor registers after they are loaded from memory, and | |
473 | thus does not require nops to be inserted. This applies to | |
474 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
475 | requires at MIPS ISA level I. */ | |
476 | #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1) | |
252b5132 | 477 | |
6b76fefe CM |
478 | /* Is this a mfhi or mflo instruction? */ |
479 | #define MF_HILO_INSN(PINFO) \ | |
480 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) | |
481 | ||
252b5132 RH |
482 | /* MIPS PIC level. */ |
483 | ||
a161fe53 | 484 | enum mips_pic_level mips_pic; |
252b5132 | 485 | |
c9914766 | 486 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 487 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 488 | static int mips_big_got = 0; |
252b5132 RH |
489 | |
490 | /* 1 if trap instructions should used for overflow rather than break | |
491 | instructions. */ | |
c9914766 | 492 | static int mips_trap = 0; |
252b5132 | 493 | |
119d663a | 494 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 495 | by assembling two single width halves into two single width floating |
119d663a NC |
496 | point registers which just happen to alias the double width destination |
497 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 498 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
499 | automatically at assemble time. */ |
500 | static int mips_disable_float_construction; | |
501 | ||
252b5132 RH |
502 | /* Non-zero if any .set noreorder directives were used. */ |
503 | ||
504 | static int mips_any_noreorder; | |
505 | ||
6b76fefe CM |
506 | /* Non-zero if nops should be inserted when the register referenced in |
507 | an mfhi/mflo instruction is read in the next two instructions. */ | |
508 | static int mips_7000_hilo_fix; | |
509 | ||
02ffd3e4 | 510 | /* The size of objects in the small data section. */ |
156c2f8b | 511 | static unsigned int g_switch_value = 8; |
252b5132 RH |
512 | /* Whether the -G option was used. */ |
513 | static int g_switch_seen = 0; | |
514 | ||
515 | #define N_RMASK 0xc4 | |
516 | #define N_VFP 0xd4 | |
517 | ||
518 | /* If we can determine in advance that GP optimization won't be | |
519 | possible, we can skip the relaxation stuff that tries to produce | |
520 | GP-relative references. This makes delay slot optimization work | |
521 | better. | |
522 | ||
523 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
524 | gcc output. It needs to guess right for gcc, otherwise gcc |
525 | will put what it thinks is a GP-relative instruction in a branch | |
526 | delay slot. | |
252b5132 RH |
527 | |
528 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
529 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 530 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
531 | |
532 | /* handle of the OPCODE hash table */ | |
533 | static struct hash_control *op_hash = NULL; | |
534 | ||
535 | /* The opcode hash table we use for the mips16. */ | |
536 | static struct hash_control *mips16_op_hash = NULL; | |
537 | ||
538 | /* This array holds the chars that always start a comment. If the | |
539 | pre-processor is disabled, these aren't very useful */ | |
540 | const char comment_chars[] = "#"; | |
541 | ||
542 | /* This array holds the chars that only start a comment at the beginning of | |
543 | a line. If the line seems to have the form '# 123 filename' | |
544 | .line and .file directives will appear in the pre-processed output */ | |
545 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
546 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 547 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
548 | /* Also note that C style comments are always supported. */ |
549 | const char line_comment_chars[] = "#"; | |
550 | ||
bdaaa2e1 | 551 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 552 | const char line_separator_chars[] = ";"; |
252b5132 RH |
553 | |
554 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
555 | const char EXP_CHARS[] = "eE"; | |
556 | ||
557 | /* Chars that mean this number is a floating point constant */ | |
558 | /* As in 0f12.456 */ | |
559 | /* or 0d1.2345e12 */ | |
560 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
561 | ||
562 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
563 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
564 | but nothing is ideal around here. | |
565 | */ | |
566 | ||
567 | static char *insn_error; | |
568 | ||
569 | static int auto_align = 1; | |
570 | ||
571 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
572 | offset in the stack frame from which to restore the $gp register. | |
573 | This is set by the .cprestore pseudo-op, and saved in this | |
574 | variable. */ | |
575 | static offsetT mips_cprestore_offset = -1; | |
576 | ||
67c1ffbe | 577 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 578 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 579 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
580 | static offsetT mips_cpreturn_offset = -1; |
581 | static int mips_cpreturn_register = -1; | |
582 | static int mips_gp_register = GP; | |
def2e0dd | 583 | static int mips_gprel_offset = 0; |
6478892d | 584 | |
7a621144 DJ |
585 | /* Whether mips_cprestore_offset has been set in the current function |
586 | (or whether it has already been warned about, if not). */ | |
587 | static int mips_cprestore_valid = 0; | |
588 | ||
252b5132 RH |
589 | /* This is the register which holds the stack frame, as set by the |
590 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
591 | static int mips_frame_reg = SP; | |
592 | ||
7a621144 DJ |
593 | /* Whether mips_frame_reg has been set in the current function |
594 | (or whether it has already been warned about, if not). */ | |
595 | static int mips_frame_reg_valid = 0; | |
596 | ||
252b5132 RH |
597 | /* To output NOP instructions correctly, we need to keep information |
598 | about the previous two instructions. */ | |
599 | ||
600 | /* Whether we are optimizing. The default value of 2 means to remove | |
601 | unneeded NOPs and swap branch instructions when possible. A value | |
602 | of 1 means to not swap branches. A value of 0 means to always | |
603 | insert NOPs. */ | |
604 | static int mips_optimize = 2; | |
605 | ||
606 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
607 | equivalent to seeing no -g option at all. */ | |
608 | static int mips_debug = 0; | |
609 | ||
7d8e00cf RS |
610 | /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ |
611 | #define MAX_VR4130_NOPS 4 | |
612 | ||
613 | /* The maximum number of NOPs needed to fill delay slots. */ | |
614 | #define MAX_DELAY_NOPS 2 | |
615 | ||
616 | /* The maximum number of NOPs needed for any purpose. */ | |
617 | #define MAX_NOPS 4 | |
71400594 RS |
618 | |
619 | /* A list of previous instructions, with index 0 being the most recent. | |
620 | We need to look back MAX_NOPS instructions when filling delay slots | |
621 | or working around processor errata. We need to look back one | |
622 | instruction further if we're thinking about using history[0] to | |
623 | fill a branch delay slot. */ | |
624 | static struct mips_cl_insn history[1 + MAX_NOPS]; | |
252b5132 | 625 | |
1e915849 RS |
626 | /* Nop instructions used by emit_nop. */ |
627 | static struct mips_cl_insn nop_insn, mips16_nop_insn; | |
628 | ||
629 | /* The appropriate nop for the current mode. */ | |
630 | #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn) | |
252b5132 | 631 | |
252b5132 RH |
632 | /* If this is set, it points to a frag holding nop instructions which |
633 | were inserted before the start of a noreorder section. If those | |
634 | nops turn out to be unnecessary, the size of the frag can be | |
635 | decreased. */ | |
636 | static fragS *prev_nop_frag; | |
637 | ||
638 | /* The number of nop instructions we created in prev_nop_frag. */ | |
639 | static int prev_nop_frag_holds; | |
640 | ||
641 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 642 | prev_nop_frag. */ |
252b5132 RH |
643 | static int prev_nop_frag_required; |
644 | ||
645 | /* The number of instructions we've seen since prev_nop_frag. */ | |
646 | static int prev_nop_frag_since; | |
647 | ||
648 | /* For ECOFF and ELF, relocations against symbols are done in two | |
649 | parts, with a HI relocation and a LO relocation. Each relocation | |
650 | has only 16 bits of space to store an addend. This means that in | |
651 | order for the linker to handle carries correctly, it must be able | |
652 | to locate both the HI and the LO relocation. This means that the | |
653 | relocations must appear in order in the relocation table. | |
654 | ||
655 | In order to implement this, we keep track of each unmatched HI | |
656 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 657 | corresponding LO relocation. */ |
252b5132 | 658 | |
e972090a NC |
659 | struct mips_hi_fixup |
660 | { | |
252b5132 RH |
661 | /* Next HI fixup. */ |
662 | struct mips_hi_fixup *next; | |
663 | /* This fixup. */ | |
664 | fixS *fixp; | |
665 | /* The section this fixup is in. */ | |
666 | segT seg; | |
667 | }; | |
668 | ||
669 | /* The list of unmatched HI relocs. */ | |
670 | ||
671 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
672 | ||
64bdfcaf RS |
673 | /* The frag containing the last explicit relocation operator. |
674 | Null if explicit relocations have not been used. */ | |
675 | ||
676 | static fragS *prev_reloc_op_frag; | |
677 | ||
252b5132 RH |
678 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
679 | ||
680 | #define X ILLEGAL_REG | |
e972090a NC |
681 | static const int mips32_to_16_reg_map[] = |
682 | { | |
252b5132 RH |
683 | X, X, 2, 3, 4, 5, 6, 7, |
684 | X, X, X, X, X, X, X, X, | |
685 | 0, 1, X, X, X, X, X, X, | |
686 | X, X, X, X, X, X, X, X | |
687 | }; | |
688 | #undef X | |
689 | ||
690 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
691 | ||
e972090a NC |
692 | static const unsigned int mips16_to_32_reg_map[] = |
693 | { | |
252b5132 RH |
694 | 16, 17, 2, 3, 4, 5, 6, 7 |
695 | }; | |
60b63b72 | 696 | |
71400594 RS |
697 | /* Classifies the kind of instructions we're interested in when |
698 | implementing -mfix-vr4120. */ | |
699 | enum fix_vr4120_class { | |
700 | FIX_VR4120_MACC, | |
701 | FIX_VR4120_DMACC, | |
702 | FIX_VR4120_MULT, | |
703 | FIX_VR4120_DMULT, | |
704 | FIX_VR4120_DIV, | |
705 | FIX_VR4120_MTHILO, | |
706 | NUM_FIX_VR4120_CLASSES | |
707 | }; | |
708 | ||
709 | /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if | |
710 | there must be at least one other instruction between an instruction | |
711 | of type X and an instruction of type Y. */ | |
712 | static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; | |
713 | ||
714 | /* True if -mfix-vr4120 is in force. */ | |
d766e8ec | 715 | static int mips_fix_vr4120; |
4a6a3df4 | 716 | |
7d8e00cf RS |
717 | /* ...likewise -mfix-vr4130. */ |
718 | static int mips_fix_vr4130; | |
719 | ||
4a6a3df4 AO |
720 | /* We don't relax branches by default, since this causes us to expand |
721 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
722 | fail to compute the offset before expanding the macro to the most | |
723 | efficient expansion. */ | |
724 | ||
725 | static int mips_relax_branch; | |
252b5132 | 726 | \f |
4d7206a2 RS |
727 | /* The expansion of many macros depends on the type of symbol that |
728 | they refer to. For example, when generating position-dependent code, | |
729 | a macro that refers to a symbol may have two different expansions, | |
730 | one which uses GP-relative addresses and one which uses absolute | |
731 | addresses. When generating SVR4-style PIC, a macro may have | |
732 | different expansions for local and global symbols. | |
733 | ||
734 | We handle these situations by generating both sequences and putting | |
735 | them in variant frags. In position-dependent code, the first sequence | |
736 | will be the GP-relative one and the second sequence will be the | |
737 | absolute one. In SVR4 PIC, the first sequence will be for global | |
738 | symbols and the second will be for local symbols. | |
739 | ||
584892a6 RS |
740 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
741 | SECOND are the lengths of the two sequences in bytes. These fields | |
742 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
743 | the subtype has the following flags: | |
4d7206a2 | 744 | |
584892a6 RS |
745 | RELAX_USE_SECOND |
746 | Set if it has been decided that we should use the second | |
747 | sequence instead of the first. | |
748 | ||
749 | RELAX_SECOND_LONGER | |
750 | Set in the first variant frag if the macro's second implementation | |
751 | is longer than its first. This refers to the macro as a whole, | |
752 | not an individual relaxation. | |
753 | ||
754 | RELAX_NOMACRO | |
755 | Set in the first variant frag if the macro appeared in a .set nomacro | |
756 | block and if one alternative requires a warning but the other does not. | |
757 | ||
758 | RELAX_DELAY_SLOT | |
759 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
760 | delay slot. | |
4d7206a2 RS |
761 | |
762 | The frag's "opcode" points to the first fixup for relaxable code. | |
763 | ||
764 | Relaxable macros are generated using a sequence such as: | |
765 | ||
766 | relax_start (SYMBOL); | |
767 | ... generate first expansion ... | |
768 | relax_switch (); | |
769 | ... generate second expansion ... | |
770 | relax_end (); | |
771 | ||
772 | The code and fixups for the unwanted alternative are discarded | |
773 | by md_convert_frag. */ | |
584892a6 | 774 | #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) |
4d7206a2 | 775 | |
584892a6 RS |
776 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
777 | #define RELAX_SECOND(X) ((X) & 0xff) | |
778 | #define RELAX_USE_SECOND 0x10000 | |
779 | #define RELAX_SECOND_LONGER 0x20000 | |
780 | #define RELAX_NOMACRO 0x40000 | |
781 | #define RELAX_DELAY_SLOT 0x80000 | |
252b5132 | 782 | |
4a6a3df4 AO |
783 | /* Branch without likely bit. If label is out of range, we turn: |
784 | ||
785 | beq reg1, reg2, label | |
786 | delay slot | |
787 | ||
788 | into | |
789 | ||
790 | bne reg1, reg2, 0f | |
791 | nop | |
792 | j label | |
793 | 0: delay slot | |
794 | ||
795 | with the following opcode replacements: | |
796 | ||
797 | beq <-> bne | |
798 | blez <-> bgtz | |
799 | bltz <-> bgez | |
800 | bc1f <-> bc1t | |
801 | ||
802 | bltzal <-> bgezal (with jal label instead of j label) | |
803 | ||
804 | Even though keeping the delay slot instruction in the delay slot of | |
805 | the branch would be more efficient, it would be very tricky to do | |
806 | correctly, because we'd have to introduce a variable frag *after* | |
807 | the delay slot instruction, and expand that instead. Let's do it | |
808 | the easy way for now, even if the branch-not-taken case now costs | |
809 | one additional instruction. Out-of-range branches are not supposed | |
810 | to be common, anyway. | |
811 | ||
812 | Branch likely. If label is out of range, we turn: | |
813 | ||
814 | beql reg1, reg2, label | |
815 | delay slot (annulled if branch not taken) | |
816 | ||
817 | into | |
818 | ||
819 | beql reg1, reg2, 1f | |
820 | nop | |
821 | beql $0, $0, 2f | |
822 | nop | |
823 | 1: j[al] label | |
824 | delay slot (executed only if branch taken) | |
825 | 2: | |
826 | ||
827 | It would be possible to generate a shorter sequence by losing the | |
828 | likely bit, generating something like: | |
b34976b6 | 829 | |
4a6a3df4 AO |
830 | bne reg1, reg2, 0f |
831 | nop | |
832 | j[al] label | |
833 | delay slot (executed only if branch taken) | |
834 | 0: | |
835 | ||
836 | beql -> bne | |
837 | bnel -> beq | |
838 | blezl -> bgtz | |
839 | bgtzl -> blez | |
840 | bltzl -> bgez | |
841 | bgezl -> bltz | |
842 | bc1fl -> bc1t | |
843 | bc1tl -> bc1f | |
844 | ||
845 | bltzall -> bgezal (with jal label instead of j label) | |
846 | bgezall -> bltzal (ditto) | |
847 | ||
848 | ||
849 | but it's not clear that it would actually improve performance. */ | |
af6ae2ad | 850 | #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \ |
4a6a3df4 AO |
851 | ((relax_substateT) \ |
852 | (0xc0000000 \ | |
853 | | ((toofar) ? 1 : 0) \ | |
854 | | ((link) ? 2 : 0) \ | |
855 | | ((likely) ? 4 : 0) \ | |
af6ae2ad | 856 | | ((uncond) ? 8 : 0))) |
4a6a3df4 | 857 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
4a6a3df4 AO |
858 | #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0) |
859 | #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0) | |
860 | #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0) | |
ae6063d4 | 861 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0) |
4a6a3df4 | 862 | |
252b5132 RH |
863 | /* For mips16 code, we use an entirely different form of relaxation. |
864 | mips16 supports two versions of most instructions which take | |
865 | immediate values: a small one which takes some small value, and a | |
866 | larger one which takes a 16 bit value. Since branches also follow | |
867 | this pattern, relaxing these values is required. | |
868 | ||
869 | We can assemble both mips16 and normal MIPS code in a single | |
870 | object. Therefore, we need to support this type of relaxation at | |
871 | the same time that we support the relaxation described above. We | |
872 | use the high bit of the subtype field to distinguish these cases. | |
873 | ||
874 | The information we store for this type of relaxation is the | |
875 | argument code found in the opcode file for this relocation, whether | |
876 | the user explicitly requested a small or extended form, and whether | |
877 | the relocation is in a jump or jal delay slot. That tells us the | |
878 | size of the value, and how it should be stored. We also store | |
879 | whether the fragment is considered to be extended or not. We also | |
880 | store whether this is known to be a branch to a different section, | |
881 | whether we have tried to relax this frag yet, and whether we have | |
882 | ever extended a PC relative fragment because of a shift count. */ | |
883 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
884 | (0x80000000 \ | |
885 | | ((type) & 0xff) \ | |
886 | | ((small) ? 0x100 : 0) \ | |
887 | | ((ext) ? 0x200 : 0) \ | |
888 | | ((dslot) ? 0x400 : 0) \ | |
889 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 890 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
891 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
892 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
893 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
894 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
895 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
896 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
897 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
898 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
899 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
900 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
901 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 CD |
902 | |
903 | /* Is the given value a sign-extended 32-bit value? */ | |
904 | #define IS_SEXT_32BIT_NUM(x) \ | |
905 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
906 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
907 | ||
908 | /* Is the given value a sign-extended 16-bit value? */ | |
909 | #define IS_SEXT_16BIT_NUM(x) \ | |
910 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
911 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
912 | ||
2051e8c4 MR |
913 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ |
914 | #define IS_ZEXT_32BIT_NUM(x) \ | |
915 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
916 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
917 | ||
bf12938e RS |
918 | /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in |
919 | VALUE << SHIFT. VALUE is evaluated exactly once. */ | |
920 | #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \ | |
921 | (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \ | |
922 | | (((VALUE) & (MASK)) << (SHIFT))) | |
923 | ||
924 | /* Extract bits MASK << SHIFT from STRUCT and shift them right | |
925 | SHIFT places. */ | |
926 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
927 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
928 | ||
929 | /* Change INSN's opcode so that the operand given by FIELD has value VALUE. | |
930 | INSN is a mips_cl_insn structure and VALUE is evaluated exactly once. | |
931 | ||
932 | include/opcode/mips.h specifies operand fields using the macros | |
933 | OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start | |
934 | with "MIPS16OP" instead of "OP". */ | |
935 | #define INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
936 | INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD) | |
937 | #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
938 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
939 | MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD) | |
940 | ||
941 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ | |
942 | #define EXTRACT_OPERAND(FIELD, INSN) \ | |
943 | EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) | |
944 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ | |
945 | EXTRACT_BITS ((INSN).insn_opcode, \ | |
946 | MIPS16OP_MASK_##FIELD, \ | |
947 | MIPS16OP_SH_##FIELD) | |
4d7206a2 RS |
948 | \f |
949 | /* Global variables used when generating relaxable macros. See the | |
950 | comment above RELAX_ENCODE for more details about how relaxation | |
951 | is used. */ | |
952 | static struct { | |
953 | /* 0 if we're not emitting a relaxable macro. | |
954 | 1 if we're emitting the first of the two relaxation alternatives. | |
955 | 2 if we're emitting the second alternative. */ | |
956 | int sequence; | |
957 | ||
958 | /* The first relaxable fixup in the current frag. (In other words, | |
959 | the first fixup that refers to relaxable code.) */ | |
960 | fixS *first_fixup; | |
961 | ||
962 | /* sizes[0] says how many bytes of the first alternative are stored in | |
963 | the current frag. Likewise sizes[1] for the second alternative. */ | |
964 | unsigned int sizes[2]; | |
965 | ||
966 | /* The symbol on which the choice of sequence depends. */ | |
967 | symbolS *symbol; | |
968 | } mips_relax; | |
252b5132 | 969 | \f |
584892a6 RS |
970 | /* Global variables used to decide whether a macro needs a warning. */ |
971 | static struct { | |
972 | /* True if the macro is in a branch delay slot. */ | |
973 | bfd_boolean delay_slot_p; | |
974 | ||
975 | /* For relaxable macros, sizes[0] is the length of the first alternative | |
976 | in bytes and sizes[1] is the length of the second alternative. | |
977 | For non-relaxable macros, both elements give the length of the | |
978 | macro in bytes. */ | |
979 | unsigned int sizes[2]; | |
980 | ||
981 | /* The first variant frag for this macro. */ | |
982 | fragS *first_frag; | |
983 | } mips_macro_warning; | |
984 | \f | |
252b5132 RH |
985 | /* Prototypes for static functions. */ |
986 | ||
17a2f251 | 987 | #define internalError() \ |
252b5132 | 988 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) |
252b5132 RH |
989 | |
990 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
991 | ||
b34976b6 | 992 | static void append_insn |
4d7206a2 | 993 | (struct mips_cl_insn *ip, expressionS *p, bfd_reloc_code_real_type *r); |
7d10b47d | 994 | static void mips_no_prev_insn (void); |
b34976b6 | 995 | static void mips16_macro_build |
67c0d1eb RS |
996 | (expressionS *, const char *, const char *, va_list); |
997 | static void load_register (int, expressionS *, int); | |
584892a6 RS |
998 | static void macro_start (void); |
999 | static void macro_end (void); | |
17a2f251 TS |
1000 | static void macro (struct mips_cl_insn * ip); |
1001 | static void mips16_macro (struct mips_cl_insn * ip); | |
252b5132 | 1002 | #ifdef LOSING_COMPILER |
17a2f251 | 1003 | static void macro2 (struct mips_cl_insn * ip); |
252b5132 | 1004 | #endif |
17a2f251 TS |
1005 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
1006 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 1007 | static void mips16_immed |
17a2f251 TS |
1008 | (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean, |
1009 | unsigned long *, bfd_boolean *, unsigned short *); | |
5e0116d5 | 1010 | static size_t my_getSmallExpression |
17a2f251 TS |
1011 | (expressionS *, bfd_reloc_code_real_type *, char *); |
1012 | static void my_getExpression (expressionS *, char *); | |
1013 | static void s_align (int); | |
1014 | static void s_change_sec (int); | |
1015 | static void s_change_section (int); | |
1016 | static void s_cons (int); | |
1017 | static void s_float_cons (int); | |
1018 | static void s_mips_globl (int); | |
1019 | static void s_option (int); | |
1020 | static void s_mipsset (int); | |
1021 | static void s_abicalls (int); | |
1022 | static void s_cpload (int); | |
1023 | static void s_cpsetup (int); | |
1024 | static void s_cplocal (int); | |
1025 | static void s_cprestore (int); | |
1026 | static void s_cpreturn (int); | |
741d6ea8 JM |
1027 | static void s_dtprelword (int); |
1028 | static void s_dtpreldword (int); | |
17a2f251 TS |
1029 | static void s_gpvalue (int); |
1030 | static void s_gpword (int); | |
1031 | static void s_gpdword (int); | |
1032 | static void s_cpadd (int); | |
1033 | static void s_insn (int); | |
1034 | static void md_obj_begin (void); | |
1035 | static void md_obj_end (void); | |
1036 | static void s_mips_ent (int); | |
1037 | static void s_mips_end (int); | |
1038 | static void s_mips_frame (int); | |
1039 | static void s_mips_mask (int reg_type); | |
1040 | static void s_mips_stab (int); | |
1041 | static void s_mips_weakext (int); | |
1042 | static void s_mips_file (int); | |
1043 | static void s_mips_loc (int); | |
1044 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 1045 | static int relaxed_branch_length (fragS *, asection *, int); |
17a2f251 | 1046 | static int validate_mips_insn (const struct mips_opcode *); |
e7af610e NC |
1047 | |
1048 | /* Table and functions used to map between CPU/ISA names, and | |
1049 | ISA levels, and CPU numbers. */ | |
1050 | ||
e972090a NC |
1051 | struct mips_cpu_info |
1052 | { | |
e7af610e | 1053 | const char *name; /* CPU or ISA name. */ |
ad3fea08 | 1054 | int flags; /* ASEs available, or ISA flag. */ |
e7af610e NC |
1055 | int isa; /* ISA level. */ |
1056 | int cpu; /* CPU number (default CPU if ISA). */ | |
1057 | }; | |
1058 | ||
ad3fea08 TS |
1059 | #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ |
1060 | #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */ | |
1061 | #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */ | |
1062 | #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */ | |
1063 | #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */ | |
1064 | #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */ | |
8b082fb1 | 1065 | #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */ |
ad3fea08 | 1066 | |
17a2f251 TS |
1067 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
1068 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
1069 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 RH |
1070 | \f |
1071 | /* Pseudo-op table. | |
1072 | ||
1073 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
1074 | should be defined here, but are currently unsupported: .alias, | |
1075 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
1076 | ||
1077 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1078 | specific to the type of debugging information being generated, and | |
1079 | should be defined by the object format: .aent, .begin, .bend, | |
1080 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
1081 | .vreg. | |
1082 | ||
1083 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1084 | not MIPS CPU specific, but are also not specific to the object file | |
1085 | format. This file is probably the best place to define them, but | |
d84bcf09 | 1086 | they are not currently supported: .asm0, .endr, .lab, .struct. */ |
252b5132 | 1087 | |
e972090a NC |
1088 | static const pseudo_typeS mips_pseudo_table[] = |
1089 | { | |
beae10d5 | 1090 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1091 | {"option", s_option, 0}, |
1092 | {"set", s_mipsset, 0}, | |
1093 | {"rdata", s_change_sec, 'r'}, | |
1094 | {"sdata", s_change_sec, 's'}, | |
1095 | {"livereg", s_ignore, 0}, | |
1096 | {"abicalls", s_abicalls, 0}, | |
1097 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1098 | {"cpsetup", s_cpsetup, 0}, |
1099 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1100 | {"cprestore", s_cprestore, 0}, |
6478892d | 1101 | {"cpreturn", s_cpreturn, 0}, |
741d6ea8 JM |
1102 | {"dtprelword", s_dtprelword, 0}, |
1103 | {"dtpreldword", s_dtpreldword, 0}, | |
6478892d | 1104 | {"gpvalue", s_gpvalue, 0}, |
252b5132 | 1105 | {"gpword", s_gpword, 0}, |
10181a0d | 1106 | {"gpdword", s_gpdword, 0}, |
252b5132 RH |
1107 | {"cpadd", s_cpadd, 0}, |
1108 | {"insn", s_insn, 0}, | |
1109 | ||
beae10d5 | 1110 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 RH |
1111 | chips. */ |
1112 | {"asciiz", stringer, 1}, | |
1113 | {"bss", s_change_sec, 'b'}, | |
1114 | {"err", s_err, 0}, | |
1115 | {"half", s_cons, 1}, | |
1116 | {"dword", s_cons, 3}, | |
1117 | {"weakext", s_mips_weakext, 0}, | |
7c752c2a TS |
1118 | {"origin", s_org, 0}, |
1119 | {"repeat", s_rept, 0}, | |
252b5132 | 1120 | |
beae10d5 | 1121 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1122 | here for one reason or another. */ |
1123 | {"align", s_align, 0}, | |
1124 | {"byte", s_cons, 0}, | |
1125 | {"data", s_change_sec, 'd'}, | |
1126 | {"double", s_float_cons, 'd'}, | |
1127 | {"float", s_float_cons, 'f'}, | |
1128 | {"globl", s_mips_globl, 0}, | |
1129 | {"global", s_mips_globl, 0}, | |
1130 | {"hword", s_cons, 1}, | |
1131 | {"int", s_cons, 2}, | |
1132 | {"long", s_cons, 2}, | |
1133 | {"octa", s_cons, 4}, | |
1134 | {"quad", s_cons, 3}, | |
cca86cc8 | 1135 | {"section", s_change_section, 0}, |
252b5132 RH |
1136 | {"short", s_cons, 1}, |
1137 | {"single", s_float_cons, 'f'}, | |
1138 | {"stabn", s_mips_stab, 'n'}, | |
1139 | {"text", s_change_sec, 't'}, | |
1140 | {"word", s_cons, 2}, | |
add56521 | 1141 | |
add56521 | 1142 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1143 | |
43841e91 | 1144 | { NULL, NULL, 0 }, |
252b5132 RH |
1145 | }; |
1146 | ||
e972090a NC |
1147 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1148 | { | |
beae10d5 KH |
1149 | /* These pseudo-ops should be defined by the object file format. |
1150 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1151 | {"aent", s_mips_ent, 1}, |
1152 | {"bgnb", s_ignore, 0}, | |
1153 | {"end", s_mips_end, 0}, | |
1154 | {"endb", s_ignore, 0}, | |
1155 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1156 | {"file", s_mips_file, 0}, |
252b5132 RH |
1157 | {"fmask", s_mips_mask, 'F'}, |
1158 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1159 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1160 | {"mask", s_mips_mask, 'R'}, |
1161 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1162 | { NULL, NULL, 0 }, |
252b5132 RH |
1163 | }; |
1164 | ||
17a2f251 | 1165 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1166 | |
1167 | void | |
17a2f251 | 1168 | mips_pop_insert (void) |
252b5132 RH |
1169 | { |
1170 | pop_insert (mips_pseudo_table); | |
1171 | if (! ECOFF_DEBUGGING) | |
1172 | pop_insert (mips_nonecoff_pseudo_table); | |
1173 | } | |
1174 | \f | |
1175 | /* Symbols labelling the current insn. */ | |
1176 | ||
e972090a NC |
1177 | struct insn_label_list |
1178 | { | |
252b5132 RH |
1179 | struct insn_label_list *next; |
1180 | symbolS *label; | |
1181 | }; | |
1182 | ||
252b5132 | 1183 | static struct insn_label_list *free_insn_labels; |
a8dbcb85 | 1184 | #define label_list tc_segment_info_data |
252b5132 | 1185 | |
17a2f251 | 1186 | static void mips_clear_insn_labels (void); |
252b5132 RH |
1187 | |
1188 | static inline void | |
17a2f251 | 1189 | mips_clear_insn_labels (void) |
252b5132 RH |
1190 | { |
1191 | register struct insn_label_list **pl; | |
a8dbcb85 | 1192 | segment_info_type *si; |
252b5132 | 1193 | |
a8dbcb85 TS |
1194 | if (now_seg) |
1195 | { | |
1196 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1197 | ; | |
1198 | ||
1199 | si = seg_info (now_seg); | |
1200 | *pl = si->label_list; | |
1201 | si->label_list = NULL; | |
1202 | } | |
252b5132 | 1203 | } |
a8dbcb85 | 1204 | |
252b5132 RH |
1205 | \f |
1206 | static char *expr_end; | |
1207 | ||
1208 | /* Expressions which appear in instructions. These are set by | |
1209 | mips_ip. */ | |
1210 | ||
1211 | static expressionS imm_expr; | |
5f74bc13 | 1212 | static expressionS imm2_expr; |
252b5132 RH |
1213 | static expressionS offset_expr; |
1214 | ||
1215 | /* Relocs associated with imm_expr and offset_expr. */ | |
1216 | ||
f6688943 TS |
1217 | static bfd_reloc_code_real_type imm_reloc[3] |
1218 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1219 | static bfd_reloc_code_real_type offset_reloc[3] | |
1220 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1221 | |
252b5132 RH |
1222 | /* These are set by mips16_ip if an explicit extension is used. */ |
1223 | ||
b34976b6 | 1224 | static bfd_boolean mips16_small, mips16_ext; |
252b5132 | 1225 | |
7ed4a06a | 1226 | #ifdef OBJ_ELF |
ecb4347a DJ |
1227 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1228 | ECOFF debugging. */ | |
252b5132 RH |
1229 | |
1230 | static segT pdr_seg; | |
7ed4a06a | 1231 | #endif |
252b5132 | 1232 | |
e013f690 TS |
1233 | /* The default target format to use. */ |
1234 | ||
1235 | const char * | |
17a2f251 | 1236 | mips_target_format (void) |
e013f690 TS |
1237 | { |
1238 | switch (OUTPUT_FLAVOR) | |
1239 | { | |
e013f690 TS |
1240 | case bfd_target_ecoff_flavour: |
1241 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1242 | case bfd_target_coff_flavour: | |
1243 | return "pe-mips"; | |
1244 | case bfd_target_elf_flavour: | |
0a44bf69 RS |
1245 | #ifdef TE_VXWORKS |
1246 | if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI) | |
1247 | return (target_big_endian | |
1248 | ? "elf32-bigmips-vxworks" | |
1249 | : "elf32-littlemips-vxworks"); | |
1250 | #endif | |
e013f690 | 1251 | #ifdef TE_TMIPS |
cfe86eaa | 1252 | /* This is traditional mips. */ |
e013f690 | 1253 | return (target_big_endian |
cfe86eaa TS |
1254 | ? (HAVE_64BIT_OBJECTS |
1255 | ? "elf64-tradbigmips" | |
1256 | : (HAVE_NEWABI | |
1257 | ? "elf32-ntradbigmips" : "elf32-tradbigmips")) | |
1258 | : (HAVE_64BIT_OBJECTS | |
1259 | ? "elf64-tradlittlemips" | |
1260 | : (HAVE_NEWABI | |
1261 | ? "elf32-ntradlittlemips" : "elf32-tradlittlemips"))); | |
e013f690 TS |
1262 | #else |
1263 | return (target_big_endian | |
cfe86eaa TS |
1264 | ? (HAVE_64BIT_OBJECTS |
1265 | ? "elf64-bigmips" | |
1266 | : (HAVE_NEWABI | |
1267 | ? "elf32-nbigmips" : "elf32-bigmips")) | |
1268 | : (HAVE_64BIT_OBJECTS | |
1269 | ? "elf64-littlemips" | |
1270 | : (HAVE_NEWABI | |
1271 | ? "elf32-nlittlemips" : "elf32-littlemips"))); | |
e013f690 TS |
1272 | #endif |
1273 | default: | |
1274 | abort (); | |
1275 | return NULL; | |
1276 | } | |
1277 | } | |
1278 | ||
1e915849 RS |
1279 | /* Return the length of instruction INSN. */ |
1280 | ||
1281 | static inline unsigned int | |
1282 | insn_length (const struct mips_cl_insn *insn) | |
1283 | { | |
1284 | if (!mips_opts.mips16) | |
1285 | return 4; | |
1286 | return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2; | |
1287 | } | |
1288 | ||
1289 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
1290 | ||
1291 | static void | |
1292 | create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) | |
1293 | { | |
1294 | size_t i; | |
1295 | ||
1296 | insn->insn_mo = mo; | |
1297 | insn->use_extend = FALSE; | |
1298 | insn->extend = 0; | |
1299 | insn->insn_opcode = mo->match; | |
1300 | insn->frag = NULL; | |
1301 | insn->where = 0; | |
1302 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1303 | insn->fixp[i] = NULL; | |
1304 | insn->fixed_p = (mips_opts.noreorder > 0); | |
1305 | insn->noreorder_p = (mips_opts.noreorder > 0); | |
1306 | insn->mips16_absolute_jump_p = 0; | |
1307 | } | |
1308 | ||
1309 | /* Install INSN at the location specified by its "frag" and "where" fields. */ | |
1310 | ||
1311 | static void | |
1312 | install_insn (const struct mips_cl_insn *insn) | |
1313 | { | |
1314 | char *f = insn->frag->fr_literal + insn->where; | |
1315 | if (!mips_opts.mips16) | |
1316 | md_number_to_chars (f, insn->insn_opcode, 4); | |
1317 | else if (insn->mips16_absolute_jump_p) | |
1318 | { | |
1319 | md_number_to_chars (f, insn->insn_opcode >> 16, 2); | |
1320 | md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2); | |
1321 | } | |
1322 | else | |
1323 | { | |
1324 | if (insn->use_extend) | |
1325 | { | |
1326 | md_number_to_chars (f, 0xf000 | insn->extend, 2); | |
1327 | f += 2; | |
1328 | } | |
1329 | md_number_to_chars (f, insn->insn_opcode, 2); | |
1330 | } | |
1331 | } | |
1332 | ||
1333 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
1334 | and install the opcode in the new location. */ | |
1335 | ||
1336 | static void | |
1337 | move_insn (struct mips_cl_insn *insn, fragS *frag, long where) | |
1338 | { | |
1339 | size_t i; | |
1340 | ||
1341 | insn->frag = frag; | |
1342 | insn->where = where; | |
1343 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1344 | if (insn->fixp[i] != NULL) | |
1345 | { | |
1346 | insn->fixp[i]->fx_frag = frag; | |
1347 | insn->fixp[i]->fx_where = where; | |
1348 | } | |
1349 | install_insn (insn); | |
1350 | } | |
1351 | ||
1352 | /* Add INSN to the end of the output. */ | |
1353 | ||
1354 | static void | |
1355 | add_fixed_insn (struct mips_cl_insn *insn) | |
1356 | { | |
1357 | char *f = frag_more (insn_length (insn)); | |
1358 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
1359 | } | |
1360 | ||
1361 | /* Start a variant frag and move INSN to the start of the variant part, | |
1362 | marking it as fixed. The other arguments are as for frag_var. */ | |
1363 | ||
1364 | static void | |
1365 | add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, | |
1366 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
1367 | { | |
1368 | frag_grow (max_chars); | |
1369 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
1370 | insn->fixed_p = 1; | |
1371 | frag_var (rs_machine_dependent, max_chars, var, | |
1372 | subtype, symbol, offset, NULL); | |
1373 | } | |
1374 | ||
1375 | /* Insert N copies of INSN into the history buffer, starting at | |
1376 | position FIRST. Neither FIRST nor N need to be clipped. */ | |
1377 | ||
1378 | static void | |
1379 | insert_into_history (unsigned int first, unsigned int n, | |
1380 | const struct mips_cl_insn *insn) | |
1381 | { | |
1382 | if (mips_relax.sequence != 2) | |
1383 | { | |
1384 | unsigned int i; | |
1385 | ||
1386 | for (i = ARRAY_SIZE (history); i-- > first;) | |
1387 | if (i >= first + n) | |
1388 | history[i] = history[i - n]; | |
1389 | else | |
1390 | history[i] = *insn; | |
1391 | } | |
1392 | } | |
1393 | ||
1394 | /* Emit a nop instruction, recording it in the history buffer. */ | |
1395 | ||
1396 | static void | |
1397 | emit_nop (void) | |
1398 | { | |
1399 | add_fixed_insn (NOP_INSN); | |
1400 | insert_into_history (0, 1, NOP_INSN); | |
1401 | } | |
1402 | ||
71400594 RS |
1403 | /* Initialize vr4120_conflicts. There is a bit of duplication here: |
1404 | the idea is to make it obvious at a glance that each errata is | |
1405 | included. */ | |
1406 | ||
1407 | static void | |
1408 | init_vr4120_conflicts (void) | |
1409 | { | |
1410 | #define CONFLICT(FIRST, SECOND) \ | |
1411 | vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND | |
1412 | ||
1413 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
1414 | CONFLICT (MACC, DIV); | |
1415 | CONFLICT (DMACC, DIV); | |
1416 | ||
1417 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ | |
1418 | CONFLICT (DMULT, DMULT); | |
1419 | CONFLICT (DMULT, DMACC); | |
1420 | CONFLICT (DMACC, DMULT); | |
1421 | CONFLICT (DMACC, DMACC); | |
1422 | ||
1423 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
1424 | CONFLICT (MACC, MTHILO); | |
1425 | CONFLICT (DMACC, MTHILO); | |
1426 | ||
1427 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU | |
1428 | instruction is executed immediately after a MACC or DMACC | |
1429 | instruction, the result of [either instruction] is incorrect." */ | |
1430 | CONFLICT (MACC, MULT); | |
1431 | CONFLICT (MACC, DMULT); | |
1432 | CONFLICT (DMACC, MULT); | |
1433 | CONFLICT (DMACC, DMULT); | |
1434 | ||
1435 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
1436 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
1437 | DDIV or DDIVU instruction, the result of the MACC or | |
1438 | DMACC instruction is incorrect.". */ | |
1439 | CONFLICT (DMULT, MACC); | |
1440 | CONFLICT (DMULT, DMACC); | |
1441 | CONFLICT (DIV, MACC); | |
1442 | CONFLICT (DIV, DMACC); | |
1443 | ||
1444 | #undef CONFLICT | |
1445 | } | |
1446 | ||
707bfff6 TS |
1447 | struct regname { |
1448 | const char *name; | |
1449 | unsigned int num; | |
1450 | }; | |
1451 | ||
1452 | #define RTYPE_MASK 0x1ff00 | |
1453 | #define RTYPE_NUM 0x00100 | |
1454 | #define RTYPE_FPU 0x00200 | |
1455 | #define RTYPE_FCC 0x00400 | |
1456 | #define RTYPE_VEC 0x00800 | |
1457 | #define RTYPE_GP 0x01000 | |
1458 | #define RTYPE_CP0 0x02000 | |
1459 | #define RTYPE_PC 0x04000 | |
1460 | #define RTYPE_ACC 0x08000 | |
1461 | #define RTYPE_CCC 0x10000 | |
1462 | #define RNUM_MASK 0x000ff | |
1463 | #define RWARN 0x80000 | |
1464 | ||
1465 | #define GENERIC_REGISTER_NUMBERS \ | |
1466 | {"$0", RTYPE_NUM | 0}, \ | |
1467 | {"$1", RTYPE_NUM | 1}, \ | |
1468 | {"$2", RTYPE_NUM | 2}, \ | |
1469 | {"$3", RTYPE_NUM | 3}, \ | |
1470 | {"$4", RTYPE_NUM | 4}, \ | |
1471 | {"$5", RTYPE_NUM | 5}, \ | |
1472 | {"$6", RTYPE_NUM | 6}, \ | |
1473 | {"$7", RTYPE_NUM | 7}, \ | |
1474 | {"$8", RTYPE_NUM | 8}, \ | |
1475 | {"$9", RTYPE_NUM | 9}, \ | |
1476 | {"$10", RTYPE_NUM | 10}, \ | |
1477 | {"$11", RTYPE_NUM | 11}, \ | |
1478 | {"$12", RTYPE_NUM | 12}, \ | |
1479 | {"$13", RTYPE_NUM | 13}, \ | |
1480 | {"$14", RTYPE_NUM | 14}, \ | |
1481 | {"$15", RTYPE_NUM | 15}, \ | |
1482 | {"$16", RTYPE_NUM | 16}, \ | |
1483 | {"$17", RTYPE_NUM | 17}, \ | |
1484 | {"$18", RTYPE_NUM | 18}, \ | |
1485 | {"$19", RTYPE_NUM | 19}, \ | |
1486 | {"$20", RTYPE_NUM | 20}, \ | |
1487 | {"$21", RTYPE_NUM | 21}, \ | |
1488 | {"$22", RTYPE_NUM | 22}, \ | |
1489 | {"$23", RTYPE_NUM | 23}, \ | |
1490 | {"$24", RTYPE_NUM | 24}, \ | |
1491 | {"$25", RTYPE_NUM | 25}, \ | |
1492 | {"$26", RTYPE_NUM | 26}, \ | |
1493 | {"$27", RTYPE_NUM | 27}, \ | |
1494 | {"$28", RTYPE_NUM | 28}, \ | |
1495 | {"$29", RTYPE_NUM | 29}, \ | |
1496 | {"$30", RTYPE_NUM | 30}, \ | |
1497 | {"$31", RTYPE_NUM | 31} | |
1498 | ||
1499 | #define FPU_REGISTER_NAMES \ | |
1500 | {"$f0", RTYPE_FPU | 0}, \ | |
1501 | {"$f1", RTYPE_FPU | 1}, \ | |
1502 | {"$f2", RTYPE_FPU | 2}, \ | |
1503 | {"$f3", RTYPE_FPU | 3}, \ | |
1504 | {"$f4", RTYPE_FPU | 4}, \ | |
1505 | {"$f5", RTYPE_FPU | 5}, \ | |
1506 | {"$f6", RTYPE_FPU | 6}, \ | |
1507 | {"$f7", RTYPE_FPU | 7}, \ | |
1508 | {"$f8", RTYPE_FPU | 8}, \ | |
1509 | {"$f9", RTYPE_FPU | 9}, \ | |
1510 | {"$f10", RTYPE_FPU | 10}, \ | |
1511 | {"$f11", RTYPE_FPU | 11}, \ | |
1512 | {"$f12", RTYPE_FPU | 12}, \ | |
1513 | {"$f13", RTYPE_FPU | 13}, \ | |
1514 | {"$f14", RTYPE_FPU | 14}, \ | |
1515 | {"$f15", RTYPE_FPU | 15}, \ | |
1516 | {"$f16", RTYPE_FPU | 16}, \ | |
1517 | {"$f17", RTYPE_FPU | 17}, \ | |
1518 | {"$f18", RTYPE_FPU | 18}, \ | |
1519 | {"$f19", RTYPE_FPU | 19}, \ | |
1520 | {"$f20", RTYPE_FPU | 20}, \ | |
1521 | {"$f21", RTYPE_FPU | 21}, \ | |
1522 | {"$f22", RTYPE_FPU | 22}, \ | |
1523 | {"$f23", RTYPE_FPU | 23}, \ | |
1524 | {"$f24", RTYPE_FPU | 24}, \ | |
1525 | {"$f25", RTYPE_FPU | 25}, \ | |
1526 | {"$f26", RTYPE_FPU | 26}, \ | |
1527 | {"$f27", RTYPE_FPU | 27}, \ | |
1528 | {"$f28", RTYPE_FPU | 28}, \ | |
1529 | {"$f29", RTYPE_FPU | 29}, \ | |
1530 | {"$f30", RTYPE_FPU | 30}, \ | |
1531 | {"$f31", RTYPE_FPU | 31} | |
1532 | ||
1533 | #define FPU_CONDITION_CODE_NAMES \ | |
1534 | {"$fcc0", RTYPE_FCC | 0}, \ | |
1535 | {"$fcc1", RTYPE_FCC | 1}, \ | |
1536 | {"$fcc2", RTYPE_FCC | 2}, \ | |
1537 | {"$fcc3", RTYPE_FCC | 3}, \ | |
1538 | {"$fcc4", RTYPE_FCC | 4}, \ | |
1539 | {"$fcc5", RTYPE_FCC | 5}, \ | |
1540 | {"$fcc6", RTYPE_FCC | 6}, \ | |
1541 | {"$fcc7", RTYPE_FCC | 7} | |
1542 | ||
1543 | #define COPROC_CONDITION_CODE_NAMES \ | |
1544 | {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \ | |
1545 | {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \ | |
1546 | {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \ | |
1547 | {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \ | |
1548 | {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \ | |
1549 | {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \ | |
1550 | {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \ | |
1551 | {"$cc7", RTYPE_FCC | RTYPE_CCC | 7} | |
1552 | ||
1553 | #define N32N64_SYMBOLIC_REGISTER_NAMES \ | |
1554 | {"$a4", RTYPE_GP | 8}, \ | |
1555 | {"$a5", RTYPE_GP | 9}, \ | |
1556 | {"$a6", RTYPE_GP | 10}, \ | |
1557 | {"$a7", RTYPE_GP | 11}, \ | |
1558 | {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \ | |
1559 | {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \ | |
1560 | {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \ | |
1561 | {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \ | |
1562 | {"$t0", RTYPE_GP | 12}, \ | |
1563 | {"$t1", RTYPE_GP | 13}, \ | |
1564 | {"$t2", RTYPE_GP | 14}, \ | |
1565 | {"$t3", RTYPE_GP | 15} | |
1566 | ||
1567 | #define O32_SYMBOLIC_REGISTER_NAMES \ | |
1568 | {"$t0", RTYPE_GP | 8}, \ | |
1569 | {"$t1", RTYPE_GP | 9}, \ | |
1570 | {"$t2", RTYPE_GP | 10}, \ | |
1571 | {"$t3", RTYPE_GP | 11}, \ | |
1572 | {"$t4", RTYPE_GP | 12}, \ | |
1573 | {"$t5", RTYPE_GP | 13}, \ | |
1574 | {"$t6", RTYPE_GP | 14}, \ | |
1575 | {"$t7", RTYPE_GP | 15}, \ | |
1576 | {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \ | |
1577 | {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \ | |
1578 | {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \ | |
1579 | {"$ta3", RTYPE_GP | 15} /* alias for $t7 */ | |
1580 | ||
1581 | /* Remaining symbolic register names */ | |
1582 | #define SYMBOLIC_REGISTER_NAMES \ | |
1583 | {"$zero", RTYPE_GP | 0}, \ | |
1584 | {"$at", RTYPE_GP | 1}, \ | |
1585 | {"$AT", RTYPE_GP | 1}, \ | |
1586 | {"$v0", RTYPE_GP | 2}, \ | |
1587 | {"$v1", RTYPE_GP | 3}, \ | |
1588 | {"$a0", RTYPE_GP | 4}, \ | |
1589 | {"$a1", RTYPE_GP | 5}, \ | |
1590 | {"$a2", RTYPE_GP | 6}, \ | |
1591 | {"$a3", RTYPE_GP | 7}, \ | |
1592 | {"$s0", RTYPE_GP | 16}, \ | |
1593 | {"$s1", RTYPE_GP | 17}, \ | |
1594 | {"$s2", RTYPE_GP | 18}, \ | |
1595 | {"$s3", RTYPE_GP | 19}, \ | |
1596 | {"$s4", RTYPE_GP | 20}, \ | |
1597 | {"$s5", RTYPE_GP | 21}, \ | |
1598 | {"$s6", RTYPE_GP | 22}, \ | |
1599 | {"$s7", RTYPE_GP | 23}, \ | |
1600 | {"$t8", RTYPE_GP | 24}, \ | |
1601 | {"$t9", RTYPE_GP | 25}, \ | |
1602 | {"$k0", RTYPE_GP | 26}, \ | |
1603 | {"$kt0", RTYPE_GP | 26}, \ | |
1604 | {"$k1", RTYPE_GP | 27}, \ | |
1605 | {"$kt1", RTYPE_GP | 27}, \ | |
1606 | {"$gp", RTYPE_GP | 28}, \ | |
1607 | {"$sp", RTYPE_GP | 29}, \ | |
1608 | {"$s8", RTYPE_GP | 30}, \ | |
1609 | {"$fp", RTYPE_GP | 30}, \ | |
1610 | {"$ra", RTYPE_GP | 31} | |
1611 | ||
1612 | #define MIPS16_SPECIAL_REGISTER_NAMES \ | |
1613 | {"$pc", RTYPE_PC | 0} | |
1614 | ||
1615 | #define MDMX_VECTOR_REGISTER_NAMES \ | |
1616 | /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \ | |
1617 | /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \ | |
1618 | {"$v2", RTYPE_VEC | 2}, \ | |
1619 | {"$v3", RTYPE_VEC | 3}, \ | |
1620 | {"$v4", RTYPE_VEC | 4}, \ | |
1621 | {"$v5", RTYPE_VEC | 5}, \ | |
1622 | {"$v6", RTYPE_VEC | 6}, \ | |
1623 | {"$v7", RTYPE_VEC | 7}, \ | |
1624 | {"$v8", RTYPE_VEC | 8}, \ | |
1625 | {"$v9", RTYPE_VEC | 9}, \ | |
1626 | {"$v10", RTYPE_VEC | 10}, \ | |
1627 | {"$v11", RTYPE_VEC | 11}, \ | |
1628 | {"$v12", RTYPE_VEC | 12}, \ | |
1629 | {"$v13", RTYPE_VEC | 13}, \ | |
1630 | {"$v14", RTYPE_VEC | 14}, \ | |
1631 | {"$v15", RTYPE_VEC | 15}, \ | |
1632 | {"$v16", RTYPE_VEC | 16}, \ | |
1633 | {"$v17", RTYPE_VEC | 17}, \ | |
1634 | {"$v18", RTYPE_VEC | 18}, \ | |
1635 | {"$v19", RTYPE_VEC | 19}, \ | |
1636 | {"$v20", RTYPE_VEC | 20}, \ | |
1637 | {"$v21", RTYPE_VEC | 21}, \ | |
1638 | {"$v22", RTYPE_VEC | 22}, \ | |
1639 | {"$v23", RTYPE_VEC | 23}, \ | |
1640 | {"$v24", RTYPE_VEC | 24}, \ | |
1641 | {"$v25", RTYPE_VEC | 25}, \ | |
1642 | {"$v26", RTYPE_VEC | 26}, \ | |
1643 | {"$v27", RTYPE_VEC | 27}, \ | |
1644 | {"$v28", RTYPE_VEC | 28}, \ | |
1645 | {"$v29", RTYPE_VEC | 29}, \ | |
1646 | {"$v30", RTYPE_VEC | 30}, \ | |
1647 | {"$v31", RTYPE_VEC | 31} | |
1648 | ||
1649 | #define MIPS_DSP_ACCUMULATOR_NAMES \ | |
1650 | {"$ac0", RTYPE_ACC | 0}, \ | |
1651 | {"$ac1", RTYPE_ACC | 1}, \ | |
1652 | {"$ac2", RTYPE_ACC | 2}, \ | |
1653 | {"$ac3", RTYPE_ACC | 3} | |
1654 | ||
1655 | static const struct regname reg_names[] = { | |
1656 | GENERIC_REGISTER_NUMBERS, | |
1657 | FPU_REGISTER_NAMES, | |
1658 | FPU_CONDITION_CODE_NAMES, | |
1659 | COPROC_CONDITION_CODE_NAMES, | |
1660 | ||
1661 | /* The $txx registers depends on the abi, | |
1662 | these will be added later into the symbol table from | |
1663 | one of the tables below once mips_abi is set after | |
1664 | parsing of arguments from the command line. */ | |
1665 | SYMBOLIC_REGISTER_NAMES, | |
1666 | ||
1667 | MIPS16_SPECIAL_REGISTER_NAMES, | |
1668 | MDMX_VECTOR_REGISTER_NAMES, | |
1669 | MIPS_DSP_ACCUMULATOR_NAMES, | |
1670 | {0, 0} | |
1671 | }; | |
1672 | ||
1673 | static const struct regname reg_names_o32[] = { | |
1674 | O32_SYMBOLIC_REGISTER_NAMES, | |
1675 | {0, 0} | |
1676 | }; | |
1677 | ||
1678 | static const struct regname reg_names_n32n64[] = { | |
1679 | N32N64_SYMBOLIC_REGISTER_NAMES, | |
1680 | {0, 0} | |
1681 | }; | |
1682 | ||
1683 | static int | |
1684 | reg_lookup (char **s, unsigned int types, unsigned int *regnop) | |
1685 | { | |
1686 | symbolS *symbolP; | |
1687 | char *e; | |
1688 | char save_c; | |
1689 | int reg = -1; | |
1690 | ||
1691 | /* Find end of name. */ | |
1692 | e = *s; | |
1693 | if (is_name_beginner (*e)) | |
1694 | ++e; | |
1695 | while (is_part_of_name (*e)) | |
1696 | ++e; | |
1697 | ||
1698 | /* Terminate name. */ | |
1699 | save_c = *e; | |
1700 | *e = '\0'; | |
1701 | ||
1702 | /* Look for a register symbol. */ | |
1703 | if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section) | |
1704 | { | |
1705 | int r = S_GET_VALUE (symbolP); | |
1706 | if (r & types) | |
1707 | reg = r & RNUM_MASK; | |
1708 | else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2)) | |
1709 | /* Convert GP reg $v0/1 to MDMX reg $v0/1! */ | |
1710 | reg = (r & RNUM_MASK) - 2; | |
1711 | } | |
1712 | /* Else see if this is a register defined in an itbl entry. */ | |
1713 | else if ((types & RTYPE_GP) && itbl_have_entries) | |
1714 | { | |
1715 | char *n = *s; | |
1716 | unsigned long r; | |
1717 | ||
1718 | if (*n == '$') | |
1719 | ++n; | |
1720 | if (itbl_get_reg_val (n, &r)) | |
1721 | reg = r & RNUM_MASK; | |
1722 | } | |
1723 | ||
1724 | /* Advance to next token if a register was recognised. */ | |
1725 | if (reg >= 0) | |
1726 | *s = e; | |
1727 | else if (types & RWARN) | |
1728 | as_warn ("Unrecognized register name `%s'", *s); | |
1729 | ||
1730 | *e = save_c; | |
1731 | if (regnop) | |
1732 | *regnop = reg; | |
1733 | return reg >= 0; | |
1734 | } | |
1735 | ||
1736 | /* This function is called once, at assembler startup time. It should set up | |
1737 | all the tables, etc. that the MD part of the assembler will need. */ | |
156c2f8b | 1738 | |
252b5132 | 1739 | void |
17a2f251 | 1740 | md_begin (void) |
252b5132 | 1741 | { |
3994f87e | 1742 | const char *retval = NULL; |
156c2f8b | 1743 | int i = 0; |
252b5132 | 1744 | int broken = 0; |
1f25f5d3 | 1745 | |
0a44bf69 RS |
1746 | if (mips_pic != NO_PIC) |
1747 | { | |
1748 | if (g_switch_seen && g_switch_value != 0) | |
1749 | as_bad (_("-G may not be used in position-independent code")); | |
1750 | g_switch_value = 0; | |
1751 | } | |
1752 | ||
fef14a42 | 1753 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) |
252b5132 RH |
1754 | as_warn (_("Could not set architecture and machine")); |
1755 | ||
252b5132 RH |
1756 | op_hash = hash_new (); |
1757 | ||
1758 | for (i = 0; i < NUMOPCODES;) | |
1759 | { | |
1760 | const char *name = mips_opcodes[i].name; | |
1761 | ||
17a2f251 | 1762 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
1763 | if (retval != NULL) |
1764 | { | |
1765 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
1766 | mips_opcodes[i].name, retval); | |
1767 | /* Probably a memory allocation problem? Give up now. */ | |
1768 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1769 | } | |
1770 | do | |
1771 | { | |
1772 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
1773 | { | |
1774 | if (!validate_mips_insn (&mips_opcodes[i])) | |
1775 | broken = 1; | |
1e915849 RS |
1776 | if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
1777 | { | |
1778 | create_insn (&nop_insn, mips_opcodes + i); | |
1779 | nop_insn.fixed_p = 1; | |
1780 | } | |
252b5132 RH |
1781 | } |
1782 | ++i; | |
1783 | } | |
1784 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
1785 | } | |
1786 | ||
1787 | mips16_op_hash = hash_new (); | |
1788 | ||
1789 | i = 0; | |
1790 | while (i < bfd_mips16_num_opcodes) | |
1791 | { | |
1792 | const char *name = mips16_opcodes[i].name; | |
1793 | ||
17a2f251 | 1794 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
1795 | if (retval != NULL) |
1796 | as_fatal (_("internal: can't hash `%s': %s"), | |
1797 | mips16_opcodes[i].name, retval); | |
1798 | do | |
1799 | { | |
1800 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1801 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1802 | != mips16_opcodes[i].match)) | |
1803 | { | |
1804 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
1805 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1806 | broken = 1; | |
1807 | } | |
1e915849 RS |
1808 | if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
1809 | { | |
1810 | create_insn (&mips16_nop_insn, mips16_opcodes + i); | |
1811 | mips16_nop_insn.fixed_p = 1; | |
1812 | } | |
252b5132 RH |
1813 | ++i; |
1814 | } | |
1815 | while (i < bfd_mips16_num_opcodes | |
1816 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1817 | } | |
1818 | ||
1819 | if (broken) | |
1820 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1821 | ||
1822 | /* We add all the general register names to the symbol table. This | |
1823 | helps us detect invalid uses of them. */ | |
707bfff6 TS |
1824 | for (i = 0; reg_names[i].name; i++) |
1825 | symbol_table_insert (symbol_new (reg_names[i].name, reg_section, | |
1826 | reg_names[i].num, // & RNUM_MASK, | |
1827 | &zero_address_frag)); | |
1828 | if (HAVE_NEWABI) | |
1829 | for (i = 0; reg_names_n32n64[i].name; i++) | |
1830 | symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section, | |
1831 | reg_names_n32n64[i].num, // & RNUM_MASK, | |
252b5132 | 1832 | &zero_address_frag)); |
707bfff6 TS |
1833 | else |
1834 | for (i = 0; reg_names_o32[i].name; i++) | |
1835 | symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section, | |
1836 | reg_names_o32[i].num, // & RNUM_MASK, | |
6047c971 | 1837 | &zero_address_frag)); |
6047c971 | 1838 | |
7d10b47d | 1839 | mips_no_prev_insn (); |
252b5132 RH |
1840 | |
1841 | mips_gprmask = 0; | |
1842 | mips_cprmask[0] = 0; | |
1843 | mips_cprmask[1] = 0; | |
1844 | mips_cprmask[2] = 0; | |
1845 | mips_cprmask[3] = 0; | |
1846 | ||
1847 | /* set the default alignment for the text section (2**2) */ | |
1848 | record_alignment (text_section, 2); | |
1849 | ||
4d0d148d | 1850 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 | 1851 | |
707bfff6 | 1852 | #ifdef OBJ_ELF |
f43abd2b | 1853 | if (IS_ELF) |
252b5132 | 1854 | { |
0a44bf69 RS |
1855 | /* On a native system other than VxWorks, sections must be aligned |
1856 | to 16 byte boundaries. When configured for an embedded ELF | |
1857 | target, we don't bother. */ | |
1858 | if (strcmp (TARGET_OS, "elf") != 0 | |
1859 | && strcmp (TARGET_OS, "vxworks") != 0) | |
252b5132 RH |
1860 | { |
1861 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
1862 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
1863 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
1864 | } | |
1865 | ||
1866 | /* Create a .reginfo section for register masks and a .mdebug | |
1867 | section for debugging information. */ | |
1868 | { | |
1869 | segT seg; | |
1870 | subsegT subseg; | |
1871 | flagword flags; | |
1872 | segT sec; | |
1873 | ||
1874 | seg = now_seg; | |
1875 | subseg = now_subseg; | |
1876 | ||
1877 | /* The ABI says this section should be loaded so that the | |
1878 | running program can access it. However, we don't load it | |
1879 | if we are configured for an embedded target */ | |
1880 | flags = SEC_READONLY | SEC_DATA; | |
1881 | if (strcmp (TARGET_OS, "elf") != 0) | |
1882 | flags |= SEC_ALLOC | SEC_LOAD; | |
1883 | ||
316f5878 | 1884 | if (mips_abi != N64_ABI) |
252b5132 RH |
1885 | { |
1886 | sec = subseg_new (".reginfo", (subsegT) 0); | |
1887 | ||
195325d2 TS |
1888 | bfd_set_section_flags (stdoutput, sec, flags); |
1889 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 1890 | |
252b5132 | 1891 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
252b5132 RH |
1892 | } |
1893 | else | |
1894 | { | |
1895 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
1896 | .reginfo section. */ | |
1897 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
1898 | bfd_set_section_flags (stdoutput, sec, flags); |
1899 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 | 1900 | |
252b5132 RH |
1901 | /* Set up the option header. */ |
1902 | { | |
1903 | Elf_Internal_Options opthdr; | |
1904 | char *f; | |
1905 | ||
1906 | opthdr.kind = ODK_REGINFO; | |
1907 | opthdr.size = (sizeof (Elf_External_Options) | |
1908 | + sizeof (Elf64_External_RegInfo)); | |
1909 | opthdr.section = 0; | |
1910 | opthdr.info = 0; | |
1911 | f = frag_more (sizeof (Elf_External_Options)); | |
1912 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
1913 | (Elf_External_Options *) f); | |
1914 | ||
1915 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
1916 | } | |
252b5132 RH |
1917 | } |
1918 | ||
1919 | if (ECOFF_DEBUGGING) | |
1920 | { | |
1921 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1922 | (void) bfd_set_section_flags (stdoutput, sec, | |
1923 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1924 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1925 | } | |
f43abd2b | 1926 | else if (mips_flag_pdr) |
ecb4347a DJ |
1927 | { |
1928 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
1929 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
1930 | SEC_READONLY | SEC_RELOC | |
1931 | | SEC_DEBUGGING); | |
1932 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
1933 | } | |
252b5132 RH |
1934 | |
1935 | subseg_set (seg, subseg); | |
1936 | } | |
1937 | } | |
707bfff6 | 1938 | #endif /* OBJ_ELF */ |
252b5132 RH |
1939 | |
1940 | if (! ECOFF_DEBUGGING) | |
1941 | md_obj_begin (); | |
71400594 RS |
1942 | |
1943 | if (mips_fix_vr4120) | |
1944 | init_vr4120_conflicts (); | |
252b5132 RH |
1945 | } |
1946 | ||
1947 | void | |
17a2f251 | 1948 | md_mips_end (void) |
252b5132 RH |
1949 | { |
1950 | if (! ECOFF_DEBUGGING) | |
1951 | md_obj_end (); | |
1952 | } | |
1953 | ||
1954 | void | |
17a2f251 | 1955 | md_assemble (char *str) |
252b5132 RH |
1956 | { |
1957 | struct mips_cl_insn insn; | |
f6688943 TS |
1958 | bfd_reloc_code_real_type unused_reloc[3] |
1959 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
1960 | |
1961 | imm_expr.X_op = O_absent; | |
5f74bc13 | 1962 | imm2_expr.X_op = O_absent; |
252b5132 | 1963 | offset_expr.X_op = O_absent; |
f6688943 TS |
1964 | imm_reloc[0] = BFD_RELOC_UNUSED; |
1965 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
1966 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
1967 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
1968 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
1969 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
1970 | |
1971 | if (mips_opts.mips16) | |
1972 | mips16_ip (str, &insn); | |
1973 | else | |
1974 | { | |
1975 | mips_ip (str, &insn); | |
beae10d5 KH |
1976 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
1977 | str, insn.insn_opcode)); | |
252b5132 RH |
1978 | } |
1979 | ||
1980 | if (insn_error) | |
1981 | { | |
1982 | as_bad ("%s `%s'", insn_error, str); | |
1983 | return; | |
1984 | } | |
1985 | ||
1986 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
1987 | { | |
584892a6 | 1988 | macro_start (); |
252b5132 RH |
1989 | if (mips_opts.mips16) |
1990 | mips16_macro (&insn); | |
1991 | else | |
1992 | macro (&insn); | |
584892a6 | 1993 | macro_end (); |
252b5132 RH |
1994 | } |
1995 | else | |
1996 | { | |
1997 | if (imm_expr.X_op != O_absent) | |
4d7206a2 | 1998 | append_insn (&insn, &imm_expr, imm_reloc); |
252b5132 | 1999 | else if (offset_expr.X_op != O_absent) |
4d7206a2 | 2000 | append_insn (&insn, &offset_expr, offset_reloc); |
252b5132 | 2001 | else |
4d7206a2 | 2002 | append_insn (&insn, NULL, unused_reloc); |
252b5132 RH |
2003 | } |
2004 | } | |
2005 | ||
5919d012 | 2006 | /* Return true if the given relocation might need a matching %lo(). |
0a44bf69 RS |
2007 | This is only "might" because SVR4 R_MIPS_GOT16 relocations only |
2008 | need a matching %lo() when applied to local symbols. */ | |
5919d012 RS |
2009 | |
2010 | static inline bfd_boolean | |
17a2f251 | 2011 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 2012 | { |
3b91255e RS |
2013 | return (HAVE_IN_PLACE_ADDENDS |
2014 | && (reloc == BFD_RELOC_HI16_S | |
0a44bf69 RS |
2015 | || reloc == BFD_RELOC_MIPS16_HI16_S |
2016 | /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo(); | |
2017 | all GOT16 relocations evaluate to "G". */ | |
2018 | || (reloc == BFD_RELOC_MIPS_GOT16 && mips_pic != VXWORKS_PIC))); | |
5919d012 RS |
2019 | } |
2020 | ||
2021 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
2022 | relocation. */ | |
2023 | ||
2024 | static inline bfd_boolean | |
17a2f251 | 2025 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
2026 | { |
2027 | return (fixp->fx_next != NULL | |
d6f16593 MR |
2028 | && (fixp->fx_next->fx_r_type == BFD_RELOC_LO16 |
2029 | || fixp->fx_next->fx_r_type == BFD_RELOC_MIPS16_LO16) | |
5919d012 RS |
2030 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
2031 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
2032 | } | |
2033 | ||
252b5132 RH |
2034 | /* See whether instruction IP reads register REG. CLASS is the type |
2035 | of register. */ | |
2036 | ||
2037 | static int | |
71400594 | 2038 | insn_uses_reg (const struct mips_cl_insn *ip, unsigned int reg, |
17a2f251 | 2039 | enum mips_regclass class) |
252b5132 RH |
2040 | { |
2041 | if (class == MIPS16_REG) | |
2042 | { | |
2043 | assert (mips_opts.mips16); | |
2044 | reg = mips16_to_32_reg_map[reg]; | |
2045 | class = MIPS_GR_REG; | |
2046 | } | |
2047 | ||
85b51719 TS |
2048 | /* Don't report on general register ZERO, since it never changes. */ |
2049 | if (class == MIPS_GR_REG && reg == ZERO) | |
252b5132 RH |
2050 | return 0; |
2051 | ||
2052 | if (class == MIPS_FP_REG) | |
2053 | { | |
2054 | assert (! mips_opts.mips16); | |
2055 | /* If we are called with either $f0 or $f1, we must check $f0. | |
2056 | This is not optimal, because it will introduce an unnecessary | |
2057 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
2058 | need to distinguish reading both $f0 and $f1 or just one of | |
2059 | them. Note that we don't have to check the other way, | |
2060 | because there is no instruction that sets both $f0 and $f1 | |
2061 | and requires a delay. */ | |
2062 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
bf12938e | 2063 | && ((EXTRACT_OPERAND (FS, *ip) & ~(unsigned) 1) |
252b5132 RH |
2064 | == (reg &~ (unsigned) 1))) |
2065 | return 1; | |
2066 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
bf12938e | 2067 | && ((EXTRACT_OPERAND (FT, *ip) & ~(unsigned) 1) |
252b5132 RH |
2068 | == (reg &~ (unsigned) 1))) |
2069 | return 1; | |
2070 | } | |
2071 | else if (! mips_opts.mips16) | |
2072 | { | |
2073 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
bf12938e | 2074 | && EXTRACT_OPERAND (RS, *ip) == reg) |
252b5132 RH |
2075 | return 1; |
2076 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
bf12938e | 2077 | && EXTRACT_OPERAND (RT, *ip) == reg) |
252b5132 RH |
2078 | return 1; |
2079 | } | |
2080 | else | |
2081 | { | |
2082 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
bf12938e | 2083 | && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)] == reg) |
252b5132 RH |
2084 | return 1; |
2085 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
bf12938e | 2086 | && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)] == reg) |
252b5132 RH |
2087 | return 1; |
2088 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
bf12938e | 2089 | && (mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)] |
252b5132 RH |
2090 | == reg)) |
2091 | return 1; | |
2092 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
2093 | return 1; | |
2094 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
2095 | return 1; | |
2096 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
2097 | return 1; | |
2098 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
bf12938e | 2099 | && MIPS16_EXTRACT_OPERAND (REGR32, *ip) == reg) |
252b5132 RH |
2100 | return 1; |
2101 | } | |
2102 | ||
2103 | return 0; | |
2104 | } | |
2105 | ||
2106 | /* This function returns true if modifying a register requires a | |
2107 | delay. */ | |
2108 | ||
2109 | static int | |
17a2f251 | 2110 | reg_needs_delay (unsigned int reg) |
252b5132 RH |
2111 | { |
2112 | unsigned long prev_pinfo; | |
2113 | ||
47e39b9d | 2114 | prev_pinfo = history[0].insn_mo->pinfo; |
252b5132 | 2115 | if (! mips_opts.noreorder |
81912461 ILT |
2116 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
2117 | && ! gpr_interlocks) | |
2118 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
2119 | && ! cop_interlocks))) | |
252b5132 | 2120 | { |
81912461 ILT |
2121 | /* A load from a coprocessor or from memory. All load delays |
2122 | delay the use of general register rt for one instruction. */ | |
bdaaa2e1 | 2123 | /* Itbl support may require additional care here. */ |
252b5132 | 2124 | know (prev_pinfo & INSN_WRITE_GPR_T); |
bf12938e | 2125 | if (reg == EXTRACT_OPERAND (RT, history[0])) |
252b5132 RH |
2126 | return 1; |
2127 | } | |
2128 | ||
2129 | return 0; | |
2130 | } | |
2131 | ||
404a8071 RS |
2132 | /* Move all labels in insn_labels to the current insertion point. */ |
2133 | ||
2134 | static void | |
2135 | mips_move_labels (void) | |
2136 | { | |
a8dbcb85 | 2137 | segment_info_type *si = seg_info (now_seg); |
404a8071 RS |
2138 | struct insn_label_list *l; |
2139 | valueT val; | |
2140 | ||
a8dbcb85 | 2141 | for (l = si->label_list; l != NULL; l = l->next) |
404a8071 RS |
2142 | { |
2143 | assert (S_GET_SEGMENT (l->label) == now_seg); | |
2144 | symbol_set_frag (l->label, frag_now); | |
2145 | val = (valueT) frag_now_fix (); | |
2146 | /* mips16 text labels are stored as odd. */ | |
2147 | if (mips_opts.mips16) | |
2148 | ++val; | |
2149 | S_SET_VALUE (l->label, val); | |
2150 | } | |
2151 | } | |
2152 | ||
5f0fe04b TS |
2153 | static bfd_boolean |
2154 | s_is_linkonce (symbolS *sym, segT from_seg) | |
2155 | { | |
2156 | bfd_boolean linkonce = FALSE; | |
2157 | segT symseg = S_GET_SEGMENT (sym); | |
2158 | ||
2159 | if (symseg != from_seg && !S_IS_LOCAL (sym)) | |
2160 | { | |
2161 | if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE)) | |
2162 | linkonce = TRUE; | |
2163 | #ifdef OBJ_ELF | |
2164 | /* The GNU toolchain uses an extension for ELF: a section | |
2165 | beginning with the magic string .gnu.linkonce is a | |
2166 | linkonce section. */ | |
2167 | if (strncmp (segment_name (symseg), ".gnu.linkonce", | |
2168 | sizeof ".gnu.linkonce" - 1) == 0) | |
2169 | linkonce = TRUE; | |
2170 | #endif | |
2171 | } | |
2172 | return linkonce; | |
2173 | } | |
2174 | ||
252b5132 RH |
2175 | /* Mark instruction labels in mips16 mode. This permits the linker to |
2176 | handle them specially, such as generating jalx instructions when | |
2177 | needed. We also make them odd for the duration of the assembly, in | |
2178 | order to generate the right sort of code. We will make them even | |
2179 | in the adjust_symtab routine, while leaving them marked. This is | |
2180 | convenient for the debugger and the disassembler. The linker knows | |
2181 | to make them odd again. */ | |
2182 | ||
2183 | static void | |
17a2f251 | 2184 | mips16_mark_labels (void) |
252b5132 | 2185 | { |
a8dbcb85 TS |
2186 | segment_info_type *si = seg_info (now_seg); |
2187 | struct insn_label_list *l; | |
252b5132 | 2188 | |
a8dbcb85 TS |
2189 | if (!mips_opts.mips16) |
2190 | return; | |
2191 | ||
2192 | for (l = si->label_list; l != NULL; l = l->next) | |
2193 | { | |
2194 | symbolS *label = l->label; | |
2195 | ||
2196 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) | |
f43abd2b | 2197 | if (IS_ELF) |
a8dbcb85 | 2198 | S_SET_OTHER (label, STO_MIPS16); |
252b5132 | 2199 | #endif |
5f0fe04b TS |
2200 | if ((S_GET_VALUE (label) & 1) == 0 |
2201 | /* Don't adjust the address if the label is global or weak, or | |
2202 | in a link-once section, since we'll be emitting symbol reloc | |
2203 | references to it which will be patched up by the linker, and | |
2204 | the final value of the symbol may or may not be MIPS16. */ | |
2205 | && ! S_IS_WEAK (label) | |
2206 | && ! S_IS_EXTERNAL (label) | |
2207 | && ! s_is_linkonce (label, now_seg)) | |
a8dbcb85 | 2208 | S_SET_VALUE (label, S_GET_VALUE (label) | 1); |
252b5132 RH |
2209 | } |
2210 | } | |
2211 | ||
4d7206a2 RS |
2212 | /* End the current frag. Make it a variant frag and record the |
2213 | relaxation info. */ | |
2214 | ||
2215 | static void | |
2216 | relax_close_frag (void) | |
2217 | { | |
584892a6 | 2218 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 2219 | frag_var (rs_machine_dependent, 0, 0, |
584892a6 | 2220 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), |
4d7206a2 RS |
2221 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
2222 | ||
2223 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
2224 | mips_relax.first_fixup = 0; | |
2225 | } | |
2226 | ||
2227 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
2228 | See the comment above RELAX_ENCODE for more details. */ | |
2229 | ||
2230 | static void | |
2231 | relax_start (symbolS *symbol) | |
2232 | { | |
2233 | assert (mips_relax.sequence == 0); | |
2234 | mips_relax.sequence = 1; | |
2235 | mips_relax.symbol = symbol; | |
2236 | } | |
2237 | ||
2238 | /* Start generating the second version of a relaxable sequence. | |
2239 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
2240 | |
2241 | static void | |
4d7206a2 RS |
2242 | relax_switch (void) |
2243 | { | |
2244 | assert (mips_relax.sequence == 1); | |
2245 | mips_relax.sequence = 2; | |
2246 | } | |
2247 | ||
2248 | /* End the current relaxable sequence. */ | |
2249 | ||
2250 | static void | |
2251 | relax_end (void) | |
2252 | { | |
2253 | assert (mips_relax.sequence == 2); | |
2254 | relax_close_frag (); | |
2255 | mips_relax.sequence = 0; | |
2256 | } | |
2257 | ||
71400594 RS |
2258 | /* Classify an instruction according to the FIX_VR4120_* enumeration. |
2259 | Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected | |
2260 | by VR4120 errata. */ | |
4d7206a2 | 2261 | |
71400594 RS |
2262 | static unsigned int |
2263 | classify_vr4120_insn (const char *name) | |
252b5132 | 2264 | { |
71400594 RS |
2265 | if (strncmp (name, "macc", 4) == 0) |
2266 | return FIX_VR4120_MACC; | |
2267 | if (strncmp (name, "dmacc", 5) == 0) | |
2268 | return FIX_VR4120_DMACC; | |
2269 | if (strncmp (name, "mult", 4) == 0) | |
2270 | return FIX_VR4120_MULT; | |
2271 | if (strncmp (name, "dmult", 5) == 0) | |
2272 | return FIX_VR4120_DMULT; | |
2273 | if (strstr (name, "div")) | |
2274 | return FIX_VR4120_DIV; | |
2275 | if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) | |
2276 | return FIX_VR4120_MTHILO; | |
2277 | return NUM_FIX_VR4120_CLASSES; | |
2278 | } | |
252b5132 | 2279 | |
71400594 RS |
2280 | /* Return the number of instructions that must separate INSN1 and INSN2, |
2281 | where INSN1 is the earlier instruction. Return the worst-case value | |
2282 | for any INSN2 if INSN2 is null. */ | |
252b5132 | 2283 | |
71400594 RS |
2284 | static unsigned int |
2285 | insns_between (const struct mips_cl_insn *insn1, | |
2286 | const struct mips_cl_insn *insn2) | |
2287 | { | |
2288 | unsigned long pinfo1, pinfo2; | |
2289 | ||
2290 | /* This function needs to know which pinfo flags are set for INSN2 | |
2291 | and which registers INSN2 uses. The former is stored in PINFO2 and | |
2292 | the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2 | |
2293 | will have every flag set and INSN2_USES_REG will always return true. */ | |
2294 | pinfo1 = insn1->insn_mo->pinfo; | |
2295 | pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; | |
252b5132 | 2296 | |
71400594 RS |
2297 | #define INSN2_USES_REG(REG, CLASS) \ |
2298 | (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS)) | |
2299 | ||
2300 | /* For most targets, write-after-read dependencies on the HI and LO | |
2301 | registers must be separated by at least two instructions. */ | |
2302 | if (!hilo_interlocks) | |
252b5132 | 2303 | { |
71400594 RS |
2304 | if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) |
2305 | return 2; | |
2306 | if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) | |
2307 | return 2; | |
2308 | } | |
2309 | ||
2310 | /* If we're working around r7000 errata, there must be two instructions | |
2311 | between an mfhi or mflo and any instruction that uses the result. */ | |
2312 | if (mips_7000_hilo_fix | |
2313 | && MF_HILO_INSN (pinfo1) | |
2314 | && INSN2_USES_REG (EXTRACT_OPERAND (RD, *insn1), MIPS_GR_REG)) | |
2315 | return 2; | |
2316 | ||
2317 | /* If working around VR4120 errata, check for combinations that need | |
2318 | a single intervening instruction. */ | |
2319 | if (mips_fix_vr4120) | |
2320 | { | |
2321 | unsigned int class1, class2; | |
252b5132 | 2322 | |
71400594 RS |
2323 | class1 = classify_vr4120_insn (insn1->insn_mo->name); |
2324 | if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) | |
252b5132 | 2325 | { |
71400594 RS |
2326 | if (insn2 == NULL) |
2327 | return 1; | |
2328 | class2 = classify_vr4120_insn (insn2->insn_mo->name); | |
2329 | if (vr4120_conflicts[class1] & (1 << class2)) | |
2330 | return 1; | |
252b5132 | 2331 | } |
71400594 RS |
2332 | } |
2333 | ||
2334 | if (!mips_opts.mips16) | |
2335 | { | |
2336 | /* Check for GPR or coprocessor load delays. All such delays | |
2337 | are on the RT register. */ | |
2338 | /* Itbl support may require additional care here. */ | |
2339 | if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY)) | |
2340 | || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY))) | |
252b5132 | 2341 | { |
71400594 RS |
2342 | know (pinfo1 & INSN_WRITE_GPR_T); |
2343 | if (INSN2_USES_REG (EXTRACT_OPERAND (RT, *insn1), MIPS_GR_REG)) | |
2344 | return 1; | |
2345 | } | |
2346 | ||
2347 | /* Check for generic coprocessor hazards. | |
2348 | ||
2349 | This case is not handled very well. There is no special | |
2350 | knowledge of CP0 handling, and the coprocessors other than | |
2351 | the floating point unit are not distinguished at all. */ | |
2352 | /* Itbl support may require additional care here. FIXME! | |
2353 | Need to modify this to include knowledge about | |
2354 | user specified delays! */ | |
2355 | else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY)) | |
2356 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) | |
2357 | { | |
2358 | /* Handle cases where INSN1 writes to a known general coprocessor | |
2359 | register. There must be a one instruction delay before INSN2 | |
2360 | if INSN2 reads that register, otherwise no delay is needed. */ | |
2361 | if (pinfo1 & INSN_WRITE_FPR_T) | |
252b5132 | 2362 | { |
71400594 RS |
2363 | if (INSN2_USES_REG (EXTRACT_OPERAND (FT, *insn1), MIPS_FP_REG)) |
2364 | return 1; | |
252b5132 | 2365 | } |
71400594 | 2366 | else if (pinfo1 & INSN_WRITE_FPR_S) |
252b5132 | 2367 | { |
71400594 RS |
2368 | if (INSN2_USES_REG (EXTRACT_OPERAND (FS, *insn1), MIPS_FP_REG)) |
2369 | return 1; | |
252b5132 RH |
2370 | } |
2371 | else | |
2372 | { | |
71400594 RS |
2373 | /* Read-after-write dependencies on the control registers |
2374 | require a two-instruction gap. */ | |
2375 | if ((pinfo1 & INSN_WRITE_COND_CODE) | |
2376 | && (pinfo2 & INSN_READ_COND_CODE)) | |
2377 | return 2; | |
2378 | ||
2379 | /* We don't know exactly what INSN1 does. If INSN2 is | |
2380 | also a coprocessor instruction, assume there must be | |
2381 | a one instruction gap. */ | |
2382 | if (pinfo2 & INSN_COP) | |
2383 | return 1; | |
252b5132 RH |
2384 | } |
2385 | } | |
6b76fefe | 2386 | |
71400594 RS |
2387 | /* Check for read-after-write dependencies on the coprocessor |
2388 | control registers in cases where INSN1 does not need a general | |
2389 | coprocessor delay. This means that INSN1 is a floating point | |
2390 | comparison instruction. */ | |
2391 | /* Itbl support may require additional care here. */ | |
2392 | else if (!cop_interlocks | |
2393 | && (pinfo1 & INSN_WRITE_COND_CODE) | |
2394 | && (pinfo2 & INSN_READ_COND_CODE)) | |
2395 | return 1; | |
2396 | } | |
6b76fefe | 2397 | |
71400594 | 2398 | #undef INSN2_USES_REG |
6b76fefe | 2399 | |
71400594 RS |
2400 | return 0; |
2401 | } | |
6b76fefe | 2402 | |
7d8e00cf RS |
2403 | /* Return the number of nops that would be needed to work around the |
2404 | VR4130 mflo/mfhi errata if instruction INSN immediately followed | |
2405 | the MAX_VR4130_NOPS instructions described by HISTORY. */ | |
2406 | ||
2407 | static int | |
2408 | nops_for_vr4130 (const struct mips_cl_insn *history, | |
2409 | const struct mips_cl_insn *insn) | |
2410 | { | |
2411 | int i, j, reg; | |
2412 | ||
2413 | /* Check if the instruction writes to HI or LO. MTHI and MTLO | |
2414 | are not affected by the errata. */ | |
2415 | if (insn != 0 | |
2416 | && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 | |
2417 | || strcmp (insn->insn_mo->name, "mtlo") == 0 | |
2418 | || strcmp (insn->insn_mo->name, "mthi") == 0)) | |
2419 | return 0; | |
2420 | ||
2421 | /* Search for the first MFLO or MFHI. */ | |
2422 | for (i = 0; i < MAX_VR4130_NOPS; i++) | |
2423 | if (!history[i].noreorder_p && MF_HILO_INSN (history[i].insn_mo->pinfo)) | |
2424 | { | |
2425 | /* Extract the destination register. */ | |
2426 | if (mips_opts.mips16) | |
2427 | reg = mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, history[i])]; | |
2428 | else | |
2429 | reg = EXTRACT_OPERAND (RD, history[i]); | |
2430 | ||
2431 | /* No nops are needed if INSN reads that register. */ | |
2432 | if (insn != NULL && insn_uses_reg (insn, reg, MIPS_GR_REG)) | |
2433 | return 0; | |
2434 | ||
2435 | /* ...or if any of the intervening instructions do. */ | |
2436 | for (j = 0; j < i; j++) | |
2437 | if (insn_uses_reg (&history[j], reg, MIPS_GR_REG)) | |
2438 | return 0; | |
2439 | ||
2440 | return MAX_VR4130_NOPS - i; | |
2441 | } | |
2442 | return 0; | |
2443 | } | |
2444 | ||
71400594 RS |
2445 | /* Return the number of nops that would be needed if instruction INSN |
2446 | immediately followed the MAX_NOPS instructions given by HISTORY, | |
2447 | where HISTORY[0] is the most recent instruction. If INSN is null, | |
2448 | return the worse-case number of nops for any instruction. */ | |
bdaaa2e1 | 2449 | |
71400594 RS |
2450 | static int |
2451 | nops_for_insn (const struct mips_cl_insn *history, | |
2452 | const struct mips_cl_insn *insn) | |
2453 | { | |
2454 | int i, nops, tmp_nops; | |
bdaaa2e1 | 2455 | |
71400594 | 2456 | nops = 0; |
7d8e00cf | 2457 | for (i = 0; i < MAX_DELAY_NOPS; i++) |
71400594 RS |
2458 | if (!history[i].noreorder_p) |
2459 | { | |
2460 | tmp_nops = insns_between (history + i, insn) - i; | |
2461 | if (tmp_nops > nops) | |
2462 | nops = tmp_nops; | |
2463 | } | |
7d8e00cf RS |
2464 | |
2465 | if (mips_fix_vr4130) | |
2466 | { | |
2467 | tmp_nops = nops_for_vr4130 (history, insn); | |
2468 | if (tmp_nops > nops) | |
2469 | nops = tmp_nops; | |
2470 | } | |
2471 | ||
71400594 RS |
2472 | return nops; |
2473 | } | |
252b5132 | 2474 | |
71400594 RS |
2475 | /* The variable arguments provide NUM_INSNS extra instructions that |
2476 | might be added to HISTORY. Return the largest number of nops that | |
2477 | would be needed after the extended sequence. */ | |
252b5132 | 2478 | |
71400594 RS |
2479 | static int |
2480 | nops_for_sequence (int num_insns, const struct mips_cl_insn *history, ...) | |
2481 | { | |
2482 | va_list args; | |
2483 | struct mips_cl_insn buffer[MAX_NOPS]; | |
2484 | struct mips_cl_insn *cursor; | |
2485 | int nops; | |
2486 | ||
2487 | va_start (args, history); | |
2488 | cursor = buffer + num_insns; | |
2489 | memcpy (cursor, history, (MAX_NOPS - num_insns) * sizeof (*cursor)); | |
2490 | while (cursor > buffer) | |
2491 | *--cursor = *va_arg (args, const struct mips_cl_insn *); | |
2492 | ||
2493 | nops = nops_for_insn (buffer, NULL); | |
2494 | va_end (args); | |
2495 | return nops; | |
2496 | } | |
252b5132 | 2497 | |
71400594 RS |
2498 | /* Like nops_for_insn, but if INSN is a branch, take into account the |
2499 | worst-case delay for the branch target. */ | |
252b5132 | 2500 | |
71400594 RS |
2501 | static int |
2502 | nops_for_insn_or_target (const struct mips_cl_insn *history, | |
2503 | const struct mips_cl_insn *insn) | |
2504 | { | |
2505 | int nops, tmp_nops; | |
60b63b72 | 2506 | |
71400594 RS |
2507 | nops = nops_for_insn (history, insn); |
2508 | if (insn->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY | |
2509 | | INSN_COND_BRANCH_DELAY | |
2510 | | INSN_COND_BRANCH_LIKELY)) | |
2511 | { | |
2512 | tmp_nops = nops_for_sequence (2, history, insn, NOP_INSN); | |
2513 | if (tmp_nops > nops) | |
2514 | nops = tmp_nops; | |
2515 | } | |
2516 | else if (mips_opts.mips16 && (insn->insn_mo->pinfo & MIPS16_INSN_BRANCH)) | |
2517 | { | |
2518 | tmp_nops = nops_for_sequence (1, history, insn); | |
2519 | if (tmp_nops > nops) | |
2520 | nops = tmp_nops; | |
2521 | } | |
2522 | return nops; | |
2523 | } | |
2524 | ||
2525 | /* Output an instruction. IP is the instruction information. | |
2526 | ADDRESS_EXPR is an operand of the instruction to be used with | |
2527 | RELOC_TYPE. */ | |
2528 | ||
2529 | static void | |
2530 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
2531 | bfd_reloc_code_real_type *reloc_type) | |
2532 | { | |
3994f87e | 2533 | unsigned long prev_pinfo, pinfo; |
71400594 RS |
2534 | relax_stateT prev_insn_frag_type = 0; |
2535 | bfd_boolean relaxed_branch = FALSE; | |
a8dbcb85 | 2536 | segment_info_type *si = seg_info (now_seg); |
71400594 RS |
2537 | |
2538 | /* Mark instruction labels in mips16 mode. */ | |
2539 | mips16_mark_labels (); | |
2540 | ||
2541 | prev_pinfo = history[0].insn_mo->pinfo; | |
2542 | pinfo = ip->insn_mo->pinfo; | |
2543 | ||
2544 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) | |
2545 | { | |
2546 | /* There are a lot of optimizations we could do that we don't. | |
2547 | In particular, we do not, in general, reorder instructions. | |
2548 | If you use gcc with optimization, it will reorder | |
2549 | instructions and generally do much more optimization then we | |
2550 | do here; repeating all that work in the assembler would only | |
2551 | benefit hand written assembly code, and does not seem worth | |
2552 | it. */ | |
2553 | int nops = (mips_optimize == 0 | |
2554 | ? nops_for_insn (history, NULL) | |
2555 | : nops_for_insn_or_target (history, ip)); | |
2556 | if (nops > 0) | |
252b5132 RH |
2557 | { |
2558 | fragS *old_frag; | |
2559 | unsigned long old_frag_offset; | |
2560 | int i; | |
252b5132 RH |
2561 | |
2562 | old_frag = frag_now; | |
2563 | old_frag_offset = frag_now_fix (); | |
2564 | ||
2565 | for (i = 0; i < nops; i++) | |
2566 | emit_nop (); | |
2567 | ||
2568 | if (listing) | |
2569 | { | |
2570 | listing_prev_line (); | |
2571 | /* We may be at the start of a variant frag. In case we | |
2572 | are, make sure there is enough space for the frag | |
2573 | after the frags created by listing_prev_line. The | |
2574 | argument to frag_grow here must be at least as large | |
2575 | as the argument to all other calls to frag_grow in | |
2576 | this file. We don't have to worry about being in the | |
2577 | middle of a variant frag, because the variants insert | |
2578 | all needed nop instructions themselves. */ | |
2579 | frag_grow (40); | |
2580 | } | |
2581 | ||
404a8071 | 2582 | mips_move_labels (); |
252b5132 RH |
2583 | |
2584 | #ifndef NO_ECOFF_DEBUGGING | |
2585 | if (ECOFF_DEBUGGING) | |
2586 | ecoff_fix_loc (old_frag, old_frag_offset); | |
2587 | #endif | |
2588 | } | |
71400594 RS |
2589 | } |
2590 | else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) | |
2591 | { | |
2592 | /* Work out how many nops in prev_nop_frag are needed by IP. */ | |
2593 | int nops = nops_for_insn_or_target (history, ip); | |
2594 | assert (nops <= prev_nop_frag_holds); | |
252b5132 | 2595 | |
71400594 RS |
2596 | /* Enforce NOPS as a minimum. */ |
2597 | if (nops > prev_nop_frag_required) | |
2598 | prev_nop_frag_required = nops; | |
252b5132 | 2599 | |
71400594 RS |
2600 | if (prev_nop_frag_holds == prev_nop_frag_required) |
2601 | { | |
2602 | /* Settle for the current number of nops. Update the history | |
2603 | accordingly (for the benefit of any future .set reorder code). */ | |
2604 | prev_nop_frag = NULL; | |
2605 | insert_into_history (prev_nop_frag_since, | |
2606 | prev_nop_frag_holds, NOP_INSN); | |
2607 | } | |
2608 | else | |
2609 | { | |
2610 | /* Allow this instruction to replace one of the nops that was | |
2611 | tentatively added to prev_nop_frag. */ | |
2612 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
2613 | prev_nop_frag_holds--; | |
2614 | prev_nop_frag_since++; | |
252b5132 RH |
2615 | } |
2616 | } | |
2617 | ||
58e2ea4d MR |
2618 | #ifdef OBJ_ELF |
2619 | /* The value passed to dwarf2_emit_insn is the distance between | |
2620 | the beginning of the current instruction and the address that | |
2621 | should be recorded in the debug tables. For MIPS16 debug info | |
2622 | we want to use ISA-encoded addresses, so we pass -1 for an | |
2623 | address higher by one than the current. */ | |
2624 | dwarf2_emit_insn (mips_opts.mips16 ? -1 : 0); | |
2625 | #endif | |
2626 | ||
895921c9 | 2627 | /* Record the frag type before frag_var. */ |
47e39b9d RS |
2628 | if (history[0].frag) |
2629 | prev_insn_frag_type = history[0].frag->fr_type; | |
895921c9 | 2630 | |
4d7206a2 | 2631 | if (address_expr |
0b25d3e6 | 2632 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
4a6a3df4 AO |
2633 | && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY |
2634 | || pinfo & INSN_COND_BRANCH_LIKELY) | |
2635 | && mips_relax_branch | |
2636 | /* Don't try branch relaxation within .set nomacro, or within | |
2637 | .set noat if we use $at for PIC computations. If it turns | |
2638 | out that the branch was out-of-range, we'll get an error. */ | |
2639 | && !mips_opts.warn_about_macros | |
2640 | && !(mips_opts.noat && mips_pic != NO_PIC) | |
2641 | && !mips_opts.mips16) | |
2642 | { | |
895921c9 | 2643 | relaxed_branch = TRUE; |
1e915849 RS |
2644 | add_relaxed_insn (ip, (relaxed_branch_length |
2645 | (NULL, NULL, | |
2646 | (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1 | |
2647 | : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 | |
2648 | : 0)), 4, | |
2649 | RELAX_BRANCH_ENCODE | |
2650 | (pinfo & INSN_UNCOND_BRANCH_DELAY, | |
2651 | pinfo & INSN_COND_BRANCH_LIKELY, | |
2652 | pinfo & INSN_WRITE_GPR_31, | |
2653 | 0), | |
2654 | address_expr->X_add_symbol, | |
2655 | address_expr->X_add_number); | |
4a6a3df4 AO |
2656 | *reloc_type = BFD_RELOC_UNUSED; |
2657 | } | |
2658 | else if (*reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
2659 | { |
2660 | /* We need to set up a variant frag. */ | |
2661 | assert (mips_opts.mips16 && address_expr != NULL); | |
1e915849 RS |
2662 | add_relaxed_insn (ip, 4, 0, |
2663 | RELAX_MIPS16_ENCODE | |
2664 | (*reloc_type - BFD_RELOC_UNUSED, | |
2665 | mips16_small, mips16_ext, | |
2666 | prev_pinfo & INSN_UNCOND_BRANCH_DELAY, | |
2667 | history[0].mips16_absolute_jump_p), | |
2668 | make_expr_symbol (address_expr), 0); | |
252b5132 | 2669 | } |
252b5132 RH |
2670 | else if (mips_opts.mips16 |
2671 | && ! ip->use_extend | |
f6688943 | 2672 | && *reloc_type != BFD_RELOC_MIPS16_JMP) |
9497f5ac | 2673 | { |
b8ee1a6e DU |
2674 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) == 0) |
2675 | /* Make sure there is enough room to swap this instruction with | |
2676 | a following jump instruction. */ | |
2677 | frag_grow (6); | |
1e915849 | 2678 | add_fixed_insn (ip); |
252b5132 RH |
2679 | } |
2680 | else | |
2681 | { | |
2682 | if (mips_opts.mips16 | |
2683 | && mips_opts.noreorder | |
2684 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
2685 | as_warn (_("extended instruction in delay slot")); | |
2686 | ||
4d7206a2 RS |
2687 | if (mips_relax.sequence) |
2688 | { | |
2689 | /* If we've reached the end of this frag, turn it into a variant | |
2690 | frag and record the information for the instructions we've | |
2691 | written so far. */ | |
2692 | if (frag_room () < 4) | |
2693 | relax_close_frag (); | |
2694 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
2695 | } | |
2696 | ||
584892a6 RS |
2697 | if (mips_relax.sequence != 2) |
2698 | mips_macro_warning.sizes[0] += 4; | |
2699 | if (mips_relax.sequence != 1) | |
2700 | mips_macro_warning.sizes[1] += 4; | |
2701 | ||
1e915849 RS |
2702 | if (mips_opts.mips16) |
2703 | { | |
2704 | ip->fixed_p = 1; | |
2705 | ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); | |
2706 | } | |
2707 | add_fixed_insn (ip); | |
252b5132 RH |
2708 | } |
2709 | ||
01a3f561 | 2710 | if (address_expr != NULL && *reloc_type <= BFD_RELOC_UNUSED) |
252b5132 RH |
2711 | { |
2712 | if (address_expr->X_op == O_constant) | |
2713 | { | |
f17c130b | 2714 | unsigned int tmp; |
f6688943 TS |
2715 | |
2716 | switch (*reloc_type) | |
252b5132 RH |
2717 | { |
2718 | case BFD_RELOC_32: | |
2719 | ip->insn_opcode |= address_expr->X_add_number; | |
2720 | break; | |
2721 | ||
f6688943 | 2722 | case BFD_RELOC_MIPS_HIGHEST: |
f17c130b AM |
2723 | tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48; |
2724 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2725 | break; |
2726 | ||
2727 | case BFD_RELOC_MIPS_HIGHER: | |
f17c130b AM |
2728 | tmp = (address_expr->X_add_number + 0x80008000ull) >> 32; |
2729 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2730 | break; |
2731 | ||
2732 | case BFD_RELOC_HI16_S: | |
f17c130b AM |
2733 | tmp = (address_expr->X_add_number + 0x8000) >> 16; |
2734 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2735 | break; |
2736 | ||
2737 | case BFD_RELOC_HI16: | |
2738 | ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; | |
2739 | break; | |
2740 | ||
01a3f561 | 2741 | case BFD_RELOC_UNUSED: |
252b5132 | 2742 | case BFD_RELOC_LO16: |
ed6fb7bd | 2743 | case BFD_RELOC_MIPS_GOT_DISP: |
252b5132 RH |
2744 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
2745 | break; | |
2746 | ||
2747 | case BFD_RELOC_MIPS_JMP: | |
2748 | if ((address_expr->X_add_number & 3) != 0) | |
2749 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2750 | (unsigned long) address_expr->X_add_number); | |
2751 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; | |
2752 | break; | |
2753 | ||
2754 | case BFD_RELOC_MIPS16_JMP: | |
2755 | if ((address_expr->X_add_number & 3) != 0) | |
2756 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2757 | (unsigned long) address_expr->X_add_number); | |
2758 | ip->insn_opcode |= | |
2759 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
2760 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
2761 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
2762 | break; | |
2763 | ||
252b5132 | 2764 | case BFD_RELOC_16_PCREL_S2: |
bad36eac DJ |
2765 | if ((address_expr->X_add_number & 3) != 0) |
2766 | as_bad (_("branch to misaligned address (0x%lx)"), | |
2767 | (unsigned long) address_expr->X_add_number); | |
2768 | if (mips_relax_branch) | |
2769 | goto need_reloc; | |
2770 | if ((address_expr->X_add_number + 0x20000) & ~0x3ffff) | |
2771 | as_bad (_("branch address range overflow (0x%lx)"), | |
2772 | (unsigned long) address_expr->X_add_number); | |
2773 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0xffff; | |
2774 | break; | |
252b5132 RH |
2775 | |
2776 | default: | |
2777 | internalError (); | |
2778 | } | |
2779 | } | |
01a3f561 | 2780 | else if (*reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 2781 | need_reloc: |
4d7206a2 RS |
2782 | { |
2783 | reloc_howto_type *howto; | |
2784 | int i; | |
34ce925e | 2785 | |
4d7206a2 RS |
2786 | /* In a compound relocation, it is the final (outermost) |
2787 | operator that determines the relocated field. */ | |
2788 | for (i = 1; i < 3; i++) | |
2789 | if (reloc_type[i] == BFD_RELOC_UNUSED) | |
2790 | break; | |
34ce925e | 2791 | |
4d7206a2 | 2792 | howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]); |
1e915849 RS |
2793 | ip->fixp[0] = fix_new_exp (ip->frag, ip->where, |
2794 | bfd_get_reloc_size (howto), | |
2795 | address_expr, | |
2796 | reloc_type[0] == BFD_RELOC_16_PCREL_S2, | |
2797 | reloc_type[0]); | |
4d7206a2 | 2798 | |
b314ec0e RS |
2799 | /* Tag symbols that have a R_MIPS16_26 relocation against them. */ |
2800 | if (reloc_type[0] == BFD_RELOC_MIPS16_JMP | |
2801 | && ip->fixp[0]->fx_addsy) | |
2802 | *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1; | |
2803 | ||
4d7206a2 RS |
2804 | /* These relocations can have an addend that won't fit in |
2805 | 4 octets for 64bit assembly. */ | |
2806 | if (HAVE_64BIT_GPRS | |
2807 | && ! howto->partial_inplace | |
2808 | && (reloc_type[0] == BFD_RELOC_16 | |
2809 | || reloc_type[0] == BFD_RELOC_32 | |
2810 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
2811 | || reloc_type[0] == BFD_RELOC_HI16_S | |
2812 | || reloc_type[0] == BFD_RELOC_LO16 | |
2813 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
2814 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
2815 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
2816 | || reloc_type[0] == BFD_RELOC_64 | |
2817 | || reloc_type[0] == BFD_RELOC_CTOR | |
2818 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
2819 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
2820 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
2821 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
2822 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
d6f16593 MR |
2823 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT |
2824 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
2825 | || reloc_type[0] == BFD_RELOC_MIPS16_HI16_S | |
2826 | || reloc_type[0] == BFD_RELOC_MIPS16_LO16)) | |
1e915849 | 2827 | ip->fixp[0]->fx_no_overflow = 1; |
4d7206a2 RS |
2828 | |
2829 | if (mips_relax.sequence) | |
2830 | { | |
2831 | if (mips_relax.first_fixup == 0) | |
1e915849 | 2832 | mips_relax.first_fixup = ip->fixp[0]; |
4d7206a2 RS |
2833 | } |
2834 | else if (reloc_needs_lo_p (*reloc_type)) | |
2835 | { | |
2836 | struct mips_hi_fixup *hi_fixup; | |
252b5132 | 2837 | |
4d7206a2 RS |
2838 | /* Reuse the last entry if it already has a matching %lo. */ |
2839 | hi_fixup = mips_hi_fixup_list; | |
2840 | if (hi_fixup == 0 | |
2841 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
2842 | { | |
2843 | hi_fixup = ((struct mips_hi_fixup *) | |
2844 | xmalloc (sizeof (struct mips_hi_fixup))); | |
2845 | hi_fixup->next = mips_hi_fixup_list; | |
2846 | mips_hi_fixup_list = hi_fixup; | |
252b5132 | 2847 | } |
1e915849 | 2848 | hi_fixup->fixp = ip->fixp[0]; |
4d7206a2 RS |
2849 | hi_fixup->seg = now_seg; |
2850 | } | |
f6688943 | 2851 | |
4d7206a2 RS |
2852 | /* Add fixups for the second and third relocations, if given. |
2853 | Note that the ABI allows the second relocation to be | |
2854 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
2855 | moment we only use RSS_UNDEF, but we could add support | |
2856 | for the others if it ever becomes necessary. */ | |
2857 | for (i = 1; i < 3; i++) | |
2858 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
2859 | { | |
1e915849 RS |
2860 | ip->fixp[i] = fix_new (ip->frag, ip->where, |
2861 | ip->fixp[0]->fx_size, NULL, 0, | |
2862 | FALSE, reloc_type[i]); | |
b1dca8ee RS |
2863 | |
2864 | /* Use fx_tcbit to mark compound relocs. */ | |
1e915849 RS |
2865 | ip->fixp[0]->fx_tcbit = 1; |
2866 | ip->fixp[i]->fx_tcbit = 1; | |
4d7206a2 | 2867 | } |
252b5132 RH |
2868 | } |
2869 | } | |
1e915849 | 2870 | install_insn (ip); |
252b5132 RH |
2871 | |
2872 | /* Update the register mask information. */ | |
2873 | if (! mips_opts.mips16) | |
2874 | { | |
2875 | if (pinfo & INSN_WRITE_GPR_D) | |
bf12938e | 2876 | mips_gprmask |= 1 << EXTRACT_OPERAND (RD, *ip); |
252b5132 | 2877 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) |
bf12938e | 2878 | mips_gprmask |= 1 << EXTRACT_OPERAND (RT, *ip); |
252b5132 | 2879 | if (pinfo & INSN_READ_GPR_S) |
bf12938e | 2880 | mips_gprmask |= 1 << EXTRACT_OPERAND (RS, *ip); |
252b5132 | 2881 | if (pinfo & INSN_WRITE_GPR_31) |
f9419b05 | 2882 | mips_gprmask |= 1 << RA; |
252b5132 | 2883 | if (pinfo & INSN_WRITE_FPR_D) |
bf12938e | 2884 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FD, *ip); |
252b5132 | 2885 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) |
bf12938e | 2886 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FS, *ip); |
252b5132 | 2887 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) |
bf12938e | 2888 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FT, *ip); |
252b5132 | 2889 | if ((pinfo & INSN_READ_FPR_R) != 0) |
bf12938e | 2890 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FR, *ip); |
252b5132 RH |
2891 | if (pinfo & INSN_COP) |
2892 | { | |
bdaaa2e1 KH |
2893 | /* We don't keep enough information to sort these cases out. |
2894 | The itbl support does keep this information however, although | |
2895 | we currently don't support itbl fprmats as part of the cop | |
2896 | instruction. May want to add this support in the future. */ | |
252b5132 RH |
2897 | } |
2898 | /* Never set the bit for $0, which is always zero. */ | |
beae10d5 | 2899 | mips_gprmask &= ~1 << 0; |
252b5132 RH |
2900 | } |
2901 | else | |
2902 | { | |
2903 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) | |
bf12938e | 2904 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RX, *ip); |
252b5132 | 2905 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) |
bf12938e | 2906 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RY, *ip); |
252b5132 | 2907 | if (pinfo & MIPS16_INSN_WRITE_Z) |
bf12938e | 2908 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RZ, *ip); |
252b5132 RH |
2909 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) |
2910 | mips_gprmask |= 1 << TREG; | |
2911 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
2912 | mips_gprmask |= 1 << SP; | |
2913 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
2914 | mips_gprmask |= 1 << RA; | |
2915 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2916 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
2917 | if (pinfo & MIPS16_INSN_READ_Z) | |
bf12938e | 2918 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip); |
252b5132 | 2919 | if (pinfo & MIPS16_INSN_READ_GPR_X) |
bf12938e | 2920 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip); |
252b5132 RH |
2921 | } |
2922 | ||
4d7206a2 | 2923 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
252b5132 RH |
2924 | { |
2925 | /* Filling the branch delay slot is more complex. We try to | |
2926 | switch the branch with the previous instruction, which we can | |
2927 | do if the previous instruction does not set up a condition | |
2928 | that the branch tests and if the branch is not itself the | |
2929 | target of any branch. */ | |
2930 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2931 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
2932 | { | |
2933 | if (mips_optimize < 2 | |
2934 | /* If we have seen .set volatile or .set nomove, don't | |
2935 | optimize. */ | |
2936 | || mips_opts.nomove != 0 | |
a38419a5 RS |
2937 | /* We can't swap if the previous instruction's position |
2938 | is fixed. */ | |
2939 | || history[0].fixed_p | |
252b5132 RH |
2940 | /* If the previous previous insn was in a .set |
2941 | noreorder, we can't swap. Actually, the MIPS | |
2942 | assembler will swap in this situation. However, gcc | |
2943 | configured -with-gnu-as will generate code like | |
2944 | .set noreorder | |
2945 | lw $4,XXX | |
2946 | .set reorder | |
2947 | INSN | |
2948 | bne $4,$0,foo | |
2949 | in which we can not swap the bne and INSN. If gcc is | |
2950 | not configured -with-gnu-as, it does not output the | |
a38419a5 | 2951 | .set pseudo-ops. */ |
47e39b9d | 2952 | || history[1].noreorder_p |
252b5132 RH |
2953 | /* If the branch is itself the target of a branch, we |
2954 | can not swap. We cheat on this; all we check for is | |
2955 | whether there is a label on this instruction. If | |
2956 | there are any branches to anything other than a | |
2957 | label, users must use .set noreorder. */ | |
a8dbcb85 | 2958 | || si->label_list != NULL |
895921c9 MR |
2959 | /* If the previous instruction is in a variant frag |
2960 | other than this branch's one, we cannot do the swap. | |
2961 | This does not apply to the mips16, which uses variant | |
2962 | frags for different purposes. */ | |
252b5132 | 2963 | || (! mips_opts.mips16 |
895921c9 | 2964 | && prev_insn_frag_type == rs_machine_dependent) |
71400594 RS |
2965 | /* Check for conflicts between the branch and the instructions |
2966 | before the candidate delay slot. */ | |
2967 | || nops_for_insn (history + 1, ip) > 0 | |
2968 | /* Check for conflicts between the swapped sequence and the | |
2969 | target of the branch. */ | |
2970 | || nops_for_sequence (2, history + 1, ip, history) > 0 | |
252b5132 RH |
2971 | /* We do not swap with a trap instruction, since it |
2972 | complicates trap handlers to have the trap | |
2973 | instruction be in a delay slot. */ | |
2974 | || (prev_pinfo & INSN_TRAP) | |
2975 | /* If the branch reads a register that the previous | |
2976 | instruction sets, we can not swap. */ | |
2977 | || (! mips_opts.mips16 | |
2978 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
bf12938e | 2979 | && insn_uses_reg (ip, EXTRACT_OPERAND (RT, history[0]), |
252b5132 RH |
2980 | MIPS_GR_REG)) |
2981 | || (! mips_opts.mips16 | |
2982 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
bf12938e | 2983 | && insn_uses_reg (ip, EXTRACT_OPERAND (RD, history[0]), |
252b5132 RH |
2984 | MIPS_GR_REG)) |
2985 | || (mips_opts.mips16 | |
2986 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
bf12938e RS |
2987 | && (insn_uses_reg |
2988 | (ip, MIPS16_EXTRACT_OPERAND (RX, history[0]), | |
2989 | MIPS16_REG))) | |
252b5132 | 2990 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) |
bf12938e RS |
2991 | && (insn_uses_reg |
2992 | (ip, MIPS16_EXTRACT_OPERAND (RY, history[0]), | |
2993 | MIPS16_REG))) | |
252b5132 | 2994 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) |
bf12938e RS |
2995 | && (insn_uses_reg |
2996 | (ip, MIPS16_EXTRACT_OPERAND (RZ, history[0]), | |
2997 | MIPS16_REG))) | |
252b5132 RH |
2998 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) |
2999 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
3000 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
3001 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
3002 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
3003 | && insn_uses_reg (ip, | |
47e39b9d RS |
3004 | MIPS16OP_EXTRACT_REG32R |
3005 | (history[0].insn_opcode), | |
252b5132 RH |
3006 | MIPS_GR_REG)))) |
3007 | /* If the branch writes a register that the previous | |
3008 | instruction sets, we can not swap (we know that | |
3009 | branches write only to RD or to $31). */ | |
3010 | || (! mips_opts.mips16 | |
3011 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
3012 | && (((pinfo & INSN_WRITE_GPR_D) | |
bf12938e RS |
3013 | && (EXTRACT_OPERAND (RT, history[0]) |
3014 | == EXTRACT_OPERAND (RD, *ip))) | |
252b5132 | 3015 | || ((pinfo & INSN_WRITE_GPR_31) |
bf12938e | 3016 | && EXTRACT_OPERAND (RT, history[0]) == RA))) |
252b5132 RH |
3017 | || (! mips_opts.mips16 |
3018 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
3019 | && (((pinfo & INSN_WRITE_GPR_D) | |
bf12938e RS |
3020 | && (EXTRACT_OPERAND (RD, history[0]) |
3021 | == EXTRACT_OPERAND (RD, *ip))) | |
252b5132 | 3022 | || ((pinfo & INSN_WRITE_GPR_31) |
bf12938e | 3023 | && EXTRACT_OPERAND (RD, history[0]) == RA))) |
252b5132 RH |
3024 | || (mips_opts.mips16 |
3025 | && (pinfo & MIPS16_INSN_WRITE_31) | |
3026 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
3027 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
47e39b9d | 3028 | && (MIPS16OP_EXTRACT_REG32R (history[0].insn_opcode) |
252b5132 RH |
3029 | == RA)))) |
3030 | /* If the branch writes a register that the previous | |
3031 | instruction reads, we can not swap (we know that | |
3032 | branches only write to RD or to $31). */ | |
3033 | || (! mips_opts.mips16 | |
3034 | && (pinfo & INSN_WRITE_GPR_D) | |
47e39b9d | 3035 | && insn_uses_reg (&history[0], |
bf12938e | 3036 | EXTRACT_OPERAND (RD, *ip), |
252b5132 RH |
3037 | MIPS_GR_REG)) |
3038 | || (! mips_opts.mips16 | |
3039 | && (pinfo & INSN_WRITE_GPR_31) | |
47e39b9d | 3040 | && insn_uses_reg (&history[0], RA, MIPS_GR_REG)) |
252b5132 RH |
3041 | || (mips_opts.mips16 |
3042 | && (pinfo & MIPS16_INSN_WRITE_31) | |
47e39b9d | 3043 | && insn_uses_reg (&history[0], RA, MIPS_GR_REG)) |
252b5132 RH |
3044 | /* If one instruction sets a condition code and the |
3045 | other one uses a condition code, we can not swap. */ | |
3046 | || ((pinfo & INSN_READ_COND_CODE) | |
3047 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
3048 | || ((pinfo & INSN_WRITE_COND_CODE) | |
3049 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
3050 | /* If the previous instruction uses the PC, we can not | |
3051 | swap. */ | |
3052 | || (mips_opts.mips16 | |
3053 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
252b5132 RH |
3054 | /* If the previous instruction had a fixup in mips16 |
3055 | mode, we can not swap. This normally means that the | |
3056 | previous instruction was a 4 byte branch anyhow. */ | |
47e39b9d | 3057 | || (mips_opts.mips16 && history[0].fixp[0]) |
bdaaa2e1 KH |
3058 | /* If the previous instruction is a sync, sync.l, or |
3059 | sync.p, we can not swap. */ | |
f173e82e | 3060 | || (prev_pinfo & INSN_SYNC)) |
252b5132 | 3061 | { |
29024861 DU |
3062 | if (mips_opts.mips16 |
3063 | && (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
3064 | && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31)) | |
3994f87e | 3065 | && ISA_SUPPORTS_MIPS16E) |
29024861 DU |
3066 | { |
3067 | /* Convert MIPS16 jr/jalr into a "compact" jump. */ | |
3068 | ip->insn_opcode |= 0x0080; | |
3069 | install_insn (ip); | |
3070 | insert_into_history (0, 1, ip); | |
3071 | } | |
3072 | else | |
3073 | { | |
3074 | /* We could do even better for unconditional branches to | |
3075 | portions of this object file; we could pick up the | |
3076 | instruction at the destination, put it in the delay | |
3077 | slot, and bump the destination address. */ | |
3078 | insert_into_history (0, 1, ip); | |
3079 | emit_nop (); | |
3080 | } | |
3081 | ||
dd22970f ILT |
3082 | if (mips_relax.sequence) |
3083 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
252b5132 RH |
3084 | } |
3085 | else | |
3086 | { | |
3087 | /* It looks like we can actually do the swap. */ | |
1e915849 RS |
3088 | struct mips_cl_insn delay = history[0]; |
3089 | if (mips_opts.mips16) | |
252b5132 | 3090 | { |
b8ee1a6e DU |
3091 | know (delay.frag == ip->frag); |
3092 | move_insn (ip, delay.frag, delay.where); | |
3093 | move_insn (&delay, ip->frag, ip->where + insn_length (ip)); | |
1e915849 RS |
3094 | } |
3095 | else if (relaxed_branch) | |
3096 | { | |
3097 | /* Add the delay slot instruction to the end of the | |
3098 | current frag and shrink the fixed part of the | |
3099 | original frag. If the branch occupies the tail of | |
3100 | the latter, move it backwards to cover the gap. */ | |
3101 | delay.frag->fr_fix -= 4; | |
3102 | if (delay.frag == ip->frag) | |
3103 | move_insn (ip, ip->frag, ip->where - 4); | |
3104 | add_fixed_insn (&delay); | |
252b5132 RH |
3105 | } |
3106 | else | |
3107 | { | |
1e915849 RS |
3108 | move_insn (&delay, ip->frag, ip->where); |
3109 | move_insn (ip, history[0].frag, history[0].where); | |
252b5132 | 3110 | } |
1e915849 RS |
3111 | history[0] = *ip; |
3112 | delay.fixed_p = 1; | |
3113 | insert_into_history (0, 1, &delay); | |
252b5132 | 3114 | } |
252b5132 RH |
3115 | |
3116 | /* If that was an unconditional branch, forget the previous | |
3117 | insn information. */ | |
3118 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
7d10b47d | 3119 | mips_no_prev_insn (); |
252b5132 RH |
3120 | } |
3121 | else if (pinfo & INSN_COND_BRANCH_LIKELY) | |
3122 | { | |
3123 | /* We don't yet optimize a branch likely. What we should do | |
3124 | is look at the target, copy the instruction found there | |
3125 | into the delay slot, and increment the branch to jump to | |
3126 | the next instruction. */ | |
1e915849 | 3127 | insert_into_history (0, 1, ip); |
252b5132 | 3128 | emit_nop (); |
252b5132 RH |
3129 | } |
3130 | else | |
1e915849 | 3131 | insert_into_history (0, 1, ip); |
252b5132 | 3132 | } |
1e915849 RS |
3133 | else |
3134 | insert_into_history (0, 1, ip); | |
252b5132 RH |
3135 | |
3136 | /* We just output an insn, so the next one doesn't have a label. */ | |
3137 | mips_clear_insn_labels (); | |
252b5132 RH |
3138 | } |
3139 | ||
7d10b47d | 3140 | /* Forget that there was any previous instruction or label. */ |
252b5132 RH |
3141 | |
3142 | static void | |
7d10b47d | 3143 | mips_no_prev_insn (void) |
252b5132 | 3144 | { |
7d10b47d RS |
3145 | prev_nop_frag = NULL; |
3146 | insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); | |
252b5132 RH |
3147 | mips_clear_insn_labels (); |
3148 | } | |
3149 | ||
7d10b47d RS |
3150 | /* This function must be called before we emit something other than |
3151 | instructions. It is like mips_no_prev_insn except that it inserts | |
3152 | any NOPS that might be needed by previous instructions. */ | |
252b5132 | 3153 | |
7d10b47d RS |
3154 | void |
3155 | mips_emit_delays (void) | |
252b5132 RH |
3156 | { |
3157 | if (! mips_opts.noreorder) | |
3158 | { | |
71400594 | 3159 | int nops = nops_for_insn (history, NULL); |
252b5132 RH |
3160 | if (nops > 0) |
3161 | { | |
7d10b47d RS |
3162 | while (nops-- > 0) |
3163 | add_fixed_insn (NOP_INSN); | |
3164 | mips_move_labels (); | |
3165 | } | |
3166 | } | |
3167 | mips_no_prev_insn (); | |
3168 | } | |
3169 | ||
3170 | /* Start a (possibly nested) noreorder block. */ | |
3171 | ||
3172 | static void | |
3173 | start_noreorder (void) | |
3174 | { | |
3175 | if (mips_opts.noreorder == 0) | |
3176 | { | |
3177 | unsigned int i; | |
3178 | int nops; | |
3179 | ||
3180 | /* None of the instructions before the .set noreorder can be moved. */ | |
3181 | for (i = 0; i < ARRAY_SIZE (history); i++) | |
3182 | history[i].fixed_p = 1; | |
3183 | ||
3184 | /* Insert any nops that might be needed between the .set noreorder | |
3185 | block and the previous instructions. We will later remove any | |
3186 | nops that turn out not to be needed. */ | |
3187 | nops = nops_for_insn (history, NULL); | |
3188 | if (nops > 0) | |
3189 | { | |
3190 | if (mips_optimize != 0) | |
252b5132 RH |
3191 | { |
3192 | /* Record the frag which holds the nop instructions, so | |
3193 | that we can remove them if we don't need them. */ | |
3194 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); | |
3195 | prev_nop_frag = frag_now; | |
3196 | prev_nop_frag_holds = nops; | |
3197 | prev_nop_frag_required = 0; | |
3198 | prev_nop_frag_since = 0; | |
3199 | } | |
3200 | ||
3201 | for (; nops > 0; --nops) | |
1e915849 | 3202 | add_fixed_insn (NOP_INSN); |
252b5132 | 3203 | |
7d10b47d RS |
3204 | /* Move on to a new frag, so that it is safe to simply |
3205 | decrease the size of prev_nop_frag. */ | |
3206 | frag_wane (frag_now); | |
3207 | frag_new (0); | |
404a8071 | 3208 | mips_move_labels (); |
252b5132 | 3209 | } |
7d10b47d RS |
3210 | mips16_mark_labels (); |
3211 | mips_clear_insn_labels (); | |
252b5132 | 3212 | } |
7d10b47d RS |
3213 | mips_opts.noreorder++; |
3214 | mips_any_noreorder = 1; | |
3215 | } | |
252b5132 | 3216 | |
7d10b47d | 3217 | /* End a nested noreorder block. */ |
252b5132 | 3218 | |
7d10b47d RS |
3219 | static void |
3220 | end_noreorder (void) | |
3221 | { | |
3222 | mips_opts.noreorder--; | |
3223 | if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) | |
3224 | { | |
3225 | /* Commit to inserting prev_nop_frag_required nops and go back to | |
3226 | handling nop insertion the .set reorder way. */ | |
3227 | prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) | |
3228 | * (mips_opts.mips16 ? 2 : 4)); | |
3229 | insert_into_history (prev_nop_frag_since, | |
3230 | prev_nop_frag_required, NOP_INSN); | |
3231 | prev_nop_frag = NULL; | |
3232 | } | |
252b5132 RH |
3233 | } |
3234 | ||
584892a6 RS |
3235 | /* Set up global variables for the start of a new macro. */ |
3236 | ||
3237 | static void | |
3238 | macro_start (void) | |
3239 | { | |
3240 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
3241 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder | |
47e39b9d | 3242 | && (history[0].insn_mo->pinfo |
584892a6 RS |
3243 | & (INSN_UNCOND_BRANCH_DELAY |
3244 | | INSN_COND_BRANCH_DELAY | |
3245 | | INSN_COND_BRANCH_LIKELY)) != 0); | |
3246 | } | |
3247 | ||
3248 | /* Given that a macro is longer than 4 bytes, return the appropriate warning | |
3249 | for it. Return null if no warning is needed. SUBTYPE is a bitmask of | |
3250 | RELAX_DELAY_SLOT and RELAX_NOMACRO. */ | |
3251 | ||
3252 | static const char * | |
3253 | macro_warning (relax_substateT subtype) | |
3254 | { | |
3255 | if (subtype & RELAX_DELAY_SLOT) | |
3256 | return _("Macro instruction expanded into multiple instructions" | |
3257 | " in a branch delay slot"); | |
3258 | else if (subtype & RELAX_NOMACRO) | |
3259 | return _("Macro instruction expanded into multiple instructions"); | |
3260 | else | |
3261 | return 0; | |
3262 | } | |
3263 | ||
3264 | /* Finish up a macro. Emit warnings as appropriate. */ | |
3265 | ||
3266 | static void | |
3267 | macro_end (void) | |
3268 | { | |
3269 | if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4) | |
3270 | { | |
3271 | relax_substateT subtype; | |
3272 | ||
3273 | /* Set up the relaxation warning flags. */ | |
3274 | subtype = 0; | |
3275 | if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0]) | |
3276 | subtype |= RELAX_SECOND_LONGER; | |
3277 | if (mips_opts.warn_about_macros) | |
3278 | subtype |= RELAX_NOMACRO; | |
3279 | if (mips_macro_warning.delay_slot_p) | |
3280 | subtype |= RELAX_DELAY_SLOT; | |
3281 | ||
3282 | if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4) | |
3283 | { | |
3284 | /* Either the macro has a single implementation or both | |
3285 | implementations are longer than 4 bytes. Emit the | |
3286 | warning now. */ | |
3287 | const char *msg = macro_warning (subtype); | |
3288 | if (msg != 0) | |
3289 | as_warn (msg); | |
3290 | } | |
3291 | else | |
3292 | { | |
3293 | /* One implementation might need a warning but the other | |
3294 | definitely doesn't. */ | |
3295 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
3296 | } | |
3297 | } | |
3298 | } | |
3299 | ||
6e1304d8 RS |
3300 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
3301 | The first argument in *ARGS will be either the code for a single | |
3302 | relocation or -1 followed by the three codes that make up a | |
3303 | composite relocation. */ | |
3304 | ||
3305 | static void | |
3306 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
3307 | { | |
3308 | int i, next; | |
3309 | ||
3310 | next = va_arg (*args, int); | |
3311 | if (next >= 0) | |
3312 | r[0] = (bfd_reloc_code_real_type) next; | |
3313 | else | |
3314 | for (i = 0; i < 3; i++) | |
3315 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
3316 | } | |
3317 | ||
252b5132 RH |
3318 | /* Build an instruction created by a macro expansion. This is passed |
3319 | a pointer to the count of instructions created so far, an | |
3320 | expression, the name of the instruction to build, an operand format | |
3321 | string, and corresponding arguments. */ | |
3322 | ||
252b5132 | 3323 | static void |
67c0d1eb | 3324 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 | 3325 | { |
1e915849 | 3326 | const struct mips_opcode *mo; |
252b5132 | 3327 | struct mips_cl_insn insn; |
f6688943 | 3328 | bfd_reloc_code_real_type r[3]; |
252b5132 | 3329 | va_list args; |
252b5132 | 3330 | |
252b5132 | 3331 | va_start (args, fmt); |
252b5132 | 3332 | |
252b5132 RH |
3333 | if (mips_opts.mips16) |
3334 | { | |
67c0d1eb | 3335 | mips16_macro_build (ep, name, fmt, args); |
252b5132 RH |
3336 | va_end (args); |
3337 | return; | |
3338 | } | |
3339 | ||
f6688943 TS |
3340 | r[0] = BFD_RELOC_UNUSED; |
3341 | r[1] = BFD_RELOC_UNUSED; | |
3342 | r[2] = BFD_RELOC_UNUSED; | |
1e915849 RS |
3343 | mo = (struct mips_opcode *) hash_find (op_hash, name); |
3344 | assert (mo); | |
3345 | assert (strcmp (name, mo->name) == 0); | |
3346 | ||
8b082fb1 TS |
3347 | while (1) |
3348 | { | |
3349 | /* Search until we get a match for NAME. It is assumed here that | |
3350 | macros will never generate MDMX, MIPS-3D, or MT instructions. */ | |
3351 | if (strcmp (fmt, mo->args) == 0 | |
3352 | && mo->pinfo != INSN_MACRO | |
3353 | && OPCODE_IS_MEMBER (mo, | |
1e915849 | 3354 | (mips_opts.isa |
9b3f89ee | 3355 | | (mips_opts.mips16 ? INSN_MIPS16 : 0) |
8b082fb1 TS |
3356 | | (mips_opts.ase_dsp ? INSN_DSP : 0) |
3357 | | ((mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE) | |
3358 | ? INSN_DSP64 : 0) | |
3359 | | (mips_opts.ase_dspr2 ? INSN_DSPR2 : 0) | |
e16bfa71 | 3360 | | (mips_opts.ase_smartmips ? INSN_SMARTMIPS : 0)), |
fef14a42 | 3361 | mips_opts.arch) |
8b082fb1 TS |
3362 | && (mips_opts.arch != CPU_R4650 || (mo->pinfo & FP_D) == 0)) |
3363 | break; | |
3364 | ||
1e915849 RS |
3365 | ++mo; |
3366 | assert (mo->name); | |
3367 | assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
3368 | } |
3369 | ||
1e915849 | 3370 | create_insn (&insn, mo); |
252b5132 RH |
3371 | for (;;) |
3372 | { | |
3373 | switch (*fmt++) | |
3374 | { | |
3375 | case '\0': | |
3376 | break; | |
3377 | ||
3378 | case ',': | |
3379 | case '(': | |
3380 | case ')': | |
3381 | continue; | |
3382 | ||
5f74bc13 CD |
3383 | case '+': |
3384 | switch (*fmt++) | |
3385 | { | |
3386 | case 'A': | |
3387 | case 'E': | |
bf12938e | 3388 | INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); |
5f74bc13 CD |
3389 | continue; |
3390 | ||
3391 | case 'B': | |
3392 | case 'F': | |
3393 | /* Note that in the macro case, these arguments are already | |
3394 | in MSB form. (When handling the instruction in the | |
3395 | non-macro case, these arguments are sizes from which | |
3396 | MSB values must be calculated.) */ | |
bf12938e | 3397 | INSERT_OPERAND (INSMSB, insn, va_arg (args, int)); |
5f74bc13 CD |
3398 | continue; |
3399 | ||
3400 | case 'C': | |
3401 | case 'G': | |
3402 | case 'H': | |
3403 | /* Note that in the macro case, these arguments are already | |
3404 | in MSBD form. (When handling the instruction in the | |
3405 | non-macro case, these arguments are sizes from which | |
3406 | MSBD values must be calculated.) */ | |
bf12938e | 3407 | INSERT_OPERAND (EXTMSBD, insn, va_arg (args, int)); |
5f74bc13 CD |
3408 | continue; |
3409 | ||
3410 | default: | |
3411 | internalError (); | |
3412 | } | |
3413 | continue; | |
3414 | ||
8b082fb1 TS |
3415 | case '2': |
3416 | INSERT_OPERAND (BP, insn, va_arg (args, int)); | |
3417 | continue; | |
3418 | ||
252b5132 RH |
3419 | case 't': |
3420 | case 'w': | |
3421 | case 'E': | |
bf12938e | 3422 | INSERT_OPERAND (RT, insn, va_arg (args, int)); |
252b5132 RH |
3423 | continue; |
3424 | ||
3425 | case 'c': | |
bf12938e | 3426 | INSERT_OPERAND (CODE, insn, va_arg (args, int)); |
38487616 TS |
3427 | continue; |
3428 | ||
252b5132 RH |
3429 | case 'T': |
3430 | case 'W': | |
bf12938e | 3431 | INSERT_OPERAND (FT, insn, va_arg (args, int)); |
252b5132 RH |
3432 | continue; |
3433 | ||
3434 | case 'd': | |
3435 | case 'G': | |
af7ee8bf | 3436 | case 'K': |
bf12938e | 3437 | INSERT_OPERAND (RD, insn, va_arg (args, int)); |
252b5132 RH |
3438 | continue; |
3439 | ||
4372b673 NC |
3440 | case 'U': |
3441 | { | |
3442 | int tmp = va_arg (args, int); | |
3443 | ||
bf12938e RS |
3444 | INSERT_OPERAND (RT, insn, tmp); |
3445 | INSERT_OPERAND (RD, insn, tmp); | |
beae10d5 | 3446 | continue; |
4372b673 NC |
3447 | } |
3448 | ||
252b5132 RH |
3449 | case 'V': |
3450 | case 'S': | |
bf12938e | 3451 | INSERT_OPERAND (FS, insn, va_arg (args, int)); |
252b5132 RH |
3452 | continue; |
3453 | ||
3454 | case 'z': | |
3455 | continue; | |
3456 | ||
3457 | case '<': | |
bf12938e | 3458 | INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); |
252b5132 RH |
3459 | continue; |
3460 | ||
3461 | case 'D': | |
bf12938e | 3462 | INSERT_OPERAND (FD, insn, va_arg (args, int)); |
252b5132 RH |
3463 | continue; |
3464 | ||
3465 | case 'B': | |
bf12938e | 3466 | INSERT_OPERAND (CODE20, insn, va_arg (args, int)); |
252b5132 RH |
3467 | continue; |
3468 | ||
4372b673 | 3469 | case 'J': |
bf12938e | 3470 | INSERT_OPERAND (CODE19, insn, va_arg (args, int)); |
4372b673 NC |
3471 | continue; |
3472 | ||
252b5132 | 3473 | case 'q': |
bf12938e | 3474 | INSERT_OPERAND (CODE2, insn, va_arg (args, int)); |
252b5132 RH |
3475 | continue; |
3476 | ||
3477 | case 'b': | |
3478 | case 's': | |
3479 | case 'r': | |
3480 | case 'v': | |
bf12938e | 3481 | INSERT_OPERAND (RS, insn, va_arg (args, int)); |
252b5132 RH |
3482 | continue; |
3483 | ||
3484 | case 'i': | |
3485 | case 'j': | |
3486 | case 'o': | |
6e1304d8 | 3487 | macro_read_relocs (&args, r); |
cdf6fd85 | 3488 | assert (*r == BFD_RELOC_GPREL16 |
f6688943 TS |
3489 | || *r == BFD_RELOC_MIPS_LITERAL |
3490 | || *r == BFD_RELOC_MIPS_HIGHER | |
3491 | || *r == BFD_RELOC_HI16_S | |
3492 | || *r == BFD_RELOC_LO16 | |
3493 | || *r == BFD_RELOC_MIPS_GOT16 | |
3494 | || *r == BFD_RELOC_MIPS_CALL16 | |
438c16b8 TS |
3495 | || *r == BFD_RELOC_MIPS_GOT_DISP |
3496 | || *r == BFD_RELOC_MIPS_GOT_PAGE | |
3497 | || *r == BFD_RELOC_MIPS_GOT_OFST | |
f6688943 | 3498 | || *r == BFD_RELOC_MIPS_GOT_LO16 |
3e722fb5 | 3499 | || *r == BFD_RELOC_MIPS_CALL_LO16); |
252b5132 RH |
3500 | continue; |
3501 | ||
3502 | case 'u': | |
6e1304d8 | 3503 | macro_read_relocs (&args, r); |
252b5132 RH |
3504 | assert (ep != NULL |
3505 | && (ep->X_op == O_constant | |
3506 | || (ep->X_op == O_symbol | |
f6688943 TS |
3507 | && (*r == BFD_RELOC_MIPS_HIGHEST |
3508 | || *r == BFD_RELOC_HI16_S | |
3509 | || *r == BFD_RELOC_HI16 | |
3510 | || *r == BFD_RELOC_GPREL16 | |
3511 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
3e722fb5 | 3512 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); |
252b5132 RH |
3513 | continue; |
3514 | ||
3515 | case 'p': | |
3516 | assert (ep != NULL); | |
bad36eac | 3517 | |
252b5132 RH |
3518 | /* |
3519 | * This allows macro() to pass an immediate expression for | |
3520 | * creating short branches without creating a symbol. | |
bad36eac DJ |
3521 | * |
3522 | * We don't allow branch relaxation for these branches, as | |
3523 | * they should only appear in ".set nomacro" anyway. | |
252b5132 RH |
3524 | */ |
3525 | if (ep->X_op == O_constant) | |
3526 | { | |
bad36eac DJ |
3527 | if ((ep->X_add_number & 3) != 0) |
3528 | as_bad (_("branch to misaligned address (0x%lx)"), | |
3529 | (unsigned long) ep->X_add_number); | |
3530 | if ((ep->X_add_number + 0x20000) & ~0x3ffff) | |
3531 | as_bad (_("branch address range overflow (0x%lx)"), | |
3532 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
3533 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; |
3534 | ep = NULL; | |
3535 | } | |
3536 | else | |
0b25d3e6 | 3537 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
3538 | continue; |
3539 | ||
3540 | case 'a': | |
3541 | assert (ep != NULL); | |
f6688943 | 3542 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
3543 | continue; |
3544 | ||
3545 | case 'C': | |
a9e24354 | 3546 | INSERT_OPERAND (COPZ, insn, va_arg (args, unsigned long)); |
252b5132 RH |
3547 | continue; |
3548 | ||
d43b4baf | 3549 | case 'k': |
a9e24354 | 3550 | INSERT_OPERAND (CACHE, insn, va_arg (args, unsigned long)); |
d43b4baf TS |
3551 | continue; |
3552 | ||
252b5132 RH |
3553 | default: |
3554 | internalError (); | |
3555 | } | |
3556 | break; | |
3557 | } | |
3558 | va_end (args); | |
f6688943 | 3559 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3560 | |
4d7206a2 | 3561 | append_insn (&insn, ep, r); |
252b5132 RH |
3562 | } |
3563 | ||
3564 | static void | |
67c0d1eb | 3565 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
17a2f251 | 3566 | va_list args) |
252b5132 | 3567 | { |
1e915849 | 3568 | struct mips_opcode *mo; |
252b5132 | 3569 | struct mips_cl_insn insn; |
f6688943 TS |
3570 | bfd_reloc_code_real_type r[3] |
3571 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 3572 | |
1e915849 RS |
3573 | mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
3574 | assert (mo); | |
3575 | assert (strcmp (name, mo->name) == 0); | |
252b5132 | 3576 | |
1e915849 | 3577 | while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) |
252b5132 | 3578 | { |
1e915849 RS |
3579 | ++mo; |
3580 | assert (mo->name); | |
3581 | assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
3582 | } |
3583 | ||
1e915849 | 3584 | create_insn (&insn, mo); |
252b5132 RH |
3585 | for (;;) |
3586 | { | |
3587 | int c; | |
3588 | ||
3589 | c = *fmt++; | |
3590 | switch (c) | |
3591 | { | |
3592 | case '\0': | |
3593 | break; | |
3594 | ||
3595 | case ',': | |
3596 | case '(': | |
3597 | case ')': | |
3598 | continue; | |
3599 | ||
3600 | case 'y': | |
3601 | case 'w': | |
bf12938e | 3602 | MIPS16_INSERT_OPERAND (RY, insn, va_arg (args, int)); |
252b5132 RH |
3603 | continue; |
3604 | ||
3605 | case 'x': | |
3606 | case 'v': | |
bf12938e | 3607 | MIPS16_INSERT_OPERAND (RX, insn, va_arg (args, int)); |
252b5132 RH |
3608 | continue; |
3609 | ||
3610 | case 'z': | |
bf12938e | 3611 | MIPS16_INSERT_OPERAND (RZ, insn, va_arg (args, int)); |
252b5132 RH |
3612 | continue; |
3613 | ||
3614 | case 'Z': | |
bf12938e | 3615 | MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (args, int)); |
252b5132 RH |
3616 | continue; |
3617 | ||
3618 | case '0': | |
3619 | case 'S': | |
3620 | case 'P': | |
3621 | case 'R': | |
3622 | continue; | |
3623 | ||
3624 | case 'X': | |
bf12938e | 3625 | MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (args, int)); |
252b5132 RH |
3626 | continue; |
3627 | ||
3628 | case 'Y': | |
3629 | { | |
3630 | int regno; | |
3631 | ||
3632 | regno = va_arg (args, int); | |
3633 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
a9e24354 | 3634 | MIPS16_INSERT_OPERAND (REG32R, insn, regno); |
252b5132 RH |
3635 | } |
3636 | continue; | |
3637 | ||
3638 | case '<': | |
3639 | case '>': | |
3640 | case '4': | |
3641 | case '5': | |
3642 | case 'H': | |
3643 | case 'W': | |
3644 | case 'D': | |
3645 | case 'j': | |
3646 | case '8': | |
3647 | case 'V': | |
3648 | case 'C': | |
3649 | case 'U': | |
3650 | case 'k': | |
3651 | case 'K': | |
3652 | case 'p': | |
3653 | case 'q': | |
3654 | { | |
3655 | assert (ep != NULL); | |
3656 | ||
3657 | if (ep->X_op != O_constant) | |
874e8986 | 3658 | *r = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
3659 | else |
3660 | { | |
b34976b6 AM |
3661 | mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE, |
3662 | FALSE, &insn.insn_opcode, &insn.use_extend, | |
c4e7957c | 3663 | &insn.extend); |
252b5132 | 3664 | ep = NULL; |
f6688943 | 3665 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
3666 | } |
3667 | } | |
3668 | continue; | |
3669 | ||
3670 | case '6': | |
bf12938e | 3671 | MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (args, int)); |
252b5132 RH |
3672 | continue; |
3673 | } | |
3674 | ||
3675 | break; | |
3676 | } | |
3677 | ||
f6688943 | 3678 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3679 | |
4d7206a2 | 3680 | append_insn (&insn, ep, r); |
252b5132 RH |
3681 | } |
3682 | ||
2051e8c4 MR |
3683 | /* |
3684 | * Sign-extend 32-bit mode constants that have bit 31 set and all | |
3685 | * higher bits unset. | |
3686 | */ | |
9f872bbe | 3687 | static void |
2051e8c4 MR |
3688 | normalize_constant_expr (expressionS *ex) |
3689 | { | |
9ee2a2d4 | 3690 | if (ex->X_op == O_constant |
2051e8c4 MR |
3691 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) |
3692 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
3693 | - 0x80000000); | |
3694 | } | |
3695 | ||
3696 | /* | |
3697 | * Sign-extend 32-bit mode address offsets that have bit 31 set and | |
3698 | * all higher bits unset. | |
3699 | */ | |
3700 | static void | |
3701 | normalize_address_expr (expressionS *ex) | |
3702 | { | |
3703 | if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) | |
3704 | || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) | |
3705 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
3706 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
3707 | - 0x80000000); | |
3708 | } | |
3709 | ||
438c16b8 TS |
3710 | /* |
3711 | * Generate a "jalr" instruction with a relocation hint to the called | |
3712 | * function. This occurs in NewABI PIC code. | |
3713 | */ | |
3714 | static void | |
67c0d1eb | 3715 | macro_build_jalr (expressionS *ep) |
438c16b8 | 3716 | { |
685736be | 3717 | char *f = NULL; |
b34976b6 | 3718 | |
438c16b8 | 3719 | if (HAVE_NEWABI) |
f21f8242 | 3720 | { |
cc3d92a5 | 3721 | frag_grow (8); |
f21f8242 AO |
3722 | f = frag_more (0); |
3723 | } | |
67c0d1eb | 3724 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); |
438c16b8 | 3725 | if (HAVE_NEWABI) |
f21f8242 | 3726 | fix_new_exp (frag_now, f - frag_now->fr_literal, |
a105a300 | 3727 | 4, ep, FALSE, BFD_RELOC_MIPS_JALR); |
438c16b8 TS |
3728 | } |
3729 | ||
252b5132 RH |
3730 | /* |
3731 | * Generate a "lui" instruction. | |
3732 | */ | |
3733 | static void | |
67c0d1eb | 3734 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 RH |
3735 | { |
3736 | expressionS high_expr; | |
1e915849 | 3737 | const struct mips_opcode *mo; |
252b5132 | 3738 | struct mips_cl_insn insn; |
f6688943 TS |
3739 | bfd_reloc_code_real_type r[3] |
3740 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
5a38dc70 AM |
3741 | const char *name = "lui"; |
3742 | const char *fmt = "t,u"; | |
252b5132 RH |
3743 | |
3744 | assert (! mips_opts.mips16); | |
3745 | ||
4d7206a2 | 3746 | high_expr = *ep; |
252b5132 RH |
3747 | |
3748 | if (high_expr.X_op == O_constant) | |
3749 | { | |
54f4ddb3 | 3750 | /* We can compute the instruction now without a relocation entry. */ |
e7d556df TS |
3751 | high_expr.X_add_number = ((high_expr.X_add_number + 0x8000) |
3752 | >> 16) & 0xffff; | |
f6688943 | 3753 | *r = BFD_RELOC_UNUSED; |
252b5132 | 3754 | } |
78e1bb40 | 3755 | else |
252b5132 RH |
3756 | { |
3757 | assert (ep->X_op == O_symbol); | |
bbe506e8 TS |
3758 | /* _gp_disp is a special case, used from s_cpload. |
3759 | __gnu_local_gp is used if mips_no_shared. */ | |
252b5132 | 3760 | assert (mips_pic == NO_PIC |
78e1bb40 | 3761 | || (! HAVE_NEWABI |
aa6975fb ILT |
3762 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
3763 | || (! mips_in_shared | |
bbe506e8 TS |
3764 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
3765 | "__gnu_local_gp") == 0)); | |
f6688943 | 3766 | *r = BFD_RELOC_HI16_S; |
252b5132 RH |
3767 | } |
3768 | ||
1e915849 RS |
3769 | mo = hash_find (op_hash, name); |
3770 | assert (strcmp (name, mo->name) == 0); | |
3771 | assert (strcmp (fmt, mo->args) == 0); | |
3772 | create_insn (&insn, mo); | |
252b5132 | 3773 | |
bf12938e RS |
3774 | insn.insn_opcode = insn.insn_mo->match; |
3775 | INSERT_OPERAND (RT, insn, regnum); | |
f6688943 | 3776 | if (*r == BFD_RELOC_UNUSED) |
252b5132 RH |
3777 | { |
3778 | insn.insn_opcode |= high_expr.X_add_number; | |
4d7206a2 | 3779 | append_insn (&insn, NULL, r); |
252b5132 RH |
3780 | } |
3781 | else | |
4d7206a2 | 3782 | append_insn (&insn, &high_expr, r); |
252b5132 RH |
3783 | } |
3784 | ||
885add95 CD |
3785 | /* Generate a sequence of instructions to do a load or store from a constant |
3786 | offset off of a base register (breg) into/from a target register (treg), | |
3787 | using AT if necessary. */ | |
3788 | static void | |
67c0d1eb RS |
3789 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
3790 | int treg, int breg, int dbl) | |
885add95 CD |
3791 | { |
3792 | assert (ep->X_op == O_constant); | |
3793 | ||
256ab948 | 3794 | /* Sign-extending 32-bit constants makes their handling easier. */ |
2051e8c4 MR |
3795 | if (!dbl) |
3796 | normalize_constant_expr (ep); | |
256ab948 | 3797 | |
67c1ffbe | 3798 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 3799 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
3800 | as_warn (_("operand overflow")); |
3801 | ||
3802 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
3803 | { | |
3804 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 3805 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
3806 | } |
3807 | else | |
3808 | { | |
3809 | /* 32-bit offset, need multiple instructions and AT, like: | |
3810 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
3811 | addu $tempreg,$tempreg,$breg | |
3812 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
3813 | to handle the complete offset. */ | |
67c0d1eb RS |
3814 | macro_build_lui (ep, AT); |
3815 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
3816 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 CD |
3817 | |
3818 | if (mips_opts.noat) | |
8fc2e39e | 3819 | as_bad (_("Macro used $at after \".set noat\"")); |
885add95 CD |
3820 | } |
3821 | } | |
3822 | ||
252b5132 RH |
3823 | /* set_at() |
3824 | * Generates code to set the $at register to true (one) | |
3825 | * if reg is less than the immediate expression. | |
3826 | */ | |
3827 | static void | |
67c0d1eb | 3828 | set_at (int reg, int unsignedp) |
252b5132 RH |
3829 | { |
3830 | if (imm_expr.X_op == O_constant | |
3831 | && imm_expr.X_add_number >= -0x8000 | |
3832 | && imm_expr.X_add_number < 0x8000) | |
67c0d1eb RS |
3833 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
3834 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
3835 | else |
3836 | { | |
67c0d1eb RS |
3837 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
3838 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); | |
252b5132 RH |
3839 | } |
3840 | } | |
3841 | ||
3842 | /* Warn if an expression is not a constant. */ | |
3843 | ||
3844 | static void | |
17a2f251 | 3845 | check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) |
252b5132 RH |
3846 | { |
3847 | if (ex->X_op == O_big) | |
3848 | as_bad (_("unsupported large constant")); | |
3849 | else if (ex->X_op != O_constant) | |
9ee2a2d4 MR |
3850 | as_bad (_("Instruction %s requires absolute expression"), |
3851 | ip->insn_mo->name); | |
13757d0c | 3852 | |
9ee2a2d4 MR |
3853 | if (HAVE_32BIT_GPRS) |
3854 | normalize_constant_expr (ex); | |
252b5132 RH |
3855 | } |
3856 | ||
3857 | /* Count the leading zeroes by performing a binary chop. This is a | |
3858 | bulky bit of source, but performance is a LOT better for the | |
3859 | majority of values than a simple loop to count the bits: | |
3860 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
3861 | if ((v) & (1 << (31 - lcnt))) | |
3862 | break; | |
3863 | However it is not code size friendly, and the gain will drop a bit | |
3864 | on certain cached systems. | |
3865 | */ | |
3866 | #define COUNT_TOP_ZEROES(v) \ | |
3867 | (((v) & ~0xffff) == 0 \ | |
3868 | ? ((v) & ~0xff) == 0 \ | |
3869 | ? ((v) & ~0xf) == 0 \ | |
3870 | ? ((v) & ~0x3) == 0 \ | |
3871 | ? ((v) & ~0x1) == 0 \ | |
3872 | ? !(v) \ | |
3873 | ? 32 \ | |
3874 | : 31 \ | |
3875 | : 30 \ | |
3876 | : ((v) & ~0x7) == 0 \ | |
3877 | ? 29 \ | |
3878 | : 28 \ | |
3879 | : ((v) & ~0x3f) == 0 \ | |
3880 | ? ((v) & ~0x1f) == 0 \ | |
3881 | ? 27 \ | |
3882 | : 26 \ | |
3883 | : ((v) & ~0x7f) == 0 \ | |
3884 | ? 25 \ | |
3885 | : 24 \ | |
3886 | : ((v) & ~0xfff) == 0 \ | |
3887 | ? ((v) & ~0x3ff) == 0 \ | |
3888 | ? ((v) & ~0x1ff) == 0 \ | |
3889 | ? 23 \ | |
3890 | : 22 \ | |
3891 | : ((v) & ~0x7ff) == 0 \ | |
3892 | ? 21 \ | |
3893 | : 20 \ | |
3894 | : ((v) & ~0x3fff) == 0 \ | |
3895 | ? ((v) & ~0x1fff) == 0 \ | |
3896 | ? 19 \ | |
3897 | : 18 \ | |
3898 | : ((v) & ~0x7fff) == 0 \ | |
3899 | ? 17 \ | |
3900 | : 16 \ | |
3901 | : ((v) & ~0xffffff) == 0 \ | |
3902 | ? ((v) & ~0xfffff) == 0 \ | |
3903 | ? ((v) & ~0x3ffff) == 0 \ | |
3904 | ? ((v) & ~0x1ffff) == 0 \ | |
3905 | ? 15 \ | |
3906 | : 14 \ | |
3907 | : ((v) & ~0x7ffff) == 0 \ | |
3908 | ? 13 \ | |
3909 | : 12 \ | |
3910 | : ((v) & ~0x3fffff) == 0 \ | |
3911 | ? ((v) & ~0x1fffff) == 0 \ | |
3912 | ? 11 \ | |
3913 | : 10 \ | |
3914 | : ((v) & ~0x7fffff) == 0 \ | |
3915 | ? 9 \ | |
3916 | : 8 \ | |
3917 | : ((v) & ~0xfffffff) == 0 \ | |
3918 | ? ((v) & ~0x3ffffff) == 0 \ | |
3919 | ? ((v) & ~0x1ffffff) == 0 \ | |
3920 | ? 7 \ | |
3921 | : 6 \ | |
3922 | : ((v) & ~0x7ffffff) == 0 \ | |
3923 | ? 5 \ | |
3924 | : 4 \ | |
3925 | : ((v) & ~0x3fffffff) == 0 \ | |
3926 | ? ((v) & ~0x1fffffff) == 0 \ | |
3927 | ? 3 \ | |
3928 | : 2 \ | |
3929 | : ((v) & ~0x7fffffff) == 0 \ | |
3930 | ? 1 \ | |
3931 | : 0) | |
3932 | ||
3933 | /* load_register() | |
67c1ffbe | 3934 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
3935 | * an absolute expression value into a register. |
3936 | */ | |
3937 | static void | |
67c0d1eb | 3938 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
3939 | { |
3940 | int freg; | |
3941 | expressionS hi32, lo32; | |
3942 | ||
3943 | if (ep->X_op != O_big) | |
3944 | { | |
3945 | assert (ep->X_op == O_constant); | |
256ab948 TS |
3946 | |
3947 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
2051e8c4 MR |
3948 | if (!dbl) |
3949 | normalize_constant_expr (ep); | |
256ab948 TS |
3950 | |
3951 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
3952 | { |
3953 | /* We can handle 16 bit signed values with an addiu to | |
3954 | $zero. No need to ever use daddiu here, since $zero and | |
3955 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 3956 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3957 | return; |
3958 | } | |
3959 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
3960 | { | |
3961 | /* We can handle 16 bit unsigned values with an ori to | |
3962 | $zero. */ | |
67c0d1eb | 3963 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3964 | return; |
3965 | } | |
256ab948 | 3966 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
3967 | { |
3968 | /* 32 bit values require an lui. */ | |
67c0d1eb | 3969 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 3970 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 3971 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
3972 | return; |
3973 | } | |
3974 | } | |
3975 | ||
3976 | /* The value is larger than 32 bits. */ | |
3977 | ||
2051e8c4 | 3978 | if (!dbl || HAVE_32BIT_GPRS) |
252b5132 | 3979 | { |
55e08f71 NC |
3980 | char value[32]; |
3981 | ||
3982 | sprintf_vma (value, ep->X_add_number); | |
20e1fcfd | 3983 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
67c0d1eb | 3984 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3985 | return; |
3986 | } | |
3987 | ||
3988 | if (ep->X_op != O_big) | |
3989 | { | |
3990 | hi32 = *ep; | |
3991 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3992 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3993 | hi32.X_add_number &= 0xffffffff; | |
3994 | lo32 = *ep; | |
3995 | lo32.X_add_number &= 0xffffffff; | |
3996 | } | |
3997 | else | |
3998 | { | |
3999 | assert (ep->X_add_number > 2); | |
4000 | if (ep->X_add_number == 3) | |
4001 | generic_bignum[3] = 0; | |
4002 | else if (ep->X_add_number > 4) | |
4003 | as_bad (_("Number larger than 64 bits")); | |
4004 | lo32.X_op = O_constant; | |
4005 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
4006 | hi32.X_op = O_constant; | |
4007 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
4008 | } | |
4009 | ||
4010 | if (hi32.X_add_number == 0) | |
4011 | freg = 0; | |
4012 | else | |
4013 | { | |
4014 | int shift, bit; | |
4015 | unsigned long hi, lo; | |
4016 | ||
956cd1d6 | 4017 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
4018 | { |
4019 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
4020 | { | |
67c0d1eb | 4021 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
4022 | return; |
4023 | } | |
4024 | if (lo32.X_add_number & 0x80000000) | |
4025 | { | |
67c0d1eb | 4026 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 4027 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 4028 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
4029 | return; |
4030 | } | |
4031 | } | |
252b5132 RH |
4032 | |
4033 | /* Check for 16bit shifted constant. We know that hi32 is | |
4034 | non-zero, so start the mask on the first bit of the hi32 | |
4035 | value. */ | |
4036 | shift = 17; | |
4037 | do | |
beae10d5 KH |
4038 | { |
4039 | unsigned long himask, lomask; | |
4040 | ||
4041 | if (shift < 32) | |
4042 | { | |
4043 | himask = 0xffff >> (32 - shift); | |
4044 | lomask = (0xffff << shift) & 0xffffffff; | |
4045 | } | |
4046 | else | |
4047 | { | |
4048 | himask = 0xffff << (shift - 32); | |
4049 | lomask = 0; | |
4050 | } | |
4051 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
4052 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
4053 | { | |
4054 | expressionS tmp; | |
4055 | ||
4056 | tmp.X_op = O_constant; | |
4057 | if (shift < 32) | |
4058 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
4059 | | (lo32.X_add_number >> shift)); | |
4060 | else | |
4061 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb RS |
4062 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
4063 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<", | |
4064 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
4065 | return; |
4066 | } | |
f9419b05 | 4067 | ++shift; |
beae10d5 KH |
4068 | } |
4069 | while (shift <= (64 - 16)); | |
252b5132 RH |
4070 | |
4071 | /* Find the bit number of the lowest one bit, and store the | |
4072 | shifted value in hi/lo. */ | |
4073 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
4074 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
4075 | if (lo != 0) | |
4076 | { | |
4077 | bit = 0; | |
4078 | while ((lo & 1) == 0) | |
4079 | { | |
4080 | lo >>= 1; | |
4081 | ++bit; | |
4082 | } | |
4083 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
4084 | hi >>= bit; | |
4085 | } | |
4086 | else | |
4087 | { | |
4088 | bit = 32; | |
4089 | while ((hi & 1) == 0) | |
4090 | { | |
4091 | hi >>= 1; | |
4092 | ++bit; | |
4093 | } | |
4094 | lo = hi; | |
4095 | hi = 0; | |
4096 | } | |
4097 | ||
4098 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
4099 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
4100 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
4101 | { |
4102 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 4103 | if (shift != 0) |
beae10d5 | 4104 | { |
252b5132 RH |
4105 | expressionS tmp; |
4106 | ||
4107 | /* This instruction will set the register to be all | |
4108 | ones. */ | |
beae10d5 KH |
4109 | tmp.X_op = O_constant; |
4110 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 4111 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
4112 | if (bit != 0) |
4113 | { | |
4114 | bit += shift; | |
67c0d1eb RS |
4115 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<", |
4116 | reg, reg, (bit >= 32) ? bit - 32 : bit); | |
beae10d5 | 4117 | } |
67c0d1eb RS |
4118 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<", |
4119 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
4120 | return; |
4121 | } | |
4122 | } | |
252b5132 RH |
4123 | |
4124 | /* Sign extend hi32 before calling load_register, because we can | |
4125 | generally get better code when we load a sign extended value. */ | |
4126 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 4127 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 4128 | load_register (reg, &hi32, 0); |
252b5132 RH |
4129 | freg = reg; |
4130 | } | |
4131 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
4132 | { | |
4133 | if (freg != 0) | |
4134 | { | |
67c0d1eb | 4135 | macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0); |
252b5132 RH |
4136 | freg = reg; |
4137 | } | |
4138 | } | |
4139 | else | |
4140 | { | |
4141 | expressionS mid16; | |
4142 | ||
956cd1d6 | 4143 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 4144 | { |
67c0d1eb RS |
4145 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
4146 | macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0); | |
beae10d5 KH |
4147 | return; |
4148 | } | |
252b5132 RH |
4149 | |
4150 | if (freg != 0) | |
4151 | { | |
67c0d1eb | 4152 | macro_build (NULL, "dsll", "d,w,<", reg, freg, 16); |
252b5132 RH |
4153 | freg = reg; |
4154 | } | |
4155 | mid16 = lo32; | |
4156 | mid16.X_add_number >>= 16; | |
67c0d1eb RS |
4157 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
4158 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
252b5132 RH |
4159 | freg = reg; |
4160 | } | |
4161 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 4162 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
4163 | } |
4164 | ||
269137b2 TS |
4165 | static inline void |
4166 | load_delay_nop (void) | |
4167 | { | |
4168 | if (!gpr_interlocks) | |
4169 | macro_build (NULL, "nop", ""); | |
4170 | } | |
4171 | ||
252b5132 RH |
4172 | /* Load an address into a register. */ |
4173 | ||
4174 | static void | |
67c0d1eb | 4175 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 4176 | { |
252b5132 RH |
4177 | if (ep->X_op != O_constant |
4178 | && ep->X_op != O_symbol) | |
4179 | { | |
4180 | as_bad (_("expression too complex")); | |
4181 | ep->X_op = O_constant; | |
4182 | } | |
4183 | ||
4184 | if (ep->X_op == O_constant) | |
4185 | { | |
67c0d1eb | 4186 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
4187 | return; |
4188 | } | |
4189 | ||
4190 | if (mips_pic == NO_PIC) | |
4191 | { | |
4192 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 4193 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
4194 | Otherwise we want |
4195 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
4196 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 4197 | If we have an addend, we always use the latter form. |
76b3015f | 4198 | |
d6bc6245 TS |
4199 | With 64bit address space and a usable $at we want |
4200 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4201 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
4202 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4203 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
4204 | dsll32 $reg,0 | |
3a482fd5 | 4205 | daddu $reg,$reg,$at |
76b3015f | 4206 | |
c03099e6 | 4207 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
4208 | on superscalar processors. |
4209 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4210 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4211 | dsll $reg,16 | |
4212 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
4213 | dsll $reg,16 | |
4214 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
6caf9ef4 TS |
4215 | |
4216 | For GP relative symbols in 64bit address space we can use | |
4217 | the same sequence as in 32bit address space. */ | |
aed1a261 | 4218 | if (HAVE_64BIT_SYMBOLS) |
d6bc6245 | 4219 | { |
6caf9ef4 TS |
4220 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
4221 | && !nopic_need_relax (ep->X_add_symbol, 1)) | |
4222 | { | |
4223 | relax_start (ep->X_add_symbol); | |
4224 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
4225 | mips_gp_register, BFD_RELOC_GPREL16); | |
4226 | relax_switch (); | |
4227 | } | |
d6bc6245 | 4228 | |
b8285c27 | 4229 | if (*used_at == 0 && !mips_opts.noat) |
d6bc6245 | 4230 | { |
67c0d1eb RS |
4231 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
4232 | macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S); | |
4233 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
4234 | BFD_RELOC_MIPS_HIGHER); | |
4235 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
4236 | macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0); | |
4237 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); | |
d6bc6245 TS |
4238 | *used_at = 1; |
4239 | } | |
4240 | else | |
4241 | { | |
67c0d1eb RS |
4242 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
4243 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
4244 | BFD_RELOC_MIPS_HIGHER); | |
4245 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
4246 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); | |
4247 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
4248 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); | |
d6bc6245 | 4249 | } |
6caf9ef4 TS |
4250 | |
4251 | if (mips_relax.sequence) | |
4252 | relax_end (); | |
d6bc6245 | 4253 | } |
252b5132 RH |
4254 | else |
4255 | { | |
d6bc6245 | 4256 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 4257 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
d6bc6245 | 4258 | { |
4d7206a2 | 4259 | relax_start (ep->X_add_symbol); |
67c0d1eb | 4260 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 4261 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 4262 | relax_switch (); |
d6bc6245 | 4263 | } |
67c0d1eb RS |
4264 | macro_build_lui (ep, reg); |
4265 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
4266 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
4267 | if (mips_relax.sequence) |
4268 | relax_end (); | |
d6bc6245 | 4269 | } |
252b5132 | 4270 | } |
0a44bf69 | 4271 | else if (!mips_big_got) |
252b5132 RH |
4272 | { |
4273 | expressionS ex; | |
4274 | ||
4275 | /* If this is a reference to an external symbol, we want | |
4276 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4277 | Otherwise we want | |
4278 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4279 | nop | |
4280 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
4281 | If there is a constant, it must be added in after. |
4282 | ||
ed6fb7bd | 4283 | If we have NewABI, we want |
f5040a92 AO |
4284 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
4285 | unless we're referencing a global symbol with a non-zero | |
4286 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
4287 | if (HAVE_NEWABI) |
4288 | { | |
f5040a92 AO |
4289 | if (ep->X_add_number) |
4290 | { | |
4d7206a2 | 4291 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 4292 | ep->X_add_number = 0; |
4d7206a2 | 4293 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4294 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
4295 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
4296 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
4297 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4298 | ex.X_op = O_constant; | |
67c0d1eb | 4299 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 4300 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 4301 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 4302 | relax_switch (); |
f5040a92 | 4303 | } |
67c0d1eb | 4304 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4305 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
4306 | if (mips_relax.sequence) |
4307 | relax_end (); | |
ed6fb7bd SC |
4308 | } |
4309 | else | |
4310 | { | |
f5040a92 AO |
4311 | ex.X_add_number = ep->X_add_number; |
4312 | ep->X_add_number = 0; | |
67c0d1eb RS |
4313 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
4314 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 4315 | load_delay_nop (); |
4d7206a2 RS |
4316 | relax_start (ep->X_add_symbol); |
4317 | relax_switch (); | |
67c0d1eb | 4318 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 4319 | BFD_RELOC_LO16); |
4d7206a2 | 4320 | relax_end (); |
ed6fb7bd | 4321 | |
f5040a92 AO |
4322 | if (ex.X_add_number != 0) |
4323 | { | |
4324 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
4325 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4326 | ex.X_op = O_constant; | |
67c0d1eb | 4327 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 4328 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 4329 | } |
252b5132 RH |
4330 | } |
4331 | } | |
0a44bf69 | 4332 | else if (mips_big_got) |
252b5132 RH |
4333 | { |
4334 | expressionS ex; | |
252b5132 RH |
4335 | |
4336 | /* This is the large GOT case. If this is a reference to an | |
4337 | external symbol, we want | |
4338 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4339 | addu $reg,$reg,$gp | |
4340 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
4341 | |
4342 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
4343 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
4344 | nop | |
4345 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 4346 | If there is a constant, it must be added in after. |
f5040a92 AO |
4347 | |
4348 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
4349 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
4350 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 4351 | */ |
438c16b8 TS |
4352 | if (HAVE_NEWABI) |
4353 | { | |
4d7206a2 | 4354 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 4355 | ep->X_add_number = 0; |
4d7206a2 | 4356 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4357 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
4358 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
4359 | reg, reg, mips_gp_register); | |
4360 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
4361 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
4362 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
4363 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4364 | else if (ex.X_add_number) | |
4365 | { | |
4366 | ex.X_op = O_constant; | |
67c0d1eb RS |
4367 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4368 | BFD_RELOC_LO16); | |
f5040a92 AO |
4369 | } |
4370 | ||
4371 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 4372 | relax_switch (); |
67c0d1eb | 4373 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4374 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
4375 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4376 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 4377 | relax_end (); |
438c16b8 | 4378 | } |
252b5132 | 4379 | else |
438c16b8 | 4380 | { |
f5040a92 AO |
4381 | ex.X_add_number = ep->X_add_number; |
4382 | ep->X_add_number = 0; | |
4d7206a2 | 4383 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4384 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
4385 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
4386 | reg, reg, mips_gp_register); | |
4387 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
4388 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
4389 | relax_switch (); |
4390 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
4391 | { |
4392 | /* We need a nop before loading from $gp. This special | |
4393 | check is required because the lui which starts the main | |
4394 | instruction stream does not refer to $gp, and so will not | |
4395 | insert the nop which may be required. */ | |
67c0d1eb | 4396 | macro_build (NULL, "nop", ""); |
438c16b8 | 4397 | } |
67c0d1eb | 4398 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4399 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 4400 | load_delay_nop (); |
67c0d1eb | 4401 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 4402 | BFD_RELOC_LO16); |
4d7206a2 | 4403 | relax_end (); |
438c16b8 | 4404 | |
f5040a92 AO |
4405 | if (ex.X_add_number != 0) |
4406 | { | |
4407 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
4408 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4409 | ex.X_op = O_constant; | |
67c0d1eb RS |
4410 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4411 | BFD_RELOC_LO16); | |
f5040a92 | 4412 | } |
252b5132 RH |
4413 | } |
4414 | } | |
252b5132 RH |
4415 | else |
4416 | abort (); | |
8fc2e39e TS |
4417 | |
4418 | if (mips_opts.noat && *used_at == 1) | |
4419 | as_bad (_("Macro used $at after \".set noat\"")); | |
252b5132 RH |
4420 | } |
4421 | ||
ea1fb5dc RS |
4422 | /* Move the contents of register SOURCE into register DEST. */ |
4423 | ||
4424 | static void | |
67c0d1eb | 4425 | move_register (int dest, int source) |
ea1fb5dc | 4426 | { |
67c0d1eb RS |
4427 | macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", |
4428 | dest, source, 0); | |
ea1fb5dc RS |
4429 | } |
4430 | ||
4d7206a2 | 4431 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
4432 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
4433 | The two alternatives are: | |
4d7206a2 RS |
4434 | |
4435 | Global symbol Local sybmol | |
4436 | ------------- ------------ | |
4437 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
4438 | ... ... | |
4439 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
4440 | ||
4441 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
4442 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
4443 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
4444 | |
4445 | static void | |
67c0d1eb | 4446 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4447 | { |
4448 | expressionS global; | |
4449 | ||
4450 | global = *local; | |
4451 | global.X_add_number = 0; | |
4452 | ||
4453 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
4454 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4455 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 4456 | relax_switch (); |
67c0d1eb RS |
4457 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4458 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
4459 | relax_end (); |
4460 | } | |
4461 | ||
4462 | static void | |
67c0d1eb | 4463 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4464 | { |
4465 | expressionS global; | |
4466 | ||
4467 | global.X_op = O_constant; | |
4468 | global.X_op_symbol = NULL; | |
4469 | global.X_add_symbol = NULL; | |
4470 | global.X_add_number = local->X_add_number; | |
4471 | ||
4472 | relax_start (local->X_add_symbol); | |
67c0d1eb | 4473 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
4474 | dest, dest, BFD_RELOC_LO16); |
4475 | relax_switch (); | |
67c0d1eb | 4476 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
4477 | relax_end (); |
4478 | } | |
4479 | ||
f6a22291 MR |
4480 | static void |
4481 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
4482 | { | |
4483 | expressionS global; | |
4484 | int hold_mips_optimize; | |
4485 | ||
4486 | global.X_op = O_constant; | |
4487 | global.X_op_symbol = NULL; | |
4488 | global.X_add_symbol = NULL; | |
4489 | global.X_add_number = local->X_add_number; | |
4490 | ||
4491 | relax_start (local->X_add_symbol); | |
4492 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
4493 | relax_switch (); | |
4494 | /* Set mips_optimize around the lui instruction to avoid | |
4495 | inserting an unnecessary nop after the lw. */ | |
4496 | hold_mips_optimize = mips_optimize; | |
4497 | mips_optimize = 2; | |
4498 | macro_build_lui (&global, tmp); | |
4499 | mips_optimize = hold_mips_optimize; | |
4500 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
4501 | relax_end (); | |
4502 | ||
4503 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
4504 | } | |
4505 | ||
252b5132 RH |
4506 | /* |
4507 | * Build macros | |
4508 | * This routine implements the seemingly endless macro or synthesized | |
4509 | * instructions and addressing modes in the mips assembly language. Many | |
4510 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 4511 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
4512 | * this verbose method. Others are not simple macros but are more like |
4513 | * optimizing code generation. | |
4514 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 4515 | * consecutively that would load AT with the upper half of the same address. |
252b5132 RH |
4516 | * The ensuing load upper instructions are ommited. This implies some kind |
4517 | * of global optimization. We currently only optimize within a single macro. | |
4518 | * For many of the load and store macros if the address is specified as a | |
4519 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
4520 | * first load register 'at' with zero and use it as the base register. The | |
4521 | * mips assembler simply uses register $zero. Just one tiny optimization | |
4522 | * we're missing. | |
4523 | */ | |
4524 | static void | |
17a2f251 | 4525 | macro (struct mips_cl_insn *ip) |
252b5132 | 4526 | { |
3994f87e | 4527 | int treg, sreg, dreg, breg; |
252b5132 RH |
4528 | int tempreg; |
4529 | int mask; | |
43841e91 | 4530 | int used_at = 0; |
252b5132 RH |
4531 | expressionS expr1; |
4532 | const char *s; | |
4533 | const char *s2; | |
4534 | const char *fmt; | |
4535 | int likely = 0; | |
4536 | int dbl = 0; | |
4537 | int coproc = 0; | |
4538 | int lr = 0; | |
4539 | int imm = 0; | |
1abe91b1 | 4540 | int call = 0; |
252b5132 | 4541 | int off; |
67c0d1eb | 4542 | offsetT maxnum; |
252b5132 | 4543 | bfd_reloc_code_real_type r; |
252b5132 RH |
4544 | int hold_mips_optimize; |
4545 | ||
4546 | assert (! mips_opts.mips16); | |
4547 | ||
4548 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
4549 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
4550 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
4551 | mask = ip->insn_mo->mask; | |
4552 | ||
4553 | expr1.X_op = O_constant; | |
4554 | expr1.X_op_symbol = NULL; | |
4555 | expr1.X_add_symbol = NULL; | |
4556 | expr1.X_add_number = 1; | |
4557 | ||
4558 | switch (mask) | |
4559 | { | |
4560 | case M_DABS: | |
4561 | dbl = 1; | |
4562 | case M_ABS: | |
4563 | /* bgez $a0,.+12 | |
4564 | move v0,$a0 | |
4565 | sub v0,$zero,$a0 | |
4566 | */ | |
4567 | ||
7d10b47d | 4568 | start_noreorder (); |
252b5132 RH |
4569 | |
4570 | expr1.X_add_number = 8; | |
67c0d1eb | 4571 | macro_build (&expr1, "bgez", "s,p", sreg); |
252b5132 | 4572 | if (dreg == sreg) |
67c0d1eb | 4573 | macro_build (NULL, "nop", "", 0); |
252b5132 | 4574 | else |
67c0d1eb RS |
4575 | move_register (dreg, sreg); |
4576 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); | |
252b5132 | 4577 | |
7d10b47d | 4578 | end_noreorder (); |
8fc2e39e | 4579 | break; |
252b5132 RH |
4580 | |
4581 | case M_ADD_I: | |
4582 | s = "addi"; | |
4583 | s2 = "add"; | |
4584 | goto do_addi; | |
4585 | case M_ADDU_I: | |
4586 | s = "addiu"; | |
4587 | s2 = "addu"; | |
4588 | goto do_addi; | |
4589 | case M_DADD_I: | |
4590 | dbl = 1; | |
4591 | s = "daddi"; | |
4592 | s2 = "dadd"; | |
4593 | goto do_addi; | |
4594 | case M_DADDU_I: | |
4595 | dbl = 1; | |
4596 | s = "daddiu"; | |
4597 | s2 = "daddu"; | |
4598 | do_addi: | |
4599 | if (imm_expr.X_op == O_constant | |
4600 | && imm_expr.X_add_number >= -0x8000 | |
4601 | && imm_expr.X_add_number < 0x8000) | |
4602 | { | |
67c0d1eb | 4603 | macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 4604 | break; |
252b5132 | 4605 | } |
8fc2e39e | 4606 | used_at = 1; |
67c0d1eb RS |
4607 | load_register (AT, &imm_expr, dbl); |
4608 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4609 | break; |
4610 | ||
4611 | case M_AND_I: | |
4612 | s = "andi"; | |
4613 | s2 = "and"; | |
4614 | goto do_bit; | |
4615 | case M_OR_I: | |
4616 | s = "ori"; | |
4617 | s2 = "or"; | |
4618 | goto do_bit; | |
4619 | case M_NOR_I: | |
4620 | s = ""; | |
4621 | s2 = "nor"; | |
4622 | goto do_bit; | |
4623 | case M_XOR_I: | |
4624 | s = "xori"; | |
4625 | s2 = "xor"; | |
4626 | do_bit: | |
4627 | if (imm_expr.X_op == O_constant | |
4628 | && imm_expr.X_add_number >= 0 | |
4629 | && imm_expr.X_add_number < 0x10000) | |
4630 | { | |
4631 | if (mask != M_NOR_I) | |
67c0d1eb | 4632 | macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
4633 | else |
4634 | { | |
67c0d1eb RS |
4635 | macro_build (&imm_expr, "ori", "t,r,i", |
4636 | treg, sreg, BFD_RELOC_LO16); | |
4637 | macro_build (NULL, "nor", "d,v,t", treg, treg, 0); | |
252b5132 | 4638 | } |
8fc2e39e | 4639 | break; |
252b5132 RH |
4640 | } |
4641 | ||
8fc2e39e | 4642 | used_at = 1; |
67c0d1eb RS |
4643 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4644 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4645 | break; |
4646 | ||
8b082fb1 TS |
4647 | case M_BALIGN: |
4648 | switch (imm_expr.X_add_number) | |
4649 | { | |
4650 | case 0: | |
4651 | macro_build (NULL, "nop", ""); | |
4652 | break; | |
4653 | case 2: | |
4654 | macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg); | |
4655 | break; | |
4656 | default: | |
4657 | macro_build (NULL, "balign", "t,s,2", treg, sreg, | |
4658 | (int)imm_expr.X_add_number); | |
4659 | break; | |
4660 | } | |
4661 | break; | |
4662 | ||
252b5132 RH |
4663 | case M_BEQ_I: |
4664 | s = "beq"; | |
4665 | goto beq_i; | |
4666 | case M_BEQL_I: | |
4667 | s = "beql"; | |
4668 | likely = 1; | |
4669 | goto beq_i; | |
4670 | case M_BNE_I: | |
4671 | s = "bne"; | |
4672 | goto beq_i; | |
4673 | case M_BNEL_I: | |
4674 | s = "bnel"; | |
4675 | likely = 1; | |
4676 | beq_i: | |
4677 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4678 | { | |
67c0d1eb | 4679 | macro_build (&offset_expr, s, "s,t,p", sreg, 0); |
8fc2e39e | 4680 | break; |
252b5132 | 4681 | } |
8fc2e39e | 4682 | used_at = 1; |
67c0d1eb RS |
4683 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4684 | macro_build (&offset_expr, s, "s,t,p", sreg, AT); | |
252b5132 RH |
4685 | break; |
4686 | ||
4687 | case M_BGEL: | |
4688 | likely = 1; | |
4689 | case M_BGE: | |
4690 | if (treg == 0) | |
4691 | { | |
67c0d1eb | 4692 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
8fc2e39e | 4693 | break; |
252b5132 RH |
4694 | } |
4695 | if (sreg == 0) | |
4696 | { | |
67c0d1eb | 4697 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg); |
8fc2e39e | 4698 | break; |
252b5132 | 4699 | } |
8fc2e39e | 4700 | used_at = 1; |
67c0d1eb RS |
4701 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
4702 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4703 | break; |
4704 | ||
4705 | case M_BGTL_I: | |
4706 | likely = 1; | |
4707 | case M_BGT_I: | |
4708 | /* check for > max integer */ | |
4709 | maxnum = 0x7fffffff; | |
ca4e0257 | 4710 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4711 | { |
4712 | maxnum <<= 16; | |
4713 | maxnum |= 0xffff; | |
4714 | maxnum <<= 16; | |
4715 | maxnum |= 0xffff; | |
4716 | } | |
4717 | if (imm_expr.X_op == O_constant | |
4718 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4719 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4720 | { |
4721 | do_false: | |
4722 | /* result is always false */ | |
4723 | if (! likely) | |
67c0d1eb | 4724 | macro_build (NULL, "nop", "", 0); |
252b5132 | 4725 | else |
67c0d1eb | 4726 | macro_build (&offset_expr, "bnel", "s,t,p", 0, 0); |
8fc2e39e | 4727 | break; |
252b5132 RH |
4728 | } |
4729 | if (imm_expr.X_op != O_constant) | |
4730 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4731 | ++imm_expr.X_add_number; |
252b5132 RH |
4732 | /* FALLTHROUGH */ |
4733 | case M_BGE_I: | |
4734 | case M_BGEL_I: | |
4735 | if (mask == M_BGEL_I) | |
4736 | likely = 1; | |
4737 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4738 | { | |
67c0d1eb | 4739 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
8fc2e39e | 4740 | break; |
252b5132 RH |
4741 | } |
4742 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4743 | { | |
67c0d1eb | 4744 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
8fc2e39e | 4745 | break; |
252b5132 RH |
4746 | } |
4747 | maxnum = 0x7fffffff; | |
ca4e0257 | 4748 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4749 | { |
4750 | maxnum <<= 16; | |
4751 | maxnum |= 0xffff; | |
4752 | maxnum <<= 16; | |
4753 | maxnum |= 0xffff; | |
4754 | } | |
4755 | maxnum = - maxnum - 1; | |
4756 | if (imm_expr.X_op == O_constant | |
4757 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 4758 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4759 | { |
4760 | do_true: | |
4761 | /* result is always true */ | |
4762 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
67c0d1eb | 4763 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 4764 | break; |
252b5132 | 4765 | } |
8fc2e39e | 4766 | used_at = 1; |
67c0d1eb RS |
4767 | set_at (sreg, 0); |
4768 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4769 | break; |
4770 | ||
4771 | case M_BGEUL: | |
4772 | likely = 1; | |
4773 | case M_BGEU: | |
4774 | if (treg == 0) | |
4775 | goto do_true; | |
4776 | if (sreg == 0) | |
4777 | { | |
67c0d1eb | 4778 | macro_build (&offset_expr, likely ? "beql" : "beq", |
17a2f251 | 4779 | "s,t,p", 0, treg); |
8fc2e39e | 4780 | break; |
252b5132 | 4781 | } |
8fc2e39e | 4782 | used_at = 1; |
67c0d1eb RS |
4783 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
4784 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4785 | break; |
4786 | ||
4787 | case M_BGTUL_I: | |
4788 | likely = 1; | |
4789 | case M_BGTU_I: | |
4790 | if (sreg == 0 | |
ca4e0257 | 4791 | || (HAVE_32BIT_GPRS |
252b5132 | 4792 | && imm_expr.X_op == O_constant |
956cd1d6 | 4793 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4794 | goto do_false; |
4795 | if (imm_expr.X_op != O_constant) | |
4796 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4797 | ++imm_expr.X_add_number; |
252b5132 RH |
4798 | /* FALLTHROUGH */ |
4799 | case M_BGEU_I: | |
4800 | case M_BGEUL_I: | |
4801 | if (mask == M_BGEUL_I) | |
4802 | likely = 1; | |
4803 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4804 | goto do_true; | |
4805 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4806 | { | |
67c0d1eb | 4807 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4808 | "s,t,p", sreg, 0); |
8fc2e39e | 4809 | break; |
252b5132 | 4810 | } |
8fc2e39e | 4811 | used_at = 1; |
67c0d1eb RS |
4812 | set_at (sreg, 1); |
4813 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4814 | break; |
4815 | ||
4816 | case M_BGTL: | |
4817 | likely = 1; | |
4818 | case M_BGT: | |
4819 | if (treg == 0) | |
4820 | { | |
67c0d1eb | 4821 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
8fc2e39e | 4822 | break; |
252b5132 RH |
4823 | } |
4824 | if (sreg == 0) | |
4825 | { | |
67c0d1eb | 4826 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg); |
8fc2e39e | 4827 | break; |
252b5132 | 4828 | } |
8fc2e39e | 4829 | used_at = 1; |
67c0d1eb RS |
4830 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
4831 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4832 | break; |
4833 | ||
4834 | case M_BGTUL: | |
4835 | likely = 1; | |
4836 | case M_BGTU: | |
4837 | if (treg == 0) | |
4838 | { | |
67c0d1eb | 4839 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4840 | "s,t,p", sreg, 0); |
8fc2e39e | 4841 | break; |
252b5132 RH |
4842 | } |
4843 | if (sreg == 0) | |
4844 | goto do_false; | |
8fc2e39e | 4845 | used_at = 1; |
67c0d1eb RS |
4846 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
4847 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4848 | break; |
4849 | ||
4850 | case M_BLEL: | |
4851 | likely = 1; | |
4852 | case M_BLE: | |
4853 | if (treg == 0) | |
4854 | { | |
67c0d1eb | 4855 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
8fc2e39e | 4856 | break; |
252b5132 RH |
4857 | } |
4858 | if (sreg == 0) | |
4859 | { | |
67c0d1eb | 4860 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg); |
8fc2e39e | 4861 | break; |
252b5132 | 4862 | } |
8fc2e39e | 4863 | used_at = 1; |
67c0d1eb RS |
4864 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
4865 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4866 | break; |
4867 | ||
4868 | case M_BLEL_I: | |
4869 | likely = 1; | |
4870 | case M_BLE_I: | |
4871 | maxnum = 0x7fffffff; | |
ca4e0257 | 4872 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4873 | { |
4874 | maxnum <<= 16; | |
4875 | maxnum |= 0xffff; | |
4876 | maxnum <<= 16; | |
4877 | maxnum |= 0xffff; | |
4878 | } | |
4879 | if (imm_expr.X_op == O_constant | |
4880 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4881 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4882 | goto do_true; |
4883 | if (imm_expr.X_op != O_constant) | |
4884 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4885 | ++imm_expr.X_add_number; |
252b5132 RH |
4886 | /* FALLTHROUGH */ |
4887 | case M_BLT_I: | |
4888 | case M_BLTL_I: | |
4889 | if (mask == M_BLTL_I) | |
4890 | likely = 1; | |
4891 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4892 | { | |
67c0d1eb | 4893 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
8fc2e39e | 4894 | break; |
252b5132 RH |
4895 | } |
4896 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4897 | { | |
67c0d1eb | 4898 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
8fc2e39e | 4899 | break; |
252b5132 | 4900 | } |
8fc2e39e | 4901 | used_at = 1; |
67c0d1eb RS |
4902 | set_at (sreg, 0); |
4903 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4904 | break; |
4905 | ||
4906 | case M_BLEUL: | |
4907 | likely = 1; | |
4908 | case M_BLEU: | |
4909 | if (treg == 0) | |
4910 | { | |
67c0d1eb | 4911 | macro_build (&offset_expr, likely ? "beql" : "beq", |
17a2f251 | 4912 | "s,t,p", sreg, 0); |
8fc2e39e | 4913 | break; |
252b5132 RH |
4914 | } |
4915 | if (sreg == 0) | |
4916 | goto do_true; | |
8fc2e39e | 4917 | used_at = 1; |
67c0d1eb RS |
4918 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
4919 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4920 | break; |
4921 | ||
4922 | case M_BLEUL_I: | |
4923 | likely = 1; | |
4924 | case M_BLEU_I: | |
4925 | if (sreg == 0 | |
ca4e0257 | 4926 | || (HAVE_32BIT_GPRS |
252b5132 | 4927 | && imm_expr.X_op == O_constant |
956cd1d6 | 4928 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4929 | goto do_true; |
4930 | if (imm_expr.X_op != O_constant) | |
4931 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4932 | ++imm_expr.X_add_number; |
252b5132 RH |
4933 | /* FALLTHROUGH */ |
4934 | case M_BLTU_I: | |
4935 | case M_BLTUL_I: | |
4936 | if (mask == M_BLTUL_I) | |
4937 | likely = 1; | |
4938 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4939 | goto do_false; | |
4940 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4941 | { | |
67c0d1eb | 4942 | macro_build (&offset_expr, likely ? "beql" : "beq", |
252b5132 | 4943 | "s,t,p", sreg, 0); |
8fc2e39e | 4944 | break; |
252b5132 | 4945 | } |
8fc2e39e | 4946 | used_at = 1; |
67c0d1eb RS |
4947 | set_at (sreg, 1); |
4948 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4949 | break; |
4950 | ||
4951 | case M_BLTL: | |
4952 | likely = 1; | |
4953 | case M_BLT: | |
4954 | if (treg == 0) | |
4955 | { | |
67c0d1eb | 4956 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
8fc2e39e | 4957 | break; |
252b5132 RH |
4958 | } |
4959 | if (sreg == 0) | |
4960 | { | |
67c0d1eb | 4961 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg); |
8fc2e39e | 4962 | break; |
252b5132 | 4963 | } |
8fc2e39e | 4964 | used_at = 1; |
67c0d1eb RS |
4965 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
4966 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4967 | break; |
4968 | ||
4969 | case M_BLTUL: | |
4970 | likely = 1; | |
4971 | case M_BLTU: | |
4972 | if (treg == 0) | |
4973 | goto do_false; | |
4974 | if (sreg == 0) | |
4975 | { | |
67c0d1eb | 4976 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4977 | "s,t,p", 0, treg); |
8fc2e39e | 4978 | break; |
252b5132 | 4979 | } |
8fc2e39e | 4980 | used_at = 1; |
67c0d1eb RS |
4981 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
4982 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4983 | break; |
4984 | ||
5f74bc13 CD |
4985 | case M_DEXT: |
4986 | { | |
4987 | unsigned long pos; | |
4988 | unsigned long size; | |
4989 | ||
4990 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
4991 | { | |
4992 | as_bad (_("Unsupported large constant")); | |
4993 | pos = size = 1; | |
4994 | } | |
4995 | else | |
4996 | { | |
4997 | pos = (unsigned long) imm_expr.X_add_number; | |
4998 | size = (unsigned long) imm2_expr.X_add_number; | |
4999 | } | |
5000 | ||
5001 | if (pos > 63) | |
5002 | { | |
5003 | as_bad (_("Improper position (%lu)"), pos); | |
5004 | pos = 1; | |
5005 | } | |
5006 | if (size == 0 || size > 64 | |
5007 | || (pos + size - 1) > 63) | |
5008 | { | |
5009 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
5010 | size, pos); | |
5011 | size = 1; | |
5012 | } | |
5013 | ||
5014 | if (size <= 32 && pos < 32) | |
5015 | { | |
5016 | s = "dext"; | |
5017 | fmt = "t,r,+A,+C"; | |
5018 | } | |
5019 | else if (size <= 32) | |
5020 | { | |
5021 | s = "dextu"; | |
5022 | fmt = "t,r,+E,+H"; | |
5023 | } | |
5024 | else | |
5025 | { | |
5026 | s = "dextm"; | |
5027 | fmt = "t,r,+A,+G"; | |
5028 | } | |
67c0d1eb | 5029 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, size - 1); |
5f74bc13 | 5030 | } |
8fc2e39e | 5031 | break; |
5f74bc13 CD |
5032 | |
5033 | case M_DINS: | |
5034 | { | |
5035 | unsigned long pos; | |
5036 | unsigned long size; | |
5037 | ||
5038 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
5039 | { | |
5040 | as_bad (_("Unsupported large constant")); | |
5041 | pos = size = 1; | |
5042 | } | |
5043 | else | |
5044 | { | |
5045 | pos = (unsigned long) imm_expr.X_add_number; | |
5046 | size = (unsigned long) imm2_expr.X_add_number; | |
5047 | } | |
5048 | ||
5049 | if (pos > 63) | |
5050 | { | |
5051 | as_bad (_("Improper position (%lu)"), pos); | |
5052 | pos = 1; | |
5053 | } | |
5054 | if (size == 0 || size > 64 | |
5055 | || (pos + size - 1) > 63) | |
5056 | { | |
5057 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
5058 | size, pos); | |
5059 | size = 1; | |
5060 | } | |
5061 | ||
5062 | if (pos < 32 && (pos + size - 1) < 32) | |
5063 | { | |
5064 | s = "dins"; | |
5065 | fmt = "t,r,+A,+B"; | |
5066 | } | |
5067 | else if (pos >= 32) | |
5068 | { | |
5069 | s = "dinsu"; | |
5070 | fmt = "t,r,+E,+F"; | |
5071 | } | |
5072 | else | |
5073 | { | |
5074 | s = "dinsm"; | |
5075 | fmt = "t,r,+A,+F"; | |
5076 | } | |
67c0d1eb RS |
5077 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, |
5078 | pos + size - 1); | |
5f74bc13 | 5079 | } |
8fc2e39e | 5080 | break; |
5f74bc13 | 5081 | |
252b5132 RH |
5082 | case M_DDIV_3: |
5083 | dbl = 1; | |
5084 | case M_DIV_3: | |
5085 | s = "mflo"; | |
5086 | goto do_div3; | |
5087 | case M_DREM_3: | |
5088 | dbl = 1; | |
5089 | case M_REM_3: | |
5090 | s = "mfhi"; | |
5091 | do_div3: | |
5092 | if (treg == 0) | |
5093 | { | |
5094 | as_warn (_("Divide by zero.")); | |
5095 | if (mips_trap) | |
67c0d1eb | 5096 | macro_build (NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 5097 | else |
67c0d1eb | 5098 | macro_build (NULL, "break", "c", 7); |
8fc2e39e | 5099 | break; |
252b5132 RH |
5100 | } |
5101 | ||
7d10b47d | 5102 | start_noreorder (); |
252b5132 RH |
5103 | if (mips_trap) |
5104 | { | |
67c0d1eb RS |
5105 | macro_build (NULL, "teq", "s,t,q", treg, 0, 7); |
5106 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); | |
252b5132 RH |
5107 | } |
5108 | else | |
5109 | { | |
5110 | expr1.X_add_number = 8; | |
67c0d1eb RS |
5111 | macro_build (&expr1, "bne", "s,t,p", treg, 0); |
5112 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); | |
5113 | macro_build (NULL, "break", "c", 7); | |
252b5132 RH |
5114 | } |
5115 | expr1.X_add_number = -1; | |
8fc2e39e | 5116 | used_at = 1; |
f6a22291 | 5117 | load_register (AT, &expr1, dbl); |
252b5132 | 5118 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
67c0d1eb | 5119 | macro_build (&expr1, "bne", "s,t,p", treg, AT); |
252b5132 RH |
5120 | if (dbl) |
5121 | { | |
5122 | expr1.X_add_number = 1; | |
f6a22291 | 5123 | load_register (AT, &expr1, dbl); |
67c0d1eb | 5124 | macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31); |
252b5132 RH |
5125 | } |
5126 | else | |
5127 | { | |
5128 | expr1.X_add_number = 0x80000000; | |
67c0d1eb | 5129 | macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16); |
252b5132 RH |
5130 | } |
5131 | if (mips_trap) | |
5132 | { | |
67c0d1eb | 5133 | macro_build (NULL, "teq", "s,t,q", sreg, AT, 6); |
252b5132 RH |
5134 | /* We want to close the noreorder block as soon as possible, so |
5135 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5136 | end_noreorder (); |
252b5132 RH |
5137 | } |
5138 | else | |
5139 | { | |
5140 | expr1.X_add_number = 8; | |
67c0d1eb RS |
5141 | macro_build (&expr1, "bne", "s,t,p", sreg, AT); |
5142 | macro_build (NULL, "nop", "", 0); | |
252b5132 RH |
5143 | |
5144 | /* We want to close the noreorder block as soon as possible, so | |
5145 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5146 | end_noreorder (); |
252b5132 | 5147 | |
67c0d1eb | 5148 | macro_build (NULL, "break", "c", 6); |
252b5132 | 5149 | } |
67c0d1eb | 5150 | macro_build (NULL, s, "d", dreg); |
252b5132 RH |
5151 | break; |
5152 | ||
5153 | case M_DIV_3I: | |
5154 | s = "div"; | |
5155 | s2 = "mflo"; | |
5156 | goto do_divi; | |
5157 | case M_DIVU_3I: | |
5158 | s = "divu"; | |
5159 | s2 = "mflo"; | |
5160 | goto do_divi; | |
5161 | case M_REM_3I: | |
5162 | s = "div"; | |
5163 | s2 = "mfhi"; | |
5164 | goto do_divi; | |
5165 | case M_REMU_3I: | |
5166 | s = "divu"; | |
5167 | s2 = "mfhi"; | |
5168 | goto do_divi; | |
5169 | case M_DDIV_3I: | |
5170 | dbl = 1; | |
5171 | s = "ddiv"; | |
5172 | s2 = "mflo"; | |
5173 | goto do_divi; | |
5174 | case M_DDIVU_3I: | |
5175 | dbl = 1; | |
5176 | s = "ddivu"; | |
5177 | s2 = "mflo"; | |
5178 | goto do_divi; | |
5179 | case M_DREM_3I: | |
5180 | dbl = 1; | |
5181 | s = "ddiv"; | |
5182 | s2 = "mfhi"; | |
5183 | goto do_divi; | |
5184 | case M_DREMU_3I: | |
5185 | dbl = 1; | |
5186 | s = "ddivu"; | |
5187 | s2 = "mfhi"; | |
5188 | do_divi: | |
5189 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5190 | { | |
5191 | as_warn (_("Divide by zero.")); | |
5192 | if (mips_trap) | |
67c0d1eb | 5193 | macro_build (NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 5194 | else |
67c0d1eb | 5195 | macro_build (NULL, "break", "c", 7); |
8fc2e39e | 5196 | break; |
252b5132 RH |
5197 | } |
5198 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
5199 | { | |
5200 | if (strcmp (s2, "mflo") == 0) | |
67c0d1eb | 5201 | move_register (dreg, sreg); |
252b5132 | 5202 | else |
67c0d1eb | 5203 | move_register (dreg, 0); |
8fc2e39e | 5204 | break; |
252b5132 RH |
5205 | } |
5206 | if (imm_expr.X_op == O_constant | |
5207 | && imm_expr.X_add_number == -1 | |
5208 | && s[strlen (s) - 1] != 'u') | |
5209 | { | |
5210 | if (strcmp (s2, "mflo") == 0) | |
5211 | { | |
67c0d1eb | 5212 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg); |
252b5132 RH |
5213 | } |
5214 | else | |
67c0d1eb | 5215 | move_register (dreg, 0); |
8fc2e39e | 5216 | break; |
252b5132 RH |
5217 | } |
5218 | ||
8fc2e39e | 5219 | used_at = 1; |
67c0d1eb RS |
5220 | load_register (AT, &imm_expr, dbl); |
5221 | macro_build (NULL, s, "z,s,t", sreg, AT); | |
5222 | macro_build (NULL, s2, "d", dreg); | |
252b5132 RH |
5223 | break; |
5224 | ||
5225 | case M_DIVU_3: | |
5226 | s = "divu"; | |
5227 | s2 = "mflo"; | |
5228 | goto do_divu3; | |
5229 | case M_REMU_3: | |
5230 | s = "divu"; | |
5231 | s2 = "mfhi"; | |
5232 | goto do_divu3; | |
5233 | case M_DDIVU_3: | |
5234 | s = "ddivu"; | |
5235 | s2 = "mflo"; | |
5236 | goto do_divu3; | |
5237 | case M_DREMU_3: | |
5238 | s = "ddivu"; | |
5239 | s2 = "mfhi"; | |
5240 | do_divu3: | |
7d10b47d | 5241 | start_noreorder (); |
252b5132 RH |
5242 | if (mips_trap) |
5243 | { | |
67c0d1eb RS |
5244 | macro_build (NULL, "teq", "s,t,q", treg, 0, 7); |
5245 | macro_build (NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
5246 | /* We want to close the noreorder block as soon as possible, so |
5247 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5248 | end_noreorder (); |
252b5132 RH |
5249 | } |
5250 | else | |
5251 | { | |
5252 | expr1.X_add_number = 8; | |
67c0d1eb RS |
5253 | macro_build (&expr1, "bne", "s,t,p", treg, 0); |
5254 | macro_build (NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
5255 | |
5256 | /* We want to close the noreorder block as soon as possible, so | |
5257 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5258 | end_noreorder (); |
67c0d1eb | 5259 | macro_build (NULL, "break", "c", 7); |
252b5132 | 5260 | } |
67c0d1eb | 5261 | macro_build (NULL, s2, "d", dreg); |
8fc2e39e | 5262 | break; |
252b5132 | 5263 | |
1abe91b1 MR |
5264 | case M_DLCA_AB: |
5265 | dbl = 1; | |
5266 | case M_LCA_AB: | |
5267 | call = 1; | |
5268 | goto do_la; | |
252b5132 RH |
5269 | case M_DLA_AB: |
5270 | dbl = 1; | |
5271 | case M_LA_AB: | |
1abe91b1 | 5272 | do_la: |
252b5132 RH |
5273 | /* Load the address of a symbol into a register. If breg is not |
5274 | zero, we then add a base register to it. */ | |
5275 | ||
3bec30a8 TS |
5276 | if (dbl && HAVE_32BIT_GPRS) |
5277 | as_warn (_("dla used to load 32-bit register")); | |
5278 | ||
c90bbe5b | 5279 | if (! dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
5280 | as_warn (_("la used to load 64-bit address")); |
5281 | ||
0c11417f MR |
5282 | if (offset_expr.X_op == O_constant |
5283 | && offset_expr.X_add_number >= -0x8000 | |
5284 | && offset_expr.X_add_number < 0x8000) | |
5285 | { | |
aed1a261 | 5286 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
17a2f251 | 5287 | "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 5288 | break; |
0c11417f MR |
5289 | } |
5290 | ||
b8285c27 | 5291 | if (!mips_opts.noat && (treg == breg)) |
afdbd6d0 CD |
5292 | { |
5293 | tempreg = AT; | |
5294 | used_at = 1; | |
5295 | } | |
5296 | else | |
5297 | { | |
5298 | tempreg = treg; | |
afdbd6d0 CD |
5299 | } |
5300 | ||
252b5132 RH |
5301 | if (offset_expr.X_op != O_symbol |
5302 | && offset_expr.X_op != O_constant) | |
5303 | { | |
5304 | as_bad (_("expression too complex")); | |
5305 | offset_expr.X_op = O_constant; | |
5306 | } | |
5307 | ||
252b5132 | 5308 | if (offset_expr.X_op == O_constant) |
aed1a261 | 5309 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
5310 | else if (mips_pic == NO_PIC) |
5311 | { | |
d6bc6245 | 5312 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 5313 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
5314 | Otherwise we want |
5315 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5316 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5317 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 5318 | so we may as well always use the latter form. |
76b3015f | 5319 | |
6caf9ef4 TS |
5320 | With 64bit address space and a usable $at we want |
5321 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5322 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5323 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5324 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
5325 | dsll32 $tempreg,0 | |
5326 | daddu $tempreg,$tempreg,$at | |
5327 | ||
5328 | If $at is already in use, we use a path which is suboptimal | |
5329 | on superscalar processors. | |
5330 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5331 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5332 | dsll $tempreg,16 | |
5333 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5334 | dsll $tempreg,16 | |
5335 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
5336 | ||
5337 | For GP relative symbols in 64bit address space we can use | |
5338 | the same sequence as in 32bit address space. */ | |
aed1a261 | 5339 | if (HAVE_64BIT_SYMBOLS) |
252b5132 | 5340 | { |
6caf9ef4 TS |
5341 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
5342 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
5343 | { | |
5344 | relax_start (offset_expr.X_add_symbol); | |
5345 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5346 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
5347 | relax_switch (); | |
5348 | } | |
d6bc6245 | 5349 | |
b8285c27 | 5350 | if (used_at == 0 && !mips_opts.noat) |
98d3f06f | 5351 | { |
67c0d1eb | 5352 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 5353 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 5354 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 5355 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 5356 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5357 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 5358 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5359 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb RS |
5360 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); |
5361 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
98d3f06f KH |
5362 | used_at = 1; |
5363 | } | |
5364 | else | |
5365 | { | |
67c0d1eb | 5366 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 5367 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 5368 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5369 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb RS |
5370 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
5371 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 5372 | tempreg, tempreg, BFD_RELOC_HI16_S); |
67c0d1eb RS |
5373 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
5374 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 5375 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 5376 | } |
6caf9ef4 TS |
5377 | |
5378 | if (mips_relax.sequence) | |
5379 | relax_end (); | |
98d3f06f KH |
5380 | } |
5381 | else | |
5382 | { | |
5383 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 5384 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
98d3f06f | 5385 | { |
4d7206a2 | 5386 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5387 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5388 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 5389 | relax_switch (); |
98d3f06f | 5390 | } |
6943caf0 ILT |
5391 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
5392 | as_bad (_("offset too large")); | |
67c0d1eb RS |
5393 | macro_build_lui (&offset_expr, tempreg); |
5394 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5395 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
5396 | if (mips_relax.sequence) |
5397 | relax_end (); | |
98d3f06f | 5398 | } |
252b5132 | 5399 | } |
0a44bf69 | 5400 | else if (!mips_big_got && !HAVE_NEWABI) |
252b5132 | 5401 | { |
9117d219 NC |
5402 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
5403 | ||
252b5132 RH |
5404 | /* If this is a reference to an external symbol, and there |
5405 | is no constant, we want | |
5406 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 5407 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 5408 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
5409 | For a local symbol, we want |
5410 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5411 | nop | |
5412 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5413 | ||
5414 | If we have a small constant, and this is a reference to | |
5415 | an external symbol, we want | |
5416 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5417 | nop | |
5418 | addiu $tempreg,$tempreg,<constant> | |
5419 | For a local symbol, we want the same instruction | |
5420 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
5421 | addiu instruction. | |
5422 | ||
5423 | If we have a large constant, and this is a reference to | |
5424 | an external symbol, we want | |
5425 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5426 | lui $at,<hiconstant> | |
5427 | addiu $at,$at,<loconstant> | |
5428 | addu $tempreg,$tempreg,$at | |
5429 | For a local symbol, we want the same instruction | |
5430 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 5431 | addiu instruction. |
ed6fb7bd SC |
5432 | */ |
5433 | ||
4d7206a2 | 5434 | if (offset_expr.X_add_number == 0) |
252b5132 | 5435 | { |
0a44bf69 RS |
5436 | if (mips_pic == SVR4_PIC |
5437 | && breg == 0 | |
5438 | && (call || tempreg == PIC_CALL_REG)) | |
4d7206a2 RS |
5439 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; |
5440 | ||
5441 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
5442 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5443 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 5444 | if (breg != 0) |
252b5132 RH |
5445 | { |
5446 | /* We're going to put in an addu instruction using | |
5447 | tempreg, so we may as well insert the nop right | |
5448 | now. */ | |
269137b2 | 5449 | load_delay_nop (); |
252b5132 | 5450 | } |
4d7206a2 | 5451 | relax_switch (); |
67c0d1eb RS |
5452 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5453 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 5454 | load_delay_nop (); |
67c0d1eb RS |
5455 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5456 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 5457 | relax_end (); |
252b5132 RH |
5458 | /* FIXME: If breg == 0, and the next instruction uses |
5459 | $tempreg, then if this variant case is used an extra | |
5460 | nop will be generated. */ | |
5461 | } | |
4d7206a2 RS |
5462 | else if (offset_expr.X_add_number >= -0x8000 |
5463 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 5464 | { |
67c0d1eb | 5465 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 5466 | load_delay_nop (); |
67c0d1eb | 5467 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
5468 | } |
5469 | else | |
5470 | { | |
4d7206a2 RS |
5471 | expr1.X_add_number = offset_expr.X_add_number; |
5472 | offset_expr.X_add_number = | |
5473 | ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
67c0d1eb | 5474 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 5475 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
5476 | /* If we are going to add in a base register, and the |
5477 | target register and the base register are the same, | |
5478 | then we are using AT as a temporary register. Since | |
5479 | we want to load the constant into AT, we add our | |
5480 | current AT (from the global offset table) and the | |
5481 | register into the register now, and pretend we were | |
5482 | not using a base register. */ | |
67c0d1eb | 5483 | if (breg == treg) |
252b5132 | 5484 | { |
269137b2 | 5485 | load_delay_nop (); |
67c0d1eb | 5486 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5487 | treg, AT, breg); |
252b5132 RH |
5488 | breg = 0; |
5489 | tempreg = treg; | |
252b5132 | 5490 | } |
f6a22291 | 5491 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
5492 | used_at = 1; |
5493 | } | |
5494 | } | |
0a44bf69 | 5495 | else if (!mips_big_got && HAVE_NEWABI) |
f5040a92 | 5496 | { |
67c0d1eb | 5497 | int add_breg_early = 0; |
f5040a92 AO |
5498 | |
5499 | /* If this is a reference to an external, and there is no | |
5500 | constant, or local symbol (*), with or without a | |
5501 | constant, we want | |
5502 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 5503 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5504 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
5505 | ||
5506 | If we have a small constant, and this is a reference to | |
5507 | an external symbol, we want | |
5508 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5509 | addiu $tempreg,$tempreg,<constant> | |
5510 | ||
5511 | If we have a large constant, and this is a reference to | |
5512 | an external symbol, we want | |
5513 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5514 | lui $at,<hiconstant> | |
5515 | addiu $at,$at,<loconstant> | |
5516 | addu $tempreg,$tempreg,$at | |
5517 | ||
5518 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
5519 | local symbols, even though it introduces an additional | |
5520 | instruction. */ | |
5521 | ||
f5040a92 AO |
5522 | if (offset_expr.X_add_number) |
5523 | { | |
4d7206a2 | 5524 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5525 | offset_expr.X_add_number = 0; |
5526 | ||
4d7206a2 | 5527 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5528 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5529 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5530 | |
5531 | if (expr1.X_add_number >= -0x8000 | |
5532 | && expr1.X_add_number < 0x8000) | |
5533 | { | |
67c0d1eb RS |
5534 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
5535 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 5536 | } |
ecd13cd3 | 5537 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 AO |
5538 | { |
5539 | int dreg; | |
5540 | ||
5541 | /* If we are going to add in a base register, and the | |
5542 | target register and the base register are the same, | |
5543 | then we are using AT as a temporary register. Since | |
5544 | we want to load the constant into AT, we add our | |
5545 | current AT (from the global offset table) and the | |
5546 | register into the register now, and pretend we were | |
5547 | not using a base register. */ | |
5548 | if (breg != treg) | |
5549 | dreg = tempreg; | |
5550 | else | |
5551 | { | |
5552 | assert (tempreg == AT); | |
67c0d1eb RS |
5553 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
5554 | treg, AT, breg); | |
f5040a92 | 5555 | dreg = treg; |
67c0d1eb | 5556 | add_breg_early = 1; |
f5040a92 AO |
5557 | } |
5558 | ||
f6a22291 | 5559 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5560 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5561 | dreg, dreg, AT); |
f5040a92 | 5562 | |
f5040a92 AO |
5563 | used_at = 1; |
5564 | } | |
5565 | else | |
5566 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5567 | ||
4d7206a2 | 5568 | relax_switch (); |
f5040a92 AO |
5569 | offset_expr.X_add_number = expr1.X_add_number; |
5570 | ||
67c0d1eb RS |
5571 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5572 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
5573 | if (add_breg_early) | |
f5040a92 | 5574 | { |
67c0d1eb | 5575 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
f899b4b8 | 5576 | treg, tempreg, breg); |
f5040a92 AO |
5577 | breg = 0; |
5578 | tempreg = treg; | |
5579 | } | |
4d7206a2 | 5580 | relax_end (); |
f5040a92 | 5581 | } |
4d7206a2 | 5582 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 5583 | { |
4d7206a2 | 5584 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5585 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5586 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 5587 | relax_switch (); |
67c0d1eb RS |
5588 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5589 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 5590 | relax_end (); |
f5040a92 | 5591 | } |
4d7206a2 | 5592 | else |
f5040a92 | 5593 | { |
67c0d1eb RS |
5594 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5595 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5596 | } |
5597 | } | |
0a44bf69 | 5598 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 5599 | { |
67c0d1eb | 5600 | int gpdelay; |
9117d219 NC |
5601 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5602 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 5603 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
5604 | |
5605 | /* This is the large GOT case. If this is a reference to an | |
5606 | external symbol, and there is no constant, we want | |
5607 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5608 | addu $tempreg,$tempreg,$gp | |
5609 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5610 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
5611 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5612 | addu $tempreg,$tempreg,$gp | |
5613 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
5614 | For a local symbol, we want |
5615 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5616 | nop | |
5617 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5618 | ||
5619 | If we have a small constant, and this is a reference to | |
5620 | an external symbol, we want | |
5621 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5622 | addu $tempreg,$tempreg,$gp | |
5623 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5624 | nop | |
5625 | addiu $tempreg,$tempreg,<constant> | |
5626 | For a local symbol, we want | |
5627 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5628 | nop | |
5629 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
5630 | ||
5631 | If we have a large constant, and this is a reference to | |
5632 | an external symbol, we want | |
5633 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5634 | addu $tempreg,$tempreg,$gp | |
5635 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5636 | lui $at,<hiconstant> | |
5637 | addiu $at,$at,<loconstant> | |
5638 | addu $tempreg,$tempreg,$at | |
5639 | For a local symbol, we want | |
5640 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5641 | lui $at,<hiconstant> | |
5642 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
5643 | addu $tempreg,$tempreg,$at | |
f5040a92 | 5644 | */ |
438c16b8 | 5645 | |
252b5132 RH |
5646 | expr1.X_add_number = offset_expr.X_add_number; |
5647 | offset_expr.X_add_number = 0; | |
4d7206a2 | 5648 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 5649 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
5650 | if (expr1.X_add_number == 0 && breg == 0 |
5651 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
5652 | { |
5653 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5654 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5655 | } | |
67c0d1eb RS |
5656 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
5657 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5658 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 5659 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 5660 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
5661 | if (expr1.X_add_number == 0) |
5662 | { | |
67c0d1eb | 5663 | if (breg != 0) |
252b5132 RH |
5664 | { |
5665 | /* We're going to put in an addu instruction using | |
5666 | tempreg, so we may as well insert the nop right | |
5667 | now. */ | |
269137b2 | 5668 | load_delay_nop (); |
252b5132 | 5669 | } |
252b5132 RH |
5670 | } |
5671 | else if (expr1.X_add_number >= -0x8000 | |
5672 | && expr1.X_add_number < 0x8000) | |
5673 | { | |
269137b2 | 5674 | load_delay_nop (); |
67c0d1eb | 5675 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5676 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
5677 | } |
5678 | else | |
5679 | { | |
67c0d1eb | 5680 | int dreg; |
252b5132 RH |
5681 | |
5682 | /* If we are going to add in a base register, and the | |
5683 | target register and the base register are the same, | |
5684 | then we are using AT as a temporary register. Since | |
5685 | we want to load the constant into AT, we add our | |
5686 | current AT (from the global offset table) and the | |
5687 | register into the register now, and pretend we were | |
5688 | not using a base register. */ | |
5689 | if (breg != treg) | |
67c0d1eb | 5690 | dreg = tempreg; |
252b5132 RH |
5691 | else |
5692 | { | |
5693 | assert (tempreg == AT); | |
269137b2 | 5694 | load_delay_nop (); |
67c0d1eb | 5695 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5696 | treg, AT, breg); |
252b5132 | 5697 | dreg = treg; |
252b5132 RH |
5698 | } |
5699 | ||
f6a22291 | 5700 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5701 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 5702 | |
252b5132 RH |
5703 | used_at = 1; |
5704 | } | |
4d7206a2 RS |
5705 | offset_expr.X_add_number = |
5706 | ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
5707 | relax_switch (); | |
252b5132 | 5708 | |
67c0d1eb | 5709 | if (gpdelay) |
252b5132 RH |
5710 | { |
5711 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 5712 | the first instruction on the main stream does not. */ |
67c0d1eb | 5713 | macro_build (NULL, "nop", ""); |
252b5132 | 5714 | } |
ed6fb7bd | 5715 | |
67c0d1eb RS |
5716 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5717 | local_reloc_type, mips_gp_register); | |
f5040a92 | 5718 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
5719 | && expr1.X_add_number < 0x8000) |
5720 | { | |
269137b2 | 5721 | load_delay_nop (); |
67c0d1eb RS |
5722 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5723 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 5724 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
5725 | register, the external symbol case ended with a load, |
5726 | so if the symbol turns out to not be external, and | |
5727 | the next instruction uses tempreg, an unnecessary nop | |
5728 | will be inserted. */ | |
252b5132 RH |
5729 | } |
5730 | else | |
5731 | { | |
5732 | if (breg == treg) | |
5733 | { | |
5734 | /* We must add in the base register now, as in the | |
f5040a92 | 5735 | external symbol case. */ |
252b5132 | 5736 | assert (tempreg == AT); |
269137b2 | 5737 | load_delay_nop (); |
67c0d1eb | 5738 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5739 | treg, AT, breg); |
252b5132 RH |
5740 | tempreg = treg; |
5741 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 5742 | it in in both cases. */ |
252b5132 RH |
5743 | breg = 0; |
5744 | } | |
5745 | ||
67c0d1eb RS |
5746 | macro_build_lui (&expr1, AT); |
5747 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 5748 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 5749 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5750 | tempreg, tempreg, AT); |
8fc2e39e | 5751 | used_at = 1; |
252b5132 | 5752 | } |
4d7206a2 | 5753 | relax_end (); |
252b5132 | 5754 | } |
0a44bf69 | 5755 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 5756 | { |
f5040a92 AO |
5757 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5758 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 5759 | int add_breg_early = 0; |
f5040a92 AO |
5760 | |
5761 | /* This is the large GOT case. If this is a reference to an | |
5762 | external symbol, and there is no constant, we want | |
5763 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5764 | add $tempreg,$tempreg,$gp | |
5765 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5766 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5767 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5768 | add $tempreg,$tempreg,$gp | |
5769 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
5770 | ||
5771 | If we have a small constant, and this is a reference to | |
5772 | an external symbol, we want | |
5773 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5774 | add $tempreg,$tempreg,$gp | |
5775 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5776 | addi $tempreg,$tempreg,<constant> | |
5777 | ||
5778 | If we have a large constant, and this is a reference to | |
5779 | an external symbol, we want | |
5780 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5781 | addu $tempreg,$tempreg,$gp | |
5782 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5783 | lui $at,<hiconstant> | |
5784 | addi $at,$at,<loconstant> | |
5785 | add $tempreg,$tempreg,$at | |
5786 | ||
5787 | If we have NewABI, and we know it's a local symbol, we want | |
5788 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
5789 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
5790 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
5791 | ||
4d7206a2 | 5792 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 5793 | |
4d7206a2 | 5794 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5795 | offset_expr.X_add_number = 0; |
5796 | ||
1abe91b1 MR |
5797 | if (expr1.X_add_number == 0 && breg == 0 |
5798 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
5799 | { |
5800 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5801 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5802 | } | |
67c0d1eb RS |
5803 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
5804 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5805 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
5806 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5807 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
5808 | |
5809 | if (expr1.X_add_number == 0) | |
4d7206a2 | 5810 | ; |
f5040a92 AO |
5811 | else if (expr1.X_add_number >= -0x8000 |
5812 | && expr1.X_add_number < 0x8000) | |
5813 | { | |
67c0d1eb | 5814 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5815 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 5816 | } |
ecd13cd3 | 5817 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 AO |
5818 | { |
5819 | int dreg; | |
5820 | ||
5821 | /* If we are going to add in a base register, and the | |
5822 | target register and the base register are the same, | |
5823 | then we are using AT as a temporary register. Since | |
5824 | we want to load the constant into AT, we add our | |
5825 | current AT (from the global offset table) and the | |
5826 | register into the register now, and pretend we were | |
5827 | not using a base register. */ | |
5828 | if (breg != treg) | |
5829 | dreg = tempreg; | |
5830 | else | |
5831 | { | |
5832 | assert (tempreg == AT); | |
67c0d1eb | 5833 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5834 | treg, AT, breg); |
f5040a92 | 5835 | dreg = treg; |
67c0d1eb | 5836 | add_breg_early = 1; |
f5040a92 AO |
5837 | } |
5838 | ||
f6a22291 | 5839 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5840 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 5841 | |
f5040a92 AO |
5842 | used_at = 1; |
5843 | } | |
5844 | else | |
5845 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5846 | ||
4d7206a2 | 5847 | relax_switch (); |
f5040a92 | 5848 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
5849 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5850 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
5851 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
5852 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
5853 | if (add_breg_early) | |
f5040a92 | 5854 | { |
67c0d1eb | 5855 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5856 | treg, tempreg, breg); |
f5040a92 AO |
5857 | breg = 0; |
5858 | tempreg = treg; | |
5859 | } | |
4d7206a2 | 5860 | relax_end (); |
f5040a92 | 5861 | } |
252b5132 RH |
5862 | else |
5863 | abort (); | |
5864 | ||
5865 | if (breg != 0) | |
aed1a261 | 5866 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg); |
252b5132 RH |
5867 | break; |
5868 | ||
5869 | case M_J_A: | |
5870 | /* The j instruction may not be used in PIC code, since it | |
5871 | requires an absolute address. We convert it to a b | |
5872 | instruction. */ | |
5873 | if (mips_pic == NO_PIC) | |
67c0d1eb | 5874 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 5875 | else |
67c0d1eb | 5876 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 5877 | break; |
252b5132 RH |
5878 | |
5879 | /* The jal instructions must be handled as macros because when | |
5880 | generating PIC code they expand to multi-instruction | |
5881 | sequences. Normally they are simple instructions. */ | |
5882 | case M_JAL_1: | |
5883 | dreg = RA; | |
5884 | /* Fall through. */ | |
5885 | case M_JAL_2: | |
3e722fb5 | 5886 | if (mips_pic == NO_PIC) |
67c0d1eb | 5887 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
0a44bf69 | 5888 | else |
252b5132 RH |
5889 | { |
5890 | if (sreg != PIC_CALL_REG) | |
5891 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 5892 | |
67c0d1eb | 5893 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
0a44bf69 | 5894 | if (mips_pic == SVR4_PIC && !HAVE_NEWABI) |
252b5132 | 5895 | { |
6478892d TS |
5896 | if (mips_cprestore_offset < 0) |
5897 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5898 | else | |
5899 | { | |
7a621144 DJ |
5900 | if (! mips_frame_reg_valid) |
5901 | { | |
5902 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5903 | /* Quiet this warning. */ | |
5904 | mips_frame_reg_valid = 1; | |
5905 | } | |
5906 | if (! mips_cprestore_valid) | |
5907 | { | |
5908 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5909 | /* Quiet this warning. */ | |
5910 | mips_cprestore_valid = 1; | |
5911 | } | |
6478892d | 5912 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 5913 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 5914 | mips_gp_register, |
256ab948 TS |
5915 | mips_frame_reg, |
5916 | HAVE_64BIT_ADDRESSES); | |
6478892d | 5917 | } |
252b5132 RH |
5918 | } |
5919 | } | |
252b5132 | 5920 | |
8fc2e39e | 5921 | break; |
252b5132 RH |
5922 | |
5923 | case M_JAL_A: | |
5924 | if (mips_pic == NO_PIC) | |
67c0d1eb | 5925 | macro_build (&offset_expr, "jal", "a"); |
252b5132 RH |
5926 | else if (mips_pic == SVR4_PIC) |
5927 | { | |
5928 | /* If this is a reference to an external symbol, and we are | |
5929 | using a small GOT, we want | |
5930 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
5931 | nop | |
f9419b05 | 5932 | jalr $ra,$25 |
252b5132 RH |
5933 | nop |
5934 | lw $gp,cprestore($sp) | |
5935 | The cprestore value is set using the .cprestore | |
5936 | pseudo-op. If we are using a big GOT, we want | |
5937 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
5938 | addu $25,$25,$gp | |
5939 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
5940 | nop | |
f9419b05 | 5941 | jalr $ra,$25 |
252b5132 RH |
5942 | nop |
5943 | lw $gp,cprestore($sp) | |
5944 | If the symbol is not external, we want | |
5945 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5946 | nop | |
5947 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 5948 | jalr $ra,$25 |
252b5132 | 5949 | nop |
438c16b8 | 5950 | lw $gp,cprestore($sp) |
f5040a92 AO |
5951 | |
5952 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
5953 | sequences above, minus nops, unless the symbol is local, | |
5954 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
5955 | GOT_DISP. */ | |
438c16b8 | 5956 | if (HAVE_NEWABI) |
252b5132 | 5957 | { |
f5040a92 AO |
5958 | if (! mips_big_got) |
5959 | { | |
4d7206a2 | 5960 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5961 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5962 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 5963 | mips_gp_register); |
4d7206a2 | 5964 | relax_switch (); |
67c0d1eb RS |
5965 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5966 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
5967 | mips_gp_register); |
5968 | relax_end (); | |
f5040a92 AO |
5969 | } |
5970 | else | |
5971 | { | |
4d7206a2 | 5972 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5973 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, |
5974 | BFD_RELOC_MIPS_CALL_HI16); | |
5975 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
5976 | PIC_CALL_REG, mips_gp_register); | |
5977 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
5978 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
5979 | PIC_CALL_REG); | |
4d7206a2 | 5980 | relax_switch (); |
67c0d1eb RS |
5981 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5982 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
5983 | mips_gp_register); | |
5984 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5985 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 5986 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 5987 | relax_end (); |
f5040a92 | 5988 | } |
684022ea | 5989 | |
67c0d1eb | 5990 | macro_build_jalr (&offset_expr); |
252b5132 RH |
5991 | } |
5992 | else | |
5993 | { | |
4d7206a2 | 5994 | relax_start (offset_expr.X_add_symbol); |
438c16b8 TS |
5995 | if (! mips_big_got) |
5996 | { | |
67c0d1eb RS |
5997 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5998 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 5999 | mips_gp_register); |
269137b2 | 6000 | load_delay_nop (); |
4d7206a2 | 6001 | relax_switch (); |
438c16b8 | 6002 | } |
252b5132 | 6003 | else |
252b5132 | 6004 | { |
67c0d1eb RS |
6005 | int gpdelay; |
6006 | ||
6007 | gpdelay = reg_needs_delay (mips_gp_register); | |
6008 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, | |
6009 | BFD_RELOC_MIPS_CALL_HI16); | |
6010 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
6011 | PIC_CALL_REG, mips_gp_register); | |
6012 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
6013 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
6014 | PIC_CALL_REG); | |
269137b2 | 6015 | load_delay_nop (); |
4d7206a2 | 6016 | relax_switch (); |
67c0d1eb RS |
6017 | if (gpdelay) |
6018 | macro_build (NULL, "nop", ""); | |
252b5132 | 6019 | } |
67c0d1eb RS |
6020 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
6021 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 6022 | mips_gp_register); |
269137b2 | 6023 | load_delay_nop (); |
67c0d1eb RS |
6024 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
6025 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 6026 | relax_end (); |
67c0d1eb | 6027 | macro_build_jalr (&offset_expr); |
438c16b8 | 6028 | |
6478892d TS |
6029 | if (mips_cprestore_offset < 0) |
6030 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
6031 | else | |
6032 | { | |
7a621144 DJ |
6033 | if (! mips_frame_reg_valid) |
6034 | { | |
6035 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
6036 | /* Quiet this warning. */ | |
6037 | mips_frame_reg_valid = 1; | |
6038 | } | |
6039 | if (! mips_cprestore_valid) | |
6040 | { | |
6041 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
6042 | /* Quiet this warning. */ | |
6043 | mips_cprestore_valid = 1; | |
6044 | } | |
6478892d | 6045 | if (mips_opts.noreorder) |
67c0d1eb | 6046 | macro_build (NULL, "nop", ""); |
6478892d | 6047 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 6048 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 6049 | mips_gp_register, |
256ab948 TS |
6050 | mips_frame_reg, |
6051 | HAVE_64BIT_ADDRESSES); | |
6478892d | 6052 | } |
252b5132 RH |
6053 | } |
6054 | } | |
0a44bf69 RS |
6055 | else if (mips_pic == VXWORKS_PIC) |
6056 | as_bad (_("Non-PIC jump used in PIC library")); | |
252b5132 RH |
6057 | else |
6058 | abort (); | |
6059 | ||
8fc2e39e | 6060 | break; |
252b5132 RH |
6061 | |
6062 | case M_LB_AB: | |
6063 | s = "lb"; | |
6064 | goto ld; | |
6065 | case M_LBU_AB: | |
6066 | s = "lbu"; | |
6067 | goto ld; | |
6068 | case M_LH_AB: | |
6069 | s = "lh"; | |
6070 | goto ld; | |
6071 | case M_LHU_AB: | |
6072 | s = "lhu"; | |
6073 | goto ld; | |
6074 | case M_LW_AB: | |
6075 | s = "lw"; | |
6076 | goto ld; | |
6077 | case M_LWC0_AB: | |
6078 | s = "lwc0"; | |
bdaaa2e1 | 6079 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6080 | coproc = 1; |
6081 | goto ld; | |
6082 | case M_LWC1_AB: | |
6083 | s = "lwc1"; | |
bdaaa2e1 | 6084 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6085 | coproc = 1; |
6086 | goto ld; | |
6087 | case M_LWC2_AB: | |
6088 | s = "lwc2"; | |
bdaaa2e1 | 6089 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6090 | coproc = 1; |
6091 | goto ld; | |
6092 | case M_LWC3_AB: | |
6093 | s = "lwc3"; | |
bdaaa2e1 | 6094 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6095 | coproc = 1; |
6096 | goto ld; | |
6097 | case M_LWL_AB: | |
6098 | s = "lwl"; | |
6099 | lr = 1; | |
6100 | goto ld; | |
6101 | case M_LWR_AB: | |
6102 | s = "lwr"; | |
6103 | lr = 1; | |
6104 | goto ld; | |
6105 | case M_LDC1_AB: | |
fef14a42 | 6106 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6107 | { |
6108 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6109 | break; |
252b5132 RH |
6110 | } |
6111 | s = "ldc1"; | |
bdaaa2e1 | 6112 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6113 | coproc = 1; |
6114 | goto ld; | |
6115 | case M_LDC2_AB: | |
6116 | s = "ldc2"; | |
bdaaa2e1 | 6117 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6118 | coproc = 1; |
6119 | goto ld; | |
6120 | case M_LDC3_AB: | |
6121 | s = "ldc3"; | |
bdaaa2e1 | 6122 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6123 | coproc = 1; |
6124 | goto ld; | |
6125 | case M_LDL_AB: | |
6126 | s = "ldl"; | |
6127 | lr = 1; | |
6128 | goto ld; | |
6129 | case M_LDR_AB: | |
6130 | s = "ldr"; | |
6131 | lr = 1; | |
6132 | goto ld; | |
6133 | case M_LL_AB: | |
6134 | s = "ll"; | |
6135 | goto ld; | |
6136 | case M_LLD_AB: | |
6137 | s = "lld"; | |
6138 | goto ld; | |
6139 | case M_LWU_AB: | |
6140 | s = "lwu"; | |
6141 | ld: | |
8fc2e39e | 6142 | if (breg == treg || coproc || lr) |
252b5132 RH |
6143 | { |
6144 | tempreg = AT; | |
6145 | used_at = 1; | |
6146 | } | |
6147 | else | |
6148 | { | |
6149 | tempreg = treg; | |
252b5132 RH |
6150 | } |
6151 | goto ld_st; | |
6152 | case M_SB_AB: | |
6153 | s = "sb"; | |
6154 | goto st; | |
6155 | case M_SH_AB: | |
6156 | s = "sh"; | |
6157 | goto st; | |
6158 | case M_SW_AB: | |
6159 | s = "sw"; | |
6160 | goto st; | |
6161 | case M_SWC0_AB: | |
6162 | s = "swc0"; | |
bdaaa2e1 | 6163 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6164 | coproc = 1; |
6165 | goto st; | |
6166 | case M_SWC1_AB: | |
6167 | s = "swc1"; | |
bdaaa2e1 | 6168 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6169 | coproc = 1; |
6170 | goto st; | |
6171 | case M_SWC2_AB: | |
6172 | s = "swc2"; | |
bdaaa2e1 | 6173 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6174 | coproc = 1; |
6175 | goto st; | |
6176 | case M_SWC3_AB: | |
6177 | s = "swc3"; | |
bdaaa2e1 | 6178 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6179 | coproc = 1; |
6180 | goto st; | |
6181 | case M_SWL_AB: | |
6182 | s = "swl"; | |
6183 | goto st; | |
6184 | case M_SWR_AB: | |
6185 | s = "swr"; | |
6186 | goto st; | |
6187 | case M_SC_AB: | |
6188 | s = "sc"; | |
6189 | goto st; | |
6190 | case M_SCD_AB: | |
6191 | s = "scd"; | |
6192 | goto st; | |
d43b4baf TS |
6193 | case M_CACHE_AB: |
6194 | s = "cache"; | |
6195 | goto st; | |
252b5132 | 6196 | case M_SDC1_AB: |
fef14a42 | 6197 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6198 | { |
6199 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6200 | break; |
252b5132 RH |
6201 | } |
6202 | s = "sdc1"; | |
6203 | coproc = 1; | |
bdaaa2e1 | 6204 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6205 | goto st; |
6206 | case M_SDC2_AB: | |
6207 | s = "sdc2"; | |
bdaaa2e1 | 6208 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6209 | coproc = 1; |
6210 | goto st; | |
6211 | case M_SDC3_AB: | |
6212 | s = "sdc3"; | |
bdaaa2e1 | 6213 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6214 | coproc = 1; |
6215 | goto st; | |
6216 | case M_SDL_AB: | |
6217 | s = "sdl"; | |
6218 | goto st; | |
6219 | case M_SDR_AB: | |
6220 | s = "sdr"; | |
6221 | st: | |
8fc2e39e TS |
6222 | tempreg = AT; |
6223 | used_at = 1; | |
252b5132 | 6224 | ld_st: |
bdaaa2e1 | 6225 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6226 | if (mask == M_LWC1_AB |
6227 | || mask == M_SWC1_AB | |
6228 | || mask == M_LDC1_AB | |
6229 | || mask == M_SDC1_AB | |
6230 | || mask == M_L_DAB | |
6231 | || mask == M_S_DAB) | |
6232 | fmt = "T,o(b)"; | |
d43b4baf TS |
6233 | else if (mask == M_CACHE_AB) |
6234 | fmt = "k,o(b)"; | |
252b5132 RH |
6235 | else if (coproc) |
6236 | fmt = "E,o(b)"; | |
6237 | else | |
6238 | fmt = "t,o(b)"; | |
6239 | ||
6240 | if (offset_expr.X_op != O_constant | |
6241 | && offset_expr.X_op != O_symbol) | |
6242 | { | |
6243 | as_bad (_("expression too complex")); | |
6244 | offset_expr.X_op = O_constant; | |
6245 | } | |
6246 | ||
2051e8c4 MR |
6247 | if (HAVE_32BIT_ADDRESSES |
6248 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
6249 | { |
6250 | char value [32]; | |
6251 | ||
6252 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 6253 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 6254 | } |
2051e8c4 | 6255 | |
252b5132 RH |
6256 | /* A constant expression in PIC code can be handled just as it |
6257 | is in non PIC code. */ | |
aed1a261 RS |
6258 | if (offset_expr.X_op == O_constant) |
6259 | { | |
aed1a261 RS |
6260 | expr1.X_add_number = ((offset_expr.X_add_number + 0x8000) |
6261 | & ~(bfd_vma) 0xffff); | |
2051e8c4 | 6262 | normalize_address_expr (&expr1); |
aed1a261 RS |
6263 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); |
6264 | if (breg != 0) | |
6265 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
6266 | tempreg, tempreg, breg); | |
6267 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, tempreg); | |
6268 | } | |
6269 | else if (mips_pic == NO_PIC) | |
252b5132 RH |
6270 | { |
6271 | /* If this is a reference to a GP relative symbol, and there | |
6272 | is no base register, we want | |
cdf6fd85 | 6273 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
6274 | Otherwise, if there is no base register, we want |
6275 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6276 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6277 | If we have a constant, we need two instructions anyhow, | |
6278 | so we always use the latter form. | |
6279 | ||
6280 | If we have a base register, and this is a reference to a | |
6281 | GP relative symbol, we want | |
6282 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 6283 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
6284 | Otherwise we want |
6285 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6286 | addu $tempreg,$tempreg,$breg | |
6287 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 6288 | With a constant we always use the latter case. |
76b3015f | 6289 | |
d6bc6245 TS |
6290 | With 64bit address space and no base register and $at usable, |
6291 | we want | |
6292 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6293 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6294 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6295 | dsll32 $tempreg,0 | |
6296 | daddu $tempreg,$at | |
6297 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6298 | If we have a base register, we want | |
6299 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6300 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6301 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6302 | daddu $at,$breg | |
6303 | dsll32 $tempreg,0 | |
6304 | daddu $tempreg,$at | |
6305 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6306 | ||
6307 | Without $at we can't generate the optimal path for superscalar | |
6308 | processors here since this would require two temporary registers. | |
6309 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6310 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6311 | dsll $tempreg,16 | |
6312 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6313 | dsll $tempreg,16 | |
6314 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6315 | If we have a base register, we want | |
6316 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6317 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6318 | dsll $tempreg,16 | |
6319 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6320 | dsll $tempreg,16 | |
6321 | daddu $tempreg,$tempreg,$breg | |
6322 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 | 6323 | |
6caf9ef4 | 6324 | For GP relative symbols in 64bit address space we can use |
aed1a261 RS |
6325 | the same sequence as in 32bit address space. */ |
6326 | if (HAVE_64BIT_SYMBOLS) | |
d6bc6245 | 6327 | { |
aed1a261 | 6328 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 TS |
6329 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
6330 | { | |
6331 | relax_start (offset_expr.X_add_symbol); | |
6332 | if (breg == 0) | |
6333 | { | |
6334 | macro_build (&offset_expr, s, fmt, treg, | |
6335 | BFD_RELOC_GPREL16, mips_gp_register); | |
6336 | } | |
6337 | else | |
6338 | { | |
6339 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
6340 | tempreg, breg, mips_gp_register); | |
6341 | macro_build (&offset_expr, s, fmt, treg, | |
6342 | BFD_RELOC_GPREL16, tempreg); | |
6343 | } | |
6344 | relax_switch (); | |
6345 | } | |
d6bc6245 | 6346 | |
b8285c27 | 6347 | if (used_at == 0 && !mips_opts.noat) |
d6bc6245 | 6348 | { |
67c0d1eb RS |
6349 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
6350 | BFD_RELOC_MIPS_HIGHEST); | |
6351 | macro_build (&offset_expr, "lui", "t,u", AT, | |
6352 | BFD_RELOC_HI16_S); | |
6353 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6354 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 6355 | if (breg != 0) |
67c0d1eb RS |
6356 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
6357 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); | |
6358 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
6359 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, | |
6360 | tempreg); | |
d6bc6245 TS |
6361 | used_at = 1; |
6362 | } | |
6363 | else | |
6364 | { | |
67c0d1eb RS |
6365 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
6366 | BFD_RELOC_MIPS_HIGHEST); | |
6367 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6368 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
6369 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
6370 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6371 | tempreg, BFD_RELOC_HI16_S); | |
6372 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
d6bc6245 | 6373 | if (breg != 0) |
67c0d1eb | 6374 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 6375 | tempreg, tempreg, breg); |
67c0d1eb | 6376 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6377 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 6378 | } |
6caf9ef4 TS |
6379 | |
6380 | if (mips_relax.sequence) | |
6381 | relax_end (); | |
8fc2e39e | 6382 | break; |
d6bc6245 | 6383 | } |
256ab948 | 6384 | |
252b5132 RH |
6385 | if (breg == 0) |
6386 | { | |
67c0d1eb | 6387 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 6388 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 6389 | { |
4d7206a2 | 6390 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6391 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, |
6392 | mips_gp_register); | |
4d7206a2 | 6393 | relax_switch (); |
252b5132 | 6394 | } |
67c0d1eb RS |
6395 | macro_build_lui (&offset_expr, tempreg); |
6396 | macro_build (&offset_expr, s, fmt, treg, | |
17a2f251 | 6397 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
6398 | if (mips_relax.sequence) |
6399 | relax_end (); | |
252b5132 RH |
6400 | } |
6401 | else | |
6402 | { | |
67c0d1eb | 6403 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 6404 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 6405 | { |
4d7206a2 | 6406 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6407 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6408 | tempreg, breg, mips_gp_register); |
67c0d1eb | 6409 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6410 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 6411 | relax_switch (); |
252b5132 | 6412 | } |
67c0d1eb RS |
6413 | macro_build_lui (&offset_expr, tempreg); |
6414 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6415 | tempreg, tempreg, breg); |
67c0d1eb | 6416 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6417 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
6418 | if (mips_relax.sequence) |
6419 | relax_end (); | |
252b5132 RH |
6420 | } |
6421 | } | |
0a44bf69 | 6422 | else if (!mips_big_got) |
252b5132 | 6423 | { |
ed6fb7bd | 6424 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 6425 | |
252b5132 RH |
6426 | /* If this is a reference to an external symbol, we want |
6427 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6428 | nop | |
6429 | <op> $treg,0($tempreg) | |
6430 | Otherwise we want | |
6431 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6432 | nop | |
6433 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6434 | <op> $treg,0($tempreg) | |
f5040a92 AO |
6435 | |
6436 | For NewABI, we want | |
6437 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6438 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
6439 | ||
252b5132 RH |
6440 | If there is a base register, we add it to $tempreg before |
6441 | the <op>. If there is a constant, we stick it in the | |
6442 | <op> instruction. We don't handle constants larger than | |
6443 | 16 bits, because we have no way to load the upper 16 bits | |
6444 | (actually, we could handle them for the subset of cases | |
6445 | in which we are not using $at). */ | |
6446 | assert (offset_expr.X_op == O_symbol); | |
f5040a92 AO |
6447 | if (HAVE_NEWABI) |
6448 | { | |
67c0d1eb RS |
6449 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6450 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6451 | if (breg != 0) |
67c0d1eb | 6452 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6453 | tempreg, tempreg, breg); |
67c0d1eb | 6454 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6455 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
6456 | break; |
6457 | } | |
252b5132 RH |
6458 | expr1.X_add_number = offset_expr.X_add_number; |
6459 | offset_expr.X_add_number = 0; | |
6460 | if (expr1.X_add_number < -0x8000 | |
6461 | || expr1.X_add_number >= 0x8000) | |
6462 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
6463 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6464 | lw_reloc_type, mips_gp_register); | |
269137b2 | 6465 | load_delay_nop (); |
4d7206a2 RS |
6466 | relax_start (offset_expr.X_add_symbol); |
6467 | relax_switch (); | |
67c0d1eb RS |
6468 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6469 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 6470 | relax_end (); |
252b5132 | 6471 | if (breg != 0) |
67c0d1eb | 6472 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6473 | tempreg, tempreg, breg); |
67c0d1eb | 6474 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6475 | } |
0a44bf69 | 6476 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 6477 | { |
67c0d1eb | 6478 | int gpdelay; |
252b5132 RH |
6479 | |
6480 | /* If this is a reference to an external symbol, we want | |
6481 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6482 | addu $tempreg,$tempreg,$gp | |
6483 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6484 | <op> $treg,0($tempreg) | |
6485 | Otherwise we want | |
6486 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6487 | nop | |
6488 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6489 | <op> $treg,0($tempreg) | |
6490 | If there is a base register, we add it to $tempreg before | |
6491 | the <op>. If there is a constant, we stick it in the | |
6492 | <op> instruction. We don't handle constants larger than | |
6493 | 16 bits, because we have no way to load the upper 16 bits | |
6494 | (actually, we could handle them for the subset of cases | |
f5040a92 | 6495 | in which we are not using $at). */ |
252b5132 RH |
6496 | assert (offset_expr.X_op == O_symbol); |
6497 | expr1.X_add_number = offset_expr.X_add_number; | |
6498 | offset_expr.X_add_number = 0; | |
6499 | if (expr1.X_add_number < -0x8000 | |
6500 | || expr1.X_add_number >= 0x8000) | |
6501 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6502 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 6503 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6504 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6505 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6506 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6507 | mips_gp_register); | |
6508 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6509 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 6510 | relax_switch (); |
67c0d1eb RS |
6511 | if (gpdelay) |
6512 | macro_build (NULL, "nop", ""); | |
6513 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6514 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6515 | load_delay_nop (); |
67c0d1eb RS |
6516 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6517 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
6518 | relax_end (); |
6519 | ||
252b5132 | 6520 | if (breg != 0) |
67c0d1eb | 6521 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6522 | tempreg, tempreg, breg); |
67c0d1eb | 6523 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6524 | } |
0a44bf69 | 6525 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 6526 | { |
f5040a92 AO |
6527 | /* If this is a reference to an external symbol, we want |
6528 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6529 | add $tempreg,$tempreg,$gp | |
6530 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6531 | <op> $treg,<ofst>($tempreg) | |
6532 | Otherwise, for local symbols, we want: | |
6533 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6534 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
6535 | assert (offset_expr.X_op == O_symbol); | |
4d7206a2 | 6536 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
6537 | offset_expr.X_add_number = 0; |
6538 | if (expr1.X_add_number < -0x8000 | |
6539 | || expr1.X_add_number >= 0x8000) | |
6540 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 6541 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6542 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6543 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6544 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6545 | mips_gp_register); | |
6546 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6547 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 6548 | if (breg != 0) |
67c0d1eb | 6549 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6550 | tempreg, tempreg, breg); |
67c0d1eb | 6551 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
684022ea | 6552 | |
4d7206a2 | 6553 | relax_switch (); |
f5040a92 | 6554 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
6555 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6556 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6557 | if (breg != 0) |
67c0d1eb | 6558 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6559 | tempreg, tempreg, breg); |
67c0d1eb | 6560 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6561 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 6562 | relax_end (); |
f5040a92 | 6563 | } |
252b5132 RH |
6564 | else |
6565 | abort (); | |
6566 | ||
252b5132 RH |
6567 | break; |
6568 | ||
6569 | case M_LI: | |
6570 | case M_LI_S: | |
67c0d1eb | 6571 | load_register (treg, &imm_expr, 0); |
8fc2e39e | 6572 | break; |
252b5132 RH |
6573 | |
6574 | case M_DLI: | |
67c0d1eb | 6575 | load_register (treg, &imm_expr, 1); |
8fc2e39e | 6576 | break; |
252b5132 RH |
6577 | |
6578 | case M_LI_SS: | |
6579 | if (imm_expr.X_op == O_constant) | |
6580 | { | |
8fc2e39e | 6581 | used_at = 1; |
67c0d1eb RS |
6582 | load_register (AT, &imm_expr, 0); |
6583 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6584 | break; |
6585 | } | |
6586 | else | |
6587 | { | |
6588 | assert (offset_expr.X_op == O_symbol | |
6589 | && strcmp (segment_name (S_GET_SEGMENT | |
6590 | (offset_expr.X_add_symbol)), | |
6591 | ".lit4") == 0 | |
6592 | && offset_expr.X_add_number == 0); | |
67c0d1eb | 6593 | macro_build (&offset_expr, "lwc1", "T,o(b)", treg, |
17a2f251 | 6594 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 6595 | break; |
252b5132 RH |
6596 | } |
6597 | ||
6598 | case M_LI_D: | |
ca4e0257 RS |
6599 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
6600 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
6601 | order 32 bits of the value and the low order 32 bits are either | |
6602 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
6603 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6604 | { | |
ca4e0257 | 6605 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 6606 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
6607 | else |
6608 | { | |
6609 | int hreg, lreg; | |
6610 | ||
6611 | if (target_big_endian) | |
6612 | { | |
6613 | hreg = treg; | |
6614 | lreg = treg + 1; | |
6615 | } | |
6616 | else | |
6617 | { | |
6618 | hreg = treg + 1; | |
6619 | lreg = treg; | |
6620 | } | |
6621 | ||
6622 | if (hreg <= 31) | |
67c0d1eb | 6623 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
6624 | if (lreg <= 31) |
6625 | { | |
6626 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 6627 | move_register (lreg, 0); |
252b5132 RH |
6628 | else |
6629 | { | |
6630 | assert (offset_expr.X_op == O_constant); | |
67c0d1eb | 6631 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
6632 | } |
6633 | } | |
6634 | } | |
8fc2e39e | 6635 | break; |
252b5132 RH |
6636 | } |
6637 | ||
6638 | /* We know that sym is in the .rdata section. First we get the | |
6639 | upper 16 bits of the address. */ | |
6640 | if (mips_pic == NO_PIC) | |
6641 | { | |
67c0d1eb | 6642 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 6643 | used_at = 1; |
252b5132 | 6644 | } |
0a44bf69 | 6645 | else |
252b5132 | 6646 | { |
67c0d1eb RS |
6647 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6648 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 6649 | used_at = 1; |
252b5132 | 6650 | } |
bdaaa2e1 | 6651 | |
252b5132 | 6652 | /* Now we load the register(s). */ |
ca4e0257 | 6653 | if (HAVE_64BIT_GPRS) |
8fc2e39e TS |
6654 | { |
6655 | used_at = 1; | |
6656 | macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
6657 | } | |
252b5132 RH |
6658 | else |
6659 | { | |
8fc2e39e | 6660 | used_at = 1; |
67c0d1eb | 6661 | macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
f9419b05 | 6662 | if (treg != RA) |
252b5132 RH |
6663 | { |
6664 | /* FIXME: How in the world do we deal with the possible | |
6665 | overflow here? */ | |
6666 | offset_expr.X_add_number += 4; | |
67c0d1eb | 6667 | macro_build (&offset_expr, "lw", "t,o(b)", |
17a2f251 | 6668 | treg + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
6669 | } |
6670 | } | |
252b5132 RH |
6671 | break; |
6672 | ||
6673 | case M_LI_DD: | |
ca4e0257 RS |
6674 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
6675 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
6676 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
6677 | the value and the low order 32 bits are either zero or in | |
6678 | OFFSET_EXPR. */ | |
252b5132 RH |
6679 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6680 | { | |
8fc2e39e | 6681 | used_at = 1; |
67c0d1eb | 6682 | load_register (AT, &imm_expr, HAVE_64BIT_FPRS); |
ca4e0257 RS |
6683 | if (HAVE_64BIT_FPRS) |
6684 | { | |
6685 | assert (HAVE_64BIT_GPRS); | |
67c0d1eb | 6686 | macro_build (NULL, "dmtc1", "t,S", AT, treg); |
ca4e0257 | 6687 | } |
252b5132 RH |
6688 | else |
6689 | { | |
67c0d1eb | 6690 | macro_build (NULL, "mtc1", "t,G", AT, treg + 1); |
252b5132 | 6691 | if (offset_expr.X_op == O_absent) |
67c0d1eb | 6692 | macro_build (NULL, "mtc1", "t,G", 0, treg); |
252b5132 RH |
6693 | else |
6694 | { | |
6695 | assert (offset_expr.X_op == O_constant); | |
67c0d1eb RS |
6696 | load_register (AT, &offset_expr, 0); |
6697 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6698 | } |
6699 | } | |
6700 | break; | |
6701 | } | |
6702 | ||
6703 | assert (offset_expr.X_op == O_symbol | |
6704 | && offset_expr.X_add_number == 0); | |
6705 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
6706 | if (strcmp (s, ".lit8") == 0) | |
6707 | { | |
e7af610e | 6708 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6709 | { |
67c0d1eb | 6710 | macro_build (&offset_expr, "ldc1", "T,o(b)", treg, |
17a2f251 | 6711 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 6712 | break; |
252b5132 | 6713 | } |
c9914766 | 6714 | breg = mips_gp_register; |
252b5132 RH |
6715 | r = BFD_RELOC_MIPS_LITERAL; |
6716 | goto dob; | |
6717 | } | |
6718 | else | |
6719 | { | |
6720 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); | |
8fc2e39e | 6721 | used_at = 1; |
0a44bf69 | 6722 | if (mips_pic != NO_PIC) |
67c0d1eb RS |
6723 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6724 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
6725 | else |
6726 | { | |
6727 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 6728 | macro_build_lui (&offset_expr, AT); |
252b5132 | 6729 | } |
bdaaa2e1 | 6730 | |
e7af610e | 6731 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6732 | { |
67c0d1eb RS |
6733 | macro_build (&offset_expr, "ldc1", "T,o(b)", |
6734 | treg, BFD_RELOC_LO16, AT); | |
252b5132 RH |
6735 | break; |
6736 | } | |
6737 | breg = AT; | |
6738 | r = BFD_RELOC_LO16; | |
6739 | goto dob; | |
6740 | } | |
6741 | ||
6742 | case M_L_DOB: | |
fef14a42 | 6743 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6744 | { |
6745 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6746 | break; |
252b5132 RH |
6747 | } |
6748 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6749 | to adjust when loading from memory. */ | |
6750 | r = BFD_RELOC_LO16; | |
6751 | dob: | |
e7af610e | 6752 | assert (mips_opts.isa == ISA_MIPS1); |
67c0d1eb | 6753 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 6754 | target_big_endian ? treg + 1 : treg, r, breg); |
252b5132 RH |
6755 | /* FIXME: A possible overflow which I don't know how to deal |
6756 | with. */ | |
6757 | offset_expr.X_add_number += 4; | |
67c0d1eb | 6758 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 6759 | target_big_endian ? treg : treg + 1, r, breg); |
252b5132 RH |
6760 | break; |
6761 | ||
6762 | case M_L_DAB: | |
6763 | /* | |
6764 | * The MIPS assembler seems to check for X_add_number not | |
6765 | * being double aligned and generating: | |
6766 | * lui at,%hi(foo+1) | |
6767 | * addu at,at,v1 | |
6768 | * addiu at,at,%lo(foo+1) | |
6769 | * lwc1 f2,0(at) | |
6770 | * lwc1 f3,4(at) | |
6771 | * But, the resulting address is the same after relocation so why | |
6772 | * generate the extra instruction? | |
6773 | */ | |
fef14a42 | 6774 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6775 | { |
6776 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6777 | break; |
252b5132 | 6778 | } |
bdaaa2e1 | 6779 | /* Itbl support may require additional care here. */ |
252b5132 | 6780 | coproc = 1; |
e7af610e | 6781 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6782 | { |
6783 | s = "ldc1"; | |
6784 | goto ld; | |
6785 | } | |
6786 | ||
6787 | s = "lwc1"; | |
6788 | fmt = "T,o(b)"; | |
6789 | goto ldd_std; | |
6790 | ||
6791 | case M_S_DAB: | |
fef14a42 | 6792 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6793 | { |
6794 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6795 | break; |
252b5132 RH |
6796 | } |
6797 | ||
e7af610e | 6798 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6799 | { |
6800 | s = "sdc1"; | |
6801 | goto st; | |
6802 | } | |
6803 | ||
6804 | s = "swc1"; | |
6805 | fmt = "T,o(b)"; | |
bdaaa2e1 | 6806 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6807 | coproc = 1; |
6808 | goto ldd_std; | |
6809 | ||
6810 | case M_LD_AB: | |
ca4e0257 | 6811 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6812 | { |
6813 | s = "ld"; | |
6814 | goto ld; | |
6815 | } | |
6816 | ||
6817 | s = "lw"; | |
6818 | fmt = "t,o(b)"; | |
6819 | goto ldd_std; | |
6820 | ||
6821 | case M_SD_AB: | |
ca4e0257 | 6822 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6823 | { |
6824 | s = "sd"; | |
6825 | goto st; | |
6826 | } | |
6827 | ||
6828 | s = "sw"; | |
6829 | fmt = "t,o(b)"; | |
6830 | ||
6831 | ldd_std: | |
6832 | if (offset_expr.X_op != O_symbol | |
6833 | && offset_expr.X_op != O_constant) | |
6834 | { | |
6835 | as_bad (_("expression too complex")); | |
6836 | offset_expr.X_op = O_constant; | |
6837 | } | |
6838 | ||
2051e8c4 MR |
6839 | if (HAVE_32BIT_ADDRESSES |
6840 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
6841 | { |
6842 | char value [32]; | |
6843 | ||
6844 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 6845 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 6846 | } |
2051e8c4 | 6847 | |
252b5132 RH |
6848 | /* Even on a big endian machine $fn comes before $fn+1. We have |
6849 | to adjust when loading from memory. We set coproc if we must | |
6850 | load $fn+1 first. */ | |
bdaaa2e1 | 6851 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6852 | if (! target_big_endian) |
6853 | coproc = 0; | |
6854 | ||
6855 | if (mips_pic == NO_PIC | |
6856 | || offset_expr.X_op == O_constant) | |
6857 | { | |
6858 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 TS |
6859 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
6860 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6861 | If we have a base register, we use this |
6862 | addu $at,$breg,$gp | |
cdf6fd85 TS |
6863 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
6864 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6865 | If this is not a GP relative symbol, we want |
6866 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6867 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6868 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6869 | If there is a base register, we add it to $at after the | |
6870 | lui instruction. If there is a constant, we always use | |
6871 | the last case. */ | |
39a59cf8 MR |
6872 | if (offset_expr.X_op == O_symbol |
6873 | && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 6874 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 6875 | { |
4d7206a2 | 6876 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
6877 | if (breg == 0) |
6878 | { | |
c9914766 | 6879 | tempreg = mips_gp_register; |
252b5132 RH |
6880 | } |
6881 | else | |
6882 | { | |
67c0d1eb | 6883 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6884 | AT, breg, mips_gp_register); |
252b5132 | 6885 | tempreg = AT; |
252b5132 RH |
6886 | used_at = 1; |
6887 | } | |
6888 | ||
beae10d5 | 6889 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6890 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6891 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6892 | offset_expr.X_add_number += 4; |
6893 | ||
6894 | /* Set mips_optimize to 2 to avoid inserting an | |
6895 | undesired nop. */ | |
6896 | hold_mips_optimize = mips_optimize; | |
6897 | mips_optimize = 2; | |
beae10d5 | 6898 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6899 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6900 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6901 | mips_optimize = hold_mips_optimize; |
6902 | ||
4d7206a2 | 6903 | relax_switch (); |
252b5132 RH |
6904 | |
6905 | /* We just generated two relocs. When tc_gen_reloc | |
6906 | handles this case, it will skip the first reloc and | |
6907 | handle the second. The second reloc already has an | |
6908 | extra addend of 4, which we added above. We must | |
6909 | subtract it out, and then subtract another 4 to make | |
6910 | the first reloc come out right. The second reloc | |
6911 | will come out right because we are going to add 4 to | |
6912 | offset_expr when we build its instruction below. | |
6913 | ||
6914 | If we have a symbol, then we don't want to include | |
6915 | the offset, because it will wind up being included | |
6916 | when we generate the reloc. */ | |
6917 | ||
6918 | if (offset_expr.X_op == O_constant) | |
6919 | offset_expr.X_add_number -= 8; | |
6920 | else | |
6921 | { | |
6922 | offset_expr.X_add_number = -4; | |
6923 | offset_expr.X_op = O_constant; | |
6924 | } | |
6925 | } | |
8fc2e39e | 6926 | used_at = 1; |
67c0d1eb | 6927 | macro_build_lui (&offset_expr, AT); |
252b5132 | 6928 | if (breg != 0) |
67c0d1eb | 6929 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6930 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6931 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6932 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6933 | /* FIXME: How do we handle overflow here? */ |
6934 | offset_expr.X_add_number += 4; | |
beae10d5 | 6935 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6936 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6937 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
6938 | if (mips_relax.sequence) |
6939 | relax_end (); | |
bdaaa2e1 | 6940 | } |
0a44bf69 | 6941 | else if (!mips_big_got) |
252b5132 | 6942 | { |
252b5132 RH |
6943 | /* If this is a reference to an external symbol, we want |
6944 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6945 | nop | |
6946 | <op> $treg,0($at) | |
6947 | <op> $treg+1,4($at) | |
6948 | Otherwise we want | |
6949 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6950 | nop | |
6951 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6952 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6953 | If there is a base register we add it to $at before the | |
6954 | lwc1 instructions. If there is a constant we include it | |
6955 | in the lwc1 instructions. */ | |
6956 | used_at = 1; | |
6957 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
6958 | if (expr1.X_add_number < -0x8000 |
6959 | || expr1.X_add_number >= 0x8000 - 4) | |
6960 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6961 | load_got_offset (AT, &offset_expr); |
269137b2 | 6962 | load_delay_nop (); |
252b5132 | 6963 | if (breg != 0) |
67c0d1eb | 6964 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
6965 | |
6966 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6967 | nop. */ | |
6968 | hold_mips_optimize = mips_optimize; | |
6969 | mips_optimize = 2; | |
4d7206a2 | 6970 | |
beae10d5 | 6971 | /* Itbl support may require additional care here. */ |
4d7206a2 | 6972 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6973 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
6974 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6975 | expr1.X_add_number += 4; |
67c0d1eb RS |
6976 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
6977 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6978 | relax_switch (); |
67c0d1eb RS |
6979 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
6980 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6981 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
6982 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
6983 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6984 | relax_end (); |
252b5132 | 6985 | |
4d7206a2 | 6986 | mips_optimize = hold_mips_optimize; |
252b5132 | 6987 | } |
0a44bf69 | 6988 | else if (mips_big_got) |
252b5132 | 6989 | { |
67c0d1eb | 6990 | int gpdelay; |
252b5132 RH |
6991 | |
6992 | /* If this is a reference to an external symbol, we want | |
6993 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6994 | addu $at,$at,$gp | |
6995 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
6996 | nop | |
6997 | <op> $treg,0($at) | |
6998 | <op> $treg+1,4($at) | |
6999 | Otherwise we want | |
7000 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7001 | nop | |
7002 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
7003 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
7004 | If there is a base register we add it to $at before the | |
7005 | lwc1 instructions. If there is a constant we include it | |
7006 | in the lwc1 instructions. */ | |
7007 | used_at = 1; | |
7008 | expr1.X_add_number = offset_expr.X_add_number; | |
7009 | offset_expr.X_add_number = 0; | |
7010 | if (expr1.X_add_number < -0x8000 | |
7011 | || expr1.X_add_number >= 0x8000 - 4) | |
7012 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 7013 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 7014 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7015 | macro_build (&offset_expr, "lui", "t,u", |
7016 | AT, BFD_RELOC_MIPS_GOT_HI16); | |
7017 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 7018 | AT, AT, mips_gp_register); |
67c0d1eb | 7019 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 7020 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 7021 | load_delay_nop (); |
252b5132 | 7022 | if (breg != 0) |
67c0d1eb | 7023 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 7024 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7025 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 7026 | BFD_RELOC_LO16, AT); |
252b5132 RH |
7027 | expr1.X_add_number += 4; |
7028 | ||
7029 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
7030 | nop. */ | |
7031 | hold_mips_optimize = mips_optimize; | |
7032 | mips_optimize = 2; | |
beae10d5 | 7033 | /* Itbl support may require additional care here. */ |
67c0d1eb | 7034 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 7035 | BFD_RELOC_LO16, AT); |
252b5132 RH |
7036 | mips_optimize = hold_mips_optimize; |
7037 | expr1.X_add_number -= 4; | |
7038 | ||
4d7206a2 RS |
7039 | relax_switch (); |
7040 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
7041 | if (gpdelay) |
7042 | macro_build (NULL, "nop", ""); | |
7043 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
7044 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 7045 | load_delay_nop (); |
252b5132 | 7046 | if (breg != 0) |
67c0d1eb | 7047 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 7048 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
7049 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
7050 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7051 | offset_expr.X_add_number += 4; |
252b5132 RH |
7052 | |
7053 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
7054 | nop. */ | |
7055 | hold_mips_optimize = mips_optimize; | |
7056 | mips_optimize = 2; | |
beae10d5 | 7057 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
7058 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
7059 | BFD_RELOC_LO16, AT); | |
252b5132 | 7060 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 7061 | relax_end (); |
252b5132 | 7062 | } |
252b5132 RH |
7063 | else |
7064 | abort (); | |
7065 | ||
252b5132 RH |
7066 | break; |
7067 | ||
7068 | case M_LD_OB: | |
7069 | s = "lw"; | |
7070 | goto sd_ob; | |
7071 | case M_SD_OB: | |
7072 | s = "sw"; | |
7073 | sd_ob: | |
ca4e0257 | 7074 | assert (HAVE_32BIT_ADDRESSES); |
67c0d1eb | 7075 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 | 7076 | offset_expr.X_add_number += 4; |
67c0d1eb | 7077 | macro_build (&offset_expr, s, "t,o(b)", treg + 1, BFD_RELOC_LO16, breg); |
8fc2e39e | 7078 | break; |
252b5132 RH |
7079 | |
7080 | /* New code added to support COPZ instructions. | |
7081 | This code builds table entries out of the macros in mip_opcodes. | |
7082 | R4000 uses interlocks to handle coproc delays. | |
7083 | Other chips (like the R3000) require nops to be inserted for delays. | |
7084 | ||
f72c8c98 | 7085 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
7086 | In order to fill delay slots for non-interlocked chips, |
7087 | we must have a way to specify delays based on the coprocessor. | |
7088 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
7089 | What are the side-effects of the cop instruction? | |
7090 | What cache support might we have and what are its effects? | |
7091 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 7092 | What registers are read/set/modified? |
252b5132 RH |
7093 | |
7094 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 7095 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
7096 | |
7097 | case M_COP0: | |
7098 | s = "c0"; | |
7099 | goto copz; | |
7100 | case M_COP1: | |
7101 | s = "c1"; | |
7102 | goto copz; | |
7103 | case M_COP2: | |
7104 | s = "c2"; | |
7105 | goto copz; | |
7106 | case M_COP3: | |
7107 | s = "c3"; | |
7108 | copz: | |
7109 | /* For now we just do C (same as Cz). The parameter will be | |
7110 | stored in insn_opcode by mips_ip. */ | |
67c0d1eb | 7111 | macro_build (NULL, s, "C", ip->insn_opcode); |
8fc2e39e | 7112 | break; |
252b5132 | 7113 | |
ea1fb5dc | 7114 | case M_MOVE: |
67c0d1eb | 7115 | move_register (dreg, sreg); |
8fc2e39e | 7116 | break; |
ea1fb5dc | 7117 | |
252b5132 RH |
7118 | #ifdef LOSING_COMPILER |
7119 | default: | |
7120 | /* Try and see if this is a new itbl instruction. | |
7121 | This code builds table entries out of the macros in mip_opcodes. | |
7122 | FIXME: For now we just assemble the expression and pass it's | |
7123 | value along as a 32-bit immediate. | |
bdaaa2e1 | 7124 | We may want to have the assembler assemble this value, |
252b5132 RH |
7125 | so that we gain the assembler's knowledge of delay slots, |
7126 | symbols, etc. | |
7127 | Would it be more efficient to use mask (id) here? */ | |
bdaaa2e1 | 7128 | if (itbl_have_entries |
252b5132 | 7129 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
beae10d5 | 7130 | { |
252b5132 RH |
7131 | s = ip->insn_mo->name; |
7132 | s2 = "cop3"; | |
7133 | coproc = ITBL_DECODE_PNUM (immed_expr);; | |
67c0d1eb | 7134 | macro_build (&immed_expr, s, "C"); |
8fc2e39e | 7135 | break; |
beae10d5 | 7136 | } |
252b5132 | 7137 | macro2 (ip); |
8fc2e39e | 7138 | break; |
252b5132 | 7139 | } |
8fc2e39e TS |
7140 | if (mips_opts.noat && used_at) |
7141 | as_bad (_("Macro used $at after \".set noat\"")); | |
252b5132 | 7142 | } |
bdaaa2e1 | 7143 | |
252b5132 | 7144 | static void |
17a2f251 | 7145 | macro2 (struct mips_cl_insn *ip) |
252b5132 | 7146 | { |
3994f87e | 7147 | int treg, sreg, dreg, breg; |
252b5132 RH |
7148 | int tempreg; |
7149 | int mask; | |
252b5132 RH |
7150 | int used_at; |
7151 | expressionS expr1; | |
7152 | const char *s; | |
7153 | const char *s2; | |
7154 | const char *fmt; | |
7155 | int likely = 0; | |
7156 | int dbl = 0; | |
7157 | int coproc = 0; | |
7158 | int lr = 0; | |
7159 | int imm = 0; | |
7160 | int off; | |
7161 | offsetT maxnum; | |
7162 | bfd_reloc_code_real_type r; | |
bdaaa2e1 | 7163 | |
252b5132 RH |
7164 | treg = (ip->insn_opcode >> 16) & 0x1f; |
7165 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
7166 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
7167 | mask = ip->insn_mo->mask; | |
bdaaa2e1 | 7168 | |
252b5132 RH |
7169 | expr1.X_op = O_constant; |
7170 | expr1.X_op_symbol = NULL; | |
7171 | expr1.X_add_symbol = NULL; | |
7172 | expr1.X_add_number = 1; | |
bdaaa2e1 | 7173 | |
252b5132 RH |
7174 | switch (mask) |
7175 | { | |
7176 | #endif /* LOSING_COMPILER */ | |
7177 | ||
7178 | case M_DMUL: | |
7179 | dbl = 1; | |
7180 | case M_MUL: | |
67c0d1eb RS |
7181 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg); |
7182 | macro_build (NULL, "mflo", "d", dreg); | |
8fc2e39e | 7183 | break; |
252b5132 RH |
7184 | |
7185 | case M_DMUL_I: | |
7186 | dbl = 1; | |
7187 | case M_MUL_I: | |
7188 | /* The MIPS assembler some times generates shifts and adds. I'm | |
7189 | not trying to be that fancy. GCC should do this for us | |
7190 | anyway. */ | |
8fc2e39e | 7191 | used_at = 1; |
67c0d1eb RS |
7192 | load_register (AT, &imm_expr, dbl); |
7193 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT); | |
7194 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 RH |
7195 | break; |
7196 | ||
7197 | case M_DMULO_I: | |
7198 | dbl = 1; | |
7199 | case M_MULO_I: | |
7200 | imm = 1; | |
7201 | goto do_mulo; | |
7202 | ||
7203 | case M_DMULO: | |
7204 | dbl = 1; | |
7205 | case M_MULO: | |
7206 | do_mulo: | |
7d10b47d | 7207 | start_noreorder (); |
8fc2e39e | 7208 | used_at = 1; |
252b5132 | 7209 | if (imm) |
67c0d1eb RS |
7210 | load_register (AT, &imm_expr, dbl); |
7211 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); | |
7212 | macro_build (NULL, "mflo", "d", dreg); | |
7213 | macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA); | |
7214 | macro_build (NULL, "mfhi", "d", AT); | |
252b5132 | 7215 | if (mips_trap) |
67c0d1eb | 7216 | macro_build (NULL, "tne", "s,t,q", dreg, AT, 6); |
252b5132 RH |
7217 | else |
7218 | { | |
7219 | expr1.X_add_number = 8; | |
67c0d1eb RS |
7220 | macro_build (&expr1, "beq", "s,t,p", dreg, AT); |
7221 | macro_build (NULL, "nop", "", 0); | |
7222 | macro_build (NULL, "break", "c", 6); | |
252b5132 | 7223 | } |
7d10b47d | 7224 | end_noreorder (); |
67c0d1eb | 7225 | macro_build (NULL, "mflo", "d", dreg); |
252b5132 RH |
7226 | break; |
7227 | ||
7228 | case M_DMULOU_I: | |
7229 | dbl = 1; | |
7230 | case M_MULOU_I: | |
7231 | imm = 1; | |
7232 | goto do_mulou; | |
7233 | ||
7234 | case M_DMULOU: | |
7235 | dbl = 1; | |
7236 | case M_MULOU: | |
7237 | do_mulou: | |
7d10b47d | 7238 | start_noreorder (); |
8fc2e39e | 7239 | used_at = 1; |
252b5132 | 7240 | if (imm) |
67c0d1eb RS |
7241 | load_register (AT, &imm_expr, dbl); |
7242 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
17a2f251 | 7243 | sreg, imm ? AT : treg); |
67c0d1eb RS |
7244 | macro_build (NULL, "mfhi", "d", AT); |
7245 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 | 7246 | if (mips_trap) |
67c0d1eb | 7247 | macro_build (NULL, "tne", "s,t,q", AT, 0, 6); |
252b5132 RH |
7248 | else |
7249 | { | |
7250 | expr1.X_add_number = 8; | |
67c0d1eb RS |
7251 | macro_build (&expr1, "beq", "s,t,p", AT, 0); |
7252 | macro_build (NULL, "nop", "", 0); | |
7253 | macro_build (NULL, "break", "c", 6); | |
252b5132 | 7254 | } |
7d10b47d | 7255 | end_noreorder (); |
252b5132 RH |
7256 | break; |
7257 | ||
771c7ce4 | 7258 | case M_DROL: |
fef14a42 | 7259 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
7260 | { |
7261 | if (dreg == sreg) | |
7262 | { | |
7263 | tempreg = AT; | |
7264 | used_at = 1; | |
7265 | } | |
7266 | else | |
7267 | { | |
7268 | tempreg = dreg; | |
82dd0097 | 7269 | } |
67c0d1eb RS |
7270 | macro_build (NULL, "dnegu", "d,w", tempreg, treg); |
7271 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 7272 | break; |
82dd0097 | 7273 | } |
8fc2e39e | 7274 | used_at = 1; |
67c0d1eb RS |
7275 | macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); |
7276 | macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT); | |
7277 | macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg); | |
7278 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7279 | break; |
7280 | ||
252b5132 | 7281 | case M_ROL: |
fef14a42 | 7282 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 CD |
7283 | { |
7284 | if (dreg == sreg) | |
7285 | { | |
7286 | tempreg = AT; | |
7287 | used_at = 1; | |
7288 | } | |
7289 | else | |
7290 | { | |
7291 | tempreg = dreg; | |
82dd0097 | 7292 | } |
67c0d1eb RS |
7293 | macro_build (NULL, "negu", "d,w", tempreg, treg); |
7294 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 7295 | break; |
82dd0097 | 7296 | } |
8fc2e39e | 7297 | used_at = 1; |
67c0d1eb RS |
7298 | macro_build (NULL, "subu", "d,v,t", AT, 0, treg); |
7299 | macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT); | |
7300 | macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg); | |
7301 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7302 | break; |
7303 | ||
771c7ce4 TS |
7304 | case M_DROL_I: |
7305 | { | |
7306 | unsigned int rot; | |
82dd0097 | 7307 | char *l, *r; |
771c7ce4 TS |
7308 | |
7309 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7310 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7311 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 7312 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
7313 | { |
7314 | rot = (64 - rot) & 0x3f; | |
7315 | if (rot >= 32) | |
67c0d1eb | 7316 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
60b63b72 | 7317 | else |
67c0d1eb | 7318 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7319 | break; |
60b63b72 | 7320 | } |
483fc7cd | 7321 | if (rot == 0) |
483fc7cd | 7322 | { |
67c0d1eb | 7323 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7324 | break; |
483fc7cd | 7325 | } |
82dd0097 CD |
7326 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
7327 | r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; | |
7328 | rot &= 0x1f; | |
8fc2e39e | 7329 | used_at = 1; |
67c0d1eb RS |
7330 | macro_build (NULL, l, "d,w,<", AT, sreg, rot); |
7331 | macro_build (NULL, r, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7332 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7333 | } |
7334 | break; | |
7335 | ||
252b5132 | 7336 | case M_ROL_I: |
771c7ce4 TS |
7337 | { |
7338 | unsigned int rot; | |
7339 | ||
7340 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7341 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7342 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 7343 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 7344 | { |
67c0d1eb | 7345 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f); |
8fc2e39e | 7346 | break; |
60b63b72 | 7347 | } |
483fc7cd | 7348 | if (rot == 0) |
483fc7cd | 7349 | { |
67c0d1eb | 7350 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7351 | break; |
483fc7cd | 7352 | } |
8fc2e39e | 7353 | used_at = 1; |
67c0d1eb RS |
7354 | macro_build (NULL, "sll", "d,w,<", AT, sreg, rot); |
7355 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7356 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7357 | } |
7358 | break; | |
7359 | ||
7360 | case M_DROR: | |
fef14a42 | 7361 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 7362 | { |
67c0d1eb | 7363 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 7364 | break; |
82dd0097 | 7365 | } |
8fc2e39e | 7366 | used_at = 1; |
67c0d1eb RS |
7367 | macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); |
7368 | macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT); | |
7369 | macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg); | |
7370 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7371 | break; |
7372 | ||
7373 | case M_ROR: | |
fef14a42 | 7374 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7375 | { |
67c0d1eb | 7376 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 7377 | break; |
82dd0097 | 7378 | } |
8fc2e39e | 7379 | used_at = 1; |
67c0d1eb RS |
7380 | macro_build (NULL, "subu", "d,v,t", AT, 0, treg); |
7381 | macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT); | |
7382 | macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg); | |
7383 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7384 | break; |
7385 | ||
771c7ce4 TS |
7386 | case M_DROR_I: |
7387 | { | |
7388 | unsigned int rot; | |
82dd0097 | 7389 | char *l, *r; |
771c7ce4 TS |
7390 | |
7391 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7392 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7393 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 7394 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
7395 | { |
7396 | if (rot >= 32) | |
67c0d1eb | 7397 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
82dd0097 | 7398 | else |
67c0d1eb | 7399 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7400 | break; |
82dd0097 | 7401 | } |
483fc7cd | 7402 | if (rot == 0) |
483fc7cd | 7403 | { |
67c0d1eb | 7404 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7405 | break; |
483fc7cd | 7406 | } |
82dd0097 CD |
7407 | r = (rot < 0x20) ? "dsrl" : "dsrl32"; |
7408 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; | |
7409 | rot &= 0x1f; | |
8fc2e39e | 7410 | used_at = 1; |
67c0d1eb RS |
7411 | macro_build (NULL, r, "d,w,<", AT, sreg, rot); |
7412 | macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7413 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7414 | } |
7415 | break; | |
7416 | ||
252b5132 | 7417 | case M_ROR_I: |
771c7ce4 TS |
7418 | { |
7419 | unsigned int rot; | |
7420 | ||
7421 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7422 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7423 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 7424 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7425 | { |
67c0d1eb | 7426 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7427 | break; |
82dd0097 | 7428 | } |
483fc7cd | 7429 | if (rot == 0) |
483fc7cd | 7430 | { |
67c0d1eb | 7431 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7432 | break; |
483fc7cd | 7433 | } |
8fc2e39e | 7434 | used_at = 1; |
67c0d1eb RS |
7435 | macro_build (NULL, "srl", "d,w,<", AT, sreg, rot); |
7436 | macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7437 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 | 7438 | } |
252b5132 RH |
7439 | break; |
7440 | ||
7441 | case M_S_DOB: | |
fef14a42 | 7442 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
7443 | { |
7444 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 7445 | break; |
252b5132 | 7446 | } |
e7af610e | 7447 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
7448 | /* Even on a big endian machine $fn comes before $fn+1. We have |
7449 | to adjust when storing to memory. */ | |
67c0d1eb RS |
7450 | macro_build (&offset_expr, "swc1", "T,o(b)", |
7451 | target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg); | |
252b5132 | 7452 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
7453 | macro_build (&offset_expr, "swc1", "T,o(b)", |
7454 | target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg); | |
8fc2e39e | 7455 | break; |
252b5132 RH |
7456 | |
7457 | case M_SEQ: | |
7458 | if (sreg == 0) | |
67c0d1eb | 7459 | macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16); |
252b5132 | 7460 | else if (treg == 0) |
67c0d1eb | 7461 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7462 | else |
7463 | { | |
67c0d1eb RS |
7464 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7465 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 | 7466 | } |
8fc2e39e | 7467 | break; |
252b5132 RH |
7468 | |
7469 | case M_SEQ_I: | |
7470 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7471 | { | |
67c0d1eb | 7472 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7473 | break; |
252b5132 RH |
7474 | } |
7475 | if (sreg == 0) | |
7476 | { | |
7477 | as_warn (_("Instruction %s: result is always false"), | |
7478 | ip->insn_mo->name); | |
67c0d1eb | 7479 | move_register (dreg, 0); |
8fc2e39e | 7480 | break; |
252b5132 RH |
7481 | } |
7482 | if (imm_expr.X_op == O_constant | |
7483 | && imm_expr.X_add_number >= 0 | |
7484 | && imm_expr.X_add_number < 0x10000) | |
7485 | { | |
67c0d1eb | 7486 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7487 | } |
7488 | else if (imm_expr.X_op == O_constant | |
7489 | && imm_expr.X_add_number > -0x8000 | |
7490 | && imm_expr.X_add_number < 0) | |
7491 | { | |
7492 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7493 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7494 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7495 | } |
7496 | else | |
7497 | { | |
67c0d1eb RS |
7498 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7499 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7500 | used_at = 1; |
7501 | } | |
67c0d1eb | 7502 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 7503 | break; |
252b5132 RH |
7504 | |
7505 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
7506 | s = "slt"; | |
7507 | goto sge; | |
7508 | case M_SGEU: | |
7509 | s = "sltu"; | |
7510 | sge: | |
67c0d1eb RS |
7511 | macro_build (NULL, s, "d,v,t", dreg, sreg, treg); |
7512 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 7513 | break; |
252b5132 RH |
7514 | |
7515 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
7516 | case M_SGEU_I: | |
7517 | if (imm_expr.X_op == O_constant | |
7518 | && imm_expr.X_add_number >= -0x8000 | |
7519 | && imm_expr.X_add_number < 0x8000) | |
7520 | { | |
67c0d1eb RS |
7521 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
7522 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
7523 | } |
7524 | else | |
7525 | { | |
67c0d1eb RS |
7526 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7527 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", | |
7528 | dreg, sreg, AT); | |
252b5132 RH |
7529 | used_at = 1; |
7530 | } | |
67c0d1eb | 7531 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 7532 | break; |
252b5132 RH |
7533 | |
7534 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
7535 | s = "slt"; | |
7536 | goto sgt; | |
7537 | case M_SGTU: | |
7538 | s = "sltu"; | |
7539 | sgt: | |
67c0d1eb | 7540 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
8fc2e39e | 7541 | break; |
252b5132 RH |
7542 | |
7543 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
7544 | s = "slt"; | |
7545 | goto sgti; | |
7546 | case M_SGTU_I: | |
7547 | s = "sltu"; | |
7548 | sgti: | |
8fc2e39e | 7549 | used_at = 1; |
67c0d1eb RS |
7550 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7551 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
252b5132 RH |
7552 | break; |
7553 | ||
2396cfb9 | 7554 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
7555 | s = "slt"; |
7556 | goto sle; | |
7557 | case M_SLEU: | |
7558 | s = "sltu"; | |
7559 | sle: | |
67c0d1eb RS |
7560 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
7561 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 7562 | break; |
252b5132 | 7563 | |
2396cfb9 | 7564 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
7565 | s = "slt"; |
7566 | goto slei; | |
7567 | case M_SLEU_I: | |
7568 | s = "sltu"; | |
7569 | slei: | |
8fc2e39e | 7570 | used_at = 1; |
67c0d1eb RS |
7571 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7572 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
7573 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
7574 | break; |
7575 | ||
7576 | case M_SLT_I: | |
7577 | if (imm_expr.X_op == O_constant | |
7578 | && imm_expr.X_add_number >= -0x8000 | |
7579 | && imm_expr.X_add_number < 0x8000) | |
7580 | { | |
67c0d1eb | 7581 | macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7582 | break; |
252b5132 | 7583 | } |
8fc2e39e | 7584 | used_at = 1; |
67c0d1eb RS |
7585 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7586 | macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7587 | break; |
7588 | ||
7589 | case M_SLTU_I: | |
7590 | if (imm_expr.X_op == O_constant | |
7591 | && imm_expr.X_add_number >= -0x8000 | |
7592 | && imm_expr.X_add_number < 0x8000) | |
7593 | { | |
67c0d1eb | 7594 | macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg, |
17a2f251 | 7595 | BFD_RELOC_LO16); |
8fc2e39e | 7596 | break; |
252b5132 | 7597 | } |
8fc2e39e | 7598 | used_at = 1; |
67c0d1eb RS |
7599 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7600 | macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7601 | break; |
7602 | ||
7603 | case M_SNE: | |
7604 | if (sreg == 0) | |
67c0d1eb | 7605 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg); |
252b5132 | 7606 | else if (treg == 0) |
67c0d1eb | 7607 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
7608 | else |
7609 | { | |
67c0d1eb RS |
7610 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7611 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
252b5132 | 7612 | } |
8fc2e39e | 7613 | break; |
252b5132 RH |
7614 | |
7615 | case M_SNE_I: | |
7616 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7617 | { | |
67c0d1eb | 7618 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
8fc2e39e | 7619 | break; |
252b5132 RH |
7620 | } |
7621 | if (sreg == 0) | |
7622 | { | |
7623 | as_warn (_("Instruction %s: result is always true"), | |
7624 | ip->insn_mo->name); | |
67c0d1eb RS |
7625 | macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", |
7626 | dreg, 0, BFD_RELOC_LO16); | |
8fc2e39e | 7627 | break; |
252b5132 RH |
7628 | } |
7629 | if (imm_expr.X_op == O_constant | |
7630 | && imm_expr.X_add_number >= 0 | |
7631 | && imm_expr.X_add_number < 0x10000) | |
7632 | { | |
67c0d1eb | 7633 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7634 | } |
7635 | else if (imm_expr.X_op == O_constant | |
7636 | && imm_expr.X_add_number > -0x8000 | |
7637 | && imm_expr.X_add_number < 0) | |
7638 | { | |
7639 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7640 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7641 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7642 | } |
7643 | else | |
7644 | { | |
67c0d1eb RS |
7645 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7646 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7647 | used_at = 1; |
7648 | } | |
67c0d1eb | 7649 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); |
8fc2e39e | 7650 | break; |
252b5132 RH |
7651 | |
7652 | case M_DSUB_I: | |
7653 | dbl = 1; | |
7654 | case M_SUB_I: | |
7655 | if (imm_expr.X_op == O_constant | |
7656 | && imm_expr.X_add_number > -0x8000 | |
7657 | && imm_expr.X_add_number <= 0x8000) | |
7658 | { | |
7659 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7660 | macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j", |
7661 | dreg, sreg, BFD_RELOC_LO16); | |
8fc2e39e | 7662 | break; |
252b5132 | 7663 | } |
8fc2e39e | 7664 | used_at = 1; |
67c0d1eb RS |
7665 | load_register (AT, &imm_expr, dbl); |
7666 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7667 | break; |
7668 | ||
7669 | case M_DSUBU_I: | |
7670 | dbl = 1; | |
7671 | case M_SUBU_I: | |
7672 | if (imm_expr.X_op == O_constant | |
7673 | && imm_expr.X_add_number > -0x8000 | |
7674 | && imm_expr.X_add_number <= 0x8000) | |
7675 | { | |
7676 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7677 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j", |
7678 | dreg, sreg, BFD_RELOC_LO16); | |
8fc2e39e | 7679 | break; |
252b5132 | 7680 | } |
8fc2e39e | 7681 | used_at = 1; |
67c0d1eb RS |
7682 | load_register (AT, &imm_expr, dbl); |
7683 | macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7684 | break; |
7685 | ||
7686 | case M_TEQ_I: | |
7687 | s = "teq"; | |
7688 | goto trap; | |
7689 | case M_TGE_I: | |
7690 | s = "tge"; | |
7691 | goto trap; | |
7692 | case M_TGEU_I: | |
7693 | s = "tgeu"; | |
7694 | goto trap; | |
7695 | case M_TLT_I: | |
7696 | s = "tlt"; | |
7697 | goto trap; | |
7698 | case M_TLTU_I: | |
7699 | s = "tltu"; | |
7700 | goto trap; | |
7701 | case M_TNE_I: | |
7702 | s = "tne"; | |
7703 | trap: | |
8fc2e39e | 7704 | used_at = 1; |
67c0d1eb RS |
7705 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7706 | macro_build (NULL, s, "s,t", sreg, AT); | |
252b5132 RH |
7707 | break; |
7708 | ||
252b5132 | 7709 | case M_TRUNCWS: |
43841e91 | 7710 | case M_TRUNCWD: |
e7af610e | 7711 | assert (mips_opts.isa == ISA_MIPS1); |
8fc2e39e | 7712 | used_at = 1; |
252b5132 RH |
7713 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
7714 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
7715 | ||
7716 | /* | |
7717 | * Is the double cfc1 instruction a bug in the mips assembler; | |
7718 | * or is there a reason for it? | |
7719 | */ | |
7d10b47d | 7720 | start_noreorder (); |
67c0d1eb RS |
7721 | macro_build (NULL, "cfc1", "t,G", treg, RA); |
7722 | macro_build (NULL, "cfc1", "t,G", treg, RA); | |
7723 | macro_build (NULL, "nop", ""); | |
252b5132 | 7724 | expr1.X_add_number = 3; |
67c0d1eb | 7725 | macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16); |
252b5132 | 7726 | expr1.X_add_number = 2; |
67c0d1eb RS |
7727 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
7728 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
7729 | macro_build (NULL, "nop", ""); | |
7730 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
7731 | dreg, sreg); | |
7732 | macro_build (NULL, "ctc1", "t,G", treg, RA); | |
7733 | macro_build (NULL, "nop", ""); | |
7d10b47d | 7734 | end_noreorder (); |
252b5132 RH |
7735 | break; |
7736 | ||
7737 | case M_ULH: | |
7738 | s = "lb"; | |
7739 | goto ulh; | |
7740 | case M_ULHU: | |
7741 | s = "lbu"; | |
7742 | ulh: | |
8fc2e39e | 7743 | used_at = 1; |
252b5132 RH |
7744 | if (offset_expr.X_add_number >= 0x7fff) |
7745 | as_bad (_("operand overflow")); | |
252b5132 | 7746 | if (! target_big_endian) |
f9419b05 | 7747 | ++offset_expr.X_add_number; |
67c0d1eb | 7748 | macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 | 7749 | if (! target_big_endian) |
f9419b05 | 7750 | --offset_expr.X_add_number; |
252b5132 | 7751 | else |
f9419b05 | 7752 | ++offset_expr.X_add_number; |
67c0d1eb RS |
7753 | macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
7754 | macro_build (NULL, "sll", "d,w,<", AT, AT, 8); | |
7755 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7756 | break; |
7757 | ||
7758 | case M_ULD: | |
7759 | s = "ldl"; | |
7760 | s2 = "ldr"; | |
7761 | off = 7; | |
7762 | goto ulw; | |
7763 | case M_ULW: | |
7764 | s = "lwl"; | |
7765 | s2 = "lwr"; | |
7766 | off = 3; | |
7767 | ulw: | |
7768 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7769 | as_bad (_("operand overflow")); | |
af22f5b2 CD |
7770 | if (treg != breg) |
7771 | tempreg = treg; | |
7772 | else | |
8fc2e39e TS |
7773 | { |
7774 | used_at = 1; | |
7775 | tempreg = AT; | |
7776 | } | |
252b5132 RH |
7777 | if (! target_big_endian) |
7778 | offset_expr.X_add_number += off; | |
67c0d1eb | 7779 | macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7780 | if (! target_big_endian) |
7781 | offset_expr.X_add_number -= off; | |
7782 | else | |
7783 | offset_expr.X_add_number += off; | |
67c0d1eb | 7784 | macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
af22f5b2 CD |
7785 | |
7786 | /* If necessary, move the result in tempreg the final destination. */ | |
7787 | if (treg == tempreg) | |
8fc2e39e | 7788 | break; |
af22f5b2 | 7789 | /* Protect second load's delay slot. */ |
017315e4 | 7790 | load_delay_nop (); |
67c0d1eb | 7791 | move_register (treg, tempreg); |
af22f5b2 | 7792 | break; |
252b5132 RH |
7793 | |
7794 | case M_ULD_A: | |
7795 | s = "ldl"; | |
7796 | s2 = "ldr"; | |
7797 | off = 7; | |
7798 | goto ulwa; | |
7799 | case M_ULW_A: | |
7800 | s = "lwl"; | |
7801 | s2 = "lwr"; | |
7802 | off = 3; | |
7803 | ulwa: | |
d6bc6245 | 7804 | used_at = 1; |
67c0d1eb | 7805 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7806 | if (breg != 0) |
67c0d1eb | 7807 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7808 | if (! target_big_endian) |
7809 | expr1.X_add_number = off; | |
7810 | else | |
7811 | expr1.X_add_number = 0; | |
67c0d1eb | 7812 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7813 | if (! target_big_endian) |
7814 | expr1.X_add_number = 0; | |
7815 | else | |
7816 | expr1.X_add_number = off; | |
67c0d1eb | 7817 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7818 | break; |
7819 | ||
7820 | case M_ULH_A: | |
7821 | case M_ULHU_A: | |
d6bc6245 | 7822 | used_at = 1; |
67c0d1eb | 7823 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7824 | if (breg != 0) |
67c0d1eb | 7825 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7826 | if (target_big_endian) |
7827 | expr1.X_add_number = 0; | |
67c0d1eb | 7828 | macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", |
17a2f251 | 7829 | treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7830 | if (target_big_endian) |
7831 | expr1.X_add_number = 1; | |
7832 | else | |
7833 | expr1.X_add_number = 0; | |
67c0d1eb RS |
7834 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
7835 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
7836 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7837 | break; |
7838 | ||
7839 | case M_USH: | |
8fc2e39e | 7840 | used_at = 1; |
252b5132 RH |
7841 | if (offset_expr.X_add_number >= 0x7fff) |
7842 | as_bad (_("operand overflow")); | |
7843 | if (target_big_endian) | |
f9419b05 | 7844 | ++offset_expr.X_add_number; |
67c0d1eb RS |
7845 | macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
7846 | macro_build (NULL, "srl", "d,w,<", AT, treg, 8); | |
252b5132 | 7847 | if (target_big_endian) |
f9419b05 | 7848 | --offset_expr.X_add_number; |
252b5132 | 7849 | else |
f9419b05 | 7850 | ++offset_expr.X_add_number; |
67c0d1eb | 7851 | macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 RH |
7852 | break; |
7853 | ||
7854 | case M_USD: | |
7855 | s = "sdl"; | |
7856 | s2 = "sdr"; | |
7857 | off = 7; | |
7858 | goto usw; | |
7859 | case M_USW: | |
7860 | s = "swl"; | |
7861 | s2 = "swr"; | |
7862 | off = 3; | |
7863 | usw: | |
7864 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7865 | as_bad (_("operand overflow")); | |
7866 | if (! target_big_endian) | |
7867 | offset_expr.X_add_number += off; | |
67c0d1eb | 7868 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7869 | if (! target_big_endian) |
7870 | offset_expr.X_add_number -= off; | |
7871 | else | |
7872 | offset_expr.X_add_number += off; | |
67c0d1eb | 7873 | macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
8fc2e39e | 7874 | break; |
252b5132 RH |
7875 | |
7876 | case M_USD_A: | |
7877 | s = "sdl"; | |
7878 | s2 = "sdr"; | |
7879 | off = 7; | |
7880 | goto uswa; | |
7881 | case M_USW_A: | |
7882 | s = "swl"; | |
7883 | s2 = "swr"; | |
7884 | off = 3; | |
7885 | uswa: | |
d6bc6245 | 7886 | used_at = 1; |
67c0d1eb | 7887 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7888 | if (breg != 0) |
67c0d1eb | 7889 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7890 | if (! target_big_endian) |
7891 | expr1.X_add_number = off; | |
7892 | else | |
7893 | expr1.X_add_number = 0; | |
67c0d1eb | 7894 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7895 | if (! target_big_endian) |
7896 | expr1.X_add_number = 0; | |
7897 | else | |
7898 | expr1.X_add_number = off; | |
67c0d1eb | 7899 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7900 | break; |
7901 | ||
7902 | case M_USH_A: | |
d6bc6245 | 7903 | used_at = 1; |
67c0d1eb | 7904 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7905 | if (breg != 0) |
67c0d1eb | 7906 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7907 | if (! target_big_endian) |
7908 | expr1.X_add_number = 0; | |
67c0d1eb RS |
7909 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
7910 | macro_build (NULL, "srl", "d,w,<", treg, treg, 8); | |
252b5132 RH |
7911 | if (! target_big_endian) |
7912 | expr1.X_add_number = 1; | |
7913 | else | |
7914 | expr1.X_add_number = 0; | |
67c0d1eb | 7915 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7916 | if (! target_big_endian) |
7917 | expr1.X_add_number = 0; | |
7918 | else | |
7919 | expr1.X_add_number = 1; | |
67c0d1eb RS |
7920 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
7921 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
7922 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7923 | break; |
7924 | ||
7925 | default: | |
7926 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 7927 | are added dynamically. */ |
252b5132 RH |
7928 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
7929 | break; | |
7930 | } | |
8fc2e39e TS |
7931 | if (mips_opts.noat && used_at) |
7932 | as_bad (_("Macro used $at after \".set noat\"")); | |
252b5132 RH |
7933 | } |
7934 | ||
7935 | /* Implement macros in mips16 mode. */ | |
7936 | ||
7937 | static void | |
17a2f251 | 7938 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 RH |
7939 | { |
7940 | int mask; | |
7941 | int xreg, yreg, zreg, tmp; | |
252b5132 RH |
7942 | expressionS expr1; |
7943 | int dbl; | |
7944 | const char *s, *s2, *s3; | |
7945 | ||
7946 | mask = ip->insn_mo->mask; | |
7947 | ||
bf12938e RS |
7948 | xreg = MIPS16_EXTRACT_OPERAND (RX, *ip); |
7949 | yreg = MIPS16_EXTRACT_OPERAND (RY, *ip); | |
7950 | zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip); | |
252b5132 | 7951 | |
252b5132 RH |
7952 | expr1.X_op = O_constant; |
7953 | expr1.X_op_symbol = NULL; | |
7954 | expr1.X_add_symbol = NULL; | |
7955 | expr1.X_add_number = 1; | |
7956 | ||
7957 | dbl = 0; | |
7958 | ||
7959 | switch (mask) | |
7960 | { | |
7961 | default: | |
7962 | internalError (); | |
7963 | ||
7964 | case M_DDIV_3: | |
7965 | dbl = 1; | |
7966 | case M_DIV_3: | |
7967 | s = "mflo"; | |
7968 | goto do_div3; | |
7969 | case M_DREM_3: | |
7970 | dbl = 1; | |
7971 | case M_REM_3: | |
7972 | s = "mfhi"; | |
7973 | do_div3: | |
7d10b47d | 7974 | start_noreorder (); |
67c0d1eb | 7975 | macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg); |
252b5132 | 7976 | expr1.X_add_number = 2; |
67c0d1eb RS |
7977 | macro_build (&expr1, "bnez", "x,p", yreg); |
7978 | macro_build (NULL, "break", "6", 7); | |
bdaaa2e1 | 7979 | |
252b5132 RH |
7980 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
7981 | since that causes an overflow. We should do that as well, | |
7982 | but I don't see how to do the comparisons without a temporary | |
7983 | register. */ | |
7d10b47d | 7984 | end_noreorder (); |
67c0d1eb | 7985 | macro_build (NULL, s, "x", zreg); |
252b5132 RH |
7986 | break; |
7987 | ||
7988 | case M_DIVU_3: | |
7989 | s = "divu"; | |
7990 | s2 = "mflo"; | |
7991 | goto do_divu3; | |
7992 | case M_REMU_3: | |
7993 | s = "divu"; | |
7994 | s2 = "mfhi"; | |
7995 | goto do_divu3; | |
7996 | case M_DDIVU_3: | |
7997 | s = "ddivu"; | |
7998 | s2 = "mflo"; | |
7999 | goto do_divu3; | |
8000 | case M_DREMU_3: | |
8001 | s = "ddivu"; | |
8002 | s2 = "mfhi"; | |
8003 | do_divu3: | |
7d10b47d | 8004 | start_noreorder (); |
67c0d1eb | 8005 | macro_build (NULL, s, "0,x,y", xreg, yreg); |
252b5132 | 8006 | expr1.X_add_number = 2; |
67c0d1eb RS |
8007 | macro_build (&expr1, "bnez", "x,p", yreg); |
8008 | macro_build (NULL, "break", "6", 7); | |
7d10b47d | 8009 | end_noreorder (); |
67c0d1eb | 8010 | macro_build (NULL, s2, "x", zreg); |
252b5132 RH |
8011 | break; |
8012 | ||
8013 | case M_DMUL: | |
8014 | dbl = 1; | |
8015 | case M_MUL: | |
67c0d1eb RS |
8016 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
8017 | macro_build (NULL, "mflo", "x", zreg); | |
8fc2e39e | 8018 | break; |
252b5132 RH |
8019 | |
8020 | case M_DSUBU_I: | |
8021 | dbl = 1; | |
8022 | goto do_subu; | |
8023 | case M_SUBU_I: | |
8024 | do_subu: | |
8025 | if (imm_expr.X_op != O_constant) | |
8026 | as_bad (_("Unsupported large constant")); | |
8027 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 8028 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
8029 | break; |
8030 | ||
8031 | case M_SUBU_I_2: | |
8032 | if (imm_expr.X_op != O_constant) | |
8033 | as_bad (_("Unsupported large constant")); | |
8034 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 8035 | macro_build (&imm_expr, "addiu", "x,k", xreg); |
252b5132 RH |
8036 | break; |
8037 | ||
8038 | case M_DSUBU_I_2: | |
8039 | if (imm_expr.X_op != O_constant) | |
8040 | as_bad (_("Unsupported large constant")); | |
8041 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 8042 | macro_build (&imm_expr, "daddiu", "y,j", yreg); |
252b5132 RH |
8043 | break; |
8044 | ||
8045 | case M_BEQ: | |
8046 | s = "cmp"; | |
8047 | s2 = "bteqz"; | |
8048 | goto do_branch; | |
8049 | case M_BNE: | |
8050 | s = "cmp"; | |
8051 | s2 = "btnez"; | |
8052 | goto do_branch; | |
8053 | case M_BLT: | |
8054 | s = "slt"; | |
8055 | s2 = "btnez"; | |
8056 | goto do_branch; | |
8057 | case M_BLTU: | |
8058 | s = "sltu"; | |
8059 | s2 = "btnez"; | |
8060 | goto do_branch; | |
8061 | case M_BLE: | |
8062 | s = "slt"; | |
8063 | s2 = "bteqz"; | |
8064 | goto do_reverse_branch; | |
8065 | case M_BLEU: | |
8066 | s = "sltu"; | |
8067 | s2 = "bteqz"; | |
8068 | goto do_reverse_branch; | |
8069 | case M_BGE: | |
8070 | s = "slt"; | |
8071 | s2 = "bteqz"; | |
8072 | goto do_branch; | |
8073 | case M_BGEU: | |
8074 | s = "sltu"; | |
8075 | s2 = "bteqz"; | |
8076 | goto do_branch; | |
8077 | case M_BGT: | |
8078 | s = "slt"; | |
8079 | s2 = "btnez"; | |
8080 | goto do_reverse_branch; | |
8081 | case M_BGTU: | |
8082 | s = "sltu"; | |
8083 | s2 = "btnez"; | |
8084 | ||
8085 | do_reverse_branch: | |
8086 | tmp = xreg; | |
8087 | xreg = yreg; | |
8088 | yreg = tmp; | |
8089 | ||
8090 | do_branch: | |
67c0d1eb RS |
8091 | macro_build (NULL, s, "x,y", xreg, yreg); |
8092 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
8093 | break; |
8094 | ||
8095 | case M_BEQ_I: | |
8096 | s = "cmpi"; | |
8097 | s2 = "bteqz"; | |
8098 | s3 = "x,U"; | |
8099 | goto do_branch_i; | |
8100 | case M_BNE_I: | |
8101 | s = "cmpi"; | |
8102 | s2 = "btnez"; | |
8103 | s3 = "x,U"; | |
8104 | goto do_branch_i; | |
8105 | case M_BLT_I: | |
8106 | s = "slti"; | |
8107 | s2 = "btnez"; | |
8108 | s3 = "x,8"; | |
8109 | goto do_branch_i; | |
8110 | case M_BLTU_I: | |
8111 | s = "sltiu"; | |
8112 | s2 = "btnez"; | |
8113 | s3 = "x,8"; | |
8114 | goto do_branch_i; | |
8115 | case M_BLE_I: | |
8116 | s = "slti"; | |
8117 | s2 = "btnez"; | |
8118 | s3 = "x,8"; | |
8119 | goto do_addone_branch_i; | |
8120 | case M_BLEU_I: | |
8121 | s = "sltiu"; | |
8122 | s2 = "btnez"; | |
8123 | s3 = "x,8"; | |
8124 | goto do_addone_branch_i; | |
8125 | case M_BGE_I: | |
8126 | s = "slti"; | |
8127 | s2 = "bteqz"; | |
8128 | s3 = "x,8"; | |
8129 | goto do_branch_i; | |
8130 | case M_BGEU_I: | |
8131 | s = "sltiu"; | |
8132 | s2 = "bteqz"; | |
8133 | s3 = "x,8"; | |
8134 | goto do_branch_i; | |
8135 | case M_BGT_I: | |
8136 | s = "slti"; | |
8137 | s2 = "bteqz"; | |
8138 | s3 = "x,8"; | |
8139 | goto do_addone_branch_i; | |
8140 | case M_BGTU_I: | |
8141 | s = "sltiu"; | |
8142 | s2 = "bteqz"; | |
8143 | s3 = "x,8"; | |
8144 | ||
8145 | do_addone_branch_i: | |
8146 | if (imm_expr.X_op != O_constant) | |
8147 | as_bad (_("Unsupported large constant")); | |
8148 | ++imm_expr.X_add_number; | |
8149 | ||
8150 | do_branch_i: | |
67c0d1eb RS |
8151 | macro_build (&imm_expr, s, s3, xreg); |
8152 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
8153 | break; |
8154 | ||
8155 | case M_ABS: | |
8156 | expr1.X_add_number = 0; | |
67c0d1eb | 8157 | macro_build (&expr1, "slti", "x,8", yreg); |
252b5132 | 8158 | if (xreg != yreg) |
67c0d1eb | 8159 | move_register (xreg, yreg); |
252b5132 | 8160 | expr1.X_add_number = 2; |
67c0d1eb RS |
8161 | macro_build (&expr1, "bteqz", "p"); |
8162 | macro_build (NULL, "neg", "x,w", xreg, xreg); | |
252b5132 RH |
8163 | } |
8164 | } | |
8165 | ||
8166 | /* For consistency checking, verify that all bits are specified either | |
8167 | by the match/mask part of the instruction definition, or by the | |
8168 | operand list. */ | |
8169 | static int | |
17a2f251 | 8170 | validate_mips_insn (const struct mips_opcode *opc) |
252b5132 RH |
8171 | { |
8172 | const char *p = opc->args; | |
8173 | char c; | |
8174 | unsigned long used_bits = opc->mask; | |
8175 | ||
8176 | if ((used_bits & opc->match) != opc->match) | |
8177 | { | |
8178 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
8179 | opc->name, opc->args); | |
8180 | return 0; | |
8181 | } | |
8182 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
8183 | while (*p) | |
8184 | switch (c = *p++) | |
8185 | { | |
8186 | case ',': break; | |
8187 | case '(': break; | |
8188 | case ')': break; | |
af7ee8bf CD |
8189 | case '+': |
8190 | switch (c = *p++) | |
8191 | { | |
9bcd4f99 TS |
8192 | case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break; |
8193 | case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break; | |
8194 | case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break; | |
8195 | case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break; | |
af7ee8bf CD |
8196 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8197 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
8198 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
bbcc0807 CD |
8199 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); |
8200 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
5f74bc13 CD |
8201 | case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8202 | case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
8203 | case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
8204 | case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
8205 | case 'I': break; | |
ef2e4d86 CF |
8206 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; |
8207 | case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT); | |
8208 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
af7ee8bf CD |
8209 | default: |
8210 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
8211 | c, opc->name, opc->args); | |
8212 | return 0; | |
8213 | } | |
8214 | break; | |
252b5132 RH |
8215 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8216 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
8217 | case 'A': break; | |
4372b673 | 8218 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
8219 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
8220 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
8221 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8222 | case 'F': break; | |
8223 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 8224 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 8225 | case 'I': break; |
e972090a | 8226 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 8227 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
8228 | case 'L': break; |
8229 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
8230 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
8231 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
8232 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
8233 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
8234 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
8235 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8236 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
8237 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8238 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
8239 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
8240 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8241 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
8242 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
8243 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8244 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
8245 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
8246 | case 'f': break; | |
8247 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
8248 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
8249 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8250 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
8251 | case 'l': break; | |
8252 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8253 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8254 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
8255 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8256 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8257 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8258 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
8259 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8260 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8261 | case 'x': break; | |
8262 | case 'z': break; | |
8263 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
8264 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
8265 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
8266 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
8267 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
8268 | case '[': break; | |
8269 | case ']': break; | |
8b082fb1 | 8270 | case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break; |
74cd071d CF |
8271 | case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break; |
8272 | case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break; | |
8273 | case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break; | |
8274 | case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8275 | case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break; | |
8276 | case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break; | |
8277 | case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break; | |
8278 | case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break; | |
8279 | case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break; | |
8280 | case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break; | |
8281 | case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break; | |
ef2e4d86 CF |
8282 | case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break; |
8283 | case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break; | |
8284 | case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break; | |
8285 | case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break; | |
8286 | case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
252b5132 RH |
8287 | default: |
8288 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
8289 | c, opc->name, opc->args); | |
8290 | return 0; | |
8291 | } | |
8292 | #undef USE_BITS | |
8293 | if (used_bits != 0xffffffff) | |
8294 | { | |
8295 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
8296 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
8297 | return 0; | |
8298 | } | |
8299 | return 1; | |
8300 | } | |
8301 | ||
9bcd4f99 TS |
8302 | /* UDI immediates. */ |
8303 | struct mips_immed { | |
8304 | char type; | |
8305 | unsigned int shift; | |
8306 | unsigned long mask; | |
8307 | const char * desc; | |
8308 | }; | |
8309 | ||
8310 | static const struct mips_immed mips_immed[] = { | |
8311 | { '1', OP_SH_UDI1, OP_MASK_UDI1, 0}, | |
8312 | { '2', OP_SH_UDI2, OP_MASK_UDI2, 0}, | |
8313 | { '3', OP_SH_UDI3, OP_MASK_UDI3, 0}, | |
8314 | { '4', OP_SH_UDI4, OP_MASK_UDI4, 0}, | |
8315 | { 0,0,0,0 } | |
8316 | }; | |
8317 | ||
7455baf8 TS |
8318 | /* Check whether an odd floating-point register is allowed. */ |
8319 | static int | |
8320 | mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum) | |
8321 | { | |
8322 | const char *s = insn->name; | |
8323 | ||
8324 | if (insn->pinfo == INSN_MACRO) | |
8325 | /* Let a macro pass, we'll catch it later when it is expanded. */ | |
8326 | return 1; | |
8327 | ||
8328 | if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa)) | |
8329 | { | |
8330 | /* Allow odd registers for single-precision ops. */ | |
8331 | switch (insn->pinfo & (FP_S | FP_D)) | |
8332 | { | |
8333 | case FP_S: | |
8334 | case 0: | |
8335 | return 1; /* both single precision - ok */ | |
8336 | case FP_D: | |
8337 | return 0; /* both double precision - fail */ | |
8338 | default: | |
8339 | break; | |
8340 | } | |
8341 | ||
8342 | /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ | |
8343 | s = strchr (insn->name, '.'); | |
8344 | if (argnum == 2) | |
8345 | s = s != NULL ? strchr (s + 1, '.') : NULL; | |
8346 | return (s != NULL && (s[1] == 'w' || s[1] == 's')); | |
8347 | } | |
8348 | ||
8349 | /* Single-precision coprocessor loads and moves are OK too. */ | |
8350 | if ((insn->pinfo & FP_S) | |
8351 | && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY | |
8352 | | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY))) | |
8353 | return 1; | |
8354 | ||
8355 | return 0; | |
8356 | } | |
8357 | ||
252b5132 RH |
8358 | /* This routine assembles an instruction into its binary format. As a |
8359 | side effect, it sets one of the global variables imm_reloc or | |
8360 | offset_reloc to the type of relocation to do if one of the operands | |
8361 | is an address expression. */ | |
8362 | ||
8363 | static void | |
17a2f251 | 8364 | mips_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
8365 | { |
8366 | char *s; | |
8367 | const char *args; | |
43841e91 | 8368 | char c = 0; |
252b5132 RH |
8369 | struct mips_opcode *insn; |
8370 | char *argsStart; | |
8371 | unsigned int regno; | |
8372 | unsigned int lastregno = 0; | |
af7ee8bf | 8373 | unsigned int lastpos = 0; |
071742cf | 8374 | unsigned int limlo, limhi; |
252b5132 RH |
8375 | char *s_reset; |
8376 | char save_c = 0; | |
74cd071d | 8377 | offsetT min_range, max_range; |
707bfff6 TS |
8378 | int argnum; |
8379 | unsigned int rtype; | |
252b5132 RH |
8380 | |
8381 | insn_error = NULL; | |
8382 | ||
8383 | /* If the instruction contains a '.', we first try to match an instruction | |
8384 | including the '.'. Then we try again without the '.'. */ | |
8385 | insn = NULL; | |
3882b010 | 8386 | for (s = str; *s != '\0' && !ISSPACE (*s); ++s) |
252b5132 RH |
8387 | continue; |
8388 | ||
8389 | /* If we stopped on whitespace, then replace the whitespace with null for | |
8390 | the call to hash_find. Save the character we replaced just in case we | |
8391 | have to re-parse the instruction. */ | |
3882b010 | 8392 | if (ISSPACE (*s)) |
252b5132 RH |
8393 | { |
8394 | save_c = *s; | |
8395 | *s++ = '\0'; | |
8396 | } | |
bdaaa2e1 | 8397 | |
252b5132 RH |
8398 | insn = (struct mips_opcode *) hash_find (op_hash, str); |
8399 | ||
8400 | /* If we didn't find the instruction in the opcode table, try again, but | |
8401 | this time with just the instruction up to, but not including the | |
8402 | first '.'. */ | |
8403 | if (insn == NULL) | |
8404 | { | |
bdaaa2e1 | 8405 | /* Restore the character we overwrite above (if any). */ |
252b5132 RH |
8406 | if (save_c) |
8407 | *(--s) = save_c; | |
8408 | ||
8409 | /* Scan up to the first '.' or whitespace. */ | |
3882b010 L |
8410 | for (s = str; |
8411 | *s != '\0' && *s != '.' && !ISSPACE (*s); | |
8412 | ++s) | |
252b5132 RH |
8413 | continue; |
8414 | ||
8415 | /* If we did not find a '.', then we can quit now. */ | |
8416 | if (*s != '.') | |
8417 | { | |
8418 | insn_error = "unrecognized opcode"; | |
8419 | return; | |
8420 | } | |
8421 | ||
8422 | /* Lookup the instruction in the hash table. */ | |
8423 | *s++ = '\0'; | |
8424 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
8425 | { | |
8426 | insn_error = "unrecognized opcode"; | |
8427 | return; | |
8428 | } | |
252b5132 RH |
8429 | } |
8430 | ||
8431 | argsStart = s; | |
8432 | for (;;) | |
8433 | { | |
b34976b6 | 8434 | bfd_boolean ok; |
252b5132 RH |
8435 | |
8436 | assert (strcmp (insn->name, str) == 0); | |
8437 | ||
1f25f5d3 CD |
8438 | if (OPCODE_IS_MEMBER (insn, |
8439 | (mips_opts.isa | |
9b3f89ee TS |
8440 | /* We don't check for mips_opts.mips16 here since |
8441 | we want to allow jalx if -mips16 was specified | |
8442 | on the command line. */ | |
3396de36 | 8443 | | (file_ase_mips16 ? INSN_MIPS16 : 0) |
deec1734 | 8444 | | (mips_opts.ase_mdmx ? INSN_MDMX : 0) |
74cd071d | 8445 | | (mips_opts.ase_dsp ? INSN_DSP : 0) |
65263ce3 TS |
8446 | | ((mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE) |
8447 | ? INSN_DSP64 : 0) | |
8b082fb1 | 8448 | | (mips_opts.ase_dspr2 ? INSN_DSPR2 : 0) |
ef2e4d86 | 8449 | | (mips_opts.ase_mt ? INSN_MT : 0) |
e16bfa71 TS |
8450 | | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0) |
8451 | | (mips_opts.ase_smartmips ? INSN_SMARTMIPS : 0)), | |
fef14a42 | 8452 | mips_opts.arch)) |
b34976b6 | 8453 | ok = TRUE; |
bdaaa2e1 | 8454 | else |
b34976b6 | 8455 | ok = FALSE; |
bdaaa2e1 | 8456 | |
252b5132 RH |
8457 | if (insn->pinfo != INSN_MACRO) |
8458 | { | |
fef14a42 | 8459 | if (mips_opts.arch == CPU_R4650 && (insn->pinfo & FP_D) != 0) |
b34976b6 | 8460 | ok = FALSE; |
252b5132 RH |
8461 | } |
8462 | ||
8463 | if (! ok) | |
8464 | { | |
8465 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
8466 | && strcmp (insn->name, insn[1].name) == 0) | |
8467 | { | |
8468 | ++insn; | |
8469 | continue; | |
8470 | } | |
252b5132 | 8471 | else |
beae10d5 | 8472 | { |
268f6bed L |
8473 | if (!insn_error) |
8474 | { | |
8475 | static char buf[100]; | |
fef14a42 TS |
8476 | sprintf (buf, |
8477 | _("opcode not supported on this processor: %s (%s)"), | |
8478 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
8479 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
268f6bed L |
8480 | insn_error = buf; |
8481 | } | |
8482 | if (save_c) | |
8483 | *(--s) = save_c; | |
2bd7f1f3 | 8484 | return; |
252b5132 | 8485 | } |
252b5132 RH |
8486 | } |
8487 | ||
1e915849 | 8488 | create_insn (ip, insn); |
268f6bed | 8489 | insn_error = NULL; |
707bfff6 | 8490 | argnum = 1; |
252b5132 RH |
8491 | for (args = insn->args;; ++args) |
8492 | { | |
deec1734 CD |
8493 | int is_mdmx; |
8494 | ||
ad8d3bb3 | 8495 | s += strspn (s, " \t"); |
deec1734 | 8496 | is_mdmx = 0; |
252b5132 RH |
8497 | switch (*args) |
8498 | { | |
8499 | case '\0': /* end of args */ | |
8500 | if (*s == '\0') | |
8501 | return; | |
8502 | break; | |
8503 | ||
8b082fb1 TS |
8504 | case '2': /* dsp 2-bit unsigned immediate in bit 11 */ |
8505 | my_getExpression (&imm_expr, s); | |
8506 | check_absolute_expr (ip, &imm_expr); | |
8507 | if ((unsigned long) imm_expr.X_add_number != 1 | |
8508 | && (unsigned long) imm_expr.X_add_number != 3) | |
8509 | { | |
8510 | as_bad (_("BALIGN immediate not 1 or 3 (%lu)"), | |
8511 | (unsigned long) imm_expr.X_add_number); | |
8512 | } | |
8513 | INSERT_OPERAND (BP, *ip, imm_expr.X_add_number); | |
8514 | imm_expr.X_op = O_absent; | |
8515 | s = expr_end; | |
8516 | continue; | |
8517 | ||
74cd071d CF |
8518 | case '3': /* dsp 3-bit unsigned immediate in bit 21 */ |
8519 | my_getExpression (&imm_expr, s); | |
8520 | check_absolute_expr (ip, &imm_expr); | |
8521 | if (imm_expr.X_add_number & ~OP_MASK_SA3) | |
8522 | { | |
a9e24354 TS |
8523 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8524 | OP_MASK_SA3, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8525 | } |
a9e24354 | 8526 | INSERT_OPERAND (SA3, *ip, imm_expr.X_add_number); |
74cd071d CF |
8527 | imm_expr.X_op = O_absent; |
8528 | s = expr_end; | |
8529 | continue; | |
8530 | ||
8531 | case '4': /* dsp 4-bit unsigned immediate in bit 21 */ | |
8532 | my_getExpression (&imm_expr, s); | |
8533 | check_absolute_expr (ip, &imm_expr); | |
8534 | if (imm_expr.X_add_number & ~OP_MASK_SA4) | |
8535 | { | |
a9e24354 TS |
8536 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8537 | OP_MASK_SA4, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8538 | } |
a9e24354 | 8539 | INSERT_OPERAND (SA4, *ip, imm_expr.X_add_number); |
74cd071d CF |
8540 | imm_expr.X_op = O_absent; |
8541 | s = expr_end; | |
8542 | continue; | |
8543 | ||
8544 | case '5': /* dsp 8-bit unsigned immediate in bit 16 */ | |
8545 | my_getExpression (&imm_expr, s); | |
8546 | check_absolute_expr (ip, &imm_expr); | |
8547 | if (imm_expr.X_add_number & ~OP_MASK_IMM8) | |
8548 | { | |
a9e24354 TS |
8549 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8550 | OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8551 | } |
a9e24354 | 8552 | INSERT_OPERAND (IMM8, *ip, imm_expr.X_add_number); |
74cd071d CF |
8553 | imm_expr.X_op = O_absent; |
8554 | s = expr_end; | |
8555 | continue; | |
8556 | ||
8557 | case '6': /* dsp 5-bit unsigned immediate in bit 21 */ | |
8558 | my_getExpression (&imm_expr, s); | |
8559 | check_absolute_expr (ip, &imm_expr); | |
8560 | if (imm_expr.X_add_number & ~OP_MASK_RS) | |
8561 | { | |
a9e24354 TS |
8562 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8563 | OP_MASK_RS, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8564 | } |
a9e24354 | 8565 | INSERT_OPERAND (RS, *ip, imm_expr.X_add_number); |
74cd071d CF |
8566 | imm_expr.X_op = O_absent; |
8567 | s = expr_end; | |
8568 | continue; | |
8569 | ||
8570 | case '7': /* four dsp accumulators in bits 11,12 */ | |
8571 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
8572 | s[3] >= '0' && s[3] <= '3') | |
8573 | { | |
8574 | regno = s[3] - '0'; | |
8575 | s += 4; | |
a9e24354 | 8576 | INSERT_OPERAND (DSPACC, *ip, regno); |
74cd071d CF |
8577 | continue; |
8578 | } | |
8579 | else | |
8580 | as_bad (_("Invalid dsp acc register")); | |
8581 | break; | |
8582 | ||
8583 | case '8': /* dsp 6-bit unsigned immediate in bit 11 */ | |
8584 | my_getExpression (&imm_expr, s); | |
8585 | check_absolute_expr (ip, &imm_expr); | |
8586 | if (imm_expr.X_add_number & ~OP_MASK_WRDSP) | |
8587 | { | |
a9e24354 TS |
8588 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8589 | OP_MASK_WRDSP, | |
8590 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8591 | } |
a9e24354 | 8592 | INSERT_OPERAND (WRDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
8593 | imm_expr.X_op = O_absent; |
8594 | s = expr_end; | |
8595 | continue; | |
8596 | ||
8597 | case '9': /* four dsp accumulators in bits 21,22 */ | |
8598 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
8599 | s[3] >= '0' && s[3] <= '3') | |
8600 | { | |
8601 | regno = s[3] - '0'; | |
8602 | s += 4; | |
a9e24354 | 8603 | INSERT_OPERAND (DSPACC_S, *ip, regno); |
74cd071d CF |
8604 | continue; |
8605 | } | |
8606 | else | |
8607 | as_bad (_("Invalid dsp acc register")); | |
8608 | break; | |
8609 | ||
8610 | case '0': /* dsp 6-bit signed immediate in bit 20 */ | |
8611 | my_getExpression (&imm_expr, s); | |
8612 | check_absolute_expr (ip, &imm_expr); | |
8613 | min_range = -((OP_MASK_DSPSFT + 1) >> 1); | |
8614 | max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1; | |
8615 | if (imm_expr.X_add_number < min_range || | |
8616 | imm_expr.X_add_number > max_range) | |
8617 | { | |
a9e24354 TS |
8618 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
8619 | (long) min_range, (long) max_range, | |
8620 | (long) imm_expr.X_add_number); | |
74cd071d | 8621 | } |
a9e24354 | 8622 | INSERT_OPERAND (DSPSFT, *ip, imm_expr.X_add_number); |
74cd071d CF |
8623 | imm_expr.X_op = O_absent; |
8624 | s = expr_end; | |
8625 | continue; | |
8626 | ||
8627 | case '\'': /* dsp 6-bit unsigned immediate in bit 16 */ | |
8628 | my_getExpression (&imm_expr, s); | |
8629 | check_absolute_expr (ip, &imm_expr); | |
8630 | if (imm_expr.X_add_number & ~OP_MASK_RDDSP) | |
8631 | { | |
a9e24354 TS |
8632 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8633 | OP_MASK_RDDSP, | |
8634 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8635 | } |
a9e24354 | 8636 | INSERT_OPERAND (RDDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
8637 | imm_expr.X_op = O_absent; |
8638 | s = expr_end; | |
8639 | continue; | |
8640 | ||
8641 | case ':': /* dsp 7-bit signed immediate in bit 19 */ | |
8642 | my_getExpression (&imm_expr, s); | |
8643 | check_absolute_expr (ip, &imm_expr); | |
8644 | min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1); | |
8645 | max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1; | |
8646 | if (imm_expr.X_add_number < min_range || | |
8647 | imm_expr.X_add_number > max_range) | |
8648 | { | |
a9e24354 TS |
8649 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
8650 | (long) min_range, (long) max_range, | |
8651 | (long) imm_expr.X_add_number); | |
74cd071d | 8652 | } |
a9e24354 | 8653 | INSERT_OPERAND (DSPSFT_7, *ip, imm_expr.X_add_number); |
74cd071d CF |
8654 | imm_expr.X_op = O_absent; |
8655 | s = expr_end; | |
8656 | continue; | |
8657 | ||
8658 | case '@': /* dsp 10-bit signed immediate in bit 16 */ | |
8659 | my_getExpression (&imm_expr, s); | |
8660 | check_absolute_expr (ip, &imm_expr); | |
8661 | min_range = -((OP_MASK_IMM10 + 1) >> 1); | |
8662 | max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1; | |
8663 | if (imm_expr.X_add_number < min_range || | |
8664 | imm_expr.X_add_number > max_range) | |
8665 | { | |
a9e24354 TS |
8666 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
8667 | (long) min_range, (long) max_range, | |
8668 | (long) imm_expr.X_add_number); | |
74cd071d | 8669 | } |
a9e24354 | 8670 | INSERT_OPERAND (IMM10, *ip, imm_expr.X_add_number); |
74cd071d CF |
8671 | imm_expr.X_op = O_absent; |
8672 | s = expr_end; | |
8673 | continue; | |
8674 | ||
a9e24354 | 8675 | case '!': /* MT usermode flag bit. */ |
ef2e4d86 CF |
8676 | my_getExpression (&imm_expr, s); |
8677 | check_absolute_expr (ip, &imm_expr); | |
8678 | if (imm_expr.X_add_number & ~OP_MASK_MT_U) | |
a9e24354 TS |
8679 | as_bad (_("MT usermode bit not 0 or 1 (%lu)"), |
8680 | (unsigned long) imm_expr.X_add_number); | |
8681 | INSERT_OPERAND (MT_U, *ip, imm_expr.X_add_number); | |
ef2e4d86 CF |
8682 | imm_expr.X_op = O_absent; |
8683 | s = expr_end; | |
8684 | continue; | |
8685 | ||
a9e24354 | 8686 | case '$': /* MT load high flag bit. */ |
ef2e4d86 CF |
8687 | my_getExpression (&imm_expr, s); |
8688 | check_absolute_expr (ip, &imm_expr); | |
8689 | if (imm_expr.X_add_number & ~OP_MASK_MT_H) | |
a9e24354 TS |
8690 | as_bad (_("MT load high bit not 0 or 1 (%lu)"), |
8691 | (unsigned long) imm_expr.X_add_number); | |
8692 | INSERT_OPERAND (MT_H, *ip, imm_expr.X_add_number); | |
ef2e4d86 CF |
8693 | imm_expr.X_op = O_absent; |
8694 | s = expr_end; | |
8695 | continue; | |
8696 | ||
8697 | case '*': /* four dsp accumulators in bits 18,19 */ | |
8698 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
8699 | s[3] >= '0' && s[3] <= '3') | |
8700 | { | |
8701 | regno = s[3] - '0'; | |
8702 | s += 4; | |
a9e24354 | 8703 | INSERT_OPERAND (MTACC_T, *ip, regno); |
ef2e4d86 CF |
8704 | continue; |
8705 | } | |
8706 | else | |
8707 | as_bad (_("Invalid dsp/smartmips acc register")); | |
8708 | break; | |
8709 | ||
8710 | case '&': /* four dsp accumulators in bits 13,14 */ | |
8711 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
8712 | s[3] >= '0' && s[3] <= '3') | |
8713 | { | |
8714 | regno = s[3] - '0'; | |
8715 | s += 4; | |
a9e24354 | 8716 | INSERT_OPERAND (MTACC_D, *ip, regno); |
ef2e4d86 CF |
8717 | continue; |
8718 | } | |
8719 | else | |
8720 | as_bad (_("Invalid dsp/smartmips acc register")); | |
8721 | break; | |
8722 | ||
252b5132 | 8723 | case ',': |
a339155f | 8724 | ++argnum; |
252b5132 RH |
8725 | if (*s++ == *args) |
8726 | continue; | |
8727 | s--; | |
8728 | switch (*++args) | |
8729 | { | |
8730 | case 'r': | |
8731 | case 'v': | |
bf12938e | 8732 | INSERT_OPERAND (RS, *ip, lastregno); |
252b5132 RH |
8733 | continue; |
8734 | ||
8735 | case 'w': | |
bf12938e | 8736 | INSERT_OPERAND (RT, *ip, lastregno); |
38487616 TS |
8737 | continue; |
8738 | ||
252b5132 | 8739 | case 'W': |
bf12938e | 8740 | INSERT_OPERAND (FT, *ip, lastregno); |
252b5132 RH |
8741 | continue; |
8742 | ||
8743 | case 'V': | |
bf12938e | 8744 | INSERT_OPERAND (FS, *ip, lastregno); |
252b5132 RH |
8745 | continue; |
8746 | } | |
8747 | break; | |
8748 | ||
8749 | case '(': | |
8750 | /* Handle optional base register. | |
8751 | Either the base register is omitted or | |
bdaaa2e1 | 8752 | we must have a left paren. */ |
252b5132 RH |
8753 | /* This is dependent on the next operand specifier |
8754 | is a base register specification. */ | |
8755 | assert (args[1] == 'b' || args[1] == '5' | |
8756 | || args[1] == '-' || args[1] == '4'); | |
8757 | if (*s == '\0') | |
8758 | return; | |
8759 | ||
8760 | case ')': /* these must match exactly */ | |
60b63b72 RS |
8761 | case '[': |
8762 | case ']': | |
252b5132 RH |
8763 | if (*s++ == *args) |
8764 | continue; | |
8765 | break; | |
8766 | ||
af7ee8bf CD |
8767 | case '+': /* Opcode extension character. */ |
8768 | switch (*++args) | |
8769 | { | |
9bcd4f99 TS |
8770 | case '1': /* UDI immediates. */ |
8771 | case '2': | |
8772 | case '3': | |
8773 | case '4': | |
8774 | { | |
8775 | const struct mips_immed *imm = mips_immed; | |
8776 | ||
8777 | while (imm->type && imm->type != *args) | |
8778 | ++imm; | |
8779 | if (! imm->type) | |
8780 | internalError (); | |
8781 | my_getExpression (&imm_expr, s); | |
8782 | check_absolute_expr (ip, &imm_expr); | |
8783 | if ((unsigned long) imm_expr.X_add_number & ~imm->mask) | |
8784 | { | |
8785 | as_warn (_("Illegal %s number (%lu, 0x%lx)"), | |
8786 | imm->desc ? imm->desc : ip->insn_mo->name, | |
8787 | (unsigned long) imm_expr.X_add_number, | |
8788 | (unsigned long) imm_expr.X_add_number); | |
8789 | imm_expr.X_add_number &= imm->mask; | |
8790 | } | |
8791 | ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number | |
8792 | << imm->shift); | |
8793 | imm_expr.X_op = O_absent; | |
8794 | s = expr_end; | |
8795 | } | |
8796 | continue; | |
8797 | ||
071742cf CD |
8798 | case 'A': /* ins/ext position, becomes LSB. */ |
8799 | limlo = 0; | |
8800 | limhi = 31; | |
5f74bc13 CD |
8801 | goto do_lsb; |
8802 | case 'E': | |
8803 | limlo = 32; | |
8804 | limhi = 63; | |
8805 | goto do_lsb; | |
8806 | do_lsb: | |
071742cf CD |
8807 | my_getExpression (&imm_expr, s); |
8808 | check_absolute_expr (ip, &imm_expr); | |
8809 | if ((unsigned long) imm_expr.X_add_number < limlo | |
8810 | || (unsigned long) imm_expr.X_add_number > limhi) | |
8811 | { | |
8812 | as_bad (_("Improper position (%lu)"), | |
8813 | (unsigned long) imm_expr.X_add_number); | |
8814 | imm_expr.X_add_number = limlo; | |
8815 | } | |
8816 | lastpos = imm_expr.X_add_number; | |
bf12938e | 8817 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); |
071742cf CD |
8818 | imm_expr.X_op = O_absent; |
8819 | s = expr_end; | |
8820 | continue; | |
8821 | ||
8822 | case 'B': /* ins size, becomes MSB. */ | |
8823 | limlo = 1; | |
8824 | limhi = 32; | |
5f74bc13 CD |
8825 | goto do_msb; |
8826 | case 'F': | |
8827 | limlo = 33; | |
8828 | limhi = 64; | |
8829 | goto do_msb; | |
8830 | do_msb: | |
071742cf CD |
8831 | my_getExpression (&imm_expr, s); |
8832 | check_absolute_expr (ip, &imm_expr); | |
8833 | /* Check for negative input so that small negative numbers | |
8834 | will not succeed incorrectly. The checks against | |
8835 | (pos+size) transitively check "size" itself, | |
8836 | assuming that "pos" is reasonable. */ | |
8837 | if ((long) imm_expr.X_add_number < 0 | |
8838 | || ((unsigned long) imm_expr.X_add_number | |
8839 | + lastpos) < limlo | |
8840 | || ((unsigned long) imm_expr.X_add_number | |
8841 | + lastpos) > limhi) | |
8842 | { | |
8843 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
8844 | (unsigned long) imm_expr.X_add_number, | |
8845 | (unsigned long) lastpos); | |
8846 | imm_expr.X_add_number = limlo - lastpos; | |
8847 | } | |
bf12938e RS |
8848 | INSERT_OPERAND (INSMSB, *ip, |
8849 | lastpos + imm_expr.X_add_number - 1); | |
071742cf CD |
8850 | imm_expr.X_op = O_absent; |
8851 | s = expr_end; | |
8852 | continue; | |
8853 | ||
8854 | case 'C': /* ext size, becomes MSBD. */ | |
8855 | limlo = 1; | |
8856 | limhi = 32; | |
5f74bc13 CD |
8857 | goto do_msbd; |
8858 | case 'G': | |
8859 | limlo = 33; | |
8860 | limhi = 64; | |
8861 | goto do_msbd; | |
8862 | case 'H': | |
8863 | limlo = 33; | |
8864 | limhi = 64; | |
8865 | goto do_msbd; | |
8866 | do_msbd: | |
071742cf CD |
8867 | my_getExpression (&imm_expr, s); |
8868 | check_absolute_expr (ip, &imm_expr); | |
8869 | /* Check for negative input so that small negative numbers | |
8870 | will not succeed incorrectly. The checks against | |
8871 | (pos+size) transitively check "size" itself, | |
8872 | assuming that "pos" is reasonable. */ | |
8873 | if ((long) imm_expr.X_add_number < 0 | |
8874 | || ((unsigned long) imm_expr.X_add_number | |
8875 | + lastpos) < limlo | |
8876 | || ((unsigned long) imm_expr.X_add_number | |
8877 | + lastpos) > limhi) | |
8878 | { | |
8879 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
8880 | (unsigned long) imm_expr.X_add_number, | |
8881 | (unsigned long) lastpos); | |
8882 | imm_expr.X_add_number = limlo - lastpos; | |
8883 | } | |
bf12938e | 8884 | INSERT_OPERAND (EXTMSBD, *ip, imm_expr.X_add_number - 1); |
071742cf CD |
8885 | imm_expr.X_op = O_absent; |
8886 | s = expr_end; | |
8887 | continue; | |
af7ee8bf | 8888 | |
bbcc0807 CD |
8889 | case 'D': |
8890 | /* +D is for disassembly only; never match. */ | |
8891 | break; | |
8892 | ||
5f74bc13 CD |
8893 | case 'I': |
8894 | /* "+I" is like "I", except that imm2_expr is used. */ | |
8895 | my_getExpression (&imm2_expr, s); | |
8896 | if (imm2_expr.X_op != O_big | |
8897 | && imm2_expr.X_op != O_constant) | |
8898 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
8899 | if (HAVE_32BIT_GPRS) |
8900 | normalize_constant_expr (&imm2_expr); | |
5f74bc13 CD |
8901 | s = expr_end; |
8902 | continue; | |
8903 | ||
707bfff6 | 8904 | case 'T': /* Coprocessor register. */ |
ef2e4d86 CF |
8905 | /* +T is for disassembly only; never match. */ |
8906 | break; | |
8907 | ||
707bfff6 | 8908 | case 't': /* Coprocessor register number. */ |
ef2e4d86 CF |
8909 | if (s[0] == '$' && ISDIGIT (s[1])) |
8910 | { | |
8911 | ++s; | |
8912 | regno = 0; | |
8913 | do | |
8914 | { | |
8915 | regno *= 10; | |
8916 | regno += *s - '0'; | |
8917 | ++s; | |
8918 | } | |
8919 | while (ISDIGIT (*s)); | |
8920 | if (regno > 31) | |
8921 | as_bad (_("Invalid register number (%d)"), regno); | |
8922 | else | |
8923 | { | |
a9e24354 | 8924 | INSERT_OPERAND (RT, *ip, regno); |
ef2e4d86 CF |
8925 | continue; |
8926 | } | |
8927 | } | |
8928 | else | |
8929 | as_bad (_("Invalid coprocessor 0 register number")); | |
8930 | break; | |
8931 | ||
af7ee8bf CD |
8932 | default: |
8933 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
8934 | *args, insn->name, insn->args); | |
8935 | /* Further processing is fruitless. */ | |
8936 | return; | |
8937 | } | |
8938 | break; | |
8939 | ||
252b5132 RH |
8940 | case '<': /* must be at least one digit */ |
8941 | /* | |
8942 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
8943 | * than 31 or less than 0, then the shift amount should be |
8944 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
8945 | * We issue a warning and mask out all but the low 5 bits. |
8946 | */ | |
8947 | my_getExpression (&imm_expr, s); | |
8948 | check_absolute_expr (ip, &imm_expr); | |
8949 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
8950 | as_warn (_("Improper shift amount (%lu)"), |
8951 | (unsigned long) imm_expr.X_add_number); | |
8952 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); | |
252b5132 RH |
8953 | imm_expr.X_op = O_absent; |
8954 | s = expr_end; | |
8955 | continue; | |
8956 | ||
8957 | case '>': /* shift amount minus 32 */ | |
8958 | my_getExpression (&imm_expr, s); | |
8959 | check_absolute_expr (ip, &imm_expr); | |
8960 | if ((unsigned long) imm_expr.X_add_number < 32 | |
8961 | || (unsigned long) imm_expr.X_add_number > 63) | |
8962 | break; | |
bf12938e | 8963 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number - 32); |
252b5132 RH |
8964 | imm_expr.X_op = O_absent; |
8965 | s = expr_end; | |
8966 | continue; | |
8967 | ||
252b5132 RH |
8968 | case 'k': /* cache code */ |
8969 | case 'h': /* prefx code */ | |
8970 | my_getExpression (&imm_expr, s); | |
8971 | check_absolute_expr (ip, &imm_expr); | |
8972 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
8973 | as_warn (_("Invalid value for `%s' (%lu)"), |
8974 | ip->insn_mo->name, | |
8975 | (unsigned long) imm_expr.X_add_number); | |
252b5132 | 8976 | if (*args == 'k') |
bf12938e | 8977 | INSERT_OPERAND (CACHE, *ip, imm_expr.X_add_number); |
252b5132 | 8978 | else |
bf12938e | 8979 | INSERT_OPERAND (PREFX, *ip, imm_expr.X_add_number); |
252b5132 RH |
8980 | imm_expr.X_op = O_absent; |
8981 | s = expr_end; | |
8982 | continue; | |
8983 | ||
8984 | case 'c': /* break code */ | |
8985 | my_getExpression (&imm_expr, s); | |
8986 | check_absolute_expr (ip, &imm_expr); | |
a9e24354 TS |
8987 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE) |
8988 | as_warn (_("Code for %s not in range 0..1023 (%lu)"), | |
8989 | ip->insn_mo->name, | |
bf12938e RS |
8990 | (unsigned long) imm_expr.X_add_number); |
8991 | INSERT_OPERAND (CODE, *ip, imm_expr.X_add_number); | |
252b5132 RH |
8992 | imm_expr.X_op = O_absent; |
8993 | s = expr_end; | |
8994 | continue; | |
8995 | ||
8996 | case 'q': /* lower break code */ | |
8997 | my_getExpression (&imm_expr, s); | |
8998 | check_absolute_expr (ip, &imm_expr); | |
a9e24354 TS |
8999 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE2) |
9000 | as_warn (_("Lower code for %s not in range 0..1023 (%lu)"), | |
9001 | ip->insn_mo->name, | |
bf12938e RS |
9002 | (unsigned long) imm_expr.X_add_number); |
9003 | INSERT_OPERAND (CODE2, *ip, imm_expr.X_add_number); | |
252b5132 RH |
9004 | imm_expr.X_op = O_absent; |
9005 | s = expr_end; | |
9006 | continue; | |
9007 | ||
4372b673 | 9008 | case 'B': /* 20-bit syscall/break code. */ |
156c2f8b | 9009 | my_getExpression (&imm_expr, s); |
156c2f8b | 9010 | check_absolute_expr (ip, &imm_expr); |
793b27f4 | 9011 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20) |
a9e24354 TS |
9012 | as_warn (_("Code for %s not in range 0..1048575 (%lu)"), |
9013 | ip->insn_mo->name, | |
793b27f4 | 9014 | (unsigned long) imm_expr.X_add_number); |
bf12938e | 9015 | INSERT_OPERAND (CODE20, *ip, imm_expr.X_add_number); |
252b5132 RH |
9016 | imm_expr.X_op = O_absent; |
9017 | s = expr_end; | |
9018 | continue; | |
9019 | ||
98d3f06f | 9020 | case 'C': /* Coprocessor code */ |
beae10d5 | 9021 | my_getExpression (&imm_expr, s); |
252b5132 | 9022 | check_absolute_expr (ip, &imm_expr); |
a9e24354 | 9023 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_COPZ) |
252b5132 | 9024 | { |
793b27f4 TS |
9025 | as_warn (_("Coproccesor code > 25 bits (%lu)"), |
9026 | (unsigned long) imm_expr.X_add_number); | |
a9e24354 | 9027 | imm_expr.X_add_number &= OP_MASK_COPZ; |
252b5132 | 9028 | } |
a9e24354 | 9029 | INSERT_OPERAND (COPZ, *ip, imm_expr.X_add_number); |
beae10d5 KH |
9030 | imm_expr.X_op = O_absent; |
9031 | s = expr_end; | |
9032 | continue; | |
252b5132 | 9033 | |
4372b673 NC |
9034 | case 'J': /* 19-bit wait code. */ |
9035 | my_getExpression (&imm_expr, s); | |
9036 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 9037 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
a9e24354 TS |
9038 | { |
9039 | as_warn (_("Illegal 19-bit code (%lu)"), | |
9040 | (unsigned long) imm_expr.X_add_number); | |
9041 | imm_expr.X_add_number &= OP_MASK_CODE19; | |
9042 | } | |
bf12938e | 9043 | INSERT_OPERAND (CODE19, *ip, imm_expr.X_add_number); |
4372b673 NC |
9044 | imm_expr.X_op = O_absent; |
9045 | s = expr_end; | |
9046 | continue; | |
9047 | ||
707bfff6 | 9048 | case 'P': /* Performance register. */ |
beae10d5 | 9049 | my_getExpression (&imm_expr, s); |
252b5132 | 9050 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 9051 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
bf12938e RS |
9052 | as_warn (_("Invalid performance register (%lu)"), |
9053 | (unsigned long) imm_expr.X_add_number); | |
9054 | INSERT_OPERAND (PERFREG, *ip, imm_expr.X_add_number); | |
beae10d5 KH |
9055 | imm_expr.X_op = O_absent; |
9056 | s = expr_end; | |
9057 | continue; | |
252b5132 | 9058 | |
707bfff6 TS |
9059 | case 'G': /* Coprocessor destination register. */ |
9060 | if (((ip->insn_opcode >> OP_SH_OP) & OP_MASK_OP) == OP_OP_COP0) | |
9061 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_CP0, ®no); | |
9062 | else | |
9063 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
a9e24354 | 9064 | INSERT_OPERAND (RD, *ip, regno); |
707bfff6 TS |
9065 | if (ok) |
9066 | { | |
9067 | lastregno = regno; | |
9068 | continue; | |
9069 | } | |
9070 | else | |
9071 | break; | |
9072 | ||
252b5132 RH |
9073 | case 'b': /* base register */ |
9074 | case 'd': /* destination register */ | |
9075 | case 's': /* source register */ | |
9076 | case 't': /* target register */ | |
9077 | case 'r': /* both target and source */ | |
9078 | case 'v': /* both dest and source */ | |
9079 | case 'w': /* both dest and target */ | |
9080 | case 'E': /* coprocessor target register */ | |
af7ee8bf | 9081 | case 'K': /* 'rdhwr' destination register */ |
252b5132 RH |
9082 | case 'x': /* ignore register name */ |
9083 | case 'z': /* must be zero register */ | |
4372b673 | 9084 | case 'U': /* destination register (clo/clz). */ |
ef2e4d86 | 9085 | case 'g': /* coprocessor destination register */ |
707bfff6 TS |
9086 | s_reset = s; |
9087 | if (*args == 'E' || *args == 'K') | |
9088 | ok = reg_lookup (&s, RTYPE_NUM, ®no); | |
9089 | else | |
9090 | { | |
9091 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
9092 | if (regno == AT && ! mips_opts.noat) | |
9093 | as_warn ("Used $at without \".set noat\""); | |
9094 | } | |
9095 | if (ok) | |
252b5132 | 9096 | { |
252b5132 RH |
9097 | c = *args; |
9098 | if (*s == ' ') | |
f9419b05 | 9099 | ++s; |
252b5132 RH |
9100 | if (args[1] != *s) |
9101 | { | |
9102 | if (c == 'r' || c == 'v' || c == 'w') | |
9103 | { | |
9104 | regno = lastregno; | |
9105 | s = s_reset; | |
f9419b05 | 9106 | ++args; |
252b5132 RH |
9107 | } |
9108 | } | |
9109 | /* 'z' only matches $0. */ | |
9110 | if (c == 'z' && regno != 0) | |
9111 | break; | |
9112 | ||
bdaaa2e1 KH |
9113 | /* Now that we have assembled one operand, we use the args string |
9114 | * to figure out where it goes in the instruction. */ | |
252b5132 RH |
9115 | switch (c) |
9116 | { | |
9117 | case 'r': | |
9118 | case 's': | |
9119 | case 'v': | |
9120 | case 'b': | |
bf12938e | 9121 | INSERT_OPERAND (RS, *ip, regno); |
252b5132 RH |
9122 | break; |
9123 | case 'd': | |
9124 | case 'G': | |
af7ee8bf | 9125 | case 'K': |
ef2e4d86 | 9126 | case 'g': |
bf12938e | 9127 | INSERT_OPERAND (RD, *ip, regno); |
252b5132 | 9128 | break; |
4372b673 | 9129 | case 'U': |
bf12938e RS |
9130 | INSERT_OPERAND (RD, *ip, regno); |
9131 | INSERT_OPERAND (RT, *ip, regno); | |
4372b673 | 9132 | break; |
252b5132 RH |
9133 | case 'w': |
9134 | case 't': | |
9135 | case 'E': | |
bf12938e | 9136 | INSERT_OPERAND (RT, *ip, regno); |
252b5132 RH |
9137 | break; |
9138 | case 'x': | |
9139 | /* This case exists because on the r3000 trunc | |
9140 | expands into a macro which requires a gp | |
9141 | register. On the r6000 or r4000 it is | |
9142 | assembled into a single instruction which | |
9143 | ignores the register. Thus the insn version | |
9144 | is MIPS_ISA2 and uses 'x', and the macro | |
9145 | version is MIPS_ISA1 and uses 't'. */ | |
9146 | break; | |
9147 | case 'z': | |
9148 | /* This case is for the div instruction, which | |
9149 | acts differently if the destination argument | |
9150 | is $0. This only matches $0, and is checked | |
9151 | outside the switch. */ | |
9152 | break; | |
9153 | case 'D': | |
9154 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
9155 | break; | |
9156 | /* What about all other operands like 'i', which | |
9157 | can be specified in the opcode table? */ | |
9158 | } | |
9159 | lastregno = regno; | |
9160 | continue; | |
9161 | } | |
252b5132 RH |
9162 | switch (*args++) |
9163 | { | |
9164 | case 'r': | |
9165 | case 'v': | |
bf12938e | 9166 | INSERT_OPERAND (RS, *ip, lastregno); |
252b5132 RH |
9167 | continue; |
9168 | case 'w': | |
bf12938e | 9169 | INSERT_OPERAND (RT, *ip, lastregno); |
252b5132 RH |
9170 | continue; |
9171 | } | |
9172 | break; | |
9173 | ||
deec1734 CD |
9174 | case 'O': /* MDMX alignment immediate constant. */ |
9175 | my_getExpression (&imm_expr, s); | |
9176 | check_absolute_expr (ip, &imm_expr); | |
9177 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
bf12938e RS |
9178 | as_warn ("Improper align amount (%ld), using low bits", |
9179 | (long) imm_expr.X_add_number); | |
9180 | INSERT_OPERAND (ALN, *ip, imm_expr.X_add_number); | |
deec1734 CD |
9181 | imm_expr.X_op = O_absent; |
9182 | s = expr_end; | |
9183 | continue; | |
9184 | ||
9185 | case 'Q': /* MDMX vector, element sel, or const. */ | |
9186 | if (s[0] != '$') | |
9187 | { | |
9188 | /* MDMX Immediate. */ | |
9189 | my_getExpression (&imm_expr, s); | |
9190 | check_absolute_expr (ip, &imm_expr); | |
9191 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
bf12938e RS |
9192 | as_warn (_("Invalid MDMX Immediate (%ld)"), |
9193 | (long) imm_expr.X_add_number); | |
9194 | INSERT_OPERAND (FT, *ip, imm_expr.X_add_number); | |
deec1734 CD |
9195 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) |
9196 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
9197 | else | |
9198 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
deec1734 CD |
9199 | imm_expr.X_op = O_absent; |
9200 | s = expr_end; | |
9201 | continue; | |
9202 | } | |
9203 | /* Not MDMX Immediate. Fall through. */ | |
9204 | case 'X': /* MDMX destination register. */ | |
9205 | case 'Y': /* MDMX source register. */ | |
9206 | case 'Z': /* MDMX target register. */ | |
9207 | is_mdmx = 1; | |
252b5132 RH |
9208 | case 'D': /* floating point destination register */ |
9209 | case 'S': /* floating point source register */ | |
9210 | case 'T': /* floating point target register */ | |
9211 | case 'R': /* floating point source register */ | |
9212 | case 'V': | |
9213 | case 'W': | |
707bfff6 TS |
9214 | rtype = RTYPE_FPU; |
9215 | if (is_mdmx | |
9216 | || (mips_opts.ase_mdmx | |
9217 | && (ip->insn_mo->pinfo & FP_D) | |
9218 | && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY | |
9219 | | INSN_COPROC_MEMORY_DELAY | |
9220 | | INSN_LOAD_COPROC_DELAY | |
9221 | | INSN_LOAD_MEMORY_DELAY | |
9222 | | INSN_STORE_MEMORY)))) | |
9223 | rtype |= RTYPE_VEC; | |
252b5132 | 9224 | s_reset = s; |
707bfff6 | 9225 | if (reg_lookup (&s, rtype, ®no)) |
252b5132 | 9226 | { |
252b5132 | 9227 | if ((regno & 1) != 0 |
ca4e0257 | 9228 | && HAVE_32BIT_FPRS |
7455baf8 | 9229 | && ! mips_oddfpreg_ok (ip->insn_mo, argnum)) |
252b5132 RH |
9230 | as_warn (_("Float register should be even, was %d"), |
9231 | regno); | |
9232 | ||
9233 | c = *args; | |
9234 | if (*s == ' ') | |
f9419b05 | 9235 | ++s; |
252b5132 RH |
9236 | if (args[1] != *s) |
9237 | { | |
9238 | if (c == 'V' || c == 'W') | |
9239 | { | |
9240 | regno = lastregno; | |
9241 | s = s_reset; | |
f9419b05 | 9242 | ++args; |
252b5132 RH |
9243 | } |
9244 | } | |
9245 | switch (c) | |
9246 | { | |
9247 | case 'D': | |
deec1734 | 9248 | case 'X': |
bf12938e | 9249 | INSERT_OPERAND (FD, *ip, regno); |
252b5132 RH |
9250 | break; |
9251 | case 'V': | |
9252 | case 'S': | |
deec1734 | 9253 | case 'Y': |
bf12938e | 9254 | INSERT_OPERAND (FS, *ip, regno); |
252b5132 | 9255 | break; |
deec1734 CD |
9256 | case 'Q': |
9257 | /* This is like 'Z', but also needs to fix the MDMX | |
9258 | vector/scalar select bits. Note that the | |
9259 | scalar immediate case is handled above. */ | |
9260 | if (*s == '[') | |
9261 | { | |
9262 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
9263 | int max_el = (is_qh ? 3 : 7); | |
9264 | s++; | |
9265 | my_getExpression(&imm_expr, s); | |
9266 | check_absolute_expr (ip, &imm_expr); | |
9267 | s = expr_end; | |
9268 | if (imm_expr.X_add_number > max_el) | |
9269 | as_bad(_("Bad element selector %ld"), | |
9270 | (long) imm_expr.X_add_number); | |
9271 | imm_expr.X_add_number &= max_el; | |
9272 | ip->insn_opcode |= (imm_expr.X_add_number | |
9273 | << (OP_SH_VSEL + | |
9274 | (is_qh ? 2 : 1))); | |
01a3f561 | 9275 | imm_expr.X_op = O_absent; |
deec1734 CD |
9276 | if (*s != ']') |
9277 | as_warn(_("Expecting ']' found '%s'"), s); | |
9278 | else | |
9279 | s++; | |
9280 | } | |
9281 | else | |
9282 | { | |
9283 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
9284 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
9285 | << OP_SH_VSEL); | |
9286 | else | |
9287 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
9288 | OP_SH_VSEL); | |
9289 | } | |
9290 | /* Fall through */ | |
252b5132 RH |
9291 | case 'W': |
9292 | case 'T': | |
deec1734 | 9293 | case 'Z': |
bf12938e | 9294 | INSERT_OPERAND (FT, *ip, regno); |
252b5132 RH |
9295 | break; |
9296 | case 'R': | |
bf12938e | 9297 | INSERT_OPERAND (FR, *ip, regno); |
252b5132 RH |
9298 | break; |
9299 | } | |
9300 | lastregno = regno; | |
9301 | continue; | |
9302 | } | |
9303 | ||
252b5132 RH |
9304 | switch (*args++) |
9305 | { | |
9306 | case 'V': | |
bf12938e | 9307 | INSERT_OPERAND (FS, *ip, lastregno); |
252b5132 RH |
9308 | continue; |
9309 | case 'W': | |
bf12938e | 9310 | INSERT_OPERAND (FT, *ip, lastregno); |
252b5132 RH |
9311 | continue; |
9312 | } | |
9313 | break; | |
9314 | ||
9315 | case 'I': | |
9316 | my_getExpression (&imm_expr, s); | |
9317 | if (imm_expr.X_op != O_big | |
9318 | && imm_expr.X_op != O_constant) | |
9319 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
9320 | if (HAVE_32BIT_GPRS) |
9321 | normalize_constant_expr (&imm_expr); | |
252b5132 RH |
9322 | s = expr_end; |
9323 | continue; | |
9324 | ||
9325 | case 'A': | |
9326 | my_getExpression (&offset_expr, s); | |
2051e8c4 | 9327 | normalize_address_expr (&offset_expr); |
f6688943 | 9328 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
9329 | s = expr_end; |
9330 | continue; | |
9331 | ||
9332 | case 'F': | |
9333 | case 'L': | |
9334 | case 'f': | |
9335 | case 'l': | |
9336 | { | |
9337 | int f64; | |
ca4e0257 | 9338 | int using_gprs; |
252b5132 RH |
9339 | char *save_in; |
9340 | char *err; | |
9341 | unsigned char temp[8]; | |
9342 | int len; | |
9343 | unsigned int length; | |
9344 | segT seg; | |
9345 | subsegT subseg; | |
9346 | char *p; | |
9347 | ||
9348 | /* These only appear as the last operand in an | |
9349 | instruction, and every instruction that accepts | |
9350 | them in any variant accepts them in all variants. | |
9351 | This means we don't have to worry about backing out | |
9352 | any changes if the instruction does not match. | |
9353 | ||
9354 | The difference between them is the size of the | |
9355 | floating point constant and where it goes. For 'F' | |
9356 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
9357 | is 32 bits. Where the constant is placed is based | |
9358 | on how the MIPS assembler does things: | |
9359 | F -- .rdata | |
9360 | L -- .lit8 | |
9361 | f -- immediate value | |
9362 | l -- .lit4 | |
9363 | ||
9364 | The .lit4 and .lit8 sections are only used if | |
9365 | permitted by the -G argument. | |
9366 | ||
ca4e0257 RS |
9367 | The code below needs to know whether the target register |
9368 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
9369 | 'F' are used with GPR-based instructions and 'l' and | |
9370 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
9371 | |
9372 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 9373 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
9374 | |
9375 | save_in = input_line_pointer; | |
9376 | input_line_pointer = s; | |
9377 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
9378 | length = len; | |
9379 | s = input_line_pointer; | |
9380 | input_line_pointer = save_in; | |
9381 | if (err != NULL && *err != '\0') | |
9382 | { | |
9383 | as_bad (_("Bad floating point constant: %s"), err); | |
9384 | memset (temp, '\0', sizeof temp); | |
9385 | length = f64 ? 8 : 4; | |
9386 | } | |
9387 | ||
156c2f8b | 9388 | assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
9389 | |
9390 | if (*args == 'f' | |
9391 | || (*args == 'l' | |
3e722fb5 | 9392 | && (g_switch_value < 4 |
252b5132 RH |
9393 | || (temp[0] == 0 && temp[1] == 0) |
9394 | || (temp[2] == 0 && temp[3] == 0)))) | |
9395 | { | |
9396 | imm_expr.X_op = O_constant; | |
9397 | if (! target_big_endian) | |
9398 | imm_expr.X_add_number = bfd_getl32 (temp); | |
9399 | else | |
9400 | imm_expr.X_add_number = bfd_getb32 (temp); | |
9401 | } | |
9402 | else if (length > 4 | |
119d663a | 9403 | && ! mips_disable_float_construction |
ca4e0257 RS |
9404 | /* Constants can only be constructed in GPRs and |
9405 | copied to FPRs if the GPRs are at least as wide | |
9406 | as the FPRs. Force the constant into memory if | |
9407 | we are using 64-bit FPRs but the GPRs are only | |
9408 | 32 bits wide. */ | |
9409 | && (using_gprs | |
9410 | || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) | |
252b5132 RH |
9411 | && ((temp[0] == 0 && temp[1] == 0) |
9412 | || (temp[2] == 0 && temp[3] == 0)) | |
9413 | && ((temp[4] == 0 && temp[5] == 0) | |
9414 | || (temp[6] == 0 && temp[7] == 0))) | |
9415 | { | |
ca4e0257 RS |
9416 | /* The value is simple enough to load with a couple of |
9417 | instructions. If using 32-bit registers, set | |
9418 | imm_expr to the high order 32 bits and offset_expr to | |
9419 | the low order 32 bits. Otherwise, set imm_expr to | |
9420 | the entire 64 bit constant. */ | |
9421 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) | |
252b5132 RH |
9422 | { |
9423 | imm_expr.X_op = O_constant; | |
9424 | offset_expr.X_op = O_constant; | |
9425 | if (! target_big_endian) | |
9426 | { | |
9427 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
9428 | offset_expr.X_add_number = bfd_getl32 (temp); | |
9429 | } | |
9430 | else | |
9431 | { | |
9432 | imm_expr.X_add_number = bfd_getb32 (temp); | |
9433 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
9434 | } | |
9435 | if (offset_expr.X_add_number == 0) | |
9436 | offset_expr.X_op = O_absent; | |
9437 | } | |
9438 | else if (sizeof (imm_expr.X_add_number) > 4) | |
9439 | { | |
9440 | imm_expr.X_op = O_constant; | |
9441 | if (! target_big_endian) | |
9442 | imm_expr.X_add_number = bfd_getl64 (temp); | |
9443 | else | |
9444 | imm_expr.X_add_number = bfd_getb64 (temp); | |
9445 | } | |
9446 | else | |
9447 | { | |
9448 | imm_expr.X_op = O_big; | |
9449 | imm_expr.X_add_number = 4; | |
9450 | if (! target_big_endian) | |
9451 | { | |
9452 | generic_bignum[0] = bfd_getl16 (temp); | |
9453 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
9454 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
9455 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
9456 | } | |
9457 | else | |
9458 | { | |
9459 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
9460 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
9461 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
9462 | generic_bignum[3] = bfd_getb16 (temp); | |
9463 | } | |
9464 | } | |
9465 | } | |
9466 | else | |
9467 | { | |
9468 | const char *newname; | |
9469 | segT new_seg; | |
9470 | ||
9471 | /* Switch to the right section. */ | |
9472 | seg = now_seg; | |
9473 | subseg = now_subseg; | |
9474 | switch (*args) | |
9475 | { | |
9476 | default: /* unused default case avoids warnings. */ | |
9477 | case 'L': | |
9478 | newname = RDATA_SECTION_NAME; | |
3e722fb5 | 9479 | if (g_switch_value >= 8) |
252b5132 RH |
9480 | newname = ".lit8"; |
9481 | break; | |
9482 | case 'F': | |
3e722fb5 | 9483 | newname = RDATA_SECTION_NAME; |
252b5132 RH |
9484 | break; |
9485 | case 'l': | |
4d0d148d | 9486 | assert (g_switch_value >= 4); |
252b5132 RH |
9487 | newname = ".lit4"; |
9488 | break; | |
9489 | } | |
9490 | new_seg = subseg_new (newname, (subsegT) 0); | |
f43abd2b | 9491 | if (IS_ELF) |
252b5132 RH |
9492 | bfd_set_section_flags (stdoutput, new_seg, |
9493 | (SEC_ALLOC | |
9494 | | SEC_LOAD | |
9495 | | SEC_READONLY | |
9496 | | SEC_DATA)); | |
9497 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
f43abd2b | 9498 | if (IS_ELF && strcmp (TARGET_OS, "elf") != 0) |
252b5132 RH |
9499 | record_alignment (new_seg, 4); |
9500 | else | |
9501 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
9502 | if (seg == now_seg) | |
9503 | as_bad (_("Can't use floating point insn in this section")); | |
9504 | ||
9505 | /* Set the argument to the current address in the | |
9506 | section. */ | |
9507 | offset_expr.X_op = O_symbol; | |
9508 | offset_expr.X_add_symbol = | |
9509 | symbol_new ("L0\001", now_seg, | |
9510 | (valueT) frag_now_fix (), frag_now); | |
9511 | offset_expr.X_add_number = 0; | |
9512 | ||
9513 | /* Put the floating point number into the section. */ | |
9514 | p = frag_more ((int) length); | |
9515 | memcpy (p, temp, length); | |
9516 | ||
9517 | /* Switch back to the original section. */ | |
9518 | subseg_set (seg, subseg); | |
9519 | } | |
9520 | } | |
9521 | continue; | |
9522 | ||
9523 | case 'i': /* 16 bit unsigned immediate */ | |
9524 | case 'j': /* 16 bit signed immediate */ | |
f6688943 | 9525 | *imm_reloc = BFD_RELOC_LO16; |
5e0116d5 | 9526 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) |
252b5132 RH |
9527 | { |
9528 | int more; | |
5e0116d5 RS |
9529 | offsetT minval, maxval; |
9530 | ||
9531 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] | |
9532 | && strcmp (insn->name, insn[1].name) == 0); | |
9533 | ||
9534 | /* If the expression was written as an unsigned number, | |
9535 | only treat it as signed if there are no more | |
9536 | alternatives. */ | |
9537 | if (more | |
9538 | && *args == 'j' | |
9539 | && sizeof (imm_expr.X_add_number) <= 4 | |
9540 | && imm_expr.X_op == O_constant | |
9541 | && imm_expr.X_add_number < 0 | |
9542 | && imm_expr.X_unsigned | |
9543 | && HAVE_64BIT_GPRS) | |
9544 | break; | |
9545 | ||
9546 | /* For compatibility with older assemblers, we accept | |
9547 | 0x8000-0xffff as signed 16-bit numbers when only | |
9548 | signed numbers are allowed. */ | |
9549 | if (*args == 'i') | |
9550 | minval = 0, maxval = 0xffff; | |
9551 | else if (more) | |
9552 | minval = -0x8000, maxval = 0x7fff; | |
252b5132 | 9553 | else |
5e0116d5 RS |
9554 | minval = -0x8000, maxval = 0xffff; |
9555 | ||
9556 | if (imm_expr.X_op != O_constant | |
9557 | || imm_expr.X_add_number < minval | |
9558 | || imm_expr.X_add_number > maxval) | |
252b5132 RH |
9559 | { |
9560 | if (more) | |
9561 | break; | |
2ae7e77b AH |
9562 | if (imm_expr.X_op == O_constant |
9563 | || imm_expr.X_op == O_big) | |
5e0116d5 | 9564 | as_bad (_("expression out of range")); |
252b5132 RH |
9565 | } |
9566 | } | |
9567 | s = expr_end; | |
9568 | continue; | |
9569 | ||
9570 | case 'o': /* 16 bit offset */ | |
5e0116d5 RS |
9571 | /* Check whether there is only a single bracketed expression |
9572 | left. If so, it must be the base register and the | |
9573 | constant must be zero. */ | |
9574 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
9575 | { | |
9576 | offset_expr.X_op = O_constant; | |
9577 | offset_expr.X_add_number = 0; | |
9578 | continue; | |
9579 | } | |
252b5132 RH |
9580 | |
9581 | /* If this value won't fit into a 16 bit offset, then go | |
9582 | find a macro that will generate the 32 bit offset | |
afdbd6d0 | 9583 | code pattern. */ |
5e0116d5 | 9584 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 |
252b5132 RH |
9585 | && (offset_expr.X_op != O_constant |
9586 | || offset_expr.X_add_number >= 0x8000 | |
afdbd6d0 | 9587 | || offset_expr.X_add_number < -0x8000)) |
252b5132 RH |
9588 | break; |
9589 | ||
252b5132 RH |
9590 | s = expr_end; |
9591 | continue; | |
9592 | ||
9593 | case 'p': /* pc relative offset */ | |
0b25d3e6 | 9594 | *offset_reloc = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
9595 | my_getExpression (&offset_expr, s); |
9596 | s = expr_end; | |
9597 | continue; | |
9598 | ||
9599 | case 'u': /* upper 16 bits */ | |
5e0116d5 RS |
9600 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 |
9601 | && imm_expr.X_op == O_constant | |
9602 | && (imm_expr.X_add_number < 0 | |
9603 | || imm_expr.X_add_number >= 0x10000)) | |
252b5132 RH |
9604 | as_bad (_("lui expression not in range 0..65535")); |
9605 | s = expr_end; | |
9606 | continue; | |
9607 | ||
9608 | case 'a': /* 26 bit address */ | |
9609 | my_getExpression (&offset_expr, s); | |
9610 | s = expr_end; | |
f6688943 | 9611 | *offset_reloc = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
9612 | continue; |
9613 | ||
9614 | case 'N': /* 3 bit branch condition code */ | |
9615 | case 'M': /* 3 bit compare condition code */ | |
707bfff6 TS |
9616 | rtype = RTYPE_CCC; |
9617 | if (ip->insn_mo->pinfo & (FP_D| FP_S)) | |
9618 | rtype |= RTYPE_FCC; | |
9619 | if (!reg_lookup (&s, rtype, ®no)) | |
252b5132 | 9620 | break; |
30c378fd CD |
9621 | if ((strcmp(str + strlen(str) - 3, ".ps") == 0 |
9622 | || strcmp(str + strlen(str) - 5, "any2f") == 0 | |
9623 | || strcmp(str + strlen(str) - 5, "any2t") == 0) | |
9624 | && (regno & 1) != 0) | |
9625 | as_warn(_("Condition code register should be even for %s, was %d"), | |
9626 | str, regno); | |
9627 | if ((strcmp(str + strlen(str) - 5, "any4f") == 0 | |
9628 | || strcmp(str + strlen(str) - 5, "any4t") == 0) | |
9629 | && (regno & 3) != 0) | |
9630 | as_warn(_("Condition code register should be 0 or 4 for %s, was %d"), | |
9631 | str, regno); | |
252b5132 | 9632 | if (*args == 'N') |
bf12938e | 9633 | INSERT_OPERAND (BCC, *ip, regno); |
252b5132 | 9634 | else |
bf12938e | 9635 | INSERT_OPERAND (CCC, *ip, regno); |
beae10d5 | 9636 | continue; |
252b5132 | 9637 | |
156c2f8b NC |
9638 | case 'H': |
9639 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
9640 | s += 2; | |
3882b010 | 9641 | if (ISDIGIT (*s)) |
156c2f8b NC |
9642 | { |
9643 | c = 0; | |
9644 | do | |
9645 | { | |
9646 | c *= 10; | |
9647 | c += *s - '0'; | |
9648 | ++s; | |
9649 | } | |
3882b010 | 9650 | while (ISDIGIT (*s)); |
156c2f8b NC |
9651 | } |
9652 | else | |
9653 | c = 8; /* Invalid sel value. */ | |
9654 | ||
9655 | if (c > 7) | |
9656 | as_bad (_("invalid coprocessor sub-selection value (0-7)")); | |
9657 | ip->insn_opcode |= c; | |
9658 | continue; | |
9659 | ||
60b63b72 RS |
9660 | case 'e': |
9661 | /* Must be at least one digit. */ | |
9662 | my_getExpression (&imm_expr, s); | |
9663 | check_absolute_expr (ip, &imm_expr); | |
9664 | ||
9665 | if ((unsigned long) imm_expr.X_add_number | |
9666 | > (unsigned long) OP_MASK_VECBYTE) | |
9667 | { | |
9668 | as_bad (_("bad byte vector index (%ld)"), | |
9669 | (long) imm_expr.X_add_number); | |
9670 | imm_expr.X_add_number = 0; | |
9671 | } | |
9672 | ||
bf12938e | 9673 | INSERT_OPERAND (VECBYTE, *ip, imm_expr.X_add_number); |
60b63b72 RS |
9674 | imm_expr.X_op = O_absent; |
9675 | s = expr_end; | |
9676 | continue; | |
9677 | ||
9678 | case '%': | |
9679 | my_getExpression (&imm_expr, s); | |
9680 | check_absolute_expr (ip, &imm_expr); | |
9681 | ||
9682 | if ((unsigned long) imm_expr.X_add_number | |
9683 | > (unsigned long) OP_MASK_VECALIGN) | |
9684 | { | |
9685 | as_bad (_("bad byte vector index (%ld)"), | |
9686 | (long) imm_expr.X_add_number); | |
9687 | imm_expr.X_add_number = 0; | |
9688 | } | |
9689 | ||
bf12938e | 9690 | INSERT_OPERAND (VECALIGN, *ip, imm_expr.X_add_number); |
60b63b72 RS |
9691 | imm_expr.X_op = O_absent; |
9692 | s = expr_end; | |
9693 | continue; | |
9694 | ||
252b5132 RH |
9695 | default: |
9696 | as_bad (_("bad char = '%c'\n"), *args); | |
9697 | internalError (); | |
9698 | } | |
9699 | break; | |
9700 | } | |
9701 | /* Args don't match. */ | |
9702 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
9703 | !strcmp (insn->name, insn[1].name)) | |
9704 | { | |
9705 | ++insn; | |
9706 | s = argsStart; | |
268f6bed | 9707 | insn_error = _("illegal operands"); |
252b5132 RH |
9708 | continue; |
9709 | } | |
268f6bed L |
9710 | if (save_c) |
9711 | *(--s) = save_c; | |
252b5132 RH |
9712 | insn_error = _("illegal operands"); |
9713 | return; | |
9714 | } | |
9715 | } | |
9716 | ||
0499d65b TS |
9717 | #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); } |
9718 | ||
252b5132 RH |
9719 | /* This routine assembles an instruction into its binary format when |
9720 | assembling for the mips16. As a side effect, it sets one of the | |
9721 | global variables imm_reloc or offset_reloc to the type of | |
9722 | relocation to do if one of the operands is an address expression. | |
9723 | It also sets mips16_small and mips16_ext if the user explicitly | |
9724 | requested a small or extended instruction. */ | |
9725 | ||
9726 | static void | |
17a2f251 | 9727 | mips16_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
9728 | { |
9729 | char *s; | |
9730 | const char *args; | |
9731 | struct mips_opcode *insn; | |
9732 | char *argsstart; | |
9733 | unsigned int regno; | |
9734 | unsigned int lastregno = 0; | |
9735 | char *s_reset; | |
d6f16593 | 9736 | size_t i; |
252b5132 RH |
9737 | |
9738 | insn_error = NULL; | |
9739 | ||
b34976b6 AM |
9740 | mips16_small = FALSE; |
9741 | mips16_ext = FALSE; | |
252b5132 | 9742 | |
3882b010 | 9743 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
9744 | ; |
9745 | switch (*s) | |
9746 | { | |
9747 | case '\0': | |
9748 | break; | |
9749 | ||
9750 | case ' ': | |
9751 | *s++ = '\0'; | |
9752 | break; | |
9753 | ||
9754 | case '.': | |
9755 | if (s[1] == 't' && s[2] == ' ') | |
9756 | { | |
9757 | *s = '\0'; | |
b34976b6 | 9758 | mips16_small = TRUE; |
252b5132 RH |
9759 | s += 3; |
9760 | break; | |
9761 | } | |
9762 | else if (s[1] == 'e' && s[2] == ' ') | |
9763 | { | |
9764 | *s = '\0'; | |
b34976b6 | 9765 | mips16_ext = TRUE; |
252b5132 RH |
9766 | s += 3; |
9767 | break; | |
9768 | } | |
9769 | /* Fall through. */ | |
9770 | default: | |
9771 | insn_error = _("unknown opcode"); | |
9772 | return; | |
9773 | } | |
9774 | ||
9775 | if (mips_opts.noautoextend && ! mips16_ext) | |
b34976b6 | 9776 | mips16_small = TRUE; |
252b5132 RH |
9777 | |
9778 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
9779 | { | |
9780 | insn_error = _("unrecognized opcode"); | |
9781 | return; | |
9782 | } | |
9783 | ||
9784 | argsstart = s; | |
9785 | for (;;) | |
9786 | { | |
9b3f89ee TS |
9787 | bfd_boolean ok; |
9788 | ||
252b5132 RH |
9789 | assert (strcmp (insn->name, str) == 0); |
9790 | ||
9b3f89ee TS |
9791 | if (OPCODE_IS_MEMBER (insn, mips_opts.isa, mips_opts.arch)) |
9792 | ok = TRUE; | |
9793 | else | |
9794 | ok = FALSE; | |
9795 | ||
9796 | if (! ok) | |
9797 | { | |
9798 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] | |
9799 | && strcmp (insn->name, insn[1].name) == 0) | |
9800 | { | |
9801 | ++insn; | |
9802 | continue; | |
9803 | } | |
9804 | else | |
9805 | { | |
9806 | if (!insn_error) | |
9807 | { | |
9808 | static char buf[100]; | |
9809 | sprintf (buf, | |
9810 | _("opcode not supported on this processor: %s (%s)"), | |
9811 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
9812 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
9813 | insn_error = buf; | |
9814 | } | |
9815 | return; | |
9816 | } | |
9817 | } | |
9818 | ||
1e915849 | 9819 | create_insn (ip, insn); |
252b5132 | 9820 | imm_expr.X_op = O_absent; |
f6688943 TS |
9821 | imm_reloc[0] = BFD_RELOC_UNUSED; |
9822 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
9823 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
5f74bc13 | 9824 | imm2_expr.X_op = O_absent; |
252b5132 | 9825 | offset_expr.X_op = O_absent; |
f6688943 TS |
9826 | offset_reloc[0] = BFD_RELOC_UNUSED; |
9827 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
9828 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
9829 | for (args = insn->args; 1; ++args) |
9830 | { | |
9831 | int c; | |
9832 | ||
9833 | if (*s == ' ') | |
9834 | ++s; | |
9835 | ||
9836 | /* In this switch statement we call break if we did not find | |
9837 | a match, continue if we did find a match, or return if we | |
9838 | are done. */ | |
9839 | ||
9840 | c = *args; | |
9841 | switch (c) | |
9842 | { | |
9843 | case '\0': | |
9844 | if (*s == '\0') | |
9845 | { | |
9846 | /* Stuff the immediate value in now, if we can. */ | |
9847 | if (imm_expr.X_op == O_constant | |
f6688943 | 9848 | && *imm_reloc > BFD_RELOC_UNUSED |
252b5132 RH |
9849 | && insn->pinfo != INSN_MACRO) |
9850 | { | |
d6f16593 MR |
9851 | valueT tmp; |
9852 | ||
9853 | switch (*offset_reloc) | |
9854 | { | |
9855 | case BFD_RELOC_MIPS16_HI16_S: | |
9856 | tmp = (imm_expr.X_add_number + 0x8000) >> 16; | |
9857 | break; | |
9858 | ||
9859 | case BFD_RELOC_MIPS16_HI16: | |
9860 | tmp = imm_expr.X_add_number >> 16; | |
9861 | break; | |
9862 | ||
9863 | case BFD_RELOC_MIPS16_LO16: | |
9864 | tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff) | |
9865 | - 0x8000; | |
9866 | break; | |
9867 | ||
9868 | case BFD_RELOC_UNUSED: | |
9869 | tmp = imm_expr.X_add_number; | |
9870 | break; | |
9871 | ||
9872 | default: | |
9873 | internalError (); | |
9874 | } | |
9875 | *offset_reloc = BFD_RELOC_UNUSED; | |
9876 | ||
c4e7957c | 9877 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
d6f16593 | 9878 | tmp, TRUE, mips16_small, |
252b5132 RH |
9879 | mips16_ext, &ip->insn_opcode, |
9880 | &ip->use_extend, &ip->extend); | |
9881 | imm_expr.X_op = O_absent; | |
f6688943 | 9882 | *imm_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
9883 | } |
9884 | ||
9885 | return; | |
9886 | } | |
9887 | break; | |
9888 | ||
9889 | case ',': | |
9890 | if (*s++ == c) | |
9891 | continue; | |
9892 | s--; | |
9893 | switch (*++args) | |
9894 | { | |
9895 | case 'v': | |
bf12938e | 9896 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 RH |
9897 | continue; |
9898 | case 'w': | |
bf12938e | 9899 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
9900 | continue; |
9901 | } | |
9902 | break; | |
9903 | ||
9904 | case '(': | |
9905 | case ')': | |
9906 | if (*s++ == c) | |
9907 | continue; | |
9908 | break; | |
9909 | ||
9910 | case 'v': | |
9911 | case 'w': | |
9912 | if (s[0] != '$') | |
9913 | { | |
9914 | if (c == 'v') | |
bf12938e | 9915 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 | 9916 | else |
bf12938e | 9917 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
9918 | ++args; |
9919 | continue; | |
9920 | } | |
9921 | /* Fall through. */ | |
9922 | case 'x': | |
9923 | case 'y': | |
9924 | case 'z': | |
9925 | case 'Z': | |
9926 | case '0': | |
9927 | case 'S': | |
9928 | case 'R': | |
9929 | case 'X': | |
9930 | case 'Y': | |
707bfff6 TS |
9931 | s_reset = s; |
9932 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) | |
252b5132 | 9933 | { |
707bfff6 | 9934 | if (c == 'v' || c == 'w') |
85b51719 | 9935 | { |
707bfff6 | 9936 | if (c == 'v') |
a9e24354 | 9937 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
707bfff6 | 9938 | else |
a9e24354 | 9939 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
707bfff6 TS |
9940 | ++args; |
9941 | continue; | |
85b51719 | 9942 | } |
707bfff6 | 9943 | break; |
252b5132 RH |
9944 | } |
9945 | ||
9946 | if (*s == ' ') | |
9947 | ++s; | |
9948 | if (args[1] != *s) | |
9949 | { | |
9950 | if (c == 'v' || c == 'w') | |
9951 | { | |
9952 | regno = mips16_to_32_reg_map[lastregno]; | |
9953 | s = s_reset; | |
f9419b05 | 9954 | ++args; |
252b5132 RH |
9955 | } |
9956 | } | |
9957 | ||
9958 | switch (c) | |
9959 | { | |
9960 | case 'x': | |
9961 | case 'y': | |
9962 | case 'z': | |
9963 | case 'v': | |
9964 | case 'w': | |
9965 | case 'Z': | |
9966 | regno = mips32_to_16_reg_map[regno]; | |
9967 | break; | |
9968 | ||
9969 | case '0': | |
9970 | if (regno != 0) | |
9971 | regno = ILLEGAL_REG; | |
9972 | break; | |
9973 | ||
9974 | case 'S': | |
9975 | if (regno != SP) | |
9976 | regno = ILLEGAL_REG; | |
9977 | break; | |
9978 | ||
9979 | case 'R': | |
9980 | if (regno != RA) | |
9981 | regno = ILLEGAL_REG; | |
9982 | break; | |
9983 | ||
9984 | case 'X': | |
9985 | case 'Y': | |
9986 | if (regno == AT && ! mips_opts.noat) | |
9987 | as_warn (_("used $at without \".set noat\"")); | |
9988 | break; | |
9989 | ||
9990 | default: | |
9991 | internalError (); | |
9992 | } | |
9993 | ||
9994 | if (regno == ILLEGAL_REG) | |
9995 | break; | |
9996 | ||
9997 | switch (c) | |
9998 | { | |
9999 | case 'x': | |
10000 | case 'v': | |
bf12938e | 10001 | MIPS16_INSERT_OPERAND (RX, *ip, regno); |
252b5132 RH |
10002 | break; |
10003 | case 'y': | |
10004 | case 'w': | |
bf12938e | 10005 | MIPS16_INSERT_OPERAND (RY, *ip, regno); |
252b5132 RH |
10006 | break; |
10007 | case 'z': | |
bf12938e | 10008 | MIPS16_INSERT_OPERAND (RZ, *ip, regno); |
252b5132 RH |
10009 | break; |
10010 | case 'Z': | |
bf12938e | 10011 | MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno); |
252b5132 RH |
10012 | case '0': |
10013 | case 'S': | |
10014 | case 'R': | |
10015 | break; | |
10016 | case 'X': | |
bf12938e | 10017 | MIPS16_INSERT_OPERAND (REGR32, *ip, regno); |
252b5132 RH |
10018 | break; |
10019 | case 'Y': | |
10020 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
bf12938e | 10021 | MIPS16_INSERT_OPERAND (REG32R, *ip, regno); |
252b5132 RH |
10022 | break; |
10023 | default: | |
10024 | internalError (); | |
10025 | } | |
10026 | ||
10027 | lastregno = regno; | |
10028 | continue; | |
10029 | ||
10030 | case 'P': | |
10031 | if (strncmp (s, "$pc", 3) == 0) | |
10032 | { | |
10033 | s += 3; | |
10034 | continue; | |
10035 | } | |
10036 | break; | |
10037 | ||
252b5132 RH |
10038 | case '5': |
10039 | case 'H': | |
10040 | case 'W': | |
10041 | case 'D': | |
10042 | case 'j': | |
252b5132 RH |
10043 | case 'V': |
10044 | case 'C': | |
10045 | case 'U': | |
10046 | case 'k': | |
10047 | case 'K': | |
d6f16593 MR |
10048 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); |
10049 | if (i > 0) | |
252b5132 | 10050 | { |
d6f16593 | 10051 | if (imm_expr.X_op != O_constant) |
252b5132 | 10052 | { |
b34976b6 | 10053 | mips16_ext = TRUE; |
b34976b6 | 10054 | ip->use_extend = TRUE; |
252b5132 | 10055 | ip->extend = 0; |
252b5132 | 10056 | } |
d6f16593 MR |
10057 | else |
10058 | { | |
10059 | /* We need to relax this instruction. */ | |
10060 | *offset_reloc = *imm_reloc; | |
10061 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
10062 | } | |
10063 | s = expr_end; | |
10064 | continue; | |
252b5132 | 10065 | } |
d6f16593 MR |
10066 | *imm_reloc = BFD_RELOC_UNUSED; |
10067 | /* Fall through. */ | |
10068 | case '<': | |
10069 | case '>': | |
10070 | case '[': | |
10071 | case ']': | |
10072 | case '4': | |
10073 | case '8': | |
10074 | my_getExpression (&imm_expr, s); | |
252b5132 RH |
10075 | if (imm_expr.X_op == O_register) |
10076 | { | |
10077 | /* What we thought was an expression turned out to | |
10078 | be a register. */ | |
10079 | ||
10080 | if (s[0] == '(' && args[1] == '(') | |
10081 | { | |
10082 | /* It looks like the expression was omitted | |
10083 | before a register indirection, which means | |
10084 | that the expression is implicitly zero. We | |
10085 | still set up imm_expr, so that we handle | |
10086 | explicit extensions correctly. */ | |
10087 | imm_expr.X_op = O_constant; | |
10088 | imm_expr.X_add_number = 0; | |
f6688943 | 10089 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
10090 | continue; |
10091 | } | |
10092 | ||
10093 | break; | |
10094 | } | |
10095 | ||
10096 | /* We need to relax this instruction. */ | |
f6688943 | 10097 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
10098 | s = expr_end; |
10099 | continue; | |
10100 | ||
10101 | case 'p': | |
10102 | case 'q': | |
10103 | case 'A': | |
10104 | case 'B': | |
10105 | case 'E': | |
10106 | /* We use offset_reloc rather than imm_reloc for the PC | |
10107 | relative operands. This lets macros with both | |
10108 | immediate and address operands work correctly. */ | |
10109 | my_getExpression (&offset_expr, s); | |
10110 | ||
10111 | if (offset_expr.X_op == O_register) | |
10112 | break; | |
10113 | ||
10114 | /* We need to relax this instruction. */ | |
f6688943 | 10115 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
10116 | s = expr_end; |
10117 | continue; | |
10118 | ||
10119 | case '6': /* break code */ | |
10120 | my_getExpression (&imm_expr, s); | |
10121 | check_absolute_expr (ip, &imm_expr); | |
10122 | if ((unsigned long) imm_expr.X_add_number > 63) | |
bf12938e RS |
10123 | as_warn (_("Invalid value for `%s' (%lu)"), |
10124 | ip->insn_mo->name, | |
10125 | (unsigned long) imm_expr.X_add_number); | |
10126 | MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number); | |
252b5132 RH |
10127 | imm_expr.X_op = O_absent; |
10128 | s = expr_end; | |
10129 | continue; | |
10130 | ||
10131 | case 'a': /* 26 bit address */ | |
10132 | my_getExpression (&offset_expr, s); | |
10133 | s = expr_end; | |
f6688943 | 10134 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
10135 | ip->insn_opcode <<= 16; |
10136 | continue; | |
10137 | ||
10138 | case 'l': /* register list for entry macro */ | |
10139 | case 'L': /* register list for exit macro */ | |
10140 | { | |
10141 | int mask; | |
10142 | ||
10143 | if (c == 'l') | |
10144 | mask = 0; | |
10145 | else | |
10146 | mask = 7 << 3; | |
10147 | while (*s != '\0') | |
10148 | { | |
707bfff6 | 10149 | unsigned int freg, reg1, reg2; |
252b5132 RH |
10150 | |
10151 | while (*s == ' ' || *s == ',') | |
10152 | ++s; | |
707bfff6 | 10153 | if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
252b5132 | 10154 | freg = 0; |
707bfff6 TS |
10155 | else if (reg_lookup (&s, RTYPE_FPU, ®1)) |
10156 | freg = 1; | |
252b5132 RH |
10157 | else |
10158 | { | |
707bfff6 TS |
10159 | as_bad (_("can't parse register list")); |
10160 | break; | |
252b5132 RH |
10161 | } |
10162 | if (*s == ' ') | |
10163 | ++s; | |
10164 | if (*s != '-') | |
10165 | reg2 = reg1; | |
10166 | else | |
10167 | { | |
10168 | ++s; | |
707bfff6 TS |
10169 | if (!reg_lookup (&s, freg ? RTYPE_FPU |
10170 | : (RTYPE_GP | RTYPE_NUM), ®2)) | |
252b5132 | 10171 | { |
707bfff6 TS |
10172 | as_bad (_("invalid register list")); |
10173 | break; | |
252b5132 RH |
10174 | } |
10175 | } | |
10176 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
10177 | { | |
10178 | mask &= ~ (7 << 3); | |
10179 | mask |= 5 << 3; | |
10180 | } | |
10181 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
10182 | { | |
10183 | mask &= ~ (7 << 3); | |
10184 | mask |= 6 << 3; | |
10185 | } | |
10186 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
10187 | mask |= (reg2 - 3) << 3; | |
10188 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
10189 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 10190 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
10191 | mask |= 1; |
10192 | else | |
10193 | { | |
10194 | as_bad (_("invalid register list")); | |
10195 | break; | |
10196 | } | |
10197 | } | |
10198 | /* The mask is filled in in the opcode table for the | |
10199 | benefit of the disassembler. We remove it before | |
10200 | applying the actual mask. */ | |
10201 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
10202 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
10203 | } | |
10204 | continue; | |
10205 | ||
0499d65b TS |
10206 | case 'm': /* Register list for save insn. */ |
10207 | case 'M': /* Register list for restore insn. */ | |
10208 | { | |
10209 | int opcode = 0; | |
10210 | int framesz = 0, seen_framesz = 0; | |
10211 | int args = 0, statics = 0, sregs = 0; | |
10212 | ||
10213 | while (*s != '\0') | |
10214 | { | |
10215 | unsigned int reg1, reg2; | |
10216 | ||
10217 | SKIP_SPACE_TABS (s); | |
10218 | while (*s == ',') | |
10219 | ++s; | |
10220 | SKIP_SPACE_TABS (s); | |
10221 | ||
10222 | my_getExpression (&imm_expr, s); | |
10223 | if (imm_expr.X_op == O_constant) | |
10224 | { | |
10225 | /* Handle the frame size. */ | |
10226 | if (seen_framesz) | |
10227 | { | |
10228 | as_bad (_("more than one frame size in list")); | |
10229 | break; | |
10230 | } | |
10231 | seen_framesz = 1; | |
10232 | framesz = imm_expr.X_add_number; | |
10233 | imm_expr.X_op = O_absent; | |
10234 | s = expr_end; | |
10235 | continue; | |
10236 | } | |
10237 | ||
707bfff6 | 10238 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
0499d65b TS |
10239 | { |
10240 | as_bad (_("can't parse register list")); | |
10241 | break; | |
10242 | } | |
0499d65b | 10243 | |
707bfff6 TS |
10244 | while (*s == ' ') |
10245 | ++s; | |
10246 | ||
0499d65b TS |
10247 | if (*s != '-') |
10248 | reg2 = reg1; | |
10249 | else | |
10250 | { | |
10251 | ++s; | |
707bfff6 TS |
10252 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2) |
10253 | || reg2 < reg1) | |
0499d65b TS |
10254 | { |
10255 | as_bad (_("can't parse register list")); | |
10256 | break; | |
10257 | } | |
0499d65b TS |
10258 | } |
10259 | ||
10260 | while (reg1 <= reg2) | |
10261 | { | |
10262 | if (reg1 >= 4 && reg1 <= 7) | |
10263 | { | |
3a93f742 | 10264 | if (!seen_framesz) |
0499d65b TS |
10265 | /* args $a0-$a3 */ |
10266 | args |= 1 << (reg1 - 4); | |
10267 | else | |
10268 | /* statics $a0-$a3 */ | |
10269 | statics |= 1 << (reg1 - 4); | |
10270 | } | |
10271 | else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30) | |
10272 | { | |
10273 | /* $s0-$s8 */ | |
10274 | sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16)); | |
10275 | } | |
10276 | else if (reg1 == 31) | |
10277 | { | |
10278 | /* Add $ra to insn. */ | |
10279 | opcode |= 0x40; | |
10280 | } | |
10281 | else | |
10282 | { | |
10283 | as_bad (_("unexpected register in list")); | |
10284 | break; | |
10285 | } | |
10286 | if (++reg1 == 24) | |
10287 | reg1 = 30; | |
10288 | } | |
10289 | } | |
10290 | ||
10291 | /* Encode args/statics combination. */ | |
10292 | if (args & statics) | |
10293 | as_bad (_("arg/static registers overlap")); | |
10294 | else if (args == 0xf) | |
10295 | /* All $a0-$a3 are args. */ | |
10296 | opcode |= MIPS16_ALL_ARGS << 16; | |
10297 | else if (statics == 0xf) | |
10298 | /* All $a0-$a3 are statics. */ | |
10299 | opcode |= MIPS16_ALL_STATICS << 16; | |
10300 | else | |
10301 | { | |
10302 | int narg = 0, nstat = 0; | |
10303 | ||
10304 | /* Count arg registers. */ | |
10305 | while (args & 0x1) | |
10306 | { | |
10307 | args >>= 1; | |
10308 | narg++; | |
10309 | } | |
10310 | if (args != 0) | |
10311 | as_bad (_("invalid arg register list")); | |
10312 | ||
10313 | /* Count static registers. */ | |
10314 | while (statics & 0x8) | |
10315 | { | |
10316 | statics = (statics << 1) & 0xf; | |
10317 | nstat++; | |
10318 | } | |
10319 | if (statics != 0) | |
10320 | as_bad (_("invalid static register list")); | |
10321 | ||
10322 | /* Encode args/statics. */ | |
10323 | opcode |= ((narg << 2) | nstat) << 16; | |
10324 | } | |
10325 | ||
10326 | /* Encode $s0/$s1. */ | |
10327 | if (sregs & (1 << 0)) /* $s0 */ | |
10328 | opcode |= 0x20; | |
10329 | if (sregs & (1 << 1)) /* $s1 */ | |
10330 | opcode |= 0x10; | |
10331 | sregs >>= 2; | |
10332 | ||
10333 | if (sregs != 0) | |
10334 | { | |
10335 | /* Count regs $s2-$s8. */ | |
10336 | int nsreg = 0; | |
10337 | while (sregs & 1) | |
10338 | { | |
10339 | sregs >>= 1; | |
10340 | nsreg++; | |
10341 | } | |
10342 | if (sregs != 0) | |
10343 | as_bad (_("invalid static register list")); | |
10344 | /* Encode $s2-$s8. */ | |
10345 | opcode |= nsreg << 24; | |
10346 | } | |
10347 | ||
10348 | /* Encode frame size. */ | |
10349 | if (!seen_framesz) | |
10350 | as_bad (_("missing frame size")); | |
10351 | else if ((framesz & 7) != 0 || framesz < 0 | |
10352 | || framesz > 0xff * 8) | |
10353 | as_bad (_("invalid frame size")); | |
10354 | else if (framesz != 128 || (opcode >> 16) != 0) | |
10355 | { | |
10356 | framesz /= 8; | |
10357 | opcode |= (((framesz & 0xf0) << 16) | |
10358 | | (framesz & 0x0f)); | |
10359 | } | |
10360 | ||
10361 | /* Finally build the instruction. */ | |
10362 | if ((opcode >> 16) != 0 || framesz == 0) | |
10363 | { | |
10364 | ip->use_extend = TRUE; | |
10365 | ip->extend = opcode >> 16; | |
10366 | } | |
10367 | ip->insn_opcode |= opcode & 0x7f; | |
10368 | } | |
10369 | continue; | |
10370 | ||
252b5132 RH |
10371 | case 'e': /* extend code */ |
10372 | my_getExpression (&imm_expr, s); | |
10373 | check_absolute_expr (ip, &imm_expr); | |
10374 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
10375 | { | |
10376 | as_warn (_("Invalid value for `%s' (%lu)"), | |
10377 | ip->insn_mo->name, | |
10378 | (unsigned long) imm_expr.X_add_number); | |
10379 | imm_expr.X_add_number &= 0x7ff; | |
10380 | } | |
10381 | ip->insn_opcode |= imm_expr.X_add_number; | |
10382 | imm_expr.X_op = O_absent; | |
10383 | s = expr_end; | |
10384 | continue; | |
10385 | ||
10386 | default: | |
10387 | internalError (); | |
10388 | } | |
10389 | break; | |
10390 | } | |
10391 | ||
10392 | /* Args don't match. */ | |
10393 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
10394 | strcmp (insn->name, insn[1].name) == 0) | |
10395 | { | |
10396 | ++insn; | |
10397 | s = argsstart; | |
10398 | continue; | |
10399 | } | |
10400 | ||
10401 | insn_error = _("illegal operands"); | |
10402 | ||
10403 | return; | |
10404 | } | |
10405 | } | |
10406 | ||
10407 | /* This structure holds information we know about a mips16 immediate | |
10408 | argument type. */ | |
10409 | ||
e972090a NC |
10410 | struct mips16_immed_operand |
10411 | { | |
252b5132 RH |
10412 | /* The type code used in the argument string in the opcode table. */ |
10413 | int type; | |
10414 | /* The number of bits in the short form of the opcode. */ | |
10415 | int nbits; | |
10416 | /* The number of bits in the extended form of the opcode. */ | |
10417 | int extbits; | |
10418 | /* The amount by which the short form is shifted when it is used; | |
10419 | for example, the sw instruction has a shift count of 2. */ | |
10420 | int shift; | |
10421 | /* The amount by which the short form is shifted when it is stored | |
10422 | into the instruction code. */ | |
10423 | int op_shift; | |
10424 | /* Non-zero if the short form is unsigned. */ | |
10425 | int unsp; | |
10426 | /* Non-zero if the extended form is unsigned. */ | |
10427 | int extu; | |
10428 | /* Non-zero if the value is PC relative. */ | |
10429 | int pcrel; | |
10430 | }; | |
10431 | ||
10432 | /* The mips16 immediate operand types. */ | |
10433 | ||
10434 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
10435 | { | |
10436 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
10437 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
10438 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
10439 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
10440 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
10441 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10442 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10443 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10444 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10445 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
10446 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10447 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10448 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10449 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
10450 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
10451 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
10452 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
10453 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
10454 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
10455 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
10456 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
10457 | }; | |
10458 | ||
10459 | #define MIPS16_NUM_IMMED \ | |
10460 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
10461 | ||
10462 | /* Handle a mips16 instruction with an immediate value. This or's the | |
10463 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
10464 | whether an extended value is needed; if one is needed, it sets | |
10465 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
10466 | If SMALL is true, an unextended opcode was explicitly requested. | |
10467 | If EXT is true, an extended opcode was explicitly requested. If | |
10468 | WARN is true, warn if EXT does not match reality. */ | |
10469 | ||
10470 | static void | |
17a2f251 TS |
10471 | mips16_immed (char *file, unsigned int line, int type, offsetT val, |
10472 | bfd_boolean warn, bfd_boolean small, bfd_boolean ext, | |
10473 | unsigned long *insn, bfd_boolean *use_extend, | |
10474 | unsigned short *extend) | |
252b5132 | 10475 | { |
3994f87e | 10476 | const struct mips16_immed_operand *op; |
252b5132 | 10477 | int mintiny, maxtiny; |
b34976b6 | 10478 | bfd_boolean needext; |
252b5132 RH |
10479 | |
10480 | op = mips16_immed_operands; | |
10481 | while (op->type != type) | |
10482 | { | |
10483 | ++op; | |
10484 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
10485 | } | |
10486 | ||
10487 | if (op->unsp) | |
10488 | { | |
10489 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
10490 | { | |
10491 | mintiny = 1; | |
10492 | maxtiny = 1 << op->nbits; | |
10493 | } | |
10494 | else | |
10495 | { | |
10496 | mintiny = 0; | |
10497 | maxtiny = (1 << op->nbits) - 1; | |
10498 | } | |
10499 | } | |
10500 | else | |
10501 | { | |
10502 | mintiny = - (1 << (op->nbits - 1)); | |
10503 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
10504 | } | |
10505 | ||
10506 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
10507 | if (type == 'p' || type == 'q') | |
10508 | val /= 2; | |
10509 | ||
10510 | if ((val & ((1 << op->shift) - 1)) != 0 | |
10511 | || val < (mintiny << op->shift) | |
10512 | || val > (maxtiny << op->shift)) | |
b34976b6 | 10513 | needext = TRUE; |
252b5132 | 10514 | else |
b34976b6 | 10515 | needext = FALSE; |
252b5132 RH |
10516 | |
10517 | if (warn && ext && ! needext) | |
beae10d5 KH |
10518 | as_warn_where (file, line, |
10519 | _("extended operand requested but not required")); | |
252b5132 RH |
10520 | if (small && needext) |
10521 | as_bad_where (file, line, _("invalid unextended operand value")); | |
10522 | ||
10523 | if (small || (! ext && ! needext)) | |
10524 | { | |
10525 | int insnval; | |
10526 | ||
b34976b6 | 10527 | *use_extend = FALSE; |
252b5132 RH |
10528 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
10529 | insnval <<= op->op_shift; | |
10530 | *insn |= insnval; | |
10531 | } | |
10532 | else | |
10533 | { | |
10534 | long minext, maxext; | |
10535 | int extval; | |
10536 | ||
10537 | if (op->extu) | |
10538 | { | |
10539 | minext = 0; | |
10540 | maxext = (1 << op->extbits) - 1; | |
10541 | } | |
10542 | else | |
10543 | { | |
10544 | minext = - (1 << (op->extbits - 1)); | |
10545 | maxext = (1 << (op->extbits - 1)) - 1; | |
10546 | } | |
10547 | if (val < minext || val > maxext) | |
10548 | as_bad_where (file, line, | |
10549 | _("operand value out of range for instruction")); | |
10550 | ||
b34976b6 | 10551 | *use_extend = TRUE; |
252b5132 RH |
10552 | if (op->extbits == 16) |
10553 | { | |
10554 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
10555 | val &= 0x1f; | |
10556 | } | |
10557 | else if (op->extbits == 15) | |
10558 | { | |
10559 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
10560 | val &= 0xf; | |
10561 | } | |
10562 | else | |
10563 | { | |
10564 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
10565 | val = 0; | |
10566 | } | |
10567 | ||
10568 | *extend = (unsigned short) extval; | |
10569 | *insn |= val; | |
10570 | } | |
10571 | } | |
10572 | \f | |
d6f16593 | 10573 | struct percent_op_match |
ad8d3bb3 | 10574 | { |
5e0116d5 RS |
10575 | const char *str; |
10576 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
10577 | }; |
10578 | ||
10579 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 10580 | { |
5e0116d5 | 10581 | {"%lo", BFD_RELOC_LO16}, |
ad8d3bb3 | 10582 | #ifdef OBJ_ELF |
5e0116d5 RS |
10583 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
10584 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
10585 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
10586 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
10587 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
10588 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
10589 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
10590 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
10591 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
10592 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
10593 | {"%half", BFD_RELOC_16}, | |
10594 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
10595 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
10596 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
10597 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
10598 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
10599 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
10600 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
10601 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
10602 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
10603 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
ad8d3bb3 | 10604 | #endif |
5e0116d5 | 10605 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
10606 | }; |
10607 | ||
d6f16593 MR |
10608 | static const struct percent_op_match mips16_percent_op[] = |
10609 | { | |
10610 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
10611 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, | |
10612 | {"%hi", BFD_RELOC_MIPS16_HI16_S} | |
10613 | }; | |
10614 | ||
252b5132 | 10615 | |
5e0116d5 RS |
10616 | /* Return true if *STR points to a relocation operator. When returning true, |
10617 | move *STR over the operator and store its relocation code in *RELOC. | |
10618 | Leave both *STR and *RELOC alone when returning false. */ | |
10619 | ||
10620 | static bfd_boolean | |
17a2f251 | 10621 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 10622 | { |
d6f16593 MR |
10623 | const struct percent_op_match *percent_op; |
10624 | size_t limit, i; | |
10625 | ||
10626 | if (mips_opts.mips16) | |
10627 | { | |
10628 | percent_op = mips16_percent_op; | |
10629 | limit = ARRAY_SIZE (mips16_percent_op); | |
10630 | } | |
10631 | else | |
10632 | { | |
10633 | percent_op = mips_percent_op; | |
10634 | limit = ARRAY_SIZE (mips_percent_op); | |
10635 | } | |
76b3015f | 10636 | |
d6f16593 | 10637 | for (i = 0; i < limit; i++) |
5e0116d5 | 10638 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 10639 | { |
3f98094e DJ |
10640 | int len = strlen (percent_op[i].str); |
10641 | ||
10642 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
10643 | continue; | |
10644 | ||
5e0116d5 RS |
10645 | *str += strlen (percent_op[i].str); |
10646 | *reloc = percent_op[i].reloc; | |
394f9b3a | 10647 | |
5e0116d5 RS |
10648 | /* Check whether the output BFD supports this relocation. |
10649 | If not, issue an error and fall back on something safe. */ | |
10650 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 10651 | { |
5e0116d5 RS |
10652 | as_bad ("relocation %s isn't supported by the current ABI", |
10653 | percent_op[i].str); | |
01a3f561 | 10654 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 10655 | } |
5e0116d5 | 10656 | return TRUE; |
394f9b3a | 10657 | } |
5e0116d5 | 10658 | return FALSE; |
394f9b3a | 10659 | } |
ad8d3bb3 | 10660 | |
ad8d3bb3 | 10661 | |
5e0116d5 RS |
10662 | /* Parse string STR as a 16-bit relocatable operand. Store the |
10663 | expression in *EP and the relocations in the array starting | |
10664 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 10665 | |
01a3f561 | 10666 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 10667 | |
5e0116d5 | 10668 | static size_t |
17a2f251 TS |
10669 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
10670 | char *str) | |
ad8d3bb3 | 10671 | { |
5e0116d5 RS |
10672 | bfd_reloc_code_real_type reversed_reloc[3]; |
10673 | size_t reloc_index, i; | |
09b8f35a RS |
10674 | int crux_depth, str_depth; |
10675 | char *crux; | |
5e0116d5 RS |
10676 | |
10677 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
10678 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
10679 | of the main expression and with CRUX_DEPTH containing the number | |
10680 | of open brackets at that point. */ | |
10681 | reloc_index = -1; | |
10682 | str_depth = 0; | |
10683 | do | |
fb1b3232 | 10684 | { |
09b8f35a RS |
10685 | reloc_index++; |
10686 | crux = str; | |
10687 | crux_depth = str_depth; | |
10688 | ||
10689 | /* Skip over whitespace and brackets, keeping count of the number | |
10690 | of brackets. */ | |
10691 | while (*str == ' ' || *str == '\t' || *str == '(') | |
10692 | if (*str++ == '(') | |
10693 | str_depth++; | |
5e0116d5 | 10694 | } |
09b8f35a RS |
10695 | while (*str == '%' |
10696 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
10697 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 10698 | |
09b8f35a | 10699 | my_getExpression (ep, crux); |
5e0116d5 | 10700 | str = expr_end; |
394f9b3a | 10701 | |
5e0116d5 | 10702 | /* Match every open bracket. */ |
09b8f35a | 10703 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 10704 | if (*str++ == ')') |
09b8f35a | 10705 | crux_depth--; |
394f9b3a | 10706 | |
09b8f35a | 10707 | if (crux_depth > 0) |
5e0116d5 | 10708 | as_bad ("unclosed '('"); |
394f9b3a | 10709 | |
5e0116d5 | 10710 | expr_end = str; |
252b5132 | 10711 | |
01a3f561 | 10712 | if (reloc_index != 0) |
64bdfcaf RS |
10713 | { |
10714 | prev_reloc_op_frag = frag_now; | |
10715 | for (i = 0; i < reloc_index; i++) | |
10716 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
10717 | } | |
fb1b3232 | 10718 | |
5e0116d5 | 10719 | return reloc_index; |
252b5132 RH |
10720 | } |
10721 | ||
10722 | static void | |
17a2f251 | 10723 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
10724 | { |
10725 | char *save_in; | |
98aa84af | 10726 | valueT val; |
252b5132 RH |
10727 | |
10728 | save_in = input_line_pointer; | |
10729 | input_line_pointer = str; | |
10730 | expression (ep); | |
10731 | expr_end = input_line_pointer; | |
10732 | input_line_pointer = save_in; | |
10733 | ||
10734 | /* If we are in mips16 mode, and this is an expression based on `.', | |
10735 | then we bump the value of the symbol by 1 since that is how other | |
10736 | text symbols are handled. We don't bother to handle complex | |
10737 | expressions, just `.' plus or minus a constant. */ | |
10738 | if (mips_opts.mips16 | |
10739 | && ep->X_op == O_symbol | |
10740 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
10741 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
49309057 ILT |
10742 | && symbol_get_frag (ep->X_add_symbol) == frag_now |
10743 | && symbol_constant_p (ep->X_add_symbol) | |
98aa84af AM |
10744 | && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ()) |
10745 | S_SET_VALUE (ep->X_add_symbol, val + 1); | |
252b5132 RH |
10746 | } |
10747 | ||
10748 | /* Turn a string in input_line_pointer into a floating point constant | |
bc0d738a NC |
10749 | of type TYPE, and store the appropriate bytes in *LITP. The number |
10750 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
252b5132 RH |
10751 | returned, or NULL on OK. */ |
10752 | ||
10753 | char * | |
17a2f251 | 10754 | md_atof (int type, char *litP, int *sizeP) |
252b5132 RH |
10755 | { |
10756 | int prec; | |
10757 | LITTLENUM_TYPE words[4]; | |
10758 | char *t; | |
10759 | int i; | |
10760 | ||
10761 | switch (type) | |
10762 | { | |
10763 | case 'f': | |
10764 | prec = 2; | |
10765 | break; | |
10766 | ||
10767 | case 'd': | |
10768 | prec = 4; | |
10769 | break; | |
10770 | ||
10771 | default: | |
10772 | *sizeP = 0; | |
10773 | return _("bad call to md_atof"); | |
10774 | } | |
10775 | ||
10776 | t = atof_ieee (input_line_pointer, type, words); | |
10777 | if (t) | |
10778 | input_line_pointer = t; | |
10779 | ||
10780 | *sizeP = prec * 2; | |
10781 | ||
10782 | if (! target_big_endian) | |
10783 | { | |
10784 | for (i = prec - 1; i >= 0; i--) | |
10785 | { | |
17a2f251 | 10786 | md_number_to_chars (litP, words[i], 2); |
252b5132 RH |
10787 | litP += 2; |
10788 | } | |
10789 | } | |
10790 | else | |
10791 | { | |
10792 | for (i = 0; i < prec; i++) | |
10793 | { | |
17a2f251 | 10794 | md_number_to_chars (litP, words[i], 2); |
252b5132 RH |
10795 | litP += 2; |
10796 | } | |
10797 | } | |
bdaaa2e1 | 10798 | |
252b5132 RH |
10799 | return NULL; |
10800 | } | |
10801 | ||
10802 | void | |
17a2f251 | 10803 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
10804 | { |
10805 | if (target_big_endian) | |
10806 | number_to_chars_bigendian (buf, val, n); | |
10807 | else | |
10808 | number_to_chars_littleendian (buf, val, n); | |
10809 | } | |
10810 | \f | |
ae948b86 | 10811 | #ifdef OBJ_ELF |
e013f690 TS |
10812 | static int support_64bit_objects(void) |
10813 | { | |
10814 | const char **list, **l; | |
aa3d8fdf | 10815 | int yes; |
e013f690 TS |
10816 | |
10817 | list = bfd_target_list (); | |
10818 | for (l = list; *l != NULL; l++) | |
10819 | #ifdef TE_TMIPS | |
10820 | /* This is traditional mips */ | |
10821 | if (strcmp (*l, "elf64-tradbigmips") == 0 | |
10822 | || strcmp (*l, "elf64-tradlittlemips") == 0) | |
10823 | #else | |
10824 | if (strcmp (*l, "elf64-bigmips") == 0 | |
10825 | || strcmp (*l, "elf64-littlemips") == 0) | |
10826 | #endif | |
10827 | break; | |
aa3d8fdf | 10828 | yes = (*l != NULL); |
e013f690 | 10829 | free (list); |
aa3d8fdf | 10830 | return yes; |
e013f690 | 10831 | } |
ae948b86 | 10832 | #endif /* OBJ_ELF */ |
e013f690 | 10833 | |
78849248 | 10834 | const char *md_shortopts = "O::g::G:"; |
252b5132 | 10835 | |
e972090a NC |
10836 | struct option md_longopts[] = |
10837 | { | |
f9b4148d CD |
10838 | /* Options which specify architecture. */ |
10839 | #define OPTION_ARCH_BASE (OPTION_MD_BASE) | |
10840 | #define OPTION_MARCH (OPTION_ARCH_BASE + 0) | |
10841 | {"march", required_argument, NULL, OPTION_MARCH}, | |
10842 | #define OPTION_MTUNE (OPTION_ARCH_BASE + 1) | |
10843 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
10844 | #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2) | |
252b5132 RH |
10845 | {"mips0", no_argument, NULL, OPTION_MIPS1}, |
10846 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
f9b4148d | 10847 | #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3) |
252b5132 | 10848 | {"mips2", no_argument, NULL, OPTION_MIPS2}, |
f9b4148d | 10849 | #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4) |
252b5132 | 10850 | {"mips3", no_argument, NULL, OPTION_MIPS3}, |
f9b4148d | 10851 | #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5) |
252b5132 | 10852 | {"mips4", no_argument, NULL, OPTION_MIPS4}, |
f9b4148d | 10853 | #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6) |
ae948b86 | 10854 | {"mips5", no_argument, NULL, OPTION_MIPS5}, |
f9b4148d | 10855 | #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7) |
ae948b86 | 10856 | {"mips32", no_argument, NULL, OPTION_MIPS32}, |
f9b4148d | 10857 | #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8) |
ae948b86 | 10858 | {"mips64", no_argument, NULL, OPTION_MIPS64}, |
f9b4148d CD |
10859 | #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9) |
10860 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, | |
5f74bc13 CD |
10861 | #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10) |
10862 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, | |
f9b4148d CD |
10863 | |
10864 | /* Options which specify Application Specific Extensions (ASEs). */ | |
5f74bc13 | 10865 | #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11) |
f9b4148d CD |
10866 | #define OPTION_MIPS16 (OPTION_ASE_BASE + 0) |
10867 | {"mips16", no_argument, NULL, OPTION_MIPS16}, | |
10868 | #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1) | |
10869 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, | |
10870 | #define OPTION_MIPS3D (OPTION_ASE_BASE + 2) | |
10871 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, | |
10872 | #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3) | |
10873 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, | |
10874 | #define OPTION_MDMX (OPTION_ASE_BASE + 4) | |
10875 | {"mdmx", no_argument, NULL, OPTION_MDMX}, | |
10876 | #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5) | |
10877 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, | |
74cd071d CF |
10878 | #define OPTION_DSP (OPTION_ASE_BASE + 6) |
10879 | {"mdsp", no_argument, NULL, OPTION_DSP}, | |
10880 | #define OPTION_NO_DSP (OPTION_ASE_BASE + 7) | |
10881 | {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, | |
ef2e4d86 CF |
10882 | #define OPTION_MT (OPTION_ASE_BASE + 8) |
10883 | {"mmt", no_argument, NULL, OPTION_MT}, | |
10884 | #define OPTION_NO_MT (OPTION_ASE_BASE + 9) | |
10885 | {"mno-mt", no_argument, NULL, OPTION_NO_MT}, | |
e16bfa71 TS |
10886 | #define OPTION_SMARTMIPS (OPTION_ASE_BASE + 10) |
10887 | {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS}, | |
10888 | #define OPTION_NO_SMARTMIPS (OPTION_ASE_BASE + 11) | |
10889 | {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS}, | |
8b082fb1 TS |
10890 | #define OPTION_DSPR2 (OPTION_ASE_BASE + 12) |
10891 | {"mdspr2", no_argument, NULL, OPTION_DSPR2}, | |
10892 | #define OPTION_NO_DSPR2 (OPTION_ASE_BASE + 13) | |
10893 | {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2}, | |
f9b4148d CD |
10894 | |
10895 | /* Old-style architecture options. Don't add more of these. */ | |
8b082fb1 | 10896 | #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 14) |
f9b4148d CD |
10897 | #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0) |
10898 | {"m4650", no_argument, NULL, OPTION_M4650}, | |
10899 | #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1) | |
10900 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, | |
10901 | #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2) | |
10902 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
10903 | #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3) | |
10904 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
10905 | #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4) | |
10906 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
10907 | #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5) | |
10908 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
10909 | #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6) | |
10910 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
10911 | #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7) | |
10912 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
10913 | ||
10914 | /* Options which enable bug fixes. */ | |
10915 | #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8) | |
10916 | #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0) | |
10917 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, | |
10918 | #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1) | |
10919 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
10920 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
d766e8ec RS |
10921 | #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2) |
10922 | #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3) | |
10923 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, | |
10924 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
7d8e00cf RS |
10925 | #define OPTION_FIX_VR4130 (OPTION_FIX_BASE + 4) |
10926 | #define OPTION_NO_FIX_VR4130 (OPTION_FIX_BASE + 5) | |
10927 | {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, | |
10928 | {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, | |
f9b4148d CD |
10929 | |
10930 | /* Miscellaneous options. */ | |
7d8e00cf | 10931 | #define OPTION_MISC_BASE (OPTION_FIX_BASE + 6) |
1ffcab4b | 10932 | #define OPTION_TRAP (OPTION_MISC_BASE + 0) |
252b5132 RH |
10933 | {"trap", no_argument, NULL, OPTION_TRAP}, |
10934 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
1ffcab4b | 10935 | #define OPTION_BREAK (OPTION_MISC_BASE + 1) |
252b5132 RH |
10936 | {"break", no_argument, NULL, OPTION_BREAK}, |
10937 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
1ffcab4b | 10938 | #define OPTION_EB (OPTION_MISC_BASE + 2) |
252b5132 | 10939 | {"EB", no_argument, NULL, OPTION_EB}, |
1ffcab4b | 10940 | #define OPTION_EL (OPTION_MISC_BASE + 3) |
252b5132 | 10941 | {"EL", no_argument, NULL, OPTION_EL}, |
1ffcab4b | 10942 | #define OPTION_FP32 (OPTION_MISC_BASE + 4) |
ae948b86 | 10943 | {"mfp32", no_argument, NULL, OPTION_FP32}, |
1ffcab4b | 10944 | #define OPTION_GP32 (OPTION_MISC_BASE + 5) |
c97ef257 | 10945 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
1ffcab4b | 10946 | #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6) |
119d663a | 10947 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
1ffcab4b | 10948 | #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7) |
119d663a | 10949 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
1ffcab4b | 10950 | #define OPTION_FP64 (OPTION_MISC_BASE + 8) |
316f5878 | 10951 | {"mfp64", no_argument, NULL, OPTION_FP64}, |
1ffcab4b | 10952 | #define OPTION_GP64 (OPTION_MISC_BASE + 9) |
ae948b86 | 10953 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
1ffcab4b CD |
10954 | #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10) |
10955 | #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11) | |
4a6a3df4 AO |
10956 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, |
10957 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
aa6975fb ILT |
10958 | #define OPTION_MSHARED (OPTION_MISC_BASE + 12) |
10959 | #define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13) | |
10960 | {"mshared", no_argument, NULL, OPTION_MSHARED}, | |
10961 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
aed1a261 RS |
10962 | #define OPTION_MSYM32 (OPTION_MISC_BASE + 14) |
10963 | #define OPTION_MNO_SYM32 (OPTION_MISC_BASE + 15) | |
10964 | {"msym32", no_argument, NULL, OPTION_MSYM32}, | |
10965 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, | |
f9b4148d CD |
10966 | |
10967 | /* ELF-specific options. */ | |
156c2f8b | 10968 | #ifdef OBJ_ELF |
aed1a261 | 10969 | #define OPTION_ELF_BASE (OPTION_MISC_BASE + 16) |
156c2f8b | 10970 | #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0) |
156c2f8b NC |
10971 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
10972 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
ae948b86 | 10973 | #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1) |
156c2f8b | 10974 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
ae948b86 | 10975 | #define OPTION_XGOT (OPTION_ELF_BASE + 2) |
156c2f8b | 10976 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
ae948b86 TS |
10977 | #define OPTION_MABI (OPTION_ELF_BASE + 3) |
10978 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
10979 | #define OPTION_32 (OPTION_ELF_BASE + 4) | |
156c2f8b | 10980 | {"32", no_argument, NULL, OPTION_32}, |
ae948b86 | 10981 | #define OPTION_N32 (OPTION_ELF_BASE + 5) |
e013f690 | 10982 | {"n32", no_argument, NULL, OPTION_N32}, |
ae948b86 | 10983 | #define OPTION_64 (OPTION_ELF_BASE + 6) |
156c2f8b | 10984 | {"64", no_argument, NULL, OPTION_64}, |
ecb4347a DJ |
10985 | #define OPTION_MDEBUG (OPTION_ELF_BASE + 7) |
10986 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, | |
10987 | #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8) | |
10988 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, | |
dcd410fe RO |
10989 | #define OPTION_PDR (OPTION_ELF_BASE + 9) |
10990 | {"mpdr", no_argument, NULL, OPTION_PDR}, | |
10991 | #define OPTION_NO_PDR (OPTION_ELF_BASE + 10) | |
10992 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, | |
0a44bf69 RS |
10993 | #define OPTION_MVXWORKS_PIC (OPTION_ELF_BASE + 11) |
10994 | {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, | |
ae948b86 | 10995 | #endif /* OBJ_ELF */ |
f9b4148d | 10996 | |
252b5132 RH |
10997 | {NULL, no_argument, NULL, 0} |
10998 | }; | |
156c2f8b | 10999 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 11000 | |
316f5878 RS |
11001 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
11002 | NEW_VALUE. Warn if another value was already specified. Note: | |
11003 | we have to defer parsing the -march and -mtune arguments in order | |
11004 | to handle 'from-abi' correctly, since the ABI might be specified | |
11005 | in a later argument. */ | |
11006 | ||
11007 | static void | |
17a2f251 | 11008 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
11009 | { |
11010 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
11011 | as_warn (_("A different %s was already specified, is now %s"), | |
11012 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
11013 | new_value); | |
11014 | ||
11015 | *string_ptr = new_value; | |
11016 | } | |
11017 | ||
252b5132 | 11018 | int |
17a2f251 | 11019 | md_parse_option (int c, char *arg) |
252b5132 RH |
11020 | { |
11021 | switch (c) | |
11022 | { | |
119d663a NC |
11023 | case OPTION_CONSTRUCT_FLOATS: |
11024 | mips_disable_float_construction = 0; | |
11025 | break; | |
bdaaa2e1 | 11026 | |
119d663a NC |
11027 | case OPTION_NO_CONSTRUCT_FLOATS: |
11028 | mips_disable_float_construction = 1; | |
11029 | break; | |
bdaaa2e1 | 11030 | |
252b5132 RH |
11031 | case OPTION_TRAP: |
11032 | mips_trap = 1; | |
11033 | break; | |
11034 | ||
11035 | case OPTION_BREAK: | |
11036 | mips_trap = 0; | |
11037 | break; | |
11038 | ||
11039 | case OPTION_EB: | |
11040 | target_big_endian = 1; | |
11041 | break; | |
11042 | ||
11043 | case OPTION_EL: | |
11044 | target_big_endian = 0; | |
11045 | break; | |
11046 | ||
11047 | case 'O': | |
24471d42 | 11048 | if (arg && arg[0] == '0') |
252b5132 RH |
11049 | mips_optimize = 1; |
11050 | else | |
11051 | mips_optimize = 2; | |
11052 | break; | |
11053 | ||
11054 | case 'g': | |
11055 | if (arg == NULL) | |
11056 | mips_debug = 2; | |
11057 | else | |
11058 | mips_debug = atoi (arg); | |
252b5132 RH |
11059 | break; |
11060 | ||
11061 | case OPTION_MIPS1: | |
316f5878 | 11062 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
11063 | break; |
11064 | ||
11065 | case OPTION_MIPS2: | |
316f5878 | 11066 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
11067 | break; |
11068 | ||
11069 | case OPTION_MIPS3: | |
316f5878 | 11070 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
11071 | break; |
11072 | ||
11073 | case OPTION_MIPS4: | |
316f5878 | 11074 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
11075 | break; |
11076 | ||
84ea6cf2 | 11077 | case OPTION_MIPS5: |
316f5878 | 11078 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
11079 | break; |
11080 | ||
e7af610e | 11081 | case OPTION_MIPS32: |
316f5878 | 11082 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
11083 | break; |
11084 | ||
af7ee8bf CD |
11085 | case OPTION_MIPS32R2: |
11086 | file_mips_isa = ISA_MIPS32R2; | |
11087 | break; | |
11088 | ||
5f74bc13 CD |
11089 | case OPTION_MIPS64R2: |
11090 | file_mips_isa = ISA_MIPS64R2; | |
11091 | break; | |
11092 | ||
84ea6cf2 | 11093 | case OPTION_MIPS64: |
316f5878 | 11094 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
11095 | break; |
11096 | ||
ec68c924 | 11097 | case OPTION_MTUNE: |
316f5878 RS |
11098 | mips_set_option_string (&mips_tune_string, arg); |
11099 | break; | |
ec68c924 | 11100 | |
316f5878 RS |
11101 | case OPTION_MARCH: |
11102 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
11103 | break; |
11104 | ||
11105 | case OPTION_M4650: | |
316f5878 RS |
11106 | mips_set_option_string (&mips_arch_string, "4650"); |
11107 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
11108 | break; |
11109 | ||
11110 | case OPTION_NO_M4650: | |
11111 | break; | |
11112 | ||
11113 | case OPTION_M4010: | |
316f5878 RS |
11114 | mips_set_option_string (&mips_arch_string, "4010"); |
11115 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
11116 | break; |
11117 | ||
11118 | case OPTION_NO_M4010: | |
11119 | break; | |
11120 | ||
11121 | case OPTION_M4100: | |
316f5878 RS |
11122 | mips_set_option_string (&mips_arch_string, "4100"); |
11123 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
11124 | break; |
11125 | ||
11126 | case OPTION_NO_M4100: | |
11127 | break; | |
11128 | ||
252b5132 | 11129 | case OPTION_M3900: |
316f5878 RS |
11130 | mips_set_option_string (&mips_arch_string, "3900"); |
11131 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 11132 | break; |
bdaaa2e1 | 11133 | |
252b5132 RH |
11134 | case OPTION_NO_M3900: |
11135 | break; | |
11136 | ||
deec1734 CD |
11137 | case OPTION_MDMX: |
11138 | mips_opts.ase_mdmx = 1; | |
11139 | break; | |
11140 | ||
11141 | case OPTION_NO_MDMX: | |
11142 | mips_opts.ase_mdmx = 0; | |
11143 | break; | |
11144 | ||
74cd071d CF |
11145 | case OPTION_DSP: |
11146 | mips_opts.ase_dsp = 1; | |
8b082fb1 | 11147 | mips_opts.ase_dspr2 = 0; |
74cd071d CF |
11148 | break; |
11149 | ||
11150 | case OPTION_NO_DSP: | |
8b082fb1 TS |
11151 | mips_opts.ase_dsp = 0; |
11152 | mips_opts.ase_dspr2 = 0; | |
11153 | break; | |
11154 | ||
11155 | case OPTION_DSPR2: | |
11156 | mips_opts.ase_dspr2 = 1; | |
11157 | mips_opts.ase_dsp = 1; | |
11158 | break; | |
11159 | ||
11160 | case OPTION_NO_DSPR2: | |
11161 | mips_opts.ase_dspr2 = 0; | |
74cd071d CF |
11162 | mips_opts.ase_dsp = 0; |
11163 | break; | |
11164 | ||
ef2e4d86 CF |
11165 | case OPTION_MT: |
11166 | mips_opts.ase_mt = 1; | |
11167 | break; | |
11168 | ||
11169 | case OPTION_NO_MT: | |
11170 | mips_opts.ase_mt = 0; | |
11171 | break; | |
11172 | ||
252b5132 RH |
11173 | case OPTION_MIPS16: |
11174 | mips_opts.mips16 = 1; | |
7d10b47d | 11175 | mips_no_prev_insn (); |
252b5132 RH |
11176 | break; |
11177 | ||
11178 | case OPTION_NO_MIPS16: | |
11179 | mips_opts.mips16 = 0; | |
7d10b47d | 11180 | mips_no_prev_insn (); |
252b5132 RH |
11181 | break; |
11182 | ||
1f25f5d3 CD |
11183 | case OPTION_MIPS3D: |
11184 | mips_opts.ase_mips3d = 1; | |
11185 | break; | |
11186 | ||
11187 | case OPTION_NO_MIPS3D: | |
11188 | mips_opts.ase_mips3d = 0; | |
11189 | break; | |
11190 | ||
e16bfa71 TS |
11191 | case OPTION_SMARTMIPS: |
11192 | mips_opts.ase_smartmips = 1; | |
11193 | break; | |
11194 | ||
11195 | case OPTION_NO_SMARTMIPS: | |
11196 | mips_opts.ase_smartmips = 0; | |
11197 | break; | |
11198 | ||
d766e8ec RS |
11199 | case OPTION_FIX_VR4120: |
11200 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
11201 | break; |
11202 | ||
d766e8ec RS |
11203 | case OPTION_NO_FIX_VR4120: |
11204 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
11205 | break; |
11206 | ||
7d8e00cf RS |
11207 | case OPTION_FIX_VR4130: |
11208 | mips_fix_vr4130 = 1; | |
11209 | break; | |
11210 | ||
11211 | case OPTION_NO_FIX_VR4130: | |
11212 | mips_fix_vr4130 = 0; | |
11213 | break; | |
11214 | ||
4a6a3df4 AO |
11215 | case OPTION_RELAX_BRANCH: |
11216 | mips_relax_branch = 1; | |
11217 | break; | |
11218 | ||
11219 | case OPTION_NO_RELAX_BRANCH: | |
11220 | mips_relax_branch = 0; | |
11221 | break; | |
11222 | ||
aa6975fb ILT |
11223 | case OPTION_MSHARED: |
11224 | mips_in_shared = TRUE; | |
11225 | break; | |
11226 | ||
11227 | case OPTION_MNO_SHARED: | |
11228 | mips_in_shared = FALSE; | |
11229 | break; | |
11230 | ||
aed1a261 RS |
11231 | case OPTION_MSYM32: |
11232 | mips_opts.sym32 = TRUE; | |
11233 | break; | |
11234 | ||
11235 | case OPTION_MNO_SYM32: | |
11236 | mips_opts.sym32 = FALSE; | |
11237 | break; | |
11238 | ||
0f074f60 | 11239 | #ifdef OBJ_ELF |
252b5132 RH |
11240 | /* When generating ELF code, we permit -KPIC and -call_shared to |
11241 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
11242 | intended to be compatible with Irix 5. */ | |
11243 | case OPTION_CALL_SHARED: | |
f43abd2b | 11244 | if (!IS_ELF) |
252b5132 RH |
11245 | { |
11246 | as_bad (_("-call_shared is supported only for ELF format")); | |
11247 | return 0; | |
11248 | } | |
11249 | mips_pic = SVR4_PIC; | |
143d77c5 | 11250 | mips_abicalls = TRUE; |
252b5132 RH |
11251 | break; |
11252 | ||
11253 | case OPTION_NON_SHARED: | |
f43abd2b | 11254 | if (!IS_ELF) |
252b5132 RH |
11255 | { |
11256 | as_bad (_("-non_shared is supported only for ELF format")); | |
11257 | return 0; | |
11258 | } | |
11259 | mips_pic = NO_PIC; | |
143d77c5 | 11260 | mips_abicalls = FALSE; |
252b5132 RH |
11261 | break; |
11262 | ||
44075ae2 TS |
11263 | /* The -xgot option tells the assembler to use 32 bit offsets |
11264 | when accessing the got in SVR4_PIC mode. It is for Irix | |
252b5132 RH |
11265 | compatibility. */ |
11266 | case OPTION_XGOT: | |
11267 | mips_big_got = 1; | |
11268 | break; | |
0f074f60 | 11269 | #endif /* OBJ_ELF */ |
252b5132 RH |
11270 | |
11271 | case 'G': | |
6caf9ef4 TS |
11272 | g_switch_value = atoi (arg); |
11273 | g_switch_seen = 1; | |
252b5132 RH |
11274 | break; |
11275 | ||
0f074f60 | 11276 | #ifdef OBJ_ELF |
34ba82a8 TS |
11277 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
11278 | and -mabi=64. */ | |
252b5132 | 11279 | case OPTION_32: |
f43abd2b | 11280 | if (!IS_ELF) |
34ba82a8 TS |
11281 | { |
11282 | as_bad (_("-32 is supported for ELF format only")); | |
11283 | return 0; | |
11284 | } | |
316f5878 | 11285 | mips_abi = O32_ABI; |
252b5132 RH |
11286 | break; |
11287 | ||
e013f690 | 11288 | case OPTION_N32: |
f43abd2b | 11289 | if (!IS_ELF) |
34ba82a8 TS |
11290 | { |
11291 | as_bad (_("-n32 is supported for ELF format only")); | |
11292 | return 0; | |
11293 | } | |
316f5878 | 11294 | mips_abi = N32_ABI; |
e013f690 | 11295 | break; |
252b5132 | 11296 | |
e013f690 | 11297 | case OPTION_64: |
f43abd2b | 11298 | if (!IS_ELF) |
34ba82a8 TS |
11299 | { |
11300 | as_bad (_("-64 is supported for ELF format only")); | |
11301 | return 0; | |
11302 | } | |
316f5878 | 11303 | mips_abi = N64_ABI; |
f43abd2b | 11304 | if (!support_64bit_objects()) |
e013f690 | 11305 | as_fatal (_("No compiled in support for 64 bit object file format")); |
252b5132 | 11306 | break; |
ae948b86 | 11307 | #endif /* OBJ_ELF */ |
252b5132 | 11308 | |
c97ef257 | 11309 | case OPTION_GP32: |
a325df1d | 11310 | file_mips_gp32 = 1; |
c97ef257 AH |
11311 | break; |
11312 | ||
11313 | case OPTION_GP64: | |
a325df1d | 11314 | file_mips_gp32 = 0; |
c97ef257 | 11315 | break; |
252b5132 | 11316 | |
ca4e0257 | 11317 | case OPTION_FP32: |
a325df1d | 11318 | file_mips_fp32 = 1; |
316f5878 RS |
11319 | break; |
11320 | ||
11321 | case OPTION_FP64: | |
11322 | file_mips_fp32 = 0; | |
ca4e0257 RS |
11323 | break; |
11324 | ||
ae948b86 | 11325 | #ifdef OBJ_ELF |
252b5132 | 11326 | case OPTION_MABI: |
f43abd2b | 11327 | if (!IS_ELF) |
34ba82a8 TS |
11328 | { |
11329 | as_bad (_("-mabi is supported for ELF format only")); | |
11330 | return 0; | |
11331 | } | |
e013f690 | 11332 | if (strcmp (arg, "32") == 0) |
316f5878 | 11333 | mips_abi = O32_ABI; |
e013f690 | 11334 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 11335 | mips_abi = O64_ABI; |
e013f690 | 11336 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 11337 | mips_abi = N32_ABI; |
e013f690 TS |
11338 | else if (strcmp (arg, "64") == 0) |
11339 | { | |
316f5878 | 11340 | mips_abi = N64_ABI; |
e013f690 TS |
11341 | if (! support_64bit_objects()) |
11342 | as_fatal (_("No compiled in support for 64 bit object file " | |
11343 | "format")); | |
11344 | } | |
11345 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 11346 | mips_abi = EABI_ABI; |
e013f690 | 11347 | else |
da0e507f TS |
11348 | { |
11349 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
11350 | return 0; | |
11351 | } | |
252b5132 | 11352 | break; |
e013f690 | 11353 | #endif /* OBJ_ELF */ |
252b5132 | 11354 | |
6b76fefe | 11355 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 11356 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
11357 | break; |
11358 | ||
9ee72ff1 | 11359 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 11360 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
11361 | break; |
11362 | ||
ecb4347a DJ |
11363 | #ifdef OBJ_ELF |
11364 | case OPTION_MDEBUG: | |
b34976b6 | 11365 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
11366 | break; |
11367 | ||
11368 | case OPTION_NO_MDEBUG: | |
b34976b6 | 11369 | mips_flag_mdebug = FALSE; |
ecb4347a | 11370 | break; |
dcd410fe RO |
11371 | |
11372 | case OPTION_PDR: | |
11373 | mips_flag_pdr = TRUE; | |
11374 | break; | |
11375 | ||
11376 | case OPTION_NO_PDR: | |
11377 | mips_flag_pdr = FALSE; | |
11378 | break; | |
0a44bf69 RS |
11379 | |
11380 | case OPTION_MVXWORKS_PIC: | |
11381 | mips_pic = VXWORKS_PIC; | |
11382 | break; | |
ecb4347a DJ |
11383 | #endif /* OBJ_ELF */ |
11384 | ||
252b5132 RH |
11385 | default: |
11386 | return 0; | |
11387 | } | |
11388 | ||
11389 | return 1; | |
11390 | } | |
316f5878 RS |
11391 | \f |
11392 | /* Set up globals to generate code for the ISA or processor | |
11393 | described by INFO. */ | |
252b5132 | 11394 | |
252b5132 | 11395 | static void |
17a2f251 | 11396 | mips_set_architecture (const struct mips_cpu_info *info) |
252b5132 | 11397 | { |
316f5878 | 11398 | if (info != 0) |
252b5132 | 11399 | { |
fef14a42 TS |
11400 | file_mips_arch = info->cpu; |
11401 | mips_opts.arch = info->cpu; | |
316f5878 | 11402 | mips_opts.isa = info->isa; |
252b5132 | 11403 | } |
252b5132 RH |
11404 | } |
11405 | ||
252b5132 | 11406 | |
316f5878 | 11407 | /* Likewise for tuning. */ |
252b5132 | 11408 | |
316f5878 | 11409 | static void |
17a2f251 | 11410 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
11411 | { |
11412 | if (info != 0) | |
fef14a42 | 11413 | mips_tune = info->cpu; |
316f5878 | 11414 | } |
80cc45a5 | 11415 | |
34ba82a8 | 11416 | |
252b5132 | 11417 | void |
17a2f251 | 11418 | mips_after_parse_args (void) |
e9670677 | 11419 | { |
fef14a42 TS |
11420 | const struct mips_cpu_info *arch_info = 0; |
11421 | const struct mips_cpu_info *tune_info = 0; | |
11422 | ||
e9670677 | 11423 | /* GP relative stuff not working for PE */ |
6caf9ef4 | 11424 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
e9670677 | 11425 | { |
6caf9ef4 | 11426 | if (g_switch_seen && g_switch_value != 0) |
e9670677 MR |
11427 | as_bad (_("-G not supported in this configuration.")); |
11428 | g_switch_value = 0; | |
11429 | } | |
11430 | ||
cac012d6 AO |
11431 | if (mips_abi == NO_ABI) |
11432 | mips_abi = MIPS_DEFAULT_ABI; | |
11433 | ||
22923709 RS |
11434 | /* The following code determines the architecture and register size. |
11435 | Similar code was added to GCC 3.3 (see override_options() in | |
11436 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
11437 | as much as possible. */ | |
e9670677 | 11438 | |
316f5878 | 11439 | if (mips_arch_string != 0) |
fef14a42 | 11440 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 11441 | |
316f5878 | 11442 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 11443 | { |
316f5878 | 11444 | /* Handle -mipsN. At this point, file_mips_isa contains the |
fef14a42 | 11445 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 11446 | the -march selection (if any). */ |
fef14a42 | 11447 | if (arch_info != 0) |
e9670677 | 11448 | { |
316f5878 RS |
11449 | /* -march takes precedence over -mipsN, since it is more descriptive. |
11450 | There's no harm in specifying both as long as the ISA levels | |
11451 | are the same. */ | |
fef14a42 | 11452 | if (file_mips_isa != arch_info->isa) |
316f5878 RS |
11453 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), |
11454 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
fef14a42 | 11455 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 11456 | } |
316f5878 | 11457 | else |
fef14a42 | 11458 | arch_info = mips_cpu_info_from_isa (file_mips_isa); |
e9670677 MR |
11459 | } |
11460 | ||
fef14a42 TS |
11461 | if (arch_info == 0) |
11462 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
e9670677 | 11463 | |
fef14a42 | 11464 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
316f5878 | 11465 | as_bad ("-march=%s is not compatible with the selected ABI", |
fef14a42 TS |
11466 | arch_info->name); |
11467 | ||
11468 | mips_set_architecture (arch_info); | |
11469 | ||
11470 | /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ | |
11471 | if (mips_tune_string != 0) | |
11472 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 11473 | |
fef14a42 TS |
11474 | if (tune_info == 0) |
11475 | mips_set_tune (arch_info); | |
11476 | else | |
11477 | mips_set_tune (tune_info); | |
e9670677 | 11478 | |
316f5878 | 11479 | if (file_mips_gp32 >= 0) |
e9670677 | 11480 | { |
316f5878 RS |
11481 | /* The user specified the size of the integer registers. Make sure |
11482 | it agrees with the ABI and ISA. */ | |
11483 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
11484 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
11485 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
11486 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
11487 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
11488 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
11489 | } |
11490 | else | |
11491 | { | |
316f5878 RS |
11492 | /* Infer the integer register size from the ABI and processor. |
11493 | Restrict ourselves to 32-bit registers if that's all the | |
11494 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
11495 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
11496 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
11497 | } |
11498 | ||
ad3fea08 TS |
11499 | switch (file_mips_fp32) |
11500 | { | |
11501 | default: | |
11502 | case -1: | |
11503 | /* No user specified float register size. | |
11504 | ??? GAS treats single-float processors as though they had 64-bit | |
11505 | float registers (although it complains when double-precision | |
11506 | instructions are used). As things stand, saying they have 32-bit | |
11507 | registers would lead to spurious "register must be even" messages. | |
11508 | So here we assume float registers are never smaller than the | |
11509 | integer ones. */ | |
11510 | if (file_mips_gp32 == 0) | |
11511 | /* 64-bit integer registers implies 64-bit float registers. */ | |
11512 | file_mips_fp32 = 0; | |
11513 | else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0) | |
11514 | && ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
11515 | /* -mips3d and -mdmx imply 64-bit float registers, if possible. */ | |
11516 | file_mips_fp32 = 0; | |
11517 | else | |
11518 | /* 32-bit float registers. */ | |
11519 | file_mips_fp32 = 1; | |
11520 | break; | |
11521 | ||
11522 | /* The user specified the size of the float registers. Check if it | |
11523 | agrees with the ABI and ISA. */ | |
11524 | case 0: | |
11525 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
11526 | as_bad (_("-mfp64 used with a 32-bit fpu")); | |
11527 | else if (ABI_NEEDS_32BIT_REGS (mips_abi) | |
11528 | && !ISA_HAS_MXHC1 (mips_opts.isa)) | |
11529 | as_warn (_("-mfp64 used with a 32-bit ABI")); | |
11530 | break; | |
11531 | case 1: | |
11532 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
11533 | as_warn (_("-mfp32 used with a 64-bit ABI")); | |
11534 | break; | |
11535 | } | |
e9670677 | 11536 | |
316f5878 | 11537 | /* End of GCC-shared inference code. */ |
e9670677 | 11538 | |
17a2f251 TS |
11539 | /* This flag is set when we have a 64-bit capable CPU but use only |
11540 | 32-bit wide registers. Note that EABI does not use it. */ | |
11541 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) | |
11542 | && ((mips_abi == NO_ABI && file_mips_gp32 == 1) | |
11543 | || mips_abi == O32_ABI)) | |
316f5878 | 11544 | mips_32bitmode = 1; |
e9670677 MR |
11545 | |
11546 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
11547 | as_bad (_("trap exception not supported at ISA 1")); | |
11548 | ||
e9670677 MR |
11549 | /* If the selected architecture includes support for ASEs, enable |
11550 | generation of code for them. */ | |
a4672219 | 11551 | if (mips_opts.mips16 == -1) |
fef14a42 | 11552 | mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 11553 | if (mips_opts.ase_mips3d == -1) |
65263ce3 | 11554 | mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D) |
ad3fea08 TS |
11555 | && file_mips_fp32 == 0) ? 1 : 0; |
11556 | if (mips_opts.ase_mips3d && file_mips_fp32 == 1) | |
11557 | as_bad (_("-mfp32 used with -mips3d")); | |
11558 | ||
ffdefa66 | 11559 | if (mips_opts.ase_mdmx == -1) |
65263ce3 | 11560 | mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX) |
ad3fea08 TS |
11561 | && file_mips_fp32 == 0) ? 1 : 0; |
11562 | if (mips_opts.ase_mdmx && file_mips_fp32 == 1) | |
11563 | as_bad (_("-mfp32 used with -mdmx")); | |
11564 | ||
11565 | if (mips_opts.ase_smartmips == -1) | |
11566 | mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0; | |
11567 | if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS) | |
11568 | as_warn ("%s ISA does not support SmartMIPS", | |
11569 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
11570 | ||
74cd071d | 11571 | if (mips_opts.ase_dsp == -1) |
ad3fea08 TS |
11572 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; |
11573 | if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE) | |
11574 | as_warn ("%s ISA does not support DSP ASE", | |
11575 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
11576 | ||
8b082fb1 TS |
11577 | if (mips_opts.ase_dspr2 == -1) |
11578 | { | |
11579 | mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0; | |
11580 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; | |
11581 | } | |
11582 | if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE) | |
11583 | as_warn ("%s ISA does not support DSP R2 ASE", | |
11584 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
11585 | ||
ef2e4d86 | 11586 | if (mips_opts.ase_mt == -1) |
ad3fea08 TS |
11587 | mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0; |
11588 | if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE) | |
8b082fb1 | 11589 | as_warn ("%s ISA does not support MT ASE", |
ad3fea08 | 11590 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
e9670677 | 11591 | |
e9670677 | 11592 | file_mips_isa = mips_opts.isa; |
a4672219 | 11593 | file_ase_mips16 = mips_opts.mips16; |
e9670677 MR |
11594 | file_ase_mips3d = mips_opts.ase_mips3d; |
11595 | file_ase_mdmx = mips_opts.ase_mdmx; | |
e16bfa71 | 11596 | file_ase_smartmips = mips_opts.ase_smartmips; |
74cd071d | 11597 | file_ase_dsp = mips_opts.ase_dsp; |
8b082fb1 | 11598 | file_ase_dspr2 = mips_opts.ase_dspr2; |
ef2e4d86 | 11599 | file_ase_mt = mips_opts.ase_mt; |
e9670677 MR |
11600 | mips_opts.gp32 = file_mips_gp32; |
11601 | mips_opts.fp32 = file_mips_fp32; | |
11602 | ||
ecb4347a DJ |
11603 | if (mips_flag_mdebug < 0) |
11604 | { | |
11605 | #ifdef OBJ_MAYBE_ECOFF | |
11606 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) | |
11607 | mips_flag_mdebug = 1; | |
11608 | else | |
11609 | #endif /* OBJ_MAYBE_ECOFF */ | |
11610 | mips_flag_mdebug = 0; | |
11611 | } | |
e9670677 MR |
11612 | } |
11613 | \f | |
11614 | void | |
17a2f251 | 11615 | mips_init_after_args (void) |
252b5132 RH |
11616 | { |
11617 | /* initialize opcodes */ | |
11618 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 11619 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
11620 | } |
11621 | ||
11622 | long | |
17a2f251 | 11623 | md_pcrel_from (fixS *fixP) |
252b5132 | 11624 | { |
a7ebbfdf TS |
11625 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
11626 | switch (fixP->fx_r_type) | |
11627 | { | |
11628 | case BFD_RELOC_16_PCREL_S2: | |
11629 | case BFD_RELOC_MIPS_JMP: | |
11630 | /* Return the address of the delay slot. */ | |
11631 | return addr + 4; | |
11632 | default: | |
58ea3d6a | 11633 | /* We have no relocation type for PC relative MIPS16 instructions. */ |
64817874 TS |
11634 | if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg) |
11635 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11636 | _("PC relative MIPS16 instruction references a different section")); | |
a7ebbfdf TS |
11637 | return addr; |
11638 | } | |
252b5132 RH |
11639 | } |
11640 | ||
252b5132 RH |
11641 | /* This is called before the symbol table is processed. In order to |
11642 | work with gcc when using mips-tfile, we must keep all local labels. | |
11643 | However, in other cases, we want to discard them. If we were | |
11644 | called with -g, but we didn't see any debugging information, it may | |
11645 | mean that gcc is smuggling debugging information through to | |
11646 | mips-tfile, in which case we must generate all local labels. */ | |
11647 | ||
11648 | void | |
17a2f251 | 11649 | mips_frob_file_before_adjust (void) |
252b5132 RH |
11650 | { |
11651 | #ifndef NO_ECOFF_DEBUGGING | |
11652 | if (ECOFF_DEBUGGING | |
11653 | && mips_debug != 0 | |
11654 | && ! ecoff_debugging_seen) | |
11655 | flag_keep_locals = 1; | |
11656 | #endif | |
11657 | } | |
11658 | ||
3b91255e | 11659 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
55cf6793 | 11660 | the corresponding LO16 reloc. This is called before md_apply_fix and |
3b91255e RS |
11661 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit |
11662 | relocation operators. | |
11663 | ||
11664 | For our purposes, a %lo() expression matches a %got() or %hi() | |
11665 | expression if: | |
11666 | ||
11667 | (a) it refers to the same symbol; and | |
11668 | (b) the offset applied in the %lo() expression is no lower than | |
11669 | the offset applied in the %got() or %hi(). | |
11670 | ||
11671 | (b) allows us to cope with code like: | |
11672 | ||
11673 | lui $4,%hi(foo) | |
11674 | lh $4,%lo(foo+2)($4) | |
11675 | ||
11676 | ...which is legal on RELA targets, and has a well-defined behaviour | |
11677 | if the user knows that adding 2 to "foo" will not induce a carry to | |
11678 | the high 16 bits. | |
11679 | ||
11680 | When several %lo()s match a particular %got() or %hi(), we use the | |
11681 | following rules to distinguish them: | |
11682 | ||
11683 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
11684 | higher offsets. | |
11685 | ||
11686 | (2) %lo()s with no matching %got() or %hi() are better than those | |
11687 | that already have a matching %got() or %hi(). | |
11688 | ||
11689 | (3) later %lo()s are better than earlier %lo()s. | |
11690 | ||
11691 | These rules are applied in order. | |
11692 | ||
11693 | (1) means, among other things, that %lo()s with identical offsets are | |
11694 | chosen if they exist. | |
11695 | ||
11696 | (2) means that we won't associate several high-part relocations with | |
11697 | the same low-part relocation unless there's no alternative. Having | |
11698 | several high parts for the same low part is a GNU extension; this rule | |
11699 | allows careful users to avoid it. | |
11700 | ||
11701 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
11702 | with the last high-part relocation being at the front of the list. | |
11703 | It therefore makes sense to choose the last matching low-part | |
11704 | relocation, all other things being equal. It's also easier | |
11705 | to code that way. */ | |
252b5132 RH |
11706 | |
11707 | void | |
17a2f251 | 11708 | mips_frob_file (void) |
252b5132 RH |
11709 | { |
11710 | struct mips_hi_fixup *l; | |
11711 | ||
11712 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
11713 | { | |
11714 | segment_info_type *seginfo; | |
3b91255e RS |
11715 | bfd_boolean matched_lo_p; |
11716 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 11717 | |
5919d012 | 11718 | assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 11719 | |
5919d012 RS |
11720 | /* If a GOT16 relocation turns out to be against a global symbol, |
11721 | there isn't supposed to be a matching LO. */ | |
11722 | if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
11723 | && !pic_need_relax (l->fixp->fx_addsy, l->seg)) | |
11724 | continue; | |
11725 | ||
11726 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
11727 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
11728 | continue; |
11729 | ||
252b5132 | 11730 | seginfo = seg_info (l->seg); |
252b5132 | 11731 | |
3b91255e RS |
11732 | /* Set HI_POS to the position of this relocation in the chain. |
11733 | Set LO_POS to the position of the chosen low-part relocation. | |
11734 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
11735 | relocation that matches an immediately-preceding high-part | |
11736 | relocation. */ | |
11737 | hi_pos = NULL; | |
11738 | lo_pos = NULL; | |
11739 | matched_lo_p = FALSE; | |
11740 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) | |
11741 | { | |
11742 | if (*pos == l->fixp) | |
11743 | hi_pos = pos; | |
11744 | ||
704803a9 MR |
11745 | if (((*pos)->fx_r_type == BFD_RELOC_LO16 |
11746 | || (*pos)->fx_r_type == BFD_RELOC_MIPS16_LO16) | |
3b91255e RS |
11747 | && (*pos)->fx_addsy == l->fixp->fx_addsy |
11748 | && (*pos)->fx_offset >= l->fixp->fx_offset | |
11749 | && (lo_pos == NULL | |
11750 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
11751 | || (!matched_lo_p | |
11752 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
11753 | lo_pos = pos; | |
11754 | ||
11755 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
11756 | && fixup_has_matching_lo_p (*pos)); | |
11757 | } | |
11758 | ||
11759 | /* If we found a match, remove the high-part relocation from its | |
11760 | current position and insert it before the low-part relocation. | |
11761 | Make the offsets match so that fixup_has_matching_lo_p() | |
11762 | will return true. | |
11763 | ||
11764 | We don't warn about unmatched high-part relocations since some | |
11765 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
11766 | instructions. */ | |
11767 | if (lo_pos != NULL) | |
11768 | { | |
11769 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
11770 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 11771 | { |
3b91255e RS |
11772 | *hi_pos = l->fixp->fx_next; |
11773 | l->fixp->fx_next = *lo_pos; | |
11774 | *lo_pos = l->fixp; | |
252b5132 | 11775 | } |
252b5132 RH |
11776 | } |
11777 | } | |
11778 | } | |
11779 | ||
3e722fb5 | 11780 | /* We may have combined relocations without symbols in the N32/N64 ABI. |
f6688943 | 11781 | We have to prevent gas from dropping them. */ |
252b5132 | 11782 | |
252b5132 | 11783 | int |
17a2f251 | 11784 | mips_force_relocation (fixS *fixp) |
252b5132 | 11785 | { |
ae6063d4 | 11786 | if (generic_force_reloc (fixp)) |
252b5132 RH |
11787 | return 1; |
11788 | ||
f6688943 TS |
11789 | if (HAVE_NEWABI |
11790 | && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr | |
11791 | && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB | |
11792 | || fixp->fx_r_type == BFD_RELOC_HI16_S | |
11793 | || fixp->fx_r_type == BFD_RELOC_LO16)) | |
11794 | return 1; | |
11795 | ||
3e722fb5 | 11796 | return 0; |
252b5132 RH |
11797 | } |
11798 | ||
11799 | /* Apply a fixup to the object file. */ | |
11800 | ||
94f592af | 11801 | void |
55cf6793 | 11802 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 11803 | { |
874e8986 | 11804 | bfd_byte *buf; |
98aa84af | 11805 | long insn; |
a7ebbfdf | 11806 | reloc_howto_type *howto; |
252b5132 | 11807 | |
a7ebbfdf TS |
11808 | /* We ignore generic BFD relocations we don't know about. */ |
11809 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
11810 | if (! howto) | |
11811 | return; | |
65551fa4 | 11812 | |
252b5132 RH |
11813 | assert (fixP->fx_size == 4 |
11814 | || fixP->fx_r_type == BFD_RELOC_16 | |
11815 | || fixP->fx_r_type == BFD_RELOC_64 | |
f6688943 TS |
11816 | || fixP->fx_r_type == BFD_RELOC_CTOR |
11817 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
252b5132 | 11818 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
741d6ea8 JM |
11819 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY |
11820 | || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64); | |
252b5132 | 11821 | |
a7ebbfdf | 11822 | buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); |
252b5132 | 11823 | |
3994f87e | 11824 | assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2); |
b1dca8ee RS |
11825 | |
11826 | /* Don't treat parts of a composite relocation as done. There are two | |
11827 | reasons for this: | |
11828 | ||
11829 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
11830 | should nevertheless be emitted if the first part is. | |
11831 | ||
11832 | (2) In normal usage, composite relocations are never assembly-time | |
11833 | constants. The easiest way of dealing with the pathological | |
11834 | exceptions is to generate a relocation against STN_UNDEF and | |
11835 | leave everything up to the linker. */ | |
3994f87e | 11836 | if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0) |
252b5132 RH |
11837 | fixP->fx_done = 1; |
11838 | ||
11839 | switch (fixP->fx_r_type) | |
11840 | { | |
3f98094e DJ |
11841 | case BFD_RELOC_MIPS_TLS_GD: |
11842 | case BFD_RELOC_MIPS_TLS_LDM: | |
741d6ea8 JM |
11843 | case BFD_RELOC_MIPS_TLS_DTPREL32: |
11844 | case BFD_RELOC_MIPS_TLS_DTPREL64: | |
3f98094e DJ |
11845 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: |
11846 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
11847 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
11848 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: | |
11849 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
11850 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
11851 | /* fall through */ | |
11852 | ||
252b5132 | 11853 | case BFD_RELOC_MIPS_JMP: |
e369bcce TS |
11854 | case BFD_RELOC_MIPS_SHIFT5: |
11855 | case BFD_RELOC_MIPS_SHIFT6: | |
11856 | case BFD_RELOC_MIPS_GOT_DISP: | |
11857 | case BFD_RELOC_MIPS_GOT_PAGE: | |
11858 | case BFD_RELOC_MIPS_GOT_OFST: | |
11859 | case BFD_RELOC_MIPS_SUB: | |
11860 | case BFD_RELOC_MIPS_INSERT_A: | |
11861 | case BFD_RELOC_MIPS_INSERT_B: | |
11862 | case BFD_RELOC_MIPS_DELETE: | |
11863 | case BFD_RELOC_MIPS_HIGHEST: | |
11864 | case BFD_RELOC_MIPS_HIGHER: | |
11865 | case BFD_RELOC_MIPS_SCN_DISP: | |
11866 | case BFD_RELOC_MIPS_REL16: | |
11867 | case BFD_RELOC_MIPS_RELGOT: | |
11868 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
11869 | case BFD_RELOC_HI16: |
11870 | case BFD_RELOC_HI16_S: | |
cdf6fd85 | 11871 | case BFD_RELOC_GPREL16: |
252b5132 RH |
11872 | case BFD_RELOC_MIPS_LITERAL: |
11873 | case BFD_RELOC_MIPS_CALL16: | |
11874 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 11875 | case BFD_RELOC_GPREL32: |
252b5132 RH |
11876 | case BFD_RELOC_MIPS_GOT_HI16: |
11877 | case BFD_RELOC_MIPS_GOT_LO16: | |
11878 | case BFD_RELOC_MIPS_CALL_HI16: | |
11879 | case BFD_RELOC_MIPS_CALL_LO16: | |
11880 | case BFD_RELOC_MIPS16_GPREL: | |
d6f16593 MR |
11881 | case BFD_RELOC_MIPS16_HI16: |
11882 | case BFD_RELOC_MIPS16_HI16_S: | |
252b5132 | 11883 | case BFD_RELOC_MIPS16_JMP: |
54f4ddb3 | 11884 | /* Nothing needed to do. The value comes from the reloc entry. */ |
252b5132 RH |
11885 | break; |
11886 | ||
252b5132 RH |
11887 | case BFD_RELOC_64: |
11888 | /* This is handled like BFD_RELOC_32, but we output a sign | |
11889 | extended value if we are only 32 bits. */ | |
3e722fb5 | 11890 | if (fixP->fx_done) |
252b5132 RH |
11891 | { |
11892 | if (8 <= sizeof (valueT)) | |
2132e3a3 | 11893 | md_number_to_chars ((char *) buf, *valP, 8); |
252b5132 RH |
11894 | else |
11895 | { | |
a7ebbfdf | 11896 | valueT hiv; |
252b5132 | 11897 | |
a7ebbfdf | 11898 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
11899 | hiv = 0xffffffff; |
11900 | else | |
11901 | hiv = 0; | |
b215186b | 11902 | md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)), |
a7ebbfdf | 11903 | *valP, 4); |
b215186b | 11904 | md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)), |
a7ebbfdf | 11905 | hiv, 4); |
252b5132 RH |
11906 | } |
11907 | } | |
11908 | break; | |
11909 | ||
056350c6 | 11910 | case BFD_RELOC_RVA: |
252b5132 | 11911 | case BFD_RELOC_32: |
252b5132 RH |
11912 | case BFD_RELOC_16: |
11913 | /* If we are deleting this reloc entry, we must fill in the | |
54f4ddb3 TS |
11914 | value now. This can happen if we have a .word which is not |
11915 | resolved when it appears but is later defined. */ | |
252b5132 | 11916 | if (fixP->fx_done) |
54f4ddb3 | 11917 | md_number_to_chars ((char *) buf, *valP, fixP->fx_size); |
252b5132 RH |
11918 | break; |
11919 | ||
11920 | case BFD_RELOC_LO16: | |
d6f16593 | 11921 | case BFD_RELOC_MIPS16_LO16: |
3e722fb5 CD |
11922 | /* FIXME: Now that embedded-PIC is gone, some of this code/comment |
11923 | may be safe to remove, but if so it's not obvious. */ | |
252b5132 RH |
11924 | /* When handling an embedded PIC switch statement, we can wind |
11925 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
11926 | if (fixP->fx_done) | |
11927 | { | |
a7ebbfdf | 11928 | if (*valP + 0x8000 > 0xffff) |
252b5132 RH |
11929 | as_bad_where (fixP->fx_file, fixP->fx_line, |
11930 | _("relocation overflow")); | |
252b5132 RH |
11931 | if (target_big_endian) |
11932 | buf += 2; | |
2132e3a3 | 11933 | md_number_to_chars ((char *) buf, *valP, 2); |
252b5132 RH |
11934 | } |
11935 | break; | |
11936 | ||
11937 | case BFD_RELOC_16_PCREL_S2: | |
a7ebbfdf | 11938 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 11939 | as_bad_where (fixP->fx_file, fixP->fx_line, |
bad36eac | 11940 | _("Branch to misaligned address (%lx)"), (long) *valP); |
cb56d3d3 | 11941 | |
54f4ddb3 TS |
11942 | /* We need to save the bits in the instruction since fixup_segment() |
11943 | might be deleting the relocation entry (i.e., a branch within | |
11944 | the current segment). */ | |
a7ebbfdf | 11945 | if (! fixP->fx_done) |
bb2d6cd7 | 11946 | break; |
252b5132 | 11947 | |
54f4ddb3 | 11948 | /* Update old instruction data. */ |
252b5132 RH |
11949 | if (target_big_endian) |
11950 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
11951 | else | |
11952 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
11953 | ||
a7ebbfdf TS |
11954 | if (*valP + 0x20000 <= 0x3ffff) |
11955 | { | |
11956 | insn |= (*valP >> 2) & 0xffff; | |
2132e3a3 | 11957 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
11958 | } |
11959 | else if (mips_pic == NO_PIC | |
11960 | && fixP->fx_done | |
11961 | && fixP->fx_frag->fr_address >= text_section->vma | |
11962 | && (fixP->fx_frag->fr_address | |
587aac4e | 11963 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
11964 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
11965 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
11966 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
11967 | { |
11968 | /* The branch offset is too large. If this is an | |
11969 | unconditional branch, and we are not generating PIC code, | |
11970 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
11971 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
11972 | insn = 0x0c000000; /* jal */ | |
252b5132 | 11973 | else |
a7ebbfdf TS |
11974 | insn = 0x08000000; /* j */ |
11975 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
11976 | fixP->fx_done = 0; | |
11977 | fixP->fx_addsy = section_symbol (text_section); | |
11978 | *valP += md_pcrel_from (fixP); | |
2132e3a3 | 11979 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
11980 | } |
11981 | else | |
11982 | { | |
11983 | /* If we got here, we have branch-relaxation disabled, | |
11984 | and there's nothing we can do to fix this instruction | |
11985 | without turning it into a longer sequence. */ | |
11986 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11987 | _("Branch out of range")); | |
252b5132 | 11988 | } |
252b5132 RH |
11989 | break; |
11990 | ||
11991 | case BFD_RELOC_VTABLE_INHERIT: | |
11992 | fixP->fx_done = 0; | |
11993 | if (fixP->fx_addsy | |
11994 | && !S_IS_DEFINED (fixP->fx_addsy) | |
11995 | && !S_IS_WEAK (fixP->fx_addsy)) | |
11996 | S_SET_WEAK (fixP->fx_addsy); | |
11997 | break; | |
11998 | ||
11999 | case BFD_RELOC_VTABLE_ENTRY: | |
12000 | fixP->fx_done = 0; | |
12001 | break; | |
12002 | ||
12003 | default: | |
12004 | internalError (); | |
12005 | } | |
a7ebbfdf TS |
12006 | |
12007 | /* Remember value for tc_gen_reloc. */ | |
12008 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
12009 | } |
12010 | ||
252b5132 | 12011 | static symbolS * |
17a2f251 | 12012 | get_symbol (void) |
252b5132 RH |
12013 | { |
12014 | int c; | |
12015 | char *name; | |
12016 | symbolS *p; | |
12017 | ||
12018 | name = input_line_pointer; | |
12019 | c = get_symbol_end (); | |
12020 | p = (symbolS *) symbol_find_or_make (name); | |
12021 | *input_line_pointer = c; | |
12022 | return p; | |
12023 | } | |
12024 | ||
12025 | /* Align the current frag to a given power of two. The MIPS assembler | |
12026 | also automatically adjusts any preceding label. */ | |
12027 | ||
12028 | static void | |
17a2f251 | 12029 | mips_align (int to, int fill, symbolS *label) |
252b5132 | 12030 | { |
7d10b47d | 12031 | mips_emit_delays (); |
252b5132 RH |
12032 | frag_align (to, fill, 0); |
12033 | record_alignment (now_seg, to); | |
12034 | if (label != NULL) | |
12035 | { | |
12036 | assert (S_GET_SEGMENT (label) == now_seg); | |
49309057 | 12037 | symbol_set_frag (label, frag_now); |
252b5132 RH |
12038 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
12039 | } | |
12040 | } | |
12041 | ||
12042 | /* Align to a given power of two. .align 0 turns off the automatic | |
12043 | alignment used by the data creating pseudo-ops. */ | |
12044 | ||
12045 | static void | |
17a2f251 | 12046 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 | 12047 | { |
3994f87e TS |
12048 | int temp; |
12049 | long temp_fill; | |
49954fb4 | 12050 | long max_alignment = 28; |
252b5132 | 12051 | |
54f4ddb3 | 12052 | /* o Note that the assembler pulls down any immediately preceding label |
252b5132 | 12053 | to the aligned address. |
54f4ddb3 | 12054 | o It's not documented but auto alignment is reinstated by |
252b5132 | 12055 | a .align pseudo instruction. |
54f4ddb3 | 12056 | o Note also that after auto alignment is turned off the mips assembler |
252b5132 | 12057 | issues an error on attempt to assemble an improperly aligned data item. |
54f4ddb3 | 12058 | We don't. */ |
252b5132 RH |
12059 | |
12060 | temp = get_absolute_expression (); | |
12061 | if (temp > max_alignment) | |
12062 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
12063 | else if (temp < 0) | |
12064 | { | |
12065 | as_warn (_("Alignment negative: 0 assumed.")); | |
12066 | temp = 0; | |
12067 | } | |
12068 | if (*input_line_pointer == ',') | |
12069 | { | |
f9419b05 | 12070 | ++input_line_pointer; |
252b5132 RH |
12071 | temp_fill = get_absolute_expression (); |
12072 | } | |
12073 | else | |
12074 | temp_fill = 0; | |
12075 | if (temp) | |
12076 | { | |
a8dbcb85 TS |
12077 | segment_info_type *si = seg_info (now_seg); |
12078 | struct insn_label_list *l = si->label_list; | |
54f4ddb3 | 12079 | /* Auto alignment should be switched on by next section change. */ |
252b5132 | 12080 | auto_align = 1; |
a8dbcb85 | 12081 | mips_align (temp, (int) temp_fill, l != NULL ? l->label : NULL); |
252b5132 RH |
12082 | } |
12083 | else | |
12084 | { | |
12085 | auto_align = 0; | |
12086 | } | |
12087 | ||
12088 | demand_empty_rest_of_line (); | |
12089 | } | |
12090 | ||
252b5132 | 12091 | static void |
17a2f251 | 12092 | s_change_sec (int sec) |
252b5132 RH |
12093 | { |
12094 | segT seg; | |
12095 | ||
252b5132 RH |
12096 | #ifdef OBJ_ELF |
12097 | /* The ELF backend needs to know that we are changing sections, so | |
12098 | that .previous works correctly. We could do something like check | |
b6ff326e | 12099 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
12100 | as it would not be appropriate to use it in the section changing |
12101 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
12102 | This should be cleaner, somehow. */ | |
f43abd2b TS |
12103 | if (IS_ELF) |
12104 | obj_elf_section_change_hook (); | |
252b5132 RH |
12105 | #endif |
12106 | ||
7d10b47d | 12107 | mips_emit_delays (); |
252b5132 RH |
12108 | switch (sec) |
12109 | { | |
12110 | case 't': | |
12111 | s_text (0); | |
12112 | break; | |
12113 | case 'd': | |
12114 | s_data (0); | |
12115 | break; | |
12116 | case 'b': | |
12117 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
12118 | demand_empty_rest_of_line (); | |
12119 | break; | |
12120 | ||
12121 | case 'r': | |
4d0d148d TS |
12122 | seg = subseg_new (RDATA_SECTION_NAME, |
12123 | (subsegT) get_absolute_expression ()); | |
f43abd2b | 12124 | if (IS_ELF) |
252b5132 | 12125 | { |
4d0d148d TS |
12126 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
12127 | | SEC_READONLY | SEC_RELOC | |
12128 | | SEC_DATA)); | |
12129 | if (strcmp (TARGET_OS, "elf") != 0) | |
12130 | record_alignment (seg, 4); | |
252b5132 | 12131 | } |
4d0d148d | 12132 | demand_empty_rest_of_line (); |
252b5132 RH |
12133 | break; |
12134 | ||
12135 | case 's': | |
4d0d148d | 12136 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
f43abd2b | 12137 | if (IS_ELF) |
252b5132 | 12138 | { |
4d0d148d TS |
12139 | bfd_set_section_flags (stdoutput, seg, |
12140 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
12141 | if (strcmp (TARGET_OS, "elf") != 0) | |
12142 | record_alignment (seg, 4); | |
252b5132 | 12143 | } |
4d0d148d TS |
12144 | demand_empty_rest_of_line (); |
12145 | break; | |
252b5132 RH |
12146 | } |
12147 | ||
12148 | auto_align = 1; | |
12149 | } | |
b34976b6 | 12150 | |
cca86cc8 | 12151 | void |
17a2f251 | 12152 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 12153 | { |
7ed4a06a | 12154 | #ifdef OBJ_ELF |
cca86cc8 SC |
12155 | char *section_name; |
12156 | char c; | |
684022ea | 12157 | char next_c = 0; |
cca86cc8 SC |
12158 | int section_type; |
12159 | int section_flag; | |
12160 | int section_entry_size; | |
12161 | int section_alignment; | |
b34976b6 | 12162 | |
f43abd2b | 12163 | if (!IS_ELF) |
7ed4a06a TS |
12164 | return; |
12165 | ||
cca86cc8 SC |
12166 | section_name = input_line_pointer; |
12167 | c = get_symbol_end (); | |
a816d1ed AO |
12168 | if (c) |
12169 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 12170 | |
4cf0dd0d TS |
12171 | /* Do we have .section Name<,"flags">? */ |
12172 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 12173 | { |
4cf0dd0d TS |
12174 | /* just after name is now '\0'. */ |
12175 | *input_line_pointer = c; | |
cca86cc8 SC |
12176 | input_line_pointer = section_name; |
12177 | obj_elf_section (ignore); | |
12178 | return; | |
12179 | } | |
12180 | input_line_pointer++; | |
12181 | ||
12182 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
12183 | if (c == ',') | |
12184 | section_type = get_absolute_expression (); | |
12185 | else | |
12186 | section_type = 0; | |
12187 | if (*input_line_pointer++ == ',') | |
12188 | section_flag = get_absolute_expression (); | |
12189 | else | |
12190 | section_flag = 0; | |
12191 | if (*input_line_pointer++ == ',') | |
12192 | section_entry_size = get_absolute_expression (); | |
12193 | else | |
12194 | section_entry_size = 0; | |
12195 | if (*input_line_pointer++ == ',') | |
12196 | section_alignment = get_absolute_expression (); | |
12197 | else | |
12198 | section_alignment = 0; | |
12199 | ||
a816d1ed AO |
12200 | section_name = xstrdup (section_name); |
12201 | ||
8ab8a5c8 RS |
12202 | /* When using the generic form of .section (as implemented by obj-elf.c), |
12203 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
12204 | traditionally had to fall back on the more common @progbits instead. | |
12205 | ||
12206 | There's nothing really harmful in this, since bfd will correct | |
12207 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
708587a4 | 12208 | means that, for backwards compatibility, the special_section entries |
8ab8a5c8 RS |
12209 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. |
12210 | ||
12211 | Even so, we shouldn't force users of the MIPS .section syntax to | |
12212 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
12213 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
12214 | generic type-checking code. */ | |
12215 | if (section_type == SHT_MIPS_DWARF) | |
12216 | section_type = SHT_PROGBITS; | |
12217 | ||
cca86cc8 SC |
12218 | obj_elf_change_section (section_name, section_type, section_flag, |
12219 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
12220 | |
12221 | if (now_seg->name != section_name) | |
12222 | free (section_name); | |
7ed4a06a | 12223 | #endif /* OBJ_ELF */ |
cca86cc8 | 12224 | } |
252b5132 RH |
12225 | |
12226 | void | |
17a2f251 | 12227 | mips_enable_auto_align (void) |
252b5132 RH |
12228 | { |
12229 | auto_align = 1; | |
12230 | } | |
12231 | ||
12232 | static void | |
17a2f251 | 12233 | s_cons (int log_size) |
252b5132 | 12234 | { |
a8dbcb85 TS |
12235 | segment_info_type *si = seg_info (now_seg); |
12236 | struct insn_label_list *l = si->label_list; | |
252b5132 RH |
12237 | symbolS *label; |
12238 | ||
a8dbcb85 | 12239 | label = l != NULL ? l->label : NULL; |
7d10b47d | 12240 | mips_emit_delays (); |
252b5132 RH |
12241 | if (log_size > 0 && auto_align) |
12242 | mips_align (log_size, 0, label); | |
12243 | mips_clear_insn_labels (); | |
12244 | cons (1 << log_size); | |
12245 | } | |
12246 | ||
12247 | static void | |
17a2f251 | 12248 | s_float_cons (int type) |
252b5132 | 12249 | { |
a8dbcb85 TS |
12250 | segment_info_type *si = seg_info (now_seg); |
12251 | struct insn_label_list *l = si->label_list; | |
252b5132 RH |
12252 | symbolS *label; |
12253 | ||
a8dbcb85 | 12254 | label = l != NULL ? l->label : NULL; |
252b5132 | 12255 | |
7d10b47d | 12256 | mips_emit_delays (); |
252b5132 RH |
12257 | |
12258 | if (auto_align) | |
49309057 ILT |
12259 | { |
12260 | if (type == 'd') | |
12261 | mips_align (3, 0, label); | |
12262 | else | |
12263 | mips_align (2, 0, label); | |
12264 | } | |
252b5132 RH |
12265 | |
12266 | mips_clear_insn_labels (); | |
12267 | ||
12268 | float_cons (type); | |
12269 | } | |
12270 | ||
12271 | /* Handle .globl. We need to override it because on Irix 5 you are | |
12272 | permitted to say | |
12273 | .globl foo .text | |
12274 | where foo is an undefined symbol, to mean that foo should be | |
12275 | considered to be the address of a function. */ | |
12276 | ||
12277 | static void | |
17a2f251 | 12278 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
12279 | { |
12280 | char *name; | |
12281 | int c; | |
12282 | symbolS *symbolP; | |
12283 | flagword flag; | |
12284 | ||
8a06b769 | 12285 | do |
252b5132 | 12286 | { |
8a06b769 | 12287 | name = input_line_pointer; |
252b5132 | 12288 | c = get_symbol_end (); |
8a06b769 TS |
12289 | symbolP = symbol_find_or_make (name); |
12290 | S_SET_EXTERNAL (symbolP); | |
12291 | ||
252b5132 | 12292 | *input_line_pointer = c; |
8a06b769 | 12293 | SKIP_WHITESPACE (); |
252b5132 | 12294 | |
8a06b769 TS |
12295 | /* On Irix 5, every global symbol that is not explicitly labelled as |
12296 | being a function is apparently labelled as being an object. */ | |
12297 | flag = BSF_OBJECT; | |
252b5132 | 12298 | |
8a06b769 TS |
12299 | if (!is_end_of_line[(unsigned char) *input_line_pointer] |
12300 | && (*input_line_pointer != ',')) | |
12301 | { | |
12302 | char *secname; | |
12303 | asection *sec; | |
12304 | ||
12305 | secname = input_line_pointer; | |
12306 | c = get_symbol_end (); | |
12307 | sec = bfd_get_section_by_name (stdoutput, secname); | |
12308 | if (sec == NULL) | |
12309 | as_bad (_("%s: no such section"), secname); | |
12310 | *input_line_pointer = c; | |
12311 | ||
12312 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
12313 | flag = BSF_FUNCTION; | |
12314 | } | |
12315 | ||
12316 | symbol_get_bfdsym (symbolP)->flags |= flag; | |
12317 | ||
12318 | c = *input_line_pointer; | |
12319 | if (c == ',') | |
12320 | { | |
12321 | input_line_pointer++; | |
12322 | SKIP_WHITESPACE (); | |
12323 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
12324 | c = '\n'; | |
12325 | } | |
12326 | } | |
12327 | while (c == ','); | |
252b5132 | 12328 | |
252b5132 RH |
12329 | demand_empty_rest_of_line (); |
12330 | } | |
12331 | ||
12332 | static void | |
17a2f251 | 12333 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
12334 | { |
12335 | char *opt; | |
12336 | char c; | |
12337 | ||
12338 | opt = input_line_pointer; | |
12339 | c = get_symbol_end (); | |
12340 | ||
12341 | if (*opt == 'O') | |
12342 | { | |
12343 | /* FIXME: What does this mean? */ | |
12344 | } | |
12345 | else if (strncmp (opt, "pic", 3) == 0) | |
12346 | { | |
12347 | int i; | |
12348 | ||
12349 | i = atoi (opt + 3); | |
12350 | if (i == 0) | |
12351 | mips_pic = NO_PIC; | |
12352 | else if (i == 2) | |
143d77c5 | 12353 | { |
252b5132 | 12354 | mips_pic = SVR4_PIC; |
143d77c5 EC |
12355 | mips_abicalls = TRUE; |
12356 | } | |
252b5132 RH |
12357 | else |
12358 | as_bad (_(".option pic%d not supported"), i); | |
12359 | ||
4d0d148d | 12360 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
12361 | { |
12362 | if (g_switch_seen && g_switch_value != 0) | |
12363 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
12364 | g_switch_value = 0; | |
12365 | bfd_set_gp_size (stdoutput, 0); | |
12366 | } | |
12367 | } | |
12368 | else | |
12369 | as_warn (_("Unrecognized option \"%s\""), opt); | |
12370 | ||
12371 | *input_line_pointer = c; | |
12372 | demand_empty_rest_of_line (); | |
12373 | } | |
12374 | ||
12375 | /* This structure is used to hold a stack of .set values. */ | |
12376 | ||
e972090a NC |
12377 | struct mips_option_stack |
12378 | { | |
252b5132 RH |
12379 | struct mips_option_stack *next; |
12380 | struct mips_set_options options; | |
12381 | }; | |
12382 | ||
12383 | static struct mips_option_stack *mips_opts_stack; | |
12384 | ||
12385 | /* Handle the .set pseudo-op. */ | |
12386 | ||
12387 | static void | |
17a2f251 | 12388 | s_mipsset (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
12389 | { |
12390 | char *name = input_line_pointer, ch; | |
12391 | ||
12392 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 12393 | ++input_line_pointer; |
252b5132 RH |
12394 | ch = *input_line_pointer; |
12395 | *input_line_pointer = '\0'; | |
12396 | ||
12397 | if (strcmp (name, "reorder") == 0) | |
12398 | { | |
7d10b47d RS |
12399 | if (mips_opts.noreorder) |
12400 | end_noreorder (); | |
252b5132 RH |
12401 | } |
12402 | else if (strcmp (name, "noreorder") == 0) | |
12403 | { | |
7d10b47d RS |
12404 | if (!mips_opts.noreorder) |
12405 | start_noreorder (); | |
252b5132 RH |
12406 | } |
12407 | else if (strcmp (name, "at") == 0) | |
12408 | { | |
12409 | mips_opts.noat = 0; | |
12410 | } | |
12411 | else if (strcmp (name, "noat") == 0) | |
12412 | { | |
12413 | mips_opts.noat = 1; | |
12414 | } | |
12415 | else if (strcmp (name, "macro") == 0) | |
12416 | { | |
12417 | mips_opts.warn_about_macros = 0; | |
12418 | } | |
12419 | else if (strcmp (name, "nomacro") == 0) | |
12420 | { | |
12421 | if (mips_opts.noreorder == 0) | |
12422 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
12423 | mips_opts.warn_about_macros = 1; | |
12424 | } | |
12425 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
12426 | { | |
12427 | mips_opts.nomove = 0; | |
12428 | } | |
12429 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
12430 | { | |
12431 | mips_opts.nomove = 1; | |
12432 | } | |
12433 | else if (strcmp (name, "bopt") == 0) | |
12434 | { | |
12435 | mips_opts.nobopt = 0; | |
12436 | } | |
12437 | else if (strcmp (name, "nobopt") == 0) | |
12438 | { | |
12439 | mips_opts.nobopt = 1; | |
12440 | } | |
ad3fea08 TS |
12441 | else if (strcmp (name, "gp=default") == 0) |
12442 | mips_opts.gp32 = file_mips_gp32; | |
12443 | else if (strcmp (name, "gp=32") == 0) | |
12444 | mips_opts.gp32 = 1; | |
12445 | else if (strcmp (name, "gp=64") == 0) | |
12446 | { | |
12447 | if (!ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
12448 | as_warn ("%s isa does not support 64-bit registers", | |
12449 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
12450 | mips_opts.gp32 = 0; | |
12451 | } | |
12452 | else if (strcmp (name, "fp=default") == 0) | |
12453 | mips_opts.fp32 = file_mips_fp32; | |
12454 | else if (strcmp (name, "fp=32") == 0) | |
12455 | mips_opts.fp32 = 1; | |
12456 | else if (strcmp (name, "fp=64") == 0) | |
12457 | { | |
12458 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
12459 | as_warn ("%s isa does not support 64-bit floating point registers", | |
12460 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
12461 | mips_opts.fp32 = 0; | |
12462 | } | |
252b5132 RH |
12463 | else if (strcmp (name, "mips16") == 0 |
12464 | || strcmp (name, "MIPS-16") == 0) | |
12465 | mips_opts.mips16 = 1; | |
12466 | else if (strcmp (name, "nomips16") == 0 | |
12467 | || strcmp (name, "noMIPS-16") == 0) | |
12468 | mips_opts.mips16 = 0; | |
e16bfa71 TS |
12469 | else if (strcmp (name, "smartmips") == 0) |
12470 | { | |
ad3fea08 | 12471 | if (!ISA_SUPPORTS_SMARTMIPS) |
e16bfa71 TS |
12472 | as_warn ("%s ISA does not support SmartMIPS ASE", |
12473 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
12474 | mips_opts.ase_smartmips = 1; | |
12475 | } | |
12476 | else if (strcmp (name, "nosmartmips") == 0) | |
12477 | mips_opts.ase_smartmips = 0; | |
1f25f5d3 CD |
12478 | else if (strcmp (name, "mips3d") == 0) |
12479 | mips_opts.ase_mips3d = 1; | |
12480 | else if (strcmp (name, "nomips3d") == 0) | |
12481 | mips_opts.ase_mips3d = 0; | |
a4672219 TS |
12482 | else if (strcmp (name, "mdmx") == 0) |
12483 | mips_opts.ase_mdmx = 1; | |
12484 | else if (strcmp (name, "nomdmx") == 0) | |
12485 | mips_opts.ase_mdmx = 0; | |
74cd071d | 12486 | else if (strcmp (name, "dsp") == 0) |
ad3fea08 TS |
12487 | { |
12488 | if (!ISA_SUPPORTS_DSP_ASE) | |
12489 | as_warn ("%s ISA does not support DSP ASE", | |
12490 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
12491 | mips_opts.ase_dsp = 1; | |
8b082fb1 | 12492 | mips_opts.ase_dspr2 = 0; |
ad3fea08 | 12493 | } |
74cd071d | 12494 | else if (strcmp (name, "nodsp") == 0) |
8b082fb1 TS |
12495 | { |
12496 | mips_opts.ase_dsp = 0; | |
12497 | mips_opts.ase_dspr2 = 0; | |
12498 | } | |
12499 | else if (strcmp (name, "dspr2") == 0) | |
12500 | { | |
12501 | if (!ISA_SUPPORTS_DSPR2_ASE) | |
12502 | as_warn ("%s ISA does not support DSP R2 ASE", | |
12503 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
12504 | mips_opts.ase_dspr2 = 1; | |
12505 | mips_opts.ase_dsp = 1; | |
12506 | } | |
12507 | else if (strcmp (name, "nodspr2") == 0) | |
12508 | { | |
12509 | mips_opts.ase_dspr2 = 0; | |
12510 | mips_opts.ase_dsp = 0; | |
12511 | } | |
ef2e4d86 | 12512 | else if (strcmp (name, "mt") == 0) |
ad3fea08 TS |
12513 | { |
12514 | if (!ISA_SUPPORTS_MT_ASE) | |
12515 | as_warn ("%s ISA does not support MT ASE", | |
12516 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
12517 | mips_opts.ase_mt = 1; | |
12518 | } | |
ef2e4d86 CF |
12519 | else if (strcmp (name, "nomt") == 0) |
12520 | mips_opts.ase_mt = 0; | |
1a2c1fad | 12521 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 12522 | { |
af7ee8bf | 12523 | int reset = 0; |
252b5132 | 12524 | |
1a2c1fad CD |
12525 | /* Permit the user to change the ISA and architecture on the fly. |
12526 | Needless to say, misuse can cause serious problems. */ | |
81a21e38 | 12527 | if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) |
af7ee8bf CD |
12528 | { |
12529 | reset = 1; | |
12530 | mips_opts.isa = file_mips_isa; | |
1a2c1fad | 12531 | mips_opts.arch = file_mips_arch; |
1a2c1fad CD |
12532 | } |
12533 | else if (strncmp (name, "arch=", 5) == 0) | |
12534 | { | |
12535 | const struct mips_cpu_info *p; | |
12536 | ||
12537 | p = mips_parse_cpu("internal use", name + 5); | |
12538 | if (!p) | |
12539 | as_bad (_("unknown architecture %s"), name + 5); | |
12540 | else | |
12541 | { | |
12542 | mips_opts.arch = p->cpu; | |
12543 | mips_opts.isa = p->isa; | |
12544 | } | |
12545 | } | |
81a21e38 TS |
12546 | else if (strncmp (name, "mips", 4) == 0) |
12547 | { | |
12548 | const struct mips_cpu_info *p; | |
12549 | ||
12550 | p = mips_parse_cpu("internal use", name); | |
12551 | if (!p) | |
12552 | as_bad (_("unknown ISA level %s"), name + 4); | |
12553 | else | |
12554 | { | |
12555 | mips_opts.arch = p->cpu; | |
12556 | mips_opts.isa = p->isa; | |
12557 | } | |
12558 | } | |
af7ee8bf | 12559 | else |
81a21e38 | 12560 | as_bad (_("unknown ISA or architecture %s"), name); |
af7ee8bf CD |
12561 | |
12562 | switch (mips_opts.isa) | |
98d3f06f KH |
12563 | { |
12564 | case 0: | |
98d3f06f | 12565 | break; |
af7ee8bf CD |
12566 | case ISA_MIPS1: |
12567 | case ISA_MIPS2: | |
12568 | case ISA_MIPS32: | |
12569 | case ISA_MIPS32R2: | |
98d3f06f KH |
12570 | mips_opts.gp32 = 1; |
12571 | mips_opts.fp32 = 1; | |
12572 | break; | |
af7ee8bf CD |
12573 | case ISA_MIPS3: |
12574 | case ISA_MIPS4: | |
12575 | case ISA_MIPS5: | |
12576 | case ISA_MIPS64: | |
5f74bc13 | 12577 | case ISA_MIPS64R2: |
98d3f06f KH |
12578 | mips_opts.gp32 = 0; |
12579 | mips_opts.fp32 = 0; | |
12580 | break; | |
12581 | default: | |
12582 | as_bad (_("unknown ISA level %s"), name + 4); | |
12583 | break; | |
12584 | } | |
af7ee8bf | 12585 | if (reset) |
98d3f06f | 12586 | { |
af7ee8bf CD |
12587 | mips_opts.gp32 = file_mips_gp32; |
12588 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 12589 | } |
252b5132 RH |
12590 | } |
12591 | else if (strcmp (name, "autoextend") == 0) | |
12592 | mips_opts.noautoextend = 0; | |
12593 | else if (strcmp (name, "noautoextend") == 0) | |
12594 | mips_opts.noautoextend = 1; | |
12595 | else if (strcmp (name, "push") == 0) | |
12596 | { | |
12597 | struct mips_option_stack *s; | |
12598 | ||
12599 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
12600 | s->next = mips_opts_stack; | |
12601 | s->options = mips_opts; | |
12602 | mips_opts_stack = s; | |
12603 | } | |
12604 | else if (strcmp (name, "pop") == 0) | |
12605 | { | |
12606 | struct mips_option_stack *s; | |
12607 | ||
12608 | s = mips_opts_stack; | |
12609 | if (s == NULL) | |
12610 | as_bad (_(".set pop with no .set push")); | |
12611 | else | |
12612 | { | |
12613 | /* If we're changing the reorder mode we need to handle | |
12614 | delay slots correctly. */ | |
12615 | if (s->options.noreorder && ! mips_opts.noreorder) | |
7d10b47d | 12616 | start_noreorder (); |
252b5132 | 12617 | else if (! s->options.noreorder && mips_opts.noreorder) |
7d10b47d | 12618 | end_noreorder (); |
252b5132 RH |
12619 | |
12620 | mips_opts = s->options; | |
12621 | mips_opts_stack = s->next; | |
12622 | free (s); | |
12623 | } | |
12624 | } | |
aed1a261 RS |
12625 | else if (strcmp (name, "sym32") == 0) |
12626 | mips_opts.sym32 = TRUE; | |
12627 | else if (strcmp (name, "nosym32") == 0) | |
12628 | mips_opts.sym32 = FALSE; | |
e6559e01 JM |
12629 | else if (strchr (name, ',')) |
12630 | { | |
12631 | /* Generic ".set" directive; use the generic handler. */ | |
12632 | *input_line_pointer = ch; | |
12633 | input_line_pointer = name; | |
12634 | s_set (0); | |
12635 | return; | |
12636 | } | |
252b5132 RH |
12637 | else |
12638 | { | |
12639 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
12640 | } | |
12641 | *input_line_pointer = ch; | |
12642 | demand_empty_rest_of_line (); | |
12643 | } | |
12644 | ||
12645 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
12646 | .option pic2. It means to generate SVR4 PIC calls. */ | |
12647 | ||
12648 | static void | |
17a2f251 | 12649 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12650 | { |
12651 | mips_pic = SVR4_PIC; | |
143d77c5 | 12652 | mips_abicalls = TRUE; |
4d0d148d TS |
12653 | |
12654 | if (g_switch_seen && g_switch_value != 0) | |
12655 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
12656 | g_switch_value = 0; | |
12657 | ||
252b5132 RH |
12658 | bfd_set_gp_size (stdoutput, 0); |
12659 | demand_empty_rest_of_line (); | |
12660 | } | |
12661 | ||
12662 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
12663 | PIC code. It sets the $gp register for the function based on the | |
12664 | function address, which is in the register named in the argument. | |
12665 | This uses a relocation against _gp_disp, which is handled specially | |
12666 | by the linker. The result is: | |
12667 | lui $gp,%hi(_gp_disp) | |
12668 | addiu $gp,$gp,%lo(_gp_disp) | |
12669 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
12670 | The .cpload argument is normally $25 == $t9. |
12671 | ||
12672 | The -mno-shared option changes this to: | |
bbe506e8 TS |
12673 | lui $gp,%hi(__gnu_local_gp) |
12674 | addiu $gp,$gp,%lo(__gnu_local_gp) | |
aa6975fb ILT |
12675 | and the argument is ignored. This saves an instruction, but the |
12676 | resulting code is not position independent; it uses an absolute | |
bbe506e8 TS |
12677 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
12678 | can go into an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
12679 | |
12680 | static void | |
17a2f251 | 12681 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12682 | { |
12683 | expressionS ex; | |
aa6975fb ILT |
12684 | int reg; |
12685 | int in_shared; | |
252b5132 | 12686 | |
6478892d TS |
12687 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
12688 | .cpload is ignored. */ | |
12689 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
12690 | { |
12691 | s_ignore (0); | |
12692 | return; | |
12693 | } | |
12694 | ||
d3ecfc59 | 12695 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
12696 | if (mips_opts.noreorder == 0) |
12697 | as_warn (_(".cpload not in noreorder section")); | |
12698 | ||
aa6975fb ILT |
12699 | reg = tc_get_register (0); |
12700 | ||
12701 | /* If we need to produce a 64-bit address, we are better off using | |
12702 | the default instruction sequence. */ | |
aed1a261 | 12703 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
aa6975fb | 12704 | |
252b5132 | 12705 | ex.X_op = O_symbol; |
bbe506e8 TS |
12706 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
12707 | "__gnu_local_gp"); | |
252b5132 RH |
12708 | ex.X_op_symbol = NULL; |
12709 | ex.X_add_number = 0; | |
12710 | ||
12711 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 12712 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 12713 | |
584892a6 | 12714 | macro_start (); |
67c0d1eb RS |
12715 | macro_build_lui (&ex, mips_gp_register); |
12716 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 12717 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
12718 | if (in_shared) |
12719 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
12720 | mips_gp_register, reg); | |
584892a6 | 12721 | macro_end (); |
252b5132 RH |
12722 | |
12723 | demand_empty_rest_of_line (); | |
12724 | } | |
12725 | ||
6478892d TS |
12726 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
12727 | .cpsetup $reg1, offset|$reg2, label | |
12728 | ||
12729 | If offset is given, this results in: | |
12730 | sd $gp, offset($sp) | |
956cd1d6 | 12731 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
12732 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
12733 | daddu $gp, $gp, $reg1 | |
6478892d TS |
12734 | |
12735 | If $reg2 is given, this results in: | |
12736 | daddu $reg2, $gp, $0 | |
956cd1d6 | 12737 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
12738 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
12739 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
12740 | $reg1 is normally $25 == $t9. |
12741 | ||
12742 | The -mno-shared option replaces the last three instructions with | |
12743 | lui $gp,%hi(_gp) | |
54f4ddb3 | 12744 | addiu $gp,$gp,%lo(_gp) */ |
aa6975fb | 12745 | |
6478892d | 12746 | static void |
17a2f251 | 12747 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12748 | { |
12749 | expressionS ex_off; | |
12750 | expressionS ex_sym; | |
12751 | int reg1; | |
6478892d | 12752 | |
8586fc66 | 12753 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
12754 | We also need NewABI support. */ |
12755 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12756 | { | |
12757 | s_ignore (0); | |
12758 | return; | |
12759 | } | |
12760 | ||
12761 | reg1 = tc_get_register (0); | |
12762 | SKIP_WHITESPACE (); | |
12763 | if (*input_line_pointer != ',') | |
12764 | { | |
12765 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
12766 | return; | |
12767 | } | |
12768 | else | |
80245285 | 12769 | ++input_line_pointer; |
6478892d TS |
12770 | SKIP_WHITESPACE (); |
12771 | if (*input_line_pointer == '$') | |
80245285 TS |
12772 | { |
12773 | mips_cpreturn_register = tc_get_register (0); | |
12774 | mips_cpreturn_offset = -1; | |
12775 | } | |
6478892d | 12776 | else |
80245285 TS |
12777 | { |
12778 | mips_cpreturn_offset = get_absolute_expression (); | |
12779 | mips_cpreturn_register = -1; | |
12780 | } | |
6478892d TS |
12781 | SKIP_WHITESPACE (); |
12782 | if (*input_line_pointer != ',') | |
12783 | { | |
12784 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
12785 | return; | |
12786 | } | |
12787 | else | |
f9419b05 | 12788 | ++input_line_pointer; |
6478892d | 12789 | SKIP_WHITESPACE (); |
f21f8242 | 12790 | expression (&ex_sym); |
6478892d | 12791 | |
584892a6 | 12792 | macro_start (); |
6478892d TS |
12793 | if (mips_cpreturn_register == -1) |
12794 | { | |
12795 | ex_off.X_op = O_constant; | |
12796 | ex_off.X_add_symbol = NULL; | |
12797 | ex_off.X_op_symbol = NULL; | |
12798 | ex_off.X_add_number = mips_cpreturn_offset; | |
12799 | ||
67c0d1eb | 12800 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 12801 | BFD_RELOC_LO16, SP); |
6478892d TS |
12802 | } |
12803 | else | |
67c0d1eb | 12804 | macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, |
17a2f251 | 12805 | mips_gp_register, 0); |
6478892d | 12806 | |
aed1a261 | 12807 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
aa6975fb ILT |
12808 | { |
12809 | macro_build (&ex_sym, "lui", "t,u", mips_gp_register, | |
12810 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, | |
12811 | BFD_RELOC_HI16_S); | |
12812 | ||
12813 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
12814 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
12815 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
12816 | ||
12817 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
12818 | mips_gp_register, reg1); | |
12819 | } | |
12820 | else | |
12821 | { | |
12822 | expressionS ex; | |
12823 | ||
12824 | ex.X_op = O_symbol; | |
4184909a | 12825 | ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); |
aa6975fb ILT |
12826 | ex.X_op_symbol = NULL; |
12827 | ex.X_add_number = 0; | |
6e1304d8 | 12828 | |
aa6975fb ILT |
12829 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
12830 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
12831 | ||
12832 | macro_build_lui (&ex, mips_gp_register); | |
12833 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
12834 | mips_gp_register, BFD_RELOC_LO16); | |
12835 | } | |
f21f8242 | 12836 | |
584892a6 | 12837 | macro_end (); |
6478892d TS |
12838 | |
12839 | demand_empty_rest_of_line (); | |
12840 | } | |
12841 | ||
12842 | static void | |
17a2f251 | 12843 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12844 | { |
12845 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
54f4ddb3 | 12846 | .cplocal is ignored. */ |
6478892d TS |
12847 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) |
12848 | { | |
12849 | s_ignore (0); | |
12850 | return; | |
12851 | } | |
12852 | ||
12853 | mips_gp_register = tc_get_register (0); | |
85b51719 | 12854 | demand_empty_rest_of_line (); |
6478892d TS |
12855 | } |
12856 | ||
252b5132 RH |
12857 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
12858 | offset from $sp. The offset is remembered, and after making a PIC | |
12859 | call $gp is restored from that location. */ | |
12860 | ||
12861 | static void | |
17a2f251 | 12862 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12863 | { |
12864 | expressionS ex; | |
252b5132 | 12865 | |
6478892d | 12866 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 12867 | .cprestore is ignored. */ |
6478892d | 12868 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
12869 | { |
12870 | s_ignore (0); | |
12871 | return; | |
12872 | } | |
12873 | ||
12874 | mips_cprestore_offset = get_absolute_expression (); | |
7a621144 | 12875 | mips_cprestore_valid = 1; |
252b5132 RH |
12876 | |
12877 | ex.X_op = O_constant; | |
12878 | ex.X_add_symbol = NULL; | |
12879 | ex.X_op_symbol = NULL; | |
12880 | ex.X_add_number = mips_cprestore_offset; | |
12881 | ||
584892a6 | 12882 | macro_start (); |
67c0d1eb RS |
12883 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
12884 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 12885 | macro_end (); |
252b5132 RH |
12886 | |
12887 | demand_empty_rest_of_line (); | |
12888 | } | |
12889 | ||
6478892d | 12890 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 12891 | was given in the preceding .cpsetup, it results in: |
6478892d | 12892 | ld $gp, offset($sp) |
76b3015f | 12893 | |
6478892d | 12894 | If a register $reg2 was given there, it results in: |
54f4ddb3 TS |
12895 | daddu $gp, $reg2, $0 */ |
12896 | ||
6478892d | 12897 | static void |
17a2f251 | 12898 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12899 | { |
12900 | expressionS ex; | |
6478892d TS |
12901 | |
12902 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
12903 | We also need NewABI support. */ | |
12904 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12905 | { | |
12906 | s_ignore (0); | |
12907 | return; | |
12908 | } | |
12909 | ||
584892a6 | 12910 | macro_start (); |
6478892d TS |
12911 | if (mips_cpreturn_register == -1) |
12912 | { | |
12913 | ex.X_op = O_constant; | |
12914 | ex.X_add_symbol = NULL; | |
12915 | ex.X_op_symbol = NULL; | |
12916 | ex.X_add_number = mips_cpreturn_offset; | |
12917 | ||
67c0d1eb | 12918 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
12919 | } |
12920 | else | |
67c0d1eb | 12921 | macro_build (NULL, "daddu", "d,v,t", mips_gp_register, |
17a2f251 | 12922 | mips_cpreturn_register, 0); |
584892a6 | 12923 | macro_end (); |
6478892d TS |
12924 | |
12925 | demand_empty_rest_of_line (); | |
12926 | } | |
12927 | ||
741d6ea8 JM |
12928 | /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate |
12929 | a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for | |
12930 | use in DWARF debug information. */ | |
12931 | ||
12932 | static void | |
12933 | s_dtprel_internal (size_t bytes) | |
12934 | { | |
12935 | expressionS ex; | |
12936 | char *p; | |
12937 | ||
12938 | expression (&ex); | |
12939 | ||
12940 | if (ex.X_op != O_symbol) | |
12941 | { | |
12942 | as_bad (_("Unsupported use of %s"), (bytes == 8 | |
12943 | ? ".dtpreldword" | |
12944 | : ".dtprelword")); | |
12945 | ignore_rest_of_line (); | |
12946 | } | |
12947 | ||
12948 | p = frag_more (bytes); | |
12949 | md_number_to_chars (p, 0, bytes); | |
12950 | fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, | |
12951 | (bytes == 8 | |
12952 | ? BFD_RELOC_MIPS_TLS_DTPREL64 | |
12953 | : BFD_RELOC_MIPS_TLS_DTPREL32)); | |
12954 | ||
12955 | demand_empty_rest_of_line (); | |
12956 | } | |
12957 | ||
12958 | /* Handle .dtprelword. */ | |
12959 | ||
12960 | static void | |
12961 | s_dtprelword (int ignore ATTRIBUTE_UNUSED) | |
12962 | { | |
12963 | s_dtprel_internal (4); | |
12964 | } | |
12965 | ||
12966 | /* Handle .dtpreldword. */ | |
12967 | ||
12968 | static void | |
12969 | s_dtpreldword (int ignore ATTRIBUTE_UNUSED) | |
12970 | { | |
12971 | s_dtprel_internal (8); | |
12972 | } | |
12973 | ||
6478892d TS |
12974 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC |
12975 | code. It sets the offset to use in gp_rel relocations. */ | |
12976 | ||
12977 | static void | |
17a2f251 | 12978 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12979 | { |
12980 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
12981 | We also need NewABI support. */ | |
12982 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12983 | { | |
12984 | s_ignore (0); | |
12985 | return; | |
12986 | } | |
12987 | ||
def2e0dd | 12988 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
12989 | |
12990 | demand_empty_rest_of_line (); | |
12991 | } | |
12992 | ||
252b5132 RH |
12993 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
12994 | code. It generates a 32 bit GP relative reloc. */ | |
12995 | ||
12996 | static void | |
17a2f251 | 12997 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 12998 | { |
a8dbcb85 TS |
12999 | segment_info_type *si; |
13000 | struct insn_label_list *l; | |
252b5132 RH |
13001 | symbolS *label; |
13002 | expressionS ex; | |
13003 | char *p; | |
13004 | ||
13005 | /* When not generating PIC code, this is treated as .word. */ | |
13006 | if (mips_pic != SVR4_PIC) | |
13007 | { | |
13008 | s_cons (2); | |
13009 | return; | |
13010 | } | |
13011 | ||
a8dbcb85 TS |
13012 | si = seg_info (now_seg); |
13013 | l = si->label_list; | |
13014 | label = l != NULL ? l->label : NULL; | |
7d10b47d | 13015 | mips_emit_delays (); |
252b5132 RH |
13016 | if (auto_align) |
13017 | mips_align (2, 0, label); | |
13018 | mips_clear_insn_labels (); | |
13019 | ||
13020 | expression (&ex); | |
13021 | ||
13022 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
13023 | { | |
13024 | as_bad (_("Unsupported use of .gpword")); | |
13025 | ignore_rest_of_line (); | |
13026 | } | |
13027 | ||
13028 | p = frag_more (4); | |
17a2f251 | 13029 | md_number_to_chars (p, 0, 4); |
b34976b6 | 13030 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 13031 | BFD_RELOC_GPREL32); |
252b5132 RH |
13032 | |
13033 | demand_empty_rest_of_line (); | |
13034 | } | |
13035 | ||
10181a0d | 13036 | static void |
17a2f251 | 13037 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d | 13038 | { |
a8dbcb85 TS |
13039 | segment_info_type *si; |
13040 | struct insn_label_list *l; | |
10181a0d AO |
13041 | symbolS *label; |
13042 | expressionS ex; | |
13043 | char *p; | |
13044 | ||
13045 | /* When not generating PIC code, this is treated as .dword. */ | |
13046 | if (mips_pic != SVR4_PIC) | |
13047 | { | |
13048 | s_cons (3); | |
13049 | return; | |
13050 | } | |
13051 | ||
a8dbcb85 TS |
13052 | si = seg_info (now_seg); |
13053 | l = si->label_list; | |
13054 | label = l != NULL ? l->label : NULL; | |
7d10b47d | 13055 | mips_emit_delays (); |
10181a0d AO |
13056 | if (auto_align) |
13057 | mips_align (3, 0, label); | |
13058 | mips_clear_insn_labels (); | |
13059 | ||
13060 | expression (&ex); | |
13061 | ||
13062 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
13063 | { | |
13064 | as_bad (_("Unsupported use of .gpdword")); | |
13065 | ignore_rest_of_line (); | |
13066 | } | |
13067 | ||
13068 | p = frag_more (8); | |
17a2f251 | 13069 | md_number_to_chars (p, 0, 8); |
a105a300 | 13070 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 13071 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
13072 | |
13073 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
13074 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
13075 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
13076 | |
13077 | demand_empty_rest_of_line (); | |
13078 | } | |
13079 | ||
252b5132 RH |
13080 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
13081 | tables in SVR4 PIC code. */ | |
13082 | ||
13083 | static void | |
17a2f251 | 13084 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13085 | { |
252b5132 RH |
13086 | int reg; |
13087 | ||
10181a0d AO |
13088 | /* This is ignored when not generating SVR4 PIC code. */ |
13089 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
13090 | { |
13091 | s_ignore (0); | |
13092 | return; | |
13093 | } | |
13094 | ||
13095 | /* Add $gp to the register named as an argument. */ | |
584892a6 | 13096 | macro_start (); |
252b5132 | 13097 | reg = tc_get_register (0); |
67c0d1eb | 13098 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 13099 | macro_end (); |
252b5132 | 13100 | |
bdaaa2e1 | 13101 | demand_empty_rest_of_line (); |
252b5132 RH |
13102 | } |
13103 | ||
13104 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
13105 | mips16 mode. This permits the linker to handle them specially, | |
13106 | such as generating jalx instructions when needed. We also make | |
13107 | them odd for the duration of the assembly, in order to generate the | |
13108 | right sort of code. We will make them even in the adjust_symtab | |
13109 | routine, while leaving them marked. This is convenient for the | |
13110 | debugger and the disassembler. The linker knows to make them odd | |
13111 | again. */ | |
13112 | ||
13113 | static void | |
17a2f251 | 13114 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13115 | { |
f9419b05 | 13116 | mips16_mark_labels (); |
252b5132 RH |
13117 | |
13118 | demand_empty_rest_of_line (); | |
13119 | } | |
13120 | ||
13121 | /* Handle a .stabn directive. We need these in order to mark a label | |
13122 | as being a mips16 text label correctly. Sometimes the compiler | |
13123 | will emit a label, followed by a .stabn, and then switch sections. | |
13124 | If the label and .stabn are in mips16 mode, then the label is | |
13125 | really a mips16 text label. */ | |
13126 | ||
13127 | static void | |
17a2f251 | 13128 | s_mips_stab (int type) |
252b5132 | 13129 | { |
f9419b05 | 13130 | if (type == 'n') |
252b5132 RH |
13131 | mips16_mark_labels (); |
13132 | ||
13133 | s_stab (type); | |
13134 | } | |
13135 | ||
54f4ddb3 | 13136 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */ |
252b5132 RH |
13137 | |
13138 | static void | |
17a2f251 | 13139 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
13140 | { |
13141 | char *name; | |
13142 | int c; | |
13143 | symbolS *symbolP; | |
13144 | expressionS exp; | |
13145 | ||
13146 | name = input_line_pointer; | |
13147 | c = get_symbol_end (); | |
13148 | symbolP = symbol_find_or_make (name); | |
13149 | S_SET_WEAK (symbolP); | |
13150 | *input_line_pointer = c; | |
13151 | ||
13152 | SKIP_WHITESPACE (); | |
13153 | ||
13154 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
13155 | { | |
13156 | if (S_IS_DEFINED (symbolP)) | |
13157 | { | |
956cd1d6 | 13158 | as_bad ("ignoring attempt to redefine symbol %s", |
252b5132 RH |
13159 | S_GET_NAME (symbolP)); |
13160 | ignore_rest_of_line (); | |
13161 | return; | |
13162 | } | |
bdaaa2e1 | 13163 | |
252b5132 RH |
13164 | if (*input_line_pointer == ',') |
13165 | { | |
13166 | ++input_line_pointer; | |
13167 | SKIP_WHITESPACE (); | |
13168 | } | |
bdaaa2e1 | 13169 | |
252b5132 RH |
13170 | expression (&exp); |
13171 | if (exp.X_op != O_symbol) | |
13172 | { | |
13173 | as_bad ("bad .weakext directive"); | |
98d3f06f | 13174 | ignore_rest_of_line (); |
252b5132 RH |
13175 | return; |
13176 | } | |
49309057 | 13177 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
13178 | } |
13179 | ||
13180 | demand_empty_rest_of_line (); | |
13181 | } | |
13182 | ||
13183 | /* Parse a register string into a number. Called from the ECOFF code | |
13184 | to parse .frame. The argument is non-zero if this is the frame | |
13185 | register, so that we can record it in mips_frame_reg. */ | |
13186 | ||
13187 | int | |
17a2f251 | 13188 | tc_get_register (int frame) |
252b5132 | 13189 | { |
707bfff6 | 13190 | unsigned int reg; |
252b5132 RH |
13191 | |
13192 | SKIP_WHITESPACE (); | |
707bfff6 TS |
13193 | if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®)) |
13194 | reg = 0; | |
252b5132 | 13195 | if (frame) |
7a621144 DJ |
13196 | { |
13197 | mips_frame_reg = reg != 0 ? reg : SP; | |
13198 | mips_frame_reg_valid = 1; | |
13199 | mips_cprestore_valid = 0; | |
13200 | } | |
252b5132 RH |
13201 | return reg; |
13202 | } | |
13203 | ||
13204 | valueT | |
17a2f251 | 13205 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
13206 | { |
13207 | int align = bfd_get_section_alignment (stdoutput, seg); | |
13208 | ||
b4c71f56 TS |
13209 | if (IS_ELF) |
13210 | { | |
13211 | /* We don't need to align ELF sections to the full alignment. | |
13212 | However, Irix 5 may prefer that we align them at least to a 16 | |
13213 | byte boundary. We don't bother to align the sections if we | |
13214 | are targeted for an embedded system. */ | |
13215 | if (strcmp (TARGET_OS, "elf") == 0) | |
13216 | return addr; | |
13217 | if (align > 4) | |
13218 | align = 4; | |
13219 | } | |
252b5132 RH |
13220 | |
13221 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
13222 | } | |
13223 | ||
13224 | /* Utility routine, called from above as well. If called while the | |
13225 | input file is still being read, it's only an approximation. (For | |
13226 | example, a symbol may later become defined which appeared to be | |
13227 | undefined earlier.) */ | |
13228 | ||
13229 | static int | |
17a2f251 | 13230 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
13231 | { |
13232 | if (sym == 0) | |
13233 | return 0; | |
13234 | ||
4d0d148d | 13235 | if (g_switch_value > 0) |
252b5132 RH |
13236 | { |
13237 | const char *symname; | |
13238 | int change; | |
13239 | ||
c9914766 | 13240 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
13241 | register. It can be if it is smaller than the -G size or if |
13242 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 13243 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
13244 | they can. */ |
13245 | symname = S_GET_NAME (sym); | |
13246 | if (symname != (const char *) NULL | |
13247 | && (strcmp (symname, "eprol") == 0 | |
13248 | || strcmp (symname, "etext") == 0 | |
13249 | || strcmp (symname, "_gp") == 0 | |
13250 | || strcmp (symname, "edata") == 0 | |
13251 | || strcmp (symname, "_fbss") == 0 | |
13252 | || strcmp (symname, "_fdata") == 0 | |
13253 | || strcmp (symname, "_ftext") == 0 | |
13254 | || strcmp (symname, "end") == 0 | |
13255 | || strcmp (symname, "_gp_disp") == 0)) | |
13256 | change = 1; | |
13257 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
13258 | && (0 | |
13259 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
13260 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
13261 | && (symbol_get_obj (sym)->ecoff_extern_size | |
13262 | <= g_switch_value)) | |
252b5132 RH |
13263 | #endif |
13264 | /* We must defer this decision until after the whole | |
13265 | file has been read, since there might be a .extern | |
13266 | after the first use of this symbol. */ | |
13267 | || (before_relaxing | |
13268 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 13269 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
13270 | #endif |
13271 | && S_GET_VALUE (sym) == 0) | |
13272 | || (S_GET_VALUE (sym) != 0 | |
13273 | && S_GET_VALUE (sym) <= g_switch_value))) | |
13274 | change = 0; | |
13275 | else | |
13276 | { | |
13277 | const char *segname; | |
13278 | ||
13279 | segname = segment_name (S_GET_SEGMENT (sym)); | |
13280 | assert (strcmp (segname, ".lit8") != 0 | |
13281 | && strcmp (segname, ".lit4") != 0); | |
13282 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
13283 | && strcmp (segname, ".sbss") != 0 |
13284 | && strncmp (segname, ".sdata.", 7) != 0 | |
d4dc2f22 TS |
13285 | && strncmp (segname, ".sbss.", 6) != 0 |
13286 | && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0 | |
fba2b7f9 | 13287 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); |
252b5132 RH |
13288 | } |
13289 | return change; | |
13290 | } | |
13291 | else | |
c9914766 | 13292 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
13293 | return 1; |
13294 | } | |
13295 | ||
5919d012 RS |
13296 | |
13297 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
13298 | ||
13299 | static bfd_boolean | |
17a2f251 | 13300 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
13301 | { |
13302 | asection *symsec; | |
5919d012 RS |
13303 | |
13304 | /* Handle the case of a symbol equated to another symbol. */ | |
13305 | while (symbol_equated_reloc_p (sym)) | |
13306 | { | |
13307 | symbolS *n; | |
13308 | ||
5f0fe04b | 13309 | /* It's possible to get a loop here in a badly written program. */ |
5919d012 RS |
13310 | n = symbol_get_value_expression (sym)->X_add_symbol; |
13311 | if (n == sym) | |
13312 | break; | |
13313 | sym = n; | |
13314 | } | |
13315 | ||
df1f3cda DD |
13316 | if (symbol_section_p (sym)) |
13317 | return TRUE; | |
13318 | ||
5919d012 RS |
13319 | symsec = S_GET_SEGMENT (sym); |
13320 | ||
5919d012 RS |
13321 | /* This must duplicate the test in adjust_reloc_syms. */ |
13322 | return (symsec != &bfd_und_section | |
13323 | && symsec != &bfd_abs_section | |
5f0fe04b TS |
13324 | && !bfd_is_com_section (symsec) |
13325 | && !s_is_linkonce (sym, segtype) | |
5919d012 RS |
13326 | #ifdef OBJ_ELF |
13327 | /* A global or weak symbol is treated as external. */ | |
f43abd2b | 13328 | && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym))) |
5919d012 RS |
13329 | #endif |
13330 | ); | |
13331 | } | |
13332 | ||
13333 | ||
252b5132 RH |
13334 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
13335 | extended opcode. SEC is the section the frag is in. */ | |
13336 | ||
13337 | static int | |
17a2f251 | 13338 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
13339 | { |
13340 | int type; | |
3994f87e | 13341 | const struct mips16_immed_operand *op; |
252b5132 RH |
13342 | offsetT val; |
13343 | int mintiny, maxtiny; | |
13344 | segT symsec; | |
98aa84af | 13345 | fragS *sym_frag; |
252b5132 RH |
13346 | |
13347 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
13348 | return 0; | |
13349 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
13350 | return 1; | |
13351 | ||
13352 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
13353 | op = mips16_immed_operands; | |
13354 | while (op->type != type) | |
13355 | { | |
13356 | ++op; | |
13357 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
13358 | } | |
13359 | ||
13360 | if (op->unsp) | |
13361 | { | |
13362 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
13363 | { | |
13364 | mintiny = 1; | |
13365 | maxtiny = 1 << op->nbits; | |
13366 | } | |
13367 | else | |
13368 | { | |
13369 | mintiny = 0; | |
13370 | maxtiny = (1 << op->nbits) - 1; | |
13371 | } | |
13372 | } | |
13373 | else | |
13374 | { | |
13375 | mintiny = - (1 << (op->nbits - 1)); | |
13376 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
13377 | } | |
13378 | ||
98aa84af | 13379 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 13380 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 13381 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
13382 | |
13383 | if (op->pcrel) | |
13384 | { | |
13385 | addressT addr; | |
13386 | ||
13387 | /* We won't have the section when we are called from | |
13388 | mips_relax_frag. However, we will always have been called | |
13389 | from md_estimate_size_before_relax first. If this is a | |
13390 | branch to a different section, we mark it as such. If SEC is | |
13391 | NULL, and the frag is not marked, then it must be a branch to | |
13392 | the same section. */ | |
13393 | if (sec == NULL) | |
13394 | { | |
13395 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
13396 | return 1; | |
13397 | } | |
13398 | else | |
13399 | { | |
98aa84af | 13400 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
13401 | if (symsec != sec) |
13402 | { | |
13403 | fragp->fr_subtype = | |
13404 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
13405 | ||
13406 | /* FIXME: We should support this, and let the linker | |
13407 | catch branches and loads that are out of range. */ | |
13408 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
13409 | _("unsupported PC relative reference to different section")); | |
13410 | ||
13411 | return 1; | |
13412 | } | |
98aa84af AM |
13413 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
13414 | /* Assume non-extended on the first relaxation pass. | |
13415 | The address we have calculated will be bogus if this is | |
13416 | a forward branch to another frag, as the forward frag | |
13417 | will have fr_address == 0. */ | |
13418 | return 0; | |
252b5132 RH |
13419 | } |
13420 | ||
13421 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
13422 | the same section. If the relax_marker of the symbol fragment |
13423 | differs from the relax_marker of this fragment, we have not | |
13424 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
13425 | in STRETCH in order to get a better estimate of the address. |
13426 | This particularly matters because of the shift bits. */ | |
13427 | if (stretch != 0 | |
98aa84af | 13428 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
13429 | { |
13430 | fragS *f; | |
13431 | ||
13432 | /* Adjust stretch for any alignment frag. Note that if have | |
13433 | been expanding the earlier code, the symbol may be | |
13434 | defined in what appears to be an earlier frag. FIXME: | |
13435 | This doesn't handle the fr_subtype field, which specifies | |
13436 | a maximum number of bytes to skip when doing an | |
13437 | alignment. */ | |
98aa84af | 13438 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
13439 | { |
13440 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
13441 | { | |
13442 | if (stretch < 0) | |
13443 | stretch = - ((- stretch) | |
13444 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
13445 | else | |
13446 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
13447 | if (stretch == 0) | |
13448 | break; | |
13449 | } | |
13450 | } | |
13451 | if (f != NULL) | |
13452 | val += stretch; | |
13453 | } | |
13454 | ||
13455 | addr = fragp->fr_address + fragp->fr_fix; | |
13456 | ||
13457 | /* The base address rules are complicated. The base address of | |
13458 | a branch is the following instruction. The base address of a | |
13459 | PC relative load or add is the instruction itself, but if it | |
13460 | is in a delay slot (in which case it can not be extended) use | |
13461 | the address of the instruction whose delay slot it is in. */ | |
13462 | if (type == 'p' || type == 'q') | |
13463 | { | |
13464 | addr += 2; | |
13465 | ||
13466 | /* If we are currently assuming that this frag should be | |
13467 | extended, then, the current address is two bytes | |
bdaaa2e1 | 13468 | higher. */ |
252b5132 RH |
13469 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
13470 | addr += 2; | |
13471 | ||
13472 | /* Ignore the low bit in the target, since it will be set | |
13473 | for a text label. */ | |
13474 | if ((val & 1) != 0) | |
13475 | --val; | |
13476 | } | |
13477 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
13478 | addr -= 4; | |
13479 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
13480 | addr -= 2; | |
13481 | ||
13482 | val -= addr & ~ ((1 << op->shift) - 1); | |
13483 | ||
13484 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
13485 | if (type == 'p' || type == 'q') | |
13486 | val /= 2; | |
13487 | ||
13488 | /* If any of the shifted bits are set, we must use an extended | |
13489 | opcode. If the address depends on the size of this | |
13490 | instruction, this can lead to a loop, so we arrange to always | |
13491 | use an extended opcode. We only check this when we are in | |
13492 | the main relaxation loop, when SEC is NULL. */ | |
13493 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
13494 | { | |
13495 | fragp->fr_subtype = | |
13496 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
13497 | return 1; | |
13498 | } | |
13499 | ||
13500 | /* If we are about to mark a frag as extended because the value | |
13501 | is precisely maxtiny + 1, then there is a chance of an | |
13502 | infinite loop as in the following code: | |
13503 | la $4,foo | |
13504 | .skip 1020 | |
13505 | .align 2 | |
13506 | foo: | |
13507 | In this case when the la is extended, foo is 0x3fc bytes | |
13508 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
13509 | the la must be extended. To avoid this loop, we mark the | |
13510 | frag as extended if it was small, and is about to become | |
13511 | extended with a value of maxtiny + 1. */ | |
13512 | if (val == ((maxtiny + 1) << op->shift) | |
13513 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
13514 | && sec == NULL) | |
13515 | { | |
13516 | fragp->fr_subtype = | |
13517 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
13518 | return 1; | |
13519 | } | |
13520 | } | |
13521 | else if (symsec != absolute_section && sec != NULL) | |
13522 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
13523 | ||
13524 | if ((val & ((1 << op->shift) - 1)) != 0 | |
13525 | || val < (mintiny << op->shift) | |
13526 | || val > (maxtiny << op->shift)) | |
13527 | return 1; | |
13528 | else | |
13529 | return 0; | |
13530 | } | |
13531 | ||
4a6a3df4 AO |
13532 | /* Compute the length of a branch sequence, and adjust the |
13533 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
13534 | worst-case length is computed, with UPDATE being used to indicate | |
13535 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
13536 | branch is to be computed. */ | |
13537 | static int | |
17a2f251 | 13538 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 13539 | { |
b34976b6 | 13540 | bfd_boolean toofar; |
4a6a3df4 AO |
13541 | int length; |
13542 | ||
13543 | if (fragp | |
13544 | && S_IS_DEFINED (fragp->fr_symbol) | |
13545 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
13546 | { | |
13547 | addressT addr; | |
13548 | offsetT val; | |
13549 | ||
13550 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
13551 | ||
13552 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
13553 | ||
13554 | val -= addr; | |
13555 | ||
13556 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
13557 | } | |
13558 | else if (fragp) | |
13559 | /* If the symbol is not defined or it's in a different segment, | |
13560 | assume the user knows what's going on and emit a short | |
13561 | branch. */ | |
b34976b6 | 13562 | toofar = FALSE; |
4a6a3df4 | 13563 | else |
b34976b6 | 13564 | toofar = TRUE; |
4a6a3df4 AO |
13565 | |
13566 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
13567 | fragp->fr_subtype | |
af6ae2ad | 13568 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype), |
4a6a3df4 AO |
13569 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
13570 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
13571 | toofar); | |
13572 | ||
13573 | length = 4; | |
13574 | if (toofar) | |
13575 | { | |
13576 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
13577 | length += 8; | |
13578 | ||
13579 | if (mips_pic != NO_PIC) | |
13580 | { | |
13581 | /* Additional space for PIC loading of target address. */ | |
13582 | length += 8; | |
13583 | if (mips_opts.isa == ISA_MIPS1) | |
13584 | /* Additional space for $at-stabilizing nop. */ | |
13585 | length += 4; | |
13586 | } | |
13587 | ||
13588 | /* If branch is conditional. */ | |
13589 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
13590 | length += 8; | |
13591 | } | |
b34976b6 | 13592 | |
4a6a3df4 AO |
13593 | return length; |
13594 | } | |
13595 | ||
252b5132 RH |
13596 | /* Estimate the size of a frag before relaxing. Unless this is the |
13597 | mips16, we are not really relaxing here, and the final size is | |
13598 | encoded in the subtype information. For the mips16, we have to | |
13599 | decide whether we are using an extended opcode or not. */ | |
13600 | ||
252b5132 | 13601 | int |
17a2f251 | 13602 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 13603 | { |
5919d012 | 13604 | int change; |
252b5132 | 13605 | |
4a6a3df4 AO |
13606 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13607 | { | |
13608 | ||
b34976b6 AM |
13609 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
13610 | ||
4a6a3df4 AO |
13611 | return fragp->fr_var; |
13612 | } | |
13613 | ||
252b5132 | 13614 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
13615 | /* We don't want to modify the EXTENDED bit here; it might get us |
13616 | into infinite loops. We change it only in mips_relax_frag(). */ | |
13617 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 RH |
13618 | |
13619 | if (mips_pic == NO_PIC) | |
5919d012 | 13620 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 13621 | else if (mips_pic == SVR4_PIC) |
5919d012 | 13622 | change = pic_need_relax (fragp->fr_symbol, segtype); |
0a44bf69 RS |
13623 | else if (mips_pic == VXWORKS_PIC) |
13624 | /* For vxworks, GOT16 relocations never have a corresponding LO16. */ | |
13625 | change = 0; | |
252b5132 RH |
13626 | else |
13627 | abort (); | |
13628 | ||
13629 | if (change) | |
13630 | { | |
4d7206a2 | 13631 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 13632 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 13633 | } |
4d7206a2 RS |
13634 | else |
13635 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
13636 | } |
13637 | ||
13638 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 13639 | should be converted into a reloc against a section. */ |
252b5132 RH |
13640 | |
13641 | int | |
17a2f251 | 13642 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 13643 | { |
252b5132 RH |
13644 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
13645 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
13646 | return 0; | |
a161fe53 | 13647 | |
252b5132 RH |
13648 | if (fixp->fx_addsy == NULL) |
13649 | return 1; | |
a161fe53 | 13650 | |
de7e6852 RS |
13651 | /* If symbol SYM is in a mergeable section, relocations of the form |
13652 | SYM + 0 can usually be made section-relative. The mergeable data | |
13653 | is then identified by the section offset rather than by the symbol. | |
13654 | ||
13655 | However, if we're generating REL LO16 relocations, the offset is split | |
13656 | between the LO16 and parterning high part relocation. The linker will | |
13657 | need to recalculate the complete offset in order to correctly identify | |
13658 | the merge data. | |
13659 | ||
13660 | The linker has traditionally not looked for the parterning high part | |
13661 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be | |
13662 | placed anywhere. Rather than break backwards compatibility by changing | |
13663 | this, it seems better not to force the issue, and instead keep the | |
13664 | original symbol. This will work with either linker behavior. */ | |
704803a9 MR |
13665 | if ((fixp->fx_r_type == BFD_RELOC_LO16 |
13666 | || fixp->fx_r_type == BFD_RELOC_MIPS16_LO16 | |
13667 | || reloc_needs_lo_p (fixp->fx_r_type)) | |
de7e6852 RS |
13668 | && HAVE_IN_PLACE_ADDENDS |
13669 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
13670 | return 0; | |
13671 | ||
252b5132 | 13672 | #ifdef OBJ_ELF |
b314ec0e RS |
13673 | /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve |
13674 | to a floating-point stub. The same is true for non-R_MIPS16_26 | |
13675 | relocations against MIPS16 functions; in this case, the stub becomes | |
13676 | the function's canonical address. | |
13677 | ||
13678 | Floating-point stubs are stored in unique .mips16.call.* or | |
13679 | .mips16.fn.* sections. If a stub T for function F is in section S, | |
13680 | the first relocation in section S must be against F; this is how the | |
13681 | linker determines the target function. All relocations that might | |
13682 | resolve to T must also be against F. We therefore have the following | |
13683 | restrictions, which are given in an intentionally-redundant way: | |
13684 | ||
13685 | 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16 | |
13686 | symbols. | |
13687 | ||
13688 | 2. We cannot reduce a stub's relocations against non-MIPS16 symbols | |
13689 | if that stub might be used. | |
13690 | ||
13691 | 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16 | |
13692 | symbols. | |
13693 | ||
13694 | 4. We cannot reduce a stub's relocations against MIPS16 symbols if | |
13695 | that stub might be used. | |
13696 | ||
13697 | There is a further restriction: | |
13698 | ||
13699 | 5. We cannot reduce R_MIPS16_26 relocations against MIPS16 symbols | |
13700 | on targets with in-place addends; the relocation field cannot | |
13701 | encode the low bit. | |
13702 | ||
13703 | For simplicity, we deal with (3)-(5) by not reducing _any_ relocation | |
13704 | against a MIPS16 symbol. | |
13705 | ||
13706 | We deal with (1)-(2) by saying that, if there's a R_MIPS16_26 | |
13707 | relocation against some symbol R, no relocation against R may be | |
13708 | reduced. (Note that this deals with (2) as well as (1) because | |
13709 | relocations against global symbols will never be reduced on ELF | |
13710 | targets.) This approach is a little simpler than trying to detect | |
13711 | stub sections, and gives the "all or nothing" per-symbol consistency | |
13712 | that we have for MIPS16 symbols. */ | |
f43abd2b | 13713 | if (IS_ELF |
b314ec0e RS |
13714 | && fixp->fx_subsy == NULL |
13715 | && (S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 | |
13716 | || *symbol_get_tc (fixp->fx_addsy))) | |
252b5132 RH |
13717 | return 0; |
13718 | #endif | |
a161fe53 | 13719 | |
252b5132 RH |
13720 | return 1; |
13721 | } | |
13722 | ||
13723 | /* Translate internal representation of relocation info to BFD target | |
13724 | format. */ | |
13725 | ||
13726 | arelent ** | |
17a2f251 | 13727 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
13728 | { |
13729 | static arelent *retval[4]; | |
13730 | arelent *reloc; | |
13731 | bfd_reloc_code_real_type code; | |
13732 | ||
4b0cff4e TS |
13733 | memset (retval, 0, sizeof(retval)); |
13734 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
13735 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
13736 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
13737 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
13738 | ||
bad36eac DJ |
13739 | if (fixp->fx_pcrel) |
13740 | { | |
13741 | assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2); | |
13742 | ||
13743 | /* At this point, fx_addnumber is "symbol offset - pcrel address". | |
13744 | Relocations want only the symbol offset. */ | |
13745 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
f43abd2b | 13746 | if (!IS_ELF) |
bad36eac DJ |
13747 | { |
13748 | /* A gruesome hack which is a result of the gruesome gas | |
13749 | reloc handling. What's worse, for COFF (as opposed to | |
13750 | ECOFF), we might need yet another copy of reloc->address. | |
13751 | See bfd_install_relocation. */ | |
13752 | reloc->addend += reloc->address; | |
13753 | } | |
13754 | } | |
13755 | else | |
13756 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 13757 | |
438c16b8 TS |
13758 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
13759 | entry to be used in the relocation's section offset. */ | |
13760 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
13761 | { |
13762 | reloc->address = reloc->addend; | |
13763 | reloc->addend = 0; | |
13764 | } | |
13765 | ||
252b5132 | 13766 | code = fixp->fx_r_type; |
252b5132 | 13767 | |
bad36eac | 13768 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
252b5132 RH |
13769 | if (reloc->howto == NULL) |
13770 | { | |
13771 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
13772 | _("Can not represent %s relocation in this object file format"), | |
13773 | bfd_get_reloc_code_name (code)); | |
13774 | retval[0] = NULL; | |
13775 | } | |
13776 | ||
13777 | return retval; | |
13778 | } | |
13779 | ||
13780 | /* Relax a machine dependent frag. This returns the amount by which | |
13781 | the current size of the frag should change. */ | |
13782 | ||
13783 | int | |
17a2f251 | 13784 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 13785 | { |
4a6a3df4 AO |
13786 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13787 | { | |
13788 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
13789 | |
13790 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
13791 | |
13792 | return fragp->fr_var - old_var; | |
13793 | } | |
13794 | ||
252b5132 RH |
13795 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
13796 | return 0; | |
13797 | ||
c4e7957c | 13798 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
13799 | { |
13800 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13801 | return 0; | |
13802 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
13803 | return 2; | |
13804 | } | |
13805 | else | |
13806 | { | |
13807 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13808 | return 0; | |
13809 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
13810 | return -2; | |
13811 | } | |
13812 | ||
13813 | return 0; | |
13814 | } | |
13815 | ||
13816 | /* Convert a machine dependent frag. */ | |
13817 | ||
13818 | void | |
17a2f251 | 13819 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 13820 | { |
4a6a3df4 AO |
13821 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13822 | { | |
13823 | bfd_byte *buf; | |
13824 | unsigned long insn; | |
13825 | expressionS exp; | |
13826 | fixS *fixp; | |
b34976b6 | 13827 | |
4a6a3df4 AO |
13828 | buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; |
13829 | ||
13830 | if (target_big_endian) | |
13831 | insn = bfd_getb32 (buf); | |
13832 | else | |
13833 | insn = bfd_getl32 (buf); | |
b34976b6 | 13834 | |
4a6a3df4 AO |
13835 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
13836 | { | |
13837 | /* We generate a fixup instead of applying it right now | |
13838 | because, if there are linker relaxations, we're going to | |
13839 | need the relocations. */ | |
13840 | exp.X_op = O_symbol; | |
13841 | exp.X_add_symbol = fragp->fr_symbol; | |
13842 | exp.X_add_number = fragp->fr_offset; | |
13843 | ||
13844 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 13845 | 4, &exp, TRUE, BFD_RELOC_16_PCREL_S2); |
4a6a3df4 AO |
13846 | fixp->fx_file = fragp->fr_file; |
13847 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 13848 | |
2132e3a3 | 13849 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13850 | buf += 4; |
13851 | } | |
13852 | else | |
13853 | { | |
13854 | int i; | |
13855 | ||
13856 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
13857 | _("relaxed out-of-range branch into a jump")); | |
13858 | ||
13859 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
13860 | goto uncond; | |
13861 | ||
13862 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13863 | { | |
13864 | /* Reverse the branch. */ | |
13865 | switch ((insn >> 28) & 0xf) | |
13866 | { | |
13867 | case 4: | |
13868 | /* bc[0-3][tf]l? and bc1any[24][ft] instructions can | |
13869 | have the condition reversed by tweaking a single | |
13870 | bit, and their opcodes all have 0x4???????. */ | |
13871 | assert ((insn & 0xf1000000) == 0x41000000); | |
13872 | insn ^= 0x00010000; | |
13873 | break; | |
13874 | ||
13875 | case 0: | |
13876 | /* bltz 0x04000000 bgez 0x04010000 | |
54f4ddb3 | 13877 | bltzal 0x04100000 bgezal 0x04110000 */ |
4a6a3df4 AO |
13878 | assert ((insn & 0xfc0e0000) == 0x04000000); |
13879 | insn ^= 0x00010000; | |
13880 | break; | |
b34976b6 | 13881 | |
4a6a3df4 AO |
13882 | case 1: |
13883 | /* beq 0x10000000 bne 0x14000000 | |
54f4ddb3 | 13884 | blez 0x18000000 bgtz 0x1c000000 */ |
4a6a3df4 AO |
13885 | insn ^= 0x04000000; |
13886 | break; | |
13887 | ||
13888 | default: | |
13889 | abort (); | |
13890 | } | |
13891 | } | |
13892 | ||
13893 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
13894 | { | |
13895 | /* Clear the and-link bit. */ | |
13896 | assert ((insn & 0xfc1c0000) == 0x04100000); | |
13897 | ||
54f4ddb3 TS |
13898 | /* bltzal 0x04100000 bgezal 0x04110000 |
13899 | bltzall 0x04120000 bgezall 0x04130000 */ | |
4a6a3df4 AO |
13900 | insn &= ~0x00100000; |
13901 | } | |
13902 | ||
13903 | /* Branch over the branch (if the branch was likely) or the | |
13904 | full jump (not likely case). Compute the offset from the | |
13905 | current instruction to branch to. */ | |
13906 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13907 | i = 16; | |
13908 | else | |
13909 | { | |
13910 | /* How many bytes in instructions we've already emitted? */ | |
13911 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
13912 | /* How many bytes in instructions from here to the end? */ | |
13913 | i = fragp->fr_var - i; | |
13914 | } | |
13915 | /* Convert to instruction count. */ | |
13916 | i >>= 2; | |
13917 | /* Branch counts from the next instruction. */ | |
b34976b6 | 13918 | i--; |
4a6a3df4 AO |
13919 | insn |= i; |
13920 | /* Branch over the jump. */ | |
2132e3a3 | 13921 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13922 | buf += 4; |
13923 | ||
54f4ddb3 | 13924 | /* nop */ |
2132e3a3 | 13925 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
13926 | buf += 4; |
13927 | ||
13928 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13929 | { | |
13930 | /* beql $0, $0, 2f */ | |
13931 | insn = 0x50000000; | |
13932 | /* Compute the PC offset from the current instruction to | |
13933 | the end of the variable frag. */ | |
13934 | /* How many bytes in instructions we've already emitted? */ | |
13935 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
13936 | /* How many bytes in instructions from here to the end? */ | |
13937 | i = fragp->fr_var - i; | |
13938 | /* Convert to instruction count. */ | |
13939 | i >>= 2; | |
13940 | /* Don't decrement i, because we want to branch over the | |
13941 | delay slot. */ | |
13942 | ||
13943 | insn |= i; | |
2132e3a3 | 13944 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13945 | buf += 4; |
13946 | ||
2132e3a3 | 13947 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
13948 | buf += 4; |
13949 | } | |
13950 | ||
13951 | uncond: | |
13952 | if (mips_pic == NO_PIC) | |
13953 | { | |
13954 | /* j or jal. */ | |
13955 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
13956 | ? 0x0c000000 : 0x08000000); | |
13957 | exp.X_op = O_symbol; | |
13958 | exp.X_add_symbol = fragp->fr_symbol; | |
13959 | exp.X_add_number = fragp->fr_offset; | |
13960 | ||
13961 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 13962 | 4, &exp, FALSE, BFD_RELOC_MIPS_JMP); |
4a6a3df4 AO |
13963 | fixp->fx_file = fragp->fr_file; |
13964 | fixp->fx_line = fragp->fr_line; | |
13965 | ||
2132e3a3 | 13966 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13967 | buf += 4; |
13968 | } | |
13969 | else | |
13970 | { | |
13971 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ | |
13972 | insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000; | |
13973 | exp.X_op = O_symbol; | |
13974 | exp.X_add_symbol = fragp->fr_symbol; | |
13975 | exp.X_add_number = fragp->fr_offset; | |
13976 | ||
13977 | if (fragp->fr_offset) | |
13978 | { | |
13979 | exp.X_add_symbol = make_expr_symbol (&exp); | |
13980 | exp.X_add_number = 0; | |
13981 | } | |
13982 | ||
13983 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 13984 | 4, &exp, FALSE, BFD_RELOC_MIPS_GOT16); |
4a6a3df4 AO |
13985 | fixp->fx_file = fragp->fr_file; |
13986 | fixp->fx_line = fragp->fr_line; | |
13987 | ||
2132e3a3 | 13988 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 | 13989 | buf += 4; |
b34976b6 | 13990 | |
4a6a3df4 AO |
13991 | if (mips_opts.isa == ISA_MIPS1) |
13992 | { | |
13993 | /* nop */ | |
2132e3a3 | 13994 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
13995 | buf += 4; |
13996 | } | |
13997 | ||
13998 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
13999 | insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000; | |
14000 | ||
14001 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 14002 | 4, &exp, FALSE, BFD_RELOC_LO16); |
4a6a3df4 AO |
14003 | fixp->fx_file = fragp->fr_file; |
14004 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 14005 | |
2132e3a3 | 14006 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14007 | buf += 4; |
14008 | ||
14009 | /* j(al)r $at. */ | |
14010 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
14011 | insn = 0x0020f809; | |
14012 | else | |
14013 | insn = 0x00200008; | |
14014 | ||
2132e3a3 | 14015 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
14016 | buf += 4; |
14017 | } | |
14018 | } | |
14019 | ||
14020 | assert (buf == (bfd_byte *)fragp->fr_literal | |
14021 | + fragp->fr_fix + fragp->fr_var); | |
14022 | ||
14023 | fragp->fr_fix += fragp->fr_var; | |
14024 | ||
14025 | return; | |
14026 | } | |
14027 | ||
252b5132 RH |
14028 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
14029 | { | |
14030 | int type; | |
3994f87e | 14031 | const struct mips16_immed_operand *op; |
b34976b6 | 14032 | bfd_boolean small, ext; |
252b5132 RH |
14033 | offsetT val; |
14034 | bfd_byte *buf; | |
14035 | unsigned long insn; | |
b34976b6 | 14036 | bfd_boolean use_extend; |
252b5132 RH |
14037 | unsigned short extend; |
14038 | ||
14039 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
14040 | op = mips16_immed_operands; | |
14041 | while (op->type != type) | |
14042 | ++op; | |
14043 | ||
14044 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
14045 | { | |
b34976b6 AM |
14046 | small = FALSE; |
14047 | ext = TRUE; | |
252b5132 RH |
14048 | } |
14049 | else | |
14050 | { | |
b34976b6 AM |
14051 | small = TRUE; |
14052 | ext = FALSE; | |
252b5132 RH |
14053 | } |
14054 | ||
6386f3a7 | 14055 | resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
14056 | val = S_GET_VALUE (fragp->fr_symbol); |
14057 | if (op->pcrel) | |
14058 | { | |
14059 | addressT addr; | |
14060 | ||
14061 | addr = fragp->fr_address + fragp->fr_fix; | |
14062 | ||
14063 | /* The rules for the base address of a PC relative reloc are | |
14064 | complicated; see mips16_extended_frag. */ | |
14065 | if (type == 'p' || type == 'q') | |
14066 | { | |
14067 | addr += 2; | |
14068 | if (ext) | |
14069 | addr += 2; | |
14070 | /* Ignore the low bit in the target, since it will be | |
14071 | set for a text label. */ | |
14072 | if ((val & 1) != 0) | |
14073 | --val; | |
14074 | } | |
14075 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
14076 | addr -= 4; | |
14077 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
14078 | addr -= 2; | |
14079 | ||
14080 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
14081 | val -= addr; | |
14082 | ||
14083 | /* Make sure the section winds up with the alignment we have | |
14084 | assumed. */ | |
14085 | if (op->shift > 0) | |
14086 | record_alignment (asec, op->shift); | |
14087 | } | |
14088 | ||
14089 | if (ext | |
14090 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
14091 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
14092 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
14093 | _("extended instruction in delay slot")); | |
14094 | ||
14095 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
14096 | ||
14097 | if (target_big_endian) | |
14098 | insn = bfd_getb16 (buf); | |
14099 | else | |
14100 | insn = bfd_getl16 (buf); | |
14101 | ||
14102 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
14103 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
14104 | small, ext, &insn, &use_extend, &extend); | |
14105 | ||
14106 | if (use_extend) | |
14107 | { | |
2132e3a3 | 14108 | md_number_to_chars ((char *) buf, 0xf000 | extend, 2); |
252b5132 RH |
14109 | fragp->fr_fix += 2; |
14110 | buf += 2; | |
14111 | } | |
14112 | ||
2132e3a3 | 14113 | md_number_to_chars ((char *) buf, insn, 2); |
252b5132 RH |
14114 | fragp->fr_fix += 2; |
14115 | buf += 2; | |
14116 | } | |
14117 | else | |
14118 | { | |
4d7206a2 RS |
14119 | int first, second; |
14120 | fixS *fixp; | |
252b5132 | 14121 | |
4d7206a2 RS |
14122 | first = RELAX_FIRST (fragp->fr_subtype); |
14123 | second = RELAX_SECOND (fragp->fr_subtype); | |
14124 | fixp = (fixS *) fragp->fr_opcode; | |
252b5132 | 14125 | |
584892a6 RS |
14126 | /* Possibly emit a warning if we've chosen the longer option. */ |
14127 | if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0) | |
14128 | == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0)) | |
14129 | { | |
14130 | const char *msg = macro_warning (fragp->fr_subtype); | |
14131 | if (msg != 0) | |
14132 | as_warn_where (fragp->fr_file, fragp->fr_line, msg); | |
14133 | } | |
14134 | ||
4d7206a2 RS |
14135 | /* Go through all the fixups for the first sequence. Disable them |
14136 | (by marking them as done) if we're going to use the second | |
14137 | sequence instead. */ | |
14138 | while (fixp | |
14139 | && fixp->fx_frag == fragp | |
14140 | && fixp->fx_where < fragp->fr_fix - second) | |
14141 | { | |
14142 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
14143 | fixp->fx_done = 1; | |
14144 | fixp = fixp->fx_next; | |
14145 | } | |
252b5132 | 14146 | |
4d7206a2 RS |
14147 | /* Go through the fixups for the second sequence. Disable them if |
14148 | we're going to use the first sequence, otherwise adjust their | |
14149 | addresses to account for the relaxation. */ | |
14150 | while (fixp && fixp->fx_frag == fragp) | |
14151 | { | |
14152 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
14153 | fixp->fx_where -= first; | |
14154 | else | |
14155 | fixp->fx_done = 1; | |
14156 | fixp = fixp->fx_next; | |
14157 | } | |
14158 | ||
14159 | /* Now modify the frag contents. */ | |
14160 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
14161 | { | |
14162 | char *start; | |
14163 | ||
14164 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
14165 | memmove (start, start + first, second); | |
14166 | fragp->fr_fix -= first; | |
14167 | } | |
14168 | else | |
14169 | fragp->fr_fix -= second; | |
252b5132 RH |
14170 | } |
14171 | } | |
14172 | ||
14173 | #ifdef OBJ_ELF | |
14174 | ||
14175 | /* This function is called after the relocs have been generated. | |
14176 | We've been storing mips16 text labels as odd. Here we convert them | |
14177 | back to even for the convenience of the debugger. */ | |
14178 | ||
14179 | void | |
17a2f251 | 14180 | mips_frob_file_after_relocs (void) |
252b5132 RH |
14181 | { |
14182 | asymbol **syms; | |
14183 | unsigned int count, i; | |
14184 | ||
f43abd2b | 14185 | if (!IS_ELF) |
252b5132 RH |
14186 | return; |
14187 | ||
14188 | syms = bfd_get_outsymbols (stdoutput); | |
14189 | count = bfd_get_symcount (stdoutput); | |
14190 | for (i = 0; i < count; i++, syms++) | |
14191 | { | |
14192 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
14193 | && ((*syms)->value & 1) != 0) | |
14194 | { | |
14195 | (*syms)->value &= ~1; | |
14196 | /* If the symbol has an odd size, it was probably computed | |
14197 | incorrectly, so adjust that as well. */ | |
14198 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
14199 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
14200 | } | |
14201 | } | |
14202 | } | |
14203 | ||
14204 | #endif | |
14205 | ||
14206 | /* This function is called whenever a label is defined. It is used | |
14207 | when handling branch delays; if a branch has a label, we assume we | |
14208 | can not move it. */ | |
14209 | ||
14210 | void | |
17a2f251 | 14211 | mips_define_label (symbolS *sym) |
252b5132 | 14212 | { |
a8dbcb85 | 14213 | segment_info_type *si = seg_info (now_seg); |
252b5132 RH |
14214 | struct insn_label_list *l; |
14215 | ||
14216 | if (free_insn_labels == NULL) | |
14217 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
14218 | else | |
14219 | { | |
14220 | l = free_insn_labels; | |
14221 | free_insn_labels = l->next; | |
14222 | } | |
14223 | ||
14224 | l->label = sym; | |
a8dbcb85 TS |
14225 | l->next = si->label_list; |
14226 | si->label_list = l; | |
07a53e5c RH |
14227 | |
14228 | #ifdef OBJ_ELF | |
14229 | dwarf2_emit_label (sym); | |
14230 | #endif | |
252b5132 RH |
14231 | } |
14232 | \f | |
14233 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
14234 | ||
14235 | /* Some special processing for a MIPS ELF file. */ | |
14236 | ||
14237 | void | |
17a2f251 | 14238 | mips_elf_final_processing (void) |
252b5132 RH |
14239 | { |
14240 | /* Write out the register information. */ | |
316f5878 | 14241 | if (mips_abi != N64_ABI) |
252b5132 RH |
14242 | { |
14243 | Elf32_RegInfo s; | |
14244 | ||
14245 | s.ri_gprmask = mips_gprmask; | |
14246 | s.ri_cprmask[0] = mips_cprmask[0]; | |
14247 | s.ri_cprmask[1] = mips_cprmask[1]; | |
14248 | s.ri_cprmask[2] = mips_cprmask[2]; | |
14249 | s.ri_cprmask[3] = mips_cprmask[3]; | |
14250 | /* The gp_value field is set by the MIPS ELF backend. */ | |
14251 | ||
14252 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
14253 | ((Elf32_External_RegInfo *) | |
14254 | mips_regmask_frag)); | |
14255 | } | |
14256 | else | |
14257 | { | |
14258 | Elf64_Internal_RegInfo s; | |
14259 | ||
14260 | s.ri_gprmask = mips_gprmask; | |
14261 | s.ri_pad = 0; | |
14262 | s.ri_cprmask[0] = mips_cprmask[0]; | |
14263 | s.ri_cprmask[1] = mips_cprmask[1]; | |
14264 | s.ri_cprmask[2] = mips_cprmask[2]; | |
14265 | s.ri_cprmask[3] = mips_cprmask[3]; | |
14266 | /* The gp_value field is set by the MIPS ELF backend. */ | |
14267 | ||
14268 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
14269 | ((Elf64_External_RegInfo *) | |
14270 | mips_regmask_frag)); | |
14271 | } | |
14272 | ||
14273 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
14274 | sort of BFD interface for this. */ | |
14275 | if (mips_any_noreorder) | |
14276 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
14277 | if (mips_pic != NO_PIC) | |
143d77c5 | 14278 | { |
252b5132 | 14279 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
14280 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
14281 | } | |
14282 | if (mips_abicalls) | |
14283 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 14284 | |
98d3f06f | 14285 | /* Set MIPS ELF flags for ASEs. */ |
74cd071d CF |
14286 | /* We may need to define a new flag for DSP ASE, and set this flag when |
14287 | file_ase_dsp is true. */ | |
8b082fb1 | 14288 | /* Same for DSP R2. */ |
ef2e4d86 CF |
14289 | /* We may need to define a new flag for MT ASE, and set this flag when |
14290 | file_ase_mt is true. */ | |
a4672219 TS |
14291 | if (file_ase_mips16) |
14292 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
1f25f5d3 CD |
14293 | #if 0 /* XXX FIXME */ |
14294 | if (file_ase_mips3d) | |
14295 | elf_elfheader (stdoutput)->e_flags |= ???; | |
14296 | #endif | |
deec1734 CD |
14297 | if (file_ase_mdmx) |
14298 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; | |
1f25f5d3 | 14299 | |
bdaaa2e1 | 14300 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 14301 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 14302 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 14303 | else if (mips_abi == O64_ABI) |
252b5132 | 14304 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 14305 | else if (mips_abi == EABI_ABI) |
252b5132 | 14306 | { |
316f5878 | 14307 | if (!file_mips_gp32) |
252b5132 RH |
14308 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
14309 | else | |
14310 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
14311 | } | |
316f5878 | 14312 | else if (mips_abi == N32_ABI) |
be00bddd TS |
14313 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
14314 | ||
c9914766 | 14315 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
14316 | |
14317 | if (mips_32bitmode) | |
14318 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
ad3fea08 TS |
14319 | |
14320 | #if 0 /* XXX FIXME */ | |
14321 | /* 32 bit code with 64 bit FP registers. */ | |
14322 | if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
14323 | elf_elfheader (stdoutput)->e_flags |= ???; | |
14324 | #endif | |
252b5132 RH |
14325 | } |
14326 | ||
14327 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
14328 | \f | |
beae10d5 | 14329 | typedef struct proc { |
9b2f1d35 EC |
14330 | symbolS *func_sym; |
14331 | symbolS *func_end_sym; | |
beae10d5 KH |
14332 | unsigned long reg_mask; |
14333 | unsigned long reg_offset; | |
14334 | unsigned long fpreg_mask; | |
14335 | unsigned long fpreg_offset; | |
14336 | unsigned long frame_offset; | |
14337 | unsigned long frame_reg; | |
14338 | unsigned long pc_reg; | |
14339 | } procS; | |
252b5132 RH |
14340 | |
14341 | static procS cur_proc; | |
14342 | static procS *cur_proc_ptr; | |
14343 | static int numprocs; | |
14344 | ||
0a9ef439 | 14345 | /* Fill in an rs_align_code fragment. */ |
a19d8eb0 | 14346 | |
0a9ef439 | 14347 | void |
17a2f251 | 14348 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 14349 | { |
0a9ef439 RH |
14350 | if (fragp->fr_type != rs_align_code) |
14351 | return; | |
14352 | ||
14353 | if (mips_opts.mips16) | |
a19d8eb0 CP |
14354 | { |
14355 | static const unsigned char be_nop[] = { 0x65, 0x00 }; | |
14356 | static const unsigned char le_nop[] = { 0x00, 0x65 }; | |
14357 | ||
0a9ef439 RH |
14358 | int bytes; |
14359 | char *p; | |
a19d8eb0 | 14360 | |
0a9ef439 RH |
14361 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
14362 | p = fragp->fr_literal + fragp->fr_fix; | |
14363 | ||
14364 | if (bytes & 1) | |
14365 | { | |
14366 | *p++ = 0; | |
f9419b05 | 14367 | fragp->fr_fix++; |
0a9ef439 RH |
14368 | } |
14369 | ||
14370 | memcpy (p, (target_big_endian ? be_nop : le_nop), 2); | |
14371 | fragp->fr_var = 2; | |
a19d8eb0 CP |
14372 | } |
14373 | ||
0a9ef439 | 14374 | /* For mips32, a nop is a zero, which we trivially get by doing nothing. */ |
a19d8eb0 CP |
14375 | } |
14376 | ||
252b5132 | 14377 | static void |
17a2f251 | 14378 | md_obj_begin (void) |
252b5132 RH |
14379 | { |
14380 | } | |
14381 | ||
14382 | static void | |
17a2f251 | 14383 | md_obj_end (void) |
252b5132 | 14384 | { |
54f4ddb3 | 14385 | /* Check for premature end, nesting errors, etc. */ |
252b5132 | 14386 | if (cur_proc_ptr) |
9a41af64 | 14387 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
14388 | } |
14389 | ||
14390 | static long | |
17a2f251 | 14391 | get_number (void) |
252b5132 RH |
14392 | { |
14393 | int negative = 0; | |
14394 | long val = 0; | |
14395 | ||
14396 | if (*input_line_pointer == '-') | |
14397 | { | |
14398 | ++input_line_pointer; | |
14399 | negative = 1; | |
14400 | } | |
3882b010 | 14401 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 14402 | as_bad (_("expected simple number")); |
252b5132 RH |
14403 | if (input_line_pointer[0] == '0') |
14404 | { | |
14405 | if (input_line_pointer[1] == 'x') | |
14406 | { | |
14407 | input_line_pointer += 2; | |
3882b010 | 14408 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
14409 | { |
14410 | val <<= 4; | |
14411 | val |= hex_value (*input_line_pointer++); | |
14412 | } | |
14413 | return negative ? -val : val; | |
14414 | } | |
14415 | else | |
14416 | { | |
14417 | ++input_line_pointer; | |
3882b010 | 14418 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
14419 | { |
14420 | val <<= 3; | |
14421 | val |= *input_line_pointer++ - '0'; | |
14422 | } | |
14423 | return negative ? -val : val; | |
14424 | } | |
14425 | } | |
3882b010 | 14426 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
14427 | { |
14428 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
14429 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 14430 | as_warn (_("invalid number")); |
252b5132 RH |
14431 | return -1; |
14432 | } | |
3882b010 | 14433 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
14434 | { |
14435 | val *= 10; | |
14436 | val += *input_line_pointer++ - '0'; | |
14437 | } | |
14438 | return negative ? -val : val; | |
14439 | } | |
14440 | ||
14441 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
14442 | is an initial number which is the ECOFF file index. In the non-ECOFF |
14443 | case .file implies DWARF-2. */ | |
14444 | ||
14445 | static void | |
17a2f251 | 14446 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 14447 | { |
ecb4347a DJ |
14448 | static int first_file_directive = 0; |
14449 | ||
c5dd6aab DJ |
14450 | if (ECOFF_DEBUGGING) |
14451 | { | |
14452 | get_number (); | |
14453 | s_app_file (0); | |
14454 | } | |
14455 | else | |
ecb4347a DJ |
14456 | { |
14457 | char *filename; | |
14458 | ||
14459 | filename = dwarf2_directive_file (0); | |
14460 | ||
14461 | /* Versions of GCC up to 3.1 start files with a ".file" | |
14462 | directive even for stabs output. Make sure that this | |
14463 | ".file" is handled. Note that you need a version of GCC | |
14464 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
14465 | if (filename != NULL && ! first_file_directive) | |
14466 | { | |
14467 | (void) new_logical_line (filename, -1); | |
c04f5787 | 14468 | s_app_file_string (filename, 0); |
ecb4347a DJ |
14469 | } |
14470 | first_file_directive = 1; | |
14471 | } | |
c5dd6aab DJ |
14472 | } |
14473 | ||
14474 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
14475 | |
14476 | static void | |
17a2f251 | 14477 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 14478 | { |
c5dd6aab DJ |
14479 | if (!ECOFF_DEBUGGING) |
14480 | dwarf2_directive_loc (0); | |
252b5132 RH |
14481 | } |
14482 | ||
252b5132 RH |
14483 | /* The .end directive. */ |
14484 | ||
14485 | static void | |
17a2f251 | 14486 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
14487 | { |
14488 | symbolS *p; | |
252b5132 | 14489 | |
7a621144 DJ |
14490 | /* Following functions need their own .frame and .cprestore directives. */ |
14491 | mips_frame_reg_valid = 0; | |
14492 | mips_cprestore_valid = 0; | |
14493 | ||
252b5132 RH |
14494 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
14495 | { | |
14496 | p = get_symbol (); | |
14497 | demand_empty_rest_of_line (); | |
14498 | } | |
14499 | else | |
14500 | p = NULL; | |
14501 | ||
14949570 | 14502 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
14503 | as_warn (_(".end not in text section")); |
14504 | ||
14505 | if (!cur_proc_ptr) | |
14506 | { | |
14507 | as_warn (_(".end directive without a preceding .ent directive.")); | |
14508 | demand_empty_rest_of_line (); | |
14509 | return; | |
14510 | } | |
14511 | ||
14512 | if (p != NULL) | |
14513 | { | |
14514 | assert (S_GET_NAME (p)); | |
9b2f1d35 | 14515 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
252b5132 | 14516 | as_warn (_(".end symbol does not match .ent symbol.")); |
ecb4347a DJ |
14517 | |
14518 | if (debug_type == DEBUG_STABS) | |
14519 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
14520 | S_GET_NAME (p)); | |
252b5132 RH |
14521 | } |
14522 | else | |
14523 | as_warn (_(".end directive missing or unknown symbol")); | |
14524 | ||
2132e3a3 | 14525 | #ifdef OBJ_ELF |
9b2f1d35 EC |
14526 | /* Create an expression to calculate the size of the function. */ |
14527 | if (p && cur_proc_ptr) | |
14528 | { | |
14529 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
14530 | expressionS *exp = xmalloc (sizeof (expressionS)); | |
14531 | ||
14532 | obj->size = exp; | |
14533 | exp->X_op = O_subtract; | |
14534 | exp->X_add_symbol = symbol_temp_new_now (); | |
14535 | exp->X_op_symbol = p; | |
14536 | exp->X_add_number = 0; | |
14537 | ||
14538 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
14539 | } | |
14540 | ||
ecb4347a | 14541 | /* Generate a .pdr section. */ |
f43abd2b | 14542 | if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr) |
ecb4347a DJ |
14543 | { |
14544 | segT saved_seg = now_seg; | |
14545 | subsegT saved_subseg = now_subseg; | |
14546 | valueT dot; | |
14547 | expressionS exp; | |
14548 | char *fragp; | |
252b5132 | 14549 | |
ecb4347a | 14550 | dot = frag_now_fix (); |
252b5132 RH |
14551 | |
14552 | #ifdef md_flush_pending_output | |
ecb4347a | 14553 | md_flush_pending_output (); |
252b5132 RH |
14554 | #endif |
14555 | ||
ecb4347a DJ |
14556 | assert (pdr_seg); |
14557 | subseg_set (pdr_seg, 0); | |
252b5132 | 14558 | |
ecb4347a DJ |
14559 | /* Write the symbol. */ |
14560 | exp.X_op = O_symbol; | |
14561 | exp.X_add_symbol = p; | |
14562 | exp.X_add_number = 0; | |
14563 | emit_expr (&exp, 4); | |
252b5132 | 14564 | |
ecb4347a | 14565 | fragp = frag_more (7 * 4); |
252b5132 | 14566 | |
17a2f251 TS |
14567 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
14568 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
14569 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
14570 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
14571 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
14572 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
14573 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 14574 | |
ecb4347a DJ |
14575 | subseg_set (saved_seg, saved_subseg); |
14576 | } | |
14577 | #endif /* OBJ_ELF */ | |
252b5132 RH |
14578 | |
14579 | cur_proc_ptr = NULL; | |
14580 | } | |
14581 | ||
14582 | /* The .aent and .ent directives. */ | |
14583 | ||
14584 | static void | |
17a2f251 | 14585 | s_mips_ent (int aent) |
252b5132 | 14586 | { |
252b5132 | 14587 | symbolS *symbolP; |
252b5132 RH |
14588 | |
14589 | symbolP = get_symbol (); | |
14590 | if (*input_line_pointer == ',') | |
f9419b05 | 14591 | ++input_line_pointer; |
252b5132 | 14592 | SKIP_WHITESPACE (); |
3882b010 | 14593 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 14594 | || *input_line_pointer == '-') |
874e8986 | 14595 | get_number (); |
252b5132 | 14596 | |
14949570 | 14597 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
14598 | as_warn (_(".ent or .aent not in text section.")); |
14599 | ||
14600 | if (!aent && cur_proc_ptr) | |
9a41af64 | 14601 | as_warn (_("missing .end")); |
252b5132 RH |
14602 | |
14603 | if (!aent) | |
14604 | { | |
7a621144 DJ |
14605 | /* This function needs its own .frame and .cprestore directives. */ |
14606 | mips_frame_reg_valid = 0; | |
14607 | mips_cprestore_valid = 0; | |
14608 | ||
252b5132 RH |
14609 | cur_proc_ptr = &cur_proc; |
14610 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
14611 | ||
9b2f1d35 | 14612 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 14613 | |
49309057 | 14614 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
252b5132 | 14615 | |
f9419b05 | 14616 | ++numprocs; |
ecb4347a DJ |
14617 | |
14618 | if (debug_type == DEBUG_STABS) | |
14619 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
14620 | S_GET_NAME (symbolP)); | |
252b5132 RH |
14621 | } |
14622 | ||
14623 | demand_empty_rest_of_line (); | |
14624 | } | |
14625 | ||
14626 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 14627 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 14628 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 14629 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
14630 | symbol table (in the mdebug section). */ |
14631 | ||
14632 | static void | |
17a2f251 | 14633 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 14634 | { |
ecb4347a | 14635 | #ifdef OBJ_ELF |
f43abd2b | 14636 | if (IS_ELF && !ECOFF_DEBUGGING) |
ecb4347a DJ |
14637 | { |
14638 | long val; | |
252b5132 | 14639 | |
ecb4347a DJ |
14640 | if (cur_proc_ptr == (procS *) NULL) |
14641 | { | |
14642 | as_warn (_(".frame outside of .ent")); | |
14643 | demand_empty_rest_of_line (); | |
14644 | return; | |
14645 | } | |
252b5132 | 14646 | |
ecb4347a DJ |
14647 | cur_proc_ptr->frame_reg = tc_get_register (1); |
14648 | ||
14649 | SKIP_WHITESPACE (); | |
14650 | if (*input_line_pointer++ != ',' | |
14651 | || get_absolute_expression_and_terminator (&val) != ',') | |
14652 | { | |
14653 | as_warn (_("Bad .frame directive")); | |
14654 | --input_line_pointer; | |
14655 | demand_empty_rest_of_line (); | |
14656 | return; | |
14657 | } | |
252b5132 | 14658 | |
ecb4347a DJ |
14659 | cur_proc_ptr->frame_offset = val; |
14660 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 14661 | |
252b5132 | 14662 | demand_empty_rest_of_line (); |
252b5132 | 14663 | } |
ecb4347a DJ |
14664 | else |
14665 | #endif /* OBJ_ELF */ | |
14666 | s_ignore (ignore); | |
252b5132 RH |
14667 | } |
14668 | ||
bdaaa2e1 KH |
14669 | /* The .fmask and .mask directives. If the mdebug section is present |
14670 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 14671 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 14672 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
14673 | make reference to the ecoff symbol table (in the mdebug section). */ |
14674 | ||
14675 | static void | |
17a2f251 | 14676 | s_mips_mask (int reg_type) |
252b5132 | 14677 | { |
ecb4347a | 14678 | #ifdef OBJ_ELF |
f43abd2b | 14679 | if (IS_ELF && !ECOFF_DEBUGGING) |
252b5132 | 14680 | { |
ecb4347a | 14681 | long mask, off; |
252b5132 | 14682 | |
ecb4347a DJ |
14683 | if (cur_proc_ptr == (procS *) NULL) |
14684 | { | |
14685 | as_warn (_(".mask/.fmask outside of .ent")); | |
14686 | demand_empty_rest_of_line (); | |
14687 | return; | |
14688 | } | |
252b5132 | 14689 | |
ecb4347a DJ |
14690 | if (get_absolute_expression_and_terminator (&mask) != ',') |
14691 | { | |
14692 | as_warn (_("Bad .mask/.fmask directive")); | |
14693 | --input_line_pointer; | |
14694 | demand_empty_rest_of_line (); | |
14695 | return; | |
14696 | } | |
252b5132 | 14697 | |
ecb4347a DJ |
14698 | off = get_absolute_expression (); |
14699 | ||
14700 | if (reg_type == 'F') | |
14701 | { | |
14702 | cur_proc_ptr->fpreg_mask = mask; | |
14703 | cur_proc_ptr->fpreg_offset = off; | |
14704 | } | |
14705 | else | |
14706 | { | |
14707 | cur_proc_ptr->reg_mask = mask; | |
14708 | cur_proc_ptr->reg_offset = off; | |
14709 | } | |
14710 | ||
14711 | demand_empty_rest_of_line (); | |
252b5132 RH |
14712 | } |
14713 | else | |
ecb4347a DJ |
14714 | #endif /* OBJ_ELF */ |
14715 | s_ignore (reg_type); | |
252b5132 RH |
14716 | } |
14717 | ||
316f5878 RS |
14718 | /* A table describing all the processors gas knows about. Names are |
14719 | matched in the order listed. | |
e7af610e | 14720 | |
316f5878 RS |
14721 | To ease comparison, please keep this table in the same order as |
14722 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
14723 | static const struct mips_cpu_info mips_cpu_info_table[] = |
14724 | { | |
316f5878 | 14725 | /* Entries for generic ISAs */ |
ad3fea08 TS |
14726 | { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 }, |
14727 | { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 }, | |
14728 | { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 }, | |
14729 | { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 }, | |
14730 | { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 }, | |
14731 | { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 }, | |
14732 | { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14733 | { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 }, | |
14734 | { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 }, | |
316f5878 RS |
14735 | |
14736 | /* MIPS I */ | |
ad3fea08 TS |
14737 | { "r3000", 0, ISA_MIPS1, CPU_R3000 }, |
14738 | { "r2000", 0, ISA_MIPS1, CPU_R3000 }, | |
14739 | { "r3900", 0, ISA_MIPS1, CPU_R3900 }, | |
316f5878 RS |
14740 | |
14741 | /* MIPS II */ | |
ad3fea08 | 14742 | { "r6000", 0, ISA_MIPS2, CPU_R6000 }, |
316f5878 RS |
14743 | |
14744 | /* MIPS III */ | |
ad3fea08 TS |
14745 | { "r4000", 0, ISA_MIPS3, CPU_R4000 }, |
14746 | { "r4010", 0, ISA_MIPS2, CPU_R4010 }, | |
14747 | { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, | |
14748 | { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, | |
14749 | { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, | |
14750 | { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, | |
14751 | { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, | |
14752 | { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, | |
14753 | { "r4400", 0, ISA_MIPS3, CPU_R4400 }, | |
14754 | { "r4600", 0, ISA_MIPS3, CPU_R4600 }, | |
14755 | { "orion", 0, ISA_MIPS3, CPU_R4600 }, | |
14756 | { "r4650", 0, ISA_MIPS3, CPU_R4650 }, | |
316f5878 RS |
14757 | |
14758 | /* MIPS IV */ | |
ad3fea08 TS |
14759 | { "r8000", 0, ISA_MIPS4, CPU_R8000 }, |
14760 | { "r10000", 0, ISA_MIPS4, CPU_R10000 }, | |
14761 | { "r12000", 0, ISA_MIPS4, CPU_R12000 }, | |
14762 | { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, | |
14763 | { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, | |
14764 | { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, | |
14765 | { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, | |
14766 | { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, | |
14767 | { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, | |
14768 | { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, | |
14769 | { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, | |
14770 | { "rm7000", 0, ISA_MIPS4, CPU_RM7000 }, | |
14771 | { "rm9000", 0, ISA_MIPS4, CPU_RM9000 }, | |
316f5878 RS |
14772 | |
14773 | /* MIPS 32 */ | |
ad3fea08 TS |
14774 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32 }, |
14775 | { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, | |
14776 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, | |
14777 | { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 }, | |
14778 | ||
14779 | /* MIPS 32 Release 2 */ | |
14780 | { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14781 | { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14782 | { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14783 | { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14784 | { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14785 | { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ad3fea08 | 14786 | { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 | 14787 | { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
ad3fea08 | 14788 | { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 RS |
14789 | { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
14790 | /* Deprecated forms of the above. */ | |
14791 | { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ad3fea08 | 14792 | { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 14793 | /* 24KE is a 24K with DSP ASE, other ASEs are optional. */ |
ad3fea08 | 14794 | { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 | 14795 | { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
ad3fea08 | 14796 | { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
0fdf1951 RS |
14797 | { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
14798 | /* Deprecated forms of the above. */ | |
14799 | { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
65263ce3 | 14800 | { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 14801 | /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */ |
a360e743 TS |
14802 | { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
14803 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
14804 | { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
14805 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
a360e743 TS |
14806 | { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
14807 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
14808 | { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
14809 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14810 | /* Deprecated forms of the above. */ | |
14811 | { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
14812 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
a360e743 TS |
14813 | { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, |
14814 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
14815 | /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */ |
14816 | { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
14817 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
14818 | { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
14819 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
14820 | { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
14821 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 RS |
14822 | { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
14823 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14824 | { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
14825 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14826 | /* Deprecated forms of the above. */ | |
14827 | { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, | |
14828 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f TS |
14829 | { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, |
14830 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
32b26a03 | 14831 | |
316f5878 | 14832 | /* MIPS 64 */ |
ad3fea08 TS |
14833 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, |
14834 | { "5kf", 0, ISA_MIPS64, CPU_MIPS64 }, | |
14835 | { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
7764b395 | 14836 | { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, |
ad3fea08 TS |
14837 | |
14838 | /* MIPS 64 Release 2 */ | |
e7af610e | 14839 | |
c7a23324 | 14840 | /* Broadcom SB-1 CPU core */ |
65263ce3 TS |
14841 | { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, |
14842 | ISA_MIPS64, CPU_SB1 }, | |
1e85aad8 JW |
14843 | /* Broadcom SB-1A CPU core */ |
14844 | { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, | |
14845 | ISA_MIPS64, CPU_SB1 }, | |
e7af610e | 14846 | |
316f5878 RS |
14847 | /* End marker */ |
14848 | { NULL, 0, 0, 0 } | |
14849 | }; | |
e7af610e | 14850 | |
84ea6cf2 | 14851 | |
316f5878 RS |
14852 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
14853 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 14854 | |
316f5878 | 14855 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 14856 | |
b34976b6 | 14857 | static bfd_boolean |
17a2f251 | 14858 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
14859 | { |
14860 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
14861 | given++, canonical++; | |
14862 | ||
14863 | return ((*given == 0 && *canonical == 0) | |
14864 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
14865 | } | |
14866 | ||
14867 | ||
14868 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
14869 | CPU name. We've traditionally allowed a lot of variation here. | |
14870 | ||
14871 | Note: this function is shared between GCC and GAS. */ | |
14872 | ||
b34976b6 | 14873 | static bfd_boolean |
17a2f251 | 14874 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
14875 | { |
14876 | /* First see if the name matches exactly, or with a final "000" | |
14877 | turned into "k". */ | |
14878 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 14879 | return TRUE; |
316f5878 RS |
14880 | |
14881 | /* If not, try comparing based on numerical designation alone. | |
14882 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
14883 | if (TOLOWER (*given) == 'r') | |
14884 | given++; | |
14885 | if (!ISDIGIT (*given)) | |
b34976b6 | 14886 | return FALSE; |
316f5878 RS |
14887 | |
14888 | /* Skip over some well-known prefixes in the canonical name, | |
14889 | hoping to find a number there too. */ | |
14890 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
14891 | canonical += 2; | |
14892 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
14893 | canonical += 2; | |
14894 | else if (TOLOWER (canonical[0]) == 'r') | |
14895 | canonical += 1; | |
14896 | ||
14897 | return mips_strict_matching_cpu_name_p (canonical, given); | |
14898 | } | |
14899 | ||
14900 | ||
14901 | /* Parse an option that takes the name of a processor as its argument. | |
14902 | OPTION is the name of the option and CPU_STRING is the argument. | |
14903 | Return the corresponding processor enumeration if the CPU_STRING is | |
14904 | recognized, otherwise report an error and return null. | |
14905 | ||
14906 | A similar function exists in GCC. */ | |
e7af610e NC |
14907 | |
14908 | static const struct mips_cpu_info * | |
17a2f251 | 14909 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 14910 | { |
316f5878 | 14911 | const struct mips_cpu_info *p; |
e7af610e | 14912 | |
316f5878 RS |
14913 | /* 'from-abi' selects the most compatible architecture for the given |
14914 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
14915 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
14916 | version. Look first at the -mgp options, if given, otherwise base | |
14917 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 14918 | |
316f5878 RS |
14919 | Treat NO_ABI like the EABIs. One reason to do this is that the |
14920 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
14921 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
14922 | 'mips64', just as we did in the days before 'from-abi'. */ | |
14923 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
14924 | { | |
14925 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
14926 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
14927 | ||
14928 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
14929 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
14930 | ||
14931 | if (file_mips_gp32 >= 0) | |
14932 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
14933 | ||
14934 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
14935 | ? ISA_MIPS3 | |
14936 | : ISA_MIPS1); | |
14937 | } | |
14938 | ||
14939 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
14940 | if (strcasecmp (cpu_string, "default") == 0) | |
14941 | return 0; | |
14942 | ||
14943 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
14944 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
14945 | return p; | |
14946 | ||
14947 | as_bad ("Bad value (%s) for %s", cpu_string, option); | |
14948 | return 0; | |
e7af610e NC |
14949 | } |
14950 | ||
316f5878 RS |
14951 | /* Return the canonical processor information for ISA (a member of the |
14952 | ISA_MIPS* enumeration). */ | |
14953 | ||
e7af610e | 14954 | static const struct mips_cpu_info * |
17a2f251 | 14955 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
14956 | { |
14957 | int i; | |
14958 | ||
14959 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
ad3fea08 | 14960 | if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA) |
316f5878 | 14961 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
14962 | return (&mips_cpu_info_table[i]); |
14963 | ||
e972090a | 14964 | return NULL; |
e7af610e | 14965 | } |
fef14a42 TS |
14966 | |
14967 | static const struct mips_cpu_info * | |
17a2f251 | 14968 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
14969 | { |
14970 | int i; | |
14971 | ||
14972 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
14973 | if (arch == mips_cpu_info_table[i].cpu) | |
14974 | return (&mips_cpu_info_table[i]); | |
14975 | ||
14976 | return NULL; | |
14977 | } | |
316f5878 RS |
14978 | \f |
14979 | static void | |
17a2f251 | 14980 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
14981 | { |
14982 | if (*first_p) | |
14983 | { | |
14984 | fprintf (stream, "%24s", ""); | |
14985 | *col_p = 24; | |
14986 | } | |
14987 | else | |
14988 | { | |
14989 | fprintf (stream, ", "); | |
14990 | *col_p += 2; | |
14991 | } | |
e7af610e | 14992 | |
316f5878 RS |
14993 | if (*col_p + strlen (string) > 72) |
14994 | { | |
14995 | fprintf (stream, "\n%24s", ""); | |
14996 | *col_p = 24; | |
14997 | } | |
14998 | ||
14999 | fprintf (stream, "%s", string); | |
15000 | *col_p += strlen (string); | |
15001 | ||
15002 | *first_p = 0; | |
15003 | } | |
15004 | ||
15005 | void | |
17a2f251 | 15006 | md_show_usage (FILE *stream) |
e7af610e | 15007 | { |
316f5878 RS |
15008 | int column, first; |
15009 | size_t i; | |
15010 | ||
15011 | fprintf (stream, _("\ | |
15012 | MIPS options:\n\ | |
316f5878 RS |
15013 | -EB generate big endian output\n\ |
15014 | -EL generate little endian output\n\ | |
15015 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
15016 | -G NUM allow referencing objects up to NUM bytes\n\ | |
15017 | implicitly with the gp register [default 8]\n")); | |
15018 | fprintf (stream, _("\ | |
15019 | -mips1 generate MIPS ISA I instructions\n\ | |
15020 | -mips2 generate MIPS ISA II instructions\n\ | |
15021 | -mips3 generate MIPS ISA III instructions\n\ | |
15022 | -mips4 generate MIPS ISA IV instructions\n\ | |
15023 | -mips5 generate MIPS ISA V instructions\n\ | |
15024 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 15025 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 | 15026 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 15027 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
316f5878 RS |
15028 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
15029 | ||
15030 | first = 1; | |
e7af610e NC |
15031 | |
15032 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
15033 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
15034 | show (stream, "from-abi", &column, &first); | |
15035 | fputc ('\n', stream); | |
e7af610e | 15036 | |
316f5878 RS |
15037 | fprintf (stream, _("\ |
15038 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
15039 | -no-mCPU don't generate code specific to CPU.\n\ | |
15040 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
15041 | ||
15042 | first = 1; | |
15043 | ||
15044 | show (stream, "3900", &column, &first); | |
15045 | show (stream, "4010", &column, &first); | |
15046 | show (stream, "4100", &column, &first); | |
15047 | show (stream, "4650", &column, &first); | |
15048 | fputc ('\n', stream); | |
15049 | ||
15050 | fprintf (stream, _("\ | |
15051 | -mips16 generate mips16 instructions\n\ | |
15052 | -no-mips16 do not generate mips16 instructions\n")); | |
15053 | fprintf (stream, _("\ | |
e16bfa71 TS |
15054 | -msmartmips generate smartmips instructions\n\ |
15055 | -mno-smartmips do not generate smartmips instructions\n")); | |
15056 | fprintf (stream, _("\ | |
74cd071d CF |
15057 | -mdsp generate DSP instructions\n\ |
15058 | -mno-dsp do not generate DSP instructions\n")); | |
15059 | fprintf (stream, _("\ | |
8b082fb1 TS |
15060 | -mdspr2 generate DSP R2 instructions\n\ |
15061 | -mno-dspr2 do not generate DSP R2 instructions\n")); | |
15062 | fprintf (stream, _("\ | |
ef2e4d86 CF |
15063 | -mmt generate MT instructions\n\ |
15064 | -mno-mt do not generate MT instructions\n")); | |
15065 | fprintf (stream, _("\ | |
d766e8ec | 15066 | -mfix-vr4120 work around certain VR4120 errata\n\ |
7d8e00cf | 15067 | -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ |
316f5878 RS |
15068 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
15069 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
aed1a261 | 15070 | -msym32 assume all symbols have 32-bit values\n\ |
316f5878 RS |
15071 | -O0 remove unneeded NOPs, do not swap branches\n\ |
15072 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
15073 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ |
15074 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ | |
15075 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
15076 | #ifdef OBJ_ELF | |
15077 | fprintf (stream, _("\ | |
15078 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
0c000745 | 15079 | -mvxworks-pic generate VxWorks position independent code\n\ |
316f5878 RS |
15080 | -non_shared do not generate position independent code\n\ |
15081 | -xgot assume a 32 bit GOT\n\ | |
dcd410fe | 15082 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
bbe506e8 | 15083 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
d821e36b | 15084 | position dependent (non shared) code\n\ |
316f5878 RS |
15085 | -mabi=ABI create ABI conformant object file for:\n")); |
15086 | ||
15087 | first = 1; | |
15088 | ||
15089 | show (stream, "32", &column, &first); | |
15090 | show (stream, "o64", &column, &first); | |
15091 | show (stream, "n32", &column, &first); | |
15092 | show (stream, "64", &column, &first); | |
15093 | show (stream, "eabi", &column, &first); | |
15094 | ||
15095 | fputc ('\n', stream); | |
15096 | ||
15097 | fprintf (stream, _("\ | |
15098 | -32 create o32 ABI object file (default)\n\ | |
15099 | -n32 create n32 ABI object file\n\ | |
15100 | -64 create 64 ABI object file\n")); | |
15101 | #endif | |
e7af610e | 15102 | } |
14e777e0 KB |
15103 | |
15104 | enum dwarf2_format | |
17a2f251 | 15105 | mips_dwarf2_format (void) |
14e777e0 | 15106 | { |
369943fe | 15107 | if (HAVE_64BIT_SYMBOLS) |
1de5b6a1 AO |
15108 | { |
15109 | #ifdef TE_IRIX | |
15110 | return dwarf2_format_64bit_irix; | |
15111 | #else | |
15112 | return dwarf2_format_64bit; | |
15113 | #endif | |
15114 | } | |
14e777e0 KB |
15115 | else |
15116 | return dwarf2_format_32bit; | |
15117 | } | |
73369e65 EC |
15118 | |
15119 | int | |
15120 | mips_dwarf2_addr_size (void) | |
15121 | { | |
369943fe | 15122 | if (HAVE_64BIT_SYMBOLS) |
73369e65 | 15123 | return 8; |
73369e65 EC |
15124 | else |
15125 | return 4; | |
15126 | } | |
5862107c EC |
15127 | |
15128 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
15129 | void | |
15130 | mips_cfi_frame_initial_instructions (void) | |
15131 | { | |
15132 | cfi_add_CFA_def_cfa_register (SP); | |
15133 | } | |
15134 | ||
707bfff6 TS |
15135 | int |
15136 | tc_mips_regname_to_dw2regnum (char *regname) | |
15137 | { | |
15138 | unsigned int regnum = -1; | |
15139 | unsigned int reg; | |
15140 | ||
15141 | if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®)) | |
15142 | regnum = reg; | |
15143 | ||
15144 | return regnum; | |
15145 | } |