Commit | Line | Data |
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252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
81912461 ILT |
2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
3 | 2003, 2004 Free Software Foundation, Inc. | |
252b5132 RH |
4 | Contributed by the OSF and Ralph Campbell. |
5 | Written by Keith Knowles and Ralph Campbell, working independently. | |
6 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
7 | Support. | |
8 | ||
9 | This file is part of GAS. | |
10 | ||
11 | GAS is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2, or (at your option) | |
14 | any later version. | |
15 | ||
16 | GAS is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with GAS; see the file COPYING. If not, write to the Free | |
23 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
24 | 02111-1307, USA. */ | |
25 | ||
26 | #include "as.h" | |
27 | #include "config.h" | |
28 | #include "subsegs.h" | |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | |
252b5132 | 31 | #include <stdarg.h> |
252b5132 RH |
32 | |
33 | #include "opcode/mips.h" | |
34 | #include "itbl-ops.h" | |
c5dd6aab | 35 | #include "dwarf2dbg.h" |
252b5132 RH |
36 | |
37 | #ifdef DEBUG | |
38 | #define DBG(x) printf x | |
39 | #else | |
40 | #define DBG(x) | |
41 | #endif | |
42 | ||
43 | #ifdef OBJ_MAYBE_ELF | |
44 | /* Clean up namespace so we can include obj-elf.h too. */ | |
17a2f251 TS |
45 | static int mips_output_flavor (void); |
46 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
47 | #undef OBJ_PROCESS_STAB |
48 | #undef OUTPUT_FLAVOR | |
49 | #undef S_GET_ALIGN | |
50 | #undef S_GET_SIZE | |
51 | #undef S_SET_ALIGN | |
52 | #undef S_SET_SIZE | |
252b5132 RH |
53 | #undef obj_frob_file |
54 | #undef obj_frob_file_after_relocs | |
55 | #undef obj_frob_symbol | |
56 | #undef obj_pop_insert | |
57 | #undef obj_sec_sym_ok_for_reloc | |
58 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
59 | ||
60 | #include "obj-elf.h" | |
61 | /* Fix any of them that we actually care about. */ | |
62 | #undef OUTPUT_FLAVOR | |
63 | #define OUTPUT_FLAVOR mips_output_flavor() | |
64 | #endif | |
65 | ||
66 | #if defined (OBJ_ELF) | |
67 | #include "elf/mips.h" | |
68 | #endif | |
69 | ||
70 | #ifndef ECOFF_DEBUGGING | |
71 | #define NO_ECOFF_DEBUGGING | |
72 | #define ECOFF_DEBUGGING 0 | |
73 | #endif | |
74 | ||
ecb4347a DJ |
75 | int mips_flag_mdebug = -1; |
76 | ||
dcd410fe RO |
77 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
78 | linker doesn't know about and discards them, but relocations against them | |
79 | remain, leading to rld crashes. */ | |
80 | #ifdef TE_IRIX | |
81 | int mips_flag_pdr = FALSE; | |
82 | #else | |
83 | int mips_flag_pdr = TRUE; | |
84 | #endif | |
85 | ||
252b5132 RH |
86 | #include "ecoff.h" |
87 | ||
88 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
89 | static char *mips_regmask_frag; | |
90 | #endif | |
91 | ||
85b51719 | 92 | #define ZERO 0 |
252b5132 RH |
93 | #define AT 1 |
94 | #define TREG 24 | |
95 | #define PIC_CALL_REG 25 | |
96 | #define KT0 26 | |
97 | #define KT1 27 | |
98 | #define GP 28 | |
99 | #define SP 29 | |
100 | #define FP 30 | |
101 | #define RA 31 | |
102 | ||
103 | #define ILLEGAL_REG (32) | |
104 | ||
105 | /* Allow override of standard little-endian ECOFF format. */ | |
106 | ||
107 | #ifndef ECOFF_LITTLE_FORMAT | |
108 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
109 | #endif | |
110 | ||
111 | extern int target_big_endian; | |
112 | ||
252b5132 RH |
113 | /* The name of the readonly data section. */ |
114 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \ | |
115 | ? ".data" \ | |
116 | : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ | |
117 | ? ".rdata" \ | |
056350c6 NC |
118 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
119 | ? ".rdata" \ | |
252b5132 RH |
120 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
121 | ? ".rodata" \ | |
122 | : (abort (), "")) | |
123 | ||
a325df1d TS |
124 | /* The ABI to use. */ |
125 | enum mips_abi_level | |
126 | { | |
127 | NO_ABI = 0, | |
128 | O32_ABI, | |
129 | O64_ABI, | |
130 | N32_ABI, | |
131 | N64_ABI, | |
132 | EABI_ABI | |
133 | }; | |
134 | ||
135 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 136 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 137 | |
143d77c5 EC |
138 | /* Whether or not we have code that can call pic code. */ |
139 | int mips_abicalls = FALSE; | |
140 | ||
252b5132 RH |
141 | /* This is the set of options which may be modified by the .set |
142 | pseudo-op. We use a struct so that .set push and .set pop are more | |
143 | reliable. */ | |
144 | ||
e972090a NC |
145 | struct mips_set_options |
146 | { | |
252b5132 RH |
147 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
148 | if it has not been initialized. Changed by `.set mipsN', and the | |
149 | -mipsN command line option, and the default CPU. */ | |
150 | int isa; | |
1f25f5d3 CD |
151 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
152 | if they have not been initialized. Changed by `.set <asename>', by | |
153 | command line options, and based on the default architecture. */ | |
154 | int ase_mips3d; | |
deec1734 | 155 | int ase_mdmx; |
252b5132 RH |
156 | /* Whether we are assembling for the mips16 processor. 0 if we are |
157 | not, 1 if we are, and -1 if the value has not been initialized. | |
158 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
159 | -nomips16 command line options, and the default CPU. */ | |
160 | int mips16; | |
161 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
162 | reorder' and `.set noreorder'. */ | |
163 | int noreorder; | |
164 | /* Non-zero if we should not permit the $at ($1) register to be used | |
165 | in instructions. Changed by `.set at' and `.set noat'. */ | |
166 | int noat; | |
167 | /* Non-zero if we should warn when a macro instruction expands into | |
168 | more than one machine instruction. Changed by `.set nomacro' and | |
169 | `.set macro'. */ | |
170 | int warn_about_macros; | |
171 | /* Non-zero if we should not move instructions. Changed by `.set | |
172 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
173 | int nomove; | |
174 | /* Non-zero if we should not optimize branches by moving the target | |
175 | of the branch into the delay slot. Actually, we don't perform | |
176 | this optimization anyhow. Changed by `.set bopt' and `.set | |
177 | nobopt'. */ | |
178 | int nobopt; | |
179 | /* Non-zero if we should not autoextend mips16 instructions. | |
180 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
181 | int noautoextend; | |
a325df1d TS |
182 | /* Restrict general purpose registers and floating point registers |
183 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
184 | is passed but can changed if the assembler code uses .set mipsN. */ | |
185 | int gp32; | |
186 | int fp32; | |
fef14a42 TS |
187 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
188 | command line option, and the default CPU. */ | |
189 | int arch; | |
252b5132 RH |
190 | }; |
191 | ||
a325df1d | 192 | /* True if -mgp32 was passed. */ |
a8e8e863 | 193 | static int file_mips_gp32 = -1; |
a325df1d TS |
194 | |
195 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 196 | static int file_mips_fp32 = -1; |
a325df1d | 197 | |
252b5132 | 198 | /* This is the struct we use to hold the current set of options. Note |
a4672219 | 199 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to |
e7af610e | 200 | -1 to indicate that they have not been initialized. */ |
252b5132 | 201 | |
e972090a NC |
202 | static struct mips_set_options mips_opts = |
203 | { | |
fef14a42 | 204 | ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN |
e7af610e | 205 | }; |
252b5132 RH |
206 | |
207 | /* These variables are filled in with the masks of registers used. | |
208 | The object format code reads them and puts them in the appropriate | |
209 | place. */ | |
210 | unsigned long mips_gprmask; | |
211 | unsigned long mips_cprmask[4]; | |
212 | ||
213 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 214 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 215 | |
a4672219 TS |
216 | /* True if -mips16 was passed or implied by arguments passed on the |
217 | command line (e.g., by -march). */ | |
218 | static int file_ase_mips16; | |
219 | ||
1f25f5d3 CD |
220 | /* True if -mips3d was passed or implied by arguments passed on the |
221 | command line (e.g., by -march). */ | |
222 | static int file_ase_mips3d; | |
223 | ||
deec1734 CD |
224 | /* True if -mdmx was passed or implied by arguments passed on the |
225 | command line (e.g., by -march). */ | |
226 | static int file_ase_mdmx; | |
227 | ||
ec68c924 | 228 | /* The argument of the -march= flag. The architecture we are assembling. */ |
fef14a42 | 229 | static int file_mips_arch = CPU_UNKNOWN; |
316f5878 | 230 | static const char *mips_arch_string; |
ec68c924 EC |
231 | |
232 | /* The argument of the -mtune= flag. The architecture for which we | |
233 | are optimizing. */ | |
234 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 235 | static const char *mips_tune_string; |
ec68c924 | 236 | |
316f5878 | 237 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
238 | static int mips_32bitmode = 0; |
239 | ||
316f5878 RS |
240 | /* True if the given ABI requires 32-bit registers. */ |
241 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
242 | ||
243 | /* Likewise 64-bit registers. */ | |
244 | #define ABI_NEEDS_64BIT_REGS(ABI) \ | |
245 | ((ABI) == N32_ABI \ | |
246 | || (ABI) == N64_ABI \ | |
247 | || (ABI) == O64_ABI) | |
248 | ||
bdaaa2e1 | 249 | /* Return true if ISA supports 64 bit gp register instructions. */ |
9ce8a5dd | 250 | #define ISA_HAS_64BIT_REGS(ISA) ( \ |
e7af610e NC |
251 | (ISA) == ISA_MIPS3 \ |
252 | || (ISA) == ISA_MIPS4 \ | |
84ea6cf2 | 253 | || (ISA) == ISA_MIPS5 \ |
d1cf510e | 254 | || (ISA) == ISA_MIPS64 \ |
5f74bc13 | 255 | || (ISA) == ISA_MIPS64R2 \ |
9ce8a5dd GRK |
256 | ) |
257 | ||
af7ee8bf CD |
258 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
259 | instructions. */ | |
260 | #define ISA_HAS_DROR(ISA) ( \ | |
5f74bc13 | 261 | (ISA) == ISA_MIPS64R2 \ |
af7ee8bf CD |
262 | ) |
263 | ||
264 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
265 | instructions. */ | |
266 | #define ISA_HAS_ROR(ISA) ( \ | |
267 | (ISA) == ISA_MIPS32R2 \ | |
5f74bc13 | 268 | || (ISA) == ISA_MIPS64R2 \ |
af7ee8bf CD |
269 | ) |
270 | ||
e013f690 | 271 | #define HAVE_32BIT_GPRS \ |
316f5878 | 272 | (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 273 | |
e013f690 | 274 | #define HAVE_32BIT_FPRS \ |
316f5878 | 275 | (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 RS |
276 | |
277 | #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS) | |
278 | #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS) | |
279 | ||
316f5878 | 280 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 281 | |
316f5878 | 282 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 TS |
283 | |
284 | /* We can only have 64bit addresses if the object file format | |
285 | supports it. */ | |
afdbd6d0 CD |
286 | #define HAVE_32BIT_ADDRESSES \ |
287 | (HAVE_32BIT_GPRS \ | |
288 | || ((bfd_arch_bits_per_address (stdoutput) == 32 \ | |
289 | || ! HAVE_64BIT_OBJECTS) \ | |
290 | && mips_pic != EMBEDDED_PIC)) | |
e013f690 TS |
291 | |
292 | #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES) | |
ca4e0257 | 293 | |
b7c7d6c1 TS |
294 | /* Addresses are loaded in different ways, depending on the address size |
295 | in use. The n32 ABI Documentation also mandates the use of additions | |
296 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 297 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 298 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
299 | |
300 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 301 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
302 | |
303 | #define ADDRESS_LOAD_INSN \ | |
304 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
305 | ||
306 | #define ADDRESS_STORE_INSN \ | |
307 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
308 | ||
a4672219 | 309 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
310 | #define CPU_HAS_MIPS16(cpu) \ |
311 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
312 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 313 | |
1f25f5d3 CD |
314 | /* Return true if the given CPU supports the MIPS3D ASE. */ |
315 | #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \ | |
316 | ) | |
317 | ||
deec1734 | 318 | /* Return true if the given CPU supports the MDMX ASE. */ |
b34976b6 | 319 | #define CPU_HAS_MDMX(cpu) (FALSE \ |
deec1734 CD |
320 | ) |
321 | ||
60b63b72 RS |
322 | /* True if CPU has a dror instruction. */ |
323 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
324 | ||
325 | /* True if CPU has a ror instruction. */ | |
326 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
327 | ||
c8978940 CD |
328 | /* True if mflo and mfhi can be immediately followed by instructions |
329 | which write to the HI and LO registers. | |
330 | ||
331 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
332 | (at least) two instructions between the reads of HI/LO and | |
333 | instructions which write them, and later ISAs do not. Contradicting | |
334 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
335 | the UM for the NEC Vr5000) document needing the instructions between | |
336 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
337 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
338 | earlier-ISA CPUs for which CPU documentation declares that the | |
339 | instructions are really interlocked. */ | |
340 | #define hilo_interlocks \ | |
341 | (mips_opts.isa == ISA_MIPS32 \ | |
342 | || mips_opts.isa == ISA_MIPS32R2 \ | |
343 | || mips_opts.isa == ISA_MIPS64 \ | |
344 | || mips_opts.isa == ISA_MIPS64R2 \ | |
345 | || mips_opts.arch == CPU_R4010 \ | |
346 | || mips_opts.arch == CPU_R10000 \ | |
347 | || mips_opts.arch == CPU_R12000 \ | |
348 | || mips_opts.arch == CPU_RM7000 \ | |
c8978940 CD |
349 | || mips_opts.arch == CPU_VR5500 \ |
350 | ) | |
252b5132 RH |
351 | |
352 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
353 | from the GPRs after they are loaded from memory, and thus does not |
354 | require nops to be inserted. This applies to instructions marked | |
355 | INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA | |
356 | level I. */ | |
252b5132 | 357 | #define gpr_interlocks \ |
e7af610e | 358 | (mips_opts.isa != ISA_MIPS1 \ |
fef14a42 | 359 | || mips_opts.arch == CPU_R3900) |
252b5132 | 360 | |
81912461 ILT |
361 | /* Whether the processor uses hardware interlocks to avoid delays |
362 | required by coprocessor instructions, and thus does not require | |
363 | nops to be inserted. This applies to instructions marked | |
364 | INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays | |
365 | between instructions marked INSN_WRITE_COND_CODE and ones marked | |
366 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA | |
367 | levels I, II, and III. */ | |
bdaaa2e1 | 368 | /* Itbl support may require additional care here. */ |
81912461 ILT |
369 | #define cop_interlocks \ |
370 | ((mips_opts.isa != ISA_MIPS1 \ | |
371 | && mips_opts.isa != ISA_MIPS2 \ | |
372 | && mips_opts.isa != ISA_MIPS3) \ | |
373 | || mips_opts.arch == CPU_R4300 \ | |
81912461 ILT |
374 | ) |
375 | ||
376 | /* Whether the processor uses hardware interlocks to protect reads | |
377 | from coprocessor registers after they are loaded from memory, and | |
378 | thus does not require nops to be inserted. This applies to | |
379 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
380 | requires at MIPS ISA level I. */ | |
381 | #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1) | |
252b5132 | 382 | |
6b76fefe CM |
383 | /* Is this a mfhi or mflo instruction? */ |
384 | #define MF_HILO_INSN(PINFO) \ | |
385 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) | |
386 | ||
252b5132 RH |
387 | /* MIPS PIC level. */ |
388 | ||
a161fe53 | 389 | enum mips_pic_level mips_pic; |
252b5132 | 390 | |
c9914766 | 391 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 392 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 393 | static int mips_big_got = 0; |
252b5132 RH |
394 | |
395 | /* 1 if trap instructions should used for overflow rather than break | |
396 | instructions. */ | |
c9914766 | 397 | static int mips_trap = 0; |
252b5132 | 398 | |
119d663a | 399 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 400 | by assembling two single width halves into two single width floating |
119d663a NC |
401 | point registers which just happen to alias the double width destination |
402 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 403 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
404 | automatically at assemble time. */ |
405 | static int mips_disable_float_construction; | |
406 | ||
252b5132 RH |
407 | /* Non-zero if any .set noreorder directives were used. */ |
408 | ||
409 | static int mips_any_noreorder; | |
410 | ||
6b76fefe CM |
411 | /* Non-zero if nops should be inserted when the register referenced in |
412 | an mfhi/mflo instruction is read in the next two instructions. */ | |
413 | static int mips_7000_hilo_fix; | |
414 | ||
252b5132 | 415 | /* The size of the small data section. */ |
156c2f8b | 416 | static unsigned int g_switch_value = 8; |
252b5132 RH |
417 | /* Whether the -G option was used. */ |
418 | static int g_switch_seen = 0; | |
419 | ||
420 | #define N_RMASK 0xc4 | |
421 | #define N_VFP 0xd4 | |
422 | ||
423 | /* If we can determine in advance that GP optimization won't be | |
424 | possible, we can skip the relaxation stuff that tries to produce | |
425 | GP-relative references. This makes delay slot optimization work | |
426 | better. | |
427 | ||
428 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
429 | gcc output. It needs to guess right for gcc, otherwise gcc |
430 | will put what it thinks is a GP-relative instruction in a branch | |
431 | delay slot. | |
252b5132 RH |
432 | |
433 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
434 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 435 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
436 | |
437 | /* handle of the OPCODE hash table */ | |
438 | static struct hash_control *op_hash = NULL; | |
439 | ||
440 | /* The opcode hash table we use for the mips16. */ | |
441 | static struct hash_control *mips16_op_hash = NULL; | |
442 | ||
443 | /* This array holds the chars that always start a comment. If the | |
444 | pre-processor is disabled, these aren't very useful */ | |
445 | const char comment_chars[] = "#"; | |
446 | ||
447 | /* This array holds the chars that only start a comment at the beginning of | |
448 | a line. If the line seems to have the form '# 123 filename' | |
449 | .line and .file directives will appear in the pre-processed output */ | |
450 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
451 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 452 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
453 | /* Also note that C style comments are always supported. */ |
454 | const char line_comment_chars[] = "#"; | |
455 | ||
bdaaa2e1 | 456 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 457 | const char line_separator_chars[] = ";"; |
252b5132 RH |
458 | |
459 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
460 | const char EXP_CHARS[] = "eE"; | |
461 | ||
462 | /* Chars that mean this number is a floating point constant */ | |
463 | /* As in 0f12.456 */ | |
464 | /* or 0d1.2345e12 */ | |
465 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
466 | ||
467 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
468 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
469 | but nothing is ideal around here. | |
470 | */ | |
471 | ||
472 | static char *insn_error; | |
473 | ||
474 | static int auto_align = 1; | |
475 | ||
476 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
477 | offset in the stack frame from which to restore the $gp register. | |
478 | This is set by the .cprestore pseudo-op, and saved in this | |
479 | variable. */ | |
480 | static offsetT mips_cprestore_offset = -1; | |
481 | ||
67c1ffbe | 482 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 483 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 484 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
485 | static offsetT mips_cpreturn_offset = -1; |
486 | static int mips_cpreturn_register = -1; | |
487 | static int mips_gp_register = GP; | |
def2e0dd | 488 | static int mips_gprel_offset = 0; |
6478892d | 489 | |
7a621144 DJ |
490 | /* Whether mips_cprestore_offset has been set in the current function |
491 | (or whether it has already been warned about, if not). */ | |
492 | static int mips_cprestore_valid = 0; | |
493 | ||
252b5132 RH |
494 | /* This is the register which holds the stack frame, as set by the |
495 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
496 | static int mips_frame_reg = SP; | |
497 | ||
7a621144 DJ |
498 | /* Whether mips_frame_reg has been set in the current function |
499 | (or whether it has already been warned about, if not). */ | |
500 | static int mips_frame_reg_valid = 0; | |
501 | ||
252b5132 RH |
502 | /* To output NOP instructions correctly, we need to keep information |
503 | about the previous two instructions. */ | |
504 | ||
505 | /* Whether we are optimizing. The default value of 2 means to remove | |
506 | unneeded NOPs and swap branch instructions when possible. A value | |
507 | of 1 means to not swap branches. A value of 0 means to always | |
508 | insert NOPs. */ | |
509 | static int mips_optimize = 2; | |
510 | ||
511 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
512 | equivalent to seeing no -g option at all. */ | |
513 | static int mips_debug = 0; | |
514 | ||
515 | /* The previous instruction. */ | |
516 | static struct mips_cl_insn prev_insn; | |
517 | ||
518 | /* The instruction before prev_insn. */ | |
519 | static struct mips_cl_insn prev_prev_insn; | |
520 | ||
521 | /* If we don't want information for prev_insn or prev_prev_insn, we | |
522 | point the insn_mo field at this dummy integer. */ | |
43841e91 | 523 | static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 }; |
252b5132 RH |
524 | |
525 | /* Non-zero if prev_insn is valid. */ | |
526 | static int prev_insn_valid; | |
527 | ||
528 | /* The frag for the previous instruction. */ | |
529 | static struct frag *prev_insn_frag; | |
530 | ||
531 | /* The offset into prev_insn_frag for the previous instruction. */ | |
532 | static long prev_insn_where; | |
533 | ||
534 | /* The reloc type for the previous instruction, if any. */ | |
f6688943 | 535 | static bfd_reloc_code_real_type prev_insn_reloc_type[3]; |
252b5132 RH |
536 | |
537 | /* The reloc for the previous instruction, if any. */ | |
f6688943 | 538 | static fixS *prev_insn_fixp[3]; |
252b5132 RH |
539 | |
540 | /* Non-zero if the previous instruction was in a delay slot. */ | |
541 | static int prev_insn_is_delay_slot; | |
542 | ||
543 | /* Non-zero if the previous instruction was in a .set noreorder. */ | |
544 | static int prev_insn_unreordered; | |
545 | ||
546 | /* Non-zero if the previous instruction uses an extend opcode (if | |
547 | mips16). */ | |
548 | static int prev_insn_extended; | |
549 | ||
550 | /* Non-zero if the previous previous instruction was in a .set | |
551 | noreorder. */ | |
552 | static int prev_prev_insn_unreordered; | |
553 | ||
554 | /* If this is set, it points to a frag holding nop instructions which | |
555 | were inserted before the start of a noreorder section. If those | |
556 | nops turn out to be unnecessary, the size of the frag can be | |
557 | decreased. */ | |
558 | static fragS *prev_nop_frag; | |
559 | ||
560 | /* The number of nop instructions we created in prev_nop_frag. */ | |
561 | static int prev_nop_frag_holds; | |
562 | ||
563 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 564 | prev_nop_frag. */ |
252b5132 RH |
565 | static int prev_nop_frag_required; |
566 | ||
567 | /* The number of instructions we've seen since prev_nop_frag. */ | |
568 | static int prev_nop_frag_since; | |
569 | ||
570 | /* For ECOFF and ELF, relocations against symbols are done in two | |
571 | parts, with a HI relocation and a LO relocation. Each relocation | |
572 | has only 16 bits of space to store an addend. This means that in | |
573 | order for the linker to handle carries correctly, it must be able | |
574 | to locate both the HI and the LO relocation. This means that the | |
575 | relocations must appear in order in the relocation table. | |
576 | ||
577 | In order to implement this, we keep track of each unmatched HI | |
578 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 579 | corresponding LO relocation. */ |
252b5132 | 580 | |
e972090a NC |
581 | struct mips_hi_fixup |
582 | { | |
252b5132 RH |
583 | /* Next HI fixup. */ |
584 | struct mips_hi_fixup *next; | |
585 | /* This fixup. */ | |
586 | fixS *fixp; | |
587 | /* The section this fixup is in. */ | |
588 | segT seg; | |
589 | }; | |
590 | ||
591 | /* The list of unmatched HI relocs. */ | |
592 | ||
593 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
594 | ||
64bdfcaf RS |
595 | /* The frag containing the last explicit relocation operator. |
596 | Null if explicit relocations have not been used. */ | |
597 | ||
598 | static fragS *prev_reloc_op_frag; | |
599 | ||
252b5132 RH |
600 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
601 | ||
602 | #define X ILLEGAL_REG | |
e972090a NC |
603 | static const int mips32_to_16_reg_map[] = |
604 | { | |
252b5132 RH |
605 | X, X, 2, 3, 4, 5, 6, 7, |
606 | X, X, X, X, X, X, X, X, | |
607 | 0, 1, X, X, X, X, X, X, | |
608 | X, X, X, X, X, X, X, X | |
609 | }; | |
610 | #undef X | |
611 | ||
612 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
613 | ||
e972090a NC |
614 | static const unsigned int mips16_to_32_reg_map[] = |
615 | { | |
252b5132 RH |
616 | 16, 17, 2, 3, 4, 5, 6, 7 |
617 | }; | |
60b63b72 | 618 | |
d766e8ec | 619 | static int mips_fix_vr4120; |
4a6a3df4 AO |
620 | |
621 | /* We don't relax branches by default, since this causes us to expand | |
622 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
623 | fail to compute the offset before expanding the macro to the most | |
624 | efficient expansion. */ | |
625 | ||
626 | static int mips_relax_branch; | |
252b5132 | 627 | \f |
4d7206a2 RS |
628 | /* The expansion of many macros depends on the type of symbol that |
629 | they refer to. For example, when generating position-dependent code, | |
630 | a macro that refers to a symbol may have two different expansions, | |
631 | one which uses GP-relative addresses and one which uses absolute | |
632 | addresses. When generating SVR4-style PIC, a macro may have | |
633 | different expansions for local and global symbols. | |
634 | ||
635 | We handle these situations by generating both sequences and putting | |
636 | them in variant frags. In position-dependent code, the first sequence | |
637 | will be the GP-relative one and the second sequence will be the | |
638 | absolute one. In SVR4 PIC, the first sequence will be for global | |
639 | symbols and the second will be for local symbols. | |
640 | ||
584892a6 RS |
641 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
642 | SECOND are the lengths of the two sequences in bytes. These fields | |
643 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
644 | the subtype has the following flags: | |
4d7206a2 | 645 | |
584892a6 RS |
646 | RELAX_USE_SECOND |
647 | Set if it has been decided that we should use the second | |
648 | sequence instead of the first. | |
649 | ||
650 | RELAX_SECOND_LONGER | |
651 | Set in the first variant frag if the macro's second implementation | |
652 | is longer than its first. This refers to the macro as a whole, | |
653 | not an individual relaxation. | |
654 | ||
655 | RELAX_NOMACRO | |
656 | Set in the first variant frag if the macro appeared in a .set nomacro | |
657 | block and if one alternative requires a warning but the other does not. | |
658 | ||
659 | RELAX_DELAY_SLOT | |
660 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
661 | delay slot. | |
4d7206a2 RS |
662 | |
663 | The frag's "opcode" points to the first fixup for relaxable code. | |
664 | ||
665 | Relaxable macros are generated using a sequence such as: | |
666 | ||
667 | relax_start (SYMBOL); | |
668 | ... generate first expansion ... | |
669 | relax_switch (); | |
670 | ... generate second expansion ... | |
671 | relax_end (); | |
672 | ||
673 | The code and fixups for the unwanted alternative are discarded | |
674 | by md_convert_frag. */ | |
584892a6 | 675 | #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) |
4d7206a2 | 676 | |
584892a6 RS |
677 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
678 | #define RELAX_SECOND(X) ((X) & 0xff) | |
679 | #define RELAX_USE_SECOND 0x10000 | |
680 | #define RELAX_SECOND_LONGER 0x20000 | |
681 | #define RELAX_NOMACRO 0x40000 | |
682 | #define RELAX_DELAY_SLOT 0x80000 | |
252b5132 | 683 | |
4a6a3df4 AO |
684 | /* Branch without likely bit. If label is out of range, we turn: |
685 | ||
686 | beq reg1, reg2, label | |
687 | delay slot | |
688 | ||
689 | into | |
690 | ||
691 | bne reg1, reg2, 0f | |
692 | nop | |
693 | j label | |
694 | 0: delay slot | |
695 | ||
696 | with the following opcode replacements: | |
697 | ||
698 | beq <-> bne | |
699 | blez <-> bgtz | |
700 | bltz <-> bgez | |
701 | bc1f <-> bc1t | |
702 | ||
703 | bltzal <-> bgezal (with jal label instead of j label) | |
704 | ||
705 | Even though keeping the delay slot instruction in the delay slot of | |
706 | the branch would be more efficient, it would be very tricky to do | |
707 | correctly, because we'd have to introduce a variable frag *after* | |
708 | the delay slot instruction, and expand that instead. Let's do it | |
709 | the easy way for now, even if the branch-not-taken case now costs | |
710 | one additional instruction. Out-of-range branches are not supposed | |
711 | to be common, anyway. | |
712 | ||
713 | Branch likely. If label is out of range, we turn: | |
714 | ||
715 | beql reg1, reg2, label | |
716 | delay slot (annulled if branch not taken) | |
717 | ||
718 | into | |
719 | ||
720 | beql reg1, reg2, 1f | |
721 | nop | |
722 | beql $0, $0, 2f | |
723 | nop | |
724 | 1: j[al] label | |
725 | delay slot (executed only if branch taken) | |
726 | 2: | |
727 | ||
728 | It would be possible to generate a shorter sequence by losing the | |
729 | likely bit, generating something like: | |
b34976b6 | 730 | |
4a6a3df4 AO |
731 | bne reg1, reg2, 0f |
732 | nop | |
733 | j[al] label | |
734 | delay slot (executed only if branch taken) | |
735 | 0: | |
736 | ||
737 | beql -> bne | |
738 | bnel -> beq | |
739 | blezl -> bgtz | |
740 | bgtzl -> blez | |
741 | bltzl -> bgez | |
742 | bgezl -> bltz | |
743 | bc1fl -> bc1t | |
744 | bc1tl -> bc1f | |
745 | ||
746 | bltzall -> bgezal (with jal label instead of j label) | |
747 | bgezall -> bltzal (ditto) | |
748 | ||
749 | ||
750 | but it's not clear that it would actually improve performance. */ | |
af6ae2ad | 751 | #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \ |
4a6a3df4 AO |
752 | ((relax_substateT) \ |
753 | (0xc0000000 \ | |
754 | | ((toofar) ? 1 : 0) \ | |
755 | | ((link) ? 2 : 0) \ | |
756 | | ((likely) ? 4 : 0) \ | |
af6ae2ad | 757 | | ((uncond) ? 8 : 0))) |
4a6a3df4 | 758 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
4a6a3df4 AO |
759 | #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0) |
760 | #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0) | |
761 | #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0) | |
ae6063d4 | 762 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0) |
4a6a3df4 | 763 | |
252b5132 RH |
764 | /* For mips16 code, we use an entirely different form of relaxation. |
765 | mips16 supports two versions of most instructions which take | |
766 | immediate values: a small one which takes some small value, and a | |
767 | larger one which takes a 16 bit value. Since branches also follow | |
768 | this pattern, relaxing these values is required. | |
769 | ||
770 | We can assemble both mips16 and normal MIPS code in a single | |
771 | object. Therefore, we need to support this type of relaxation at | |
772 | the same time that we support the relaxation described above. We | |
773 | use the high bit of the subtype field to distinguish these cases. | |
774 | ||
775 | The information we store for this type of relaxation is the | |
776 | argument code found in the opcode file for this relocation, whether | |
777 | the user explicitly requested a small or extended form, and whether | |
778 | the relocation is in a jump or jal delay slot. That tells us the | |
779 | size of the value, and how it should be stored. We also store | |
780 | whether the fragment is considered to be extended or not. We also | |
781 | store whether this is known to be a branch to a different section, | |
782 | whether we have tried to relax this frag yet, and whether we have | |
783 | ever extended a PC relative fragment because of a shift count. */ | |
784 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
785 | (0x80000000 \ | |
786 | | ((type) & 0xff) \ | |
787 | | ((small) ? 0x100 : 0) \ | |
788 | | ((ext) ? 0x200 : 0) \ | |
789 | | ((dslot) ? 0x400 : 0) \ | |
790 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 791 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
792 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
793 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
794 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
795 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
796 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
797 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
798 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
799 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
800 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
801 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
802 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 CD |
803 | |
804 | /* Is the given value a sign-extended 32-bit value? */ | |
805 | #define IS_SEXT_32BIT_NUM(x) \ | |
806 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
807 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
808 | ||
809 | /* Is the given value a sign-extended 16-bit value? */ | |
810 | #define IS_SEXT_16BIT_NUM(x) \ | |
811 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
812 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
813 | ||
4d7206a2 RS |
814 | \f |
815 | /* Global variables used when generating relaxable macros. See the | |
816 | comment above RELAX_ENCODE for more details about how relaxation | |
817 | is used. */ | |
818 | static struct { | |
819 | /* 0 if we're not emitting a relaxable macro. | |
820 | 1 if we're emitting the first of the two relaxation alternatives. | |
821 | 2 if we're emitting the second alternative. */ | |
822 | int sequence; | |
823 | ||
824 | /* The first relaxable fixup in the current frag. (In other words, | |
825 | the first fixup that refers to relaxable code.) */ | |
826 | fixS *first_fixup; | |
827 | ||
828 | /* sizes[0] says how many bytes of the first alternative are stored in | |
829 | the current frag. Likewise sizes[1] for the second alternative. */ | |
830 | unsigned int sizes[2]; | |
831 | ||
832 | /* The symbol on which the choice of sequence depends. */ | |
833 | symbolS *symbol; | |
834 | } mips_relax; | |
252b5132 | 835 | \f |
584892a6 RS |
836 | /* Global variables used to decide whether a macro needs a warning. */ |
837 | static struct { | |
838 | /* True if the macro is in a branch delay slot. */ | |
839 | bfd_boolean delay_slot_p; | |
840 | ||
841 | /* For relaxable macros, sizes[0] is the length of the first alternative | |
842 | in bytes and sizes[1] is the length of the second alternative. | |
843 | For non-relaxable macros, both elements give the length of the | |
844 | macro in bytes. */ | |
845 | unsigned int sizes[2]; | |
846 | ||
847 | /* The first variant frag for this macro. */ | |
848 | fragS *first_frag; | |
849 | } mips_macro_warning; | |
850 | \f | |
252b5132 RH |
851 | /* Prototypes for static functions. */ |
852 | ||
17a2f251 | 853 | #define internalError() \ |
252b5132 | 854 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) |
252b5132 RH |
855 | |
856 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
857 | ||
b34976b6 | 858 | static void append_insn |
4d7206a2 | 859 | (struct mips_cl_insn *ip, expressionS *p, bfd_reloc_code_real_type *r); |
17a2f251 | 860 | static void mips_no_prev_insn (int); |
b34976b6 | 861 | static void mips16_macro_build |
67c0d1eb RS |
862 | (expressionS *, const char *, const char *, va_list); |
863 | static void load_register (int, expressionS *, int); | |
584892a6 RS |
864 | static void macro_start (void); |
865 | static void macro_end (void); | |
17a2f251 TS |
866 | static void macro (struct mips_cl_insn * ip); |
867 | static void mips16_macro (struct mips_cl_insn * ip); | |
252b5132 | 868 | #ifdef LOSING_COMPILER |
17a2f251 | 869 | static void macro2 (struct mips_cl_insn * ip); |
252b5132 | 870 | #endif |
17a2f251 TS |
871 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
872 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 873 | static void mips16_immed |
17a2f251 TS |
874 | (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean, |
875 | unsigned long *, bfd_boolean *, unsigned short *); | |
5e0116d5 | 876 | static size_t my_getSmallExpression |
17a2f251 TS |
877 | (expressionS *, bfd_reloc_code_real_type *, char *); |
878 | static void my_getExpression (expressionS *, char *); | |
879 | static void s_align (int); | |
880 | static void s_change_sec (int); | |
881 | static void s_change_section (int); | |
882 | static void s_cons (int); | |
883 | static void s_float_cons (int); | |
884 | static void s_mips_globl (int); | |
885 | static void s_option (int); | |
886 | static void s_mipsset (int); | |
887 | static void s_abicalls (int); | |
888 | static void s_cpload (int); | |
889 | static void s_cpsetup (int); | |
890 | static void s_cplocal (int); | |
891 | static void s_cprestore (int); | |
892 | static void s_cpreturn (int); | |
893 | static void s_gpvalue (int); | |
894 | static void s_gpword (int); | |
895 | static void s_gpdword (int); | |
896 | static void s_cpadd (int); | |
897 | static void s_insn (int); | |
898 | static void md_obj_begin (void); | |
899 | static void md_obj_end (void); | |
900 | static void s_mips_ent (int); | |
901 | static void s_mips_end (int); | |
902 | static void s_mips_frame (int); | |
903 | static void s_mips_mask (int reg_type); | |
904 | static void s_mips_stab (int); | |
905 | static void s_mips_weakext (int); | |
906 | static void s_mips_file (int); | |
907 | static void s_mips_loc (int); | |
908 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 909 | static int relaxed_branch_length (fragS *, asection *, int); |
17a2f251 | 910 | static int validate_mips_insn (const struct mips_opcode *); |
e7af610e NC |
911 | |
912 | /* Table and functions used to map between CPU/ISA names, and | |
913 | ISA levels, and CPU numbers. */ | |
914 | ||
e972090a NC |
915 | struct mips_cpu_info |
916 | { | |
e7af610e NC |
917 | const char *name; /* CPU or ISA name. */ |
918 | int is_isa; /* Is this an ISA? (If 0, a CPU.) */ | |
919 | int isa; /* ISA level. */ | |
920 | int cpu; /* CPU number (default CPU if ISA). */ | |
921 | }; | |
922 | ||
17a2f251 TS |
923 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
924 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
925 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 RH |
926 | \f |
927 | /* Pseudo-op table. | |
928 | ||
929 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
930 | should be defined here, but are currently unsupported: .alias, | |
931 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
932 | ||
933 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
934 | specific to the type of debugging information being generated, and | |
935 | should be defined by the object format: .aent, .begin, .bend, | |
936 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
937 | .vreg. | |
938 | ||
939 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
940 | not MIPS CPU specific, but are also not specific to the object file | |
941 | format. This file is probably the best place to define them, but | |
942 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
943 | .struct. */ | |
944 | ||
e972090a NC |
945 | static const pseudo_typeS mips_pseudo_table[] = |
946 | { | |
beae10d5 | 947 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
948 | {"option", s_option, 0}, |
949 | {"set", s_mipsset, 0}, | |
950 | {"rdata", s_change_sec, 'r'}, | |
951 | {"sdata", s_change_sec, 's'}, | |
952 | {"livereg", s_ignore, 0}, | |
953 | {"abicalls", s_abicalls, 0}, | |
954 | {"cpload", s_cpload, 0}, | |
6478892d TS |
955 | {"cpsetup", s_cpsetup, 0}, |
956 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 957 | {"cprestore", s_cprestore, 0}, |
6478892d TS |
958 | {"cpreturn", s_cpreturn, 0}, |
959 | {"gpvalue", s_gpvalue, 0}, | |
252b5132 | 960 | {"gpword", s_gpword, 0}, |
10181a0d | 961 | {"gpdword", s_gpdword, 0}, |
252b5132 RH |
962 | {"cpadd", s_cpadd, 0}, |
963 | {"insn", s_insn, 0}, | |
964 | ||
beae10d5 | 965 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 RH |
966 | chips. */ |
967 | {"asciiz", stringer, 1}, | |
968 | {"bss", s_change_sec, 'b'}, | |
969 | {"err", s_err, 0}, | |
970 | {"half", s_cons, 1}, | |
971 | {"dword", s_cons, 3}, | |
972 | {"weakext", s_mips_weakext, 0}, | |
973 | ||
beae10d5 | 974 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
975 | here for one reason or another. */ |
976 | {"align", s_align, 0}, | |
977 | {"byte", s_cons, 0}, | |
978 | {"data", s_change_sec, 'd'}, | |
979 | {"double", s_float_cons, 'd'}, | |
980 | {"float", s_float_cons, 'f'}, | |
981 | {"globl", s_mips_globl, 0}, | |
982 | {"global", s_mips_globl, 0}, | |
983 | {"hword", s_cons, 1}, | |
984 | {"int", s_cons, 2}, | |
985 | {"long", s_cons, 2}, | |
986 | {"octa", s_cons, 4}, | |
987 | {"quad", s_cons, 3}, | |
cca86cc8 | 988 | {"section", s_change_section, 0}, |
252b5132 RH |
989 | {"short", s_cons, 1}, |
990 | {"single", s_float_cons, 'f'}, | |
991 | {"stabn", s_mips_stab, 'n'}, | |
992 | {"text", s_change_sec, 't'}, | |
993 | {"word", s_cons, 2}, | |
add56521 | 994 | |
add56521 | 995 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 996 | |
43841e91 | 997 | { NULL, NULL, 0 }, |
252b5132 RH |
998 | }; |
999 | ||
e972090a NC |
1000 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1001 | { | |
beae10d5 KH |
1002 | /* These pseudo-ops should be defined by the object file format. |
1003 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1004 | {"aent", s_mips_ent, 1}, |
1005 | {"bgnb", s_ignore, 0}, | |
1006 | {"end", s_mips_end, 0}, | |
1007 | {"endb", s_ignore, 0}, | |
1008 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1009 | {"file", s_mips_file, 0}, |
252b5132 RH |
1010 | {"fmask", s_mips_mask, 'F'}, |
1011 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1012 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1013 | {"mask", s_mips_mask, 'R'}, |
1014 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1015 | { NULL, NULL, 0 }, |
252b5132 RH |
1016 | }; |
1017 | ||
17a2f251 | 1018 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1019 | |
1020 | void | |
17a2f251 | 1021 | mips_pop_insert (void) |
252b5132 RH |
1022 | { |
1023 | pop_insert (mips_pseudo_table); | |
1024 | if (! ECOFF_DEBUGGING) | |
1025 | pop_insert (mips_nonecoff_pseudo_table); | |
1026 | } | |
1027 | \f | |
1028 | /* Symbols labelling the current insn. */ | |
1029 | ||
e972090a NC |
1030 | struct insn_label_list |
1031 | { | |
252b5132 RH |
1032 | struct insn_label_list *next; |
1033 | symbolS *label; | |
1034 | }; | |
1035 | ||
1036 | static struct insn_label_list *insn_labels; | |
1037 | static struct insn_label_list *free_insn_labels; | |
1038 | ||
17a2f251 | 1039 | static void mips_clear_insn_labels (void); |
252b5132 RH |
1040 | |
1041 | static inline void | |
17a2f251 | 1042 | mips_clear_insn_labels (void) |
252b5132 RH |
1043 | { |
1044 | register struct insn_label_list **pl; | |
1045 | ||
1046 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1047 | ; | |
1048 | *pl = insn_labels; | |
1049 | insn_labels = NULL; | |
1050 | } | |
1051 | \f | |
1052 | static char *expr_end; | |
1053 | ||
1054 | /* Expressions which appear in instructions. These are set by | |
1055 | mips_ip. */ | |
1056 | ||
1057 | static expressionS imm_expr; | |
5f74bc13 | 1058 | static expressionS imm2_expr; |
252b5132 RH |
1059 | static expressionS offset_expr; |
1060 | ||
1061 | /* Relocs associated with imm_expr and offset_expr. */ | |
1062 | ||
f6688943 TS |
1063 | static bfd_reloc_code_real_type imm_reloc[3] |
1064 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1065 | static bfd_reloc_code_real_type offset_reloc[3] | |
1066 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1067 | |
252b5132 RH |
1068 | /* These are set by mips16_ip if an explicit extension is used. */ |
1069 | ||
b34976b6 | 1070 | static bfd_boolean mips16_small, mips16_ext; |
252b5132 | 1071 | |
7ed4a06a | 1072 | #ifdef OBJ_ELF |
ecb4347a DJ |
1073 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1074 | ECOFF debugging. */ | |
252b5132 RH |
1075 | |
1076 | static segT pdr_seg; | |
7ed4a06a | 1077 | #endif |
252b5132 | 1078 | |
e013f690 TS |
1079 | /* The default target format to use. */ |
1080 | ||
1081 | const char * | |
17a2f251 | 1082 | mips_target_format (void) |
e013f690 TS |
1083 | { |
1084 | switch (OUTPUT_FLAVOR) | |
1085 | { | |
1086 | case bfd_target_aout_flavour: | |
1087 | return target_big_endian ? "a.out-mips-big" : "a.out-mips-little"; | |
1088 | case bfd_target_ecoff_flavour: | |
1089 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1090 | case bfd_target_coff_flavour: | |
1091 | return "pe-mips"; | |
1092 | case bfd_target_elf_flavour: | |
1093 | #ifdef TE_TMIPS | |
cfe86eaa | 1094 | /* This is traditional mips. */ |
e013f690 | 1095 | return (target_big_endian |
cfe86eaa TS |
1096 | ? (HAVE_64BIT_OBJECTS |
1097 | ? "elf64-tradbigmips" | |
1098 | : (HAVE_NEWABI | |
1099 | ? "elf32-ntradbigmips" : "elf32-tradbigmips")) | |
1100 | : (HAVE_64BIT_OBJECTS | |
1101 | ? "elf64-tradlittlemips" | |
1102 | : (HAVE_NEWABI | |
1103 | ? "elf32-ntradlittlemips" : "elf32-tradlittlemips"))); | |
e013f690 TS |
1104 | #else |
1105 | return (target_big_endian | |
cfe86eaa TS |
1106 | ? (HAVE_64BIT_OBJECTS |
1107 | ? "elf64-bigmips" | |
1108 | : (HAVE_NEWABI | |
1109 | ? "elf32-nbigmips" : "elf32-bigmips")) | |
1110 | : (HAVE_64BIT_OBJECTS | |
1111 | ? "elf64-littlemips" | |
1112 | : (HAVE_NEWABI | |
1113 | ? "elf32-nlittlemips" : "elf32-littlemips"))); | |
e013f690 TS |
1114 | #endif |
1115 | default: | |
1116 | abort (); | |
1117 | return NULL; | |
1118 | } | |
1119 | } | |
1120 | ||
156c2f8b NC |
1121 | /* This function is called once, at assembler startup time. It should |
1122 | set up all the tables, etc. that the MD part of the assembler will need. */ | |
1123 | ||
252b5132 | 1124 | void |
17a2f251 | 1125 | md_begin (void) |
252b5132 | 1126 | { |
252b5132 | 1127 | register const char *retval = NULL; |
156c2f8b | 1128 | int i = 0; |
252b5132 | 1129 | int broken = 0; |
1f25f5d3 | 1130 | |
fef14a42 | 1131 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) |
252b5132 RH |
1132 | as_warn (_("Could not set architecture and machine")); |
1133 | ||
252b5132 RH |
1134 | op_hash = hash_new (); |
1135 | ||
1136 | for (i = 0; i < NUMOPCODES;) | |
1137 | { | |
1138 | const char *name = mips_opcodes[i].name; | |
1139 | ||
17a2f251 | 1140 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
1141 | if (retval != NULL) |
1142 | { | |
1143 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
1144 | mips_opcodes[i].name, retval); | |
1145 | /* Probably a memory allocation problem? Give up now. */ | |
1146 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1147 | } | |
1148 | do | |
1149 | { | |
1150 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
1151 | { | |
1152 | if (!validate_mips_insn (&mips_opcodes[i])) | |
1153 | broken = 1; | |
1154 | } | |
1155 | ++i; | |
1156 | } | |
1157 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
1158 | } | |
1159 | ||
1160 | mips16_op_hash = hash_new (); | |
1161 | ||
1162 | i = 0; | |
1163 | while (i < bfd_mips16_num_opcodes) | |
1164 | { | |
1165 | const char *name = mips16_opcodes[i].name; | |
1166 | ||
17a2f251 | 1167 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
1168 | if (retval != NULL) |
1169 | as_fatal (_("internal: can't hash `%s': %s"), | |
1170 | mips16_opcodes[i].name, retval); | |
1171 | do | |
1172 | { | |
1173 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1174 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1175 | != mips16_opcodes[i].match)) | |
1176 | { | |
1177 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
1178 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1179 | broken = 1; | |
1180 | } | |
1181 | ++i; | |
1182 | } | |
1183 | while (i < bfd_mips16_num_opcodes | |
1184 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1185 | } | |
1186 | ||
1187 | if (broken) | |
1188 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1189 | ||
1190 | /* We add all the general register names to the symbol table. This | |
1191 | helps us detect invalid uses of them. */ | |
1192 | for (i = 0; i < 32; i++) | |
1193 | { | |
1194 | char buf[5]; | |
1195 | ||
1196 | sprintf (buf, "$%d", i); | |
1197 | symbol_table_insert (symbol_new (buf, reg_section, i, | |
1198 | &zero_address_frag)); | |
1199 | } | |
76db943d TS |
1200 | symbol_table_insert (symbol_new ("$ra", reg_section, RA, |
1201 | &zero_address_frag)); | |
252b5132 RH |
1202 | symbol_table_insert (symbol_new ("$fp", reg_section, FP, |
1203 | &zero_address_frag)); | |
1204 | symbol_table_insert (symbol_new ("$sp", reg_section, SP, | |
1205 | &zero_address_frag)); | |
1206 | symbol_table_insert (symbol_new ("$gp", reg_section, GP, | |
1207 | &zero_address_frag)); | |
1208 | symbol_table_insert (symbol_new ("$at", reg_section, AT, | |
1209 | &zero_address_frag)); | |
1210 | symbol_table_insert (symbol_new ("$kt0", reg_section, KT0, | |
1211 | &zero_address_frag)); | |
1212 | symbol_table_insert (symbol_new ("$kt1", reg_section, KT1, | |
1213 | &zero_address_frag)); | |
85b51719 TS |
1214 | symbol_table_insert (symbol_new ("$zero", reg_section, ZERO, |
1215 | &zero_address_frag)); | |
252b5132 RH |
1216 | symbol_table_insert (symbol_new ("$pc", reg_section, -1, |
1217 | &zero_address_frag)); | |
1218 | ||
6047c971 AO |
1219 | /* If we don't add these register names to the symbol table, they |
1220 | may end up being added as regular symbols by operand(), and then | |
1221 | make it to the object file as undefined in case they're not | |
1222 | regarded as local symbols. They're local in o32, since `$' is a | |
1223 | local symbol prefix, but not in n32 or n64. */ | |
1224 | for (i = 0; i < 8; i++) | |
1225 | { | |
1226 | char buf[6]; | |
1227 | ||
1228 | sprintf (buf, "$fcc%i", i); | |
1229 | symbol_table_insert (symbol_new (buf, reg_section, -1, | |
1230 | &zero_address_frag)); | |
1231 | } | |
1232 | ||
b34976b6 | 1233 | mips_no_prev_insn (FALSE); |
252b5132 RH |
1234 | |
1235 | mips_gprmask = 0; | |
1236 | mips_cprmask[0] = 0; | |
1237 | mips_cprmask[1] = 0; | |
1238 | mips_cprmask[2] = 0; | |
1239 | mips_cprmask[3] = 0; | |
1240 | ||
1241 | /* set the default alignment for the text section (2**2) */ | |
1242 | record_alignment (text_section, 2); | |
1243 | ||
1244 | if (USE_GLOBAL_POINTER_OPT) | |
1245 | bfd_set_gp_size (stdoutput, g_switch_value); | |
1246 | ||
1247 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1248 | { | |
1249 | /* On a native system, sections must be aligned to 16 byte | |
1250 | boundaries. When configured for an embedded ELF target, we | |
1251 | don't bother. */ | |
1252 | if (strcmp (TARGET_OS, "elf") != 0) | |
1253 | { | |
1254 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
1255 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
1256 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
1257 | } | |
1258 | ||
1259 | /* Create a .reginfo section for register masks and a .mdebug | |
1260 | section for debugging information. */ | |
1261 | { | |
1262 | segT seg; | |
1263 | subsegT subseg; | |
1264 | flagword flags; | |
1265 | segT sec; | |
1266 | ||
1267 | seg = now_seg; | |
1268 | subseg = now_subseg; | |
1269 | ||
1270 | /* The ABI says this section should be loaded so that the | |
1271 | running program can access it. However, we don't load it | |
1272 | if we are configured for an embedded target */ | |
1273 | flags = SEC_READONLY | SEC_DATA; | |
1274 | if (strcmp (TARGET_OS, "elf") != 0) | |
1275 | flags |= SEC_ALLOC | SEC_LOAD; | |
1276 | ||
316f5878 | 1277 | if (mips_abi != N64_ABI) |
252b5132 RH |
1278 | { |
1279 | sec = subseg_new (".reginfo", (subsegT) 0); | |
1280 | ||
195325d2 TS |
1281 | bfd_set_section_flags (stdoutput, sec, flags); |
1282 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 1283 | |
252b5132 RH |
1284 | #ifdef OBJ_ELF |
1285 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); | |
1286 | #endif | |
1287 | } | |
1288 | else | |
1289 | { | |
1290 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
1291 | .reginfo section. */ | |
1292 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
1293 | bfd_set_section_flags (stdoutput, sec, flags); |
1294 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 RH |
1295 | |
1296 | #ifdef OBJ_ELF | |
1297 | /* Set up the option header. */ | |
1298 | { | |
1299 | Elf_Internal_Options opthdr; | |
1300 | char *f; | |
1301 | ||
1302 | opthdr.kind = ODK_REGINFO; | |
1303 | opthdr.size = (sizeof (Elf_External_Options) | |
1304 | + sizeof (Elf64_External_RegInfo)); | |
1305 | opthdr.section = 0; | |
1306 | opthdr.info = 0; | |
1307 | f = frag_more (sizeof (Elf_External_Options)); | |
1308 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
1309 | (Elf_External_Options *) f); | |
1310 | ||
1311 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
1312 | } | |
1313 | #endif | |
1314 | } | |
1315 | ||
1316 | if (ECOFF_DEBUGGING) | |
1317 | { | |
1318 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1319 | (void) bfd_set_section_flags (stdoutput, sec, | |
1320 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1321 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1322 | } | |
ecb4347a | 1323 | #ifdef OBJ_ELF |
dcd410fe | 1324 | else if (OUTPUT_FLAVOR == bfd_target_elf_flavour && mips_flag_pdr) |
ecb4347a DJ |
1325 | { |
1326 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
1327 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
1328 | SEC_READONLY | SEC_RELOC | |
1329 | | SEC_DEBUGGING); | |
1330 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
1331 | } | |
252b5132 RH |
1332 | #endif |
1333 | ||
1334 | subseg_set (seg, subseg); | |
1335 | } | |
1336 | } | |
1337 | ||
1338 | if (! ECOFF_DEBUGGING) | |
1339 | md_obj_begin (); | |
1340 | } | |
1341 | ||
1342 | void | |
17a2f251 | 1343 | md_mips_end (void) |
252b5132 RH |
1344 | { |
1345 | if (! ECOFF_DEBUGGING) | |
1346 | md_obj_end (); | |
1347 | } | |
1348 | ||
1349 | void | |
17a2f251 | 1350 | md_assemble (char *str) |
252b5132 RH |
1351 | { |
1352 | struct mips_cl_insn insn; | |
f6688943 TS |
1353 | bfd_reloc_code_real_type unused_reloc[3] |
1354 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
1355 | |
1356 | imm_expr.X_op = O_absent; | |
5f74bc13 | 1357 | imm2_expr.X_op = O_absent; |
252b5132 | 1358 | offset_expr.X_op = O_absent; |
f6688943 TS |
1359 | imm_reloc[0] = BFD_RELOC_UNUSED; |
1360 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
1361 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
1362 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
1363 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
1364 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
1365 | |
1366 | if (mips_opts.mips16) | |
1367 | mips16_ip (str, &insn); | |
1368 | else | |
1369 | { | |
1370 | mips_ip (str, &insn); | |
beae10d5 KH |
1371 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
1372 | str, insn.insn_opcode)); | |
252b5132 RH |
1373 | } |
1374 | ||
1375 | if (insn_error) | |
1376 | { | |
1377 | as_bad ("%s `%s'", insn_error, str); | |
1378 | return; | |
1379 | } | |
1380 | ||
1381 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
1382 | { | |
584892a6 | 1383 | macro_start (); |
252b5132 RH |
1384 | if (mips_opts.mips16) |
1385 | mips16_macro (&insn); | |
1386 | else | |
1387 | macro (&insn); | |
584892a6 | 1388 | macro_end (); |
252b5132 RH |
1389 | } |
1390 | else | |
1391 | { | |
1392 | if (imm_expr.X_op != O_absent) | |
4d7206a2 | 1393 | append_insn (&insn, &imm_expr, imm_reloc); |
252b5132 | 1394 | else if (offset_expr.X_op != O_absent) |
4d7206a2 | 1395 | append_insn (&insn, &offset_expr, offset_reloc); |
252b5132 | 1396 | else |
4d7206a2 | 1397 | append_insn (&insn, NULL, unused_reloc); |
252b5132 RH |
1398 | } |
1399 | } | |
1400 | ||
5919d012 RS |
1401 | /* Return true if the given relocation might need a matching %lo(). |
1402 | Note that R_MIPS_GOT16 relocations only need a matching %lo() when | |
1403 | applied to local symbols. */ | |
1404 | ||
1405 | static inline bfd_boolean | |
17a2f251 | 1406 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 RS |
1407 | { |
1408 | return (reloc == BFD_RELOC_HI16_S | |
1409 | || reloc == BFD_RELOC_MIPS_GOT16); | |
1410 | } | |
1411 | ||
1412 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
1413 | relocation. */ | |
1414 | ||
1415 | static inline bfd_boolean | |
17a2f251 | 1416 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
1417 | { |
1418 | return (fixp->fx_next != NULL | |
1419 | && fixp->fx_next->fx_r_type == BFD_RELOC_LO16 | |
1420 | && fixp->fx_addsy == fixp->fx_next->fx_addsy | |
1421 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
1422 | } | |
1423 | ||
252b5132 RH |
1424 | /* See whether instruction IP reads register REG. CLASS is the type |
1425 | of register. */ | |
1426 | ||
1427 | static int | |
17a2f251 TS |
1428 | insn_uses_reg (struct mips_cl_insn *ip, unsigned int reg, |
1429 | enum mips_regclass class) | |
252b5132 RH |
1430 | { |
1431 | if (class == MIPS16_REG) | |
1432 | { | |
1433 | assert (mips_opts.mips16); | |
1434 | reg = mips16_to_32_reg_map[reg]; | |
1435 | class = MIPS_GR_REG; | |
1436 | } | |
1437 | ||
85b51719 TS |
1438 | /* Don't report on general register ZERO, since it never changes. */ |
1439 | if (class == MIPS_GR_REG && reg == ZERO) | |
252b5132 RH |
1440 | return 0; |
1441 | ||
1442 | if (class == MIPS_FP_REG) | |
1443 | { | |
1444 | assert (! mips_opts.mips16); | |
1445 | /* If we are called with either $f0 or $f1, we must check $f0. | |
1446 | This is not optimal, because it will introduce an unnecessary | |
1447 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
1448 | need to distinguish reading both $f0 and $f1 or just one of | |
1449 | them. Note that we don't have to check the other way, | |
1450 | because there is no instruction that sets both $f0 and $f1 | |
1451 | and requires a delay. */ | |
1452 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
1453 | && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1) | |
1454 | == (reg &~ (unsigned) 1))) | |
1455 | return 1; | |
1456 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
1457 | && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1) | |
1458 | == (reg &~ (unsigned) 1))) | |
1459 | return 1; | |
1460 | } | |
1461 | else if (! mips_opts.mips16) | |
1462 | { | |
1463 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
1464 | && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg) | |
1465 | return 1; | |
1466 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
1467 | && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg) | |
1468 | return 1; | |
1469 | } | |
1470 | else | |
1471 | { | |
1472 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
1473 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX) | |
1474 | & MIPS16OP_MASK_RX)] | |
1475 | == reg)) | |
1476 | return 1; | |
1477 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
1478 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY) | |
1479 | & MIPS16OP_MASK_RY)] | |
1480 | == reg)) | |
1481 | return 1; | |
1482 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
1483 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1484 | & MIPS16OP_MASK_MOVE32Z)] | |
1485 | == reg)) | |
1486 | return 1; | |
1487 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
1488 | return 1; | |
1489 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
1490 | return 1; | |
1491 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
1492 | return 1; | |
1493 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
1494 | && ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1495 | & MIPS16OP_MASK_REGR32) == reg) | |
1496 | return 1; | |
1497 | } | |
1498 | ||
1499 | return 0; | |
1500 | } | |
1501 | ||
1502 | /* This function returns true if modifying a register requires a | |
1503 | delay. */ | |
1504 | ||
1505 | static int | |
17a2f251 | 1506 | reg_needs_delay (unsigned int reg) |
252b5132 RH |
1507 | { |
1508 | unsigned long prev_pinfo; | |
1509 | ||
1510 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1511 | if (! mips_opts.noreorder | |
81912461 ILT |
1512 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
1513 | && ! gpr_interlocks) | |
1514 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
1515 | && ! cop_interlocks))) | |
252b5132 | 1516 | { |
81912461 ILT |
1517 | /* A load from a coprocessor or from memory. All load delays |
1518 | delay the use of general register rt for one instruction. */ | |
bdaaa2e1 | 1519 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1520 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1521 | if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)) | |
1522 | return 1; | |
1523 | } | |
1524 | ||
1525 | return 0; | |
1526 | } | |
1527 | ||
1528 | /* Mark instruction labels in mips16 mode. This permits the linker to | |
1529 | handle them specially, such as generating jalx instructions when | |
1530 | needed. We also make them odd for the duration of the assembly, in | |
1531 | order to generate the right sort of code. We will make them even | |
1532 | in the adjust_symtab routine, while leaving them marked. This is | |
1533 | convenient for the debugger and the disassembler. The linker knows | |
1534 | to make them odd again. */ | |
1535 | ||
1536 | static void | |
17a2f251 | 1537 | mips16_mark_labels (void) |
252b5132 RH |
1538 | { |
1539 | if (mips_opts.mips16) | |
1540 | { | |
1541 | struct insn_label_list *l; | |
98aa84af | 1542 | valueT val; |
252b5132 RH |
1543 | |
1544 | for (l = insn_labels; l != NULL; l = l->next) | |
1545 | { | |
1546 | #ifdef OBJ_ELF | |
1547 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1548 | S_SET_OTHER (l->label, STO_MIPS16); | |
1549 | #endif | |
98aa84af AM |
1550 | val = S_GET_VALUE (l->label); |
1551 | if ((val & 1) == 0) | |
1552 | S_SET_VALUE (l->label, val + 1); | |
252b5132 RH |
1553 | } |
1554 | } | |
1555 | } | |
1556 | ||
4d7206a2 RS |
1557 | /* End the current frag. Make it a variant frag and record the |
1558 | relaxation info. */ | |
1559 | ||
1560 | static void | |
1561 | relax_close_frag (void) | |
1562 | { | |
584892a6 | 1563 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 1564 | frag_var (rs_machine_dependent, 0, 0, |
584892a6 | 1565 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), |
4d7206a2 RS |
1566 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
1567 | ||
1568 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
1569 | mips_relax.first_fixup = 0; | |
1570 | } | |
1571 | ||
1572 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
1573 | See the comment above RELAX_ENCODE for more details. */ | |
1574 | ||
1575 | static void | |
1576 | relax_start (symbolS *symbol) | |
1577 | { | |
1578 | assert (mips_relax.sequence == 0); | |
1579 | mips_relax.sequence = 1; | |
1580 | mips_relax.symbol = symbol; | |
1581 | } | |
1582 | ||
1583 | /* Start generating the second version of a relaxable sequence. | |
1584 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
1585 | |
1586 | static void | |
4d7206a2 RS |
1587 | relax_switch (void) |
1588 | { | |
1589 | assert (mips_relax.sequence == 1); | |
1590 | mips_relax.sequence = 2; | |
1591 | } | |
1592 | ||
1593 | /* End the current relaxable sequence. */ | |
1594 | ||
1595 | static void | |
1596 | relax_end (void) | |
1597 | { | |
1598 | assert (mips_relax.sequence == 2); | |
1599 | relax_close_frag (); | |
1600 | mips_relax.sequence = 0; | |
1601 | } | |
1602 | ||
1603 | /* Output an instruction. IP is the instruction information. | |
1604 | ADDRESS_EXPR is an operand of the instruction to be used with | |
1605 | RELOC_TYPE. */ | |
1606 | ||
1607 | static void | |
1608 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
17a2f251 | 1609 | bfd_reloc_code_real_type *reloc_type) |
252b5132 RH |
1610 | { |
1611 | register unsigned long prev_pinfo, pinfo; | |
1612 | char *f; | |
f6688943 | 1613 | fixS *fixp[3]; |
252b5132 | 1614 | int nops = 0; |
895921c9 MR |
1615 | relax_stateT prev_insn_frag_type = 0; |
1616 | bfd_boolean relaxed_branch = FALSE; | |
f5040a92 | 1617 | bfd_boolean force_new_frag = FALSE; |
252b5132 RH |
1618 | |
1619 | /* Mark instruction labels in mips16 mode. */ | |
f9419b05 | 1620 | mips16_mark_labels (); |
252b5132 RH |
1621 | |
1622 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1623 | pinfo = ip->insn_mo->pinfo; | |
1624 | ||
4d7206a2 RS |
1625 | if (mips_relax.sequence != 2 |
1626 | && (!mips_opts.noreorder || prev_nop_frag != NULL)) | |
252b5132 RH |
1627 | { |
1628 | int prev_prev_nop; | |
1629 | ||
1630 | /* If the previous insn required any delay slots, see if we need | |
1631 | to insert a NOP or two. There are eight kinds of possible | |
1632 | hazards, of which an instruction can have at most one type. | |
1633 | (1) a load from memory delay | |
1634 | (2) a load from a coprocessor delay | |
1635 | (3) an unconditional branch delay | |
1636 | (4) a conditional branch delay | |
1637 | (5) a move to coprocessor register delay | |
1638 | (6) a load coprocessor register from memory delay | |
1639 | (7) a coprocessor condition code delay | |
1640 | (8) a HI/LO special register delay | |
1641 | ||
1642 | There are a lot of optimizations we could do that we don't. | |
1643 | In particular, we do not, in general, reorder instructions. | |
1644 | If you use gcc with optimization, it will reorder | |
1645 | instructions and generally do much more optimization then we | |
1646 | do here; repeating all that work in the assembler would only | |
1647 | benefit hand written assembly code, and does not seem worth | |
1648 | it. */ | |
1649 | ||
1650 | /* This is how a NOP is emitted. */ | |
1651 | #define emit_nop() \ | |
1652 | (mips_opts.mips16 \ | |
1653 | ? md_number_to_chars (frag_more (2), 0x6500, 2) \ | |
1654 | : md_number_to_chars (frag_more (4), 0, 4)) | |
1655 | ||
1656 | /* The previous insn might require a delay slot, depending upon | |
1657 | the contents of the current insn. */ | |
1658 | if (! mips_opts.mips16 | |
81912461 ILT |
1659 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
1660 | && ! gpr_interlocks) | |
1661 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
1662 | && ! cop_interlocks))) | |
252b5132 RH |
1663 | { |
1664 | /* A load from a coprocessor or from memory. All load | |
1665 | delays delay the use of general register rt for one | |
81912461 | 1666 | instruction. */ |
beae10d5 | 1667 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1668 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1669 | if (mips_optimize == 0 | |
1670 | || insn_uses_reg (ip, | |
1671 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1672 | & OP_MASK_RT), | |
1673 | MIPS_GR_REG)) | |
1674 | ++nops; | |
1675 | } | |
1676 | else if (! mips_opts.mips16 | |
252b5132 | 1677 | && (((prev_pinfo & INSN_COPROC_MOVE_DELAY) |
beae10d5 | 1678 | && ! cop_interlocks) |
81912461 ILT |
1679 | || ((prev_pinfo & INSN_COPROC_MEMORY_DELAY) |
1680 | && ! cop_mem_interlocks))) | |
252b5132 RH |
1681 | { |
1682 | /* A generic coprocessor delay. The previous instruction | |
1683 | modified a coprocessor general or control register. If | |
1684 | it modified a control register, we need to avoid any | |
1685 | coprocessor instruction (this is probably not always | |
1686 | required, but it sometimes is). If it modified a general | |
1687 | register, we avoid using that register. | |
1688 | ||
252b5132 RH |
1689 | This case is not handled very well. There is no special |
1690 | knowledge of CP0 handling, and the coprocessors other | |
1691 | than the floating point unit are not distinguished at | |
1692 | all. */ | |
1693 | /* Itbl support may require additional care here. FIXME! | |
bdaaa2e1 | 1694 | Need to modify this to include knowledge about |
252b5132 RH |
1695 | user specified delays! */ |
1696 | if (prev_pinfo & INSN_WRITE_FPR_T) | |
1697 | { | |
1698 | if (mips_optimize == 0 | |
1699 | || insn_uses_reg (ip, | |
1700 | ((prev_insn.insn_opcode >> OP_SH_FT) | |
1701 | & OP_MASK_FT), | |
1702 | MIPS_FP_REG)) | |
1703 | ++nops; | |
1704 | } | |
1705 | else if (prev_pinfo & INSN_WRITE_FPR_S) | |
1706 | { | |
1707 | if (mips_optimize == 0 | |
1708 | || insn_uses_reg (ip, | |
1709 | ((prev_insn.insn_opcode >> OP_SH_FS) | |
1710 | & OP_MASK_FS), | |
1711 | MIPS_FP_REG)) | |
1712 | ++nops; | |
1713 | } | |
1714 | else | |
1715 | { | |
1716 | /* We don't know exactly what the previous instruction | |
1717 | does. If the current instruction uses a coprocessor | |
1718 | register, we must insert a NOP. If previous | |
1719 | instruction may set the condition codes, and the | |
1720 | current instruction uses them, we must insert two | |
1721 | NOPS. */ | |
bdaaa2e1 | 1722 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1723 | if (mips_optimize == 0 |
1724 | || ((prev_pinfo & INSN_WRITE_COND_CODE) | |
1725 | && (pinfo & INSN_READ_COND_CODE))) | |
1726 | nops += 2; | |
1727 | else if (pinfo & INSN_COP) | |
1728 | ++nops; | |
1729 | } | |
1730 | } | |
1731 | else if (! mips_opts.mips16 | |
252b5132 RH |
1732 | && (prev_pinfo & INSN_WRITE_COND_CODE) |
1733 | && ! cop_interlocks) | |
1734 | { | |
1735 | /* The previous instruction sets the coprocessor condition | |
1736 | codes, but does not require a general coprocessor delay | |
1737 | (this means it is a floating point comparison | |
1738 | instruction). If this instruction uses the condition | |
1739 | codes, we need to insert a single NOP. */ | |
beae10d5 | 1740 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1741 | if (mips_optimize == 0 |
1742 | || (pinfo & INSN_READ_COND_CODE)) | |
1743 | ++nops; | |
1744 | } | |
6b76fefe CM |
1745 | |
1746 | /* If we're fixing up mfhi/mflo for the r7000 and the | |
1747 | previous insn was an mfhi/mflo and the current insn | |
1748 | reads the register that the mfhi/mflo wrote to, then | |
1749 | insert two nops. */ | |
1750 | ||
1751 | else if (mips_7000_hilo_fix | |
1752 | && MF_HILO_INSN (prev_pinfo) | |
1753 | && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD) | |
beae10d5 KH |
1754 | & OP_MASK_RD), |
1755 | MIPS_GR_REG)) | |
6b76fefe CM |
1756 | { |
1757 | nops += 2; | |
1758 | } | |
1759 | ||
1760 | /* If we're fixing up mfhi/mflo for the r7000 and the | |
1761 | 2nd previous insn was an mfhi/mflo and the current insn | |
1762 | reads the register that the mfhi/mflo wrote to, then | |
1763 | insert one nop. */ | |
1764 | ||
1765 | else if (mips_7000_hilo_fix | |
1766 | && MF_HILO_INSN (prev_prev_insn.insn_opcode) | |
1767 | && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD) | |
1768 | & OP_MASK_RD), | |
1769 | MIPS_GR_REG)) | |
bdaaa2e1 | 1770 | |
6b76fefe | 1771 | { |
f9419b05 | 1772 | ++nops; |
6b76fefe | 1773 | } |
bdaaa2e1 | 1774 | |
252b5132 RH |
1775 | else if (prev_pinfo & INSN_READ_LO) |
1776 | { | |
1777 | /* The previous instruction reads the LO register; if the | |
1778 | current instruction writes to the LO register, we must | |
bdaaa2e1 | 1779 | insert two NOPS. Some newer processors have interlocks. |
67c1ffbe KH |
1780 | Also the tx39's multiply instructions can be executed |
1781 | immediately after a read from HI/LO (without the delay), | |
bdaaa2e1 KH |
1782 | though the tx39's divide insns still do require the |
1783 | delay. */ | |
252b5132 | 1784 | if (! (hilo_interlocks |
048cdf86 | 1785 | || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
1786 | && (mips_optimize == 0 |
1787 | || (pinfo & INSN_WRITE_LO))) | |
1788 | nops += 2; | |
1789 | /* Most mips16 branch insns don't have a delay slot. | |
1790 | If a read from LO is immediately followed by a branch | |
1791 | to a write to LO we have a read followed by a write | |
1792 | less than 2 insns away. We assume the target of | |
1793 | a branch might be a write to LO, and insert a nop | |
bdaaa2e1 | 1794 | between a read and an immediately following branch. */ |
252b5132 RH |
1795 | else if (mips_opts.mips16 |
1796 | && (mips_optimize == 0 | |
1797 | || (pinfo & MIPS16_INSN_BRANCH))) | |
f9419b05 | 1798 | ++nops; |
252b5132 RH |
1799 | } |
1800 | else if (prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1801 | { | |
1802 | /* The previous instruction reads the HI register; if the | |
1803 | current instruction writes to the HI register, we must | |
1804 | insert a NOP. Some newer processors have interlocks. | |
bdaaa2e1 | 1805 | Also the note tx39's multiply above. */ |
252b5132 | 1806 | if (! (hilo_interlocks |
048cdf86 | 1807 | || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
1808 | && (mips_optimize == 0 |
1809 | || (pinfo & INSN_WRITE_HI))) | |
1810 | nops += 2; | |
1811 | /* Most mips16 branch insns don't have a delay slot. | |
1812 | If a read from HI is immediately followed by a branch | |
1813 | to a write to HI we have a read followed by a write | |
1814 | less than 2 insns away. We assume the target of | |
1815 | a branch might be a write to HI, and insert a nop | |
bdaaa2e1 | 1816 | between a read and an immediately following branch. */ |
252b5132 RH |
1817 | else if (mips_opts.mips16 |
1818 | && (mips_optimize == 0 | |
1819 | || (pinfo & MIPS16_INSN_BRANCH))) | |
f9419b05 | 1820 | ++nops; |
252b5132 RH |
1821 | } |
1822 | ||
1823 | /* If the previous instruction was in a noreorder section, then | |
1824 | we don't want to insert the nop after all. */ | |
bdaaa2e1 | 1825 | /* Itbl support may require additional care here. */ |
252b5132 RH |
1826 | if (prev_insn_unreordered) |
1827 | nops = 0; | |
1828 | ||
1829 | /* There are two cases which require two intervening | |
1830 | instructions: 1) setting the condition codes using a move to | |
1831 | coprocessor instruction which requires a general coprocessor | |
1832 | delay and then reading the condition codes 2) reading the HI | |
1833 | or LO register and then writing to it (except on processors | |
1834 | which have interlocks). If we are not already emitting a NOP | |
1835 | instruction, we must check for these cases compared to the | |
1836 | instruction previous to the previous instruction. */ | |
1837 | if ((! mips_opts.mips16 | |
252b5132 RH |
1838 | && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) |
1839 | && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) | |
1840 | && (pinfo & INSN_READ_COND_CODE) | |
1841 | && ! cop_interlocks) | |
1842 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO) | |
1843 | && (pinfo & INSN_WRITE_LO) | |
1844 | && ! (hilo_interlocks | |
048cdf86 | 1845 | || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))) |
252b5132 RH |
1846 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
1847 | && (pinfo & INSN_WRITE_HI) | |
1848 | && ! (hilo_interlocks | |
048cdf86 | 1849 | || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))))) |
252b5132 RH |
1850 | prev_prev_nop = 1; |
1851 | else | |
1852 | prev_prev_nop = 0; | |
1853 | ||
1854 | if (prev_prev_insn_unreordered) | |
1855 | prev_prev_nop = 0; | |
1856 | ||
1857 | if (prev_prev_nop && nops == 0) | |
1858 | ++nops; | |
1859 | ||
d766e8ec | 1860 | if (mips_fix_vr4120 && prev_insn.insn_mo->name) |
60b63b72 RS |
1861 | { |
1862 | /* We're out of bits in pinfo, so we must resort to string | |
1863 | ops here. Shortcuts are selected based on opcodes being | |
d766e8ec | 1864 | limited to the VR4120 instruction set. */ |
60b63b72 RS |
1865 | int min_nops = 0; |
1866 | const char *pn = prev_insn.insn_mo->name; | |
1867 | const char *tn = ip->insn_mo->name; | |
1868 | if (strncmp(pn, "macc", 4) == 0 | |
1869 | || strncmp(pn, "dmacc", 5) == 0) | |
1870 | { | |
1871 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
1872 | if (strstr (tn, "div")) | |
1873 | { | |
1874 | min_nops = 1; | |
1875 | } | |
1876 | ||
1877 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions */ | |
1878 | if (pn[0] == 'd' /* dmacc */ | |
1879 | && (strncmp(tn, "dmult", 5) == 0 | |
1880 | || strncmp(tn, "dmacc", 5) == 0)) | |
1881 | { | |
1882 | min_nops = 1; | |
1883 | } | |
1884 | ||
1885 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
1886 | if (strcmp (tn, "mtlo") == 0 | |
1887 | || strcmp (tn, "mthi") == 0) | |
1888 | { | |
1889 | min_nops = 1; | |
1890 | } | |
1891 | ||
1892 | } | |
1893 | else if (strncmp(pn, "dmult", 5) == 0 | |
1894 | && (strncmp(tn, "dmult", 5) == 0 | |
1895 | || strncmp(tn, "dmacc", 5) == 0)) | |
1896 | { | |
1897 | /* Here is the rest of errata 23. */ | |
1898 | min_nops = 1; | |
1899 | } | |
1900 | if (nops < min_nops) | |
1901 | nops = min_nops; | |
1902 | } | |
1903 | ||
252b5132 RH |
1904 | /* If we are being given a nop instruction, don't bother with |
1905 | one of the nops we would otherwise output. This will only | |
1906 | happen when a nop instruction is used with mips_optimize set | |
1907 | to 0. */ | |
1908 | if (nops > 0 | |
1909 | && ! mips_opts.noreorder | |
156c2f8b | 1910 | && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0)) |
252b5132 RH |
1911 | --nops; |
1912 | ||
1913 | /* Now emit the right number of NOP instructions. */ | |
1914 | if (nops > 0 && ! mips_opts.noreorder) | |
1915 | { | |
1916 | fragS *old_frag; | |
1917 | unsigned long old_frag_offset; | |
1918 | int i; | |
1919 | struct insn_label_list *l; | |
1920 | ||
1921 | old_frag = frag_now; | |
1922 | old_frag_offset = frag_now_fix (); | |
1923 | ||
1924 | for (i = 0; i < nops; i++) | |
1925 | emit_nop (); | |
1926 | ||
1927 | if (listing) | |
1928 | { | |
1929 | listing_prev_line (); | |
1930 | /* We may be at the start of a variant frag. In case we | |
1931 | are, make sure there is enough space for the frag | |
1932 | after the frags created by listing_prev_line. The | |
1933 | argument to frag_grow here must be at least as large | |
1934 | as the argument to all other calls to frag_grow in | |
1935 | this file. We don't have to worry about being in the | |
1936 | middle of a variant frag, because the variants insert | |
1937 | all needed nop instructions themselves. */ | |
1938 | frag_grow (40); | |
1939 | } | |
1940 | ||
1941 | for (l = insn_labels; l != NULL; l = l->next) | |
1942 | { | |
98aa84af AM |
1943 | valueT val; |
1944 | ||
252b5132 | 1945 | assert (S_GET_SEGMENT (l->label) == now_seg); |
49309057 | 1946 | symbol_set_frag (l->label, frag_now); |
98aa84af | 1947 | val = (valueT) frag_now_fix (); |
252b5132 RH |
1948 | /* mips16 text labels are stored as odd. */ |
1949 | if (mips_opts.mips16) | |
f9419b05 | 1950 | ++val; |
98aa84af | 1951 | S_SET_VALUE (l->label, val); |
252b5132 RH |
1952 | } |
1953 | ||
1954 | #ifndef NO_ECOFF_DEBUGGING | |
1955 | if (ECOFF_DEBUGGING) | |
1956 | ecoff_fix_loc (old_frag, old_frag_offset); | |
1957 | #endif | |
1958 | } | |
1959 | else if (prev_nop_frag != NULL) | |
1960 | { | |
1961 | /* We have a frag holding nops we may be able to remove. If | |
1962 | we don't need any nops, we can decrease the size of | |
1963 | prev_nop_frag by the size of one instruction. If we do | |
bdaaa2e1 | 1964 | need some nops, we count them in prev_nops_required. */ |
252b5132 RH |
1965 | if (prev_nop_frag_since == 0) |
1966 | { | |
1967 | if (nops == 0) | |
1968 | { | |
1969 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
1970 | --prev_nop_frag_holds; | |
1971 | } | |
1972 | else | |
1973 | prev_nop_frag_required += nops; | |
1974 | } | |
1975 | else | |
1976 | { | |
1977 | if (prev_prev_nop == 0) | |
1978 | { | |
1979 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
1980 | --prev_nop_frag_holds; | |
1981 | } | |
1982 | else | |
1983 | ++prev_nop_frag_required; | |
1984 | } | |
1985 | ||
1986 | if (prev_nop_frag_holds <= prev_nop_frag_required) | |
1987 | prev_nop_frag = NULL; | |
1988 | ||
1989 | ++prev_nop_frag_since; | |
1990 | ||
1991 | /* Sanity check: by the time we reach the second instruction | |
1992 | after prev_nop_frag, we should have used up all the nops | |
1993 | one way or another. */ | |
1994 | assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL); | |
1995 | } | |
1996 | } | |
1997 | ||
895921c9 MR |
1998 | /* Record the frag type before frag_var. */ |
1999 | if (prev_insn_frag) | |
2000 | prev_insn_frag_type = prev_insn_frag->fr_type; | |
2001 | ||
4d7206a2 | 2002 | if (address_expr |
0b25d3e6 | 2003 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
4a6a3df4 AO |
2004 | && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY |
2005 | || pinfo & INSN_COND_BRANCH_LIKELY) | |
2006 | && mips_relax_branch | |
2007 | /* Don't try branch relaxation within .set nomacro, or within | |
2008 | .set noat if we use $at for PIC computations. If it turns | |
2009 | out that the branch was out-of-range, we'll get an error. */ | |
2010 | && !mips_opts.warn_about_macros | |
2011 | && !(mips_opts.noat && mips_pic != NO_PIC) | |
2012 | && !mips_opts.mips16) | |
2013 | { | |
895921c9 | 2014 | relaxed_branch = TRUE; |
4a6a3df4 AO |
2015 | f = frag_var (rs_machine_dependent, |
2016 | relaxed_branch_length | |
2017 | (NULL, NULL, | |
2018 | (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1 | |
2019 | : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 : 0), 4, | |
2020 | RELAX_BRANCH_ENCODE | |
af6ae2ad | 2021 | (pinfo & INSN_UNCOND_BRANCH_DELAY, |
4a6a3df4 AO |
2022 | pinfo & INSN_COND_BRANCH_LIKELY, |
2023 | pinfo & INSN_WRITE_GPR_31, | |
2024 | 0), | |
2025 | address_expr->X_add_symbol, | |
2026 | address_expr->X_add_number, | |
2027 | 0); | |
2028 | *reloc_type = BFD_RELOC_UNUSED; | |
2029 | } | |
2030 | else if (*reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
2031 | { |
2032 | /* We need to set up a variant frag. */ | |
2033 | assert (mips_opts.mips16 && address_expr != NULL); | |
2034 | f = frag_var (rs_machine_dependent, 4, 0, | |
f6688943 | 2035 | RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED, |
252b5132 RH |
2036 | mips16_small, mips16_ext, |
2037 | (prev_pinfo | |
2038 | & INSN_UNCOND_BRANCH_DELAY), | |
f6688943 | 2039 | (*prev_insn_reloc_type |
252b5132 | 2040 | == BFD_RELOC_MIPS16_JMP)), |
c4e7957c | 2041 | make_expr_symbol (address_expr), 0, NULL); |
252b5132 | 2042 | } |
252b5132 RH |
2043 | else if (mips_opts.mips16 |
2044 | && ! ip->use_extend | |
f6688943 | 2045 | && *reloc_type != BFD_RELOC_MIPS16_JMP) |
252b5132 RH |
2046 | { |
2047 | /* Make sure there is enough room to swap this instruction with | |
2048 | a following jump instruction. */ | |
2049 | frag_grow (6); | |
2050 | f = frag_more (2); | |
2051 | } | |
2052 | else | |
2053 | { | |
2054 | if (mips_opts.mips16 | |
2055 | && mips_opts.noreorder | |
2056 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
2057 | as_warn (_("extended instruction in delay slot")); | |
2058 | ||
4d7206a2 RS |
2059 | if (mips_relax.sequence) |
2060 | { | |
2061 | /* If we've reached the end of this frag, turn it into a variant | |
2062 | frag and record the information for the instructions we've | |
2063 | written so far. */ | |
2064 | if (frag_room () < 4) | |
2065 | relax_close_frag (); | |
2066 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
2067 | } | |
2068 | ||
584892a6 RS |
2069 | if (mips_relax.sequence != 2) |
2070 | mips_macro_warning.sizes[0] += 4; | |
2071 | if (mips_relax.sequence != 1) | |
2072 | mips_macro_warning.sizes[1] += 4; | |
2073 | ||
252b5132 RH |
2074 | f = frag_more (4); |
2075 | } | |
2076 | ||
f6688943 TS |
2077 | fixp[0] = fixp[1] = fixp[2] = NULL; |
2078 | if (address_expr != NULL && *reloc_type < BFD_RELOC_UNUSED) | |
252b5132 RH |
2079 | { |
2080 | if (address_expr->X_op == O_constant) | |
2081 | { | |
4db1a35d | 2082 | valueT tmp; |
f6688943 TS |
2083 | |
2084 | switch (*reloc_type) | |
252b5132 RH |
2085 | { |
2086 | case BFD_RELOC_32: | |
2087 | ip->insn_opcode |= address_expr->X_add_number; | |
2088 | break; | |
2089 | ||
f6688943 | 2090 | case BFD_RELOC_MIPS_HIGHEST: |
6344efa4 AM |
2091 | tmp = (address_expr->X_add_number |
2092 | + ((valueT) 0x8000 << 32) + 0x80008000) >> 16; | |
f6688943 TS |
2093 | tmp >>= 16; |
2094 | ip->insn_opcode |= (tmp >> 16) & 0xffff; | |
2095 | break; | |
2096 | ||
2097 | case BFD_RELOC_MIPS_HIGHER: | |
2098 | tmp = (address_expr->X_add_number + 0x80008000) >> 16; | |
2099 | ip->insn_opcode |= (tmp >> 16) & 0xffff; | |
2100 | break; | |
2101 | ||
2102 | case BFD_RELOC_HI16_S: | |
2103 | ip->insn_opcode |= ((address_expr->X_add_number + 0x8000) | |
2104 | >> 16) & 0xffff; | |
2105 | break; | |
2106 | ||
2107 | case BFD_RELOC_HI16: | |
2108 | ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; | |
2109 | break; | |
2110 | ||
252b5132 | 2111 | case BFD_RELOC_LO16: |
ed6fb7bd | 2112 | case BFD_RELOC_MIPS_GOT_DISP: |
252b5132 RH |
2113 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
2114 | break; | |
2115 | ||
2116 | case BFD_RELOC_MIPS_JMP: | |
2117 | if ((address_expr->X_add_number & 3) != 0) | |
2118 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2119 | (unsigned long) address_expr->X_add_number); | |
f3c0ec86 | 2120 | if (address_expr->X_add_number & ~0xfffffff) |
7496292d TS |
2121 | as_bad (_("jump address range overflow (0x%lx)"), |
2122 | (unsigned long) address_expr->X_add_number); | |
252b5132 RH |
2123 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; |
2124 | break; | |
2125 | ||
2126 | case BFD_RELOC_MIPS16_JMP: | |
2127 | if ((address_expr->X_add_number & 3) != 0) | |
2128 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2129 | (unsigned long) address_expr->X_add_number); | |
f3c0ec86 | 2130 | if (address_expr->X_add_number & ~0xfffffff) |
7496292d TS |
2131 | as_bad (_("jump address range overflow (0x%lx)"), |
2132 | (unsigned long) address_expr->X_add_number); | |
252b5132 RH |
2133 | ip->insn_opcode |= |
2134 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
2135 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
2136 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
2137 | break; | |
2138 | ||
252b5132 RH |
2139 | case BFD_RELOC_16_PCREL_S2: |
2140 | goto need_reloc; | |
2141 | ||
2142 | default: | |
2143 | internalError (); | |
2144 | } | |
2145 | } | |
2146 | else | |
252b5132 | 2147 | need_reloc: |
4d7206a2 RS |
2148 | { |
2149 | reloc_howto_type *howto; | |
2150 | int i; | |
34ce925e | 2151 | |
4d7206a2 RS |
2152 | /* In a compound relocation, it is the final (outermost) |
2153 | operator that determines the relocated field. */ | |
2154 | for (i = 1; i < 3; i++) | |
2155 | if (reloc_type[i] == BFD_RELOC_UNUSED) | |
2156 | break; | |
34ce925e | 2157 | |
4d7206a2 RS |
2158 | howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]); |
2159 | fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal, | |
2160 | bfd_get_reloc_size(howto), | |
2161 | address_expr, | |
2162 | reloc_type[0] == BFD_RELOC_16_PCREL_S2, | |
2163 | reloc_type[0]); | |
2164 | ||
2165 | /* These relocations can have an addend that won't fit in | |
2166 | 4 octets for 64bit assembly. */ | |
2167 | if (HAVE_64BIT_GPRS | |
2168 | && ! howto->partial_inplace | |
2169 | && (reloc_type[0] == BFD_RELOC_16 | |
2170 | || reloc_type[0] == BFD_RELOC_32 | |
2171 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
2172 | || reloc_type[0] == BFD_RELOC_HI16_S | |
2173 | || reloc_type[0] == BFD_RELOC_LO16 | |
2174 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
2175 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
2176 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
2177 | || reloc_type[0] == BFD_RELOC_64 | |
2178 | || reloc_type[0] == BFD_RELOC_CTOR | |
2179 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
2180 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
2181 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
2182 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
2183 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
2184 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT)) | |
2185 | fixp[0]->fx_no_overflow = 1; | |
2186 | ||
2187 | if (mips_relax.sequence) | |
2188 | { | |
2189 | if (mips_relax.first_fixup == 0) | |
2190 | mips_relax.first_fixup = fixp[0]; | |
2191 | } | |
2192 | else if (reloc_needs_lo_p (*reloc_type)) | |
2193 | { | |
2194 | struct mips_hi_fixup *hi_fixup; | |
252b5132 | 2195 | |
4d7206a2 RS |
2196 | /* Reuse the last entry if it already has a matching %lo. */ |
2197 | hi_fixup = mips_hi_fixup_list; | |
2198 | if (hi_fixup == 0 | |
2199 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
2200 | { | |
2201 | hi_fixup = ((struct mips_hi_fixup *) | |
2202 | xmalloc (sizeof (struct mips_hi_fixup))); | |
2203 | hi_fixup->next = mips_hi_fixup_list; | |
2204 | mips_hi_fixup_list = hi_fixup; | |
252b5132 | 2205 | } |
4d7206a2 RS |
2206 | hi_fixup->fixp = fixp[0]; |
2207 | hi_fixup->seg = now_seg; | |
2208 | } | |
f6688943 | 2209 | |
4d7206a2 RS |
2210 | /* Add fixups for the second and third relocations, if given. |
2211 | Note that the ABI allows the second relocation to be | |
2212 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
2213 | moment we only use RSS_UNDEF, but we could add support | |
2214 | for the others if it ever becomes necessary. */ | |
2215 | for (i = 1; i < 3; i++) | |
2216 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
2217 | { | |
2218 | address_expr->X_op = O_absent; | |
2219 | address_expr->X_add_symbol = 0; | |
2220 | address_expr->X_add_number = 0; | |
34ce925e | 2221 | |
4d7206a2 RS |
2222 | fixp[i] = fix_new_exp (frag_now, fixp[0]->fx_where, |
2223 | fixp[0]->fx_size, address_expr, | |
2224 | FALSE, reloc_type[i]); | |
2225 | } | |
252b5132 RH |
2226 | } |
2227 | } | |
2228 | ||
2229 | if (! mips_opts.mips16) | |
c5dd6aab DJ |
2230 | { |
2231 | md_number_to_chars (f, ip->insn_opcode, 4); | |
2232 | #ifdef OBJ_ELF | |
2233 | dwarf2_emit_insn (4); | |
2234 | #endif | |
2235 | } | |
f6688943 | 2236 | else if (*reloc_type == BFD_RELOC_MIPS16_JMP) |
252b5132 RH |
2237 | { |
2238 | md_number_to_chars (f, ip->insn_opcode >> 16, 2); | |
2239 | md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2); | |
c5dd6aab DJ |
2240 | #ifdef OBJ_ELF |
2241 | dwarf2_emit_insn (4); | |
2242 | #endif | |
252b5132 RH |
2243 | } |
2244 | else | |
2245 | { | |
2246 | if (ip->use_extend) | |
2247 | { | |
2248 | md_number_to_chars (f, 0xf000 | ip->extend, 2); | |
2249 | f += 2; | |
2250 | } | |
2251 | md_number_to_chars (f, ip->insn_opcode, 2); | |
c5dd6aab DJ |
2252 | #ifdef OBJ_ELF |
2253 | dwarf2_emit_insn (ip->use_extend ? 4 : 2); | |
2254 | #endif | |
252b5132 RH |
2255 | } |
2256 | ||
2257 | /* Update the register mask information. */ | |
2258 | if (! mips_opts.mips16) | |
2259 | { | |
2260 | if (pinfo & INSN_WRITE_GPR_D) | |
2261 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD); | |
2262 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) | |
2263 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT); | |
2264 | if (pinfo & INSN_READ_GPR_S) | |
2265 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS); | |
2266 | if (pinfo & INSN_WRITE_GPR_31) | |
f9419b05 | 2267 | mips_gprmask |= 1 << RA; |
252b5132 RH |
2268 | if (pinfo & INSN_WRITE_FPR_D) |
2269 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD); | |
2270 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) | |
2271 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS); | |
2272 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) | |
2273 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT); | |
2274 | if ((pinfo & INSN_READ_FPR_R) != 0) | |
2275 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR); | |
2276 | if (pinfo & INSN_COP) | |
2277 | { | |
bdaaa2e1 KH |
2278 | /* We don't keep enough information to sort these cases out. |
2279 | The itbl support does keep this information however, although | |
2280 | we currently don't support itbl fprmats as part of the cop | |
2281 | instruction. May want to add this support in the future. */ | |
252b5132 RH |
2282 | } |
2283 | /* Never set the bit for $0, which is always zero. */ | |
beae10d5 | 2284 | mips_gprmask &= ~1 << 0; |
252b5132 RH |
2285 | } |
2286 | else | |
2287 | { | |
2288 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) | |
2289 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX) | |
2290 | & MIPS16OP_MASK_RX); | |
2291 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) | |
2292 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY) | |
2293 | & MIPS16OP_MASK_RY); | |
2294 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
2295 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ) | |
2296 | & MIPS16OP_MASK_RZ); | |
2297 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) | |
2298 | mips_gprmask |= 1 << TREG; | |
2299 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
2300 | mips_gprmask |= 1 << SP; | |
2301 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
2302 | mips_gprmask |= 1 << RA; | |
2303 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2304 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
2305 | if (pinfo & MIPS16_INSN_READ_Z) | |
2306 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
2307 | & MIPS16OP_MASK_MOVE32Z); | |
2308 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
2309 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
2310 | & MIPS16OP_MASK_REGR32); | |
2311 | } | |
2312 | ||
4d7206a2 | 2313 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
252b5132 RH |
2314 | { |
2315 | /* Filling the branch delay slot is more complex. We try to | |
2316 | switch the branch with the previous instruction, which we can | |
2317 | do if the previous instruction does not set up a condition | |
2318 | that the branch tests and if the branch is not itself the | |
2319 | target of any branch. */ | |
2320 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2321 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
2322 | { | |
2323 | if (mips_optimize < 2 | |
2324 | /* If we have seen .set volatile or .set nomove, don't | |
2325 | optimize. */ | |
2326 | || mips_opts.nomove != 0 | |
2327 | /* If we had to emit any NOP instructions, then we | |
2328 | already know we can not swap. */ | |
2329 | || nops != 0 | |
2330 | /* If we don't even know the previous insn, we can not | |
bdaaa2e1 | 2331 | swap. */ |
252b5132 RH |
2332 | || ! prev_insn_valid |
2333 | /* If the previous insn is already in a branch delay | |
2334 | slot, then we can not swap. */ | |
2335 | || prev_insn_is_delay_slot | |
2336 | /* If the previous previous insn was in a .set | |
2337 | noreorder, we can't swap. Actually, the MIPS | |
2338 | assembler will swap in this situation. However, gcc | |
2339 | configured -with-gnu-as will generate code like | |
2340 | .set noreorder | |
2341 | lw $4,XXX | |
2342 | .set reorder | |
2343 | INSN | |
2344 | bne $4,$0,foo | |
2345 | in which we can not swap the bne and INSN. If gcc is | |
2346 | not configured -with-gnu-as, it does not output the | |
2347 | .set pseudo-ops. We don't have to check | |
2348 | prev_insn_unreordered, because prev_insn_valid will | |
2349 | be 0 in that case. We don't want to use | |
2350 | prev_prev_insn_valid, because we do want to be able | |
2351 | to swap at the start of a function. */ | |
2352 | || prev_prev_insn_unreordered | |
2353 | /* If the branch is itself the target of a branch, we | |
2354 | can not swap. We cheat on this; all we check for is | |
2355 | whether there is a label on this instruction. If | |
2356 | there are any branches to anything other than a | |
2357 | label, users must use .set noreorder. */ | |
2358 | || insn_labels != NULL | |
895921c9 MR |
2359 | /* If the previous instruction is in a variant frag |
2360 | other than this branch's one, we cannot do the swap. | |
2361 | This does not apply to the mips16, which uses variant | |
2362 | frags for different purposes. */ | |
252b5132 | 2363 | || (! mips_opts.mips16 |
895921c9 | 2364 | && prev_insn_frag_type == rs_machine_dependent) |
252b5132 RH |
2365 | /* If the branch reads the condition codes, we don't |
2366 | even try to swap, because in the sequence | |
2367 | ctc1 $X,$31 | |
2368 | INSN | |
2369 | INSN | |
2370 | bc1t LABEL | |
2371 | we can not swap, and I don't feel like handling that | |
2372 | case. */ | |
2373 | || (! mips_opts.mips16 | |
81912461 ILT |
2374 | && (pinfo & INSN_READ_COND_CODE) |
2375 | && ! cop_interlocks) | |
252b5132 | 2376 | /* We can not swap with an instruction that requires a |
67c1ffbe | 2377 | delay slot, because the target of the branch might |
252b5132 RH |
2378 | interfere with that instruction. */ |
2379 | || (! mips_opts.mips16 | |
252b5132 | 2380 | && (prev_pinfo |
bdaaa2e1 | 2381 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2382 | & (INSN_LOAD_COPROC_DELAY |
2383 | | INSN_COPROC_MOVE_DELAY | |
81912461 ILT |
2384 | | INSN_WRITE_COND_CODE)) |
2385 | && ! cop_interlocks) | |
252b5132 | 2386 | || (! (hilo_interlocks |
048cdf86 | 2387 | || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))) |
252b5132 RH |
2388 | && (prev_pinfo |
2389 | & (INSN_READ_LO | |
2390 | | INSN_READ_HI))) | |
2391 | || (! mips_opts.mips16 | |
81912461 ILT |
2392 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
2393 | && ! gpr_interlocks) | |
252b5132 | 2394 | || (! mips_opts.mips16 |
bdaaa2e1 | 2395 | /* Itbl support may require additional care here. */ |
81912461 ILT |
2396 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY) |
2397 | && ! cop_mem_interlocks) | |
252b5132 RH |
2398 | /* We can not swap with a branch instruction. */ |
2399 | || (prev_pinfo | |
2400 | & (INSN_UNCOND_BRANCH_DELAY | |
2401 | | INSN_COND_BRANCH_DELAY | |
2402 | | INSN_COND_BRANCH_LIKELY)) | |
2403 | /* We do not swap with a trap instruction, since it | |
2404 | complicates trap handlers to have the trap | |
2405 | instruction be in a delay slot. */ | |
2406 | || (prev_pinfo & INSN_TRAP) | |
2407 | /* If the branch reads a register that the previous | |
2408 | instruction sets, we can not swap. */ | |
2409 | || (! mips_opts.mips16 | |
2410 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2411 | && insn_uses_reg (ip, | |
2412 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
2413 | & OP_MASK_RT), | |
2414 | MIPS_GR_REG)) | |
2415 | || (! mips_opts.mips16 | |
2416 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2417 | && insn_uses_reg (ip, | |
2418 | ((prev_insn.insn_opcode >> OP_SH_RD) | |
2419 | & OP_MASK_RD), | |
2420 | MIPS_GR_REG)) | |
2421 | || (mips_opts.mips16 | |
2422 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
2423 | && insn_uses_reg (ip, | |
2424 | ((prev_insn.insn_opcode | |
2425 | >> MIPS16OP_SH_RX) | |
2426 | & MIPS16OP_MASK_RX), | |
2427 | MIPS16_REG)) | |
2428 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) | |
2429 | && insn_uses_reg (ip, | |
2430 | ((prev_insn.insn_opcode | |
2431 | >> MIPS16OP_SH_RY) | |
2432 | & MIPS16OP_MASK_RY), | |
2433 | MIPS16_REG)) | |
2434 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) | |
2435 | && insn_uses_reg (ip, | |
2436 | ((prev_insn.insn_opcode | |
2437 | >> MIPS16OP_SH_RZ) | |
2438 | & MIPS16OP_MASK_RZ), | |
2439 | MIPS16_REG)) | |
2440 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) | |
2441 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
2442 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2443 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
2444 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2445 | && insn_uses_reg (ip, | |
2446 | MIPS16OP_EXTRACT_REG32R (prev_insn. | |
2447 | insn_opcode), | |
2448 | MIPS_GR_REG)))) | |
2449 | /* If the branch writes a register that the previous | |
2450 | instruction sets, we can not swap (we know that | |
2451 | branches write only to RD or to $31). */ | |
2452 | || (! mips_opts.mips16 | |
2453 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2454 | && (((pinfo & INSN_WRITE_GPR_D) | |
2455 | && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT) | |
2456 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
2457 | || ((pinfo & INSN_WRITE_GPR_31) | |
2458 | && (((prev_insn.insn_opcode >> OP_SH_RT) | |
2459 | & OP_MASK_RT) | |
f9419b05 | 2460 | == RA)))) |
252b5132 RH |
2461 | || (! mips_opts.mips16 |
2462 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2463 | && (((pinfo & INSN_WRITE_GPR_D) | |
2464 | && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD) | |
2465 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
2466 | || ((pinfo & INSN_WRITE_GPR_31) | |
2467 | && (((prev_insn.insn_opcode >> OP_SH_RD) | |
2468 | & OP_MASK_RD) | |
f9419b05 | 2469 | == RA)))) |
252b5132 RH |
2470 | || (mips_opts.mips16 |
2471 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2472 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2473 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2474 | && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode) | |
2475 | == RA)))) | |
2476 | /* If the branch writes a register that the previous | |
2477 | instruction reads, we can not swap (we know that | |
2478 | branches only write to RD or to $31). */ | |
2479 | || (! mips_opts.mips16 | |
2480 | && (pinfo & INSN_WRITE_GPR_D) | |
2481 | && insn_uses_reg (&prev_insn, | |
2482 | ((ip->insn_opcode >> OP_SH_RD) | |
2483 | & OP_MASK_RD), | |
2484 | MIPS_GR_REG)) | |
2485 | || (! mips_opts.mips16 | |
2486 | && (pinfo & INSN_WRITE_GPR_31) | |
f9419b05 | 2487 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) |
252b5132 RH |
2488 | || (mips_opts.mips16 |
2489 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2490 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) | |
2491 | /* If we are generating embedded PIC code, the branch | |
2492 | might be expanded into a sequence which uses $at, so | |
2493 | we can't swap with an instruction which reads it. */ | |
2494 | || (mips_pic == EMBEDDED_PIC | |
2495 | && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG)) | |
2496 | /* If the previous previous instruction has a load | |
2497 | delay, and sets a register that the branch reads, we | |
2498 | can not swap. */ | |
2499 | || (! mips_opts.mips16 | |
bdaaa2e1 | 2500 | /* Itbl support may require additional care here. */ |
81912461 ILT |
2501 | && (((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) |
2502 | && ! cop_interlocks) | |
2503 | || ((prev_prev_insn.insn_mo->pinfo | |
2504 | & INSN_LOAD_MEMORY_DELAY) | |
2505 | && ! gpr_interlocks)) | |
252b5132 RH |
2506 | && insn_uses_reg (ip, |
2507 | ((prev_prev_insn.insn_opcode >> OP_SH_RT) | |
2508 | & OP_MASK_RT), | |
2509 | MIPS_GR_REG)) | |
2510 | /* If one instruction sets a condition code and the | |
2511 | other one uses a condition code, we can not swap. */ | |
2512 | || ((pinfo & INSN_READ_COND_CODE) | |
2513 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
2514 | || ((pinfo & INSN_WRITE_COND_CODE) | |
2515 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
2516 | /* If the previous instruction uses the PC, we can not | |
2517 | swap. */ | |
2518 | || (mips_opts.mips16 | |
2519 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
2520 | /* If the previous instruction was extended, we can not | |
2521 | swap. */ | |
2522 | || (mips_opts.mips16 && prev_insn_extended) | |
2523 | /* If the previous instruction had a fixup in mips16 | |
2524 | mode, we can not swap. This normally means that the | |
2525 | previous instruction was a 4 byte branch anyhow. */ | |
f6688943 | 2526 | || (mips_opts.mips16 && prev_insn_fixp[0]) |
bdaaa2e1 KH |
2527 | /* If the previous instruction is a sync, sync.l, or |
2528 | sync.p, we can not swap. */ | |
f173e82e | 2529 | || (prev_pinfo & INSN_SYNC)) |
252b5132 RH |
2530 | { |
2531 | /* We could do even better for unconditional branches to | |
2532 | portions of this object file; we could pick up the | |
2533 | instruction at the destination, put it in the delay | |
2534 | slot, and bump the destination address. */ | |
2535 | emit_nop (); | |
2536 | /* Update the previous insn information. */ | |
2537 | prev_prev_insn = *ip; | |
2538 | prev_insn.insn_mo = &dummy_opcode; | |
2539 | } | |
2540 | else | |
2541 | { | |
2542 | /* It looks like we can actually do the swap. */ | |
2543 | if (! mips_opts.mips16) | |
2544 | { | |
2545 | char *prev_f; | |
2546 | char temp[4]; | |
2547 | ||
2548 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
895921c9 MR |
2549 | if (!relaxed_branch) |
2550 | { | |
2551 | /* If this is not a relaxed branch, then just | |
2552 | swap the instructions. */ | |
2553 | memcpy (temp, prev_f, 4); | |
2554 | memcpy (prev_f, f, 4); | |
2555 | memcpy (f, temp, 4); | |
2556 | } | |
2557 | else | |
2558 | { | |
2559 | /* If this is a relaxed branch, then we move the | |
2560 | instruction to be placed in the delay slot to | |
2561 | the current frag, shrinking the fixed part of | |
2562 | the originating frag. If the branch occupies | |
2563 | the tail of the latter, we move it backwards, | |
2564 | into the space freed by the moved instruction. */ | |
2565 | f = frag_more (4); | |
2566 | memcpy (f, prev_f, 4); | |
2567 | prev_insn_frag->fr_fix -= 4; | |
2568 | if (prev_insn_frag->fr_type == rs_machine_dependent) | |
2569 | memmove (prev_f, prev_f + 4, prev_insn_frag->fr_var); | |
2570 | } | |
2571 | ||
f6688943 TS |
2572 | if (prev_insn_fixp[0]) |
2573 | { | |
2574 | prev_insn_fixp[0]->fx_frag = frag_now; | |
2575 | prev_insn_fixp[0]->fx_where = f - frag_now->fr_literal; | |
2576 | } | |
2577 | if (prev_insn_fixp[1]) | |
2578 | { | |
2579 | prev_insn_fixp[1]->fx_frag = frag_now; | |
2580 | prev_insn_fixp[1]->fx_where = f - frag_now->fr_literal; | |
2581 | } | |
2582 | if (prev_insn_fixp[2]) | |
252b5132 | 2583 | { |
f6688943 TS |
2584 | prev_insn_fixp[2]->fx_frag = frag_now; |
2585 | prev_insn_fixp[2]->fx_where = f - frag_now->fr_literal; | |
252b5132 | 2586 | } |
f5040a92 AO |
2587 | if (prev_insn_fixp[0] && HAVE_NEWABI |
2588 | && prev_insn_frag != frag_now | |
2589 | && (prev_insn_fixp[0]->fx_r_type | |
2590 | == BFD_RELOC_MIPS_GOT_DISP | |
2591 | || (prev_insn_fixp[0]->fx_r_type | |
2592 | == BFD_RELOC_MIPS_CALL16))) | |
2593 | { | |
2594 | /* To avoid confusion in tc_gen_reloc, we must | |
2595 | ensure that this does not become a variant | |
2596 | frag. */ | |
2597 | force_new_frag = TRUE; | |
2598 | } | |
895921c9 MR |
2599 | |
2600 | if (!relaxed_branch) | |
f6688943 | 2601 | { |
895921c9 MR |
2602 | if (fixp[0]) |
2603 | { | |
2604 | fixp[0]->fx_frag = prev_insn_frag; | |
2605 | fixp[0]->fx_where = prev_insn_where; | |
2606 | } | |
2607 | if (fixp[1]) | |
2608 | { | |
2609 | fixp[1]->fx_frag = prev_insn_frag; | |
2610 | fixp[1]->fx_where = prev_insn_where; | |
2611 | } | |
2612 | if (fixp[2]) | |
2613 | { | |
2614 | fixp[2]->fx_frag = prev_insn_frag; | |
2615 | fixp[2]->fx_where = prev_insn_where; | |
2616 | } | |
f6688943 | 2617 | } |
895921c9 | 2618 | else if (prev_insn_frag->fr_type == rs_machine_dependent) |
f6688943 | 2619 | { |
895921c9 MR |
2620 | if (fixp[0]) |
2621 | fixp[0]->fx_where -= 4; | |
2622 | if (fixp[1]) | |
2623 | fixp[1]->fx_where -= 4; | |
2624 | if (fixp[2]) | |
2625 | fixp[2]->fx_where -= 4; | |
252b5132 RH |
2626 | } |
2627 | } | |
2628 | else | |
2629 | { | |
2630 | char *prev_f; | |
2631 | char temp[2]; | |
2632 | ||
f6688943 TS |
2633 | assert (prev_insn_fixp[0] == NULL); |
2634 | assert (prev_insn_fixp[1] == NULL); | |
2635 | assert (prev_insn_fixp[2] == NULL); | |
252b5132 RH |
2636 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; |
2637 | memcpy (temp, prev_f, 2); | |
2638 | memcpy (prev_f, f, 2); | |
f6688943 | 2639 | if (*reloc_type != BFD_RELOC_MIPS16_JMP) |
252b5132 | 2640 | { |
f6688943 | 2641 | assert (*reloc_type == BFD_RELOC_UNUSED); |
252b5132 RH |
2642 | memcpy (f, temp, 2); |
2643 | } | |
2644 | else | |
2645 | { | |
2646 | memcpy (f, f + 2, 2); | |
2647 | memcpy (f + 2, temp, 2); | |
2648 | } | |
f6688943 TS |
2649 | if (fixp[0]) |
2650 | { | |
2651 | fixp[0]->fx_frag = prev_insn_frag; | |
2652 | fixp[0]->fx_where = prev_insn_where; | |
2653 | } | |
2654 | if (fixp[1]) | |
2655 | { | |
2656 | fixp[1]->fx_frag = prev_insn_frag; | |
2657 | fixp[1]->fx_where = prev_insn_where; | |
2658 | } | |
2659 | if (fixp[2]) | |
252b5132 | 2660 | { |
f6688943 TS |
2661 | fixp[2]->fx_frag = prev_insn_frag; |
2662 | fixp[2]->fx_where = prev_insn_where; | |
252b5132 RH |
2663 | } |
2664 | } | |
2665 | ||
2666 | /* Update the previous insn information; leave prev_insn | |
2667 | unchanged. */ | |
2668 | prev_prev_insn = *ip; | |
2669 | } | |
2670 | prev_insn_is_delay_slot = 1; | |
2671 | ||
2672 | /* If that was an unconditional branch, forget the previous | |
2673 | insn information. */ | |
2674 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2675 | { | |
2676 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2677 | prev_insn.insn_mo = &dummy_opcode; | |
2678 | } | |
2679 | ||
f6688943 TS |
2680 | prev_insn_fixp[0] = NULL; |
2681 | prev_insn_fixp[1] = NULL; | |
2682 | prev_insn_fixp[2] = NULL; | |
2683 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; | |
2684 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2685 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2686 | prev_insn_extended = 0; |
2687 | } | |
2688 | else if (pinfo & INSN_COND_BRANCH_LIKELY) | |
2689 | { | |
2690 | /* We don't yet optimize a branch likely. What we should do | |
2691 | is look at the target, copy the instruction found there | |
2692 | into the delay slot, and increment the branch to jump to | |
2693 | the next instruction. */ | |
2694 | emit_nop (); | |
2695 | /* Update the previous insn information. */ | |
2696 | prev_prev_insn = *ip; | |
2697 | prev_insn.insn_mo = &dummy_opcode; | |
f6688943 TS |
2698 | prev_insn_fixp[0] = NULL; |
2699 | prev_insn_fixp[1] = NULL; | |
2700 | prev_insn_fixp[2] = NULL; | |
2701 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; | |
2702 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2703 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2704 | prev_insn_extended = 0; |
2705 | } | |
2706 | else | |
2707 | { | |
2708 | /* Update the previous insn information. */ | |
2709 | if (nops > 0) | |
2710 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2711 | else | |
2712 | prev_prev_insn = prev_insn; | |
2713 | prev_insn = *ip; | |
2714 | ||
2715 | /* Any time we see a branch, we always fill the delay slot | |
2716 | immediately; since this insn is not a branch, we know it | |
2717 | is not in a delay slot. */ | |
2718 | prev_insn_is_delay_slot = 0; | |
2719 | ||
f6688943 TS |
2720 | prev_insn_fixp[0] = fixp[0]; |
2721 | prev_insn_fixp[1] = fixp[1]; | |
2722 | prev_insn_fixp[2] = fixp[2]; | |
2723 | prev_insn_reloc_type[0] = reloc_type[0]; | |
2724 | prev_insn_reloc_type[1] = reloc_type[1]; | |
2725 | prev_insn_reloc_type[2] = reloc_type[2]; | |
252b5132 RH |
2726 | if (mips_opts.mips16) |
2727 | prev_insn_extended = (ip->use_extend | |
f6688943 | 2728 | || *reloc_type > BFD_RELOC_UNUSED); |
252b5132 RH |
2729 | } |
2730 | ||
2731 | prev_prev_insn_unreordered = prev_insn_unreordered; | |
2732 | prev_insn_unreordered = 0; | |
2733 | prev_insn_frag = frag_now; | |
2734 | prev_insn_where = f - frag_now->fr_literal; | |
2735 | prev_insn_valid = 1; | |
2736 | } | |
4d7206a2 | 2737 | else if (mips_relax.sequence != 2) |
252b5132 RH |
2738 | { |
2739 | /* We need to record a bit of information even when we are not | |
2740 | reordering, in order to determine the base address for mips16 | |
2741 | PC relative relocs. */ | |
2742 | prev_prev_insn = prev_insn; | |
2743 | prev_insn = *ip; | |
f6688943 TS |
2744 | prev_insn_reloc_type[0] = reloc_type[0]; |
2745 | prev_insn_reloc_type[1] = reloc_type[1]; | |
2746 | prev_insn_reloc_type[2] = reloc_type[2]; | |
252b5132 RH |
2747 | prev_prev_insn_unreordered = prev_insn_unreordered; |
2748 | prev_insn_unreordered = 1; | |
2749 | } | |
2750 | ||
2751 | /* We just output an insn, so the next one doesn't have a label. */ | |
2752 | mips_clear_insn_labels (); | |
252b5132 RH |
2753 | } |
2754 | ||
2755 | /* This function forgets that there was any previous instruction or | |
2756 | label. If PRESERVE is non-zero, it remembers enough information to | |
bdaaa2e1 | 2757 | know whether nops are needed before a noreorder section. */ |
252b5132 RH |
2758 | |
2759 | static void | |
17a2f251 | 2760 | mips_no_prev_insn (int preserve) |
252b5132 RH |
2761 | { |
2762 | if (! preserve) | |
2763 | { | |
2764 | prev_insn.insn_mo = &dummy_opcode; | |
2765 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2766 | prev_nop_frag = NULL; | |
2767 | prev_nop_frag_holds = 0; | |
2768 | prev_nop_frag_required = 0; | |
2769 | prev_nop_frag_since = 0; | |
2770 | } | |
2771 | prev_insn_valid = 0; | |
2772 | prev_insn_is_delay_slot = 0; | |
2773 | prev_insn_unreordered = 0; | |
2774 | prev_insn_extended = 0; | |
f6688943 TS |
2775 | prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; |
2776 | prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; | |
2777 | prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2778 | prev_prev_insn_unreordered = 0; |
2779 | mips_clear_insn_labels (); | |
2780 | } | |
2781 | ||
2782 | /* This function must be called whenever we turn on noreorder or emit | |
2783 | something other than instructions. It inserts any NOPS which might | |
2784 | be needed by the previous instruction, and clears the information | |
2785 | kept for the previous instructions. The INSNS parameter is true if | |
bdaaa2e1 | 2786 | instructions are to follow. */ |
252b5132 RH |
2787 | |
2788 | static void | |
17a2f251 | 2789 | mips_emit_delays (bfd_boolean insns) |
252b5132 RH |
2790 | { |
2791 | if (! mips_opts.noreorder) | |
2792 | { | |
2793 | int nops; | |
2794 | ||
2795 | nops = 0; | |
2796 | if ((! mips_opts.mips16 | |
81912461 ILT |
2797 | && ((prev_insn.insn_mo->pinfo |
2798 | & (INSN_LOAD_COPROC_DELAY | |
2799 | | INSN_COPROC_MOVE_DELAY | |
2800 | | INSN_WRITE_COND_CODE)) | |
2801 | && ! cop_interlocks)) | |
252b5132 RH |
2802 | || (! hilo_interlocks |
2803 | && (prev_insn.insn_mo->pinfo | |
2804 | & (INSN_READ_LO | |
2805 | | INSN_READ_HI))) | |
2806 | || (! mips_opts.mips16 | |
81912461 ILT |
2807 | && (prev_insn.insn_mo->pinfo & INSN_LOAD_MEMORY_DELAY) |
2808 | && ! gpr_interlocks) | |
252b5132 | 2809 | || (! mips_opts.mips16 |
81912461 ILT |
2810 | && (prev_insn.insn_mo->pinfo & INSN_COPROC_MEMORY_DELAY) |
2811 | && ! cop_mem_interlocks)) | |
252b5132 | 2812 | { |
beae10d5 | 2813 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2814 | ++nops; |
2815 | if ((! mips_opts.mips16 | |
81912461 ILT |
2816 | && ((prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) |
2817 | && ! cop_interlocks)) | |
252b5132 RH |
2818 | || (! hilo_interlocks |
2819 | && ((prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
2820 | || (prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
2821 | ++nops; | |
2822 | ||
2823 | if (prev_insn_unreordered) | |
2824 | nops = 0; | |
2825 | } | |
2826 | else if ((! mips_opts.mips16 | |
81912461 ILT |
2827 | && ((prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) |
2828 | && ! cop_interlocks)) | |
252b5132 RH |
2829 | || (! hilo_interlocks |
2830 | && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
2831 | || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
2832 | { | |
beae10d5 | 2833 | /* Itbl support may require additional care here. */ |
252b5132 RH |
2834 | if (! prev_prev_insn_unreordered) |
2835 | ++nops; | |
2836 | } | |
2837 | ||
d766e8ec | 2838 | if (mips_fix_vr4120 && prev_insn.insn_mo->name) |
60b63b72 RS |
2839 | { |
2840 | int min_nops = 0; | |
2841 | const char *pn = prev_insn.insn_mo->name; | |
2842 | if (strncmp(pn, "macc", 4) == 0 | |
2843 | || strncmp(pn, "dmacc", 5) == 0 | |
2844 | || strncmp(pn, "dmult", 5) == 0) | |
2845 | { | |
2846 | min_nops = 1; | |
2847 | } | |
2848 | if (nops < min_nops) | |
2849 | nops = min_nops; | |
2850 | } | |
2851 | ||
252b5132 RH |
2852 | if (nops > 0) |
2853 | { | |
2854 | struct insn_label_list *l; | |
2855 | ||
2856 | if (insns) | |
2857 | { | |
2858 | /* Record the frag which holds the nop instructions, so | |
2859 | that we can remove them if we don't need them. */ | |
2860 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); | |
2861 | prev_nop_frag = frag_now; | |
2862 | prev_nop_frag_holds = nops; | |
2863 | prev_nop_frag_required = 0; | |
2864 | prev_nop_frag_since = 0; | |
2865 | } | |
2866 | ||
2867 | for (; nops > 0; --nops) | |
2868 | emit_nop (); | |
2869 | ||
2870 | if (insns) | |
2871 | { | |
2872 | /* Move on to a new frag, so that it is safe to simply | |
bdaaa2e1 | 2873 | decrease the size of prev_nop_frag. */ |
252b5132 RH |
2874 | frag_wane (frag_now); |
2875 | frag_new (0); | |
2876 | } | |
2877 | ||
2878 | for (l = insn_labels; l != NULL; l = l->next) | |
2879 | { | |
98aa84af AM |
2880 | valueT val; |
2881 | ||
252b5132 | 2882 | assert (S_GET_SEGMENT (l->label) == now_seg); |
49309057 | 2883 | symbol_set_frag (l->label, frag_now); |
98aa84af | 2884 | val = (valueT) frag_now_fix (); |
252b5132 RH |
2885 | /* mips16 text labels are stored as odd. */ |
2886 | if (mips_opts.mips16) | |
f9419b05 | 2887 | ++val; |
98aa84af | 2888 | S_SET_VALUE (l->label, val); |
252b5132 RH |
2889 | } |
2890 | } | |
2891 | } | |
2892 | ||
2893 | /* Mark instruction labels in mips16 mode. */ | |
f9419b05 | 2894 | if (insns) |
252b5132 RH |
2895 | mips16_mark_labels (); |
2896 | ||
2897 | mips_no_prev_insn (insns); | |
2898 | } | |
2899 | ||
584892a6 RS |
2900 | /* Set up global variables for the start of a new macro. */ |
2901 | ||
2902 | static void | |
2903 | macro_start (void) | |
2904 | { | |
2905 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
2906 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder | |
2907 | && (prev_insn.insn_mo->pinfo | |
2908 | & (INSN_UNCOND_BRANCH_DELAY | |
2909 | | INSN_COND_BRANCH_DELAY | |
2910 | | INSN_COND_BRANCH_LIKELY)) != 0); | |
2911 | } | |
2912 | ||
2913 | /* Given that a macro is longer than 4 bytes, return the appropriate warning | |
2914 | for it. Return null if no warning is needed. SUBTYPE is a bitmask of | |
2915 | RELAX_DELAY_SLOT and RELAX_NOMACRO. */ | |
2916 | ||
2917 | static const char * | |
2918 | macro_warning (relax_substateT subtype) | |
2919 | { | |
2920 | if (subtype & RELAX_DELAY_SLOT) | |
2921 | return _("Macro instruction expanded into multiple instructions" | |
2922 | " in a branch delay slot"); | |
2923 | else if (subtype & RELAX_NOMACRO) | |
2924 | return _("Macro instruction expanded into multiple instructions"); | |
2925 | else | |
2926 | return 0; | |
2927 | } | |
2928 | ||
2929 | /* Finish up a macro. Emit warnings as appropriate. */ | |
2930 | ||
2931 | static void | |
2932 | macro_end (void) | |
2933 | { | |
2934 | if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4) | |
2935 | { | |
2936 | relax_substateT subtype; | |
2937 | ||
2938 | /* Set up the relaxation warning flags. */ | |
2939 | subtype = 0; | |
2940 | if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0]) | |
2941 | subtype |= RELAX_SECOND_LONGER; | |
2942 | if (mips_opts.warn_about_macros) | |
2943 | subtype |= RELAX_NOMACRO; | |
2944 | if (mips_macro_warning.delay_slot_p) | |
2945 | subtype |= RELAX_DELAY_SLOT; | |
2946 | ||
2947 | if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4) | |
2948 | { | |
2949 | /* Either the macro has a single implementation or both | |
2950 | implementations are longer than 4 bytes. Emit the | |
2951 | warning now. */ | |
2952 | const char *msg = macro_warning (subtype); | |
2953 | if (msg != 0) | |
2954 | as_warn (msg); | |
2955 | } | |
2956 | else | |
2957 | { | |
2958 | /* One implementation might need a warning but the other | |
2959 | definitely doesn't. */ | |
2960 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
2961 | } | |
2962 | } | |
2963 | } | |
2964 | ||
252b5132 RH |
2965 | /* Build an instruction created by a macro expansion. This is passed |
2966 | a pointer to the count of instructions created so far, an | |
2967 | expression, the name of the instruction to build, an operand format | |
2968 | string, and corresponding arguments. */ | |
2969 | ||
252b5132 | 2970 | static void |
67c0d1eb | 2971 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 RH |
2972 | { |
2973 | struct mips_cl_insn insn; | |
f6688943 | 2974 | bfd_reloc_code_real_type r[3]; |
252b5132 | 2975 | va_list args; |
252b5132 | 2976 | |
252b5132 | 2977 | va_start (args, fmt); |
252b5132 | 2978 | |
252b5132 RH |
2979 | if (mips_opts.mips16) |
2980 | { | |
67c0d1eb | 2981 | mips16_macro_build (ep, name, fmt, args); |
252b5132 RH |
2982 | va_end (args); |
2983 | return; | |
2984 | } | |
2985 | ||
f6688943 TS |
2986 | r[0] = BFD_RELOC_UNUSED; |
2987 | r[1] = BFD_RELOC_UNUSED; | |
2988 | r[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
2989 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); |
2990 | assert (insn.insn_mo); | |
2991 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2992 | ||
2993 | /* Search until we get a match for NAME. */ | |
2994 | while (1) | |
2995 | { | |
b34976b6 | 2996 | /* It is assumed here that macros will never generate |
deec1734 | 2997 | MDMX or MIPS-3D instructions. */ |
252b5132 RH |
2998 | if (strcmp (fmt, insn.insn_mo->args) == 0 |
2999 | && insn.insn_mo->pinfo != INSN_MACRO | |
aec421e0 TS |
3000 | && OPCODE_IS_MEMBER (insn.insn_mo, |
3001 | (mips_opts.isa | |
3396de36 | 3002 | | (file_ase_mips16 ? INSN_MIPS16 : 0)), |
fef14a42 TS |
3003 | mips_opts.arch) |
3004 | && (mips_opts.arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0)) | |
252b5132 RH |
3005 | break; |
3006 | ||
3007 | ++insn.insn_mo; | |
3008 | assert (insn.insn_mo->name); | |
3009 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3010 | } | |
3011 | ||
3012 | insn.insn_opcode = insn.insn_mo->match; | |
3013 | for (;;) | |
3014 | { | |
3015 | switch (*fmt++) | |
3016 | { | |
3017 | case '\0': | |
3018 | break; | |
3019 | ||
3020 | case ',': | |
3021 | case '(': | |
3022 | case ')': | |
3023 | continue; | |
3024 | ||
5f74bc13 CD |
3025 | case '+': |
3026 | switch (*fmt++) | |
3027 | { | |
3028 | case 'A': | |
3029 | case 'E': | |
3030 | insn.insn_opcode |= (va_arg (args, int) | |
3031 | & OP_MASK_SHAMT) << OP_SH_SHAMT; | |
3032 | continue; | |
3033 | ||
3034 | case 'B': | |
3035 | case 'F': | |
3036 | /* Note that in the macro case, these arguments are already | |
3037 | in MSB form. (When handling the instruction in the | |
3038 | non-macro case, these arguments are sizes from which | |
3039 | MSB values must be calculated.) */ | |
3040 | insn.insn_opcode |= (va_arg (args, int) | |
3041 | & OP_MASK_INSMSB) << OP_SH_INSMSB; | |
3042 | continue; | |
3043 | ||
3044 | case 'C': | |
3045 | case 'G': | |
3046 | case 'H': | |
3047 | /* Note that in the macro case, these arguments are already | |
3048 | in MSBD form. (When handling the instruction in the | |
3049 | non-macro case, these arguments are sizes from which | |
3050 | MSBD values must be calculated.) */ | |
3051 | insn.insn_opcode |= (va_arg (args, int) | |
3052 | & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD; | |
3053 | continue; | |
3054 | ||
3055 | default: | |
3056 | internalError (); | |
3057 | } | |
3058 | continue; | |
3059 | ||
252b5132 RH |
3060 | case 't': |
3061 | case 'w': | |
3062 | case 'E': | |
38487616 | 3063 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RT; |
252b5132 RH |
3064 | continue; |
3065 | ||
3066 | case 'c': | |
38487616 TS |
3067 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE; |
3068 | continue; | |
3069 | ||
252b5132 RH |
3070 | case 'T': |
3071 | case 'W': | |
38487616 | 3072 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FT; |
252b5132 RH |
3073 | continue; |
3074 | ||
3075 | case 'd': | |
3076 | case 'G': | |
af7ee8bf | 3077 | case 'K': |
38487616 | 3078 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RD; |
252b5132 RH |
3079 | continue; |
3080 | ||
4372b673 NC |
3081 | case 'U': |
3082 | { | |
3083 | int tmp = va_arg (args, int); | |
3084 | ||
38487616 TS |
3085 | insn.insn_opcode |= tmp << OP_SH_RT; |
3086 | insn.insn_opcode |= tmp << OP_SH_RD; | |
beae10d5 | 3087 | continue; |
4372b673 NC |
3088 | } |
3089 | ||
252b5132 RH |
3090 | case 'V': |
3091 | case 'S': | |
38487616 | 3092 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FS; |
252b5132 RH |
3093 | continue; |
3094 | ||
3095 | case 'z': | |
3096 | continue; | |
3097 | ||
3098 | case '<': | |
38487616 | 3099 | insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT; |
252b5132 RH |
3100 | continue; |
3101 | ||
3102 | case 'D': | |
38487616 | 3103 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FD; |
252b5132 RH |
3104 | continue; |
3105 | ||
3106 | case 'B': | |
38487616 | 3107 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20; |
252b5132 RH |
3108 | continue; |
3109 | ||
4372b673 | 3110 | case 'J': |
38487616 | 3111 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19; |
4372b673 NC |
3112 | continue; |
3113 | ||
252b5132 | 3114 | case 'q': |
38487616 | 3115 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2; |
252b5132 RH |
3116 | continue; |
3117 | ||
3118 | case 'b': | |
3119 | case 's': | |
3120 | case 'r': | |
3121 | case 'v': | |
38487616 | 3122 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RS; |
252b5132 RH |
3123 | continue; |
3124 | ||
3125 | case 'i': | |
3126 | case 'j': | |
3127 | case 'o': | |
f6688943 | 3128 | *r = (bfd_reloc_code_real_type) va_arg (args, int); |
cdf6fd85 | 3129 | assert (*r == BFD_RELOC_GPREL16 |
f6688943 TS |
3130 | || *r == BFD_RELOC_MIPS_LITERAL |
3131 | || *r == BFD_RELOC_MIPS_HIGHER | |
3132 | || *r == BFD_RELOC_HI16_S | |
3133 | || *r == BFD_RELOC_LO16 | |
3134 | || *r == BFD_RELOC_MIPS_GOT16 | |
3135 | || *r == BFD_RELOC_MIPS_CALL16 | |
438c16b8 TS |
3136 | || *r == BFD_RELOC_MIPS_GOT_DISP |
3137 | || *r == BFD_RELOC_MIPS_GOT_PAGE | |
3138 | || *r == BFD_RELOC_MIPS_GOT_OFST | |
f6688943 TS |
3139 | || *r == BFD_RELOC_MIPS_GOT_LO16 |
3140 | || *r == BFD_RELOC_MIPS_CALL_LO16 | |
252b5132 | 3141 | || (ep->X_op == O_subtract |
f6688943 | 3142 | && *r == BFD_RELOC_PCREL_LO16)); |
252b5132 RH |
3143 | continue; |
3144 | ||
3145 | case 'u': | |
f6688943 | 3146 | *r = (bfd_reloc_code_real_type) va_arg (args, int); |
252b5132 RH |
3147 | assert (ep != NULL |
3148 | && (ep->X_op == O_constant | |
3149 | || (ep->X_op == O_symbol | |
f6688943 TS |
3150 | && (*r == BFD_RELOC_MIPS_HIGHEST |
3151 | || *r == BFD_RELOC_HI16_S | |
3152 | || *r == BFD_RELOC_HI16 | |
3153 | || *r == BFD_RELOC_GPREL16 | |
3154 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
3155 | || *r == BFD_RELOC_MIPS_CALL_HI16)) | |
252b5132 | 3156 | || (ep->X_op == O_subtract |
f6688943 | 3157 | && *r == BFD_RELOC_PCREL_HI16_S))); |
252b5132 RH |
3158 | continue; |
3159 | ||
3160 | case 'p': | |
3161 | assert (ep != NULL); | |
3162 | /* | |
3163 | * This allows macro() to pass an immediate expression for | |
3164 | * creating short branches without creating a symbol. | |
0b25d3e6 AO |
3165 | * Note that the expression still might come from the assembly |
3166 | * input, in which case the value is not checked for range nor | |
3167 | * is a relocation entry generated (yuck). | |
252b5132 RH |
3168 | */ |
3169 | if (ep->X_op == O_constant) | |
3170 | { | |
3171 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
3172 | ep = NULL; | |
3173 | } | |
3174 | else | |
0b25d3e6 | 3175 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
3176 | continue; |
3177 | ||
3178 | case 'a': | |
3179 | assert (ep != NULL); | |
f6688943 | 3180 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
3181 | continue; |
3182 | ||
3183 | case 'C': | |
3184 | insn.insn_opcode |= va_arg (args, unsigned long); | |
3185 | continue; | |
3186 | ||
3187 | default: | |
3188 | internalError (); | |
3189 | } | |
3190 | break; | |
3191 | } | |
3192 | va_end (args); | |
f6688943 | 3193 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3194 | |
4d7206a2 | 3195 | append_insn (&insn, ep, r); |
252b5132 RH |
3196 | } |
3197 | ||
3198 | static void | |
67c0d1eb | 3199 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
17a2f251 | 3200 | va_list args) |
252b5132 RH |
3201 | { |
3202 | struct mips_cl_insn insn; | |
f6688943 TS |
3203 | bfd_reloc_code_real_type r[3] |
3204 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 3205 | |
252b5132 RH |
3206 | insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
3207 | assert (insn.insn_mo); | |
3208 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3209 | ||
3210 | while (strcmp (fmt, insn.insn_mo->args) != 0 | |
3211 | || insn.insn_mo->pinfo == INSN_MACRO) | |
3212 | { | |
3213 | ++insn.insn_mo; | |
3214 | assert (insn.insn_mo->name); | |
3215 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3216 | } | |
3217 | ||
3218 | insn.insn_opcode = insn.insn_mo->match; | |
b34976b6 | 3219 | insn.use_extend = FALSE; |
252b5132 RH |
3220 | |
3221 | for (;;) | |
3222 | { | |
3223 | int c; | |
3224 | ||
3225 | c = *fmt++; | |
3226 | switch (c) | |
3227 | { | |
3228 | case '\0': | |
3229 | break; | |
3230 | ||
3231 | case ',': | |
3232 | case '(': | |
3233 | case ')': | |
3234 | continue; | |
3235 | ||
3236 | case 'y': | |
3237 | case 'w': | |
3238 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY; | |
3239 | continue; | |
3240 | ||
3241 | case 'x': | |
3242 | case 'v': | |
3243 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX; | |
3244 | continue; | |
3245 | ||
3246 | case 'z': | |
3247 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ; | |
3248 | continue; | |
3249 | ||
3250 | case 'Z': | |
3251 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z; | |
3252 | continue; | |
3253 | ||
3254 | case '0': | |
3255 | case 'S': | |
3256 | case 'P': | |
3257 | case 'R': | |
3258 | continue; | |
3259 | ||
3260 | case 'X': | |
3261 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32; | |
3262 | continue; | |
3263 | ||
3264 | case 'Y': | |
3265 | { | |
3266 | int regno; | |
3267 | ||
3268 | regno = va_arg (args, int); | |
3269 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
3270 | insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
3271 | } | |
3272 | continue; | |
3273 | ||
3274 | case '<': | |
3275 | case '>': | |
3276 | case '4': | |
3277 | case '5': | |
3278 | case 'H': | |
3279 | case 'W': | |
3280 | case 'D': | |
3281 | case 'j': | |
3282 | case '8': | |
3283 | case 'V': | |
3284 | case 'C': | |
3285 | case 'U': | |
3286 | case 'k': | |
3287 | case 'K': | |
3288 | case 'p': | |
3289 | case 'q': | |
3290 | { | |
3291 | assert (ep != NULL); | |
3292 | ||
3293 | if (ep->X_op != O_constant) | |
874e8986 | 3294 | *r = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
3295 | else |
3296 | { | |
b34976b6 AM |
3297 | mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE, |
3298 | FALSE, &insn.insn_opcode, &insn.use_extend, | |
c4e7957c | 3299 | &insn.extend); |
252b5132 | 3300 | ep = NULL; |
f6688943 | 3301 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
3302 | } |
3303 | } | |
3304 | continue; | |
3305 | ||
3306 | case '6': | |
3307 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6; | |
3308 | continue; | |
3309 | } | |
3310 | ||
3311 | break; | |
3312 | } | |
3313 | ||
f6688943 | 3314 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3315 | |
4d7206a2 | 3316 | append_insn (&insn, ep, r); |
252b5132 RH |
3317 | } |
3318 | ||
438c16b8 TS |
3319 | /* |
3320 | * Generate a "jalr" instruction with a relocation hint to the called | |
3321 | * function. This occurs in NewABI PIC code. | |
3322 | */ | |
3323 | static void | |
67c0d1eb | 3324 | macro_build_jalr (expressionS *ep) |
438c16b8 | 3325 | { |
685736be | 3326 | char *f = NULL; |
b34976b6 | 3327 | |
438c16b8 | 3328 | if (HAVE_NEWABI) |
f21f8242 | 3329 | { |
cc3d92a5 | 3330 | frag_grow (8); |
f21f8242 AO |
3331 | f = frag_more (0); |
3332 | } | |
67c0d1eb | 3333 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); |
438c16b8 | 3334 | if (HAVE_NEWABI) |
f21f8242 | 3335 | fix_new_exp (frag_now, f - frag_now->fr_literal, |
a105a300 | 3336 | 4, ep, FALSE, BFD_RELOC_MIPS_JALR); |
438c16b8 TS |
3337 | } |
3338 | ||
252b5132 RH |
3339 | /* |
3340 | * Generate a "lui" instruction. | |
3341 | */ | |
3342 | static void | |
67c0d1eb | 3343 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 RH |
3344 | { |
3345 | expressionS high_expr; | |
3346 | struct mips_cl_insn insn; | |
f6688943 TS |
3347 | bfd_reloc_code_real_type r[3] |
3348 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
5a38dc70 AM |
3349 | const char *name = "lui"; |
3350 | const char *fmt = "t,u"; | |
252b5132 RH |
3351 | |
3352 | assert (! mips_opts.mips16); | |
3353 | ||
4d7206a2 | 3354 | high_expr = *ep; |
252b5132 RH |
3355 | |
3356 | if (high_expr.X_op == O_constant) | |
3357 | { | |
3358 | /* we can compute the instruction now without a relocation entry */ | |
e7d556df TS |
3359 | high_expr.X_add_number = ((high_expr.X_add_number + 0x8000) |
3360 | >> 16) & 0xffff; | |
f6688943 | 3361 | *r = BFD_RELOC_UNUSED; |
252b5132 | 3362 | } |
78e1bb40 | 3363 | else |
252b5132 RH |
3364 | { |
3365 | assert (ep->X_op == O_symbol); | |
3366 | /* _gp_disp is a special case, used from s_cpload. */ | |
3367 | assert (mips_pic == NO_PIC | |
78e1bb40 AO |
3368 | || (! HAVE_NEWABI |
3369 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)); | |
f6688943 | 3370 | *r = BFD_RELOC_HI16_S; |
252b5132 RH |
3371 | } |
3372 | ||
252b5132 RH |
3373 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); |
3374 | assert (insn.insn_mo); | |
3375 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3376 | assert (strcmp (fmt, insn.insn_mo->args) == 0); | |
3377 | ||
3378 | insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT); | |
f6688943 | 3379 | if (*r == BFD_RELOC_UNUSED) |
252b5132 RH |
3380 | { |
3381 | insn.insn_opcode |= high_expr.X_add_number; | |
4d7206a2 | 3382 | append_insn (&insn, NULL, r); |
252b5132 RH |
3383 | } |
3384 | else | |
4d7206a2 | 3385 | append_insn (&insn, &high_expr, r); |
252b5132 RH |
3386 | } |
3387 | ||
885add95 CD |
3388 | /* Generate a sequence of instructions to do a load or store from a constant |
3389 | offset off of a base register (breg) into/from a target register (treg), | |
3390 | using AT if necessary. */ | |
3391 | static void | |
67c0d1eb RS |
3392 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
3393 | int treg, int breg, int dbl) | |
885add95 CD |
3394 | { |
3395 | assert (ep->X_op == O_constant); | |
3396 | ||
256ab948 | 3397 | /* Sign-extending 32-bit constants makes their handling easier. */ |
d17e7bce TS |
3398 | if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff)) |
3399 | == ~((bfd_vma) 0x7fffffff))) | |
ae826530 | 3400 | { |
d17e7bce | 3401 | if (ep->X_add_number & ~((bfd_vma) 0xffffffff)) |
1b8e29e5 | 3402 | as_bad (_("constant too large")); |
ae826530 | 3403 | |
1b8e29e5 TS |
3404 | ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000) |
3405 | - 0x80000000); | |
ae826530 | 3406 | } |
256ab948 | 3407 | |
67c1ffbe | 3408 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 3409 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
3410 | as_warn (_("operand overflow")); |
3411 | ||
3412 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
3413 | { | |
3414 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 3415 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
3416 | } |
3417 | else | |
3418 | { | |
3419 | /* 32-bit offset, need multiple instructions and AT, like: | |
3420 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
3421 | addu $tempreg,$tempreg,$breg | |
3422 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
3423 | to handle the complete offset. */ | |
67c0d1eb RS |
3424 | macro_build_lui (ep, AT); |
3425 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
3426 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 CD |
3427 | |
3428 | if (mips_opts.noat) | |
3429 | as_warn (_("Macro used $at after \".set noat\"")); | |
3430 | } | |
3431 | } | |
3432 | ||
252b5132 RH |
3433 | /* set_at() |
3434 | * Generates code to set the $at register to true (one) | |
3435 | * if reg is less than the immediate expression. | |
3436 | */ | |
3437 | static void | |
67c0d1eb | 3438 | set_at (int reg, int unsignedp) |
252b5132 RH |
3439 | { |
3440 | if (imm_expr.X_op == O_constant | |
3441 | && imm_expr.X_add_number >= -0x8000 | |
3442 | && imm_expr.X_add_number < 0x8000) | |
67c0d1eb RS |
3443 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
3444 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
3445 | else |
3446 | { | |
67c0d1eb RS |
3447 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
3448 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); | |
252b5132 RH |
3449 | } |
3450 | } | |
3451 | ||
13757d0c TS |
3452 | static void |
3453 | normalize_constant_expr (expressionS *ex) | |
3454 | { | |
3455 | if (ex->X_op == O_constant && HAVE_32BIT_GPRS) | |
3456 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
3457 | - 0x80000000); | |
3458 | } | |
3459 | ||
252b5132 RH |
3460 | /* Warn if an expression is not a constant. */ |
3461 | ||
3462 | static void | |
17a2f251 | 3463 | check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) |
252b5132 RH |
3464 | { |
3465 | if (ex->X_op == O_big) | |
3466 | as_bad (_("unsupported large constant")); | |
3467 | else if (ex->X_op != O_constant) | |
3468 | as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name); | |
13757d0c TS |
3469 | |
3470 | normalize_constant_expr (ex); | |
252b5132 RH |
3471 | } |
3472 | ||
3473 | /* Count the leading zeroes by performing a binary chop. This is a | |
3474 | bulky bit of source, but performance is a LOT better for the | |
3475 | majority of values than a simple loop to count the bits: | |
3476 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
3477 | if ((v) & (1 << (31 - lcnt))) | |
3478 | break; | |
3479 | However it is not code size friendly, and the gain will drop a bit | |
3480 | on certain cached systems. | |
3481 | */ | |
3482 | #define COUNT_TOP_ZEROES(v) \ | |
3483 | (((v) & ~0xffff) == 0 \ | |
3484 | ? ((v) & ~0xff) == 0 \ | |
3485 | ? ((v) & ~0xf) == 0 \ | |
3486 | ? ((v) & ~0x3) == 0 \ | |
3487 | ? ((v) & ~0x1) == 0 \ | |
3488 | ? !(v) \ | |
3489 | ? 32 \ | |
3490 | : 31 \ | |
3491 | : 30 \ | |
3492 | : ((v) & ~0x7) == 0 \ | |
3493 | ? 29 \ | |
3494 | : 28 \ | |
3495 | : ((v) & ~0x3f) == 0 \ | |
3496 | ? ((v) & ~0x1f) == 0 \ | |
3497 | ? 27 \ | |
3498 | : 26 \ | |
3499 | : ((v) & ~0x7f) == 0 \ | |
3500 | ? 25 \ | |
3501 | : 24 \ | |
3502 | : ((v) & ~0xfff) == 0 \ | |
3503 | ? ((v) & ~0x3ff) == 0 \ | |
3504 | ? ((v) & ~0x1ff) == 0 \ | |
3505 | ? 23 \ | |
3506 | : 22 \ | |
3507 | : ((v) & ~0x7ff) == 0 \ | |
3508 | ? 21 \ | |
3509 | : 20 \ | |
3510 | : ((v) & ~0x3fff) == 0 \ | |
3511 | ? ((v) & ~0x1fff) == 0 \ | |
3512 | ? 19 \ | |
3513 | : 18 \ | |
3514 | : ((v) & ~0x7fff) == 0 \ | |
3515 | ? 17 \ | |
3516 | : 16 \ | |
3517 | : ((v) & ~0xffffff) == 0 \ | |
3518 | ? ((v) & ~0xfffff) == 0 \ | |
3519 | ? ((v) & ~0x3ffff) == 0 \ | |
3520 | ? ((v) & ~0x1ffff) == 0 \ | |
3521 | ? 15 \ | |
3522 | : 14 \ | |
3523 | : ((v) & ~0x7ffff) == 0 \ | |
3524 | ? 13 \ | |
3525 | : 12 \ | |
3526 | : ((v) & ~0x3fffff) == 0 \ | |
3527 | ? ((v) & ~0x1fffff) == 0 \ | |
3528 | ? 11 \ | |
3529 | : 10 \ | |
3530 | : ((v) & ~0x7fffff) == 0 \ | |
3531 | ? 9 \ | |
3532 | : 8 \ | |
3533 | : ((v) & ~0xfffffff) == 0 \ | |
3534 | ? ((v) & ~0x3ffffff) == 0 \ | |
3535 | ? ((v) & ~0x1ffffff) == 0 \ | |
3536 | ? 7 \ | |
3537 | : 6 \ | |
3538 | : ((v) & ~0x7ffffff) == 0 \ | |
3539 | ? 5 \ | |
3540 | : 4 \ | |
3541 | : ((v) & ~0x3fffffff) == 0 \ | |
3542 | ? ((v) & ~0x1fffffff) == 0 \ | |
3543 | ? 3 \ | |
3544 | : 2 \ | |
3545 | : ((v) & ~0x7fffffff) == 0 \ | |
3546 | ? 1 \ | |
3547 | : 0) | |
3548 | ||
3549 | /* load_register() | |
67c1ffbe | 3550 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
3551 | * an absolute expression value into a register. |
3552 | */ | |
3553 | static void | |
67c0d1eb | 3554 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
3555 | { |
3556 | int freg; | |
3557 | expressionS hi32, lo32; | |
3558 | ||
3559 | if (ep->X_op != O_big) | |
3560 | { | |
3561 | assert (ep->X_op == O_constant); | |
256ab948 TS |
3562 | |
3563 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
d17e7bce TS |
3564 | if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff)) |
3565 | == ~((bfd_vma) 0x7fffffff))) | |
ae826530 | 3566 | { |
d17e7bce | 3567 | if (ep->X_add_number & ~((bfd_vma) 0xffffffff)) |
1b8e29e5 | 3568 | as_bad (_("constant too large")); |
ae826530 | 3569 | |
1b8e29e5 TS |
3570 | ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000) |
3571 | - 0x80000000); | |
ae826530 | 3572 | } |
256ab948 TS |
3573 | |
3574 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
3575 | { |
3576 | /* We can handle 16 bit signed values with an addiu to | |
3577 | $zero. No need to ever use daddiu here, since $zero and | |
3578 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 3579 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3580 | return; |
3581 | } | |
3582 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
3583 | { | |
3584 | /* We can handle 16 bit unsigned values with an ori to | |
3585 | $zero. */ | |
67c0d1eb | 3586 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3587 | return; |
3588 | } | |
256ab948 | 3589 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
3590 | { |
3591 | /* 32 bit values require an lui. */ | |
67c0d1eb | 3592 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 3593 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 3594 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
3595 | return; |
3596 | } | |
3597 | } | |
3598 | ||
3599 | /* The value is larger than 32 bits. */ | |
3600 | ||
ca4e0257 | 3601 | if (HAVE_32BIT_GPRS) |
252b5132 | 3602 | { |
956cd1d6 TS |
3603 | as_bad (_("Number (0x%lx) larger than 32 bits"), |
3604 | (unsigned long) ep->X_add_number); | |
67c0d1eb | 3605 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3606 | return; |
3607 | } | |
3608 | ||
3609 | if (ep->X_op != O_big) | |
3610 | { | |
3611 | hi32 = *ep; | |
3612 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3613 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3614 | hi32.X_add_number &= 0xffffffff; | |
3615 | lo32 = *ep; | |
3616 | lo32.X_add_number &= 0xffffffff; | |
3617 | } | |
3618 | else | |
3619 | { | |
3620 | assert (ep->X_add_number > 2); | |
3621 | if (ep->X_add_number == 3) | |
3622 | generic_bignum[3] = 0; | |
3623 | else if (ep->X_add_number > 4) | |
3624 | as_bad (_("Number larger than 64 bits")); | |
3625 | lo32.X_op = O_constant; | |
3626 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
3627 | hi32.X_op = O_constant; | |
3628 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
3629 | } | |
3630 | ||
3631 | if (hi32.X_add_number == 0) | |
3632 | freg = 0; | |
3633 | else | |
3634 | { | |
3635 | int shift, bit; | |
3636 | unsigned long hi, lo; | |
3637 | ||
956cd1d6 | 3638 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
3639 | { |
3640 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
3641 | { | |
67c0d1eb | 3642 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
3643 | return; |
3644 | } | |
3645 | if (lo32.X_add_number & 0x80000000) | |
3646 | { | |
67c0d1eb | 3647 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 3648 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 3649 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
3650 | return; |
3651 | } | |
3652 | } | |
252b5132 RH |
3653 | |
3654 | /* Check for 16bit shifted constant. We know that hi32 is | |
3655 | non-zero, so start the mask on the first bit of the hi32 | |
3656 | value. */ | |
3657 | shift = 17; | |
3658 | do | |
beae10d5 KH |
3659 | { |
3660 | unsigned long himask, lomask; | |
3661 | ||
3662 | if (shift < 32) | |
3663 | { | |
3664 | himask = 0xffff >> (32 - shift); | |
3665 | lomask = (0xffff << shift) & 0xffffffff; | |
3666 | } | |
3667 | else | |
3668 | { | |
3669 | himask = 0xffff << (shift - 32); | |
3670 | lomask = 0; | |
3671 | } | |
3672 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
3673 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
3674 | { | |
3675 | expressionS tmp; | |
3676 | ||
3677 | tmp.X_op = O_constant; | |
3678 | if (shift < 32) | |
3679 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
3680 | | (lo32.X_add_number >> shift)); | |
3681 | else | |
3682 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb RS |
3683 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
3684 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<", | |
3685 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
3686 | return; |
3687 | } | |
f9419b05 | 3688 | ++shift; |
beae10d5 KH |
3689 | } |
3690 | while (shift <= (64 - 16)); | |
252b5132 RH |
3691 | |
3692 | /* Find the bit number of the lowest one bit, and store the | |
3693 | shifted value in hi/lo. */ | |
3694 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
3695 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
3696 | if (lo != 0) | |
3697 | { | |
3698 | bit = 0; | |
3699 | while ((lo & 1) == 0) | |
3700 | { | |
3701 | lo >>= 1; | |
3702 | ++bit; | |
3703 | } | |
3704 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
3705 | hi >>= bit; | |
3706 | } | |
3707 | else | |
3708 | { | |
3709 | bit = 32; | |
3710 | while ((hi & 1) == 0) | |
3711 | { | |
3712 | hi >>= 1; | |
3713 | ++bit; | |
3714 | } | |
3715 | lo = hi; | |
3716 | hi = 0; | |
3717 | } | |
3718 | ||
3719 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
3720 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
3721 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
3722 | { |
3723 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 3724 | if (shift != 0) |
beae10d5 | 3725 | { |
252b5132 RH |
3726 | expressionS tmp; |
3727 | ||
3728 | /* This instruction will set the register to be all | |
3729 | ones. */ | |
beae10d5 KH |
3730 | tmp.X_op = O_constant; |
3731 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 3732 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
3733 | if (bit != 0) |
3734 | { | |
3735 | bit += shift; | |
67c0d1eb RS |
3736 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<", |
3737 | reg, reg, (bit >= 32) ? bit - 32 : bit); | |
beae10d5 | 3738 | } |
67c0d1eb RS |
3739 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<", |
3740 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
3741 | return; |
3742 | } | |
3743 | } | |
252b5132 RH |
3744 | |
3745 | /* Sign extend hi32 before calling load_register, because we can | |
3746 | generally get better code when we load a sign extended value. */ | |
3747 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 3748 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 3749 | load_register (reg, &hi32, 0); |
252b5132 RH |
3750 | freg = reg; |
3751 | } | |
3752 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
3753 | { | |
3754 | if (freg != 0) | |
3755 | { | |
67c0d1eb | 3756 | macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0); |
252b5132 RH |
3757 | freg = reg; |
3758 | } | |
3759 | } | |
3760 | else | |
3761 | { | |
3762 | expressionS mid16; | |
3763 | ||
956cd1d6 | 3764 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 3765 | { |
67c0d1eb RS |
3766 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
3767 | macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0); | |
beae10d5 KH |
3768 | return; |
3769 | } | |
252b5132 RH |
3770 | |
3771 | if (freg != 0) | |
3772 | { | |
67c0d1eb | 3773 | macro_build (NULL, "dsll", "d,w,<", reg, freg, 16); |
252b5132 RH |
3774 | freg = reg; |
3775 | } | |
3776 | mid16 = lo32; | |
3777 | mid16.X_add_number >>= 16; | |
67c0d1eb RS |
3778 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
3779 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
252b5132 RH |
3780 | freg = reg; |
3781 | } | |
3782 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 3783 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
3784 | } |
3785 | ||
269137b2 TS |
3786 | static inline void |
3787 | load_delay_nop (void) | |
3788 | { | |
3789 | if (!gpr_interlocks) | |
3790 | macro_build (NULL, "nop", ""); | |
3791 | } | |
3792 | ||
252b5132 RH |
3793 | /* Load an address into a register. */ |
3794 | ||
3795 | static void | |
67c0d1eb | 3796 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 3797 | { |
252b5132 RH |
3798 | if (ep->X_op != O_constant |
3799 | && ep->X_op != O_symbol) | |
3800 | { | |
3801 | as_bad (_("expression too complex")); | |
3802 | ep->X_op = O_constant; | |
3803 | } | |
3804 | ||
3805 | if (ep->X_op == O_constant) | |
3806 | { | |
67c0d1eb | 3807 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
3808 | return; |
3809 | } | |
3810 | ||
3811 | if (mips_pic == NO_PIC) | |
3812 | { | |
3813 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 3814 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
3815 | Otherwise we want |
3816 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
3817 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 3818 | If we have an addend, we always use the latter form. |
76b3015f | 3819 | |
d6bc6245 TS |
3820 | With 64bit address space and a usable $at we want |
3821 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3822 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
3823 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3824 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
3825 | dsll32 $reg,0 | |
3a482fd5 | 3826 | daddu $reg,$reg,$at |
76b3015f | 3827 | |
c03099e6 | 3828 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
3829 | on superscalar processors. |
3830 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3831 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3832 | dsll $reg,16 | |
3833 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
3834 | dsll $reg,16 | |
3835 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
3836 | */ | |
c9914766 | 3837 | if (HAVE_64BIT_ADDRESSES) |
d6bc6245 | 3838 | { |
e864ceca RS |
3839 | /* ??? We don't provide a GP-relative alternative for these macros. |
3840 | It used not to be possible with the original relaxation code, | |
3841 | but it could be done now. */ | |
d6bc6245 | 3842 | |
460597ba | 3843 | if (*used_at == 0 && ! mips_opts.noat) |
d6bc6245 | 3844 | { |
67c0d1eb RS |
3845 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
3846 | macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S); | |
3847 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
3848 | BFD_RELOC_MIPS_HIGHER); | |
3849 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
3850 | macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0); | |
3851 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); | |
d6bc6245 TS |
3852 | *used_at = 1; |
3853 | } | |
3854 | else | |
3855 | { | |
67c0d1eb RS |
3856 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
3857 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
3858 | BFD_RELOC_MIPS_HIGHER); | |
3859 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
3860 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); | |
3861 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
3862 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); | |
d6bc6245 TS |
3863 | } |
3864 | } | |
252b5132 RH |
3865 | else |
3866 | { | |
d6bc6245 TS |
3867 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
3868 | && ! nopic_need_relax (ep->X_add_symbol, 1)) | |
3869 | { | |
4d7206a2 | 3870 | relax_start (ep->X_add_symbol); |
67c0d1eb | 3871 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 3872 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 3873 | relax_switch (); |
d6bc6245 | 3874 | } |
67c0d1eb RS |
3875 | macro_build_lui (ep, reg); |
3876 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
3877 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
3878 | if (mips_relax.sequence) |
3879 | relax_end (); | |
d6bc6245 | 3880 | } |
252b5132 RH |
3881 | } |
3882 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
3883 | { | |
3884 | expressionS ex; | |
3885 | ||
3886 | /* If this is a reference to an external symbol, we want | |
3887 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3888 | Otherwise we want | |
3889 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3890 | nop | |
3891 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
3892 | If there is a constant, it must be added in after. |
3893 | ||
ed6fb7bd | 3894 | If we have NewABI, we want |
f5040a92 AO |
3895 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
3896 | unless we're referencing a global symbol with a non-zero | |
3897 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
3898 | if (HAVE_NEWABI) |
3899 | { | |
f5040a92 AO |
3900 | if (ep->X_add_number) |
3901 | { | |
4d7206a2 | 3902 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 3903 | ep->X_add_number = 0; |
4d7206a2 | 3904 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
3905 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
3906 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
3907 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
3908 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3909 | ex.X_op = O_constant; | |
67c0d1eb | 3910 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 3911 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 3912 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 3913 | relax_switch (); |
f5040a92 | 3914 | } |
67c0d1eb | 3915 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 3916 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
3917 | if (mips_relax.sequence) |
3918 | relax_end (); | |
ed6fb7bd SC |
3919 | } |
3920 | else | |
3921 | { | |
f5040a92 AO |
3922 | ex.X_add_number = ep->X_add_number; |
3923 | ep->X_add_number = 0; | |
67c0d1eb RS |
3924 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
3925 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 3926 | load_delay_nop (); |
4d7206a2 RS |
3927 | relax_start (ep->X_add_symbol); |
3928 | relax_switch (); | |
67c0d1eb | 3929 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 3930 | BFD_RELOC_LO16); |
4d7206a2 | 3931 | relax_end (); |
ed6fb7bd | 3932 | |
f5040a92 AO |
3933 | if (ex.X_add_number != 0) |
3934 | { | |
3935 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3936 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3937 | ex.X_op = O_constant; | |
67c0d1eb | 3938 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 3939 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 3940 | } |
252b5132 RH |
3941 | } |
3942 | } | |
3943 | else if (mips_pic == SVR4_PIC) | |
3944 | { | |
3945 | expressionS ex; | |
252b5132 RH |
3946 | |
3947 | /* This is the large GOT case. If this is a reference to an | |
3948 | external symbol, we want | |
3949 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3950 | addu $reg,$reg,$gp | |
3951 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
3952 | |
3953 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
3954 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
3955 | nop | |
3956 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 3957 | If there is a constant, it must be added in after. |
f5040a92 AO |
3958 | |
3959 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
3960 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
3961 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 3962 | */ |
438c16b8 TS |
3963 | if (HAVE_NEWABI) |
3964 | { | |
4d7206a2 | 3965 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 3966 | ep->X_add_number = 0; |
4d7206a2 | 3967 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
3968 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
3969 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
3970 | reg, reg, mips_gp_register); | |
3971 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
3972 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
3973 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
3974 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3975 | else if (ex.X_add_number) | |
3976 | { | |
3977 | ex.X_op = O_constant; | |
67c0d1eb RS |
3978 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
3979 | BFD_RELOC_LO16); | |
f5040a92 AO |
3980 | } |
3981 | ||
3982 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 3983 | relax_switch (); |
67c0d1eb | 3984 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 3985 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
3986 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
3987 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 3988 | relax_end (); |
438c16b8 | 3989 | } |
252b5132 | 3990 | else |
438c16b8 | 3991 | { |
f5040a92 AO |
3992 | ex.X_add_number = ep->X_add_number; |
3993 | ep->X_add_number = 0; | |
4d7206a2 | 3994 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
3995 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
3996 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
3997 | reg, reg, mips_gp_register); | |
3998 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
3999 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
4000 | relax_switch (); |
4001 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
4002 | { |
4003 | /* We need a nop before loading from $gp. This special | |
4004 | check is required because the lui which starts the main | |
4005 | instruction stream does not refer to $gp, and so will not | |
4006 | insert the nop which may be required. */ | |
67c0d1eb | 4007 | macro_build (NULL, "nop", ""); |
438c16b8 | 4008 | } |
67c0d1eb | 4009 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4010 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 4011 | load_delay_nop (); |
67c0d1eb | 4012 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 4013 | BFD_RELOC_LO16); |
4d7206a2 | 4014 | relax_end (); |
438c16b8 | 4015 | |
f5040a92 AO |
4016 | if (ex.X_add_number != 0) |
4017 | { | |
4018 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
4019 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4020 | ex.X_op = O_constant; | |
67c0d1eb RS |
4021 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4022 | BFD_RELOC_LO16); | |
f5040a92 | 4023 | } |
252b5132 RH |
4024 | } |
4025 | } | |
4026 | else if (mips_pic == EMBEDDED_PIC) | |
4027 | { | |
4028 | /* We always do | |
cdf6fd85 | 4029 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
c9914766 | 4030 | */ |
67c0d1eb RS |
4031 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", |
4032 | reg, mips_gp_register, BFD_RELOC_GPREL16); | |
252b5132 RH |
4033 | } |
4034 | else | |
4035 | abort (); | |
4036 | } | |
4037 | ||
ea1fb5dc RS |
4038 | /* Move the contents of register SOURCE into register DEST. */ |
4039 | ||
4040 | static void | |
67c0d1eb | 4041 | move_register (int dest, int source) |
ea1fb5dc | 4042 | { |
67c0d1eb RS |
4043 | macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", |
4044 | dest, source, 0); | |
ea1fb5dc RS |
4045 | } |
4046 | ||
4d7206a2 | 4047 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
4048 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
4049 | The two alternatives are: | |
4d7206a2 RS |
4050 | |
4051 | Global symbol Local sybmol | |
4052 | ------------- ------------ | |
4053 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
4054 | ... ... | |
4055 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
4056 | ||
4057 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
4058 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
4059 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
4060 | |
4061 | static void | |
67c0d1eb | 4062 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4063 | { |
4064 | expressionS global; | |
4065 | ||
4066 | global = *local; | |
4067 | global.X_add_number = 0; | |
4068 | ||
4069 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
4070 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4071 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 4072 | relax_switch (); |
67c0d1eb RS |
4073 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4074 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
4075 | relax_end (); |
4076 | } | |
4077 | ||
4078 | static void | |
67c0d1eb | 4079 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4080 | { |
4081 | expressionS global; | |
4082 | ||
4083 | global.X_op = O_constant; | |
4084 | global.X_op_symbol = NULL; | |
4085 | global.X_add_symbol = NULL; | |
4086 | global.X_add_number = local->X_add_number; | |
4087 | ||
4088 | relax_start (local->X_add_symbol); | |
67c0d1eb | 4089 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
4090 | dest, dest, BFD_RELOC_LO16); |
4091 | relax_switch (); | |
67c0d1eb | 4092 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
4093 | relax_end (); |
4094 | } | |
4095 | ||
f6a22291 MR |
4096 | static void |
4097 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
4098 | { | |
4099 | expressionS global; | |
4100 | int hold_mips_optimize; | |
4101 | ||
4102 | global.X_op = O_constant; | |
4103 | global.X_op_symbol = NULL; | |
4104 | global.X_add_symbol = NULL; | |
4105 | global.X_add_number = local->X_add_number; | |
4106 | ||
4107 | relax_start (local->X_add_symbol); | |
4108 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
4109 | relax_switch (); | |
4110 | /* Set mips_optimize around the lui instruction to avoid | |
4111 | inserting an unnecessary nop after the lw. */ | |
4112 | hold_mips_optimize = mips_optimize; | |
4113 | mips_optimize = 2; | |
4114 | macro_build_lui (&global, tmp); | |
4115 | mips_optimize = hold_mips_optimize; | |
4116 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
4117 | relax_end (); | |
4118 | ||
4119 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
4120 | } | |
4121 | ||
252b5132 RH |
4122 | /* |
4123 | * Build macros | |
4124 | * This routine implements the seemingly endless macro or synthesized | |
4125 | * instructions and addressing modes in the mips assembly language. Many | |
4126 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 4127 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
4128 | * this verbose method. Others are not simple macros but are more like |
4129 | * optimizing code generation. | |
4130 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 4131 | * consecutively that would load AT with the upper half of the same address. |
252b5132 RH |
4132 | * The ensuing load upper instructions are ommited. This implies some kind |
4133 | * of global optimization. We currently only optimize within a single macro. | |
4134 | * For many of the load and store macros if the address is specified as a | |
4135 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
4136 | * first load register 'at' with zero and use it as the base register. The | |
4137 | * mips assembler simply uses register $zero. Just one tiny optimization | |
4138 | * we're missing. | |
4139 | */ | |
4140 | static void | |
17a2f251 | 4141 | macro (struct mips_cl_insn *ip) |
252b5132 RH |
4142 | { |
4143 | register int treg, sreg, dreg, breg; | |
4144 | int tempreg; | |
4145 | int mask; | |
43841e91 | 4146 | int used_at = 0; |
252b5132 RH |
4147 | expressionS expr1; |
4148 | const char *s; | |
4149 | const char *s2; | |
4150 | const char *fmt; | |
4151 | int likely = 0; | |
4152 | int dbl = 0; | |
4153 | int coproc = 0; | |
4154 | int lr = 0; | |
4155 | int imm = 0; | |
1abe91b1 | 4156 | int call = 0; |
252b5132 | 4157 | int off; |
67c0d1eb | 4158 | offsetT maxnum; |
252b5132 | 4159 | bfd_reloc_code_real_type r; |
252b5132 RH |
4160 | int hold_mips_optimize; |
4161 | ||
4162 | assert (! mips_opts.mips16); | |
4163 | ||
4164 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
4165 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
4166 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
4167 | mask = ip->insn_mo->mask; | |
4168 | ||
4169 | expr1.X_op = O_constant; | |
4170 | expr1.X_op_symbol = NULL; | |
4171 | expr1.X_add_symbol = NULL; | |
4172 | expr1.X_add_number = 1; | |
4173 | ||
4174 | switch (mask) | |
4175 | { | |
4176 | case M_DABS: | |
4177 | dbl = 1; | |
4178 | case M_ABS: | |
4179 | /* bgez $a0,.+12 | |
4180 | move v0,$a0 | |
4181 | sub v0,$zero,$a0 | |
4182 | */ | |
4183 | ||
b34976b6 | 4184 | mips_emit_delays (TRUE); |
252b5132 RH |
4185 | ++mips_opts.noreorder; |
4186 | mips_any_noreorder = 1; | |
4187 | ||
4188 | expr1.X_add_number = 8; | |
67c0d1eb | 4189 | macro_build (&expr1, "bgez", "s,p", sreg); |
252b5132 | 4190 | if (dreg == sreg) |
67c0d1eb | 4191 | macro_build (NULL, "nop", "", 0); |
252b5132 | 4192 | else |
67c0d1eb RS |
4193 | move_register (dreg, sreg); |
4194 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); | |
252b5132 RH |
4195 | |
4196 | --mips_opts.noreorder; | |
4197 | return; | |
4198 | ||
4199 | case M_ADD_I: | |
4200 | s = "addi"; | |
4201 | s2 = "add"; | |
4202 | goto do_addi; | |
4203 | case M_ADDU_I: | |
4204 | s = "addiu"; | |
4205 | s2 = "addu"; | |
4206 | goto do_addi; | |
4207 | case M_DADD_I: | |
4208 | dbl = 1; | |
4209 | s = "daddi"; | |
4210 | s2 = "dadd"; | |
4211 | goto do_addi; | |
4212 | case M_DADDU_I: | |
4213 | dbl = 1; | |
4214 | s = "daddiu"; | |
4215 | s2 = "daddu"; | |
4216 | do_addi: | |
4217 | if (imm_expr.X_op == O_constant | |
4218 | && imm_expr.X_add_number >= -0x8000 | |
4219 | && imm_expr.X_add_number < 0x8000) | |
4220 | { | |
67c0d1eb | 4221 | macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
4222 | return; |
4223 | } | |
67c0d1eb RS |
4224 | load_register (AT, &imm_expr, dbl); |
4225 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4226 | break; |
4227 | ||
4228 | case M_AND_I: | |
4229 | s = "andi"; | |
4230 | s2 = "and"; | |
4231 | goto do_bit; | |
4232 | case M_OR_I: | |
4233 | s = "ori"; | |
4234 | s2 = "or"; | |
4235 | goto do_bit; | |
4236 | case M_NOR_I: | |
4237 | s = ""; | |
4238 | s2 = "nor"; | |
4239 | goto do_bit; | |
4240 | case M_XOR_I: | |
4241 | s = "xori"; | |
4242 | s2 = "xor"; | |
4243 | do_bit: | |
4244 | if (imm_expr.X_op == O_constant | |
4245 | && imm_expr.X_add_number >= 0 | |
4246 | && imm_expr.X_add_number < 0x10000) | |
4247 | { | |
4248 | if (mask != M_NOR_I) | |
67c0d1eb | 4249 | macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
4250 | else |
4251 | { | |
67c0d1eb RS |
4252 | macro_build (&imm_expr, "ori", "t,r,i", |
4253 | treg, sreg, BFD_RELOC_LO16); | |
4254 | macro_build (NULL, "nor", "d,v,t", treg, treg, 0); | |
252b5132 RH |
4255 | } |
4256 | return; | |
4257 | } | |
4258 | ||
67c0d1eb RS |
4259 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4260 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4261 | break; |
4262 | ||
4263 | case M_BEQ_I: | |
4264 | s = "beq"; | |
4265 | goto beq_i; | |
4266 | case M_BEQL_I: | |
4267 | s = "beql"; | |
4268 | likely = 1; | |
4269 | goto beq_i; | |
4270 | case M_BNE_I: | |
4271 | s = "bne"; | |
4272 | goto beq_i; | |
4273 | case M_BNEL_I: | |
4274 | s = "bnel"; | |
4275 | likely = 1; | |
4276 | beq_i: | |
4277 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4278 | { | |
67c0d1eb | 4279 | macro_build (&offset_expr, s, "s,t,p", sreg, 0); |
252b5132 RH |
4280 | return; |
4281 | } | |
67c0d1eb RS |
4282 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4283 | macro_build (&offset_expr, s, "s,t,p", sreg, AT); | |
252b5132 RH |
4284 | break; |
4285 | ||
4286 | case M_BGEL: | |
4287 | likely = 1; | |
4288 | case M_BGE: | |
4289 | if (treg == 0) | |
4290 | { | |
67c0d1eb | 4291 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
252b5132 RH |
4292 | return; |
4293 | } | |
4294 | if (sreg == 0) | |
4295 | { | |
67c0d1eb | 4296 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg); |
252b5132 RH |
4297 | return; |
4298 | } | |
67c0d1eb RS |
4299 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
4300 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4301 | break; |
4302 | ||
4303 | case M_BGTL_I: | |
4304 | likely = 1; | |
4305 | case M_BGT_I: | |
4306 | /* check for > max integer */ | |
4307 | maxnum = 0x7fffffff; | |
ca4e0257 | 4308 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4309 | { |
4310 | maxnum <<= 16; | |
4311 | maxnum |= 0xffff; | |
4312 | maxnum <<= 16; | |
4313 | maxnum |= 0xffff; | |
4314 | } | |
4315 | if (imm_expr.X_op == O_constant | |
4316 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4317 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4318 | { |
4319 | do_false: | |
4320 | /* result is always false */ | |
4321 | if (! likely) | |
67c0d1eb | 4322 | macro_build (NULL, "nop", "", 0); |
252b5132 | 4323 | else |
67c0d1eb | 4324 | macro_build (&offset_expr, "bnel", "s,t,p", 0, 0); |
252b5132 RH |
4325 | return; |
4326 | } | |
4327 | if (imm_expr.X_op != O_constant) | |
4328 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4329 | ++imm_expr.X_add_number; |
252b5132 RH |
4330 | /* FALLTHROUGH */ |
4331 | case M_BGE_I: | |
4332 | case M_BGEL_I: | |
4333 | if (mask == M_BGEL_I) | |
4334 | likely = 1; | |
4335 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4336 | { | |
67c0d1eb | 4337 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
252b5132 RH |
4338 | return; |
4339 | } | |
4340 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4341 | { | |
67c0d1eb | 4342 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
252b5132 RH |
4343 | return; |
4344 | } | |
4345 | maxnum = 0x7fffffff; | |
ca4e0257 | 4346 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4347 | { |
4348 | maxnum <<= 16; | |
4349 | maxnum |= 0xffff; | |
4350 | maxnum <<= 16; | |
4351 | maxnum |= 0xffff; | |
4352 | } | |
4353 | maxnum = - maxnum - 1; | |
4354 | if (imm_expr.X_op == O_constant | |
4355 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 4356 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4357 | { |
4358 | do_true: | |
4359 | /* result is always true */ | |
4360 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
67c0d1eb | 4361 | macro_build (&offset_expr, "b", "p"); |
252b5132 RH |
4362 | return; |
4363 | } | |
67c0d1eb RS |
4364 | set_at (sreg, 0); |
4365 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4366 | break; |
4367 | ||
4368 | case M_BGEUL: | |
4369 | likely = 1; | |
4370 | case M_BGEU: | |
4371 | if (treg == 0) | |
4372 | goto do_true; | |
4373 | if (sreg == 0) | |
4374 | { | |
67c0d1eb | 4375 | macro_build (&offset_expr, likely ? "beql" : "beq", |
17a2f251 | 4376 | "s,t,p", 0, treg); |
252b5132 RH |
4377 | return; |
4378 | } | |
67c0d1eb RS |
4379 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
4380 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4381 | break; |
4382 | ||
4383 | case M_BGTUL_I: | |
4384 | likely = 1; | |
4385 | case M_BGTU_I: | |
4386 | if (sreg == 0 | |
ca4e0257 | 4387 | || (HAVE_32BIT_GPRS |
252b5132 | 4388 | && imm_expr.X_op == O_constant |
956cd1d6 | 4389 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4390 | goto do_false; |
4391 | if (imm_expr.X_op != O_constant) | |
4392 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4393 | ++imm_expr.X_add_number; |
252b5132 RH |
4394 | /* FALLTHROUGH */ |
4395 | case M_BGEU_I: | |
4396 | case M_BGEUL_I: | |
4397 | if (mask == M_BGEUL_I) | |
4398 | likely = 1; | |
4399 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4400 | goto do_true; | |
4401 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4402 | { | |
67c0d1eb | 4403 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4404 | "s,t,p", sreg, 0); |
252b5132 RH |
4405 | return; |
4406 | } | |
67c0d1eb RS |
4407 | set_at (sreg, 1); |
4408 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4409 | break; |
4410 | ||
4411 | case M_BGTL: | |
4412 | likely = 1; | |
4413 | case M_BGT: | |
4414 | if (treg == 0) | |
4415 | { | |
67c0d1eb | 4416 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
252b5132 RH |
4417 | return; |
4418 | } | |
4419 | if (sreg == 0) | |
4420 | { | |
67c0d1eb | 4421 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg); |
252b5132 RH |
4422 | return; |
4423 | } | |
67c0d1eb RS |
4424 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
4425 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4426 | break; |
4427 | ||
4428 | case M_BGTUL: | |
4429 | likely = 1; | |
4430 | case M_BGTU: | |
4431 | if (treg == 0) | |
4432 | { | |
67c0d1eb | 4433 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4434 | "s,t,p", sreg, 0); |
252b5132 RH |
4435 | return; |
4436 | } | |
4437 | if (sreg == 0) | |
4438 | goto do_false; | |
67c0d1eb RS |
4439 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
4440 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4441 | break; |
4442 | ||
4443 | case M_BLEL: | |
4444 | likely = 1; | |
4445 | case M_BLE: | |
4446 | if (treg == 0) | |
4447 | { | |
67c0d1eb | 4448 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
252b5132 RH |
4449 | return; |
4450 | } | |
4451 | if (sreg == 0) | |
4452 | { | |
67c0d1eb | 4453 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg); |
252b5132 RH |
4454 | return; |
4455 | } | |
67c0d1eb RS |
4456 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
4457 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4458 | break; |
4459 | ||
4460 | case M_BLEL_I: | |
4461 | likely = 1; | |
4462 | case M_BLE_I: | |
4463 | maxnum = 0x7fffffff; | |
ca4e0257 | 4464 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4465 | { |
4466 | maxnum <<= 16; | |
4467 | maxnum |= 0xffff; | |
4468 | maxnum <<= 16; | |
4469 | maxnum |= 0xffff; | |
4470 | } | |
4471 | if (imm_expr.X_op == O_constant | |
4472 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4473 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4474 | goto do_true; |
4475 | if (imm_expr.X_op != O_constant) | |
4476 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4477 | ++imm_expr.X_add_number; |
252b5132 RH |
4478 | /* FALLTHROUGH */ |
4479 | case M_BLT_I: | |
4480 | case M_BLTL_I: | |
4481 | if (mask == M_BLTL_I) | |
4482 | likely = 1; | |
4483 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4484 | { | |
67c0d1eb | 4485 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
252b5132 RH |
4486 | return; |
4487 | } | |
4488 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4489 | { | |
67c0d1eb | 4490 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
252b5132 RH |
4491 | return; |
4492 | } | |
67c0d1eb RS |
4493 | set_at (sreg, 0); |
4494 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4495 | break; |
4496 | ||
4497 | case M_BLEUL: | |
4498 | likely = 1; | |
4499 | case M_BLEU: | |
4500 | if (treg == 0) | |
4501 | { | |
67c0d1eb | 4502 | macro_build (&offset_expr, likely ? "beql" : "beq", |
17a2f251 | 4503 | "s,t,p", sreg, 0); |
252b5132 RH |
4504 | return; |
4505 | } | |
4506 | if (sreg == 0) | |
4507 | goto do_true; | |
67c0d1eb RS |
4508 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
4509 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4510 | break; |
4511 | ||
4512 | case M_BLEUL_I: | |
4513 | likely = 1; | |
4514 | case M_BLEU_I: | |
4515 | if (sreg == 0 | |
ca4e0257 | 4516 | || (HAVE_32BIT_GPRS |
252b5132 | 4517 | && imm_expr.X_op == O_constant |
956cd1d6 | 4518 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4519 | goto do_true; |
4520 | if (imm_expr.X_op != O_constant) | |
4521 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4522 | ++imm_expr.X_add_number; |
252b5132 RH |
4523 | /* FALLTHROUGH */ |
4524 | case M_BLTU_I: | |
4525 | case M_BLTUL_I: | |
4526 | if (mask == M_BLTUL_I) | |
4527 | likely = 1; | |
4528 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4529 | goto do_false; | |
4530 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4531 | { | |
67c0d1eb | 4532 | macro_build (&offset_expr, likely ? "beql" : "beq", |
252b5132 RH |
4533 | "s,t,p", sreg, 0); |
4534 | return; | |
4535 | } | |
67c0d1eb RS |
4536 | set_at (sreg, 1); |
4537 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4538 | break; |
4539 | ||
4540 | case M_BLTL: | |
4541 | likely = 1; | |
4542 | case M_BLT: | |
4543 | if (treg == 0) | |
4544 | { | |
67c0d1eb | 4545 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
252b5132 RH |
4546 | return; |
4547 | } | |
4548 | if (sreg == 0) | |
4549 | { | |
67c0d1eb | 4550 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg); |
252b5132 RH |
4551 | return; |
4552 | } | |
67c0d1eb RS |
4553 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
4554 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4555 | break; |
4556 | ||
4557 | case M_BLTUL: | |
4558 | likely = 1; | |
4559 | case M_BLTU: | |
4560 | if (treg == 0) | |
4561 | goto do_false; | |
4562 | if (sreg == 0) | |
4563 | { | |
67c0d1eb | 4564 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4565 | "s,t,p", 0, treg); |
252b5132 RH |
4566 | return; |
4567 | } | |
67c0d1eb RS |
4568 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
4569 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4570 | break; |
4571 | ||
5f74bc13 CD |
4572 | case M_DEXT: |
4573 | { | |
4574 | unsigned long pos; | |
4575 | unsigned long size; | |
4576 | ||
4577 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
4578 | { | |
4579 | as_bad (_("Unsupported large constant")); | |
4580 | pos = size = 1; | |
4581 | } | |
4582 | else | |
4583 | { | |
4584 | pos = (unsigned long) imm_expr.X_add_number; | |
4585 | size = (unsigned long) imm2_expr.X_add_number; | |
4586 | } | |
4587 | ||
4588 | if (pos > 63) | |
4589 | { | |
4590 | as_bad (_("Improper position (%lu)"), pos); | |
4591 | pos = 1; | |
4592 | } | |
4593 | if (size == 0 || size > 64 | |
4594 | || (pos + size - 1) > 63) | |
4595 | { | |
4596 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
4597 | size, pos); | |
4598 | size = 1; | |
4599 | } | |
4600 | ||
4601 | if (size <= 32 && pos < 32) | |
4602 | { | |
4603 | s = "dext"; | |
4604 | fmt = "t,r,+A,+C"; | |
4605 | } | |
4606 | else if (size <= 32) | |
4607 | { | |
4608 | s = "dextu"; | |
4609 | fmt = "t,r,+E,+H"; | |
4610 | } | |
4611 | else | |
4612 | { | |
4613 | s = "dextm"; | |
4614 | fmt = "t,r,+A,+G"; | |
4615 | } | |
67c0d1eb | 4616 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, size - 1); |
5f74bc13 CD |
4617 | } |
4618 | return; | |
4619 | ||
4620 | case M_DINS: | |
4621 | { | |
4622 | unsigned long pos; | |
4623 | unsigned long size; | |
4624 | ||
4625 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
4626 | { | |
4627 | as_bad (_("Unsupported large constant")); | |
4628 | pos = size = 1; | |
4629 | } | |
4630 | else | |
4631 | { | |
4632 | pos = (unsigned long) imm_expr.X_add_number; | |
4633 | size = (unsigned long) imm2_expr.X_add_number; | |
4634 | } | |
4635 | ||
4636 | if (pos > 63) | |
4637 | { | |
4638 | as_bad (_("Improper position (%lu)"), pos); | |
4639 | pos = 1; | |
4640 | } | |
4641 | if (size == 0 || size > 64 | |
4642 | || (pos + size - 1) > 63) | |
4643 | { | |
4644 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
4645 | size, pos); | |
4646 | size = 1; | |
4647 | } | |
4648 | ||
4649 | if (pos < 32 && (pos + size - 1) < 32) | |
4650 | { | |
4651 | s = "dins"; | |
4652 | fmt = "t,r,+A,+B"; | |
4653 | } | |
4654 | else if (pos >= 32) | |
4655 | { | |
4656 | s = "dinsu"; | |
4657 | fmt = "t,r,+E,+F"; | |
4658 | } | |
4659 | else | |
4660 | { | |
4661 | s = "dinsm"; | |
4662 | fmt = "t,r,+A,+F"; | |
4663 | } | |
67c0d1eb RS |
4664 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, |
4665 | pos + size - 1); | |
5f74bc13 CD |
4666 | } |
4667 | return; | |
4668 | ||
252b5132 RH |
4669 | case M_DDIV_3: |
4670 | dbl = 1; | |
4671 | case M_DIV_3: | |
4672 | s = "mflo"; | |
4673 | goto do_div3; | |
4674 | case M_DREM_3: | |
4675 | dbl = 1; | |
4676 | case M_REM_3: | |
4677 | s = "mfhi"; | |
4678 | do_div3: | |
4679 | if (treg == 0) | |
4680 | { | |
4681 | as_warn (_("Divide by zero.")); | |
4682 | if (mips_trap) | |
67c0d1eb | 4683 | macro_build (NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 4684 | else |
67c0d1eb | 4685 | macro_build (NULL, "break", "c", 7); |
252b5132 RH |
4686 | return; |
4687 | } | |
4688 | ||
b34976b6 | 4689 | mips_emit_delays (TRUE); |
252b5132 RH |
4690 | ++mips_opts.noreorder; |
4691 | mips_any_noreorder = 1; | |
4692 | if (mips_trap) | |
4693 | { | |
67c0d1eb RS |
4694 | macro_build (NULL, "teq", "s,t,q", treg, 0, 7); |
4695 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); | |
252b5132 RH |
4696 | } |
4697 | else | |
4698 | { | |
4699 | expr1.X_add_number = 8; | |
67c0d1eb RS |
4700 | macro_build (&expr1, "bne", "s,t,p", treg, 0); |
4701 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); | |
4702 | macro_build (NULL, "break", "c", 7); | |
252b5132 RH |
4703 | } |
4704 | expr1.X_add_number = -1; | |
f6a22291 | 4705 | load_register (AT, &expr1, dbl); |
252b5132 | 4706 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
67c0d1eb | 4707 | macro_build (&expr1, "bne", "s,t,p", treg, AT); |
252b5132 RH |
4708 | if (dbl) |
4709 | { | |
4710 | expr1.X_add_number = 1; | |
f6a22291 | 4711 | load_register (AT, &expr1, dbl); |
67c0d1eb | 4712 | macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31); |
252b5132 RH |
4713 | } |
4714 | else | |
4715 | { | |
4716 | expr1.X_add_number = 0x80000000; | |
67c0d1eb | 4717 | macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16); |
252b5132 RH |
4718 | } |
4719 | if (mips_trap) | |
4720 | { | |
67c0d1eb | 4721 | macro_build (NULL, "teq", "s,t,q", sreg, AT, 6); |
252b5132 RH |
4722 | /* We want to close the noreorder block as soon as possible, so |
4723 | that later insns are available for delay slot filling. */ | |
4724 | --mips_opts.noreorder; | |
4725 | } | |
4726 | else | |
4727 | { | |
4728 | expr1.X_add_number = 8; | |
67c0d1eb RS |
4729 | macro_build (&expr1, "bne", "s,t,p", sreg, AT); |
4730 | macro_build (NULL, "nop", "", 0); | |
252b5132 RH |
4731 | |
4732 | /* We want to close the noreorder block as soon as possible, so | |
4733 | that later insns are available for delay slot filling. */ | |
4734 | --mips_opts.noreorder; | |
4735 | ||
67c0d1eb | 4736 | macro_build (NULL, "break", "c", 6); |
252b5132 | 4737 | } |
67c0d1eb | 4738 | macro_build (NULL, s, "d", dreg); |
252b5132 RH |
4739 | break; |
4740 | ||
4741 | case M_DIV_3I: | |
4742 | s = "div"; | |
4743 | s2 = "mflo"; | |
4744 | goto do_divi; | |
4745 | case M_DIVU_3I: | |
4746 | s = "divu"; | |
4747 | s2 = "mflo"; | |
4748 | goto do_divi; | |
4749 | case M_REM_3I: | |
4750 | s = "div"; | |
4751 | s2 = "mfhi"; | |
4752 | goto do_divi; | |
4753 | case M_REMU_3I: | |
4754 | s = "divu"; | |
4755 | s2 = "mfhi"; | |
4756 | goto do_divi; | |
4757 | case M_DDIV_3I: | |
4758 | dbl = 1; | |
4759 | s = "ddiv"; | |
4760 | s2 = "mflo"; | |
4761 | goto do_divi; | |
4762 | case M_DDIVU_3I: | |
4763 | dbl = 1; | |
4764 | s = "ddivu"; | |
4765 | s2 = "mflo"; | |
4766 | goto do_divi; | |
4767 | case M_DREM_3I: | |
4768 | dbl = 1; | |
4769 | s = "ddiv"; | |
4770 | s2 = "mfhi"; | |
4771 | goto do_divi; | |
4772 | case M_DREMU_3I: | |
4773 | dbl = 1; | |
4774 | s = "ddivu"; | |
4775 | s2 = "mfhi"; | |
4776 | do_divi: | |
4777 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4778 | { | |
4779 | as_warn (_("Divide by zero.")); | |
4780 | if (mips_trap) | |
67c0d1eb | 4781 | macro_build (NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 4782 | else |
67c0d1eb | 4783 | macro_build (NULL, "break", "c", 7); |
252b5132 RH |
4784 | return; |
4785 | } | |
4786 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4787 | { | |
4788 | if (strcmp (s2, "mflo") == 0) | |
67c0d1eb | 4789 | move_register (dreg, sreg); |
252b5132 | 4790 | else |
67c0d1eb | 4791 | move_register (dreg, 0); |
252b5132 RH |
4792 | return; |
4793 | } | |
4794 | if (imm_expr.X_op == O_constant | |
4795 | && imm_expr.X_add_number == -1 | |
4796 | && s[strlen (s) - 1] != 'u') | |
4797 | { | |
4798 | if (strcmp (s2, "mflo") == 0) | |
4799 | { | |
67c0d1eb | 4800 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg); |
252b5132 RH |
4801 | } |
4802 | else | |
67c0d1eb | 4803 | move_register (dreg, 0); |
252b5132 RH |
4804 | return; |
4805 | } | |
4806 | ||
67c0d1eb RS |
4807 | load_register (AT, &imm_expr, dbl); |
4808 | macro_build (NULL, s, "z,s,t", sreg, AT); | |
4809 | macro_build (NULL, s2, "d", dreg); | |
252b5132 RH |
4810 | break; |
4811 | ||
4812 | case M_DIVU_3: | |
4813 | s = "divu"; | |
4814 | s2 = "mflo"; | |
4815 | goto do_divu3; | |
4816 | case M_REMU_3: | |
4817 | s = "divu"; | |
4818 | s2 = "mfhi"; | |
4819 | goto do_divu3; | |
4820 | case M_DDIVU_3: | |
4821 | s = "ddivu"; | |
4822 | s2 = "mflo"; | |
4823 | goto do_divu3; | |
4824 | case M_DREMU_3: | |
4825 | s = "ddivu"; | |
4826 | s2 = "mfhi"; | |
4827 | do_divu3: | |
b34976b6 | 4828 | mips_emit_delays (TRUE); |
252b5132 RH |
4829 | ++mips_opts.noreorder; |
4830 | mips_any_noreorder = 1; | |
4831 | if (mips_trap) | |
4832 | { | |
67c0d1eb RS |
4833 | macro_build (NULL, "teq", "s,t,q", treg, 0, 7); |
4834 | macro_build (NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
4835 | /* We want to close the noreorder block as soon as possible, so |
4836 | that later insns are available for delay slot filling. */ | |
4837 | --mips_opts.noreorder; | |
4838 | } | |
4839 | else | |
4840 | { | |
4841 | expr1.X_add_number = 8; | |
67c0d1eb RS |
4842 | macro_build (&expr1, "bne", "s,t,p", treg, 0); |
4843 | macro_build (NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
4844 | |
4845 | /* We want to close the noreorder block as soon as possible, so | |
4846 | that later insns are available for delay slot filling. */ | |
4847 | --mips_opts.noreorder; | |
67c0d1eb | 4848 | macro_build (NULL, "break", "c", 7); |
252b5132 | 4849 | } |
67c0d1eb | 4850 | macro_build (NULL, s2, "d", dreg); |
252b5132 RH |
4851 | return; |
4852 | ||
1abe91b1 MR |
4853 | case M_DLCA_AB: |
4854 | dbl = 1; | |
4855 | case M_LCA_AB: | |
4856 | call = 1; | |
4857 | goto do_la; | |
252b5132 RH |
4858 | case M_DLA_AB: |
4859 | dbl = 1; | |
4860 | case M_LA_AB: | |
1abe91b1 | 4861 | do_la: |
252b5132 RH |
4862 | /* Load the address of a symbol into a register. If breg is not |
4863 | zero, we then add a base register to it. */ | |
4864 | ||
3bec30a8 TS |
4865 | if (dbl && HAVE_32BIT_GPRS) |
4866 | as_warn (_("dla used to load 32-bit register")); | |
4867 | ||
c90bbe5b | 4868 | if (! dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
4869 | as_warn (_("la used to load 64-bit address")); |
4870 | ||
0c11417f MR |
4871 | if (offset_expr.X_op == O_constant |
4872 | && offset_expr.X_add_number >= -0x8000 | |
4873 | && offset_expr.X_add_number < 0x8000) | |
4874 | { | |
67c0d1eb | 4875 | macro_build (&offset_expr, |
b7c7d6c1 | 4876 | (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu", |
17a2f251 | 4877 | "t,r,j", treg, sreg, BFD_RELOC_LO16); |
0c11417f MR |
4878 | return; |
4879 | } | |
4880 | ||
afdbd6d0 CD |
4881 | if (treg == breg) |
4882 | { | |
4883 | tempreg = AT; | |
4884 | used_at = 1; | |
4885 | } | |
4886 | else | |
4887 | { | |
4888 | tempreg = treg; | |
4889 | used_at = 0; | |
4890 | } | |
4891 | ||
252b5132 RH |
4892 | /* When generating embedded PIC code, we permit expressions of |
4893 | the form | |
afdbd6d0 CD |
4894 | la $treg,foo-bar |
4895 | la $treg,foo-bar($breg) | |
bb2d6cd7 | 4896 | where bar is an address in the current section. These are used |
252b5132 RH |
4897 | when getting the addresses of functions. We don't permit |
4898 | X_add_number to be non-zero, because if the symbol is | |
4899 | external the relaxing code needs to know that any addend is | |
4900 | purely the offset to X_op_symbol. */ | |
4901 | if (mips_pic == EMBEDDED_PIC | |
4902 | && offset_expr.X_op == O_subtract | |
49309057 | 4903 | && (symbol_constant_p (offset_expr.X_op_symbol) |
bb2d6cd7 | 4904 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg |
49309057 ILT |
4905 | : (symbol_equated_p (offset_expr.X_op_symbol) |
4906 | && (S_GET_SEGMENT | |
4907 | (symbol_get_value_expression (offset_expr.X_op_symbol) | |
4908 | ->X_add_symbol) | |
bb2d6cd7 | 4909 | == now_seg))) |
bb2d6cd7 GK |
4910 | && (offset_expr.X_add_number == 0 |
4911 | || OUTPUT_FLAVOR == bfd_target_elf_flavour)) | |
252b5132 | 4912 | { |
afdbd6d0 CD |
4913 | if (breg == 0) |
4914 | { | |
4915 | tempreg = treg; | |
4916 | used_at = 0; | |
67c0d1eb RS |
4917 | macro_build (&offset_expr, "lui", "t,u", |
4918 | tempreg, BFD_RELOC_PCREL_HI16_S); | |
afdbd6d0 CD |
4919 | } |
4920 | else | |
4921 | { | |
67c0d1eb RS |
4922 | macro_build (&offset_expr, "lui", "t,u", |
4923 | tempreg, BFD_RELOC_PCREL_HI16_S); | |
4924 | macro_build (NULL, | |
4d34fb5f | 4925 | (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu", |
afdbd6d0 CD |
4926 | "d,v,t", tempreg, tempreg, breg); |
4927 | } | |
67c0d1eb | 4928 | macro_build (&offset_expr, |
4d34fb5f | 4929 | (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu", |
17a2f251 | 4930 | "t,r,j", treg, tempreg, BFD_RELOC_PCREL_LO16); |
afdbd6d0 CD |
4931 | if (! used_at) |
4932 | return; | |
4933 | break; | |
252b5132 RH |
4934 | } |
4935 | ||
4936 | if (offset_expr.X_op != O_symbol | |
4937 | && offset_expr.X_op != O_constant) | |
4938 | { | |
4939 | as_bad (_("expression too complex")); | |
4940 | offset_expr.X_op = O_constant; | |
4941 | } | |
4942 | ||
252b5132 | 4943 | if (offset_expr.X_op == O_constant) |
67c0d1eb | 4944 | load_register (tempreg, &offset_expr, |
4d34fb5f TS |
4945 | ((mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC) |
4946 | ? (dbl || HAVE_64BIT_ADDRESSES) | |
4947 | : HAVE_64BIT_ADDRESSES)); | |
252b5132 RH |
4948 | else if (mips_pic == NO_PIC) |
4949 | { | |
d6bc6245 | 4950 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 4951 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
4952 | Otherwise we want |
4953 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4954 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4955 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 4956 | so we may as well always use the latter form. |
76b3015f | 4957 | |
d6bc6245 TS |
4958 | With 64bit address space and a usable $at we want |
4959 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4960 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
4961 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4962 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
4963 | dsll32 $tempreg,0 | |
3a482fd5 | 4964 | daddu $tempreg,$tempreg,$at |
76b3015f | 4965 | |
c03099e6 | 4966 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
4967 | on superscalar processors. |
4968 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4969 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4970 | dsll $tempreg,16 | |
4971 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4972 | dsll $tempreg,16 | |
4973 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
4974 | */ | |
d6bc6245 | 4975 | if (HAVE_64BIT_ADDRESSES) |
252b5132 | 4976 | { |
e864ceca RS |
4977 | /* ??? We don't provide a GP-relative alternative for |
4978 | these macros. It used not to be possible with the | |
4979 | original relaxation code, but it could be done now. */ | |
d6bc6245 | 4980 | |
460597ba | 4981 | if (used_at == 0 && ! mips_opts.noat) |
98d3f06f | 4982 | { |
67c0d1eb | 4983 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 4984 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 4985 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 4986 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 4987 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 4988 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 4989 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 4990 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb RS |
4991 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); |
4992 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
98d3f06f KH |
4993 | used_at = 1; |
4994 | } | |
4995 | else | |
4996 | { | |
67c0d1eb | 4997 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 4998 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 4999 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5000 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb RS |
5001 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
5002 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 5003 | tempreg, tempreg, BFD_RELOC_HI16_S); |
67c0d1eb RS |
5004 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
5005 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 5006 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f KH |
5007 | } |
5008 | } | |
5009 | else | |
5010 | { | |
5011 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
5012 | && ! nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
5013 | { | |
4d7206a2 | 5014 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5015 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5016 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 5017 | relax_switch (); |
98d3f06f | 5018 | } |
67c0d1eb RS |
5019 | macro_build_lui (&offset_expr, tempreg); |
5020 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5021 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
5022 | if (mips_relax.sequence) |
5023 | relax_end (); | |
98d3f06f | 5024 | } |
252b5132 | 5025 | } |
f5040a92 | 5026 | else if (mips_pic == SVR4_PIC && ! mips_big_got && ! HAVE_NEWABI) |
252b5132 | 5027 | { |
9117d219 NC |
5028 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
5029 | ||
252b5132 RH |
5030 | /* If this is a reference to an external symbol, and there |
5031 | is no constant, we want | |
5032 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 5033 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 5034 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
5035 | For a local symbol, we want |
5036 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5037 | nop | |
5038 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5039 | ||
5040 | If we have a small constant, and this is a reference to | |
5041 | an external symbol, we want | |
5042 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5043 | nop | |
5044 | addiu $tempreg,$tempreg,<constant> | |
5045 | For a local symbol, we want the same instruction | |
5046 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
5047 | addiu instruction. | |
5048 | ||
5049 | If we have a large constant, and this is a reference to | |
5050 | an external symbol, we want | |
5051 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5052 | lui $at,<hiconstant> | |
5053 | addiu $at,$at,<loconstant> | |
5054 | addu $tempreg,$tempreg,$at | |
5055 | For a local symbol, we want the same instruction | |
5056 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 5057 | addiu instruction. |
ed6fb7bd SC |
5058 | */ |
5059 | ||
4d7206a2 | 5060 | if (offset_expr.X_add_number == 0) |
252b5132 | 5061 | { |
4d7206a2 RS |
5062 | if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
5063 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; | |
5064 | ||
5065 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
5066 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5067 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 5068 | if (breg != 0) |
252b5132 RH |
5069 | { |
5070 | /* We're going to put in an addu instruction using | |
5071 | tempreg, so we may as well insert the nop right | |
5072 | now. */ | |
269137b2 | 5073 | load_delay_nop (); |
252b5132 | 5074 | } |
4d7206a2 | 5075 | relax_switch (); |
67c0d1eb RS |
5076 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5077 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 5078 | load_delay_nop (); |
67c0d1eb RS |
5079 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5080 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 5081 | relax_end (); |
252b5132 RH |
5082 | /* FIXME: If breg == 0, and the next instruction uses |
5083 | $tempreg, then if this variant case is used an extra | |
5084 | nop will be generated. */ | |
5085 | } | |
4d7206a2 RS |
5086 | else if (offset_expr.X_add_number >= -0x8000 |
5087 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 5088 | { |
67c0d1eb | 5089 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 5090 | load_delay_nop (); |
67c0d1eb | 5091 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
5092 | } |
5093 | else | |
5094 | { | |
4d7206a2 RS |
5095 | expr1.X_add_number = offset_expr.X_add_number; |
5096 | offset_expr.X_add_number = | |
5097 | ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
67c0d1eb | 5098 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 5099 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
5100 | /* If we are going to add in a base register, and the |
5101 | target register and the base register are the same, | |
5102 | then we are using AT as a temporary register. Since | |
5103 | we want to load the constant into AT, we add our | |
5104 | current AT (from the global offset table) and the | |
5105 | register into the register now, and pretend we were | |
5106 | not using a base register. */ | |
67c0d1eb | 5107 | if (breg == treg) |
252b5132 | 5108 | { |
269137b2 | 5109 | load_delay_nop (); |
67c0d1eb | 5110 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5111 | treg, AT, breg); |
252b5132 RH |
5112 | breg = 0; |
5113 | tempreg = treg; | |
252b5132 | 5114 | } |
f6a22291 | 5115 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
5116 | used_at = 1; |
5117 | } | |
5118 | } | |
f5040a92 AO |
5119 | else if (mips_pic == SVR4_PIC && ! mips_big_got && HAVE_NEWABI) |
5120 | { | |
67c0d1eb | 5121 | int add_breg_early = 0; |
f5040a92 AO |
5122 | |
5123 | /* If this is a reference to an external, and there is no | |
5124 | constant, or local symbol (*), with or without a | |
5125 | constant, we want | |
5126 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 5127 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5128 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
5129 | ||
5130 | If we have a small constant, and this is a reference to | |
5131 | an external symbol, we want | |
5132 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5133 | addiu $tempreg,$tempreg,<constant> | |
5134 | ||
5135 | If we have a large constant, and this is a reference to | |
5136 | an external symbol, we want | |
5137 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5138 | lui $at,<hiconstant> | |
5139 | addiu $at,$at,<loconstant> | |
5140 | addu $tempreg,$tempreg,$at | |
5141 | ||
5142 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
5143 | local symbols, even though it introduces an additional | |
5144 | instruction. */ | |
5145 | ||
f5040a92 AO |
5146 | if (offset_expr.X_add_number) |
5147 | { | |
4d7206a2 | 5148 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5149 | offset_expr.X_add_number = 0; |
5150 | ||
4d7206a2 | 5151 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5152 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5153 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5154 | |
5155 | if (expr1.X_add_number >= -0x8000 | |
5156 | && expr1.X_add_number < 0x8000) | |
5157 | { | |
67c0d1eb RS |
5158 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
5159 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 5160 | } |
ecd13cd3 | 5161 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 AO |
5162 | { |
5163 | int dreg; | |
5164 | ||
5165 | /* If we are going to add in a base register, and the | |
5166 | target register and the base register are the same, | |
5167 | then we are using AT as a temporary register. Since | |
5168 | we want to load the constant into AT, we add our | |
5169 | current AT (from the global offset table) and the | |
5170 | register into the register now, and pretend we were | |
5171 | not using a base register. */ | |
5172 | if (breg != treg) | |
5173 | dreg = tempreg; | |
5174 | else | |
5175 | { | |
5176 | assert (tempreg == AT); | |
67c0d1eb RS |
5177 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
5178 | treg, AT, breg); | |
f5040a92 | 5179 | dreg = treg; |
67c0d1eb | 5180 | add_breg_early = 1; |
f5040a92 AO |
5181 | } |
5182 | ||
f6a22291 | 5183 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5184 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5185 | dreg, dreg, AT); |
f5040a92 | 5186 | |
f5040a92 AO |
5187 | used_at = 1; |
5188 | } | |
5189 | else | |
5190 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5191 | ||
4d7206a2 | 5192 | relax_switch (); |
f5040a92 AO |
5193 | offset_expr.X_add_number = expr1.X_add_number; |
5194 | ||
67c0d1eb RS |
5195 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5196 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
5197 | if (add_breg_early) | |
f5040a92 | 5198 | { |
67c0d1eb | 5199 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
f899b4b8 | 5200 | treg, tempreg, breg); |
f5040a92 AO |
5201 | breg = 0; |
5202 | tempreg = treg; | |
5203 | } | |
4d7206a2 | 5204 | relax_end (); |
f5040a92 | 5205 | } |
4d7206a2 | 5206 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 5207 | { |
4d7206a2 | 5208 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5209 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5210 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 5211 | relax_switch (); |
67c0d1eb RS |
5212 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5213 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 5214 | relax_end (); |
f5040a92 | 5215 | } |
4d7206a2 | 5216 | else |
f5040a92 | 5217 | { |
67c0d1eb RS |
5218 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5219 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5220 | } |
5221 | } | |
5222 | else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI) | |
252b5132 | 5223 | { |
67c0d1eb | 5224 | int gpdelay; |
9117d219 NC |
5225 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5226 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 5227 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
5228 | |
5229 | /* This is the large GOT case. If this is a reference to an | |
5230 | external symbol, and there is no constant, we want | |
5231 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5232 | addu $tempreg,$tempreg,$gp | |
5233 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5234 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
5235 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5236 | addu $tempreg,$tempreg,$gp | |
5237 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
5238 | For a local symbol, we want |
5239 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5240 | nop | |
5241 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5242 | ||
5243 | If we have a small constant, and this is a reference to | |
5244 | an external symbol, we want | |
5245 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5246 | addu $tempreg,$tempreg,$gp | |
5247 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5248 | nop | |
5249 | addiu $tempreg,$tempreg,<constant> | |
5250 | For a local symbol, we want | |
5251 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5252 | nop | |
5253 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
5254 | ||
5255 | If we have a large constant, and this is a reference to | |
5256 | an external symbol, we want | |
5257 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5258 | addu $tempreg,$tempreg,$gp | |
5259 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5260 | lui $at,<hiconstant> | |
5261 | addiu $at,$at,<loconstant> | |
5262 | addu $tempreg,$tempreg,$at | |
5263 | For a local symbol, we want | |
5264 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5265 | lui $at,<hiconstant> | |
5266 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
5267 | addu $tempreg,$tempreg,$at | |
f5040a92 | 5268 | */ |
438c16b8 | 5269 | |
252b5132 RH |
5270 | expr1.X_add_number = offset_expr.X_add_number; |
5271 | offset_expr.X_add_number = 0; | |
4d7206a2 | 5272 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 5273 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
5274 | if (expr1.X_add_number == 0 && breg == 0 |
5275 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
5276 | { |
5277 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5278 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5279 | } | |
67c0d1eb RS |
5280 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
5281 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5282 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 5283 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 5284 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
5285 | if (expr1.X_add_number == 0) |
5286 | { | |
67c0d1eb | 5287 | if (breg != 0) |
252b5132 RH |
5288 | { |
5289 | /* We're going to put in an addu instruction using | |
5290 | tempreg, so we may as well insert the nop right | |
5291 | now. */ | |
269137b2 | 5292 | load_delay_nop (); |
252b5132 | 5293 | } |
252b5132 RH |
5294 | } |
5295 | else if (expr1.X_add_number >= -0x8000 | |
5296 | && expr1.X_add_number < 0x8000) | |
5297 | { | |
269137b2 | 5298 | load_delay_nop (); |
67c0d1eb | 5299 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5300 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
5301 | } |
5302 | else | |
5303 | { | |
67c0d1eb | 5304 | int dreg; |
252b5132 RH |
5305 | |
5306 | /* If we are going to add in a base register, and the | |
5307 | target register and the base register are the same, | |
5308 | then we are using AT as a temporary register. Since | |
5309 | we want to load the constant into AT, we add our | |
5310 | current AT (from the global offset table) and the | |
5311 | register into the register now, and pretend we were | |
5312 | not using a base register. */ | |
5313 | if (breg != treg) | |
67c0d1eb | 5314 | dreg = tempreg; |
252b5132 RH |
5315 | else |
5316 | { | |
5317 | assert (tempreg == AT); | |
269137b2 | 5318 | load_delay_nop (); |
67c0d1eb | 5319 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5320 | treg, AT, breg); |
252b5132 | 5321 | dreg = treg; |
252b5132 RH |
5322 | } |
5323 | ||
f6a22291 | 5324 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5325 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 5326 | |
252b5132 RH |
5327 | used_at = 1; |
5328 | } | |
4d7206a2 RS |
5329 | offset_expr.X_add_number = |
5330 | ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
5331 | relax_switch (); | |
252b5132 | 5332 | |
67c0d1eb | 5333 | if (gpdelay) |
252b5132 RH |
5334 | { |
5335 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 5336 | the first instruction on the main stream does not. */ |
67c0d1eb | 5337 | macro_build (NULL, "nop", ""); |
252b5132 | 5338 | } |
ed6fb7bd | 5339 | |
67c0d1eb RS |
5340 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5341 | local_reloc_type, mips_gp_register); | |
f5040a92 | 5342 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
5343 | && expr1.X_add_number < 0x8000) |
5344 | { | |
269137b2 | 5345 | load_delay_nop (); |
67c0d1eb RS |
5346 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5347 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 5348 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
5349 | register, the external symbol case ended with a load, |
5350 | so if the symbol turns out to not be external, and | |
5351 | the next instruction uses tempreg, an unnecessary nop | |
5352 | will be inserted. */ | |
252b5132 RH |
5353 | } |
5354 | else | |
5355 | { | |
5356 | if (breg == treg) | |
5357 | { | |
5358 | /* We must add in the base register now, as in the | |
f5040a92 | 5359 | external symbol case. */ |
252b5132 | 5360 | assert (tempreg == AT); |
269137b2 | 5361 | load_delay_nop (); |
67c0d1eb | 5362 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5363 | treg, AT, breg); |
252b5132 RH |
5364 | tempreg = treg; |
5365 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 5366 | it in in both cases. */ |
252b5132 RH |
5367 | breg = 0; |
5368 | } | |
5369 | ||
67c0d1eb RS |
5370 | macro_build_lui (&expr1, AT); |
5371 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 5372 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 5373 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5374 | tempreg, tempreg, AT); |
252b5132 | 5375 | } |
4d7206a2 | 5376 | relax_end (); |
252b5132 | 5377 | } |
f5040a92 AO |
5378 | else if (mips_pic == SVR4_PIC && HAVE_NEWABI) |
5379 | { | |
f5040a92 AO |
5380 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5381 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 5382 | int add_breg_early = 0; |
f5040a92 AO |
5383 | |
5384 | /* This is the large GOT case. If this is a reference to an | |
5385 | external symbol, and there is no constant, we want | |
5386 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5387 | add $tempreg,$tempreg,$gp | |
5388 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5389 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5390 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5391 | add $tempreg,$tempreg,$gp | |
5392 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
5393 | ||
5394 | If we have a small constant, and this is a reference to | |
5395 | an external symbol, we want | |
5396 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5397 | add $tempreg,$tempreg,$gp | |
5398 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5399 | addi $tempreg,$tempreg,<constant> | |
5400 | ||
5401 | If we have a large constant, and this is a reference to | |
5402 | an external symbol, we want | |
5403 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5404 | addu $tempreg,$tempreg,$gp | |
5405 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5406 | lui $at,<hiconstant> | |
5407 | addi $at,$at,<loconstant> | |
5408 | add $tempreg,$tempreg,$at | |
5409 | ||
5410 | If we have NewABI, and we know it's a local symbol, we want | |
5411 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
5412 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
5413 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
5414 | ||
4d7206a2 | 5415 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 5416 | |
4d7206a2 | 5417 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5418 | offset_expr.X_add_number = 0; |
5419 | ||
1abe91b1 MR |
5420 | if (expr1.X_add_number == 0 && breg == 0 |
5421 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
5422 | { |
5423 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5424 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5425 | } | |
67c0d1eb RS |
5426 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
5427 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5428 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
5429 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5430 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
5431 | |
5432 | if (expr1.X_add_number == 0) | |
4d7206a2 | 5433 | ; |
f5040a92 AO |
5434 | else if (expr1.X_add_number >= -0x8000 |
5435 | && expr1.X_add_number < 0x8000) | |
5436 | { | |
67c0d1eb | 5437 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5438 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 5439 | } |
ecd13cd3 | 5440 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 AO |
5441 | { |
5442 | int dreg; | |
5443 | ||
5444 | /* If we are going to add in a base register, and the | |
5445 | target register and the base register are the same, | |
5446 | then we are using AT as a temporary register. Since | |
5447 | we want to load the constant into AT, we add our | |
5448 | current AT (from the global offset table) and the | |
5449 | register into the register now, and pretend we were | |
5450 | not using a base register. */ | |
5451 | if (breg != treg) | |
5452 | dreg = tempreg; | |
5453 | else | |
5454 | { | |
5455 | assert (tempreg == AT); | |
67c0d1eb | 5456 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5457 | treg, AT, breg); |
f5040a92 | 5458 | dreg = treg; |
67c0d1eb | 5459 | add_breg_early = 1; |
f5040a92 AO |
5460 | } |
5461 | ||
f6a22291 | 5462 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5463 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 5464 | |
f5040a92 AO |
5465 | used_at = 1; |
5466 | } | |
5467 | else | |
5468 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5469 | ||
4d7206a2 | 5470 | relax_switch (); |
f5040a92 | 5471 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
5472 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5473 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
5474 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
5475 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
5476 | if (add_breg_early) | |
f5040a92 | 5477 | { |
67c0d1eb | 5478 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5479 | treg, tempreg, breg); |
f5040a92 AO |
5480 | breg = 0; |
5481 | tempreg = treg; | |
5482 | } | |
4d7206a2 | 5483 | relax_end (); |
f5040a92 | 5484 | } |
252b5132 RH |
5485 | else if (mips_pic == EMBEDDED_PIC) |
5486 | { | |
5487 | /* We use | |
cdf6fd85 | 5488 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 | 5489 | */ |
67c0d1eb RS |
5490 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
5491 | mips_gp_register, BFD_RELOC_GPREL16); | |
252b5132 RH |
5492 | } |
5493 | else | |
5494 | abort (); | |
5495 | ||
5496 | if (breg != 0) | |
4d34fb5f TS |
5497 | { |
5498 | char *s; | |
5499 | ||
5500 | if (mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC) | |
b7c7d6c1 | 5501 | s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu"; |
4d34fb5f | 5502 | else |
f899b4b8 | 5503 | s = ADDRESS_ADD_INSN; |
4d34fb5f | 5504 | |
67c0d1eb | 5505 | macro_build (NULL, s, "d,v,t", treg, tempreg, breg); |
4d34fb5f | 5506 | } |
252b5132 RH |
5507 | |
5508 | if (! used_at) | |
5509 | return; | |
5510 | ||
5511 | break; | |
5512 | ||
5513 | case M_J_A: | |
5514 | /* The j instruction may not be used in PIC code, since it | |
5515 | requires an absolute address. We convert it to a b | |
5516 | instruction. */ | |
5517 | if (mips_pic == NO_PIC) | |
67c0d1eb | 5518 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 5519 | else |
67c0d1eb | 5520 | macro_build (&offset_expr, "b", "p"); |
252b5132 RH |
5521 | return; |
5522 | ||
5523 | /* The jal instructions must be handled as macros because when | |
5524 | generating PIC code they expand to multi-instruction | |
5525 | sequences. Normally they are simple instructions. */ | |
5526 | case M_JAL_1: | |
5527 | dreg = RA; | |
5528 | /* Fall through. */ | |
5529 | case M_JAL_2: | |
5530 | if (mips_pic == NO_PIC | |
5531 | || mips_pic == EMBEDDED_PIC) | |
67c0d1eb | 5532 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
252b5132 RH |
5533 | else if (mips_pic == SVR4_PIC) |
5534 | { | |
5535 | if (sreg != PIC_CALL_REG) | |
5536 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 5537 | |
67c0d1eb | 5538 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
6478892d | 5539 | if (! HAVE_NEWABI) |
252b5132 | 5540 | { |
6478892d TS |
5541 | if (mips_cprestore_offset < 0) |
5542 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5543 | else | |
5544 | { | |
7a621144 DJ |
5545 | if (! mips_frame_reg_valid) |
5546 | { | |
5547 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5548 | /* Quiet this warning. */ | |
5549 | mips_frame_reg_valid = 1; | |
5550 | } | |
5551 | if (! mips_cprestore_valid) | |
5552 | { | |
5553 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5554 | /* Quiet this warning. */ | |
5555 | mips_cprestore_valid = 1; | |
5556 | } | |
6478892d | 5557 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 5558 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 5559 | mips_gp_register, |
256ab948 TS |
5560 | mips_frame_reg, |
5561 | HAVE_64BIT_ADDRESSES); | |
6478892d | 5562 | } |
252b5132 RH |
5563 | } |
5564 | } | |
5565 | else | |
5566 | abort (); | |
5567 | ||
5568 | return; | |
5569 | ||
5570 | case M_JAL_A: | |
5571 | if (mips_pic == NO_PIC) | |
67c0d1eb | 5572 | macro_build (&offset_expr, "jal", "a"); |
252b5132 RH |
5573 | else if (mips_pic == SVR4_PIC) |
5574 | { | |
5575 | /* If this is a reference to an external symbol, and we are | |
5576 | using a small GOT, we want | |
5577 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
5578 | nop | |
f9419b05 | 5579 | jalr $ra,$25 |
252b5132 RH |
5580 | nop |
5581 | lw $gp,cprestore($sp) | |
5582 | The cprestore value is set using the .cprestore | |
5583 | pseudo-op. If we are using a big GOT, we want | |
5584 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
5585 | addu $25,$25,$gp | |
5586 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
5587 | nop | |
f9419b05 | 5588 | jalr $ra,$25 |
252b5132 RH |
5589 | nop |
5590 | lw $gp,cprestore($sp) | |
5591 | If the symbol is not external, we want | |
5592 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5593 | nop | |
5594 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 5595 | jalr $ra,$25 |
252b5132 | 5596 | nop |
438c16b8 | 5597 | lw $gp,cprestore($sp) |
f5040a92 AO |
5598 | |
5599 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
5600 | sequences above, minus nops, unless the symbol is local, | |
5601 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
5602 | GOT_DISP. */ | |
438c16b8 | 5603 | if (HAVE_NEWABI) |
252b5132 | 5604 | { |
f5040a92 AO |
5605 | if (! mips_big_got) |
5606 | { | |
4d7206a2 | 5607 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5608 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5609 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 5610 | mips_gp_register); |
4d7206a2 | 5611 | relax_switch (); |
67c0d1eb RS |
5612 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5613 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
5614 | mips_gp_register); |
5615 | relax_end (); | |
f5040a92 AO |
5616 | } |
5617 | else | |
5618 | { | |
4d7206a2 | 5619 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5620 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, |
5621 | BFD_RELOC_MIPS_CALL_HI16); | |
5622 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
5623 | PIC_CALL_REG, mips_gp_register); | |
5624 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
5625 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
5626 | PIC_CALL_REG); | |
4d7206a2 | 5627 | relax_switch (); |
67c0d1eb RS |
5628 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5629 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
5630 | mips_gp_register); | |
5631 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5632 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 5633 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 5634 | relax_end (); |
f5040a92 | 5635 | } |
684022ea | 5636 | |
67c0d1eb | 5637 | macro_build_jalr (&offset_expr); |
252b5132 RH |
5638 | } |
5639 | else | |
5640 | { | |
4d7206a2 | 5641 | relax_start (offset_expr.X_add_symbol); |
438c16b8 TS |
5642 | if (! mips_big_got) |
5643 | { | |
67c0d1eb RS |
5644 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5645 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 5646 | mips_gp_register); |
269137b2 | 5647 | load_delay_nop (); |
4d7206a2 | 5648 | relax_switch (); |
438c16b8 | 5649 | } |
252b5132 | 5650 | else |
252b5132 | 5651 | { |
67c0d1eb RS |
5652 | int gpdelay; |
5653 | ||
5654 | gpdelay = reg_needs_delay (mips_gp_register); | |
5655 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, | |
5656 | BFD_RELOC_MIPS_CALL_HI16); | |
5657 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
5658 | PIC_CALL_REG, mips_gp_register); | |
5659 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
5660 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
5661 | PIC_CALL_REG); | |
269137b2 | 5662 | load_delay_nop (); |
4d7206a2 | 5663 | relax_switch (); |
67c0d1eb RS |
5664 | if (gpdelay) |
5665 | macro_build (NULL, "nop", ""); | |
252b5132 | 5666 | } |
67c0d1eb RS |
5667 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5668 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 5669 | mips_gp_register); |
269137b2 | 5670 | load_delay_nop (); |
67c0d1eb RS |
5671 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5672 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 5673 | relax_end (); |
67c0d1eb | 5674 | macro_build_jalr (&offset_expr); |
438c16b8 | 5675 | |
6478892d TS |
5676 | if (mips_cprestore_offset < 0) |
5677 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5678 | else | |
5679 | { | |
7a621144 DJ |
5680 | if (! mips_frame_reg_valid) |
5681 | { | |
5682 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5683 | /* Quiet this warning. */ | |
5684 | mips_frame_reg_valid = 1; | |
5685 | } | |
5686 | if (! mips_cprestore_valid) | |
5687 | { | |
5688 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5689 | /* Quiet this warning. */ | |
5690 | mips_cprestore_valid = 1; | |
5691 | } | |
6478892d | 5692 | if (mips_opts.noreorder) |
67c0d1eb | 5693 | macro_build (NULL, "nop", ""); |
6478892d | 5694 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 5695 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 5696 | mips_gp_register, |
256ab948 TS |
5697 | mips_frame_reg, |
5698 | HAVE_64BIT_ADDRESSES); | |
6478892d | 5699 | } |
252b5132 RH |
5700 | } |
5701 | } | |
5702 | else if (mips_pic == EMBEDDED_PIC) | |
5703 | { | |
67c0d1eb | 5704 | macro_build (&offset_expr, "bal", "p"); |
252b5132 RH |
5705 | /* The linker may expand the call to a longer sequence which |
5706 | uses $at, so we must break rather than return. */ | |
5707 | break; | |
5708 | } | |
5709 | else | |
5710 | abort (); | |
5711 | ||
5712 | return; | |
5713 | ||
5714 | case M_LB_AB: | |
5715 | s = "lb"; | |
5716 | goto ld; | |
5717 | case M_LBU_AB: | |
5718 | s = "lbu"; | |
5719 | goto ld; | |
5720 | case M_LH_AB: | |
5721 | s = "lh"; | |
5722 | goto ld; | |
5723 | case M_LHU_AB: | |
5724 | s = "lhu"; | |
5725 | goto ld; | |
5726 | case M_LW_AB: | |
5727 | s = "lw"; | |
5728 | goto ld; | |
5729 | case M_LWC0_AB: | |
5730 | s = "lwc0"; | |
bdaaa2e1 | 5731 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5732 | coproc = 1; |
5733 | goto ld; | |
5734 | case M_LWC1_AB: | |
5735 | s = "lwc1"; | |
bdaaa2e1 | 5736 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5737 | coproc = 1; |
5738 | goto ld; | |
5739 | case M_LWC2_AB: | |
5740 | s = "lwc2"; | |
bdaaa2e1 | 5741 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5742 | coproc = 1; |
5743 | goto ld; | |
5744 | case M_LWC3_AB: | |
5745 | s = "lwc3"; | |
bdaaa2e1 | 5746 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5747 | coproc = 1; |
5748 | goto ld; | |
5749 | case M_LWL_AB: | |
5750 | s = "lwl"; | |
5751 | lr = 1; | |
5752 | goto ld; | |
5753 | case M_LWR_AB: | |
5754 | s = "lwr"; | |
5755 | lr = 1; | |
5756 | goto ld; | |
5757 | case M_LDC1_AB: | |
fef14a42 | 5758 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
5759 | { |
5760 | as_bad (_("opcode not supported on this processor")); | |
5761 | return; | |
5762 | } | |
5763 | s = "ldc1"; | |
bdaaa2e1 | 5764 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5765 | coproc = 1; |
5766 | goto ld; | |
5767 | case M_LDC2_AB: | |
5768 | s = "ldc2"; | |
bdaaa2e1 | 5769 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5770 | coproc = 1; |
5771 | goto ld; | |
5772 | case M_LDC3_AB: | |
5773 | s = "ldc3"; | |
bdaaa2e1 | 5774 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5775 | coproc = 1; |
5776 | goto ld; | |
5777 | case M_LDL_AB: | |
5778 | s = "ldl"; | |
5779 | lr = 1; | |
5780 | goto ld; | |
5781 | case M_LDR_AB: | |
5782 | s = "ldr"; | |
5783 | lr = 1; | |
5784 | goto ld; | |
5785 | case M_LL_AB: | |
5786 | s = "ll"; | |
5787 | goto ld; | |
5788 | case M_LLD_AB: | |
5789 | s = "lld"; | |
5790 | goto ld; | |
5791 | case M_LWU_AB: | |
5792 | s = "lwu"; | |
5793 | ld: | |
5794 | if (breg == treg || coproc || lr) | |
5795 | { | |
5796 | tempreg = AT; | |
5797 | used_at = 1; | |
5798 | } | |
5799 | else | |
5800 | { | |
5801 | tempreg = treg; | |
5802 | used_at = 0; | |
5803 | } | |
5804 | goto ld_st; | |
5805 | case M_SB_AB: | |
5806 | s = "sb"; | |
5807 | goto st; | |
5808 | case M_SH_AB: | |
5809 | s = "sh"; | |
5810 | goto st; | |
5811 | case M_SW_AB: | |
5812 | s = "sw"; | |
5813 | goto st; | |
5814 | case M_SWC0_AB: | |
5815 | s = "swc0"; | |
bdaaa2e1 | 5816 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5817 | coproc = 1; |
5818 | goto st; | |
5819 | case M_SWC1_AB: | |
5820 | s = "swc1"; | |
bdaaa2e1 | 5821 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5822 | coproc = 1; |
5823 | goto st; | |
5824 | case M_SWC2_AB: | |
5825 | s = "swc2"; | |
bdaaa2e1 | 5826 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5827 | coproc = 1; |
5828 | goto st; | |
5829 | case M_SWC3_AB: | |
5830 | s = "swc3"; | |
bdaaa2e1 | 5831 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5832 | coproc = 1; |
5833 | goto st; | |
5834 | case M_SWL_AB: | |
5835 | s = "swl"; | |
5836 | goto st; | |
5837 | case M_SWR_AB: | |
5838 | s = "swr"; | |
5839 | goto st; | |
5840 | case M_SC_AB: | |
5841 | s = "sc"; | |
5842 | goto st; | |
5843 | case M_SCD_AB: | |
5844 | s = "scd"; | |
5845 | goto st; | |
5846 | case M_SDC1_AB: | |
fef14a42 | 5847 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
5848 | { |
5849 | as_bad (_("opcode not supported on this processor")); | |
5850 | return; | |
5851 | } | |
5852 | s = "sdc1"; | |
5853 | coproc = 1; | |
bdaaa2e1 | 5854 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5855 | goto st; |
5856 | case M_SDC2_AB: | |
5857 | s = "sdc2"; | |
bdaaa2e1 | 5858 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5859 | coproc = 1; |
5860 | goto st; | |
5861 | case M_SDC3_AB: | |
5862 | s = "sdc3"; | |
bdaaa2e1 | 5863 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5864 | coproc = 1; |
5865 | goto st; | |
5866 | case M_SDL_AB: | |
5867 | s = "sdl"; | |
5868 | goto st; | |
5869 | case M_SDR_AB: | |
5870 | s = "sdr"; | |
5871 | st: | |
5872 | tempreg = AT; | |
5873 | used_at = 1; | |
5874 | ld_st: | |
bdaaa2e1 | 5875 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5876 | if (mask == M_LWC1_AB |
5877 | || mask == M_SWC1_AB | |
5878 | || mask == M_LDC1_AB | |
5879 | || mask == M_SDC1_AB | |
5880 | || mask == M_L_DAB | |
5881 | || mask == M_S_DAB) | |
5882 | fmt = "T,o(b)"; | |
5883 | else if (coproc) | |
5884 | fmt = "E,o(b)"; | |
5885 | else | |
5886 | fmt = "t,o(b)"; | |
5887 | ||
256ab948 TS |
5888 | /* Sign-extending 32-bit constants makes their handling easier. |
5889 | The HAVE_64BIT_GPRS... part is due to the linux kernel hack | |
5890 | described below. */ | |
5891 | if ((! HAVE_64BIT_ADDRESSES | |
5892 | && (! HAVE_64BIT_GPRS && offset_expr.X_op == O_constant)) | |
d17e7bce TS |
5893 | && (offset_expr.X_op == O_constant) |
5894 | && ! ((offset_expr.X_add_number & ~((bfd_vma) 0x7fffffff)) | |
5895 | == ~((bfd_vma) 0x7fffffff))) | |
ae826530 | 5896 | { |
d17e7bce | 5897 | if (offset_expr.X_add_number & ~((bfd_vma) 0xffffffff)) |
1b8e29e5 | 5898 | as_bad (_("constant too large")); |
ae826530 | 5899 | |
1b8e29e5 TS |
5900 | offset_expr.X_add_number = (((offset_expr.X_add_number & 0xffffffff) |
5901 | ^ 0x80000000) - 0x80000000); | |
ae826530 | 5902 | } |
256ab948 | 5903 | |
afdbd6d0 CD |
5904 | /* For embedded PIC, we allow loads where the offset is calculated |
5905 | by subtracting a symbol in the current segment from an unknown | |
5906 | symbol, relative to a base register, e.g.: | |
5907 | <op> $treg, <sym>-<localsym>($breg) | |
5908 | This is used by the compiler for switch statements. */ | |
76b3015f | 5909 | if (mips_pic == EMBEDDED_PIC |
afdbd6d0 CD |
5910 | && offset_expr.X_op == O_subtract |
5911 | && (symbol_constant_p (offset_expr.X_op_symbol) | |
5912 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg | |
5913 | : (symbol_equated_p (offset_expr.X_op_symbol) | |
5914 | && (S_GET_SEGMENT | |
5915 | (symbol_get_value_expression (offset_expr.X_op_symbol) | |
5916 | ->X_add_symbol) | |
5917 | == now_seg))) | |
5918 | && breg != 0 | |
5919 | && (offset_expr.X_add_number == 0 | |
5920 | || OUTPUT_FLAVOR == bfd_target_elf_flavour)) | |
5921 | { | |
5922 | /* For this case, we output the instructions: | |
5923 | lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S) | |
5924 | addiu $tempreg,$tempreg,$breg | |
5925 | <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16) | |
5926 | If the relocation would fit entirely in 16 bits, it would be | |
5927 | nice to emit: | |
5928 | <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16) | |
5929 | instead, but that seems quite difficult. */ | |
67c0d1eb | 5930 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 5931 | BFD_RELOC_PCREL_HI16_S); |
67c0d1eb RS |
5932 | macro_build (NULL, |
5933 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
5934 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
5935 | ? "addu" : "daddu"), | |
5936 | "d,v,t", tempreg, tempreg, breg); | |
5937 | macro_build (&offset_expr, s, fmt, treg, | |
5938 | BFD_RELOC_PCREL_LO16, tempreg); | |
afdbd6d0 CD |
5939 | if (! used_at) |
5940 | return; | |
5941 | break; | |
5942 | } | |
5943 | ||
252b5132 RH |
5944 | if (offset_expr.X_op != O_constant |
5945 | && offset_expr.X_op != O_symbol) | |
5946 | { | |
5947 | as_bad (_("expression too complex")); | |
5948 | offset_expr.X_op = O_constant; | |
5949 | } | |
5950 | ||
5951 | /* A constant expression in PIC code can be handled just as it | |
5952 | is in non PIC code. */ | |
5953 | if (mips_pic == NO_PIC | |
5954 | || offset_expr.X_op == O_constant) | |
5955 | { | |
5956 | /* If this is a reference to a GP relative symbol, and there | |
5957 | is no base register, we want | |
cdf6fd85 | 5958 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
5959 | Otherwise, if there is no base register, we want |
5960 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5961 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5962 | If we have a constant, we need two instructions anyhow, | |
5963 | so we always use the latter form. | |
5964 | ||
5965 | If we have a base register, and this is a reference to a | |
5966 | GP relative symbol, we want | |
5967 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 5968 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
5969 | Otherwise we want |
5970 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5971 | addu $tempreg,$tempreg,$breg | |
5972 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 5973 | With a constant we always use the latter case. |
76b3015f | 5974 | |
d6bc6245 TS |
5975 | With 64bit address space and no base register and $at usable, |
5976 | we want | |
5977 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5978 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5979 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5980 | dsll32 $tempreg,0 | |
5981 | daddu $tempreg,$at | |
5982 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5983 | If we have a base register, we want | |
5984 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5985 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5986 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5987 | daddu $at,$breg | |
5988 | dsll32 $tempreg,0 | |
5989 | daddu $tempreg,$at | |
5990 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5991 | ||
5992 | Without $at we can't generate the optimal path for superscalar | |
5993 | processors here since this would require two temporary registers. | |
5994 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5995 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5996 | dsll $tempreg,16 | |
5997 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5998 | dsll $tempreg,16 | |
5999 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6000 | If we have a base register, we want | |
6001 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6002 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6003 | dsll $tempreg,16 | |
6004 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6005 | dsll $tempreg,16 | |
6006 | daddu $tempreg,$tempreg,$breg | |
6007 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 CD |
6008 | |
6009 | If we have 64-bit addresses, as an optimization, for | |
6010 | addresses which are 32-bit constants (e.g. kseg0/kseg1 | |
6011 | addresses) we fall back to the 32-bit address generation | |
78d32a17 MR |
6012 | mechanism since it is more efficient. Note that due to |
6013 | the signed offset used by memory operations, the 32-bit | |
6014 | range is shifted down by 32768 here. This code should | |
6373ee54 CD |
6015 | probably attempt to generate 64-bit constants more |
6016 | efficiently in general. | |
9214dd3b AO |
6017 | |
6018 | As an extension for architectures with 64-bit registers, | |
6019 | we don't truncate 64-bit addresses given as literal | |
6020 | constants down to 32 bits, to support existing practice | |
6021 | in the mips64 Linux (the kernel), that compiles source | |
6022 | files with -mabi=64, assembling them as o32 or n32 (with | |
6023 | -Wa,-32 or -Wa,-n32). This is not beautiful, but since | |
6024 | the whole kernel is loaded into a memory region that is | |
67c1ffbe | 6025 | addressable with sign-extended 32-bit addresses, it is |
9214dd3b AO |
6026 | wasteful to compute the upper 32 bits of every |
6027 | non-literal address, that takes more space and time. | |
6028 | Some day this should probably be implemented as an | |
6029 | assembler option, such that the kernel doesn't have to | |
6030 | use such ugly hacks, even though it will still have to | |
6031 | end up converting the binary to ELF32 for a number of | |
6032 | platforms whose boot loaders don't support ELF64 | |
6033 | binaries. */ | |
256ab948 TS |
6034 | if ((HAVE_64BIT_ADDRESSES |
6035 | && ! (offset_expr.X_op == O_constant | |
6036 | && IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000))) | |
6037 | || (HAVE_64BIT_GPRS | |
6038 | && offset_expr.X_op == O_constant | |
6039 | && ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000))) | |
d6bc6245 | 6040 | { |
e864ceca RS |
6041 | /* ??? We don't provide a GP-relative alternative for |
6042 | these macros. It used not to be possible with the | |
6043 | original relaxation code, but it could be done now. */ | |
d6bc6245 | 6044 | |
460597ba | 6045 | if (used_at == 0 && ! mips_opts.noat) |
d6bc6245 | 6046 | { |
67c0d1eb RS |
6047 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
6048 | BFD_RELOC_MIPS_HIGHEST); | |
6049 | macro_build (&offset_expr, "lui", "t,u", AT, | |
6050 | BFD_RELOC_HI16_S); | |
6051 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6052 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 6053 | if (breg != 0) |
67c0d1eb RS |
6054 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
6055 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); | |
6056 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
6057 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, | |
6058 | tempreg); | |
d6bc6245 TS |
6059 | used_at = 1; |
6060 | } | |
6061 | else | |
6062 | { | |
67c0d1eb RS |
6063 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
6064 | BFD_RELOC_MIPS_HIGHEST); | |
6065 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6066 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
6067 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
6068 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6069 | tempreg, BFD_RELOC_HI16_S); | |
6070 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
d6bc6245 | 6071 | if (breg != 0) |
67c0d1eb | 6072 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 6073 | tempreg, tempreg, breg); |
67c0d1eb | 6074 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6075 | BFD_RELOC_LO16, tempreg); |
d6bc6245 TS |
6076 | } |
6077 | ||
6078 | return; | |
6079 | } | |
256ab948 TS |
6080 | |
6081 | if (offset_expr.X_op == O_constant | |
ecd13cd3 | 6082 | && ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000)) |
5a7a0b7b | 6083 | as_bad (_("load/store address overflow (max 32 bits)")); |
76b3015f | 6084 | |
252b5132 RH |
6085 | if (breg == 0) |
6086 | { | |
67c0d1eb RS |
6087 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6088 | && ! nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
252b5132 | 6089 | { |
4d7206a2 | 6090 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6091 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, |
6092 | mips_gp_register); | |
4d7206a2 | 6093 | relax_switch (); |
252b5132 RH |
6094 | used_at = 0; |
6095 | } | |
67c0d1eb RS |
6096 | macro_build_lui (&offset_expr, tempreg); |
6097 | macro_build (&offset_expr, s, fmt, treg, | |
17a2f251 | 6098 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
6099 | if (mips_relax.sequence) |
6100 | relax_end (); | |
252b5132 RH |
6101 | } |
6102 | else | |
6103 | { | |
67c0d1eb RS |
6104 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6105 | && ! nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
252b5132 | 6106 | { |
4d7206a2 | 6107 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6108 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6109 | tempreg, breg, mips_gp_register); |
67c0d1eb | 6110 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6111 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 6112 | relax_switch (); |
252b5132 | 6113 | } |
67c0d1eb RS |
6114 | macro_build_lui (&offset_expr, tempreg); |
6115 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6116 | tempreg, tempreg, breg); |
67c0d1eb | 6117 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6118 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
6119 | if (mips_relax.sequence) |
6120 | relax_end (); | |
252b5132 RH |
6121 | } |
6122 | } | |
6123 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
6124 | { | |
ed6fb7bd | 6125 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 6126 | |
252b5132 RH |
6127 | /* If this is a reference to an external symbol, we want |
6128 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6129 | nop | |
6130 | <op> $treg,0($tempreg) | |
6131 | Otherwise we want | |
6132 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6133 | nop | |
6134 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6135 | <op> $treg,0($tempreg) | |
f5040a92 AO |
6136 | |
6137 | For NewABI, we want | |
6138 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6139 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
6140 | ||
252b5132 RH |
6141 | If there is a base register, we add it to $tempreg before |
6142 | the <op>. If there is a constant, we stick it in the | |
6143 | <op> instruction. We don't handle constants larger than | |
6144 | 16 bits, because we have no way to load the upper 16 bits | |
6145 | (actually, we could handle them for the subset of cases | |
6146 | in which we are not using $at). */ | |
6147 | assert (offset_expr.X_op == O_symbol); | |
f5040a92 AO |
6148 | if (HAVE_NEWABI) |
6149 | { | |
67c0d1eb RS |
6150 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6151 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6152 | if (breg != 0) |
67c0d1eb | 6153 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6154 | tempreg, tempreg, breg); |
67c0d1eb | 6155 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6156 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
6157 | |
6158 | if (! used_at) | |
6159 | return; | |
6160 | ||
6161 | break; | |
6162 | } | |
252b5132 RH |
6163 | expr1.X_add_number = offset_expr.X_add_number; |
6164 | offset_expr.X_add_number = 0; | |
6165 | if (expr1.X_add_number < -0x8000 | |
6166 | || expr1.X_add_number >= 0x8000) | |
6167 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
6168 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6169 | lw_reloc_type, mips_gp_register); | |
269137b2 | 6170 | load_delay_nop (); |
4d7206a2 RS |
6171 | relax_start (offset_expr.X_add_symbol); |
6172 | relax_switch (); | |
67c0d1eb RS |
6173 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6174 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 6175 | relax_end (); |
252b5132 | 6176 | if (breg != 0) |
67c0d1eb | 6177 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6178 | tempreg, tempreg, breg); |
67c0d1eb | 6179 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6180 | } |
f5040a92 | 6181 | else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI) |
252b5132 | 6182 | { |
67c0d1eb | 6183 | int gpdelay; |
252b5132 RH |
6184 | |
6185 | /* If this is a reference to an external symbol, we want | |
6186 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6187 | addu $tempreg,$tempreg,$gp | |
6188 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6189 | <op> $treg,0($tempreg) | |
6190 | Otherwise we want | |
6191 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6192 | nop | |
6193 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6194 | <op> $treg,0($tempreg) | |
6195 | If there is a base register, we add it to $tempreg before | |
6196 | the <op>. If there is a constant, we stick it in the | |
6197 | <op> instruction. We don't handle constants larger than | |
6198 | 16 bits, because we have no way to load the upper 16 bits | |
6199 | (actually, we could handle them for the subset of cases | |
f5040a92 | 6200 | in which we are not using $at). */ |
252b5132 RH |
6201 | assert (offset_expr.X_op == O_symbol); |
6202 | expr1.X_add_number = offset_expr.X_add_number; | |
6203 | offset_expr.X_add_number = 0; | |
6204 | if (expr1.X_add_number < -0x8000 | |
6205 | || expr1.X_add_number >= 0x8000) | |
6206 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6207 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 6208 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6209 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6210 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6211 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6212 | mips_gp_register); | |
6213 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6214 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 6215 | relax_switch (); |
67c0d1eb RS |
6216 | if (gpdelay) |
6217 | macro_build (NULL, "nop", ""); | |
6218 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6219 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6220 | load_delay_nop (); |
67c0d1eb RS |
6221 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6222 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
6223 | relax_end (); |
6224 | ||
252b5132 | 6225 | if (breg != 0) |
67c0d1eb | 6226 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6227 | tempreg, tempreg, breg); |
67c0d1eb | 6228 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6229 | } |
f5040a92 AO |
6230 | else if (mips_pic == SVR4_PIC && HAVE_NEWABI) |
6231 | { | |
f5040a92 AO |
6232 | /* If this is a reference to an external symbol, we want |
6233 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6234 | add $tempreg,$tempreg,$gp | |
6235 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6236 | <op> $treg,<ofst>($tempreg) | |
6237 | Otherwise, for local symbols, we want: | |
6238 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6239 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
6240 | assert (offset_expr.X_op == O_symbol); | |
4d7206a2 | 6241 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
6242 | offset_expr.X_add_number = 0; |
6243 | if (expr1.X_add_number < -0x8000 | |
6244 | || expr1.X_add_number >= 0x8000) | |
6245 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 6246 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6247 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6248 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6249 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6250 | mips_gp_register); | |
6251 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6252 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 6253 | if (breg != 0) |
67c0d1eb | 6254 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6255 | tempreg, tempreg, breg); |
67c0d1eb | 6256 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
684022ea | 6257 | |
4d7206a2 | 6258 | relax_switch (); |
f5040a92 | 6259 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
6260 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6261 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6262 | if (breg != 0) |
67c0d1eb | 6263 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6264 | tempreg, tempreg, breg); |
67c0d1eb | 6265 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6266 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 6267 | relax_end (); |
f5040a92 | 6268 | } |
252b5132 RH |
6269 | else if (mips_pic == EMBEDDED_PIC) |
6270 | { | |
6271 | /* If there is no base register, we want | |
cdf6fd85 | 6272 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
6273 | If there is a base register, we want |
6274 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 6275 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
6276 | */ |
6277 | assert (offset_expr.X_op == O_symbol); | |
6278 | if (breg == 0) | |
6279 | { | |
67c0d1eb RS |
6280 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, |
6281 | mips_gp_register); | |
252b5132 RH |
6282 | used_at = 0; |
6283 | } | |
6284 | else | |
6285 | { | |
67c0d1eb | 6286 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6287 | tempreg, breg, mips_gp_register); |
67c0d1eb | 6288 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6289 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6290 | } |
6291 | } | |
6292 | else | |
6293 | abort (); | |
6294 | ||
6295 | if (! used_at) | |
6296 | return; | |
6297 | ||
6298 | break; | |
6299 | ||
6300 | case M_LI: | |
6301 | case M_LI_S: | |
67c0d1eb | 6302 | load_register (treg, &imm_expr, 0); |
252b5132 RH |
6303 | return; |
6304 | ||
6305 | case M_DLI: | |
67c0d1eb | 6306 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
6307 | return; |
6308 | ||
6309 | case M_LI_SS: | |
6310 | if (imm_expr.X_op == O_constant) | |
6311 | { | |
67c0d1eb RS |
6312 | load_register (AT, &imm_expr, 0); |
6313 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6314 | break; |
6315 | } | |
6316 | else | |
6317 | { | |
6318 | assert (offset_expr.X_op == O_symbol | |
6319 | && strcmp (segment_name (S_GET_SEGMENT | |
6320 | (offset_expr.X_add_symbol)), | |
6321 | ".lit4") == 0 | |
6322 | && offset_expr.X_add_number == 0); | |
67c0d1eb | 6323 | macro_build (&offset_expr, "lwc1", "T,o(b)", treg, |
17a2f251 | 6324 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
252b5132 RH |
6325 | return; |
6326 | } | |
6327 | ||
6328 | case M_LI_D: | |
ca4e0257 RS |
6329 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
6330 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
6331 | order 32 bits of the value and the low order 32 bits are either | |
6332 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
6333 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6334 | { | |
ca4e0257 | 6335 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 6336 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
6337 | else |
6338 | { | |
6339 | int hreg, lreg; | |
6340 | ||
6341 | if (target_big_endian) | |
6342 | { | |
6343 | hreg = treg; | |
6344 | lreg = treg + 1; | |
6345 | } | |
6346 | else | |
6347 | { | |
6348 | hreg = treg + 1; | |
6349 | lreg = treg; | |
6350 | } | |
6351 | ||
6352 | if (hreg <= 31) | |
67c0d1eb | 6353 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
6354 | if (lreg <= 31) |
6355 | { | |
6356 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 6357 | move_register (lreg, 0); |
252b5132 RH |
6358 | else |
6359 | { | |
6360 | assert (offset_expr.X_op == O_constant); | |
67c0d1eb | 6361 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
6362 | } |
6363 | } | |
6364 | } | |
6365 | return; | |
6366 | } | |
6367 | ||
6368 | /* We know that sym is in the .rdata section. First we get the | |
6369 | upper 16 bits of the address. */ | |
6370 | if (mips_pic == NO_PIC) | |
6371 | { | |
67c0d1eb | 6372 | macro_build_lui (&offset_expr, AT); |
252b5132 RH |
6373 | } |
6374 | else if (mips_pic == SVR4_PIC) | |
6375 | { | |
67c0d1eb RS |
6376 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6377 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
6378 | } |
6379 | else if (mips_pic == EMBEDDED_PIC) | |
6380 | { | |
6381 | /* For embedded PIC we pick up the entire address off $gp in | |
6382 | a single instruction. */ | |
67c0d1eb RS |
6383 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT, |
6384 | mips_gp_register, BFD_RELOC_GPREL16); | |
252b5132 RH |
6385 | offset_expr.X_op = O_constant; |
6386 | offset_expr.X_add_number = 0; | |
6387 | } | |
6388 | else | |
6389 | abort (); | |
bdaaa2e1 | 6390 | |
252b5132 | 6391 | /* Now we load the register(s). */ |
ca4e0257 | 6392 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 6393 | macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
6394 | else |
6395 | { | |
67c0d1eb | 6396 | macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
f9419b05 | 6397 | if (treg != RA) |
252b5132 RH |
6398 | { |
6399 | /* FIXME: How in the world do we deal with the possible | |
6400 | overflow here? */ | |
6401 | offset_expr.X_add_number += 4; | |
67c0d1eb | 6402 | macro_build (&offset_expr, "lw", "t,o(b)", |
17a2f251 | 6403 | treg + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
6404 | } |
6405 | } | |
252b5132 RH |
6406 | break; |
6407 | ||
6408 | case M_LI_DD: | |
ca4e0257 RS |
6409 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
6410 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
6411 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
6412 | the value and the low order 32 bits are either zero or in | |
6413 | OFFSET_EXPR. */ | |
252b5132 RH |
6414 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6415 | { | |
67c0d1eb | 6416 | load_register (AT, &imm_expr, HAVE_64BIT_FPRS); |
ca4e0257 RS |
6417 | if (HAVE_64BIT_FPRS) |
6418 | { | |
6419 | assert (HAVE_64BIT_GPRS); | |
67c0d1eb | 6420 | macro_build (NULL, "dmtc1", "t,S", AT, treg); |
ca4e0257 | 6421 | } |
252b5132 RH |
6422 | else |
6423 | { | |
67c0d1eb | 6424 | macro_build (NULL, "mtc1", "t,G", AT, treg + 1); |
252b5132 | 6425 | if (offset_expr.X_op == O_absent) |
67c0d1eb | 6426 | macro_build (NULL, "mtc1", "t,G", 0, treg); |
252b5132 RH |
6427 | else |
6428 | { | |
6429 | assert (offset_expr.X_op == O_constant); | |
67c0d1eb RS |
6430 | load_register (AT, &offset_expr, 0); |
6431 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6432 | } |
6433 | } | |
6434 | break; | |
6435 | } | |
6436 | ||
6437 | assert (offset_expr.X_op == O_symbol | |
6438 | && offset_expr.X_add_number == 0); | |
6439 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
6440 | if (strcmp (s, ".lit8") == 0) | |
6441 | { | |
e7af610e | 6442 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6443 | { |
67c0d1eb | 6444 | macro_build (&offset_expr, "ldc1", "T,o(b)", treg, |
17a2f251 | 6445 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
252b5132 RH |
6446 | return; |
6447 | } | |
c9914766 | 6448 | breg = mips_gp_register; |
252b5132 RH |
6449 | r = BFD_RELOC_MIPS_LITERAL; |
6450 | goto dob; | |
6451 | } | |
6452 | else | |
6453 | { | |
6454 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); | |
6455 | if (mips_pic == SVR4_PIC) | |
67c0d1eb RS |
6456 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6457 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
6458 | else |
6459 | { | |
6460 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 6461 | macro_build_lui (&offset_expr, AT); |
252b5132 | 6462 | } |
bdaaa2e1 | 6463 | |
e7af610e | 6464 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6465 | { |
67c0d1eb RS |
6466 | macro_build (&offset_expr, "ldc1", "T,o(b)", |
6467 | treg, BFD_RELOC_LO16, AT); | |
252b5132 RH |
6468 | break; |
6469 | } | |
6470 | breg = AT; | |
6471 | r = BFD_RELOC_LO16; | |
6472 | goto dob; | |
6473 | } | |
6474 | ||
6475 | case M_L_DOB: | |
fef14a42 | 6476 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6477 | { |
6478 | as_bad (_("opcode not supported on this processor")); | |
6479 | return; | |
6480 | } | |
6481 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6482 | to adjust when loading from memory. */ | |
6483 | r = BFD_RELOC_LO16; | |
6484 | dob: | |
e7af610e | 6485 | assert (mips_opts.isa == ISA_MIPS1); |
67c0d1eb | 6486 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 6487 | target_big_endian ? treg + 1 : treg, r, breg); |
252b5132 RH |
6488 | /* FIXME: A possible overflow which I don't know how to deal |
6489 | with. */ | |
6490 | offset_expr.X_add_number += 4; | |
67c0d1eb | 6491 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 6492 | target_big_endian ? treg : treg + 1, r, breg); |
252b5132 | 6493 | |
252b5132 RH |
6494 | if (breg != AT) |
6495 | return; | |
6496 | break; | |
6497 | ||
6498 | case M_L_DAB: | |
6499 | /* | |
6500 | * The MIPS assembler seems to check for X_add_number not | |
6501 | * being double aligned and generating: | |
6502 | * lui at,%hi(foo+1) | |
6503 | * addu at,at,v1 | |
6504 | * addiu at,at,%lo(foo+1) | |
6505 | * lwc1 f2,0(at) | |
6506 | * lwc1 f3,4(at) | |
6507 | * But, the resulting address is the same after relocation so why | |
6508 | * generate the extra instruction? | |
6509 | */ | |
fef14a42 | 6510 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6511 | { |
6512 | as_bad (_("opcode not supported on this processor")); | |
6513 | return; | |
6514 | } | |
bdaaa2e1 | 6515 | /* Itbl support may require additional care here. */ |
252b5132 | 6516 | coproc = 1; |
e7af610e | 6517 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6518 | { |
6519 | s = "ldc1"; | |
6520 | goto ld; | |
6521 | } | |
6522 | ||
6523 | s = "lwc1"; | |
6524 | fmt = "T,o(b)"; | |
6525 | goto ldd_std; | |
6526 | ||
6527 | case M_S_DAB: | |
fef14a42 | 6528 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6529 | { |
6530 | as_bad (_("opcode not supported on this processor")); | |
6531 | return; | |
6532 | } | |
6533 | ||
e7af610e | 6534 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6535 | { |
6536 | s = "sdc1"; | |
6537 | goto st; | |
6538 | } | |
6539 | ||
6540 | s = "swc1"; | |
6541 | fmt = "T,o(b)"; | |
bdaaa2e1 | 6542 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6543 | coproc = 1; |
6544 | goto ldd_std; | |
6545 | ||
6546 | case M_LD_AB: | |
ca4e0257 | 6547 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6548 | { |
6549 | s = "ld"; | |
6550 | goto ld; | |
6551 | } | |
6552 | ||
6553 | s = "lw"; | |
6554 | fmt = "t,o(b)"; | |
6555 | goto ldd_std; | |
6556 | ||
6557 | case M_SD_AB: | |
ca4e0257 | 6558 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6559 | { |
6560 | s = "sd"; | |
6561 | goto st; | |
6562 | } | |
6563 | ||
6564 | s = "sw"; | |
6565 | fmt = "t,o(b)"; | |
6566 | ||
6567 | ldd_std: | |
afdbd6d0 CD |
6568 | /* We do _not_ bother to allow embedded PIC (symbol-local_symbol) |
6569 | loads for the case of doing a pair of loads to simulate an 'ld'. | |
6570 | This is not currently done by the compiler, and assembly coders | |
6571 | writing embedded-pic code can cope. */ | |
6572 | ||
252b5132 RH |
6573 | if (offset_expr.X_op != O_symbol |
6574 | && offset_expr.X_op != O_constant) | |
6575 | { | |
6576 | as_bad (_("expression too complex")); | |
6577 | offset_expr.X_op = O_constant; | |
6578 | } | |
6579 | ||
6580 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6581 | to adjust when loading from memory. We set coproc if we must | |
6582 | load $fn+1 first. */ | |
bdaaa2e1 | 6583 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6584 | if (! target_big_endian) |
6585 | coproc = 0; | |
6586 | ||
6587 | if (mips_pic == NO_PIC | |
6588 | || offset_expr.X_op == O_constant) | |
6589 | { | |
6590 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 TS |
6591 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
6592 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6593 | If we have a base register, we use this |
6594 | addu $at,$breg,$gp | |
cdf6fd85 TS |
6595 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
6596 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6597 | If this is not a GP relative symbol, we want |
6598 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6599 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6600 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6601 | If there is a base register, we add it to $at after the | |
6602 | lui instruction. If there is a constant, we always use | |
6603 | the last case. */ | |
e7d556df | 6604 | if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET |
252b5132 | 6605 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
67c0d1eb | 6606 | used_at = 1; |
252b5132 RH |
6607 | else |
6608 | { | |
4d7206a2 | 6609 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
6610 | if (breg == 0) |
6611 | { | |
c9914766 | 6612 | tempreg = mips_gp_register; |
252b5132 RH |
6613 | used_at = 0; |
6614 | } | |
6615 | else | |
6616 | { | |
67c0d1eb | 6617 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6618 | AT, breg, mips_gp_register); |
252b5132 | 6619 | tempreg = AT; |
252b5132 RH |
6620 | used_at = 1; |
6621 | } | |
6622 | ||
beae10d5 | 6623 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6624 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6625 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6626 | offset_expr.X_add_number += 4; |
6627 | ||
6628 | /* Set mips_optimize to 2 to avoid inserting an | |
6629 | undesired nop. */ | |
6630 | hold_mips_optimize = mips_optimize; | |
6631 | mips_optimize = 2; | |
beae10d5 | 6632 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6633 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6634 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6635 | mips_optimize = hold_mips_optimize; |
6636 | ||
4d7206a2 | 6637 | relax_switch (); |
252b5132 RH |
6638 | |
6639 | /* We just generated two relocs. When tc_gen_reloc | |
6640 | handles this case, it will skip the first reloc and | |
6641 | handle the second. The second reloc already has an | |
6642 | extra addend of 4, which we added above. We must | |
6643 | subtract it out, and then subtract another 4 to make | |
6644 | the first reloc come out right. The second reloc | |
6645 | will come out right because we are going to add 4 to | |
6646 | offset_expr when we build its instruction below. | |
6647 | ||
6648 | If we have a symbol, then we don't want to include | |
6649 | the offset, because it will wind up being included | |
6650 | when we generate the reloc. */ | |
6651 | ||
6652 | if (offset_expr.X_op == O_constant) | |
6653 | offset_expr.X_add_number -= 8; | |
6654 | else | |
6655 | { | |
6656 | offset_expr.X_add_number = -4; | |
6657 | offset_expr.X_op = O_constant; | |
6658 | } | |
6659 | } | |
67c0d1eb | 6660 | macro_build_lui (&offset_expr, AT); |
252b5132 | 6661 | if (breg != 0) |
67c0d1eb | 6662 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6663 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6664 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6665 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6666 | /* FIXME: How do we handle overflow here? */ |
6667 | offset_expr.X_add_number += 4; | |
beae10d5 | 6668 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6669 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6670 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
6671 | if (mips_relax.sequence) |
6672 | relax_end (); | |
bdaaa2e1 | 6673 | } |
252b5132 RH |
6674 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
6675 | { | |
252b5132 RH |
6676 | /* If this is a reference to an external symbol, we want |
6677 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6678 | nop | |
6679 | <op> $treg,0($at) | |
6680 | <op> $treg+1,4($at) | |
6681 | Otherwise we want | |
6682 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6683 | nop | |
6684 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6685 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6686 | If there is a base register we add it to $at before the | |
6687 | lwc1 instructions. If there is a constant we include it | |
6688 | in the lwc1 instructions. */ | |
6689 | used_at = 1; | |
6690 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
6691 | if (expr1.X_add_number < -0x8000 |
6692 | || expr1.X_add_number >= 0x8000 - 4) | |
6693 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6694 | load_got_offset (AT, &offset_expr); |
269137b2 | 6695 | load_delay_nop (); |
252b5132 | 6696 | if (breg != 0) |
67c0d1eb | 6697 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
6698 | |
6699 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6700 | nop. */ | |
6701 | hold_mips_optimize = mips_optimize; | |
6702 | mips_optimize = 2; | |
4d7206a2 | 6703 | |
beae10d5 | 6704 | /* Itbl support may require additional care here. */ |
4d7206a2 | 6705 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6706 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
6707 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6708 | expr1.X_add_number += 4; |
67c0d1eb RS |
6709 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
6710 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6711 | relax_switch (); |
67c0d1eb RS |
6712 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
6713 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6714 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
6715 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
6716 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6717 | relax_end (); |
252b5132 | 6718 | |
4d7206a2 | 6719 | mips_optimize = hold_mips_optimize; |
252b5132 RH |
6720 | } |
6721 | else if (mips_pic == SVR4_PIC) | |
6722 | { | |
67c0d1eb | 6723 | int gpdelay; |
252b5132 RH |
6724 | |
6725 | /* If this is a reference to an external symbol, we want | |
6726 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6727 | addu $at,$at,$gp | |
6728 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
6729 | nop | |
6730 | <op> $treg,0($at) | |
6731 | <op> $treg+1,4($at) | |
6732 | Otherwise we want | |
6733 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6734 | nop | |
6735 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6736 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6737 | If there is a base register we add it to $at before the | |
6738 | lwc1 instructions. If there is a constant we include it | |
6739 | in the lwc1 instructions. */ | |
6740 | used_at = 1; | |
6741 | expr1.X_add_number = offset_expr.X_add_number; | |
6742 | offset_expr.X_add_number = 0; | |
6743 | if (expr1.X_add_number < -0x8000 | |
6744 | || expr1.X_add_number >= 0x8000 - 4) | |
6745 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6746 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 6747 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6748 | macro_build (&offset_expr, "lui", "t,u", |
6749 | AT, BFD_RELOC_MIPS_GOT_HI16); | |
6750 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6751 | AT, AT, mips_gp_register); |
67c0d1eb | 6752 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 6753 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 6754 | load_delay_nop (); |
252b5132 | 6755 | if (breg != 0) |
67c0d1eb | 6756 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6757 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6758 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6759 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6760 | expr1.X_add_number += 4; |
6761 | ||
6762 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6763 | nop. */ | |
6764 | hold_mips_optimize = mips_optimize; | |
6765 | mips_optimize = 2; | |
beae10d5 | 6766 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6767 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6768 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6769 | mips_optimize = hold_mips_optimize; |
6770 | expr1.X_add_number -= 4; | |
6771 | ||
4d7206a2 RS |
6772 | relax_switch (); |
6773 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
6774 | if (gpdelay) |
6775 | macro_build (NULL, "nop", ""); | |
6776 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
6777 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6778 | load_delay_nop (); |
252b5132 | 6779 | if (breg != 0) |
67c0d1eb | 6780 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6781 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
6782 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
6783 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6784 | offset_expr.X_add_number += 4; |
252b5132 RH |
6785 | |
6786 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6787 | nop. */ | |
6788 | hold_mips_optimize = mips_optimize; | |
6789 | mips_optimize = 2; | |
beae10d5 | 6790 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
6791 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
6792 | BFD_RELOC_LO16, AT); | |
252b5132 | 6793 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 6794 | relax_end (); |
252b5132 RH |
6795 | } |
6796 | else if (mips_pic == EMBEDDED_PIC) | |
6797 | { | |
6798 | /* If there is no base register, we use | |
cdf6fd85 TS |
6799 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
6800 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6801 | If we have a base register, we use |
6802 | addu $at,$breg,$gp | |
cdf6fd85 TS |
6803 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
6804 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6805 | */ |
6806 | if (breg == 0) | |
6807 | { | |
c9914766 | 6808 | tempreg = mips_gp_register; |
252b5132 RH |
6809 | used_at = 0; |
6810 | } | |
6811 | else | |
6812 | { | |
67c0d1eb | 6813 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6814 | AT, breg, mips_gp_register); |
252b5132 RH |
6815 | tempreg = AT; |
6816 | used_at = 1; | |
6817 | } | |
6818 | ||
beae10d5 | 6819 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6820 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6821 | BFD_RELOC_GPREL16, tempreg); |
252b5132 | 6822 | offset_expr.X_add_number += 4; |
beae10d5 | 6823 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6824 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6825 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6826 | } |
6827 | else | |
6828 | abort (); | |
6829 | ||
6830 | if (! used_at) | |
6831 | return; | |
6832 | ||
6833 | break; | |
6834 | ||
6835 | case M_LD_OB: | |
6836 | s = "lw"; | |
6837 | goto sd_ob; | |
6838 | case M_SD_OB: | |
6839 | s = "sw"; | |
6840 | sd_ob: | |
ca4e0257 | 6841 | assert (HAVE_32BIT_ADDRESSES); |
67c0d1eb | 6842 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 | 6843 | offset_expr.X_add_number += 4; |
67c0d1eb | 6844 | macro_build (&offset_expr, s, "t,o(b)", treg + 1, BFD_RELOC_LO16, breg); |
252b5132 RH |
6845 | return; |
6846 | ||
6847 | /* New code added to support COPZ instructions. | |
6848 | This code builds table entries out of the macros in mip_opcodes. | |
6849 | R4000 uses interlocks to handle coproc delays. | |
6850 | Other chips (like the R3000) require nops to be inserted for delays. | |
6851 | ||
f72c8c98 | 6852 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
6853 | In order to fill delay slots for non-interlocked chips, |
6854 | we must have a way to specify delays based on the coprocessor. | |
6855 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
6856 | What are the side-effects of the cop instruction? | |
6857 | What cache support might we have and what are its effects? | |
6858 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 6859 | What registers are read/set/modified? |
252b5132 RH |
6860 | |
6861 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 6862 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
6863 | |
6864 | case M_COP0: | |
6865 | s = "c0"; | |
6866 | goto copz; | |
6867 | case M_COP1: | |
6868 | s = "c1"; | |
6869 | goto copz; | |
6870 | case M_COP2: | |
6871 | s = "c2"; | |
6872 | goto copz; | |
6873 | case M_COP3: | |
6874 | s = "c3"; | |
6875 | copz: | |
6876 | /* For now we just do C (same as Cz). The parameter will be | |
6877 | stored in insn_opcode by mips_ip. */ | |
67c0d1eb | 6878 | macro_build (NULL, s, "C", ip->insn_opcode); |
252b5132 RH |
6879 | return; |
6880 | ||
ea1fb5dc | 6881 | case M_MOVE: |
67c0d1eb | 6882 | move_register (dreg, sreg); |
ea1fb5dc RS |
6883 | return; |
6884 | ||
252b5132 RH |
6885 | #ifdef LOSING_COMPILER |
6886 | default: | |
6887 | /* Try and see if this is a new itbl instruction. | |
6888 | This code builds table entries out of the macros in mip_opcodes. | |
6889 | FIXME: For now we just assemble the expression and pass it's | |
6890 | value along as a 32-bit immediate. | |
bdaaa2e1 | 6891 | We may want to have the assembler assemble this value, |
252b5132 RH |
6892 | so that we gain the assembler's knowledge of delay slots, |
6893 | symbols, etc. | |
6894 | Would it be more efficient to use mask (id) here? */ | |
bdaaa2e1 | 6895 | if (itbl_have_entries |
252b5132 | 6896 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
beae10d5 | 6897 | { |
252b5132 RH |
6898 | s = ip->insn_mo->name; |
6899 | s2 = "cop3"; | |
6900 | coproc = ITBL_DECODE_PNUM (immed_expr);; | |
67c0d1eb | 6901 | macro_build (&immed_expr, s, "C"); |
252b5132 | 6902 | return; |
beae10d5 | 6903 | } |
252b5132 RH |
6904 | macro2 (ip); |
6905 | return; | |
6906 | } | |
6907 | if (mips_opts.noat) | |
6908 | as_warn (_("Macro used $at after \".set noat\"")); | |
6909 | } | |
bdaaa2e1 | 6910 | |
252b5132 | 6911 | static void |
17a2f251 | 6912 | macro2 (struct mips_cl_insn *ip) |
252b5132 RH |
6913 | { |
6914 | register int treg, sreg, dreg, breg; | |
6915 | int tempreg; | |
6916 | int mask; | |
252b5132 RH |
6917 | int used_at; |
6918 | expressionS expr1; | |
6919 | const char *s; | |
6920 | const char *s2; | |
6921 | const char *fmt; | |
6922 | int likely = 0; | |
6923 | int dbl = 0; | |
6924 | int coproc = 0; | |
6925 | int lr = 0; | |
6926 | int imm = 0; | |
6927 | int off; | |
6928 | offsetT maxnum; | |
6929 | bfd_reloc_code_real_type r; | |
bdaaa2e1 | 6930 | |
252b5132 RH |
6931 | treg = (ip->insn_opcode >> 16) & 0x1f; |
6932 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
6933 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
6934 | mask = ip->insn_mo->mask; | |
bdaaa2e1 | 6935 | |
252b5132 RH |
6936 | expr1.X_op = O_constant; |
6937 | expr1.X_op_symbol = NULL; | |
6938 | expr1.X_add_symbol = NULL; | |
6939 | expr1.X_add_number = 1; | |
bdaaa2e1 | 6940 | |
252b5132 RH |
6941 | switch (mask) |
6942 | { | |
6943 | #endif /* LOSING_COMPILER */ | |
6944 | ||
6945 | case M_DMUL: | |
6946 | dbl = 1; | |
6947 | case M_MUL: | |
67c0d1eb RS |
6948 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg); |
6949 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 RH |
6950 | return; |
6951 | ||
6952 | case M_DMUL_I: | |
6953 | dbl = 1; | |
6954 | case M_MUL_I: | |
6955 | /* The MIPS assembler some times generates shifts and adds. I'm | |
6956 | not trying to be that fancy. GCC should do this for us | |
6957 | anyway. */ | |
67c0d1eb RS |
6958 | load_register (AT, &imm_expr, dbl); |
6959 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT); | |
6960 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 RH |
6961 | break; |
6962 | ||
6963 | case M_DMULO_I: | |
6964 | dbl = 1; | |
6965 | case M_MULO_I: | |
6966 | imm = 1; | |
6967 | goto do_mulo; | |
6968 | ||
6969 | case M_DMULO: | |
6970 | dbl = 1; | |
6971 | case M_MULO: | |
6972 | do_mulo: | |
b34976b6 | 6973 | mips_emit_delays (TRUE); |
252b5132 RH |
6974 | ++mips_opts.noreorder; |
6975 | mips_any_noreorder = 1; | |
6976 | if (imm) | |
67c0d1eb RS |
6977 | load_register (AT, &imm_expr, dbl); |
6978 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); | |
6979 | macro_build (NULL, "mflo", "d", dreg); | |
6980 | macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA); | |
6981 | macro_build (NULL, "mfhi", "d", AT); | |
252b5132 | 6982 | if (mips_trap) |
67c0d1eb | 6983 | macro_build (NULL, "tne", "s,t,q", dreg, AT, 6); |
252b5132 RH |
6984 | else |
6985 | { | |
6986 | expr1.X_add_number = 8; | |
67c0d1eb RS |
6987 | macro_build (&expr1, "beq", "s,t,p", dreg, AT); |
6988 | macro_build (NULL, "nop", "", 0); | |
6989 | macro_build (NULL, "break", "c", 6); | |
252b5132 RH |
6990 | } |
6991 | --mips_opts.noreorder; | |
67c0d1eb | 6992 | macro_build (NULL, "mflo", "d", dreg); |
252b5132 RH |
6993 | break; |
6994 | ||
6995 | case M_DMULOU_I: | |
6996 | dbl = 1; | |
6997 | case M_MULOU_I: | |
6998 | imm = 1; | |
6999 | goto do_mulou; | |
7000 | ||
7001 | case M_DMULOU: | |
7002 | dbl = 1; | |
7003 | case M_MULOU: | |
7004 | do_mulou: | |
b34976b6 | 7005 | mips_emit_delays (TRUE); |
252b5132 RH |
7006 | ++mips_opts.noreorder; |
7007 | mips_any_noreorder = 1; | |
7008 | if (imm) | |
67c0d1eb RS |
7009 | load_register (AT, &imm_expr, dbl); |
7010 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
17a2f251 | 7011 | sreg, imm ? AT : treg); |
67c0d1eb RS |
7012 | macro_build (NULL, "mfhi", "d", AT); |
7013 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 | 7014 | if (mips_trap) |
67c0d1eb | 7015 | macro_build (NULL, "tne", "s,t,q", AT, 0, 6); |
252b5132 RH |
7016 | else |
7017 | { | |
7018 | expr1.X_add_number = 8; | |
67c0d1eb RS |
7019 | macro_build (&expr1, "beq", "s,t,p", AT, 0); |
7020 | macro_build (NULL, "nop", "", 0); | |
7021 | macro_build (NULL, "break", "c", 6); | |
252b5132 RH |
7022 | } |
7023 | --mips_opts.noreorder; | |
7024 | break; | |
7025 | ||
771c7ce4 | 7026 | case M_DROL: |
fef14a42 | 7027 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
7028 | { |
7029 | if (dreg == sreg) | |
7030 | { | |
7031 | tempreg = AT; | |
7032 | used_at = 1; | |
7033 | } | |
7034 | else | |
7035 | { | |
7036 | tempreg = dreg; | |
7037 | used_at = 0; | |
7038 | } | |
67c0d1eb RS |
7039 | macro_build (NULL, "dnegu", "d,w", tempreg, treg); |
7040 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg); | |
82dd0097 CD |
7041 | if (used_at) |
7042 | break; | |
7043 | return; | |
7044 | } | |
67c0d1eb RS |
7045 | macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); |
7046 | macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT); | |
7047 | macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg); | |
7048 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7049 | break; |
7050 | ||
252b5132 | 7051 | case M_ROL: |
fef14a42 | 7052 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 CD |
7053 | { |
7054 | if (dreg == sreg) | |
7055 | { | |
7056 | tempreg = AT; | |
7057 | used_at = 1; | |
7058 | } | |
7059 | else | |
7060 | { | |
7061 | tempreg = dreg; | |
7062 | used_at = 0; | |
7063 | } | |
67c0d1eb RS |
7064 | macro_build (NULL, "negu", "d,w", tempreg, treg); |
7065 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg); | |
82dd0097 CD |
7066 | if (used_at) |
7067 | break; | |
7068 | return; | |
7069 | } | |
67c0d1eb RS |
7070 | macro_build (NULL, "subu", "d,v,t", AT, 0, treg); |
7071 | macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT); | |
7072 | macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg); | |
7073 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7074 | break; |
7075 | ||
771c7ce4 TS |
7076 | case M_DROL_I: |
7077 | { | |
7078 | unsigned int rot; | |
82dd0097 | 7079 | char *l, *r; |
771c7ce4 TS |
7080 | |
7081 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7082 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7083 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 7084 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
7085 | { |
7086 | rot = (64 - rot) & 0x3f; | |
7087 | if (rot >= 32) | |
67c0d1eb | 7088 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
60b63b72 | 7089 | else |
67c0d1eb | 7090 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
82dd0097 | 7091 | return; |
60b63b72 | 7092 | } |
483fc7cd | 7093 | if (rot == 0) |
483fc7cd | 7094 | { |
67c0d1eb | 7095 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
82dd0097 | 7096 | return; |
483fc7cd | 7097 | } |
82dd0097 CD |
7098 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
7099 | r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; | |
7100 | rot &= 0x1f; | |
67c0d1eb RS |
7101 | macro_build (NULL, l, "d,w,<", AT, sreg, rot); |
7102 | macro_build (NULL, r, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7103 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7104 | } |
7105 | break; | |
7106 | ||
252b5132 | 7107 | case M_ROL_I: |
771c7ce4 TS |
7108 | { |
7109 | unsigned int rot; | |
7110 | ||
7111 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7112 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7113 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 7114 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 7115 | { |
67c0d1eb | 7116 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f); |
82dd0097 | 7117 | return; |
60b63b72 | 7118 | } |
483fc7cd | 7119 | if (rot == 0) |
483fc7cd | 7120 | { |
67c0d1eb | 7121 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
82dd0097 | 7122 | return; |
483fc7cd | 7123 | } |
67c0d1eb RS |
7124 | macro_build (NULL, "sll", "d,w,<", AT, sreg, rot); |
7125 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7126 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7127 | } |
7128 | break; | |
7129 | ||
7130 | case M_DROR: | |
fef14a42 | 7131 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 7132 | { |
67c0d1eb | 7133 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg); |
82dd0097 CD |
7134 | return; |
7135 | } | |
67c0d1eb RS |
7136 | macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); |
7137 | macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT); | |
7138 | macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg); | |
7139 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7140 | break; |
7141 | ||
7142 | case M_ROR: | |
fef14a42 | 7143 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7144 | { |
67c0d1eb | 7145 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg); |
82dd0097 CD |
7146 | return; |
7147 | } | |
67c0d1eb RS |
7148 | macro_build (NULL, "subu", "d,v,t", AT, 0, treg); |
7149 | macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT); | |
7150 | macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg); | |
7151 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7152 | break; |
7153 | ||
771c7ce4 TS |
7154 | case M_DROR_I: |
7155 | { | |
7156 | unsigned int rot; | |
82dd0097 | 7157 | char *l, *r; |
771c7ce4 TS |
7158 | |
7159 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7160 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7161 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 7162 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
7163 | { |
7164 | if (rot >= 32) | |
67c0d1eb | 7165 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
82dd0097 | 7166 | else |
67c0d1eb | 7167 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
82dd0097 CD |
7168 | return; |
7169 | } | |
483fc7cd | 7170 | if (rot == 0) |
483fc7cd | 7171 | { |
67c0d1eb | 7172 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
82dd0097 | 7173 | return; |
483fc7cd | 7174 | } |
82dd0097 CD |
7175 | r = (rot < 0x20) ? "dsrl" : "dsrl32"; |
7176 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; | |
7177 | rot &= 0x1f; | |
67c0d1eb RS |
7178 | macro_build (NULL, r, "d,w,<", AT, sreg, rot); |
7179 | macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7180 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7181 | } |
7182 | break; | |
7183 | ||
252b5132 | 7184 | case M_ROR_I: |
771c7ce4 TS |
7185 | { |
7186 | unsigned int rot; | |
7187 | ||
7188 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7189 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7190 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 7191 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7192 | { |
67c0d1eb | 7193 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot); |
82dd0097 CD |
7194 | return; |
7195 | } | |
483fc7cd | 7196 | if (rot == 0) |
483fc7cd | 7197 | { |
67c0d1eb | 7198 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
82dd0097 | 7199 | return; |
483fc7cd | 7200 | } |
67c0d1eb RS |
7201 | macro_build (NULL, "srl", "d,w,<", AT, sreg, rot); |
7202 | macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7203 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 | 7204 | } |
252b5132 RH |
7205 | break; |
7206 | ||
7207 | case M_S_DOB: | |
fef14a42 | 7208 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
7209 | { |
7210 | as_bad (_("opcode not supported on this processor")); | |
7211 | return; | |
7212 | } | |
e7af610e | 7213 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
7214 | /* Even on a big endian machine $fn comes before $fn+1. We have |
7215 | to adjust when storing to memory. */ | |
67c0d1eb RS |
7216 | macro_build (&offset_expr, "swc1", "T,o(b)", |
7217 | target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg); | |
252b5132 | 7218 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
7219 | macro_build (&offset_expr, "swc1", "T,o(b)", |
7220 | target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg); | |
252b5132 RH |
7221 | return; |
7222 | ||
7223 | case M_SEQ: | |
7224 | if (sreg == 0) | |
67c0d1eb | 7225 | macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16); |
252b5132 | 7226 | else if (treg == 0) |
67c0d1eb | 7227 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7228 | else |
7229 | { | |
67c0d1eb RS |
7230 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7231 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
7232 | } |
7233 | return; | |
7234 | ||
7235 | case M_SEQ_I: | |
7236 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7237 | { | |
67c0d1eb | 7238 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7239 | return; |
7240 | } | |
7241 | if (sreg == 0) | |
7242 | { | |
7243 | as_warn (_("Instruction %s: result is always false"), | |
7244 | ip->insn_mo->name); | |
67c0d1eb | 7245 | move_register (dreg, 0); |
252b5132 RH |
7246 | return; |
7247 | } | |
7248 | if (imm_expr.X_op == O_constant | |
7249 | && imm_expr.X_add_number >= 0 | |
7250 | && imm_expr.X_add_number < 0x10000) | |
7251 | { | |
67c0d1eb | 7252 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7253 | used_at = 0; |
7254 | } | |
7255 | else if (imm_expr.X_op == O_constant | |
7256 | && imm_expr.X_add_number > -0x8000 | |
7257 | && imm_expr.X_add_number < 0) | |
7258 | { | |
7259 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7260 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7261 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7262 | used_at = 0; |
7263 | } | |
7264 | else | |
7265 | { | |
67c0d1eb RS |
7266 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7267 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7268 | used_at = 1; |
7269 | } | |
67c0d1eb | 7270 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); |
252b5132 RH |
7271 | if (used_at) |
7272 | break; | |
7273 | return; | |
7274 | ||
7275 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
7276 | s = "slt"; | |
7277 | goto sge; | |
7278 | case M_SGEU: | |
7279 | s = "sltu"; | |
7280 | sge: | |
67c0d1eb RS |
7281 | macro_build (NULL, s, "d,v,t", dreg, sreg, treg); |
7282 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
7283 | return; |
7284 | ||
7285 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
7286 | case M_SGEU_I: | |
7287 | if (imm_expr.X_op == O_constant | |
7288 | && imm_expr.X_add_number >= -0x8000 | |
7289 | && imm_expr.X_add_number < 0x8000) | |
7290 | { | |
67c0d1eb RS |
7291 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
7292 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
7293 | used_at = 0; |
7294 | } | |
7295 | else | |
7296 | { | |
67c0d1eb RS |
7297 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7298 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", | |
7299 | dreg, sreg, AT); | |
252b5132 RH |
7300 | used_at = 1; |
7301 | } | |
67c0d1eb | 7302 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); |
252b5132 RH |
7303 | if (used_at) |
7304 | break; | |
7305 | return; | |
7306 | ||
7307 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
7308 | s = "slt"; | |
7309 | goto sgt; | |
7310 | case M_SGTU: | |
7311 | s = "sltu"; | |
7312 | sgt: | |
67c0d1eb | 7313 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
252b5132 RH |
7314 | return; |
7315 | ||
7316 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
7317 | s = "slt"; | |
7318 | goto sgti; | |
7319 | case M_SGTU_I: | |
7320 | s = "sltu"; | |
7321 | sgti: | |
67c0d1eb RS |
7322 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7323 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
252b5132 RH |
7324 | break; |
7325 | ||
2396cfb9 | 7326 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
7327 | s = "slt"; |
7328 | goto sle; | |
7329 | case M_SLEU: | |
7330 | s = "sltu"; | |
7331 | sle: | |
67c0d1eb RS |
7332 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
7333 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
7334 | return; |
7335 | ||
2396cfb9 | 7336 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
7337 | s = "slt"; |
7338 | goto slei; | |
7339 | case M_SLEU_I: | |
7340 | s = "sltu"; | |
7341 | slei: | |
67c0d1eb RS |
7342 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7343 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
7344 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
7345 | break; |
7346 | ||
7347 | case M_SLT_I: | |
7348 | if (imm_expr.X_op == O_constant | |
7349 | && imm_expr.X_add_number >= -0x8000 | |
7350 | && imm_expr.X_add_number < 0x8000) | |
7351 | { | |
67c0d1eb | 7352 | macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7353 | return; |
7354 | } | |
67c0d1eb RS |
7355 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7356 | macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7357 | break; |
7358 | ||
7359 | case M_SLTU_I: | |
7360 | if (imm_expr.X_op == O_constant | |
7361 | && imm_expr.X_add_number >= -0x8000 | |
7362 | && imm_expr.X_add_number < 0x8000) | |
7363 | { | |
67c0d1eb | 7364 | macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg, |
17a2f251 | 7365 | BFD_RELOC_LO16); |
252b5132 RH |
7366 | return; |
7367 | } | |
67c0d1eb RS |
7368 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7369 | macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7370 | break; |
7371 | ||
7372 | case M_SNE: | |
7373 | if (sreg == 0) | |
67c0d1eb | 7374 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg); |
252b5132 | 7375 | else if (treg == 0) |
67c0d1eb | 7376 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
7377 | else |
7378 | { | |
67c0d1eb RS |
7379 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7380 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
252b5132 RH |
7381 | } |
7382 | return; | |
7383 | ||
7384 | case M_SNE_I: | |
7385 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7386 | { | |
67c0d1eb | 7387 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
7388 | return; |
7389 | } | |
7390 | if (sreg == 0) | |
7391 | { | |
7392 | as_warn (_("Instruction %s: result is always true"), | |
7393 | ip->insn_mo->name); | |
67c0d1eb RS |
7394 | macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", |
7395 | dreg, 0, BFD_RELOC_LO16); | |
252b5132 RH |
7396 | return; |
7397 | } | |
7398 | if (imm_expr.X_op == O_constant | |
7399 | && imm_expr.X_add_number >= 0 | |
7400 | && imm_expr.X_add_number < 0x10000) | |
7401 | { | |
67c0d1eb | 7402 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7403 | used_at = 0; |
7404 | } | |
7405 | else if (imm_expr.X_op == O_constant | |
7406 | && imm_expr.X_add_number > -0x8000 | |
7407 | && imm_expr.X_add_number < 0) | |
7408 | { | |
7409 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7410 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7411 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7412 | used_at = 0; |
7413 | } | |
7414 | else | |
7415 | { | |
67c0d1eb RS |
7416 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7417 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7418 | used_at = 1; |
7419 | } | |
67c0d1eb | 7420 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); |
252b5132 RH |
7421 | if (used_at) |
7422 | break; | |
7423 | return; | |
7424 | ||
7425 | case M_DSUB_I: | |
7426 | dbl = 1; | |
7427 | case M_SUB_I: | |
7428 | if (imm_expr.X_op == O_constant | |
7429 | && imm_expr.X_add_number > -0x8000 | |
7430 | && imm_expr.X_add_number <= 0x8000) | |
7431 | { | |
7432 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7433 | macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j", |
7434 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
7435 | return; |
7436 | } | |
67c0d1eb RS |
7437 | load_register (AT, &imm_expr, dbl); |
7438 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7439 | break; |
7440 | ||
7441 | case M_DSUBU_I: | |
7442 | dbl = 1; | |
7443 | case M_SUBU_I: | |
7444 | if (imm_expr.X_op == O_constant | |
7445 | && imm_expr.X_add_number > -0x8000 | |
7446 | && imm_expr.X_add_number <= 0x8000) | |
7447 | { | |
7448 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7449 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j", |
7450 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
7451 | return; |
7452 | } | |
67c0d1eb RS |
7453 | load_register (AT, &imm_expr, dbl); |
7454 | macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7455 | break; |
7456 | ||
7457 | case M_TEQ_I: | |
7458 | s = "teq"; | |
7459 | goto trap; | |
7460 | case M_TGE_I: | |
7461 | s = "tge"; | |
7462 | goto trap; | |
7463 | case M_TGEU_I: | |
7464 | s = "tgeu"; | |
7465 | goto trap; | |
7466 | case M_TLT_I: | |
7467 | s = "tlt"; | |
7468 | goto trap; | |
7469 | case M_TLTU_I: | |
7470 | s = "tltu"; | |
7471 | goto trap; | |
7472 | case M_TNE_I: | |
7473 | s = "tne"; | |
7474 | trap: | |
67c0d1eb RS |
7475 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7476 | macro_build (NULL, s, "s,t", sreg, AT); | |
252b5132 RH |
7477 | break; |
7478 | ||
252b5132 | 7479 | case M_TRUNCWS: |
43841e91 | 7480 | case M_TRUNCWD: |
e7af610e | 7481 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
7482 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
7483 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
7484 | ||
7485 | /* | |
7486 | * Is the double cfc1 instruction a bug in the mips assembler; | |
7487 | * or is there a reason for it? | |
7488 | */ | |
b34976b6 | 7489 | mips_emit_delays (TRUE); |
252b5132 RH |
7490 | ++mips_opts.noreorder; |
7491 | mips_any_noreorder = 1; | |
67c0d1eb RS |
7492 | macro_build (NULL, "cfc1", "t,G", treg, RA); |
7493 | macro_build (NULL, "cfc1", "t,G", treg, RA); | |
7494 | macro_build (NULL, "nop", ""); | |
252b5132 | 7495 | expr1.X_add_number = 3; |
67c0d1eb | 7496 | macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16); |
252b5132 | 7497 | expr1.X_add_number = 2; |
67c0d1eb RS |
7498 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
7499 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
7500 | macro_build (NULL, "nop", ""); | |
7501 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
7502 | dreg, sreg); | |
7503 | macro_build (NULL, "ctc1", "t,G", treg, RA); | |
7504 | macro_build (NULL, "nop", ""); | |
252b5132 RH |
7505 | --mips_opts.noreorder; |
7506 | break; | |
7507 | ||
7508 | case M_ULH: | |
7509 | s = "lb"; | |
7510 | goto ulh; | |
7511 | case M_ULHU: | |
7512 | s = "lbu"; | |
7513 | ulh: | |
7514 | if (offset_expr.X_add_number >= 0x7fff) | |
7515 | as_bad (_("operand overflow")); | |
252b5132 | 7516 | if (! target_big_endian) |
f9419b05 | 7517 | ++offset_expr.X_add_number; |
67c0d1eb | 7518 | macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 | 7519 | if (! target_big_endian) |
f9419b05 | 7520 | --offset_expr.X_add_number; |
252b5132 | 7521 | else |
f9419b05 | 7522 | ++offset_expr.X_add_number; |
67c0d1eb RS |
7523 | macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
7524 | macro_build (NULL, "sll", "d,w,<", AT, AT, 8); | |
7525 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7526 | break; |
7527 | ||
7528 | case M_ULD: | |
7529 | s = "ldl"; | |
7530 | s2 = "ldr"; | |
7531 | off = 7; | |
7532 | goto ulw; | |
7533 | case M_ULW: | |
7534 | s = "lwl"; | |
7535 | s2 = "lwr"; | |
7536 | off = 3; | |
7537 | ulw: | |
7538 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7539 | as_bad (_("operand overflow")); | |
af22f5b2 CD |
7540 | if (treg != breg) |
7541 | tempreg = treg; | |
7542 | else | |
7543 | tempreg = AT; | |
252b5132 RH |
7544 | if (! target_big_endian) |
7545 | offset_expr.X_add_number += off; | |
67c0d1eb | 7546 | macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7547 | if (! target_big_endian) |
7548 | offset_expr.X_add_number -= off; | |
7549 | else | |
7550 | offset_expr.X_add_number += off; | |
67c0d1eb | 7551 | macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
af22f5b2 CD |
7552 | |
7553 | /* If necessary, move the result in tempreg the final destination. */ | |
7554 | if (treg == tempreg) | |
7555 | return; | |
7556 | /* Protect second load's delay slot. */ | |
017315e4 | 7557 | load_delay_nop (); |
67c0d1eb | 7558 | move_register (treg, tempreg); |
af22f5b2 | 7559 | break; |
252b5132 RH |
7560 | |
7561 | case M_ULD_A: | |
7562 | s = "ldl"; | |
7563 | s2 = "ldr"; | |
7564 | off = 7; | |
7565 | goto ulwa; | |
7566 | case M_ULW_A: | |
7567 | s = "lwl"; | |
7568 | s2 = "lwr"; | |
7569 | off = 3; | |
7570 | ulwa: | |
d6bc6245 | 7571 | used_at = 1; |
67c0d1eb | 7572 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7573 | if (breg != 0) |
67c0d1eb | 7574 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7575 | if (! target_big_endian) |
7576 | expr1.X_add_number = off; | |
7577 | else | |
7578 | expr1.X_add_number = 0; | |
67c0d1eb | 7579 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7580 | if (! target_big_endian) |
7581 | expr1.X_add_number = 0; | |
7582 | else | |
7583 | expr1.X_add_number = off; | |
67c0d1eb | 7584 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7585 | break; |
7586 | ||
7587 | case M_ULH_A: | |
7588 | case M_ULHU_A: | |
d6bc6245 | 7589 | used_at = 1; |
67c0d1eb | 7590 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7591 | if (breg != 0) |
67c0d1eb | 7592 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7593 | if (target_big_endian) |
7594 | expr1.X_add_number = 0; | |
67c0d1eb | 7595 | macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", |
17a2f251 | 7596 | treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7597 | if (target_big_endian) |
7598 | expr1.X_add_number = 1; | |
7599 | else | |
7600 | expr1.X_add_number = 0; | |
67c0d1eb RS |
7601 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
7602 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
7603 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7604 | break; |
7605 | ||
7606 | case M_USH: | |
7607 | if (offset_expr.X_add_number >= 0x7fff) | |
7608 | as_bad (_("operand overflow")); | |
7609 | if (target_big_endian) | |
f9419b05 | 7610 | ++offset_expr.X_add_number; |
67c0d1eb RS |
7611 | macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
7612 | macro_build (NULL, "srl", "d,w,<", AT, treg, 8); | |
252b5132 | 7613 | if (target_big_endian) |
f9419b05 | 7614 | --offset_expr.X_add_number; |
252b5132 | 7615 | else |
f9419b05 | 7616 | ++offset_expr.X_add_number; |
67c0d1eb | 7617 | macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 RH |
7618 | break; |
7619 | ||
7620 | case M_USD: | |
7621 | s = "sdl"; | |
7622 | s2 = "sdr"; | |
7623 | off = 7; | |
7624 | goto usw; | |
7625 | case M_USW: | |
7626 | s = "swl"; | |
7627 | s2 = "swr"; | |
7628 | off = 3; | |
7629 | usw: | |
7630 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7631 | as_bad (_("operand overflow")); | |
7632 | if (! target_big_endian) | |
7633 | offset_expr.X_add_number += off; | |
67c0d1eb | 7634 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7635 | if (! target_big_endian) |
7636 | offset_expr.X_add_number -= off; | |
7637 | else | |
7638 | offset_expr.X_add_number += off; | |
67c0d1eb | 7639 | macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7640 | return; |
7641 | ||
7642 | case M_USD_A: | |
7643 | s = "sdl"; | |
7644 | s2 = "sdr"; | |
7645 | off = 7; | |
7646 | goto uswa; | |
7647 | case M_USW_A: | |
7648 | s = "swl"; | |
7649 | s2 = "swr"; | |
7650 | off = 3; | |
7651 | uswa: | |
d6bc6245 | 7652 | used_at = 1; |
67c0d1eb | 7653 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7654 | if (breg != 0) |
67c0d1eb | 7655 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7656 | if (! target_big_endian) |
7657 | expr1.X_add_number = off; | |
7658 | else | |
7659 | expr1.X_add_number = 0; | |
67c0d1eb | 7660 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7661 | if (! target_big_endian) |
7662 | expr1.X_add_number = 0; | |
7663 | else | |
7664 | expr1.X_add_number = off; | |
67c0d1eb | 7665 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7666 | break; |
7667 | ||
7668 | case M_USH_A: | |
d6bc6245 | 7669 | used_at = 1; |
67c0d1eb | 7670 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7671 | if (breg != 0) |
67c0d1eb | 7672 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7673 | if (! target_big_endian) |
7674 | expr1.X_add_number = 0; | |
67c0d1eb RS |
7675 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
7676 | macro_build (NULL, "srl", "d,w,<", treg, treg, 8); | |
252b5132 RH |
7677 | if (! target_big_endian) |
7678 | expr1.X_add_number = 1; | |
7679 | else | |
7680 | expr1.X_add_number = 0; | |
67c0d1eb | 7681 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7682 | if (! target_big_endian) |
7683 | expr1.X_add_number = 0; | |
7684 | else | |
7685 | expr1.X_add_number = 1; | |
67c0d1eb RS |
7686 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
7687 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
7688 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7689 | break; |
7690 | ||
7691 | default: | |
7692 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 7693 | are added dynamically. */ |
252b5132 RH |
7694 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
7695 | break; | |
7696 | } | |
7697 | if (mips_opts.noat) | |
7698 | as_warn (_("Macro used $at after \".set noat\"")); | |
7699 | } | |
7700 | ||
7701 | /* Implement macros in mips16 mode. */ | |
7702 | ||
7703 | static void | |
17a2f251 | 7704 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 RH |
7705 | { |
7706 | int mask; | |
7707 | int xreg, yreg, zreg, tmp; | |
252b5132 RH |
7708 | expressionS expr1; |
7709 | int dbl; | |
7710 | const char *s, *s2, *s3; | |
7711 | ||
7712 | mask = ip->insn_mo->mask; | |
7713 | ||
7714 | xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; | |
7715 | yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY; | |
7716 | zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; | |
7717 | ||
252b5132 RH |
7718 | expr1.X_op = O_constant; |
7719 | expr1.X_op_symbol = NULL; | |
7720 | expr1.X_add_symbol = NULL; | |
7721 | expr1.X_add_number = 1; | |
7722 | ||
7723 | dbl = 0; | |
7724 | ||
7725 | switch (mask) | |
7726 | { | |
7727 | default: | |
7728 | internalError (); | |
7729 | ||
7730 | case M_DDIV_3: | |
7731 | dbl = 1; | |
7732 | case M_DIV_3: | |
7733 | s = "mflo"; | |
7734 | goto do_div3; | |
7735 | case M_DREM_3: | |
7736 | dbl = 1; | |
7737 | case M_REM_3: | |
7738 | s = "mfhi"; | |
7739 | do_div3: | |
b34976b6 | 7740 | mips_emit_delays (TRUE); |
252b5132 RH |
7741 | ++mips_opts.noreorder; |
7742 | mips_any_noreorder = 1; | |
67c0d1eb | 7743 | macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg); |
252b5132 | 7744 | expr1.X_add_number = 2; |
67c0d1eb RS |
7745 | macro_build (&expr1, "bnez", "x,p", yreg); |
7746 | macro_build (NULL, "break", "6", 7); | |
bdaaa2e1 | 7747 | |
252b5132 RH |
7748 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
7749 | since that causes an overflow. We should do that as well, | |
7750 | but I don't see how to do the comparisons without a temporary | |
7751 | register. */ | |
7752 | --mips_opts.noreorder; | |
67c0d1eb | 7753 | macro_build (NULL, s, "x", zreg); |
252b5132 RH |
7754 | break; |
7755 | ||
7756 | case M_DIVU_3: | |
7757 | s = "divu"; | |
7758 | s2 = "mflo"; | |
7759 | goto do_divu3; | |
7760 | case M_REMU_3: | |
7761 | s = "divu"; | |
7762 | s2 = "mfhi"; | |
7763 | goto do_divu3; | |
7764 | case M_DDIVU_3: | |
7765 | s = "ddivu"; | |
7766 | s2 = "mflo"; | |
7767 | goto do_divu3; | |
7768 | case M_DREMU_3: | |
7769 | s = "ddivu"; | |
7770 | s2 = "mfhi"; | |
7771 | do_divu3: | |
b34976b6 | 7772 | mips_emit_delays (TRUE); |
252b5132 RH |
7773 | ++mips_opts.noreorder; |
7774 | mips_any_noreorder = 1; | |
67c0d1eb | 7775 | macro_build (NULL, s, "0,x,y", xreg, yreg); |
252b5132 | 7776 | expr1.X_add_number = 2; |
67c0d1eb RS |
7777 | macro_build (&expr1, "bnez", "x,p", yreg); |
7778 | macro_build (NULL, "break", "6", 7); | |
252b5132 | 7779 | --mips_opts.noreorder; |
67c0d1eb | 7780 | macro_build (NULL, s2, "x", zreg); |
252b5132 RH |
7781 | break; |
7782 | ||
7783 | case M_DMUL: | |
7784 | dbl = 1; | |
7785 | case M_MUL: | |
67c0d1eb RS |
7786 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
7787 | macro_build (NULL, "mflo", "x", zreg); | |
252b5132 RH |
7788 | return; |
7789 | ||
7790 | case M_DSUBU_I: | |
7791 | dbl = 1; | |
7792 | goto do_subu; | |
7793 | case M_SUBU_I: | |
7794 | do_subu: | |
7795 | if (imm_expr.X_op != O_constant) | |
7796 | as_bad (_("Unsupported large constant")); | |
7797 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7798 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
7799 | break; |
7800 | ||
7801 | case M_SUBU_I_2: | |
7802 | if (imm_expr.X_op != O_constant) | |
7803 | as_bad (_("Unsupported large constant")); | |
7804 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7805 | macro_build (&imm_expr, "addiu", "x,k", xreg); |
252b5132 RH |
7806 | break; |
7807 | ||
7808 | case M_DSUBU_I_2: | |
7809 | if (imm_expr.X_op != O_constant) | |
7810 | as_bad (_("Unsupported large constant")); | |
7811 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7812 | macro_build (&imm_expr, "daddiu", "y,j", yreg); |
252b5132 RH |
7813 | break; |
7814 | ||
7815 | case M_BEQ: | |
7816 | s = "cmp"; | |
7817 | s2 = "bteqz"; | |
7818 | goto do_branch; | |
7819 | case M_BNE: | |
7820 | s = "cmp"; | |
7821 | s2 = "btnez"; | |
7822 | goto do_branch; | |
7823 | case M_BLT: | |
7824 | s = "slt"; | |
7825 | s2 = "btnez"; | |
7826 | goto do_branch; | |
7827 | case M_BLTU: | |
7828 | s = "sltu"; | |
7829 | s2 = "btnez"; | |
7830 | goto do_branch; | |
7831 | case M_BLE: | |
7832 | s = "slt"; | |
7833 | s2 = "bteqz"; | |
7834 | goto do_reverse_branch; | |
7835 | case M_BLEU: | |
7836 | s = "sltu"; | |
7837 | s2 = "bteqz"; | |
7838 | goto do_reverse_branch; | |
7839 | case M_BGE: | |
7840 | s = "slt"; | |
7841 | s2 = "bteqz"; | |
7842 | goto do_branch; | |
7843 | case M_BGEU: | |
7844 | s = "sltu"; | |
7845 | s2 = "bteqz"; | |
7846 | goto do_branch; | |
7847 | case M_BGT: | |
7848 | s = "slt"; | |
7849 | s2 = "btnez"; | |
7850 | goto do_reverse_branch; | |
7851 | case M_BGTU: | |
7852 | s = "sltu"; | |
7853 | s2 = "btnez"; | |
7854 | ||
7855 | do_reverse_branch: | |
7856 | tmp = xreg; | |
7857 | xreg = yreg; | |
7858 | yreg = tmp; | |
7859 | ||
7860 | do_branch: | |
67c0d1eb RS |
7861 | macro_build (NULL, s, "x,y", xreg, yreg); |
7862 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
7863 | break; |
7864 | ||
7865 | case M_BEQ_I: | |
7866 | s = "cmpi"; | |
7867 | s2 = "bteqz"; | |
7868 | s3 = "x,U"; | |
7869 | goto do_branch_i; | |
7870 | case M_BNE_I: | |
7871 | s = "cmpi"; | |
7872 | s2 = "btnez"; | |
7873 | s3 = "x,U"; | |
7874 | goto do_branch_i; | |
7875 | case M_BLT_I: | |
7876 | s = "slti"; | |
7877 | s2 = "btnez"; | |
7878 | s3 = "x,8"; | |
7879 | goto do_branch_i; | |
7880 | case M_BLTU_I: | |
7881 | s = "sltiu"; | |
7882 | s2 = "btnez"; | |
7883 | s3 = "x,8"; | |
7884 | goto do_branch_i; | |
7885 | case M_BLE_I: | |
7886 | s = "slti"; | |
7887 | s2 = "btnez"; | |
7888 | s3 = "x,8"; | |
7889 | goto do_addone_branch_i; | |
7890 | case M_BLEU_I: | |
7891 | s = "sltiu"; | |
7892 | s2 = "btnez"; | |
7893 | s3 = "x,8"; | |
7894 | goto do_addone_branch_i; | |
7895 | case M_BGE_I: | |
7896 | s = "slti"; | |
7897 | s2 = "bteqz"; | |
7898 | s3 = "x,8"; | |
7899 | goto do_branch_i; | |
7900 | case M_BGEU_I: | |
7901 | s = "sltiu"; | |
7902 | s2 = "bteqz"; | |
7903 | s3 = "x,8"; | |
7904 | goto do_branch_i; | |
7905 | case M_BGT_I: | |
7906 | s = "slti"; | |
7907 | s2 = "bteqz"; | |
7908 | s3 = "x,8"; | |
7909 | goto do_addone_branch_i; | |
7910 | case M_BGTU_I: | |
7911 | s = "sltiu"; | |
7912 | s2 = "bteqz"; | |
7913 | s3 = "x,8"; | |
7914 | ||
7915 | do_addone_branch_i: | |
7916 | if (imm_expr.X_op != O_constant) | |
7917 | as_bad (_("Unsupported large constant")); | |
7918 | ++imm_expr.X_add_number; | |
7919 | ||
7920 | do_branch_i: | |
67c0d1eb RS |
7921 | macro_build (&imm_expr, s, s3, xreg); |
7922 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
7923 | break; |
7924 | ||
7925 | case M_ABS: | |
7926 | expr1.X_add_number = 0; | |
67c0d1eb | 7927 | macro_build (&expr1, "slti", "x,8", yreg); |
252b5132 | 7928 | if (xreg != yreg) |
67c0d1eb | 7929 | move_register (xreg, yreg); |
252b5132 | 7930 | expr1.X_add_number = 2; |
67c0d1eb RS |
7931 | macro_build (&expr1, "bteqz", "p"); |
7932 | macro_build (NULL, "neg", "x,w", xreg, xreg); | |
252b5132 RH |
7933 | } |
7934 | } | |
7935 | ||
7936 | /* For consistency checking, verify that all bits are specified either | |
7937 | by the match/mask part of the instruction definition, or by the | |
7938 | operand list. */ | |
7939 | static int | |
17a2f251 | 7940 | validate_mips_insn (const struct mips_opcode *opc) |
252b5132 RH |
7941 | { |
7942 | const char *p = opc->args; | |
7943 | char c; | |
7944 | unsigned long used_bits = opc->mask; | |
7945 | ||
7946 | if ((used_bits & opc->match) != opc->match) | |
7947 | { | |
7948 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
7949 | opc->name, opc->args); | |
7950 | return 0; | |
7951 | } | |
7952 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
7953 | while (*p) | |
7954 | switch (c = *p++) | |
7955 | { | |
7956 | case ',': break; | |
7957 | case '(': break; | |
7958 | case ')': break; | |
af7ee8bf CD |
7959 | case '+': |
7960 | switch (c = *p++) | |
7961 | { | |
7962 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
7963 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
7964 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
bbcc0807 CD |
7965 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); |
7966 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
5f74bc13 CD |
7967 | case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
7968 | case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
7969 | case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
7970 | case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
7971 | case 'I': break; | |
af7ee8bf CD |
7972 | default: |
7973 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
7974 | c, opc->name, opc->args); | |
7975 | return 0; | |
7976 | } | |
7977 | break; | |
252b5132 RH |
7978 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
7979 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
7980 | case 'A': break; | |
4372b673 | 7981 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
7982 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
7983 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
7984 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7985 | case 'F': break; | |
7986 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 7987 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 7988 | case 'I': break; |
e972090a | 7989 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 7990 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
7991 | case 'L': break; |
7992 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
7993 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
7994 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
7995 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
7996 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
7997 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
7998 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7999 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
8000 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8001 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
8002 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
8003 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8004 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
8005 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
8006 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8007 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
8008 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
8009 | case 'f': break; | |
8010 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
8011 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
8012 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8013 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
8014 | case 'l': break; | |
8015 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8016 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8017 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
8018 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8019 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8020 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8021 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
8022 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8023 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8024 | case 'x': break; | |
8025 | case 'z': break; | |
8026 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
8027 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
8028 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
8029 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
8030 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
8031 | case '[': break; | |
8032 | case ']': break; | |
252b5132 RH |
8033 | default: |
8034 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
8035 | c, opc->name, opc->args); | |
8036 | return 0; | |
8037 | } | |
8038 | #undef USE_BITS | |
8039 | if (used_bits != 0xffffffff) | |
8040 | { | |
8041 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
8042 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
8043 | return 0; | |
8044 | } | |
8045 | return 1; | |
8046 | } | |
8047 | ||
8048 | /* This routine assembles an instruction into its binary format. As a | |
8049 | side effect, it sets one of the global variables imm_reloc or | |
8050 | offset_reloc to the type of relocation to do if one of the operands | |
8051 | is an address expression. */ | |
8052 | ||
8053 | static void | |
17a2f251 | 8054 | mips_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
8055 | { |
8056 | char *s; | |
8057 | const char *args; | |
43841e91 | 8058 | char c = 0; |
252b5132 RH |
8059 | struct mips_opcode *insn; |
8060 | char *argsStart; | |
8061 | unsigned int regno; | |
8062 | unsigned int lastregno = 0; | |
af7ee8bf | 8063 | unsigned int lastpos = 0; |
071742cf | 8064 | unsigned int limlo, limhi; |
252b5132 RH |
8065 | char *s_reset; |
8066 | char save_c = 0; | |
252b5132 RH |
8067 | |
8068 | insn_error = NULL; | |
8069 | ||
8070 | /* If the instruction contains a '.', we first try to match an instruction | |
8071 | including the '.'. Then we try again without the '.'. */ | |
8072 | insn = NULL; | |
3882b010 | 8073 | for (s = str; *s != '\0' && !ISSPACE (*s); ++s) |
252b5132 RH |
8074 | continue; |
8075 | ||
8076 | /* If we stopped on whitespace, then replace the whitespace with null for | |
8077 | the call to hash_find. Save the character we replaced just in case we | |
8078 | have to re-parse the instruction. */ | |
3882b010 | 8079 | if (ISSPACE (*s)) |
252b5132 RH |
8080 | { |
8081 | save_c = *s; | |
8082 | *s++ = '\0'; | |
8083 | } | |
bdaaa2e1 | 8084 | |
252b5132 RH |
8085 | insn = (struct mips_opcode *) hash_find (op_hash, str); |
8086 | ||
8087 | /* If we didn't find the instruction in the opcode table, try again, but | |
8088 | this time with just the instruction up to, but not including the | |
8089 | first '.'. */ | |
8090 | if (insn == NULL) | |
8091 | { | |
bdaaa2e1 | 8092 | /* Restore the character we overwrite above (if any). */ |
252b5132 RH |
8093 | if (save_c) |
8094 | *(--s) = save_c; | |
8095 | ||
8096 | /* Scan up to the first '.' or whitespace. */ | |
3882b010 L |
8097 | for (s = str; |
8098 | *s != '\0' && *s != '.' && !ISSPACE (*s); | |
8099 | ++s) | |
252b5132 RH |
8100 | continue; |
8101 | ||
8102 | /* If we did not find a '.', then we can quit now. */ | |
8103 | if (*s != '.') | |
8104 | { | |
8105 | insn_error = "unrecognized opcode"; | |
8106 | return; | |
8107 | } | |
8108 | ||
8109 | /* Lookup the instruction in the hash table. */ | |
8110 | *s++ = '\0'; | |
8111 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
8112 | { | |
8113 | insn_error = "unrecognized opcode"; | |
8114 | return; | |
8115 | } | |
252b5132 RH |
8116 | } |
8117 | ||
8118 | argsStart = s; | |
8119 | for (;;) | |
8120 | { | |
b34976b6 | 8121 | bfd_boolean ok; |
252b5132 RH |
8122 | |
8123 | assert (strcmp (insn->name, str) == 0); | |
8124 | ||
1f25f5d3 CD |
8125 | if (OPCODE_IS_MEMBER (insn, |
8126 | (mips_opts.isa | |
3396de36 | 8127 | | (file_ase_mips16 ? INSN_MIPS16 : 0) |
deec1734 | 8128 | | (mips_opts.ase_mdmx ? INSN_MDMX : 0) |
98d3f06f | 8129 | | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)), |
fef14a42 | 8130 | mips_opts.arch)) |
b34976b6 | 8131 | ok = TRUE; |
bdaaa2e1 | 8132 | else |
b34976b6 | 8133 | ok = FALSE; |
bdaaa2e1 | 8134 | |
252b5132 RH |
8135 | if (insn->pinfo != INSN_MACRO) |
8136 | { | |
fef14a42 | 8137 | if (mips_opts.arch == CPU_R4650 && (insn->pinfo & FP_D) != 0) |
b34976b6 | 8138 | ok = FALSE; |
252b5132 RH |
8139 | } |
8140 | ||
8141 | if (! ok) | |
8142 | { | |
8143 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
8144 | && strcmp (insn->name, insn[1].name) == 0) | |
8145 | { | |
8146 | ++insn; | |
8147 | continue; | |
8148 | } | |
252b5132 | 8149 | else |
beae10d5 | 8150 | { |
268f6bed L |
8151 | if (!insn_error) |
8152 | { | |
8153 | static char buf[100]; | |
fef14a42 TS |
8154 | sprintf (buf, |
8155 | _("opcode not supported on this processor: %s (%s)"), | |
8156 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
8157 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
268f6bed L |
8158 | insn_error = buf; |
8159 | } | |
8160 | if (save_c) | |
8161 | *(--s) = save_c; | |
2bd7f1f3 | 8162 | return; |
252b5132 | 8163 | } |
252b5132 RH |
8164 | } |
8165 | ||
8166 | ip->insn_mo = insn; | |
8167 | ip->insn_opcode = insn->match; | |
268f6bed | 8168 | insn_error = NULL; |
252b5132 RH |
8169 | for (args = insn->args;; ++args) |
8170 | { | |
deec1734 CD |
8171 | int is_mdmx; |
8172 | ||
ad8d3bb3 | 8173 | s += strspn (s, " \t"); |
deec1734 | 8174 | is_mdmx = 0; |
252b5132 RH |
8175 | switch (*args) |
8176 | { | |
8177 | case '\0': /* end of args */ | |
8178 | if (*s == '\0') | |
8179 | return; | |
8180 | break; | |
8181 | ||
8182 | case ',': | |
8183 | if (*s++ == *args) | |
8184 | continue; | |
8185 | s--; | |
8186 | switch (*++args) | |
8187 | { | |
8188 | case 'r': | |
8189 | case 'v': | |
38487616 | 8190 | ip->insn_opcode |= lastregno << OP_SH_RS; |
252b5132 RH |
8191 | continue; |
8192 | ||
8193 | case 'w': | |
38487616 TS |
8194 | ip->insn_opcode |= lastregno << OP_SH_RT; |
8195 | continue; | |
8196 | ||
252b5132 | 8197 | case 'W': |
38487616 | 8198 | ip->insn_opcode |= lastregno << OP_SH_FT; |
252b5132 RH |
8199 | continue; |
8200 | ||
8201 | case 'V': | |
38487616 | 8202 | ip->insn_opcode |= lastregno << OP_SH_FS; |
252b5132 RH |
8203 | continue; |
8204 | } | |
8205 | break; | |
8206 | ||
8207 | case '(': | |
8208 | /* Handle optional base register. | |
8209 | Either the base register is omitted or | |
bdaaa2e1 | 8210 | we must have a left paren. */ |
252b5132 RH |
8211 | /* This is dependent on the next operand specifier |
8212 | is a base register specification. */ | |
8213 | assert (args[1] == 'b' || args[1] == '5' | |
8214 | || args[1] == '-' || args[1] == '4'); | |
8215 | if (*s == '\0') | |
8216 | return; | |
8217 | ||
8218 | case ')': /* these must match exactly */ | |
60b63b72 RS |
8219 | case '[': |
8220 | case ']': | |
252b5132 RH |
8221 | if (*s++ == *args) |
8222 | continue; | |
8223 | break; | |
8224 | ||
af7ee8bf CD |
8225 | case '+': /* Opcode extension character. */ |
8226 | switch (*++args) | |
8227 | { | |
071742cf CD |
8228 | case 'A': /* ins/ext position, becomes LSB. */ |
8229 | limlo = 0; | |
8230 | limhi = 31; | |
5f74bc13 CD |
8231 | goto do_lsb; |
8232 | case 'E': | |
8233 | limlo = 32; | |
8234 | limhi = 63; | |
8235 | goto do_lsb; | |
8236 | do_lsb: | |
071742cf CD |
8237 | my_getExpression (&imm_expr, s); |
8238 | check_absolute_expr (ip, &imm_expr); | |
8239 | if ((unsigned long) imm_expr.X_add_number < limlo | |
8240 | || (unsigned long) imm_expr.X_add_number > limhi) | |
8241 | { | |
8242 | as_bad (_("Improper position (%lu)"), | |
8243 | (unsigned long) imm_expr.X_add_number); | |
8244 | imm_expr.X_add_number = limlo; | |
8245 | } | |
8246 | lastpos = imm_expr.X_add_number; | |
8247 | ip->insn_opcode |= (imm_expr.X_add_number | |
8248 | & OP_MASK_SHAMT) << OP_SH_SHAMT; | |
8249 | imm_expr.X_op = O_absent; | |
8250 | s = expr_end; | |
8251 | continue; | |
8252 | ||
8253 | case 'B': /* ins size, becomes MSB. */ | |
8254 | limlo = 1; | |
8255 | limhi = 32; | |
5f74bc13 CD |
8256 | goto do_msb; |
8257 | case 'F': | |
8258 | limlo = 33; | |
8259 | limhi = 64; | |
8260 | goto do_msb; | |
8261 | do_msb: | |
071742cf CD |
8262 | my_getExpression (&imm_expr, s); |
8263 | check_absolute_expr (ip, &imm_expr); | |
8264 | /* Check for negative input so that small negative numbers | |
8265 | will not succeed incorrectly. The checks against | |
8266 | (pos+size) transitively check "size" itself, | |
8267 | assuming that "pos" is reasonable. */ | |
8268 | if ((long) imm_expr.X_add_number < 0 | |
8269 | || ((unsigned long) imm_expr.X_add_number | |
8270 | + lastpos) < limlo | |
8271 | || ((unsigned long) imm_expr.X_add_number | |
8272 | + lastpos) > limhi) | |
8273 | { | |
8274 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
8275 | (unsigned long) imm_expr.X_add_number, | |
8276 | (unsigned long) lastpos); | |
8277 | imm_expr.X_add_number = limlo - lastpos; | |
8278 | } | |
8279 | ip->insn_opcode |= ((lastpos + imm_expr.X_add_number - 1) | |
8280 | & OP_MASK_INSMSB) << OP_SH_INSMSB; | |
8281 | imm_expr.X_op = O_absent; | |
8282 | s = expr_end; | |
8283 | continue; | |
8284 | ||
8285 | case 'C': /* ext size, becomes MSBD. */ | |
8286 | limlo = 1; | |
8287 | limhi = 32; | |
5f74bc13 CD |
8288 | goto do_msbd; |
8289 | case 'G': | |
8290 | limlo = 33; | |
8291 | limhi = 64; | |
8292 | goto do_msbd; | |
8293 | case 'H': | |
8294 | limlo = 33; | |
8295 | limhi = 64; | |
8296 | goto do_msbd; | |
8297 | do_msbd: | |
071742cf CD |
8298 | my_getExpression (&imm_expr, s); |
8299 | check_absolute_expr (ip, &imm_expr); | |
8300 | /* Check for negative input so that small negative numbers | |
8301 | will not succeed incorrectly. The checks against | |
8302 | (pos+size) transitively check "size" itself, | |
8303 | assuming that "pos" is reasonable. */ | |
8304 | if ((long) imm_expr.X_add_number < 0 | |
8305 | || ((unsigned long) imm_expr.X_add_number | |
8306 | + lastpos) < limlo | |
8307 | || ((unsigned long) imm_expr.X_add_number | |
8308 | + lastpos) > limhi) | |
8309 | { | |
8310 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
8311 | (unsigned long) imm_expr.X_add_number, | |
8312 | (unsigned long) lastpos); | |
8313 | imm_expr.X_add_number = limlo - lastpos; | |
8314 | } | |
8315 | ip->insn_opcode |= ((imm_expr.X_add_number - 1) | |
8316 | & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD; | |
8317 | imm_expr.X_op = O_absent; | |
8318 | s = expr_end; | |
8319 | continue; | |
af7ee8bf | 8320 | |
bbcc0807 CD |
8321 | case 'D': |
8322 | /* +D is for disassembly only; never match. */ | |
8323 | break; | |
8324 | ||
5f74bc13 CD |
8325 | case 'I': |
8326 | /* "+I" is like "I", except that imm2_expr is used. */ | |
8327 | my_getExpression (&imm2_expr, s); | |
8328 | if (imm2_expr.X_op != O_big | |
8329 | && imm2_expr.X_op != O_constant) | |
8330 | insn_error = _("absolute expression required"); | |
13757d0c | 8331 | normalize_constant_expr (&imm2_expr); |
5f74bc13 CD |
8332 | s = expr_end; |
8333 | continue; | |
8334 | ||
af7ee8bf CD |
8335 | default: |
8336 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
8337 | *args, insn->name, insn->args); | |
8338 | /* Further processing is fruitless. */ | |
8339 | return; | |
8340 | } | |
8341 | break; | |
8342 | ||
252b5132 RH |
8343 | case '<': /* must be at least one digit */ |
8344 | /* | |
8345 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
8346 | * than 31 or less than 0, then the shift amount should be |
8347 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
8348 | * We issue a warning and mask out all but the low 5 bits. |
8349 | */ | |
8350 | my_getExpression (&imm_expr, s); | |
8351 | check_absolute_expr (ip, &imm_expr); | |
8352 | if ((unsigned long) imm_expr.X_add_number > 31) | |
8353 | { | |
793b27f4 TS |
8354 | as_warn (_("Improper shift amount (%lu)"), |
8355 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8356 | imm_expr.X_add_number &= OP_MASK_SHAMT; |
252b5132 | 8357 | } |
38487616 | 8358 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT; |
252b5132 RH |
8359 | imm_expr.X_op = O_absent; |
8360 | s = expr_end; | |
8361 | continue; | |
8362 | ||
8363 | case '>': /* shift amount minus 32 */ | |
8364 | my_getExpression (&imm_expr, s); | |
8365 | check_absolute_expr (ip, &imm_expr); | |
8366 | if ((unsigned long) imm_expr.X_add_number < 32 | |
8367 | || (unsigned long) imm_expr.X_add_number > 63) | |
8368 | break; | |
38487616 | 8369 | ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT; |
252b5132 RH |
8370 | imm_expr.X_op = O_absent; |
8371 | s = expr_end; | |
8372 | continue; | |
8373 | ||
252b5132 RH |
8374 | case 'k': /* cache code */ |
8375 | case 'h': /* prefx code */ | |
8376 | my_getExpression (&imm_expr, s); | |
8377 | check_absolute_expr (ip, &imm_expr); | |
8378 | if ((unsigned long) imm_expr.X_add_number > 31) | |
8379 | { | |
8380 | as_warn (_("Invalid value for `%s' (%lu)"), | |
8381 | ip->insn_mo->name, | |
8382 | (unsigned long) imm_expr.X_add_number); | |
8383 | imm_expr.X_add_number &= 0x1f; | |
8384 | } | |
8385 | if (*args == 'k') | |
8386 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE; | |
8387 | else | |
8388 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX; | |
8389 | imm_expr.X_op = O_absent; | |
8390 | s = expr_end; | |
8391 | continue; | |
8392 | ||
8393 | case 'c': /* break code */ | |
8394 | my_getExpression (&imm_expr, s); | |
8395 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 8396 | if ((unsigned long) imm_expr.X_add_number > 1023) |
252b5132 | 8397 | { |
793b27f4 TS |
8398 | as_warn (_("Illegal break code (%lu)"), |
8399 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8400 | imm_expr.X_add_number &= OP_MASK_CODE; |
252b5132 | 8401 | } |
38487616 | 8402 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE; |
252b5132 RH |
8403 | imm_expr.X_op = O_absent; |
8404 | s = expr_end; | |
8405 | continue; | |
8406 | ||
8407 | case 'q': /* lower break code */ | |
8408 | my_getExpression (&imm_expr, s); | |
8409 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 8410 | if ((unsigned long) imm_expr.X_add_number > 1023) |
252b5132 | 8411 | { |
793b27f4 TS |
8412 | as_warn (_("Illegal lower break code (%lu)"), |
8413 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8414 | imm_expr.X_add_number &= OP_MASK_CODE2; |
252b5132 | 8415 | } |
38487616 | 8416 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2; |
252b5132 RH |
8417 | imm_expr.X_op = O_absent; |
8418 | s = expr_end; | |
8419 | continue; | |
8420 | ||
4372b673 | 8421 | case 'B': /* 20-bit syscall/break code. */ |
156c2f8b | 8422 | my_getExpression (&imm_expr, s); |
156c2f8b | 8423 | check_absolute_expr (ip, &imm_expr); |
793b27f4 TS |
8424 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20) |
8425 | as_warn (_("Illegal 20-bit code (%lu)"), | |
8426 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8427 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20; |
252b5132 RH |
8428 | imm_expr.X_op = O_absent; |
8429 | s = expr_end; | |
8430 | continue; | |
8431 | ||
98d3f06f | 8432 | case 'C': /* Coprocessor code */ |
beae10d5 | 8433 | my_getExpression (&imm_expr, s); |
252b5132 | 8434 | check_absolute_expr (ip, &imm_expr); |
98d3f06f | 8435 | if ((unsigned long) imm_expr.X_add_number >= (1 << 25)) |
252b5132 | 8436 | { |
793b27f4 TS |
8437 | as_warn (_("Coproccesor code > 25 bits (%lu)"), |
8438 | (unsigned long) imm_expr.X_add_number); | |
98d3f06f | 8439 | imm_expr.X_add_number &= ((1 << 25) - 1); |
252b5132 | 8440 | } |
beae10d5 KH |
8441 | ip->insn_opcode |= imm_expr.X_add_number; |
8442 | imm_expr.X_op = O_absent; | |
8443 | s = expr_end; | |
8444 | continue; | |
252b5132 | 8445 | |
4372b673 NC |
8446 | case 'J': /* 19-bit wait code. */ |
8447 | my_getExpression (&imm_expr, s); | |
8448 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 TS |
8449 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
8450 | as_warn (_("Illegal 19-bit code (%lu)"), | |
8451 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8452 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19; |
4372b673 NC |
8453 | imm_expr.X_op = O_absent; |
8454 | s = expr_end; | |
8455 | continue; | |
8456 | ||
252b5132 | 8457 | case 'P': /* Performance register */ |
beae10d5 | 8458 | my_getExpression (&imm_expr, s); |
252b5132 | 8459 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 8460 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
252b5132 | 8461 | { |
793b27f4 TS |
8462 | as_warn (_("Invalid performance register (%lu)"), |
8463 | (unsigned long) imm_expr.X_add_number); | |
38487616 | 8464 | imm_expr.X_add_number &= OP_MASK_PERFREG; |
252b5132 | 8465 | } |
38487616 | 8466 | ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG); |
beae10d5 KH |
8467 | imm_expr.X_op = O_absent; |
8468 | s = expr_end; | |
8469 | continue; | |
252b5132 RH |
8470 | |
8471 | case 'b': /* base register */ | |
8472 | case 'd': /* destination register */ | |
8473 | case 's': /* source register */ | |
8474 | case 't': /* target register */ | |
8475 | case 'r': /* both target and source */ | |
8476 | case 'v': /* both dest and source */ | |
8477 | case 'w': /* both dest and target */ | |
8478 | case 'E': /* coprocessor target register */ | |
8479 | case 'G': /* coprocessor destination register */ | |
af7ee8bf | 8480 | case 'K': /* 'rdhwr' destination register */ |
252b5132 RH |
8481 | case 'x': /* ignore register name */ |
8482 | case 'z': /* must be zero register */ | |
4372b673 | 8483 | case 'U': /* destination register (clo/clz). */ |
252b5132 RH |
8484 | s_reset = s; |
8485 | if (s[0] == '$') | |
8486 | { | |
8487 | ||
3882b010 | 8488 | if (ISDIGIT (s[1])) |
252b5132 RH |
8489 | { |
8490 | ++s; | |
8491 | regno = 0; | |
8492 | do | |
8493 | { | |
8494 | regno *= 10; | |
8495 | regno += *s - '0'; | |
8496 | ++s; | |
8497 | } | |
3882b010 | 8498 | while (ISDIGIT (*s)); |
252b5132 RH |
8499 | if (regno > 31) |
8500 | as_bad (_("Invalid register number (%d)"), regno); | |
8501 | } | |
af7ee8bf | 8502 | else if (*args == 'E' || *args == 'G' || *args == 'K') |
252b5132 RH |
8503 | goto notreg; |
8504 | else | |
8505 | { | |
76db943d TS |
8506 | if (s[1] == 'r' && s[2] == 'a') |
8507 | { | |
8508 | s += 3; | |
8509 | regno = RA; | |
8510 | } | |
8511 | else if (s[1] == 'f' && s[2] == 'p') | |
252b5132 RH |
8512 | { |
8513 | s += 3; | |
8514 | regno = FP; | |
8515 | } | |
8516 | else if (s[1] == 's' && s[2] == 'p') | |
8517 | { | |
8518 | s += 3; | |
8519 | regno = SP; | |
8520 | } | |
8521 | else if (s[1] == 'g' && s[2] == 'p') | |
8522 | { | |
8523 | s += 3; | |
8524 | regno = GP; | |
8525 | } | |
8526 | else if (s[1] == 'a' && s[2] == 't') | |
8527 | { | |
8528 | s += 3; | |
8529 | regno = AT; | |
8530 | } | |
8531 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
8532 | { | |
8533 | s += 4; | |
8534 | regno = KT0; | |
8535 | } | |
8536 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
8537 | { | |
8538 | s += 4; | |
8539 | regno = KT1; | |
8540 | } | |
85b51719 TS |
8541 | else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o') |
8542 | { | |
8543 | s += 5; | |
8544 | regno = ZERO; | |
8545 | } | |
252b5132 RH |
8546 | else if (itbl_have_entries) |
8547 | { | |
8548 | char *p, *n; | |
d7ba4a77 | 8549 | unsigned long r; |
252b5132 | 8550 | |
d7ba4a77 | 8551 | p = s + 1; /* advance past '$' */ |
252b5132 RH |
8552 | n = itbl_get_field (&p); /* n is name */ |
8553 | ||
d7ba4a77 ILT |
8554 | /* See if this is a register defined in an |
8555 | itbl entry. */ | |
8556 | if (itbl_get_reg_val (n, &r)) | |
252b5132 RH |
8557 | { |
8558 | /* Get_field advances to the start of | |
8559 | the next field, so we need to back | |
d7ba4a77 | 8560 | rack to the end of the last field. */ |
bdaaa2e1 | 8561 | if (p) |
252b5132 | 8562 | s = p - 1; |
bdaaa2e1 | 8563 | else |
d7ba4a77 | 8564 | s = strchr (s, '\0'); |
252b5132 RH |
8565 | regno = r; |
8566 | } | |
8567 | else | |
8568 | goto notreg; | |
beae10d5 | 8569 | } |
252b5132 RH |
8570 | else |
8571 | goto notreg; | |
8572 | } | |
8573 | if (regno == AT | |
8574 | && ! mips_opts.noat | |
8575 | && *args != 'E' | |
af7ee8bf CD |
8576 | && *args != 'G' |
8577 | && *args != 'K') | |
252b5132 RH |
8578 | as_warn (_("Used $at without \".set noat\"")); |
8579 | c = *args; | |
8580 | if (*s == ' ') | |
f9419b05 | 8581 | ++s; |
252b5132 RH |
8582 | if (args[1] != *s) |
8583 | { | |
8584 | if (c == 'r' || c == 'v' || c == 'w') | |
8585 | { | |
8586 | regno = lastregno; | |
8587 | s = s_reset; | |
f9419b05 | 8588 | ++args; |
252b5132 RH |
8589 | } |
8590 | } | |
8591 | /* 'z' only matches $0. */ | |
8592 | if (c == 'z' && regno != 0) | |
8593 | break; | |
8594 | ||
bdaaa2e1 KH |
8595 | /* Now that we have assembled one operand, we use the args string |
8596 | * to figure out where it goes in the instruction. */ | |
252b5132 RH |
8597 | switch (c) |
8598 | { | |
8599 | case 'r': | |
8600 | case 's': | |
8601 | case 'v': | |
8602 | case 'b': | |
38487616 | 8603 | ip->insn_opcode |= regno << OP_SH_RS; |
252b5132 RH |
8604 | break; |
8605 | case 'd': | |
8606 | case 'G': | |
af7ee8bf | 8607 | case 'K': |
38487616 | 8608 | ip->insn_opcode |= regno << OP_SH_RD; |
252b5132 | 8609 | break; |
4372b673 | 8610 | case 'U': |
38487616 TS |
8611 | ip->insn_opcode |= regno << OP_SH_RD; |
8612 | ip->insn_opcode |= regno << OP_SH_RT; | |
4372b673 | 8613 | break; |
252b5132 RH |
8614 | case 'w': |
8615 | case 't': | |
8616 | case 'E': | |
38487616 | 8617 | ip->insn_opcode |= regno << OP_SH_RT; |
252b5132 RH |
8618 | break; |
8619 | case 'x': | |
8620 | /* This case exists because on the r3000 trunc | |
8621 | expands into a macro which requires a gp | |
8622 | register. On the r6000 or r4000 it is | |
8623 | assembled into a single instruction which | |
8624 | ignores the register. Thus the insn version | |
8625 | is MIPS_ISA2 and uses 'x', and the macro | |
8626 | version is MIPS_ISA1 and uses 't'. */ | |
8627 | break; | |
8628 | case 'z': | |
8629 | /* This case is for the div instruction, which | |
8630 | acts differently if the destination argument | |
8631 | is $0. This only matches $0, and is checked | |
8632 | outside the switch. */ | |
8633 | break; | |
8634 | case 'D': | |
8635 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
8636 | break; | |
8637 | /* What about all other operands like 'i', which | |
8638 | can be specified in the opcode table? */ | |
8639 | } | |
8640 | lastregno = regno; | |
8641 | continue; | |
8642 | } | |
8643 | notreg: | |
8644 | switch (*args++) | |
8645 | { | |
8646 | case 'r': | |
8647 | case 'v': | |
38487616 | 8648 | ip->insn_opcode |= lastregno << OP_SH_RS; |
252b5132 RH |
8649 | continue; |
8650 | case 'w': | |
38487616 | 8651 | ip->insn_opcode |= lastregno << OP_SH_RT; |
252b5132 RH |
8652 | continue; |
8653 | } | |
8654 | break; | |
8655 | ||
deec1734 CD |
8656 | case 'O': /* MDMX alignment immediate constant. */ |
8657 | my_getExpression (&imm_expr, s); | |
8658 | check_absolute_expr (ip, &imm_expr); | |
8659 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
8660 | { | |
8661 | as_warn ("Improper align amount (%ld), using low bits", | |
8662 | (long) imm_expr.X_add_number); | |
8663 | imm_expr.X_add_number &= OP_MASK_ALN; | |
8664 | } | |
8665 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_ALN; | |
8666 | imm_expr.X_op = O_absent; | |
8667 | s = expr_end; | |
8668 | continue; | |
8669 | ||
8670 | case 'Q': /* MDMX vector, element sel, or const. */ | |
8671 | if (s[0] != '$') | |
8672 | { | |
8673 | /* MDMX Immediate. */ | |
8674 | my_getExpression (&imm_expr, s); | |
8675 | check_absolute_expr (ip, &imm_expr); | |
8676 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
8677 | { | |
8678 | as_warn (_("Invalid MDMX Immediate (%ld)"), | |
8679 | (long) imm_expr.X_add_number); | |
8680 | imm_expr.X_add_number &= OP_MASK_FT; | |
8681 | } | |
8682 | imm_expr.X_add_number &= OP_MASK_FT; | |
8683 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
8684 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
8685 | else | |
8686 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
8687 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_FT; | |
8688 | imm_expr.X_op = O_absent; | |
8689 | s = expr_end; | |
8690 | continue; | |
8691 | } | |
8692 | /* Not MDMX Immediate. Fall through. */ | |
8693 | case 'X': /* MDMX destination register. */ | |
8694 | case 'Y': /* MDMX source register. */ | |
8695 | case 'Z': /* MDMX target register. */ | |
8696 | is_mdmx = 1; | |
252b5132 RH |
8697 | case 'D': /* floating point destination register */ |
8698 | case 'S': /* floating point source register */ | |
8699 | case 'T': /* floating point target register */ | |
8700 | case 'R': /* floating point source register */ | |
8701 | case 'V': | |
8702 | case 'W': | |
8703 | s_reset = s; | |
deec1734 CD |
8704 | /* Accept $fN for FP and MDMX register numbers, and in |
8705 | addition accept $vN for MDMX register numbers. */ | |
8706 | if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2])) | |
8707 | || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v' | |
8708 | && ISDIGIT (s[2]))) | |
252b5132 RH |
8709 | { |
8710 | s += 2; | |
8711 | regno = 0; | |
8712 | do | |
8713 | { | |
8714 | regno *= 10; | |
8715 | regno += *s - '0'; | |
8716 | ++s; | |
8717 | } | |
3882b010 | 8718 | while (ISDIGIT (*s)); |
252b5132 RH |
8719 | |
8720 | if (regno > 31) | |
8721 | as_bad (_("Invalid float register number (%d)"), regno); | |
8722 | ||
8723 | if ((regno & 1) != 0 | |
ca4e0257 | 8724 | && HAVE_32BIT_FPRS |
252b5132 RH |
8725 | && ! (strcmp (str, "mtc1") == 0 |
8726 | || strcmp (str, "mfc1") == 0 | |
8727 | || strcmp (str, "lwc1") == 0 | |
8728 | || strcmp (str, "swc1") == 0 | |
8729 | || strcmp (str, "l.s") == 0 | |
8730 | || strcmp (str, "s.s") == 0)) | |
8731 | as_warn (_("Float register should be even, was %d"), | |
8732 | regno); | |
8733 | ||
8734 | c = *args; | |
8735 | if (*s == ' ') | |
f9419b05 | 8736 | ++s; |
252b5132 RH |
8737 | if (args[1] != *s) |
8738 | { | |
8739 | if (c == 'V' || c == 'W') | |
8740 | { | |
8741 | regno = lastregno; | |
8742 | s = s_reset; | |
f9419b05 | 8743 | ++args; |
252b5132 RH |
8744 | } |
8745 | } | |
8746 | switch (c) | |
8747 | { | |
8748 | case 'D': | |
deec1734 | 8749 | case 'X': |
38487616 | 8750 | ip->insn_opcode |= regno << OP_SH_FD; |
252b5132 RH |
8751 | break; |
8752 | case 'V': | |
8753 | case 'S': | |
deec1734 | 8754 | case 'Y': |
38487616 | 8755 | ip->insn_opcode |= regno << OP_SH_FS; |
252b5132 | 8756 | break; |
deec1734 CD |
8757 | case 'Q': |
8758 | /* This is like 'Z', but also needs to fix the MDMX | |
8759 | vector/scalar select bits. Note that the | |
8760 | scalar immediate case is handled above. */ | |
8761 | if (*s == '[') | |
8762 | { | |
8763 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
8764 | int max_el = (is_qh ? 3 : 7); | |
8765 | s++; | |
8766 | my_getExpression(&imm_expr, s); | |
8767 | check_absolute_expr (ip, &imm_expr); | |
8768 | s = expr_end; | |
8769 | if (imm_expr.X_add_number > max_el) | |
8770 | as_bad(_("Bad element selector %ld"), | |
8771 | (long) imm_expr.X_add_number); | |
8772 | imm_expr.X_add_number &= max_el; | |
8773 | ip->insn_opcode |= (imm_expr.X_add_number | |
8774 | << (OP_SH_VSEL + | |
8775 | (is_qh ? 2 : 1))); | |
8776 | if (*s != ']') | |
8777 | as_warn(_("Expecting ']' found '%s'"), s); | |
8778 | else | |
8779 | s++; | |
8780 | } | |
8781 | else | |
8782 | { | |
8783 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
8784 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
8785 | << OP_SH_VSEL); | |
8786 | else | |
8787 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
8788 | OP_SH_VSEL); | |
8789 | } | |
8790 | /* Fall through */ | |
252b5132 RH |
8791 | case 'W': |
8792 | case 'T': | |
deec1734 | 8793 | case 'Z': |
38487616 | 8794 | ip->insn_opcode |= regno << OP_SH_FT; |
252b5132 RH |
8795 | break; |
8796 | case 'R': | |
38487616 | 8797 | ip->insn_opcode |= regno << OP_SH_FR; |
252b5132 RH |
8798 | break; |
8799 | } | |
8800 | lastregno = regno; | |
8801 | continue; | |
8802 | } | |
8803 | ||
252b5132 RH |
8804 | switch (*args++) |
8805 | { | |
8806 | case 'V': | |
38487616 | 8807 | ip->insn_opcode |= lastregno << OP_SH_FS; |
252b5132 RH |
8808 | continue; |
8809 | case 'W': | |
38487616 | 8810 | ip->insn_opcode |= lastregno << OP_SH_FT; |
252b5132 RH |
8811 | continue; |
8812 | } | |
8813 | break; | |
8814 | ||
8815 | case 'I': | |
8816 | my_getExpression (&imm_expr, s); | |
8817 | if (imm_expr.X_op != O_big | |
8818 | && imm_expr.X_op != O_constant) | |
8819 | insn_error = _("absolute expression required"); | |
13757d0c | 8820 | normalize_constant_expr (&imm_expr); |
252b5132 RH |
8821 | s = expr_end; |
8822 | continue; | |
8823 | ||
8824 | case 'A': | |
8825 | my_getExpression (&offset_expr, s); | |
f6688943 | 8826 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
8827 | s = expr_end; |
8828 | continue; | |
8829 | ||
8830 | case 'F': | |
8831 | case 'L': | |
8832 | case 'f': | |
8833 | case 'l': | |
8834 | { | |
8835 | int f64; | |
ca4e0257 | 8836 | int using_gprs; |
252b5132 RH |
8837 | char *save_in; |
8838 | char *err; | |
8839 | unsigned char temp[8]; | |
8840 | int len; | |
8841 | unsigned int length; | |
8842 | segT seg; | |
8843 | subsegT subseg; | |
8844 | char *p; | |
8845 | ||
8846 | /* These only appear as the last operand in an | |
8847 | instruction, and every instruction that accepts | |
8848 | them in any variant accepts them in all variants. | |
8849 | This means we don't have to worry about backing out | |
8850 | any changes if the instruction does not match. | |
8851 | ||
8852 | The difference between them is the size of the | |
8853 | floating point constant and where it goes. For 'F' | |
8854 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
8855 | is 32 bits. Where the constant is placed is based | |
8856 | on how the MIPS assembler does things: | |
8857 | F -- .rdata | |
8858 | L -- .lit8 | |
8859 | f -- immediate value | |
8860 | l -- .lit4 | |
8861 | ||
8862 | The .lit4 and .lit8 sections are only used if | |
8863 | permitted by the -G argument. | |
8864 | ||
8865 | When generating embedded PIC code, we use the | |
8866 | .lit8 section but not the .lit4 section (we can do | |
8867 | .lit4 inline easily; we need to put .lit8 | |
8868 | somewhere in the data segment, and using .lit8 | |
8869 | permits the linker to eventually combine identical | |
ca4e0257 RS |
8870 | .lit8 entries). |
8871 | ||
8872 | The code below needs to know whether the target register | |
8873 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
8874 | 'F' are used with GPR-based instructions and 'l' and | |
8875 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
8876 | |
8877 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 8878 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
8879 | |
8880 | save_in = input_line_pointer; | |
8881 | input_line_pointer = s; | |
8882 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
8883 | length = len; | |
8884 | s = input_line_pointer; | |
8885 | input_line_pointer = save_in; | |
8886 | if (err != NULL && *err != '\0') | |
8887 | { | |
8888 | as_bad (_("Bad floating point constant: %s"), err); | |
8889 | memset (temp, '\0', sizeof temp); | |
8890 | length = f64 ? 8 : 4; | |
8891 | } | |
8892 | ||
156c2f8b | 8893 | assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
8894 | |
8895 | if (*args == 'f' | |
8896 | || (*args == 'l' | |
8897 | && (! USE_GLOBAL_POINTER_OPT | |
8898 | || mips_pic == EMBEDDED_PIC | |
8899 | || g_switch_value < 4 | |
8900 | || (temp[0] == 0 && temp[1] == 0) | |
8901 | || (temp[2] == 0 && temp[3] == 0)))) | |
8902 | { | |
8903 | imm_expr.X_op = O_constant; | |
8904 | if (! target_big_endian) | |
8905 | imm_expr.X_add_number = bfd_getl32 (temp); | |
8906 | else | |
8907 | imm_expr.X_add_number = bfd_getb32 (temp); | |
8908 | } | |
8909 | else if (length > 4 | |
119d663a | 8910 | && ! mips_disable_float_construction |
ca4e0257 RS |
8911 | /* Constants can only be constructed in GPRs and |
8912 | copied to FPRs if the GPRs are at least as wide | |
8913 | as the FPRs. Force the constant into memory if | |
8914 | we are using 64-bit FPRs but the GPRs are only | |
8915 | 32 bits wide. */ | |
8916 | && (using_gprs | |
8917 | || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) | |
252b5132 RH |
8918 | && ((temp[0] == 0 && temp[1] == 0) |
8919 | || (temp[2] == 0 && temp[3] == 0)) | |
8920 | && ((temp[4] == 0 && temp[5] == 0) | |
8921 | || (temp[6] == 0 && temp[7] == 0))) | |
8922 | { | |
ca4e0257 RS |
8923 | /* The value is simple enough to load with a couple of |
8924 | instructions. If using 32-bit registers, set | |
8925 | imm_expr to the high order 32 bits and offset_expr to | |
8926 | the low order 32 bits. Otherwise, set imm_expr to | |
8927 | the entire 64 bit constant. */ | |
8928 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) | |
252b5132 RH |
8929 | { |
8930 | imm_expr.X_op = O_constant; | |
8931 | offset_expr.X_op = O_constant; | |
8932 | if (! target_big_endian) | |
8933 | { | |
8934 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
8935 | offset_expr.X_add_number = bfd_getl32 (temp); | |
8936 | } | |
8937 | else | |
8938 | { | |
8939 | imm_expr.X_add_number = bfd_getb32 (temp); | |
8940 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
8941 | } | |
8942 | if (offset_expr.X_add_number == 0) | |
8943 | offset_expr.X_op = O_absent; | |
8944 | } | |
8945 | else if (sizeof (imm_expr.X_add_number) > 4) | |
8946 | { | |
8947 | imm_expr.X_op = O_constant; | |
8948 | if (! target_big_endian) | |
8949 | imm_expr.X_add_number = bfd_getl64 (temp); | |
8950 | else | |
8951 | imm_expr.X_add_number = bfd_getb64 (temp); | |
8952 | } | |
8953 | else | |
8954 | { | |
8955 | imm_expr.X_op = O_big; | |
8956 | imm_expr.X_add_number = 4; | |
8957 | if (! target_big_endian) | |
8958 | { | |
8959 | generic_bignum[0] = bfd_getl16 (temp); | |
8960 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
8961 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
8962 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
8963 | } | |
8964 | else | |
8965 | { | |
8966 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
8967 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
8968 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
8969 | generic_bignum[3] = bfd_getb16 (temp); | |
8970 | } | |
8971 | } | |
8972 | } | |
8973 | else | |
8974 | { | |
8975 | const char *newname; | |
8976 | segT new_seg; | |
8977 | ||
8978 | /* Switch to the right section. */ | |
8979 | seg = now_seg; | |
8980 | subseg = now_subseg; | |
8981 | switch (*args) | |
8982 | { | |
8983 | default: /* unused default case avoids warnings. */ | |
8984 | case 'L': | |
8985 | newname = RDATA_SECTION_NAME; | |
bb2d6cd7 GK |
8986 | if ((USE_GLOBAL_POINTER_OPT && g_switch_value >= 8) |
8987 | || mips_pic == EMBEDDED_PIC) | |
252b5132 RH |
8988 | newname = ".lit8"; |
8989 | break; | |
8990 | case 'F': | |
bb2d6cd7 GK |
8991 | if (mips_pic == EMBEDDED_PIC) |
8992 | newname = ".lit8"; | |
8993 | else | |
8994 | newname = RDATA_SECTION_NAME; | |
252b5132 RH |
8995 | break; |
8996 | case 'l': | |
8997 | assert (!USE_GLOBAL_POINTER_OPT | |
8998 | || g_switch_value >= 4); | |
8999 | newname = ".lit4"; | |
9000 | break; | |
9001 | } | |
9002 | new_seg = subseg_new (newname, (subsegT) 0); | |
9003 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
9004 | bfd_set_section_flags (stdoutput, new_seg, | |
9005 | (SEC_ALLOC | |
9006 | | SEC_LOAD | |
9007 | | SEC_READONLY | |
9008 | | SEC_DATA)); | |
9009 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
9010 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
9011 | && strcmp (TARGET_OS, "elf") != 0) | |
9012 | record_alignment (new_seg, 4); | |
9013 | else | |
9014 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
9015 | if (seg == now_seg) | |
9016 | as_bad (_("Can't use floating point insn in this section")); | |
9017 | ||
9018 | /* Set the argument to the current address in the | |
9019 | section. */ | |
9020 | offset_expr.X_op = O_symbol; | |
9021 | offset_expr.X_add_symbol = | |
9022 | symbol_new ("L0\001", now_seg, | |
9023 | (valueT) frag_now_fix (), frag_now); | |
9024 | offset_expr.X_add_number = 0; | |
9025 | ||
9026 | /* Put the floating point number into the section. */ | |
9027 | p = frag_more ((int) length); | |
9028 | memcpy (p, temp, length); | |
9029 | ||
9030 | /* Switch back to the original section. */ | |
9031 | subseg_set (seg, subseg); | |
9032 | } | |
9033 | } | |
9034 | continue; | |
9035 | ||
9036 | case 'i': /* 16 bit unsigned immediate */ | |
9037 | case 'j': /* 16 bit signed immediate */ | |
f6688943 | 9038 | *imm_reloc = BFD_RELOC_LO16; |
5e0116d5 | 9039 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) |
252b5132 RH |
9040 | { |
9041 | int more; | |
5e0116d5 RS |
9042 | offsetT minval, maxval; |
9043 | ||
9044 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] | |
9045 | && strcmp (insn->name, insn[1].name) == 0); | |
9046 | ||
9047 | /* If the expression was written as an unsigned number, | |
9048 | only treat it as signed if there are no more | |
9049 | alternatives. */ | |
9050 | if (more | |
9051 | && *args == 'j' | |
9052 | && sizeof (imm_expr.X_add_number) <= 4 | |
9053 | && imm_expr.X_op == O_constant | |
9054 | && imm_expr.X_add_number < 0 | |
9055 | && imm_expr.X_unsigned | |
9056 | && HAVE_64BIT_GPRS) | |
9057 | break; | |
9058 | ||
9059 | /* For compatibility with older assemblers, we accept | |
9060 | 0x8000-0xffff as signed 16-bit numbers when only | |
9061 | signed numbers are allowed. */ | |
9062 | if (*args == 'i') | |
9063 | minval = 0, maxval = 0xffff; | |
9064 | else if (more) | |
9065 | minval = -0x8000, maxval = 0x7fff; | |
252b5132 | 9066 | else |
5e0116d5 RS |
9067 | minval = -0x8000, maxval = 0xffff; |
9068 | ||
9069 | if (imm_expr.X_op != O_constant | |
9070 | || imm_expr.X_add_number < minval | |
9071 | || imm_expr.X_add_number > maxval) | |
252b5132 RH |
9072 | { |
9073 | if (more) | |
9074 | break; | |
2ae7e77b AH |
9075 | if (imm_expr.X_op == O_constant |
9076 | || imm_expr.X_op == O_big) | |
5e0116d5 | 9077 | as_bad (_("expression out of range")); |
252b5132 RH |
9078 | } |
9079 | } | |
9080 | s = expr_end; | |
9081 | continue; | |
9082 | ||
9083 | case 'o': /* 16 bit offset */ | |
5e0116d5 RS |
9084 | /* Check whether there is only a single bracketed expression |
9085 | left. If so, it must be the base register and the | |
9086 | constant must be zero. */ | |
9087 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
9088 | { | |
9089 | offset_expr.X_op = O_constant; | |
9090 | offset_expr.X_add_number = 0; | |
9091 | continue; | |
9092 | } | |
252b5132 RH |
9093 | |
9094 | /* If this value won't fit into a 16 bit offset, then go | |
9095 | find a macro that will generate the 32 bit offset | |
afdbd6d0 | 9096 | code pattern. */ |
5e0116d5 | 9097 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 |
252b5132 RH |
9098 | && (offset_expr.X_op != O_constant |
9099 | || offset_expr.X_add_number >= 0x8000 | |
afdbd6d0 | 9100 | || offset_expr.X_add_number < -0x8000)) |
252b5132 RH |
9101 | break; |
9102 | ||
252b5132 RH |
9103 | s = expr_end; |
9104 | continue; | |
9105 | ||
9106 | case 'p': /* pc relative offset */ | |
0b25d3e6 | 9107 | *offset_reloc = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
9108 | my_getExpression (&offset_expr, s); |
9109 | s = expr_end; | |
9110 | continue; | |
9111 | ||
9112 | case 'u': /* upper 16 bits */ | |
5e0116d5 RS |
9113 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 |
9114 | && imm_expr.X_op == O_constant | |
9115 | && (imm_expr.X_add_number < 0 | |
9116 | || imm_expr.X_add_number >= 0x10000)) | |
252b5132 RH |
9117 | as_bad (_("lui expression not in range 0..65535")); |
9118 | s = expr_end; | |
9119 | continue; | |
9120 | ||
9121 | case 'a': /* 26 bit address */ | |
9122 | my_getExpression (&offset_expr, s); | |
9123 | s = expr_end; | |
f6688943 | 9124 | *offset_reloc = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
9125 | continue; |
9126 | ||
9127 | case 'N': /* 3 bit branch condition code */ | |
9128 | case 'M': /* 3 bit compare condition code */ | |
9129 | if (strncmp (s, "$fcc", 4) != 0) | |
9130 | break; | |
9131 | s += 4; | |
9132 | regno = 0; | |
9133 | do | |
9134 | { | |
9135 | regno *= 10; | |
9136 | regno += *s - '0'; | |
9137 | ++s; | |
9138 | } | |
3882b010 | 9139 | while (ISDIGIT (*s)); |
252b5132 | 9140 | if (regno > 7) |
30c378fd CD |
9141 | as_bad (_("Invalid condition code register $fcc%d"), regno); |
9142 | if ((strcmp(str + strlen(str) - 3, ".ps") == 0 | |
9143 | || strcmp(str + strlen(str) - 5, "any2f") == 0 | |
9144 | || strcmp(str + strlen(str) - 5, "any2t") == 0) | |
9145 | && (regno & 1) != 0) | |
9146 | as_warn(_("Condition code register should be even for %s, was %d"), | |
9147 | str, regno); | |
9148 | if ((strcmp(str + strlen(str) - 5, "any4f") == 0 | |
9149 | || strcmp(str + strlen(str) - 5, "any4t") == 0) | |
9150 | && (regno & 3) != 0) | |
9151 | as_warn(_("Condition code register should be 0 or 4 for %s, was %d"), | |
9152 | str, regno); | |
252b5132 RH |
9153 | if (*args == 'N') |
9154 | ip->insn_opcode |= regno << OP_SH_BCC; | |
9155 | else | |
9156 | ip->insn_opcode |= regno << OP_SH_CCC; | |
beae10d5 | 9157 | continue; |
252b5132 | 9158 | |
156c2f8b NC |
9159 | case 'H': |
9160 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
9161 | s += 2; | |
3882b010 | 9162 | if (ISDIGIT (*s)) |
156c2f8b NC |
9163 | { |
9164 | c = 0; | |
9165 | do | |
9166 | { | |
9167 | c *= 10; | |
9168 | c += *s - '0'; | |
9169 | ++s; | |
9170 | } | |
3882b010 | 9171 | while (ISDIGIT (*s)); |
156c2f8b NC |
9172 | } |
9173 | else | |
9174 | c = 8; /* Invalid sel value. */ | |
9175 | ||
9176 | if (c > 7) | |
9177 | as_bad (_("invalid coprocessor sub-selection value (0-7)")); | |
9178 | ip->insn_opcode |= c; | |
9179 | continue; | |
9180 | ||
60b63b72 RS |
9181 | case 'e': |
9182 | /* Must be at least one digit. */ | |
9183 | my_getExpression (&imm_expr, s); | |
9184 | check_absolute_expr (ip, &imm_expr); | |
9185 | ||
9186 | if ((unsigned long) imm_expr.X_add_number | |
9187 | > (unsigned long) OP_MASK_VECBYTE) | |
9188 | { | |
9189 | as_bad (_("bad byte vector index (%ld)"), | |
9190 | (long) imm_expr.X_add_number); | |
9191 | imm_expr.X_add_number = 0; | |
9192 | } | |
9193 | ||
9194 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECBYTE; | |
9195 | imm_expr.X_op = O_absent; | |
9196 | s = expr_end; | |
9197 | continue; | |
9198 | ||
9199 | case '%': | |
9200 | my_getExpression (&imm_expr, s); | |
9201 | check_absolute_expr (ip, &imm_expr); | |
9202 | ||
9203 | if ((unsigned long) imm_expr.X_add_number | |
9204 | > (unsigned long) OP_MASK_VECALIGN) | |
9205 | { | |
9206 | as_bad (_("bad byte vector index (%ld)"), | |
9207 | (long) imm_expr.X_add_number); | |
9208 | imm_expr.X_add_number = 0; | |
9209 | } | |
9210 | ||
9211 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECALIGN; | |
9212 | imm_expr.X_op = O_absent; | |
9213 | s = expr_end; | |
9214 | continue; | |
9215 | ||
252b5132 RH |
9216 | default: |
9217 | as_bad (_("bad char = '%c'\n"), *args); | |
9218 | internalError (); | |
9219 | } | |
9220 | break; | |
9221 | } | |
9222 | /* Args don't match. */ | |
9223 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
9224 | !strcmp (insn->name, insn[1].name)) | |
9225 | { | |
9226 | ++insn; | |
9227 | s = argsStart; | |
268f6bed | 9228 | insn_error = _("illegal operands"); |
252b5132 RH |
9229 | continue; |
9230 | } | |
268f6bed L |
9231 | if (save_c) |
9232 | *(--s) = save_c; | |
252b5132 RH |
9233 | insn_error = _("illegal operands"); |
9234 | return; | |
9235 | } | |
9236 | } | |
9237 | ||
9238 | /* This routine assembles an instruction into its binary format when | |
9239 | assembling for the mips16. As a side effect, it sets one of the | |
9240 | global variables imm_reloc or offset_reloc to the type of | |
9241 | relocation to do if one of the operands is an address expression. | |
9242 | It also sets mips16_small and mips16_ext if the user explicitly | |
9243 | requested a small or extended instruction. */ | |
9244 | ||
9245 | static void | |
17a2f251 | 9246 | mips16_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
9247 | { |
9248 | char *s; | |
9249 | const char *args; | |
9250 | struct mips_opcode *insn; | |
9251 | char *argsstart; | |
9252 | unsigned int regno; | |
9253 | unsigned int lastregno = 0; | |
9254 | char *s_reset; | |
9255 | ||
9256 | insn_error = NULL; | |
9257 | ||
b34976b6 AM |
9258 | mips16_small = FALSE; |
9259 | mips16_ext = FALSE; | |
252b5132 | 9260 | |
3882b010 | 9261 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
9262 | ; |
9263 | switch (*s) | |
9264 | { | |
9265 | case '\0': | |
9266 | break; | |
9267 | ||
9268 | case ' ': | |
9269 | *s++ = '\0'; | |
9270 | break; | |
9271 | ||
9272 | case '.': | |
9273 | if (s[1] == 't' && s[2] == ' ') | |
9274 | { | |
9275 | *s = '\0'; | |
b34976b6 | 9276 | mips16_small = TRUE; |
252b5132 RH |
9277 | s += 3; |
9278 | break; | |
9279 | } | |
9280 | else if (s[1] == 'e' && s[2] == ' ') | |
9281 | { | |
9282 | *s = '\0'; | |
b34976b6 | 9283 | mips16_ext = TRUE; |
252b5132 RH |
9284 | s += 3; |
9285 | break; | |
9286 | } | |
9287 | /* Fall through. */ | |
9288 | default: | |
9289 | insn_error = _("unknown opcode"); | |
9290 | return; | |
9291 | } | |
9292 | ||
9293 | if (mips_opts.noautoextend && ! mips16_ext) | |
b34976b6 | 9294 | mips16_small = TRUE; |
252b5132 RH |
9295 | |
9296 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
9297 | { | |
9298 | insn_error = _("unrecognized opcode"); | |
9299 | return; | |
9300 | } | |
9301 | ||
9302 | argsstart = s; | |
9303 | for (;;) | |
9304 | { | |
9305 | assert (strcmp (insn->name, str) == 0); | |
9306 | ||
9307 | ip->insn_mo = insn; | |
9308 | ip->insn_opcode = insn->match; | |
b34976b6 | 9309 | ip->use_extend = FALSE; |
252b5132 | 9310 | imm_expr.X_op = O_absent; |
f6688943 TS |
9311 | imm_reloc[0] = BFD_RELOC_UNUSED; |
9312 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
9313 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
5f74bc13 | 9314 | imm2_expr.X_op = O_absent; |
252b5132 | 9315 | offset_expr.X_op = O_absent; |
f6688943 TS |
9316 | offset_reloc[0] = BFD_RELOC_UNUSED; |
9317 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
9318 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
9319 | for (args = insn->args; 1; ++args) |
9320 | { | |
9321 | int c; | |
9322 | ||
9323 | if (*s == ' ') | |
9324 | ++s; | |
9325 | ||
9326 | /* In this switch statement we call break if we did not find | |
9327 | a match, continue if we did find a match, or return if we | |
9328 | are done. */ | |
9329 | ||
9330 | c = *args; | |
9331 | switch (c) | |
9332 | { | |
9333 | case '\0': | |
9334 | if (*s == '\0') | |
9335 | { | |
9336 | /* Stuff the immediate value in now, if we can. */ | |
9337 | if (imm_expr.X_op == O_constant | |
f6688943 | 9338 | && *imm_reloc > BFD_RELOC_UNUSED |
252b5132 RH |
9339 | && insn->pinfo != INSN_MACRO) |
9340 | { | |
c4e7957c | 9341 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
b34976b6 | 9342 | imm_expr.X_add_number, TRUE, mips16_small, |
252b5132 RH |
9343 | mips16_ext, &ip->insn_opcode, |
9344 | &ip->use_extend, &ip->extend); | |
9345 | imm_expr.X_op = O_absent; | |
f6688943 | 9346 | *imm_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
9347 | } |
9348 | ||
9349 | return; | |
9350 | } | |
9351 | break; | |
9352 | ||
9353 | case ',': | |
9354 | if (*s++ == c) | |
9355 | continue; | |
9356 | s--; | |
9357 | switch (*++args) | |
9358 | { | |
9359 | case 'v': | |
9360 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
9361 | continue; | |
9362 | case 'w': | |
9363 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
9364 | continue; | |
9365 | } | |
9366 | break; | |
9367 | ||
9368 | case '(': | |
9369 | case ')': | |
9370 | if (*s++ == c) | |
9371 | continue; | |
9372 | break; | |
9373 | ||
9374 | case 'v': | |
9375 | case 'w': | |
9376 | if (s[0] != '$') | |
9377 | { | |
9378 | if (c == 'v') | |
9379 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
9380 | else | |
9381 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
9382 | ++args; | |
9383 | continue; | |
9384 | } | |
9385 | /* Fall through. */ | |
9386 | case 'x': | |
9387 | case 'y': | |
9388 | case 'z': | |
9389 | case 'Z': | |
9390 | case '0': | |
9391 | case 'S': | |
9392 | case 'R': | |
9393 | case 'X': | |
9394 | case 'Y': | |
9395 | if (s[0] != '$') | |
9396 | break; | |
9397 | s_reset = s; | |
3882b010 | 9398 | if (ISDIGIT (s[1])) |
252b5132 RH |
9399 | { |
9400 | ++s; | |
9401 | regno = 0; | |
9402 | do | |
9403 | { | |
9404 | regno *= 10; | |
9405 | regno += *s - '0'; | |
9406 | ++s; | |
9407 | } | |
3882b010 | 9408 | while (ISDIGIT (*s)); |
252b5132 RH |
9409 | if (regno > 31) |
9410 | { | |
9411 | as_bad (_("invalid register number (%d)"), regno); | |
9412 | regno = 2; | |
9413 | } | |
9414 | } | |
9415 | else | |
9416 | { | |
76db943d TS |
9417 | if (s[1] == 'r' && s[2] == 'a') |
9418 | { | |
9419 | s += 3; | |
9420 | regno = RA; | |
9421 | } | |
9422 | else if (s[1] == 'f' && s[2] == 'p') | |
252b5132 RH |
9423 | { |
9424 | s += 3; | |
9425 | regno = FP; | |
9426 | } | |
9427 | else if (s[1] == 's' && s[2] == 'p') | |
9428 | { | |
9429 | s += 3; | |
9430 | regno = SP; | |
9431 | } | |
9432 | else if (s[1] == 'g' && s[2] == 'p') | |
9433 | { | |
9434 | s += 3; | |
9435 | regno = GP; | |
9436 | } | |
9437 | else if (s[1] == 'a' && s[2] == 't') | |
9438 | { | |
9439 | s += 3; | |
9440 | regno = AT; | |
9441 | } | |
9442 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
9443 | { | |
9444 | s += 4; | |
9445 | regno = KT0; | |
9446 | } | |
9447 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
9448 | { | |
9449 | s += 4; | |
9450 | regno = KT1; | |
9451 | } | |
85b51719 TS |
9452 | else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o') |
9453 | { | |
9454 | s += 5; | |
9455 | regno = ZERO; | |
9456 | } | |
252b5132 RH |
9457 | else |
9458 | break; | |
9459 | } | |
9460 | ||
9461 | if (*s == ' ') | |
9462 | ++s; | |
9463 | if (args[1] != *s) | |
9464 | { | |
9465 | if (c == 'v' || c == 'w') | |
9466 | { | |
9467 | regno = mips16_to_32_reg_map[lastregno]; | |
9468 | s = s_reset; | |
f9419b05 | 9469 | ++args; |
252b5132 RH |
9470 | } |
9471 | } | |
9472 | ||
9473 | switch (c) | |
9474 | { | |
9475 | case 'x': | |
9476 | case 'y': | |
9477 | case 'z': | |
9478 | case 'v': | |
9479 | case 'w': | |
9480 | case 'Z': | |
9481 | regno = mips32_to_16_reg_map[regno]; | |
9482 | break; | |
9483 | ||
9484 | case '0': | |
9485 | if (regno != 0) | |
9486 | regno = ILLEGAL_REG; | |
9487 | break; | |
9488 | ||
9489 | case 'S': | |
9490 | if (regno != SP) | |
9491 | regno = ILLEGAL_REG; | |
9492 | break; | |
9493 | ||
9494 | case 'R': | |
9495 | if (regno != RA) | |
9496 | regno = ILLEGAL_REG; | |
9497 | break; | |
9498 | ||
9499 | case 'X': | |
9500 | case 'Y': | |
9501 | if (regno == AT && ! mips_opts.noat) | |
9502 | as_warn (_("used $at without \".set noat\"")); | |
9503 | break; | |
9504 | ||
9505 | default: | |
9506 | internalError (); | |
9507 | } | |
9508 | ||
9509 | if (regno == ILLEGAL_REG) | |
9510 | break; | |
9511 | ||
9512 | switch (c) | |
9513 | { | |
9514 | case 'x': | |
9515 | case 'v': | |
9516 | ip->insn_opcode |= regno << MIPS16OP_SH_RX; | |
9517 | break; | |
9518 | case 'y': | |
9519 | case 'w': | |
9520 | ip->insn_opcode |= regno << MIPS16OP_SH_RY; | |
9521 | break; | |
9522 | case 'z': | |
9523 | ip->insn_opcode |= regno << MIPS16OP_SH_RZ; | |
9524 | break; | |
9525 | case 'Z': | |
9526 | ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z; | |
9527 | case '0': | |
9528 | case 'S': | |
9529 | case 'R': | |
9530 | break; | |
9531 | case 'X': | |
9532 | ip->insn_opcode |= regno << MIPS16OP_SH_REGR32; | |
9533 | break; | |
9534 | case 'Y': | |
9535 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
9536 | ip->insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
9537 | break; | |
9538 | default: | |
9539 | internalError (); | |
9540 | } | |
9541 | ||
9542 | lastregno = regno; | |
9543 | continue; | |
9544 | ||
9545 | case 'P': | |
9546 | if (strncmp (s, "$pc", 3) == 0) | |
9547 | { | |
9548 | s += 3; | |
9549 | continue; | |
9550 | } | |
9551 | break; | |
9552 | ||
9553 | case '<': | |
9554 | case '>': | |
9555 | case '[': | |
9556 | case ']': | |
9557 | case '4': | |
9558 | case '5': | |
9559 | case 'H': | |
9560 | case 'W': | |
9561 | case 'D': | |
9562 | case 'j': | |
9563 | case '8': | |
9564 | case 'V': | |
9565 | case 'C': | |
9566 | case 'U': | |
9567 | case 'k': | |
9568 | case 'K': | |
9569 | if (s[0] == '%' | |
9570 | && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0) | |
9571 | { | |
9572 | /* This is %gprel(SYMBOL). We need to read SYMBOL, | |
9573 | and generate the appropriate reloc. If the text | |
9574 | inside %gprel is not a symbol name with an | |
9575 | optional offset, then we generate a normal reloc | |
9576 | and will probably fail later. */ | |
9577 | my_getExpression (&imm_expr, s + sizeof "%gprel" - 1); | |
9578 | if (imm_expr.X_op == O_symbol) | |
9579 | { | |
b34976b6 | 9580 | mips16_ext = TRUE; |
f6688943 | 9581 | *imm_reloc = BFD_RELOC_MIPS16_GPREL; |
252b5132 | 9582 | s = expr_end; |
b34976b6 | 9583 | ip->use_extend = TRUE; |
252b5132 RH |
9584 | ip->extend = 0; |
9585 | continue; | |
9586 | } | |
9587 | } | |
9588 | else | |
9589 | { | |
9590 | /* Just pick up a normal expression. */ | |
9591 | my_getExpression (&imm_expr, s); | |
9592 | } | |
9593 | ||
9594 | if (imm_expr.X_op == O_register) | |
9595 | { | |
9596 | /* What we thought was an expression turned out to | |
9597 | be a register. */ | |
9598 | ||
9599 | if (s[0] == '(' && args[1] == '(') | |
9600 | { | |
9601 | /* It looks like the expression was omitted | |
9602 | before a register indirection, which means | |
9603 | that the expression is implicitly zero. We | |
9604 | still set up imm_expr, so that we handle | |
9605 | explicit extensions correctly. */ | |
9606 | imm_expr.X_op = O_constant; | |
9607 | imm_expr.X_add_number = 0; | |
f6688943 | 9608 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9609 | continue; |
9610 | } | |
9611 | ||
9612 | break; | |
9613 | } | |
9614 | ||
9615 | /* We need to relax this instruction. */ | |
f6688943 | 9616 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9617 | s = expr_end; |
9618 | continue; | |
9619 | ||
9620 | case 'p': | |
9621 | case 'q': | |
9622 | case 'A': | |
9623 | case 'B': | |
9624 | case 'E': | |
9625 | /* We use offset_reloc rather than imm_reloc for the PC | |
9626 | relative operands. This lets macros with both | |
9627 | immediate and address operands work correctly. */ | |
9628 | my_getExpression (&offset_expr, s); | |
9629 | ||
9630 | if (offset_expr.X_op == O_register) | |
9631 | break; | |
9632 | ||
9633 | /* We need to relax this instruction. */ | |
f6688943 | 9634 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9635 | s = expr_end; |
9636 | continue; | |
9637 | ||
9638 | case '6': /* break code */ | |
9639 | my_getExpression (&imm_expr, s); | |
9640 | check_absolute_expr (ip, &imm_expr); | |
9641 | if ((unsigned long) imm_expr.X_add_number > 63) | |
9642 | { | |
9643 | as_warn (_("Invalid value for `%s' (%lu)"), | |
9644 | ip->insn_mo->name, | |
9645 | (unsigned long) imm_expr.X_add_number); | |
9646 | imm_expr.X_add_number &= 0x3f; | |
9647 | } | |
9648 | ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6; | |
9649 | imm_expr.X_op = O_absent; | |
9650 | s = expr_end; | |
9651 | continue; | |
9652 | ||
9653 | case 'a': /* 26 bit address */ | |
9654 | my_getExpression (&offset_expr, s); | |
9655 | s = expr_end; | |
f6688943 | 9656 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
9657 | ip->insn_opcode <<= 16; |
9658 | continue; | |
9659 | ||
9660 | case 'l': /* register list for entry macro */ | |
9661 | case 'L': /* register list for exit macro */ | |
9662 | { | |
9663 | int mask; | |
9664 | ||
9665 | if (c == 'l') | |
9666 | mask = 0; | |
9667 | else | |
9668 | mask = 7 << 3; | |
9669 | while (*s != '\0') | |
9670 | { | |
9671 | int freg, reg1, reg2; | |
9672 | ||
9673 | while (*s == ' ' || *s == ',') | |
9674 | ++s; | |
9675 | if (*s != '$') | |
9676 | { | |
9677 | as_bad (_("can't parse register list")); | |
9678 | break; | |
9679 | } | |
9680 | ++s; | |
9681 | if (*s != 'f') | |
9682 | freg = 0; | |
9683 | else | |
9684 | { | |
9685 | freg = 1; | |
9686 | ++s; | |
9687 | } | |
9688 | reg1 = 0; | |
3882b010 | 9689 | while (ISDIGIT (*s)) |
252b5132 RH |
9690 | { |
9691 | reg1 *= 10; | |
9692 | reg1 += *s - '0'; | |
9693 | ++s; | |
9694 | } | |
9695 | if (*s == ' ') | |
9696 | ++s; | |
9697 | if (*s != '-') | |
9698 | reg2 = reg1; | |
9699 | else | |
9700 | { | |
9701 | ++s; | |
9702 | if (*s != '$') | |
9703 | break; | |
9704 | ++s; | |
9705 | if (freg) | |
9706 | { | |
9707 | if (*s == 'f') | |
9708 | ++s; | |
9709 | else | |
9710 | { | |
9711 | as_bad (_("invalid register list")); | |
9712 | break; | |
9713 | } | |
9714 | } | |
9715 | reg2 = 0; | |
3882b010 | 9716 | while (ISDIGIT (*s)) |
252b5132 RH |
9717 | { |
9718 | reg2 *= 10; | |
9719 | reg2 += *s - '0'; | |
9720 | ++s; | |
9721 | } | |
9722 | } | |
9723 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
9724 | { | |
9725 | mask &= ~ (7 << 3); | |
9726 | mask |= 5 << 3; | |
9727 | } | |
9728 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
9729 | { | |
9730 | mask &= ~ (7 << 3); | |
9731 | mask |= 6 << 3; | |
9732 | } | |
9733 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
9734 | mask |= (reg2 - 3) << 3; | |
9735 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
9736 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 9737 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
9738 | mask |= 1; |
9739 | else | |
9740 | { | |
9741 | as_bad (_("invalid register list")); | |
9742 | break; | |
9743 | } | |
9744 | } | |
9745 | /* The mask is filled in in the opcode table for the | |
9746 | benefit of the disassembler. We remove it before | |
9747 | applying the actual mask. */ | |
9748 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
9749 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
9750 | } | |
9751 | continue; | |
9752 | ||
9753 | case 'e': /* extend code */ | |
9754 | my_getExpression (&imm_expr, s); | |
9755 | check_absolute_expr (ip, &imm_expr); | |
9756 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
9757 | { | |
9758 | as_warn (_("Invalid value for `%s' (%lu)"), | |
9759 | ip->insn_mo->name, | |
9760 | (unsigned long) imm_expr.X_add_number); | |
9761 | imm_expr.X_add_number &= 0x7ff; | |
9762 | } | |
9763 | ip->insn_opcode |= imm_expr.X_add_number; | |
9764 | imm_expr.X_op = O_absent; | |
9765 | s = expr_end; | |
9766 | continue; | |
9767 | ||
9768 | default: | |
9769 | internalError (); | |
9770 | } | |
9771 | break; | |
9772 | } | |
9773 | ||
9774 | /* Args don't match. */ | |
9775 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
9776 | strcmp (insn->name, insn[1].name) == 0) | |
9777 | { | |
9778 | ++insn; | |
9779 | s = argsstart; | |
9780 | continue; | |
9781 | } | |
9782 | ||
9783 | insn_error = _("illegal operands"); | |
9784 | ||
9785 | return; | |
9786 | } | |
9787 | } | |
9788 | ||
9789 | /* This structure holds information we know about a mips16 immediate | |
9790 | argument type. */ | |
9791 | ||
e972090a NC |
9792 | struct mips16_immed_operand |
9793 | { | |
252b5132 RH |
9794 | /* The type code used in the argument string in the opcode table. */ |
9795 | int type; | |
9796 | /* The number of bits in the short form of the opcode. */ | |
9797 | int nbits; | |
9798 | /* The number of bits in the extended form of the opcode. */ | |
9799 | int extbits; | |
9800 | /* The amount by which the short form is shifted when it is used; | |
9801 | for example, the sw instruction has a shift count of 2. */ | |
9802 | int shift; | |
9803 | /* The amount by which the short form is shifted when it is stored | |
9804 | into the instruction code. */ | |
9805 | int op_shift; | |
9806 | /* Non-zero if the short form is unsigned. */ | |
9807 | int unsp; | |
9808 | /* Non-zero if the extended form is unsigned. */ | |
9809 | int extu; | |
9810 | /* Non-zero if the value is PC relative. */ | |
9811 | int pcrel; | |
9812 | }; | |
9813 | ||
9814 | /* The mips16 immediate operand types. */ | |
9815 | ||
9816 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
9817 | { | |
9818 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
9819 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
9820 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
9821 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
9822 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
9823 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9824 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9825 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9826 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9827 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
9828 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9829 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9830 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9831 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
9832 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
9833 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
9834 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
9835 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
9836 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
9837 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
9838 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
9839 | }; | |
9840 | ||
9841 | #define MIPS16_NUM_IMMED \ | |
9842 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
9843 | ||
9844 | /* Handle a mips16 instruction with an immediate value. This or's the | |
9845 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
9846 | whether an extended value is needed; if one is needed, it sets | |
9847 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
9848 | If SMALL is true, an unextended opcode was explicitly requested. | |
9849 | If EXT is true, an extended opcode was explicitly requested. If | |
9850 | WARN is true, warn if EXT does not match reality. */ | |
9851 | ||
9852 | static void | |
17a2f251 TS |
9853 | mips16_immed (char *file, unsigned int line, int type, offsetT val, |
9854 | bfd_boolean warn, bfd_boolean small, bfd_boolean ext, | |
9855 | unsigned long *insn, bfd_boolean *use_extend, | |
9856 | unsigned short *extend) | |
252b5132 RH |
9857 | { |
9858 | register const struct mips16_immed_operand *op; | |
9859 | int mintiny, maxtiny; | |
b34976b6 | 9860 | bfd_boolean needext; |
252b5132 RH |
9861 | |
9862 | op = mips16_immed_operands; | |
9863 | while (op->type != type) | |
9864 | { | |
9865 | ++op; | |
9866 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
9867 | } | |
9868 | ||
9869 | if (op->unsp) | |
9870 | { | |
9871 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
9872 | { | |
9873 | mintiny = 1; | |
9874 | maxtiny = 1 << op->nbits; | |
9875 | } | |
9876 | else | |
9877 | { | |
9878 | mintiny = 0; | |
9879 | maxtiny = (1 << op->nbits) - 1; | |
9880 | } | |
9881 | } | |
9882 | else | |
9883 | { | |
9884 | mintiny = - (1 << (op->nbits - 1)); | |
9885 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
9886 | } | |
9887 | ||
9888 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
9889 | if (type == 'p' || type == 'q') | |
9890 | val /= 2; | |
9891 | ||
9892 | if ((val & ((1 << op->shift) - 1)) != 0 | |
9893 | || val < (mintiny << op->shift) | |
9894 | || val > (maxtiny << op->shift)) | |
b34976b6 | 9895 | needext = TRUE; |
252b5132 | 9896 | else |
b34976b6 | 9897 | needext = FALSE; |
252b5132 RH |
9898 | |
9899 | if (warn && ext && ! needext) | |
beae10d5 KH |
9900 | as_warn_where (file, line, |
9901 | _("extended operand requested but not required")); | |
252b5132 RH |
9902 | if (small && needext) |
9903 | as_bad_where (file, line, _("invalid unextended operand value")); | |
9904 | ||
9905 | if (small || (! ext && ! needext)) | |
9906 | { | |
9907 | int insnval; | |
9908 | ||
b34976b6 | 9909 | *use_extend = FALSE; |
252b5132 RH |
9910 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
9911 | insnval <<= op->op_shift; | |
9912 | *insn |= insnval; | |
9913 | } | |
9914 | else | |
9915 | { | |
9916 | long minext, maxext; | |
9917 | int extval; | |
9918 | ||
9919 | if (op->extu) | |
9920 | { | |
9921 | minext = 0; | |
9922 | maxext = (1 << op->extbits) - 1; | |
9923 | } | |
9924 | else | |
9925 | { | |
9926 | minext = - (1 << (op->extbits - 1)); | |
9927 | maxext = (1 << (op->extbits - 1)) - 1; | |
9928 | } | |
9929 | if (val < minext || val > maxext) | |
9930 | as_bad_where (file, line, | |
9931 | _("operand value out of range for instruction")); | |
9932 | ||
b34976b6 | 9933 | *use_extend = TRUE; |
252b5132 RH |
9934 | if (op->extbits == 16) |
9935 | { | |
9936 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
9937 | val &= 0x1f; | |
9938 | } | |
9939 | else if (op->extbits == 15) | |
9940 | { | |
9941 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
9942 | val &= 0xf; | |
9943 | } | |
9944 | else | |
9945 | { | |
9946 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
9947 | val = 0; | |
9948 | } | |
9949 | ||
9950 | *extend = (unsigned short) extval; | |
9951 | *insn |= val; | |
9952 | } | |
9953 | } | |
9954 | \f | |
5e0116d5 | 9955 | static const struct percent_op_match |
ad8d3bb3 | 9956 | { |
5e0116d5 RS |
9957 | const char *str; |
9958 | bfd_reloc_code_real_type reloc; | |
ad8d3bb3 TS |
9959 | } percent_op[] = |
9960 | { | |
5e0116d5 | 9961 | {"%lo", BFD_RELOC_LO16}, |
ad8d3bb3 | 9962 | #ifdef OBJ_ELF |
5e0116d5 RS |
9963 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
9964 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
9965 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
9966 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
9967 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
9968 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
9969 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
9970 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
9971 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
9972 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
9973 | {"%half", BFD_RELOC_16}, | |
9974 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
9975 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
9976 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
ad8d3bb3 | 9977 | #endif |
5e0116d5 | 9978 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
9979 | }; |
9980 | ||
252b5132 | 9981 | |
5e0116d5 RS |
9982 | /* Return true if *STR points to a relocation operator. When returning true, |
9983 | move *STR over the operator and store its relocation code in *RELOC. | |
9984 | Leave both *STR and *RELOC alone when returning false. */ | |
9985 | ||
9986 | static bfd_boolean | |
17a2f251 | 9987 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 9988 | { |
5e0116d5 | 9989 | size_t i; |
76b3015f | 9990 | |
5e0116d5 RS |
9991 | for (i = 0; i < ARRAY_SIZE (percent_op); i++) |
9992 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) | |
394f9b3a | 9993 | { |
5e0116d5 RS |
9994 | *str += strlen (percent_op[i].str); |
9995 | *reloc = percent_op[i].reloc; | |
394f9b3a | 9996 | |
5e0116d5 RS |
9997 | /* Check whether the output BFD supports this relocation. |
9998 | If not, issue an error and fall back on something safe. */ | |
9999 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 10000 | { |
5e0116d5 RS |
10001 | as_bad ("relocation %s isn't supported by the current ABI", |
10002 | percent_op[i].str); | |
10003 | *reloc = BFD_RELOC_LO16; | |
394f9b3a | 10004 | } |
5e0116d5 | 10005 | return TRUE; |
394f9b3a | 10006 | } |
5e0116d5 | 10007 | return FALSE; |
394f9b3a | 10008 | } |
ad8d3bb3 | 10009 | |
ad8d3bb3 | 10010 | |
5e0116d5 RS |
10011 | /* Parse string STR as a 16-bit relocatable operand. Store the |
10012 | expression in *EP and the relocations in the array starting | |
10013 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 10014 | |
5e0116d5 RS |
10015 | On exit, EXPR_END points to the first character after the expression. |
10016 | If no relocation operators are used, RELOC[0] is set to BFD_RELOC_LO16. */ | |
ad8d3bb3 | 10017 | |
5e0116d5 | 10018 | static size_t |
17a2f251 TS |
10019 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
10020 | char *str) | |
ad8d3bb3 | 10021 | { |
5e0116d5 RS |
10022 | bfd_reloc_code_real_type reversed_reloc[3]; |
10023 | size_t reloc_index, i; | |
09b8f35a RS |
10024 | int crux_depth, str_depth; |
10025 | char *crux; | |
5e0116d5 RS |
10026 | |
10027 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
10028 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
10029 | of the main expression and with CRUX_DEPTH containing the number | |
10030 | of open brackets at that point. */ | |
10031 | reloc_index = -1; | |
10032 | str_depth = 0; | |
10033 | do | |
fb1b3232 | 10034 | { |
09b8f35a RS |
10035 | reloc_index++; |
10036 | crux = str; | |
10037 | crux_depth = str_depth; | |
10038 | ||
10039 | /* Skip over whitespace and brackets, keeping count of the number | |
10040 | of brackets. */ | |
10041 | while (*str == ' ' || *str == '\t' || *str == '(') | |
10042 | if (*str++ == '(') | |
10043 | str_depth++; | |
5e0116d5 | 10044 | } |
09b8f35a RS |
10045 | while (*str == '%' |
10046 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
10047 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 10048 | |
09b8f35a | 10049 | my_getExpression (ep, crux); |
5e0116d5 | 10050 | str = expr_end; |
394f9b3a | 10051 | |
5e0116d5 | 10052 | /* Match every open bracket. */ |
09b8f35a | 10053 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 10054 | if (*str++ == ')') |
09b8f35a | 10055 | crux_depth--; |
394f9b3a | 10056 | |
09b8f35a | 10057 | if (crux_depth > 0) |
5e0116d5 | 10058 | as_bad ("unclosed '('"); |
394f9b3a | 10059 | |
5e0116d5 | 10060 | expr_end = str; |
252b5132 | 10061 | |
64bdfcaf RS |
10062 | if (reloc_index == 0) |
10063 | reloc[0] = BFD_RELOC_LO16; | |
10064 | else | |
10065 | { | |
10066 | prev_reloc_op_frag = frag_now; | |
10067 | for (i = 0; i < reloc_index; i++) | |
10068 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
10069 | } | |
fb1b3232 | 10070 | |
5e0116d5 | 10071 | return reloc_index; |
252b5132 RH |
10072 | } |
10073 | ||
10074 | static void | |
17a2f251 | 10075 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
10076 | { |
10077 | char *save_in; | |
98aa84af | 10078 | valueT val; |
252b5132 RH |
10079 | |
10080 | save_in = input_line_pointer; | |
10081 | input_line_pointer = str; | |
10082 | expression (ep); | |
10083 | expr_end = input_line_pointer; | |
10084 | input_line_pointer = save_in; | |
10085 | ||
10086 | /* If we are in mips16 mode, and this is an expression based on `.', | |
10087 | then we bump the value of the symbol by 1 since that is how other | |
10088 | text symbols are handled. We don't bother to handle complex | |
10089 | expressions, just `.' plus or minus a constant. */ | |
10090 | if (mips_opts.mips16 | |
10091 | && ep->X_op == O_symbol | |
10092 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
10093 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
49309057 ILT |
10094 | && symbol_get_frag (ep->X_add_symbol) == frag_now |
10095 | && symbol_constant_p (ep->X_add_symbol) | |
98aa84af AM |
10096 | && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ()) |
10097 | S_SET_VALUE (ep->X_add_symbol, val + 1); | |
252b5132 RH |
10098 | } |
10099 | ||
10100 | /* Turn a string in input_line_pointer into a floating point constant | |
bc0d738a NC |
10101 | of type TYPE, and store the appropriate bytes in *LITP. The number |
10102 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
252b5132 RH |
10103 | returned, or NULL on OK. */ |
10104 | ||
10105 | char * | |
17a2f251 | 10106 | md_atof (int type, char *litP, int *sizeP) |
252b5132 RH |
10107 | { |
10108 | int prec; | |
10109 | LITTLENUM_TYPE words[4]; | |
10110 | char *t; | |
10111 | int i; | |
10112 | ||
10113 | switch (type) | |
10114 | { | |
10115 | case 'f': | |
10116 | prec = 2; | |
10117 | break; | |
10118 | ||
10119 | case 'd': | |
10120 | prec = 4; | |
10121 | break; | |
10122 | ||
10123 | default: | |
10124 | *sizeP = 0; | |
10125 | return _("bad call to md_atof"); | |
10126 | } | |
10127 | ||
10128 | t = atof_ieee (input_line_pointer, type, words); | |
10129 | if (t) | |
10130 | input_line_pointer = t; | |
10131 | ||
10132 | *sizeP = prec * 2; | |
10133 | ||
10134 | if (! target_big_endian) | |
10135 | { | |
10136 | for (i = prec - 1; i >= 0; i--) | |
10137 | { | |
17a2f251 | 10138 | md_number_to_chars (litP, words[i], 2); |
252b5132 RH |
10139 | litP += 2; |
10140 | } | |
10141 | } | |
10142 | else | |
10143 | { | |
10144 | for (i = 0; i < prec; i++) | |
10145 | { | |
17a2f251 | 10146 | md_number_to_chars (litP, words[i], 2); |
252b5132 RH |
10147 | litP += 2; |
10148 | } | |
10149 | } | |
bdaaa2e1 | 10150 | |
252b5132 RH |
10151 | return NULL; |
10152 | } | |
10153 | ||
10154 | void | |
17a2f251 | 10155 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
10156 | { |
10157 | if (target_big_endian) | |
10158 | number_to_chars_bigendian (buf, val, n); | |
10159 | else | |
10160 | number_to_chars_littleendian (buf, val, n); | |
10161 | } | |
10162 | \f | |
ae948b86 | 10163 | #ifdef OBJ_ELF |
e013f690 TS |
10164 | static int support_64bit_objects(void) |
10165 | { | |
10166 | const char **list, **l; | |
aa3d8fdf | 10167 | int yes; |
e013f690 TS |
10168 | |
10169 | list = bfd_target_list (); | |
10170 | for (l = list; *l != NULL; l++) | |
10171 | #ifdef TE_TMIPS | |
10172 | /* This is traditional mips */ | |
10173 | if (strcmp (*l, "elf64-tradbigmips") == 0 | |
10174 | || strcmp (*l, "elf64-tradlittlemips") == 0) | |
10175 | #else | |
10176 | if (strcmp (*l, "elf64-bigmips") == 0 | |
10177 | || strcmp (*l, "elf64-littlemips") == 0) | |
10178 | #endif | |
10179 | break; | |
aa3d8fdf | 10180 | yes = (*l != NULL); |
e013f690 | 10181 | free (list); |
aa3d8fdf | 10182 | return yes; |
e013f690 | 10183 | } |
ae948b86 | 10184 | #endif /* OBJ_ELF */ |
e013f690 | 10185 | |
78849248 | 10186 | const char *md_shortopts = "O::g::G:"; |
252b5132 | 10187 | |
e972090a NC |
10188 | struct option md_longopts[] = |
10189 | { | |
f9b4148d CD |
10190 | /* Options which specify architecture. */ |
10191 | #define OPTION_ARCH_BASE (OPTION_MD_BASE) | |
10192 | #define OPTION_MARCH (OPTION_ARCH_BASE + 0) | |
10193 | {"march", required_argument, NULL, OPTION_MARCH}, | |
10194 | #define OPTION_MTUNE (OPTION_ARCH_BASE + 1) | |
10195 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
10196 | #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2) | |
252b5132 RH |
10197 | {"mips0", no_argument, NULL, OPTION_MIPS1}, |
10198 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
f9b4148d | 10199 | #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3) |
252b5132 | 10200 | {"mips2", no_argument, NULL, OPTION_MIPS2}, |
f9b4148d | 10201 | #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4) |
252b5132 | 10202 | {"mips3", no_argument, NULL, OPTION_MIPS3}, |
f9b4148d | 10203 | #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5) |
252b5132 | 10204 | {"mips4", no_argument, NULL, OPTION_MIPS4}, |
f9b4148d | 10205 | #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6) |
ae948b86 | 10206 | {"mips5", no_argument, NULL, OPTION_MIPS5}, |
f9b4148d | 10207 | #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7) |
ae948b86 | 10208 | {"mips32", no_argument, NULL, OPTION_MIPS32}, |
f9b4148d | 10209 | #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8) |
ae948b86 | 10210 | {"mips64", no_argument, NULL, OPTION_MIPS64}, |
f9b4148d CD |
10211 | #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9) |
10212 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, | |
5f74bc13 CD |
10213 | #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10) |
10214 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, | |
f9b4148d CD |
10215 | |
10216 | /* Options which specify Application Specific Extensions (ASEs). */ | |
5f74bc13 | 10217 | #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11) |
f9b4148d CD |
10218 | #define OPTION_MIPS16 (OPTION_ASE_BASE + 0) |
10219 | {"mips16", no_argument, NULL, OPTION_MIPS16}, | |
10220 | #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1) | |
10221 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, | |
10222 | #define OPTION_MIPS3D (OPTION_ASE_BASE + 2) | |
10223 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, | |
10224 | #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3) | |
10225 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, | |
10226 | #define OPTION_MDMX (OPTION_ASE_BASE + 4) | |
10227 | {"mdmx", no_argument, NULL, OPTION_MDMX}, | |
10228 | #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5) | |
10229 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, | |
10230 | ||
10231 | /* Old-style architecture options. Don't add more of these. */ | |
10232 | #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6) | |
10233 | #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0) | |
10234 | {"m4650", no_argument, NULL, OPTION_M4650}, | |
10235 | #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1) | |
10236 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, | |
10237 | #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2) | |
10238 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
10239 | #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3) | |
10240 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
10241 | #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4) | |
10242 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
10243 | #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5) | |
10244 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
10245 | #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6) | |
10246 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
10247 | #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7) | |
10248 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
10249 | ||
10250 | /* Options which enable bug fixes. */ | |
10251 | #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8) | |
10252 | #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0) | |
10253 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, | |
10254 | #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1) | |
10255 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
10256 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
d766e8ec RS |
10257 | #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2) |
10258 | #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3) | |
10259 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, | |
10260 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
f9b4148d CD |
10261 | |
10262 | /* Miscellaneous options. */ | |
10263 | #define OPTION_MISC_BASE (OPTION_FIX_BASE + 4) | |
10264 | #define OPTION_MEMBEDDED_PIC (OPTION_MISC_BASE + 0) | |
252b5132 | 10265 | {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC}, |
f9b4148d | 10266 | #define OPTION_TRAP (OPTION_MISC_BASE + 1) |
252b5132 RH |
10267 | {"trap", no_argument, NULL, OPTION_TRAP}, |
10268 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
f9b4148d | 10269 | #define OPTION_BREAK (OPTION_MISC_BASE + 2) |
252b5132 RH |
10270 | {"break", no_argument, NULL, OPTION_BREAK}, |
10271 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
f9b4148d | 10272 | #define OPTION_EB (OPTION_MISC_BASE + 3) |
252b5132 | 10273 | {"EB", no_argument, NULL, OPTION_EB}, |
f9b4148d | 10274 | #define OPTION_EL (OPTION_MISC_BASE + 4) |
252b5132 | 10275 | {"EL", no_argument, NULL, OPTION_EL}, |
f9b4148d | 10276 | #define OPTION_FP32 (OPTION_MISC_BASE + 5) |
ae948b86 | 10277 | {"mfp32", no_argument, NULL, OPTION_FP32}, |
f9b4148d | 10278 | #define OPTION_GP32 (OPTION_MISC_BASE + 6) |
c97ef257 | 10279 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
f9b4148d | 10280 | #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7) |
119d663a | 10281 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
f9b4148d | 10282 | #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 8) |
119d663a | 10283 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
f9b4148d | 10284 | #define OPTION_FP64 (OPTION_MISC_BASE + 9) |
316f5878 | 10285 | {"mfp64", no_argument, NULL, OPTION_FP64}, |
f9b4148d | 10286 | #define OPTION_GP64 (OPTION_MISC_BASE + 10) |
ae948b86 | 10287 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
f9b4148d CD |
10288 | #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 11) |
10289 | #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 12) | |
4a6a3df4 AO |
10290 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, |
10291 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
f9b4148d CD |
10292 | |
10293 | /* ELF-specific options. */ | |
156c2f8b | 10294 | #ifdef OBJ_ELF |
f9b4148d | 10295 | #define OPTION_ELF_BASE (OPTION_MISC_BASE + 13) |
156c2f8b | 10296 | #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0) |
156c2f8b NC |
10297 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
10298 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
ae948b86 | 10299 | #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1) |
156c2f8b | 10300 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
ae948b86 | 10301 | #define OPTION_XGOT (OPTION_ELF_BASE + 2) |
156c2f8b | 10302 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
ae948b86 TS |
10303 | #define OPTION_MABI (OPTION_ELF_BASE + 3) |
10304 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
10305 | #define OPTION_32 (OPTION_ELF_BASE + 4) | |
156c2f8b | 10306 | {"32", no_argument, NULL, OPTION_32}, |
ae948b86 | 10307 | #define OPTION_N32 (OPTION_ELF_BASE + 5) |
e013f690 | 10308 | {"n32", no_argument, NULL, OPTION_N32}, |
ae948b86 | 10309 | #define OPTION_64 (OPTION_ELF_BASE + 6) |
156c2f8b | 10310 | {"64", no_argument, NULL, OPTION_64}, |
ecb4347a DJ |
10311 | #define OPTION_MDEBUG (OPTION_ELF_BASE + 7) |
10312 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, | |
10313 | #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8) | |
10314 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, | |
dcd410fe RO |
10315 | #define OPTION_PDR (OPTION_ELF_BASE + 9) |
10316 | {"mpdr", no_argument, NULL, OPTION_PDR}, | |
10317 | #define OPTION_NO_PDR (OPTION_ELF_BASE + 10) | |
10318 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, | |
ae948b86 | 10319 | #endif /* OBJ_ELF */ |
f9b4148d | 10320 | |
252b5132 RH |
10321 | {NULL, no_argument, NULL, 0} |
10322 | }; | |
156c2f8b | 10323 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 10324 | |
316f5878 RS |
10325 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
10326 | NEW_VALUE. Warn if another value was already specified. Note: | |
10327 | we have to defer parsing the -march and -mtune arguments in order | |
10328 | to handle 'from-abi' correctly, since the ABI might be specified | |
10329 | in a later argument. */ | |
10330 | ||
10331 | static void | |
17a2f251 | 10332 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
10333 | { |
10334 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
10335 | as_warn (_("A different %s was already specified, is now %s"), | |
10336 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
10337 | new_value); | |
10338 | ||
10339 | *string_ptr = new_value; | |
10340 | } | |
10341 | ||
252b5132 | 10342 | int |
17a2f251 | 10343 | md_parse_option (int c, char *arg) |
252b5132 RH |
10344 | { |
10345 | switch (c) | |
10346 | { | |
119d663a NC |
10347 | case OPTION_CONSTRUCT_FLOATS: |
10348 | mips_disable_float_construction = 0; | |
10349 | break; | |
bdaaa2e1 | 10350 | |
119d663a NC |
10351 | case OPTION_NO_CONSTRUCT_FLOATS: |
10352 | mips_disable_float_construction = 1; | |
10353 | break; | |
bdaaa2e1 | 10354 | |
252b5132 RH |
10355 | case OPTION_TRAP: |
10356 | mips_trap = 1; | |
10357 | break; | |
10358 | ||
10359 | case OPTION_BREAK: | |
10360 | mips_trap = 0; | |
10361 | break; | |
10362 | ||
10363 | case OPTION_EB: | |
10364 | target_big_endian = 1; | |
10365 | break; | |
10366 | ||
10367 | case OPTION_EL: | |
10368 | target_big_endian = 0; | |
10369 | break; | |
10370 | ||
10371 | case 'O': | |
10372 | if (arg && arg[1] == '0') | |
10373 | mips_optimize = 1; | |
10374 | else | |
10375 | mips_optimize = 2; | |
10376 | break; | |
10377 | ||
10378 | case 'g': | |
10379 | if (arg == NULL) | |
10380 | mips_debug = 2; | |
10381 | else | |
10382 | mips_debug = atoi (arg); | |
10383 | /* When the MIPS assembler sees -g or -g2, it does not do | |
10384 | optimizations which limit full symbolic debugging. We take | |
10385 | that to be equivalent to -O0. */ | |
10386 | if (mips_debug == 2) | |
10387 | mips_optimize = 1; | |
10388 | break; | |
10389 | ||
10390 | case OPTION_MIPS1: | |
316f5878 | 10391 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
10392 | break; |
10393 | ||
10394 | case OPTION_MIPS2: | |
316f5878 | 10395 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
10396 | break; |
10397 | ||
10398 | case OPTION_MIPS3: | |
316f5878 | 10399 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
10400 | break; |
10401 | ||
10402 | case OPTION_MIPS4: | |
316f5878 | 10403 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
10404 | break; |
10405 | ||
84ea6cf2 | 10406 | case OPTION_MIPS5: |
316f5878 | 10407 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
10408 | break; |
10409 | ||
e7af610e | 10410 | case OPTION_MIPS32: |
316f5878 | 10411 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
10412 | break; |
10413 | ||
af7ee8bf CD |
10414 | case OPTION_MIPS32R2: |
10415 | file_mips_isa = ISA_MIPS32R2; | |
10416 | break; | |
10417 | ||
5f74bc13 CD |
10418 | case OPTION_MIPS64R2: |
10419 | file_mips_isa = ISA_MIPS64R2; | |
10420 | break; | |
10421 | ||
84ea6cf2 | 10422 | case OPTION_MIPS64: |
316f5878 | 10423 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
10424 | break; |
10425 | ||
ec68c924 | 10426 | case OPTION_MTUNE: |
316f5878 RS |
10427 | mips_set_option_string (&mips_tune_string, arg); |
10428 | break; | |
ec68c924 | 10429 | |
316f5878 RS |
10430 | case OPTION_MARCH: |
10431 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
10432 | break; |
10433 | ||
10434 | case OPTION_M4650: | |
316f5878 RS |
10435 | mips_set_option_string (&mips_arch_string, "4650"); |
10436 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
10437 | break; |
10438 | ||
10439 | case OPTION_NO_M4650: | |
10440 | break; | |
10441 | ||
10442 | case OPTION_M4010: | |
316f5878 RS |
10443 | mips_set_option_string (&mips_arch_string, "4010"); |
10444 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
10445 | break; |
10446 | ||
10447 | case OPTION_NO_M4010: | |
10448 | break; | |
10449 | ||
10450 | case OPTION_M4100: | |
316f5878 RS |
10451 | mips_set_option_string (&mips_arch_string, "4100"); |
10452 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
10453 | break; |
10454 | ||
10455 | case OPTION_NO_M4100: | |
10456 | break; | |
10457 | ||
252b5132 | 10458 | case OPTION_M3900: |
316f5878 RS |
10459 | mips_set_option_string (&mips_arch_string, "3900"); |
10460 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 10461 | break; |
bdaaa2e1 | 10462 | |
252b5132 RH |
10463 | case OPTION_NO_M3900: |
10464 | break; | |
10465 | ||
deec1734 CD |
10466 | case OPTION_MDMX: |
10467 | mips_opts.ase_mdmx = 1; | |
10468 | break; | |
10469 | ||
10470 | case OPTION_NO_MDMX: | |
10471 | mips_opts.ase_mdmx = 0; | |
10472 | break; | |
10473 | ||
252b5132 RH |
10474 | case OPTION_MIPS16: |
10475 | mips_opts.mips16 = 1; | |
b34976b6 | 10476 | mips_no_prev_insn (FALSE); |
252b5132 RH |
10477 | break; |
10478 | ||
10479 | case OPTION_NO_MIPS16: | |
10480 | mips_opts.mips16 = 0; | |
b34976b6 | 10481 | mips_no_prev_insn (FALSE); |
252b5132 RH |
10482 | break; |
10483 | ||
1f25f5d3 CD |
10484 | case OPTION_MIPS3D: |
10485 | mips_opts.ase_mips3d = 1; | |
10486 | break; | |
10487 | ||
10488 | case OPTION_NO_MIPS3D: | |
10489 | mips_opts.ase_mips3d = 0; | |
10490 | break; | |
10491 | ||
252b5132 RH |
10492 | case OPTION_MEMBEDDED_PIC: |
10493 | mips_pic = EMBEDDED_PIC; | |
10494 | if (USE_GLOBAL_POINTER_OPT && g_switch_seen) | |
10495 | { | |
10496 | as_bad (_("-G may not be used with embedded PIC code")); | |
10497 | return 0; | |
10498 | } | |
10499 | g_switch_value = 0x7fffffff; | |
10500 | break; | |
10501 | ||
d766e8ec RS |
10502 | case OPTION_FIX_VR4120: |
10503 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
10504 | break; |
10505 | ||
d766e8ec RS |
10506 | case OPTION_NO_FIX_VR4120: |
10507 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
10508 | break; |
10509 | ||
4a6a3df4 AO |
10510 | case OPTION_RELAX_BRANCH: |
10511 | mips_relax_branch = 1; | |
10512 | break; | |
10513 | ||
10514 | case OPTION_NO_RELAX_BRANCH: | |
10515 | mips_relax_branch = 0; | |
10516 | break; | |
10517 | ||
0f074f60 | 10518 | #ifdef OBJ_ELF |
252b5132 RH |
10519 | /* When generating ELF code, we permit -KPIC and -call_shared to |
10520 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
10521 | intended to be compatible with Irix 5. */ | |
10522 | case OPTION_CALL_SHARED: | |
10523 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10524 | { | |
10525 | as_bad (_("-call_shared is supported only for ELF format")); | |
10526 | return 0; | |
10527 | } | |
10528 | mips_pic = SVR4_PIC; | |
143d77c5 | 10529 | mips_abicalls = TRUE; |
252b5132 RH |
10530 | if (g_switch_seen && g_switch_value != 0) |
10531 | { | |
10532 | as_bad (_("-G may not be used with SVR4 PIC code")); | |
10533 | return 0; | |
10534 | } | |
10535 | g_switch_value = 0; | |
10536 | break; | |
10537 | ||
10538 | case OPTION_NON_SHARED: | |
10539 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10540 | { | |
10541 | as_bad (_("-non_shared is supported only for ELF format")); | |
10542 | return 0; | |
10543 | } | |
10544 | mips_pic = NO_PIC; | |
143d77c5 | 10545 | mips_abicalls = FALSE; |
252b5132 RH |
10546 | break; |
10547 | ||
10548 | /* The -xgot option tells the assembler to use 32 offsets when | |
10549 | accessing the got in SVR4_PIC mode. It is for Irix | |
10550 | compatibility. */ | |
10551 | case OPTION_XGOT: | |
10552 | mips_big_got = 1; | |
10553 | break; | |
0f074f60 | 10554 | #endif /* OBJ_ELF */ |
252b5132 RH |
10555 | |
10556 | case 'G': | |
10557 | if (! USE_GLOBAL_POINTER_OPT) | |
10558 | { | |
10559 | as_bad (_("-G is not supported for this configuration")); | |
10560 | return 0; | |
10561 | } | |
10562 | else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC) | |
10563 | { | |
10564 | as_bad (_("-G may not be used with SVR4 or embedded PIC code")); | |
10565 | return 0; | |
10566 | } | |
10567 | else | |
10568 | g_switch_value = atoi (arg); | |
10569 | g_switch_seen = 1; | |
10570 | break; | |
10571 | ||
0f074f60 | 10572 | #ifdef OBJ_ELF |
34ba82a8 TS |
10573 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
10574 | and -mabi=64. */ | |
252b5132 | 10575 | case OPTION_32: |
34ba82a8 TS |
10576 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10577 | { | |
10578 | as_bad (_("-32 is supported for ELF format only")); | |
10579 | return 0; | |
10580 | } | |
316f5878 | 10581 | mips_abi = O32_ABI; |
252b5132 RH |
10582 | break; |
10583 | ||
e013f690 | 10584 | case OPTION_N32: |
34ba82a8 TS |
10585 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10586 | { | |
10587 | as_bad (_("-n32 is supported for ELF format only")); | |
10588 | return 0; | |
10589 | } | |
316f5878 | 10590 | mips_abi = N32_ABI; |
e013f690 | 10591 | break; |
252b5132 | 10592 | |
e013f690 | 10593 | case OPTION_64: |
34ba82a8 TS |
10594 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10595 | { | |
10596 | as_bad (_("-64 is supported for ELF format only")); | |
10597 | return 0; | |
10598 | } | |
316f5878 | 10599 | mips_abi = N64_ABI; |
e013f690 TS |
10600 | if (! support_64bit_objects()) |
10601 | as_fatal (_("No compiled in support for 64 bit object file format")); | |
252b5132 | 10602 | break; |
ae948b86 | 10603 | #endif /* OBJ_ELF */ |
252b5132 | 10604 | |
c97ef257 | 10605 | case OPTION_GP32: |
a325df1d | 10606 | file_mips_gp32 = 1; |
c97ef257 AH |
10607 | break; |
10608 | ||
10609 | case OPTION_GP64: | |
a325df1d | 10610 | file_mips_gp32 = 0; |
c97ef257 | 10611 | break; |
252b5132 | 10612 | |
ca4e0257 | 10613 | case OPTION_FP32: |
a325df1d | 10614 | file_mips_fp32 = 1; |
316f5878 RS |
10615 | break; |
10616 | ||
10617 | case OPTION_FP64: | |
10618 | file_mips_fp32 = 0; | |
ca4e0257 RS |
10619 | break; |
10620 | ||
ae948b86 | 10621 | #ifdef OBJ_ELF |
252b5132 | 10622 | case OPTION_MABI: |
34ba82a8 TS |
10623 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10624 | { | |
10625 | as_bad (_("-mabi is supported for ELF format only")); | |
10626 | return 0; | |
10627 | } | |
e013f690 | 10628 | if (strcmp (arg, "32") == 0) |
316f5878 | 10629 | mips_abi = O32_ABI; |
e013f690 | 10630 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 10631 | mips_abi = O64_ABI; |
e013f690 | 10632 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 10633 | mips_abi = N32_ABI; |
e013f690 TS |
10634 | else if (strcmp (arg, "64") == 0) |
10635 | { | |
316f5878 | 10636 | mips_abi = N64_ABI; |
e013f690 TS |
10637 | if (! support_64bit_objects()) |
10638 | as_fatal (_("No compiled in support for 64 bit object file " | |
10639 | "format")); | |
10640 | } | |
10641 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 10642 | mips_abi = EABI_ABI; |
e013f690 | 10643 | else |
da0e507f TS |
10644 | { |
10645 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
10646 | return 0; | |
10647 | } | |
252b5132 | 10648 | break; |
e013f690 | 10649 | #endif /* OBJ_ELF */ |
252b5132 | 10650 | |
6b76fefe | 10651 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 10652 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
10653 | break; |
10654 | ||
9ee72ff1 | 10655 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 10656 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
10657 | break; |
10658 | ||
ecb4347a DJ |
10659 | #ifdef OBJ_ELF |
10660 | case OPTION_MDEBUG: | |
b34976b6 | 10661 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
10662 | break; |
10663 | ||
10664 | case OPTION_NO_MDEBUG: | |
b34976b6 | 10665 | mips_flag_mdebug = FALSE; |
ecb4347a | 10666 | break; |
dcd410fe RO |
10667 | |
10668 | case OPTION_PDR: | |
10669 | mips_flag_pdr = TRUE; | |
10670 | break; | |
10671 | ||
10672 | case OPTION_NO_PDR: | |
10673 | mips_flag_pdr = FALSE; | |
10674 | break; | |
ecb4347a DJ |
10675 | #endif /* OBJ_ELF */ |
10676 | ||
252b5132 RH |
10677 | default: |
10678 | return 0; | |
10679 | } | |
10680 | ||
10681 | return 1; | |
10682 | } | |
316f5878 RS |
10683 | \f |
10684 | /* Set up globals to generate code for the ISA or processor | |
10685 | described by INFO. */ | |
252b5132 | 10686 | |
252b5132 | 10687 | static void |
17a2f251 | 10688 | mips_set_architecture (const struct mips_cpu_info *info) |
252b5132 | 10689 | { |
316f5878 | 10690 | if (info != 0) |
252b5132 | 10691 | { |
fef14a42 TS |
10692 | file_mips_arch = info->cpu; |
10693 | mips_opts.arch = info->cpu; | |
316f5878 | 10694 | mips_opts.isa = info->isa; |
252b5132 | 10695 | } |
252b5132 RH |
10696 | } |
10697 | ||
252b5132 | 10698 | |
316f5878 | 10699 | /* Likewise for tuning. */ |
252b5132 | 10700 | |
316f5878 | 10701 | static void |
17a2f251 | 10702 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
10703 | { |
10704 | if (info != 0) | |
fef14a42 | 10705 | mips_tune = info->cpu; |
316f5878 | 10706 | } |
80cc45a5 | 10707 | |
34ba82a8 | 10708 | |
252b5132 | 10709 | void |
17a2f251 | 10710 | mips_after_parse_args (void) |
e9670677 | 10711 | { |
fef14a42 TS |
10712 | const struct mips_cpu_info *arch_info = 0; |
10713 | const struct mips_cpu_info *tune_info = 0; | |
10714 | ||
e9670677 MR |
10715 | /* GP relative stuff not working for PE */ |
10716 | if (strncmp (TARGET_OS, "pe", 2) == 0 | |
10717 | && g_switch_value != 0) | |
10718 | { | |
10719 | if (g_switch_seen) | |
10720 | as_bad (_("-G not supported in this configuration.")); | |
10721 | g_switch_value = 0; | |
10722 | } | |
10723 | ||
cac012d6 AO |
10724 | if (mips_abi == NO_ABI) |
10725 | mips_abi = MIPS_DEFAULT_ABI; | |
10726 | ||
22923709 RS |
10727 | /* The following code determines the architecture and register size. |
10728 | Similar code was added to GCC 3.3 (see override_options() in | |
10729 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
10730 | as much as possible. */ | |
e9670677 | 10731 | |
316f5878 | 10732 | if (mips_arch_string != 0) |
fef14a42 | 10733 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 10734 | |
316f5878 | 10735 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 10736 | { |
316f5878 | 10737 | /* Handle -mipsN. At this point, file_mips_isa contains the |
fef14a42 | 10738 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 10739 | the -march selection (if any). */ |
fef14a42 | 10740 | if (arch_info != 0) |
e9670677 | 10741 | { |
316f5878 RS |
10742 | /* -march takes precedence over -mipsN, since it is more descriptive. |
10743 | There's no harm in specifying both as long as the ISA levels | |
10744 | are the same. */ | |
fef14a42 | 10745 | if (file_mips_isa != arch_info->isa) |
316f5878 RS |
10746 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), |
10747 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
fef14a42 | 10748 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 10749 | } |
316f5878 | 10750 | else |
fef14a42 | 10751 | arch_info = mips_cpu_info_from_isa (file_mips_isa); |
e9670677 MR |
10752 | } |
10753 | ||
fef14a42 TS |
10754 | if (arch_info == 0) |
10755 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
e9670677 | 10756 | |
fef14a42 | 10757 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
316f5878 | 10758 | as_bad ("-march=%s is not compatible with the selected ABI", |
fef14a42 TS |
10759 | arch_info->name); |
10760 | ||
10761 | mips_set_architecture (arch_info); | |
10762 | ||
10763 | /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ | |
10764 | if (mips_tune_string != 0) | |
10765 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 10766 | |
fef14a42 TS |
10767 | if (tune_info == 0) |
10768 | mips_set_tune (arch_info); | |
10769 | else | |
10770 | mips_set_tune (tune_info); | |
e9670677 | 10771 | |
316f5878 | 10772 | if (file_mips_gp32 >= 0) |
e9670677 | 10773 | { |
316f5878 RS |
10774 | /* The user specified the size of the integer registers. Make sure |
10775 | it agrees with the ABI and ISA. */ | |
10776 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
10777 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
10778 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
10779 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
10780 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
10781 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
10782 | } |
10783 | else | |
10784 | { | |
316f5878 RS |
10785 | /* Infer the integer register size from the ABI and processor. |
10786 | Restrict ourselves to 32-bit registers if that's all the | |
10787 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
10788 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
10789 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
10790 | } |
10791 | ||
316f5878 RS |
10792 | /* ??? GAS treats single-float processors as though they had 64-bit |
10793 | float registers (although it complains when double-precision | |
10794 | instructions are used). As things stand, saying they have 32-bit | |
10795 | registers would lead to spurious "register must be even" messages. | |
10796 | So here we assume float registers are always the same size as | |
10797 | integer ones, unless the user says otherwise. */ | |
10798 | if (file_mips_fp32 < 0) | |
10799 | file_mips_fp32 = file_mips_gp32; | |
e9670677 | 10800 | |
316f5878 | 10801 | /* End of GCC-shared inference code. */ |
e9670677 | 10802 | |
17a2f251 TS |
10803 | /* This flag is set when we have a 64-bit capable CPU but use only |
10804 | 32-bit wide registers. Note that EABI does not use it. */ | |
10805 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) | |
10806 | && ((mips_abi == NO_ABI && file_mips_gp32 == 1) | |
10807 | || mips_abi == O32_ABI)) | |
316f5878 | 10808 | mips_32bitmode = 1; |
e9670677 MR |
10809 | |
10810 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
10811 | as_bad (_("trap exception not supported at ISA 1")); | |
10812 | ||
e9670677 MR |
10813 | /* If the selected architecture includes support for ASEs, enable |
10814 | generation of code for them. */ | |
a4672219 | 10815 | if (mips_opts.mips16 == -1) |
fef14a42 | 10816 | mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 10817 | if (mips_opts.ase_mips3d == -1) |
fef14a42 | 10818 | mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 10819 | if (mips_opts.ase_mdmx == -1) |
fef14a42 | 10820 | mips_opts.ase_mdmx = (CPU_HAS_MDMX (file_mips_arch)) ? 1 : 0; |
e9670677 | 10821 | |
e9670677 | 10822 | file_mips_isa = mips_opts.isa; |
a4672219 | 10823 | file_ase_mips16 = mips_opts.mips16; |
e9670677 MR |
10824 | file_ase_mips3d = mips_opts.ase_mips3d; |
10825 | file_ase_mdmx = mips_opts.ase_mdmx; | |
10826 | mips_opts.gp32 = file_mips_gp32; | |
10827 | mips_opts.fp32 = file_mips_fp32; | |
10828 | ||
ecb4347a DJ |
10829 | if (mips_flag_mdebug < 0) |
10830 | { | |
10831 | #ifdef OBJ_MAYBE_ECOFF | |
10832 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) | |
10833 | mips_flag_mdebug = 1; | |
10834 | else | |
10835 | #endif /* OBJ_MAYBE_ECOFF */ | |
10836 | mips_flag_mdebug = 0; | |
10837 | } | |
e9670677 MR |
10838 | } |
10839 | \f | |
10840 | void | |
17a2f251 | 10841 | mips_init_after_args (void) |
252b5132 RH |
10842 | { |
10843 | /* initialize opcodes */ | |
10844 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 10845 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
10846 | } |
10847 | ||
10848 | long | |
17a2f251 | 10849 | md_pcrel_from (fixS *fixP) |
252b5132 | 10850 | { |
a7ebbfdf TS |
10851 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
10852 | switch (fixP->fx_r_type) | |
10853 | { | |
10854 | case BFD_RELOC_16_PCREL_S2: | |
10855 | case BFD_RELOC_MIPS_JMP: | |
10856 | /* Return the address of the delay slot. */ | |
10857 | return addr + 4; | |
10858 | default: | |
10859 | return addr; | |
10860 | } | |
252b5132 RH |
10861 | } |
10862 | ||
252b5132 RH |
10863 | /* This is called before the symbol table is processed. In order to |
10864 | work with gcc when using mips-tfile, we must keep all local labels. | |
10865 | However, in other cases, we want to discard them. If we were | |
10866 | called with -g, but we didn't see any debugging information, it may | |
10867 | mean that gcc is smuggling debugging information through to | |
10868 | mips-tfile, in which case we must generate all local labels. */ | |
10869 | ||
10870 | void | |
17a2f251 | 10871 | mips_frob_file_before_adjust (void) |
252b5132 RH |
10872 | { |
10873 | #ifndef NO_ECOFF_DEBUGGING | |
10874 | if (ECOFF_DEBUGGING | |
10875 | && mips_debug != 0 | |
10876 | && ! ecoff_debugging_seen) | |
10877 | flag_keep_locals = 1; | |
10878 | #endif | |
10879 | } | |
10880 | ||
10881 | /* Sort any unmatched HI16_S relocs so that they immediately precede | |
94f592af | 10882 | the corresponding LO reloc. This is called before md_apply_fix3 and |
252b5132 RH |
10883 | tc_gen_reloc. Unmatched HI16_S relocs can only be generated by |
10884 | explicit use of the %hi modifier. */ | |
10885 | ||
10886 | void | |
17a2f251 | 10887 | mips_frob_file (void) |
252b5132 RH |
10888 | { |
10889 | struct mips_hi_fixup *l; | |
10890 | ||
10891 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
10892 | { | |
10893 | segment_info_type *seginfo; | |
10894 | int pass; | |
10895 | ||
5919d012 | 10896 | assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 10897 | |
5919d012 RS |
10898 | /* If a GOT16 relocation turns out to be against a global symbol, |
10899 | there isn't supposed to be a matching LO. */ | |
10900 | if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
10901 | && !pic_need_relax (l->fixp->fx_addsy, l->seg)) | |
10902 | continue; | |
10903 | ||
10904 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
10905 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
10906 | continue; |
10907 | ||
10908 | /* Look through the fixups for this segment for a matching %lo. | |
10909 | When we find one, move the %hi just in front of it. We do | |
10910 | this in two passes. In the first pass, we try to find a | |
10911 | unique %lo. In the second pass, we permit multiple %hi | |
10912 | relocs for a single %lo (this is a GNU extension). */ | |
10913 | seginfo = seg_info (l->seg); | |
10914 | for (pass = 0; pass < 2; pass++) | |
10915 | { | |
10916 | fixS *f, *prev; | |
10917 | ||
10918 | prev = NULL; | |
10919 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) | |
10920 | { | |
10921 | /* Check whether this is a %lo fixup which matches l->fixp. */ | |
10922 | if (f->fx_r_type == BFD_RELOC_LO16 | |
10923 | && f->fx_addsy == l->fixp->fx_addsy | |
10924 | && f->fx_offset == l->fixp->fx_offset | |
10925 | && (pass == 1 | |
10926 | || prev == NULL | |
5919d012 RS |
10927 | || !reloc_needs_lo_p (prev->fx_r_type) |
10928 | || !fixup_has_matching_lo_p (prev))) | |
252b5132 RH |
10929 | { |
10930 | fixS **pf; | |
10931 | ||
10932 | /* Move l->fixp before f. */ | |
10933 | for (pf = &seginfo->fix_root; | |
10934 | *pf != l->fixp; | |
10935 | pf = &(*pf)->fx_next) | |
10936 | assert (*pf != NULL); | |
10937 | ||
10938 | *pf = l->fixp->fx_next; | |
10939 | ||
10940 | l->fixp->fx_next = f; | |
10941 | if (prev == NULL) | |
10942 | seginfo->fix_root = l->fixp; | |
10943 | else | |
10944 | prev->fx_next = l->fixp; | |
10945 | ||
10946 | break; | |
10947 | } | |
10948 | ||
10949 | prev = f; | |
10950 | } | |
10951 | ||
10952 | if (f != NULL) | |
10953 | break; | |
10954 | ||
10955 | #if 0 /* GCC code motion plus incomplete dead code elimination | |
10956 | can leave a %hi without a %lo. */ | |
10957 | if (pass == 1) | |
10958 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, | |
10959 | _("Unmatched %%hi reloc")); | |
10960 | #endif | |
10961 | } | |
10962 | } | |
10963 | } | |
10964 | ||
10965 | /* When generating embedded PIC code we need to use a special | |
10966 | relocation to represent the difference of two symbols in the .text | |
10967 | section (switch tables use a difference of this sort). See | |
10968 | include/coff/mips.h for details. This macro checks whether this | |
10969 | fixup requires the special reloc. */ | |
10970 | #define SWITCH_TABLE(fixp) \ | |
10971 | ((fixp)->fx_r_type == BFD_RELOC_32 \ | |
bb2d6cd7 | 10972 | && OUTPUT_FLAVOR != bfd_target_elf_flavour \ |
252b5132 RH |
10973 | && (fixp)->fx_addsy != NULL \ |
10974 | && (fixp)->fx_subsy != NULL \ | |
10975 | && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \ | |
10976 | && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section) | |
10977 | ||
10978 | /* When generating embedded PIC code we must keep all PC relative | |
10979 | relocations, in case the linker has to relax a call. We also need | |
f6688943 TS |
10980 | to keep relocations for switch table entries. |
10981 | ||
10982 | We may have combined relocations without symbols in the N32/N64 ABI. | |
10983 | We have to prevent gas from dropping them. */ | |
252b5132 | 10984 | |
252b5132 | 10985 | int |
17a2f251 | 10986 | mips_force_relocation (fixS *fixp) |
252b5132 | 10987 | { |
ae6063d4 | 10988 | if (generic_force_reloc (fixp)) |
252b5132 RH |
10989 | return 1; |
10990 | ||
f6688943 TS |
10991 | if (HAVE_NEWABI |
10992 | && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr | |
10993 | && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB | |
10994 | || fixp->fx_r_type == BFD_RELOC_HI16_S | |
10995 | || fixp->fx_r_type == BFD_RELOC_LO16)) | |
10996 | return 1; | |
10997 | ||
252b5132 RH |
10998 | return (mips_pic == EMBEDDED_PIC |
10999 | && (fixp->fx_pcrel | |
11000 | || SWITCH_TABLE (fixp) | |
11001 | || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S | |
11002 | || fixp->fx_r_type == BFD_RELOC_PCREL_LO16)); | |
11003 | } | |
11004 | ||
45f8dfe8 AO |
11005 | /* This hook is called before a fix is simplified. We don't really |
11006 | decide whether to skip a fix here. Rather, we turn global symbols | |
11007 | used as branch targets into local symbols, such that they undergo | |
11008 | simplification. We can only do this if the symbol is defined and | |
11009 | it is in the same section as the branch. If this doesn't hold, we | |
11010 | emit a better error message than just saying the relocation is not | |
11011 | valid for the selected object format. | |
11012 | ||
11013 | FIXP is the fix-up we're going to try to simplify, SEG is the | |
11014 | segment in which the fix up occurs. The return value should be | |
11015 | non-zero to indicate the fix-up is valid for further | |
11016 | simplifications. */ | |
11017 | ||
11018 | int | |
17a2f251 | 11019 | mips_validate_fix (struct fix *fixP, asection *seg) |
45f8dfe8 AO |
11020 | { |
11021 | /* There's a lot of discussion on whether it should be possible to | |
11022 | use R_MIPS_PC16 to represent branch relocations. The outcome | |
11023 | seems to be that it can, but gas/bfd are very broken in creating | |
11024 | RELA relocations for this, so for now we only accept branches to | |
11025 | symbols in the same section. Anything else is of dubious value, | |
11026 | since there's no guarantee that at link time the symbol would be | |
11027 | in range. Even for branches to local symbols this is arguably | |
11028 | wrong, since it we assume the symbol is not going to be | |
11029 | overridden, which should be possible per ELF library semantics, | |
11030 | but then, there isn't a dynamic relocation that could be used to | |
11031 | this effect, and the target would likely be out of range as well. | |
11032 | ||
11033 | Unfortunately, it seems that there is too much code out there | |
11034 | that relies on branches to symbols that are global to be resolved | |
11035 | as if they were local, like the IRIX tools do, so we do it as | |
11036 | well, but with a warning so that people are reminded to fix their | |
11037 | code. If we ever get back to using R_MIPS_PC16 for branch | |
11038 | targets, this entire block should go away (and probably the | |
11039 | whole function). */ | |
11040 | ||
11041 | if (fixP->fx_r_type == BFD_RELOC_16_PCREL_S2 | |
11042 | && (((OUTPUT_FLAVOR == bfd_target_ecoff_flavour | |
11043 | || OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
11044 | && mips_pic != EMBEDDED_PIC) | |
11045 | || bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16_PCREL_S2) == NULL) | |
11046 | && fixP->fx_addsy) | |
11047 | { | |
11048 | if (! S_IS_DEFINED (fixP->fx_addsy)) | |
11049 | { | |
11050 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11051 | _("Cannot branch to undefined symbol.")); | |
11052 | /* Avoid any further errors about this fixup. */ | |
11053 | fixP->fx_done = 1; | |
11054 | } | |
11055 | else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
11056 | { | |
11057 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11058 | _("Cannot branch to symbol in another section.")); | |
11059 | fixP->fx_done = 1; | |
11060 | } | |
11061 | else if (S_IS_EXTERNAL (fixP->fx_addsy)) | |
11062 | { | |
11063 | symbolS *sym = fixP->fx_addsy; | |
11064 | ||
115695a8 CD |
11065 | if (mips_pic == SVR4_PIC) |
11066 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
11067 | _("Pretending global symbol used as branch target is local.")); | |
45f8dfe8 AO |
11068 | |
11069 | fixP->fx_addsy = symbol_create (S_GET_NAME (sym), | |
11070 | S_GET_SEGMENT (sym), | |
11071 | S_GET_VALUE (sym), | |
11072 | symbol_get_frag (sym)); | |
11073 | copy_symbol_attributes (fixP->fx_addsy, sym); | |
11074 | S_CLEAR_EXTERNAL (fixP->fx_addsy); | |
11075 | assert (symbol_resolved_p (sym)); | |
11076 | symbol_mark_resolved (fixP->fx_addsy); | |
11077 | } | |
11078 | } | |
11079 | ||
11080 | return 1; | |
11081 | } | |
11082 | ||
252b5132 RH |
11083 | /* Apply a fixup to the object file. */ |
11084 | ||
94f592af | 11085 | void |
17a2f251 | 11086 | md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 11087 | { |
874e8986 | 11088 | bfd_byte *buf; |
98aa84af | 11089 | long insn; |
ed6fb7bd | 11090 | static int previous_fx_r_type = 0; |
a7ebbfdf | 11091 | reloc_howto_type *howto; |
252b5132 | 11092 | |
a7ebbfdf TS |
11093 | /* We ignore generic BFD relocations we don't know about. */ |
11094 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
11095 | if (! howto) | |
11096 | return; | |
65551fa4 | 11097 | |
252b5132 RH |
11098 | assert (fixP->fx_size == 4 |
11099 | || fixP->fx_r_type == BFD_RELOC_16 | |
11100 | || fixP->fx_r_type == BFD_RELOC_64 | |
f6688943 TS |
11101 | || fixP->fx_r_type == BFD_RELOC_CTOR |
11102 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
252b5132 | 11103 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
a7ebbfdf | 11104 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY); |
252b5132 | 11105 | |
a7ebbfdf | 11106 | buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); |
252b5132 | 11107 | |
ed6fb7bd SC |
11108 | /* We are not done if this is a composite relocation to set up gp. */ |
11109 | if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel | |
11110 | && !(fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
10181a0d AO |
11111 | || (fixP->fx_r_type == BFD_RELOC_64 |
11112 | && (previous_fx_r_type == BFD_RELOC_GPREL32 | |
11113 | || previous_fx_r_type == BFD_RELOC_GPREL16)) | |
ed6fb7bd SC |
11114 | || (previous_fx_r_type == BFD_RELOC_MIPS_SUB |
11115 | && (fixP->fx_r_type == BFD_RELOC_HI16_S | |
11116 | || fixP->fx_r_type == BFD_RELOC_LO16)))) | |
252b5132 | 11117 | fixP->fx_done = 1; |
ed6fb7bd | 11118 | previous_fx_r_type = fixP->fx_r_type; |
252b5132 RH |
11119 | |
11120 | switch (fixP->fx_r_type) | |
11121 | { | |
11122 | case BFD_RELOC_MIPS_JMP: | |
e369bcce TS |
11123 | case BFD_RELOC_MIPS_SHIFT5: |
11124 | case BFD_RELOC_MIPS_SHIFT6: | |
11125 | case BFD_RELOC_MIPS_GOT_DISP: | |
11126 | case BFD_RELOC_MIPS_GOT_PAGE: | |
11127 | case BFD_RELOC_MIPS_GOT_OFST: | |
11128 | case BFD_RELOC_MIPS_SUB: | |
11129 | case BFD_RELOC_MIPS_INSERT_A: | |
11130 | case BFD_RELOC_MIPS_INSERT_B: | |
11131 | case BFD_RELOC_MIPS_DELETE: | |
11132 | case BFD_RELOC_MIPS_HIGHEST: | |
11133 | case BFD_RELOC_MIPS_HIGHER: | |
11134 | case BFD_RELOC_MIPS_SCN_DISP: | |
11135 | case BFD_RELOC_MIPS_REL16: | |
11136 | case BFD_RELOC_MIPS_RELGOT: | |
11137 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
11138 | case BFD_RELOC_HI16: |
11139 | case BFD_RELOC_HI16_S: | |
cdf6fd85 | 11140 | case BFD_RELOC_GPREL16: |
252b5132 RH |
11141 | case BFD_RELOC_MIPS_LITERAL: |
11142 | case BFD_RELOC_MIPS_CALL16: | |
11143 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 11144 | case BFD_RELOC_GPREL32: |
252b5132 RH |
11145 | case BFD_RELOC_MIPS_GOT_HI16: |
11146 | case BFD_RELOC_MIPS_GOT_LO16: | |
11147 | case BFD_RELOC_MIPS_CALL_HI16: | |
11148 | case BFD_RELOC_MIPS_CALL_LO16: | |
11149 | case BFD_RELOC_MIPS16_GPREL: | |
11150 | if (fixP->fx_pcrel) | |
11151 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11152 | _("Invalid PC relative reloc")); | |
11153 | /* Nothing needed to do. The value comes from the reloc entry */ | |
11154 | break; | |
11155 | ||
11156 | case BFD_RELOC_MIPS16_JMP: | |
11157 | /* We currently always generate a reloc against a symbol, which | |
11158 | means that we don't want an addend even if the symbol is | |
11159 | defined. */ | |
a7ebbfdf | 11160 | *valP = 0; |
252b5132 RH |
11161 | break; |
11162 | ||
11163 | case BFD_RELOC_PCREL_HI16_S: | |
11164 | /* The addend for this is tricky if it is internal, so we just | |
11165 | do everything here rather than in bfd_install_relocation. */ | |
a7ebbfdf | 11166 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && !fixP->fx_done) |
bb2d6cd7 GK |
11167 | break; |
11168 | if (fixP->fx_addsy | |
11169 | && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0) | |
252b5132 RH |
11170 | { |
11171 | /* For an external symbol adjust by the address to make it | |
11172 | pcrel_offset. We use the address of the RELLO reloc | |
11173 | which follows this one. */ | |
a7ebbfdf | 11174 | *valP += (fixP->fx_next->fx_frag->fr_address |
252b5132 RH |
11175 | + fixP->fx_next->fx_where); |
11176 | } | |
a7ebbfdf | 11177 | *valP = ((*valP + 0x8000) >> 16) & 0xffff; |
252b5132 RH |
11178 | if (target_big_endian) |
11179 | buf += 2; | |
17a2f251 | 11180 | md_number_to_chars (buf, *valP, 2); |
252b5132 RH |
11181 | break; |
11182 | ||
11183 | case BFD_RELOC_PCREL_LO16: | |
11184 | /* The addend for this is tricky if it is internal, so we just | |
11185 | do everything here rather than in bfd_install_relocation. */ | |
a7ebbfdf | 11186 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && !fixP->fx_done) |
bb2d6cd7 GK |
11187 | break; |
11188 | if (fixP->fx_addsy | |
11189 | && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0) | |
a7ebbfdf | 11190 | *valP += fixP->fx_frag->fr_address + fixP->fx_where; |
252b5132 RH |
11191 | if (target_big_endian) |
11192 | buf += 2; | |
17a2f251 | 11193 | md_number_to_chars (buf, *valP, 2); |
252b5132 RH |
11194 | break; |
11195 | ||
11196 | case BFD_RELOC_64: | |
11197 | /* This is handled like BFD_RELOC_32, but we output a sign | |
11198 | extended value if we are only 32 bits. */ | |
11199 | if (fixP->fx_done | |
11200 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
11201 | { | |
11202 | if (8 <= sizeof (valueT)) | |
a7ebbfdf | 11203 | md_number_to_chars (buf, *valP, 8); |
252b5132 RH |
11204 | else |
11205 | { | |
a7ebbfdf | 11206 | valueT hiv; |
252b5132 | 11207 | |
a7ebbfdf | 11208 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
11209 | hiv = 0xffffffff; |
11210 | else | |
11211 | hiv = 0; | |
a7ebbfdf TS |
11212 | md_number_to_chars ((char *)(buf + target_big_endian ? 4 : 0), |
11213 | *valP, 4); | |
11214 | md_number_to_chars ((char *)(buf + target_big_endian ? 0 : 4), | |
11215 | hiv, 4); | |
252b5132 RH |
11216 | } |
11217 | } | |
11218 | break; | |
11219 | ||
056350c6 | 11220 | case BFD_RELOC_RVA: |
252b5132 RH |
11221 | case BFD_RELOC_32: |
11222 | /* If we are deleting this reloc entry, we must fill in the | |
11223 | value now. This can happen if we have a .word which is not | |
11224 | resolved when it appears but is later defined. We also need | |
11225 | to fill in the value if this is an embedded PIC switch table | |
11226 | entry. */ | |
11227 | if (fixP->fx_done | |
11228 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
a7ebbfdf | 11229 | md_number_to_chars (buf, *valP, 4); |
252b5132 RH |
11230 | break; |
11231 | ||
11232 | case BFD_RELOC_16: | |
11233 | /* If we are deleting this reloc entry, we must fill in the | |
11234 | value now. */ | |
11235 | assert (fixP->fx_size == 2); | |
11236 | if (fixP->fx_done) | |
a7ebbfdf | 11237 | md_number_to_chars (buf, *valP, 2); |
252b5132 RH |
11238 | break; |
11239 | ||
11240 | case BFD_RELOC_LO16: | |
11241 | /* When handling an embedded PIC switch statement, we can wind | |
11242 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
11243 | if (fixP->fx_done) | |
11244 | { | |
a7ebbfdf | 11245 | if (*valP + 0x8000 > 0xffff) |
252b5132 RH |
11246 | as_bad_where (fixP->fx_file, fixP->fx_line, |
11247 | _("relocation overflow")); | |
252b5132 RH |
11248 | if (target_big_endian) |
11249 | buf += 2; | |
17a2f251 | 11250 | md_number_to_chars (buf, *valP, 2); |
252b5132 RH |
11251 | } |
11252 | break; | |
11253 | ||
11254 | case BFD_RELOC_16_PCREL_S2: | |
a7ebbfdf | 11255 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 11256 | as_bad_where (fixP->fx_file, fixP->fx_line, |
a7ebbfdf | 11257 | _("Branch to odd address (%lx)"), (long) *valP); |
cb56d3d3 | 11258 | |
252b5132 RH |
11259 | /* |
11260 | * We need to save the bits in the instruction since fixup_segment() | |
11261 | * might be deleting the relocation entry (i.e., a branch within | |
11262 | * the current segment). | |
11263 | */ | |
a7ebbfdf | 11264 | if (! fixP->fx_done) |
bb2d6cd7 | 11265 | break; |
252b5132 RH |
11266 | |
11267 | /* update old instruction data */ | |
252b5132 RH |
11268 | if (target_big_endian) |
11269 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
11270 | else | |
11271 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
11272 | ||
a7ebbfdf TS |
11273 | if (*valP + 0x20000 <= 0x3ffff) |
11274 | { | |
11275 | insn |= (*valP >> 2) & 0xffff; | |
17a2f251 | 11276 | md_number_to_chars (buf, insn, 4); |
a7ebbfdf TS |
11277 | } |
11278 | else if (mips_pic == NO_PIC | |
11279 | && fixP->fx_done | |
11280 | && fixP->fx_frag->fr_address >= text_section->vma | |
11281 | && (fixP->fx_frag->fr_address | |
11282 | < text_section->vma + text_section->_raw_size) | |
11283 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
11284 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
11285 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
11286 | { |
11287 | /* The branch offset is too large. If this is an | |
11288 | unconditional branch, and we are not generating PIC code, | |
11289 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
11290 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
11291 | insn = 0x0c000000; /* jal */ | |
252b5132 | 11292 | else |
a7ebbfdf TS |
11293 | insn = 0x08000000; /* j */ |
11294 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
11295 | fixP->fx_done = 0; | |
11296 | fixP->fx_addsy = section_symbol (text_section); | |
11297 | *valP += md_pcrel_from (fixP); | |
17a2f251 | 11298 | md_number_to_chars (buf, insn, 4); |
a7ebbfdf TS |
11299 | } |
11300 | else | |
11301 | { | |
11302 | /* If we got here, we have branch-relaxation disabled, | |
11303 | and there's nothing we can do to fix this instruction | |
11304 | without turning it into a longer sequence. */ | |
11305 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11306 | _("Branch out of range")); | |
252b5132 | 11307 | } |
252b5132 RH |
11308 | break; |
11309 | ||
11310 | case BFD_RELOC_VTABLE_INHERIT: | |
11311 | fixP->fx_done = 0; | |
11312 | if (fixP->fx_addsy | |
11313 | && !S_IS_DEFINED (fixP->fx_addsy) | |
11314 | && !S_IS_WEAK (fixP->fx_addsy)) | |
11315 | S_SET_WEAK (fixP->fx_addsy); | |
11316 | break; | |
11317 | ||
11318 | case BFD_RELOC_VTABLE_ENTRY: | |
11319 | fixP->fx_done = 0; | |
11320 | break; | |
11321 | ||
11322 | default: | |
11323 | internalError (); | |
11324 | } | |
a7ebbfdf TS |
11325 | |
11326 | /* Remember value for tc_gen_reloc. */ | |
11327 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
11328 | } |
11329 | ||
11330 | #if 0 | |
11331 | void | |
17a2f251 | 11332 | printInsn (unsigned long oc) |
252b5132 RH |
11333 | { |
11334 | const struct mips_opcode *p; | |
11335 | int treg, sreg, dreg, shamt; | |
11336 | short imm; | |
11337 | const char *args; | |
11338 | int i; | |
11339 | ||
11340 | for (i = 0; i < NUMOPCODES; ++i) | |
11341 | { | |
11342 | p = &mips_opcodes[i]; | |
11343 | if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO)) | |
11344 | { | |
11345 | printf ("%08lx %s\t", oc, p->name); | |
11346 | treg = (oc >> 16) & 0x1f; | |
11347 | sreg = (oc >> 21) & 0x1f; | |
11348 | dreg = (oc >> 11) & 0x1f; | |
11349 | shamt = (oc >> 6) & 0x1f; | |
11350 | imm = oc; | |
11351 | for (args = p->args;; ++args) | |
11352 | { | |
11353 | switch (*args) | |
11354 | { | |
11355 | case '\0': | |
11356 | printf ("\n"); | |
11357 | break; | |
11358 | ||
11359 | case ',': | |
11360 | case '(': | |
11361 | case ')': | |
11362 | printf ("%c", *args); | |
11363 | continue; | |
11364 | ||
11365 | case 'r': | |
11366 | assert (treg == sreg); | |
11367 | printf ("$%d,$%d", treg, sreg); | |
11368 | continue; | |
11369 | ||
11370 | case 'd': | |
11371 | case 'G': | |
11372 | printf ("$%d", dreg); | |
11373 | continue; | |
11374 | ||
11375 | case 't': | |
11376 | case 'E': | |
11377 | printf ("$%d", treg); | |
11378 | continue; | |
11379 | ||
11380 | case 'k': | |
11381 | printf ("0x%x", treg); | |
11382 | continue; | |
11383 | ||
11384 | case 'b': | |
11385 | case 's': | |
11386 | printf ("$%d", sreg); | |
11387 | continue; | |
11388 | ||
11389 | case 'a': | |
11390 | printf ("0x%08lx", oc & 0x1ffffff); | |
11391 | continue; | |
11392 | ||
11393 | case 'i': | |
11394 | case 'j': | |
11395 | case 'o': | |
11396 | case 'u': | |
11397 | printf ("%d", imm); | |
11398 | continue; | |
11399 | ||
11400 | case '<': | |
11401 | case '>': | |
11402 | printf ("$%d", shamt); | |
11403 | continue; | |
11404 | ||
11405 | default: | |
11406 | internalError (); | |
11407 | } | |
11408 | break; | |
11409 | } | |
11410 | return; | |
11411 | } | |
11412 | } | |
11413 | printf (_("%08lx UNDEFINED\n"), oc); | |
11414 | } | |
11415 | #endif | |
11416 | ||
11417 | static symbolS * | |
17a2f251 | 11418 | get_symbol (void) |
252b5132 RH |
11419 | { |
11420 | int c; | |
11421 | char *name; | |
11422 | symbolS *p; | |
11423 | ||
11424 | name = input_line_pointer; | |
11425 | c = get_symbol_end (); | |
11426 | p = (symbolS *) symbol_find_or_make (name); | |
11427 | *input_line_pointer = c; | |
11428 | return p; | |
11429 | } | |
11430 | ||
11431 | /* Align the current frag to a given power of two. The MIPS assembler | |
11432 | also automatically adjusts any preceding label. */ | |
11433 | ||
11434 | static void | |
17a2f251 | 11435 | mips_align (int to, int fill, symbolS *label) |
252b5132 | 11436 | { |
b34976b6 | 11437 | mips_emit_delays (FALSE); |
252b5132 RH |
11438 | frag_align (to, fill, 0); |
11439 | record_alignment (now_seg, to); | |
11440 | if (label != NULL) | |
11441 | { | |
11442 | assert (S_GET_SEGMENT (label) == now_seg); | |
49309057 | 11443 | symbol_set_frag (label, frag_now); |
252b5132 RH |
11444 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
11445 | } | |
11446 | } | |
11447 | ||
11448 | /* Align to a given power of two. .align 0 turns off the automatic | |
11449 | alignment used by the data creating pseudo-ops. */ | |
11450 | ||
11451 | static void | |
17a2f251 | 11452 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11453 | { |
11454 | register int temp; | |
11455 | register long temp_fill; | |
11456 | long max_alignment = 15; | |
11457 | ||
11458 | /* | |
11459 | ||
67c1ffbe | 11460 | o Note that the assembler pulls down any immediately preceding label |
252b5132 RH |
11461 | to the aligned address. |
11462 | o It's not documented but auto alignment is reinstated by | |
11463 | a .align pseudo instruction. | |
11464 | o Note also that after auto alignment is turned off the mips assembler | |
11465 | issues an error on attempt to assemble an improperly aligned data item. | |
11466 | We don't. | |
11467 | ||
11468 | */ | |
11469 | ||
11470 | temp = get_absolute_expression (); | |
11471 | if (temp > max_alignment) | |
11472 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
11473 | else if (temp < 0) | |
11474 | { | |
11475 | as_warn (_("Alignment negative: 0 assumed.")); | |
11476 | temp = 0; | |
11477 | } | |
11478 | if (*input_line_pointer == ',') | |
11479 | { | |
f9419b05 | 11480 | ++input_line_pointer; |
252b5132 RH |
11481 | temp_fill = get_absolute_expression (); |
11482 | } | |
11483 | else | |
11484 | temp_fill = 0; | |
11485 | if (temp) | |
11486 | { | |
11487 | auto_align = 1; | |
11488 | mips_align (temp, (int) temp_fill, | |
11489 | insn_labels != NULL ? insn_labels->label : NULL); | |
11490 | } | |
11491 | else | |
11492 | { | |
11493 | auto_align = 0; | |
11494 | } | |
11495 | ||
11496 | demand_empty_rest_of_line (); | |
11497 | } | |
11498 | ||
11499 | void | |
17a2f251 | 11500 | mips_flush_pending_output (void) |
252b5132 | 11501 | { |
b34976b6 | 11502 | mips_emit_delays (FALSE); |
252b5132 RH |
11503 | mips_clear_insn_labels (); |
11504 | } | |
11505 | ||
11506 | static void | |
17a2f251 | 11507 | s_change_sec (int sec) |
252b5132 RH |
11508 | { |
11509 | segT seg; | |
11510 | ||
11511 | /* When generating embedded PIC code, we only use the .text, .lit8, | |
11512 | .sdata and .sbss sections. We change the .data and .rdata | |
11513 | pseudo-ops to use .sdata. */ | |
11514 | if (mips_pic == EMBEDDED_PIC | |
11515 | && (sec == 'd' || sec == 'r')) | |
11516 | sec = 's'; | |
11517 | ||
11518 | #ifdef OBJ_ELF | |
11519 | /* The ELF backend needs to know that we are changing sections, so | |
11520 | that .previous works correctly. We could do something like check | |
b6ff326e | 11521 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
11522 | as it would not be appropriate to use it in the section changing |
11523 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
11524 | This should be cleaner, somehow. */ | |
11525 | obj_elf_section_change_hook (); | |
11526 | #endif | |
11527 | ||
b34976b6 | 11528 | mips_emit_delays (FALSE); |
252b5132 RH |
11529 | switch (sec) |
11530 | { | |
11531 | case 't': | |
11532 | s_text (0); | |
11533 | break; | |
11534 | case 'd': | |
11535 | s_data (0); | |
11536 | break; | |
11537 | case 'b': | |
11538 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
11539 | demand_empty_rest_of_line (); | |
11540 | break; | |
11541 | ||
11542 | case 'r': | |
11543 | if (USE_GLOBAL_POINTER_OPT) | |
11544 | { | |
11545 | seg = subseg_new (RDATA_SECTION_NAME, | |
11546 | (subsegT) get_absolute_expression ()); | |
11547 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
11548 | { | |
11549 | bfd_set_section_flags (stdoutput, seg, | |
11550 | (SEC_ALLOC | |
11551 | | SEC_LOAD | |
11552 | | SEC_READONLY | |
11553 | | SEC_RELOC | |
11554 | | SEC_DATA)); | |
11555 | if (strcmp (TARGET_OS, "elf") != 0) | |
e799a695 | 11556 | record_alignment (seg, 4); |
252b5132 RH |
11557 | } |
11558 | demand_empty_rest_of_line (); | |
11559 | } | |
11560 | else | |
11561 | { | |
11562 | as_bad (_("No read only data section in this object file format")); | |
11563 | demand_empty_rest_of_line (); | |
11564 | return; | |
11565 | } | |
11566 | break; | |
11567 | ||
11568 | case 's': | |
11569 | if (USE_GLOBAL_POINTER_OPT) | |
11570 | { | |
11571 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); | |
11572 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
11573 | { | |
11574 | bfd_set_section_flags (stdoutput, seg, | |
11575 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | |
11576 | | SEC_DATA); | |
11577 | if (strcmp (TARGET_OS, "elf") != 0) | |
e799a695 | 11578 | record_alignment (seg, 4); |
252b5132 RH |
11579 | } |
11580 | demand_empty_rest_of_line (); | |
11581 | break; | |
11582 | } | |
11583 | else | |
11584 | { | |
11585 | as_bad (_("Global pointers not supported; recompile -G 0")); | |
11586 | demand_empty_rest_of_line (); | |
11587 | return; | |
11588 | } | |
11589 | } | |
11590 | ||
11591 | auto_align = 1; | |
11592 | } | |
b34976b6 | 11593 | |
cca86cc8 | 11594 | void |
17a2f251 | 11595 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 11596 | { |
7ed4a06a | 11597 | #ifdef OBJ_ELF |
cca86cc8 SC |
11598 | char *section_name; |
11599 | char c; | |
684022ea | 11600 | char next_c = 0; |
cca86cc8 SC |
11601 | int section_type; |
11602 | int section_flag; | |
11603 | int section_entry_size; | |
11604 | int section_alignment; | |
b34976b6 | 11605 | |
7ed4a06a TS |
11606 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
11607 | return; | |
11608 | ||
cca86cc8 SC |
11609 | section_name = input_line_pointer; |
11610 | c = get_symbol_end (); | |
a816d1ed AO |
11611 | if (c) |
11612 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 11613 | |
4cf0dd0d TS |
11614 | /* Do we have .section Name<,"flags">? */ |
11615 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 11616 | { |
4cf0dd0d TS |
11617 | /* just after name is now '\0'. */ |
11618 | *input_line_pointer = c; | |
cca86cc8 SC |
11619 | input_line_pointer = section_name; |
11620 | obj_elf_section (ignore); | |
11621 | return; | |
11622 | } | |
11623 | input_line_pointer++; | |
11624 | ||
11625 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
11626 | if (c == ',') | |
11627 | section_type = get_absolute_expression (); | |
11628 | else | |
11629 | section_type = 0; | |
11630 | if (*input_line_pointer++ == ',') | |
11631 | section_flag = get_absolute_expression (); | |
11632 | else | |
11633 | section_flag = 0; | |
11634 | if (*input_line_pointer++ == ',') | |
11635 | section_entry_size = get_absolute_expression (); | |
11636 | else | |
11637 | section_entry_size = 0; | |
11638 | if (*input_line_pointer++ == ',') | |
11639 | section_alignment = get_absolute_expression (); | |
11640 | else | |
11641 | section_alignment = 0; | |
11642 | ||
a816d1ed AO |
11643 | section_name = xstrdup (section_name); |
11644 | ||
8ab8a5c8 RS |
11645 | /* When using the generic form of .section (as implemented by obj-elf.c), |
11646 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
11647 | traditionally had to fall back on the more common @progbits instead. | |
11648 | ||
11649 | There's nothing really harmful in this, since bfd will correct | |
11650 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
11651 | means that, for backwards compatibiltiy, the special_section entries | |
11652 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. | |
11653 | ||
11654 | Even so, we shouldn't force users of the MIPS .section syntax to | |
11655 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
11656 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
11657 | generic type-checking code. */ | |
11658 | if (section_type == SHT_MIPS_DWARF) | |
11659 | section_type = SHT_PROGBITS; | |
11660 | ||
cca86cc8 SC |
11661 | obj_elf_change_section (section_name, section_type, section_flag, |
11662 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
11663 | |
11664 | if (now_seg->name != section_name) | |
11665 | free (section_name); | |
7ed4a06a | 11666 | #endif /* OBJ_ELF */ |
cca86cc8 | 11667 | } |
252b5132 RH |
11668 | |
11669 | void | |
17a2f251 | 11670 | mips_enable_auto_align (void) |
252b5132 RH |
11671 | { |
11672 | auto_align = 1; | |
11673 | } | |
11674 | ||
11675 | static void | |
17a2f251 | 11676 | s_cons (int log_size) |
252b5132 RH |
11677 | { |
11678 | symbolS *label; | |
11679 | ||
11680 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
b34976b6 | 11681 | mips_emit_delays (FALSE); |
252b5132 RH |
11682 | if (log_size > 0 && auto_align) |
11683 | mips_align (log_size, 0, label); | |
11684 | mips_clear_insn_labels (); | |
11685 | cons (1 << log_size); | |
11686 | } | |
11687 | ||
11688 | static void | |
17a2f251 | 11689 | s_float_cons (int type) |
252b5132 RH |
11690 | { |
11691 | symbolS *label; | |
11692 | ||
11693 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
11694 | ||
b34976b6 | 11695 | mips_emit_delays (FALSE); |
252b5132 RH |
11696 | |
11697 | if (auto_align) | |
49309057 ILT |
11698 | { |
11699 | if (type == 'd') | |
11700 | mips_align (3, 0, label); | |
11701 | else | |
11702 | mips_align (2, 0, label); | |
11703 | } | |
252b5132 RH |
11704 | |
11705 | mips_clear_insn_labels (); | |
11706 | ||
11707 | float_cons (type); | |
11708 | } | |
11709 | ||
11710 | /* Handle .globl. We need to override it because on Irix 5 you are | |
11711 | permitted to say | |
11712 | .globl foo .text | |
11713 | where foo is an undefined symbol, to mean that foo should be | |
11714 | considered to be the address of a function. */ | |
11715 | ||
11716 | static void | |
17a2f251 | 11717 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11718 | { |
11719 | char *name; | |
11720 | int c; | |
11721 | symbolS *symbolP; | |
11722 | flagword flag; | |
11723 | ||
11724 | name = input_line_pointer; | |
11725 | c = get_symbol_end (); | |
11726 | symbolP = symbol_find_or_make (name); | |
11727 | *input_line_pointer = c; | |
11728 | SKIP_WHITESPACE (); | |
11729 | ||
11730 | /* On Irix 5, every global symbol that is not explicitly labelled as | |
11731 | being a function is apparently labelled as being an object. */ | |
11732 | flag = BSF_OBJECT; | |
11733 | ||
11734 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
11735 | { | |
11736 | char *secname; | |
11737 | asection *sec; | |
11738 | ||
11739 | secname = input_line_pointer; | |
11740 | c = get_symbol_end (); | |
11741 | sec = bfd_get_section_by_name (stdoutput, secname); | |
11742 | if (sec == NULL) | |
11743 | as_bad (_("%s: no such section"), secname); | |
11744 | *input_line_pointer = c; | |
11745 | ||
11746 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
11747 | flag = BSF_FUNCTION; | |
11748 | } | |
11749 | ||
49309057 | 11750 | symbol_get_bfdsym (symbolP)->flags |= flag; |
252b5132 RH |
11751 | |
11752 | S_SET_EXTERNAL (symbolP); | |
11753 | demand_empty_rest_of_line (); | |
11754 | } | |
11755 | ||
11756 | static void | |
17a2f251 | 11757 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11758 | { |
11759 | char *opt; | |
11760 | char c; | |
11761 | ||
11762 | opt = input_line_pointer; | |
11763 | c = get_symbol_end (); | |
11764 | ||
11765 | if (*opt == 'O') | |
11766 | { | |
11767 | /* FIXME: What does this mean? */ | |
11768 | } | |
11769 | else if (strncmp (opt, "pic", 3) == 0) | |
11770 | { | |
11771 | int i; | |
11772 | ||
11773 | i = atoi (opt + 3); | |
11774 | if (i == 0) | |
11775 | mips_pic = NO_PIC; | |
11776 | else if (i == 2) | |
143d77c5 | 11777 | { |
252b5132 | 11778 | mips_pic = SVR4_PIC; |
143d77c5 EC |
11779 | mips_abicalls = TRUE; |
11780 | } | |
252b5132 RH |
11781 | else |
11782 | as_bad (_(".option pic%d not supported"), i); | |
11783 | ||
11784 | if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC) | |
11785 | { | |
11786 | if (g_switch_seen && g_switch_value != 0) | |
11787 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
11788 | g_switch_value = 0; | |
11789 | bfd_set_gp_size (stdoutput, 0); | |
11790 | } | |
11791 | } | |
11792 | else | |
11793 | as_warn (_("Unrecognized option \"%s\""), opt); | |
11794 | ||
11795 | *input_line_pointer = c; | |
11796 | demand_empty_rest_of_line (); | |
11797 | } | |
11798 | ||
11799 | /* This structure is used to hold a stack of .set values. */ | |
11800 | ||
e972090a NC |
11801 | struct mips_option_stack |
11802 | { | |
252b5132 RH |
11803 | struct mips_option_stack *next; |
11804 | struct mips_set_options options; | |
11805 | }; | |
11806 | ||
11807 | static struct mips_option_stack *mips_opts_stack; | |
11808 | ||
11809 | /* Handle the .set pseudo-op. */ | |
11810 | ||
11811 | static void | |
17a2f251 | 11812 | s_mipsset (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11813 | { |
11814 | char *name = input_line_pointer, ch; | |
11815 | ||
11816 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 11817 | ++input_line_pointer; |
252b5132 RH |
11818 | ch = *input_line_pointer; |
11819 | *input_line_pointer = '\0'; | |
11820 | ||
11821 | if (strcmp (name, "reorder") == 0) | |
11822 | { | |
11823 | if (mips_opts.noreorder && prev_nop_frag != NULL) | |
11824 | { | |
11825 | /* If we still have pending nops, we can discard them. The | |
11826 | usual nop handling will insert any that are still | |
bdaaa2e1 | 11827 | needed. */ |
252b5132 RH |
11828 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds |
11829 | * (mips_opts.mips16 ? 2 : 4)); | |
11830 | prev_nop_frag = NULL; | |
11831 | } | |
11832 | mips_opts.noreorder = 0; | |
11833 | } | |
11834 | else if (strcmp (name, "noreorder") == 0) | |
11835 | { | |
b34976b6 | 11836 | mips_emit_delays (TRUE); |
252b5132 RH |
11837 | mips_opts.noreorder = 1; |
11838 | mips_any_noreorder = 1; | |
11839 | } | |
11840 | else if (strcmp (name, "at") == 0) | |
11841 | { | |
11842 | mips_opts.noat = 0; | |
11843 | } | |
11844 | else if (strcmp (name, "noat") == 0) | |
11845 | { | |
11846 | mips_opts.noat = 1; | |
11847 | } | |
11848 | else if (strcmp (name, "macro") == 0) | |
11849 | { | |
11850 | mips_opts.warn_about_macros = 0; | |
11851 | } | |
11852 | else if (strcmp (name, "nomacro") == 0) | |
11853 | { | |
11854 | if (mips_opts.noreorder == 0) | |
11855 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
11856 | mips_opts.warn_about_macros = 1; | |
11857 | } | |
11858 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
11859 | { | |
11860 | mips_opts.nomove = 0; | |
11861 | } | |
11862 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
11863 | { | |
11864 | mips_opts.nomove = 1; | |
11865 | } | |
11866 | else if (strcmp (name, "bopt") == 0) | |
11867 | { | |
11868 | mips_opts.nobopt = 0; | |
11869 | } | |
11870 | else if (strcmp (name, "nobopt") == 0) | |
11871 | { | |
11872 | mips_opts.nobopt = 1; | |
11873 | } | |
11874 | else if (strcmp (name, "mips16") == 0 | |
11875 | || strcmp (name, "MIPS-16") == 0) | |
11876 | mips_opts.mips16 = 1; | |
11877 | else if (strcmp (name, "nomips16") == 0 | |
11878 | || strcmp (name, "noMIPS-16") == 0) | |
11879 | mips_opts.mips16 = 0; | |
1f25f5d3 CD |
11880 | else if (strcmp (name, "mips3d") == 0) |
11881 | mips_opts.ase_mips3d = 1; | |
11882 | else if (strcmp (name, "nomips3d") == 0) | |
11883 | mips_opts.ase_mips3d = 0; | |
a4672219 TS |
11884 | else if (strcmp (name, "mdmx") == 0) |
11885 | mips_opts.ase_mdmx = 1; | |
11886 | else if (strcmp (name, "nomdmx") == 0) | |
11887 | mips_opts.ase_mdmx = 0; | |
1a2c1fad | 11888 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 11889 | { |
af7ee8bf | 11890 | int reset = 0; |
252b5132 | 11891 | |
1a2c1fad CD |
11892 | /* Permit the user to change the ISA and architecture on the fly. |
11893 | Needless to say, misuse can cause serious problems. */ | |
af7ee8bf CD |
11894 | if (strcmp (name, "mips0") == 0) |
11895 | { | |
11896 | reset = 1; | |
11897 | mips_opts.isa = file_mips_isa; | |
11898 | } | |
11899 | else if (strcmp (name, "mips1") == 0) | |
11900 | mips_opts.isa = ISA_MIPS1; | |
11901 | else if (strcmp (name, "mips2") == 0) | |
11902 | mips_opts.isa = ISA_MIPS2; | |
11903 | else if (strcmp (name, "mips3") == 0) | |
11904 | mips_opts.isa = ISA_MIPS3; | |
11905 | else if (strcmp (name, "mips4") == 0) | |
11906 | mips_opts.isa = ISA_MIPS4; | |
11907 | else if (strcmp (name, "mips5") == 0) | |
11908 | mips_opts.isa = ISA_MIPS5; | |
11909 | else if (strcmp (name, "mips32") == 0) | |
11910 | mips_opts.isa = ISA_MIPS32; | |
11911 | else if (strcmp (name, "mips32r2") == 0) | |
11912 | mips_opts.isa = ISA_MIPS32R2; | |
11913 | else if (strcmp (name, "mips64") == 0) | |
11914 | mips_opts.isa = ISA_MIPS64; | |
5f74bc13 CD |
11915 | else if (strcmp (name, "mips64r2") == 0) |
11916 | mips_opts.isa = ISA_MIPS64R2; | |
1a2c1fad CD |
11917 | else if (strcmp (name, "arch=default") == 0) |
11918 | { | |
11919 | reset = 1; | |
11920 | mips_opts.arch = file_mips_arch; | |
11921 | mips_opts.isa = file_mips_isa; | |
11922 | } | |
11923 | else if (strncmp (name, "arch=", 5) == 0) | |
11924 | { | |
11925 | const struct mips_cpu_info *p; | |
11926 | ||
11927 | p = mips_parse_cpu("internal use", name + 5); | |
11928 | if (!p) | |
11929 | as_bad (_("unknown architecture %s"), name + 5); | |
11930 | else | |
11931 | { | |
11932 | mips_opts.arch = p->cpu; | |
11933 | mips_opts.isa = p->isa; | |
11934 | } | |
11935 | } | |
af7ee8bf CD |
11936 | else |
11937 | as_bad (_("unknown ISA level %s"), name + 4); | |
11938 | ||
11939 | switch (mips_opts.isa) | |
98d3f06f KH |
11940 | { |
11941 | case 0: | |
98d3f06f | 11942 | break; |
af7ee8bf CD |
11943 | case ISA_MIPS1: |
11944 | case ISA_MIPS2: | |
11945 | case ISA_MIPS32: | |
11946 | case ISA_MIPS32R2: | |
98d3f06f KH |
11947 | mips_opts.gp32 = 1; |
11948 | mips_opts.fp32 = 1; | |
11949 | break; | |
af7ee8bf CD |
11950 | case ISA_MIPS3: |
11951 | case ISA_MIPS4: | |
11952 | case ISA_MIPS5: | |
11953 | case ISA_MIPS64: | |
5f74bc13 | 11954 | case ISA_MIPS64R2: |
98d3f06f KH |
11955 | mips_opts.gp32 = 0; |
11956 | mips_opts.fp32 = 0; | |
11957 | break; | |
11958 | default: | |
11959 | as_bad (_("unknown ISA level %s"), name + 4); | |
11960 | break; | |
11961 | } | |
af7ee8bf | 11962 | if (reset) |
98d3f06f | 11963 | { |
af7ee8bf CD |
11964 | mips_opts.gp32 = file_mips_gp32; |
11965 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 11966 | } |
252b5132 RH |
11967 | } |
11968 | else if (strcmp (name, "autoextend") == 0) | |
11969 | mips_opts.noautoextend = 0; | |
11970 | else if (strcmp (name, "noautoextend") == 0) | |
11971 | mips_opts.noautoextend = 1; | |
11972 | else if (strcmp (name, "push") == 0) | |
11973 | { | |
11974 | struct mips_option_stack *s; | |
11975 | ||
11976 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
11977 | s->next = mips_opts_stack; | |
11978 | s->options = mips_opts; | |
11979 | mips_opts_stack = s; | |
11980 | } | |
11981 | else if (strcmp (name, "pop") == 0) | |
11982 | { | |
11983 | struct mips_option_stack *s; | |
11984 | ||
11985 | s = mips_opts_stack; | |
11986 | if (s == NULL) | |
11987 | as_bad (_(".set pop with no .set push")); | |
11988 | else | |
11989 | { | |
11990 | /* If we're changing the reorder mode we need to handle | |
11991 | delay slots correctly. */ | |
11992 | if (s->options.noreorder && ! mips_opts.noreorder) | |
b34976b6 | 11993 | mips_emit_delays (TRUE); |
252b5132 RH |
11994 | else if (! s->options.noreorder && mips_opts.noreorder) |
11995 | { | |
11996 | if (prev_nop_frag != NULL) | |
11997 | { | |
11998 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds | |
11999 | * (mips_opts.mips16 ? 2 : 4)); | |
12000 | prev_nop_frag = NULL; | |
12001 | } | |
12002 | } | |
12003 | ||
12004 | mips_opts = s->options; | |
12005 | mips_opts_stack = s->next; | |
12006 | free (s); | |
12007 | } | |
12008 | } | |
12009 | else | |
12010 | { | |
12011 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
12012 | } | |
12013 | *input_line_pointer = ch; | |
12014 | demand_empty_rest_of_line (); | |
12015 | } | |
12016 | ||
12017 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
12018 | .option pic2. It means to generate SVR4 PIC calls. */ | |
12019 | ||
12020 | static void | |
17a2f251 | 12021 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12022 | { |
12023 | mips_pic = SVR4_PIC; | |
143d77c5 | 12024 | mips_abicalls = TRUE; |
252b5132 RH |
12025 | if (USE_GLOBAL_POINTER_OPT) |
12026 | { | |
12027 | if (g_switch_seen && g_switch_value != 0) | |
12028 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
12029 | g_switch_value = 0; | |
12030 | } | |
12031 | bfd_set_gp_size (stdoutput, 0); | |
12032 | demand_empty_rest_of_line (); | |
12033 | } | |
12034 | ||
12035 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
12036 | PIC code. It sets the $gp register for the function based on the | |
12037 | function address, which is in the register named in the argument. | |
12038 | This uses a relocation against _gp_disp, which is handled specially | |
12039 | by the linker. The result is: | |
12040 | lui $gp,%hi(_gp_disp) | |
12041 | addiu $gp,$gp,%lo(_gp_disp) | |
12042 | addu $gp,$gp,.cpload argument | |
12043 | The .cpload argument is normally $25 == $t9. */ | |
12044 | ||
12045 | static void | |
17a2f251 | 12046 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12047 | { |
12048 | expressionS ex; | |
252b5132 | 12049 | |
6478892d TS |
12050 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
12051 | .cpload is ignored. */ | |
12052 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
12053 | { |
12054 | s_ignore (0); | |
12055 | return; | |
12056 | } | |
12057 | ||
d3ecfc59 | 12058 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
12059 | if (mips_opts.noreorder == 0) |
12060 | as_warn (_(".cpload not in noreorder section")); | |
12061 | ||
12062 | ex.X_op = O_symbol; | |
12063 | ex.X_add_symbol = symbol_find_or_make ("_gp_disp"); | |
12064 | ex.X_op_symbol = NULL; | |
12065 | ex.X_add_number = 0; | |
12066 | ||
12067 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 12068 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 12069 | |
584892a6 | 12070 | macro_start (); |
67c0d1eb RS |
12071 | macro_build_lui (&ex, mips_gp_register); |
12072 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 12073 | mips_gp_register, BFD_RELOC_LO16); |
67c0d1eb | 12074 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, |
17a2f251 | 12075 | mips_gp_register, tc_get_register (0)); |
584892a6 | 12076 | macro_end (); |
252b5132 RH |
12077 | |
12078 | demand_empty_rest_of_line (); | |
12079 | } | |
12080 | ||
6478892d TS |
12081 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
12082 | .cpsetup $reg1, offset|$reg2, label | |
12083 | ||
12084 | If offset is given, this results in: | |
12085 | sd $gp, offset($sp) | |
956cd1d6 | 12086 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
12087 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
12088 | daddu $gp, $gp, $reg1 | |
6478892d TS |
12089 | |
12090 | If $reg2 is given, this results in: | |
12091 | daddu $reg2, $gp, $0 | |
956cd1d6 | 12092 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
12093 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
12094 | daddu $gp, $gp, $reg1 | |
12095 | $reg1 is normally $25 == $t9. */ | |
6478892d | 12096 | static void |
17a2f251 | 12097 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12098 | { |
12099 | expressionS ex_off; | |
12100 | expressionS ex_sym; | |
12101 | int reg1; | |
f21f8242 | 12102 | char *f; |
6478892d | 12103 | |
8586fc66 | 12104 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
12105 | We also need NewABI support. */ |
12106 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12107 | { | |
12108 | s_ignore (0); | |
12109 | return; | |
12110 | } | |
12111 | ||
12112 | reg1 = tc_get_register (0); | |
12113 | SKIP_WHITESPACE (); | |
12114 | if (*input_line_pointer != ',') | |
12115 | { | |
12116 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
12117 | return; | |
12118 | } | |
12119 | else | |
80245285 | 12120 | ++input_line_pointer; |
6478892d TS |
12121 | SKIP_WHITESPACE (); |
12122 | if (*input_line_pointer == '$') | |
80245285 TS |
12123 | { |
12124 | mips_cpreturn_register = tc_get_register (0); | |
12125 | mips_cpreturn_offset = -1; | |
12126 | } | |
6478892d | 12127 | else |
80245285 TS |
12128 | { |
12129 | mips_cpreturn_offset = get_absolute_expression (); | |
12130 | mips_cpreturn_register = -1; | |
12131 | } | |
6478892d TS |
12132 | SKIP_WHITESPACE (); |
12133 | if (*input_line_pointer != ',') | |
12134 | { | |
12135 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
12136 | return; | |
12137 | } | |
12138 | else | |
f9419b05 | 12139 | ++input_line_pointer; |
6478892d | 12140 | SKIP_WHITESPACE (); |
f21f8242 | 12141 | expression (&ex_sym); |
6478892d | 12142 | |
584892a6 | 12143 | macro_start (); |
6478892d TS |
12144 | if (mips_cpreturn_register == -1) |
12145 | { | |
12146 | ex_off.X_op = O_constant; | |
12147 | ex_off.X_add_symbol = NULL; | |
12148 | ex_off.X_op_symbol = NULL; | |
12149 | ex_off.X_add_number = mips_cpreturn_offset; | |
12150 | ||
67c0d1eb | 12151 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 12152 | BFD_RELOC_LO16, SP); |
6478892d TS |
12153 | } |
12154 | else | |
67c0d1eb | 12155 | macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, |
17a2f251 | 12156 | mips_gp_register, 0); |
6478892d | 12157 | |
f21f8242 AO |
12158 | /* Ensure there's room for the next two instructions, so that `f' |
12159 | doesn't end up with an address in the wrong frag. */ | |
12160 | frag_grow (8); | |
12161 | f = frag_more (0); | |
67c0d1eb | 12162 | macro_build (&ex_sym, "lui", "t,u", mips_gp_register, BFD_RELOC_GPREL16); |
f21f8242 | 12163 | fix_new (frag_now, f - frag_now->fr_literal, |
a105a300 | 12164 | 8, NULL, 0, 0, BFD_RELOC_MIPS_SUB); |
f21f8242 | 12165 | fix_new (frag_now, f - frag_now->fr_literal, |
a105a300 | 12166 | 4, NULL, 0, 0, BFD_RELOC_HI16_S); |
f21f8242 AO |
12167 | |
12168 | f = frag_more (0); | |
67c0d1eb | 12169 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, |
17a2f251 | 12170 | mips_gp_register, BFD_RELOC_GPREL16); |
f21f8242 | 12171 | fix_new (frag_now, f - frag_now->fr_literal, |
a105a300 | 12172 | 8, NULL, 0, 0, BFD_RELOC_MIPS_SUB); |
f21f8242 | 12173 | fix_new (frag_now, f - frag_now->fr_literal, |
a105a300 | 12174 | 4, NULL, 0, 0, BFD_RELOC_LO16); |
f21f8242 | 12175 | |
67c0d1eb | 12176 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, |
17a2f251 | 12177 | mips_gp_register, reg1); |
584892a6 | 12178 | macro_end (); |
6478892d TS |
12179 | |
12180 | demand_empty_rest_of_line (); | |
12181 | } | |
12182 | ||
12183 | static void | |
17a2f251 | 12184 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12185 | { |
12186 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
12187 | .cplocal is ignored. */ | |
12188 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12189 | { | |
12190 | s_ignore (0); | |
12191 | return; | |
12192 | } | |
12193 | ||
12194 | mips_gp_register = tc_get_register (0); | |
85b51719 | 12195 | demand_empty_rest_of_line (); |
6478892d TS |
12196 | } |
12197 | ||
252b5132 RH |
12198 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
12199 | offset from $sp. The offset is remembered, and after making a PIC | |
12200 | call $gp is restored from that location. */ | |
12201 | ||
12202 | static void | |
17a2f251 | 12203 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12204 | { |
12205 | expressionS ex; | |
252b5132 | 12206 | |
6478892d | 12207 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 12208 | .cprestore is ignored. */ |
6478892d | 12209 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
12210 | { |
12211 | s_ignore (0); | |
12212 | return; | |
12213 | } | |
12214 | ||
12215 | mips_cprestore_offset = get_absolute_expression (); | |
7a621144 | 12216 | mips_cprestore_valid = 1; |
252b5132 RH |
12217 | |
12218 | ex.X_op = O_constant; | |
12219 | ex.X_add_symbol = NULL; | |
12220 | ex.X_op_symbol = NULL; | |
12221 | ex.X_add_number = mips_cprestore_offset; | |
12222 | ||
584892a6 | 12223 | macro_start (); |
67c0d1eb RS |
12224 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
12225 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 12226 | macro_end (); |
252b5132 RH |
12227 | |
12228 | demand_empty_rest_of_line (); | |
12229 | } | |
12230 | ||
6478892d | 12231 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 12232 | was given in the preceding .cpsetup, it results in: |
6478892d | 12233 | ld $gp, offset($sp) |
76b3015f | 12234 | |
6478892d | 12235 | If a register $reg2 was given there, it results in: |
609f23f4 | 12236 | daddu $gp, $reg2, $0 |
6478892d TS |
12237 | */ |
12238 | static void | |
17a2f251 | 12239 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12240 | { |
12241 | expressionS ex; | |
6478892d TS |
12242 | |
12243 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
12244 | We also need NewABI support. */ | |
12245 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12246 | { | |
12247 | s_ignore (0); | |
12248 | return; | |
12249 | } | |
12250 | ||
584892a6 | 12251 | macro_start (); |
6478892d TS |
12252 | if (mips_cpreturn_register == -1) |
12253 | { | |
12254 | ex.X_op = O_constant; | |
12255 | ex.X_add_symbol = NULL; | |
12256 | ex.X_op_symbol = NULL; | |
12257 | ex.X_add_number = mips_cpreturn_offset; | |
12258 | ||
67c0d1eb | 12259 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
12260 | } |
12261 | else | |
67c0d1eb | 12262 | macro_build (NULL, "daddu", "d,v,t", mips_gp_register, |
17a2f251 | 12263 | mips_cpreturn_register, 0); |
584892a6 | 12264 | macro_end (); |
6478892d TS |
12265 | |
12266 | demand_empty_rest_of_line (); | |
12267 | } | |
12268 | ||
12269 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC | |
12270 | code. It sets the offset to use in gp_rel relocations. */ | |
12271 | ||
12272 | static void | |
17a2f251 | 12273 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12274 | { |
12275 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
12276 | We also need NewABI support. */ | |
12277 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12278 | { | |
12279 | s_ignore (0); | |
12280 | return; | |
12281 | } | |
12282 | ||
def2e0dd | 12283 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
12284 | |
12285 | demand_empty_rest_of_line (); | |
12286 | } | |
12287 | ||
252b5132 RH |
12288 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
12289 | code. It generates a 32 bit GP relative reloc. */ | |
12290 | ||
12291 | static void | |
17a2f251 | 12292 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12293 | { |
12294 | symbolS *label; | |
12295 | expressionS ex; | |
12296 | char *p; | |
12297 | ||
12298 | /* When not generating PIC code, this is treated as .word. */ | |
12299 | if (mips_pic != SVR4_PIC) | |
12300 | { | |
12301 | s_cons (2); | |
12302 | return; | |
12303 | } | |
12304 | ||
12305 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
b34976b6 | 12306 | mips_emit_delays (TRUE); |
252b5132 RH |
12307 | if (auto_align) |
12308 | mips_align (2, 0, label); | |
12309 | mips_clear_insn_labels (); | |
12310 | ||
12311 | expression (&ex); | |
12312 | ||
12313 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
12314 | { | |
12315 | as_bad (_("Unsupported use of .gpword")); | |
12316 | ignore_rest_of_line (); | |
12317 | } | |
12318 | ||
12319 | p = frag_more (4); | |
17a2f251 | 12320 | md_number_to_chars (p, 0, 4); |
b34976b6 | 12321 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 12322 | BFD_RELOC_GPREL32); |
252b5132 RH |
12323 | |
12324 | demand_empty_rest_of_line (); | |
12325 | } | |
12326 | ||
10181a0d | 12327 | static void |
17a2f251 | 12328 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d AO |
12329 | { |
12330 | symbolS *label; | |
12331 | expressionS ex; | |
12332 | char *p; | |
12333 | ||
12334 | /* When not generating PIC code, this is treated as .dword. */ | |
12335 | if (mips_pic != SVR4_PIC) | |
12336 | { | |
12337 | s_cons (3); | |
12338 | return; | |
12339 | } | |
12340 | ||
12341 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
b34976b6 | 12342 | mips_emit_delays (TRUE); |
10181a0d AO |
12343 | if (auto_align) |
12344 | mips_align (3, 0, label); | |
12345 | mips_clear_insn_labels (); | |
12346 | ||
12347 | expression (&ex); | |
12348 | ||
12349 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
12350 | { | |
12351 | as_bad (_("Unsupported use of .gpdword")); | |
12352 | ignore_rest_of_line (); | |
12353 | } | |
12354 | ||
12355 | p = frag_more (8); | |
17a2f251 | 12356 | md_number_to_chars (p, 0, 8); |
a105a300 | 12357 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
10181a0d AO |
12358 | BFD_RELOC_GPREL32); |
12359 | ||
12360 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
12361 | ex.X_op = O_absent; | |
12362 | ex.X_add_symbol = 0; | |
12363 | ex.X_add_number = 0; | |
b34976b6 | 12364 | fix_new_exp (frag_now, p - frag_now->fr_literal, 8, &ex, FALSE, |
10181a0d AO |
12365 | BFD_RELOC_64); |
12366 | ||
12367 | demand_empty_rest_of_line (); | |
12368 | } | |
12369 | ||
252b5132 RH |
12370 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
12371 | tables in SVR4 PIC code. */ | |
12372 | ||
12373 | static void | |
17a2f251 | 12374 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 12375 | { |
252b5132 RH |
12376 | int reg; |
12377 | ||
10181a0d AO |
12378 | /* This is ignored when not generating SVR4 PIC code. */ |
12379 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
12380 | { |
12381 | s_ignore (0); | |
12382 | return; | |
12383 | } | |
12384 | ||
12385 | /* Add $gp to the register named as an argument. */ | |
584892a6 | 12386 | macro_start (); |
252b5132 | 12387 | reg = tc_get_register (0); |
67c0d1eb | 12388 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 12389 | macro_end (); |
252b5132 | 12390 | |
bdaaa2e1 | 12391 | demand_empty_rest_of_line (); |
252b5132 RH |
12392 | } |
12393 | ||
12394 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
12395 | mips16 mode. This permits the linker to handle them specially, | |
12396 | such as generating jalx instructions when needed. We also make | |
12397 | them odd for the duration of the assembly, in order to generate the | |
12398 | right sort of code. We will make them even in the adjust_symtab | |
12399 | routine, while leaving them marked. This is convenient for the | |
12400 | debugger and the disassembler. The linker knows to make them odd | |
12401 | again. */ | |
12402 | ||
12403 | static void | |
17a2f251 | 12404 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 12405 | { |
f9419b05 | 12406 | mips16_mark_labels (); |
252b5132 RH |
12407 | |
12408 | demand_empty_rest_of_line (); | |
12409 | } | |
12410 | ||
12411 | /* Handle a .stabn directive. We need these in order to mark a label | |
12412 | as being a mips16 text label correctly. Sometimes the compiler | |
12413 | will emit a label, followed by a .stabn, and then switch sections. | |
12414 | If the label and .stabn are in mips16 mode, then the label is | |
12415 | really a mips16 text label. */ | |
12416 | ||
12417 | static void | |
17a2f251 | 12418 | s_mips_stab (int type) |
252b5132 | 12419 | { |
f9419b05 | 12420 | if (type == 'n') |
252b5132 RH |
12421 | mips16_mark_labels (); |
12422 | ||
12423 | s_stab (type); | |
12424 | } | |
12425 | ||
12426 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. | |
12427 | */ | |
12428 | ||
12429 | static void | |
17a2f251 | 12430 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12431 | { |
12432 | char *name; | |
12433 | int c; | |
12434 | symbolS *symbolP; | |
12435 | expressionS exp; | |
12436 | ||
12437 | name = input_line_pointer; | |
12438 | c = get_symbol_end (); | |
12439 | symbolP = symbol_find_or_make (name); | |
12440 | S_SET_WEAK (symbolP); | |
12441 | *input_line_pointer = c; | |
12442 | ||
12443 | SKIP_WHITESPACE (); | |
12444 | ||
12445 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
12446 | { | |
12447 | if (S_IS_DEFINED (symbolP)) | |
12448 | { | |
956cd1d6 | 12449 | as_bad ("ignoring attempt to redefine symbol %s", |
252b5132 RH |
12450 | S_GET_NAME (symbolP)); |
12451 | ignore_rest_of_line (); | |
12452 | return; | |
12453 | } | |
bdaaa2e1 | 12454 | |
252b5132 RH |
12455 | if (*input_line_pointer == ',') |
12456 | { | |
12457 | ++input_line_pointer; | |
12458 | SKIP_WHITESPACE (); | |
12459 | } | |
bdaaa2e1 | 12460 | |
252b5132 RH |
12461 | expression (&exp); |
12462 | if (exp.X_op != O_symbol) | |
12463 | { | |
12464 | as_bad ("bad .weakext directive"); | |
98d3f06f | 12465 | ignore_rest_of_line (); |
252b5132 RH |
12466 | return; |
12467 | } | |
49309057 | 12468 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
12469 | } |
12470 | ||
12471 | demand_empty_rest_of_line (); | |
12472 | } | |
12473 | ||
12474 | /* Parse a register string into a number. Called from the ECOFF code | |
12475 | to parse .frame. The argument is non-zero if this is the frame | |
12476 | register, so that we can record it in mips_frame_reg. */ | |
12477 | ||
12478 | int | |
17a2f251 | 12479 | tc_get_register (int frame) |
252b5132 RH |
12480 | { |
12481 | int reg; | |
12482 | ||
12483 | SKIP_WHITESPACE (); | |
12484 | if (*input_line_pointer++ != '$') | |
12485 | { | |
12486 | as_warn (_("expected `$'")); | |
85b51719 | 12487 | reg = ZERO; |
252b5132 | 12488 | } |
3882b010 | 12489 | else if (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
12490 | { |
12491 | reg = get_absolute_expression (); | |
12492 | if (reg < 0 || reg >= 32) | |
12493 | { | |
12494 | as_warn (_("Bad register number")); | |
85b51719 | 12495 | reg = ZERO; |
252b5132 RH |
12496 | } |
12497 | } | |
12498 | else | |
12499 | { | |
76db943d | 12500 | if (strncmp (input_line_pointer, "ra", 2) == 0) |
85b51719 TS |
12501 | { |
12502 | reg = RA; | |
12503 | input_line_pointer += 2; | |
12504 | } | |
76db943d | 12505 | else if (strncmp (input_line_pointer, "fp", 2) == 0) |
85b51719 TS |
12506 | { |
12507 | reg = FP; | |
12508 | input_line_pointer += 2; | |
12509 | } | |
252b5132 | 12510 | else if (strncmp (input_line_pointer, "sp", 2) == 0) |
85b51719 TS |
12511 | { |
12512 | reg = SP; | |
12513 | input_line_pointer += 2; | |
12514 | } | |
252b5132 | 12515 | else if (strncmp (input_line_pointer, "gp", 2) == 0) |
85b51719 TS |
12516 | { |
12517 | reg = GP; | |
12518 | input_line_pointer += 2; | |
12519 | } | |
252b5132 | 12520 | else if (strncmp (input_line_pointer, "at", 2) == 0) |
85b51719 TS |
12521 | { |
12522 | reg = AT; | |
12523 | input_line_pointer += 2; | |
12524 | } | |
12525 | else if (strncmp (input_line_pointer, "kt0", 3) == 0) | |
12526 | { | |
12527 | reg = KT0; | |
12528 | input_line_pointer += 3; | |
12529 | } | |
12530 | else if (strncmp (input_line_pointer, "kt1", 3) == 0) | |
12531 | { | |
12532 | reg = KT1; | |
12533 | input_line_pointer += 3; | |
12534 | } | |
12535 | else if (strncmp (input_line_pointer, "zero", 4) == 0) | |
12536 | { | |
12537 | reg = ZERO; | |
12538 | input_line_pointer += 4; | |
12539 | } | |
252b5132 RH |
12540 | else |
12541 | { | |
12542 | as_warn (_("Unrecognized register name")); | |
85b51719 TS |
12543 | reg = ZERO; |
12544 | while (ISALNUM(*input_line_pointer)) | |
12545 | input_line_pointer++; | |
252b5132 | 12546 | } |
252b5132 RH |
12547 | } |
12548 | if (frame) | |
7a621144 DJ |
12549 | { |
12550 | mips_frame_reg = reg != 0 ? reg : SP; | |
12551 | mips_frame_reg_valid = 1; | |
12552 | mips_cprestore_valid = 0; | |
12553 | } | |
252b5132 RH |
12554 | return reg; |
12555 | } | |
12556 | ||
12557 | valueT | |
17a2f251 | 12558 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
12559 | { |
12560 | int align = bfd_get_section_alignment (stdoutput, seg); | |
12561 | ||
12562 | #ifdef OBJ_ELF | |
12563 | /* We don't need to align ELF sections to the full alignment. | |
12564 | However, Irix 5 may prefer that we align them at least to a 16 | |
12565 | byte boundary. We don't bother to align the sections if we are | |
12566 | targeted for an embedded system. */ | |
12567 | if (strcmp (TARGET_OS, "elf") == 0) | |
12568 | return addr; | |
12569 | if (align > 4) | |
12570 | align = 4; | |
12571 | #endif | |
12572 | ||
12573 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
12574 | } | |
12575 | ||
12576 | /* Utility routine, called from above as well. If called while the | |
12577 | input file is still being read, it's only an approximation. (For | |
12578 | example, a symbol may later become defined which appeared to be | |
12579 | undefined earlier.) */ | |
12580 | ||
12581 | static int | |
17a2f251 | 12582 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
12583 | { |
12584 | if (sym == 0) | |
12585 | return 0; | |
12586 | ||
6478892d | 12587 | if (USE_GLOBAL_POINTER_OPT && g_switch_value > 0) |
252b5132 RH |
12588 | { |
12589 | const char *symname; | |
12590 | int change; | |
12591 | ||
c9914766 | 12592 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
12593 | register. It can be if it is smaller than the -G size or if |
12594 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 12595 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
12596 | they can. */ |
12597 | symname = S_GET_NAME (sym); | |
12598 | if (symname != (const char *) NULL | |
12599 | && (strcmp (symname, "eprol") == 0 | |
12600 | || strcmp (symname, "etext") == 0 | |
12601 | || strcmp (symname, "_gp") == 0 | |
12602 | || strcmp (symname, "edata") == 0 | |
12603 | || strcmp (symname, "_fbss") == 0 | |
12604 | || strcmp (symname, "_fdata") == 0 | |
12605 | || strcmp (symname, "_ftext") == 0 | |
12606 | || strcmp (symname, "end") == 0 | |
12607 | || strcmp (symname, "_gp_disp") == 0)) | |
12608 | change = 1; | |
12609 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
12610 | && (0 | |
12611 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
12612 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
12613 | && (symbol_get_obj (sym)->ecoff_extern_size | |
12614 | <= g_switch_value)) | |
252b5132 RH |
12615 | #endif |
12616 | /* We must defer this decision until after the whole | |
12617 | file has been read, since there might be a .extern | |
12618 | after the first use of this symbol. */ | |
12619 | || (before_relaxing | |
12620 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 12621 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
12622 | #endif |
12623 | && S_GET_VALUE (sym) == 0) | |
12624 | || (S_GET_VALUE (sym) != 0 | |
12625 | && S_GET_VALUE (sym) <= g_switch_value))) | |
12626 | change = 0; | |
12627 | else | |
12628 | { | |
12629 | const char *segname; | |
12630 | ||
12631 | segname = segment_name (S_GET_SEGMENT (sym)); | |
12632 | assert (strcmp (segname, ".lit8") != 0 | |
12633 | && strcmp (segname, ".lit4") != 0); | |
12634 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
12635 | && strcmp (segname, ".sbss") != 0 |
12636 | && strncmp (segname, ".sdata.", 7) != 0 | |
12637 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); | |
252b5132 RH |
12638 | } |
12639 | return change; | |
12640 | } | |
12641 | else | |
c9914766 | 12642 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
12643 | return 1; |
12644 | } | |
12645 | ||
5919d012 RS |
12646 | |
12647 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
12648 | ||
12649 | static bfd_boolean | |
17a2f251 | 12650 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
12651 | { |
12652 | asection *symsec; | |
12653 | bfd_boolean linkonce; | |
12654 | ||
12655 | /* Handle the case of a symbol equated to another symbol. */ | |
12656 | while (symbol_equated_reloc_p (sym)) | |
12657 | { | |
12658 | symbolS *n; | |
12659 | ||
12660 | /* It's possible to get a loop here in a badly written | |
12661 | program. */ | |
12662 | n = symbol_get_value_expression (sym)->X_add_symbol; | |
12663 | if (n == sym) | |
12664 | break; | |
12665 | sym = n; | |
12666 | } | |
12667 | ||
12668 | symsec = S_GET_SEGMENT (sym); | |
12669 | ||
12670 | /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */ | |
12671 | linkonce = FALSE; | |
12672 | if (symsec != segtype && ! S_IS_LOCAL (sym)) | |
12673 | { | |
12674 | if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE) | |
12675 | != 0) | |
12676 | linkonce = TRUE; | |
12677 | ||
12678 | /* The GNU toolchain uses an extension for ELF: a section | |
12679 | beginning with the magic string .gnu.linkonce is a linkonce | |
12680 | section. */ | |
12681 | if (strncmp (segment_name (symsec), ".gnu.linkonce", | |
12682 | sizeof ".gnu.linkonce" - 1) == 0) | |
12683 | linkonce = TRUE; | |
12684 | } | |
12685 | ||
12686 | /* This must duplicate the test in adjust_reloc_syms. */ | |
12687 | return (symsec != &bfd_und_section | |
12688 | && symsec != &bfd_abs_section | |
12689 | && ! bfd_is_com_section (symsec) | |
12690 | && !linkonce | |
12691 | #ifdef OBJ_ELF | |
12692 | /* A global or weak symbol is treated as external. */ | |
12693 | && (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
12694 | || (! S_IS_WEAK (sym) | |
12695 | && (! S_IS_EXTERNAL (sym) | |
12696 | || mips_pic == EMBEDDED_PIC))) | |
12697 | #endif | |
12698 | ); | |
12699 | } | |
12700 | ||
12701 | ||
252b5132 RH |
12702 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
12703 | extended opcode. SEC is the section the frag is in. */ | |
12704 | ||
12705 | static int | |
17a2f251 | 12706 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
12707 | { |
12708 | int type; | |
12709 | register const struct mips16_immed_operand *op; | |
12710 | offsetT val; | |
12711 | int mintiny, maxtiny; | |
12712 | segT symsec; | |
98aa84af | 12713 | fragS *sym_frag; |
252b5132 RH |
12714 | |
12715 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
12716 | return 0; | |
12717 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
12718 | return 1; | |
12719 | ||
12720 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
12721 | op = mips16_immed_operands; | |
12722 | while (op->type != type) | |
12723 | { | |
12724 | ++op; | |
12725 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
12726 | } | |
12727 | ||
12728 | if (op->unsp) | |
12729 | { | |
12730 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
12731 | { | |
12732 | mintiny = 1; | |
12733 | maxtiny = 1 << op->nbits; | |
12734 | } | |
12735 | else | |
12736 | { | |
12737 | mintiny = 0; | |
12738 | maxtiny = (1 << op->nbits) - 1; | |
12739 | } | |
12740 | } | |
12741 | else | |
12742 | { | |
12743 | mintiny = - (1 << (op->nbits - 1)); | |
12744 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
12745 | } | |
12746 | ||
98aa84af | 12747 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 12748 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 12749 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
12750 | |
12751 | if (op->pcrel) | |
12752 | { | |
12753 | addressT addr; | |
12754 | ||
12755 | /* We won't have the section when we are called from | |
12756 | mips_relax_frag. However, we will always have been called | |
12757 | from md_estimate_size_before_relax first. If this is a | |
12758 | branch to a different section, we mark it as such. If SEC is | |
12759 | NULL, and the frag is not marked, then it must be a branch to | |
12760 | the same section. */ | |
12761 | if (sec == NULL) | |
12762 | { | |
12763 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
12764 | return 1; | |
12765 | } | |
12766 | else | |
12767 | { | |
98aa84af | 12768 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
12769 | if (symsec != sec) |
12770 | { | |
12771 | fragp->fr_subtype = | |
12772 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12773 | ||
12774 | /* FIXME: We should support this, and let the linker | |
12775 | catch branches and loads that are out of range. */ | |
12776 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
12777 | _("unsupported PC relative reference to different section")); | |
12778 | ||
12779 | return 1; | |
12780 | } | |
98aa84af AM |
12781 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
12782 | /* Assume non-extended on the first relaxation pass. | |
12783 | The address we have calculated will be bogus if this is | |
12784 | a forward branch to another frag, as the forward frag | |
12785 | will have fr_address == 0. */ | |
12786 | return 0; | |
252b5132 RH |
12787 | } |
12788 | ||
12789 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
12790 | the same section. If the relax_marker of the symbol fragment |
12791 | differs from the relax_marker of this fragment, we have not | |
12792 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
12793 | in STRETCH in order to get a better estimate of the address. |
12794 | This particularly matters because of the shift bits. */ | |
12795 | if (stretch != 0 | |
98aa84af | 12796 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
12797 | { |
12798 | fragS *f; | |
12799 | ||
12800 | /* Adjust stretch for any alignment frag. Note that if have | |
12801 | been expanding the earlier code, the symbol may be | |
12802 | defined in what appears to be an earlier frag. FIXME: | |
12803 | This doesn't handle the fr_subtype field, which specifies | |
12804 | a maximum number of bytes to skip when doing an | |
12805 | alignment. */ | |
98aa84af | 12806 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
12807 | { |
12808 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
12809 | { | |
12810 | if (stretch < 0) | |
12811 | stretch = - ((- stretch) | |
12812 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
12813 | else | |
12814 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
12815 | if (stretch == 0) | |
12816 | break; | |
12817 | } | |
12818 | } | |
12819 | if (f != NULL) | |
12820 | val += stretch; | |
12821 | } | |
12822 | ||
12823 | addr = fragp->fr_address + fragp->fr_fix; | |
12824 | ||
12825 | /* The base address rules are complicated. The base address of | |
12826 | a branch is the following instruction. The base address of a | |
12827 | PC relative load or add is the instruction itself, but if it | |
12828 | is in a delay slot (in which case it can not be extended) use | |
12829 | the address of the instruction whose delay slot it is in. */ | |
12830 | if (type == 'p' || type == 'q') | |
12831 | { | |
12832 | addr += 2; | |
12833 | ||
12834 | /* If we are currently assuming that this frag should be | |
12835 | extended, then, the current address is two bytes | |
bdaaa2e1 | 12836 | higher. */ |
252b5132 RH |
12837 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
12838 | addr += 2; | |
12839 | ||
12840 | /* Ignore the low bit in the target, since it will be set | |
12841 | for a text label. */ | |
12842 | if ((val & 1) != 0) | |
12843 | --val; | |
12844 | } | |
12845 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
12846 | addr -= 4; | |
12847 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
12848 | addr -= 2; | |
12849 | ||
12850 | val -= addr & ~ ((1 << op->shift) - 1); | |
12851 | ||
12852 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
12853 | if (type == 'p' || type == 'q') | |
12854 | val /= 2; | |
12855 | ||
12856 | /* If any of the shifted bits are set, we must use an extended | |
12857 | opcode. If the address depends on the size of this | |
12858 | instruction, this can lead to a loop, so we arrange to always | |
12859 | use an extended opcode. We only check this when we are in | |
12860 | the main relaxation loop, when SEC is NULL. */ | |
12861 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
12862 | { | |
12863 | fragp->fr_subtype = | |
12864 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12865 | return 1; | |
12866 | } | |
12867 | ||
12868 | /* If we are about to mark a frag as extended because the value | |
12869 | is precisely maxtiny + 1, then there is a chance of an | |
12870 | infinite loop as in the following code: | |
12871 | la $4,foo | |
12872 | .skip 1020 | |
12873 | .align 2 | |
12874 | foo: | |
12875 | In this case when the la is extended, foo is 0x3fc bytes | |
12876 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
12877 | the la must be extended. To avoid this loop, we mark the | |
12878 | frag as extended if it was small, and is about to become | |
12879 | extended with a value of maxtiny + 1. */ | |
12880 | if (val == ((maxtiny + 1) << op->shift) | |
12881 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
12882 | && sec == NULL) | |
12883 | { | |
12884 | fragp->fr_subtype = | |
12885 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12886 | return 1; | |
12887 | } | |
12888 | } | |
12889 | else if (symsec != absolute_section && sec != NULL) | |
12890 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
12891 | ||
12892 | if ((val & ((1 << op->shift) - 1)) != 0 | |
12893 | || val < (mintiny << op->shift) | |
12894 | || val > (maxtiny << op->shift)) | |
12895 | return 1; | |
12896 | else | |
12897 | return 0; | |
12898 | } | |
12899 | ||
4a6a3df4 AO |
12900 | /* Compute the length of a branch sequence, and adjust the |
12901 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
12902 | worst-case length is computed, with UPDATE being used to indicate | |
12903 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
12904 | branch is to be computed. */ | |
12905 | static int | |
17a2f251 | 12906 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 12907 | { |
b34976b6 | 12908 | bfd_boolean toofar; |
4a6a3df4 AO |
12909 | int length; |
12910 | ||
12911 | if (fragp | |
12912 | && S_IS_DEFINED (fragp->fr_symbol) | |
12913 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
12914 | { | |
12915 | addressT addr; | |
12916 | offsetT val; | |
12917 | ||
12918 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
12919 | ||
12920 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
12921 | ||
12922 | val -= addr; | |
12923 | ||
12924 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
12925 | } | |
12926 | else if (fragp) | |
12927 | /* If the symbol is not defined or it's in a different segment, | |
12928 | assume the user knows what's going on and emit a short | |
12929 | branch. */ | |
b34976b6 | 12930 | toofar = FALSE; |
4a6a3df4 | 12931 | else |
b34976b6 | 12932 | toofar = TRUE; |
4a6a3df4 AO |
12933 | |
12934 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
12935 | fragp->fr_subtype | |
af6ae2ad | 12936 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype), |
4a6a3df4 AO |
12937 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
12938 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
12939 | toofar); | |
12940 | ||
12941 | length = 4; | |
12942 | if (toofar) | |
12943 | { | |
12944 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
12945 | length += 8; | |
12946 | ||
12947 | if (mips_pic != NO_PIC) | |
12948 | { | |
12949 | /* Additional space for PIC loading of target address. */ | |
12950 | length += 8; | |
12951 | if (mips_opts.isa == ISA_MIPS1) | |
12952 | /* Additional space for $at-stabilizing nop. */ | |
12953 | length += 4; | |
12954 | } | |
12955 | ||
12956 | /* If branch is conditional. */ | |
12957 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
12958 | length += 8; | |
12959 | } | |
b34976b6 | 12960 | |
4a6a3df4 AO |
12961 | return length; |
12962 | } | |
12963 | ||
252b5132 RH |
12964 | /* Estimate the size of a frag before relaxing. Unless this is the |
12965 | mips16, we are not really relaxing here, and the final size is | |
12966 | encoded in the subtype information. For the mips16, we have to | |
12967 | decide whether we are using an extended opcode or not. */ | |
12968 | ||
252b5132 | 12969 | int |
17a2f251 | 12970 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 12971 | { |
5919d012 | 12972 | int change; |
252b5132 | 12973 | |
4a6a3df4 AO |
12974 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
12975 | { | |
12976 | ||
b34976b6 AM |
12977 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
12978 | ||
4a6a3df4 AO |
12979 | return fragp->fr_var; |
12980 | } | |
12981 | ||
252b5132 | 12982 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
12983 | /* We don't want to modify the EXTENDED bit here; it might get us |
12984 | into infinite loops. We change it only in mips_relax_frag(). */ | |
12985 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 RH |
12986 | |
12987 | if (mips_pic == NO_PIC) | |
5919d012 | 12988 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 12989 | else if (mips_pic == SVR4_PIC) |
5919d012 | 12990 | change = pic_need_relax (fragp->fr_symbol, segtype); |
252b5132 RH |
12991 | else |
12992 | abort (); | |
12993 | ||
12994 | if (change) | |
12995 | { | |
4d7206a2 | 12996 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 12997 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 12998 | } |
4d7206a2 RS |
12999 | else |
13000 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
13001 | } |
13002 | ||
13003 | /* This is called to see whether a reloc against a defined symbol | |
13004 | should be converted into a reloc against a section. Don't adjust | |
13005 | MIPS16 jump relocations, so we don't have to worry about the format | |
13006 | of the offset in the .o file. Don't adjust relocations against | |
13007 | mips16 symbols, so that the linker can find them if it needs to set | |
13008 | up a stub. */ | |
13009 | ||
13010 | int | |
17a2f251 | 13011 | mips_fix_adjustable (fixS *fixp) |
252b5132 RH |
13012 | { |
13013 | if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) | |
13014 | return 0; | |
a161fe53 | 13015 | |
252b5132 RH |
13016 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
13017 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
13018 | return 0; | |
a161fe53 | 13019 | |
252b5132 RH |
13020 | if (fixp->fx_addsy == NULL) |
13021 | return 1; | |
a161fe53 | 13022 | |
252b5132 RH |
13023 | #ifdef OBJ_ELF |
13024 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
13025 | && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 | |
13026 | && fixp->fx_subsy == NULL) | |
13027 | return 0; | |
13028 | #endif | |
a161fe53 | 13029 | |
252b5132 RH |
13030 | return 1; |
13031 | } | |
13032 | ||
13033 | /* Translate internal representation of relocation info to BFD target | |
13034 | format. */ | |
13035 | ||
13036 | arelent ** | |
17a2f251 | 13037 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
13038 | { |
13039 | static arelent *retval[4]; | |
13040 | arelent *reloc; | |
13041 | bfd_reloc_code_real_type code; | |
13042 | ||
4b0cff4e TS |
13043 | memset (retval, 0, sizeof(retval)); |
13044 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
13045 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
13046 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
13047 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
13048 | ||
13049 | if (mips_pic == EMBEDDED_PIC | |
13050 | && SWITCH_TABLE (fixp)) | |
13051 | { | |
13052 | /* For a switch table entry we use a special reloc. The addend | |
13053 | is actually the difference between the reloc address and the | |
13054 | subtrahend. */ | |
13055 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
13056 | if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour) | |
13057 | as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc")); | |
13058 | fixp->fx_r_type = BFD_RELOC_GPREL32; | |
13059 | } | |
30ac9238 | 13060 | else if (fixp->fx_pcrel) |
252b5132 | 13061 | { |
30ac9238 RS |
13062 | bfd_vma pcrel_address; |
13063 | ||
13064 | /* Set PCREL_ADDRESS to this relocation's "PC". The PC for high | |
13065 | high-part relocs is the address of the low-part reloc. */ | |
13066 | if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S) | |
13067 | { | |
13068 | assert (fixp->fx_next != NULL | |
13069 | && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16); | |
13070 | pcrel_address = (fixp->fx_next->fx_where | |
13071 | + fixp->fx_next->fx_frag->fr_address); | |
13072 | } | |
252b5132 | 13073 | else |
30ac9238 RS |
13074 | pcrel_address = reloc->address; |
13075 | ||
13076 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
13077 | { | |
13078 | /* At this point, fx_addnumber is "symbol offset - pcrel_address". | |
13079 | Relocations want only the symbol offset. */ | |
13080 | reloc->addend = fixp->fx_addnumber + pcrel_address; | |
13081 | } | |
13082 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16 | |
13083 | || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S) | |
4514d474 | 13084 | { |
30ac9238 | 13085 | /* We use a special addend for an internal RELLO or RELHI reloc. */ |
4514d474 | 13086 | if (symbol_section_p (fixp->fx_addsy)) |
30ac9238 | 13087 | reloc->addend = pcrel_address - S_GET_VALUE (fixp->fx_subsy); |
4514d474 | 13088 | else |
30ac9238 | 13089 | reloc->addend = fixp->fx_addnumber + pcrel_address; |
4514d474 | 13090 | } |
252b5132 | 13091 | else |
4514d474 | 13092 | { |
30ac9238 RS |
13093 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour) |
13094 | /* A gruesome hack which is a result of the gruesome gas reloc | |
13095 | handling. */ | |
13096 | reloc->addend = pcrel_address; | |
4514d474 | 13097 | else |
30ac9238 | 13098 | reloc->addend = -pcrel_address; |
4514d474 | 13099 | } |
252b5132 | 13100 | } |
252b5132 | 13101 | else |
30ac9238 | 13102 | reloc->addend = fixp->fx_addnumber; |
252b5132 | 13103 | |
438c16b8 TS |
13104 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
13105 | entry to be used in the relocation's section offset. */ | |
13106 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
13107 | { |
13108 | reloc->address = reloc->addend; | |
13109 | reloc->addend = 0; | |
13110 | } | |
13111 | ||
13112 | /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that | |
13113 | fixup_segment converted a non-PC relative reloc into a PC | |
13114 | relative reloc. In such a case, we need to convert the reloc | |
13115 | code. */ | |
13116 | code = fixp->fx_r_type; | |
13117 | if (fixp->fx_pcrel) | |
13118 | { | |
13119 | switch (code) | |
13120 | { | |
13121 | case BFD_RELOC_8: | |
13122 | code = BFD_RELOC_8_PCREL; | |
13123 | break; | |
13124 | case BFD_RELOC_16: | |
13125 | code = BFD_RELOC_16_PCREL; | |
13126 | break; | |
13127 | case BFD_RELOC_32: | |
13128 | code = BFD_RELOC_32_PCREL; | |
13129 | break; | |
13130 | case BFD_RELOC_64: | |
13131 | code = BFD_RELOC_64_PCREL; | |
13132 | break; | |
13133 | case BFD_RELOC_8_PCREL: | |
13134 | case BFD_RELOC_16_PCREL: | |
13135 | case BFD_RELOC_32_PCREL: | |
13136 | case BFD_RELOC_64_PCREL: | |
13137 | case BFD_RELOC_16_PCREL_S2: | |
13138 | case BFD_RELOC_PCREL_HI16_S: | |
13139 | case BFD_RELOC_PCREL_LO16: | |
13140 | break; | |
13141 | default: | |
13142 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
13143 | _("Cannot make %s relocation PC relative"), | |
13144 | bfd_get_reloc_code_name (code)); | |
13145 | } | |
13146 | } | |
13147 | ||
0b25d3e6 AO |
13148 | /* To support a PC relative reloc when generating embedded PIC code |
13149 | for ECOFF, we use a Cygnus extension. We check for that here to | |
13150 | make sure that we don't let such a reloc escape normally. */ | |
13151 | if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour | |
13152 | || OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
13153 | && code == BFD_RELOC_16_PCREL_S2 | |
13154 | && mips_pic != EMBEDDED_PIC) | |
13155 | reloc->howto = NULL; | |
13156 | else | |
13157 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
13158 | ||
252b5132 RH |
13159 | if (reloc->howto == NULL) |
13160 | { | |
13161 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
13162 | _("Can not represent %s relocation in this object file format"), | |
13163 | bfd_get_reloc_code_name (code)); | |
13164 | retval[0] = NULL; | |
13165 | } | |
13166 | ||
13167 | return retval; | |
13168 | } | |
13169 | ||
13170 | /* Relax a machine dependent frag. This returns the amount by which | |
13171 | the current size of the frag should change. */ | |
13172 | ||
13173 | int | |
17a2f251 | 13174 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 13175 | { |
4a6a3df4 AO |
13176 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13177 | { | |
13178 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
13179 | |
13180 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
13181 | |
13182 | return fragp->fr_var - old_var; | |
13183 | } | |
13184 | ||
252b5132 RH |
13185 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
13186 | return 0; | |
13187 | ||
c4e7957c | 13188 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
13189 | { |
13190 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13191 | return 0; | |
13192 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
13193 | return 2; | |
13194 | } | |
13195 | else | |
13196 | { | |
13197 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13198 | return 0; | |
13199 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
13200 | return -2; | |
13201 | } | |
13202 | ||
13203 | return 0; | |
13204 | } | |
13205 | ||
13206 | /* Convert a machine dependent frag. */ | |
13207 | ||
13208 | void | |
17a2f251 | 13209 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 13210 | { |
4a6a3df4 AO |
13211 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13212 | { | |
13213 | bfd_byte *buf; | |
13214 | unsigned long insn; | |
13215 | expressionS exp; | |
13216 | fixS *fixp; | |
b34976b6 | 13217 | |
4a6a3df4 AO |
13218 | buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; |
13219 | ||
13220 | if (target_big_endian) | |
13221 | insn = bfd_getb32 (buf); | |
13222 | else | |
13223 | insn = bfd_getl32 (buf); | |
b34976b6 | 13224 | |
4a6a3df4 AO |
13225 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
13226 | { | |
13227 | /* We generate a fixup instead of applying it right now | |
13228 | because, if there are linker relaxations, we're going to | |
13229 | need the relocations. */ | |
13230 | exp.X_op = O_symbol; | |
13231 | exp.X_add_symbol = fragp->fr_symbol; | |
13232 | exp.X_add_number = fragp->fr_offset; | |
13233 | ||
13234 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
0b25d3e6 AO |
13235 | 4, &exp, 1, |
13236 | BFD_RELOC_16_PCREL_S2); | |
4a6a3df4 AO |
13237 | fixp->fx_file = fragp->fr_file; |
13238 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 13239 | |
17a2f251 | 13240 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
13241 | buf += 4; |
13242 | } | |
13243 | else | |
13244 | { | |
13245 | int i; | |
13246 | ||
13247 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
13248 | _("relaxed out-of-range branch into a jump")); | |
13249 | ||
13250 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
13251 | goto uncond; | |
13252 | ||
13253 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13254 | { | |
13255 | /* Reverse the branch. */ | |
13256 | switch ((insn >> 28) & 0xf) | |
13257 | { | |
13258 | case 4: | |
13259 | /* bc[0-3][tf]l? and bc1any[24][ft] instructions can | |
13260 | have the condition reversed by tweaking a single | |
13261 | bit, and their opcodes all have 0x4???????. */ | |
13262 | assert ((insn & 0xf1000000) == 0x41000000); | |
13263 | insn ^= 0x00010000; | |
13264 | break; | |
13265 | ||
13266 | case 0: | |
13267 | /* bltz 0x04000000 bgez 0x04010000 | |
13268 | bltzal 0x04100000 bgezal 0x04110000 */ | |
13269 | assert ((insn & 0xfc0e0000) == 0x04000000); | |
13270 | insn ^= 0x00010000; | |
13271 | break; | |
b34976b6 | 13272 | |
4a6a3df4 AO |
13273 | case 1: |
13274 | /* beq 0x10000000 bne 0x14000000 | |
13275 | blez 0x18000000 bgtz 0x1c000000 */ | |
13276 | insn ^= 0x04000000; | |
13277 | break; | |
13278 | ||
13279 | default: | |
13280 | abort (); | |
13281 | } | |
13282 | } | |
13283 | ||
13284 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
13285 | { | |
13286 | /* Clear the and-link bit. */ | |
13287 | assert ((insn & 0xfc1c0000) == 0x04100000); | |
13288 | ||
13289 | /* bltzal 0x04100000 bgezal 0x04110000 | |
13290 | bltzall 0x04120000 bgezall 0x04130000 */ | |
13291 | insn &= ~0x00100000; | |
13292 | } | |
13293 | ||
13294 | /* Branch over the branch (if the branch was likely) or the | |
13295 | full jump (not likely case). Compute the offset from the | |
13296 | current instruction to branch to. */ | |
13297 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13298 | i = 16; | |
13299 | else | |
13300 | { | |
13301 | /* How many bytes in instructions we've already emitted? */ | |
13302 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
13303 | /* How many bytes in instructions from here to the end? */ | |
13304 | i = fragp->fr_var - i; | |
13305 | } | |
13306 | /* Convert to instruction count. */ | |
13307 | i >>= 2; | |
13308 | /* Branch counts from the next instruction. */ | |
b34976b6 | 13309 | i--; |
4a6a3df4 AO |
13310 | insn |= i; |
13311 | /* Branch over the jump. */ | |
17a2f251 | 13312 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
13313 | buf += 4; |
13314 | ||
13315 | /* Nop */ | |
17a2f251 | 13316 | md_number_to_chars (buf, 0, 4); |
4a6a3df4 AO |
13317 | buf += 4; |
13318 | ||
13319 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13320 | { | |
13321 | /* beql $0, $0, 2f */ | |
13322 | insn = 0x50000000; | |
13323 | /* Compute the PC offset from the current instruction to | |
13324 | the end of the variable frag. */ | |
13325 | /* How many bytes in instructions we've already emitted? */ | |
13326 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
13327 | /* How many bytes in instructions from here to the end? */ | |
13328 | i = fragp->fr_var - i; | |
13329 | /* Convert to instruction count. */ | |
13330 | i >>= 2; | |
13331 | /* Don't decrement i, because we want to branch over the | |
13332 | delay slot. */ | |
13333 | ||
13334 | insn |= i; | |
17a2f251 | 13335 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
13336 | buf += 4; |
13337 | ||
17a2f251 | 13338 | md_number_to_chars (buf, 0, 4); |
4a6a3df4 AO |
13339 | buf += 4; |
13340 | } | |
13341 | ||
13342 | uncond: | |
13343 | if (mips_pic == NO_PIC) | |
13344 | { | |
13345 | /* j or jal. */ | |
13346 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
13347 | ? 0x0c000000 : 0x08000000); | |
13348 | exp.X_op = O_symbol; | |
13349 | exp.X_add_symbol = fragp->fr_symbol; | |
13350 | exp.X_add_number = fragp->fr_offset; | |
13351 | ||
13352 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13353 | 4, &exp, 0, BFD_RELOC_MIPS_JMP); | |
13354 | fixp->fx_file = fragp->fr_file; | |
13355 | fixp->fx_line = fragp->fr_line; | |
13356 | ||
17a2f251 | 13357 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
13358 | buf += 4; |
13359 | } | |
13360 | else | |
13361 | { | |
13362 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ | |
13363 | insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000; | |
13364 | exp.X_op = O_symbol; | |
13365 | exp.X_add_symbol = fragp->fr_symbol; | |
13366 | exp.X_add_number = fragp->fr_offset; | |
13367 | ||
13368 | if (fragp->fr_offset) | |
13369 | { | |
13370 | exp.X_add_symbol = make_expr_symbol (&exp); | |
13371 | exp.X_add_number = 0; | |
13372 | } | |
13373 | ||
13374 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13375 | 4, &exp, 0, BFD_RELOC_MIPS_GOT16); | |
13376 | fixp->fx_file = fragp->fr_file; | |
13377 | fixp->fx_line = fragp->fr_line; | |
13378 | ||
17a2f251 | 13379 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 | 13380 | buf += 4; |
b34976b6 | 13381 | |
4a6a3df4 AO |
13382 | if (mips_opts.isa == ISA_MIPS1) |
13383 | { | |
13384 | /* nop */ | |
17a2f251 | 13385 | md_number_to_chars (buf, 0, 4); |
4a6a3df4 AO |
13386 | buf += 4; |
13387 | } | |
13388 | ||
13389 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
13390 | insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000; | |
13391 | ||
13392 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13393 | 4, &exp, 0, BFD_RELOC_LO16); | |
13394 | fixp->fx_file = fragp->fr_file; | |
13395 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 13396 | |
17a2f251 | 13397 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
13398 | buf += 4; |
13399 | ||
13400 | /* j(al)r $at. */ | |
13401 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
13402 | insn = 0x0020f809; | |
13403 | else | |
13404 | insn = 0x00200008; | |
13405 | ||
17a2f251 | 13406 | md_number_to_chars (buf, insn, 4); |
4a6a3df4 AO |
13407 | buf += 4; |
13408 | } | |
13409 | } | |
13410 | ||
13411 | assert (buf == (bfd_byte *)fragp->fr_literal | |
13412 | + fragp->fr_fix + fragp->fr_var); | |
13413 | ||
13414 | fragp->fr_fix += fragp->fr_var; | |
13415 | ||
13416 | return; | |
13417 | } | |
13418 | ||
252b5132 RH |
13419 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
13420 | { | |
13421 | int type; | |
13422 | register const struct mips16_immed_operand *op; | |
b34976b6 | 13423 | bfd_boolean small, ext; |
252b5132 RH |
13424 | offsetT val; |
13425 | bfd_byte *buf; | |
13426 | unsigned long insn; | |
b34976b6 | 13427 | bfd_boolean use_extend; |
252b5132 RH |
13428 | unsigned short extend; |
13429 | ||
13430 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
13431 | op = mips16_immed_operands; | |
13432 | while (op->type != type) | |
13433 | ++op; | |
13434 | ||
13435 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13436 | { | |
b34976b6 AM |
13437 | small = FALSE; |
13438 | ext = TRUE; | |
252b5132 RH |
13439 | } |
13440 | else | |
13441 | { | |
b34976b6 AM |
13442 | small = TRUE; |
13443 | ext = FALSE; | |
252b5132 RH |
13444 | } |
13445 | ||
6386f3a7 | 13446 | resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
13447 | val = S_GET_VALUE (fragp->fr_symbol); |
13448 | if (op->pcrel) | |
13449 | { | |
13450 | addressT addr; | |
13451 | ||
13452 | addr = fragp->fr_address + fragp->fr_fix; | |
13453 | ||
13454 | /* The rules for the base address of a PC relative reloc are | |
13455 | complicated; see mips16_extended_frag. */ | |
13456 | if (type == 'p' || type == 'q') | |
13457 | { | |
13458 | addr += 2; | |
13459 | if (ext) | |
13460 | addr += 2; | |
13461 | /* Ignore the low bit in the target, since it will be | |
13462 | set for a text label. */ | |
13463 | if ((val & 1) != 0) | |
13464 | --val; | |
13465 | } | |
13466 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
13467 | addr -= 4; | |
13468 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
13469 | addr -= 2; | |
13470 | ||
13471 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
13472 | val -= addr; | |
13473 | ||
13474 | /* Make sure the section winds up with the alignment we have | |
13475 | assumed. */ | |
13476 | if (op->shift > 0) | |
13477 | record_alignment (asec, op->shift); | |
13478 | } | |
13479 | ||
13480 | if (ext | |
13481 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
13482 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
13483 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
13484 | _("extended instruction in delay slot")); | |
13485 | ||
13486 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
13487 | ||
13488 | if (target_big_endian) | |
13489 | insn = bfd_getb16 (buf); | |
13490 | else | |
13491 | insn = bfd_getl16 (buf); | |
13492 | ||
13493 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
13494 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
13495 | small, ext, &insn, &use_extend, &extend); | |
13496 | ||
13497 | if (use_extend) | |
13498 | { | |
17a2f251 | 13499 | md_number_to_chars (buf, 0xf000 | extend, 2); |
252b5132 RH |
13500 | fragp->fr_fix += 2; |
13501 | buf += 2; | |
13502 | } | |
13503 | ||
17a2f251 | 13504 | md_number_to_chars (buf, insn, 2); |
252b5132 RH |
13505 | fragp->fr_fix += 2; |
13506 | buf += 2; | |
13507 | } | |
13508 | else | |
13509 | { | |
4d7206a2 RS |
13510 | int first, second; |
13511 | fixS *fixp; | |
252b5132 | 13512 | |
4d7206a2 RS |
13513 | first = RELAX_FIRST (fragp->fr_subtype); |
13514 | second = RELAX_SECOND (fragp->fr_subtype); | |
13515 | fixp = (fixS *) fragp->fr_opcode; | |
252b5132 | 13516 | |
584892a6 RS |
13517 | /* Possibly emit a warning if we've chosen the longer option. */ |
13518 | if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0) | |
13519 | == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0)) | |
13520 | { | |
13521 | const char *msg = macro_warning (fragp->fr_subtype); | |
13522 | if (msg != 0) | |
13523 | as_warn_where (fragp->fr_file, fragp->fr_line, msg); | |
13524 | } | |
13525 | ||
4d7206a2 RS |
13526 | /* Go through all the fixups for the first sequence. Disable them |
13527 | (by marking them as done) if we're going to use the second | |
13528 | sequence instead. */ | |
13529 | while (fixp | |
13530 | && fixp->fx_frag == fragp | |
13531 | && fixp->fx_where < fragp->fr_fix - second) | |
13532 | { | |
13533 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13534 | fixp->fx_done = 1; | |
13535 | fixp = fixp->fx_next; | |
13536 | } | |
252b5132 | 13537 | |
4d7206a2 RS |
13538 | /* Go through the fixups for the second sequence. Disable them if |
13539 | we're going to use the first sequence, otherwise adjust their | |
13540 | addresses to account for the relaxation. */ | |
13541 | while (fixp && fixp->fx_frag == fragp) | |
13542 | { | |
13543 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13544 | fixp->fx_where -= first; | |
13545 | else | |
13546 | fixp->fx_done = 1; | |
13547 | fixp = fixp->fx_next; | |
13548 | } | |
13549 | ||
13550 | /* Now modify the frag contents. */ | |
13551 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13552 | { | |
13553 | char *start; | |
13554 | ||
13555 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
13556 | memmove (start, start + first, second); | |
13557 | fragp->fr_fix -= first; | |
13558 | } | |
13559 | else | |
13560 | fragp->fr_fix -= second; | |
252b5132 RH |
13561 | } |
13562 | } | |
13563 | ||
13564 | #ifdef OBJ_ELF | |
13565 | ||
13566 | /* This function is called after the relocs have been generated. | |
13567 | We've been storing mips16 text labels as odd. Here we convert them | |
13568 | back to even for the convenience of the debugger. */ | |
13569 | ||
13570 | void | |
17a2f251 | 13571 | mips_frob_file_after_relocs (void) |
252b5132 RH |
13572 | { |
13573 | asymbol **syms; | |
13574 | unsigned int count, i; | |
13575 | ||
13576 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
13577 | return; | |
13578 | ||
13579 | syms = bfd_get_outsymbols (stdoutput); | |
13580 | count = bfd_get_symcount (stdoutput); | |
13581 | for (i = 0; i < count; i++, syms++) | |
13582 | { | |
13583 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
13584 | && ((*syms)->value & 1) != 0) | |
13585 | { | |
13586 | (*syms)->value &= ~1; | |
13587 | /* If the symbol has an odd size, it was probably computed | |
13588 | incorrectly, so adjust that as well. */ | |
13589 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
13590 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
13591 | } | |
13592 | } | |
13593 | } | |
13594 | ||
13595 | #endif | |
13596 | ||
13597 | /* This function is called whenever a label is defined. It is used | |
13598 | when handling branch delays; if a branch has a label, we assume we | |
13599 | can not move it. */ | |
13600 | ||
13601 | void | |
17a2f251 | 13602 | mips_define_label (symbolS *sym) |
252b5132 RH |
13603 | { |
13604 | struct insn_label_list *l; | |
13605 | ||
13606 | if (free_insn_labels == NULL) | |
13607 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
13608 | else | |
13609 | { | |
13610 | l = free_insn_labels; | |
13611 | free_insn_labels = l->next; | |
13612 | } | |
13613 | ||
13614 | l->label = sym; | |
13615 | l->next = insn_labels; | |
13616 | insn_labels = l; | |
13617 | } | |
13618 | \f | |
13619 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
13620 | ||
13621 | /* Some special processing for a MIPS ELF file. */ | |
13622 | ||
13623 | void | |
17a2f251 | 13624 | mips_elf_final_processing (void) |
252b5132 RH |
13625 | { |
13626 | /* Write out the register information. */ | |
316f5878 | 13627 | if (mips_abi != N64_ABI) |
252b5132 RH |
13628 | { |
13629 | Elf32_RegInfo s; | |
13630 | ||
13631 | s.ri_gprmask = mips_gprmask; | |
13632 | s.ri_cprmask[0] = mips_cprmask[0]; | |
13633 | s.ri_cprmask[1] = mips_cprmask[1]; | |
13634 | s.ri_cprmask[2] = mips_cprmask[2]; | |
13635 | s.ri_cprmask[3] = mips_cprmask[3]; | |
13636 | /* The gp_value field is set by the MIPS ELF backend. */ | |
13637 | ||
13638 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
13639 | ((Elf32_External_RegInfo *) | |
13640 | mips_regmask_frag)); | |
13641 | } | |
13642 | else | |
13643 | { | |
13644 | Elf64_Internal_RegInfo s; | |
13645 | ||
13646 | s.ri_gprmask = mips_gprmask; | |
13647 | s.ri_pad = 0; | |
13648 | s.ri_cprmask[0] = mips_cprmask[0]; | |
13649 | s.ri_cprmask[1] = mips_cprmask[1]; | |
13650 | s.ri_cprmask[2] = mips_cprmask[2]; | |
13651 | s.ri_cprmask[3] = mips_cprmask[3]; | |
13652 | /* The gp_value field is set by the MIPS ELF backend. */ | |
13653 | ||
13654 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
13655 | ((Elf64_External_RegInfo *) | |
13656 | mips_regmask_frag)); | |
13657 | } | |
13658 | ||
13659 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
13660 | sort of BFD interface for this. */ | |
13661 | if (mips_any_noreorder) | |
13662 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
13663 | if (mips_pic != NO_PIC) | |
143d77c5 | 13664 | { |
252b5132 | 13665 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
13666 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
13667 | } | |
13668 | if (mips_abicalls) | |
13669 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 13670 | |
98d3f06f | 13671 | /* Set MIPS ELF flags for ASEs. */ |
a4672219 TS |
13672 | if (file_ase_mips16) |
13673 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
1f25f5d3 CD |
13674 | #if 0 /* XXX FIXME */ |
13675 | if (file_ase_mips3d) | |
13676 | elf_elfheader (stdoutput)->e_flags |= ???; | |
13677 | #endif | |
deec1734 CD |
13678 | if (file_ase_mdmx) |
13679 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; | |
1f25f5d3 | 13680 | |
bdaaa2e1 | 13681 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 13682 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 13683 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 13684 | else if (mips_abi == O64_ABI) |
252b5132 | 13685 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 13686 | else if (mips_abi == EABI_ABI) |
252b5132 | 13687 | { |
316f5878 | 13688 | if (!file_mips_gp32) |
252b5132 RH |
13689 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
13690 | else | |
13691 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
13692 | } | |
316f5878 | 13693 | else if (mips_abi == N32_ABI) |
be00bddd TS |
13694 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
13695 | ||
c9914766 | 13696 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
13697 | |
13698 | if (mips_32bitmode) | |
13699 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
13700 | } | |
13701 | ||
13702 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
13703 | \f | |
beae10d5 KH |
13704 | typedef struct proc { |
13705 | symbolS *isym; | |
13706 | unsigned long reg_mask; | |
13707 | unsigned long reg_offset; | |
13708 | unsigned long fpreg_mask; | |
13709 | unsigned long fpreg_offset; | |
13710 | unsigned long frame_offset; | |
13711 | unsigned long frame_reg; | |
13712 | unsigned long pc_reg; | |
13713 | } procS; | |
252b5132 RH |
13714 | |
13715 | static procS cur_proc; | |
13716 | static procS *cur_proc_ptr; | |
13717 | static int numprocs; | |
13718 | ||
0a9ef439 | 13719 | /* Fill in an rs_align_code fragment. */ |
a19d8eb0 | 13720 | |
0a9ef439 | 13721 | void |
17a2f251 | 13722 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 13723 | { |
0a9ef439 RH |
13724 | if (fragp->fr_type != rs_align_code) |
13725 | return; | |
13726 | ||
13727 | if (mips_opts.mips16) | |
a19d8eb0 CP |
13728 | { |
13729 | static const unsigned char be_nop[] = { 0x65, 0x00 }; | |
13730 | static const unsigned char le_nop[] = { 0x00, 0x65 }; | |
13731 | ||
0a9ef439 RH |
13732 | int bytes; |
13733 | char *p; | |
a19d8eb0 | 13734 | |
0a9ef439 RH |
13735 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
13736 | p = fragp->fr_literal + fragp->fr_fix; | |
13737 | ||
13738 | if (bytes & 1) | |
13739 | { | |
13740 | *p++ = 0; | |
f9419b05 | 13741 | fragp->fr_fix++; |
0a9ef439 RH |
13742 | } |
13743 | ||
13744 | memcpy (p, (target_big_endian ? be_nop : le_nop), 2); | |
13745 | fragp->fr_var = 2; | |
a19d8eb0 CP |
13746 | } |
13747 | ||
0a9ef439 | 13748 | /* For mips32, a nop is a zero, which we trivially get by doing nothing. */ |
a19d8eb0 CP |
13749 | } |
13750 | ||
252b5132 | 13751 | static void |
17a2f251 | 13752 | md_obj_begin (void) |
252b5132 RH |
13753 | { |
13754 | } | |
13755 | ||
13756 | static void | |
17a2f251 | 13757 | md_obj_end (void) |
252b5132 RH |
13758 | { |
13759 | /* check for premature end, nesting errors, etc */ | |
13760 | if (cur_proc_ptr) | |
9a41af64 | 13761 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
13762 | } |
13763 | ||
13764 | static long | |
17a2f251 | 13765 | get_number (void) |
252b5132 RH |
13766 | { |
13767 | int negative = 0; | |
13768 | long val = 0; | |
13769 | ||
13770 | if (*input_line_pointer == '-') | |
13771 | { | |
13772 | ++input_line_pointer; | |
13773 | negative = 1; | |
13774 | } | |
3882b010 | 13775 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 13776 | as_bad (_("expected simple number")); |
252b5132 RH |
13777 | if (input_line_pointer[0] == '0') |
13778 | { | |
13779 | if (input_line_pointer[1] == 'x') | |
13780 | { | |
13781 | input_line_pointer += 2; | |
3882b010 | 13782 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
13783 | { |
13784 | val <<= 4; | |
13785 | val |= hex_value (*input_line_pointer++); | |
13786 | } | |
13787 | return negative ? -val : val; | |
13788 | } | |
13789 | else | |
13790 | { | |
13791 | ++input_line_pointer; | |
3882b010 | 13792 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13793 | { |
13794 | val <<= 3; | |
13795 | val |= *input_line_pointer++ - '0'; | |
13796 | } | |
13797 | return negative ? -val : val; | |
13798 | } | |
13799 | } | |
3882b010 | 13800 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13801 | { |
13802 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
13803 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 13804 | as_warn (_("invalid number")); |
252b5132 RH |
13805 | return -1; |
13806 | } | |
3882b010 | 13807 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13808 | { |
13809 | val *= 10; | |
13810 | val += *input_line_pointer++ - '0'; | |
13811 | } | |
13812 | return negative ? -val : val; | |
13813 | } | |
13814 | ||
13815 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
13816 | is an initial number which is the ECOFF file index. In the non-ECOFF |
13817 | case .file implies DWARF-2. */ | |
13818 | ||
13819 | static void | |
17a2f251 | 13820 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 13821 | { |
ecb4347a DJ |
13822 | static int first_file_directive = 0; |
13823 | ||
c5dd6aab DJ |
13824 | if (ECOFF_DEBUGGING) |
13825 | { | |
13826 | get_number (); | |
13827 | s_app_file (0); | |
13828 | } | |
13829 | else | |
ecb4347a DJ |
13830 | { |
13831 | char *filename; | |
13832 | ||
13833 | filename = dwarf2_directive_file (0); | |
13834 | ||
13835 | /* Versions of GCC up to 3.1 start files with a ".file" | |
13836 | directive even for stabs output. Make sure that this | |
13837 | ".file" is handled. Note that you need a version of GCC | |
13838 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
13839 | if (filename != NULL && ! first_file_directive) | |
13840 | { | |
13841 | (void) new_logical_line (filename, -1); | |
13842 | s_app_file_string (filename); | |
13843 | } | |
13844 | first_file_directive = 1; | |
13845 | } | |
c5dd6aab DJ |
13846 | } |
13847 | ||
13848 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
13849 | |
13850 | static void | |
17a2f251 | 13851 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 13852 | { |
c5dd6aab DJ |
13853 | if (!ECOFF_DEBUGGING) |
13854 | dwarf2_directive_loc (0); | |
252b5132 RH |
13855 | } |
13856 | ||
252b5132 RH |
13857 | /* The .end directive. */ |
13858 | ||
13859 | static void | |
17a2f251 | 13860 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
13861 | { |
13862 | symbolS *p; | |
252b5132 | 13863 | |
7a621144 DJ |
13864 | /* Following functions need their own .frame and .cprestore directives. */ |
13865 | mips_frame_reg_valid = 0; | |
13866 | mips_cprestore_valid = 0; | |
13867 | ||
252b5132 RH |
13868 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
13869 | { | |
13870 | p = get_symbol (); | |
13871 | demand_empty_rest_of_line (); | |
13872 | } | |
13873 | else | |
13874 | p = NULL; | |
13875 | ||
14949570 | 13876 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
13877 | as_warn (_(".end not in text section")); |
13878 | ||
13879 | if (!cur_proc_ptr) | |
13880 | { | |
13881 | as_warn (_(".end directive without a preceding .ent directive.")); | |
13882 | demand_empty_rest_of_line (); | |
13883 | return; | |
13884 | } | |
13885 | ||
13886 | if (p != NULL) | |
13887 | { | |
13888 | assert (S_GET_NAME (p)); | |
13889 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym))) | |
13890 | as_warn (_(".end symbol does not match .ent symbol.")); | |
ecb4347a DJ |
13891 | |
13892 | if (debug_type == DEBUG_STABS) | |
13893 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
13894 | S_GET_NAME (p)); | |
252b5132 RH |
13895 | } |
13896 | else | |
13897 | as_warn (_(".end directive missing or unknown symbol")); | |
13898 | ||
ecb4347a DJ |
13899 | #ifdef OBJ_ELF |
13900 | /* Generate a .pdr section. */ | |
dcd410fe RO |
13901 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING |
13902 | && mips_flag_pdr) | |
ecb4347a DJ |
13903 | { |
13904 | segT saved_seg = now_seg; | |
13905 | subsegT saved_subseg = now_subseg; | |
13906 | valueT dot; | |
13907 | expressionS exp; | |
13908 | char *fragp; | |
252b5132 | 13909 | |
ecb4347a | 13910 | dot = frag_now_fix (); |
252b5132 RH |
13911 | |
13912 | #ifdef md_flush_pending_output | |
ecb4347a | 13913 | md_flush_pending_output (); |
252b5132 RH |
13914 | #endif |
13915 | ||
ecb4347a DJ |
13916 | assert (pdr_seg); |
13917 | subseg_set (pdr_seg, 0); | |
252b5132 | 13918 | |
ecb4347a DJ |
13919 | /* Write the symbol. */ |
13920 | exp.X_op = O_symbol; | |
13921 | exp.X_add_symbol = p; | |
13922 | exp.X_add_number = 0; | |
13923 | emit_expr (&exp, 4); | |
252b5132 | 13924 | |
ecb4347a | 13925 | fragp = frag_more (7 * 4); |
252b5132 | 13926 | |
17a2f251 TS |
13927 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
13928 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
13929 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
13930 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
13931 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
13932 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
13933 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 13934 | |
ecb4347a DJ |
13935 | subseg_set (saved_seg, saved_subseg); |
13936 | } | |
13937 | #endif /* OBJ_ELF */ | |
252b5132 RH |
13938 | |
13939 | cur_proc_ptr = NULL; | |
13940 | } | |
13941 | ||
13942 | /* The .aent and .ent directives. */ | |
13943 | ||
13944 | static void | |
17a2f251 | 13945 | s_mips_ent (int aent) |
252b5132 | 13946 | { |
252b5132 | 13947 | symbolS *symbolP; |
252b5132 RH |
13948 | |
13949 | symbolP = get_symbol (); | |
13950 | if (*input_line_pointer == ',') | |
f9419b05 | 13951 | ++input_line_pointer; |
252b5132 | 13952 | SKIP_WHITESPACE (); |
3882b010 | 13953 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 13954 | || *input_line_pointer == '-') |
874e8986 | 13955 | get_number (); |
252b5132 | 13956 | |
14949570 | 13957 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
13958 | as_warn (_(".ent or .aent not in text section.")); |
13959 | ||
13960 | if (!aent && cur_proc_ptr) | |
9a41af64 | 13961 | as_warn (_("missing .end")); |
252b5132 RH |
13962 | |
13963 | if (!aent) | |
13964 | { | |
7a621144 DJ |
13965 | /* This function needs its own .frame and .cprestore directives. */ |
13966 | mips_frame_reg_valid = 0; | |
13967 | mips_cprestore_valid = 0; | |
13968 | ||
252b5132 RH |
13969 | cur_proc_ptr = &cur_proc; |
13970 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
13971 | ||
13972 | cur_proc_ptr->isym = symbolP; | |
13973 | ||
49309057 | 13974 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
252b5132 | 13975 | |
f9419b05 | 13976 | ++numprocs; |
ecb4347a DJ |
13977 | |
13978 | if (debug_type == DEBUG_STABS) | |
13979 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
13980 | S_GET_NAME (symbolP)); | |
252b5132 RH |
13981 | } |
13982 | ||
13983 | demand_empty_rest_of_line (); | |
13984 | } | |
13985 | ||
13986 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 13987 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 13988 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 13989 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
13990 | symbol table (in the mdebug section). */ |
13991 | ||
13992 | static void | |
17a2f251 | 13993 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13994 | { |
ecb4347a DJ |
13995 | #ifdef OBJ_ELF |
13996 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
13997 | { | |
13998 | long val; | |
252b5132 | 13999 | |
ecb4347a DJ |
14000 | if (cur_proc_ptr == (procS *) NULL) |
14001 | { | |
14002 | as_warn (_(".frame outside of .ent")); | |
14003 | demand_empty_rest_of_line (); | |
14004 | return; | |
14005 | } | |
252b5132 | 14006 | |
ecb4347a DJ |
14007 | cur_proc_ptr->frame_reg = tc_get_register (1); |
14008 | ||
14009 | SKIP_WHITESPACE (); | |
14010 | if (*input_line_pointer++ != ',' | |
14011 | || get_absolute_expression_and_terminator (&val) != ',') | |
14012 | { | |
14013 | as_warn (_("Bad .frame directive")); | |
14014 | --input_line_pointer; | |
14015 | demand_empty_rest_of_line (); | |
14016 | return; | |
14017 | } | |
252b5132 | 14018 | |
ecb4347a DJ |
14019 | cur_proc_ptr->frame_offset = val; |
14020 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 14021 | |
252b5132 | 14022 | demand_empty_rest_of_line (); |
252b5132 | 14023 | } |
ecb4347a DJ |
14024 | else |
14025 | #endif /* OBJ_ELF */ | |
14026 | s_ignore (ignore); | |
252b5132 RH |
14027 | } |
14028 | ||
bdaaa2e1 KH |
14029 | /* The .fmask and .mask directives. If the mdebug section is present |
14030 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 14031 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 14032 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
14033 | make reference to the ecoff symbol table (in the mdebug section). */ |
14034 | ||
14035 | static void | |
17a2f251 | 14036 | s_mips_mask (int reg_type) |
252b5132 | 14037 | { |
ecb4347a DJ |
14038 | #ifdef OBJ_ELF |
14039 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
252b5132 | 14040 | { |
ecb4347a | 14041 | long mask, off; |
252b5132 | 14042 | |
ecb4347a DJ |
14043 | if (cur_proc_ptr == (procS *) NULL) |
14044 | { | |
14045 | as_warn (_(".mask/.fmask outside of .ent")); | |
14046 | demand_empty_rest_of_line (); | |
14047 | return; | |
14048 | } | |
252b5132 | 14049 | |
ecb4347a DJ |
14050 | if (get_absolute_expression_and_terminator (&mask) != ',') |
14051 | { | |
14052 | as_warn (_("Bad .mask/.fmask directive")); | |
14053 | --input_line_pointer; | |
14054 | demand_empty_rest_of_line (); | |
14055 | return; | |
14056 | } | |
252b5132 | 14057 | |
ecb4347a DJ |
14058 | off = get_absolute_expression (); |
14059 | ||
14060 | if (reg_type == 'F') | |
14061 | { | |
14062 | cur_proc_ptr->fpreg_mask = mask; | |
14063 | cur_proc_ptr->fpreg_offset = off; | |
14064 | } | |
14065 | else | |
14066 | { | |
14067 | cur_proc_ptr->reg_mask = mask; | |
14068 | cur_proc_ptr->reg_offset = off; | |
14069 | } | |
14070 | ||
14071 | demand_empty_rest_of_line (); | |
252b5132 RH |
14072 | } |
14073 | else | |
ecb4347a DJ |
14074 | #endif /* OBJ_ELF */ |
14075 | s_ignore (reg_type); | |
252b5132 RH |
14076 | } |
14077 | ||
14078 | /* The .loc directive. */ | |
14079 | ||
14080 | #if 0 | |
14081 | static void | |
17a2f251 | 14082 | s_loc (int x) |
252b5132 RH |
14083 | { |
14084 | symbolS *symbolP; | |
14085 | int lineno; | |
14086 | int addroff; | |
14087 | ||
14088 | assert (now_seg == text_section); | |
14089 | ||
14090 | lineno = get_number (); | |
14091 | addroff = frag_now_fix (); | |
14092 | ||
14093 | symbolP = symbol_new ("", N_SLINE, addroff, frag_now); | |
14094 | S_SET_TYPE (symbolP, N_SLINE); | |
14095 | S_SET_OTHER (symbolP, 0); | |
14096 | S_SET_DESC (symbolP, lineno); | |
14097 | symbolP->sy_segment = now_seg; | |
14098 | } | |
14099 | #endif | |
e7af610e | 14100 | |
316f5878 RS |
14101 | /* A table describing all the processors gas knows about. Names are |
14102 | matched in the order listed. | |
e7af610e | 14103 | |
316f5878 RS |
14104 | To ease comparison, please keep this table in the same order as |
14105 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
14106 | static const struct mips_cpu_info mips_cpu_info_table[] = |
14107 | { | |
316f5878 RS |
14108 | /* Entries for generic ISAs */ |
14109 | { "mips1", 1, ISA_MIPS1, CPU_R3000 }, | |
14110 | { "mips2", 1, ISA_MIPS2, CPU_R6000 }, | |
14111 | { "mips3", 1, ISA_MIPS3, CPU_R4000 }, | |
14112 | { "mips4", 1, ISA_MIPS4, CPU_R8000 }, | |
14113 | { "mips5", 1, ISA_MIPS5, CPU_MIPS5 }, | |
14114 | { "mips32", 1, ISA_MIPS32, CPU_MIPS32 }, | |
af7ee8bf | 14115 | { "mips32r2", 1, ISA_MIPS32R2, CPU_MIPS32R2 }, |
316f5878 | 14116 | { "mips64", 1, ISA_MIPS64, CPU_MIPS64 }, |
5f74bc13 | 14117 | { "mips64r2", 1, ISA_MIPS64R2, CPU_MIPS64R2 }, |
316f5878 RS |
14118 | |
14119 | /* MIPS I */ | |
14120 | { "r3000", 0, ISA_MIPS1, CPU_R3000 }, | |
14121 | { "r2000", 0, ISA_MIPS1, CPU_R3000 }, | |
14122 | { "r3900", 0, ISA_MIPS1, CPU_R3900 }, | |
14123 | ||
14124 | /* MIPS II */ | |
14125 | { "r6000", 0, ISA_MIPS2, CPU_R6000 }, | |
14126 | ||
14127 | /* MIPS III */ | |
14128 | { "r4000", 0, ISA_MIPS3, CPU_R4000 }, | |
14129 | { "r4010", 0, ISA_MIPS2, CPU_R4010 }, | |
14130 | { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, | |
14131 | { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, | |
60b63b72 RS |
14132 | { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, |
14133 | { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, | |
14134 | { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, | |
316f5878 RS |
14135 | { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, |
14136 | { "r4400", 0, ISA_MIPS3, CPU_R4400 }, | |
14137 | { "r4600", 0, ISA_MIPS3, CPU_R4600 }, | |
14138 | { "orion", 0, ISA_MIPS3, CPU_R4600 }, | |
14139 | { "r4650", 0, ISA_MIPS3, CPU_R4650 }, | |
14140 | ||
14141 | /* MIPS IV */ | |
14142 | { "r8000", 0, ISA_MIPS4, CPU_R8000 }, | |
14143 | { "r10000", 0, ISA_MIPS4, CPU_R10000 }, | |
14144 | { "r12000", 0, ISA_MIPS4, CPU_R12000 }, | |
14145 | { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, | |
60b63b72 RS |
14146 | { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, |
14147 | { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, | |
316f5878 RS |
14148 | { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, |
14149 | { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, | |
14150 | { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, | |
14151 | { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, | |
14152 | { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, | |
5a7ea749 RS |
14153 | { "rm7000", 0, ISA_MIPS4, CPU_RM7000 }, |
14154 | { "rm9000", 0, ISA_MIPS4, CPU_RM7000 }, | |
316f5878 RS |
14155 | |
14156 | /* MIPS 32 */ | |
fef14a42 | 14157 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32 }, |
316f5878 RS |
14158 | { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, |
14159 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, | |
e7af610e | 14160 | |
316f5878 RS |
14161 | /* MIPS 64 */ |
14162 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, | |
14163 | { "20kc", 0, ISA_MIPS64, CPU_MIPS64 }, | |
e7af610e | 14164 | |
c7a23324 | 14165 | /* Broadcom SB-1 CPU core */ |
316f5878 | 14166 | { "sb1", 0, ISA_MIPS64, CPU_SB1 }, |
e7af610e | 14167 | |
316f5878 RS |
14168 | /* End marker */ |
14169 | { NULL, 0, 0, 0 } | |
14170 | }; | |
e7af610e | 14171 | |
84ea6cf2 | 14172 | |
316f5878 RS |
14173 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
14174 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 14175 | |
316f5878 | 14176 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 14177 | |
b34976b6 | 14178 | static bfd_boolean |
17a2f251 | 14179 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
14180 | { |
14181 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
14182 | given++, canonical++; | |
14183 | ||
14184 | return ((*given == 0 && *canonical == 0) | |
14185 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
14186 | } | |
14187 | ||
14188 | ||
14189 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
14190 | CPU name. We've traditionally allowed a lot of variation here. | |
14191 | ||
14192 | Note: this function is shared between GCC and GAS. */ | |
14193 | ||
b34976b6 | 14194 | static bfd_boolean |
17a2f251 | 14195 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
14196 | { |
14197 | /* First see if the name matches exactly, or with a final "000" | |
14198 | turned into "k". */ | |
14199 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 14200 | return TRUE; |
316f5878 RS |
14201 | |
14202 | /* If not, try comparing based on numerical designation alone. | |
14203 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
14204 | if (TOLOWER (*given) == 'r') | |
14205 | given++; | |
14206 | if (!ISDIGIT (*given)) | |
b34976b6 | 14207 | return FALSE; |
316f5878 RS |
14208 | |
14209 | /* Skip over some well-known prefixes in the canonical name, | |
14210 | hoping to find a number there too. */ | |
14211 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
14212 | canonical += 2; | |
14213 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
14214 | canonical += 2; | |
14215 | else if (TOLOWER (canonical[0]) == 'r') | |
14216 | canonical += 1; | |
14217 | ||
14218 | return mips_strict_matching_cpu_name_p (canonical, given); | |
14219 | } | |
14220 | ||
14221 | ||
14222 | /* Parse an option that takes the name of a processor as its argument. | |
14223 | OPTION is the name of the option and CPU_STRING is the argument. | |
14224 | Return the corresponding processor enumeration if the CPU_STRING is | |
14225 | recognized, otherwise report an error and return null. | |
14226 | ||
14227 | A similar function exists in GCC. */ | |
e7af610e NC |
14228 | |
14229 | static const struct mips_cpu_info * | |
17a2f251 | 14230 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 14231 | { |
316f5878 | 14232 | const struct mips_cpu_info *p; |
e7af610e | 14233 | |
316f5878 RS |
14234 | /* 'from-abi' selects the most compatible architecture for the given |
14235 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
14236 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
14237 | version. Look first at the -mgp options, if given, otherwise base | |
14238 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 14239 | |
316f5878 RS |
14240 | Treat NO_ABI like the EABIs. One reason to do this is that the |
14241 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
14242 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
14243 | 'mips64', just as we did in the days before 'from-abi'. */ | |
14244 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
14245 | { | |
14246 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
14247 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
14248 | ||
14249 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
14250 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
14251 | ||
14252 | if (file_mips_gp32 >= 0) | |
14253 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
14254 | ||
14255 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
14256 | ? ISA_MIPS3 | |
14257 | : ISA_MIPS1); | |
14258 | } | |
14259 | ||
14260 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
14261 | if (strcasecmp (cpu_string, "default") == 0) | |
14262 | return 0; | |
14263 | ||
14264 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
14265 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
14266 | return p; | |
14267 | ||
14268 | as_bad ("Bad value (%s) for %s", cpu_string, option); | |
14269 | return 0; | |
e7af610e NC |
14270 | } |
14271 | ||
316f5878 RS |
14272 | /* Return the canonical processor information for ISA (a member of the |
14273 | ISA_MIPS* enumeration). */ | |
14274 | ||
e7af610e | 14275 | static const struct mips_cpu_info * |
17a2f251 | 14276 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
14277 | { |
14278 | int i; | |
14279 | ||
14280 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
14281 | if (mips_cpu_info_table[i].is_isa | |
316f5878 | 14282 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
14283 | return (&mips_cpu_info_table[i]); |
14284 | ||
e972090a | 14285 | return NULL; |
e7af610e | 14286 | } |
fef14a42 TS |
14287 | |
14288 | static const struct mips_cpu_info * | |
17a2f251 | 14289 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
14290 | { |
14291 | int i; | |
14292 | ||
14293 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
14294 | if (arch == mips_cpu_info_table[i].cpu) | |
14295 | return (&mips_cpu_info_table[i]); | |
14296 | ||
14297 | return NULL; | |
14298 | } | |
316f5878 RS |
14299 | \f |
14300 | static void | |
17a2f251 | 14301 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
14302 | { |
14303 | if (*first_p) | |
14304 | { | |
14305 | fprintf (stream, "%24s", ""); | |
14306 | *col_p = 24; | |
14307 | } | |
14308 | else | |
14309 | { | |
14310 | fprintf (stream, ", "); | |
14311 | *col_p += 2; | |
14312 | } | |
e7af610e | 14313 | |
316f5878 RS |
14314 | if (*col_p + strlen (string) > 72) |
14315 | { | |
14316 | fprintf (stream, "\n%24s", ""); | |
14317 | *col_p = 24; | |
14318 | } | |
14319 | ||
14320 | fprintf (stream, "%s", string); | |
14321 | *col_p += strlen (string); | |
14322 | ||
14323 | *first_p = 0; | |
14324 | } | |
14325 | ||
14326 | void | |
17a2f251 | 14327 | md_show_usage (FILE *stream) |
e7af610e | 14328 | { |
316f5878 RS |
14329 | int column, first; |
14330 | size_t i; | |
14331 | ||
14332 | fprintf (stream, _("\ | |
14333 | MIPS options:\n\ | |
14334 | -membedded-pic generate embedded position independent code\n\ | |
14335 | -EB generate big endian output\n\ | |
14336 | -EL generate little endian output\n\ | |
14337 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
14338 | -G NUM allow referencing objects up to NUM bytes\n\ | |
14339 | implicitly with the gp register [default 8]\n")); | |
14340 | fprintf (stream, _("\ | |
14341 | -mips1 generate MIPS ISA I instructions\n\ | |
14342 | -mips2 generate MIPS ISA II instructions\n\ | |
14343 | -mips3 generate MIPS ISA III instructions\n\ | |
14344 | -mips4 generate MIPS ISA IV instructions\n\ | |
14345 | -mips5 generate MIPS ISA V instructions\n\ | |
14346 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 14347 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 | 14348 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 14349 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
316f5878 RS |
14350 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
14351 | ||
14352 | first = 1; | |
e7af610e NC |
14353 | |
14354 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
14355 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
14356 | show (stream, "from-abi", &column, &first); | |
14357 | fputc ('\n', stream); | |
e7af610e | 14358 | |
316f5878 RS |
14359 | fprintf (stream, _("\ |
14360 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
14361 | -no-mCPU don't generate code specific to CPU.\n\ | |
14362 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
14363 | ||
14364 | first = 1; | |
14365 | ||
14366 | show (stream, "3900", &column, &first); | |
14367 | show (stream, "4010", &column, &first); | |
14368 | show (stream, "4100", &column, &first); | |
14369 | show (stream, "4650", &column, &first); | |
14370 | fputc ('\n', stream); | |
14371 | ||
14372 | fprintf (stream, _("\ | |
14373 | -mips16 generate mips16 instructions\n\ | |
14374 | -no-mips16 do not generate mips16 instructions\n")); | |
14375 | fprintf (stream, _("\ | |
d766e8ec | 14376 | -mfix-vr4120 work around certain VR4120 errata\n\ |
316f5878 RS |
14377 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
14378 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
14379 | -O0 remove unneeded NOPs, do not swap branches\n\ | |
14380 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
14381 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ |
14382 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ | |
14383 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
14384 | #ifdef OBJ_ELF | |
14385 | fprintf (stream, _("\ | |
14386 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
14387 | -non_shared do not generate position independent code\n\ | |
14388 | -xgot assume a 32 bit GOT\n\ | |
dcd410fe | 14389 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
316f5878 RS |
14390 | -mabi=ABI create ABI conformant object file for:\n")); |
14391 | ||
14392 | first = 1; | |
14393 | ||
14394 | show (stream, "32", &column, &first); | |
14395 | show (stream, "o64", &column, &first); | |
14396 | show (stream, "n32", &column, &first); | |
14397 | show (stream, "64", &column, &first); | |
14398 | show (stream, "eabi", &column, &first); | |
14399 | ||
14400 | fputc ('\n', stream); | |
14401 | ||
14402 | fprintf (stream, _("\ | |
14403 | -32 create o32 ABI object file (default)\n\ | |
14404 | -n32 create n32 ABI object file\n\ | |
14405 | -64 create 64 ABI object file\n")); | |
14406 | #endif | |
e7af610e | 14407 | } |
14e777e0 KB |
14408 | |
14409 | enum dwarf2_format | |
17a2f251 | 14410 | mips_dwarf2_format (void) |
14e777e0 KB |
14411 | { |
14412 | if (mips_abi == N64_ABI) | |
1de5b6a1 AO |
14413 | { |
14414 | #ifdef TE_IRIX | |
14415 | return dwarf2_format_64bit_irix; | |
14416 | #else | |
14417 | return dwarf2_format_64bit; | |
14418 | #endif | |
14419 | } | |
14e777e0 KB |
14420 | else |
14421 | return dwarf2_format_32bit; | |
14422 | } | |
73369e65 EC |
14423 | |
14424 | int | |
14425 | mips_dwarf2_addr_size (void) | |
14426 | { | |
14427 | if (mips_abi == N64_ABI) | |
14428 | return 8; | |
73369e65 EC |
14429 | else |
14430 | return 4; | |
14431 | } |