Commit | Line | Data |
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3d3c5039 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
b9129c6f | 2 | Copyright (C) 1993, 1994, 1995, 1996, 1997 Free Software Foundation, Inc. |
3d3c5039 ILT |
3 | Contributed by the OSF and Ralph Campbell. |
4 | Written by Keith Knowles and Ralph Campbell, working independently. | |
8358c818 ILT |
5 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus |
6 | Support. | |
3d3c5039 ILT |
7 | |
8 | This file is part of GAS. | |
9 | ||
10 | GAS is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2, or (at your option) | |
13 | any later version. | |
14 | ||
15 | GAS is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
fb251650 ILT |
21 | along with GAS; see the file COPYING. If not, write to the Free |
22 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
23 | 02111-1307, USA. */ | |
3d3c5039 ILT |
24 | |
25 | #include "as.h" | |
8358c818 | 26 | #include "config.h" |
9da4c5d1 | 27 | #include "subsegs.h" |
3d3c5039 ILT |
28 | |
29 | #include <ctype.h> | |
30 | ||
1dc1e798 | 31 | #ifdef USE_STDARG |
3d3c5039 | 32 | #include <stdarg.h> |
1dc1e798 KR |
33 | #endif |
34 | #ifdef USE_VARARGS | |
3d3c5039 | 35 | #include <varargs.h> |
1dc1e798 | 36 | #endif |
3d3c5039 | 37 | |
918692a5 | 38 | #include "opcode/mips.h" |
efec4a28 DP |
39 | #include "itbl-ops.h" |
40 | ||
41 | #ifdef DEBUG | |
42 | #define DBG(x) printf x | |
43 | #else | |
44 | #define DBG(x) | |
45 | #endif | |
3d3c5039 | 46 | |
739708fa KR |
47 | #ifdef OBJ_MAYBE_ELF |
48 | /* Clean up namespace so we can include obj-elf.h too. */ | |
7cd06f44 | 49 | static int mips_output_flavor PARAMS ((void)); |
739708fa KR |
50 | static int mips_output_flavor () { return OUTPUT_FLAVOR; } |
51 | #undef OBJ_PROCESS_STAB | |
52 | #undef OUTPUT_FLAVOR | |
53 | #undef S_GET_ALIGN | |
54 | #undef S_GET_SIZE | |
55 | #undef S_SET_ALIGN | |
56 | #undef S_SET_SIZE | |
57 | #undef TARGET_SYMBOL_FIELDS | |
58 | #undef obj_frob_file | |
cc5703cd | 59 | #undef obj_frob_file_after_relocs |
739708fa KR |
60 | #undef obj_frob_symbol |
61 | #undef obj_pop_insert | |
62 | #undef obj_sec_sym_ok_for_reloc | |
63 | ||
64 | #include "obj-elf.h" | |
65 | /* Fix any of them that we actually care about. */ | |
66 | #undef OUTPUT_FLAVOR | |
67 | #define OUTPUT_FLAVOR mips_output_flavor() | |
68 | #endif | |
69 | ||
70 | #if defined (OBJ_ELF) | |
f2a663d3 | 71 | #include "elf/mips.h" |
1dc1e798 | 72 | #endif |
f2a663d3 | 73 | |
739708fa | 74 | #ifndef ECOFF_DEBUGGING |
c625fc23 | 75 | #define NO_ECOFF_DEBUGGING |
739708fa KR |
76 | #define ECOFF_DEBUGGING 0 |
77 | #endif | |
78 | ||
22ba90ce ILT |
79 | #include "ecoff.h" |
80 | ||
a8aed9dd | 81 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
f2a663d3 | 82 | static char *mips_regmask_frag; |
a8aed9dd | 83 | #endif |
f2a663d3 | 84 | |
3d3c5039 | 85 | #define AT 1 |
cc5703cd | 86 | #define TREG 24 |
9226253a | 87 | #define PIC_CALL_REG 25 |
b2b8c24e ILT |
88 | #define KT0 26 |
89 | #define KT1 27 | |
670a50eb | 90 | #define GP 28 |
9226253a ILT |
91 | #define SP 29 |
92 | #define FP 30 | |
3d3c5039 ILT |
93 | #define RA 31 |
94 | ||
cc5703cd ILT |
95 | #define ILLEGAL_REG (32) |
96 | ||
af942793 SS |
97 | /* Allow override of standard little-endian ECOFF format. */ |
98 | ||
99 | #ifndef ECOFF_LITTLE_FORMAT | |
100 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
101 | #endif | |
102 | ||
1dc1e798 | 103 | extern int target_big_endian; |
88225433 | 104 | |
7f9880e5 ILT |
105 | /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the |
106 | 32 bit ABI. This has no meaning for ECOFF. */ | |
107 | static int mips_64; | |
108 | ||
04cb3372 | 109 | /* The default target format to use. */ |
1dc1e798 KR |
110 | const char * |
111 | mips_target_format () | |
112 | { | |
113 | switch (OUTPUT_FLAVOR) | |
114 | { | |
115 | case bfd_target_aout_flavour: | |
116 | return target_big_endian ? "a.out-mips-big" : "a.out-mips-little"; | |
117 | case bfd_target_ecoff_flavour: | |
af942793 | 118 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; |
1dc1e798 | 119 | case bfd_target_elf_flavour: |
7f9880e5 ILT |
120 | return (target_big_endian |
121 | ? (mips_64 ? "elf64-bigmips" : "elf32-bigmips") | |
122 | : (mips_64 ? "elf64-littlemips" : "elf32-littlemips")); | |
1dc1e798 KR |
123 | default: |
124 | abort (); | |
125 | } | |
126 | } | |
04cb3372 | 127 | |
d2c71068 | 128 | /* The name of the readonly data section. */ |
1dc1e798 KR |
129 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \ |
130 | ? ".data" \ | |
131 | : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ | |
132 | ? ".rdata" \ | |
133 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ | |
134 | ? ".rodata" \ | |
135 | : (abort (), "")) | |
d2c71068 | 136 | |
3c83da8a JW |
137 | /* This is the set of options which may be modified by the .set |
138 | pseudo-op. We use a struct so that .set push and .set pop are more | |
139 | reliable. */ | |
140 | ||
141 | struct mips_set_options | |
142 | { | |
143 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 | |
144 | if it has not been initialized. Changed by `.set mipsN', and the | |
145 | -mipsN command line option, and the default CPU. */ | |
146 | int isa; | |
147 | /* Whether we are assembling for the mips16 processor. 0 if we are | |
148 | not, 1 if we are, and -1 if the value has not been initialized. | |
149 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
150 | -nomips16 command line options, and the default CPU. */ | |
151 | int mips16; | |
152 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
153 | reorder' and `.set noreorder'. */ | |
154 | int noreorder; | |
155 | /* Non-zero if we should not permit the $at ($1) register to be used | |
156 | in instructions. Changed by `.set at' and `.set noat'. */ | |
157 | int noat; | |
158 | /* Non-zero if we should warn when a macro instruction expands into | |
159 | more than one machine instruction. Changed by `.set nomacro' and | |
160 | `.set macro'. */ | |
161 | int warn_about_macros; | |
162 | /* Non-zero if we should not move instructions. Changed by `.set | |
163 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
164 | int nomove; | |
165 | /* Non-zero if we should not optimize branches by moving the target | |
166 | of the branch into the delay slot. Actually, we don't perform | |
167 | this optimization anyhow. Changed by `.set bopt' and `.set | |
168 | nobopt'. */ | |
169 | int nobopt; | |
170 | /* Non-zero if we should not autoextend mips16 instructions. | |
171 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
172 | int noautoextend; | |
173 | }; | |
174 | ||
175 | /* This is the struct we use to hold the current set of options. Note | |
176 | that we must set the isa and mips16 fields to -1 to indicate that | |
177 | they have not been initialized. */ | |
178 | ||
179 | static struct mips_set_options mips_opts = { -1, -1 }; | |
180 | ||
1aa6938e ILT |
181 | /* These variables are filled in with the masks of registers used. |
182 | The object format code reads them and puts them in the appropriate | |
183 | place. */ | |
184 | unsigned long mips_gprmask; | |
185 | unsigned long mips_cprmask[4]; | |
186 | ||
1051c97f ILT |
187 | /* MIPS ISA we are using for this output file. */ |
188 | static int file_mips_isa; | |
189 | ||
8c63448a | 190 | /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */ |
4bb0cc41 | 191 | static int mips_cpu = -1; |
8c63448a | 192 | |
b2b8c24e ILT |
193 | /* Whether the 4650 instructions (mad/madu) are permitted. */ |
194 | static int mips_4650 = -1; | |
195 | ||
e532b44c ILT |
196 | /* Whether the 4010 instructions are permitted. */ |
197 | static int mips_4010 = -1; | |
198 | ||
c625fc23 JSC |
199 | /* Whether the 4100 MADD16 and DMADD16 are permitted. */ |
200 | static int mips_4100 = -1; | |
201 | ||
276c2d7d GRK |
202 | /* start-sanitize-r5900 */ |
203 | /* Whether Toshiba r5900 instructions are permitted. */ | |
204 | static int mips_5900 = -1; | |
205 | /* end-sanitize-r5900 */ | |
206 | ||
5c6f5923 GRK |
207 | /* Whether Toshiba r3900 instructions are permitted. */ |
208 | static int mips_3900 = -1; | |
209 | ||
210 | /* Whether the processor uses hardware interlocks to protect | |
211 | reads from the HI and LO registers, and thus does not | |
212 | require nops to be inserted. */ | |
213 | static int hilo_interlocks = -1; | |
214 | ||
215 | /* Whether the processor uses hardware interlocks to protect | |
216 | reads from the GPRs, and thus does not | |
e532b44c | 217 | require nops to be inserted. */ |
5c6f5923 | 218 | static int gpr_interlocks = -1; |
e532b44c | 219 | |
5c6f5923 | 220 | /* As with other "interlocks" this is used by hardware that has FP |
344a8d61 | 221 | (co-processor) interlocks. */ |
efec4a28 | 222 | /* Itbl support may require additional care here. */ |
344a8d61 JSC |
223 | static int cop_interlocks = -1; |
224 | ||
d9aba805 ILT |
225 | /* MIPS PIC level. */ |
226 | ||
227 | enum mips_pic_level | |
228 | { | |
229 | /* Do not generate PIC code. */ | |
230 | NO_PIC, | |
231 | ||
232 | /* Generate PIC code as in Irix 4. This is not implemented, and I'm | |
233 | not sure what it is supposed to do. */ | |
234 | IRIX4_PIC, | |
235 | ||
236 | /* Generate PIC code as in the SVR4 MIPS ABI. */ | |
237 | SVR4_PIC, | |
238 | ||
239 | /* Generate PIC code without using a global offset table: the data | |
240 | segment has a maximum size of 64K, all data references are off | |
241 | the $gp register, and all text references are PC relative. This | |
242 | is used on some embedded systems. */ | |
243 | EMBEDDED_PIC | |
244 | }; | |
245 | ||
246 | static enum mips_pic_level mips_pic; | |
9226253a | 247 | |
fb251650 ILT |
248 | /* 1 if we should generate 32 bit offsets from the GP register in |
249 | SVR4_PIC mode. Currently has no meaning in other modes. */ | |
250 | static int mips_big_got; | |
251 | ||
8ea7f4e8 ILT |
252 | /* 1 if trap instructions should used for overflow rather than break |
253 | instructions. */ | |
254 | static int mips_trap; | |
255 | ||
3c83da8a | 256 | /* Non-zero if any .set noreorder directives were used. */ |
cc5703cd | 257 | |
0dd2d296 | 258 | static int mips_any_noreorder; |
3d3c5039 | 259 | |
670a50eb ILT |
260 | /* The size of the small data section. */ |
261 | static int g_switch_value = 8; | |
42562568 ILT |
262 | /* Whether the -G option was used. */ |
263 | static int g_switch_seen = 0; | |
670a50eb | 264 | |
3d3c5039 ILT |
265 | #define N_RMASK 0xc4 |
266 | #define N_VFP 0xd4 | |
267 | ||
d8a1c247 KR |
268 | /* If we can determine in advance that GP optimization won't be |
269 | possible, we can skip the relaxation stuff that tries to produce | |
270 | GP-relative references. This makes delay slot optimization work | |
271 | better. | |
272 | ||
273 | This function can only provide a guess, but it seems to work for | |
274 | gcc output. If it guesses wrong, the only loss should be in | |
275 | efficiency; it shouldn't introduce any bugs. | |
276 | ||
277 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
278 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
85ce5635 | 279 | static int nopic_need_relax PARAMS ((symbolS *, int)); |
d8a1c247 | 280 | |
3d3c5039 ILT |
281 | /* handle of the OPCODE hash table */ |
282 | static struct hash_control *op_hash = NULL; | |
283 | ||
cc5703cd ILT |
284 | /* The opcode hash table we use for the mips16. */ |
285 | static struct hash_control *mips16_op_hash = NULL; | |
286 | ||
3d3c5039 ILT |
287 | /* This array holds the chars that always start a comment. If the |
288 | pre-processor is disabled, these aren't very useful */ | |
289 | const char comment_chars[] = "#"; | |
290 | ||
291 | /* This array holds the chars that only start a comment at the beginning of | |
292 | a line. If the line seems to have the form '# 123 filename' | |
293 | .line and .file directives will appear in the pre-processed output */ | |
294 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
295 | first line of the input file. This is because the compiler outputs | |
296 | #NO_APP at the beginning of its output. */ | |
297 | /* Also note that C style comments are always supported. */ | |
298 | const char line_comment_chars[] = "#"; | |
299 | ||
300 | /* This array holds machine specific line separator characters. */ | |
301 | const char line_separator_chars[] = ""; | |
302 | ||
303 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
304 | const char EXP_CHARS[] = "eE"; | |
305 | ||
306 | /* Chars that mean this number is a floating point constant */ | |
307 | /* As in 0f12.456 */ | |
308 | /* or 0d1.2345e12 */ | |
309 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
310 | ||
311 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
312 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
313 | but nothing is ideal around here. | |
314 | */ | |
315 | ||
670a50eb | 316 | static char *insn_error; |
3d3c5039 | 317 | |
3d3c5039 | 318 | static int auto_align = 1; |
becfe05e | 319 | |
9226253a ILT |
320 | /* When outputting SVR4 PIC code, the assembler needs to know the |
321 | offset in the stack frame from which to restore the $gp register. | |
322 | This is set by the .cprestore pseudo-op, and saved in this | |
323 | variable. */ | |
0dd2d296 ILT |
324 | static offsetT mips_cprestore_offset = -1; |
325 | ||
326 | /* This is the register which holds the stack frame, as set by the | |
327 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
328 | static int mips_frame_reg = SP; | |
9226253a | 329 | |
becfe05e ILT |
330 | /* To output NOP instructions correctly, we need to keep information |
331 | about the previous two instructions. */ | |
332 | ||
0aa07269 ILT |
333 | /* Whether we are optimizing. The default value of 2 means to remove |
334 | unneeded NOPs and swap branch instructions when possible. A value | |
335 | of 1 means to not swap branches. A value of 0 means to always | |
336 | insert NOPs. */ | |
337 | static int mips_optimize = 2; | |
4e95866e | 338 | |
22ba90ce ILT |
339 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is |
340 | equivalent to seeing no -g option at all. */ | |
341 | static int mips_debug = 0; | |
342 | ||
becfe05e ILT |
343 | /* The previous instruction. */ |
344 | static struct mips_cl_insn prev_insn; | |
345 | ||
346 | /* The instruction before prev_insn. */ | |
347 | static struct mips_cl_insn prev_prev_insn; | |
348 | ||
349 | /* If we don't want information for prev_insn or prev_prev_insn, we | |
350 | point the insn_mo field at this dummy integer. */ | |
351 | static const struct mips_opcode dummy_opcode = { 0 }; | |
352 | ||
353 | /* Non-zero if prev_insn is valid. */ | |
354 | static int prev_insn_valid; | |
355 | ||
356 | /* The frag for the previous instruction. */ | |
357 | static struct frag *prev_insn_frag; | |
358 | ||
359 | /* The offset into prev_insn_frag for the previous instruction. */ | |
360 | static long prev_insn_where; | |
361 | ||
a677feeb ILT |
362 | /* The reloc type for the previous instruction, if any. */ |
363 | static bfd_reloc_code_real_type prev_insn_reloc_type; | |
364 | ||
becfe05e ILT |
365 | /* The reloc for the previous instruction, if any. */ |
366 | static fixS *prev_insn_fixp; | |
367 | ||
368 | /* Non-zero if the previous instruction was in a delay slot. */ | |
369 | static int prev_insn_is_delay_slot; | |
4e95866e ILT |
370 | |
371 | /* Non-zero if the previous instruction was in a .set noreorder. */ | |
372 | static int prev_insn_unreordered; | |
373 | ||
cc5703cd ILT |
374 | /* Non-zero if the previous instruction uses an extend opcode (if |
375 | mips16). */ | |
376 | static int prev_insn_extended; | |
377 | ||
4e95866e ILT |
378 | /* Non-zero if the previous previous instruction was in a .set |
379 | noreorder. */ | |
380 | static int prev_prev_insn_unreordered; | |
867a58b3 | 381 | |
4a1cb507 ILT |
382 | /* If this is set, it points to a frag holding nop instructions which |
383 | were inserted before the start of a noreorder section. If those | |
384 | nops turn out to be unnecessary, the size of the frag can be | |
385 | decreased. */ | |
386 | static fragS *prev_nop_frag; | |
387 | ||
388 | /* The number of nop instructions we created in prev_nop_frag. */ | |
389 | static int prev_nop_frag_holds; | |
390 | ||
391 | /* The number of nop instructions that we know we need in | |
392 | prev_nop_frag. */ | |
393 | static int prev_nop_frag_required; | |
394 | ||
395 | /* The number of instructions we've seen since prev_nop_frag. */ | |
396 | static int prev_nop_frag_since; | |
397 | ||
867a58b3 ILT |
398 | /* For ECOFF and ELF, relocations against symbols are done in two |
399 | parts, with a HI relocation and a LO relocation. Each relocation | |
400 | has only 16 bits of space to store an addend. This means that in | |
401 | order for the linker to handle carries correctly, it must be able | |
402 | to locate both the HI and the LO relocation. This means that the | |
403 | relocations must appear in order in the relocation table. | |
404 | ||
405 | In order to implement this, we keep track of each unmatched HI | |
406 | relocation. We then sort them so that they immediately precede the | |
407 | corresponding LO relocation. */ | |
408 | ||
409 | struct mips_hi_fixup | |
410 | { | |
411 | /* Next HI fixup. */ | |
412 | struct mips_hi_fixup *next; | |
413 | /* This fixup. */ | |
414 | fixS *fixp; | |
415 | /* The section this fixup is in. */ | |
416 | segT seg; | |
417 | }; | |
418 | ||
419 | /* The list of unmatched HI relocs. */ | |
420 | ||
421 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
cc5703cd ILT |
422 | |
423 | /* Map normal MIPS register numbers to mips16 register numbers. */ | |
424 | ||
425 | #define X ILLEGAL_REG | |
426 | static const int mips32_to_16_reg_map[] = | |
427 | { | |
428 | X, X, 2, 3, 4, 5, 6, 7, | |
429 | X, X, X, X, X, X, X, X, | |
430 | 0, 1, X, X, X, X, X, X, | |
431 | X, X, X, X, X, X, X, X | |
432 | }; | |
433 | #undef X | |
434 | ||
435 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
436 | ||
437 | static const int mips16_to_32_reg_map[] = | |
438 | { | |
439 | 16, 17, 2, 3, 4, 5, 6, 7 | |
440 | }; | |
3d3c5039 | 441 | \f |
0dd2d296 ILT |
442 | /* Since the MIPS does not have multiple forms of PC relative |
443 | instructions, we do not have to do relaxing as is done on other | |
444 | platforms. However, we do have to handle GP relative addressing | |
445 | correctly, which turns out to be a similar problem. | |
446 | ||
447 | Every macro that refers to a symbol can occur in (at least) two | |
448 | forms, one with GP relative addressing and one without. For | |
449 | example, loading a global variable into a register generally uses | |
23dc1ae3 | 450 | a macro instruction like this: |
0dd2d296 ILT |
451 | lw $4,i |
452 | If i can be addressed off the GP register (this is true if it is in | |
453 | the .sbss or .sdata section, or if it is known to be smaller than | |
454 | the -G argument) this will generate the following instruction: | |
455 | lw $4,i($gp) | |
456 | This instruction will use a GPREL reloc. If i can not be addressed | |
457 | off the GP register, the following instruction sequence will be used: | |
458 | lui $at,i | |
459 | lw $4,i($at) | |
460 | In this case the first instruction will have a HI16 reloc, and the | |
461 | second reloc will have a LO16 reloc. Both relocs will be against | |
462 | the symbol i. | |
463 | ||
464 | The issue here is that we may not know whether i is GP addressable | |
465 | until after we see the instruction that uses it. Therefore, we | |
466 | want to be able to choose the final instruction sequence only at | |
467 | the end of the assembly. This is similar to the way other | |
23dc1ae3 | 468 | platforms choose the size of a PC relative instruction only at the |
0dd2d296 ILT |
469 | end of assembly. |
470 | ||
471 | When generating position independent code we do not use GP | |
23dc1ae3 ILT |
472 | addressing in quite the same way, but the issue still arises as |
473 | external symbols and local symbols must be handled differently. | |
0dd2d296 ILT |
474 | |
475 | We handle these issues by actually generating both possible | |
476 | instruction sequences. The longer one is put in a frag_var with | |
477 | type rs_machine_dependent. We encode what to do with the frag in | |
478 | the subtype field. We encode (1) the number of existing bytes to | |
479 | replace, (2) the number of new bytes to use, (3) the offset from | |
480 | the start of the existing bytes to the first reloc we must generate | |
481 | (that is, the offset is applied from the start of the existing | |
482 | bytes after they are replaced by the new bytes, if any), (4) the | |
483 | offset from the start of the existing bytes to the second reloc, | |
484 | (5) whether a third reloc is needed (the third reloc is always four | |
485 | bytes after the second reloc), and (6) whether to warn if this | |
486 | variant is used (this is sometimes needed if .set nomacro or .set | |
487 | noat is in effect). All these numbers are reasonably small. | |
488 | ||
489 | Generating two instruction sequences must be handled carefully to | |
23dc1ae3 ILT |
490 | ensure that delay slots are handled correctly. Fortunately, there |
491 | are a limited number of cases. When the second instruction | |
492 | sequence is generated, append_insn is directed to maintain the | |
493 | existing delay slot information, so it continues to apply to any | |
494 | code after the second instruction sequence. This means that the | |
495 | second instruction sequence must not impose any requirements not | |
496 | required by the first instruction sequence. | |
0dd2d296 ILT |
497 | |
498 | These variant frags are then handled in functions called by the | |
499 | machine independent code. md_estimate_size_before_relax returns | |
500 | the final size of the frag. md_convert_frag sets up the final form | |
501 | of the frag. tc_gen_reloc adjust the first reloc and adds a second | |
502 | one if needed. */ | |
503 | #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \ | |
504 | ((relax_substateT) \ | |
cc5703cd | 505 | (((old) << 23) \ |
0dd2d296 ILT |
506 | | ((new) << 16) \ |
507 | | (((reloc1) + 64) << 9) \ | |
508 | | (((reloc2) + 64) << 2) \ | |
509 | | ((reloc3) ? (1 << 1) : 0) \ | |
510 | | ((warn) ? 1 : 0))) | |
cc5703cd ILT |
511 | #define RELAX_OLD(i) (((i) >> 23) & 0x7f) |
512 | #define RELAX_NEW(i) (((i) >> 16) & 0x7f) | |
483971bd KR |
513 | #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64) |
514 | #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64) | |
0dd2d296 ILT |
515 | #define RELAX_RELOC3(i) (((i) >> 1) & 1) |
516 | #define RELAX_WARN(i) ((i) & 1) | |
cc5703cd ILT |
517 | |
518 | /* For mips16 code, we use an entirely different form of relaxation. | |
519 | mips16 supports two versions of most instructions which take | |
520 | immediate values: a small one which takes some small value, and a | |
521 | larger one which takes a 16 bit value. Since branches also follow | |
522 | this pattern, relaxing these values is required. | |
523 | ||
524 | We can assemble both mips16 and normal MIPS code in a single | |
525 | object. Therefore, we need to support this type of relaxation at | |
526 | the same time that we support the relaxation described above. We | |
527 | use the high bit of the subtype field to distinguish these cases. | |
528 | ||
a677feeb ILT |
529 | The information we store for this type of relaxation is the |
530 | argument code found in the opcode file for this relocation, whether | |
531 | the user explicitly requested a small or extended form, and whether | |
532 | the relocation is in a jump or jal delay slot. That tells us the | |
533 | size of the value, and how it should be stored. We also store | |
534 | whether the fragment is considered to be extended or not. We also | |
535 | store whether this is known to be a branch to a different section, | |
536 | whether we have tried to relax this frag yet, and whether we have | |
537 | ever extended a PC relative fragment because of a shift count. */ | |
538 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
539 | (0x80000000 \ | |
540 | | ((type) & 0xff) \ | |
541 | | ((small) ? 0x100 : 0) \ | |
542 | | ((ext) ? 0x200 : 0) \ | |
543 | | ((dslot) ? 0x400 : 0) \ | |
544 | | ((jal_dslot) ? 0x800 : 0)) | |
cc5703cd ILT |
545 | #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0) |
546 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) | |
8728fa92 ILT |
547 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) |
548 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
a677feeb ILT |
549 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) |
550 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
551 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
552 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
553 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
554 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
555 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
556 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
0dd2d296 | 557 | \f |
3d3c5039 ILT |
558 | /* Prototypes for static functions. */ |
559 | ||
560 | #ifdef __STDC__ | |
561 | #define internalError() \ | |
562 | as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__) | |
563 | #else | |
564 | #define internalError() as_fatal ("MIPS internal Error"); | |
565 | #endif | |
566 | ||
cc5703cd ILT |
567 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; |
568 | ||
becfe05e | 569 | static int insn_uses_reg PARAMS ((struct mips_cl_insn *ip, |
cc5703cd | 570 | unsigned int reg, enum mips_regclass class)); |
fb251650 | 571 | static int reg_needs_delay PARAMS ((int)); |
3c83da8a | 572 | static void mips16_mark_labels PARAMS ((void)); |
0dd2d296 ILT |
573 | static void append_insn PARAMS ((char *place, |
574 | struct mips_cl_insn * ip, | |
670a50eb | 575 | expressionS * p, |
867a58b3 ILT |
576 | bfd_reloc_code_real_type r, |
577 | boolean)); | |
4a1cb507 | 578 | static void mips_no_prev_insn PARAMS ((int)); |
fbcfacb7 | 579 | static void mips_emit_delays PARAMS ((boolean)); |
c625fc23 | 580 | #ifdef USE_STDARG |
0dd2d296 | 581 | static void macro_build PARAMS ((char *place, int *counter, expressionS * ep, |
3d3c5039 ILT |
582 | const char *name, const char *fmt, |
583 | ...)); | |
c625fc23 JSC |
584 | #else |
585 | static void macro_build (); | |
586 | #endif | |
cc5703cd ILT |
587 | static void mips16_macro_build PARAMS ((char *, int *, expressionS *, |
588 | const char *, const char *, | |
589 | va_list)); | |
0dd2d296 ILT |
590 | static void macro_build_lui PARAMS ((char *place, int *counter, |
591 | expressionS * ep, int regnum)); | |
6e8dda9c | 592 | static void set_at PARAMS ((int *counter, int reg, int unsignedp)); |
670a50eb | 593 | static void check_absolute_expr PARAMS ((struct mips_cl_insn * ip, |
19ed8960 | 594 | expressionS *)); |
d8a1c247 | 595 | static void load_register PARAMS ((int *, int, expressionS *, int)); |
0dd2d296 | 596 | static void load_address PARAMS ((int *counter, int reg, expressionS *ep)); |
670a50eb | 597 | static void macro PARAMS ((struct mips_cl_insn * ip)); |
cc5703cd | 598 | static void mips16_macro PARAMS ((struct mips_cl_insn * ip)); |
917fae09 SS |
599 | #ifdef LOSING_COMPILER |
600 | static void macro2 PARAMS ((struct mips_cl_insn * ip)); | |
601 | #endif | |
670a50eb | 602 | static void mips_ip PARAMS ((char *str, struct mips_cl_insn * ip)); |
cc5703cd | 603 | static void mips16_ip PARAMS ((char *str, struct mips_cl_insn * ip)); |
15e69f98 ILT |
604 | static void mips16_immed PARAMS ((char *, unsigned int, int, offsetT, boolean, |
605 | boolean, boolean, unsigned long *, | |
606 | boolean *, unsigned short *)); | |
670a50eb ILT |
607 | static int my_getSmallExpression PARAMS ((expressionS * ep, char *str)); |
608 | static void my_getExpression PARAMS ((expressionS * ep, char *str)); | |
3d3c5039 | 609 | static symbolS *get_symbol PARAMS ((void)); |
23dc1ae3 | 610 | static void mips_align PARAMS ((int to, int fill, symbolS *label)); |
3d3c5039 ILT |
611 | static void s_align PARAMS ((int)); |
612 | static void s_change_sec PARAMS ((int)); | |
613 | static void s_cons PARAMS ((int)); | |
3d3c5039 | 614 | static void s_float_cons PARAMS ((int)); |
c1444ec4 | 615 | static void s_mips_globl PARAMS ((int)); |
3d3c5039 ILT |
616 | static void s_option PARAMS ((int)); |
617 | static void s_mipsset PARAMS ((int)); | |
9226253a ILT |
618 | static void s_abicalls PARAMS ((int)); |
619 | static void s_cpload PARAMS ((int)); | |
620 | static void s_cprestore PARAMS ((int)); | |
0dd2d296 ILT |
621 | static void s_gpword PARAMS ((int)); |
622 | static void s_cpadd PARAMS ((int)); | |
ed3eb786 | 623 | static void s_insn PARAMS ((int)); |
3d3c5039 ILT |
624 | static void md_obj_begin PARAMS ((void)); |
625 | static void md_obj_end PARAMS ((void)); | |
626 | static long get_number PARAMS ((void)); | |
627 | static void s_ent PARAMS ((int)); | |
628 | static void s_mipsend PARAMS ((int)); | |
629 | static void s_file PARAMS ((int)); | |
3c83da8a | 630 | static void s_mips_stab PARAMS ((int)); |
cc5703cd | 631 | static int mips16_extended_frag PARAMS ((fragS *, asection *, long)); |
3d3c5039 ILT |
632 | \f |
633 | /* Pseudo-op table. | |
634 | ||
635 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
636 | should be defined here, but are currently unsupported: .alias, | |
637 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
638 | ||
639 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
640 | specific to the type of debugging information being generated, and | |
641 | should be defined by the object format: .aent, .begin, .bend, | |
642 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
643 | .vreg. | |
644 | ||
645 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
646 | not MIPS CPU specific, but are also not specific to the object file | |
647 | format. This file is probably the best place to define them, but | |
648 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
649 | .struct, .weakext. */ | |
650 | ||
739708fa | 651 | static const pseudo_typeS mips_pseudo_table[] = |
3d3c5039 | 652 | { |
670a50eb ILT |
653 | /* MIPS specific pseudo-ops. */ |
654 | {"option", s_option, 0}, | |
655 | {"set", s_mipsset, 0}, | |
dd3f1f76 ILT |
656 | {"rdata", s_change_sec, 'r'}, |
657 | {"sdata", s_change_sec, 's'}, | |
658 | {"livereg", s_ignore, 0}, | |
739708fa KR |
659 | {"abicalls", s_abicalls, 0}, |
660 | {"cpload", s_cpload, 0}, | |
661 | {"cprestore", s_cprestore, 0}, | |
662 | {"gpword", s_gpword, 0}, | |
663 | {"cpadd", s_cpadd, 0}, | |
ed3eb786 | 664 | {"insn", s_insn, 0}, |
3d3c5039 | 665 | |
670a50eb | 666 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
3d3c5039 | 667 | chips. */ |
739708fa | 668 | {"asciiz", stringer, 1}, |
670a50eb ILT |
669 | {"bss", s_change_sec, 'b'}, |
670 | {"err", s_err, 0}, | |
671 | {"half", s_cons, 1}, | |
52aa70b5 | 672 | {"dword", s_cons, 3}, |
3d3c5039 | 673 | |
670a50eb | 674 | /* These pseudo-ops are defined in read.c, but must be overridden |
3d3c5039 | 675 | here for one reason or another. */ |
670a50eb ILT |
676 | {"align", s_align, 0}, |
677 | {"byte", s_cons, 0}, | |
678 | {"data", s_change_sec, 'd'}, | |
becfe05e | 679 | {"double", s_float_cons, 'd'}, |
becfe05e | 680 | {"float", s_float_cons, 'f'}, |
c1444ec4 ILT |
681 | {"globl", s_mips_globl, 0}, |
682 | {"global", s_mips_globl, 0}, | |
eb8fd0e9 ILT |
683 | {"hword", s_cons, 1}, |
684 | {"int", s_cons, 2}, | |
685 | {"long", s_cons, 2}, | |
686 | {"octa", s_cons, 4}, | |
687 | {"quad", s_cons, 3}, | |
688 | {"short", s_cons, 1}, | |
689 | {"single", s_float_cons, 'f'}, | |
3c83da8a | 690 | {"stabn", s_mips_stab, 'n'}, |
670a50eb ILT |
691 | {"text", s_change_sec, 't'}, |
692 | {"word", s_cons, 2}, | |
739708fa KR |
693 | { 0 }, |
694 | }; | |
3d3c5039 | 695 | |
739708fa | 696 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = { |
670a50eb | 697 | /* These pseudo-ops should be defined by the object file format. |
0dd2d296 | 698 | However, a.out doesn't support them, so we have versions here. */ |
670a50eb | 699 | {"aent", s_ent, 1}, |
9226253a | 700 | {"bgnb", s_ignore, 0}, |
670a50eb | 701 | {"end", s_mipsend, 0}, |
9226253a | 702 | {"endb", s_ignore, 0}, |
670a50eb ILT |
703 | {"ent", s_ent, 0}, |
704 | {"file", s_file, 0}, | |
705 | {"fmask", s_ignore, 'F'}, | |
706 | {"frame", s_ignore, 0}, | |
707 | {"loc", s_ignore, 0}, | |
708 | {"mask", s_ignore, 'R'}, | |
709 | {"verstamp", s_ignore, 0}, | |
739708fa KR |
710 | { 0 }, |
711 | }; | |
61420a20 | 712 | |
739708fa KR |
713 | extern void pop_insert PARAMS ((const pseudo_typeS *)); |
714 | ||
715 | void | |
716 | mips_pop_insert () | |
717 | { | |
718 | pop_insert (mips_pseudo_table); | |
719 | if (! ECOFF_DEBUGGING) | |
720 | pop_insert (mips_nonecoff_pseudo_table); | |
739708fa | 721 | } |
3d3c5039 | 722 | \f |
fbcfacb7 ILT |
723 | /* Symbols labelling the current insn. */ |
724 | ||
725 | struct insn_label_list | |
726 | { | |
727 | struct insn_label_list *next; | |
728 | symbolS *label; | |
729 | }; | |
730 | ||
731 | static struct insn_label_list *insn_labels; | |
732 | static struct insn_label_list *free_insn_labels; | |
733 | ||
734 | static void mips_clear_insn_labels PARAMS ((void)); | |
735 | ||
736 | static inline void | |
737 | mips_clear_insn_labels () | |
738 | { | |
739 | register struct insn_label_list **pl; | |
740 | ||
741 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
742 | ; | |
743 | *pl = insn_labels; | |
744 | insn_labels = NULL; | |
745 | } | |
746 | \f | |
3d3c5039 ILT |
747 | static char *expr_end; |
748 | ||
867a58b3 ILT |
749 | /* Expressions which appear in instructions. These are set by |
750 | mips_ip. */ | |
751 | ||
3d3c5039 ILT |
752 | static expressionS imm_expr; |
753 | static expressionS offset_expr; | |
867a58b3 ILT |
754 | |
755 | /* Relocs associated with imm_expr and offset_expr. */ | |
756 | ||
3d3c5039 ILT |
757 | static bfd_reloc_code_real_type imm_reloc; |
758 | static bfd_reloc_code_real_type offset_reloc; | |
759 | ||
867a58b3 ILT |
760 | /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */ |
761 | ||
762 | static boolean imm_unmatched_hi; | |
763 | ||
8728fa92 ILT |
764 | /* These are set by mips16_ip if an explicit extension is used. */ |
765 | ||
766 | static boolean mips16_small, mips16_ext; | |
767 | ||
3d3c5039 ILT |
768 | /* |
769 | * This function is called once, at assembler startup time. It should | |
770 | * set up all the tables, etc. that the MD part of the assembler will need. | |
771 | */ | |
772 | void | |
670a50eb | 773 | md_begin () |
3d3c5039 | 774 | { |
0dd2d296 | 775 | boolean ok = false; |
604633ae | 776 | register const char *retval = NULL; |
670a50eb | 777 | register unsigned int i = 0; |
3d3c5039 | 778 | |
3c83da8a | 779 | if (mips_opts.isa == -1) |
8358c818 | 780 | { |
8c63448a ILT |
781 | const char *cpu; |
782 | char *a = NULL; | |
783 | ||
784 | cpu = TARGET_CPU; | |
785 | if (strcmp (cpu + (sizeof TARGET_CPU) - 3, "el") == 0) | |
786 | { | |
787 | a = xmalloc (sizeof TARGET_CPU); | |
788 | strcpy (a, TARGET_CPU); | |
789 | a[(sizeof TARGET_CPU) - 3] = '\0'; | |
790 | cpu = a; | |
791 | } | |
792 | ||
793 | if (strcmp (cpu, "mips") == 0) | |
794 | { | |
3c83da8a | 795 | mips_opts.isa = 1; |
4bb0cc41 ILT |
796 | if (mips_cpu == -1) |
797 | mips_cpu = 3000; | |
8c63448a | 798 | } |
5c6f5923 GRK |
799 | else if (strcmp (cpu, "r3900") == 0 |
800 | || strcmp (cpu, "mipsr3900") == 0) | |
801 | { | |
802 | mips_opts.isa = 1; | |
803 | if (mips_cpu == -1) | |
804 | mips_cpu = 3900; | |
805 | if (mips_3900 == -1) | |
806 | mips_3900 = 1; | |
807 | } | |
8c63448a ILT |
808 | else if (strcmp (cpu, "r6000") == 0 |
809 | || strcmp (cpu, "mips2") == 0) | |
810 | { | |
3c83da8a | 811 | mips_opts.isa = 2; |
4bb0cc41 ILT |
812 | if (mips_cpu == -1) |
813 | mips_cpu = 6000; | |
8c63448a ILT |
814 | } |
815 | else if (strcmp (cpu, "mips64") == 0 | |
816 | || strcmp (cpu, "r4000") == 0 | |
817 | || strcmp (cpu, "mips3") == 0) | |
818 | { | |
3c83da8a | 819 | mips_opts.isa = 3; |
4bb0cc41 ILT |
820 | if (mips_cpu == -1) |
821 | mips_cpu = 4000; | |
8c63448a ILT |
822 | } |
823 | else if (strcmp (cpu, "r4400") == 0) | |
824 | { | |
3c83da8a | 825 | mips_opts.isa = 3; |
4bb0cc41 ILT |
826 | if (mips_cpu == -1) |
827 | mips_cpu = 4400; | |
8c63448a ILT |
828 | } |
829 | else if (strcmp (cpu, "mips64orion") == 0 | |
830 | || strcmp (cpu, "r4600") == 0) | |
831 | { | |
3c83da8a | 832 | mips_opts.isa = 3; |
4bb0cc41 ILT |
833 | if (mips_cpu == -1) |
834 | mips_cpu = 4600; | |
8c63448a | 835 | } |
b2b8c24e ILT |
836 | else if (strcmp (cpu, "r4650") == 0) |
837 | { | |
3c83da8a | 838 | mips_opts.isa = 3; |
b2b8c24e ILT |
839 | if (mips_cpu == -1) |
840 | mips_cpu = 4650; | |
841 | if (mips_4650 == -1) | |
842 | mips_4650 = 1; | |
843 | } | |
c625fc23 JSC |
844 | else if (strcmp (cpu, "mips64vr4300") == 0) |
845 | { | |
3c83da8a | 846 | mips_opts.isa = 3; |
c625fc23 JSC |
847 | if (mips_cpu == -1) |
848 | mips_cpu = 4300; | |
849 | } | |
850 | else if (strcmp (cpu, "mips64vr4100") == 0) | |
851 | { | |
3c83da8a | 852 | mips_opts.isa = 3; |
c625fc23 JSC |
853 | if (mips_cpu == -1) |
854 | mips_cpu = 4100; | |
855 | if (mips_4100 == -1) | |
856 | mips_4100 = 1; | |
857 | } | |
e532b44c ILT |
858 | else if (strcmp (cpu, "r4010") == 0) |
859 | { | |
3c83da8a | 860 | mips_opts.isa = 2; |
e532b44c ILT |
861 | if (mips_cpu == -1) |
862 | mips_cpu = 4010; | |
863 | if (mips_4010 == -1) | |
864 | mips_4010 = 1; | |
865 | } | |
517078c1 ILT |
866 | else if (strcmp (cpu, "r5000") == 0 |
867 | || strcmp (cpu, "mips64vr5000") == 0) | |
868 | { | |
3c83da8a | 869 | mips_opts.isa = 4; |
517078c1 ILT |
870 | if (mips_cpu == -1) |
871 | mips_cpu = 5000; | |
872 | } | |
276c2d7d GRK |
873 | /* start-sanitize-r5900 */ |
874 | else if (strcmp (cpu, "r5900") == 0 | |
875 | || strcmp (cpu, "mips64vr5900") == 0 | |
876 | || strcmp (cpu, "mips64vr5900el") == 0) | |
877 | { | |
3c83da8a | 878 | mips_opts.isa = 3; |
276c2d7d GRK |
879 | if (mips_cpu == -1) |
880 | mips_cpu = 5900; | |
16262668 | 881 | if (mips_5900 == -1) |
276c2d7d GRK |
882 | mips_5900 = 1; |
883 | } | |
884 | /* end-sanitize-r5900 */ | |
d8a1c247 KR |
885 | else if (strcmp (cpu, "r8000") == 0 |
886 | || strcmp (cpu, "mips4") == 0) | |
887 | { | |
3c83da8a | 888 | mips_opts.isa = 4; |
d8a1c247 KR |
889 | if (mips_cpu == -1) |
890 | mips_cpu = 8000; | |
891 | } | |
892 | else if (strcmp (cpu, "r10000") == 0) | |
893 | { | |
3c83da8a | 894 | mips_opts.isa = 4; |
d8a1c247 KR |
895 | if (mips_cpu == -1) |
896 | mips_cpu = 10000; | |
897 | } | |
cc5703cd ILT |
898 | else if (strcmp (cpu, "mips16") == 0) |
899 | { | |
3c83da8a | 900 | mips_opts.isa = 3; |
cc5703cd ILT |
901 | if (mips_cpu == -1) |
902 | mips_cpu = 0; /* FIXME */ | |
903 | } | |
8358c818 | 904 | else |
8c63448a | 905 | { |
3c83da8a | 906 | mips_opts.isa = 1; |
4bb0cc41 ILT |
907 | if (mips_cpu == -1) |
908 | mips_cpu = 3000; | |
8c63448a ILT |
909 | } |
910 | ||
911 | if (a != NULL) | |
912 | free (a); | |
8358c818 ILT |
913 | } |
914 | ||
3c83da8a | 915 | if (mips_opts.mips16 < 0) |
cc5703cd ILT |
916 | { |
917 | if (strncmp (TARGET_CPU, "mips16", sizeof "mips16" - 1) == 0) | |
3c83da8a | 918 | mips_opts.mips16 = 1; |
cc5703cd | 919 | else |
3c83da8a | 920 | mips_opts.mips16 = 0; |
cc5703cd ILT |
921 | } |
922 | ||
b2b8c24e ILT |
923 | if (mips_4650 < 0) |
924 | mips_4650 = 0; | |
925 | ||
e532b44c ILT |
926 | if (mips_4010 < 0) |
927 | mips_4010 = 0; | |
928 | ||
c625fc23 JSC |
929 | if (mips_4100 < 0) |
930 | mips_4100 = 0; | |
931 | ||
276c2d7d GRK |
932 | /* start-sanitize-r5900 */ |
933 | if (mips_5900 < 0) | |
934 | mips_5900 = 0; | |
935 | /* end-sanitize-r5900 */ | |
936 | ||
5c6f5923 GRK |
937 | if (mips_3900 < 0) |
938 | mips_3900 = 0; | |
939 | ||
940 | if (mips_4010 | |
941 | || mips_cpu == 4300 | |
942 | || mips_3900 | |
943 | ) | |
944 | hilo_interlocks = 1; | |
e532b44c | 945 | else |
5c6f5923 GRK |
946 | hilo_interlocks = 0; |
947 | ||
948 | if (mips_opts.isa >= 2 | |
949 | || mips_3900 | |
950 | ) | |
951 | gpr_interlocks = 1; | |
952 | else | |
953 | gpr_interlocks = 0; | |
e532b44c | 954 | |
efec4a28 | 955 | /* Itbl support may require additional care here. */ |
ca296aab | 956 | if (mips_cpu == 4300) |
344a8d61 JSC |
957 | cop_interlocks = 1; |
958 | else | |
959 | cop_interlocks = 0; | |
960 | ||
3c83da8a | 961 | if (mips_opts.isa < 2 && mips_trap) |
8ea7f4e8 ILT |
962 | as_bad ("trap exception not supported at ISA 1"); |
963 | ||
3c83da8a | 964 | switch (mips_opts.isa) |
97f99d11 ILT |
965 | { |
966 | case 1: | |
967 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 3000); | |
968 | break; | |
969 | case 2: | |
970 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 6000); | |
971 | break; | |
972 | case 3: | |
973 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 4000); | |
974 | break; | |
d8a1c247 KR |
975 | case 4: |
976 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 8000); | |
977 | break; | |
97f99d11 ILT |
978 | } |
979 | if (! ok) | |
980 | as_warn ("Could not set architecture and machine"); | |
981 | ||
3c83da8a | 982 | file_mips_isa = mips_opts.isa; |
1051c97f | 983 | |
13fe1379 ILT |
984 | op_hash = hash_new (); |
985 | ||
670a50eb ILT |
986 | for (i = 0; i < NUMOPCODES;) |
987 | { | |
988 | const char *name = mips_opcodes[i].name; | |
989 | ||
604633ae | 990 | retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]); |
abdad6bc | 991 | if (retval != NULL) |
670a50eb ILT |
992 | { |
993 | fprintf (stderr, "internal error: can't hash `%s': %s\n", | |
994 | mips_opcodes[i].name, retval); | |
995 | as_fatal ("Broken assembler. No assembly attempted."); | |
996 | } | |
997 | do | |
998 | { | |
8358c818 ILT |
999 | if (mips_opcodes[i].pinfo != INSN_MACRO |
1000 | && ((mips_opcodes[i].match & mips_opcodes[i].mask) | |
1001 | != mips_opcodes[i].match)) | |
670a50eb ILT |
1002 | { |
1003 | fprintf (stderr, "internal error: bad opcode: `%s' \"%s\"\n", | |
1004 | mips_opcodes[i].name, mips_opcodes[i].args); | |
1005 | as_fatal ("Broken assembler. No assembly attempted."); | |
3d3c5039 | 1006 | } |
670a50eb ILT |
1007 | ++i; |
1008 | } | |
1009 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
3d3c5039 ILT |
1010 | } |
1011 | ||
cc5703cd ILT |
1012 | mips16_op_hash = hash_new (); |
1013 | ||
1014 | i = 0; | |
1015 | while (i < bfd_mips16_num_opcodes) | |
1016 | { | |
1017 | const char *name = mips16_opcodes[i].name; | |
1018 | ||
1019 | retval = hash_insert (mips16_op_hash, name, (PTR) &mips16_opcodes[i]); | |
1020 | if (retval != NULL) | |
1021 | as_fatal ("internal error: can't hash `%s': %s\n", | |
1022 | mips16_opcodes[i].name, retval); | |
1023 | do | |
1024 | { | |
1025 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1026 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1027 | != mips16_opcodes[i].match)) | |
1028 | as_fatal ("internal error: bad opcode: `%s' \"%s\"\n", | |
1029 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1030 | ++i; | |
1031 | } | |
1032 | while (i < bfd_mips16_num_opcodes | |
1033 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1034 | } | |
1035 | ||
ebf28372 ILT |
1036 | /* We add all the general register names to the symbol table. This |
1037 | helps us detect invalid uses of them. */ | |
1038 | for (i = 0; i < 32; i++) | |
1039 | { | |
1040 | char buf[5]; | |
1041 | ||
1042 | sprintf (buf, "$%d", i); | |
1043 | symbol_table_insert (symbol_new (buf, reg_section, i, | |
1044 | &zero_address_frag)); | |
1045 | } | |
1046 | symbol_table_insert (symbol_new ("$fp", reg_section, FP, | |
1047 | &zero_address_frag)); | |
1048 | symbol_table_insert (symbol_new ("$sp", reg_section, SP, | |
1049 | &zero_address_frag)); | |
1050 | symbol_table_insert (symbol_new ("$gp", reg_section, GP, | |
1051 | &zero_address_frag)); | |
1052 | symbol_table_insert (symbol_new ("$at", reg_section, AT, | |
1053 | &zero_address_frag)); | |
1054 | symbol_table_insert (symbol_new ("$kt0", reg_section, KT0, | |
1055 | &zero_address_frag)); | |
1056 | symbol_table_insert (symbol_new ("$kt1", reg_section, KT1, | |
1057 | &zero_address_frag)); | |
1058 | symbol_table_insert (symbol_new ("$pc", reg_section, -1, | |
1059 | &zero_address_frag)); | |
1060 | ||
4a1cb507 | 1061 | mips_no_prev_insn (false); |
becfe05e | 1062 | |
1aa6938e ILT |
1063 | mips_gprmask = 0; |
1064 | mips_cprmask[0] = 0; | |
1065 | mips_cprmask[1] = 0; | |
1066 | mips_cprmask[2] = 0; | |
1067 | mips_cprmask[3] = 0; | |
1068 | ||
8358c818 | 1069 | /* set the default alignment for the text section (2**2) */ |
f5e38044 | 1070 | record_alignment (text_section, 2); |
8358c818 | 1071 | |
1dc1e798 KR |
1072 | if (USE_GLOBAL_POINTER_OPT) |
1073 | bfd_set_gp_size (stdoutput, g_switch_value); | |
abdad6bc | 1074 | |
1dc1e798 KR |
1075 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
1076 | { | |
08e17202 ILT |
1077 | /* On a native system, sections must be aligned to 16 byte |
1078 | boundaries. When configured for an embedded ELF target, we | |
1079 | don't bother. */ | |
1080 | if (strcmp (TARGET_OS, "elf") != 0) | |
1081 | { | |
1082 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
1083 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
1084 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
1085 | } | |
1dc1e798 KR |
1086 | |
1087 | /* Create a .reginfo section for register masks and a .mdebug | |
1088 | section for debugging information. */ | |
1089 | { | |
1090 | segT seg; | |
1091 | subsegT subseg; | |
b3a64736 | 1092 | flagword flags; |
1dc1e798 KR |
1093 | segT sec; |
1094 | ||
1095 | seg = now_seg; | |
1096 | subseg = now_subseg; | |
1dc1e798 | 1097 | |
b3a64736 ILT |
1098 | /* The ABI says this section should be loaded so that the |
1099 | running program can access it. However, we don't load it | |
1100 | if we are configured for an embedded target */ | |
1101 | flags = SEC_READONLY | SEC_DATA; | |
1102 | if (strcmp (TARGET_OS, "elf") != 0) | |
1103 | flags |= SEC_ALLOC | SEC_LOAD; | |
1104 | ||
87178180 ILT |
1105 | if (! mips_64) |
1106 | { | |
1107 | sec = subseg_new (".reginfo", (subsegT) 0); | |
8358c818 | 1108 | |
b3a64736 ILT |
1109 | |
1110 | (void) bfd_set_section_flags (stdoutput, sec, flags); | |
87178180 ILT |
1111 | (void) bfd_set_section_alignment (stdoutput, sec, 2); |
1112 | ||
f2a663d3 | 1113 | #ifdef OBJ_ELF |
87178180 | 1114 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
1dc1e798 | 1115 | #endif |
87178180 ILT |
1116 | } |
1117 | else | |
1118 | { | |
1119 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
1120 | .reginfo section. */ | |
1121 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
b3a64736 | 1122 | (void) bfd_set_section_flags (stdoutput, sec, flags); |
87178180 ILT |
1123 | (void) bfd_set_section_alignment (stdoutput, sec, 3); |
1124 | ||
1125 | #ifdef OBJ_ELF | |
1126 | /* Set up the option header. */ | |
1127 | { | |
1128 | Elf_Internal_Options opthdr; | |
1129 | char *f; | |
1130 | ||
1131 | opthdr.kind = ODK_REGINFO; | |
1132 | opthdr.size = (sizeof (Elf_External_Options) | |
1133 | + sizeof (Elf64_External_RegInfo)); | |
1134 | opthdr.section = 0; | |
1135 | opthdr.info = 0; | |
1136 | f = frag_more (sizeof (Elf_External_Options)); | |
1137 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
1138 | (Elf_External_Options *) f); | |
1139 | ||
1140 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
1141 | } | |
1142 | #endif | |
1143 | } | |
f2a663d3 | 1144 | |
739708fa KR |
1145 | if (ECOFF_DEBUGGING) |
1146 | { | |
1147 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1148 | (void) bfd_set_section_flags (stdoutput, sec, | |
1149 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1150 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1151 | } | |
0dd2d296 | 1152 | |
1dc1e798 KR |
1153 | subseg_set (seg, subseg); |
1154 | } | |
1155 | } | |
f2a663d3 | 1156 | |
739708fa KR |
1157 | if (! ECOFF_DEBUGGING) |
1158 | md_obj_begin (); | |
3d3c5039 ILT |
1159 | } |
1160 | ||
1161 | void | |
13fe1379 | 1162 | md_mips_end () |
3d3c5039 | 1163 | { |
739708fa KR |
1164 | if (! ECOFF_DEBUGGING) |
1165 | md_obj_end (); | |
3d3c5039 ILT |
1166 | } |
1167 | ||
1168 | void | |
670a50eb ILT |
1169 | md_assemble (str) |
1170 | char *str; | |
3d3c5039 | 1171 | { |
670a50eb | 1172 | struct mips_cl_insn insn; |
3d3c5039 | 1173 | |
5ac34ac3 | 1174 | imm_expr.X_op = O_absent; |
867a58b3 ILT |
1175 | imm_reloc = BFD_RELOC_UNUSED; |
1176 | imm_unmatched_hi = false; | |
5ac34ac3 | 1177 | offset_expr.X_op = O_absent; |
867a58b3 | 1178 | offset_reloc = BFD_RELOC_UNUSED; |
3d3c5039 | 1179 | |
3c83da8a | 1180 | if (mips_opts.mips16) |
cc5703cd ILT |
1181 | mips16_ip (str, &insn); |
1182 | else | |
efec4a28 | 1183 | { |
9218cee0 | 1184 | mips_ip (str, &insn); |
efec4a28 DP |
1185 | DBG(("returned from mips_ip(%s) insn_opcode = 0x%x\n", |
1186 | str, insn.insn_opcode)); | |
1187 | } | |
cc5703cd | 1188 | |
670a50eb ILT |
1189 | if (insn_error) |
1190 | { | |
1191 | as_bad ("%s `%s'", insn_error, str); | |
1192 | return; | |
1193 | } | |
cc5703cd | 1194 | |
670a50eb ILT |
1195 | if (insn.insn_mo->pinfo == INSN_MACRO) |
1196 | { | |
3c83da8a | 1197 | if (mips_opts.mips16) |
cc5703cd ILT |
1198 | mips16_macro (&insn); |
1199 | else | |
1200 | macro (&insn); | |
3d3c5039 | 1201 | } |
670a50eb ILT |
1202 | else |
1203 | { | |
5ac34ac3 | 1204 | if (imm_expr.X_op != O_absent) |
867a58b3 ILT |
1205 | append_insn ((char *) NULL, &insn, &imm_expr, imm_reloc, |
1206 | imm_unmatched_hi); | |
5ac34ac3 | 1207 | else if (offset_expr.X_op != O_absent) |
867a58b3 | 1208 | append_insn ((char *) NULL, &insn, &offset_expr, offset_reloc, false); |
670a50eb | 1209 | else |
867a58b3 | 1210 | append_insn ((char *) NULL, &insn, NULL, BFD_RELOC_UNUSED, false); |
3d3c5039 ILT |
1211 | } |
1212 | } | |
1213 | ||
cc5703cd ILT |
1214 | /* See whether instruction IP reads register REG. CLASS is the type |
1215 | of register. */ | |
becfe05e ILT |
1216 | |
1217 | static int | |
cc5703cd | 1218 | insn_uses_reg (ip, reg, class) |
becfe05e | 1219 | struct mips_cl_insn *ip; |
604633ae | 1220 | unsigned int reg; |
cc5703cd | 1221 | enum mips_regclass class; |
becfe05e | 1222 | { |
cc5703cd ILT |
1223 | if (class == MIPS16_REG) |
1224 | { | |
3c83da8a | 1225 | assert (mips_opts.mips16); |
cc5703cd ILT |
1226 | reg = mips16_to_32_reg_map[reg]; |
1227 | class = MIPS_GR_REG; | |
1228 | } | |
1229 | ||
becfe05e | 1230 | /* Don't report on general register 0, since it never changes. */ |
cc5703cd | 1231 | if (class == MIPS_GR_REG && reg == 0) |
becfe05e ILT |
1232 | return 0; |
1233 | ||
cc5703cd | 1234 | if (class == MIPS_FP_REG) |
becfe05e | 1235 | { |
3c83da8a | 1236 | assert (! mips_opts.mips16); |
becfe05e ILT |
1237 | /* If we are called with either $f0 or $f1, we must check $f0. |
1238 | This is not optimal, because it will introduce an unnecessary | |
1239 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
1240 | need to distinguish reading both $f0 and $f1 or just one of | |
1241 | them. Note that we don't have to check the other way, | |
1242 | because there is no instruction that sets both $f0 and $f1 | |
1243 | and requires a delay. */ | |
1244 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
68952421 | 1245 | && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1) |
604633ae | 1246 | == (reg &~ (unsigned) 1))) |
becfe05e ILT |
1247 | return 1; |
1248 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
68952421 | 1249 | && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1) |
604633ae | 1250 | == (reg &~ (unsigned) 1))) |
becfe05e ILT |
1251 | return 1; |
1252 | } | |
3c83da8a | 1253 | else if (! mips_opts.mips16) |
becfe05e ILT |
1254 | { |
1255 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
1256 | && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg) | |
1257 | return 1; | |
1258 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
1259 | && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg) | |
1260 | return 1; | |
1261 | } | |
cc5703cd ILT |
1262 | else |
1263 | { | |
1264 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
23ac3ca1 ILT |
1265 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX) |
1266 | & MIPS16OP_MASK_RX)] | |
1267 | == reg)) | |
cc5703cd ILT |
1268 | return 1; |
1269 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
23ac3ca1 ILT |
1270 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY) |
1271 | & MIPS16OP_MASK_RY)] | |
1272 | == reg)) | |
cc5703cd ILT |
1273 | return 1; |
1274 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
23ac3ca1 ILT |
1275 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) |
1276 | & MIPS16OP_MASK_MOVE32Z)] | |
1277 | == reg)) | |
cc5703cd ILT |
1278 | return 1; |
1279 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
1280 | return 1; | |
1281 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
1282 | return 1; | |
1283 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
1284 | return 1; | |
1285 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
1286 | && ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1287 | & MIPS16OP_MASK_REGR32) == reg) | |
1288 | return 1; | |
1289 | } | |
becfe05e ILT |
1290 | |
1291 | return 0; | |
1292 | } | |
1293 | ||
fb251650 ILT |
1294 | /* This function returns true if modifying a register requires a |
1295 | delay. */ | |
1296 | ||
1297 | static int | |
1298 | reg_needs_delay (reg) | |
1299 | int reg; | |
1300 | { | |
1301 | unsigned long prev_pinfo; | |
1302 | ||
1303 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
3c83da8a JW |
1304 | if (! mips_opts.noreorder |
1305 | && mips_opts.isa < 4 | |
fb251650 | 1306 | && ((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
5c6f5923 | 1307 | || (! gpr_interlocks |
fb251650 ILT |
1308 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) |
1309 | { | |
1310 | /* A load from a coprocessor or from memory. All load | |
1311 | delays delay the use of general register rt for one | |
1312 | instruction on the r3000. The r6000 and r4000 use | |
1313 | interlocks. */ | |
efec4a28 | 1314 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
1315 | know (prev_pinfo & INSN_WRITE_GPR_T); |
1316 | if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)) | |
1317 | return 1; | |
1318 | } | |
1319 | ||
1320 | return 0; | |
1321 | } | |
1322 | ||
3c83da8a JW |
1323 | /* Mark instruction labels in mips16 mode. This permits the linker to |
1324 | handle them specially, such as generating jalx instructions when | |
1325 | needed. We also make them odd for the duration of the assembly, in | |
1326 | order to generate the right sort of code. We will make them even | |
1327 | in the adjust_symtab routine, while leaving them marked. This is | |
1328 | convenient for the debugger and the disassembler. The linker knows | |
1329 | to make them odd again. */ | |
1330 | ||
1331 | static void | |
1332 | mips16_mark_labels () | |
1333 | { | |
1334 | if (mips_opts.mips16) | |
1335 | { | |
1336 | struct insn_label_list *l; | |
1337 | ||
1338 | for (l = insn_labels; l != NULL; l = l->next) | |
1339 | { | |
68952421 | 1340 | #ifdef OBJ_ELF |
3c83da8a JW |
1341 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
1342 | S_SET_OTHER (l->label, STO_MIPS16); | |
1343 | #endif | |
1344 | if ((l->label->sy_value.X_add_number & 1) == 0) | |
1345 | ++l->label->sy_value.X_add_number; | |
1346 | } | |
1347 | } | |
1348 | } | |
1349 | ||
0dd2d296 ILT |
1350 | /* Output an instruction. PLACE is where to put the instruction; if |
1351 | it is NULL, this uses frag_more to get room. IP is the instruction | |
1352 | information. ADDRESS_EXPR is an operand of the instruction to be | |
1353 | used with RELOC_TYPE. */ | |
3d3c5039 | 1354 | |
3d3c5039 | 1355 | static void |
867a58b3 | 1356 | append_insn (place, ip, address_expr, reloc_type, unmatched_hi) |
0dd2d296 | 1357 | char *place; |
670a50eb ILT |
1358 | struct mips_cl_insn *ip; |
1359 | expressionS *address_expr; | |
1360 | bfd_reloc_code_real_type reloc_type; | |
867a58b3 | 1361 | boolean unmatched_hi; |
3d3c5039 | 1362 | { |
1aa6938e | 1363 | register unsigned long prev_pinfo, pinfo; |
670a50eb | 1364 | char *f; |
becfe05e ILT |
1365 | fixS *fixp; |
1366 | int nops = 0; | |
3d3c5039 | 1367 | |
3c83da8a JW |
1368 | /* Mark instruction labels in mips16 mode. */ |
1369 | if (mips_opts.mips16) | |
1370 | mips16_mark_labels (); | |
fbcfacb7 | 1371 | |
1aa6938e ILT |
1372 | prev_pinfo = prev_insn.insn_mo->pinfo; |
1373 | pinfo = ip->insn_mo->pinfo; | |
1374 | ||
3c83da8a | 1375 | if (place == NULL && (! mips_opts.noreorder || prev_nop_frag != NULL)) |
becfe05e | 1376 | { |
4a1cb507 ILT |
1377 | int prev_prev_nop; |
1378 | ||
becfe05e | 1379 | /* If the previous insn required any delay slots, see if we need |
8358c818 | 1380 | to insert a NOP or two. There are eight kinds of possible |
becfe05e | 1381 | hazards, of which an instruction can have at most one type. |
8358c818 ILT |
1382 | (1) a load from memory delay |
1383 | (2) a load from a coprocessor delay | |
1384 | (3) an unconditional branch delay | |
1385 | (4) a conditional branch delay | |
1386 | (5) a move to coprocessor register delay | |
1387 | (6) a load coprocessor register from memory delay | |
1388 | (7) a coprocessor condition code delay | |
1389 | (8) a HI/LO special register delay | |
becfe05e ILT |
1390 | |
1391 | There are a lot of optimizations we could do that we don't. | |
1392 | In particular, we do not, in general, reorder instructions. | |
1393 | If you use gcc with optimization, it will reorder | |
1394 | instructions and generally do much more optimization then we | |
1395 | do here; repeating all that work in the assembler would only | |
1396 | benefit hand written assembly code, and does not seem worth | |
1397 | it. */ | |
1398 | ||
1399 | /* This is how a NOP is emitted. */ | |
cc5703cd | 1400 | #define emit_nop() \ |
3c83da8a | 1401 | (mips_opts.mips16 \ |
cc5703cd ILT |
1402 | ? md_number_to_chars (frag_more (2), 0x6500, 2) \ |
1403 | : md_number_to_chars (frag_more (4), 0, 4)) | |
becfe05e ILT |
1404 | |
1405 | /* The previous insn might require a delay slot, depending upon | |
1406 | the contents of the current insn. */ | |
3c83da8a JW |
1407 | if (! mips_opts.mips16 |
1408 | && mips_opts.isa < 4 | |
5af96dce ILT |
1409 | && (((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
1410 | && ! cop_interlocks) | |
5c6f5923 | 1411 | || (! gpr_interlocks |
d8a1c247 | 1412 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) |
8358c818 ILT |
1413 | { |
1414 | /* A load from a coprocessor or from memory. All load | |
1415 | delays delay the use of general register rt for one | |
1416 | instruction on the r3000. The r6000 and r4000 use | |
1417 | interlocks. */ | |
efec4a28 | 1418 | /* Itbl support may require additional care here. */ |
1aa6938e | 1419 | know (prev_pinfo & INSN_WRITE_GPR_T); |
0aa07269 ILT |
1420 | if (mips_optimize == 0 |
1421 | || insn_uses_reg (ip, | |
1422 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1423 | & OP_MASK_RT), | |
cc5703cd | 1424 | MIPS_GR_REG)) |
becfe05e ILT |
1425 | ++nops; |
1426 | } | |
3c83da8a JW |
1427 | else if (! mips_opts.mips16 |
1428 | && mips_opts.isa < 4 | |
5af96dce ILT |
1429 | && (((prev_pinfo & INSN_COPROC_MOVE_DELAY) |
1430 | && ! cop_interlocks) | |
3c83da8a | 1431 | || (mips_opts.isa < 2 |
d8a1c247 | 1432 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)))) |
becfe05e ILT |
1433 | { |
1434 | /* A generic coprocessor delay. The previous instruction | |
1435 | modified a coprocessor general or control register. If | |
1436 | it modified a control register, we need to avoid any | |
1437 | coprocessor instruction (this is probably not always | |
1438 | required, but it sometimes is). If it modified a general | |
1439 | register, we avoid using that register. | |
1440 | ||
8358c818 ILT |
1441 | On the r6000 and r4000 loading a coprocessor register |
1442 | from memory is interlocked, and does not require a delay. | |
1443 | ||
becfe05e ILT |
1444 | This case is not handled very well. There is no special |
1445 | knowledge of CP0 handling, and the coprocessors other | |
1446 | than the floating point unit are not distinguished at | |
1447 | all. */ | |
efec4a28 DP |
1448 | /* Itbl support may require additional care here. FIXME! |
1449 | Need to modify this to include knowledge about | |
1450 | user specified delays! */ | |
1aa6938e | 1451 | if (prev_pinfo & INSN_WRITE_FPR_T) |
becfe05e | 1452 | { |
0aa07269 ILT |
1453 | if (mips_optimize == 0 |
1454 | || insn_uses_reg (ip, | |
8358c818 ILT |
1455 | ((prev_insn.insn_opcode >> OP_SH_FT) |
1456 | & OP_MASK_FT), | |
cc5703cd | 1457 | MIPS_FP_REG)) |
becfe05e ILT |
1458 | ++nops; |
1459 | } | |
1aa6938e | 1460 | else if (prev_pinfo & INSN_WRITE_FPR_S) |
becfe05e | 1461 | { |
0aa07269 ILT |
1462 | if (mips_optimize == 0 |
1463 | || insn_uses_reg (ip, | |
8358c818 ILT |
1464 | ((prev_insn.insn_opcode >> OP_SH_FS) |
1465 | & OP_MASK_FS), | |
cc5703cd | 1466 | MIPS_FP_REG)) |
becfe05e ILT |
1467 | ++nops; |
1468 | } | |
1469 | else | |
1470 | { | |
1471 | /* We don't know exactly what the previous instruction | |
1472 | does. If the current instruction uses a coprocessor | |
1473 | register, we must insert a NOP. If previous | |
1474 | instruction may set the condition codes, and the | |
1475 | current instruction uses them, we must insert two | |
1476 | NOPS. */ | |
efec4a28 | 1477 | /* Itbl support may require additional care here. */ |
0aa07269 | 1478 | if (mips_optimize == 0 |
1aa6938e ILT |
1479 | || ((prev_pinfo & INSN_WRITE_COND_CODE) |
1480 | && (pinfo & INSN_READ_COND_CODE))) | |
becfe05e | 1481 | nops += 2; |
1aa6938e | 1482 | else if (pinfo & INSN_COP) |
becfe05e ILT |
1483 | ++nops; |
1484 | } | |
1485 | } | |
3c83da8a JW |
1486 | else if (! mips_opts.mips16 |
1487 | && mips_opts.isa < 4 | |
344a8d61 JSC |
1488 | && (prev_pinfo & INSN_WRITE_COND_CODE) |
1489 | && ! cop_interlocks) | |
becfe05e ILT |
1490 | { |
1491 | /* The previous instruction sets the coprocessor condition | |
1492 | codes, but does not require a general coprocessor delay | |
1493 | (this means it is a floating point comparison | |
1494 | instruction). If this instruction uses the condition | |
1495 | codes, we need to insert a single NOP. */ | |
efec4a28 | 1496 | /* Itbl support may require additional care here. */ |
0aa07269 | 1497 | if (mips_optimize == 0 |
1aa6938e | 1498 | || (pinfo & INSN_READ_COND_CODE)) |
becfe05e ILT |
1499 | ++nops; |
1500 | } | |
1aa6938e | 1501 | else if (prev_pinfo & INSN_READ_LO) |
becfe05e ILT |
1502 | { |
1503 | /* The previous instruction reads the LO register; if the | |
1504 | current instruction writes to the LO register, we must | |
517078c1 | 1505 | insert two NOPS. Some newer processors have interlocks. */ |
5c6f5923 | 1506 | if (! hilo_interlocks |
b2b8c24e ILT |
1507 | && (mips_optimize == 0 |
1508 | || (pinfo & INSN_WRITE_LO))) | |
becfe05e ILT |
1509 | nops += 2; |
1510 | } | |
1511 | else if (prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1512 | { | |
1513 | /* The previous instruction reads the HI register; if the | |
1514 | current instruction writes to the HI register, we must | |
517078c1 | 1515 | insert a NOP. Some newer processors have interlocks. */ |
5c6f5923 | 1516 | if (! hilo_interlocks |
b2b8c24e ILT |
1517 | && (mips_optimize == 0 |
1518 | || (pinfo & INSN_WRITE_HI))) | |
becfe05e ILT |
1519 | nops += 2; |
1520 | } | |
1521 | ||
4a1cb507 ILT |
1522 | /* If the previous instruction was in a noreorder section, then |
1523 | we don't want to insert the nop after all. */ | |
efec4a28 | 1524 | /* Itbl support may require additional care here. */ |
4a1cb507 ILT |
1525 | if (prev_insn_unreordered) |
1526 | nops = 0; | |
1527 | ||
becfe05e ILT |
1528 | /* There are two cases which require two intervening |
1529 | instructions: 1) setting the condition codes using a move to | |
1530 | coprocessor instruction which requires a general coprocessor | |
1531 | delay and then reading the condition codes 2) reading the HI | |
517078c1 ILT |
1532 | or LO register and then writing to it (except on processors |
1533 | which have interlocks). If we are not already emitting a NOP | |
1534 | instruction, we must check for these cases compared to the | |
1535 | instruction previous to the previous instruction. */ | |
3c83da8a JW |
1536 | if ((! mips_opts.mips16 |
1537 | && mips_opts.isa < 4 | |
4a1cb507 ILT |
1538 | && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) |
1539 | && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) | |
1540 | && (pinfo & INSN_READ_COND_CODE) | |
1541 | && ! cop_interlocks) | |
1542 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO) | |
1543 | && (pinfo & INSN_WRITE_LO) | |
5c6f5923 | 1544 | && ! hilo_interlocks) |
4a1cb507 ILT |
1545 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
1546 | && (pinfo & INSN_WRITE_HI) | |
5c6f5923 | 1547 | && ! hilo_interlocks)) |
4a1cb507 ILT |
1548 | prev_prev_nop = 1; |
1549 | else | |
1550 | prev_prev_nop = 0; | |
1551 | ||
1552 | if (prev_prev_insn_unreordered) | |
1553 | prev_prev_nop = 0; | |
1554 | ||
1555 | if (prev_prev_nop && nops == 0) | |
becfe05e ILT |
1556 | ++nops; |
1557 | ||
0dd2d296 ILT |
1558 | /* If we are being given a nop instruction, don't bother with |
1559 | one of the nops we would otherwise output. This will only | |
1560 | happen when a nop instruction is used with mips_optimize set | |
1561 | to 0. */ | |
4a1cb507 | 1562 | if (nops > 0 |
3c83da8a JW |
1563 | && ! mips_opts.noreorder |
1564 | && ip->insn_opcode == (mips_opts.mips16 ? 0x6500 : 0)) | |
0dd2d296 ILT |
1565 | --nops; |
1566 | ||
becfe05e | 1567 | /* Now emit the right number of NOP instructions. */ |
3c83da8a | 1568 | if (nops > 0 && ! mips_opts.noreorder) |
becfe05e | 1569 | { |
5af96dce ILT |
1570 | fragS *old_frag; |
1571 | unsigned long old_frag_offset; | |
8c63448a | 1572 | int i; |
fbcfacb7 | 1573 | struct insn_label_list *l; |
8c63448a | 1574 | |
5af96dce ILT |
1575 | old_frag = frag_now; |
1576 | old_frag_offset = frag_now_fix (); | |
1577 | ||
8c63448a | 1578 | for (i = 0; i < nops; i++) |
becfe05e | 1579 | emit_nop (); |
5af96dce | 1580 | |
af255ca0 | 1581 | if (listing) |
546f5536 ILT |
1582 | { |
1583 | listing_prev_line (); | |
1584 | /* We may be at the start of a variant frag. In case we | |
1585 | are, make sure there is enough space for the frag | |
1586 | after the frags created by listing_prev_line. The | |
1587 | argument to frag_grow here must be at least as large | |
1588 | as the argument to all other calls to frag_grow in | |
1589 | this file. We don't have to worry about being in the | |
1590 | middle of a variant frag, because the variants insert | |
1591 | all needed nop instructions themselves. */ | |
1592 | frag_grow (40); | |
1593 | } | |
5af96dce | 1594 | |
fbcfacb7 | 1595 | for (l = insn_labels; l != NULL; l = l->next) |
becfe05e | 1596 | { |
fbcfacb7 ILT |
1597 | assert (S_GET_SEGMENT (l->label) == now_seg); |
1598 | l->label->sy_frag = frag_now; | |
1599 | S_SET_VALUE (l->label, (valueT) frag_now_fix ()); | |
1600 | /* mips16 text labels are stored as odd. */ | |
3c83da8a | 1601 | if (mips_opts.mips16) |
fbcfacb7 | 1602 | ++l->label->sy_value.X_add_number; |
becfe05e | 1603 | } |
5af96dce ILT |
1604 | |
1605 | #ifndef NO_ECOFF_DEBUGGING | |
1606 | if (ECOFF_DEBUGGING) | |
1607 | ecoff_fix_loc (old_frag, old_frag_offset); | |
1608 | #endif | |
becfe05e | 1609 | } |
4a1cb507 ILT |
1610 | else if (prev_nop_frag != NULL) |
1611 | { | |
1612 | /* We have a frag holding nops we may be able to remove. If | |
1613 | we don't need any nops, we can decrease the size of | |
1614 | prev_nop_frag by the size of one instruction. If we do | |
1615 | need some nops, we count them in prev_nops_required. */ | |
1616 | if (prev_nop_frag_since == 0) | |
1617 | { | |
1618 | if (nops == 0) | |
1619 | { | |
3c83da8a | 1620 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; |
4a1cb507 ILT |
1621 | --prev_nop_frag_holds; |
1622 | } | |
1623 | else | |
1624 | prev_nop_frag_required += nops; | |
1625 | } | |
1626 | else | |
1627 | { | |
1628 | if (prev_prev_nop == 0) | |
1629 | { | |
3c83da8a | 1630 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; |
4a1cb507 ILT |
1631 | --prev_nop_frag_holds; |
1632 | } | |
1633 | else | |
1634 | ++prev_nop_frag_required; | |
1635 | } | |
1636 | ||
1637 | if (prev_nop_frag_holds <= prev_nop_frag_required) | |
1638 | prev_nop_frag = NULL; | |
1639 | ||
1640 | ++prev_nop_frag_since; | |
1641 | ||
1642 | /* Sanity check: by the time we reach the second instruction | |
1643 | after prev_nop_frag, we should have used up all the nops | |
1644 | one way or another. */ | |
1645 | assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL); | |
1646 | } | |
becfe05e | 1647 | } |
4a1cb507 | 1648 | |
cc5703cd ILT |
1649 | if (reloc_type > BFD_RELOC_UNUSED) |
1650 | { | |
1651 | /* We need to set up a variant frag. */ | |
3c83da8a | 1652 | assert (mips_opts.mips16 && address_expr != NULL); |
cc5703cd | 1653 | f = frag_var (rs_machine_dependent, 4, 0, |
8728fa92 | 1654 | RELAX_MIPS16_ENCODE (reloc_type - BFD_RELOC_UNUSED, |
a677feeb ILT |
1655 | mips16_small, mips16_ext, |
1656 | (prev_pinfo | |
1657 | & INSN_UNCOND_BRANCH_DELAY), | |
1658 | (prev_insn_reloc_type | |
1659 | == BFD_RELOC_MIPS16_JMP)), | |
f59fb6ca | 1660 | make_expr_symbol (address_expr), (offsetT) 0, |
cc5703cd ILT |
1661 | (char *) NULL); |
1662 | } | |
1663 | else if (place != NULL) | |
0dd2d296 | 1664 | f = place; |
3c83da8a JW |
1665 | else if (mips_opts.mips16 |
1666 | && ! ip->use_extend | |
1667 | && reloc_type != BFD_RELOC_MIPS16_JMP) | |
08e17202 ILT |
1668 | { |
1669 | /* Make sure there is enough room to swap this instruction with | |
1670 | a following jump instruction. */ | |
1671 | frag_grow (6); | |
1672 | f = frag_more (2); | |
1673 | } | |
cc5703cd | 1674 | else |
035936da | 1675 | { |
3c83da8a JW |
1676 | if (mips_opts.mips16 |
1677 | && mips_opts.noreorder | |
035936da ILT |
1678 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) |
1679 | as_warn ("extended instruction in delay slot"); | |
1680 | ||
1681 | f = frag_more (4); | |
1682 | } | |
1683 | ||
becfe05e | 1684 | fixp = NULL; |
cc5703cd | 1685 | if (address_expr != NULL && reloc_type < BFD_RELOC_UNUSED) |
670a50eb | 1686 | { |
5ac34ac3 | 1687 | if (address_expr->X_op == O_constant) |
670a50eb ILT |
1688 | { |
1689 | switch (reloc_type) | |
1690 | { | |
3d3c5039 | 1691 | case BFD_RELOC_32: |
670a50eb ILT |
1692 | ip->insn_opcode |= address_expr->X_add_number; |
1693 | break; | |
3d3c5039 ILT |
1694 | |
1695 | case BFD_RELOC_LO16: | |
670a50eb ILT |
1696 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
1697 | break; | |
3d3c5039 ILT |
1698 | |
1699 | case BFD_RELOC_MIPS_JMP: | |
39bb58e0 ILT |
1700 | if ((address_expr->X_add_number & 3) != 0) |
1701 | as_bad ("jump to misaligned address (0x%lx)", | |
1702 | (unsigned long) address_expr->X_add_number); | |
5e1e8f23 ILT |
1703 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; |
1704 | break; | |
1705 | ||
cc5703cd | 1706 | case BFD_RELOC_MIPS16_JMP: |
39bb58e0 ILT |
1707 | if ((address_expr->X_add_number & 3) != 0) |
1708 | as_bad ("jump to misaligned address (0x%lx)", | |
1709 | (unsigned long) address_expr->X_add_number); | |
cc5703cd ILT |
1710 | ip->insn_opcode |= |
1711 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
1712 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
1713 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
1714 | break; | |
1715 | ||
3d3c5039 | 1716 | case BFD_RELOC_16_PCREL_S2: |
670a50eb | 1717 | goto need_reloc; |
3d3c5039 ILT |
1718 | |
1719 | default: | |
670a50eb | 1720 | internalError (); |
3d3c5039 | 1721 | } |
670a50eb ILT |
1722 | } |
1723 | else | |
1724 | { | |
3d3c5039 | 1725 | need_reloc: |
0dd2d296 ILT |
1726 | /* Don't generate a reloc if we are writing into a variant |
1727 | frag. */ | |
1728 | if (place == NULL) | |
867a58b3 ILT |
1729 | { |
1730 | fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 4, | |
1731 | address_expr, | |
1732 | reloc_type == BFD_RELOC_16_PCREL_S2, | |
1733 | reloc_type); | |
1734 | if (unmatched_hi) | |
1735 | { | |
1736 | struct mips_hi_fixup *hi_fixup; | |
1737 | ||
1738 | assert (reloc_type == BFD_RELOC_HI16_S); | |
1739 | hi_fixup = ((struct mips_hi_fixup *) | |
1740 | xmalloc (sizeof (struct mips_hi_fixup))); | |
1741 | hi_fixup->fixp = fixp; | |
1742 | hi_fixup->seg = now_seg; | |
1743 | hi_fixup->next = mips_hi_fixup_list; | |
1744 | mips_hi_fixup_list = hi_fixup; | |
1745 | } | |
1746 | } | |
3d3c5039 ILT |
1747 | } |
1748 | } | |
becfe05e | 1749 | |
3c83da8a | 1750 | if (! mips_opts.mips16) |
cc5703cd | 1751 | md_number_to_chars (f, ip->insn_opcode, 4); |
16262668 ILT |
1752 | else if (reloc_type == BFD_RELOC_MIPS16_JMP) |
1753 | { | |
1754 | md_number_to_chars (f, ip->insn_opcode >> 16, 2); | |
1755 | md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2); | |
1756 | } | |
cc5703cd ILT |
1757 | else |
1758 | { | |
1759 | if (ip->use_extend) | |
1760 | { | |
1761 | md_number_to_chars (f, 0xf000 | ip->extend, 2); | |
1762 | f += 2; | |
1763 | } | |
1764 | md_number_to_chars (f, ip->insn_opcode, 2); | |
1765 | } | |
670a50eb | 1766 | |
1aa6938e | 1767 | /* Update the register mask information. */ |
3c83da8a | 1768 | if (! mips_opts.mips16) |
cc5703cd ILT |
1769 | { |
1770 | if (pinfo & INSN_WRITE_GPR_D) | |
1771 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD); | |
1772 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) | |
1773 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT); | |
1774 | if (pinfo & INSN_READ_GPR_S) | |
1775 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS); | |
1776 | if (pinfo & INSN_WRITE_GPR_31) | |
1777 | mips_gprmask |= 1 << 31; | |
1778 | if (pinfo & INSN_WRITE_FPR_D) | |
1779 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD); | |
1780 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) | |
1781 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS); | |
1782 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) | |
1783 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT); | |
1784 | if ((pinfo & INSN_READ_FPR_R) != 0) | |
1785 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR); | |
1786 | if (pinfo & INSN_COP) | |
1787 | { | |
efec4a28 DP |
1788 | /* We don't keep enough information to sort these cases out. |
1789 | The itbl support does keep this information however, although | |
1790 | we currently don't support itbl fprmats as part of the cop | |
1791 | instruction. May want to add this support in the future. */ | |
cc5703cd ILT |
1792 | } |
1793 | /* Never set the bit for $0, which is always zero. */ | |
1794 | mips_gprmask &=~ 1 << 0; | |
1795 | } | |
1796 | else | |
1aa6938e | 1797 | { |
cc5703cd ILT |
1798 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) |
1799 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX) | |
1800 | & MIPS16OP_MASK_RX); | |
1801 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) | |
1802 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY) | |
1803 | & MIPS16OP_MASK_RY); | |
1804 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
1805 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ) | |
1806 | & MIPS16OP_MASK_RZ); | |
1807 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) | |
1808 | mips_gprmask |= 1 << TREG; | |
1809 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
1810 | mips_gprmask |= 1 << SP; | |
1811 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
1812 | mips_gprmask |= 1 << RA; | |
1813 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
1814 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
1815 | if (pinfo & MIPS16_INSN_READ_Z) | |
1816 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1817 | & MIPS16OP_MASK_MOVE32Z); | |
1818 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
1819 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1820 | & MIPS16OP_MASK_REGR32); | |
1aa6938e | 1821 | } |
1aa6938e | 1822 | |
3c83da8a | 1823 | if (place == NULL && ! mips_opts.noreorder) |
670a50eb | 1824 | { |
becfe05e ILT |
1825 | /* Filling the branch delay slot is more complex. We try to |
1826 | switch the branch with the previous instruction, which we can | |
1827 | do if the previous instruction does not set up a condition | |
1828 | that the branch tests and if the branch is not itself the | |
1829 | target of any branch. */ | |
1aa6938e ILT |
1830 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) |
1831 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
becfe05e | 1832 | { |
0aa07269 | 1833 | if (mips_optimize < 2 |
19ed8960 ILT |
1834 | /* If we have seen .set volatile or .set nomove, don't |
1835 | optimize. */ | |
3c83da8a | 1836 | || mips_opts.nomove != 0 |
4e95866e ILT |
1837 | /* If we had to emit any NOP instructions, then we |
1838 | already know we can not swap. */ | |
1839 | || nops != 0 | |
becfe05e ILT |
1840 | /* If we don't even know the previous insn, we can not |
1841 | swap. */ | |
1842 | || ! prev_insn_valid | |
1843 | /* If the previous insn is already in a branch delay | |
1844 | slot, then we can not swap. */ | |
1845 | || prev_insn_is_delay_slot | |
4e95866e ILT |
1846 | /* If the previous previous insn was in a .set |
1847 | noreorder, we can't swap. Actually, the MIPS | |
1848 | assembler will swap in this situation. However, gcc | |
1849 | configured -with-gnu-as will generate code like | |
1850 | .set noreorder | |
1851 | lw $4,XXX | |
1852 | .set reorder | |
1853 | INSN | |
1854 | bne $4,$0,foo | |
1855 | in which we can not swap the bne and INSN. If gcc is | |
1856 | not configured -with-gnu-as, it does not output the | |
1857 | .set pseudo-ops. We don't have to check | |
1858 | prev_insn_unreordered, because prev_insn_valid will | |
1859 | be 0 in that case. We don't want to use | |
1860 | prev_prev_insn_valid, because we do want to be able | |
1861 | to swap at the start of a function. */ | |
1862 | || prev_prev_insn_unreordered | |
becfe05e ILT |
1863 | /* If the branch is itself the target of a branch, we |
1864 | can not swap. We cheat on this; all we check for is | |
1865 | whether there is a label on this instruction. If | |
1866 | there are any branches to anything other than a | |
1867 | label, users must use .set noreorder. */ | |
fbcfacb7 | 1868 | || insn_labels != NULL |
777ad64d | 1869 | /* If the previous instruction is in a variant frag, we |
cc5703cd ILT |
1870 | can not do the swap. This does not apply to the |
1871 | mips16, which uses variant frags for different | |
1872 | purposes. */ | |
3c83da8a | 1873 | || (! mips_opts.mips16 |
cc5703cd | 1874 | && prev_insn_frag->fr_type == rs_machine_dependent) |
becfe05e ILT |
1875 | /* If the branch reads the condition codes, we don't |
1876 | even try to swap, because in the sequence | |
1877 | ctc1 $X,$31 | |
1878 | INSN | |
1879 | INSN | |
1880 | bc1t LABEL | |
1881 | we can not swap, and I don't feel like handling that | |
1882 | case. */ | |
3c83da8a JW |
1883 | || (! mips_opts.mips16 |
1884 | && mips_opts.isa < 4 | |
d8a1c247 | 1885 | && (pinfo & INSN_READ_COND_CODE)) |
becfe05e ILT |
1886 | /* We can not swap with an instruction that requires a |
1887 | delay slot, becase the target of the branch might | |
1888 | interfere with that instruction. */ | |
3c83da8a JW |
1889 | || (! mips_opts.mips16 |
1890 | && mips_opts.isa < 4 | |
d8a1c247 | 1891 | && (prev_pinfo |
efec4a28 | 1892 | /* Itbl support may require additional care here. */ |
d8a1c247 KR |
1893 | & (INSN_LOAD_COPROC_DELAY |
1894 | | INSN_COPROC_MOVE_DELAY | |
1895 | | INSN_WRITE_COND_CODE))) | |
5c6f5923 | 1896 | || (! hilo_interlocks |
b2b8c24e ILT |
1897 | && (prev_pinfo |
1898 | & (INSN_READ_LO | |
1899 | | INSN_READ_HI))) | |
5c6f5923 GRK |
1900 | || (! mips_opts.mips16 |
1901 | && ! gpr_interlocks | |
1902 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)) | |
3c83da8a JW |
1903 | || (! mips_opts.mips16 |
1904 | && mips_opts.isa < 2 | |
5c6f5923 GRK |
1905 | /* Itbl support may require additional care here. */ |
1906 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)) | |
becfe05e | 1907 | /* We can not swap with a branch instruction. */ |
1aa6938e | 1908 | || (prev_pinfo |
6e8dda9c ILT |
1909 | & (INSN_UNCOND_BRANCH_DELAY |
1910 | | INSN_COND_BRANCH_DELAY | |
1911 | | INSN_COND_BRANCH_LIKELY)) | |
abdad6bc ILT |
1912 | /* We do not swap with a trap instruction, since it |
1913 | complicates trap handlers to have the trap | |
1914 | instruction be in a delay slot. */ | |
1aa6938e | 1915 | || (prev_pinfo & INSN_TRAP) |
becfe05e ILT |
1916 | /* If the branch reads a register that the previous |
1917 | instruction sets, we can not swap. */ | |
3c83da8a | 1918 | || (! mips_opts.mips16 |
cc5703cd | 1919 | && (prev_pinfo & INSN_WRITE_GPR_T) |
becfe05e ILT |
1920 | && insn_uses_reg (ip, |
1921 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1922 | & OP_MASK_RT), | |
cc5703cd | 1923 | MIPS_GR_REG)) |
3c83da8a | 1924 | || (! mips_opts.mips16 |
cc5703cd | 1925 | && (prev_pinfo & INSN_WRITE_GPR_D) |
becfe05e ILT |
1926 | && insn_uses_reg (ip, |
1927 | ((prev_insn.insn_opcode >> OP_SH_RD) | |
1928 | & OP_MASK_RD), | |
cc5703cd | 1929 | MIPS_GR_REG)) |
3c83da8a | 1930 | || (mips_opts.mips16 |
cc5703cd ILT |
1931 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) |
1932 | && insn_uses_reg (ip, | |
1933 | ((prev_insn.insn_opcode | |
1934 | >> MIPS16OP_SH_RX) | |
1935 | & MIPS16OP_MASK_RX), | |
1936 | MIPS16_REG)) | |
1937 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) | |
1938 | && insn_uses_reg (ip, | |
1939 | ((prev_insn.insn_opcode | |
1940 | >> MIPS16OP_SH_RY) | |
1941 | & MIPS16OP_MASK_RY), | |
1942 | MIPS16_REG)) | |
1943 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) | |
1944 | && insn_uses_reg (ip, | |
1945 | ((prev_insn.insn_opcode | |
1946 | >> MIPS16OP_SH_RZ) | |
1947 | & MIPS16OP_MASK_RZ), | |
1948 | MIPS16_REG)) | |
1949 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) | |
1950 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
1951 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
1952 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
1953 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
1954 | && insn_uses_reg (ip, | |
1955 | MIPS16OP_EXTRACT_REG32R (prev_insn. | |
1956 | insn_opcode), | |
1957 | MIPS_GR_REG)))) | |
1849d646 ILT |
1958 | /* If the branch writes a register that the previous |
1959 | instruction sets, we can not swap (we know that | |
1960 | branches write only to RD or to $31). */ | |
3c83da8a | 1961 | || (! mips_opts.mips16 |
cc5703cd | 1962 | && (prev_pinfo & INSN_WRITE_GPR_T) |
1aa6938e | 1963 | && (((pinfo & INSN_WRITE_GPR_D) |
1849d646 ILT |
1964 | && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT) |
1965 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
1aa6938e | 1966 | || ((pinfo & INSN_WRITE_GPR_31) |
1849d646 ILT |
1967 | && (((prev_insn.insn_opcode >> OP_SH_RT) |
1968 | & OP_MASK_RT) | |
1969 | == 31)))) | |
3c83da8a | 1970 | || (! mips_opts.mips16 |
cc5703cd | 1971 | && (prev_pinfo & INSN_WRITE_GPR_D) |
1aa6938e | 1972 | && (((pinfo & INSN_WRITE_GPR_D) |
1849d646 ILT |
1973 | && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD) |
1974 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
1aa6938e | 1975 | || ((pinfo & INSN_WRITE_GPR_31) |
1849d646 ILT |
1976 | && (((prev_insn.insn_opcode >> OP_SH_RD) |
1977 | & OP_MASK_RD) | |
1978 | == 31)))) | |
3c83da8a | 1979 | || (mips_opts.mips16 |
cc5703cd ILT |
1980 | && (pinfo & MIPS16_INSN_WRITE_31) |
1981 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
1982 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
1983 | && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode) | |
1984 | == RA)))) | |
becfe05e ILT |
1985 | /* If the branch writes a register that the previous |
1986 | instruction reads, we can not swap (we know that | |
1987 | branches only write to RD or to $31). */ | |
3c83da8a | 1988 | || (! mips_opts.mips16 |
cc5703cd | 1989 | && (pinfo & INSN_WRITE_GPR_D) |
becfe05e ILT |
1990 | && insn_uses_reg (&prev_insn, |
1991 | ((ip->insn_opcode >> OP_SH_RD) | |
1992 | & OP_MASK_RD), | |
cc5703cd | 1993 | MIPS_GR_REG)) |
3c83da8a | 1994 | || (! mips_opts.mips16 |
cc5703cd ILT |
1995 | && (pinfo & INSN_WRITE_GPR_31) |
1996 | && insn_uses_reg (&prev_insn, 31, MIPS_GR_REG)) | |
3c83da8a | 1997 | || (mips_opts.mips16 |
cc5703cd ILT |
1998 | && (pinfo & MIPS16_INSN_WRITE_31) |
1999 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) | |
5b63f465 ILT |
2000 | /* If we are generating embedded PIC code, the branch |
2001 | might be expanded into a sequence which uses $at, so | |
2002 | we can't swap with an instruction which reads it. */ | |
2003 | || (mips_pic == EMBEDDED_PIC | |
cc5703cd | 2004 | && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG)) |
becfe05e ILT |
2005 | /* If the previous previous instruction has a load |
2006 | delay, and sets a register that the branch reads, we | |
2007 | can not swap. */ | |
3c83da8a JW |
2008 | || (! mips_opts.mips16 |
2009 | && mips_opts.isa < 4 | |
efec4a28 | 2010 | /* Itbl support may require additional care here. */ |
d8a1c247 | 2011 | && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) |
5c6f5923 | 2012 | || (! gpr_interlocks |
d8a1c247 KR |
2013 | && (prev_prev_insn.insn_mo->pinfo |
2014 | & INSN_LOAD_MEMORY_DELAY))) | |
becfe05e ILT |
2015 | && insn_uses_reg (ip, |
2016 | ((prev_prev_insn.insn_opcode >> OP_SH_RT) | |
2017 | & OP_MASK_RT), | |
cc5703cd | 2018 | MIPS_GR_REG)) |
d31a3f5e ILT |
2019 | /* If one instruction sets a condition code and the |
2020 | other one uses a condition code, we can not swap. */ | |
2021 | || ((pinfo & INSN_READ_COND_CODE) | |
2022 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
2023 | || ((pinfo & INSN_WRITE_COND_CODE) | |
cc5703cd ILT |
2024 | && (prev_pinfo & INSN_READ_COND_CODE)) |
2025 | /* If the previous instruction uses the PC, we can not | |
2026 | swap. */ | |
3c83da8a | 2027 | || (mips_opts.mips16 |
cc5703cd ILT |
2028 | && (prev_pinfo & MIPS16_INSN_READ_PC)) |
2029 | /* If the previous instruction was extended, we can not | |
2030 | swap. */ | |
3c83da8a | 2031 | || (mips_opts.mips16 && prev_insn_extended) |
cc5703cd ILT |
2032 | /* If the previous instruction had a fixup in mips16 |
2033 | mode, we can not swap. This normally means that the | |
2034 | previous instruction was a 4 byte branch anyhow. */ | |
3c83da8a | 2035 | || (mips_opts.mips16 && prev_insn_fixp)) |
becfe05e ILT |
2036 | { |
2037 | /* We could do even better for unconditional branches to | |
2038 | portions of this object file; we could pick up the | |
2039 | instruction at the destination, put it in the delay | |
2040 | slot, and bump the destination address. */ | |
2041 | emit_nop (); | |
2042 | /* Update the previous insn information. */ | |
2043 | prev_prev_insn = *ip; | |
2044 | prev_insn.insn_mo = &dummy_opcode; | |
2045 | } | |
2046 | else | |
2047 | { | |
becfe05e | 2048 | /* It looks like we can actually do the swap. */ |
3c83da8a | 2049 | if (! mips_opts.mips16) |
cc5703cd ILT |
2050 | { |
2051 | char *prev_f; | |
2052 | char temp[4]; | |
2053 | ||
2054 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
2055 | memcpy (temp, prev_f, 4); | |
2056 | memcpy (prev_f, f, 4); | |
2057 | memcpy (f, temp, 4); | |
2058 | if (prev_insn_fixp) | |
2059 | { | |
2060 | prev_insn_fixp->fx_frag = frag_now; | |
2061 | prev_insn_fixp->fx_where = f - frag_now->fr_literal; | |
2062 | } | |
2063 | if (fixp) | |
2064 | { | |
2065 | fixp->fx_frag = prev_insn_frag; | |
2066 | fixp->fx_where = prev_insn_where; | |
2067 | } | |
2068 | } | |
cc5703cd | 2069 | else |
becfe05e | 2070 | { |
cc5703cd ILT |
2071 | char *prev_f; |
2072 | char temp[2]; | |
2073 | ||
2074 | assert (prev_insn_fixp == NULL); | |
2075 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
2076 | memcpy (temp, prev_f, 2); | |
2077 | memcpy (prev_f, f, 2); | |
2078 | if (reloc_type != BFD_RELOC_MIPS16_JMP) | |
9cd4e6cc ILT |
2079 | { |
2080 | assert (reloc_type == BFD_RELOC_UNUSED); | |
2081 | memcpy (f, temp, 2); | |
2082 | } | |
cc5703cd ILT |
2083 | else |
2084 | { | |
2085 | memcpy (f, f + 2, 2); | |
2086 | memcpy (f + 2, temp, 2); | |
2087 | } | |
2088 | if (fixp) | |
2089 | { | |
2090 | fixp->fx_frag = prev_insn_frag; | |
2091 | fixp->fx_where = prev_insn_where; | |
2092 | } | |
becfe05e | 2093 | } |
cc5703cd | 2094 | |
becfe05e ILT |
2095 | /* Update the previous insn information; leave prev_insn |
2096 | unchanged. */ | |
2097 | prev_prev_insn = *ip; | |
2098 | } | |
2099 | prev_insn_is_delay_slot = 1; | |
2100 | ||
2101 | /* If that was an unconditional branch, forget the previous | |
2102 | insn information. */ | |
1aa6938e | 2103 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) |
becfe05e ILT |
2104 | { |
2105 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2106 | prev_insn.insn_mo = &dummy_opcode; | |
2107 | } | |
a677feeb ILT |
2108 | |
2109 | prev_insn_fixp = NULL; | |
2110 | prev_insn_reloc_type = BFD_RELOC_UNUSED; | |
2111 | prev_insn_extended = 0; | |
becfe05e | 2112 | } |
1aa6938e | 2113 | else if (pinfo & INSN_COND_BRANCH_LIKELY) |
8358c818 ILT |
2114 | { |
2115 | /* We don't yet optimize a branch likely. What we should do | |
2116 | is look at the target, copy the instruction found there | |
2117 | into the delay slot, and increment the branch to jump to | |
2118 | the next instruction. */ | |
2119 | emit_nop (); | |
2120 | /* Update the previous insn information. */ | |
2121 | prev_prev_insn = *ip; | |
2122 | prev_insn.insn_mo = &dummy_opcode; | |
a677feeb ILT |
2123 | prev_insn_fixp = NULL; |
2124 | prev_insn_reloc_type = BFD_RELOC_UNUSED; | |
2125 | prev_insn_extended = 0; | |
8358c818 | 2126 | } |
becfe05e | 2127 | else |
670a50eb | 2128 | { |
becfe05e ILT |
2129 | /* Update the previous insn information. */ |
2130 | if (nops > 0) | |
2131 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2132 | else | |
2133 | prev_prev_insn = prev_insn; | |
2134 | prev_insn = *ip; | |
2135 | ||
2136 | /* Any time we see a branch, we always fill the delay slot | |
2137 | immediately; since this insn is not a branch, we know it | |
2138 | is not in a delay slot. */ | |
2139 | prev_insn_is_delay_slot = 0; | |
a677feeb ILT |
2140 | |
2141 | prev_insn_fixp = fixp; | |
2142 | prev_insn_reloc_type = reloc_type; | |
3c83da8a | 2143 | if (mips_opts.mips16) |
a677feeb ILT |
2144 | prev_insn_extended = (ip->use_extend |
2145 | || reloc_type > BFD_RELOC_UNUSED); | |
becfe05e ILT |
2146 | } |
2147 | ||
4e95866e ILT |
2148 | prev_prev_insn_unreordered = prev_insn_unreordered; |
2149 | prev_insn_unreordered = 0; | |
becfe05e ILT |
2150 | prev_insn_frag = frag_now; |
2151 | prev_insn_where = f - frag_now->fr_literal; | |
becfe05e ILT |
2152 | prev_insn_valid = 1; |
2153 | } | |
fbcfacb7 | 2154 | else if (place == NULL) |
a677feeb | 2155 | { |
fbcfacb7 | 2156 | /* We need to record a bit of information even when we are not |
a677feeb ILT |
2157 | reordering, in order to determine the base address for mips16 |
2158 | PC relative relocs. */ | |
4a1cb507 | 2159 | prev_prev_insn = prev_insn; |
a677feeb ILT |
2160 | prev_insn = *ip; |
2161 | prev_insn_reloc_type = reloc_type; | |
4a1cb507 ILT |
2162 | prev_prev_insn_unreordered = prev_insn_unreordered; |
2163 | prev_insn_unreordered = 1; | |
a677feeb | 2164 | } |
3d3c5039 | 2165 | |
becfe05e | 2166 | /* We just output an insn, so the next one doesn't have a label. */ |
fbcfacb7 | 2167 | mips_clear_insn_labels (); |
becfe05e ILT |
2168 | } |
2169 | ||
2170 | /* This function forgets that there was any previous instruction or | |
4a1cb507 ILT |
2171 | label. If PRESERVE is non-zero, it remembers enough information to |
2172 | know whether nops are needed before a noreorder section. */ | |
becfe05e ILT |
2173 | |
2174 | static void | |
4a1cb507 ILT |
2175 | mips_no_prev_insn (preserve) |
2176 | int preserve; | |
becfe05e | 2177 | { |
4a1cb507 ILT |
2178 | if (! preserve) |
2179 | { | |
2180 | prev_insn.insn_mo = &dummy_opcode; | |
2181 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2182 | prev_nop_frag = NULL; | |
2183 | prev_nop_frag_holds = 0; | |
2184 | prev_nop_frag_required = 0; | |
2185 | prev_nop_frag_since = 0; | |
2186 | } | |
becfe05e ILT |
2187 | prev_insn_valid = 0; |
2188 | prev_insn_is_delay_slot = 0; | |
4e95866e | 2189 | prev_insn_unreordered = 0; |
cc5703cd | 2190 | prev_insn_extended = 0; |
a677feeb | 2191 | prev_insn_reloc_type = BFD_RELOC_UNUSED; |
4e95866e | 2192 | prev_prev_insn_unreordered = 0; |
fbcfacb7 | 2193 | mips_clear_insn_labels (); |
becfe05e ILT |
2194 | } |
2195 | ||
2196 | /* This function must be called whenever we turn on noreorder or emit | |
2197 | something other than instructions. It inserts any NOPS which might | |
2198 | be needed by the previous instruction, and clears the information | |
fbcfacb7 ILT |
2199 | kept for the previous instructions. The INSNS parameter is true if |
2200 | instructions are to follow. */ | |
becfe05e ILT |
2201 | |
2202 | static void | |
fbcfacb7 ILT |
2203 | mips_emit_delays (insns) |
2204 | boolean insns; | |
becfe05e | 2205 | { |
3c83da8a | 2206 | if (! mips_opts.noreorder) |
becfe05e | 2207 | { |
4a1cb507 | 2208 | int nops; |
becfe05e | 2209 | |
4a1cb507 | 2210 | nops = 0; |
3c83da8a JW |
2211 | if ((! mips_opts.mips16 |
2212 | && mips_opts.isa < 4 | |
344a8d61 JSC |
2213 | && (! cop_interlocks |
2214 | && (prev_insn.insn_mo->pinfo | |
2215 | & (INSN_LOAD_COPROC_DELAY | |
2216 | | INSN_COPROC_MOVE_DELAY | |
2217 | | INSN_WRITE_COND_CODE)))) | |
5c6f5923 | 2218 | || (! hilo_interlocks |
b2b8c24e ILT |
2219 | && (prev_insn.insn_mo->pinfo |
2220 | & (INSN_READ_LO | |
2221 | | INSN_READ_HI))) | |
5c6f5923 GRK |
2222 | || (! mips_opts.mips16 |
2223 | && ! gpr_interlocks | |
2224 | && (prev_insn.insn_mo->pinfo | |
2225 | & INSN_LOAD_MEMORY_DELAY)) | |
3c83da8a JW |
2226 | || (! mips_opts.mips16 |
2227 | && mips_opts.isa < 2 | |
8358c818 | 2228 | && (prev_insn.insn_mo->pinfo |
5c6f5923 | 2229 | & INSN_COPROC_MEMORY_DELAY))) |
becfe05e | 2230 | { |
efec4a28 | 2231 | /* Itbl support may require additional care here. */ |
4a1cb507 | 2232 | ++nops; |
3c83da8a JW |
2233 | if ((! mips_opts.mips16 |
2234 | && mips_opts.isa < 4 | |
344a8d61 JSC |
2235 | && (! cop_interlocks |
2236 | && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
5c6f5923 | 2237 | || (! hilo_interlocks |
b2b8c24e ILT |
2238 | && ((prev_insn.insn_mo->pinfo & INSN_READ_HI) |
2239 | || (prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
4a1cb507 ILT |
2240 | ++nops; |
2241 | ||
2242 | if (prev_insn_unreordered) | |
2243 | nops = 0; | |
becfe05e | 2244 | } |
3c83da8a JW |
2245 | else if ((! mips_opts.mips16 |
2246 | && mips_opts.isa < 4 | |
344a8d61 JSC |
2247 | && (! cop_interlocks |
2248 | && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
5c6f5923 | 2249 | || (! hilo_interlocks |
b2b8c24e ILT |
2250 | && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
2251 | || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
4a1cb507 | 2252 | { |
efec4a28 | 2253 | /* Itbl support may require additional care here. */ |
4a1cb507 ILT |
2254 | if (! prev_prev_insn_unreordered) |
2255 | ++nops; | |
2256 | } | |
2257 | ||
2258 | if (nops > 0) | |
670a50eb | 2259 | { |
fbcfacb7 ILT |
2260 | struct insn_label_list *l; |
2261 | ||
4a1cb507 ILT |
2262 | if (insns) |
2263 | { | |
2264 | /* Record the frag which holds the nop instructions, so | |
2265 | that we can remove them if we don't need them. */ | |
3c83da8a | 2266 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); |
4a1cb507 ILT |
2267 | prev_nop_frag = frag_now; |
2268 | prev_nop_frag_holds = nops; | |
2269 | prev_nop_frag_required = 0; | |
2270 | prev_nop_frag_since = 0; | |
2271 | } | |
2272 | ||
2273 | for (; nops > 0; --nops) | |
2274 | emit_nop (); | |
2275 | ||
2276 | if (insns) | |
2277 | { | |
2278 | /* Move on to a new frag, so that it is safe to simply | |
2279 | decrease the size of prev_nop_frag. */ | |
2280 | frag_wane (frag_now); | |
2281 | frag_new (0); | |
2282 | } | |
2283 | ||
fbcfacb7 | 2284 | for (l = insn_labels; l != NULL; l = l->next) |
becfe05e | 2285 | { |
fbcfacb7 ILT |
2286 | assert (S_GET_SEGMENT (l->label) == now_seg); |
2287 | l->label->sy_frag = frag_now; | |
2288 | S_SET_VALUE (l->label, (valueT) frag_now_fix ()); | |
2289 | /* mips16 text labels are stored as odd. */ | |
3c83da8a | 2290 | if (mips_opts.mips16) |
fbcfacb7 | 2291 | ++l->label->sy_value.X_add_number; |
becfe05e | 2292 | } |
3d3c5039 ILT |
2293 | } |
2294 | } | |
0221ddf7 | 2295 | |
3c83da8a JW |
2296 | /* Mark instruction labels in mips16 mode. */ |
2297 | if (mips_opts.mips16 && insns) | |
2298 | mips16_mark_labels (); | |
fbcfacb7 | 2299 | |
4a1cb507 | 2300 | mips_no_prev_insn (insns); |
3d3c5039 ILT |
2301 | } |
2302 | ||
670a50eb ILT |
2303 | /* Build an instruction created by a macro expansion. This is passed |
2304 | a pointer to the count of instructions created so far, an | |
2305 | expression, the name of the instruction to build, an operand format | |
2306 | string, and corresponding arguments. */ | |
2307 | ||
1dc1e798 | 2308 | #ifdef USE_STDARG |
3d3c5039 | 2309 | static void |
0dd2d296 ILT |
2310 | macro_build (char *place, |
2311 | int *counter, | |
670a50eb | 2312 | expressionS * ep, |
3d3c5039 ILT |
2313 | const char *name, |
2314 | const char *fmt, | |
2315 | ...) | |
1dc1e798 | 2316 | #else |
3d3c5039 | 2317 | static void |
0dd2d296 ILT |
2318 | macro_build (place, counter, ep, name, fmt, va_alist) |
2319 | char *place; | |
3d3c5039 ILT |
2320 | int *counter; |
2321 | expressionS *ep; | |
2322 | const char *name; | |
2323 | const char *fmt; | |
2324 | va_dcl | |
1dc1e798 | 2325 | #endif |
3d3c5039 | 2326 | { |
670a50eb ILT |
2327 | struct mips_cl_insn insn; |
2328 | bfd_reloc_code_real_type r; | |
2329 | va_list args; | |
931a1858 | 2330 | int insn_isa; |
3d3c5039 | 2331 | |
1dc1e798 | 2332 | #ifdef USE_STDARG |
670a50eb | 2333 | va_start (args, fmt); |
3d3c5039 | 2334 | #else |
670a50eb | 2335 | va_start (args); |
3d3c5039 ILT |
2336 | #endif |
2337 | ||
670a50eb ILT |
2338 | /* |
2339 | * If the macro is about to expand into a second instruction, | |
2340 | * print a warning if needed. We need to pass ip as a parameter | |
2341 | * to generate a better warning message here... | |
2342 | */ | |
3c83da8a | 2343 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) |
670a50eb ILT |
2344 | as_warn ("Macro instruction expanded into multiple instructions"); |
2345 | ||
0dd2d296 ILT |
2346 | if (place == NULL) |
2347 | *counter += 1; /* bump instruction counter */ | |
670a50eb | 2348 | |
3c83da8a | 2349 | if (mips_opts.mips16) |
cc5703cd ILT |
2350 | { |
2351 | mips16_macro_build (place, counter, ep, name, fmt, args); | |
2352 | va_end (args); | |
2353 | return; | |
2354 | } | |
2355 | ||
670a50eb ILT |
2356 | r = BFD_RELOC_UNUSED; |
2357 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
2358 | assert (insn.insn_mo); | |
2359 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2360 | ||
931a1858 JL |
2361 | |
2362 | /* Search until we get a match for NAME. */ | |
2363 | while (1) | |
670a50eb | 2364 | { |
931a1858 JL |
2365 | if (insn.insn_mo->pinfo == INSN_MACRO) |
2366 | insn_isa = insn.insn_mo->match; | |
2367 | else if ((insn.insn_mo->membership & INSN_ISA) == INSN_ISA1) | |
2368 | insn_isa = 1; | |
2369 | else if ((insn.insn_mo->membership & INSN_ISA) == INSN_ISA2) | |
2370 | insn_isa = 2; | |
2371 | else if ((insn.insn_mo->membership & INSN_ISA) == INSN_ISA3) | |
2372 | insn_isa = 3; | |
2373 | else if ((insn.insn_mo->membership & INSN_ISA) == INSN_ISA4) | |
2374 | insn_isa = 4; | |
2375 | else | |
2376 | insn_isa = 15; | |
2377 | ||
2378 | if (insn_isa > mips_opts.isa | |
2379 | && (insn.insn_mo->pinfo != INSN_MACRO | |
2380 | && ((mips_4650 | |
2381 | && (insn.insn_mo->membership & INSN_4650) != INSN_4650) | |
2382 | || (mips_4650 && (insn.insn_mo->pinfo & FP_D)) | |
2383 | || (mips_4010 | |
2384 | && (insn.insn_mo->membership & INSN_4010) != INSN_4010) | |
2385 | || (mips_4100 | |
2386 | && (insn.insn_mo->membership & INSN_4100) != INSN_4100) | |
2387 | /* start-sanitize-r5900 */ | |
2388 | || (mips_5900 | |
2389 | && (insn.insn_mo->membership & INSN_5900) != INSN_5900) | |
2390 | || (mips_5900 && (insn.insn_mo->pinfo & FP_D)) | |
2391 | /* end-sanitize-r5900 */ | |
2392 | || (mips_3900 | |
2393 | && (insn.insn_mo->membership & INSN_3900) != INSN_3900)))) | |
2394 | { | |
2395 | ++insn.insn_mo; | |
2396 | assert (insn.insn_mo->name); | |
2397 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2398 | continue; | |
2399 | } | |
2400 | ||
2401 | /* We got a successful match. */ | |
2402 | break; | |
3d3c5039 | 2403 | } |
931a1858 | 2404 | |
670a50eb ILT |
2405 | insn.insn_opcode = insn.insn_mo->match; |
2406 | for (;;) | |
2407 | { | |
2408 | switch (*fmt++) | |
2409 | { | |
3d3c5039 | 2410 | case '\0': |
670a50eb | 2411 | break; |
3d3c5039 ILT |
2412 | |
2413 | case ',': | |
2414 | case '(': | |
2415 | case ')': | |
670a50eb | 2416 | continue; |
3d3c5039 ILT |
2417 | |
2418 | case 't': | |
2419 | case 'w': | |
918692a5 | 2420 | case 'E': |
670a50eb ILT |
2421 | insn.insn_opcode |= va_arg (args, int) << 16; |
2422 | continue; | |
3d3c5039 ILT |
2423 | |
2424 | case 'c': | |
2425 | case 'T': | |
2426 | case 'W': | |
670a50eb ILT |
2427 | insn.insn_opcode |= va_arg (args, int) << 16; |
2428 | continue; | |
3d3c5039 ILT |
2429 | |
2430 | case 'd': | |
918692a5 | 2431 | case 'G': |
670a50eb ILT |
2432 | insn.insn_opcode |= va_arg (args, int) << 11; |
2433 | continue; | |
3d3c5039 ILT |
2434 | |
2435 | case 'V': | |
2436 | case 'S': | |
670a50eb ILT |
2437 | insn.insn_opcode |= va_arg (args, int) << 11; |
2438 | continue; | |
3d3c5039 | 2439 | |
ff3a5c18 ILT |
2440 | case 'z': |
2441 | continue; | |
2442 | ||
3d3c5039 | 2443 | case '<': |
670a50eb ILT |
2444 | insn.insn_opcode |= va_arg (args, int) << 6; |
2445 | continue; | |
3d3c5039 ILT |
2446 | |
2447 | case 'D': | |
670a50eb ILT |
2448 | insn.insn_opcode |= va_arg (args, int) << 6; |
2449 | continue; | |
3d3c5039 | 2450 | |
918692a5 ILT |
2451 | case 'B': |
2452 | insn.insn_opcode |= va_arg (args, int) << 6; | |
2453 | continue; | |
2454 | ||
3d3c5039 ILT |
2455 | case 'b': |
2456 | case 's': | |
2457 | case 'r': | |
2458 | case 'v': | |
670a50eb ILT |
2459 | insn.insn_opcode |= va_arg (args, int) << 21; |
2460 | continue; | |
3d3c5039 ILT |
2461 | |
2462 | case 'i': | |
2463 | case 'j': | |
2464 | case 'o': | |
9226253a | 2465 | r = (bfd_reloc_code_real_type) va_arg (args, int); |
0dd2d296 ILT |
2466 | assert (r == BFD_RELOC_MIPS_GPREL |
2467 | || r == BFD_RELOC_MIPS_LITERAL | |
2468 | || r == BFD_RELOC_LO16 | |
2469 | || r == BFD_RELOC_MIPS_GOT16 | |
ecd4ca1c | 2470 | || r == BFD_RELOC_MIPS_CALL16 |
fb251650 ILT |
2471 | || r == BFD_RELOC_MIPS_GOT_LO16 |
2472 | || r == BFD_RELOC_MIPS_CALL_LO16 | |
ecd4ca1c ILT |
2473 | || (ep->X_op == O_subtract |
2474 | && now_seg == text_section | |
ecd4ca1c | 2475 | && r == BFD_RELOC_PCREL_LO16)); |
670a50eb | 2476 | continue; |
3d3c5039 | 2477 | |
6e8dda9c | 2478 | case 'u': |
ecd4ca1c ILT |
2479 | r = (bfd_reloc_code_real_type) va_arg (args, int); |
2480 | assert (ep != NULL | |
2481 | && (ep->X_op == O_constant | |
2482 | || (ep->X_op == O_symbol | |
2483 | && (r == BFD_RELOC_HI16_S | |
fb251650 ILT |
2484 | || r == BFD_RELOC_HI16 |
2485 | || r == BFD_RELOC_MIPS_GOT_HI16 | |
2486 | || r == BFD_RELOC_MIPS_CALL_HI16)) | |
ecd4ca1c ILT |
2487 | || (ep->X_op == O_subtract |
2488 | && now_seg == text_section | |
ecd4ca1c ILT |
2489 | && r == BFD_RELOC_PCREL_HI16_S))); |
2490 | if (ep->X_op == O_constant) | |
2491 | { | |
2492 | insn.insn_opcode |= (ep->X_add_number >> 16) & 0xffff; | |
2493 | ep = NULL; | |
2494 | r = BFD_RELOC_UNUSED; | |
2495 | } | |
6e8dda9c ILT |
2496 | continue; |
2497 | ||
3d3c5039 | 2498 | case 'p': |
670a50eb ILT |
2499 | assert (ep != NULL); |
2500 | /* | |
2501 | * This allows macro() to pass an immediate expression for | |
2502 | * creating short branches without creating a symbol. | |
2503 | * Note that the expression still might come from the assembly | |
2504 | * input, in which case the value is not checked for range nor | |
2505 | * is a relocation entry generated (yuck). | |
2506 | */ | |
5ac34ac3 | 2507 | if (ep->X_op == O_constant) |
670a50eb ILT |
2508 | { |
2509 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
2510 | ep = NULL; | |
2511 | } | |
2512 | else | |
2513 | r = BFD_RELOC_16_PCREL_S2; | |
2514 | continue; | |
3d3c5039 | 2515 | |
9226253a ILT |
2516 | case 'a': |
2517 | assert (ep != NULL); | |
2518 | r = BFD_RELOC_MIPS_JMP; | |
2519 | continue; | |
2520 | ||
3d3c5039 | 2521 | default: |
670a50eb | 2522 | internalError (); |
3d3c5039 | 2523 | } |
670a50eb | 2524 | break; |
3d3c5039 | 2525 | } |
670a50eb ILT |
2526 | va_end (args); |
2527 | assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
2528 | ||
867a58b3 | 2529 | append_insn (place, &insn, ep, r, false); |
3d3c5039 ILT |
2530 | } |
2531 | ||
cc5703cd ILT |
2532 | static void |
2533 | mips16_macro_build (place, counter, ep, name, fmt, args) | |
2534 | char *place; | |
2535 | int *counter; | |
2536 | expressionS *ep; | |
2537 | const char *name; | |
2538 | const char *fmt; | |
2539 | va_list args; | |
2540 | { | |
2541 | struct mips_cl_insn insn; | |
2542 | bfd_reloc_code_real_type r; | |
2543 | ||
2544 | r = BFD_RELOC_UNUSED; | |
2545 | insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); | |
2546 | assert (insn.insn_mo); | |
2547 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2548 | ||
2549 | while (strcmp (fmt, insn.insn_mo->args) != 0 | |
2550 | || insn.insn_mo->pinfo == INSN_MACRO) | |
2551 | { | |
2552 | ++insn.insn_mo; | |
2553 | assert (insn.insn_mo->name); | |
2554 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2555 | } | |
2556 | ||
2557 | insn.insn_opcode = insn.insn_mo->match; | |
2558 | insn.use_extend = false; | |
2559 | ||
2560 | for (;;) | |
2561 | { | |
2562 | int c; | |
2563 | ||
2564 | c = *fmt++; | |
2565 | switch (c) | |
2566 | { | |
2567 | case '\0': | |
2568 | break; | |
2569 | ||
2570 | case ',': | |
2571 | case '(': | |
2572 | case ')': | |
2573 | continue; | |
2574 | ||
2575 | case 'y': | |
2576 | case 'w': | |
2577 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY; | |
2578 | continue; | |
2579 | ||
2580 | case 'x': | |
2581 | case 'v': | |
2582 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX; | |
2583 | continue; | |
2584 | ||
2585 | case 'z': | |
2586 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ; | |
2587 | continue; | |
2588 | ||
2589 | case 'Z': | |
2590 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z; | |
2591 | continue; | |
2592 | ||
2593 | case '0': | |
2594 | case 'S': | |
2595 | case 'P': | |
2596 | case 'R': | |
2597 | continue; | |
2598 | ||
2599 | case 'X': | |
2600 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32; | |
2601 | continue; | |
2602 | ||
2603 | case 'Y': | |
2604 | { | |
2605 | int regno; | |
2606 | ||
2607 | regno = va_arg (args, int); | |
2608 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
2609 | insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
2610 | } | |
2611 | continue; | |
2612 | ||
2613 | case '<': | |
2614 | case '>': | |
2615 | case '4': | |
2616 | case '5': | |
2617 | case 'H': | |
2618 | case 'W': | |
2619 | case 'D': | |
2620 | case 'j': | |
2621 | case '8': | |
2622 | case 'V': | |
2623 | case 'C': | |
2624 | case 'U': | |
2625 | case 'k': | |
2626 | case 'K': | |
2627 | case 'p': | |
2628 | case 'q': | |
2629 | { | |
2630 | assert (ep != NULL); | |
2631 | ||
2632 | if (ep->X_op != O_constant) | |
2633 | r = BFD_RELOC_UNUSED + c; | |
2634 | else | |
2635 | { | |
15e69f98 ILT |
2636 | mips16_immed ((char *) NULL, 0, c, ep->X_add_number, false, |
2637 | false, false, &insn.insn_opcode, | |
2638 | &insn.use_extend, &insn.extend); | |
cc5703cd ILT |
2639 | ep = NULL; |
2640 | r = BFD_RELOC_UNUSED; | |
2641 | } | |
2642 | } | |
2643 | continue; | |
2644 | ||
2645 | case '6': | |
2646 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6; | |
2647 | continue; | |
2648 | } | |
2649 | ||
2650 | break; | |
2651 | } | |
2652 | ||
2653 | assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
2654 | ||
2655 | append_insn (place, &insn, ep, r, false); | |
2656 | } | |
2657 | ||
3d3c5039 ILT |
2658 | /* |
2659 | * Generate a "lui" instruction. | |
2660 | */ | |
2661 | static void | |
0dd2d296 ILT |
2662 | macro_build_lui (place, counter, ep, regnum) |
2663 | char *place; | |
3d3c5039 ILT |
2664 | int *counter; |
2665 | expressionS *ep; | |
2666 | int regnum; | |
2667 | { | |
670a50eb ILT |
2668 | expressionS high_expr; |
2669 | struct mips_cl_insn insn; | |
2670 | bfd_reloc_code_real_type r; | |
2671 | CONST char *name = "lui"; | |
2672 | CONST char *fmt = "t,u"; | |
2673 | ||
3c83da8a | 2674 | assert (! mips_opts.mips16); |
cc5703cd | 2675 | |
0dd2d296 ILT |
2676 | if (place == NULL) |
2677 | high_expr = *ep; | |
2678 | else | |
2679 | { | |
2680 | high_expr.X_op = O_constant; | |
fb251650 | 2681 | high_expr.X_add_number = ep->X_add_number; |
0dd2d296 | 2682 | } |
670a50eb | 2683 | |
5ac34ac3 | 2684 | if (high_expr.X_op == O_constant) |
670a50eb ILT |
2685 | { |
2686 | /* we can compute the instruction now without a relocation entry */ | |
2687 | if (high_expr.X_add_number & 0x8000) | |
2688 | high_expr.X_add_number += 0x10000; | |
2689 | high_expr.X_add_number = | |
2690 | ((unsigned long) high_expr.X_add_number >> 16) & 0xffff; | |
2691 | r = BFD_RELOC_UNUSED; | |
2692 | } | |
2693 | else | |
0dd2d296 ILT |
2694 | { |
2695 | assert (ep->X_op == O_symbol); | |
2696 | /* _gp_disp is a special case, used from s_cpload. */ | |
d9aba805 | 2697 | assert (mips_pic == NO_PIC |
0dd2d296 ILT |
2698 | || strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0); |
2699 | r = BFD_RELOC_HI16_S; | |
2700 | } | |
670a50eb ILT |
2701 | |
2702 | /* | |
2703 | * If the macro is about to expand into a second instruction, | |
2704 | * print a warning if needed. We need to pass ip as a parameter | |
2705 | * to generate a better warning message here... | |
2706 | */ | |
3c83da8a | 2707 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) |
670a50eb ILT |
2708 | as_warn ("Macro instruction expanded into multiple instructions"); |
2709 | ||
0dd2d296 ILT |
2710 | if (place == NULL) |
2711 | *counter += 1; /* bump instruction counter */ | |
670a50eb ILT |
2712 | |
2713 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
2714 | assert (insn.insn_mo); | |
2715 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2716 | assert (strcmp (fmt, insn.insn_mo->args) == 0); | |
2717 | ||
0dd2d296 | 2718 | insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT); |
670a50eb ILT |
2719 | if (r == BFD_RELOC_UNUSED) |
2720 | { | |
2721 | insn.insn_opcode |= high_expr.X_add_number; | |
867a58b3 | 2722 | append_insn (place, &insn, NULL, r, false); |
670a50eb ILT |
2723 | } |
2724 | else | |
867a58b3 | 2725 | append_insn (place, &insn, &high_expr, r, false); |
3d3c5039 ILT |
2726 | } |
2727 | ||
2728 | /* set_at() | |
2729 | * Generates code to set the $at register to true (one) | |
2730 | * if reg is less than the immediate expression. | |
2731 | */ | |
2732 | static void | |
6e8dda9c | 2733 | set_at (counter, reg, unsignedp) |
3d3c5039 ILT |
2734 | int *counter; |
2735 | int reg; | |
6e8dda9c | 2736 | int unsignedp; |
3d3c5039 | 2737 | { |
5c6f5923 GRK |
2738 | if (imm_expr.X_op == O_constant |
2739 | && imm_expr.X_add_number >= -0x8000 | |
2740 | && imm_expr.X_add_number < 0x8000) | |
0dd2d296 | 2741 | macro_build ((char *) NULL, counter, &imm_expr, |
6e8dda9c | 2742 | unsignedp ? "sltiu" : "slti", |
9226253a | 2743 | "t,r,j", AT, reg, (int) BFD_RELOC_LO16); |
6e8dda9c | 2744 | else |
670a50eb | 2745 | { |
d8a1c247 | 2746 | load_register (counter, AT, &imm_expr, 0); |
0dd2d296 | 2747 | macro_build ((char *) NULL, counter, NULL, |
6e8dda9c ILT |
2748 | unsignedp ? "sltu" : "slt", |
2749 | "d,v,t", AT, reg, AT); | |
670a50eb | 2750 | } |
3d3c5039 ILT |
2751 | } |
2752 | ||
6e8dda9c | 2753 | /* Warn if an expression is not a constant. */ |
3d3c5039 ILT |
2754 | |
2755 | static void | |
19ed8960 | 2756 | check_absolute_expr (ip, ex) |
3d3c5039 | 2757 | struct mips_cl_insn *ip; |
19ed8960 | 2758 | expressionS *ex; |
3d3c5039 | 2759 | { |
5c6f5923 GRK |
2760 | if (ex->X_op == O_big) |
2761 | as_bad ("unsupported large constant"); | |
2762 | else if (ex->X_op != O_constant) | |
4dc85508 | 2763 | as_bad ("Instruction %s requires absolute expression", ip->insn_mo->name); |
3d3c5039 ILT |
2764 | } |
2765 | ||
ff8716f5 JSC |
2766 | /* Count the leading zeroes by performing a binary chop. This is a |
2767 | bulky bit of source, but performance is a LOT better for the | |
2768 | majority of values than a simple loop to count the bits: | |
2769 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
2770 | if ((v) & (1 << (31 - lcnt))) | |
2771 | break; | |
2772 | However it is not code size friendly, and the gain will drop a bit | |
2773 | on certain cached systems. | |
2774 | */ | |
2775 | #define COUNT_TOP_ZEROES(v) \ | |
2776 | (((v) & ~0xffff) == 0 \ | |
2777 | ? ((v) & ~0xff) == 0 \ | |
2778 | ? ((v) & ~0xf) == 0 \ | |
2779 | ? ((v) & ~0x3) == 0 \ | |
2780 | ? ((v) & ~0x1) == 0 \ | |
2781 | ? !(v) \ | |
2782 | ? 32 \ | |
2783 | : 31 \ | |
2784 | : 30 \ | |
2785 | : ((v) & ~0x7) == 0 \ | |
2786 | ? 29 \ | |
2787 | : 28 \ | |
2788 | : ((v) & ~0x3f) == 0 \ | |
2789 | ? ((v) & ~0x1f) == 0 \ | |
2790 | ? 27 \ | |
2791 | : 26 \ | |
2792 | : ((v) & ~0x7f) == 0 \ | |
2793 | ? 25 \ | |
2794 | : 24 \ | |
2795 | : ((v) & ~0xfff) == 0 \ | |
2796 | ? ((v) & ~0x3ff) == 0 \ | |
2797 | ? ((v) & ~0x1ff) == 0 \ | |
2798 | ? 23 \ | |
2799 | : 22 \ | |
2800 | : ((v) & ~0x7ff) == 0 \ | |
2801 | ? 21 \ | |
2802 | : 20 \ | |
2803 | : ((v) & ~0x3fff) == 0 \ | |
2804 | ? ((v) & ~0x1fff) == 0 \ | |
2805 | ? 19 \ | |
2806 | : 18 \ | |
2807 | : ((v) & ~0x7fff) == 0 \ | |
2808 | ? 17 \ | |
2809 | : 16 \ | |
2810 | : ((v) & ~0xffffff) == 0 \ | |
2811 | ? ((v) & ~0xfffff) == 0 \ | |
2812 | ? ((v) & ~0x3ffff) == 0 \ | |
2813 | ? ((v) & ~0x1ffff) == 0 \ | |
2814 | ? 15 \ | |
2815 | : 14 \ | |
2816 | : ((v) & ~0x7ffff) == 0 \ | |
2817 | ? 13 \ | |
2818 | : 12 \ | |
2819 | : ((v) & ~0x3fffff) == 0 \ | |
2820 | ? ((v) & ~0x1fffff) == 0 \ | |
2821 | ? 11 \ | |
2822 | : 10 \ | |
2823 | : ((v) & ~0x7fffff) == 0 \ | |
2824 | ? 9 \ | |
2825 | : 8 \ | |
2826 | : ((v) & ~0xfffffff) == 0 \ | |
2827 | ? ((v) & ~0x3ffffff) == 0 \ | |
2828 | ? ((v) & ~0x1ffffff) == 0 \ | |
2829 | ? 7 \ | |
2830 | : 6 \ | |
2831 | : ((v) & ~0x7ffffff) == 0 \ | |
2832 | ? 5 \ | |
2833 | : 4 \ | |
2834 | : ((v) & ~0x3fffffff) == 0 \ | |
2835 | ? ((v) & ~0x1fffffff) == 0 \ | |
2836 | ? 3 \ | |
2837 | : 2 \ | |
2838 | : ((v) & ~0x7fffffff) == 0 \ | |
2839 | ? 1 \ | |
2840 | : 0) | |
2841 | ||
3d3c5039 ILT |
2842 | /* load_register() |
2843 | * This routine generates the least number of instructions neccessary to load | |
2844 | * an absolute expression value into a register. | |
2845 | */ | |
2846 | static void | |
d8a1c247 | 2847 | load_register (counter, reg, ep, dbl) |
670a50eb | 2848 | int *counter; |
670a50eb ILT |
2849 | int reg; |
2850 | expressionS *ep; | |
d8a1c247 | 2851 | int dbl; |
3d3c5039 | 2852 | { |
c36a90ef ILT |
2853 | int freg; |
2854 | expressionS hi32, lo32; | |
847a01cd ILT |
2855 | |
2856 | if (ep->X_op != O_big) | |
6e8dda9c | 2857 | { |
847a01cd | 2858 | assert (ep->X_op == O_constant); |
d8a1c247 KR |
2859 | if (ep->X_add_number < 0x8000 |
2860 | && (ep->X_add_number >= 0 | |
2861 | || (ep->X_add_number >= -0x8000 | |
2862 | && (! dbl | |
2863 | || ! ep->X_unsigned | |
2864 | || sizeof (ep->X_add_number) > 4)))) | |
847a01cd ILT |
2865 | { |
2866 | /* We can handle 16 bit signed values with an addiu to | |
2867 | $zero. No need to ever use daddiu here, since $zero and | |
2868 | the result are always correct in 32 bit mode. */ | |
2869 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, | |
2870 | (int) BFD_RELOC_LO16); | |
2871 | return; | |
2872 | } | |
2873 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
2874 | { | |
2875 | /* We can handle 16 bit unsigned values with an ori to | |
2876 | $zero. */ | |
2877 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0, | |
2878 | (int) BFD_RELOC_LO16); | |
2879 | return; | |
2880 | } | |
98bfd087 ILT |
2881 | else if ((((ep->X_add_number &~ (offsetT) 0x7fffffff) == 0 |
2882 | || ((ep->X_add_number &~ (offsetT) 0x7fffffff) | |
2883 | == ~ (offsetT) 0x7fffffff)) | |
2884 | && (! dbl | |
2885 | || ! ep->X_unsigned | |
2886 | || sizeof (ep->X_add_number) > 4 | |
2887 | || (ep->X_add_number & 0x80000000) == 0)) | |
3c83da8a | 2888 | || ((mips_opts.isa < 3 || ! dbl) |
f59fb6ca | 2889 | && (ep->X_add_number &~ (offsetT) 0xffffffff) == 0) |
3c83da8a | 2890 | || (mips_opts.isa < 3 |
f59fb6ca ILT |
2891 | && ! dbl |
2892 | && ((ep->X_add_number &~ (offsetT) 0xffffffff) | |
2893 | == ~ (offsetT) 0xffffffff))) | |
847a01cd ILT |
2894 | { |
2895 | /* 32 bit values require an lui. */ | |
2896 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
2897 | (int) BFD_RELOC_HI16); | |
2898 | if ((ep->X_add_number & 0xffff) != 0) | |
2899 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg, | |
2900 | (int) BFD_RELOC_LO16); | |
2901 | return; | |
2902 | } | |
6e8dda9c | 2903 | } |
847a01cd ILT |
2904 | |
2905 | /* The value is larger than 32 bits. */ | |
2906 | ||
3c83da8a | 2907 | if (mips_opts.isa < 3) |
670a50eb | 2908 | { |
6e8dda9c | 2909 | as_bad ("Number larger than 32 bits"); |
0dd2d296 | 2910 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, |
9226253a | 2911 | (int) BFD_RELOC_LO16); |
847a01cd | 2912 | return; |
6e8dda9c | 2913 | } |
6e8dda9c | 2914 | |
847a01cd ILT |
2915 | if (ep->X_op != O_big) |
2916 | { | |
6e8dda9c | 2917 | hi32 = *ep; |
c36a90ef ILT |
2918 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; |
2919 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
6e8dda9c | 2920 | hi32.X_add_number &= 0xffffffff; |
6e8dda9c ILT |
2921 | lo32 = *ep; |
2922 | lo32.X_add_number &= 0xffffffff; | |
670a50eb | 2923 | } |
847a01cd ILT |
2924 | else |
2925 | { | |
2926 | assert (ep->X_add_number > 2); | |
2927 | if (ep->X_add_number == 3) | |
2928 | generic_bignum[3] = 0; | |
2929 | else if (ep->X_add_number > 4) | |
2930 | as_bad ("Number larger than 64 bits"); | |
2931 | lo32.X_op = O_constant; | |
2932 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
2933 | hi32.X_op = O_constant; | |
2934 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
2935 | } | |
2936 | ||
d8a1c247 KR |
2937 | if (hi32.X_add_number == 0) |
2938 | freg = 0; | |
2939 | else | |
2940 | { | |
c36a90ef ILT |
2941 | int shift, bit; |
2942 | unsigned long hi, lo; | |
2943 | ||
fb251650 ILT |
2944 | if (hi32.X_add_number == 0xffffffff) |
2945 | { | |
2946 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
2947 | { | |
c36a90ef ILT |
2948 | macro_build ((char *) NULL, counter, &lo32, "addiu", "t,r,j", |
2949 | reg, 0, (int) BFD_RELOC_LO16); | |
fb251650 ILT |
2950 | return; |
2951 | } | |
2952 | if (lo32.X_add_number & 0x80000000) | |
2953 | { | |
2954 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
2955 | (int) BFD_RELOC_HI16); | |
c36a90ef ILT |
2956 | if (lo32.X_add_number & 0xffff) |
2957 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", | |
2958 | reg, reg, (int) BFD_RELOC_LO16); | |
fb251650 ILT |
2959 | return; |
2960 | } | |
2961 | } | |
ff8716f5 | 2962 | |
c36a90ef ILT |
2963 | /* Check for 16bit shifted constant. We know that hi32 is |
2964 | non-zero, so start the mask on the first bit of the hi32 | |
2965 | value. */ | |
ff8716f5 JSC |
2966 | shift = 17; |
2967 | do | |
2968 | { | |
c36a90ef ILT |
2969 | unsigned long himask, lomask; |
2970 | ||
2971 | if (shift < 32) | |
2972 | { | |
2973 | himask = 0xffff >> (32 - shift); | |
2974 | lomask = (0xffff << shift) & 0xffffffff; | |
2975 | } | |
2976 | else | |
2977 | { | |
2978 | himask = 0xffff << (shift - 32); | |
2979 | lomask = 0; | |
2980 | } | |
2981 | if ((hi32.X_add_number & ~ (offsetT) himask) == 0 | |
2982 | && (lo32.X_add_number & ~ (offsetT) lomask) == 0) | |
2983 | { | |
2984 | expressionS tmp; | |
2985 | ||
2986 | tmp.X_op = O_constant; | |
2987 | if (shift < 32) | |
2988 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
2989 | | (lo32.X_add_number >> shift)); | |
2990 | else | |
2991 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
2992 | macro_build ((char *) NULL, counter, &tmp, "ori", "t,r,i", reg, 0, | |
2993 | (int) BFD_RELOC_LO16); | |
2994 | macro_build ((char *) NULL, counter, NULL, | |
2995 | (shift >= 32) ? "dsll32" : "dsll", | |
2996 | "d,w,<", reg, reg, | |
2997 | (shift >= 32) ? shift - 32 : shift); | |
2998 | return; | |
2999 | } | |
ff8716f5 JSC |
3000 | shift++; |
3001 | } while (shift <= (64 - 16)); | |
3002 | ||
c36a90ef ILT |
3003 | /* Find the bit number of the lowest one bit, and store the |
3004 | shifted value in hi/lo. */ | |
3005 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
3006 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
3007 | if (lo != 0) | |
3008 | { | |
3009 | bit = 0; | |
3010 | while ((lo & 1) == 0) | |
3011 | { | |
3012 | lo >>= 1; | |
3013 | ++bit; | |
3014 | } | |
3015 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
3016 | hi >>= bit; | |
3017 | } | |
3018 | else | |
3019 | { | |
3020 | bit = 32; | |
3021 | while ((hi & 1) == 0) | |
3022 | { | |
3023 | hi >>= 1; | |
3024 | ++bit; | |
3025 | } | |
3026 | lo = hi; | |
3027 | hi = 0; | |
3028 | } | |
3029 | ||
3030 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
3031 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
3032 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
ff8716f5 | 3033 | { |
c36a90ef | 3034 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); |
ff8716f5 JSC |
3035 | if (shift != 0) |
3036 | { | |
c36a90ef ILT |
3037 | expressionS tmp; |
3038 | ||
3039 | /* This instruction will set the register to be all | |
3040 | ones. */ | |
ff8716f5 | 3041 | tmp.X_op = O_constant; |
c36a90ef ILT |
3042 | tmp.X_add_number = (offsetT) -1; |
3043 | macro_build ((char *) NULL, counter, &tmp, "addiu", "t,r,j", | |
3044 | reg, 0, (int) BFD_RELOC_LO16); | |
3045 | if (bit != 0) | |
ff8716f5 | 3046 | { |
c36a90ef | 3047 | bit += shift; |
ff8716f5 | 3048 | macro_build ((char *) NULL, counter, NULL, |
c36a90ef | 3049 | (bit >= 32) ? "dsll32" : "dsll", |
ff8716f5 | 3050 | "d,w,<", reg, reg, |
c36a90ef | 3051 | (bit >= 32) ? bit - 32 : bit); |
ff8716f5 | 3052 | } |
c36a90ef ILT |
3053 | macro_build ((char *) NULL, counter, NULL, |
3054 | (shift >= 32) ? "dsrl32" : "dsrl", | |
3055 | "d,w,<", reg, reg, | |
3056 | (shift >= 32) ? shift - 32 : shift); | |
ff8716f5 JSC |
3057 | return; |
3058 | } | |
3059 | } | |
c36a90ef ILT |
3060 | |
3061 | /* Sign extend hi32 before calling load_register, because we can | |
3062 | generally get better code when we load a sign extended value. */ | |
3063 | if ((hi32.X_add_number & 0x80000000) != 0) | |
3064 | hi32.X_add_number |= ~ (offsetT) 0xffffffff; | |
d8a1c247 KR |
3065 | load_register (counter, reg, &hi32, 0); |
3066 | freg = reg; | |
3067 | } | |
847a01cd | 3068 | if ((lo32.X_add_number & 0xffff0000) == 0) |
d8a1c247 KR |
3069 | { |
3070 | if (freg != 0) | |
3071 | { | |
3072 | macro_build ((char *) NULL, counter, NULL, "dsll32", "d,w,<", reg, | |
3073 | freg, 0); | |
3074 | freg = reg; | |
3075 | } | |
3076 | } | |
847a01cd ILT |
3077 | else |
3078 | { | |
3079 | expressionS mid16; | |
3080 | ||
fb251650 ILT |
3081 | if ((freg == 0) && (lo32.X_add_number == 0xffffffff)) |
3082 | { | |
3083 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
3084 | (int) BFD_RELOC_HI16); | |
3085 | macro_build ((char *) NULL, counter, NULL, "dsrl32", "d,w,<", reg, | |
ff8716f5 | 3086 | reg, 0); |
fb251650 ILT |
3087 | return; |
3088 | } | |
3089 | ||
d8a1c247 KR |
3090 | if (freg != 0) |
3091 | { | |
3092 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, | |
3093 | freg, 16); | |
3094 | freg = reg; | |
3095 | } | |
847a01cd ILT |
3096 | mid16 = lo32; |
3097 | mid16.X_add_number >>= 16; | |
3098 | macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg, | |
d8a1c247 | 3099 | freg, (int) BFD_RELOC_LO16); |
847a01cd ILT |
3100 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, |
3101 | reg, 16); | |
d8a1c247 | 3102 | freg = reg; |
847a01cd ILT |
3103 | } |
3104 | if ((lo32.X_add_number & 0xffff) != 0) | |
d8a1c247 | 3105 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, freg, |
847a01cd | 3106 | (int) BFD_RELOC_LO16); |
3d3c5039 ILT |
3107 | } |
3108 | ||
0dd2d296 ILT |
3109 | /* Load an address into a register. */ |
3110 | ||
3111 | static void | |
3112 | load_address (counter, reg, ep) | |
3113 | int *counter; | |
3114 | int reg; | |
3115 | expressionS *ep; | |
3116 | { | |
3117 | char *p; | |
3118 | ||
3119 | if (ep->X_op != O_constant | |
3120 | && ep->X_op != O_symbol) | |
3121 | { | |
3122 | as_bad ("expression too complex"); | |
3123 | ep->X_op = O_constant; | |
3124 | } | |
3125 | ||
3126 | if (ep->X_op == O_constant) | |
d9aba805 | 3127 | { |
d8a1c247 | 3128 | load_register (counter, reg, ep, 0); |
d9aba805 ILT |
3129 | return; |
3130 | } | |
3131 | ||
3132 | if (mips_pic == NO_PIC) | |
0dd2d296 ILT |
3133 | { |
3134 | /* If this is a reference to a GP relative symbol, we want | |
3135 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
3136 | Otherwise we want | |
04cb3372 | 3137 | lui $reg,<sym> (BFD_RELOC_HI16_S) |
0dd2d296 ILT |
3138 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) |
3139 | If we have an addend, we always use the latter form. */ | |
7a15a226 | 3140 | if ((valueT) ep->X_add_number >= MAX_GPREL_OFFSET |
85ce5635 | 3141 | || nopic_need_relax (ep->X_add_symbol, 1)) |
0dd2d296 ILT |
3142 | p = NULL; |
3143 | else | |
3144 | { | |
8ea7f4e8 | 3145 | frag_grow (20); |
0dd2d296 | 3146 | macro_build ((char *) NULL, counter, ep, |
3c83da8a | 3147 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
0dd2d296 ILT |
3148 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); |
3149 | p = frag_var (rs_machine_dependent, 8, 0, | |
3c83da8a JW |
3150 | RELAX_ENCODE (4, 8, 0, 4, 0, |
3151 | mips_opts.warn_about_macros), | |
f59fb6ca | 3152 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); |
0dd2d296 ILT |
3153 | } |
3154 | macro_build_lui (p, counter, ep, reg); | |
3155 | if (p != NULL) | |
3156 | p += 4; | |
3157 | macro_build (p, counter, ep, | |
3c83da8a | 3158 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
0dd2d296 ILT |
3159 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3160 | } | |
fb251650 | 3161 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
0dd2d296 ILT |
3162 | { |
3163 | expressionS ex; | |
3164 | ||
3165 | /* If this is a reference to an external symbol, we want | |
3166 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3167 | Otherwise we want | |
3168 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3169 | nop | |
3170 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d9aba805 | 3171 | If there is a constant, it must be added in after. */ |
0dd2d296 ILT |
3172 | ex.X_add_number = ep->X_add_number; |
3173 | ep->X_add_number = 0; | |
8ea7f4e8 | 3174 | frag_grow (20); |
0dd2d296 | 3175 | macro_build ((char *) NULL, counter, ep, |
3c83da8a | 3176 | mips_opts.isa < 3 ? "lw" : "ld", |
0dd2d296 ILT |
3177 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); |
3178 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", ""); | |
3179 | p = frag_var (rs_machine_dependent, 4, 0, | |
3c83da8a | 3180 | RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts.warn_about_macros), |
f59fb6ca | 3181 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); |
0dd2d296 | 3182 | macro_build (p, counter, ep, |
3c83da8a | 3183 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
0dd2d296 ILT |
3184 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3185 | if (ex.X_add_number != 0) | |
3186 | { | |
3187 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3188 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
3189 | ex.X_op = O_constant; | |
fb251650 | 3190 | macro_build ((char *) NULL, counter, &ex, |
3c83da8a | 3191 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
fb251650 ILT |
3192 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3193 | } | |
3194 | } | |
3195 | else if (mips_pic == SVR4_PIC) | |
3196 | { | |
3197 | expressionS ex; | |
3198 | int off; | |
3199 | ||
3200 | /* This is the large GOT case. If this is a reference to an | |
3201 | external symbol, we want | |
3202 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3203 | addu $reg,$reg,$gp | |
3204 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
3205 | Otherwise, for a reference to a local symbol, we want | |
3206 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3207 | nop | |
3208 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
3209 | If there is a constant, it must be added in after. */ | |
3210 | ex.X_add_number = ep->X_add_number; | |
3211 | ep->X_add_number = 0; | |
3212 | if (reg_needs_delay (GP)) | |
3213 | off = 4; | |
3214 | else | |
3215 | off = 0; | |
3216 | frag_grow (32); | |
3217 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
3218 | (int) BFD_RELOC_MIPS_GOT_HI16); | |
3219 | macro_build ((char *) NULL, counter, (expressionS *) NULL, | |
3c83da8a | 3220 | mips_opts.isa < 3 ? "addu" : "daddu", |
fb251650 ILT |
3221 | "d,v,t", reg, reg, GP); |
3222 | macro_build ((char *) NULL, counter, ep, | |
3c83da8a | 3223 | mips_opts.isa < 3 ? "lw" : "ld", |
fb251650 ILT |
3224 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg); |
3225 | p = frag_var (rs_machine_dependent, 12 + off, 0, | |
3226 | RELAX_ENCODE (12, 12 + off, off, 8 + off, 0, | |
3c83da8a | 3227 | mips_opts.warn_about_macros), |
f59fb6ca | 3228 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); |
fb251650 ILT |
3229 | if (off > 0) |
3230 | { | |
3231 | /* We need a nop before loading from $gp. This special | |
3232 | check is required because the lui which starts the main | |
3233 | instruction stream does not refer to $gp, and so will not | |
3234 | insert the nop which may be required. */ | |
3235 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
3236 | p += 4; | |
3237 | } | |
3238 | macro_build (p, counter, ep, | |
3c83da8a | 3239 | mips_opts.isa < 3 ? "lw" : "ld", |
fb251650 ILT |
3240 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); |
3241 | p += 4; | |
3242 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
3243 | p += 4; | |
3244 | macro_build (p, counter, ep, | |
3c83da8a | 3245 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
fb251650 ILT |
3246 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3247 | if (ex.X_add_number != 0) | |
3248 | { | |
3249 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3250 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
3251 | ex.X_op = O_constant; | |
3252 | macro_build ((char *) NULL, counter, &ex, | |
3c83da8a | 3253 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
0dd2d296 ILT |
3254 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
3255 | } | |
d9aba805 ILT |
3256 | } |
3257 | else if (mips_pic == EMBEDDED_PIC) | |
3258 | { | |
3259 | /* We always do | |
3260 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
3261 | */ | |
3262 | macro_build ((char *) NULL, counter, ep, | |
3c83da8a | 3263 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
d9aba805 ILT |
3264 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); |
3265 | } | |
3266 | else | |
3267 | abort (); | |
0dd2d296 ILT |
3268 | } |
3269 | ||
3d3c5039 ILT |
3270 | /* |
3271 | * Build macros | |
3272 | * This routine implements the seemingly endless macro or synthesized | |
3273 | * instructions and addressing modes in the mips assembly language. Many | |
3274 | * of these macros are simple and are similar to each other. These could | |
3275 | * probably be handled by some kind of table or grammer aproach instead of | |
3276 | * this verbose method. Others are not simple macros but are more like | |
3277 | * optimizing code generation. | |
3278 | * One interesting optimization is when several store macros appear | |
3279 | * consecutivly that would load AT with the upper half of the same address. | |
3280 | * The ensuing load upper instructions are ommited. This implies some kind | |
3281 | * of global optimization. We currently only optimize within a single macro. | |
3282 | * For many of the load and store macros if the address is specified as a | |
3283 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
3284 | * first load register 'at' with zero and use it as the base register. The | |
3285 | * mips assembler simply uses register $zero. Just one tiny optimization | |
3286 | * we're missing. | |
3287 | */ | |
3288 | static void | |
3289 | macro (ip) | |
3290 | struct mips_cl_insn *ip; | |
3291 | { | |
670a50eb ILT |
3292 | register int treg, sreg, dreg, breg; |
3293 | int tempreg; | |
3294 | int mask; | |
3295 | int icnt = 0; | |
3296 | int used_at; | |
670a50eb ILT |
3297 | expressionS expr1; |
3298 | const char *s; | |
8358c818 | 3299 | const char *s2; |
670a50eb | 3300 | const char *fmt; |
8358c818 ILT |
3301 | int likely = 0; |
3302 | int dbl = 0; | |
3303 | int coproc = 0; | |
b2b8c24e | 3304 | int lr = 0; |
6e8dda9c | 3305 | offsetT maxnum; |
adcf2b9d | 3306 | int off; |
9226253a | 3307 | bfd_reloc_code_real_type r; |
0dd2d296 | 3308 | char *p; |
55933a58 | 3309 | int hold_mips_optimize; |
670a50eb | 3310 | |
3c83da8a | 3311 | assert (! mips_opts.mips16); |
cc5703cd | 3312 | |
670a50eb ILT |
3313 | treg = (ip->insn_opcode >> 16) & 0x1f; |
3314 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
3315 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
3316 | mask = ip->insn_mo->mask; | |
3317 | ||
5ac34ac3 ILT |
3318 | expr1.X_op = O_constant; |
3319 | expr1.X_op_symbol = NULL; | |
670a50eb ILT |
3320 | expr1.X_add_symbol = NULL; |
3321 | expr1.X_add_number = 1; | |
3322 | ||
3323 | switch (mask) | |
3324 | { | |
6e8dda9c ILT |
3325 | case M_DABS: |
3326 | dbl = 1; | |
3d3c5039 | 3327 | case M_ABS: |
6e8dda9c ILT |
3328 | /* bgez $a0,.+12 |
3329 | move v0,$a0 | |
3330 | sub v0,$zero,$a0 | |
3331 | */ | |
3d3c5039 | 3332 | |
fbcfacb7 | 3333 | mips_emit_delays (true); |
3c83da8a | 3334 | ++mips_opts.noreorder; |
0dd2d296 | 3335 | mips_any_noreorder = 1; |
3d3c5039 | 3336 | |
670a50eb | 3337 | expr1.X_add_number = 8; |
0dd2d296 | 3338 | macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg); |
6e8dda9c | 3339 | if (dreg == sreg) |
0dd2d296 | 3340 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); |
6e8dda9c | 3341 | else |
0dd2d296 ILT |
3342 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, sreg, 0); |
3343 | macro_build ((char *) NULL, &icnt, NULL, | |
6e8dda9c ILT |
3344 | dbl ? "dsub" : "sub", |
3345 | "d,v,t", dreg, 0, sreg); | |
3d3c5039 | 3346 | |
3c83da8a | 3347 | --mips_opts.noreorder; |
670a50eb | 3348 | return; |
3d3c5039 ILT |
3349 | |
3350 | case M_ADD_I: | |
8358c818 ILT |
3351 | s = "addi"; |
3352 | s2 = "add"; | |
3353 | goto do_addi; | |
3d3c5039 | 3354 | case M_ADDU_I: |
8358c818 ILT |
3355 | s = "addiu"; |
3356 | s2 = "addu"; | |
3357 | goto do_addi; | |
3358 | case M_DADD_I: | |
6e8dda9c | 3359 | dbl = 1; |
8358c818 ILT |
3360 | s = "daddi"; |
3361 | s2 = "dadd"; | |
3362 | goto do_addi; | |
3363 | case M_DADDU_I: | |
6e8dda9c | 3364 | dbl = 1; |
8358c818 ILT |
3365 | s = "daddiu"; |
3366 | s2 = "daddu"; | |
3367 | do_addi: | |
5c6f5923 GRK |
3368 | if (imm_expr.X_op == O_constant |
3369 | && imm_expr.X_add_number >= -0x8000 | |
3370 | && imm_expr.X_add_number < 0x8000) | |
670a50eb | 3371 | { |
0dd2d296 | 3372 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg, |
9226253a | 3373 | (int) BFD_RELOC_LO16); |
670a50eb | 3374 | return; |
3d3c5039 | 3375 | } |
d8a1c247 | 3376 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 3377 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
670a50eb | 3378 | break; |
3d3c5039 ILT |
3379 | |
3380 | case M_AND_I: | |
6e8dda9c ILT |
3381 | s = "andi"; |
3382 | s2 = "and"; | |
3383 | goto do_bit; | |
3d3c5039 | 3384 | case M_OR_I: |
6e8dda9c ILT |
3385 | s = "ori"; |
3386 | s2 = "or"; | |
3387 | goto do_bit; | |
3d3c5039 | 3388 | case M_NOR_I: |
6e8dda9c ILT |
3389 | s = ""; |
3390 | s2 = "nor"; | |
3391 | goto do_bit; | |
3d3c5039 | 3392 | case M_XOR_I: |
6e8dda9c ILT |
3393 | s = "xori"; |
3394 | s2 = "xor"; | |
3395 | do_bit: | |
5c6f5923 GRK |
3396 | if (imm_expr.X_op == O_constant |
3397 | && imm_expr.X_add_number >= 0 | |
3398 | && imm_expr.X_add_number < 0x10000) | |
670a50eb | 3399 | { |
6e8dda9c | 3400 | if (mask != M_NOR_I) |
0dd2d296 ILT |
3401 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg, |
3402 | sreg, (int) BFD_RELOC_LO16); | |
6e8dda9c | 3403 | else |
670a50eb | 3404 | { |
0dd2d296 ILT |
3405 | macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i", |
3406 | treg, sreg, (int) BFD_RELOC_LO16); | |
1c803e52 | 3407 | macro_build ((char *) NULL, &icnt, NULL, "nor", "d,v,t", |
0dd2d296 | 3408 | treg, treg, 0); |
3d3c5039 | 3409 | } |
6e8dda9c | 3410 | return; |
3d3c5039 | 3411 | } |
6e8dda9c | 3412 | |
d8a1c247 | 3413 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 3414 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
670a50eb | 3415 | break; |
3d3c5039 ILT |
3416 | |
3417 | case M_BEQ_I: | |
8358c818 ILT |
3418 | s = "beq"; |
3419 | goto beq_i; | |
3420 | case M_BEQL_I: | |
3421 | s = "beql"; | |
3422 | likely = 1; | |
3423 | goto beq_i; | |
3d3c5039 | 3424 | case M_BNE_I: |
8358c818 ILT |
3425 | s = "bne"; |
3426 | goto beq_i; | |
3427 | case M_BNEL_I: | |
3428 | s = "bnel"; | |
3429 | likely = 1; | |
3430 | beq_i: | |
5c6f5923 | 3431 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
670a50eb | 3432 | { |
0dd2d296 ILT |
3433 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, |
3434 | 0); | |
670a50eb ILT |
3435 | return; |
3436 | } | |
d8a1c247 | 3437 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 3438 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT); |
670a50eb | 3439 | break; |
3d3c5039 | 3440 | |
8358c818 ILT |
3441 | case M_BGEL: |
3442 | likely = 1; | |
3d3c5039 | 3443 | case M_BGE: |
670a50eb ILT |
3444 | if (treg == 0) |
3445 | { | |
0dd2d296 | 3446 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3447 | likely ? "bgezl" : "bgez", |
3448 | "s,p", sreg); | |
670a50eb | 3449 | return; |
3d3c5039 | 3450 | } |
9a7d824a ILT |
3451 | if (sreg == 0) |
3452 | { | |
0dd2d296 | 3453 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3454 | likely ? "blezl" : "blez", |
3455 | "s,p", treg); | |
9a7d824a ILT |
3456 | return; |
3457 | } | |
0dd2d296 ILT |
3458 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); |
3459 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3460 | likely ? "beql" : "beq", |
3461 | "s,t,p", AT, 0); | |
670a50eb | 3462 | break; |
3d3c5039 | 3463 | |
8358c818 ILT |
3464 | case M_BGTL_I: |
3465 | likely = 1; | |
3d3c5039 | 3466 | case M_BGT_I: |
9a7d824a | 3467 | /* check for > max integer */ |
6e8dda9c | 3468 | maxnum = 0x7fffffff; |
5c6f5923 | 3469 | if (mips_opts.isa >= 3 && sizeof (maxnum) > 4) |
6e8dda9c ILT |
3470 | { |
3471 | maxnum <<= 16; | |
3472 | maxnum |= 0xffff; | |
3473 | maxnum <<= 16; | |
3474 | maxnum |= 0xffff; | |
3475 | } | |
5c6f5923 GRK |
3476 | if (imm_expr.X_op == O_constant |
3477 | && imm_expr.X_add_number >= maxnum | |
3c83da8a | 3478 | && (mips_opts.isa < 3 || sizeof (maxnum) > 4)) |
9a7d824a ILT |
3479 | { |
3480 | do_false: | |
3481 | /* result is always false */ | |
8358c818 ILT |
3482 | if (! likely) |
3483 | { | |
3484 | as_warn ("Branch %s is always false (nop)", ip->insn_mo->name); | |
0dd2d296 | 3485 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); |
8358c818 ILT |
3486 | } |
3487 | else | |
3488 | { | |
3489 | as_warn ("Branch likely %s is always false", ip->insn_mo->name); | |
0dd2d296 ILT |
3490 | macro_build ((char *) NULL, &icnt, &offset_expr, "bnel", |
3491 | "s,t,p", 0, 0); | |
8358c818 | 3492 | } |
9a7d824a ILT |
3493 | return; |
3494 | } | |
5c6f5923 GRK |
3495 | if (imm_expr.X_op != O_constant) |
3496 | as_bad ("Unsupported large constant"); | |
670a50eb ILT |
3497 | imm_expr.X_add_number++; |
3498 | /* FALLTHROUGH */ | |
3d3c5039 | 3499 | case M_BGE_I: |
8358c818 ILT |
3500 | case M_BGEL_I: |
3501 | if (mask == M_BGEL_I) | |
3502 | likely = 1; | |
5c6f5923 | 3503 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
670a50eb | 3504 | { |
0dd2d296 | 3505 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3506 | likely ? "bgezl" : "bgez", |
3507 | "s,p", sreg); | |
670a50eb | 3508 | return; |
3d3c5039 | 3509 | } |
5c6f5923 | 3510 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
670a50eb | 3511 | { |
0dd2d296 | 3512 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3513 | likely ? "bgtzl" : "bgtz", |
3514 | "s,p", sreg); | |
670a50eb | 3515 | return; |
3d3c5039 | 3516 | } |
6e8dda9c | 3517 | maxnum = 0x7fffffff; |
5c6f5923 | 3518 | if (mips_opts.isa >= 3 && sizeof (maxnum) > 4) |
6e8dda9c ILT |
3519 | { |
3520 | maxnum <<= 16; | |
3521 | maxnum |= 0xffff; | |
3522 | maxnum <<= 16; | |
3523 | maxnum |= 0xffff; | |
3524 | } | |
3525 | maxnum = - maxnum - 1; | |
5c6f5923 GRK |
3526 | if (imm_expr.X_op == O_constant |
3527 | && imm_expr.X_add_number <= maxnum | |
3c83da8a | 3528 | && (mips_opts.isa < 3 || sizeof (maxnum) > 4)) |
9a7d824a ILT |
3529 | { |
3530 | do_true: | |
3531 | /* result is always true */ | |
3532 | as_warn ("Branch %s is always true", ip->insn_mo->name); | |
0dd2d296 | 3533 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); |
9a7d824a ILT |
3534 | return; |
3535 | } | |
6e8dda9c | 3536 | set_at (&icnt, sreg, 0); |
0dd2d296 | 3537 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3538 | likely ? "beql" : "beq", |
3539 | "s,t,p", AT, 0); | |
670a50eb | 3540 | break; |
3d3c5039 | 3541 | |
8358c818 ILT |
3542 | case M_BGEUL: |
3543 | likely = 1; | |
3d3c5039 | 3544 | case M_BGEU: |
670a50eb | 3545 | if (treg == 0) |
9a7d824a ILT |
3546 | goto do_true; |
3547 | if (sreg == 0) | |
670a50eb | 3548 | { |
0dd2d296 | 3549 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3550 | likely ? "beql" : "beq", |
3551 | "s,t,p", 0, treg); | |
670a50eb | 3552 | return; |
3d3c5039 | 3553 | } |
0dd2d296 ILT |
3554 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, |
3555 | treg); | |
3556 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3557 | likely ? "beql" : "beq", |
3558 | "s,t,p", AT, 0); | |
670a50eb | 3559 | break; |
3d3c5039 | 3560 | |
8358c818 ILT |
3561 | case M_BGTUL_I: |
3562 | likely = 1; | |
9a7d824a | 3563 | case M_BGTU_I: |
5c6f5923 GRK |
3564 | if (sreg == 0 |
3565 | || (mips_opts.isa < 3 | |
3566 | && imm_expr.X_op == O_constant | |
3567 | && imm_expr.X_add_number == 0xffffffff)) | |
9a7d824a | 3568 | goto do_false; |
5c6f5923 GRK |
3569 | if (imm_expr.X_op != O_constant) |
3570 | as_bad ("Unsupported large constant"); | |
9a7d824a ILT |
3571 | imm_expr.X_add_number++; |
3572 | /* FALLTHROUGH */ | |
3d3c5039 | 3573 | case M_BGEU_I: |
8358c818 ILT |
3574 | case M_BGEUL_I: |
3575 | if (mask == M_BGEUL_I) | |
3576 | likely = 1; | |
5c6f5923 | 3577 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
9a7d824a | 3578 | goto do_true; |
5c6f5923 | 3579 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
670a50eb | 3580 | { |
0dd2d296 | 3581 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3582 | likely ? "bnel" : "bne", |
3583 | "s,t,p", sreg, 0); | |
670a50eb | 3584 | return; |
3d3c5039 | 3585 | } |
6e8dda9c | 3586 | set_at (&icnt, sreg, 1); |
0dd2d296 | 3587 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3588 | likely ? "beql" : "beq", |
3589 | "s,t,p", AT, 0); | |
670a50eb | 3590 | break; |
3d3c5039 | 3591 | |
8358c818 ILT |
3592 | case M_BGTL: |
3593 | likely = 1; | |
3d3c5039 | 3594 | case M_BGT: |
670a50eb ILT |
3595 | if (treg == 0) |
3596 | { | |
0dd2d296 | 3597 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3598 | likely ? "bgtzl" : "bgtz", |
3599 | "s,p", sreg); | |
670a50eb | 3600 | return; |
3d3c5039 | 3601 | } |
9a7d824a ILT |
3602 | if (sreg == 0) |
3603 | { | |
0dd2d296 | 3604 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3605 | likely ? "bltzl" : "bltz", |
3606 | "s,p", treg); | |
9a7d824a ILT |
3607 | return; |
3608 | } | |
0dd2d296 ILT |
3609 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); |
3610 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3611 | likely ? "bnel" : "bne", |
3612 | "s,t,p", AT, 0); | |
670a50eb | 3613 | break; |
3d3c5039 | 3614 | |
8358c818 ILT |
3615 | case M_BGTUL: |
3616 | likely = 1; | |
3d3c5039 | 3617 | case M_BGTU: |
670a50eb ILT |
3618 | if (treg == 0) |
3619 | { | |
0dd2d296 | 3620 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3621 | likely ? "bnel" : "bne", |
3622 | "s,t,p", sreg, 0); | |
670a50eb | 3623 | return; |
3d3c5039 | 3624 | } |
9a7d824a ILT |
3625 | if (sreg == 0) |
3626 | goto do_false; | |
0dd2d296 ILT |
3627 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, |
3628 | sreg); | |
3629 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3630 | likely ? "bnel" : "bne", |
3631 | "s,t,p", AT, 0); | |
670a50eb | 3632 | break; |
3d3c5039 | 3633 | |
8358c818 ILT |
3634 | case M_BLEL: |
3635 | likely = 1; | |
3d3c5039 | 3636 | case M_BLE: |
670a50eb ILT |
3637 | if (treg == 0) |
3638 | { | |
0dd2d296 | 3639 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3640 | likely ? "blezl" : "blez", |
3641 | "s,p", sreg); | |
670a50eb ILT |
3642 | return; |
3643 | } | |
9a7d824a ILT |
3644 | if (sreg == 0) |
3645 | { | |
0dd2d296 | 3646 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3647 | likely ? "bgezl" : "bgez", |
3648 | "s,p", treg); | |
9a7d824a ILT |
3649 | return; |
3650 | } | |
0dd2d296 ILT |
3651 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); |
3652 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3653 | likely ? "beql" : "beq", |
3654 | "s,t,p", AT, 0); | |
670a50eb | 3655 | break; |
3d3c5039 | 3656 | |
8358c818 ILT |
3657 | case M_BLEL_I: |
3658 | likely = 1; | |
3d3c5039 | 3659 | case M_BLE_I: |
6e8dda9c | 3660 | maxnum = 0x7fffffff; |
5c6f5923 | 3661 | if (mips_opts.isa >= 3 && sizeof (maxnum) > 4) |
6e8dda9c ILT |
3662 | { |
3663 | maxnum <<= 16; | |
3664 | maxnum |= 0xffff; | |
3665 | maxnum <<= 16; | |
3666 | maxnum |= 0xffff; | |
3667 | } | |
5c6f5923 GRK |
3668 | if (imm_expr.X_op == O_constant |
3669 | && imm_expr.X_add_number >= maxnum | |
3c83da8a | 3670 | && (mips_opts.isa < 3 || sizeof (maxnum) > 4)) |
9a7d824a | 3671 | goto do_true; |
5c6f5923 GRK |
3672 | if (imm_expr.X_op != O_constant) |
3673 | as_bad ("Unsupported large constant"); | |
9a7d824a ILT |
3674 | imm_expr.X_add_number++; |
3675 | /* FALLTHROUGH */ | |
9a7d824a | 3676 | case M_BLT_I: |
8358c818 ILT |
3677 | case M_BLTL_I: |
3678 | if (mask == M_BLTL_I) | |
3679 | likely = 1; | |
5c6f5923 | 3680 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
670a50eb | 3681 | { |
0dd2d296 | 3682 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3683 | likely ? "bltzl" : "bltz", |
3684 | "s,p", sreg); | |
670a50eb ILT |
3685 | return; |
3686 | } | |
5c6f5923 | 3687 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
670a50eb | 3688 | { |
0dd2d296 | 3689 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3690 | likely ? "blezl" : "blez", |
3691 | "s,p", sreg); | |
670a50eb ILT |
3692 | return; |
3693 | } | |
6e8dda9c | 3694 | set_at (&icnt, sreg, 0); |
0dd2d296 | 3695 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3696 | likely ? "bnel" : "bne", |
3697 | "s,t,p", AT, 0); | |
670a50eb | 3698 | break; |
3d3c5039 | 3699 | |
8358c818 ILT |
3700 | case M_BLEUL: |
3701 | likely = 1; | |
3d3c5039 | 3702 | case M_BLEU: |
670a50eb ILT |
3703 | if (treg == 0) |
3704 | { | |
0dd2d296 | 3705 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3706 | likely ? "beql" : "beq", |
3707 | "s,t,p", sreg, 0); | |
670a50eb | 3708 | return; |
3d3c5039 | 3709 | } |
9a7d824a ILT |
3710 | if (sreg == 0) |
3711 | goto do_true; | |
0dd2d296 ILT |
3712 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, |
3713 | sreg); | |
3714 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3715 | likely ? "beql" : "beq", |
3716 | "s,t,p", AT, 0); | |
670a50eb | 3717 | break; |
3d3c5039 | 3718 | |
8358c818 ILT |
3719 | case M_BLEUL_I: |
3720 | likely = 1; | |
3d3c5039 | 3721 | case M_BLEU_I: |
5c6f5923 GRK |
3722 | if (sreg == 0 |
3723 | || (mips_opts.isa < 3 | |
3724 | && imm_expr.X_op == O_constant | |
3725 | && imm_expr.X_add_number == 0xffffffff)) | |
9a7d824a | 3726 | goto do_true; |
5c6f5923 GRK |
3727 | if (imm_expr.X_op != O_constant) |
3728 | as_bad ("Unsupported large constant"); | |
9a7d824a ILT |
3729 | imm_expr.X_add_number++; |
3730 | /* FALLTHROUGH */ | |
9a7d824a | 3731 | case M_BLTU_I: |
8358c818 ILT |
3732 | case M_BLTUL_I: |
3733 | if (mask == M_BLTUL_I) | |
3734 | likely = 1; | |
5c6f5923 | 3735 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
9a7d824a | 3736 | goto do_false; |
5c6f5923 | 3737 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
670a50eb | 3738 | { |
0dd2d296 | 3739 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3740 | likely ? "beql" : "beq", |
3741 | "s,t,p", sreg, 0); | |
670a50eb | 3742 | return; |
3d3c5039 | 3743 | } |
6e8dda9c | 3744 | set_at (&icnt, sreg, 1); |
0dd2d296 | 3745 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3746 | likely ? "bnel" : "bne", |
3747 | "s,t,p", AT, 0); | |
670a50eb | 3748 | break; |
3d3c5039 | 3749 | |
8358c818 ILT |
3750 | case M_BLTL: |
3751 | likely = 1; | |
3d3c5039 | 3752 | case M_BLT: |
670a50eb ILT |
3753 | if (treg == 0) |
3754 | { | |
0dd2d296 | 3755 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3756 | likely ? "bltzl" : "bltz", |
3757 | "s,p", sreg); | |
670a50eb | 3758 | return; |
3d3c5039 | 3759 | } |
9a7d824a | 3760 | if (sreg == 0) |
670a50eb | 3761 | { |
0dd2d296 | 3762 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3763 | likely ? "bgtzl" : "bgtz", |
3764 | "s,p", treg); | |
670a50eb | 3765 | return; |
3d3c5039 | 3766 | } |
0dd2d296 ILT |
3767 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); |
3768 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3769 | likely ? "bnel" : "bne", |
3770 | "s,t,p", AT, 0); | |
670a50eb | 3771 | break; |
3d3c5039 | 3772 | |
8358c818 ILT |
3773 | case M_BLTUL: |
3774 | likely = 1; | |
3d3c5039 | 3775 | case M_BLTU: |
670a50eb | 3776 | if (treg == 0) |
9a7d824a ILT |
3777 | goto do_false; |
3778 | if (sreg == 0) | |
670a50eb | 3779 | { |
0dd2d296 | 3780 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
3781 | likely ? "bnel" : "bne", |
3782 | "s,t,p", 0, treg); | |
670a50eb ILT |
3783 | return; |
3784 | } | |
0dd2d296 ILT |
3785 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, |
3786 | treg); | |
3787 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
3788 | likely ? "bnel" : "bne", |
3789 | "s,t,p", AT, 0); | |
670a50eb | 3790 | break; |
3d3c5039 | 3791 | |
8358c818 ILT |
3792 | case M_DDIV_3: |
3793 | dbl = 1; | |
3d3c5039 | 3794 | case M_DIV_3: |
8358c818 ILT |
3795 | s = "mflo"; |
3796 | goto do_div3; | |
3797 | case M_DREM_3: | |
3798 | dbl = 1; | |
3d3c5039 | 3799 | case M_REM_3: |
8358c818 ILT |
3800 | s = "mfhi"; |
3801 | do_div3: | |
670a50eb ILT |
3802 | if (treg == 0) |
3803 | { | |
3804 | as_warn ("Divide by zero."); | |
8ea7f4e8 ILT |
3805 | if (mips_trap) |
3806 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
3807 | else | |
3808 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
670a50eb ILT |
3809 | return; |
3810 | } | |
3811 | ||
fbcfacb7 | 3812 | mips_emit_delays (true); |
3c83da8a | 3813 | ++mips_opts.noreorder; |
0dd2d296 ILT |
3814 | mips_any_noreorder = 1; |
3815 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 | 3816 | dbl ? "ddiv" : "div", |
ff3a5c18 | 3817 | "z,s,t", sreg, treg); |
8ea7f4e8 ILT |
3818 | if (mips_trap) |
3819 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
3820 | else | |
3821 | { | |
3822 | expr1.X_add_number = 8; | |
3823 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
3824 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3825 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
3826 | } | |
670a50eb | 3827 | expr1.X_add_number = -1; |
0dd2d296 | 3828 | macro_build ((char *) NULL, &icnt, &expr1, |
8358c818 | 3829 | dbl ? "daddiu" : "addiu", |
9226253a | 3830 | "t,r,j", AT, 0, (int) BFD_RELOC_LO16); |
8ea7f4e8 | 3831 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
0dd2d296 | 3832 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT); |
8358c818 ILT |
3833 | if (dbl) |
3834 | { | |
3835 | expr1.X_add_number = 1; | |
0dd2d296 | 3836 | macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0, |
9226253a | 3837 | (int) BFD_RELOC_LO16); |
0dd2d296 ILT |
3838 | macro_build ((char *) NULL, &icnt, NULL, "dsll32", "d,w,<", AT, AT, |
3839 | 31); | |
8358c818 ILT |
3840 | } |
3841 | else | |
3842 | { | |
3843 | expr1.X_add_number = 0x80000000; | |
ecd4ca1c ILT |
3844 | macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT, |
3845 | (int) BFD_RELOC_HI16); | |
8358c818 | 3846 | } |
8ea7f4e8 ILT |
3847 | if (mips_trap) |
3848 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", sreg, AT); | |
3849 | else | |
3850 | { | |
3851 | expr1.X_add_number = 8; | |
3852 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT); | |
3853 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3854 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
3855 | } | |
3c83da8a | 3856 | --mips_opts.noreorder; |
0dd2d296 | 3857 | macro_build ((char *) NULL, &icnt, NULL, s, "d", dreg); |
670a50eb | 3858 | break; |
3d3c5039 ILT |
3859 | |
3860 | case M_DIV_3I: | |
8358c818 ILT |
3861 | s = "div"; |
3862 | s2 = "mflo"; | |
3863 | goto do_divi; | |
3d3c5039 | 3864 | case M_DIVU_3I: |
8358c818 ILT |
3865 | s = "divu"; |
3866 | s2 = "mflo"; | |
3867 | goto do_divi; | |
3d3c5039 | 3868 | case M_REM_3I: |
8358c818 ILT |
3869 | s = "div"; |
3870 | s2 = "mfhi"; | |
3871 | goto do_divi; | |
3d3c5039 | 3872 | case M_REMU_3I: |
8358c818 ILT |
3873 | s = "divu"; |
3874 | s2 = "mfhi"; | |
3875 | goto do_divi; | |
3876 | case M_DDIV_3I: | |
3877 | dbl = 1; | |
3878 | s = "ddiv"; | |
3879 | s2 = "mflo"; | |
3880 | goto do_divi; | |
3881 | case M_DDIVU_3I: | |
3882 | dbl = 1; | |
3883 | s = "ddivu"; | |
3884 | s2 = "mflo"; | |
3885 | goto do_divi; | |
3886 | case M_DREM_3I: | |
3887 | dbl = 1; | |
3888 | s = "ddiv"; | |
3889 | s2 = "mfhi"; | |
3890 | goto do_divi; | |
3891 | case M_DREMU_3I: | |
3892 | dbl = 1; | |
3893 | s = "ddivu"; | |
3894 | s2 = "mfhi"; | |
3895 | do_divi: | |
5c6f5923 | 3896 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
670a50eb ILT |
3897 | { |
3898 | as_warn ("Divide by zero."); | |
8ea7f4e8 ILT |
3899 | if (mips_trap) |
3900 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
3901 | else | |
3902 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
670a50eb ILT |
3903 | return; |
3904 | } | |
5c6f5923 | 3905 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
670a50eb | 3906 | { |
8358c818 | 3907 | if (strcmp (s2, "mflo") == 0) |
0dd2d296 ILT |
3908 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, |
3909 | sreg); | |
3d3c5039 | 3910 | else |
0dd2d296 | 3911 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
3d3c5039 ILT |
3912 | return; |
3913 | } | |
5c6f5923 GRK |
3914 | if (imm_expr.X_op == O_constant |
3915 | && imm_expr.X_add_number == -1 | |
8358c818 ILT |
3916 | && s[strlen (s) - 1] != 'u') |
3917 | { | |
3918 | if (strcmp (s2, "mflo") == 0) | |
3919 | { | |
3920 | if (dbl) | |
0dd2d296 ILT |
3921 | macro_build ((char *) NULL, &icnt, NULL, "dneg", "d,w", dreg, |
3922 | sreg); | |
8358c818 | 3923 | else |
0dd2d296 ILT |
3924 | macro_build ((char *) NULL, &icnt, NULL, "neg", "d,w", dreg, |
3925 | sreg); | |
8358c818 ILT |
3926 | } |
3927 | else | |
0dd2d296 | 3928 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
8358c818 ILT |
3929 | return; |
3930 | } | |
3d3c5039 | 3931 | |
d8a1c247 | 3932 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 ILT |
3933 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, AT); |
3934 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); | |
670a50eb ILT |
3935 | break; |
3936 | ||
3937 | case M_DIVU_3: | |
8358c818 ILT |
3938 | s = "divu"; |
3939 | s2 = "mflo"; | |
3940 | goto do_divu3; | |
670a50eb | 3941 | case M_REMU_3: |
8358c818 ILT |
3942 | s = "divu"; |
3943 | s2 = "mfhi"; | |
3944 | goto do_divu3; | |
3945 | case M_DDIVU_3: | |
3946 | s = "ddivu"; | |
3947 | s2 = "mflo"; | |
3948 | goto do_divu3; | |
3949 | case M_DREMU_3: | |
3950 | s = "ddivu"; | |
3951 | s2 = "mfhi"; | |
3952 | do_divu3: | |
fbcfacb7 | 3953 | mips_emit_delays (true); |
3c83da8a | 3954 | ++mips_opts.noreorder; |
0dd2d296 ILT |
3955 | mips_any_noreorder = 1; |
3956 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, treg); | |
8ea7f4e8 ILT |
3957 | if (mips_trap) |
3958 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
3959 | else | |
3960 | { | |
3961 | expr1.X_add_number = 8; | |
3962 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
3963 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3964 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
3965 | } | |
3c83da8a | 3966 | --mips_opts.noreorder; |
0dd2d296 | 3967 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); |
670a50eb | 3968 | return; |
3d3c5039 | 3969 | |
d8a1c247 KR |
3970 | case M_DLA_AB: |
3971 | dbl = 1; | |
0dd2d296 | 3972 | case M_LA_AB: |
d9aba805 ILT |
3973 | /* Load the address of a symbol into a register. If breg is not |
3974 | zero, we then add a base register to it. */ | |
ecd4ca1c ILT |
3975 | |
3976 | /* When generating embedded PIC code, we permit expressions of | |
3977 | the form | |
3978 | la $4,foo-bar | |
3979 | where bar is an address in the .text section. These are used | |
3980 | when getting the addresses of functions. We don't permit | |
3981 | X_add_number to be non-zero, because if the symbol is | |
3982 | external the relaxing code needs to know that any addend is | |
3983 | purely the offset to X_op_symbol. */ | |
3984 | if (mips_pic == EMBEDDED_PIC | |
3985 | && offset_expr.X_op == O_subtract | |
3986 | && now_seg == text_section | |
847a01cd ILT |
3987 | && (offset_expr.X_op_symbol->sy_value.X_op == O_constant |
3988 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == text_section | |
3989 | : (offset_expr.X_op_symbol->sy_value.X_op == O_symbol | |
3990 | && (S_GET_SEGMENT (offset_expr.X_op_symbol | |
3991 | ->sy_value.X_add_symbol) | |
3992 | == text_section))) | |
ecd4ca1c ILT |
3993 | && breg == 0 |
3994 | && offset_expr.X_add_number == 0) | |
3995 | { | |
3996 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
3997 | treg, (int) BFD_RELOC_PCREL_HI16_S); | |
3998 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3c83da8a | 3999 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
ecd4ca1c ILT |
4000 | "t,r,j", treg, treg, (int) BFD_RELOC_PCREL_LO16); |
4001 | return; | |
4002 | } | |
4003 | ||
0dd2d296 ILT |
4004 | if (offset_expr.X_op != O_symbol |
4005 | && offset_expr.X_op != O_constant) | |
670a50eb | 4006 | { |
0dd2d296 ILT |
4007 | as_bad ("expression too complex"); |
4008 | offset_expr.X_op = O_constant; | |
4009 | } | |
4010 | ||
4011 | if (treg == breg) | |
4012 | { | |
4013 | tempreg = AT; | |
4014 | used_at = 1; | |
3d3c5039 | 4015 | } |
670a50eb ILT |
4016 | else |
4017 | { | |
0dd2d296 ILT |
4018 | tempreg = treg; |
4019 | used_at = 0; | |
670a50eb | 4020 | } |
3d3c5039 | 4021 | |
5ac34ac3 | 4022 | if (offset_expr.X_op == O_constant) |
d8a1c247 | 4023 | load_register (&icnt, tempreg, &offset_expr, dbl); |
d9aba805 | 4024 | else if (mips_pic == NO_PIC) |
670a50eb | 4025 | { |
0dd2d296 ILT |
4026 | /* If this is a reference to an GP relative symbol, we want |
4027 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
4028 | Otherwise we want | |
4029 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4030 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4031 | If we have a constant, we need two instructions anyhow, | |
4032 | so we may as well always use the latter form. */ | |
7a15a226 | 4033 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
85ce5635 | 4034 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
0dd2d296 ILT |
4035 | p = NULL; |
4036 | else | |
4037 | { | |
8ea7f4e8 | 4038 | frag_grow (20); |
0dd2d296 | 4039 | macro_build ((char *) NULL, &icnt, &offset_expr, |
3c83da8a | 4040 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
0dd2d296 ILT |
4041 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); |
4042 | p = frag_var (rs_machine_dependent, 8, 0, | |
4043 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
3c83da8a | 4044 | mips_opts.warn_about_macros), |
f59fb6ca | 4045 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
4046 | (char *) NULL); |
4047 | } | |
4048 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4049 | if (p != NULL) | |
4050 | p += 4; | |
4051 | macro_build (p, &icnt, &offset_expr, | |
3c83da8a | 4052 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
0dd2d296 ILT |
4053 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4054 | } | |
fb251650 | 4055 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
0dd2d296 ILT |
4056 | { |
4057 | /* If this is a reference to an external symbol, and there | |
4058 | is no constant, we want | |
4059 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4060 | For a local symbol, we want | |
4061 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4062 | nop | |
4063 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4064 | ||
4065 | If we have a small constant, and this is a reference to | |
4066 | an external symbol, we want | |
4067 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4068 | nop | |
4069 | addiu $tempreg,$tempreg,<constant> | |
4070 | For a local symbol, we want the same instruction | |
4071 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
4072 | addiu instruction. | |
4073 | ||
4074 | If we have a large constant, and this is a reference to | |
4075 | an external symbol, we want | |
4076 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4077 | lui $at,<hiconstant> | |
4078 | addiu $at,$at,<loconstant> | |
4079 | addu $tempreg,$tempreg,$at | |
4080 | For a local symbol, we want the same instruction | |
4081 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
4082 | addiu instruction. */ | |
4083 | expr1.X_add_number = offset_expr.X_add_number; | |
4084 | offset_expr.X_add_number = 0; | |
8ea7f4e8 | 4085 | frag_grow (32); |
0dd2d296 | 4086 | macro_build ((char *) NULL, &icnt, &offset_expr, |
d8a1c247 | 4087 | dbl ? "ld" : "lw", |
0dd2d296 ILT |
4088 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
4089 | if (expr1.X_add_number == 0) | |
4090 | { | |
4091 | int off; | |
4092 | ||
4093 | if (breg == 0) | |
4094 | off = 0; | |
4095 | else | |
4096 | { | |
4097 | /* We're going to put in an addu instruction using | |
4098 | tempreg, so we may as well insert the nop right | |
4099 | now. */ | |
4100 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4101 | "nop", ""); | |
4102 | off = 4; | |
4103 | } | |
4104 | p = frag_var (rs_machine_dependent, 8 - off, 0, | |
4105 | RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0, | |
4106 | (breg == 0 | |
3c83da8a | 4107 | ? mips_opts.warn_about_macros |
0dd2d296 | 4108 | : 0)), |
f59fb6ca | 4109 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
4110 | (char *) NULL); |
4111 | if (breg == 0) | |
4112 | { | |
4113 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4114 | p += 4; | |
4115 | } | |
4116 | macro_build (p, &icnt, &expr1, | |
3c83da8a | 4117 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
0dd2d296 ILT |
4118 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4119 | /* FIXME: If breg == 0, and the next instruction uses | |
4120 | $tempreg, then if this variant case is used an extra | |
4121 | nop will be generated. */ | |
4122 | } | |
4123 | else if (expr1.X_add_number >= -0x8000 | |
4124 | && expr1.X_add_number < 0x8000) | |
4125 | { | |
4126 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4127 | "nop", ""); | |
4128 | macro_build ((char *) NULL, &icnt, &expr1, | |
3c83da8a | 4129 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
0dd2d296 ILT |
4130 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4131 | (void) frag_var (rs_machine_dependent, 0, 0, | |
4132 | RELAX_ENCODE (0, 0, -12, -4, 0, 0), | |
f59fb6ca | 4133 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
4134 | (char *) NULL); |
4135 | } | |
4136 | else | |
4137 | { | |
4138 | int off1; | |
4139 | ||
4140 | /* If we are going to add in a base register, and the | |
4141 | target register and the base register are the same, | |
4142 | then we are using AT as a temporary register. Since | |
4143 | we want to load the constant into AT, we add our | |
4144 | current AT (from the global offset table) and the | |
4145 | register into the register now, and pretend we were | |
4146 | not using a base register. */ | |
4147 | if (breg != treg) | |
4148 | off1 = 0; | |
4149 | else | |
4150 | { | |
4151 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4152 | "nop", ""); | |
4153 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3c83da8a | 4154 | mips_opts.isa < 3 ? "addu" : "daddu", |
0dd2d296 ILT |
4155 | "d,v,t", treg, AT, breg); |
4156 | breg = 0; | |
4157 | tempreg = treg; | |
4158 | off1 = -8; | |
4159 | } | |
4160 | ||
55933a58 ILT |
4161 | /* Set mips_optimize around the lui instruction to avoid |
4162 | inserting an unnecessary nop after the lw. */ | |
4163 | hold_mips_optimize = mips_optimize; | |
4164 | mips_optimize = 2; | |
0dd2d296 | 4165 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); |
55933a58 ILT |
4166 | mips_optimize = hold_mips_optimize; |
4167 | ||
0dd2d296 | 4168 | macro_build ((char *) NULL, &icnt, &expr1, |
3c83da8a | 4169 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
0dd2d296 ILT |
4170 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
4171 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3c83da8a | 4172 | mips_opts.isa < 3 ? "addu" : "daddu", |
0dd2d296 ILT |
4173 | "d,v,t", tempreg, tempreg, AT); |
4174 | (void) frag_var (rs_machine_dependent, 0, 0, | |
4175 | RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0), | |
f59fb6ca | 4176 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
4177 | (char *) NULL); |
4178 | used_at = 1; | |
4179 | } | |
670a50eb | 4180 | } |
fb251650 ILT |
4181 | else if (mips_pic == SVR4_PIC) |
4182 | { | |
4183 | int gpdel; | |
4184 | ||
4185 | /* This is the large GOT case. If this is a reference to an | |
4186 | external symbol, and there is no constant, we want | |
4187 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4188 | addu $tempreg,$tempreg,$gp | |
4189 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4190 | For a local symbol, we want | |
4191 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4192 | nop | |
4193 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4194 | ||
4195 | If we have a small constant, and this is a reference to | |
4196 | an external symbol, we want | |
4197 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4198 | addu $tempreg,$tempreg,$gp | |
4199 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4200 | nop | |
4201 | addiu $tempreg,$tempreg,<constant> | |
4202 | For a local symbol, we want | |
4203 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4204 | nop | |
4205 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
4206 | ||
4207 | If we have a large constant, and this is a reference to | |
4208 | an external symbol, we want | |
4209 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4210 | addu $tempreg,$tempreg,$gp | |
4211 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4212 | lui $at,<hiconstant> | |
4213 | addiu $at,$at,<loconstant> | |
4214 | addu $tempreg,$tempreg,$at | |
4215 | For a local symbol, we want | |
4216 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4217 | lui $at,<hiconstant> | |
4218 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
4219 | addu $tempreg,$tempreg,$at | |
4220 | */ | |
4221 | expr1.X_add_number = offset_expr.X_add_number; | |
4222 | offset_expr.X_add_number = 0; | |
4223 | frag_grow (52); | |
4224 | if (reg_needs_delay (GP)) | |
4225 | gpdel = 4; | |
4226 | else | |
4227 | gpdel = 0; | |
4228 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4229 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
4230 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3c83da8a | 4231 | mips_opts.isa < 3 ? "addu" : "daddu", |
fb251650 ILT |
4232 | "d,v,t", tempreg, tempreg, GP); |
4233 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4234 | dbl ? "ld" : "lw", | |
4235 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, | |
4236 | tempreg); | |
4237 | if (expr1.X_add_number == 0) | |
4238 | { | |
4239 | int off; | |
4240 | ||
4241 | if (breg == 0) | |
4242 | off = 0; | |
4243 | else | |
4244 | { | |
4245 | /* We're going to put in an addu instruction using | |
4246 | tempreg, so we may as well insert the nop right | |
4247 | now. */ | |
4248 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4249 | "nop", ""); | |
4250 | off = 4; | |
4251 | } | |
4252 | ||
4253 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4254 | RELAX_ENCODE (12 + off, 12 + gpdel, gpdel, | |
4255 | 8 + gpdel, 0, | |
4256 | (breg == 0 | |
3c83da8a | 4257 | ? mips_opts.warn_about_macros |
fb251650 | 4258 | : 0)), |
f59fb6ca | 4259 | offset_expr.X_add_symbol, (offsetT) 0, |
fb251650 ILT |
4260 | (char *) NULL); |
4261 | } | |
4262 | else if (expr1.X_add_number >= -0x8000 | |
4263 | && expr1.X_add_number < 0x8000) | |
4264 | { | |
4265 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4266 | "nop", ""); | |
4267 | macro_build ((char *) NULL, &icnt, &expr1, | |
3c83da8a | 4268 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
fb251650 ILT |
4269 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4270 | ||
4271 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4272 | RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0, | |
4273 | (breg == 0 | |
3c83da8a | 4274 | ? mips_opts.warn_about_macros |
fb251650 | 4275 | : 0)), |
f59fb6ca | 4276 | offset_expr.X_add_symbol, (offsetT) 0, |
fb251650 ILT |
4277 | (char *) NULL); |
4278 | } | |
4279 | else | |
4280 | { | |
4281 | int adj, dreg; | |
4282 | ||
4283 | /* If we are going to add in a base register, and the | |
4284 | target register and the base register are the same, | |
4285 | then we are using AT as a temporary register. Since | |
4286 | we want to load the constant into AT, we add our | |
4287 | current AT (from the global offset table) and the | |
4288 | register into the register now, and pretend we were | |
4289 | not using a base register. */ | |
4290 | if (breg != treg) | |
4291 | { | |
4292 | adj = 0; | |
4293 | dreg = tempreg; | |
4294 | } | |
4295 | else | |
4296 | { | |
4297 | assert (tempreg == AT); | |
4298 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4299 | "nop", ""); | |
4300 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3c83da8a | 4301 | mips_opts.isa < 3 ? "addu" : "daddu", |
fb251650 ILT |
4302 | "d,v,t", treg, AT, breg); |
4303 | dreg = treg; | |
4304 | adj = 8; | |
4305 | } | |
4306 | ||
4307 | /* Set mips_optimize around the lui instruction to avoid | |
4308 | inserting an unnecessary nop after the lw. */ | |
4309 | hold_mips_optimize = mips_optimize; | |
4310 | mips_optimize = 2; | |
4311 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); | |
4312 | mips_optimize = hold_mips_optimize; | |
4313 | ||
4314 | macro_build ((char *) NULL, &icnt, &expr1, | |
3c83da8a | 4315 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
fb251650 ILT |
4316 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
4317 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3c83da8a | 4318 | mips_opts.isa < 3 ? "addu" : "daddu", |
fb251650 ILT |
4319 | "d,v,t", dreg, dreg, AT); |
4320 | ||
4321 | p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0, | |
4322 | RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel, | |
4323 | 8 + gpdel, 0, | |
4324 | (breg == 0 | |
3c83da8a | 4325 | ? mips_opts.warn_about_macros |
fb251650 | 4326 | : 0)), |
f59fb6ca | 4327 | offset_expr.X_add_symbol, (offsetT) 0, |
fb251650 ILT |
4328 | (char *) NULL); |
4329 | ||
4330 | used_at = 1; | |
4331 | } | |
4332 | ||
4333 | if (gpdel > 0) | |
4334 | { | |
4335 | /* This is needed because this instruction uses $gp, but | |
4336 | the first instruction on the main stream does not. */ | |
4337 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4338 | p += 4; | |
4339 | } | |
4340 | macro_build (p, &icnt, &offset_expr, | |
4341 | dbl ? "ld" : "lw", | |
4342 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4343 | p += 4; | |
4344 | if (expr1.X_add_number >= -0x8000 | |
4345 | && expr1.X_add_number < 0x8000) | |
4346 | { | |
4347 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4348 | p += 4; | |
4349 | macro_build (p, &icnt, &expr1, | |
3c83da8a | 4350 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
fb251650 ILT |
4351 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4352 | /* FIXME: If add_number is 0, and there was no base | |
4353 | register, the external symbol case ended with a load, | |
4354 | so if the symbol turns out to not be external, and | |
4355 | the next instruction uses tempreg, an unnecessary nop | |
4356 | will be inserted. */ | |
4357 | } | |
4358 | else | |
4359 | { | |
4360 | if (breg == treg) | |
4361 | { | |
4362 | /* We must add in the base register now, as in the | |
4363 | external symbol case. */ | |
4364 | assert (tempreg == AT); | |
4365 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4366 | p += 4; | |
4367 | macro_build (p, &icnt, (expressionS *) NULL, | |
3c83da8a | 4368 | mips_opts.isa < 3 ? "addu" : "daddu", |
fb251650 ILT |
4369 | "d,v,t", treg, AT, breg); |
4370 | p += 4; | |
4371 | tempreg = treg; | |
4372 | /* We set breg to 0 because we have arranged to add | |
4373 | it in in both cases. */ | |
4374 | breg = 0; | |
4375 | } | |
4376 | ||
4377 | macro_build_lui (p, &icnt, &expr1, AT); | |
4378 | p += 4; | |
4379 | macro_build (p, &icnt, &expr1, | |
3c83da8a | 4380 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
fb251650 ILT |
4381 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
4382 | p += 4; | |
4383 | macro_build (p, &icnt, (expressionS *) NULL, | |
3c83da8a | 4384 | mips_opts.isa < 3 ? "addu" : "daddu", |
fb251650 ILT |
4385 | "d,v,t", tempreg, tempreg, AT); |
4386 | p += 4; | |
4387 | } | |
4388 | } | |
d9aba805 ILT |
4389 | else if (mips_pic == EMBEDDED_PIC) |
4390 | { | |
4391 | /* We use | |
4392 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
4393 | */ | |
4394 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3c83da8a | 4395 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
d9aba805 ILT |
4396 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); |
4397 | } | |
4398 | else | |
4399 | abort (); | |
0dd2d296 | 4400 | |
670a50eb | 4401 | if (breg != 0) |
0dd2d296 | 4402 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
3c83da8a | 4403 | mips_opts.isa < 3 ? "addu" : "daddu", |
0dd2d296 ILT |
4404 | "d,v,t", treg, tempreg, breg); |
4405 | ||
4406 | if (! used_at) | |
4407 | return; | |
4408 | ||
4409 | break; | |
4410 | ||
4411 | case M_J_A: | |
4412 | /* The j instruction may not be used in PIC code, since it | |
4413 | requires an absolute address. We convert it to a b | |
4414 | instruction. */ | |
d9aba805 | 4415 | if (mips_pic == NO_PIC) |
0dd2d296 ILT |
4416 | macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a"); |
4417 | else | |
4418 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); | |
670a50eb | 4419 | return; |
3d3c5039 | 4420 | |
9226253a ILT |
4421 | /* The jal instructions must be handled as macros because when |
4422 | generating PIC code they expand to multi-instruction | |
4423 | sequences. Normally they are simple instructions. */ | |
4424 | case M_JAL_1: | |
4425 | dreg = RA; | |
4426 | /* Fall through. */ | |
4427 | case M_JAL_2: | |
d9aba805 ILT |
4428 | if (mips_pic == NO_PIC |
4429 | || mips_pic == EMBEDDED_PIC) | |
4430 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", | |
4431 | "d,s", dreg, sreg); | |
4432 | else if (mips_pic == SVR4_PIC) | |
9226253a | 4433 | { |
d9aba805 ILT |
4434 | if (sreg != PIC_CALL_REG) |
4435 | as_warn ("MIPS PIC call to register other than $25"); | |
4436 | ||
0dd2d296 ILT |
4437 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", |
4438 | "d,s", dreg, sreg); | |
d9aba805 ILT |
4439 | if (mips_cprestore_offset < 0) |
4440 | as_warn ("No .cprestore pseudo-op used in PIC code"); | |
4441 | else | |
4442 | { | |
4443 | expr1.X_add_number = mips_cprestore_offset; | |
4444 | macro_build ((char *) NULL, &icnt, &expr1, | |
3c83da8a | 4445 | mips_opts.isa < 3 ? "lw" : "ld", |
d9aba805 ILT |
4446 | "t,o(b)", GP, (int) BFD_RELOC_LO16, mips_frame_reg); |
4447 | } | |
9226253a | 4448 | } |
0dd2d296 | 4449 | else |
d9aba805 ILT |
4450 | abort (); |
4451 | ||
9226253a ILT |
4452 | return; |
4453 | ||
4454 | case M_JAL_A: | |
d9aba805 ILT |
4455 | if (mips_pic == NO_PIC) |
4456 | macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a"); | |
4457 | else if (mips_pic == SVR4_PIC) | |
9226253a | 4458 | { |
fb251650 ILT |
4459 | /* If this is a reference to an external symbol, and we are |
4460 | using a small GOT, we want | |
d9aba805 ILT |
4461 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
4462 | nop | |
4463 | jalr $25 | |
4464 | nop | |
4465 | lw $gp,cprestore($sp) | |
4466 | The cprestore value is set using the .cprestore | |
fb251650 ILT |
4467 | pseudo-op. If we are using a big GOT, we want |
4468 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
4469 | addu $25,$25,$gp | |
4470 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
4471 | nop | |
4472 | jalr $25 | |
4473 | nop | |
4474 | lw $gp,cprestore($sp) | |
4475 | If the symbol is not external, we want | |
d9aba805 ILT |
4476 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
4477 | nop | |
4478 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
4479 | jalr $25 | |
4480 | nop | |
fb251650 ILT |
4481 | lw $gp,cprestore($sp) */ |
4482 | frag_grow (40); | |
4483 | if (! mips_big_got) | |
4484 | { | |
4485 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3c83da8a | 4486 | mips_opts.isa < 3 ? "lw" : "ld", |
fb251650 ILT |
4487 | "t,o(b)", PIC_CALL_REG, |
4488 | (int) BFD_RELOC_MIPS_CALL16, GP); | |
4489 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4490 | "nop", ""); | |
4491 | p = frag_var (rs_machine_dependent, 4, 0, | |
4492 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
f59fb6ca ILT |
4493 | offset_expr.X_add_symbol, (offsetT) 0, |
4494 | (char *) NULL); | |
fb251650 ILT |
4495 | } |
4496 | else | |
4497 | { | |
4498 | int gpdel; | |
4499 | ||
4500 | if (reg_needs_delay (GP)) | |
4501 | gpdel = 4; | |
4502 | else | |
4503 | gpdel = 0; | |
4504 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4505 | PIC_CALL_REG, (int) BFD_RELOC_MIPS_CALL_HI16); | |
4506 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3c83da8a | 4507 | mips_opts.isa < 3 ? "addu" : "daddu", |
fb251650 ILT |
4508 | "d,v,t", PIC_CALL_REG, PIC_CALL_REG, GP); |
4509 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3c83da8a | 4510 | mips_opts.isa < 3 ? "lw" : "ld", |
fb251650 ILT |
4511 | "t,o(b)", PIC_CALL_REG, |
4512 | (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG); | |
4513 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4514 | "nop", ""); | |
4515 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4516 | RELAX_ENCODE (16, 12 + gpdel, gpdel, 8 + gpdel, | |
4517 | 0, 0), | |
f59fb6ca ILT |
4518 | offset_expr.X_add_symbol, (offsetT) 0, |
4519 | (char *) NULL); | |
fb251650 ILT |
4520 | if (gpdel > 0) |
4521 | { | |
4522 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4523 | p += 4; | |
4524 | } | |
4525 | macro_build (p, &icnt, &offset_expr, | |
3c83da8a | 4526 | mips_opts.isa < 3 ? "lw" : "ld", |
fb251650 ILT |
4527 | "t,o(b)", PIC_CALL_REG, |
4528 | (int) BFD_RELOC_MIPS_GOT16, GP); | |
4529 | p += 4; | |
4530 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4531 | p += 4; | |
4532 | } | |
d9aba805 | 4533 | macro_build (p, &icnt, &offset_expr, |
3c83da8a | 4534 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
d9aba805 ILT |
4535 | "t,r,j", PIC_CALL_REG, PIC_CALL_REG, |
4536 | (int) BFD_RELOC_LO16); | |
4537 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4538 | "jalr", "s", PIC_CALL_REG); | |
4539 | if (mips_cprestore_offset < 0) | |
4540 | as_warn ("No .cprestore pseudo-op used in PIC code"); | |
4541 | else | |
4542 | { | |
3c83da8a | 4543 | if (mips_opts.noreorder) |
d9aba805 ILT |
4544 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4545 | "nop", ""); | |
4546 | expr1.X_add_number = mips_cprestore_offset; | |
4547 | macro_build ((char *) NULL, &icnt, &expr1, | |
3c83da8a | 4548 | mips_opts.isa < 3 ? "lw" : "ld", |
d9aba805 ILT |
4549 | "t,o(b)", GP, (int) BFD_RELOC_LO16, |
4550 | mips_frame_reg); | |
4551 | } | |
0dd2d296 | 4552 | } |
d9aba805 | 4553 | else if (mips_pic == EMBEDDED_PIC) |
5b63f465 ILT |
4554 | { |
4555 | macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p"); | |
4556 | /* The linker may expand the call to a longer sequence which | |
4557 | uses $at, so we must break rather than return. */ | |
4558 | break; | |
4559 | } | |
d9aba805 ILT |
4560 | else |
4561 | abort (); | |
4562 | ||
9226253a ILT |
4563 | return; |
4564 | ||
3d3c5039 | 4565 | case M_LB_AB: |
670a50eb ILT |
4566 | s = "lb"; |
4567 | goto ld; | |
3d3c5039 | 4568 | case M_LBU_AB: |
670a50eb ILT |
4569 | s = "lbu"; |
4570 | goto ld; | |
3d3c5039 | 4571 | case M_LH_AB: |
670a50eb ILT |
4572 | s = "lh"; |
4573 | goto ld; | |
3d3c5039 | 4574 | case M_LHU_AB: |
670a50eb ILT |
4575 | s = "lhu"; |
4576 | goto ld; | |
3d3c5039 | 4577 | case M_LW_AB: |
670a50eb ILT |
4578 | s = "lw"; |
4579 | goto ld; | |
3d3c5039 | 4580 | case M_LWC0_AB: |
670a50eb | 4581 | s = "lwc0"; |
efec4a28 | 4582 | /* Itbl support may require additional care here. */ |
8358c818 | 4583 | coproc = 1; |
670a50eb | 4584 | goto ld; |
3d3c5039 | 4585 | case M_LWC1_AB: |
670a50eb | 4586 | s = "lwc1"; |
efec4a28 | 4587 | /* Itbl support may require additional care here. */ |
8358c818 | 4588 | coproc = 1; |
670a50eb | 4589 | goto ld; |
3d3c5039 | 4590 | case M_LWC2_AB: |
670a50eb | 4591 | s = "lwc2"; |
efec4a28 | 4592 | /* Itbl support may require additional care here. */ |
8358c818 | 4593 | coproc = 1; |
670a50eb | 4594 | goto ld; |
3d3c5039 | 4595 | case M_LWC3_AB: |
670a50eb | 4596 | s = "lwc3"; |
efec4a28 | 4597 | /* Itbl support may require additional care here. */ |
8358c818 | 4598 | coproc = 1; |
670a50eb | 4599 | goto ld; |
3d3c5039 | 4600 | case M_LWL_AB: |
670a50eb | 4601 | s = "lwl"; |
b2b8c24e | 4602 | lr = 1; |
670a50eb | 4603 | goto ld; |
3d3c5039 | 4604 | case M_LWR_AB: |
670a50eb | 4605 | s = "lwr"; |
b2b8c24e | 4606 | lr = 1; |
8358c818 ILT |
4607 | goto ld; |
4608 | case M_LDC1_AB: | |
4609 | s = "ldc1"; | |
efec4a28 | 4610 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4611 | coproc = 1; |
4612 | goto ld; | |
4613 | case M_LDC2_AB: | |
4614 | s = "ldc2"; | |
efec4a28 | 4615 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4616 | coproc = 1; |
4617 | goto ld; | |
4618 | case M_LDC3_AB: | |
4619 | s = "ldc3"; | |
efec4a28 | 4620 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4621 | coproc = 1; |
4622 | goto ld; | |
4623 | case M_LDL_AB: | |
4624 | s = "ldl"; | |
b2b8c24e | 4625 | lr = 1; |
8358c818 ILT |
4626 | goto ld; |
4627 | case M_LDR_AB: | |
4628 | s = "ldr"; | |
b2b8c24e | 4629 | lr = 1; |
8358c818 ILT |
4630 | goto ld; |
4631 | case M_LL_AB: | |
4632 | s = "ll"; | |
4633 | goto ld; | |
4634 | case M_LLD_AB: | |
4635 | s = "lld"; | |
4636 | goto ld; | |
4637 | case M_LWU_AB: | |
4638 | s = "lwu"; | |
3d3c5039 | 4639 | ld: |
b2b8c24e | 4640 | if (breg == treg || coproc || lr) |
670a50eb ILT |
4641 | { |
4642 | tempreg = AT; | |
4643 | used_at = 1; | |
4644 | } | |
4645 | else | |
4646 | { | |
4647 | tempreg = treg; | |
4648 | used_at = 0; | |
4649 | } | |
4650 | goto ld_st; | |
3d3c5039 | 4651 | case M_SB_AB: |
670a50eb ILT |
4652 | s = "sb"; |
4653 | goto st; | |
3d3c5039 | 4654 | case M_SH_AB: |
670a50eb ILT |
4655 | s = "sh"; |
4656 | goto st; | |
3d3c5039 | 4657 | case M_SW_AB: |
670a50eb ILT |
4658 | s = "sw"; |
4659 | goto st; | |
3d3c5039 | 4660 | case M_SWC0_AB: |
670a50eb | 4661 | s = "swc0"; |
efec4a28 | 4662 | /* Itbl support may require additional care here. */ |
8358c818 | 4663 | coproc = 1; |
670a50eb | 4664 | goto st; |
3d3c5039 | 4665 | case M_SWC1_AB: |
670a50eb | 4666 | s = "swc1"; |
efec4a28 | 4667 | /* Itbl support may require additional care here. */ |
8358c818 | 4668 | coproc = 1; |
670a50eb | 4669 | goto st; |
3d3c5039 | 4670 | case M_SWC2_AB: |
670a50eb | 4671 | s = "swc2"; |
efec4a28 | 4672 | /* Itbl support may require additional care here. */ |
8358c818 | 4673 | coproc = 1; |
670a50eb | 4674 | goto st; |
3d3c5039 | 4675 | case M_SWC3_AB: |
670a50eb | 4676 | s = "swc3"; |
efec4a28 | 4677 | /* Itbl support may require additional care here. */ |
8358c818 | 4678 | coproc = 1; |
670a50eb | 4679 | goto st; |
3d3c5039 | 4680 | case M_SWL_AB: |
670a50eb ILT |
4681 | s = "swl"; |
4682 | goto st; | |
3d3c5039 | 4683 | case M_SWR_AB: |
670a50eb | 4684 | s = "swr"; |
8358c818 ILT |
4685 | goto st; |
4686 | case M_SC_AB: | |
4687 | s = "sc"; | |
4688 | goto st; | |
4689 | case M_SCD_AB: | |
4690 | s = "scd"; | |
4691 | goto st; | |
4692 | case M_SDC1_AB: | |
4693 | s = "sdc1"; | |
4694 | coproc = 1; | |
efec4a28 | 4695 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4696 | goto st; |
4697 | case M_SDC2_AB: | |
4698 | s = "sdc2"; | |
efec4a28 | 4699 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4700 | coproc = 1; |
4701 | goto st; | |
4702 | case M_SDC3_AB: | |
4703 | s = "sdc3"; | |
efec4a28 | 4704 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4705 | coproc = 1; |
4706 | goto st; | |
4707 | case M_SDL_AB: | |
4708 | s = "sdl"; | |
4709 | goto st; | |
4710 | case M_SDR_AB: | |
4711 | s = "sdr"; | |
3d3c5039 | 4712 | st: |
670a50eb ILT |
4713 | tempreg = AT; |
4714 | used_at = 1; | |
3d3c5039 | 4715 | ld_st: |
efec4a28 | 4716 | /* Itbl support may require additional care here. */ |
8358c818 ILT |
4717 | if (mask == M_LWC1_AB |
4718 | || mask == M_SWC1_AB | |
8358c818 | 4719 | || mask == M_LDC1_AB |
0dd2d296 ILT |
4720 | || mask == M_SDC1_AB |
4721 | || mask == M_L_DAB | |
4722 | || mask == M_S_DAB) | |
670a50eb | 4723 | fmt = "T,o(b)"; |
8358c818 | 4724 | else if (coproc) |
19ed8960 | 4725 | fmt = "E,o(b)"; |
670a50eb ILT |
4726 | else |
4727 | fmt = "t,o(b)"; | |
0dd2d296 ILT |
4728 | |
4729 | if (offset_expr.X_op != O_constant | |
4730 | && offset_expr.X_op != O_symbol) | |
4731 | { | |
4732 | as_bad ("expression too complex"); | |
4733 | offset_expr.X_op = O_constant; | |
4734 | } | |
4735 | ||
4736 | /* A constant expression in PIC code can be handled just as it | |
4737 | is in non PIC code. */ | |
d9aba805 | 4738 | if (mips_pic == NO_PIC |
0dd2d296 | 4739 | || offset_expr.X_op == O_constant) |
670a50eb | 4740 | { |
0dd2d296 ILT |
4741 | /* If this is a reference to a GP relative symbol, and there |
4742 | is no base register, we want | |
4743 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
d9aba805 | 4744 | Otherwise, if there is no base register, we want |
0dd2d296 ILT |
4745 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) |
4746 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
4747 | If we have a constant, we need two instructions anyhow, | |
4748 | so we always use the latter form. | |
4749 | ||
4750 | If we have a base register, and this is a reference to a | |
4751 | GP relative symbol, we want | |
4752 | addu $tempreg,$breg,$gp | |
4753 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
4754 | Otherwise we want | |
4755 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4756 | addu $tempreg,$tempreg,$breg | |
4757 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
4758 | With a constant we always use the latter case. */ | |
670a50eb ILT |
4759 | if (breg == 0) |
4760 | { | |
7a15a226 | 4761 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
85ce5635 | 4762 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
0dd2d296 ILT |
4763 | p = NULL; |
4764 | else | |
4765 | { | |
8ea7f4e8 | 4766 | frag_grow (20); |
0dd2d296 ILT |
4767 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
4768 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
4769 | p = frag_var (rs_machine_dependent, 8, 0, | |
4770 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
3c83da8a JW |
4771 | (mips_opts.warn_about_macros |
4772 | || (used_at | |
4773 | && mips_opts.noat))), | |
f59fb6ca | 4774 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 | 4775 | (char *) NULL); |
8197b589 | 4776 | used_at = 0; |
0dd2d296 ILT |
4777 | } |
4778 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4779 | if (p != NULL) | |
4780 | p += 4; | |
4781 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
4782 | (int) BFD_RELOC_LO16, tempreg); | |
4783 | } | |
4784 | else | |
4785 | { | |
7a15a226 | 4786 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
85ce5635 | 4787 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
0dd2d296 ILT |
4788 | p = NULL; |
4789 | else | |
4790 | { | |
8ea7f4e8 | 4791 | frag_grow (28); |
0dd2d296 | 4792 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
3c83da8a | 4793 | mips_opts.isa < 3 ? "addu" : "daddu", |
0dd2d296 ILT |
4794 | "d,v,t", tempreg, breg, GP); |
4795 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4796 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
4797 | p = frag_var (rs_machine_dependent, 12, 0, | |
4798 | RELAX_ENCODE (8, 12, 0, 8, 0, 0), | |
f59fb6ca | 4799 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
4800 | (char *) NULL); |
4801 | } | |
4802 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4803 | if (p != NULL) | |
4804 | p += 4; | |
4805 | macro_build (p, &icnt, (expressionS *) NULL, | |
3c83da8a | 4806 | mips_opts.isa < 3 ? "addu" : "daddu", |
0dd2d296 ILT |
4807 | "d,v,t", tempreg, tempreg, breg); |
4808 | if (p != NULL) | |
4809 | p += 4; | |
4810 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
4811 | (int) BFD_RELOC_LO16, tempreg); | |
670a50eb | 4812 | } |
670a50eb | 4813 | } |
fb251650 | 4814 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
670a50eb | 4815 | { |
0dd2d296 ILT |
4816 | /* If this is a reference to an external symbol, we want |
4817 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4818 | nop | |
4819 | <op> $treg,0($tempreg) | |
4820 | Otherwise we want | |
4821 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4822 | nop | |
4823 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4824 | <op> $treg,0($tempreg) | |
4825 | If there is a base register, we add it to $tempreg before | |
4826 | the <op>. If there is a constant, we stick it in the | |
4827 | <op> instruction. We don't handle constants larger than | |
4828 | 16 bits, because we have no way to load the upper 16 bits | |
4829 | (actually, we could handle them for the subset of cases | |
4830 | in which we are not using $at). */ | |
4831 | assert (offset_expr.X_op == O_symbol); | |
4832 | expr1.X_add_number = offset_expr.X_add_number; | |
4833 | offset_expr.X_add_number = 0; | |
4834 | if (expr1.X_add_number < -0x8000 | |
4835 | || expr1.X_add_number >= 0x8000) | |
4836 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
8ea7f4e8 | 4837 | frag_grow (20); |
0dd2d296 | 4838 | macro_build ((char *) NULL, &icnt, &offset_expr, |
3c83da8a | 4839 | mips_opts.isa < 3 ? "lw" : "ld", |
0dd2d296 ILT |
4840 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
4841 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
4842 | p = frag_var (rs_machine_dependent, 4, 0, | |
4843 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
f59fb6ca | 4844 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 ILT |
4845 | (char *) NULL); |
4846 | macro_build (p, &icnt, &offset_expr, | |
3c83da8a | 4847 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
0dd2d296 | 4848 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
670a50eb | 4849 | if (breg != 0) |
0dd2d296 | 4850 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
3c83da8a | 4851 | mips_opts.isa < 3 ? "addu" : "daddu", |
6e8dda9c | 4852 | "d,v,t", tempreg, tempreg, breg); |
0dd2d296 ILT |
4853 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, |
4854 | (int) BFD_RELOC_LO16, tempreg); | |
670a50eb | 4855 | } |
fb251650 ILT |
4856 | else if (mips_pic == SVR4_PIC) |
4857 | { | |
4858 | int gpdel; | |
4859 | ||
4860 | /* If this is a reference to an external symbol, we want | |
4861 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4862 | addu $tempreg,$tempreg,$gp | |
4863 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4864 | <op> $treg,0($tempreg) | |
4865 | Otherwise we want | |
4866 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4867 | nop | |
4868 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4869 | <op> $treg,0($tempreg) | |
4870 | If there is a base register, we add it to $tempreg before | |
4871 | the <op>. If there is a constant, we stick it in the | |
4872 | <op> instruction. We don't handle constants larger than | |
4873 | 16 bits, because we have no way to load the upper 16 bits | |
4874 | (actually, we could handle them for the subset of cases | |
4875 | in which we are not using $at). */ | |
4876 | assert (offset_expr.X_op == O_symbol); | |
4877 | expr1.X_add_number = offset_expr.X_add_number; | |
4878 | offset_expr.X_add_number = 0; | |
4879 | if (expr1.X_add_number < -0x8000 | |
4880 | || expr1.X_add_number >= 0x8000) | |
4881 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
4882 | if (reg_needs_delay (GP)) | |
4883 | gpdel = 4; | |
4884 | else | |
4885 | gpdel = 0; | |
4886 | frag_grow (36); | |
4887 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4888 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
4889 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3c83da8a | 4890 | mips_opts.isa < 3 ? "addu" : "daddu", |
fb251650 ILT |
4891 | "d,v,t", tempreg, tempreg, GP); |
4892 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3c83da8a | 4893 | mips_opts.isa < 3 ? "lw" : "ld", |
867a58b3 ILT |
4894 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, |
4895 | tempreg); | |
fb251650 ILT |
4896 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, |
4897 | RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0), | |
f59fb6ca | 4898 | offset_expr.X_add_symbol, (offsetT) 0, (char *) NULL); |
fb251650 ILT |
4899 | if (gpdel > 0) |
4900 | { | |
4901 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4902 | p += 4; | |
4903 | } | |
4904 | macro_build (p, &icnt, &offset_expr, | |
3c83da8a | 4905 | mips_opts.isa < 3 ? "lw" : "ld", |
867a58b3 | 4906 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
fb251650 ILT |
4907 | p += 4; |
4908 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4909 | p += 4; | |
4910 | macro_build (p, &icnt, &offset_expr, | |
3c83da8a | 4911 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
fb251650 ILT |
4912 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
4913 | if (breg != 0) | |
4914 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3c83da8a | 4915 | mips_opts.isa < 3 ? "addu" : "daddu", |
fb251650 ILT |
4916 | "d,v,t", tempreg, tempreg, breg); |
4917 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, | |
4918 | (int) BFD_RELOC_LO16, tempreg); | |
4919 | } | |
d9aba805 ILT |
4920 | else if (mips_pic == EMBEDDED_PIC) |
4921 | { | |
4922 | /* If there is no base register, we want | |
4923 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
4924 | If there is a base register, we want | |
4925 | addu $tempreg,$breg,$gp | |
4926 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
4927 | */ | |
4928 | assert (offset_expr.X_op == O_symbol); | |
4929 | if (breg == 0) | |
4930 | { | |
4931 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4932 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
4933 | used_at = 0; | |
4934 | } | |
4935 | else | |
4936 | { | |
4937 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3c83da8a | 4938 | mips_opts.isa < 3 ? "addu" : "daddu", |
d9aba805 ILT |
4939 | "d,v,t", tempreg, breg, GP); |
4940 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4941 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
4942 | } | |
4943 | } | |
4944 | else | |
4945 | abort (); | |
0dd2d296 ILT |
4946 | |
4947 | if (! used_at) | |
4948 | return; | |
4949 | ||
4950 | break; | |
3d3c5039 ILT |
4951 | |
4952 | case M_LI: | |
19ed8960 | 4953 | case M_LI_S: |
d8a1c247 KR |
4954 | load_register (&icnt, treg, &imm_expr, 0); |
4955 | return; | |
4956 | ||
4957 | case M_DLI: | |
4958 | load_register (&icnt, treg, &imm_expr, 1); | |
670a50eb | 4959 | return; |
3d3c5039 | 4960 | |
0dd2d296 | 4961 | case M_LI_SS: |
55933a58 | 4962 | if (imm_expr.X_op == O_constant) |
0dd2d296 | 4963 | { |
d8a1c247 | 4964 | load_register (&icnt, AT, &imm_expr, 0); |
d2c71068 ILT |
4965 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
4966 | "mtc1", "t,G", AT, treg); | |
4967 | break; | |
0dd2d296 | 4968 | } |
d9aba805 | 4969 | else |
d2c71068 | 4970 | { |
55933a58 ILT |
4971 | assert (offset_expr.X_op == O_symbol |
4972 | && strcmp (segment_name (S_GET_SEGMENT | |
4973 | (offset_expr.X_add_symbol)), | |
4974 | ".lit4") == 0 | |
4975 | && offset_expr.X_add_number == 0); | |
4976 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", | |
4977 | treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
d2c71068 ILT |
4978 | return; |
4979 | } | |
0dd2d296 | 4980 | |
3d3c5039 | 4981 | case M_LI_D: |
a5586bdc ILT |
4982 | /* If we have a constant in IMM_EXPR, then in mips3 mode it is |
4983 | the entire value, and in mips1 mode it is the high order 32 | |
4984 | bits of the value and the low order 32 bits are either zero | |
4985 | or in offset_expr. */ | |
4986 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) | |
4987 | { | |
4988 | load_register (&icnt, treg, &imm_expr, mips_opts.isa >= 3); | |
4989 | if (mips_opts.isa < 3 && treg != 31) | |
4990 | { | |
4991 | if (offset_expr.X_op == O_absent) | |
4992 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", | |
4993 | treg + 1, 0); | |
4994 | else | |
4995 | { | |
4996 | assert (offset_expr.X_op == O_constant); | |
4997 | load_register (&icnt, treg + 1, &offset_expr, 0); | |
4998 | } | |
4999 | } | |
5000 | return; | |
5001 | } | |
5002 | ||
d9aba805 ILT |
5003 | /* We know that sym is in the .rdata section. First we get the |
5004 | upper 16 bits of the address. */ | |
5005 | if (mips_pic == NO_PIC) | |
0dd2d296 ILT |
5006 | { |
5007 | /* FIXME: This won't work for a 64 bit address. */ | |
5008 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
5009 | } | |
d9aba805 | 5010 | else if (mips_pic == SVR4_PIC) |
0dd2d296 ILT |
5011 | { |
5012 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3c83da8a | 5013 | mips_opts.isa < 3 ? "lw" : "ld", |
0dd2d296 ILT |
5014 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); |
5015 | } | |
d9aba805 ILT |
5016 | else if (mips_pic == EMBEDDED_PIC) |
5017 | { | |
5018 | /* For embedded PIC we pick up the entire address off $gp in | |
5019 | a single instruction. */ | |
5020 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3c83da8a | 5021 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
d9aba805 ILT |
5022 | "t,r,j", AT, GP, (int) BFD_RELOC_MIPS_GPREL); |
5023 | offset_expr.X_op = O_constant; | |
5024 | offset_expr.X_add_number = 0; | |
5025 | } | |
5026 | else | |
5027 | abort (); | |
5028 | ||
0dd2d296 | 5029 | /* Now we load the register(s). */ |
3c83da8a | 5030 | if (mips_opts.isa >= 3) |
0dd2d296 ILT |
5031 | macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)", |
5032 | treg, (int) BFD_RELOC_LO16, AT); | |
8358c818 ILT |
5033 | else |
5034 | { | |
0dd2d296 ILT |
5035 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", |
5036 | treg, (int) BFD_RELOC_LO16, AT); | |
5037 | if (treg != 31) | |
5038 | { | |
5039 | /* FIXME: How in the world do we deal with the possible | |
5040 | overflow here? */ | |
5041 | offset_expr.X_add_number += 4; | |
5042 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", | |
5043 | treg + 1, (int) BFD_RELOC_LO16, AT); | |
5044 | } | |
8358c818 | 5045 | } |
d2c71068 ILT |
5046 | |
5047 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
5048 | does not become a variant frag. */ | |
5049 | frag_wane (frag_now); | |
5050 | frag_new (0); | |
5051 | ||
670a50eb | 5052 | break; |
3d3c5039 ILT |
5053 | |
5054 | case M_LI_DD: | |
a5586bdc ILT |
5055 | /* If we have a constant in IMM_EXPR, then in mips3 mode it is |
5056 | the entire value, and in mips1 mode it is the high order 32 | |
5057 | bits of the value and the low order 32 bits are either zero | |
5058 | or in offset_expr. */ | |
5059 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) | |
5060 | { | |
5061 | load_register (&icnt, AT, &imm_expr, mips_opts.isa >= 3); | |
5062 | if (mips_opts.isa >= 3) | |
5063 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5064 | "dmtc1", "t,S", AT, treg); | |
5065 | else | |
5066 | { | |
5067 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5068 | "mtc1", "t,G", AT, treg + 1); | |
5069 | if (offset_expr.X_op == O_absent) | |
5070 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5071 | "mtc1", "t,G", 0, treg); | |
5072 | else | |
5073 | { | |
5074 | assert (offset_expr.X_op == O_constant); | |
5075 | load_register (&icnt, AT, &offset_expr, 0); | |
5076 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5077 | "mtc1", "t,G", AT, treg); | |
5078 | } | |
5079 | } | |
5080 | break; | |
5081 | } | |
5082 | ||
55933a58 ILT |
5083 | assert (offset_expr.X_op == O_symbol |
5084 | && offset_expr.X_add_number == 0); | |
5085 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
5086 | if (strcmp (s, ".lit8") == 0) | |
8358c818 | 5087 | { |
3c83da8a | 5088 | if (mips_opts.isa >= 2) |
0dd2d296 ILT |
5089 | { |
5090 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
5091 | "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
5092 | return; | |
5093 | } | |
5094 | breg = GP; | |
5095 | r = BFD_RELOC_MIPS_LITERAL; | |
5096 | goto dob; | |
5097 | } | |
55933a58 | 5098 | else |
0dd2d296 | 5099 | { |
55933a58 ILT |
5100 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
5101 | if (mips_pic == SVR4_PIC) | |
5102 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3c83da8a | 5103 | mips_opts.isa < 3 ? "lw" : "ld", |
55933a58 ILT |
5104 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); |
5105 | else | |
5106 | { | |
5107 | /* FIXME: This won't work for a 64 bit address. */ | |
5108 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
5109 | } | |
5110 | ||
3c83da8a | 5111 | if (mips_opts.isa >= 2) |
0dd2d296 ILT |
5112 | { |
5113 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
55933a58 | 5114 | "T,o(b)", treg, (int) BFD_RELOC_LO16, AT); |
94b68f04 ILT |
5115 | |
5116 | /* To avoid confusion in tc_gen_reloc, we must ensure | |
5117 | that this does not become a variant frag. */ | |
5118 | frag_wane (frag_now); | |
5119 | frag_new (0); | |
5120 | ||
0dd2d296 ILT |
5121 | break; |
5122 | } | |
5123 | breg = AT; | |
5124 | r = BFD_RELOC_LO16; | |
5125 | goto dob; | |
8358c818 | 5126 | } |
9226253a | 5127 | |
3d3c5039 | 5128 | case M_L_DOB: |
9a7d824a ILT |
5129 | /* Even on a big endian machine $fn comes before $fn+1. We have |
5130 | to adjust when loading from memory. */ | |
9226253a ILT |
5131 | r = BFD_RELOC_LO16; |
5132 | dob: | |
3c83da8a | 5133 | assert (mips_opts.isa < 2); |
0dd2d296 | 5134 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
b9129c6f | 5135 | target_big_endian ? treg + 1 : treg, |
9226253a | 5136 | (int) r, breg); |
0dd2d296 ILT |
5137 | /* FIXME: A possible overflow which I don't know how to deal |
5138 | with. */ | |
670a50eb | 5139 | offset_expr.X_add_number += 4; |
0dd2d296 | 5140 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
b9129c6f | 5141 | target_big_endian ? treg : treg + 1, |
9226253a | 5142 | (int) r, breg); |
d2c71068 ILT |
5143 | |
5144 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
5145 | does not become a variant frag. */ | |
5146 | frag_wane (frag_now); | |
5147 | frag_new (0); | |
5148 | ||
0dd2d296 ILT |
5149 | if (breg != AT) |
5150 | return; | |
5151 | break; | |
3d3c5039 ILT |
5152 | |
5153 | case M_L_DAB: | |
670a50eb ILT |
5154 | /* |
5155 | * The MIPS assembler seems to check for X_add_number not | |
5156 | * being double aligned and generating: | |
5157 | * lui at,%hi(foo+1) | |
5158 | * addu at,at,v1 | |
5159 | * addiu at,at,%lo(foo+1) | |
5160 | * lwc1 f2,0(at) | |
5161 | * lwc1 f3,4(at) | |
5162 | * But, the resulting address is the same after relocation so why | |
5163 | * generate the extra instruction? | |
5164 | */ | |
efec4a28 | 5165 | /* Itbl support may require additional care here. */ |
4032d3f0 | 5166 | coproc = 1; |
3c83da8a | 5167 | if (mips_opts.isa >= 2) |
670a50eb | 5168 | { |
0dd2d296 ILT |
5169 | s = "ldc1"; |
5170 | goto ld; | |
670a50eb | 5171 | } |
0dd2d296 ILT |
5172 | |
5173 | s = "lwc1"; | |
5174 | fmt = "T,o(b)"; | |
0dd2d296 ILT |
5175 | goto ldd_std; |
5176 | ||
5177 | case M_S_DAB: | |
3c83da8a | 5178 | if (mips_opts.isa >= 2) |
8358c818 | 5179 | { |
0dd2d296 ILT |
5180 | s = "sdc1"; |
5181 | goto st; | |
8358c818 | 5182 | } |
3d3c5039 | 5183 | |
0dd2d296 ILT |
5184 | s = "swc1"; |
5185 | fmt = "T,o(b)"; | |
efec4a28 | 5186 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5187 | coproc = 1; |
5188 | goto ldd_std; | |
3d3c5039 ILT |
5189 | |
5190 | case M_LD_AB: | |
3c83da8a | 5191 | if (mips_opts.isa >= 3) |
670a50eb | 5192 | { |
0dd2d296 ILT |
5193 | s = "ld"; |
5194 | goto ld; | |
670a50eb | 5195 | } |
0dd2d296 ILT |
5196 | |
5197 | s = "lw"; | |
5198 | fmt = "t,o(b)"; | |
5199 | goto ldd_std; | |
5200 | ||
5201 | case M_SD_AB: | |
3c83da8a | 5202 | if (mips_opts.isa >= 3) |
670a50eb | 5203 | { |
0dd2d296 ILT |
5204 | s = "sd"; |
5205 | goto st; | |
670a50eb | 5206 | } |
0dd2d296 | 5207 | |
670a50eb | 5208 | s = "sw"; |
0dd2d296 ILT |
5209 | fmt = "t,o(b)"; |
5210 | ||
5211 | ldd_std: | |
5212 | if (offset_expr.X_op != O_symbol | |
5213 | && offset_expr.X_op != O_constant) | |
670a50eb | 5214 | { |
0dd2d296 ILT |
5215 | as_bad ("expression too complex"); |
5216 | offset_expr.X_op = O_constant; | |
5217 | } | |
5218 | ||
5219 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
5220 | to adjust when loading from memory. We set coproc if we must | |
5221 | load $fn+1 first. */ | |
efec4a28 | 5222 | /* Itbl support may require additional care here. */ |
b9129c6f | 5223 | if (! target_big_endian) |
0dd2d296 ILT |
5224 | coproc = 0; |
5225 | ||
d9aba805 | 5226 | if (mips_pic == NO_PIC |
0dd2d296 ILT |
5227 | || offset_expr.X_op == O_constant) |
5228 | { | |
5229 | /* If this is a reference to a GP relative symbol, we want | |
5230 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
5231 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
5232 | If we have a base register, we use this | |
5233 | addu $at,$breg,$gp | |
5234 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
5235 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
5236 | If this is not a GP relative symbol, we want | |
5237 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5238 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5239 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5240 | If there is a base register, we add it to $at after the | |
5241 | lui instruction. If there is a constant, we always use | |
5242 | the last case. */ | |
7a15a226 | 5243 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET |
85ce5635 | 5244 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
670a50eb | 5245 | { |
0dd2d296 ILT |
5246 | p = NULL; |
5247 | used_at = 1; | |
670a50eb ILT |
5248 | } |
5249 | else | |
0dd2d296 ILT |
5250 | { |
5251 | int off; | |
5252 | ||
5253 | if (breg == 0) | |
5254 | { | |
8ea7f4e8 | 5255 | frag_grow (28); |
0dd2d296 ILT |
5256 | tempreg = GP; |
5257 | off = 0; | |
5258 | used_at = 0; | |
5259 | } | |
5260 | else | |
5261 | { | |
8ea7f4e8 | 5262 | frag_grow (36); |
0dd2d296 | 5263 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
3c83da8a | 5264 | mips_opts.isa < 3 ? "addu" : "daddu", |
0dd2d296 ILT |
5265 | "d,v,t", AT, breg, GP); |
5266 | tempreg = AT; | |
5267 | off = 4; | |
5268 | used_at = 1; | |
5269 | } | |
5270 | ||
efec4a28 | 5271 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5272 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5273 | coproc ? treg + 1 : treg, | |
5274 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5275 | offset_expr.X_add_number += 4; | |
55933a58 ILT |
5276 | |
5277 | /* Set mips_optimize to 2 to avoid inserting an | |
5278 | undesired nop. */ | |
5279 | hold_mips_optimize = mips_optimize; | |
5280 | mips_optimize = 2; | |
efec4a28 | 5281 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5282 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5283 | coproc ? treg : treg + 1, | |
5284 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
55933a58 ILT |
5285 | mips_optimize = hold_mips_optimize; |
5286 | ||
0dd2d296 ILT |
5287 | p = frag_var (rs_machine_dependent, 12 + off, 0, |
5288 | RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1, | |
3c83da8a | 5289 | used_at && mips_opts.noat), |
f59fb6ca | 5290 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 | 5291 | (char *) NULL); |
777ad64d ILT |
5292 | |
5293 | /* We just generated two relocs. When tc_gen_reloc | |
5294 | handles this case, it will skip the first reloc and | |
5295 | handle the second. The second reloc already has an | |
5296 | extra addend of 4, which we added above. We must | |
5297 | subtract it out, and then subtract another 4 to make | |
5298 | the first reloc come out right. The second reloc | |
5299 | will come out right because we are going to add 4 to | |
5300 | offset_expr when we build its instruction below. */ | |
5301 | offset_expr.X_add_number -= 8; | |
0dd2d296 ILT |
5302 | offset_expr.X_op = O_constant; |
5303 | } | |
5304 | macro_build_lui (p, &icnt, &offset_expr, AT); | |
5305 | if (p != NULL) | |
5306 | p += 4; | |
5307 | if (breg != 0) | |
5308 | { | |
5309 | macro_build (p, &icnt, (expressionS *) NULL, | |
3c83da8a | 5310 | mips_opts.isa < 3 ? "addu" : "daddu", |
0dd2d296 ILT |
5311 | "d,v,t", AT, breg, AT); |
5312 | if (p != NULL) | |
5313 | p += 4; | |
5314 | } | |
efec4a28 | 5315 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5316 | macro_build (p, &icnt, &offset_expr, s, fmt, |
5317 | coproc ? treg + 1 : treg, | |
5318 | (int) BFD_RELOC_LO16, AT); | |
5319 | if (p != NULL) | |
5320 | p += 4; | |
5321 | /* FIXME: How do we handle overflow here? */ | |
5322 | offset_expr.X_add_number += 4; | |
efec4a28 | 5323 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5324 | macro_build (p, &icnt, &offset_expr, s, fmt, |
5325 | coproc ? treg : treg + 1, | |
5326 | (int) BFD_RELOC_LO16, AT); | |
5327 | } | |
fb251650 | 5328 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
670a50eb | 5329 | { |
0dd2d296 ILT |
5330 | int off; |
5331 | ||
5332 | /* If this is a reference to an external symbol, we want | |
5333 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5334 | nop | |
5335 | <op> $treg,0($at) | |
5336 | <op> $treg+1,4($at) | |
5337 | Otherwise we want | |
5338 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5339 | nop | |
5340 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5341 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5342 | If there is a base register we add it to $at before the | |
5343 | lwc1 instructions. If there is a constant we include it | |
5344 | in the lwc1 instructions. */ | |
5345 | used_at = 1; | |
5346 | expr1.X_add_number = offset_expr.X_add_number; | |
5347 | offset_expr.X_add_number = 0; | |
5348 | if (expr1.X_add_number < -0x8000 | |
5349 | || expr1.X_add_number >= 0x8000 - 4) | |
5350 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
5351 | if (breg == 0) | |
5352 | off = 0; | |
5353 | else | |
5354 | off = 4; | |
8ea7f4e8 | 5355 | frag_grow (24 + off); |
0dd2d296 | 5356 | macro_build ((char *) NULL, &icnt, &offset_expr, |
3c83da8a | 5357 | mips_opts.isa < 3 ? "lw" : "ld", |
0dd2d296 ILT |
5358 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); |
5359 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
670a50eb | 5360 | if (breg != 0) |
0dd2d296 | 5361 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
3c83da8a | 5362 | mips_opts.isa < 3 ? "addu" : "daddu", |
0dd2d296 | 5363 | "d,v,t", AT, breg, AT); |
efec4a28 | 5364 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5365 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5366 | coproc ? treg + 1 : treg, | |
5367 | (int) BFD_RELOC_LO16, AT); | |
5368 | expr1.X_add_number += 4; | |
55933a58 ILT |
5369 | |
5370 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5371 | nop. */ | |
5372 | hold_mips_optimize = mips_optimize; | |
5373 | mips_optimize = 2; | |
efec4a28 | 5374 | /* Itbl support may require additional care here. */ |
0dd2d296 ILT |
5375 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5376 | coproc ? treg : treg + 1, | |
5377 | (int) BFD_RELOC_LO16, AT); | |
55933a58 ILT |
5378 | mips_optimize = hold_mips_optimize; |
5379 | ||
0dd2d296 ILT |
5380 | (void) frag_var (rs_machine_dependent, 0, 0, |
5381 | RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0), | |
f59fb6ca | 5382 | offset_expr.X_add_symbol, (offsetT) 0, |
0dd2d296 | 5383 | (char *) NULL); |
8358c818 | 5384 | } |
fb251650 ILT |
5385 | else if (mips_pic == SVR4_PIC) |
5386 | { | |
5387 | int gpdel, off; | |
5388 | ||
5389 | /* If this is a reference to an external symbol, we want | |
5390 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5391 | addu $at,$at,$gp | |
5392 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
5393 | nop | |
5394 | <op> $treg,0($at) | |
5395 | <op> $treg+1,4($at) | |
5396 | Otherwise we want | |
5397 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5398 | nop | |
5399 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5400 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5401 | If there is a base register we add it to $at before the | |
5402 | lwc1 instructions. If there is a constant we include it | |
5403 | in the lwc1 instructions. */ | |
5404 | used_at = 1; | |
5405 | expr1.X_add_number = offset_expr.X_add_number; | |
5406 | offset_expr.X_add_number = 0; | |
5407 | if (expr1.X_add_number < -0x8000 | |
5408 | || expr1.X_add_number >= 0x8000 - 4) | |
5409 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
5410 | if (reg_needs_delay (GP)) | |
5411 | gpdel = 4; | |
5412 | else | |
5413 | gpdel = 0; | |
5414 | if (breg == 0) | |
5415 | off = 0; | |
5416 | else | |
5417 | off = 4; | |
5418 | frag_grow (56); | |
5419 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
5420 | AT, (int) BFD_RELOC_MIPS_GOT_HI16); | |
5421 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3c83da8a | 5422 | mips_opts.isa < 3 ? "addu" : "daddu", |
fb251650 ILT |
5423 | "d,v,t", AT, AT, GP); |
5424 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3c83da8a | 5425 | mips_opts.isa < 3 ? "lw" : "ld", |
fb251650 ILT |
5426 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT); |
5427 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
5428 | if (breg != 0) | |
5429 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3c83da8a | 5430 | mips_opts.isa < 3 ? "addu" : "daddu", |
fb251650 | 5431 | "d,v,t", AT, breg, AT); |
efec4a28 | 5432 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
5433 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5434 | coproc ? treg + 1 : treg, | |
5435 | (int) BFD_RELOC_LO16, AT); | |
5436 | expr1.X_add_number += 4; | |
5437 | ||
5438 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5439 | nop. */ | |
5440 | hold_mips_optimize = mips_optimize; | |
5441 | mips_optimize = 2; | |
efec4a28 | 5442 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
5443 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
5444 | coproc ? treg : treg + 1, | |
5445 | (int) BFD_RELOC_LO16, AT); | |
5446 | mips_optimize = hold_mips_optimize; | |
5447 | expr1.X_add_number -= 4; | |
5448 | ||
5449 | p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0, | |
5450 | RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel, | |
5451 | 8 + gpdel + off, 1, 0), | |
f59fb6ca | 5452 | offset_expr.X_add_symbol, (offsetT) 0, |
fb251650 ILT |
5453 | (char *) NULL); |
5454 | if (gpdel > 0) | |
5455 | { | |
5456 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5457 | p += 4; | |
5458 | } | |
5459 | macro_build (p, &icnt, &offset_expr, | |
3c83da8a | 5460 | mips_opts.isa < 3 ? "lw" : "ld", |
fb251650 ILT |
5461 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); |
5462 | p += 4; | |
5463 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5464 | p += 4; | |
5465 | if (breg != 0) | |
5466 | { | |
5467 | macro_build (p, &icnt, (expressionS *) NULL, | |
3c83da8a | 5468 | mips_opts.isa < 3 ? "addu" : "daddu", |
fb251650 ILT |
5469 | "d,v,t", AT, breg, AT); |
5470 | p += 4; | |
5471 | } | |
efec4a28 | 5472 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
5473 | macro_build (p, &icnt, &expr1, s, fmt, |
5474 | coproc ? treg + 1 : treg, | |
5475 | (int) BFD_RELOC_LO16, AT); | |
5476 | p += 4; | |
5477 | expr1.X_add_number += 4; | |
5478 | ||
5479 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5480 | nop. */ | |
5481 | hold_mips_optimize = mips_optimize; | |
5482 | mips_optimize = 2; | |
efec4a28 | 5483 | /* Itbl support may require additional care here. */ |
fb251650 ILT |
5484 | macro_build (p, &icnt, &expr1, s, fmt, |
5485 | coproc ? treg : treg + 1, | |
5486 | (int) BFD_RELOC_LO16, AT); | |
5487 | mips_optimize = hold_mips_optimize; | |
5488 | } | |
d9aba805 ILT |
5489 | else if (mips_pic == EMBEDDED_PIC) |
5490 | { | |
5491 | /* If there is no base register, we use | |
5492 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
5493 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
5494 | If we have a base register, we use | |
5495 | addu $at,$breg,$gp | |
5496 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
5497 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
5498 | */ | |
5499 | if (breg == 0) | |
5500 | { | |
5501 | tempreg = GP; | |
5502 | used_at = 0; | |
5503 | } | |
5504 | else | |
5505 | { | |
5506 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3c83da8a | 5507 | mips_opts.isa < 3 ? "addu" : "daddu", |
d9aba805 ILT |
5508 | "d,v,t", AT, breg, GP); |
5509 | tempreg = AT; | |
5510 | used_at = 1; | |
5511 | } | |
5512 | ||
efec4a28 | 5513 | /* Itbl support may require additional care here. */ |
d9aba805 ILT |
5514 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5515 | coproc ? treg + 1 : treg, | |
5516 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5517 | offset_expr.X_add_number += 4; | |
efec4a28 | 5518 | /* Itbl support may require additional care here. */ |
d9aba805 ILT |
5519 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
5520 | coproc ? treg : treg + 1, | |
5521 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5522 | } | |
5523 | else | |
5524 | abort (); | |
0dd2d296 ILT |
5525 | |
5526 | if (! used_at) | |
5527 | return; | |
5528 | ||
5529 | break; | |
5530 | ||
5531 | case M_LD_OB: | |
5532 | s = "lw"; | |
5533 | goto sd_ob; | |
5534 | case M_SD_OB: | |
5535 | s = "sw"; | |
5536 | sd_ob: | |
3c83da8a | 5537 | assert (mips_opts.isa < 3); |
0dd2d296 ILT |
5538 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
5539 | (int) BFD_RELOC_LO16, breg); | |
5540 | offset_expr.X_add_number += 4; | |
5541 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1, | |
5542 | (int) BFD_RELOC_LO16, breg); | |
670a50eb | 5543 | return; |
efec4a28 DP |
5544 | |
5545 | /* New code added to support COPZ instructions. | |
5546 | This code builds table entries out of the macros in mip_opcodes. | |
5547 | R4000 uses interlocks to handle coproc delays. | |
5548 | Other chips (like the R3000) require nops to be inserted for delays. | |
5549 | ||
5550 | FIXME: Currently, we require that the user handle delays. | |
5551 | In order to fill delay slots for non-interlocked chips, | |
5552 | we must have a way to specify delays based on the coprocessor. | |
5553 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
5554 | What are the side-effects of the cop instruction? | |
5555 | What cache support might we have and what are its effects? | |
5556 | Both coprocessor & memory require delays. how long??? | |
5557 | What registers are read/set/modified? | |
5558 | ||
5559 | If an itbl is provided to interpret cop instructions, | |
5560 | this knowledge can be encoded in the itbl spec. */ | |
5561 | ||
5562 | case M_COP0: | |
5563 | s = "cop0"; | |
5564 | goto copz; | |
5565 | case M_COP1: | |
5566 | s = "cop1"; | |
5567 | goto copz; | |
5568 | case M_COP2: | |
5569 | s = "cop2"; | |
5570 | goto copz; | |
5571 | case M_COP3: | |
5572 | s = "cop3"; | |
5573 | copz: | |
5574 | /* For now we just do C (same as Cz). */ | |
9218cee0 | 5575 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "C"); |
efec4a28 DP |
5576 | return; |
5577 | ||
917fae09 SS |
5578 | #ifdef LOSING_COMPILER |
5579 | default: | |
efec4a28 DP |
5580 | /* Try and see if this is a new itbl instruction. |
5581 | This code builds table entries out of the macros in mip_opcodes. | |
5582 | FIXME: For now we just assemble the expression and pass it's | |
5583 | value along as a 32-bit immediate. | |
5584 | We may want to have the assembler assemble this value, | |
5585 | so that we gain the assembler's knowledge of delay slots, | |
5586 | symbols, etc. | |
5587 | Would it be more efficient to use mask (id) here? */ | |
5588 | if (itbl_have_entries | |
9218cee0 | 5589 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
efec4a28 DP |
5590 | { |
5591 | s = ip->insn_mo->name; | |
5592 | s2 = "cop3"; | |
9218cee0 | 5593 | coproc = ITBL_DECODE_PNUM (immed_expr);; |
efec4a28 DP |
5594 | macro_build ((char *) NULL, &icnt, &immed_expr, s, "C"); |
5595 | return; | |
5596 | } | |
917fae09 SS |
5597 | macro2 (ip); |
5598 | return; | |
5599 | } | |
3c83da8a | 5600 | if (mips_opts.noat) |
917fae09 SS |
5601 | as_warn ("Macro used $at after \".set noat\""); |
5602 | } | |
5603 | ||
5604 | static void | |
5605 | macro2 (ip) | |
5606 | struct mips_cl_insn *ip; | |
5607 | { | |
5608 | register int treg, sreg, dreg, breg; | |
5609 | int tempreg; | |
5610 | int mask; | |
5611 | int icnt = 0; | |
5612 | int used_at; | |
5613 | expressionS expr1; | |
5614 | const char *s; | |
5615 | const char *s2; | |
5616 | const char *fmt; | |
5617 | int likely = 0; | |
5618 | int dbl = 0; | |
5619 | int coproc = 0; | |
adcf2b9d ILT |
5620 | int lr = 0; |
5621 | int off; | |
917fae09 SS |
5622 | offsetT maxnum; |
5623 | bfd_reloc_code_real_type r; | |
5624 | char *p; | |
5625 | ||
5626 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
5627 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
5628 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
5629 | mask = ip->insn_mo->mask; | |
5630 | ||
5631 | expr1.X_op = O_constant; | |
5632 | expr1.X_op_symbol = NULL; | |
5633 | expr1.X_add_symbol = NULL; | |
5634 | expr1.X_add_number = 1; | |
5635 | ||
5636 | switch (mask) | |
5637 | { | |
5638 | #endif /* LOSING_COMPILER */ | |
3d3c5039 | 5639 | |
8358c818 ILT |
5640 | case M_DMUL: |
5641 | dbl = 1; | |
3d3c5039 | 5642 | case M_MUL: |
0dd2d296 | 5643 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
5644 | dbl ? "dmultu" : "multu", |
5645 | "s,t", sreg, treg); | |
0dd2d296 | 5646 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
670a50eb | 5647 | return; |
3d3c5039 | 5648 | |
8358c818 ILT |
5649 | case M_DMUL_I: |
5650 | dbl = 1; | |
3d3c5039 | 5651 | case M_MUL_I: |
8358c818 ILT |
5652 | /* The MIPS assembler some times generates shifts and adds. I'm |
5653 | not trying to be that fancy. GCC should do this for us | |
5654 | anyway. */ | |
d8a1c247 | 5655 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 5656 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
5657 | dbl ? "dmult" : "mult", |
5658 | "s,t", sreg, AT); | |
0dd2d296 | 5659 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
670a50eb | 5660 | break; |
3d3c5039 | 5661 | |
8358c818 ILT |
5662 | case M_DMULO: |
5663 | dbl = 1; | |
5664 | case M_MULO: | |
fbcfacb7 | 5665 | mips_emit_delays (true); |
3c83da8a | 5666 | ++mips_opts.noreorder; |
0dd2d296 ILT |
5667 | mips_any_noreorder = 1; |
5668 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
5669 | dbl ? "dmult" : "mult", |
5670 | "s,t", sreg, treg); | |
0dd2d296 ILT |
5671 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
5672 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
5673 | dbl ? "dsra32" : "sra", |
5674 | "d,w,<", dreg, dreg, 31); | |
0dd2d296 | 5675 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); |
8ea7f4e8 ILT |
5676 | if (mips_trap) |
5677 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", dreg, AT); | |
5678 | else | |
5679 | { | |
5680 | expr1.X_add_number = 8; | |
5681 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg, AT); | |
5682 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
5683 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
5684 | } | |
3c83da8a | 5685 | --mips_opts.noreorder; |
0dd2d296 | 5686 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
8358c818 ILT |
5687 | break; |
5688 | ||
5689 | case M_DMULOU: | |
5690 | dbl = 1; | |
5691 | case M_MULOU: | |
fbcfacb7 | 5692 | mips_emit_delays (true); |
3c83da8a | 5693 | ++mips_opts.noreorder; |
0dd2d296 ILT |
5694 | mips_any_noreorder = 1; |
5695 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
5696 | dbl ? "dmultu" : "multu", |
5697 | "s,t", sreg, treg); | |
0dd2d296 ILT |
5698 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); |
5699 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); | |
8ea7f4e8 ILT |
5700 | if (mips_trap) |
5701 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", AT, 0); | |
5702 | else | |
5703 | { | |
5704 | expr1.X_add_number = 8; | |
5705 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0); | |
5706 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
5707 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
5708 | } | |
3c83da8a | 5709 | --mips_opts.noreorder; |
8358c818 ILT |
5710 | break; |
5711 | ||
3d3c5039 | 5712 | case M_ROL: |
0dd2d296 ILT |
5713 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); |
5714 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", AT, sreg, AT); | |
5715 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", dreg, sreg, | |
5716 | treg); | |
5717 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
670a50eb | 5718 | break; |
3d3c5039 ILT |
5719 | |
5720 | case M_ROL_I: | |
5c6f5923 GRK |
5721 | if (imm_expr.X_op != O_constant) |
5722 | as_bad ("rotate count too large"); | |
0dd2d296 | 5723 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", AT, sreg, |
a40aee38 | 5724 | (int) (imm_expr.X_add_number & 0x1f)); |
0dd2d296 | 5725 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, |
a40aee38 | 5726 | (int) ((0 - imm_expr.X_add_number) & 0x1f)); |
0dd2d296 | 5727 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); |
670a50eb | 5728 | break; |
3d3c5039 ILT |
5729 | |
5730 | case M_ROR: | |
0dd2d296 ILT |
5731 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); |
5732 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", AT, sreg, AT); | |
5733 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", dreg, sreg, | |
5734 | treg); | |
5735 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
670a50eb | 5736 | break; |
3d3c5039 ILT |
5737 | |
5738 | case M_ROR_I: | |
5c6f5923 GRK |
5739 | if (imm_expr.X_op != O_constant) |
5740 | as_bad ("rotate count too large"); | |
0dd2d296 | 5741 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, sreg, |
a40aee38 | 5742 | (int) (imm_expr.X_add_number & 0x1f)); |
0dd2d296 | 5743 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", dreg, sreg, |
a40aee38 | 5744 | (int) ((0 - imm_expr.X_add_number) & 0x1f)); |
0dd2d296 | 5745 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); |
670a50eb | 5746 | break; |
3d3c5039 ILT |
5747 | |
5748 | case M_S_DOB: | |
3c83da8a | 5749 | assert (mips_opts.isa < 2); |
9a7d824a ILT |
5750 | /* Even on a big endian machine $fn comes before $fn+1. We have |
5751 | to adjust when storing to memory. */ | |
0dd2d296 | 5752 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
b9129c6f | 5753 | target_big_endian ? treg + 1 : treg, |
9226253a | 5754 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 5755 | offset_expr.X_add_number += 4; |
0dd2d296 | 5756 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
b9129c6f | 5757 | target_big_endian ? treg : treg + 1, |
9226253a | 5758 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 5759 | return; |
3d3c5039 | 5760 | |
3d3c5039 | 5761 | case M_SEQ: |
670a50eb | 5762 | if (sreg == 0) |
0dd2d296 ILT |
5763 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
5764 | treg, (int) BFD_RELOC_LO16); | |
670a50eb | 5765 | else if (treg == 0) |
0dd2d296 ILT |
5766 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
5767 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb ILT |
5768 | else |
5769 | { | |
0dd2d296 ILT |
5770 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
5771 | sreg, treg); | |
5772 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
5773 | dreg, (int) BFD_RELOC_LO16); | |
3d3c5039 | 5774 | } |
670a50eb | 5775 | return; |
3d3c5039 ILT |
5776 | |
5777 | case M_SEQ_I: | |
5c6f5923 | 5778 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
670a50eb | 5779 | { |
0dd2d296 ILT |
5780 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
5781 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5782 | return; |
3d3c5039 | 5783 | } |
670a50eb ILT |
5784 | if (sreg == 0) |
5785 | { | |
9a7d824a | 5786 | as_warn ("Instruction %s: result is always false", |
6e8dda9c | 5787 | ip->insn_mo->name); |
0dd2d296 | 5788 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
670a50eb | 5789 | return; |
3d3c5039 | 5790 | } |
5c6f5923 GRK |
5791 | if (imm_expr.X_op == O_constant |
5792 | && imm_expr.X_add_number >= 0 | |
5793 | && imm_expr.X_add_number < 0x10000) | |
670a50eb | 5794 | { |
0dd2d296 ILT |
5795 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, |
5796 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5797 | used_at = 0; |
6e8dda9c | 5798 | } |
5c6f5923 GRK |
5799 | else if (imm_expr.X_op == O_constant |
5800 | && imm_expr.X_add_number > -0x8000 | |
5801 | && imm_expr.X_add_number < 0) | |
6e8dda9c ILT |
5802 | { |
5803 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 5804 | macro_build ((char *) NULL, &icnt, &imm_expr, |
3c83da8a | 5805 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
9226253a ILT |
5806 | "t,r,j", dreg, sreg, |
5807 | (int) BFD_RELOC_LO16); | |
6e8dda9c ILT |
5808 | used_at = 0; |
5809 | } | |
5810 | else | |
5811 | { | |
d8a1c247 | 5812 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
5813 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
5814 | sreg, AT); | |
670a50eb ILT |
5815 | used_at = 1; |
5816 | } | |
0dd2d296 | 5817 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg, |
9226253a | 5818 | (int) BFD_RELOC_LO16); |
670a50eb ILT |
5819 | if (used_at) |
5820 | break; | |
5821 | return; | |
3d3c5039 ILT |
5822 | |
5823 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
670a50eb ILT |
5824 | s = "slt"; |
5825 | goto sge; | |
3d3c5039 | 5826 | case M_SGEU: |
670a50eb | 5827 | s = "sltu"; |
3d3c5039 | 5828 | sge: |
0dd2d296 ILT |
5829 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, sreg, treg); |
5830 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 5831 | (int) BFD_RELOC_LO16); |
670a50eb | 5832 | return; |
3d3c5039 | 5833 | |
670a50eb | 5834 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ |
3d3c5039 | 5835 | case M_SGEU_I: |
5c6f5923 GRK |
5836 | if (imm_expr.X_op == O_constant |
5837 | && imm_expr.X_add_number >= -0x8000 | |
5838 | && imm_expr.X_add_number < 0x8000) | |
670a50eb | 5839 | { |
0dd2d296 | 5840 | macro_build ((char *) NULL, &icnt, &expr1, |
6e8dda9c | 5841 | mask == M_SGE_I ? "slti" : "sltiu", |
9226253a | 5842 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb ILT |
5843 | used_at = 0; |
5844 | } | |
5845 | else | |
5846 | { | |
d8a1c247 | 5847 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 5848 | macro_build ((char *) NULL, &icnt, NULL, |
6e8dda9c ILT |
5849 | mask == M_SGE_I ? "slt" : "sltu", |
5850 | "d,v,t", dreg, sreg, AT); | |
670a50eb ILT |
5851 | used_at = 1; |
5852 | } | |
0dd2d296 | 5853 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
9226253a | 5854 | (int) BFD_RELOC_LO16); |
670a50eb ILT |
5855 | if (used_at) |
5856 | break; | |
5857 | return; | |
3d3c5039 ILT |
5858 | |
5859 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
670a50eb ILT |
5860 | s = "slt"; |
5861 | goto sgt; | |
3d3c5039 | 5862 | case M_SGTU: |
670a50eb | 5863 | s = "sltu"; |
3d3c5039 | 5864 | sgt: |
0dd2d296 | 5865 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); |
670a50eb | 5866 | return; |
3d3c5039 | 5867 | |
670a50eb ILT |
5868 | case M_SGT_I: /* sreg > I <==> I < sreg */ |
5869 | s = "slt"; | |
5870 | goto sgti; | |
3d3c5039 | 5871 | case M_SGTU_I: |
670a50eb | 5872 | s = "sltu"; |
3d3c5039 | 5873 | sgti: |
d8a1c247 | 5874 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 5875 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); |
670a50eb | 5876 | break; |
3d3c5039 | 5877 | |
670a50eb ILT |
5878 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
5879 | s = "slt"; | |
5880 | goto sle; | |
3d3c5039 | 5881 | case M_SLEU: |
670a50eb | 5882 | s = "sltu"; |
3d3c5039 | 5883 | sle: |
0dd2d296 ILT |
5884 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); |
5885 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 5886 | (int) BFD_RELOC_LO16); |
670a50eb | 5887 | return; |
3d3c5039 | 5888 | |
670a50eb ILT |
5889 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
5890 | s = "slt"; | |
5891 | goto slei; | |
3d3c5039 | 5892 | case M_SLEU_I: |
670a50eb | 5893 | s = "sltu"; |
3d3c5039 | 5894 | slei: |
d8a1c247 | 5895 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
5896 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); |
5897 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 5898 | (int) BFD_RELOC_LO16); |
670a50eb | 5899 | break; |
3d3c5039 ILT |
5900 | |
5901 | case M_SLT_I: | |
5c6f5923 GRK |
5902 | if (imm_expr.X_op == O_constant |
5903 | && imm_expr.X_add_number >= -0x8000 | |
5904 | && imm_expr.X_add_number < 0x8000) | |
670a50eb | 5905 | { |
0dd2d296 ILT |
5906 | macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j", |
5907 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5908 | return; |
3d3c5039 | 5909 | } |
d8a1c247 | 5910 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 5911 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", dreg, sreg, AT); |
670a50eb | 5912 | break; |
3d3c5039 ILT |
5913 | |
5914 | case M_SLTU_I: | |
5c6f5923 GRK |
5915 | if (imm_expr.X_op == O_constant |
5916 | && imm_expr.X_add_number >= -0x8000 | |
5917 | && imm_expr.X_add_number < 0x8000) | |
670a50eb | 5918 | { |
0dd2d296 ILT |
5919 | macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j", |
5920 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5921 | return; |
3d3c5039 | 5922 | } |
d8a1c247 | 5923 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
5924 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, sreg, |
5925 | AT); | |
670a50eb | 5926 | break; |
3d3c5039 ILT |
5927 | |
5928 | case M_SNE: | |
670a50eb | 5929 | if (sreg == 0) |
0dd2d296 ILT |
5930 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
5931 | treg); | |
670a50eb | 5932 | else if (treg == 0) |
0dd2d296 ILT |
5933 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
5934 | sreg); | |
670a50eb ILT |
5935 | else |
5936 | { | |
0dd2d296 ILT |
5937 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
5938 | sreg, treg); | |
5939 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, | |
5940 | dreg); | |
3d3c5039 | 5941 | } |
670a50eb | 5942 | return; |
3d3c5039 ILT |
5943 | |
5944 | case M_SNE_I: | |
5c6f5923 | 5945 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
670a50eb | 5946 | { |
0dd2d296 ILT |
5947 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
5948 | sreg); | |
670a50eb | 5949 | return; |
3d3c5039 | 5950 | } |
670a50eb ILT |
5951 | if (sreg == 0) |
5952 | { | |
9a7d824a | 5953 | as_warn ("Instruction %s: result is always true", |
6e8dda9c | 5954 | ip->insn_mo->name); |
0dd2d296 | 5955 | macro_build ((char *) NULL, &icnt, &expr1, |
3c83da8a | 5956 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
9226253a | 5957 | "t,r,j", dreg, 0, (int) BFD_RELOC_LO16); |
670a50eb | 5958 | return; |
3d3c5039 | 5959 | } |
5c6f5923 GRK |
5960 | if (imm_expr.X_op == O_constant |
5961 | && imm_expr.X_add_number >= 0 | |
5962 | && imm_expr.X_add_number < 0x10000) | |
670a50eb | 5963 | { |
0dd2d296 ILT |
5964 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", |
5965 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 5966 | used_at = 0; |
6e8dda9c | 5967 | } |
5c6f5923 GRK |
5968 | else if (imm_expr.X_op == O_constant |
5969 | && imm_expr.X_add_number > -0x8000 | |
5970 | && imm_expr.X_add_number < 0) | |
6e8dda9c ILT |
5971 | { |
5972 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 5973 | macro_build ((char *) NULL, &icnt, &imm_expr, |
3c83da8a | 5974 | mips_opts.isa < 3 ? "addiu" : "daddiu", |
9226253a | 5975 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
6e8dda9c ILT |
5976 | used_at = 0; |
5977 | } | |
5978 | else | |
5979 | { | |
d8a1c247 | 5980 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 ILT |
5981 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
5982 | sreg, AT); | |
670a50eb ILT |
5983 | used_at = 1; |
5984 | } | |
0dd2d296 | 5985 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg); |
670a50eb ILT |
5986 | if (used_at) |
5987 | break; | |
5988 | return; | |
3d3c5039 | 5989 | |
8358c818 ILT |
5990 | case M_DSUB_I: |
5991 | dbl = 1; | |
3d3c5039 | 5992 | case M_SUB_I: |
5c6f5923 GRK |
5993 | if (imm_expr.X_op == O_constant |
5994 | && imm_expr.X_add_number > -0x8000 | |
5995 | && imm_expr.X_add_number <= 0x8000) | |
670a50eb ILT |
5996 | { |
5997 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 5998 | macro_build ((char *) NULL, &icnt, &imm_expr, |
8358c818 | 5999 | dbl ? "daddi" : "addi", |
9226253a | 6000 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb | 6001 | return; |
3d3c5039 | 6002 | } |
d8a1c247 | 6003 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 6004 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
6005 | dbl ? "dsub" : "sub", |
6006 | "d,v,t", dreg, sreg, AT); | |
670a50eb | 6007 | break; |
3d3c5039 | 6008 | |
8358c818 ILT |
6009 | case M_DSUBU_I: |
6010 | dbl = 1; | |
3d3c5039 | 6011 | case M_SUBU_I: |
5c6f5923 GRK |
6012 | if (imm_expr.X_op == O_constant |
6013 | && imm_expr.X_add_number > -0x8000 | |
6014 | && imm_expr.X_add_number <= 0x8000) | |
670a50eb ILT |
6015 | { |
6016 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 6017 | macro_build ((char *) NULL, &icnt, &imm_expr, |
8358c818 | 6018 | dbl ? "daddiu" : "addiu", |
9226253a | 6019 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb | 6020 | return; |
3d3c5039 | 6021 | } |
d8a1c247 | 6022 | load_register (&icnt, AT, &imm_expr, dbl); |
0dd2d296 | 6023 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
6024 | dbl ? "dsubu" : "subu", |
6025 | "d,v,t", dreg, sreg, AT); | |
6026 | break; | |
6027 | ||
6028 | case M_TEQ_I: | |
6029 | s = "teq"; | |
6030 | goto trap; | |
6031 | case M_TGE_I: | |
6032 | s = "tge"; | |
6033 | goto trap; | |
6034 | case M_TGEU_I: | |
6035 | s = "tgeu"; | |
6036 | goto trap; | |
6037 | case M_TLT_I: | |
6038 | s = "tlt"; | |
6039 | goto trap; | |
6040 | case M_TLTU_I: | |
6041 | s = "tltu"; | |
6042 | goto trap; | |
6043 | case M_TNE_I: | |
6044 | s = "tne"; | |
6045 | trap: | |
d8a1c247 | 6046 | load_register (&icnt, AT, &imm_expr, 0); |
0dd2d296 | 6047 | macro_build ((char *) NULL, &icnt, NULL, s, "s,t", sreg, AT); |
670a50eb | 6048 | break; |
3d3c5039 ILT |
6049 | |
6050 | case M_TRUNCWD: | |
6051 | case M_TRUNCWS: | |
3c83da8a | 6052 | assert (mips_opts.isa < 2); |
670a50eb ILT |
6053 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
6054 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
6055 | ||
6056 | /* | |
6057 | * Is the double cfc1 instruction a bug in the mips assembler; | |
6058 | * or is there a reason for it? | |
6059 | */ | |
fbcfacb7 | 6060 | mips_emit_delays (true); |
3c83da8a | 6061 | ++mips_opts.noreorder; |
0dd2d296 ILT |
6062 | mips_any_noreorder = 1; |
6063 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
6064 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
6065 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
670a50eb | 6066 | expr1.X_add_number = 3; |
0dd2d296 | 6067 | macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg, |
9226253a | 6068 | (int) BFD_RELOC_LO16); |
670a50eb | 6069 | expr1.X_add_number = 2; |
0dd2d296 | 6070 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT, |
9226253a | 6071 | (int) BFD_RELOC_LO16); |
0dd2d296 ILT |
6072 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", AT, 31); |
6073 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
6074 | macro_build ((char *) NULL, &icnt, NULL, | |
670a50eb | 6075 | mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg); |
0dd2d296 ILT |
6076 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", treg, 31); |
6077 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
3c83da8a | 6078 | --mips_opts.noreorder; |
670a50eb | 6079 | break; |
3d3c5039 ILT |
6080 | |
6081 | case M_ULH: | |
670a50eb ILT |
6082 | s = "lb"; |
6083 | goto ulh; | |
3d3c5039 | 6084 | case M_ULHU: |
670a50eb | 6085 | s = "lbu"; |
3d3c5039 | 6086 | ulh: |
8ea7f4e8 ILT |
6087 | if (offset_expr.X_add_number >= 0x7fff) |
6088 | as_bad ("operand overflow"); | |
670a50eb | 6089 | /* avoid load delay */ |
b9129c6f | 6090 | if (! target_big_endian) |
8ea7f4e8 | 6091 | offset_expr.X_add_number += 1; |
0dd2d296 | 6092 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
9226253a | 6093 | (int) BFD_RELOC_LO16, breg); |
b9129c6f | 6094 | if (! target_big_endian) |
8ea7f4e8 ILT |
6095 | offset_expr.X_add_number -= 1; |
6096 | else | |
6097 | offset_expr.X_add_number += 1; | |
0dd2d296 | 6098 | macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT, |
9226253a | 6099 | (int) BFD_RELOC_LO16, breg); |
0dd2d296 ILT |
6100 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8); |
6101 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT); | |
670a50eb | 6102 | break; |
3d3c5039 | 6103 | |
adcf2b9d ILT |
6104 | case M_ULD: |
6105 | s = "ldl"; | |
6106 | s2 = "ldr"; | |
6107 | off = 7; | |
6108 | goto ulw; | |
3d3c5039 | 6109 | case M_ULW: |
adcf2b9d ILT |
6110 | s = "lwl"; |
6111 | s2 = "lwr"; | |
6112 | off = 3; | |
6113 | ulw: | |
6114 | if (offset_expr.X_add_number >= 0x8000 - off) | |
8ea7f4e8 | 6115 | as_bad ("operand overflow"); |
b9129c6f | 6116 | if (! target_big_endian) |
adcf2b9d ILT |
6117 | offset_expr.X_add_number += off; |
6118 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
9226253a | 6119 | (int) BFD_RELOC_LO16, breg); |
b9129c6f | 6120 | if (! target_big_endian) |
adcf2b9d | 6121 | offset_expr.X_add_number -= off; |
8ea7f4e8 | 6122 | else |
adcf2b9d ILT |
6123 | offset_expr.X_add_number += off; |
6124 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
9226253a | 6125 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 6126 | return; |
3d3c5039 | 6127 | |
adcf2b9d ILT |
6128 | case M_ULD_A: |
6129 | s = "ldl"; | |
6130 | s2 = "ldr"; | |
6131 | off = 7; | |
6132 | goto ulwa; | |
6133 | case M_ULW_A: | |
6134 | s = "lwl"; | |
6135 | s2 = "lwr"; | |
6136 | off = 3; | |
6137 | ulwa: | |
6138 | load_address (&icnt, AT, &offset_expr); | |
c625fc23 JSC |
6139 | if (breg != 0) |
6140 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3c83da8a | 6141 | mips_opts.isa < 3 ? "addu" : "daddu", |
c625fc23 | 6142 | "d,v,t", AT, AT, breg); |
b9129c6f | 6143 | if (! target_big_endian) |
adcf2b9d ILT |
6144 | expr1.X_add_number = off; |
6145 | else | |
6146 | expr1.X_add_number = 0; | |
6147 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
6148 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 6149 | if (! target_big_endian) |
adcf2b9d ILT |
6150 | expr1.X_add_number = 0; |
6151 | else | |
6152 | expr1.X_add_number = off; | |
6153 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
6154 | (int) BFD_RELOC_LO16, AT); | |
6155 | break; | |
6156 | ||
3d3c5039 ILT |
6157 | case M_ULH_A: |
6158 | case M_ULHU_A: | |
0dd2d296 | 6159 | load_address (&icnt, AT, &offset_expr); |
c625fc23 JSC |
6160 | if (breg != 0) |
6161 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3c83da8a | 6162 | mips_opts.isa < 3 ? "addu" : "daddu", |
c625fc23 | 6163 | "d,v,t", AT, AT, breg); |
b9129c6f | 6164 | if (target_big_endian) |
adcf2b9d ILT |
6165 | expr1.X_add_number = 0; |
6166 | macro_build ((char *) NULL, &icnt, &expr1, | |
6167 | mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg, | |
6168 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 6169 | if (target_big_endian) |
adcf2b9d | 6170 | expr1.X_add_number = 1; |
670a50eb | 6171 | else |
adcf2b9d ILT |
6172 | expr1.X_add_number = 0; |
6173 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
6174 | (int) BFD_RELOC_LO16, AT); | |
6175 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, | |
6176 | treg, 8); | |
6177 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
6178 | treg, AT); | |
670a50eb | 6179 | break; |
3d3c5039 ILT |
6180 | |
6181 | case M_USH: | |
8ea7f4e8 ILT |
6182 | if (offset_expr.X_add_number >= 0x7fff) |
6183 | as_bad ("operand overflow"); | |
b9129c6f | 6184 | if (target_big_endian) |
8ea7f4e8 | 6185 | offset_expr.X_add_number += 1; |
0dd2d296 | 6186 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg, |
9226253a | 6187 | (int) BFD_RELOC_LO16, breg); |
0dd2d296 | 6188 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, treg, 8); |
b9129c6f | 6189 | if (target_big_endian) |
8ea7f4e8 ILT |
6190 | offset_expr.X_add_number -= 1; |
6191 | else | |
6192 | offset_expr.X_add_number += 1; | |
0dd2d296 | 6193 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT, |
9226253a | 6194 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 6195 | break; |
3d3c5039 | 6196 | |
adcf2b9d ILT |
6197 | case M_USD: |
6198 | s = "sdl"; | |
6199 | s2 = "sdr"; | |
6200 | off = 7; | |
6201 | goto usw; | |
3d3c5039 | 6202 | case M_USW: |
adcf2b9d ILT |
6203 | s = "swl"; |
6204 | s2 = "swr"; | |
6205 | off = 3; | |
6206 | usw: | |
6207 | if (offset_expr.X_add_number >= 0x8000 - off) | |
8ea7f4e8 | 6208 | as_bad ("operand overflow"); |
b9129c6f | 6209 | if (! target_big_endian) |
adcf2b9d ILT |
6210 | offset_expr.X_add_number += off; |
6211 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
9226253a | 6212 | (int) BFD_RELOC_LO16, breg); |
b9129c6f | 6213 | if (! target_big_endian) |
adcf2b9d | 6214 | offset_expr.X_add_number -= off; |
8ea7f4e8 | 6215 | else |
adcf2b9d ILT |
6216 | offset_expr.X_add_number += off; |
6217 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
9226253a | 6218 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 6219 | return; |
3d3c5039 | 6220 | |
adcf2b9d ILT |
6221 | case M_USD_A: |
6222 | s = "sdl"; | |
6223 | s2 = "sdr"; | |
6224 | off = 7; | |
6225 | goto uswa; | |
3d3c5039 | 6226 | case M_USW_A: |
adcf2b9d ILT |
6227 | s = "swl"; |
6228 | s2 = "swr"; | |
6229 | off = 3; | |
6230 | uswa: | |
0dd2d296 | 6231 | load_address (&icnt, AT, &offset_expr); |
c625fc23 JSC |
6232 | if (breg != 0) |
6233 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3c83da8a | 6234 | mips_opts.isa < 3 ? "addu" : "daddu", |
c625fc23 | 6235 | "d,v,t", AT, AT, breg); |
b9129c6f | 6236 | if (! target_big_endian) |
adcf2b9d | 6237 | expr1.X_add_number = off; |
670a50eb | 6238 | else |
adcf2b9d ILT |
6239 | expr1.X_add_number = 0; |
6240 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
6241 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 6242 | if (! target_big_endian) |
adcf2b9d ILT |
6243 | expr1.X_add_number = 0; |
6244 | else | |
6245 | expr1.X_add_number = off; | |
6246 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
6247 | (int) BFD_RELOC_LO16, AT); | |
6248 | break; | |
6249 | ||
6250 | case M_USH_A: | |
6251 | load_address (&icnt, AT, &offset_expr); | |
c625fc23 JSC |
6252 | if (breg != 0) |
6253 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3c83da8a | 6254 | mips_opts.isa < 3 ? "addu" : "daddu", |
c625fc23 | 6255 | "d,v,t", AT, AT, breg); |
b9129c6f | 6256 | if (! target_big_endian) |
adcf2b9d ILT |
6257 | expr1.X_add_number = 0; |
6258 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
6259 | (int) BFD_RELOC_LO16, AT); | |
6260 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", treg, | |
6261 | treg, 8); | |
b9129c6f | 6262 | if (! target_big_endian) |
adcf2b9d ILT |
6263 | expr1.X_add_number = 1; |
6264 | else | |
6265 | expr1.X_add_number = 0; | |
6266 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
6267 | (int) BFD_RELOC_LO16, AT); | |
b9129c6f | 6268 | if (! target_big_endian) |
adcf2b9d ILT |
6269 | expr1.X_add_number = 0; |
6270 | else | |
6271 | expr1.X_add_number = 1; | |
6272 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
6273 | (int) BFD_RELOC_LO16, AT); | |
6274 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, | |
6275 | treg, 8); | |
6276 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
6277 | treg, AT); | |
670a50eb | 6278 | break; |
3d3c5039 ILT |
6279 | |
6280 | default: | |
9218cee0 ILT |
6281 | /* FIXME: Check if this is one of the itbl macros, since they |
6282 | are added dynamically. */ | |
670a50eb | 6283 | as_bad ("Macro %s not implemented yet", ip->insn_mo->name); |
8358c818 | 6284 | break; |
3d3c5039 | 6285 | } |
3c83da8a | 6286 | if (mips_opts.noat) |
670a50eb | 6287 | as_warn ("Macro used $at after \".set noat\""); |
3d3c5039 ILT |
6288 | } |
6289 | ||
cc5703cd | 6290 | /* Implement macros in mips16 mode. */ |
3d3c5039 | 6291 | |
3d3c5039 | 6292 | static void |
cc5703cd | 6293 | mips16_macro (ip) |
3d3c5039 ILT |
6294 | struct mips_cl_insn *ip; |
6295 | { | |
cc5703cd ILT |
6296 | int mask; |
6297 | int xreg, yreg, zreg, tmp; | |
6298 | int icnt; | |
6299 | expressionS expr1; | |
6300 | int dbl; | |
6301 | const char *s, *s2, *s3; | |
3d3c5039 | 6302 | |
cc5703cd | 6303 | mask = ip->insn_mo->mask; |
3d3c5039 | 6304 | |
cc5703cd ILT |
6305 | xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; |
6306 | yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY; | |
6307 | zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; | |
8358c818 | 6308 | |
cc5703cd | 6309 | icnt = 0; |
8358c818 | 6310 | |
cc5703cd ILT |
6311 | expr1.X_op = O_constant; |
6312 | expr1.X_op_symbol = NULL; | |
6313 | expr1.X_add_symbol = NULL; | |
6314 | expr1.X_add_number = 1; | |
8358c818 | 6315 | |
cc5703cd | 6316 | dbl = 0; |
517078c1 | 6317 | |
cc5703cd ILT |
6318 | switch (mask) |
6319 | { | |
6320 | default: | |
6321 | internalError (); | |
6322 | ||
6323 | case M_DDIV_3: | |
6324 | dbl = 1; | |
6325 | case M_DIV_3: | |
6326 | s = "mflo"; | |
6327 | goto do_div3; | |
6328 | case M_DREM_3: | |
6329 | dbl = 1; | |
6330 | case M_REM_3: | |
6331 | s = "mfhi"; | |
6332 | do_div3: | |
fbcfacb7 | 6333 | mips_emit_delays (true); |
3c83da8a | 6334 | ++mips_opts.noreorder; |
cc5703cd ILT |
6335 | mips_any_noreorder = 1; |
6336 | macro_build ((char *) NULL, &icnt, NULL, | |
6337 | dbl ? "ddiv" : "div", | |
6338 | "0,x,y", xreg, yreg); | |
8a8121d5 | 6339 | expr1.X_add_number = 2; |
cc5703cd | 6340 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); |
cc5703cd ILT |
6341 | macro_build ((char *) NULL, &icnt, NULL, "break", "6", 7); |
6342 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, | |
6343 | since that causes an overflow. We should do that as well, | |
6344 | but I don't see how to do the comparisons without a temporary | |
6345 | register. */ | |
3c83da8a | 6346 | --mips_opts.noreorder; |
cc5703cd ILT |
6347 | macro_build ((char *) NULL, &icnt, NULL, s, "x", zreg); |
6348 | break; | |
6349 | ||
6350 | case M_DIVU_3: | |
6351 | s = "divu"; | |
6352 | s2 = "mflo"; | |
6353 | goto do_divu3; | |
6354 | case M_REMU_3: | |
6355 | s = "divu"; | |
6356 | s2 = "mfhi"; | |
6357 | goto do_divu3; | |
6358 | case M_DDIVU_3: | |
6359 | s = "ddivu"; | |
6360 | s2 = "mflo"; | |
6361 | goto do_divu3; | |
6362 | case M_DREMU_3: | |
6363 | s = "ddivu"; | |
6364 | s2 = "mfhi"; | |
6365 | do_divu3: | |
fbcfacb7 | 6366 | mips_emit_delays (true); |
3c83da8a | 6367 | ++mips_opts.noreorder; |
cc5703cd ILT |
6368 | mips_any_noreorder = 1; |
6369 | macro_build ((char *) NULL, &icnt, NULL, s, "0,x,y", xreg, yreg); | |
8a8121d5 | 6370 | expr1.X_add_number = 2; |
cc5703cd | 6371 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); |
cc5703cd | 6372 | macro_build ((char *) NULL, &icnt, NULL, "break", "6", 7); |
3c83da8a | 6373 | --mips_opts.noreorder; |
cc5703cd ILT |
6374 | macro_build ((char *) NULL, &icnt, NULL, s2, "x", zreg); |
6375 | break; | |
6376 | ||
08438bef ILT |
6377 | case M_DMUL: |
6378 | dbl = 1; | |
6379 | case M_MUL: | |
6380 | macro_build ((char *) NULL, &icnt, NULL, | |
6381 | dbl ? "dmultu" : "multu", | |
6382 | "x,y", xreg, yreg); | |
6383 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "x", zreg); | |
6384 | return; | |
6385 | ||
cc5703cd ILT |
6386 | case M_DSUBU_I: |
6387 | dbl = 1; | |
6388 | goto do_subu; | |
6389 | case M_SUBU_I: | |
6390 | do_subu: | |
5c6f5923 GRK |
6391 | if (imm_expr.X_op != O_constant) |
6392 | as_bad ("Unsupported large constant"); | |
cc5703cd ILT |
6393 | imm_expr.X_add_number = -imm_expr.X_add_number; |
6394 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
6395 | dbl ? "daddiu" : "addiu", | |
6396 | "y,x,4", yreg, xreg); | |
6397 | break; | |
6398 | ||
6399 | case M_SUBU_I_2: | |
5c6f5923 GRK |
6400 | if (imm_expr.X_op != O_constant) |
6401 | as_bad ("Unsupported large constant"); | |
cc5703cd ILT |
6402 | imm_expr.X_add_number = -imm_expr.X_add_number; |
6403 | macro_build ((char *) NULL, &icnt, &imm_expr, "addiu", | |
6404 | "x,k", xreg); | |
6405 | break; | |
6406 | ||
6407 | case M_DSUBU_I_2: | |
5c6f5923 GRK |
6408 | if (imm_expr.X_op != O_constant) |
6409 | as_bad ("Unsupported large constant"); | |
cc5703cd ILT |
6410 | imm_expr.X_add_number = -imm_expr.X_add_number; |
6411 | macro_build ((char *) NULL, &icnt, &imm_expr, "daddiu", | |
6412 | "y,j", yreg); | |
6413 | break; | |
6414 | ||
6415 | case M_BEQ: | |
6416 | s = "cmp"; | |
6417 | s2 = "bteqz"; | |
6418 | goto do_branch; | |
6419 | case M_BNE: | |
6420 | s = "cmp"; | |
6421 | s2 = "btnez"; | |
6422 | goto do_branch; | |
6423 | case M_BLT: | |
6424 | s = "slt"; | |
6425 | s2 = "btnez"; | |
6426 | goto do_branch; | |
6427 | case M_BLTU: | |
6428 | s = "sltu"; | |
6429 | s2 = "btnez"; | |
6430 | goto do_branch; | |
6431 | case M_BLE: | |
6432 | s = "slt"; | |
6433 | s2 = "bteqz"; | |
6434 | goto do_reverse_branch; | |
6435 | case M_BLEU: | |
6436 | s = "sltu"; | |
6437 | s2 = "bteqz"; | |
6438 | goto do_reverse_branch; | |
6439 | case M_BGE: | |
6440 | s = "slt"; | |
6441 | s2 = "bteqz"; | |
6442 | goto do_branch; | |
6443 | case M_BGEU: | |
6444 | s = "sltu"; | |
6445 | s2 = "bteqz"; | |
6446 | goto do_branch; | |
6447 | case M_BGT: | |
6448 | s = "slt"; | |
6449 | s2 = "btnez"; | |
6450 | goto do_reverse_branch; | |
6451 | case M_BGTU: | |
6452 | s = "sltu"; | |
6453 | s2 = "btnez"; | |
6454 | ||
6455 | do_reverse_branch: | |
6456 | tmp = xreg; | |
6457 | xreg = yreg; | |
6458 | yreg = tmp; | |
6459 | ||
6460 | do_branch: | |
6461 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x,y", | |
6462 | xreg, yreg); | |
6463 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
6464 | break; | |
6465 | ||
6466 | case M_BEQ_I: | |
6467 | s = "cmpi"; | |
6468 | s2 = "bteqz"; | |
6469 | s3 = "x,U"; | |
6470 | goto do_branch_i; | |
6471 | case M_BNE_I: | |
6472 | s = "cmpi"; | |
6473 | s2 = "btnez"; | |
6474 | s3 = "x,U"; | |
6475 | goto do_branch_i; | |
6476 | case M_BLT_I: | |
6477 | s = "slti"; | |
6478 | s2 = "btnez"; | |
6479 | s3 = "x,8"; | |
6480 | goto do_branch_i; | |
6481 | case M_BLTU_I: | |
6482 | s = "sltiu"; | |
6483 | s2 = "btnez"; | |
6484 | s3 = "x,8"; | |
6485 | goto do_branch_i; | |
6486 | case M_BLE_I: | |
6487 | s = "slti"; | |
6488 | s2 = "btnez"; | |
6489 | s3 = "x,8"; | |
6490 | goto do_addone_branch_i; | |
6491 | case M_BLEU_I: | |
6492 | s = "sltiu"; | |
6493 | s2 = "btnez"; | |
6494 | s3 = "x,8"; | |
6495 | goto do_addone_branch_i; | |
6496 | case M_BGE_I: | |
6497 | s = "slti"; | |
6498 | s2 = "bteqz"; | |
6499 | s3 = "x,8"; | |
6500 | goto do_branch_i; | |
6501 | case M_BGEU_I: | |
6502 | s = "sltiu"; | |
6503 | s2 = "bteqz"; | |
6504 | s3 = "x,8"; | |
6505 | goto do_branch_i; | |
6506 | case M_BGT_I: | |
6507 | s = "slti"; | |
6508 | s2 = "bteqz"; | |
6509 | s3 = "x,8"; | |
6510 | goto do_addone_branch_i; | |
6511 | case M_BGTU_I: | |
6512 | s = "sltiu"; | |
6513 | s2 = "bteqz"; | |
6514 | s3 = "x,8"; | |
6515 | ||
6516 | do_addone_branch_i: | |
5c6f5923 GRK |
6517 | if (imm_expr.X_op != O_constant) |
6518 | as_bad ("Unsupported large constant"); | |
cc5703cd ILT |
6519 | ++imm_expr.X_add_number; |
6520 | ||
6521 | do_branch_i: | |
6522 | macro_build ((char *) NULL, &icnt, &imm_expr, s, s3, xreg); | |
6523 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
6524 | break; | |
18e0764d ILT |
6525 | |
6526 | case M_ABS: | |
6527 | expr1.X_add_number = 0; | |
6528 | macro_build ((char *) NULL, &icnt, &expr1, "slti", "x,8", yreg); | |
6529 | if (xreg != yreg) | |
6530 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6531 | "move", "y,X", xreg, yreg); | |
6532 | expr1.X_add_number = 2; | |
6533 | macro_build ((char *) NULL, &icnt, &expr1, "bteqz", "p"); | |
6534 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6535 | "neg", "x,w", xreg, xreg); | |
cc5703cd ILT |
6536 | } |
6537 | } | |
6538 | ||
6539 | /* This routine assembles an instruction into its binary format. As a | |
6540 | side effect, it sets one of the global variables imm_reloc or | |
6541 | offset_reloc to the type of relocation to do if one of the operands | |
6542 | is an address expression. */ | |
6543 | ||
6544 | static void | |
6545 | mips_ip (str, ip) | |
6546 | char *str; | |
6547 | struct mips_cl_insn *ip; | |
6548 | { | |
6549 | char *s; | |
6550 | const char *args; | |
6551 | char c; | |
6552 | struct mips_opcode *insn; | |
6553 | char *argsStart; | |
6554 | unsigned int regno; | |
6555 | unsigned int lastregno = 0; | |
6556 | char *s_reset; | |
6557 | ||
6558 | insn_error = NULL; | |
6559 | ||
e2e5acfa | 6560 | for (s = str; *s != '\0' && !isspace(*s); ++s) |
cc5703cd | 6561 | continue; |
1857d1e6 | 6562 | if (isspace (*s)) |
e2e5acfa | 6563 | *s++ = '\0'; |
1857d1e6 | 6564 | |
cc5703cd ILT |
6565 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) |
6566 | { | |
6567 | insn_error = "unrecognized opcode"; | |
6568 | return; | |
6569 | } | |
6570 | argsStart = s; | |
6571 | for (;;) | |
6572 | { | |
6573 | int insn_isa; | |
6574 | ||
6575 | assert (strcmp (insn->name, str) == 0); | |
6576 | ||
6577 | if (insn->pinfo == INSN_MACRO) | |
6578 | insn_isa = insn->match; | |
931a1858 JL |
6579 | else if ((insn->membership & INSN_ISA) == INSN_ISA1) |
6580 | insn_isa = 1; | |
5c6f5923 | 6581 | else if ((insn->membership & INSN_ISA) == INSN_ISA2) |
cc5703cd | 6582 | insn_isa = 2; |
5c6f5923 | 6583 | else if ((insn->membership & INSN_ISA) == INSN_ISA3) |
cc5703cd | 6584 | insn_isa = 3; |
5c6f5923 | 6585 | else if ((insn->membership & INSN_ISA) == INSN_ISA4) |
cc5703cd ILT |
6586 | insn_isa = 4; |
6587 | else | |
931a1858 | 6588 | insn_isa = 15; |
cc5703cd | 6589 | |
3c83da8a | 6590 | if (insn_isa > mips_opts.isa |
931a1858 JL |
6591 | && (insn->pinfo != INSN_MACRO |
6592 | && ((mips_4650 | |
6593 | && (insn->membership & INSN_4650) != INSN_4650) | |
6594 | || (mips_4650 && (insn->pinfo & FP_D)) | |
6595 | || (mips_4010 | |
6596 | && (insn->membership & INSN_4010) != INSN_4010) | |
6597 | || (mips_4100 | |
6598 | && (insn->membership & INSN_4100) != INSN_4100) | |
16262668 | 6599 | /* start-sanitize-r5900 */ |
931a1858 JL |
6600 | || (mips_5900 |
6601 | && (insn->membership & INSN_5900) != INSN_5900) | |
6602 | || (mips_5900 && (insn->pinfo & FP_D)) | |
16262668 | 6603 | /* end-sanitize-r5900 */ |
931a1858 JL |
6604 | || (mips_3900 |
6605 | && (insn->membership & INSN_3900) != INSN_3900)))) | |
cc5703cd ILT |
6606 | { |
6607 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
6608 | && strcmp (insn->name, insn[1].name) == 0) | |
6609 | { | |
6610 | ++insn; | |
6611 | continue; | |
6612 | } | |
3c83da8a | 6613 | if (insn_isa <= mips_opts.isa) |
cc5703cd ILT |
6614 | insn_error = "opcode not supported on this processor"; |
6615 | else | |
6616 | { | |
6617 | static char buf[100]; | |
6618 | ||
6619 | sprintf (buf, "opcode requires -mips%d or greater", insn_isa); | |
6620 | insn_error = buf; | |
6621 | } | |
6622 | return; | |
6623 | } | |
8358c818 | 6624 | |
670a50eb ILT |
6625 | ip->insn_mo = insn; |
6626 | ip->insn_opcode = insn->match; | |
6627 | for (args = insn->args;; ++args) | |
6628 | { | |
6629 | if (*s == ' ') | |
6630 | ++s; | |
6631 | switch (*args) | |
6632 | { | |
6633 | case '\0': /* end of args */ | |
6634 | if (*s == '\0') | |
6635 | return; | |
6636 | break; | |
3d3c5039 ILT |
6637 | |
6638 | case ',': | |
670a50eb ILT |
6639 | if (*s++ == *args) |
6640 | continue; | |
6641 | s--; | |
6642 | switch (*++args) | |
6643 | { | |
3d3c5039 ILT |
6644 | case 'r': |
6645 | case 'v': | |
670a50eb ILT |
6646 | ip->insn_opcode |= lastregno << 21; |
6647 | continue; | |
3d3c5039 ILT |
6648 | |
6649 | case 'w': | |
6650 | case 'W': | |
670a50eb ILT |
6651 | ip->insn_opcode |= lastregno << 16; |
6652 | continue; | |
3d3c5039 ILT |
6653 | |
6654 | case 'V': | |
670a50eb ILT |
6655 | ip->insn_opcode |= lastregno << 11; |
6656 | continue; | |
3d3c5039 | 6657 | } |
670a50eb | 6658 | break; |
3d3c5039 ILT |
6659 | |
6660 | case '(': | |
670a50eb ILT |
6661 | /* handle optional base register. |
6662 | Either the base register is omitted or | |
6663 | we must have a left paren. */ | |
6664 | /* this is dependent on the next operand specifier | |
6665 | is a 'b' for base register */ | |
6666 | assert (args[1] == 'b'); | |
6667 | if (*s == '\0') | |
6668 | return; | |
3d3c5039 | 6669 | |
670a50eb ILT |
6670 | case ')': /* these must match exactly */ |
6671 | if (*s++ == *args) | |
3d3c5039 | 6672 | continue; |
670a50eb ILT |
6673 | break; |
6674 | ||
6675 | case '<': /* must be at least one digit */ | |
6676 | /* | |
6677 | * According to the manual, if the shift amount is greater | |
6678 | * than 31 or less than 0 the the shift amount should be | |
6679 | * mod 32. In reality the mips assembler issues an error. | |
9226253a | 6680 | * We issue a warning and mask out all but the low 5 bits. |
670a50eb ILT |
6681 | */ |
6682 | my_getExpression (&imm_expr, s); | |
6683 | check_absolute_expr (ip, &imm_expr); | |
6684 | if ((unsigned long) imm_expr.X_add_number > 31) | |
6685 | { | |
58d4951d ILT |
6686 | as_warn ("Improper shift amount (%ld)", |
6687 | (long) imm_expr.X_add_number); | |
9226253a | 6688 | imm_expr.X_add_number = imm_expr.X_add_number & 0x1f; |
670a50eb ILT |
6689 | } |
6690 | ip->insn_opcode |= imm_expr.X_add_number << 6; | |
5ac34ac3 | 6691 | imm_expr.X_op = O_absent; |
670a50eb ILT |
6692 | s = expr_end; |
6693 | continue; | |
6694 | ||
56c96faa ILT |
6695 | case '>': /* shift amount minus 32 */ |
6696 | my_getExpression (&imm_expr, s); | |
6697 | check_absolute_expr (ip, &imm_expr); | |
6698 | if ((unsigned long) imm_expr.X_add_number < 32 | |
6699 | || (unsigned long) imm_expr.X_add_number > 63) | |
6700 | break; | |
6701 | ip->insn_opcode |= (imm_expr.X_add_number - 32) << 6; | |
6702 | imm_expr.X_op = O_absent; | |
6703 | s = expr_end; | |
6704 | continue; | |
6705 | ||
9226253a | 6706 | case 'k': /* cache code */ |
d8a1c247 | 6707 | case 'h': /* prefx code */ |
9226253a ILT |
6708 | my_getExpression (&imm_expr, s); |
6709 | check_absolute_expr (ip, &imm_expr); | |
6710 | if ((unsigned long) imm_expr.X_add_number > 31) | |
6711 | { | |
d8a1c247 KR |
6712 | as_warn ("Invalid value for `%s' (%lu)", |
6713 | ip->insn_mo->name, | |
9226253a ILT |
6714 | (unsigned long) imm_expr.X_add_number); |
6715 | imm_expr.X_add_number &= 0x1f; | |
6716 | } | |
d8a1c247 KR |
6717 | if (*args == 'k') |
6718 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE; | |
6719 | else | |
6720 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX; | |
9226253a ILT |
6721 | imm_expr.X_op = O_absent; |
6722 | s = expr_end; | |
6723 | continue; | |
6724 | ||
670a50eb ILT |
6725 | case 'c': /* break code */ |
6726 | my_getExpression (&imm_expr, s); | |
6727 | check_absolute_expr (ip, &imm_expr); | |
6728 | if ((unsigned) imm_expr.X_add_number > 1023) | |
58d4951d ILT |
6729 | as_warn ("Illegal break code (%ld)", |
6730 | (long) imm_expr.X_add_number); | |
670a50eb | 6731 | ip->insn_opcode |= imm_expr.X_add_number << 16; |
5ac34ac3 | 6732 | imm_expr.X_op = O_absent; |
670a50eb ILT |
6733 | s = expr_end; |
6734 | continue; | |
6735 | ||
918692a5 ILT |
6736 | case 'B': /* syscall code */ |
6737 | my_getExpression (&imm_expr, s); | |
6738 | check_absolute_expr (ip, &imm_expr); | |
6739 | if ((unsigned) imm_expr.X_add_number > 0xfffff) | |
58d4951d ILT |
6740 | as_warn ("Illegal syscall code (%ld)", |
6741 | (long) imm_expr.X_add_number); | |
918692a5 | 6742 | ip->insn_opcode |= imm_expr.X_add_number << 6; |
5ac34ac3 | 6743 | imm_expr.X_op = O_absent; |
918692a5 ILT |
6744 | s = expr_end; |
6745 | continue; | |
6746 | ||
0aa07269 ILT |
6747 | case 'C': /* Coprocessor code */ |
6748 | my_getExpression (&imm_expr, s); | |
6749 | check_absolute_expr (ip, &imm_expr); | |
6750 | if ((unsigned long) imm_expr.X_add_number >= (1<<25)) | |
6751 | { | |
58d4951d ILT |
6752 | as_warn ("Coproccesor code > 25 bits (%ld)", |
6753 | (long) imm_expr.X_add_number); | |
0aa07269 ILT |
6754 | imm_expr.X_add_number &= ((1<<25) - 1); |
6755 | } | |
6756 | ip->insn_opcode |= imm_expr.X_add_number; | |
6757 | imm_expr.X_op = O_absent; | |
6758 | s = expr_end; | |
6759 | continue; | |
6760 | ||
670a50eb ILT |
6761 | case 'b': /* base register */ |
6762 | case 'd': /* destination register */ | |
6763 | case 's': /* source register */ | |
6764 | case 't': /* target register */ | |
6765 | case 'r': /* both target and source */ | |
6766 | case 'v': /* both dest and source */ | |
6767 | case 'w': /* both dest and target */ | |
918692a5 ILT |
6768 | case 'E': /* coprocessor target register */ |
6769 | case 'G': /* coprocessor destination register */ | |
8358c818 | 6770 | case 'x': /* ignore register name */ |
ff3a5c18 | 6771 | case 'z': /* must be zero register */ |
670a50eb ILT |
6772 | s_reset = s; |
6773 | if (s[0] == '$') | |
6774 | { | |
6775 | if (isdigit (s[1])) | |
6776 | { | |
6777 | ++s; | |
6778 | regno = 0; | |
6779 | do | |
6780 | { | |
6781 | regno *= 10; | |
6782 | regno += *s - '0'; | |
6783 | ++s; | |
6784 | } | |
6785 | while (isdigit (*s)); | |
0aa07269 ILT |
6786 | if (regno > 31) |
6787 | as_bad ("Invalid register number (%d)", regno); | |
670a50eb | 6788 | } |
0dd2d296 ILT |
6789 | else if (*args == 'E' || *args == 'G') |
6790 | goto notreg; | |
6791 | else | |
670a50eb | 6792 | { |
0aa07269 ILT |
6793 | if (s[1] == 'f' && s[2] == 'p') |
6794 | { | |
6795 | s += 3; | |
9226253a | 6796 | regno = FP; |
0aa07269 ILT |
6797 | } |
6798 | else if (s[1] == 's' && s[2] == 'p') | |
6799 | { | |
6800 | s += 3; | |
9226253a | 6801 | regno = SP; |
0aa07269 ILT |
6802 | } |
6803 | else if (s[1] == 'g' && s[2] == 'p') | |
6804 | { | |
6805 | s += 3; | |
9226253a | 6806 | regno = GP; |
0aa07269 ILT |
6807 | } |
6808 | else if (s[1] == 'a' && s[2] == 't') | |
6809 | { | |
6810 | s += 3; | |
9226253a | 6811 | regno = AT; |
0aa07269 | 6812 | } |
b2b8c24e ILT |
6813 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') |
6814 | { | |
6815 | s += 4; | |
6816 | regno = KT0; | |
6817 | } | |
6818 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
6819 | { | |
6820 | s += 4; | |
6821 | regno = KT1; | |
6822 | } | |
efec4a28 DP |
6823 | else if (itbl_have_entries) |
6824 | { | |
6825 | char *p, *n; | |
6826 | int r; | |
6827 | ||
6828 | p = s+1; /* advance past '$' */ | |
9218cee0 | 6829 | n = itbl_get_field (&p); /* n is name */ |
efec4a28 DP |
6830 | |
6831 | /* See if this is a register defined in an | |
6832 | itbl entry */ | |
9218cee0 ILT |
6833 | r = itbl_get_reg_val (n); |
6834 | if (r) | |
efec4a28 | 6835 | { |
9218cee0 ILT |
6836 | /* Get_field advances to the start of |
6837 | the next field, so we need to back | |
6838 | rack to the end of the last field. */ | |
efec4a28 | 6839 | if (p) |
9218cee0 | 6840 | s = p - 1; |
efec4a28 | 6841 | else |
9218cee0 | 6842 | s = strchr (s,'\0'); |
efec4a28 DP |
6843 | regno = r; |
6844 | } | |
6845 | else | |
6846 | goto notreg; | |
6847 | } | |
0aa07269 ILT |
6848 | else |
6849 | goto notreg; | |
670a50eb | 6850 | } |
9753202d | 6851 | if (regno == AT |
3c83da8a | 6852 | && ! mips_opts.noat |
9753202d ILT |
6853 | && *args != 'E' |
6854 | && *args != 'G') | |
13fe1379 | 6855 | as_warn ("Used $at without \".set noat\""); |
670a50eb ILT |
6856 | c = *args; |
6857 | if (*s == ' ') | |
6858 | s++; | |
6859 | if (args[1] != *s) | |
6860 | { | |
6861 | if (c == 'r' || c == 'v' || c == 'w') | |
6862 | { | |
6863 | regno = lastregno; | |
6864 | s = s_reset; | |
6865 | args++; | |
6866 | } | |
6867 | } | |
ff3a5c18 ILT |
6868 | /* 'z' only matches $0. */ |
6869 | if (c == 'z' && regno != 0) | |
6870 | break; | |
efec4a28 DP |
6871 | |
6872 | /* Now that we have assembled one operand, we use the args string | |
6873 | * to figure out where it goes in the instruction. */ | |
670a50eb ILT |
6874 | switch (c) |
6875 | { | |
3d3c5039 ILT |
6876 | case 'r': |
6877 | case 's': | |
6878 | case 'v': | |
6879 | case 'b': | |
670a50eb ILT |
6880 | ip->insn_opcode |= regno << 21; |
6881 | break; | |
3d3c5039 | 6882 | case 'd': |
918692a5 | 6883 | case 'G': |
670a50eb ILT |
6884 | ip->insn_opcode |= regno << 11; |
6885 | break; | |
3d3c5039 ILT |
6886 | case 'w': |
6887 | case 't': | |
918692a5 | 6888 | case 'E': |
670a50eb | 6889 | ip->insn_opcode |= regno << 16; |
8358c818 ILT |
6890 | break; |
6891 | case 'x': | |
6892 | /* This case exists because on the r3000 trunc | |
6893 | expands into a macro which requires a gp | |
6894 | register. On the r6000 or r4000 it is | |
6895 | assembled into a single instruction which | |
6896 | ignores the register. Thus the insn version | |
6897 | is MIPS_ISA2 and uses 'x', and the macro | |
6898 | version is MIPS_ISA1 and uses 't'. */ | |
6899 | break; | |
ff3a5c18 ILT |
6900 | case 'z': |
6901 | /* This case is for the div instruction, which | |
6902 | acts differently if the destination argument | |
6903 | is $0. This only matches $0, and is checked | |
6904 | outside the switch. */ | |
6905 | break; | |
efec4a28 DP |
6906 | case 'D': |
6907 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
6908 | break; | |
9218cee0 ILT |
6909 | /* What about all other operands like 'i', which |
6910 | can be specified in the opcode table? */ | |
3d3c5039 | 6911 | } |
670a50eb ILT |
6912 | lastregno = regno; |
6913 | continue; | |
3d3c5039 ILT |
6914 | } |
6915 | notreg: | |
670a50eb ILT |
6916 | switch (*args++) |
6917 | { | |
3d3c5039 ILT |
6918 | case 'r': |
6919 | case 'v': | |
670a50eb ILT |
6920 | ip->insn_opcode |= lastregno << 21; |
6921 | continue; | |
3d3c5039 | 6922 | case 'w': |
670a50eb ILT |
6923 | ip->insn_opcode |= lastregno << 16; |
6924 | continue; | |
3d3c5039 | 6925 | } |
670a50eb | 6926 | break; |
3d3c5039 | 6927 | |
670a50eb ILT |
6928 | case 'D': /* floating point destination register */ |
6929 | case 'S': /* floating point source register */ | |
6930 | case 'T': /* floating point target register */ | |
d8a1c247 | 6931 | case 'R': /* floating point source register */ |
3d3c5039 ILT |
6932 | case 'V': |
6933 | case 'W': | |
670a50eb ILT |
6934 | s_reset = s; |
6935 | if (s[0] == '$' && s[1] == 'f' && isdigit (s[2])) | |
6936 | { | |
6937 | s += 2; | |
6938 | regno = 0; | |
6939 | do | |
6940 | { | |
6941 | regno *= 10; | |
6942 | regno += *s - '0'; | |
6943 | ++s; | |
6944 | } | |
6945 | while (isdigit (*s)); | |
6946 | ||
6947 | if (regno > 31) | |
6948 | as_bad ("Invalid float register number (%d)", regno); | |
6949 | ||
9226253a | 6950 | if ((regno & 1) != 0 |
3c83da8a | 6951 | && mips_opts.isa < 3 |
538034cf ILT |
6952 | && ! (strcmp (str, "mtc1") == 0 |
6953 | || strcmp (str, "mfc1") == 0 | |
6954 | || strcmp (str, "lwc1") == 0 | |
6955 | || strcmp (str, "swc1") == 0 | |
6956 | || strcmp (str, "l.s") == 0 | |
6957 | || strcmp (str, "s.s") == 0)) | |
670a50eb ILT |
6958 | as_warn ("Float register should be even, was %d", |
6959 | regno); | |
6960 | ||
6961 | c = *args; | |
6962 | if (*s == ' ') | |
6963 | s++; | |
6964 | if (args[1] != *s) | |
6965 | { | |
6966 | if (c == 'V' || c == 'W') | |
6967 | { | |
6968 | regno = lastregno; | |
6969 | s = s_reset; | |
6970 | args++; | |
3d3c5039 ILT |
6971 | } |
6972 | } | |
670a50eb ILT |
6973 | switch (c) |
6974 | { | |
3d3c5039 | 6975 | case 'D': |
670a50eb ILT |
6976 | ip->insn_opcode |= regno << 6; |
6977 | break; | |
3d3c5039 ILT |
6978 | case 'V': |
6979 | case 'S': | |
670a50eb ILT |
6980 | ip->insn_opcode |= regno << 11; |
6981 | break; | |
3d3c5039 ILT |
6982 | case 'W': |
6983 | case 'T': | |
670a50eb | 6984 | ip->insn_opcode |= regno << 16; |
d8a1c247 KR |
6985 | break; |
6986 | case 'R': | |
6987 | ip->insn_opcode |= regno << 21; | |
6988 | break; | |
3d3c5039 | 6989 | } |
670a50eb ILT |
6990 | lastregno = regno; |
6991 | continue; | |
3d3c5039 | 6992 | } |
670a50eb ILT |
6993 | switch (*args++) |
6994 | { | |
3d3c5039 | 6995 | case 'V': |
670a50eb ILT |
6996 | ip->insn_opcode |= lastregno << 11; |
6997 | continue; | |
3d3c5039 | 6998 | case 'W': |
670a50eb ILT |
6999 | ip->insn_opcode |= lastregno << 16; |
7000 | continue; | |
3d3c5039 | 7001 | } |
670a50eb | 7002 | break; |
3d3c5039 ILT |
7003 | |
7004 | case 'I': | |
670a50eb | 7005 | my_getExpression (&imm_expr, s); |
9753202d ILT |
7006 | if (imm_expr.X_op != O_big |
7007 | && imm_expr.X_op != O_constant) | |
7008 | insn_error = "absolute expression required"; | |
670a50eb ILT |
7009 | s = expr_end; |
7010 | continue; | |
3d3c5039 ILT |
7011 | |
7012 | case 'A': | |
670a50eb ILT |
7013 | my_getExpression (&offset_expr, s); |
7014 | imm_reloc = BFD_RELOC_32; | |
7015 | s = expr_end; | |
7016 | continue; | |
3d3c5039 ILT |
7017 | |
7018 | case 'F': | |
19ed8960 ILT |
7019 | case 'L': |
7020 | case 'f': | |
7021 | case 'l': | |
7022 | { | |
7023 | int f64; | |
7024 | char *save_in; | |
7025 | char *err; | |
7026 | unsigned char temp[8]; | |
604633ae ILT |
7027 | int len; |
7028 | unsigned int length; | |
19ed8960 ILT |
7029 | segT seg; |
7030 | subsegT subseg; | |
7031 | char *p; | |
7032 | ||
7033 | /* These only appear as the last operand in an | |
7034 | instruction, and every instruction that accepts | |
7035 | them in any variant accepts them in all variants. | |
7036 | This means we don't have to worry about backing out | |
7037 | any changes if the instruction does not match. | |
7038 | ||
7039 | The difference between them is the size of the | |
7040 | floating point constant and where it goes. For 'F' | |
7041 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
7042 | is 32 bits. Where the constant is placed is based | |
7043 | on how the MIPS assembler does things: | |
7044 | F -- .rdata | |
7045 | L -- .lit8 | |
7046 | f -- immediate value | |
7047 | l -- .lit4 | |
0dd2d296 | 7048 | |
55933a58 ILT |
7049 | The .lit4 and .lit8 sections are only used if |
7050 | permitted by the -G argument. | |
7051 | ||
7052 | When generating embedded PIC code, we use the | |
7053 | .lit8 section but not the .lit4 section (we can do | |
7054 | .lit4 inline easily; we need to put .lit8 | |
7055 | somewhere in the data segment, and using .lit8 | |
7056 | permits the linker to eventually combine identical | |
7057 | .lit8 entries). */ | |
19ed8960 ILT |
7058 | |
7059 | f64 = *args == 'F' || *args == 'L'; | |
7060 | ||
7061 | save_in = input_line_pointer; | |
7062 | input_line_pointer = s; | |
604633ae ILT |
7063 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); |
7064 | length = len; | |
19ed8960 ILT |
7065 | s = input_line_pointer; |
7066 | input_line_pointer = save_in; | |
7067 | if (err != NULL && *err != '\0') | |
7068 | { | |
7069 | as_bad ("Bad floating point constant: %s", err); | |
7070 | memset (temp, '\0', sizeof temp); | |
7071 | length = f64 ? 8 : 4; | |
7072 | } | |
7073 | ||
7074 | assert (length == (f64 ? 8 : 4)); | |
7075 | ||
0dd2d296 | 7076 | if (*args == 'f' |
55933a58 | 7077 | || (*args == 'l' |
1dc1e798 KR |
7078 | && (! USE_GLOBAL_POINTER_OPT |
7079 | || mips_pic == EMBEDDED_PIC | |
a5586bdc ILT |
7080 | || g_switch_value < 4 |
7081 | || (temp[0] == 0 && temp[1] == 0) | |
7082 | || (temp[2] == 0 && temp[3] == 0)))) | |
19ed8960 ILT |
7083 | { |
7084 | imm_expr.X_op = O_constant; | |
b9129c6f | 7085 | if (! target_big_endian) |
a5586bdc | 7086 | imm_expr.X_add_number = bfd_getl32 (temp); |
19ed8960 | 7087 | else |
a5586bdc ILT |
7088 | imm_expr.X_add_number = bfd_getb32 (temp); |
7089 | } | |
7090 | else if (length > 4 | |
7091 | && ((temp[0] == 0 && temp[1] == 0) | |
7092 | || (temp[2] == 0 && temp[3] == 0)) | |
7093 | && ((temp[4] == 0 && temp[5] == 0) | |
7094 | || (temp[6] == 0 && temp[7] == 0))) | |
7095 | { | |
7096 | /* The value is simple enough to load with a | |
7097 | couple of instructions. In mips1 mode, set | |
7098 | imm_expr to the high order 32 bits and | |
7099 | offset_expr to the low order 32 bits. | |
7100 | Otherwise, set imm_expr to the entire 64 bit | |
7101 | constant. */ | |
7102 | if (mips_opts.isa < 3) | |
7103 | { | |
7104 | imm_expr.X_op = O_constant; | |
7105 | offset_expr.X_op = O_constant; | |
7106 | if (! target_big_endian) | |
7107 | { | |
7108 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
7109 | offset_expr.X_add_number = bfd_getl32 (temp); | |
7110 | } | |
7111 | else | |
7112 | { | |
7113 | imm_expr.X_add_number = bfd_getb32 (temp); | |
7114 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
7115 | } | |
7116 | if (offset_expr.X_add_number == 0) | |
7117 | offset_expr.X_op = O_absent; | |
7118 | } | |
7119 | else if (sizeof (imm_expr.X_add_number) > 4) | |
7120 | { | |
7121 | imm_expr.X_op = O_constant; | |
7122 | if (! target_big_endian) | |
7123 | imm_expr.X_add_number = bfd_getl64 (temp); | |
7124 | else | |
7125 | imm_expr.X_add_number = bfd_getb64 (temp); | |
7126 | } | |
7127 | else | |
7128 | { | |
7129 | imm_expr.X_op = O_big; | |
7130 | imm_expr.X_add_number = 4; | |
7131 | if (! target_big_endian) | |
7132 | { | |
7133 | generic_bignum[0] = bfd_getl16 (temp); | |
7134 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
7135 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
7136 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
7137 | } | |
7138 | else | |
7139 | { | |
7140 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
7141 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
7142 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
7143 | generic_bignum[3] = bfd_getb16 (temp); | |
7144 | } | |
7145 | } | |
19ed8960 ILT |
7146 | } |
7147 | else | |
7148 | { | |
0dd2d296 ILT |
7149 | const char *newname; |
7150 | segT new_seg; | |
7151 | ||
19ed8960 ILT |
7152 | /* Switch to the right section. */ |
7153 | seg = now_seg; | |
7154 | subseg = now_subseg; | |
7155 | switch (*args) | |
7156 | { | |
0dd2d296 | 7157 | default: /* unused default case avoids warnings. */ |
19ed8960 | 7158 | case 'L': |
1113140a | 7159 | newname = RDATA_SECTION_NAME; |
1dc1e798 | 7160 | if (USE_GLOBAL_POINTER_OPT && g_switch_value >= 8) |
1113140a | 7161 | newname = ".lit8"; |
0dd2d296 ILT |
7162 | break; |
7163 | case 'F': | |
d2c71068 | 7164 | newname = RDATA_SECTION_NAME; |
19ed8960 ILT |
7165 | break; |
7166 | case 'l': | |
1dc1e798 KR |
7167 | assert (!USE_GLOBAL_POINTER_OPT |
7168 | || g_switch_value >= 4); | |
0dd2d296 | 7169 | newname = ".lit4"; |
19ed8960 ILT |
7170 | break; |
7171 | } | |
0dd2d296 | 7172 | new_seg = subseg_new (newname, (subsegT) 0); |
9b61d62b ILT |
7173 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
7174 | bfd_set_section_flags (stdoutput, new_seg, | |
7175 | (SEC_ALLOC | |
7176 | | SEC_LOAD | |
7177 | | SEC_READONLY | |
7178 | | SEC_DATA)); | |
e2e5acfa JW |
7179 | frag_align (*args == 'l' ? 2 : 3, 0, 0); |
7180 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
7181 | && strcmp (TARGET_OS, "elf") != 0) | |
1dc1e798 KR |
7182 | record_alignment (new_seg, 4); |
7183 | else | |
7184 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
19ed8960 ILT |
7185 | if (seg == now_seg) |
7186 | as_bad ("Can't use floating point insn in this section"); | |
7187 | ||
7188 | /* Set the argument to the current address in the | |
6e8dda9c | 7189 | section. */ |
19ed8960 ILT |
7190 | offset_expr.X_op = O_symbol; |
7191 | offset_expr.X_add_symbol = | |
7192 | symbol_new ("L0\001", now_seg, | |
7193 | (valueT) frag_now_fix (), frag_now); | |
7194 | offset_expr.X_add_number = 0; | |
7195 | ||
7196 | /* Put the floating point number into the section. */ | |
604633ae | 7197 | p = frag_more ((int) length); |
19ed8960 ILT |
7198 | memcpy (p, temp, length); |
7199 | ||
7200 | /* Switch back to the original section. */ | |
7201 | subseg_set (seg, subseg); | |
7202 | } | |
7203 | } | |
670a50eb ILT |
7204 | continue; |
7205 | ||
7206 | case 'i': /* 16 bit unsigned immediate */ | |
7207 | case 'j': /* 16 bit signed immediate */ | |
7208 | imm_reloc = BFD_RELOC_LO16; | |
7209 | c = my_getSmallExpression (&imm_expr, s); | |
344a8d61 | 7210 | if (c != '\0') |
670a50eb ILT |
7211 | { |
7212 | if (c != 'l') | |
7213 | { | |
5ac34ac3 | 7214 | if (imm_expr.X_op == O_constant) |
670a50eb ILT |
7215 | imm_expr.X_add_number = |
7216 | (imm_expr.X_add_number >> 16) & 0xffff; | |
7217 | else if (c == 'h') | |
867a58b3 ILT |
7218 | { |
7219 | imm_reloc = BFD_RELOC_HI16_S; | |
7220 | imm_unmatched_hi = true; | |
7221 | } | |
670a50eb ILT |
7222 | else |
7223 | imm_reloc = BFD_RELOC_HI16; | |
3d3c5039 | 7224 | } |
670a50eb | 7225 | } |
670a50eb ILT |
7226 | if (*args == 'i') |
7227 | { | |
344a8d61 | 7228 | if ((c == '\0' && imm_expr.X_op != O_constant) |
a8aed9dd ILT |
7229 | || ((imm_expr.X_add_number < 0 |
7230 | || imm_expr.X_add_number >= 0x10000) | |
7231 | && imm_expr.X_op == O_constant)) | |
99c24539 ILT |
7232 | { |
7233 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
7234 | !strcmp (insn->name, insn[1].name)) | |
7235 | break; | |
9753202d ILT |
7236 | if (imm_expr.X_op != O_constant |
7237 | && imm_expr.X_op != O_big) | |
7238 | insn_error = "absolute expression required"; | |
7239 | else | |
7240 | as_bad ("16 bit expression not in range 0..65535"); | |
99c24539 | 7241 | } |
670a50eb ILT |
7242 | } |
7243 | else | |
7244 | { | |
d9aba805 ILT |
7245 | int more; |
7246 | offsetT max; | |
7247 | ||
be22008b ILT |
7248 | /* The upper bound should be 0x8000, but |
7249 | unfortunately the MIPS assembler accepts numbers | |
7250 | from 0x8000 to 0xffff and sign extends them, and | |
d9aba805 ILT |
7251 | we want to be compatible. We only permit this |
7252 | extended range for an instruction which does not | |
7253 | provide any further alternates, since those | |
7254 | alternates may handle other cases. People should | |
7255 | use the numbers they mean, rather than relying on | |
7256 | a mysterious sign extension. */ | |
7257 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
7258 | strcmp (insn->name, insn[1].name) == 0); | |
7259 | if (more) | |
7260 | max = 0x8000; | |
7261 | else | |
7262 | max = 0x10000; | |
344a8d61 | 7263 | if ((c == '\0' && imm_expr.X_op != O_constant) |
a8aed9dd ILT |
7264 | || ((imm_expr.X_add_number < -0x8000 |
7265 | || imm_expr.X_add_number >= max) | |
7266 | && imm_expr.X_op == O_constant) | |
d8a1c247 KR |
7267 | || (more |
7268 | && imm_expr.X_add_number < 0 | |
3c83da8a | 7269 | && mips_opts.isa >= 3 |
d8a1c247 KR |
7270 | && imm_expr.X_unsigned |
7271 | && sizeof (imm_expr.X_add_number) <= 4)) | |
99c24539 | 7272 | { |
d9aba805 | 7273 | if (more) |
99c24539 | 7274 | break; |
9753202d ILT |
7275 | if (imm_expr.X_op != O_constant |
7276 | && imm_expr.X_op != O_big) | |
7277 | insn_error = "absolute expression required"; | |
7278 | else | |
7279 | as_bad ("16 bit expression not in range -32768..32767"); | |
99c24539 | 7280 | } |
3d3c5039 | 7281 | } |
670a50eb ILT |
7282 | s = expr_end; |
7283 | continue; | |
7284 | ||
7285 | case 'o': /* 16 bit offset */ | |
7286 | c = my_getSmallExpression (&offset_expr, s); | |
f3645945 ILT |
7287 | |
7288 | /* If this value won't fit into a 16 bit offset, then go | |
7289 | find a macro that will generate the 32 bit offset | |
7290 | code pattern. As a special hack, we accept the | |
7291 | difference of two local symbols as a constant. This | |
7292 | is required to suppose embedded PIC switches, which | |
7293 | use an instruction which looks like | |
7294 | lw $4,$L12-$LS12($4) | |
7295 | The problem with handling this in a more general | |
7296 | fashion is that the macro function doesn't expect to | |
7297 | see anything which can be handled in a single | |
7298 | constant instruction. */ | |
6f0b87c3 SS |
7299 | if (c == 0 |
7300 | && (offset_expr.X_op != O_constant | |
7301 | || offset_expr.X_add_number >= 0x8000 | |
7302 | || offset_expr.X_add_number < -0x8000) | |
f3645945 ILT |
7303 | && (mips_pic != EMBEDDED_PIC |
7304 | || offset_expr.X_op != O_subtract | |
9da4c5d1 ILT |
7305 | || now_seg != text_section |
7306 | || (S_GET_SEGMENT (offset_expr.X_op_symbol) | |
7307 | != text_section))) | |
670a50eb | 7308 | break; |
3d3c5039 | 7309 | |
670a50eb ILT |
7310 | offset_reloc = BFD_RELOC_LO16; |
7311 | if (c == 'h' || c == 'H') | |
6e8dda9c ILT |
7312 | { |
7313 | assert (offset_expr.X_op == O_constant); | |
7314 | offset_expr.X_add_number = | |
7315 | (offset_expr.X_add_number >> 16) & 0xffff; | |
7316 | } | |
cc5703cd ILT |
7317 | s = expr_end; |
7318 | continue; | |
7319 | ||
7320 | case 'p': /* pc relative offset */ | |
7321 | offset_reloc = BFD_RELOC_16_PCREL_S2; | |
7322 | my_getExpression (&offset_expr, s); | |
7323 | s = expr_end; | |
7324 | continue; | |
7325 | ||
7326 | case 'u': /* upper 16 bits */ | |
7327 | c = my_getSmallExpression (&imm_expr, s); | |
7328 | if (imm_expr.X_op == O_constant | |
7329 | && (imm_expr.X_add_number < 0 | |
7330 | || imm_expr.X_add_number >= 0x10000)) | |
7331 | as_bad ("lui expression not in range 0..65535"); | |
7332 | imm_reloc = BFD_RELOC_LO16; | |
7333 | if (c) | |
7334 | { | |
7335 | if (c != 'l') | |
7336 | { | |
7337 | if (imm_expr.X_op == O_constant) | |
7338 | imm_expr.X_add_number = | |
7339 | (imm_expr.X_add_number >> 16) & 0xffff; | |
7340 | else if (c == 'h') | |
7341 | { | |
7342 | imm_reloc = BFD_RELOC_HI16_S; | |
7343 | imm_unmatched_hi = true; | |
7344 | } | |
7345 | else | |
7346 | imm_reloc = BFD_RELOC_HI16; | |
7347 | } | |
7348 | } | |
7349 | s = expr_end; | |
7350 | continue; | |
7351 | ||
7352 | case 'a': /* 26 bit address */ | |
7353 | my_getExpression (&offset_expr, s); | |
7354 | s = expr_end; | |
7355 | offset_reloc = BFD_RELOC_MIPS_JMP; | |
7356 | continue; | |
7357 | ||
7358 | case 'N': /* 3 bit branch condition code */ | |
7359 | case 'M': /* 3 bit compare condition code */ | |
7360 | if (strncmp (s, "$fcc", 4) != 0) | |
7361 | break; | |
7362 | s += 4; | |
7363 | regno = 0; | |
7364 | do | |
7365 | { | |
7366 | regno *= 10; | |
7367 | regno += *s - '0'; | |
7368 | ++s; | |
7369 | } | |
7370 | while (isdigit (*s)); | |
7371 | if (regno > 7) | |
7372 | as_bad ("invalid condition code register $fcc%d", regno); | |
7373 | if (*args == 'N') | |
7374 | ip->insn_opcode |= regno << OP_SH_BCC; | |
7375 | else | |
7376 | ip->insn_opcode |= regno << OP_SH_CCC; | |
7377 | continue; | |
7378 | ||
7379 | default: | |
7380 | fprintf (stderr, "bad char = '%c'\n", *args); | |
7381 | internalError (); | |
7382 | } | |
7383 | break; | |
7384 | } | |
7385 | /* Args don't match. */ | |
7386 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
7387 | !strcmp (insn->name, insn[1].name)) | |
7388 | { | |
7389 | ++insn; | |
7390 | s = argsStart; | |
7391 | continue; | |
7392 | } | |
7393 | insn_error = "illegal operands"; | |
7394 | return; | |
7395 | } | |
7396 | } | |
7397 | ||
7398 | /* This routine assembles an instruction into its binary format when | |
7399 | assembling for the mips16. As a side effect, it sets one of the | |
7400 | global variables imm_reloc or offset_reloc to the type of | |
8728fa92 ILT |
7401 | relocation to do if one of the operands is an address expression. |
7402 | It also sets mips16_small and mips16_ext if the user explicitly | |
7403 | requested a small or extended instruction. */ | |
cc5703cd ILT |
7404 | |
7405 | static void | |
7406 | mips16_ip (str, ip) | |
7407 | char *str; | |
7408 | struct mips_cl_insn *ip; | |
7409 | { | |
7410 | char *s; | |
cc5703cd ILT |
7411 | const char *args; |
7412 | struct mips_opcode *insn; | |
7413 | char *argsstart; | |
7414 | unsigned int regno; | |
7415 | unsigned int lastregno = 0; | |
7416 | char *s_reset; | |
7417 | ||
7418 | insn_error = NULL; | |
7419 | ||
8728fa92 ILT |
7420 | mips16_small = false; |
7421 | mips16_ext = false; | |
cc5703cd ILT |
7422 | |
7423 | for (s = str; islower (*s); ++s) | |
7424 | ; | |
7425 | switch (*s) | |
7426 | { | |
7427 | case '\0': | |
7428 | break; | |
7429 | ||
7430 | case ' ': | |
7431 | *s++ = '\0'; | |
7432 | break; | |
7433 | ||
7434 | case '.': | |
7435 | if (s[1] == 't' && s[2] == ' ') | |
7436 | { | |
7437 | *s = '\0'; | |
8728fa92 | 7438 | mips16_small = true; |
cc5703cd ILT |
7439 | s += 3; |
7440 | break; | |
7441 | } | |
7442 | else if (s[1] == 'e' && s[2] == ' ') | |
7443 | { | |
7444 | *s = '\0'; | |
8728fa92 | 7445 | mips16_ext = true; |
cc5703cd ILT |
7446 | s += 3; |
7447 | break; | |
7448 | } | |
7449 | /* Fall through. */ | |
7450 | default: | |
7451 | insn_error = "unknown opcode"; | |
7452 | return; | |
7453 | } | |
7454 | ||
3c83da8a | 7455 | if (mips_opts.noautoextend && ! mips16_ext) |
8728fa92 ILT |
7456 | mips16_small = true; |
7457 | ||
cc5703cd ILT |
7458 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) |
7459 | { | |
7460 | insn_error = "unrecognized opcode"; | |
7461 | return; | |
7462 | } | |
7463 | ||
7464 | argsstart = s; | |
7465 | for (;;) | |
7466 | { | |
7467 | assert (strcmp (insn->name, str) == 0); | |
7468 | ||
7469 | ip->insn_mo = insn; | |
7470 | ip->insn_opcode = insn->match; | |
7471 | ip->use_extend = false; | |
7472 | imm_expr.X_op = O_absent; | |
7473 | imm_reloc = BFD_RELOC_UNUSED; | |
7474 | offset_expr.X_op = O_absent; | |
7475 | offset_reloc = BFD_RELOC_UNUSED; | |
7476 | for (args = insn->args; 1; ++args) | |
7477 | { | |
7478 | int c; | |
7479 | ||
7480 | if (*s == ' ') | |
7481 | ++s; | |
7482 | ||
7483 | /* In this switch statement we call break if we did not find | |
7484 | a match, continue if we did find a match, or return if we | |
7485 | are done. */ | |
7486 | ||
7487 | c = *args; | |
7488 | switch (c) | |
7489 | { | |
7490 | case '\0': | |
7491 | if (*s == '\0') | |
7492 | { | |
7493 | /* Stuff the immediate value in now, if we can. */ | |
7494 | if (imm_expr.X_op == O_constant | |
7495 | && imm_reloc > BFD_RELOC_UNUSED | |
7496 | && insn->pinfo != INSN_MACRO) | |
7497 | { | |
15e69f98 ILT |
7498 | mips16_immed ((char *) NULL, 0, |
7499 | imm_reloc - BFD_RELOC_UNUSED, | |
8728fa92 ILT |
7500 | imm_expr.X_add_number, true, mips16_small, |
7501 | mips16_ext, &ip->insn_opcode, | |
7502 | &ip->use_extend, &ip->extend); | |
cc5703cd ILT |
7503 | imm_expr.X_op = O_absent; |
7504 | imm_reloc = BFD_RELOC_UNUSED; | |
7505 | } | |
7506 | ||
7507 | return; | |
7508 | } | |
7509 | break; | |
7510 | ||
7511 | case ',': | |
7512 | if (*s++ == c) | |
7513 | continue; | |
7514 | s--; | |
7515 | switch (*++args) | |
7516 | { | |
7517 | case 'v': | |
7518 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
7519 | continue; | |
7520 | case 'w': | |
7521 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
7522 | continue; | |
7523 | } | |
7524 | break; | |
7525 | ||
7526 | case '(': | |
7527 | case ')': | |
7528 | if (*s++ == c) | |
7529 | continue; | |
7530 | break; | |
7531 | ||
7532 | case 'v': | |
7533 | case 'w': | |
7534 | if (s[0] != '$') | |
7535 | { | |
7536 | if (c == 'v') | |
7537 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
7538 | else | |
7539 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
7540 | ++args; | |
7541 | continue; | |
7542 | } | |
7543 | /* Fall through. */ | |
7544 | case 'x': | |
7545 | case 'y': | |
7546 | case 'z': | |
7547 | case 'Z': | |
7548 | case '0': | |
7549 | case 'S': | |
7550 | case 'R': | |
7551 | case 'X': | |
7552 | case 'Y': | |
7553 | if (s[0] != '$') | |
7554 | break; | |
7555 | s_reset = s; | |
7556 | if (isdigit (s[1])) | |
7557 | { | |
7558 | ++s; | |
7559 | regno = 0; | |
7560 | do | |
7561 | { | |
7562 | regno *= 10; | |
7563 | regno += *s - '0'; | |
7564 | ++s; | |
7565 | } | |
7566 | while (isdigit (*s)); | |
7567 | if (regno > 31) | |
7568 | { | |
7569 | as_bad ("invalid register number (%d)", regno); | |
7570 | regno = 2; | |
7571 | } | |
7572 | } | |
7573 | else | |
7574 | { | |
7575 | if (s[1] == 'f' && s[2] == 'p') | |
7576 | { | |
7577 | s += 3; | |
7578 | regno = FP; | |
7579 | } | |
7580 | else if (s[1] == 's' && s[2] == 'p') | |
7581 | { | |
7582 | s += 3; | |
7583 | regno = SP; | |
7584 | } | |
7585 | else if (s[1] == 'g' && s[2] == 'p') | |
7586 | { | |
7587 | s += 3; | |
7588 | regno = GP; | |
7589 | } | |
7590 | else if (s[1] == 'a' && s[2] == 't') | |
7591 | { | |
7592 | s += 3; | |
7593 | regno = AT; | |
7594 | } | |
7595 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
7596 | { | |
7597 | s += 4; | |
7598 | regno = KT0; | |
7599 | } | |
7600 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
7601 | { | |
7602 | s += 4; | |
7603 | regno = KT1; | |
7604 | } | |
7605 | else | |
7606 | break; | |
7607 | } | |
7608 | ||
7609 | if (*s == ' ') | |
7610 | ++s; | |
7611 | if (args[1] != *s) | |
7612 | { | |
7613 | if (c == 'v' || c == 'w') | |
7614 | { | |
7615 | regno = mips16_to_32_reg_map[lastregno]; | |
7616 | s = s_reset; | |
7617 | args++; | |
7618 | } | |
7619 | } | |
7620 | ||
7621 | switch (c) | |
7622 | { | |
7623 | case 'x': | |
7624 | case 'y': | |
7625 | case 'z': | |
7626 | case 'v': | |
7627 | case 'w': | |
7628 | case 'Z': | |
7629 | regno = mips32_to_16_reg_map[regno]; | |
7630 | break; | |
7631 | ||
7632 | case '0': | |
7633 | if (regno != 0) | |
7634 | regno = ILLEGAL_REG; | |
7635 | break; | |
7636 | ||
7637 | case 'S': | |
7638 | if (regno != SP) | |
7639 | regno = ILLEGAL_REG; | |
7640 | break; | |
7641 | ||
7642 | case 'R': | |
7643 | if (regno != RA) | |
7644 | regno = ILLEGAL_REG; | |
7645 | break; | |
7646 | ||
7647 | case 'X': | |
7648 | case 'Y': | |
3c83da8a | 7649 | if (regno == AT && ! mips_opts.noat) |
cc5703cd ILT |
7650 | as_warn ("used $at without \".set noat\""); |
7651 | break; | |
7652 | ||
7653 | default: | |
7654 | internalError (); | |
7655 | } | |
7656 | ||
7657 | if (regno == ILLEGAL_REG) | |
7658 | break; | |
7659 | ||
7660 | switch (c) | |
7661 | { | |
7662 | case 'x': | |
7663 | case 'v': | |
7664 | ip->insn_opcode |= regno << MIPS16OP_SH_RX; | |
7665 | break; | |
7666 | case 'y': | |
7667 | case 'w': | |
7668 | ip->insn_opcode |= regno << MIPS16OP_SH_RY; | |
7669 | break; | |
7670 | case 'z': | |
7671 | ip->insn_opcode |= regno << MIPS16OP_SH_RZ; | |
7672 | break; | |
7673 | case 'Z': | |
7674 | ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z; | |
7675 | case '0': | |
7676 | case 'S': | |
7677 | case 'R': | |
7678 | break; | |
7679 | case 'X': | |
7680 | ip->insn_opcode |= regno << MIPS16OP_SH_REGR32; | |
7681 | break; | |
7682 | case 'Y': | |
7683 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
7684 | ip->insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
7685 | break; | |
7686 | default: | |
7687 | internalError (); | |
7688 | } | |
7689 | ||
7690 | lastregno = regno; | |
7691 | continue; | |
7692 | ||
7693 | case 'P': | |
7694 | if (strncmp (s, "$pc", 3) == 0) | |
7695 | { | |
7696 | s += 3; | |
7697 | continue; | |
7698 | } | |
7699 | break; | |
7700 | ||
7701 | case '<': | |
7702 | case '>': | |
7703 | case '[': | |
7704 | case ']': | |
7705 | case '4': | |
7706 | case '5': | |
7707 | case 'H': | |
7708 | case 'W': | |
7709 | case 'D': | |
7710 | case 'j': | |
7711 | case '8': | |
7712 | case 'V': | |
7713 | case 'C': | |
7714 | case 'U': | |
7715 | case 'k': | |
7716 | case 'K': | |
16262668 ILT |
7717 | if (s[0] == '%' |
7718 | && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0) | |
7719 | { | |
7720 | /* This is %gprel(SYMBOL). We need to read SYMBOL, | |
7721 | and generate the appropriate reloc. If the text | |
7722 | inside %gprel is not a symbol name with an | |
7723 | optional offset, then we generate a normal reloc | |
7724 | and will probably fail later. */ | |
7725 | my_getExpression (&imm_expr, s + sizeof "%gprel" - 1); | |
7726 | if (imm_expr.X_op == O_symbol) | |
7727 | { | |
7728 | mips16_ext = true; | |
7729 | imm_reloc = BFD_RELOC_MIPS16_GPREL; | |
7730 | s = expr_end; | |
7731 | ip->use_extend = true; | |
7732 | ip->extend = 0; | |
7733 | continue; | |
7734 | } | |
7735 | } | |
7736 | else | |
7737 | { | |
7738 | /* Just pick up a normal expression. */ | |
7739 | my_getExpression (&imm_expr, s); | |
7740 | } | |
7741 | ||
ebf28372 ILT |
7742 | if (imm_expr.X_op == O_register) |
7743 | { | |
7744 | /* What we thought was an expression turned out to | |
7745 | be a register. */ | |
7746 | ||
7747 | if (s[0] == '(' && args[1] == '(') | |
7748 | { | |
7749 | /* It looks like the expression was omitted | |
7750 | before a register indirection, which means | |
7751 | that the expression is implicitly zero. We | |
7752 | still set up imm_expr, so that we handle | |
7753 | explicit extensions correctly. */ | |
7754 | imm_expr.X_op = O_constant; | |
7755 | imm_expr.X_add_number = 0; | |
7756 | imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
7757 | continue; | |
7758 | } | |
7759 | ||
7760 | break; | |
7761 | } | |
7762 | ||
cc5703cd ILT |
7763 | /* We need to relax this instruction. */ |
7764 | imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
7765 | s = expr_end; | |
7766 | continue; | |
7767 | ||
7768 | case 'p': | |
7769 | case 'q': | |
7770 | case 'A': | |
7771 | case 'B': | |
7772 | case 'E': | |
7773 | /* We use offset_reloc rather than imm_reloc for the PC | |
7774 | relative operands. This lets macros with both | |
7775 | immediate and address operands work correctly. */ | |
670a50eb | 7776 | my_getExpression (&offset_expr, s); |
ebf28372 ILT |
7777 | |
7778 | if (offset_expr.X_op == O_register) | |
7779 | break; | |
7780 | ||
cc5703cd ILT |
7781 | /* We need to relax this instruction. */ |
7782 | offset_reloc = (int) BFD_RELOC_UNUSED + c; | |
670a50eb ILT |
7783 | s = expr_end; |
7784 | continue; | |
7785 | ||
cc5703cd ILT |
7786 | case '6': /* break code */ |
7787 | my_getExpression (&imm_expr, s); | |
7788 | check_absolute_expr (ip, &imm_expr); | |
7789 | if ((unsigned long) imm_expr.X_add_number > 63) | |
670a50eb | 7790 | { |
cc5703cd ILT |
7791 | as_warn ("Invalid value for `%s' (%lu)", |
7792 | ip->insn_mo->name, | |
7793 | (unsigned long) imm_expr.X_add_number); | |
7794 | imm_expr.X_add_number &= 0x3f; | |
3d3c5039 | 7795 | } |
cc5703cd ILT |
7796 | ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6; |
7797 | imm_expr.X_op = O_absent; | |
670a50eb ILT |
7798 | s = expr_end; |
7799 | continue; | |
3d3c5039 | 7800 | |
670a50eb ILT |
7801 | case 'a': /* 26 bit address */ |
7802 | my_getExpression (&offset_expr, s); | |
7803 | s = expr_end; | |
cc5703cd ILT |
7804 | offset_reloc = BFD_RELOC_MIPS16_JMP; |
7805 | ip->insn_opcode <<= 16; | |
670a50eb | 7806 | continue; |
3d3c5039 | 7807 | |
cc5703cd ILT |
7808 | case 'l': /* register list for entry macro */ |
7809 | case 'L': /* register list for exit macro */ | |
7810 | { | |
7811 | int mask; | |
7812 | ||
7813 | if (c == 'l') | |
7814 | mask = 0; | |
7815 | else | |
7816 | mask = 7 << 3; | |
7817 | while (*s != '\0') | |
7818 | { | |
c9167640 | 7819 | int freg, reg1, reg2; |
cc5703cd ILT |
7820 | |
7821 | while (*s == ' ' || *s == ',') | |
7822 | ++s; | |
7823 | if (*s != '$') | |
7824 | { | |
7825 | as_bad ("can't parse register list"); | |
7826 | break; | |
7827 | } | |
7828 | ++s; | |
c9167640 ILT |
7829 | if (*s != 'f') |
7830 | freg = 0; | |
7831 | else | |
7832 | { | |
7833 | freg = 1; | |
7834 | ++s; | |
7835 | } | |
cc5703cd ILT |
7836 | reg1 = 0; |
7837 | while (isdigit (*s)) | |
7838 | { | |
7839 | reg1 *= 10; | |
7840 | reg1 += *s - '0'; | |
7841 | ++s; | |
7842 | } | |
7843 | if (*s == ' ') | |
7844 | ++s; | |
7845 | if (*s != '-') | |
7846 | reg2 = reg1; | |
7847 | else | |
7848 | { | |
7849 | ++s; | |
7850 | if (*s != '$') | |
7851 | break; | |
7852 | ++s; | |
c9167640 ILT |
7853 | if (freg) |
7854 | { | |
7855 | if (*s == 'f') | |
7856 | ++s; | |
7857 | else | |
7858 | { | |
7859 | as_bad ("invalid register list"); | |
7860 | break; | |
7861 | } | |
7862 | } | |
cc5703cd ILT |
7863 | reg2 = 0; |
7864 | while (isdigit (*s)) | |
7865 | { | |
7866 | reg2 *= 10; | |
7867 | reg2 += *s - '0'; | |
7868 | ++s; | |
7869 | } | |
7870 | } | |
c9167640 ILT |
7871 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') |
7872 | { | |
7873 | mask &= ~ (7 << 3); | |
7874 | mask |= 5 << 3; | |
7875 | } | |
7876 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
7877 | { | |
7878 | mask &= ~ (7 << 3); | |
7879 | mask |= 6 << 3; | |
7880 | } | |
7881 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
cc5703cd ILT |
7882 | mask |= (reg2 - 3) << 3; |
7883 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
7884 | mask |= (reg2 - 15) << 1; | |
7885 | else if (reg1 == 31 && reg2 == 31) | |
7886 | mask |= 1; | |
7887 | else | |
c9167640 ILT |
7888 | { |
7889 | as_bad ("invalid register list"); | |
7890 | break; | |
7891 | } | |
cc5703cd | 7892 | } |
c9167640 ILT |
7893 | /* The mask is filled in in the opcode table for the |
7894 | benefit of the disassembler. We remove it before | |
7895 | applying the actual mask. */ | |
7896 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
cc5703cd ILT |
7897 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; |
7898 | } | |
7899 | continue; | |
d8a1c247 | 7900 | |
56bb6eee ILT |
7901 | case 'e': /* extend code */ |
7902 | my_getExpression (&imm_expr, s); | |
7903 | check_absolute_expr (ip, &imm_expr); | |
7904 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
7905 | { | |
7906 | as_warn ("Invalid value for `%s' (%lu)", | |
7907 | ip->insn_mo->name, | |
7908 | (unsigned long) imm_expr.X_add_number); | |
7909 | imm_expr.X_add_number &= 0x7ff; | |
7910 | } | |
7911 | ip->insn_opcode |= imm_expr.X_add_number; | |
7912 | imm_expr.X_op = O_absent; | |
7913 | s = expr_end; | |
7914 | continue; | |
7915 | ||
3d3c5039 | 7916 | default: |
670a50eb | 7917 | internalError (); |
3d3c5039 | 7918 | } |
670a50eb | 7919 | break; |
3d3c5039 | 7920 | } |
cc5703cd | 7921 | |
670a50eb | 7922 | /* Args don't match. */ |
cc5703cd ILT |
7923 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && |
7924 | strcmp (insn->name, insn[1].name) == 0) | |
670a50eb ILT |
7925 | { |
7926 | ++insn; | |
cc5703cd | 7927 | s = argsstart; |
670a50eb | 7928 | continue; |
3d3c5039 | 7929 | } |
cc5703cd | 7930 | |
9753202d | 7931 | insn_error = "illegal operands"; |
cc5703cd | 7932 | |
670a50eb | 7933 | return; |
3d3c5039 ILT |
7934 | } |
7935 | } | |
7936 | ||
cc5703cd ILT |
7937 | /* This structure holds information we know about a mips16 immediate |
7938 | argument type. */ | |
7939 | ||
7940 | struct mips16_immed_operand | |
7941 | { | |
7942 | /* The type code used in the argument string in the opcode table. */ | |
7943 | int type; | |
7944 | /* The number of bits in the short form of the opcode. */ | |
7945 | int nbits; | |
7946 | /* The number of bits in the extended form of the opcode. */ | |
7947 | int extbits; | |
7948 | /* The amount by which the short form is shifted when it is used; | |
7949 | for example, the sw instruction has a shift count of 2. */ | |
7950 | int shift; | |
7951 | /* The amount by which the short form is shifted when it is stored | |
7952 | into the instruction code. */ | |
7953 | int op_shift; | |
7954 | /* Non-zero if the short form is unsigned. */ | |
7955 | int unsp; | |
7956 | /* Non-zero if the extended form is unsigned. */ | |
7957 | int extu; | |
7958 | /* Non-zero if the value is PC relative. */ | |
7959 | int pcrel; | |
7960 | }; | |
7961 | ||
7962 | /* The mips16 immediate operand types. */ | |
7963 | ||
7964 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
7965 | { | |
7966 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
7967 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
7968 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
7969 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
7970 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
7971 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
7972 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
7973 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
7974 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
7975 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
7976 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
7977 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
7978 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
7979 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
7980 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
7981 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
7982 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
7983 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
7984 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
7985 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
7986 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
7987 | }; | |
7988 | ||
7989 | #define MIPS16_NUM_IMMED \ | |
7990 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
7991 | ||
7992 | /* Handle a mips16 instruction with an immediate value. This or's the | |
7993 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
7994 | whether an extended value is needed; if one is needed, it sets | |
7995 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
7996 | If SMALL is true, an unextended opcode was explicitly requested. | |
7997 | If EXT is true, an extended opcode was explicitly requested. If | |
7998 | WARN is true, warn if EXT does not match reality. */ | |
7999 | ||
8000 | static void | |
15e69f98 ILT |
8001 | mips16_immed (file, line, type, val, warn, small, ext, insn, use_extend, |
8002 | extend) | |
8003 | char *file; | |
8004 | unsigned int line; | |
cc5703cd ILT |
8005 | int type; |
8006 | offsetT val; | |
8007 | boolean warn; | |
8008 | boolean small; | |
8009 | boolean ext; | |
8010 | unsigned long *insn; | |
8011 | boolean *use_extend; | |
8012 | unsigned short *extend; | |
8013 | { | |
8014 | register const struct mips16_immed_operand *op; | |
8015 | int mintiny, maxtiny; | |
8016 | boolean needext; | |
8017 | ||
8018 | op = mips16_immed_operands; | |
8019 | while (op->type != type) | |
8020 | { | |
8021 | ++op; | |
8022 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
8023 | } | |
8024 | ||
8025 | if (op->unsp) | |
8026 | { | |
8027 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
8028 | { | |
8029 | mintiny = 1; | |
8030 | maxtiny = 1 << op->nbits; | |
8031 | } | |
8032 | else | |
8033 | { | |
8034 | mintiny = 0; | |
8035 | maxtiny = (1 << op->nbits) - 1; | |
8036 | } | |
8037 | } | |
8038 | else | |
8039 | { | |
8040 | mintiny = - (1 << (op->nbits - 1)); | |
8041 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
8042 | } | |
8043 | ||
8044 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
8045 | if (type == 'p' || type == 'q') | |
fbcfacb7 | 8046 | val /= 2; |
cc5703cd ILT |
8047 | |
8048 | if ((val & ((1 << op->shift) - 1)) != 0 | |
8049 | || val < (mintiny << op->shift) | |
8050 | || val > (maxtiny << op->shift)) | |
8051 | needext = true; | |
8052 | else | |
8053 | needext = false; | |
8054 | ||
8055 | if (warn && ext && ! needext) | |
15e69f98 | 8056 | as_warn_where (file, line, "extended operand requested but not required"); |
8728fa92 | 8057 | if (small && needext) |
15e69f98 | 8058 | as_bad_where (file, line, "invalid unextended operand value"); |
cc5703cd ILT |
8059 | |
8060 | if (small || (! ext && ! needext)) | |
8061 | { | |
8062 | int insnval; | |
8063 | ||
8064 | *use_extend = false; | |
8065 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); | |
8066 | insnval <<= op->op_shift; | |
8067 | *insn |= insnval; | |
8068 | } | |
8069 | else | |
8070 | { | |
8071 | long minext, maxext; | |
8072 | int extval; | |
8073 | ||
8074 | if (op->extu) | |
8075 | { | |
8076 | minext = 0; | |
8077 | maxext = (1 << op->extbits) - 1; | |
8078 | } | |
8079 | else | |
8080 | { | |
8081 | minext = - (1 << (op->extbits - 1)); | |
8082 | maxext = (1 << (op->extbits - 1)) - 1; | |
8083 | } | |
8084 | if (val < minext || val > maxext) | |
15e69f98 ILT |
8085 | as_bad_where (file, line, |
8086 | "operand value out of range for instruction"); | |
cc5703cd ILT |
8087 | |
8088 | *use_extend = true; | |
8089 | if (op->extbits == 16) | |
8090 | { | |
8091 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
8092 | val &= 0x1f; | |
8093 | } | |
8094 | else if (op->extbits == 15) | |
8095 | { | |
8096 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
8097 | val &= 0xf; | |
8098 | } | |
8099 | else | |
8100 | { | |
8101 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
8102 | val = 0; | |
8103 | } | |
8104 | ||
8105 | *extend = (unsigned short) extval; | |
8106 | *insn |= val; | |
8107 | } | |
8108 | } | |
8109 | \f | |
3d3c5039 ILT |
8110 | #define LP '(' |
8111 | #define RP ')' | |
8112 | ||
8113 | static int | |
8114 | my_getSmallExpression (ep, str) | |
670a50eb ILT |
8115 | expressionS *ep; |
8116 | char *str; | |
3d3c5039 | 8117 | { |
670a50eb ILT |
8118 | char *sp; |
8119 | int c = 0; | |
8120 | ||
8121 | if (*str == ' ') | |
8122 | str++; | |
8123 | if (*str == LP | |
8124 | || (*str == '%' && | |
8125 | ((str[1] == 'h' && str[2] == 'i') | |
8126 | || (str[1] == 'H' && str[2] == 'I') | |
8127 | || (str[1] == 'l' && str[2] == 'o')) | |
8128 | && str[3] == LP)) | |
8129 | { | |
8130 | if (*str == LP) | |
8131 | c = 0; | |
8132 | else | |
8133 | { | |
8134 | c = str[1]; | |
8135 | str += 3; | |
8136 | } | |
8137 | ||
8138 | /* | |
8139 | * A small expression may be followed by a base register. | |
8140 | * Scan to the end of this operand, and then back over a possible | |
8141 | * base register. Then scan the small expression up to that | |
8142 | * point. (Based on code in sparc.c...) | |
8143 | */ | |
8144 | for (sp = str; *sp && *sp != ','; sp++) | |
8145 | ; | |
8146 | if (sp - 4 >= str && sp[-1] == RP) | |
8147 | { | |
8148 | if (isdigit (sp[-2])) | |
8149 | { | |
8150 | for (sp -= 3; sp >= str && isdigit (*sp); sp--) | |
8151 | ; | |
8152 | if (*sp == '$' && sp > str && sp[-1] == LP) | |
8153 | { | |
8154 | sp--; | |
8155 | goto do_it; | |
3d3c5039 | 8156 | } |
670a50eb ILT |
8157 | } |
8158 | else if (sp - 5 >= str | |
8159 | && sp[-5] == LP | |
8160 | && sp[-4] == '$' | |
8161 | && ((sp[-3] == 'f' && sp[-2] == 'p') | |
8162 | || (sp[-3] == 's' && sp[-2] == 'p') | |
8163 | || (sp[-3] == 'g' && sp[-2] == 'p') | |
8164 | || (sp[-3] == 'a' && sp[-2] == 't'))) | |
8165 | { | |
8166 | sp -= 5; | |
3d3c5039 | 8167 | do_it: |
670a50eb ILT |
8168 | if (sp == str) |
8169 | { | |
8170 | /* no expression means zero offset */ | |
8171 | if (c) | |
8172 | { | |
8173 | /* %xx(reg) is an error */ | |
5ac34ac3 | 8174 | ep->X_op = O_absent; |
670a50eb | 8175 | expr_end = str - 3; |
3d3c5039 | 8176 | } |
670a50eb ILT |
8177 | else |
8178 | { | |
52aa70b5 | 8179 | ep->X_op = O_constant; |
670a50eb ILT |
8180 | expr_end = sp; |
8181 | } | |
8182 | ep->X_add_symbol = NULL; | |
5ac34ac3 | 8183 | ep->X_op_symbol = NULL; |
670a50eb ILT |
8184 | ep->X_add_number = 0; |
8185 | } | |
8186 | else | |
8187 | { | |
8188 | *sp = '\0'; | |
8189 | my_getExpression (ep, str); | |
8190 | *sp = LP; | |
3d3c5039 | 8191 | } |
670a50eb | 8192 | return c; |
3d3c5039 ILT |
8193 | } |
8194 | } | |
8195 | } | |
670a50eb ILT |
8196 | my_getExpression (ep, str); |
8197 | return c; /* => %hi or %lo encountered */ | |
3d3c5039 ILT |
8198 | } |
8199 | ||
8200 | static void | |
8201 | my_getExpression (ep, str) | |
670a50eb ILT |
8202 | expressionS *ep; |
8203 | char *str; | |
3d3c5039 | 8204 | { |
670a50eb | 8205 | char *save_in; |
670a50eb ILT |
8206 | |
8207 | save_in = input_line_pointer; | |
8208 | input_line_pointer = str; | |
5ac34ac3 | 8209 | expression (ep); |
670a50eb ILT |
8210 | expr_end = input_line_pointer; |
8211 | input_line_pointer = save_in; | |
eb17f56c ILT |
8212 | |
8213 | /* If we are in mips16 mode, and this is an expression based on `.', | |
8214 | then we bump the value of the symbol by 1 since that is how other | |
8215 | text symbols are handled. We don't bother to handle complex | |
8216 | expressions, just `.' plus or minus a constant. */ | |
3c83da8a | 8217 | if (mips_opts.mips16 |
eb17f56c ILT |
8218 | && ep->X_op == O_symbol |
8219 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
8220 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
8221 | && ep->X_add_symbol->sy_frag == frag_now | |
8222 | && ep->X_add_symbol->sy_value.X_op == O_constant | |
8223 | && ep->X_add_symbol->sy_value.X_add_number == frag_now_fix ()) | |
8224 | ++ep->X_add_symbol->sy_value.X_add_number; | |
3d3c5039 ILT |
8225 | } |
8226 | ||
becfe05e ILT |
8227 | /* Turn a string in input_line_pointer into a floating point constant |
8228 | of type type, and store the appropriate bytes in *litP. The number | |
8229 | of LITTLENUMS emitted is stored in *sizeP . An error message is | |
8230 | returned, or NULL on OK. */ | |
8231 | ||
3d3c5039 | 8232 | char * |
670a50eb | 8233 | md_atof (type, litP, sizeP) |
becfe05e | 8234 | int type; |
3d3c5039 ILT |
8235 | char *litP; |
8236 | int *sizeP; | |
8237 | { | |
becfe05e ILT |
8238 | int prec; |
8239 | LITTLENUM_TYPE words[4]; | |
8240 | char *t; | |
8241 | int i; | |
8242 | ||
8243 | switch (type) | |
8244 | { | |
8245 | case 'f': | |
8246 | prec = 2; | |
8247 | break; | |
8248 | ||
8249 | case 'd': | |
8250 | prec = 4; | |
8251 | break; | |
8252 | ||
8253 | default: | |
8254 | *sizeP = 0; | |
8255 | return "bad call to md_atof"; | |
8256 | } | |
8257 | ||
8258 | t = atof_ieee (input_line_pointer, type, words); | |
8259 | if (t) | |
8260 | input_line_pointer = t; | |
8261 | ||
8262 | *sizeP = prec * 2; | |
8263 | ||
b9129c6f | 8264 | if (! target_big_endian) |
becfe05e ILT |
8265 | { |
8266 | for (i = prec - 1; i >= 0; i--) | |
8267 | { | |
8268 | md_number_to_chars (litP, (valueT) words[i], 2); | |
8269 | litP += 2; | |
8270 | } | |
8271 | } | |
8272 | else | |
8273 | { | |
8274 | for (i = 0; i < prec; i++) | |
8275 | { | |
8276 | md_number_to_chars (litP, (valueT) words[i], 2); | |
8277 | litP += 2; | |
8278 | } | |
8279 | } | |
8280 | ||
670a50eb | 8281 | return NULL; |
3d3c5039 ILT |
8282 | } |
8283 | ||
8284 | void | |
8285 | md_number_to_chars (buf, val, n) | |
8286 | char *buf; | |
918692a5 | 8287 | valueT val; |
3d3c5039 ILT |
8288 | int n; |
8289 | { | |
b9129c6f ILT |
8290 | if (target_big_endian) |
8291 | number_to_chars_bigendian (buf, val, n); | |
8292 | else | |
8293 | number_to_chars_littleendian (buf, val, n); | |
3d3c5039 | 8294 | } |
f3d817d8 | 8295 | \f |
e8d4d475 | 8296 | CONST char *md_shortopts = "O::g::G:"; |
1dc1e798 | 8297 | |
f3d817d8 DM |
8298 | struct option md_longopts[] = { |
8299 | #define OPTION_MIPS1 (OPTION_MD_BASE + 1) | |
8300 | {"mips0", no_argument, NULL, OPTION_MIPS1}, | |
8301 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
8302 | #define OPTION_MIPS2 (OPTION_MD_BASE + 2) | |
8303 | {"mips2", no_argument, NULL, OPTION_MIPS2}, | |
8304 | #define OPTION_MIPS3 (OPTION_MD_BASE + 3) | |
8305 | {"mips3", no_argument, NULL, OPTION_MIPS3}, | |
d8a1c247 KR |
8306 | #define OPTION_MIPS4 (OPTION_MD_BASE + 4) |
8307 | {"mips4", no_argument, NULL, OPTION_MIPS4}, | |
8308 | #define OPTION_MCPU (OPTION_MD_BASE + 5) | |
f3d817d8 | 8309 | {"mcpu", required_argument, NULL, OPTION_MCPU}, |
d8a1c247 | 8310 | #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6) |
f3d817d8 | 8311 | {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC}, |
d8a1c247 | 8312 | #define OPTION_TRAP (OPTION_MD_BASE + 9) |
f3d817d8 DM |
8313 | {"trap", no_argument, NULL, OPTION_TRAP}, |
8314 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
d8a1c247 | 8315 | #define OPTION_BREAK (OPTION_MD_BASE + 10) |
f3d817d8 DM |
8316 | {"break", no_argument, NULL, OPTION_BREAK}, |
8317 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
d8a1c247 | 8318 | #define OPTION_EB (OPTION_MD_BASE + 11) |
e8d4d475 | 8319 | {"EB", no_argument, NULL, OPTION_EB}, |
d8a1c247 | 8320 | #define OPTION_EL (OPTION_MD_BASE + 12) |
e8d4d475 | 8321 | {"EL", no_argument, NULL, OPTION_EL}, |
d8a1c247 | 8322 | #define OPTION_M4650 (OPTION_MD_BASE + 13) |
b2b8c24e | 8323 | {"m4650", no_argument, NULL, OPTION_M4650}, |
d8a1c247 | 8324 | #define OPTION_NO_M4650 (OPTION_MD_BASE + 14) |
b2b8c24e | 8325 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, |
e532b44c ILT |
8326 | #define OPTION_M4010 (OPTION_MD_BASE + 15) |
8327 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
8328 | #define OPTION_NO_M4010 (OPTION_MD_BASE + 16) | |
8329 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
c625fc23 JSC |
8330 | #define OPTION_M4100 (OPTION_MD_BASE + 17) |
8331 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
8332 | #define OPTION_NO_M4100 (OPTION_MD_BASE + 18) | |
8333 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
cc5703cd | 8334 | #define OPTION_MIPS16 (OPTION_MD_BASE + 22) |
943321c0 | 8335 | {"mips16", no_argument, NULL, OPTION_MIPS16}, |
cc5703cd | 8336 | #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23) |
943321c0 | 8337 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, |
46a92fde | 8338 | /* start-sanitize-r5900 */ |
276c2d7d GRK |
8339 | #define OPTION_M5900 (OPTION_MD_BASE + 24) |
8340 | {"m5900", no_argument, NULL, OPTION_M5900}, | |
8341 | #define OPTION_NO_M5900 (OPTION_MD_BASE + 25) | |
8342 | {"no-m5900", no_argument, NULL, OPTION_NO_M5900}, | |
46a92fde | 8343 | /* end-sanitize-r5900 */ |
5c6f5923 GRK |
8344 | #define OPTION_M3900 (OPTION_MD_BASE + 26) |
8345 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
8346 | #define OPTION_NO_M3900 (OPTION_MD_BASE + 27) | |
8347 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
8348 | ||
f3d817d8 | 8349 | |
d8a1c247 | 8350 | #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7) |
1dc1e798 | 8351 | #define OPTION_NON_SHARED (OPTION_MD_BASE + 8) |
fb251650 | 8352 | #define OPTION_XGOT (OPTION_MD_BASE + 19) |
7f9880e5 ILT |
8353 | #define OPTION_32 (OPTION_MD_BASE + 20) |
8354 | #define OPTION_64 (OPTION_MD_BASE + 21) | |
1dc1e798 | 8355 | #ifdef OBJ_ELF |
f3d817d8 | 8356 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
fb251650 | 8357 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
f3d817d8 | 8358 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, |
f3d817d8 | 8359 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
7f9880e5 ILT |
8360 | {"32", no_argument, NULL, OPTION_32}, |
8361 | {"64", no_argument, NULL, OPTION_64}, | |
f3d817d8 DM |
8362 | #endif |
8363 | ||
8364 | {NULL, no_argument, NULL, 0} | |
8365 | }; | |
8366 | size_t md_longopts_size = sizeof(md_longopts); | |
3d3c5039 ILT |
8367 | |
8368 | int | |
f3d817d8 DM |
8369 | md_parse_option (c, arg) |
8370 | int c; | |
8371 | char *arg; | |
3d3c5039 | 8372 | { |
f3d817d8 | 8373 | switch (c) |
670a50eb | 8374 | { |
f3d817d8 DM |
8375 | case OPTION_TRAP: |
8376 | mips_trap = 1; | |
8377 | break; | |
670a50eb | 8378 | |
f3d817d8 DM |
8379 | case OPTION_BREAK: |
8380 | mips_trap = 0; | |
8381 | break; | |
8382 | ||
e8d4d475 | 8383 | case OPTION_EB: |
1dc1e798 | 8384 | target_big_endian = 1; |
e8d4d475 | 8385 | break; |
04cb3372 | 8386 | |
e8d4d475 | 8387 | case OPTION_EL: |
1dc1e798 | 8388 | target_big_endian = 0; |
f3d817d8 | 8389 | break; |
670a50eb | 8390 | |
f3d817d8 DM |
8391 | case 'O': |
8392 | if (arg && arg[1] == '0') | |
0aa07269 ILT |
8393 | mips_optimize = 1; |
8394 | else | |
8395 | mips_optimize = 2; | |
f3d817d8 | 8396 | break; |
0aa07269 | 8397 | |
f3d817d8 | 8398 | case 'g': |
22ba90ce ILT |
8399 | if (arg == NULL) |
8400 | mips_debug = 2; | |
8401 | else | |
8402 | mips_debug = atoi (arg); | |
8403 | /* When the MIPS assembler sees -g or -g2, it does not do | |
8404 | optimizations which limit full symbolic debugging. We take | |
8405 | that to be equivalent to -O0. */ | |
8406 | if (mips_debug == 2) | |
05874c2e | 8407 | mips_optimize = 1; |
f3d817d8 | 8408 | break; |
4e95866e | 8409 | |
f3d817d8 | 8410 | case OPTION_MIPS1: |
3c83da8a | 8411 | mips_opts.isa = 1; |
4bb0cc41 ILT |
8412 | if (mips_cpu == -1) |
8413 | mips_cpu = 3000; | |
f3d817d8 | 8414 | break; |
8358c818 | 8415 | |
f3d817d8 | 8416 | case OPTION_MIPS2: |
3c83da8a | 8417 | mips_opts.isa = 2; |
4bb0cc41 ILT |
8418 | if (mips_cpu == -1) |
8419 | mips_cpu = 6000; | |
f3d817d8 | 8420 | break; |
8358c818 | 8421 | |
f3d817d8 | 8422 | case OPTION_MIPS3: |
3c83da8a | 8423 | mips_opts.isa = 3; |
4bb0cc41 ILT |
8424 | if (mips_cpu == -1) |
8425 | mips_cpu = 4000; | |
f3d817d8 | 8426 | break; |
8358c818 | 8427 | |
d8a1c247 | 8428 | case OPTION_MIPS4: |
3c83da8a | 8429 | mips_opts.isa = 4; |
d8a1c247 KR |
8430 | if (mips_cpu == -1) |
8431 | mips_cpu = 8000; | |
8432 | break; | |
8433 | ||
f3d817d8 DM |
8434 | case OPTION_MCPU: |
8435 | { | |
8436 | char *p; | |
8437 | ||
8438 | /* Identify the processor type */ | |
8439 | p = arg; | |
8440 | if (strcmp (p, "default") == 0 | |
8441 | || strcmp (p, "DEFAULT") == 0) | |
4bb0cc41 | 8442 | mips_cpu = -1; |
f3d817d8 DM |
8443 | else |
8444 | { | |
c625fc23 JSC |
8445 | int sv = 0; |
8446 | ||
8447 | /* We need to cope with the various "vr" prefixes for the 4300 | |
8448 | processor. */ | |
8449 | if (*p == 'v' || *p == 'V') | |
8450 | { | |
8451 | sv = 1; | |
8452 | p++; | |
8453 | } | |
8454 | ||
f3d817d8 DM |
8455 | if (*p == 'r' || *p == 'R') |
8456 | p++; | |
8358c818 | 8457 | |
4bb0cc41 | 8458 | mips_cpu = -1; |
f3d817d8 DM |
8459 | switch (*p) |
8460 | { | |
d8a1c247 KR |
8461 | case '1': |
8462 | if (strcmp (p, "10000") == 0 | |
8463 | || strcmp (p, "10k") == 0 | |
8464 | || strcmp (p, "10K") == 0) | |
8465 | mips_cpu = 10000; | |
8466 | break; | |
8467 | ||
f3d817d8 DM |
8468 | case '2': |
8469 | if (strcmp (p, "2000") == 0 | |
8470 | || strcmp (p, "2k") == 0 | |
8471 | || strcmp (p, "2K") == 0) | |
4bb0cc41 | 8472 | mips_cpu = 2000; |
f3d817d8 | 8473 | break; |
8358c818 | 8474 | |
f3d817d8 DM |
8475 | case '3': |
8476 | if (strcmp (p, "3000") == 0 | |
8477 | || strcmp (p, "3k") == 0 | |
8478 | || strcmp (p, "3K") == 0) | |
4bb0cc41 | 8479 | mips_cpu = 3000; |
5c6f5923 GRK |
8480 | else if (strcmp (p, "3900") == 0) |
8481 | mips_cpu = 3900; | |
f3d817d8 | 8482 | break; |
8358c818 | 8483 | |
f3d817d8 DM |
8484 | case '4': |
8485 | if (strcmp (p, "4000") == 0 | |
8486 | || strcmp (p, "4k") == 0 | |
8c63448a | 8487 | || strcmp (p, "4K") == 0) |
4bb0cc41 | 8488 | mips_cpu = 4000; |
c625fc23 JSC |
8489 | else if (strcmp (p, "4100") == 0) |
8490 | { | |
8491 | mips_cpu = 4100; | |
8492 | if (mips_4100 < 0) | |
8493 | mips_4100 = 1; | |
8494 | } | |
8495 | else if (strcmp (p, "4300") == 0) | |
8496 | mips_cpu = 4300; | |
8c63448a | 8497 | else if (strcmp (p, "4400") == 0) |
4bb0cc41 | 8498 | mips_cpu = 4400; |
8c63448a | 8499 | else if (strcmp (p, "4600") == 0) |
4bb0cc41 | 8500 | mips_cpu = 4600; |
b2b8c24e ILT |
8501 | else if (strcmp (p, "4650") == 0) |
8502 | { | |
8503 | mips_cpu = 4650; | |
8504 | if (mips_4650 < 0) | |
8505 | mips_4650 = 1; | |
8506 | } | |
e532b44c ILT |
8507 | else if (strcmp (p, "4010") == 0) |
8508 | { | |
8509 | mips_cpu = 4010; | |
8510 | if (mips_4010 < 0) | |
8511 | mips_4010 = 1; | |
8512 | } | |
f3d817d8 | 8513 | break; |
8358c818 | 8514 | |
517078c1 ILT |
8515 | case '5': |
8516 | if (strcmp (p, "5000") == 0 | |
8517 | || strcmp (p, "5k") == 0 | |
8518 | || strcmp (p, "5K") == 0) | |
8519 | mips_cpu = 5000; | |
276c2d7d GRK |
8520 | /* start-sanitize-r5900 */ |
8521 | else if (strcmp (p, "5900") == 0) | |
8522 | mips_cpu = 5900; | |
8523 | /* end-sanitize-r5900 */ | |
517078c1 ILT |
8524 | break; |
8525 | ||
f3d817d8 DM |
8526 | case '6': |
8527 | if (strcmp (p, "6000") == 0 | |
8528 | || strcmp (p, "6k") == 0 | |
8529 | || strcmp (p, "6K") == 0) | |
4bb0cc41 | 8530 | mips_cpu = 6000; |
f3d817d8 | 8531 | break; |
55933a58 | 8532 | |
d8a1c247 KR |
8533 | case '8': |
8534 | if (strcmp (p, "8000") == 0 | |
8535 | || strcmp (p, "8k") == 0 | |
8536 | || strcmp (p, "8K") == 0) | |
8537 | mips_cpu = 8000; | |
8538 | break; | |
8539 | ||
55933a58 ILT |
8540 | case 'o': |
8541 | if (strcmp (p, "orion") == 0) | |
4bb0cc41 | 8542 | mips_cpu = 4600; |
55933a58 | 8543 | break; |
f3d817d8 | 8544 | } |
8358c818 | 8545 | |
517078c1 | 8546 | if (sv && mips_cpu != 4300 && mips_cpu != 4100 && mips_cpu != 5000) |
c625fc23 JSC |
8547 | { |
8548 | as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg); | |
8549 | return 0; | |
8550 | } | |
8551 | ||
4bb0cc41 | 8552 | if (mips_cpu == -1) |
f3d817d8 DM |
8553 | { |
8554 | as_bad ("invalid architecture -mcpu=%s", arg); | |
8555 | return 0; | |
8556 | } | |
8557 | } | |
8558 | } | |
8559 | break; | |
8358c818 | 8560 | |
b2b8c24e ILT |
8561 | case OPTION_M4650: |
8562 | mips_4650 = 1; | |
8563 | break; | |
8564 | ||
8565 | case OPTION_NO_M4650: | |
8566 | mips_4650 = 0; | |
8567 | break; | |
8568 | ||
e532b44c ILT |
8569 | case OPTION_M4010: |
8570 | mips_4010 = 1; | |
8571 | break; | |
8572 | ||
8573 | case OPTION_NO_M4010: | |
8574 | mips_4010 = 0; | |
8575 | break; | |
8576 | ||
c625fc23 JSC |
8577 | case OPTION_M4100: |
8578 | mips_4100 = 1; | |
8579 | break; | |
8580 | ||
8581 | case OPTION_NO_M4100: | |
8582 | mips_4100 = 0; | |
8583 | break; | |
8584 | ||
276c2d7d GRK |
8585 | /* start-sanitize-r5900 */ |
8586 | case OPTION_M5900: | |
8587 | mips_5900 = 1; | |
8588 | break; | |
8589 | ||
8590 | case OPTION_NO_M5900: | |
8591 | mips_5900 = 0; | |
8592 | break; | |
8593 | /* end-sanitize-r5900 */ | |
8594 | ||
5c6f5923 GRK |
8595 | case OPTION_M3900: |
8596 | mips_3900 = 1; | |
8597 | break; | |
8598 | ||
8599 | case OPTION_NO_M3900: | |
8600 | mips_3900 = 0; | |
8601 | break; | |
8602 | ||
cc5703cd | 8603 | case OPTION_MIPS16: |
3c83da8a | 8604 | mips_opts.mips16 = 1; |
4a1cb507 | 8605 | mips_no_prev_insn (false); |
cc5703cd ILT |
8606 | break; |
8607 | ||
8608 | case OPTION_NO_MIPS16: | |
3c83da8a | 8609 | mips_opts.mips16 = 0; |
4a1cb507 | 8610 | mips_no_prev_insn (false); |
cc5703cd ILT |
8611 | break; |
8612 | ||
f3d817d8 | 8613 | case OPTION_MEMBEDDED_PIC: |
d9aba805 | 8614 | mips_pic = EMBEDDED_PIC; |
1dc1e798 | 8615 | if (USE_GLOBAL_POINTER_OPT && g_switch_seen) |
f3d817d8 DM |
8616 | { |
8617 | as_bad ("-G may not be used with embedded PIC code"); | |
8618 | return 0; | |
8619 | } | |
5b63f465 | 8620 | g_switch_value = 0x7fffffff; |
f3d817d8 | 8621 | break; |
d9aba805 | 8622 | |
fb251650 ILT |
8623 | /* When generating ELF code, we permit -KPIC and -call_shared to |
8624 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
8625 | intended to be compatible with Irix 5. */ | |
f3d817d8 | 8626 | case OPTION_CALL_SHARED: |
1dc1e798 KR |
8627 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
8628 | { | |
8629 | as_bad ("-call_shared is supported only for ELF format"); | |
8630 | return 0; | |
8631 | } | |
d9aba805 ILT |
8632 | mips_pic = SVR4_PIC; |
8633 | if (g_switch_seen && g_switch_value != 0) | |
f3d817d8 DM |
8634 | { |
8635 | as_bad ("-G may not be used with SVR4 PIC code"); | |
8636 | return 0; | |
8637 | } | |
d9aba805 | 8638 | g_switch_value = 0; |
f3d817d8 DM |
8639 | break; |
8640 | ||
8641 | case OPTION_NON_SHARED: | |
1dc1e798 KR |
8642 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
8643 | { | |
8644 | as_bad ("-non_shared is supported only for ELF format"); | |
8645 | return 0; | |
8646 | } | |
d9aba805 | 8647 | mips_pic = NO_PIC; |
f3d817d8 | 8648 | break; |
8358c818 | 8649 | |
fb251650 ILT |
8650 | /* The -xgot option tells the assembler to use 32 offsets when |
8651 | accessing the got in SVR4_PIC mode. It is for Irix | |
8652 | compatibility. */ | |
8653 | case OPTION_XGOT: | |
8654 | mips_big_got = 1; | |
8655 | break; | |
8656 | ||
f3d817d8 | 8657 | case 'G': |
1dc1e798 KR |
8658 | if (! USE_GLOBAL_POINTER_OPT) |
8659 | { | |
8660 | as_bad ("-G is not supported for this configuration"); | |
8661 | return 0; | |
8662 | } | |
8663 | else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC) | |
670a50eb | 8664 | { |
f3d817d8 DM |
8665 | as_bad ("-G may not be used with SVR4 or embedded PIC code"); |
8666 | return 0; | |
670a50eb ILT |
8667 | } |
8668 | else | |
f3d817d8 | 8669 | g_switch_value = atoi (arg); |
42562568 | 8670 | g_switch_seen = 1; |
f3d817d8 | 8671 | break; |
4e95866e | 8672 | |
7f9880e5 ILT |
8673 | /* The -32 and -64 options tell the assembler to output the 32 |
8674 | bit or the 64 bit MIPS ELF format. */ | |
8675 | case OPTION_32: | |
8676 | mips_64 = 0; | |
8677 | break; | |
8678 | ||
8679 | case OPTION_64: | |
9c44af60 ILT |
8680 | { |
8681 | const char **list, **l; | |
8682 | ||
8683 | list = bfd_target_list (); | |
8684 | for (l = list; *l != NULL; l++) | |
8685 | if (strcmp (*l, "elf64-bigmips") == 0 | |
8686 | || strcmp (*l, "elf64-littlemips") == 0) | |
8687 | break; | |
8688 | if (*l == NULL) | |
8689 | as_fatal ("No compiled in support for 64 bit object file format"); | |
8690 | free (list); | |
8691 | mips_64 = 1; | |
8692 | } | |
7f9880e5 ILT |
8693 | break; |
8694 | ||
f3d817d8 DM |
8695 | default: |
8696 | return 0; | |
8ea7f4e8 ILT |
8697 | } |
8698 | ||
f3d817d8 | 8699 | return 1; |
8ea7f4e8 ILT |
8700 | } |
8701 | ||
f3d817d8 DM |
8702 | void |
8703 | md_show_usage (stream) | |
8704 | FILE *stream; | |
8705 | { | |
8706 | fprintf(stream, "\ | |
8707 | MIPS options:\n\ | |
8708 | -membedded-pic generate embedded position independent code\n\ | |
f3d817d8 DM |
8709 | -EB generate big endian output\n\ |
8710 | -EL generate little endian output\n\ | |
8711 | -g, -g2 do not remove uneeded NOPs or swap branches\n\ | |
8712 | -G NUM allow referencing objects up to NUM bytes\n\ | |
6f0b87c3 SS |
8713 | implicitly with the gp register [default 8]\n"); |
8714 | fprintf(stream, "\ | |
f3d817d8 DM |
8715 | -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\ |
8716 | -mips2, -mcpu=r6000 generate code for r6000\n\ | |
8717 | -mips3, -mcpu=r4000 generate code for r4000\n\ | |
d8a1c247 | 8718 | -mips4, -mcpu=r8000 generate code for r8000\n\ |
c625fc23 | 8719 | -mcpu=vr4300 generate code for vr4300\n\ |
fb251650 | 8720 | -mcpu=vr4100 generate code for vr4100\n\ |
e532b44c ILT |
8721 | -m4650 permit R4650 instructions\n\ |
8722 | -no-m4650 do not permit R4650 instructions\n\ | |
8723 | -m4010 permit R4010 instructions\n\ | |
8724 | -no-m4010 do not permit R4010 instructions\n\ | |
c625fc23 JSC |
8725 | -m4100 permit VR4100 instructions\n\ |
8726 | -no-m4100 do not permit VR4100 instructions\n"); | |
8727 | fprintf(stream, "\ | |
cc5703cd ILT |
8728 | -mips16 generate mips16 instructions\n\ |
8729 | -no-mips16 do not generate mips16 instructions\n"); | |
8730 | fprintf(stream, "\ | |
f3d817d8 DM |
8731 | -O0 remove unneeded NOPs, do not swap branches\n\ |
8732 | -O remove unneeded NOPs and swap branches\n\ | |
8733 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ | |
8734 | --break, --no-trap break exception on div by 0 and mult overflow\n"); | |
8735 | #ifdef OBJ_ELF | |
8736 | fprintf(stream, "\ | |
8737 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
fb251650 | 8738 | -non_shared do not generate position independent code\n\ |
7f9880e5 ILT |
8739 | -xgot assume a 32 bit GOT\n\ |
8740 | -32 create 32 bit object file (default)\n\ | |
8741 | -64 create 64 bit object file\n"); | |
f3d817d8 DM |
8742 | #endif |
8743 | } | |
8744 | \f | |
efec4a28 DP |
8745 | void |
8746 | mips_init_after_args () | |
8747 | { | |
af942793 SS |
8748 | /* initialize opcodes */ |
8749 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
8750 | mips_opcodes = (struct mips_opcode*) mips_builtin_opcodes; | |
efec4a28 DP |
8751 | } |
8752 | ||
3d3c5039 ILT |
8753 | long |
8754 | md_pcrel_from (fixP) | |
8755 | fixS *fixP; | |
8756 | { | |
1dc1e798 KR |
8757 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour |
8758 | && fixP->fx_addsy != (symbolS *) NULL | |
5b63f465 ILT |
8759 | && ! S_IS_DEFINED (fixP->fx_addsy)) |
8760 | { | |
8761 | /* This makes a branch to an undefined symbol be a branch to the | |
8762 | current location. */ | |
8763 | return 4; | |
8764 | } | |
5b63f465 | 8765 | |
670a50eb ILT |
8766 | /* return the address of the delay slot */ |
8767 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
3d3c5039 ILT |
8768 | } |
8769 | ||
abdad6bc ILT |
8770 | /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a |
8771 | reloc for a cons. We could use the definition there, except that | |
8772 | we want to handle 64 bit relocs specially. */ | |
8773 | ||
8774 | void | |
8775 | cons_fix_new_mips (frag, where, nbytes, exp) | |
8776 | fragS *frag; | |
8777 | int where; | |
8778 | unsigned int nbytes; | |
8779 | expressionS *exp; | |
8780 | { | |
bf39474f | 8781 | #ifndef OBJ_ELF |
abdad6bc | 8782 | /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a |
7f9880e5 ILT |
8783 | 4 byte reloc. */ |
8784 | if (nbytes == 8 && ! mips_64) | |
abdad6bc | 8785 | { |
b9129c6f | 8786 | if (target_big_endian) |
abdad6bc ILT |
8787 | where += 4; |
8788 | nbytes = 4; | |
8789 | } | |
bf39474f | 8790 | #endif |
abdad6bc | 8791 | |
7f9880e5 | 8792 | if (nbytes != 2 && nbytes != 4 && nbytes != 8) |
abdad6bc ILT |
8793 | as_bad ("Unsupported reloc size %d", nbytes); |
8794 | ||
8795 | fix_new_exp (frag_now, where, (int) nbytes, exp, 0, | |
7f9880e5 ILT |
8796 | (nbytes == 2 |
8797 | ? BFD_RELOC_16 | |
8798 | : (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64))); | |
abdad6bc ILT |
8799 | } |
8800 | ||
23604921 ILT |
8801 | /* This is called before the symbol table is processed. In order to |
8802 | work with gcc when using mips-tfile, we must keep all local labels. | |
8803 | However, in other cases, we want to discard them. If we were | |
8804 | called with -g, but we didn't see any debugging information, it may | |
8805 | mean that gcc is smuggling debugging information through to | |
8806 | mips-tfile, in which case we must generate all local labels. */ | |
8807 | ||
8808 | void | |
8809 | mips_frob_file_before_adjust () | |
8810 | { | |
8811 | #ifndef NO_ECOFF_DEBUGGING | |
8812 | if (ECOFF_DEBUGGING | |
8813 | && mips_debug != 0 | |
8814 | && ! ecoff_debugging_seen) | |
8815 | flag_keep_locals = 1; | |
8816 | #endif | |
8817 | } | |
8818 | ||
867a58b3 ILT |
8819 | /* Sort any unmatched HI16_S relocs so that they immediately precede |
8820 | the corresponding LO reloc. This is called before md_apply_fix and | |
8821 | tc_gen_reloc. Unmatched HI16_S relocs can only be generated by | |
8822 | explicit use of the %hi modifier. */ | |
8823 | ||
8824 | void | |
8825 | mips_frob_file () | |
8826 | { | |
8827 | struct mips_hi_fixup *l; | |
8828 | ||
8829 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
8830 | { | |
8831 | segment_info_type *seginfo; | |
9b61d62b | 8832 | int pass; |
867a58b3 ILT |
8833 | |
8834 | assert (l->fixp->fx_r_type == BFD_RELOC_HI16_S); | |
8835 | ||
8836 | /* Check quickly whether the next fixup happens to be a matching | |
8837 | %lo. */ | |
8838 | if (l->fixp->fx_next != NULL | |
8839 | && l->fixp->fx_next->fx_r_type == BFD_RELOC_LO16 | |
8840 | && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy | |
8841 | && l->fixp->fx_offset == l->fixp->fx_next->fx_offset) | |
8842 | continue; | |
8843 | ||
8844 | /* Look through the fixups for this segment for a matching %lo. | |
9b61d62b ILT |
8845 | When we find one, move the %hi just in front of it. We do |
8846 | this in two passes. In the first pass, we try to find a | |
8847 | unique %lo. In the second pass, we permit multiple %hi | |
8848 | relocs for a single %lo (this is a GNU extension). */ | |
867a58b3 | 8849 | seginfo = seg_info (l->seg); |
9b61d62b ILT |
8850 | for (pass = 0; pass < 2; pass++) |
8851 | { | |
8852 | fixS *f, *prev; | |
8853 | ||
8854 | prev = NULL; | |
8855 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) | |
867a58b3 | 8856 | { |
9b61d62b ILT |
8857 | /* Check whether this is a %lo fixup which matches l->fixp. */ |
8858 | if (f->fx_r_type == BFD_RELOC_LO16 | |
8859 | && f->fx_addsy == l->fixp->fx_addsy | |
8860 | && f->fx_offset == l->fixp->fx_offset | |
8861 | && (pass == 1 | |
8862 | || prev == NULL | |
8863 | || prev->fx_r_type != BFD_RELOC_HI16_S | |
8864 | || prev->fx_addsy != f->fx_addsy | |
8865 | || prev->fx_offset != f->fx_offset)) | |
8866 | { | |
8867 | fixS **pf; | |
867a58b3 | 8868 | |
9b61d62b ILT |
8869 | /* Move l->fixp before f. */ |
8870 | for (pf = &seginfo->fix_root; | |
8871 | *pf != l->fixp; | |
8872 | pf = &(*pf)->fx_next) | |
8873 | assert (*pf != NULL); | |
867a58b3 | 8874 | |
9b61d62b | 8875 | *pf = l->fixp->fx_next; |
867a58b3 | 8876 | |
9b61d62b ILT |
8877 | l->fixp->fx_next = f; |
8878 | if (prev == NULL) | |
8879 | seginfo->fix_root = l->fixp; | |
8880 | else | |
8881 | prev->fx_next = l->fixp; | |
867a58b3 | 8882 | |
9b61d62b ILT |
8883 | break; |
8884 | } | |
8885 | ||
8886 | prev = f; | |
867a58b3 ILT |
8887 | } |
8888 | ||
9b61d62b ILT |
8889 | if (f != NULL) |
8890 | break; | |
867a58b3 | 8891 | |
9b61d62b ILT |
8892 | if (pass == 1) |
8893 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, | |
8894 | "Unmatched %%hi reloc"); | |
8895 | } | |
867a58b3 ILT |
8896 | } |
8897 | } | |
8898 | ||
1c803e52 ILT |
8899 | /* When generating embedded PIC code we need to use a special |
8900 | relocation to represent the difference of two symbols in the .text | |
8901 | section (switch tables use a difference of this sort). See | |
8902 | include/coff/mips.h for details. This macro checks whether this | |
8903 | fixup requires the special reloc. */ | |
8904 | #define SWITCH_TABLE(fixp) \ | |
8905 | ((fixp)->fx_r_type == BFD_RELOC_32 \ | |
8906 | && (fixp)->fx_addsy != NULL \ | |
8907 | && (fixp)->fx_subsy != NULL \ | |
8908 | && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \ | |
8909 | && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section) | |
8910 | ||
5b63f465 | 8911 | /* When generating embedded PIC code we must keep all PC relative |
1c803e52 ILT |
8912 | relocations, in case the linker has to relax a call. We also need |
8913 | to keep relocations for switch table entries. */ | |
5b63f465 ILT |
8914 | |
8915 | /*ARGSUSED*/ | |
8916 | int | |
8917 | mips_force_relocation (fixp) | |
8918 | fixS *fixp; | |
8919 | { | |
1c803e52 | 8920 | return (mips_pic == EMBEDDED_PIC |
ecd4ca1c ILT |
8921 | && (fixp->fx_pcrel |
8922 | || SWITCH_TABLE (fixp) | |
8923 | || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S | |
8924 | || fixp->fx_r_type == BFD_RELOC_PCREL_LO16)); | |
5b63f465 ILT |
8925 | } |
8926 | ||
8927 | /* Apply a fixup to the object file. */ | |
8928 | ||
3d3c5039 ILT |
8929 | int |
8930 | md_apply_fix (fixP, valueP) | |
8931 | fixS *fixP; | |
918692a5 | 8932 | valueT *valueP; |
3d3c5039 | 8933 | { |
670a50eb ILT |
8934 | unsigned char *buf; |
8935 | long insn, value; | |
3d3c5039 | 8936 | |
bf39474f ILT |
8937 | assert (fixP->fx_size == 4 |
8938 | || fixP->fx_r_type == BFD_RELOC_16 | |
8939 | || fixP->fx_r_type == BFD_RELOC_64); | |
3d3c5039 | 8940 | |
670a50eb | 8941 | value = *valueP; |
1748b9d8 ILT |
8942 | |
8943 | /* If we aren't adjusting this fixup to be against the section | |
8944 | symbol, we need to adjust the value. */ | |
68952421 | 8945 | #ifdef OBJ_ELF |
1748b9d8 | 8946 | if (fixP->fx_addsy != NULL |
1748b9d8 ILT |
8947 | && OUTPUT_FLAVOR == bfd_target_elf_flavour |
8948 | && S_GET_OTHER (fixP->fx_addsy) == STO_MIPS16) | |
8949 | { | |
8950 | value -= S_GET_VALUE (fixP->fx_addsy); | |
8951 | if (value != 0 && ! fixP->fx_pcrel) | |
8952 | { | |
8953 | /* In this case, the bfd_install_relocation routine will | |
8954 | incorrectly add the symbol value back in. We just want | |
8955 | the addend to appear in the object file. */ | |
8956 | value -= S_GET_VALUE (fixP->fx_addsy); | |
8957 | } | |
8958 | } | |
8959 | #endif | |
8960 | ||
670a50eb | 8961 | fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc */ |
3d3c5039 | 8962 | |
5b63f465 ILT |
8963 | if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel) |
8964 | fixP->fx_done = 1; | |
8965 | ||
670a50eb ILT |
8966 | switch (fixP->fx_r_type) |
8967 | { | |
3d3c5039 ILT |
8968 | case BFD_RELOC_MIPS_JMP: |
8969 | case BFD_RELOC_HI16: | |
8970 | case BFD_RELOC_HI16_S: | |
670a50eb | 8971 | case BFD_RELOC_MIPS_GPREL: |
9226253a ILT |
8972 | case BFD_RELOC_MIPS_LITERAL: |
8973 | case BFD_RELOC_MIPS_CALL16: | |
0dd2d296 ILT |
8974 | case BFD_RELOC_MIPS_GOT16: |
8975 | case BFD_RELOC_MIPS_GPREL32: | |
fb251650 ILT |
8976 | case BFD_RELOC_MIPS_GOT_HI16: |
8977 | case BFD_RELOC_MIPS_GOT_LO16: | |
8978 | case BFD_RELOC_MIPS_CALL_HI16: | |
8979 | case BFD_RELOC_MIPS_CALL_LO16: | |
16262668 | 8980 | case BFD_RELOC_MIPS16_GPREL: |
ecd4ca1c | 8981 | if (fixP->fx_pcrel) |
7b777690 ILT |
8982 | as_bad_where (fixP->fx_file, fixP->fx_line, |
8983 | "Invalid PC relative reloc"); | |
670a50eb | 8984 | /* Nothing needed to do. The value comes from the reloc entry */ |
5b63f465 | 8985 | break; |
3d3c5039 | 8986 | |
cc5703cd ILT |
8987 | case BFD_RELOC_MIPS16_JMP: |
8988 | /* We currently always generate a reloc against a symbol, which | |
8989 | means that we don't want an addend even if the symbol is | |
8990 | defined. */ | |
8991 | fixP->fx_addnumber = 0; | |
8992 | break; | |
8993 | ||
ecd4ca1c ILT |
8994 | case BFD_RELOC_PCREL_HI16_S: |
8995 | /* The addend for this is tricky if it is internal, so we just | |
9e6f4c6b | 8996 | do everything here rather than in bfd_install_relocation. */ |
ecd4ca1c ILT |
8997 | if ((fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0) |
8998 | { | |
8999 | /* For an external symbol adjust by the address to make it | |
9000 | pcrel_offset. We use the address of the RELLO reloc | |
9001 | which follows this one. */ | |
9002 | value += (fixP->fx_next->fx_frag->fr_address | |
9003 | + fixP->fx_next->fx_where); | |
9004 | } | |
9005 | if (value & 0x8000) | |
9006 | value += 0x10000; | |
9007 | value >>= 16; | |
0221ddf7 | 9008 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
b9129c6f | 9009 | if (target_big_endian) |
ecd4ca1c ILT |
9010 | buf += 2; |
9011 | md_number_to_chars (buf, value, 2); | |
9012 | break; | |
9013 | ||
9014 | case BFD_RELOC_PCREL_LO16: | |
9015 | /* The addend for this is tricky if it is internal, so we just | |
9e6f4c6b | 9016 | do everything here rather than in bfd_install_relocation. */ |
ecd4ca1c ILT |
9017 | if ((fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0) |
9018 | value += fixP->fx_frag->fr_address + fixP->fx_where; | |
0221ddf7 | 9019 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
b9129c6f | 9020 | if (target_big_endian) |
ecd4ca1c ILT |
9021 | buf += 2; |
9022 | md_number_to_chars (buf, value, 2); | |
9023 | break; | |
9024 | ||
bf39474f ILT |
9025 | case BFD_RELOC_64: |
9026 | /* This is handled like BFD_RELOC_32, but we output a sign | |
9027 | extended value if we are only 32 bits. */ | |
9028 | if (fixP->fx_done | |
9029 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
9030 | { | |
9031 | if (8 <= sizeof (valueT)) | |
9032 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
9033 | value, 8); | |
9034 | else | |
9035 | { | |
9036 | long w1, w2; | |
9037 | long hiv; | |
9038 | ||
9039 | w1 = w2 = fixP->fx_where; | |
b9129c6f | 9040 | if (target_big_endian) |
bf39474f ILT |
9041 | w1 += 4; |
9042 | else | |
9043 | w2 += 4; | |
9044 | md_number_to_chars (fixP->fx_frag->fr_literal + w1, value, 4); | |
9045 | if ((value & 0x80000000) != 0) | |
9046 | hiv = 0xffffffff; | |
9047 | else | |
9048 | hiv = 0; | |
9049 | md_number_to_chars (fixP->fx_frag->fr_literal + w2, hiv, 4); | |
9050 | } | |
9051 | } | |
9052 | break; | |
9053 | ||
f3645945 ILT |
9054 | case BFD_RELOC_32: |
9055 | /* If we are deleting this reloc entry, we must fill in the | |
9056 | value now. This can happen if we have a .word which is not | |
1c803e52 ILT |
9057 | resolved when it appears but is later defined. We also need |
9058 | to fill in the value if this is an embedded PIC switch table | |
9059 | entry. */ | |
9060 | if (fixP->fx_done | |
9061 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
f3645945 ILT |
9062 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, |
9063 | value, 4); | |
9064 | break; | |
9065 | ||
49ad0c4c ILT |
9066 | case BFD_RELOC_16: |
9067 | /* If we are deleting this reloc entry, we must fill in the | |
9068 | value now. */ | |
9069 | assert (fixP->fx_size == 2); | |
9070 | if (fixP->fx_done) | |
9071 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
9072 | value, 2); | |
9073 | break; | |
9074 | ||
f3645945 ILT |
9075 | case BFD_RELOC_LO16: |
9076 | /* When handling an embedded PIC switch statement, we can wind | |
9077 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
9078 | if (fixP->fx_done) | |
9079 | { | |
9080 | if (value < -0x8000 || value > 0x7fff) | |
9081 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
9082 | "relocation overflow"); | |
0221ddf7 | 9083 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
b9129c6f | 9084 | if (target_big_endian) |
f3645945 ILT |
9085 | buf += 2; |
9086 | md_number_to_chars (buf, value, 2); | |
9087 | } | |
9088 | break; | |
9089 | ||
3d3c5039 | 9090 | case BFD_RELOC_16_PCREL_S2: |
670a50eb ILT |
9091 | /* |
9092 | * We need to save the bits in the instruction since fixup_segment() | |
9093 | * might be deleting the relocation entry (i.e., a branch within | |
9094 | * the current segment). | |
9095 | */ | |
fbcfacb7 | 9096 | if ((value & 0x3) != 0) |
3b320c48 ILT |
9097 | as_bad_where (fixP->fx_file, fixP->fx_line, |
9098 | "Branch to odd address (%lx)", value); | |
670a50eb | 9099 | value >>= 2; |
670a50eb ILT |
9100 | |
9101 | /* update old instruction data */ | |
9102 | buf = (unsigned char *) (fixP->fx_where + fixP->fx_frag->fr_literal); | |
b9129c6f ILT |
9103 | if (target_big_endian) |
9104 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
9105 | else | |
9106 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
9da4c5d1 ILT |
9107 | |
9108 | if (value >= -0x8000 && value < 0x8000) | |
9109 | insn |= value & 0xffff; | |
9110 | else | |
9111 | { | |
9112 | /* The branch offset is too large. If this is an | |
9113 | unconditional branch, and we are not generating PIC code, | |
9114 | we can convert it to an absolute jump instruction. */ | |
9115 | if (mips_pic == NO_PIC | |
9116 | && fixP->fx_done | |
9117 | && fixP->fx_frag->fr_address >= text_section->vma | |
9118 | && (fixP->fx_frag->fr_address | |
9119 | < text_section->vma + text_section->_raw_size) | |
9120 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
9121 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
9122 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
9123 | { | |
9124 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ | |
9125 | insn = 0x0c000000; /* jal */ | |
9126 | else | |
9127 | insn = 0x08000000; /* j */ | |
9128 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
9129 | fixP->fx_done = 0; | |
9130 | fixP->fx_addsy = section_symbol (text_section); | |
9131 | fixP->fx_addnumber = (value << 2) + md_pcrel_from (fixP); | |
9132 | } | |
9133 | else | |
9134 | { | |
9135 | /* FIXME. It would be possible in principle to handle | |
9136 | conditional branches which overflow. They could be | |
9137 | transformed into a branch around a jump. This would | |
9138 | require setting up variant frags for each different | |
9139 | branch type. The native MIPS assembler attempts to | |
9140 | handle these cases, but it appears to do it | |
9141 | incorrectly. */ | |
9142 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
18f7e3dc | 9143 | "Branch out of range"); |
9da4c5d1 ILT |
9144 | } |
9145 | } | |
9146 | ||
604633ae | 9147 | md_number_to_chars ((char *) buf, (valueT) insn, 4); |
670a50eb | 9148 | break; |
3d3c5039 ILT |
9149 | |
9150 | default: | |
670a50eb | 9151 | internalError (); |
3d3c5039 | 9152 | } |
5b63f465 | 9153 | |
670a50eb | 9154 | return 1; |
3d3c5039 ILT |
9155 | } |
9156 | ||
9157 | #if 0 | |
9158 | void | |
670a50eb ILT |
9159 | printInsn (oc) |
9160 | unsigned long oc; | |
3d3c5039 | 9161 | { |
670a50eb ILT |
9162 | const struct mips_opcode *p; |
9163 | int treg, sreg, dreg, shamt; | |
9164 | short imm; | |
9165 | const char *args; | |
9166 | int i; | |
3d3c5039 | 9167 | |
670a50eb ILT |
9168 | for (i = 0; i < NUMOPCODES; ++i) |
9169 | { | |
9170 | p = &mips_opcodes[i]; | |
9171 | if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO)) | |
9172 | { | |
9173 | printf ("%08lx %s\t", oc, p->name); | |
9174 | treg = (oc >> 16) & 0x1f; | |
9175 | sreg = (oc >> 21) & 0x1f; | |
9176 | dreg = (oc >> 11) & 0x1f; | |
9177 | shamt = (oc >> 6) & 0x1f; | |
9178 | imm = oc; | |
9179 | for (args = p->args;; ++args) | |
9180 | { | |
9181 | switch (*args) | |
9182 | { | |
3d3c5039 | 9183 | case '\0': |
670a50eb ILT |
9184 | printf ("\n"); |
9185 | break; | |
3d3c5039 ILT |
9186 | |
9187 | case ',': | |
9188 | case '(': | |
9189 | case ')': | |
670a50eb ILT |
9190 | printf ("%c", *args); |
9191 | continue; | |
3d3c5039 ILT |
9192 | |
9193 | case 'r': | |
670a50eb ILT |
9194 | assert (treg == sreg); |
9195 | printf ("$%d,$%d", treg, sreg); | |
9196 | continue; | |
3d3c5039 ILT |
9197 | |
9198 | case 'd': | |
918692a5 | 9199 | case 'G': |
670a50eb ILT |
9200 | printf ("$%d", dreg); |
9201 | continue; | |
3d3c5039 ILT |
9202 | |
9203 | case 't': | |
918692a5 | 9204 | case 'E': |
670a50eb ILT |
9205 | printf ("$%d", treg); |
9206 | continue; | |
3d3c5039 | 9207 | |
9226253a ILT |
9208 | case 'k': |
9209 | printf ("0x%x", treg); | |
9210 | continue; | |
9211 | ||
3d3c5039 ILT |
9212 | case 'b': |
9213 | case 's': | |
670a50eb ILT |
9214 | printf ("$%d", sreg); |
9215 | continue; | |
3d3c5039 ILT |
9216 | |
9217 | case 'a': | |
670a50eb ILT |
9218 | printf ("0x%08lx", oc & 0x1ffffff); |
9219 | continue; | |
3d3c5039 ILT |
9220 | |
9221 | case 'i': | |
9222 | case 'j': | |
9223 | case 'o': | |
9224 | case 'u': | |
670a50eb ILT |
9225 | printf ("%d", imm); |
9226 | continue; | |
3d3c5039 ILT |
9227 | |
9228 | case '<': | |
56c96faa | 9229 | case '>': |
670a50eb ILT |
9230 | printf ("$%d", shamt); |
9231 | continue; | |
3d3c5039 ILT |
9232 | |
9233 | default: | |
670a50eb | 9234 | internalError (); |
3d3c5039 | 9235 | } |
670a50eb | 9236 | break; |
3d3c5039 | 9237 | } |
670a50eb | 9238 | return; |
3d3c5039 ILT |
9239 | } |
9240 | } | |
670a50eb | 9241 | printf ("%08lx UNDEFINED\n", oc); |
3d3c5039 ILT |
9242 | } |
9243 | #endif | |
9244 | ||
9245 | static symbolS * | |
9246 | get_symbol () | |
9247 | { | |
670a50eb ILT |
9248 | int c; |
9249 | char *name; | |
9250 | symbolS *p; | |
9251 | ||
9252 | name = input_line_pointer; | |
9253 | c = get_symbol_end (); | |
9254 | p = (symbolS *) symbol_find_or_make (name); | |
9255 | *input_line_pointer = c; | |
9256 | return p; | |
3d3c5039 ILT |
9257 | } |
9258 | ||
becfe05e ILT |
9259 | /* Align the current frag to a given power of two. The MIPS assembler |
9260 | also automatically adjusts any preceding label. */ | |
9261 | ||
9262 | static void | |
23dc1ae3 | 9263 | mips_align (to, fill, label) |
becfe05e ILT |
9264 | int to; |
9265 | int fill; | |
23dc1ae3 | 9266 | symbolS *label; |
becfe05e | 9267 | { |
fbcfacb7 | 9268 | mips_emit_delays (false); |
e2e5acfa | 9269 | frag_align (to, fill, 0); |
becfe05e | 9270 | record_alignment (now_seg, to); |
23dc1ae3 | 9271 | if (label != NULL) |
becfe05e | 9272 | { |
23dc1ae3 ILT |
9273 | assert (S_GET_SEGMENT (label) == now_seg); |
9274 | label->sy_frag = frag_now; | |
9275 | S_SET_VALUE (label, (valueT) frag_now_fix ()); | |
becfe05e ILT |
9276 | } |
9277 | } | |
9278 | ||
9279 | /* Align to a given power of two. .align 0 turns off the automatic | |
9280 | alignment used by the data creating pseudo-ops. */ | |
9281 | ||
3d3c5039 ILT |
9282 | static void |
9283 | s_align (x) | |
9284 | int x; | |
9285 | { | |
670a50eb ILT |
9286 | register int temp; |
9287 | register long temp_fill; | |
9288 | long max_alignment = 15; | |
3d3c5039 | 9289 | |
670a50eb | 9290 | /* |
3d3c5039 ILT |
9291 | |
9292 | o Note that the assembler pulls down any immediately preceeding label | |
9293 | to the aligned address. | |
9294 | o It's not documented but auto alignment is reinstated by | |
9295 | a .align pseudo instruction. | |
9296 | o Note also that after auto alignment is turned off the mips assembler | |
9297 | issues an error on attempt to assemble an improperly aligned data item. | |
9298 | We don't. | |
9299 | ||
9300 | */ | |
9301 | ||
670a50eb ILT |
9302 | temp = get_absolute_expression (); |
9303 | if (temp > max_alignment) | |
9304 | as_bad ("Alignment too large: %d. assumed.", temp = max_alignment); | |
9305 | else if (temp < 0) | |
9306 | { | |
9307 | as_warn ("Alignment negative: 0 assumed."); | |
9308 | temp = 0; | |
9309 | } | |
9310 | if (*input_line_pointer == ',') | |
9311 | { | |
9312 | input_line_pointer++; | |
9313 | temp_fill = get_absolute_expression (); | |
9314 | } | |
9315 | else | |
9316 | temp_fill = 0; | |
9317 | if (temp) | |
9318 | { | |
9319 | auto_align = 1; | |
fbcfacb7 ILT |
9320 | mips_align (temp, (int) temp_fill, |
9321 | insn_labels != NULL ? insn_labels->label : NULL); | |
3d3c5039 | 9322 | } |
670a50eb ILT |
9323 | else |
9324 | { | |
9325 | auto_align = 0; | |
3d3c5039 ILT |
9326 | } |
9327 | ||
670a50eb | 9328 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
9329 | } |
9330 | ||
739708fa KR |
9331 | void |
9332 | mips_flush_pending_output () | |
becfe05e | 9333 | { |
fbcfacb7 ILT |
9334 | mips_emit_delays (false); |
9335 | mips_clear_insn_labels (); | |
becfe05e ILT |
9336 | } |
9337 | ||
3d3c5039 ILT |
9338 | static void |
9339 | s_change_sec (sec) | |
9340 | int sec; | |
9341 | { | |
88225433 | 9342 | segT seg; |
becfe05e | 9343 | |
5b63f465 ILT |
9344 | /* When generating embedded PIC code, we only use the .text, .lit8, |
9345 | .sdata and .sbss sections. We change the .data and .rdata | |
9346 | pseudo-ops to use .sdata. */ | |
9347 | if (mips_pic == EMBEDDED_PIC | |
9348 | && (sec == 'd' || sec == 'r')) | |
9349 | sec = 's'; | |
9350 | ||
acdc7ce3 ILT |
9351 | #ifdef OBJ_ELF |
9352 | /* The ELF backend needs to know that we are changing sections, so | |
9353 | that .previous works correctly. We could do something like check | |
9354 | for a obj_section_change_hook macro, but that might be confusing | |
9355 | as it would not be appropriate to use it in the section changing | |
9356 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
9357 | This should be cleaner, somehow. */ | |
9358 | obj_elf_section_change_hook (); | |
9359 | #endif | |
9360 | ||
fbcfacb7 | 9361 | mips_emit_delays (false); |
670a50eb ILT |
9362 | switch (sec) |
9363 | { | |
3d3c5039 | 9364 | case 't': |
604633ae | 9365 | s_text (0); |
670a50eb | 9366 | break; |
3d3c5039 | 9367 | case 'd': |
604633ae | 9368 | s_data (0); |
670a50eb | 9369 | break; |
3d3c5039 | 9370 | case 'b': |
670a50eb | 9371 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); |
670a50eb ILT |
9372 | demand_empty_rest_of_line (); |
9373 | break; | |
88225433 ILT |
9374 | |
9375 | case 'r': | |
1dc1e798 KR |
9376 | if (USE_GLOBAL_POINTER_OPT) |
9377 | { | |
9378 | seg = subseg_new (RDATA_SECTION_NAME, | |
9379 | (subsegT) get_absolute_expression ()); | |
9380 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
9381 | { | |
9382 | bfd_set_section_flags (stdoutput, seg, | |
9383 | (SEC_ALLOC | |
9384 | | SEC_LOAD | |
9385 | | SEC_READONLY | |
9386 | | SEC_RELOC | |
9387 | | SEC_DATA)); | |
08e17202 ILT |
9388 | if (strcmp (TARGET_OS, "elf") != 0) |
9389 | bfd_set_section_alignment (stdoutput, seg, 4); | |
1dc1e798 KR |
9390 | } |
9391 | demand_empty_rest_of_line (); | |
9392 | } | |
9393 | else | |
9394 | { | |
9395 | as_bad ("No read only data section in this object file format"); | |
9396 | demand_empty_rest_of_line (); | |
9397 | return; | |
9398 | } | |
88225433 | 9399 | break; |
88225433 ILT |
9400 | |
9401 | case 's': | |
1dc1e798 KR |
9402 | if (USE_GLOBAL_POINTER_OPT) |
9403 | { | |
9404 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); | |
9405 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
9406 | { | |
9407 | bfd_set_section_flags (stdoutput, seg, | |
9408 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | |
9409 | | SEC_DATA); | |
08e17202 ILT |
9410 | if (strcmp (TARGET_OS, "elf") != 0) |
9411 | bfd_set_section_alignment (stdoutput, seg, 4); | |
1dc1e798 KR |
9412 | } |
9413 | demand_empty_rest_of_line (); | |
9414 | break; | |
9415 | } | |
9416 | else | |
9417 | { | |
9418 | as_bad ("Global pointers not supported; recompile -G 0"); | |
9419 | demand_empty_rest_of_line (); | |
9420 | return; | |
9421 | } | |
3d3c5039 | 9422 | } |
88225433 | 9423 | |
670a50eb | 9424 | auto_align = 1; |
3d3c5039 ILT |
9425 | } |
9426 | ||
739708fa KR |
9427 | void |
9428 | mips_enable_auto_align () | |
9da4c5d1 | 9429 | { |
9da4c5d1 ILT |
9430 | auto_align = 1; |
9431 | } | |
9432 | ||
3d3c5039 ILT |
9433 | static void |
9434 | s_cons (log_size) | |
9435 | int log_size; | |
9436 | { | |
23dc1ae3 ILT |
9437 | symbolS *label; |
9438 | ||
fbcfacb7 ILT |
9439 | label = insn_labels != NULL ? insn_labels->label : NULL; |
9440 | mips_emit_delays (false); | |
670a50eb | 9441 | if (log_size > 0 && auto_align) |
23dc1ae3 | 9442 | mips_align (log_size, 0, label); |
fbcfacb7 | 9443 | mips_clear_insn_labels (); |
670a50eb | 9444 | cons (1 << log_size); |
3d3c5039 ILT |
9445 | } |
9446 | ||
3d3c5039 | 9447 | static void |
becfe05e ILT |
9448 | s_float_cons (type) |
9449 | int type; | |
3d3c5039 | 9450 | { |
23dc1ae3 ILT |
9451 | symbolS *label; |
9452 | ||
fbcfacb7 | 9453 | label = insn_labels != NULL ? insn_labels->label : NULL; |
23dc1ae3 | 9454 | |
fbcfacb7 | 9455 | mips_emit_delays (false); |
670a50eb ILT |
9456 | |
9457 | if (auto_align) | |
becfe05e | 9458 | if (type == 'd') |
23dc1ae3 | 9459 | mips_align (3, 0, label); |
670a50eb | 9460 | else |
23dc1ae3 | 9461 | mips_align (2, 0, label); |
670a50eb | 9462 | |
fbcfacb7 | 9463 | mips_clear_insn_labels (); |
1849d646 | 9464 | |
becfe05e | 9465 | float_cons (type); |
3d3c5039 ILT |
9466 | } |
9467 | ||
c1444ec4 ILT |
9468 | /* Handle .globl. We need to override it because on Irix 5 you are |
9469 | permitted to say | |
9470 | .globl foo .text | |
9471 | where foo is an undefined symbol, to mean that foo should be | |
9472 | considered to be the address of a function. */ | |
9473 | ||
9474 | static void | |
9475 | s_mips_globl (x) | |
9476 | int x; | |
9477 | { | |
9478 | char *name; | |
9479 | int c; | |
9480 | symbolS *symbolP; | |
fb251650 | 9481 | flagword flag; |
c1444ec4 ILT |
9482 | |
9483 | name = input_line_pointer; | |
9484 | c = get_symbol_end (); | |
9485 | symbolP = symbol_find_or_make (name); | |
9486 | *input_line_pointer = c; | |
9487 | SKIP_WHITESPACE (); | |
fb251650 ILT |
9488 | |
9489 | /* On Irix 5, every global symbol that is not explicitly labelled as | |
9490 | being a function is apparently labelled as being an object. */ | |
9491 | flag = BSF_OBJECT; | |
9492 | ||
c1444ec4 ILT |
9493 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) |
9494 | { | |
9495 | char *secname; | |
9496 | asection *sec; | |
9497 | ||
9498 | secname = input_line_pointer; | |
9499 | c = get_symbol_end (); | |
9500 | sec = bfd_get_section_by_name (stdoutput, secname); | |
9501 | if (sec == NULL) | |
9502 | as_bad ("%s: no such section", secname); | |
9503 | *input_line_pointer = c; | |
9504 | ||
9505 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
fb251650 | 9506 | flag = BSF_FUNCTION; |
c1444ec4 ILT |
9507 | } |
9508 | ||
fb251650 ILT |
9509 | symbolP->bsym->flags |= flag; |
9510 | ||
c1444ec4 ILT |
9511 | S_SET_EXTERNAL (symbolP); |
9512 | demand_empty_rest_of_line (); | |
9513 | } | |
9514 | ||
3d3c5039 ILT |
9515 | static void |
9516 | s_option (x) | |
9517 | int x; | |
9518 | { | |
dd3f1f76 ILT |
9519 | char *opt; |
9520 | char c; | |
9521 | ||
9522 | opt = input_line_pointer; | |
9523 | c = get_symbol_end (); | |
9524 | ||
dd3f1f76 | 9525 | if (*opt == 'O') |
9226253a ILT |
9526 | { |
9527 | /* FIXME: What does this mean? */ | |
9528 | } | |
dd3f1f76 | 9529 | else if (strncmp (opt, "pic", 3) == 0) |
9226253a | 9530 | { |
d9aba805 | 9531 | int i; |
42562568 | 9532 | |
d9aba805 ILT |
9533 | i = atoi (opt + 3); |
9534 | if (i == 0) | |
9535 | mips_pic = NO_PIC; | |
9536 | else if (i == 2) | |
9537 | mips_pic = SVR4_PIC; | |
9538 | else | |
9539 | as_bad (".option pic%d not supported", i); | |
9540 | ||
1dc1e798 | 9541 | if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC) |
42562568 ILT |
9542 | { |
9543 | if (g_switch_seen && g_switch_value != 0) | |
d9aba805 | 9544 | as_warn ("-G may not be used with SVR4 PIC code"); |
42562568 ILT |
9545 | g_switch_value = 0; |
9546 | bfd_set_gp_size (stdoutput, 0); | |
9547 | } | |
9226253a | 9548 | } |
dd3f1f76 ILT |
9549 | else |
9550 | as_warn ("Unrecognized option \"%s\"", opt); | |
9551 | ||
9552 | *input_line_pointer = c; | |
670a50eb | 9553 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
9554 | } |
9555 | ||
3c83da8a JW |
9556 | /* This structure is used to hold a stack of .set values. */ |
9557 | ||
9558 | struct mips_option_stack | |
9559 | { | |
9560 | struct mips_option_stack *next; | |
9561 | struct mips_set_options options; | |
9562 | }; | |
9563 | ||
9564 | static struct mips_option_stack *mips_opts_stack; | |
9565 | ||
9566 | /* Handle the .set pseudo-op. */ | |
9567 | ||
3d3c5039 ILT |
9568 | static void |
9569 | s_mipsset (x) | |
9570 | int x; | |
9571 | { | |
670a50eb ILT |
9572 | char *name = input_line_pointer, ch; |
9573 | ||
9574 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
9575 | input_line_pointer++; | |
9576 | ch = *input_line_pointer; | |
9577 | *input_line_pointer = '\0'; | |
9578 | ||
9579 | if (strcmp (name, "reorder") == 0) | |
9580 | { | |
3c83da8a | 9581 | if (mips_opts.noreorder && prev_nop_frag != NULL) |
4e95866e | 9582 | { |
4a1cb507 ILT |
9583 | /* If we still have pending nops, we can discard them. The |
9584 | usual nop handling will insert any that are still | |
9585 | needed. */ | |
3c83da8a JW |
9586 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds |
9587 | * (mips_opts.mips16 ? 2 : 4)); | |
4a1cb507 | 9588 | prev_nop_frag = NULL; |
4e95866e | 9589 | } |
3c83da8a | 9590 | mips_opts.noreorder = 0; |
670a50eb ILT |
9591 | } |
9592 | else if (strcmp (name, "noreorder") == 0) | |
9593 | { | |
fbcfacb7 | 9594 | mips_emit_delays (true); |
3c83da8a | 9595 | mips_opts.noreorder = 1; |
0dd2d296 | 9596 | mips_any_noreorder = 1; |
670a50eb ILT |
9597 | } |
9598 | else if (strcmp (name, "at") == 0) | |
9599 | { | |
3c83da8a | 9600 | mips_opts.noat = 0; |
670a50eb ILT |
9601 | } |
9602 | else if (strcmp (name, "noat") == 0) | |
9603 | { | |
3c83da8a | 9604 | mips_opts.noat = 1; |
3d3c5039 | 9605 | } |
670a50eb ILT |
9606 | else if (strcmp (name, "macro") == 0) |
9607 | { | |
3c83da8a | 9608 | mips_opts.warn_about_macros = 0; |
670a50eb ILT |
9609 | } |
9610 | else if (strcmp (name, "nomacro") == 0) | |
9611 | { | |
3c83da8a | 9612 | if (mips_opts.noreorder == 0) |
670a50eb | 9613 | as_bad ("`noreorder' must be set before `nomacro'"); |
3c83da8a | 9614 | mips_opts.warn_about_macros = 1; |
670a50eb ILT |
9615 | } |
9616 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
9617 | { | |
3c83da8a | 9618 | mips_opts.nomove = 0; |
670a50eb ILT |
9619 | } |
9620 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
9621 | { | |
3c83da8a | 9622 | mips_opts.nomove = 1; |
670a50eb ILT |
9623 | } |
9624 | else if (strcmp (name, "bopt") == 0) | |
9625 | { | |
3c83da8a | 9626 | mips_opts.nobopt = 0; |
670a50eb ILT |
9627 | } |
9628 | else if (strcmp (name, "nobopt") == 0) | |
9629 | { | |
3c83da8a | 9630 | mips_opts.nobopt = 1; |
670a50eb | 9631 | } |
943321c0 ILT |
9632 | else if (strcmp (name, "mips16") == 0 |
9633 | || strcmp (name, "MIPS-16") == 0) | |
3c83da8a | 9634 | mips_opts.mips16 = 1; |
943321c0 ILT |
9635 | else if (strcmp (name, "nomips16") == 0 |
9636 | || strcmp (name, "noMIPS-16") == 0) | |
3c83da8a | 9637 | mips_opts.mips16 = 0; |
1051c97f ILT |
9638 | else if (strncmp (name, "mips", 4) == 0) |
9639 | { | |
9640 | int isa; | |
9641 | ||
9642 | /* Permit the user to change the ISA on the fly. Needless to | |
9643 | say, misuse can cause serious problems. */ | |
9644 | isa = atoi (name + 4); | |
9645 | if (isa == 0) | |
3c83da8a | 9646 | mips_opts.isa = file_mips_isa; |
d8a1c247 | 9647 | else if (isa < 1 || isa > 4) |
1051c97f ILT |
9648 | as_bad ("unknown ISA level"); |
9649 | else | |
3c83da8a | 9650 | mips_opts.isa = isa; |
1051c97f | 9651 | } |
cc5703cd | 9652 | else if (strcmp (name, "autoextend") == 0) |
3c83da8a | 9653 | mips_opts.noautoextend = 0; |
cc5703cd | 9654 | else if (strcmp (name, "noautoextend") == 0) |
3c83da8a JW |
9655 | mips_opts.noautoextend = 1; |
9656 | else if (strcmp (name, "push") == 0) | |
9657 | { | |
9658 | struct mips_option_stack *s; | |
9659 | ||
9660 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
9661 | s->next = mips_opts_stack; | |
9662 | s->options = mips_opts; | |
9663 | mips_opts_stack = s; | |
9664 | } | |
9665 | else if (strcmp (name, "pop") == 0) | |
9666 | { | |
9667 | struct mips_option_stack *s; | |
9668 | ||
9669 | s = mips_opts_stack; | |
9670 | if (s == NULL) | |
9671 | as_bad (".set pop with no .set push"); | |
9672 | else | |
9673 | { | |
9674 | /* If we're changing the reorder mode we need to handle | |
9675 | delay slots correctly. */ | |
9676 | if (s->options.noreorder && ! mips_opts.noreorder) | |
9677 | mips_emit_delays (true); | |
9678 | else if (! s->options.noreorder && mips_opts.noreorder) | |
9679 | { | |
9680 | if (prev_nop_frag != NULL) | |
9681 | { | |
9682 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds | |
9683 | * (mips_opts.mips16 ? 2 : 4)); | |
9684 | prev_nop_frag = NULL; | |
9685 | } | |
9686 | } | |
9687 | ||
9688 | mips_opts = s->options; | |
9689 | mips_opts_stack = s->next; | |
9690 | free (s); | |
9691 | } | |
9692 | } | |
670a50eb ILT |
9693 | else |
9694 | { | |
9695 | as_warn ("Tried to set unrecognized symbol: %s\n", name); | |
9696 | } | |
9697 | *input_line_pointer = ch; | |
9698 | demand_empty_rest_of_line (); | |
3d3c5039 ILT |
9699 | } |
9700 | ||
9226253a ILT |
9701 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to |
9702 | .option pic2. It means to generate SVR4 PIC calls. */ | |
9703 | ||
9704 | static void | |
9705 | s_abicalls (ignore) | |
9706 | int ignore; | |
9707 | { | |
d9aba805 | 9708 | mips_pic = SVR4_PIC; |
1dc1e798 KR |
9709 | if (USE_GLOBAL_POINTER_OPT) |
9710 | { | |
9711 | if (g_switch_seen && g_switch_value != 0) | |
9712 | as_warn ("-G may not be used with SVR4 PIC code"); | |
9713 | g_switch_value = 0; | |
9714 | } | |
d9aba805 | 9715 | bfd_set_gp_size (stdoutput, 0); |
9226253a ILT |
9716 | demand_empty_rest_of_line (); |
9717 | } | |
9718 | ||
9719 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
9720 | PIC code. It sets the $gp register for the function based on the | |
9721 | function address, which is in the register named in the argument. | |
9722 | This uses a relocation against _gp_disp, which is handled specially | |
9723 | by the linker. The result is: | |
9724 | lui $gp,%hi(_gp_disp) | |
9725 | addiu $gp,$gp,%lo(_gp_disp) | |
9726 | addu $gp,$gp,.cpload argument | |
0dd2d296 | 9727 | The .cpload argument is normally $25 == $t9. */ |
9226253a ILT |
9728 | |
9729 | static void | |
9730 | s_cpload (ignore) | |
9731 | int ignore; | |
9732 | { | |
9733 | expressionS ex; | |
9734 | int icnt = 0; | |
9735 | ||
d9aba805 ILT |
9736 | /* If we are not generating SVR4 PIC code, .cpload is ignored. */ |
9737 | if (mips_pic != SVR4_PIC) | |
0dd2d296 ILT |
9738 | { |
9739 | s_ignore (0); | |
9740 | return; | |
9741 | } | |
9742 | ||
9743 | /* .cpload should be a in .set noreorder section. */ | |
3c83da8a | 9744 | if (mips_opts.noreorder == 0) |
0dd2d296 ILT |
9745 | as_warn (".cpload not in noreorder section"); |
9746 | ||
9226253a ILT |
9747 | ex.X_op = O_symbol; |
9748 | ex.X_add_symbol = symbol_find_or_make ("_gp_disp"); | |
9749 | ex.X_op_symbol = NULL; | |
9750 | ex.X_add_number = 0; | |
9751 | ||
fb251650 ILT |
9752 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
9753 | ex.X_add_symbol->bsym->flags |= BSF_OBJECT; | |
9754 | ||
0dd2d296 ILT |
9755 | macro_build_lui ((char *) NULL, &icnt, &ex, GP); |
9756 | macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j", GP, GP, | |
9226253a ILT |
9757 | (int) BFD_RELOC_LO16); |
9758 | ||
0dd2d296 ILT |
9759 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t", |
9760 | GP, GP, tc_get_register (0)); | |
9226253a ILT |
9761 | |
9762 | demand_empty_rest_of_line (); | |
9763 | } | |
9764 | ||
9765 | /* Handle the .cprestore pseudo-op. This stores $gp into a given | |
9766 | offset from $sp. The offset is remembered, and after making a PIC | |
9767 | call $gp is restored from that location. */ | |
9768 | ||
9769 | static void | |
9770 | s_cprestore (ignore) | |
9771 | int ignore; | |
9772 | { | |
9773 | expressionS ex; | |
9774 | int icnt = 0; | |
9775 | ||
d9aba805 ILT |
9776 | /* If we are not generating SVR4 PIC code, .cprestore is ignored. */ |
9777 | if (mips_pic != SVR4_PIC) | |
0dd2d296 ILT |
9778 | { |
9779 | s_ignore (0); | |
9780 | return; | |
9781 | } | |
9782 | ||
9226253a ILT |
9783 | mips_cprestore_offset = get_absolute_expression (); |
9784 | ||
9785 | ex.X_op = O_constant; | |
9786 | ex.X_add_symbol = NULL; | |
9787 | ex.X_op_symbol = NULL; | |
9788 | ex.X_add_number = mips_cprestore_offset; | |
9789 | ||
0dd2d296 | 9790 | macro_build ((char *) NULL, &icnt, &ex, |
3c83da8a | 9791 | mips_opts.isa < 3 ? "sw" : "sd", |
9226253a ILT |
9792 | "t,o(b)", GP, (int) BFD_RELOC_LO16, SP); |
9793 | ||
9794 | demand_empty_rest_of_line (); | |
9795 | } | |
9796 | ||
0dd2d296 ILT |
9797 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
9798 | code. It generates a 32 bit GP relative reloc. */ | |
9799 | ||
9800 | static void | |
9801 | s_gpword (ignore) | |
9802 | int ignore; | |
9803 | { | |
23dc1ae3 | 9804 | symbolS *label; |
0dd2d296 ILT |
9805 | expressionS ex; |
9806 | char *p; | |
9807 | ||
9808 | /* When not generating PIC code, this is treated as .word. */ | |
7dfa376e | 9809 | if (mips_pic != SVR4_PIC) |
0dd2d296 ILT |
9810 | { |
9811 | s_cons (2); | |
9812 | return; | |
9813 | } | |
9814 | ||
fbcfacb7 ILT |
9815 | label = insn_labels != NULL ? insn_labels->label : NULL; |
9816 | mips_emit_delays (true); | |
0dd2d296 | 9817 | if (auto_align) |
23dc1ae3 | 9818 | mips_align (2, 0, label); |
fbcfacb7 | 9819 | mips_clear_insn_labels (); |
0dd2d296 ILT |
9820 | |
9821 | expression (&ex); | |
9822 | ||
9823 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
9824 | { | |
9825 | as_bad ("Unsupported use of .gpword"); | |
9826 | ignore_rest_of_line (); | |
9827 | } | |
9828 | ||
9829 | p = frag_more (4); | |
9830 | md_number_to_chars (p, (valueT) 0, 4); | |
9831 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, 0, | |
9832 | BFD_RELOC_MIPS_GPREL32); | |
9833 | ||
9834 | demand_empty_rest_of_line (); | |
9835 | } | |
9836 | ||
9837 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch | |
9838 | tables in SVR4 PIC code. */ | |
9839 | ||
9840 | static void | |
9841 | s_cpadd (ignore) | |
9842 | int ignore; | |
9843 | { | |
9844 | int icnt = 0; | |
9845 | int reg; | |
9846 | ||
9847 | /* This is ignored when not generating SVR4 PIC code. */ | |
7dfa376e | 9848 | if (mips_pic != SVR4_PIC) |
0dd2d296 ILT |
9849 | { |
9850 | s_ignore (0); | |
9851 | return; | |
9852 | } | |
9853 | ||
9854 | /* Add $gp to the register named as an argument. */ | |
9855 | reg = tc_get_register (0); | |
9856 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3c83da8a | 9857 | mips_opts.isa < 3 ? "addu" : "daddu", |
0dd2d296 ILT |
9858 | "d,v,t", reg, reg, GP); |
9859 | ||
9860 | demand_empty_rest_of_line (); | |
9861 | } | |
9862 | ||
ed3eb786 ILT |
9863 | /* Handle the .insn pseudo-op. This marks instruction labels in |
9864 | mips16 mode. This permits the linker to handle them specially, | |
9865 | such as generating jalx instructions when needed. We also make | |
9866 | them odd for the duration of the assembly, in order to generate the | |
9867 | right sort of code. We will make them even in the adjust_symtab | |
9868 | routine, while leaving them marked. This is convenient for the | |
9869 | debugger and the disassembler. The linker knows to make them odd | |
9870 | again. */ | |
9871 | ||
9872 | static void | |
9873 | s_insn (ignore) | |
9874 | int ignore; | |
9875 | { | |
3c83da8a JW |
9876 | if (mips_opts.mips16) |
9877 | mips16_mark_labels (); | |
ed3eb786 | 9878 | |
3c83da8a JW |
9879 | demand_empty_rest_of_line (); |
9880 | } | |
ed3eb786 | 9881 | |
3c83da8a JW |
9882 | /* Handle a .stabn directive. We need these in order to mark a label |
9883 | as being a mips16 text label correctly. Sometimes the compiler | |
9884 | will emit a label, followed by a .stabn, and then switch sections. | |
9885 | If the label and .stabn are in mips16 mode, then the label is | |
9886 | really a mips16 text label. */ | |
ed3eb786 | 9887 | |
3c83da8a JW |
9888 | static void |
9889 | s_mips_stab (type) | |
9890 | int type; | |
9891 | { | |
9892 | if (type == 'n' && mips_opts.mips16) | |
9893 | mips16_mark_labels (); | |
9894 | ||
9895 | s_stab (type); | |
ed3eb786 ILT |
9896 | } |
9897 | ||
9226253a | 9898 | /* Parse a register string into a number. Called from the ECOFF code |
0dd2d296 ILT |
9899 | to parse .frame. The argument is non-zero if this is the frame |
9900 | register, so that we can record it in mips_frame_reg. */ | |
9226253a | 9901 | |
3d3c5039 | 9902 | int |
0dd2d296 ILT |
9903 | tc_get_register (frame) |
9904 | int frame; | |
3d3c5039 ILT |
9905 | { |
9906 | int reg; | |
9907 | ||
9908 | SKIP_WHITESPACE (); | |
9909 | if (*input_line_pointer++ != '$') | |
9910 | { | |
9911 | as_warn ("expected `$'"); | |
0dd2d296 | 9912 | reg = 0; |
3d3c5039 | 9913 | } |
0dd2d296 | 9914 | else if (isdigit ((unsigned char) *input_line_pointer)) |
3d3c5039 ILT |
9915 | { |
9916 | reg = get_absolute_expression (); | |
9917 | if (reg < 0 || reg >= 32) | |
9918 | { | |
9919 | as_warn ("Bad register number"); | |
9920 | reg = 0; | |
9921 | } | |
9922 | } | |
9923 | else | |
9924 | { | |
9925 | if (strncmp (input_line_pointer, "fp", 2) == 0) | |
9226253a | 9926 | reg = FP; |
3d3c5039 | 9927 | else if (strncmp (input_line_pointer, "sp", 2) == 0) |
9226253a | 9928 | reg = SP; |
3d3c5039 | 9929 | else if (strncmp (input_line_pointer, "gp", 2) == 0) |
9226253a | 9930 | reg = GP; |
3d3c5039 | 9931 | else if (strncmp (input_line_pointer, "at", 2) == 0) |
9226253a | 9932 | reg = AT; |
3d3c5039 ILT |
9933 | else |
9934 | { | |
9935 | as_warn ("Unrecognized register name"); | |
0dd2d296 | 9936 | reg = 0; |
3d3c5039 ILT |
9937 | } |
9938 | input_line_pointer += 2; | |
9939 | } | |
0dd2d296 ILT |
9940 | if (frame) |
9941 | mips_frame_reg = reg != 0 ? reg : SP; | |
3d3c5039 ILT |
9942 | return reg; |
9943 | } | |
9944 | ||
0dd2d296 ILT |
9945 | valueT |
9946 | md_section_align (seg, addr) | |
9947 | asection *seg; | |
9948 | valueT addr; | |
9949 | { | |
9950 | int align = bfd_get_section_alignment (stdoutput, seg); | |
9951 | ||
cf32394d ILT |
9952 | #ifdef OBJ_ELF |
9953 | /* We don't need to align ELF sections to the full alignment. | |
9954 | However, Irix 5 may prefer that we align them at least to a 16 | |
08e17202 ILT |
9955 | byte boundary. We don't bother to align the sections if we are |
9956 | targeted for an embedded system. */ | |
9957 | if (strcmp (TARGET_OS, "elf") == 0) | |
9958 | return addr; | |
943321c0 ILT |
9959 | if (align > 4) |
9960 | align = 4; | |
10a14e36 | 9961 | #endif |
cf32394d ILT |
9962 | |
9963 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
0dd2d296 ILT |
9964 | } |
9965 | ||
d8a1c247 KR |
9966 | /* Utility routine, called from above as well. If called while the |
9967 | input file is still being read, it's only an approximation. (For | |
9968 | example, a symbol may later become defined which appeared to be | |
9969 | undefined earlier.) */ | |
22ba90ce ILT |
9970 | |
9971 | static int | |
85ce5635 | 9972 | nopic_need_relax (sym, before_relaxing) |
d8a1c247 | 9973 | symbolS *sym; |
85ce5635 | 9974 | int before_relaxing; |
d8a1c247 KR |
9975 | { |
9976 | if (sym == 0) | |
9977 | return 0; | |
9978 | ||
1dc1e798 KR |
9979 | if (USE_GLOBAL_POINTER_OPT) |
9980 | { | |
9981 | const char *symname; | |
9982 | int change; | |
9983 | ||
9984 | /* Find out whether this symbol can be referenced off the GP | |
9985 | register. It can be if it is smaller than the -G size or if | |
9986 | it is in the .sdata or .sbss section. Certain symbols can | |
9987 | not be referenced off the GP, although it appears as though | |
9988 | they can. */ | |
9989 | symname = S_GET_NAME (sym); | |
9990 | if (symname != (const char *) NULL | |
9991 | && (strcmp (symname, "eprol") == 0 | |
9992 | || strcmp (symname, "etext") == 0 | |
9993 | || strcmp (symname, "_gp") == 0 | |
9994 | || strcmp (symname, "edata") == 0 | |
9995 | || strcmp (symname, "_fbss") == 0 | |
9996 | || strcmp (symname, "_fdata") == 0 | |
9997 | || strcmp (symname, "_ftext") == 0 | |
9998 | || strcmp (symname, "end") == 0 | |
9999 | || strcmp (symname, "_gp_disp") == 0)) | |
10000 | change = 1; | |
23ac3ca1 | 10001 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) |
c625fc23 JSC |
10002 | && (0 |
10003 | #ifndef NO_ECOFF_DEBUGGING | |
10004 | || (sym->ecoff_extern_size != 0 | |
10005 | && sym->ecoff_extern_size <= g_switch_value) | |
a5586bdc | 10006 | #endif |
85ce5635 ILT |
10007 | /* We must defer this decision until after the whole |
10008 | file has been read, since there might be a .extern | |
10009 | after the first use of this symbol. */ | |
a5586bdc ILT |
10010 | || (before_relaxing |
10011 | #ifndef NO_ECOFF_DEBUGGING | |
10012 | && sym->ecoff_extern_size == 0 | |
c625fc23 | 10013 | #endif |
a5586bdc | 10014 | && S_GET_VALUE (sym) == 0) |
1dc1e798 KR |
10015 | || (S_GET_VALUE (sym) != 0 |
10016 | && S_GET_VALUE (sym) <= g_switch_value))) | |
10017 | change = 0; | |
10018 | else | |
10019 | { | |
10020 | const char *segname; | |
d8a1c247 | 10021 | |
1dc1e798 KR |
10022 | segname = segment_name (S_GET_SEGMENT (sym)); |
10023 | assert (strcmp (segname, ".lit8") != 0 | |
10024 | && strcmp (segname, ".lit4") != 0); | |
10025 | change = (strcmp (segname, ".sdata") != 0 | |
10026 | && strcmp (segname, ".sbss") != 0); | |
10027 | } | |
10028 | return change; | |
10029 | } | |
10030 | else | |
10031 | /* We are not optimizing for the GP register. */ | |
10032 | return 1; | |
d8a1c247 KR |
10033 | } |
10034 | ||
cc5703cd ILT |
10035 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
10036 | extended opcode. SEC is the section the frag is in. */ | |
10037 | ||
10038 | static int | |
10039 | mips16_extended_frag (fragp, sec, stretch) | |
10040 | fragS *fragp; | |
10041 | asection *sec; | |
10042 | long stretch; | |
10043 | { | |
10044 | int type; | |
10045 | register const struct mips16_immed_operand *op; | |
10046 | offsetT val; | |
10047 | int mintiny, maxtiny; | |
f74ba7a3 | 10048 | segT symsec; |
cc5703cd | 10049 | |
8728fa92 ILT |
10050 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) |
10051 | return 0; | |
10052 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
10053 | return 1; | |
10054 | ||
cc5703cd ILT |
10055 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); |
10056 | op = mips16_immed_operands; | |
10057 | while (op->type != type) | |
10058 | { | |
10059 | ++op; | |
10060 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
10061 | } | |
10062 | ||
10063 | if (op->unsp) | |
10064 | { | |
10065 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
10066 | { | |
10067 | mintiny = 1; | |
10068 | maxtiny = 1 << op->nbits; | |
10069 | } | |
10070 | else | |
10071 | { | |
10072 | mintiny = 0; | |
10073 | maxtiny = (1 << op->nbits) - 1; | |
10074 | } | |
10075 | } | |
10076 | else | |
10077 | { | |
10078 | mintiny = - (1 << (op->nbits - 1)); | |
10079 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
10080 | } | |
10081 | ||
f74ba7a3 ILT |
10082 | /* We can't call S_GET_VALUE here, because we don't want to lock in |
10083 | a particular frag address. */ | |
10084 | if (fragp->fr_symbol->sy_value.X_op == O_constant) | |
10085 | { | |
10086 | val = (fragp->fr_symbol->sy_value.X_add_number | |
10087 | + fragp->fr_symbol->sy_frag->fr_address); | |
10088 | symsec = S_GET_SEGMENT (fragp->fr_symbol); | |
10089 | } | |
10090 | else if (fragp->fr_symbol->sy_value.X_op == O_symbol | |
10091 | && (fragp->fr_symbol->sy_value.X_add_symbol->sy_value.X_op | |
10092 | == O_constant)) | |
10093 | { | |
10094 | val = (fragp->fr_symbol->sy_value.X_add_symbol->sy_value.X_add_number | |
10095 | + fragp->fr_symbol->sy_value.X_add_symbol->sy_frag->fr_address | |
10096 | + fragp->fr_symbol->sy_value.X_add_number | |
10097 | + fragp->fr_symbol->sy_frag->fr_address); | |
10098 | symsec = S_GET_SEGMENT (fragp->fr_symbol->sy_value.X_add_symbol); | |
10099 | } | |
10100 | else | |
10101 | return 1; | |
cc5703cd ILT |
10102 | |
10103 | if (op->pcrel) | |
10104 | { | |
10105 | addressT addr; | |
10106 | ||
10107 | /* We won't have the section when we are called from | |
10108 | mips_relax_frag. However, we will always have been called | |
10109 | from md_estimate_size_before_relax first. If this is a | |
10110 | branch to a different section, we mark it as such. If SEC is | |
10111 | NULL, and the frag is not marked, then it must be a branch to | |
10112 | the same section. */ | |
10113 | if (sec == NULL) | |
10114 | { | |
10115 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
10116 | return 1; | |
10117 | } | |
10118 | else | |
10119 | { | |
f74ba7a3 | 10120 | if (symsec != sec) |
cc5703cd ILT |
10121 | { |
10122 | fragp->fr_subtype = | |
10123 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
10124 | ||
10125 | /* FIXME: We should support this, and let the linker | |
10126 | catch branches and loads that are out of range. */ | |
10127 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
10128 | "unsupported PC relative reference to different section"); | |
10129 | ||
10130 | return 1; | |
10131 | } | |
10132 | } | |
10133 | ||
10134 | /* In this case, we know for sure that the symbol fragment is in | |
10135 | the same section. If the fr_address of the symbol fragment | |
10136 | is greater then the address of this fragment we want to add | |
10137 | in STRETCH in order to get a better estimate of the address. | |
10138 | This particularly matters because of the shift bits. */ | |
10139 | if (stretch != 0 | |
10140 | && fragp->fr_symbol->sy_frag->fr_address >= fragp->fr_address) | |
10141 | { | |
10142 | fragS *f; | |
10143 | ||
a941619c ILT |
10144 | /* Adjust stretch for any alignment frag. Note that if have |
10145 | been expanding the earlier code, the symbol may be | |
10146 | defined in what appears to be an earlier frag. FIXME: | |
10147 | This doesn't handle the fr_subtype field, which specifies | |
10148 | a maximum number of bytes to skip when doing an | |
10149 | alignment. */ | |
10150 | for (f = fragp; | |
10151 | f != NULL && f != fragp->fr_symbol->sy_frag; | |
10152 | f = f->fr_next) | |
cc5703cd | 10153 | { |
cc5703cd ILT |
10154 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) |
10155 | { | |
10156 | if (stretch < 0) | |
10157 | stretch = - ((- stretch) | |
10158 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
10159 | else | |
10160 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
10161 | if (stretch == 0) | |
10162 | break; | |
10163 | } | |
10164 | } | |
a941619c ILT |
10165 | if (f != NULL) |
10166 | val += stretch; | |
cc5703cd ILT |
10167 | } |
10168 | ||
a677feeb ILT |
10169 | addr = fragp->fr_address + fragp->fr_fix; |
10170 | ||
10171 | /* The base address rules are complicated. The base address of | |
10172 | a branch is the following instruction. The base address of a | |
10173 | PC relative load or add is the instruction itself, but if it | |
319305a7 ILT |
10174 | is in a delay slot (in which case it can not be extended) use |
10175 | the address of the instruction whose delay slot it is in. */ | |
a677feeb | 10176 | if (type == 'p' || type == 'q') |
fbcfacb7 ILT |
10177 | { |
10178 | addr += 2; | |
319305a7 ILT |
10179 | |
10180 | /* If we are currently assuming that this frag should be | |
10181 | extended, then, the current address is two bytes | |
10182 | higher. */ | |
10183 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
10184 | addr += 2; | |
10185 | ||
fbcfacb7 ILT |
10186 | /* Ignore the low bit in the target, since it will be set |
10187 | for a text label. */ | |
10188 | if ((val & 1) != 0) | |
10189 | --val; | |
10190 | } | |
a677feeb ILT |
10191 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) |
10192 | addr -= 4; | |
10193 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
10194 | addr -= 2; | |
cc5703cd | 10195 | |
cc5703cd ILT |
10196 | val -= addr & ~ ((1 << op->shift) - 1); |
10197 | ||
10198 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
10199 | if (type == 'p' || type == 'q') | |
10200 | val /= 2; | |
10201 | ||
10202 | /* If any of the shifted bits are set, we must use an extended | |
10203 | opcode. If the address depends on the size of this | |
10204 | instruction, this can lead to a loop, so we arrange to always | |
559c664a ILT |
10205 | use an extended opcode. We only check this when we are in |
10206 | the main relaxation loop, when SEC is NULL. */ | |
10207 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
10208 | { | |
10209 | fragp->fr_subtype = | |
10210 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
10211 | return 1; | |
10212 | } | |
10213 | ||
10214 | /* If we are about to mark a frag as extended because the value | |
10215 | is precisely maxtiny + 1, then there is a chance of an | |
10216 | infinite loop as in the following code: | |
10217 | la $4,foo | |
10218 | .skip 1020 | |
10219 | .align 2 | |
10220 | foo: | |
10221 | In this case when the la is extended, foo is 0x3fc bytes | |
10222 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
10223 | the la must be extended. To avoid this loop, we mark the | |
10224 | frag as extended if it was small, and is about to become | |
10225 | extended with a value of maxtiny + 1. */ | |
10226 | if (val == ((maxtiny + 1) << op->shift) | |
10227 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
10228 | && sec == NULL) | |
cc5703cd ILT |
10229 | { |
10230 | fragp->fr_subtype = | |
10231 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
10232 | return 1; | |
10233 | } | |
10234 | } | |
41a0ed22 ILT |
10235 | else if (symsec != absolute_section && sec != NULL) |
10236 | as_bad_where (fragp->fr_file, fragp->fr_line, "unsupported relocation"); | |
cc5703cd ILT |
10237 | |
10238 | if ((val & ((1 << op->shift) - 1)) != 0 | |
10239 | || val < (mintiny << op->shift) | |
10240 | || val > (maxtiny << op->shift)) | |
10241 | return 1; | |
10242 | else | |
10243 | return 0; | |
10244 | } | |
10245 | ||
10246 | /* Estimate the size of a frag before relaxing. Unless this is the | |
10247 | mips16, we are not really relaxing here, and the final size is | |
10248 | encoded in the subtype information. For the mips16, we have to | |
10249 | decide whether we are using an extended opcode or not. */ | |
22ba90ce | 10250 | |
0dd2d296 ILT |
10251 | /*ARGSUSED*/ |
10252 | int | |
10253 | md_estimate_size_before_relax (fragp, segtype) | |
10254 | fragS *fragp; | |
10255 | asection *segtype; | |
10256 | { | |
10257 | int change; | |
10258 | ||
cc5703cd ILT |
10259 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
10260 | { | |
10261 | if (mips16_extended_frag (fragp, segtype, 0)) | |
10262 | { | |
10263 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
10264 | return 4; | |
10265 | } | |
10266 | else | |
10267 | { | |
10268 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
10269 | return 2; | |
10270 | } | |
10271 | } | |
10272 | ||
d9aba805 | 10273 | if (mips_pic == NO_PIC) |
0dd2d296 | 10274 | { |
85ce5635 | 10275 | change = nopic_need_relax (fragp->fr_symbol, 0); |
0dd2d296 | 10276 | } |
d9aba805 | 10277 | else if (mips_pic == SVR4_PIC) |
0dd2d296 | 10278 | { |
46a92fde ILT |
10279 | symbolS *sym; |
10280 | asection *symsec; | |
10281 | ||
10282 | sym = fragp->fr_symbol; | |
10283 | ||
10284 | /* Handle the case of a symbol equated to another symbol. */ | |
10285 | while (sym->sy_value.X_op == O_symbol | |
10286 | && (! S_IS_DEFINED (sym) || S_IS_COMMON (sym))) | |
10287 | { | |
10288 | symbolS *n; | |
10289 | ||
10290 | /* It's possible to get a loop here in a badly written | |
10291 | program. */ | |
10292 | n = sym->sy_value.X_add_symbol; | |
10293 | if (n == sym) | |
10294 | break; | |
10295 | sym = n; | |
10296 | } | |
10297 | ||
10298 | symsec = S_GET_SEGMENT (sym); | |
0dd2d296 ILT |
10299 | |
10300 | /* This must duplicate the test in adjust_reloc_syms. */ | |
10301 | change = (symsec != &bfd_und_section | |
10302 | && symsec != &bfd_abs_section | |
10303 | && ! bfd_is_com_section (symsec)); | |
10304 | } | |
d9aba805 ILT |
10305 | else |
10306 | abort (); | |
0dd2d296 ILT |
10307 | |
10308 | if (change) | |
10309 | { | |
10310 | /* Record the offset to the first reloc in the fr_opcode field. | |
10311 | This lets md_convert_frag and tc_gen_reloc know that the code | |
10312 | must be expanded. */ | |
10313 | fragp->fr_opcode = (fragp->fr_literal | |
10314 | + fragp->fr_fix | |
10315 | - RELAX_OLD (fragp->fr_subtype) | |
10316 | + RELAX_RELOC1 (fragp->fr_subtype)); | |
10317 | /* FIXME: This really needs as_warn_where. */ | |
10318 | if (RELAX_WARN (fragp->fr_subtype)) | |
10319 | as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\""); | |
10320 | } | |
10321 | ||
10322 | if (! change) | |
10323 | return 0; | |
10324 | else | |
10325 | return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype); | |
10326 | } | |
10327 | ||
0d7f9025 ILT |
10328 | /* This is called to see whether a reloc against a defined symbol |
10329 | should be converted into a reloc against a section. Don't adjust | |
10330 | MIPS16 jump relocations, so we don't have to worry about the format | |
10331 | of the offset in the .o file. Don't adjust relocations against | |
6927c24d ILT |
10332 | mips16 symbols, so that the linker can find them if it needs to set |
10333 | up a stub. */ | |
0d7f9025 ILT |
10334 | |
10335 | int | |
10336 | mips_fix_adjustable (fixp) | |
10337 | fixS *fixp; | |
10338 | { | |
10339 | if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) | |
10340 | return 0; | |
10341 | if (fixp->fx_addsy == NULL) | |
10342 | return 1; | |
68952421 | 10343 | #ifdef OBJ_ELF |
0d7f9025 | 10344 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
46a92fde ILT |
10345 | && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 |
10346 | && fixp->fx_subsy == NULL) | |
0d7f9025 ILT |
10347 | return 0; |
10348 | #endif | |
10349 | return 1; | |
10350 | } | |
10351 | ||
0dd2d296 ILT |
10352 | /* Translate internal representation of relocation info to BFD target |
10353 | format. */ | |
10354 | ||
10355 | arelent ** | |
3d3c5039 ILT |
10356 | tc_gen_reloc (section, fixp) |
10357 | asection *section; | |
10358 | fixS *fixp; | |
10359 | { | |
0dd2d296 | 10360 | static arelent *retval[4]; |
3d3c5039 | 10361 | arelent *reloc; |
a8aed9dd | 10362 | bfd_reloc_code_real_type code; |
3d3c5039 | 10363 | |
0dd2d296 ILT |
10364 | reloc = retval[0] = (arelent *) xmalloc (sizeof (arelent)); |
10365 | retval[1] = NULL; | |
3d3c5039 ILT |
10366 | |
10367 | reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym; | |
10368 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
1c803e52 ILT |
10369 | |
10370 | if (mips_pic == EMBEDDED_PIC | |
10371 | && SWITCH_TABLE (fixp)) | |
10372 | { | |
10373 | /* For a switch table entry we use a special reloc. The addend | |
10374 | is actually the difference between the reloc address and the | |
10375 | subtrahend. */ | |
10376 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
1dc1e798 KR |
10377 | if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour) |
10378 | as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc"); | |
1c803e52 ILT |
10379 | fixp->fx_r_type = BFD_RELOC_GPREL32; |
10380 | } | |
ecd4ca1c ILT |
10381 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16) |
10382 | { | |
10383 | /* We use a special addend for an internal RELLO reloc. */ | |
10384 | if (fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) | |
10385 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
10386 | else | |
10387 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
10388 | } | |
10389 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S) | |
10390 | { | |
10391 | assert (fixp->fx_next != NULL | |
10392 | && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16); | |
10393 | /* We use a special addend for an internal RELHI reloc. The | |
10394 | reloc is relative to the RELLO; adjust the addend | |
10395 | accordingly. */ | |
10396 | if (fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) | |
10397 | reloc->addend = (fixp->fx_next->fx_frag->fr_address | |
10398 | + fixp->fx_next->fx_where | |
10399 | - S_GET_VALUE (fixp->fx_subsy)); | |
10400 | else | |
10401 | reloc->addend = (fixp->fx_addnumber | |
10402 | + fixp->fx_next->fx_frag->fr_address | |
10403 | + fixp->fx_next->fx_where); | |
10404 | } | |
1c803e52 | 10405 | else if (fixp->fx_pcrel == 0) |
3d3c5039 ILT |
10406 | reloc->addend = fixp->fx_addnumber; |
10407 | else | |
5b63f465 | 10408 | { |
1dc1e798 KR |
10409 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour) |
10410 | /* A gruesome hack which is a result of the gruesome gas reloc | |
10411 | handling. */ | |
10412 | reloc->addend = reloc->address; | |
10413 | else | |
10414 | reloc->addend = -reloc->address; | |
5b63f465 | 10415 | } |
0dd2d296 ILT |
10416 | |
10417 | /* If this is a variant frag, we may need to adjust the existing | |
10418 | reloc and generate a new one. */ | |
10419 | if (fixp->fx_frag->fr_opcode != NULL | |
10420 | && (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL | |
10421 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
fb251650 ILT |
10422 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16 |
10423 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
10424 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16 | |
10425 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
10426 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16)) | |
0dd2d296 ILT |
10427 | { |
10428 | arelent *reloc2; | |
10429 | ||
cc5703cd ILT |
10430 | assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype)); |
10431 | ||
0dd2d296 | 10432 | /* If this is not the last reloc in this frag, then we have two |
fb251650 ILT |
10433 | GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a |
10434 | CALL_HI16/CALL_LO16, both of which are being replaced. Let | |
10435 | the second one handle all of them. */ | |
0dd2d296 ILT |
10436 | if (fixp->fx_next != NULL |
10437 | && fixp->fx_frag == fixp->fx_next->fx_frag) | |
10438 | { | |
fb251650 ILT |
10439 | assert ((fixp->fx_r_type == BFD_RELOC_MIPS_GPREL |
10440 | && fixp->fx_next->fx_r_type == BFD_RELOC_MIPS_GPREL) | |
10441 | || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
10442 | && (fixp->fx_next->fx_r_type | |
10443 | == BFD_RELOC_MIPS_GOT_LO16)) | |
10444 | || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
10445 | && (fixp->fx_next->fx_r_type | |
10446 | == BFD_RELOC_MIPS_CALL_LO16))); | |
0dd2d296 ILT |
10447 | retval[0] = NULL; |
10448 | return retval; | |
10449 | } | |
10450 | ||
10451 | fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal; | |
10452 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
10453 | reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent)); | |
10454 | retval[2] = NULL; | |
10455 | reloc2->sym_ptr_ptr = &fixp->fx_addsy->bsym; | |
10456 | reloc2->address = (reloc->address | |
10457 | + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype) | |
10458 | - RELAX_RELOC1 (fixp->fx_frag->fr_subtype))); | |
10459 | reloc2->addend = fixp->fx_addnumber; | |
10460 | reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16); | |
10461 | assert (reloc2->howto != NULL); | |
10462 | ||
10463 | if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype)) | |
10464 | { | |
10465 | arelent *reloc3; | |
10466 | ||
10467 | reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent)); | |
10468 | retval[3] = NULL; | |
10469 | *reloc3 = *reloc2; | |
10470 | reloc3->address += 4; | |
10471 | } | |
10472 | ||
d9aba805 | 10473 | if (mips_pic == NO_PIC) |
0dd2d296 ILT |
10474 | { |
10475 | assert (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL); | |
10476 | fixp->fx_r_type = BFD_RELOC_HI16_S; | |
10477 | } | |
d9aba805 | 10478 | else if (mips_pic == SVR4_PIC) |
0dd2d296 | 10479 | { |
fb251650 | 10480 | switch (fixp->fx_r_type) |
0dd2d296 | 10481 | { |
fb251650 ILT |
10482 | default: |
10483 | abort (); | |
10484 | case BFD_RELOC_MIPS_GOT16: | |
10485 | break; | |
10486 | case BFD_RELOC_MIPS_CALL16: | |
10487 | case BFD_RELOC_MIPS_GOT_LO16: | |
10488 | case BFD_RELOC_MIPS_CALL_LO16: | |
0dd2d296 | 10489 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT16; |
fb251650 | 10490 | break; |
0dd2d296 ILT |
10491 | } |
10492 | } | |
d9aba805 ILT |
10493 | else |
10494 | abort (); | |
0dd2d296 ILT |
10495 | } |
10496 | ||
a8aed9dd ILT |
10497 | /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that |
10498 | fixup_segment converted a non-PC relative reloc into a PC | |
10499 | relative reloc. In such a case, we need to convert the reloc | |
10500 | code. */ | |
10501 | code = fixp->fx_r_type; | |
10502 | if (fixp->fx_pcrel) | |
10503 | { | |
10504 | switch (code) | |
10505 | { | |
10506 | case BFD_RELOC_8: | |
10507 | code = BFD_RELOC_8_PCREL; | |
10508 | break; | |
10509 | case BFD_RELOC_16: | |
10510 | code = BFD_RELOC_16_PCREL; | |
10511 | break; | |
10512 | case BFD_RELOC_32: | |
10513 | code = BFD_RELOC_32_PCREL; | |
10514 | break; | |
bf39474f ILT |
10515 | case BFD_RELOC_64: |
10516 | code = BFD_RELOC_64_PCREL; | |
10517 | break; | |
a8aed9dd ILT |
10518 | case BFD_RELOC_8_PCREL: |
10519 | case BFD_RELOC_16_PCREL: | |
10520 | case BFD_RELOC_32_PCREL: | |
bf39474f | 10521 | case BFD_RELOC_64_PCREL: |
a8aed9dd | 10522 | case BFD_RELOC_16_PCREL_S2: |
97aca1bc ILT |
10523 | case BFD_RELOC_PCREL_HI16_S: |
10524 | case BFD_RELOC_PCREL_LO16: | |
a8aed9dd ILT |
10525 | break; |
10526 | default: | |
10527 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
10528 | "Cannot make %s relocation PC relative", | |
10529 | bfd_get_reloc_code_name (code)); | |
10530 | } | |
10531 | } | |
10532 | ||
d9aba805 ILT |
10533 | /* To support a PC relative reloc when generating embedded PIC code |
10534 | for ECOFF, we use a Cygnus extension. We check for that here to | |
10535 | make sure that we don't let such a reloc escape normally. */ | |
1dc1e798 | 10536 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
a8aed9dd | 10537 | && code == BFD_RELOC_16_PCREL_S2 |
d9aba805 ILT |
10538 | && mips_pic != EMBEDDED_PIC) |
10539 | reloc->howto = NULL; | |
10540 | else | |
a8aed9dd | 10541 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
0dd2d296 | 10542 | |
52aa70b5 JW |
10543 | if (reloc->howto == NULL) |
10544 | { | |
10545 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
a8aed9dd ILT |
10546 | "Can not represent %s relocation in this object file format", |
10547 | bfd_get_reloc_code_name (code)); | |
0dd2d296 | 10548 | retval[0] = NULL; |
52aa70b5 | 10549 | } |
3d3c5039 | 10550 | |
0dd2d296 | 10551 | return retval; |
3d3c5039 ILT |
10552 | } |
10553 | ||
cc5703cd ILT |
10554 | /* Relax a machine dependent frag. This returns the amount by which |
10555 | the current size of the frag should change. */ | |
10556 | ||
10557 | int | |
10558 | mips_relax_frag (fragp, stretch) | |
10559 | fragS *fragp; | |
10560 | long stretch; | |
10561 | { | |
10562 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) | |
10563 | return 0; | |
10564 | ||
10565 | if (mips16_extended_frag (fragp, (asection *) NULL, stretch)) | |
10566 | { | |
10567 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
10568 | return 0; | |
10569 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
10570 | return 2; | |
10571 | } | |
10572 | else | |
10573 | { | |
10574 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
10575 | return 0; | |
10576 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
10577 | return -2; | |
10578 | } | |
10579 | ||
10580 | return 0; | |
10581 | } | |
10582 | ||
0dd2d296 ILT |
10583 | /* Convert a machine dependent frag. */ |
10584 | ||
10585 | void | |
10586 | md_convert_frag (abfd, asec, fragp) | |
10587 | bfd *abfd; | |
10588 | segT asec; | |
10589 | fragS *fragp; | |
3d3c5039 | 10590 | { |
0dd2d296 ILT |
10591 | int old, new; |
10592 | char *fixptr; | |
3d3c5039 | 10593 | |
cc5703cd ILT |
10594 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
10595 | { | |
10596 | int type; | |
10597 | register const struct mips16_immed_operand *op; | |
10598 | boolean small, ext; | |
10599 | offsetT val; | |
10600 | bfd_byte *buf; | |
10601 | unsigned long insn; | |
10602 | boolean use_extend; | |
10603 | unsigned short extend; | |
10604 | ||
10605 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
10606 | op = mips16_immed_operands; | |
10607 | while (op->type != type) | |
10608 | ++op; | |
10609 | ||
10610 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
10611 | { | |
10612 | small = false; | |
10613 | ext = true; | |
10614 | } | |
10615 | else | |
10616 | { | |
10617 | small = true; | |
10618 | ext = false; | |
10619 | } | |
10620 | ||
f74ba7a3 | 10621 | resolve_symbol_value (fragp->fr_symbol); |
cc5703cd | 10622 | val = S_GET_VALUE (fragp->fr_symbol); |
cc5703cd ILT |
10623 | if (op->pcrel) |
10624 | { | |
10625 | addressT addr; | |
10626 | ||
a677feeb ILT |
10627 | addr = fragp->fr_address + fragp->fr_fix; |
10628 | ||
10629 | /* The rules for the base address of a PC relative reloc are | |
10630 | complicated; see mips16_extended_frag. */ | |
10631 | if (type == 'p' || type == 'q') | |
fbcfacb7 ILT |
10632 | { |
10633 | addr += 2; | |
319305a7 ILT |
10634 | if (ext) |
10635 | addr += 2; | |
fbcfacb7 ILT |
10636 | /* Ignore the low bit in the target, since it will be |
10637 | set for a text label. */ | |
10638 | if ((val & 1) != 0) | |
10639 | --val; | |
10640 | } | |
a677feeb ILT |
10641 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) |
10642 | addr -= 4; | |
10643 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
10644 | addr -= 2; | |
10645 | ||
cc5703cd ILT |
10646 | addr &= ~ (addressT) ((1 << op->shift) - 1); |
10647 | val -= addr; | |
a677feeb ILT |
10648 | |
10649 | /* Make sure the section winds up with the alignment we have | |
10650 | assumed. */ | |
10651 | if (op->shift > 0) | |
10652 | record_alignment (asec, op->shift); | |
cc5703cd ILT |
10653 | } |
10654 | ||
035936da ILT |
10655 | if (ext |
10656 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
10657 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
10658 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
10659 | "extended instruction in delay slot"); | |
10660 | ||
cc5703cd ILT |
10661 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); |
10662 | ||
b9129c6f ILT |
10663 | if (target_big_endian) |
10664 | insn = bfd_getb16 (buf); | |
10665 | else | |
10666 | insn = bfd_getl16 (buf); | |
cc5703cd | 10667 | |
31a2c6ff ILT |
10668 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, |
10669 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
10670 | small, ext, &insn, &use_extend, &extend); | |
cc5703cd ILT |
10671 | |
10672 | if (use_extend) | |
10673 | { | |
10674 | md_number_to_chars (buf, 0xf000 | extend, 2); | |
10675 | fragp->fr_fix += 2; | |
10676 | buf += 2; | |
10677 | } | |
3d3c5039 | 10678 | |
cc5703cd ILT |
10679 | md_number_to_chars (buf, insn, 2); |
10680 | fragp->fr_fix += 2; | |
10681 | buf += 2; | |
10682 | } | |
10683 | else | |
10684 | { | |
10685 | if (fragp->fr_opcode == NULL) | |
10686 | return; | |
0dd2d296 | 10687 | |
cc5703cd ILT |
10688 | old = RELAX_OLD (fragp->fr_subtype); |
10689 | new = RELAX_NEW (fragp->fr_subtype); | |
10690 | fixptr = fragp->fr_literal + fragp->fr_fix; | |
0dd2d296 | 10691 | |
cc5703cd ILT |
10692 | if (new > 0) |
10693 | memcpy (fixptr - old, fixptr, new); | |
10694 | ||
10695 | fragp->fr_fix += new - old; | |
10696 | } | |
0dd2d296 | 10697 | } |
becfe05e | 10698 | |
fbcfacb7 ILT |
10699 | #ifdef OBJ_ELF |
10700 | ||
10701 | /* This function is called after the relocs have been generated. | |
10702 | We've been storing mips16 text labels as odd. Here we convert them | |
10703 | back to even for the convenience of the debugger. */ | |
10704 | ||
10705 | void | |
10706 | mips_frob_file_after_relocs () | |
10707 | { | |
10708 | asymbol **syms; | |
10709 | unsigned int count, i; | |
10710 | ||
10711 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10712 | return; | |
10713 | ||
10714 | syms = bfd_get_outsymbols (stdoutput); | |
10715 | count = bfd_get_symcount (stdoutput); | |
10716 | for (i = 0; i < count; i++, syms++) | |
10717 | { | |
10718 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
10719 | && ((*syms)->value & 1) != 0) | |
10720 | { | |
10721 | (*syms)->value &= ~1; | |
10722 | /* If the symbol has an odd size, it was probably computed | |
10723 | incorrectly, so adjust that as well. */ | |
10724 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
10725 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
10726 | } | |
10727 | } | |
10728 | } | |
10729 | ||
10730 | #endif | |
10731 | ||
becfe05e ILT |
10732 | /* This function is called whenever a label is defined. It is used |
10733 | when handling branch delays; if a branch has a label, we assume we | |
10734 | can not move it. */ | |
10735 | ||
10736 | void | |
10737 | mips_define_label (sym) | |
10738 | symbolS *sym; | |
10739 | { | |
fbcfacb7 ILT |
10740 | struct insn_label_list *l; |
10741 | ||
10742 | if (free_insn_labels == NULL) | |
10743 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
10744 | else | |
10745 | { | |
10746 | l = free_insn_labels; | |
10747 | free_insn_labels = l->next; | |
10748 | } | |
10749 | ||
10750 | l->label = sym; | |
10751 | l->next = insn_labels; | |
10752 | insn_labels = l; | |
becfe05e | 10753 | } |
3d3c5039 | 10754 | \f |
739708fa | 10755 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
f2a663d3 | 10756 | |
0dd2d296 | 10757 | /* Some special processing for a MIPS ELF file. */ |
f2a663d3 ILT |
10758 | |
10759 | void | |
10760 | mips_elf_final_processing () | |
10761 | { | |
87178180 ILT |
10762 | /* Write out the register information. */ |
10763 | if (! mips_64) | |
10764 | { | |
10765 | Elf32_RegInfo s; | |
10766 | ||
10767 | s.ri_gprmask = mips_gprmask; | |
10768 | s.ri_cprmask[0] = mips_cprmask[0]; | |
10769 | s.ri_cprmask[1] = mips_cprmask[1]; | |
10770 | s.ri_cprmask[2] = mips_cprmask[2]; | |
10771 | s.ri_cprmask[3] = mips_cprmask[3]; | |
10772 | /* The gp_value field is set by the MIPS ELF backend. */ | |
10773 | ||
10774 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
10775 | ((Elf32_External_RegInfo *) | |
10776 | mips_regmask_frag)); | |
10777 | } | |
10778 | else | |
10779 | { | |
10780 | Elf64_Internal_RegInfo s; | |
10781 | ||
10782 | s.ri_gprmask = mips_gprmask; | |
10783 | s.ri_pad = 0; | |
10784 | s.ri_cprmask[0] = mips_cprmask[0]; | |
10785 | s.ri_cprmask[1] = mips_cprmask[1]; | |
10786 | s.ri_cprmask[2] = mips_cprmask[2]; | |
10787 | s.ri_cprmask[3] = mips_cprmask[3]; | |
10788 | /* The gp_value field is set by the MIPS ELF backend. */ | |
10789 | ||
10790 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
10791 | ((Elf64_External_RegInfo *) | |
10792 | mips_regmask_frag)); | |
10793 | } | |
0dd2d296 ILT |
10794 | |
10795 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
10796 | sort of BFD interface for this. */ | |
10797 | if (mips_any_noreorder) | |
10798 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
d9aba805 | 10799 | if (mips_pic != NO_PIC) |
0dd2d296 | 10800 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
f2a663d3 ILT |
10801 | } |
10802 | ||
739708fa | 10803 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |
f2a663d3 | 10804 | \f |
3d3c5039 ILT |
10805 | /* These functions should really be defined by the object file format, |
10806 | since they are related to debugging information. However, this | |
10807 | code has to work for the a.out format, which does not define them, | |
10808 | so we provide simple versions here. These don't actually generate | |
10809 | any debugging information, but they do simple checking and someday | |
10810 | somebody may make them useful. */ | |
10811 | ||
670a50eb ILT |
10812 | typedef struct loc |
10813 | { | |
10814 | struct loc *loc_next; | |
10815 | unsigned long loc_fileno; | |
10816 | unsigned long loc_lineno; | |
10817 | unsigned long loc_offset; | |
10818 | unsigned short loc_delta; | |
10819 | unsigned short loc_count; | |
3d3c5039 | 10820 | #if 0 |
670a50eb | 10821 | fragS *loc_frag; |
3d3c5039 | 10822 | #endif |
670a50eb ILT |
10823 | } |
10824 | locS; | |
3d3c5039 | 10825 | |
670a50eb ILT |
10826 | typedef struct proc |
10827 | { | |
3d3c5039 ILT |
10828 | struct proc *proc_next; |
10829 | struct symbol *proc_isym; | |
10830 | struct symbol *proc_end; | |
10831 | unsigned long proc_reg_mask; | |
10832 | unsigned long proc_reg_offset; | |
10833 | unsigned long proc_fpreg_mask; | |
10834 | unsigned long proc_fpreg_offset; | |
10835 | unsigned long proc_frameoffset; | |
10836 | unsigned long proc_framereg; | |
10837 | unsigned long proc_pcreg; | |
10838 | locS *proc_iline; | |
10839 | struct file *proc_file; | |
10840 | int proc_index; | |
670a50eb ILT |
10841 | } |
10842 | procS; | |
3d3c5039 | 10843 | |
670a50eb ILT |
10844 | typedef struct file |
10845 | { | |
3d3c5039 ILT |
10846 | struct file *file_next; |
10847 | unsigned long file_fileno; | |
10848 | struct symbol *file_symbol; | |
10849 | struct symbol *file_end; | |
10850 | struct proc *file_proc; | |
10851 | int file_numprocs; | |
670a50eb ILT |
10852 | } |
10853 | fileS; | |
3d3c5039 ILT |
10854 | |
10855 | static struct obstack proc_frags; | |
10856 | static procS *proc_lastP; | |
10857 | static procS *proc_rootP; | |
10858 | static int numprocs; | |
10859 | ||
10860 | static void | |
10861 | md_obj_begin () | |
10862 | { | |
670a50eb | 10863 | obstack_begin (&proc_frags, 0x2000); |
3d3c5039 ILT |
10864 | } |
10865 | ||
10866 | static void | |
10867 | md_obj_end () | |
10868 | { | |
10869 | /* check for premature end, nesting errors, etc */ | |
10870 | if (proc_lastP && proc_lastP->proc_end == NULL) | |
670a50eb | 10871 | as_warn ("missing `.end' at end of assembly"); |
3d3c5039 ILT |
10872 | } |
10873 | ||
3d3c5039 ILT |
10874 | static long |
10875 | get_number () | |
10876 | { | |
670a50eb ILT |
10877 | int negative = 0; |
10878 | long val = 0; | |
3d3c5039 | 10879 | |
670a50eb ILT |
10880 | if (*input_line_pointer == '-') |
10881 | { | |
10882 | ++input_line_pointer; | |
10883 | negative = 1; | |
3d3c5039 | 10884 | } |
670a50eb ILT |
10885 | if (!isdigit (*input_line_pointer)) |
10886 | as_bad ("Expected simple number."); | |
10887 | if (input_line_pointer[0] == '0') | |
10888 | { | |
10889 | if (input_line_pointer[1] == 'x') | |
10890 | { | |
10891 | input_line_pointer += 2; | |
10892 | while (isxdigit (*input_line_pointer)) | |
10893 | { | |
10894 | val <<= 4; | |
3a762a0b | 10895 | val |= hex_value (*input_line_pointer++); |
3d3c5039 | 10896 | } |
670a50eb ILT |
10897 | return negative ? -val : val; |
10898 | } | |
10899 | else | |
10900 | { | |
10901 | ++input_line_pointer; | |
10902 | while (isdigit (*input_line_pointer)) | |
10903 | { | |
10904 | val <<= 3; | |
10905 | val |= *input_line_pointer++ - '0'; | |
3d3c5039 | 10906 | } |
670a50eb | 10907 | return negative ? -val : val; |
3d3c5039 ILT |
10908 | } |
10909 | } | |
670a50eb ILT |
10910 | if (!isdigit (*input_line_pointer)) |
10911 | { | |
10912 | printf (" *input_line_pointer == '%c' 0x%02x\n", | |
10913 | *input_line_pointer, *input_line_pointer); | |
10914 | as_warn ("Invalid number"); | |
10915 | return -1; | |
3d3c5039 | 10916 | } |
670a50eb ILT |
10917 | while (isdigit (*input_line_pointer)) |
10918 | { | |
10919 | val *= 10; | |
10920 | val += *input_line_pointer++ - '0'; | |
3d3c5039 | 10921 | } |
670a50eb | 10922 | return negative ? -val : val; |
3d3c5039 ILT |
10923 | } |
10924 | ||
10925 | /* The .file directive; just like the usual .file directive, but there | |
10926 | is an initial number which is the ECOFF file index. */ | |
10927 | ||
10928 | static void | |
10929 | s_file (x) | |
10930 | int x; | |
10931 | { | |
670a50eb | 10932 | int line; |
3d3c5039 | 10933 | |
670a50eb | 10934 | line = get_number (); |
9a7d824a | 10935 | s_app_file (0); |
3d3c5039 ILT |
10936 | } |
10937 | ||
10938 | ||
10939 | /* The .end directive. */ | |
10940 | ||
10941 | static void | |
10942 | s_mipsend (x) | |
10943 | int x; | |
10944 | { | |
670a50eb ILT |
10945 | symbolS *p; |
10946 | ||
10947 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
10948 | { | |
10949 | p = get_symbol (); | |
10950 | demand_empty_rest_of_line (); | |
10951 | } | |
10952 | else | |
10953 | p = NULL; | |
10954 | if (now_seg != text_section) | |
10955 | as_warn (".end not in text section"); | |
10956 | if (!proc_lastP) | |
10957 | { | |
10958 | as_warn (".end and no .ent seen yet."); | |
10959 | return; | |
3d3c5039 ILT |
10960 | } |
10961 | ||
670a50eb ILT |
10962 | if (p != NULL) |
10963 | { | |
10964 | assert (S_GET_NAME (p)); | |
10965 | if (strcmp (S_GET_NAME (p), S_GET_NAME (proc_lastP->proc_isym))) | |
10966 | as_warn (".end symbol does not match .ent symbol."); | |
3d3c5039 ILT |
10967 | } |
10968 | ||
670a50eb | 10969 | proc_lastP->proc_end = (symbolS *) 1; |
3d3c5039 ILT |
10970 | } |
10971 | ||
10972 | /* The .aent and .ent directives. */ | |
10973 | ||
10974 | static void | |
10975 | s_ent (aent) | |
10976 | int aent; | |
10977 | { | |
670a50eb ILT |
10978 | int number = 0; |
10979 | procS *procP; | |
10980 | symbolS *symbolP; | |
10981 | ||
10982 | symbolP = get_symbol (); | |
10983 | if (*input_line_pointer == ',') | |
10984 | input_line_pointer++; | |
dd3f1f76 | 10985 | SKIP_WHITESPACE (); |
670a50eb ILT |
10986 | if (isdigit (*input_line_pointer) || *input_line_pointer == '-') |
10987 | number = get_number (); | |
10988 | if (now_seg != text_section) | |
10989 | as_warn (".ent or .aent not in text section."); | |
10990 | ||
10991 | if (!aent && proc_lastP && proc_lastP->proc_end == NULL) | |
10992 | as_warn ("missing `.end'"); | |
10993 | ||
10994 | if (!aent) | |
10995 | { | |
10996 | procP = (procS *) obstack_alloc (&proc_frags, sizeof (*procP)); | |
10997 | procP->proc_isym = symbolP; | |
10998 | procP->proc_reg_mask = 0; | |
10999 | procP->proc_reg_offset = 0; | |
11000 | procP->proc_fpreg_mask = 0; | |
11001 | procP->proc_fpreg_offset = 0; | |
11002 | procP->proc_frameoffset = 0; | |
11003 | procP->proc_framereg = 0; | |
11004 | procP->proc_pcreg = 0; | |
11005 | procP->proc_end = NULL; | |
11006 | procP->proc_next = NULL; | |
11007 | if (proc_lastP) | |
11008 | proc_lastP->proc_next = procP; | |
11009 | else | |
11010 | proc_rootP = procP; | |
11011 | proc_lastP = procP; | |
11012 | numprocs++; | |
3d3c5039 | 11013 | } |
670a50eb | 11014 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
11015 | } |
11016 | ||
11017 | /* The .frame directive. */ | |
11018 | ||
88225433 | 11019 | #if 0 |
3d3c5039 ILT |
11020 | static void |
11021 | s_frame (x) | |
670a50eb | 11022 | int x; |
3d3c5039 | 11023 | { |
670a50eb ILT |
11024 | char str[100]; |
11025 | symbolS *symP; | |
11026 | int frame_reg; | |
11027 | int frame_off; | |
11028 | int pcreg; | |
11029 | ||
0dd2d296 | 11030 | frame_reg = tc_get_register (1); |
670a50eb ILT |
11031 | if (*input_line_pointer == ',') |
11032 | input_line_pointer++; | |
5ac34ac3 | 11033 | frame_off = get_absolute_expression (); |
670a50eb ILT |
11034 | if (*input_line_pointer == ',') |
11035 | input_line_pointer++; | |
0dd2d296 | 11036 | pcreg = tc_get_register (0); |
670a50eb ILT |
11037 | |
11038 | /* bob third eye */ | |
11039 | assert (proc_rootP); | |
11040 | proc_rootP->proc_framereg = frame_reg; | |
11041 | proc_rootP->proc_frameoffset = frame_off; | |
11042 | proc_rootP->proc_pcreg = pcreg; | |
11043 | /* bob macho .frame */ | |
11044 | ||
11045 | /* We don't have to write out a frame stab for unoptimized code. */ | |
9226253a | 11046 | if (!(frame_reg == FP && frame_off == 0)) |
670a50eb ILT |
11047 | { |
11048 | if (!proc_lastP) | |
11049 | as_warn ("No .ent for .frame to use."); | |
11050 | (void) sprintf (str, "R%d;%d", frame_reg, frame_off); | |
11051 | symP = symbol_new (str, N_VFP, 0, frag_now); | |
11052 | S_SET_TYPE (symP, N_RMASK); | |
11053 | S_SET_OTHER (symP, 0); | |
11054 | S_SET_DESC (symP, 0); | |
11055 | symP->sy_forward = proc_lastP->proc_isym; | |
11056 | /* bob perhaps I should have used pseudo set */ | |
3d3c5039 | 11057 | } |
670a50eb | 11058 | demand_empty_rest_of_line (); |
3d3c5039 | 11059 | } |
88225433 | 11060 | #endif |
3d3c5039 ILT |
11061 | |
11062 | /* The .fmask and .mask directives. */ | |
11063 | ||
88225433 | 11064 | #if 0 |
3d3c5039 ILT |
11065 | static void |
11066 | s_mask (reg_type) | |
11067 | char reg_type; | |
11068 | { | |
670a50eb ILT |
11069 | char str[100], *strP; |
11070 | symbolS *symP; | |
11071 | int i; | |
11072 | unsigned int mask; | |
11073 | int off; | |
11074 | ||
11075 | mask = get_number (); | |
11076 | if (*input_line_pointer == ',') | |
11077 | input_line_pointer++; | |
11078 | off = get_absolute_expression (); | |
11079 | ||
11080 | /* bob only for coff */ | |
11081 | assert (proc_rootP); | |
11082 | if (reg_type == 'F') | |
11083 | { | |
11084 | proc_rootP->proc_fpreg_mask = mask; | |
11085 | proc_rootP->proc_fpreg_offset = off; | |
3d3c5039 | 11086 | } |
670a50eb ILT |
11087 | else |
11088 | { | |
11089 | proc_rootP->proc_reg_mask = mask; | |
11090 | proc_rootP->proc_reg_offset = off; | |
11091 | } | |
11092 | ||
11093 | /* bob macho .mask + .fmask */ | |
3d3c5039 | 11094 | |
670a50eb ILT |
11095 | /* We don't have to write out a mask stab if no saved regs. */ |
11096 | if (!(mask == 0)) | |
11097 | { | |
11098 | if (!proc_lastP) | |
11099 | as_warn ("No .ent for .mask to use."); | |
11100 | strP = str; | |
11101 | for (i = 0; i < 32; i++) | |
11102 | { | |
11103 | if (mask % 2) | |
11104 | { | |
11105 | sprintf (strP, "%c%d,", reg_type, i); | |
11106 | strP += strlen (strP); | |
11107 | } | |
3d3c5039 | 11108 | mask /= 2; |
670a50eb ILT |
11109 | } |
11110 | sprintf (strP, ";%d,", off); | |
11111 | symP = symbol_new (str, N_RMASK, 0, frag_now); | |
11112 | S_SET_TYPE (symP, N_RMASK); | |
11113 | S_SET_OTHER (symP, 0); | |
11114 | S_SET_DESC (symP, 0); | |
11115 | symP->sy_forward = proc_lastP->proc_isym; | |
11116 | /* bob perhaps I should have used pseudo set */ | |
3d3c5039 | 11117 | } |
3d3c5039 | 11118 | } |
88225433 | 11119 | #endif |
3d3c5039 ILT |
11120 | |
11121 | /* The .loc directive. */ | |
11122 | ||
88225433 | 11123 | #if 0 |
3d3c5039 ILT |
11124 | static void |
11125 | s_loc (x) | |
11126 | int x; | |
11127 | { | |
670a50eb ILT |
11128 | symbolS *symbolP; |
11129 | int lineno; | |
11130 | int addroff; | |
3d3c5039 | 11131 | |
670a50eb | 11132 | assert (now_seg == text_section); |
3d3c5039 | 11133 | |
670a50eb | 11134 | lineno = get_number (); |
87e48495 | 11135 | addroff = frag_now_fix (); |
3d3c5039 | 11136 | |
670a50eb ILT |
11137 | symbolP = symbol_new ("", N_SLINE, addroff, frag_now); |
11138 | S_SET_TYPE (symbolP, N_SLINE); | |
11139 | S_SET_OTHER (symbolP, 0); | |
11140 | S_SET_DESC (symbolP, lineno); | |
11141 | symbolP->sy_segment = now_seg; | |
3d3c5039 | 11142 | } |
88225433 | 11143 | #endif |