Commit | Line | Data |
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252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
2571583a | 2 | Copyright (C) 1993-2017 Free Software Foundation, Inc. |
252b5132 RH |
3 | Contributed by the OSF and Ralph Campbell. |
4 | Written by Keith Knowles and Ralph Campbell, working independently. | |
5 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
6 | Support. | |
7 | ||
8 | This file is part of GAS. | |
9 | ||
10 | GAS is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 12 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
13 | any later version. |
14 | ||
15 | GAS is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
21 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
22 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
23 | 02110-1301, USA. */ | |
252b5132 RH |
24 | |
25 | #include "as.h" | |
26 | #include "config.h" | |
27 | #include "subsegs.h" | |
3882b010 | 28 | #include "safe-ctype.h" |
252b5132 | 29 | |
252b5132 RH |
30 | #include "opcode/mips.h" |
31 | #include "itbl-ops.h" | |
c5dd6aab | 32 | #include "dwarf2dbg.h" |
5862107c | 33 | #include "dw2gencfi.h" |
252b5132 | 34 | |
42429eac RS |
35 | /* Check assumptions made in this file. */ |
36 | typedef char static_assert1[sizeof (offsetT) < 8 ? -1 : 1]; | |
37 | typedef char static_assert2[sizeof (valueT) < 8 ? -1 : 1]; | |
38 | ||
252b5132 RH |
39 | #ifdef DEBUG |
40 | #define DBG(x) printf x | |
41 | #else | |
42 | #define DBG(x) | |
43 | #endif | |
44 | ||
263b2574 | 45 | #define streq(a, b) (strcmp (a, b) == 0) |
46 | ||
9e12b7a2 RS |
47 | #define SKIP_SPACE_TABS(S) \ |
48 | do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0) | |
49 | ||
252b5132 | 50 | /* Clean up namespace so we can include obj-elf.h too. */ |
17a2f251 TS |
51 | static int mips_output_flavor (void); |
52 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
53 | #undef OBJ_PROCESS_STAB |
54 | #undef OUTPUT_FLAVOR | |
55 | #undef S_GET_ALIGN | |
56 | #undef S_GET_SIZE | |
57 | #undef S_SET_ALIGN | |
58 | #undef S_SET_SIZE | |
252b5132 RH |
59 | #undef obj_frob_file |
60 | #undef obj_frob_file_after_relocs | |
61 | #undef obj_frob_symbol | |
62 | #undef obj_pop_insert | |
63 | #undef obj_sec_sym_ok_for_reloc | |
64 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
65 | ||
66 | #include "obj-elf.h" | |
67 | /* Fix any of them that we actually care about. */ | |
68 | #undef OUTPUT_FLAVOR | |
69 | #define OUTPUT_FLAVOR mips_output_flavor() | |
252b5132 | 70 | |
252b5132 | 71 | #include "elf/mips.h" |
252b5132 RH |
72 | |
73 | #ifndef ECOFF_DEBUGGING | |
74 | #define NO_ECOFF_DEBUGGING | |
75 | #define ECOFF_DEBUGGING 0 | |
76 | #endif | |
77 | ||
ecb4347a DJ |
78 | int mips_flag_mdebug = -1; |
79 | ||
dcd410fe RO |
80 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
81 | linker doesn't know about and discards them, but relocations against them | |
82 | remain, leading to rld crashes. */ | |
83 | #ifdef TE_IRIX | |
84 | int mips_flag_pdr = FALSE; | |
85 | #else | |
86 | int mips_flag_pdr = TRUE; | |
87 | #endif | |
88 | ||
252b5132 RH |
89 | #include "ecoff.h" |
90 | ||
252b5132 | 91 | static char *mips_regmask_frag; |
351cdf24 | 92 | static char *mips_flags_frag; |
252b5132 | 93 | |
85b51719 | 94 | #define ZERO 0 |
741fe287 | 95 | #define ATREG 1 |
df58fc94 RS |
96 | #define S0 16 |
97 | #define S7 23 | |
252b5132 RH |
98 | #define TREG 24 |
99 | #define PIC_CALL_REG 25 | |
100 | #define KT0 26 | |
101 | #define KT1 27 | |
102 | #define GP 28 | |
103 | #define SP 29 | |
104 | #define FP 30 | |
105 | #define RA 31 | |
106 | ||
107 | #define ILLEGAL_REG (32) | |
108 | ||
741fe287 MR |
109 | #define AT mips_opts.at |
110 | ||
252b5132 RH |
111 | extern int target_big_endian; |
112 | ||
252b5132 | 113 | /* The name of the readonly data section. */ |
e8044f35 | 114 | #define RDATA_SECTION_NAME ".rodata" |
252b5132 | 115 | |
a4e06468 RS |
116 | /* Ways in which an instruction can be "appended" to the output. */ |
117 | enum append_method { | |
118 | /* Just add it normally. */ | |
119 | APPEND_ADD, | |
120 | ||
121 | /* Add it normally and then add a nop. */ | |
122 | APPEND_ADD_WITH_NOP, | |
123 | ||
124 | /* Turn an instruction with a delay slot into a "compact" version. */ | |
125 | APPEND_ADD_COMPACT, | |
126 | ||
127 | /* Insert the instruction before the last one. */ | |
128 | APPEND_SWAP | |
129 | }; | |
130 | ||
47e39b9d RS |
131 | /* Information about an instruction, including its format, operands |
132 | and fixups. */ | |
133 | struct mips_cl_insn | |
134 | { | |
135 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ | |
136 | const struct mips_opcode *insn_mo; | |
137 | ||
47e39b9d | 138 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is |
5c04167a RS |
139 | a copy of INSN_MO->match with the operands filled in. If we have |
140 | decided to use an extended MIPS16 instruction, this includes the | |
141 | extension. */ | |
47e39b9d RS |
142 | unsigned long insn_opcode; |
143 | ||
144 | /* The frag that contains the instruction. */ | |
145 | struct frag *frag; | |
146 | ||
147 | /* The offset into FRAG of the first instruction byte. */ | |
148 | long where; | |
149 | ||
150 | /* The relocs associated with the instruction, if any. */ | |
151 | fixS *fixp[3]; | |
152 | ||
a38419a5 RS |
153 | /* True if this entry cannot be moved from its current position. */ |
154 | unsigned int fixed_p : 1; | |
47e39b9d | 155 | |
708587a4 | 156 | /* True if this instruction occurred in a .set noreorder block. */ |
47e39b9d RS |
157 | unsigned int noreorder_p : 1; |
158 | ||
2fa15973 RS |
159 | /* True for mips16 instructions that jump to an absolute address. */ |
160 | unsigned int mips16_absolute_jump_p : 1; | |
15be625d CM |
161 | |
162 | /* True if this instruction is complete. */ | |
163 | unsigned int complete_p : 1; | |
e407c74b NC |
164 | |
165 | /* True if this instruction is cleared from history by unconditional | |
166 | branch. */ | |
167 | unsigned int cleared_p : 1; | |
47e39b9d RS |
168 | }; |
169 | ||
a325df1d TS |
170 | /* The ABI to use. */ |
171 | enum mips_abi_level | |
172 | { | |
173 | NO_ABI = 0, | |
174 | O32_ABI, | |
175 | O64_ABI, | |
176 | N32_ABI, | |
177 | N64_ABI, | |
178 | EABI_ABI | |
179 | }; | |
180 | ||
181 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 182 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 183 | |
143d77c5 EC |
184 | /* Whether or not we have code that can call pic code. */ |
185 | int mips_abicalls = FALSE; | |
186 | ||
aa6975fb ILT |
187 | /* Whether or not we have code which can be put into a shared |
188 | library. */ | |
189 | static bfd_boolean mips_in_shared = TRUE; | |
190 | ||
252b5132 RH |
191 | /* This is the set of options which may be modified by the .set |
192 | pseudo-op. We use a struct so that .set push and .set pop are more | |
193 | reliable. */ | |
194 | ||
e972090a NC |
195 | struct mips_set_options |
196 | { | |
252b5132 RH |
197 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
198 | if it has not been initialized. Changed by `.set mipsN', and the | |
199 | -mipsN command line option, and the default CPU. */ | |
200 | int isa; | |
846ef2d0 RS |
201 | /* Enabled Application Specific Extensions (ASEs). Changed by `.set |
202 | <asename>', by command line options, and based on the default | |
203 | architecture. */ | |
204 | int ase; | |
252b5132 RH |
205 | /* Whether we are assembling for the mips16 processor. 0 if we are |
206 | not, 1 if we are, and -1 if the value has not been initialized. | |
207 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
208 | -nomips16 command line options, and the default CPU. */ | |
209 | int mips16; | |
df58fc94 RS |
210 | /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not, |
211 | 1 if we are, and -1 if the value has not been initialized. Changed | |
212 | by `.set micromips' and `.set nomicromips', and the -mmicromips | |
213 | and -mno-micromips command line options, and the default CPU. */ | |
214 | int micromips; | |
252b5132 RH |
215 | /* Non-zero if we should not reorder instructions. Changed by `.set |
216 | reorder' and `.set noreorder'. */ | |
217 | int noreorder; | |
741fe287 MR |
218 | /* Non-zero if we should not permit the register designated "assembler |
219 | temporary" to be used in instructions. The value is the register | |
220 | number, normally $at ($1). Changed by `.set at=REG', `.set noat' | |
221 | (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */ | |
222 | unsigned int at; | |
252b5132 RH |
223 | /* Non-zero if we should warn when a macro instruction expands into |
224 | more than one machine instruction. Changed by `.set nomacro' and | |
225 | `.set macro'. */ | |
226 | int warn_about_macros; | |
227 | /* Non-zero if we should not move instructions. Changed by `.set | |
228 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
229 | int nomove; | |
230 | /* Non-zero if we should not optimize branches by moving the target | |
231 | of the branch into the delay slot. Actually, we don't perform | |
232 | this optimization anyhow. Changed by `.set bopt' and `.set | |
233 | nobopt'. */ | |
234 | int nobopt; | |
235 | /* Non-zero if we should not autoextend mips16 instructions. | |
236 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
237 | int noautoextend; | |
833794fc MR |
238 | /* True if we should only emit 32-bit microMIPS instructions. |
239 | Changed by `.set insn32' and `.set noinsn32', and the -minsn32 | |
240 | and -mno-insn32 command line options. */ | |
241 | bfd_boolean insn32; | |
a325df1d TS |
242 | /* Restrict general purpose registers and floating point registers |
243 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
244 | is passed but can changed if the assembler code uses .set mipsN. */ | |
bad1aba3 | 245 | int gp; |
0b35dfee | 246 | int fp; |
fef14a42 TS |
247 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
248 | command line option, and the default CPU. */ | |
249 | int arch; | |
aed1a261 RS |
250 | /* True if ".set sym32" is in effect. */ |
251 | bfd_boolean sym32; | |
037b32b9 AN |
252 | /* True if floating-point operations are not allowed. Changed by .set |
253 | softfloat or .set hardfloat, by command line options -msoft-float or | |
254 | -mhard-float. The default is false. */ | |
255 | bfd_boolean soft_float; | |
256 | ||
257 | /* True if only single-precision floating-point operations are allowed. | |
258 | Changed by .set singlefloat or .set doublefloat, command-line options | |
259 | -msingle-float or -mdouble-float. The default is false. */ | |
260 | bfd_boolean single_float; | |
351cdf24 MF |
261 | |
262 | /* 1 if single-precision operations on odd-numbered registers are | |
263 | allowed. */ | |
264 | int oddspreg; | |
252b5132 RH |
265 | }; |
266 | ||
919731af | 267 | /* Specifies whether module level options have been checked yet. */ |
268 | static bfd_boolean file_mips_opts_checked = FALSE; | |
269 | ||
7361da2c AB |
270 | /* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the |
271 | value has not been initialized. Changed by `.nan legacy' and | |
272 | `.nan 2008', and the -mnan=legacy and -mnan=2008 command line | |
273 | options, and the default CPU. */ | |
274 | static int mips_nan2008 = -1; | |
a325df1d | 275 | |
0b35dfee | 276 | /* This is the struct we use to hold the module level set of options. |
bad1aba3 | 277 | Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and |
0b35dfee | 278 | fp fields to -1 to indicate that they have not been initialized. */ |
037b32b9 | 279 | |
0b35dfee | 280 | static struct mips_set_options file_mips_opts = |
281 | { | |
282 | /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1, | |
283 | /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0, | |
284 | /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE, | |
bad1aba3 | 285 | /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE, |
351cdf24 | 286 | /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1 |
0b35dfee | 287 | }; |
252b5132 | 288 | |
0b35dfee | 289 | /* This is similar to file_mips_opts, but for the current set of options. */ |
ba92f887 | 290 | |
e972090a NC |
291 | static struct mips_set_options mips_opts = |
292 | { | |
846ef2d0 | 293 | /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1, |
b015e599 | 294 | /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0, |
833794fc | 295 | /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE, |
bad1aba3 | 296 | /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE, |
351cdf24 | 297 | /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1 |
e7af610e | 298 | }; |
252b5132 | 299 | |
846ef2d0 RS |
300 | /* Which bits of file_ase were explicitly set or cleared by ASE options. */ |
301 | static unsigned int file_ase_explicit; | |
302 | ||
252b5132 RH |
303 | /* These variables are filled in with the masks of registers used. |
304 | The object format code reads them and puts them in the appropriate | |
305 | place. */ | |
306 | unsigned long mips_gprmask; | |
307 | unsigned long mips_cprmask[4]; | |
308 | ||
738f4d98 | 309 | /* True if any MIPS16 code was produced. */ |
a4672219 TS |
310 | static int file_ase_mips16; |
311 | ||
3994f87e TS |
312 | #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \ |
313 | || mips_opts.isa == ISA_MIPS32R2 \ | |
ae52f483 AB |
314 | || mips_opts.isa == ISA_MIPS32R3 \ |
315 | || mips_opts.isa == ISA_MIPS32R5 \ | |
3994f87e | 316 | || mips_opts.isa == ISA_MIPS64 \ |
ae52f483 AB |
317 | || mips_opts.isa == ISA_MIPS64R2 \ |
318 | || mips_opts.isa == ISA_MIPS64R3 \ | |
319 | || mips_opts.isa == ISA_MIPS64R5) | |
3994f87e | 320 | |
df58fc94 RS |
321 | /* True if any microMIPS code was produced. */ |
322 | static int file_ase_micromips; | |
323 | ||
b12dd2e4 CF |
324 | /* True if we want to create R_MIPS_JALR for jalr $25. */ |
325 | #ifdef TE_IRIX | |
1180b5a4 | 326 | #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI |
b12dd2e4 | 327 | #else |
1180b5a4 RS |
328 | /* As a GNU extension, we use R_MIPS_JALR for o32 too. However, |
329 | because there's no place for any addend, the only acceptable | |
330 | expression is a bare symbol. */ | |
331 | #define MIPS_JALR_HINT_P(EXPR) \ | |
332 | (!HAVE_IN_PLACE_ADDENDS \ | |
333 | || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0)) | |
b12dd2e4 CF |
334 | #endif |
335 | ||
ec68c924 | 336 | /* The argument of the -march= flag. The architecture we are assembling. */ |
316f5878 | 337 | static const char *mips_arch_string; |
ec68c924 EC |
338 | |
339 | /* The argument of the -mtune= flag. The architecture for which we | |
340 | are optimizing. */ | |
341 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 342 | static const char *mips_tune_string; |
ec68c924 | 343 | |
316f5878 | 344 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
345 | static int mips_32bitmode = 0; |
346 | ||
316f5878 RS |
347 | /* True if the given ABI requires 32-bit registers. */ |
348 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
349 | ||
350 | /* Likewise 64-bit registers. */ | |
707bfff6 | 351 | #define ABI_NEEDS_64BIT_REGS(ABI) \ |
134c0c8b | 352 | ((ABI) == N32_ABI \ |
707bfff6 | 353 | || (ABI) == N64_ABI \ |
316f5878 RS |
354 | || (ABI) == O64_ABI) |
355 | ||
7361da2c AB |
356 | #define ISA_IS_R6(ISA) \ |
357 | ((ISA) == ISA_MIPS32R6 \ | |
358 | || (ISA) == ISA_MIPS64R6) | |
359 | ||
ad3fea08 | 360 | /* Return true if ISA supports 64 bit wide gp registers. */ |
707bfff6 TS |
361 | #define ISA_HAS_64BIT_REGS(ISA) \ |
362 | ((ISA) == ISA_MIPS3 \ | |
363 | || (ISA) == ISA_MIPS4 \ | |
364 | || (ISA) == ISA_MIPS5 \ | |
365 | || (ISA) == ISA_MIPS64 \ | |
ae52f483 AB |
366 | || (ISA) == ISA_MIPS64R2 \ |
367 | || (ISA) == ISA_MIPS64R3 \ | |
7361da2c AB |
368 | || (ISA) == ISA_MIPS64R5 \ |
369 | || (ISA) == ISA_MIPS64R6) | |
9ce8a5dd | 370 | |
ad3fea08 TS |
371 | /* Return true if ISA supports 64 bit wide float registers. */ |
372 | #define ISA_HAS_64BIT_FPRS(ISA) \ | |
373 | ((ISA) == ISA_MIPS3 \ | |
374 | || (ISA) == ISA_MIPS4 \ | |
375 | || (ISA) == ISA_MIPS5 \ | |
376 | || (ISA) == ISA_MIPS32R2 \ | |
ae52f483 AB |
377 | || (ISA) == ISA_MIPS32R3 \ |
378 | || (ISA) == ISA_MIPS32R5 \ | |
7361da2c | 379 | || (ISA) == ISA_MIPS32R6 \ |
ad3fea08 | 380 | || (ISA) == ISA_MIPS64 \ |
ae52f483 AB |
381 | || (ISA) == ISA_MIPS64R2 \ |
382 | || (ISA) == ISA_MIPS64R3 \ | |
7361da2c AB |
383 | || (ISA) == ISA_MIPS64R5 \ |
384 | || (ISA) == ISA_MIPS64R6) | |
ad3fea08 | 385 | |
af7ee8bf CD |
386 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
387 | instructions. */ | |
707bfff6 | 388 | #define ISA_HAS_DROR(ISA) \ |
df58fc94 | 389 | ((ISA) == ISA_MIPS64R2 \ |
ae52f483 AB |
390 | || (ISA) == ISA_MIPS64R3 \ |
391 | || (ISA) == ISA_MIPS64R5 \ | |
7361da2c | 392 | || (ISA) == ISA_MIPS64R6 \ |
df58fc94 RS |
393 | || (mips_opts.micromips \ |
394 | && ISA_HAS_64BIT_REGS (ISA)) \ | |
395 | ) | |
af7ee8bf CD |
396 | |
397 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
398 | instructions. */ | |
707bfff6 TS |
399 | #define ISA_HAS_ROR(ISA) \ |
400 | ((ISA) == ISA_MIPS32R2 \ | |
ae52f483 AB |
401 | || (ISA) == ISA_MIPS32R3 \ |
402 | || (ISA) == ISA_MIPS32R5 \ | |
7361da2c | 403 | || (ISA) == ISA_MIPS32R6 \ |
707bfff6 | 404 | || (ISA) == ISA_MIPS64R2 \ |
ae52f483 AB |
405 | || (ISA) == ISA_MIPS64R3 \ |
406 | || (ISA) == ISA_MIPS64R5 \ | |
7361da2c | 407 | || (ISA) == ISA_MIPS64R6 \ |
846ef2d0 | 408 | || (mips_opts.ase & ASE_SMARTMIPS) \ |
df58fc94 RS |
409 | || mips_opts.micromips \ |
410 | ) | |
707bfff6 | 411 | |
7455baf8 | 412 | /* Return true if ISA supports single-precision floats in odd registers. */ |
351cdf24 MF |
413 | #define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\ |
414 | (((ISA) == ISA_MIPS32 \ | |
415 | || (ISA) == ISA_MIPS32R2 \ | |
416 | || (ISA) == ISA_MIPS32R3 \ | |
417 | || (ISA) == ISA_MIPS32R5 \ | |
7361da2c | 418 | || (ISA) == ISA_MIPS32R6 \ |
351cdf24 MF |
419 | || (ISA) == ISA_MIPS64 \ |
420 | || (ISA) == ISA_MIPS64R2 \ | |
421 | || (ISA) == ISA_MIPS64R3 \ | |
422 | || (ISA) == ISA_MIPS64R5 \ | |
7361da2c | 423 | || (ISA) == ISA_MIPS64R6 \ |
351cdf24 MF |
424 | || (CPU) == CPU_R5900) \ |
425 | && (CPU) != CPU_LOONGSON_3A) | |
af7ee8bf | 426 | |
ad3fea08 TS |
427 | /* Return true if ISA supports move to/from high part of a 64-bit |
428 | floating-point register. */ | |
429 | #define ISA_HAS_MXHC1(ISA) \ | |
430 | ((ISA) == ISA_MIPS32R2 \ | |
ae52f483 AB |
431 | || (ISA) == ISA_MIPS32R3 \ |
432 | || (ISA) == ISA_MIPS32R5 \ | |
7361da2c AB |
433 | || (ISA) == ISA_MIPS32R6 \ |
434 | || (ISA) == ISA_MIPS64R2 \ | |
435 | || (ISA) == ISA_MIPS64R3 \ | |
436 | || (ISA) == ISA_MIPS64R5 \ | |
437 | || (ISA) == ISA_MIPS64R6) | |
438 | ||
439 | /* Return true if ISA supports legacy NAN. */ | |
440 | #define ISA_HAS_LEGACY_NAN(ISA) \ | |
441 | ((ISA) == ISA_MIPS1 \ | |
442 | || (ISA) == ISA_MIPS2 \ | |
443 | || (ISA) == ISA_MIPS3 \ | |
444 | || (ISA) == ISA_MIPS4 \ | |
445 | || (ISA) == ISA_MIPS5 \ | |
446 | || (ISA) == ISA_MIPS32 \ | |
447 | || (ISA) == ISA_MIPS32R2 \ | |
448 | || (ISA) == ISA_MIPS32R3 \ | |
449 | || (ISA) == ISA_MIPS32R5 \ | |
450 | || (ISA) == ISA_MIPS64 \ | |
ae52f483 AB |
451 | || (ISA) == ISA_MIPS64R2 \ |
452 | || (ISA) == ISA_MIPS64R3 \ | |
453 | || (ISA) == ISA_MIPS64R5) | |
ad3fea08 | 454 | |
bad1aba3 | 455 | #define GPR_SIZE \ |
456 | (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \ | |
457 | ? 32 \ | |
458 | : mips_opts.gp) | |
ca4e0257 | 459 | |
bad1aba3 | 460 | #define FPR_SIZE \ |
461 | (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \ | |
462 | ? 32 \ | |
463 | : mips_opts.fp) | |
ca4e0257 | 464 | |
316f5878 | 465 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 466 | |
316f5878 | 467 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 468 | |
3b91255e RS |
469 | /* True if relocations are stored in-place. */ |
470 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
471 | ||
aed1a261 RS |
472 | /* The ABI-derived address size. */ |
473 | #define HAVE_64BIT_ADDRESSES \ | |
bad1aba3 | 474 | (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) |
aed1a261 | 475 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) |
e013f690 | 476 | |
aed1a261 RS |
477 | /* The size of symbolic constants (i.e., expressions of the form |
478 | "SYMBOL" or "SYMBOL + OFFSET"). */ | |
479 | #define HAVE_32BIT_SYMBOLS \ | |
480 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) | |
481 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) | |
ca4e0257 | 482 | |
b7c7d6c1 TS |
483 | /* Addresses are loaded in different ways, depending on the address size |
484 | in use. The n32 ABI Documentation also mandates the use of additions | |
485 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 486 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 487 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
488 | |
489 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 490 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
491 | |
492 | #define ADDRESS_LOAD_INSN \ | |
493 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
494 | ||
495 | #define ADDRESS_STORE_INSN \ | |
496 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
497 | ||
a4672219 | 498 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
499 | #define CPU_HAS_MIPS16(cpu) \ |
500 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
501 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 502 | |
2309ddf2 | 503 | /* Return true if the given CPU supports the microMIPS ASE. */ |
df58fc94 RS |
504 | #define CPU_HAS_MICROMIPS(cpu) 0 |
505 | ||
60b63b72 RS |
506 | /* True if CPU has a dror instruction. */ |
507 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
508 | ||
509 | /* True if CPU has a ror instruction. */ | |
510 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
511 | ||
dd6a37e7 | 512 | /* True if CPU is in the Octeon family */ |
2c629856 N |
513 | #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \ |
514 | || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3) | |
dd6a37e7 | 515 | |
dd3cbb7e | 516 | /* True if CPU has seq/sne and seqi/snei instructions. */ |
dd6a37e7 | 517 | #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU)) |
dd3cbb7e | 518 | |
0aa27725 RS |
519 | /* True, if CPU has support for ldc1 and sdc1. */ |
520 | #define CPU_HAS_LDC1_SDC1(CPU) \ | |
521 | ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900)) | |
522 | ||
c8978940 CD |
523 | /* True if mflo and mfhi can be immediately followed by instructions |
524 | which write to the HI and LO registers. | |
525 | ||
526 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
527 | (at least) two instructions between the reads of HI/LO and | |
528 | instructions which write them, and later ISAs do not. Contradicting | |
529 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
530 | the UM for the NEC Vr5000) document needing the instructions between | |
531 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
532 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
533 | earlier-ISA CPUs for which CPU documentation declares that the | |
534 | instructions are really interlocked. */ | |
535 | #define hilo_interlocks \ | |
536 | (mips_opts.isa == ISA_MIPS32 \ | |
537 | || mips_opts.isa == ISA_MIPS32R2 \ | |
ae52f483 AB |
538 | || mips_opts.isa == ISA_MIPS32R3 \ |
539 | || mips_opts.isa == ISA_MIPS32R5 \ | |
7361da2c | 540 | || mips_opts.isa == ISA_MIPS32R6 \ |
c8978940 CD |
541 | || mips_opts.isa == ISA_MIPS64 \ |
542 | || mips_opts.isa == ISA_MIPS64R2 \ | |
ae52f483 AB |
543 | || mips_opts.isa == ISA_MIPS64R3 \ |
544 | || mips_opts.isa == ISA_MIPS64R5 \ | |
7361da2c | 545 | || mips_opts.isa == ISA_MIPS64R6 \ |
c8978940 | 546 | || mips_opts.arch == CPU_R4010 \ |
e407c74b | 547 | || mips_opts.arch == CPU_R5900 \ |
c8978940 CD |
548 | || mips_opts.arch == CPU_R10000 \ |
549 | || mips_opts.arch == CPU_R12000 \ | |
3aa3176b TS |
550 | || mips_opts.arch == CPU_R14000 \ |
551 | || mips_opts.arch == CPU_R16000 \ | |
c8978940 | 552 | || mips_opts.arch == CPU_RM7000 \ |
c8978940 | 553 | || mips_opts.arch == CPU_VR5500 \ |
df58fc94 | 554 | || mips_opts.micromips \ |
c8978940 | 555 | ) |
252b5132 RH |
556 | |
557 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
558 | from the GPRs after they are loaded from memory, and thus does not |
559 | require nops to be inserted. This applies to instructions marked | |
67dc82bc | 560 | INSN_LOAD_MEMORY. These nops are only required at MIPS ISA |
df58fc94 RS |
561 | level I and microMIPS mode instructions are always interlocked. */ |
562 | #define gpr_interlocks \ | |
563 | (mips_opts.isa != ISA_MIPS1 \ | |
564 | || mips_opts.arch == CPU_R3900 \ | |
e407c74b | 565 | || mips_opts.arch == CPU_R5900 \ |
df58fc94 RS |
566 | || mips_opts.micromips \ |
567 | ) | |
252b5132 | 568 | |
81912461 ILT |
569 | /* Whether the processor uses hardware interlocks to avoid delays |
570 | required by coprocessor instructions, and thus does not require | |
571 | nops to be inserted. This applies to instructions marked | |
43885403 MF |
572 | INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between |
573 | instructions marked INSN_WRITE_COND_CODE and ones marked | |
81912461 | 574 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA |
df58fc94 RS |
575 | levels I, II, and III and microMIPS mode instructions are always |
576 | interlocked. */ | |
bdaaa2e1 | 577 | /* Itbl support may require additional care here. */ |
81912461 ILT |
578 | #define cop_interlocks \ |
579 | ((mips_opts.isa != ISA_MIPS1 \ | |
580 | && mips_opts.isa != ISA_MIPS2 \ | |
581 | && mips_opts.isa != ISA_MIPS3) \ | |
582 | || mips_opts.arch == CPU_R4300 \ | |
df58fc94 | 583 | || mips_opts.micromips \ |
81912461 ILT |
584 | ) |
585 | ||
586 | /* Whether the processor uses hardware interlocks to protect reads | |
587 | from coprocessor registers after they are loaded from memory, and | |
588 | thus does not require nops to be inserted. This applies to | |
589 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
df58fc94 RS |
590 | requires at MIPS ISA level I and microMIPS mode instructions are |
591 | always interlocked. */ | |
592 | #define cop_mem_interlocks \ | |
593 | (mips_opts.isa != ISA_MIPS1 \ | |
594 | || mips_opts.micromips \ | |
595 | ) | |
252b5132 | 596 | |
6b76fefe CM |
597 | /* Is this a mfhi or mflo instruction? */ |
598 | #define MF_HILO_INSN(PINFO) \ | |
b19e8a9b AN |
599 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) |
600 | ||
df58fc94 RS |
601 | /* Whether code compression (either of the MIPS16 or the microMIPS ASEs) |
602 | has been selected. This implies, in particular, that addresses of text | |
603 | labels have their LSB set. */ | |
604 | #define HAVE_CODE_COMPRESSION \ | |
605 | ((mips_opts.mips16 | mips_opts.micromips) != 0) | |
606 | ||
42429eac | 607 | /* The minimum and maximum signed values that can be stored in a GPR. */ |
bad1aba3 | 608 | #define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1)) |
42429eac RS |
609 | #define GPR_SMIN (-GPR_SMAX - 1) |
610 | ||
252b5132 RH |
611 | /* MIPS PIC level. */ |
612 | ||
a161fe53 | 613 | enum mips_pic_level mips_pic; |
252b5132 | 614 | |
c9914766 | 615 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 616 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 617 | static int mips_big_got = 0; |
252b5132 RH |
618 | |
619 | /* 1 if trap instructions should used for overflow rather than break | |
620 | instructions. */ | |
c9914766 | 621 | static int mips_trap = 0; |
252b5132 | 622 | |
119d663a | 623 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 624 | by assembling two single width halves into two single width floating |
119d663a NC |
625 | point registers which just happen to alias the double width destination |
626 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 627 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
628 | automatically at assemble time. */ |
629 | static int mips_disable_float_construction; | |
630 | ||
252b5132 RH |
631 | /* Non-zero if any .set noreorder directives were used. */ |
632 | ||
633 | static int mips_any_noreorder; | |
634 | ||
6b76fefe CM |
635 | /* Non-zero if nops should be inserted when the register referenced in |
636 | an mfhi/mflo instruction is read in the next two instructions. */ | |
637 | static int mips_7000_hilo_fix; | |
638 | ||
02ffd3e4 | 639 | /* The size of objects in the small data section. */ |
156c2f8b | 640 | static unsigned int g_switch_value = 8; |
252b5132 RH |
641 | /* Whether the -G option was used. */ |
642 | static int g_switch_seen = 0; | |
643 | ||
644 | #define N_RMASK 0xc4 | |
645 | #define N_VFP 0xd4 | |
646 | ||
647 | /* If we can determine in advance that GP optimization won't be | |
648 | possible, we can skip the relaxation stuff that tries to produce | |
649 | GP-relative references. This makes delay slot optimization work | |
650 | better. | |
651 | ||
652 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
653 | gcc output. It needs to guess right for gcc, otherwise gcc |
654 | will put what it thinks is a GP-relative instruction in a branch | |
655 | delay slot. | |
252b5132 RH |
656 | |
657 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
658 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 659 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
660 | |
661 | /* handle of the OPCODE hash table */ | |
662 | static struct hash_control *op_hash = NULL; | |
663 | ||
664 | /* The opcode hash table we use for the mips16. */ | |
665 | static struct hash_control *mips16_op_hash = NULL; | |
666 | ||
df58fc94 RS |
667 | /* The opcode hash table we use for the microMIPS ASE. */ |
668 | static struct hash_control *micromips_op_hash = NULL; | |
669 | ||
252b5132 RH |
670 | /* This array holds the chars that always start a comment. If the |
671 | pre-processor is disabled, these aren't very useful */ | |
672 | const char comment_chars[] = "#"; | |
673 | ||
674 | /* This array holds the chars that only start a comment at the beginning of | |
675 | a line. If the line seems to have the form '# 123 filename' | |
676 | .line and .file directives will appear in the pre-processed output */ | |
677 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
678 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 679 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
680 | /* Also note that C style comments are always supported. */ |
681 | const char line_comment_chars[] = "#"; | |
682 | ||
bdaaa2e1 | 683 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 684 | const char line_separator_chars[] = ";"; |
252b5132 RH |
685 | |
686 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
687 | const char EXP_CHARS[] = "eE"; | |
688 | ||
689 | /* Chars that mean this number is a floating point constant */ | |
690 | /* As in 0f12.456 */ | |
691 | /* or 0d1.2345e12 */ | |
692 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
693 | ||
694 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
695 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
696 | but nothing is ideal around here. | |
697 | */ | |
698 | ||
e3de51ce RS |
699 | /* Types of printf format used for instruction-related error messages. |
700 | "I" means int ("%d") and "S" means string ("%s"). */ | |
701 | enum mips_insn_error_format { | |
702 | ERR_FMT_PLAIN, | |
703 | ERR_FMT_I, | |
704 | ERR_FMT_SS, | |
705 | }; | |
706 | ||
707 | /* Information about an error that was found while assembling the current | |
708 | instruction. */ | |
709 | struct mips_insn_error { | |
710 | /* We sometimes need to match an instruction against more than one | |
711 | opcode table entry. Errors found during this matching are reported | |
712 | against a particular syntactic argument rather than against the | |
713 | instruction as a whole. We grade these messages so that errors | |
714 | against argument N have a greater priority than an error against | |
715 | any argument < N, since the former implies that arguments up to N | |
716 | were acceptable and that the opcode entry was therefore a closer match. | |
717 | If several matches report an error against the same argument, | |
718 | we only use that error if it is the same in all cases. | |
719 | ||
720 | min_argnum is the minimum argument number for which an error message | |
721 | should be accepted. It is 0 if MSG is against the instruction as | |
722 | a whole. */ | |
723 | int min_argnum; | |
724 | ||
725 | /* The printf()-style message, including its format and arguments. */ | |
726 | enum mips_insn_error_format format; | |
727 | const char *msg; | |
728 | union { | |
729 | int i; | |
730 | const char *ss[2]; | |
731 | } u; | |
732 | }; | |
733 | ||
734 | /* The error that should be reported for the current instruction. */ | |
735 | static struct mips_insn_error insn_error; | |
252b5132 RH |
736 | |
737 | static int auto_align = 1; | |
738 | ||
739 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
740 | offset in the stack frame from which to restore the $gp register. | |
741 | This is set by the .cprestore pseudo-op, and saved in this | |
742 | variable. */ | |
743 | static offsetT mips_cprestore_offset = -1; | |
744 | ||
67c1ffbe | 745 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 746 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 747 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
748 | static offsetT mips_cpreturn_offset = -1; |
749 | static int mips_cpreturn_register = -1; | |
750 | static int mips_gp_register = GP; | |
def2e0dd | 751 | static int mips_gprel_offset = 0; |
6478892d | 752 | |
7a621144 DJ |
753 | /* Whether mips_cprestore_offset has been set in the current function |
754 | (or whether it has already been warned about, if not). */ | |
755 | static int mips_cprestore_valid = 0; | |
756 | ||
252b5132 RH |
757 | /* This is the register which holds the stack frame, as set by the |
758 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
759 | static int mips_frame_reg = SP; | |
760 | ||
7a621144 DJ |
761 | /* Whether mips_frame_reg has been set in the current function |
762 | (or whether it has already been warned about, if not). */ | |
763 | static int mips_frame_reg_valid = 0; | |
764 | ||
252b5132 RH |
765 | /* To output NOP instructions correctly, we need to keep information |
766 | about the previous two instructions. */ | |
767 | ||
768 | /* Whether we are optimizing. The default value of 2 means to remove | |
769 | unneeded NOPs and swap branch instructions when possible. A value | |
770 | of 1 means to not swap branches. A value of 0 means to always | |
771 | insert NOPs. */ | |
772 | static int mips_optimize = 2; | |
773 | ||
774 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
775 | equivalent to seeing no -g option at all. */ | |
776 | static int mips_debug = 0; | |
777 | ||
7d8e00cf RS |
778 | /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ |
779 | #define MAX_VR4130_NOPS 4 | |
780 | ||
781 | /* The maximum number of NOPs needed to fill delay slots. */ | |
782 | #define MAX_DELAY_NOPS 2 | |
783 | ||
784 | /* The maximum number of NOPs needed for any purpose. */ | |
785 | #define MAX_NOPS 4 | |
71400594 RS |
786 | |
787 | /* A list of previous instructions, with index 0 being the most recent. | |
788 | We need to look back MAX_NOPS instructions when filling delay slots | |
789 | or working around processor errata. We need to look back one | |
790 | instruction further if we're thinking about using history[0] to | |
791 | fill a branch delay slot. */ | |
792 | static struct mips_cl_insn history[1 + MAX_NOPS]; | |
252b5132 | 793 | |
fc76e730 | 794 | /* Arrays of operands for each instruction. */ |
14daeee3 | 795 | #define MAX_OPERANDS 6 |
fc76e730 RS |
796 | struct mips_operand_array { |
797 | const struct mips_operand *operand[MAX_OPERANDS]; | |
798 | }; | |
799 | static struct mips_operand_array *mips_operands; | |
800 | static struct mips_operand_array *mips16_operands; | |
801 | static struct mips_operand_array *micromips_operands; | |
802 | ||
1e915849 | 803 | /* Nop instructions used by emit_nop. */ |
df58fc94 RS |
804 | static struct mips_cl_insn nop_insn; |
805 | static struct mips_cl_insn mips16_nop_insn; | |
806 | static struct mips_cl_insn micromips_nop16_insn; | |
807 | static struct mips_cl_insn micromips_nop32_insn; | |
1e915849 RS |
808 | |
809 | /* The appropriate nop for the current mode. */ | |
833794fc MR |
810 | #define NOP_INSN (mips_opts.mips16 \ |
811 | ? &mips16_nop_insn \ | |
812 | : (mips_opts.micromips \ | |
813 | ? (mips_opts.insn32 \ | |
814 | ? µmips_nop32_insn \ | |
815 | : µmips_nop16_insn) \ | |
816 | : &nop_insn)) | |
df58fc94 RS |
817 | |
818 | /* The size of NOP_INSN in bytes. */ | |
833794fc MR |
819 | #define NOP_INSN_SIZE ((mips_opts.mips16 \ |
820 | || (mips_opts.micromips && !mips_opts.insn32)) \ | |
821 | ? 2 : 4) | |
252b5132 | 822 | |
252b5132 RH |
823 | /* If this is set, it points to a frag holding nop instructions which |
824 | were inserted before the start of a noreorder section. If those | |
825 | nops turn out to be unnecessary, the size of the frag can be | |
826 | decreased. */ | |
827 | static fragS *prev_nop_frag; | |
828 | ||
829 | /* The number of nop instructions we created in prev_nop_frag. */ | |
830 | static int prev_nop_frag_holds; | |
831 | ||
832 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 833 | prev_nop_frag. */ |
252b5132 RH |
834 | static int prev_nop_frag_required; |
835 | ||
836 | /* The number of instructions we've seen since prev_nop_frag. */ | |
837 | static int prev_nop_frag_since; | |
838 | ||
e8044f35 RS |
839 | /* Relocations against symbols are sometimes done in two parts, with a HI |
840 | relocation and a LO relocation. Each relocation has only 16 bits of | |
841 | space to store an addend. This means that in order for the linker to | |
842 | handle carries correctly, it must be able to locate both the HI and | |
843 | the LO relocation. This means that the relocations must appear in | |
844 | order in the relocation table. | |
252b5132 RH |
845 | |
846 | In order to implement this, we keep track of each unmatched HI | |
847 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 848 | corresponding LO relocation. */ |
252b5132 | 849 | |
e972090a NC |
850 | struct mips_hi_fixup |
851 | { | |
252b5132 RH |
852 | /* Next HI fixup. */ |
853 | struct mips_hi_fixup *next; | |
854 | /* This fixup. */ | |
855 | fixS *fixp; | |
856 | /* The section this fixup is in. */ | |
857 | segT seg; | |
858 | }; | |
859 | ||
860 | /* The list of unmatched HI relocs. */ | |
861 | ||
862 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
863 | ||
64bdfcaf RS |
864 | /* The frag containing the last explicit relocation operator. |
865 | Null if explicit relocations have not been used. */ | |
866 | ||
867 | static fragS *prev_reloc_op_frag; | |
868 | ||
252b5132 RH |
869 | /* Map mips16 register numbers to normal MIPS register numbers. */ |
870 | ||
e972090a NC |
871 | static const unsigned int mips16_to_32_reg_map[] = |
872 | { | |
252b5132 RH |
873 | 16, 17, 2, 3, 4, 5, 6, 7 |
874 | }; | |
60b63b72 | 875 | |
df58fc94 RS |
876 | /* Map microMIPS register numbers to normal MIPS register numbers. */ |
877 | ||
df58fc94 | 878 | #define micromips_to_32_reg_d_map mips16_to_32_reg_map |
df58fc94 RS |
879 | |
880 | /* The microMIPS registers with type h. */ | |
e76ff5ab | 881 | static const unsigned int micromips_to_32_reg_h_map1[] = |
df58fc94 RS |
882 | { |
883 | 5, 5, 6, 4, 4, 4, 4, 4 | |
884 | }; | |
e76ff5ab | 885 | static const unsigned int micromips_to_32_reg_h_map2[] = |
df58fc94 RS |
886 | { |
887 | 6, 7, 7, 21, 22, 5, 6, 7 | |
888 | }; | |
889 | ||
df58fc94 RS |
890 | /* The microMIPS registers with type m. */ |
891 | static const unsigned int micromips_to_32_reg_m_map[] = | |
892 | { | |
893 | 0, 17, 2, 3, 16, 18, 19, 20 | |
894 | }; | |
895 | ||
896 | #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map | |
897 | ||
71400594 RS |
898 | /* Classifies the kind of instructions we're interested in when |
899 | implementing -mfix-vr4120. */ | |
c67a084a NC |
900 | enum fix_vr4120_class |
901 | { | |
71400594 RS |
902 | FIX_VR4120_MACC, |
903 | FIX_VR4120_DMACC, | |
904 | FIX_VR4120_MULT, | |
905 | FIX_VR4120_DMULT, | |
906 | FIX_VR4120_DIV, | |
907 | FIX_VR4120_MTHILO, | |
908 | NUM_FIX_VR4120_CLASSES | |
909 | }; | |
910 | ||
c67a084a NC |
911 | /* ...likewise -mfix-loongson2f-jump. */ |
912 | static bfd_boolean mips_fix_loongson2f_jump; | |
913 | ||
914 | /* ...likewise -mfix-loongson2f-nop. */ | |
915 | static bfd_boolean mips_fix_loongson2f_nop; | |
916 | ||
917 | /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */ | |
918 | static bfd_boolean mips_fix_loongson2f; | |
919 | ||
71400594 RS |
920 | /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if |
921 | there must be at least one other instruction between an instruction | |
922 | of type X and an instruction of type Y. */ | |
923 | static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; | |
924 | ||
925 | /* True if -mfix-vr4120 is in force. */ | |
d766e8ec | 926 | static int mips_fix_vr4120; |
4a6a3df4 | 927 | |
7d8e00cf RS |
928 | /* ...likewise -mfix-vr4130. */ |
929 | static int mips_fix_vr4130; | |
930 | ||
6a32d874 CM |
931 | /* ...likewise -mfix-24k. */ |
932 | static int mips_fix_24k; | |
933 | ||
a8d14a88 CM |
934 | /* ...likewise -mfix-rm7000 */ |
935 | static int mips_fix_rm7000; | |
936 | ||
d954098f DD |
937 | /* ...likewise -mfix-cn63xxp1 */ |
938 | static bfd_boolean mips_fix_cn63xxp1; | |
939 | ||
4a6a3df4 AO |
940 | /* We don't relax branches by default, since this causes us to expand |
941 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
942 | fail to compute the offset before expanding the macro to the most | |
943 | efficient expansion. */ | |
944 | ||
945 | static int mips_relax_branch; | |
8b10b0b3 MR |
946 | |
947 | /* TRUE if checks are suppressed for invalid branches between ISA modes. | |
948 | Needed for broken assembly produced by some GCC versions and some | |
949 | sloppy code out there, where branches to data labels are present. */ | |
950 | static bfd_boolean mips_ignore_branch_isa; | |
252b5132 | 951 | \f |
4d7206a2 RS |
952 | /* The expansion of many macros depends on the type of symbol that |
953 | they refer to. For example, when generating position-dependent code, | |
954 | a macro that refers to a symbol may have two different expansions, | |
955 | one which uses GP-relative addresses and one which uses absolute | |
956 | addresses. When generating SVR4-style PIC, a macro may have | |
957 | different expansions for local and global symbols. | |
958 | ||
959 | We handle these situations by generating both sequences and putting | |
960 | them in variant frags. In position-dependent code, the first sequence | |
961 | will be the GP-relative one and the second sequence will be the | |
962 | absolute one. In SVR4 PIC, the first sequence will be for global | |
963 | symbols and the second will be for local symbols. | |
964 | ||
584892a6 RS |
965 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
966 | SECOND are the lengths of the two sequences in bytes. These fields | |
967 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
968 | the subtype has the following flags: | |
4d7206a2 | 969 | |
ce8ad872 MR |
970 | RELAX_PIC |
971 | Set if generating PIC code. | |
972 | ||
584892a6 RS |
973 | RELAX_USE_SECOND |
974 | Set if it has been decided that we should use the second | |
975 | sequence instead of the first. | |
976 | ||
977 | RELAX_SECOND_LONGER | |
978 | Set in the first variant frag if the macro's second implementation | |
979 | is longer than its first. This refers to the macro as a whole, | |
980 | not an individual relaxation. | |
981 | ||
982 | RELAX_NOMACRO | |
983 | Set in the first variant frag if the macro appeared in a .set nomacro | |
984 | block and if one alternative requires a warning but the other does not. | |
985 | ||
986 | RELAX_DELAY_SLOT | |
987 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
988 | delay slot. | |
4d7206a2 | 989 | |
df58fc94 RS |
990 | RELAX_DELAY_SLOT_16BIT |
991 | Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a | |
992 | 16-bit instruction. | |
993 | ||
994 | RELAX_DELAY_SLOT_SIZE_FIRST | |
995 | Like RELAX_DELAY_SLOT, but indicates that the first implementation of | |
996 | the macro is of the wrong size for the branch delay slot. | |
997 | ||
998 | RELAX_DELAY_SLOT_SIZE_SECOND | |
999 | Like RELAX_DELAY_SLOT, but indicates that the second implementation of | |
1000 | the macro is of the wrong size for the branch delay slot. | |
1001 | ||
4d7206a2 RS |
1002 | The frag's "opcode" points to the first fixup for relaxable code. |
1003 | ||
1004 | Relaxable macros are generated using a sequence such as: | |
1005 | ||
1006 | relax_start (SYMBOL); | |
1007 | ... generate first expansion ... | |
1008 | relax_switch (); | |
1009 | ... generate second expansion ... | |
1010 | relax_end (); | |
1011 | ||
1012 | The code and fixups for the unwanted alternative are discarded | |
1013 | by md_convert_frag. */ | |
ce8ad872 MR |
1014 | #define RELAX_ENCODE(FIRST, SECOND, PIC) \ |
1015 | (((FIRST) << 8) | (SECOND) | ((PIC) ? 0x10000 : 0)) | |
4d7206a2 | 1016 | |
584892a6 RS |
1017 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
1018 | #define RELAX_SECOND(X) ((X) & 0xff) | |
ce8ad872 MR |
1019 | #define RELAX_PIC(X) (((X) & 0x10000) != 0) |
1020 | #define RELAX_USE_SECOND 0x20000 | |
1021 | #define RELAX_SECOND_LONGER 0x40000 | |
1022 | #define RELAX_NOMACRO 0x80000 | |
1023 | #define RELAX_DELAY_SLOT 0x100000 | |
1024 | #define RELAX_DELAY_SLOT_16BIT 0x200000 | |
1025 | #define RELAX_DELAY_SLOT_SIZE_FIRST 0x400000 | |
1026 | #define RELAX_DELAY_SLOT_SIZE_SECOND 0x800000 | |
252b5132 | 1027 | |
4a6a3df4 AO |
1028 | /* Branch without likely bit. If label is out of range, we turn: |
1029 | ||
134c0c8b | 1030 | beq reg1, reg2, label |
4a6a3df4 AO |
1031 | delay slot |
1032 | ||
1033 | into | |
1034 | ||
1035 | bne reg1, reg2, 0f | |
1036 | nop | |
1037 | j label | |
1038 | 0: delay slot | |
1039 | ||
1040 | with the following opcode replacements: | |
1041 | ||
1042 | beq <-> bne | |
1043 | blez <-> bgtz | |
1044 | bltz <-> bgez | |
1045 | bc1f <-> bc1t | |
1046 | ||
1047 | bltzal <-> bgezal (with jal label instead of j label) | |
1048 | ||
1049 | Even though keeping the delay slot instruction in the delay slot of | |
1050 | the branch would be more efficient, it would be very tricky to do | |
1051 | correctly, because we'd have to introduce a variable frag *after* | |
1052 | the delay slot instruction, and expand that instead. Let's do it | |
1053 | the easy way for now, even if the branch-not-taken case now costs | |
1054 | one additional instruction. Out-of-range branches are not supposed | |
1055 | to be common, anyway. | |
1056 | ||
1057 | Branch likely. If label is out of range, we turn: | |
1058 | ||
1059 | beql reg1, reg2, label | |
1060 | delay slot (annulled if branch not taken) | |
1061 | ||
1062 | into | |
1063 | ||
1064 | beql reg1, reg2, 1f | |
1065 | nop | |
1066 | beql $0, $0, 2f | |
1067 | nop | |
1068 | 1: j[al] label | |
1069 | delay slot (executed only if branch taken) | |
1070 | 2: | |
1071 | ||
1072 | It would be possible to generate a shorter sequence by losing the | |
1073 | likely bit, generating something like: | |
b34976b6 | 1074 | |
4a6a3df4 AO |
1075 | bne reg1, reg2, 0f |
1076 | nop | |
1077 | j[al] label | |
1078 | delay slot (executed only if branch taken) | |
1079 | 0: | |
1080 | ||
1081 | beql -> bne | |
1082 | bnel -> beq | |
1083 | blezl -> bgtz | |
1084 | bgtzl -> blez | |
1085 | bltzl -> bgez | |
1086 | bgezl -> bltz | |
1087 | bc1fl -> bc1t | |
1088 | bc1tl -> bc1f | |
1089 | ||
1090 | bltzall -> bgezal (with jal label instead of j label) | |
1091 | bgezall -> bltzal (ditto) | |
1092 | ||
1093 | ||
1094 | but it's not clear that it would actually improve performance. */ | |
ce8ad872 MR |
1095 | #define RELAX_BRANCH_ENCODE(at, pic, \ |
1096 | uncond, likely, link, toofar) \ | |
66b3e8da MR |
1097 | ((relax_substateT) \ |
1098 | (0xc0000000 \ | |
1099 | | ((at) & 0x1f) \ | |
ce8ad872 MR |
1100 | | ((pic) ? 0x20 : 0) \ |
1101 | | ((toofar) ? 0x40 : 0) \ | |
1102 | | ((link) ? 0x80 : 0) \ | |
1103 | | ((likely) ? 0x100 : 0) \ | |
1104 | | ((uncond) ? 0x200 : 0))) | |
4a6a3df4 | 1105 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
ce8ad872 MR |
1106 | #define RELAX_BRANCH_UNCOND(i) (((i) & 0x200) != 0) |
1107 | #define RELAX_BRANCH_LIKELY(i) (((i) & 0x100) != 0) | |
1108 | #define RELAX_BRANCH_LINK(i) (((i) & 0x80) != 0) | |
1109 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x40) != 0) | |
1110 | #define RELAX_BRANCH_PIC(i) (((i) & 0x20) != 0) | |
66b3e8da | 1111 | #define RELAX_BRANCH_AT(i) ((i) & 0x1f) |
4a6a3df4 | 1112 | |
252b5132 RH |
1113 | /* For mips16 code, we use an entirely different form of relaxation. |
1114 | mips16 supports two versions of most instructions which take | |
1115 | immediate values: a small one which takes some small value, and a | |
1116 | larger one which takes a 16 bit value. Since branches also follow | |
1117 | this pattern, relaxing these values is required. | |
1118 | ||
1119 | We can assemble both mips16 and normal MIPS code in a single | |
1120 | object. Therefore, we need to support this type of relaxation at | |
1121 | the same time that we support the relaxation described above. We | |
1122 | use the high bit of the subtype field to distinguish these cases. | |
1123 | ||
1124 | The information we store for this type of relaxation is the | |
1125 | argument code found in the opcode file for this relocation, whether | |
1126 | the user explicitly requested a small or extended form, and whether | |
1127 | the relocation is in a jump or jal delay slot. That tells us the | |
1128 | size of the value, and how it should be stored. We also store | |
1129 | whether the fragment is considered to be extended or not. We also | |
1130 | store whether this is known to be a branch to a different section, | |
1131 | whether we have tried to relax this frag yet, and whether we have | |
1132 | ever extended a PC relative fragment because of a shift count. */ | |
8507b6e7 MR |
1133 | #define RELAX_MIPS16_ENCODE(type, pic, sym32, nomacro, \ |
1134 | small, ext, \ | |
1135 | dslot, jal_dslot) \ | |
252b5132 RH |
1136 | (0x80000000 \ |
1137 | | ((type) & 0xff) \ | |
8507b6e7 MR |
1138 | | ((pic) ? 0x100 : 0) \ |
1139 | | ((sym32) ? 0x200 : 0) \ | |
1140 | | ((nomacro) ? 0x400 : 0) \ | |
1141 | | ((small) ? 0x800 : 0) \ | |
1142 | | ((ext) ? 0x1000 : 0) \ | |
1143 | | ((dslot) ? 0x2000 : 0) \ | |
1144 | | ((jal_dslot) ? 0x4000 : 0)) | |
1145 | ||
4a6a3df4 | 1146 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 | 1147 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
8507b6e7 MR |
1148 | #define RELAX_MIPS16_PIC(i) (((i) & 0x100) != 0) |
1149 | #define RELAX_MIPS16_SYM32(i) (((i) & 0x200) != 0) | |
1150 | #define RELAX_MIPS16_NOMACRO(i) (((i) & 0x400) != 0) | |
1151 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x800) != 0) | |
1152 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x1000) != 0) | |
1153 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x2000) != 0) | |
1154 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x4000) != 0) | |
1155 | ||
1156 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x8000) != 0) | |
1157 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x8000) | |
1158 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) & ~0x8000) | |
1159 | #define RELAX_MIPS16_ALWAYS_EXTENDED(i) (((i) & 0x10000) != 0) | |
1160 | #define RELAX_MIPS16_MARK_ALWAYS_EXTENDED(i) ((i) | 0x10000) | |
1161 | #define RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED(i) ((i) & ~0x10000) | |
1162 | #define RELAX_MIPS16_MACRO(i) (((i) & 0x20000) != 0) | |
1163 | #define RELAX_MIPS16_MARK_MACRO(i) ((i) | 0x20000) | |
1164 | #define RELAX_MIPS16_CLEAR_MACRO(i) ((i) & ~0x20000) | |
885add95 | 1165 | |
df58fc94 RS |
1166 | /* For microMIPS code, we use relaxation similar to one we use for |
1167 | MIPS16 code. Some instructions that take immediate values support | |
1168 | two encodings: a small one which takes some small value, and a | |
1169 | larger one which takes a 16 bit value. As some branches also follow | |
1170 | this pattern, relaxing these values is required. | |
1171 | ||
1172 | We can assemble both microMIPS and normal MIPS code in a single | |
1173 | object. Therefore, we need to support this type of relaxation at | |
1174 | the same time that we support the relaxation described above. We | |
1175 | use one of the high bits of the subtype field to distinguish these | |
1176 | cases. | |
1177 | ||
1178 | The information we store for this type of relaxation is the argument | |
1179 | code found in the opcode file for this relocation, the register | |
8484fb75 MR |
1180 | selected as the assembler temporary, whether in the 32-bit |
1181 | instruction mode, whether the branch is unconditional, whether it is | |
7bd374a4 MR |
1182 | compact, whether there is no delay-slot instruction available to fill |
1183 | in, whether it stores the link address implicitly in $ra, whether | |
1184 | relaxation of out-of-range 32-bit branches to a sequence of | |
8484fb75 MR |
1185 | instructions is enabled, and whether the displacement of a branch is |
1186 | too large to fit as an immediate argument of a 16-bit and a 32-bit | |
1187 | branch, respectively. */ | |
ce8ad872 | 1188 | #define RELAX_MICROMIPS_ENCODE(type, at, insn32, pic, \ |
7bd374a4 | 1189 | uncond, compact, link, nods, \ |
40209cad MR |
1190 | relax32, toofar16, toofar32) \ |
1191 | (0x40000000 \ | |
1192 | | ((type) & 0xff) \ | |
1193 | | (((at) & 0x1f) << 8) \ | |
8484fb75 | 1194 | | ((insn32) ? 0x2000 : 0) \ |
ce8ad872 MR |
1195 | | ((pic) ? 0x4000 : 0) \ |
1196 | | ((uncond) ? 0x8000 : 0) \ | |
1197 | | ((compact) ? 0x10000 : 0) \ | |
1198 | | ((link) ? 0x20000 : 0) \ | |
1199 | | ((nods) ? 0x40000 : 0) \ | |
1200 | | ((relax32) ? 0x80000 : 0) \ | |
1201 | | ((toofar16) ? 0x100000 : 0) \ | |
1202 | | ((toofar32) ? 0x200000 : 0)) | |
df58fc94 RS |
1203 | #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000) |
1204 | #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff) | |
1205 | #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f) | |
8484fb75 | 1206 | #define RELAX_MICROMIPS_INSN32(i) (((i) & 0x2000) != 0) |
ce8ad872 MR |
1207 | #define RELAX_MICROMIPS_PIC(i) (((i) & 0x4000) != 0) |
1208 | #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x8000) != 0) | |
1209 | #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x10000) != 0) | |
1210 | #define RELAX_MICROMIPS_LINK(i) (((i) & 0x20000) != 0) | |
1211 | #define RELAX_MICROMIPS_NODS(i) (((i) & 0x40000) != 0) | |
1212 | #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x80000) != 0) | |
1213 | ||
1214 | #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x100000) != 0) | |
1215 | #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x100000) | |
1216 | #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x100000) | |
1217 | #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x200000) != 0) | |
1218 | #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x200000) | |
1219 | #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x200000) | |
df58fc94 | 1220 | |
43c0598f RS |
1221 | /* Sign-extend 16-bit value X. */ |
1222 | #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000) | |
1223 | ||
885add95 CD |
1224 | /* Is the given value a sign-extended 32-bit value? */ |
1225 | #define IS_SEXT_32BIT_NUM(x) \ | |
1226 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
1227 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
1228 | ||
1229 | /* Is the given value a sign-extended 16-bit value? */ | |
1230 | #define IS_SEXT_16BIT_NUM(x) \ | |
1231 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
1232 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
1233 | ||
df58fc94 RS |
1234 | /* Is the given value a sign-extended 12-bit value? */ |
1235 | #define IS_SEXT_12BIT_NUM(x) \ | |
1236 | (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x)) | |
1237 | ||
7f3c4072 CM |
1238 | /* Is the given value a sign-extended 9-bit value? */ |
1239 | #define IS_SEXT_9BIT_NUM(x) \ | |
1240 | (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x)) | |
1241 | ||
2051e8c4 MR |
1242 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ |
1243 | #define IS_ZEXT_32BIT_NUM(x) \ | |
1244 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
1245 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
1246 | ||
bf12938e RS |
1247 | /* Extract bits MASK << SHIFT from STRUCT and shift them right |
1248 | SHIFT places. */ | |
1249 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
1250 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
1251 | ||
bf12938e | 1252 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ |
df58fc94 RS |
1253 | #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \ |
1254 | (!(MICROMIPS) \ | |
1255 | ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \ | |
1256 | : EXTRACT_BITS ((INSN).insn_opcode, \ | |
1257 | MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD)) | |
bf12938e RS |
1258 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ |
1259 | EXTRACT_BITS ((INSN).insn_opcode, \ | |
1260 | MIPS16OP_MASK_##FIELD, \ | |
1261 | MIPS16OP_SH_##FIELD) | |
5c04167a RS |
1262 | |
1263 | /* The MIPS16 EXTEND opcode, shifted left 16 places. */ | |
1264 | #define MIPS16_EXTEND (0xf000U << 16) | |
4d7206a2 | 1265 | \f |
df58fc94 RS |
1266 | /* Whether or not we are emitting a branch-likely macro. */ |
1267 | static bfd_boolean emit_branch_likely_macro = FALSE; | |
1268 | ||
4d7206a2 RS |
1269 | /* Global variables used when generating relaxable macros. See the |
1270 | comment above RELAX_ENCODE for more details about how relaxation | |
1271 | is used. */ | |
1272 | static struct { | |
1273 | /* 0 if we're not emitting a relaxable macro. | |
1274 | 1 if we're emitting the first of the two relaxation alternatives. | |
1275 | 2 if we're emitting the second alternative. */ | |
1276 | int sequence; | |
1277 | ||
1278 | /* The first relaxable fixup in the current frag. (In other words, | |
1279 | the first fixup that refers to relaxable code.) */ | |
1280 | fixS *first_fixup; | |
1281 | ||
1282 | /* sizes[0] says how many bytes of the first alternative are stored in | |
1283 | the current frag. Likewise sizes[1] for the second alternative. */ | |
1284 | unsigned int sizes[2]; | |
1285 | ||
1286 | /* The symbol on which the choice of sequence depends. */ | |
1287 | symbolS *symbol; | |
1288 | } mips_relax; | |
252b5132 | 1289 | \f |
584892a6 RS |
1290 | /* Global variables used to decide whether a macro needs a warning. */ |
1291 | static struct { | |
1292 | /* True if the macro is in a branch delay slot. */ | |
1293 | bfd_boolean delay_slot_p; | |
1294 | ||
df58fc94 RS |
1295 | /* Set to the length in bytes required if the macro is in a delay slot |
1296 | that requires a specific length of instruction, otherwise zero. */ | |
1297 | unsigned int delay_slot_length; | |
1298 | ||
584892a6 RS |
1299 | /* For relaxable macros, sizes[0] is the length of the first alternative |
1300 | in bytes and sizes[1] is the length of the second alternative. | |
1301 | For non-relaxable macros, both elements give the length of the | |
1302 | macro in bytes. */ | |
1303 | unsigned int sizes[2]; | |
1304 | ||
df58fc94 RS |
1305 | /* For relaxable macros, first_insn_sizes[0] is the length of the first |
1306 | instruction of the first alternative in bytes and first_insn_sizes[1] | |
1307 | is the length of the first instruction of the second alternative. | |
1308 | For non-relaxable macros, both elements give the length of the first | |
1309 | instruction in bytes. | |
1310 | ||
1311 | Set to zero if we haven't yet seen the first instruction. */ | |
1312 | unsigned int first_insn_sizes[2]; | |
1313 | ||
1314 | /* For relaxable macros, insns[0] is the number of instructions for the | |
1315 | first alternative and insns[1] is the number of instructions for the | |
1316 | second alternative. | |
1317 | ||
1318 | For non-relaxable macros, both elements give the number of | |
1319 | instructions for the macro. */ | |
1320 | unsigned int insns[2]; | |
1321 | ||
584892a6 RS |
1322 | /* The first variant frag for this macro. */ |
1323 | fragS *first_frag; | |
1324 | } mips_macro_warning; | |
1325 | \f | |
252b5132 RH |
1326 | /* Prototypes for static functions. */ |
1327 | ||
252b5132 RH |
1328 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; |
1329 | ||
b34976b6 | 1330 | static void append_insn |
df58fc94 RS |
1331 | (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *, |
1332 | bfd_boolean expansionp); | |
7d10b47d | 1333 | static void mips_no_prev_insn (void); |
c67a084a | 1334 | static void macro_build (expressionS *, const char *, const char *, ...); |
b34976b6 | 1335 | static void mips16_macro_build |
03ea81db | 1336 | (expressionS *, const char *, const char *, va_list *); |
67c0d1eb | 1337 | static void load_register (int, expressionS *, int); |
584892a6 RS |
1338 | static void macro_start (void); |
1339 | static void macro_end (void); | |
833794fc | 1340 | static void macro (struct mips_cl_insn *ip, char *str); |
17a2f251 | 1341 | static void mips16_macro (struct mips_cl_insn * ip); |
17a2f251 TS |
1342 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
1343 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 1344 | static void mips16_immed |
3b4dbbbf | 1345 | (const char *, unsigned int, int, bfd_reloc_code_real_type, offsetT, |
43c0598f | 1346 | unsigned int, unsigned long *); |
5e0116d5 | 1347 | static size_t my_getSmallExpression |
17a2f251 TS |
1348 | (expressionS *, bfd_reloc_code_real_type *, char *); |
1349 | static void my_getExpression (expressionS *, char *); | |
1350 | static void s_align (int); | |
1351 | static void s_change_sec (int); | |
1352 | static void s_change_section (int); | |
1353 | static void s_cons (int); | |
1354 | static void s_float_cons (int); | |
1355 | static void s_mips_globl (int); | |
1356 | static void s_option (int); | |
1357 | static void s_mipsset (int); | |
1358 | static void s_abicalls (int); | |
1359 | static void s_cpload (int); | |
1360 | static void s_cpsetup (int); | |
1361 | static void s_cplocal (int); | |
1362 | static void s_cprestore (int); | |
1363 | static void s_cpreturn (int); | |
741d6ea8 JM |
1364 | static void s_dtprelword (int); |
1365 | static void s_dtpreldword (int); | |
d0f13682 CLT |
1366 | static void s_tprelword (int); |
1367 | static void s_tpreldword (int); | |
17a2f251 TS |
1368 | static void s_gpvalue (int); |
1369 | static void s_gpword (int); | |
1370 | static void s_gpdword (int); | |
a3f278e2 | 1371 | static void s_ehword (int); |
17a2f251 TS |
1372 | static void s_cpadd (int); |
1373 | static void s_insn (int); | |
ba92f887 | 1374 | static void s_nan (int); |
919731af | 1375 | static void s_module (int); |
17a2f251 TS |
1376 | static void s_mips_ent (int); |
1377 | static void s_mips_end (int); | |
1378 | static void s_mips_frame (int); | |
1379 | static void s_mips_mask (int reg_type); | |
1380 | static void s_mips_stab (int); | |
1381 | static void s_mips_weakext (int); | |
1382 | static void s_mips_file (int); | |
1383 | static void s_mips_loc (int); | |
9e009953 | 1384 | static bfd_boolean pic_need_relax (symbolS *); |
4a6a3df4 | 1385 | static int relaxed_branch_length (fragS *, asection *, int); |
df58fc94 RS |
1386 | static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int); |
1387 | static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int); | |
919731af | 1388 | static void file_mips_check_options (void); |
e7af610e NC |
1389 | |
1390 | /* Table and functions used to map between CPU/ISA names, and | |
1391 | ISA levels, and CPU numbers. */ | |
1392 | ||
e972090a NC |
1393 | struct mips_cpu_info |
1394 | { | |
e7af610e | 1395 | const char *name; /* CPU or ISA name. */ |
d16afab6 RS |
1396 | int flags; /* MIPS_CPU_* flags. */ |
1397 | int ase; /* Set of ASEs implemented by the CPU. */ | |
e7af610e NC |
1398 | int isa; /* ISA level. */ |
1399 | int cpu; /* CPU number (default CPU if ISA). */ | |
1400 | }; | |
1401 | ||
ad3fea08 | 1402 | #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ |
ad3fea08 | 1403 | |
17a2f251 TS |
1404 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
1405 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
1406 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 | 1407 | \f |
c31f3936 RS |
1408 | /* Command-line options. */ |
1409 | const char *md_shortopts = "O::g::G:"; | |
1410 | ||
1411 | enum options | |
1412 | { | |
1413 | OPTION_MARCH = OPTION_MD_BASE, | |
1414 | OPTION_MTUNE, | |
1415 | OPTION_MIPS1, | |
1416 | OPTION_MIPS2, | |
1417 | OPTION_MIPS3, | |
1418 | OPTION_MIPS4, | |
1419 | OPTION_MIPS5, | |
1420 | OPTION_MIPS32, | |
1421 | OPTION_MIPS64, | |
1422 | OPTION_MIPS32R2, | |
ae52f483 AB |
1423 | OPTION_MIPS32R3, |
1424 | OPTION_MIPS32R5, | |
7361da2c | 1425 | OPTION_MIPS32R6, |
c31f3936 | 1426 | OPTION_MIPS64R2, |
ae52f483 AB |
1427 | OPTION_MIPS64R3, |
1428 | OPTION_MIPS64R5, | |
7361da2c | 1429 | OPTION_MIPS64R6, |
c31f3936 RS |
1430 | OPTION_MIPS16, |
1431 | OPTION_NO_MIPS16, | |
1432 | OPTION_MIPS3D, | |
1433 | OPTION_NO_MIPS3D, | |
1434 | OPTION_MDMX, | |
1435 | OPTION_NO_MDMX, | |
1436 | OPTION_DSP, | |
1437 | OPTION_NO_DSP, | |
1438 | OPTION_MT, | |
1439 | OPTION_NO_MT, | |
1440 | OPTION_VIRT, | |
1441 | OPTION_NO_VIRT, | |
56d438b1 CF |
1442 | OPTION_MSA, |
1443 | OPTION_NO_MSA, | |
c31f3936 RS |
1444 | OPTION_SMARTMIPS, |
1445 | OPTION_NO_SMARTMIPS, | |
1446 | OPTION_DSPR2, | |
1447 | OPTION_NO_DSPR2, | |
8f4f9071 MF |
1448 | OPTION_DSPR3, |
1449 | OPTION_NO_DSPR3, | |
c31f3936 RS |
1450 | OPTION_EVA, |
1451 | OPTION_NO_EVA, | |
7d64c587 AB |
1452 | OPTION_XPA, |
1453 | OPTION_NO_XPA, | |
c31f3936 RS |
1454 | OPTION_MICROMIPS, |
1455 | OPTION_NO_MICROMIPS, | |
1456 | OPTION_MCU, | |
1457 | OPTION_NO_MCU, | |
1458 | OPTION_COMPAT_ARCH_BASE, | |
1459 | OPTION_M4650, | |
1460 | OPTION_NO_M4650, | |
1461 | OPTION_M4010, | |
1462 | OPTION_NO_M4010, | |
1463 | OPTION_M4100, | |
1464 | OPTION_NO_M4100, | |
1465 | OPTION_M3900, | |
1466 | OPTION_NO_M3900, | |
1467 | OPTION_M7000_HILO_FIX, | |
1468 | OPTION_MNO_7000_HILO_FIX, | |
1469 | OPTION_FIX_24K, | |
1470 | OPTION_NO_FIX_24K, | |
a8d14a88 CM |
1471 | OPTION_FIX_RM7000, |
1472 | OPTION_NO_FIX_RM7000, | |
c31f3936 RS |
1473 | OPTION_FIX_LOONGSON2F_JUMP, |
1474 | OPTION_NO_FIX_LOONGSON2F_JUMP, | |
1475 | OPTION_FIX_LOONGSON2F_NOP, | |
1476 | OPTION_NO_FIX_LOONGSON2F_NOP, | |
1477 | OPTION_FIX_VR4120, | |
1478 | OPTION_NO_FIX_VR4120, | |
1479 | OPTION_FIX_VR4130, | |
1480 | OPTION_NO_FIX_VR4130, | |
1481 | OPTION_FIX_CN63XXP1, | |
1482 | OPTION_NO_FIX_CN63XXP1, | |
1483 | OPTION_TRAP, | |
1484 | OPTION_BREAK, | |
1485 | OPTION_EB, | |
1486 | OPTION_EL, | |
1487 | OPTION_FP32, | |
1488 | OPTION_GP32, | |
1489 | OPTION_CONSTRUCT_FLOATS, | |
1490 | OPTION_NO_CONSTRUCT_FLOATS, | |
1491 | OPTION_FP64, | |
351cdf24 | 1492 | OPTION_FPXX, |
c31f3936 RS |
1493 | OPTION_GP64, |
1494 | OPTION_RELAX_BRANCH, | |
1495 | OPTION_NO_RELAX_BRANCH, | |
8b10b0b3 MR |
1496 | OPTION_IGNORE_BRANCH_ISA, |
1497 | OPTION_NO_IGNORE_BRANCH_ISA, | |
833794fc MR |
1498 | OPTION_INSN32, |
1499 | OPTION_NO_INSN32, | |
c31f3936 RS |
1500 | OPTION_MSHARED, |
1501 | OPTION_MNO_SHARED, | |
1502 | OPTION_MSYM32, | |
1503 | OPTION_MNO_SYM32, | |
1504 | OPTION_SOFT_FLOAT, | |
1505 | OPTION_HARD_FLOAT, | |
1506 | OPTION_SINGLE_FLOAT, | |
1507 | OPTION_DOUBLE_FLOAT, | |
1508 | OPTION_32, | |
c31f3936 RS |
1509 | OPTION_CALL_SHARED, |
1510 | OPTION_CALL_NONPIC, | |
1511 | OPTION_NON_SHARED, | |
1512 | OPTION_XGOT, | |
1513 | OPTION_MABI, | |
1514 | OPTION_N32, | |
1515 | OPTION_64, | |
1516 | OPTION_MDEBUG, | |
1517 | OPTION_NO_MDEBUG, | |
1518 | OPTION_PDR, | |
1519 | OPTION_NO_PDR, | |
1520 | OPTION_MVXWORKS_PIC, | |
ba92f887 | 1521 | OPTION_NAN, |
351cdf24 MF |
1522 | OPTION_ODD_SPREG, |
1523 | OPTION_NO_ODD_SPREG, | |
c31f3936 RS |
1524 | OPTION_END_OF_ENUM |
1525 | }; | |
1526 | ||
1527 | struct option md_longopts[] = | |
1528 | { | |
1529 | /* Options which specify architecture. */ | |
1530 | {"march", required_argument, NULL, OPTION_MARCH}, | |
1531 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
1532 | {"mips0", no_argument, NULL, OPTION_MIPS1}, | |
1533 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
1534 | {"mips2", no_argument, NULL, OPTION_MIPS2}, | |
1535 | {"mips3", no_argument, NULL, OPTION_MIPS3}, | |
1536 | {"mips4", no_argument, NULL, OPTION_MIPS4}, | |
1537 | {"mips5", no_argument, NULL, OPTION_MIPS5}, | |
1538 | {"mips32", no_argument, NULL, OPTION_MIPS32}, | |
1539 | {"mips64", no_argument, NULL, OPTION_MIPS64}, | |
1540 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, | |
ae52f483 AB |
1541 | {"mips32r3", no_argument, NULL, OPTION_MIPS32R3}, |
1542 | {"mips32r5", no_argument, NULL, OPTION_MIPS32R5}, | |
7361da2c | 1543 | {"mips32r6", no_argument, NULL, OPTION_MIPS32R6}, |
c31f3936 | 1544 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, |
ae52f483 AB |
1545 | {"mips64r3", no_argument, NULL, OPTION_MIPS64R3}, |
1546 | {"mips64r5", no_argument, NULL, OPTION_MIPS64R5}, | |
7361da2c | 1547 | {"mips64r6", no_argument, NULL, OPTION_MIPS64R6}, |
c31f3936 RS |
1548 | |
1549 | /* Options which specify Application Specific Extensions (ASEs). */ | |
1550 | {"mips16", no_argument, NULL, OPTION_MIPS16}, | |
1551 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, | |
1552 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, | |
1553 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, | |
1554 | {"mdmx", no_argument, NULL, OPTION_MDMX}, | |
1555 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, | |
1556 | {"mdsp", no_argument, NULL, OPTION_DSP}, | |
1557 | {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, | |
1558 | {"mmt", no_argument, NULL, OPTION_MT}, | |
1559 | {"mno-mt", no_argument, NULL, OPTION_NO_MT}, | |
1560 | {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS}, | |
1561 | {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS}, | |
1562 | {"mdspr2", no_argument, NULL, OPTION_DSPR2}, | |
1563 | {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2}, | |
8f4f9071 MF |
1564 | {"mdspr3", no_argument, NULL, OPTION_DSPR3}, |
1565 | {"mno-dspr3", no_argument, NULL, OPTION_NO_DSPR3}, | |
c31f3936 RS |
1566 | {"meva", no_argument, NULL, OPTION_EVA}, |
1567 | {"mno-eva", no_argument, NULL, OPTION_NO_EVA}, | |
1568 | {"mmicromips", no_argument, NULL, OPTION_MICROMIPS}, | |
1569 | {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS}, | |
1570 | {"mmcu", no_argument, NULL, OPTION_MCU}, | |
1571 | {"mno-mcu", no_argument, NULL, OPTION_NO_MCU}, | |
1572 | {"mvirt", no_argument, NULL, OPTION_VIRT}, | |
1573 | {"mno-virt", no_argument, NULL, OPTION_NO_VIRT}, | |
56d438b1 CF |
1574 | {"mmsa", no_argument, NULL, OPTION_MSA}, |
1575 | {"mno-msa", no_argument, NULL, OPTION_NO_MSA}, | |
7d64c587 AB |
1576 | {"mxpa", no_argument, NULL, OPTION_XPA}, |
1577 | {"mno-xpa", no_argument, NULL, OPTION_NO_XPA}, | |
c31f3936 RS |
1578 | |
1579 | /* Old-style architecture options. Don't add more of these. */ | |
1580 | {"m4650", no_argument, NULL, OPTION_M4650}, | |
1581 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, | |
1582 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
1583 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
1584 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
1585 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
1586 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
1587 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
1588 | ||
1589 | /* Options which enable bug fixes. */ | |
1590 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, | |
1591 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
1592 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
1593 | {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP}, | |
1594 | {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP}, | |
1595 | {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP}, | |
1596 | {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP}, | |
1597 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, | |
1598 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
1599 | {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, | |
1600 | {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, | |
1601 | {"mfix-24k", no_argument, NULL, OPTION_FIX_24K}, | |
1602 | {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K}, | |
a8d14a88 CM |
1603 | {"mfix-rm7000", no_argument, NULL, OPTION_FIX_RM7000}, |
1604 | {"mno-fix-rm7000", no_argument, NULL, OPTION_NO_FIX_RM7000}, | |
c31f3936 RS |
1605 | {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1}, |
1606 | {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1}, | |
1607 | ||
1608 | /* Miscellaneous options. */ | |
1609 | {"trap", no_argument, NULL, OPTION_TRAP}, | |
1610 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
1611 | {"break", no_argument, NULL, OPTION_BREAK}, | |
1612 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
1613 | {"EB", no_argument, NULL, OPTION_EB}, | |
1614 | {"EL", no_argument, NULL, OPTION_EL}, | |
1615 | {"mfp32", no_argument, NULL, OPTION_FP32}, | |
1616 | {"mgp32", no_argument, NULL, OPTION_GP32}, | |
1617 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, | |
1618 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, | |
1619 | {"mfp64", no_argument, NULL, OPTION_FP64}, | |
351cdf24 | 1620 | {"mfpxx", no_argument, NULL, OPTION_FPXX}, |
c31f3936 RS |
1621 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
1622 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, | |
1623 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
8b10b0b3 MR |
1624 | {"mignore-branch-isa", no_argument, NULL, OPTION_IGNORE_BRANCH_ISA}, |
1625 | {"mno-ignore-branch-isa", no_argument, NULL, OPTION_NO_IGNORE_BRANCH_ISA}, | |
833794fc MR |
1626 | {"minsn32", no_argument, NULL, OPTION_INSN32}, |
1627 | {"mno-insn32", no_argument, NULL, OPTION_NO_INSN32}, | |
c31f3936 RS |
1628 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
1629 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
1630 | {"msym32", no_argument, NULL, OPTION_MSYM32}, | |
1631 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, | |
1632 | {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT}, | |
1633 | {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT}, | |
1634 | {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT}, | |
1635 | {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT}, | |
351cdf24 MF |
1636 | {"modd-spreg", no_argument, NULL, OPTION_ODD_SPREG}, |
1637 | {"mno-odd-spreg", no_argument, NULL, OPTION_NO_ODD_SPREG}, | |
c31f3936 RS |
1638 | |
1639 | /* Strictly speaking this next option is ELF specific, | |
1640 | but we allow it for other ports as well in order to | |
1641 | make testing easier. */ | |
1642 | {"32", no_argument, NULL, OPTION_32}, | |
1643 | ||
1644 | /* ELF-specific options. */ | |
c31f3936 RS |
1645 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
1646 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
1647 | {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC}, | |
1648 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, | |
1649 | {"xgot", no_argument, NULL, OPTION_XGOT}, | |
1650 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
1651 | {"n32", no_argument, NULL, OPTION_N32}, | |
1652 | {"64", no_argument, NULL, OPTION_64}, | |
1653 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, | |
1654 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, | |
1655 | {"mpdr", no_argument, NULL, OPTION_PDR}, | |
1656 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, | |
1657 | {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, | |
ba92f887 | 1658 | {"mnan", required_argument, NULL, OPTION_NAN}, |
c31f3936 RS |
1659 | |
1660 | {NULL, no_argument, NULL, 0} | |
1661 | }; | |
1662 | size_t md_longopts_size = sizeof (md_longopts); | |
1663 | \f | |
c6278170 RS |
1664 | /* Information about either an Application Specific Extension or an |
1665 | optional architecture feature that, for simplicity, we treat in the | |
1666 | same way as an ASE. */ | |
1667 | struct mips_ase | |
1668 | { | |
1669 | /* The name of the ASE, used in both the command-line and .set options. */ | |
1670 | const char *name; | |
1671 | ||
1672 | /* The associated ASE_* flags. If the ASE is available on both 32-bit | |
1673 | and 64-bit architectures, the flags here refer to the subset that | |
1674 | is available on both. */ | |
1675 | unsigned int flags; | |
1676 | ||
1677 | /* The ASE_* flag used for instructions that are available on 64-bit | |
1678 | architectures but that are not included in FLAGS. */ | |
1679 | unsigned int flags64; | |
1680 | ||
1681 | /* The command-line options that turn the ASE on and off. */ | |
1682 | int option_on; | |
1683 | int option_off; | |
1684 | ||
1685 | /* The minimum required architecture revisions for MIPS32, MIPS64, | |
1686 | microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */ | |
1687 | int mips32_rev; | |
1688 | int mips64_rev; | |
1689 | int micromips32_rev; | |
1690 | int micromips64_rev; | |
7361da2c AB |
1691 | |
1692 | /* The architecture where the ASE was removed or -1 if the extension has not | |
1693 | been removed. */ | |
1694 | int rem_rev; | |
c6278170 RS |
1695 | }; |
1696 | ||
1697 | /* A table of all supported ASEs. */ | |
1698 | static const struct mips_ase mips_ases[] = { | |
1699 | { "dsp", ASE_DSP, ASE_DSP64, | |
1700 | OPTION_DSP, OPTION_NO_DSP, | |
7361da2c AB |
1701 | 2, 2, 2, 2, |
1702 | -1 }, | |
c6278170 RS |
1703 | |
1704 | { "dspr2", ASE_DSP | ASE_DSPR2, 0, | |
1705 | OPTION_DSPR2, OPTION_NO_DSPR2, | |
7361da2c AB |
1706 | 2, 2, 2, 2, |
1707 | -1 }, | |
c6278170 | 1708 | |
8f4f9071 MF |
1709 | { "dspr3", ASE_DSP | ASE_DSPR2 | ASE_DSPR3, 0, |
1710 | OPTION_DSPR3, OPTION_NO_DSPR3, | |
1711 | 6, 6, -1, -1, | |
1712 | -1 }, | |
1713 | ||
c6278170 RS |
1714 | { "eva", ASE_EVA, 0, |
1715 | OPTION_EVA, OPTION_NO_EVA, | |
7361da2c AB |
1716 | 2, 2, 2, 2, |
1717 | -1 }, | |
c6278170 RS |
1718 | |
1719 | { "mcu", ASE_MCU, 0, | |
1720 | OPTION_MCU, OPTION_NO_MCU, | |
7361da2c AB |
1721 | 2, 2, 2, 2, |
1722 | -1 }, | |
c6278170 RS |
1723 | |
1724 | /* Deprecated in MIPS64r5, but we don't implement that yet. */ | |
1725 | { "mdmx", ASE_MDMX, 0, | |
1726 | OPTION_MDMX, OPTION_NO_MDMX, | |
7361da2c AB |
1727 | -1, 1, -1, -1, |
1728 | 6 }, | |
c6278170 RS |
1729 | |
1730 | /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */ | |
1731 | { "mips3d", ASE_MIPS3D, 0, | |
1732 | OPTION_MIPS3D, OPTION_NO_MIPS3D, | |
7361da2c AB |
1733 | 2, 1, -1, -1, |
1734 | 6 }, | |
c6278170 RS |
1735 | |
1736 | { "mt", ASE_MT, 0, | |
1737 | OPTION_MT, OPTION_NO_MT, | |
7361da2c AB |
1738 | 2, 2, -1, -1, |
1739 | -1 }, | |
c6278170 RS |
1740 | |
1741 | { "smartmips", ASE_SMARTMIPS, 0, | |
1742 | OPTION_SMARTMIPS, OPTION_NO_SMARTMIPS, | |
7361da2c AB |
1743 | 1, -1, -1, -1, |
1744 | 6 }, | |
c6278170 RS |
1745 | |
1746 | { "virt", ASE_VIRT, ASE_VIRT64, | |
1747 | OPTION_VIRT, OPTION_NO_VIRT, | |
7361da2c AB |
1748 | 2, 2, 2, 2, |
1749 | -1 }, | |
56d438b1 CF |
1750 | |
1751 | { "msa", ASE_MSA, ASE_MSA64, | |
1752 | OPTION_MSA, OPTION_NO_MSA, | |
7361da2c AB |
1753 | 2, 2, 2, 2, |
1754 | -1 }, | |
7d64c587 AB |
1755 | |
1756 | { "xpa", ASE_XPA, 0, | |
1757 | OPTION_XPA, OPTION_NO_XPA, | |
7361da2c AB |
1758 | 2, 2, -1, -1, |
1759 | -1 }, | |
c6278170 RS |
1760 | }; |
1761 | ||
1762 | /* The set of ASEs that require -mfp64. */ | |
82bda27b | 1763 | #define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA) |
c6278170 RS |
1764 | |
1765 | /* Groups of ASE_* flags that represent different revisions of an ASE. */ | |
1766 | static const unsigned int mips_ase_groups[] = { | |
8f4f9071 | 1767 | ASE_DSP | ASE_DSPR2 | ASE_DSPR3 |
c6278170 RS |
1768 | }; |
1769 | \f | |
252b5132 RH |
1770 | /* Pseudo-op table. |
1771 | ||
1772 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
1773 | should be defined here, but are currently unsupported: .alias, | |
1774 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
1775 | ||
1776 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1777 | specific to the type of debugging information being generated, and | |
1778 | should be defined by the object format: .aent, .begin, .bend, | |
1779 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
1780 | .vreg. | |
1781 | ||
1782 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1783 | not MIPS CPU specific, but are also not specific to the object file | |
1784 | format. This file is probably the best place to define them, but | |
d84bcf09 | 1785 | they are not currently supported: .asm0, .endr, .lab, .struct. */ |
252b5132 | 1786 | |
e972090a NC |
1787 | static const pseudo_typeS mips_pseudo_table[] = |
1788 | { | |
beae10d5 | 1789 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1790 | {"option", s_option, 0}, |
1791 | {"set", s_mipsset, 0}, | |
1792 | {"rdata", s_change_sec, 'r'}, | |
1793 | {"sdata", s_change_sec, 's'}, | |
1794 | {"livereg", s_ignore, 0}, | |
1795 | {"abicalls", s_abicalls, 0}, | |
1796 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1797 | {"cpsetup", s_cpsetup, 0}, |
1798 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1799 | {"cprestore", s_cprestore, 0}, |
6478892d | 1800 | {"cpreturn", s_cpreturn, 0}, |
741d6ea8 JM |
1801 | {"dtprelword", s_dtprelword, 0}, |
1802 | {"dtpreldword", s_dtpreldword, 0}, | |
d0f13682 CLT |
1803 | {"tprelword", s_tprelword, 0}, |
1804 | {"tpreldword", s_tpreldword, 0}, | |
6478892d | 1805 | {"gpvalue", s_gpvalue, 0}, |
252b5132 | 1806 | {"gpword", s_gpword, 0}, |
10181a0d | 1807 | {"gpdword", s_gpdword, 0}, |
a3f278e2 | 1808 | {"ehword", s_ehword, 0}, |
252b5132 RH |
1809 | {"cpadd", s_cpadd, 0}, |
1810 | {"insn", s_insn, 0}, | |
ba92f887 | 1811 | {"nan", s_nan, 0}, |
919731af | 1812 | {"module", s_module, 0}, |
252b5132 | 1813 | |
beae10d5 | 1814 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 | 1815 | chips. */ |
38a57ae7 | 1816 | {"asciiz", stringer, 8 + 1}, |
252b5132 RH |
1817 | {"bss", s_change_sec, 'b'}, |
1818 | {"err", s_err, 0}, | |
1819 | {"half", s_cons, 1}, | |
1820 | {"dword", s_cons, 3}, | |
1821 | {"weakext", s_mips_weakext, 0}, | |
7c752c2a TS |
1822 | {"origin", s_org, 0}, |
1823 | {"repeat", s_rept, 0}, | |
252b5132 | 1824 | |
998b3c36 MR |
1825 | /* For MIPS this is non-standard, but we define it for consistency. */ |
1826 | {"sbss", s_change_sec, 'B'}, | |
1827 | ||
beae10d5 | 1828 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1829 | here for one reason or another. */ |
1830 | {"align", s_align, 0}, | |
1831 | {"byte", s_cons, 0}, | |
1832 | {"data", s_change_sec, 'd'}, | |
1833 | {"double", s_float_cons, 'd'}, | |
1834 | {"float", s_float_cons, 'f'}, | |
1835 | {"globl", s_mips_globl, 0}, | |
1836 | {"global", s_mips_globl, 0}, | |
1837 | {"hword", s_cons, 1}, | |
1838 | {"int", s_cons, 2}, | |
1839 | {"long", s_cons, 2}, | |
1840 | {"octa", s_cons, 4}, | |
1841 | {"quad", s_cons, 3}, | |
cca86cc8 | 1842 | {"section", s_change_section, 0}, |
252b5132 RH |
1843 | {"short", s_cons, 1}, |
1844 | {"single", s_float_cons, 'f'}, | |
754e2bb9 | 1845 | {"stabd", s_mips_stab, 'd'}, |
252b5132 | 1846 | {"stabn", s_mips_stab, 'n'}, |
754e2bb9 | 1847 | {"stabs", s_mips_stab, 's'}, |
252b5132 RH |
1848 | {"text", s_change_sec, 't'}, |
1849 | {"word", s_cons, 2}, | |
add56521 | 1850 | |
add56521 | 1851 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1852 | |
43841e91 | 1853 | { NULL, NULL, 0 }, |
252b5132 RH |
1854 | }; |
1855 | ||
e972090a NC |
1856 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1857 | { | |
beae10d5 KH |
1858 | /* These pseudo-ops should be defined by the object file format. |
1859 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1860 | {"aent", s_mips_ent, 1}, |
1861 | {"bgnb", s_ignore, 0}, | |
1862 | {"end", s_mips_end, 0}, | |
1863 | {"endb", s_ignore, 0}, | |
1864 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1865 | {"file", s_mips_file, 0}, |
252b5132 RH |
1866 | {"fmask", s_mips_mask, 'F'}, |
1867 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1868 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1869 | {"mask", s_mips_mask, 'R'}, |
1870 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1871 | { NULL, NULL, 0 }, |
252b5132 RH |
1872 | }; |
1873 | ||
3ae8dd8d MR |
1874 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
1875 | purpose of the `.dc.a' internal pseudo-op. */ | |
1876 | ||
1877 | int | |
1878 | mips_address_bytes (void) | |
1879 | { | |
919731af | 1880 | file_mips_check_options (); |
3ae8dd8d MR |
1881 | return HAVE_64BIT_ADDRESSES ? 8 : 4; |
1882 | } | |
1883 | ||
17a2f251 | 1884 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1885 | |
1886 | void | |
17a2f251 | 1887 | mips_pop_insert (void) |
252b5132 RH |
1888 | { |
1889 | pop_insert (mips_pseudo_table); | |
1890 | if (! ECOFF_DEBUGGING) | |
1891 | pop_insert (mips_nonecoff_pseudo_table); | |
1892 | } | |
1893 | \f | |
1894 | /* Symbols labelling the current insn. */ | |
1895 | ||
e972090a NC |
1896 | struct insn_label_list |
1897 | { | |
252b5132 RH |
1898 | struct insn_label_list *next; |
1899 | symbolS *label; | |
1900 | }; | |
1901 | ||
252b5132 | 1902 | static struct insn_label_list *free_insn_labels; |
742a56fe | 1903 | #define label_list tc_segment_info_data.labels |
252b5132 | 1904 | |
17a2f251 | 1905 | static void mips_clear_insn_labels (void); |
df58fc94 RS |
1906 | static void mips_mark_labels (void); |
1907 | static void mips_compressed_mark_labels (void); | |
252b5132 RH |
1908 | |
1909 | static inline void | |
17a2f251 | 1910 | mips_clear_insn_labels (void) |
252b5132 | 1911 | { |
ed9e98c2 | 1912 | struct insn_label_list **pl; |
a8dbcb85 | 1913 | segment_info_type *si; |
252b5132 | 1914 | |
a8dbcb85 TS |
1915 | if (now_seg) |
1916 | { | |
1917 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1918 | ; | |
3739860c | 1919 | |
a8dbcb85 TS |
1920 | si = seg_info (now_seg); |
1921 | *pl = si->label_list; | |
1922 | si->label_list = NULL; | |
1923 | } | |
252b5132 | 1924 | } |
a8dbcb85 | 1925 | |
df58fc94 RS |
1926 | /* Mark instruction labels in MIPS16/microMIPS mode. */ |
1927 | ||
1928 | static inline void | |
1929 | mips_mark_labels (void) | |
1930 | { | |
1931 | if (HAVE_CODE_COMPRESSION) | |
1932 | mips_compressed_mark_labels (); | |
1933 | } | |
252b5132 RH |
1934 | \f |
1935 | static char *expr_end; | |
1936 | ||
e423441d | 1937 | /* An expression in a macro instruction. This is set by mips_ip and |
b0e6f033 | 1938 | mips16_ip and when populated is always an O_constant. */ |
252b5132 RH |
1939 | |
1940 | static expressionS imm_expr; | |
252b5132 | 1941 | |
77bd4346 RS |
1942 | /* The relocatable field in an instruction and the relocs associated |
1943 | with it. These variables are used for instructions like LUI and | |
1944 | JAL as well as true offsets. They are also used for address | |
1945 | operands in macros. */ | |
252b5132 | 1946 | |
77bd4346 | 1947 | static expressionS offset_expr; |
f6688943 TS |
1948 | static bfd_reloc_code_real_type offset_reloc[3] |
1949 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1950 | |
df58fc94 RS |
1951 | /* This is set to the resulting size of the instruction to be produced |
1952 | by mips16_ip if an explicit extension is used or by mips_ip if an | |
1953 | explicit size is supplied. */ | |
252b5132 | 1954 | |
df58fc94 | 1955 | static unsigned int forced_insn_length; |
252b5132 | 1956 | |
e1b47bd5 RS |
1957 | /* True if we are assembling an instruction. All dot symbols defined during |
1958 | this time should be treated as code labels. */ | |
1959 | ||
1960 | static bfd_boolean mips_assembling_insn; | |
1961 | ||
ecb4347a DJ |
1962 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1963 | ECOFF debugging. */ | |
252b5132 RH |
1964 | |
1965 | static segT pdr_seg; | |
252b5132 | 1966 | |
e013f690 TS |
1967 | /* The default target format to use. */ |
1968 | ||
aeffff67 RS |
1969 | #if defined (TE_FreeBSD) |
1970 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd" | |
1971 | #elif defined (TE_TMIPS) | |
1972 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips" | |
1973 | #else | |
1974 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips" | |
1975 | #endif | |
1976 | ||
e013f690 | 1977 | const char * |
17a2f251 | 1978 | mips_target_format (void) |
e013f690 TS |
1979 | { |
1980 | switch (OUTPUT_FLAVOR) | |
1981 | { | |
e013f690 | 1982 | case bfd_target_elf_flavour: |
0a44bf69 RS |
1983 | #ifdef TE_VXWORKS |
1984 | if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI) | |
1985 | return (target_big_endian | |
1986 | ? "elf32-bigmips-vxworks" | |
1987 | : "elf32-littlemips-vxworks"); | |
1988 | #endif | |
e013f690 | 1989 | return (target_big_endian |
cfe86eaa | 1990 | ? (HAVE_64BIT_OBJECTS |
aeffff67 | 1991 | ? ELF_TARGET ("elf64-", "big") |
cfe86eaa | 1992 | : (HAVE_NEWABI |
aeffff67 RS |
1993 | ? ELF_TARGET ("elf32-n", "big") |
1994 | : ELF_TARGET ("elf32-", "big"))) | |
cfe86eaa | 1995 | : (HAVE_64BIT_OBJECTS |
aeffff67 | 1996 | ? ELF_TARGET ("elf64-", "little") |
cfe86eaa | 1997 | : (HAVE_NEWABI |
aeffff67 RS |
1998 | ? ELF_TARGET ("elf32-n", "little") |
1999 | : ELF_TARGET ("elf32-", "little")))); | |
e013f690 TS |
2000 | default: |
2001 | abort (); | |
2002 | return NULL; | |
2003 | } | |
2004 | } | |
2005 | ||
c6278170 RS |
2006 | /* Return the ISA revision that is currently in use, or 0 if we are |
2007 | generating code for MIPS V or below. */ | |
2008 | ||
2009 | static int | |
2010 | mips_isa_rev (void) | |
2011 | { | |
2012 | if (mips_opts.isa == ISA_MIPS32R2 || mips_opts.isa == ISA_MIPS64R2) | |
2013 | return 2; | |
2014 | ||
ae52f483 AB |
2015 | if (mips_opts.isa == ISA_MIPS32R3 || mips_opts.isa == ISA_MIPS64R3) |
2016 | return 3; | |
2017 | ||
2018 | if (mips_opts.isa == ISA_MIPS32R5 || mips_opts.isa == ISA_MIPS64R5) | |
2019 | return 5; | |
2020 | ||
7361da2c AB |
2021 | if (mips_opts.isa == ISA_MIPS32R6 || mips_opts.isa == ISA_MIPS64R6) |
2022 | return 6; | |
2023 | ||
c6278170 RS |
2024 | /* microMIPS implies revision 2 or above. */ |
2025 | if (mips_opts.micromips) | |
2026 | return 2; | |
2027 | ||
2028 | if (mips_opts.isa == ISA_MIPS32 || mips_opts.isa == ISA_MIPS64) | |
2029 | return 1; | |
2030 | ||
2031 | return 0; | |
2032 | } | |
2033 | ||
2034 | /* Return the mask of all ASEs that are revisions of those in FLAGS. */ | |
2035 | ||
2036 | static unsigned int | |
2037 | mips_ase_mask (unsigned int flags) | |
2038 | { | |
2039 | unsigned int i; | |
2040 | ||
2041 | for (i = 0; i < ARRAY_SIZE (mips_ase_groups); i++) | |
2042 | if (flags & mips_ase_groups[i]) | |
2043 | flags |= mips_ase_groups[i]; | |
2044 | return flags; | |
2045 | } | |
2046 | ||
2047 | /* Check whether the current ISA supports ASE. Issue a warning if | |
2048 | appropriate. */ | |
2049 | ||
2050 | static void | |
2051 | mips_check_isa_supports_ase (const struct mips_ase *ase) | |
2052 | { | |
2053 | const char *base; | |
2054 | int min_rev, size; | |
2055 | static unsigned int warned_isa; | |
2056 | static unsigned int warned_fp32; | |
2057 | ||
2058 | if (ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
2059 | min_rev = mips_opts.micromips ? ase->micromips64_rev : ase->mips64_rev; | |
2060 | else | |
2061 | min_rev = mips_opts.micromips ? ase->micromips32_rev : ase->mips32_rev; | |
2062 | if ((min_rev < 0 || mips_isa_rev () < min_rev) | |
2063 | && (warned_isa & ase->flags) != ase->flags) | |
2064 | { | |
2065 | warned_isa |= ase->flags; | |
2066 | base = mips_opts.micromips ? "microMIPS" : "MIPS"; | |
2067 | size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32; | |
2068 | if (min_rev < 0) | |
1661c76c | 2069 | as_warn (_("the %d-bit %s architecture does not support the" |
c6278170 RS |
2070 | " `%s' extension"), size, base, ase->name); |
2071 | else | |
1661c76c | 2072 | as_warn (_("the `%s' extension requires %s%d revision %d or greater"), |
c6278170 RS |
2073 | ase->name, base, size, min_rev); |
2074 | } | |
7361da2c AB |
2075 | else if ((ase->rem_rev > 0 && mips_isa_rev () >= ase->rem_rev) |
2076 | && (warned_isa & ase->flags) != ase->flags) | |
2077 | { | |
2078 | warned_isa |= ase->flags; | |
2079 | base = mips_opts.micromips ? "microMIPS" : "MIPS"; | |
2080 | size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32; | |
2081 | as_warn (_("the `%s' extension was removed in %s%d revision %d"), | |
2082 | ase->name, base, size, ase->rem_rev); | |
2083 | } | |
2084 | ||
c6278170 | 2085 | if ((ase->flags & FP64_ASES) |
0b35dfee | 2086 | && mips_opts.fp != 64 |
c6278170 RS |
2087 | && (warned_fp32 & ase->flags) != ase->flags) |
2088 | { | |
2089 | warned_fp32 |= ase->flags; | |
1661c76c | 2090 | as_warn (_("the `%s' extension requires 64-bit FPRs"), ase->name); |
c6278170 RS |
2091 | } |
2092 | } | |
2093 | ||
2094 | /* Check all enabled ASEs to see whether they are supported by the | |
2095 | chosen architecture. */ | |
2096 | ||
2097 | static void | |
2098 | mips_check_isa_supports_ases (void) | |
2099 | { | |
2100 | unsigned int i, mask; | |
2101 | ||
2102 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
2103 | { | |
2104 | mask = mips_ase_mask (mips_ases[i].flags); | |
2105 | if ((mips_opts.ase & mask) == mips_ases[i].flags) | |
2106 | mips_check_isa_supports_ase (&mips_ases[i]); | |
2107 | } | |
2108 | } | |
2109 | ||
2110 | /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags | |
2111 | that were affected. */ | |
2112 | ||
2113 | static unsigned int | |
919731af | 2114 | mips_set_ase (const struct mips_ase *ase, struct mips_set_options *opts, |
2115 | bfd_boolean enabled_p) | |
c6278170 RS |
2116 | { |
2117 | unsigned int mask; | |
2118 | ||
2119 | mask = mips_ase_mask (ase->flags); | |
919731af | 2120 | opts->ase &= ~mask; |
c6278170 | 2121 | if (enabled_p) |
919731af | 2122 | opts->ase |= ase->flags; |
c6278170 RS |
2123 | return mask; |
2124 | } | |
2125 | ||
2126 | /* Return the ASE called NAME, or null if none. */ | |
2127 | ||
2128 | static const struct mips_ase * | |
2129 | mips_lookup_ase (const char *name) | |
2130 | { | |
2131 | unsigned int i; | |
2132 | ||
2133 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
2134 | if (strcmp (name, mips_ases[i].name) == 0) | |
2135 | return &mips_ases[i]; | |
2136 | return NULL; | |
2137 | } | |
2138 | ||
df58fc94 | 2139 | /* Return the length of a microMIPS instruction in bytes. If bits of |
100b4f2e MR |
2140 | the mask beyond the low 16 are 0, then it is a 16-bit instruction, |
2141 | otherwise it is a 32-bit instruction. */ | |
df58fc94 RS |
2142 | |
2143 | static inline unsigned int | |
2144 | micromips_insn_length (const struct mips_opcode *mo) | |
2145 | { | |
7fd53920 | 2146 | return mips_opcode_32bit_p (mo) ? 4 : 2; |
df58fc94 RS |
2147 | } |
2148 | ||
5c04167a RS |
2149 | /* Return the length of MIPS16 instruction OPCODE. */ |
2150 | ||
2151 | static inline unsigned int | |
2152 | mips16_opcode_length (unsigned long opcode) | |
2153 | { | |
2154 | return (opcode >> 16) == 0 ? 2 : 4; | |
2155 | } | |
2156 | ||
1e915849 RS |
2157 | /* Return the length of instruction INSN. */ |
2158 | ||
2159 | static inline unsigned int | |
2160 | insn_length (const struct mips_cl_insn *insn) | |
2161 | { | |
df58fc94 RS |
2162 | if (mips_opts.micromips) |
2163 | return micromips_insn_length (insn->insn_mo); | |
2164 | else if (mips_opts.mips16) | |
5c04167a | 2165 | return mips16_opcode_length (insn->insn_opcode); |
df58fc94 | 2166 | else |
1e915849 | 2167 | return 4; |
1e915849 RS |
2168 | } |
2169 | ||
2170 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
2171 | ||
2172 | static void | |
2173 | create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) | |
2174 | { | |
2175 | size_t i; | |
2176 | ||
2177 | insn->insn_mo = mo; | |
1e915849 RS |
2178 | insn->insn_opcode = mo->match; |
2179 | insn->frag = NULL; | |
2180 | insn->where = 0; | |
2181 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
2182 | insn->fixp[i] = NULL; | |
2183 | insn->fixed_p = (mips_opts.noreorder > 0); | |
2184 | insn->noreorder_p = (mips_opts.noreorder > 0); | |
2185 | insn->mips16_absolute_jump_p = 0; | |
15be625d | 2186 | insn->complete_p = 0; |
e407c74b | 2187 | insn->cleared_p = 0; |
1e915849 RS |
2188 | } |
2189 | ||
fc76e730 RS |
2190 | /* Get a list of all the operands in INSN. */ |
2191 | ||
2192 | static const struct mips_operand_array * | |
2193 | insn_operands (const struct mips_cl_insn *insn) | |
2194 | { | |
2195 | if (insn->insn_mo >= &mips_opcodes[0] | |
2196 | && insn->insn_mo < &mips_opcodes[NUMOPCODES]) | |
2197 | return &mips_operands[insn->insn_mo - &mips_opcodes[0]]; | |
2198 | ||
2199 | if (insn->insn_mo >= &mips16_opcodes[0] | |
2200 | && insn->insn_mo < &mips16_opcodes[bfd_mips16_num_opcodes]) | |
2201 | return &mips16_operands[insn->insn_mo - &mips16_opcodes[0]]; | |
2202 | ||
2203 | if (insn->insn_mo >= µmips_opcodes[0] | |
2204 | && insn->insn_mo < µmips_opcodes[bfd_micromips_num_opcodes]) | |
2205 | return µmips_operands[insn->insn_mo - µmips_opcodes[0]]; | |
2206 | ||
2207 | abort (); | |
2208 | } | |
2209 | ||
2210 | /* Get a description of operand OPNO of INSN. */ | |
2211 | ||
2212 | static const struct mips_operand * | |
2213 | insn_opno (const struct mips_cl_insn *insn, unsigned opno) | |
2214 | { | |
2215 | const struct mips_operand_array *operands; | |
2216 | ||
2217 | operands = insn_operands (insn); | |
2218 | if (opno >= MAX_OPERANDS || !operands->operand[opno]) | |
2219 | abort (); | |
2220 | return operands->operand[opno]; | |
2221 | } | |
2222 | ||
e077a1c8 RS |
2223 | /* Install UVAL as the value of OPERAND in INSN. */ |
2224 | ||
2225 | static inline void | |
2226 | insn_insert_operand (struct mips_cl_insn *insn, | |
2227 | const struct mips_operand *operand, unsigned int uval) | |
2228 | { | |
2229 | insn->insn_opcode = mips_insert_operand (operand, insn->insn_opcode, uval); | |
2230 | } | |
2231 | ||
fc76e730 RS |
2232 | /* Extract the value of OPERAND from INSN. */ |
2233 | ||
2234 | static inline unsigned | |
2235 | insn_extract_operand (const struct mips_cl_insn *insn, | |
2236 | const struct mips_operand *operand) | |
2237 | { | |
2238 | return mips_extract_operand (operand, insn->insn_opcode); | |
2239 | } | |
2240 | ||
df58fc94 | 2241 | /* Record the current MIPS16/microMIPS mode in now_seg. */ |
742a56fe RS |
2242 | |
2243 | static void | |
df58fc94 | 2244 | mips_record_compressed_mode (void) |
742a56fe RS |
2245 | { |
2246 | segment_info_type *si; | |
2247 | ||
2248 | si = seg_info (now_seg); | |
2249 | if (si->tc_segment_info_data.mips16 != mips_opts.mips16) | |
2250 | si->tc_segment_info_data.mips16 = mips_opts.mips16; | |
df58fc94 RS |
2251 | if (si->tc_segment_info_data.micromips != mips_opts.micromips) |
2252 | si->tc_segment_info_data.micromips = mips_opts.micromips; | |
742a56fe RS |
2253 | } |
2254 | ||
4d68580a RS |
2255 | /* Read a standard MIPS instruction from BUF. */ |
2256 | ||
2257 | static unsigned long | |
2258 | read_insn (char *buf) | |
2259 | { | |
2260 | if (target_big_endian) | |
2261 | return bfd_getb32 ((bfd_byte *) buf); | |
2262 | else | |
2263 | return bfd_getl32 ((bfd_byte *) buf); | |
2264 | } | |
2265 | ||
2266 | /* Write standard MIPS instruction INSN to BUF. Return a pointer to | |
2267 | the next byte. */ | |
2268 | ||
2269 | static char * | |
2270 | write_insn (char *buf, unsigned int insn) | |
2271 | { | |
2272 | md_number_to_chars (buf, insn, 4); | |
2273 | return buf + 4; | |
2274 | } | |
2275 | ||
2276 | /* Read a microMIPS or MIPS16 opcode from BUF, given that it | |
2277 | has length LENGTH. */ | |
2278 | ||
2279 | static unsigned long | |
2280 | read_compressed_insn (char *buf, unsigned int length) | |
2281 | { | |
2282 | unsigned long insn; | |
2283 | unsigned int i; | |
2284 | ||
2285 | insn = 0; | |
2286 | for (i = 0; i < length; i += 2) | |
2287 | { | |
2288 | insn <<= 16; | |
2289 | if (target_big_endian) | |
2290 | insn |= bfd_getb16 ((char *) buf); | |
2291 | else | |
2292 | insn |= bfd_getl16 ((char *) buf); | |
2293 | buf += 2; | |
2294 | } | |
2295 | return insn; | |
2296 | } | |
2297 | ||
5c04167a RS |
2298 | /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the |
2299 | instruction is LENGTH bytes long. Return a pointer to the next byte. */ | |
2300 | ||
2301 | static char * | |
2302 | write_compressed_insn (char *buf, unsigned int insn, unsigned int length) | |
2303 | { | |
2304 | unsigned int i; | |
2305 | ||
2306 | for (i = 0; i < length; i += 2) | |
2307 | md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2); | |
2308 | return buf + length; | |
2309 | } | |
2310 | ||
1e915849 RS |
2311 | /* Install INSN at the location specified by its "frag" and "where" fields. */ |
2312 | ||
2313 | static void | |
2314 | install_insn (const struct mips_cl_insn *insn) | |
2315 | { | |
2316 | char *f = insn->frag->fr_literal + insn->where; | |
5c04167a RS |
2317 | if (HAVE_CODE_COMPRESSION) |
2318 | write_compressed_insn (f, insn->insn_opcode, insn_length (insn)); | |
1e915849 | 2319 | else |
4d68580a | 2320 | write_insn (f, insn->insn_opcode); |
df58fc94 | 2321 | mips_record_compressed_mode (); |
1e915849 RS |
2322 | } |
2323 | ||
2324 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
2325 | and install the opcode in the new location. */ | |
2326 | ||
2327 | static void | |
2328 | move_insn (struct mips_cl_insn *insn, fragS *frag, long where) | |
2329 | { | |
2330 | size_t i; | |
2331 | ||
2332 | insn->frag = frag; | |
2333 | insn->where = where; | |
2334 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
2335 | if (insn->fixp[i] != NULL) | |
2336 | { | |
2337 | insn->fixp[i]->fx_frag = frag; | |
2338 | insn->fixp[i]->fx_where = where; | |
2339 | } | |
2340 | install_insn (insn); | |
2341 | } | |
2342 | ||
2343 | /* Add INSN to the end of the output. */ | |
2344 | ||
2345 | static void | |
2346 | add_fixed_insn (struct mips_cl_insn *insn) | |
2347 | { | |
2348 | char *f = frag_more (insn_length (insn)); | |
2349 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
2350 | } | |
2351 | ||
2352 | /* Start a variant frag and move INSN to the start of the variant part, | |
2353 | marking it as fixed. The other arguments are as for frag_var. */ | |
2354 | ||
2355 | static void | |
2356 | add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, | |
2357 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
2358 | { | |
2359 | frag_grow (max_chars); | |
2360 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
2361 | insn->fixed_p = 1; | |
2362 | frag_var (rs_machine_dependent, max_chars, var, | |
2363 | subtype, symbol, offset, NULL); | |
2364 | } | |
2365 | ||
2366 | /* Insert N copies of INSN into the history buffer, starting at | |
2367 | position FIRST. Neither FIRST nor N need to be clipped. */ | |
2368 | ||
2369 | static void | |
2370 | insert_into_history (unsigned int first, unsigned int n, | |
2371 | const struct mips_cl_insn *insn) | |
2372 | { | |
2373 | if (mips_relax.sequence != 2) | |
2374 | { | |
2375 | unsigned int i; | |
2376 | ||
2377 | for (i = ARRAY_SIZE (history); i-- > first;) | |
2378 | if (i >= first + n) | |
2379 | history[i] = history[i - n]; | |
2380 | else | |
2381 | history[i] = *insn; | |
2382 | } | |
2383 | } | |
2384 | ||
e3de51ce RS |
2385 | /* Clear the error in insn_error. */ |
2386 | ||
2387 | static void | |
2388 | clear_insn_error (void) | |
2389 | { | |
2390 | memset (&insn_error, 0, sizeof (insn_error)); | |
2391 | } | |
2392 | ||
2393 | /* Possibly record error message MSG for the current instruction. | |
2394 | If the error is about a particular argument, ARGNUM is the 1-based | |
2395 | number of that argument, otherwise it is 0. FORMAT is the format | |
2396 | of MSG. Return true if MSG was used, false if the current message | |
2397 | was kept. */ | |
2398 | ||
2399 | static bfd_boolean | |
2400 | set_insn_error_format (int argnum, enum mips_insn_error_format format, | |
2401 | const char *msg) | |
2402 | { | |
2403 | if (argnum == 0) | |
2404 | { | |
2405 | /* Give priority to errors against specific arguments, and to | |
2406 | the first whole-instruction message. */ | |
2407 | if (insn_error.msg) | |
2408 | return FALSE; | |
2409 | } | |
2410 | else | |
2411 | { | |
2412 | /* Keep insn_error if it is against a later argument. */ | |
2413 | if (argnum < insn_error.min_argnum) | |
2414 | return FALSE; | |
2415 | ||
2416 | /* If both errors are against the same argument but are different, | |
2417 | give up on reporting a specific error for this argument. | |
2418 | See the comment about mips_insn_error for details. */ | |
2419 | if (argnum == insn_error.min_argnum | |
2420 | && insn_error.msg | |
2421 | && strcmp (insn_error.msg, msg) != 0) | |
2422 | { | |
2423 | insn_error.msg = 0; | |
2424 | insn_error.min_argnum += 1; | |
2425 | return FALSE; | |
2426 | } | |
2427 | } | |
2428 | insn_error.min_argnum = argnum; | |
2429 | insn_error.format = format; | |
2430 | insn_error.msg = msg; | |
2431 | return TRUE; | |
2432 | } | |
2433 | ||
2434 | /* Record an instruction error with no % format fields. ARGNUM and MSG are | |
2435 | as for set_insn_error_format. */ | |
2436 | ||
2437 | static void | |
2438 | set_insn_error (int argnum, const char *msg) | |
2439 | { | |
2440 | set_insn_error_format (argnum, ERR_FMT_PLAIN, msg); | |
2441 | } | |
2442 | ||
2443 | /* Record an instruction error with one %d field I. ARGNUM and MSG are | |
2444 | as for set_insn_error_format. */ | |
2445 | ||
2446 | static void | |
2447 | set_insn_error_i (int argnum, const char *msg, int i) | |
2448 | { | |
2449 | if (set_insn_error_format (argnum, ERR_FMT_I, msg)) | |
2450 | insn_error.u.i = i; | |
2451 | } | |
2452 | ||
2453 | /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG | |
2454 | are as for set_insn_error_format. */ | |
2455 | ||
2456 | static void | |
2457 | set_insn_error_ss (int argnum, const char *msg, const char *s1, const char *s2) | |
2458 | { | |
2459 | if (set_insn_error_format (argnum, ERR_FMT_SS, msg)) | |
2460 | { | |
2461 | insn_error.u.ss[0] = s1; | |
2462 | insn_error.u.ss[1] = s2; | |
2463 | } | |
2464 | } | |
2465 | ||
2466 | /* Report the error in insn_error, which is against assembly code STR. */ | |
2467 | ||
2468 | static void | |
2469 | report_insn_error (const char *str) | |
2470 | { | |
e1fa0163 | 2471 | const char *msg = concat (insn_error.msg, " `%s'", NULL); |
e3de51ce | 2472 | |
e3de51ce RS |
2473 | switch (insn_error.format) |
2474 | { | |
2475 | case ERR_FMT_PLAIN: | |
2476 | as_bad (msg, str); | |
2477 | break; | |
2478 | ||
2479 | case ERR_FMT_I: | |
2480 | as_bad (msg, insn_error.u.i, str); | |
2481 | break; | |
2482 | ||
2483 | case ERR_FMT_SS: | |
2484 | as_bad (msg, insn_error.u.ss[0], insn_error.u.ss[1], str); | |
2485 | break; | |
2486 | } | |
e1fa0163 NC |
2487 | |
2488 | free ((char *) msg); | |
e3de51ce RS |
2489 | } |
2490 | ||
71400594 RS |
2491 | /* Initialize vr4120_conflicts. There is a bit of duplication here: |
2492 | the idea is to make it obvious at a glance that each errata is | |
2493 | included. */ | |
2494 | ||
2495 | static void | |
2496 | init_vr4120_conflicts (void) | |
2497 | { | |
2498 | #define CONFLICT(FIRST, SECOND) \ | |
2499 | vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND | |
2500 | ||
2501 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
2502 | CONFLICT (MACC, DIV); | |
2503 | CONFLICT (DMACC, DIV); | |
2504 | ||
2505 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ | |
2506 | CONFLICT (DMULT, DMULT); | |
2507 | CONFLICT (DMULT, DMACC); | |
2508 | CONFLICT (DMACC, DMULT); | |
2509 | CONFLICT (DMACC, DMACC); | |
2510 | ||
2511 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
2512 | CONFLICT (MACC, MTHILO); | |
2513 | CONFLICT (DMACC, MTHILO); | |
2514 | ||
2515 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU | |
2516 | instruction is executed immediately after a MACC or DMACC | |
2517 | instruction, the result of [either instruction] is incorrect." */ | |
2518 | CONFLICT (MACC, MULT); | |
2519 | CONFLICT (MACC, DMULT); | |
2520 | CONFLICT (DMACC, MULT); | |
2521 | CONFLICT (DMACC, DMULT); | |
2522 | ||
2523 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
2524 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
2525 | DDIV or DDIVU instruction, the result of the MACC or | |
2526 | DMACC instruction is incorrect.". */ | |
2527 | CONFLICT (DMULT, MACC); | |
2528 | CONFLICT (DMULT, DMACC); | |
2529 | CONFLICT (DIV, MACC); | |
2530 | CONFLICT (DIV, DMACC); | |
2531 | ||
2532 | #undef CONFLICT | |
2533 | } | |
2534 | ||
707bfff6 TS |
2535 | struct regname { |
2536 | const char *name; | |
2537 | unsigned int num; | |
2538 | }; | |
2539 | ||
14daeee3 | 2540 | #define RNUM_MASK 0x00000ff |
56d438b1 | 2541 | #define RTYPE_MASK 0x0ffff00 |
14daeee3 RS |
2542 | #define RTYPE_NUM 0x0000100 |
2543 | #define RTYPE_FPU 0x0000200 | |
2544 | #define RTYPE_FCC 0x0000400 | |
2545 | #define RTYPE_VEC 0x0000800 | |
2546 | #define RTYPE_GP 0x0001000 | |
2547 | #define RTYPE_CP0 0x0002000 | |
2548 | #define RTYPE_PC 0x0004000 | |
2549 | #define RTYPE_ACC 0x0008000 | |
2550 | #define RTYPE_CCC 0x0010000 | |
2551 | #define RTYPE_VI 0x0020000 | |
2552 | #define RTYPE_VF 0x0040000 | |
2553 | #define RTYPE_R5900_I 0x0080000 | |
2554 | #define RTYPE_R5900_Q 0x0100000 | |
2555 | #define RTYPE_R5900_R 0x0200000 | |
2556 | #define RTYPE_R5900_ACC 0x0400000 | |
56d438b1 | 2557 | #define RTYPE_MSA 0x0800000 |
14daeee3 | 2558 | #define RWARN 0x8000000 |
707bfff6 TS |
2559 | |
2560 | #define GENERIC_REGISTER_NUMBERS \ | |
2561 | {"$0", RTYPE_NUM | 0}, \ | |
2562 | {"$1", RTYPE_NUM | 1}, \ | |
2563 | {"$2", RTYPE_NUM | 2}, \ | |
2564 | {"$3", RTYPE_NUM | 3}, \ | |
2565 | {"$4", RTYPE_NUM | 4}, \ | |
2566 | {"$5", RTYPE_NUM | 5}, \ | |
2567 | {"$6", RTYPE_NUM | 6}, \ | |
2568 | {"$7", RTYPE_NUM | 7}, \ | |
2569 | {"$8", RTYPE_NUM | 8}, \ | |
2570 | {"$9", RTYPE_NUM | 9}, \ | |
2571 | {"$10", RTYPE_NUM | 10}, \ | |
2572 | {"$11", RTYPE_NUM | 11}, \ | |
2573 | {"$12", RTYPE_NUM | 12}, \ | |
2574 | {"$13", RTYPE_NUM | 13}, \ | |
2575 | {"$14", RTYPE_NUM | 14}, \ | |
2576 | {"$15", RTYPE_NUM | 15}, \ | |
2577 | {"$16", RTYPE_NUM | 16}, \ | |
2578 | {"$17", RTYPE_NUM | 17}, \ | |
2579 | {"$18", RTYPE_NUM | 18}, \ | |
2580 | {"$19", RTYPE_NUM | 19}, \ | |
2581 | {"$20", RTYPE_NUM | 20}, \ | |
2582 | {"$21", RTYPE_NUM | 21}, \ | |
2583 | {"$22", RTYPE_NUM | 22}, \ | |
2584 | {"$23", RTYPE_NUM | 23}, \ | |
2585 | {"$24", RTYPE_NUM | 24}, \ | |
2586 | {"$25", RTYPE_NUM | 25}, \ | |
2587 | {"$26", RTYPE_NUM | 26}, \ | |
2588 | {"$27", RTYPE_NUM | 27}, \ | |
2589 | {"$28", RTYPE_NUM | 28}, \ | |
2590 | {"$29", RTYPE_NUM | 29}, \ | |
2591 | {"$30", RTYPE_NUM | 30}, \ | |
3739860c | 2592 | {"$31", RTYPE_NUM | 31} |
707bfff6 TS |
2593 | |
2594 | #define FPU_REGISTER_NAMES \ | |
2595 | {"$f0", RTYPE_FPU | 0}, \ | |
2596 | {"$f1", RTYPE_FPU | 1}, \ | |
2597 | {"$f2", RTYPE_FPU | 2}, \ | |
2598 | {"$f3", RTYPE_FPU | 3}, \ | |
2599 | {"$f4", RTYPE_FPU | 4}, \ | |
2600 | {"$f5", RTYPE_FPU | 5}, \ | |
2601 | {"$f6", RTYPE_FPU | 6}, \ | |
2602 | {"$f7", RTYPE_FPU | 7}, \ | |
2603 | {"$f8", RTYPE_FPU | 8}, \ | |
2604 | {"$f9", RTYPE_FPU | 9}, \ | |
2605 | {"$f10", RTYPE_FPU | 10}, \ | |
2606 | {"$f11", RTYPE_FPU | 11}, \ | |
2607 | {"$f12", RTYPE_FPU | 12}, \ | |
2608 | {"$f13", RTYPE_FPU | 13}, \ | |
2609 | {"$f14", RTYPE_FPU | 14}, \ | |
2610 | {"$f15", RTYPE_FPU | 15}, \ | |
2611 | {"$f16", RTYPE_FPU | 16}, \ | |
2612 | {"$f17", RTYPE_FPU | 17}, \ | |
2613 | {"$f18", RTYPE_FPU | 18}, \ | |
2614 | {"$f19", RTYPE_FPU | 19}, \ | |
2615 | {"$f20", RTYPE_FPU | 20}, \ | |
2616 | {"$f21", RTYPE_FPU | 21}, \ | |
2617 | {"$f22", RTYPE_FPU | 22}, \ | |
2618 | {"$f23", RTYPE_FPU | 23}, \ | |
2619 | {"$f24", RTYPE_FPU | 24}, \ | |
2620 | {"$f25", RTYPE_FPU | 25}, \ | |
2621 | {"$f26", RTYPE_FPU | 26}, \ | |
2622 | {"$f27", RTYPE_FPU | 27}, \ | |
2623 | {"$f28", RTYPE_FPU | 28}, \ | |
2624 | {"$f29", RTYPE_FPU | 29}, \ | |
2625 | {"$f30", RTYPE_FPU | 30}, \ | |
2626 | {"$f31", RTYPE_FPU | 31} | |
2627 | ||
2628 | #define FPU_CONDITION_CODE_NAMES \ | |
2629 | {"$fcc0", RTYPE_FCC | 0}, \ | |
2630 | {"$fcc1", RTYPE_FCC | 1}, \ | |
2631 | {"$fcc2", RTYPE_FCC | 2}, \ | |
2632 | {"$fcc3", RTYPE_FCC | 3}, \ | |
2633 | {"$fcc4", RTYPE_FCC | 4}, \ | |
2634 | {"$fcc5", RTYPE_FCC | 5}, \ | |
2635 | {"$fcc6", RTYPE_FCC | 6}, \ | |
2636 | {"$fcc7", RTYPE_FCC | 7} | |
2637 | ||
2638 | #define COPROC_CONDITION_CODE_NAMES \ | |
2639 | {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \ | |
2640 | {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \ | |
2641 | {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \ | |
2642 | {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \ | |
2643 | {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \ | |
2644 | {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \ | |
2645 | {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \ | |
2646 | {"$cc7", RTYPE_FCC | RTYPE_CCC | 7} | |
2647 | ||
2648 | #define N32N64_SYMBOLIC_REGISTER_NAMES \ | |
2649 | {"$a4", RTYPE_GP | 8}, \ | |
2650 | {"$a5", RTYPE_GP | 9}, \ | |
2651 | {"$a6", RTYPE_GP | 10}, \ | |
2652 | {"$a7", RTYPE_GP | 11}, \ | |
2653 | {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \ | |
2654 | {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \ | |
2655 | {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \ | |
2656 | {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \ | |
2657 | {"$t0", RTYPE_GP | 12}, \ | |
2658 | {"$t1", RTYPE_GP | 13}, \ | |
2659 | {"$t2", RTYPE_GP | 14}, \ | |
2660 | {"$t3", RTYPE_GP | 15} | |
2661 | ||
2662 | #define O32_SYMBOLIC_REGISTER_NAMES \ | |
2663 | {"$t0", RTYPE_GP | 8}, \ | |
2664 | {"$t1", RTYPE_GP | 9}, \ | |
2665 | {"$t2", RTYPE_GP | 10}, \ | |
2666 | {"$t3", RTYPE_GP | 11}, \ | |
2667 | {"$t4", RTYPE_GP | 12}, \ | |
2668 | {"$t5", RTYPE_GP | 13}, \ | |
2669 | {"$t6", RTYPE_GP | 14}, \ | |
2670 | {"$t7", RTYPE_GP | 15}, \ | |
2671 | {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \ | |
2672 | {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \ | |
2673 | {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \ | |
3739860c | 2674 | {"$ta3", RTYPE_GP | 15} /* alias for $t7 */ |
707bfff6 TS |
2675 | |
2676 | /* Remaining symbolic register names */ | |
2677 | #define SYMBOLIC_REGISTER_NAMES \ | |
2678 | {"$zero", RTYPE_GP | 0}, \ | |
2679 | {"$at", RTYPE_GP | 1}, \ | |
2680 | {"$AT", RTYPE_GP | 1}, \ | |
2681 | {"$v0", RTYPE_GP | 2}, \ | |
2682 | {"$v1", RTYPE_GP | 3}, \ | |
2683 | {"$a0", RTYPE_GP | 4}, \ | |
2684 | {"$a1", RTYPE_GP | 5}, \ | |
2685 | {"$a2", RTYPE_GP | 6}, \ | |
2686 | {"$a3", RTYPE_GP | 7}, \ | |
2687 | {"$s0", RTYPE_GP | 16}, \ | |
2688 | {"$s1", RTYPE_GP | 17}, \ | |
2689 | {"$s2", RTYPE_GP | 18}, \ | |
2690 | {"$s3", RTYPE_GP | 19}, \ | |
2691 | {"$s4", RTYPE_GP | 20}, \ | |
2692 | {"$s5", RTYPE_GP | 21}, \ | |
2693 | {"$s6", RTYPE_GP | 22}, \ | |
2694 | {"$s7", RTYPE_GP | 23}, \ | |
2695 | {"$t8", RTYPE_GP | 24}, \ | |
2696 | {"$t9", RTYPE_GP | 25}, \ | |
2697 | {"$k0", RTYPE_GP | 26}, \ | |
2698 | {"$kt0", RTYPE_GP | 26}, \ | |
2699 | {"$k1", RTYPE_GP | 27}, \ | |
2700 | {"$kt1", RTYPE_GP | 27}, \ | |
2701 | {"$gp", RTYPE_GP | 28}, \ | |
2702 | {"$sp", RTYPE_GP | 29}, \ | |
2703 | {"$s8", RTYPE_GP | 30}, \ | |
2704 | {"$fp", RTYPE_GP | 30}, \ | |
2705 | {"$ra", RTYPE_GP | 31} | |
2706 | ||
2707 | #define MIPS16_SPECIAL_REGISTER_NAMES \ | |
2708 | {"$pc", RTYPE_PC | 0} | |
2709 | ||
2710 | #define MDMX_VECTOR_REGISTER_NAMES \ | |
2711 | /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \ | |
2712 | /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \ | |
2713 | {"$v2", RTYPE_VEC | 2}, \ | |
2714 | {"$v3", RTYPE_VEC | 3}, \ | |
2715 | {"$v4", RTYPE_VEC | 4}, \ | |
2716 | {"$v5", RTYPE_VEC | 5}, \ | |
2717 | {"$v6", RTYPE_VEC | 6}, \ | |
2718 | {"$v7", RTYPE_VEC | 7}, \ | |
2719 | {"$v8", RTYPE_VEC | 8}, \ | |
2720 | {"$v9", RTYPE_VEC | 9}, \ | |
2721 | {"$v10", RTYPE_VEC | 10}, \ | |
2722 | {"$v11", RTYPE_VEC | 11}, \ | |
2723 | {"$v12", RTYPE_VEC | 12}, \ | |
2724 | {"$v13", RTYPE_VEC | 13}, \ | |
2725 | {"$v14", RTYPE_VEC | 14}, \ | |
2726 | {"$v15", RTYPE_VEC | 15}, \ | |
2727 | {"$v16", RTYPE_VEC | 16}, \ | |
2728 | {"$v17", RTYPE_VEC | 17}, \ | |
2729 | {"$v18", RTYPE_VEC | 18}, \ | |
2730 | {"$v19", RTYPE_VEC | 19}, \ | |
2731 | {"$v20", RTYPE_VEC | 20}, \ | |
2732 | {"$v21", RTYPE_VEC | 21}, \ | |
2733 | {"$v22", RTYPE_VEC | 22}, \ | |
2734 | {"$v23", RTYPE_VEC | 23}, \ | |
2735 | {"$v24", RTYPE_VEC | 24}, \ | |
2736 | {"$v25", RTYPE_VEC | 25}, \ | |
2737 | {"$v26", RTYPE_VEC | 26}, \ | |
2738 | {"$v27", RTYPE_VEC | 27}, \ | |
2739 | {"$v28", RTYPE_VEC | 28}, \ | |
2740 | {"$v29", RTYPE_VEC | 29}, \ | |
2741 | {"$v30", RTYPE_VEC | 30}, \ | |
2742 | {"$v31", RTYPE_VEC | 31} | |
2743 | ||
14daeee3 RS |
2744 | #define R5900_I_NAMES \ |
2745 | {"$I", RTYPE_R5900_I | 0} | |
2746 | ||
2747 | #define R5900_Q_NAMES \ | |
2748 | {"$Q", RTYPE_R5900_Q | 0} | |
2749 | ||
2750 | #define R5900_R_NAMES \ | |
2751 | {"$R", RTYPE_R5900_R | 0} | |
2752 | ||
2753 | #define R5900_ACC_NAMES \ | |
2754 | {"$ACC", RTYPE_R5900_ACC | 0 } | |
2755 | ||
707bfff6 TS |
2756 | #define MIPS_DSP_ACCUMULATOR_NAMES \ |
2757 | {"$ac0", RTYPE_ACC | 0}, \ | |
2758 | {"$ac1", RTYPE_ACC | 1}, \ | |
2759 | {"$ac2", RTYPE_ACC | 2}, \ | |
2760 | {"$ac3", RTYPE_ACC | 3} | |
2761 | ||
2762 | static const struct regname reg_names[] = { | |
2763 | GENERIC_REGISTER_NUMBERS, | |
2764 | FPU_REGISTER_NAMES, | |
2765 | FPU_CONDITION_CODE_NAMES, | |
2766 | COPROC_CONDITION_CODE_NAMES, | |
2767 | ||
2768 | /* The $txx registers depends on the abi, | |
2769 | these will be added later into the symbol table from | |
3739860c | 2770 | one of the tables below once mips_abi is set after |
707bfff6 TS |
2771 | parsing of arguments from the command line. */ |
2772 | SYMBOLIC_REGISTER_NAMES, | |
2773 | ||
2774 | MIPS16_SPECIAL_REGISTER_NAMES, | |
2775 | MDMX_VECTOR_REGISTER_NAMES, | |
14daeee3 RS |
2776 | R5900_I_NAMES, |
2777 | R5900_Q_NAMES, | |
2778 | R5900_R_NAMES, | |
2779 | R5900_ACC_NAMES, | |
707bfff6 TS |
2780 | MIPS_DSP_ACCUMULATOR_NAMES, |
2781 | {0, 0} | |
2782 | }; | |
2783 | ||
2784 | static const struct regname reg_names_o32[] = { | |
2785 | O32_SYMBOLIC_REGISTER_NAMES, | |
2786 | {0, 0} | |
2787 | }; | |
2788 | ||
2789 | static const struct regname reg_names_n32n64[] = { | |
2790 | N32N64_SYMBOLIC_REGISTER_NAMES, | |
2791 | {0, 0} | |
2792 | }; | |
2793 | ||
a92713e6 RS |
2794 | /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be |
2795 | interpreted as vector registers 0 and 1. If SYMVAL is the value of one | |
2796 | of these register symbols, return the associated vector register, | |
2797 | otherwise return SYMVAL itself. */ | |
df58fc94 | 2798 | |
a92713e6 RS |
2799 | static unsigned int |
2800 | mips_prefer_vec_regno (unsigned int symval) | |
707bfff6 | 2801 | { |
a92713e6 RS |
2802 | if ((symval & -2) == (RTYPE_GP | 2)) |
2803 | return RTYPE_VEC | (symval & 1); | |
2804 | return symval; | |
2805 | } | |
2806 | ||
14daeee3 RS |
2807 | /* Return true if string [S, E) is a valid register name, storing its |
2808 | symbol value in *SYMVAL_PTR if so. */ | |
a92713e6 RS |
2809 | |
2810 | static bfd_boolean | |
14daeee3 | 2811 | mips_parse_register_1 (char *s, char *e, unsigned int *symval_ptr) |
a92713e6 | 2812 | { |
707bfff6 | 2813 | char save_c; |
14daeee3 | 2814 | symbolS *symbol; |
707bfff6 TS |
2815 | |
2816 | /* Terminate name. */ | |
2817 | save_c = *e; | |
2818 | *e = '\0'; | |
2819 | ||
a92713e6 RS |
2820 | /* Look up the name. */ |
2821 | symbol = symbol_find (s); | |
2822 | *e = save_c; | |
2823 | ||
2824 | if (!symbol || S_GET_SEGMENT (symbol) != reg_section) | |
2825 | return FALSE; | |
2826 | ||
14daeee3 RS |
2827 | *symval_ptr = S_GET_VALUE (symbol); |
2828 | return TRUE; | |
2829 | } | |
2830 | ||
2831 | /* Return true if the string at *SPTR is a valid register name. Allow it | |
2832 | to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR | |
2833 | is nonnull. | |
2834 | ||
2835 | When returning true, move *SPTR past the register, store the | |
2836 | register's symbol value in *SYMVAL_PTR and the channel mask in | |
2837 | *CHANNELS_PTR (if nonnull). The symbol value includes the register | |
2838 | number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask | |
2839 | is a 4-bit value of the form XYZW and is 0 if no suffix was given. */ | |
2840 | ||
2841 | static bfd_boolean | |
2842 | mips_parse_register (char **sptr, unsigned int *symval_ptr, | |
2843 | unsigned int *channels_ptr) | |
2844 | { | |
2845 | char *s, *e, *m; | |
2846 | const char *q; | |
2847 | unsigned int channels, symval, bit; | |
2848 | ||
2849 | /* Find end of name. */ | |
2850 | s = e = *sptr; | |
2851 | if (is_name_beginner (*e)) | |
2852 | ++e; | |
2853 | while (is_part_of_name (*e)) | |
2854 | ++e; | |
2855 | ||
2856 | channels = 0; | |
2857 | if (!mips_parse_register_1 (s, e, &symval)) | |
2858 | { | |
2859 | if (!channels_ptr) | |
2860 | return FALSE; | |
2861 | ||
2862 | /* Eat characters from the end of the string that are valid | |
2863 | channel suffixes. The preceding register must be $ACC or | |
2864 | end with a digit, so there is no ambiguity. */ | |
2865 | bit = 1; | |
2866 | m = e; | |
2867 | for (q = "wzyx"; *q; q++, bit <<= 1) | |
2868 | if (m > s && m[-1] == *q) | |
2869 | { | |
2870 | --m; | |
2871 | channels |= bit; | |
2872 | } | |
2873 | ||
2874 | if (channels == 0 | |
2875 | || !mips_parse_register_1 (s, m, &symval) | |
2876 | || (symval & (RTYPE_VI | RTYPE_VF | RTYPE_R5900_ACC)) == 0) | |
2877 | return FALSE; | |
2878 | } | |
2879 | ||
a92713e6 | 2880 | *sptr = e; |
14daeee3 RS |
2881 | *symval_ptr = symval; |
2882 | if (channels_ptr) | |
2883 | *channels_ptr = channels; | |
a92713e6 RS |
2884 | return TRUE; |
2885 | } | |
2886 | ||
2887 | /* Check if SPTR points at a valid register specifier according to TYPES. | |
2888 | If so, then return 1, advance S to consume the specifier and store | |
2889 | the register's number in REGNOP, otherwise return 0. */ | |
2890 | ||
2891 | static int | |
2892 | reg_lookup (char **s, unsigned int types, unsigned int *regnop) | |
2893 | { | |
2894 | unsigned int regno; | |
2895 | ||
14daeee3 | 2896 | if (mips_parse_register (s, ®no, NULL)) |
707bfff6 | 2897 | { |
a92713e6 RS |
2898 | if (types & RTYPE_VEC) |
2899 | regno = mips_prefer_vec_regno (regno); | |
2900 | if (regno & types) | |
2901 | regno &= RNUM_MASK; | |
2902 | else | |
2903 | regno = ~0; | |
707bfff6 | 2904 | } |
a92713e6 | 2905 | else |
707bfff6 | 2906 | { |
a92713e6 | 2907 | if (types & RWARN) |
1661c76c | 2908 | as_warn (_("unrecognized register name `%s'"), *s); |
a92713e6 | 2909 | regno = ~0; |
707bfff6 | 2910 | } |
707bfff6 | 2911 | if (regnop) |
a92713e6 RS |
2912 | *regnop = regno; |
2913 | return regno <= RNUM_MASK; | |
707bfff6 TS |
2914 | } |
2915 | ||
14daeee3 RS |
2916 | /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated |
2917 | mask in *CHANNELS. Return a pointer to the first unconsumed character. */ | |
2918 | ||
2919 | static char * | |
2920 | mips_parse_vu0_channels (char *s, unsigned int *channels) | |
2921 | { | |
2922 | unsigned int i; | |
2923 | ||
2924 | *channels = 0; | |
2925 | for (i = 0; i < 4; i++) | |
2926 | if (*s == "xyzw"[i]) | |
2927 | { | |
2928 | *channels |= 1 << (3 - i); | |
2929 | ++s; | |
2930 | } | |
2931 | return s; | |
2932 | } | |
2933 | ||
a92713e6 RS |
2934 | /* Token types for parsed operand lists. */ |
2935 | enum mips_operand_token_type { | |
2936 | /* A plain register, e.g. $f2. */ | |
2937 | OT_REG, | |
df58fc94 | 2938 | |
14daeee3 RS |
2939 | /* A 4-bit XYZW channel mask. */ |
2940 | OT_CHANNELS, | |
2941 | ||
56d438b1 CF |
2942 | /* A constant vector index, e.g. [1]. */ |
2943 | OT_INTEGER_INDEX, | |
2944 | ||
2945 | /* A register vector index, e.g. [$2]. */ | |
2946 | OT_REG_INDEX, | |
df58fc94 | 2947 | |
a92713e6 RS |
2948 | /* A continuous range of registers, e.g. $s0-$s4. */ |
2949 | OT_REG_RANGE, | |
2950 | ||
2951 | /* A (possibly relocated) expression. */ | |
2952 | OT_INTEGER, | |
2953 | ||
2954 | /* A floating-point value. */ | |
2955 | OT_FLOAT, | |
2956 | ||
2957 | /* A single character. This can be '(', ')' or ',', but '(' only appears | |
2958 | before OT_REGs. */ | |
2959 | OT_CHAR, | |
2960 | ||
14daeee3 RS |
2961 | /* A doubled character, either "--" or "++". */ |
2962 | OT_DOUBLE_CHAR, | |
2963 | ||
a92713e6 RS |
2964 | /* The end of the operand list. */ |
2965 | OT_END | |
2966 | }; | |
2967 | ||
2968 | /* A parsed operand token. */ | |
2969 | struct mips_operand_token | |
2970 | { | |
2971 | /* The type of token. */ | |
2972 | enum mips_operand_token_type type; | |
2973 | union | |
2974 | { | |
56d438b1 | 2975 | /* The register symbol value for an OT_REG or OT_REG_INDEX. */ |
a92713e6 RS |
2976 | unsigned int regno; |
2977 | ||
14daeee3 RS |
2978 | /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */ |
2979 | unsigned int channels; | |
2980 | ||
56d438b1 CF |
2981 | /* The integer value of an OT_INTEGER_INDEX. */ |
2982 | addressT index; | |
a92713e6 RS |
2983 | |
2984 | /* The two register symbol values involved in an OT_REG_RANGE. */ | |
2985 | struct { | |
2986 | unsigned int regno1; | |
2987 | unsigned int regno2; | |
2988 | } reg_range; | |
2989 | ||
2990 | /* The value of an OT_INTEGER. The value is represented as an | |
2991 | expression and the relocation operators that were applied to | |
2992 | that expression. The reloc entries are BFD_RELOC_UNUSED if no | |
2993 | relocation operators were used. */ | |
2994 | struct { | |
2995 | expressionS value; | |
2996 | bfd_reloc_code_real_type relocs[3]; | |
2997 | } integer; | |
2998 | ||
2999 | /* The binary data for an OT_FLOAT constant, and the number of bytes | |
3000 | in the constant. */ | |
3001 | struct { | |
3002 | unsigned char data[8]; | |
3003 | int length; | |
3004 | } flt; | |
3005 | ||
14daeee3 | 3006 | /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */ |
a92713e6 RS |
3007 | char ch; |
3008 | } u; | |
3009 | }; | |
3010 | ||
3011 | /* An obstack used to construct lists of mips_operand_tokens. */ | |
3012 | static struct obstack mips_operand_tokens; | |
3013 | ||
3014 | /* Give TOKEN type TYPE and add it to mips_operand_tokens. */ | |
3015 | ||
3016 | static void | |
3017 | mips_add_token (struct mips_operand_token *token, | |
3018 | enum mips_operand_token_type type) | |
3019 | { | |
3020 | token->type = type; | |
3021 | obstack_grow (&mips_operand_tokens, token, sizeof (*token)); | |
3022 | } | |
3023 | ||
3024 | /* Check whether S is '(' followed by a register name. Add OT_CHAR | |
3025 | and OT_REG tokens for them if so, and return a pointer to the first | |
3026 | unconsumed character. Return null otherwise. */ | |
3027 | ||
3028 | static char * | |
3029 | mips_parse_base_start (char *s) | |
3030 | { | |
3031 | struct mips_operand_token token; | |
14daeee3 RS |
3032 | unsigned int regno, channels; |
3033 | bfd_boolean decrement_p; | |
df58fc94 | 3034 | |
a92713e6 RS |
3035 | if (*s != '(') |
3036 | return 0; | |
3037 | ||
3038 | ++s; | |
3039 | SKIP_SPACE_TABS (s); | |
14daeee3 RS |
3040 | |
3041 | /* Only match "--" as part of a base expression. In other contexts "--X" | |
3042 | is a double negative. */ | |
3043 | decrement_p = (s[0] == '-' && s[1] == '-'); | |
3044 | if (decrement_p) | |
3045 | { | |
3046 | s += 2; | |
3047 | SKIP_SPACE_TABS (s); | |
3048 | } | |
3049 | ||
3050 | /* Allow a channel specifier because that leads to better error messages | |
3051 | than treating something like "$vf0x++" as an expression. */ | |
3052 | if (!mips_parse_register (&s, ®no, &channels)) | |
a92713e6 RS |
3053 | return 0; |
3054 | ||
3055 | token.u.ch = '('; | |
3056 | mips_add_token (&token, OT_CHAR); | |
3057 | ||
14daeee3 RS |
3058 | if (decrement_p) |
3059 | { | |
3060 | token.u.ch = '-'; | |
3061 | mips_add_token (&token, OT_DOUBLE_CHAR); | |
3062 | } | |
3063 | ||
a92713e6 RS |
3064 | token.u.regno = regno; |
3065 | mips_add_token (&token, OT_REG); | |
3066 | ||
14daeee3 RS |
3067 | if (channels) |
3068 | { | |
3069 | token.u.channels = channels; | |
3070 | mips_add_token (&token, OT_CHANNELS); | |
3071 | } | |
3072 | ||
3073 | /* For consistency, only match "++" as part of base expressions too. */ | |
3074 | SKIP_SPACE_TABS (s); | |
3075 | if (s[0] == '+' && s[1] == '+') | |
3076 | { | |
3077 | s += 2; | |
3078 | token.u.ch = '+'; | |
3079 | mips_add_token (&token, OT_DOUBLE_CHAR); | |
3080 | } | |
3081 | ||
a92713e6 RS |
3082 | return s; |
3083 | } | |
3084 | ||
3085 | /* Parse one or more tokens from S. Return a pointer to the first | |
3086 | unconsumed character on success. Return null if an error was found | |
3087 | and store the error text in insn_error. FLOAT_FORMAT is as for | |
3088 | mips_parse_arguments. */ | |
3089 | ||
3090 | static char * | |
3091 | mips_parse_argument_token (char *s, char float_format) | |
3092 | { | |
6d4af3c2 AM |
3093 | char *end, *save_in; |
3094 | const char *err; | |
14daeee3 | 3095 | unsigned int regno1, regno2, channels; |
a92713e6 RS |
3096 | struct mips_operand_token token; |
3097 | ||
3098 | /* First look for "($reg", since we want to treat that as an | |
3099 | OT_CHAR and OT_REG rather than an expression. */ | |
3100 | end = mips_parse_base_start (s); | |
3101 | if (end) | |
3102 | return end; | |
3103 | ||
3104 | /* Handle other characters that end up as OT_CHARs. */ | |
3105 | if (*s == ')' || *s == ',') | |
3106 | { | |
3107 | token.u.ch = *s; | |
3108 | mips_add_token (&token, OT_CHAR); | |
3109 | ++s; | |
3110 | return s; | |
3111 | } | |
3112 | ||
3113 | /* Handle tokens that start with a register. */ | |
14daeee3 | 3114 | if (mips_parse_register (&s, ®no1, &channels)) |
df58fc94 | 3115 | { |
14daeee3 RS |
3116 | if (channels) |
3117 | { | |
3118 | /* A register and a VU0 channel suffix. */ | |
3119 | token.u.regno = regno1; | |
3120 | mips_add_token (&token, OT_REG); | |
3121 | ||
3122 | token.u.channels = channels; | |
3123 | mips_add_token (&token, OT_CHANNELS); | |
3124 | return s; | |
3125 | } | |
3126 | ||
a92713e6 RS |
3127 | SKIP_SPACE_TABS (s); |
3128 | if (*s == '-') | |
df58fc94 | 3129 | { |
a92713e6 RS |
3130 | /* A register range. */ |
3131 | ++s; | |
3132 | SKIP_SPACE_TABS (s); | |
14daeee3 | 3133 | if (!mips_parse_register (&s, ®no2, NULL)) |
a92713e6 | 3134 | { |
1661c76c | 3135 | set_insn_error (0, _("invalid register range")); |
a92713e6 RS |
3136 | return 0; |
3137 | } | |
df58fc94 | 3138 | |
a92713e6 RS |
3139 | token.u.reg_range.regno1 = regno1; |
3140 | token.u.reg_range.regno2 = regno2; | |
3141 | mips_add_token (&token, OT_REG_RANGE); | |
3142 | return s; | |
3143 | } | |
a92713e6 | 3144 | |
56d438b1 CF |
3145 | /* Add the register itself. */ |
3146 | token.u.regno = regno1; | |
3147 | mips_add_token (&token, OT_REG); | |
3148 | ||
3149 | /* Check for a vector index. */ | |
3150 | if (*s == '[') | |
3151 | { | |
a92713e6 RS |
3152 | ++s; |
3153 | SKIP_SPACE_TABS (s); | |
56d438b1 CF |
3154 | if (mips_parse_register (&s, &token.u.regno, NULL)) |
3155 | mips_add_token (&token, OT_REG_INDEX); | |
3156 | else | |
a92713e6 | 3157 | { |
56d438b1 CF |
3158 | expressionS element; |
3159 | ||
3160 | my_getExpression (&element, s); | |
3161 | if (element.X_op != O_constant) | |
3162 | { | |
3163 | set_insn_error (0, _("vector element must be constant")); | |
3164 | return 0; | |
3165 | } | |
3166 | s = expr_end; | |
3167 | token.u.index = element.X_add_number; | |
3168 | mips_add_token (&token, OT_INTEGER_INDEX); | |
a92713e6 | 3169 | } |
a92713e6 RS |
3170 | SKIP_SPACE_TABS (s); |
3171 | if (*s != ']') | |
3172 | { | |
1661c76c | 3173 | set_insn_error (0, _("missing `]'")); |
a92713e6 RS |
3174 | return 0; |
3175 | } | |
3176 | ++s; | |
df58fc94 | 3177 | } |
a92713e6 | 3178 | return s; |
df58fc94 RS |
3179 | } |
3180 | ||
a92713e6 RS |
3181 | if (float_format) |
3182 | { | |
3183 | /* First try to treat expressions as floats. */ | |
3184 | save_in = input_line_pointer; | |
3185 | input_line_pointer = s; | |
3186 | err = md_atof (float_format, (char *) token.u.flt.data, | |
3187 | &token.u.flt.length); | |
3188 | end = input_line_pointer; | |
3189 | input_line_pointer = save_in; | |
3190 | if (err && *err) | |
3191 | { | |
e3de51ce | 3192 | set_insn_error (0, err); |
a92713e6 RS |
3193 | return 0; |
3194 | } | |
3195 | if (s != end) | |
3196 | { | |
3197 | mips_add_token (&token, OT_FLOAT); | |
3198 | return end; | |
3199 | } | |
3200 | } | |
3201 | ||
3202 | /* Treat everything else as an integer expression. */ | |
3203 | token.u.integer.relocs[0] = BFD_RELOC_UNUSED; | |
3204 | token.u.integer.relocs[1] = BFD_RELOC_UNUSED; | |
3205 | token.u.integer.relocs[2] = BFD_RELOC_UNUSED; | |
3206 | my_getSmallExpression (&token.u.integer.value, token.u.integer.relocs, s); | |
3207 | s = expr_end; | |
3208 | mips_add_token (&token, OT_INTEGER); | |
3209 | return s; | |
3210 | } | |
3211 | ||
3212 | /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f' | |
3213 | if expressions should be treated as 32-bit floating-point constants, | |
3214 | 'd' if they should be treated as 64-bit floating-point constants, | |
3215 | or 0 if they should be treated as integer expressions (the usual case). | |
3216 | ||
3217 | Return a list of tokens on success, otherwise return 0. The caller | |
3218 | must obstack_free the list after use. */ | |
3219 | ||
3220 | static struct mips_operand_token * | |
3221 | mips_parse_arguments (char *s, char float_format) | |
3222 | { | |
3223 | struct mips_operand_token token; | |
3224 | ||
3225 | SKIP_SPACE_TABS (s); | |
3226 | while (*s) | |
3227 | { | |
3228 | s = mips_parse_argument_token (s, float_format); | |
3229 | if (!s) | |
3230 | { | |
3231 | obstack_free (&mips_operand_tokens, | |
3232 | obstack_finish (&mips_operand_tokens)); | |
3233 | return 0; | |
3234 | } | |
3235 | SKIP_SPACE_TABS (s); | |
3236 | } | |
3237 | mips_add_token (&token, OT_END); | |
3238 | return (struct mips_operand_token *) obstack_finish (&mips_operand_tokens); | |
df58fc94 RS |
3239 | } |
3240 | ||
d301a56b RS |
3241 | /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE |
3242 | and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */ | |
037b32b9 AN |
3243 | |
3244 | static bfd_boolean | |
f79e2745 | 3245 | is_opcode_valid (const struct mips_opcode *mo) |
037b32b9 AN |
3246 | { |
3247 | int isa = mips_opts.isa; | |
846ef2d0 | 3248 | int ase = mips_opts.ase; |
037b32b9 | 3249 | int fp_s, fp_d; |
c6278170 | 3250 | unsigned int i; |
037b32b9 | 3251 | |
be0fcbee | 3252 | if (ISA_HAS_64BIT_REGS (isa)) |
c6278170 RS |
3253 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) |
3254 | if ((ase & mips_ases[i].flags) == mips_ases[i].flags) | |
3255 | ase |= mips_ases[i].flags64; | |
037b32b9 | 3256 | |
d301a56b | 3257 | if (!opcode_is_member (mo, isa, ase, mips_opts.arch)) |
037b32b9 AN |
3258 | return FALSE; |
3259 | ||
3260 | /* Check whether the instruction or macro requires single-precision or | |
3261 | double-precision floating-point support. Note that this information is | |
3262 | stored differently in the opcode table for insns and macros. */ | |
3263 | if (mo->pinfo == INSN_MACRO) | |
3264 | { | |
3265 | fp_s = mo->pinfo2 & INSN2_M_FP_S; | |
3266 | fp_d = mo->pinfo2 & INSN2_M_FP_D; | |
3267 | } | |
3268 | else | |
3269 | { | |
3270 | fp_s = mo->pinfo & FP_S; | |
3271 | fp_d = mo->pinfo & FP_D; | |
3272 | } | |
3273 | ||
3274 | if (fp_d && (mips_opts.soft_float || mips_opts.single_float)) | |
3275 | return FALSE; | |
3276 | ||
3277 | if (fp_s && mips_opts.soft_float) | |
3278 | return FALSE; | |
3279 | ||
3280 | return TRUE; | |
3281 | } | |
3282 | ||
3283 | /* Return TRUE if the MIPS16 opcode MO is valid on the currently | |
3284 | selected ISA and architecture. */ | |
3285 | ||
3286 | static bfd_boolean | |
3287 | is_opcode_valid_16 (const struct mips_opcode *mo) | |
3288 | { | |
d301a56b | 3289 | return opcode_is_member (mo, mips_opts.isa, 0, mips_opts.arch); |
037b32b9 AN |
3290 | } |
3291 | ||
df58fc94 | 3292 | /* Return TRUE if the size of the microMIPS opcode MO matches one |
7fd53920 MR |
3293 | explicitly requested. Always TRUE in the standard MIPS mode. |
3294 | Use is_size_valid_16 for MIPS16 opcodes. */ | |
df58fc94 RS |
3295 | |
3296 | static bfd_boolean | |
3297 | is_size_valid (const struct mips_opcode *mo) | |
3298 | { | |
3299 | if (!mips_opts.micromips) | |
3300 | return TRUE; | |
3301 | ||
833794fc MR |
3302 | if (mips_opts.insn32) |
3303 | { | |
3304 | if (mo->pinfo != INSN_MACRO && micromips_insn_length (mo) != 4) | |
3305 | return FALSE; | |
3306 | if ((mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0) | |
3307 | return FALSE; | |
3308 | } | |
df58fc94 RS |
3309 | if (!forced_insn_length) |
3310 | return TRUE; | |
3311 | if (mo->pinfo == INSN_MACRO) | |
3312 | return FALSE; | |
3313 | return forced_insn_length == micromips_insn_length (mo); | |
3314 | } | |
3315 | ||
7fd53920 MR |
3316 | /* Return TRUE if the size of the MIPS16 opcode MO matches one |
3317 | explicitly requested. */ | |
3318 | ||
3319 | static bfd_boolean | |
3320 | is_size_valid_16 (const struct mips_opcode *mo) | |
3321 | { | |
3322 | if (!forced_insn_length) | |
3323 | return TRUE; | |
3324 | if (mo->pinfo == INSN_MACRO) | |
3325 | return FALSE; | |
3326 | if (forced_insn_length == 2 && mips_opcode_32bit_p (mo)) | |
3327 | return FALSE; | |
0674ee5d MR |
3328 | if (forced_insn_length == 4 && (mo->pinfo2 & INSN2_SHORT_ONLY)) |
3329 | return FALSE; | |
7fd53920 MR |
3330 | return TRUE; |
3331 | } | |
3332 | ||
df58fc94 | 3333 | /* Return TRUE if the microMIPS opcode MO is valid for the delay slot |
e64af278 MR |
3334 | of the preceding instruction. Always TRUE in the standard MIPS mode. |
3335 | ||
3336 | We don't accept macros in 16-bit delay slots to avoid a case where | |
3337 | a macro expansion fails because it relies on a preceding 32-bit real | |
3338 | instruction to have matched and does not handle the operands correctly. | |
3339 | The only macros that may expand to 16-bit instructions are JAL that | |
3340 | cannot be placed in a delay slot anyway, and corner cases of BALIGN | |
3341 | and BGT (that likewise cannot be placed in a delay slot) that decay to | |
3342 | a NOP. In all these cases the macros precede any corresponding real | |
3343 | instruction definitions in the opcode table, so they will match in the | |
3344 | second pass where the size of the delay slot is ignored and therefore | |
3345 | produce correct code. */ | |
df58fc94 RS |
3346 | |
3347 | static bfd_boolean | |
3348 | is_delay_slot_valid (const struct mips_opcode *mo) | |
3349 | { | |
3350 | if (!mips_opts.micromips) | |
3351 | return TRUE; | |
3352 | ||
3353 | if (mo->pinfo == INSN_MACRO) | |
c06dec14 | 3354 | return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0; |
df58fc94 RS |
3355 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 |
3356 | && micromips_insn_length (mo) != 4) | |
3357 | return FALSE; | |
3358 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 | |
3359 | && micromips_insn_length (mo) != 2) | |
3360 | return FALSE; | |
3361 | ||
3362 | return TRUE; | |
3363 | } | |
3364 | ||
fc76e730 RS |
3365 | /* For consistency checking, verify that all bits of OPCODE are specified |
3366 | either by the match/mask part of the instruction definition, or by the | |
3367 | operand list. Also build up a list of operands in OPERANDS. | |
3368 | ||
3369 | INSN_BITS says which bits of the instruction are significant. | |
3370 | If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND | |
3371 | provides the mips_operand description of each operand. DECODE_OPERAND | |
3372 | is null for MIPS16 instructions. */ | |
ab902481 RS |
3373 | |
3374 | static int | |
3375 | validate_mips_insn (const struct mips_opcode *opcode, | |
3376 | unsigned long insn_bits, | |
fc76e730 RS |
3377 | const struct mips_operand *(*decode_operand) (const char *), |
3378 | struct mips_operand_array *operands) | |
ab902481 RS |
3379 | { |
3380 | const char *s; | |
fc76e730 | 3381 | unsigned long used_bits, doubled, undefined, opno, mask; |
ab902481 RS |
3382 | const struct mips_operand *operand; |
3383 | ||
fc76e730 RS |
3384 | mask = (opcode->pinfo == INSN_MACRO ? 0 : opcode->mask); |
3385 | if ((mask & opcode->match) != opcode->match) | |
ab902481 RS |
3386 | { |
3387 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
3388 | opcode->name, opcode->args); | |
3389 | return 0; | |
3390 | } | |
3391 | used_bits = 0; | |
fc76e730 | 3392 | opno = 0; |
14daeee3 RS |
3393 | if (opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) |
3394 | used_bits = mips_insert_operand (&mips_vu0_channel_mask, used_bits, -1); | |
ab902481 RS |
3395 | for (s = opcode->args; *s; ++s) |
3396 | switch (*s) | |
3397 | { | |
3398 | case ',': | |
3399 | case '(': | |
3400 | case ')': | |
3401 | break; | |
3402 | ||
14daeee3 RS |
3403 | case '#': |
3404 | s++; | |
3405 | break; | |
3406 | ||
ab902481 | 3407 | default: |
fc76e730 | 3408 | if (!decode_operand) |
7fd53920 | 3409 | operand = decode_mips16_operand (*s, mips_opcode_32bit_p (opcode)); |
fc76e730 RS |
3410 | else |
3411 | operand = decode_operand (s); | |
3412 | if (!operand && opcode->pinfo != INSN_MACRO) | |
ab902481 RS |
3413 | { |
3414 | as_bad (_("internal: unknown operand type: %s %s"), | |
3415 | opcode->name, opcode->args); | |
3416 | return 0; | |
3417 | } | |
fc76e730 RS |
3418 | gas_assert (opno < MAX_OPERANDS); |
3419 | operands->operand[opno] = operand; | |
14daeee3 | 3420 | if (operand && operand->type != OP_VU0_MATCH_SUFFIX) |
fc76e730 | 3421 | { |
14daeee3 | 3422 | used_bits = mips_insert_operand (operand, used_bits, -1); |
fc76e730 RS |
3423 | if (operand->type == OP_MDMX_IMM_REG) |
3424 | /* Bit 5 is the format selector (OB vs QH). The opcode table | |
3425 | has separate entries for each format. */ | |
3426 | used_bits &= ~(1 << (operand->lsb + 5)); | |
3427 | if (operand->type == OP_ENTRY_EXIT_LIST) | |
3428 | used_bits &= ~(mask & 0x700); | |
3429 | } | |
ab902481 | 3430 | /* Skip prefix characters. */ |
7361da2c | 3431 | if (decode_operand && (*s == '+' || *s == 'm' || *s == '-')) |
ab902481 | 3432 | ++s; |
fc76e730 | 3433 | opno += 1; |
ab902481 RS |
3434 | break; |
3435 | } | |
fc76e730 | 3436 | doubled = used_bits & mask & insn_bits; |
ab902481 RS |
3437 | if (doubled) |
3438 | { | |
3439 | as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):" | |
3440 | " %s %s"), doubled, opcode->name, opcode->args); | |
3441 | return 0; | |
3442 | } | |
fc76e730 | 3443 | used_bits |= mask; |
ab902481 | 3444 | undefined = ~used_bits & insn_bits; |
fc76e730 | 3445 | if (opcode->pinfo != INSN_MACRO && undefined) |
ab902481 RS |
3446 | { |
3447 | as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"), | |
3448 | undefined, opcode->name, opcode->args); | |
3449 | return 0; | |
3450 | } | |
3451 | used_bits &= ~insn_bits; | |
3452 | if (used_bits) | |
3453 | { | |
3454 | as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"), | |
3455 | used_bits, opcode->name, opcode->args); | |
3456 | return 0; | |
3457 | } | |
3458 | return 1; | |
3459 | } | |
3460 | ||
fc76e730 RS |
3461 | /* The MIPS16 version of validate_mips_insn. */ |
3462 | ||
3463 | static int | |
3464 | validate_mips16_insn (const struct mips_opcode *opcode, | |
3465 | struct mips_operand_array *operands) | |
3466 | { | |
7fd53920 | 3467 | unsigned long insn_bits = mips_opcode_32bit_p (opcode) ? 0xffffffff : 0xffff; |
fc76e730 | 3468 | |
7fd53920 | 3469 | return validate_mips_insn (opcode, insn_bits, 0, operands); |
fc76e730 RS |
3470 | } |
3471 | ||
ab902481 RS |
3472 | /* The microMIPS version of validate_mips_insn. */ |
3473 | ||
3474 | static int | |
fc76e730 RS |
3475 | validate_micromips_insn (const struct mips_opcode *opc, |
3476 | struct mips_operand_array *operands) | |
ab902481 RS |
3477 | { |
3478 | unsigned long insn_bits; | |
3479 | unsigned long major; | |
3480 | unsigned int length; | |
3481 | ||
fc76e730 RS |
3482 | if (opc->pinfo == INSN_MACRO) |
3483 | return validate_mips_insn (opc, 0xffffffff, decode_micromips_operand, | |
3484 | operands); | |
3485 | ||
ab902481 RS |
3486 | length = micromips_insn_length (opc); |
3487 | if (length != 2 && length != 4) | |
3488 | { | |
1661c76c | 3489 | as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): " |
ab902481 RS |
3490 | "%s %s"), length, opc->name, opc->args); |
3491 | return 0; | |
3492 | } | |
3493 | major = opc->match >> (10 + 8 * (length - 2)); | |
3494 | if ((length == 2 && (major & 7) != 1 && (major & 6) != 2) | |
3495 | || (length == 4 && (major & 7) != 0 && (major & 4) != 4)) | |
3496 | { | |
1661c76c | 3497 | as_bad (_("internal error: bad microMIPS opcode " |
ab902481 RS |
3498 | "(opcode/length mismatch): %s %s"), opc->name, opc->args); |
3499 | return 0; | |
3500 | } | |
3501 | ||
3502 | /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */ | |
3503 | insn_bits = 1 << 4 * length; | |
3504 | insn_bits <<= 4 * length; | |
3505 | insn_bits -= 1; | |
fc76e730 RS |
3506 | return validate_mips_insn (opc, insn_bits, decode_micromips_operand, |
3507 | operands); | |
ab902481 RS |
3508 | } |
3509 | ||
707bfff6 TS |
3510 | /* This function is called once, at assembler startup time. It should set up |
3511 | all the tables, etc. that the MD part of the assembler will need. */ | |
156c2f8b | 3512 | |
252b5132 | 3513 | void |
17a2f251 | 3514 | md_begin (void) |
252b5132 | 3515 | { |
3994f87e | 3516 | const char *retval = NULL; |
156c2f8b | 3517 | int i = 0; |
252b5132 | 3518 | int broken = 0; |
1f25f5d3 | 3519 | |
0a44bf69 RS |
3520 | if (mips_pic != NO_PIC) |
3521 | { | |
3522 | if (g_switch_seen && g_switch_value != 0) | |
3523 | as_bad (_("-G may not be used in position-independent code")); | |
3524 | g_switch_value = 0; | |
3525 | } | |
00acd688 CM |
3526 | else if (mips_abicalls) |
3527 | { | |
3528 | if (g_switch_seen && g_switch_value != 0) | |
3529 | as_bad (_("-G may not be used with abicalls")); | |
3530 | g_switch_value = 0; | |
3531 | } | |
0a44bf69 | 3532 | |
0b35dfee | 3533 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch)) |
1661c76c | 3534 | as_warn (_("could not set architecture and machine")); |
252b5132 | 3535 | |
252b5132 RH |
3536 | op_hash = hash_new (); |
3537 | ||
fc76e730 | 3538 | mips_operands = XCNEWVEC (struct mips_operand_array, NUMOPCODES); |
252b5132 RH |
3539 | for (i = 0; i < NUMOPCODES;) |
3540 | { | |
3541 | const char *name = mips_opcodes[i].name; | |
3542 | ||
17a2f251 | 3543 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
3544 | if (retval != NULL) |
3545 | { | |
3546 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
3547 | mips_opcodes[i].name, retval); | |
3548 | /* Probably a memory allocation problem? Give up now. */ | |
1661c76c | 3549 | as_fatal (_("broken assembler, no assembly attempted")); |
252b5132 RH |
3550 | } |
3551 | do | |
3552 | { | |
fc76e730 RS |
3553 | if (!validate_mips_insn (&mips_opcodes[i], 0xffffffff, |
3554 | decode_mips_operand, &mips_operands[i])) | |
3555 | broken = 1; | |
3556 | if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) | |
252b5132 | 3557 | { |
fc76e730 RS |
3558 | create_insn (&nop_insn, mips_opcodes + i); |
3559 | if (mips_fix_loongson2f_nop) | |
3560 | nop_insn.insn_opcode = LOONGSON2F_NOP_INSN; | |
3561 | nop_insn.fixed_p = 1; | |
252b5132 RH |
3562 | } |
3563 | ++i; | |
3564 | } | |
3565 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
3566 | } | |
3567 | ||
3568 | mips16_op_hash = hash_new (); | |
fc76e730 RS |
3569 | mips16_operands = XCNEWVEC (struct mips_operand_array, |
3570 | bfd_mips16_num_opcodes); | |
252b5132 RH |
3571 | |
3572 | i = 0; | |
3573 | while (i < bfd_mips16_num_opcodes) | |
3574 | { | |
3575 | const char *name = mips16_opcodes[i].name; | |
3576 | ||
17a2f251 | 3577 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
3578 | if (retval != NULL) |
3579 | as_fatal (_("internal: can't hash `%s': %s"), | |
3580 | mips16_opcodes[i].name, retval); | |
3581 | do | |
3582 | { | |
fc76e730 RS |
3583 | if (!validate_mips16_insn (&mips16_opcodes[i], &mips16_operands[i])) |
3584 | broken = 1; | |
1e915849 RS |
3585 | if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
3586 | { | |
3587 | create_insn (&mips16_nop_insn, mips16_opcodes + i); | |
3588 | mips16_nop_insn.fixed_p = 1; | |
3589 | } | |
252b5132 RH |
3590 | ++i; |
3591 | } | |
3592 | while (i < bfd_mips16_num_opcodes | |
3593 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
3594 | } | |
3595 | ||
df58fc94 | 3596 | micromips_op_hash = hash_new (); |
fc76e730 RS |
3597 | micromips_operands = XCNEWVEC (struct mips_operand_array, |
3598 | bfd_micromips_num_opcodes); | |
df58fc94 RS |
3599 | |
3600 | i = 0; | |
3601 | while (i < bfd_micromips_num_opcodes) | |
3602 | { | |
3603 | const char *name = micromips_opcodes[i].name; | |
3604 | ||
3605 | retval = hash_insert (micromips_op_hash, name, | |
3606 | (void *) µmips_opcodes[i]); | |
3607 | if (retval != NULL) | |
3608 | as_fatal (_("internal: can't hash `%s': %s"), | |
3609 | micromips_opcodes[i].name, retval); | |
3610 | do | |
fc76e730 RS |
3611 | { |
3612 | struct mips_cl_insn *micromips_nop_insn; | |
3613 | ||
3614 | if (!validate_micromips_insn (µmips_opcodes[i], | |
3615 | µmips_operands[i])) | |
3616 | broken = 1; | |
3617 | ||
3618 | if (micromips_opcodes[i].pinfo != INSN_MACRO) | |
3619 | { | |
3620 | if (micromips_insn_length (micromips_opcodes + i) == 2) | |
3621 | micromips_nop_insn = µmips_nop16_insn; | |
3622 | else if (micromips_insn_length (micromips_opcodes + i) == 4) | |
3623 | micromips_nop_insn = µmips_nop32_insn; | |
3624 | else | |
3625 | continue; | |
3626 | ||
3627 | if (micromips_nop_insn->insn_mo == NULL | |
3628 | && strcmp (name, "nop") == 0) | |
3629 | { | |
3630 | create_insn (micromips_nop_insn, micromips_opcodes + i); | |
3631 | micromips_nop_insn->fixed_p = 1; | |
3632 | } | |
3633 | } | |
3634 | } | |
df58fc94 RS |
3635 | while (++i < bfd_micromips_num_opcodes |
3636 | && strcmp (micromips_opcodes[i].name, name) == 0); | |
3637 | } | |
3638 | ||
252b5132 | 3639 | if (broken) |
1661c76c | 3640 | as_fatal (_("broken assembler, no assembly attempted")); |
252b5132 RH |
3641 | |
3642 | /* We add all the general register names to the symbol table. This | |
3643 | helps us detect invalid uses of them. */ | |
3739860c | 3644 | for (i = 0; reg_names[i].name; i++) |
707bfff6 | 3645 | symbol_table_insert (symbol_new (reg_names[i].name, reg_section, |
8fc4ee9b | 3646 | reg_names[i].num, /* & RNUM_MASK, */ |
707bfff6 TS |
3647 | &zero_address_frag)); |
3648 | if (HAVE_NEWABI) | |
3739860c | 3649 | for (i = 0; reg_names_n32n64[i].name; i++) |
707bfff6 | 3650 | symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section, |
8fc4ee9b | 3651 | reg_names_n32n64[i].num, /* & RNUM_MASK, */ |
252b5132 | 3652 | &zero_address_frag)); |
707bfff6 | 3653 | else |
3739860c | 3654 | for (i = 0; reg_names_o32[i].name; i++) |
707bfff6 | 3655 | symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section, |
8fc4ee9b | 3656 | reg_names_o32[i].num, /* & RNUM_MASK, */ |
6047c971 | 3657 | &zero_address_frag)); |
6047c971 | 3658 | |
14daeee3 RS |
3659 | for (i = 0; i < 32; i++) |
3660 | { | |
92fce9bd | 3661 | char regname[6]; |
14daeee3 RS |
3662 | |
3663 | /* R5900 VU0 floating-point register. */ | |
92fce9bd | 3664 | sprintf (regname, "$vf%d", i); |
14daeee3 RS |
3665 | symbol_table_insert (symbol_new (regname, reg_section, |
3666 | RTYPE_VF | i, &zero_address_frag)); | |
3667 | ||
3668 | /* R5900 VU0 integer register. */ | |
92fce9bd | 3669 | sprintf (regname, "$vi%d", i); |
14daeee3 RS |
3670 | symbol_table_insert (symbol_new (regname, reg_section, |
3671 | RTYPE_VI | i, &zero_address_frag)); | |
3672 | ||
56d438b1 | 3673 | /* MSA register. */ |
92fce9bd | 3674 | sprintf (regname, "$w%d", i); |
56d438b1 CF |
3675 | symbol_table_insert (symbol_new (regname, reg_section, |
3676 | RTYPE_MSA | i, &zero_address_frag)); | |
14daeee3 RS |
3677 | } |
3678 | ||
a92713e6 RS |
3679 | obstack_init (&mips_operand_tokens); |
3680 | ||
7d10b47d | 3681 | mips_no_prev_insn (); |
252b5132 RH |
3682 | |
3683 | mips_gprmask = 0; | |
3684 | mips_cprmask[0] = 0; | |
3685 | mips_cprmask[1] = 0; | |
3686 | mips_cprmask[2] = 0; | |
3687 | mips_cprmask[3] = 0; | |
3688 | ||
3689 | /* set the default alignment for the text section (2**2) */ | |
3690 | record_alignment (text_section, 2); | |
3691 | ||
4d0d148d | 3692 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 | 3693 | |
f3ded42a RS |
3694 | /* On a native system other than VxWorks, sections must be aligned |
3695 | to 16 byte boundaries. When configured for an embedded ELF | |
3696 | target, we don't bother. */ | |
3697 | if (strncmp (TARGET_OS, "elf", 3) != 0 | |
3698 | && strncmp (TARGET_OS, "vxworks", 7) != 0) | |
252b5132 | 3699 | { |
f3ded42a RS |
3700 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); |
3701 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
3702 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
3703 | } | |
252b5132 | 3704 | |
f3ded42a RS |
3705 | /* Create a .reginfo section for register masks and a .mdebug |
3706 | section for debugging information. */ | |
3707 | { | |
3708 | segT seg; | |
3709 | subsegT subseg; | |
3710 | flagword flags; | |
3711 | segT sec; | |
3712 | ||
3713 | seg = now_seg; | |
3714 | subseg = now_subseg; | |
3715 | ||
3716 | /* The ABI says this section should be loaded so that the | |
3717 | running program can access it. However, we don't load it | |
3718 | if we are configured for an embedded target */ | |
3719 | flags = SEC_READONLY | SEC_DATA; | |
3720 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
3721 | flags |= SEC_ALLOC | SEC_LOAD; | |
3722 | ||
3723 | if (mips_abi != N64_ABI) | |
252b5132 | 3724 | { |
f3ded42a | 3725 | sec = subseg_new (".reginfo", (subsegT) 0); |
bdaaa2e1 | 3726 | |
f3ded42a RS |
3727 | bfd_set_section_flags (stdoutput, sec, flags); |
3728 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
252b5132 | 3729 | |
f3ded42a RS |
3730 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
3731 | } | |
3732 | else | |
3733 | { | |
3734 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
3735 | .reginfo section. */ | |
3736 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
3737 | bfd_set_section_flags (stdoutput, sec, flags); | |
3738 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 | 3739 | |
f3ded42a RS |
3740 | /* Set up the option header. */ |
3741 | { | |
3742 | Elf_Internal_Options opthdr; | |
3743 | char *f; | |
3744 | ||
3745 | opthdr.kind = ODK_REGINFO; | |
3746 | opthdr.size = (sizeof (Elf_External_Options) | |
3747 | + sizeof (Elf64_External_RegInfo)); | |
3748 | opthdr.section = 0; | |
3749 | opthdr.info = 0; | |
3750 | f = frag_more (sizeof (Elf_External_Options)); | |
3751 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
3752 | (Elf_External_Options *) f); | |
3753 | ||
3754 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
3755 | } | |
3756 | } | |
252b5132 | 3757 | |
351cdf24 MF |
3758 | sec = subseg_new (".MIPS.abiflags", (subsegT) 0); |
3759 | bfd_set_section_flags (stdoutput, sec, | |
3760 | SEC_READONLY | SEC_DATA | SEC_ALLOC | SEC_LOAD); | |
3761 | bfd_set_section_alignment (stdoutput, sec, 3); | |
3762 | mips_flags_frag = frag_more (sizeof (Elf_External_ABIFlags_v0)); | |
3763 | ||
f3ded42a RS |
3764 | if (ECOFF_DEBUGGING) |
3765 | { | |
3766 | sec = subseg_new (".mdebug", (subsegT) 0); | |
3767 | (void) bfd_set_section_flags (stdoutput, sec, | |
3768 | SEC_HAS_CONTENTS | SEC_READONLY); | |
3769 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
252b5132 | 3770 | } |
f3ded42a RS |
3771 | else if (mips_flag_pdr) |
3772 | { | |
3773 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
3774 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
3775 | SEC_READONLY | SEC_RELOC | |
3776 | | SEC_DEBUGGING); | |
3777 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
3778 | } | |
3779 | ||
3780 | subseg_set (seg, subseg); | |
3781 | } | |
252b5132 | 3782 | |
71400594 RS |
3783 | if (mips_fix_vr4120) |
3784 | init_vr4120_conflicts (); | |
252b5132 RH |
3785 | } |
3786 | ||
351cdf24 MF |
3787 | static inline void |
3788 | fpabi_incompatible_with (int fpabi, const char *what) | |
3789 | { | |
3790 | as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"), | |
3791 | Tag_GNU_MIPS_ABI_FP, fpabi, what); | |
3792 | } | |
3793 | ||
3794 | static inline void | |
3795 | fpabi_requires (int fpabi, const char *what) | |
3796 | { | |
3797 | as_warn (_(".gnu_attribute %d,%d requires `%s'"), | |
3798 | Tag_GNU_MIPS_ABI_FP, fpabi, what); | |
3799 | } | |
3800 | ||
3801 | /* Check -mabi and register sizes against the specified FP ABI. */ | |
3802 | static void | |
3803 | check_fpabi (int fpabi) | |
3804 | { | |
351cdf24 MF |
3805 | switch (fpabi) |
3806 | { | |
3807 | case Val_GNU_MIPS_ABI_FP_DOUBLE: | |
ea79f94a MF |
3808 | if (file_mips_opts.soft_float) |
3809 | fpabi_incompatible_with (fpabi, "softfloat"); | |
3810 | else if (file_mips_opts.single_float) | |
3811 | fpabi_incompatible_with (fpabi, "singlefloat"); | |
351cdf24 MF |
3812 | if (file_mips_opts.gp == 64 && file_mips_opts.fp == 32) |
3813 | fpabi_incompatible_with (fpabi, "gp=64 fp=32"); | |
3814 | else if (file_mips_opts.gp == 32 && file_mips_opts.fp == 64) | |
3815 | fpabi_incompatible_with (fpabi, "gp=32 fp=64"); | |
351cdf24 MF |
3816 | break; |
3817 | ||
3818 | case Val_GNU_MIPS_ABI_FP_XX: | |
3819 | if (mips_abi != O32_ABI) | |
3820 | fpabi_requires (fpabi, "-mabi=32"); | |
ea79f94a MF |
3821 | else if (file_mips_opts.soft_float) |
3822 | fpabi_incompatible_with (fpabi, "softfloat"); | |
3823 | else if (file_mips_opts.single_float) | |
3824 | fpabi_incompatible_with (fpabi, "singlefloat"); | |
351cdf24 MF |
3825 | else if (file_mips_opts.fp != 0) |
3826 | fpabi_requires (fpabi, "fp=xx"); | |
351cdf24 MF |
3827 | break; |
3828 | ||
3829 | case Val_GNU_MIPS_ABI_FP_64A: | |
3830 | case Val_GNU_MIPS_ABI_FP_64: | |
3831 | if (mips_abi != O32_ABI) | |
3832 | fpabi_requires (fpabi, "-mabi=32"); | |
ea79f94a MF |
3833 | else if (file_mips_opts.soft_float) |
3834 | fpabi_incompatible_with (fpabi, "softfloat"); | |
3835 | else if (file_mips_opts.single_float) | |
3836 | fpabi_incompatible_with (fpabi, "singlefloat"); | |
351cdf24 MF |
3837 | else if (file_mips_opts.fp != 64) |
3838 | fpabi_requires (fpabi, "fp=64"); | |
3839 | else if (fpabi == Val_GNU_MIPS_ABI_FP_64 && !file_mips_opts.oddspreg) | |
3840 | fpabi_incompatible_with (fpabi, "nooddspreg"); | |
3841 | else if (fpabi == Val_GNU_MIPS_ABI_FP_64A && file_mips_opts.oddspreg) | |
3842 | fpabi_requires (fpabi, "nooddspreg"); | |
351cdf24 MF |
3843 | break; |
3844 | ||
3845 | case Val_GNU_MIPS_ABI_FP_SINGLE: | |
3846 | if (file_mips_opts.soft_float) | |
3847 | fpabi_incompatible_with (fpabi, "softfloat"); | |
3848 | else if (!file_mips_opts.single_float) | |
3849 | fpabi_requires (fpabi, "singlefloat"); | |
3850 | break; | |
3851 | ||
3852 | case Val_GNU_MIPS_ABI_FP_SOFT: | |
3853 | if (!file_mips_opts.soft_float) | |
3854 | fpabi_requires (fpabi, "softfloat"); | |
3855 | break; | |
3856 | ||
3857 | case Val_GNU_MIPS_ABI_FP_OLD_64: | |
3858 | as_warn (_(".gnu_attribute %d,%d is no longer supported"), | |
3859 | Tag_GNU_MIPS_ABI_FP, fpabi); | |
3860 | break; | |
3861 | ||
3350cc01 CM |
3862 | case Val_GNU_MIPS_ABI_FP_NAN2008: |
3863 | /* Silently ignore compatibility value. */ | |
3864 | break; | |
3865 | ||
351cdf24 MF |
3866 | default: |
3867 | as_warn (_(".gnu_attribute %d,%d is not a recognized" | |
3868 | " floating-point ABI"), Tag_GNU_MIPS_ABI_FP, fpabi); | |
3869 | break; | |
3870 | } | |
351cdf24 MF |
3871 | } |
3872 | ||
919731af | 3873 | /* Perform consistency checks on the current options. */ |
3874 | ||
3875 | static void | |
3876 | mips_check_options (struct mips_set_options *opts, bfd_boolean abi_checks) | |
3877 | { | |
3878 | /* Check the size of integer registers agrees with the ABI and ISA. */ | |
3879 | if (opts->gp == 64 && !ISA_HAS_64BIT_REGS (opts->isa)) | |
3880 | as_bad (_("`gp=64' used with a 32-bit processor")); | |
3881 | else if (abi_checks | |
3882 | && opts->gp == 32 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
3883 | as_bad (_("`gp=32' used with a 64-bit ABI")); | |
3884 | else if (abi_checks | |
3885 | && opts->gp == 64 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
3886 | as_bad (_("`gp=64' used with a 32-bit ABI")); | |
3887 | ||
3888 | /* Check the size of the float registers agrees with the ABI and ISA. */ | |
3889 | switch (opts->fp) | |
3890 | { | |
351cdf24 MF |
3891 | case 0: |
3892 | if (!CPU_HAS_LDC1_SDC1 (opts->arch)) | |
3893 | as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions")); | |
3894 | else if (opts->single_float == 1) | |
3895 | as_bad (_("`fp=xx' cannot be used with `singlefloat'")); | |
3896 | break; | |
919731af | 3897 | case 64: |
3898 | if (!ISA_HAS_64BIT_FPRS (opts->isa)) | |
3899 | as_bad (_("`fp=64' used with a 32-bit fpu")); | |
3900 | else if (abi_checks | |
3901 | && ABI_NEEDS_32BIT_REGS (mips_abi) | |
3902 | && !ISA_HAS_MXHC1 (opts->isa)) | |
3903 | as_warn (_("`fp=64' used with a 32-bit ABI")); | |
3904 | break; | |
3905 | case 32: | |
3906 | if (abi_checks | |
3907 | && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
3908 | as_warn (_("`fp=32' used with a 64-bit ABI")); | |
5f4678bb | 3909 | if (ISA_IS_R6 (opts->isa) && opts->single_float == 0) |
7361da2c | 3910 | as_bad (_("`fp=32' used with a MIPS R6 cpu")); |
919731af | 3911 | break; |
3912 | default: | |
3913 | as_bad (_("Unknown size of floating point registers")); | |
3914 | break; | |
3915 | } | |
3916 | ||
351cdf24 MF |
3917 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !opts->oddspreg) |
3918 | as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI")); | |
3919 | ||
919731af | 3920 | if (opts->micromips == 1 && opts->mips16 == 1) |
1357373c | 3921 | as_bad (_("`%s' cannot be used with `%s'"), "mips16", "micromips"); |
5f4678bb | 3922 | else if (ISA_IS_R6 (opts->isa) |
7361da2c AB |
3923 | && (opts->micromips == 1 |
3924 | || opts->mips16 == 1)) | |
1357373c | 3925 | as_fatal (_("`%s' cannot be used with `%s'"), |
7361da2c | 3926 | opts->micromips ? "micromips" : "mips16", |
5f4678bb | 3927 | mips_cpu_info_from_isa (opts->isa)->name); |
7361da2c AB |
3928 | |
3929 | if (ISA_IS_R6 (opts->isa) && mips_relax_branch) | |
3930 | as_fatal (_("branch relaxation is not supported in `%s'"), | |
3931 | mips_cpu_info_from_isa (opts->isa)->name); | |
919731af | 3932 | } |
3933 | ||
3934 | /* Perform consistency checks on the module level options exactly once. | |
3935 | This is a deferred check that happens: | |
3936 | at the first .set directive | |
3937 | or, at the first pseudo op that generates code (inc .dc.a) | |
3938 | or, at the first instruction | |
3939 | or, at the end. */ | |
3940 | ||
3941 | static void | |
3942 | file_mips_check_options (void) | |
3943 | { | |
3944 | const struct mips_cpu_info *arch_info = 0; | |
3945 | ||
3946 | if (file_mips_opts_checked) | |
3947 | return; | |
3948 | ||
3949 | /* The following code determines the register size. | |
3950 | Similar code was added to GCC 3.3 (see override_options() in | |
3951 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
3952 | as much as possible. */ | |
3953 | ||
3954 | if (file_mips_opts.gp < 0) | |
3955 | { | |
3956 | /* Infer the integer register size from the ABI and processor. | |
3957 | Restrict ourselves to 32-bit registers if that's all the | |
3958 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
3959 | file_mips_opts.gp = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
3960 | || !ISA_HAS_64BIT_REGS (file_mips_opts.isa)) | |
3961 | ? 32 : 64; | |
3962 | } | |
3963 | ||
3964 | if (file_mips_opts.fp < 0) | |
3965 | { | |
3966 | /* No user specified float register size. | |
3967 | ??? GAS treats single-float processors as though they had 64-bit | |
3968 | float registers (although it complains when double-precision | |
3969 | instructions are used). As things stand, saying they have 32-bit | |
3970 | registers would lead to spurious "register must be even" messages. | |
3971 | So here we assume float registers are never smaller than the | |
3972 | integer ones. */ | |
3973 | if (file_mips_opts.gp == 64) | |
3974 | /* 64-bit integer registers implies 64-bit float registers. */ | |
3975 | file_mips_opts.fp = 64; | |
3976 | else if ((file_mips_opts.ase & FP64_ASES) | |
3977 | && ISA_HAS_64BIT_FPRS (file_mips_opts.isa)) | |
3978 | /* Handle ASEs that require 64-bit float registers, if possible. */ | |
3979 | file_mips_opts.fp = 64; | |
7361da2c AB |
3980 | else if (ISA_IS_R6 (mips_opts.isa)) |
3981 | /* R6 implies 64-bit float registers. */ | |
3982 | file_mips_opts.fp = 64; | |
919731af | 3983 | else |
3984 | /* 32-bit float registers. */ | |
3985 | file_mips_opts.fp = 32; | |
3986 | } | |
3987 | ||
3988 | arch_info = mips_cpu_info_from_arch (file_mips_opts.arch); | |
3989 | ||
351cdf24 MF |
3990 | /* Disable operations on odd-numbered floating-point registers by default |
3991 | when using the FPXX ABI. */ | |
3992 | if (file_mips_opts.oddspreg < 0) | |
3993 | { | |
3994 | if (file_mips_opts.fp == 0) | |
3995 | file_mips_opts.oddspreg = 0; | |
3996 | else | |
3997 | file_mips_opts.oddspreg = 1; | |
3998 | } | |
3999 | ||
919731af | 4000 | /* End of GCC-shared inference code. */ |
4001 | ||
4002 | /* This flag is set when we have a 64-bit capable CPU but use only | |
4003 | 32-bit wide registers. Note that EABI does not use it. */ | |
4004 | if (ISA_HAS_64BIT_REGS (file_mips_opts.isa) | |
4005 | && ((mips_abi == NO_ABI && file_mips_opts.gp == 32) | |
4006 | || mips_abi == O32_ABI)) | |
4007 | mips_32bitmode = 1; | |
4008 | ||
4009 | if (file_mips_opts.isa == ISA_MIPS1 && mips_trap) | |
4010 | as_bad (_("trap exception not supported at ISA 1")); | |
4011 | ||
4012 | /* If the selected architecture includes support for ASEs, enable | |
4013 | generation of code for them. */ | |
4014 | if (file_mips_opts.mips16 == -1) | |
4015 | file_mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_opts.arch)) ? 1 : 0; | |
4016 | if (file_mips_opts.micromips == -1) | |
4017 | file_mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_opts.arch)) | |
4018 | ? 1 : 0; | |
4019 | ||
7361da2c AB |
4020 | if (mips_nan2008 == -1) |
4021 | mips_nan2008 = (ISA_HAS_LEGACY_NAN (file_mips_opts.isa)) ? 0 : 1; | |
4022 | else if (!ISA_HAS_LEGACY_NAN (file_mips_opts.isa) && mips_nan2008 == 0) | |
4023 | as_fatal (_("`%s' does not support legacy NaN"), | |
4024 | mips_cpu_info_from_arch (file_mips_opts.arch)->name); | |
4025 | ||
919731af | 4026 | /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from |
4027 | being selected implicitly. */ | |
4028 | if (file_mips_opts.fp != 64) | |
4029 | file_ase_explicit |= ASE_MIPS3D | ASE_MDMX | ASE_MSA; | |
4030 | ||
4031 | /* If the user didn't explicitly select or deselect a particular ASE, | |
4032 | use the default setting for the CPU. */ | |
4033 | file_mips_opts.ase |= (arch_info->ase & ~file_ase_explicit); | |
4034 | ||
4035 | /* Set up the current options. These may change throughout assembly. */ | |
4036 | mips_opts = file_mips_opts; | |
4037 | ||
4038 | mips_check_isa_supports_ases (); | |
4039 | mips_check_options (&file_mips_opts, TRUE); | |
4040 | file_mips_opts_checked = TRUE; | |
4041 | ||
4042 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch)) | |
4043 | as_warn (_("could not set architecture and machine")); | |
4044 | } | |
4045 | ||
252b5132 | 4046 | void |
17a2f251 | 4047 | md_assemble (char *str) |
252b5132 RH |
4048 | { |
4049 | struct mips_cl_insn insn; | |
f6688943 TS |
4050 | bfd_reloc_code_real_type unused_reloc[3] |
4051 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 4052 | |
919731af | 4053 | file_mips_check_options (); |
4054 | ||
252b5132 | 4055 | imm_expr.X_op = O_absent; |
252b5132 | 4056 | offset_expr.X_op = O_absent; |
f6688943 TS |
4057 | offset_reloc[0] = BFD_RELOC_UNUSED; |
4058 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
4059 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 | 4060 | |
e1b47bd5 RS |
4061 | mips_mark_labels (); |
4062 | mips_assembling_insn = TRUE; | |
e3de51ce | 4063 | clear_insn_error (); |
e1b47bd5 | 4064 | |
252b5132 RH |
4065 | if (mips_opts.mips16) |
4066 | mips16_ip (str, &insn); | |
4067 | else | |
4068 | { | |
4069 | mips_ip (str, &insn); | |
beae10d5 KH |
4070 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
4071 | str, insn.insn_opcode)); | |
252b5132 RH |
4072 | } |
4073 | ||
e3de51ce RS |
4074 | if (insn_error.msg) |
4075 | report_insn_error (str); | |
e1b47bd5 | 4076 | else if (insn.insn_mo->pinfo == INSN_MACRO) |
252b5132 | 4077 | { |
584892a6 | 4078 | macro_start (); |
252b5132 RH |
4079 | if (mips_opts.mips16) |
4080 | mips16_macro (&insn); | |
4081 | else | |
833794fc | 4082 | macro (&insn, str); |
584892a6 | 4083 | macro_end (); |
252b5132 RH |
4084 | } |
4085 | else | |
4086 | { | |
77bd4346 | 4087 | if (offset_expr.X_op != O_absent) |
df58fc94 | 4088 | append_insn (&insn, &offset_expr, offset_reloc, FALSE); |
252b5132 | 4089 | else |
df58fc94 | 4090 | append_insn (&insn, NULL, unused_reloc, FALSE); |
252b5132 | 4091 | } |
e1b47bd5 RS |
4092 | |
4093 | mips_assembling_insn = FALSE; | |
252b5132 RH |
4094 | } |
4095 | ||
738e5348 RS |
4096 | /* Convenience functions for abstracting away the differences between |
4097 | MIPS16 and non-MIPS16 relocations. */ | |
4098 | ||
4099 | static inline bfd_boolean | |
4100 | mips16_reloc_p (bfd_reloc_code_real_type reloc) | |
4101 | { | |
4102 | switch (reloc) | |
4103 | { | |
4104 | case BFD_RELOC_MIPS16_JMP: | |
4105 | case BFD_RELOC_MIPS16_GPREL: | |
4106 | case BFD_RELOC_MIPS16_GOT16: | |
4107 | case BFD_RELOC_MIPS16_CALL16: | |
4108 | case BFD_RELOC_MIPS16_HI16_S: | |
4109 | case BFD_RELOC_MIPS16_HI16: | |
4110 | case BFD_RELOC_MIPS16_LO16: | |
c9775dde | 4111 | case BFD_RELOC_MIPS16_16_PCREL_S1: |
738e5348 RS |
4112 | return TRUE; |
4113 | ||
4114 | default: | |
4115 | return FALSE; | |
4116 | } | |
4117 | } | |
4118 | ||
df58fc94 RS |
4119 | static inline bfd_boolean |
4120 | micromips_reloc_p (bfd_reloc_code_real_type reloc) | |
4121 | { | |
4122 | switch (reloc) | |
4123 | { | |
4124 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: | |
4125 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
4126 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
4127 | case BFD_RELOC_MICROMIPS_GPREL16: | |
4128 | case BFD_RELOC_MICROMIPS_JMP: | |
4129 | case BFD_RELOC_MICROMIPS_HI16: | |
4130 | case BFD_RELOC_MICROMIPS_HI16_S: | |
4131 | case BFD_RELOC_MICROMIPS_LO16: | |
4132 | case BFD_RELOC_MICROMIPS_LITERAL: | |
4133 | case BFD_RELOC_MICROMIPS_GOT16: | |
4134 | case BFD_RELOC_MICROMIPS_CALL16: | |
4135 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
4136 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
4137 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
4138 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
4139 | case BFD_RELOC_MICROMIPS_SUB: | |
4140 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
4141 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
4142 | case BFD_RELOC_MICROMIPS_GOT_DISP: | |
4143 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
4144 | case BFD_RELOC_MICROMIPS_HIGHER: | |
4145 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
4146 | case BFD_RELOC_MICROMIPS_JALR: | |
4147 | return TRUE; | |
4148 | ||
4149 | default: | |
4150 | return FALSE; | |
4151 | } | |
4152 | } | |
4153 | ||
2309ddf2 MR |
4154 | static inline bfd_boolean |
4155 | jmp_reloc_p (bfd_reloc_code_real_type reloc) | |
4156 | { | |
4157 | return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP; | |
4158 | } | |
4159 | ||
0e9c5a5c MR |
4160 | static inline bfd_boolean |
4161 | b_reloc_p (bfd_reloc_code_real_type reloc) | |
4162 | { | |
4163 | return (reloc == BFD_RELOC_MIPS_26_PCREL_S2 | |
4164 | || reloc == BFD_RELOC_MIPS_21_PCREL_S2 | |
4165 | || reloc == BFD_RELOC_16_PCREL_S2 | |
c9775dde | 4166 | || reloc == BFD_RELOC_MIPS16_16_PCREL_S1 |
0e9c5a5c MR |
4167 | || reloc == BFD_RELOC_MICROMIPS_16_PCREL_S1 |
4168 | || reloc == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
4169 | || reloc == BFD_RELOC_MICROMIPS_7_PCREL_S1); | |
4170 | } | |
4171 | ||
738e5348 RS |
4172 | static inline bfd_boolean |
4173 | got16_reloc_p (bfd_reloc_code_real_type reloc) | |
4174 | { | |
2309ddf2 | 4175 | return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16 |
df58fc94 | 4176 | || reloc == BFD_RELOC_MICROMIPS_GOT16); |
738e5348 RS |
4177 | } |
4178 | ||
4179 | static inline bfd_boolean | |
4180 | hi16_reloc_p (bfd_reloc_code_real_type reloc) | |
4181 | { | |
2309ddf2 | 4182 | return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S |
df58fc94 | 4183 | || reloc == BFD_RELOC_MICROMIPS_HI16_S); |
738e5348 RS |
4184 | } |
4185 | ||
4186 | static inline bfd_boolean | |
4187 | lo16_reloc_p (bfd_reloc_code_real_type reloc) | |
4188 | { | |
2309ddf2 | 4189 | return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16 |
df58fc94 RS |
4190 | || reloc == BFD_RELOC_MICROMIPS_LO16); |
4191 | } | |
4192 | ||
df58fc94 RS |
4193 | static inline bfd_boolean |
4194 | jalr_reloc_p (bfd_reloc_code_real_type reloc) | |
4195 | { | |
2309ddf2 | 4196 | return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR; |
738e5348 RS |
4197 | } |
4198 | ||
f2ae14a1 RS |
4199 | static inline bfd_boolean |
4200 | gprel16_reloc_p (bfd_reloc_code_real_type reloc) | |
4201 | { | |
4202 | return (reloc == BFD_RELOC_GPREL16 || reloc == BFD_RELOC_MIPS16_GPREL | |
4203 | || reloc == BFD_RELOC_MICROMIPS_GPREL16); | |
4204 | } | |
4205 | ||
2de39019 CM |
4206 | /* Return true if RELOC is a PC-relative relocation that does not have |
4207 | full address range. */ | |
4208 | ||
4209 | static inline bfd_boolean | |
4210 | limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc) | |
4211 | { | |
4212 | switch (reloc) | |
4213 | { | |
4214 | case BFD_RELOC_16_PCREL_S2: | |
c9775dde | 4215 | case BFD_RELOC_MIPS16_16_PCREL_S1: |
2de39019 CM |
4216 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
4217 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
4218 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
7361da2c AB |
4219 | case BFD_RELOC_MIPS_21_PCREL_S2: |
4220 | case BFD_RELOC_MIPS_26_PCREL_S2: | |
4221 | case BFD_RELOC_MIPS_18_PCREL_S3: | |
4222 | case BFD_RELOC_MIPS_19_PCREL_S2: | |
2de39019 CM |
4223 | return TRUE; |
4224 | ||
b47468a6 | 4225 | case BFD_RELOC_32_PCREL: |
7361da2c AB |
4226 | case BFD_RELOC_HI16_S_PCREL: |
4227 | case BFD_RELOC_LO16_PCREL: | |
b47468a6 CM |
4228 | return HAVE_64BIT_ADDRESSES; |
4229 | ||
2de39019 CM |
4230 | default: |
4231 | return FALSE; | |
4232 | } | |
4233 | } | |
b47468a6 | 4234 | |
5919d012 | 4235 | /* Return true if the given relocation might need a matching %lo(). |
0a44bf69 RS |
4236 | This is only "might" because SVR4 R_MIPS_GOT16 relocations only |
4237 | need a matching %lo() when applied to local symbols. */ | |
5919d012 RS |
4238 | |
4239 | static inline bfd_boolean | |
17a2f251 | 4240 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 4241 | { |
3b91255e | 4242 | return (HAVE_IN_PLACE_ADDENDS |
738e5348 | 4243 | && (hi16_reloc_p (reloc) |
0a44bf69 RS |
4244 | /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo(); |
4245 | all GOT16 relocations evaluate to "G". */ | |
738e5348 RS |
4246 | || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC))); |
4247 | } | |
4248 | ||
4249 | /* Return the type of %lo() reloc needed by RELOC, given that | |
4250 | reloc_needs_lo_p. */ | |
4251 | ||
4252 | static inline bfd_reloc_code_real_type | |
4253 | matching_lo_reloc (bfd_reloc_code_real_type reloc) | |
4254 | { | |
df58fc94 RS |
4255 | return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 |
4256 | : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16 | |
4257 | : BFD_RELOC_LO16)); | |
5919d012 RS |
4258 | } |
4259 | ||
4260 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
4261 | relocation. */ | |
4262 | ||
4263 | static inline bfd_boolean | |
17a2f251 | 4264 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
4265 | { |
4266 | return (fixp->fx_next != NULL | |
738e5348 | 4267 | && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type) |
5919d012 RS |
4268 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
4269 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
4270 | } | |
4271 | ||
462427c4 RS |
4272 | /* Move all labels in LABELS to the current insertion point. TEXT_P |
4273 | says whether the labels refer to text or data. */ | |
404a8071 RS |
4274 | |
4275 | static void | |
462427c4 | 4276 | mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p) |
404a8071 RS |
4277 | { |
4278 | struct insn_label_list *l; | |
4279 | valueT val; | |
4280 | ||
462427c4 | 4281 | for (l = labels; l != NULL; l = l->next) |
404a8071 | 4282 | { |
9c2799c2 | 4283 | gas_assert (S_GET_SEGMENT (l->label) == now_seg); |
404a8071 RS |
4284 | symbol_set_frag (l->label, frag_now); |
4285 | val = (valueT) frag_now_fix (); | |
df58fc94 | 4286 | /* MIPS16/microMIPS text labels are stored as odd. */ |
462427c4 | 4287 | if (text_p && HAVE_CODE_COMPRESSION) |
404a8071 RS |
4288 | ++val; |
4289 | S_SET_VALUE (l->label, val); | |
4290 | } | |
4291 | } | |
4292 | ||
462427c4 RS |
4293 | /* Move all labels in insn_labels to the current insertion point |
4294 | and treat them as text labels. */ | |
4295 | ||
4296 | static void | |
4297 | mips_move_text_labels (void) | |
4298 | { | |
4299 | mips_move_labels (seg_info (now_seg)->label_list, TRUE); | |
4300 | } | |
4301 | ||
9e009953 MR |
4302 | /* Duplicate the test for LINK_ONCE sections as in `adjust_reloc_syms'. */ |
4303 | ||
5f0fe04b TS |
4304 | static bfd_boolean |
4305 | s_is_linkonce (symbolS *sym, segT from_seg) | |
4306 | { | |
4307 | bfd_boolean linkonce = FALSE; | |
4308 | segT symseg = S_GET_SEGMENT (sym); | |
4309 | ||
4310 | if (symseg != from_seg && !S_IS_LOCAL (sym)) | |
4311 | { | |
4312 | if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE)) | |
4313 | linkonce = TRUE; | |
5f0fe04b TS |
4314 | /* The GNU toolchain uses an extension for ELF: a section |
4315 | beginning with the magic string .gnu.linkonce is a | |
4316 | linkonce section. */ | |
4317 | if (strncmp (segment_name (symseg), ".gnu.linkonce", | |
4318 | sizeof ".gnu.linkonce" - 1) == 0) | |
4319 | linkonce = TRUE; | |
5f0fe04b TS |
4320 | } |
4321 | return linkonce; | |
4322 | } | |
4323 | ||
e1b47bd5 | 4324 | /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the |
df58fc94 RS |
4325 | linker to handle them specially, such as generating jalx instructions |
4326 | when needed. We also make them odd for the duration of the assembly, | |
4327 | in order to generate the right sort of code. We will make them even | |
252b5132 RH |
4328 | in the adjust_symtab routine, while leaving them marked. This is |
4329 | convenient for the debugger and the disassembler. The linker knows | |
4330 | to make them odd again. */ | |
4331 | ||
4332 | static void | |
e1b47bd5 | 4333 | mips_compressed_mark_label (symbolS *label) |
252b5132 | 4334 | { |
df58fc94 | 4335 | gas_assert (HAVE_CODE_COMPRESSION); |
a8dbcb85 | 4336 | |
f3ded42a RS |
4337 | if (mips_opts.mips16) |
4338 | S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label))); | |
4339 | else | |
4340 | S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label))); | |
e1b47bd5 RS |
4341 | if ((S_GET_VALUE (label) & 1) == 0 |
4342 | /* Don't adjust the address if the label is global or weak, or | |
4343 | in a link-once section, since we'll be emitting symbol reloc | |
4344 | references to it which will be patched up by the linker, and | |
4345 | the final value of the symbol may or may not be MIPS16/microMIPS. */ | |
4346 | && !S_IS_WEAK (label) | |
4347 | && !S_IS_EXTERNAL (label) | |
4348 | && !s_is_linkonce (label, now_seg)) | |
4349 | S_SET_VALUE (label, S_GET_VALUE (label) | 1); | |
4350 | } | |
4351 | ||
4352 | /* Mark preceding MIPS16 or microMIPS instruction labels. */ | |
4353 | ||
4354 | static void | |
4355 | mips_compressed_mark_labels (void) | |
4356 | { | |
4357 | struct insn_label_list *l; | |
4358 | ||
4359 | for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next) | |
4360 | mips_compressed_mark_label (l->label); | |
252b5132 RH |
4361 | } |
4362 | ||
4d7206a2 RS |
4363 | /* End the current frag. Make it a variant frag and record the |
4364 | relaxation info. */ | |
4365 | ||
4366 | static void | |
4367 | relax_close_frag (void) | |
4368 | { | |
584892a6 | 4369 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 4370 | frag_var (rs_machine_dependent, 0, 0, |
ce8ad872 MR |
4371 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1], |
4372 | mips_pic != NO_PIC), | |
4d7206a2 RS |
4373 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
4374 | ||
4375 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
4376 | mips_relax.first_fixup = 0; | |
4377 | } | |
4378 | ||
4379 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
4380 | See the comment above RELAX_ENCODE for more details. */ | |
4381 | ||
4382 | static void | |
4383 | relax_start (symbolS *symbol) | |
4384 | { | |
9c2799c2 | 4385 | gas_assert (mips_relax.sequence == 0); |
4d7206a2 RS |
4386 | mips_relax.sequence = 1; |
4387 | mips_relax.symbol = symbol; | |
4388 | } | |
4389 | ||
4390 | /* Start generating the second version of a relaxable sequence. | |
4391 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
4392 | |
4393 | static void | |
4d7206a2 RS |
4394 | relax_switch (void) |
4395 | { | |
9c2799c2 | 4396 | gas_assert (mips_relax.sequence == 1); |
4d7206a2 RS |
4397 | mips_relax.sequence = 2; |
4398 | } | |
4399 | ||
4400 | /* End the current relaxable sequence. */ | |
4401 | ||
4402 | static void | |
4403 | relax_end (void) | |
4404 | { | |
9c2799c2 | 4405 | gas_assert (mips_relax.sequence == 2); |
4d7206a2 RS |
4406 | relax_close_frag (); |
4407 | mips_relax.sequence = 0; | |
4408 | } | |
4409 | ||
11625dd8 RS |
4410 | /* Return true if IP is a delayed branch or jump. */ |
4411 | ||
4412 | static inline bfd_boolean | |
4413 | delayed_branch_p (const struct mips_cl_insn *ip) | |
4414 | { | |
4415 | return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY | |
4416 | | INSN_COND_BRANCH_DELAY | |
4417 | | INSN_COND_BRANCH_LIKELY)) != 0; | |
4418 | } | |
4419 | ||
4420 | /* Return true if IP is a compact branch or jump. */ | |
4421 | ||
4422 | static inline bfd_boolean | |
4423 | compact_branch_p (const struct mips_cl_insn *ip) | |
4424 | { | |
26545944 RS |
4425 | return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH |
4426 | | INSN2_COND_BRANCH)) != 0; | |
11625dd8 RS |
4427 | } |
4428 | ||
4429 | /* Return true if IP is an unconditional branch or jump. */ | |
4430 | ||
4431 | static inline bfd_boolean | |
4432 | uncond_branch_p (const struct mips_cl_insn *ip) | |
4433 | { | |
4434 | return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0 | |
26545944 | 4435 | || (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0); |
11625dd8 RS |
4436 | } |
4437 | ||
4438 | /* Return true if IP is a branch-likely instruction. */ | |
4439 | ||
4440 | static inline bfd_boolean | |
4441 | branch_likely_p (const struct mips_cl_insn *ip) | |
4442 | { | |
4443 | return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0; | |
4444 | } | |
4445 | ||
14fe068b RS |
4446 | /* Return the type of nop that should be used to fill the delay slot |
4447 | of delayed branch IP. */ | |
4448 | ||
4449 | static struct mips_cl_insn * | |
4450 | get_delay_slot_nop (const struct mips_cl_insn *ip) | |
4451 | { | |
4452 | if (mips_opts.micromips | |
4453 | && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
4454 | return µmips_nop32_insn; | |
4455 | return NOP_INSN; | |
4456 | } | |
4457 | ||
fc76e730 RS |
4458 | /* Return a mask that has bit N set if OPCODE reads the register(s) |
4459 | in operand N. */ | |
df58fc94 RS |
4460 | |
4461 | static unsigned int | |
fc76e730 | 4462 | insn_read_mask (const struct mips_opcode *opcode) |
df58fc94 | 4463 | { |
fc76e730 RS |
4464 | return (opcode->pinfo & INSN_READ_ALL) >> INSN_READ_SHIFT; |
4465 | } | |
df58fc94 | 4466 | |
fc76e730 RS |
4467 | /* Return a mask that has bit N set if OPCODE writes to the register(s) |
4468 | in operand N. */ | |
4469 | ||
4470 | static unsigned int | |
4471 | insn_write_mask (const struct mips_opcode *opcode) | |
4472 | { | |
4473 | return (opcode->pinfo & INSN_WRITE_ALL) >> INSN_WRITE_SHIFT; | |
4474 | } | |
4475 | ||
4476 | /* Return a mask of the registers specified by operand OPERAND of INSN. | |
4477 | Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK | |
4478 | is set. */ | |
4479 | ||
4480 | static unsigned int | |
4481 | operand_reg_mask (const struct mips_cl_insn *insn, | |
4482 | const struct mips_operand *operand, | |
4483 | unsigned int type_mask) | |
4484 | { | |
4485 | unsigned int uval, vsel; | |
4486 | ||
4487 | switch (operand->type) | |
df58fc94 | 4488 | { |
fc76e730 RS |
4489 | case OP_INT: |
4490 | case OP_MAPPED_INT: | |
4491 | case OP_MSB: | |
4492 | case OP_PCREL: | |
4493 | case OP_PERF_REG: | |
4494 | case OP_ADDIUSP_INT: | |
4495 | case OP_ENTRY_EXIT_LIST: | |
4496 | case OP_REPEAT_DEST_REG: | |
4497 | case OP_REPEAT_PREV_REG: | |
4498 | case OP_PC: | |
14daeee3 RS |
4499 | case OP_VU0_SUFFIX: |
4500 | case OP_VU0_MATCH_SUFFIX: | |
56d438b1 | 4501 | case OP_IMM_INDEX: |
fc76e730 RS |
4502 | abort (); |
4503 | ||
4504 | case OP_REG: | |
0f35dbc4 | 4505 | case OP_OPTIONAL_REG: |
fc76e730 RS |
4506 | { |
4507 | const struct mips_reg_operand *reg_op; | |
4508 | ||
4509 | reg_op = (const struct mips_reg_operand *) operand; | |
4510 | if (!(type_mask & (1 << reg_op->reg_type))) | |
4511 | return 0; | |
4512 | uval = insn_extract_operand (insn, operand); | |
4513 | return 1 << mips_decode_reg_operand (reg_op, uval); | |
4514 | } | |
4515 | ||
4516 | case OP_REG_PAIR: | |
4517 | { | |
4518 | const struct mips_reg_pair_operand *pair_op; | |
4519 | ||
4520 | pair_op = (const struct mips_reg_pair_operand *) operand; | |
4521 | if (!(type_mask & (1 << pair_op->reg_type))) | |
4522 | return 0; | |
4523 | uval = insn_extract_operand (insn, operand); | |
4524 | return (1 << pair_op->reg1_map[uval]) | (1 << pair_op->reg2_map[uval]); | |
4525 | } | |
4526 | ||
4527 | case OP_CLO_CLZ_DEST: | |
4528 | if (!(type_mask & (1 << OP_REG_GP))) | |
4529 | return 0; | |
4530 | uval = insn_extract_operand (insn, operand); | |
4531 | return (1 << (uval & 31)) | (1 << (uval >> 5)); | |
4532 | ||
7361da2c AB |
4533 | case OP_SAME_RS_RT: |
4534 | if (!(type_mask & (1 << OP_REG_GP))) | |
4535 | return 0; | |
4536 | uval = insn_extract_operand (insn, operand); | |
4537 | gas_assert ((uval & 31) == (uval >> 5)); | |
4538 | return 1 << (uval & 31); | |
4539 | ||
4540 | case OP_CHECK_PREV: | |
4541 | case OP_NON_ZERO_REG: | |
4542 | if (!(type_mask & (1 << OP_REG_GP))) | |
4543 | return 0; | |
4544 | uval = insn_extract_operand (insn, operand); | |
4545 | return 1 << (uval & 31); | |
4546 | ||
fc76e730 RS |
4547 | case OP_LWM_SWM_LIST: |
4548 | abort (); | |
4549 | ||
4550 | case OP_SAVE_RESTORE_LIST: | |
4551 | abort (); | |
4552 | ||
4553 | case OP_MDMX_IMM_REG: | |
4554 | if (!(type_mask & (1 << OP_REG_VEC))) | |
4555 | return 0; | |
4556 | uval = insn_extract_operand (insn, operand); | |
4557 | vsel = uval >> 5; | |
4558 | if ((vsel & 0x18) == 0x18) | |
4559 | return 0; | |
4560 | return 1 << (uval & 31); | |
56d438b1 CF |
4561 | |
4562 | case OP_REG_INDEX: | |
4563 | if (!(type_mask & (1 << OP_REG_GP))) | |
4564 | return 0; | |
4565 | return 1 << insn_extract_operand (insn, operand); | |
df58fc94 | 4566 | } |
fc76e730 RS |
4567 | abort (); |
4568 | } | |
4569 | ||
4570 | /* Return a mask of the registers specified by operands OPNO_MASK of INSN, | |
4571 | where bit N of OPNO_MASK is set if operand N should be included. | |
4572 | Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK | |
4573 | is set. */ | |
4574 | ||
4575 | static unsigned int | |
4576 | insn_reg_mask (const struct mips_cl_insn *insn, | |
4577 | unsigned int type_mask, unsigned int opno_mask) | |
4578 | { | |
4579 | unsigned int opno, reg_mask; | |
4580 | ||
4581 | opno = 0; | |
4582 | reg_mask = 0; | |
4583 | while (opno_mask != 0) | |
4584 | { | |
4585 | if (opno_mask & 1) | |
4586 | reg_mask |= operand_reg_mask (insn, insn_opno (insn, opno), type_mask); | |
4587 | opno_mask >>= 1; | |
4588 | opno += 1; | |
4589 | } | |
4590 | return reg_mask; | |
df58fc94 RS |
4591 | } |
4592 | ||
4c260379 RS |
4593 | /* Return the mask of core registers that IP reads. */ |
4594 | ||
4595 | static unsigned int | |
4596 | gpr_read_mask (const struct mips_cl_insn *ip) | |
4597 | { | |
4598 | unsigned long pinfo, pinfo2; | |
4599 | unsigned int mask; | |
4600 | ||
fc76e730 | 4601 | mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_read_mask (ip->insn_mo)); |
4c260379 RS |
4602 | pinfo = ip->insn_mo->pinfo; |
4603 | pinfo2 = ip->insn_mo->pinfo2; | |
fc76e730 | 4604 | if (pinfo & INSN_UDI) |
4c260379 | 4605 | { |
fc76e730 RS |
4606 | /* UDI instructions have traditionally been assumed to read RS |
4607 | and RT. */ | |
4608 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); | |
4609 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); | |
4c260379 | 4610 | } |
fc76e730 RS |
4611 | if (pinfo & INSN_READ_GPR_24) |
4612 | mask |= 1 << 24; | |
4613 | if (pinfo2 & INSN2_READ_GPR_16) | |
4614 | mask |= 1 << 16; | |
4615 | if (pinfo2 & INSN2_READ_SP) | |
4616 | mask |= 1 << SP; | |
26545944 | 4617 | if (pinfo2 & INSN2_READ_GPR_31) |
fc76e730 | 4618 | mask |= 1 << 31; |
fe35f09f RS |
4619 | /* Don't include register 0. */ |
4620 | return mask & ~1; | |
4c260379 RS |
4621 | } |
4622 | ||
4623 | /* Return the mask of core registers that IP writes. */ | |
4624 | ||
4625 | static unsigned int | |
4626 | gpr_write_mask (const struct mips_cl_insn *ip) | |
4627 | { | |
4628 | unsigned long pinfo, pinfo2; | |
4629 | unsigned int mask; | |
4630 | ||
fc76e730 | 4631 | mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_write_mask (ip->insn_mo)); |
4c260379 RS |
4632 | pinfo = ip->insn_mo->pinfo; |
4633 | pinfo2 = ip->insn_mo->pinfo2; | |
fc76e730 RS |
4634 | if (pinfo & INSN_WRITE_GPR_24) |
4635 | mask |= 1 << 24; | |
4636 | if (pinfo & INSN_WRITE_GPR_31) | |
4637 | mask |= 1 << 31; | |
4638 | if (pinfo & INSN_UDI) | |
4639 | /* UDI instructions have traditionally been assumed to write to RD. */ | |
4640 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); | |
4641 | if (pinfo2 & INSN2_WRITE_SP) | |
4642 | mask |= 1 << SP; | |
fe35f09f RS |
4643 | /* Don't include register 0. */ |
4644 | return mask & ~1; | |
4c260379 RS |
4645 | } |
4646 | ||
4647 | /* Return the mask of floating-point registers that IP reads. */ | |
4648 | ||
4649 | static unsigned int | |
4650 | fpr_read_mask (const struct mips_cl_insn *ip) | |
4651 | { | |
fc76e730 | 4652 | unsigned long pinfo; |
4c260379 RS |
4653 | unsigned int mask; |
4654 | ||
9d5de888 CF |
4655 | mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC) |
4656 | | (1 << OP_REG_MSA)), | |
fc76e730 | 4657 | insn_read_mask (ip->insn_mo)); |
4c260379 | 4658 | pinfo = ip->insn_mo->pinfo; |
4c260379 RS |
4659 | /* Conservatively treat all operands to an FP_D instruction are doubles. |
4660 | (This is overly pessimistic for things like cvt.d.s.) */ | |
bad1aba3 | 4661 | if (FPR_SIZE != 64 && (pinfo & FP_D)) |
4c260379 RS |
4662 | mask |= mask << 1; |
4663 | return mask; | |
4664 | } | |
4665 | ||
4666 | /* Return the mask of floating-point registers that IP writes. */ | |
4667 | ||
4668 | static unsigned int | |
4669 | fpr_write_mask (const struct mips_cl_insn *ip) | |
4670 | { | |
fc76e730 | 4671 | unsigned long pinfo; |
4c260379 RS |
4672 | unsigned int mask; |
4673 | ||
9d5de888 CF |
4674 | mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC) |
4675 | | (1 << OP_REG_MSA)), | |
fc76e730 | 4676 | insn_write_mask (ip->insn_mo)); |
4c260379 | 4677 | pinfo = ip->insn_mo->pinfo; |
4c260379 RS |
4678 | /* Conservatively treat all operands to an FP_D instruction are doubles. |
4679 | (This is overly pessimistic for things like cvt.s.d.) */ | |
bad1aba3 | 4680 | if (FPR_SIZE != 64 && (pinfo & FP_D)) |
4c260379 RS |
4681 | mask |= mask << 1; |
4682 | return mask; | |
4683 | } | |
4684 | ||
a1d78564 RS |
4685 | /* Operand OPNUM of INSN is an odd-numbered floating-point register. |
4686 | Check whether that is allowed. */ | |
4687 | ||
4688 | static bfd_boolean | |
4689 | mips_oddfpreg_ok (const struct mips_opcode *insn, int opnum) | |
4690 | { | |
4691 | const char *s = insn->name; | |
351cdf24 MF |
4692 | bfd_boolean oddspreg = (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa, mips_opts.arch) |
4693 | || FPR_SIZE == 64) | |
4694 | && mips_opts.oddspreg; | |
a1d78564 RS |
4695 | |
4696 | if (insn->pinfo == INSN_MACRO) | |
4697 | /* Let a macro pass, we'll catch it later when it is expanded. */ | |
4698 | return TRUE; | |
4699 | ||
351cdf24 MF |
4700 | /* Single-precision coprocessor loads and moves are OK for 32-bit registers, |
4701 | otherwise it depends on oddspreg. */ | |
4702 | if ((insn->pinfo & FP_S) | |
4703 | && (insn->pinfo & (INSN_LOAD_MEMORY | INSN_STORE_MEMORY | |
43885403 | 4704 | | INSN_LOAD_COPROC | INSN_COPROC_MOVE))) |
351cdf24 | 4705 | return FPR_SIZE == 32 || oddspreg; |
a1d78564 | 4706 | |
351cdf24 MF |
4707 | /* Allow odd registers for single-precision ops and double-precision if the |
4708 | floating-point registers are 64-bit wide. */ | |
4709 | switch (insn->pinfo & (FP_S | FP_D)) | |
4710 | { | |
4711 | case FP_S: | |
4712 | case 0: | |
4713 | return oddspreg; | |
4714 | case FP_D: | |
4715 | return FPR_SIZE == 64; | |
4716 | default: | |
4717 | break; | |
a1d78564 RS |
4718 | } |
4719 | ||
351cdf24 MF |
4720 | /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ |
4721 | s = strchr (insn->name, '.'); | |
4722 | if (s != NULL && opnum == 2) | |
4723 | s = strchr (s + 1, '.'); | |
4724 | if (s != NULL && (s[1] == 'w' || s[1] == 's')) | |
4725 | return oddspreg; | |
a1d78564 | 4726 | |
351cdf24 | 4727 | return FPR_SIZE == 64; |
a1d78564 RS |
4728 | } |
4729 | ||
a1d78564 RS |
4730 | /* Information about an instruction argument that we're trying to match. */ |
4731 | struct mips_arg_info | |
4732 | { | |
4733 | /* The instruction so far. */ | |
4734 | struct mips_cl_insn *insn; | |
4735 | ||
a92713e6 RS |
4736 | /* The first unconsumed operand token. */ |
4737 | struct mips_operand_token *token; | |
4738 | ||
a1d78564 RS |
4739 | /* The 1-based operand number, in terms of insn->insn_mo->args. */ |
4740 | int opnum; | |
4741 | ||
4742 | /* The 1-based argument number, for error reporting. This does not | |
4743 | count elided optional registers, etc.. */ | |
4744 | int argnum; | |
4745 | ||
4746 | /* The last OP_REG operand seen, or ILLEGAL_REG if none. */ | |
4747 | unsigned int last_regno; | |
4748 | ||
4749 | /* If the first operand was an OP_REG, this is the register that it | |
4750 | specified, otherwise it is ILLEGAL_REG. */ | |
4751 | unsigned int dest_regno; | |
4752 | ||
4753 | /* The value of the last OP_INT operand. Only used for OP_MSB, | |
4754 | where it gives the lsb position. */ | |
4755 | unsigned int last_op_int; | |
4756 | ||
60f20e8b | 4757 | /* If true, match routines should assume that no later instruction |
2b0f3761 | 4758 | alternative matches and should therefore be as accommodating as |
60f20e8b RS |
4759 | possible. Match routines should not report errors if something |
4760 | is only invalid for !LAX_MATCH. */ | |
4761 | bfd_boolean lax_match; | |
a1d78564 | 4762 | |
a1d78564 RS |
4763 | /* True if a reference to the current AT register was seen. */ |
4764 | bfd_boolean seen_at; | |
4765 | }; | |
4766 | ||
1a00e612 RS |
4767 | /* Record that the argument is out of range. */ |
4768 | ||
4769 | static void | |
4770 | match_out_of_range (struct mips_arg_info *arg) | |
4771 | { | |
4772 | set_insn_error_i (arg->argnum, _("operand %d out of range"), arg->argnum); | |
4773 | } | |
4774 | ||
4775 | /* Record that the argument isn't constant but needs to be. */ | |
4776 | ||
4777 | static void | |
4778 | match_not_constant (struct mips_arg_info *arg) | |
4779 | { | |
4780 | set_insn_error_i (arg->argnum, _("operand %d must be constant"), | |
4781 | arg->argnum); | |
4782 | } | |
4783 | ||
a92713e6 RS |
4784 | /* Try to match an OT_CHAR token for character CH. Consume the token |
4785 | and return true on success, otherwise return false. */ | |
a1d78564 | 4786 | |
a92713e6 RS |
4787 | static bfd_boolean |
4788 | match_char (struct mips_arg_info *arg, char ch) | |
a1d78564 | 4789 | { |
a92713e6 RS |
4790 | if (arg->token->type == OT_CHAR && arg->token->u.ch == ch) |
4791 | { | |
4792 | ++arg->token; | |
4793 | if (ch == ',') | |
4794 | arg->argnum += 1; | |
4795 | return TRUE; | |
4796 | } | |
4797 | return FALSE; | |
4798 | } | |
a1d78564 | 4799 | |
a92713e6 RS |
4800 | /* Try to get an expression from the next tokens in ARG. Consume the |
4801 | tokens and return true on success, storing the expression value in | |
4802 | VALUE and relocation types in R. */ | |
4803 | ||
4804 | static bfd_boolean | |
4805 | match_expression (struct mips_arg_info *arg, expressionS *value, | |
4806 | bfd_reloc_code_real_type *r) | |
4807 | { | |
d436c1c2 RS |
4808 | /* If the next token is a '(' that was parsed as being part of a base |
4809 | expression, assume we have an elided offset. The later match will fail | |
4810 | if this turns out to be wrong. */ | |
4811 | if (arg->token->type == OT_CHAR && arg->token->u.ch == '(') | |
a1d78564 | 4812 | { |
d436c1c2 RS |
4813 | value->X_op = O_constant; |
4814 | value->X_add_number = 0; | |
4815 | r[0] = r[1] = r[2] = BFD_RELOC_UNUSED; | |
a92713e6 RS |
4816 | return TRUE; |
4817 | } | |
4818 | ||
d436c1c2 RS |
4819 | /* Reject register-based expressions such as "0+$2" and "(($2))". |
4820 | For plain registers the default error seems more appropriate. */ | |
4821 | if (arg->token->type == OT_INTEGER | |
4822 | && arg->token->u.integer.value.X_op == O_register) | |
a92713e6 | 4823 | { |
d436c1c2 RS |
4824 | set_insn_error (arg->argnum, _("register value used as expression")); |
4825 | return FALSE; | |
a1d78564 | 4826 | } |
d436c1c2 RS |
4827 | |
4828 | if (arg->token->type == OT_INTEGER) | |
a92713e6 | 4829 | { |
d436c1c2 RS |
4830 | *value = arg->token->u.integer.value; |
4831 | memcpy (r, arg->token->u.integer.relocs, 3 * sizeof (*r)); | |
4832 | ++arg->token; | |
4833 | return TRUE; | |
a92713e6 | 4834 | } |
a92713e6 | 4835 | |
d436c1c2 RS |
4836 | set_insn_error_i |
4837 | (arg->argnum, _("operand %d must be an immediate expression"), | |
4838 | arg->argnum); | |
4839 | return FALSE; | |
a92713e6 RS |
4840 | } |
4841 | ||
4842 | /* Try to get a constant expression from the next tokens in ARG. Consume | |
4843 | the tokens and return return true on success, storing the constant value | |
a54d5f8b | 4844 | in *VALUE. */ |
a92713e6 RS |
4845 | |
4846 | static bfd_boolean | |
1a00e612 | 4847 | match_const_int (struct mips_arg_info *arg, offsetT *value) |
a92713e6 RS |
4848 | { |
4849 | expressionS ex; | |
4850 | bfd_reloc_code_real_type r[3]; | |
a1d78564 | 4851 | |
a92713e6 RS |
4852 | if (!match_expression (arg, &ex, r)) |
4853 | return FALSE; | |
4854 | ||
4855 | if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_constant) | |
a1d78564 RS |
4856 | *value = ex.X_add_number; |
4857 | else | |
4858 | { | |
c96425c5 MR |
4859 | if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_big) |
4860 | match_out_of_range (arg); | |
4861 | else | |
4862 | match_not_constant (arg); | |
1a00e612 | 4863 | return FALSE; |
a1d78564 | 4864 | } |
a92713e6 | 4865 | return TRUE; |
a1d78564 RS |
4866 | } |
4867 | ||
4868 | /* Return the RTYPE_* flags for a register operand of type TYPE that | |
4869 | appears in instruction OPCODE. */ | |
4870 | ||
4871 | static unsigned int | |
4872 | convert_reg_type (const struct mips_opcode *opcode, | |
4873 | enum mips_reg_operand_type type) | |
4874 | { | |
4875 | switch (type) | |
4876 | { | |
4877 | case OP_REG_GP: | |
4878 | return RTYPE_NUM | RTYPE_GP; | |
4879 | ||
4880 | case OP_REG_FP: | |
4881 | /* Allow vector register names for MDMX if the instruction is a 64-bit | |
4882 | FPR load, store or move (including moves to and from GPRs). */ | |
4883 | if ((mips_opts.ase & ASE_MDMX) | |
4884 | && (opcode->pinfo & FP_D) | |
43885403 | 4885 | && (opcode->pinfo & (INSN_COPROC_MOVE |
a1d78564 | 4886 | | INSN_COPROC_MEMORY_DELAY |
43885403 | 4887 | | INSN_LOAD_COPROC |
67dc82bc | 4888 | | INSN_LOAD_MEMORY |
a1d78564 RS |
4889 | | INSN_STORE_MEMORY))) |
4890 | return RTYPE_FPU | RTYPE_VEC; | |
4891 | return RTYPE_FPU; | |
4892 | ||
4893 | case OP_REG_CCC: | |
4894 | if (opcode->pinfo & (FP_D | FP_S)) | |
4895 | return RTYPE_CCC | RTYPE_FCC; | |
4896 | return RTYPE_CCC; | |
4897 | ||
4898 | case OP_REG_VEC: | |
4899 | if (opcode->membership & INSN_5400) | |
4900 | return RTYPE_FPU; | |
4901 | return RTYPE_FPU | RTYPE_VEC; | |
4902 | ||
4903 | case OP_REG_ACC: | |
4904 | return RTYPE_ACC; | |
4905 | ||
4906 | case OP_REG_COPRO: | |
4907 | if (opcode->name[strlen (opcode->name) - 1] == '0') | |
4908 | return RTYPE_NUM | RTYPE_CP0; | |
4909 | return RTYPE_NUM; | |
4910 | ||
4911 | case OP_REG_HW: | |
4912 | return RTYPE_NUM; | |
14daeee3 RS |
4913 | |
4914 | case OP_REG_VI: | |
4915 | return RTYPE_NUM | RTYPE_VI; | |
4916 | ||
4917 | case OP_REG_VF: | |
4918 | return RTYPE_NUM | RTYPE_VF; | |
4919 | ||
4920 | case OP_REG_R5900_I: | |
4921 | return RTYPE_R5900_I; | |
4922 | ||
4923 | case OP_REG_R5900_Q: | |
4924 | return RTYPE_R5900_Q; | |
4925 | ||
4926 | case OP_REG_R5900_R: | |
4927 | return RTYPE_R5900_R; | |
4928 | ||
4929 | case OP_REG_R5900_ACC: | |
4930 | return RTYPE_R5900_ACC; | |
56d438b1 CF |
4931 | |
4932 | case OP_REG_MSA: | |
4933 | return RTYPE_MSA; | |
4934 | ||
4935 | case OP_REG_MSA_CTRL: | |
4936 | return RTYPE_NUM; | |
a1d78564 RS |
4937 | } |
4938 | abort (); | |
4939 | } | |
4940 | ||
4941 | /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */ | |
4942 | ||
4943 | static void | |
4944 | check_regno (struct mips_arg_info *arg, | |
4945 | enum mips_reg_operand_type type, unsigned int regno) | |
4946 | { | |
4947 | if (AT && type == OP_REG_GP && regno == AT) | |
4948 | arg->seen_at = TRUE; | |
4949 | ||
4950 | if (type == OP_REG_FP | |
4951 | && (regno & 1) != 0 | |
a1d78564 | 4952 | && !mips_oddfpreg_ok (arg->insn->insn_mo, arg->opnum)) |
351cdf24 MF |
4953 | { |
4954 | /* This was a warning prior to introducing O32 FPXX and FP64 support | |
4955 | so maintain a warning for FP32 but raise an error for the new | |
4956 | cases. */ | |
4957 | if (FPR_SIZE == 32) | |
4958 | as_warn (_("float register should be even, was %d"), regno); | |
4959 | else | |
4960 | as_bad (_("float register should be even, was %d"), regno); | |
4961 | } | |
a1d78564 RS |
4962 | |
4963 | if (type == OP_REG_CCC) | |
4964 | { | |
4965 | const char *name; | |
4966 | size_t length; | |
4967 | ||
4968 | name = arg->insn->insn_mo->name; | |
4969 | length = strlen (name); | |
4970 | if ((regno & 1) != 0 | |
4971 | && ((length >= 3 && strcmp (name + length - 3, ".ps") == 0) | |
4972 | || (length >= 5 && strncmp (name + length - 5, "any2", 4) == 0))) | |
1661c76c | 4973 | as_warn (_("condition code register should be even for %s, was %d"), |
a1d78564 RS |
4974 | name, regno); |
4975 | ||
4976 | if ((regno & 3) != 0 | |
4977 | && (length >= 5 && strncmp (name + length - 5, "any4", 4) == 0)) | |
1661c76c | 4978 | as_warn (_("condition code register should be 0 or 4 for %s, was %d"), |
a1d78564 RS |
4979 | name, regno); |
4980 | } | |
4981 | } | |
4982 | ||
a92713e6 RS |
4983 | /* ARG is a register with symbol value SYMVAL. Try to interpret it as |
4984 | a register of type TYPE. Return true on success, storing the register | |
4985 | number in *REGNO and warning about any dubious uses. */ | |
4986 | ||
4987 | static bfd_boolean | |
4988 | match_regno (struct mips_arg_info *arg, enum mips_reg_operand_type type, | |
4989 | unsigned int symval, unsigned int *regno) | |
4990 | { | |
4991 | if (type == OP_REG_VEC) | |
4992 | symval = mips_prefer_vec_regno (symval); | |
4993 | if (!(symval & convert_reg_type (arg->insn->insn_mo, type))) | |
4994 | return FALSE; | |
4995 | ||
4996 | *regno = symval & RNUM_MASK; | |
4997 | check_regno (arg, type, *regno); | |
4998 | return TRUE; | |
4999 | } | |
5000 | ||
5001 | /* Try to interpret the next token in ARG as a register of type TYPE. | |
5002 | Consume the token and return true on success, storing the register | |
5003 | number in *REGNO. Return false on failure. */ | |
5004 | ||
5005 | static bfd_boolean | |
5006 | match_reg (struct mips_arg_info *arg, enum mips_reg_operand_type type, | |
5007 | unsigned int *regno) | |
5008 | { | |
5009 | if (arg->token->type == OT_REG | |
5010 | && match_regno (arg, type, arg->token->u.regno, regno)) | |
5011 | { | |
5012 | ++arg->token; | |
5013 | return TRUE; | |
5014 | } | |
5015 | return FALSE; | |
5016 | } | |
5017 | ||
5018 | /* Try to interpret the next token in ARG as a range of registers of type TYPE. | |
5019 | Consume the token and return true on success, storing the register numbers | |
5020 | in *REGNO1 and *REGNO2. Return false on failure. */ | |
5021 | ||
5022 | static bfd_boolean | |
5023 | match_reg_range (struct mips_arg_info *arg, enum mips_reg_operand_type type, | |
5024 | unsigned int *regno1, unsigned int *regno2) | |
5025 | { | |
5026 | if (match_reg (arg, type, regno1)) | |
5027 | { | |
5028 | *regno2 = *regno1; | |
5029 | return TRUE; | |
5030 | } | |
5031 | if (arg->token->type == OT_REG_RANGE | |
5032 | && match_regno (arg, type, arg->token->u.reg_range.regno1, regno1) | |
5033 | && match_regno (arg, type, arg->token->u.reg_range.regno2, regno2) | |
5034 | && *regno1 <= *regno2) | |
5035 | { | |
5036 | ++arg->token; | |
5037 | return TRUE; | |
5038 | } | |
5039 | return FALSE; | |
5040 | } | |
5041 | ||
a1d78564 RS |
5042 | /* OP_INT matcher. */ |
5043 | ||
a92713e6 | 5044 | static bfd_boolean |
a1d78564 | 5045 | match_int_operand (struct mips_arg_info *arg, |
a92713e6 | 5046 | const struct mips_operand *operand_base) |
a1d78564 RS |
5047 | { |
5048 | const struct mips_int_operand *operand; | |
3ccad066 | 5049 | unsigned int uval; |
a1d78564 RS |
5050 | int min_val, max_val, factor; |
5051 | offsetT sval; | |
a1d78564 RS |
5052 | |
5053 | operand = (const struct mips_int_operand *) operand_base; | |
5054 | factor = 1 << operand->shift; | |
3ccad066 RS |
5055 | min_val = mips_int_operand_min (operand); |
5056 | max_val = mips_int_operand_max (operand); | |
a1d78564 | 5057 | |
d436c1c2 RS |
5058 | if (operand_base->lsb == 0 |
5059 | && operand_base->size == 16 | |
5060 | && operand->shift == 0 | |
5061 | && operand->bias == 0 | |
5062 | && (operand->max_val == 32767 || operand->max_val == 65535)) | |
a1d78564 RS |
5063 | { |
5064 | /* The operand can be relocated. */ | |
a92713e6 RS |
5065 | if (!match_expression (arg, &offset_expr, offset_reloc)) |
5066 | return FALSE; | |
5067 | ||
c96425c5 MR |
5068 | if (offset_expr.X_op == O_big) |
5069 | { | |
5070 | match_out_of_range (arg); | |
5071 | return FALSE; | |
5072 | } | |
5073 | ||
a92713e6 | 5074 | if (offset_reloc[0] != BFD_RELOC_UNUSED) |
33eaf5de | 5075 | /* Relocation operators were used. Accept the argument and |
a1d78564 RS |
5076 | leave the relocation value in offset_expr and offset_relocs |
5077 | for the caller to process. */ | |
a92713e6 RS |
5078 | return TRUE; |
5079 | ||
5080 | if (offset_expr.X_op != O_constant) | |
a1d78564 | 5081 | { |
60f20e8b RS |
5082 | /* Accept non-constant operands if no later alternative matches, |
5083 | leaving it for the caller to process. */ | |
5084 | if (!arg->lax_match) | |
602b88e3 MR |
5085 | { |
5086 | match_not_constant (arg); | |
5087 | return FALSE; | |
5088 | } | |
a92713e6 RS |
5089 | offset_reloc[0] = BFD_RELOC_LO16; |
5090 | return TRUE; | |
a1d78564 | 5091 | } |
a92713e6 | 5092 | |
a1d78564 RS |
5093 | /* Clear the global state; we're going to install the operand |
5094 | ourselves. */ | |
a92713e6 | 5095 | sval = offset_expr.X_add_number; |
a1d78564 | 5096 | offset_expr.X_op = O_absent; |
60f20e8b RS |
5097 | |
5098 | /* For compatibility with older assemblers, we accept | |
5099 | 0x8000-0xffff as signed 16-bit numbers when only | |
5100 | signed numbers are allowed. */ | |
5101 | if (sval > max_val) | |
5102 | { | |
5103 | max_val = ((1 << operand_base->size) - 1) << operand->shift; | |
5104 | if (!arg->lax_match && sval <= max_val) | |
5105 | return FALSE; | |
5106 | } | |
a1d78564 RS |
5107 | } |
5108 | else | |
5109 | { | |
1a00e612 | 5110 | if (!match_const_int (arg, &sval)) |
a92713e6 | 5111 | return FALSE; |
a1d78564 RS |
5112 | } |
5113 | ||
5114 | arg->last_op_int = sval; | |
5115 | ||
1a00e612 | 5116 | if (sval < min_val || sval > max_val || sval % factor) |
a1d78564 | 5117 | { |
1a00e612 RS |
5118 | match_out_of_range (arg); |
5119 | return FALSE; | |
a1d78564 RS |
5120 | } |
5121 | ||
5122 | uval = (unsigned int) sval >> operand->shift; | |
5123 | uval -= operand->bias; | |
5124 | ||
5125 | /* Handle -mfix-cn63xxp1. */ | |
5126 | if (arg->opnum == 1 | |
5127 | && mips_fix_cn63xxp1 | |
5128 | && !mips_opts.micromips | |
5129 | && strcmp ("pref", arg->insn->insn_mo->name) == 0) | |
5130 | switch (uval) | |
5131 | { | |
5132 | case 5: | |
5133 | case 25: | |
5134 | case 26: | |
5135 | case 27: | |
5136 | case 28: | |
5137 | case 29: | |
5138 | case 30: | |
5139 | case 31: | |
5140 | /* These are ok. */ | |
5141 | break; | |
5142 | ||
5143 | default: | |
5144 | /* The rest must be changed to 28. */ | |
5145 | uval = 28; | |
5146 | break; | |
5147 | } | |
5148 | ||
5149 | insn_insert_operand (arg->insn, operand_base, uval); | |
a92713e6 | 5150 | return TRUE; |
a1d78564 RS |
5151 | } |
5152 | ||
5153 | /* OP_MAPPED_INT matcher. */ | |
5154 | ||
a92713e6 | 5155 | static bfd_boolean |
a1d78564 | 5156 | match_mapped_int_operand (struct mips_arg_info *arg, |
a92713e6 | 5157 | const struct mips_operand *operand_base) |
a1d78564 RS |
5158 | { |
5159 | const struct mips_mapped_int_operand *operand; | |
5160 | unsigned int uval, num_vals; | |
5161 | offsetT sval; | |
5162 | ||
5163 | operand = (const struct mips_mapped_int_operand *) operand_base; | |
1a00e612 | 5164 | if (!match_const_int (arg, &sval)) |
a92713e6 | 5165 | return FALSE; |
a1d78564 RS |
5166 | |
5167 | num_vals = 1 << operand_base->size; | |
5168 | for (uval = 0; uval < num_vals; uval++) | |
5169 | if (operand->int_map[uval] == sval) | |
5170 | break; | |
5171 | if (uval == num_vals) | |
1a00e612 RS |
5172 | { |
5173 | match_out_of_range (arg); | |
5174 | return FALSE; | |
5175 | } | |
a1d78564 RS |
5176 | |
5177 | insn_insert_operand (arg->insn, operand_base, uval); | |
a92713e6 | 5178 | return TRUE; |
a1d78564 RS |
5179 | } |
5180 | ||
5181 | /* OP_MSB matcher. */ | |
5182 | ||
a92713e6 | 5183 | static bfd_boolean |
a1d78564 | 5184 | match_msb_operand (struct mips_arg_info *arg, |
a92713e6 | 5185 | const struct mips_operand *operand_base) |
a1d78564 RS |
5186 | { |
5187 | const struct mips_msb_operand *operand; | |
5188 | int min_val, max_val, max_high; | |
5189 | offsetT size, sval, high; | |
5190 | ||
5191 | operand = (const struct mips_msb_operand *) operand_base; | |
5192 | min_val = operand->bias; | |
5193 | max_val = min_val + (1 << operand_base->size) - 1; | |
5194 | max_high = operand->opsize; | |
5195 | ||
1a00e612 | 5196 | if (!match_const_int (arg, &size)) |
a92713e6 | 5197 | return FALSE; |
a1d78564 RS |
5198 | |
5199 | high = size + arg->last_op_int; | |
5200 | sval = operand->add_lsb ? high : size; | |
5201 | ||
5202 | if (size < 0 || high > max_high || sval < min_val || sval > max_val) | |
5203 | { | |
1a00e612 RS |
5204 | match_out_of_range (arg); |
5205 | return FALSE; | |
a1d78564 RS |
5206 | } |
5207 | insn_insert_operand (arg->insn, operand_base, sval - min_val); | |
a92713e6 | 5208 | return TRUE; |
a1d78564 RS |
5209 | } |
5210 | ||
5211 | /* OP_REG matcher. */ | |
5212 | ||
a92713e6 | 5213 | static bfd_boolean |
a1d78564 | 5214 | match_reg_operand (struct mips_arg_info *arg, |
a92713e6 | 5215 | const struct mips_operand *operand_base) |
a1d78564 RS |
5216 | { |
5217 | const struct mips_reg_operand *operand; | |
a92713e6 | 5218 | unsigned int regno, uval, num_vals; |
a1d78564 RS |
5219 | |
5220 | operand = (const struct mips_reg_operand *) operand_base; | |
a92713e6 RS |
5221 | if (!match_reg (arg, operand->reg_type, ®no)) |
5222 | return FALSE; | |
a1d78564 RS |
5223 | |
5224 | if (operand->reg_map) | |
5225 | { | |
5226 | num_vals = 1 << operand->root.size; | |
5227 | for (uval = 0; uval < num_vals; uval++) | |
5228 | if (operand->reg_map[uval] == regno) | |
5229 | break; | |
5230 | if (num_vals == uval) | |
a92713e6 | 5231 | return FALSE; |
a1d78564 RS |
5232 | } |
5233 | else | |
5234 | uval = regno; | |
5235 | ||
a1d78564 RS |
5236 | arg->last_regno = regno; |
5237 | if (arg->opnum == 1) | |
5238 | arg->dest_regno = regno; | |
5239 | insn_insert_operand (arg->insn, operand_base, uval); | |
a92713e6 | 5240 | return TRUE; |
a1d78564 RS |
5241 | } |
5242 | ||
5243 | /* OP_REG_PAIR matcher. */ | |
5244 | ||
a92713e6 | 5245 | static bfd_boolean |
a1d78564 | 5246 | match_reg_pair_operand (struct mips_arg_info *arg, |
a92713e6 | 5247 | const struct mips_operand *operand_base) |
a1d78564 RS |
5248 | { |
5249 | const struct mips_reg_pair_operand *operand; | |
a92713e6 | 5250 | unsigned int regno1, regno2, uval, num_vals; |
a1d78564 RS |
5251 | |
5252 | operand = (const struct mips_reg_pair_operand *) operand_base; | |
a92713e6 RS |
5253 | if (!match_reg (arg, operand->reg_type, ®no1) |
5254 | || !match_char (arg, ',') | |
5255 | || !match_reg (arg, operand->reg_type, ®no2)) | |
5256 | return FALSE; | |
a1d78564 RS |
5257 | |
5258 | num_vals = 1 << operand_base->size; | |
5259 | for (uval = 0; uval < num_vals; uval++) | |
5260 | if (operand->reg1_map[uval] == regno1 && operand->reg2_map[uval] == regno2) | |
5261 | break; | |
5262 | if (uval == num_vals) | |
a92713e6 | 5263 | return FALSE; |
a1d78564 | 5264 | |
a1d78564 | 5265 | insn_insert_operand (arg->insn, operand_base, uval); |
a92713e6 | 5266 | return TRUE; |
a1d78564 RS |
5267 | } |
5268 | ||
5269 | /* OP_PCREL matcher. The caller chooses the relocation type. */ | |
5270 | ||
a92713e6 RS |
5271 | static bfd_boolean |
5272 | match_pcrel_operand (struct mips_arg_info *arg) | |
a1d78564 | 5273 | { |
a92713e6 RS |
5274 | bfd_reloc_code_real_type r[3]; |
5275 | ||
5276 | return match_expression (arg, &offset_expr, r) && r[0] == BFD_RELOC_UNUSED; | |
a1d78564 RS |
5277 | } |
5278 | ||
5279 | /* OP_PERF_REG matcher. */ | |
5280 | ||
a92713e6 | 5281 | static bfd_boolean |
a1d78564 | 5282 | match_perf_reg_operand (struct mips_arg_info *arg, |
a92713e6 | 5283 | const struct mips_operand *operand) |
a1d78564 RS |
5284 | { |
5285 | offsetT sval; | |
5286 | ||
1a00e612 | 5287 | if (!match_const_int (arg, &sval)) |
a92713e6 | 5288 | return FALSE; |
a1d78564 RS |
5289 | |
5290 | if (sval != 0 | |
5291 | && (sval != 1 | |
5292 | || (mips_opts.arch == CPU_R5900 | |
5293 | && (strcmp (arg->insn->insn_mo->name, "mfps") == 0 | |
5294 | || strcmp (arg->insn->insn_mo->name, "mtps") == 0)))) | |
5295 | { | |
1a00e612 RS |
5296 | set_insn_error (arg->argnum, _("invalid performance register")); |
5297 | return FALSE; | |
a1d78564 RS |
5298 | } |
5299 | ||
5300 | insn_insert_operand (arg->insn, operand, sval); | |
a92713e6 | 5301 | return TRUE; |
a1d78564 RS |
5302 | } |
5303 | ||
5304 | /* OP_ADDIUSP matcher. */ | |
5305 | ||
a92713e6 | 5306 | static bfd_boolean |
a1d78564 | 5307 | match_addiusp_operand (struct mips_arg_info *arg, |
a92713e6 | 5308 | const struct mips_operand *operand) |
a1d78564 RS |
5309 | { |
5310 | offsetT sval; | |
5311 | unsigned int uval; | |
5312 | ||
1a00e612 | 5313 | if (!match_const_int (arg, &sval)) |
a92713e6 | 5314 | return FALSE; |
a1d78564 RS |
5315 | |
5316 | if (sval % 4) | |
1a00e612 RS |
5317 | { |
5318 | match_out_of_range (arg); | |
5319 | return FALSE; | |
5320 | } | |
a1d78564 RS |
5321 | |
5322 | sval /= 4; | |
5323 | if (!(sval >= -258 && sval <= 257) || (sval >= -2 && sval <= 1)) | |
1a00e612 RS |
5324 | { |
5325 | match_out_of_range (arg); | |
5326 | return FALSE; | |
5327 | } | |
a1d78564 RS |
5328 | |
5329 | uval = (unsigned int) sval; | |
5330 | uval = ((uval >> 1) & ~0xff) | (uval & 0xff); | |
5331 | insn_insert_operand (arg->insn, operand, uval); | |
a92713e6 | 5332 | return TRUE; |
a1d78564 RS |
5333 | } |
5334 | ||
5335 | /* OP_CLO_CLZ_DEST matcher. */ | |
5336 | ||
a92713e6 | 5337 | static bfd_boolean |
a1d78564 | 5338 | match_clo_clz_dest_operand (struct mips_arg_info *arg, |
a92713e6 | 5339 | const struct mips_operand *operand) |
a1d78564 RS |
5340 | { |
5341 | unsigned int regno; | |
5342 | ||
a92713e6 RS |
5343 | if (!match_reg (arg, OP_REG_GP, ®no)) |
5344 | return FALSE; | |
a1d78564 | 5345 | |
a1d78564 | 5346 | insn_insert_operand (arg->insn, operand, regno | (regno << 5)); |
a92713e6 | 5347 | return TRUE; |
a1d78564 RS |
5348 | } |
5349 | ||
7361da2c AB |
5350 | /* OP_CHECK_PREV matcher. */ |
5351 | ||
5352 | static bfd_boolean | |
5353 | match_check_prev_operand (struct mips_arg_info *arg, | |
5354 | const struct mips_operand *operand_base) | |
5355 | { | |
5356 | const struct mips_check_prev_operand *operand; | |
5357 | unsigned int regno; | |
5358 | ||
5359 | operand = (const struct mips_check_prev_operand *) operand_base; | |
5360 | ||
5361 | if (!match_reg (arg, OP_REG_GP, ®no)) | |
5362 | return FALSE; | |
5363 | ||
5364 | if (!operand->zero_ok && regno == 0) | |
5365 | return FALSE; | |
5366 | ||
5367 | if ((operand->less_than_ok && regno < arg->last_regno) | |
5368 | || (operand->greater_than_ok && regno > arg->last_regno) | |
5369 | || (operand->equal_ok && regno == arg->last_regno)) | |
5370 | { | |
5371 | arg->last_regno = regno; | |
5372 | insn_insert_operand (arg->insn, operand_base, regno); | |
5373 | return TRUE; | |
5374 | } | |
5375 | ||
5376 | return FALSE; | |
5377 | } | |
5378 | ||
5379 | /* OP_SAME_RS_RT matcher. */ | |
5380 | ||
5381 | static bfd_boolean | |
5382 | match_same_rs_rt_operand (struct mips_arg_info *arg, | |
5383 | const struct mips_operand *operand) | |
5384 | { | |
5385 | unsigned int regno; | |
5386 | ||
5387 | if (!match_reg (arg, OP_REG_GP, ®no)) | |
5388 | return FALSE; | |
5389 | ||
5390 | if (regno == 0) | |
5391 | { | |
5392 | set_insn_error (arg->argnum, _("the source register must not be $0")); | |
5393 | return FALSE; | |
5394 | } | |
5395 | ||
5396 | arg->last_regno = regno; | |
5397 | ||
5398 | insn_insert_operand (arg->insn, operand, regno | (regno << 5)); | |
5399 | return TRUE; | |
5400 | } | |
5401 | ||
a1d78564 RS |
5402 | /* OP_LWM_SWM_LIST matcher. */ |
5403 | ||
a92713e6 | 5404 | static bfd_boolean |
a1d78564 | 5405 | match_lwm_swm_list_operand (struct mips_arg_info *arg, |
a92713e6 | 5406 | const struct mips_operand *operand) |
a1d78564 | 5407 | { |
a92713e6 RS |
5408 | unsigned int reglist, sregs, ra, regno1, regno2; |
5409 | struct mips_arg_info reset; | |
a1d78564 | 5410 | |
a92713e6 RS |
5411 | reglist = 0; |
5412 | if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2)) | |
5413 | return FALSE; | |
5414 | do | |
5415 | { | |
5416 | if (regno2 == FP && regno1 >= S0 && regno1 <= S7) | |
5417 | { | |
5418 | reglist |= 1 << FP; | |
5419 | regno2 = S7; | |
5420 | } | |
5421 | reglist |= ((1U << regno2 << 1) - 1) & -(1U << regno1); | |
5422 | reset = *arg; | |
5423 | } | |
5424 | while (match_char (arg, ',') | |
5425 | && match_reg_range (arg, OP_REG_GP, ®no1, ®no2)); | |
5426 | *arg = reset; | |
a1d78564 RS |
5427 | |
5428 | if (operand->size == 2) | |
5429 | { | |
5430 | /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.: | |
5431 | ||
5432 | s0, ra | |
5433 | s0, s1, ra, s2, s3 | |
5434 | s0-s2, ra | |
5435 | ||
5436 | and any permutations of these. */ | |
5437 | if ((reglist & 0xfff1ffff) != 0x80010000) | |
a92713e6 | 5438 | return FALSE; |
a1d78564 RS |
5439 | |
5440 | sregs = (reglist >> 17) & 7; | |
5441 | ra = 0; | |
5442 | } | |
5443 | else | |
5444 | { | |
5445 | /* The list must include at least one of ra and s0-sN, | |
5446 | for 0 <= N <= 8. (Note that there is a gap between s7 and s8, | |
5447 | which are $23 and $30 respectively.) E.g.: | |
5448 | ||
5449 | ra | |
5450 | s0 | |
5451 | ra, s0, s1, s2 | |
5452 | s0-s8 | |
5453 | s0-s5, ra | |
5454 | ||
5455 | and any permutations of these. */ | |
5456 | if ((reglist & 0x3f00ffff) != 0) | |
a92713e6 | 5457 | return FALSE; |
a1d78564 RS |
5458 | |
5459 | ra = (reglist >> 27) & 0x10; | |
5460 | sregs = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff); | |
5461 | } | |
5462 | sregs += 1; | |
5463 | if ((sregs & -sregs) != sregs) | |
a92713e6 | 5464 | return FALSE; |
a1d78564 RS |
5465 | |
5466 | insn_insert_operand (arg->insn, operand, (ffs (sregs) - 1) | ra); | |
a92713e6 | 5467 | return TRUE; |
a1d78564 RS |
5468 | } |
5469 | ||
364215c8 RS |
5470 | /* OP_ENTRY_EXIT_LIST matcher. */ |
5471 | ||
a92713e6 | 5472 | static unsigned int |
364215c8 | 5473 | match_entry_exit_operand (struct mips_arg_info *arg, |
a92713e6 | 5474 | const struct mips_operand *operand) |
364215c8 RS |
5475 | { |
5476 | unsigned int mask; | |
5477 | bfd_boolean is_exit; | |
5478 | ||
5479 | /* The format is the same for both ENTRY and EXIT, but the constraints | |
5480 | are different. */ | |
5481 | is_exit = strcmp (arg->insn->insn_mo->name, "exit") == 0; | |
5482 | mask = (is_exit ? 7 << 3 : 0); | |
a92713e6 | 5483 | do |
364215c8 RS |
5484 | { |
5485 | unsigned int regno1, regno2; | |
5486 | bfd_boolean is_freg; | |
5487 | ||
a92713e6 | 5488 | if (match_reg_range (arg, OP_REG_GP, ®no1, ®no2)) |
364215c8 | 5489 | is_freg = FALSE; |
a92713e6 | 5490 | else if (match_reg_range (arg, OP_REG_FP, ®no1, ®no2)) |
364215c8 RS |
5491 | is_freg = TRUE; |
5492 | else | |
a92713e6 | 5493 | return FALSE; |
364215c8 RS |
5494 | |
5495 | if (is_exit && is_freg && regno1 == 0 && regno2 < 2) | |
5496 | { | |
5497 | mask &= ~(7 << 3); | |
5498 | mask |= (5 + regno2) << 3; | |
5499 | } | |
5500 | else if (!is_exit && regno1 == 4 && regno2 >= 4 && regno2 <= 7) | |
5501 | mask |= (regno2 - 3) << 3; | |
5502 | else if (regno1 == 16 && regno2 >= 16 && regno2 <= 17) | |
5503 | mask |= (regno2 - 15) << 1; | |
5504 | else if (regno1 == RA && regno2 == RA) | |
5505 | mask |= 1; | |
5506 | else | |
a92713e6 | 5507 | return FALSE; |
364215c8 | 5508 | } |
a92713e6 RS |
5509 | while (match_char (arg, ',')); |
5510 | ||
364215c8 | 5511 | insn_insert_operand (arg->insn, operand, mask); |
a92713e6 | 5512 | return TRUE; |
364215c8 RS |
5513 | } |
5514 | ||
5515 | /* OP_SAVE_RESTORE_LIST matcher. */ | |
5516 | ||
a92713e6 RS |
5517 | static bfd_boolean |
5518 | match_save_restore_list_operand (struct mips_arg_info *arg) | |
364215c8 RS |
5519 | { |
5520 | unsigned int opcode, args, statics, sregs; | |
5521 | unsigned int num_frame_sizes, num_args, num_statics, num_sregs; | |
364215c8 | 5522 | offsetT frame_size; |
364215c8 | 5523 | |
364215c8 RS |
5524 | opcode = arg->insn->insn_opcode; |
5525 | frame_size = 0; | |
5526 | num_frame_sizes = 0; | |
5527 | args = 0; | |
5528 | statics = 0; | |
5529 | sregs = 0; | |
a92713e6 | 5530 | do |
364215c8 RS |
5531 | { |
5532 | unsigned int regno1, regno2; | |
5533 | ||
a92713e6 | 5534 | if (arg->token->type == OT_INTEGER) |
364215c8 RS |
5535 | { |
5536 | /* Handle the frame size. */ | |
1a00e612 | 5537 | if (!match_const_int (arg, &frame_size)) |
a92713e6 | 5538 | return FALSE; |
364215c8 | 5539 | num_frame_sizes += 1; |
364215c8 RS |
5540 | } |
5541 | else | |
5542 | { | |
a92713e6 RS |
5543 | if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2)) |
5544 | return FALSE; | |
364215c8 RS |
5545 | |
5546 | while (regno1 <= regno2) | |
5547 | { | |
5548 | if (regno1 >= 4 && regno1 <= 7) | |
5549 | { | |
5550 | if (num_frame_sizes == 0) | |
5551 | /* args $a0-$a3 */ | |
5552 | args |= 1 << (regno1 - 4); | |
5553 | else | |
5554 | /* statics $a0-$a3 */ | |
5555 | statics |= 1 << (regno1 - 4); | |
5556 | } | |
5557 | else if (regno1 >= 16 && regno1 <= 23) | |
5558 | /* $s0-$s7 */ | |
5559 | sregs |= 1 << (regno1 - 16); | |
5560 | else if (regno1 == 30) | |
5561 | /* $s8 */ | |
5562 | sregs |= 1 << 8; | |
5563 | else if (regno1 == 31) | |
5564 | /* Add $ra to insn. */ | |
5565 | opcode |= 0x40; | |
5566 | else | |
a92713e6 | 5567 | return FALSE; |
364215c8 RS |
5568 | regno1 += 1; |
5569 | if (regno1 == 24) | |
5570 | regno1 = 30; | |
5571 | } | |
5572 | } | |
364215c8 | 5573 | } |
a92713e6 | 5574 | while (match_char (arg, ',')); |
364215c8 RS |
5575 | |
5576 | /* Encode args/statics combination. */ | |
5577 | if (args & statics) | |
a92713e6 | 5578 | return FALSE; |
364215c8 RS |
5579 | else if (args == 0xf) |
5580 | /* All $a0-$a3 are args. */ | |
5581 | opcode |= MIPS16_ALL_ARGS << 16; | |
5582 | else if (statics == 0xf) | |
5583 | /* All $a0-$a3 are statics. */ | |
5584 | opcode |= MIPS16_ALL_STATICS << 16; | |
5585 | else | |
5586 | { | |
5587 | /* Count arg registers. */ | |
5588 | num_args = 0; | |
5589 | while (args & 0x1) | |
5590 | { | |
5591 | args >>= 1; | |
5592 | num_args += 1; | |
5593 | } | |
5594 | if (args != 0) | |
a92713e6 | 5595 | return FALSE; |
364215c8 RS |
5596 | |
5597 | /* Count static registers. */ | |
5598 | num_statics = 0; | |
5599 | while (statics & 0x8) | |
5600 | { | |
5601 | statics = (statics << 1) & 0xf; | |
5602 | num_statics += 1; | |
5603 | } | |
5604 | if (statics != 0) | |
a92713e6 | 5605 | return FALSE; |
364215c8 RS |
5606 | |
5607 | /* Encode args/statics. */ | |
5608 | opcode |= ((num_args << 2) | num_statics) << 16; | |
5609 | } | |
5610 | ||
5611 | /* Encode $s0/$s1. */ | |
5612 | if (sregs & (1 << 0)) /* $s0 */ | |
5613 | opcode |= 0x20; | |
5614 | if (sregs & (1 << 1)) /* $s1 */ | |
5615 | opcode |= 0x10; | |
5616 | sregs >>= 2; | |
5617 | ||
5618 | /* Encode $s2-$s8. */ | |
5619 | num_sregs = 0; | |
5620 | while (sregs & 1) | |
5621 | { | |
5622 | sregs >>= 1; | |
5623 | num_sregs += 1; | |
5624 | } | |
5625 | if (sregs != 0) | |
a92713e6 | 5626 | return FALSE; |
364215c8 RS |
5627 | opcode |= num_sregs << 24; |
5628 | ||
5629 | /* Encode frame size. */ | |
5630 | if (num_frame_sizes == 0) | |
1a00e612 RS |
5631 | { |
5632 | set_insn_error (arg->argnum, _("missing frame size")); | |
5633 | return FALSE; | |
5634 | } | |
5635 | if (num_frame_sizes > 1) | |
5636 | { | |
5637 | set_insn_error (arg->argnum, _("frame size specified twice")); | |
5638 | return FALSE; | |
5639 | } | |
5640 | if ((frame_size & 7) != 0 || frame_size < 0 || frame_size > 0xff * 8) | |
5641 | { | |
5642 | set_insn_error (arg->argnum, _("invalid frame size")); | |
5643 | return FALSE; | |
5644 | } | |
5645 | if (frame_size != 128 || (opcode >> 16) != 0) | |
364215c8 RS |
5646 | { |
5647 | frame_size /= 8; | |
5648 | opcode |= (((frame_size & 0xf0) << 16) | |
5649 | | (frame_size & 0x0f)); | |
5650 | } | |
5651 | ||
364215c8 RS |
5652 | /* Finally build the instruction. */ |
5653 | if ((opcode >> 16) != 0 || frame_size == 0) | |
5654 | opcode |= MIPS16_EXTEND; | |
5655 | arg->insn->insn_opcode = opcode; | |
a92713e6 | 5656 | return TRUE; |
364215c8 RS |
5657 | } |
5658 | ||
a1d78564 RS |
5659 | /* OP_MDMX_IMM_REG matcher. */ |
5660 | ||
a92713e6 | 5661 | static bfd_boolean |
a1d78564 | 5662 | match_mdmx_imm_reg_operand (struct mips_arg_info *arg, |
a92713e6 | 5663 | const struct mips_operand *operand) |
a1d78564 | 5664 | { |
a92713e6 | 5665 | unsigned int regno, uval; |
a1d78564 RS |
5666 | bfd_boolean is_qh; |
5667 | const struct mips_opcode *opcode; | |
5668 | ||
5669 | /* The mips_opcode records whether this is an octobyte or quadhalf | |
5670 | instruction. Start out with that bit in place. */ | |
5671 | opcode = arg->insn->insn_mo; | |
5672 | uval = mips_extract_operand (operand, opcode->match); | |
5673 | is_qh = (uval != 0); | |
5674 | ||
56d438b1 | 5675 | if (arg->token->type == OT_REG) |
a1d78564 RS |
5676 | { |
5677 | if ((opcode->membership & INSN_5400) | |
5678 | && strcmp (opcode->name, "rzu.ob") == 0) | |
5679 | { | |
1a00e612 RS |
5680 | set_insn_error_i (arg->argnum, _("operand %d must be an immediate"), |
5681 | arg->argnum); | |
5682 | return FALSE; | |
a1d78564 RS |
5683 | } |
5684 | ||
56d438b1 CF |
5685 | if (!match_regno (arg, OP_REG_VEC, arg->token->u.regno, ®no)) |
5686 | return FALSE; | |
5687 | ++arg->token; | |
5688 | ||
a1d78564 RS |
5689 | /* Check whether this is a vector register or a broadcast of |
5690 | a single element. */ | |
56d438b1 | 5691 | if (arg->token->type == OT_INTEGER_INDEX) |
a1d78564 | 5692 | { |
56d438b1 | 5693 | if (arg->token->u.index > (is_qh ? 3 : 7)) |
a1d78564 | 5694 | { |
1a00e612 RS |
5695 | set_insn_error (arg->argnum, _("invalid element selector")); |
5696 | return FALSE; | |
a1d78564 | 5697 | } |
56d438b1 CF |
5698 | uval |= arg->token->u.index << (is_qh ? 2 : 1) << 5; |
5699 | ++arg->token; | |
a1d78564 RS |
5700 | } |
5701 | else | |
5702 | { | |
5703 | /* A full vector. */ | |
5704 | if ((opcode->membership & INSN_5400) | |
5705 | && (strcmp (opcode->name, "sll.ob") == 0 | |
5706 | || strcmp (opcode->name, "srl.ob") == 0)) | |
5707 | { | |
1a00e612 RS |
5708 | set_insn_error_i (arg->argnum, _("operand %d must be scalar"), |
5709 | arg->argnum); | |
5710 | return FALSE; | |
a1d78564 RS |
5711 | } |
5712 | ||
5713 | if (is_qh) | |
5714 | uval |= MDMX_FMTSEL_VEC_QH << 5; | |
5715 | else | |
5716 | uval |= MDMX_FMTSEL_VEC_OB << 5; | |
5717 | } | |
a1d78564 RS |
5718 | uval |= regno; |
5719 | } | |
5720 | else | |
5721 | { | |
5722 | offsetT sval; | |
5723 | ||
1a00e612 | 5724 | if (!match_const_int (arg, &sval)) |
a92713e6 | 5725 | return FALSE; |
a1d78564 RS |
5726 | if (sval < 0 || sval > 31) |
5727 | { | |
1a00e612 RS |
5728 | match_out_of_range (arg); |
5729 | return FALSE; | |
a1d78564 RS |
5730 | } |
5731 | uval |= (sval & 31); | |
5732 | if (is_qh) | |
5733 | uval |= MDMX_FMTSEL_IMM_QH << 5; | |
5734 | else | |
5735 | uval |= MDMX_FMTSEL_IMM_OB << 5; | |
5736 | } | |
5737 | insn_insert_operand (arg->insn, operand, uval); | |
a92713e6 | 5738 | return TRUE; |
a1d78564 RS |
5739 | } |
5740 | ||
56d438b1 CF |
5741 | /* OP_IMM_INDEX matcher. */ |
5742 | ||
5743 | static bfd_boolean | |
5744 | match_imm_index_operand (struct mips_arg_info *arg, | |
5745 | const struct mips_operand *operand) | |
5746 | { | |
5747 | unsigned int max_val; | |
5748 | ||
5749 | if (arg->token->type != OT_INTEGER_INDEX) | |
5750 | return FALSE; | |
5751 | ||
5752 | max_val = (1 << operand->size) - 1; | |
5753 | if (arg->token->u.index > max_val) | |
5754 | { | |
5755 | match_out_of_range (arg); | |
5756 | return FALSE; | |
5757 | } | |
5758 | insn_insert_operand (arg->insn, operand, arg->token->u.index); | |
5759 | ++arg->token; | |
5760 | return TRUE; | |
5761 | } | |
5762 | ||
5763 | /* OP_REG_INDEX matcher. */ | |
5764 | ||
5765 | static bfd_boolean | |
5766 | match_reg_index_operand (struct mips_arg_info *arg, | |
5767 | const struct mips_operand *operand) | |
5768 | { | |
5769 | unsigned int regno; | |
5770 | ||
5771 | if (arg->token->type != OT_REG_INDEX) | |
5772 | return FALSE; | |
5773 | ||
5774 | if (!match_regno (arg, OP_REG_GP, arg->token->u.regno, ®no)) | |
5775 | return FALSE; | |
5776 | ||
5777 | insn_insert_operand (arg->insn, operand, regno); | |
5778 | ++arg->token; | |
5779 | return TRUE; | |
5780 | } | |
5781 | ||
a1d78564 RS |
5782 | /* OP_PC matcher. */ |
5783 | ||
a92713e6 RS |
5784 | static bfd_boolean |
5785 | match_pc_operand (struct mips_arg_info *arg) | |
a1d78564 | 5786 | { |
a92713e6 RS |
5787 | if (arg->token->type == OT_REG && (arg->token->u.regno & RTYPE_PC)) |
5788 | { | |
5789 | ++arg->token; | |
5790 | return TRUE; | |
5791 | } | |
5792 | return FALSE; | |
a1d78564 RS |
5793 | } |
5794 | ||
7361da2c AB |
5795 | /* OP_NON_ZERO_REG matcher. */ |
5796 | ||
5797 | static bfd_boolean | |
5798 | match_non_zero_reg_operand (struct mips_arg_info *arg, | |
5799 | const struct mips_operand *operand) | |
5800 | { | |
5801 | unsigned int regno; | |
5802 | ||
5803 | if (!match_reg (arg, OP_REG_GP, ®no)) | |
5804 | return FALSE; | |
5805 | ||
5806 | if (regno == 0) | |
5807 | return FALSE; | |
5808 | ||
5809 | arg->last_regno = regno; | |
5810 | insn_insert_operand (arg->insn, operand, regno); | |
5811 | return TRUE; | |
5812 | } | |
5813 | ||
a1d78564 RS |
5814 | /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the |
5815 | register that we need to match. */ | |
5816 | ||
a92713e6 RS |
5817 | static bfd_boolean |
5818 | match_tied_reg_operand (struct mips_arg_info *arg, unsigned int other_regno) | |
a1d78564 RS |
5819 | { |
5820 | unsigned int regno; | |
5821 | ||
a92713e6 | 5822 | return match_reg (arg, OP_REG_GP, ®no) && regno == other_regno; |
a1d78564 RS |
5823 | } |
5824 | ||
89565f1b RS |
5825 | /* Read a floating-point constant from S for LI.S or LI.D. LENGTH is |
5826 | the length of the value in bytes (4 for float, 8 for double) and | |
5827 | USING_GPRS says whether the destination is a GPR rather than an FPR. | |
5828 | ||
5829 | Return the constant in IMM and OFFSET as follows: | |
5830 | ||
5831 | - If the constant should be loaded via memory, set IMM to O_absent and | |
5832 | OFFSET to the memory address. | |
5833 | ||
5834 | - Otherwise, if the constant should be loaded into two 32-bit registers, | |
5835 | set IMM to the O_constant to load into the high register and OFFSET | |
5836 | to the corresponding value for the low register. | |
5837 | ||
5838 | - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent. | |
5839 | ||
5840 | These constants only appear as the last operand in an instruction, | |
5841 | and every instruction that accepts them in any variant accepts them | |
5842 | in all variants. This means we don't have to worry about backing out | |
5843 | any changes if the instruction does not match. We just match | |
5844 | unconditionally and report an error if the constant is invalid. */ | |
5845 | ||
a92713e6 RS |
5846 | static bfd_boolean |
5847 | match_float_constant (struct mips_arg_info *arg, expressionS *imm, | |
5848 | expressionS *offset, int length, bfd_boolean using_gprs) | |
89565f1b | 5849 | { |
a92713e6 | 5850 | char *p; |
89565f1b RS |
5851 | segT seg, new_seg; |
5852 | subsegT subseg; | |
5853 | const char *newname; | |
a92713e6 | 5854 | unsigned char *data; |
89565f1b RS |
5855 | |
5856 | /* Where the constant is placed is based on how the MIPS assembler | |
5857 | does things: | |
5858 | ||
5859 | length == 4 && using_gprs -- immediate value only | |
5860 | length == 8 && using_gprs -- .rdata or immediate value | |
5861 | length == 4 && !using_gprs -- .lit4 or immediate value | |
5862 | length == 8 && !using_gprs -- .lit8 or immediate value | |
5863 | ||
5864 | The .lit4 and .lit8 sections are only used if permitted by the | |
5865 | -G argument. */ | |
a92713e6 | 5866 | if (arg->token->type != OT_FLOAT) |
1a00e612 RS |
5867 | { |
5868 | set_insn_error (arg->argnum, _("floating-point expression required")); | |
5869 | return FALSE; | |
5870 | } | |
a92713e6 RS |
5871 | |
5872 | gas_assert (arg->token->u.flt.length == length); | |
5873 | data = arg->token->u.flt.data; | |
5874 | ++arg->token; | |
89565f1b RS |
5875 | |
5876 | /* Handle 32-bit constants for which an immediate value is best. */ | |
5877 | if (length == 4 | |
5878 | && (using_gprs | |
5879 | || g_switch_value < 4 | |
5880 | || (data[0] == 0 && data[1] == 0) | |
5881 | || (data[2] == 0 && data[3] == 0))) | |
5882 | { | |
5883 | imm->X_op = O_constant; | |
5884 | if (!target_big_endian) | |
5885 | imm->X_add_number = bfd_getl32 (data); | |
5886 | else | |
5887 | imm->X_add_number = bfd_getb32 (data); | |
5888 | offset->X_op = O_absent; | |
a92713e6 | 5889 | return TRUE; |
89565f1b RS |
5890 | } |
5891 | ||
5892 | /* Handle 64-bit constants for which an immediate value is best. */ | |
5893 | if (length == 8 | |
5894 | && !mips_disable_float_construction | |
351cdf24 MF |
5895 | /* Constants can only be constructed in GPRs and copied to FPRs if the |
5896 | GPRs are at least as wide as the FPRs or MTHC1 is available. | |
5897 | Unlike most tests for 32-bit floating-point registers this check | |
5898 | specifically looks for GPR_SIZE == 32 as the FPXX ABI does not | |
5899 | permit 64-bit moves without MXHC1. | |
5900 | Force the constant into memory otherwise. */ | |
5901 | && (using_gprs | |
5902 | || GPR_SIZE == 64 | |
5903 | || ISA_HAS_MXHC1 (mips_opts.isa) | |
5904 | || FPR_SIZE == 32) | |
89565f1b RS |
5905 | && ((data[0] == 0 && data[1] == 0) |
5906 | || (data[2] == 0 && data[3] == 0)) | |
5907 | && ((data[4] == 0 && data[5] == 0) | |
5908 | || (data[6] == 0 && data[7] == 0))) | |
5909 | { | |
5910 | /* The value is simple enough to load with a couple of instructions. | |
5911 | If using 32-bit registers, set IMM to the high order 32 bits and | |
5912 | OFFSET to the low order 32 bits. Otherwise, set IMM to the entire | |
5913 | 64 bit constant. */ | |
351cdf24 | 5914 | if (GPR_SIZE == 32 || (!using_gprs && FPR_SIZE != 64)) |
89565f1b RS |
5915 | { |
5916 | imm->X_op = O_constant; | |
5917 | offset->X_op = O_constant; | |
5918 | if (!target_big_endian) | |
5919 | { | |
5920 | imm->X_add_number = bfd_getl32 (data + 4); | |
5921 | offset->X_add_number = bfd_getl32 (data); | |
5922 | } | |
5923 | else | |
5924 | { | |
5925 | imm->X_add_number = bfd_getb32 (data); | |
5926 | offset->X_add_number = bfd_getb32 (data + 4); | |
5927 | } | |
5928 | if (offset->X_add_number == 0) | |
5929 | offset->X_op = O_absent; | |
5930 | } | |
5931 | else | |
5932 | { | |
5933 | imm->X_op = O_constant; | |
5934 | if (!target_big_endian) | |
5935 | imm->X_add_number = bfd_getl64 (data); | |
5936 | else | |
5937 | imm->X_add_number = bfd_getb64 (data); | |
5938 | offset->X_op = O_absent; | |
5939 | } | |
a92713e6 | 5940 | return TRUE; |
89565f1b RS |
5941 | } |
5942 | ||
5943 | /* Switch to the right section. */ | |
5944 | seg = now_seg; | |
5945 | subseg = now_subseg; | |
5946 | if (length == 4) | |
5947 | { | |
5948 | gas_assert (!using_gprs && g_switch_value >= 4); | |
5949 | newname = ".lit4"; | |
5950 | } | |
5951 | else | |
5952 | { | |
5953 | if (using_gprs || g_switch_value < 8) | |
5954 | newname = RDATA_SECTION_NAME; | |
5955 | else | |
5956 | newname = ".lit8"; | |
5957 | } | |
5958 | ||
5959 | new_seg = subseg_new (newname, (subsegT) 0); | |
5960 | bfd_set_section_flags (stdoutput, new_seg, | |
5961 | SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_DATA); | |
5962 | frag_align (length == 4 ? 2 : 3, 0, 0); | |
5963 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
5964 | record_alignment (new_seg, 4); | |
5965 | else | |
5966 | record_alignment (new_seg, length == 4 ? 2 : 3); | |
5967 | if (seg == now_seg) | |
1661c76c | 5968 | as_bad (_("cannot use `%s' in this section"), arg->insn->insn_mo->name); |
89565f1b RS |
5969 | |
5970 | /* Set the argument to the current address in the section. */ | |
5971 | imm->X_op = O_absent; | |
5972 | offset->X_op = O_symbol; | |
5973 | offset->X_add_symbol = symbol_temp_new_now (); | |
5974 | offset->X_add_number = 0; | |
5975 | ||
5976 | /* Put the floating point number into the section. */ | |
5977 | p = frag_more (length); | |
5978 | memcpy (p, data, length); | |
5979 | ||
5980 | /* Switch back to the original section. */ | |
5981 | subseg_set (seg, subseg); | |
a92713e6 | 5982 | return TRUE; |
89565f1b RS |
5983 | } |
5984 | ||
14daeee3 RS |
5985 | /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between |
5986 | them. */ | |
5987 | ||
5988 | static bfd_boolean | |
5989 | match_vu0_suffix_operand (struct mips_arg_info *arg, | |
5990 | const struct mips_operand *operand, | |
5991 | bfd_boolean match_p) | |
5992 | { | |
5993 | unsigned int uval; | |
5994 | ||
5995 | /* The operand can be an XYZW mask or a single 2-bit channel index | |
5996 | (with X being 0). */ | |
5997 | gas_assert (operand->size == 2 || operand->size == 4); | |
5998 | ||
ee5734f0 | 5999 | /* The suffix can be omitted when it is already part of the opcode. */ |
14daeee3 | 6000 | if (arg->token->type != OT_CHANNELS) |
ee5734f0 | 6001 | return match_p; |
14daeee3 RS |
6002 | |
6003 | uval = arg->token->u.channels; | |
6004 | if (operand->size == 2) | |
6005 | { | |
6006 | /* Check that a single bit is set and convert it into a 2-bit index. */ | |
6007 | if ((uval & -uval) != uval) | |
6008 | return FALSE; | |
6009 | uval = 4 - ffs (uval); | |
6010 | } | |
6011 | ||
6012 | if (match_p && insn_extract_operand (arg->insn, operand) != uval) | |
6013 | return FALSE; | |
6014 | ||
6015 | ++arg->token; | |
6016 | if (!match_p) | |
6017 | insn_insert_operand (arg->insn, operand, uval); | |
6018 | return TRUE; | |
6019 | } | |
6020 | ||
a1d78564 RS |
6021 | /* S is the text seen for ARG. Match it against OPERAND. Return the end |
6022 | of the argument text if the match is successful, otherwise return null. */ | |
6023 | ||
a92713e6 | 6024 | static bfd_boolean |
a1d78564 | 6025 | match_operand (struct mips_arg_info *arg, |
a92713e6 | 6026 | const struct mips_operand *operand) |
a1d78564 RS |
6027 | { |
6028 | switch (operand->type) | |
6029 | { | |
6030 | case OP_INT: | |
a92713e6 | 6031 | return match_int_operand (arg, operand); |
a1d78564 RS |
6032 | |
6033 | case OP_MAPPED_INT: | |
a92713e6 | 6034 | return match_mapped_int_operand (arg, operand); |
a1d78564 RS |
6035 | |
6036 | case OP_MSB: | |
a92713e6 | 6037 | return match_msb_operand (arg, operand); |
a1d78564 RS |
6038 | |
6039 | case OP_REG: | |
0f35dbc4 | 6040 | case OP_OPTIONAL_REG: |
a92713e6 | 6041 | return match_reg_operand (arg, operand); |
a1d78564 RS |
6042 | |
6043 | case OP_REG_PAIR: | |
a92713e6 | 6044 | return match_reg_pair_operand (arg, operand); |
a1d78564 RS |
6045 | |
6046 | case OP_PCREL: | |
a92713e6 | 6047 | return match_pcrel_operand (arg); |
a1d78564 RS |
6048 | |
6049 | case OP_PERF_REG: | |
a92713e6 | 6050 | return match_perf_reg_operand (arg, operand); |
a1d78564 RS |
6051 | |
6052 | case OP_ADDIUSP_INT: | |
a92713e6 | 6053 | return match_addiusp_operand (arg, operand); |
a1d78564 RS |
6054 | |
6055 | case OP_CLO_CLZ_DEST: | |
a92713e6 | 6056 | return match_clo_clz_dest_operand (arg, operand); |
a1d78564 RS |
6057 | |
6058 | case OP_LWM_SWM_LIST: | |
a92713e6 | 6059 | return match_lwm_swm_list_operand (arg, operand); |
a1d78564 RS |
6060 | |
6061 | case OP_ENTRY_EXIT_LIST: | |
a92713e6 | 6062 | return match_entry_exit_operand (arg, operand); |
364215c8 | 6063 | |
a1d78564 | 6064 | case OP_SAVE_RESTORE_LIST: |
a92713e6 | 6065 | return match_save_restore_list_operand (arg); |
a1d78564 RS |
6066 | |
6067 | case OP_MDMX_IMM_REG: | |
a92713e6 | 6068 | return match_mdmx_imm_reg_operand (arg, operand); |
a1d78564 RS |
6069 | |
6070 | case OP_REPEAT_DEST_REG: | |
a92713e6 | 6071 | return match_tied_reg_operand (arg, arg->dest_regno); |
a1d78564 RS |
6072 | |
6073 | case OP_REPEAT_PREV_REG: | |
a92713e6 | 6074 | return match_tied_reg_operand (arg, arg->last_regno); |
a1d78564 RS |
6075 | |
6076 | case OP_PC: | |
a92713e6 | 6077 | return match_pc_operand (arg); |
14daeee3 RS |
6078 | |
6079 | case OP_VU0_SUFFIX: | |
6080 | return match_vu0_suffix_operand (arg, operand, FALSE); | |
6081 | ||
6082 | case OP_VU0_MATCH_SUFFIX: | |
6083 | return match_vu0_suffix_operand (arg, operand, TRUE); | |
56d438b1 CF |
6084 | |
6085 | case OP_IMM_INDEX: | |
6086 | return match_imm_index_operand (arg, operand); | |
6087 | ||
6088 | case OP_REG_INDEX: | |
6089 | return match_reg_index_operand (arg, operand); | |
7361da2c AB |
6090 | |
6091 | case OP_SAME_RS_RT: | |
6092 | return match_same_rs_rt_operand (arg, operand); | |
6093 | ||
6094 | case OP_CHECK_PREV: | |
6095 | return match_check_prev_operand (arg, operand); | |
6096 | ||
6097 | case OP_NON_ZERO_REG: | |
6098 | return match_non_zero_reg_operand (arg, operand); | |
a1d78564 RS |
6099 | } |
6100 | abort (); | |
6101 | } | |
6102 | ||
6103 | /* ARG is the state after successfully matching an instruction. | |
6104 | Issue any queued-up warnings. */ | |
6105 | ||
6106 | static void | |
6107 | check_completed_insn (struct mips_arg_info *arg) | |
6108 | { | |
6109 | if (arg->seen_at) | |
6110 | { | |
6111 | if (AT == ATREG) | |
1661c76c | 6112 | as_warn (_("used $at without \".set noat\"")); |
a1d78564 | 6113 | else |
1661c76c | 6114 | as_warn (_("used $%u with \".set at=$%u\""), AT, AT); |
a1d78564 RS |
6115 | } |
6116 | } | |
a1d78564 | 6117 | |
85fcb30f RS |
6118 | /* Return true if modifying general-purpose register REG needs a delay. */ |
6119 | ||
6120 | static bfd_boolean | |
6121 | reg_needs_delay (unsigned int reg) | |
6122 | { | |
6123 | unsigned long prev_pinfo; | |
6124 | ||
6125 | prev_pinfo = history[0].insn_mo->pinfo; | |
6126 | if (!mips_opts.noreorder | |
67dc82bc | 6127 | && (((prev_pinfo & INSN_LOAD_MEMORY) && !gpr_interlocks) |
43885403 | 6128 | || ((prev_pinfo & INSN_LOAD_COPROC) && !cop_interlocks)) |
85fcb30f RS |
6129 | && (gpr_write_mask (&history[0]) & (1 << reg))) |
6130 | return TRUE; | |
6131 | ||
6132 | return FALSE; | |
6133 | } | |
6134 | ||
71400594 RS |
6135 | /* Classify an instruction according to the FIX_VR4120_* enumeration. |
6136 | Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected | |
6137 | by VR4120 errata. */ | |
4d7206a2 | 6138 | |
71400594 RS |
6139 | static unsigned int |
6140 | classify_vr4120_insn (const char *name) | |
252b5132 | 6141 | { |
71400594 RS |
6142 | if (strncmp (name, "macc", 4) == 0) |
6143 | return FIX_VR4120_MACC; | |
6144 | if (strncmp (name, "dmacc", 5) == 0) | |
6145 | return FIX_VR4120_DMACC; | |
6146 | if (strncmp (name, "mult", 4) == 0) | |
6147 | return FIX_VR4120_MULT; | |
6148 | if (strncmp (name, "dmult", 5) == 0) | |
6149 | return FIX_VR4120_DMULT; | |
6150 | if (strstr (name, "div")) | |
6151 | return FIX_VR4120_DIV; | |
6152 | if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) | |
6153 | return FIX_VR4120_MTHILO; | |
6154 | return NUM_FIX_VR4120_CLASSES; | |
6155 | } | |
252b5132 | 6156 | |
a8d14a88 CM |
6157 | #define INSN_ERET 0x42000018 |
6158 | #define INSN_DERET 0x4200001f | |
6159 | #define INSN_DMULT 0x1c | |
6160 | #define INSN_DMULTU 0x1d | |
ff239038 | 6161 | |
71400594 RS |
6162 | /* Return the number of instructions that must separate INSN1 and INSN2, |
6163 | where INSN1 is the earlier instruction. Return the worst-case value | |
6164 | for any INSN2 if INSN2 is null. */ | |
252b5132 | 6165 | |
71400594 RS |
6166 | static unsigned int |
6167 | insns_between (const struct mips_cl_insn *insn1, | |
6168 | const struct mips_cl_insn *insn2) | |
6169 | { | |
6170 | unsigned long pinfo1, pinfo2; | |
4c260379 | 6171 | unsigned int mask; |
71400594 | 6172 | |
85fcb30f RS |
6173 | /* If INFO2 is null, pessimistically assume that all flags are set for |
6174 | the second instruction. */ | |
71400594 RS |
6175 | pinfo1 = insn1->insn_mo->pinfo; |
6176 | pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; | |
252b5132 | 6177 | |
71400594 RS |
6178 | /* For most targets, write-after-read dependencies on the HI and LO |
6179 | registers must be separated by at least two instructions. */ | |
6180 | if (!hilo_interlocks) | |
252b5132 | 6181 | { |
71400594 RS |
6182 | if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) |
6183 | return 2; | |
6184 | if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) | |
6185 | return 2; | |
6186 | } | |
6187 | ||
6188 | /* If we're working around r7000 errata, there must be two instructions | |
6189 | between an mfhi or mflo and any instruction that uses the result. */ | |
6190 | if (mips_7000_hilo_fix | |
df58fc94 | 6191 | && !mips_opts.micromips |
71400594 | 6192 | && MF_HILO_INSN (pinfo1) |
85fcb30f | 6193 | && (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1)))) |
71400594 RS |
6194 | return 2; |
6195 | ||
ff239038 CM |
6196 | /* If we're working around 24K errata, one instruction is required |
6197 | if an ERET or DERET is followed by a branch instruction. */ | |
df58fc94 | 6198 | if (mips_fix_24k && !mips_opts.micromips) |
ff239038 CM |
6199 | { |
6200 | if (insn1->insn_opcode == INSN_ERET | |
6201 | || insn1->insn_opcode == INSN_DERET) | |
6202 | { | |
6203 | if (insn2 == NULL | |
6204 | || insn2->insn_opcode == INSN_ERET | |
6205 | || insn2->insn_opcode == INSN_DERET | |
11625dd8 | 6206 | || delayed_branch_p (insn2)) |
ff239038 CM |
6207 | return 1; |
6208 | } | |
6209 | } | |
6210 | ||
a8d14a88 CM |
6211 | /* If we're working around PMC RM7000 errata, there must be three |
6212 | nops between a dmult and a load instruction. */ | |
6213 | if (mips_fix_rm7000 && !mips_opts.micromips) | |
6214 | { | |
6215 | if ((insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULT | |
6216 | || (insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULTU) | |
6217 | { | |
6218 | if (pinfo2 & INSN_LOAD_MEMORY) | |
6219 | return 3; | |
6220 | } | |
6221 | } | |
6222 | ||
71400594 RS |
6223 | /* If working around VR4120 errata, check for combinations that need |
6224 | a single intervening instruction. */ | |
df58fc94 | 6225 | if (mips_fix_vr4120 && !mips_opts.micromips) |
71400594 RS |
6226 | { |
6227 | unsigned int class1, class2; | |
252b5132 | 6228 | |
71400594 RS |
6229 | class1 = classify_vr4120_insn (insn1->insn_mo->name); |
6230 | if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) | |
252b5132 | 6231 | { |
71400594 RS |
6232 | if (insn2 == NULL) |
6233 | return 1; | |
6234 | class2 = classify_vr4120_insn (insn2->insn_mo->name); | |
6235 | if (vr4120_conflicts[class1] & (1 << class2)) | |
6236 | return 1; | |
252b5132 | 6237 | } |
71400594 RS |
6238 | } |
6239 | ||
df58fc94 | 6240 | if (!HAVE_CODE_COMPRESSION) |
71400594 RS |
6241 | { |
6242 | /* Check for GPR or coprocessor load delays. All such delays | |
6243 | are on the RT register. */ | |
6244 | /* Itbl support may require additional care here. */ | |
67dc82bc | 6245 | if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY)) |
43885403 | 6246 | || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC))) |
252b5132 | 6247 | { |
85fcb30f | 6248 | if (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1))) |
71400594 RS |
6249 | return 1; |
6250 | } | |
6251 | ||
6252 | /* Check for generic coprocessor hazards. | |
6253 | ||
6254 | This case is not handled very well. There is no special | |
6255 | knowledge of CP0 handling, and the coprocessors other than | |
6256 | the floating point unit are not distinguished at all. */ | |
6257 | /* Itbl support may require additional care here. FIXME! | |
6258 | Need to modify this to include knowledge about | |
6259 | user specified delays! */ | |
43885403 | 6260 | else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE)) |
71400594 RS |
6261 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) |
6262 | { | |
6263 | /* Handle cases where INSN1 writes to a known general coprocessor | |
6264 | register. There must be a one instruction delay before INSN2 | |
6265 | if INSN2 reads that register, otherwise no delay is needed. */ | |
4c260379 RS |
6266 | mask = fpr_write_mask (insn1); |
6267 | if (mask != 0) | |
252b5132 | 6268 | { |
4c260379 | 6269 | if (!insn2 || (mask & fpr_read_mask (insn2)) != 0) |
71400594 | 6270 | return 1; |
252b5132 RH |
6271 | } |
6272 | else | |
6273 | { | |
71400594 RS |
6274 | /* Read-after-write dependencies on the control registers |
6275 | require a two-instruction gap. */ | |
6276 | if ((pinfo1 & INSN_WRITE_COND_CODE) | |
6277 | && (pinfo2 & INSN_READ_COND_CODE)) | |
6278 | return 2; | |
6279 | ||
6280 | /* We don't know exactly what INSN1 does. If INSN2 is | |
6281 | also a coprocessor instruction, assume there must be | |
6282 | a one instruction gap. */ | |
6283 | if (pinfo2 & INSN_COP) | |
6284 | return 1; | |
252b5132 RH |
6285 | } |
6286 | } | |
6b76fefe | 6287 | |
71400594 RS |
6288 | /* Check for read-after-write dependencies on the coprocessor |
6289 | control registers in cases where INSN1 does not need a general | |
6290 | coprocessor delay. This means that INSN1 is a floating point | |
6291 | comparison instruction. */ | |
6292 | /* Itbl support may require additional care here. */ | |
6293 | else if (!cop_interlocks | |
6294 | && (pinfo1 & INSN_WRITE_COND_CODE) | |
6295 | && (pinfo2 & INSN_READ_COND_CODE)) | |
6296 | return 1; | |
6297 | } | |
6b76fefe | 6298 | |
7361da2c AB |
6299 | /* Forbidden slots can not contain Control Transfer Instructions (CTIs) |
6300 | CTIs include all branches and jumps, nal, eret, eretnc, deret, wait | |
6301 | and pause. */ | |
6302 | if ((insn1->insn_mo->pinfo2 & INSN2_FORBIDDEN_SLOT) | |
6303 | && ((pinfo2 & INSN_NO_DELAY_SLOT) | |
6304 | || (insn2 && delayed_branch_p (insn2)))) | |
6305 | return 1; | |
6306 | ||
71400594 RS |
6307 | return 0; |
6308 | } | |
6b76fefe | 6309 | |
7d8e00cf RS |
6310 | /* Return the number of nops that would be needed to work around the |
6311 | VR4130 mflo/mfhi errata if instruction INSN immediately followed | |
932d1a1b RS |
6312 | the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards |
6313 | that are contained within the first IGNORE instructions of HIST. */ | |
7d8e00cf RS |
6314 | |
6315 | static int | |
932d1a1b | 6316 | nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist, |
7d8e00cf RS |
6317 | const struct mips_cl_insn *insn) |
6318 | { | |
4c260379 RS |
6319 | int i, j; |
6320 | unsigned int mask; | |
7d8e00cf RS |
6321 | |
6322 | /* Check if the instruction writes to HI or LO. MTHI and MTLO | |
6323 | are not affected by the errata. */ | |
6324 | if (insn != 0 | |
6325 | && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 | |
6326 | || strcmp (insn->insn_mo->name, "mtlo") == 0 | |
6327 | || strcmp (insn->insn_mo->name, "mthi") == 0)) | |
6328 | return 0; | |
6329 | ||
6330 | /* Search for the first MFLO or MFHI. */ | |
6331 | for (i = 0; i < MAX_VR4130_NOPS; i++) | |
91d6fa6a | 6332 | if (MF_HILO_INSN (hist[i].insn_mo->pinfo)) |
7d8e00cf RS |
6333 | { |
6334 | /* Extract the destination register. */ | |
4c260379 | 6335 | mask = gpr_write_mask (&hist[i]); |
7d8e00cf RS |
6336 | |
6337 | /* No nops are needed if INSN reads that register. */ | |
4c260379 | 6338 | if (insn != NULL && (gpr_read_mask (insn) & mask) != 0) |
7d8e00cf RS |
6339 | return 0; |
6340 | ||
6341 | /* ...or if any of the intervening instructions do. */ | |
6342 | for (j = 0; j < i; j++) | |
4c260379 | 6343 | if (gpr_read_mask (&hist[j]) & mask) |
7d8e00cf RS |
6344 | return 0; |
6345 | ||
932d1a1b RS |
6346 | if (i >= ignore) |
6347 | return MAX_VR4130_NOPS - i; | |
7d8e00cf RS |
6348 | } |
6349 | return 0; | |
6350 | } | |
6351 | ||
134c0c8b MR |
6352 | #define BASE_REG_EQ(INSN1, INSN2) \ |
6353 | ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \ | |
15be625d CM |
6354 | == (((INSN2) >> OP_SH_RS) & OP_MASK_RS)) |
6355 | ||
6356 | /* Return the minimum alignment for this store instruction. */ | |
6357 | ||
6358 | static int | |
6359 | fix_24k_align_to (const struct mips_opcode *mo) | |
6360 | { | |
6361 | if (strcmp (mo->name, "sh") == 0) | |
6362 | return 2; | |
6363 | ||
6364 | if (strcmp (mo->name, "swc1") == 0 | |
6365 | || strcmp (mo->name, "swc2") == 0 | |
6366 | || strcmp (mo->name, "sw") == 0 | |
6367 | || strcmp (mo->name, "sc") == 0 | |
6368 | || strcmp (mo->name, "s.s") == 0) | |
6369 | return 4; | |
6370 | ||
6371 | if (strcmp (mo->name, "sdc1") == 0 | |
6372 | || strcmp (mo->name, "sdc2") == 0 | |
6373 | || strcmp (mo->name, "s.d") == 0) | |
6374 | return 8; | |
6375 | ||
6376 | /* sb, swl, swr */ | |
6377 | return 1; | |
6378 | } | |
6379 | ||
6380 | struct fix_24k_store_info | |
6381 | { | |
6382 | /* Immediate offset, if any, for this store instruction. */ | |
6383 | short off; | |
6384 | /* Alignment required by this store instruction. */ | |
6385 | int align_to; | |
6386 | /* True for register offsets. */ | |
6387 | int register_offset; | |
6388 | }; | |
6389 | ||
6390 | /* Comparison function used by qsort. */ | |
6391 | ||
6392 | static int | |
6393 | fix_24k_sort (const void *a, const void *b) | |
6394 | { | |
6395 | const struct fix_24k_store_info *pos1 = a; | |
6396 | const struct fix_24k_store_info *pos2 = b; | |
6397 | ||
6398 | return (pos1->off - pos2->off); | |
6399 | } | |
6400 | ||
6401 | /* INSN is a store instruction. Try to record the store information | |
6402 | in STINFO. Return false if the information isn't known. */ | |
6403 | ||
6404 | static bfd_boolean | |
6405 | fix_24k_record_store_info (struct fix_24k_store_info *stinfo, | |
ab9794cf | 6406 | const struct mips_cl_insn *insn) |
15be625d CM |
6407 | { |
6408 | /* The instruction must have a known offset. */ | |
6409 | if (!insn->complete_p || !strstr (insn->insn_mo->args, "o(")) | |
6410 | return FALSE; | |
6411 | ||
6412 | stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE; | |
6413 | stinfo->align_to = fix_24k_align_to (insn->insn_mo); | |
6414 | return TRUE; | |
6415 | } | |
6416 | ||
932d1a1b RS |
6417 | /* Return the number of nops that would be needed to work around the 24k |
6418 | "lost data on stores during refill" errata if instruction INSN | |
6419 | immediately followed the 2 instructions described by HIST. | |
6420 | Ignore hazards that are contained within the first IGNORE | |
6421 | instructions of HIST. | |
6422 | ||
6423 | Problem: The FSB (fetch store buffer) acts as an intermediate buffer | |
6424 | for the data cache refills and store data. The following describes | |
6425 | the scenario where the store data could be lost. | |
6426 | ||
6427 | * A data cache miss, due to either a load or a store, causing fill | |
6428 | data to be supplied by the memory subsystem | |
6429 | * The first three doublewords of fill data are returned and written | |
6430 | into the cache | |
6431 | * A sequence of four stores occurs in consecutive cycles around the | |
6432 | final doubleword of the fill: | |
6433 | * Store A | |
6434 | * Store B | |
6435 | * Store C | |
6436 | * Zero, One or more instructions | |
6437 | * Store D | |
6438 | ||
6439 | The four stores A-D must be to different doublewords of the line that | |
6440 | is being filled. The fourth instruction in the sequence above permits | |
6441 | the fill of the final doubleword to be transferred from the FSB into | |
6442 | the cache. In the sequence above, the stores may be either integer | |
6443 | (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2, | |
6444 | swxc1, sdxc1, suxc1) stores, as long as the four stores are to | |
6445 | different doublewords on the line. If the floating point unit is | |
6446 | running in 1:2 mode, it is not possible to create the sequence above | |
6447 | using only floating point store instructions. | |
15be625d CM |
6448 | |
6449 | In this case, the cache line being filled is incorrectly marked | |
6450 | invalid, thereby losing the data from any store to the line that | |
6451 | occurs between the original miss and the completion of the five | |
6452 | cycle sequence shown above. | |
6453 | ||
932d1a1b | 6454 | The workarounds are: |
15be625d | 6455 | |
932d1a1b RS |
6456 | * Run the data cache in write-through mode. |
6457 | * Insert a non-store instruction between | |
6458 | Store A and Store B or Store B and Store C. */ | |
3739860c | 6459 | |
15be625d | 6460 | static int |
932d1a1b | 6461 | nops_for_24k (int ignore, const struct mips_cl_insn *hist, |
15be625d CM |
6462 | const struct mips_cl_insn *insn) |
6463 | { | |
6464 | struct fix_24k_store_info pos[3]; | |
6465 | int align, i, base_offset; | |
6466 | ||
932d1a1b RS |
6467 | if (ignore >= 2) |
6468 | return 0; | |
6469 | ||
ab9794cf RS |
6470 | /* If the previous instruction wasn't a store, there's nothing to |
6471 | worry about. */ | |
15be625d CM |
6472 | if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) |
6473 | return 0; | |
6474 | ||
ab9794cf RS |
6475 | /* If the instructions after the previous one are unknown, we have |
6476 | to assume the worst. */ | |
6477 | if (!insn) | |
15be625d CM |
6478 | return 1; |
6479 | ||
ab9794cf RS |
6480 | /* Check whether we are dealing with three consecutive stores. */ |
6481 | if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0 | |
6482 | || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) | |
15be625d CM |
6483 | return 0; |
6484 | ||
6485 | /* If we don't know the relationship between the store addresses, | |
6486 | assume the worst. */ | |
ab9794cf | 6487 | if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode) |
15be625d CM |
6488 | || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode)) |
6489 | return 1; | |
6490 | ||
6491 | if (!fix_24k_record_store_info (&pos[0], insn) | |
6492 | || !fix_24k_record_store_info (&pos[1], &hist[0]) | |
6493 | || !fix_24k_record_store_info (&pos[2], &hist[1])) | |
6494 | return 1; | |
6495 | ||
6496 | qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort); | |
6497 | ||
6498 | /* Pick a value of ALIGN and X such that all offsets are adjusted by | |
6499 | X bytes and such that the base register + X is known to be aligned | |
6500 | to align bytes. */ | |
6501 | ||
6502 | if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP) | |
6503 | align = 8; | |
6504 | else | |
6505 | { | |
6506 | align = pos[0].align_to; | |
6507 | base_offset = pos[0].off; | |
6508 | for (i = 1; i < 3; i++) | |
6509 | if (align < pos[i].align_to) | |
6510 | { | |
6511 | align = pos[i].align_to; | |
6512 | base_offset = pos[i].off; | |
6513 | } | |
6514 | for (i = 0; i < 3; i++) | |
6515 | pos[i].off -= base_offset; | |
6516 | } | |
6517 | ||
6518 | pos[0].off &= ~align + 1; | |
6519 | pos[1].off &= ~align + 1; | |
6520 | pos[2].off &= ~align + 1; | |
6521 | ||
6522 | /* If any two stores write to the same chunk, they also write to the | |
6523 | same doubleword. The offsets are still sorted at this point. */ | |
6524 | if (pos[0].off == pos[1].off || pos[1].off == pos[2].off) | |
6525 | return 0; | |
6526 | ||
6527 | /* A range of at least 9 bytes is needed for the stores to be in | |
6528 | non-overlapping doublewords. */ | |
6529 | if (pos[2].off - pos[0].off <= 8) | |
6530 | return 0; | |
6531 | ||
6532 | if (pos[2].off - pos[1].off >= 24 | |
6533 | || pos[1].off - pos[0].off >= 24 | |
6534 | || pos[2].off - pos[0].off >= 32) | |
6535 | return 0; | |
6536 | ||
6537 | return 1; | |
6538 | } | |
6539 | ||
71400594 | 6540 | /* Return the number of nops that would be needed if instruction INSN |
91d6fa6a | 6541 | immediately followed the MAX_NOPS instructions given by HIST, |
932d1a1b RS |
6542 | where HIST[0] is the most recent instruction. Ignore hazards |
6543 | between INSN and the first IGNORE instructions in HIST. | |
6544 | ||
6545 | If INSN is null, return the worse-case number of nops for any | |
6546 | instruction. */ | |
bdaaa2e1 | 6547 | |
71400594 | 6548 | static int |
932d1a1b | 6549 | nops_for_insn (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
6550 | const struct mips_cl_insn *insn) |
6551 | { | |
6552 | int i, nops, tmp_nops; | |
bdaaa2e1 | 6553 | |
71400594 | 6554 | nops = 0; |
932d1a1b | 6555 | for (i = ignore; i < MAX_DELAY_NOPS; i++) |
65b02341 | 6556 | { |
91d6fa6a | 6557 | tmp_nops = insns_between (hist + i, insn) - i; |
65b02341 RS |
6558 | if (tmp_nops > nops) |
6559 | nops = tmp_nops; | |
6560 | } | |
7d8e00cf | 6561 | |
df58fc94 | 6562 | if (mips_fix_vr4130 && !mips_opts.micromips) |
7d8e00cf | 6563 | { |
932d1a1b | 6564 | tmp_nops = nops_for_vr4130 (ignore, hist, insn); |
7d8e00cf RS |
6565 | if (tmp_nops > nops) |
6566 | nops = tmp_nops; | |
6567 | } | |
6568 | ||
df58fc94 | 6569 | if (mips_fix_24k && !mips_opts.micromips) |
15be625d | 6570 | { |
932d1a1b | 6571 | tmp_nops = nops_for_24k (ignore, hist, insn); |
15be625d CM |
6572 | if (tmp_nops > nops) |
6573 | nops = tmp_nops; | |
6574 | } | |
6575 | ||
71400594 RS |
6576 | return nops; |
6577 | } | |
252b5132 | 6578 | |
71400594 | 6579 | /* The variable arguments provide NUM_INSNS extra instructions that |
91d6fa6a | 6580 | might be added to HIST. Return the largest number of nops that |
932d1a1b RS |
6581 | would be needed after the extended sequence, ignoring hazards |
6582 | in the first IGNORE instructions. */ | |
252b5132 | 6583 | |
71400594 | 6584 | static int |
932d1a1b RS |
6585 | nops_for_sequence (int num_insns, int ignore, |
6586 | const struct mips_cl_insn *hist, ...) | |
71400594 RS |
6587 | { |
6588 | va_list args; | |
6589 | struct mips_cl_insn buffer[MAX_NOPS]; | |
6590 | struct mips_cl_insn *cursor; | |
6591 | int nops; | |
6592 | ||
91d6fa6a | 6593 | va_start (args, hist); |
71400594 | 6594 | cursor = buffer + num_insns; |
91d6fa6a | 6595 | memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor)); |
71400594 RS |
6596 | while (cursor > buffer) |
6597 | *--cursor = *va_arg (args, const struct mips_cl_insn *); | |
6598 | ||
932d1a1b | 6599 | nops = nops_for_insn (ignore, buffer, NULL); |
71400594 RS |
6600 | va_end (args); |
6601 | return nops; | |
6602 | } | |
252b5132 | 6603 | |
71400594 RS |
6604 | /* Like nops_for_insn, but if INSN is a branch, take into account the |
6605 | worst-case delay for the branch target. */ | |
252b5132 | 6606 | |
71400594 | 6607 | static int |
932d1a1b | 6608 | nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
6609 | const struct mips_cl_insn *insn) |
6610 | { | |
6611 | int nops, tmp_nops; | |
60b63b72 | 6612 | |
932d1a1b | 6613 | nops = nops_for_insn (ignore, hist, insn); |
11625dd8 | 6614 | if (delayed_branch_p (insn)) |
71400594 | 6615 | { |
932d1a1b | 6616 | tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0, |
14fe068b | 6617 | hist, insn, get_delay_slot_nop (insn)); |
71400594 RS |
6618 | if (tmp_nops > nops) |
6619 | nops = tmp_nops; | |
6620 | } | |
11625dd8 | 6621 | else if (compact_branch_p (insn)) |
71400594 | 6622 | { |
932d1a1b | 6623 | tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn); |
71400594 RS |
6624 | if (tmp_nops > nops) |
6625 | nops = tmp_nops; | |
6626 | } | |
6627 | return nops; | |
6628 | } | |
6629 | ||
c67a084a NC |
6630 | /* Fix NOP issue: Replace nops by "or at,at,zero". */ |
6631 | ||
6632 | static void | |
6633 | fix_loongson2f_nop (struct mips_cl_insn * ip) | |
6634 | { | |
df58fc94 | 6635 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
6636 | if (strcmp (ip->insn_mo->name, "nop") == 0) |
6637 | ip->insn_opcode = LOONGSON2F_NOP_INSN; | |
6638 | } | |
6639 | ||
6640 | /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region | |
6641 | jr target pc &= 'hffff_ffff_cfff_ffff. */ | |
6642 | ||
6643 | static void | |
6644 | fix_loongson2f_jump (struct mips_cl_insn * ip) | |
6645 | { | |
df58fc94 | 6646 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
6647 | if (strcmp (ip->insn_mo->name, "j") == 0 |
6648 | || strcmp (ip->insn_mo->name, "jr") == 0 | |
6649 | || strcmp (ip->insn_mo->name, "jalr") == 0) | |
6650 | { | |
6651 | int sreg; | |
6652 | expressionS ep; | |
6653 | ||
6654 | if (! mips_opts.at) | |
6655 | return; | |
6656 | ||
df58fc94 | 6657 | sreg = EXTRACT_OPERAND (0, RS, *ip); |
c67a084a NC |
6658 | if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG) |
6659 | return; | |
6660 | ||
6661 | ep.X_op = O_constant; | |
6662 | ep.X_add_number = 0xcfff0000; | |
6663 | macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16); | |
6664 | ep.X_add_number = 0xffff; | |
6665 | macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16); | |
6666 | macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG); | |
6667 | } | |
6668 | } | |
6669 | ||
6670 | static void | |
6671 | fix_loongson2f (struct mips_cl_insn * ip) | |
6672 | { | |
6673 | if (mips_fix_loongson2f_nop) | |
6674 | fix_loongson2f_nop (ip); | |
6675 | ||
6676 | if (mips_fix_loongson2f_jump) | |
6677 | fix_loongson2f_jump (ip); | |
6678 | } | |
6679 | ||
a4e06468 RS |
6680 | /* IP is a branch that has a delay slot, and we need to fill it |
6681 | automatically. Return true if we can do that by swapping IP | |
e407c74b NC |
6682 | with the previous instruction. |
6683 | ADDRESS_EXPR is an operand of the instruction to be used with | |
6684 | RELOC_TYPE. */ | |
a4e06468 RS |
6685 | |
6686 | static bfd_boolean | |
e407c74b | 6687 | can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr, |
26545944 | 6688 | bfd_reloc_code_real_type *reloc_type) |
a4e06468 | 6689 | { |
2b0c8b40 | 6690 | unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2; |
a4e06468 | 6691 | unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write; |
9d5de888 | 6692 | unsigned int fpr_read, prev_fpr_write; |
a4e06468 RS |
6693 | |
6694 | /* -O2 and above is required for this optimization. */ | |
6695 | if (mips_optimize < 2) | |
6696 | return FALSE; | |
6697 | ||
6698 | /* If we have seen .set volatile or .set nomove, don't optimize. */ | |
6699 | if (mips_opts.nomove) | |
6700 | return FALSE; | |
6701 | ||
6702 | /* We can't swap if the previous instruction's position is fixed. */ | |
6703 | if (history[0].fixed_p) | |
6704 | return FALSE; | |
6705 | ||
6706 | /* If the previous previous insn was in a .set noreorder, we can't | |
6707 | swap. Actually, the MIPS assembler will swap in this situation. | |
6708 | However, gcc configured -with-gnu-as will generate code like | |
6709 | ||
6710 | .set noreorder | |
6711 | lw $4,XXX | |
6712 | .set reorder | |
6713 | INSN | |
6714 | bne $4,$0,foo | |
6715 | ||
6716 | in which we can not swap the bne and INSN. If gcc is not configured | |
6717 | -with-gnu-as, it does not output the .set pseudo-ops. */ | |
6718 | if (history[1].noreorder_p) | |
6719 | return FALSE; | |
6720 | ||
87333bb7 MR |
6721 | /* If the previous instruction had a fixup in mips16 mode, we can not swap. |
6722 | This means that the previous instruction was a 4-byte one anyhow. */ | |
a4e06468 RS |
6723 | if (mips_opts.mips16 && history[0].fixp[0]) |
6724 | return FALSE; | |
6725 | ||
6726 | /* If the branch is itself the target of a branch, we can not swap. | |
6727 | We cheat on this; all we check for is whether there is a label on | |
6728 | this instruction. If there are any branches to anything other than | |
6729 | a label, users must use .set noreorder. */ | |
6730 | if (seg_info (now_seg)->label_list) | |
6731 | return FALSE; | |
6732 | ||
6733 | /* If the previous instruction is in a variant frag other than this | |
2309ddf2 | 6734 | branch's one, we cannot do the swap. This does not apply to |
9301f9c3 MR |
6735 | MIPS16 code, which uses variant frags for different purposes. */ |
6736 | if (!mips_opts.mips16 | |
a4e06468 RS |
6737 | && history[0].frag |
6738 | && history[0].frag->fr_type == rs_machine_dependent) | |
6739 | return FALSE; | |
6740 | ||
bcd530a7 RS |
6741 | /* We do not swap with instructions that cannot architecturally |
6742 | be placed in a branch delay slot, such as SYNC or ERET. We | |
6743 | also refrain from swapping with a trap instruction, since it | |
6744 | complicates trap handlers to have the trap instruction be in | |
6745 | a delay slot. */ | |
a4e06468 | 6746 | prev_pinfo = history[0].insn_mo->pinfo; |
bcd530a7 | 6747 | if (prev_pinfo & INSN_NO_DELAY_SLOT) |
a4e06468 RS |
6748 | return FALSE; |
6749 | ||
6750 | /* Check for conflicts between the branch and the instructions | |
6751 | before the candidate delay slot. */ | |
6752 | if (nops_for_insn (0, history + 1, ip) > 0) | |
6753 | return FALSE; | |
6754 | ||
6755 | /* Check for conflicts between the swapped sequence and the | |
6756 | target of the branch. */ | |
6757 | if (nops_for_sequence (2, 0, history + 1, ip, history) > 0) | |
6758 | return FALSE; | |
6759 | ||
6760 | /* If the branch reads a register that the previous | |
6761 | instruction sets, we can not swap. */ | |
6762 | gpr_read = gpr_read_mask (ip); | |
6763 | prev_gpr_write = gpr_write_mask (&history[0]); | |
6764 | if (gpr_read & prev_gpr_write) | |
6765 | return FALSE; | |
6766 | ||
9d5de888 CF |
6767 | fpr_read = fpr_read_mask (ip); |
6768 | prev_fpr_write = fpr_write_mask (&history[0]); | |
6769 | if (fpr_read & prev_fpr_write) | |
6770 | return FALSE; | |
6771 | ||
a4e06468 RS |
6772 | /* If the branch writes a register that the previous |
6773 | instruction sets, we can not swap. */ | |
6774 | gpr_write = gpr_write_mask (ip); | |
6775 | if (gpr_write & prev_gpr_write) | |
6776 | return FALSE; | |
6777 | ||
6778 | /* If the branch writes a register that the previous | |
6779 | instruction reads, we can not swap. */ | |
6780 | prev_gpr_read = gpr_read_mask (&history[0]); | |
6781 | if (gpr_write & prev_gpr_read) | |
6782 | return FALSE; | |
6783 | ||
6784 | /* If one instruction sets a condition code and the | |
6785 | other one uses a condition code, we can not swap. */ | |
6786 | pinfo = ip->insn_mo->pinfo; | |
6787 | if ((pinfo & INSN_READ_COND_CODE) | |
6788 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
6789 | return FALSE; | |
6790 | if ((pinfo & INSN_WRITE_COND_CODE) | |
6791 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
6792 | return FALSE; | |
6793 | ||
6794 | /* If the previous instruction uses the PC, we can not swap. */ | |
2b0c8b40 | 6795 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
26545944 | 6796 | if (prev_pinfo2 & INSN2_READ_PC) |
2b0c8b40 | 6797 | return FALSE; |
a4e06468 | 6798 | |
df58fc94 RS |
6799 | /* If the previous instruction has an incorrect size for a fixed |
6800 | branch delay slot in microMIPS mode, we cannot swap. */ | |
2309ddf2 MR |
6801 | pinfo2 = ip->insn_mo->pinfo2; |
6802 | if (mips_opts.micromips | |
6803 | && (pinfo2 & INSN2_BRANCH_DELAY_16BIT) | |
6804 | && insn_length (history) != 2) | |
6805 | return FALSE; | |
6806 | if (mips_opts.micromips | |
6807 | && (pinfo2 & INSN2_BRANCH_DELAY_32BIT) | |
6808 | && insn_length (history) != 4) | |
6809 | return FALSE; | |
6810 | ||
e407c74b NC |
6811 | /* On R5900 short loops need to be fixed by inserting a nop in |
6812 | the branch delay slots. | |
6813 | A short loop can be terminated too early. */ | |
6814 | if (mips_opts.arch == CPU_R5900 | |
6815 | /* Check if instruction has a parameter, ignore "j $31". */ | |
6816 | && (address_expr != NULL) | |
6817 | /* Parameter must be 16 bit. */ | |
6818 | && (*reloc_type == BFD_RELOC_16_PCREL_S2) | |
6819 | /* Branch to same segment. */ | |
41065f5e | 6820 | && (S_GET_SEGMENT (address_expr->X_add_symbol) == now_seg) |
e407c74b | 6821 | /* Branch to same code fragment. */ |
41065f5e | 6822 | && (symbol_get_frag (address_expr->X_add_symbol) == frag_now) |
e407c74b | 6823 | /* Can only calculate branch offset if value is known. */ |
41065f5e | 6824 | && symbol_constant_p (address_expr->X_add_symbol) |
e407c74b NC |
6825 | /* Check if branch is really conditional. */ |
6826 | && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
6827 | || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
6828 | || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
6829 | { | |
6830 | int distance; | |
6831 | /* Check if loop is shorter than 6 instructions including | |
6832 | branch and delay slot. */ | |
41065f5e | 6833 | distance = frag_now_fix () - S_GET_VALUE (address_expr->X_add_symbol); |
e407c74b NC |
6834 | if (distance <= 20) |
6835 | { | |
6836 | int i; | |
6837 | int rv; | |
6838 | ||
6839 | rv = FALSE; | |
6840 | /* When the loop includes branches or jumps, | |
6841 | it is not a short loop. */ | |
6842 | for (i = 0; i < (distance / 4); i++) | |
6843 | { | |
6844 | if ((history[i].cleared_p) | |
41065f5e | 6845 | || delayed_branch_p (&history[i])) |
e407c74b NC |
6846 | { |
6847 | rv = TRUE; | |
6848 | break; | |
6849 | } | |
6850 | } | |
6851 | if (rv == FALSE) | |
6852 | { | |
6853 | /* Insert nop after branch to fix short loop. */ | |
6854 | return FALSE; | |
6855 | } | |
6856 | } | |
6857 | } | |
6858 | ||
a4e06468 RS |
6859 | return TRUE; |
6860 | } | |
6861 | ||
e407c74b NC |
6862 | /* Decide how we should add IP to the instruction stream. |
6863 | ADDRESS_EXPR is an operand of the instruction to be used with | |
6864 | RELOC_TYPE. */ | |
a4e06468 RS |
6865 | |
6866 | static enum append_method | |
e407c74b | 6867 | get_append_method (struct mips_cl_insn *ip, expressionS *address_expr, |
26545944 | 6868 | bfd_reloc_code_real_type *reloc_type) |
a4e06468 | 6869 | { |
a4e06468 RS |
6870 | /* The relaxed version of a macro sequence must be inherently |
6871 | hazard-free. */ | |
6872 | if (mips_relax.sequence == 2) | |
6873 | return APPEND_ADD; | |
6874 | ||
3b821a28 | 6875 | /* We must not dabble with instructions in a ".set noreorder" block. */ |
a4e06468 RS |
6876 | if (mips_opts.noreorder) |
6877 | return APPEND_ADD; | |
6878 | ||
6879 | /* Otherwise, it's our responsibility to fill branch delay slots. */ | |
11625dd8 | 6880 | if (delayed_branch_p (ip)) |
a4e06468 | 6881 | { |
e407c74b NC |
6882 | if (!branch_likely_p (ip) |
6883 | && can_swap_branch_p (ip, address_expr, reloc_type)) | |
a4e06468 RS |
6884 | return APPEND_SWAP; |
6885 | ||
6886 | if (mips_opts.mips16 | |
6887 | && ISA_SUPPORTS_MIPS16E | |
fc76e730 | 6888 | && gpr_read_mask (ip) != 0) |
a4e06468 RS |
6889 | return APPEND_ADD_COMPACT; |
6890 | ||
7bd374a4 MR |
6891 | if (mips_opts.micromips |
6892 | && ((ip->insn_opcode & 0xffe0) == 0x4580 | |
6893 | || (!forced_insn_length | |
6894 | && ((ip->insn_opcode & 0xfc00) == 0xcc00 | |
6895 | || (ip->insn_opcode & 0xdc00) == 0x8c00)) | |
6896 | || (ip->insn_opcode & 0xdfe00000) == 0x94000000 | |
6897 | || (ip->insn_opcode & 0xdc1f0000) == 0x94000000)) | |
6898 | return APPEND_ADD_COMPACT; | |
6899 | ||
a4e06468 RS |
6900 | return APPEND_ADD_WITH_NOP; |
6901 | } | |
6902 | ||
a4e06468 RS |
6903 | return APPEND_ADD; |
6904 | } | |
6905 | ||
7bd374a4 MR |
6906 | /* IP is an instruction whose opcode we have just changed, END points |
6907 | to the end of the opcode table processed. Point IP->insn_mo to the | |
6908 | new opcode's definition. */ | |
ceb94aa5 RS |
6909 | |
6910 | static void | |
7bd374a4 | 6911 | find_altered_opcode (struct mips_cl_insn *ip, const struct mips_opcode *end) |
ceb94aa5 | 6912 | { |
7bd374a4 | 6913 | const struct mips_opcode *mo; |
ceb94aa5 | 6914 | |
ceb94aa5 | 6915 | for (mo = ip->insn_mo; mo < end; mo++) |
7bd374a4 MR |
6916 | if (mo->pinfo != INSN_MACRO |
6917 | && (ip->insn_opcode & mo->mask) == mo->match) | |
ceb94aa5 RS |
6918 | { |
6919 | ip->insn_mo = mo; | |
6920 | return; | |
6921 | } | |
6922 | abort (); | |
6923 | } | |
6924 | ||
7bd374a4 MR |
6925 | /* IP is a MIPS16 instruction whose opcode we have just changed. |
6926 | Point IP->insn_mo to the new opcode's definition. */ | |
6927 | ||
6928 | static void | |
6929 | find_altered_mips16_opcode (struct mips_cl_insn *ip) | |
6930 | { | |
6931 | find_altered_opcode (ip, &mips16_opcodes[bfd_mips16_num_opcodes]); | |
6932 | } | |
6933 | ||
6934 | /* IP is a microMIPS instruction whose opcode we have just changed. | |
6935 | Point IP->insn_mo to the new opcode's definition. */ | |
6936 | ||
6937 | static void | |
6938 | find_altered_micromips_opcode (struct mips_cl_insn *ip) | |
6939 | { | |
6940 | find_altered_opcode (ip, µmips_opcodes[bfd_micromips_num_opcodes]); | |
6941 | } | |
6942 | ||
df58fc94 RS |
6943 | /* For microMIPS macros, we need to generate a local number label |
6944 | as the target of branches. */ | |
6945 | #define MICROMIPS_LABEL_CHAR '\037' | |
6946 | static unsigned long micromips_target_label; | |
6947 | static char micromips_target_name[32]; | |
6948 | ||
6949 | static char * | |
6950 | micromips_label_name (void) | |
6951 | { | |
6952 | char *p = micromips_target_name; | |
6953 | char symbol_name_temporary[24]; | |
6954 | unsigned long l; | |
6955 | int i; | |
6956 | ||
6957 | if (*p) | |
6958 | return p; | |
6959 | ||
6960 | i = 0; | |
6961 | l = micromips_target_label; | |
6962 | #ifdef LOCAL_LABEL_PREFIX | |
6963 | *p++ = LOCAL_LABEL_PREFIX; | |
6964 | #endif | |
6965 | *p++ = 'L'; | |
6966 | *p++ = MICROMIPS_LABEL_CHAR; | |
6967 | do | |
6968 | { | |
6969 | symbol_name_temporary[i++] = l % 10 + '0'; | |
6970 | l /= 10; | |
6971 | } | |
6972 | while (l != 0); | |
6973 | while (i > 0) | |
6974 | *p++ = symbol_name_temporary[--i]; | |
6975 | *p = '\0'; | |
6976 | ||
6977 | return micromips_target_name; | |
6978 | } | |
6979 | ||
6980 | static void | |
6981 | micromips_label_expr (expressionS *label_expr) | |
6982 | { | |
6983 | label_expr->X_op = O_symbol; | |
6984 | label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ()); | |
6985 | label_expr->X_add_number = 0; | |
6986 | } | |
6987 | ||
6988 | static void | |
6989 | micromips_label_inc (void) | |
6990 | { | |
6991 | micromips_target_label++; | |
6992 | *micromips_target_name = '\0'; | |
6993 | } | |
6994 | ||
6995 | static void | |
6996 | micromips_add_label (void) | |
6997 | { | |
6998 | symbolS *s; | |
6999 | ||
7000 | s = colon (micromips_label_name ()); | |
7001 | micromips_label_inc (); | |
f3ded42a | 7002 | S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s))); |
df58fc94 RS |
7003 | } |
7004 | ||
7005 | /* If assembling microMIPS code, then return the microMIPS reloc | |
7006 | corresponding to the requested one if any. Otherwise return | |
7007 | the reloc unchanged. */ | |
7008 | ||
7009 | static bfd_reloc_code_real_type | |
7010 | micromips_map_reloc (bfd_reloc_code_real_type reloc) | |
7011 | { | |
7012 | static const bfd_reloc_code_real_type relocs[][2] = | |
7013 | { | |
7014 | /* Keep sorted incrementally by the left-hand key. */ | |
7015 | { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 }, | |
7016 | { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 }, | |
7017 | { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP }, | |
7018 | { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 }, | |
7019 | { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S }, | |
7020 | { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 }, | |
7021 | { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL }, | |
7022 | { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 }, | |
7023 | { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 }, | |
7024 | { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 }, | |
7025 | { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 }, | |
7026 | { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 }, | |
7027 | { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 }, | |
7028 | { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB }, | |
7029 | { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE }, | |
7030 | { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST }, | |
7031 | { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP }, | |
7032 | { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST }, | |
7033 | { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER }, | |
7034 | { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP }, | |
7035 | { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD }, | |
7036 | { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM }, | |
7037 | { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 }, | |
7038 | { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 }, | |
7039 | { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL }, | |
7040 | { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 }, | |
7041 | { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 } | |
7042 | }; | |
7043 | bfd_reloc_code_real_type r; | |
7044 | size_t i; | |
7045 | ||
7046 | if (!mips_opts.micromips) | |
7047 | return reloc; | |
7048 | for (i = 0; i < ARRAY_SIZE (relocs); i++) | |
7049 | { | |
7050 | r = relocs[i][0]; | |
7051 | if (r > reloc) | |
7052 | return reloc; | |
7053 | if (r == reloc) | |
7054 | return relocs[i][1]; | |
7055 | } | |
7056 | return reloc; | |
7057 | } | |
7058 | ||
b886a2ab RS |
7059 | /* Try to resolve relocation RELOC against constant OPERAND at assembly time. |
7060 | Return true on success, storing the resolved value in RESULT. */ | |
7061 | ||
7062 | static bfd_boolean | |
7063 | calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand, | |
7064 | offsetT *result) | |
7065 | { | |
7066 | switch (reloc) | |
7067 | { | |
7068 | case BFD_RELOC_MIPS_HIGHEST: | |
7069 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
7070 | *result = ((operand + 0x800080008000ull) >> 48) & 0xffff; | |
7071 | return TRUE; | |
7072 | ||
7073 | case BFD_RELOC_MIPS_HIGHER: | |
7074 | case BFD_RELOC_MICROMIPS_HIGHER: | |
7075 | *result = ((operand + 0x80008000ull) >> 32) & 0xffff; | |
7076 | return TRUE; | |
7077 | ||
7078 | case BFD_RELOC_HI16_S: | |
41947d9e | 7079 | case BFD_RELOC_HI16_S_PCREL: |
b886a2ab RS |
7080 | case BFD_RELOC_MICROMIPS_HI16_S: |
7081 | case BFD_RELOC_MIPS16_HI16_S: | |
7082 | *result = ((operand + 0x8000) >> 16) & 0xffff; | |
7083 | return TRUE; | |
7084 | ||
7085 | case BFD_RELOC_HI16: | |
7086 | case BFD_RELOC_MICROMIPS_HI16: | |
7087 | case BFD_RELOC_MIPS16_HI16: | |
7088 | *result = (operand >> 16) & 0xffff; | |
7089 | return TRUE; | |
7090 | ||
7091 | case BFD_RELOC_LO16: | |
41947d9e | 7092 | case BFD_RELOC_LO16_PCREL: |
b886a2ab RS |
7093 | case BFD_RELOC_MICROMIPS_LO16: |
7094 | case BFD_RELOC_MIPS16_LO16: | |
7095 | *result = operand & 0xffff; | |
7096 | return TRUE; | |
7097 | ||
7098 | case BFD_RELOC_UNUSED: | |
7099 | *result = operand; | |
7100 | return TRUE; | |
7101 | ||
7102 | default: | |
7103 | return FALSE; | |
7104 | } | |
7105 | } | |
7106 | ||
71400594 RS |
7107 | /* Output an instruction. IP is the instruction information. |
7108 | ADDRESS_EXPR is an operand of the instruction to be used with | |
df58fc94 RS |
7109 | RELOC_TYPE. EXPANSIONP is true if the instruction is part of |
7110 | a macro expansion. */ | |
71400594 RS |
7111 | |
7112 | static void | |
7113 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
df58fc94 | 7114 | bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp) |
71400594 | 7115 | { |
14fe068b | 7116 | unsigned long prev_pinfo2, pinfo; |
71400594 | 7117 | bfd_boolean relaxed_branch = FALSE; |
a4e06468 | 7118 | enum append_method method; |
2309ddf2 | 7119 | bfd_boolean relax32; |
2b0c8b40 | 7120 | int branch_disp; |
71400594 | 7121 | |
2309ddf2 | 7122 | if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION) |
c67a084a NC |
7123 | fix_loongson2f (ip); |
7124 | ||
738f4d98 | 7125 | file_ase_mips16 |= mips_opts.mips16; |
df58fc94 | 7126 | file_ase_micromips |= mips_opts.micromips; |
738f4d98 | 7127 | |
df58fc94 | 7128 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
71400594 | 7129 | pinfo = ip->insn_mo->pinfo; |
df58fc94 | 7130 | |
7bd374a4 MR |
7131 | /* Don't raise alarm about `nods' frags as they'll fill in the right |
7132 | kind of nop in relaxation if required. */ | |
df58fc94 RS |
7133 | if (mips_opts.micromips |
7134 | && !expansionp | |
7bd374a4 MR |
7135 | && !(history[0].frag |
7136 | && history[0].frag->fr_type == rs_machine_dependent | |
7137 | && RELAX_MICROMIPS_P (history[0].frag->fr_subtype) | |
7138 | && RELAX_MICROMIPS_NODS (history[0].frag->fr_subtype)) | |
df58fc94 RS |
7139 | && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 |
7140 | && micromips_insn_length (ip->insn_mo) != 2) | |
7141 | || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 | |
7142 | && micromips_insn_length (ip->insn_mo) != 4))) | |
1661c76c | 7143 | as_warn (_("wrong size instruction in a %u-bit branch delay slot"), |
df58fc94 | 7144 | (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32); |
71400594 | 7145 | |
15be625d CM |
7146 | if (address_expr == NULL) |
7147 | ip->complete_p = 1; | |
b886a2ab RS |
7148 | else if (reloc_type[0] <= BFD_RELOC_UNUSED |
7149 | && reloc_type[1] == BFD_RELOC_UNUSED | |
7150 | && reloc_type[2] == BFD_RELOC_UNUSED | |
15be625d CM |
7151 | && address_expr->X_op == O_constant) |
7152 | { | |
15be625d CM |
7153 | switch (*reloc_type) |
7154 | { | |
15be625d | 7155 | case BFD_RELOC_MIPS_JMP: |
df58fc94 RS |
7156 | { |
7157 | int shift; | |
7158 | ||
17c6c9d9 MR |
7159 | /* Shift is 2, unusually, for microMIPS JALX. */ |
7160 | shift = (mips_opts.micromips | |
7161 | && strcmp (ip->insn_mo->name, "jalx") != 0) ? 1 : 2; | |
df58fc94 RS |
7162 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) |
7163 | as_bad (_("jump to misaligned address (0x%lx)"), | |
7164 | (unsigned long) address_expr->X_add_number); | |
7165 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
7166 | & 0x3ffffff); | |
335574df | 7167 | ip->complete_p = 1; |
df58fc94 | 7168 | } |
15be625d CM |
7169 | break; |
7170 | ||
7171 | case BFD_RELOC_MIPS16_JMP: | |
7172 | if ((address_expr->X_add_number & 3) != 0) | |
7173 | as_bad (_("jump to misaligned address (0x%lx)"), | |
7174 | (unsigned long) address_expr->X_add_number); | |
7175 | ip->insn_opcode |= | |
7176 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
7177 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
7178 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
335574df | 7179 | ip->complete_p = 1; |
15be625d CM |
7180 | break; |
7181 | ||
7182 | case BFD_RELOC_16_PCREL_S2: | |
df58fc94 RS |
7183 | { |
7184 | int shift; | |
7185 | ||
7186 | shift = mips_opts.micromips ? 1 : 2; | |
7187 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
7188 | as_bad (_("branch to misaligned address (0x%lx)"), | |
7189 | (unsigned long) address_expr->X_add_number); | |
7190 | if (!mips_relax_branch) | |
7191 | { | |
7192 | if ((address_expr->X_add_number + (1 << (shift + 15))) | |
7193 | & ~((1 << (shift + 16)) - 1)) | |
7194 | as_bad (_("branch address range overflow (0x%lx)"), | |
7195 | (unsigned long) address_expr->X_add_number); | |
7196 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
7197 | & 0xffff); | |
7198 | } | |
df58fc94 | 7199 | } |
15be625d CM |
7200 | break; |
7201 | ||
7361da2c AB |
7202 | case BFD_RELOC_MIPS_21_PCREL_S2: |
7203 | { | |
7204 | int shift; | |
7205 | ||
7206 | shift = 2; | |
7207 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
7208 | as_bad (_("branch to misaligned address (0x%lx)"), | |
7209 | (unsigned long) address_expr->X_add_number); | |
7210 | if ((address_expr->X_add_number + (1 << (shift + 20))) | |
7211 | & ~((1 << (shift + 21)) - 1)) | |
7212 | as_bad (_("branch address range overflow (0x%lx)"), | |
7213 | (unsigned long) address_expr->X_add_number); | |
7214 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
7215 | & 0x1fffff); | |
7216 | } | |
7217 | break; | |
7218 | ||
7219 | case BFD_RELOC_MIPS_26_PCREL_S2: | |
7220 | { | |
7221 | int shift; | |
7222 | ||
7223 | shift = 2; | |
7224 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
7225 | as_bad (_("branch to misaligned address (0x%lx)"), | |
7226 | (unsigned long) address_expr->X_add_number); | |
7227 | if ((address_expr->X_add_number + (1 << (shift + 25))) | |
7228 | & ~((1 << (shift + 26)) - 1)) | |
7229 | as_bad (_("branch address range overflow (0x%lx)"), | |
7230 | (unsigned long) address_expr->X_add_number); | |
7231 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
7232 | & 0x3ffffff); | |
7233 | } | |
7234 | break; | |
7235 | ||
15be625d | 7236 | default: |
b886a2ab RS |
7237 | { |
7238 | offsetT value; | |
7239 | ||
7240 | if (calculate_reloc (*reloc_type, address_expr->X_add_number, | |
7241 | &value)) | |
7242 | { | |
7243 | ip->insn_opcode |= value & 0xffff; | |
7244 | ip->complete_p = 1; | |
7245 | } | |
7246 | } | |
7247 | break; | |
7248 | } | |
15be625d CM |
7249 | } |
7250 | ||
71400594 RS |
7251 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
7252 | { | |
7253 | /* There are a lot of optimizations we could do that we don't. | |
7254 | In particular, we do not, in general, reorder instructions. | |
7255 | If you use gcc with optimization, it will reorder | |
7256 | instructions and generally do much more optimization then we | |
7257 | do here; repeating all that work in the assembler would only | |
7258 | benefit hand written assembly code, and does not seem worth | |
7259 | it. */ | |
7260 | int nops = (mips_optimize == 0 | |
932d1a1b RS |
7261 | ? nops_for_insn (0, history, NULL) |
7262 | : nops_for_insn_or_target (0, history, ip)); | |
71400594 | 7263 | if (nops > 0) |
252b5132 RH |
7264 | { |
7265 | fragS *old_frag; | |
7266 | unsigned long old_frag_offset; | |
7267 | int i; | |
252b5132 RH |
7268 | |
7269 | old_frag = frag_now; | |
7270 | old_frag_offset = frag_now_fix (); | |
7271 | ||
7272 | for (i = 0; i < nops; i++) | |
14fe068b RS |
7273 | add_fixed_insn (NOP_INSN); |
7274 | insert_into_history (0, nops, NOP_INSN); | |
252b5132 RH |
7275 | |
7276 | if (listing) | |
7277 | { | |
7278 | listing_prev_line (); | |
7279 | /* We may be at the start of a variant frag. In case we | |
7280 | are, make sure there is enough space for the frag | |
7281 | after the frags created by listing_prev_line. The | |
7282 | argument to frag_grow here must be at least as large | |
7283 | as the argument to all other calls to frag_grow in | |
7284 | this file. We don't have to worry about being in the | |
7285 | middle of a variant frag, because the variants insert | |
7286 | all needed nop instructions themselves. */ | |
7287 | frag_grow (40); | |
7288 | } | |
7289 | ||
462427c4 | 7290 | mips_move_text_labels (); |
252b5132 RH |
7291 | |
7292 | #ifndef NO_ECOFF_DEBUGGING | |
7293 | if (ECOFF_DEBUGGING) | |
7294 | ecoff_fix_loc (old_frag, old_frag_offset); | |
7295 | #endif | |
7296 | } | |
71400594 RS |
7297 | } |
7298 | else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) | |
7299 | { | |
932d1a1b RS |
7300 | int nops; |
7301 | ||
7302 | /* Work out how many nops in prev_nop_frag are needed by IP, | |
7303 | ignoring hazards generated by the first prev_nop_frag_since | |
7304 | instructions. */ | |
7305 | nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip); | |
9c2799c2 | 7306 | gas_assert (nops <= prev_nop_frag_holds); |
252b5132 | 7307 | |
71400594 RS |
7308 | /* Enforce NOPS as a minimum. */ |
7309 | if (nops > prev_nop_frag_required) | |
7310 | prev_nop_frag_required = nops; | |
252b5132 | 7311 | |
71400594 RS |
7312 | if (prev_nop_frag_holds == prev_nop_frag_required) |
7313 | { | |
7314 | /* Settle for the current number of nops. Update the history | |
7315 | accordingly (for the benefit of any future .set reorder code). */ | |
7316 | prev_nop_frag = NULL; | |
7317 | insert_into_history (prev_nop_frag_since, | |
7318 | prev_nop_frag_holds, NOP_INSN); | |
7319 | } | |
7320 | else | |
7321 | { | |
7322 | /* Allow this instruction to replace one of the nops that was | |
7323 | tentatively added to prev_nop_frag. */ | |
df58fc94 | 7324 | prev_nop_frag->fr_fix -= NOP_INSN_SIZE; |
71400594 RS |
7325 | prev_nop_frag_holds--; |
7326 | prev_nop_frag_since++; | |
252b5132 RH |
7327 | } |
7328 | } | |
7329 | ||
e407c74b | 7330 | method = get_append_method (ip, address_expr, reloc_type); |
2b0c8b40 | 7331 | branch_disp = method == APPEND_SWAP ? insn_length (history) : 0; |
a4e06468 | 7332 | |
e410add4 RS |
7333 | dwarf2_emit_insn (0); |
7334 | /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses, | |
7335 | so "move" the instruction address accordingly. | |
7336 | ||
7337 | Also, it doesn't seem appropriate for the assembler to reorder .loc | |
7338 | entries. If this instruction is a branch that we are going to swap | |
7339 | with the previous instruction, the two instructions should be | |
7340 | treated as a unit, and the debug information for both instructions | |
7341 | should refer to the start of the branch sequence. Using the | |
7342 | current position is certainly wrong when swapping a 32-bit branch | |
7343 | and a 16-bit delay slot, since the current position would then be | |
7344 | in the middle of a branch. */ | |
7345 | dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp); | |
58e2ea4d | 7346 | |
df58fc94 RS |
7347 | relax32 = (mips_relax_branch |
7348 | /* Don't try branch relaxation within .set nomacro, or within | |
7349 | .set noat if we use $at for PIC computations. If it turns | |
7350 | out that the branch was out-of-range, we'll get an error. */ | |
7351 | && !mips_opts.warn_about_macros | |
7352 | && (mips_opts.at || mips_pic == NO_PIC) | |
3bf0dbfb MR |
7353 | /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F |
7354 | as they have no complementing branches. */ | |
7355 | && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP))); | |
df58fc94 RS |
7356 | |
7357 | if (!HAVE_CODE_COMPRESSION | |
7358 | && address_expr | |
7359 | && relax32 | |
0b25d3e6 | 7360 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
11625dd8 | 7361 | && delayed_branch_p (ip)) |
4a6a3df4 | 7362 | { |
895921c9 | 7363 | relaxed_branch = TRUE; |
1e915849 RS |
7364 | add_relaxed_insn (ip, (relaxed_branch_length |
7365 | (NULL, NULL, | |
11625dd8 RS |
7366 | uncond_branch_p (ip) ? -1 |
7367 | : branch_likely_p (ip) ? 1 | |
1e915849 RS |
7368 | : 0)), 4, |
7369 | RELAX_BRANCH_ENCODE | |
ce8ad872 | 7370 | (AT, mips_pic != NO_PIC, |
11625dd8 RS |
7371 | uncond_branch_p (ip), |
7372 | branch_likely_p (ip), | |
1e915849 RS |
7373 | pinfo & INSN_WRITE_GPR_31, |
7374 | 0), | |
7375 | address_expr->X_add_symbol, | |
7376 | address_expr->X_add_number); | |
4a6a3df4 AO |
7377 | *reloc_type = BFD_RELOC_UNUSED; |
7378 | } | |
df58fc94 RS |
7379 | else if (mips_opts.micromips |
7380 | && address_expr | |
7381 | && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2) | |
7382 | || *reloc_type > BFD_RELOC_UNUSED) | |
40209cad MR |
7383 | && (delayed_branch_p (ip) || compact_branch_p (ip)) |
7384 | /* Don't try branch relaxation when users specify | |
7385 | 16-bit/32-bit instructions. */ | |
7386 | && !forced_insn_length) | |
df58fc94 | 7387 | { |
7bd374a4 MR |
7388 | bfd_boolean relax16 = (method != APPEND_ADD_COMPACT |
7389 | && *reloc_type > BFD_RELOC_UNUSED); | |
df58fc94 | 7390 | int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0; |
11625dd8 | 7391 | int uncond = uncond_branch_p (ip) ? -1 : 0; |
7bd374a4 MR |
7392 | int compact = compact_branch_p (ip) || method == APPEND_ADD_COMPACT; |
7393 | int nods = method == APPEND_ADD_WITH_NOP; | |
df58fc94 | 7394 | int al = pinfo & INSN_WRITE_GPR_31; |
7bd374a4 | 7395 | int length32 = nods ? 8 : 4; |
df58fc94 RS |
7396 | |
7397 | gas_assert (address_expr != NULL); | |
7398 | gas_assert (!mips_relax.sequence); | |
7399 | ||
2b0c8b40 | 7400 | relaxed_branch = TRUE; |
7bd374a4 MR |
7401 | if (nods) |
7402 | method = APPEND_ADD; | |
7403 | if (relax32) | |
7404 | length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond); | |
7405 | add_relaxed_insn (ip, length32, relax16 ? 2 : 4, | |
8484fb75 | 7406 | RELAX_MICROMIPS_ENCODE (type, AT, mips_opts.insn32, |
ce8ad872 | 7407 | mips_pic != NO_PIC, |
7bd374a4 | 7408 | uncond, compact, al, nods, |
40209cad | 7409 | relax32, 0, 0), |
df58fc94 RS |
7410 | address_expr->X_add_symbol, |
7411 | address_expr->X_add_number); | |
7412 | *reloc_type = BFD_RELOC_UNUSED; | |
7413 | } | |
7414 | else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED) | |
252b5132 | 7415 | { |
7fd53920 MR |
7416 | bfd_boolean require_unextended; |
7417 | bfd_boolean require_extended; | |
88a7ef16 MR |
7418 | symbolS *symbol; |
7419 | offsetT offset; | |
7420 | ||
7fd53920 MR |
7421 | if (forced_insn_length != 0) |
7422 | { | |
7423 | require_unextended = forced_insn_length == 2; | |
7424 | require_extended = forced_insn_length == 4; | |
7425 | } | |
7426 | else | |
7427 | { | |
7428 | require_unextended = (mips_opts.noautoextend | |
7429 | && !mips_opcode_32bit_p (ip->insn_mo)); | |
7430 | require_extended = 0; | |
7431 | } | |
7432 | ||
252b5132 | 7433 | /* We need to set up a variant frag. */ |
df58fc94 | 7434 | gas_assert (address_expr != NULL); |
88a7ef16 MR |
7435 | /* Pass any `O_symbol' expression unchanged as an `expr_section' |
7436 | symbol created by `make_expr_symbol' may not get a necessary | |
7437 | external relocation produced. */ | |
7438 | if (address_expr->X_op == O_symbol) | |
7439 | { | |
7440 | symbol = address_expr->X_add_symbol; | |
7441 | offset = address_expr->X_add_number; | |
7442 | } | |
7443 | else | |
7444 | { | |
7445 | symbol = make_expr_symbol (address_expr); | |
82d808ed | 7446 | symbol_append (symbol, symbol_lastP, &symbol_rootP, &symbol_lastP); |
88a7ef16 MR |
7447 | offset = 0; |
7448 | } | |
8507b6e7 | 7449 | add_relaxed_insn (ip, 12, 0, |
1e915849 RS |
7450 | RELAX_MIPS16_ENCODE |
7451 | (*reloc_type - BFD_RELOC_UNUSED, | |
8507b6e7 MR |
7452 | mips_pic != NO_PIC, |
7453 | HAVE_32BIT_SYMBOLS, | |
7454 | mips_opts.warn_about_macros, | |
7fd53920 | 7455 | require_unextended, require_extended, |
11625dd8 | 7456 | delayed_branch_p (&history[0]), |
1e915849 | 7457 | history[0].mips16_absolute_jump_p), |
88a7ef16 | 7458 | symbol, offset); |
252b5132 | 7459 | } |
5c04167a | 7460 | else if (mips_opts.mips16 && insn_length (ip) == 2) |
9497f5ac | 7461 | { |
11625dd8 | 7462 | if (!delayed_branch_p (ip)) |
b8ee1a6e DU |
7463 | /* Make sure there is enough room to swap this instruction with |
7464 | a following jump instruction. */ | |
7465 | frag_grow (6); | |
1e915849 | 7466 | add_fixed_insn (ip); |
252b5132 RH |
7467 | } |
7468 | else | |
7469 | { | |
7470 | if (mips_opts.mips16 | |
7471 | && mips_opts.noreorder | |
11625dd8 | 7472 | && delayed_branch_p (&history[0])) |
252b5132 RH |
7473 | as_warn (_("extended instruction in delay slot")); |
7474 | ||
4d7206a2 RS |
7475 | if (mips_relax.sequence) |
7476 | { | |
7477 | /* If we've reached the end of this frag, turn it into a variant | |
7478 | frag and record the information for the instructions we've | |
7479 | written so far. */ | |
7480 | if (frag_room () < 4) | |
7481 | relax_close_frag (); | |
df58fc94 | 7482 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip); |
4d7206a2 RS |
7483 | } |
7484 | ||
584892a6 | 7485 | if (mips_relax.sequence != 2) |
df58fc94 RS |
7486 | { |
7487 | if (mips_macro_warning.first_insn_sizes[0] == 0) | |
7488 | mips_macro_warning.first_insn_sizes[0] = insn_length (ip); | |
7489 | mips_macro_warning.sizes[0] += insn_length (ip); | |
7490 | mips_macro_warning.insns[0]++; | |
7491 | } | |
584892a6 | 7492 | if (mips_relax.sequence != 1) |
df58fc94 RS |
7493 | { |
7494 | if (mips_macro_warning.first_insn_sizes[1] == 0) | |
7495 | mips_macro_warning.first_insn_sizes[1] = insn_length (ip); | |
7496 | mips_macro_warning.sizes[1] += insn_length (ip); | |
7497 | mips_macro_warning.insns[1]++; | |
7498 | } | |
584892a6 | 7499 | |
1e915849 RS |
7500 | if (mips_opts.mips16) |
7501 | { | |
7502 | ip->fixed_p = 1; | |
7503 | ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); | |
7504 | } | |
7505 | add_fixed_insn (ip); | |
252b5132 RH |
7506 | } |
7507 | ||
9fe77896 | 7508 | if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 7509 | { |
df58fc94 | 7510 | bfd_reloc_code_real_type final_type[3]; |
2309ddf2 | 7511 | reloc_howto_type *howto0; |
9fe77896 RS |
7512 | reloc_howto_type *howto; |
7513 | int i; | |
34ce925e | 7514 | |
df58fc94 RS |
7515 | /* Perform any necessary conversion to microMIPS relocations |
7516 | and find out how many relocations there actually are. */ | |
7517 | for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++) | |
7518 | final_type[i] = micromips_map_reloc (reloc_type[i]); | |
7519 | ||
9fe77896 RS |
7520 | /* In a compound relocation, it is the final (outermost) |
7521 | operator that determines the relocated field. */ | |
2309ddf2 | 7522 | howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]); |
e8044f35 RS |
7523 | if (!howto) |
7524 | abort (); | |
2309ddf2 MR |
7525 | |
7526 | if (i > 1) | |
7527 | howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]); | |
9fe77896 RS |
7528 | ip->fixp[0] = fix_new_exp (ip->frag, ip->where, |
7529 | bfd_get_reloc_size (howto), | |
7530 | address_expr, | |
2309ddf2 MR |
7531 | howto0 && howto0->pc_relative, |
7532 | final_type[0]); | |
ce8ad872 MR |
7533 | /* Record non-PIC mode in `fx_tcbit2' for `md_apply_fix'. */ |
7534 | ip->fixp[0]->fx_tcbit2 = mips_pic == NO_PIC; | |
9fe77896 RS |
7535 | |
7536 | /* Tag symbols that have a R_MIPS16_26 relocation against them. */ | |
2309ddf2 | 7537 | if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy) |
9fe77896 RS |
7538 | *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1; |
7539 | ||
7540 | /* These relocations can have an addend that won't fit in | |
7541 | 4 octets for 64bit assembly. */ | |
bad1aba3 | 7542 | if (GPR_SIZE == 64 |
9fe77896 RS |
7543 | && ! howto->partial_inplace |
7544 | && (reloc_type[0] == BFD_RELOC_16 | |
7545 | || reloc_type[0] == BFD_RELOC_32 | |
7546 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
7547 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
7548 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
7549 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
7550 | || reloc_type[0] == BFD_RELOC_64 | |
7551 | || reloc_type[0] == BFD_RELOC_CTOR | |
7552 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
7553 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
7554 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
7555 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
7556 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
7557 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT | |
7558 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
7559 | || hi16_reloc_p (reloc_type[0]) | |
7560 | || lo16_reloc_p (reloc_type[0]))) | |
7561 | ip->fixp[0]->fx_no_overflow = 1; | |
7562 | ||
ddaf2c41 MR |
7563 | /* These relocations can have an addend that won't fit in 2 octets. */ |
7564 | if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
7565 | || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1) | |
7566 | ip->fixp[0]->fx_no_overflow = 1; | |
7567 | ||
9fe77896 RS |
7568 | if (mips_relax.sequence) |
7569 | { | |
7570 | if (mips_relax.first_fixup == 0) | |
7571 | mips_relax.first_fixup = ip->fixp[0]; | |
7572 | } | |
7573 | else if (reloc_needs_lo_p (*reloc_type)) | |
7574 | { | |
7575 | struct mips_hi_fixup *hi_fixup; | |
7576 | ||
7577 | /* Reuse the last entry if it already has a matching %lo. */ | |
7578 | hi_fixup = mips_hi_fixup_list; | |
7579 | if (hi_fixup == 0 | |
7580 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
4d7206a2 | 7581 | { |
325801bd | 7582 | hi_fixup = XNEW (struct mips_hi_fixup); |
9fe77896 RS |
7583 | hi_fixup->next = mips_hi_fixup_list; |
7584 | mips_hi_fixup_list = hi_fixup; | |
4d7206a2 | 7585 | } |
9fe77896 RS |
7586 | hi_fixup->fixp = ip->fixp[0]; |
7587 | hi_fixup->seg = now_seg; | |
7588 | } | |
252b5132 | 7589 | |
9fe77896 RS |
7590 | /* Add fixups for the second and third relocations, if given. |
7591 | Note that the ABI allows the second relocation to be | |
7592 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
7593 | moment we only use RSS_UNDEF, but we could add support | |
7594 | for the others if it ever becomes necessary. */ | |
7595 | for (i = 1; i < 3; i++) | |
7596 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
7597 | { | |
7598 | ip->fixp[i] = fix_new (ip->frag, ip->where, | |
7599 | ip->fixp[0]->fx_size, NULL, 0, | |
df58fc94 | 7600 | FALSE, final_type[i]); |
f6688943 | 7601 | |
9fe77896 RS |
7602 | /* Use fx_tcbit to mark compound relocs. */ |
7603 | ip->fixp[0]->fx_tcbit = 1; | |
7604 | ip->fixp[i]->fx_tcbit = 1; | |
7605 | } | |
252b5132 | 7606 | } |
252b5132 RH |
7607 | |
7608 | /* Update the register mask information. */ | |
4c260379 RS |
7609 | mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip); |
7610 | mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip); | |
252b5132 | 7611 | |
a4e06468 | 7612 | switch (method) |
252b5132 | 7613 | { |
a4e06468 RS |
7614 | case APPEND_ADD: |
7615 | insert_into_history (0, 1, ip); | |
7616 | break; | |
7617 | ||
7618 | case APPEND_ADD_WITH_NOP: | |
14fe068b RS |
7619 | { |
7620 | struct mips_cl_insn *nop; | |
7621 | ||
7622 | insert_into_history (0, 1, ip); | |
7623 | nop = get_delay_slot_nop (ip); | |
7624 | add_fixed_insn (nop); | |
7625 | insert_into_history (0, 1, nop); | |
7626 | if (mips_relax.sequence) | |
7627 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop); | |
7628 | } | |
a4e06468 RS |
7629 | break; |
7630 | ||
7631 | case APPEND_ADD_COMPACT: | |
7632 | /* Convert MIPS16 jr/jalr into a "compact" jump. */ | |
7bd374a4 MR |
7633 | if (mips_opts.mips16) |
7634 | { | |
7635 | ip->insn_opcode |= 0x0080; | |
7636 | find_altered_mips16_opcode (ip); | |
7637 | } | |
7638 | /* Convert microMIPS instructions. */ | |
7639 | else if (mips_opts.micromips) | |
7640 | { | |
7641 | /* jr16->jrc */ | |
7642 | if ((ip->insn_opcode & 0xffe0) == 0x4580) | |
7643 | ip->insn_opcode |= 0x0020; | |
7644 | /* b16->bc */ | |
7645 | else if ((ip->insn_opcode & 0xfc00) == 0xcc00) | |
7646 | ip->insn_opcode = 0x40e00000; | |
7647 | /* beqz16->beqzc, bnez16->bnezc */ | |
7648 | else if ((ip->insn_opcode & 0xdc00) == 0x8c00) | |
7649 | { | |
7650 | unsigned long regno; | |
7651 | ||
7652 | regno = ip->insn_opcode >> MICROMIPSOP_SH_MD; | |
7653 | regno &= MICROMIPSOP_MASK_MD; | |
7654 | regno = micromips_to_32_reg_d_map[regno]; | |
7655 | ip->insn_opcode = (((ip->insn_opcode << 9) & 0x00400000) | |
7656 | | (regno << MICROMIPSOP_SH_RS) | |
7657 | | 0x40a00000) ^ 0x00400000; | |
7658 | } | |
7659 | /* beqz->beqzc, bnez->bnezc */ | |
7660 | else if ((ip->insn_opcode & 0xdfe00000) == 0x94000000) | |
7661 | ip->insn_opcode = ((ip->insn_opcode & 0x001f0000) | |
7662 | | ((ip->insn_opcode >> 7) & 0x00400000) | |
7663 | | 0x40a00000) ^ 0x00400000; | |
7664 | /* beq $0->beqzc, bne $0->bnezc */ | |
7665 | else if ((ip->insn_opcode & 0xdc1f0000) == 0x94000000) | |
7666 | ip->insn_opcode = (((ip->insn_opcode >> | |
7667 | (MICROMIPSOP_SH_RT - MICROMIPSOP_SH_RS)) | |
7668 | & (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS)) | |
7669 | | ((ip->insn_opcode >> 7) & 0x00400000) | |
7670 | | 0x40a00000) ^ 0x00400000; | |
7671 | else | |
7672 | abort (); | |
7673 | find_altered_micromips_opcode (ip); | |
7674 | } | |
7675 | else | |
7676 | abort (); | |
a4e06468 RS |
7677 | install_insn (ip); |
7678 | insert_into_history (0, 1, ip); | |
7679 | break; | |
7680 | ||
7681 | case APPEND_SWAP: | |
7682 | { | |
7683 | struct mips_cl_insn delay = history[0]; | |
99e7978b MF |
7684 | |
7685 | if (relaxed_branch || delay.frag != ip->frag) | |
a4e06468 RS |
7686 | { |
7687 | /* Add the delay slot instruction to the end of the | |
7688 | current frag and shrink the fixed part of the | |
7689 | original frag. If the branch occupies the tail of | |
7690 | the latter, move it backwards to cover the gap. */ | |
2b0c8b40 | 7691 | delay.frag->fr_fix -= branch_disp; |
a4e06468 | 7692 | if (delay.frag == ip->frag) |
2b0c8b40 | 7693 | move_insn (ip, ip->frag, ip->where - branch_disp); |
a4e06468 RS |
7694 | add_fixed_insn (&delay); |
7695 | } | |
7696 | else | |
7697 | { | |
5e35670b MR |
7698 | /* If this is not a relaxed branch and we are in the |
7699 | same frag, then just swap the instructions. */ | |
7700 | move_insn (ip, delay.frag, delay.where); | |
7701 | move_insn (&delay, ip->frag, ip->where + insn_length (ip)); | |
a4e06468 RS |
7702 | } |
7703 | history[0] = *ip; | |
7704 | delay.fixed_p = 1; | |
7705 | insert_into_history (0, 1, &delay); | |
7706 | } | |
7707 | break; | |
252b5132 RH |
7708 | } |
7709 | ||
13408f1e | 7710 | /* If we have just completed an unconditional branch, clear the history. */ |
11625dd8 RS |
7711 | if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1])) |
7712 | || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0]))) | |
e407c74b NC |
7713 | { |
7714 | unsigned int i; | |
7715 | ||
79850f26 | 7716 | mips_no_prev_insn (); |
13408f1e | 7717 | |
e407c74b | 7718 | for (i = 0; i < ARRAY_SIZE (history); i++) |
79850f26 | 7719 | history[i].cleared_p = 1; |
e407c74b NC |
7720 | } |
7721 | ||
df58fc94 RS |
7722 | /* We need to emit a label at the end of branch-likely macros. */ |
7723 | if (emit_branch_likely_macro) | |
7724 | { | |
7725 | emit_branch_likely_macro = FALSE; | |
7726 | micromips_add_label (); | |
7727 | } | |
7728 | ||
252b5132 RH |
7729 | /* We just output an insn, so the next one doesn't have a label. */ |
7730 | mips_clear_insn_labels (); | |
252b5132 RH |
7731 | } |
7732 | ||
e407c74b NC |
7733 | /* Forget that there was any previous instruction or label. |
7734 | When BRANCH is true, the branch history is also flushed. */ | |
252b5132 RH |
7735 | |
7736 | static void | |
7d10b47d | 7737 | mips_no_prev_insn (void) |
252b5132 | 7738 | { |
7d10b47d RS |
7739 | prev_nop_frag = NULL; |
7740 | insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); | |
252b5132 RH |
7741 | mips_clear_insn_labels (); |
7742 | } | |
7743 | ||
7d10b47d RS |
7744 | /* This function must be called before we emit something other than |
7745 | instructions. It is like mips_no_prev_insn except that it inserts | |
7746 | any NOPS that might be needed by previous instructions. */ | |
252b5132 | 7747 | |
7d10b47d RS |
7748 | void |
7749 | mips_emit_delays (void) | |
252b5132 RH |
7750 | { |
7751 | if (! mips_opts.noreorder) | |
7752 | { | |
932d1a1b | 7753 | int nops = nops_for_insn (0, history, NULL); |
252b5132 RH |
7754 | if (nops > 0) |
7755 | { | |
7d10b47d RS |
7756 | while (nops-- > 0) |
7757 | add_fixed_insn (NOP_INSN); | |
462427c4 | 7758 | mips_move_text_labels (); |
7d10b47d RS |
7759 | } |
7760 | } | |
7761 | mips_no_prev_insn (); | |
7762 | } | |
7763 | ||
7764 | /* Start a (possibly nested) noreorder block. */ | |
7765 | ||
7766 | static void | |
7767 | start_noreorder (void) | |
7768 | { | |
7769 | if (mips_opts.noreorder == 0) | |
7770 | { | |
7771 | unsigned int i; | |
7772 | int nops; | |
7773 | ||
7774 | /* None of the instructions before the .set noreorder can be moved. */ | |
7775 | for (i = 0; i < ARRAY_SIZE (history); i++) | |
7776 | history[i].fixed_p = 1; | |
7777 | ||
7778 | /* Insert any nops that might be needed between the .set noreorder | |
7779 | block and the previous instructions. We will later remove any | |
7780 | nops that turn out not to be needed. */ | |
932d1a1b | 7781 | nops = nops_for_insn (0, history, NULL); |
7d10b47d RS |
7782 | if (nops > 0) |
7783 | { | |
7784 | if (mips_optimize != 0) | |
252b5132 RH |
7785 | { |
7786 | /* Record the frag which holds the nop instructions, so | |
7787 | that we can remove them if we don't need them. */ | |
df58fc94 | 7788 | frag_grow (nops * NOP_INSN_SIZE); |
252b5132 RH |
7789 | prev_nop_frag = frag_now; |
7790 | prev_nop_frag_holds = nops; | |
7791 | prev_nop_frag_required = 0; | |
7792 | prev_nop_frag_since = 0; | |
7793 | } | |
7794 | ||
7795 | for (; nops > 0; --nops) | |
1e915849 | 7796 | add_fixed_insn (NOP_INSN); |
252b5132 | 7797 | |
7d10b47d RS |
7798 | /* Move on to a new frag, so that it is safe to simply |
7799 | decrease the size of prev_nop_frag. */ | |
7800 | frag_wane (frag_now); | |
7801 | frag_new (0); | |
462427c4 | 7802 | mips_move_text_labels (); |
252b5132 | 7803 | } |
df58fc94 | 7804 | mips_mark_labels (); |
7d10b47d | 7805 | mips_clear_insn_labels (); |
252b5132 | 7806 | } |
7d10b47d RS |
7807 | mips_opts.noreorder++; |
7808 | mips_any_noreorder = 1; | |
7809 | } | |
252b5132 | 7810 | |
7d10b47d | 7811 | /* End a nested noreorder block. */ |
252b5132 | 7812 | |
7d10b47d RS |
7813 | static void |
7814 | end_noreorder (void) | |
7815 | { | |
7816 | mips_opts.noreorder--; | |
7817 | if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) | |
7818 | { | |
7819 | /* Commit to inserting prev_nop_frag_required nops and go back to | |
7820 | handling nop insertion the .set reorder way. */ | |
7821 | prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) | |
df58fc94 | 7822 | * NOP_INSN_SIZE); |
7d10b47d RS |
7823 | insert_into_history (prev_nop_frag_since, |
7824 | prev_nop_frag_required, NOP_INSN); | |
7825 | prev_nop_frag = NULL; | |
7826 | } | |
252b5132 RH |
7827 | } |
7828 | ||
97d87491 RS |
7829 | /* Sign-extend 32-bit mode constants that have bit 31 set and all |
7830 | higher bits unset. */ | |
7831 | ||
7832 | static void | |
7833 | normalize_constant_expr (expressionS *ex) | |
7834 | { | |
7835 | if (ex->X_op == O_constant | |
7836 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
7837 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
7838 | - 0x80000000); | |
7839 | } | |
7840 | ||
7841 | /* Sign-extend 32-bit mode address offsets that have bit 31 set and | |
7842 | all higher bits unset. */ | |
7843 | ||
7844 | static void | |
7845 | normalize_address_expr (expressionS *ex) | |
7846 | { | |
7847 | if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) | |
7848 | || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) | |
7849 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
7850 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
7851 | - 0x80000000); | |
7852 | } | |
7853 | ||
7854 | /* Try to match TOKENS against OPCODE, storing the result in INSN. | |
7855 | Return true if the match was successful. | |
7856 | ||
7857 | OPCODE_EXTRA is a value that should be ORed into the opcode | |
7858 | (used for VU0 channel suffixes, etc.). MORE_ALTS is true if | |
7859 | there are more alternatives after OPCODE and SOFT_MATCH is | |
7860 | as for mips_arg_info. */ | |
7861 | ||
7862 | static bfd_boolean | |
7863 | match_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode, | |
7864 | struct mips_operand_token *tokens, unsigned int opcode_extra, | |
60f20e8b | 7865 | bfd_boolean lax_match, bfd_boolean complete_p) |
97d87491 RS |
7866 | { |
7867 | const char *args; | |
7868 | struct mips_arg_info arg; | |
7869 | const struct mips_operand *operand; | |
7870 | char c; | |
7871 | ||
7872 | imm_expr.X_op = O_absent; | |
97d87491 RS |
7873 | offset_expr.X_op = O_absent; |
7874 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
7875 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
7876 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
7877 | ||
7878 | create_insn (insn, opcode); | |
60f20e8b RS |
7879 | /* When no opcode suffix is specified, assume ".xyzw". */ |
7880 | if ((opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0 && opcode_extra == 0) | |
7881 | insn->insn_opcode |= 0xf << mips_vu0_channel_mask.lsb; | |
7882 | else | |
7883 | insn->insn_opcode |= opcode_extra; | |
97d87491 RS |
7884 | memset (&arg, 0, sizeof (arg)); |
7885 | arg.insn = insn; | |
7886 | arg.token = tokens; | |
7887 | arg.argnum = 1; | |
7888 | arg.last_regno = ILLEGAL_REG; | |
7889 | arg.dest_regno = ILLEGAL_REG; | |
60f20e8b | 7890 | arg.lax_match = lax_match; |
97d87491 RS |
7891 | for (args = opcode->args;; ++args) |
7892 | { | |
7893 | if (arg.token->type == OT_END) | |
7894 | { | |
7895 | /* Handle unary instructions in which only one operand is given. | |
7896 | The source is then the same as the destination. */ | |
7897 | if (arg.opnum == 1 && *args == ',') | |
7898 | { | |
7899 | operand = (mips_opts.micromips | |
7900 | ? decode_micromips_operand (args + 1) | |
7901 | : decode_mips_operand (args + 1)); | |
7902 | if (operand && mips_optional_operand_p (operand)) | |
7903 | { | |
7904 | arg.token = tokens; | |
7905 | arg.argnum = 1; | |
7906 | continue; | |
7907 | } | |
7908 | } | |
7909 | ||
7910 | /* Treat elided base registers as $0. */ | |
7911 | if (strcmp (args, "(b)") == 0) | |
7912 | args += 3; | |
7913 | ||
7914 | if (args[0] == '+') | |
7915 | switch (args[1]) | |
7916 | { | |
7917 | case 'K': | |
7918 | case 'N': | |
7919 | /* The register suffix is optional. */ | |
7920 | args += 2; | |
7921 | break; | |
7922 | } | |
7923 | ||
7924 | /* Fail the match if there were too few operands. */ | |
7925 | if (*args) | |
7926 | return FALSE; | |
7927 | ||
7928 | /* Successful match. */ | |
60f20e8b RS |
7929 | if (!complete_p) |
7930 | return TRUE; | |
e3de51ce | 7931 | clear_insn_error (); |
97d87491 RS |
7932 | if (arg.dest_regno == arg.last_regno |
7933 | && strncmp (insn->insn_mo->name, "jalr", 4) == 0) | |
7934 | { | |
7935 | if (arg.opnum == 2) | |
e3de51ce | 7936 | set_insn_error |
1661c76c | 7937 | (0, _("source and destination must be different")); |
97d87491 | 7938 | else if (arg.last_regno == 31) |
e3de51ce | 7939 | set_insn_error |
1661c76c | 7940 | (0, _("a destination register must be supplied")); |
97d87491 | 7941 | } |
173d3447 CF |
7942 | else if (arg.last_regno == 31 |
7943 | && (strncmp (insn->insn_mo->name, "bltzal", 6) == 0 | |
7944 | || strncmp (insn->insn_mo->name, "bgezal", 6) == 0)) | |
7945 | set_insn_error (0, _("the source register must not be $31")); | |
97d87491 RS |
7946 | check_completed_insn (&arg); |
7947 | return TRUE; | |
7948 | } | |
7949 | ||
7950 | /* Fail the match if the line has too many operands. */ | |
7951 | if (*args == 0) | |
7952 | return FALSE; | |
7953 | ||
7954 | /* Handle characters that need to match exactly. */ | |
7955 | if (*args == '(' || *args == ')' || *args == ',') | |
7956 | { | |
7957 | if (match_char (&arg, *args)) | |
7958 | continue; | |
7959 | return FALSE; | |
7960 | } | |
7961 | if (*args == '#') | |
7962 | { | |
7963 | ++args; | |
7964 | if (arg.token->type == OT_DOUBLE_CHAR | |
7965 | && arg.token->u.ch == *args) | |
7966 | { | |
7967 | ++arg.token; | |
7968 | continue; | |
7969 | } | |
7970 | return FALSE; | |
7971 | } | |
7972 | ||
7973 | /* Handle special macro operands. Work out the properties of | |
7974 | other operands. */ | |
7975 | arg.opnum += 1; | |
97d87491 RS |
7976 | switch (*args) |
7977 | { | |
7361da2c AB |
7978 | case '-': |
7979 | switch (args[1]) | |
7980 | { | |
7981 | case 'A': | |
7982 | *offset_reloc = BFD_RELOC_MIPS_19_PCREL_S2; | |
7983 | break; | |
7984 | ||
7985 | case 'B': | |
7986 | *offset_reloc = BFD_RELOC_MIPS_18_PCREL_S3; | |
7987 | break; | |
7988 | } | |
7989 | break; | |
7990 | ||
97d87491 RS |
7991 | case '+': |
7992 | switch (args[1]) | |
7993 | { | |
97d87491 RS |
7994 | case 'i': |
7995 | *offset_reloc = BFD_RELOC_MIPS_JMP; | |
7996 | break; | |
7361da2c AB |
7997 | |
7998 | case '\'': | |
7999 | *offset_reloc = BFD_RELOC_MIPS_26_PCREL_S2; | |
8000 | break; | |
8001 | ||
8002 | case '\"': | |
8003 | *offset_reloc = BFD_RELOC_MIPS_21_PCREL_S2; | |
8004 | break; | |
97d87491 RS |
8005 | } |
8006 | break; | |
8007 | ||
97d87491 | 8008 | case 'I': |
1a00e612 RS |
8009 | if (!match_const_int (&arg, &imm_expr.X_add_number)) |
8010 | return FALSE; | |
8011 | imm_expr.X_op = O_constant; | |
bad1aba3 | 8012 | if (GPR_SIZE == 32) |
97d87491 RS |
8013 | normalize_constant_expr (&imm_expr); |
8014 | continue; | |
8015 | ||
8016 | case 'A': | |
8017 | if (arg.token->type == OT_CHAR && arg.token->u.ch == '(') | |
8018 | { | |
8019 | /* Assume that the offset has been elided and that what | |
8020 | we saw was a base register. The match will fail later | |
8021 | if that assumption turns out to be wrong. */ | |
8022 | offset_expr.X_op = O_constant; | |
8023 | offset_expr.X_add_number = 0; | |
8024 | } | |
97d87491 | 8025 | else |
1a00e612 RS |
8026 | { |
8027 | if (!match_expression (&arg, &offset_expr, offset_reloc)) | |
8028 | return FALSE; | |
8029 | normalize_address_expr (&offset_expr); | |
8030 | } | |
97d87491 RS |
8031 | continue; |
8032 | ||
8033 | case 'F': | |
8034 | if (!match_float_constant (&arg, &imm_expr, &offset_expr, | |
8035 | 8, TRUE)) | |
1a00e612 | 8036 | return FALSE; |
97d87491 RS |
8037 | continue; |
8038 | ||
8039 | case 'L': | |
8040 | if (!match_float_constant (&arg, &imm_expr, &offset_expr, | |
8041 | 8, FALSE)) | |
1a00e612 | 8042 | return FALSE; |
97d87491 RS |
8043 | continue; |
8044 | ||
8045 | case 'f': | |
8046 | if (!match_float_constant (&arg, &imm_expr, &offset_expr, | |
8047 | 4, TRUE)) | |
1a00e612 | 8048 | return FALSE; |
97d87491 RS |
8049 | continue; |
8050 | ||
8051 | case 'l': | |
8052 | if (!match_float_constant (&arg, &imm_expr, &offset_expr, | |
8053 | 4, FALSE)) | |
1a00e612 | 8054 | return FALSE; |
97d87491 RS |
8055 | continue; |
8056 | ||
97d87491 RS |
8057 | case 'p': |
8058 | *offset_reloc = BFD_RELOC_16_PCREL_S2; | |
8059 | break; | |
8060 | ||
8061 | case 'a': | |
8062 | *offset_reloc = BFD_RELOC_MIPS_JMP; | |
8063 | break; | |
8064 | ||
8065 | case 'm': | |
8066 | gas_assert (mips_opts.micromips); | |
8067 | c = args[1]; | |
8068 | switch (c) | |
8069 | { | |
8070 | case 'D': | |
8071 | case 'E': | |
8072 | if (!forced_insn_length) | |
8073 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; | |
8074 | else if (c == 'D') | |
8075 | *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1; | |
8076 | else | |
8077 | *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1; | |
8078 | break; | |
8079 | } | |
8080 | break; | |
8081 | } | |
8082 | ||
8083 | operand = (mips_opts.micromips | |
8084 | ? decode_micromips_operand (args) | |
8085 | : decode_mips_operand (args)); | |
8086 | if (!operand) | |
8087 | abort (); | |
8088 | ||
8089 | /* Skip prefixes. */ | |
7361da2c | 8090 | if (*args == '+' || *args == 'm' || *args == '-') |
97d87491 RS |
8091 | args++; |
8092 | ||
8093 | if (mips_optional_operand_p (operand) | |
8094 | && args[1] == ',' | |
8095 | && (arg.token[0].type != OT_REG | |
8096 | || arg.token[1].type == OT_END)) | |
8097 | { | |
8098 | /* Assume that the register has been elided and is the | |
8099 | same as the first operand. */ | |
8100 | arg.token = tokens; | |
8101 | arg.argnum = 1; | |
8102 | } | |
8103 | ||
8104 | if (!match_operand (&arg, operand)) | |
8105 | return FALSE; | |
8106 | } | |
8107 | } | |
8108 | ||
8109 | /* Like match_insn, but for MIPS16. */ | |
8110 | ||
8111 | static bfd_boolean | |
8112 | match_mips16_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode, | |
1a00e612 | 8113 | struct mips_operand_token *tokens) |
97d87491 RS |
8114 | { |
8115 | const char *args; | |
8116 | const struct mips_operand *operand; | |
8117 | const struct mips_operand *ext_operand; | |
82d808ed | 8118 | bfd_boolean pcrel = FALSE; |
7fd53920 | 8119 | int required_insn_length; |
97d87491 RS |
8120 | struct mips_arg_info arg; |
8121 | int relax_char; | |
8122 | ||
7fd53920 MR |
8123 | if (forced_insn_length) |
8124 | required_insn_length = forced_insn_length; | |
8125 | else if (mips_opts.noautoextend && !mips_opcode_32bit_p (opcode)) | |
8126 | required_insn_length = 2; | |
8127 | else | |
8128 | required_insn_length = 0; | |
8129 | ||
97d87491 RS |
8130 | create_insn (insn, opcode); |
8131 | imm_expr.X_op = O_absent; | |
97d87491 RS |
8132 | offset_expr.X_op = O_absent; |
8133 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
8134 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
8135 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
8136 | relax_char = 0; | |
8137 | ||
8138 | memset (&arg, 0, sizeof (arg)); | |
8139 | arg.insn = insn; | |
8140 | arg.token = tokens; | |
8141 | arg.argnum = 1; | |
8142 | arg.last_regno = ILLEGAL_REG; | |
8143 | arg.dest_regno = ILLEGAL_REG; | |
97d87491 RS |
8144 | relax_char = 0; |
8145 | for (args = opcode->args;; ++args) | |
8146 | { | |
8147 | int c; | |
8148 | ||
8149 | if (arg.token->type == OT_END) | |
8150 | { | |
8151 | offsetT value; | |
8152 | ||
8153 | /* Handle unary instructions in which only one operand is given. | |
8154 | The source is then the same as the destination. */ | |
8155 | if (arg.opnum == 1 && *args == ',') | |
8156 | { | |
8157 | operand = decode_mips16_operand (args[1], FALSE); | |
8158 | if (operand && mips_optional_operand_p (operand)) | |
8159 | { | |
8160 | arg.token = tokens; | |
8161 | arg.argnum = 1; | |
8162 | continue; | |
8163 | } | |
8164 | } | |
8165 | ||
8166 | /* Fail the match if there were too few operands. */ | |
8167 | if (*args) | |
8168 | return FALSE; | |
8169 | ||
8170 | /* Successful match. Stuff the immediate value in now, if | |
8171 | we can. */ | |
e3de51ce | 8172 | clear_insn_error (); |
97d87491 RS |
8173 | if (opcode->pinfo == INSN_MACRO) |
8174 | { | |
8175 | gas_assert (relax_char == 0 || relax_char == 'p'); | |
8176 | gas_assert (*offset_reloc == BFD_RELOC_UNUSED); | |
8177 | } | |
8178 | else if (relax_char | |
8179 | && offset_expr.X_op == O_constant | |
82d808ed | 8180 | && !pcrel |
97d87491 RS |
8181 | && calculate_reloc (*offset_reloc, |
8182 | offset_expr.X_add_number, | |
8183 | &value)) | |
8184 | { | |
8185 | mips16_immed (NULL, 0, relax_char, *offset_reloc, value, | |
7fd53920 | 8186 | required_insn_length, &insn->insn_opcode); |
97d87491 RS |
8187 | offset_expr.X_op = O_absent; |
8188 | *offset_reloc = BFD_RELOC_UNUSED; | |
8189 | } | |
8190 | else if (relax_char && *offset_reloc != BFD_RELOC_UNUSED) | |
8191 | { | |
7fd53920 | 8192 | if (required_insn_length == 2) |
e3de51ce | 8193 | set_insn_error (0, _("invalid unextended operand value")); |
1da43acc MR |
8194 | else |
8195 | { | |
8196 | forced_insn_length = 4; | |
8197 | insn->insn_opcode |= MIPS16_EXTEND; | |
8198 | } | |
97d87491 RS |
8199 | } |
8200 | else if (relax_char) | |
8201 | *offset_reloc = (int) BFD_RELOC_UNUSED + relax_char; | |
8202 | ||
8203 | check_completed_insn (&arg); | |
8204 | return TRUE; | |
8205 | } | |
8206 | ||
8207 | /* Fail the match if the line has too many operands. */ | |
8208 | if (*args == 0) | |
8209 | return FALSE; | |
8210 | ||
8211 | /* Handle characters that need to match exactly. */ | |
8212 | if (*args == '(' || *args == ')' || *args == ',') | |
8213 | { | |
8214 | if (match_char (&arg, *args)) | |
8215 | continue; | |
8216 | return FALSE; | |
8217 | } | |
8218 | ||
8219 | arg.opnum += 1; | |
8220 | c = *args; | |
8221 | switch (c) | |
8222 | { | |
8223 | case 'p': | |
8224 | case 'q': | |
8225 | case 'A': | |
8226 | case 'B': | |
8227 | case 'E': | |
8228 | relax_char = c; | |
8229 | break; | |
8230 | ||
8231 | case 'I': | |
1a00e612 RS |
8232 | if (!match_const_int (&arg, &imm_expr.X_add_number)) |
8233 | return FALSE; | |
8234 | imm_expr.X_op = O_constant; | |
bad1aba3 | 8235 | if (GPR_SIZE == 32) |
97d87491 RS |
8236 | normalize_constant_expr (&imm_expr); |
8237 | continue; | |
8238 | ||
8239 | case 'a': | |
8240 | case 'i': | |
8241 | *offset_reloc = BFD_RELOC_MIPS16_JMP; | |
97d87491 RS |
8242 | break; |
8243 | } | |
8244 | ||
7fd53920 | 8245 | operand = decode_mips16_operand (c, mips_opcode_32bit_p (opcode)); |
97d87491 RS |
8246 | if (!operand) |
8247 | abort (); | |
8248 | ||
82d808ed MR |
8249 | if (operand->type == OP_PCREL) |
8250 | pcrel = TRUE; | |
8251 | else | |
97d87491 RS |
8252 | { |
8253 | ext_operand = decode_mips16_operand (c, TRUE); | |
8254 | if (operand != ext_operand) | |
8255 | { | |
8256 | if (arg.token->type == OT_CHAR && arg.token->u.ch == '(') | |
8257 | { | |
8258 | offset_expr.X_op = O_constant; | |
8259 | offset_expr.X_add_number = 0; | |
8260 | relax_char = c; | |
8261 | continue; | |
8262 | } | |
8263 | ||
1a7bf198 | 8264 | if (!match_expression (&arg, &offset_expr, offset_reloc)) |
97d87491 RS |
8265 | return FALSE; |
8266 | ||
8267 | /* '8' is used for SLTI(U) and has traditionally not | |
8268 | been allowed to take relocation operators. */ | |
8269 | if (offset_reloc[0] != BFD_RELOC_UNUSED | |
8270 | && (ext_operand->size != 16 || c == '8')) | |
e295202f MR |
8271 | { |
8272 | match_not_constant (&arg); | |
8273 | return FALSE; | |
8274 | } | |
97d87491 | 8275 | |
c96425c5 MR |
8276 | if (offset_expr.X_op == O_big) |
8277 | { | |
8278 | match_out_of_range (&arg); | |
8279 | return FALSE; | |
8280 | } | |
8281 | ||
97d87491 RS |
8282 | relax_char = c; |
8283 | continue; | |
8284 | } | |
8285 | } | |
8286 | ||
8287 | if (mips_optional_operand_p (operand) | |
8288 | && args[1] == ',' | |
8289 | && (arg.token[0].type != OT_REG | |
8290 | || arg.token[1].type == OT_END)) | |
8291 | { | |
8292 | /* Assume that the register has been elided and is the | |
8293 | same as the first operand. */ | |
8294 | arg.token = tokens; | |
8295 | arg.argnum = 1; | |
8296 | } | |
8297 | ||
8298 | if (!match_operand (&arg, operand)) | |
8299 | return FALSE; | |
8300 | } | |
8301 | } | |
8302 | ||
60f20e8b RS |
8303 | /* Record that the current instruction is invalid for the current ISA. */ |
8304 | ||
8305 | static void | |
8306 | match_invalid_for_isa (void) | |
8307 | { | |
8308 | set_insn_error_ss | |
1661c76c | 8309 | (0, _("opcode not supported on this processor: %s (%s)"), |
60f20e8b RS |
8310 | mips_cpu_info_from_arch (mips_opts.arch)->name, |
8311 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
8312 | } | |
8313 | ||
8314 | /* Try to match TOKENS against a series of opcode entries, starting at FIRST. | |
8315 | Return true if a definite match or failure was found, storing any match | |
8316 | in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode | |
8317 | (to handle things like VU0 suffixes). LAX_MATCH is true if we have already | |
8318 | tried and failed to match under normal conditions and now want to try a | |
8319 | more relaxed match. */ | |
8320 | ||
8321 | static bfd_boolean | |
8322 | match_insns (struct mips_cl_insn *insn, const struct mips_opcode *first, | |
8323 | const struct mips_opcode *past, struct mips_operand_token *tokens, | |
8324 | int opcode_extra, bfd_boolean lax_match) | |
8325 | { | |
8326 | const struct mips_opcode *opcode; | |
8327 | const struct mips_opcode *invalid_delay_slot; | |
8328 | bfd_boolean seen_valid_for_isa, seen_valid_for_size; | |
8329 | ||
8330 | /* Search for a match, ignoring alternatives that don't satisfy the | |
8331 | current ISA or forced_length. */ | |
8332 | invalid_delay_slot = 0; | |
8333 | seen_valid_for_isa = FALSE; | |
8334 | seen_valid_for_size = FALSE; | |
8335 | opcode = first; | |
8336 | do | |
8337 | { | |
8338 | gas_assert (strcmp (opcode->name, first->name) == 0); | |
8339 | if (is_opcode_valid (opcode)) | |
8340 | { | |
8341 | seen_valid_for_isa = TRUE; | |
8342 | if (is_size_valid (opcode)) | |
8343 | { | |
8344 | bfd_boolean delay_slot_ok; | |
8345 | ||
8346 | seen_valid_for_size = TRUE; | |
8347 | delay_slot_ok = is_delay_slot_valid (opcode); | |
8348 | if (match_insn (insn, opcode, tokens, opcode_extra, | |
8349 | lax_match, delay_slot_ok)) | |
8350 | { | |
8351 | if (!delay_slot_ok) | |
8352 | { | |
8353 | if (!invalid_delay_slot) | |
8354 | invalid_delay_slot = opcode; | |
8355 | } | |
8356 | else | |
8357 | return TRUE; | |
8358 | } | |
8359 | } | |
8360 | } | |
8361 | ++opcode; | |
8362 | } | |
8363 | while (opcode < past && strcmp (opcode->name, first->name) == 0); | |
8364 | ||
8365 | /* If the only matches we found had the wrong length for the delay slot, | |
8366 | pick the first such match. We'll issue an appropriate warning later. */ | |
8367 | if (invalid_delay_slot) | |
8368 | { | |
8369 | if (match_insn (insn, invalid_delay_slot, tokens, opcode_extra, | |
8370 | lax_match, TRUE)) | |
8371 | return TRUE; | |
8372 | abort (); | |
8373 | } | |
8374 | ||
8375 | /* Handle the case where we didn't try to match an instruction because | |
8376 | all the alternatives were incompatible with the current ISA. */ | |
8377 | if (!seen_valid_for_isa) | |
8378 | { | |
8379 | match_invalid_for_isa (); | |
8380 | return TRUE; | |
8381 | } | |
8382 | ||
8383 | /* Handle the case where we didn't try to match an instruction because | |
8384 | all the alternatives were of the wrong size. */ | |
8385 | if (!seen_valid_for_size) | |
8386 | { | |
8387 | if (mips_opts.insn32) | |
1661c76c | 8388 | set_insn_error (0, _("opcode not supported in the `insn32' mode")); |
60f20e8b RS |
8389 | else |
8390 | set_insn_error_i | |
1661c76c | 8391 | (0, _("unrecognized %d-bit version of microMIPS opcode"), |
60f20e8b RS |
8392 | 8 * forced_insn_length); |
8393 | return TRUE; | |
8394 | } | |
8395 | ||
8396 | return FALSE; | |
8397 | } | |
8398 | ||
8399 | /* Like match_insns, but for MIPS16. */ | |
8400 | ||
8401 | static bfd_boolean | |
8402 | match_mips16_insns (struct mips_cl_insn *insn, const struct mips_opcode *first, | |
8403 | struct mips_operand_token *tokens) | |
8404 | { | |
8405 | const struct mips_opcode *opcode; | |
8406 | bfd_boolean seen_valid_for_isa; | |
7fd53920 | 8407 | bfd_boolean seen_valid_for_size; |
60f20e8b RS |
8408 | |
8409 | /* Search for a match, ignoring alternatives that don't satisfy the | |
8410 | current ISA. There are no separate entries for extended forms so | |
8411 | we deal with forced_length later. */ | |
8412 | seen_valid_for_isa = FALSE; | |
7fd53920 | 8413 | seen_valid_for_size = FALSE; |
60f20e8b RS |
8414 | opcode = first; |
8415 | do | |
8416 | { | |
8417 | gas_assert (strcmp (opcode->name, first->name) == 0); | |
8418 | if (is_opcode_valid_16 (opcode)) | |
8419 | { | |
8420 | seen_valid_for_isa = TRUE; | |
7fd53920 MR |
8421 | if (is_size_valid_16 (opcode)) |
8422 | { | |
8423 | seen_valid_for_size = TRUE; | |
8424 | if (match_mips16_insn (insn, opcode, tokens)) | |
8425 | return TRUE; | |
8426 | } | |
60f20e8b RS |
8427 | } |
8428 | ++opcode; | |
8429 | } | |
8430 | while (opcode < &mips16_opcodes[bfd_mips16_num_opcodes] | |
8431 | && strcmp (opcode->name, first->name) == 0); | |
8432 | ||
8433 | /* Handle the case where we didn't try to match an instruction because | |
8434 | all the alternatives were incompatible with the current ISA. */ | |
8435 | if (!seen_valid_for_isa) | |
8436 | { | |
8437 | match_invalid_for_isa (); | |
8438 | return TRUE; | |
8439 | } | |
8440 | ||
7fd53920 MR |
8441 | /* Handle the case where we didn't try to match an instruction because |
8442 | all the alternatives were of the wrong size. */ | |
8443 | if (!seen_valid_for_size) | |
8444 | { | |
8445 | if (forced_insn_length == 2) | |
8446 | set_insn_error | |
8447 | (0, _("unrecognized unextended version of MIPS16 opcode")); | |
8448 | else | |
8449 | set_insn_error | |
8450 | (0, _("unrecognized extended version of MIPS16 opcode")); | |
8451 | return TRUE; | |
8452 | } | |
8453 | ||
60f20e8b RS |
8454 | return FALSE; |
8455 | } | |
8456 | ||
584892a6 RS |
8457 | /* Set up global variables for the start of a new macro. */ |
8458 | ||
8459 | static void | |
8460 | macro_start (void) | |
8461 | { | |
8462 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
df58fc94 RS |
8463 | memset (&mips_macro_warning.first_insn_sizes, 0, |
8464 | sizeof (mips_macro_warning.first_insn_sizes)); | |
8465 | memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns)); | |
584892a6 | 8466 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder |
11625dd8 | 8467 | && delayed_branch_p (&history[0])); |
7bd374a4 MR |
8468 | if (history[0].frag |
8469 | && history[0].frag->fr_type == rs_machine_dependent | |
8470 | && RELAX_MICROMIPS_P (history[0].frag->fr_subtype) | |
8471 | && RELAX_MICROMIPS_NODS (history[0].frag->fr_subtype)) | |
8472 | mips_macro_warning.delay_slot_length = 0; | |
8473 | else | |
8474 | switch (history[0].insn_mo->pinfo2 | |
8475 | & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT)) | |
8476 | { | |
8477 | case INSN2_BRANCH_DELAY_32BIT: | |
8478 | mips_macro_warning.delay_slot_length = 4; | |
8479 | break; | |
8480 | case INSN2_BRANCH_DELAY_16BIT: | |
8481 | mips_macro_warning.delay_slot_length = 2; | |
8482 | break; | |
8483 | default: | |
8484 | mips_macro_warning.delay_slot_length = 0; | |
8485 | break; | |
8486 | } | |
df58fc94 | 8487 | mips_macro_warning.first_frag = NULL; |
584892a6 RS |
8488 | } |
8489 | ||
df58fc94 RS |
8490 | /* Given that a macro is longer than one instruction or of the wrong size, |
8491 | return the appropriate warning for it. Return null if no warning is | |
8492 | needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT, | |
8493 | RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND, | |
8494 | and RELAX_NOMACRO. */ | |
584892a6 RS |
8495 | |
8496 | static const char * | |
8497 | macro_warning (relax_substateT subtype) | |
8498 | { | |
8499 | if (subtype & RELAX_DELAY_SLOT) | |
1661c76c | 8500 | return _("macro instruction expanded into multiple instructions" |
584892a6 RS |
8501 | " in a branch delay slot"); |
8502 | else if (subtype & RELAX_NOMACRO) | |
1661c76c | 8503 | return _("macro instruction expanded into multiple instructions"); |
df58fc94 RS |
8504 | else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST |
8505 | | RELAX_DELAY_SLOT_SIZE_SECOND)) | |
8506 | return ((subtype & RELAX_DELAY_SLOT_16BIT) | |
1661c76c | 8507 | ? _("macro instruction expanded into a wrong size instruction" |
df58fc94 | 8508 | " in a 16-bit branch delay slot") |
1661c76c | 8509 | : _("macro instruction expanded into a wrong size instruction" |
df58fc94 | 8510 | " in a 32-bit branch delay slot")); |
584892a6 RS |
8511 | else |
8512 | return 0; | |
8513 | } | |
8514 | ||
8515 | /* Finish up a macro. Emit warnings as appropriate. */ | |
8516 | ||
8517 | static void | |
8518 | macro_end (void) | |
8519 | { | |
df58fc94 RS |
8520 | /* Relaxation warning flags. */ |
8521 | relax_substateT subtype = 0; | |
8522 | ||
8523 | /* Check delay slot size requirements. */ | |
8524 | if (mips_macro_warning.delay_slot_length == 2) | |
8525 | subtype |= RELAX_DELAY_SLOT_16BIT; | |
8526 | if (mips_macro_warning.delay_slot_length != 0) | |
584892a6 | 8527 | { |
df58fc94 RS |
8528 | if (mips_macro_warning.delay_slot_length |
8529 | != mips_macro_warning.first_insn_sizes[0]) | |
8530 | subtype |= RELAX_DELAY_SLOT_SIZE_FIRST; | |
8531 | if (mips_macro_warning.delay_slot_length | |
8532 | != mips_macro_warning.first_insn_sizes[1]) | |
8533 | subtype |= RELAX_DELAY_SLOT_SIZE_SECOND; | |
8534 | } | |
584892a6 | 8535 | |
df58fc94 RS |
8536 | /* Check instruction count requirements. */ |
8537 | if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1) | |
8538 | { | |
8539 | if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0]) | |
584892a6 RS |
8540 | subtype |= RELAX_SECOND_LONGER; |
8541 | if (mips_opts.warn_about_macros) | |
8542 | subtype |= RELAX_NOMACRO; | |
8543 | if (mips_macro_warning.delay_slot_p) | |
8544 | subtype |= RELAX_DELAY_SLOT; | |
df58fc94 | 8545 | } |
584892a6 | 8546 | |
df58fc94 RS |
8547 | /* If both alternatives fail to fill a delay slot correctly, |
8548 | emit the warning now. */ | |
8549 | if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0 | |
8550 | && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0) | |
8551 | { | |
8552 | relax_substateT s; | |
8553 | const char *msg; | |
8554 | ||
8555 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
8556 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
8557 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
8558 | msg = macro_warning (s); | |
8559 | if (msg != NULL) | |
8560 | as_warn ("%s", msg); | |
8561 | subtype &= ~s; | |
8562 | } | |
8563 | ||
8564 | /* If both implementations are longer than 1 instruction, then emit the | |
8565 | warning now. */ | |
8566 | if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1) | |
8567 | { | |
8568 | relax_substateT s; | |
8569 | const char *msg; | |
8570 | ||
8571 | s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT); | |
8572 | msg = macro_warning (s); | |
8573 | if (msg != NULL) | |
8574 | as_warn ("%s", msg); | |
8575 | subtype &= ~s; | |
584892a6 | 8576 | } |
df58fc94 RS |
8577 | |
8578 | /* If any flags still set, then one implementation might need a warning | |
8579 | and the other either will need one of a different kind or none at all. | |
8580 | Pass any remaining flags over to relaxation. */ | |
8581 | if (mips_macro_warning.first_frag != NULL) | |
8582 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
584892a6 RS |
8583 | } |
8584 | ||
df58fc94 RS |
8585 | /* Instruction operand formats used in macros that vary between |
8586 | standard MIPS and microMIPS code. */ | |
8587 | ||
833794fc | 8588 | static const char * const brk_fmt[2][2] = { { "c", "c" }, { "mF", "c" } }; |
df58fc94 RS |
8589 | static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" }; |
8590 | static const char * const jalr_fmt[2] = { "d,s", "t,s" }; | |
8591 | static const char * const lui_fmt[2] = { "t,u", "s,u" }; | |
8592 | static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" }; | |
833794fc | 8593 | static const char * const mfhl_fmt[2][2] = { { "d", "d" }, { "mj", "s" } }; |
df58fc94 RS |
8594 | static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" }; |
8595 | static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" }; | |
8596 | ||
833794fc | 8597 | #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32]) |
7361da2c AB |
8598 | #define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \ |
8599 | : cop12_fmt[mips_opts.micromips]) | |
df58fc94 RS |
8600 | #define JALR_FMT (jalr_fmt[mips_opts.micromips]) |
8601 | #define LUI_FMT (lui_fmt[mips_opts.micromips]) | |
8602 | #define MEM12_FMT (mem12_fmt[mips_opts.micromips]) | |
7361da2c AB |
8603 | #define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \ |
8604 | : mem12_fmt[mips_opts.micromips]) | |
833794fc | 8605 | #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32]) |
df58fc94 RS |
8606 | #define SHFT_FMT (shft_fmt[mips_opts.micromips]) |
8607 | #define TRAP_FMT (trap_fmt[mips_opts.micromips]) | |
8608 | ||
6e1304d8 RS |
8609 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
8610 | The first argument in *ARGS will be either the code for a single | |
8611 | relocation or -1 followed by the three codes that make up a | |
8612 | composite relocation. */ | |
8613 | ||
8614 | static void | |
8615 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
8616 | { | |
8617 | int i, next; | |
8618 | ||
8619 | next = va_arg (*args, int); | |
8620 | if (next >= 0) | |
8621 | r[0] = (bfd_reloc_code_real_type) next; | |
8622 | else | |
f2ae14a1 RS |
8623 | { |
8624 | for (i = 0; i < 3; i++) | |
8625 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
8626 | /* This function is only used for 16-bit relocation fields. | |
8627 | To make the macro code simpler, treat an unrelocated value | |
8628 | in the same way as BFD_RELOC_LO16. */ | |
8629 | if (r[0] == BFD_RELOC_UNUSED) | |
8630 | r[0] = BFD_RELOC_LO16; | |
8631 | } | |
6e1304d8 RS |
8632 | } |
8633 | ||
252b5132 RH |
8634 | /* Build an instruction created by a macro expansion. This is passed |
8635 | a pointer to the count of instructions created so far, an | |
8636 | expression, the name of the instruction to build, an operand format | |
8637 | string, and corresponding arguments. */ | |
8638 | ||
252b5132 | 8639 | static void |
67c0d1eb | 8640 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 | 8641 | { |
df58fc94 | 8642 | const struct mips_opcode *mo = NULL; |
f6688943 | 8643 | bfd_reloc_code_real_type r[3]; |
df58fc94 | 8644 | const struct mips_opcode *amo; |
e077a1c8 | 8645 | const struct mips_operand *operand; |
df58fc94 RS |
8646 | struct hash_control *hash; |
8647 | struct mips_cl_insn insn; | |
252b5132 | 8648 | va_list args; |
e077a1c8 | 8649 | unsigned int uval; |
252b5132 | 8650 | |
252b5132 | 8651 | va_start (args, fmt); |
252b5132 | 8652 | |
252b5132 RH |
8653 | if (mips_opts.mips16) |
8654 | { | |
03ea81db | 8655 | mips16_macro_build (ep, name, fmt, &args); |
252b5132 RH |
8656 | va_end (args); |
8657 | return; | |
8658 | } | |
8659 | ||
f6688943 TS |
8660 | r[0] = BFD_RELOC_UNUSED; |
8661 | r[1] = BFD_RELOC_UNUSED; | |
8662 | r[2] = BFD_RELOC_UNUSED; | |
df58fc94 RS |
8663 | hash = mips_opts.micromips ? micromips_op_hash : op_hash; |
8664 | amo = (struct mips_opcode *) hash_find (hash, name); | |
8665 | gas_assert (amo); | |
8666 | gas_assert (strcmp (name, amo->name) == 0); | |
1e915849 | 8667 | |
df58fc94 | 8668 | do |
8b082fb1 TS |
8669 | { |
8670 | /* Search until we get a match for NAME. It is assumed here that | |
df58fc94 | 8671 | macros will never generate MDMX, MIPS-3D, or MT instructions. |
33eaf5de | 8672 | We try to match an instruction that fulfills the branch delay |
df58fc94 RS |
8673 | slot instruction length requirement (if any) of the previous |
8674 | instruction. While doing this we record the first instruction | |
8675 | seen that matches all the other conditions and use it anyway | |
8676 | if the requirement cannot be met; we will issue an appropriate | |
8677 | warning later on. */ | |
8678 | if (strcmp (fmt, amo->args) == 0 | |
8679 | && amo->pinfo != INSN_MACRO | |
8680 | && is_opcode_valid (amo) | |
8681 | && is_size_valid (amo)) | |
8682 | { | |
8683 | if (is_delay_slot_valid (amo)) | |
8684 | { | |
8685 | mo = amo; | |
8686 | break; | |
8687 | } | |
8688 | else if (!mo) | |
8689 | mo = amo; | |
8690 | } | |
8b082fb1 | 8691 | |
df58fc94 RS |
8692 | ++amo; |
8693 | gas_assert (amo->name); | |
252b5132 | 8694 | } |
df58fc94 | 8695 | while (strcmp (name, amo->name) == 0); |
252b5132 | 8696 | |
df58fc94 | 8697 | gas_assert (mo); |
1e915849 | 8698 | create_insn (&insn, mo); |
e077a1c8 | 8699 | for (; *fmt; ++fmt) |
252b5132 | 8700 | { |
e077a1c8 | 8701 | switch (*fmt) |
252b5132 | 8702 | { |
252b5132 RH |
8703 | case ',': |
8704 | case '(': | |
8705 | case ')': | |
252b5132 | 8706 | case 'z': |
e077a1c8 | 8707 | break; |
252b5132 RH |
8708 | |
8709 | case 'i': | |
8710 | case 'j': | |
6e1304d8 | 8711 | macro_read_relocs (&args, r); |
9c2799c2 | 8712 | gas_assert (*r == BFD_RELOC_GPREL16 |
e391c024 RS |
8713 | || *r == BFD_RELOC_MIPS_HIGHER |
8714 | || *r == BFD_RELOC_HI16_S | |
8715 | || *r == BFD_RELOC_LO16 | |
8716 | || *r == BFD_RELOC_MIPS_GOT_OFST); | |
e077a1c8 | 8717 | break; |
e391c024 RS |
8718 | |
8719 | case 'o': | |
8720 | macro_read_relocs (&args, r); | |
e077a1c8 | 8721 | break; |
252b5132 RH |
8722 | |
8723 | case 'u': | |
6e1304d8 | 8724 | macro_read_relocs (&args, r); |
9c2799c2 | 8725 | gas_assert (ep != NULL |
90ecf173 MR |
8726 | && (ep->X_op == O_constant |
8727 | || (ep->X_op == O_symbol | |
8728 | && (*r == BFD_RELOC_MIPS_HIGHEST | |
8729 | || *r == BFD_RELOC_HI16_S | |
8730 | || *r == BFD_RELOC_HI16 | |
8731 | || *r == BFD_RELOC_GPREL16 | |
8732 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
8733 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); | |
e077a1c8 | 8734 | break; |
252b5132 RH |
8735 | |
8736 | case 'p': | |
9c2799c2 | 8737 | gas_assert (ep != NULL); |
bad36eac | 8738 | |
252b5132 RH |
8739 | /* |
8740 | * This allows macro() to pass an immediate expression for | |
8741 | * creating short branches without creating a symbol. | |
bad36eac DJ |
8742 | * |
8743 | * We don't allow branch relaxation for these branches, as | |
8744 | * they should only appear in ".set nomacro" anyway. | |
252b5132 RH |
8745 | */ |
8746 | if (ep->X_op == O_constant) | |
8747 | { | |
df58fc94 RS |
8748 | /* For microMIPS we always use relocations for branches. |
8749 | So we should not resolve immediate values. */ | |
8750 | gas_assert (!mips_opts.micromips); | |
8751 | ||
bad36eac DJ |
8752 | if ((ep->X_add_number & 3) != 0) |
8753 | as_bad (_("branch to misaligned address (0x%lx)"), | |
8754 | (unsigned long) ep->X_add_number); | |
8755 | if ((ep->X_add_number + 0x20000) & ~0x3ffff) | |
8756 | as_bad (_("branch address range overflow (0x%lx)"), | |
8757 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
8758 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; |
8759 | ep = NULL; | |
8760 | } | |
8761 | else | |
0b25d3e6 | 8762 | *r = BFD_RELOC_16_PCREL_S2; |
e077a1c8 | 8763 | break; |
252b5132 RH |
8764 | |
8765 | case 'a': | |
9c2799c2 | 8766 | gas_assert (ep != NULL); |
f6688943 | 8767 | *r = BFD_RELOC_MIPS_JMP; |
e077a1c8 | 8768 | break; |
d43b4baf | 8769 | |
252b5132 | 8770 | default: |
e077a1c8 RS |
8771 | operand = (mips_opts.micromips |
8772 | ? decode_micromips_operand (fmt) | |
8773 | : decode_mips_operand (fmt)); | |
8774 | if (!operand) | |
8775 | abort (); | |
8776 | ||
8777 | uval = va_arg (args, int); | |
8778 | if (operand->type == OP_CLO_CLZ_DEST) | |
8779 | uval |= (uval << 5); | |
8780 | insn_insert_operand (&insn, operand, uval); | |
8781 | ||
7361da2c | 8782 | if (*fmt == '+' || *fmt == 'm' || *fmt == '-') |
e077a1c8 RS |
8783 | ++fmt; |
8784 | break; | |
252b5132 | 8785 | } |
252b5132 RH |
8786 | } |
8787 | va_end (args); | |
9c2799c2 | 8788 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 8789 | |
df58fc94 | 8790 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
8791 | } |
8792 | ||
8793 | static void | |
67c0d1eb | 8794 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
03ea81db | 8795 | va_list *args) |
252b5132 | 8796 | { |
1e915849 | 8797 | struct mips_opcode *mo; |
252b5132 | 8798 | struct mips_cl_insn insn; |
e077a1c8 | 8799 | const struct mips_operand *operand; |
f6688943 TS |
8800 | bfd_reloc_code_real_type r[3] |
8801 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 8802 | |
1e915849 | 8803 | mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
9c2799c2 NC |
8804 | gas_assert (mo); |
8805 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 | 8806 | |
1e915849 | 8807 | while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) |
252b5132 | 8808 | { |
1e915849 | 8809 | ++mo; |
9c2799c2 NC |
8810 | gas_assert (mo->name); |
8811 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
8812 | } |
8813 | ||
1e915849 | 8814 | create_insn (&insn, mo); |
e077a1c8 | 8815 | for (; *fmt; ++fmt) |
252b5132 RH |
8816 | { |
8817 | int c; | |
8818 | ||
e077a1c8 | 8819 | c = *fmt; |
252b5132 RH |
8820 | switch (c) |
8821 | { | |
252b5132 RH |
8822 | case ',': |
8823 | case '(': | |
8824 | case ')': | |
e077a1c8 | 8825 | break; |
252b5132 | 8826 | |
d8722d76 | 8827 | case '.': |
252b5132 RH |
8828 | case 'S': |
8829 | case 'P': | |
8830 | case 'R': | |
e077a1c8 | 8831 | break; |
252b5132 RH |
8832 | |
8833 | case '<': | |
252b5132 | 8834 | case '5': |
d8722d76 | 8835 | case 'F': |
252b5132 RH |
8836 | case 'H': |
8837 | case 'W': | |
8838 | case 'D': | |
8839 | case 'j': | |
8840 | case '8': | |
8841 | case 'V': | |
8842 | case 'C': | |
8843 | case 'U': | |
8844 | case 'k': | |
8845 | case 'K': | |
8846 | case 'p': | |
8847 | case 'q': | |
8848 | { | |
b886a2ab RS |
8849 | offsetT value; |
8850 | ||
9c2799c2 | 8851 | gas_assert (ep != NULL); |
252b5132 RH |
8852 | |
8853 | if (ep->X_op != O_constant) | |
874e8986 | 8854 | *r = (int) BFD_RELOC_UNUSED + c; |
b886a2ab | 8855 | else if (calculate_reloc (*r, ep->X_add_number, &value)) |
252b5132 | 8856 | { |
b886a2ab | 8857 | mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode); |
252b5132 | 8858 | ep = NULL; |
f6688943 | 8859 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
8860 | } |
8861 | } | |
e077a1c8 | 8862 | break; |
252b5132 | 8863 | |
e077a1c8 RS |
8864 | default: |
8865 | operand = decode_mips16_operand (c, FALSE); | |
8866 | if (!operand) | |
8867 | abort (); | |
252b5132 | 8868 | |
4a06e5a2 | 8869 | insn_insert_operand (&insn, operand, va_arg (*args, int)); |
e077a1c8 RS |
8870 | break; |
8871 | } | |
252b5132 RH |
8872 | } |
8873 | ||
9c2799c2 | 8874 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 8875 | |
df58fc94 | 8876 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
8877 | } |
8878 | ||
438c16b8 TS |
8879 | /* |
8880 | * Generate a "jalr" instruction with a relocation hint to the called | |
8881 | * function. This occurs in NewABI PIC code. | |
8882 | */ | |
8883 | static void | |
df58fc94 | 8884 | macro_build_jalr (expressionS *ep, int cprestore) |
438c16b8 | 8885 | { |
df58fc94 RS |
8886 | static const bfd_reloc_code_real_type jalr_relocs[2] |
8887 | = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR }; | |
8888 | bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips]; | |
8889 | const char *jalr; | |
685736be | 8890 | char *f = NULL; |
b34976b6 | 8891 | |
1180b5a4 | 8892 | if (MIPS_JALR_HINT_P (ep)) |
f21f8242 | 8893 | { |
cc3d92a5 | 8894 | frag_grow (8); |
f21f8242 AO |
8895 | f = frag_more (0); |
8896 | } | |
2906b037 | 8897 | if (mips_opts.micromips) |
df58fc94 | 8898 | { |
833794fc MR |
8899 | jalr = ((mips_opts.noreorder && !cprestore) || mips_opts.insn32 |
8900 | ? "jalr" : "jalrs"); | |
e64af278 | 8901 | if (MIPS_JALR_HINT_P (ep) |
833794fc | 8902 | || mips_opts.insn32 |
e64af278 | 8903 | || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
df58fc94 RS |
8904 | macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG); |
8905 | else | |
8906 | macro_build (NULL, jalr, "mj", PIC_CALL_REG); | |
8907 | } | |
2906b037 MR |
8908 | else |
8909 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); | |
1180b5a4 | 8910 | if (MIPS_JALR_HINT_P (ep)) |
df58fc94 | 8911 | fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc); |
438c16b8 TS |
8912 | } |
8913 | ||
252b5132 RH |
8914 | /* |
8915 | * Generate a "lui" instruction. | |
8916 | */ | |
8917 | static void | |
67c0d1eb | 8918 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 | 8919 | { |
9c2799c2 | 8920 | gas_assert (! mips_opts.mips16); |
252b5132 | 8921 | |
df58fc94 | 8922 | if (ep->X_op != O_constant) |
252b5132 | 8923 | { |
9c2799c2 | 8924 | gas_assert (ep->X_op == O_symbol); |
bbe506e8 TS |
8925 | /* _gp_disp is a special case, used from s_cpload. |
8926 | __gnu_local_gp is used if mips_no_shared. */ | |
9c2799c2 | 8927 | gas_assert (mips_pic == NO_PIC |
78e1bb40 | 8928 | || (! HAVE_NEWABI |
aa6975fb ILT |
8929 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
8930 | || (! mips_in_shared | |
bbe506e8 TS |
8931 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
8932 | "__gnu_local_gp") == 0)); | |
252b5132 RH |
8933 | } |
8934 | ||
df58fc94 | 8935 | macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S); |
252b5132 RH |
8936 | } |
8937 | ||
885add95 CD |
8938 | /* Generate a sequence of instructions to do a load or store from a constant |
8939 | offset off of a base register (breg) into/from a target register (treg), | |
8940 | using AT if necessary. */ | |
8941 | static void | |
67c0d1eb RS |
8942 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
8943 | int treg, int breg, int dbl) | |
885add95 | 8944 | { |
9c2799c2 | 8945 | gas_assert (ep->X_op == O_constant); |
885add95 | 8946 | |
256ab948 | 8947 | /* Sign-extending 32-bit constants makes their handling easier. */ |
2051e8c4 MR |
8948 | if (!dbl) |
8949 | normalize_constant_expr (ep); | |
256ab948 | 8950 | |
67c1ffbe | 8951 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 8952 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
8953 | as_warn (_("operand overflow")); |
8954 | ||
8955 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
8956 | { | |
8957 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 8958 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
8959 | } |
8960 | else | |
8961 | { | |
8962 | /* 32-bit offset, need multiple instructions and AT, like: | |
8963 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
8964 | addu $tempreg,$tempreg,$breg | |
8965 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
8966 | to handle the complete offset. */ | |
67c0d1eb RS |
8967 | macro_build_lui (ep, AT); |
8968 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
8969 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 | 8970 | |
741fe287 | 8971 | if (!mips_opts.at) |
1661c76c | 8972 | as_bad (_("macro used $at after \".set noat\"")); |
885add95 CD |
8973 | } |
8974 | } | |
8975 | ||
252b5132 RH |
8976 | /* set_at() |
8977 | * Generates code to set the $at register to true (one) | |
8978 | * if reg is less than the immediate expression. | |
8979 | */ | |
8980 | static void | |
67c0d1eb | 8981 | set_at (int reg, int unsignedp) |
252b5132 | 8982 | { |
b0e6f033 | 8983 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 | 8984 | && imm_expr.X_add_number < 0x8000) |
67c0d1eb RS |
8985 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
8986 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
8987 | else |
8988 | { | |
bad1aba3 | 8989 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
67c0d1eb | 8990 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); |
252b5132 RH |
8991 | } |
8992 | } | |
8993 | ||
252b5132 RH |
8994 | /* Count the leading zeroes by performing a binary chop. This is a |
8995 | bulky bit of source, but performance is a LOT better for the | |
8996 | majority of values than a simple loop to count the bits: | |
8997 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
8998 | if ((v) & (1 << (31 - lcnt))) | |
8999 | break; | |
9000 | However it is not code size friendly, and the gain will drop a bit | |
9001 | on certain cached systems. | |
9002 | */ | |
9003 | #define COUNT_TOP_ZEROES(v) \ | |
9004 | (((v) & ~0xffff) == 0 \ | |
9005 | ? ((v) & ~0xff) == 0 \ | |
9006 | ? ((v) & ~0xf) == 0 \ | |
9007 | ? ((v) & ~0x3) == 0 \ | |
9008 | ? ((v) & ~0x1) == 0 \ | |
9009 | ? !(v) \ | |
9010 | ? 32 \ | |
9011 | : 31 \ | |
9012 | : 30 \ | |
9013 | : ((v) & ~0x7) == 0 \ | |
9014 | ? 29 \ | |
9015 | : 28 \ | |
9016 | : ((v) & ~0x3f) == 0 \ | |
9017 | ? ((v) & ~0x1f) == 0 \ | |
9018 | ? 27 \ | |
9019 | : 26 \ | |
9020 | : ((v) & ~0x7f) == 0 \ | |
9021 | ? 25 \ | |
9022 | : 24 \ | |
9023 | : ((v) & ~0xfff) == 0 \ | |
9024 | ? ((v) & ~0x3ff) == 0 \ | |
9025 | ? ((v) & ~0x1ff) == 0 \ | |
9026 | ? 23 \ | |
9027 | : 22 \ | |
9028 | : ((v) & ~0x7ff) == 0 \ | |
9029 | ? 21 \ | |
9030 | : 20 \ | |
9031 | : ((v) & ~0x3fff) == 0 \ | |
9032 | ? ((v) & ~0x1fff) == 0 \ | |
9033 | ? 19 \ | |
9034 | : 18 \ | |
9035 | : ((v) & ~0x7fff) == 0 \ | |
9036 | ? 17 \ | |
9037 | : 16 \ | |
9038 | : ((v) & ~0xffffff) == 0 \ | |
9039 | ? ((v) & ~0xfffff) == 0 \ | |
9040 | ? ((v) & ~0x3ffff) == 0 \ | |
9041 | ? ((v) & ~0x1ffff) == 0 \ | |
9042 | ? 15 \ | |
9043 | : 14 \ | |
9044 | : ((v) & ~0x7ffff) == 0 \ | |
9045 | ? 13 \ | |
9046 | : 12 \ | |
9047 | : ((v) & ~0x3fffff) == 0 \ | |
9048 | ? ((v) & ~0x1fffff) == 0 \ | |
9049 | ? 11 \ | |
9050 | : 10 \ | |
9051 | : ((v) & ~0x7fffff) == 0 \ | |
9052 | ? 9 \ | |
9053 | : 8 \ | |
9054 | : ((v) & ~0xfffffff) == 0 \ | |
9055 | ? ((v) & ~0x3ffffff) == 0 \ | |
9056 | ? ((v) & ~0x1ffffff) == 0 \ | |
9057 | ? 7 \ | |
9058 | : 6 \ | |
9059 | : ((v) & ~0x7ffffff) == 0 \ | |
9060 | ? 5 \ | |
9061 | : 4 \ | |
9062 | : ((v) & ~0x3fffffff) == 0 \ | |
9063 | ? ((v) & ~0x1fffffff) == 0 \ | |
9064 | ? 3 \ | |
9065 | : 2 \ | |
9066 | : ((v) & ~0x7fffffff) == 0 \ | |
9067 | ? 1 \ | |
9068 | : 0) | |
9069 | ||
9070 | /* load_register() | |
67c1ffbe | 9071 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
9072 | * an absolute expression value into a register. |
9073 | */ | |
9074 | static void | |
67c0d1eb | 9075 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
9076 | { |
9077 | int freg; | |
9078 | expressionS hi32, lo32; | |
9079 | ||
9080 | if (ep->X_op != O_big) | |
9081 | { | |
9c2799c2 | 9082 | gas_assert (ep->X_op == O_constant); |
256ab948 TS |
9083 | |
9084 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
2051e8c4 MR |
9085 | if (!dbl) |
9086 | normalize_constant_expr (ep); | |
256ab948 TS |
9087 | |
9088 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
9089 | { |
9090 | /* We can handle 16 bit signed values with an addiu to | |
9091 | $zero. No need to ever use daddiu here, since $zero and | |
9092 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 9093 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
9094 | return; |
9095 | } | |
9096 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
9097 | { | |
9098 | /* We can handle 16 bit unsigned values with an ori to | |
9099 | $zero. */ | |
67c0d1eb | 9100 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
9101 | return; |
9102 | } | |
256ab948 | 9103 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
9104 | { |
9105 | /* 32 bit values require an lui. */ | |
df58fc94 | 9106 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 9107 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 9108 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
9109 | return; |
9110 | } | |
9111 | } | |
9112 | ||
9113 | /* The value is larger than 32 bits. */ | |
9114 | ||
bad1aba3 | 9115 | if (!dbl || GPR_SIZE == 32) |
252b5132 | 9116 | { |
55e08f71 NC |
9117 | char value[32]; |
9118 | ||
9119 | sprintf_vma (value, ep->X_add_number); | |
1661c76c | 9120 | as_bad (_("number (0x%s) larger than 32 bits"), value); |
67c0d1eb | 9121 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
9122 | return; |
9123 | } | |
9124 | ||
9125 | if (ep->X_op != O_big) | |
9126 | { | |
9127 | hi32 = *ep; | |
9128 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
9129 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
9130 | hi32.X_add_number &= 0xffffffff; | |
9131 | lo32 = *ep; | |
9132 | lo32.X_add_number &= 0xffffffff; | |
9133 | } | |
9134 | else | |
9135 | { | |
9c2799c2 | 9136 | gas_assert (ep->X_add_number > 2); |
252b5132 RH |
9137 | if (ep->X_add_number == 3) |
9138 | generic_bignum[3] = 0; | |
9139 | else if (ep->X_add_number > 4) | |
1661c76c | 9140 | as_bad (_("number larger than 64 bits")); |
252b5132 RH |
9141 | lo32.X_op = O_constant; |
9142 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
9143 | hi32.X_op = O_constant; | |
9144 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
9145 | } | |
9146 | ||
9147 | if (hi32.X_add_number == 0) | |
9148 | freg = 0; | |
9149 | else | |
9150 | { | |
9151 | int shift, bit; | |
9152 | unsigned long hi, lo; | |
9153 | ||
956cd1d6 | 9154 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
9155 | { |
9156 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
9157 | { | |
67c0d1eb | 9158 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
9159 | return; |
9160 | } | |
9161 | if (lo32.X_add_number & 0x80000000) | |
9162 | { | |
df58fc94 | 9163 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 9164 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 9165 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
9166 | return; |
9167 | } | |
9168 | } | |
252b5132 RH |
9169 | |
9170 | /* Check for 16bit shifted constant. We know that hi32 is | |
9171 | non-zero, so start the mask on the first bit of the hi32 | |
9172 | value. */ | |
9173 | shift = 17; | |
9174 | do | |
beae10d5 KH |
9175 | { |
9176 | unsigned long himask, lomask; | |
9177 | ||
9178 | if (shift < 32) | |
9179 | { | |
9180 | himask = 0xffff >> (32 - shift); | |
9181 | lomask = (0xffff << shift) & 0xffffffff; | |
9182 | } | |
9183 | else | |
9184 | { | |
9185 | himask = 0xffff << (shift - 32); | |
9186 | lomask = 0; | |
9187 | } | |
9188 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
9189 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
9190 | { | |
9191 | expressionS tmp; | |
9192 | ||
9193 | tmp.X_op = O_constant; | |
9194 | if (shift < 32) | |
9195 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
9196 | | (lo32.X_add_number >> shift)); | |
9197 | else | |
9198 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb | 9199 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
df58fc94 | 9200 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 9201 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
9202 | return; |
9203 | } | |
f9419b05 | 9204 | ++shift; |
beae10d5 KH |
9205 | } |
9206 | while (shift <= (64 - 16)); | |
252b5132 RH |
9207 | |
9208 | /* Find the bit number of the lowest one bit, and store the | |
9209 | shifted value in hi/lo. */ | |
9210 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
9211 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
9212 | if (lo != 0) | |
9213 | { | |
9214 | bit = 0; | |
9215 | while ((lo & 1) == 0) | |
9216 | { | |
9217 | lo >>= 1; | |
9218 | ++bit; | |
9219 | } | |
9220 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
9221 | hi >>= bit; | |
9222 | } | |
9223 | else | |
9224 | { | |
9225 | bit = 32; | |
9226 | while ((hi & 1) == 0) | |
9227 | { | |
9228 | hi >>= 1; | |
9229 | ++bit; | |
9230 | } | |
9231 | lo = hi; | |
9232 | hi = 0; | |
9233 | } | |
9234 | ||
9235 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
9236 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
9237 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
9238 | { |
9239 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 9240 | if (shift != 0) |
beae10d5 | 9241 | { |
252b5132 RH |
9242 | expressionS tmp; |
9243 | ||
9244 | /* This instruction will set the register to be all | |
9245 | ones. */ | |
beae10d5 KH |
9246 | tmp.X_op = O_constant; |
9247 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 9248 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
9249 | if (bit != 0) |
9250 | { | |
9251 | bit += shift; | |
df58fc94 | 9252 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 9253 | reg, reg, (bit >= 32) ? bit - 32 : bit); |
beae10d5 | 9254 | } |
df58fc94 | 9255 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT, |
67c0d1eb | 9256 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
9257 | return; |
9258 | } | |
9259 | } | |
252b5132 RH |
9260 | |
9261 | /* Sign extend hi32 before calling load_register, because we can | |
9262 | generally get better code when we load a sign extended value. */ | |
9263 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 9264 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 9265 | load_register (reg, &hi32, 0); |
252b5132 RH |
9266 | freg = reg; |
9267 | } | |
9268 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
9269 | { | |
9270 | if (freg != 0) | |
9271 | { | |
df58fc94 | 9272 | macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0); |
252b5132 RH |
9273 | freg = reg; |
9274 | } | |
9275 | } | |
9276 | else | |
9277 | { | |
9278 | expressionS mid16; | |
9279 | ||
956cd1d6 | 9280 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 9281 | { |
df58fc94 RS |
9282 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
9283 | macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0); | |
beae10d5 KH |
9284 | return; |
9285 | } | |
252b5132 RH |
9286 | |
9287 | if (freg != 0) | |
9288 | { | |
df58fc94 | 9289 | macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16); |
252b5132 RH |
9290 | freg = reg; |
9291 | } | |
9292 | mid16 = lo32; | |
9293 | mid16.X_add_number >>= 16; | |
67c0d1eb | 9294 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
df58fc94 | 9295 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
252b5132 RH |
9296 | freg = reg; |
9297 | } | |
9298 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 9299 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
9300 | } |
9301 | ||
269137b2 TS |
9302 | static inline void |
9303 | load_delay_nop (void) | |
9304 | { | |
9305 | if (!gpr_interlocks) | |
9306 | macro_build (NULL, "nop", ""); | |
9307 | } | |
9308 | ||
252b5132 RH |
9309 | /* Load an address into a register. */ |
9310 | ||
9311 | static void | |
67c0d1eb | 9312 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 9313 | { |
252b5132 RH |
9314 | if (ep->X_op != O_constant |
9315 | && ep->X_op != O_symbol) | |
9316 | { | |
9317 | as_bad (_("expression too complex")); | |
9318 | ep->X_op = O_constant; | |
9319 | } | |
9320 | ||
9321 | if (ep->X_op == O_constant) | |
9322 | { | |
67c0d1eb | 9323 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
9324 | return; |
9325 | } | |
9326 | ||
9327 | if (mips_pic == NO_PIC) | |
9328 | { | |
9329 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 9330 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
9331 | Otherwise we want |
9332 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
9333 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 9334 | If we have an addend, we always use the latter form. |
76b3015f | 9335 | |
d6bc6245 TS |
9336 | With 64bit address space and a usable $at we want |
9337 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
9338 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
9339 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
9340 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
9341 | dsll32 $reg,0 | |
3a482fd5 | 9342 | daddu $reg,$reg,$at |
76b3015f | 9343 | |
c03099e6 | 9344 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
9345 | on superscalar processors. |
9346 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
9347 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
9348 | dsll $reg,16 | |
9349 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
9350 | dsll $reg,16 | |
9351 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
6caf9ef4 TS |
9352 | |
9353 | For GP relative symbols in 64bit address space we can use | |
9354 | the same sequence as in 32bit address space. */ | |
aed1a261 | 9355 | if (HAVE_64BIT_SYMBOLS) |
d6bc6245 | 9356 | { |
6caf9ef4 TS |
9357 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
9358 | && !nopic_need_relax (ep->X_add_symbol, 1)) | |
9359 | { | |
9360 | relax_start (ep->X_add_symbol); | |
9361 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
9362 | mips_gp_register, BFD_RELOC_GPREL16); | |
9363 | relax_switch (); | |
9364 | } | |
d6bc6245 | 9365 | |
741fe287 | 9366 | if (*used_at == 0 && mips_opts.at) |
d6bc6245 | 9367 | { |
df58fc94 RS |
9368 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
9369 | macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S); | |
67c0d1eb RS |
9370 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
9371 | BFD_RELOC_MIPS_HIGHER); | |
9372 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
df58fc94 | 9373 | macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0); |
67c0d1eb | 9374 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); |
d6bc6245 TS |
9375 | *used_at = 1; |
9376 | } | |
9377 | else | |
9378 | { | |
df58fc94 | 9379 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb RS |
9380 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
9381 | BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 9382 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 9383 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); |
df58fc94 | 9384 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 9385 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); |
d6bc6245 | 9386 | } |
6caf9ef4 TS |
9387 | |
9388 | if (mips_relax.sequence) | |
9389 | relax_end (); | |
d6bc6245 | 9390 | } |
252b5132 RH |
9391 | else |
9392 | { | |
d6bc6245 | 9393 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 9394 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
d6bc6245 | 9395 | { |
4d7206a2 | 9396 | relax_start (ep->X_add_symbol); |
67c0d1eb | 9397 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 9398 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 9399 | relax_switch (); |
d6bc6245 | 9400 | } |
67c0d1eb RS |
9401 | macro_build_lui (ep, reg); |
9402 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
9403 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
9404 | if (mips_relax.sequence) |
9405 | relax_end (); | |
d6bc6245 | 9406 | } |
252b5132 | 9407 | } |
0a44bf69 | 9408 | else if (!mips_big_got) |
252b5132 RH |
9409 | { |
9410 | expressionS ex; | |
9411 | ||
9412 | /* If this is a reference to an external symbol, we want | |
9413 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9414 | Otherwise we want | |
9415 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9416 | nop | |
9417 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
9418 | If there is a constant, it must be added in after. |
9419 | ||
ed6fb7bd | 9420 | If we have NewABI, we want |
f5040a92 AO |
9421 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
9422 | unless we're referencing a global symbol with a non-zero | |
9423 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
9424 | if (HAVE_NEWABI) |
9425 | { | |
f5040a92 AO |
9426 | if (ep->X_add_number) |
9427 | { | |
4d7206a2 | 9428 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 9429 | ep->X_add_number = 0; |
4d7206a2 | 9430 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
9431 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
9432 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
9433 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
9434 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
9435 | ex.X_op = O_constant; | |
67c0d1eb | 9436 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 9437 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 9438 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 9439 | relax_switch (); |
f5040a92 | 9440 | } |
67c0d1eb | 9441 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 9442 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
9443 | if (mips_relax.sequence) |
9444 | relax_end (); | |
ed6fb7bd SC |
9445 | } |
9446 | else | |
9447 | { | |
f5040a92 AO |
9448 | ex.X_add_number = ep->X_add_number; |
9449 | ep->X_add_number = 0; | |
67c0d1eb RS |
9450 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
9451 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 9452 | load_delay_nop (); |
4d7206a2 RS |
9453 | relax_start (ep->X_add_symbol); |
9454 | relax_switch (); | |
67c0d1eb | 9455 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 9456 | BFD_RELOC_LO16); |
4d7206a2 | 9457 | relax_end (); |
ed6fb7bd | 9458 | |
f5040a92 AO |
9459 | if (ex.X_add_number != 0) |
9460 | { | |
9461 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
9462 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
9463 | ex.X_op = O_constant; | |
67c0d1eb | 9464 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 9465 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 9466 | } |
252b5132 RH |
9467 | } |
9468 | } | |
0a44bf69 | 9469 | else if (mips_big_got) |
252b5132 RH |
9470 | { |
9471 | expressionS ex; | |
252b5132 RH |
9472 | |
9473 | /* This is the large GOT case. If this is a reference to an | |
9474 | external symbol, we want | |
9475 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
9476 | addu $reg,$reg,$gp | |
9477 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
9478 | |
9479 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
9480 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
9481 | nop | |
9482 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 9483 | If there is a constant, it must be added in after. |
f5040a92 AO |
9484 | |
9485 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
9486 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
9487 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 9488 | */ |
438c16b8 TS |
9489 | if (HAVE_NEWABI) |
9490 | { | |
4d7206a2 | 9491 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 9492 | ep->X_add_number = 0; |
4d7206a2 | 9493 | relax_start (ep->X_add_symbol); |
df58fc94 | 9494 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
9495 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
9496 | reg, reg, mips_gp_register); | |
9497 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
9498 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
9499 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
9500 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
9501 | else if (ex.X_add_number) | |
9502 | { | |
9503 | ex.X_op = O_constant; | |
67c0d1eb RS |
9504 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
9505 | BFD_RELOC_LO16); | |
f5040a92 AO |
9506 | } |
9507 | ||
9508 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 9509 | relax_switch (); |
67c0d1eb | 9510 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 9511 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
9512 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
9513 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 9514 | relax_end (); |
438c16b8 | 9515 | } |
252b5132 | 9516 | else |
438c16b8 | 9517 | { |
f5040a92 AO |
9518 | ex.X_add_number = ep->X_add_number; |
9519 | ep->X_add_number = 0; | |
4d7206a2 | 9520 | relax_start (ep->X_add_symbol); |
df58fc94 | 9521 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
9522 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
9523 | reg, reg, mips_gp_register); | |
9524 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
9525 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
9526 | relax_switch (); |
9527 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
9528 | { |
9529 | /* We need a nop before loading from $gp. This special | |
9530 | check is required because the lui which starts the main | |
9531 | instruction stream does not refer to $gp, and so will not | |
9532 | insert the nop which may be required. */ | |
67c0d1eb | 9533 | macro_build (NULL, "nop", ""); |
438c16b8 | 9534 | } |
67c0d1eb | 9535 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 9536 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 9537 | load_delay_nop (); |
67c0d1eb | 9538 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 9539 | BFD_RELOC_LO16); |
4d7206a2 | 9540 | relax_end (); |
438c16b8 | 9541 | |
f5040a92 AO |
9542 | if (ex.X_add_number != 0) |
9543 | { | |
9544 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
9545 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
9546 | ex.X_op = O_constant; | |
67c0d1eb RS |
9547 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
9548 | BFD_RELOC_LO16); | |
f5040a92 | 9549 | } |
252b5132 RH |
9550 | } |
9551 | } | |
252b5132 RH |
9552 | else |
9553 | abort (); | |
8fc2e39e | 9554 | |
741fe287 | 9555 | if (!mips_opts.at && *used_at == 1) |
1661c76c | 9556 | as_bad (_("macro used $at after \".set noat\"")); |
252b5132 RH |
9557 | } |
9558 | ||
ea1fb5dc RS |
9559 | /* Move the contents of register SOURCE into register DEST. */ |
9560 | ||
9561 | static void | |
67c0d1eb | 9562 | move_register (int dest, int source) |
ea1fb5dc | 9563 | { |
df58fc94 RS |
9564 | /* Prefer to use a 16-bit microMIPS instruction unless the previous |
9565 | instruction specifically requires a 32-bit one. */ | |
9566 | if (mips_opts.micromips | |
833794fc | 9567 | && !mips_opts.insn32 |
df58fc94 | 9568 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
7951ca42 | 9569 | macro_build (NULL, "move", "mp,mj", dest, source); |
df58fc94 | 9570 | else |
40fc1451 | 9571 | macro_build (NULL, "or", "d,v,t", dest, source, 0); |
ea1fb5dc RS |
9572 | } |
9573 | ||
4d7206a2 | 9574 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
9575 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
9576 | The two alternatives are: | |
4d7206a2 | 9577 | |
33eaf5de | 9578 | Global symbol Local symbol |
4d7206a2 RS |
9579 | ------------- ------------ |
9580 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
9581 | ... ... | |
9582 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
9583 | ||
9584 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
9585 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
9586 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
9587 | |
9588 | static void | |
67c0d1eb | 9589 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
9590 | { |
9591 | expressionS global; | |
9592 | ||
9593 | global = *local; | |
9594 | global.X_add_number = 0; | |
9595 | ||
9596 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
9597 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
9598 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 9599 | relax_switch (); |
67c0d1eb RS |
9600 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
9601 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
9602 | relax_end (); |
9603 | } | |
9604 | ||
9605 | static void | |
67c0d1eb | 9606 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
9607 | { |
9608 | expressionS global; | |
9609 | ||
9610 | global.X_op = O_constant; | |
9611 | global.X_op_symbol = NULL; | |
9612 | global.X_add_symbol = NULL; | |
9613 | global.X_add_number = local->X_add_number; | |
9614 | ||
9615 | relax_start (local->X_add_symbol); | |
67c0d1eb | 9616 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
9617 | dest, dest, BFD_RELOC_LO16); |
9618 | relax_switch (); | |
67c0d1eb | 9619 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
9620 | relax_end (); |
9621 | } | |
9622 | ||
f6a22291 MR |
9623 | static void |
9624 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
9625 | { | |
9626 | expressionS global; | |
9627 | int hold_mips_optimize; | |
9628 | ||
9629 | global.X_op = O_constant; | |
9630 | global.X_op_symbol = NULL; | |
9631 | global.X_add_symbol = NULL; | |
9632 | global.X_add_number = local->X_add_number; | |
9633 | ||
9634 | relax_start (local->X_add_symbol); | |
9635 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
9636 | relax_switch (); | |
9637 | /* Set mips_optimize around the lui instruction to avoid | |
9638 | inserting an unnecessary nop after the lw. */ | |
9639 | hold_mips_optimize = mips_optimize; | |
9640 | mips_optimize = 2; | |
9641 | macro_build_lui (&global, tmp); | |
9642 | mips_optimize = hold_mips_optimize; | |
9643 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
9644 | relax_end (); | |
9645 | ||
9646 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
9647 | } | |
9648 | ||
df58fc94 RS |
9649 | /* Emit a sequence of instructions to emulate a branch likely operation. |
9650 | BR is an ordinary branch corresponding to one to be emulated. BRNEG | |
9651 | is its complementing branch with the original condition negated. | |
9652 | CALL is set if the original branch specified the link operation. | |
9653 | EP, FMT, SREG and TREG specify the usual macro_build() parameters. | |
9654 | ||
9655 | Code like this is produced in the noreorder mode: | |
9656 | ||
9657 | BRNEG <args>, 1f | |
9658 | nop | |
9659 | b <sym> | |
9660 | delay slot (executed only if branch taken) | |
9661 | 1: | |
9662 | ||
9663 | or, if CALL is set: | |
9664 | ||
9665 | BRNEG <args>, 1f | |
9666 | nop | |
9667 | bal <sym> | |
9668 | delay slot (executed only if branch taken) | |
9669 | 1: | |
9670 | ||
9671 | In the reorder mode the delay slot would be filled with a nop anyway, | |
9672 | so code produced is simply: | |
9673 | ||
9674 | BR <args>, <sym> | |
9675 | nop | |
9676 | ||
9677 | This function is used when producing code for the microMIPS ASE that | |
9678 | does not implement branch likely instructions in hardware. */ | |
9679 | ||
9680 | static void | |
9681 | macro_build_branch_likely (const char *br, const char *brneg, | |
9682 | int call, expressionS *ep, const char *fmt, | |
9683 | unsigned int sreg, unsigned int treg) | |
9684 | { | |
9685 | int noreorder = mips_opts.noreorder; | |
9686 | expressionS expr1; | |
9687 | ||
9688 | gas_assert (mips_opts.micromips); | |
9689 | start_noreorder (); | |
9690 | if (noreorder) | |
9691 | { | |
9692 | micromips_label_expr (&expr1); | |
9693 | macro_build (&expr1, brneg, fmt, sreg, treg); | |
9694 | macro_build (NULL, "nop", ""); | |
9695 | macro_build (ep, call ? "bal" : "b", "p"); | |
9696 | ||
9697 | /* Set to true so that append_insn adds a label. */ | |
9698 | emit_branch_likely_macro = TRUE; | |
9699 | } | |
9700 | else | |
9701 | { | |
9702 | macro_build (ep, br, fmt, sreg, treg); | |
9703 | macro_build (NULL, "nop", ""); | |
9704 | } | |
9705 | end_noreorder (); | |
9706 | } | |
9707 | ||
9708 | /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as | |
9709 | the condition code tested. EP specifies the branch target. */ | |
9710 | ||
9711 | static void | |
9712 | macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc) | |
9713 | { | |
9714 | const int call = 0; | |
9715 | const char *brneg; | |
9716 | const char *br; | |
9717 | ||
9718 | switch (type) | |
9719 | { | |
9720 | case M_BC1FL: | |
9721 | br = "bc1f"; | |
9722 | brneg = "bc1t"; | |
9723 | break; | |
9724 | case M_BC1TL: | |
9725 | br = "bc1t"; | |
9726 | brneg = "bc1f"; | |
9727 | break; | |
9728 | case M_BC2FL: | |
9729 | br = "bc2f"; | |
9730 | brneg = "bc2t"; | |
9731 | break; | |
9732 | case M_BC2TL: | |
9733 | br = "bc2t"; | |
9734 | brneg = "bc2f"; | |
9735 | break; | |
9736 | default: | |
9737 | abort (); | |
9738 | } | |
9739 | macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO); | |
9740 | } | |
9741 | ||
9742 | /* Emit a two-argument branch macro specified by TYPE, using SREG as | |
9743 | the register tested. EP specifies the branch target. */ | |
9744 | ||
9745 | static void | |
9746 | macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg) | |
9747 | { | |
9748 | const char *brneg = NULL; | |
9749 | const char *br; | |
9750 | int call = 0; | |
9751 | ||
9752 | switch (type) | |
9753 | { | |
9754 | case M_BGEZ: | |
9755 | br = "bgez"; | |
9756 | break; | |
9757 | case M_BGEZL: | |
9758 | br = mips_opts.micromips ? "bgez" : "bgezl"; | |
9759 | brneg = "bltz"; | |
9760 | break; | |
9761 | case M_BGEZALL: | |
9762 | gas_assert (mips_opts.micromips); | |
833794fc | 9763 | br = mips_opts.insn32 ? "bgezal" : "bgezals"; |
df58fc94 RS |
9764 | brneg = "bltz"; |
9765 | call = 1; | |
9766 | break; | |
9767 | case M_BGTZ: | |
9768 | br = "bgtz"; | |
9769 | break; | |
9770 | case M_BGTZL: | |
9771 | br = mips_opts.micromips ? "bgtz" : "bgtzl"; | |
9772 | brneg = "blez"; | |
9773 | break; | |
9774 | case M_BLEZ: | |
9775 | br = "blez"; | |
9776 | break; | |
9777 | case M_BLEZL: | |
9778 | br = mips_opts.micromips ? "blez" : "blezl"; | |
9779 | brneg = "bgtz"; | |
9780 | break; | |
9781 | case M_BLTZ: | |
9782 | br = "bltz"; | |
9783 | break; | |
9784 | case M_BLTZL: | |
9785 | br = mips_opts.micromips ? "bltz" : "bltzl"; | |
9786 | brneg = "bgez"; | |
9787 | break; | |
9788 | case M_BLTZALL: | |
9789 | gas_assert (mips_opts.micromips); | |
833794fc | 9790 | br = mips_opts.insn32 ? "bltzal" : "bltzals"; |
df58fc94 RS |
9791 | brneg = "bgez"; |
9792 | call = 1; | |
9793 | break; | |
9794 | default: | |
9795 | abort (); | |
9796 | } | |
9797 | if (mips_opts.micromips && brneg) | |
9798 | macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO); | |
9799 | else | |
9800 | macro_build (ep, br, "s,p", sreg); | |
9801 | } | |
9802 | ||
9803 | /* Emit a three-argument branch macro specified by TYPE, using SREG and | |
9804 | TREG as the registers tested. EP specifies the branch target. */ | |
9805 | ||
9806 | static void | |
9807 | macro_build_branch_rsrt (int type, expressionS *ep, | |
9808 | unsigned int sreg, unsigned int treg) | |
9809 | { | |
9810 | const char *brneg = NULL; | |
9811 | const int call = 0; | |
9812 | const char *br; | |
9813 | ||
9814 | switch (type) | |
9815 | { | |
9816 | case M_BEQ: | |
9817 | case M_BEQ_I: | |
9818 | br = "beq"; | |
9819 | break; | |
9820 | case M_BEQL: | |
9821 | case M_BEQL_I: | |
9822 | br = mips_opts.micromips ? "beq" : "beql"; | |
9823 | brneg = "bne"; | |
9824 | break; | |
9825 | case M_BNE: | |
9826 | case M_BNE_I: | |
9827 | br = "bne"; | |
9828 | break; | |
9829 | case M_BNEL: | |
9830 | case M_BNEL_I: | |
9831 | br = mips_opts.micromips ? "bne" : "bnel"; | |
9832 | brneg = "beq"; | |
9833 | break; | |
9834 | default: | |
9835 | abort (); | |
9836 | } | |
9837 | if (mips_opts.micromips && brneg) | |
9838 | macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg); | |
9839 | else | |
9840 | macro_build (ep, br, "s,t,p", sreg, treg); | |
9841 | } | |
9842 | ||
f2ae14a1 RS |
9843 | /* Return the high part that should be loaded in order to make the low |
9844 | part of VALUE accessible using an offset of OFFBITS bits. */ | |
9845 | ||
9846 | static offsetT | |
9847 | offset_high_part (offsetT value, unsigned int offbits) | |
9848 | { | |
9849 | offsetT bias; | |
9850 | addressT low_mask; | |
9851 | ||
9852 | if (offbits == 0) | |
9853 | return value; | |
9854 | bias = 1 << (offbits - 1); | |
9855 | low_mask = bias * 2 - 1; | |
9856 | return (value + bias) & ~low_mask; | |
9857 | } | |
9858 | ||
9859 | /* Return true if the value stored in offset_expr and offset_reloc | |
9860 | fits into a signed offset of OFFBITS bits. RANGE is the maximum | |
9861 | amount that the caller wants to add without inducing overflow | |
9862 | and ALIGN is the known alignment of the value in bytes. */ | |
9863 | ||
9864 | static bfd_boolean | |
9865 | small_offset_p (unsigned int range, unsigned int align, unsigned int offbits) | |
9866 | { | |
9867 | if (offbits == 16) | |
9868 | { | |
9869 | /* Accept any relocation operator if overflow isn't a concern. */ | |
9870 | if (range < align && *offset_reloc != BFD_RELOC_UNUSED) | |
9871 | return TRUE; | |
9872 | ||
9873 | /* These relocations are guaranteed not to overflow in correct links. */ | |
9874 | if (*offset_reloc == BFD_RELOC_MIPS_LITERAL | |
9875 | || gprel16_reloc_p (*offset_reloc)) | |
9876 | return TRUE; | |
9877 | } | |
9878 | if (offset_expr.X_op == O_constant | |
9879 | && offset_high_part (offset_expr.X_add_number, offbits) == 0 | |
9880 | && offset_high_part (offset_expr.X_add_number + range, offbits) == 0) | |
9881 | return TRUE; | |
9882 | return FALSE; | |
9883 | } | |
9884 | ||
252b5132 RH |
9885 | /* |
9886 | * Build macros | |
9887 | * This routine implements the seemingly endless macro or synthesized | |
9888 | * instructions and addressing modes in the mips assembly language. Many | |
9889 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 9890 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
9891 | * this verbose method. Others are not simple macros but are more like |
9892 | * optimizing code generation. | |
9893 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 9894 | * consecutively that would load AT with the upper half of the same address. |
2b0f3761 | 9895 | * The ensuing load upper instructions are omitted. This implies some kind |
252b5132 RH |
9896 | * of global optimization. We currently only optimize within a single macro. |
9897 | * For many of the load and store macros if the address is specified as a | |
9898 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
9899 | * first load register 'at' with zero and use it as the base register. The | |
9900 | * mips assembler simply uses register $zero. Just one tiny optimization | |
9901 | * we're missing. | |
9902 | */ | |
9903 | static void | |
833794fc | 9904 | macro (struct mips_cl_insn *ip, char *str) |
252b5132 | 9905 | { |
c0ebe874 RS |
9906 | const struct mips_operand_array *operands; |
9907 | unsigned int breg, i; | |
741fe287 | 9908 | unsigned int tempreg; |
252b5132 | 9909 | int mask; |
43841e91 | 9910 | int used_at = 0; |
df58fc94 | 9911 | expressionS label_expr; |
252b5132 | 9912 | expressionS expr1; |
df58fc94 | 9913 | expressionS *ep; |
252b5132 RH |
9914 | const char *s; |
9915 | const char *s2; | |
9916 | const char *fmt; | |
9917 | int likely = 0; | |
252b5132 | 9918 | int coproc = 0; |
7f3c4072 | 9919 | int offbits = 16; |
1abe91b1 | 9920 | int call = 0; |
df58fc94 RS |
9921 | int jals = 0; |
9922 | int dbl = 0; | |
9923 | int imm = 0; | |
9924 | int ust = 0; | |
9925 | int lp = 0; | |
f2ae14a1 | 9926 | bfd_boolean large_offset; |
252b5132 | 9927 | int off; |
252b5132 | 9928 | int hold_mips_optimize; |
f2ae14a1 | 9929 | unsigned int align; |
c0ebe874 | 9930 | unsigned int op[MAX_OPERANDS]; |
252b5132 | 9931 | |
9c2799c2 | 9932 | gas_assert (! mips_opts.mips16); |
252b5132 | 9933 | |
c0ebe874 RS |
9934 | operands = insn_operands (ip); |
9935 | for (i = 0; i < MAX_OPERANDS; i++) | |
9936 | if (operands->operand[i]) | |
9937 | op[i] = insn_extract_operand (ip, operands->operand[i]); | |
9938 | else | |
9939 | op[i] = -1; | |
9940 | ||
252b5132 RH |
9941 | mask = ip->insn_mo->mask; |
9942 | ||
df58fc94 RS |
9943 | label_expr.X_op = O_constant; |
9944 | label_expr.X_op_symbol = NULL; | |
9945 | label_expr.X_add_symbol = NULL; | |
9946 | label_expr.X_add_number = 0; | |
9947 | ||
252b5132 RH |
9948 | expr1.X_op = O_constant; |
9949 | expr1.X_op_symbol = NULL; | |
9950 | expr1.X_add_symbol = NULL; | |
9951 | expr1.X_add_number = 1; | |
f2ae14a1 | 9952 | align = 1; |
252b5132 RH |
9953 | |
9954 | switch (mask) | |
9955 | { | |
9956 | case M_DABS: | |
9957 | dbl = 1; | |
1a0670f3 | 9958 | /* Fall through. */ |
252b5132 | 9959 | case M_ABS: |
df58fc94 RS |
9960 | /* bgez $a0,1f |
9961 | move v0,$a0 | |
9962 | sub v0,$zero,$a0 | |
9963 | 1: | |
9964 | */ | |
252b5132 | 9965 | |
7d10b47d | 9966 | start_noreorder (); |
252b5132 | 9967 | |
df58fc94 RS |
9968 | if (mips_opts.micromips) |
9969 | micromips_label_expr (&label_expr); | |
9970 | else | |
9971 | label_expr.X_add_number = 8; | |
c0ebe874 RS |
9972 | macro_build (&label_expr, "bgez", "s,p", op[1]); |
9973 | if (op[0] == op[1]) | |
a605d2b3 | 9974 | macro_build (NULL, "nop", ""); |
252b5132 | 9975 | else |
c0ebe874 RS |
9976 | move_register (op[0], op[1]); |
9977 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", op[0], 0, op[1]); | |
df58fc94 RS |
9978 | if (mips_opts.micromips) |
9979 | micromips_add_label (); | |
252b5132 | 9980 | |
7d10b47d | 9981 | end_noreorder (); |
8fc2e39e | 9982 | break; |
252b5132 RH |
9983 | |
9984 | case M_ADD_I: | |
9985 | s = "addi"; | |
9986 | s2 = "add"; | |
9987 | goto do_addi; | |
9988 | case M_ADDU_I: | |
9989 | s = "addiu"; | |
9990 | s2 = "addu"; | |
9991 | goto do_addi; | |
9992 | case M_DADD_I: | |
9993 | dbl = 1; | |
9994 | s = "daddi"; | |
9995 | s2 = "dadd"; | |
df58fc94 RS |
9996 | if (!mips_opts.micromips) |
9997 | goto do_addi; | |
b0e6f033 | 9998 | if (imm_expr.X_add_number >= -0x200 |
df58fc94 RS |
9999 | && imm_expr.X_add_number < 0x200) |
10000 | { | |
b0e6f033 RS |
10001 | macro_build (NULL, s, "t,r,.", op[0], op[1], |
10002 | (int) imm_expr.X_add_number); | |
df58fc94 RS |
10003 | break; |
10004 | } | |
10005 | goto do_addi_i; | |
252b5132 RH |
10006 | case M_DADDU_I: |
10007 | dbl = 1; | |
10008 | s = "daddiu"; | |
10009 | s2 = "daddu"; | |
10010 | do_addi: | |
b0e6f033 | 10011 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 RH |
10012 | && imm_expr.X_add_number < 0x8000) |
10013 | { | |
c0ebe874 | 10014 | macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
8fc2e39e | 10015 | break; |
252b5132 | 10016 | } |
df58fc94 | 10017 | do_addi_i: |
8fc2e39e | 10018 | used_at = 1; |
67c0d1eb | 10019 | load_register (AT, &imm_expr, dbl); |
c0ebe874 | 10020 | macro_build (NULL, s2, "d,v,t", op[0], op[1], AT); |
252b5132 RH |
10021 | break; |
10022 | ||
10023 | case M_AND_I: | |
10024 | s = "andi"; | |
10025 | s2 = "and"; | |
10026 | goto do_bit; | |
10027 | case M_OR_I: | |
10028 | s = "ori"; | |
10029 | s2 = "or"; | |
10030 | goto do_bit; | |
10031 | case M_NOR_I: | |
10032 | s = ""; | |
10033 | s2 = "nor"; | |
10034 | goto do_bit; | |
10035 | case M_XOR_I: | |
10036 | s = "xori"; | |
10037 | s2 = "xor"; | |
10038 | do_bit: | |
b0e6f033 | 10039 | if (imm_expr.X_add_number >= 0 |
252b5132 RH |
10040 | && imm_expr.X_add_number < 0x10000) |
10041 | { | |
10042 | if (mask != M_NOR_I) | |
c0ebe874 | 10043 | macro_build (&imm_expr, s, "t,r,i", op[0], op[1], BFD_RELOC_LO16); |
252b5132 RH |
10044 | else |
10045 | { | |
67c0d1eb | 10046 | macro_build (&imm_expr, "ori", "t,r,i", |
c0ebe874 RS |
10047 | op[0], op[1], BFD_RELOC_LO16); |
10048 | macro_build (NULL, "nor", "d,v,t", op[0], op[0], 0); | |
252b5132 | 10049 | } |
8fc2e39e | 10050 | break; |
252b5132 RH |
10051 | } |
10052 | ||
8fc2e39e | 10053 | used_at = 1; |
bad1aba3 | 10054 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 10055 | macro_build (NULL, s2, "d,v,t", op[0], op[1], AT); |
252b5132 RH |
10056 | break; |
10057 | ||
8b082fb1 TS |
10058 | case M_BALIGN: |
10059 | switch (imm_expr.X_add_number) | |
10060 | { | |
10061 | case 0: | |
10062 | macro_build (NULL, "nop", ""); | |
10063 | break; | |
10064 | case 2: | |
c0ebe874 | 10065 | macro_build (NULL, "packrl.ph", "d,s,t", op[0], op[0], op[1]); |
8b082fb1 | 10066 | break; |
03f66e8a MR |
10067 | case 1: |
10068 | case 3: | |
c0ebe874 | 10069 | macro_build (NULL, "balign", "t,s,2", op[0], op[1], |
90ecf173 | 10070 | (int) imm_expr.X_add_number); |
8b082fb1 | 10071 | break; |
03f66e8a MR |
10072 | default: |
10073 | as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"), | |
10074 | (unsigned long) imm_expr.X_add_number); | |
10075 | break; | |
8b082fb1 TS |
10076 | } |
10077 | break; | |
10078 | ||
df58fc94 RS |
10079 | case M_BC1FL: |
10080 | case M_BC1TL: | |
10081 | case M_BC2FL: | |
10082 | case M_BC2TL: | |
10083 | gas_assert (mips_opts.micromips); | |
10084 | macro_build_branch_ccl (mask, &offset_expr, | |
10085 | EXTRACT_OPERAND (1, BCC, *ip)); | |
10086 | break; | |
10087 | ||
252b5132 | 10088 | case M_BEQ_I: |
252b5132 | 10089 | case M_BEQL_I: |
252b5132 | 10090 | case M_BNE_I: |
252b5132 | 10091 | case M_BNEL_I: |
b0e6f033 | 10092 | if (imm_expr.X_add_number == 0) |
c0ebe874 | 10093 | op[1] = 0; |
df58fc94 | 10094 | else |
252b5132 | 10095 | { |
c0ebe874 | 10096 | op[1] = AT; |
df58fc94 | 10097 | used_at = 1; |
bad1aba3 | 10098 | load_register (op[1], &imm_expr, GPR_SIZE == 64); |
252b5132 | 10099 | } |
df58fc94 RS |
10100 | /* Fall through. */ |
10101 | case M_BEQL: | |
10102 | case M_BNEL: | |
c0ebe874 | 10103 | macro_build_branch_rsrt (mask, &offset_expr, op[0], op[1]); |
252b5132 RH |
10104 | break; |
10105 | ||
10106 | case M_BGEL: | |
10107 | likely = 1; | |
1a0670f3 | 10108 | /* Fall through. */ |
252b5132 | 10109 | case M_BGE: |
c0ebe874 RS |
10110 | if (op[1] == 0) |
10111 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[0]); | |
10112 | else if (op[0] == 0) | |
10113 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[1]); | |
df58fc94 | 10114 | else |
252b5132 | 10115 | { |
df58fc94 | 10116 | used_at = 1; |
c0ebe874 | 10117 | macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]); |
df58fc94 RS |
10118 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10119 | &offset_expr, AT, ZERO); | |
252b5132 | 10120 | } |
df58fc94 RS |
10121 | break; |
10122 | ||
10123 | case M_BGEZL: | |
10124 | case M_BGEZALL: | |
10125 | case M_BGTZL: | |
10126 | case M_BLEZL: | |
10127 | case M_BLTZL: | |
10128 | case M_BLTZALL: | |
c0ebe874 | 10129 | macro_build_branch_rs (mask, &offset_expr, op[0]); |
252b5132 RH |
10130 | break; |
10131 | ||
10132 | case M_BGTL_I: | |
10133 | likely = 1; | |
1a0670f3 | 10134 | /* Fall through. */ |
252b5132 | 10135 | case M_BGT_I: |
90ecf173 | 10136 | /* Check for > max integer. */ |
b0e6f033 | 10137 | if (imm_expr.X_add_number >= GPR_SMAX) |
252b5132 RH |
10138 | { |
10139 | do_false: | |
90ecf173 | 10140 | /* Result is always false. */ |
252b5132 | 10141 | if (! likely) |
a605d2b3 | 10142 | macro_build (NULL, "nop", ""); |
252b5132 | 10143 | else |
df58fc94 | 10144 | macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO); |
8fc2e39e | 10145 | break; |
252b5132 | 10146 | } |
f9419b05 | 10147 | ++imm_expr.X_add_number; |
252b5132 RH |
10148 | /* FALLTHROUGH */ |
10149 | case M_BGE_I: | |
10150 | case M_BGEL_I: | |
10151 | if (mask == M_BGEL_I) | |
10152 | likely = 1; | |
b0e6f033 | 10153 | if (imm_expr.X_add_number == 0) |
252b5132 | 10154 | { |
df58fc94 | 10155 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, |
c0ebe874 | 10156 | &offset_expr, op[0]); |
8fc2e39e | 10157 | break; |
252b5132 | 10158 | } |
b0e6f033 | 10159 | if (imm_expr.X_add_number == 1) |
252b5132 | 10160 | { |
df58fc94 | 10161 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, |
c0ebe874 | 10162 | &offset_expr, op[0]); |
8fc2e39e | 10163 | break; |
252b5132 | 10164 | } |
b0e6f033 | 10165 | if (imm_expr.X_add_number <= GPR_SMIN) |
252b5132 RH |
10166 | { |
10167 | do_true: | |
10168 | /* result is always true */ | |
1661c76c | 10169 | as_warn (_("branch %s is always true"), ip->insn_mo->name); |
67c0d1eb | 10170 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 10171 | break; |
252b5132 | 10172 | } |
8fc2e39e | 10173 | used_at = 1; |
c0ebe874 | 10174 | set_at (op[0], 0); |
df58fc94 RS |
10175 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10176 | &offset_expr, AT, ZERO); | |
252b5132 RH |
10177 | break; |
10178 | ||
10179 | case M_BGEUL: | |
10180 | likely = 1; | |
1a0670f3 | 10181 | /* Fall through. */ |
252b5132 | 10182 | case M_BGEU: |
c0ebe874 | 10183 | if (op[1] == 0) |
252b5132 | 10184 | goto do_true; |
c0ebe874 | 10185 | else if (op[0] == 0) |
df58fc94 | 10186 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
c0ebe874 | 10187 | &offset_expr, ZERO, op[1]); |
df58fc94 | 10188 | else |
252b5132 | 10189 | { |
df58fc94 | 10190 | used_at = 1; |
c0ebe874 | 10191 | macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]); |
df58fc94 RS |
10192 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10193 | &offset_expr, AT, ZERO); | |
252b5132 | 10194 | } |
252b5132 RH |
10195 | break; |
10196 | ||
10197 | case M_BGTUL_I: | |
10198 | likely = 1; | |
1a0670f3 | 10199 | /* Fall through. */ |
252b5132 | 10200 | case M_BGTU_I: |
c0ebe874 | 10201 | if (op[0] == 0 |
bad1aba3 | 10202 | || (GPR_SIZE == 32 |
f01dc953 | 10203 | && imm_expr.X_add_number == -1)) |
252b5132 | 10204 | goto do_false; |
f9419b05 | 10205 | ++imm_expr.X_add_number; |
252b5132 RH |
10206 | /* FALLTHROUGH */ |
10207 | case M_BGEU_I: | |
10208 | case M_BGEUL_I: | |
10209 | if (mask == M_BGEUL_I) | |
10210 | likely = 1; | |
b0e6f033 | 10211 | if (imm_expr.X_add_number == 0) |
252b5132 | 10212 | goto do_true; |
b0e6f033 | 10213 | else if (imm_expr.X_add_number == 1) |
df58fc94 | 10214 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
c0ebe874 | 10215 | &offset_expr, op[0], ZERO); |
df58fc94 | 10216 | else |
252b5132 | 10217 | { |
df58fc94 | 10218 | used_at = 1; |
c0ebe874 | 10219 | set_at (op[0], 1); |
df58fc94 RS |
10220 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10221 | &offset_expr, AT, ZERO); | |
252b5132 | 10222 | } |
252b5132 RH |
10223 | break; |
10224 | ||
10225 | case M_BGTL: | |
10226 | likely = 1; | |
1a0670f3 | 10227 | /* Fall through. */ |
252b5132 | 10228 | case M_BGT: |
c0ebe874 RS |
10229 | if (op[1] == 0) |
10230 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[0]); | |
10231 | else if (op[0] == 0) | |
10232 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[1]); | |
df58fc94 | 10233 | else |
252b5132 | 10234 | { |
df58fc94 | 10235 | used_at = 1; |
c0ebe874 | 10236 | macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]); |
df58fc94 RS |
10237 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10238 | &offset_expr, AT, ZERO); | |
252b5132 | 10239 | } |
252b5132 RH |
10240 | break; |
10241 | ||
10242 | case M_BGTUL: | |
10243 | likely = 1; | |
1a0670f3 | 10244 | /* Fall through. */ |
252b5132 | 10245 | case M_BGTU: |
c0ebe874 | 10246 | if (op[1] == 0) |
df58fc94 | 10247 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
c0ebe874 RS |
10248 | &offset_expr, op[0], ZERO); |
10249 | else if (op[0] == 0) | |
df58fc94 RS |
10250 | goto do_false; |
10251 | else | |
252b5132 | 10252 | { |
df58fc94 | 10253 | used_at = 1; |
c0ebe874 | 10254 | macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]); |
df58fc94 RS |
10255 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10256 | &offset_expr, AT, ZERO); | |
252b5132 | 10257 | } |
252b5132 RH |
10258 | break; |
10259 | ||
10260 | case M_BLEL: | |
10261 | likely = 1; | |
1a0670f3 | 10262 | /* Fall through. */ |
252b5132 | 10263 | case M_BLE: |
c0ebe874 RS |
10264 | if (op[1] == 0) |
10265 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]); | |
10266 | else if (op[0] == 0) | |
10267 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[1]); | |
df58fc94 | 10268 | else |
252b5132 | 10269 | { |
df58fc94 | 10270 | used_at = 1; |
c0ebe874 | 10271 | macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]); |
df58fc94 RS |
10272 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10273 | &offset_expr, AT, ZERO); | |
252b5132 | 10274 | } |
252b5132 RH |
10275 | break; |
10276 | ||
10277 | case M_BLEL_I: | |
10278 | likely = 1; | |
1a0670f3 | 10279 | /* Fall through. */ |
252b5132 | 10280 | case M_BLE_I: |
b0e6f033 | 10281 | if (imm_expr.X_add_number >= GPR_SMAX) |
252b5132 | 10282 | goto do_true; |
f9419b05 | 10283 | ++imm_expr.X_add_number; |
252b5132 RH |
10284 | /* FALLTHROUGH */ |
10285 | case M_BLT_I: | |
10286 | case M_BLTL_I: | |
10287 | if (mask == M_BLTL_I) | |
10288 | likely = 1; | |
b0e6f033 | 10289 | if (imm_expr.X_add_number == 0) |
c0ebe874 | 10290 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]); |
b0e6f033 | 10291 | else if (imm_expr.X_add_number == 1) |
c0ebe874 | 10292 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]); |
df58fc94 | 10293 | else |
252b5132 | 10294 | { |
df58fc94 | 10295 | used_at = 1; |
c0ebe874 | 10296 | set_at (op[0], 0); |
df58fc94 RS |
10297 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10298 | &offset_expr, AT, ZERO); | |
252b5132 | 10299 | } |
252b5132 RH |
10300 | break; |
10301 | ||
10302 | case M_BLEUL: | |
10303 | likely = 1; | |
1a0670f3 | 10304 | /* Fall through. */ |
252b5132 | 10305 | case M_BLEU: |
c0ebe874 | 10306 | if (op[1] == 0) |
df58fc94 | 10307 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
c0ebe874 RS |
10308 | &offset_expr, op[0], ZERO); |
10309 | else if (op[0] == 0) | |
df58fc94 RS |
10310 | goto do_true; |
10311 | else | |
252b5132 | 10312 | { |
df58fc94 | 10313 | used_at = 1; |
c0ebe874 | 10314 | macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]); |
df58fc94 RS |
10315 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10316 | &offset_expr, AT, ZERO); | |
252b5132 | 10317 | } |
252b5132 RH |
10318 | break; |
10319 | ||
10320 | case M_BLEUL_I: | |
10321 | likely = 1; | |
1a0670f3 | 10322 | /* Fall through. */ |
252b5132 | 10323 | case M_BLEU_I: |
c0ebe874 | 10324 | if (op[0] == 0 |
bad1aba3 | 10325 | || (GPR_SIZE == 32 |
f01dc953 | 10326 | && imm_expr.X_add_number == -1)) |
252b5132 | 10327 | goto do_true; |
f9419b05 | 10328 | ++imm_expr.X_add_number; |
252b5132 RH |
10329 | /* FALLTHROUGH */ |
10330 | case M_BLTU_I: | |
10331 | case M_BLTUL_I: | |
10332 | if (mask == M_BLTUL_I) | |
10333 | likely = 1; | |
b0e6f033 | 10334 | if (imm_expr.X_add_number == 0) |
252b5132 | 10335 | goto do_false; |
b0e6f033 | 10336 | else if (imm_expr.X_add_number == 1) |
df58fc94 | 10337 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
c0ebe874 | 10338 | &offset_expr, op[0], ZERO); |
df58fc94 | 10339 | else |
252b5132 | 10340 | { |
df58fc94 | 10341 | used_at = 1; |
c0ebe874 | 10342 | set_at (op[0], 1); |
df58fc94 RS |
10343 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10344 | &offset_expr, AT, ZERO); | |
252b5132 | 10345 | } |
252b5132 RH |
10346 | break; |
10347 | ||
10348 | case M_BLTL: | |
10349 | likely = 1; | |
1a0670f3 | 10350 | /* Fall through. */ |
252b5132 | 10351 | case M_BLT: |
c0ebe874 RS |
10352 | if (op[1] == 0) |
10353 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]); | |
10354 | else if (op[0] == 0) | |
10355 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[1]); | |
df58fc94 | 10356 | else |
252b5132 | 10357 | { |
df58fc94 | 10358 | used_at = 1; |
c0ebe874 | 10359 | macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]); |
df58fc94 RS |
10360 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10361 | &offset_expr, AT, ZERO); | |
252b5132 | 10362 | } |
252b5132 RH |
10363 | break; |
10364 | ||
10365 | case M_BLTUL: | |
10366 | likely = 1; | |
1a0670f3 | 10367 | /* Fall through. */ |
252b5132 | 10368 | case M_BLTU: |
c0ebe874 | 10369 | if (op[1] == 0) |
252b5132 | 10370 | goto do_false; |
c0ebe874 | 10371 | else if (op[0] == 0) |
df58fc94 | 10372 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
c0ebe874 | 10373 | &offset_expr, ZERO, op[1]); |
df58fc94 | 10374 | else |
252b5132 | 10375 | { |
df58fc94 | 10376 | used_at = 1; |
c0ebe874 | 10377 | macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]); |
df58fc94 RS |
10378 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10379 | &offset_expr, AT, ZERO); | |
252b5132 | 10380 | } |
252b5132 RH |
10381 | break; |
10382 | ||
10383 | case M_DDIV_3: | |
10384 | dbl = 1; | |
1a0670f3 | 10385 | /* Fall through. */ |
252b5132 RH |
10386 | case M_DIV_3: |
10387 | s = "mflo"; | |
10388 | goto do_div3; | |
10389 | case M_DREM_3: | |
10390 | dbl = 1; | |
1a0670f3 | 10391 | /* Fall through. */ |
252b5132 RH |
10392 | case M_REM_3: |
10393 | s = "mfhi"; | |
10394 | do_div3: | |
c0ebe874 | 10395 | if (op[2] == 0) |
252b5132 | 10396 | { |
1661c76c | 10397 | as_warn (_("divide by zero")); |
252b5132 | 10398 | if (mips_trap) |
df58fc94 | 10399 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 10400 | else |
df58fc94 | 10401 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 10402 | break; |
252b5132 RH |
10403 | } |
10404 | ||
7d10b47d | 10405 | start_noreorder (); |
252b5132 RH |
10406 | if (mips_trap) |
10407 | { | |
c0ebe874 RS |
10408 | macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7); |
10409 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]); | |
252b5132 RH |
10410 | } |
10411 | else | |
10412 | { | |
df58fc94 RS |
10413 | if (mips_opts.micromips) |
10414 | micromips_label_expr (&label_expr); | |
10415 | else | |
10416 | label_expr.X_add_number = 8; | |
c0ebe874 RS |
10417 | macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO); |
10418 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]); | |
df58fc94 RS |
10419 | macro_build (NULL, "break", BRK_FMT, 7); |
10420 | if (mips_opts.micromips) | |
10421 | micromips_add_label (); | |
252b5132 RH |
10422 | } |
10423 | expr1.X_add_number = -1; | |
8fc2e39e | 10424 | used_at = 1; |
f6a22291 | 10425 | load_register (AT, &expr1, dbl); |
df58fc94 RS |
10426 | if (mips_opts.micromips) |
10427 | micromips_label_expr (&label_expr); | |
10428 | else | |
10429 | label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); | |
c0ebe874 | 10430 | macro_build (&label_expr, "bne", "s,t,p", op[2], AT); |
252b5132 RH |
10431 | if (dbl) |
10432 | { | |
10433 | expr1.X_add_number = 1; | |
f6a22291 | 10434 | load_register (AT, &expr1, dbl); |
df58fc94 | 10435 | macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31); |
252b5132 RH |
10436 | } |
10437 | else | |
10438 | { | |
10439 | expr1.X_add_number = 0x80000000; | |
df58fc94 | 10440 | macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16); |
252b5132 RH |
10441 | } |
10442 | if (mips_trap) | |
10443 | { | |
c0ebe874 | 10444 | macro_build (NULL, "teq", TRAP_FMT, op[1], AT, 6); |
252b5132 RH |
10445 | /* We want to close the noreorder block as soon as possible, so |
10446 | that later insns are available for delay slot filling. */ | |
7d10b47d | 10447 | end_noreorder (); |
252b5132 RH |
10448 | } |
10449 | else | |
10450 | { | |
df58fc94 RS |
10451 | if (mips_opts.micromips) |
10452 | micromips_label_expr (&label_expr); | |
10453 | else | |
10454 | label_expr.X_add_number = 8; | |
c0ebe874 | 10455 | macro_build (&label_expr, "bne", "s,t,p", op[1], AT); |
a605d2b3 | 10456 | macro_build (NULL, "nop", ""); |
252b5132 RH |
10457 | |
10458 | /* We want to close the noreorder block as soon as possible, so | |
10459 | that later insns are available for delay slot filling. */ | |
7d10b47d | 10460 | end_noreorder (); |
252b5132 | 10461 | |
df58fc94 | 10462 | macro_build (NULL, "break", BRK_FMT, 6); |
252b5132 | 10463 | } |
df58fc94 RS |
10464 | if (mips_opts.micromips) |
10465 | micromips_add_label (); | |
c0ebe874 | 10466 | macro_build (NULL, s, MFHL_FMT, op[0]); |
252b5132 RH |
10467 | break; |
10468 | ||
10469 | case M_DIV_3I: | |
10470 | s = "div"; | |
10471 | s2 = "mflo"; | |
10472 | goto do_divi; | |
10473 | case M_DIVU_3I: | |
10474 | s = "divu"; | |
10475 | s2 = "mflo"; | |
10476 | goto do_divi; | |
10477 | case M_REM_3I: | |
10478 | s = "div"; | |
10479 | s2 = "mfhi"; | |
10480 | goto do_divi; | |
10481 | case M_REMU_3I: | |
10482 | s = "divu"; | |
10483 | s2 = "mfhi"; | |
10484 | goto do_divi; | |
10485 | case M_DDIV_3I: | |
10486 | dbl = 1; | |
10487 | s = "ddiv"; | |
10488 | s2 = "mflo"; | |
10489 | goto do_divi; | |
10490 | case M_DDIVU_3I: | |
10491 | dbl = 1; | |
10492 | s = "ddivu"; | |
10493 | s2 = "mflo"; | |
10494 | goto do_divi; | |
10495 | case M_DREM_3I: | |
10496 | dbl = 1; | |
10497 | s = "ddiv"; | |
10498 | s2 = "mfhi"; | |
10499 | goto do_divi; | |
10500 | case M_DREMU_3I: | |
10501 | dbl = 1; | |
10502 | s = "ddivu"; | |
10503 | s2 = "mfhi"; | |
10504 | do_divi: | |
b0e6f033 | 10505 | if (imm_expr.X_add_number == 0) |
252b5132 | 10506 | { |
1661c76c | 10507 | as_warn (_("divide by zero")); |
252b5132 | 10508 | if (mips_trap) |
df58fc94 | 10509 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 10510 | else |
df58fc94 | 10511 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 10512 | break; |
252b5132 | 10513 | } |
b0e6f033 | 10514 | if (imm_expr.X_add_number == 1) |
252b5132 RH |
10515 | { |
10516 | if (strcmp (s2, "mflo") == 0) | |
c0ebe874 | 10517 | move_register (op[0], op[1]); |
252b5132 | 10518 | else |
c0ebe874 | 10519 | move_register (op[0], ZERO); |
8fc2e39e | 10520 | break; |
252b5132 | 10521 | } |
b0e6f033 | 10522 | if (imm_expr.X_add_number == -1 && s[strlen (s) - 1] != 'u') |
252b5132 RH |
10523 | { |
10524 | if (strcmp (s2, "mflo") == 0) | |
c0ebe874 | 10525 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", op[0], op[1]); |
252b5132 | 10526 | else |
c0ebe874 | 10527 | move_register (op[0], ZERO); |
8fc2e39e | 10528 | break; |
252b5132 RH |
10529 | } |
10530 | ||
8fc2e39e | 10531 | used_at = 1; |
67c0d1eb | 10532 | load_register (AT, &imm_expr, dbl); |
c0ebe874 RS |
10533 | macro_build (NULL, s, "z,s,t", op[1], AT); |
10534 | macro_build (NULL, s2, MFHL_FMT, op[0]); | |
252b5132 RH |
10535 | break; |
10536 | ||
10537 | case M_DIVU_3: | |
10538 | s = "divu"; | |
10539 | s2 = "mflo"; | |
10540 | goto do_divu3; | |
10541 | case M_REMU_3: | |
10542 | s = "divu"; | |
10543 | s2 = "mfhi"; | |
10544 | goto do_divu3; | |
10545 | case M_DDIVU_3: | |
10546 | s = "ddivu"; | |
10547 | s2 = "mflo"; | |
10548 | goto do_divu3; | |
10549 | case M_DREMU_3: | |
10550 | s = "ddivu"; | |
10551 | s2 = "mfhi"; | |
10552 | do_divu3: | |
7d10b47d | 10553 | start_noreorder (); |
252b5132 RH |
10554 | if (mips_trap) |
10555 | { | |
c0ebe874 RS |
10556 | macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7); |
10557 | macro_build (NULL, s, "z,s,t", op[1], op[2]); | |
252b5132 RH |
10558 | /* We want to close the noreorder block as soon as possible, so |
10559 | that later insns are available for delay slot filling. */ | |
7d10b47d | 10560 | end_noreorder (); |
252b5132 RH |
10561 | } |
10562 | else | |
10563 | { | |
df58fc94 RS |
10564 | if (mips_opts.micromips) |
10565 | micromips_label_expr (&label_expr); | |
10566 | else | |
10567 | label_expr.X_add_number = 8; | |
c0ebe874 RS |
10568 | macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO); |
10569 | macro_build (NULL, s, "z,s,t", op[1], op[2]); | |
252b5132 RH |
10570 | |
10571 | /* We want to close the noreorder block as soon as possible, so | |
10572 | that later insns are available for delay slot filling. */ | |
7d10b47d | 10573 | end_noreorder (); |
df58fc94 RS |
10574 | macro_build (NULL, "break", BRK_FMT, 7); |
10575 | if (mips_opts.micromips) | |
10576 | micromips_add_label (); | |
252b5132 | 10577 | } |
c0ebe874 | 10578 | macro_build (NULL, s2, MFHL_FMT, op[0]); |
8fc2e39e | 10579 | break; |
252b5132 | 10580 | |
1abe91b1 MR |
10581 | case M_DLCA_AB: |
10582 | dbl = 1; | |
1a0670f3 | 10583 | /* Fall through. */ |
1abe91b1 MR |
10584 | case M_LCA_AB: |
10585 | call = 1; | |
10586 | goto do_la; | |
252b5132 RH |
10587 | case M_DLA_AB: |
10588 | dbl = 1; | |
1a0670f3 | 10589 | /* Fall through. */ |
252b5132 | 10590 | case M_LA_AB: |
1abe91b1 | 10591 | do_la: |
252b5132 RH |
10592 | /* Load the address of a symbol into a register. If breg is not |
10593 | zero, we then add a base register to it. */ | |
10594 | ||
c0ebe874 | 10595 | breg = op[2]; |
bad1aba3 | 10596 | if (dbl && GPR_SIZE == 32) |
ece794d9 MF |
10597 | as_warn (_("dla used to load 32-bit register; recommend using la " |
10598 | "instead")); | |
3bec30a8 | 10599 | |
90ecf173 | 10600 | if (!dbl && HAVE_64BIT_OBJECTS) |
ece794d9 MF |
10601 | as_warn (_("la used to load 64-bit address; recommend using dla " |
10602 | "instead")); | |
3bec30a8 | 10603 | |
f2ae14a1 | 10604 | if (small_offset_p (0, align, 16)) |
0c11417f | 10605 | { |
c0ebe874 | 10606 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", op[0], breg, |
f2ae14a1 | 10607 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]); |
8fc2e39e | 10608 | break; |
0c11417f MR |
10609 | } |
10610 | ||
c0ebe874 | 10611 | if (mips_opts.at && (op[0] == breg)) |
afdbd6d0 CD |
10612 | { |
10613 | tempreg = AT; | |
10614 | used_at = 1; | |
10615 | } | |
10616 | else | |
c0ebe874 | 10617 | tempreg = op[0]; |
afdbd6d0 | 10618 | |
252b5132 RH |
10619 | if (offset_expr.X_op != O_symbol |
10620 | && offset_expr.X_op != O_constant) | |
10621 | { | |
1661c76c | 10622 | as_bad (_("expression too complex")); |
252b5132 RH |
10623 | offset_expr.X_op = O_constant; |
10624 | } | |
10625 | ||
252b5132 | 10626 | if (offset_expr.X_op == O_constant) |
aed1a261 | 10627 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
10628 | else if (mips_pic == NO_PIC) |
10629 | { | |
d6bc6245 | 10630 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 10631 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
10632 | Otherwise we want |
10633 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
10634 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
10635 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 10636 | so we may as well always use the latter form. |
76b3015f | 10637 | |
6caf9ef4 TS |
10638 | With 64bit address space and a usable $at we want |
10639 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
10640 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
10641 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
10642 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
10643 | dsll32 $tempreg,0 | |
10644 | daddu $tempreg,$tempreg,$at | |
10645 | ||
10646 | If $at is already in use, we use a path which is suboptimal | |
10647 | on superscalar processors. | |
10648 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
10649 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
10650 | dsll $tempreg,16 | |
10651 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
10652 | dsll $tempreg,16 | |
10653 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
10654 | ||
10655 | For GP relative symbols in 64bit address space we can use | |
10656 | the same sequence as in 32bit address space. */ | |
aed1a261 | 10657 | if (HAVE_64BIT_SYMBOLS) |
252b5132 | 10658 | { |
6caf9ef4 TS |
10659 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
10660 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
10661 | { | |
10662 | relax_start (offset_expr.X_add_symbol); | |
10663 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
10664 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
10665 | relax_switch (); | |
10666 | } | |
d6bc6245 | 10667 | |
741fe287 | 10668 | if (used_at == 0 && mips_opts.at) |
98d3f06f | 10669 | { |
df58fc94 | 10670 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 10671 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 10672 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 10673 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 10674 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 10675 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 10676 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 10677 | AT, AT, BFD_RELOC_LO16); |
df58fc94 | 10678 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb | 10679 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
98d3f06f KH |
10680 | used_at = 1; |
10681 | } | |
10682 | else | |
10683 | { | |
df58fc94 | 10684 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 10685 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 10686 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 10687 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
df58fc94 | 10688 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 10689 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 10690 | tempreg, tempreg, BFD_RELOC_HI16_S); |
df58fc94 | 10691 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 10692 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 10693 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 10694 | } |
6caf9ef4 TS |
10695 | |
10696 | if (mips_relax.sequence) | |
10697 | relax_end (); | |
98d3f06f KH |
10698 | } |
10699 | else | |
10700 | { | |
10701 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 10702 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
98d3f06f | 10703 | { |
4d7206a2 | 10704 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
10705 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
10706 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 10707 | relax_switch (); |
98d3f06f | 10708 | } |
6943caf0 | 10709 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
1661c76c | 10710 | as_bad (_("offset too large")); |
67c0d1eb RS |
10711 | macro_build_lui (&offset_expr, tempreg); |
10712 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
10713 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
10714 | if (mips_relax.sequence) |
10715 | relax_end (); | |
98d3f06f | 10716 | } |
252b5132 | 10717 | } |
0a44bf69 | 10718 | else if (!mips_big_got && !HAVE_NEWABI) |
252b5132 | 10719 | { |
9117d219 NC |
10720 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
10721 | ||
252b5132 RH |
10722 | /* If this is a reference to an external symbol, and there |
10723 | is no constant, we want | |
10724 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 10725 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 10726 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
10727 | For a local symbol, we want |
10728 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
10729 | nop | |
10730 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
10731 | ||
10732 | If we have a small constant, and this is a reference to | |
10733 | an external symbol, we want | |
10734 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
10735 | nop | |
10736 | addiu $tempreg,$tempreg,<constant> | |
10737 | For a local symbol, we want the same instruction | |
10738 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
10739 | addiu instruction. | |
10740 | ||
10741 | If we have a large constant, and this is a reference to | |
10742 | an external symbol, we want | |
10743 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
10744 | lui $at,<hiconstant> | |
10745 | addiu $at,$at,<loconstant> | |
10746 | addu $tempreg,$tempreg,$at | |
10747 | For a local symbol, we want the same instruction | |
10748 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 10749 | addiu instruction. |
ed6fb7bd SC |
10750 | */ |
10751 | ||
4d7206a2 | 10752 | if (offset_expr.X_add_number == 0) |
252b5132 | 10753 | { |
0a44bf69 RS |
10754 | if (mips_pic == SVR4_PIC |
10755 | && breg == 0 | |
10756 | && (call || tempreg == PIC_CALL_REG)) | |
4d7206a2 RS |
10757 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; |
10758 | ||
10759 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
10760 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
10761 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 10762 | if (breg != 0) |
252b5132 RH |
10763 | { |
10764 | /* We're going to put in an addu instruction using | |
10765 | tempreg, so we may as well insert the nop right | |
10766 | now. */ | |
269137b2 | 10767 | load_delay_nop (); |
252b5132 | 10768 | } |
4d7206a2 | 10769 | relax_switch (); |
67c0d1eb RS |
10770 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
10771 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 10772 | load_delay_nop (); |
67c0d1eb RS |
10773 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
10774 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 10775 | relax_end (); |
252b5132 RH |
10776 | /* FIXME: If breg == 0, and the next instruction uses |
10777 | $tempreg, then if this variant case is used an extra | |
10778 | nop will be generated. */ | |
10779 | } | |
4d7206a2 RS |
10780 | else if (offset_expr.X_add_number >= -0x8000 |
10781 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 10782 | { |
67c0d1eb | 10783 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 10784 | load_delay_nop (); |
67c0d1eb | 10785 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
10786 | } |
10787 | else | |
10788 | { | |
4d7206a2 RS |
10789 | expr1.X_add_number = offset_expr.X_add_number; |
10790 | offset_expr.X_add_number = | |
43c0598f | 10791 | SEXT_16BIT (offset_expr.X_add_number); |
67c0d1eb | 10792 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 10793 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
10794 | /* If we are going to add in a base register, and the |
10795 | target register and the base register are the same, | |
10796 | then we are using AT as a temporary register. Since | |
10797 | we want to load the constant into AT, we add our | |
10798 | current AT (from the global offset table) and the | |
10799 | register into the register now, and pretend we were | |
10800 | not using a base register. */ | |
c0ebe874 | 10801 | if (breg == op[0]) |
252b5132 | 10802 | { |
269137b2 | 10803 | load_delay_nop (); |
67c0d1eb | 10804 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 | 10805 | op[0], AT, breg); |
252b5132 | 10806 | breg = 0; |
c0ebe874 | 10807 | tempreg = op[0]; |
252b5132 | 10808 | } |
f6a22291 | 10809 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
10810 | used_at = 1; |
10811 | } | |
10812 | } | |
0a44bf69 | 10813 | else if (!mips_big_got && HAVE_NEWABI) |
f5040a92 | 10814 | { |
67c0d1eb | 10815 | int add_breg_early = 0; |
f5040a92 AO |
10816 | |
10817 | /* If this is a reference to an external, and there is no | |
10818 | constant, or local symbol (*), with or without a | |
10819 | constant, we want | |
10820 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 10821 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
10822 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
10823 | ||
10824 | If we have a small constant, and this is a reference to | |
10825 | an external symbol, we want | |
10826 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
10827 | addiu $tempreg,$tempreg,<constant> | |
10828 | ||
10829 | If we have a large constant, and this is a reference to | |
10830 | an external symbol, we want | |
10831 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
10832 | lui $at,<hiconstant> | |
10833 | addiu $at,$at,<loconstant> | |
10834 | addu $tempreg,$tempreg,$at | |
10835 | ||
10836 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
10837 | local symbols, even though it introduces an additional | |
10838 | instruction. */ | |
10839 | ||
f5040a92 AO |
10840 | if (offset_expr.X_add_number) |
10841 | { | |
4d7206a2 | 10842 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
10843 | offset_expr.X_add_number = 0; |
10844 | ||
4d7206a2 | 10845 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
10846 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
10847 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
10848 | |
10849 | if (expr1.X_add_number >= -0x8000 | |
10850 | && expr1.X_add_number < 0x8000) | |
10851 | { | |
67c0d1eb RS |
10852 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
10853 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 10854 | } |
ecd13cd3 | 10855 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 10856 | { |
c0ebe874 RS |
10857 | unsigned int dreg; |
10858 | ||
f5040a92 AO |
10859 | /* If we are going to add in a base register, and the |
10860 | target register and the base register are the same, | |
10861 | then we are using AT as a temporary register. Since | |
10862 | we want to load the constant into AT, we add our | |
10863 | current AT (from the global offset table) and the | |
10864 | register into the register now, and pretend we were | |
10865 | not using a base register. */ | |
c0ebe874 | 10866 | if (breg != op[0]) |
f5040a92 AO |
10867 | dreg = tempreg; |
10868 | else | |
10869 | { | |
9c2799c2 | 10870 | gas_assert (tempreg == AT); |
67c0d1eb | 10871 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 RS |
10872 | op[0], AT, breg); |
10873 | dreg = op[0]; | |
67c0d1eb | 10874 | add_breg_early = 1; |
f5040a92 AO |
10875 | } |
10876 | ||
f6a22291 | 10877 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 10878 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 10879 | dreg, dreg, AT); |
f5040a92 | 10880 | |
f5040a92 AO |
10881 | used_at = 1; |
10882 | } | |
10883 | else | |
10884 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
10885 | ||
4d7206a2 | 10886 | relax_switch (); |
f5040a92 AO |
10887 | offset_expr.X_add_number = expr1.X_add_number; |
10888 | ||
67c0d1eb RS |
10889 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
10890 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
10891 | if (add_breg_early) | |
f5040a92 | 10892 | { |
67c0d1eb | 10893 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 | 10894 | op[0], tempreg, breg); |
f5040a92 | 10895 | breg = 0; |
c0ebe874 | 10896 | tempreg = op[0]; |
f5040a92 | 10897 | } |
4d7206a2 | 10898 | relax_end (); |
f5040a92 | 10899 | } |
4d7206a2 | 10900 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 10901 | { |
4d7206a2 | 10902 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
10903 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
10904 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 10905 | relax_switch (); |
67c0d1eb RS |
10906 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
10907 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 10908 | relax_end (); |
f5040a92 | 10909 | } |
4d7206a2 | 10910 | else |
f5040a92 | 10911 | { |
67c0d1eb RS |
10912 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
10913 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
10914 | } |
10915 | } | |
0a44bf69 | 10916 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 10917 | { |
67c0d1eb | 10918 | int gpdelay; |
9117d219 NC |
10919 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
10920 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 10921 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
10922 | |
10923 | /* This is the large GOT case. If this is a reference to an | |
10924 | external symbol, and there is no constant, we want | |
10925 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
10926 | addu $tempreg,$tempreg,$gp | |
10927 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 10928 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
10929 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
10930 | addu $tempreg,$tempreg,$gp | |
10931 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
10932 | For a local symbol, we want |
10933 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
10934 | nop | |
10935 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
10936 | ||
10937 | If we have a small constant, and this is a reference to | |
10938 | an external symbol, we want | |
10939 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
10940 | addu $tempreg,$tempreg,$gp | |
10941 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
10942 | nop | |
10943 | addiu $tempreg,$tempreg,<constant> | |
10944 | For a local symbol, we want | |
10945 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
10946 | nop | |
10947 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
10948 | ||
10949 | If we have a large constant, and this is a reference to | |
10950 | an external symbol, we want | |
10951 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
10952 | addu $tempreg,$tempreg,$gp | |
10953 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
10954 | lui $at,<hiconstant> | |
10955 | addiu $at,$at,<loconstant> | |
10956 | addu $tempreg,$tempreg,$at | |
10957 | For a local symbol, we want | |
10958 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
10959 | lui $at,<hiconstant> | |
10960 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
10961 | addu $tempreg,$tempreg,$at | |
f5040a92 | 10962 | */ |
438c16b8 | 10963 | |
252b5132 RH |
10964 | expr1.X_add_number = offset_expr.X_add_number; |
10965 | offset_expr.X_add_number = 0; | |
4d7206a2 | 10966 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 10967 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
10968 | if (expr1.X_add_number == 0 && breg == 0 |
10969 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
10970 | { |
10971 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
10972 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
10973 | } | |
df58fc94 | 10974 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 10975 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 10976 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 10977 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 10978 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
10979 | if (expr1.X_add_number == 0) |
10980 | { | |
67c0d1eb | 10981 | if (breg != 0) |
252b5132 RH |
10982 | { |
10983 | /* We're going to put in an addu instruction using | |
10984 | tempreg, so we may as well insert the nop right | |
10985 | now. */ | |
269137b2 | 10986 | load_delay_nop (); |
252b5132 | 10987 | } |
252b5132 RH |
10988 | } |
10989 | else if (expr1.X_add_number >= -0x8000 | |
10990 | && expr1.X_add_number < 0x8000) | |
10991 | { | |
269137b2 | 10992 | load_delay_nop (); |
67c0d1eb | 10993 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 10994 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
10995 | } |
10996 | else | |
10997 | { | |
c0ebe874 RS |
10998 | unsigned int dreg; |
10999 | ||
252b5132 RH |
11000 | /* If we are going to add in a base register, and the |
11001 | target register and the base register are the same, | |
11002 | then we are using AT as a temporary register. Since | |
11003 | we want to load the constant into AT, we add our | |
11004 | current AT (from the global offset table) and the | |
11005 | register into the register now, and pretend we were | |
11006 | not using a base register. */ | |
c0ebe874 | 11007 | if (breg != op[0]) |
67c0d1eb | 11008 | dreg = tempreg; |
252b5132 RH |
11009 | else |
11010 | { | |
9c2799c2 | 11011 | gas_assert (tempreg == AT); |
269137b2 | 11012 | load_delay_nop (); |
67c0d1eb | 11013 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 RS |
11014 | op[0], AT, breg); |
11015 | dreg = op[0]; | |
252b5132 RH |
11016 | } |
11017 | ||
f6a22291 | 11018 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 11019 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 11020 | |
252b5132 RH |
11021 | used_at = 1; |
11022 | } | |
43c0598f | 11023 | offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number); |
4d7206a2 | 11024 | relax_switch (); |
252b5132 | 11025 | |
67c0d1eb | 11026 | if (gpdelay) |
252b5132 RH |
11027 | { |
11028 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 11029 | the first instruction on the main stream does not. */ |
67c0d1eb | 11030 | macro_build (NULL, "nop", ""); |
252b5132 | 11031 | } |
ed6fb7bd | 11032 | |
67c0d1eb RS |
11033 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11034 | local_reloc_type, mips_gp_register); | |
f5040a92 | 11035 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
11036 | && expr1.X_add_number < 0x8000) |
11037 | { | |
269137b2 | 11038 | load_delay_nop (); |
67c0d1eb RS |
11039 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
11040 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 11041 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
11042 | register, the external symbol case ended with a load, |
11043 | so if the symbol turns out to not be external, and | |
11044 | the next instruction uses tempreg, an unnecessary nop | |
11045 | will be inserted. */ | |
252b5132 RH |
11046 | } |
11047 | else | |
11048 | { | |
c0ebe874 | 11049 | if (breg == op[0]) |
252b5132 RH |
11050 | { |
11051 | /* We must add in the base register now, as in the | |
f5040a92 | 11052 | external symbol case. */ |
9c2799c2 | 11053 | gas_assert (tempreg == AT); |
269137b2 | 11054 | load_delay_nop (); |
67c0d1eb | 11055 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 RS |
11056 | op[0], AT, breg); |
11057 | tempreg = op[0]; | |
252b5132 | 11058 | /* We set breg to 0 because we have arranged to add |
f5040a92 | 11059 | it in in both cases. */ |
252b5132 RH |
11060 | breg = 0; |
11061 | } | |
11062 | ||
67c0d1eb RS |
11063 | macro_build_lui (&expr1, AT); |
11064 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 11065 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 11066 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 11067 | tempreg, tempreg, AT); |
8fc2e39e | 11068 | used_at = 1; |
252b5132 | 11069 | } |
4d7206a2 | 11070 | relax_end (); |
252b5132 | 11071 | } |
0a44bf69 | 11072 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 11073 | { |
f5040a92 AO |
11074 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
11075 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 11076 | int add_breg_early = 0; |
f5040a92 AO |
11077 | |
11078 | /* This is the large GOT case. If this is a reference to an | |
11079 | external symbol, and there is no constant, we want | |
11080 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11081 | add $tempreg,$tempreg,$gp | |
11082 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 11083 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
11084 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
11085 | add $tempreg,$tempreg,$gp | |
11086 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
11087 | ||
11088 | If we have a small constant, and this is a reference to | |
11089 | an external symbol, we want | |
11090 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11091 | add $tempreg,$tempreg,$gp | |
11092 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
11093 | addi $tempreg,$tempreg,<constant> | |
11094 | ||
11095 | If we have a large constant, and this is a reference to | |
11096 | an external symbol, we want | |
11097 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11098 | addu $tempreg,$tempreg,$gp | |
11099 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
11100 | lui $at,<hiconstant> | |
11101 | addi $at,$at,<loconstant> | |
11102 | add $tempreg,$tempreg,$at | |
11103 | ||
11104 | If we have NewABI, and we know it's a local symbol, we want | |
11105 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
11106 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
11107 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
11108 | ||
4d7206a2 | 11109 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 11110 | |
4d7206a2 | 11111 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
11112 | offset_expr.X_add_number = 0; |
11113 | ||
1abe91b1 MR |
11114 | if (expr1.X_add_number == 0 && breg == 0 |
11115 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
11116 | { |
11117 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
11118 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
11119 | } | |
df58fc94 | 11120 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 11121 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 11122 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
11123 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11124 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
11125 | |
11126 | if (expr1.X_add_number == 0) | |
4d7206a2 | 11127 | ; |
f5040a92 AO |
11128 | else if (expr1.X_add_number >= -0x8000 |
11129 | && expr1.X_add_number < 0x8000) | |
11130 | { | |
67c0d1eb | 11131 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 11132 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 11133 | } |
ecd13cd3 | 11134 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 11135 | { |
c0ebe874 RS |
11136 | unsigned int dreg; |
11137 | ||
f5040a92 AO |
11138 | /* If we are going to add in a base register, and the |
11139 | target register and the base register are the same, | |
11140 | then we are using AT as a temporary register. Since | |
11141 | we want to load the constant into AT, we add our | |
11142 | current AT (from the global offset table) and the | |
11143 | register into the register now, and pretend we were | |
11144 | not using a base register. */ | |
c0ebe874 | 11145 | if (breg != op[0]) |
f5040a92 AO |
11146 | dreg = tempreg; |
11147 | else | |
11148 | { | |
9c2799c2 | 11149 | gas_assert (tempreg == AT); |
67c0d1eb | 11150 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 RS |
11151 | op[0], AT, breg); |
11152 | dreg = op[0]; | |
67c0d1eb | 11153 | add_breg_early = 1; |
f5040a92 AO |
11154 | } |
11155 | ||
f6a22291 | 11156 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 11157 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 11158 | |
f5040a92 AO |
11159 | used_at = 1; |
11160 | } | |
11161 | else | |
11162 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
11163 | ||
4d7206a2 | 11164 | relax_switch (); |
f5040a92 | 11165 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
11166 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11167 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
11168 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
11169 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
11170 | if (add_breg_early) | |
f5040a92 | 11171 | { |
67c0d1eb | 11172 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 | 11173 | op[0], tempreg, breg); |
f5040a92 | 11174 | breg = 0; |
c0ebe874 | 11175 | tempreg = op[0]; |
f5040a92 | 11176 | } |
4d7206a2 | 11177 | relax_end (); |
f5040a92 | 11178 | } |
252b5132 RH |
11179 | else |
11180 | abort (); | |
11181 | ||
11182 | if (breg != 0) | |
c0ebe874 | 11183 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", op[0], tempreg, breg); |
252b5132 RH |
11184 | break; |
11185 | ||
52b6b6b9 | 11186 | case M_MSGSND: |
df58fc94 | 11187 | gas_assert (!mips_opts.micromips); |
c0ebe874 | 11188 | macro_build (NULL, "c2", "C", (op[0] << 16) | 0x01); |
c7af4273 | 11189 | break; |
52b6b6b9 JM |
11190 | |
11191 | case M_MSGLD: | |
df58fc94 | 11192 | gas_assert (!mips_opts.micromips); |
c8276761 | 11193 | macro_build (NULL, "c2", "C", 0x02); |
c7af4273 | 11194 | break; |
52b6b6b9 JM |
11195 | |
11196 | case M_MSGLD_T: | |
df58fc94 | 11197 | gas_assert (!mips_opts.micromips); |
c0ebe874 | 11198 | macro_build (NULL, "c2", "C", (op[0] << 16) | 0x02); |
c7af4273 | 11199 | break; |
52b6b6b9 JM |
11200 | |
11201 | case M_MSGWAIT: | |
df58fc94 | 11202 | gas_assert (!mips_opts.micromips); |
52b6b6b9 | 11203 | macro_build (NULL, "c2", "C", 3); |
c7af4273 | 11204 | break; |
52b6b6b9 JM |
11205 | |
11206 | case M_MSGWAIT_T: | |
df58fc94 | 11207 | gas_assert (!mips_opts.micromips); |
c0ebe874 | 11208 | macro_build (NULL, "c2", "C", (op[0] << 16) | 0x03); |
c7af4273 | 11209 | break; |
52b6b6b9 | 11210 | |
252b5132 RH |
11211 | case M_J_A: |
11212 | /* The j instruction may not be used in PIC code, since it | |
11213 | requires an absolute address. We convert it to a b | |
11214 | instruction. */ | |
11215 | if (mips_pic == NO_PIC) | |
67c0d1eb | 11216 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 11217 | else |
67c0d1eb | 11218 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 11219 | break; |
252b5132 RH |
11220 | |
11221 | /* The jal instructions must be handled as macros because when | |
11222 | generating PIC code they expand to multi-instruction | |
11223 | sequences. Normally they are simple instructions. */ | |
df58fc94 | 11224 | case M_JALS_1: |
c0ebe874 RS |
11225 | op[1] = op[0]; |
11226 | op[0] = RA; | |
df58fc94 RS |
11227 | /* Fall through. */ |
11228 | case M_JALS_2: | |
11229 | gas_assert (mips_opts.micromips); | |
833794fc MR |
11230 | if (mips_opts.insn32) |
11231 | { | |
1661c76c | 11232 | as_bad (_("opcode not supported in the `insn32' mode `%s'"), str); |
833794fc MR |
11233 | break; |
11234 | } | |
df58fc94 RS |
11235 | jals = 1; |
11236 | goto jal; | |
252b5132 | 11237 | case M_JAL_1: |
c0ebe874 RS |
11238 | op[1] = op[0]; |
11239 | op[0] = RA; | |
252b5132 RH |
11240 | /* Fall through. */ |
11241 | case M_JAL_2: | |
df58fc94 | 11242 | jal: |
3e722fb5 | 11243 | if (mips_pic == NO_PIC) |
df58fc94 RS |
11244 | { |
11245 | s = jals ? "jalrs" : "jalr"; | |
e64af278 | 11246 | if (mips_opts.micromips |
833794fc | 11247 | && !mips_opts.insn32 |
c0ebe874 | 11248 | && op[0] == RA |
e64af278 | 11249 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
c0ebe874 | 11250 | macro_build (NULL, s, "mj", op[1]); |
df58fc94 | 11251 | else |
c0ebe874 | 11252 | macro_build (NULL, s, JALR_FMT, op[0], op[1]); |
df58fc94 | 11253 | } |
0a44bf69 | 11254 | else |
252b5132 | 11255 | { |
df58fc94 RS |
11256 | int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI |
11257 | && mips_cprestore_offset >= 0); | |
11258 | ||
c0ebe874 | 11259 | if (op[1] != PIC_CALL_REG) |
252b5132 | 11260 | as_warn (_("MIPS PIC call to register other than $25")); |
bdaaa2e1 | 11261 | |
833794fc MR |
11262 | s = ((mips_opts.micromips |
11263 | && !mips_opts.insn32 | |
11264 | && (!mips_opts.noreorder || cprestore)) | |
df58fc94 | 11265 | ? "jalrs" : "jalr"); |
e64af278 | 11266 | if (mips_opts.micromips |
833794fc | 11267 | && !mips_opts.insn32 |
c0ebe874 | 11268 | && op[0] == RA |
e64af278 | 11269 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
c0ebe874 | 11270 | macro_build (NULL, s, "mj", op[1]); |
df58fc94 | 11271 | else |
c0ebe874 | 11272 | macro_build (NULL, s, JALR_FMT, op[0], op[1]); |
0a44bf69 | 11273 | if (mips_pic == SVR4_PIC && !HAVE_NEWABI) |
252b5132 | 11274 | { |
6478892d | 11275 | if (mips_cprestore_offset < 0) |
1661c76c | 11276 | as_warn (_("no .cprestore pseudo-op used in PIC code")); |
6478892d TS |
11277 | else |
11278 | { | |
90ecf173 | 11279 | if (!mips_frame_reg_valid) |
7a621144 | 11280 | { |
1661c76c | 11281 | as_warn (_("no .frame pseudo-op used in PIC code")); |
7a621144 DJ |
11282 | /* Quiet this warning. */ |
11283 | mips_frame_reg_valid = 1; | |
11284 | } | |
90ecf173 | 11285 | if (!mips_cprestore_valid) |
7a621144 | 11286 | { |
1661c76c | 11287 | as_warn (_("no .cprestore pseudo-op used in PIC code")); |
7a621144 DJ |
11288 | /* Quiet this warning. */ |
11289 | mips_cprestore_valid = 1; | |
11290 | } | |
d3fca0b5 MR |
11291 | if (mips_opts.noreorder) |
11292 | macro_build (NULL, "nop", ""); | |
6478892d | 11293 | expr1.X_add_number = mips_cprestore_offset; |
134c0c8b | 11294 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 11295 | mips_gp_register, |
256ab948 TS |
11296 | mips_frame_reg, |
11297 | HAVE_64BIT_ADDRESSES); | |
6478892d | 11298 | } |
252b5132 RH |
11299 | } |
11300 | } | |
252b5132 | 11301 | |
8fc2e39e | 11302 | break; |
252b5132 | 11303 | |
df58fc94 RS |
11304 | case M_JALS_A: |
11305 | gas_assert (mips_opts.micromips); | |
833794fc MR |
11306 | if (mips_opts.insn32) |
11307 | { | |
1661c76c | 11308 | as_bad (_("opcode not supported in the `insn32' mode `%s'"), str); |
833794fc MR |
11309 | break; |
11310 | } | |
df58fc94 RS |
11311 | jals = 1; |
11312 | /* Fall through. */ | |
252b5132 RH |
11313 | case M_JAL_A: |
11314 | if (mips_pic == NO_PIC) | |
df58fc94 | 11315 | macro_build (&offset_expr, jals ? "jals" : "jal", "a"); |
252b5132 RH |
11316 | else if (mips_pic == SVR4_PIC) |
11317 | { | |
11318 | /* If this is a reference to an external symbol, and we are | |
11319 | using a small GOT, we want | |
11320 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
11321 | nop | |
f9419b05 | 11322 | jalr $ra,$25 |
252b5132 RH |
11323 | nop |
11324 | lw $gp,cprestore($sp) | |
11325 | The cprestore value is set using the .cprestore | |
11326 | pseudo-op. If we are using a big GOT, we want | |
11327 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
11328 | addu $25,$25,$gp | |
11329 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
11330 | nop | |
f9419b05 | 11331 | jalr $ra,$25 |
252b5132 RH |
11332 | nop |
11333 | lw $gp,cprestore($sp) | |
11334 | If the symbol is not external, we want | |
11335 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
11336 | nop | |
11337 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 11338 | jalr $ra,$25 |
252b5132 | 11339 | nop |
438c16b8 | 11340 | lw $gp,cprestore($sp) |
f5040a92 AO |
11341 | |
11342 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
11343 | sequences above, minus nops, unless the symbol is local, | |
11344 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
11345 | GOT_DISP. */ | |
438c16b8 | 11346 | if (HAVE_NEWABI) |
252b5132 | 11347 | { |
90ecf173 | 11348 | if (!mips_big_got) |
f5040a92 | 11349 | { |
4d7206a2 | 11350 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
11351 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11352 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 11353 | mips_gp_register); |
4d7206a2 | 11354 | relax_switch (); |
67c0d1eb RS |
11355 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11356 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
11357 | mips_gp_register); |
11358 | relax_end (); | |
f5040a92 AO |
11359 | } |
11360 | else | |
11361 | { | |
4d7206a2 | 11362 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 11363 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
11364 | BFD_RELOC_MIPS_CALL_HI16); |
11365 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
11366 | PIC_CALL_REG, mips_gp_register); | |
11367 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
11368 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
11369 | PIC_CALL_REG); | |
4d7206a2 | 11370 | relax_switch (); |
67c0d1eb RS |
11371 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11372 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
11373 | mips_gp_register); | |
11374 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
11375 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 11376 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 11377 | relax_end (); |
f5040a92 | 11378 | } |
684022ea | 11379 | |
df58fc94 | 11380 | macro_build_jalr (&offset_expr, 0); |
252b5132 RH |
11381 | } |
11382 | else | |
11383 | { | |
4d7206a2 | 11384 | relax_start (offset_expr.X_add_symbol); |
90ecf173 | 11385 | if (!mips_big_got) |
438c16b8 | 11386 | { |
67c0d1eb RS |
11387 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11388 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 11389 | mips_gp_register); |
269137b2 | 11390 | load_delay_nop (); |
4d7206a2 | 11391 | relax_switch (); |
438c16b8 | 11392 | } |
252b5132 | 11393 | else |
252b5132 | 11394 | { |
67c0d1eb RS |
11395 | int gpdelay; |
11396 | ||
11397 | gpdelay = reg_needs_delay (mips_gp_register); | |
df58fc94 | 11398 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
11399 | BFD_RELOC_MIPS_CALL_HI16); |
11400 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
11401 | PIC_CALL_REG, mips_gp_register); | |
11402 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
11403 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
11404 | PIC_CALL_REG); | |
269137b2 | 11405 | load_delay_nop (); |
4d7206a2 | 11406 | relax_switch (); |
67c0d1eb RS |
11407 | if (gpdelay) |
11408 | macro_build (NULL, "nop", ""); | |
252b5132 | 11409 | } |
67c0d1eb RS |
11410 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11411 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 11412 | mips_gp_register); |
269137b2 | 11413 | load_delay_nop (); |
67c0d1eb RS |
11414 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
11415 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 11416 | relax_end (); |
df58fc94 | 11417 | macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0); |
438c16b8 | 11418 | |
6478892d | 11419 | if (mips_cprestore_offset < 0) |
1661c76c | 11420 | as_warn (_("no .cprestore pseudo-op used in PIC code")); |
6478892d TS |
11421 | else |
11422 | { | |
90ecf173 | 11423 | if (!mips_frame_reg_valid) |
7a621144 | 11424 | { |
1661c76c | 11425 | as_warn (_("no .frame pseudo-op used in PIC code")); |
7a621144 DJ |
11426 | /* Quiet this warning. */ |
11427 | mips_frame_reg_valid = 1; | |
11428 | } | |
90ecf173 | 11429 | if (!mips_cprestore_valid) |
7a621144 | 11430 | { |
1661c76c | 11431 | as_warn (_("no .cprestore pseudo-op used in PIC code")); |
7a621144 DJ |
11432 | /* Quiet this warning. */ |
11433 | mips_cprestore_valid = 1; | |
11434 | } | |
6478892d | 11435 | if (mips_opts.noreorder) |
67c0d1eb | 11436 | macro_build (NULL, "nop", ""); |
6478892d | 11437 | expr1.X_add_number = mips_cprestore_offset; |
134c0c8b | 11438 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 11439 | mips_gp_register, |
256ab948 TS |
11440 | mips_frame_reg, |
11441 | HAVE_64BIT_ADDRESSES); | |
6478892d | 11442 | } |
252b5132 RH |
11443 | } |
11444 | } | |
0a44bf69 | 11445 | else if (mips_pic == VXWORKS_PIC) |
1661c76c | 11446 | as_bad (_("non-PIC jump used in PIC library")); |
252b5132 RH |
11447 | else |
11448 | abort (); | |
11449 | ||
8fc2e39e | 11450 | break; |
252b5132 | 11451 | |
7f3c4072 | 11452 | case M_LBUE_AB: |
7f3c4072 CM |
11453 | s = "lbue"; |
11454 | fmt = "t,+j(b)"; | |
11455 | offbits = 9; | |
11456 | goto ld_st; | |
11457 | case M_LHUE_AB: | |
7f3c4072 CM |
11458 | s = "lhue"; |
11459 | fmt = "t,+j(b)"; | |
11460 | offbits = 9; | |
11461 | goto ld_st; | |
11462 | case M_LBE_AB: | |
7f3c4072 CM |
11463 | s = "lbe"; |
11464 | fmt = "t,+j(b)"; | |
11465 | offbits = 9; | |
11466 | goto ld_st; | |
11467 | case M_LHE_AB: | |
7f3c4072 CM |
11468 | s = "lhe"; |
11469 | fmt = "t,+j(b)"; | |
11470 | offbits = 9; | |
11471 | goto ld_st; | |
11472 | case M_LLE_AB: | |
7f3c4072 CM |
11473 | s = "lle"; |
11474 | fmt = "t,+j(b)"; | |
11475 | offbits = 9; | |
11476 | goto ld_st; | |
11477 | case M_LWE_AB: | |
7f3c4072 CM |
11478 | s = "lwe"; |
11479 | fmt = "t,+j(b)"; | |
11480 | offbits = 9; | |
11481 | goto ld_st; | |
11482 | case M_LWLE_AB: | |
7f3c4072 CM |
11483 | s = "lwle"; |
11484 | fmt = "t,+j(b)"; | |
11485 | offbits = 9; | |
11486 | goto ld_st; | |
11487 | case M_LWRE_AB: | |
7f3c4072 CM |
11488 | s = "lwre"; |
11489 | fmt = "t,+j(b)"; | |
11490 | offbits = 9; | |
11491 | goto ld_st; | |
11492 | case M_SBE_AB: | |
7f3c4072 CM |
11493 | s = "sbe"; |
11494 | fmt = "t,+j(b)"; | |
11495 | offbits = 9; | |
11496 | goto ld_st; | |
11497 | case M_SCE_AB: | |
7f3c4072 CM |
11498 | s = "sce"; |
11499 | fmt = "t,+j(b)"; | |
11500 | offbits = 9; | |
11501 | goto ld_st; | |
11502 | case M_SHE_AB: | |
7f3c4072 CM |
11503 | s = "she"; |
11504 | fmt = "t,+j(b)"; | |
11505 | offbits = 9; | |
11506 | goto ld_st; | |
11507 | case M_SWE_AB: | |
7f3c4072 CM |
11508 | s = "swe"; |
11509 | fmt = "t,+j(b)"; | |
11510 | offbits = 9; | |
11511 | goto ld_st; | |
11512 | case M_SWLE_AB: | |
7f3c4072 CM |
11513 | s = "swle"; |
11514 | fmt = "t,+j(b)"; | |
11515 | offbits = 9; | |
11516 | goto ld_st; | |
11517 | case M_SWRE_AB: | |
7f3c4072 CM |
11518 | s = "swre"; |
11519 | fmt = "t,+j(b)"; | |
11520 | offbits = 9; | |
11521 | goto ld_st; | |
dec0624d | 11522 | case M_ACLR_AB: |
dec0624d | 11523 | s = "aclr"; |
dec0624d | 11524 | fmt = "\\,~(b)"; |
7f3c4072 | 11525 | offbits = 12; |
dec0624d MR |
11526 | goto ld_st; |
11527 | case M_ASET_AB: | |
dec0624d | 11528 | s = "aset"; |
dec0624d | 11529 | fmt = "\\,~(b)"; |
7f3c4072 | 11530 | offbits = 12; |
dec0624d | 11531 | goto ld_st; |
252b5132 RH |
11532 | case M_LB_AB: |
11533 | s = "lb"; | |
df58fc94 | 11534 | fmt = "t,o(b)"; |
252b5132 RH |
11535 | goto ld; |
11536 | case M_LBU_AB: | |
11537 | s = "lbu"; | |
df58fc94 | 11538 | fmt = "t,o(b)"; |
252b5132 RH |
11539 | goto ld; |
11540 | case M_LH_AB: | |
11541 | s = "lh"; | |
df58fc94 | 11542 | fmt = "t,o(b)"; |
252b5132 RH |
11543 | goto ld; |
11544 | case M_LHU_AB: | |
11545 | s = "lhu"; | |
df58fc94 | 11546 | fmt = "t,o(b)"; |
252b5132 RH |
11547 | goto ld; |
11548 | case M_LW_AB: | |
11549 | s = "lw"; | |
df58fc94 | 11550 | fmt = "t,o(b)"; |
252b5132 RH |
11551 | goto ld; |
11552 | case M_LWC0_AB: | |
df58fc94 | 11553 | gas_assert (!mips_opts.micromips); |
252b5132 | 11554 | s = "lwc0"; |
df58fc94 | 11555 | fmt = "E,o(b)"; |
bdaaa2e1 | 11556 | /* Itbl support may require additional care here. */ |
252b5132 | 11557 | coproc = 1; |
df58fc94 | 11558 | goto ld_st; |
252b5132 RH |
11559 | case M_LWC1_AB: |
11560 | s = "lwc1"; | |
df58fc94 | 11561 | fmt = "T,o(b)"; |
bdaaa2e1 | 11562 | /* Itbl support may require additional care here. */ |
252b5132 | 11563 | coproc = 1; |
df58fc94 | 11564 | goto ld_st; |
252b5132 RH |
11565 | case M_LWC2_AB: |
11566 | s = "lwc2"; | |
df58fc94 | 11567 | fmt = COP12_FMT; |
7361da2c AB |
11568 | offbits = (mips_opts.micromips ? 12 |
11569 | : ISA_IS_R6 (mips_opts.isa) ? 11 | |
11570 | : 16); | |
bdaaa2e1 | 11571 | /* Itbl support may require additional care here. */ |
252b5132 | 11572 | coproc = 1; |
df58fc94 | 11573 | goto ld_st; |
252b5132 | 11574 | case M_LWC3_AB: |
df58fc94 | 11575 | gas_assert (!mips_opts.micromips); |
252b5132 | 11576 | s = "lwc3"; |
df58fc94 | 11577 | fmt = "E,o(b)"; |
bdaaa2e1 | 11578 | /* Itbl support may require additional care here. */ |
252b5132 | 11579 | coproc = 1; |
df58fc94 | 11580 | goto ld_st; |
252b5132 RH |
11581 | case M_LWL_AB: |
11582 | s = "lwl"; | |
df58fc94 | 11583 | fmt = MEM12_FMT; |
7f3c4072 | 11584 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11585 | goto ld_st; |
252b5132 RH |
11586 | case M_LWR_AB: |
11587 | s = "lwr"; | |
df58fc94 | 11588 | fmt = MEM12_FMT; |
7f3c4072 | 11589 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11590 | goto ld_st; |
252b5132 | 11591 | case M_LDC1_AB: |
252b5132 | 11592 | s = "ldc1"; |
df58fc94 | 11593 | fmt = "T,o(b)"; |
bdaaa2e1 | 11594 | /* Itbl support may require additional care here. */ |
252b5132 | 11595 | coproc = 1; |
df58fc94 | 11596 | goto ld_st; |
252b5132 RH |
11597 | case M_LDC2_AB: |
11598 | s = "ldc2"; | |
df58fc94 | 11599 | fmt = COP12_FMT; |
7361da2c AB |
11600 | offbits = (mips_opts.micromips ? 12 |
11601 | : ISA_IS_R6 (mips_opts.isa) ? 11 | |
11602 | : 16); | |
bdaaa2e1 | 11603 | /* Itbl support may require additional care here. */ |
252b5132 | 11604 | coproc = 1; |
df58fc94 | 11605 | goto ld_st; |
c77c0862 | 11606 | case M_LQC2_AB: |
c77c0862 | 11607 | s = "lqc2"; |
14daeee3 | 11608 | fmt = "+7,o(b)"; |
c77c0862 RS |
11609 | /* Itbl support may require additional care here. */ |
11610 | coproc = 1; | |
11611 | goto ld_st; | |
252b5132 RH |
11612 | case M_LDC3_AB: |
11613 | s = "ldc3"; | |
df58fc94 | 11614 | fmt = "E,o(b)"; |
bdaaa2e1 | 11615 | /* Itbl support may require additional care here. */ |
252b5132 | 11616 | coproc = 1; |
df58fc94 | 11617 | goto ld_st; |
252b5132 RH |
11618 | case M_LDL_AB: |
11619 | s = "ldl"; | |
df58fc94 | 11620 | fmt = MEM12_FMT; |
7f3c4072 | 11621 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11622 | goto ld_st; |
252b5132 RH |
11623 | case M_LDR_AB: |
11624 | s = "ldr"; | |
df58fc94 | 11625 | fmt = MEM12_FMT; |
7f3c4072 | 11626 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11627 | goto ld_st; |
252b5132 RH |
11628 | case M_LL_AB: |
11629 | s = "ll"; | |
7361da2c AB |
11630 | fmt = LL_SC_FMT; |
11631 | offbits = (mips_opts.micromips ? 12 | |
11632 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
11633 | : 16); | |
252b5132 RH |
11634 | goto ld; |
11635 | case M_LLD_AB: | |
11636 | s = "lld"; | |
7361da2c AB |
11637 | fmt = LL_SC_FMT; |
11638 | offbits = (mips_opts.micromips ? 12 | |
11639 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
11640 | : 16); | |
252b5132 RH |
11641 | goto ld; |
11642 | case M_LWU_AB: | |
11643 | s = "lwu"; | |
df58fc94 | 11644 | fmt = MEM12_FMT; |
7f3c4072 | 11645 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
11646 | goto ld; |
11647 | case M_LWP_AB: | |
df58fc94 RS |
11648 | gas_assert (mips_opts.micromips); |
11649 | s = "lwp"; | |
11650 | fmt = "t,~(b)"; | |
7f3c4072 | 11651 | offbits = 12; |
df58fc94 RS |
11652 | lp = 1; |
11653 | goto ld; | |
11654 | case M_LDP_AB: | |
df58fc94 RS |
11655 | gas_assert (mips_opts.micromips); |
11656 | s = "ldp"; | |
11657 | fmt = "t,~(b)"; | |
7f3c4072 | 11658 | offbits = 12; |
df58fc94 RS |
11659 | lp = 1; |
11660 | goto ld; | |
11661 | case M_LWM_AB: | |
df58fc94 RS |
11662 | gas_assert (mips_opts.micromips); |
11663 | s = "lwm"; | |
11664 | fmt = "n,~(b)"; | |
7f3c4072 | 11665 | offbits = 12; |
df58fc94 RS |
11666 | goto ld_st; |
11667 | case M_LDM_AB: | |
df58fc94 RS |
11668 | gas_assert (mips_opts.micromips); |
11669 | s = "ldm"; | |
11670 | fmt = "n,~(b)"; | |
7f3c4072 | 11671 | offbits = 12; |
df58fc94 RS |
11672 | goto ld_st; |
11673 | ||
252b5132 | 11674 | ld: |
f19ccbda | 11675 | /* We don't want to use $0 as tempreg. */ |
c0ebe874 | 11676 | if (op[2] == op[0] + lp || op[0] + lp == ZERO) |
df58fc94 | 11677 | goto ld_st; |
252b5132 | 11678 | else |
c0ebe874 | 11679 | tempreg = op[0] + lp; |
df58fc94 RS |
11680 | goto ld_noat; |
11681 | ||
252b5132 RH |
11682 | case M_SB_AB: |
11683 | s = "sb"; | |
df58fc94 RS |
11684 | fmt = "t,o(b)"; |
11685 | goto ld_st; | |
252b5132 RH |
11686 | case M_SH_AB: |
11687 | s = "sh"; | |
df58fc94 RS |
11688 | fmt = "t,o(b)"; |
11689 | goto ld_st; | |
252b5132 RH |
11690 | case M_SW_AB: |
11691 | s = "sw"; | |
df58fc94 RS |
11692 | fmt = "t,o(b)"; |
11693 | goto ld_st; | |
252b5132 | 11694 | case M_SWC0_AB: |
df58fc94 | 11695 | gas_assert (!mips_opts.micromips); |
252b5132 | 11696 | s = "swc0"; |
df58fc94 | 11697 | fmt = "E,o(b)"; |
bdaaa2e1 | 11698 | /* Itbl support may require additional care here. */ |
252b5132 | 11699 | coproc = 1; |
df58fc94 | 11700 | goto ld_st; |
252b5132 RH |
11701 | case M_SWC1_AB: |
11702 | s = "swc1"; | |
df58fc94 | 11703 | fmt = "T,o(b)"; |
bdaaa2e1 | 11704 | /* Itbl support may require additional care here. */ |
252b5132 | 11705 | coproc = 1; |
df58fc94 | 11706 | goto ld_st; |
252b5132 RH |
11707 | case M_SWC2_AB: |
11708 | s = "swc2"; | |
df58fc94 | 11709 | fmt = COP12_FMT; |
7361da2c AB |
11710 | offbits = (mips_opts.micromips ? 12 |
11711 | : ISA_IS_R6 (mips_opts.isa) ? 11 | |
11712 | : 16); | |
bdaaa2e1 | 11713 | /* Itbl support may require additional care here. */ |
252b5132 | 11714 | coproc = 1; |
df58fc94 | 11715 | goto ld_st; |
252b5132 | 11716 | case M_SWC3_AB: |
df58fc94 | 11717 | gas_assert (!mips_opts.micromips); |
252b5132 | 11718 | s = "swc3"; |
df58fc94 | 11719 | fmt = "E,o(b)"; |
bdaaa2e1 | 11720 | /* Itbl support may require additional care here. */ |
252b5132 | 11721 | coproc = 1; |
df58fc94 | 11722 | goto ld_st; |
252b5132 RH |
11723 | case M_SWL_AB: |
11724 | s = "swl"; | |
df58fc94 | 11725 | fmt = MEM12_FMT; |
7f3c4072 | 11726 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11727 | goto ld_st; |
252b5132 RH |
11728 | case M_SWR_AB: |
11729 | s = "swr"; | |
df58fc94 | 11730 | fmt = MEM12_FMT; |
7f3c4072 | 11731 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11732 | goto ld_st; |
252b5132 RH |
11733 | case M_SC_AB: |
11734 | s = "sc"; | |
7361da2c AB |
11735 | fmt = LL_SC_FMT; |
11736 | offbits = (mips_opts.micromips ? 12 | |
11737 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
11738 | : 16); | |
df58fc94 | 11739 | goto ld_st; |
252b5132 RH |
11740 | case M_SCD_AB: |
11741 | s = "scd"; | |
7361da2c AB |
11742 | fmt = LL_SC_FMT; |
11743 | offbits = (mips_opts.micromips ? 12 | |
11744 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
11745 | : 16); | |
df58fc94 | 11746 | goto ld_st; |
d43b4baf TS |
11747 | case M_CACHE_AB: |
11748 | s = "cache"; | |
7361da2c AB |
11749 | fmt = (mips_opts.micromips ? "k,~(b)" |
11750 | : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)" | |
11751 | : "k,o(b)"); | |
11752 | offbits = (mips_opts.micromips ? 12 | |
11753 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
11754 | : 16); | |
7f3c4072 CM |
11755 | goto ld_st; |
11756 | case M_CACHEE_AB: | |
7f3c4072 CM |
11757 | s = "cachee"; |
11758 | fmt = "k,+j(b)"; | |
11759 | offbits = 9; | |
df58fc94 | 11760 | goto ld_st; |
3eebd5eb MR |
11761 | case M_PREF_AB: |
11762 | s = "pref"; | |
7361da2c AB |
11763 | fmt = (mips_opts.micromips ? "k,~(b)" |
11764 | : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)" | |
11765 | : "k,o(b)"); | |
11766 | offbits = (mips_opts.micromips ? 12 | |
11767 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
11768 | : 16); | |
7f3c4072 CM |
11769 | goto ld_st; |
11770 | case M_PREFE_AB: | |
7f3c4072 CM |
11771 | s = "prefe"; |
11772 | fmt = "k,+j(b)"; | |
11773 | offbits = 9; | |
df58fc94 | 11774 | goto ld_st; |
252b5132 | 11775 | case M_SDC1_AB: |
252b5132 | 11776 | s = "sdc1"; |
df58fc94 | 11777 | fmt = "T,o(b)"; |
252b5132 | 11778 | coproc = 1; |
bdaaa2e1 | 11779 | /* Itbl support may require additional care here. */ |
df58fc94 | 11780 | goto ld_st; |
252b5132 RH |
11781 | case M_SDC2_AB: |
11782 | s = "sdc2"; | |
df58fc94 | 11783 | fmt = COP12_FMT; |
7361da2c AB |
11784 | offbits = (mips_opts.micromips ? 12 |
11785 | : ISA_IS_R6 (mips_opts.isa) ? 11 | |
11786 | : 16); | |
c77c0862 RS |
11787 | /* Itbl support may require additional care here. */ |
11788 | coproc = 1; | |
11789 | goto ld_st; | |
11790 | case M_SQC2_AB: | |
c77c0862 | 11791 | s = "sqc2"; |
14daeee3 | 11792 | fmt = "+7,o(b)"; |
bdaaa2e1 | 11793 | /* Itbl support may require additional care here. */ |
252b5132 | 11794 | coproc = 1; |
df58fc94 | 11795 | goto ld_st; |
252b5132 | 11796 | case M_SDC3_AB: |
df58fc94 | 11797 | gas_assert (!mips_opts.micromips); |
252b5132 | 11798 | s = "sdc3"; |
df58fc94 | 11799 | fmt = "E,o(b)"; |
bdaaa2e1 | 11800 | /* Itbl support may require additional care here. */ |
252b5132 | 11801 | coproc = 1; |
df58fc94 | 11802 | goto ld_st; |
252b5132 RH |
11803 | case M_SDL_AB: |
11804 | s = "sdl"; | |
df58fc94 | 11805 | fmt = MEM12_FMT; |
7f3c4072 | 11806 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11807 | goto ld_st; |
252b5132 RH |
11808 | case M_SDR_AB: |
11809 | s = "sdr"; | |
df58fc94 | 11810 | fmt = MEM12_FMT; |
7f3c4072 | 11811 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
11812 | goto ld_st; |
11813 | case M_SWP_AB: | |
df58fc94 RS |
11814 | gas_assert (mips_opts.micromips); |
11815 | s = "swp"; | |
11816 | fmt = "t,~(b)"; | |
7f3c4072 | 11817 | offbits = 12; |
df58fc94 RS |
11818 | goto ld_st; |
11819 | case M_SDP_AB: | |
df58fc94 RS |
11820 | gas_assert (mips_opts.micromips); |
11821 | s = "sdp"; | |
11822 | fmt = "t,~(b)"; | |
7f3c4072 | 11823 | offbits = 12; |
df58fc94 RS |
11824 | goto ld_st; |
11825 | case M_SWM_AB: | |
df58fc94 RS |
11826 | gas_assert (mips_opts.micromips); |
11827 | s = "swm"; | |
11828 | fmt = "n,~(b)"; | |
7f3c4072 | 11829 | offbits = 12; |
df58fc94 RS |
11830 | goto ld_st; |
11831 | case M_SDM_AB: | |
df58fc94 RS |
11832 | gas_assert (mips_opts.micromips); |
11833 | s = "sdm"; | |
11834 | fmt = "n,~(b)"; | |
7f3c4072 | 11835 | offbits = 12; |
df58fc94 RS |
11836 | |
11837 | ld_st: | |
8fc2e39e | 11838 | tempreg = AT; |
df58fc94 | 11839 | ld_noat: |
c0ebe874 | 11840 | breg = op[2]; |
f2ae14a1 RS |
11841 | if (small_offset_p (0, align, 16)) |
11842 | { | |
11843 | /* The first case exists for M_LD_AB and M_SD_AB, which are | |
11844 | macros for o32 but which should act like normal instructions | |
11845 | otherwise. */ | |
11846 | if (offbits == 16) | |
c0ebe874 | 11847 | macro_build (&offset_expr, s, fmt, op[0], -1, offset_reloc[0], |
f2ae14a1 RS |
11848 | offset_reloc[1], offset_reloc[2], breg); |
11849 | else if (small_offset_p (0, align, offbits)) | |
11850 | { | |
11851 | if (offbits == 0) | |
c0ebe874 | 11852 | macro_build (NULL, s, fmt, op[0], breg); |
f2ae14a1 | 11853 | else |
c0ebe874 | 11854 | macro_build (NULL, s, fmt, op[0], |
c8276761 | 11855 | (int) offset_expr.X_add_number, breg); |
f2ae14a1 RS |
11856 | } |
11857 | else | |
11858 | { | |
11859 | if (tempreg == AT) | |
11860 | used_at = 1; | |
11861 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
11862 | tempreg, breg, -1, offset_reloc[0], | |
11863 | offset_reloc[1], offset_reloc[2]); | |
11864 | if (offbits == 0) | |
c0ebe874 | 11865 | macro_build (NULL, s, fmt, op[0], tempreg); |
f2ae14a1 | 11866 | else |
c0ebe874 | 11867 | macro_build (NULL, s, fmt, op[0], 0, tempreg); |
f2ae14a1 RS |
11868 | } |
11869 | break; | |
11870 | } | |
11871 | ||
11872 | if (tempreg == AT) | |
11873 | used_at = 1; | |
11874 | ||
252b5132 RH |
11875 | if (offset_expr.X_op != O_constant |
11876 | && offset_expr.X_op != O_symbol) | |
11877 | { | |
1661c76c | 11878 | as_bad (_("expression too complex")); |
252b5132 RH |
11879 | offset_expr.X_op = O_constant; |
11880 | } | |
11881 | ||
2051e8c4 MR |
11882 | if (HAVE_32BIT_ADDRESSES |
11883 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
11884 | { |
11885 | char value [32]; | |
11886 | ||
11887 | sprintf_vma (value, offset_expr.X_add_number); | |
1661c76c | 11888 | as_bad (_("number (0x%s) larger than 32 bits"), value); |
55e08f71 | 11889 | } |
2051e8c4 | 11890 | |
252b5132 RH |
11891 | /* A constant expression in PIC code can be handled just as it |
11892 | is in non PIC code. */ | |
aed1a261 RS |
11893 | if (offset_expr.X_op == O_constant) |
11894 | { | |
f2ae14a1 RS |
11895 | expr1.X_add_number = offset_high_part (offset_expr.X_add_number, |
11896 | offbits == 0 ? 16 : offbits); | |
11897 | offset_expr.X_add_number -= expr1.X_add_number; | |
df58fc94 | 11898 | |
f2ae14a1 RS |
11899 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); |
11900 | if (breg != 0) | |
11901 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
11902 | tempreg, tempreg, breg); | |
7f3c4072 | 11903 | if (offbits == 0) |
dd6a37e7 | 11904 | { |
f2ae14a1 | 11905 | if (offset_expr.X_add_number != 0) |
dd6a37e7 | 11906 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
f2ae14a1 | 11907 | "t,r,j", tempreg, tempreg, BFD_RELOC_LO16); |
c0ebe874 | 11908 | macro_build (NULL, s, fmt, op[0], tempreg); |
dd6a37e7 | 11909 | } |
7f3c4072 | 11910 | else if (offbits == 16) |
c0ebe874 | 11911 | macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, tempreg); |
df58fc94 | 11912 | else |
c0ebe874 | 11913 | macro_build (NULL, s, fmt, op[0], |
c8276761 | 11914 | (int) offset_expr.X_add_number, tempreg); |
df58fc94 | 11915 | } |
7f3c4072 | 11916 | else if (offbits != 16) |
df58fc94 | 11917 | { |
7f3c4072 | 11918 | /* The offset field is too narrow to be used for a low-part |
2b0f3761 | 11919 | relocation, so load the whole address into the auxiliary |
f2ae14a1 RS |
11920 | register. */ |
11921 | load_address (tempreg, &offset_expr, &used_at); | |
11922 | if (breg != 0) | |
11923 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
11924 | tempreg, tempreg, breg); | |
7f3c4072 | 11925 | if (offbits == 0) |
c0ebe874 | 11926 | macro_build (NULL, s, fmt, op[0], tempreg); |
dd6a37e7 | 11927 | else |
c0ebe874 | 11928 | macro_build (NULL, s, fmt, op[0], 0, tempreg); |
aed1a261 RS |
11929 | } |
11930 | else if (mips_pic == NO_PIC) | |
252b5132 RH |
11931 | { |
11932 | /* If this is a reference to a GP relative symbol, and there | |
11933 | is no base register, we want | |
c0ebe874 | 11934 | <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
11935 | Otherwise, if there is no base register, we want |
11936 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
c0ebe874 | 11937 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
252b5132 RH |
11938 | If we have a constant, we need two instructions anyhow, |
11939 | so we always use the latter form. | |
11940 | ||
11941 | If we have a base register, and this is a reference to a | |
11942 | GP relative symbol, we want | |
11943 | addu $tempreg,$breg,$gp | |
c0ebe874 | 11944 | <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
11945 | Otherwise we want |
11946 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
11947 | addu $tempreg,$tempreg,$breg | |
c0ebe874 | 11948 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
d6bc6245 | 11949 | With a constant we always use the latter case. |
76b3015f | 11950 | |
d6bc6245 TS |
11951 | With 64bit address space and no base register and $at usable, |
11952 | we want | |
11953 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
11954 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
11955 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
11956 | dsll32 $tempreg,0 | |
11957 | daddu $tempreg,$at | |
c0ebe874 | 11958 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
d6bc6245 TS |
11959 | If we have a base register, we want |
11960 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
11961 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
11962 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
11963 | daddu $at,$breg | |
11964 | dsll32 $tempreg,0 | |
11965 | daddu $tempreg,$at | |
c0ebe874 | 11966 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
d6bc6245 TS |
11967 | |
11968 | Without $at we can't generate the optimal path for superscalar | |
11969 | processors here since this would require two temporary registers. | |
11970 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
11971 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
11972 | dsll $tempreg,16 | |
11973 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
11974 | dsll $tempreg,16 | |
c0ebe874 | 11975 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
d6bc6245 TS |
11976 | If we have a base register, we want |
11977 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
11978 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
11979 | dsll $tempreg,16 | |
11980 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
11981 | dsll $tempreg,16 | |
11982 | daddu $tempreg,$tempreg,$breg | |
c0ebe874 | 11983 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
6373ee54 | 11984 | |
6caf9ef4 | 11985 | For GP relative symbols in 64bit address space we can use |
aed1a261 RS |
11986 | the same sequence as in 32bit address space. */ |
11987 | if (HAVE_64BIT_SYMBOLS) | |
d6bc6245 | 11988 | { |
aed1a261 | 11989 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 TS |
11990 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
11991 | { | |
11992 | relax_start (offset_expr.X_add_symbol); | |
11993 | if (breg == 0) | |
11994 | { | |
c0ebe874 | 11995 | macro_build (&offset_expr, s, fmt, op[0], |
6caf9ef4 TS |
11996 | BFD_RELOC_GPREL16, mips_gp_register); |
11997 | } | |
11998 | else | |
11999 | { | |
12000 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
12001 | tempreg, breg, mips_gp_register); | |
c0ebe874 | 12002 | macro_build (&offset_expr, s, fmt, op[0], |
6caf9ef4 TS |
12003 | BFD_RELOC_GPREL16, tempreg); |
12004 | } | |
12005 | relax_switch (); | |
12006 | } | |
d6bc6245 | 12007 | |
741fe287 | 12008 | if (used_at == 0 && mips_opts.at) |
d6bc6245 | 12009 | { |
df58fc94 | 12010 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb | 12011 | BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 12012 | macro_build (&offset_expr, "lui", LUI_FMT, AT, |
67c0d1eb RS |
12013 | BFD_RELOC_HI16_S); |
12014 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
12015 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 12016 | if (breg != 0) |
67c0d1eb | 12017 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
df58fc94 | 12018 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb | 12019 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
c0ebe874 | 12020 | macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, |
67c0d1eb | 12021 | tempreg); |
d6bc6245 TS |
12022 | used_at = 1; |
12023 | } | |
12024 | else | |
12025 | { | |
df58fc94 | 12026 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb RS |
12027 | BFD_RELOC_MIPS_HIGHEST); |
12028 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
12029 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 12030 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb RS |
12031 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, |
12032 | tempreg, BFD_RELOC_HI16_S); | |
df58fc94 | 12033 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
d6bc6245 | 12034 | if (breg != 0) |
67c0d1eb | 12035 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 12036 | tempreg, tempreg, breg); |
c0ebe874 | 12037 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12038 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 12039 | } |
6caf9ef4 TS |
12040 | |
12041 | if (mips_relax.sequence) | |
12042 | relax_end (); | |
8fc2e39e | 12043 | break; |
d6bc6245 | 12044 | } |
256ab948 | 12045 | |
252b5132 RH |
12046 | if (breg == 0) |
12047 | { | |
67c0d1eb | 12048 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 12049 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 12050 | { |
4d7206a2 | 12051 | relax_start (offset_expr.X_add_symbol); |
c0ebe874 | 12052 | macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_GPREL16, |
67c0d1eb | 12053 | mips_gp_register); |
4d7206a2 | 12054 | relax_switch (); |
252b5132 | 12055 | } |
67c0d1eb | 12056 | macro_build_lui (&offset_expr, tempreg); |
c0ebe874 | 12057 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12058 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
12059 | if (mips_relax.sequence) |
12060 | relax_end (); | |
252b5132 RH |
12061 | } |
12062 | else | |
12063 | { | |
67c0d1eb | 12064 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 12065 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 12066 | { |
4d7206a2 | 12067 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 12068 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12069 | tempreg, breg, mips_gp_register); |
c0ebe874 | 12070 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12071 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 12072 | relax_switch (); |
252b5132 | 12073 | } |
67c0d1eb RS |
12074 | macro_build_lui (&offset_expr, tempreg); |
12075 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 12076 | tempreg, tempreg, breg); |
c0ebe874 | 12077 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12078 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
12079 | if (mips_relax.sequence) |
12080 | relax_end (); | |
252b5132 RH |
12081 | } |
12082 | } | |
0a44bf69 | 12083 | else if (!mips_big_got) |
252b5132 | 12084 | { |
ed6fb7bd | 12085 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 12086 | |
252b5132 RH |
12087 | /* If this is a reference to an external symbol, we want |
12088 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
12089 | nop | |
c0ebe874 | 12090 | <op> op[0],0($tempreg) |
252b5132 RH |
12091 | Otherwise we want |
12092 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
12093 | nop | |
12094 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
c0ebe874 | 12095 | <op> op[0],0($tempreg) |
f5040a92 AO |
12096 | |
12097 | For NewABI, we want | |
12098 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
c0ebe874 | 12099 | <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) |
f5040a92 | 12100 | |
252b5132 RH |
12101 | If there is a base register, we add it to $tempreg before |
12102 | the <op>. If there is a constant, we stick it in the | |
12103 | <op> instruction. We don't handle constants larger than | |
12104 | 16 bits, because we have no way to load the upper 16 bits | |
12105 | (actually, we could handle them for the subset of cases | |
12106 | in which we are not using $at). */ | |
9c2799c2 | 12107 | gas_assert (offset_expr.X_op == O_symbol); |
f5040a92 AO |
12108 | if (HAVE_NEWABI) |
12109 | { | |
67c0d1eb RS |
12110 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
12111 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 12112 | if (breg != 0) |
67c0d1eb | 12113 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12114 | tempreg, tempreg, breg); |
c0ebe874 | 12115 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12116 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
12117 | break; |
12118 | } | |
252b5132 RH |
12119 | expr1.X_add_number = offset_expr.X_add_number; |
12120 | offset_expr.X_add_number = 0; | |
12121 | if (expr1.X_add_number < -0x8000 | |
12122 | || expr1.X_add_number >= 0x8000) | |
12123 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
12124 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
12125 | lw_reloc_type, mips_gp_register); | |
269137b2 | 12126 | load_delay_nop (); |
4d7206a2 RS |
12127 | relax_start (offset_expr.X_add_symbol); |
12128 | relax_switch (); | |
67c0d1eb RS |
12129 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
12130 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 12131 | relax_end (); |
252b5132 | 12132 | if (breg != 0) |
67c0d1eb | 12133 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12134 | tempreg, tempreg, breg); |
c0ebe874 | 12135 | macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg); |
252b5132 | 12136 | } |
0a44bf69 | 12137 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 12138 | { |
67c0d1eb | 12139 | int gpdelay; |
252b5132 RH |
12140 | |
12141 | /* If this is a reference to an external symbol, we want | |
12142 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
12143 | addu $tempreg,$tempreg,$gp | |
12144 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
c0ebe874 | 12145 | <op> op[0],0($tempreg) |
252b5132 RH |
12146 | Otherwise we want |
12147 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
12148 | nop | |
12149 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
c0ebe874 | 12150 | <op> op[0],0($tempreg) |
252b5132 RH |
12151 | If there is a base register, we add it to $tempreg before |
12152 | the <op>. If there is a constant, we stick it in the | |
12153 | <op> instruction. We don't handle constants larger than | |
12154 | 16 bits, because we have no way to load the upper 16 bits | |
12155 | (actually, we could handle them for the subset of cases | |
f5040a92 | 12156 | in which we are not using $at). */ |
9c2799c2 | 12157 | gas_assert (offset_expr.X_op == O_symbol); |
252b5132 RH |
12158 | expr1.X_add_number = offset_expr.X_add_number; |
12159 | offset_expr.X_add_number = 0; | |
12160 | if (expr1.X_add_number < -0x8000 | |
12161 | || expr1.X_add_number >= 0x8000) | |
12162 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 12163 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 12164 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 12165 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 12166 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
12167 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
12168 | mips_gp_register); | |
12169 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
12170 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 12171 | relax_switch (); |
67c0d1eb RS |
12172 | if (gpdelay) |
12173 | macro_build (NULL, "nop", ""); | |
12174 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
12175 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 12176 | load_delay_nop (); |
67c0d1eb RS |
12177 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
12178 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
12179 | relax_end (); |
12180 | ||
252b5132 | 12181 | if (breg != 0) |
67c0d1eb | 12182 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12183 | tempreg, tempreg, breg); |
c0ebe874 | 12184 | macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg); |
252b5132 | 12185 | } |
0a44bf69 | 12186 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 12187 | { |
f5040a92 AO |
12188 | /* If this is a reference to an external symbol, we want |
12189 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
12190 | add $tempreg,$tempreg,$gp | |
12191 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
c0ebe874 | 12192 | <op> op[0],<ofst>($tempreg) |
f5040a92 AO |
12193 | Otherwise, for local symbols, we want: |
12194 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
c0ebe874 | 12195 | <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ |
9c2799c2 | 12196 | gas_assert (offset_expr.X_op == O_symbol); |
4d7206a2 | 12197 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
12198 | offset_expr.X_add_number = 0; |
12199 | if (expr1.X_add_number < -0x8000 | |
12200 | || expr1.X_add_number >= 0x8000) | |
12201 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 12202 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 12203 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 12204 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
12205 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
12206 | mips_gp_register); | |
12207 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
12208 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 12209 | if (breg != 0) |
67c0d1eb | 12210 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12211 | tempreg, tempreg, breg); |
c0ebe874 | 12212 | macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg); |
684022ea | 12213 | |
4d7206a2 | 12214 | relax_switch (); |
f5040a92 | 12215 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
12216 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
12217 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 12218 | if (breg != 0) |
67c0d1eb | 12219 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12220 | tempreg, tempreg, breg); |
c0ebe874 | 12221 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12222 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 12223 | relax_end (); |
f5040a92 | 12224 | } |
252b5132 RH |
12225 | else |
12226 | abort (); | |
12227 | ||
252b5132 RH |
12228 | break; |
12229 | ||
833794fc MR |
12230 | case M_JRADDIUSP: |
12231 | gas_assert (mips_opts.micromips); | |
12232 | gas_assert (mips_opts.insn32); | |
12233 | start_noreorder (); | |
12234 | macro_build (NULL, "jr", "s", RA); | |
c0ebe874 | 12235 | expr1.X_add_number = op[0] << 2; |
833794fc MR |
12236 | macro_build (&expr1, "addiu", "t,r,j", SP, SP, BFD_RELOC_LO16); |
12237 | end_noreorder (); | |
12238 | break; | |
12239 | ||
12240 | case M_JRC: | |
12241 | gas_assert (mips_opts.micromips); | |
12242 | gas_assert (mips_opts.insn32); | |
c0ebe874 | 12243 | macro_build (NULL, "jr", "s", op[0]); |
833794fc MR |
12244 | if (mips_opts.noreorder) |
12245 | macro_build (NULL, "nop", ""); | |
12246 | break; | |
12247 | ||
252b5132 RH |
12248 | case M_LI: |
12249 | case M_LI_S: | |
c0ebe874 | 12250 | load_register (op[0], &imm_expr, 0); |
8fc2e39e | 12251 | break; |
252b5132 RH |
12252 | |
12253 | case M_DLI: | |
c0ebe874 | 12254 | load_register (op[0], &imm_expr, 1); |
8fc2e39e | 12255 | break; |
252b5132 RH |
12256 | |
12257 | case M_LI_SS: | |
12258 | if (imm_expr.X_op == O_constant) | |
12259 | { | |
8fc2e39e | 12260 | used_at = 1; |
67c0d1eb | 12261 | load_register (AT, &imm_expr, 0); |
c0ebe874 | 12262 | macro_build (NULL, "mtc1", "t,G", AT, op[0]); |
252b5132 RH |
12263 | break; |
12264 | } | |
12265 | else | |
12266 | { | |
b0e6f033 RS |
12267 | gas_assert (imm_expr.X_op == O_absent |
12268 | && offset_expr.X_op == O_symbol | |
90ecf173 MR |
12269 | && strcmp (segment_name (S_GET_SEGMENT |
12270 | (offset_expr.X_add_symbol)), | |
12271 | ".lit4") == 0 | |
12272 | && offset_expr.X_add_number == 0); | |
c0ebe874 | 12273 | macro_build (&offset_expr, "lwc1", "T,o(b)", op[0], |
17a2f251 | 12274 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 12275 | break; |
252b5132 RH |
12276 | } |
12277 | ||
12278 | case M_LI_D: | |
ca4e0257 RS |
12279 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
12280 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
12281 | order 32 bits of the value and the low order 32 bits are either | |
12282 | zero or in OFFSET_EXPR. */ | |
b0e6f033 | 12283 | if (imm_expr.X_op == O_constant) |
252b5132 | 12284 | { |
bad1aba3 | 12285 | if (GPR_SIZE == 64) |
c0ebe874 | 12286 | load_register (op[0], &imm_expr, 1); |
252b5132 RH |
12287 | else |
12288 | { | |
12289 | int hreg, lreg; | |
12290 | ||
12291 | if (target_big_endian) | |
12292 | { | |
c0ebe874 RS |
12293 | hreg = op[0]; |
12294 | lreg = op[0] + 1; | |
252b5132 RH |
12295 | } |
12296 | else | |
12297 | { | |
c0ebe874 RS |
12298 | hreg = op[0] + 1; |
12299 | lreg = op[0]; | |
252b5132 RH |
12300 | } |
12301 | ||
12302 | if (hreg <= 31) | |
67c0d1eb | 12303 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
12304 | if (lreg <= 31) |
12305 | { | |
12306 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 12307 | move_register (lreg, 0); |
252b5132 RH |
12308 | else |
12309 | { | |
9c2799c2 | 12310 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb | 12311 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
12312 | } |
12313 | } | |
12314 | } | |
8fc2e39e | 12315 | break; |
252b5132 | 12316 | } |
b0e6f033 | 12317 | gas_assert (imm_expr.X_op == O_absent); |
252b5132 RH |
12318 | |
12319 | /* We know that sym is in the .rdata section. First we get the | |
12320 | upper 16 bits of the address. */ | |
12321 | if (mips_pic == NO_PIC) | |
12322 | { | |
67c0d1eb | 12323 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 12324 | used_at = 1; |
252b5132 | 12325 | } |
0a44bf69 | 12326 | else |
252b5132 | 12327 | { |
67c0d1eb RS |
12328 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
12329 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 12330 | used_at = 1; |
252b5132 | 12331 | } |
bdaaa2e1 | 12332 | |
252b5132 | 12333 | /* Now we load the register(s). */ |
bad1aba3 | 12334 | if (GPR_SIZE == 64) |
8fc2e39e TS |
12335 | { |
12336 | used_at = 1; | |
c0ebe874 RS |
12337 | macro_build (&offset_expr, "ld", "t,o(b)", op[0], |
12338 | BFD_RELOC_LO16, AT); | |
8fc2e39e | 12339 | } |
252b5132 RH |
12340 | else |
12341 | { | |
8fc2e39e | 12342 | used_at = 1; |
c0ebe874 RS |
12343 | macro_build (&offset_expr, "lw", "t,o(b)", op[0], |
12344 | BFD_RELOC_LO16, AT); | |
12345 | if (op[0] != RA) | |
252b5132 RH |
12346 | { |
12347 | /* FIXME: How in the world do we deal with the possible | |
12348 | overflow here? */ | |
12349 | offset_expr.X_add_number += 4; | |
67c0d1eb | 12350 | macro_build (&offset_expr, "lw", "t,o(b)", |
c0ebe874 | 12351 | op[0] + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
12352 | } |
12353 | } | |
252b5132 RH |
12354 | break; |
12355 | ||
12356 | case M_LI_DD: | |
ca4e0257 RS |
12357 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
12358 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
12359 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
12360 | the value and the low order 32 bits are either zero or in | |
12361 | OFFSET_EXPR. */ | |
b0e6f033 | 12362 | if (imm_expr.X_op == O_constant) |
252b5132 | 12363 | { |
8fc2e39e | 12364 | used_at = 1; |
bad1aba3 | 12365 | load_register (AT, &imm_expr, FPR_SIZE == 64); |
351cdf24 MF |
12366 | if (FPR_SIZE == 64 && GPR_SIZE == 64) |
12367 | macro_build (NULL, "dmtc1", "t,S", AT, op[0]); | |
252b5132 RH |
12368 | else |
12369 | { | |
351cdf24 MF |
12370 | if (ISA_HAS_MXHC1 (mips_opts.isa)) |
12371 | macro_build (NULL, "mthc1", "t,G", AT, op[0]); | |
12372 | else if (FPR_SIZE != 32) | |
12373 | as_bad (_("Unable to generate `%s' compliant code " | |
12374 | "without mthc1"), | |
12375 | (FPR_SIZE == 64) ? "fp64" : "fpxx"); | |
12376 | else | |
12377 | macro_build (NULL, "mtc1", "t,G", AT, op[0] + 1); | |
252b5132 | 12378 | if (offset_expr.X_op == O_absent) |
c0ebe874 | 12379 | macro_build (NULL, "mtc1", "t,G", 0, op[0]); |
252b5132 RH |
12380 | else |
12381 | { | |
9c2799c2 | 12382 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb | 12383 | load_register (AT, &offset_expr, 0); |
c0ebe874 | 12384 | macro_build (NULL, "mtc1", "t,G", AT, op[0]); |
252b5132 RH |
12385 | } |
12386 | } | |
12387 | break; | |
12388 | } | |
12389 | ||
b0e6f033 RS |
12390 | gas_assert (imm_expr.X_op == O_absent |
12391 | && offset_expr.X_op == O_symbol | |
90ecf173 | 12392 | && offset_expr.X_add_number == 0); |
252b5132 RH |
12393 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); |
12394 | if (strcmp (s, ".lit8") == 0) | |
134c0c8b MR |
12395 | { |
12396 | op[2] = mips_gp_register; | |
f2ae14a1 RS |
12397 | offset_reloc[0] = BFD_RELOC_MIPS_LITERAL; |
12398 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
12399 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
12400 | } |
12401 | else | |
12402 | { | |
9c2799c2 | 12403 | gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
8fc2e39e | 12404 | used_at = 1; |
0a44bf69 | 12405 | if (mips_pic != NO_PIC) |
67c0d1eb RS |
12406 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
12407 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
12408 | else |
12409 | { | |
12410 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 12411 | macro_build_lui (&offset_expr, AT); |
252b5132 | 12412 | } |
bdaaa2e1 | 12413 | |
c0ebe874 | 12414 | op[2] = AT; |
f2ae14a1 RS |
12415 | offset_reloc[0] = BFD_RELOC_LO16; |
12416 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
12417 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
134c0c8b | 12418 | } |
f2ae14a1 RS |
12419 | align = 8; |
12420 | /* Fall through */ | |
c4a68bea | 12421 | |
252b5132 RH |
12422 | case M_L_DAB: |
12423 | /* | |
12424 | * The MIPS assembler seems to check for X_add_number not | |
12425 | * being double aligned and generating: | |
12426 | * lui at,%hi(foo+1) | |
12427 | * addu at,at,v1 | |
12428 | * addiu at,at,%lo(foo+1) | |
12429 | * lwc1 f2,0(at) | |
12430 | * lwc1 f3,4(at) | |
12431 | * But, the resulting address is the same after relocation so why | |
12432 | * generate the extra instruction? | |
12433 | */ | |
bdaaa2e1 | 12434 | /* Itbl support may require additional care here. */ |
252b5132 | 12435 | coproc = 1; |
df58fc94 | 12436 | fmt = "T,o(b)"; |
0aa27725 | 12437 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch)) |
252b5132 RH |
12438 | { |
12439 | s = "ldc1"; | |
df58fc94 | 12440 | goto ld_st; |
252b5132 | 12441 | } |
252b5132 | 12442 | s = "lwc1"; |
252b5132 RH |
12443 | goto ldd_std; |
12444 | ||
12445 | case M_S_DAB: | |
df58fc94 RS |
12446 | gas_assert (!mips_opts.micromips); |
12447 | /* Itbl support may require additional care here. */ | |
12448 | coproc = 1; | |
12449 | fmt = "T,o(b)"; | |
0aa27725 | 12450 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch)) |
252b5132 RH |
12451 | { |
12452 | s = "sdc1"; | |
df58fc94 | 12453 | goto ld_st; |
252b5132 | 12454 | } |
252b5132 | 12455 | s = "swc1"; |
252b5132 RH |
12456 | goto ldd_std; |
12457 | ||
e407c74b NC |
12458 | case M_LQ_AB: |
12459 | fmt = "t,o(b)"; | |
12460 | s = "lq"; | |
12461 | goto ld; | |
12462 | ||
12463 | case M_SQ_AB: | |
12464 | fmt = "t,o(b)"; | |
12465 | s = "sq"; | |
12466 | goto ld_st; | |
12467 | ||
252b5132 | 12468 | case M_LD_AB: |
df58fc94 | 12469 | fmt = "t,o(b)"; |
bad1aba3 | 12470 | if (GPR_SIZE == 64) |
252b5132 RH |
12471 | { |
12472 | s = "ld"; | |
12473 | goto ld; | |
12474 | } | |
252b5132 | 12475 | s = "lw"; |
252b5132 RH |
12476 | goto ldd_std; |
12477 | ||
12478 | case M_SD_AB: | |
df58fc94 | 12479 | fmt = "t,o(b)"; |
bad1aba3 | 12480 | if (GPR_SIZE == 64) |
252b5132 RH |
12481 | { |
12482 | s = "sd"; | |
df58fc94 | 12483 | goto ld_st; |
252b5132 | 12484 | } |
252b5132 | 12485 | s = "sw"; |
252b5132 RH |
12486 | |
12487 | ldd_std: | |
f2ae14a1 RS |
12488 | /* Even on a big endian machine $fn comes before $fn+1. We have |
12489 | to adjust when loading from memory. We set coproc if we must | |
12490 | load $fn+1 first. */ | |
12491 | /* Itbl support may require additional care here. */ | |
12492 | if (!target_big_endian) | |
12493 | coproc = 0; | |
12494 | ||
c0ebe874 | 12495 | breg = op[2]; |
f2ae14a1 RS |
12496 | if (small_offset_p (0, align, 16)) |
12497 | { | |
12498 | ep = &offset_expr; | |
12499 | if (!small_offset_p (4, align, 16)) | |
12500 | { | |
12501 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT, breg, | |
12502 | -1, offset_reloc[0], offset_reloc[1], | |
12503 | offset_reloc[2]); | |
12504 | expr1.X_add_number = 0; | |
12505 | ep = &expr1; | |
12506 | breg = AT; | |
12507 | used_at = 1; | |
12508 | offset_reloc[0] = BFD_RELOC_LO16; | |
12509 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
12510 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
12511 | } | |
c0ebe874 | 12512 | if (strcmp (s, "lw") == 0 && op[0] == breg) |
f2ae14a1 RS |
12513 | { |
12514 | ep->X_add_number += 4; | |
c0ebe874 | 12515 | macro_build (ep, s, fmt, op[0] + 1, -1, offset_reloc[0], |
f2ae14a1 RS |
12516 | offset_reloc[1], offset_reloc[2], breg); |
12517 | ep->X_add_number -= 4; | |
c0ebe874 | 12518 | macro_build (ep, s, fmt, op[0], -1, offset_reloc[0], |
f2ae14a1 RS |
12519 | offset_reloc[1], offset_reloc[2], breg); |
12520 | } | |
12521 | else | |
12522 | { | |
c0ebe874 | 12523 | macro_build (ep, s, fmt, coproc ? op[0] + 1 : op[0], -1, |
f2ae14a1 RS |
12524 | offset_reloc[0], offset_reloc[1], offset_reloc[2], |
12525 | breg); | |
12526 | ep->X_add_number += 4; | |
c0ebe874 | 12527 | macro_build (ep, s, fmt, coproc ? op[0] : op[0] + 1, -1, |
f2ae14a1 RS |
12528 | offset_reloc[0], offset_reloc[1], offset_reloc[2], |
12529 | breg); | |
12530 | } | |
12531 | break; | |
12532 | } | |
12533 | ||
252b5132 RH |
12534 | if (offset_expr.X_op != O_symbol |
12535 | && offset_expr.X_op != O_constant) | |
12536 | { | |
1661c76c | 12537 | as_bad (_("expression too complex")); |
252b5132 RH |
12538 | offset_expr.X_op = O_constant; |
12539 | } | |
12540 | ||
2051e8c4 MR |
12541 | if (HAVE_32BIT_ADDRESSES |
12542 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
12543 | { |
12544 | char value [32]; | |
12545 | ||
12546 | sprintf_vma (value, offset_expr.X_add_number); | |
1661c76c | 12547 | as_bad (_("number (0x%s) larger than 32 bits"), value); |
55e08f71 | 12548 | } |
2051e8c4 | 12549 | |
90ecf173 | 12550 | if (mips_pic == NO_PIC || offset_expr.X_op == O_constant) |
252b5132 RH |
12551 | { |
12552 | /* If this is a reference to a GP relative symbol, we want | |
c0ebe874 RS |
12553 | <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16) |
12554 | <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
12555 | If we have a base register, we use this |
12556 | addu $at,$breg,$gp | |
c0ebe874 RS |
12557 | <op> op[0],<sym>($at) (BFD_RELOC_GPREL16) |
12558 | <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
12559 | If this is not a GP relative symbol, we want |
12560 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
c0ebe874 RS |
12561 | <op> op[0],<sym>($at) (BFD_RELOC_LO16) |
12562 | <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16) | |
252b5132 RH |
12563 | If there is a base register, we add it to $at after the |
12564 | lui instruction. If there is a constant, we always use | |
12565 | the last case. */ | |
39a59cf8 MR |
12566 | if (offset_expr.X_op == O_symbol |
12567 | && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 12568 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 12569 | { |
4d7206a2 | 12570 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
12571 | if (breg == 0) |
12572 | { | |
c9914766 | 12573 | tempreg = mips_gp_register; |
252b5132 RH |
12574 | } |
12575 | else | |
12576 | { | |
67c0d1eb | 12577 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12578 | AT, breg, mips_gp_register); |
252b5132 | 12579 | tempreg = AT; |
252b5132 RH |
12580 | used_at = 1; |
12581 | } | |
12582 | ||
beae10d5 | 12583 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12584 | macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], |
17a2f251 | 12585 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
12586 | offset_expr.X_add_number += 4; |
12587 | ||
12588 | /* Set mips_optimize to 2 to avoid inserting an | |
12589 | undesired nop. */ | |
12590 | hold_mips_optimize = mips_optimize; | |
12591 | mips_optimize = 2; | |
beae10d5 | 12592 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12593 | macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, |
17a2f251 | 12594 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
12595 | mips_optimize = hold_mips_optimize; |
12596 | ||
4d7206a2 | 12597 | relax_switch (); |
252b5132 | 12598 | |
0970e49e | 12599 | offset_expr.X_add_number -= 4; |
252b5132 | 12600 | } |
8fc2e39e | 12601 | used_at = 1; |
f2ae14a1 RS |
12602 | if (offset_high_part (offset_expr.X_add_number, 16) |
12603 | != offset_high_part (offset_expr.X_add_number + 4, 16)) | |
12604 | { | |
12605 | load_address (AT, &offset_expr, &used_at); | |
12606 | offset_expr.X_op = O_constant; | |
12607 | offset_expr.X_add_number = 0; | |
12608 | } | |
12609 | else | |
12610 | macro_build_lui (&offset_expr, AT); | |
252b5132 | 12611 | if (breg != 0) |
67c0d1eb | 12612 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 12613 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12614 | macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], |
17a2f251 | 12615 | BFD_RELOC_LO16, AT); |
252b5132 RH |
12616 | /* FIXME: How do we handle overflow here? */ |
12617 | offset_expr.X_add_number += 4; | |
beae10d5 | 12618 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12619 | macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, |
17a2f251 | 12620 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
12621 | if (mips_relax.sequence) |
12622 | relax_end (); | |
bdaaa2e1 | 12623 | } |
0a44bf69 | 12624 | else if (!mips_big_got) |
252b5132 | 12625 | { |
252b5132 RH |
12626 | /* If this is a reference to an external symbol, we want |
12627 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
12628 | nop | |
c0ebe874 RS |
12629 | <op> op[0],0($at) |
12630 | <op> op[0]+1,4($at) | |
252b5132 RH |
12631 | Otherwise we want |
12632 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
12633 | nop | |
c0ebe874 RS |
12634 | <op> op[0],<sym>($at) (BFD_RELOC_LO16) |
12635 | <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16) | |
252b5132 RH |
12636 | If there is a base register we add it to $at before the |
12637 | lwc1 instructions. If there is a constant we include it | |
12638 | in the lwc1 instructions. */ | |
12639 | used_at = 1; | |
12640 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
12641 | if (expr1.X_add_number < -0x8000 |
12642 | || expr1.X_add_number >= 0x8000 - 4) | |
12643 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 12644 | load_got_offset (AT, &offset_expr); |
269137b2 | 12645 | load_delay_nop (); |
252b5132 | 12646 | if (breg != 0) |
67c0d1eb | 12647 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
12648 | |
12649 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
12650 | nop. */ | |
12651 | hold_mips_optimize = mips_optimize; | |
12652 | mips_optimize = 2; | |
4d7206a2 | 12653 | |
beae10d5 | 12654 | /* Itbl support may require additional care here. */ |
4d7206a2 | 12655 | relax_start (offset_expr.X_add_symbol); |
c0ebe874 | 12656 | macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0], |
67c0d1eb | 12657 | BFD_RELOC_LO16, AT); |
4d7206a2 | 12658 | expr1.X_add_number += 4; |
c0ebe874 | 12659 | macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1, |
67c0d1eb | 12660 | BFD_RELOC_LO16, AT); |
4d7206a2 | 12661 | relax_switch (); |
c0ebe874 | 12662 | macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], |
67c0d1eb | 12663 | BFD_RELOC_LO16, AT); |
4d7206a2 | 12664 | offset_expr.X_add_number += 4; |
c0ebe874 | 12665 | macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, |
67c0d1eb | 12666 | BFD_RELOC_LO16, AT); |
4d7206a2 | 12667 | relax_end (); |
252b5132 | 12668 | |
4d7206a2 | 12669 | mips_optimize = hold_mips_optimize; |
252b5132 | 12670 | } |
0a44bf69 | 12671 | else if (mips_big_got) |
252b5132 | 12672 | { |
67c0d1eb | 12673 | int gpdelay; |
252b5132 RH |
12674 | |
12675 | /* If this is a reference to an external symbol, we want | |
12676 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
12677 | addu $at,$at,$gp | |
12678 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
12679 | nop | |
c0ebe874 RS |
12680 | <op> op[0],0($at) |
12681 | <op> op[0]+1,4($at) | |
252b5132 RH |
12682 | Otherwise we want |
12683 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
12684 | nop | |
c0ebe874 RS |
12685 | <op> op[0],<sym>($at) (BFD_RELOC_LO16) |
12686 | <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16) | |
252b5132 RH |
12687 | If there is a base register we add it to $at before the |
12688 | lwc1 instructions. If there is a constant we include it | |
12689 | in the lwc1 instructions. */ | |
12690 | used_at = 1; | |
12691 | expr1.X_add_number = offset_expr.X_add_number; | |
12692 | offset_expr.X_add_number = 0; | |
12693 | if (expr1.X_add_number < -0x8000 | |
12694 | || expr1.X_add_number >= 0x8000 - 4) | |
12695 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 12696 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 12697 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 12698 | macro_build (&offset_expr, "lui", LUI_FMT, |
67c0d1eb RS |
12699 | AT, BFD_RELOC_MIPS_GOT_HI16); |
12700 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 12701 | AT, AT, mips_gp_register); |
67c0d1eb | 12702 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 12703 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 12704 | load_delay_nop (); |
252b5132 | 12705 | if (breg != 0) |
67c0d1eb | 12706 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 12707 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12708 | macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0], |
17a2f251 | 12709 | BFD_RELOC_LO16, AT); |
252b5132 RH |
12710 | expr1.X_add_number += 4; |
12711 | ||
12712 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
12713 | nop. */ | |
12714 | hold_mips_optimize = mips_optimize; | |
12715 | mips_optimize = 2; | |
beae10d5 | 12716 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12717 | macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1, |
17a2f251 | 12718 | BFD_RELOC_LO16, AT); |
252b5132 RH |
12719 | mips_optimize = hold_mips_optimize; |
12720 | expr1.X_add_number -= 4; | |
12721 | ||
4d7206a2 RS |
12722 | relax_switch (); |
12723 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
12724 | if (gpdelay) |
12725 | macro_build (NULL, "nop", ""); | |
12726 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
12727 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 12728 | load_delay_nop (); |
252b5132 | 12729 | if (breg != 0) |
67c0d1eb | 12730 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 12731 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12732 | macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], |
67c0d1eb | 12733 | BFD_RELOC_LO16, AT); |
4d7206a2 | 12734 | offset_expr.X_add_number += 4; |
252b5132 RH |
12735 | |
12736 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
12737 | nop. */ | |
12738 | hold_mips_optimize = mips_optimize; | |
12739 | mips_optimize = 2; | |
beae10d5 | 12740 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12741 | macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, |
67c0d1eb | 12742 | BFD_RELOC_LO16, AT); |
252b5132 | 12743 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 12744 | relax_end (); |
252b5132 | 12745 | } |
252b5132 RH |
12746 | else |
12747 | abort (); | |
12748 | ||
252b5132 | 12749 | break; |
3739860c | 12750 | |
dd6a37e7 | 12751 | case M_SAA_AB: |
dd6a37e7 | 12752 | s = "saa"; |
0db377d0 | 12753 | goto saa_saad; |
dd6a37e7 | 12754 | case M_SAAD_AB: |
dd6a37e7 | 12755 | s = "saad"; |
0db377d0 MR |
12756 | saa_saad: |
12757 | gas_assert (!mips_opts.micromips); | |
7f3c4072 | 12758 | offbits = 0; |
dd6a37e7 AP |
12759 | fmt = "t,(b)"; |
12760 | goto ld_st; | |
12761 | ||
252b5132 RH |
12762 | /* New code added to support COPZ instructions. |
12763 | This code builds table entries out of the macros in mip_opcodes. | |
12764 | R4000 uses interlocks to handle coproc delays. | |
12765 | Other chips (like the R3000) require nops to be inserted for delays. | |
12766 | ||
f72c8c98 | 12767 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
12768 | In order to fill delay slots for non-interlocked chips, |
12769 | we must have a way to specify delays based on the coprocessor. | |
12770 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
12771 | What are the side-effects of the cop instruction? | |
12772 | What cache support might we have and what are its effects? | |
12773 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 12774 | What registers are read/set/modified? |
252b5132 RH |
12775 | |
12776 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 12777 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
12778 | |
12779 | case M_COP0: | |
12780 | s = "c0"; | |
12781 | goto copz; | |
12782 | case M_COP1: | |
12783 | s = "c1"; | |
12784 | goto copz; | |
12785 | case M_COP2: | |
12786 | s = "c2"; | |
12787 | goto copz; | |
12788 | case M_COP3: | |
12789 | s = "c3"; | |
12790 | copz: | |
df58fc94 | 12791 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
12792 | /* For now we just do C (same as Cz). The parameter will be |
12793 | stored in insn_opcode by mips_ip. */ | |
c8276761 | 12794 | macro_build (NULL, s, "C", (int) ip->insn_opcode); |
8fc2e39e | 12795 | break; |
252b5132 | 12796 | |
ea1fb5dc | 12797 | case M_MOVE: |
c0ebe874 | 12798 | move_register (op[0], op[1]); |
8fc2e39e | 12799 | break; |
ea1fb5dc | 12800 | |
833794fc MR |
12801 | case M_MOVEP: |
12802 | gas_assert (mips_opts.micromips); | |
12803 | gas_assert (mips_opts.insn32); | |
c0ebe874 RS |
12804 | move_register (micromips_to_32_reg_h_map1[op[0]], |
12805 | micromips_to_32_reg_m_map[op[1]]); | |
12806 | move_register (micromips_to_32_reg_h_map2[op[0]], | |
12807 | micromips_to_32_reg_n_map[op[2]]); | |
833794fc MR |
12808 | break; |
12809 | ||
252b5132 RH |
12810 | case M_DMUL: |
12811 | dbl = 1; | |
1a0670f3 | 12812 | /* Fall through. */ |
252b5132 | 12813 | case M_MUL: |
e407c74b | 12814 | if (mips_opts.arch == CPU_R5900) |
c0ebe874 RS |
12815 | macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", op[0], op[1], |
12816 | op[2]); | |
e407c74b NC |
12817 | else |
12818 | { | |
c0ebe874 RS |
12819 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", op[1], op[2]); |
12820 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); | |
e407c74b | 12821 | } |
8fc2e39e | 12822 | break; |
252b5132 RH |
12823 | |
12824 | case M_DMUL_I: | |
12825 | dbl = 1; | |
1a0670f3 | 12826 | /* Fall through. */ |
252b5132 RH |
12827 | case M_MUL_I: |
12828 | /* The MIPS assembler some times generates shifts and adds. I'm | |
12829 | not trying to be that fancy. GCC should do this for us | |
12830 | anyway. */ | |
8fc2e39e | 12831 | used_at = 1; |
67c0d1eb | 12832 | load_register (AT, &imm_expr, dbl); |
c0ebe874 RS |
12833 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", op[1], AT); |
12834 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); | |
252b5132 RH |
12835 | break; |
12836 | ||
12837 | case M_DMULO_I: | |
12838 | dbl = 1; | |
1a0670f3 | 12839 | /* Fall through. */ |
252b5132 RH |
12840 | case M_MULO_I: |
12841 | imm = 1; | |
12842 | goto do_mulo; | |
12843 | ||
12844 | case M_DMULO: | |
12845 | dbl = 1; | |
1a0670f3 | 12846 | /* Fall through. */ |
252b5132 RH |
12847 | case M_MULO: |
12848 | do_mulo: | |
7d10b47d | 12849 | start_noreorder (); |
8fc2e39e | 12850 | used_at = 1; |
252b5132 | 12851 | if (imm) |
67c0d1eb | 12852 | load_register (AT, &imm_expr, dbl); |
c0ebe874 RS |
12853 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", |
12854 | op[1], imm ? AT : op[2]); | |
12855 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); | |
12856 | macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, op[0], op[0], 31); | |
df58fc94 | 12857 | macro_build (NULL, "mfhi", MFHL_FMT, AT); |
252b5132 | 12858 | if (mips_trap) |
c0ebe874 | 12859 | macro_build (NULL, "tne", TRAP_FMT, op[0], AT, 6); |
252b5132 RH |
12860 | else |
12861 | { | |
df58fc94 RS |
12862 | if (mips_opts.micromips) |
12863 | micromips_label_expr (&label_expr); | |
12864 | else | |
12865 | label_expr.X_add_number = 8; | |
c0ebe874 | 12866 | macro_build (&label_expr, "beq", "s,t,p", op[0], AT); |
a605d2b3 | 12867 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
12868 | macro_build (NULL, "break", BRK_FMT, 6); |
12869 | if (mips_opts.micromips) | |
12870 | micromips_add_label (); | |
252b5132 | 12871 | } |
7d10b47d | 12872 | end_noreorder (); |
c0ebe874 | 12873 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); |
252b5132 RH |
12874 | break; |
12875 | ||
12876 | case M_DMULOU_I: | |
12877 | dbl = 1; | |
1a0670f3 | 12878 | /* Fall through. */ |
252b5132 RH |
12879 | case M_MULOU_I: |
12880 | imm = 1; | |
12881 | goto do_mulou; | |
12882 | ||
12883 | case M_DMULOU: | |
12884 | dbl = 1; | |
1a0670f3 | 12885 | /* Fall through. */ |
252b5132 RH |
12886 | case M_MULOU: |
12887 | do_mulou: | |
7d10b47d | 12888 | start_noreorder (); |
8fc2e39e | 12889 | used_at = 1; |
252b5132 | 12890 | if (imm) |
67c0d1eb RS |
12891 | load_register (AT, &imm_expr, dbl); |
12892 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
c0ebe874 | 12893 | op[1], imm ? AT : op[2]); |
df58fc94 | 12894 | macro_build (NULL, "mfhi", MFHL_FMT, AT); |
c0ebe874 | 12895 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); |
252b5132 | 12896 | if (mips_trap) |
df58fc94 | 12897 | macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6); |
252b5132 RH |
12898 | else |
12899 | { | |
df58fc94 RS |
12900 | if (mips_opts.micromips) |
12901 | micromips_label_expr (&label_expr); | |
12902 | else | |
12903 | label_expr.X_add_number = 8; | |
12904 | macro_build (&label_expr, "beq", "s,t,p", AT, ZERO); | |
a605d2b3 | 12905 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
12906 | macro_build (NULL, "break", BRK_FMT, 6); |
12907 | if (mips_opts.micromips) | |
12908 | micromips_add_label (); | |
252b5132 | 12909 | } |
7d10b47d | 12910 | end_noreorder (); |
252b5132 RH |
12911 | break; |
12912 | ||
771c7ce4 | 12913 | case M_DROL: |
fef14a42 | 12914 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 12915 | { |
c0ebe874 | 12916 | if (op[0] == op[1]) |
82dd0097 CD |
12917 | { |
12918 | tempreg = AT; | |
12919 | used_at = 1; | |
12920 | } | |
12921 | else | |
c0ebe874 RS |
12922 | tempreg = op[0]; |
12923 | macro_build (NULL, "dnegu", "d,w", tempreg, op[2]); | |
12924 | macro_build (NULL, "drorv", "d,t,s", op[0], op[1], tempreg); | |
8fc2e39e | 12925 | break; |
82dd0097 | 12926 | } |
8fc2e39e | 12927 | used_at = 1; |
c0ebe874 RS |
12928 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]); |
12929 | macro_build (NULL, "dsrlv", "d,t,s", AT, op[1], AT); | |
12930 | macro_build (NULL, "dsllv", "d,t,s", op[0], op[1], op[2]); | |
12931 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 TS |
12932 | break; |
12933 | ||
252b5132 | 12934 | case M_ROL: |
fef14a42 | 12935 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 12936 | { |
c0ebe874 | 12937 | if (op[0] == op[1]) |
82dd0097 CD |
12938 | { |
12939 | tempreg = AT; | |
12940 | used_at = 1; | |
12941 | } | |
12942 | else | |
c0ebe874 RS |
12943 | tempreg = op[0]; |
12944 | macro_build (NULL, "negu", "d,w", tempreg, op[2]); | |
12945 | macro_build (NULL, "rorv", "d,t,s", op[0], op[1], tempreg); | |
8fc2e39e | 12946 | break; |
82dd0097 | 12947 | } |
8fc2e39e | 12948 | used_at = 1; |
c0ebe874 RS |
12949 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]); |
12950 | macro_build (NULL, "srlv", "d,t,s", AT, op[1], AT); | |
12951 | macro_build (NULL, "sllv", "d,t,s", op[0], op[1], op[2]); | |
12952 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
252b5132 RH |
12953 | break; |
12954 | ||
771c7ce4 TS |
12955 | case M_DROL_I: |
12956 | { | |
12957 | unsigned int rot; | |
e0471c16 TS |
12958 | const char *l; |
12959 | const char *rr; | |
771c7ce4 | 12960 | |
771c7ce4 | 12961 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 12962 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
12963 | { |
12964 | rot = (64 - rot) & 0x3f; | |
12965 | if (rot >= 32) | |
c0ebe874 | 12966 | macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32); |
60b63b72 | 12967 | else |
c0ebe874 | 12968 | macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot); |
8fc2e39e | 12969 | break; |
60b63b72 | 12970 | } |
483fc7cd | 12971 | if (rot == 0) |
483fc7cd | 12972 | { |
c0ebe874 | 12973 | macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0); |
8fc2e39e | 12974 | break; |
483fc7cd | 12975 | } |
82dd0097 | 12976 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
91d6fa6a | 12977 | rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 | 12978 | rot &= 0x1f; |
8fc2e39e | 12979 | used_at = 1; |
c0ebe874 RS |
12980 | macro_build (NULL, l, SHFT_FMT, AT, op[1], rot); |
12981 | macro_build (NULL, rr, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); | |
12982 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 TS |
12983 | } |
12984 | break; | |
12985 | ||
252b5132 | 12986 | case M_ROL_I: |
771c7ce4 TS |
12987 | { |
12988 | unsigned int rot; | |
12989 | ||
771c7ce4 | 12990 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 12991 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 12992 | { |
c0ebe874 RS |
12993 | macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], |
12994 | (32 - rot) & 0x1f); | |
8fc2e39e | 12995 | break; |
60b63b72 | 12996 | } |
483fc7cd | 12997 | if (rot == 0) |
483fc7cd | 12998 | { |
c0ebe874 | 12999 | macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0); |
8fc2e39e | 13000 | break; |
483fc7cd | 13001 | } |
8fc2e39e | 13002 | used_at = 1; |
c0ebe874 RS |
13003 | macro_build (NULL, "sll", SHFT_FMT, AT, op[1], rot); |
13004 | macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); | |
13005 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 TS |
13006 | } |
13007 | break; | |
13008 | ||
13009 | case M_DROR: | |
fef14a42 | 13010 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 13011 | { |
c0ebe874 | 13012 | macro_build (NULL, "drorv", "d,t,s", op[0], op[1], op[2]); |
8fc2e39e | 13013 | break; |
82dd0097 | 13014 | } |
8fc2e39e | 13015 | used_at = 1; |
c0ebe874 RS |
13016 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]); |
13017 | macro_build (NULL, "dsllv", "d,t,s", AT, op[1], AT); | |
13018 | macro_build (NULL, "dsrlv", "d,t,s", op[0], op[1], op[2]); | |
13019 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
252b5132 RH |
13020 | break; |
13021 | ||
13022 | case M_ROR: | |
fef14a42 | 13023 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 13024 | { |
c0ebe874 | 13025 | macro_build (NULL, "rorv", "d,t,s", op[0], op[1], op[2]); |
8fc2e39e | 13026 | break; |
82dd0097 | 13027 | } |
8fc2e39e | 13028 | used_at = 1; |
c0ebe874 RS |
13029 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]); |
13030 | macro_build (NULL, "sllv", "d,t,s", AT, op[1], AT); | |
13031 | macro_build (NULL, "srlv", "d,t,s", op[0], op[1], op[2]); | |
13032 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
252b5132 RH |
13033 | break; |
13034 | ||
771c7ce4 TS |
13035 | case M_DROR_I: |
13036 | { | |
13037 | unsigned int rot; | |
e0471c16 TS |
13038 | const char *l; |
13039 | const char *rr; | |
771c7ce4 | 13040 | |
771c7ce4 | 13041 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 13042 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
13043 | { |
13044 | if (rot >= 32) | |
c0ebe874 | 13045 | macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32); |
82dd0097 | 13046 | else |
c0ebe874 | 13047 | macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot); |
8fc2e39e | 13048 | break; |
82dd0097 | 13049 | } |
483fc7cd | 13050 | if (rot == 0) |
483fc7cd | 13051 | { |
c0ebe874 | 13052 | macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0); |
8fc2e39e | 13053 | break; |
483fc7cd | 13054 | } |
91d6fa6a | 13055 | rr = (rot < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 CD |
13056 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; |
13057 | rot &= 0x1f; | |
8fc2e39e | 13058 | used_at = 1; |
c0ebe874 RS |
13059 | macro_build (NULL, rr, SHFT_FMT, AT, op[1], rot); |
13060 | macro_build (NULL, l, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); | |
13061 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 TS |
13062 | } |
13063 | break; | |
13064 | ||
252b5132 | 13065 | case M_ROR_I: |
771c7ce4 TS |
13066 | { |
13067 | unsigned int rot; | |
13068 | ||
771c7ce4 | 13069 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 13070 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 13071 | { |
c0ebe874 | 13072 | macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], rot); |
8fc2e39e | 13073 | break; |
82dd0097 | 13074 | } |
483fc7cd | 13075 | if (rot == 0) |
483fc7cd | 13076 | { |
c0ebe874 | 13077 | macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0); |
8fc2e39e | 13078 | break; |
483fc7cd | 13079 | } |
8fc2e39e | 13080 | used_at = 1; |
c0ebe874 RS |
13081 | macro_build (NULL, "srl", SHFT_FMT, AT, op[1], rot); |
13082 | macro_build (NULL, "sll", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); | |
13083 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 | 13084 | } |
252b5132 RH |
13085 | break; |
13086 | ||
252b5132 | 13087 | case M_SEQ: |
c0ebe874 RS |
13088 | if (op[1] == 0) |
13089 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[2], BFD_RELOC_LO16); | |
13090 | else if (op[2] == 0) | |
13091 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16); | |
252b5132 RH |
13092 | else |
13093 | { | |
c0ebe874 RS |
13094 | macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]); |
13095 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16); | |
252b5132 | 13096 | } |
8fc2e39e | 13097 | break; |
252b5132 RH |
13098 | |
13099 | case M_SEQ_I: | |
b0e6f033 | 13100 | if (imm_expr.X_add_number == 0) |
252b5132 | 13101 | { |
c0ebe874 | 13102 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
8fc2e39e | 13103 | break; |
252b5132 | 13104 | } |
c0ebe874 | 13105 | if (op[1] == 0) |
252b5132 | 13106 | { |
1661c76c | 13107 | as_warn (_("instruction %s: result is always false"), |
252b5132 | 13108 | ip->insn_mo->name); |
c0ebe874 | 13109 | move_register (op[0], 0); |
8fc2e39e | 13110 | break; |
252b5132 | 13111 | } |
dd3cbb7e NC |
13112 | if (CPU_HAS_SEQ (mips_opts.arch) |
13113 | && -512 <= imm_expr.X_add_number | |
13114 | && imm_expr.X_add_number < 512) | |
13115 | { | |
c0ebe874 | 13116 | macro_build (NULL, "seqi", "t,r,+Q", op[0], op[1], |
750bdd57 | 13117 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
13118 | break; |
13119 | } | |
b0e6f033 | 13120 | if (imm_expr.X_add_number >= 0 |
252b5132 | 13121 | && imm_expr.X_add_number < 0x10000) |
c0ebe874 | 13122 | macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1], BFD_RELOC_LO16); |
b0e6f033 | 13123 | else if (imm_expr.X_add_number > -0x8000 |
252b5132 RH |
13124 | && imm_expr.X_add_number < 0) |
13125 | { | |
13126 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
bad1aba3 | 13127 | macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu", |
c0ebe874 | 13128 | "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
252b5132 | 13129 | } |
dd3cbb7e NC |
13130 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
13131 | { | |
13132 | used_at = 1; | |
bad1aba3 | 13133 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13134 | macro_build (NULL, "seq", "d,v,t", op[0], op[1], AT); |
dd3cbb7e NC |
13135 | break; |
13136 | } | |
252b5132 RH |
13137 | else |
13138 | { | |
bad1aba3 | 13139 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13140 | macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT); |
252b5132 RH |
13141 | used_at = 1; |
13142 | } | |
c0ebe874 | 13143 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16); |
8fc2e39e | 13144 | break; |
252b5132 | 13145 | |
c0ebe874 | 13146 | case M_SGE: /* X >= Y <==> not (X < Y) */ |
252b5132 RH |
13147 | s = "slt"; |
13148 | goto sge; | |
13149 | case M_SGEU: | |
13150 | s = "sltu"; | |
13151 | sge: | |
c0ebe874 RS |
13152 | macro_build (NULL, s, "d,v,t", op[0], op[1], op[2]); |
13153 | macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); | |
8fc2e39e | 13154 | break; |
252b5132 | 13155 | |
c0ebe874 | 13156 | case M_SGE_I: /* X >= I <==> not (X < I) */ |
252b5132 | 13157 | case M_SGEU_I: |
b0e6f033 | 13158 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 | 13159 | && imm_expr.X_add_number < 0x8000) |
c0ebe874 RS |
13160 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
13161 | op[0], op[1], BFD_RELOC_LO16); | |
252b5132 RH |
13162 | else |
13163 | { | |
bad1aba3 | 13164 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
67c0d1eb | 13165 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", |
c0ebe874 | 13166 | op[0], op[1], AT); |
252b5132 RH |
13167 | used_at = 1; |
13168 | } | |
c0ebe874 | 13169 | macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); |
8fc2e39e | 13170 | break; |
252b5132 | 13171 | |
c0ebe874 | 13172 | case M_SGT: /* X > Y <==> Y < X */ |
252b5132 RH |
13173 | s = "slt"; |
13174 | goto sgt; | |
13175 | case M_SGTU: | |
13176 | s = "sltu"; | |
13177 | sgt: | |
c0ebe874 | 13178 | macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]); |
8fc2e39e | 13179 | break; |
252b5132 | 13180 | |
c0ebe874 | 13181 | case M_SGT_I: /* X > I <==> I < X */ |
252b5132 RH |
13182 | s = "slt"; |
13183 | goto sgti; | |
13184 | case M_SGTU_I: | |
13185 | s = "sltu"; | |
13186 | sgti: | |
8fc2e39e | 13187 | used_at = 1; |
bad1aba3 | 13188 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13189 | macro_build (NULL, s, "d,v,t", op[0], AT, op[1]); |
252b5132 RH |
13190 | break; |
13191 | ||
c0ebe874 | 13192 | case M_SLE: /* X <= Y <==> Y >= X <==> not (Y < X) */ |
252b5132 RH |
13193 | s = "slt"; |
13194 | goto sle; | |
13195 | case M_SLEU: | |
13196 | s = "sltu"; | |
13197 | sle: | |
c0ebe874 RS |
13198 | macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]); |
13199 | macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); | |
8fc2e39e | 13200 | break; |
252b5132 | 13201 | |
c0ebe874 | 13202 | case M_SLE_I: /* X <= I <==> I >= X <==> not (I < X) */ |
252b5132 RH |
13203 | s = "slt"; |
13204 | goto slei; | |
13205 | case M_SLEU_I: | |
13206 | s = "sltu"; | |
13207 | slei: | |
8fc2e39e | 13208 | used_at = 1; |
bad1aba3 | 13209 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 RS |
13210 | macro_build (NULL, s, "d,v,t", op[0], AT, op[1]); |
13211 | macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); | |
252b5132 RH |
13212 | break; |
13213 | ||
13214 | case M_SLT_I: | |
b0e6f033 | 13215 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 RH |
13216 | && imm_expr.X_add_number < 0x8000) |
13217 | { | |
c0ebe874 RS |
13218 | macro_build (&imm_expr, "slti", "t,r,j", op[0], op[1], |
13219 | BFD_RELOC_LO16); | |
8fc2e39e | 13220 | break; |
252b5132 | 13221 | } |
8fc2e39e | 13222 | used_at = 1; |
bad1aba3 | 13223 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13224 | macro_build (NULL, "slt", "d,v,t", op[0], op[1], AT); |
252b5132 RH |
13225 | break; |
13226 | ||
13227 | case M_SLTU_I: | |
b0e6f033 | 13228 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 RH |
13229 | && imm_expr.X_add_number < 0x8000) |
13230 | { | |
c0ebe874 | 13231 | macro_build (&imm_expr, "sltiu", "t,r,j", op[0], op[1], |
17a2f251 | 13232 | BFD_RELOC_LO16); |
8fc2e39e | 13233 | break; |
252b5132 | 13234 | } |
8fc2e39e | 13235 | used_at = 1; |
bad1aba3 | 13236 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13237 | macro_build (NULL, "sltu", "d,v,t", op[0], op[1], AT); |
252b5132 RH |
13238 | break; |
13239 | ||
13240 | case M_SNE: | |
c0ebe874 RS |
13241 | if (op[1] == 0) |
13242 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[2]); | |
13243 | else if (op[2] == 0) | |
13244 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]); | |
252b5132 RH |
13245 | else |
13246 | { | |
c0ebe874 RS |
13247 | macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]); |
13248 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]); | |
252b5132 | 13249 | } |
8fc2e39e | 13250 | break; |
252b5132 RH |
13251 | |
13252 | case M_SNE_I: | |
b0e6f033 | 13253 | if (imm_expr.X_add_number == 0) |
252b5132 | 13254 | { |
c0ebe874 | 13255 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]); |
8fc2e39e | 13256 | break; |
252b5132 | 13257 | } |
c0ebe874 | 13258 | if (op[1] == 0) |
252b5132 | 13259 | { |
1661c76c | 13260 | as_warn (_("instruction %s: result is always true"), |
252b5132 | 13261 | ip->insn_mo->name); |
bad1aba3 | 13262 | macro_build (&expr1, GPR_SIZE == 32 ? "addiu" : "daddiu", "t,r,j", |
c0ebe874 | 13263 | op[0], 0, BFD_RELOC_LO16); |
8fc2e39e | 13264 | break; |
252b5132 | 13265 | } |
dd3cbb7e NC |
13266 | if (CPU_HAS_SEQ (mips_opts.arch) |
13267 | && -512 <= imm_expr.X_add_number | |
13268 | && imm_expr.X_add_number < 512) | |
13269 | { | |
c0ebe874 | 13270 | macro_build (NULL, "snei", "t,r,+Q", op[0], op[1], |
750bdd57 | 13271 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
13272 | break; |
13273 | } | |
b0e6f033 | 13274 | if (imm_expr.X_add_number >= 0 |
252b5132 RH |
13275 | && imm_expr.X_add_number < 0x10000) |
13276 | { | |
c0ebe874 RS |
13277 | macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1], |
13278 | BFD_RELOC_LO16); | |
252b5132 | 13279 | } |
b0e6f033 | 13280 | else if (imm_expr.X_add_number > -0x8000 |
252b5132 RH |
13281 | && imm_expr.X_add_number < 0) |
13282 | { | |
13283 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
bad1aba3 | 13284 | macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu", |
c0ebe874 | 13285 | "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
252b5132 | 13286 | } |
dd3cbb7e NC |
13287 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
13288 | { | |
13289 | used_at = 1; | |
bad1aba3 | 13290 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13291 | macro_build (NULL, "sne", "d,v,t", op[0], op[1], AT); |
dd3cbb7e NC |
13292 | break; |
13293 | } | |
252b5132 RH |
13294 | else |
13295 | { | |
bad1aba3 | 13296 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13297 | macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT); |
252b5132 RH |
13298 | used_at = 1; |
13299 | } | |
c0ebe874 | 13300 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]); |
8fc2e39e | 13301 | break; |
252b5132 | 13302 | |
df58fc94 RS |
13303 | case M_SUB_I: |
13304 | s = "addi"; | |
13305 | s2 = "sub"; | |
13306 | goto do_subi; | |
13307 | case M_SUBU_I: | |
13308 | s = "addiu"; | |
13309 | s2 = "subu"; | |
13310 | goto do_subi; | |
252b5132 RH |
13311 | case M_DSUB_I: |
13312 | dbl = 1; | |
df58fc94 RS |
13313 | s = "daddi"; |
13314 | s2 = "dsub"; | |
13315 | if (!mips_opts.micromips) | |
13316 | goto do_subi; | |
b0e6f033 | 13317 | if (imm_expr.X_add_number > -0x200 |
df58fc94 | 13318 | && imm_expr.X_add_number <= 0x200) |
252b5132 | 13319 | { |
b0e6f033 RS |
13320 | macro_build (NULL, s, "t,r,.", op[0], op[1], |
13321 | (int) -imm_expr.X_add_number); | |
8fc2e39e | 13322 | break; |
252b5132 | 13323 | } |
df58fc94 | 13324 | goto do_subi_i; |
252b5132 RH |
13325 | case M_DSUBU_I: |
13326 | dbl = 1; | |
df58fc94 RS |
13327 | s = "daddiu"; |
13328 | s2 = "dsubu"; | |
13329 | do_subi: | |
b0e6f033 | 13330 | if (imm_expr.X_add_number > -0x8000 |
252b5132 RH |
13331 | && imm_expr.X_add_number <= 0x8000) |
13332 | { | |
13333 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
c0ebe874 | 13334 | macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
8fc2e39e | 13335 | break; |
252b5132 | 13336 | } |
df58fc94 | 13337 | do_subi_i: |
8fc2e39e | 13338 | used_at = 1; |
67c0d1eb | 13339 | load_register (AT, &imm_expr, dbl); |
c0ebe874 | 13340 | macro_build (NULL, s2, "d,v,t", op[0], op[1], AT); |
252b5132 RH |
13341 | break; |
13342 | ||
13343 | case M_TEQ_I: | |
13344 | s = "teq"; | |
13345 | goto trap; | |
13346 | case M_TGE_I: | |
13347 | s = "tge"; | |
13348 | goto trap; | |
13349 | case M_TGEU_I: | |
13350 | s = "tgeu"; | |
13351 | goto trap; | |
13352 | case M_TLT_I: | |
13353 | s = "tlt"; | |
13354 | goto trap; | |
13355 | case M_TLTU_I: | |
13356 | s = "tltu"; | |
13357 | goto trap; | |
13358 | case M_TNE_I: | |
13359 | s = "tne"; | |
13360 | trap: | |
8fc2e39e | 13361 | used_at = 1; |
bad1aba3 | 13362 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13363 | macro_build (NULL, s, "s,t", op[0], AT); |
252b5132 RH |
13364 | break; |
13365 | ||
252b5132 | 13366 | case M_TRUNCWS: |
43841e91 | 13367 | case M_TRUNCWD: |
df58fc94 | 13368 | gas_assert (!mips_opts.micromips); |
0aa27725 | 13369 | gas_assert (mips_opts.isa == ISA_MIPS1); |
8fc2e39e | 13370 | used_at = 1; |
252b5132 RH |
13371 | |
13372 | /* | |
13373 | * Is the double cfc1 instruction a bug in the mips assembler; | |
13374 | * or is there a reason for it? | |
13375 | */ | |
7d10b47d | 13376 | start_noreorder (); |
c0ebe874 RS |
13377 | macro_build (NULL, "cfc1", "t,G", op[2], RA); |
13378 | macro_build (NULL, "cfc1", "t,G", op[2], RA); | |
67c0d1eb | 13379 | macro_build (NULL, "nop", ""); |
252b5132 | 13380 | expr1.X_add_number = 3; |
c0ebe874 | 13381 | macro_build (&expr1, "ori", "t,r,i", AT, op[2], BFD_RELOC_LO16); |
252b5132 | 13382 | expr1.X_add_number = 2; |
67c0d1eb RS |
13383 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
13384 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
13385 | macro_build (NULL, "nop", ""); | |
13386 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
c0ebe874 RS |
13387 | op[0], op[1]); |
13388 | macro_build (NULL, "ctc1", "t,G", op[2], RA); | |
67c0d1eb | 13389 | macro_build (NULL, "nop", ""); |
7d10b47d | 13390 | end_noreorder (); |
252b5132 RH |
13391 | break; |
13392 | ||
f2ae14a1 | 13393 | case M_ULH_AB: |
252b5132 | 13394 | s = "lb"; |
df58fc94 RS |
13395 | s2 = "lbu"; |
13396 | off = 1; | |
13397 | goto uld_st; | |
f2ae14a1 | 13398 | case M_ULHU_AB: |
252b5132 | 13399 | s = "lbu"; |
df58fc94 RS |
13400 | s2 = "lbu"; |
13401 | off = 1; | |
13402 | goto uld_st; | |
f2ae14a1 | 13403 | case M_ULW_AB: |
df58fc94 RS |
13404 | s = "lwl"; |
13405 | s2 = "lwr"; | |
7f3c4072 | 13406 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
13407 | off = 3; |
13408 | goto uld_st; | |
f2ae14a1 | 13409 | case M_ULD_AB: |
252b5132 RH |
13410 | s = "ldl"; |
13411 | s2 = "ldr"; | |
7f3c4072 | 13412 | offbits = (mips_opts.micromips ? 12 : 16); |
252b5132 | 13413 | off = 7; |
df58fc94 | 13414 | goto uld_st; |
f2ae14a1 | 13415 | case M_USH_AB: |
df58fc94 RS |
13416 | s = "sb"; |
13417 | s2 = "sb"; | |
13418 | off = 1; | |
13419 | ust = 1; | |
13420 | goto uld_st; | |
f2ae14a1 | 13421 | case M_USW_AB: |
df58fc94 RS |
13422 | s = "swl"; |
13423 | s2 = "swr"; | |
7f3c4072 | 13424 | offbits = (mips_opts.micromips ? 12 : 16); |
252b5132 | 13425 | off = 3; |
df58fc94 RS |
13426 | ust = 1; |
13427 | goto uld_st; | |
f2ae14a1 | 13428 | case M_USD_AB: |
df58fc94 RS |
13429 | s = "sdl"; |
13430 | s2 = "sdr"; | |
7f3c4072 | 13431 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
13432 | off = 7; |
13433 | ust = 1; | |
13434 | ||
13435 | uld_st: | |
c0ebe874 | 13436 | breg = op[2]; |
f2ae14a1 | 13437 | large_offset = !small_offset_p (off, align, offbits); |
df58fc94 RS |
13438 | ep = &offset_expr; |
13439 | expr1.X_add_number = 0; | |
f2ae14a1 | 13440 | if (large_offset) |
df58fc94 RS |
13441 | { |
13442 | used_at = 1; | |
13443 | tempreg = AT; | |
f2ae14a1 RS |
13444 | if (small_offset_p (0, align, 16)) |
13445 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, -1, | |
13446 | offset_reloc[0], offset_reloc[1], offset_reloc[2]); | |
13447 | else | |
13448 | { | |
13449 | load_address (tempreg, ep, &used_at); | |
13450 | if (breg != 0) | |
13451 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
13452 | tempreg, tempreg, breg); | |
13453 | } | |
13454 | offset_reloc[0] = BFD_RELOC_LO16; | |
13455 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
13456 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
df58fc94 | 13457 | breg = tempreg; |
c0ebe874 | 13458 | tempreg = op[0]; |
df58fc94 RS |
13459 | ep = &expr1; |
13460 | } | |
c0ebe874 | 13461 | else if (!ust && op[0] == breg) |
8fc2e39e TS |
13462 | { |
13463 | used_at = 1; | |
13464 | tempreg = AT; | |
13465 | } | |
252b5132 | 13466 | else |
c0ebe874 | 13467 | tempreg = op[0]; |
af22f5b2 | 13468 | |
df58fc94 RS |
13469 | if (off == 1) |
13470 | goto ulh_sh; | |
252b5132 | 13471 | |
90ecf173 | 13472 | if (!target_big_endian) |
df58fc94 | 13473 | ep->X_add_number += off; |
f2ae14a1 | 13474 | if (offbits == 12) |
c8276761 | 13475 | macro_build (NULL, s, "t,~(b)", tempreg, (int) ep->X_add_number, breg); |
f2ae14a1 RS |
13476 | else |
13477 | macro_build (ep, s, "t,o(b)", tempreg, -1, | |
13478 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); | |
df58fc94 | 13479 | |
90ecf173 | 13480 | if (!target_big_endian) |
df58fc94 | 13481 | ep->X_add_number -= off; |
252b5132 | 13482 | else |
df58fc94 | 13483 | ep->X_add_number += off; |
f2ae14a1 | 13484 | if (offbits == 12) |
df58fc94 | 13485 | macro_build (NULL, s2, "t,~(b)", |
c8276761 | 13486 | tempreg, (int) ep->X_add_number, breg); |
f2ae14a1 RS |
13487 | else |
13488 | macro_build (ep, s2, "t,o(b)", tempreg, -1, | |
13489 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); | |
252b5132 | 13490 | |
df58fc94 | 13491 | /* If necessary, move the result in tempreg to the final destination. */ |
c0ebe874 | 13492 | if (!ust && op[0] != tempreg) |
df58fc94 RS |
13493 | { |
13494 | /* Protect second load's delay slot. */ | |
13495 | load_delay_nop (); | |
c0ebe874 | 13496 | move_register (op[0], tempreg); |
df58fc94 | 13497 | } |
8fc2e39e | 13498 | break; |
252b5132 | 13499 | |
df58fc94 | 13500 | ulh_sh: |
d6bc6245 | 13501 | used_at = 1; |
df58fc94 RS |
13502 | if (target_big_endian == ust) |
13503 | ep->X_add_number += off; | |
c0ebe874 | 13504 | tempreg = ust || large_offset ? op[0] : AT; |
f2ae14a1 RS |
13505 | macro_build (ep, s, "t,o(b)", tempreg, -1, |
13506 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); | |
df58fc94 RS |
13507 | |
13508 | /* For halfword transfers we need a temporary register to shuffle | |
13509 | bytes. Unfortunately for M_USH_A we have none available before | |
13510 | the next store as AT holds the base address. We deal with this | |
13511 | case by clobbering TREG and then restoring it as with ULH. */ | |
c0ebe874 | 13512 | tempreg = ust == large_offset ? op[0] : AT; |
df58fc94 | 13513 | if (ust) |
c0ebe874 | 13514 | macro_build (NULL, "srl", SHFT_FMT, tempreg, op[0], 8); |
df58fc94 RS |
13515 | |
13516 | if (target_big_endian == ust) | |
13517 | ep->X_add_number -= off; | |
252b5132 | 13518 | else |
df58fc94 | 13519 | ep->X_add_number += off; |
f2ae14a1 RS |
13520 | macro_build (ep, s2, "t,o(b)", tempreg, -1, |
13521 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); | |
252b5132 | 13522 | |
df58fc94 | 13523 | /* For M_USH_A re-retrieve the LSB. */ |
f2ae14a1 | 13524 | if (ust && large_offset) |
df58fc94 RS |
13525 | { |
13526 | if (target_big_endian) | |
13527 | ep->X_add_number += off; | |
13528 | else | |
13529 | ep->X_add_number -= off; | |
f2ae14a1 RS |
13530 | macro_build (&expr1, "lbu", "t,o(b)", AT, -1, |
13531 | offset_reloc[0], offset_reloc[1], offset_reloc[2], AT); | |
df58fc94 RS |
13532 | } |
13533 | /* For ULH and M_USH_A OR the LSB in. */ | |
f2ae14a1 | 13534 | if (!ust || large_offset) |
df58fc94 | 13535 | { |
c0ebe874 | 13536 | tempreg = !large_offset ? AT : op[0]; |
df58fc94 | 13537 | macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8); |
c0ebe874 | 13538 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); |
df58fc94 | 13539 | } |
252b5132 RH |
13540 | break; |
13541 | ||
13542 | default: | |
13543 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 13544 | are added dynamically. */ |
1661c76c | 13545 | as_bad (_("macro %s not implemented yet"), ip->insn_mo->name); |
252b5132 RH |
13546 | break; |
13547 | } | |
741fe287 | 13548 | if (!mips_opts.at && used_at) |
1661c76c | 13549 | as_bad (_("macro used $at after \".set noat\"")); |
252b5132 RH |
13550 | } |
13551 | ||
13552 | /* Implement macros in mips16 mode. */ | |
13553 | ||
13554 | static void | |
17a2f251 | 13555 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 | 13556 | { |
c0ebe874 | 13557 | const struct mips_operand_array *operands; |
252b5132 | 13558 | int mask; |
c0ebe874 | 13559 | int tmp; |
252b5132 RH |
13560 | expressionS expr1; |
13561 | int dbl; | |
13562 | const char *s, *s2, *s3; | |
c0ebe874 RS |
13563 | unsigned int op[MAX_OPERANDS]; |
13564 | unsigned int i; | |
252b5132 RH |
13565 | |
13566 | mask = ip->insn_mo->mask; | |
13567 | ||
c0ebe874 RS |
13568 | operands = insn_operands (ip); |
13569 | for (i = 0; i < MAX_OPERANDS; i++) | |
13570 | if (operands->operand[i]) | |
13571 | op[i] = insn_extract_operand (ip, operands->operand[i]); | |
13572 | else | |
13573 | op[i] = -1; | |
252b5132 | 13574 | |
252b5132 RH |
13575 | expr1.X_op = O_constant; |
13576 | expr1.X_op_symbol = NULL; | |
13577 | expr1.X_add_symbol = NULL; | |
13578 | expr1.X_add_number = 1; | |
13579 | ||
13580 | dbl = 0; | |
13581 | ||
13582 | switch (mask) | |
13583 | { | |
13584 | default: | |
b37df7c4 | 13585 | abort (); |
252b5132 RH |
13586 | |
13587 | case M_DDIV_3: | |
13588 | dbl = 1; | |
1a0670f3 | 13589 | /* Fall through. */ |
252b5132 RH |
13590 | case M_DIV_3: |
13591 | s = "mflo"; | |
13592 | goto do_div3; | |
13593 | case M_DREM_3: | |
13594 | dbl = 1; | |
1a0670f3 | 13595 | /* Fall through. */ |
252b5132 RH |
13596 | case M_REM_3: |
13597 | s = "mfhi"; | |
13598 | do_div3: | |
7d10b47d | 13599 | start_noreorder (); |
d8722d76 | 13600 | macro_build (NULL, dbl ? "ddiv" : "div", ".,x,y", op[1], op[2]); |
252b5132 | 13601 | expr1.X_add_number = 2; |
c0ebe874 | 13602 | macro_build (&expr1, "bnez", "x,p", op[2]); |
67c0d1eb | 13603 | macro_build (NULL, "break", "6", 7); |
bdaaa2e1 | 13604 | |
252b5132 RH |
13605 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
13606 | since that causes an overflow. We should do that as well, | |
13607 | but I don't see how to do the comparisons without a temporary | |
13608 | register. */ | |
7d10b47d | 13609 | end_noreorder (); |
c0ebe874 | 13610 | macro_build (NULL, s, "x", op[0]); |
252b5132 RH |
13611 | break; |
13612 | ||
13613 | case M_DIVU_3: | |
13614 | s = "divu"; | |
13615 | s2 = "mflo"; | |
13616 | goto do_divu3; | |
13617 | case M_REMU_3: | |
13618 | s = "divu"; | |
13619 | s2 = "mfhi"; | |
13620 | goto do_divu3; | |
13621 | case M_DDIVU_3: | |
13622 | s = "ddivu"; | |
13623 | s2 = "mflo"; | |
13624 | goto do_divu3; | |
13625 | case M_DREMU_3: | |
13626 | s = "ddivu"; | |
13627 | s2 = "mfhi"; | |
13628 | do_divu3: | |
7d10b47d | 13629 | start_noreorder (); |
d8722d76 | 13630 | macro_build (NULL, s, ".,x,y", op[1], op[2]); |
252b5132 | 13631 | expr1.X_add_number = 2; |
c0ebe874 | 13632 | macro_build (&expr1, "bnez", "x,p", op[2]); |
67c0d1eb | 13633 | macro_build (NULL, "break", "6", 7); |
7d10b47d | 13634 | end_noreorder (); |
c0ebe874 | 13635 | macro_build (NULL, s2, "x", op[0]); |
252b5132 RH |
13636 | break; |
13637 | ||
13638 | case M_DMUL: | |
13639 | dbl = 1; | |
1a0670f3 | 13640 | /* Fall through. */ |
252b5132 | 13641 | case M_MUL: |
c0ebe874 RS |
13642 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", op[1], op[2]); |
13643 | macro_build (NULL, "mflo", "x", op[0]); | |
8fc2e39e | 13644 | break; |
252b5132 RH |
13645 | |
13646 | case M_DSUBU_I: | |
13647 | dbl = 1; | |
13648 | goto do_subu; | |
13649 | case M_SUBU_I: | |
13650 | do_subu: | |
252b5132 | 13651 | imm_expr.X_add_number = -imm_expr.X_add_number; |
d8722d76 | 13652 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,F", op[0], op[1]); |
252b5132 RH |
13653 | break; |
13654 | ||
13655 | case M_SUBU_I_2: | |
252b5132 | 13656 | imm_expr.X_add_number = -imm_expr.X_add_number; |
c0ebe874 | 13657 | macro_build (&imm_expr, "addiu", "x,k", op[0]); |
252b5132 RH |
13658 | break; |
13659 | ||
13660 | case M_DSUBU_I_2: | |
252b5132 | 13661 | imm_expr.X_add_number = -imm_expr.X_add_number; |
c0ebe874 | 13662 | macro_build (&imm_expr, "daddiu", "y,j", op[0]); |
252b5132 RH |
13663 | break; |
13664 | ||
13665 | case M_BEQ: | |
13666 | s = "cmp"; | |
13667 | s2 = "bteqz"; | |
13668 | goto do_branch; | |
13669 | case M_BNE: | |
13670 | s = "cmp"; | |
13671 | s2 = "btnez"; | |
13672 | goto do_branch; | |
13673 | case M_BLT: | |
13674 | s = "slt"; | |
13675 | s2 = "btnez"; | |
13676 | goto do_branch; | |
13677 | case M_BLTU: | |
13678 | s = "sltu"; | |
13679 | s2 = "btnez"; | |
13680 | goto do_branch; | |
13681 | case M_BLE: | |
13682 | s = "slt"; | |
13683 | s2 = "bteqz"; | |
13684 | goto do_reverse_branch; | |
13685 | case M_BLEU: | |
13686 | s = "sltu"; | |
13687 | s2 = "bteqz"; | |
13688 | goto do_reverse_branch; | |
13689 | case M_BGE: | |
13690 | s = "slt"; | |
13691 | s2 = "bteqz"; | |
13692 | goto do_branch; | |
13693 | case M_BGEU: | |
13694 | s = "sltu"; | |
13695 | s2 = "bteqz"; | |
13696 | goto do_branch; | |
13697 | case M_BGT: | |
13698 | s = "slt"; | |
13699 | s2 = "btnez"; | |
13700 | goto do_reverse_branch; | |
13701 | case M_BGTU: | |
13702 | s = "sltu"; | |
13703 | s2 = "btnez"; | |
13704 | ||
13705 | do_reverse_branch: | |
c0ebe874 RS |
13706 | tmp = op[1]; |
13707 | op[1] = op[0]; | |
13708 | op[0] = tmp; | |
252b5132 RH |
13709 | |
13710 | do_branch: | |
c0ebe874 | 13711 | macro_build (NULL, s, "x,y", op[0], op[1]); |
67c0d1eb | 13712 | macro_build (&offset_expr, s2, "p"); |
252b5132 RH |
13713 | break; |
13714 | ||
13715 | case M_BEQ_I: | |
13716 | s = "cmpi"; | |
13717 | s2 = "bteqz"; | |
13718 | s3 = "x,U"; | |
13719 | goto do_branch_i; | |
13720 | case M_BNE_I: | |
13721 | s = "cmpi"; | |
13722 | s2 = "btnez"; | |
13723 | s3 = "x,U"; | |
13724 | goto do_branch_i; | |
13725 | case M_BLT_I: | |
13726 | s = "slti"; | |
13727 | s2 = "btnez"; | |
13728 | s3 = "x,8"; | |
13729 | goto do_branch_i; | |
13730 | case M_BLTU_I: | |
13731 | s = "sltiu"; | |
13732 | s2 = "btnez"; | |
13733 | s3 = "x,8"; | |
13734 | goto do_branch_i; | |
13735 | case M_BLE_I: | |
13736 | s = "slti"; | |
13737 | s2 = "btnez"; | |
13738 | s3 = "x,8"; | |
13739 | goto do_addone_branch_i; | |
13740 | case M_BLEU_I: | |
13741 | s = "sltiu"; | |
13742 | s2 = "btnez"; | |
13743 | s3 = "x,8"; | |
13744 | goto do_addone_branch_i; | |
13745 | case M_BGE_I: | |
13746 | s = "slti"; | |
13747 | s2 = "bteqz"; | |
13748 | s3 = "x,8"; | |
13749 | goto do_branch_i; | |
13750 | case M_BGEU_I: | |
13751 | s = "sltiu"; | |
13752 | s2 = "bteqz"; | |
13753 | s3 = "x,8"; | |
13754 | goto do_branch_i; | |
13755 | case M_BGT_I: | |
13756 | s = "slti"; | |
13757 | s2 = "bteqz"; | |
13758 | s3 = "x,8"; | |
13759 | goto do_addone_branch_i; | |
13760 | case M_BGTU_I: | |
13761 | s = "sltiu"; | |
13762 | s2 = "bteqz"; | |
13763 | s3 = "x,8"; | |
13764 | ||
13765 | do_addone_branch_i: | |
252b5132 RH |
13766 | ++imm_expr.X_add_number; |
13767 | ||
13768 | do_branch_i: | |
c0ebe874 | 13769 | macro_build (&imm_expr, s, s3, op[0]); |
67c0d1eb | 13770 | macro_build (&offset_expr, s2, "p"); |
252b5132 RH |
13771 | break; |
13772 | ||
13773 | case M_ABS: | |
13774 | expr1.X_add_number = 0; | |
c0ebe874 RS |
13775 | macro_build (&expr1, "slti", "x,8", op[1]); |
13776 | if (op[0] != op[1]) | |
13777 | macro_build (NULL, "move", "y,X", op[0], mips16_to_32_reg_map[op[1]]); | |
252b5132 | 13778 | expr1.X_add_number = 2; |
67c0d1eb | 13779 | macro_build (&expr1, "bteqz", "p"); |
c0ebe874 | 13780 | macro_build (NULL, "neg", "x,w", op[0], op[0]); |
0acfaea6 | 13781 | break; |
252b5132 RH |
13782 | } |
13783 | } | |
13784 | ||
14daeee3 RS |
13785 | /* Look up instruction [START, START + LENGTH) in HASH. Record any extra |
13786 | opcode bits in *OPCODE_EXTRA. */ | |
13787 | ||
13788 | static struct mips_opcode * | |
13789 | mips_lookup_insn (struct hash_control *hash, const char *start, | |
da8bca91 | 13790 | ssize_t length, unsigned int *opcode_extra) |
14daeee3 RS |
13791 | { |
13792 | char *name, *dot, *p; | |
13793 | unsigned int mask, suffix; | |
da8bca91 | 13794 | ssize_t opend; |
14daeee3 RS |
13795 | struct mips_opcode *insn; |
13796 | ||
13797 | /* Make a copy of the instruction so that we can fiddle with it. */ | |
4ec9d7d5 | 13798 | name = xstrndup (start, length); |
14daeee3 RS |
13799 | |
13800 | /* Look up the instruction as-is. */ | |
13801 | insn = (struct mips_opcode *) hash_find (hash, name); | |
ee5734f0 | 13802 | if (insn) |
e1fa0163 | 13803 | goto end; |
14daeee3 RS |
13804 | |
13805 | dot = strchr (name, '.'); | |
13806 | if (dot && dot[1]) | |
13807 | { | |
13808 | /* Try to interpret the text after the dot as a VU0 channel suffix. */ | |
13809 | p = mips_parse_vu0_channels (dot + 1, &mask); | |
13810 | if (*p == 0 && mask != 0) | |
13811 | { | |
13812 | *dot = 0; | |
13813 | insn = (struct mips_opcode *) hash_find (hash, name); | |
13814 | *dot = '.'; | |
13815 | if (insn && (insn->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0) | |
13816 | { | |
13817 | *opcode_extra |= mask << mips_vu0_channel_mask.lsb; | |
e1fa0163 | 13818 | goto end; |
14daeee3 RS |
13819 | } |
13820 | } | |
13821 | } | |
13822 | ||
13823 | if (mips_opts.micromips) | |
13824 | { | |
13825 | /* See if there's an instruction size override suffix, | |
13826 | either `16' or `32', at the end of the mnemonic proper, | |
13827 | that defines the operation, i.e. before the first `.' | |
13828 | character if any. Strip it and retry. */ | |
13829 | opend = dot != NULL ? dot - name : length; | |
13830 | if (opend >= 3 && name[opend - 2] == '1' && name[opend - 1] == '6') | |
13831 | suffix = 2; | |
13832 | else if (name[opend - 2] == '3' && name[opend - 1] == '2') | |
13833 | suffix = 4; | |
13834 | else | |
13835 | suffix = 0; | |
13836 | if (suffix) | |
13837 | { | |
13838 | memcpy (name + opend - 2, name + opend, length - opend + 1); | |
13839 | insn = (struct mips_opcode *) hash_find (hash, name); | |
ee5734f0 | 13840 | if (insn) |
14daeee3 RS |
13841 | { |
13842 | forced_insn_length = suffix; | |
e1fa0163 | 13843 | goto end; |
14daeee3 RS |
13844 | } |
13845 | } | |
13846 | } | |
13847 | ||
e1fa0163 NC |
13848 | insn = NULL; |
13849 | end: | |
13850 | free (name); | |
13851 | return insn; | |
14daeee3 RS |
13852 | } |
13853 | ||
77bd4346 | 13854 | /* Assemble an instruction into its binary format. If the instruction |
e423441d RS |
13855 | is a macro, set imm_expr and offset_expr to the values associated |
13856 | with "I" and "A" operands respectively. Otherwise store the value | |
13857 | of the relocatable field (if any) in offset_expr. In both cases | |
13858 | set offset_reloc to the relocation operators applied to offset_expr. */ | |
252b5132 RH |
13859 | |
13860 | static void | |
60f20e8b | 13861 | mips_ip (char *str, struct mips_cl_insn *insn) |
252b5132 | 13862 | { |
60f20e8b | 13863 | const struct mips_opcode *first, *past; |
df58fc94 | 13864 | struct hash_control *hash; |
a92713e6 | 13865 | char format; |
14daeee3 | 13866 | size_t end; |
a92713e6 | 13867 | struct mips_operand_token *tokens; |
14daeee3 | 13868 | unsigned int opcode_extra; |
252b5132 | 13869 | |
df58fc94 RS |
13870 | if (mips_opts.micromips) |
13871 | { | |
13872 | hash = micromips_op_hash; | |
13873 | past = µmips_opcodes[bfd_micromips_num_opcodes]; | |
13874 | } | |
13875 | else | |
13876 | { | |
13877 | hash = op_hash; | |
13878 | past = &mips_opcodes[NUMOPCODES]; | |
13879 | } | |
13880 | forced_insn_length = 0; | |
14daeee3 | 13881 | opcode_extra = 0; |
252b5132 | 13882 | |
df58fc94 | 13883 | /* We first try to match an instruction up to a space or to the end. */ |
a40bc9dd RS |
13884 | for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++) |
13885 | continue; | |
bdaaa2e1 | 13886 | |
60f20e8b RS |
13887 | first = mips_lookup_insn (hash, str, end, &opcode_extra); |
13888 | if (first == NULL) | |
252b5132 | 13889 | { |
1661c76c | 13890 | set_insn_error (0, _("unrecognized opcode")); |
a40bc9dd | 13891 | return; |
252b5132 RH |
13892 | } |
13893 | ||
60f20e8b | 13894 | if (strcmp (first->name, "li.s") == 0) |
a92713e6 | 13895 | format = 'f'; |
60f20e8b | 13896 | else if (strcmp (first->name, "li.d") == 0) |
a92713e6 RS |
13897 | format = 'd'; |
13898 | else | |
13899 | format = 0; | |
13900 | tokens = mips_parse_arguments (str + end, format); | |
13901 | if (!tokens) | |
13902 | return; | |
13903 | ||
60f20e8b RS |
13904 | if (!match_insns (insn, first, past, tokens, opcode_extra, FALSE) |
13905 | && !match_insns (insn, first, past, tokens, opcode_extra, TRUE)) | |
1661c76c | 13906 | set_insn_error (0, _("invalid operands")); |
df58fc94 | 13907 | |
e3de51ce | 13908 | obstack_free (&mips_operand_tokens, tokens); |
252b5132 RH |
13909 | } |
13910 | ||
77bd4346 RS |
13911 | /* As for mips_ip, but used when assembling MIPS16 code. |
13912 | Also set forced_insn_length to the resulting instruction size in | |
13913 | bytes if the user explicitly requested a small or extended instruction. */ | |
252b5132 RH |
13914 | |
13915 | static void | |
60f20e8b | 13916 | mips16_ip (char *str, struct mips_cl_insn *insn) |
252b5132 | 13917 | { |
1a00e612 | 13918 | char *end, *s, c; |
60f20e8b | 13919 | struct mips_opcode *first; |
a92713e6 | 13920 | struct mips_operand_token *tokens; |
3fb49709 | 13921 | unsigned int l; |
252b5132 | 13922 | |
3882b010 | 13923 | for (s = str; ISLOWER (*s); ++s) |
252b5132 | 13924 | ; |
1a00e612 RS |
13925 | end = s; |
13926 | c = *end; | |
3fb49709 MR |
13927 | |
13928 | l = 0; | |
1a00e612 | 13929 | switch (c) |
252b5132 RH |
13930 | { |
13931 | case '\0': | |
13932 | break; | |
13933 | ||
13934 | case ' ': | |
1a00e612 | 13935 | s++; |
252b5132 RH |
13936 | break; |
13937 | ||
13938 | case '.': | |
3fb49709 MR |
13939 | s++; |
13940 | if (*s == 't') | |
252b5132 | 13941 | { |
3fb49709 MR |
13942 | l = 2; |
13943 | s++; | |
252b5132 | 13944 | } |
3fb49709 | 13945 | else if (*s == 'e') |
252b5132 | 13946 | { |
3fb49709 MR |
13947 | l = 4; |
13948 | s++; | |
252b5132 | 13949 | } |
3fb49709 MR |
13950 | if (*s == '\0') |
13951 | break; | |
13952 | else if (*s++ == ' ') | |
13953 | break; | |
252b5132 RH |
13954 | /* Fall through. */ |
13955 | default: | |
1661c76c | 13956 | set_insn_error (0, _("unrecognized opcode")); |
252b5132 RH |
13957 | return; |
13958 | } | |
3fb49709 | 13959 | forced_insn_length = l; |
252b5132 | 13960 | |
1a00e612 | 13961 | *end = 0; |
60f20e8b | 13962 | first = (struct mips_opcode *) hash_find (mips16_op_hash, str); |
1a00e612 RS |
13963 | *end = c; |
13964 | ||
60f20e8b | 13965 | if (!first) |
252b5132 | 13966 | { |
1661c76c | 13967 | set_insn_error (0, _("unrecognized opcode")); |
252b5132 RH |
13968 | return; |
13969 | } | |
13970 | ||
a92713e6 RS |
13971 | tokens = mips_parse_arguments (s, 0); |
13972 | if (!tokens) | |
13973 | return; | |
13974 | ||
60f20e8b | 13975 | if (!match_mips16_insns (insn, first, tokens)) |
1661c76c | 13976 | set_insn_error (0, _("invalid operands")); |
252b5132 | 13977 | |
e3de51ce | 13978 | obstack_free (&mips_operand_tokens, tokens); |
252b5132 RH |
13979 | } |
13980 | ||
b886a2ab RS |
13981 | /* Marshal immediate value VAL for an extended MIPS16 instruction. |
13982 | NBITS is the number of significant bits in VAL. */ | |
13983 | ||
13984 | static unsigned long | |
13985 | mips16_immed_extend (offsetT val, unsigned int nbits) | |
13986 | { | |
13987 | int extval; | |
13988 | if (nbits == 16) | |
13989 | { | |
13990 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
13991 | val &= 0x1f; | |
13992 | } | |
13993 | else if (nbits == 15) | |
13994 | { | |
13995 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
13996 | val &= 0xf; | |
13997 | } | |
13998 | else | |
13999 | { | |
14000 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
14001 | val = 0; | |
14002 | } | |
14003 | return (extval << 16) | val; | |
14004 | } | |
14005 | ||
3ccad066 RS |
14006 | /* Like decode_mips16_operand, but require the operand to be defined and |
14007 | require it to be an integer. */ | |
14008 | ||
14009 | static const struct mips_int_operand * | |
14010 | mips16_immed_operand (int type, bfd_boolean extended_p) | |
14011 | { | |
14012 | const struct mips_operand *operand; | |
14013 | ||
14014 | operand = decode_mips16_operand (type, extended_p); | |
14015 | if (!operand || (operand->type != OP_INT && operand->type != OP_PCREL)) | |
14016 | abort (); | |
14017 | return (const struct mips_int_operand *) operand; | |
14018 | } | |
14019 | ||
14020 | /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */ | |
14021 | ||
14022 | static bfd_boolean | |
14023 | mips16_immed_in_range_p (const struct mips_int_operand *operand, | |
14024 | bfd_reloc_code_real_type reloc, offsetT sval) | |
14025 | { | |
14026 | int min_val, max_val; | |
14027 | ||
14028 | min_val = mips_int_operand_min (operand); | |
14029 | max_val = mips_int_operand_max (operand); | |
14030 | if (reloc != BFD_RELOC_UNUSED) | |
14031 | { | |
14032 | if (min_val < 0) | |
14033 | sval = SEXT_16BIT (sval); | |
14034 | else | |
14035 | sval &= 0xffff; | |
14036 | } | |
14037 | ||
14038 | return (sval >= min_val | |
14039 | && sval <= max_val | |
14040 | && (sval & ((1 << operand->shift) - 1)) == 0); | |
14041 | } | |
14042 | ||
5c04167a RS |
14043 | /* Install immediate value VAL into MIPS16 instruction *INSN, |
14044 | extending it if necessary. The instruction in *INSN may | |
14045 | already be extended. | |
14046 | ||
43c0598f RS |
14047 | RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED |
14048 | if none. In the former case, VAL is a 16-bit number with no | |
14049 | defined signedness. | |
14050 | ||
14051 | TYPE is the type of the immediate field. USER_INSN_LENGTH | |
14052 | is the length that the user requested, or 0 if none. */ | |
252b5132 RH |
14053 | |
14054 | static void | |
3b4dbbbf | 14055 | mips16_immed (const char *file, unsigned int line, int type, |
43c0598f | 14056 | bfd_reloc_code_real_type reloc, offsetT val, |
5c04167a | 14057 | unsigned int user_insn_length, unsigned long *insn) |
252b5132 | 14058 | { |
3ccad066 RS |
14059 | const struct mips_int_operand *operand; |
14060 | unsigned int uval, length; | |
252b5132 | 14061 | |
3ccad066 RS |
14062 | operand = mips16_immed_operand (type, FALSE); |
14063 | if (!mips16_immed_in_range_p (operand, reloc, val)) | |
5c04167a RS |
14064 | { |
14065 | /* We need an extended instruction. */ | |
14066 | if (user_insn_length == 2) | |
14067 | as_bad_where (file, line, _("invalid unextended operand value")); | |
14068 | else | |
14069 | *insn |= MIPS16_EXTEND; | |
14070 | } | |
14071 | else if (user_insn_length == 4) | |
14072 | { | |
14073 | /* The operand doesn't force an unextended instruction to be extended. | |
14074 | Warn if the user wanted an extended instruction anyway. */ | |
14075 | *insn |= MIPS16_EXTEND; | |
14076 | as_warn_where (file, line, | |
14077 | _("extended operand requested but not required")); | |
14078 | } | |
252b5132 | 14079 | |
3ccad066 RS |
14080 | length = mips16_opcode_length (*insn); |
14081 | if (length == 4) | |
252b5132 | 14082 | { |
3ccad066 RS |
14083 | operand = mips16_immed_operand (type, TRUE); |
14084 | if (!mips16_immed_in_range_p (operand, reloc, val)) | |
14085 | as_bad_where (file, line, | |
14086 | _("operand value out of range for instruction")); | |
252b5132 | 14087 | } |
3ccad066 | 14088 | uval = ((unsigned int) val >> operand->shift) - operand->bias; |
bdd15286 | 14089 | if (length == 2 || operand->root.lsb != 0) |
3ccad066 | 14090 | *insn = mips_insert_operand (&operand->root, *insn, uval); |
252b5132 | 14091 | else |
3ccad066 | 14092 | *insn |= mips16_immed_extend (uval, operand->root.size); |
252b5132 RH |
14093 | } |
14094 | \f | |
d6f16593 | 14095 | struct percent_op_match |
ad8d3bb3 | 14096 | { |
5e0116d5 RS |
14097 | const char *str; |
14098 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
14099 | }; |
14100 | ||
14101 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 14102 | { |
5e0116d5 | 14103 | {"%lo", BFD_RELOC_LO16}, |
5e0116d5 RS |
14104 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
14105 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
14106 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
14107 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
14108 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
14109 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
14110 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
14111 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
14112 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
14113 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
be3f1006 | 14114 | {"%gprel", BFD_RELOC_GPREL16}, |
5e0116d5 RS |
14115 | {"%half", BFD_RELOC_16}, |
14116 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
14117 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
14118 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
14119 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
14120 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
14121 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
14122 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
14123 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
14124 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
14125 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
7361da2c AB |
14126 | {"%hi", BFD_RELOC_HI16_S}, |
14127 | {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL}, | |
14128 | {"%pcrel_lo", BFD_RELOC_LO16_PCREL} | |
ad8d3bb3 TS |
14129 | }; |
14130 | ||
d6f16593 MR |
14131 | static const struct percent_op_match mips16_percent_op[] = |
14132 | { | |
14133 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
be3f1006 | 14134 | {"%gp_rel", BFD_RELOC_MIPS16_GPREL}, |
d6f16593 | 14135 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, |
738e5348 RS |
14136 | {"%got", BFD_RELOC_MIPS16_GOT16}, |
14137 | {"%call16", BFD_RELOC_MIPS16_CALL16}, | |
d0f13682 CLT |
14138 | {"%hi", BFD_RELOC_MIPS16_HI16_S}, |
14139 | {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD}, | |
14140 | {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM}, | |
14141 | {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16}, | |
14142 | {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16}, | |
14143 | {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16}, | |
14144 | {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16}, | |
14145 | {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL} | |
d6f16593 MR |
14146 | }; |
14147 | ||
252b5132 | 14148 | |
5e0116d5 RS |
14149 | /* Return true if *STR points to a relocation operator. When returning true, |
14150 | move *STR over the operator and store its relocation code in *RELOC. | |
14151 | Leave both *STR and *RELOC alone when returning false. */ | |
14152 | ||
14153 | static bfd_boolean | |
17a2f251 | 14154 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 14155 | { |
d6f16593 MR |
14156 | const struct percent_op_match *percent_op; |
14157 | size_t limit, i; | |
14158 | ||
14159 | if (mips_opts.mips16) | |
14160 | { | |
14161 | percent_op = mips16_percent_op; | |
14162 | limit = ARRAY_SIZE (mips16_percent_op); | |
14163 | } | |
14164 | else | |
14165 | { | |
14166 | percent_op = mips_percent_op; | |
14167 | limit = ARRAY_SIZE (mips_percent_op); | |
14168 | } | |
76b3015f | 14169 | |
d6f16593 | 14170 | for (i = 0; i < limit; i++) |
5e0116d5 | 14171 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 14172 | { |
3f98094e DJ |
14173 | int len = strlen (percent_op[i].str); |
14174 | ||
14175 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
14176 | continue; | |
14177 | ||
5e0116d5 RS |
14178 | *str += strlen (percent_op[i].str); |
14179 | *reloc = percent_op[i].reloc; | |
394f9b3a | 14180 | |
5e0116d5 RS |
14181 | /* Check whether the output BFD supports this relocation. |
14182 | If not, issue an error and fall back on something safe. */ | |
14183 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 14184 | { |
20203fb9 | 14185 | as_bad (_("relocation %s isn't supported by the current ABI"), |
5e0116d5 | 14186 | percent_op[i].str); |
01a3f561 | 14187 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 14188 | } |
5e0116d5 | 14189 | return TRUE; |
394f9b3a | 14190 | } |
5e0116d5 | 14191 | return FALSE; |
394f9b3a | 14192 | } |
ad8d3bb3 | 14193 | |
ad8d3bb3 | 14194 | |
5e0116d5 RS |
14195 | /* Parse string STR as a 16-bit relocatable operand. Store the |
14196 | expression in *EP and the relocations in the array starting | |
14197 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 14198 | |
01a3f561 | 14199 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 14200 | |
5e0116d5 | 14201 | static size_t |
17a2f251 TS |
14202 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
14203 | char *str) | |
ad8d3bb3 | 14204 | { |
5e0116d5 RS |
14205 | bfd_reloc_code_real_type reversed_reloc[3]; |
14206 | size_t reloc_index, i; | |
09b8f35a RS |
14207 | int crux_depth, str_depth; |
14208 | char *crux; | |
5e0116d5 RS |
14209 | |
14210 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
14211 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
14212 | of the main expression and with CRUX_DEPTH containing the number | |
14213 | of open brackets at that point. */ | |
14214 | reloc_index = -1; | |
14215 | str_depth = 0; | |
14216 | do | |
fb1b3232 | 14217 | { |
09b8f35a RS |
14218 | reloc_index++; |
14219 | crux = str; | |
14220 | crux_depth = str_depth; | |
14221 | ||
14222 | /* Skip over whitespace and brackets, keeping count of the number | |
14223 | of brackets. */ | |
14224 | while (*str == ' ' || *str == '\t' || *str == '(') | |
14225 | if (*str++ == '(') | |
14226 | str_depth++; | |
5e0116d5 | 14227 | } |
09b8f35a RS |
14228 | while (*str == '%' |
14229 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
14230 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 14231 | |
09b8f35a | 14232 | my_getExpression (ep, crux); |
5e0116d5 | 14233 | str = expr_end; |
394f9b3a | 14234 | |
5e0116d5 | 14235 | /* Match every open bracket. */ |
09b8f35a | 14236 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 14237 | if (*str++ == ')') |
09b8f35a | 14238 | crux_depth--; |
394f9b3a | 14239 | |
09b8f35a | 14240 | if (crux_depth > 0) |
20203fb9 | 14241 | as_bad (_("unclosed '('")); |
394f9b3a | 14242 | |
5e0116d5 | 14243 | expr_end = str; |
252b5132 | 14244 | |
01a3f561 | 14245 | if (reloc_index != 0) |
64bdfcaf RS |
14246 | { |
14247 | prev_reloc_op_frag = frag_now; | |
14248 | for (i = 0; i < reloc_index; i++) | |
14249 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
14250 | } | |
fb1b3232 | 14251 | |
5e0116d5 | 14252 | return reloc_index; |
252b5132 RH |
14253 | } |
14254 | ||
14255 | static void | |
17a2f251 | 14256 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
14257 | { |
14258 | char *save_in; | |
14259 | ||
14260 | save_in = input_line_pointer; | |
14261 | input_line_pointer = str; | |
14262 | expression (ep); | |
14263 | expr_end = input_line_pointer; | |
14264 | input_line_pointer = save_in; | |
252b5132 RH |
14265 | } |
14266 | ||
6d4af3c2 | 14267 | const char * |
17a2f251 | 14268 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 14269 | { |
499ac353 | 14270 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
252b5132 RH |
14271 | } |
14272 | ||
14273 | void | |
17a2f251 | 14274 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
14275 | { |
14276 | if (target_big_endian) | |
14277 | number_to_chars_bigendian (buf, val, n); | |
14278 | else | |
14279 | number_to_chars_littleendian (buf, val, n); | |
14280 | } | |
14281 | \f | |
e013f690 TS |
14282 | static int support_64bit_objects(void) |
14283 | { | |
14284 | const char **list, **l; | |
aa3d8fdf | 14285 | int yes; |
e013f690 TS |
14286 | |
14287 | list = bfd_target_list (); | |
14288 | for (l = list; *l != NULL; l++) | |
aeffff67 RS |
14289 | if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0 |
14290 | || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0) | |
e013f690 | 14291 | break; |
aa3d8fdf | 14292 | yes = (*l != NULL); |
e013f690 | 14293 | free (list); |
aa3d8fdf | 14294 | return yes; |
e013f690 TS |
14295 | } |
14296 | ||
316f5878 RS |
14297 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
14298 | NEW_VALUE. Warn if another value was already specified. Note: | |
14299 | we have to defer parsing the -march and -mtune arguments in order | |
14300 | to handle 'from-abi' correctly, since the ABI might be specified | |
14301 | in a later argument. */ | |
14302 | ||
14303 | static void | |
17a2f251 | 14304 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
14305 | { |
14306 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
1661c76c | 14307 | as_warn (_("a different %s was already specified, is now %s"), |
316f5878 RS |
14308 | string_ptr == &mips_arch_string ? "-march" : "-mtune", |
14309 | new_value); | |
14310 | ||
14311 | *string_ptr = new_value; | |
14312 | } | |
14313 | ||
252b5132 | 14314 | int |
17b9d67d | 14315 | md_parse_option (int c, const char *arg) |
252b5132 | 14316 | { |
c6278170 RS |
14317 | unsigned int i; |
14318 | ||
14319 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
14320 | if (c == mips_ases[i].option_on || c == mips_ases[i].option_off) | |
14321 | { | |
919731af | 14322 | file_ase_explicit |= mips_set_ase (&mips_ases[i], &file_mips_opts, |
c6278170 RS |
14323 | c == mips_ases[i].option_on); |
14324 | return 1; | |
14325 | } | |
14326 | ||
252b5132 RH |
14327 | switch (c) |
14328 | { | |
119d663a NC |
14329 | case OPTION_CONSTRUCT_FLOATS: |
14330 | mips_disable_float_construction = 0; | |
14331 | break; | |
bdaaa2e1 | 14332 | |
119d663a NC |
14333 | case OPTION_NO_CONSTRUCT_FLOATS: |
14334 | mips_disable_float_construction = 1; | |
14335 | break; | |
bdaaa2e1 | 14336 | |
252b5132 RH |
14337 | case OPTION_TRAP: |
14338 | mips_trap = 1; | |
14339 | break; | |
14340 | ||
14341 | case OPTION_BREAK: | |
14342 | mips_trap = 0; | |
14343 | break; | |
14344 | ||
14345 | case OPTION_EB: | |
14346 | target_big_endian = 1; | |
14347 | break; | |
14348 | ||
14349 | case OPTION_EL: | |
14350 | target_big_endian = 0; | |
14351 | break; | |
14352 | ||
14353 | case 'O': | |
4ffff32f TS |
14354 | if (arg == NULL) |
14355 | mips_optimize = 1; | |
14356 | else if (arg[0] == '0') | |
14357 | mips_optimize = 0; | |
14358 | else if (arg[0] == '1') | |
252b5132 RH |
14359 | mips_optimize = 1; |
14360 | else | |
14361 | mips_optimize = 2; | |
14362 | break; | |
14363 | ||
14364 | case 'g': | |
14365 | if (arg == NULL) | |
14366 | mips_debug = 2; | |
14367 | else | |
14368 | mips_debug = atoi (arg); | |
252b5132 RH |
14369 | break; |
14370 | ||
14371 | case OPTION_MIPS1: | |
0b35dfee | 14372 | file_mips_opts.isa = ISA_MIPS1; |
252b5132 RH |
14373 | break; |
14374 | ||
14375 | case OPTION_MIPS2: | |
0b35dfee | 14376 | file_mips_opts.isa = ISA_MIPS2; |
252b5132 RH |
14377 | break; |
14378 | ||
14379 | case OPTION_MIPS3: | |
0b35dfee | 14380 | file_mips_opts.isa = ISA_MIPS3; |
252b5132 RH |
14381 | break; |
14382 | ||
14383 | case OPTION_MIPS4: | |
0b35dfee | 14384 | file_mips_opts.isa = ISA_MIPS4; |
e7af610e NC |
14385 | break; |
14386 | ||
84ea6cf2 | 14387 | case OPTION_MIPS5: |
0b35dfee | 14388 | file_mips_opts.isa = ISA_MIPS5; |
84ea6cf2 NC |
14389 | break; |
14390 | ||
e7af610e | 14391 | case OPTION_MIPS32: |
0b35dfee | 14392 | file_mips_opts.isa = ISA_MIPS32; |
252b5132 RH |
14393 | break; |
14394 | ||
af7ee8bf | 14395 | case OPTION_MIPS32R2: |
0b35dfee | 14396 | file_mips_opts.isa = ISA_MIPS32R2; |
af7ee8bf CD |
14397 | break; |
14398 | ||
ae52f483 | 14399 | case OPTION_MIPS32R3: |
0ae19f05 | 14400 | file_mips_opts.isa = ISA_MIPS32R3; |
ae52f483 AB |
14401 | break; |
14402 | ||
14403 | case OPTION_MIPS32R5: | |
0ae19f05 | 14404 | file_mips_opts.isa = ISA_MIPS32R5; |
ae52f483 AB |
14405 | break; |
14406 | ||
7361da2c AB |
14407 | case OPTION_MIPS32R6: |
14408 | file_mips_opts.isa = ISA_MIPS32R6; | |
14409 | break; | |
14410 | ||
5f74bc13 | 14411 | case OPTION_MIPS64R2: |
0b35dfee | 14412 | file_mips_opts.isa = ISA_MIPS64R2; |
5f74bc13 CD |
14413 | break; |
14414 | ||
ae52f483 | 14415 | case OPTION_MIPS64R3: |
0ae19f05 | 14416 | file_mips_opts.isa = ISA_MIPS64R3; |
ae52f483 AB |
14417 | break; |
14418 | ||
14419 | case OPTION_MIPS64R5: | |
0ae19f05 | 14420 | file_mips_opts.isa = ISA_MIPS64R5; |
ae52f483 AB |
14421 | break; |
14422 | ||
7361da2c AB |
14423 | case OPTION_MIPS64R6: |
14424 | file_mips_opts.isa = ISA_MIPS64R6; | |
14425 | break; | |
14426 | ||
84ea6cf2 | 14427 | case OPTION_MIPS64: |
0b35dfee | 14428 | file_mips_opts.isa = ISA_MIPS64; |
84ea6cf2 NC |
14429 | break; |
14430 | ||
ec68c924 | 14431 | case OPTION_MTUNE: |
316f5878 RS |
14432 | mips_set_option_string (&mips_tune_string, arg); |
14433 | break; | |
ec68c924 | 14434 | |
316f5878 RS |
14435 | case OPTION_MARCH: |
14436 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
14437 | break; |
14438 | ||
14439 | case OPTION_M4650: | |
316f5878 RS |
14440 | mips_set_option_string (&mips_arch_string, "4650"); |
14441 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
14442 | break; |
14443 | ||
14444 | case OPTION_NO_M4650: | |
14445 | break; | |
14446 | ||
14447 | case OPTION_M4010: | |
316f5878 RS |
14448 | mips_set_option_string (&mips_arch_string, "4010"); |
14449 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
14450 | break; |
14451 | ||
14452 | case OPTION_NO_M4010: | |
14453 | break; | |
14454 | ||
14455 | case OPTION_M4100: | |
316f5878 RS |
14456 | mips_set_option_string (&mips_arch_string, "4100"); |
14457 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
14458 | break; |
14459 | ||
14460 | case OPTION_NO_M4100: | |
14461 | break; | |
14462 | ||
252b5132 | 14463 | case OPTION_M3900: |
316f5878 RS |
14464 | mips_set_option_string (&mips_arch_string, "3900"); |
14465 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 14466 | break; |
bdaaa2e1 | 14467 | |
252b5132 RH |
14468 | case OPTION_NO_M3900: |
14469 | break; | |
14470 | ||
df58fc94 | 14471 | case OPTION_MICROMIPS: |
919731af | 14472 | if (file_mips_opts.mips16 == 1) |
df58fc94 RS |
14473 | { |
14474 | as_bad (_("-mmicromips cannot be used with -mips16")); | |
14475 | return 0; | |
14476 | } | |
919731af | 14477 | file_mips_opts.micromips = 1; |
df58fc94 RS |
14478 | mips_no_prev_insn (); |
14479 | break; | |
14480 | ||
14481 | case OPTION_NO_MICROMIPS: | |
919731af | 14482 | file_mips_opts.micromips = 0; |
df58fc94 RS |
14483 | mips_no_prev_insn (); |
14484 | break; | |
14485 | ||
252b5132 | 14486 | case OPTION_MIPS16: |
919731af | 14487 | if (file_mips_opts.micromips == 1) |
df58fc94 RS |
14488 | { |
14489 | as_bad (_("-mips16 cannot be used with -micromips")); | |
14490 | return 0; | |
14491 | } | |
919731af | 14492 | file_mips_opts.mips16 = 1; |
7d10b47d | 14493 | mips_no_prev_insn (); |
252b5132 RH |
14494 | break; |
14495 | ||
14496 | case OPTION_NO_MIPS16: | |
919731af | 14497 | file_mips_opts.mips16 = 0; |
7d10b47d | 14498 | mips_no_prev_insn (); |
252b5132 RH |
14499 | break; |
14500 | ||
6a32d874 CM |
14501 | case OPTION_FIX_24K: |
14502 | mips_fix_24k = 1; | |
14503 | break; | |
14504 | ||
14505 | case OPTION_NO_FIX_24K: | |
14506 | mips_fix_24k = 0; | |
14507 | break; | |
14508 | ||
a8d14a88 CM |
14509 | case OPTION_FIX_RM7000: |
14510 | mips_fix_rm7000 = 1; | |
14511 | break; | |
14512 | ||
14513 | case OPTION_NO_FIX_RM7000: | |
14514 | mips_fix_rm7000 = 0; | |
14515 | break; | |
14516 | ||
c67a084a NC |
14517 | case OPTION_FIX_LOONGSON2F_JUMP: |
14518 | mips_fix_loongson2f_jump = TRUE; | |
14519 | break; | |
14520 | ||
14521 | case OPTION_NO_FIX_LOONGSON2F_JUMP: | |
14522 | mips_fix_loongson2f_jump = FALSE; | |
14523 | break; | |
14524 | ||
14525 | case OPTION_FIX_LOONGSON2F_NOP: | |
14526 | mips_fix_loongson2f_nop = TRUE; | |
14527 | break; | |
14528 | ||
14529 | case OPTION_NO_FIX_LOONGSON2F_NOP: | |
14530 | mips_fix_loongson2f_nop = FALSE; | |
14531 | break; | |
14532 | ||
d766e8ec RS |
14533 | case OPTION_FIX_VR4120: |
14534 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
14535 | break; |
14536 | ||
d766e8ec RS |
14537 | case OPTION_NO_FIX_VR4120: |
14538 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
14539 | break; |
14540 | ||
7d8e00cf RS |
14541 | case OPTION_FIX_VR4130: |
14542 | mips_fix_vr4130 = 1; | |
14543 | break; | |
14544 | ||
14545 | case OPTION_NO_FIX_VR4130: | |
14546 | mips_fix_vr4130 = 0; | |
14547 | break; | |
14548 | ||
d954098f DD |
14549 | case OPTION_FIX_CN63XXP1: |
14550 | mips_fix_cn63xxp1 = TRUE; | |
14551 | break; | |
14552 | ||
14553 | case OPTION_NO_FIX_CN63XXP1: | |
14554 | mips_fix_cn63xxp1 = FALSE; | |
14555 | break; | |
14556 | ||
4a6a3df4 AO |
14557 | case OPTION_RELAX_BRANCH: |
14558 | mips_relax_branch = 1; | |
14559 | break; | |
14560 | ||
14561 | case OPTION_NO_RELAX_BRANCH: | |
14562 | mips_relax_branch = 0; | |
14563 | break; | |
14564 | ||
8b10b0b3 MR |
14565 | case OPTION_IGNORE_BRANCH_ISA: |
14566 | mips_ignore_branch_isa = TRUE; | |
14567 | break; | |
14568 | ||
14569 | case OPTION_NO_IGNORE_BRANCH_ISA: | |
14570 | mips_ignore_branch_isa = FALSE; | |
14571 | break; | |
14572 | ||
833794fc | 14573 | case OPTION_INSN32: |
919731af | 14574 | file_mips_opts.insn32 = TRUE; |
833794fc MR |
14575 | break; |
14576 | ||
14577 | case OPTION_NO_INSN32: | |
919731af | 14578 | file_mips_opts.insn32 = FALSE; |
833794fc MR |
14579 | break; |
14580 | ||
aa6975fb ILT |
14581 | case OPTION_MSHARED: |
14582 | mips_in_shared = TRUE; | |
14583 | break; | |
14584 | ||
14585 | case OPTION_MNO_SHARED: | |
14586 | mips_in_shared = FALSE; | |
14587 | break; | |
14588 | ||
aed1a261 | 14589 | case OPTION_MSYM32: |
919731af | 14590 | file_mips_opts.sym32 = TRUE; |
aed1a261 RS |
14591 | break; |
14592 | ||
14593 | case OPTION_MNO_SYM32: | |
919731af | 14594 | file_mips_opts.sym32 = FALSE; |
aed1a261 RS |
14595 | break; |
14596 | ||
252b5132 RH |
14597 | /* When generating ELF code, we permit -KPIC and -call_shared to |
14598 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
14599 | intended to be compatible with Irix 5. */ | |
14600 | case OPTION_CALL_SHARED: | |
252b5132 | 14601 | mips_pic = SVR4_PIC; |
143d77c5 | 14602 | mips_abicalls = TRUE; |
252b5132 RH |
14603 | break; |
14604 | ||
861fb55a | 14605 | case OPTION_CALL_NONPIC: |
861fb55a DJ |
14606 | mips_pic = NO_PIC; |
14607 | mips_abicalls = TRUE; | |
14608 | break; | |
14609 | ||
252b5132 | 14610 | case OPTION_NON_SHARED: |
252b5132 | 14611 | mips_pic = NO_PIC; |
143d77c5 | 14612 | mips_abicalls = FALSE; |
252b5132 RH |
14613 | break; |
14614 | ||
44075ae2 TS |
14615 | /* The -xgot option tells the assembler to use 32 bit offsets |
14616 | when accessing the got in SVR4_PIC mode. It is for Irix | |
252b5132 RH |
14617 | compatibility. */ |
14618 | case OPTION_XGOT: | |
14619 | mips_big_got = 1; | |
14620 | break; | |
14621 | ||
14622 | case 'G': | |
6caf9ef4 TS |
14623 | g_switch_value = atoi (arg); |
14624 | g_switch_seen = 1; | |
252b5132 RH |
14625 | break; |
14626 | ||
34ba82a8 TS |
14627 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
14628 | and -mabi=64. */ | |
252b5132 | 14629 | case OPTION_32: |
f3ded42a | 14630 | mips_abi = O32_ABI; |
252b5132 RH |
14631 | break; |
14632 | ||
e013f690 | 14633 | case OPTION_N32: |
316f5878 | 14634 | mips_abi = N32_ABI; |
e013f690 | 14635 | break; |
252b5132 | 14636 | |
e013f690 | 14637 | case OPTION_64: |
316f5878 | 14638 | mips_abi = N64_ABI; |
f43abd2b | 14639 | if (!support_64bit_objects()) |
1661c76c | 14640 | as_fatal (_("no compiled in support for 64 bit object file format")); |
252b5132 RH |
14641 | break; |
14642 | ||
c97ef257 | 14643 | case OPTION_GP32: |
bad1aba3 | 14644 | file_mips_opts.gp = 32; |
c97ef257 AH |
14645 | break; |
14646 | ||
14647 | case OPTION_GP64: | |
bad1aba3 | 14648 | file_mips_opts.gp = 64; |
c97ef257 | 14649 | break; |
252b5132 | 14650 | |
ca4e0257 | 14651 | case OPTION_FP32: |
0b35dfee | 14652 | file_mips_opts.fp = 32; |
316f5878 RS |
14653 | break; |
14654 | ||
351cdf24 MF |
14655 | case OPTION_FPXX: |
14656 | file_mips_opts.fp = 0; | |
14657 | break; | |
14658 | ||
316f5878 | 14659 | case OPTION_FP64: |
0b35dfee | 14660 | file_mips_opts.fp = 64; |
ca4e0257 RS |
14661 | break; |
14662 | ||
351cdf24 MF |
14663 | case OPTION_ODD_SPREG: |
14664 | file_mips_opts.oddspreg = 1; | |
14665 | break; | |
14666 | ||
14667 | case OPTION_NO_ODD_SPREG: | |
14668 | file_mips_opts.oddspreg = 0; | |
14669 | break; | |
14670 | ||
037b32b9 | 14671 | case OPTION_SINGLE_FLOAT: |
0b35dfee | 14672 | file_mips_opts.single_float = 1; |
037b32b9 AN |
14673 | break; |
14674 | ||
14675 | case OPTION_DOUBLE_FLOAT: | |
0b35dfee | 14676 | file_mips_opts.single_float = 0; |
037b32b9 AN |
14677 | break; |
14678 | ||
14679 | case OPTION_SOFT_FLOAT: | |
0b35dfee | 14680 | file_mips_opts.soft_float = 1; |
037b32b9 AN |
14681 | break; |
14682 | ||
14683 | case OPTION_HARD_FLOAT: | |
0b35dfee | 14684 | file_mips_opts.soft_float = 0; |
037b32b9 AN |
14685 | break; |
14686 | ||
252b5132 | 14687 | case OPTION_MABI: |
e013f690 | 14688 | if (strcmp (arg, "32") == 0) |
316f5878 | 14689 | mips_abi = O32_ABI; |
e013f690 | 14690 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 14691 | mips_abi = O64_ABI; |
e013f690 | 14692 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 14693 | mips_abi = N32_ABI; |
e013f690 TS |
14694 | else if (strcmp (arg, "64") == 0) |
14695 | { | |
316f5878 | 14696 | mips_abi = N64_ABI; |
e013f690 | 14697 | if (! support_64bit_objects()) |
1661c76c | 14698 | as_fatal (_("no compiled in support for 64 bit object file " |
e013f690 TS |
14699 | "format")); |
14700 | } | |
14701 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 14702 | mips_abi = EABI_ABI; |
e013f690 | 14703 | else |
da0e507f TS |
14704 | { |
14705 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
14706 | return 0; | |
14707 | } | |
252b5132 RH |
14708 | break; |
14709 | ||
6b76fefe | 14710 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 14711 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
14712 | break; |
14713 | ||
9ee72ff1 | 14714 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 14715 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
14716 | break; |
14717 | ||
ecb4347a | 14718 | case OPTION_MDEBUG: |
b34976b6 | 14719 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
14720 | break; |
14721 | ||
14722 | case OPTION_NO_MDEBUG: | |
b34976b6 | 14723 | mips_flag_mdebug = FALSE; |
ecb4347a | 14724 | break; |
dcd410fe RO |
14725 | |
14726 | case OPTION_PDR: | |
14727 | mips_flag_pdr = TRUE; | |
14728 | break; | |
14729 | ||
14730 | case OPTION_NO_PDR: | |
14731 | mips_flag_pdr = FALSE; | |
14732 | break; | |
0a44bf69 RS |
14733 | |
14734 | case OPTION_MVXWORKS_PIC: | |
14735 | mips_pic = VXWORKS_PIC; | |
14736 | break; | |
ecb4347a | 14737 | |
ba92f887 MR |
14738 | case OPTION_NAN: |
14739 | if (strcmp (arg, "2008") == 0) | |
7361da2c | 14740 | mips_nan2008 = 1; |
ba92f887 | 14741 | else if (strcmp (arg, "legacy") == 0) |
7361da2c | 14742 | mips_nan2008 = 0; |
ba92f887 MR |
14743 | else |
14744 | { | |
1661c76c | 14745 | as_fatal (_("invalid NaN setting -mnan=%s"), arg); |
ba92f887 MR |
14746 | return 0; |
14747 | } | |
14748 | break; | |
14749 | ||
252b5132 RH |
14750 | default: |
14751 | return 0; | |
14752 | } | |
14753 | ||
c67a084a NC |
14754 | mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump; |
14755 | ||
252b5132 RH |
14756 | return 1; |
14757 | } | |
316f5878 | 14758 | \f |
919731af | 14759 | /* Set up globals to tune for the ISA or processor described by INFO. */ |
252b5132 | 14760 | |
316f5878 | 14761 | static void |
17a2f251 | 14762 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
14763 | { |
14764 | if (info != 0) | |
fef14a42 | 14765 | mips_tune = info->cpu; |
316f5878 | 14766 | } |
80cc45a5 | 14767 | |
34ba82a8 | 14768 | |
252b5132 | 14769 | void |
17a2f251 | 14770 | mips_after_parse_args (void) |
e9670677 | 14771 | { |
fef14a42 TS |
14772 | const struct mips_cpu_info *arch_info = 0; |
14773 | const struct mips_cpu_info *tune_info = 0; | |
14774 | ||
e9670677 | 14775 | /* GP relative stuff not working for PE */ |
6caf9ef4 | 14776 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
e9670677 | 14777 | { |
6caf9ef4 | 14778 | if (g_switch_seen && g_switch_value != 0) |
1661c76c | 14779 | as_bad (_("-G not supported in this configuration")); |
e9670677 MR |
14780 | g_switch_value = 0; |
14781 | } | |
14782 | ||
cac012d6 AO |
14783 | if (mips_abi == NO_ABI) |
14784 | mips_abi = MIPS_DEFAULT_ABI; | |
14785 | ||
919731af | 14786 | /* The following code determines the architecture. |
22923709 RS |
14787 | Similar code was added to GCC 3.3 (see override_options() in |
14788 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
14789 | as much as possible. */ | |
e9670677 | 14790 | |
316f5878 | 14791 | if (mips_arch_string != 0) |
fef14a42 | 14792 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 14793 | |
0b35dfee | 14794 | if (file_mips_opts.isa != ISA_UNKNOWN) |
e9670677 | 14795 | { |
0b35dfee | 14796 | /* Handle -mipsN. At this point, file_mips_opts.isa contains the |
fef14a42 | 14797 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 14798 | the -march selection (if any). */ |
fef14a42 | 14799 | if (arch_info != 0) |
e9670677 | 14800 | { |
316f5878 RS |
14801 | /* -march takes precedence over -mipsN, since it is more descriptive. |
14802 | There's no harm in specifying both as long as the ISA levels | |
14803 | are the same. */ | |
0b35dfee | 14804 | if (file_mips_opts.isa != arch_info->isa) |
1661c76c RS |
14805 | as_bad (_("-%s conflicts with the other architecture options," |
14806 | " which imply -%s"), | |
0b35dfee | 14807 | mips_cpu_info_from_isa (file_mips_opts.isa)->name, |
fef14a42 | 14808 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 14809 | } |
316f5878 | 14810 | else |
0b35dfee | 14811 | arch_info = mips_cpu_info_from_isa (file_mips_opts.isa); |
e9670677 MR |
14812 | } |
14813 | ||
fef14a42 | 14814 | if (arch_info == 0) |
95bfe26e MF |
14815 | { |
14816 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
14817 | gas_assert (arch_info); | |
14818 | } | |
e9670677 | 14819 | |
fef14a42 | 14820 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
20203fb9 | 14821 | as_bad (_("-march=%s is not compatible with the selected ABI"), |
fef14a42 TS |
14822 | arch_info->name); |
14823 | ||
919731af | 14824 | file_mips_opts.arch = arch_info->cpu; |
14825 | file_mips_opts.isa = arch_info->isa; | |
14826 | ||
14827 | /* Set up initial mips_opts state. */ | |
14828 | mips_opts = file_mips_opts; | |
14829 | ||
14830 | /* The register size inference code is now placed in | |
14831 | file_mips_check_options. */ | |
fef14a42 | 14832 | |
0b35dfee | 14833 | /* Optimize for file_mips_opts.arch, unless -mtune selects a different |
14834 | processor. */ | |
fef14a42 TS |
14835 | if (mips_tune_string != 0) |
14836 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 14837 | |
fef14a42 TS |
14838 | if (tune_info == 0) |
14839 | mips_set_tune (arch_info); | |
14840 | else | |
14841 | mips_set_tune (tune_info); | |
e9670677 | 14842 | |
ecb4347a | 14843 | if (mips_flag_mdebug < 0) |
e8044f35 | 14844 | mips_flag_mdebug = 0; |
e9670677 MR |
14845 | } |
14846 | \f | |
14847 | void | |
17a2f251 | 14848 | mips_init_after_args (void) |
252b5132 RH |
14849 | { |
14850 | /* initialize opcodes */ | |
14851 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 14852 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
14853 | } |
14854 | ||
14855 | long | |
17a2f251 | 14856 | md_pcrel_from (fixS *fixP) |
252b5132 | 14857 | { |
a7ebbfdf TS |
14858 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
14859 | switch (fixP->fx_r_type) | |
14860 | { | |
df58fc94 RS |
14861 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
14862 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
14863 | /* Return the address of the delay slot. */ | |
14864 | return addr + 2; | |
14865 | ||
14866 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
14867 | case BFD_RELOC_MICROMIPS_JMP: | |
c9775dde | 14868 | case BFD_RELOC_MIPS16_16_PCREL_S1: |
a7ebbfdf | 14869 | case BFD_RELOC_16_PCREL_S2: |
7361da2c AB |
14870 | case BFD_RELOC_MIPS_21_PCREL_S2: |
14871 | case BFD_RELOC_MIPS_26_PCREL_S2: | |
a7ebbfdf TS |
14872 | case BFD_RELOC_MIPS_JMP: |
14873 | /* Return the address of the delay slot. */ | |
14874 | return addr + 4; | |
df58fc94 | 14875 | |
51f6035b MR |
14876 | case BFD_RELOC_MIPS_18_PCREL_S3: |
14877 | /* Return the aligned address of the doubleword containing | |
14878 | the instruction. */ | |
14879 | return addr & ~7; | |
14880 | ||
a7ebbfdf TS |
14881 | default: |
14882 | return addr; | |
14883 | } | |
252b5132 RH |
14884 | } |
14885 | ||
252b5132 RH |
14886 | /* This is called before the symbol table is processed. In order to |
14887 | work with gcc when using mips-tfile, we must keep all local labels. | |
14888 | However, in other cases, we want to discard them. If we were | |
14889 | called with -g, but we didn't see any debugging information, it may | |
14890 | mean that gcc is smuggling debugging information through to | |
14891 | mips-tfile, in which case we must generate all local labels. */ | |
14892 | ||
14893 | void | |
17a2f251 | 14894 | mips_frob_file_before_adjust (void) |
252b5132 RH |
14895 | { |
14896 | #ifndef NO_ECOFF_DEBUGGING | |
14897 | if (ECOFF_DEBUGGING | |
14898 | && mips_debug != 0 | |
14899 | && ! ecoff_debugging_seen) | |
14900 | flag_keep_locals = 1; | |
14901 | #endif | |
14902 | } | |
14903 | ||
3b91255e | 14904 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
55cf6793 | 14905 | the corresponding LO16 reloc. This is called before md_apply_fix and |
3b91255e RS |
14906 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit |
14907 | relocation operators. | |
14908 | ||
14909 | For our purposes, a %lo() expression matches a %got() or %hi() | |
14910 | expression if: | |
14911 | ||
14912 | (a) it refers to the same symbol; and | |
14913 | (b) the offset applied in the %lo() expression is no lower than | |
14914 | the offset applied in the %got() or %hi(). | |
14915 | ||
14916 | (b) allows us to cope with code like: | |
14917 | ||
14918 | lui $4,%hi(foo) | |
14919 | lh $4,%lo(foo+2)($4) | |
14920 | ||
14921 | ...which is legal on RELA targets, and has a well-defined behaviour | |
14922 | if the user knows that adding 2 to "foo" will not induce a carry to | |
14923 | the high 16 bits. | |
14924 | ||
14925 | When several %lo()s match a particular %got() or %hi(), we use the | |
14926 | following rules to distinguish them: | |
14927 | ||
14928 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
14929 | higher offsets. | |
14930 | ||
14931 | (2) %lo()s with no matching %got() or %hi() are better than those | |
14932 | that already have a matching %got() or %hi(). | |
14933 | ||
14934 | (3) later %lo()s are better than earlier %lo()s. | |
14935 | ||
14936 | These rules are applied in order. | |
14937 | ||
14938 | (1) means, among other things, that %lo()s with identical offsets are | |
14939 | chosen if they exist. | |
14940 | ||
14941 | (2) means that we won't associate several high-part relocations with | |
14942 | the same low-part relocation unless there's no alternative. Having | |
14943 | several high parts for the same low part is a GNU extension; this rule | |
14944 | allows careful users to avoid it. | |
14945 | ||
14946 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
14947 | with the last high-part relocation being at the front of the list. | |
14948 | It therefore makes sense to choose the last matching low-part | |
14949 | relocation, all other things being equal. It's also easier | |
14950 | to code that way. */ | |
252b5132 RH |
14951 | |
14952 | void | |
17a2f251 | 14953 | mips_frob_file (void) |
252b5132 RH |
14954 | { |
14955 | struct mips_hi_fixup *l; | |
35903be0 | 14956 | bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED; |
252b5132 RH |
14957 | |
14958 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
14959 | { | |
14960 | segment_info_type *seginfo; | |
3b91255e RS |
14961 | bfd_boolean matched_lo_p; |
14962 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 14963 | |
9c2799c2 | 14964 | gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 14965 | |
5919d012 | 14966 | /* If a GOT16 relocation turns out to be against a global symbol, |
b886a2ab RS |
14967 | there isn't supposed to be a matching LO. Ignore %gots against |
14968 | constants; we'll report an error for those later. */ | |
738e5348 | 14969 | if (got16_reloc_p (l->fixp->fx_r_type) |
b886a2ab | 14970 | && !(l->fixp->fx_addsy |
9e009953 | 14971 | && pic_need_relax (l->fixp->fx_addsy))) |
5919d012 RS |
14972 | continue; |
14973 | ||
14974 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
14975 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
14976 | continue; |
14977 | ||
252b5132 | 14978 | seginfo = seg_info (l->seg); |
252b5132 | 14979 | |
3b91255e RS |
14980 | /* Set HI_POS to the position of this relocation in the chain. |
14981 | Set LO_POS to the position of the chosen low-part relocation. | |
14982 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
14983 | relocation that matches an immediately-preceding high-part | |
14984 | relocation. */ | |
14985 | hi_pos = NULL; | |
14986 | lo_pos = NULL; | |
14987 | matched_lo_p = FALSE; | |
738e5348 | 14988 | looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type); |
35903be0 | 14989 | |
3b91255e RS |
14990 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) |
14991 | { | |
14992 | if (*pos == l->fixp) | |
14993 | hi_pos = pos; | |
14994 | ||
35903be0 | 14995 | if ((*pos)->fx_r_type == looking_for_rtype |
30cfc97a | 14996 | && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy) |
3b91255e RS |
14997 | && (*pos)->fx_offset >= l->fixp->fx_offset |
14998 | && (lo_pos == NULL | |
14999 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
15000 | || (!matched_lo_p | |
15001 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
15002 | lo_pos = pos; | |
15003 | ||
15004 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
15005 | && fixup_has_matching_lo_p (*pos)); | |
15006 | } | |
15007 | ||
15008 | /* If we found a match, remove the high-part relocation from its | |
15009 | current position and insert it before the low-part relocation. | |
15010 | Make the offsets match so that fixup_has_matching_lo_p() | |
15011 | will return true. | |
15012 | ||
15013 | We don't warn about unmatched high-part relocations since some | |
15014 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
15015 | instructions. */ | |
15016 | if (lo_pos != NULL) | |
15017 | { | |
15018 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
15019 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 15020 | { |
3b91255e RS |
15021 | *hi_pos = l->fixp->fx_next; |
15022 | l->fixp->fx_next = *lo_pos; | |
15023 | *lo_pos = l->fixp; | |
252b5132 | 15024 | } |
252b5132 RH |
15025 | } |
15026 | } | |
15027 | } | |
15028 | ||
252b5132 | 15029 | int |
17a2f251 | 15030 | mips_force_relocation (fixS *fixp) |
252b5132 | 15031 | { |
ae6063d4 | 15032 | if (generic_force_reloc (fixp)) |
252b5132 RH |
15033 | return 1; |
15034 | ||
df58fc94 RS |
15035 | /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation, |
15036 | so that the linker relaxation can update targets. */ | |
15037 | if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
15038 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
15039 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1) | |
15040 | return 1; | |
15041 | ||
5caa2b07 MR |
15042 | /* We want to keep BFD_RELOC_16_PCREL_S2 BFD_RELOC_MIPS_21_PCREL_S2 |
15043 | and BFD_RELOC_MIPS_26_PCREL_S2 relocations against MIPS16 and | |
15044 | microMIPS symbols so that we can do cross-mode branch diagnostics | |
15045 | and BAL to JALX conversion by the linker. */ | |
15046 | if ((fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 | |
9d862524 MR |
15047 | || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2 |
15048 | || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2) | |
15049 | && fixp->fx_addsy | |
15050 | && ELF_ST_IS_COMPRESSED (S_GET_OTHER (fixp->fx_addsy))) | |
15051 | return 1; | |
15052 | ||
7361da2c | 15053 | /* We want all PC-relative relocations to be kept for R6 relaxation. */ |
912815f0 | 15054 | if (ISA_IS_R6 (file_mips_opts.isa) |
7361da2c AB |
15055 | && (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 |
15056 | || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2 | |
15057 | || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2 | |
15058 | || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3 | |
15059 | || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2 | |
15060 | || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL | |
15061 | || fixp->fx_r_type == BFD_RELOC_LO16_PCREL)) | |
15062 | return 1; | |
15063 | ||
3e722fb5 | 15064 | return 0; |
252b5132 RH |
15065 | } |
15066 | ||
b416ba9b MR |
15067 | /* Implement TC_FORCE_RELOCATION_ABS. */ |
15068 | ||
15069 | bfd_boolean | |
15070 | mips_force_relocation_abs (fixS *fixp) | |
15071 | { | |
15072 | if (generic_force_reloc (fixp)) | |
15073 | return TRUE; | |
15074 | ||
15075 | /* These relocations do not have enough bits in the in-place addend | |
15076 | to hold an arbitrary absolute section's offset. */ | |
15077 | if (HAVE_IN_PLACE_ADDENDS && limited_pcrel_reloc_p (fixp->fx_r_type)) | |
15078 | return TRUE; | |
15079 | ||
15080 | return FALSE; | |
15081 | } | |
15082 | ||
b886a2ab RS |
15083 | /* Read the instruction associated with RELOC from BUF. */ |
15084 | ||
15085 | static unsigned int | |
15086 | read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc) | |
15087 | { | |
15088 | if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) | |
15089 | return read_compressed_insn (buf, 4); | |
15090 | else | |
15091 | return read_insn (buf); | |
15092 | } | |
15093 | ||
15094 | /* Write instruction INSN to BUF, given that it has been relocated | |
15095 | by RELOC. */ | |
15096 | ||
15097 | static void | |
15098 | write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc, | |
15099 | unsigned long insn) | |
15100 | { | |
15101 | if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) | |
15102 | write_compressed_insn (buf, insn, 4); | |
15103 | else | |
15104 | write_insn (buf, insn); | |
15105 | } | |
15106 | ||
9d862524 MR |
15107 | /* Return TRUE if the instruction pointed to by FIXP is an invalid jump |
15108 | to a symbol in another ISA mode, which cannot be converted to JALX. */ | |
15109 | ||
15110 | static bfd_boolean | |
15111 | fix_bad_cross_mode_jump_p (fixS *fixP) | |
15112 | { | |
15113 | unsigned long opcode; | |
15114 | int other; | |
15115 | char *buf; | |
15116 | ||
15117 | if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) | |
15118 | return FALSE; | |
15119 | ||
15120 | other = S_GET_OTHER (fixP->fx_addsy); | |
15121 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; | |
15122 | opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 26; | |
15123 | switch (fixP->fx_r_type) | |
15124 | { | |
15125 | case BFD_RELOC_MIPS_JMP: | |
15126 | return opcode != 0x1d && opcode != 0x03 && ELF_ST_IS_COMPRESSED (other); | |
15127 | case BFD_RELOC_MICROMIPS_JMP: | |
15128 | return opcode != 0x3c && opcode != 0x3d && !ELF_ST_IS_MICROMIPS (other); | |
15129 | default: | |
15130 | return FALSE; | |
15131 | } | |
15132 | } | |
15133 | ||
15134 | /* Return TRUE if the instruction pointed to by FIXP is an invalid JALX | |
15135 | jump to a symbol in the same ISA mode. */ | |
15136 | ||
15137 | static bfd_boolean | |
15138 | fix_bad_same_mode_jalx_p (fixS *fixP) | |
15139 | { | |
15140 | unsigned long opcode; | |
15141 | int other; | |
15142 | char *buf; | |
15143 | ||
15144 | if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) | |
15145 | return FALSE; | |
15146 | ||
15147 | other = S_GET_OTHER (fixP->fx_addsy); | |
15148 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; | |
15149 | opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 26; | |
15150 | switch (fixP->fx_r_type) | |
15151 | { | |
15152 | case BFD_RELOC_MIPS_JMP: | |
15153 | return opcode == 0x1d && !ELF_ST_IS_COMPRESSED (other); | |
15154 | case BFD_RELOC_MIPS16_JMP: | |
15155 | return opcode == 0x07 && ELF_ST_IS_COMPRESSED (other); | |
15156 | case BFD_RELOC_MICROMIPS_JMP: | |
15157 | return opcode == 0x3c && ELF_ST_IS_COMPRESSED (other); | |
15158 | default: | |
15159 | return FALSE; | |
15160 | } | |
15161 | } | |
15162 | ||
15163 | /* Return TRUE if the instruction pointed to by FIXP is an invalid jump | |
15164 | to a symbol whose value plus addend is not aligned according to the | |
15165 | ultimate (after linker relaxation) jump instruction's immediate field | |
15166 | requirement, either to (1 << SHIFT), or, for jumps from microMIPS to | |
15167 | regular MIPS code, to (1 << 2). */ | |
15168 | ||
15169 | static bfd_boolean | |
15170 | fix_bad_misaligned_jump_p (fixS *fixP, int shift) | |
15171 | { | |
15172 | bfd_boolean micro_to_mips_p; | |
15173 | valueT val; | |
15174 | int other; | |
15175 | ||
15176 | if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) | |
15177 | return FALSE; | |
15178 | ||
15179 | other = S_GET_OTHER (fixP->fx_addsy); | |
15180 | val = S_GET_VALUE (fixP->fx_addsy) | ELF_ST_IS_COMPRESSED (other); | |
15181 | val += fixP->fx_offset; | |
15182 | micro_to_mips_p = (fixP->fx_r_type == BFD_RELOC_MICROMIPS_JMP | |
15183 | && !ELF_ST_IS_MICROMIPS (other)); | |
15184 | return ((val & ((1 << (micro_to_mips_p ? 2 : shift)) - 1)) | |
15185 | != ELF_ST_IS_COMPRESSED (other)); | |
15186 | } | |
15187 | ||
15188 | /* Return TRUE if the instruction pointed to by FIXP is an invalid branch | |
15189 | to a symbol whose annotation indicates another ISA mode. For absolute | |
a6ebf616 MR |
15190 | symbols check the ISA bit instead. |
15191 | ||
15192 | We accept BFD_RELOC_16_PCREL_S2 relocations against MIPS16 and microMIPS | |
15193 | symbols or BFD_RELOC_MICROMIPS_16_PCREL_S1 relocations against regular | |
15194 | MIPS symbols and associated with BAL instructions as these instructions | |
15195 | may be be converted to JALX by the linker. */ | |
9d862524 MR |
15196 | |
15197 | static bfd_boolean | |
15198 | fix_bad_cross_mode_branch_p (fixS *fixP) | |
15199 | { | |
15200 | bfd_boolean absolute_p; | |
15201 | unsigned long opcode; | |
15202 | asection *symsec; | |
15203 | valueT val; | |
15204 | int other; | |
15205 | char *buf; | |
15206 | ||
8b10b0b3 MR |
15207 | if (mips_ignore_branch_isa) |
15208 | return FALSE; | |
15209 | ||
9d862524 MR |
15210 | if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) |
15211 | return FALSE; | |
15212 | ||
15213 | symsec = S_GET_SEGMENT (fixP->fx_addsy); | |
15214 | absolute_p = bfd_is_abs_section (symsec); | |
15215 | ||
15216 | val = S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset; | |
15217 | other = S_GET_OTHER (fixP->fx_addsy); | |
15218 | ||
15219 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; | |
15220 | opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 16; | |
15221 | switch (fixP->fx_r_type) | |
15222 | { | |
15223 | case BFD_RELOC_16_PCREL_S2: | |
a6ebf616 MR |
15224 | return ((absolute_p ? val & 1 : ELF_ST_IS_COMPRESSED (other)) |
15225 | && opcode != 0x0411); | |
15226 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15227 | return ((absolute_p ? !(val & 1) : !ELF_ST_IS_MICROMIPS (other)) | |
15228 | && opcode != 0x4060); | |
9d862524 MR |
15229 | case BFD_RELOC_MIPS_21_PCREL_S2: |
15230 | case BFD_RELOC_MIPS_26_PCREL_S2: | |
15231 | return absolute_p ? val & 1 : ELF_ST_IS_COMPRESSED (other); | |
15232 | case BFD_RELOC_MIPS16_16_PCREL_S1: | |
15233 | return absolute_p ? !(val & 1) : !ELF_ST_IS_MIPS16 (other); | |
15234 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: | |
15235 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
9d862524 MR |
15236 | return absolute_p ? !(val & 1) : !ELF_ST_IS_MICROMIPS (other); |
15237 | default: | |
15238 | abort (); | |
15239 | } | |
15240 | } | |
15241 | ||
15242 | /* Return TRUE if the symbol plus addend associated with a regular MIPS | |
15243 | branch instruction pointed to by FIXP is not aligned according to the | |
15244 | branch instruction's immediate field requirement. We need the addend | |
15245 | to preserve the ISA bit and also the sum must not have bit 2 set. We | |
15246 | must explicitly OR in the ISA bit from symbol annotation as the bit | |
15247 | won't be set in the symbol's value then. */ | |
15248 | ||
15249 | static bfd_boolean | |
15250 | fix_bad_misaligned_branch_p (fixS *fixP) | |
15251 | { | |
15252 | bfd_boolean absolute_p; | |
15253 | asection *symsec; | |
15254 | valueT isa_bit; | |
15255 | valueT val; | |
15256 | valueT off; | |
15257 | int other; | |
15258 | ||
15259 | if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) | |
15260 | return FALSE; | |
15261 | ||
15262 | symsec = S_GET_SEGMENT (fixP->fx_addsy); | |
15263 | absolute_p = bfd_is_abs_section (symsec); | |
15264 | ||
15265 | val = S_GET_VALUE (fixP->fx_addsy); | |
15266 | other = S_GET_OTHER (fixP->fx_addsy); | |
15267 | off = fixP->fx_offset; | |
15268 | ||
15269 | isa_bit = absolute_p ? (val + off) & 1 : ELF_ST_IS_COMPRESSED (other); | |
15270 | val |= ELF_ST_IS_COMPRESSED (other); | |
15271 | val += off; | |
15272 | return (val & 0x3) != isa_bit; | |
15273 | } | |
15274 | ||
15275 | /* Make the necessary checks on a regular MIPS branch pointed to by FIXP | |
15276 | and its calculated value VAL. */ | |
15277 | ||
15278 | static void | |
15279 | fix_validate_branch (fixS *fixP, valueT val) | |
15280 | { | |
15281 | if (fixP->fx_done && (val & 0x3) != 0) | |
15282 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15283 | _("branch to misaligned address (0x%lx)"), | |
15284 | (long) (val + md_pcrel_from (fixP))); | |
15285 | else if (fix_bad_cross_mode_branch_p (fixP)) | |
15286 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15287 | _("branch to a symbol in another ISA mode")); | |
15288 | else if (fix_bad_misaligned_branch_p (fixP)) | |
15289 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15290 | _("branch to misaligned address (0x%lx)"), | |
15291 | (long) (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset)); | |
15292 | else if (HAVE_IN_PLACE_ADDENDS && (fixP->fx_offset & 0x3) != 0) | |
15293 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15294 | _("cannot encode misaligned addend " | |
15295 | "in the relocatable field (0x%lx)"), | |
15296 | (long) fixP->fx_offset); | |
15297 | } | |
15298 | ||
252b5132 RH |
15299 | /* Apply a fixup to the object file. */ |
15300 | ||
94f592af | 15301 | void |
55cf6793 | 15302 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 15303 | { |
4d68580a | 15304 | char *buf; |
b886a2ab | 15305 | unsigned long insn; |
a7ebbfdf | 15306 | reloc_howto_type *howto; |
252b5132 | 15307 | |
d56a8dda RS |
15308 | if (fixP->fx_pcrel) |
15309 | switch (fixP->fx_r_type) | |
15310 | { | |
15311 | case BFD_RELOC_16_PCREL_S2: | |
c9775dde | 15312 | case BFD_RELOC_MIPS16_16_PCREL_S1: |
d56a8dda RS |
15313 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15314 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15315 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15316 | case BFD_RELOC_32_PCREL: | |
7361da2c AB |
15317 | case BFD_RELOC_MIPS_21_PCREL_S2: |
15318 | case BFD_RELOC_MIPS_26_PCREL_S2: | |
15319 | case BFD_RELOC_MIPS_18_PCREL_S3: | |
15320 | case BFD_RELOC_MIPS_19_PCREL_S2: | |
15321 | case BFD_RELOC_HI16_S_PCREL: | |
15322 | case BFD_RELOC_LO16_PCREL: | |
d56a8dda RS |
15323 | break; |
15324 | ||
15325 | case BFD_RELOC_32: | |
15326 | fixP->fx_r_type = BFD_RELOC_32_PCREL; | |
15327 | break; | |
15328 | ||
15329 | default: | |
15330 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15331 | _("PC-relative reference to a different section")); | |
15332 | break; | |
15333 | } | |
15334 | ||
15335 | /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations | |
15336 | that have no MIPS ELF equivalent. */ | |
15337 | if (fixP->fx_r_type != BFD_RELOC_8) | |
15338 | { | |
15339 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
15340 | if (!howto) | |
15341 | return; | |
15342 | } | |
65551fa4 | 15343 | |
df58fc94 RS |
15344 | gas_assert (fixP->fx_size == 2 |
15345 | || fixP->fx_size == 4 | |
d56a8dda | 15346 | || fixP->fx_r_type == BFD_RELOC_8 |
90ecf173 MR |
15347 | || fixP->fx_r_type == BFD_RELOC_16 |
15348 | || fixP->fx_r_type == BFD_RELOC_64 | |
15349 | || fixP->fx_r_type == BFD_RELOC_CTOR | |
15350 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
df58fc94 | 15351 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB |
90ecf173 MR |
15352 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
15353 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY | |
2f0c68f2 CM |
15354 | || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64 |
15355 | || fixP->fx_r_type == BFD_RELOC_NONE); | |
252b5132 | 15356 | |
4d68580a | 15357 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; |
252b5132 | 15358 | |
b1dca8ee RS |
15359 | /* Don't treat parts of a composite relocation as done. There are two |
15360 | reasons for this: | |
15361 | ||
15362 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
15363 | should nevertheless be emitted if the first part is. | |
15364 | ||
15365 | (2) In normal usage, composite relocations are never assembly-time | |
15366 | constants. The easiest way of dealing with the pathological | |
15367 | exceptions is to generate a relocation against STN_UNDEF and | |
15368 | leave everything up to the linker. */ | |
3994f87e | 15369 | if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0) |
252b5132 RH |
15370 | fixP->fx_done = 1; |
15371 | ||
15372 | switch (fixP->fx_r_type) | |
15373 | { | |
3f98094e DJ |
15374 | case BFD_RELOC_MIPS_TLS_GD: |
15375 | case BFD_RELOC_MIPS_TLS_LDM: | |
741d6ea8 JM |
15376 | case BFD_RELOC_MIPS_TLS_DTPREL32: |
15377 | case BFD_RELOC_MIPS_TLS_DTPREL64: | |
3f98094e DJ |
15378 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: |
15379 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
15380 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
d0f13682 CLT |
15381 | case BFD_RELOC_MIPS_TLS_TPREL32: |
15382 | case BFD_RELOC_MIPS_TLS_TPREL64: | |
3f98094e DJ |
15383 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: |
15384 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
df58fc94 RS |
15385 | case BFD_RELOC_MICROMIPS_TLS_GD: |
15386 | case BFD_RELOC_MICROMIPS_TLS_LDM: | |
15387 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16: | |
15388 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16: | |
15389 | case BFD_RELOC_MICROMIPS_TLS_GOTTPREL: | |
15390 | case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16: | |
15391 | case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16: | |
d0f13682 CLT |
15392 | case BFD_RELOC_MIPS16_TLS_GD: |
15393 | case BFD_RELOC_MIPS16_TLS_LDM: | |
15394 | case BFD_RELOC_MIPS16_TLS_DTPREL_HI16: | |
15395 | case BFD_RELOC_MIPS16_TLS_DTPREL_LO16: | |
15396 | case BFD_RELOC_MIPS16_TLS_GOTTPREL: | |
15397 | case BFD_RELOC_MIPS16_TLS_TPREL_HI16: | |
15398 | case BFD_RELOC_MIPS16_TLS_TPREL_LO16: | |
4512dafa MR |
15399 | if (fixP->fx_addsy) |
15400 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
15401 | else | |
15402 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15403 | _("TLS relocation against a constant")); | |
15404 | break; | |
3f98094e | 15405 | |
252b5132 | 15406 | case BFD_RELOC_MIPS_JMP: |
9d862524 MR |
15407 | case BFD_RELOC_MIPS16_JMP: |
15408 | case BFD_RELOC_MICROMIPS_JMP: | |
15409 | { | |
15410 | int shift; | |
15411 | ||
15412 | gas_assert (!fixP->fx_done); | |
15413 | ||
15414 | /* Shift is 2, unusually, for microMIPS JALX. */ | |
15415 | if (fixP->fx_r_type == BFD_RELOC_MICROMIPS_JMP | |
15416 | && (read_compressed_insn (buf, 4) >> 26) != 0x3c) | |
15417 | shift = 1; | |
15418 | else | |
15419 | shift = 2; | |
15420 | ||
15421 | if (fix_bad_cross_mode_jump_p (fixP)) | |
15422 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15423 | _("jump to a symbol in another ISA mode")); | |
15424 | else if (fix_bad_same_mode_jalx_p (fixP)) | |
15425 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15426 | _("JALX to a symbol in the same ISA mode")); | |
15427 | else if (fix_bad_misaligned_jump_p (fixP, shift)) | |
15428 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15429 | _("jump to misaligned address (0x%lx)"), | |
15430 | (long) (S_GET_VALUE (fixP->fx_addsy) | |
15431 | + fixP->fx_offset)); | |
15432 | else if (HAVE_IN_PLACE_ADDENDS | |
15433 | && (fixP->fx_offset & ((1 << shift) - 1)) != 0) | |
15434 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15435 | _("cannot encode misaligned addend " | |
15436 | "in the relocatable field (0x%lx)"), | |
15437 | (long) fixP->fx_offset); | |
15438 | } | |
15439 | /* Fall through. */ | |
15440 | ||
e369bcce TS |
15441 | case BFD_RELOC_MIPS_SHIFT5: |
15442 | case BFD_RELOC_MIPS_SHIFT6: | |
15443 | case BFD_RELOC_MIPS_GOT_DISP: | |
15444 | case BFD_RELOC_MIPS_GOT_PAGE: | |
15445 | case BFD_RELOC_MIPS_GOT_OFST: | |
15446 | case BFD_RELOC_MIPS_SUB: | |
15447 | case BFD_RELOC_MIPS_INSERT_A: | |
15448 | case BFD_RELOC_MIPS_INSERT_B: | |
15449 | case BFD_RELOC_MIPS_DELETE: | |
15450 | case BFD_RELOC_MIPS_HIGHEST: | |
15451 | case BFD_RELOC_MIPS_HIGHER: | |
15452 | case BFD_RELOC_MIPS_SCN_DISP: | |
15453 | case BFD_RELOC_MIPS_REL16: | |
15454 | case BFD_RELOC_MIPS_RELGOT: | |
15455 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
15456 | case BFD_RELOC_HI16: |
15457 | case BFD_RELOC_HI16_S: | |
b886a2ab | 15458 | case BFD_RELOC_LO16: |
cdf6fd85 | 15459 | case BFD_RELOC_GPREL16: |
252b5132 RH |
15460 | case BFD_RELOC_MIPS_LITERAL: |
15461 | case BFD_RELOC_MIPS_CALL16: | |
15462 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 15463 | case BFD_RELOC_GPREL32: |
252b5132 RH |
15464 | case BFD_RELOC_MIPS_GOT_HI16: |
15465 | case BFD_RELOC_MIPS_GOT_LO16: | |
15466 | case BFD_RELOC_MIPS_CALL_HI16: | |
15467 | case BFD_RELOC_MIPS_CALL_LO16: | |
41947d9e MR |
15468 | case BFD_RELOC_HI16_S_PCREL: |
15469 | case BFD_RELOC_LO16_PCREL: | |
252b5132 | 15470 | case BFD_RELOC_MIPS16_GPREL: |
738e5348 RS |
15471 | case BFD_RELOC_MIPS16_GOT16: |
15472 | case BFD_RELOC_MIPS16_CALL16: | |
d6f16593 MR |
15473 | case BFD_RELOC_MIPS16_HI16: |
15474 | case BFD_RELOC_MIPS16_HI16_S: | |
b886a2ab | 15475 | case BFD_RELOC_MIPS16_LO16: |
df58fc94 RS |
15476 | case BFD_RELOC_MICROMIPS_GOT_DISP: |
15477 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
15478 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
15479 | case BFD_RELOC_MICROMIPS_SUB: | |
15480 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
15481 | case BFD_RELOC_MICROMIPS_HIGHER: | |
15482 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
15483 | case BFD_RELOC_MICROMIPS_JALR: | |
15484 | case BFD_RELOC_MICROMIPS_HI16: | |
15485 | case BFD_RELOC_MICROMIPS_HI16_S: | |
b886a2ab | 15486 | case BFD_RELOC_MICROMIPS_LO16: |
df58fc94 RS |
15487 | case BFD_RELOC_MICROMIPS_GPREL16: |
15488 | case BFD_RELOC_MICROMIPS_LITERAL: | |
15489 | case BFD_RELOC_MICROMIPS_CALL16: | |
15490 | case BFD_RELOC_MICROMIPS_GOT16: | |
15491 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
15492 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
15493 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
15494 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
067ec077 | 15495 | case BFD_RELOC_MIPS_EH: |
b886a2ab RS |
15496 | if (fixP->fx_done) |
15497 | { | |
15498 | offsetT value; | |
15499 | ||
15500 | if (calculate_reloc (fixP->fx_r_type, *valP, &value)) | |
15501 | { | |
15502 | insn = read_reloc_insn (buf, fixP->fx_r_type); | |
15503 | if (mips16_reloc_p (fixP->fx_r_type)) | |
15504 | insn |= mips16_immed_extend (value, 16); | |
15505 | else | |
15506 | insn |= (value & 0xffff); | |
15507 | write_reloc_insn (buf, fixP->fx_r_type, insn); | |
15508 | } | |
15509 | else | |
15510 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
1661c76c | 15511 | _("unsupported constant in relocation")); |
b886a2ab | 15512 | } |
252b5132 RH |
15513 | break; |
15514 | ||
252b5132 RH |
15515 | case BFD_RELOC_64: |
15516 | /* This is handled like BFD_RELOC_32, but we output a sign | |
15517 | extended value if we are only 32 bits. */ | |
3e722fb5 | 15518 | if (fixP->fx_done) |
252b5132 RH |
15519 | { |
15520 | if (8 <= sizeof (valueT)) | |
4d68580a | 15521 | md_number_to_chars (buf, *valP, 8); |
252b5132 RH |
15522 | else |
15523 | { | |
a7ebbfdf | 15524 | valueT hiv; |
252b5132 | 15525 | |
a7ebbfdf | 15526 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
15527 | hiv = 0xffffffff; |
15528 | else | |
15529 | hiv = 0; | |
4d68580a RS |
15530 | md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4); |
15531 | md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4); | |
252b5132 RH |
15532 | } |
15533 | } | |
15534 | break; | |
15535 | ||
056350c6 | 15536 | case BFD_RELOC_RVA: |
252b5132 | 15537 | case BFD_RELOC_32: |
b47468a6 | 15538 | case BFD_RELOC_32_PCREL: |
252b5132 | 15539 | case BFD_RELOC_16: |
d56a8dda | 15540 | case BFD_RELOC_8: |
252b5132 | 15541 | /* If we are deleting this reloc entry, we must fill in the |
54f4ddb3 TS |
15542 | value now. This can happen if we have a .word which is not |
15543 | resolved when it appears but is later defined. */ | |
252b5132 | 15544 | if (fixP->fx_done) |
4d68580a | 15545 | md_number_to_chars (buf, *valP, fixP->fx_size); |
252b5132 RH |
15546 | break; |
15547 | ||
7361da2c | 15548 | case BFD_RELOC_MIPS_21_PCREL_S2: |
9d862524 | 15549 | fix_validate_branch (fixP, *valP); |
41947d9e MR |
15550 | if (!fixP->fx_done) |
15551 | break; | |
15552 | ||
15553 | if (*valP + 0x400000 <= 0x7fffff) | |
15554 | { | |
15555 | insn = read_insn (buf); | |
15556 | insn |= (*valP >> 2) & 0x1fffff; | |
15557 | write_insn (buf, insn); | |
15558 | } | |
15559 | else | |
15560 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15561 | _("branch out of range")); | |
15562 | break; | |
15563 | ||
7361da2c | 15564 | case BFD_RELOC_MIPS_26_PCREL_S2: |
9d862524 | 15565 | fix_validate_branch (fixP, *valP); |
41947d9e MR |
15566 | if (!fixP->fx_done) |
15567 | break; | |
7361da2c | 15568 | |
41947d9e MR |
15569 | if (*valP + 0x8000000 <= 0xfffffff) |
15570 | { | |
15571 | insn = read_insn (buf); | |
15572 | insn |= (*valP >> 2) & 0x3ffffff; | |
15573 | write_insn (buf, insn); | |
15574 | } | |
15575 | else | |
15576 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15577 | _("branch out of range")); | |
7361da2c AB |
15578 | break; |
15579 | ||
15580 | case BFD_RELOC_MIPS_18_PCREL_S3: | |
717ba204 | 15581 | if (fixP->fx_addsy && (S_GET_VALUE (fixP->fx_addsy) & 0x7) != 0) |
7361da2c | 15582 | as_bad_where (fixP->fx_file, fixP->fx_line, |
0866e94c MF |
15583 | _("PC-relative access using misaligned symbol (%lx)"), |
15584 | (long) S_GET_VALUE (fixP->fx_addsy)); | |
15585 | if ((fixP->fx_offset & 0x7) != 0) | |
15586 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15587 | _("PC-relative access using misaligned offset (%lx)"), | |
15588 | (long) fixP->fx_offset); | |
41947d9e MR |
15589 | if (!fixP->fx_done) |
15590 | break; | |
7361da2c | 15591 | |
41947d9e MR |
15592 | if (*valP + 0x100000 <= 0x1fffff) |
15593 | { | |
15594 | insn = read_insn (buf); | |
15595 | insn |= (*valP >> 3) & 0x3ffff; | |
15596 | write_insn (buf, insn); | |
15597 | } | |
15598 | else | |
15599 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15600 | _("PC-relative access out of range")); | |
7361da2c AB |
15601 | break; |
15602 | ||
15603 | case BFD_RELOC_MIPS_19_PCREL_S2: | |
15604 | if ((*valP & 0x3) != 0) | |
15605 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15606 | _("PC-relative access to misaligned address (%lx)"), | |
717ba204 | 15607 | (long) *valP); |
41947d9e MR |
15608 | if (!fixP->fx_done) |
15609 | break; | |
7361da2c | 15610 | |
41947d9e MR |
15611 | if (*valP + 0x100000 <= 0x1fffff) |
15612 | { | |
15613 | insn = read_insn (buf); | |
15614 | insn |= (*valP >> 2) & 0x7ffff; | |
15615 | write_insn (buf, insn); | |
15616 | } | |
15617 | else | |
15618 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15619 | _("PC-relative access out of range")); | |
7361da2c AB |
15620 | break; |
15621 | ||
252b5132 | 15622 | case BFD_RELOC_16_PCREL_S2: |
9d862524 | 15623 | fix_validate_branch (fixP, *valP); |
cb56d3d3 | 15624 | |
54f4ddb3 TS |
15625 | /* We need to save the bits in the instruction since fixup_segment() |
15626 | might be deleting the relocation entry (i.e., a branch within | |
15627 | the current segment). */ | |
a7ebbfdf | 15628 | if (! fixP->fx_done) |
bb2d6cd7 | 15629 | break; |
252b5132 | 15630 | |
54f4ddb3 | 15631 | /* Update old instruction data. */ |
4d68580a | 15632 | insn = read_insn (buf); |
252b5132 | 15633 | |
a7ebbfdf TS |
15634 | if (*valP + 0x20000 <= 0x3ffff) |
15635 | { | |
15636 | insn |= (*valP >> 2) & 0xffff; | |
4d68580a | 15637 | write_insn (buf, insn); |
a7ebbfdf | 15638 | } |
ce8ad872 | 15639 | else if (fixP->fx_tcbit2 |
a7ebbfdf TS |
15640 | && fixP->fx_done |
15641 | && fixP->fx_frag->fr_address >= text_section->vma | |
15642 | && (fixP->fx_frag->fr_address | |
587aac4e | 15643 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
15644 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
15645 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
15646 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
15647 | { |
15648 | /* The branch offset is too large. If this is an | |
15649 | unconditional branch, and we are not generating PIC code, | |
15650 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
15651 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
15652 | insn = 0x0c000000; /* jal */ | |
252b5132 | 15653 | else |
a7ebbfdf TS |
15654 | insn = 0x08000000; /* j */ |
15655 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
15656 | fixP->fx_done = 0; | |
15657 | fixP->fx_addsy = section_symbol (text_section); | |
15658 | *valP += md_pcrel_from (fixP); | |
4d68580a | 15659 | write_insn (buf, insn); |
a7ebbfdf TS |
15660 | } |
15661 | else | |
15662 | { | |
15663 | /* If we got here, we have branch-relaxation disabled, | |
15664 | and there's nothing we can do to fix this instruction | |
15665 | without turning it into a longer sequence. */ | |
15666 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
1661c76c | 15667 | _("branch out of range")); |
252b5132 | 15668 | } |
252b5132 RH |
15669 | break; |
15670 | ||
c9775dde | 15671 | case BFD_RELOC_MIPS16_16_PCREL_S1: |
df58fc94 RS |
15672 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15673 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15674 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
96e9ba5f | 15675 | gas_assert (!fixP->fx_done); |
9d862524 MR |
15676 | if (fix_bad_cross_mode_branch_p (fixP)) |
15677 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15678 | _("branch to a symbol in another ISA mode")); | |
15679 | else if (fixP->fx_addsy | |
15680 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) | |
15681 | && !bfd_is_abs_section (S_GET_SEGMENT (fixP->fx_addsy)) | |
15682 | && (fixP->fx_offset & 0x1) != 0) | |
15683 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15684 | _("branch to misaligned address (0x%lx)"), | |
15685 | (long) (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset)); | |
15686 | else if (HAVE_IN_PLACE_ADDENDS && (fixP->fx_offset & 0x1) != 0) | |
15687 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15688 | _("cannot encode misaligned addend " | |
15689 | "in the relocatable field (0x%lx)"), | |
15690 | (long) fixP->fx_offset); | |
df58fc94 RS |
15691 | break; |
15692 | ||
252b5132 RH |
15693 | case BFD_RELOC_VTABLE_INHERIT: |
15694 | fixP->fx_done = 0; | |
15695 | if (fixP->fx_addsy | |
15696 | && !S_IS_DEFINED (fixP->fx_addsy) | |
15697 | && !S_IS_WEAK (fixP->fx_addsy)) | |
15698 | S_SET_WEAK (fixP->fx_addsy); | |
15699 | break; | |
15700 | ||
2f0c68f2 | 15701 | case BFD_RELOC_NONE: |
252b5132 RH |
15702 | case BFD_RELOC_VTABLE_ENTRY: |
15703 | fixP->fx_done = 0; | |
15704 | break; | |
15705 | ||
15706 | default: | |
b37df7c4 | 15707 | abort (); |
252b5132 | 15708 | } |
a7ebbfdf TS |
15709 | |
15710 | /* Remember value for tc_gen_reloc. */ | |
15711 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
15712 | } |
15713 | ||
252b5132 | 15714 | static symbolS * |
17a2f251 | 15715 | get_symbol (void) |
252b5132 RH |
15716 | { |
15717 | int c; | |
15718 | char *name; | |
15719 | symbolS *p; | |
15720 | ||
d02603dc | 15721 | c = get_symbol_name (&name); |
252b5132 | 15722 | p = (symbolS *) symbol_find_or_make (name); |
d02603dc | 15723 | (void) restore_line_pointer (c); |
252b5132 RH |
15724 | return p; |
15725 | } | |
15726 | ||
742a56fe RS |
15727 | /* Align the current frag to a given power of two. If a particular |
15728 | fill byte should be used, FILL points to an integer that contains | |
15729 | that byte, otherwise FILL is null. | |
15730 | ||
462427c4 RS |
15731 | This function used to have the comment: |
15732 | ||
15733 | The MIPS assembler also automatically adjusts any preceding label. | |
15734 | ||
15735 | The implementation therefore applied the adjustment to a maximum of | |
15736 | one label. However, other label adjustments are applied to batches | |
15737 | of labels, and adjusting just one caused problems when new labels | |
15738 | were added for the sake of debugging or unwind information. | |
15739 | We therefore adjust all preceding labels (given as LABELS) instead. */ | |
252b5132 RH |
15740 | |
15741 | static void | |
462427c4 | 15742 | mips_align (int to, int *fill, struct insn_label_list *labels) |
252b5132 | 15743 | { |
7d10b47d | 15744 | mips_emit_delays (); |
df58fc94 | 15745 | mips_record_compressed_mode (); |
742a56fe RS |
15746 | if (fill == NULL && subseg_text_p (now_seg)) |
15747 | frag_align_code (to, 0); | |
15748 | else | |
15749 | frag_align (to, fill ? *fill : 0, 0); | |
252b5132 | 15750 | record_alignment (now_seg, to); |
462427c4 | 15751 | mips_move_labels (labels, FALSE); |
252b5132 RH |
15752 | } |
15753 | ||
15754 | /* Align to a given power of two. .align 0 turns off the automatic | |
15755 | alignment used by the data creating pseudo-ops. */ | |
15756 | ||
15757 | static void | |
17a2f251 | 15758 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 | 15759 | { |
742a56fe | 15760 | int temp, fill_value, *fill_ptr; |
49954fb4 | 15761 | long max_alignment = 28; |
252b5132 | 15762 | |
54f4ddb3 | 15763 | /* o Note that the assembler pulls down any immediately preceding label |
252b5132 | 15764 | to the aligned address. |
54f4ddb3 | 15765 | o It's not documented but auto alignment is reinstated by |
252b5132 | 15766 | a .align pseudo instruction. |
54f4ddb3 | 15767 | o Note also that after auto alignment is turned off the mips assembler |
252b5132 | 15768 | issues an error on attempt to assemble an improperly aligned data item. |
54f4ddb3 | 15769 | We don't. */ |
252b5132 RH |
15770 | |
15771 | temp = get_absolute_expression (); | |
15772 | if (temp > max_alignment) | |
1661c76c | 15773 | as_bad (_("alignment too large, %d assumed"), temp = max_alignment); |
252b5132 RH |
15774 | else if (temp < 0) |
15775 | { | |
1661c76c | 15776 | as_warn (_("alignment negative, 0 assumed")); |
252b5132 RH |
15777 | temp = 0; |
15778 | } | |
15779 | if (*input_line_pointer == ',') | |
15780 | { | |
f9419b05 | 15781 | ++input_line_pointer; |
742a56fe RS |
15782 | fill_value = get_absolute_expression (); |
15783 | fill_ptr = &fill_value; | |
252b5132 RH |
15784 | } |
15785 | else | |
742a56fe | 15786 | fill_ptr = 0; |
252b5132 RH |
15787 | if (temp) |
15788 | { | |
a8dbcb85 TS |
15789 | segment_info_type *si = seg_info (now_seg); |
15790 | struct insn_label_list *l = si->label_list; | |
54f4ddb3 | 15791 | /* Auto alignment should be switched on by next section change. */ |
252b5132 | 15792 | auto_align = 1; |
462427c4 | 15793 | mips_align (temp, fill_ptr, l); |
252b5132 RH |
15794 | } |
15795 | else | |
15796 | { | |
15797 | auto_align = 0; | |
15798 | } | |
15799 | ||
15800 | demand_empty_rest_of_line (); | |
15801 | } | |
15802 | ||
252b5132 | 15803 | static void |
17a2f251 | 15804 | s_change_sec (int sec) |
252b5132 RH |
15805 | { |
15806 | segT seg; | |
15807 | ||
252b5132 RH |
15808 | /* The ELF backend needs to know that we are changing sections, so |
15809 | that .previous works correctly. We could do something like check | |
b6ff326e | 15810 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
15811 | as it would not be appropriate to use it in the section changing |
15812 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
15813 | This should be cleaner, somehow. */ | |
f3ded42a | 15814 | obj_elf_section_change_hook (); |
252b5132 | 15815 | |
7d10b47d | 15816 | mips_emit_delays (); |
6a32d874 | 15817 | |
252b5132 RH |
15818 | switch (sec) |
15819 | { | |
15820 | case 't': | |
15821 | s_text (0); | |
15822 | break; | |
15823 | case 'd': | |
15824 | s_data (0); | |
15825 | break; | |
15826 | case 'b': | |
15827 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
15828 | demand_empty_rest_of_line (); | |
15829 | break; | |
15830 | ||
15831 | case 'r': | |
4d0d148d TS |
15832 | seg = subseg_new (RDATA_SECTION_NAME, |
15833 | (subsegT) get_absolute_expression ()); | |
f3ded42a RS |
15834 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
15835 | | SEC_READONLY | SEC_RELOC | |
15836 | | SEC_DATA)); | |
15837 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
15838 | record_alignment (seg, 4); | |
4d0d148d | 15839 | demand_empty_rest_of_line (); |
252b5132 RH |
15840 | break; |
15841 | ||
15842 | case 's': | |
4d0d148d | 15843 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
f3ded42a RS |
15844 | bfd_set_section_flags (stdoutput, seg, |
15845 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
15846 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
15847 | record_alignment (seg, 4); | |
4d0d148d TS |
15848 | demand_empty_rest_of_line (); |
15849 | break; | |
998b3c36 MR |
15850 | |
15851 | case 'B': | |
15852 | seg = subseg_new (".sbss", (subsegT) get_absolute_expression ()); | |
f3ded42a RS |
15853 | bfd_set_section_flags (stdoutput, seg, SEC_ALLOC); |
15854 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
15855 | record_alignment (seg, 4); | |
998b3c36 MR |
15856 | demand_empty_rest_of_line (); |
15857 | break; | |
252b5132 RH |
15858 | } |
15859 | ||
15860 | auto_align = 1; | |
15861 | } | |
b34976b6 | 15862 | |
cca86cc8 | 15863 | void |
17a2f251 | 15864 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 15865 | { |
d02603dc | 15866 | char *saved_ilp; |
cca86cc8 | 15867 | char *section_name; |
d02603dc | 15868 | char c, endc; |
684022ea | 15869 | char next_c = 0; |
cca86cc8 SC |
15870 | int section_type; |
15871 | int section_flag; | |
15872 | int section_entry_size; | |
15873 | int section_alignment; | |
b34976b6 | 15874 | |
d02603dc NC |
15875 | saved_ilp = input_line_pointer; |
15876 | endc = get_symbol_name (§ion_name); | |
15877 | c = (endc == '"' ? input_line_pointer[1] : endc); | |
a816d1ed | 15878 | if (c) |
d02603dc | 15879 | next_c = input_line_pointer [(endc == '"' ? 2 : 1)]; |
cca86cc8 | 15880 | |
4cf0dd0d TS |
15881 | /* Do we have .section Name<,"flags">? */ |
15882 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 15883 | { |
d02603dc NC |
15884 | /* Just after name is now '\0'. */ |
15885 | (void) restore_line_pointer (endc); | |
15886 | input_line_pointer = saved_ilp; | |
cca86cc8 SC |
15887 | obj_elf_section (ignore); |
15888 | return; | |
15889 | } | |
d02603dc NC |
15890 | |
15891 | section_name = xstrdup (section_name); | |
15892 | c = restore_line_pointer (endc); | |
15893 | ||
cca86cc8 SC |
15894 | input_line_pointer++; |
15895 | ||
15896 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
15897 | if (c == ',') | |
15898 | section_type = get_absolute_expression (); | |
15899 | else | |
15900 | section_type = 0; | |
d02603dc | 15901 | |
cca86cc8 SC |
15902 | if (*input_line_pointer++ == ',') |
15903 | section_flag = get_absolute_expression (); | |
15904 | else | |
15905 | section_flag = 0; | |
d02603dc | 15906 | |
cca86cc8 SC |
15907 | if (*input_line_pointer++ == ',') |
15908 | section_entry_size = get_absolute_expression (); | |
15909 | else | |
15910 | section_entry_size = 0; | |
d02603dc | 15911 | |
cca86cc8 SC |
15912 | if (*input_line_pointer++ == ',') |
15913 | section_alignment = get_absolute_expression (); | |
15914 | else | |
15915 | section_alignment = 0; | |
d02603dc | 15916 | |
87975d2a AM |
15917 | /* FIXME: really ignore? */ |
15918 | (void) section_alignment; | |
cca86cc8 | 15919 | |
8ab8a5c8 RS |
15920 | /* When using the generic form of .section (as implemented by obj-elf.c), |
15921 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
15922 | traditionally had to fall back on the more common @progbits instead. | |
15923 | ||
15924 | There's nothing really harmful in this, since bfd will correct | |
15925 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
708587a4 | 15926 | means that, for backwards compatibility, the special_section entries |
8ab8a5c8 RS |
15927 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. |
15928 | ||
15929 | Even so, we shouldn't force users of the MIPS .section syntax to | |
15930 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
15931 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
15932 | generic type-checking code. */ | |
15933 | if (section_type == SHT_MIPS_DWARF) | |
15934 | section_type = SHT_PROGBITS; | |
15935 | ||
a91e1603 | 15936 | obj_elf_change_section (section_name, section_type, 0, section_flag, |
cca86cc8 | 15937 | section_entry_size, 0, 0, 0); |
a816d1ed AO |
15938 | |
15939 | if (now_seg->name != section_name) | |
15940 | free (section_name); | |
cca86cc8 | 15941 | } |
252b5132 RH |
15942 | |
15943 | void | |
17a2f251 | 15944 | mips_enable_auto_align (void) |
252b5132 RH |
15945 | { |
15946 | auto_align = 1; | |
15947 | } | |
15948 | ||
15949 | static void | |
17a2f251 | 15950 | s_cons (int log_size) |
252b5132 | 15951 | { |
a8dbcb85 TS |
15952 | segment_info_type *si = seg_info (now_seg); |
15953 | struct insn_label_list *l = si->label_list; | |
252b5132 | 15954 | |
7d10b47d | 15955 | mips_emit_delays (); |
252b5132 | 15956 | if (log_size > 0 && auto_align) |
462427c4 | 15957 | mips_align (log_size, 0, l); |
252b5132 | 15958 | cons (1 << log_size); |
a1facbec | 15959 | mips_clear_insn_labels (); |
252b5132 RH |
15960 | } |
15961 | ||
15962 | static void | |
17a2f251 | 15963 | s_float_cons (int type) |
252b5132 | 15964 | { |
a8dbcb85 TS |
15965 | segment_info_type *si = seg_info (now_seg); |
15966 | struct insn_label_list *l = si->label_list; | |
252b5132 | 15967 | |
7d10b47d | 15968 | mips_emit_delays (); |
252b5132 RH |
15969 | |
15970 | if (auto_align) | |
49309057 ILT |
15971 | { |
15972 | if (type == 'd') | |
462427c4 | 15973 | mips_align (3, 0, l); |
49309057 | 15974 | else |
462427c4 | 15975 | mips_align (2, 0, l); |
49309057 | 15976 | } |
252b5132 | 15977 | |
252b5132 | 15978 | float_cons (type); |
a1facbec | 15979 | mips_clear_insn_labels (); |
252b5132 RH |
15980 | } |
15981 | ||
15982 | /* Handle .globl. We need to override it because on Irix 5 you are | |
15983 | permitted to say | |
15984 | .globl foo .text | |
15985 | where foo is an undefined symbol, to mean that foo should be | |
15986 | considered to be the address of a function. */ | |
15987 | ||
15988 | static void | |
17a2f251 | 15989 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
15990 | { |
15991 | char *name; | |
15992 | int c; | |
15993 | symbolS *symbolP; | |
15994 | flagword flag; | |
15995 | ||
8a06b769 | 15996 | do |
252b5132 | 15997 | { |
d02603dc | 15998 | c = get_symbol_name (&name); |
8a06b769 TS |
15999 | symbolP = symbol_find_or_make (name); |
16000 | S_SET_EXTERNAL (symbolP); | |
16001 | ||
252b5132 | 16002 | *input_line_pointer = c; |
d02603dc | 16003 | SKIP_WHITESPACE_AFTER_NAME (); |
252b5132 | 16004 | |
8a06b769 TS |
16005 | /* On Irix 5, every global symbol that is not explicitly labelled as |
16006 | being a function is apparently labelled as being an object. */ | |
16007 | flag = BSF_OBJECT; | |
252b5132 | 16008 | |
8a06b769 TS |
16009 | if (!is_end_of_line[(unsigned char) *input_line_pointer] |
16010 | && (*input_line_pointer != ',')) | |
16011 | { | |
16012 | char *secname; | |
16013 | asection *sec; | |
16014 | ||
d02603dc | 16015 | c = get_symbol_name (&secname); |
8a06b769 TS |
16016 | sec = bfd_get_section_by_name (stdoutput, secname); |
16017 | if (sec == NULL) | |
16018 | as_bad (_("%s: no such section"), secname); | |
d02603dc | 16019 | (void) restore_line_pointer (c); |
8a06b769 TS |
16020 | |
16021 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
16022 | flag = BSF_FUNCTION; | |
16023 | } | |
16024 | ||
16025 | symbol_get_bfdsym (symbolP)->flags |= flag; | |
16026 | ||
16027 | c = *input_line_pointer; | |
16028 | if (c == ',') | |
16029 | { | |
16030 | input_line_pointer++; | |
16031 | SKIP_WHITESPACE (); | |
16032 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
16033 | c = '\n'; | |
16034 | } | |
16035 | } | |
16036 | while (c == ','); | |
252b5132 | 16037 | |
252b5132 RH |
16038 | demand_empty_rest_of_line (); |
16039 | } | |
16040 | ||
16041 | static void | |
17a2f251 | 16042 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16043 | { |
16044 | char *opt; | |
16045 | char c; | |
16046 | ||
d02603dc | 16047 | c = get_symbol_name (&opt); |
252b5132 RH |
16048 | |
16049 | if (*opt == 'O') | |
16050 | { | |
16051 | /* FIXME: What does this mean? */ | |
16052 | } | |
41a1578e | 16053 | else if (strncmp (opt, "pic", 3) == 0 && ISDIGIT (opt[3]) && opt[4] == '\0') |
252b5132 RH |
16054 | { |
16055 | int i; | |
16056 | ||
16057 | i = atoi (opt + 3); | |
668c5ebc MR |
16058 | if (i != 0 && i != 2) |
16059 | as_bad (_(".option pic%d not supported"), i); | |
16060 | else if (mips_pic == VXWORKS_PIC) | |
16061 | as_bad (_(".option pic%d not supported in VxWorks PIC mode"), i); | |
16062 | else if (i == 0) | |
252b5132 RH |
16063 | mips_pic = NO_PIC; |
16064 | else if (i == 2) | |
143d77c5 | 16065 | { |
8b828383 | 16066 | mips_pic = SVR4_PIC; |
143d77c5 EC |
16067 | mips_abicalls = TRUE; |
16068 | } | |
252b5132 | 16069 | |
4d0d148d | 16070 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
16071 | { |
16072 | if (g_switch_seen && g_switch_value != 0) | |
16073 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
16074 | g_switch_value = 0; | |
16075 | bfd_set_gp_size (stdoutput, 0); | |
16076 | } | |
16077 | } | |
16078 | else | |
1661c76c | 16079 | as_warn (_("unrecognized option \"%s\""), opt); |
252b5132 | 16080 | |
d02603dc | 16081 | (void) restore_line_pointer (c); |
252b5132 RH |
16082 | demand_empty_rest_of_line (); |
16083 | } | |
16084 | ||
16085 | /* This structure is used to hold a stack of .set values. */ | |
16086 | ||
e972090a NC |
16087 | struct mips_option_stack |
16088 | { | |
252b5132 RH |
16089 | struct mips_option_stack *next; |
16090 | struct mips_set_options options; | |
16091 | }; | |
16092 | ||
16093 | static struct mips_option_stack *mips_opts_stack; | |
16094 | ||
22522f88 MR |
16095 | /* Return status for .set/.module option handling. */ |
16096 | ||
16097 | enum code_option_type | |
16098 | { | |
16099 | /* Unrecognized option. */ | |
16100 | OPTION_TYPE_BAD = -1, | |
16101 | ||
16102 | /* Ordinary option. */ | |
16103 | OPTION_TYPE_NORMAL, | |
16104 | ||
16105 | /* ISA changing option. */ | |
16106 | OPTION_TYPE_ISA | |
16107 | }; | |
16108 | ||
16109 | /* Handle common .set/.module options. Return status indicating option | |
16110 | type. */ | |
16111 | ||
16112 | static enum code_option_type | |
919731af | 16113 | parse_code_option (char * name) |
252b5132 | 16114 | { |
22522f88 | 16115 | bfd_boolean isa_set = FALSE; |
c6278170 | 16116 | const struct mips_ase *ase; |
22522f88 | 16117 | |
919731af | 16118 | if (strncmp (name, "at=", 3) == 0) |
741fe287 MR |
16119 | { |
16120 | char *s = name + 3; | |
16121 | ||
16122 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at)) | |
1661c76c | 16123 | as_bad (_("unrecognized register name `%s'"), s); |
741fe287 | 16124 | } |
252b5132 | 16125 | else if (strcmp (name, "at") == 0) |
919731af | 16126 | mips_opts.at = ATREG; |
252b5132 | 16127 | else if (strcmp (name, "noat") == 0) |
919731af | 16128 | mips_opts.at = ZERO; |
252b5132 | 16129 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) |
919731af | 16130 | mips_opts.nomove = 0; |
252b5132 | 16131 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) |
919731af | 16132 | mips_opts.nomove = 1; |
252b5132 | 16133 | else if (strcmp (name, "bopt") == 0) |
919731af | 16134 | mips_opts.nobopt = 0; |
252b5132 | 16135 | else if (strcmp (name, "nobopt") == 0) |
919731af | 16136 | mips_opts.nobopt = 1; |
ad3fea08 | 16137 | else if (strcmp (name, "gp=32") == 0) |
bad1aba3 | 16138 | mips_opts.gp = 32; |
ad3fea08 | 16139 | else if (strcmp (name, "gp=64") == 0) |
919731af | 16140 | mips_opts.gp = 64; |
ad3fea08 | 16141 | else if (strcmp (name, "fp=32") == 0) |
0b35dfee | 16142 | mips_opts.fp = 32; |
351cdf24 MF |
16143 | else if (strcmp (name, "fp=xx") == 0) |
16144 | mips_opts.fp = 0; | |
ad3fea08 | 16145 | else if (strcmp (name, "fp=64") == 0) |
919731af | 16146 | mips_opts.fp = 64; |
037b32b9 AN |
16147 | else if (strcmp (name, "softfloat") == 0) |
16148 | mips_opts.soft_float = 1; | |
16149 | else if (strcmp (name, "hardfloat") == 0) | |
16150 | mips_opts.soft_float = 0; | |
16151 | else if (strcmp (name, "singlefloat") == 0) | |
16152 | mips_opts.single_float = 1; | |
16153 | else if (strcmp (name, "doublefloat") == 0) | |
16154 | mips_opts.single_float = 0; | |
351cdf24 MF |
16155 | else if (strcmp (name, "nooddspreg") == 0) |
16156 | mips_opts.oddspreg = 0; | |
16157 | else if (strcmp (name, "oddspreg") == 0) | |
16158 | mips_opts.oddspreg = 1; | |
252b5132 RH |
16159 | else if (strcmp (name, "mips16") == 0 |
16160 | || strcmp (name, "MIPS-16") == 0) | |
919731af | 16161 | mips_opts.mips16 = 1; |
252b5132 RH |
16162 | else if (strcmp (name, "nomips16") == 0 |
16163 | || strcmp (name, "noMIPS-16") == 0) | |
16164 | mips_opts.mips16 = 0; | |
df58fc94 | 16165 | else if (strcmp (name, "micromips") == 0) |
919731af | 16166 | mips_opts.micromips = 1; |
df58fc94 RS |
16167 | else if (strcmp (name, "nomicromips") == 0) |
16168 | mips_opts.micromips = 0; | |
c6278170 RS |
16169 | else if (name[0] == 'n' |
16170 | && name[1] == 'o' | |
16171 | && (ase = mips_lookup_ase (name + 2))) | |
919731af | 16172 | mips_set_ase (ase, &mips_opts, FALSE); |
c6278170 | 16173 | else if ((ase = mips_lookup_ase (name))) |
919731af | 16174 | mips_set_ase (ase, &mips_opts, TRUE); |
1a2c1fad | 16175 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 16176 | { |
1a2c1fad CD |
16177 | /* Permit the user to change the ISA and architecture on the fly. |
16178 | Needless to say, misuse can cause serious problems. */ | |
919731af | 16179 | if (strncmp (name, "arch=", 5) == 0) |
1a2c1fad CD |
16180 | { |
16181 | const struct mips_cpu_info *p; | |
16182 | ||
919731af | 16183 | p = mips_parse_cpu ("internal use", name + 5); |
1a2c1fad CD |
16184 | if (!p) |
16185 | as_bad (_("unknown architecture %s"), name + 5); | |
16186 | else | |
16187 | { | |
16188 | mips_opts.arch = p->cpu; | |
16189 | mips_opts.isa = p->isa; | |
22522f88 | 16190 | isa_set = TRUE; |
1a2c1fad CD |
16191 | } |
16192 | } | |
81a21e38 TS |
16193 | else if (strncmp (name, "mips", 4) == 0) |
16194 | { | |
16195 | const struct mips_cpu_info *p; | |
16196 | ||
919731af | 16197 | p = mips_parse_cpu ("internal use", name); |
81a21e38 TS |
16198 | if (!p) |
16199 | as_bad (_("unknown ISA level %s"), name + 4); | |
16200 | else | |
16201 | { | |
16202 | mips_opts.arch = p->cpu; | |
16203 | mips_opts.isa = p->isa; | |
22522f88 | 16204 | isa_set = TRUE; |
81a21e38 TS |
16205 | } |
16206 | } | |
af7ee8bf | 16207 | else |
81a21e38 | 16208 | as_bad (_("unknown ISA or architecture %s"), name); |
252b5132 RH |
16209 | } |
16210 | else if (strcmp (name, "autoextend") == 0) | |
16211 | mips_opts.noautoextend = 0; | |
16212 | else if (strcmp (name, "noautoextend") == 0) | |
16213 | mips_opts.noautoextend = 1; | |
833794fc MR |
16214 | else if (strcmp (name, "insn32") == 0) |
16215 | mips_opts.insn32 = TRUE; | |
16216 | else if (strcmp (name, "noinsn32") == 0) | |
16217 | mips_opts.insn32 = FALSE; | |
919731af | 16218 | else if (strcmp (name, "sym32") == 0) |
16219 | mips_opts.sym32 = TRUE; | |
16220 | else if (strcmp (name, "nosym32") == 0) | |
16221 | mips_opts.sym32 = FALSE; | |
16222 | else | |
22522f88 MR |
16223 | return OPTION_TYPE_BAD; |
16224 | ||
16225 | return isa_set ? OPTION_TYPE_ISA : OPTION_TYPE_NORMAL; | |
919731af | 16226 | } |
16227 | ||
16228 | /* Handle the .set pseudo-op. */ | |
16229 | ||
16230 | static void | |
16231 | s_mipsset (int x ATTRIBUTE_UNUSED) | |
16232 | { | |
22522f88 | 16233 | enum code_option_type type = OPTION_TYPE_NORMAL; |
919731af | 16234 | char *name = input_line_pointer, ch; |
919731af | 16235 | |
16236 | file_mips_check_options (); | |
16237 | ||
16238 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
16239 | ++input_line_pointer; | |
16240 | ch = *input_line_pointer; | |
16241 | *input_line_pointer = '\0'; | |
16242 | ||
16243 | if (strchr (name, ',')) | |
16244 | { | |
16245 | /* Generic ".set" directive; use the generic handler. */ | |
16246 | *input_line_pointer = ch; | |
16247 | input_line_pointer = name; | |
16248 | s_set (0); | |
16249 | return; | |
16250 | } | |
16251 | ||
16252 | if (strcmp (name, "reorder") == 0) | |
16253 | { | |
16254 | if (mips_opts.noreorder) | |
16255 | end_noreorder (); | |
16256 | } | |
16257 | else if (strcmp (name, "noreorder") == 0) | |
16258 | { | |
16259 | if (!mips_opts.noreorder) | |
16260 | start_noreorder (); | |
16261 | } | |
16262 | else if (strcmp (name, "macro") == 0) | |
16263 | mips_opts.warn_about_macros = 0; | |
16264 | else if (strcmp (name, "nomacro") == 0) | |
16265 | { | |
16266 | if (mips_opts.noreorder == 0) | |
16267 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
16268 | mips_opts.warn_about_macros = 1; | |
16269 | } | |
16270 | else if (strcmp (name, "gp=default") == 0) | |
16271 | mips_opts.gp = file_mips_opts.gp; | |
16272 | else if (strcmp (name, "fp=default") == 0) | |
16273 | mips_opts.fp = file_mips_opts.fp; | |
16274 | else if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) | |
16275 | { | |
16276 | mips_opts.isa = file_mips_opts.isa; | |
16277 | mips_opts.arch = file_mips_opts.arch; | |
16278 | mips_opts.gp = file_mips_opts.gp; | |
16279 | mips_opts.fp = file_mips_opts.fp; | |
16280 | } | |
252b5132 RH |
16281 | else if (strcmp (name, "push") == 0) |
16282 | { | |
16283 | struct mips_option_stack *s; | |
16284 | ||
325801bd | 16285 | s = XNEW (struct mips_option_stack); |
252b5132 RH |
16286 | s->next = mips_opts_stack; |
16287 | s->options = mips_opts; | |
16288 | mips_opts_stack = s; | |
16289 | } | |
16290 | else if (strcmp (name, "pop") == 0) | |
16291 | { | |
16292 | struct mips_option_stack *s; | |
16293 | ||
16294 | s = mips_opts_stack; | |
16295 | if (s == NULL) | |
16296 | as_bad (_(".set pop with no .set push")); | |
16297 | else | |
16298 | { | |
16299 | /* If we're changing the reorder mode we need to handle | |
16300 | delay slots correctly. */ | |
16301 | if (s->options.noreorder && ! mips_opts.noreorder) | |
7d10b47d | 16302 | start_noreorder (); |
252b5132 | 16303 | else if (! s->options.noreorder && mips_opts.noreorder) |
7d10b47d | 16304 | end_noreorder (); |
252b5132 RH |
16305 | |
16306 | mips_opts = s->options; | |
16307 | mips_opts_stack = s->next; | |
16308 | free (s); | |
16309 | } | |
16310 | } | |
22522f88 MR |
16311 | else |
16312 | { | |
16313 | type = parse_code_option (name); | |
16314 | if (type == OPTION_TYPE_BAD) | |
16315 | as_warn (_("tried to set unrecognized symbol: %s\n"), name); | |
16316 | } | |
919731af | 16317 | |
16318 | /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp | |
16319 | registers based on what is supported by the arch/cpu. */ | |
22522f88 | 16320 | if (type == OPTION_TYPE_ISA) |
e6559e01 | 16321 | { |
919731af | 16322 | switch (mips_opts.isa) |
16323 | { | |
16324 | case 0: | |
16325 | break; | |
16326 | case ISA_MIPS1: | |
351cdf24 MF |
16327 | /* MIPS I cannot support FPXX. */ |
16328 | mips_opts.fp = 32; | |
16329 | /* fall-through. */ | |
919731af | 16330 | case ISA_MIPS2: |
16331 | case ISA_MIPS32: | |
16332 | case ISA_MIPS32R2: | |
16333 | case ISA_MIPS32R3: | |
16334 | case ISA_MIPS32R5: | |
16335 | mips_opts.gp = 32; | |
351cdf24 MF |
16336 | if (mips_opts.fp != 0) |
16337 | mips_opts.fp = 32; | |
919731af | 16338 | break; |
7361da2c AB |
16339 | case ISA_MIPS32R6: |
16340 | mips_opts.gp = 32; | |
16341 | mips_opts.fp = 64; | |
16342 | break; | |
919731af | 16343 | case ISA_MIPS3: |
16344 | case ISA_MIPS4: | |
16345 | case ISA_MIPS5: | |
16346 | case ISA_MIPS64: | |
16347 | case ISA_MIPS64R2: | |
16348 | case ISA_MIPS64R3: | |
16349 | case ISA_MIPS64R5: | |
7361da2c | 16350 | case ISA_MIPS64R6: |
919731af | 16351 | mips_opts.gp = 64; |
351cdf24 MF |
16352 | if (mips_opts.fp != 0) |
16353 | { | |
16354 | if (mips_opts.arch == CPU_R5900) | |
16355 | mips_opts.fp = 32; | |
16356 | else | |
16357 | mips_opts.fp = 64; | |
16358 | } | |
919731af | 16359 | break; |
16360 | default: | |
16361 | as_bad (_("unknown ISA level %s"), name + 4); | |
16362 | break; | |
16363 | } | |
e6559e01 | 16364 | } |
919731af | 16365 | |
16366 | mips_check_options (&mips_opts, FALSE); | |
16367 | ||
16368 | mips_check_isa_supports_ases (); | |
16369 | *input_line_pointer = ch; | |
16370 | demand_empty_rest_of_line (); | |
16371 | } | |
16372 | ||
16373 | /* Handle the .module pseudo-op. */ | |
16374 | ||
16375 | static void | |
16376 | s_module (int ignore ATTRIBUTE_UNUSED) | |
16377 | { | |
16378 | char *name = input_line_pointer, ch; | |
16379 | ||
16380 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
16381 | ++input_line_pointer; | |
16382 | ch = *input_line_pointer; | |
16383 | *input_line_pointer = '\0'; | |
16384 | ||
16385 | if (!file_mips_opts_checked) | |
252b5132 | 16386 | { |
22522f88 | 16387 | if (parse_code_option (name) == OPTION_TYPE_BAD) |
919731af | 16388 | as_bad (_(".module used with unrecognized symbol: %s\n"), name); |
16389 | ||
16390 | /* Update module level settings from mips_opts. */ | |
16391 | file_mips_opts = mips_opts; | |
252b5132 | 16392 | } |
919731af | 16393 | else |
16394 | as_bad (_(".module is not permitted after generating code")); | |
16395 | ||
252b5132 RH |
16396 | *input_line_pointer = ch; |
16397 | demand_empty_rest_of_line (); | |
16398 | } | |
16399 | ||
16400 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
16401 | .option pic2. It means to generate SVR4 PIC calls. */ | |
16402 | ||
16403 | static void | |
17a2f251 | 16404 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16405 | { |
16406 | mips_pic = SVR4_PIC; | |
143d77c5 | 16407 | mips_abicalls = TRUE; |
4d0d148d TS |
16408 | |
16409 | if (g_switch_seen && g_switch_value != 0) | |
16410 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
16411 | g_switch_value = 0; | |
16412 | ||
252b5132 RH |
16413 | bfd_set_gp_size (stdoutput, 0); |
16414 | demand_empty_rest_of_line (); | |
16415 | } | |
16416 | ||
16417 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
16418 | PIC code. It sets the $gp register for the function based on the | |
16419 | function address, which is in the register named in the argument. | |
16420 | This uses a relocation against _gp_disp, which is handled specially | |
16421 | by the linker. The result is: | |
16422 | lui $gp,%hi(_gp_disp) | |
16423 | addiu $gp,$gp,%lo(_gp_disp) | |
16424 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
16425 | The .cpload argument is normally $25 == $t9. |
16426 | ||
16427 | The -mno-shared option changes this to: | |
bbe506e8 TS |
16428 | lui $gp,%hi(__gnu_local_gp) |
16429 | addiu $gp,$gp,%lo(__gnu_local_gp) | |
aa6975fb ILT |
16430 | and the argument is ignored. This saves an instruction, but the |
16431 | resulting code is not position independent; it uses an absolute | |
bbe506e8 TS |
16432 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
16433 | can go into an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
16434 | |
16435 | static void | |
17a2f251 | 16436 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16437 | { |
16438 | expressionS ex; | |
aa6975fb ILT |
16439 | int reg; |
16440 | int in_shared; | |
252b5132 | 16441 | |
919731af | 16442 | file_mips_check_options (); |
16443 | ||
6478892d TS |
16444 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
16445 | .cpload is ignored. */ | |
16446 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
16447 | { |
16448 | s_ignore (0); | |
16449 | return; | |
16450 | } | |
16451 | ||
a276b80c MR |
16452 | if (mips_opts.mips16) |
16453 | { | |
16454 | as_bad (_("%s not supported in MIPS16 mode"), ".cpload"); | |
16455 | ignore_rest_of_line (); | |
16456 | return; | |
16457 | } | |
16458 | ||
d3ecfc59 | 16459 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
16460 | if (mips_opts.noreorder == 0) |
16461 | as_warn (_(".cpload not in noreorder section")); | |
16462 | ||
aa6975fb ILT |
16463 | reg = tc_get_register (0); |
16464 | ||
16465 | /* If we need to produce a 64-bit address, we are better off using | |
16466 | the default instruction sequence. */ | |
aed1a261 | 16467 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
aa6975fb | 16468 | |
252b5132 | 16469 | ex.X_op = O_symbol; |
bbe506e8 TS |
16470 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
16471 | "__gnu_local_gp"); | |
252b5132 RH |
16472 | ex.X_op_symbol = NULL; |
16473 | ex.X_add_number = 0; | |
16474 | ||
16475 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 16476 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 16477 | |
8a75745d MR |
16478 | mips_mark_labels (); |
16479 | mips_assembling_insn = TRUE; | |
16480 | ||
584892a6 | 16481 | macro_start (); |
67c0d1eb RS |
16482 | macro_build_lui (&ex, mips_gp_register); |
16483 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 16484 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
16485 | if (in_shared) |
16486 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
16487 | mips_gp_register, reg); | |
584892a6 | 16488 | macro_end (); |
252b5132 | 16489 | |
8a75745d | 16490 | mips_assembling_insn = FALSE; |
252b5132 RH |
16491 | demand_empty_rest_of_line (); |
16492 | } | |
16493 | ||
6478892d TS |
16494 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
16495 | .cpsetup $reg1, offset|$reg2, label | |
16496 | ||
16497 | If offset is given, this results in: | |
16498 | sd $gp, offset($sp) | |
956cd1d6 | 16499 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
16500 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
16501 | daddu $gp, $gp, $reg1 | |
6478892d TS |
16502 | |
16503 | If $reg2 is given, this results in: | |
40fc1451 | 16504 | or $reg2, $gp, $0 |
956cd1d6 | 16505 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
16506 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
16507 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
16508 | $reg1 is normally $25 == $t9. |
16509 | ||
16510 | The -mno-shared option replaces the last three instructions with | |
16511 | lui $gp,%hi(_gp) | |
54f4ddb3 | 16512 | addiu $gp,$gp,%lo(_gp) */ |
aa6975fb | 16513 | |
6478892d | 16514 | static void |
17a2f251 | 16515 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16516 | { |
16517 | expressionS ex_off; | |
16518 | expressionS ex_sym; | |
16519 | int reg1; | |
6478892d | 16520 | |
919731af | 16521 | file_mips_check_options (); |
16522 | ||
8586fc66 | 16523 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
16524 | We also need NewABI support. */ |
16525 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16526 | { | |
16527 | s_ignore (0); | |
16528 | return; | |
16529 | } | |
16530 | ||
a276b80c MR |
16531 | if (mips_opts.mips16) |
16532 | { | |
16533 | as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup"); | |
16534 | ignore_rest_of_line (); | |
16535 | return; | |
16536 | } | |
16537 | ||
6478892d TS |
16538 | reg1 = tc_get_register (0); |
16539 | SKIP_WHITESPACE (); | |
16540 | if (*input_line_pointer != ',') | |
16541 | { | |
16542 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
16543 | return; | |
16544 | } | |
16545 | else | |
80245285 | 16546 | ++input_line_pointer; |
6478892d TS |
16547 | SKIP_WHITESPACE (); |
16548 | if (*input_line_pointer == '$') | |
80245285 TS |
16549 | { |
16550 | mips_cpreturn_register = tc_get_register (0); | |
16551 | mips_cpreturn_offset = -1; | |
16552 | } | |
6478892d | 16553 | else |
80245285 TS |
16554 | { |
16555 | mips_cpreturn_offset = get_absolute_expression (); | |
16556 | mips_cpreturn_register = -1; | |
16557 | } | |
6478892d TS |
16558 | SKIP_WHITESPACE (); |
16559 | if (*input_line_pointer != ',') | |
16560 | { | |
16561 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
16562 | return; | |
16563 | } | |
16564 | else | |
f9419b05 | 16565 | ++input_line_pointer; |
6478892d | 16566 | SKIP_WHITESPACE (); |
f21f8242 | 16567 | expression (&ex_sym); |
6478892d | 16568 | |
8a75745d MR |
16569 | mips_mark_labels (); |
16570 | mips_assembling_insn = TRUE; | |
16571 | ||
584892a6 | 16572 | macro_start (); |
6478892d TS |
16573 | if (mips_cpreturn_register == -1) |
16574 | { | |
16575 | ex_off.X_op = O_constant; | |
16576 | ex_off.X_add_symbol = NULL; | |
16577 | ex_off.X_op_symbol = NULL; | |
16578 | ex_off.X_add_number = mips_cpreturn_offset; | |
16579 | ||
67c0d1eb | 16580 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 16581 | BFD_RELOC_LO16, SP); |
6478892d TS |
16582 | } |
16583 | else | |
40fc1451 | 16584 | move_register (mips_cpreturn_register, mips_gp_register); |
6478892d | 16585 | |
aed1a261 | 16586 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
aa6975fb | 16587 | { |
df58fc94 | 16588 | macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register, |
aa6975fb ILT |
16589 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, |
16590 | BFD_RELOC_HI16_S); | |
16591 | ||
16592 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
16593 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
16594 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
16595 | ||
16596 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
16597 | mips_gp_register, reg1); | |
16598 | } | |
16599 | else | |
16600 | { | |
16601 | expressionS ex; | |
16602 | ||
16603 | ex.X_op = O_symbol; | |
4184909a | 16604 | ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); |
aa6975fb ILT |
16605 | ex.X_op_symbol = NULL; |
16606 | ex.X_add_number = 0; | |
6e1304d8 | 16607 | |
aa6975fb ILT |
16608 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
16609 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
16610 | ||
16611 | macro_build_lui (&ex, mips_gp_register); | |
16612 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
16613 | mips_gp_register, BFD_RELOC_LO16); | |
16614 | } | |
f21f8242 | 16615 | |
584892a6 | 16616 | macro_end (); |
6478892d | 16617 | |
8a75745d | 16618 | mips_assembling_insn = FALSE; |
6478892d TS |
16619 | demand_empty_rest_of_line (); |
16620 | } | |
16621 | ||
16622 | static void | |
17a2f251 | 16623 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d | 16624 | { |
919731af | 16625 | file_mips_check_options (); |
16626 | ||
6478892d | 16627 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, |
54f4ddb3 | 16628 | .cplocal is ignored. */ |
6478892d TS |
16629 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) |
16630 | { | |
16631 | s_ignore (0); | |
16632 | return; | |
16633 | } | |
16634 | ||
a276b80c MR |
16635 | if (mips_opts.mips16) |
16636 | { | |
16637 | as_bad (_("%s not supported in MIPS16 mode"), ".cplocal"); | |
16638 | ignore_rest_of_line (); | |
16639 | return; | |
16640 | } | |
16641 | ||
6478892d | 16642 | mips_gp_register = tc_get_register (0); |
85b51719 | 16643 | demand_empty_rest_of_line (); |
6478892d TS |
16644 | } |
16645 | ||
252b5132 RH |
16646 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
16647 | offset from $sp. The offset is remembered, and after making a PIC | |
16648 | call $gp is restored from that location. */ | |
16649 | ||
16650 | static void | |
17a2f251 | 16651 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16652 | { |
16653 | expressionS ex; | |
252b5132 | 16654 | |
919731af | 16655 | file_mips_check_options (); |
16656 | ||
6478892d | 16657 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 16658 | .cprestore is ignored. */ |
6478892d | 16659 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
16660 | { |
16661 | s_ignore (0); | |
16662 | return; | |
16663 | } | |
16664 | ||
a276b80c MR |
16665 | if (mips_opts.mips16) |
16666 | { | |
16667 | as_bad (_("%s not supported in MIPS16 mode"), ".cprestore"); | |
16668 | ignore_rest_of_line (); | |
16669 | return; | |
16670 | } | |
16671 | ||
252b5132 | 16672 | mips_cprestore_offset = get_absolute_expression (); |
7a621144 | 16673 | mips_cprestore_valid = 1; |
252b5132 RH |
16674 | |
16675 | ex.X_op = O_constant; | |
16676 | ex.X_add_symbol = NULL; | |
16677 | ex.X_op_symbol = NULL; | |
16678 | ex.X_add_number = mips_cprestore_offset; | |
16679 | ||
8a75745d MR |
16680 | mips_mark_labels (); |
16681 | mips_assembling_insn = TRUE; | |
16682 | ||
584892a6 | 16683 | macro_start (); |
67c0d1eb RS |
16684 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
16685 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 16686 | macro_end (); |
252b5132 | 16687 | |
8a75745d | 16688 | mips_assembling_insn = FALSE; |
252b5132 RH |
16689 | demand_empty_rest_of_line (); |
16690 | } | |
16691 | ||
6478892d | 16692 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 16693 | was given in the preceding .cpsetup, it results in: |
6478892d | 16694 | ld $gp, offset($sp) |
76b3015f | 16695 | |
6478892d | 16696 | If a register $reg2 was given there, it results in: |
40fc1451 | 16697 | or $gp, $reg2, $0 */ |
54f4ddb3 | 16698 | |
6478892d | 16699 | static void |
17a2f251 | 16700 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16701 | { |
16702 | expressionS ex; | |
6478892d | 16703 | |
919731af | 16704 | file_mips_check_options (); |
16705 | ||
6478892d TS |
16706 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. |
16707 | We also need NewABI support. */ | |
16708 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16709 | { | |
16710 | s_ignore (0); | |
16711 | return; | |
16712 | } | |
16713 | ||
a276b80c MR |
16714 | if (mips_opts.mips16) |
16715 | { | |
16716 | as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn"); | |
16717 | ignore_rest_of_line (); | |
16718 | return; | |
16719 | } | |
16720 | ||
8a75745d MR |
16721 | mips_mark_labels (); |
16722 | mips_assembling_insn = TRUE; | |
16723 | ||
584892a6 | 16724 | macro_start (); |
6478892d TS |
16725 | if (mips_cpreturn_register == -1) |
16726 | { | |
16727 | ex.X_op = O_constant; | |
16728 | ex.X_add_symbol = NULL; | |
16729 | ex.X_op_symbol = NULL; | |
16730 | ex.X_add_number = mips_cpreturn_offset; | |
16731 | ||
67c0d1eb | 16732 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
16733 | } |
16734 | else | |
40fc1451 SD |
16735 | move_register (mips_gp_register, mips_cpreturn_register); |
16736 | ||
584892a6 | 16737 | macro_end (); |
6478892d | 16738 | |
8a75745d | 16739 | mips_assembling_insn = FALSE; |
6478892d TS |
16740 | demand_empty_rest_of_line (); |
16741 | } | |
16742 | ||
d0f13682 CLT |
16743 | /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword |
16744 | pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size | |
16745 | DTP- or TP-relative relocation of type RTYPE, for use in either DWARF | |
16746 | debug information or MIPS16 TLS. */ | |
741d6ea8 JM |
16747 | |
16748 | static void | |
d0f13682 CLT |
16749 | s_tls_rel_directive (const size_t bytes, const char *dirstr, |
16750 | bfd_reloc_code_real_type rtype) | |
741d6ea8 JM |
16751 | { |
16752 | expressionS ex; | |
16753 | char *p; | |
16754 | ||
16755 | expression (&ex); | |
16756 | ||
16757 | if (ex.X_op != O_symbol) | |
16758 | { | |
1661c76c | 16759 | as_bad (_("unsupported use of %s"), dirstr); |
741d6ea8 JM |
16760 | ignore_rest_of_line (); |
16761 | } | |
16762 | ||
16763 | p = frag_more (bytes); | |
16764 | md_number_to_chars (p, 0, bytes); | |
d0f13682 | 16765 | fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype); |
741d6ea8 | 16766 | demand_empty_rest_of_line (); |
de64cffd | 16767 | mips_clear_insn_labels (); |
741d6ea8 JM |
16768 | } |
16769 | ||
16770 | /* Handle .dtprelword. */ | |
16771 | ||
16772 | static void | |
16773 | s_dtprelword (int ignore ATTRIBUTE_UNUSED) | |
16774 | { | |
d0f13682 | 16775 | s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32); |
741d6ea8 JM |
16776 | } |
16777 | ||
16778 | /* Handle .dtpreldword. */ | |
16779 | ||
16780 | static void | |
16781 | s_dtpreldword (int ignore ATTRIBUTE_UNUSED) | |
16782 | { | |
d0f13682 CLT |
16783 | s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64); |
16784 | } | |
16785 | ||
16786 | /* Handle .tprelword. */ | |
16787 | ||
16788 | static void | |
16789 | s_tprelword (int ignore ATTRIBUTE_UNUSED) | |
16790 | { | |
16791 | s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32); | |
16792 | } | |
16793 | ||
16794 | /* Handle .tpreldword. */ | |
16795 | ||
16796 | static void | |
16797 | s_tpreldword (int ignore ATTRIBUTE_UNUSED) | |
16798 | { | |
16799 | s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64); | |
741d6ea8 JM |
16800 | } |
16801 | ||
6478892d TS |
16802 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC |
16803 | code. It sets the offset to use in gp_rel relocations. */ | |
16804 | ||
16805 | static void | |
17a2f251 | 16806 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16807 | { |
16808 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
16809 | We also need NewABI support. */ | |
16810 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16811 | { | |
16812 | s_ignore (0); | |
16813 | return; | |
16814 | } | |
16815 | ||
def2e0dd | 16816 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
16817 | |
16818 | demand_empty_rest_of_line (); | |
16819 | } | |
16820 | ||
252b5132 RH |
16821 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
16822 | code. It generates a 32 bit GP relative reloc. */ | |
16823 | ||
16824 | static void | |
17a2f251 | 16825 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 16826 | { |
a8dbcb85 TS |
16827 | segment_info_type *si; |
16828 | struct insn_label_list *l; | |
252b5132 RH |
16829 | expressionS ex; |
16830 | char *p; | |
16831 | ||
16832 | /* When not generating PIC code, this is treated as .word. */ | |
16833 | if (mips_pic != SVR4_PIC) | |
16834 | { | |
16835 | s_cons (2); | |
16836 | return; | |
16837 | } | |
16838 | ||
a8dbcb85 TS |
16839 | si = seg_info (now_seg); |
16840 | l = si->label_list; | |
7d10b47d | 16841 | mips_emit_delays (); |
252b5132 | 16842 | if (auto_align) |
462427c4 | 16843 | mips_align (2, 0, l); |
252b5132 RH |
16844 | |
16845 | expression (&ex); | |
a1facbec | 16846 | mips_clear_insn_labels (); |
252b5132 RH |
16847 | |
16848 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
16849 | { | |
1661c76c | 16850 | as_bad (_("unsupported use of .gpword")); |
252b5132 RH |
16851 | ignore_rest_of_line (); |
16852 | } | |
16853 | ||
16854 | p = frag_more (4); | |
17a2f251 | 16855 | md_number_to_chars (p, 0, 4); |
b34976b6 | 16856 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 16857 | BFD_RELOC_GPREL32); |
252b5132 RH |
16858 | |
16859 | demand_empty_rest_of_line (); | |
16860 | } | |
16861 | ||
10181a0d | 16862 | static void |
17a2f251 | 16863 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d | 16864 | { |
a8dbcb85 TS |
16865 | segment_info_type *si; |
16866 | struct insn_label_list *l; | |
10181a0d AO |
16867 | expressionS ex; |
16868 | char *p; | |
16869 | ||
16870 | /* When not generating PIC code, this is treated as .dword. */ | |
16871 | if (mips_pic != SVR4_PIC) | |
16872 | { | |
16873 | s_cons (3); | |
16874 | return; | |
16875 | } | |
16876 | ||
a8dbcb85 TS |
16877 | si = seg_info (now_seg); |
16878 | l = si->label_list; | |
7d10b47d | 16879 | mips_emit_delays (); |
10181a0d | 16880 | if (auto_align) |
462427c4 | 16881 | mips_align (3, 0, l); |
10181a0d AO |
16882 | |
16883 | expression (&ex); | |
a1facbec | 16884 | mips_clear_insn_labels (); |
10181a0d AO |
16885 | |
16886 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
16887 | { | |
1661c76c | 16888 | as_bad (_("unsupported use of .gpdword")); |
10181a0d AO |
16889 | ignore_rest_of_line (); |
16890 | } | |
16891 | ||
16892 | p = frag_more (8); | |
17a2f251 | 16893 | md_number_to_chars (p, 0, 8); |
a105a300 | 16894 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 16895 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
16896 | |
16897 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
16898 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
16899 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
16900 | |
16901 | demand_empty_rest_of_line (); | |
16902 | } | |
16903 | ||
a3f278e2 CM |
16904 | /* Handle the .ehword pseudo-op. This is used when generating unwinding |
16905 | tables. It generates a R_MIPS_EH reloc. */ | |
16906 | ||
16907 | static void | |
16908 | s_ehword (int ignore ATTRIBUTE_UNUSED) | |
16909 | { | |
16910 | expressionS ex; | |
16911 | char *p; | |
16912 | ||
16913 | mips_emit_delays (); | |
16914 | ||
16915 | expression (&ex); | |
16916 | mips_clear_insn_labels (); | |
16917 | ||
16918 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
16919 | { | |
1661c76c | 16920 | as_bad (_("unsupported use of .ehword")); |
a3f278e2 CM |
16921 | ignore_rest_of_line (); |
16922 | } | |
16923 | ||
16924 | p = frag_more (4); | |
16925 | md_number_to_chars (p, 0, 4); | |
16926 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, | |
2f0c68f2 | 16927 | BFD_RELOC_32_PCREL); |
a3f278e2 CM |
16928 | |
16929 | demand_empty_rest_of_line (); | |
16930 | } | |
16931 | ||
252b5132 RH |
16932 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
16933 | tables in SVR4 PIC code. */ | |
16934 | ||
16935 | static void | |
17a2f251 | 16936 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 16937 | { |
252b5132 RH |
16938 | int reg; |
16939 | ||
919731af | 16940 | file_mips_check_options (); |
16941 | ||
10181a0d AO |
16942 | /* This is ignored when not generating SVR4 PIC code. */ |
16943 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
16944 | { |
16945 | s_ignore (0); | |
16946 | return; | |
16947 | } | |
16948 | ||
8a75745d MR |
16949 | mips_mark_labels (); |
16950 | mips_assembling_insn = TRUE; | |
16951 | ||
252b5132 | 16952 | /* Add $gp to the register named as an argument. */ |
584892a6 | 16953 | macro_start (); |
252b5132 | 16954 | reg = tc_get_register (0); |
67c0d1eb | 16955 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 16956 | macro_end (); |
252b5132 | 16957 | |
8a75745d | 16958 | mips_assembling_insn = FALSE; |
bdaaa2e1 | 16959 | demand_empty_rest_of_line (); |
252b5132 RH |
16960 | } |
16961 | ||
16962 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
df58fc94 | 16963 | mips16/micromips mode. This permits the linker to handle them specially, |
252b5132 RH |
16964 | such as generating jalx instructions when needed. We also make |
16965 | them odd for the duration of the assembly, in order to generate the | |
16966 | right sort of code. We will make them even in the adjust_symtab | |
16967 | routine, while leaving them marked. This is convenient for the | |
16968 | debugger and the disassembler. The linker knows to make them odd | |
16969 | again. */ | |
16970 | ||
16971 | static void | |
17a2f251 | 16972 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 16973 | { |
7bb01e2d MR |
16974 | file_mips_check_options (); |
16975 | file_ase_mips16 |= mips_opts.mips16; | |
16976 | file_ase_micromips |= mips_opts.micromips; | |
16977 | ||
df58fc94 | 16978 | mips_mark_labels (); |
252b5132 RH |
16979 | |
16980 | demand_empty_rest_of_line (); | |
16981 | } | |
16982 | ||
ba92f887 MR |
16983 | /* Handle the .nan pseudo-op. */ |
16984 | ||
16985 | static void | |
16986 | s_nan (int ignore ATTRIBUTE_UNUSED) | |
16987 | { | |
16988 | static const char str_legacy[] = "legacy"; | |
16989 | static const char str_2008[] = "2008"; | |
16990 | size_t i; | |
16991 | ||
16992 | for (i = 0; !is_end_of_line[(unsigned char) input_line_pointer[i]]; i++); | |
16993 | ||
16994 | if (i == sizeof (str_2008) - 1 | |
16995 | && memcmp (input_line_pointer, str_2008, i) == 0) | |
7361da2c | 16996 | mips_nan2008 = 1; |
ba92f887 MR |
16997 | else if (i == sizeof (str_legacy) - 1 |
16998 | && memcmp (input_line_pointer, str_legacy, i) == 0) | |
7361da2c AB |
16999 | { |
17000 | if (ISA_HAS_LEGACY_NAN (file_mips_opts.isa)) | |
17001 | mips_nan2008 = 0; | |
17002 | else | |
17003 | as_bad (_("`%s' does not support legacy NaN"), | |
17004 | mips_cpu_info_from_isa (file_mips_opts.isa)->name); | |
17005 | } | |
ba92f887 | 17006 | else |
1661c76c | 17007 | as_bad (_("bad .nan directive")); |
ba92f887 MR |
17008 | |
17009 | input_line_pointer += i; | |
17010 | demand_empty_rest_of_line (); | |
17011 | } | |
17012 | ||
754e2bb9 RS |
17013 | /* Handle a .stab[snd] directive. Ideally these directives would be |
17014 | implemented in a transparent way, so that removing them would not | |
17015 | have any effect on the generated instructions. However, s_stab | |
17016 | internally changes the section, so in practice we need to decide | |
17017 | now whether the preceding label marks compressed code. We do not | |
17018 | support changing the compression mode of a label after a .stab* | |
17019 | directive, such as in: | |
17020 | ||
17021 | foo: | |
134c0c8b | 17022 | .stabs ... |
754e2bb9 RS |
17023 | .set mips16 |
17024 | ||
17025 | so the current mode wins. */ | |
252b5132 RH |
17026 | |
17027 | static void | |
17a2f251 | 17028 | s_mips_stab (int type) |
252b5132 | 17029 | { |
754e2bb9 | 17030 | mips_mark_labels (); |
252b5132 RH |
17031 | s_stab (type); |
17032 | } | |
17033 | ||
54f4ddb3 | 17034 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */ |
252b5132 RH |
17035 | |
17036 | static void | |
17a2f251 | 17037 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
17038 | { |
17039 | char *name; | |
17040 | int c; | |
17041 | symbolS *symbolP; | |
17042 | expressionS exp; | |
17043 | ||
d02603dc | 17044 | c = get_symbol_name (&name); |
252b5132 RH |
17045 | symbolP = symbol_find_or_make (name); |
17046 | S_SET_WEAK (symbolP); | |
17047 | *input_line_pointer = c; | |
17048 | ||
d02603dc | 17049 | SKIP_WHITESPACE_AFTER_NAME (); |
252b5132 RH |
17050 | |
17051 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
17052 | { | |
17053 | if (S_IS_DEFINED (symbolP)) | |
17054 | { | |
20203fb9 | 17055 | as_bad (_("ignoring attempt to redefine symbol %s"), |
252b5132 RH |
17056 | S_GET_NAME (symbolP)); |
17057 | ignore_rest_of_line (); | |
17058 | return; | |
17059 | } | |
bdaaa2e1 | 17060 | |
252b5132 RH |
17061 | if (*input_line_pointer == ',') |
17062 | { | |
17063 | ++input_line_pointer; | |
17064 | SKIP_WHITESPACE (); | |
17065 | } | |
bdaaa2e1 | 17066 | |
252b5132 RH |
17067 | expression (&exp); |
17068 | if (exp.X_op != O_symbol) | |
17069 | { | |
20203fb9 | 17070 | as_bad (_("bad .weakext directive")); |
98d3f06f | 17071 | ignore_rest_of_line (); |
252b5132 RH |
17072 | return; |
17073 | } | |
49309057 | 17074 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
17075 | } |
17076 | ||
17077 | demand_empty_rest_of_line (); | |
17078 | } | |
17079 | ||
17080 | /* Parse a register string into a number. Called from the ECOFF code | |
17081 | to parse .frame. The argument is non-zero if this is the frame | |
17082 | register, so that we can record it in mips_frame_reg. */ | |
17083 | ||
17084 | int | |
17a2f251 | 17085 | tc_get_register (int frame) |
252b5132 | 17086 | { |
707bfff6 | 17087 | unsigned int reg; |
252b5132 RH |
17088 | |
17089 | SKIP_WHITESPACE (); | |
707bfff6 TS |
17090 | if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®)) |
17091 | reg = 0; | |
252b5132 | 17092 | if (frame) |
7a621144 DJ |
17093 | { |
17094 | mips_frame_reg = reg != 0 ? reg : SP; | |
17095 | mips_frame_reg_valid = 1; | |
17096 | mips_cprestore_valid = 0; | |
17097 | } | |
252b5132 RH |
17098 | return reg; |
17099 | } | |
17100 | ||
17101 | valueT | |
17a2f251 | 17102 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
17103 | { |
17104 | int align = bfd_get_section_alignment (stdoutput, seg); | |
17105 | ||
f3ded42a RS |
17106 | /* We don't need to align ELF sections to the full alignment. |
17107 | However, Irix 5 may prefer that we align them at least to a 16 | |
17108 | byte boundary. We don't bother to align the sections if we | |
17109 | are targeted for an embedded system. */ | |
17110 | if (strncmp (TARGET_OS, "elf", 3) == 0) | |
17111 | return addr; | |
17112 | if (align > 4) | |
17113 | align = 4; | |
252b5132 | 17114 | |
8d3842cd | 17115 | return ((addr + (1 << align) - 1) & -(1 << align)); |
252b5132 RH |
17116 | } |
17117 | ||
17118 | /* Utility routine, called from above as well. If called while the | |
17119 | input file is still being read, it's only an approximation. (For | |
17120 | example, a symbol may later become defined which appeared to be | |
17121 | undefined earlier.) */ | |
17122 | ||
17123 | static int | |
17a2f251 | 17124 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
17125 | { |
17126 | if (sym == 0) | |
17127 | return 0; | |
17128 | ||
4d0d148d | 17129 | if (g_switch_value > 0) |
252b5132 RH |
17130 | { |
17131 | const char *symname; | |
17132 | int change; | |
17133 | ||
c9914766 | 17134 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
17135 | register. It can be if it is smaller than the -G size or if |
17136 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 17137 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
17138 | they can. */ |
17139 | symname = S_GET_NAME (sym); | |
17140 | if (symname != (const char *) NULL | |
17141 | && (strcmp (symname, "eprol") == 0 | |
17142 | || strcmp (symname, "etext") == 0 | |
17143 | || strcmp (symname, "_gp") == 0 | |
17144 | || strcmp (symname, "edata") == 0 | |
17145 | || strcmp (symname, "_fbss") == 0 | |
17146 | || strcmp (symname, "_fdata") == 0 | |
17147 | || strcmp (symname, "_ftext") == 0 | |
17148 | || strcmp (symname, "end") == 0 | |
17149 | || strcmp (symname, "_gp_disp") == 0)) | |
17150 | change = 1; | |
17151 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
17152 | && (0 | |
17153 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
17154 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
17155 | && (symbol_get_obj (sym)->ecoff_extern_size | |
17156 | <= g_switch_value)) | |
252b5132 RH |
17157 | #endif |
17158 | /* We must defer this decision until after the whole | |
17159 | file has been read, since there might be a .extern | |
17160 | after the first use of this symbol. */ | |
17161 | || (before_relaxing | |
17162 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 17163 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
17164 | #endif |
17165 | && S_GET_VALUE (sym) == 0) | |
17166 | || (S_GET_VALUE (sym) != 0 | |
17167 | && S_GET_VALUE (sym) <= g_switch_value))) | |
17168 | change = 0; | |
17169 | else | |
17170 | { | |
17171 | const char *segname; | |
17172 | ||
17173 | segname = segment_name (S_GET_SEGMENT (sym)); | |
9c2799c2 | 17174 | gas_assert (strcmp (segname, ".lit8") != 0 |
252b5132 RH |
17175 | && strcmp (segname, ".lit4") != 0); |
17176 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
17177 | && strcmp (segname, ".sbss") != 0 |
17178 | && strncmp (segname, ".sdata.", 7) != 0 | |
d4dc2f22 TS |
17179 | && strncmp (segname, ".sbss.", 6) != 0 |
17180 | && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0 | |
fba2b7f9 | 17181 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); |
252b5132 RH |
17182 | } |
17183 | return change; | |
17184 | } | |
17185 | else | |
c9914766 | 17186 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
17187 | return 1; |
17188 | } | |
17189 | ||
5919d012 RS |
17190 | |
17191 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
17192 | ||
17193 | static bfd_boolean | |
9e009953 | 17194 | pic_need_relax (symbolS *sym) |
5919d012 RS |
17195 | { |
17196 | asection *symsec; | |
5919d012 RS |
17197 | |
17198 | /* Handle the case of a symbol equated to another symbol. */ | |
17199 | while (symbol_equated_reloc_p (sym)) | |
17200 | { | |
17201 | symbolS *n; | |
17202 | ||
5f0fe04b | 17203 | /* It's possible to get a loop here in a badly written program. */ |
5919d012 RS |
17204 | n = symbol_get_value_expression (sym)->X_add_symbol; |
17205 | if (n == sym) | |
17206 | break; | |
17207 | sym = n; | |
17208 | } | |
17209 | ||
df1f3cda DD |
17210 | if (symbol_section_p (sym)) |
17211 | return TRUE; | |
17212 | ||
5919d012 RS |
17213 | symsec = S_GET_SEGMENT (sym); |
17214 | ||
5919d012 | 17215 | /* This must duplicate the test in adjust_reloc_syms. */ |
45dfa85a AM |
17216 | return (!bfd_is_und_section (symsec) |
17217 | && !bfd_is_abs_section (symsec) | |
5f0fe04b | 17218 | && !bfd_is_com_section (symsec) |
5919d012 | 17219 | /* A global or weak symbol is treated as external. */ |
f3ded42a | 17220 | && (!S_IS_WEAK (sym) && !S_IS_EXTERNAL (sym))); |
5919d012 | 17221 | } |
14f72d45 MR |
17222 | \f |
17223 | /* Given a MIPS16 variant frag FRAGP and PC-relative operand PCREL_OP | |
17224 | convert a section-relative value VAL to the equivalent PC-relative | |
17225 | value. */ | |
17226 | ||
17227 | static offsetT | |
17228 | mips16_pcrel_val (fragS *fragp, const struct mips_pcrel_operand *pcrel_op, | |
17229 | offsetT val, long stretch) | |
17230 | { | |
17231 | fragS *sym_frag; | |
17232 | addressT addr; | |
17233 | ||
17234 | gas_assert (pcrel_op->root.root.type == OP_PCREL); | |
17235 | ||
17236 | sym_frag = symbol_get_frag (fragp->fr_symbol); | |
17237 | ||
17238 | /* If the relax_marker of the symbol fragment differs from the | |
17239 | relax_marker of this fragment, we have not yet adjusted the | |
17240 | symbol fragment fr_address. We want to add in STRETCH in | |
17241 | order to get a better estimate of the address. This | |
17242 | particularly matters because of the shift bits. */ | |
17243 | if (stretch != 0 && sym_frag->relax_marker != fragp->relax_marker) | |
17244 | { | |
17245 | fragS *f; | |
17246 | ||
17247 | /* Adjust stretch for any alignment frag. Note that if have | |
17248 | been expanding the earlier code, the symbol may be | |
17249 | defined in what appears to be an earlier frag. FIXME: | |
17250 | This doesn't handle the fr_subtype field, which specifies | |
17251 | a maximum number of bytes to skip when doing an | |
17252 | alignment. */ | |
17253 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) | |
17254 | { | |
17255 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
17256 | { | |
17257 | if (stretch < 0) | |
17258 | stretch = -(-stretch & ~((1 << (int) f->fr_offset) - 1)); | |
17259 | else | |
17260 | stretch &= ~((1 << (int) f->fr_offset) - 1); | |
17261 | if (stretch == 0) | |
17262 | break; | |
17263 | } | |
17264 | } | |
17265 | if (f != NULL) | |
17266 | val += stretch; | |
17267 | } | |
17268 | ||
17269 | addr = fragp->fr_address + fragp->fr_fix; | |
17270 | ||
17271 | /* The base address rules are complicated. The base address of | |
17272 | a branch is the following instruction. The base address of a | |
17273 | PC relative load or add is the instruction itself, but if it | |
17274 | is in a delay slot (in which case it can not be extended) use | |
17275 | the address of the instruction whose delay slot it is in. */ | |
17276 | if (pcrel_op->include_isa_bit) | |
17277 | { | |
17278 | addr += 2; | |
17279 | ||
17280 | /* If we are currently assuming that this frag should be | |
17281 | extended, then the current address is two bytes higher. */ | |
17282 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
17283 | addr += 2; | |
17284 | ||
17285 | /* Ignore the low bit in the target, since it will be set | |
17286 | for a text label. */ | |
17287 | val &= -2; | |
17288 | } | |
17289 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
17290 | addr -= 4; | |
17291 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
17292 | addr -= 2; | |
5919d012 | 17293 | |
14f72d45 MR |
17294 | val -= addr & -(1 << pcrel_op->align_log2); |
17295 | ||
17296 | return val; | |
17297 | } | |
5919d012 | 17298 | |
252b5132 RH |
17299 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
17300 | extended opcode. SEC is the section the frag is in. */ | |
17301 | ||
17302 | static int | |
17a2f251 | 17303 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 | 17304 | { |
3ccad066 | 17305 | const struct mips_int_operand *operand; |
252b5132 | 17306 | offsetT val; |
252b5132 | 17307 | segT symsec; |
14f72d45 | 17308 | int type; |
252b5132 RH |
17309 | |
17310 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
17311 | return 0; | |
17312 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
17313 | return 1; | |
17314 | ||
88a7ef16 | 17315 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 | 17316 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); |
3ccad066 | 17317 | operand = mips16_immed_operand (type, FALSE); |
88a7ef16 MR |
17318 | if (S_FORCE_RELOC (fragp->fr_symbol, TRUE) |
17319 | || (operand->root.type == OP_PCREL | |
17320 | ? sec != symsec | |
17321 | : !bfd_is_abs_section (symsec))) | |
17322 | return 1; | |
252b5132 | 17323 | |
88a7ef16 | 17324 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; |
252b5132 | 17325 | |
3ccad066 | 17326 | if (operand->root.type == OP_PCREL) |
252b5132 | 17327 | { |
3ccad066 | 17328 | const struct mips_pcrel_operand *pcrel_op; |
3ccad066 | 17329 | offsetT maxtiny; |
252b5132 | 17330 | |
1425c41d | 17331 | if (RELAX_MIPS16_ALWAYS_EXTENDED (fragp->fr_subtype)) |
88a7ef16 | 17332 | return 1; |
252b5132 | 17333 | |
88a7ef16 | 17334 | pcrel_op = (const struct mips_pcrel_operand *) operand; |
14f72d45 | 17335 | val = mips16_pcrel_val (fragp, pcrel_op, val, stretch); |
252b5132 RH |
17336 | |
17337 | /* If any of the shifted bits are set, we must use an extended | |
17338 | opcode. If the address depends on the size of this | |
17339 | instruction, this can lead to a loop, so we arrange to always | |
88a7ef16 MR |
17340 | use an extended opcode. */ |
17341 | if ((val & ((1 << operand->shift) - 1)) != 0) | |
252b5132 RH |
17342 | { |
17343 | fragp->fr_subtype = | |
1425c41d | 17344 | RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp->fr_subtype); |
252b5132 RH |
17345 | return 1; |
17346 | } | |
17347 | ||
17348 | /* If we are about to mark a frag as extended because the value | |
3ccad066 RS |
17349 | is precisely the next value above maxtiny, then there is a |
17350 | chance of an infinite loop as in the following code: | |
252b5132 RH |
17351 | la $4,foo |
17352 | .skip 1020 | |
17353 | .align 2 | |
17354 | foo: | |
17355 | In this case when the la is extended, foo is 0x3fc bytes | |
17356 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
17357 | the la must be extended. To avoid this loop, we mark the | |
17358 | frag as extended if it was small, and is about to become | |
3ccad066 RS |
17359 | extended with the next value above maxtiny. */ |
17360 | maxtiny = mips_int_operand_max (operand); | |
17361 | if (val == maxtiny + (1 << operand->shift) | |
88a7ef16 | 17362 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
252b5132 RH |
17363 | { |
17364 | fragp->fr_subtype = | |
1425c41d | 17365 | RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp->fr_subtype); |
252b5132 RH |
17366 | return 1; |
17367 | } | |
17368 | } | |
252b5132 | 17369 | |
3ccad066 | 17370 | return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val); |
252b5132 RH |
17371 | } |
17372 | ||
8507b6e7 MR |
17373 | /* Given a MIPS16 variant frag FRAGP, return non-zero if it needs |
17374 | macro expansion. SEC is the section the frag is in. We only | |
17375 | support PC-relative instructions (LA, DLA, LW, LD) here, in | |
17376 | non-PIC code using 32-bit addressing. */ | |
17377 | ||
17378 | static int | |
17379 | mips16_macro_frag (fragS *fragp, asection *sec, long stretch) | |
17380 | { | |
17381 | const struct mips_pcrel_operand *pcrel_op; | |
17382 | const struct mips_int_operand *operand; | |
17383 | offsetT val; | |
17384 | segT symsec; | |
17385 | int type; | |
17386 | ||
17387 | gas_assert (!RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)); | |
17388 | ||
17389 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
17390 | return 0; | |
17391 | if (!RELAX_MIPS16_SYM32 (fragp->fr_subtype)) | |
17392 | return 0; | |
17393 | ||
17394 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
17395 | switch (type) | |
17396 | { | |
17397 | case 'A': | |
17398 | case 'B': | |
17399 | case 'E': | |
17400 | symsec = S_GET_SEGMENT (fragp->fr_symbol); | |
17401 | if (bfd_is_abs_section (symsec)) | |
17402 | return 1; | |
17403 | if (RELAX_MIPS16_PIC (fragp->fr_subtype)) | |
17404 | return 0; | |
17405 | if (S_FORCE_RELOC (fragp->fr_symbol, TRUE) || sec != symsec) | |
17406 | return 1; | |
17407 | ||
17408 | operand = mips16_immed_operand (type, TRUE); | |
17409 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17410 | pcrel_op = (const struct mips_pcrel_operand *) operand; | |
17411 | val = mips16_pcrel_val (fragp, pcrel_op, val, stretch); | |
17412 | ||
17413 | return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val); | |
17414 | ||
17415 | default: | |
17416 | return 0; | |
17417 | } | |
17418 | } | |
17419 | ||
4a6a3df4 AO |
17420 | /* Compute the length of a branch sequence, and adjust the |
17421 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
17422 | worst-case length is computed, with UPDATE being used to indicate | |
17423 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
17424 | branch is to be computed. */ | |
17425 | static int | |
17a2f251 | 17426 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 17427 | { |
b34976b6 | 17428 | bfd_boolean toofar; |
4a6a3df4 AO |
17429 | int length; |
17430 | ||
17431 | if (fragp | |
17432 | && S_IS_DEFINED (fragp->fr_symbol) | |
991f40a9 | 17433 | && !S_IS_WEAK (fragp->fr_symbol) |
4a6a3df4 AO |
17434 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) |
17435 | { | |
17436 | addressT addr; | |
17437 | offsetT val; | |
17438 | ||
17439 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17440 | ||
17441 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
17442 | ||
17443 | val -= addr; | |
17444 | ||
17445 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
17446 | } | |
4a6a3df4 | 17447 | else |
c1f61bd2 MR |
17448 | /* If the symbol is not defined or it's in a different segment, |
17449 | we emit the long sequence. */ | |
b34976b6 | 17450 | toofar = TRUE; |
4a6a3df4 AO |
17451 | |
17452 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
17453 | fragp->fr_subtype | |
66b3e8da | 17454 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype), |
ce8ad872 | 17455 | RELAX_BRANCH_PIC (fragp->fr_subtype), |
66b3e8da | 17456 | RELAX_BRANCH_UNCOND (fragp->fr_subtype), |
4a6a3df4 AO |
17457 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
17458 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
17459 | toofar); | |
17460 | ||
17461 | length = 4; | |
17462 | if (toofar) | |
17463 | { | |
17464 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
17465 | length += 8; | |
17466 | ||
ce8ad872 | 17467 | if (!fragp || RELAX_BRANCH_PIC (fragp->fr_subtype)) |
4a6a3df4 AO |
17468 | { |
17469 | /* Additional space for PIC loading of target address. */ | |
17470 | length += 8; | |
17471 | if (mips_opts.isa == ISA_MIPS1) | |
17472 | /* Additional space for $at-stabilizing nop. */ | |
17473 | length += 4; | |
17474 | } | |
17475 | ||
17476 | /* If branch is conditional. */ | |
17477 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
17478 | length += 8; | |
17479 | } | |
b34976b6 | 17480 | |
4a6a3df4 AO |
17481 | return length; |
17482 | } | |
17483 | ||
7bd374a4 MR |
17484 | /* Get a FRAG's branch instruction delay slot size, either from the |
17485 | short-delay-slot bit of a branch-and-link instruction if AL is TRUE, | |
17486 | or SHORT_INSN_SIZE otherwise. */ | |
17487 | ||
17488 | static int | |
17489 | frag_branch_delay_slot_size (fragS *fragp, bfd_boolean al, int short_insn_size) | |
17490 | { | |
17491 | char *buf = fragp->fr_literal + fragp->fr_fix; | |
17492 | ||
17493 | if (al) | |
17494 | return (read_compressed_insn (buf, 4) & 0x02000000) ? 2 : 4; | |
17495 | else | |
17496 | return short_insn_size; | |
17497 | } | |
17498 | ||
df58fc94 RS |
17499 | /* Compute the length of a branch sequence, and adjust the |
17500 | RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the | |
17501 | worst-case length is computed, with UPDATE being used to indicate | |
17502 | whether an unconditional (-1), or regular (0) branch is to be | |
17503 | computed. */ | |
17504 | ||
17505 | static int | |
17506 | relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update) | |
17507 | { | |
7bd374a4 MR |
17508 | bfd_boolean insn32 = TRUE; |
17509 | bfd_boolean nods = TRUE; | |
ce8ad872 | 17510 | bfd_boolean pic = TRUE; |
7bd374a4 MR |
17511 | bfd_boolean al = TRUE; |
17512 | int short_insn_size; | |
df58fc94 RS |
17513 | bfd_boolean toofar; |
17514 | int length; | |
17515 | ||
7bd374a4 MR |
17516 | if (fragp) |
17517 | { | |
17518 | insn32 = RELAX_MICROMIPS_INSN32 (fragp->fr_subtype); | |
17519 | nods = RELAX_MICROMIPS_NODS (fragp->fr_subtype); | |
ce8ad872 | 17520 | pic = RELAX_MICROMIPS_PIC (fragp->fr_subtype); |
7bd374a4 MR |
17521 | al = RELAX_MICROMIPS_LINK (fragp->fr_subtype); |
17522 | } | |
17523 | short_insn_size = insn32 ? 4 : 2; | |
17524 | ||
df58fc94 RS |
17525 | if (fragp |
17526 | && S_IS_DEFINED (fragp->fr_symbol) | |
991f40a9 | 17527 | && !S_IS_WEAK (fragp->fr_symbol) |
df58fc94 RS |
17528 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) |
17529 | { | |
17530 | addressT addr; | |
17531 | offsetT val; | |
17532 | ||
17533 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17534 | /* Ignore the low bit in the target, since it will be set | |
17535 | for a text label. */ | |
17536 | if ((val & 1) != 0) | |
17537 | --val; | |
17538 | ||
17539 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
17540 | ||
17541 | val -= addr; | |
17542 | ||
17543 | toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1); | |
17544 | } | |
df58fc94 | 17545 | else |
c1f61bd2 MR |
17546 | /* If the symbol is not defined or it's in a different segment, |
17547 | we emit the long sequence. */ | |
df58fc94 RS |
17548 | toofar = TRUE; |
17549 | ||
17550 | if (fragp && update | |
17551 | && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
17552 | fragp->fr_subtype = (toofar | |
17553 | ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype) | |
17554 | : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype)); | |
17555 | ||
17556 | length = 4; | |
17557 | if (toofar) | |
17558 | { | |
17559 | bfd_boolean compact_known = fragp != NULL; | |
17560 | bfd_boolean compact = FALSE; | |
17561 | bfd_boolean uncond; | |
17562 | ||
df58fc94 | 17563 | if (fragp) |
8484fb75 MR |
17564 | { |
17565 | compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); | |
17566 | uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype); | |
8484fb75 | 17567 | } |
df58fc94 RS |
17568 | else |
17569 | uncond = update < 0; | |
17570 | ||
17571 | /* If label is out of range, we turn branch <br>: | |
17572 | ||
17573 | <br> label # 4 bytes | |
17574 | 0: | |
17575 | ||
17576 | into: | |
17577 | ||
17578 | j label # 4 bytes | |
8484fb75 MR |
17579 | nop # 2/4 bytes if |
17580 | # compact && (!PIC || insn32) | |
df58fc94 RS |
17581 | 0: |
17582 | */ | |
ce8ad872 | 17583 | if ((!pic || insn32) && (!compact_known || compact)) |
8484fb75 | 17584 | length += short_insn_size; |
df58fc94 RS |
17585 | |
17586 | /* If assembling PIC code, we further turn: | |
17587 | ||
17588 | j label # 4 bytes | |
17589 | ||
17590 | into: | |
17591 | ||
17592 | lw/ld at, %got(label)(gp) # 4 bytes | |
17593 | d/addiu at, %lo(label) # 4 bytes | |
8484fb75 | 17594 | jr/c at # 2/4 bytes |
df58fc94 | 17595 | */ |
ce8ad872 | 17596 | if (pic) |
8484fb75 | 17597 | length += 4 + short_insn_size; |
df58fc94 | 17598 | |
7bd374a4 MR |
17599 | /* Add an extra nop if the jump has no compact form and we need |
17600 | to fill the delay slot. */ | |
ce8ad872 | 17601 | if ((!pic || al) && nods) |
7bd374a4 MR |
17602 | length += (fragp |
17603 | ? frag_branch_delay_slot_size (fragp, al, short_insn_size) | |
17604 | : short_insn_size); | |
17605 | ||
df58fc94 RS |
17606 | /* If branch <br> is conditional, we prepend negated branch <brneg>: |
17607 | ||
17608 | <brneg> 0f # 4 bytes | |
8484fb75 | 17609 | nop # 2/4 bytes if !compact |
df58fc94 RS |
17610 | */ |
17611 | if (!uncond) | |
8484fb75 | 17612 | length += (compact_known && compact) ? 4 : 4 + short_insn_size; |
df58fc94 | 17613 | } |
7bd374a4 MR |
17614 | else if (nods) |
17615 | { | |
17616 | /* Add an extra nop to fill the delay slot. */ | |
17617 | gas_assert (fragp); | |
17618 | length += frag_branch_delay_slot_size (fragp, al, short_insn_size); | |
17619 | } | |
df58fc94 RS |
17620 | |
17621 | return length; | |
17622 | } | |
17623 | ||
17624 | /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16 | |
17625 | bit accordingly. */ | |
17626 | ||
17627 | static int | |
17628 | relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update) | |
17629 | { | |
17630 | bfd_boolean toofar; | |
17631 | ||
df58fc94 RS |
17632 | if (fragp |
17633 | && S_IS_DEFINED (fragp->fr_symbol) | |
991f40a9 | 17634 | && !S_IS_WEAK (fragp->fr_symbol) |
df58fc94 RS |
17635 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) |
17636 | { | |
17637 | addressT addr; | |
17638 | offsetT val; | |
17639 | int type; | |
17640 | ||
17641 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17642 | /* Ignore the low bit in the target, since it will be set | |
17643 | for a text label. */ | |
17644 | if ((val & 1) != 0) | |
17645 | --val; | |
17646 | ||
17647 | /* Assume this is a 2-byte branch. */ | |
17648 | addr = fragp->fr_address + fragp->fr_fix + 2; | |
17649 | ||
17650 | /* We try to avoid the infinite loop by not adding 2 more bytes for | |
17651 | long branches. */ | |
17652 | ||
17653 | val -= addr; | |
17654 | ||
17655 | type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
17656 | if (type == 'D') | |
17657 | toofar = val < - (0x200 << 1) || val >= (0x200 << 1); | |
17658 | else if (type == 'E') | |
17659 | toofar = val < - (0x40 << 1) || val >= (0x40 << 1); | |
17660 | else | |
17661 | abort (); | |
17662 | } | |
17663 | else | |
17664 | /* If the symbol is not defined or it's in a different segment, | |
17665 | we emit a normal 32-bit branch. */ | |
17666 | toofar = TRUE; | |
17667 | ||
17668 | if (fragp && update | |
17669 | && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
17670 | fragp->fr_subtype | |
17671 | = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype) | |
17672 | : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype); | |
17673 | ||
17674 | if (toofar) | |
17675 | return 4; | |
17676 | ||
17677 | return 2; | |
17678 | } | |
17679 | ||
252b5132 RH |
17680 | /* Estimate the size of a frag before relaxing. Unless this is the |
17681 | mips16, we are not really relaxing here, and the final size is | |
17682 | encoded in the subtype information. For the mips16, we have to | |
17683 | decide whether we are using an extended opcode or not. */ | |
17684 | ||
252b5132 | 17685 | int |
17a2f251 | 17686 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 17687 | { |
5919d012 | 17688 | int change; |
252b5132 | 17689 | |
4a6a3df4 AO |
17690 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
17691 | { | |
17692 | ||
b34976b6 AM |
17693 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
17694 | ||
4a6a3df4 AO |
17695 | return fragp->fr_var; |
17696 | } | |
17697 | ||
252b5132 | 17698 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
8507b6e7 MR |
17699 | { |
17700 | /* We don't want to modify the EXTENDED bit here; it might get us | |
17701 | into infinite loops. We change it only in mips_relax_frag(). */ | |
17702 | if (RELAX_MIPS16_MACRO (fragp->fr_subtype)) | |
17703 | return 12; | |
17704 | else | |
17705 | return RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2; | |
17706 | } | |
252b5132 | 17707 | |
df58fc94 RS |
17708 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
17709 | { | |
17710 | int length = 4; | |
17711 | ||
17712 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
17713 | length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE); | |
17714 | if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
17715 | length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE); | |
17716 | fragp->fr_var = length; | |
17717 | ||
17718 | return length; | |
17719 | } | |
17720 | ||
ce8ad872 | 17721 | if (mips_pic == VXWORKS_PIC) |
0a44bf69 RS |
17722 | /* For vxworks, GOT16 relocations never have a corresponding LO16. */ |
17723 | change = 0; | |
ce8ad872 MR |
17724 | else if (RELAX_PIC (fragp->fr_subtype)) |
17725 | change = pic_need_relax (fragp->fr_symbol); | |
252b5132 | 17726 | else |
ce8ad872 | 17727 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 RH |
17728 | |
17729 | if (change) | |
17730 | { | |
4d7206a2 | 17731 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 17732 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 17733 | } |
4d7206a2 RS |
17734 | else |
17735 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
17736 | } |
17737 | ||
17738 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 17739 | should be converted into a reloc against a section. */ |
252b5132 RH |
17740 | |
17741 | int | |
17a2f251 | 17742 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 17743 | { |
252b5132 RH |
17744 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
17745 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
17746 | return 0; | |
a161fe53 | 17747 | |
252b5132 RH |
17748 | if (fixp->fx_addsy == NULL) |
17749 | return 1; | |
a161fe53 | 17750 | |
2f0c68f2 CM |
17751 | /* Allow relocs used for EH tables. */ |
17752 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) | |
17753 | return 1; | |
17754 | ||
de7e6852 RS |
17755 | /* If symbol SYM is in a mergeable section, relocations of the form |
17756 | SYM + 0 can usually be made section-relative. The mergeable data | |
17757 | is then identified by the section offset rather than by the symbol. | |
17758 | ||
17759 | However, if we're generating REL LO16 relocations, the offset is split | |
33eaf5de | 17760 | between the LO16 and partnering high part relocation. The linker will |
de7e6852 RS |
17761 | need to recalculate the complete offset in order to correctly identify |
17762 | the merge data. | |
17763 | ||
33eaf5de | 17764 | The linker has traditionally not looked for the partnering high part |
de7e6852 RS |
17765 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be |
17766 | placed anywhere. Rather than break backwards compatibility by changing | |
17767 | this, it seems better not to force the issue, and instead keep the | |
17768 | original symbol. This will work with either linker behavior. */ | |
738e5348 | 17769 | if ((lo16_reloc_p (fixp->fx_r_type) |
704803a9 | 17770 | || reloc_needs_lo_p (fixp->fx_r_type)) |
de7e6852 RS |
17771 | && HAVE_IN_PLACE_ADDENDS |
17772 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
17773 | return 0; | |
17774 | ||
97f50151 MR |
17775 | /* There is no place to store an in-place offset for JALR relocations. */ |
17776 | if (jalr_reloc_p (fixp->fx_r_type) && HAVE_IN_PLACE_ADDENDS) | |
17777 | return 0; | |
17778 | ||
17779 | /* Likewise an in-range offset of limited PC-relative relocations may | |
2de39019 | 17780 | overflow the in-place relocatable field if recalculated against the |
7361da2c AB |
17781 | start address of the symbol's containing section. |
17782 | ||
17783 | Also, PC relative relocations for MIPS R6 need to be symbol rather than | |
17784 | section relative to allow linker relaxations to be performed later on. */ | |
97f50151 | 17785 | if (limited_pcrel_reloc_p (fixp->fx_r_type) |
912815f0 | 17786 | && (HAVE_IN_PLACE_ADDENDS || ISA_IS_R6 (file_mips_opts.isa))) |
1180b5a4 RS |
17787 | return 0; |
17788 | ||
b314ec0e RS |
17789 | /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve |
17790 | to a floating-point stub. The same is true for non-R_MIPS16_26 | |
17791 | relocations against MIPS16 functions; in this case, the stub becomes | |
17792 | the function's canonical address. | |
17793 | ||
17794 | Floating-point stubs are stored in unique .mips16.call.* or | |
17795 | .mips16.fn.* sections. If a stub T for function F is in section S, | |
17796 | the first relocation in section S must be against F; this is how the | |
17797 | linker determines the target function. All relocations that might | |
17798 | resolve to T must also be against F. We therefore have the following | |
17799 | restrictions, which are given in an intentionally-redundant way: | |
17800 | ||
17801 | 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16 | |
17802 | symbols. | |
17803 | ||
17804 | 2. We cannot reduce a stub's relocations against non-MIPS16 symbols | |
17805 | if that stub might be used. | |
17806 | ||
17807 | 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16 | |
17808 | symbols. | |
17809 | ||
17810 | 4. We cannot reduce a stub's relocations against MIPS16 symbols if | |
17811 | that stub might be used. | |
17812 | ||
17813 | There is a further restriction: | |
17814 | ||
df58fc94 | 17815 | 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or |
0e9c5a5c | 17816 | R_MICROMIPS_26_S1) or branch relocations (R_MIPS_PC26_S2, |
c9775dde MR |
17817 | R_MIPS_PC21_S2, R_MIPS_PC16, R_MIPS16_PC16_S1, |
17818 | R_MICROMIPS_PC16_S1, R_MICROMIPS_PC10_S1 or R_MICROMIPS_PC7_S1) | |
17819 | against MIPS16 or microMIPS symbols because we need to keep the | |
17820 | MIPS16 or microMIPS symbol for the purpose of mode mismatch | |
a6ebf616 MR |
17821 | detection and JAL or BAL to JALX instruction conversion in the |
17822 | linker. | |
b314ec0e | 17823 | |
df58fc94 | 17824 | For simplicity, we deal with (3)-(4) by not reducing _any_ relocation |
507dcb32 | 17825 | against a MIPS16 symbol. We deal with (5) by additionally leaving |
0e9c5a5c | 17826 | alone any jump and branch relocations against a microMIPS symbol. |
b314ec0e RS |
17827 | |
17828 | We deal with (1)-(2) by saying that, if there's a R_MIPS16_26 | |
17829 | relocation against some symbol R, no relocation against R may be | |
17830 | reduced. (Note that this deals with (2) as well as (1) because | |
17831 | relocations against global symbols will never be reduced on ELF | |
17832 | targets.) This approach is a little simpler than trying to detect | |
17833 | stub sections, and gives the "all or nothing" per-symbol consistency | |
17834 | that we have for MIPS16 symbols. */ | |
f3ded42a | 17835 | if (fixp->fx_subsy == NULL |
30c09090 | 17836 | && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy)) |
44d3da23 | 17837 | || (ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy)) |
0e9c5a5c MR |
17838 | && (jmp_reloc_p (fixp->fx_r_type) |
17839 | || b_reloc_p (fixp->fx_r_type))) | |
44d3da23 | 17840 | || *symbol_get_tc (fixp->fx_addsy))) |
252b5132 | 17841 | return 0; |
a161fe53 | 17842 | |
252b5132 RH |
17843 | return 1; |
17844 | } | |
17845 | ||
17846 | /* Translate internal representation of relocation info to BFD target | |
17847 | format. */ | |
17848 | ||
17849 | arelent ** | |
17a2f251 | 17850 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
17851 | { |
17852 | static arelent *retval[4]; | |
17853 | arelent *reloc; | |
17854 | bfd_reloc_code_real_type code; | |
17855 | ||
4b0cff4e | 17856 | memset (retval, 0, sizeof(retval)); |
325801bd TS |
17857 | reloc = retval[0] = XCNEW (arelent); |
17858 | reloc->sym_ptr_ptr = XNEW (asymbol *); | |
49309057 | 17859 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
252b5132 RH |
17860 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
17861 | ||
bad36eac DJ |
17862 | if (fixp->fx_pcrel) |
17863 | { | |
df58fc94 | 17864 | gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 |
c9775dde | 17865 | || fixp->fx_r_type == BFD_RELOC_MIPS16_16_PCREL_S1 |
df58fc94 RS |
17866 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 |
17867 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
b47468a6 | 17868 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1 |
7361da2c AB |
17869 | || fixp->fx_r_type == BFD_RELOC_32_PCREL |
17870 | || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2 | |
17871 | || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2 | |
17872 | || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3 | |
17873 | || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2 | |
17874 | || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL | |
17875 | || fixp->fx_r_type == BFD_RELOC_LO16_PCREL); | |
bad36eac DJ |
17876 | |
17877 | /* At this point, fx_addnumber is "symbol offset - pcrel address". | |
17878 | Relocations want only the symbol offset. */ | |
51f6035b MR |
17879 | switch (fixp->fx_r_type) |
17880 | { | |
17881 | case BFD_RELOC_MIPS_18_PCREL_S3: | |
17882 | reloc->addend = fixp->fx_addnumber + (reloc->address & ~7); | |
17883 | break; | |
17884 | default: | |
17885 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
17886 | break; | |
17887 | } | |
bad36eac | 17888 | } |
17c6c9d9 MR |
17889 | else if (HAVE_IN_PLACE_ADDENDS |
17890 | && fixp->fx_r_type == BFD_RELOC_MICROMIPS_JMP | |
17891 | && (read_compressed_insn (fixp->fx_frag->fr_literal | |
17892 | + fixp->fx_where, 4) >> 26) == 0x3c) | |
17893 | { | |
17894 | /* Shift is 2, unusually, for microMIPS JALX. Adjust the in-place | |
17895 | addend accordingly. */ | |
17896 | reloc->addend = fixp->fx_addnumber >> 1; | |
17897 | } | |
bad36eac DJ |
17898 | else |
17899 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 17900 | |
438c16b8 TS |
17901 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
17902 | entry to be used in the relocation's section offset. */ | |
17903 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
17904 | { |
17905 | reloc->address = reloc->addend; | |
17906 | reloc->addend = 0; | |
17907 | } | |
17908 | ||
252b5132 | 17909 | code = fixp->fx_r_type; |
252b5132 | 17910 | |
bad36eac | 17911 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
252b5132 RH |
17912 | if (reloc->howto == NULL) |
17913 | { | |
17914 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
1661c76c RS |
17915 | _("cannot represent %s relocation in this object file" |
17916 | " format"), | |
252b5132 RH |
17917 | bfd_get_reloc_code_name (code)); |
17918 | retval[0] = NULL; | |
17919 | } | |
17920 | ||
17921 | return retval; | |
17922 | } | |
17923 | ||
17924 | /* Relax a machine dependent frag. This returns the amount by which | |
17925 | the current size of the frag should change. */ | |
17926 | ||
17927 | int | |
17a2f251 | 17928 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 17929 | { |
4a6a3df4 AO |
17930 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
17931 | { | |
17932 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
17933 | |
17934 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
17935 | |
17936 | return fragp->fr_var - old_var; | |
17937 | } | |
17938 | ||
df58fc94 RS |
17939 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
17940 | { | |
17941 | offsetT old_var = fragp->fr_var; | |
17942 | offsetT new_var = 4; | |
17943 | ||
17944 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
17945 | new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE); | |
17946 | if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
17947 | new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE); | |
17948 | fragp->fr_var = new_var; | |
17949 | ||
17950 | return new_var - old_var; | |
17951 | } | |
17952 | ||
252b5132 RH |
17953 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
17954 | return 0; | |
17955 | ||
8507b6e7 | 17956 | if (!mips16_extended_frag (fragp, sec, stretch)) |
252b5132 | 17957 | { |
8507b6e7 MR |
17958 | if (RELAX_MIPS16_MACRO (fragp->fr_subtype)) |
17959 | { | |
17960 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_MACRO (fragp->fr_subtype); | |
17961 | return -10; | |
17962 | } | |
17963 | else if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
17964 | { | |
17965 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
17966 | return -2; | |
17967 | } | |
17968 | else | |
17969 | return 0; | |
17970 | } | |
17971 | else if (!mips16_macro_frag (fragp, sec, stretch)) | |
17972 | { | |
17973 | if (RELAX_MIPS16_MACRO (fragp->fr_subtype)) | |
17974 | { | |
17975 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_MACRO (fragp->fr_subtype); | |
17976 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
17977 | return -8; | |
17978 | } | |
17979 | else if (!RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
17980 | { | |
17981 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
17982 | return 2; | |
17983 | } | |
17984 | else | |
252b5132 | 17985 | return 0; |
252b5132 RH |
17986 | } |
17987 | else | |
17988 | { | |
8507b6e7 | 17989 | if (RELAX_MIPS16_MACRO (fragp->fr_subtype)) |
252b5132 | 17990 | return 0; |
8507b6e7 MR |
17991 | else if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
17992 | { | |
17993 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
17994 | fragp->fr_subtype = RELAX_MIPS16_MARK_MACRO (fragp->fr_subtype); | |
17995 | return 8; | |
17996 | } | |
17997 | else | |
17998 | { | |
17999 | fragp->fr_subtype = RELAX_MIPS16_MARK_MACRO (fragp->fr_subtype); | |
18000 | return 10; | |
18001 | } | |
252b5132 RH |
18002 | } |
18003 | ||
18004 | return 0; | |
18005 | } | |
18006 | ||
18007 | /* Convert a machine dependent frag. */ | |
18008 | ||
18009 | void | |
17a2f251 | 18010 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 18011 | { |
4a6a3df4 AO |
18012 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
18013 | { | |
4d68580a | 18014 | char *buf; |
4a6a3df4 AO |
18015 | unsigned long insn; |
18016 | expressionS exp; | |
18017 | fixS *fixp; | |
b34976b6 | 18018 | |
4d68580a RS |
18019 | buf = fragp->fr_literal + fragp->fr_fix; |
18020 | insn = read_insn (buf); | |
b34976b6 | 18021 | |
4a6a3df4 AO |
18022 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
18023 | { | |
18024 | /* We generate a fixup instead of applying it right now | |
18025 | because, if there are linker relaxations, we're going to | |
18026 | need the relocations. */ | |
18027 | exp.X_op = O_symbol; | |
18028 | exp.X_add_symbol = fragp->fr_symbol; | |
18029 | exp.X_add_number = fragp->fr_offset; | |
18030 | ||
4d68580a RS |
18031 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE, |
18032 | BFD_RELOC_16_PCREL_S2); | |
4a6a3df4 AO |
18033 | fixp->fx_file = fragp->fr_file; |
18034 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 18035 | |
4d68580a | 18036 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18037 | } |
18038 | else | |
18039 | { | |
18040 | int i; | |
18041 | ||
18042 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
1661c76c | 18043 | _("relaxed out-of-range branch into a jump")); |
4a6a3df4 AO |
18044 | |
18045 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
18046 | goto uncond; | |
18047 | ||
18048 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18049 | { | |
18050 | /* Reverse the branch. */ | |
18051 | switch ((insn >> 28) & 0xf) | |
18052 | { | |
18053 | case 4: | |
56d438b1 CF |
18054 | if ((insn & 0xff000000) == 0x47000000 |
18055 | || (insn & 0xff600000) == 0x45600000) | |
18056 | { | |
18057 | /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition | |
18058 | reversed by tweaking bit 23. */ | |
18059 | insn ^= 0x00800000; | |
18060 | } | |
18061 | else | |
18062 | { | |
18063 | /* bc[0-3][tf]l? instructions can have the condition | |
18064 | reversed by tweaking a single TF bit, and their | |
18065 | opcodes all have 0x4???????. */ | |
18066 | gas_assert ((insn & 0xf3e00000) == 0x41000000); | |
18067 | insn ^= 0x00010000; | |
18068 | } | |
4a6a3df4 AO |
18069 | break; |
18070 | ||
18071 | case 0: | |
18072 | /* bltz 0x04000000 bgez 0x04010000 | |
54f4ddb3 | 18073 | bltzal 0x04100000 bgezal 0x04110000 */ |
9c2799c2 | 18074 | gas_assert ((insn & 0xfc0e0000) == 0x04000000); |
4a6a3df4 AO |
18075 | insn ^= 0x00010000; |
18076 | break; | |
b34976b6 | 18077 | |
4a6a3df4 AO |
18078 | case 1: |
18079 | /* beq 0x10000000 bne 0x14000000 | |
54f4ddb3 | 18080 | blez 0x18000000 bgtz 0x1c000000 */ |
4a6a3df4 AO |
18081 | insn ^= 0x04000000; |
18082 | break; | |
18083 | ||
18084 | default: | |
18085 | abort (); | |
18086 | } | |
18087 | } | |
18088 | ||
18089 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
18090 | { | |
18091 | /* Clear the and-link bit. */ | |
9c2799c2 | 18092 | gas_assert ((insn & 0xfc1c0000) == 0x04100000); |
4a6a3df4 | 18093 | |
54f4ddb3 TS |
18094 | /* bltzal 0x04100000 bgezal 0x04110000 |
18095 | bltzall 0x04120000 bgezall 0x04130000 */ | |
4a6a3df4 AO |
18096 | insn &= ~0x00100000; |
18097 | } | |
18098 | ||
18099 | /* Branch over the branch (if the branch was likely) or the | |
18100 | full jump (not likely case). Compute the offset from the | |
18101 | current instruction to branch to. */ | |
18102 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18103 | i = 16; | |
18104 | else | |
18105 | { | |
18106 | /* How many bytes in instructions we've already emitted? */ | |
4d68580a | 18107 | i = buf - fragp->fr_literal - fragp->fr_fix; |
4a6a3df4 AO |
18108 | /* How many bytes in instructions from here to the end? */ |
18109 | i = fragp->fr_var - i; | |
18110 | } | |
18111 | /* Convert to instruction count. */ | |
18112 | i >>= 2; | |
18113 | /* Branch counts from the next instruction. */ | |
b34976b6 | 18114 | i--; |
4a6a3df4 AO |
18115 | insn |= i; |
18116 | /* Branch over the jump. */ | |
4d68580a | 18117 | buf = write_insn (buf, insn); |
4a6a3df4 | 18118 | |
54f4ddb3 | 18119 | /* nop */ |
4d68580a | 18120 | buf = write_insn (buf, 0); |
4a6a3df4 AO |
18121 | |
18122 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18123 | { | |
18124 | /* beql $0, $0, 2f */ | |
18125 | insn = 0x50000000; | |
18126 | /* Compute the PC offset from the current instruction to | |
18127 | the end of the variable frag. */ | |
18128 | /* How many bytes in instructions we've already emitted? */ | |
4d68580a | 18129 | i = buf - fragp->fr_literal - fragp->fr_fix; |
4a6a3df4 AO |
18130 | /* How many bytes in instructions from here to the end? */ |
18131 | i = fragp->fr_var - i; | |
18132 | /* Convert to instruction count. */ | |
18133 | i >>= 2; | |
18134 | /* Don't decrement i, because we want to branch over the | |
18135 | delay slot. */ | |
4a6a3df4 | 18136 | insn |= i; |
4a6a3df4 | 18137 | |
4d68580a RS |
18138 | buf = write_insn (buf, insn); |
18139 | buf = write_insn (buf, 0); | |
4a6a3df4 AO |
18140 | } |
18141 | ||
18142 | uncond: | |
ce8ad872 | 18143 | if (!RELAX_BRANCH_PIC (fragp->fr_subtype)) |
4a6a3df4 AO |
18144 | { |
18145 | /* j or jal. */ | |
18146 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
18147 | ? 0x0c000000 : 0x08000000); | |
18148 | exp.X_op = O_symbol; | |
18149 | exp.X_add_symbol = fragp->fr_symbol; | |
18150 | exp.X_add_number = fragp->fr_offset; | |
18151 | ||
4d68580a RS |
18152 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
18153 | FALSE, BFD_RELOC_MIPS_JMP); | |
4a6a3df4 AO |
18154 | fixp->fx_file = fragp->fr_file; |
18155 | fixp->fx_line = fragp->fr_line; | |
18156 | ||
4d68580a | 18157 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18158 | } |
18159 | else | |
18160 | { | |
66b3e8da MR |
18161 | unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype); |
18162 | ||
4a6a3df4 | 18163 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ |
66b3e8da MR |
18164 | insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000; |
18165 | insn |= at << OP_SH_RT; | |
4a6a3df4 AO |
18166 | exp.X_op = O_symbol; |
18167 | exp.X_add_symbol = fragp->fr_symbol; | |
18168 | exp.X_add_number = fragp->fr_offset; | |
18169 | ||
18170 | if (fragp->fr_offset) | |
18171 | { | |
18172 | exp.X_add_symbol = make_expr_symbol (&exp); | |
18173 | exp.X_add_number = 0; | |
18174 | } | |
18175 | ||
4d68580a RS |
18176 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
18177 | FALSE, BFD_RELOC_MIPS_GOT16); | |
4a6a3df4 AO |
18178 | fixp->fx_file = fragp->fr_file; |
18179 | fixp->fx_line = fragp->fr_line; | |
18180 | ||
4d68580a | 18181 | buf = write_insn (buf, insn); |
b34976b6 | 18182 | |
4a6a3df4 | 18183 | if (mips_opts.isa == ISA_MIPS1) |
4d68580a RS |
18184 | /* nop */ |
18185 | buf = write_insn (buf, 0); | |
4a6a3df4 AO |
18186 | |
18187 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
66b3e8da MR |
18188 | insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000; |
18189 | insn |= at << OP_SH_RS | at << OP_SH_RT; | |
4a6a3df4 | 18190 | |
4d68580a RS |
18191 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
18192 | FALSE, BFD_RELOC_LO16); | |
4a6a3df4 AO |
18193 | fixp->fx_file = fragp->fr_file; |
18194 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 18195 | |
4d68580a | 18196 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18197 | |
18198 | /* j(al)r $at. */ | |
18199 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
66b3e8da | 18200 | insn = 0x0000f809; |
4a6a3df4 | 18201 | else |
66b3e8da MR |
18202 | insn = 0x00000008; |
18203 | insn |= at << OP_SH_RS; | |
4a6a3df4 | 18204 | |
4d68580a | 18205 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18206 | } |
18207 | } | |
18208 | ||
4a6a3df4 | 18209 | fragp->fr_fix += fragp->fr_var; |
4d68580a | 18210 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
4a6a3df4 AO |
18211 | return; |
18212 | } | |
18213 | ||
df58fc94 RS |
18214 | /* Relax microMIPS branches. */ |
18215 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) | |
18216 | { | |
4d68580a | 18217 | char *buf = fragp->fr_literal + fragp->fr_fix; |
df58fc94 | 18218 | bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); |
8484fb75 | 18219 | bfd_boolean insn32 = RELAX_MICROMIPS_INSN32 (fragp->fr_subtype); |
7bd374a4 | 18220 | bfd_boolean nods = RELAX_MICROMIPS_NODS (fragp->fr_subtype); |
ce8ad872 | 18221 | bfd_boolean pic = RELAX_MICROMIPS_PIC (fragp->fr_subtype); |
df58fc94 RS |
18222 | bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype); |
18223 | int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
2309ddf2 | 18224 | bfd_boolean short_ds; |
df58fc94 RS |
18225 | unsigned long insn; |
18226 | expressionS exp; | |
18227 | fixS *fixp; | |
18228 | ||
18229 | exp.X_op = O_symbol; | |
18230 | exp.X_add_symbol = fragp->fr_symbol; | |
18231 | exp.X_add_number = fragp->fr_offset; | |
18232 | ||
18233 | fragp->fr_fix += fragp->fr_var; | |
18234 | ||
18235 | /* Handle 16-bit branches that fit or are forced to fit. */ | |
18236 | if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
18237 | { | |
18238 | /* We generate a fixup instead of applying it right now, | |
18239 | because if there is linker relaxation, we're going to | |
18240 | need the relocations. */ | |
18241 | if (type == 'D') | |
4d68580a | 18242 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE, |
df58fc94 RS |
18243 | BFD_RELOC_MICROMIPS_10_PCREL_S1); |
18244 | else if (type == 'E') | |
4d68580a | 18245 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE, |
df58fc94 RS |
18246 | BFD_RELOC_MICROMIPS_7_PCREL_S1); |
18247 | else | |
18248 | abort (); | |
18249 | ||
18250 | fixp->fx_file = fragp->fr_file; | |
18251 | fixp->fx_line = fragp->fr_line; | |
18252 | ||
18253 | /* These relocations can have an addend that won't fit in | |
18254 | 2 octets. */ | |
18255 | fixp->fx_no_overflow = 1; | |
18256 | ||
18257 | return; | |
18258 | } | |
18259 | ||
2309ddf2 | 18260 | /* Handle 32-bit branches that fit or are forced to fit. */ |
df58fc94 RS |
18261 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) |
18262 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
18263 | { | |
18264 | /* We generate a fixup instead of applying it right now, | |
18265 | because if there is linker relaxation, we're going to | |
18266 | need the relocations. */ | |
4d68580a RS |
18267 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE, |
18268 | BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
df58fc94 RS |
18269 | fixp->fx_file = fragp->fr_file; |
18270 | fixp->fx_line = fragp->fr_line; | |
18271 | ||
18272 | if (type == 0) | |
7bd374a4 MR |
18273 | { |
18274 | insn = read_compressed_insn (buf, 4); | |
18275 | buf += 4; | |
18276 | ||
18277 | if (nods) | |
18278 | { | |
18279 | /* Check the short-delay-slot bit. */ | |
18280 | if (!al || (insn & 0x02000000) != 0) | |
18281 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
18282 | else | |
18283 | buf = write_compressed_insn (buf, 0x00000000, 4); | |
18284 | } | |
18285 | ||
18286 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); | |
18287 | return; | |
18288 | } | |
df58fc94 RS |
18289 | } |
18290 | ||
18291 | /* Relax 16-bit branches to 32-bit branches. */ | |
18292 | if (type != 0) | |
18293 | { | |
4d68580a | 18294 | insn = read_compressed_insn (buf, 2); |
df58fc94 RS |
18295 | |
18296 | if ((insn & 0xfc00) == 0xcc00) /* b16 */ | |
18297 | insn = 0x94000000; /* beq */ | |
18298 | else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */ | |
18299 | { | |
18300 | unsigned long regno; | |
18301 | ||
18302 | regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD; | |
18303 | regno = micromips_to_32_reg_d_map [regno]; | |
18304 | insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */ | |
18305 | insn |= regno << MICROMIPSOP_SH_RS; | |
18306 | } | |
18307 | else | |
18308 | abort (); | |
18309 | ||
18310 | /* Nothing else to do, just write it out. */ | |
18311 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) | |
18312 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
18313 | { | |
4d68580a | 18314 | buf = write_compressed_insn (buf, insn, 4); |
7bd374a4 MR |
18315 | if (nods) |
18316 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
4d68580a | 18317 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
df58fc94 RS |
18318 | return; |
18319 | } | |
18320 | } | |
18321 | else | |
4d68580a | 18322 | insn = read_compressed_insn (buf, 4); |
df58fc94 RS |
18323 | |
18324 | /* Relax 32-bit branches to a sequence of instructions. */ | |
18325 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
1661c76c | 18326 | _("relaxed out-of-range branch into a jump")); |
df58fc94 | 18327 | |
2309ddf2 | 18328 | /* Set the short-delay-slot bit. */ |
7bd374a4 | 18329 | short_ds = !al || (insn & 0x02000000) != 0; |
df58fc94 RS |
18330 | |
18331 | if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype)) | |
18332 | { | |
18333 | symbolS *l; | |
18334 | ||
18335 | /* Reverse the branch. */ | |
18336 | if ((insn & 0xfc000000) == 0x94000000 /* beq */ | |
18337 | || (insn & 0xfc000000) == 0xb4000000) /* bne */ | |
18338 | insn ^= 0x20000000; | |
18339 | else if ((insn & 0xffe00000) == 0x40000000 /* bltz */ | |
18340 | || (insn & 0xffe00000) == 0x40400000 /* bgez */ | |
18341 | || (insn & 0xffe00000) == 0x40800000 /* blez */ | |
18342 | || (insn & 0xffe00000) == 0x40c00000 /* bgtz */ | |
18343 | || (insn & 0xffe00000) == 0x40a00000 /* bnezc */ | |
18344 | || (insn & 0xffe00000) == 0x40e00000 /* beqzc */ | |
18345 | || (insn & 0xffe00000) == 0x40200000 /* bltzal */ | |
18346 | || (insn & 0xffe00000) == 0x40600000 /* bgezal */ | |
18347 | || (insn & 0xffe00000) == 0x42200000 /* bltzals */ | |
18348 | || (insn & 0xffe00000) == 0x42600000) /* bgezals */ | |
18349 | insn ^= 0x00400000; | |
18350 | else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */ | |
18351 | || (insn & 0xffe30000) == 0x43a00000 /* bc1t */ | |
18352 | || (insn & 0xffe30000) == 0x42800000 /* bc2f */ | |
18353 | || (insn & 0xffe30000) == 0x42a00000) /* bc2t */ | |
18354 | insn ^= 0x00200000; | |
56d438b1 CF |
18355 | else if ((insn & 0xff000000) == 0x83000000 /* BZ.df |
18356 | BNZ.df */ | |
18357 | || (insn & 0xff600000) == 0x81600000) /* BZ.V | |
18358 | BNZ.V */ | |
18359 | insn ^= 0x00800000; | |
df58fc94 RS |
18360 | else |
18361 | abort (); | |
18362 | ||
18363 | if (al) | |
18364 | { | |
18365 | /* Clear the and-link and short-delay-slot bits. */ | |
18366 | gas_assert ((insn & 0xfda00000) == 0x40200000); | |
18367 | ||
18368 | /* bltzal 0x40200000 bgezal 0x40600000 */ | |
18369 | /* bltzals 0x42200000 bgezals 0x42600000 */ | |
18370 | insn &= ~0x02200000; | |
18371 | } | |
18372 | ||
18373 | /* Make a label at the end for use with the branch. */ | |
18374 | l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp); | |
18375 | micromips_label_inc (); | |
f3ded42a | 18376 | S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l))); |
df58fc94 RS |
18377 | |
18378 | /* Refer to it. */ | |
4d68580a RS |
18379 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE, |
18380 | BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
df58fc94 RS |
18381 | fixp->fx_file = fragp->fr_file; |
18382 | fixp->fx_line = fragp->fr_line; | |
18383 | ||
18384 | /* Branch over the jump. */ | |
4d68580a | 18385 | buf = write_compressed_insn (buf, insn, 4); |
8484fb75 | 18386 | |
df58fc94 | 18387 | if (!compact) |
8484fb75 MR |
18388 | { |
18389 | /* nop */ | |
18390 | if (insn32) | |
18391 | buf = write_compressed_insn (buf, 0x00000000, 4); | |
18392 | else | |
18393 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
18394 | } | |
df58fc94 RS |
18395 | } |
18396 | ||
ce8ad872 | 18397 | if (!pic) |
df58fc94 | 18398 | { |
7bd374a4 MR |
18399 | unsigned long jal = (short_ds || nods |
18400 | ? 0x74000000 : 0xf4000000); /* jal/s */ | |
2309ddf2 | 18401 | |
df58fc94 RS |
18402 | /* j/jal/jals <sym> R_MICROMIPS_26_S1 */ |
18403 | insn = al ? jal : 0xd4000000; | |
18404 | ||
4d68580a RS |
18405 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
18406 | BFD_RELOC_MICROMIPS_JMP); | |
df58fc94 RS |
18407 | fixp->fx_file = fragp->fr_file; |
18408 | fixp->fx_line = fragp->fr_line; | |
18409 | ||
4d68580a | 18410 | buf = write_compressed_insn (buf, insn, 4); |
8484fb75 | 18411 | |
7bd374a4 | 18412 | if (compact || nods) |
8484fb75 MR |
18413 | { |
18414 | /* nop */ | |
18415 | if (insn32) | |
18416 | buf = write_compressed_insn (buf, 0x00000000, 4); | |
18417 | else | |
18418 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
18419 | } | |
df58fc94 RS |
18420 | } |
18421 | else | |
18422 | { | |
18423 | unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype); | |
18424 | ||
18425 | /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */ | |
18426 | insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000; | |
18427 | insn |= at << MICROMIPSOP_SH_RT; | |
18428 | ||
18429 | if (exp.X_add_number) | |
18430 | { | |
18431 | exp.X_add_symbol = make_expr_symbol (&exp); | |
18432 | exp.X_add_number = 0; | |
18433 | } | |
18434 | ||
4d68580a RS |
18435 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
18436 | BFD_RELOC_MICROMIPS_GOT16); | |
df58fc94 RS |
18437 | fixp->fx_file = fragp->fr_file; |
18438 | fixp->fx_line = fragp->fr_line; | |
18439 | ||
4d68580a | 18440 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 RS |
18441 | |
18442 | /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */ | |
18443 | insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000; | |
18444 | insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS; | |
18445 | ||
4d68580a RS |
18446 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
18447 | BFD_RELOC_MICROMIPS_LO16); | |
df58fc94 RS |
18448 | fixp->fx_file = fragp->fr_file; |
18449 | fixp->fx_line = fragp->fr_line; | |
18450 | ||
4d68580a | 18451 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 | 18452 | |
8484fb75 MR |
18453 | if (insn32) |
18454 | { | |
18455 | /* jr/jalr $at */ | |
18456 | insn = 0x00000f3c | (al ? RA : ZERO) << MICROMIPSOP_SH_RT; | |
18457 | insn |= at << MICROMIPSOP_SH_RS; | |
18458 | ||
18459 | buf = write_compressed_insn (buf, insn, 4); | |
df58fc94 | 18460 | |
7bd374a4 | 18461 | if (compact || nods) |
8484fb75 MR |
18462 | /* nop */ |
18463 | buf = write_compressed_insn (buf, 0x00000000, 4); | |
18464 | } | |
18465 | else | |
18466 | { | |
18467 | /* jr/jrc/jalr/jalrs $at */ | |
18468 | unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */ | |
7bd374a4 | 18469 | unsigned long jr = compact || nods ? 0x45a0 : 0x4580; /* jr/c */ |
8484fb75 MR |
18470 | |
18471 | insn = al ? jalr : jr; | |
18472 | insn |= at << MICROMIPSOP_SH_MJ; | |
18473 | ||
18474 | buf = write_compressed_insn (buf, insn, 2); | |
7bd374a4 MR |
18475 | if (al && nods) |
18476 | { | |
18477 | /* nop */ | |
18478 | if (short_ds) | |
18479 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
18480 | else | |
18481 | buf = write_compressed_insn (buf, 0x00000000, 4); | |
18482 | } | |
8484fb75 | 18483 | } |
df58fc94 RS |
18484 | } |
18485 | ||
4d68580a | 18486 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
df58fc94 RS |
18487 | return; |
18488 | } | |
18489 | ||
252b5132 RH |
18490 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
18491 | { | |
18492 | int type; | |
3ccad066 | 18493 | const struct mips_int_operand *operand; |
252b5132 | 18494 | offsetT val; |
5c04167a | 18495 | char *buf; |
8507b6e7 | 18496 | unsigned int user_length; |
9d862524 | 18497 | bfd_boolean need_reloc; |
252b5132 | 18498 | unsigned long insn; |
8507b6e7 | 18499 | bfd_boolean mac; |
5c04167a | 18500 | bfd_boolean ext; |
88a7ef16 | 18501 | segT symsec; |
252b5132 RH |
18502 | |
18503 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
3ccad066 | 18504 | operand = mips16_immed_operand (type, FALSE); |
252b5132 | 18505 | |
8507b6e7 | 18506 | mac = RELAX_MIPS16_MACRO (fragp->fr_subtype); |
5c04167a | 18507 | ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype); |
88a7ef16 | 18508 | val = resolve_symbol_value (fragp->fr_symbol) + fragp->fr_offset; |
9d862524 MR |
18509 | |
18510 | symsec = S_GET_SEGMENT (fragp->fr_symbol); | |
18511 | need_reloc = (S_FORCE_RELOC (fragp->fr_symbol, TRUE) | |
8507b6e7 | 18512 | || (operand->root.type == OP_PCREL && !mac |
9d862524 MR |
18513 | ? asec != symsec |
18514 | : !bfd_is_abs_section (symsec))); | |
18515 | ||
8507b6e7 | 18516 | if (operand->root.type == OP_PCREL && !mac) |
252b5132 | 18517 | { |
3ccad066 | 18518 | const struct mips_pcrel_operand *pcrel_op; |
252b5132 | 18519 | |
3ccad066 | 18520 | pcrel_op = (const struct mips_pcrel_operand *) operand; |
252b5132 | 18521 | |
14f72d45 | 18522 | if (pcrel_op->include_isa_bit && !need_reloc) |
252b5132 | 18523 | { |
14f72d45 MR |
18524 | if (!ELF_ST_IS_MIPS16 (S_GET_OTHER (fragp->fr_symbol))) |
18525 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
18526 | _("branch to a symbol in another ISA mode")); | |
18527 | else if ((fragp->fr_offset & 0x1) != 0) | |
18528 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
18529 | _("branch to misaligned address (0x%lx)"), | |
18530 | (long) val); | |
252b5132 | 18531 | } |
252b5132 | 18532 | |
14f72d45 | 18533 | val = mips16_pcrel_val (fragp, pcrel_op, val, 0); |
252b5132 RH |
18534 | |
18535 | /* Make sure the section winds up with the alignment we have | |
18536 | assumed. */ | |
3ccad066 RS |
18537 | if (operand->shift > 0) |
18538 | record_alignment (asec, operand->shift); | |
252b5132 RH |
18539 | } |
18540 | ||
8507b6e7 MR |
18541 | if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) |
18542 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
18543 | { | |
18544 | if (mac) | |
18545 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
18546 | _("macro instruction expanded into multiple " | |
18547 | "instructions in a branch delay slot")); | |
18548 | else if (ext) | |
18549 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
18550 | _("extended instruction in a branch delay slot")); | |
18551 | } | |
18552 | else if (RELAX_MIPS16_NOMACRO (fragp->fr_subtype) && mac) | |
252b5132 | 18553 | as_warn_where (fragp->fr_file, fragp->fr_line, |
8507b6e7 MR |
18554 | _("macro instruction expanded into multiple " |
18555 | "instructions")); | |
252b5132 | 18556 | |
5c04167a | 18557 | buf = fragp->fr_literal + fragp->fr_fix; |
252b5132 | 18558 | |
4d68580a | 18559 | insn = read_compressed_insn (buf, 2); |
5c04167a RS |
18560 | if (ext) |
18561 | insn |= MIPS16_EXTEND; | |
252b5132 | 18562 | |
5c04167a RS |
18563 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) |
18564 | user_length = 4; | |
18565 | else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
18566 | user_length = 2; | |
18567 | else | |
18568 | user_length = 0; | |
18569 | ||
8507b6e7 | 18570 | if (mac) |
c9775dde | 18571 | { |
8507b6e7 MR |
18572 | unsigned long reg; |
18573 | unsigned long new; | |
18574 | unsigned long op; | |
18575 | ||
18576 | gas_assert (type == 'A' || type == 'B' || type == 'E'); | |
18577 | gas_assert (RELAX_MIPS16_SYM32 (fragp->fr_subtype)); | |
c9775dde | 18578 | |
8507b6e7 | 18579 | if (need_reloc) |
c9775dde | 18580 | { |
8507b6e7 MR |
18581 | fixS *fixp; |
18582 | ||
18583 | gas_assert (!RELAX_MIPS16_PIC (fragp->fr_subtype)); | |
18584 | ||
18585 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, | |
18586 | fragp->fr_symbol, fragp->fr_offset, | |
18587 | FALSE, BFD_RELOC_MIPS16_HI16_S); | |
18588 | fixp->fx_file = fragp->fr_file; | |
18589 | fixp->fx_line = fragp->fr_line; | |
18590 | ||
18591 | fixp = fix_new (fragp, buf - fragp->fr_literal + 8, 4, | |
18592 | fragp->fr_symbol, fragp->fr_offset, | |
18593 | FALSE, BFD_RELOC_MIPS16_LO16); | |
18594 | fixp->fx_file = fragp->fr_file; | |
18595 | fixp->fx_line = fragp->fr_line; | |
18596 | ||
18597 | val = 0; | |
18598 | } | |
18599 | ||
18600 | switch (insn & 0xf800) | |
18601 | { | |
18602 | case 0x0800: /* ADDIU */ | |
18603 | reg = (insn >> 8) & 0x7; | |
18604 | op = 0xf0004800 | (reg << 8); | |
c9775dde | 18605 | break; |
8507b6e7 MR |
18606 | case 0xb000: /* LW */ |
18607 | reg = (insn >> 8) & 0x7; | |
18608 | op = 0xf0009800 | (reg << 8) | (reg << 5); | |
c9775dde | 18609 | break; |
8507b6e7 MR |
18610 | case 0xf800: /* I64 */ |
18611 | reg = (insn >> 5) & 0x7; | |
18612 | switch (insn & 0x0700) | |
18613 | { | |
18614 | case 0x0400: /* LD */ | |
18615 | op = 0xf0003800 | (reg << 8) | (reg << 5); | |
18616 | break; | |
18617 | case 0x0600: /* DADDIU */ | |
18618 | op = 0xf000fd00 | (reg << 5); | |
18619 | break; | |
18620 | default: | |
18621 | abort (); | |
18622 | } | |
18623 | break; | |
18624 | default: | |
18625 | abort (); | |
c9775dde | 18626 | } |
8507b6e7 MR |
18627 | |
18628 | new = 0xf0006800 | (reg << 8); /* LI */ | |
18629 | new |= mips16_immed_extend ((val + 0x8000) >> 16, 16); | |
18630 | buf = write_compressed_insn (buf, new, 4); | |
18631 | new = 0xf4003000 | (reg << 8) | (reg << 5); /* SLL */ | |
18632 | buf = write_compressed_insn (buf, new, 4); | |
18633 | op |= mips16_immed_extend (val, 16); | |
18634 | buf = write_compressed_insn (buf, op, 4); | |
18635 | ||
18636 | fragp->fr_fix += 12; | |
18637 | } | |
18638 | else | |
18639 | { | |
18640 | unsigned int length = ext ? 4 : 2; | |
18641 | ||
18642 | if (need_reloc) | |
c9775dde | 18643 | { |
8507b6e7 MR |
18644 | bfd_reloc_code_real_type reloc = BFD_RELOC_NONE; |
18645 | expressionS exp; | |
18646 | fixS *fixp; | |
c9775dde | 18647 | |
8507b6e7 MR |
18648 | switch (type) |
18649 | { | |
18650 | case 'p': | |
18651 | case 'q': | |
18652 | reloc = BFD_RELOC_MIPS16_16_PCREL_S1; | |
18653 | break; | |
18654 | default: | |
18655 | break; | |
18656 | } | |
18657 | if (mac || reloc == BFD_RELOC_NONE) | |
18658 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
18659 | _("unsupported relocation")); | |
18660 | else if (ext) | |
18661 | { | |
18662 | exp.X_op = O_symbol; | |
18663 | exp.X_add_symbol = fragp->fr_symbol; | |
18664 | exp.X_add_number = fragp->fr_offset; | |
c9775dde | 18665 | |
8507b6e7 MR |
18666 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
18667 | TRUE, reloc); | |
18668 | ||
18669 | fixp->fx_file = fragp->fr_file; | |
18670 | fixp->fx_line = fragp->fr_line; | |
18671 | } | |
18672 | else | |
18673 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
18674 | _("invalid unextended operand value")); | |
c9775dde | 18675 | } |
eefc3365 | 18676 | else |
8507b6e7 MR |
18677 | mips16_immed (fragp->fr_file, fragp->fr_line, type, |
18678 | BFD_RELOC_UNUSED, val, user_length, &insn); | |
252b5132 | 18679 | |
8507b6e7 MR |
18680 | gas_assert (mips16_opcode_length (insn) == length); |
18681 | write_compressed_insn (buf, insn, length); | |
18682 | fragp->fr_fix += length; | |
18683 | } | |
252b5132 RH |
18684 | } |
18685 | else | |
18686 | { | |
df58fc94 RS |
18687 | relax_substateT subtype = fragp->fr_subtype; |
18688 | bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0; | |
18689 | bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0; | |
4d7206a2 RS |
18690 | int first, second; |
18691 | fixS *fixp; | |
252b5132 | 18692 | |
df58fc94 RS |
18693 | first = RELAX_FIRST (subtype); |
18694 | second = RELAX_SECOND (subtype); | |
4d7206a2 | 18695 | fixp = (fixS *) fragp->fr_opcode; |
252b5132 | 18696 | |
df58fc94 RS |
18697 | /* If the delay slot chosen does not match the size of the instruction, |
18698 | then emit a warning. */ | |
18699 | if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0) | |
18700 | || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)) | |
18701 | { | |
18702 | relax_substateT s; | |
18703 | const char *msg; | |
18704 | ||
18705 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
18706 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
18707 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
18708 | msg = macro_warning (s); | |
18709 | if (msg != NULL) | |
db9b2be4 | 18710 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
df58fc94 RS |
18711 | subtype &= ~s; |
18712 | } | |
18713 | ||
584892a6 | 18714 | /* Possibly emit a warning if we've chosen the longer option. */ |
df58fc94 | 18715 | if (use_second == second_longer) |
584892a6 | 18716 | { |
df58fc94 RS |
18717 | relax_substateT s; |
18718 | const char *msg; | |
18719 | ||
18720 | s = (subtype | |
18721 | & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT)); | |
18722 | msg = macro_warning (s); | |
18723 | if (msg != NULL) | |
db9b2be4 | 18724 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
df58fc94 | 18725 | subtype &= ~s; |
584892a6 RS |
18726 | } |
18727 | ||
4d7206a2 RS |
18728 | /* Go through all the fixups for the first sequence. Disable them |
18729 | (by marking them as done) if we're going to use the second | |
18730 | sequence instead. */ | |
18731 | while (fixp | |
18732 | && fixp->fx_frag == fragp | |
18733 | && fixp->fx_where < fragp->fr_fix - second) | |
18734 | { | |
df58fc94 | 18735 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18736 | fixp->fx_done = 1; |
18737 | fixp = fixp->fx_next; | |
18738 | } | |
252b5132 | 18739 | |
4d7206a2 RS |
18740 | /* Go through the fixups for the second sequence. Disable them if |
18741 | we're going to use the first sequence, otherwise adjust their | |
18742 | addresses to account for the relaxation. */ | |
18743 | while (fixp && fixp->fx_frag == fragp) | |
18744 | { | |
df58fc94 | 18745 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18746 | fixp->fx_where -= first; |
18747 | else | |
18748 | fixp->fx_done = 1; | |
18749 | fixp = fixp->fx_next; | |
18750 | } | |
18751 | ||
18752 | /* Now modify the frag contents. */ | |
df58fc94 | 18753 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18754 | { |
18755 | char *start; | |
18756 | ||
18757 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
18758 | memmove (start, start + first, second); | |
18759 | fragp->fr_fix -= first; | |
18760 | } | |
18761 | else | |
18762 | fragp->fr_fix -= second; | |
252b5132 RH |
18763 | } |
18764 | } | |
18765 | ||
252b5132 RH |
18766 | /* This function is called after the relocs have been generated. |
18767 | We've been storing mips16 text labels as odd. Here we convert them | |
18768 | back to even for the convenience of the debugger. */ | |
18769 | ||
18770 | void | |
17a2f251 | 18771 | mips_frob_file_after_relocs (void) |
252b5132 RH |
18772 | { |
18773 | asymbol **syms; | |
18774 | unsigned int count, i; | |
18775 | ||
252b5132 RH |
18776 | syms = bfd_get_outsymbols (stdoutput); |
18777 | count = bfd_get_symcount (stdoutput); | |
18778 | for (i = 0; i < count; i++, syms++) | |
df58fc94 RS |
18779 | if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other) |
18780 | && ((*syms)->value & 1) != 0) | |
18781 | { | |
18782 | (*syms)->value &= ~1; | |
18783 | /* If the symbol has an odd size, it was probably computed | |
18784 | incorrectly, so adjust that as well. */ | |
18785 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
18786 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
18787 | } | |
252b5132 RH |
18788 | } |
18789 | ||
a1facbec MR |
18790 | /* This function is called whenever a label is defined, including fake |
18791 | labels instantiated off the dot special symbol. It is used when | |
18792 | handling branch delays; if a branch has a label, we assume we cannot | |
18793 | move it. This also bumps the value of the symbol by 1 in compressed | |
18794 | code. */ | |
252b5132 | 18795 | |
e1b47bd5 | 18796 | static void |
a1facbec | 18797 | mips_record_label (symbolS *sym) |
252b5132 | 18798 | { |
a8dbcb85 | 18799 | segment_info_type *si = seg_info (now_seg); |
252b5132 RH |
18800 | struct insn_label_list *l; |
18801 | ||
18802 | if (free_insn_labels == NULL) | |
325801bd | 18803 | l = XNEW (struct insn_label_list); |
252b5132 RH |
18804 | else |
18805 | { | |
18806 | l = free_insn_labels; | |
18807 | free_insn_labels = l->next; | |
18808 | } | |
18809 | ||
18810 | l->label = sym; | |
a8dbcb85 TS |
18811 | l->next = si->label_list; |
18812 | si->label_list = l; | |
a1facbec | 18813 | } |
07a53e5c | 18814 | |
a1facbec MR |
18815 | /* This function is called as tc_frob_label() whenever a label is defined |
18816 | and adds a DWARF-2 record we only want for true labels. */ | |
18817 | ||
18818 | void | |
18819 | mips_define_label (symbolS *sym) | |
18820 | { | |
18821 | mips_record_label (sym); | |
07a53e5c | 18822 | dwarf2_emit_label (sym); |
252b5132 | 18823 | } |
e1b47bd5 RS |
18824 | |
18825 | /* This function is called by tc_new_dot_label whenever a new dot symbol | |
18826 | is defined. */ | |
18827 | ||
18828 | void | |
18829 | mips_add_dot_label (symbolS *sym) | |
18830 | { | |
18831 | mips_record_label (sym); | |
18832 | if (mips_assembling_insn && HAVE_CODE_COMPRESSION) | |
18833 | mips_compressed_mark_label (sym); | |
18834 | } | |
252b5132 | 18835 | \f |
351cdf24 MF |
18836 | /* Converting ASE flags from internal to .MIPS.abiflags values. */ |
18837 | static unsigned int | |
18838 | mips_convert_ase_flags (int ase) | |
18839 | { | |
18840 | unsigned int ext_ases = 0; | |
18841 | ||
18842 | if (ase & ASE_DSP) | |
18843 | ext_ases |= AFL_ASE_DSP; | |
18844 | if (ase & ASE_DSPR2) | |
18845 | ext_ases |= AFL_ASE_DSPR2; | |
8f4f9071 MF |
18846 | if (ase & ASE_DSPR3) |
18847 | ext_ases |= AFL_ASE_DSPR3; | |
351cdf24 MF |
18848 | if (ase & ASE_EVA) |
18849 | ext_ases |= AFL_ASE_EVA; | |
18850 | if (ase & ASE_MCU) | |
18851 | ext_ases |= AFL_ASE_MCU; | |
18852 | if (ase & ASE_MDMX) | |
18853 | ext_ases |= AFL_ASE_MDMX; | |
18854 | if (ase & ASE_MIPS3D) | |
18855 | ext_ases |= AFL_ASE_MIPS3D; | |
18856 | if (ase & ASE_MT) | |
18857 | ext_ases |= AFL_ASE_MT; | |
18858 | if (ase & ASE_SMARTMIPS) | |
18859 | ext_ases |= AFL_ASE_SMARTMIPS; | |
18860 | if (ase & ASE_VIRT) | |
18861 | ext_ases |= AFL_ASE_VIRT; | |
18862 | if (ase & ASE_MSA) | |
18863 | ext_ases |= AFL_ASE_MSA; | |
18864 | if (ase & ASE_XPA) | |
18865 | ext_ases |= AFL_ASE_XPA; | |
18866 | ||
18867 | return ext_ases; | |
18868 | } | |
252b5132 RH |
18869 | /* Some special processing for a MIPS ELF file. */ |
18870 | ||
18871 | void | |
17a2f251 | 18872 | mips_elf_final_processing (void) |
252b5132 | 18873 | { |
351cdf24 MF |
18874 | int fpabi; |
18875 | Elf_Internal_ABIFlags_v0 flags; | |
18876 | ||
18877 | flags.version = 0; | |
18878 | flags.isa_rev = 0; | |
18879 | switch (file_mips_opts.isa) | |
18880 | { | |
18881 | case INSN_ISA1: | |
18882 | flags.isa_level = 1; | |
18883 | break; | |
18884 | case INSN_ISA2: | |
18885 | flags.isa_level = 2; | |
18886 | break; | |
18887 | case INSN_ISA3: | |
18888 | flags.isa_level = 3; | |
18889 | break; | |
18890 | case INSN_ISA4: | |
18891 | flags.isa_level = 4; | |
18892 | break; | |
18893 | case INSN_ISA5: | |
18894 | flags.isa_level = 5; | |
18895 | break; | |
18896 | case INSN_ISA32: | |
18897 | flags.isa_level = 32; | |
18898 | flags.isa_rev = 1; | |
18899 | break; | |
18900 | case INSN_ISA32R2: | |
18901 | flags.isa_level = 32; | |
18902 | flags.isa_rev = 2; | |
18903 | break; | |
18904 | case INSN_ISA32R3: | |
18905 | flags.isa_level = 32; | |
18906 | flags.isa_rev = 3; | |
18907 | break; | |
18908 | case INSN_ISA32R5: | |
18909 | flags.isa_level = 32; | |
18910 | flags.isa_rev = 5; | |
18911 | break; | |
09c14161 MF |
18912 | case INSN_ISA32R6: |
18913 | flags.isa_level = 32; | |
18914 | flags.isa_rev = 6; | |
18915 | break; | |
351cdf24 MF |
18916 | case INSN_ISA64: |
18917 | flags.isa_level = 64; | |
18918 | flags.isa_rev = 1; | |
18919 | break; | |
18920 | case INSN_ISA64R2: | |
18921 | flags.isa_level = 64; | |
18922 | flags.isa_rev = 2; | |
18923 | break; | |
18924 | case INSN_ISA64R3: | |
18925 | flags.isa_level = 64; | |
18926 | flags.isa_rev = 3; | |
18927 | break; | |
18928 | case INSN_ISA64R5: | |
18929 | flags.isa_level = 64; | |
18930 | flags.isa_rev = 5; | |
18931 | break; | |
09c14161 MF |
18932 | case INSN_ISA64R6: |
18933 | flags.isa_level = 64; | |
18934 | flags.isa_rev = 6; | |
18935 | break; | |
351cdf24 MF |
18936 | } |
18937 | ||
18938 | flags.gpr_size = file_mips_opts.gp == 32 ? AFL_REG_32 : AFL_REG_64; | |
18939 | flags.cpr1_size = file_mips_opts.soft_float ? AFL_REG_NONE | |
18940 | : (file_mips_opts.ase & ASE_MSA) ? AFL_REG_128 | |
18941 | : (file_mips_opts.fp == 64) ? AFL_REG_64 | |
18942 | : AFL_REG_32; | |
18943 | flags.cpr2_size = AFL_REG_NONE; | |
18944 | flags.fp_abi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, | |
18945 | Tag_GNU_MIPS_ABI_FP); | |
18946 | flags.isa_ext = bfd_mips_isa_ext (stdoutput); | |
18947 | flags.ases = mips_convert_ase_flags (file_mips_opts.ase); | |
18948 | if (file_ase_mips16) | |
18949 | flags.ases |= AFL_ASE_MIPS16; | |
18950 | if (file_ase_micromips) | |
18951 | flags.ases |= AFL_ASE_MICROMIPS; | |
18952 | flags.flags1 = 0; | |
18953 | if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts.isa, file_mips_opts.arch) | |
18954 | || file_mips_opts.fp == 64) | |
18955 | && file_mips_opts.oddspreg) | |
18956 | flags.flags1 |= AFL_FLAGS1_ODDSPREG; | |
18957 | flags.flags2 = 0; | |
18958 | ||
18959 | bfd_mips_elf_swap_abiflags_v0_out (stdoutput, &flags, | |
18960 | ((Elf_External_ABIFlags_v0 *) | |
18961 | mips_flags_frag)); | |
18962 | ||
252b5132 | 18963 | /* Write out the register information. */ |
316f5878 | 18964 | if (mips_abi != N64_ABI) |
252b5132 RH |
18965 | { |
18966 | Elf32_RegInfo s; | |
18967 | ||
18968 | s.ri_gprmask = mips_gprmask; | |
18969 | s.ri_cprmask[0] = mips_cprmask[0]; | |
18970 | s.ri_cprmask[1] = mips_cprmask[1]; | |
18971 | s.ri_cprmask[2] = mips_cprmask[2]; | |
18972 | s.ri_cprmask[3] = mips_cprmask[3]; | |
18973 | /* The gp_value field is set by the MIPS ELF backend. */ | |
18974 | ||
18975 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
18976 | ((Elf32_External_RegInfo *) | |
18977 | mips_regmask_frag)); | |
18978 | } | |
18979 | else | |
18980 | { | |
18981 | Elf64_Internal_RegInfo s; | |
18982 | ||
18983 | s.ri_gprmask = mips_gprmask; | |
18984 | s.ri_pad = 0; | |
18985 | s.ri_cprmask[0] = mips_cprmask[0]; | |
18986 | s.ri_cprmask[1] = mips_cprmask[1]; | |
18987 | s.ri_cprmask[2] = mips_cprmask[2]; | |
18988 | s.ri_cprmask[3] = mips_cprmask[3]; | |
18989 | /* The gp_value field is set by the MIPS ELF backend. */ | |
18990 | ||
18991 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
18992 | ((Elf64_External_RegInfo *) | |
18993 | mips_regmask_frag)); | |
18994 | } | |
18995 | ||
18996 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
18997 | sort of BFD interface for this. */ | |
18998 | if (mips_any_noreorder) | |
18999 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
19000 | if (mips_pic != NO_PIC) | |
143d77c5 | 19001 | { |
8b828383 | 19002 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
19003 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
19004 | } | |
19005 | if (mips_abicalls) | |
19006 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 19007 | |
b015e599 AP |
19008 | /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags |
19009 | defined at present; this might need to change in future. */ | |
a4672219 TS |
19010 | if (file_ase_mips16) |
19011 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
df58fc94 RS |
19012 | if (file_ase_micromips) |
19013 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS; | |
919731af | 19014 | if (file_mips_opts.ase & ASE_MDMX) |
deec1734 | 19015 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; |
1f25f5d3 | 19016 | |
bdaaa2e1 | 19017 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 19018 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 19019 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 19020 | else if (mips_abi == O64_ABI) |
252b5132 | 19021 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 19022 | else if (mips_abi == EABI_ABI) |
252b5132 | 19023 | { |
bad1aba3 | 19024 | if (file_mips_opts.gp == 64) |
252b5132 RH |
19025 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
19026 | else | |
19027 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
19028 | } | |
316f5878 | 19029 | else if (mips_abi == N32_ABI) |
be00bddd TS |
19030 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
19031 | ||
c9914766 | 19032 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
19033 | |
19034 | if (mips_32bitmode) | |
19035 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
ad3fea08 | 19036 | |
7361da2c | 19037 | if (mips_nan2008 == 1) |
ba92f887 MR |
19038 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NAN2008; |
19039 | ||
ad3fea08 | 19040 | /* 32 bit code with 64 bit FP registers. */ |
351cdf24 MF |
19041 | fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, |
19042 | Tag_GNU_MIPS_ABI_FP); | |
19043 | if (fpabi == Val_GNU_MIPS_ABI_FP_OLD_64) | |
f1c38003 | 19044 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_FP64; |
252b5132 | 19045 | } |
252b5132 | 19046 | \f |
beae10d5 | 19047 | typedef struct proc { |
9b2f1d35 EC |
19048 | symbolS *func_sym; |
19049 | symbolS *func_end_sym; | |
beae10d5 KH |
19050 | unsigned long reg_mask; |
19051 | unsigned long reg_offset; | |
19052 | unsigned long fpreg_mask; | |
19053 | unsigned long fpreg_offset; | |
19054 | unsigned long frame_offset; | |
19055 | unsigned long frame_reg; | |
19056 | unsigned long pc_reg; | |
19057 | } procS; | |
252b5132 RH |
19058 | |
19059 | static procS cur_proc; | |
19060 | static procS *cur_proc_ptr; | |
19061 | static int numprocs; | |
19062 | ||
df58fc94 RS |
19063 | /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop |
19064 | as "2", and a normal nop as "0". */ | |
19065 | ||
19066 | #define NOP_OPCODE_MIPS 0 | |
19067 | #define NOP_OPCODE_MIPS16 1 | |
19068 | #define NOP_OPCODE_MICROMIPS 2 | |
742a56fe RS |
19069 | |
19070 | char | |
19071 | mips_nop_opcode (void) | |
19072 | { | |
df58fc94 RS |
19073 | if (seg_info (now_seg)->tc_segment_info_data.micromips) |
19074 | return NOP_OPCODE_MICROMIPS; | |
19075 | else if (seg_info (now_seg)->tc_segment_info_data.mips16) | |
19076 | return NOP_OPCODE_MIPS16; | |
19077 | else | |
19078 | return NOP_OPCODE_MIPS; | |
742a56fe RS |
19079 | } |
19080 | ||
df58fc94 RS |
19081 | /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use |
19082 | 32-bit microMIPS NOPs here (if applicable). */ | |
a19d8eb0 | 19083 | |
0a9ef439 | 19084 | void |
17a2f251 | 19085 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 19086 | { |
df58fc94 | 19087 | char nop_opcode; |
742a56fe | 19088 | char *p; |
c67a084a NC |
19089 | int bytes, size, excess; |
19090 | valueT opcode; | |
742a56fe | 19091 | |
0a9ef439 RH |
19092 | if (fragp->fr_type != rs_align_code) |
19093 | return; | |
19094 | ||
742a56fe | 19095 | p = fragp->fr_literal + fragp->fr_fix; |
df58fc94 RS |
19096 | nop_opcode = *p; |
19097 | switch (nop_opcode) | |
a19d8eb0 | 19098 | { |
df58fc94 RS |
19099 | case NOP_OPCODE_MICROMIPS: |
19100 | opcode = micromips_nop32_insn.insn_opcode; | |
19101 | size = 4; | |
19102 | break; | |
19103 | case NOP_OPCODE_MIPS16: | |
c67a084a NC |
19104 | opcode = mips16_nop_insn.insn_opcode; |
19105 | size = 2; | |
df58fc94 RS |
19106 | break; |
19107 | case NOP_OPCODE_MIPS: | |
19108 | default: | |
c67a084a NC |
19109 | opcode = nop_insn.insn_opcode; |
19110 | size = 4; | |
df58fc94 | 19111 | break; |
c67a084a | 19112 | } |
a19d8eb0 | 19113 | |
c67a084a NC |
19114 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
19115 | excess = bytes % size; | |
df58fc94 RS |
19116 | |
19117 | /* Handle the leading part if we're not inserting a whole number of | |
19118 | instructions, and make it the end of the fixed part of the frag. | |
19119 | Try to fit in a short microMIPS NOP if applicable and possible, | |
19120 | and use zeroes otherwise. */ | |
19121 | gas_assert (excess < 4); | |
19122 | fragp->fr_fix += excess; | |
19123 | switch (excess) | |
c67a084a | 19124 | { |
df58fc94 RS |
19125 | case 3: |
19126 | *p++ = '\0'; | |
19127 | /* Fall through. */ | |
19128 | case 2: | |
833794fc | 19129 | if (nop_opcode == NOP_OPCODE_MICROMIPS && !mips_opts.insn32) |
df58fc94 | 19130 | { |
4d68580a | 19131 | p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2); |
df58fc94 RS |
19132 | break; |
19133 | } | |
19134 | *p++ = '\0'; | |
19135 | /* Fall through. */ | |
19136 | case 1: | |
19137 | *p++ = '\0'; | |
19138 | /* Fall through. */ | |
19139 | case 0: | |
19140 | break; | |
a19d8eb0 | 19141 | } |
c67a084a NC |
19142 | |
19143 | md_number_to_chars (p, opcode, size); | |
19144 | fragp->fr_var = size; | |
a19d8eb0 CP |
19145 | } |
19146 | ||
252b5132 | 19147 | static long |
17a2f251 | 19148 | get_number (void) |
252b5132 RH |
19149 | { |
19150 | int negative = 0; | |
19151 | long val = 0; | |
19152 | ||
19153 | if (*input_line_pointer == '-') | |
19154 | { | |
19155 | ++input_line_pointer; | |
19156 | negative = 1; | |
19157 | } | |
3882b010 | 19158 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 19159 | as_bad (_("expected simple number")); |
252b5132 RH |
19160 | if (input_line_pointer[0] == '0') |
19161 | { | |
19162 | if (input_line_pointer[1] == 'x') | |
19163 | { | |
19164 | input_line_pointer += 2; | |
3882b010 | 19165 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
19166 | { |
19167 | val <<= 4; | |
19168 | val |= hex_value (*input_line_pointer++); | |
19169 | } | |
19170 | return negative ? -val : val; | |
19171 | } | |
19172 | else | |
19173 | { | |
19174 | ++input_line_pointer; | |
3882b010 | 19175 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
19176 | { |
19177 | val <<= 3; | |
19178 | val |= *input_line_pointer++ - '0'; | |
19179 | } | |
19180 | return negative ? -val : val; | |
19181 | } | |
19182 | } | |
3882b010 | 19183 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
19184 | { |
19185 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
19186 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 19187 | as_warn (_("invalid number")); |
252b5132 RH |
19188 | return -1; |
19189 | } | |
3882b010 | 19190 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
19191 | { |
19192 | val *= 10; | |
19193 | val += *input_line_pointer++ - '0'; | |
19194 | } | |
19195 | return negative ? -val : val; | |
19196 | } | |
19197 | ||
19198 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
19199 | is an initial number which is the ECOFF file index. In the non-ECOFF |
19200 | case .file implies DWARF-2. */ | |
19201 | ||
19202 | static void | |
17a2f251 | 19203 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 19204 | { |
ecb4347a DJ |
19205 | static int first_file_directive = 0; |
19206 | ||
c5dd6aab DJ |
19207 | if (ECOFF_DEBUGGING) |
19208 | { | |
19209 | get_number (); | |
19210 | s_app_file (0); | |
19211 | } | |
19212 | else | |
ecb4347a DJ |
19213 | { |
19214 | char *filename; | |
19215 | ||
19216 | filename = dwarf2_directive_file (0); | |
19217 | ||
19218 | /* Versions of GCC up to 3.1 start files with a ".file" | |
19219 | directive even for stabs output. Make sure that this | |
19220 | ".file" is handled. Note that you need a version of GCC | |
19221 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
19222 | if (filename != NULL && ! first_file_directive) | |
19223 | { | |
19224 | (void) new_logical_line (filename, -1); | |
c04f5787 | 19225 | s_app_file_string (filename, 0); |
ecb4347a DJ |
19226 | } |
19227 | first_file_directive = 1; | |
19228 | } | |
c5dd6aab DJ |
19229 | } |
19230 | ||
19231 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
19232 | |
19233 | static void | |
17a2f251 | 19234 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 19235 | { |
c5dd6aab DJ |
19236 | if (!ECOFF_DEBUGGING) |
19237 | dwarf2_directive_loc (0); | |
252b5132 RH |
19238 | } |
19239 | ||
252b5132 RH |
19240 | /* The .end directive. */ |
19241 | ||
19242 | static void | |
17a2f251 | 19243 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
19244 | { |
19245 | symbolS *p; | |
252b5132 | 19246 | |
7a621144 DJ |
19247 | /* Following functions need their own .frame and .cprestore directives. */ |
19248 | mips_frame_reg_valid = 0; | |
19249 | mips_cprestore_valid = 0; | |
19250 | ||
252b5132 RH |
19251 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
19252 | { | |
19253 | p = get_symbol (); | |
19254 | demand_empty_rest_of_line (); | |
19255 | } | |
19256 | else | |
19257 | p = NULL; | |
19258 | ||
14949570 | 19259 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
19260 | as_warn (_(".end not in text section")); |
19261 | ||
19262 | if (!cur_proc_ptr) | |
19263 | { | |
1661c76c | 19264 | as_warn (_(".end directive without a preceding .ent directive")); |
252b5132 RH |
19265 | demand_empty_rest_of_line (); |
19266 | return; | |
19267 | } | |
19268 | ||
19269 | if (p != NULL) | |
19270 | { | |
9c2799c2 | 19271 | gas_assert (S_GET_NAME (p)); |
9b2f1d35 | 19272 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
1661c76c | 19273 | as_warn (_(".end symbol does not match .ent symbol")); |
ecb4347a DJ |
19274 | |
19275 | if (debug_type == DEBUG_STABS) | |
19276 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
19277 | S_GET_NAME (p)); | |
252b5132 RH |
19278 | } |
19279 | else | |
19280 | as_warn (_(".end directive missing or unknown symbol")); | |
19281 | ||
9b2f1d35 EC |
19282 | /* Create an expression to calculate the size of the function. */ |
19283 | if (p && cur_proc_ptr) | |
19284 | { | |
19285 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
325801bd | 19286 | expressionS *exp = XNEW (expressionS); |
9b2f1d35 EC |
19287 | |
19288 | obj->size = exp; | |
19289 | exp->X_op = O_subtract; | |
19290 | exp->X_add_symbol = symbol_temp_new_now (); | |
19291 | exp->X_op_symbol = p; | |
19292 | exp->X_add_number = 0; | |
19293 | ||
19294 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
19295 | } | |
19296 | ||
5ff6a06c MR |
19297 | #ifdef md_flush_pending_output |
19298 | md_flush_pending_output (); | |
19299 | #endif | |
19300 | ||
ecb4347a | 19301 | /* Generate a .pdr section. */ |
f3ded42a | 19302 | if (!ECOFF_DEBUGGING && mips_flag_pdr) |
ecb4347a DJ |
19303 | { |
19304 | segT saved_seg = now_seg; | |
19305 | subsegT saved_subseg = now_subseg; | |
ecb4347a DJ |
19306 | expressionS exp; |
19307 | char *fragp; | |
252b5132 | 19308 | |
9c2799c2 | 19309 | gas_assert (pdr_seg); |
ecb4347a | 19310 | subseg_set (pdr_seg, 0); |
252b5132 | 19311 | |
ecb4347a DJ |
19312 | /* Write the symbol. */ |
19313 | exp.X_op = O_symbol; | |
19314 | exp.X_add_symbol = p; | |
19315 | exp.X_add_number = 0; | |
19316 | emit_expr (&exp, 4); | |
252b5132 | 19317 | |
ecb4347a | 19318 | fragp = frag_more (7 * 4); |
252b5132 | 19319 | |
17a2f251 TS |
19320 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
19321 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
19322 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
19323 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
19324 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
19325 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
19326 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 19327 | |
ecb4347a DJ |
19328 | subseg_set (saved_seg, saved_subseg); |
19329 | } | |
252b5132 RH |
19330 | |
19331 | cur_proc_ptr = NULL; | |
19332 | } | |
19333 | ||
19334 | /* The .aent and .ent directives. */ | |
19335 | ||
19336 | static void | |
17a2f251 | 19337 | s_mips_ent (int aent) |
252b5132 | 19338 | { |
252b5132 | 19339 | symbolS *symbolP; |
252b5132 RH |
19340 | |
19341 | symbolP = get_symbol (); | |
19342 | if (*input_line_pointer == ',') | |
f9419b05 | 19343 | ++input_line_pointer; |
252b5132 | 19344 | SKIP_WHITESPACE (); |
3882b010 | 19345 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 19346 | || *input_line_pointer == '-') |
874e8986 | 19347 | get_number (); |
252b5132 | 19348 | |
14949570 | 19349 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
1661c76c | 19350 | as_warn (_(".ent or .aent not in text section")); |
252b5132 RH |
19351 | |
19352 | if (!aent && cur_proc_ptr) | |
9a41af64 | 19353 | as_warn (_("missing .end")); |
252b5132 RH |
19354 | |
19355 | if (!aent) | |
19356 | { | |
7a621144 DJ |
19357 | /* This function needs its own .frame and .cprestore directives. */ |
19358 | mips_frame_reg_valid = 0; | |
19359 | mips_cprestore_valid = 0; | |
19360 | ||
252b5132 RH |
19361 | cur_proc_ptr = &cur_proc; |
19362 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
19363 | ||
9b2f1d35 | 19364 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 19365 | |
f9419b05 | 19366 | ++numprocs; |
ecb4347a DJ |
19367 | |
19368 | if (debug_type == DEBUG_STABS) | |
19369 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
19370 | S_GET_NAME (symbolP)); | |
252b5132 RH |
19371 | } |
19372 | ||
7c0fc524 MR |
19373 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
19374 | ||
252b5132 RH |
19375 | demand_empty_rest_of_line (); |
19376 | } | |
19377 | ||
19378 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 19379 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 19380 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 19381 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
19382 | symbol table (in the mdebug section). */ |
19383 | ||
19384 | static void | |
17a2f251 | 19385 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 19386 | { |
f3ded42a RS |
19387 | if (ECOFF_DEBUGGING) |
19388 | s_ignore (ignore); | |
19389 | else | |
ecb4347a DJ |
19390 | { |
19391 | long val; | |
252b5132 | 19392 | |
ecb4347a DJ |
19393 | if (cur_proc_ptr == (procS *) NULL) |
19394 | { | |
19395 | as_warn (_(".frame outside of .ent")); | |
19396 | demand_empty_rest_of_line (); | |
19397 | return; | |
19398 | } | |
252b5132 | 19399 | |
ecb4347a DJ |
19400 | cur_proc_ptr->frame_reg = tc_get_register (1); |
19401 | ||
19402 | SKIP_WHITESPACE (); | |
19403 | if (*input_line_pointer++ != ',' | |
19404 | || get_absolute_expression_and_terminator (&val) != ',') | |
19405 | { | |
1661c76c | 19406 | as_warn (_("bad .frame directive")); |
ecb4347a DJ |
19407 | --input_line_pointer; |
19408 | demand_empty_rest_of_line (); | |
19409 | return; | |
19410 | } | |
252b5132 | 19411 | |
ecb4347a DJ |
19412 | cur_proc_ptr->frame_offset = val; |
19413 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 19414 | |
252b5132 | 19415 | demand_empty_rest_of_line (); |
252b5132 | 19416 | } |
252b5132 RH |
19417 | } |
19418 | ||
bdaaa2e1 KH |
19419 | /* The .fmask and .mask directives. If the mdebug section is present |
19420 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 19421 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 19422 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
19423 | make reference to the ecoff symbol table (in the mdebug section). */ |
19424 | ||
19425 | static void | |
17a2f251 | 19426 | s_mips_mask (int reg_type) |
252b5132 | 19427 | { |
f3ded42a RS |
19428 | if (ECOFF_DEBUGGING) |
19429 | s_ignore (reg_type); | |
19430 | else | |
252b5132 | 19431 | { |
ecb4347a | 19432 | long mask, off; |
252b5132 | 19433 | |
ecb4347a DJ |
19434 | if (cur_proc_ptr == (procS *) NULL) |
19435 | { | |
19436 | as_warn (_(".mask/.fmask outside of .ent")); | |
19437 | demand_empty_rest_of_line (); | |
19438 | return; | |
19439 | } | |
252b5132 | 19440 | |
ecb4347a DJ |
19441 | if (get_absolute_expression_and_terminator (&mask) != ',') |
19442 | { | |
1661c76c | 19443 | as_warn (_("bad .mask/.fmask directive")); |
ecb4347a DJ |
19444 | --input_line_pointer; |
19445 | demand_empty_rest_of_line (); | |
19446 | return; | |
19447 | } | |
252b5132 | 19448 | |
ecb4347a DJ |
19449 | off = get_absolute_expression (); |
19450 | ||
19451 | if (reg_type == 'F') | |
19452 | { | |
19453 | cur_proc_ptr->fpreg_mask = mask; | |
19454 | cur_proc_ptr->fpreg_offset = off; | |
19455 | } | |
19456 | else | |
19457 | { | |
19458 | cur_proc_ptr->reg_mask = mask; | |
19459 | cur_proc_ptr->reg_offset = off; | |
19460 | } | |
19461 | ||
19462 | demand_empty_rest_of_line (); | |
252b5132 | 19463 | } |
252b5132 RH |
19464 | } |
19465 | ||
316f5878 RS |
19466 | /* A table describing all the processors gas knows about. Names are |
19467 | matched in the order listed. | |
e7af610e | 19468 | |
316f5878 RS |
19469 | To ease comparison, please keep this table in the same order as |
19470 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
19471 | static const struct mips_cpu_info mips_cpu_info_table[] = |
19472 | { | |
316f5878 | 19473 | /* Entries for generic ISAs */ |
d16afab6 RS |
19474 | { "mips1", MIPS_CPU_IS_ISA, 0, ISA_MIPS1, CPU_R3000 }, |
19475 | { "mips2", MIPS_CPU_IS_ISA, 0, ISA_MIPS2, CPU_R6000 }, | |
19476 | { "mips3", MIPS_CPU_IS_ISA, 0, ISA_MIPS3, CPU_R4000 }, | |
19477 | { "mips4", MIPS_CPU_IS_ISA, 0, ISA_MIPS4, CPU_R8000 }, | |
19478 | { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 }, | |
19479 | { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 }, | |
19480 | { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ae52f483 AB |
19481 | { "mips32r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R3, CPU_MIPS32R3 }, |
19482 | { "mips32r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R5, CPU_MIPS32R5 }, | |
7361da2c | 19483 | { "mips32r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R6, CPU_MIPS32R6 }, |
d16afab6 RS |
19484 | { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 }, |
19485 | { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 }, | |
ae52f483 AB |
19486 | { "mips64r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R3, CPU_MIPS64R3 }, |
19487 | { "mips64r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R5, CPU_MIPS64R5 }, | |
7361da2c | 19488 | { "mips64r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R6, CPU_MIPS64R6 }, |
316f5878 RS |
19489 | |
19490 | /* MIPS I */ | |
d16afab6 RS |
19491 | { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 }, |
19492 | { "r2000", 0, 0, ISA_MIPS1, CPU_R3000 }, | |
19493 | { "r3900", 0, 0, ISA_MIPS1, CPU_R3900 }, | |
316f5878 RS |
19494 | |
19495 | /* MIPS II */ | |
d16afab6 | 19496 | { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 }, |
316f5878 RS |
19497 | |
19498 | /* MIPS III */ | |
d16afab6 RS |
19499 | { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 }, |
19500 | { "r4010", 0, 0, ISA_MIPS2, CPU_R4010 }, | |
19501 | { "vr4100", 0, 0, ISA_MIPS3, CPU_VR4100 }, | |
19502 | { "vr4111", 0, 0, ISA_MIPS3, CPU_R4111 }, | |
19503 | { "vr4120", 0, 0, ISA_MIPS3, CPU_VR4120 }, | |
19504 | { "vr4130", 0, 0, ISA_MIPS3, CPU_VR4120 }, | |
19505 | { "vr4181", 0, 0, ISA_MIPS3, CPU_R4111 }, | |
19506 | { "vr4300", 0, 0, ISA_MIPS3, CPU_R4300 }, | |
19507 | { "r4400", 0, 0, ISA_MIPS3, CPU_R4400 }, | |
19508 | { "r4600", 0, 0, ISA_MIPS3, CPU_R4600 }, | |
19509 | { "orion", 0, 0, ISA_MIPS3, CPU_R4600 }, | |
19510 | { "r4650", 0, 0, ISA_MIPS3, CPU_R4650 }, | |
19511 | { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 }, | |
b15591bb | 19512 | /* ST Microelectronics Loongson 2E and 2F cores */ |
d16afab6 RS |
19513 | { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E }, |
19514 | { "loongson2f", 0, 0, ISA_MIPS3, CPU_LOONGSON_2F }, | |
316f5878 RS |
19515 | |
19516 | /* MIPS IV */ | |
d16afab6 RS |
19517 | { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 }, |
19518 | { "r10000", 0, 0, ISA_MIPS4, CPU_R10000 }, | |
19519 | { "r12000", 0, 0, ISA_MIPS4, CPU_R12000 }, | |
19520 | { "r14000", 0, 0, ISA_MIPS4, CPU_R14000 }, | |
19521 | { "r16000", 0, 0, ISA_MIPS4, CPU_R16000 }, | |
19522 | { "vr5000", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19523 | { "vr5400", 0, 0, ISA_MIPS4, CPU_VR5400 }, | |
19524 | { "vr5500", 0, 0, ISA_MIPS4, CPU_VR5500 }, | |
19525 | { "rm5200", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19526 | { "rm5230", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19527 | { "rm5231", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19528 | { "rm5261", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19529 | { "rm5721", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19530 | { "rm7000", 0, 0, ISA_MIPS4, CPU_RM7000 }, | |
19531 | { "rm9000", 0, 0, ISA_MIPS4, CPU_RM9000 }, | |
316f5878 RS |
19532 | |
19533 | /* MIPS 32 */ | |
d16afab6 RS |
19534 | { "4kc", 0, 0, ISA_MIPS32, CPU_MIPS32 }, |
19535 | { "4km", 0, 0, ISA_MIPS32, CPU_MIPS32 }, | |
19536 | { "4kp", 0, 0, ISA_MIPS32, CPU_MIPS32 }, | |
19537 | { "4ksc", 0, ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 }, | |
ad3fea08 TS |
19538 | |
19539 | /* MIPS 32 Release 2 */ | |
d16afab6 RS |
19540 | { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19541 | { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19542 | { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19543 | { "4ksd", 0, ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19544 | { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19545 | { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19546 | { "m14k", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19547 | { "m14kc", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19548 | { "m14ke", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU, | |
19549 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19550 | { "m14kec", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU, | |
19551 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19552 | { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19553 | { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19554 | { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19555 | { "24kf1_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 19556 | /* Deprecated forms of the above. */ |
d16afab6 RS |
19557 | { "24kfx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19558 | { "24kx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f | 19559 | /* 24KE is a 24K with DSP ASE, other ASEs are optional. */ |
d16afab6 RS |
19560 | { "24kec", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19561 | { "24kef2_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19562 | { "24kef", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19563 | { "24kef1_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 19564 | /* Deprecated forms of the above. */ |
d16afab6 RS |
19565 | { "24kefx", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19566 | { "24kex", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f | 19567 | /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */ |
d16afab6 RS |
19568 | { "34kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19569 | { "34kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19570 | { "34kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19571 | { "34kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 19572 | /* Deprecated forms of the above. */ |
d16afab6 RS |
19573 | { "34kfx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19574 | { "34kx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
711eefe4 | 19575 | /* 34Kn is a 34kc without DSP. */ |
d16afab6 | 19576 | { "34kn", 0, ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 19577 | /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */ |
d16afab6 RS |
19578 | { "74kc", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19579 | { "74kf2_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19580 | { "74kf", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19581 | { "74kf1_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19582 | { "74kf3_2", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 19583 | /* Deprecated forms of the above. */ |
d16afab6 RS |
19584 | { "74kfx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19585 | { "74kx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
30f8113a | 19586 | /* 1004K cores are multiprocessor versions of the 34K. */ |
d16afab6 RS |
19587 | { "1004kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19588 | { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19589 | { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19590 | { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
77403ce9 RS |
19591 | /* interaptiv is the new name for 1004kf */ |
19592 | { "interaptiv", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
c6e5c03a RS |
19593 | /* M5100 family */ |
19594 | { "m5100", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 }, | |
19595 | { "m5101", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 }, | |
bbaa46c0 | 19596 | /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */ |
134c0c8b | 19597 | { "p5600", 0, ASE_VIRT | ASE_EVA | ASE_XPA, ISA_MIPS32R5, CPU_MIPS32R5 }, |
32b26a03 | 19598 | |
316f5878 | 19599 | /* MIPS 64 */ |
d16afab6 RS |
19600 | { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 }, |
19601 | { "5kf", 0, 0, ISA_MIPS64, CPU_MIPS64 }, | |
19602 | { "20kc", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
19603 | { "25kf", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
ad3fea08 | 19604 | |
c7a23324 | 19605 | /* Broadcom SB-1 CPU core */ |
d16afab6 | 19606 | { "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 }, |
1e85aad8 | 19607 | /* Broadcom SB-1A CPU core */ |
d16afab6 | 19608 | { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 }, |
3739860c | 19609 | |
4ba154f5 | 19610 | { "loongson3a", 0, 0, ISA_MIPS64R2, CPU_LOONGSON_3A }, |
e7af610e | 19611 | |
ed163775 MR |
19612 | /* MIPS 64 Release 2 */ |
19613 | ||
967344c6 | 19614 | /* Cavium Networks Octeon CPU core */ |
d16afab6 RS |
19615 | { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON }, |
19616 | { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP }, | |
19617 | { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 }, | |
2c629856 | 19618 | { "octeon3", 0, ASE_VIRT | ASE_VIRT64, ISA_MIPS64R5, CPU_OCTEON3 }, |
967344c6 | 19619 | |
52b6b6b9 | 19620 | /* RMI Xlr */ |
d16afab6 | 19621 | { "xlr", 0, 0, ISA_MIPS64, CPU_XLR }, |
52b6b6b9 | 19622 | |
55a36193 MK |
19623 | /* Broadcom XLP. |
19624 | XLP is mostly like XLR, with the prominent exception that it is | |
19625 | MIPS64R2 rather than MIPS64. */ | |
d16afab6 | 19626 | { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR }, |
55a36193 | 19627 | |
a4968f42 | 19628 | /* MIPS 64 Release 6 */ |
7ef0d297 | 19629 | { "i6400", 0, ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6}, |
a4968f42 | 19630 | { "p6600", 0, ASE_VIRT | ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6}, |
7ef0d297 | 19631 | |
316f5878 | 19632 | /* End marker */ |
d16afab6 | 19633 | { NULL, 0, 0, 0, 0 } |
316f5878 | 19634 | }; |
e7af610e | 19635 | |
84ea6cf2 | 19636 | |
316f5878 RS |
19637 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
19638 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 19639 | |
316f5878 | 19640 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 19641 | |
b34976b6 | 19642 | static bfd_boolean |
17a2f251 | 19643 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
19644 | { |
19645 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
19646 | given++, canonical++; | |
19647 | ||
19648 | return ((*given == 0 && *canonical == 0) | |
19649 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
19650 | } | |
19651 | ||
19652 | ||
19653 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
19654 | CPU name. We've traditionally allowed a lot of variation here. | |
19655 | ||
19656 | Note: this function is shared between GCC and GAS. */ | |
19657 | ||
b34976b6 | 19658 | static bfd_boolean |
17a2f251 | 19659 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
19660 | { |
19661 | /* First see if the name matches exactly, or with a final "000" | |
19662 | turned into "k". */ | |
19663 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 19664 | return TRUE; |
316f5878 RS |
19665 | |
19666 | /* If not, try comparing based on numerical designation alone. | |
19667 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
19668 | if (TOLOWER (*given) == 'r') | |
19669 | given++; | |
19670 | if (!ISDIGIT (*given)) | |
b34976b6 | 19671 | return FALSE; |
316f5878 RS |
19672 | |
19673 | /* Skip over some well-known prefixes in the canonical name, | |
19674 | hoping to find a number there too. */ | |
19675 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
19676 | canonical += 2; | |
19677 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
19678 | canonical += 2; | |
19679 | else if (TOLOWER (canonical[0]) == 'r') | |
19680 | canonical += 1; | |
19681 | ||
19682 | return mips_strict_matching_cpu_name_p (canonical, given); | |
19683 | } | |
19684 | ||
19685 | ||
19686 | /* Parse an option that takes the name of a processor as its argument. | |
19687 | OPTION is the name of the option and CPU_STRING is the argument. | |
19688 | Return the corresponding processor enumeration if the CPU_STRING is | |
19689 | recognized, otherwise report an error and return null. | |
19690 | ||
19691 | A similar function exists in GCC. */ | |
e7af610e NC |
19692 | |
19693 | static const struct mips_cpu_info * | |
17a2f251 | 19694 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 19695 | { |
316f5878 | 19696 | const struct mips_cpu_info *p; |
e7af610e | 19697 | |
316f5878 RS |
19698 | /* 'from-abi' selects the most compatible architecture for the given |
19699 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
19700 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
19701 | version. Look first at the -mgp options, if given, otherwise base | |
19702 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 19703 | |
316f5878 RS |
19704 | Treat NO_ABI like the EABIs. One reason to do this is that the |
19705 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
19706 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
19707 | 'mips64', just as we did in the days before 'from-abi'. */ | |
19708 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
19709 | { | |
19710 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
19711 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
19712 | ||
19713 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
19714 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
19715 | ||
bad1aba3 | 19716 | if (file_mips_opts.gp >= 0) |
19717 | return mips_cpu_info_from_isa (file_mips_opts.gp == 32 | |
0b35dfee | 19718 | ? ISA_MIPS1 : ISA_MIPS3); |
316f5878 RS |
19719 | |
19720 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
19721 | ? ISA_MIPS3 | |
19722 | : ISA_MIPS1); | |
19723 | } | |
19724 | ||
19725 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
19726 | if (strcasecmp (cpu_string, "default") == 0) | |
19727 | return 0; | |
19728 | ||
19729 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
19730 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
19731 | return p; | |
19732 | ||
1661c76c | 19733 | as_bad (_("bad value (%s) for %s"), cpu_string, option); |
316f5878 | 19734 | return 0; |
e7af610e NC |
19735 | } |
19736 | ||
316f5878 RS |
19737 | /* Return the canonical processor information for ISA (a member of the |
19738 | ISA_MIPS* enumeration). */ | |
19739 | ||
e7af610e | 19740 | static const struct mips_cpu_info * |
17a2f251 | 19741 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
19742 | { |
19743 | int i; | |
19744 | ||
19745 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
ad3fea08 | 19746 | if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA) |
316f5878 | 19747 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
19748 | return (&mips_cpu_info_table[i]); |
19749 | ||
e972090a | 19750 | return NULL; |
e7af610e | 19751 | } |
fef14a42 TS |
19752 | |
19753 | static const struct mips_cpu_info * | |
17a2f251 | 19754 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
19755 | { |
19756 | int i; | |
19757 | ||
19758 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
19759 | if (arch == mips_cpu_info_table[i].cpu) | |
19760 | return (&mips_cpu_info_table[i]); | |
19761 | ||
19762 | return NULL; | |
19763 | } | |
316f5878 RS |
19764 | \f |
19765 | static void | |
17a2f251 | 19766 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
19767 | { |
19768 | if (*first_p) | |
19769 | { | |
19770 | fprintf (stream, "%24s", ""); | |
19771 | *col_p = 24; | |
19772 | } | |
19773 | else | |
19774 | { | |
19775 | fprintf (stream, ", "); | |
19776 | *col_p += 2; | |
19777 | } | |
e7af610e | 19778 | |
316f5878 RS |
19779 | if (*col_p + strlen (string) > 72) |
19780 | { | |
19781 | fprintf (stream, "\n%24s", ""); | |
19782 | *col_p = 24; | |
19783 | } | |
19784 | ||
19785 | fprintf (stream, "%s", string); | |
19786 | *col_p += strlen (string); | |
19787 | ||
19788 | *first_p = 0; | |
19789 | } | |
19790 | ||
19791 | void | |
17a2f251 | 19792 | md_show_usage (FILE *stream) |
e7af610e | 19793 | { |
316f5878 RS |
19794 | int column, first; |
19795 | size_t i; | |
19796 | ||
19797 | fprintf (stream, _("\ | |
19798 | MIPS options:\n\ | |
316f5878 RS |
19799 | -EB generate big endian output\n\ |
19800 | -EL generate little endian output\n\ | |
19801 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
19802 | -G NUM allow referencing objects up to NUM bytes\n\ | |
19803 | implicitly with the gp register [default 8]\n")); | |
19804 | fprintf (stream, _("\ | |
19805 | -mips1 generate MIPS ISA I instructions\n\ | |
19806 | -mips2 generate MIPS ISA II instructions\n\ | |
19807 | -mips3 generate MIPS ISA III instructions\n\ | |
19808 | -mips4 generate MIPS ISA IV instructions\n\ | |
19809 | -mips5 generate MIPS ISA V instructions\n\ | |
19810 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 19811 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
ae52f483 AB |
19812 | -mips32r3 generate MIPS32 release 3 ISA instructions\n\ |
19813 | -mips32r5 generate MIPS32 release 5 ISA instructions\n\ | |
7361da2c | 19814 | -mips32r6 generate MIPS32 release 6 ISA instructions\n\ |
316f5878 | 19815 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 19816 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
ae52f483 AB |
19817 | -mips64r3 generate MIPS64 release 3 ISA instructions\n\ |
19818 | -mips64r5 generate MIPS64 release 5 ISA instructions\n\ | |
7361da2c | 19819 | -mips64r6 generate MIPS64 release 6 ISA instructions\n\ |
316f5878 RS |
19820 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
19821 | ||
19822 | first = 1; | |
e7af610e NC |
19823 | |
19824 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
19825 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
19826 | show (stream, "from-abi", &column, &first); | |
19827 | fputc ('\n', stream); | |
e7af610e | 19828 | |
316f5878 RS |
19829 | fprintf (stream, _("\ |
19830 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
19831 | -no-mCPU don't generate code specific to CPU.\n\ | |
19832 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
19833 | ||
19834 | first = 1; | |
19835 | ||
19836 | show (stream, "3900", &column, &first); | |
19837 | show (stream, "4010", &column, &first); | |
19838 | show (stream, "4100", &column, &first); | |
19839 | show (stream, "4650", &column, &first); | |
19840 | fputc ('\n', stream); | |
19841 | ||
19842 | fprintf (stream, _("\ | |
19843 | -mips16 generate mips16 instructions\n\ | |
19844 | -no-mips16 do not generate mips16 instructions\n")); | |
19845 | fprintf (stream, _("\ | |
df58fc94 RS |
19846 | -mmicromips generate microMIPS instructions\n\ |
19847 | -mno-micromips do not generate microMIPS instructions\n")); | |
19848 | fprintf (stream, _("\ | |
e16bfa71 | 19849 | -msmartmips generate smartmips instructions\n\ |
3739860c | 19850 | -mno-smartmips do not generate smartmips instructions\n")); |
e16bfa71 | 19851 | fprintf (stream, _("\ |
74cd071d CF |
19852 | -mdsp generate DSP instructions\n\ |
19853 | -mno-dsp do not generate DSP instructions\n")); | |
19854 | fprintf (stream, _("\ | |
8b082fb1 TS |
19855 | -mdspr2 generate DSP R2 instructions\n\ |
19856 | -mno-dspr2 do not generate DSP R2 instructions\n")); | |
19857 | fprintf (stream, _("\ | |
8f4f9071 MF |
19858 | -mdspr3 generate DSP R3 instructions\n\ |
19859 | -mno-dspr3 do not generate DSP R3 instructions\n")); | |
19860 | fprintf (stream, _("\ | |
ef2e4d86 CF |
19861 | -mmt generate MT instructions\n\ |
19862 | -mno-mt do not generate MT instructions\n")); | |
19863 | fprintf (stream, _("\ | |
dec0624d MR |
19864 | -mmcu generate MCU instructions\n\ |
19865 | -mno-mcu do not generate MCU instructions\n")); | |
19866 | fprintf (stream, _("\ | |
56d438b1 CF |
19867 | -mmsa generate MSA instructions\n\ |
19868 | -mno-msa do not generate MSA instructions\n")); | |
19869 | fprintf (stream, _("\ | |
7d64c587 AB |
19870 | -mxpa generate eXtended Physical Address (XPA) instructions\n\ |
19871 | -mno-xpa do not generate eXtended Physical Address (XPA) instructions\n")); | |
19872 | fprintf (stream, _("\ | |
b015e599 AP |
19873 | -mvirt generate Virtualization instructions\n\ |
19874 | -mno-virt do not generate Virtualization instructions\n")); | |
19875 | fprintf (stream, _("\ | |
833794fc MR |
19876 | -minsn32 only generate 32-bit microMIPS instructions\n\ |
19877 | -mno-insn32 generate all microMIPS instructions\n")); | |
19878 | fprintf (stream, _("\ | |
c67a084a NC |
19879 | -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\ |
19880 | -mfix-loongson2f-nop work around Loongson2F NOP errata\n\ | |
d766e8ec | 19881 | -mfix-vr4120 work around certain VR4120 errata\n\ |
7d8e00cf | 19882 | -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ |
6a32d874 | 19883 | -mfix-24k insert a nop after ERET and DERET instructions\n\ |
d954098f | 19884 | -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\ |
316f5878 RS |
19885 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
19886 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
aed1a261 | 19887 | -msym32 assume all symbols have 32-bit values\n\ |
316f5878 RS |
19888 | -O0 remove unneeded NOPs, do not swap branches\n\ |
19889 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
19890 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ |
19891 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
037b32b9 AN |
19892 | fprintf (stream, _("\ |
19893 | -mhard-float allow floating-point instructions\n\ | |
19894 | -msoft-float do not allow floating-point instructions\n\ | |
19895 | -msingle-float only allow 32-bit floating-point operations\n\ | |
19896 | -mdouble-float allow 32-bit and 64-bit floating-point operations\n\ | |
3bf0dbfb | 19897 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ |
ba92f887 | 19898 | --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\ |
8b10b0b3 MR |
19899 | -mignore-branch-isa accept invalid branches requiring an ISA mode switch\n\ |
19900 | -mno-ignore-branch-isa reject invalid branches requiring an ISA mode switch\n\ | |
ba92f887 MR |
19901 | -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n")); |
19902 | ||
19903 | first = 1; | |
19904 | ||
19905 | show (stream, "legacy", &column, &first); | |
19906 | show (stream, "2008", &column, &first); | |
19907 | ||
19908 | fputc ('\n', stream); | |
19909 | ||
316f5878 RS |
19910 | fprintf (stream, _("\ |
19911 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
861fb55a | 19912 | -call_nonpic generate non-PIC code that can operate with DSOs\n\ |
0c000745 | 19913 | -mvxworks-pic generate VxWorks position independent code\n\ |
861fb55a | 19914 | -non_shared do not generate code that can operate with DSOs\n\ |
316f5878 | 19915 | -xgot assume a 32 bit GOT\n\ |
dcd410fe | 19916 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
bbe506e8 | 19917 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
d821e36b | 19918 | position dependent (non shared) code\n\ |
316f5878 RS |
19919 | -mabi=ABI create ABI conformant object file for:\n")); |
19920 | ||
19921 | first = 1; | |
19922 | ||
19923 | show (stream, "32", &column, &first); | |
19924 | show (stream, "o64", &column, &first); | |
19925 | show (stream, "n32", &column, &first); | |
19926 | show (stream, "64", &column, &first); | |
19927 | show (stream, "eabi", &column, &first); | |
19928 | ||
19929 | fputc ('\n', stream); | |
19930 | ||
19931 | fprintf (stream, _("\ | |
19932 | -32 create o32 ABI object file (default)\n\ | |
19933 | -n32 create n32 ABI object file\n\ | |
19934 | -64 create 64 ABI object file\n")); | |
e7af610e | 19935 | } |
14e777e0 | 19936 | |
1575952e | 19937 | #ifdef TE_IRIX |
14e777e0 | 19938 | enum dwarf2_format |
413a266c | 19939 | mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED) |
14e777e0 | 19940 | { |
369943fe | 19941 | if (HAVE_64BIT_SYMBOLS) |
1575952e | 19942 | return dwarf2_format_64bit_irix; |
14e777e0 KB |
19943 | else |
19944 | return dwarf2_format_32bit; | |
19945 | } | |
1575952e | 19946 | #endif |
73369e65 EC |
19947 | |
19948 | int | |
19949 | mips_dwarf2_addr_size (void) | |
19950 | { | |
6b6b3450 | 19951 | if (HAVE_64BIT_OBJECTS) |
73369e65 | 19952 | return 8; |
73369e65 EC |
19953 | else |
19954 | return 4; | |
19955 | } | |
5862107c EC |
19956 | |
19957 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
19958 | void | |
19959 | mips_cfi_frame_initial_instructions (void) | |
19960 | { | |
19961 | cfi_add_CFA_def_cfa_register (SP); | |
19962 | } | |
19963 | ||
707bfff6 TS |
19964 | int |
19965 | tc_mips_regname_to_dw2regnum (char *regname) | |
19966 | { | |
19967 | unsigned int regnum = -1; | |
19968 | unsigned int reg; | |
19969 | ||
19970 | if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®)) | |
19971 | regnum = reg; | |
19972 | ||
19973 | return regnum; | |
19974 | } | |
263b2574 | 19975 | |
19976 | /* Implement CONVERT_SYMBOLIC_ATTRIBUTE. | |
19977 | Given a symbolic attribute NAME, return the proper integer value. | |
19978 | Returns -1 if the attribute is not known. */ | |
19979 | ||
19980 | int | |
19981 | mips_convert_symbolic_attribute (const char *name) | |
19982 | { | |
19983 | static const struct | |
19984 | { | |
19985 | const char * name; | |
19986 | const int tag; | |
19987 | } | |
19988 | attribute_table[] = | |
19989 | { | |
19990 | #define T(tag) {#tag, tag} | |
19991 | T (Tag_GNU_MIPS_ABI_FP), | |
19992 | T (Tag_GNU_MIPS_ABI_MSA), | |
19993 | #undef T | |
19994 | }; | |
19995 | unsigned int i; | |
19996 | ||
19997 | if (name == NULL) | |
19998 | return -1; | |
19999 | ||
20000 | for (i = 0; i < ARRAY_SIZE (attribute_table); i++) | |
20001 | if (streq (name, attribute_table[i].name)) | |
20002 | return attribute_table[i].tag; | |
20003 | ||
20004 | return -1; | |
20005 | } | |
fd5c94ab RS |
20006 | |
20007 | void | |
20008 | md_mips_end (void) | |
20009 | { | |
351cdf24 MF |
20010 | int fpabi = Val_GNU_MIPS_ABI_FP_ANY; |
20011 | ||
fd5c94ab RS |
20012 | mips_emit_delays (); |
20013 | if (cur_proc_ptr) | |
20014 | as_warn (_("missing .end at end of assembly")); | |
919731af | 20015 | |
20016 | /* Just in case no code was emitted, do the consistency check. */ | |
20017 | file_mips_check_options (); | |
351cdf24 MF |
20018 | |
20019 | /* Set a floating-point ABI if the user did not. */ | |
20020 | if (obj_elf_seen_attribute (OBJ_ATTR_GNU, Tag_GNU_MIPS_ABI_FP)) | |
20021 | { | |
20022 | /* Perform consistency checks on the floating-point ABI. */ | |
20023 | fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, | |
20024 | Tag_GNU_MIPS_ABI_FP); | |
20025 | if (fpabi != Val_GNU_MIPS_ABI_FP_ANY) | |
20026 | check_fpabi (fpabi); | |
20027 | } | |
20028 | else | |
20029 | { | |
20030 | /* Soft-float gets precedence over single-float, the two options should | |
20031 | not be used together so this should not matter. */ | |
20032 | if (file_mips_opts.soft_float == 1) | |
20033 | fpabi = Val_GNU_MIPS_ABI_FP_SOFT; | |
20034 | /* Single-float gets precedence over all double_float cases. */ | |
20035 | else if (file_mips_opts.single_float == 1) | |
20036 | fpabi = Val_GNU_MIPS_ABI_FP_SINGLE; | |
20037 | else | |
20038 | { | |
20039 | switch (file_mips_opts.fp) | |
20040 | { | |
20041 | case 32: | |
20042 | if (file_mips_opts.gp == 32) | |
20043 | fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE; | |
20044 | break; | |
20045 | case 0: | |
20046 | fpabi = Val_GNU_MIPS_ABI_FP_XX; | |
20047 | break; | |
20048 | case 64: | |
20049 | if (file_mips_opts.gp == 32 && !file_mips_opts.oddspreg) | |
20050 | fpabi = Val_GNU_MIPS_ABI_FP_64A; | |
20051 | else if (file_mips_opts.gp == 32) | |
20052 | fpabi = Val_GNU_MIPS_ABI_FP_64; | |
20053 | else | |
20054 | fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE; | |
20055 | break; | |
20056 | } | |
20057 | } | |
20058 | ||
20059 | bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, | |
20060 | Tag_GNU_MIPS_ABI_FP, fpabi); | |
20061 | } | |
fd5c94ab | 20062 | } |
2f0c68f2 CM |
20063 | |
20064 | /* Returns the relocation type required for a particular CFI encoding. */ | |
20065 | ||
20066 | bfd_reloc_code_real_type | |
20067 | mips_cfi_reloc_for_encoding (int encoding) | |
20068 | { | |
20069 | if (encoding == (DW_EH_PE_sdata4 | DW_EH_PE_pcrel)) | |
20070 | return BFD_RELOC_32_PCREL; | |
20071 | else return BFD_RELOC_NONE; | |
20072 | } |