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3d3c5039 ILT |
1 | /* tc-mips.c -- assemble code for a MIPS chip. |
2 | Copyright (C) 1993 Free Software Foundation, Inc. | |
3 | Contributed by the OSF and Ralph Campbell. | |
4 | Written by Keith Knowles and Ralph Campbell, working independently. | |
8358c818 ILT |
5 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus |
6 | Support. | |
3d3c5039 ILT |
7 | |
8 | This file is part of GAS. | |
9 | ||
10 | GAS is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2, or (at your option) | |
13 | any later version. | |
14 | ||
15 | GAS is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
21 | along with GAS; see the file COPYING. If not, write to | |
22 | the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ | |
23 | ||
24 | #include "as.h" | |
8358c818 | 25 | #include "config.h" |
9da4c5d1 | 26 | #include "subsegs.h" |
3d3c5039 ILT |
27 | |
28 | #include <ctype.h> | |
29 | ||
30 | #ifndef __STDC__ | |
31 | #ifndef NO_STDARG | |
32 | #define NO_STDARG | |
33 | #endif | |
34 | #endif | |
35 | ||
36 | #ifndef NO_STDARG | |
37 | #include <stdarg.h> | |
38 | #else | |
39 | #ifndef NO_VARARGS | |
40 | #include <varargs.h> | |
41 | #endif /* NO_VARARGS */ | |
42 | #endif /* NO_STDARG */ | |
43 | ||
918692a5 | 44 | #include "opcode/mips.h" |
3d3c5039 | 45 | |
f2a663d3 ILT |
46 | #ifdef OBJ_ELF |
47 | #include "elf/mips.h" | |
48 | ||
49 | static char *mips_regmask_frag; | |
50 | #endif | |
51 | ||
3d3c5039 | 52 | #define AT 1 |
9226253a | 53 | #define PIC_CALL_REG 25 |
670a50eb | 54 | #define GP 28 |
9226253a ILT |
55 | #define SP 29 |
56 | #define FP 30 | |
3d3c5039 ILT |
57 | #define RA 31 |
58 | ||
88225433 ILT |
59 | /* Decide whether to do GP reference optimizations based on the object |
60 | file format. */ | |
61 | #undef GPOPT | |
62 | #ifdef OBJ_ECOFF | |
63 | #define GPOPT | |
64 | #endif | |
65 | #ifdef OBJ_ELF | |
66 | #define GPOPT | |
67 | #endif | |
68 | ||
04cb3372 ILT |
69 | /* The default target format to use. */ |
70 | #ifdef OBJ_AOUT | |
71 | #ifdef TARGET_BYTES_BIG_ENDIAN | |
72 | #define DEFAULT_TARGET_FORMAT "a.out-mips-big" | |
73 | #else | |
74 | #define DEFAULT_TARGET_FORMAT "a.out-mips-little" | |
75 | #endif | |
76 | #endif /* OBJ_AOUT */ | |
77 | #ifdef OBJ_ECOFF | |
78 | #ifdef TARGET_BYTES_BIG_ENDIAN | |
79 | #define DEFAULT_TARGET_FORMAT "ecoff-bigmips" | |
80 | #else | |
81 | #define DEFAULT_TARGET_FORMAT "ecoff-littlemips" | |
82 | #endif | |
83 | #endif /* OBJ_ECOFF */ | |
84 | #ifdef OBJ_ELF | |
85 | #ifdef TARGET_BYTES_BIG_ENDIAN | |
86 | #define DEFAULT_TARGET_FORMAT "elf32-bigmips" | |
87 | #else | |
88 | #define DEFAULT_TARGET_FORMAT "elf32-littlemips" | |
89 | #endif | |
90 | #endif /* OBJ_ELF */ | |
91 | ||
92 | const char *mips_target_format = DEFAULT_TARGET_FORMAT; | |
93 | ||
d2c71068 ILT |
94 | /* The name of the readonly data section. */ |
95 | #ifdef OBJ_AOUT | |
96 | #define RDATA_SECTION_NAME ".data" | |
97 | #endif | |
98 | #ifdef OBJ_ECOFF | |
99 | #define RDATA_SECTION_NAME ".rdata" | |
100 | #endif | |
101 | #ifdef OBJ_ELF | |
102 | #define RDATA_SECTION_NAME ".rodata" | |
103 | #endif | |
104 | ||
1aa6938e ILT |
105 | /* These variables are filled in with the masks of registers used. |
106 | The object format code reads them and puts them in the appropriate | |
107 | place. */ | |
108 | unsigned long mips_gprmask; | |
109 | unsigned long mips_cprmask[4]; | |
110 | ||
1051c97f ILT |
111 | /* MIPS ISA (Instruction Set Architecture) level (may be changed |
112 | temporarily using .set mipsN). */ | |
8358c818 ILT |
113 | static int mips_isa = -1; |
114 | ||
1051c97f ILT |
115 | /* MIPS ISA we are using for this output file. */ |
116 | static int file_mips_isa; | |
117 | ||
8c63448a | 118 | /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */ |
4bb0cc41 | 119 | static int mips_cpu = -1; |
8c63448a | 120 | |
d9aba805 ILT |
121 | /* MIPS PIC level. */ |
122 | ||
123 | enum mips_pic_level | |
124 | { | |
125 | /* Do not generate PIC code. */ | |
126 | NO_PIC, | |
127 | ||
128 | /* Generate PIC code as in Irix 4. This is not implemented, and I'm | |
129 | not sure what it is supposed to do. */ | |
130 | IRIX4_PIC, | |
131 | ||
132 | /* Generate PIC code as in the SVR4 MIPS ABI. */ | |
133 | SVR4_PIC, | |
134 | ||
135 | /* Generate PIC code without using a global offset table: the data | |
136 | segment has a maximum size of 64K, all data references are off | |
137 | the $gp register, and all text references are PC relative. This | |
138 | is used on some embedded systems. */ | |
139 | EMBEDDED_PIC | |
140 | }; | |
141 | ||
142 | static enum mips_pic_level mips_pic; | |
9226253a | 143 | |
8ea7f4e8 ILT |
144 | /* 1 if trap instructions should used for overflow rather than break |
145 | instructions. */ | |
146 | static int mips_trap; | |
147 | ||
3d3c5039 ILT |
148 | static int mips_warn_about_macros; |
149 | static int mips_noreorder; | |
0dd2d296 | 150 | static int mips_any_noreorder; |
3d3c5039 ILT |
151 | static int mips_nomove; |
152 | static int mips_noat; | |
153 | static int mips_nobopt; | |
154 | ||
88225433 | 155 | #ifdef GPOPT |
670a50eb ILT |
156 | /* The size of the small data section. */ |
157 | static int g_switch_value = 8; | |
42562568 ILT |
158 | /* Whether the -G option was used. */ |
159 | static int g_switch_seen = 0; | |
670a50eb ILT |
160 | #endif |
161 | ||
3d3c5039 ILT |
162 | #define N_RMASK 0xc4 |
163 | #define N_VFP 0xd4 | |
164 | ||
165 | /* handle of the OPCODE hash table */ | |
166 | static struct hash_control *op_hash = NULL; | |
167 | ||
168 | /* This array holds the chars that always start a comment. If the | |
169 | pre-processor is disabled, these aren't very useful */ | |
170 | const char comment_chars[] = "#"; | |
171 | ||
172 | /* This array holds the chars that only start a comment at the beginning of | |
173 | a line. If the line seems to have the form '# 123 filename' | |
174 | .line and .file directives will appear in the pre-processed output */ | |
175 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
176 | first line of the input file. This is because the compiler outputs | |
177 | #NO_APP at the beginning of its output. */ | |
178 | /* Also note that C style comments are always supported. */ | |
179 | const char line_comment_chars[] = "#"; | |
180 | ||
181 | /* This array holds machine specific line separator characters. */ | |
182 | const char line_separator_chars[] = ""; | |
183 | ||
184 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
185 | const char EXP_CHARS[] = "eE"; | |
186 | ||
187 | /* Chars that mean this number is a floating point constant */ | |
188 | /* As in 0f12.456 */ | |
189 | /* or 0d1.2345e12 */ | |
190 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
191 | ||
192 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
193 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
194 | but nothing is ideal around here. | |
195 | */ | |
196 | ||
670a50eb | 197 | static char *insn_error; |
3d3c5039 ILT |
198 | |
199 | static int byte_order = BYTE_ORDER; | |
200 | ||
201 | static int auto_align = 1; | |
becfe05e ILT |
202 | |
203 | /* Symbol labelling the current insn. */ | |
204 | static symbolS *insn_label; | |
205 | ||
9226253a ILT |
206 | /* When outputting SVR4 PIC code, the assembler needs to know the |
207 | offset in the stack frame from which to restore the $gp register. | |
208 | This is set by the .cprestore pseudo-op, and saved in this | |
209 | variable. */ | |
0dd2d296 ILT |
210 | static offsetT mips_cprestore_offset = -1; |
211 | ||
212 | /* This is the register which holds the stack frame, as set by the | |
213 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
214 | static int mips_frame_reg = SP; | |
9226253a | 215 | |
becfe05e ILT |
216 | /* To output NOP instructions correctly, we need to keep information |
217 | about the previous two instructions. */ | |
218 | ||
0aa07269 ILT |
219 | /* Whether we are optimizing. The default value of 2 means to remove |
220 | unneeded NOPs and swap branch instructions when possible. A value | |
221 | of 1 means to not swap branches. A value of 0 means to always | |
222 | insert NOPs. */ | |
223 | static int mips_optimize = 2; | |
4e95866e | 224 | |
becfe05e ILT |
225 | /* The previous instruction. */ |
226 | static struct mips_cl_insn prev_insn; | |
227 | ||
228 | /* The instruction before prev_insn. */ | |
229 | static struct mips_cl_insn prev_prev_insn; | |
230 | ||
231 | /* If we don't want information for prev_insn or prev_prev_insn, we | |
232 | point the insn_mo field at this dummy integer. */ | |
233 | static const struct mips_opcode dummy_opcode = { 0 }; | |
234 | ||
235 | /* Non-zero if prev_insn is valid. */ | |
236 | static int prev_insn_valid; | |
237 | ||
238 | /* The frag for the previous instruction. */ | |
239 | static struct frag *prev_insn_frag; | |
240 | ||
241 | /* The offset into prev_insn_frag for the previous instruction. */ | |
242 | static long prev_insn_where; | |
243 | ||
244 | /* The reloc for the previous instruction, if any. */ | |
245 | static fixS *prev_insn_fixp; | |
246 | ||
247 | /* Non-zero if the previous instruction was in a delay slot. */ | |
248 | static int prev_insn_is_delay_slot; | |
4e95866e ILT |
249 | |
250 | /* Non-zero if the previous instruction was in a .set noreorder. */ | |
251 | static int prev_insn_unreordered; | |
252 | ||
253 | /* Non-zero if the previous previous instruction was in a .set | |
254 | noreorder. */ | |
255 | static int prev_prev_insn_unreordered; | |
3d3c5039 | 256 | \f |
0dd2d296 ILT |
257 | /* Since the MIPS does not have multiple forms of PC relative |
258 | instructions, we do not have to do relaxing as is done on other | |
259 | platforms. However, we do have to handle GP relative addressing | |
260 | correctly, which turns out to be a similar problem. | |
261 | ||
262 | Every macro that refers to a symbol can occur in (at least) two | |
263 | forms, one with GP relative addressing and one without. For | |
264 | example, loading a global variable into a register generally uses | |
23dc1ae3 | 265 | a macro instruction like this: |
0dd2d296 ILT |
266 | lw $4,i |
267 | If i can be addressed off the GP register (this is true if it is in | |
268 | the .sbss or .sdata section, or if it is known to be smaller than | |
269 | the -G argument) this will generate the following instruction: | |
270 | lw $4,i($gp) | |
271 | This instruction will use a GPREL reloc. If i can not be addressed | |
272 | off the GP register, the following instruction sequence will be used: | |
273 | lui $at,i | |
274 | lw $4,i($at) | |
275 | In this case the first instruction will have a HI16 reloc, and the | |
276 | second reloc will have a LO16 reloc. Both relocs will be against | |
277 | the symbol i. | |
278 | ||
279 | The issue here is that we may not know whether i is GP addressable | |
280 | until after we see the instruction that uses it. Therefore, we | |
281 | want to be able to choose the final instruction sequence only at | |
282 | the end of the assembly. This is similar to the way other | |
23dc1ae3 | 283 | platforms choose the size of a PC relative instruction only at the |
0dd2d296 ILT |
284 | end of assembly. |
285 | ||
286 | When generating position independent code we do not use GP | |
23dc1ae3 ILT |
287 | addressing in quite the same way, but the issue still arises as |
288 | external symbols and local symbols must be handled differently. | |
0dd2d296 ILT |
289 | |
290 | We handle these issues by actually generating both possible | |
291 | instruction sequences. The longer one is put in a frag_var with | |
292 | type rs_machine_dependent. We encode what to do with the frag in | |
293 | the subtype field. We encode (1) the number of existing bytes to | |
294 | replace, (2) the number of new bytes to use, (3) the offset from | |
295 | the start of the existing bytes to the first reloc we must generate | |
296 | (that is, the offset is applied from the start of the existing | |
297 | bytes after they are replaced by the new bytes, if any), (4) the | |
298 | offset from the start of the existing bytes to the second reloc, | |
299 | (5) whether a third reloc is needed (the third reloc is always four | |
300 | bytes after the second reloc), and (6) whether to warn if this | |
301 | variant is used (this is sometimes needed if .set nomacro or .set | |
302 | noat is in effect). All these numbers are reasonably small. | |
303 | ||
304 | Generating two instruction sequences must be handled carefully to | |
23dc1ae3 ILT |
305 | ensure that delay slots are handled correctly. Fortunately, there |
306 | are a limited number of cases. When the second instruction | |
307 | sequence is generated, append_insn is directed to maintain the | |
308 | existing delay slot information, so it continues to apply to any | |
309 | code after the second instruction sequence. This means that the | |
310 | second instruction sequence must not impose any requirements not | |
311 | required by the first instruction sequence. | |
0dd2d296 ILT |
312 | |
313 | These variant frags are then handled in functions called by the | |
314 | machine independent code. md_estimate_size_before_relax returns | |
315 | the final size of the frag. md_convert_frag sets up the final form | |
316 | of the frag. tc_gen_reloc adjust the first reloc and adds a second | |
317 | one if needed. */ | |
318 | #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \ | |
319 | ((relax_substateT) \ | |
320 | (((old) << 24) \ | |
321 | | ((new) << 16) \ | |
322 | | (((reloc1) + 64) << 9) \ | |
323 | | (((reloc2) + 64) << 2) \ | |
324 | | ((reloc3) ? (1 << 1) : 0) \ | |
325 | | ((warn) ? 1 : 0))) | |
326 | #define RELAX_OLD(i) (((i) >> 24) & 0xff) | |
327 | #define RELAX_NEW(i) (((i) >> 16) & 0xff) | |
328 | #define RELAX_RELOC1(i) ((((i) >> 9) & 0x7f) - 64) | |
329 | #define RELAX_RELOC2(i) ((((i) >> 2) & 0x7f) - 64) | |
330 | #define RELAX_RELOC3(i) (((i) >> 1) & 1) | |
331 | #define RELAX_WARN(i) ((i) & 1) | |
332 | \f | |
3d3c5039 ILT |
333 | /* Prototypes for static functions. */ |
334 | ||
335 | #ifdef __STDC__ | |
336 | #define internalError() \ | |
337 | as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__) | |
338 | #else | |
339 | #define internalError() as_fatal ("MIPS internal Error"); | |
340 | #endif | |
341 | ||
becfe05e | 342 | static int insn_uses_reg PARAMS ((struct mips_cl_insn *ip, |
604633ae | 343 | unsigned int reg, int fpr)); |
0dd2d296 ILT |
344 | static void append_insn PARAMS ((char *place, |
345 | struct mips_cl_insn * ip, | |
670a50eb | 346 | expressionS * p, |
3d3c5039 | 347 | bfd_reloc_code_real_type r)); |
becfe05e ILT |
348 | static void mips_no_prev_insn PARAMS ((void)); |
349 | static void mips_emit_delays PARAMS ((void)); | |
0dd2d296 | 350 | static void macro_build PARAMS ((char *place, int *counter, expressionS * ep, |
3d3c5039 ILT |
351 | const char *name, const char *fmt, |
352 | ...)); | |
0dd2d296 ILT |
353 | static void macro_build_lui PARAMS ((char *place, int *counter, |
354 | expressionS * ep, int regnum)); | |
6e8dda9c | 355 | static void set_at PARAMS ((int *counter, int reg, int unsignedp)); |
670a50eb | 356 | static void check_absolute_expr PARAMS ((struct mips_cl_insn * ip, |
19ed8960 | 357 | expressionS *)); |
0dd2d296 ILT |
358 | static void load_register PARAMS ((int *counter, int reg, expressionS * ep)); |
359 | static void load_address PARAMS ((int *counter, int reg, expressionS *ep)); | |
670a50eb | 360 | static void macro PARAMS ((struct mips_cl_insn * ip)); |
917fae09 SS |
361 | #ifdef LOSING_COMPILER |
362 | static void macro2 PARAMS ((struct mips_cl_insn * ip)); | |
363 | #endif | |
670a50eb ILT |
364 | static void mips_ip PARAMS ((char *str, struct mips_cl_insn * ip)); |
365 | static int my_getSmallExpression PARAMS ((expressionS * ep, char *str)); | |
366 | static void my_getExpression PARAMS ((expressionS * ep, char *str)); | |
3d3c5039 | 367 | static symbolS *get_symbol PARAMS ((void)); |
23dc1ae3 | 368 | static void mips_align PARAMS ((int to, int fill, symbolS *label)); |
3d3c5039 | 369 | static void s_align PARAMS ((int)); |
becfe05e | 370 | static void s_stringer PARAMS ((int)); |
3d3c5039 ILT |
371 | static void s_change_sec PARAMS ((int)); |
372 | static void s_cons PARAMS ((int)); | |
373 | static void s_err PARAMS ((int)); | |
374 | static void s_extern PARAMS ((int)); | |
375 | static void s_float_cons PARAMS ((int)); | |
c1444ec4 | 376 | static void s_mips_globl PARAMS ((int)); |
3d3c5039 ILT |
377 | static void s_option PARAMS ((int)); |
378 | static void s_mipsset PARAMS ((int)); | |
becfe05e | 379 | static void s_mips_space PARAMS ((int)); |
9226253a ILT |
380 | static void s_abicalls PARAMS ((int)); |
381 | static void s_cpload PARAMS ((int)); | |
382 | static void s_cprestore PARAMS ((int)); | |
0dd2d296 ILT |
383 | static void s_gpword PARAMS ((int)); |
384 | static void s_cpadd PARAMS ((int)); | |
385 | #ifndef ECOFF_DEBUGGING | |
3d3c5039 ILT |
386 | static void md_obj_begin PARAMS ((void)); |
387 | static void md_obj_end PARAMS ((void)); | |
388 | static long get_number PARAMS ((void)); | |
389 | static void s_ent PARAMS ((int)); | |
390 | static void s_mipsend PARAMS ((int)); | |
391 | static void s_file PARAMS ((int)); | |
88225433 | 392 | #if 0 |
3d3c5039 ILT |
393 | static void s_frame PARAMS ((int)); |
394 | static void s_loc PARAMS ((int)); | |
395 | static void s_mask PARAMS ((char)); | |
396 | #endif | |
88225433 | 397 | #endif |
9da4c5d1 ILT |
398 | #ifdef OBJ_ELF |
399 | static void s_elf_section PARAMS ((int)); | |
400 | #endif | |
3d3c5039 ILT |
401 | \f |
402 | /* Pseudo-op table. | |
403 | ||
404 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
405 | should be defined here, but are currently unsupported: .alias, | |
406 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
407 | ||
408 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
409 | specific to the type of debugging information being generated, and | |
410 | should be defined by the object format: .aent, .begin, .bend, | |
411 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
412 | .vreg. | |
413 | ||
414 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
415 | not MIPS CPU specific, but are also not specific to the object file | |
416 | format. This file is probably the best place to define them, but | |
417 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
418 | .struct, .weakext. */ | |
419 | ||
420 | const pseudo_typeS md_pseudo_table[] = | |
421 | { | |
670a50eb ILT |
422 | /* MIPS specific pseudo-ops. */ |
423 | {"option", s_option, 0}, | |
424 | {"set", s_mipsset, 0}, | |
dd3f1f76 ILT |
425 | {"rdata", s_change_sec, 'r'}, |
426 | {"sdata", s_change_sec, 's'}, | |
427 | {"livereg", s_ignore, 0}, | |
9226253a ILT |
428 | { "abicalls", s_abicalls, 0}, |
429 | { "cpload", s_cpload, 0}, | |
430 | { "cprestore", s_cprestore, 0}, | |
0dd2d296 ILT |
431 | { "gpword", s_gpword, 0}, |
432 | { "cpadd", s_cpadd, 0}, | |
3d3c5039 | 433 | |
670a50eb | 434 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
3d3c5039 | 435 | chips. */ |
becfe05e | 436 | {"asciiz", s_stringer, 1}, |
670a50eb ILT |
437 | {"bss", s_change_sec, 'b'}, |
438 | {"err", s_err, 0}, | |
439 | {"half", s_cons, 1}, | |
52aa70b5 | 440 | {"dword", s_cons, 3}, |
3d3c5039 | 441 | |
670a50eb | 442 | /* These pseudo-ops are defined in read.c, but must be overridden |
3d3c5039 | 443 | here for one reason or another. */ |
670a50eb | 444 | {"align", s_align, 0}, |
becfe05e ILT |
445 | {"ascii", s_stringer, 0}, |
446 | {"asciz", s_stringer, 1}, | |
670a50eb ILT |
447 | {"byte", s_cons, 0}, |
448 | {"data", s_change_sec, 'd'}, | |
becfe05e | 449 | {"double", s_float_cons, 'd'}, |
670a50eb | 450 | {"extern", s_extern, 0}, |
becfe05e | 451 | {"float", s_float_cons, 'f'}, |
c1444ec4 ILT |
452 | {"globl", s_mips_globl, 0}, |
453 | {"global", s_mips_globl, 0}, | |
eb8fd0e9 ILT |
454 | {"hword", s_cons, 1}, |
455 | {"int", s_cons, 2}, | |
456 | {"long", s_cons, 2}, | |
457 | {"octa", s_cons, 4}, | |
458 | {"quad", s_cons, 3}, | |
459 | {"short", s_cons, 1}, | |
460 | {"single", s_float_cons, 'f'}, | |
becfe05e | 461 | {"space", s_mips_space, 0}, |
670a50eb ILT |
462 | {"text", s_change_sec, 't'}, |
463 | {"word", s_cons, 2}, | |
3d3c5039 | 464 | |
0dd2d296 | 465 | #ifndef ECOFF_DEBUGGING |
670a50eb | 466 | /* These pseudo-ops should be defined by the object file format. |
0dd2d296 | 467 | However, a.out doesn't support them, so we have versions here. */ |
670a50eb | 468 | {"aent", s_ent, 1}, |
9226253a | 469 | {"bgnb", s_ignore, 0}, |
670a50eb | 470 | {"end", s_mipsend, 0}, |
9226253a | 471 | {"endb", s_ignore, 0}, |
670a50eb ILT |
472 | {"ent", s_ent, 0}, |
473 | {"file", s_file, 0}, | |
474 | {"fmask", s_ignore, 'F'}, | |
475 | {"frame", s_ignore, 0}, | |
476 | {"loc", s_ignore, 0}, | |
477 | {"mask", s_ignore, 'R'}, | |
478 | {"verstamp", s_ignore, 0}, | |
3d3c5039 ILT |
479 | #endif |
480 | ||
9da4c5d1 ILT |
481 | #ifdef OBJ_ELF |
482 | /* We need to tweak the ELF ".section" pseudo-op a bit. */ | |
483 | {"section", s_elf_section, 0}, | |
484 | #endif | |
485 | ||
670a50eb ILT |
486 | /* Sentinel. */ |
487 | {NULL} | |
3d3c5039 ILT |
488 | }; |
489 | \f | |
670a50eb ILT |
490 | const relax_typeS md_relax_table[] = |
491 | { | |
918692a5 | 492 | { 0 } |
3d3c5039 ILT |
493 | }; |
494 | ||
3d3c5039 ILT |
495 | static char *expr_end; |
496 | ||
497 | static expressionS imm_expr; | |
498 | static expressionS offset_expr; | |
499 | static bfd_reloc_code_real_type imm_reloc; | |
500 | static bfd_reloc_code_real_type offset_reloc; | |
501 | ||
abdad6bc ILT |
502 | /* FIXME: This should be handled in a different way. */ |
503 | extern int target_big_endian; | |
504 | ||
3d3c5039 ILT |
505 | /* |
506 | * This function is called once, at assembler startup time. It should | |
507 | * set up all the tables, etc. that the MD part of the assembler will need. | |
508 | */ | |
509 | void | |
670a50eb | 510 | md_begin () |
3d3c5039 | 511 | { |
0dd2d296 | 512 | boolean ok = false; |
604633ae | 513 | register const char *retval = NULL; |
670a50eb | 514 | register unsigned int i = 0; |
3d3c5039 | 515 | |
8358c818 ILT |
516 | if (mips_isa == -1) |
517 | { | |
8c63448a ILT |
518 | const char *cpu; |
519 | char *a = NULL; | |
520 | ||
521 | cpu = TARGET_CPU; | |
522 | if (strcmp (cpu + (sizeof TARGET_CPU) - 3, "el") == 0) | |
523 | { | |
524 | a = xmalloc (sizeof TARGET_CPU); | |
525 | strcpy (a, TARGET_CPU); | |
526 | a[(sizeof TARGET_CPU) - 3] = '\0'; | |
527 | cpu = a; | |
528 | } | |
529 | ||
530 | if (strcmp (cpu, "mips") == 0) | |
531 | { | |
532 | mips_isa = 1; | |
4bb0cc41 ILT |
533 | if (mips_cpu == -1) |
534 | mips_cpu = 3000; | |
8c63448a ILT |
535 | } |
536 | else if (strcmp (cpu, "r6000") == 0 | |
537 | || strcmp (cpu, "mips2") == 0) | |
538 | { | |
539 | mips_isa = 2; | |
4bb0cc41 ILT |
540 | if (mips_cpu == -1) |
541 | mips_cpu = 6000; | |
8c63448a ILT |
542 | } |
543 | else if (strcmp (cpu, "mips64") == 0 | |
544 | || strcmp (cpu, "r4000") == 0 | |
545 | || strcmp (cpu, "mips3") == 0) | |
546 | { | |
547 | mips_isa = 3; | |
4bb0cc41 ILT |
548 | if (mips_cpu == -1) |
549 | mips_cpu = 4000; | |
8c63448a ILT |
550 | } |
551 | else if (strcmp (cpu, "r4400") == 0) | |
552 | { | |
553 | mips_isa = 3; | |
4bb0cc41 ILT |
554 | if (mips_cpu == -1) |
555 | mips_cpu = 4400; | |
8c63448a ILT |
556 | } |
557 | else if (strcmp (cpu, "mips64orion") == 0 | |
558 | || strcmp (cpu, "r4600") == 0) | |
559 | { | |
560 | mips_isa = 3; | |
4bb0cc41 ILT |
561 | if (mips_cpu == -1) |
562 | mips_cpu = 4600; | |
8c63448a | 563 | } |
8358c818 | 564 | else |
8c63448a ILT |
565 | { |
566 | mips_isa = 1; | |
4bb0cc41 ILT |
567 | if (mips_cpu == -1) |
568 | mips_cpu = 3000; | |
8c63448a ILT |
569 | } |
570 | ||
571 | if (a != NULL) | |
572 | free (a); | |
8358c818 ILT |
573 | } |
574 | ||
8ea7f4e8 ILT |
575 | if (mips_isa < 2 && mips_trap) |
576 | as_bad ("trap exception not supported at ISA 1"); | |
577 | ||
97f99d11 ILT |
578 | switch (mips_isa) |
579 | { | |
580 | case 1: | |
581 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 3000); | |
582 | break; | |
583 | case 2: | |
584 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 6000); | |
585 | break; | |
586 | case 3: | |
587 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 4000); | |
588 | break; | |
589 | } | |
590 | if (! ok) | |
591 | as_warn ("Could not set architecture and machine"); | |
592 | ||
1051c97f ILT |
593 | file_mips_isa = mips_isa; |
594 | ||
13fe1379 ILT |
595 | op_hash = hash_new (); |
596 | ||
670a50eb ILT |
597 | for (i = 0; i < NUMOPCODES;) |
598 | { | |
599 | const char *name = mips_opcodes[i].name; | |
600 | ||
604633ae | 601 | retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]); |
abdad6bc | 602 | if (retval != NULL) |
670a50eb ILT |
603 | { |
604 | fprintf (stderr, "internal error: can't hash `%s': %s\n", | |
605 | mips_opcodes[i].name, retval); | |
606 | as_fatal ("Broken assembler. No assembly attempted."); | |
607 | } | |
608 | do | |
609 | { | |
8358c818 ILT |
610 | if (mips_opcodes[i].pinfo != INSN_MACRO |
611 | && ((mips_opcodes[i].match & mips_opcodes[i].mask) | |
612 | != mips_opcodes[i].match)) | |
670a50eb ILT |
613 | { |
614 | fprintf (stderr, "internal error: bad opcode: `%s' \"%s\"\n", | |
615 | mips_opcodes[i].name, mips_opcodes[i].args); | |
616 | as_fatal ("Broken assembler. No assembly attempted."); | |
3d3c5039 | 617 | } |
670a50eb ILT |
618 | ++i; |
619 | } | |
620 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
3d3c5039 ILT |
621 | } |
622 | ||
becfe05e ILT |
623 | mips_no_prev_insn (); |
624 | ||
1aa6938e ILT |
625 | mips_gprmask = 0; |
626 | mips_cprmask[0] = 0; | |
627 | mips_cprmask[1] = 0; | |
628 | mips_cprmask[2] = 0; | |
629 | mips_cprmask[3] = 0; | |
630 | ||
8358c818 ILT |
631 | /* set the default alignment for the text section (2**2) */ |
632 | record_alignment (text_section, 2); | |
633 | ||
abdad6bc ILT |
634 | /* FIXME: This should be handled in a different way. */ |
635 | target_big_endian = byte_order == BIG_ENDIAN; | |
636 | ||
88225433 | 637 | #ifdef GPOPT |
8358c818 ILT |
638 | bfd_set_gp_size (stdoutput, g_switch_value); |
639 | #endif | |
640 | ||
f2a663d3 | 641 | #ifdef OBJ_ELF |
0dd2d296 ILT |
642 | /* Sections must be aligned to 16 byte boundaries. */ |
643 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
644 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
645 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
646 | ||
647 | /* Create a .reginfo section for register masks and a .mdebug | |
648 | section for debugging information. */ | |
f2a663d3 ILT |
649 | { |
650 | segT seg; | |
651 | subsegT subseg; | |
0dd2d296 | 652 | segT sec; |
f2a663d3 ILT |
653 | |
654 | seg = now_seg; | |
655 | subseg = now_subseg; | |
0dd2d296 | 656 | sec = subseg_new (".reginfo", (subsegT) 0); |
f2a663d3 | 657 | |
04cb3372 ILT |
658 | /* The ABI says this section should be loaded so that the running |
659 | program can access it. */ | |
0dd2d296 ILT |
660 | (void) bfd_set_section_flags (stdoutput, sec, |
661 | (SEC_ALLOC | SEC_LOAD | |
662 | | SEC_READONLY | SEC_DATA)); | |
663 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
f2a663d3 ILT |
664 | |
665 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); | |
666 | ||
0dd2d296 ILT |
667 | #ifdef ECOFF_DEBUGGING |
668 | sec = subseg_new (".mdebug", (subsegT) 0); | |
669 | (void) bfd_set_section_flags (stdoutput, sec, | |
670 | SEC_HAS_CONTENTS | SEC_READONLY); | |
671 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
672 | #endif | |
673 | ||
f2a663d3 ILT |
674 | subseg_set (seg, subseg); |
675 | } | |
676 | #endif /* OBJ_ELF */ | |
677 | ||
0dd2d296 | 678 | #ifndef ECOFF_DEBUGGING |
670a50eb | 679 | md_obj_begin (); |
3d3c5039 ILT |
680 | #endif |
681 | } | |
682 | ||
683 | void | |
13fe1379 | 684 | md_mips_end () |
3d3c5039 | 685 | { |
0dd2d296 | 686 | #ifndef ECOFF_DEBUGGING |
3d3c5039 ILT |
687 | md_obj_end (); |
688 | #endif | |
689 | } | |
690 | ||
691 | void | |
670a50eb ILT |
692 | md_assemble (str) |
693 | char *str; | |
3d3c5039 | 694 | { |
670a50eb | 695 | struct mips_cl_insn insn; |
3d3c5039 | 696 | |
5ac34ac3 ILT |
697 | imm_expr.X_op = O_absent; |
698 | offset_expr.X_op = O_absent; | |
3d3c5039 | 699 | |
670a50eb ILT |
700 | mips_ip (str, &insn); |
701 | if (insn_error) | |
702 | { | |
703 | as_bad ("%s `%s'", insn_error, str); | |
704 | return; | |
705 | } | |
706 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
707 | { | |
708 | macro (&insn); | |
3d3c5039 | 709 | } |
670a50eb ILT |
710 | else |
711 | { | |
5ac34ac3 | 712 | if (imm_expr.X_op != O_absent) |
0dd2d296 | 713 | append_insn ((char *) NULL, &insn, &imm_expr, imm_reloc); |
5ac34ac3 | 714 | else if (offset_expr.X_op != O_absent) |
0dd2d296 | 715 | append_insn ((char *) NULL, &insn, &offset_expr, offset_reloc); |
670a50eb | 716 | else |
0dd2d296 | 717 | append_insn ((char *) NULL, &insn, NULL, BFD_RELOC_UNUSED); |
3d3c5039 ILT |
718 | } |
719 | } | |
720 | ||
becfe05e ILT |
721 | /* See whether instruction IP reads register REG. If FPR is non-zero, |
722 | REG is a floating point register. */ | |
723 | ||
724 | static int | |
725 | insn_uses_reg (ip, reg, fpr) | |
726 | struct mips_cl_insn *ip; | |
604633ae | 727 | unsigned int reg; |
becfe05e ILT |
728 | int fpr; |
729 | { | |
730 | /* Don't report on general register 0, since it never changes. */ | |
731 | if (! fpr && reg == 0) | |
732 | return 0; | |
733 | ||
734 | if (fpr) | |
735 | { | |
736 | /* If we are called with either $f0 or $f1, we must check $f0. | |
737 | This is not optimal, because it will introduce an unnecessary | |
738 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
739 | need to distinguish reading both $f0 and $f1 or just one of | |
740 | them. Note that we don't have to check the other way, | |
741 | because there is no instruction that sets both $f0 and $f1 | |
742 | and requires a delay. */ | |
743 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
604633ae ILT |
744 | && (((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) |
745 | == (reg &~ (unsigned) 1))) | |
becfe05e ILT |
746 | return 1; |
747 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
604633ae ILT |
748 | && (((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) |
749 | == (reg &~ (unsigned) 1))) | |
becfe05e ILT |
750 | return 1; |
751 | } | |
752 | else | |
753 | { | |
754 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
755 | && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg) | |
756 | return 1; | |
757 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
758 | && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg) | |
759 | return 1; | |
760 | } | |
761 | ||
762 | return 0; | |
763 | } | |
764 | ||
0dd2d296 ILT |
765 | /* Output an instruction. PLACE is where to put the instruction; if |
766 | it is NULL, this uses frag_more to get room. IP is the instruction | |
767 | information. ADDRESS_EXPR is an operand of the instruction to be | |
768 | used with RELOC_TYPE. */ | |
3d3c5039 | 769 | |
3d3c5039 | 770 | static void |
0dd2d296 ILT |
771 | append_insn (place, ip, address_expr, reloc_type) |
772 | char *place; | |
670a50eb ILT |
773 | struct mips_cl_insn *ip; |
774 | expressionS *address_expr; | |
775 | bfd_reloc_code_real_type reloc_type; | |
3d3c5039 | 776 | { |
1aa6938e | 777 | register unsigned long prev_pinfo, pinfo; |
670a50eb | 778 | char *f; |
becfe05e ILT |
779 | fixS *fixp; |
780 | int nops = 0; | |
3d3c5039 | 781 | |
1aa6938e ILT |
782 | prev_pinfo = prev_insn.insn_mo->pinfo; |
783 | pinfo = ip->insn_mo->pinfo; | |
784 | ||
0dd2d296 | 785 | if (place == NULL && ! mips_noreorder) |
becfe05e ILT |
786 | { |
787 | /* If the previous insn required any delay slots, see if we need | |
8358c818 | 788 | to insert a NOP or two. There are eight kinds of possible |
becfe05e | 789 | hazards, of which an instruction can have at most one type. |
8358c818 ILT |
790 | (1) a load from memory delay |
791 | (2) a load from a coprocessor delay | |
792 | (3) an unconditional branch delay | |
793 | (4) a conditional branch delay | |
794 | (5) a move to coprocessor register delay | |
795 | (6) a load coprocessor register from memory delay | |
796 | (7) a coprocessor condition code delay | |
797 | (8) a HI/LO special register delay | |
becfe05e ILT |
798 | |
799 | There are a lot of optimizations we could do that we don't. | |
800 | In particular, we do not, in general, reorder instructions. | |
801 | If you use gcc with optimization, it will reorder | |
802 | instructions and generally do much more optimization then we | |
803 | do here; repeating all that work in the assembler would only | |
804 | benefit hand written assembly code, and does not seem worth | |
805 | it. */ | |
806 | ||
807 | /* This is how a NOP is emitted. */ | |
808 | #define emit_nop() md_number_to_chars (frag_more (4), 0, 4) | |
809 | ||
810 | /* The previous insn might require a delay slot, depending upon | |
811 | the contents of the current insn. */ | |
1aa6938e | 812 | if ((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
8358c818 | 813 | || (mips_isa < 2 |
1aa6938e | 814 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))) |
8358c818 ILT |
815 | { |
816 | /* A load from a coprocessor or from memory. All load | |
817 | delays delay the use of general register rt for one | |
818 | instruction on the r3000. The r6000 and r4000 use | |
819 | interlocks. */ | |
1aa6938e | 820 | know (prev_pinfo & INSN_WRITE_GPR_T); |
0aa07269 ILT |
821 | if (mips_optimize == 0 |
822 | || insn_uses_reg (ip, | |
823 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
824 | & OP_MASK_RT), | |
825 | 0)) | |
becfe05e ILT |
826 | ++nops; |
827 | } | |
1aa6938e | 828 | else if ((prev_pinfo & INSN_COPROC_MOVE_DELAY) |
8358c818 | 829 | || (mips_isa < 2 |
1aa6938e | 830 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY))) |
becfe05e ILT |
831 | { |
832 | /* A generic coprocessor delay. The previous instruction | |
833 | modified a coprocessor general or control register. If | |
834 | it modified a control register, we need to avoid any | |
835 | coprocessor instruction (this is probably not always | |
836 | required, but it sometimes is). If it modified a general | |
837 | register, we avoid using that register. | |
838 | ||
8358c818 ILT |
839 | On the r6000 and r4000 loading a coprocessor register |
840 | from memory is interlocked, and does not require a delay. | |
841 | ||
becfe05e ILT |
842 | This case is not handled very well. There is no special |
843 | knowledge of CP0 handling, and the coprocessors other | |
844 | than the floating point unit are not distinguished at | |
845 | all. */ | |
1aa6938e | 846 | if (prev_pinfo & INSN_WRITE_FPR_T) |
becfe05e | 847 | { |
0aa07269 ILT |
848 | if (mips_optimize == 0 |
849 | || insn_uses_reg (ip, | |
8358c818 ILT |
850 | ((prev_insn.insn_opcode >> OP_SH_FT) |
851 | & OP_MASK_FT), | |
0aa07269 | 852 | 1)) |
becfe05e ILT |
853 | ++nops; |
854 | } | |
1aa6938e | 855 | else if (prev_pinfo & INSN_WRITE_FPR_S) |
becfe05e | 856 | { |
0aa07269 ILT |
857 | if (mips_optimize == 0 |
858 | || insn_uses_reg (ip, | |
8358c818 ILT |
859 | ((prev_insn.insn_opcode >> OP_SH_FS) |
860 | & OP_MASK_FS), | |
0aa07269 | 861 | 1)) |
becfe05e ILT |
862 | ++nops; |
863 | } | |
864 | else | |
865 | { | |
866 | /* We don't know exactly what the previous instruction | |
867 | does. If the current instruction uses a coprocessor | |
868 | register, we must insert a NOP. If previous | |
869 | instruction may set the condition codes, and the | |
870 | current instruction uses them, we must insert two | |
871 | NOPS. */ | |
0aa07269 | 872 | if (mips_optimize == 0 |
1aa6938e ILT |
873 | || ((prev_pinfo & INSN_WRITE_COND_CODE) |
874 | && (pinfo & INSN_READ_COND_CODE))) | |
becfe05e | 875 | nops += 2; |
1aa6938e | 876 | else if (pinfo & INSN_COP) |
becfe05e ILT |
877 | ++nops; |
878 | } | |
879 | } | |
1aa6938e | 880 | else if (prev_pinfo & INSN_WRITE_COND_CODE) |
becfe05e ILT |
881 | { |
882 | /* The previous instruction sets the coprocessor condition | |
883 | codes, but does not require a general coprocessor delay | |
884 | (this means it is a floating point comparison | |
885 | instruction). If this instruction uses the condition | |
886 | codes, we need to insert a single NOP. */ | |
0aa07269 | 887 | if (mips_optimize == 0 |
1aa6938e | 888 | || (pinfo & INSN_READ_COND_CODE)) |
becfe05e ILT |
889 | ++nops; |
890 | } | |
1aa6938e | 891 | else if (prev_pinfo & INSN_READ_LO) |
becfe05e ILT |
892 | { |
893 | /* The previous instruction reads the LO register; if the | |
894 | current instruction writes to the LO register, we must | |
895 | insert two NOPS. */ | |
0aa07269 | 896 | if (mips_optimize == 0 |
1aa6938e | 897 | || (pinfo & INSN_WRITE_LO)) |
becfe05e ILT |
898 | nops += 2; |
899 | } | |
900 | else if (prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
901 | { | |
902 | /* The previous instruction reads the HI register; if the | |
903 | current instruction writes to the HI register, we must | |
904 | insert a NOP. */ | |
0aa07269 | 905 | if (mips_optimize == 0 |
1aa6938e | 906 | || (pinfo & INSN_WRITE_HI)) |
becfe05e ILT |
907 | nops += 2; |
908 | } | |
909 | ||
910 | /* There are two cases which require two intervening | |
911 | instructions: 1) setting the condition codes using a move to | |
912 | coprocessor instruction which requires a general coprocessor | |
913 | delay and then reading the condition codes 2) reading the HI | |
914 | or LO register and then writing to it. If we are not already | |
915 | emitting a NOP instruction, we must check for these cases | |
916 | compared to the instruction previous to the previous | |
917 | instruction. */ | |
918 | if (nops == 0 | |
8358c818 | 919 | && (((prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) |
becfe05e | 920 | && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) |
1aa6938e | 921 | && (pinfo & INSN_READ_COND_CODE)) |
becfe05e | 922 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO) |
1aa6938e | 923 | && (pinfo & INSN_WRITE_LO)) |
becfe05e | 924 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
1aa6938e | 925 | && (pinfo & INSN_WRITE_HI)))) |
becfe05e ILT |
926 | ++nops; |
927 | ||
0dd2d296 ILT |
928 | /* If we are being given a nop instruction, don't bother with |
929 | one of the nops we would otherwise output. This will only | |
930 | happen when a nop instruction is used with mips_optimize set | |
931 | to 0. */ | |
932 | if (nops > 0 && ip->insn_opcode == 0) | |
933 | --nops; | |
934 | ||
becfe05e ILT |
935 | /* Now emit the right number of NOP instructions. */ |
936 | if (nops > 0) | |
937 | { | |
8c63448a ILT |
938 | int i; |
939 | ||
940 | for (i = 0; i < nops; i++) | |
becfe05e | 941 | emit_nop (); |
af255ca0 ILT |
942 | if (listing) |
943 | listing_prev_line (); | |
becfe05e ILT |
944 | if (insn_label != NULL) |
945 | { | |
946 | assert (S_GET_SEGMENT (insn_label) == now_seg); | |
947 | insn_label->sy_frag = frag_now; | |
604633ae | 948 | S_SET_VALUE (insn_label, (valueT) frag_now_fix ()); |
becfe05e ILT |
949 | } |
950 | } | |
951 | } | |
952 | ||
0dd2d296 ILT |
953 | if (place == NULL) |
954 | f = frag_more (4); | |
955 | else | |
956 | f = place; | |
becfe05e | 957 | fixp = NULL; |
670a50eb ILT |
958 | if (address_expr != NULL) |
959 | { | |
5ac34ac3 | 960 | if (address_expr->X_op == O_constant) |
670a50eb ILT |
961 | { |
962 | switch (reloc_type) | |
963 | { | |
3d3c5039 | 964 | case BFD_RELOC_32: |
670a50eb ILT |
965 | ip->insn_opcode |= address_expr->X_add_number; |
966 | break; | |
3d3c5039 ILT |
967 | |
968 | case BFD_RELOC_LO16: | |
670a50eb ILT |
969 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
970 | break; | |
3d3c5039 ILT |
971 | |
972 | case BFD_RELOC_MIPS_JMP: | |
973 | case BFD_RELOC_16_PCREL_S2: | |
670a50eb | 974 | goto need_reloc; |
3d3c5039 ILT |
975 | |
976 | default: | |
670a50eb | 977 | internalError (); |
3d3c5039 | 978 | } |
670a50eb ILT |
979 | } |
980 | else | |
981 | { | |
982 | assert (reloc_type != BFD_RELOC_UNUSED); | |
3d3c5039 | 983 | need_reloc: |
0dd2d296 ILT |
984 | /* Don't generate a reloc if we are writing into a variant |
985 | frag. */ | |
986 | if (place == NULL) | |
987 | fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 4, | |
988 | address_expr, | |
989 | reloc_type == BFD_RELOC_16_PCREL_S2, | |
990 | reloc_type); | |
3d3c5039 ILT |
991 | } |
992 | } | |
becfe05e | 993 | |
670a50eb ILT |
994 | md_number_to_chars (f, ip->insn_opcode, 4); |
995 | ||
1aa6938e ILT |
996 | /* Update the register mask information. */ |
997 | if (pinfo & INSN_WRITE_GPR_D) | |
998 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD); | |
999 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) | |
1000 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT); | |
1001 | if (pinfo & INSN_READ_GPR_S) | |
1002 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS); | |
1003 | if (pinfo & INSN_WRITE_GPR_31) | |
1004 | mips_gprmask |= 1 << 31; | |
1005 | if (pinfo & INSN_WRITE_FPR_D) | |
1006 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD); | |
1007 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) | |
1008 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS); | |
1009 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) | |
1010 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT); | |
1011 | if (pinfo & INSN_COP) | |
1012 | { | |
1013 | /* We don't keep enough information to sort these cases out. */ | |
1014 | } | |
1015 | /* Never set the bit for $0, which is always zero. */ | |
1016 | mips_gprmask &=~ 1 << 0; | |
1017 | ||
0dd2d296 | 1018 | if (place == NULL && ! mips_noreorder) |
670a50eb | 1019 | { |
becfe05e ILT |
1020 | /* Filling the branch delay slot is more complex. We try to |
1021 | switch the branch with the previous instruction, which we can | |
1022 | do if the previous instruction does not set up a condition | |
1023 | that the branch tests and if the branch is not itself the | |
1024 | target of any branch. */ | |
1aa6938e ILT |
1025 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) |
1026 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
becfe05e | 1027 | { |
0aa07269 | 1028 | if (mips_optimize < 2 |
19ed8960 ILT |
1029 | /* If we have seen .set volatile or .set nomove, don't |
1030 | optimize. */ | |
1031 | || mips_nomove != 0 | |
4e95866e ILT |
1032 | /* If we had to emit any NOP instructions, then we |
1033 | already know we can not swap. */ | |
1034 | || nops != 0 | |
becfe05e ILT |
1035 | /* If we don't even know the previous insn, we can not |
1036 | swap. */ | |
1037 | || ! prev_insn_valid | |
1038 | /* If the previous insn is already in a branch delay | |
1039 | slot, then we can not swap. */ | |
1040 | || prev_insn_is_delay_slot | |
4e95866e ILT |
1041 | /* If the previous previous insn was in a .set |
1042 | noreorder, we can't swap. Actually, the MIPS | |
1043 | assembler will swap in this situation. However, gcc | |
1044 | configured -with-gnu-as will generate code like | |
1045 | .set noreorder | |
1046 | lw $4,XXX | |
1047 | .set reorder | |
1048 | INSN | |
1049 | bne $4,$0,foo | |
1050 | in which we can not swap the bne and INSN. If gcc is | |
1051 | not configured -with-gnu-as, it does not output the | |
1052 | .set pseudo-ops. We don't have to check | |
1053 | prev_insn_unreordered, because prev_insn_valid will | |
1054 | be 0 in that case. We don't want to use | |
1055 | prev_prev_insn_valid, because we do want to be able | |
1056 | to swap at the start of a function. */ | |
1057 | || prev_prev_insn_unreordered | |
becfe05e ILT |
1058 | /* If the branch is itself the target of a branch, we |
1059 | can not swap. We cheat on this; all we check for is | |
1060 | whether there is a label on this instruction. If | |
1061 | there are any branches to anything other than a | |
1062 | label, users must use .set noreorder. */ | |
1063 | || insn_label != NULL | |
777ad64d ILT |
1064 | /* If the previous instruction is in a variant frag, we |
1065 | can not do the swap. */ | |
1066 | || prev_insn_frag->fr_type == rs_machine_dependent | |
becfe05e ILT |
1067 | /* If the branch reads the condition codes, we don't |
1068 | even try to swap, because in the sequence | |
1069 | ctc1 $X,$31 | |
1070 | INSN | |
1071 | INSN | |
1072 | bc1t LABEL | |
1073 | we can not swap, and I don't feel like handling that | |
1074 | case. */ | |
1aa6938e | 1075 | || (pinfo & INSN_READ_COND_CODE) |
becfe05e ILT |
1076 | /* We can not swap with an instruction that requires a |
1077 | delay slot, becase the target of the branch might | |
1078 | interfere with that instruction. */ | |
1aa6938e | 1079 | || (prev_pinfo |
8358c818 ILT |
1080 | & (INSN_LOAD_COPROC_DELAY |
1081 | | INSN_COPROC_MOVE_DELAY | |
becfe05e ILT |
1082 | | INSN_WRITE_COND_CODE |
1083 | | INSN_READ_LO | |
1084 | | INSN_READ_HI)) | |
8358c818 | 1085 | || (mips_isa < 2 |
1aa6938e | 1086 | && (prev_pinfo |
8358c818 ILT |
1087 | & (INSN_LOAD_MEMORY_DELAY |
1088 | | INSN_COPROC_MEMORY_DELAY))) | |
becfe05e | 1089 | /* We can not swap with a branch instruction. */ |
1aa6938e | 1090 | || (prev_pinfo |
6e8dda9c ILT |
1091 | & (INSN_UNCOND_BRANCH_DELAY |
1092 | | INSN_COND_BRANCH_DELAY | |
1093 | | INSN_COND_BRANCH_LIKELY)) | |
abdad6bc ILT |
1094 | /* We do not swap with a trap instruction, since it |
1095 | complicates trap handlers to have the trap | |
1096 | instruction be in a delay slot. */ | |
1aa6938e | 1097 | || (prev_pinfo & INSN_TRAP) |
becfe05e ILT |
1098 | /* If the branch reads a register that the previous |
1099 | instruction sets, we can not swap. */ | |
1aa6938e | 1100 | || ((prev_pinfo & INSN_WRITE_GPR_T) |
becfe05e ILT |
1101 | && insn_uses_reg (ip, |
1102 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1103 | & OP_MASK_RT), | |
1104 | 0)) | |
1aa6938e | 1105 | || ((prev_pinfo & INSN_WRITE_GPR_D) |
becfe05e ILT |
1106 | && insn_uses_reg (ip, |
1107 | ((prev_insn.insn_opcode >> OP_SH_RD) | |
1108 | & OP_MASK_RD), | |
1109 | 0)) | |
1849d646 ILT |
1110 | /* If the branch writes a register that the previous |
1111 | instruction sets, we can not swap (we know that | |
1112 | branches write only to RD or to $31). */ | |
1aa6938e ILT |
1113 | || ((prev_pinfo & INSN_WRITE_GPR_T) |
1114 | && (((pinfo & INSN_WRITE_GPR_D) | |
1849d646 ILT |
1115 | && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT) |
1116 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
1aa6938e | 1117 | || ((pinfo & INSN_WRITE_GPR_31) |
1849d646 ILT |
1118 | && (((prev_insn.insn_opcode >> OP_SH_RT) |
1119 | & OP_MASK_RT) | |
1120 | == 31)))) | |
1aa6938e ILT |
1121 | || ((prev_pinfo & INSN_WRITE_GPR_D) |
1122 | && (((pinfo & INSN_WRITE_GPR_D) | |
1849d646 ILT |
1123 | && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD) |
1124 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
1aa6938e | 1125 | || ((pinfo & INSN_WRITE_GPR_31) |
1849d646 ILT |
1126 | && (((prev_insn.insn_opcode >> OP_SH_RD) |
1127 | & OP_MASK_RD) | |
1128 | == 31)))) | |
becfe05e ILT |
1129 | /* If the branch writes a register that the previous |
1130 | instruction reads, we can not swap (we know that | |
1131 | branches only write to RD or to $31). */ | |
1aa6938e | 1132 | || ((pinfo & INSN_WRITE_GPR_D) |
becfe05e ILT |
1133 | && insn_uses_reg (&prev_insn, |
1134 | ((ip->insn_opcode >> OP_SH_RD) | |
1135 | & OP_MASK_RD), | |
1136 | 0)) | |
1aa6938e | 1137 | || ((pinfo & INSN_WRITE_GPR_31) |
becfe05e | 1138 | && insn_uses_reg (&prev_insn, 31, 0)) |
5b63f465 ILT |
1139 | /* If we are generating embedded PIC code, the branch |
1140 | might be expanded into a sequence which uses $at, so | |
1141 | we can't swap with an instruction which reads it. */ | |
1142 | || (mips_pic == EMBEDDED_PIC | |
1143 | && insn_uses_reg (&prev_insn, AT, 0)) | |
becfe05e ILT |
1144 | /* If the previous previous instruction has a load |
1145 | delay, and sets a register that the branch reads, we | |
1146 | can not swap. */ | |
8358c818 ILT |
1147 | || (((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) |
1148 | || (mips_isa < 2 | |
1149 | && (prev_prev_insn.insn_mo->pinfo | |
1150 | & INSN_LOAD_MEMORY_DELAY))) | |
becfe05e ILT |
1151 | && insn_uses_reg (ip, |
1152 | ((prev_prev_insn.insn_opcode >> OP_SH_RT) | |
1153 | & OP_MASK_RT), | |
1154 | 0))) | |
1155 | { | |
1156 | /* We could do even better for unconditional branches to | |
1157 | portions of this object file; we could pick up the | |
1158 | instruction at the destination, put it in the delay | |
1159 | slot, and bump the destination address. */ | |
1160 | emit_nop (); | |
1161 | /* Update the previous insn information. */ | |
1162 | prev_prev_insn = *ip; | |
1163 | prev_insn.insn_mo = &dummy_opcode; | |
1164 | } | |
1165 | else | |
1166 | { | |
1167 | char *prev_f; | |
1168 | char temp[4]; | |
1169 | ||
1170 | /* It looks like we can actually do the swap. */ | |
1171 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
1172 | memcpy (temp, prev_f, 4); | |
1173 | memcpy (prev_f, f, 4); | |
1174 | memcpy (f, temp, 4); | |
1175 | if (prev_insn_fixp) | |
1176 | { | |
1177 | prev_insn_fixp->fx_frag = frag_now; | |
1178 | prev_insn_fixp->fx_where = f - frag_now->fr_literal; | |
1179 | } | |
1180 | if (fixp) | |
1181 | { | |
1182 | fixp->fx_frag = prev_insn_frag; | |
1183 | fixp->fx_where = prev_insn_where; | |
1184 | } | |
1185 | /* Update the previous insn information; leave prev_insn | |
1186 | unchanged. */ | |
1187 | prev_prev_insn = *ip; | |
1188 | } | |
1189 | prev_insn_is_delay_slot = 1; | |
1190 | ||
1191 | /* If that was an unconditional branch, forget the previous | |
1192 | insn information. */ | |
1aa6938e | 1193 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) |
becfe05e ILT |
1194 | { |
1195 | prev_prev_insn.insn_mo = &dummy_opcode; | |
1196 | prev_insn.insn_mo = &dummy_opcode; | |
1197 | } | |
1198 | } | |
1aa6938e | 1199 | else if (pinfo & INSN_COND_BRANCH_LIKELY) |
8358c818 ILT |
1200 | { |
1201 | /* We don't yet optimize a branch likely. What we should do | |
1202 | is look at the target, copy the instruction found there | |
1203 | into the delay slot, and increment the branch to jump to | |
1204 | the next instruction. */ | |
1205 | emit_nop (); | |
1206 | /* Update the previous insn information. */ | |
1207 | prev_prev_insn = *ip; | |
1208 | prev_insn.insn_mo = &dummy_opcode; | |
1209 | } | |
becfe05e | 1210 | else |
670a50eb | 1211 | { |
becfe05e ILT |
1212 | /* Update the previous insn information. */ |
1213 | if (nops > 0) | |
1214 | prev_prev_insn.insn_mo = &dummy_opcode; | |
1215 | else | |
1216 | prev_prev_insn = prev_insn; | |
1217 | prev_insn = *ip; | |
1218 | ||
1219 | /* Any time we see a branch, we always fill the delay slot | |
1220 | immediately; since this insn is not a branch, we know it | |
1221 | is not in a delay slot. */ | |
1222 | prev_insn_is_delay_slot = 0; | |
1223 | } | |
1224 | ||
4e95866e ILT |
1225 | prev_prev_insn_unreordered = prev_insn_unreordered; |
1226 | prev_insn_unreordered = 0; | |
becfe05e ILT |
1227 | prev_insn_frag = frag_now; |
1228 | prev_insn_where = f - frag_now->fr_literal; | |
1229 | prev_insn_fixp = fixp; | |
1230 | prev_insn_valid = 1; | |
1231 | } | |
3d3c5039 | 1232 | |
becfe05e ILT |
1233 | /* We just output an insn, so the next one doesn't have a label. */ |
1234 | insn_label = NULL; | |
1235 | } | |
1236 | ||
1237 | /* This function forgets that there was any previous instruction or | |
1238 | label. */ | |
1239 | ||
1240 | static void | |
1241 | mips_no_prev_insn () | |
1242 | { | |
1243 | prev_insn.insn_mo = &dummy_opcode; | |
1244 | prev_prev_insn.insn_mo = &dummy_opcode; | |
1245 | prev_insn_valid = 0; | |
1246 | prev_insn_is_delay_slot = 0; | |
4e95866e ILT |
1247 | prev_insn_unreordered = 0; |
1248 | prev_prev_insn_unreordered = 0; | |
becfe05e ILT |
1249 | insn_label = NULL; |
1250 | } | |
1251 | ||
1252 | /* This function must be called whenever we turn on noreorder or emit | |
1253 | something other than instructions. It inserts any NOPS which might | |
1254 | be needed by the previous instruction, and clears the information | |
1255 | kept for the previous instructions. */ | |
1256 | ||
1257 | static void | |
1258 | mips_emit_delays () | |
1259 | { | |
1260 | if (! mips_noreorder) | |
1261 | { | |
1262 | int nop; | |
1263 | ||
1264 | nop = 0; | |
8358c818 ILT |
1265 | if ((prev_insn.insn_mo->pinfo |
1266 | & (INSN_LOAD_COPROC_DELAY | |
1267 | | INSN_COPROC_MOVE_DELAY | |
1268 | | INSN_WRITE_COND_CODE | |
1269 | | INSN_READ_LO | |
1270 | | INSN_READ_HI)) | |
1271 | || (mips_isa < 2 | |
1272 | && (prev_insn.insn_mo->pinfo | |
1273 | & (INSN_LOAD_MEMORY_DELAY | |
1274 | | INSN_COPROC_MEMORY_DELAY)))) | |
becfe05e ILT |
1275 | { |
1276 | nop = 1; | |
1277 | if ((prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) | |
1278 | || (prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1279 | || (prev_insn.insn_mo->pinfo & INSN_READ_LO)) | |
1280 | emit_nop (); | |
1281 | } | |
1282 | else if ((prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) | |
1283 | || (prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1284 | || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)) | |
1285 | nop = 1; | |
1286 | if (nop) | |
670a50eb | 1287 | { |
becfe05e ILT |
1288 | emit_nop (); |
1289 | if (insn_label != NULL) | |
1290 | { | |
1291 | assert (S_GET_SEGMENT (insn_label) == now_seg); | |
1292 | insn_label->sy_frag = frag_now; | |
604633ae | 1293 | S_SET_VALUE (insn_label, (valueT) frag_now_fix ()); |
becfe05e | 1294 | } |
3d3c5039 ILT |
1295 | } |
1296 | } | |
0221ddf7 ILT |
1297 | |
1298 | mips_no_prev_insn (); | |
3d3c5039 ILT |
1299 | } |
1300 | ||
670a50eb ILT |
1301 | /* Build an instruction created by a macro expansion. This is passed |
1302 | a pointer to the count of instructions created so far, an | |
1303 | expression, the name of the instruction to build, an operand format | |
1304 | string, and corresponding arguments. */ | |
1305 | ||
3d3c5039 ILT |
1306 | #ifndef NO_STDARG |
1307 | static void | |
0dd2d296 ILT |
1308 | macro_build (char *place, |
1309 | int *counter, | |
670a50eb | 1310 | expressionS * ep, |
3d3c5039 ILT |
1311 | const char *name, |
1312 | const char *fmt, | |
1313 | ...) | |
1314 | #else /* ! defined (NO_STDARG) */ | |
1315 | static void | |
0dd2d296 ILT |
1316 | macro_build (place, counter, ep, name, fmt, va_alist) |
1317 | char *place; | |
3d3c5039 ILT |
1318 | int *counter; |
1319 | expressionS *ep; | |
1320 | const char *name; | |
1321 | const char *fmt; | |
1322 | va_dcl | |
1323 | #endif /* ! defined (NO_STDARG) */ | |
1324 | { | |
670a50eb ILT |
1325 | struct mips_cl_insn insn; |
1326 | bfd_reloc_code_real_type r; | |
1327 | va_list args; | |
3d3c5039 ILT |
1328 | |
1329 | #ifndef NO_STDARG | |
670a50eb | 1330 | va_start (args, fmt); |
3d3c5039 | 1331 | #else |
670a50eb | 1332 | va_start (args); |
3d3c5039 ILT |
1333 | #endif |
1334 | ||
670a50eb ILT |
1335 | /* |
1336 | * If the macro is about to expand into a second instruction, | |
1337 | * print a warning if needed. We need to pass ip as a parameter | |
1338 | * to generate a better warning message here... | |
1339 | */ | |
0dd2d296 | 1340 | if (mips_warn_about_macros && place == NULL && *counter == 1) |
670a50eb ILT |
1341 | as_warn ("Macro instruction expanded into multiple instructions"); |
1342 | ||
0dd2d296 ILT |
1343 | if (place == NULL) |
1344 | *counter += 1; /* bump instruction counter */ | |
670a50eb ILT |
1345 | |
1346 | r = BFD_RELOC_UNUSED; | |
1347 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
1348 | assert (insn.insn_mo); | |
1349 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
1350 | ||
9226253a ILT |
1351 | while (strcmp (fmt, insn.insn_mo->args) != 0 |
1352 | || insn.insn_mo->pinfo == INSN_MACRO) | |
670a50eb ILT |
1353 | { |
1354 | ++insn.insn_mo; | |
1355 | assert (insn.insn_mo->name); | |
1356 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
3d3c5039 | 1357 | } |
670a50eb ILT |
1358 | insn.insn_opcode = insn.insn_mo->match; |
1359 | for (;;) | |
1360 | { | |
1361 | switch (*fmt++) | |
1362 | { | |
3d3c5039 | 1363 | case '\0': |
670a50eb | 1364 | break; |
3d3c5039 ILT |
1365 | |
1366 | case ',': | |
1367 | case '(': | |
1368 | case ')': | |
670a50eb | 1369 | continue; |
3d3c5039 ILT |
1370 | |
1371 | case 't': | |
1372 | case 'w': | |
918692a5 | 1373 | case 'E': |
670a50eb ILT |
1374 | insn.insn_opcode |= va_arg (args, int) << 16; |
1375 | continue; | |
3d3c5039 ILT |
1376 | |
1377 | case 'c': | |
1378 | case 'T': | |
1379 | case 'W': | |
670a50eb ILT |
1380 | insn.insn_opcode |= va_arg (args, int) << 16; |
1381 | continue; | |
3d3c5039 ILT |
1382 | |
1383 | case 'd': | |
918692a5 | 1384 | case 'G': |
670a50eb ILT |
1385 | insn.insn_opcode |= va_arg (args, int) << 11; |
1386 | continue; | |
3d3c5039 ILT |
1387 | |
1388 | case 'V': | |
1389 | case 'S': | |
670a50eb ILT |
1390 | insn.insn_opcode |= va_arg (args, int) << 11; |
1391 | continue; | |
3d3c5039 | 1392 | |
ff3a5c18 ILT |
1393 | case 'z': |
1394 | continue; | |
1395 | ||
3d3c5039 | 1396 | case '<': |
670a50eb ILT |
1397 | insn.insn_opcode |= va_arg (args, int) << 6; |
1398 | continue; | |
3d3c5039 ILT |
1399 | |
1400 | case 'D': | |
670a50eb ILT |
1401 | insn.insn_opcode |= va_arg (args, int) << 6; |
1402 | continue; | |
3d3c5039 | 1403 | |
918692a5 ILT |
1404 | case 'B': |
1405 | insn.insn_opcode |= va_arg (args, int) << 6; | |
1406 | continue; | |
1407 | ||
3d3c5039 ILT |
1408 | case 'b': |
1409 | case 's': | |
1410 | case 'r': | |
1411 | case 'v': | |
670a50eb ILT |
1412 | insn.insn_opcode |= va_arg (args, int) << 21; |
1413 | continue; | |
3d3c5039 ILT |
1414 | |
1415 | case 'i': | |
1416 | case 'j': | |
1417 | case 'o': | |
9226253a | 1418 | r = (bfd_reloc_code_real_type) va_arg (args, int); |
0dd2d296 ILT |
1419 | assert (r == BFD_RELOC_MIPS_GPREL |
1420 | || r == BFD_RELOC_MIPS_LITERAL | |
1421 | || r == BFD_RELOC_LO16 | |
1422 | || r == BFD_RELOC_MIPS_GOT16 | |
ecd4ca1c ILT |
1423 | || r == BFD_RELOC_MIPS_CALL16 |
1424 | || (ep->X_op == O_subtract | |
1425 | && now_seg == text_section | |
1426 | && S_GET_SEGMENT (ep->X_op_symbol) == text_section | |
1427 | && r == BFD_RELOC_PCREL_LO16)); | |
670a50eb | 1428 | continue; |
3d3c5039 | 1429 | |
6e8dda9c | 1430 | case 'u': |
ecd4ca1c ILT |
1431 | r = (bfd_reloc_code_real_type) va_arg (args, int); |
1432 | assert (ep != NULL | |
1433 | && (ep->X_op == O_constant | |
1434 | || (ep->X_op == O_symbol | |
1435 | && (r == BFD_RELOC_HI16_S | |
1436 | || r == BFD_RELOC_HI16)) | |
1437 | || (ep->X_op == O_subtract | |
1438 | && now_seg == text_section | |
1439 | && S_GET_SEGMENT (ep->X_op_symbol) == text_section | |
1440 | && r == BFD_RELOC_PCREL_HI16_S))); | |
1441 | if (ep->X_op == O_constant) | |
1442 | { | |
1443 | insn.insn_opcode |= (ep->X_add_number >> 16) & 0xffff; | |
1444 | ep = NULL; | |
1445 | r = BFD_RELOC_UNUSED; | |
1446 | } | |
6e8dda9c ILT |
1447 | continue; |
1448 | ||
3d3c5039 | 1449 | case 'p': |
670a50eb ILT |
1450 | assert (ep != NULL); |
1451 | /* | |
1452 | * This allows macro() to pass an immediate expression for | |
1453 | * creating short branches without creating a symbol. | |
1454 | * Note that the expression still might come from the assembly | |
1455 | * input, in which case the value is not checked for range nor | |
1456 | * is a relocation entry generated (yuck). | |
1457 | */ | |
5ac34ac3 | 1458 | if (ep->X_op == O_constant) |
670a50eb ILT |
1459 | { |
1460 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
1461 | ep = NULL; | |
1462 | } | |
1463 | else | |
1464 | r = BFD_RELOC_16_PCREL_S2; | |
1465 | continue; | |
3d3c5039 | 1466 | |
9226253a ILT |
1467 | case 'a': |
1468 | assert (ep != NULL); | |
1469 | r = BFD_RELOC_MIPS_JMP; | |
1470 | continue; | |
1471 | ||
3d3c5039 | 1472 | default: |
670a50eb | 1473 | internalError (); |
3d3c5039 | 1474 | } |
670a50eb | 1475 | break; |
3d3c5039 | 1476 | } |
670a50eb ILT |
1477 | va_end (args); |
1478 | assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
1479 | ||
0dd2d296 | 1480 | append_insn (place, &insn, ep, r); |
3d3c5039 ILT |
1481 | } |
1482 | ||
1483 | /* | |
1484 | * Generate a "lui" instruction. | |
1485 | */ | |
1486 | static void | |
0dd2d296 ILT |
1487 | macro_build_lui (place, counter, ep, regnum) |
1488 | char *place; | |
3d3c5039 ILT |
1489 | int *counter; |
1490 | expressionS *ep; | |
1491 | int regnum; | |
1492 | { | |
670a50eb ILT |
1493 | expressionS high_expr; |
1494 | struct mips_cl_insn insn; | |
1495 | bfd_reloc_code_real_type r; | |
1496 | CONST char *name = "lui"; | |
1497 | CONST char *fmt = "t,u"; | |
1498 | ||
0dd2d296 ILT |
1499 | if (place == NULL) |
1500 | high_expr = *ep; | |
1501 | else | |
1502 | { | |
1503 | high_expr.X_op = O_constant; | |
1504 | high_expr.X_add_number = 0; | |
1505 | } | |
670a50eb | 1506 | |
5ac34ac3 | 1507 | if (high_expr.X_op == O_constant) |
670a50eb ILT |
1508 | { |
1509 | /* we can compute the instruction now without a relocation entry */ | |
1510 | if (high_expr.X_add_number & 0x8000) | |
1511 | high_expr.X_add_number += 0x10000; | |
1512 | high_expr.X_add_number = | |
1513 | ((unsigned long) high_expr.X_add_number >> 16) & 0xffff; | |
1514 | r = BFD_RELOC_UNUSED; | |
1515 | } | |
1516 | else | |
0dd2d296 ILT |
1517 | { |
1518 | assert (ep->X_op == O_symbol); | |
1519 | /* _gp_disp is a special case, used from s_cpload. */ | |
d9aba805 | 1520 | assert (mips_pic == NO_PIC |
0dd2d296 ILT |
1521 | || strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0); |
1522 | r = BFD_RELOC_HI16_S; | |
1523 | } | |
670a50eb ILT |
1524 | |
1525 | /* | |
1526 | * If the macro is about to expand into a second instruction, | |
1527 | * print a warning if needed. We need to pass ip as a parameter | |
1528 | * to generate a better warning message here... | |
1529 | */ | |
0dd2d296 | 1530 | if (mips_warn_about_macros && place == NULL && *counter == 1) |
670a50eb ILT |
1531 | as_warn ("Macro instruction expanded into multiple instructions"); |
1532 | ||
0dd2d296 ILT |
1533 | if (place == NULL) |
1534 | *counter += 1; /* bump instruction counter */ | |
670a50eb ILT |
1535 | |
1536 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
1537 | assert (insn.insn_mo); | |
1538 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
1539 | assert (strcmp (fmt, insn.insn_mo->args) == 0); | |
1540 | ||
0dd2d296 | 1541 | insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT); |
670a50eb ILT |
1542 | if (r == BFD_RELOC_UNUSED) |
1543 | { | |
1544 | insn.insn_opcode |= high_expr.X_add_number; | |
0dd2d296 | 1545 | append_insn (place, &insn, NULL, r); |
670a50eb ILT |
1546 | } |
1547 | else | |
0dd2d296 | 1548 | append_insn (place, &insn, &high_expr, r); |
3d3c5039 ILT |
1549 | } |
1550 | ||
1551 | /* set_at() | |
1552 | * Generates code to set the $at register to true (one) | |
1553 | * if reg is less than the immediate expression. | |
1554 | */ | |
1555 | static void | |
6e8dda9c | 1556 | set_at (counter, reg, unsignedp) |
3d3c5039 ILT |
1557 | int *counter; |
1558 | int reg; | |
6e8dda9c | 1559 | int unsignedp; |
3d3c5039 | 1560 | { |
6e8dda9c | 1561 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
0dd2d296 | 1562 | macro_build ((char *) NULL, counter, &imm_expr, |
6e8dda9c | 1563 | unsignedp ? "sltiu" : "slti", |
9226253a | 1564 | "t,r,j", AT, reg, (int) BFD_RELOC_LO16); |
6e8dda9c | 1565 | else |
670a50eb | 1566 | { |
6e8dda9c | 1567 | load_register (counter, AT, &imm_expr); |
0dd2d296 | 1568 | macro_build ((char *) NULL, counter, NULL, |
6e8dda9c ILT |
1569 | unsignedp ? "sltu" : "slt", |
1570 | "d,v,t", AT, reg, AT); | |
670a50eb | 1571 | } |
3d3c5039 ILT |
1572 | } |
1573 | ||
6e8dda9c | 1574 | /* Warn if an expression is not a constant. */ |
3d3c5039 ILT |
1575 | |
1576 | static void | |
19ed8960 | 1577 | check_absolute_expr (ip, ex) |
3d3c5039 | 1578 | struct mips_cl_insn *ip; |
19ed8960 | 1579 | expressionS *ex; |
3d3c5039 | 1580 | { |
19ed8960 | 1581 | if (ex->X_op != O_constant) |
670a50eb | 1582 | as_warn ("Instruction %s requires absolute expression", ip->insn_mo->name); |
3d3c5039 ILT |
1583 | } |
1584 | ||
1585 | /* load_register() | |
1586 | * This routine generates the least number of instructions neccessary to load | |
1587 | * an absolute expression value into a register. | |
1588 | */ | |
1589 | static void | |
6e8dda9c | 1590 | load_register (counter, reg, ep) |
670a50eb | 1591 | int *counter; |
670a50eb ILT |
1592 | int reg; |
1593 | expressionS *ep; | |
3d3c5039 | 1594 | { |
6e8dda9c ILT |
1595 | assert (ep->X_op == O_constant); |
1596 | if (ep->X_add_number >= -0x8000 && ep->X_add_number < 0x8000) | |
7b777690 ILT |
1597 | { |
1598 | /* No need to ever use daddiu here, since we are adding in | |
1599 | register $zero. */ | |
1600 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, | |
1601 | (int) BFD_RELOC_LO16); | |
1602 | } | |
6e8dda9c | 1603 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) |
0dd2d296 ILT |
1604 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0, |
1605 | (int) BFD_RELOC_LO16); | |
6e8dda9c ILT |
1606 | else if ((ep->X_add_number &~ (offsetT) 0x7fffffff) == 0 |
1607 | || ((ep->X_add_number &~ (offsetT) 0x7fffffff) | |
1608 | == ~ (offsetT) 0x7fffffff)) | |
1609 | { | |
ecd4ca1c ILT |
1610 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, |
1611 | (int) BFD_RELOC_HI16); | |
6e8dda9c | 1612 | if ((ep->X_add_number & 0xffff) != 0) |
0dd2d296 | 1613 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg, |
9226253a | 1614 | (int) BFD_RELOC_LO16); |
6e8dda9c ILT |
1615 | } |
1616 | else if (mips_isa < 3) | |
670a50eb | 1617 | { |
6e8dda9c | 1618 | as_bad ("Number larger than 32 bits"); |
0dd2d296 | 1619 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, |
9226253a | 1620 | (int) BFD_RELOC_LO16); |
6e8dda9c ILT |
1621 | } |
1622 | else | |
1623 | { | |
1624 | int shift; | |
1625 | expressionS hi32, lo32; | |
1626 | ||
1627 | hi32 = *ep; | |
1628 | shift = 32; | |
1629 | hi32.X_add_number >>= shift; | |
1630 | hi32.X_add_number &= 0xffffffff; | |
1631 | if ((hi32.X_add_number & 0x80000000) != 0) | |
1632 | hi32.X_add_number |= ~ (offsetT) 0xffffffff; | |
1633 | load_register (counter, reg, &hi32); | |
1634 | lo32 = *ep; | |
1635 | lo32.X_add_number &= 0xffffffff; | |
1636 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
0dd2d296 ILT |
1637 | macro_build ((char *) NULL, counter, NULL, "dsll32", "d,w,<", reg, |
1638 | reg, 0); | |
6e8dda9c ILT |
1639 | else |
1640 | { | |
1641 | expressionS mid16; | |
670a50eb | 1642 | |
0dd2d296 ILT |
1643 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, |
1644 | reg, 16); | |
6e8dda9c ILT |
1645 | mid16 = lo32; |
1646 | mid16.X_add_number >>= 16; | |
0dd2d296 ILT |
1647 | macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg, |
1648 | reg, (int) BFD_RELOC_LO16); | |
1649 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, | |
1650 | reg, 16); | |
6e8dda9c ILT |
1651 | } |
1652 | if ((lo32.X_add_number & 0xffff) != 0) | |
0dd2d296 | 1653 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, reg, |
9226253a | 1654 | (int) BFD_RELOC_LO16); |
670a50eb | 1655 | } |
3d3c5039 ILT |
1656 | } |
1657 | ||
0dd2d296 ILT |
1658 | /* Load an address into a register. */ |
1659 | ||
1660 | static void | |
1661 | load_address (counter, reg, ep) | |
1662 | int *counter; | |
1663 | int reg; | |
1664 | expressionS *ep; | |
1665 | { | |
1666 | char *p; | |
1667 | ||
1668 | if (ep->X_op != O_constant | |
1669 | && ep->X_op != O_symbol) | |
1670 | { | |
1671 | as_bad ("expression too complex"); | |
1672 | ep->X_op = O_constant; | |
1673 | } | |
1674 | ||
1675 | if (ep->X_op == O_constant) | |
d9aba805 ILT |
1676 | { |
1677 | load_register (counter, reg, ep); | |
1678 | return; | |
1679 | } | |
1680 | ||
1681 | if (mips_pic == NO_PIC) | |
0dd2d296 ILT |
1682 | { |
1683 | /* If this is a reference to a GP relative symbol, we want | |
1684 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
1685 | Otherwise we want | |
04cb3372 | 1686 | lui $reg,<sym> (BFD_RELOC_HI16_S) |
0dd2d296 ILT |
1687 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) |
1688 | If we have an addend, we always use the latter form. */ | |
1689 | if (ep->X_add_number != 0) | |
1690 | p = NULL; | |
1691 | else | |
1692 | { | |
8ea7f4e8 | 1693 | frag_grow (20); |
0dd2d296 ILT |
1694 | macro_build ((char *) NULL, counter, ep, |
1695 | mips_isa < 3 ? "addiu" : "daddiu", | |
1696 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
1697 | p = frag_var (rs_machine_dependent, 8, 0, | |
1698 | RELAX_ENCODE (4, 8, -4, 0, 0, mips_warn_about_macros), | |
1699 | ep->X_add_symbol, (long) 0, (char *) NULL); | |
1700 | } | |
1701 | macro_build_lui (p, counter, ep, reg); | |
1702 | if (p != NULL) | |
1703 | p += 4; | |
1704 | macro_build (p, counter, ep, | |
1705 | mips_isa < 3 ? "addiu" : "daddiu", | |
1706 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
1707 | } | |
d9aba805 | 1708 | else if (mips_pic == SVR4_PIC) |
0dd2d296 ILT |
1709 | { |
1710 | expressionS ex; | |
1711 | ||
1712 | /* If this is a reference to an external symbol, we want | |
1713 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1714 | Otherwise we want | |
1715 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1716 | nop | |
1717 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d9aba805 | 1718 | If there is a constant, it must be added in after. */ |
0dd2d296 ILT |
1719 | ex.X_add_number = ep->X_add_number; |
1720 | ep->X_add_number = 0; | |
8ea7f4e8 | 1721 | frag_grow (20); |
0dd2d296 ILT |
1722 | macro_build ((char *) NULL, counter, ep, |
1723 | mips_isa < 3 ? "lw" : "ld", | |
1724 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
1725 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", ""); | |
1726 | p = frag_var (rs_machine_dependent, 4, 0, | |
1727 | RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros), | |
1728 | ep->X_add_symbol, (long) 0, (char *) NULL); | |
1729 | macro_build (p, counter, ep, | |
1730 | mips_isa < 3 ? "addiu" : "daddiu", | |
1731 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
1732 | if (ex.X_add_number != 0) | |
1733 | { | |
1734 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
1735 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
1736 | ex.X_op = O_constant; | |
1737 | macro_build (p, counter, &ex, | |
1738 | mips_isa < 3 ? "addiu" : "daddiu", | |
1739 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
1740 | } | |
d9aba805 ILT |
1741 | } |
1742 | else if (mips_pic == EMBEDDED_PIC) | |
1743 | { | |
1744 | /* We always do | |
1745 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
1746 | */ | |
1747 | macro_build ((char *) NULL, counter, ep, | |
1748 | mips_isa < 3 ? "addiu" : "daddiu", | |
1749 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
1750 | } | |
1751 | else | |
1752 | abort (); | |
0dd2d296 ILT |
1753 | } |
1754 | ||
3d3c5039 ILT |
1755 | /* |
1756 | * Build macros | |
1757 | * This routine implements the seemingly endless macro or synthesized | |
1758 | * instructions and addressing modes in the mips assembly language. Many | |
1759 | * of these macros are simple and are similar to each other. These could | |
1760 | * probably be handled by some kind of table or grammer aproach instead of | |
1761 | * this verbose method. Others are not simple macros but are more like | |
1762 | * optimizing code generation. | |
1763 | * One interesting optimization is when several store macros appear | |
1764 | * consecutivly that would load AT with the upper half of the same address. | |
1765 | * The ensuing load upper instructions are ommited. This implies some kind | |
1766 | * of global optimization. We currently only optimize within a single macro. | |
1767 | * For many of the load and store macros if the address is specified as a | |
1768 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
1769 | * first load register 'at' with zero and use it as the base register. The | |
1770 | * mips assembler simply uses register $zero. Just one tiny optimization | |
1771 | * we're missing. | |
1772 | */ | |
1773 | static void | |
1774 | macro (ip) | |
1775 | struct mips_cl_insn *ip; | |
1776 | { | |
670a50eb ILT |
1777 | register int treg, sreg, dreg, breg; |
1778 | int tempreg; | |
1779 | int mask; | |
1780 | int icnt = 0; | |
1781 | int used_at; | |
670a50eb ILT |
1782 | expressionS expr1; |
1783 | const char *s; | |
8358c818 | 1784 | const char *s2; |
670a50eb | 1785 | const char *fmt; |
8358c818 ILT |
1786 | int likely = 0; |
1787 | int dbl = 0; | |
1788 | int coproc = 0; | |
6e8dda9c | 1789 | offsetT maxnum; |
9226253a | 1790 | bfd_reloc_code_real_type r; |
0dd2d296 | 1791 | char *p; |
55933a58 | 1792 | int hold_mips_optimize; |
670a50eb ILT |
1793 | |
1794 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
1795 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
1796 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
1797 | mask = ip->insn_mo->mask; | |
1798 | ||
5ac34ac3 ILT |
1799 | expr1.X_op = O_constant; |
1800 | expr1.X_op_symbol = NULL; | |
670a50eb ILT |
1801 | expr1.X_add_symbol = NULL; |
1802 | expr1.X_add_number = 1; | |
1803 | ||
1804 | switch (mask) | |
1805 | { | |
6e8dda9c ILT |
1806 | case M_DABS: |
1807 | dbl = 1; | |
3d3c5039 | 1808 | case M_ABS: |
6e8dda9c ILT |
1809 | /* bgez $a0,.+12 |
1810 | move v0,$a0 | |
1811 | sub v0,$zero,$a0 | |
1812 | */ | |
3d3c5039 | 1813 | |
becfe05e ILT |
1814 | mips_emit_delays (); |
1815 | ++mips_noreorder; | |
0dd2d296 | 1816 | mips_any_noreorder = 1; |
3d3c5039 | 1817 | |
670a50eb | 1818 | expr1.X_add_number = 8; |
0dd2d296 | 1819 | macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg); |
6e8dda9c | 1820 | if (dreg == sreg) |
0dd2d296 | 1821 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); |
6e8dda9c | 1822 | else |
0dd2d296 ILT |
1823 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, sreg, 0); |
1824 | macro_build ((char *) NULL, &icnt, NULL, | |
6e8dda9c ILT |
1825 | dbl ? "dsub" : "sub", |
1826 | "d,v,t", dreg, 0, sreg); | |
3d3c5039 | 1827 | |
becfe05e | 1828 | --mips_noreorder; |
670a50eb | 1829 | return; |
3d3c5039 ILT |
1830 | |
1831 | case M_ADD_I: | |
8358c818 ILT |
1832 | s = "addi"; |
1833 | s2 = "add"; | |
1834 | goto do_addi; | |
3d3c5039 | 1835 | case M_ADDU_I: |
8358c818 ILT |
1836 | s = "addiu"; |
1837 | s2 = "addu"; | |
1838 | goto do_addi; | |
1839 | case M_DADD_I: | |
6e8dda9c | 1840 | dbl = 1; |
8358c818 ILT |
1841 | s = "daddi"; |
1842 | s2 = "dadd"; | |
1843 | goto do_addi; | |
1844 | case M_DADDU_I: | |
6e8dda9c | 1845 | dbl = 1; |
8358c818 ILT |
1846 | s = "daddiu"; |
1847 | s2 = "daddu"; | |
1848 | do_addi: | |
6e8dda9c | 1849 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 1850 | { |
0dd2d296 | 1851 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg, |
9226253a | 1852 | (int) BFD_RELOC_LO16); |
670a50eb | 1853 | return; |
3d3c5039 | 1854 | } |
6e8dda9c | 1855 | load_register (&icnt, AT, &imm_expr); |
0dd2d296 | 1856 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
670a50eb | 1857 | break; |
3d3c5039 ILT |
1858 | |
1859 | case M_AND_I: | |
6e8dda9c ILT |
1860 | s = "andi"; |
1861 | s2 = "and"; | |
1862 | goto do_bit; | |
3d3c5039 | 1863 | case M_OR_I: |
6e8dda9c ILT |
1864 | s = "ori"; |
1865 | s2 = "or"; | |
1866 | goto do_bit; | |
3d3c5039 | 1867 | case M_NOR_I: |
6e8dda9c ILT |
1868 | s = ""; |
1869 | s2 = "nor"; | |
1870 | goto do_bit; | |
3d3c5039 | 1871 | case M_XOR_I: |
6e8dda9c ILT |
1872 | s = "xori"; |
1873 | s2 = "xor"; | |
1874 | do_bit: | |
1875 | if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000) | |
670a50eb | 1876 | { |
6e8dda9c | 1877 | if (mask != M_NOR_I) |
0dd2d296 ILT |
1878 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg, |
1879 | sreg, (int) BFD_RELOC_LO16); | |
6e8dda9c | 1880 | else |
670a50eb | 1881 | { |
0dd2d296 ILT |
1882 | macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i", |
1883 | treg, sreg, (int) BFD_RELOC_LO16); | |
1c803e52 | 1884 | macro_build ((char *) NULL, &icnt, NULL, "nor", "d,v,t", |
0dd2d296 | 1885 | treg, treg, 0); |
3d3c5039 | 1886 | } |
6e8dda9c | 1887 | return; |
3d3c5039 | 1888 | } |
6e8dda9c ILT |
1889 | |
1890 | load_register (&icnt, AT, &imm_expr); | |
0dd2d296 | 1891 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
670a50eb | 1892 | break; |
3d3c5039 ILT |
1893 | |
1894 | case M_BEQ_I: | |
8358c818 ILT |
1895 | s = "beq"; |
1896 | goto beq_i; | |
1897 | case M_BEQL_I: | |
1898 | s = "beql"; | |
1899 | likely = 1; | |
1900 | goto beq_i; | |
3d3c5039 | 1901 | case M_BNE_I: |
8358c818 ILT |
1902 | s = "bne"; |
1903 | goto beq_i; | |
1904 | case M_BNEL_I: | |
1905 | s = "bnel"; | |
1906 | likely = 1; | |
1907 | beq_i: | |
670a50eb ILT |
1908 | if (imm_expr.X_add_number == 0) |
1909 | { | |
0dd2d296 ILT |
1910 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, |
1911 | 0); | |
670a50eb ILT |
1912 | return; |
1913 | } | |
6e8dda9c | 1914 | load_register (&icnt, AT, &imm_expr); |
0dd2d296 | 1915 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT); |
670a50eb | 1916 | break; |
3d3c5039 | 1917 | |
8358c818 ILT |
1918 | case M_BGEL: |
1919 | likely = 1; | |
3d3c5039 | 1920 | case M_BGE: |
670a50eb ILT |
1921 | if (treg == 0) |
1922 | { | |
0dd2d296 | 1923 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
1924 | likely ? "bgezl" : "bgez", |
1925 | "s,p", sreg); | |
670a50eb | 1926 | return; |
3d3c5039 | 1927 | } |
9a7d824a ILT |
1928 | if (sreg == 0) |
1929 | { | |
0dd2d296 | 1930 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
1931 | likely ? "blezl" : "blez", |
1932 | "s,p", treg); | |
9a7d824a ILT |
1933 | return; |
1934 | } | |
0dd2d296 ILT |
1935 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); |
1936 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
1937 | likely ? "beql" : "beq", |
1938 | "s,t,p", AT, 0); | |
670a50eb | 1939 | break; |
3d3c5039 | 1940 | |
8358c818 ILT |
1941 | case M_BGTL_I: |
1942 | likely = 1; | |
3d3c5039 | 1943 | case M_BGT_I: |
9a7d824a | 1944 | /* check for > max integer */ |
6e8dda9c ILT |
1945 | maxnum = 0x7fffffff; |
1946 | if (mips_isa >= 3) | |
1947 | { | |
1948 | maxnum <<= 16; | |
1949 | maxnum |= 0xffff; | |
1950 | maxnum <<= 16; | |
1951 | maxnum |= 0xffff; | |
1952 | } | |
7b777690 ILT |
1953 | if (imm_expr.X_add_number >= maxnum |
1954 | && (mips_isa < 3 || sizeof (maxnum) > 4)) | |
9a7d824a ILT |
1955 | { |
1956 | do_false: | |
1957 | /* result is always false */ | |
8358c818 ILT |
1958 | if (! likely) |
1959 | { | |
1960 | as_warn ("Branch %s is always false (nop)", ip->insn_mo->name); | |
0dd2d296 | 1961 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); |
8358c818 ILT |
1962 | } |
1963 | else | |
1964 | { | |
1965 | as_warn ("Branch likely %s is always false", ip->insn_mo->name); | |
0dd2d296 ILT |
1966 | macro_build ((char *) NULL, &icnt, &offset_expr, "bnel", |
1967 | "s,t,p", 0, 0); | |
8358c818 | 1968 | } |
9a7d824a ILT |
1969 | return; |
1970 | } | |
670a50eb ILT |
1971 | imm_expr.X_add_number++; |
1972 | /* FALLTHROUGH */ | |
3d3c5039 | 1973 | case M_BGE_I: |
8358c818 ILT |
1974 | case M_BGEL_I: |
1975 | if (mask == M_BGEL_I) | |
1976 | likely = 1; | |
670a50eb ILT |
1977 | if (imm_expr.X_add_number == 0) |
1978 | { | |
0dd2d296 | 1979 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
1980 | likely ? "bgezl" : "bgez", |
1981 | "s,p", sreg); | |
670a50eb | 1982 | return; |
3d3c5039 | 1983 | } |
670a50eb ILT |
1984 | if (imm_expr.X_add_number == 1) |
1985 | { | |
0dd2d296 | 1986 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
1987 | likely ? "bgtzl" : "bgtz", |
1988 | "s,p", sreg); | |
670a50eb | 1989 | return; |
3d3c5039 | 1990 | } |
6e8dda9c ILT |
1991 | maxnum = 0x7fffffff; |
1992 | if (mips_isa >= 3) | |
1993 | { | |
1994 | maxnum <<= 16; | |
1995 | maxnum |= 0xffff; | |
1996 | maxnum <<= 16; | |
1997 | maxnum |= 0xffff; | |
1998 | } | |
1999 | maxnum = - maxnum - 1; | |
7b777690 ILT |
2000 | if (imm_expr.X_add_number <= maxnum |
2001 | && (mips_isa < 3 || sizeof (maxnum) > 4)) | |
9a7d824a ILT |
2002 | { |
2003 | do_true: | |
2004 | /* result is always true */ | |
2005 | as_warn ("Branch %s is always true", ip->insn_mo->name); | |
0dd2d296 | 2006 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); |
9a7d824a ILT |
2007 | return; |
2008 | } | |
6e8dda9c | 2009 | set_at (&icnt, sreg, 0); |
0dd2d296 | 2010 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2011 | likely ? "beql" : "beq", |
2012 | "s,t,p", AT, 0); | |
670a50eb | 2013 | break; |
3d3c5039 | 2014 | |
8358c818 ILT |
2015 | case M_BGEUL: |
2016 | likely = 1; | |
3d3c5039 | 2017 | case M_BGEU: |
670a50eb | 2018 | if (treg == 0) |
9a7d824a ILT |
2019 | goto do_true; |
2020 | if (sreg == 0) | |
670a50eb | 2021 | { |
0dd2d296 | 2022 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2023 | likely ? "beql" : "beq", |
2024 | "s,t,p", 0, treg); | |
670a50eb | 2025 | return; |
3d3c5039 | 2026 | } |
0dd2d296 ILT |
2027 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, |
2028 | treg); | |
2029 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
2030 | likely ? "beql" : "beq", |
2031 | "s,t,p", AT, 0); | |
670a50eb | 2032 | break; |
3d3c5039 | 2033 | |
8358c818 ILT |
2034 | case M_BGTUL_I: |
2035 | likely = 1; | |
9a7d824a | 2036 | case M_BGTU_I: |
6e8dda9c | 2037 | if (sreg == 0 || imm_expr.X_add_number == -1) |
9a7d824a ILT |
2038 | goto do_false; |
2039 | imm_expr.X_add_number++; | |
2040 | /* FALLTHROUGH */ | |
3d3c5039 | 2041 | case M_BGEU_I: |
8358c818 ILT |
2042 | case M_BGEUL_I: |
2043 | if (mask == M_BGEUL_I) | |
2044 | likely = 1; | |
670a50eb | 2045 | if (imm_expr.X_add_number == 0) |
9a7d824a | 2046 | goto do_true; |
670a50eb ILT |
2047 | if (imm_expr.X_add_number == 1) |
2048 | { | |
0dd2d296 | 2049 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2050 | likely ? "bnel" : "bne", |
2051 | "s,t,p", sreg, 0); | |
670a50eb | 2052 | return; |
3d3c5039 | 2053 | } |
6e8dda9c | 2054 | set_at (&icnt, sreg, 1); |
0dd2d296 | 2055 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2056 | likely ? "beql" : "beq", |
2057 | "s,t,p", AT, 0); | |
670a50eb | 2058 | break; |
3d3c5039 | 2059 | |
8358c818 ILT |
2060 | case M_BGTL: |
2061 | likely = 1; | |
3d3c5039 | 2062 | case M_BGT: |
670a50eb ILT |
2063 | if (treg == 0) |
2064 | { | |
0dd2d296 | 2065 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2066 | likely ? "bgtzl" : "bgtz", |
2067 | "s,p", sreg); | |
670a50eb | 2068 | return; |
3d3c5039 | 2069 | } |
9a7d824a ILT |
2070 | if (sreg == 0) |
2071 | { | |
0dd2d296 | 2072 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2073 | likely ? "bltzl" : "bltz", |
2074 | "s,p", treg); | |
9a7d824a ILT |
2075 | return; |
2076 | } | |
0dd2d296 ILT |
2077 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); |
2078 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
2079 | likely ? "bnel" : "bne", |
2080 | "s,t,p", AT, 0); | |
670a50eb | 2081 | break; |
3d3c5039 | 2082 | |
8358c818 ILT |
2083 | case M_BGTUL: |
2084 | likely = 1; | |
3d3c5039 | 2085 | case M_BGTU: |
670a50eb ILT |
2086 | if (treg == 0) |
2087 | { | |
0dd2d296 | 2088 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2089 | likely ? "bnel" : "bne", |
2090 | "s,t,p", sreg, 0); | |
670a50eb | 2091 | return; |
3d3c5039 | 2092 | } |
9a7d824a ILT |
2093 | if (sreg == 0) |
2094 | goto do_false; | |
0dd2d296 ILT |
2095 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, |
2096 | sreg); | |
2097 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
2098 | likely ? "bnel" : "bne", |
2099 | "s,t,p", AT, 0); | |
670a50eb | 2100 | break; |
3d3c5039 | 2101 | |
8358c818 ILT |
2102 | case M_BLEL: |
2103 | likely = 1; | |
3d3c5039 | 2104 | case M_BLE: |
670a50eb ILT |
2105 | if (treg == 0) |
2106 | { | |
0dd2d296 | 2107 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2108 | likely ? "blezl" : "blez", |
2109 | "s,p", sreg); | |
670a50eb ILT |
2110 | return; |
2111 | } | |
9a7d824a ILT |
2112 | if (sreg == 0) |
2113 | { | |
0dd2d296 | 2114 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2115 | likely ? "bgezl" : "bgez", |
2116 | "s,p", treg); | |
9a7d824a ILT |
2117 | return; |
2118 | } | |
0dd2d296 ILT |
2119 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); |
2120 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
2121 | likely ? "beql" : "beq", |
2122 | "s,t,p", AT, 0); | |
670a50eb | 2123 | break; |
3d3c5039 | 2124 | |
8358c818 ILT |
2125 | case M_BLEL_I: |
2126 | likely = 1; | |
3d3c5039 | 2127 | case M_BLE_I: |
6e8dda9c ILT |
2128 | maxnum = 0x7fffffff; |
2129 | if (mips_isa >= 3) | |
2130 | { | |
2131 | maxnum <<= 16; | |
2132 | maxnum |= 0xffff; | |
2133 | maxnum <<= 16; | |
2134 | maxnum |= 0xffff; | |
2135 | } | |
7b777690 ILT |
2136 | if (imm_expr.X_add_number >= maxnum |
2137 | && (mips_isa < 3 || sizeof (maxnum) > 4)) | |
9a7d824a ILT |
2138 | goto do_true; |
2139 | imm_expr.X_add_number++; | |
2140 | /* FALLTHROUGH */ | |
9a7d824a | 2141 | case M_BLT_I: |
8358c818 ILT |
2142 | case M_BLTL_I: |
2143 | if (mask == M_BLTL_I) | |
2144 | likely = 1; | |
670a50eb ILT |
2145 | if (imm_expr.X_add_number == 0) |
2146 | { | |
0dd2d296 | 2147 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2148 | likely ? "bltzl" : "bltz", |
2149 | "s,p", sreg); | |
670a50eb ILT |
2150 | return; |
2151 | } | |
9a7d824a | 2152 | if (imm_expr.X_add_number == 1) |
670a50eb | 2153 | { |
0dd2d296 | 2154 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2155 | likely ? "blezl" : "blez", |
2156 | "s,p", sreg); | |
670a50eb ILT |
2157 | return; |
2158 | } | |
6e8dda9c | 2159 | set_at (&icnt, sreg, 0); |
0dd2d296 | 2160 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2161 | likely ? "bnel" : "bne", |
2162 | "s,t,p", AT, 0); | |
670a50eb | 2163 | break; |
3d3c5039 | 2164 | |
8358c818 ILT |
2165 | case M_BLEUL: |
2166 | likely = 1; | |
3d3c5039 | 2167 | case M_BLEU: |
670a50eb ILT |
2168 | if (treg == 0) |
2169 | { | |
0dd2d296 | 2170 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2171 | likely ? "beql" : "beq", |
2172 | "s,t,p", sreg, 0); | |
670a50eb | 2173 | return; |
3d3c5039 | 2174 | } |
9a7d824a ILT |
2175 | if (sreg == 0) |
2176 | goto do_true; | |
0dd2d296 ILT |
2177 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, |
2178 | sreg); | |
2179 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
2180 | likely ? "beql" : "beq", |
2181 | "s,t,p", AT, 0); | |
670a50eb | 2182 | break; |
3d3c5039 | 2183 | |
8358c818 ILT |
2184 | case M_BLEUL_I: |
2185 | likely = 1; | |
3d3c5039 | 2186 | case M_BLEU_I: |
6e8dda9c | 2187 | if (sreg == 0 || imm_expr.X_add_number == -1) |
9a7d824a ILT |
2188 | goto do_true; |
2189 | imm_expr.X_add_number++; | |
2190 | /* FALLTHROUGH */ | |
9a7d824a | 2191 | case M_BLTU_I: |
8358c818 ILT |
2192 | case M_BLTUL_I: |
2193 | if (mask == M_BLTUL_I) | |
2194 | likely = 1; | |
670a50eb | 2195 | if (imm_expr.X_add_number == 0) |
9a7d824a ILT |
2196 | goto do_false; |
2197 | if (imm_expr.X_add_number == 1) | |
670a50eb | 2198 | { |
0dd2d296 | 2199 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2200 | likely ? "beql" : "beq", |
2201 | "s,t,p", sreg, 0); | |
670a50eb | 2202 | return; |
3d3c5039 | 2203 | } |
6e8dda9c | 2204 | set_at (&icnt, sreg, 1); |
0dd2d296 | 2205 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2206 | likely ? "bnel" : "bne", |
2207 | "s,t,p", AT, 0); | |
670a50eb | 2208 | break; |
3d3c5039 | 2209 | |
8358c818 ILT |
2210 | case M_BLTL: |
2211 | likely = 1; | |
3d3c5039 | 2212 | case M_BLT: |
670a50eb ILT |
2213 | if (treg == 0) |
2214 | { | |
0dd2d296 | 2215 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2216 | likely ? "bltzl" : "bltz", |
2217 | "s,p", sreg); | |
670a50eb | 2218 | return; |
3d3c5039 | 2219 | } |
9a7d824a | 2220 | if (sreg == 0) |
670a50eb | 2221 | { |
0dd2d296 | 2222 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2223 | likely ? "bgtzl" : "bgtz", |
2224 | "s,p", treg); | |
670a50eb | 2225 | return; |
3d3c5039 | 2226 | } |
0dd2d296 ILT |
2227 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); |
2228 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
2229 | likely ? "bnel" : "bne", |
2230 | "s,t,p", AT, 0); | |
670a50eb | 2231 | break; |
3d3c5039 | 2232 | |
8358c818 ILT |
2233 | case M_BLTUL: |
2234 | likely = 1; | |
3d3c5039 | 2235 | case M_BLTU: |
670a50eb | 2236 | if (treg == 0) |
9a7d824a ILT |
2237 | goto do_false; |
2238 | if (sreg == 0) | |
670a50eb | 2239 | { |
0dd2d296 | 2240 | macro_build ((char *) NULL, &icnt, &offset_expr, |
8358c818 ILT |
2241 | likely ? "bnel" : "bne", |
2242 | "s,t,p", 0, treg); | |
670a50eb ILT |
2243 | return; |
2244 | } | |
0dd2d296 ILT |
2245 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, |
2246 | treg); | |
2247 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
8358c818 ILT |
2248 | likely ? "bnel" : "bne", |
2249 | "s,t,p", AT, 0); | |
670a50eb | 2250 | break; |
3d3c5039 | 2251 | |
8358c818 ILT |
2252 | case M_DDIV_3: |
2253 | dbl = 1; | |
3d3c5039 | 2254 | case M_DIV_3: |
8358c818 ILT |
2255 | s = "mflo"; |
2256 | goto do_div3; | |
2257 | case M_DREM_3: | |
2258 | dbl = 1; | |
3d3c5039 | 2259 | case M_REM_3: |
8358c818 ILT |
2260 | s = "mfhi"; |
2261 | do_div3: | |
670a50eb ILT |
2262 | if (treg == 0) |
2263 | { | |
2264 | as_warn ("Divide by zero."); | |
8ea7f4e8 ILT |
2265 | if (mips_trap) |
2266 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
2267 | else | |
2268 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
670a50eb ILT |
2269 | return; |
2270 | } | |
2271 | ||
becfe05e ILT |
2272 | mips_emit_delays (); |
2273 | ++mips_noreorder; | |
0dd2d296 ILT |
2274 | mips_any_noreorder = 1; |
2275 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 | 2276 | dbl ? "ddiv" : "div", |
ff3a5c18 | 2277 | "z,s,t", sreg, treg); |
8ea7f4e8 ILT |
2278 | if (mips_trap) |
2279 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
2280 | else | |
2281 | { | |
2282 | expr1.X_add_number = 8; | |
2283 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
2284 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
2285 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
2286 | } | |
670a50eb | 2287 | expr1.X_add_number = -1; |
0dd2d296 | 2288 | macro_build ((char *) NULL, &icnt, &expr1, |
8358c818 | 2289 | dbl ? "daddiu" : "addiu", |
9226253a | 2290 | "t,r,j", AT, 0, (int) BFD_RELOC_LO16); |
8ea7f4e8 | 2291 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
0dd2d296 | 2292 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT); |
8358c818 ILT |
2293 | if (dbl) |
2294 | { | |
2295 | expr1.X_add_number = 1; | |
0dd2d296 | 2296 | macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0, |
9226253a | 2297 | (int) BFD_RELOC_LO16); |
0dd2d296 ILT |
2298 | macro_build ((char *) NULL, &icnt, NULL, "dsll32", "d,w,<", AT, AT, |
2299 | 31); | |
8358c818 ILT |
2300 | } |
2301 | else | |
2302 | { | |
2303 | expr1.X_add_number = 0x80000000; | |
ecd4ca1c ILT |
2304 | macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT, |
2305 | (int) BFD_RELOC_HI16); | |
8358c818 | 2306 | } |
8ea7f4e8 ILT |
2307 | if (mips_trap) |
2308 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", sreg, AT); | |
2309 | else | |
2310 | { | |
2311 | expr1.X_add_number = 8; | |
2312 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT); | |
2313 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
2314 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
2315 | } | |
becfe05e | 2316 | --mips_noreorder; |
0dd2d296 | 2317 | macro_build ((char *) NULL, &icnt, NULL, s, "d", dreg); |
670a50eb | 2318 | break; |
3d3c5039 ILT |
2319 | |
2320 | case M_DIV_3I: | |
8358c818 ILT |
2321 | s = "div"; |
2322 | s2 = "mflo"; | |
2323 | goto do_divi; | |
3d3c5039 | 2324 | case M_DIVU_3I: |
8358c818 ILT |
2325 | s = "divu"; |
2326 | s2 = "mflo"; | |
2327 | goto do_divi; | |
3d3c5039 | 2328 | case M_REM_3I: |
8358c818 ILT |
2329 | s = "div"; |
2330 | s2 = "mfhi"; | |
2331 | goto do_divi; | |
3d3c5039 | 2332 | case M_REMU_3I: |
8358c818 ILT |
2333 | s = "divu"; |
2334 | s2 = "mfhi"; | |
2335 | goto do_divi; | |
2336 | case M_DDIV_3I: | |
2337 | dbl = 1; | |
2338 | s = "ddiv"; | |
2339 | s2 = "mflo"; | |
2340 | goto do_divi; | |
2341 | case M_DDIVU_3I: | |
2342 | dbl = 1; | |
2343 | s = "ddivu"; | |
2344 | s2 = "mflo"; | |
2345 | goto do_divi; | |
2346 | case M_DREM_3I: | |
2347 | dbl = 1; | |
2348 | s = "ddiv"; | |
2349 | s2 = "mfhi"; | |
2350 | goto do_divi; | |
2351 | case M_DREMU_3I: | |
2352 | dbl = 1; | |
2353 | s = "ddivu"; | |
2354 | s2 = "mfhi"; | |
2355 | do_divi: | |
670a50eb ILT |
2356 | if (imm_expr.X_add_number == 0) |
2357 | { | |
2358 | as_warn ("Divide by zero."); | |
8ea7f4e8 ILT |
2359 | if (mips_trap) |
2360 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
2361 | else | |
2362 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
670a50eb ILT |
2363 | return; |
2364 | } | |
2365 | if (imm_expr.X_add_number == 1) | |
2366 | { | |
8358c818 | 2367 | if (strcmp (s2, "mflo") == 0) |
0dd2d296 ILT |
2368 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, |
2369 | sreg); | |
3d3c5039 | 2370 | else |
0dd2d296 | 2371 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
3d3c5039 ILT |
2372 | return; |
2373 | } | |
8358c818 ILT |
2374 | if (imm_expr.X_add_number == -1 |
2375 | && s[strlen (s) - 1] != 'u') | |
2376 | { | |
2377 | if (strcmp (s2, "mflo") == 0) | |
2378 | { | |
2379 | if (dbl) | |
0dd2d296 ILT |
2380 | macro_build ((char *) NULL, &icnt, NULL, "dneg", "d,w", dreg, |
2381 | sreg); | |
8358c818 | 2382 | else |
0dd2d296 ILT |
2383 | macro_build ((char *) NULL, &icnt, NULL, "neg", "d,w", dreg, |
2384 | sreg); | |
8358c818 ILT |
2385 | } |
2386 | else | |
0dd2d296 | 2387 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
8358c818 ILT |
2388 | return; |
2389 | } | |
3d3c5039 | 2390 | |
6e8dda9c | 2391 | load_register (&icnt, AT, &imm_expr); |
0dd2d296 ILT |
2392 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, AT); |
2393 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); | |
670a50eb ILT |
2394 | break; |
2395 | ||
2396 | case M_DIVU_3: | |
8358c818 ILT |
2397 | s = "divu"; |
2398 | s2 = "mflo"; | |
2399 | goto do_divu3; | |
670a50eb | 2400 | case M_REMU_3: |
8358c818 ILT |
2401 | s = "divu"; |
2402 | s2 = "mfhi"; | |
2403 | goto do_divu3; | |
2404 | case M_DDIVU_3: | |
2405 | s = "ddivu"; | |
2406 | s2 = "mflo"; | |
2407 | goto do_divu3; | |
2408 | case M_DREMU_3: | |
2409 | s = "ddivu"; | |
2410 | s2 = "mfhi"; | |
2411 | do_divu3: | |
becfe05e ILT |
2412 | mips_emit_delays (); |
2413 | ++mips_noreorder; | |
0dd2d296 ILT |
2414 | mips_any_noreorder = 1; |
2415 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, treg); | |
8ea7f4e8 ILT |
2416 | if (mips_trap) |
2417 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
2418 | else | |
2419 | { | |
2420 | expr1.X_add_number = 8; | |
2421 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
2422 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
2423 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
2424 | } | |
becfe05e | 2425 | --mips_noreorder; |
0dd2d296 | 2426 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); |
670a50eb | 2427 | return; |
3d3c5039 | 2428 | |
0dd2d296 | 2429 | case M_LA_AB: |
d9aba805 ILT |
2430 | /* Load the address of a symbol into a register. If breg is not |
2431 | zero, we then add a base register to it. */ | |
ecd4ca1c ILT |
2432 | |
2433 | /* When generating embedded PIC code, we permit expressions of | |
2434 | the form | |
2435 | la $4,foo-bar | |
2436 | where bar is an address in the .text section. These are used | |
2437 | when getting the addresses of functions. We don't permit | |
2438 | X_add_number to be non-zero, because if the symbol is | |
2439 | external the relaxing code needs to know that any addend is | |
2440 | purely the offset to X_op_symbol. */ | |
2441 | if (mips_pic == EMBEDDED_PIC | |
2442 | && offset_expr.X_op == O_subtract | |
2443 | && now_seg == text_section | |
2444 | && S_GET_SEGMENT (offset_expr.X_op_symbol) == text_section | |
2445 | && breg == 0 | |
2446 | && offset_expr.X_add_number == 0) | |
2447 | { | |
2448 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
2449 | treg, (int) BFD_RELOC_PCREL_HI16_S); | |
2450 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
2451 | mips_isa < 3 ? "addiu" : "daddiu", | |
2452 | "t,r,j", treg, treg, (int) BFD_RELOC_PCREL_LO16); | |
2453 | return; | |
2454 | } | |
2455 | ||
0dd2d296 ILT |
2456 | if (offset_expr.X_op != O_symbol |
2457 | && offset_expr.X_op != O_constant) | |
670a50eb | 2458 | { |
0dd2d296 ILT |
2459 | as_bad ("expression too complex"); |
2460 | offset_expr.X_op = O_constant; | |
2461 | } | |
2462 | ||
2463 | if (treg == breg) | |
2464 | { | |
2465 | tempreg = AT; | |
2466 | used_at = 1; | |
3d3c5039 | 2467 | } |
670a50eb ILT |
2468 | else |
2469 | { | |
0dd2d296 ILT |
2470 | tempreg = treg; |
2471 | used_at = 0; | |
670a50eb | 2472 | } |
3d3c5039 | 2473 | |
5ac34ac3 | 2474 | if (offset_expr.X_op == O_constant) |
6e8dda9c | 2475 | load_register (&icnt, tempreg, &offset_expr); |
d9aba805 | 2476 | else if (mips_pic == NO_PIC) |
670a50eb | 2477 | { |
0dd2d296 ILT |
2478 | /* If this is a reference to an GP relative symbol, we want |
2479 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
2480 | Otherwise we want | |
2481 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
2482 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
2483 | If we have a constant, we need two instructions anyhow, | |
2484 | so we may as well always use the latter form. */ | |
2485 | if (offset_expr.X_add_number != 0) | |
2486 | p = NULL; | |
2487 | else | |
2488 | { | |
8ea7f4e8 | 2489 | frag_grow (20); |
0dd2d296 ILT |
2490 | macro_build ((char *) NULL, &icnt, &offset_expr, |
2491 | mips_isa < 3 ? "addiu" : "daddiu", | |
2492 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
2493 | p = frag_var (rs_machine_dependent, 8, 0, | |
2494 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
2495 | mips_warn_about_macros), | |
2496 | offset_expr.X_add_symbol, (long) 0, | |
2497 | (char *) NULL); | |
2498 | } | |
2499 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
2500 | if (p != NULL) | |
2501 | p += 4; | |
2502 | macro_build (p, &icnt, &offset_expr, | |
6e8dda9c | 2503 | mips_isa < 3 ? "addiu" : "daddiu", |
0dd2d296 ILT |
2504 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
2505 | } | |
d9aba805 | 2506 | else if (mips_pic == SVR4_PIC) |
0dd2d296 ILT |
2507 | { |
2508 | /* If this is a reference to an external symbol, and there | |
2509 | is no constant, we want | |
2510 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
2511 | For a local symbol, we want | |
2512 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
2513 | nop | |
2514 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
2515 | ||
2516 | If we have a small constant, and this is a reference to | |
2517 | an external symbol, we want | |
2518 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
2519 | nop | |
2520 | addiu $tempreg,$tempreg,<constant> | |
2521 | For a local symbol, we want the same instruction | |
2522 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
2523 | addiu instruction. | |
2524 | ||
2525 | If we have a large constant, and this is a reference to | |
2526 | an external symbol, we want | |
2527 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
2528 | lui $at,<hiconstant> | |
2529 | addiu $at,$at,<loconstant> | |
2530 | addu $tempreg,$tempreg,$at | |
2531 | For a local symbol, we want the same instruction | |
2532 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
2533 | addiu instruction. */ | |
2534 | expr1.X_add_number = offset_expr.X_add_number; | |
2535 | offset_expr.X_add_number = 0; | |
8ea7f4e8 | 2536 | frag_grow (32); |
0dd2d296 ILT |
2537 | macro_build ((char *) NULL, &icnt, &offset_expr, |
2538 | mips_isa < 3 ? "lw" : "ld", | |
2539 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
2540 | if (expr1.X_add_number == 0) | |
2541 | { | |
2542 | int off; | |
2543 | ||
2544 | if (breg == 0) | |
2545 | off = 0; | |
2546 | else | |
2547 | { | |
2548 | /* We're going to put in an addu instruction using | |
2549 | tempreg, so we may as well insert the nop right | |
2550 | now. */ | |
2551 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
2552 | "nop", ""); | |
2553 | off = 4; | |
2554 | } | |
2555 | p = frag_var (rs_machine_dependent, 8 - off, 0, | |
2556 | RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0, | |
2557 | (breg == 0 | |
2558 | ? mips_warn_about_macros | |
2559 | : 0)), | |
2560 | offset_expr.X_add_symbol, (long) 0, | |
2561 | (char *) NULL); | |
2562 | if (breg == 0) | |
2563 | { | |
2564 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
2565 | p += 4; | |
2566 | } | |
2567 | macro_build (p, &icnt, &expr1, | |
2568 | mips_isa < 3 ? "addiu" : "daddiu", | |
2569 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
2570 | /* FIXME: If breg == 0, and the next instruction uses | |
2571 | $tempreg, then if this variant case is used an extra | |
2572 | nop will be generated. */ | |
2573 | } | |
2574 | else if (expr1.X_add_number >= -0x8000 | |
2575 | && expr1.X_add_number < 0x8000) | |
2576 | { | |
2577 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
2578 | "nop", ""); | |
2579 | macro_build ((char *) NULL, &icnt, &expr1, | |
2580 | mips_isa < 3 ? "addiu" : "daddiu", | |
2581 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
2582 | (void) frag_var (rs_machine_dependent, 0, 0, | |
2583 | RELAX_ENCODE (0, 0, -12, -4, 0, 0), | |
2584 | offset_expr.X_add_symbol, (long) 0, | |
2585 | (char *) NULL); | |
2586 | } | |
2587 | else | |
2588 | { | |
2589 | int off1; | |
2590 | ||
2591 | /* If we are going to add in a base register, and the | |
2592 | target register and the base register are the same, | |
2593 | then we are using AT as a temporary register. Since | |
2594 | we want to load the constant into AT, we add our | |
2595 | current AT (from the global offset table) and the | |
2596 | register into the register now, and pretend we were | |
2597 | not using a base register. */ | |
2598 | if (breg != treg) | |
2599 | off1 = 0; | |
2600 | else | |
2601 | { | |
2602 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
2603 | "nop", ""); | |
2604 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
2605 | mips_isa < 3 ? "addu" : "daddu", | |
2606 | "d,v,t", treg, AT, breg); | |
2607 | breg = 0; | |
2608 | tempreg = treg; | |
2609 | off1 = -8; | |
2610 | } | |
2611 | ||
55933a58 ILT |
2612 | /* Set mips_optimize around the lui instruction to avoid |
2613 | inserting an unnecessary nop after the lw. */ | |
2614 | hold_mips_optimize = mips_optimize; | |
2615 | mips_optimize = 2; | |
0dd2d296 | 2616 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); |
55933a58 ILT |
2617 | mips_optimize = hold_mips_optimize; |
2618 | ||
0dd2d296 ILT |
2619 | macro_build ((char *) NULL, &icnt, &expr1, |
2620 | mips_isa < 3 ? "addiu" : "daddiu", | |
2621 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); | |
2622 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
2623 | mips_isa < 3 ? "addu" : "daddu", | |
2624 | "d,v,t", tempreg, tempreg, AT); | |
2625 | (void) frag_var (rs_machine_dependent, 0, 0, | |
2626 | RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0), | |
2627 | offset_expr.X_add_symbol, (long) 0, | |
2628 | (char *) NULL); | |
2629 | used_at = 1; | |
2630 | } | |
670a50eb | 2631 | } |
d9aba805 ILT |
2632 | else if (mips_pic == EMBEDDED_PIC) |
2633 | { | |
2634 | /* We use | |
2635 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
2636 | */ | |
2637 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
2638 | mips_isa < 3 ? "addiu" : "daddiu", | |
2639 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
2640 | } | |
2641 | else | |
2642 | abort (); | |
0dd2d296 | 2643 | |
670a50eb | 2644 | if (breg != 0) |
0dd2d296 ILT |
2645 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
2646 | mips_isa < 3 ? "addu" : "daddu", | |
2647 | "d,v,t", treg, tempreg, breg); | |
2648 | ||
2649 | if (! used_at) | |
2650 | return; | |
2651 | ||
2652 | break; | |
2653 | ||
2654 | case M_J_A: | |
2655 | /* The j instruction may not be used in PIC code, since it | |
2656 | requires an absolute address. We convert it to a b | |
2657 | instruction. */ | |
d9aba805 | 2658 | if (mips_pic == NO_PIC) |
0dd2d296 ILT |
2659 | macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a"); |
2660 | else | |
2661 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); | |
670a50eb | 2662 | return; |
3d3c5039 | 2663 | |
9226253a ILT |
2664 | /* The jal instructions must be handled as macros because when |
2665 | generating PIC code they expand to multi-instruction | |
2666 | sequences. Normally they are simple instructions. */ | |
2667 | case M_JAL_1: | |
2668 | dreg = RA; | |
2669 | /* Fall through. */ | |
2670 | case M_JAL_2: | |
d9aba805 ILT |
2671 | if (mips_pic == NO_PIC |
2672 | || mips_pic == EMBEDDED_PIC) | |
2673 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", | |
2674 | "d,s", dreg, sreg); | |
2675 | else if (mips_pic == SVR4_PIC) | |
9226253a | 2676 | { |
d9aba805 ILT |
2677 | if (sreg != PIC_CALL_REG) |
2678 | as_warn ("MIPS PIC call to register other than $25"); | |
2679 | ||
0dd2d296 ILT |
2680 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", |
2681 | "d,s", dreg, sreg); | |
d9aba805 ILT |
2682 | if (mips_cprestore_offset < 0) |
2683 | as_warn ("No .cprestore pseudo-op used in PIC code"); | |
2684 | else | |
2685 | { | |
2686 | expr1.X_add_number = mips_cprestore_offset; | |
2687 | macro_build ((char *) NULL, &icnt, &expr1, | |
2688 | mips_isa < 3 ? "lw" : "ld", | |
2689 | "t,o(b)", GP, (int) BFD_RELOC_LO16, mips_frame_reg); | |
2690 | } | |
9226253a | 2691 | } |
0dd2d296 | 2692 | else |
d9aba805 ILT |
2693 | abort (); |
2694 | ||
9226253a ILT |
2695 | return; |
2696 | ||
2697 | case M_JAL_A: | |
d9aba805 ILT |
2698 | if (mips_pic == NO_PIC) |
2699 | macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a"); | |
2700 | else if (mips_pic == SVR4_PIC) | |
9226253a | 2701 | { |
d9aba805 ILT |
2702 | /* If this is a reference to an external symbol, we want |
2703 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
2704 | nop | |
2705 | jalr $25 | |
2706 | nop | |
2707 | lw $gp,cprestore($sp) | |
2708 | The cprestore value is set using the .cprestore | |
2709 | pseudo-op. If the symbol is not external, we want | |
2710 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
2711 | nop | |
2712 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
2713 | jalr $25 | |
2714 | nop | |
2715 | lw $gp,cprestore($sp) | |
2716 | */ | |
2717 | frag_grow (20); | |
2718 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
0dd2d296 | 2719 | mips_isa < 3 ? "lw" : "ld", |
d9aba805 ILT |
2720 | "t,o(b)", PIC_CALL_REG, |
2721 | (int) BFD_RELOC_MIPS_CALL16, GP); | |
2722 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
2723 | p = frag_var (rs_machine_dependent, 4, 0, | |
2724 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
2725 | offset_expr.X_add_symbol, (long) 0, (char *) NULL); | |
2726 | macro_build (p, &icnt, &offset_expr, | |
2727 | mips_isa < 3 ? "addiu" : "daddiu", | |
2728 | "t,r,j", PIC_CALL_REG, PIC_CALL_REG, | |
2729 | (int) BFD_RELOC_LO16); | |
2730 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
2731 | "jalr", "s", PIC_CALL_REG); | |
2732 | if (mips_cprestore_offset < 0) | |
2733 | as_warn ("No .cprestore pseudo-op used in PIC code"); | |
2734 | else | |
2735 | { | |
2736 | if (mips_noreorder) | |
2737 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
2738 | "nop", ""); | |
2739 | expr1.X_add_number = mips_cprestore_offset; | |
2740 | macro_build ((char *) NULL, &icnt, &expr1, | |
2741 | mips_isa < 3 ? "lw" : "ld", | |
2742 | "t,o(b)", GP, (int) BFD_RELOC_LO16, | |
2743 | mips_frame_reg); | |
2744 | } | |
0dd2d296 | 2745 | } |
d9aba805 | 2746 | else if (mips_pic == EMBEDDED_PIC) |
5b63f465 ILT |
2747 | { |
2748 | macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p"); | |
2749 | /* The linker may expand the call to a longer sequence which | |
2750 | uses $at, so we must break rather than return. */ | |
2751 | break; | |
2752 | } | |
d9aba805 ILT |
2753 | else |
2754 | abort (); | |
2755 | ||
9226253a ILT |
2756 | return; |
2757 | ||
3d3c5039 | 2758 | case M_LB_AB: |
670a50eb ILT |
2759 | s = "lb"; |
2760 | goto ld; | |
3d3c5039 | 2761 | case M_LBU_AB: |
670a50eb ILT |
2762 | s = "lbu"; |
2763 | goto ld; | |
3d3c5039 | 2764 | case M_LH_AB: |
670a50eb ILT |
2765 | s = "lh"; |
2766 | goto ld; | |
3d3c5039 | 2767 | case M_LHU_AB: |
670a50eb ILT |
2768 | s = "lhu"; |
2769 | goto ld; | |
3d3c5039 | 2770 | case M_LW_AB: |
670a50eb ILT |
2771 | s = "lw"; |
2772 | goto ld; | |
3d3c5039 | 2773 | case M_LWC0_AB: |
670a50eb | 2774 | s = "lwc0"; |
8358c818 | 2775 | coproc = 1; |
670a50eb | 2776 | goto ld; |
3d3c5039 | 2777 | case M_LWC1_AB: |
670a50eb | 2778 | s = "lwc1"; |
8358c818 | 2779 | coproc = 1; |
670a50eb | 2780 | goto ld; |
3d3c5039 | 2781 | case M_LWC2_AB: |
670a50eb | 2782 | s = "lwc2"; |
8358c818 | 2783 | coproc = 1; |
670a50eb | 2784 | goto ld; |
3d3c5039 | 2785 | case M_LWC3_AB: |
670a50eb | 2786 | s = "lwc3"; |
8358c818 | 2787 | coproc = 1; |
670a50eb | 2788 | goto ld; |
3d3c5039 | 2789 | case M_LWL_AB: |
670a50eb ILT |
2790 | s = "lwl"; |
2791 | goto ld; | |
3d3c5039 | 2792 | case M_LWR_AB: |
670a50eb | 2793 | s = "lwr"; |
8358c818 ILT |
2794 | goto ld; |
2795 | case M_LDC1_AB: | |
2796 | s = "ldc1"; | |
2797 | coproc = 1; | |
2798 | goto ld; | |
2799 | case M_LDC2_AB: | |
2800 | s = "ldc2"; | |
2801 | coproc = 1; | |
2802 | goto ld; | |
2803 | case M_LDC3_AB: | |
2804 | s = "ldc3"; | |
2805 | coproc = 1; | |
2806 | goto ld; | |
2807 | case M_LDL_AB: | |
2808 | s = "ldl"; | |
2809 | goto ld; | |
2810 | case M_LDR_AB: | |
2811 | s = "ldr"; | |
2812 | goto ld; | |
2813 | case M_LL_AB: | |
2814 | s = "ll"; | |
2815 | goto ld; | |
2816 | case M_LLD_AB: | |
2817 | s = "lld"; | |
2818 | goto ld; | |
2819 | case M_LWU_AB: | |
2820 | s = "lwu"; | |
3d3c5039 | 2821 | ld: |
8358c818 | 2822 | if (breg == treg || coproc) |
670a50eb ILT |
2823 | { |
2824 | tempreg = AT; | |
2825 | used_at = 1; | |
2826 | } | |
2827 | else | |
2828 | { | |
2829 | tempreg = treg; | |
2830 | used_at = 0; | |
2831 | } | |
2832 | goto ld_st; | |
3d3c5039 | 2833 | case M_SB_AB: |
670a50eb ILT |
2834 | s = "sb"; |
2835 | goto st; | |
3d3c5039 | 2836 | case M_SH_AB: |
670a50eb ILT |
2837 | s = "sh"; |
2838 | goto st; | |
3d3c5039 | 2839 | case M_SW_AB: |
670a50eb ILT |
2840 | s = "sw"; |
2841 | goto st; | |
3d3c5039 | 2842 | case M_SWC0_AB: |
670a50eb | 2843 | s = "swc0"; |
8358c818 | 2844 | coproc = 1; |
670a50eb | 2845 | goto st; |
3d3c5039 | 2846 | case M_SWC1_AB: |
670a50eb | 2847 | s = "swc1"; |
8358c818 | 2848 | coproc = 1; |
670a50eb | 2849 | goto st; |
3d3c5039 | 2850 | case M_SWC2_AB: |
670a50eb | 2851 | s = "swc2"; |
8358c818 | 2852 | coproc = 1; |
670a50eb | 2853 | goto st; |
3d3c5039 | 2854 | case M_SWC3_AB: |
670a50eb | 2855 | s = "swc3"; |
8358c818 | 2856 | coproc = 1; |
670a50eb | 2857 | goto st; |
3d3c5039 | 2858 | case M_SWL_AB: |
670a50eb ILT |
2859 | s = "swl"; |
2860 | goto st; | |
3d3c5039 | 2861 | case M_SWR_AB: |
670a50eb | 2862 | s = "swr"; |
8358c818 ILT |
2863 | goto st; |
2864 | case M_SC_AB: | |
2865 | s = "sc"; | |
2866 | goto st; | |
2867 | case M_SCD_AB: | |
2868 | s = "scd"; | |
2869 | goto st; | |
2870 | case M_SDC1_AB: | |
2871 | s = "sdc1"; | |
2872 | coproc = 1; | |
2873 | goto st; | |
2874 | case M_SDC2_AB: | |
2875 | s = "sdc2"; | |
2876 | coproc = 1; | |
2877 | goto st; | |
2878 | case M_SDC3_AB: | |
2879 | s = "sdc3"; | |
2880 | coproc = 1; | |
2881 | goto st; | |
2882 | case M_SDL_AB: | |
2883 | s = "sdl"; | |
2884 | goto st; | |
2885 | case M_SDR_AB: | |
2886 | s = "sdr"; | |
3d3c5039 | 2887 | st: |
670a50eb ILT |
2888 | tempreg = AT; |
2889 | used_at = 1; | |
3d3c5039 | 2890 | ld_st: |
8358c818 ILT |
2891 | if (mask == M_LWC1_AB |
2892 | || mask == M_SWC1_AB | |
8358c818 | 2893 | || mask == M_LDC1_AB |
0dd2d296 ILT |
2894 | || mask == M_SDC1_AB |
2895 | || mask == M_L_DAB | |
2896 | || mask == M_S_DAB) | |
670a50eb | 2897 | fmt = "T,o(b)"; |
8358c818 | 2898 | else if (coproc) |
19ed8960 | 2899 | fmt = "E,o(b)"; |
670a50eb ILT |
2900 | else |
2901 | fmt = "t,o(b)"; | |
0dd2d296 ILT |
2902 | |
2903 | if (offset_expr.X_op != O_constant | |
2904 | && offset_expr.X_op != O_symbol) | |
2905 | { | |
2906 | as_bad ("expression too complex"); | |
2907 | offset_expr.X_op = O_constant; | |
2908 | } | |
2909 | ||
2910 | /* A constant expression in PIC code can be handled just as it | |
2911 | is in non PIC code. */ | |
d9aba805 | 2912 | if (mips_pic == NO_PIC |
0dd2d296 | 2913 | || offset_expr.X_op == O_constant) |
670a50eb | 2914 | { |
0dd2d296 ILT |
2915 | /* If this is a reference to a GP relative symbol, and there |
2916 | is no base register, we want | |
2917 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
d9aba805 | 2918 | Otherwise, if there is no base register, we want |
0dd2d296 ILT |
2919 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) |
2920 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
2921 | If we have a constant, we need two instructions anyhow, | |
2922 | so we always use the latter form. | |
2923 | ||
2924 | If we have a base register, and this is a reference to a | |
2925 | GP relative symbol, we want | |
2926 | addu $tempreg,$breg,$gp | |
2927 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
2928 | Otherwise we want | |
2929 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
2930 | addu $tempreg,$tempreg,$breg | |
2931 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
2932 | With a constant we always use the latter case. */ | |
670a50eb ILT |
2933 | if (breg == 0) |
2934 | { | |
0dd2d296 ILT |
2935 | if (offset_expr.X_add_number != 0) |
2936 | p = NULL; | |
2937 | else | |
2938 | { | |
8ea7f4e8 | 2939 | frag_grow (20); |
0dd2d296 ILT |
2940 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
2941 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
2942 | p = frag_var (rs_machine_dependent, 8, 0, | |
2943 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
8197b589 ILT |
2944 | (mips_warn_about_macros |
2945 | || (used_at && mips_noat))), | |
0dd2d296 ILT |
2946 | offset_expr.X_add_symbol, (long) 0, |
2947 | (char *) NULL); | |
8197b589 | 2948 | used_at = 0; |
0dd2d296 ILT |
2949 | } |
2950 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
2951 | if (p != NULL) | |
2952 | p += 4; | |
2953 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
2954 | (int) BFD_RELOC_LO16, tempreg); | |
2955 | } | |
2956 | else | |
2957 | { | |
2958 | if (offset_expr.X_add_number != 0) | |
2959 | p = NULL; | |
2960 | else | |
2961 | { | |
8ea7f4e8 | 2962 | frag_grow (28); |
0dd2d296 ILT |
2963 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
2964 | mips_isa < 3 ? "addu" : "daddu", | |
2965 | "d,v,t", tempreg, breg, GP); | |
2966 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
2967 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
2968 | p = frag_var (rs_machine_dependent, 12, 0, | |
2969 | RELAX_ENCODE (8, 12, 0, 8, 0, 0), | |
2970 | offset_expr.X_add_symbol, (long) 0, | |
2971 | (char *) NULL); | |
2972 | } | |
2973 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
2974 | if (p != NULL) | |
2975 | p += 4; | |
2976 | macro_build (p, &icnt, (expressionS *) NULL, | |
2977 | mips_isa < 3 ? "addu" : "daddu", | |
2978 | "d,v,t", tempreg, tempreg, breg); | |
2979 | if (p != NULL) | |
2980 | p += 4; | |
2981 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
2982 | (int) BFD_RELOC_LO16, tempreg); | |
670a50eb | 2983 | } |
670a50eb | 2984 | } |
d9aba805 | 2985 | else if (mips_pic == SVR4_PIC) |
670a50eb | 2986 | { |
0dd2d296 ILT |
2987 | /* If this is a reference to an external symbol, we want |
2988 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
2989 | nop | |
2990 | <op> $treg,0($tempreg) | |
2991 | Otherwise we want | |
2992 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
2993 | nop | |
2994 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
2995 | <op> $treg,0($tempreg) | |
2996 | If there is a base register, we add it to $tempreg before | |
2997 | the <op>. If there is a constant, we stick it in the | |
2998 | <op> instruction. We don't handle constants larger than | |
2999 | 16 bits, because we have no way to load the upper 16 bits | |
3000 | (actually, we could handle them for the subset of cases | |
3001 | in which we are not using $at). */ | |
3002 | assert (offset_expr.X_op == O_symbol); | |
3003 | expr1.X_add_number = offset_expr.X_add_number; | |
3004 | offset_expr.X_add_number = 0; | |
3005 | if (expr1.X_add_number < -0x8000 | |
3006 | || expr1.X_add_number >= 0x8000) | |
3007 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
8ea7f4e8 | 3008 | frag_grow (20); |
0dd2d296 ILT |
3009 | macro_build ((char *) NULL, &icnt, &offset_expr, |
3010 | mips_isa < 3 ? "lw" : "ld", | |
3011 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
3012 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
3013 | p = frag_var (rs_machine_dependent, 4, 0, | |
3014 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
3015 | offset_expr.X_add_symbol, (long) 0, | |
3016 | (char *) NULL); | |
3017 | macro_build (p, &icnt, &offset_expr, | |
3018 | mips_isa < 3 ? "addiu" : "daddiu", | |
3019 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
670a50eb | 3020 | if (breg != 0) |
0dd2d296 | 3021 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
6e8dda9c ILT |
3022 | mips_isa < 3 ? "addu" : "daddu", |
3023 | "d,v,t", tempreg, tempreg, breg); | |
0dd2d296 ILT |
3024 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, |
3025 | (int) BFD_RELOC_LO16, tempreg); | |
670a50eb | 3026 | } |
d9aba805 ILT |
3027 | else if (mips_pic == EMBEDDED_PIC) |
3028 | { | |
3029 | /* If there is no base register, we want | |
3030 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
3031 | If there is a base register, we want | |
3032 | addu $tempreg,$breg,$gp | |
3033 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
3034 | */ | |
3035 | assert (offset_expr.X_op == O_symbol); | |
3036 | if (breg == 0) | |
3037 | { | |
3038 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
3039 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
3040 | used_at = 0; | |
3041 | } | |
3042 | else | |
3043 | { | |
3044 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3045 | mips_isa < 3 ? "addu" : "daddu", | |
3046 | "d,v,t", tempreg, breg, GP); | |
3047 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
3048 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
3049 | } | |
3050 | } | |
3051 | else | |
3052 | abort (); | |
0dd2d296 ILT |
3053 | |
3054 | if (! used_at) | |
3055 | return; | |
3056 | ||
3057 | break; | |
3d3c5039 ILT |
3058 | |
3059 | case M_LI: | |
19ed8960 | 3060 | case M_LI_S: |
6e8dda9c | 3061 | load_register (&icnt, treg, &imm_expr); |
670a50eb | 3062 | return; |
3d3c5039 | 3063 | |
0dd2d296 | 3064 | case M_LI_SS: |
55933a58 | 3065 | if (imm_expr.X_op == O_constant) |
0dd2d296 | 3066 | { |
d2c71068 ILT |
3067 | load_register (&icnt, AT, &imm_expr); |
3068 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3069 | "mtc1", "t,G", AT, treg); | |
3070 | break; | |
0dd2d296 | 3071 | } |
d9aba805 | 3072 | else |
d2c71068 | 3073 | { |
55933a58 ILT |
3074 | assert (offset_expr.X_op == O_symbol |
3075 | && strcmp (segment_name (S_GET_SEGMENT | |
3076 | (offset_expr.X_add_symbol)), | |
3077 | ".lit4") == 0 | |
3078 | && offset_expr.X_add_number == 0); | |
3079 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", | |
3080 | treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
d2c71068 ILT |
3081 | return; |
3082 | } | |
0dd2d296 | 3083 | |
3d3c5039 | 3084 | case M_LI_D: |
d9aba805 ILT |
3085 | /* We know that sym is in the .rdata section. First we get the |
3086 | upper 16 bits of the address. */ | |
3087 | if (mips_pic == NO_PIC) | |
0dd2d296 ILT |
3088 | { |
3089 | /* FIXME: This won't work for a 64 bit address. */ | |
3090 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
3091 | } | |
d9aba805 | 3092 | else if (mips_pic == SVR4_PIC) |
0dd2d296 ILT |
3093 | { |
3094 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3095 | mips_isa < 3 ? "lw" : "ld", | |
3096 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
3097 | } | |
d9aba805 ILT |
3098 | else if (mips_pic == EMBEDDED_PIC) |
3099 | { | |
3100 | /* For embedded PIC we pick up the entire address off $gp in | |
3101 | a single instruction. */ | |
3102 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3103 | mips_isa < 3 ? "addiu" : "daddiu", | |
3104 | "t,r,j", AT, GP, (int) BFD_RELOC_MIPS_GPREL); | |
3105 | offset_expr.X_op = O_constant; | |
3106 | offset_expr.X_add_number = 0; | |
3107 | } | |
3108 | else | |
3109 | abort (); | |
3110 | ||
0dd2d296 | 3111 | /* Now we load the register(s). */ |
8358c818 | 3112 | if (mips_isa >= 3) |
0dd2d296 ILT |
3113 | macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)", |
3114 | treg, (int) BFD_RELOC_LO16, AT); | |
8358c818 ILT |
3115 | else |
3116 | { | |
0dd2d296 ILT |
3117 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", |
3118 | treg, (int) BFD_RELOC_LO16, AT); | |
3119 | if (treg != 31) | |
3120 | { | |
3121 | /* FIXME: How in the world do we deal with the possible | |
3122 | overflow here? */ | |
3123 | offset_expr.X_add_number += 4; | |
3124 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", | |
3125 | treg + 1, (int) BFD_RELOC_LO16, AT); | |
3126 | } | |
8358c818 | 3127 | } |
d2c71068 ILT |
3128 | |
3129 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
3130 | does not become a variant frag. */ | |
3131 | frag_wane (frag_now); | |
3132 | frag_new (0); | |
3133 | ||
670a50eb | 3134 | break; |
3d3c5039 ILT |
3135 | |
3136 | case M_LI_DD: | |
55933a58 ILT |
3137 | assert (offset_expr.X_op == O_symbol |
3138 | && offset_expr.X_add_number == 0); | |
3139 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
3140 | if (strcmp (s, ".lit8") == 0) | |
8358c818 | 3141 | { |
0dd2d296 ILT |
3142 | if (mips_isa >= 2) |
3143 | { | |
3144 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
3145 | "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
3146 | return; | |
3147 | } | |
3148 | breg = GP; | |
3149 | r = BFD_RELOC_MIPS_LITERAL; | |
3150 | goto dob; | |
3151 | } | |
55933a58 | 3152 | else |
0dd2d296 | 3153 | { |
55933a58 ILT |
3154 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
3155 | if (mips_pic == SVR4_PIC) | |
3156 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3157 | mips_isa < 3 ? "lw" : "ld", | |
3158 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
3159 | else | |
3160 | { | |
3161 | /* FIXME: This won't work for a 64 bit address. */ | |
3162 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
3163 | } | |
3164 | ||
0dd2d296 ILT |
3165 | if (mips_isa >= 2) |
3166 | { | |
3167 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
55933a58 | 3168 | "T,o(b)", treg, (int) BFD_RELOC_LO16, AT); |
94b68f04 ILT |
3169 | |
3170 | /* To avoid confusion in tc_gen_reloc, we must ensure | |
3171 | that this does not become a variant frag. */ | |
3172 | frag_wane (frag_now); | |
3173 | frag_new (0); | |
3174 | ||
0dd2d296 ILT |
3175 | break; |
3176 | } | |
3177 | breg = AT; | |
3178 | r = BFD_RELOC_LO16; | |
3179 | goto dob; | |
8358c818 | 3180 | } |
9226253a | 3181 | |
3d3c5039 | 3182 | case M_L_DOB: |
9a7d824a ILT |
3183 | /* Even on a big endian machine $fn comes before $fn+1. We have |
3184 | to adjust when loading from memory. */ | |
9226253a ILT |
3185 | r = BFD_RELOC_LO16; |
3186 | dob: | |
8358c818 | 3187 | assert (mips_isa < 2); |
0dd2d296 | 3188 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
9a7d824a | 3189 | byte_order == LITTLE_ENDIAN ? treg : treg + 1, |
9226253a | 3190 | (int) r, breg); |
0dd2d296 ILT |
3191 | /* FIXME: A possible overflow which I don't know how to deal |
3192 | with. */ | |
670a50eb | 3193 | offset_expr.X_add_number += 4; |
0dd2d296 | 3194 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
9a7d824a | 3195 | byte_order == LITTLE_ENDIAN ? treg + 1 : treg, |
9226253a | 3196 | (int) r, breg); |
d2c71068 ILT |
3197 | |
3198 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
3199 | does not become a variant frag. */ | |
3200 | frag_wane (frag_now); | |
3201 | frag_new (0); | |
3202 | ||
0dd2d296 ILT |
3203 | if (breg != AT) |
3204 | return; | |
3205 | break; | |
3d3c5039 ILT |
3206 | |
3207 | case M_L_DAB: | |
670a50eb ILT |
3208 | /* |
3209 | * The MIPS assembler seems to check for X_add_number not | |
3210 | * being double aligned and generating: | |
3211 | * lui at,%hi(foo+1) | |
3212 | * addu at,at,v1 | |
3213 | * addiu at,at,%lo(foo+1) | |
3214 | * lwc1 f2,0(at) | |
3215 | * lwc1 f3,4(at) | |
3216 | * But, the resulting address is the same after relocation so why | |
3217 | * generate the extra instruction? | |
3218 | */ | |
4032d3f0 | 3219 | coproc = 1; |
0dd2d296 | 3220 | if (mips_isa >= 2) |
670a50eb | 3221 | { |
0dd2d296 ILT |
3222 | s = "ldc1"; |
3223 | goto ld; | |
670a50eb | 3224 | } |
0dd2d296 ILT |
3225 | |
3226 | s = "lwc1"; | |
3227 | fmt = "T,o(b)"; | |
0dd2d296 ILT |
3228 | goto ldd_std; |
3229 | ||
3230 | case M_S_DAB: | |
8358c818 | 3231 | if (mips_isa >= 2) |
8358c818 | 3232 | { |
0dd2d296 ILT |
3233 | s = "sdc1"; |
3234 | goto st; | |
8358c818 | 3235 | } |
3d3c5039 | 3236 | |
0dd2d296 ILT |
3237 | s = "swc1"; |
3238 | fmt = "T,o(b)"; | |
3239 | coproc = 1; | |
3240 | goto ldd_std; | |
3d3c5039 ILT |
3241 | |
3242 | case M_LD_AB: | |
0dd2d296 | 3243 | if (mips_isa >= 3) |
670a50eb | 3244 | { |
0dd2d296 ILT |
3245 | s = "ld"; |
3246 | goto ld; | |
670a50eb | 3247 | } |
0dd2d296 ILT |
3248 | |
3249 | s = "lw"; | |
3250 | fmt = "t,o(b)"; | |
3251 | goto ldd_std; | |
3252 | ||
3253 | case M_SD_AB: | |
3254 | if (mips_isa >= 3) | |
670a50eb | 3255 | { |
0dd2d296 ILT |
3256 | s = "sd"; |
3257 | goto st; | |
670a50eb | 3258 | } |
0dd2d296 | 3259 | |
670a50eb | 3260 | s = "sw"; |
0dd2d296 ILT |
3261 | fmt = "t,o(b)"; |
3262 | ||
3263 | ldd_std: | |
3264 | if (offset_expr.X_op != O_symbol | |
3265 | && offset_expr.X_op != O_constant) | |
670a50eb | 3266 | { |
0dd2d296 ILT |
3267 | as_bad ("expression too complex"); |
3268 | offset_expr.X_op = O_constant; | |
3269 | } | |
3270 | ||
3271 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
3272 | to adjust when loading from memory. We set coproc if we must | |
3273 | load $fn+1 first. */ | |
3274 | if (byte_order == LITTLE_ENDIAN) | |
3275 | coproc = 0; | |
3276 | ||
d9aba805 | 3277 | if (mips_pic == NO_PIC |
0dd2d296 ILT |
3278 | || offset_expr.X_op == O_constant) |
3279 | { | |
3280 | /* If this is a reference to a GP relative symbol, we want | |
3281 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
3282 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
3283 | If we have a base register, we use this | |
3284 | addu $at,$breg,$gp | |
3285 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
3286 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
3287 | If this is not a GP relative symbol, we want | |
3288 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
3289 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
3290 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
3291 | If there is a base register, we add it to $at after the | |
3292 | lui instruction. If there is a constant, we always use | |
3293 | the last case. */ | |
3294 | if (offset_expr.X_add_number != 0) | |
670a50eb | 3295 | { |
0dd2d296 ILT |
3296 | p = NULL; |
3297 | used_at = 1; | |
670a50eb ILT |
3298 | } |
3299 | else | |
0dd2d296 ILT |
3300 | { |
3301 | int off; | |
3302 | ||
3303 | if (breg == 0) | |
3304 | { | |
8ea7f4e8 | 3305 | frag_grow (28); |
0dd2d296 ILT |
3306 | tempreg = GP; |
3307 | off = 0; | |
3308 | used_at = 0; | |
3309 | } | |
3310 | else | |
3311 | { | |
8ea7f4e8 | 3312 | frag_grow (36); |
0dd2d296 ILT |
3313 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
3314 | mips_isa < 3 ? "addu" : "daddu", | |
3315 | "d,v,t", AT, breg, GP); | |
3316 | tempreg = AT; | |
3317 | off = 4; | |
3318 | used_at = 1; | |
3319 | } | |
3320 | ||
3321 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
3322 | coproc ? treg + 1 : treg, | |
3323 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
3324 | offset_expr.X_add_number += 4; | |
55933a58 ILT |
3325 | |
3326 | /* Set mips_optimize to 2 to avoid inserting an | |
3327 | undesired nop. */ | |
3328 | hold_mips_optimize = mips_optimize; | |
3329 | mips_optimize = 2; | |
0dd2d296 ILT |
3330 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
3331 | coproc ? treg : treg + 1, | |
3332 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
55933a58 ILT |
3333 | mips_optimize = hold_mips_optimize; |
3334 | ||
0dd2d296 ILT |
3335 | p = frag_var (rs_machine_dependent, 12 + off, 0, |
3336 | RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1, | |
8197b589 | 3337 | used_at && mips_noat), |
0dd2d296 ILT |
3338 | offset_expr.X_add_symbol, (long) 0, |
3339 | (char *) NULL); | |
777ad64d ILT |
3340 | |
3341 | /* We just generated two relocs. When tc_gen_reloc | |
3342 | handles this case, it will skip the first reloc and | |
3343 | handle the second. The second reloc already has an | |
3344 | extra addend of 4, which we added above. We must | |
3345 | subtract it out, and then subtract another 4 to make | |
3346 | the first reloc come out right. The second reloc | |
3347 | will come out right because we are going to add 4 to | |
3348 | offset_expr when we build its instruction below. */ | |
3349 | offset_expr.X_add_number -= 8; | |
0dd2d296 ILT |
3350 | offset_expr.X_op = O_constant; |
3351 | } | |
3352 | macro_build_lui (p, &icnt, &offset_expr, AT); | |
3353 | if (p != NULL) | |
3354 | p += 4; | |
3355 | if (breg != 0) | |
3356 | { | |
3357 | macro_build (p, &icnt, (expressionS *) NULL, | |
3358 | mips_isa < 3 ? "addu" : "daddu", | |
3359 | "d,v,t", AT, breg, AT); | |
3360 | if (p != NULL) | |
3361 | p += 4; | |
3362 | } | |
3363 | macro_build (p, &icnt, &offset_expr, s, fmt, | |
3364 | coproc ? treg + 1 : treg, | |
3365 | (int) BFD_RELOC_LO16, AT); | |
3366 | if (p != NULL) | |
3367 | p += 4; | |
3368 | /* FIXME: How do we handle overflow here? */ | |
3369 | offset_expr.X_add_number += 4; | |
3370 | macro_build (p, &icnt, &offset_expr, s, fmt, | |
3371 | coproc ? treg : treg + 1, | |
3372 | (int) BFD_RELOC_LO16, AT); | |
3373 | } | |
d9aba805 | 3374 | else if (mips_pic == SVR4_PIC) |
670a50eb | 3375 | { |
0dd2d296 ILT |
3376 | int off; |
3377 | ||
3378 | /* If this is a reference to an external symbol, we want | |
3379 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3380 | nop | |
3381 | <op> $treg,0($at) | |
3382 | <op> $treg+1,4($at) | |
3383 | Otherwise we want | |
3384 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3385 | nop | |
3386 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
3387 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
3388 | If there is a base register we add it to $at before the | |
3389 | lwc1 instructions. If there is a constant we include it | |
3390 | in the lwc1 instructions. */ | |
3391 | used_at = 1; | |
3392 | expr1.X_add_number = offset_expr.X_add_number; | |
3393 | offset_expr.X_add_number = 0; | |
3394 | if (expr1.X_add_number < -0x8000 | |
3395 | || expr1.X_add_number >= 0x8000 - 4) | |
3396 | as_bad ("PIC code offset overflow (max 16 signed bits)"); | |
3397 | if (breg == 0) | |
3398 | off = 0; | |
3399 | else | |
3400 | off = 4; | |
8ea7f4e8 | 3401 | frag_grow (24 + off); |
0dd2d296 ILT |
3402 | macro_build ((char *) NULL, &icnt, &offset_expr, |
3403 | mips_isa < 3 ? "lw" : "ld", | |
3404 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
3405 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
670a50eb | 3406 | if (breg != 0) |
0dd2d296 | 3407 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
6e8dda9c | 3408 | mips_isa < 3 ? "addu" : "daddu", |
0dd2d296 ILT |
3409 | "d,v,t", AT, breg, AT); |
3410 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, | |
3411 | coproc ? treg + 1 : treg, | |
3412 | (int) BFD_RELOC_LO16, AT); | |
3413 | expr1.X_add_number += 4; | |
55933a58 ILT |
3414 | |
3415 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
3416 | nop. */ | |
3417 | hold_mips_optimize = mips_optimize; | |
3418 | mips_optimize = 2; | |
0dd2d296 ILT |
3419 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
3420 | coproc ? treg : treg + 1, | |
3421 | (int) BFD_RELOC_LO16, AT); | |
55933a58 ILT |
3422 | mips_optimize = hold_mips_optimize; |
3423 | ||
0dd2d296 ILT |
3424 | (void) frag_var (rs_machine_dependent, 0, 0, |
3425 | RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0), | |
3426 | offset_expr.X_add_symbol, (long) 0, | |
3427 | (char *) NULL); | |
8358c818 | 3428 | } |
d9aba805 ILT |
3429 | else if (mips_pic == EMBEDDED_PIC) |
3430 | { | |
3431 | /* If there is no base register, we use | |
3432 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
3433 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
3434 | If we have a base register, we use | |
3435 | addu $at,$breg,$gp | |
3436 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
3437 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
3438 | */ | |
3439 | if (breg == 0) | |
3440 | { | |
3441 | tempreg = GP; | |
3442 | used_at = 0; | |
3443 | } | |
3444 | else | |
3445 | { | |
3446 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
3447 | mips_isa < 3 ? "addu" : "daddu", | |
3448 | "d,v,t", AT, breg, GP); | |
3449 | tempreg = AT; | |
3450 | used_at = 1; | |
3451 | } | |
3452 | ||
3453 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
3454 | coproc ? treg + 1 : treg, | |
3455 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
3456 | offset_expr.X_add_number += 4; | |
3457 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
3458 | coproc ? treg : treg + 1, | |
3459 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
3460 | } | |
3461 | else | |
3462 | abort (); | |
0dd2d296 ILT |
3463 | |
3464 | if (! used_at) | |
3465 | return; | |
3466 | ||
3467 | break; | |
3468 | ||
3469 | case M_LD_OB: | |
3470 | s = "lw"; | |
3471 | goto sd_ob; | |
3472 | case M_SD_OB: | |
3473 | s = "sw"; | |
3474 | sd_ob: | |
3475 | assert (mips_isa < 3); | |
3476 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
3477 | (int) BFD_RELOC_LO16, breg); | |
3478 | offset_expr.X_add_number += 4; | |
3479 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1, | |
3480 | (int) BFD_RELOC_LO16, breg); | |
670a50eb | 3481 | return; |
917fae09 SS |
3482 | #ifdef LOSING_COMPILER |
3483 | default: | |
3484 | macro2 (ip); | |
3485 | return; | |
3486 | } | |
3487 | if (mips_noat) | |
3488 | as_warn ("Macro used $at after \".set noat\""); | |
3489 | } | |
3490 | ||
3491 | static void | |
3492 | macro2 (ip) | |
3493 | struct mips_cl_insn *ip; | |
3494 | { | |
3495 | register int treg, sreg, dreg, breg; | |
3496 | int tempreg; | |
3497 | int mask; | |
3498 | int icnt = 0; | |
3499 | int used_at; | |
3500 | expressionS expr1; | |
3501 | const char *s; | |
3502 | const char *s2; | |
3503 | const char *fmt; | |
3504 | int likely = 0; | |
3505 | int dbl = 0; | |
3506 | int coproc = 0; | |
3507 | offsetT maxnum; | |
3508 | bfd_reloc_code_real_type r; | |
3509 | char *p; | |
3510 | ||
3511 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
3512 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
3513 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
3514 | mask = ip->insn_mo->mask; | |
3515 | ||
3516 | expr1.X_op = O_constant; | |
3517 | expr1.X_op_symbol = NULL; | |
3518 | expr1.X_add_symbol = NULL; | |
3519 | expr1.X_add_number = 1; | |
3520 | ||
3521 | switch (mask) | |
3522 | { | |
3523 | #endif /* LOSING_COMPILER */ | |
3d3c5039 | 3524 | |
8358c818 ILT |
3525 | case M_DMUL: |
3526 | dbl = 1; | |
3d3c5039 | 3527 | case M_MUL: |
0dd2d296 | 3528 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
3529 | dbl ? "dmultu" : "multu", |
3530 | "s,t", sreg, treg); | |
0dd2d296 | 3531 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
670a50eb | 3532 | return; |
3d3c5039 | 3533 | |
8358c818 ILT |
3534 | case M_DMUL_I: |
3535 | dbl = 1; | |
3d3c5039 | 3536 | case M_MUL_I: |
8358c818 ILT |
3537 | /* The MIPS assembler some times generates shifts and adds. I'm |
3538 | not trying to be that fancy. GCC should do this for us | |
3539 | anyway. */ | |
6e8dda9c | 3540 | load_register (&icnt, AT, &imm_expr); |
0dd2d296 | 3541 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
3542 | dbl ? "dmult" : "mult", |
3543 | "s,t", sreg, AT); | |
0dd2d296 | 3544 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
670a50eb | 3545 | break; |
3d3c5039 | 3546 | |
8358c818 ILT |
3547 | case M_DMULO: |
3548 | dbl = 1; | |
3549 | case M_MULO: | |
3550 | mips_emit_delays (); | |
3551 | ++mips_noreorder; | |
0dd2d296 ILT |
3552 | mips_any_noreorder = 1; |
3553 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
3554 | dbl ? "dmult" : "mult", |
3555 | "s,t", sreg, treg); | |
0dd2d296 ILT |
3556 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
3557 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
3558 | dbl ? "dsra32" : "sra", |
3559 | "d,w,<", dreg, dreg, 31); | |
0dd2d296 | 3560 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); |
8ea7f4e8 ILT |
3561 | if (mips_trap) |
3562 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", dreg, AT); | |
3563 | else | |
3564 | { | |
3565 | expr1.X_add_number = 8; | |
3566 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg, AT); | |
3567 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3568 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
3569 | } | |
8358c818 | 3570 | --mips_noreorder; |
0dd2d296 | 3571 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
8358c818 ILT |
3572 | break; |
3573 | ||
3574 | case M_DMULOU: | |
3575 | dbl = 1; | |
3576 | case M_MULOU: | |
3577 | mips_emit_delays (); | |
3578 | ++mips_noreorder; | |
0dd2d296 ILT |
3579 | mips_any_noreorder = 1; |
3580 | macro_build ((char *) NULL, &icnt, NULL, | |
8358c818 ILT |
3581 | dbl ? "dmultu" : "multu", |
3582 | "s,t", sreg, treg); | |
0dd2d296 ILT |
3583 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); |
3584 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); | |
8ea7f4e8 ILT |
3585 | if (mips_trap) |
3586 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", AT, 0); | |
3587 | else | |
3588 | { | |
3589 | expr1.X_add_number = 8; | |
3590 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0); | |
3591 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3592 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
3593 | } | |
8358c818 ILT |
3594 | --mips_noreorder; |
3595 | break; | |
3596 | ||
3d3c5039 | 3597 | case M_ROL: |
0dd2d296 ILT |
3598 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); |
3599 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", AT, sreg, AT); | |
3600 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", dreg, sreg, | |
3601 | treg); | |
3602 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
670a50eb | 3603 | break; |
3d3c5039 ILT |
3604 | |
3605 | case M_ROL_I: | |
0dd2d296 | 3606 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", AT, sreg, |
670a50eb | 3607 | imm_expr.X_add_number & 0x1f); |
0dd2d296 | 3608 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, |
670a50eb | 3609 | (0 - imm_expr.X_add_number) & 0x1f); |
0dd2d296 | 3610 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); |
670a50eb | 3611 | break; |
3d3c5039 ILT |
3612 | |
3613 | case M_ROR: | |
0dd2d296 ILT |
3614 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); |
3615 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", AT, sreg, AT); | |
3616 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", dreg, sreg, | |
3617 | treg); | |
3618 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
670a50eb | 3619 | break; |
3d3c5039 ILT |
3620 | |
3621 | case M_ROR_I: | |
0dd2d296 | 3622 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, sreg, |
670a50eb | 3623 | imm_expr.X_add_number & 0x1f); |
0dd2d296 | 3624 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", dreg, sreg, |
670a50eb | 3625 | (0 - imm_expr.X_add_number) & 0x1f); |
0dd2d296 | 3626 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); |
670a50eb | 3627 | break; |
3d3c5039 ILT |
3628 | |
3629 | case M_S_DOB: | |
8358c818 | 3630 | assert (mips_isa < 2); |
9a7d824a ILT |
3631 | /* Even on a big endian machine $fn comes before $fn+1. We have |
3632 | to adjust when storing to memory. */ | |
0dd2d296 | 3633 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
9a7d824a | 3634 | byte_order == LITTLE_ENDIAN ? treg : treg + 1, |
9226253a | 3635 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 3636 | offset_expr.X_add_number += 4; |
0dd2d296 | 3637 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
9a7d824a | 3638 | byte_order == LITTLE_ENDIAN ? treg + 1 : treg, |
9226253a | 3639 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 3640 | return; |
3d3c5039 | 3641 | |
3d3c5039 | 3642 | case M_SEQ: |
670a50eb | 3643 | if (sreg == 0) |
0dd2d296 ILT |
3644 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
3645 | treg, (int) BFD_RELOC_LO16); | |
670a50eb | 3646 | else if (treg == 0) |
0dd2d296 ILT |
3647 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
3648 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb ILT |
3649 | else |
3650 | { | |
0dd2d296 ILT |
3651 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
3652 | sreg, treg); | |
3653 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
3654 | dreg, (int) BFD_RELOC_LO16); | |
3d3c5039 | 3655 | } |
670a50eb | 3656 | return; |
3d3c5039 ILT |
3657 | |
3658 | case M_SEQ_I: | |
670a50eb ILT |
3659 | if (imm_expr.X_add_number == 0) |
3660 | { | |
0dd2d296 ILT |
3661 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
3662 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 3663 | return; |
3d3c5039 | 3664 | } |
670a50eb ILT |
3665 | if (sreg == 0) |
3666 | { | |
9a7d824a | 3667 | as_warn ("Instruction %s: result is always false", |
6e8dda9c | 3668 | ip->insn_mo->name); |
0dd2d296 | 3669 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); |
670a50eb | 3670 | return; |
3d3c5039 | 3671 | } |
6e8dda9c | 3672 | if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000) |
670a50eb | 3673 | { |
0dd2d296 ILT |
3674 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, |
3675 | sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 3676 | used_at = 0; |
6e8dda9c ILT |
3677 | } |
3678 | else if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number < 0) | |
3679 | { | |
3680 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 3681 | macro_build ((char *) NULL, &icnt, &imm_expr, |
6e8dda9c | 3682 | mips_isa < 3 ? "addiu" : "daddiu", |
9226253a ILT |
3683 | "t,r,j", dreg, sreg, |
3684 | (int) BFD_RELOC_LO16); | |
6e8dda9c ILT |
3685 | used_at = 0; |
3686 | } | |
3687 | else | |
3688 | { | |
3689 | load_register (&icnt, AT, &imm_expr); | |
0dd2d296 ILT |
3690 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
3691 | sreg, AT); | |
670a50eb ILT |
3692 | used_at = 1; |
3693 | } | |
0dd2d296 | 3694 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg, |
9226253a | 3695 | (int) BFD_RELOC_LO16); |
670a50eb ILT |
3696 | if (used_at) |
3697 | break; | |
3698 | return; | |
3d3c5039 ILT |
3699 | |
3700 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
670a50eb ILT |
3701 | s = "slt"; |
3702 | goto sge; | |
3d3c5039 | 3703 | case M_SGEU: |
670a50eb | 3704 | s = "sltu"; |
3d3c5039 | 3705 | sge: |
0dd2d296 ILT |
3706 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, sreg, treg); |
3707 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 3708 | (int) BFD_RELOC_LO16); |
670a50eb | 3709 | return; |
3d3c5039 | 3710 | |
670a50eb | 3711 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ |
3d3c5039 | 3712 | case M_SGEU_I: |
6e8dda9c | 3713 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 3714 | { |
0dd2d296 | 3715 | macro_build ((char *) NULL, &icnt, &expr1, |
6e8dda9c | 3716 | mask == M_SGE_I ? "slti" : "sltiu", |
9226253a | 3717 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb ILT |
3718 | used_at = 0; |
3719 | } | |
3720 | else | |
3721 | { | |
6e8dda9c | 3722 | load_register (&icnt, AT, &imm_expr); |
0dd2d296 | 3723 | macro_build ((char *) NULL, &icnt, NULL, |
6e8dda9c ILT |
3724 | mask == M_SGE_I ? "slt" : "sltu", |
3725 | "d,v,t", dreg, sreg, AT); | |
670a50eb ILT |
3726 | used_at = 1; |
3727 | } | |
0dd2d296 | 3728 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
9226253a | 3729 | (int) BFD_RELOC_LO16); |
670a50eb ILT |
3730 | if (used_at) |
3731 | break; | |
3732 | return; | |
3d3c5039 ILT |
3733 | |
3734 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
670a50eb ILT |
3735 | s = "slt"; |
3736 | goto sgt; | |
3d3c5039 | 3737 | case M_SGTU: |
670a50eb | 3738 | s = "sltu"; |
3d3c5039 | 3739 | sgt: |
0dd2d296 | 3740 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); |
670a50eb | 3741 | return; |
3d3c5039 | 3742 | |
670a50eb ILT |
3743 | case M_SGT_I: /* sreg > I <==> I < sreg */ |
3744 | s = "slt"; | |
3745 | goto sgti; | |
3d3c5039 | 3746 | case M_SGTU_I: |
670a50eb | 3747 | s = "sltu"; |
3d3c5039 | 3748 | sgti: |
6e8dda9c | 3749 | load_register (&icnt, AT, &imm_expr); |
0dd2d296 | 3750 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); |
670a50eb | 3751 | break; |
3d3c5039 | 3752 | |
670a50eb ILT |
3753 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
3754 | s = "slt"; | |
3755 | goto sle; | |
3d3c5039 | 3756 | case M_SLEU: |
670a50eb | 3757 | s = "sltu"; |
3d3c5039 | 3758 | sle: |
0dd2d296 ILT |
3759 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); |
3760 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 3761 | (int) BFD_RELOC_LO16); |
670a50eb | 3762 | return; |
3d3c5039 | 3763 | |
670a50eb ILT |
3764 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
3765 | s = "slt"; | |
3766 | goto slei; | |
3d3c5039 | 3767 | case M_SLEU_I: |
670a50eb | 3768 | s = "sltu"; |
3d3c5039 | 3769 | slei: |
6e8dda9c | 3770 | load_register (&icnt, AT, &imm_expr); |
0dd2d296 ILT |
3771 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); |
3772 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
9226253a | 3773 | (int) BFD_RELOC_LO16); |
670a50eb | 3774 | break; |
3d3c5039 ILT |
3775 | |
3776 | case M_SLT_I: | |
6e8dda9c | 3777 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 3778 | { |
0dd2d296 ILT |
3779 | macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j", |
3780 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 3781 | return; |
3d3c5039 | 3782 | } |
6e8dda9c | 3783 | load_register (&icnt, AT, &imm_expr); |
0dd2d296 | 3784 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", dreg, sreg, AT); |
670a50eb | 3785 | break; |
3d3c5039 ILT |
3786 | |
3787 | case M_SLTU_I: | |
6e8dda9c | 3788 | if (imm_expr.X_add_number >= -0x8000 && imm_expr.X_add_number < 0x8000) |
670a50eb | 3789 | { |
0dd2d296 ILT |
3790 | macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j", |
3791 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 3792 | return; |
3d3c5039 | 3793 | } |
6e8dda9c | 3794 | load_register (&icnt, AT, &imm_expr); |
0dd2d296 ILT |
3795 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, sreg, |
3796 | AT); | |
670a50eb | 3797 | break; |
3d3c5039 ILT |
3798 | |
3799 | case M_SNE: | |
670a50eb | 3800 | if (sreg == 0) |
0dd2d296 ILT |
3801 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
3802 | treg); | |
670a50eb | 3803 | else if (treg == 0) |
0dd2d296 ILT |
3804 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
3805 | sreg); | |
670a50eb ILT |
3806 | else |
3807 | { | |
0dd2d296 ILT |
3808 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
3809 | sreg, treg); | |
3810 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, | |
3811 | dreg); | |
3d3c5039 | 3812 | } |
670a50eb | 3813 | return; |
3d3c5039 ILT |
3814 | |
3815 | case M_SNE_I: | |
670a50eb ILT |
3816 | if (imm_expr.X_add_number == 0) |
3817 | { | |
0dd2d296 ILT |
3818 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
3819 | sreg); | |
670a50eb | 3820 | return; |
3d3c5039 | 3821 | } |
670a50eb ILT |
3822 | if (sreg == 0) |
3823 | { | |
9a7d824a | 3824 | as_warn ("Instruction %s: result is always true", |
6e8dda9c | 3825 | ip->insn_mo->name); |
0dd2d296 | 3826 | macro_build ((char *) NULL, &icnt, &expr1, |
6e8dda9c | 3827 | mips_isa < 3 ? "addiu" : "daddiu", |
9226253a | 3828 | "t,r,j", dreg, 0, (int) BFD_RELOC_LO16); |
670a50eb | 3829 | return; |
3d3c5039 | 3830 | } |
6e8dda9c | 3831 | if (imm_expr.X_add_number >= 0 && imm_expr.X_add_number < 0x10000) |
670a50eb | 3832 | { |
0dd2d296 ILT |
3833 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", |
3834 | dreg, sreg, (int) BFD_RELOC_LO16); | |
670a50eb | 3835 | used_at = 0; |
6e8dda9c ILT |
3836 | } |
3837 | else if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number < 0) | |
3838 | { | |
3839 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 3840 | macro_build ((char *) NULL, &icnt, &imm_expr, |
6e8dda9c | 3841 | mips_isa < 3 ? "addiu" : "daddiu", |
9226253a | 3842 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
6e8dda9c ILT |
3843 | used_at = 0; |
3844 | } | |
3845 | else | |
3846 | { | |
3847 | load_register (&icnt, AT, &imm_expr); | |
0dd2d296 ILT |
3848 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
3849 | sreg, AT); | |
670a50eb ILT |
3850 | used_at = 1; |
3851 | } | |
0dd2d296 | 3852 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg); |
670a50eb ILT |
3853 | if (used_at) |
3854 | break; | |
3855 | return; | |
3d3c5039 | 3856 | |
8358c818 ILT |
3857 | case M_DSUB_I: |
3858 | dbl = 1; | |
3d3c5039 | 3859 | case M_SUB_I: |
6e8dda9c | 3860 | if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number <= 0x8000) |
670a50eb ILT |
3861 | { |
3862 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 3863 | macro_build ((char *) NULL, &icnt, &imm_expr, |
8358c818 | 3864 | dbl ? "daddi" : "addi", |
9226253a | 3865 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb | 3866 | return; |
3d3c5039 | 3867 | } |
6e8dda9c | 3868 | load_register (&icnt, AT, &imm_expr); |
0dd2d296 | 3869 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
3870 | dbl ? "dsub" : "sub", |
3871 | "d,v,t", dreg, sreg, AT); | |
670a50eb | 3872 | break; |
3d3c5039 | 3873 | |
8358c818 ILT |
3874 | case M_DSUBU_I: |
3875 | dbl = 1; | |
3d3c5039 | 3876 | case M_SUBU_I: |
6e8dda9c | 3877 | if (imm_expr.X_add_number > -0x8000 && imm_expr.X_add_number <= 0x8000) |
670a50eb ILT |
3878 | { |
3879 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
0dd2d296 | 3880 | macro_build ((char *) NULL, &icnt, &imm_expr, |
8358c818 | 3881 | dbl ? "daddiu" : "addiu", |
9226253a | 3882 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
670a50eb | 3883 | return; |
3d3c5039 | 3884 | } |
6e8dda9c | 3885 | load_register (&icnt, AT, &imm_expr); |
0dd2d296 | 3886 | macro_build ((char *) NULL, &icnt, NULL, |
8358c818 ILT |
3887 | dbl ? "dsubu" : "subu", |
3888 | "d,v,t", dreg, sreg, AT); | |
3889 | break; | |
3890 | ||
3891 | case M_TEQ_I: | |
3892 | s = "teq"; | |
3893 | goto trap; | |
3894 | case M_TGE_I: | |
3895 | s = "tge"; | |
3896 | goto trap; | |
3897 | case M_TGEU_I: | |
3898 | s = "tgeu"; | |
3899 | goto trap; | |
3900 | case M_TLT_I: | |
3901 | s = "tlt"; | |
3902 | goto trap; | |
3903 | case M_TLTU_I: | |
3904 | s = "tltu"; | |
3905 | goto trap; | |
3906 | case M_TNE_I: | |
3907 | s = "tne"; | |
3908 | trap: | |
6e8dda9c | 3909 | load_register (&icnt, AT, &imm_expr); |
0dd2d296 | 3910 | macro_build ((char *) NULL, &icnt, NULL, s, "s,t", sreg, AT); |
670a50eb | 3911 | break; |
3d3c5039 ILT |
3912 | |
3913 | case M_TRUNCWD: | |
3914 | case M_TRUNCWS: | |
8358c818 | 3915 | assert (mips_isa < 2); |
670a50eb ILT |
3916 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
3917 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
3918 | ||
3919 | /* | |
3920 | * Is the double cfc1 instruction a bug in the mips assembler; | |
3921 | * or is there a reason for it? | |
3922 | */ | |
becfe05e ILT |
3923 | mips_emit_delays (); |
3924 | ++mips_noreorder; | |
0dd2d296 ILT |
3925 | mips_any_noreorder = 1; |
3926 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
3927 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
3928 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
670a50eb | 3929 | expr1.X_add_number = 3; |
0dd2d296 | 3930 | macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg, |
9226253a | 3931 | (int) BFD_RELOC_LO16); |
670a50eb | 3932 | expr1.X_add_number = 2; |
0dd2d296 | 3933 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT, |
9226253a | 3934 | (int) BFD_RELOC_LO16); |
0dd2d296 ILT |
3935 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", AT, 31); |
3936 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
3937 | macro_build ((char *) NULL, &icnt, NULL, | |
670a50eb | 3938 | mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg); |
0dd2d296 ILT |
3939 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", treg, 31); |
3940 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
becfe05e | 3941 | --mips_noreorder; |
670a50eb | 3942 | break; |
3d3c5039 ILT |
3943 | |
3944 | case M_ULH: | |
670a50eb ILT |
3945 | s = "lb"; |
3946 | goto ulh; | |
3d3c5039 | 3947 | case M_ULHU: |
670a50eb | 3948 | s = "lbu"; |
3d3c5039 | 3949 | ulh: |
8ea7f4e8 ILT |
3950 | if (offset_expr.X_add_number >= 0x7fff) |
3951 | as_bad ("operand overflow"); | |
670a50eb | 3952 | /* avoid load delay */ |
8ea7f4e8 ILT |
3953 | if (byte_order == LITTLE_ENDIAN) |
3954 | offset_expr.X_add_number += 1; | |
0dd2d296 | 3955 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
9226253a | 3956 | (int) BFD_RELOC_LO16, breg); |
8ea7f4e8 ILT |
3957 | if (byte_order == LITTLE_ENDIAN) |
3958 | offset_expr.X_add_number -= 1; | |
3959 | else | |
3960 | offset_expr.X_add_number += 1; | |
0dd2d296 | 3961 | macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT, |
9226253a | 3962 | (int) BFD_RELOC_LO16, breg); |
0dd2d296 ILT |
3963 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8); |
3964 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT); | |
670a50eb | 3965 | break; |
3d3c5039 ILT |
3966 | |
3967 | case M_ULW: | |
8ea7f4e8 ILT |
3968 | if (offset_expr.X_add_number >= 0x7ffd) |
3969 | as_bad ("operand overflow"); | |
3970 | if (byte_order == LITTLE_ENDIAN) | |
3971 | offset_expr.X_add_number += 3; | |
0dd2d296 | 3972 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwl", "t,o(b)", treg, |
9226253a | 3973 | (int) BFD_RELOC_LO16, breg); |
8ea7f4e8 ILT |
3974 | if (byte_order == LITTLE_ENDIAN) |
3975 | offset_expr.X_add_number -= 3; | |
3976 | else | |
3977 | offset_expr.X_add_number += 3; | |
0dd2d296 | 3978 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwr", "t,o(b)", treg, |
9226253a | 3979 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 3980 | return; |
3d3c5039 ILT |
3981 | |
3982 | case M_ULH_A: | |
3983 | case M_ULHU_A: | |
3984 | case M_ULW_A: | |
0dd2d296 | 3985 | load_address (&icnt, AT, &offset_expr); |
670a50eb ILT |
3986 | if (mask == M_ULW_A) |
3987 | { | |
8ea7f4e8 ILT |
3988 | if (byte_order == LITTLE_ENDIAN) |
3989 | expr1.X_add_number = 3; | |
3990 | else | |
3991 | expr1.X_add_number = 0; | |
0dd2d296 | 3992 | macro_build ((char *) NULL, &icnt, &expr1, "lwl", "t,o(b)", treg, |
9226253a | 3993 | (int) BFD_RELOC_LO16, AT); |
8ea7f4e8 ILT |
3994 | if (byte_order == LITTLE_ENDIAN) |
3995 | expr1.X_add_number = 0; | |
3996 | else | |
3997 | expr1.X_add_number = 3; | |
0dd2d296 | 3998 | macro_build ((char *) NULL, &icnt, &expr1, "lwr", "t,o(b)", treg, |
9226253a | 3999 | (int) BFD_RELOC_LO16, AT); |
670a50eb ILT |
4000 | } |
4001 | else | |
4002 | { | |
8ea7f4e8 ILT |
4003 | if (byte_order == BIG_ENDIAN) |
4004 | expr1.X_add_number = 0; | |
0dd2d296 | 4005 | macro_build ((char *) NULL, &icnt, &expr1, |
9226253a ILT |
4006 | mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg, |
4007 | (int) BFD_RELOC_LO16, AT); | |
8ea7f4e8 ILT |
4008 | if (byte_order == BIG_ENDIAN) |
4009 | expr1.X_add_number = 1; | |
4010 | else | |
4011 | expr1.X_add_number = 0; | |
0dd2d296 | 4012 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, |
9226253a | 4013 | (int) BFD_RELOC_LO16, AT); |
0dd2d296 ILT |
4014 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, |
4015 | treg, 8); | |
4016 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
4017 | treg, AT); | |
670a50eb ILT |
4018 | } |
4019 | break; | |
3d3c5039 ILT |
4020 | |
4021 | case M_USH: | |
8ea7f4e8 ILT |
4022 | if (offset_expr.X_add_number >= 0x7fff) |
4023 | as_bad ("operand overflow"); | |
4024 | if (byte_order == BIG_ENDIAN) | |
4025 | offset_expr.X_add_number += 1; | |
0dd2d296 | 4026 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg, |
9226253a | 4027 | (int) BFD_RELOC_LO16, breg); |
0dd2d296 | 4028 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, treg, 8); |
8ea7f4e8 ILT |
4029 | if (byte_order == BIG_ENDIAN) |
4030 | offset_expr.X_add_number -= 1; | |
4031 | else | |
4032 | offset_expr.X_add_number += 1; | |
0dd2d296 | 4033 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT, |
9226253a | 4034 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 4035 | break; |
3d3c5039 ILT |
4036 | |
4037 | case M_USW: | |
8ea7f4e8 ILT |
4038 | if (offset_expr.X_add_number >= 0x7ffd) |
4039 | as_bad ("operand overflow"); | |
4040 | if (byte_order == LITTLE_ENDIAN) | |
4041 | offset_expr.X_add_number += 3; | |
0dd2d296 | 4042 | macro_build ((char *) NULL, &icnt, &offset_expr, "swl", "t,o(b)", treg, |
9226253a | 4043 | (int) BFD_RELOC_LO16, breg); |
8ea7f4e8 ILT |
4044 | if (byte_order == LITTLE_ENDIAN) |
4045 | offset_expr.X_add_number -= 3; | |
4046 | else | |
4047 | offset_expr.X_add_number += 3; | |
0dd2d296 | 4048 | macro_build ((char *) NULL, &icnt, &offset_expr, "swr", "t,o(b)", treg, |
9226253a | 4049 | (int) BFD_RELOC_LO16, breg); |
670a50eb | 4050 | return; |
3d3c5039 ILT |
4051 | |
4052 | case M_USH_A: | |
4053 | case M_USW_A: | |
0dd2d296 | 4054 | load_address (&icnt, AT, &offset_expr); |
670a50eb ILT |
4055 | if (mask == M_USW_A) |
4056 | { | |
8ea7f4e8 ILT |
4057 | if (byte_order == LITTLE_ENDIAN) |
4058 | expr1.X_add_number = 3; | |
4059 | else | |
4060 | expr1.X_add_number = 0; | |
0dd2d296 | 4061 | macro_build ((char *) NULL, &icnt, &expr1, "swl", "t,o(b)", treg, |
9226253a | 4062 | (int) BFD_RELOC_LO16, AT); |
8ea7f4e8 ILT |
4063 | if (byte_order == LITTLE_ENDIAN) |
4064 | expr1.X_add_number = 0; | |
4065 | else | |
4066 | expr1.X_add_number = 3; | |
0dd2d296 | 4067 | macro_build ((char *) NULL, &icnt, &expr1, "swr", "t,o(b)", treg, |
9226253a | 4068 | (int) BFD_RELOC_LO16, AT); |
670a50eb ILT |
4069 | } |
4070 | else | |
4071 | { | |
8ea7f4e8 ILT |
4072 | if (byte_order == LITTLE_ENDIAN) |
4073 | expr1.X_add_number = 0; | |
0dd2d296 | 4074 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, |
9226253a | 4075 | (int) BFD_RELOC_LO16, AT); |
0dd2d296 ILT |
4076 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", treg, |
4077 | treg, 8); | |
8ea7f4e8 ILT |
4078 | if (byte_order == LITTLE_ENDIAN) |
4079 | expr1.X_add_number = 1; | |
4080 | else | |
4081 | expr1.X_add_number = 0; | |
0dd2d296 | 4082 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, |
9226253a | 4083 | (int) BFD_RELOC_LO16, AT); |
8ea7f4e8 ILT |
4084 | if (byte_order == LITTLE_ENDIAN) |
4085 | expr1.X_add_number = 0; | |
4086 | else | |
4087 | expr1.X_add_number = 1; | |
0dd2d296 | 4088 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, |
9226253a | 4089 | (int) BFD_RELOC_LO16, AT); |
0dd2d296 ILT |
4090 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, |
4091 | treg, 8); | |
4092 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
4093 | treg, AT); | |
670a50eb ILT |
4094 | } |
4095 | break; | |
3d3c5039 ILT |
4096 | |
4097 | default: | |
670a50eb | 4098 | as_bad ("Macro %s not implemented yet", ip->insn_mo->name); |
8358c818 | 4099 | break; |
3d3c5039 | 4100 | } |
670a50eb ILT |
4101 | if (mips_noat) |
4102 | as_warn ("Macro used $at after \".set noat\""); | |
3d3c5039 ILT |
4103 | } |
4104 | ||
4105 | ||
4106 | /* | |
4107 | This routine assembles an instruction into its binary format. As a side | |
4108 | effect it sets one of the global variables imm_reloc or offset_reloc to the | |
4109 | type of relocation to do if one of the operands is an address expression. | |
4110 | */ | |
4111 | static void | |
4112 | mips_ip (str, ip) | |
4113 | char *str; | |
4114 | struct mips_cl_insn *ip; | |
4115 | { | |
670a50eb ILT |
4116 | char *s; |
4117 | const char *args; | |
4118 | char c; | |
4119 | struct mips_opcode *insn; | |
4120 | char *argsStart; | |
4121 | unsigned int regno; | |
4122 | unsigned int lastregno = 0; | |
4123 | char *s_reset; | |
4124 | ||
4125 | insn_error = NULL; | |
4126 | ||
4127 | for (s = str; islower (*s) || (*s >= '0' && *s <= '3') || *s == '.'; ++s) | |
4128 | continue; | |
4129 | switch (*s) | |
4130 | { | |
3d3c5039 | 4131 | case '\0': |
670a50eb | 4132 | break; |
3d3c5039 ILT |
4133 | |
4134 | case ' ': | |
670a50eb ILT |
4135 | *s++ = '\0'; |
4136 | break; | |
3d3c5039 ILT |
4137 | |
4138 | default: | |
460531da | 4139 | as_fatal ("Unknown opcode: `%s'", str); |
3d3c5039 | 4140 | } |
670a50eb ILT |
4141 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) |
4142 | { | |
4143 | as_warn ("`%s' not in hash table.", str); | |
4144 | insn_error = "ERROR: Unrecognized opcode"; | |
4145 | return; | |
3d3c5039 | 4146 | } |
670a50eb ILT |
4147 | argsStart = s; |
4148 | for (;;) | |
4149 | { | |
8358c818 ILT |
4150 | int insn_isa; |
4151 | ||
670a50eb | 4152 | assert (strcmp (insn->name, str) == 0); |
8358c818 ILT |
4153 | |
4154 | if (insn->pinfo == INSN_MACRO) | |
4155 | insn_isa = insn->match; | |
4156 | else if (insn->pinfo & INSN_ISA2) | |
4157 | insn_isa = 2; | |
4158 | else if (insn->pinfo & INSN_ISA3) | |
4159 | insn_isa = 3; | |
4160 | else | |
4161 | insn_isa = 1; | |
4162 | ||
4163 | if (insn_isa > mips_isa) | |
4164 | { | |
4165 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
4166 | && strcmp (insn->name, insn[1].name) == 0) | |
4167 | { | |
4168 | ++insn; | |
4169 | continue; | |
4170 | } | |
8bbad6fd | 4171 | as_warn ("Instruction not supported on this processor"); |
8358c818 ILT |
4172 | } |
4173 | ||
670a50eb ILT |
4174 | ip->insn_mo = insn; |
4175 | ip->insn_opcode = insn->match; | |
4176 | for (args = insn->args;; ++args) | |
4177 | { | |
4178 | if (*s == ' ') | |
4179 | ++s; | |
4180 | switch (*args) | |
4181 | { | |
4182 | case '\0': /* end of args */ | |
4183 | if (*s == '\0') | |
4184 | return; | |
4185 | break; | |
3d3c5039 ILT |
4186 | |
4187 | case ',': | |
670a50eb ILT |
4188 | if (*s++ == *args) |
4189 | continue; | |
4190 | s--; | |
4191 | switch (*++args) | |
4192 | { | |
3d3c5039 ILT |
4193 | case 'r': |
4194 | case 'v': | |
670a50eb ILT |
4195 | ip->insn_opcode |= lastregno << 21; |
4196 | continue; | |
3d3c5039 ILT |
4197 | |
4198 | case 'w': | |
4199 | case 'W': | |
670a50eb ILT |
4200 | ip->insn_opcode |= lastregno << 16; |
4201 | continue; | |
3d3c5039 ILT |
4202 | |
4203 | case 'V': | |
670a50eb ILT |
4204 | ip->insn_opcode |= lastregno << 11; |
4205 | continue; | |
3d3c5039 | 4206 | } |
670a50eb | 4207 | break; |
3d3c5039 ILT |
4208 | |
4209 | case '(': | |
670a50eb ILT |
4210 | /* handle optional base register. |
4211 | Either the base register is omitted or | |
4212 | we must have a left paren. */ | |
4213 | /* this is dependent on the next operand specifier | |
4214 | is a 'b' for base register */ | |
4215 | assert (args[1] == 'b'); | |
4216 | if (*s == '\0') | |
4217 | return; | |
3d3c5039 | 4218 | |
670a50eb ILT |
4219 | case ')': /* these must match exactly */ |
4220 | if (*s++ == *args) | |
3d3c5039 | 4221 | continue; |
670a50eb ILT |
4222 | break; |
4223 | ||
4224 | case '<': /* must be at least one digit */ | |
4225 | /* | |
4226 | * According to the manual, if the shift amount is greater | |
4227 | * than 31 or less than 0 the the shift amount should be | |
4228 | * mod 32. In reality the mips assembler issues an error. | |
9226253a | 4229 | * We issue a warning and mask out all but the low 5 bits. |
670a50eb ILT |
4230 | */ |
4231 | my_getExpression (&imm_expr, s); | |
4232 | check_absolute_expr (ip, &imm_expr); | |
4233 | if ((unsigned long) imm_expr.X_add_number > 31) | |
4234 | { | |
58d4951d ILT |
4235 | as_warn ("Improper shift amount (%ld)", |
4236 | (long) imm_expr.X_add_number); | |
9226253a | 4237 | imm_expr.X_add_number = imm_expr.X_add_number & 0x1f; |
670a50eb ILT |
4238 | } |
4239 | ip->insn_opcode |= imm_expr.X_add_number << 6; | |
5ac34ac3 | 4240 | imm_expr.X_op = O_absent; |
670a50eb ILT |
4241 | s = expr_end; |
4242 | continue; | |
4243 | ||
56c96faa ILT |
4244 | case '>': /* shift amount minus 32 */ |
4245 | my_getExpression (&imm_expr, s); | |
4246 | check_absolute_expr (ip, &imm_expr); | |
4247 | if ((unsigned long) imm_expr.X_add_number < 32 | |
4248 | || (unsigned long) imm_expr.X_add_number > 63) | |
4249 | break; | |
4250 | ip->insn_opcode |= (imm_expr.X_add_number - 32) << 6; | |
4251 | imm_expr.X_op = O_absent; | |
4252 | s = expr_end; | |
4253 | continue; | |
4254 | ||
9226253a ILT |
4255 | case 'k': /* cache code */ |
4256 | my_getExpression (&imm_expr, s); | |
4257 | check_absolute_expr (ip, &imm_expr); | |
4258 | if ((unsigned long) imm_expr.X_add_number > 31) | |
4259 | { | |
4260 | as_warn ("Invalid cahce opcode (%lu)", | |
4261 | (unsigned long) imm_expr.X_add_number); | |
4262 | imm_expr.X_add_number &= 0x1f; | |
4263 | } | |
4264 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE; | |
4265 | imm_expr.X_op = O_absent; | |
4266 | s = expr_end; | |
4267 | continue; | |
4268 | ||
670a50eb ILT |
4269 | case 'c': /* break code */ |
4270 | my_getExpression (&imm_expr, s); | |
4271 | check_absolute_expr (ip, &imm_expr); | |
4272 | if ((unsigned) imm_expr.X_add_number > 1023) | |
58d4951d ILT |
4273 | as_warn ("Illegal break code (%ld)", |
4274 | (long) imm_expr.X_add_number); | |
670a50eb | 4275 | ip->insn_opcode |= imm_expr.X_add_number << 16; |
5ac34ac3 | 4276 | imm_expr.X_op = O_absent; |
670a50eb ILT |
4277 | s = expr_end; |
4278 | continue; | |
4279 | ||
918692a5 ILT |
4280 | case 'B': /* syscall code */ |
4281 | my_getExpression (&imm_expr, s); | |
4282 | check_absolute_expr (ip, &imm_expr); | |
4283 | if ((unsigned) imm_expr.X_add_number > 0xfffff) | |
58d4951d ILT |
4284 | as_warn ("Illegal syscall code (%ld)", |
4285 | (long) imm_expr.X_add_number); | |
918692a5 | 4286 | ip->insn_opcode |= imm_expr.X_add_number << 6; |
5ac34ac3 | 4287 | imm_expr.X_op = O_absent; |
918692a5 ILT |
4288 | s = expr_end; |
4289 | continue; | |
4290 | ||
0aa07269 ILT |
4291 | case 'C': /* Coprocessor code */ |
4292 | my_getExpression (&imm_expr, s); | |
4293 | check_absolute_expr (ip, &imm_expr); | |
4294 | if ((unsigned long) imm_expr.X_add_number >= (1<<25)) | |
4295 | { | |
58d4951d ILT |
4296 | as_warn ("Coproccesor code > 25 bits (%ld)", |
4297 | (long) imm_expr.X_add_number); | |
0aa07269 ILT |
4298 | imm_expr.X_add_number &= ((1<<25) - 1); |
4299 | } | |
4300 | ip->insn_opcode |= imm_expr.X_add_number; | |
4301 | imm_expr.X_op = O_absent; | |
4302 | s = expr_end; | |
4303 | continue; | |
4304 | ||
670a50eb ILT |
4305 | case 'b': /* base register */ |
4306 | case 'd': /* destination register */ | |
4307 | case 's': /* source register */ | |
4308 | case 't': /* target register */ | |
4309 | case 'r': /* both target and source */ | |
4310 | case 'v': /* both dest and source */ | |
4311 | case 'w': /* both dest and target */ | |
918692a5 ILT |
4312 | case 'E': /* coprocessor target register */ |
4313 | case 'G': /* coprocessor destination register */ | |
8358c818 | 4314 | case 'x': /* ignore register name */ |
ff3a5c18 | 4315 | case 'z': /* must be zero register */ |
670a50eb ILT |
4316 | s_reset = s; |
4317 | if (s[0] == '$') | |
4318 | { | |
4319 | if (isdigit (s[1])) | |
4320 | { | |
4321 | ++s; | |
4322 | regno = 0; | |
4323 | do | |
4324 | { | |
4325 | regno *= 10; | |
4326 | regno += *s - '0'; | |
4327 | ++s; | |
4328 | } | |
4329 | while (isdigit (*s)); | |
0aa07269 ILT |
4330 | if (regno > 31) |
4331 | as_bad ("Invalid register number (%d)", regno); | |
670a50eb | 4332 | } |
0dd2d296 ILT |
4333 | else if (*args == 'E' || *args == 'G') |
4334 | goto notreg; | |
4335 | else | |
670a50eb | 4336 | { |
0aa07269 ILT |
4337 | if (s[1] == 'f' && s[2] == 'p') |
4338 | { | |
4339 | s += 3; | |
9226253a | 4340 | regno = FP; |
0aa07269 ILT |
4341 | } |
4342 | else if (s[1] == 's' && s[2] == 'p') | |
4343 | { | |
4344 | s += 3; | |
9226253a | 4345 | regno = SP; |
0aa07269 ILT |
4346 | } |
4347 | else if (s[1] == 'g' && s[2] == 'p') | |
4348 | { | |
4349 | s += 3; | |
9226253a | 4350 | regno = GP; |
0aa07269 ILT |
4351 | } |
4352 | else if (s[1] == 'a' && s[2] == 't') | |
4353 | { | |
4354 | s += 3; | |
9226253a | 4355 | regno = AT; |
0aa07269 ILT |
4356 | } |
4357 | else | |
4358 | goto notreg; | |
670a50eb | 4359 | } |
13fe1379 ILT |
4360 | if (regno == AT && ! mips_noat) |
4361 | as_warn ("Used $at without \".set noat\""); | |
670a50eb ILT |
4362 | c = *args; |
4363 | if (*s == ' ') | |
4364 | s++; | |
4365 | if (args[1] != *s) | |
4366 | { | |
4367 | if (c == 'r' || c == 'v' || c == 'w') | |
4368 | { | |
4369 | regno = lastregno; | |
4370 | s = s_reset; | |
4371 | args++; | |
4372 | } | |
4373 | } | |
ff3a5c18 ILT |
4374 | /* 'z' only matches $0. */ |
4375 | if (c == 'z' && regno != 0) | |
4376 | break; | |
670a50eb ILT |
4377 | switch (c) |
4378 | { | |
3d3c5039 ILT |
4379 | case 'r': |
4380 | case 's': | |
4381 | case 'v': | |
4382 | case 'b': | |
670a50eb ILT |
4383 | ip->insn_opcode |= regno << 21; |
4384 | break; | |
3d3c5039 | 4385 | case 'd': |
918692a5 | 4386 | case 'G': |
670a50eb ILT |
4387 | ip->insn_opcode |= regno << 11; |
4388 | break; | |
3d3c5039 ILT |
4389 | case 'w': |
4390 | case 't': | |
918692a5 | 4391 | case 'E': |
670a50eb | 4392 | ip->insn_opcode |= regno << 16; |
8358c818 ILT |
4393 | break; |
4394 | case 'x': | |
4395 | /* This case exists because on the r3000 trunc | |
4396 | expands into a macro which requires a gp | |
4397 | register. On the r6000 or r4000 it is | |
4398 | assembled into a single instruction which | |
4399 | ignores the register. Thus the insn version | |
4400 | is MIPS_ISA2 and uses 'x', and the macro | |
4401 | version is MIPS_ISA1 and uses 't'. */ | |
4402 | break; | |
ff3a5c18 ILT |
4403 | case 'z': |
4404 | /* This case is for the div instruction, which | |
4405 | acts differently if the destination argument | |
4406 | is $0. This only matches $0, and is checked | |
4407 | outside the switch. */ | |
4408 | break; | |
3d3c5039 | 4409 | } |
670a50eb ILT |
4410 | lastregno = regno; |
4411 | continue; | |
3d3c5039 ILT |
4412 | } |
4413 | notreg: | |
670a50eb ILT |
4414 | switch (*args++) |
4415 | { | |
3d3c5039 ILT |
4416 | case 'r': |
4417 | case 'v': | |
670a50eb ILT |
4418 | ip->insn_opcode |= lastregno << 21; |
4419 | continue; | |
3d3c5039 | 4420 | case 'w': |
670a50eb ILT |
4421 | ip->insn_opcode |= lastregno << 16; |
4422 | continue; | |
3d3c5039 | 4423 | } |
670a50eb | 4424 | break; |
3d3c5039 | 4425 | |
670a50eb ILT |
4426 | case 'D': /* floating point destination register */ |
4427 | case 'S': /* floating point source register */ | |
4428 | case 'T': /* floating point target register */ | |
3d3c5039 ILT |
4429 | case 'V': |
4430 | case 'W': | |
670a50eb ILT |
4431 | s_reset = s; |
4432 | if (s[0] == '$' && s[1] == 'f' && isdigit (s[2])) | |
4433 | { | |
4434 | s += 2; | |
4435 | regno = 0; | |
4436 | do | |
4437 | { | |
4438 | regno *= 10; | |
4439 | regno += *s - '0'; | |
4440 | ++s; | |
4441 | } | |
4442 | while (isdigit (*s)); | |
4443 | ||
4444 | if (regno > 31) | |
4445 | as_bad ("Invalid float register number (%d)", regno); | |
4446 | ||
9226253a ILT |
4447 | if ((regno & 1) != 0 |
4448 | && mips_isa < 3 | |
4449 | && ! (strcmp (str, "mtc1") == 0 || | |
4450 | strcmp (str, "mfc1") == 0 || | |
4451 | strcmp (str, "lwc1") == 0 || | |
4452 | strcmp (str, "swc1") == 0)) | |
670a50eb ILT |
4453 | as_warn ("Float register should be even, was %d", |
4454 | regno); | |
4455 | ||
4456 | c = *args; | |
4457 | if (*s == ' ') | |
4458 | s++; | |
4459 | if (args[1] != *s) | |
4460 | { | |
4461 | if (c == 'V' || c == 'W') | |
4462 | { | |
4463 | regno = lastregno; | |
4464 | s = s_reset; | |
4465 | args++; | |
3d3c5039 ILT |
4466 | } |
4467 | } | |
670a50eb ILT |
4468 | switch (c) |
4469 | { | |
3d3c5039 | 4470 | case 'D': |
670a50eb ILT |
4471 | ip->insn_opcode |= regno << 6; |
4472 | break; | |
3d3c5039 ILT |
4473 | case 'V': |
4474 | case 'S': | |
670a50eb ILT |
4475 | ip->insn_opcode |= regno << 11; |
4476 | break; | |
3d3c5039 ILT |
4477 | case 'W': |
4478 | case 'T': | |
670a50eb | 4479 | ip->insn_opcode |= regno << 16; |
3d3c5039 | 4480 | } |
670a50eb ILT |
4481 | lastregno = regno; |
4482 | continue; | |
3d3c5039 | 4483 | } |
670a50eb ILT |
4484 | switch (*args++) |
4485 | { | |
3d3c5039 | 4486 | case 'V': |
670a50eb ILT |
4487 | ip->insn_opcode |= lastregno << 11; |
4488 | continue; | |
3d3c5039 | 4489 | case 'W': |
670a50eb ILT |
4490 | ip->insn_opcode |= lastregno << 16; |
4491 | continue; | |
3d3c5039 | 4492 | } |
670a50eb | 4493 | break; |
3d3c5039 ILT |
4494 | |
4495 | case 'I': | |
670a50eb ILT |
4496 | my_getExpression (&imm_expr, s); |
4497 | check_absolute_expr (ip, &imm_expr); | |
4498 | s = expr_end; | |
4499 | continue; | |
3d3c5039 ILT |
4500 | |
4501 | case 'A': | |
670a50eb ILT |
4502 | my_getExpression (&offset_expr, s); |
4503 | imm_reloc = BFD_RELOC_32; | |
4504 | s = expr_end; | |
4505 | continue; | |
3d3c5039 ILT |
4506 | |
4507 | case 'F': | |
19ed8960 ILT |
4508 | case 'L': |
4509 | case 'f': | |
4510 | case 'l': | |
4511 | { | |
4512 | int f64; | |
4513 | char *save_in; | |
4514 | char *err; | |
4515 | unsigned char temp[8]; | |
604633ae ILT |
4516 | int len; |
4517 | unsigned int length; | |
19ed8960 ILT |
4518 | segT seg; |
4519 | subsegT subseg; | |
4520 | char *p; | |
4521 | ||
4522 | /* These only appear as the last operand in an | |
4523 | instruction, and every instruction that accepts | |
4524 | them in any variant accepts them in all variants. | |
4525 | This means we don't have to worry about backing out | |
4526 | any changes if the instruction does not match. | |
4527 | ||
4528 | The difference between them is the size of the | |
4529 | floating point constant and where it goes. For 'F' | |
4530 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
4531 | is 32 bits. Where the constant is placed is based | |
4532 | on how the MIPS assembler does things: | |
4533 | F -- .rdata | |
4534 | L -- .lit8 | |
4535 | f -- immediate value | |
4536 | l -- .lit4 | |
0dd2d296 | 4537 | |
55933a58 ILT |
4538 | The .lit4 and .lit8 sections are only used if |
4539 | permitted by the -G argument. | |
4540 | ||
4541 | When generating embedded PIC code, we use the | |
4542 | .lit8 section but not the .lit4 section (we can do | |
4543 | .lit4 inline easily; we need to put .lit8 | |
4544 | somewhere in the data segment, and using .lit8 | |
4545 | permits the linker to eventually combine identical | |
4546 | .lit8 entries). */ | |
19ed8960 ILT |
4547 | |
4548 | f64 = *args == 'F' || *args == 'L'; | |
4549 | ||
4550 | save_in = input_line_pointer; | |
4551 | input_line_pointer = s; | |
604633ae ILT |
4552 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); |
4553 | length = len; | |
19ed8960 ILT |
4554 | s = input_line_pointer; |
4555 | input_line_pointer = save_in; | |
4556 | if (err != NULL && *err != '\0') | |
4557 | { | |
4558 | as_bad ("Bad floating point constant: %s", err); | |
4559 | memset (temp, '\0', sizeof temp); | |
4560 | length = f64 ? 8 : 4; | |
4561 | } | |
4562 | ||
4563 | assert (length == (f64 ? 8 : 4)); | |
4564 | ||
0dd2d296 | 4565 | if (*args == 'f' |
55933a58 ILT |
4566 | || (*args == 'l' |
4567 | && (mips_pic == EMBEDDED_PIC | |
4568 | #ifdef GPOPT | |
4569 | || g_switch_value < 4 | |
4570 | #endif | |
4571 | ))) | |
19ed8960 ILT |
4572 | { |
4573 | imm_expr.X_op = O_constant; | |
4574 | if (byte_order == LITTLE_ENDIAN) | |
4575 | imm_expr.X_add_number = | |
4576 | (((((((int) temp[3] << 8) | |
4577 | | temp[2]) << 8) | |
4578 | | temp[1]) << 8) | |
4579 | | temp[0]); | |
4580 | else | |
4581 | imm_expr.X_add_number = | |
4582 | (((((((int) temp[0] << 8) | |
4583 | | temp[1]) << 8) | |
4584 | | temp[2]) << 8) | |
4585 | | temp[3]); | |
4586 | } | |
4587 | else | |
4588 | { | |
0dd2d296 ILT |
4589 | const char *newname; |
4590 | segT new_seg; | |
4591 | ||
19ed8960 ILT |
4592 | /* Switch to the right section. */ |
4593 | seg = now_seg; | |
4594 | subseg = now_subseg; | |
4595 | switch (*args) | |
4596 | { | |
0dd2d296 | 4597 | default: /* unused default case avoids warnings. */ |
19ed8960 | 4598 | case 'L': |
55933a58 ILT |
4599 | newname = ".lit8"; |
4600 | #ifdef GPOPT | |
4601 | if (g_switch_value < 8) | |
4602 | newname = RDATA_SECTION_NAME; | |
4603 | #endif | |
0dd2d296 ILT |
4604 | break; |
4605 | case 'F': | |
d2c71068 | 4606 | newname = RDATA_SECTION_NAME; |
19ed8960 ILT |
4607 | break; |
4608 | case 'l': | |
55933a58 ILT |
4609 | #ifdef GPOPT |
4610 | assert (g_switch_value >= 4); | |
4611 | #endif | |
0dd2d296 | 4612 | newname = ".lit4"; |
19ed8960 ILT |
4613 | break; |
4614 | } | |
0dd2d296 | 4615 | new_seg = subseg_new (newname, (subsegT) 0); |
0221ddf7 | 4616 | frag_align (*args == 'l' ? 2 : 3, 0); |
0dd2d296 | 4617 | #ifdef OBJ_ELF |
0221ddf7 ILT |
4618 | record_alignment (new_seg, 4); |
4619 | #else | |
4620 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
0dd2d296 | 4621 | #endif |
19ed8960 ILT |
4622 | if (seg == now_seg) |
4623 | as_bad ("Can't use floating point insn in this section"); | |
4624 | ||
4625 | /* Set the argument to the current address in the | |
6e8dda9c | 4626 | section. */ |
19ed8960 ILT |
4627 | offset_expr.X_op = O_symbol; |
4628 | offset_expr.X_add_symbol = | |
4629 | symbol_new ("L0\001", now_seg, | |
4630 | (valueT) frag_now_fix (), frag_now); | |
4631 | offset_expr.X_add_number = 0; | |
4632 | ||
4633 | /* Put the floating point number into the section. */ | |
604633ae | 4634 | p = frag_more ((int) length); |
19ed8960 ILT |
4635 | memcpy (p, temp, length); |
4636 | ||
4637 | /* Switch back to the original section. */ | |
4638 | subseg_set (seg, subseg); | |
4639 | } | |
4640 | } | |
670a50eb ILT |
4641 | continue; |
4642 | ||
4643 | case 'i': /* 16 bit unsigned immediate */ | |
4644 | case 'j': /* 16 bit signed immediate */ | |
4645 | imm_reloc = BFD_RELOC_LO16; | |
4646 | c = my_getSmallExpression (&imm_expr, s); | |
4647 | if (c) | |
4648 | { | |
4649 | if (c != 'l') | |
4650 | { | |
5ac34ac3 | 4651 | if (imm_expr.X_op == O_constant) |
670a50eb ILT |
4652 | imm_expr.X_add_number = |
4653 | (imm_expr.X_add_number >> 16) & 0xffff; | |
4654 | else if (c == 'h') | |
4655 | imm_reloc = BFD_RELOC_HI16_S; | |
4656 | else | |
4657 | imm_reloc = BFD_RELOC_HI16; | |
3d3c5039 | 4658 | } |
670a50eb ILT |
4659 | } |
4660 | else | |
4661 | check_absolute_expr (ip, &imm_expr); | |
4662 | if (*args == 'i') | |
4663 | { | |
6e8dda9c ILT |
4664 | if (imm_expr.X_add_number < 0 |
4665 | || imm_expr.X_add_number >= 0x10000) | |
99c24539 ILT |
4666 | { |
4667 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
4668 | !strcmp (insn->name, insn[1].name)) | |
4669 | break; | |
4670 | as_bad ("16 bit expression not in range 0..65535"); | |
4671 | } | |
670a50eb ILT |
4672 | } |
4673 | else | |
4674 | { | |
d9aba805 ILT |
4675 | int more; |
4676 | offsetT max; | |
4677 | ||
be22008b ILT |
4678 | /* The upper bound should be 0x8000, but |
4679 | unfortunately the MIPS assembler accepts numbers | |
4680 | from 0x8000 to 0xffff and sign extends them, and | |
d9aba805 ILT |
4681 | we want to be compatible. We only permit this |
4682 | extended range for an instruction which does not | |
4683 | provide any further alternates, since those | |
4684 | alternates may handle other cases. People should | |
4685 | use the numbers they mean, rather than relying on | |
4686 | a mysterious sign extension. */ | |
4687 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
4688 | strcmp (insn->name, insn[1].name) == 0); | |
4689 | if (more) | |
4690 | max = 0x8000; | |
4691 | else | |
4692 | max = 0x10000; | |
6e8dda9c | 4693 | if (imm_expr.X_add_number < -0x8000 || |
d9aba805 | 4694 | imm_expr.X_add_number >= max) |
99c24539 | 4695 | { |
d9aba805 | 4696 | if (more) |
99c24539 ILT |
4697 | break; |
4698 | as_bad ("16 bit expression not in range -32768..32767"); | |
4699 | } | |
3d3c5039 | 4700 | } |
670a50eb ILT |
4701 | s = expr_end; |
4702 | continue; | |
4703 | ||
4704 | case 'o': /* 16 bit offset */ | |
4705 | c = my_getSmallExpression (&offset_expr, s); | |
f3645945 ILT |
4706 | |
4707 | /* If this value won't fit into a 16 bit offset, then go | |
4708 | find a macro that will generate the 32 bit offset | |
4709 | code pattern. As a special hack, we accept the | |
4710 | difference of two local symbols as a constant. This | |
4711 | is required to suppose embedded PIC switches, which | |
4712 | use an instruction which looks like | |
4713 | lw $4,$L12-$LS12($4) | |
4714 | The problem with handling this in a more general | |
4715 | fashion is that the macro function doesn't expect to | |
4716 | see anything which can be handled in a single | |
4717 | constant instruction. */ | |
6f0b87c3 SS |
4718 | if (c == 0 |
4719 | && (offset_expr.X_op != O_constant | |
4720 | || offset_expr.X_add_number >= 0x8000 | |
4721 | || offset_expr.X_add_number < -0x8000) | |
f3645945 ILT |
4722 | && (mips_pic != EMBEDDED_PIC |
4723 | || offset_expr.X_op != O_subtract | |
9da4c5d1 ILT |
4724 | || now_seg != text_section |
4725 | || (S_GET_SEGMENT (offset_expr.X_op_symbol) | |
4726 | != text_section))) | |
670a50eb | 4727 | break; |
3d3c5039 | 4728 | |
670a50eb ILT |
4729 | offset_reloc = BFD_RELOC_LO16; |
4730 | if (c == 'h' || c == 'H') | |
6e8dda9c ILT |
4731 | { |
4732 | assert (offset_expr.X_op == O_constant); | |
4733 | offset_expr.X_add_number = | |
4734 | (offset_expr.X_add_number >> 16) & 0xffff; | |
4735 | } | |
670a50eb ILT |
4736 | s = expr_end; |
4737 | continue; | |
4738 | ||
4739 | case 'p': /* pc relative offset */ | |
4740 | offset_reloc = BFD_RELOC_16_PCREL_S2; | |
4741 | my_getExpression (&offset_expr, s); | |
4742 | s = expr_end; | |
4743 | continue; | |
4744 | ||
4745 | case 'u': /* upper 16 bits */ | |
4746 | c = my_getSmallExpression (&imm_expr, s); | |
36a87ad7 ILT |
4747 | if (imm_expr.X_op == O_constant |
4748 | && (imm_expr.X_add_number < 0 | |
4749 | || imm_expr.X_add_number >= 0x10000)) | |
670a50eb ILT |
4750 | as_bad ("lui expression not in range 0..65535"); |
4751 | imm_reloc = BFD_RELOC_LO16; | |
4752 | if (c) | |
4753 | { | |
4754 | if (c != 'l') | |
4755 | { | |
5ac34ac3 | 4756 | if (imm_expr.X_op == O_constant) |
670a50eb ILT |
4757 | imm_expr.X_add_number = |
4758 | (imm_expr.X_add_number >> 16) & 0xffff; | |
4759 | else if (c == 'h') | |
4760 | imm_reloc = BFD_RELOC_HI16_S; | |
4761 | else | |
4762 | imm_reloc = BFD_RELOC_HI16; | |
3d3c5039 ILT |
4763 | } |
4764 | } | |
670a50eb ILT |
4765 | s = expr_end; |
4766 | continue; | |
3d3c5039 | 4767 | |
670a50eb ILT |
4768 | case 'a': /* 26 bit address */ |
4769 | my_getExpression (&offset_expr, s); | |
4770 | s = expr_end; | |
4771 | offset_reloc = BFD_RELOC_MIPS_JMP; | |
4772 | continue; | |
3d3c5039 ILT |
4773 | |
4774 | default: | |
670a50eb ILT |
4775 | fprintf (stderr, "bad char = '%c'\n", *args); |
4776 | internalError (); | |
3d3c5039 | 4777 | } |
670a50eb | 4778 | break; |
3d3c5039 | 4779 | } |
670a50eb ILT |
4780 | /* Args don't match. */ |
4781 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
4782 | !strcmp (insn->name, insn[1].name)) | |
4783 | { | |
4784 | ++insn; | |
4785 | s = argsStart; | |
4786 | continue; | |
3d3c5039 | 4787 | } |
670a50eb ILT |
4788 | insn_error = "ERROR: Illegal operands"; |
4789 | return; | |
3d3c5039 ILT |
4790 | } |
4791 | } | |
4792 | ||
4793 | #define LP '(' | |
4794 | #define RP ')' | |
4795 | ||
4796 | static int | |
4797 | my_getSmallExpression (ep, str) | |
670a50eb ILT |
4798 | expressionS *ep; |
4799 | char *str; | |
3d3c5039 | 4800 | { |
670a50eb ILT |
4801 | char *sp; |
4802 | int c = 0; | |
4803 | ||
4804 | if (*str == ' ') | |
4805 | str++; | |
4806 | if (*str == LP | |
4807 | || (*str == '%' && | |
4808 | ((str[1] == 'h' && str[2] == 'i') | |
4809 | || (str[1] == 'H' && str[2] == 'I') | |
4810 | || (str[1] == 'l' && str[2] == 'o')) | |
4811 | && str[3] == LP)) | |
4812 | { | |
4813 | if (*str == LP) | |
4814 | c = 0; | |
4815 | else | |
4816 | { | |
4817 | c = str[1]; | |
4818 | str += 3; | |
4819 | } | |
4820 | ||
4821 | /* | |
4822 | * A small expression may be followed by a base register. | |
4823 | * Scan to the end of this operand, and then back over a possible | |
4824 | * base register. Then scan the small expression up to that | |
4825 | * point. (Based on code in sparc.c...) | |
4826 | */ | |
4827 | for (sp = str; *sp && *sp != ','; sp++) | |
4828 | ; | |
4829 | if (sp - 4 >= str && sp[-1] == RP) | |
4830 | { | |
4831 | if (isdigit (sp[-2])) | |
4832 | { | |
4833 | for (sp -= 3; sp >= str && isdigit (*sp); sp--) | |
4834 | ; | |
4835 | if (*sp == '$' && sp > str && sp[-1] == LP) | |
4836 | { | |
4837 | sp--; | |
4838 | goto do_it; | |
3d3c5039 | 4839 | } |
670a50eb ILT |
4840 | } |
4841 | else if (sp - 5 >= str | |
4842 | && sp[-5] == LP | |
4843 | && sp[-4] == '$' | |
4844 | && ((sp[-3] == 'f' && sp[-2] == 'p') | |
4845 | || (sp[-3] == 's' && sp[-2] == 'p') | |
4846 | || (sp[-3] == 'g' && sp[-2] == 'p') | |
4847 | || (sp[-3] == 'a' && sp[-2] == 't'))) | |
4848 | { | |
4849 | sp -= 5; | |
3d3c5039 | 4850 | do_it: |
670a50eb ILT |
4851 | if (sp == str) |
4852 | { | |
4853 | /* no expression means zero offset */ | |
4854 | if (c) | |
4855 | { | |
4856 | /* %xx(reg) is an error */ | |
5ac34ac3 | 4857 | ep->X_op = O_absent; |
670a50eb | 4858 | expr_end = str - 3; |
3d3c5039 | 4859 | } |
670a50eb ILT |
4860 | else |
4861 | { | |
52aa70b5 | 4862 | ep->X_op = O_constant; |
670a50eb ILT |
4863 | expr_end = sp; |
4864 | } | |
4865 | ep->X_add_symbol = NULL; | |
5ac34ac3 | 4866 | ep->X_op_symbol = NULL; |
670a50eb ILT |
4867 | ep->X_add_number = 0; |
4868 | } | |
4869 | else | |
4870 | { | |
4871 | *sp = '\0'; | |
4872 | my_getExpression (ep, str); | |
4873 | *sp = LP; | |
3d3c5039 | 4874 | } |
670a50eb | 4875 | return c; |
3d3c5039 ILT |
4876 | } |
4877 | } | |
4878 | } | |
670a50eb ILT |
4879 | my_getExpression (ep, str); |
4880 | return c; /* => %hi or %lo encountered */ | |
3d3c5039 ILT |
4881 | } |
4882 | ||
4883 | static void | |
4884 | my_getExpression (ep, str) | |
670a50eb ILT |
4885 | expressionS *ep; |
4886 | char *str; | |
3d3c5039 | 4887 | { |
670a50eb | 4888 | char *save_in; |
670a50eb ILT |
4889 | |
4890 | save_in = input_line_pointer; | |
4891 | input_line_pointer = str; | |
5ac34ac3 | 4892 | expression (ep); |
670a50eb ILT |
4893 | expr_end = input_line_pointer; |
4894 | input_line_pointer = save_in; | |
3d3c5039 ILT |
4895 | } |
4896 | ||
becfe05e ILT |
4897 | /* Turn a string in input_line_pointer into a floating point constant |
4898 | of type type, and store the appropriate bytes in *litP. The number | |
4899 | of LITTLENUMS emitted is stored in *sizeP . An error message is | |
4900 | returned, or NULL on OK. */ | |
4901 | ||
3d3c5039 | 4902 | char * |
670a50eb | 4903 | md_atof (type, litP, sizeP) |
becfe05e | 4904 | int type; |
3d3c5039 ILT |
4905 | char *litP; |
4906 | int *sizeP; | |
4907 | { | |
becfe05e ILT |
4908 | int prec; |
4909 | LITTLENUM_TYPE words[4]; | |
4910 | char *t; | |
4911 | int i; | |
4912 | ||
4913 | switch (type) | |
4914 | { | |
4915 | case 'f': | |
4916 | prec = 2; | |
4917 | break; | |
4918 | ||
4919 | case 'd': | |
4920 | prec = 4; | |
4921 | break; | |
4922 | ||
4923 | default: | |
4924 | *sizeP = 0; | |
4925 | return "bad call to md_atof"; | |
4926 | } | |
4927 | ||
4928 | t = atof_ieee (input_line_pointer, type, words); | |
4929 | if (t) | |
4930 | input_line_pointer = t; | |
4931 | ||
4932 | *sizeP = prec * 2; | |
4933 | ||
4934 | if (byte_order == LITTLE_ENDIAN) | |
4935 | { | |
4936 | for (i = prec - 1; i >= 0; i--) | |
4937 | { | |
4938 | md_number_to_chars (litP, (valueT) words[i], 2); | |
4939 | litP += 2; | |
4940 | } | |
4941 | } | |
4942 | else | |
4943 | { | |
4944 | for (i = 0; i < prec; i++) | |
4945 | { | |
4946 | md_number_to_chars (litP, (valueT) words[i], 2); | |
4947 | litP += 2; | |
4948 | } | |
4949 | } | |
4950 | ||
670a50eb | 4951 | return NULL; |
3d3c5039 ILT |
4952 | } |
4953 | ||
4954 | void | |
4955 | md_number_to_chars (buf, val, n) | |
4956 | char *buf; | |
918692a5 | 4957 | valueT val; |
3d3c5039 ILT |
4958 | int n; |
4959 | { | |
670a50eb ILT |
4960 | switch (byte_order) |
4961 | { | |
3d3c5039 | 4962 | case LITTLE_ENDIAN: |
13fe1379 ILT |
4963 | number_to_chars_littleendian (buf, val, n); |
4964 | break; | |
3d3c5039 ILT |
4965 | |
4966 | case BIG_ENDIAN: | |
13fe1379 ILT |
4967 | number_to_chars_bigendian (buf, val, n); |
4968 | break; | |
3d3c5039 ILT |
4969 | |
4970 | default: | |
670a50eb | 4971 | internalError (); |
3d3c5039 ILT |
4972 | } |
4973 | } | |
f3d817d8 DM |
4974 | \f |
4975 | #ifdef GPOPT | |
e8d4d475 | 4976 | CONST char *md_shortopts = "O::g::G:"; |
f3d817d8 | 4977 | #else |
e8d4d475 | 4978 | CONST char *md_shortopts = "O::g::"; |
f3d817d8 DM |
4979 | #endif |
4980 | struct option md_longopts[] = { | |
4981 | #define OPTION_MIPS1 (OPTION_MD_BASE + 1) | |
4982 | {"mips0", no_argument, NULL, OPTION_MIPS1}, | |
4983 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
4984 | #define OPTION_MIPS2 (OPTION_MD_BASE + 2) | |
4985 | {"mips2", no_argument, NULL, OPTION_MIPS2}, | |
4986 | #define OPTION_MIPS3 (OPTION_MD_BASE + 3) | |
4987 | {"mips3", no_argument, NULL, OPTION_MIPS3}, | |
4988 | #define OPTION_MCPU (OPTION_MD_BASE + 4) | |
4989 | {"mcpu", required_argument, NULL, OPTION_MCPU}, | |
4990 | #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 5) | |
4991 | {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC}, | |
4992 | #define OPTION_TRAP (OPTION_MD_BASE + 8) | |
4993 | {"trap", no_argument, NULL, OPTION_TRAP}, | |
4994 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
4995 | #define OPTION_BREAK (OPTION_MD_BASE + 9) | |
4996 | {"break", no_argument, NULL, OPTION_BREAK}, | |
4997 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
e8d4d475 ILT |
4998 | #define OPTION_EB (OPTION_MD_BASE + 10) |
4999 | {"EB", no_argument, NULL, OPTION_EB}, | |
5000 | #define OPTION_EL (OPTION_MD_BASE + 11) | |
5001 | {"EL", no_argument, NULL, OPTION_EL}, | |
f3d817d8 DM |
5002 | |
5003 | #ifdef OBJ_ELF | |
5004 | #define OPTION_CALL_SHARED (OPTION_MD_BASE + 6) | |
5005 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, | |
5006 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
5007 | #define OPTION_NON_SHARED (OPTION_MD_BASE + 7) | |
5008 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, | |
5009 | #endif | |
5010 | ||
5011 | {NULL, no_argument, NULL, 0} | |
5012 | }; | |
5013 | size_t md_longopts_size = sizeof(md_longopts); | |
3d3c5039 ILT |
5014 | |
5015 | int | |
f3d817d8 DM |
5016 | md_parse_option (c, arg) |
5017 | int c; | |
5018 | char *arg; | |
3d3c5039 | 5019 | { |
f3d817d8 | 5020 | switch (c) |
670a50eb | 5021 | { |
f3d817d8 DM |
5022 | case OPTION_TRAP: |
5023 | mips_trap = 1; | |
5024 | break; | |
670a50eb | 5025 | |
f3d817d8 DM |
5026 | case OPTION_BREAK: |
5027 | mips_trap = 0; | |
5028 | break; | |
5029 | ||
e8d4d475 ILT |
5030 | case OPTION_EB: |
5031 | byte_order = BIG_ENDIAN; | |
04cb3372 | 5032 | #ifdef OBJ_AOUT |
e8d4d475 | 5033 | mips_target_format = "a.out-mips-big"; |
04cb3372 ILT |
5034 | #endif |
5035 | #ifdef OBJ_ECOFF | |
e8d4d475 | 5036 | mips_target_format = "ecoff-bigmips"; |
04cb3372 ILT |
5037 | #endif |
5038 | #ifdef OBJ_ELF | |
e8d4d475 | 5039 | mips_target_format = "elf32-bigmips"; |
04cb3372 | 5040 | #endif |
e8d4d475 | 5041 | break; |
04cb3372 | 5042 | |
e8d4d475 ILT |
5043 | case OPTION_EL: |
5044 | byte_order = LITTLE_ENDIAN; | |
5045 | #ifdef OBJ_AOUT | |
5046 | mips_target_format = "a.out-mips-little"; | |
5047 | #endif | |
5048 | #ifdef OBJ_ECOFF | |
5049 | mips_target_format = "ecoff-littlemips"; | |
5050 | #endif | |
5051 | #ifdef OBJ_ELF | |
5052 | mips_target_format = "elf32-littlemips"; | |
5053 | #endif | |
f3d817d8 | 5054 | break; |
670a50eb | 5055 | |
f3d817d8 DM |
5056 | case 'O': |
5057 | if (arg && arg[1] == '0') | |
0aa07269 ILT |
5058 | mips_optimize = 1; |
5059 | else | |
5060 | mips_optimize = 2; | |
f3d817d8 | 5061 | break; |
0aa07269 | 5062 | |
f3d817d8 DM |
5063 | case 'g': |
5064 | if (arg == NULL || arg[1] == '2') | |
0aa07269 | 5065 | mips_optimize = 0; |
f3d817d8 | 5066 | break; |
4e95866e | 5067 | |
f3d817d8 DM |
5068 | case OPTION_MIPS1: |
5069 | mips_isa = 1; | |
4bb0cc41 ILT |
5070 | if (mips_cpu == -1) |
5071 | mips_cpu = 3000; | |
f3d817d8 | 5072 | break; |
8358c818 | 5073 | |
f3d817d8 DM |
5074 | case OPTION_MIPS2: |
5075 | mips_isa = 2; | |
4bb0cc41 ILT |
5076 | if (mips_cpu == -1) |
5077 | mips_cpu = 6000; | |
f3d817d8 | 5078 | break; |
8358c818 | 5079 | |
f3d817d8 DM |
5080 | case OPTION_MIPS3: |
5081 | mips_isa = 3; | |
4bb0cc41 ILT |
5082 | if (mips_cpu == -1) |
5083 | mips_cpu = 4000; | |
f3d817d8 | 5084 | break; |
8358c818 | 5085 | |
f3d817d8 DM |
5086 | case OPTION_MCPU: |
5087 | { | |
5088 | char *p; | |
5089 | ||
5090 | /* Identify the processor type */ | |
5091 | p = arg; | |
5092 | if (strcmp (p, "default") == 0 | |
5093 | || strcmp (p, "DEFAULT") == 0) | |
4bb0cc41 | 5094 | mips_cpu = -1; |
f3d817d8 DM |
5095 | else |
5096 | { | |
5097 | if (*p == 'r' || *p == 'R') | |
5098 | p++; | |
8358c818 | 5099 | |
4bb0cc41 | 5100 | mips_cpu = -1; |
f3d817d8 DM |
5101 | switch (*p) |
5102 | { | |
5103 | case '2': | |
5104 | if (strcmp (p, "2000") == 0 | |
5105 | || strcmp (p, "2k") == 0 | |
5106 | || strcmp (p, "2K") == 0) | |
4bb0cc41 | 5107 | mips_cpu = 2000; |
f3d817d8 | 5108 | break; |
8358c818 | 5109 | |
f3d817d8 DM |
5110 | case '3': |
5111 | if (strcmp (p, "3000") == 0 | |
5112 | || strcmp (p, "3k") == 0 | |
5113 | || strcmp (p, "3K") == 0) | |
4bb0cc41 | 5114 | mips_cpu = 3000; |
f3d817d8 | 5115 | break; |
8358c818 | 5116 | |
f3d817d8 DM |
5117 | case '4': |
5118 | if (strcmp (p, "4000") == 0 | |
5119 | || strcmp (p, "4k") == 0 | |
8c63448a | 5120 | || strcmp (p, "4K") == 0) |
4bb0cc41 | 5121 | mips_cpu = 4000; |
8c63448a | 5122 | else if (strcmp (p, "4400") == 0) |
4bb0cc41 | 5123 | mips_cpu = 4400; |
8c63448a | 5124 | else if (strcmp (p, "4600") == 0) |
4bb0cc41 | 5125 | mips_cpu = 4600; |
f3d817d8 | 5126 | break; |
8358c818 | 5127 | |
f3d817d8 DM |
5128 | case '6': |
5129 | if (strcmp (p, "6000") == 0 | |
5130 | || strcmp (p, "6k") == 0 | |
5131 | || strcmp (p, "6K") == 0) | |
4bb0cc41 | 5132 | mips_cpu = 6000; |
f3d817d8 | 5133 | break; |
55933a58 ILT |
5134 | |
5135 | case 'o': | |
5136 | if (strcmp (p, "orion") == 0) | |
4bb0cc41 | 5137 | mips_cpu = 4600; |
55933a58 | 5138 | break; |
f3d817d8 | 5139 | } |
8358c818 | 5140 | |
4bb0cc41 | 5141 | if (mips_cpu == -1) |
f3d817d8 DM |
5142 | { |
5143 | as_bad ("invalid architecture -mcpu=%s", arg); | |
5144 | return 0; | |
5145 | } | |
5146 | } | |
5147 | } | |
5148 | break; | |
8358c818 | 5149 | |
f3d817d8 | 5150 | case OPTION_MEMBEDDED_PIC: |
d9aba805 | 5151 | mips_pic = EMBEDDED_PIC; |
5b63f465 ILT |
5152 | #ifdef GPOPT |
5153 | if (g_switch_seen) | |
f3d817d8 DM |
5154 | { |
5155 | as_bad ("-G may not be used with embedded PIC code"); | |
5156 | return 0; | |
5157 | } | |
5b63f465 ILT |
5158 | g_switch_value = 0x7fffffff; |
5159 | #endif | |
f3d817d8 | 5160 | break; |
d9aba805 ILT |
5161 | |
5162 | #ifdef OBJ_ELF | |
5163 | /* When generating ELF code, we permit -KPIC and -call_shared to | |
5164 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
5165 | intended to be compatible with Irix 5. */ | |
f3d817d8 | 5166 | case OPTION_CALL_SHARED: |
d9aba805 ILT |
5167 | mips_pic = SVR4_PIC; |
5168 | if (g_switch_seen && g_switch_value != 0) | |
f3d817d8 DM |
5169 | { |
5170 | as_bad ("-G may not be used with SVR4 PIC code"); | |
5171 | return 0; | |
5172 | } | |
d9aba805 | 5173 | g_switch_value = 0; |
f3d817d8 DM |
5174 | break; |
5175 | ||
5176 | case OPTION_NON_SHARED: | |
d9aba805 | 5177 | mips_pic = NO_PIC; |
f3d817d8 | 5178 | break; |
d9aba805 | 5179 | #endif /* OBJ_ELF */ |
8358c818 | 5180 | |
88225433 | 5181 | #ifdef GPOPT |
f3d817d8 | 5182 | case 'G': |
5b63f465 | 5183 | if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC) |
670a50eb | 5184 | { |
f3d817d8 DM |
5185 | as_bad ("-G may not be used with SVR4 or embedded PIC code"); |
5186 | return 0; | |
670a50eb ILT |
5187 | } |
5188 | else | |
f3d817d8 | 5189 | g_switch_value = atoi (arg); |
42562568 | 5190 | g_switch_seen = 1; |
f3d817d8 | 5191 | break; |
670a50eb | 5192 | #endif |
4e95866e | 5193 | |
f3d817d8 DM |
5194 | default: |
5195 | return 0; | |
8ea7f4e8 ILT |
5196 | } |
5197 | ||
f3d817d8 | 5198 | return 1; |
8ea7f4e8 ILT |
5199 | } |
5200 | ||
f3d817d8 DM |
5201 | void |
5202 | md_show_usage (stream) | |
5203 | FILE *stream; | |
5204 | { | |
5205 | fprintf(stream, "\ | |
5206 | MIPS options:\n\ | |
5207 | -membedded-pic generate embedded position independent code\n\ | |
f3d817d8 DM |
5208 | -EB generate big endian output\n\ |
5209 | -EL generate little endian output\n\ | |
5210 | -g, -g2 do not remove uneeded NOPs or swap branches\n\ | |
5211 | -G NUM allow referencing objects up to NUM bytes\n\ | |
6f0b87c3 SS |
5212 | implicitly with the gp register [default 8]\n"); |
5213 | fprintf(stream, "\ | |
f3d817d8 DM |
5214 | -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\ |
5215 | -mips2, -mcpu=r6000 generate code for r6000\n\ | |
5216 | -mips3, -mcpu=r4000 generate code for r4000\n\ | |
5217 | -O0 remove unneeded NOPs, do not swap branches\n\ | |
5218 | -O remove unneeded NOPs and swap branches\n\ | |
5219 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ | |
5220 | --break, --no-trap break exception on div by 0 and mult overflow\n"); | |
5221 | #ifdef OBJ_ELF | |
5222 | fprintf(stream, "\ | |
5223 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
5224 | -non_shared do not generate position independent code\n"); | |
5225 | #endif | |
5226 | } | |
5227 | \f | |
3d3c5039 ILT |
5228 | long |
5229 | md_pcrel_from (fixP) | |
5230 | fixS *fixP; | |
5231 | { | |
5b63f465 ILT |
5232 | #ifndef OBJ_AOUT |
5233 | if (fixP->fx_addsy != (symbolS *) NULL | |
5234 | && ! S_IS_DEFINED (fixP->fx_addsy)) | |
5235 | { | |
5236 | /* This makes a branch to an undefined symbol be a branch to the | |
5237 | current location. */ | |
5238 | return 4; | |
5239 | } | |
5240 | #endif | |
5241 | ||
670a50eb ILT |
5242 | /* return the address of the delay slot */ |
5243 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
3d3c5039 ILT |
5244 | } |
5245 | ||
abdad6bc ILT |
5246 | /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a |
5247 | reloc for a cons. We could use the definition there, except that | |
5248 | we want to handle 64 bit relocs specially. */ | |
5249 | ||
5250 | void | |
5251 | cons_fix_new_mips (frag, where, nbytes, exp) | |
5252 | fragS *frag; | |
5253 | int where; | |
5254 | unsigned int nbytes; | |
5255 | expressionS *exp; | |
5256 | { | |
5257 | /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a | |
5258 | 4 byte reloc. | |
5259 | FIXME: There is no way to select anything but 32 bit mode right | |
5260 | now. */ | |
5261 | if (nbytes == 8) | |
5262 | { | |
5263 | if (byte_order == BIG_ENDIAN) | |
5264 | where += 4; | |
5265 | nbytes = 4; | |
5266 | } | |
5267 | ||
5268 | if (nbytes != 2 && nbytes != 4) | |
5269 | as_bad ("Unsupported reloc size %d", nbytes); | |
5270 | ||
5271 | fix_new_exp (frag_now, where, (int) nbytes, exp, 0, | |
5272 | nbytes == 2 ? BFD_RELOC_16 : BFD_RELOC_32); | |
5273 | } | |
5274 | ||
1c803e52 ILT |
5275 | /* When generating embedded PIC code we need to use a special |
5276 | relocation to represent the difference of two symbols in the .text | |
5277 | section (switch tables use a difference of this sort). See | |
5278 | include/coff/mips.h for details. This macro checks whether this | |
5279 | fixup requires the special reloc. */ | |
5280 | #define SWITCH_TABLE(fixp) \ | |
5281 | ((fixp)->fx_r_type == BFD_RELOC_32 \ | |
5282 | && (fixp)->fx_addsy != NULL \ | |
5283 | && (fixp)->fx_subsy != NULL \ | |
5284 | && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \ | |
5285 | && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section) | |
5286 | ||
5b63f465 | 5287 | /* When generating embedded PIC code we must keep all PC relative |
1c803e52 ILT |
5288 | relocations, in case the linker has to relax a call. We also need |
5289 | to keep relocations for switch table entries. */ | |
5b63f465 ILT |
5290 | |
5291 | /*ARGSUSED*/ | |
5292 | int | |
5293 | mips_force_relocation (fixp) | |
5294 | fixS *fixp; | |
5295 | { | |
1c803e52 | 5296 | return (mips_pic == EMBEDDED_PIC |
ecd4ca1c ILT |
5297 | && (fixp->fx_pcrel |
5298 | || SWITCH_TABLE (fixp) | |
5299 | || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S | |
5300 | || fixp->fx_r_type == BFD_RELOC_PCREL_LO16)); | |
5b63f465 ILT |
5301 | } |
5302 | ||
5303 | /* Apply a fixup to the object file. */ | |
5304 | ||
3d3c5039 ILT |
5305 | int |
5306 | md_apply_fix (fixP, valueP) | |
5307 | fixS *fixP; | |
918692a5 | 5308 | valueT *valueP; |
3d3c5039 | 5309 | { |
670a50eb ILT |
5310 | unsigned char *buf; |
5311 | long insn, value; | |
3d3c5039 | 5312 | |
670a50eb | 5313 | assert (fixP->fx_size == 4); |
3d3c5039 | 5314 | |
670a50eb ILT |
5315 | value = *valueP; |
5316 | fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc */ | |
3d3c5039 | 5317 | |
5b63f465 ILT |
5318 | if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel) |
5319 | fixP->fx_done = 1; | |
5320 | ||
670a50eb ILT |
5321 | switch (fixP->fx_r_type) |
5322 | { | |
3d3c5039 ILT |
5323 | case BFD_RELOC_MIPS_JMP: |
5324 | case BFD_RELOC_HI16: | |
5325 | case BFD_RELOC_HI16_S: | |
670a50eb | 5326 | case BFD_RELOC_MIPS_GPREL: |
9226253a ILT |
5327 | case BFD_RELOC_MIPS_LITERAL: |
5328 | case BFD_RELOC_MIPS_CALL16: | |
0dd2d296 ILT |
5329 | case BFD_RELOC_MIPS_GOT16: |
5330 | case BFD_RELOC_MIPS_GPREL32: | |
ecd4ca1c | 5331 | if (fixP->fx_pcrel) |
7b777690 ILT |
5332 | as_bad_where (fixP->fx_file, fixP->fx_line, |
5333 | "Invalid PC relative reloc"); | |
670a50eb | 5334 | /* Nothing needed to do. The value comes from the reloc entry */ |
5b63f465 | 5335 | break; |
3d3c5039 | 5336 | |
ecd4ca1c ILT |
5337 | case BFD_RELOC_PCREL_HI16_S: |
5338 | /* The addend for this is tricky if it is internal, so we just | |
5339 | do everything here rather than in bfd_perform_relocation. */ | |
5340 | if ((fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0) | |
5341 | { | |
5342 | /* For an external symbol adjust by the address to make it | |
5343 | pcrel_offset. We use the address of the RELLO reloc | |
5344 | which follows this one. */ | |
5345 | value += (fixP->fx_next->fx_frag->fr_address | |
5346 | + fixP->fx_next->fx_where); | |
5347 | } | |
5348 | if (value & 0x8000) | |
5349 | value += 0x10000; | |
5350 | value >>= 16; | |
0221ddf7 | 5351 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
ecd4ca1c ILT |
5352 | if (byte_order == BIG_ENDIAN) |
5353 | buf += 2; | |
5354 | md_number_to_chars (buf, value, 2); | |
5355 | break; | |
5356 | ||
5357 | case BFD_RELOC_PCREL_LO16: | |
5358 | /* The addend for this is tricky if it is internal, so we just | |
5359 | do everything here rather than in bfd_perform_relocation. */ | |
5360 | if ((fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0) | |
5361 | value += fixP->fx_frag->fr_address + fixP->fx_where; | |
0221ddf7 | 5362 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
ecd4ca1c ILT |
5363 | if (byte_order == BIG_ENDIAN) |
5364 | buf += 2; | |
5365 | md_number_to_chars (buf, value, 2); | |
5366 | break; | |
5367 | ||
f3645945 ILT |
5368 | case BFD_RELOC_32: |
5369 | /* If we are deleting this reloc entry, we must fill in the | |
5370 | value now. This can happen if we have a .word which is not | |
1c803e52 ILT |
5371 | resolved when it appears but is later defined. We also need |
5372 | to fill in the value if this is an embedded PIC switch table | |
5373 | entry. */ | |
5374 | if (fixP->fx_done | |
5375 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
f3645945 ILT |
5376 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, |
5377 | value, 4); | |
5378 | break; | |
5379 | ||
5380 | case BFD_RELOC_LO16: | |
5381 | /* When handling an embedded PIC switch statement, we can wind | |
5382 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
5383 | if (fixP->fx_done) | |
5384 | { | |
5385 | if (value < -0x8000 || value > 0x7fff) | |
5386 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
5387 | "relocation overflow"); | |
0221ddf7 | 5388 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
f3645945 ILT |
5389 | if (byte_order == BIG_ENDIAN) |
5390 | buf += 2; | |
5391 | md_number_to_chars (buf, value, 2); | |
5392 | } | |
5393 | break; | |
5394 | ||
3d3c5039 | 5395 | case BFD_RELOC_16_PCREL_S2: |
670a50eb ILT |
5396 | /* |
5397 | * We need to save the bits in the instruction since fixup_segment() | |
5398 | * might be deleting the relocation entry (i.e., a branch within | |
5399 | * the current segment). | |
5400 | */ | |
5401 | if (value & 0x3) | |
7b777690 ILT |
5402 | as_warn_where (fixP->fx_file, fixP->fx_line, |
5403 | "Branch to odd address (%lx)", value); | |
670a50eb | 5404 | value >>= 2; |
670a50eb ILT |
5405 | |
5406 | /* update old instruction data */ | |
5407 | buf = (unsigned char *) (fixP->fx_where + fixP->fx_frag->fr_literal); | |
5408 | switch (byte_order) | |
5409 | { | |
3d3c5039 | 5410 | case LITTLE_ENDIAN: |
670a50eb ILT |
5411 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; |
5412 | break; | |
3d3c5039 ILT |
5413 | |
5414 | case BIG_ENDIAN: | |
670a50eb ILT |
5415 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; |
5416 | break; | |
3d3c5039 ILT |
5417 | |
5418 | default: | |
670a50eb ILT |
5419 | internalError (); |
5420 | return 0; | |
3d3c5039 | 5421 | } |
9da4c5d1 ILT |
5422 | |
5423 | if (value >= -0x8000 && value < 0x8000) | |
5424 | insn |= value & 0xffff; | |
5425 | else | |
5426 | { | |
5427 | /* The branch offset is too large. If this is an | |
5428 | unconditional branch, and we are not generating PIC code, | |
5429 | we can convert it to an absolute jump instruction. */ | |
5430 | if (mips_pic == NO_PIC | |
5431 | && fixP->fx_done | |
5432 | && fixP->fx_frag->fr_address >= text_section->vma | |
5433 | && (fixP->fx_frag->fr_address | |
5434 | < text_section->vma + text_section->_raw_size) | |
5435 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
5436 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
5437 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
5438 | { | |
5439 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ | |
5440 | insn = 0x0c000000; /* jal */ | |
5441 | else | |
5442 | insn = 0x08000000; /* j */ | |
5443 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
5444 | fixP->fx_done = 0; | |
5445 | fixP->fx_addsy = section_symbol (text_section); | |
5446 | fixP->fx_addnumber = (value << 2) + md_pcrel_from (fixP); | |
5447 | } | |
5448 | else | |
5449 | { | |
5450 | /* FIXME. It would be possible in principle to handle | |
5451 | conditional branches which overflow. They could be | |
5452 | transformed into a branch around a jump. This would | |
5453 | require setting up variant frags for each different | |
5454 | branch type. The native MIPS assembler attempts to | |
5455 | handle these cases, but it appears to do it | |
5456 | incorrectly. */ | |
5457 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
5458 | "Relocation overflow"); | |
5459 | } | |
5460 | } | |
5461 | ||
604633ae | 5462 | md_number_to_chars ((char *) buf, (valueT) insn, 4); |
670a50eb | 5463 | break; |
3d3c5039 ILT |
5464 | |
5465 | default: | |
670a50eb | 5466 | internalError (); |
3d3c5039 | 5467 | } |
5b63f465 | 5468 | |
670a50eb | 5469 | return 1; |
3d3c5039 ILT |
5470 | } |
5471 | ||
5472 | #if 0 | |
5473 | void | |
670a50eb ILT |
5474 | printInsn (oc) |
5475 | unsigned long oc; | |
3d3c5039 | 5476 | { |
670a50eb ILT |
5477 | const struct mips_opcode *p; |
5478 | int treg, sreg, dreg, shamt; | |
5479 | short imm; | |
5480 | const char *args; | |
5481 | int i; | |
3d3c5039 | 5482 | |
670a50eb ILT |
5483 | for (i = 0; i < NUMOPCODES; ++i) |
5484 | { | |
5485 | p = &mips_opcodes[i]; | |
5486 | if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO)) | |
5487 | { | |
5488 | printf ("%08lx %s\t", oc, p->name); | |
5489 | treg = (oc >> 16) & 0x1f; | |
5490 | sreg = (oc >> 21) & 0x1f; | |
5491 | dreg = (oc >> 11) & 0x1f; | |
5492 | shamt = (oc >> 6) & 0x1f; | |
5493 | imm = oc; | |
5494 | for (args = p->args;; ++args) | |
5495 | { | |
5496 | switch (*args) | |
5497 | { | |
3d3c5039 | 5498 | case '\0': |
670a50eb ILT |
5499 | printf ("\n"); |
5500 | break; | |
3d3c5039 ILT |
5501 | |
5502 | case ',': | |
5503 | case '(': | |
5504 | case ')': | |
670a50eb ILT |
5505 | printf ("%c", *args); |
5506 | continue; | |
3d3c5039 ILT |
5507 | |
5508 | case 'r': | |
670a50eb ILT |
5509 | assert (treg == sreg); |
5510 | printf ("$%d,$%d", treg, sreg); | |
5511 | continue; | |
3d3c5039 ILT |
5512 | |
5513 | case 'd': | |
918692a5 | 5514 | case 'G': |
670a50eb ILT |
5515 | printf ("$%d", dreg); |
5516 | continue; | |
3d3c5039 ILT |
5517 | |
5518 | case 't': | |
918692a5 | 5519 | case 'E': |
670a50eb ILT |
5520 | printf ("$%d", treg); |
5521 | continue; | |
3d3c5039 | 5522 | |
9226253a ILT |
5523 | case 'k': |
5524 | printf ("0x%x", treg); | |
5525 | continue; | |
5526 | ||
3d3c5039 ILT |
5527 | case 'b': |
5528 | case 's': | |
670a50eb ILT |
5529 | printf ("$%d", sreg); |
5530 | continue; | |
3d3c5039 ILT |
5531 | |
5532 | case 'a': | |
670a50eb ILT |
5533 | printf ("0x%08lx", oc & 0x1ffffff); |
5534 | continue; | |
3d3c5039 ILT |
5535 | |
5536 | case 'i': | |
5537 | case 'j': | |
5538 | case 'o': | |
5539 | case 'u': | |
670a50eb ILT |
5540 | printf ("%d", imm); |
5541 | continue; | |
3d3c5039 ILT |
5542 | |
5543 | case '<': | |
56c96faa | 5544 | case '>': |
670a50eb ILT |
5545 | printf ("$%d", shamt); |
5546 | continue; | |
3d3c5039 ILT |
5547 | |
5548 | default: | |
670a50eb | 5549 | internalError (); |
3d3c5039 | 5550 | } |
670a50eb | 5551 | break; |
3d3c5039 | 5552 | } |
670a50eb | 5553 | return; |
3d3c5039 ILT |
5554 | } |
5555 | } | |
670a50eb | 5556 | printf ("%08lx UNDEFINED\n", oc); |
3d3c5039 ILT |
5557 | } |
5558 | #endif | |
5559 | ||
5560 | static symbolS * | |
5561 | get_symbol () | |
5562 | { | |
670a50eb ILT |
5563 | int c; |
5564 | char *name; | |
5565 | symbolS *p; | |
5566 | ||
5567 | name = input_line_pointer; | |
5568 | c = get_symbol_end (); | |
5569 | p = (symbolS *) symbol_find_or_make (name); | |
5570 | *input_line_pointer = c; | |
5571 | return p; | |
3d3c5039 ILT |
5572 | } |
5573 | ||
becfe05e ILT |
5574 | /* Align the current frag to a given power of two. The MIPS assembler |
5575 | also automatically adjusts any preceding label. */ | |
5576 | ||
5577 | static void | |
23dc1ae3 | 5578 | mips_align (to, fill, label) |
becfe05e ILT |
5579 | int to; |
5580 | int fill; | |
23dc1ae3 | 5581 | symbolS *label; |
becfe05e ILT |
5582 | { |
5583 | mips_emit_delays (); | |
5584 | frag_align (to, fill); | |
5585 | record_alignment (now_seg, to); | |
23dc1ae3 | 5586 | if (label != NULL) |
becfe05e | 5587 | { |
23dc1ae3 ILT |
5588 | assert (S_GET_SEGMENT (label) == now_seg); |
5589 | label->sy_frag = frag_now; | |
5590 | S_SET_VALUE (label, (valueT) frag_now_fix ()); | |
becfe05e ILT |
5591 | } |
5592 | } | |
5593 | ||
5594 | /* Align to a given power of two. .align 0 turns off the automatic | |
5595 | alignment used by the data creating pseudo-ops. */ | |
5596 | ||
3d3c5039 ILT |
5597 | static void |
5598 | s_align (x) | |
5599 | int x; | |
5600 | { | |
670a50eb ILT |
5601 | register int temp; |
5602 | register long temp_fill; | |
5603 | long max_alignment = 15; | |
3d3c5039 | 5604 | |
670a50eb | 5605 | /* |
3d3c5039 ILT |
5606 | |
5607 | o Note that the assembler pulls down any immediately preceeding label | |
5608 | to the aligned address. | |
5609 | o It's not documented but auto alignment is reinstated by | |
5610 | a .align pseudo instruction. | |
5611 | o Note also that after auto alignment is turned off the mips assembler | |
5612 | issues an error on attempt to assemble an improperly aligned data item. | |
5613 | We don't. | |
5614 | ||
5615 | */ | |
5616 | ||
670a50eb ILT |
5617 | temp = get_absolute_expression (); |
5618 | if (temp > max_alignment) | |
5619 | as_bad ("Alignment too large: %d. assumed.", temp = max_alignment); | |
5620 | else if (temp < 0) | |
5621 | { | |
5622 | as_warn ("Alignment negative: 0 assumed."); | |
5623 | temp = 0; | |
5624 | } | |
5625 | if (*input_line_pointer == ',') | |
5626 | { | |
5627 | input_line_pointer++; | |
5628 | temp_fill = get_absolute_expression (); | |
5629 | } | |
5630 | else | |
5631 | temp_fill = 0; | |
5632 | if (temp) | |
5633 | { | |
5634 | auto_align = 1; | |
23dc1ae3 | 5635 | mips_align (temp, (int) temp_fill, insn_label); |
3d3c5039 | 5636 | } |
670a50eb ILT |
5637 | else |
5638 | { | |
5639 | auto_align = 0; | |
3d3c5039 ILT |
5640 | } |
5641 | ||
670a50eb | 5642 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
5643 | } |
5644 | ||
becfe05e ILT |
5645 | /* Handle .ascii and .asciiz. This just calls stringer and forgets |
5646 | that there was a previous instruction. */ | |
5647 | ||
5648 | static void | |
5649 | s_stringer (append_zero) | |
5650 | int append_zero; | |
5651 | { | |
5652 | mips_emit_delays (); | |
1849d646 | 5653 | insn_label = NULL; |
becfe05e ILT |
5654 | stringer (append_zero); |
5655 | } | |
5656 | ||
3d3c5039 ILT |
5657 | static void |
5658 | s_change_sec (sec) | |
5659 | int sec; | |
5660 | { | |
88225433 ILT |
5661 | #ifdef GPOPT |
5662 | segT seg; | |
5663 | #endif | |
becfe05e | 5664 | |
5b63f465 ILT |
5665 | /* When generating embedded PIC code, we only use the .text, .lit8, |
5666 | .sdata and .sbss sections. We change the .data and .rdata | |
5667 | pseudo-ops to use .sdata. */ | |
5668 | if (mips_pic == EMBEDDED_PIC | |
5669 | && (sec == 'd' || sec == 'r')) | |
5670 | sec = 's'; | |
5671 | ||
becfe05e | 5672 | mips_emit_delays (); |
670a50eb ILT |
5673 | switch (sec) |
5674 | { | |
3d3c5039 | 5675 | case 't': |
604633ae | 5676 | s_text (0); |
670a50eb | 5677 | break; |
3d3c5039 | 5678 | case 'd': |
604633ae | 5679 | s_data (0); |
670a50eb | 5680 | break; |
3d3c5039 | 5681 | case 'b': |
670a50eb | 5682 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); |
670a50eb ILT |
5683 | demand_empty_rest_of_line (); |
5684 | break; | |
88225433 ILT |
5685 | |
5686 | case 'r': | |
da15a93e | 5687 | #ifdef GPOPT |
d2c71068 ILT |
5688 | seg = subseg_new (RDATA_SECTION_NAME, |
5689 | (subsegT) get_absolute_expression ()); | |
88225433 | 5690 | #ifdef OBJ_ELF |
88225433 ILT |
5691 | bfd_set_section_flags (stdoutput, seg, |
5692 | (SEC_ALLOC | |
5693 | | SEC_LOAD | |
5694 | | SEC_READONLY | |
5695 | | SEC_RELOC | |
5696 | | SEC_DATA)); | |
0dd2d296 | 5697 | bfd_set_section_alignment (stdoutput, seg, 4); |
d2c71068 | 5698 | #endif |
88225433 | 5699 | demand_empty_rest_of_line (); |
da15a93e ILT |
5700 | #else /* ! defined (GPOPT) */ |
5701 | as_bad ("No read only data section in this object file format"); | |
5702 | demand_empty_rest_of_line (); | |
5703 | return; | |
5704 | #endif /* ! defined (GPOPT) */ | |
88225433 | 5705 | break; |
88225433 ILT |
5706 | |
5707 | case 's': | |
5708 | #ifdef GPOPT | |
5709 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); | |
5710 | #ifdef OBJ_ELF | |
5711 | bfd_set_section_flags (stdoutput, seg, | |
5712 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
0dd2d296 | 5713 | bfd_set_section_alignment (stdoutput, seg, 4); |
88225433 ILT |
5714 | #endif |
5715 | demand_empty_rest_of_line (); | |
5716 | break; | |
5717 | #else /* ! defined (GPOPT) */ | |
670a50eb | 5718 | as_bad ("Global pointers not supported; recompile -G 0"); |
becfe05e | 5719 | demand_empty_rest_of_line (); |
670a50eb | 5720 | return; |
88225433 | 5721 | #endif /* ! defined (GPOPT) */ |
3d3c5039 | 5722 | } |
88225433 | 5723 | |
670a50eb | 5724 | auto_align = 1; |
3d3c5039 ILT |
5725 | } |
5726 | ||
9da4c5d1 ILT |
5727 | #ifdef OBJ_ELF |
5728 | ||
5729 | /* Handle the ELF .section pseudo-op. This is a wrapper around | |
5730 | obj_elf_section. */ | |
5731 | ||
5732 | static void | |
5733 | s_elf_section (x) | |
5734 | int x; | |
5735 | { | |
5736 | mips_emit_delays (); | |
5737 | obj_elf_section (x); | |
5738 | auto_align = 1; | |
5739 | } | |
5740 | ||
5741 | #endif /* OBJ_ELF */ | |
5742 | ||
3d3c5039 ILT |
5743 | static void |
5744 | s_cons (log_size) | |
5745 | int log_size; | |
5746 | { | |
23dc1ae3 ILT |
5747 | symbolS *label; |
5748 | ||
5749 | label = insn_label; | |
becfe05e | 5750 | mips_emit_delays (); |
670a50eb | 5751 | if (log_size > 0 && auto_align) |
23dc1ae3 | 5752 | mips_align (log_size, 0, label); |
1849d646 | 5753 | insn_label = NULL; |
670a50eb | 5754 | cons (1 << log_size); |
3d3c5039 ILT |
5755 | } |
5756 | ||
5757 | static void | |
5758 | s_err (x) | |
5759 | int x; | |
5760 | { | |
670a50eb | 5761 | as_fatal ("Encountered `.err', aborting assembly"); |
3d3c5039 ILT |
5762 | } |
5763 | ||
5764 | static void | |
5765 | s_extern (x) | |
5766 | int x; | |
5767 | { | |
604633ae | 5768 | valueT size; |
670a50eb ILT |
5769 | symbolS *symbolP; |
5770 | ||
5771 | symbolP = get_symbol (); | |
5772 | if (*input_line_pointer == ',') | |
5773 | input_line_pointer++; | |
5ac34ac3 | 5774 | size = get_absolute_expression (); |
670a50eb ILT |
5775 | S_SET_EXTERNAL (symbolP); |
5776 | ||
0dd2d296 | 5777 | #ifdef ECOFF_DEBUGGING |
8ea7f4e8 | 5778 | symbolP->ecoff_extern_size = size; |
670a50eb | 5779 | #endif |
3d3c5039 ILT |
5780 | } |
5781 | ||
5782 | static void | |
becfe05e ILT |
5783 | s_float_cons (type) |
5784 | int type; | |
3d3c5039 | 5785 | { |
23dc1ae3 ILT |
5786 | symbolS *label; |
5787 | ||
5788 | label = insn_label; | |
5789 | ||
becfe05e | 5790 | mips_emit_delays (); |
670a50eb ILT |
5791 | |
5792 | if (auto_align) | |
becfe05e | 5793 | if (type == 'd') |
23dc1ae3 | 5794 | mips_align (3, 0, label); |
670a50eb | 5795 | else |
23dc1ae3 | 5796 | mips_align (2, 0, label); |
670a50eb | 5797 | |
1849d646 ILT |
5798 | insn_label = NULL; |
5799 | ||
becfe05e | 5800 | float_cons (type); |
3d3c5039 ILT |
5801 | } |
5802 | ||
c1444ec4 ILT |
5803 | /* Handle .globl. We need to override it because on Irix 5 you are |
5804 | permitted to say | |
5805 | .globl foo .text | |
5806 | where foo is an undefined symbol, to mean that foo should be | |
5807 | considered to be the address of a function. */ | |
5808 | ||
5809 | static void | |
5810 | s_mips_globl (x) | |
5811 | int x; | |
5812 | { | |
5813 | char *name; | |
5814 | int c; | |
5815 | symbolS *symbolP; | |
5816 | ||
5817 | name = input_line_pointer; | |
5818 | c = get_symbol_end (); | |
5819 | symbolP = symbol_find_or_make (name); | |
5820 | *input_line_pointer = c; | |
5821 | SKIP_WHITESPACE (); | |
5822 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
5823 | { | |
5824 | char *secname; | |
5825 | asection *sec; | |
5826 | ||
5827 | secname = input_line_pointer; | |
5828 | c = get_symbol_end (); | |
5829 | sec = bfd_get_section_by_name (stdoutput, secname); | |
5830 | if (sec == NULL) | |
5831 | as_bad ("%s: no such section", secname); | |
5832 | *input_line_pointer = c; | |
5833 | ||
5834 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
5835 | symbolP->bsym->flags |= BSF_FUNCTION; | |
5836 | } | |
5837 | ||
5838 | S_SET_EXTERNAL (symbolP); | |
5839 | demand_empty_rest_of_line (); | |
5840 | } | |
5841 | ||
3d3c5039 ILT |
5842 | static void |
5843 | s_option (x) | |
5844 | int x; | |
5845 | { | |
dd3f1f76 ILT |
5846 | char *opt; |
5847 | char c; | |
5848 | ||
5849 | opt = input_line_pointer; | |
5850 | c = get_symbol_end (); | |
5851 | ||
dd3f1f76 | 5852 | if (*opt == 'O') |
9226253a ILT |
5853 | { |
5854 | /* FIXME: What does this mean? */ | |
5855 | } | |
dd3f1f76 | 5856 | else if (strncmp (opt, "pic", 3) == 0) |
9226253a | 5857 | { |
d9aba805 | 5858 | int i; |
42562568 | 5859 | |
d9aba805 ILT |
5860 | i = atoi (opt + 3); |
5861 | if (i == 0) | |
5862 | mips_pic = NO_PIC; | |
5863 | else if (i == 2) | |
5864 | mips_pic = SVR4_PIC; | |
5865 | else | |
5866 | as_bad (".option pic%d not supported", i); | |
5867 | ||
0221ddf7 | 5868 | #ifdef GPOPT |
d9aba805 | 5869 | if (mips_pic == SVR4_PIC) |
42562568 ILT |
5870 | { |
5871 | if (g_switch_seen && g_switch_value != 0) | |
d9aba805 | 5872 | as_warn ("-G may not be used with SVR4 PIC code"); |
42562568 ILT |
5873 | g_switch_value = 0; |
5874 | bfd_set_gp_size (stdoutput, 0); | |
5875 | } | |
0221ddf7 | 5876 | #endif |
9226253a | 5877 | } |
dd3f1f76 ILT |
5878 | else |
5879 | as_warn ("Unrecognized option \"%s\"", opt); | |
5880 | ||
5881 | *input_line_pointer = c; | |
670a50eb | 5882 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
5883 | } |
5884 | ||
5885 | static void | |
5886 | s_mipsset (x) | |
5887 | int x; | |
5888 | { | |
670a50eb ILT |
5889 | char *name = input_line_pointer, ch; |
5890 | ||
5891 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
5892 | input_line_pointer++; | |
5893 | ch = *input_line_pointer; | |
5894 | *input_line_pointer = '\0'; | |
5895 | ||
5896 | if (strcmp (name, "reorder") == 0) | |
5897 | { | |
4e95866e ILT |
5898 | if (mips_noreorder) |
5899 | { | |
5900 | prev_insn_unreordered = 1; | |
5901 | prev_prev_insn_unreordered = 1; | |
5902 | } | |
670a50eb ILT |
5903 | mips_noreorder = 0; |
5904 | } | |
5905 | else if (strcmp (name, "noreorder") == 0) | |
5906 | { | |
becfe05e | 5907 | mips_emit_delays (); |
670a50eb | 5908 | mips_noreorder = 1; |
0dd2d296 | 5909 | mips_any_noreorder = 1; |
670a50eb ILT |
5910 | } |
5911 | else if (strcmp (name, "at") == 0) | |
5912 | { | |
5913 | mips_noat = 0; | |
5914 | } | |
5915 | else if (strcmp (name, "noat") == 0) | |
5916 | { | |
5917 | mips_noat = 1; | |
3d3c5039 | 5918 | } |
670a50eb ILT |
5919 | else if (strcmp (name, "macro") == 0) |
5920 | { | |
5921 | mips_warn_about_macros = 0; | |
5922 | } | |
5923 | else if (strcmp (name, "nomacro") == 0) | |
5924 | { | |
5925 | if (mips_noreorder == 0) | |
5926 | as_bad ("`noreorder' must be set before `nomacro'"); | |
5927 | mips_warn_about_macros = 1; | |
5928 | } | |
5929 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
5930 | { | |
5931 | mips_nomove = 0; | |
5932 | } | |
5933 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
5934 | { | |
5935 | mips_nomove = 1; | |
5936 | } | |
5937 | else if (strcmp (name, "bopt") == 0) | |
5938 | { | |
5939 | mips_nobopt = 0; | |
5940 | } | |
5941 | else if (strcmp (name, "nobopt") == 0) | |
5942 | { | |
5943 | mips_nobopt = 1; | |
5944 | } | |
1051c97f ILT |
5945 | else if (strncmp (name, "mips", 4) == 0) |
5946 | { | |
5947 | int isa; | |
5948 | ||
5949 | /* Permit the user to change the ISA on the fly. Needless to | |
5950 | say, misuse can cause serious problems. */ | |
5951 | isa = atoi (name + 4); | |
5952 | if (isa == 0) | |
5953 | mips_isa = file_mips_isa; | |
5954 | else if (isa < 1 || isa > 3) | |
5955 | as_bad ("unknown ISA level"); | |
5956 | else | |
5957 | mips_isa = isa; | |
5958 | } | |
670a50eb ILT |
5959 | else |
5960 | { | |
5961 | as_warn ("Tried to set unrecognized symbol: %s\n", name); | |
5962 | } | |
5963 | *input_line_pointer = ch; | |
5964 | demand_empty_rest_of_line (); | |
3d3c5039 ILT |
5965 | } |
5966 | ||
becfe05e ILT |
5967 | /* The same as the usual .space directive, except that we have to |
5968 | forget about any previous instruction. */ | |
5969 | ||
5970 | static void | |
5971 | s_mips_space (param) | |
5972 | int param; | |
5973 | { | |
5974 | mips_emit_delays (); | |
1849d646 | 5975 | insn_label = NULL; |
becfe05e ILT |
5976 | s_space (param); |
5977 | } | |
5978 | ||
9226253a ILT |
5979 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to |
5980 | .option pic2. It means to generate SVR4 PIC calls. */ | |
5981 | ||
5982 | static void | |
5983 | s_abicalls (ignore) | |
5984 | int ignore; | |
5985 | { | |
d9aba805 | 5986 | mips_pic = SVR4_PIC; |
0221ddf7 | 5987 | #ifdef GPOPT |
d9aba805 ILT |
5988 | if (g_switch_seen && g_switch_value != 0) |
5989 | as_warn ("-G may not be used with SVR4 PIC code"); | |
5990 | g_switch_value = 0; | |
0221ddf7 | 5991 | #endif |
d9aba805 | 5992 | bfd_set_gp_size (stdoutput, 0); |
9226253a ILT |
5993 | demand_empty_rest_of_line (); |
5994 | } | |
5995 | ||
5996 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
5997 | PIC code. It sets the $gp register for the function based on the | |
5998 | function address, which is in the register named in the argument. | |
5999 | This uses a relocation against _gp_disp, which is handled specially | |
6000 | by the linker. The result is: | |
6001 | lui $gp,%hi(_gp_disp) | |
6002 | addiu $gp,$gp,%lo(_gp_disp) | |
6003 | addu $gp,$gp,.cpload argument | |
0dd2d296 | 6004 | The .cpload argument is normally $25 == $t9. */ |
9226253a ILT |
6005 | |
6006 | static void | |
6007 | s_cpload (ignore) | |
6008 | int ignore; | |
6009 | { | |
6010 | expressionS ex; | |
6011 | int icnt = 0; | |
6012 | ||
d9aba805 ILT |
6013 | /* If we are not generating SVR4 PIC code, .cpload is ignored. */ |
6014 | if (mips_pic != SVR4_PIC) | |
0dd2d296 ILT |
6015 | { |
6016 | s_ignore (0); | |
6017 | return; | |
6018 | } | |
6019 | ||
6020 | /* .cpload should be a in .set noreorder section. */ | |
6021 | if (mips_noreorder == 0) | |
6022 | as_warn (".cpload not in noreorder section"); | |
6023 | ||
9226253a ILT |
6024 | ex.X_op = O_symbol; |
6025 | ex.X_add_symbol = symbol_find_or_make ("_gp_disp"); | |
6026 | ex.X_op_symbol = NULL; | |
6027 | ex.X_add_number = 0; | |
6028 | ||
0dd2d296 ILT |
6029 | macro_build_lui ((char *) NULL, &icnt, &ex, GP); |
6030 | macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j", GP, GP, | |
9226253a ILT |
6031 | (int) BFD_RELOC_LO16); |
6032 | ||
0dd2d296 ILT |
6033 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t", |
6034 | GP, GP, tc_get_register (0)); | |
9226253a ILT |
6035 | |
6036 | demand_empty_rest_of_line (); | |
6037 | } | |
6038 | ||
6039 | /* Handle the .cprestore pseudo-op. This stores $gp into a given | |
6040 | offset from $sp. The offset is remembered, and after making a PIC | |
6041 | call $gp is restored from that location. */ | |
6042 | ||
6043 | static void | |
6044 | s_cprestore (ignore) | |
6045 | int ignore; | |
6046 | { | |
6047 | expressionS ex; | |
6048 | int icnt = 0; | |
6049 | ||
d9aba805 ILT |
6050 | /* If we are not generating SVR4 PIC code, .cprestore is ignored. */ |
6051 | if (mips_pic != SVR4_PIC) | |
0dd2d296 ILT |
6052 | { |
6053 | s_ignore (0); | |
6054 | return; | |
6055 | } | |
6056 | ||
9226253a ILT |
6057 | mips_cprestore_offset = get_absolute_expression (); |
6058 | ||
6059 | ex.X_op = O_constant; | |
6060 | ex.X_add_symbol = NULL; | |
6061 | ex.X_op_symbol = NULL; | |
6062 | ex.X_add_number = mips_cprestore_offset; | |
6063 | ||
0dd2d296 | 6064 | macro_build ((char *) NULL, &icnt, &ex, |
9226253a ILT |
6065 | mips_isa < 3 ? "sw" : "sd", |
6066 | "t,o(b)", GP, (int) BFD_RELOC_LO16, SP); | |
6067 | ||
6068 | demand_empty_rest_of_line (); | |
6069 | } | |
6070 | ||
0dd2d296 ILT |
6071 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
6072 | code. It generates a 32 bit GP relative reloc. */ | |
6073 | ||
6074 | static void | |
6075 | s_gpword (ignore) | |
6076 | int ignore; | |
6077 | { | |
23dc1ae3 | 6078 | symbolS *label; |
0dd2d296 ILT |
6079 | expressionS ex; |
6080 | char *p; | |
6081 | ||
6082 | /* When not generating PIC code, this is treated as .word. */ | |
7dfa376e | 6083 | if (mips_pic != SVR4_PIC) |
0dd2d296 ILT |
6084 | { |
6085 | s_cons (2); | |
6086 | return; | |
6087 | } | |
6088 | ||
23dc1ae3 | 6089 | label = insn_label; |
0dd2d296 ILT |
6090 | mips_emit_delays (); |
6091 | if (auto_align) | |
23dc1ae3 | 6092 | mips_align (2, 0, label); |
0dd2d296 ILT |
6093 | insn_label = NULL; |
6094 | ||
6095 | expression (&ex); | |
6096 | ||
6097 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
6098 | { | |
6099 | as_bad ("Unsupported use of .gpword"); | |
6100 | ignore_rest_of_line (); | |
6101 | } | |
6102 | ||
6103 | p = frag_more (4); | |
6104 | md_number_to_chars (p, (valueT) 0, 4); | |
6105 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, 0, | |
6106 | BFD_RELOC_MIPS_GPREL32); | |
6107 | ||
6108 | demand_empty_rest_of_line (); | |
6109 | } | |
6110 | ||
6111 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch | |
6112 | tables in SVR4 PIC code. */ | |
6113 | ||
6114 | static void | |
6115 | s_cpadd (ignore) | |
6116 | int ignore; | |
6117 | { | |
6118 | int icnt = 0; | |
6119 | int reg; | |
6120 | ||
6121 | /* This is ignored when not generating SVR4 PIC code. */ | |
7dfa376e | 6122 | if (mips_pic != SVR4_PIC) |
0dd2d296 ILT |
6123 | { |
6124 | s_ignore (0); | |
6125 | return; | |
6126 | } | |
6127 | ||
6128 | /* Add $gp to the register named as an argument. */ | |
6129 | reg = tc_get_register (0); | |
6130 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6131 | mips_isa < 3 ? "addu" : "daddu", | |
6132 | "d,v,t", reg, reg, GP); | |
6133 | ||
6134 | demand_empty_rest_of_line (); | |
6135 | } | |
6136 | ||
9226253a | 6137 | /* Parse a register string into a number. Called from the ECOFF code |
0dd2d296 ILT |
6138 | to parse .frame. The argument is non-zero if this is the frame |
6139 | register, so that we can record it in mips_frame_reg. */ | |
9226253a | 6140 | |
3d3c5039 | 6141 | int |
0dd2d296 ILT |
6142 | tc_get_register (frame) |
6143 | int frame; | |
3d3c5039 ILT |
6144 | { |
6145 | int reg; | |
6146 | ||
6147 | SKIP_WHITESPACE (); | |
6148 | if (*input_line_pointer++ != '$') | |
6149 | { | |
6150 | as_warn ("expected `$'"); | |
0dd2d296 | 6151 | reg = 0; |
3d3c5039 | 6152 | } |
0dd2d296 | 6153 | else if (isdigit ((unsigned char) *input_line_pointer)) |
3d3c5039 ILT |
6154 | { |
6155 | reg = get_absolute_expression (); | |
6156 | if (reg < 0 || reg >= 32) | |
6157 | { | |
6158 | as_warn ("Bad register number"); | |
6159 | reg = 0; | |
6160 | } | |
6161 | } | |
6162 | else | |
6163 | { | |
6164 | if (strncmp (input_line_pointer, "fp", 2) == 0) | |
9226253a | 6165 | reg = FP; |
3d3c5039 | 6166 | else if (strncmp (input_line_pointer, "sp", 2) == 0) |
9226253a | 6167 | reg = SP; |
3d3c5039 | 6168 | else if (strncmp (input_line_pointer, "gp", 2) == 0) |
9226253a | 6169 | reg = GP; |
3d3c5039 | 6170 | else if (strncmp (input_line_pointer, "at", 2) == 0) |
9226253a | 6171 | reg = AT; |
3d3c5039 ILT |
6172 | else |
6173 | { | |
6174 | as_warn ("Unrecognized register name"); | |
0dd2d296 | 6175 | reg = 0; |
3d3c5039 ILT |
6176 | } |
6177 | input_line_pointer += 2; | |
6178 | } | |
0dd2d296 ILT |
6179 | if (frame) |
6180 | mips_frame_reg = reg != 0 ? reg : SP; | |
3d3c5039 ILT |
6181 | return reg; |
6182 | } | |
6183 | ||
0dd2d296 ILT |
6184 | valueT |
6185 | md_section_align (seg, addr) | |
6186 | asection *seg; | |
6187 | valueT addr; | |
6188 | { | |
6189 | int align = bfd_get_section_alignment (stdoutput, seg); | |
6190 | ||
6191 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
6192 | } | |
6193 | ||
6194 | /* Estimate the size of a frag before relaxing. We are not really | |
6195 | relaxing here, and the final size is encoded in the subtype | |
6196 | information. */ | |
6197 | ||
6198 | /*ARGSUSED*/ | |
6199 | int | |
6200 | md_estimate_size_before_relax (fragp, segtype) | |
6201 | fragS *fragp; | |
6202 | asection *segtype; | |
6203 | { | |
6204 | int change; | |
6205 | ||
d9aba805 | 6206 | if (mips_pic == NO_PIC) |
0dd2d296 ILT |
6207 | { |
6208 | #ifdef GPOPT | |
6209 | const char *symname; | |
6210 | ||
6211 | /* Find out whether this symbol can be referenced off the GP | |
6212 | register. It can be if it is smaller than the -G size or if | |
6213 | it is in the .sdata or .sbss section. Certain symbols can | |
6214 | not be referenced off the GP, although it appears as though | |
6215 | they can. */ | |
6216 | symname = S_GET_NAME (fragp->fr_symbol); | |
6217 | if (symname != (const char *) NULL | |
6218 | && (strcmp (symname, "eprol") == 0 | |
6219 | || strcmp (symname, "etext") == 0 | |
6220 | || strcmp (symname, "_gp") == 0 | |
6221 | || strcmp (symname, "edata") == 0 | |
6222 | || strcmp (symname, "_fbss") == 0 | |
6223 | || strcmp (symname, "_fdata") == 0 | |
6224 | || strcmp (symname, "_ftext") == 0 | |
6225 | || strcmp (symname, "end") == 0 | |
6226 | || strcmp (symname, "_gp_disp") == 0)) | |
6227 | change = 1; | |
6228 | else if (! S_IS_DEFINED (fragp->fr_symbol) | |
8ea7f4e8 ILT |
6229 | && ((fragp->fr_symbol->ecoff_extern_size != 0 |
6230 | && fragp->fr_symbol->ecoff_extern_size <= g_switch_value) | |
6231 | || (S_GET_VALUE (fragp->fr_symbol) != 0 | |
6232 | && S_GET_VALUE (fragp->fr_symbol) <= g_switch_value))) | |
0dd2d296 ILT |
6233 | change = 0; |
6234 | else | |
6235 | { | |
6236 | const char *segname; | |
6237 | ||
6238 | segname = segment_name (S_GET_SEGMENT (fragp->fr_symbol)); | |
6239 | assert (strcmp (segname, ".lit8") != 0 | |
6240 | && strcmp (segname, ".lit4") != 0); | |
6241 | change = (strcmp (segname, ".sdata") != 0 | |
6242 | && strcmp (segname, ".sbss") != 0); | |
6243 | } | |
6244 | #else /* ! defined (GPOPT) */ | |
6245 | /* We are not optimizing for the GP register. */ | |
6246 | change = 1; | |
6247 | #endif /* ! defined (GPOPT) */ | |
6248 | } | |
d9aba805 | 6249 | else if (mips_pic == SVR4_PIC) |
0dd2d296 ILT |
6250 | { |
6251 | asection *symsec = fragp->fr_symbol->bsym->section; | |
6252 | ||
6253 | /* This must duplicate the test in adjust_reloc_syms. */ | |
6254 | change = (symsec != &bfd_und_section | |
6255 | && symsec != &bfd_abs_section | |
6256 | && ! bfd_is_com_section (symsec)); | |
6257 | } | |
d9aba805 ILT |
6258 | else |
6259 | abort (); | |
0dd2d296 ILT |
6260 | |
6261 | if (change) | |
6262 | { | |
6263 | /* Record the offset to the first reloc in the fr_opcode field. | |
6264 | This lets md_convert_frag and tc_gen_reloc know that the code | |
6265 | must be expanded. */ | |
6266 | fragp->fr_opcode = (fragp->fr_literal | |
6267 | + fragp->fr_fix | |
6268 | - RELAX_OLD (fragp->fr_subtype) | |
6269 | + RELAX_RELOC1 (fragp->fr_subtype)); | |
6270 | /* FIXME: This really needs as_warn_where. */ | |
6271 | if (RELAX_WARN (fragp->fr_subtype)) | |
6272 | as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\""); | |
6273 | } | |
6274 | ||
6275 | if (! change) | |
6276 | return 0; | |
6277 | else | |
6278 | return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype); | |
6279 | } | |
6280 | ||
6281 | /* Translate internal representation of relocation info to BFD target | |
6282 | format. */ | |
6283 | ||
6284 | arelent ** | |
3d3c5039 ILT |
6285 | tc_gen_reloc (section, fixp) |
6286 | asection *section; | |
6287 | fixS *fixp; | |
6288 | { | |
0dd2d296 | 6289 | static arelent *retval[4]; |
3d3c5039 ILT |
6290 | arelent *reloc; |
6291 | ||
0dd2d296 ILT |
6292 | reloc = retval[0] = (arelent *) xmalloc (sizeof (arelent)); |
6293 | retval[1] = NULL; | |
3d3c5039 ILT |
6294 | |
6295 | reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym; | |
6296 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
1c803e52 ILT |
6297 | |
6298 | if (mips_pic == EMBEDDED_PIC | |
6299 | && SWITCH_TABLE (fixp)) | |
6300 | { | |
6301 | /* For a switch table entry we use a special reloc. The addend | |
6302 | is actually the difference between the reloc address and the | |
6303 | subtrahend. */ | |
6304 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
6305 | #ifndef OBJ_ECOFF | |
ecd4ca1c | 6306 | as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc"); |
1c803e52 ILT |
6307 | #endif |
6308 | fixp->fx_r_type = BFD_RELOC_GPREL32; | |
6309 | } | |
ecd4ca1c ILT |
6310 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16) |
6311 | { | |
6312 | /* We use a special addend for an internal RELLO reloc. */ | |
6313 | if (fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) | |
6314 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
6315 | else | |
6316 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
6317 | } | |
6318 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S) | |
6319 | { | |
6320 | assert (fixp->fx_next != NULL | |
6321 | && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16); | |
6322 | /* We use a special addend for an internal RELHI reloc. The | |
6323 | reloc is relative to the RELLO; adjust the addend | |
6324 | accordingly. */ | |
6325 | if (fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) | |
6326 | reloc->addend = (fixp->fx_next->fx_frag->fr_address | |
6327 | + fixp->fx_next->fx_where | |
6328 | - S_GET_VALUE (fixp->fx_subsy)); | |
6329 | else | |
6330 | reloc->addend = (fixp->fx_addnumber | |
6331 | + fixp->fx_next->fx_frag->fr_address | |
6332 | + fixp->fx_next->fx_where); | |
6333 | } | |
1c803e52 | 6334 | else if (fixp->fx_pcrel == 0) |
3d3c5039 ILT |
6335 | reloc->addend = fixp->fx_addnumber; |
6336 | else | |
5b63f465 | 6337 | { |
d9aba805 | 6338 | #ifndef OBJ_AOUT |
5b63f465 ILT |
6339 | /* A gruesome hack which is a result of the gruesome gas reloc |
6340 | handling. */ | |
6341 | reloc->addend = reloc->address; | |
3d3c5039 | 6342 | #else |
5b63f465 | 6343 | reloc->addend = -reloc->address; |
3d3c5039 | 6344 | #endif |
5b63f465 | 6345 | } |
0dd2d296 ILT |
6346 | |
6347 | /* If this is a variant frag, we may need to adjust the existing | |
6348 | reloc and generate a new one. */ | |
6349 | if (fixp->fx_frag->fr_opcode != NULL | |
6350 | && (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL | |
6351 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
6352 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16)) | |
6353 | { | |
6354 | arelent *reloc2; | |
6355 | ||
6356 | /* If this is not the last reloc in this frag, then we have two | |
6357 | GPREL relocs, both of which are being replaced. Let the | |
6358 | second one handle all of them. */ | |
6359 | if (fixp->fx_next != NULL | |
6360 | && fixp->fx_frag == fixp->fx_next->fx_frag) | |
6361 | { | |
6362 | assert (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL | |
6363 | && fixp->fx_next->fx_r_type == BFD_RELOC_MIPS_GPREL); | |
6364 | retval[0] = NULL; | |
6365 | return retval; | |
6366 | } | |
6367 | ||
6368 | fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal; | |
6369 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
6370 | reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent)); | |
6371 | retval[2] = NULL; | |
6372 | reloc2->sym_ptr_ptr = &fixp->fx_addsy->bsym; | |
6373 | reloc2->address = (reloc->address | |
6374 | + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype) | |
6375 | - RELAX_RELOC1 (fixp->fx_frag->fr_subtype))); | |
6376 | reloc2->addend = fixp->fx_addnumber; | |
6377 | reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16); | |
6378 | assert (reloc2->howto != NULL); | |
6379 | ||
6380 | if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype)) | |
6381 | { | |
6382 | arelent *reloc3; | |
6383 | ||
6384 | reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent)); | |
6385 | retval[3] = NULL; | |
6386 | *reloc3 = *reloc2; | |
6387 | reloc3->address += 4; | |
6388 | } | |
6389 | ||
d9aba805 | 6390 | if (mips_pic == NO_PIC) |
0dd2d296 ILT |
6391 | { |
6392 | assert (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL); | |
6393 | fixp->fx_r_type = BFD_RELOC_HI16_S; | |
6394 | } | |
d9aba805 | 6395 | else if (mips_pic == SVR4_PIC) |
0dd2d296 ILT |
6396 | { |
6397 | if (fixp->fx_r_type != BFD_RELOC_MIPS_GOT16) | |
6398 | { | |
6399 | assert (fixp->fx_r_type == BFD_RELOC_MIPS_CALL16); | |
6400 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT16; | |
6401 | } | |
6402 | } | |
d9aba805 ILT |
6403 | else |
6404 | abort (); | |
0dd2d296 ILT |
6405 | } |
6406 | ||
d9aba805 ILT |
6407 | /* To support a PC relative reloc when generating embedded PIC code |
6408 | for ECOFF, we use a Cygnus extension. We check for that here to | |
6409 | make sure that we don't let such a reloc escape normally. */ | |
6410 | #ifdef OBJ_ECOFF | |
6411 | if (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 | |
6412 | && mips_pic != EMBEDDED_PIC) | |
6413 | reloc->howto = NULL; | |
6414 | else | |
6415 | #endif | |
6416 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); | |
0dd2d296 | 6417 | |
52aa70b5 JW |
6418 | if (reloc->howto == NULL) |
6419 | { | |
6420 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
6421 | "Can not represent relocation in this object file format"); | |
0dd2d296 | 6422 | retval[0] = NULL; |
52aa70b5 | 6423 | } |
3d3c5039 | 6424 | |
0dd2d296 | 6425 | return retval; |
3d3c5039 ILT |
6426 | } |
6427 | ||
0dd2d296 ILT |
6428 | /* Convert a machine dependent frag. */ |
6429 | ||
6430 | void | |
6431 | md_convert_frag (abfd, asec, fragp) | |
6432 | bfd *abfd; | |
6433 | segT asec; | |
6434 | fragS *fragp; | |
3d3c5039 | 6435 | { |
0dd2d296 ILT |
6436 | int old, new; |
6437 | char *fixptr; | |
3d3c5039 | 6438 | |
0dd2d296 ILT |
6439 | if (fragp->fr_opcode == NULL) |
6440 | return; | |
3d3c5039 | 6441 | |
0dd2d296 ILT |
6442 | old = RELAX_OLD (fragp->fr_subtype); |
6443 | new = RELAX_NEW (fragp->fr_subtype); | |
6444 | fixptr = fragp->fr_literal + fragp->fr_fix; | |
6445 | ||
6446 | if (new > 0) | |
6447 | memcpy (fixptr - old, fixptr, new); | |
6448 | ||
6449 | fragp->fr_fix += new - old; | |
6450 | } | |
becfe05e ILT |
6451 | |
6452 | /* This function is called whenever a label is defined. It is used | |
6453 | when handling branch delays; if a branch has a label, we assume we | |
6454 | can not move it. */ | |
6455 | ||
6456 | void | |
6457 | mips_define_label (sym) | |
6458 | symbolS *sym; | |
6459 | { | |
6460 | insn_label = sym; | |
6461 | } | |
3d3c5039 | 6462 | \f |
f2a663d3 ILT |
6463 | #ifdef OBJ_ELF |
6464 | ||
0dd2d296 | 6465 | /* Some special processing for a MIPS ELF file. */ |
f2a663d3 ILT |
6466 | |
6467 | void | |
6468 | mips_elf_final_processing () | |
6469 | { | |
6470 | Elf32_RegInfo s; | |
6471 | ||
0dd2d296 | 6472 | /* Write out the .reginfo section. */ |
f2a663d3 ILT |
6473 | s.ri_gprmask = mips_gprmask; |
6474 | s.ri_cprmask[0] = mips_cprmask[0]; | |
6475 | s.ri_cprmask[1] = mips_cprmask[1]; | |
6476 | s.ri_cprmask[2] = mips_cprmask[2]; | |
6477 | s.ri_cprmask[3] = mips_cprmask[3]; | |
6478 | /* The gp_value field is set by the MIPS ELF backend. */ | |
6479 | ||
6480 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
6481 | ((Elf32_External_RegInfo *) | |
6482 | mips_regmask_frag)); | |
0dd2d296 ILT |
6483 | |
6484 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
6485 | sort of BFD interface for this. */ | |
6486 | if (mips_any_noreorder) | |
6487 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
d9aba805 | 6488 | if (mips_pic != NO_PIC) |
0dd2d296 | 6489 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
f2a663d3 ILT |
6490 | } |
6491 | ||
6492 | #endif /* OBJ_ELF */ | |
6493 | \f | |
0dd2d296 | 6494 | #ifndef ECOFF_DEBUGGING |
3d3c5039 ILT |
6495 | |
6496 | /* These functions should really be defined by the object file format, | |
6497 | since they are related to debugging information. However, this | |
6498 | code has to work for the a.out format, which does not define them, | |
6499 | so we provide simple versions here. These don't actually generate | |
6500 | any debugging information, but they do simple checking and someday | |
6501 | somebody may make them useful. */ | |
6502 | ||
670a50eb ILT |
6503 | typedef struct loc |
6504 | { | |
6505 | struct loc *loc_next; | |
6506 | unsigned long loc_fileno; | |
6507 | unsigned long loc_lineno; | |
6508 | unsigned long loc_offset; | |
6509 | unsigned short loc_delta; | |
6510 | unsigned short loc_count; | |
3d3c5039 | 6511 | #if 0 |
670a50eb | 6512 | fragS *loc_frag; |
3d3c5039 | 6513 | #endif |
670a50eb ILT |
6514 | } |
6515 | locS; | |
3d3c5039 | 6516 | |
670a50eb ILT |
6517 | typedef struct proc |
6518 | { | |
3d3c5039 ILT |
6519 | struct proc *proc_next; |
6520 | struct symbol *proc_isym; | |
6521 | struct symbol *proc_end; | |
6522 | unsigned long proc_reg_mask; | |
6523 | unsigned long proc_reg_offset; | |
6524 | unsigned long proc_fpreg_mask; | |
6525 | unsigned long proc_fpreg_offset; | |
6526 | unsigned long proc_frameoffset; | |
6527 | unsigned long proc_framereg; | |
6528 | unsigned long proc_pcreg; | |
6529 | locS *proc_iline; | |
6530 | struct file *proc_file; | |
6531 | int proc_index; | |
670a50eb ILT |
6532 | } |
6533 | procS; | |
3d3c5039 | 6534 | |
670a50eb ILT |
6535 | typedef struct file |
6536 | { | |
3d3c5039 ILT |
6537 | struct file *file_next; |
6538 | unsigned long file_fileno; | |
6539 | struct symbol *file_symbol; | |
6540 | struct symbol *file_end; | |
6541 | struct proc *file_proc; | |
6542 | int file_numprocs; | |
670a50eb ILT |
6543 | } |
6544 | fileS; | |
3d3c5039 ILT |
6545 | |
6546 | static struct obstack proc_frags; | |
6547 | static procS *proc_lastP; | |
6548 | static procS *proc_rootP; | |
6549 | static int numprocs; | |
6550 | ||
6551 | static void | |
6552 | md_obj_begin () | |
6553 | { | |
670a50eb | 6554 | obstack_begin (&proc_frags, 0x2000); |
3d3c5039 ILT |
6555 | } |
6556 | ||
6557 | static void | |
6558 | md_obj_end () | |
6559 | { | |
6560 | /* check for premature end, nesting errors, etc */ | |
6561 | if (proc_lastP && proc_lastP->proc_end == NULL) | |
670a50eb | 6562 | as_warn ("missing `.end' at end of assembly"); |
3d3c5039 ILT |
6563 | } |
6564 | ||
6565 | extern char hex_value[]; | |
6566 | ||
6567 | static long | |
6568 | get_number () | |
6569 | { | |
670a50eb ILT |
6570 | int negative = 0; |
6571 | long val = 0; | |
3d3c5039 | 6572 | |
670a50eb ILT |
6573 | if (*input_line_pointer == '-') |
6574 | { | |
6575 | ++input_line_pointer; | |
6576 | negative = 1; | |
3d3c5039 | 6577 | } |
670a50eb ILT |
6578 | if (!isdigit (*input_line_pointer)) |
6579 | as_bad ("Expected simple number."); | |
6580 | if (input_line_pointer[0] == '0') | |
6581 | { | |
6582 | if (input_line_pointer[1] == 'x') | |
6583 | { | |
6584 | input_line_pointer += 2; | |
6585 | while (isxdigit (*input_line_pointer)) | |
6586 | { | |
6587 | val <<= 4; | |
6588 | val |= hex_value[(int) *input_line_pointer++]; | |
3d3c5039 | 6589 | } |
670a50eb ILT |
6590 | return negative ? -val : val; |
6591 | } | |
6592 | else | |
6593 | { | |
6594 | ++input_line_pointer; | |
6595 | while (isdigit (*input_line_pointer)) | |
6596 | { | |
6597 | val <<= 3; | |
6598 | val |= *input_line_pointer++ - '0'; | |
3d3c5039 | 6599 | } |
670a50eb | 6600 | return negative ? -val : val; |
3d3c5039 ILT |
6601 | } |
6602 | } | |
670a50eb ILT |
6603 | if (!isdigit (*input_line_pointer)) |
6604 | { | |
6605 | printf (" *input_line_pointer == '%c' 0x%02x\n", | |
6606 | *input_line_pointer, *input_line_pointer); | |
6607 | as_warn ("Invalid number"); | |
6608 | return -1; | |
3d3c5039 | 6609 | } |
670a50eb ILT |
6610 | while (isdigit (*input_line_pointer)) |
6611 | { | |
6612 | val *= 10; | |
6613 | val += *input_line_pointer++ - '0'; | |
3d3c5039 | 6614 | } |
670a50eb | 6615 | return negative ? -val : val; |
3d3c5039 ILT |
6616 | } |
6617 | ||
6618 | /* The .file directive; just like the usual .file directive, but there | |
6619 | is an initial number which is the ECOFF file index. */ | |
6620 | ||
6621 | static void | |
6622 | s_file (x) | |
6623 | int x; | |
6624 | { | |
670a50eb | 6625 | int line; |
3d3c5039 | 6626 | |
670a50eb | 6627 | line = get_number (); |
9a7d824a | 6628 | s_app_file (0); |
3d3c5039 ILT |
6629 | } |
6630 | ||
6631 | ||
6632 | /* The .end directive. */ | |
6633 | ||
6634 | static void | |
6635 | s_mipsend (x) | |
6636 | int x; | |
6637 | { | |
670a50eb ILT |
6638 | symbolS *p; |
6639 | ||
6640 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
6641 | { | |
6642 | p = get_symbol (); | |
6643 | demand_empty_rest_of_line (); | |
6644 | } | |
6645 | else | |
6646 | p = NULL; | |
6647 | if (now_seg != text_section) | |
6648 | as_warn (".end not in text section"); | |
6649 | if (!proc_lastP) | |
6650 | { | |
6651 | as_warn (".end and no .ent seen yet."); | |
6652 | return; | |
3d3c5039 ILT |
6653 | } |
6654 | ||
670a50eb ILT |
6655 | if (p != NULL) |
6656 | { | |
6657 | assert (S_GET_NAME (p)); | |
6658 | if (strcmp (S_GET_NAME (p), S_GET_NAME (proc_lastP->proc_isym))) | |
6659 | as_warn (".end symbol does not match .ent symbol."); | |
3d3c5039 ILT |
6660 | } |
6661 | ||
670a50eb | 6662 | proc_lastP->proc_end = (symbolS *) 1; |
3d3c5039 ILT |
6663 | } |
6664 | ||
6665 | /* The .aent and .ent directives. */ | |
6666 | ||
6667 | static void | |
6668 | s_ent (aent) | |
6669 | int aent; | |
6670 | { | |
670a50eb ILT |
6671 | int number = 0; |
6672 | procS *procP; | |
6673 | symbolS *symbolP; | |
6674 | ||
6675 | symbolP = get_symbol (); | |
6676 | if (*input_line_pointer == ',') | |
6677 | input_line_pointer++; | |
dd3f1f76 | 6678 | SKIP_WHITESPACE (); |
670a50eb ILT |
6679 | if (isdigit (*input_line_pointer) || *input_line_pointer == '-') |
6680 | number = get_number (); | |
6681 | if (now_seg != text_section) | |
6682 | as_warn (".ent or .aent not in text section."); | |
6683 | ||
6684 | if (!aent && proc_lastP && proc_lastP->proc_end == NULL) | |
6685 | as_warn ("missing `.end'"); | |
6686 | ||
6687 | if (!aent) | |
6688 | { | |
6689 | procP = (procS *) obstack_alloc (&proc_frags, sizeof (*procP)); | |
6690 | procP->proc_isym = symbolP; | |
6691 | procP->proc_reg_mask = 0; | |
6692 | procP->proc_reg_offset = 0; | |
6693 | procP->proc_fpreg_mask = 0; | |
6694 | procP->proc_fpreg_offset = 0; | |
6695 | procP->proc_frameoffset = 0; | |
6696 | procP->proc_framereg = 0; | |
6697 | procP->proc_pcreg = 0; | |
6698 | procP->proc_end = NULL; | |
6699 | procP->proc_next = NULL; | |
6700 | if (proc_lastP) | |
6701 | proc_lastP->proc_next = procP; | |
6702 | else | |
6703 | proc_rootP = procP; | |
6704 | proc_lastP = procP; | |
6705 | numprocs++; | |
3d3c5039 | 6706 | } |
670a50eb | 6707 | demand_empty_rest_of_line (); |
3d3c5039 ILT |
6708 | } |
6709 | ||
6710 | /* The .frame directive. */ | |
6711 | ||
88225433 | 6712 | #if 0 |
3d3c5039 ILT |
6713 | static void |
6714 | s_frame (x) | |
670a50eb | 6715 | int x; |
3d3c5039 | 6716 | { |
670a50eb ILT |
6717 | char str[100]; |
6718 | symbolS *symP; | |
6719 | int frame_reg; | |
6720 | int frame_off; | |
6721 | int pcreg; | |
6722 | ||
0dd2d296 | 6723 | frame_reg = tc_get_register (1); |
670a50eb ILT |
6724 | if (*input_line_pointer == ',') |
6725 | input_line_pointer++; | |
5ac34ac3 | 6726 | frame_off = get_absolute_expression (); |
670a50eb ILT |
6727 | if (*input_line_pointer == ',') |
6728 | input_line_pointer++; | |
0dd2d296 | 6729 | pcreg = tc_get_register (0); |
670a50eb ILT |
6730 | |
6731 | /* bob third eye */ | |
6732 | assert (proc_rootP); | |
6733 | proc_rootP->proc_framereg = frame_reg; | |
6734 | proc_rootP->proc_frameoffset = frame_off; | |
6735 | proc_rootP->proc_pcreg = pcreg; | |
6736 | /* bob macho .frame */ | |
6737 | ||
6738 | /* We don't have to write out a frame stab for unoptimized code. */ | |
9226253a | 6739 | if (!(frame_reg == FP && frame_off == 0)) |
670a50eb ILT |
6740 | { |
6741 | if (!proc_lastP) | |
6742 | as_warn ("No .ent for .frame to use."); | |
6743 | (void) sprintf (str, "R%d;%d", frame_reg, frame_off); | |
6744 | symP = symbol_new (str, N_VFP, 0, frag_now); | |
6745 | S_SET_TYPE (symP, N_RMASK); | |
6746 | S_SET_OTHER (symP, 0); | |
6747 | S_SET_DESC (symP, 0); | |
6748 | symP->sy_forward = proc_lastP->proc_isym; | |
6749 | /* bob perhaps I should have used pseudo set */ | |
3d3c5039 | 6750 | } |
670a50eb | 6751 | demand_empty_rest_of_line (); |
3d3c5039 | 6752 | } |
88225433 | 6753 | #endif |
3d3c5039 ILT |
6754 | |
6755 | /* The .fmask and .mask directives. */ | |
6756 | ||
88225433 | 6757 | #if 0 |
3d3c5039 ILT |
6758 | static void |
6759 | s_mask (reg_type) | |
6760 | char reg_type; | |
6761 | { | |
670a50eb ILT |
6762 | char str[100], *strP; |
6763 | symbolS *symP; | |
6764 | int i; | |
6765 | unsigned int mask; | |
6766 | int off; | |
6767 | ||
6768 | mask = get_number (); | |
6769 | if (*input_line_pointer == ',') | |
6770 | input_line_pointer++; | |
6771 | off = get_absolute_expression (); | |
6772 | ||
6773 | /* bob only for coff */ | |
6774 | assert (proc_rootP); | |
6775 | if (reg_type == 'F') | |
6776 | { | |
6777 | proc_rootP->proc_fpreg_mask = mask; | |
6778 | proc_rootP->proc_fpreg_offset = off; | |
3d3c5039 | 6779 | } |
670a50eb ILT |
6780 | else |
6781 | { | |
6782 | proc_rootP->proc_reg_mask = mask; | |
6783 | proc_rootP->proc_reg_offset = off; | |
6784 | } | |
6785 | ||
6786 | /* bob macho .mask + .fmask */ | |
3d3c5039 | 6787 | |
670a50eb ILT |
6788 | /* We don't have to write out a mask stab if no saved regs. */ |
6789 | if (!(mask == 0)) | |
6790 | { | |
6791 | if (!proc_lastP) | |
6792 | as_warn ("No .ent for .mask to use."); | |
6793 | strP = str; | |
6794 | for (i = 0; i < 32; i++) | |
6795 | { | |
6796 | if (mask % 2) | |
6797 | { | |
6798 | sprintf (strP, "%c%d,", reg_type, i); | |
6799 | strP += strlen (strP); | |
6800 | } | |
3d3c5039 | 6801 | mask /= 2; |
670a50eb ILT |
6802 | } |
6803 | sprintf (strP, ";%d,", off); | |
6804 | symP = symbol_new (str, N_RMASK, 0, frag_now); | |
6805 | S_SET_TYPE (symP, N_RMASK); | |
6806 | S_SET_OTHER (symP, 0); | |
6807 | S_SET_DESC (symP, 0); | |
6808 | symP->sy_forward = proc_lastP->proc_isym; | |
6809 | /* bob perhaps I should have used pseudo set */ | |
3d3c5039 | 6810 | } |
3d3c5039 | 6811 | } |
88225433 | 6812 | #endif |
3d3c5039 ILT |
6813 | |
6814 | /* The .loc directive. */ | |
6815 | ||
88225433 | 6816 | #if 0 |
3d3c5039 ILT |
6817 | static void |
6818 | s_loc (x) | |
6819 | int x; | |
6820 | { | |
670a50eb ILT |
6821 | symbolS *symbolP; |
6822 | int lineno; | |
6823 | int addroff; | |
3d3c5039 | 6824 | |
670a50eb | 6825 | assert (now_seg == text_section); |
3d3c5039 | 6826 | |
670a50eb ILT |
6827 | lineno = get_number (); |
6828 | addroff = obstack_next_free (&frags) - frag_now->fr_literal; | |
3d3c5039 | 6829 | |
670a50eb ILT |
6830 | symbolP = symbol_new ("", N_SLINE, addroff, frag_now); |
6831 | S_SET_TYPE (symbolP, N_SLINE); | |
6832 | S_SET_OTHER (symbolP, 0); | |
6833 | S_SET_DESC (symbolP, lineno); | |
6834 | symbolP->sy_segment = now_seg; | |
3d3c5039 | 6835 | } |
88225433 | 6836 | #endif |
3d3c5039 | 6837 | |
0dd2d296 | 6838 | #endif /* ! defined (ECOFF_DEBUGGING) */ |