Commit | Line | Data |
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252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
81912461 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
f17c130b | 3 | 2003, 2004, 2005 Free Software Foundation, Inc. |
252b5132 RH |
4 | Contributed by the OSF and Ralph Campbell. |
5 | Written by Keith Knowles and Ralph Campbell, working independently. | |
6 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
7 | Support. | |
8 | ||
9 | This file is part of GAS. | |
10 | ||
11 | GAS is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2, or (at your option) | |
14 | any later version. | |
15 | ||
16 | GAS is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
23 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
24 | 02110-1301, USA. */ | |
252b5132 RH |
25 | |
26 | #include "as.h" | |
27 | #include "config.h" | |
28 | #include "subsegs.h" | |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | |
252b5132 | 31 | #include <stdarg.h> |
252b5132 RH |
32 | |
33 | #include "opcode/mips.h" | |
34 | #include "itbl-ops.h" | |
c5dd6aab | 35 | #include "dwarf2dbg.h" |
5862107c | 36 | #include "dw2gencfi.h" |
252b5132 RH |
37 | |
38 | #ifdef DEBUG | |
39 | #define DBG(x) printf x | |
40 | #else | |
41 | #define DBG(x) | |
42 | #endif | |
43 | ||
44 | #ifdef OBJ_MAYBE_ELF | |
45 | /* Clean up namespace so we can include obj-elf.h too. */ | |
17a2f251 TS |
46 | static int mips_output_flavor (void); |
47 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
48 | #undef OBJ_PROCESS_STAB |
49 | #undef OUTPUT_FLAVOR | |
50 | #undef S_GET_ALIGN | |
51 | #undef S_GET_SIZE | |
52 | #undef S_SET_ALIGN | |
53 | #undef S_SET_SIZE | |
252b5132 RH |
54 | #undef obj_frob_file |
55 | #undef obj_frob_file_after_relocs | |
56 | #undef obj_frob_symbol | |
57 | #undef obj_pop_insert | |
58 | #undef obj_sec_sym_ok_for_reloc | |
59 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
60 | ||
61 | #include "obj-elf.h" | |
62 | /* Fix any of them that we actually care about. */ | |
63 | #undef OUTPUT_FLAVOR | |
64 | #define OUTPUT_FLAVOR mips_output_flavor() | |
65 | #endif | |
66 | ||
67 | #if defined (OBJ_ELF) | |
68 | #include "elf/mips.h" | |
69 | #endif | |
70 | ||
71 | #ifndef ECOFF_DEBUGGING | |
72 | #define NO_ECOFF_DEBUGGING | |
73 | #define ECOFF_DEBUGGING 0 | |
74 | #endif | |
75 | ||
ecb4347a DJ |
76 | int mips_flag_mdebug = -1; |
77 | ||
dcd410fe RO |
78 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
79 | linker doesn't know about and discards them, but relocations against them | |
80 | remain, leading to rld crashes. */ | |
81 | #ifdef TE_IRIX | |
82 | int mips_flag_pdr = FALSE; | |
83 | #else | |
84 | int mips_flag_pdr = TRUE; | |
85 | #endif | |
86 | ||
252b5132 RH |
87 | #include "ecoff.h" |
88 | ||
89 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
90 | static char *mips_regmask_frag; | |
91 | #endif | |
92 | ||
85b51719 | 93 | #define ZERO 0 |
252b5132 RH |
94 | #define AT 1 |
95 | #define TREG 24 | |
96 | #define PIC_CALL_REG 25 | |
97 | #define KT0 26 | |
98 | #define KT1 27 | |
99 | #define GP 28 | |
100 | #define SP 29 | |
101 | #define FP 30 | |
102 | #define RA 31 | |
103 | ||
104 | #define ILLEGAL_REG (32) | |
105 | ||
106 | /* Allow override of standard little-endian ECOFF format. */ | |
107 | ||
108 | #ifndef ECOFF_LITTLE_FORMAT | |
109 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
110 | #endif | |
111 | ||
112 | extern int target_big_endian; | |
113 | ||
252b5132 | 114 | /* The name of the readonly data section. */ |
4d0d148d | 115 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ |
252b5132 | 116 | ? ".rdata" \ |
056350c6 NC |
117 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
118 | ? ".rdata" \ | |
252b5132 RH |
119 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
120 | ? ".rodata" \ | |
121 | : (abort (), "")) | |
122 | ||
47e39b9d RS |
123 | /* Information about an instruction, including its format, operands |
124 | and fixups. */ | |
125 | struct mips_cl_insn | |
126 | { | |
127 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ | |
128 | const struct mips_opcode *insn_mo; | |
129 | ||
130 | /* True if this is a mips16 instruction and if we want the extended | |
131 | form of INSN_MO. */ | |
132 | bfd_boolean use_extend; | |
133 | ||
134 | /* The 16-bit extension instruction to use when USE_EXTEND is true. */ | |
135 | unsigned short extend; | |
136 | ||
137 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is | |
138 | a copy of INSN_MO->match with the operands filled in. */ | |
139 | unsigned long insn_opcode; | |
140 | ||
141 | /* The frag that contains the instruction. */ | |
142 | struct frag *frag; | |
143 | ||
144 | /* The offset into FRAG of the first instruction byte. */ | |
145 | long where; | |
146 | ||
147 | /* The relocs associated with the instruction, if any. */ | |
148 | fixS *fixp[3]; | |
149 | ||
a38419a5 RS |
150 | /* True if this entry cannot be moved from its current position. */ |
151 | unsigned int fixed_p : 1; | |
47e39b9d | 152 | |
708587a4 | 153 | /* True if this instruction occurred in a .set noreorder block. */ |
47e39b9d RS |
154 | unsigned int noreorder_p : 1; |
155 | ||
2fa15973 RS |
156 | /* True for mips16 instructions that jump to an absolute address. */ |
157 | unsigned int mips16_absolute_jump_p : 1; | |
47e39b9d RS |
158 | }; |
159 | ||
a325df1d TS |
160 | /* The ABI to use. */ |
161 | enum mips_abi_level | |
162 | { | |
163 | NO_ABI = 0, | |
164 | O32_ABI, | |
165 | O64_ABI, | |
166 | N32_ABI, | |
167 | N64_ABI, | |
168 | EABI_ABI | |
169 | }; | |
170 | ||
171 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 172 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 173 | |
143d77c5 EC |
174 | /* Whether or not we have code that can call pic code. */ |
175 | int mips_abicalls = FALSE; | |
176 | ||
aa6975fb ILT |
177 | /* Whether or not we have code which can be put into a shared |
178 | library. */ | |
179 | static bfd_boolean mips_in_shared = TRUE; | |
180 | ||
252b5132 RH |
181 | /* This is the set of options which may be modified by the .set |
182 | pseudo-op. We use a struct so that .set push and .set pop are more | |
183 | reliable. */ | |
184 | ||
e972090a NC |
185 | struct mips_set_options |
186 | { | |
252b5132 RH |
187 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
188 | if it has not been initialized. Changed by `.set mipsN', and the | |
189 | -mipsN command line option, and the default CPU. */ | |
190 | int isa; | |
1f25f5d3 CD |
191 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
192 | if they have not been initialized. Changed by `.set <asename>', by | |
193 | command line options, and based on the default architecture. */ | |
194 | int ase_mips3d; | |
deec1734 | 195 | int ase_mdmx; |
e16bfa71 | 196 | int ase_smartmips; |
74cd071d | 197 | int ase_dsp; |
ef2e4d86 | 198 | int ase_mt; |
252b5132 RH |
199 | /* Whether we are assembling for the mips16 processor. 0 if we are |
200 | not, 1 if we are, and -1 if the value has not been initialized. | |
201 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
202 | -nomips16 command line options, and the default CPU. */ | |
203 | int mips16; | |
204 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
205 | reorder' and `.set noreorder'. */ | |
206 | int noreorder; | |
207 | /* Non-zero if we should not permit the $at ($1) register to be used | |
208 | in instructions. Changed by `.set at' and `.set noat'. */ | |
209 | int noat; | |
210 | /* Non-zero if we should warn when a macro instruction expands into | |
211 | more than one machine instruction. Changed by `.set nomacro' and | |
212 | `.set macro'. */ | |
213 | int warn_about_macros; | |
214 | /* Non-zero if we should not move instructions. Changed by `.set | |
215 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
216 | int nomove; | |
217 | /* Non-zero if we should not optimize branches by moving the target | |
218 | of the branch into the delay slot. Actually, we don't perform | |
219 | this optimization anyhow. Changed by `.set bopt' and `.set | |
220 | nobopt'. */ | |
221 | int nobopt; | |
222 | /* Non-zero if we should not autoextend mips16 instructions. | |
223 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
224 | int noautoextend; | |
a325df1d TS |
225 | /* Restrict general purpose registers and floating point registers |
226 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
227 | is passed but can changed if the assembler code uses .set mipsN. */ | |
228 | int gp32; | |
229 | int fp32; | |
fef14a42 TS |
230 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
231 | command line option, and the default CPU. */ | |
232 | int arch; | |
aed1a261 RS |
233 | /* True if ".set sym32" is in effect. */ |
234 | bfd_boolean sym32; | |
252b5132 RH |
235 | }; |
236 | ||
a325df1d | 237 | /* True if -mgp32 was passed. */ |
a8e8e863 | 238 | static int file_mips_gp32 = -1; |
a325df1d TS |
239 | |
240 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 241 | static int file_mips_fp32 = -1; |
a325df1d | 242 | |
252b5132 | 243 | /* This is the struct we use to hold the current set of options. Note |
a4672219 | 244 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to |
e7af610e | 245 | -1 to indicate that they have not been initialized. */ |
252b5132 | 246 | |
e972090a NC |
247 | static struct mips_set_options mips_opts = |
248 | { | |
e16bfa71 | 249 | ISA_UNKNOWN, -1, -1, 0, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN, FALSE |
e7af610e | 250 | }; |
252b5132 RH |
251 | |
252 | /* These variables are filled in with the masks of registers used. | |
253 | The object format code reads them and puts them in the appropriate | |
254 | place. */ | |
255 | unsigned long mips_gprmask; | |
256 | unsigned long mips_cprmask[4]; | |
257 | ||
258 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 259 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 260 | |
a4672219 TS |
261 | /* True if -mips16 was passed or implied by arguments passed on the |
262 | command line (e.g., by -march). */ | |
263 | static int file_ase_mips16; | |
264 | ||
1f25f5d3 CD |
265 | /* True if -mips3d was passed or implied by arguments passed on the |
266 | command line (e.g., by -march). */ | |
267 | static int file_ase_mips3d; | |
268 | ||
deec1734 CD |
269 | /* True if -mdmx was passed or implied by arguments passed on the |
270 | command line (e.g., by -march). */ | |
271 | static int file_ase_mdmx; | |
272 | ||
e16bfa71 TS |
273 | /* True if -msmartmips was passed or implied by arguments passed on the |
274 | command line (e.g., by -march). */ | |
275 | static int file_ase_smartmips; | |
276 | ||
ad3fea08 TS |
277 | #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \ |
278 | || mips_opts.isa == ISA_MIPS32R2) | |
e16bfa71 | 279 | |
74cd071d CF |
280 | /* True if -mdsp was passed or implied by arguments passed on the |
281 | command line (e.g., by -march). */ | |
282 | static int file_ase_dsp; | |
283 | ||
ad3fea08 TS |
284 | #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
285 | || mips_opts.isa == ISA_MIPS64R2) | |
286 | ||
65263ce3 TS |
287 | #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2) |
288 | ||
ef2e4d86 CF |
289 | /* True if -mmt was passed or implied by arguments passed on the |
290 | command line (e.g., by -march). */ | |
291 | static int file_ase_mt; | |
292 | ||
ad3fea08 TS |
293 | #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
294 | || mips_opts.isa == ISA_MIPS64R2) | |
295 | ||
ec68c924 | 296 | /* The argument of the -march= flag. The architecture we are assembling. */ |
fef14a42 | 297 | static int file_mips_arch = CPU_UNKNOWN; |
316f5878 | 298 | static const char *mips_arch_string; |
ec68c924 EC |
299 | |
300 | /* The argument of the -mtune= flag. The architecture for which we | |
301 | are optimizing. */ | |
302 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 303 | static const char *mips_tune_string; |
ec68c924 | 304 | |
316f5878 | 305 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
306 | static int mips_32bitmode = 0; |
307 | ||
316f5878 RS |
308 | /* True if the given ABI requires 32-bit registers. */ |
309 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
310 | ||
311 | /* Likewise 64-bit registers. */ | |
707bfff6 TS |
312 | #define ABI_NEEDS_64BIT_REGS(ABI) \ |
313 | ((ABI) == N32_ABI \ | |
314 | || (ABI) == N64_ABI \ | |
316f5878 RS |
315 | || (ABI) == O64_ABI) |
316 | ||
ad3fea08 | 317 | /* Return true if ISA supports 64 bit wide gp registers. */ |
707bfff6 TS |
318 | #define ISA_HAS_64BIT_REGS(ISA) \ |
319 | ((ISA) == ISA_MIPS3 \ | |
320 | || (ISA) == ISA_MIPS4 \ | |
321 | || (ISA) == ISA_MIPS5 \ | |
322 | || (ISA) == ISA_MIPS64 \ | |
323 | || (ISA) == ISA_MIPS64R2) | |
9ce8a5dd | 324 | |
ad3fea08 TS |
325 | /* Return true if ISA supports 64 bit wide float registers. */ |
326 | #define ISA_HAS_64BIT_FPRS(ISA) \ | |
327 | ((ISA) == ISA_MIPS3 \ | |
328 | || (ISA) == ISA_MIPS4 \ | |
329 | || (ISA) == ISA_MIPS5 \ | |
330 | || (ISA) == ISA_MIPS32R2 \ | |
331 | || (ISA) == ISA_MIPS64 \ | |
332 | || (ISA) == ISA_MIPS64R2) | |
333 | ||
af7ee8bf CD |
334 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
335 | instructions. */ | |
707bfff6 TS |
336 | #define ISA_HAS_DROR(ISA) \ |
337 | ((ISA) == ISA_MIPS64R2) | |
af7ee8bf CD |
338 | |
339 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
340 | instructions. */ | |
707bfff6 TS |
341 | #define ISA_HAS_ROR(ISA) \ |
342 | ((ISA) == ISA_MIPS32R2 \ | |
343 | || (ISA) == ISA_MIPS64R2 \ | |
344 | || mips_opts.ase_smartmips) | |
345 | ||
7455baf8 TS |
346 | /* Return true if ISA supports single-precision floats in odd registers. */ |
347 | #define ISA_HAS_ODD_SINGLE_FPR(ISA) \ | |
348 | ((ISA) == ISA_MIPS32 \ | |
349 | || (ISA) == ISA_MIPS32R2 \ | |
350 | || (ISA) == ISA_MIPS64 \ | |
351 | || (ISA) == ISA_MIPS64R2) | |
af7ee8bf | 352 | |
ad3fea08 TS |
353 | /* Return true if ISA supports move to/from high part of a 64-bit |
354 | floating-point register. */ | |
355 | #define ISA_HAS_MXHC1(ISA) \ | |
356 | ((ISA) == ISA_MIPS32R2 \ | |
357 | || (ISA) == ISA_MIPS64R2) | |
358 | ||
e013f690 | 359 | #define HAVE_32BIT_GPRS \ |
ad3fea08 | 360 | (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 361 | |
e013f690 | 362 | #define HAVE_32BIT_FPRS \ |
ad3fea08 | 363 | (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa)) |
ca4e0257 | 364 | |
ad3fea08 TS |
365 | #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS) |
366 | #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS) | |
ca4e0257 | 367 | |
316f5878 | 368 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 369 | |
316f5878 | 370 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 371 | |
3b91255e RS |
372 | /* True if relocations are stored in-place. */ |
373 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
374 | ||
aed1a261 RS |
375 | /* The ABI-derived address size. */ |
376 | #define HAVE_64BIT_ADDRESSES \ | |
377 | (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) | |
378 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) | |
e013f690 | 379 | |
aed1a261 RS |
380 | /* The size of symbolic constants (i.e., expressions of the form |
381 | "SYMBOL" or "SYMBOL + OFFSET"). */ | |
382 | #define HAVE_32BIT_SYMBOLS \ | |
383 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) | |
384 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) | |
ca4e0257 | 385 | |
b7c7d6c1 TS |
386 | /* Addresses are loaded in different ways, depending on the address size |
387 | in use. The n32 ABI Documentation also mandates the use of additions | |
388 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 389 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 390 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
391 | |
392 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 393 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
394 | |
395 | #define ADDRESS_LOAD_INSN \ | |
396 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
397 | ||
398 | #define ADDRESS_STORE_INSN \ | |
399 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
400 | ||
a4672219 | 401 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
402 | #define CPU_HAS_MIPS16(cpu) \ |
403 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
404 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 405 | |
60b63b72 RS |
406 | /* True if CPU has a dror instruction. */ |
407 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
408 | ||
409 | /* True if CPU has a ror instruction. */ | |
410 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
411 | ||
c8978940 CD |
412 | /* True if mflo and mfhi can be immediately followed by instructions |
413 | which write to the HI and LO registers. | |
414 | ||
415 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
416 | (at least) two instructions between the reads of HI/LO and | |
417 | instructions which write them, and later ISAs do not. Contradicting | |
418 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
419 | the UM for the NEC Vr5000) document needing the instructions between | |
420 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
421 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
422 | earlier-ISA CPUs for which CPU documentation declares that the | |
423 | instructions are really interlocked. */ | |
424 | #define hilo_interlocks \ | |
425 | (mips_opts.isa == ISA_MIPS32 \ | |
426 | || mips_opts.isa == ISA_MIPS32R2 \ | |
427 | || mips_opts.isa == ISA_MIPS64 \ | |
428 | || mips_opts.isa == ISA_MIPS64R2 \ | |
429 | || mips_opts.arch == CPU_R4010 \ | |
430 | || mips_opts.arch == CPU_R10000 \ | |
431 | || mips_opts.arch == CPU_R12000 \ | |
432 | || mips_opts.arch == CPU_RM7000 \ | |
c8978940 CD |
433 | || mips_opts.arch == CPU_VR5500 \ |
434 | ) | |
252b5132 RH |
435 | |
436 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
437 | from the GPRs after they are loaded from memory, and thus does not |
438 | require nops to be inserted. This applies to instructions marked | |
439 | INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA | |
440 | level I. */ | |
252b5132 | 441 | #define gpr_interlocks \ |
e7af610e | 442 | (mips_opts.isa != ISA_MIPS1 \ |
fef14a42 | 443 | || mips_opts.arch == CPU_R3900) |
252b5132 | 444 | |
81912461 ILT |
445 | /* Whether the processor uses hardware interlocks to avoid delays |
446 | required by coprocessor instructions, and thus does not require | |
447 | nops to be inserted. This applies to instructions marked | |
448 | INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays | |
449 | between instructions marked INSN_WRITE_COND_CODE and ones marked | |
450 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA | |
451 | levels I, II, and III. */ | |
bdaaa2e1 | 452 | /* Itbl support may require additional care here. */ |
81912461 ILT |
453 | #define cop_interlocks \ |
454 | ((mips_opts.isa != ISA_MIPS1 \ | |
455 | && mips_opts.isa != ISA_MIPS2 \ | |
456 | && mips_opts.isa != ISA_MIPS3) \ | |
457 | || mips_opts.arch == CPU_R4300 \ | |
81912461 ILT |
458 | ) |
459 | ||
460 | /* Whether the processor uses hardware interlocks to protect reads | |
461 | from coprocessor registers after they are loaded from memory, and | |
462 | thus does not require nops to be inserted. This applies to | |
463 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
464 | requires at MIPS ISA level I. */ | |
465 | #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1) | |
252b5132 | 466 | |
6b76fefe CM |
467 | /* Is this a mfhi or mflo instruction? */ |
468 | #define MF_HILO_INSN(PINFO) \ | |
469 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) | |
470 | ||
252b5132 RH |
471 | /* MIPS PIC level. */ |
472 | ||
a161fe53 | 473 | enum mips_pic_level mips_pic; |
252b5132 | 474 | |
c9914766 | 475 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 476 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 477 | static int mips_big_got = 0; |
252b5132 RH |
478 | |
479 | /* 1 if trap instructions should used for overflow rather than break | |
480 | instructions. */ | |
c9914766 | 481 | static int mips_trap = 0; |
252b5132 | 482 | |
119d663a | 483 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 484 | by assembling two single width halves into two single width floating |
119d663a NC |
485 | point registers which just happen to alias the double width destination |
486 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 487 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
488 | automatically at assemble time. */ |
489 | static int mips_disable_float_construction; | |
490 | ||
252b5132 RH |
491 | /* Non-zero if any .set noreorder directives were used. */ |
492 | ||
493 | static int mips_any_noreorder; | |
494 | ||
6b76fefe CM |
495 | /* Non-zero if nops should be inserted when the register referenced in |
496 | an mfhi/mflo instruction is read in the next two instructions. */ | |
497 | static int mips_7000_hilo_fix; | |
498 | ||
252b5132 | 499 | /* The size of the small data section. */ |
156c2f8b | 500 | static unsigned int g_switch_value = 8; |
252b5132 RH |
501 | /* Whether the -G option was used. */ |
502 | static int g_switch_seen = 0; | |
503 | ||
504 | #define N_RMASK 0xc4 | |
505 | #define N_VFP 0xd4 | |
506 | ||
507 | /* If we can determine in advance that GP optimization won't be | |
508 | possible, we can skip the relaxation stuff that tries to produce | |
509 | GP-relative references. This makes delay slot optimization work | |
510 | better. | |
511 | ||
512 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
513 | gcc output. It needs to guess right for gcc, otherwise gcc |
514 | will put what it thinks is a GP-relative instruction in a branch | |
515 | delay slot. | |
252b5132 RH |
516 | |
517 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
518 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 519 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
520 | |
521 | /* handle of the OPCODE hash table */ | |
522 | static struct hash_control *op_hash = NULL; | |
523 | ||
524 | /* The opcode hash table we use for the mips16. */ | |
525 | static struct hash_control *mips16_op_hash = NULL; | |
526 | ||
527 | /* This array holds the chars that always start a comment. If the | |
528 | pre-processor is disabled, these aren't very useful */ | |
529 | const char comment_chars[] = "#"; | |
530 | ||
531 | /* This array holds the chars that only start a comment at the beginning of | |
532 | a line. If the line seems to have the form '# 123 filename' | |
533 | .line and .file directives will appear in the pre-processed output */ | |
534 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
535 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 536 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
537 | /* Also note that C style comments are always supported. */ |
538 | const char line_comment_chars[] = "#"; | |
539 | ||
bdaaa2e1 | 540 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 541 | const char line_separator_chars[] = ";"; |
252b5132 RH |
542 | |
543 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
544 | const char EXP_CHARS[] = "eE"; | |
545 | ||
546 | /* Chars that mean this number is a floating point constant */ | |
547 | /* As in 0f12.456 */ | |
548 | /* or 0d1.2345e12 */ | |
549 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
550 | ||
551 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
552 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
553 | but nothing is ideal around here. | |
554 | */ | |
555 | ||
556 | static char *insn_error; | |
557 | ||
558 | static int auto_align = 1; | |
559 | ||
560 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
561 | offset in the stack frame from which to restore the $gp register. | |
562 | This is set by the .cprestore pseudo-op, and saved in this | |
563 | variable. */ | |
564 | static offsetT mips_cprestore_offset = -1; | |
565 | ||
67c1ffbe | 566 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 567 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 568 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
569 | static offsetT mips_cpreturn_offset = -1; |
570 | static int mips_cpreturn_register = -1; | |
571 | static int mips_gp_register = GP; | |
def2e0dd | 572 | static int mips_gprel_offset = 0; |
6478892d | 573 | |
7a621144 DJ |
574 | /* Whether mips_cprestore_offset has been set in the current function |
575 | (or whether it has already been warned about, if not). */ | |
576 | static int mips_cprestore_valid = 0; | |
577 | ||
252b5132 RH |
578 | /* This is the register which holds the stack frame, as set by the |
579 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
580 | static int mips_frame_reg = SP; | |
581 | ||
7a621144 DJ |
582 | /* Whether mips_frame_reg has been set in the current function |
583 | (or whether it has already been warned about, if not). */ | |
584 | static int mips_frame_reg_valid = 0; | |
585 | ||
252b5132 RH |
586 | /* To output NOP instructions correctly, we need to keep information |
587 | about the previous two instructions. */ | |
588 | ||
589 | /* Whether we are optimizing. The default value of 2 means to remove | |
590 | unneeded NOPs and swap branch instructions when possible. A value | |
591 | of 1 means to not swap branches. A value of 0 means to always | |
592 | insert NOPs. */ | |
593 | static int mips_optimize = 2; | |
594 | ||
595 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
596 | equivalent to seeing no -g option at all. */ | |
597 | static int mips_debug = 0; | |
598 | ||
7d8e00cf RS |
599 | /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ |
600 | #define MAX_VR4130_NOPS 4 | |
601 | ||
602 | /* The maximum number of NOPs needed to fill delay slots. */ | |
603 | #define MAX_DELAY_NOPS 2 | |
604 | ||
605 | /* The maximum number of NOPs needed for any purpose. */ | |
606 | #define MAX_NOPS 4 | |
71400594 RS |
607 | |
608 | /* A list of previous instructions, with index 0 being the most recent. | |
609 | We need to look back MAX_NOPS instructions when filling delay slots | |
610 | or working around processor errata. We need to look back one | |
611 | instruction further if we're thinking about using history[0] to | |
612 | fill a branch delay slot. */ | |
613 | static struct mips_cl_insn history[1 + MAX_NOPS]; | |
252b5132 | 614 | |
1e915849 RS |
615 | /* Nop instructions used by emit_nop. */ |
616 | static struct mips_cl_insn nop_insn, mips16_nop_insn; | |
617 | ||
618 | /* The appropriate nop for the current mode. */ | |
619 | #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn) | |
252b5132 | 620 | |
252b5132 RH |
621 | /* If this is set, it points to a frag holding nop instructions which |
622 | were inserted before the start of a noreorder section. If those | |
623 | nops turn out to be unnecessary, the size of the frag can be | |
624 | decreased. */ | |
625 | static fragS *prev_nop_frag; | |
626 | ||
627 | /* The number of nop instructions we created in prev_nop_frag. */ | |
628 | static int prev_nop_frag_holds; | |
629 | ||
630 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 631 | prev_nop_frag. */ |
252b5132 RH |
632 | static int prev_nop_frag_required; |
633 | ||
634 | /* The number of instructions we've seen since prev_nop_frag. */ | |
635 | static int prev_nop_frag_since; | |
636 | ||
637 | /* For ECOFF and ELF, relocations against symbols are done in two | |
638 | parts, with a HI relocation and a LO relocation. Each relocation | |
639 | has only 16 bits of space to store an addend. This means that in | |
640 | order for the linker to handle carries correctly, it must be able | |
641 | to locate both the HI and the LO relocation. This means that the | |
642 | relocations must appear in order in the relocation table. | |
643 | ||
644 | In order to implement this, we keep track of each unmatched HI | |
645 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 646 | corresponding LO relocation. */ |
252b5132 | 647 | |
e972090a NC |
648 | struct mips_hi_fixup |
649 | { | |
252b5132 RH |
650 | /* Next HI fixup. */ |
651 | struct mips_hi_fixup *next; | |
652 | /* This fixup. */ | |
653 | fixS *fixp; | |
654 | /* The section this fixup is in. */ | |
655 | segT seg; | |
656 | }; | |
657 | ||
658 | /* The list of unmatched HI relocs. */ | |
659 | ||
660 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
661 | ||
64bdfcaf RS |
662 | /* The frag containing the last explicit relocation operator. |
663 | Null if explicit relocations have not been used. */ | |
664 | ||
665 | static fragS *prev_reloc_op_frag; | |
666 | ||
252b5132 RH |
667 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
668 | ||
669 | #define X ILLEGAL_REG | |
e972090a NC |
670 | static const int mips32_to_16_reg_map[] = |
671 | { | |
252b5132 RH |
672 | X, X, 2, 3, 4, 5, 6, 7, |
673 | X, X, X, X, X, X, X, X, | |
674 | 0, 1, X, X, X, X, X, X, | |
675 | X, X, X, X, X, X, X, X | |
676 | }; | |
677 | #undef X | |
678 | ||
679 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
680 | ||
e972090a NC |
681 | static const unsigned int mips16_to_32_reg_map[] = |
682 | { | |
252b5132 RH |
683 | 16, 17, 2, 3, 4, 5, 6, 7 |
684 | }; | |
60b63b72 | 685 | |
71400594 RS |
686 | /* Classifies the kind of instructions we're interested in when |
687 | implementing -mfix-vr4120. */ | |
688 | enum fix_vr4120_class { | |
689 | FIX_VR4120_MACC, | |
690 | FIX_VR4120_DMACC, | |
691 | FIX_VR4120_MULT, | |
692 | FIX_VR4120_DMULT, | |
693 | FIX_VR4120_DIV, | |
694 | FIX_VR4120_MTHILO, | |
695 | NUM_FIX_VR4120_CLASSES | |
696 | }; | |
697 | ||
698 | /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if | |
699 | there must be at least one other instruction between an instruction | |
700 | of type X and an instruction of type Y. */ | |
701 | static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; | |
702 | ||
703 | /* True if -mfix-vr4120 is in force. */ | |
d766e8ec | 704 | static int mips_fix_vr4120; |
4a6a3df4 | 705 | |
7d8e00cf RS |
706 | /* ...likewise -mfix-vr4130. */ |
707 | static int mips_fix_vr4130; | |
708 | ||
4a6a3df4 AO |
709 | /* We don't relax branches by default, since this causes us to expand |
710 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
711 | fail to compute the offset before expanding the macro to the most | |
712 | efficient expansion. */ | |
713 | ||
714 | static int mips_relax_branch; | |
252b5132 | 715 | \f |
4d7206a2 RS |
716 | /* The expansion of many macros depends on the type of symbol that |
717 | they refer to. For example, when generating position-dependent code, | |
718 | a macro that refers to a symbol may have two different expansions, | |
719 | one which uses GP-relative addresses and one which uses absolute | |
720 | addresses. When generating SVR4-style PIC, a macro may have | |
721 | different expansions for local and global symbols. | |
722 | ||
723 | We handle these situations by generating both sequences and putting | |
724 | them in variant frags. In position-dependent code, the first sequence | |
725 | will be the GP-relative one and the second sequence will be the | |
726 | absolute one. In SVR4 PIC, the first sequence will be for global | |
727 | symbols and the second will be for local symbols. | |
728 | ||
584892a6 RS |
729 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
730 | SECOND are the lengths of the two sequences in bytes. These fields | |
731 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
732 | the subtype has the following flags: | |
4d7206a2 | 733 | |
584892a6 RS |
734 | RELAX_USE_SECOND |
735 | Set if it has been decided that we should use the second | |
736 | sequence instead of the first. | |
737 | ||
738 | RELAX_SECOND_LONGER | |
739 | Set in the first variant frag if the macro's second implementation | |
740 | is longer than its first. This refers to the macro as a whole, | |
741 | not an individual relaxation. | |
742 | ||
743 | RELAX_NOMACRO | |
744 | Set in the first variant frag if the macro appeared in a .set nomacro | |
745 | block and if one alternative requires a warning but the other does not. | |
746 | ||
747 | RELAX_DELAY_SLOT | |
748 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
749 | delay slot. | |
4d7206a2 RS |
750 | |
751 | The frag's "opcode" points to the first fixup for relaxable code. | |
752 | ||
753 | Relaxable macros are generated using a sequence such as: | |
754 | ||
755 | relax_start (SYMBOL); | |
756 | ... generate first expansion ... | |
757 | relax_switch (); | |
758 | ... generate second expansion ... | |
759 | relax_end (); | |
760 | ||
761 | The code and fixups for the unwanted alternative are discarded | |
762 | by md_convert_frag. */ | |
584892a6 | 763 | #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) |
4d7206a2 | 764 | |
584892a6 RS |
765 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
766 | #define RELAX_SECOND(X) ((X) & 0xff) | |
767 | #define RELAX_USE_SECOND 0x10000 | |
768 | #define RELAX_SECOND_LONGER 0x20000 | |
769 | #define RELAX_NOMACRO 0x40000 | |
770 | #define RELAX_DELAY_SLOT 0x80000 | |
252b5132 | 771 | |
4a6a3df4 AO |
772 | /* Branch without likely bit. If label is out of range, we turn: |
773 | ||
774 | beq reg1, reg2, label | |
775 | delay slot | |
776 | ||
777 | into | |
778 | ||
779 | bne reg1, reg2, 0f | |
780 | nop | |
781 | j label | |
782 | 0: delay slot | |
783 | ||
784 | with the following opcode replacements: | |
785 | ||
786 | beq <-> bne | |
787 | blez <-> bgtz | |
788 | bltz <-> bgez | |
789 | bc1f <-> bc1t | |
790 | ||
791 | bltzal <-> bgezal (with jal label instead of j label) | |
792 | ||
793 | Even though keeping the delay slot instruction in the delay slot of | |
794 | the branch would be more efficient, it would be very tricky to do | |
795 | correctly, because we'd have to introduce a variable frag *after* | |
796 | the delay slot instruction, and expand that instead. Let's do it | |
797 | the easy way for now, even if the branch-not-taken case now costs | |
798 | one additional instruction. Out-of-range branches are not supposed | |
799 | to be common, anyway. | |
800 | ||
801 | Branch likely. If label is out of range, we turn: | |
802 | ||
803 | beql reg1, reg2, label | |
804 | delay slot (annulled if branch not taken) | |
805 | ||
806 | into | |
807 | ||
808 | beql reg1, reg2, 1f | |
809 | nop | |
810 | beql $0, $0, 2f | |
811 | nop | |
812 | 1: j[al] label | |
813 | delay slot (executed only if branch taken) | |
814 | 2: | |
815 | ||
816 | It would be possible to generate a shorter sequence by losing the | |
817 | likely bit, generating something like: | |
b34976b6 | 818 | |
4a6a3df4 AO |
819 | bne reg1, reg2, 0f |
820 | nop | |
821 | j[al] label | |
822 | delay slot (executed only if branch taken) | |
823 | 0: | |
824 | ||
825 | beql -> bne | |
826 | bnel -> beq | |
827 | blezl -> bgtz | |
828 | bgtzl -> blez | |
829 | bltzl -> bgez | |
830 | bgezl -> bltz | |
831 | bc1fl -> bc1t | |
832 | bc1tl -> bc1f | |
833 | ||
834 | bltzall -> bgezal (with jal label instead of j label) | |
835 | bgezall -> bltzal (ditto) | |
836 | ||
837 | ||
838 | but it's not clear that it would actually improve performance. */ | |
af6ae2ad | 839 | #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \ |
4a6a3df4 AO |
840 | ((relax_substateT) \ |
841 | (0xc0000000 \ | |
842 | | ((toofar) ? 1 : 0) \ | |
843 | | ((link) ? 2 : 0) \ | |
844 | | ((likely) ? 4 : 0) \ | |
af6ae2ad | 845 | | ((uncond) ? 8 : 0))) |
4a6a3df4 | 846 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
4a6a3df4 AO |
847 | #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0) |
848 | #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0) | |
849 | #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0) | |
ae6063d4 | 850 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0) |
4a6a3df4 | 851 | |
252b5132 RH |
852 | /* For mips16 code, we use an entirely different form of relaxation. |
853 | mips16 supports two versions of most instructions which take | |
854 | immediate values: a small one which takes some small value, and a | |
855 | larger one which takes a 16 bit value. Since branches also follow | |
856 | this pattern, relaxing these values is required. | |
857 | ||
858 | We can assemble both mips16 and normal MIPS code in a single | |
859 | object. Therefore, we need to support this type of relaxation at | |
860 | the same time that we support the relaxation described above. We | |
861 | use the high bit of the subtype field to distinguish these cases. | |
862 | ||
863 | The information we store for this type of relaxation is the | |
864 | argument code found in the opcode file for this relocation, whether | |
865 | the user explicitly requested a small or extended form, and whether | |
866 | the relocation is in a jump or jal delay slot. That tells us the | |
867 | size of the value, and how it should be stored. We also store | |
868 | whether the fragment is considered to be extended or not. We also | |
869 | store whether this is known to be a branch to a different section, | |
870 | whether we have tried to relax this frag yet, and whether we have | |
871 | ever extended a PC relative fragment because of a shift count. */ | |
872 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
873 | (0x80000000 \ | |
874 | | ((type) & 0xff) \ | |
875 | | ((small) ? 0x100 : 0) \ | |
876 | | ((ext) ? 0x200 : 0) \ | |
877 | | ((dslot) ? 0x400 : 0) \ | |
878 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 879 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
880 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
881 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
882 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
883 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
884 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
885 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
886 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
887 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
888 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
889 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
890 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 CD |
891 | |
892 | /* Is the given value a sign-extended 32-bit value? */ | |
893 | #define IS_SEXT_32BIT_NUM(x) \ | |
894 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
895 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
896 | ||
897 | /* Is the given value a sign-extended 16-bit value? */ | |
898 | #define IS_SEXT_16BIT_NUM(x) \ | |
899 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
900 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
901 | ||
2051e8c4 MR |
902 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ |
903 | #define IS_ZEXT_32BIT_NUM(x) \ | |
904 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
905 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
906 | ||
bf12938e RS |
907 | /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in |
908 | VALUE << SHIFT. VALUE is evaluated exactly once. */ | |
909 | #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \ | |
910 | (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \ | |
911 | | (((VALUE) & (MASK)) << (SHIFT))) | |
912 | ||
913 | /* Extract bits MASK << SHIFT from STRUCT and shift them right | |
914 | SHIFT places. */ | |
915 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
916 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
917 | ||
918 | /* Change INSN's opcode so that the operand given by FIELD has value VALUE. | |
919 | INSN is a mips_cl_insn structure and VALUE is evaluated exactly once. | |
920 | ||
921 | include/opcode/mips.h specifies operand fields using the macros | |
922 | OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start | |
923 | with "MIPS16OP" instead of "OP". */ | |
924 | #define INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
925 | INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD) | |
926 | #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
927 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
928 | MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD) | |
929 | ||
930 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ | |
931 | #define EXTRACT_OPERAND(FIELD, INSN) \ | |
932 | EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) | |
933 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ | |
934 | EXTRACT_BITS ((INSN).insn_opcode, \ | |
935 | MIPS16OP_MASK_##FIELD, \ | |
936 | MIPS16OP_SH_##FIELD) | |
4d7206a2 RS |
937 | \f |
938 | /* Global variables used when generating relaxable macros. See the | |
939 | comment above RELAX_ENCODE for more details about how relaxation | |
940 | is used. */ | |
941 | static struct { | |
942 | /* 0 if we're not emitting a relaxable macro. | |
943 | 1 if we're emitting the first of the two relaxation alternatives. | |
944 | 2 if we're emitting the second alternative. */ | |
945 | int sequence; | |
946 | ||
947 | /* The first relaxable fixup in the current frag. (In other words, | |
948 | the first fixup that refers to relaxable code.) */ | |
949 | fixS *first_fixup; | |
950 | ||
951 | /* sizes[0] says how many bytes of the first alternative are stored in | |
952 | the current frag. Likewise sizes[1] for the second alternative. */ | |
953 | unsigned int sizes[2]; | |
954 | ||
955 | /* The symbol on which the choice of sequence depends. */ | |
956 | symbolS *symbol; | |
957 | } mips_relax; | |
252b5132 | 958 | \f |
584892a6 RS |
959 | /* Global variables used to decide whether a macro needs a warning. */ |
960 | static struct { | |
961 | /* True if the macro is in a branch delay slot. */ | |
962 | bfd_boolean delay_slot_p; | |
963 | ||
964 | /* For relaxable macros, sizes[0] is the length of the first alternative | |
965 | in bytes and sizes[1] is the length of the second alternative. | |
966 | For non-relaxable macros, both elements give the length of the | |
967 | macro in bytes. */ | |
968 | unsigned int sizes[2]; | |
969 | ||
970 | /* The first variant frag for this macro. */ | |
971 | fragS *first_frag; | |
972 | } mips_macro_warning; | |
973 | \f | |
252b5132 RH |
974 | /* Prototypes for static functions. */ |
975 | ||
17a2f251 | 976 | #define internalError() \ |
252b5132 | 977 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) |
252b5132 RH |
978 | |
979 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
980 | ||
b34976b6 | 981 | static void append_insn |
4d7206a2 | 982 | (struct mips_cl_insn *ip, expressionS *p, bfd_reloc_code_real_type *r); |
7d10b47d | 983 | static void mips_no_prev_insn (void); |
b34976b6 | 984 | static void mips16_macro_build |
67c0d1eb RS |
985 | (expressionS *, const char *, const char *, va_list); |
986 | static void load_register (int, expressionS *, int); | |
584892a6 RS |
987 | static void macro_start (void); |
988 | static void macro_end (void); | |
17a2f251 TS |
989 | static void macro (struct mips_cl_insn * ip); |
990 | static void mips16_macro (struct mips_cl_insn * ip); | |
252b5132 | 991 | #ifdef LOSING_COMPILER |
17a2f251 | 992 | static void macro2 (struct mips_cl_insn * ip); |
252b5132 | 993 | #endif |
17a2f251 TS |
994 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
995 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 996 | static void mips16_immed |
17a2f251 TS |
997 | (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean, |
998 | unsigned long *, bfd_boolean *, unsigned short *); | |
5e0116d5 | 999 | static size_t my_getSmallExpression |
17a2f251 TS |
1000 | (expressionS *, bfd_reloc_code_real_type *, char *); |
1001 | static void my_getExpression (expressionS *, char *); | |
1002 | static void s_align (int); | |
1003 | static void s_change_sec (int); | |
1004 | static void s_change_section (int); | |
1005 | static void s_cons (int); | |
1006 | static void s_float_cons (int); | |
1007 | static void s_mips_globl (int); | |
1008 | static void s_option (int); | |
1009 | static void s_mipsset (int); | |
1010 | static void s_abicalls (int); | |
1011 | static void s_cpload (int); | |
1012 | static void s_cpsetup (int); | |
1013 | static void s_cplocal (int); | |
1014 | static void s_cprestore (int); | |
1015 | static void s_cpreturn (int); | |
1016 | static void s_gpvalue (int); | |
1017 | static void s_gpword (int); | |
1018 | static void s_gpdword (int); | |
1019 | static void s_cpadd (int); | |
1020 | static void s_insn (int); | |
1021 | static void md_obj_begin (void); | |
1022 | static void md_obj_end (void); | |
1023 | static void s_mips_ent (int); | |
1024 | static void s_mips_end (int); | |
1025 | static void s_mips_frame (int); | |
1026 | static void s_mips_mask (int reg_type); | |
1027 | static void s_mips_stab (int); | |
1028 | static void s_mips_weakext (int); | |
1029 | static void s_mips_file (int); | |
1030 | static void s_mips_loc (int); | |
1031 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 1032 | static int relaxed_branch_length (fragS *, asection *, int); |
17a2f251 | 1033 | static int validate_mips_insn (const struct mips_opcode *); |
e7af610e NC |
1034 | |
1035 | /* Table and functions used to map between CPU/ISA names, and | |
1036 | ISA levels, and CPU numbers. */ | |
1037 | ||
e972090a NC |
1038 | struct mips_cpu_info |
1039 | { | |
e7af610e | 1040 | const char *name; /* CPU or ISA name. */ |
ad3fea08 | 1041 | int flags; /* ASEs available, or ISA flag. */ |
e7af610e NC |
1042 | int isa; /* ISA level. */ |
1043 | int cpu; /* CPU number (default CPU if ISA). */ | |
1044 | }; | |
1045 | ||
ad3fea08 TS |
1046 | #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ |
1047 | #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */ | |
1048 | #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */ | |
1049 | #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */ | |
1050 | #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */ | |
1051 | #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */ | |
1052 | ||
17a2f251 TS |
1053 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
1054 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
1055 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 RH |
1056 | \f |
1057 | /* Pseudo-op table. | |
1058 | ||
1059 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
1060 | should be defined here, but are currently unsupported: .alias, | |
1061 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
1062 | ||
1063 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1064 | specific to the type of debugging information being generated, and | |
1065 | should be defined by the object format: .aent, .begin, .bend, | |
1066 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
1067 | .vreg. | |
1068 | ||
1069 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1070 | not MIPS CPU specific, but are also not specific to the object file | |
1071 | format. This file is probably the best place to define them, but | |
1072 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
1073 | .struct. */ | |
1074 | ||
e972090a NC |
1075 | static const pseudo_typeS mips_pseudo_table[] = |
1076 | { | |
beae10d5 | 1077 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1078 | {"option", s_option, 0}, |
1079 | {"set", s_mipsset, 0}, | |
1080 | {"rdata", s_change_sec, 'r'}, | |
1081 | {"sdata", s_change_sec, 's'}, | |
1082 | {"livereg", s_ignore, 0}, | |
1083 | {"abicalls", s_abicalls, 0}, | |
1084 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1085 | {"cpsetup", s_cpsetup, 0}, |
1086 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1087 | {"cprestore", s_cprestore, 0}, |
6478892d TS |
1088 | {"cpreturn", s_cpreturn, 0}, |
1089 | {"gpvalue", s_gpvalue, 0}, | |
252b5132 | 1090 | {"gpword", s_gpword, 0}, |
10181a0d | 1091 | {"gpdword", s_gpdword, 0}, |
252b5132 RH |
1092 | {"cpadd", s_cpadd, 0}, |
1093 | {"insn", s_insn, 0}, | |
1094 | ||
beae10d5 | 1095 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 RH |
1096 | chips. */ |
1097 | {"asciiz", stringer, 1}, | |
1098 | {"bss", s_change_sec, 'b'}, | |
1099 | {"err", s_err, 0}, | |
1100 | {"half", s_cons, 1}, | |
1101 | {"dword", s_cons, 3}, | |
1102 | {"weakext", s_mips_weakext, 0}, | |
1103 | ||
beae10d5 | 1104 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1105 | here for one reason or another. */ |
1106 | {"align", s_align, 0}, | |
1107 | {"byte", s_cons, 0}, | |
1108 | {"data", s_change_sec, 'd'}, | |
1109 | {"double", s_float_cons, 'd'}, | |
1110 | {"float", s_float_cons, 'f'}, | |
1111 | {"globl", s_mips_globl, 0}, | |
1112 | {"global", s_mips_globl, 0}, | |
1113 | {"hword", s_cons, 1}, | |
1114 | {"int", s_cons, 2}, | |
1115 | {"long", s_cons, 2}, | |
1116 | {"octa", s_cons, 4}, | |
1117 | {"quad", s_cons, 3}, | |
cca86cc8 | 1118 | {"section", s_change_section, 0}, |
252b5132 RH |
1119 | {"short", s_cons, 1}, |
1120 | {"single", s_float_cons, 'f'}, | |
1121 | {"stabn", s_mips_stab, 'n'}, | |
1122 | {"text", s_change_sec, 't'}, | |
1123 | {"word", s_cons, 2}, | |
add56521 | 1124 | |
add56521 | 1125 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1126 | |
43841e91 | 1127 | { NULL, NULL, 0 }, |
252b5132 RH |
1128 | }; |
1129 | ||
e972090a NC |
1130 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1131 | { | |
beae10d5 KH |
1132 | /* These pseudo-ops should be defined by the object file format. |
1133 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1134 | {"aent", s_mips_ent, 1}, |
1135 | {"bgnb", s_ignore, 0}, | |
1136 | {"end", s_mips_end, 0}, | |
1137 | {"endb", s_ignore, 0}, | |
1138 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1139 | {"file", s_mips_file, 0}, |
252b5132 RH |
1140 | {"fmask", s_mips_mask, 'F'}, |
1141 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1142 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1143 | {"mask", s_mips_mask, 'R'}, |
1144 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1145 | { NULL, NULL, 0 }, |
252b5132 RH |
1146 | }; |
1147 | ||
17a2f251 | 1148 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1149 | |
1150 | void | |
17a2f251 | 1151 | mips_pop_insert (void) |
252b5132 RH |
1152 | { |
1153 | pop_insert (mips_pseudo_table); | |
1154 | if (! ECOFF_DEBUGGING) | |
1155 | pop_insert (mips_nonecoff_pseudo_table); | |
1156 | } | |
1157 | \f | |
1158 | /* Symbols labelling the current insn. */ | |
1159 | ||
e972090a NC |
1160 | struct insn_label_list |
1161 | { | |
252b5132 RH |
1162 | struct insn_label_list *next; |
1163 | symbolS *label; | |
1164 | }; | |
1165 | ||
1166 | static struct insn_label_list *insn_labels; | |
1167 | static struct insn_label_list *free_insn_labels; | |
1168 | ||
17a2f251 | 1169 | static void mips_clear_insn_labels (void); |
252b5132 RH |
1170 | |
1171 | static inline void | |
17a2f251 | 1172 | mips_clear_insn_labels (void) |
252b5132 RH |
1173 | { |
1174 | register struct insn_label_list **pl; | |
1175 | ||
1176 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1177 | ; | |
1178 | *pl = insn_labels; | |
1179 | insn_labels = NULL; | |
1180 | } | |
1181 | \f | |
1182 | static char *expr_end; | |
1183 | ||
1184 | /* Expressions which appear in instructions. These are set by | |
1185 | mips_ip. */ | |
1186 | ||
1187 | static expressionS imm_expr; | |
5f74bc13 | 1188 | static expressionS imm2_expr; |
252b5132 RH |
1189 | static expressionS offset_expr; |
1190 | ||
1191 | /* Relocs associated with imm_expr and offset_expr. */ | |
1192 | ||
f6688943 TS |
1193 | static bfd_reloc_code_real_type imm_reloc[3] |
1194 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1195 | static bfd_reloc_code_real_type offset_reloc[3] | |
1196 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1197 | |
252b5132 RH |
1198 | /* These are set by mips16_ip if an explicit extension is used. */ |
1199 | ||
b34976b6 | 1200 | static bfd_boolean mips16_small, mips16_ext; |
252b5132 | 1201 | |
7ed4a06a | 1202 | #ifdef OBJ_ELF |
ecb4347a DJ |
1203 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1204 | ECOFF debugging. */ | |
252b5132 RH |
1205 | |
1206 | static segT pdr_seg; | |
7ed4a06a | 1207 | #endif |
252b5132 | 1208 | |
e013f690 TS |
1209 | /* The default target format to use. */ |
1210 | ||
1211 | const char * | |
17a2f251 | 1212 | mips_target_format (void) |
e013f690 TS |
1213 | { |
1214 | switch (OUTPUT_FLAVOR) | |
1215 | { | |
e013f690 TS |
1216 | case bfd_target_ecoff_flavour: |
1217 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1218 | case bfd_target_coff_flavour: | |
1219 | return "pe-mips"; | |
1220 | case bfd_target_elf_flavour: | |
0a44bf69 RS |
1221 | #ifdef TE_VXWORKS |
1222 | if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI) | |
1223 | return (target_big_endian | |
1224 | ? "elf32-bigmips-vxworks" | |
1225 | : "elf32-littlemips-vxworks"); | |
1226 | #endif | |
e013f690 | 1227 | #ifdef TE_TMIPS |
cfe86eaa | 1228 | /* This is traditional mips. */ |
e013f690 | 1229 | return (target_big_endian |
cfe86eaa TS |
1230 | ? (HAVE_64BIT_OBJECTS |
1231 | ? "elf64-tradbigmips" | |
1232 | : (HAVE_NEWABI | |
1233 | ? "elf32-ntradbigmips" : "elf32-tradbigmips")) | |
1234 | : (HAVE_64BIT_OBJECTS | |
1235 | ? "elf64-tradlittlemips" | |
1236 | : (HAVE_NEWABI | |
1237 | ? "elf32-ntradlittlemips" : "elf32-tradlittlemips"))); | |
e013f690 TS |
1238 | #else |
1239 | return (target_big_endian | |
cfe86eaa TS |
1240 | ? (HAVE_64BIT_OBJECTS |
1241 | ? "elf64-bigmips" | |
1242 | : (HAVE_NEWABI | |
1243 | ? "elf32-nbigmips" : "elf32-bigmips")) | |
1244 | : (HAVE_64BIT_OBJECTS | |
1245 | ? "elf64-littlemips" | |
1246 | : (HAVE_NEWABI | |
1247 | ? "elf32-nlittlemips" : "elf32-littlemips"))); | |
e013f690 TS |
1248 | #endif |
1249 | default: | |
1250 | abort (); | |
1251 | return NULL; | |
1252 | } | |
1253 | } | |
1254 | ||
1e915849 RS |
1255 | /* Return the length of instruction INSN. */ |
1256 | ||
1257 | static inline unsigned int | |
1258 | insn_length (const struct mips_cl_insn *insn) | |
1259 | { | |
1260 | if (!mips_opts.mips16) | |
1261 | return 4; | |
1262 | return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2; | |
1263 | } | |
1264 | ||
1265 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
1266 | ||
1267 | static void | |
1268 | create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) | |
1269 | { | |
1270 | size_t i; | |
1271 | ||
1272 | insn->insn_mo = mo; | |
1273 | insn->use_extend = FALSE; | |
1274 | insn->extend = 0; | |
1275 | insn->insn_opcode = mo->match; | |
1276 | insn->frag = NULL; | |
1277 | insn->where = 0; | |
1278 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1279 | insn->fixp[i] = NULL; | |
1280 | insn->fixed_p = (mips_opts.noreorder > 0); | |
1281 | insn->noreorder_p = (mips_opts.noreorder > 0); | |
1282 | insn->mips16_absolute_jump_p = 0; | |
1283 | } | |
1284 | ||
1285 | /* Install INSN at the location specified by its "frag" and "where" fields. */ | |
1286 | ||
1287 | static void | |
1288 | install_insn (const struct mips_cl_insn *insn) | |
1289 | { | |
1290 | char *f = insn->frag->fr_literal + insn->where; | |
1291 | if (!mips_opts.mips16) | |
1292 | md_number_to_chars (f, insn->insn_opcode, 4); | |
1293 | else if (insn->mips16_absolute_jump_p) | |
1294 | { | |
1295 | md_number_to_chars (f, insn->insn_opcode >> 16, 2); | |
1296 | md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2); | |
1297 | } | |
1298 | else | |
1299 | { | |
1300 | if (insn->use_extend) | |
1301 | { | |
1302 | md_number_to_chars (f, 0xf000 | insn->extend, 2); | |
1303 | f += 2; | |
1304 | } | |
1305 | md_number_to_chars (f, insn->insn_opcode, 2); | |
1306 | } | |
1307 | } | |
1308 | ||
1309 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
1310 | and install the opcode in the new location. */ | |
1311 | ||
1312 | static void | |
1313 | move_insn (struct mips_cl_insn *insn, fragS *frag, long where) | |
1314 | { | |
1315 | size_t i; | |
1316 | ||
1317 | insn->frag = frag; | |
1318 | insn->where = where; | |
1319 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1320 | if (insn->fixp[i] != NULL) | |
1321 | { | |
1322 | insn->fixp[i]->fx_frag = frag; | |
1323 | insn->fixp[i]->fx_where = where; | |
1324 | } | |
1325 | install_insn (insn); | |
1326 | } | |
1327 | ||
1328 | /* Add INSN to the end of the output. */ | |
1329 | ||
1330 | static void | |
1331 | add_fixed_insn (struct mips_cl_insn *insn) | |
1332 | { | |
1333 | char *f = frag_more (insn_length (insn)); | |
1334 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
1335 | } | |
1336 | ||
1337 | /* Start a variant frag and move INSN to the start of the variant part, | |
1338 | marking it as fixed. The other arguments are as for frag_var. */ | |
1339 | ||
1340 | static void | |
1341 | add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, | |
1342 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
1343 | { | |
1344 | frag_grow (max_chars); | |
1345 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
1346 | insn->fixed_p = 1; | |
1347 | frag_var (rs_machine_dependent, max_chars, var, | |
1348 | subtype, symbol, offset, NULL); | |
1349 | } | |
1350 | ||
1351 | /* Insert N copies of INSN into the history buffer, starting at | |
1352 | position FIRST. Neither FIRST nor N need to be clipped. */ | |
1353 | ||
1354 | static void | |
1355 | insert_into_history (unsigned int first, unsigned int n, | |
1356 | const struct mips_cl_insn *insn) | |
1357 | { | |
1358 | if (mips_relax.sequence != 2) | |
1359 | { | |
1360 | unsigned int i; | |
1361 | ||
1362 | for (i = ARRAY_SIZE (history); i-- > first;) | |
1363 | if (i >= first + n) | |
1364 | history[i] = history[i - n]; | |
1365 | else | |
1366 | history[i] = *insn; | |
1367 | } | |
1368 | } | |
1369 | ||
1370 | /* Emit a nop instruction, recording it in the history buffer. */ | |
1371 | ||
1372 | static void | |
1373 | emit_nop (void) | |
1374 | { | |
1375 | add_fixed_insn (NOP_INSN); | |
1376 | insert_into_history (0, 1, NOP_INSN); | |
1377 | } | |
1378 | ||
71400594 RS |
1379 | /* Initialize vr4120_conflicts. There is a bit of duplication here: |
1380 | the idea is to make it obvious at a glance that each errata is | |
1381 | included. */ | |
1382 | ||
1383 | static void | |
1384 | init_vr4120_conflicts (void) | |
1385 | { | |
1386 | #define CONFLICT(FIRST, SECOND) \ | |
1387 | vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND | |
1388 | ||
1389 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
1390 | CONFLICT (MACC, DIV); | |
1391 | CONFLICT (DMACC, DIV); | |
1392 | ||
1393 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ | |
1394 | CONFLICT (DMULT, DMULT); | |
1395 | CONFLICT (DMULT, DMACC); | |
1396 | CONFLICT (DMACC, DMULT); | |
1397 | CONFLICT (DMACC, DMACC); | |
1398 | ||
1399 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
1400 | CONFLICT (MACC, MTHILO); | |
1401 | CONFLICT (DMACC, MTHILO); | |
1402 | ||
1403 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU | |
1404 | instruction is executed immediately after a MACC or DMACC | |
1405 | instruction, the result of [either instruction] is incorrect." */ | |
1406 | CONFLICT (MACC, MULT); | |
1407 | CONFLICT (MACC, DMULT); | |
1408 | CONFLICT (DMACC, MULT); | |
1409 | CONFLICT (DMACC, DMULT); | |
1410 | ||
1411 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
1412 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
1413 | DDIV or DDIVU instruction, the result of the MACC or | |
1414 | DMACC instruction is incorrect.". */ | |
1415 | CONFLICT (DMULT, MACC); | |
1416 | CONFLICT (DMULT, DMACC); | |
1417 | CONFLICT (DIV, MACC); | |
1418 | CONFLICT (DIV, DMACC); | |
1419 | ||
1420 | #undef CONFLICT | |
1421 | } | |
1422 | ||
707bfff6 TS |
1423 | struct regname { |
1424 | const char *name; | |
1425 | unsigned int num; | |
1426 | }; | |
1427 | ||
1428 | #define RTYPE_MASK 0x1ff00 | |
1429 | #define RTYPE_NUM 0x00100 | |
1430 | #define RTYPE_FPU 0x00200 | |
1431 | #define RTYPE_FCC 0x00400 | |
1432 | #define RTYPE_VEC 0x00800 | |
1433 | #define RTYPE_GP 0x01000 | |
1434 | #define RTYPE_CP0 0x02000 | |
1435 | #define RTYPE_PC 0x04000 | |
1436 | #define RTYPE_ACC 0x08000 | |
1437 | #define RTYPE_CCC 0x10000 | |
1438 | #define RNUM_MASK 0x000ff | |
1439 | #define RWARN 0x80000 | |
1440 | ||
1441 | #define GENERIC_REGISTER_NUMBERS \ | |
1442 | {"$0", RTYPE_NUM | 0}, \ | |
1443 | {"$1", RTYPE_NUM | 1}, \ | |
1444 | {"$2", RTYPE_NUM | 2}, \ | |
1445 | {"$3", RTYPE_NUM | 3}, \ | |
1446 | {"$4", RTYPE_NUM | 4}, \ | |
1447 | {"$5", RTYPE_NUM | 5}, \ | |
1448 | {"$6", RTYPE_NUM | 6}, \ | |
1449 | {"$7", RTYPE_NUM | 7}, \ | |
1450 | {"$8", RTYPE_NUM | 8}, \ | |
1451 | {"$9", RTYPE_NUM | 9}, \ | |
1452 | {"$10", RTYPE_NUM | 10}, \ | |
1453 | {"$11", RTYPE_NUM | 11}, \ | |
1454 | {"$12", RTYPE_NUM | 12}, \ | |
1455 | {"$13", RTYPE_NUM | 13}, \ | |
1456 | {"$14", RTYPE_NUM | 14}, \ | |
1457 | {"$15", RTYPE_NUM | 15}, \ | |
1458 | {"$16", RTYPE_NUM | 16}, \ | |
1459 | {"$17", RTYPE_NUM | 17}, \ | |
1460 | {"$18", RTYPE_NUM | 18}, \ | |
1461 | {"$19", RTYPE_NUM | 19}, \ | |
1462 | {"$20", RTYPE_NUM | 20}, \ | |
1463 | {"$21", RTYPE_NUM | 21}, \ | |
1464 | {"$22", RTYPE_NUM | 22}, \ | |
1465 | {"$23", RTYPE_NUM | 23}, \ | |
1466 | {"$24", RTYPE_NUM | 24}, \ | |
1467 | {"$25", RTYPE_NUM | 25}, \ | |
1468 | {"$26", RTYPE_NUM | 26}, \ | |
1469 | {"$27", RTYPE_NUM | 27}, \ | |
1470 | {"$28", RTYPE_NUM | 28}, \ | |
1471 | {"$29", RTYPE_NUM | 29}, \ | |
1472 | {"$30", RTYPE_NUM | 30}, \ | |
1473 | {"$31", RTYPE_NUM | 31} | |
1474 | ||
1475 | #define FPU_REGISTER_NAMES \ | |
1476 | {"$f0", RTYPE_FPU | 0}, \ | |
1477 | {"$f1", RTYPE_FPU | 1}, \ | |
1478 | {"$f2", RTYPE_FPU | 2}, \ | |
1479 | {"$f3", RTYPE_FPU | 3}, \ | |
1480 | {"$f4", RTYPE_FPU | 4}, \ | |
1481 | {"$f5", RTYPE_FPU | 5}, \ | |
1482 | {"$f6", RTYPE_FPU | 6}, \ | |
1483 | {"$f7", RTYPE_FPU | 7}, \ | |
1484 | {"$f8", RTYPE_FPU | 8}, \ | |
1485 | {"$f9", RTYPE_FPU | 9}, \ | |
1486 | {"$f10", RTYPE_FPU | 10}, \ | |
1487 | {"$f11", RTYPE_FPU | 11}, \ | |
1488 | {"$f12", RTYPE_FPU | 12}, \ | |
1489 | {"$f13", RTYPE_FPU | 13}, \ | |
1490 | {"$f14", RTYPE_FPU | 14}, \ | |
1491 | {"$f15", RTYPE_FPU | 15}, \ | |
1492 | {"$f16", RTYPE_FPU | 16}, \ | |
1493 | {"$f17", RTYPE_FPU | 17}, \ | |
1494 | {"$f18", RTYPE_FPU | 18}, \ | |
1495 | {"$f19", RTYPE_FPU | 19}, \ | |
1496 | {"$f20", RTYPE_FPU | 20}, \ | |
1497 | {"$f21", RTYPE_FPU | 21}, \ | |
1498 | {"$f22", RTYPE_FPU | 22}, \ | |
1499 | {"$f23", RTYPE_FPU | 23}, \ | |
1500 | {"$f24", RTYPE_FPU | 24}, \ | |
1501 | {"$f25", RTYPE_FPU | 25}, \ | |
1502 | {"$f26", RTYPE_FPU | 26}, \ | |
1503 | {"$f27", RTYPE_FPU | 27}, \ | |
1504 | {"$f28", RTYPE_FPU | 28}, \ | |
1505 | {"$f29", RTYPE_FPU | 29}, \ | |
1506 | {"$f30", RTYPE_FPU | 30}, \ | |
1507 | {"$f31", RTYPE_FPU | 31} | |
1508 | ||
1509 | #define FPU_CONDITION_CODE_NAMES \ | |
1510 | {"$fcc0", RTYPE_FCC | 0}, \ | |
1511 | {"$fcc1", RTYPE_FCC | 1}, \ | |
1512 | {"$fcc2", RTYPE_FCC | 2}, \ | |
1513 | {"$fcc3", RTYPE_FCC | 3}, \ | |
1514 | {"$fcc4", RTYPE_FCC | 4}, \ | |
1515 | {"$fcc5", RTYPE_FCC | 5}, \ | |
1516 | {"$fcc6", RTYPE_FCC | 6}, \ | |
1517 | {"$fcc7", RTYPE_FCC | 7} | |
1518 | ||
1519 | #define COPROC_CONDITION_CODE_NAMES \ | |
1520 | {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \ | |
1521 | {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \ | |
1522 | {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \ | |
1523 | {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \ | |
1524 | {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \ | |
1525 | {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \ | |
1526 | {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \ | |
1527 | {"$cc7", RTYPE_FCC | RTYPE_CCC | 7} | |
1528 | ||
1529 | #define N32N64_SYMBOLIC_REGISTER_NAMES \ | |
1530 | {"$a4", RTYPE_GP | 8}, \ | |
1531 | {"$a5", RTYPE_GP | 9}, \ | |
1532 | {"$a6", RTYPE_GP | 10}, \ | |
1533 | {"$a7", RTYPE_GP | 11}, \ | |
1534 | {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \ | |
1535 | {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \ | |
1536 | {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \ | |
1537 | {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \ | |
1538 | {"$t0", RTYPE_GP | 12}, \ | |
1539 | {"$t1", RTYPE_GP | 13}, \ | |
1540 | {"$t2", RTYPE_GP | 14}, \ | |
1541 | {"$t3", RTYPE_GP | 15} | |
1542 | ||
1543 | #define O32_SYMBOLIC_REGISTER_NAMES \ | |
1544 | {"$t0", RTYPE_GP | 8}, \ | |
1545 | {"$t1", RTYPE_GP | 9}, \ | |
1546 | {"$t2", RTYPE_GP | 10}, \ | |
1547 | {"$t3", RTYPE_GP | 11}, \ | |
1548 | {"$t4", RTYPE_GP | 12}, \ | |
1549 | {"$t5", RTYPE_GP | 13}, \ | |
1550 | {"$t6", RTYPE_GP | 14}, \ | |
1551 | {"$t7", RTYPE_GP | 15}, \ | |
1552 | {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \ | |
1553 | {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \ | |
1554 | {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \ | |
1555 | {"$ta3", RTYPE_GP | 15} /* alias for $t7 */ | |
1556 | ||
1557 | /* Remaining symbolic register names */ | |
1558 | #define SYMBOLIC_REGISTER_NAMES \ | |
1559 | {"$zero", RTYPE_GP | 0}, \ | |
1560 | {"$at", RTYPE_GP | 1}, \ | |
1561 | {"$AT", RTYPE_GP | 1}, \ | |
1562 | {"$v0", RTYPE_GP | 2}, \ | |
1563 | {"$v1", RTYPE_GP | 3}, \ | |
1564 | {"$a0", RTYPE_GP | 4}, \ | |
1565 | {"$a1", RTYPE_GP | 5}, \ | |
1566 | {"$a2", RTYPE_GP | 6}, \ | |
1567 | {"$a3", RTYPE_GP | 7}, \ | |
1568 | {"$s0", RTYPE_GP | 16}, \ | |
1569 | {"$s1", RTYPE_GP | 17}, \ | |
1570 | {"$s2", RTYPE_GP | 18}, \ | |
1571 | {"$s3", RTYPE_GP | 19}, \ | |
1572 | {"$s4", RTYPE_GP | 20}, \ | |
1573 | {"$s5", RTYPE_GP | 21}, \ | |
1574 | {"$s6", RTYPE_GP | 22}, \ | |
1575 | {"$s7", RTYPE_GP | 23}, \ | |
1576 | {"$t8", RTYPE_GP | 24}, \ | |
1577 | {"$t9", RTYPE_GP | 25}, \ | |
1578 | {"$k0", RTYPE_GP | 26}, \ | |
1579 | {"$kt0", RTYPE_GP | 26}, \ | |
1580 | {"$k1", RTYPE_GP | 27}, \ | |
1581 | {"$kt1", RTYPE_GP | 27}, \ | |
1582 | {"$gp", RTYPE_GP | 28}, \ | |
1583 | {"$sp", RTYPE_GP | 29}, \ | |
1584 | {"$s8", RTYPE_GP | 30}, \ | |
1585 | {"$fp", RTYPE_GP | 30}, \ | |
1586 | {"$ra", RTYPE_GP | 31} | |
1587 | ||
1588 | #define MIPS16_SPECIAL_REGISTER_NAMES \ | |
1589 | {"$pc", RTYPE_PC | 0} | |
1590 | ||
1591 | #define MDMX_VECTOR_REGISTER_NAMES \ | |
1592 | /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \ | |
1593 | /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \ | |
1594 | {"$v2", RTYPE_VEC | 2}, \ | |
1595 | {"$v3", RTYPE_VEC | 3}, \ | |
1596 | {"$v4", RTYPE_VEC | 4}, \ | |
1597 | {"$v5", RTYPE_VEC | 5}, \ | |
1598 | {"$v6", RTYPE_VEC | 6}, \ | |
1599 | {"$v7", RTYPE_VEC | 7}, \ | |
1600 | {"$v8", RTYPE_VEC | 8}, \ | |
1601 | {"$v9", RTYPE_VEC | 9}, \ | |
1602 | {"$v10", RTYPE_VEC | 10}, \ | |
1603 | {"$v11", RTYPE_VEC | 11}, \ | |
1604 | {"$v12", RTYPE_VEC | 12}, \ | |
1605 | {"$v13", RTYPE_VEC | 13}, \ | |
1606 | {"$v14", RTYPE_VEC | 14}, \ | |
1607 | {"$v15", RTYPE_VEC | 15}, \ | |
1608 | {"$v16", RTYPE_VEC | 16}, \ | |
1609 | {"$v17", RTYPE_VEC | 17}, \ | |
1610 | {"$v18", RTYPE_VEC | 18}, \ | |
1611 | {"$v19", RTYPE_VEC | 19}, \ | |
1612 | {"$v20", RTYPE_VEC | 20}, \ | |
1613 | {"$v21", RTYPE_VEC | 21}, \ | |
1614 | {"$v22", RTYPE_VEC | 22}, \ | |
1615 | {"$v23", RTYPE_VEC | 23}, \ | |
1616 | {"$v24", RTYPE_VEC | 24}, \ | |
1617 | {"$v25", RTYPE_VEC | 25}, \ | |
1618 | {"$v26", RTYPE_VEC | 26}, \ | |
1619 | {"$v27", RTYPE_VEC | 27}, \ | |
1620 | {"$v28", RTYPE_VEC | 28}, \ | |
1621 | {"$v29", RTYPE_VEC | 29}, \ | |
1622 | {"$v30", RTYPE_VEC | 30}, \ | |
1623 | {"$v31", RTYPE_VEC | 31} | |
1624 | ||
1625 | #define MIPS_DSP_ACCUMULATOR_NAMES \ | |
1626 | {"$ac0", RTYPE_ACC | 0}, \ | |
1627 | {"$ac1", RTYPE_ACC | 1}, \ | |
1628 | {"$ac2", RTYPE_ACC | 2}, \ | |
1629 | {"$ac3", RTYPE_ACC | 3} | |
1630 | ||
1631 | static const struct regname reg_names[] = { | |
1632 | GENERIC_REGISTER_NUMBERS, | |
1633 | FPU_REGISTER_NAMES, | |
1634 | FPU_CONDITION_CODE_NAMES, | |
1635 | COPROC_CONDITION_CODE_NAMES, | |
1636 | ||
1637 | /* The $txx registers depends on the abi, | |
1638 | these will be added later into the symbol table from | |
1639 | one of the tables below once mips_abi is set after | |
1640 | parsing of arguments from the command line. */ | |
1641 | SYMBOLIC_REGISTER_NAMES, | |
1642 | ||
1643 | MIPS16_SPECIAL_REGISTER_NAMES, | |
1644 | MDMX_VECTOR_REGISTER_NAMES, | |
1645 | MIPS_DSP_ACCUMULATOR_NAMES, | |
1646 | {0, 0} | |
1647 | }; | |
1648 | ||
1649 | static const struct regname reg_names_o32[] = { | |
1650 | O32_SYMBOLIC_REGISTER_NAMES, | |
1651 | {0, 0} | |
1652 | }; | |
1653 | ||
1654 | static const struct regname reg_names_n32n64[] = { | |
1655 | N32N64_SYMBOLIC_REGISTER_NAMES, | |
1656 | {0, 0} | |
1657 | }; | |
1658 | ||
1659 | static int | |
1660 | reg_lookup (char **s, unsigned int types, unsigned int *regnop) | |
1661 | { | |
1662 | symbolS *symbolP; | |
1663 | char *e; | |
1664 | char save_c; | |
1665 | int reg = -1; | |
1666 | ||
1667 | /* Find end of name. */ | |
1668 | e = *s; | |
1669 | if (is_name_beginner (*e)) | |
1670 | ++e; | |
1671 | while (is_part_of_name (*e)) | |
1672 | ++e; | |
1673 | ||
1674 | /* Terminate name. */ | |
1675 | save_c = *e; | |
1676 | *e = '\0'; | |
1677 | ||
1678 | /* Look for a register symbol. */ | |
1679 | if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section) | |
1680 | { | |
1681 | int r = S_GET_VALUE (symbolP); | |
1682 | if (r & types) | |
1683 | reg = r & RNUM_MASK; | |
1684 | else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2)) | |
1685 | /* Convert GP reg $v0/1 to MDMX reg $v0/1! */ | |
1686 | reg = (r & RNUM_MASK) - 2; | |
1687 | } | |
1688 | /* Else see if this is a register defined in an itbl entry. */ | |
1689 | else if ((types & RTYPE_GP) && itbl_have_entries) | |
1690 | { | |
1691 | char *n = *s; | |
1692 | unsigned long r; | |
1693 | ||
1694 | if (*n == '$') | |
1695 | ++n; | |
1696 | if (itbl_get_reg_val (n, &r)) | |
1697 | reg = r & RNUM_MASK; | |
1698 | } | |
1699 | ||
1700 | /* Advance to next token if a register was recognised. */ | |
1701 | if (reg >= 0) | |
1702 | *s = e; | |
1703 | else if (types & RWARN) | |
1704 | as_warn ("Unrecognized register name `%s'", *s); | |
1705 | ||
1706 | *e = save_c; | |
1707 | if (regnop) | |
1708 | *regnop = reg; | |
1709 | return reg >= 0; | |
1710 | } | |
1711 | ||
1712 | /* This function is called once, at assembler startup time. It should set up | |
1713 | all the tables, etc. that the MD part of the assembler will need. */ | |
156c2f8b | 1714 | |
252b5132 | 1715 | void |
17a2f251 | 1716 | md_begin (void) |
252b5132 | 1717 | { |
252b5132 | 1718 | register const char *retval = NULL; |
156c2f8b | 1719 | int i = 0; |
252b5132 | 1720 | int broken = 0; |
1f25f5d3 | 1721 | |
0a44bf69 RS |
1722 | if (mips_pic != NO_PIC) |
1723 | { | |
1724 | if (g_switch_seen && g_switch_value != 0) | |
1725 | as_bad (_("-G may not be used in position-independent code")); | |
1726 | g_switch_value = 0; | |
1727 | } | |
1728 | ||
fef14a42 | 1729 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) |
252b5132 RH |
1730 | as_warn (_("Could not set architecture and machine")); |
1731 | ||
252b5132 RH |
1732 | op_hash = hash_new (); |
1733 | ||
1734 | for (i = 0; i < NUMOPCODES;) | |
1735 | { | |
1736 | const char *name = mips_opcodes[i].name; | |
1737 | ||
17a2f251 | 1738 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
1739 | if (retval != NULL) |
1740 | { | |
1741 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
1742 | mips_opcodes[i].name, retval); | |
1743 | /* Probably a memory allocation problem? Give up now. */ | |
1744 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1745 | } | |
1746 | do | |
1747 | { | |
1748 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
1749 | { | |
1750 | if (!validate_mips_insn (&mips_opcodes[i])) | |
1751 | broken = 1; | |
1e915849 RS |
1752 | if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
1753 | { | |
1754 | create_insn (&nop_insn, mips_opcodes + i); | |
1755 | nop_insn.fixed_p = 1; | |
1756 | } | |
252b5132 RH |
1757 | } |
1758 | ++i; | |
1759 | } | |
1760 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
1761 | } | |
1762 | ||
1763 | mips16_op_hash = hash_new (); | |
1764 | ||
1765 | i = 0; | |
1766 | while (i < bfd_mips16_num_opcodes) | |
1767 | { | |
1768 | const char *name = mips16_opcodes[i].name; | |
1769 | ||
17a2f251 | 1770 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
1771 | if (retval != NULL) |
1772 | as_fatal (_("internal: can't hash `%s': %s"), | |
1773 | mips16_opcodes[i].name, retval); | |
1774 | do | |
1775 | { | |
1776 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1777 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1778 | != mips16_opcodes[i].match)) | |
1779 | { | |
1780 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
1781 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1782 | broken = 1; | |
1783 | } | |
1e915849 RS |
1784 | if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
1785 | { | |
1786 | create_insn (&mips16_nop_insn, mips16_opcodes + i); | |
1787 | mips16_nop_insn.fixed_p = 1; | |
1788 | } | |
252b5132 RH |
1789 | ++i; |
1790 | } | |
1791 | while (i < bfd_mips16_num_opcodes | |
1792 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1793 | } | |
1794 | ||
1795 | if (broken) | |
1796 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1797 | ||
1798 | /* We add all the general register names to the symbol table. This | |
1799 | helps us detect invalid uses of them. */ | |
707bfff6 TS |
1800 | for (i = 0; reg_names[i].name; i++) |
1801 | symbol_table_insert (symbol_new (reg_names[i].name, reg_section, | |
1802 | reg_names[i].num, // & RNUM_MASK, | |
1803 | &zero_address_frag)); | |
1804 | if (HAVE_NEWABI) | |
1805 | for (i = 0; reg_names_n32n64[i].name; i++) | |
1806 | symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section, | |
1807 | reg_names_n32n64[i].num, // & RNUM_MASK, | |
252b5132 | 1808 | &zero_address_frag)); |
707bfff6 TS |
1809 | else |
1810 | for (i = 0; reg_names_o32[i].name; i++) | |
1811 | symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section, | |
1812 | reg_names_o32[i].num, // & RNUM_MASK, | |
6047c971 | 1813 | &zero_address_frag)); |
6047c971 | 1814 | |
7d10b47d | 1815 | mips_no_prev_insn (); |
252b5132 RH |
1816 | |
1817 | mips_gprmask = 0; | |
1818 | mips_cprmask[0] = 0; | |
1819 | mips_cprmask[1] = 0; | |
1820 | mips_cprmask[2] = 0; | |
1821 | mips_cprmask[3] = 0; | |
1822 | ||
1823 | /* set the default alignment for the text section (2**2) */ | |
1824 | record_alignment (text_section, 2); | |
1825 | ||
4d0d148d | 1826 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 | 1827 | |
707bfff6 | 1828 | #ifdef OBJ_ELF |
252b5132 RH |
1829 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
1830 | { | |
0a44bf69 RS |
1831 | /* On a native system other than VxWorks, sections must be aligned |
1832 | to 16 byte boundaries. When configured for an embedded ELF | |
1833 | target, we don't bother. */ | |
1834 | if (strcmp (TARGET_OS, "elf") != 0 | |
1835 | && strcmp (TARGET_OS, "vxworks") != 0) | |
252b5132 RH |
1836 | { |
1837 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
1838 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
1839 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
1840 | } | |
1841 | ||
1842 | /* Create a .reginfo section for register masks and a .mdebug | |
1843 | section for debugging information. */ | |
1844 | { | |
1845 | segT seg; | |
1846 | subsegT subseg; | |
1847 | flagword flags; | |
1848 | segT sec; | |
1849 | ||
1850 | seg = now_seg; | |
1851 | subseg = now_subseg; | |
1852 | ||
1853 | /* The ABI says this section should be loaded so that the | |
1854 | running program can access it. However, we don't load it | |
1855 | if we are configured for an embedded target */ | |
1856 | flags = SEC_READONLY | SEC_DATA; | |
1857 | if (strcmp (TARGET_OS, "elf") != 0) | |
1858 | flags |= SEC_ALLOC | SEC_LOAD; | |
1859 | ||
316f5878 | 1860 | if (mips_abi != N64_ABI) |
252b5132 RH |
1861 | { |
1862 | sec = subseg_new (".reginfo", (subsegT) 0); | |
1863 | ||
195325d2 TS |
1864 | bfd_set_section_flags (stdoutput, sec, flags); |
1865 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 1866 | |
252b5132 | 1867 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
252b5132 RH |
1868 | } |
1869 | else | |
1870 | { | |
1871 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
1872 | .reginfo section. */ | |
1873 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
1874 | bfd_set_section_flags (stdoutput, sec, flags); |
1875 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 | 1876 | |
252b5132 RH |
1877 | /* Set up the option header. */ |
1878 | { | |
1879 | Elf_Internal_Options opthdr; | |
1880 | char *f; | |
1881 | ||
1882 | opthdr.kind = ODK_REGINFO; | |
1883 | opthdr.size = (sizeof (Elf_External_Options) | |
1884 | + sizeof (Elf64_External_RegInfo)); | |
1885 | opthdr.section = 0; | |
1886 | opthdr.info = 0; | |
1887 | f = frag_more (sizeof (Elf_External_Options)); | |
1888 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
1889 | (Elf_External_Options *) f); | |
1890 | ||
1891 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
1892 | } | |
252b5132 RH |
1893 | } |
1894 | ||
1895 | if (ECOFF_DEBUGGING) | |
1896 | { | |
1897 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1898 | (void) bfd_set_section_flags (stdoutput, sec, | |
1899 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1900 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1901 | } | |
dcd410fe | 1902 | else if (OUTPUT_FLAVOR == bfd_target_elf_flavour && mips_flag_pdr) |
ecb4347a DJ |
1903 | { |
1904 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
1905 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
1906 | SEC_READONLY | SEC_RELOC | |
1907 | | SEC_DEBUGGING); | |
1908 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
1909 | } | |
252b5132 RH |
1910 | |
1911 | subseg_set (seg, subseg); | |
1912 | } | |
1913 | } | |
707bfff6 | 1914 | #endif /* OBJ_ELF */ |
252b5132 RH |
1915 | |
1916 | if (! ECOFF_DEBUGGING) | |
1917 | md_obj_begin (); | |
71400594 RS |
1918 | |
1919 | if (mips_fix_vr4120) | |
1920 | init_vr4120_conflicts (); | |
252b5132 RH |
1921 | } |
1922 | ||
1923 | void | |
17a2f251 | 1924 | md_mips_end (void) |
252b5132 RH |
1925 | { |
1926 | if (! ECOFF_DEBUGGING) | |
1927 | md_obj_end (); | |
1928 | } | |
1929 | ||
1930 | void | |
17a2f251 | 1931 | md_assemble (char *str) |
252b5132 RH |
1932 | { |
1933 | struct mips_cl_insn insn; | |
f6688943 TS |
1934 | bfd_reloc_code_real_type unused_reloc[3] |
1935 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
1936 | |
1937 | imm_expr.X_op = O_absent; | |
5f74bc13 | 1938 | imm2_expr.X_op = O_absent; |
252b5132 | 1939 | offset_expr.X_op = O_absent; |
f6688943 TS |
1940 | imm_reloc[0] = BFD_RELOC_UNUSED; |
1941 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
1942 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
1943 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
1944 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
1945 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
1946 | |
1947 | if (mips_opts.mips16) | |
1948 | mips16_ip (str, &insn); | |
1949 | else | |
1950 | { | |
1951 | mips_ip (str, &insn); | |
beae10d5 KH |
1952 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
1953 | str, insn.insn_opcode)); | |
252b5132 RH |
1954 | } |
1955 | ||
1956 | if (insn_error) | |
1957 | { | |
1958 | as_bad ("%s `%s'", insn_error, str); | |
1959 | return; | |
1960 | } | |
1961 | ||
1962 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
1963 | { | |
584892a6 | 1964 | macro_start (); |
252b5132 RH |
1965 | if (mips_opts.mips16) |
1966 | mips16_macro (&insn); | |
1967 | else | |
1968 | macro (&insn); | |
584892a6 | 1969 | macro_end (); |
252b5132 RH |
1970 | } |
1971 | else | |
1972 | { | |
1973 | if (imm_expr.X_op != O_absent) | |
4d7206a2 | 1974 | append_insn (&insn, &imm_expr, imm_reloc); |
252b5132 | 1975 | else if (offset_expr.X_op != O_absent) |
4d7206a2 | 1976 | append_insn (&insn, &offset_expr, offset_reloc); |
252b5132 | 1977 | else |
4d7206a2 | 1978 | append_insn (&insn, NULL, unused_reloc); |
252b5132 RH |
1979 | } |
1980 | } | |
1981 | ||
5919d012 | 1982 | /* Return true if the given relocation might need a matching %lo(). |
0a44bf69 RS |
1983 | This is only "might" because SVR4 R_MIPS_GOT16 relocations only |
1984 | need a matching %lo() when applied to local symbols. */ | |
5919d012 RS |
1985 | |
1986 | static inline bfd_boolean | |
17a2f251 | 1987 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 1988 | { |
3b91255e RS |
1989 | return (HAVE_IN_PLACE_ADDENDS |
1990 | && (reloc == BFD_RELOC_HI16_S | |
0a44bf69 RS |
1991 | || reloc == BFD_RELOC_MIPS16_HI16_S |
1992 | /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo(); | |
1993 | all GOT16 relocations evaluate to "G". */ | |
1994 | || (reloc == BFD_RELOC_MIPS_GOT16 && mips_pic != VXWORKS_PIC))); | |
5919d012 RS |
1995 | } |
1996 | ||
1997 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
1998 | relocation. */ | |
1999 | ||
2000 | static inline bfd_boolean | |
17a2f251 | 2001 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
2002 | { |
2003 | return (fixp->fx_next != NULL | |
d6f16593 MR |
2004 | && (fixp->fx_next->fx_r_type == BFD_RELOC_LO16 |
2005 | || fixp->fx_next->fx_r_type == BFD_RELOC_MIPS16_LO16) | |
5919d012 RS |
2006 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
2007 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
2008 | } | |
2009 | ||
252b5132 RH |
2010 | /* See whether instruction IP reads register REG. CLASS is the type |
2011 | of register. */ | |
2012 | ||
2013 | static int | |
71400594 | 2014 | insn_uses_reg (const struct mips_cl_insn *ip, unsigned int reg, |
17a2f251 | 2015 | enum mips_regclass class) |
252b5132 RH |
2016 | { |
2017 | if (class == MIPS16_REG) | |
2018 | { | |
2019 | assert (mips_opts.mips16); | |
2020 | reg = mips16_to_32_reg_map[reg]; | |
2021 | class = MIPS_GR_REG; | |
2022 | } | |
2023 | ||
85b51719 TS |
2024 | /* Don't report on general register ZERO, since it never changes. */ |
2025 | if (class == MIPS_GR_REG && reg == ZERO) | |
252b5132 RH |
2026 | return 0; |
2027 | ||
2028 | if (class == MIPS_FP_REG) | |
2029 | { | |
2030 | assert (! mips_opts.mips16); | |
2031 | /* If we are called with either $f0 or $f1, we must check $f0. | |
2032 | This is not optimal, because it will introduce an unnecessary | |
2033 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
2034 | need to distinguish reading both $f0 and $f1 or just one of | |
2035 | them. Note that we don't have to check the other way, | |
2036 | because there is no instruction that sets both $f0 and $f1 | |
2037 | and requires a delay. */ | |
2038 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
bf12938e | 2039 | && ((EXTRACT_OPERAND (FS, *ip) & ~(unsigned) 1) |
252b5132 RH |
2040 | == (reg &~ (unsigned) 1))) |
2041 | return 1; | |
2042 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
bf12938e | 2043 | && ((EXTRACT_OPERAND (FT, *ip) & ~(unsigned) 1) |
252b5132 RH |
2044 | == (reg &~ (unsigned) 1))) |
2045 | return 1; | |
2046 | } | |
2047 | else if (! mips_opts.mips16) | |
2048 | { | |
2049 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
bf12938e | 2050 | && EXTRACT_OPERAND (RS, *ip) == reg) |
252b5132 RH |
2051 | return 1; |
2052 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
bf12938e | 2053 | && EXTRACT_OPERAND (RT, *ip) == reg) |
252b5132 RH |
2054 | return 1; |
2055 | } | |
2056 | else | |
2057 | { | |
2058 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
bf12938e | 2059 | && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)] == reg) |
252b5132 RH |
2060 | return 1; |
2061 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
bf12938e | 2062 | && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)] == reg) |
252b5132 RH |
2063 | return 1; |
2064 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
bf12938e | 2065 | && (mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)] |
252b5132 RH |
2066 | == reg)) |
2067 | return 1; | |
2068 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
2069 | return 1; | |
2070 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
2071 | return 1; | |
2072 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
2073 | return 1; | |
2074 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
bf12938e | 2075 | && MIPS16_EXTRACT_OPERAND (REGR32, *ip) == reg) |
252b5132 RH |
2076 | return 1; |
2077 | } | |
2078 | ||
2079 | return 0; | |
2080 | } | |
2081 | ||
2082 | /* This function returns true if modifying a register requires a | |
2083 | delay. */ | |
2084 | ||
2085 | static int | |
17a2f251 | 2086 | reg_needs_delay (unsigned int reg) |
252b5132 RH |
2087 | { |
2088 | unsigned long prev_pinfo; | |
2089 | ||
47e39b9d | 2090 | prev_pinfo = history[0].insn_mo->pinfo; |
252b5132 | 2091 | if (! mips_opts.noreorder |
81912461 ILT |
2092 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
2093 | && ! gpr_interlocks) | |
2094 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
2095 | && ! cop_interlocks))) | |
252b5132 | 2096 | { |
81912461 ILT |
2097 | /* A load from a coprocessor or from memory. All load delays |
2098 | delay the use of general register rt for one instruction. */ | |
bdaaa2e1 | 2099 | /* Itbl support may require additional care here. */ |
252b5132 | 2100 | know (prev_pinfo & INSN_WRITE_GPR_T); |
bf12938e | 2101 | if (reg == EXTRACT_OPERAND (RT, history[0])) |
252b5132 RH |
2102 | return 1; |
2103 | } | |
2104 | ||
2105 | return 0; | |
2106 | } | |
2107 | ||
404a8071 RS |
2108 | /* Move all labels in insn_labels to the current insertion point. */ |
2109 | ||
2110 | static void | |
2111 | mips_move_labels (void) | |
2112 | { | |
2113 | struct insn_label_list *l; | |
2114 | valueT val; | |
2115 | ||
2116 | for (l = insn_labels; l != NULL; l = l->next) | |
2117 | { | |
2118 | assert (S_GET_SEGMENT (l->label) == now_seg); | |
2119 | symbol_set_frag (l->label, frag_now); | |
2120 | val = (valueT) frag_now_fix (); | |
2121 | /* mips16 text labels are stored as odd. */ | |
2122 | if (mips_opts.mips16) | |
2123 | ++val; | |
2124 | S_SET_VALUE (l->label, val); | |
2125 | } | |
2126 | } | |
2127 | ||
252b5132 RH |
2128 | /* Mark instruction labels in mips16 mode. This permits the linker to |
2129 | handle them specially, such as generating jalx instructions when | |
2130 | needed. We also make them odd for the duration of the assembly, in | |
2131 | order to generate the right sort of code. We will make them even | |
2132 | in the adjust_symtab routine, while leaving them marked. This is | |
2133 | convenient for the debugger and the disassembler. The linker knows | |
2134 | to make them odd again. */ | |
2135 | ||
2136 | static void | |
17a2f251 | 2137 | mips16_mark_labels (void) |
252b5132 RH |
2138 | { |
2139 | if (mips_opts.mips16) | |
2140 | { | |
2141 | struct insn_label_list *l; | |
98aa84af | 2142 | valueT val; |
252b5132 RH |
2143 | |
2144 | for (l = insn_labels; l != NULL; l = l->next) | |
2145 | { | |
2146 | #ifdef OBJ_ELF | |
2147 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
2148 | S_SET_OTHER (l->label, STO_MIPS16); | |
2149 | #endif | |
98aa84af AM |
2150 | val = S_GET_VALUE (l->label); |
2151 | if ((val & 1) == 0) | |
2152 | S_SET_VALUE (l->label, val + 1); | |
252b5132 RH |
2153 | } |
2154 | } | |
2155 | } | |
2156 | ||
4d7206a2 RS |
2157 | /* End the current frag. Make it a variant frag and record the |
2158 | relaxation info. */ | |
2159 | ||
2160 | static void | |
2161 | relax_close_frag (void) | |
2162 | { | |
584892a6 | 2163 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 2164 | frag_var (rs_machine_dependent, 0, 0, |
584892a6 | 2165 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), |
4d7206a2 RS |
2166 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
2167 | ||
2168 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
2169 | mips_relax.first_fixup = 0; | |
2170 | } | |
2171 | ||
2172 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
2173 | See the comment above RELAX_ENCODE for more details. */ | |
2174 | ||
2175 | static void | |
2176 | relax_start (symbolS *symbol) | |
2177 | { | |
2178 | assert (mips_relax.sequence == 0); | |
2179 | mips_relax.sequence = 1; | |
2180 | mips_relax.symbol = symbol; | |
2181 | } | |
2182 | ||
2183 | /* Start generating the second version of a relaxable sequence. | |
2184 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
2185 | |
2186 | static void | |
4d7206a2 RS |
2187 | relax_switch (void) |
2188 | { | |
2189 | assert (mips_relax.sequence == 1); | |
2190 | mips_relax.sequence = 2; | |
2191 | } | |
2192 | ||
2193 | /* End the current relaxable sequence. */ | |
2194 | ||
2195 | static void | |
2196 | relax_end (void) | |
2197 | { | |
2198 | assert (mips_relax.sequence == 2); | |
2199 | relax_close_frag (); | |
2200 | mips_relax.sequence = 0; | |
2201 | } | |
2202 | ||
71400594 RS |
2203 | /* Classify an instruction according to the FIX_VR4120_* enumeration. |
2204 | Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected | |
2205 | by VR4120 errata. */ | |
4d7206a2 | 2206 | |
71400594 RS |
2207 | static unsigned int |
2208 | classify_vr4120_insn (const char *name) | |
252b5132 | 2209 | { |
71400594 RS |
2210 | if (strncmp (name, "macc", 4) == 0) |
2211 | return FIX_VR4120_MACC; | |
2212 | if (strncmp (name, "dmacc", 5) == 0) | |
2213 | return FIX_VR4120_DMACC; | |
2214 | if (strncmp (name, "mult", 4) == 0) | |
2215 | return FIX_VR4120_MULT; | |
2216 | if (strncmp (name, "dmult", 5) == 0) | |
2217 | return FIX_VR4120_DMULT; | |
2218 | if (strstr (name, "div")) | |
2219 | return FIX_VR4120_DIV; | |
2220 | if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) | |
2221 | return FIX_VR4120_MTHILO; | |
2222 | return NUM_FIX_VR4120_CLASSES; | |
2223 | } | |
252b5132 | 2224 | |
71400594 RS |
2225 | /* Return the number of instructions that must separate INSN1 and INSN2, |
2226 | where INSN1 is the earlier instruction. Return the worst-case value | |
2227 | for any INSN2 if INSN2 is null. */ | |
252b5132 | 2228 | |
71400594 RS |
2229 | static unsigned int |
2230 | insns_between (const struct mips_cl_insn *insn1, | |
2231 | const struct mips_cl_insn *insn2) | |
2232 | { | |
2233 | unsigned long pinfo1, pinfo2; | |
2234 | ||
2235 | /* This function needs to know which pinfo flags are set for INSN2 | |
2236 | and which registers INSN2 uses. The former is stored in PINFO2 and | |
2237 | the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2 | |
2238 | will have every flag set and INSN2_USES_REG will always return true. */ | |
2239 | pinfo1 = insn1->insn_mo->pinfo; | |
2240 | pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; | |
252b5132 | 2241 | |
71400594 RS |
2242 | #define INSN2_USES_REG(REG, CLASS) \ |
2243 | (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS)) | |
2244 | ||
2245 | /* For most targets, write-after-read dependencies on the HI and LO | |
2246 | registers must be separated by at least two instructions. */ | |
2247 | if (!hilo_interlocks) | |
252b5132 | 2248 | { |
71400594 RS |
2249 | if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) |
2250 | return 2; | |
2251 | if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) | |
2252 | return 2; | |
2253 | } | |
2254 | ||
2255 | /* If we're working around r7000 errata, there must be two instructions | |
2256 | between an mfhi or mflo and any instruction that uses the result. */ | |
2257 | if (mips_7000_hilo_fix | |
2258 | && MF_HILO_INSN (pinfo1) | |
2259 | && INSN2_USES_REG (EXTRACT_OPERAND (RD, *insn1), MIPS_GR_REG)) | |
2260 | return 2; | |
2261 | ||
2262 | /* If working around VR4120 errata, check for combinations that need | |
2263 | a single intervening instruction. */ | |
2264 | if (mips_fix_vr4120) | |
2265 | { | |
2266 | unsigned int class1, class2; | |
252b5132 | 2267 | |
71400594 RS |
2268 | class1 = classify_vr4120_insn (insn1->insn_mo->name); |
2269 | if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) | |
252b5132 | 2270 | { |
71400594 RS |
2271 | if (insn2 == NULL) |
2272 | return 1; | |
2273 | class2 = classify_vr4120_insn (insn2->insn_mo->name); | |
2274 | if (vr4120_conflicts[class1] & (1 << class2)) | |
2275 | return 1; | |
252b5132 | 2276 | } |
71400594 RS |
2277 | } |
2278 | ||
2279 | if (!mips_opts.mips16) | |
2280 | { | |
2281 | /* Check for GPR or coprocessor load delays. All such delays | |
2282 | are on the RT register. */ | |
2283 | /* Itbl support may require additional care here. */ | |
2284 | if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY)) | |
2285 | || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY))) | |
252b5132 | 2286 | { |
71400594 RS |
2287 | know (pinfo1 & INSN_WRITE_GPR_T); |
2288 | if (INSN2_USES_REG (EXTRACT_OPERAND (RT, *insn1), MIPS_GR_REG)) | |
2289 | return 1; | |
2290 | } | |
2291 | ||
2292 | /* Check for generic coprocessor hazards. | |
2293 | ||
2294 | This case is not handled very well. There is no special | |
2295 | knowledge of CP0 handling, and the coprocessors other than | |
2296 | the floating point unit are not distinguished at all. */ | |
2297 | /* Itbl support may require additional care here. FIXME! | |
2298 | Need to modify this to include knowledge about | |
2299 | user specified delays! */ | |
2300 | else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY)) | |
2301 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) | |
2302 | { | |
2303 | /* Handle cases where INSN1 writes to a known general coprocessor | |
2304 | register. There must be a one instruction delay before INSN2 | |
2305 | if INSN2 reads that register, otherwise no delay is needed. */ | |
2306 | if (pinfo1 & INSN_WRITE_FPR_T) | |
252b5132 | 2307 | { |
71400594 RS |
2308 | if (INSN2_USES_REG (EXTRACT_OPERAND (FT, *insn1), MIPS_FP_REG)) |
2309 | return 1; | |
252b5132 | 2310 | } |
71400594 | 2311 | else if (pinfo1 & INSN_WRITE_FPR_S) |
252b5132 | 2312 | { |
71400594 RS |
2313 | if (INSN2_USES_REG (EXTRACT_OPERAND (FS, *insn1), MIPS_FP_REG)) |
2314 | return 1; | |
252b5132 RH |
2315 | } |
2316 | else | |
2317 | { | |
71400594 RS |
2318 | /* Read-after-write dependencies on the control registers |
2319 | require a two-instruction gap. */ | |
2320 | if ((pinfo1 & INSN_WRITE_COND_CODE) | |
2321 | && (pinfo2 & INSN_READ_COND_CODE)) | |
2322 | return 2; | |
2323 | ||
2324 | /* We don't know exactly what INSN1 does. If INSN2 is | |
2325 | also a coprocessor instruction, assume there must be | |
2326 | a one instruction gap. */ | |
2327 | if (pinfo2 & INSN_COP) | |
2328 | return 1; | |
252b5132 RH |
2329 | } |
2330 | } | |
6b76fefe | 2331 | |
71400594 RS |
2332 | /* Check for read-after-write dependencies on the coprocessor |
2333 | control registers in cases where INSN1 does not need a general | |
2334 | coprocessor delay. This means that INSN1 is a floating point | |
2335 | comparison instruction. */ | |
2336 | /* Itbl support may require additional care here. */ | |
2337 | else if (!cop_interlocks | |
2338 | && (pinfo1 & INSN_WRITE_COND_CODE) | |
2339 | && (pinfo2 & INSN_READ_COND_CODE)) | |
2340 | return 1; | |
2341 | } | |
6b76fefe | 2342 | |
71400594 | 2343 | #undef INSN2_USES_REG |
6b76fefe | 2344 | |
71400594 RS |
2345 | return 0; |
2346 | } | |
6b76fefe | 2347 | |
7d8e00cf RS |
2348 | /* Return the number of nops that would be needed to work around the |
2349 | VR4130 mflo/mfhi errata if instruction INSN immediately followed | |
2350 | the MAX_VR4130_NOPS instructions described by HISTORY. */ | |
2351 | ||
2352 | static int | |
2353 | nops_for_vr4130 (const struct mips_cl_insn *history, | |
2354 | const struct mips_cl_insn *insn) | |
2355 | { | |
2356 | int i, j, reg; | |
2357 | ||
2358 | /* Check if the instruction writes to HI or LO. MTHI and MTLO | |
2359 | are not affected by the errata. */ | |
2360 | if (insn != 0 | |
2361 | && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 | |
2362 | || strcmp (insn->insn_mo->name, "mtlo") == 0 | |
2363 | || strcmp (insn->insn_mo->name, "mthi") == 0)) | |
2364 | return 0; | |
2365 | ||
2366 | /* Search for the first MFLO or MFHI. */ | |
2367 | for (i = 0; i < MAX_VR4130_NOPS; i++) | |
2368 | if (!history[i].noreorder_p && MF_HILO_INSN (history[i].insn_mo->pinfo)) | |
2369 | { | |
2370 | /* Extract the destination register. */ | |
2371 | if (mips_opts.mips16) | |
2372 | reg = mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, history[i])]; | |
2373 | else | |
2374 | reg = EXTRACT_OPERAND (RD, history[i]); | |
2375 | ||
2376 | /* No nops are needed if INSN reads that register. */ | |
2377 | if (insn != NULL && insn_uses_reg (insn, reg, MIPS_GR_REG)) | |
2378 | return 0; | |
2379 | ||
2380 | /* ...or if any of the intervening instructions do. */ | |
2381 | for (j = 0; j < i; j++) | |
2382 | if (insn_uses_reg (&history[j], reg, MIPS_GR_REG)) | |
2383 | return 0; | |
2384 | ||
2385 | return MAX_VR4130_NOPS - i; | |
2386 | } | |
2387 | return 0; | |
2388 | } | |
2389 | ||
71400594 RS |
2390 | /* Return the number of nops that would be needed if instruction INSN |
2391 | immediately followed the MAX_NOPS instructions given by HISTORY, | |
2392 | where HISTORY[0] is the most recent instruction. If INSN is null, | |
2393 | return the worse-case number of nops for any instruction. */ | |
bdaaa2e1 | 2394 | |
71400594 RS |
2395 | static int |
2396 | nops_for_insn (const struct mips_cl_insn *history, | |
2397 | const struct mips_cl_insn *insn) | |
2398 | { | |
2399 | int i, nops, tmp_nops; | |
bdaaa2e1 | 2400 | |
71400594 | 2401 | nops = 0; |
7d8e00cf | 2402 | for (i = 0; i < MAX_DELAY_NOPS; i++) |
71400594 RS |
2403 | if (!history[i].noreorder_p) |
2404 | { | |
2405 | tmp_nops = insns_between (history + i, insn) - i; | |
2406 | if (tmp_nops > nops) | |
2407 | nops = tmp_nops; | |
2408 | } | |
7d8e00cf RS |
2409 | |
2410 | if (mips_fix_vr4130) | |
2411 | { | |
2412 | tmp_nops = nops_for_vr4130 (history, insn); | |
2413 | if (tmp_nops > nops) | |
2414 | nops = tmp_nops; | |
2415 | } | |
2416 | ||
71400594 RS |
2417 | return nops; |
2418 | } | |
252b5132 | 2419 | |
71400594 RS |
2420 | /* The variable arguments provide NUM_INSNS extra instructions that |
2421 | might be added to HISTORY. Return the largest number of nops that | |
2422 | would be needed after the extended sequence. */ | |
252b5132 | 2423 | |
71400594 RS |
2424 | static int |
2425 | nops_for_sequence (int num_insns, const struct mips_cl_insn *history, ...) | |
2426 | { | |
2427 | va_list args; | |
2428 | struct mips_cl_insn buffer[MAX_NOPS]; | |
2429 | struct mips_cl_insn *cursor; | |
2430 | int nops; | |
2431 | ||
2432 | va_start (args, history); | |
2433 | cursor = buffer + num_insns; | |
2434 | memcpy (cursor, history, (MAX_NOPS - num_insns) * sizeof (*cursor)); | |
2435 | while (cursor > buffer) | |
2436 | *--cursor = *va_arg (args, const struct mips_cl_insn *); | |
2437 | ||
2438 | nops = nops_for_insn (buffer, NULL); | |
2439 | va_end (args); | |
2440 | return nops; | |
2441 | } | |
252b5132 | 2442 | |
71400594 RS |
2443 | /* Like nops_for_insn, but if INSN is a branch, take into account the |
2444 | worst-case delay for the branch target. */ | |
252b5132 | 2445 | |
71400594 RS |
2446 | static int |
2447 | nops_for_insn_or_target (const struct mips_cl_insn *history, | |
2448 | const struct mips_cl_insn *insn) | |
2449 | { | |
2450 | int nops, tmp_nops; | |
60b63b72 | 2451 | |
71400594 RS |
2452 | nops = nops_for_insn (history, insn); |
2453 | if (insn->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY | |
2454 | | INSN_COND_BRANCH_DELAY | |
2455 | | INSN_COND_BRANCH_LIKELY)) | |
2456 | { | |
2457 | tmp_nops = nops_for_sequence (2, history, insn, NOP_INSN); | |
2458 | if (tmp_nops > nops) | |
2459 | nops = tmp_nops; | |
2460 | } | |
2461 | else if (mips_opts.mips16 && (insn->insn_mo->pinfo & MIPS16_INSN_BRANCH)) | |
2462 | { | |
2463 | tmp_nops = nops_for_sequence (1, history, insn); | |
2464 | if (tmp_nops > nops) | |
2465 | nops = tmp_nops; | |
2466 | } | |
2467 | return nops; | |
2468 | } | |
2469 | ||
2470 | /* Output an instruction. IP is the instruction information. | |
2471 | ADDRESS_EXPR is an operand of the instruction to be used with | |
2472 | RELOC_TYPE. */ | |
2473 | ||
2474 | static void | |
2475 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
2476 | bfd_reloc_code_real_type *reloc_type) | |
2477 | { | |
2478 | register unsigned long prev_pinfo, pinfo; | |
2479 | relax_stateT prev_insn_frag_type = 0; | |
2480 | bfd_boolean relaxed_branch = FALSE; | |
2481 | ||
2482 | /* Mark instruction labels in mips16 mode. */ | |
2483 | mips16_mark_labels (); | |
2484 | ||
2485 | prev_pinfo = history[0].insn_mo->pinfo; | |
2486 | pinfo = ip->insn_mo->pinfo; | |
2487 | ||
2488 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) | |
2489 | { | |
2490 | /* There are a lot of optimizations we could do that we don't. | |
2491 | In particular, we do not, in general, reorder instructions. | |
2492 | If you use gcc with optimization, it will reorder | |
2493 | instructions and generally do much more optimization then we | |
2494 | do here; repeating all that work in the assembler would only | |
2495 | benefit hand written assembly code, and does not seem worth | |
2496 | it. */ | |
2497 | int nops = (mips_optimize == 0 | |
2498 | ? nops_for_insn (history, NULL) | |
2499 | : nops_for_insn_or_target (history, ip)); | |
2500 | if (nops > 0) | |
252b5132 RH |
2501 | { |
2502 | fragS *old_frag; | |
2503 | unsigned long old_frag_offset; | |
2504 | int i; | |
252b5132 RH |
2505 | |
2506 | old_frag = frag_now; | |
2507 | old_frag_offset = frag_now_fix (); | |
2508 | ||
2509 | for (i = 0; i < nops; i++) | |
2510 | emit_nop (); | |
2511 | ||
2512 | if (listing) | |
2513 | { | |
2514 | listing_prev_line (); | |
2515 | /* We may be at the start of a variant frag. In case we | |
2516 | are, make sure there is enough space for the frag | |
2517 | after the frags created by listing_prev_line. The | |
2518 | argument to frag_grow here must be at least as large | |
2519 | as the argument to all other calls to frag_grow in | |
2520 | this file. We don't have to worry about being in the | |
2521 | middle of a variant frag, because the variants insert | |
2522 | all needed nop instructions themselves. */ | |
2523 | frag_grow (40); | |
2524 | } | |
2525 | ||
404a8071 | 2526 | mips_move_labels (); |
252b5132 RH |
2527 | |
2528 | #ifndef NO_ECOFF_DEBUGGING | |
2529 | if (ECOFF_DEBUGGING) | |
2530 | ecoff_fix_loc (old_frag, old_frag_offset); | |
2531 | #endif | |
2532 | } | |
71400594 RS |
2533 | } |
2534 | else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) | |
2535 | { | |
2536 | /* Work out how many nops in prev_nop_frag are needed by IP. */ | |
2537 | int nops = nops_for_insn_or_target (history, ip); | |
2538 | assert (nops <= prev_nop_frag_holds); | |
252b5132 | 2539 | |
71400594 RS |
2540 | /* Enforce NOPS as a minimum. */ |
2541 | if (nops > prev_nop_frag_required) | |
2542 | prev_nop_frag_required = nops; | |
252b5132 | 2543 | |
71400594 RS |
2544 | if (prev_nop_frag_holds == prev_nop_frag_required) |
2545 | { | |
2546 | /* Settle for the current number of nops. Update the history | |
2547 | accordingly (for the benefit of any future .set reorder code). */ | |
2548 | prev_nop_frag = NULL; | |
2549 | insert_into_history (prev_nop_frag_since, | |
2550 | prev_nop_frag_holds, NOP_INSN); | |
2551 | } | |
2552 | else | |
2553 | { | |
2554 | /* Allow this instruction to replace one of the nops that was | |
2555 | tentatively added to prev_nop_frag. */ | |
2556 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
2557 | prev_nop_frag_holds--; | |
2558 | prev_nop_frag_since++; | |
252b5132 RH |
2559 | } |
2560 | } | |
2561 | ||
58e2ea4d MR |
2562 | #ifdef OBJ_ELF |
2563 | /* The value passed to dwarf2_emit_insn is the distance between | |
2564 | the beginning of the current instruction and the address that | |
2565 | should be recorded in the debug tables. For MIPS16 debug info | |
2566 | we want to use ISA-encoded addresses, so we pass -1 for an | |
2567 | address higher by one than the current. */ | |
2568 | dwarf2_emit_insn (mips_opts.mips16 ? -1 : 0); | |
2569 | #endif | |
2570 | ||
895921c9 | 2571 | /* Record the frag type before frag_var. */ |
47e39b9d RS |
2572 | if (history[0].frag) |
2573 | prev_insn_frag_type = history[0].frag->fr_type; | |
895921c9 | 2574 | |
4d7206a2 | 2575 | if (address_expr |
0b25d3e6 | 2576 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
4a6a3df4 AO |
2577 | && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY |
2578 | || pinfo & INSN_COND_BRANCH_LIKELY) | |
2579 | && mips_relax_branch | |
2580 | /* Don't try branch relaxation within .set nomacro, or within | |
2581 | .set noat if we use $at for PIC computations. If it turns | |
2582 | out that the branch was out-of-range, we'll get an error. */ | |
2583 | && !mips_opts.warn_about_macros | |
2584 | && !(mips_opts.noat && mips_pic != NO_PIC) | |
2585 | && !mips_opts.mips16) | |
2586 | { | |
895921c9 | 2587 | relaxed_branch = TRUE; |
1e915849 RS |
2588 | add_relaxed_insn (ip, (relaxed_branch_length |
2589 | (NULL, NULL, | |
2590 | (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1 | |
2591 | : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 | |
2592 | : 0)), 4, | |
2593 | RELAX_BRANCH_ENCODE | |
2594 | (pinfo & INSN_UNCOND_BRANCH_DELAY, | |
2595 | pinfo & INSN_COND_BRANCH_LIKELY, | |
2596 | pinfo & INSN_WRITE_GPR_31, | |
2597 | 0), | |
2598 | address_expr->X_add_symbol, | |
2599 | address_expr->X_add_number); | |
4a6a3df4 AO |
2600 | *reloc_type = BFD_RELOC_UNUSED; |
2601 | } | |
2602 | else if (*reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
2603 | { |
2604 | /* We need to set up a variant frag. */ | |
2605 | assert (mips_opts.mips16 && address_expr != NULL); | |
1e915849 RS |
2606 | add_relaxed_insn (ip, 4, 0, |
2607 | RELAX_MIPS16_ENCODE | |
2608 | (*reloc_type - BFD_RELOC_UNUSED, | |
2609 | mips16_small, mips16_ext, | |
2610 | prev_pinfo & INSN_UNCOND_BRANCH_DELAY, | |
2611 | history[0].mips16_absolute_jump_p), | |
2612 | make_expr_symbol (address_expr), 0); | |
252b5132 | 2613 | } |
252b5132 RH |
2614 | else if (mips_opts.mips16 |
2615 | && ! ip->use_extend | |
f6688943 | 2616 | && *reloc_type != BFD_RELOC_MIPS16_JMP) |
9497f5ac | 2617 | { |
b8ee1a6e DU |
2618 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) == 0) |
2619 | /* Make sure there is enough room to swap this instruction with | |
2620 | a following jump instruction. */ | |
2621 | frag_grow (6); | |
1e915849 | 2622 | add_fixed_insn (ip); |
252b5132 RH |
2623 | } |
2624 | else | |
2625 | { | |
2626 | if (mips_opts.mips16 | |
2627 | && mips_opts.noreorder | |
2628 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
2629 | as_warn (_("extended instruction in delay slot")); | |
2630 | ||
4d7206a2 RS |
2631 | if (mips_relax.sequence) |
2632 | { | |
2633 | /* If we've reached the end of this frag, turn it into a variant | |
2634 | frag and record the information for the instructions we've | |
2635 | written so far. */ | |
2636 | if (frag_room () < 4) | |
2637 | relax_close_frag (); | |
2638 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
2639 | } | |
2640 | ||
584892a6 RS |
2641 | if (mips_relax.sequence != 2) |
2642 | mips_macro_warning.sizes[0] += 4; | |
2643 | if (mips_relax.sequence != 1) | |
2644 | mips_macro_warning.sizes[1] += 4; | |
2645 | ||
1e915849 RS |
2646 | if (mips_opts.mips16) |
2647 | { | |
2648 | ip->fixed_p = 1; | |
2649 | ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); | |
2650 | } | |
2651 | add_fixed_insn (ip); | |
252b5132 RH |
2652 | } |
2653 | ||
01a3f561 | 2654 | if (address_expr != NULL && *reloc_type <= BFD_RELOC_UNUSED) |
252b5132 RH |
2655 | { |
2656 | if (address_expr->X_op == O_constant) | |
2657 | { | |
f17c130b | 2658 | unsigned int tmp; |
f6688943 TS |
2659 | |
2660 | switch (*reloc_type) | |
252b5132 RH |
2661 | { |
2662 | case BFD_RELOC_32: | |
2663 | ip->insn_opcode |= address_expr->X_add_number; | |
2664 | break; | |
2665 | ||
f6688943 | 2666 | case BFD_RELOC_MIPS_HIGHEST: |
f17c130b AM |
2667 | tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48; |
2668 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2669 | break; |
2670 | ||
2671 | case BFD_RELOC_MIPS_HIGHER: | |
f17c130b AM |
2672 | tmp = (address_expr->X_add_number + 0x80008000ull) >> 32; |
2673 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2674 | break; |
2675 | ||
2676 | case BFD_RELOC_HI16_S: | |
f17c130b AM |
2677 | tmp = (address_expr->X_add_number + 0x8000) >> 16; |
2678 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2679 | break; |
2680 | ||
2681 | case BFD_RELOC_HI16: | |
2682 | ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; | |
2683 | break; | |
2684 | ||
01a3f561 | 2685 | case BFD_RELOC_UNUSED: |
252b5132 | 2686 | case BFD_RELOC_LO16: |
ed6fb7bd | 2687 | case BFD_RELOC_MIPS_GOT_DISP: |
252b5132 RH |
2688 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
2689 | break; | |
2690 | ||
2691 | case BFD_RELOC_MIPS_JMP: | |
2692 | if ((address_expr->X_add_number & 3) != 0) | |
2693 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2694 | (unsigned long) address_expr->X_add_number); | |
2695 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; | |
2696 | break; | |
2697 | ||
2698 | case BFD_RELOC_MIPS16_JMP: | |
2699 | if ((address_expr->X_add_number & 3) != 0) | |
2700 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2701 | (unsigned long) address_expr->X_add_number); | |
2702 | ip->insn_opcode |= | |
2703 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
2704 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
2705 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
2706 | break; | |
2707 | ||
252b5132 | 2708 | case BFD_RELOC_16_PCREL_S2: |
bad36eac DJ |
2709 | if ((address_expr->X_add_number & 3) != 0) |
2710 | as_bad (_("branch to misaligned address (0x%lx)"), | |
2711 | (unsigned long) address_expr->X_add_number); | |
2712 | if (mips_relax_branch) | |
2713 | goto need_reloc; | |
2714 | if ((address_expr->X_add_number + 0x20000) & ~0x3ffff) | |
2715 | as_bad (_("branch address range overflow (0x%lx)"), | |
2716 | (unsigned long) address_expr->X_add_number); | |
2717 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0xffff; | |
2718 | break; | |
252b5132 RH |
2719 | |
2720 | default: | |
2721 | internalError (); | |
2722 | } | |
2723 | } | |
01a3f561 | 2724 | else if (*reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 2725 | need_reloc: |
4d7206a2 RS |
2726 | { |
2727 | reloc_howto_type *howto; | |
2728 | int i; | |
34ce925e | 2729 | |
4d7206a2 RS |
2730 | /* In a compound relocation, it is the final (outermost) |
2731 | operator that determines the relocated field. */ | |
2732 | for (i = 1; i < 3; i++) | |
2733 | if (reloc_type[i] == BFD_RELOC_UNUSED) | |
2734 | break; | |
34ce925e | 2735 | |
4d7206a2 | 2736 | howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]); |
1e915849 RS |
2737 | ip->fixp[0] = fix_new_exp (ip->frag, ip->where, |
2738 | bfd_get_reloc_size (howto), | |
2739 | address_expr, | |
2740 | reloc_type[0] == BFD_RELOC_16_PCREL_S2, | |
2741 | reloc_type[0]); | |
4d7206a2 RS |
2742 | |
2743 | /* These relocations can have an addend that won't fit in | |
2744 | 4 octets for 64bit assembly. */ | |
2745 | if (HAVE_64BIT_GPRS | |
2746 | && ! howto->partial_inplace | |
2747 | && (reloc_type[0] == BFD_RELOC_16 | |
2748 | || reloc_type[0] == BFD_RELOC_32 | |
2749 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
2750 | || reloc_type[0] == BFD_RELOC_HI16_S | |
2751 | || reloc_type[0] == BFD_RELOC_LO16 | |
2752 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
2753 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
2754 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
2755 | || reloc_type[0] == BFD_RELOC_64 | |
2756 | || reloc_type[0] == BFD_RELOC_CTOR | |
2757 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
2758 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
2759 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
2760 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
2761 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
d6f16593 MR |
2762 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT |
2763 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
2764 | || reloc_type[0] == BFD_RELOC_MIPS16_HI16_S | |
2765 | || reloc_type[0] == BFD_RELOC_MIPS16_LO16)) | |
1e915849 | 2766 | ip->fixp[0]->fx_no_overflow = 1; |
4d7206a2 RS |
2767 | |
2768 | if (mips_relax.sequence) | |
2769 | { | |
2770 | if (mips_relax.first_fixup == 0) | |
1e915849 | 2771 | mips_relax.first_fixup = ip->fixp[0]; |
4d7206a2 RS |
2772 | } |
2773 | else if (reloc_needs_lo_p (*reloc_type)) | |
2774 | { | |
2775 | struct mips_hi_fixup *hi_fixup; | |
252b5132 | 2776 | |
4d7206a2 RS |
2777 | /* Reuse the last entry if it already has a matching %lo. */ |
2778 | hi_fixup = mips_hi_fixup_list; | |
2779 | if (hi_fixup == 0 | |
2780 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
2781 | { | |
2782 | hi_fixup = ((struct mips_hi_fixup *) | |
2783 | xmalloc (sizeof (struct mips_hi_fixup))); | |
2784 | hi_fixup->next = mips_hi_fixup_list; | |
2785 | mips_hi_fixup_list = hi_fixup; | |
252b5132 | 2786 | } |
1e915849 | 2787 | hi_fixup->fixp = ip->fixp[0]; |
4d7206a2 RS |
2788 | hi_fixup->seg = now_seg; |
2789 | } | |
f6688943 | 2790 | |
4d7206a2 RS |
2791 | /* Add fixups for the second and third relocations, if given. |
2792 | Note that the ABI allows the second relocation to be | |
2793 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
2794 | moment we only use RSS_UNDEF, but we could add support | |
2795 | for the others if it ever becomes necessary. */ | |
2796 | for (i = 1; i < 3; i++) | |
2797 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
2798 | { | |
1e915849 RS |
2799 | ip->fixp[i] = fix_new (ip->frag, ip->where, |
2800 | ip->fixp[0]->fx_size, NULL, 0, | |
2801 | FALSE, reloc_type[i]); | |
b1dca8ee RS |
2802 | |
2803 | /* Use fx_tcbit to mark compound relocs. */ | |
1e915849 RS |
2804 | ip->fixp[0]->fx_tcbit = 1; |
2805 | ip->fixp[i]->fx_tcbit = 1; | |
4d7206a2 | 2806 | } |
252b5132 RH |
2807 | } |
2808 | } | |
1e915849 | 2809 | install_insn (ip); |
252b5132 RH |
2810 | |
2811 | /* Update the register mask information. */ | |
2812 | if (! mips_opts.mips16) | |
2813 | { | |
2814 | if (pinfo & INSN_WRITE_GPR_D) | |
bf12938e | 2815 | mips_gprmask |= 1 << EXTRACT_OPERAND (RD, *ip); |
252b5132 | 2816 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) |
bf12938e | 2817 | mips_gprmask |= 1 << EXTRACT_OPERAND (RT, *ip); |
252b5132 | 2818 | if (pinfo & INSN_READ_GPR_S) |
bf12938e | 2819 | mips_gprmask |= 1 << EXTRACT_OPERAND (RS, *ip); |
252b5132 | 2820 | if (pinfo & INSN_WRITE_GPR_31) |
f9419b05 | 2821 | mips_gprmask |= 1 << RA; |
252b5132 | 2822 | if (pinfo & INSN_WRITE_FPR_D) |
bf12938e | 2823 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FD, *ip); |
252b5132 | 2824 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) |
bf12938e | 2825 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FS, *ip); |
252b5132 | 2826 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) |
bf12938e | 2827 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FT, *ip); |
252b5132 | 2828 | if ((pinfo & INSN_READ_FPR_R) != 0) |
bf12938e | 2829 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FR, *ip); |
252b5132 RH |
2830 | if (pinfo & INSN_COP) |
2831 | { | |
bdaaa2e1 KH |
2832 | /* We don't keep enough information to sort these cases out. |
2833 | The itbl support does keep this information however, although | |
2834 | we currently don't support itbl fprmats as part of the cop | |
2835 | instruction. May want to add this support in the future. */ | |
252b5132 RH |
2836 | } |
2837 | /* Never set the bit for $0, which is always zero. */ | |
beae10d5 | 2838 | mips_gprmask &= ~1 << 0; |
252b5132 RH |
2839 | } |
2840 | else | |
2841 | { | |
2842 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) | |
bf12938e | 2843 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RX, *ip); |
252b5132 | 2844 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) |
bf12938e | 2845 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RY, *ip); |
252b5132 | 2846 | if (pinfo & MIPS16_INSN_WRITE_Z) |
bf12938e | 2847 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RZ, *ip); |
252b5132 RH |
2848 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) |
2849 | mips_gprmask |= 1 << TREG; | |
2850 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
2851 | mips_gprmask |= 1 << SP; | |
2852 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
2853 | mips_gprmask |= 1 << RA; | |
2854 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2855 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
2856 | if (pinfo & MIPS16_INSN_READ_Z) | |
bf12938e | 2857 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip); |
252b5132 | 2858 | if (pinfo & MIPS16_INSN_READ_GPR_X) |
bf12938e | 2859 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip); |
252b5132 RH |
2860 | } |
2861 | ||
4d7206a2 | 2862 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
252b5132 RH |
2863 | { |
2864 | /* Filling the branch delay slot is more complex. We try to | |
2865 | switch the branch with the previous instruction, which we can | |
2866 | do if the previous instruction does not set up a condition | |
2867 | that the branch tests and if the branch is not itself the | |
2868 | target of any branch. */ | |
2869 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2870 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
2871 | { | |
2872 | if (mips_optimize < 2 | |
2873 | /* If we have seen .set volatile or .set nomove, don't | |
2874 | optimize. */ | |
2875 | || mips_opts.nomove != 0 | |
a38419a5 RS |
2876 | /* We can't swap if the previous instruction's position |
2877 | is fixed. */ | |
2878 | || history[0].fixed_p | |
252b5132 RH |
2879 | /* If the previous previous insn was in a .set |
2880 | noreorder, we can't swap. Actually, the MIPS | |
2881 | assembler will swap in this situation. However, gcc | |
2882 | configured -with-gnu-as will generate code like | |
2883 | .set noreorder | |
2884 | lw $4,XXX | |
2885 | .set reorder | |
2886 | INSN | |
2887 | bne $4,$0,foo | |
2888 | in which we can not swap the bne and INSN. If gcc is | |
2889 | not configured -with-gnu-as, it does not output the | |
a38419a5 | 2890 | .set pseudo-ops. */ |
47e39b9d | 2891 | || history[1].noreorder_p |
252b5132 RH |
2892 | /* If the branch is itself the target of a branch, we |
2893 | can not swap. We cheat on this; all we check for is | |
2894 | whether there is a label on this instruction. If | |
2895 | there are any branches to anything other than a | |
2896 | label, users must use .set noreorder. */ | |
2897 | || insn_labels != NULL | |
895921c9 MR |
2898 | /* If the previous instruction is in a variant frag |
2899 | other than this branch's one, we cannot do the swap. | |
2900 | This does not apply to the mips16, which uses variant | |
2901 | frags for different purposes. */ | |
252b5132 | 2902 | || (! mips_opts.mips16 |
895921c9 | 2903 | && prev_insn_frag_type == rs_machine_dependent) |
71400594 RS |
2904 | /* Check for conflicts between the branch and the instructions |
2905 | before the candidate delay slot. */ | |
2906 | || nops_for_insn (history + 1, ip) > 0 | |
2907 | /* Check for conflicts between the swapped sequence and the | |
2908 | target of the branch. */ | |
2909 | || nops_for_sequence (2, history + 1, ip, history) > 0 | |
252b5132 RH |
2910 | /* We do not swap with a trap instruction, since it |
2911 | complicates trap handlers to have the trap | |
2912 | instruction be in a delay slot. */ | |
2913 | || (prev_pinfo & INSN_TRAP) | |
2914 | /* If the branch reads a register that the previous | |
2915 | instruction sets, we can not swap. */ | |
2916 | || (! mips_opts.mips16 | |
2917 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
bf12938e | 2918 | && insn_uses_reg (ip, EXTRACT_OPERAND (RT, history[0]), |
252b5132 RH |
2919 | MIPS_GR_REG)) |
2920 | || (! mips_opts.mips16 | |
2921 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
bf12938e | 2922 | && insn_uses_reg (ip, EXTRACT_OPERAND (RD, history[0]), |
252b5132 RH |
2923 | MIPS_GR_REG)) |
2924 | || (mips_opts.mips16 | |
2925 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
bf12938e RS |
2926 | && (insn_uses_reg |
2927 | (ip, MIPS16_EXTRACT_OPERAND (RX, history[0]), | |
2928 | MIPS16_REG))) | |
252b5132 | 2929 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) |
bf12938e RS |
2930 | && (insn_uses_reg |
2931 | (ip, MIPS16_EXTRACT_OPERAND (RY, history[0]), | |
2932 | MIPS16_REG))) | |
252b5132 | 2933 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) |
bf12938e RS |
2934 | && (insn_uses_reg |
2935 | (ip, MIPS16_EXTRACT_OPERAND (RZ, history[0]), | |
2936 | MIPS16_REG))) | |
252b5132 RH |
2937 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) |
2938 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
2939 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2940 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
2941 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2942 | && insn_uses_reg (ip, | |
47e39b9d RS |
2943 | MIPS16OP_EXTRACT_REG32R |
2944 | (history[0].insn_opcode), | |
252b5132 RH |
2945 | MIPS_GR_REG)))) |
2946 | /* If the branch writes a register that the previous | |
2947 | instruction sets, we can not swap (we know that | |
2948 | branches write only to RD or to $31). */ | |
2949 | || (! mips_opts.mips16 | |
2950 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2951 | && (((pinfo & INSN_WRITE_GPR_D) | |
bf12938e RS |
2952 | && (EXTRACT_OPERAND (RT, history[0]) |
2953 | == EXTRACT_OPERAND (RD, *ip))) | |
252b5132 | 2954 | || ((pinfo & INSN_WRITE_GPR_31) |
bf12938e | 2955 | && EXTRACT_OPERAND (RT, history[0]) == RA))) |
252b5132 RH |
2956 | || (! mips_opts.mips16 |
2957 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2958 | && (((pinfo & INSN_WRITE_GPR_D) | |
bf12938e RS |
2959 | && (EXTRACT_OPERAND (RD, history[0]) |
2960 | == EXTRACT_OPERAND (RD, *ip))) | |
252b5132 | 2961 | || ((pinfo & INSN_WRITE_GPR_31) |
bf12938e | 2962 | && EXTRACT_OPERAND (RD, history[0]) == RA))) |
252b5132 RH |
2963 | || (mips_opts.mips16 |
2964 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2965 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2966 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
47e39b9d | 2967 | && (MIPS16OP_EXTRACT_REG32R (history[0].insn_opcode) |
252b5132 RH |
2968 | == RA)))) |
2969 | /* If the branch writes a register that the previous | |
2970 | instruction reads, we can not swap (we know that | |
2971 | branches only write to RD or to $31). */ | |
2972 | || (! mips_opts.mips16 | |
2973 | && (pinfo & INSN_WRITE_GPR_D) | |
47e39b9d | 2974 | && insn_uses_reg (&history[0], |
bf12938e | 2975 | EXTRACT_OPERAND (RD, *ip), |
252b5132 RH |
2976 | MIPS_GR_REG)) |
2977 | || (! mips_opts.mips16 | |
2978 | && (pinfo & INSN_WRITE_GPR_31) | |
47e39b9d | 2979 | && insn_uses_reg (&history[0], RA, MIPS_GR_REG)) |
252b5132 RH |
2980 | || (mips_opts.mips16 |
2981 | && (pinfo & MIPS16_INSN_WRITE_31) | |
47e39b9d | 2982 | && insn_uses_reg (&history[0], RA, MIPS_GR_REG)) |
252b5132 RH |
2983 | /* If one instruction sets a condition code and the |
2984 | other one uses a condition code, we can not swap. */ | |
2985 | || ((pinfo & INSN_READ_COND_CODE) | |
2986 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
2987 | || ((pinfo & INSN_WRITE_COND_CODE) | |
2988 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
2989 | /* If the previous instruction uses the PC, we can not | |
2990 | swap. */ | |
2991 | || (mips_opts.mips16 | |
2992 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
252b5132 RH |
2993 | /* If the previous instruction had a fixup in mips16 |
2994 | mode, we can not swap. This normally means that the | |
2995 | previous instruction was a 4 byte branch anyhow. */ | |
47e39b9d | 2996 | || (mips_opts.mips16 && history[0].fixp[0]) |
bdaaa2e1 KH |
2997 | /* If the previous instruction is a sync, sync.l, or |
2998 | sync.p, we can not swap. */ | |
f173e82e | 2999 | || (prev_pinfo & INSN_SYNC)) |
252b5132 | 3000 | { |
29024861 DU |
3001 | if (mips_opts.mips16 |
3002 | && (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
3003 | && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31)) | |
3004 | && (mips_opts.isa == ISA_MIPS32 | |
3005 | || mips_opts.isa == ISA_MIPS32R2 | |
3006 | || mips_opts.isa == ISA_MIPS64 | |
3007 | || mips_opts.isa == ISA_MIPS64R2)) | |
3008 | { | |
3009 | /* Convert MIPS16 jr/jalr into a "compact" jump. */ | |
3010 | ip->insn_opcode |= 0x0080; | |
3011 | install_insn (ip); | |
3012 | insert_into_history (0, 1, ip); | |
3013 | } | |
3014 | else | |
3015 | { | |
3016 | /* We could do even better for unconditional branches to | |
3017 | portions of this object file; we could pick up the | |
3018 | instruction at the destination, put it in the delay | |
3019 | slot, and bump the destination address. */ | |
3020 | insert_into_history (0, 1, ip); | |
3021 | emit_nop (); | |
3022 | } | |
3023 | ||
dd22970f ILT |
3024 | if (mips_relax.sequence) |
3025 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
252b5132 RH |
3026 | } |
3027 | else | |
3028 | { | |
3029 | /* It looks like we can actually do the swap. */ | |
1e915849 RS |
3030 | struct mips_cl_insn delay = history[0]; |
3031 | if (mips_opts.mips16) | |
252b5132 | 3032 | { |
b8ee1a6e DU |
3033 | know (delay.frag == ip->frag); |
3034 | move_insn (ip, delay.frag, delay.where); | |
3035 | move_insn (&delay, ip->frag, ip->where + insn_length (ip)); | |
1e915849 RS |
3036 | } |
3037 | else if (relaxed_branch) | |
3038 | { | |
3039 | /* Add the delay slot instruction to the end of the | |
3040 | current frag and shrink the fixed part of the | |
3041 | original frag. If the branch occupies the tail of | |
3042 | the latter, move it backwards to cover the gap. */ | |
3043 | delay.frag->fr_fix -= 4; | |
3044 | if (delay.frag == ip->frag) | |
3045 | move_insn (ip, ip->frag, ip->where - 4); | |
3046 | add_fixed_insn (&delay); | |
252b5132 RH |
3047 | } |
3048 | else | |
3049 | { | |
1e915849 RS |
3050 | move_insn (&delay, ip->frag, ip->where); |
3051 | move_insn (ip, history[0].frag, history[0].where); | |
252b5132 | 3052 | } |
1e915849 RS |
3053 | history[0] = *ip; |
3054 | delay.fixed_p = 1; | |
3055 | insert_into_history (0, 1, &delay); | |
252b5132 | 3056 | } |
252b5132 RH |
3057 | |
3058 | /* If that was an unconditional branch, forget the previous | |
3059 | insn information. */ | |
3060 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
7d10b47d | 3061 | mips_no_prev_insn (); |
252b5132 RH |
3062 | } |
3063 | else if (pinfo & INSN_COND_BRANCH_LIKELY) | |
3064 | { | |
3065 | /* We don't yet optimize a branch likely. What we should do | |
3066 | is look at the target, copy the instruction found there | |
3067 | into the delay slot, and increment the branch to jump to | |
3068 | the next instruction. */ | |
1e915849 | 3069 | insert_into_history (0, 1, ip); |
252b5132 | 3070 | emit_nop (); |
252b5132 RH |
3071 | } |
3072 | else | |
1e915849 | 3073 | insert_into_history (0, 1, ip); |
252b5132 | 3074 | } |
1e915849 RS |
3075 | else |
3076 | insert_into_history (0, 1, ip); | |
252b5132 RH |
3077 | |
3078 | /* We just output an insn, so the next one doesn't have a label. */ | |
3079 | mips_clear_insn_labels (); | |
252b5132 RH |
3080 | } |
3081 | ||
7d10b47d | 3082 | /* Forget that there was any previous instruction or label. */ |
252b5132 RH |
3083 | |
3084 | static void | |
7d10b47d | 3085 | mips_no_prev_insn (void) |
252b5132 | 3086 | { |
7d10b47d RS |
3087 | prev_nop_frag = NULL; |
3088 | insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); | |
252b5132 RH |
3089 | mips_clear_insn_labels (); |
3090 | } | |
3091 | ||
7d10b47d RS |
3092 | /* This function must be called before we emit something other than |
3093 | instructions. It is like mips_no_prev_insn except that it inserts | |
3094 | any NOPS that might be needed by previous instructions. */ | |
252b5132 | 3095 | |
7d10b47d RS |
3096 | void |
3097 | mips_emit_delays (void) | |
252b5132 RH |
3098 | { |
3099 | if (! mips_opts.noreorder) | |
3100 | { | |
71400594 | 3101 | int nops = nops_for_insn (history, NULL); |
252b5132 RH |
3102 | if (nops > 0) |
3103 | { | |
7d10b47d RS |
3104 | while (nops-- > 0) |
3105 | add_fixed_insn (NOP_INSN); | |
3106 | mips_move_labels (); | |
3107 | } | |
3108 | } | |
3109 | mips_no_prev_insn (); | |
3110 | } | |
3111 | ||
3112 | /* Start a (possibly nested) noreorder block. */ | |
3113 | ||
3114 | static void | |
3115 | start_noreorder (void) | |
3116 | { | |
3117 | if (mips_opts.noreorder == 0) | |
3118 | { | |
3119 | unsigned int i; | |
3120 | int nops; | |
3121 | ||
3122 | /* None of the instructions before the .set noreorder can be moved. */ | |
3123 | for (i = 0; i < ARRAY_SIZE (history); i++) | |
3124 | history[i].fixed_p = 1; | |
3125 | ||
3126 | /* Insert any nops that might be needed between the .set noreorder | |
3127 | block and the previous instructions. We will later remove any | |
3128 | nops that turn out not to be needed. */ | |
3129 | nops = nops_for_insn (history, NULL); | |
3130 | if (nops > 0) | |
3131 | { | |
3132 | if (mips_optimize != 0) | |
252b5132 RH |
3133 | { |
3134 | /* Record the frag which holds the nop instructions, so | |
3135 | that we can remove them if we don't need them. */ | |
3136 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); | |
3137 | prev_nop_frag = frag_now; | |
3138 | prev_nop_frag_holds = nops; | |
3139 | prev_nop_frag_required = 0; | |
3140 | prev_nop_frag_since = 0; | |
3141 | } | |
3142 | ||
3143 | for (; nops > 0; --nops) | |
1e915849 | 3144 | add_fixed_insn (NOP_INSN); |
252b5132 | 3145 | |
7d10b47d RS |
3146 | /* Move on to a new frag, so that it is safe to simply |
3147 | decrease the size of prev_nop_frag. */ | |
3148 | frag_wane (frag_now); | |
3149 | frag_new (0); | |
404a8071 | 3150 | mips_move_labels (); |
252b5132 | 3151 | } |
7d10b47d RS |
3152 | mips16_mark_labels (); |
3153 | mips_clear_insn_labels (); | |
252b5132 | 3154 | } |
7d10b47d RS |
3155 | mips_opts.noreorder++; |
3156 | mips_any_noreorder = 1; | |
3157 | } | |
252b5132 | 3158 | |
7d10b47d | 3159 | /* End a nested noreorder block. */ |
252b5132 | 3160 | |
7d10b47d RS |
3161 | static void |
3162 | end_noreorder (void) | |
3163 | { | |
3164 | mips_opts.noreorder--; | |
3165 | if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) | |
3166 | { | |
3167 | /* Commit to inserting prev_nop_frag_required nops and go back to | |
3168 | handling nop insertion the .set reorder way. */ | |
3169 | prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) | |
3170 | * (mips_opts.mips16 ? 2 : 4)); | |
3171 | insert_into_history (prev_nop_frag_since, | |
3172 | prev_nop_frag_required, NOP_INSN); | |
3173 | prev_nop_frag = NULL; | |
3174 | } | |
252b5132 RH |
3175 | } |
3176 | ||
584892a6 RS |
3177 | /* Set up global variables for the start of a new macro. */ |
3178 | ||
3179 | static void | |
3180 | macro_start (void) | |
3181 | { | |
3182 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
3183 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder | |
47e39b9d | 3184 | && (history[0].insn_mo->pinfo |
584892a6 RS |
3185 | & (INSN_UNCOND_BRANCH_DELAY |
3186 | | INSN_COND_BRANCH_DELAY | |
3187 | | INSN_COND_BRANCH_LIKELY)) != 0); | |
3188 | } | |
3189 | ||
3190 | /* Given that a macro is longer than 4 bytes, return the appropriate warning | |
3191 | for it. Return null if no warning is needed. SUBTYPE is a bitmask of | |
3192 | RELAX_DELAY_SLOT and RELAX_NOMACRO. */ | |
3193 | ||
3194 | static const char * | |
3195 | macro_warning (relax_substateT subtype) | |
3196 | { | |
3197 | if (subtype & RELAX_DELAY_SLOT) | |
3198 | return _("Macro instruction expanded into multiple instructions" | |
3199 | " in a branch delay slot"); | |
3200 | else if (subtype & RELAX_NOMACRO) | |
3201 | return _("Macro instruction expanded into multiple instructions"); | |
3202 | else | |
3203 | return 0; | |
3204 | } | |
3205 | ||
3206 | /* Finish up a macro. Emit warnings as appropriate. */ | |
3207 | ||
3208 | static void | |
3209 | macro_end (void) | |
3210 | { | |
3211 | if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4) | |
3212 | { | |
3213 | relax_substateT subtype; | |
3214 | ||
3215 | /* Set up the relaxation warning flags. */ | |
3216 | subtype = 0; | |
3217 | if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0]) | |
3218 | subtype |= RELAX_SECOND_LONGER; | |
3219 | if (mips_opts.warn_about_macros) | |
3220 | subtype |= RELAX_NOMACRO; | |
3221 | if (mips_macro_warning.delay_slot_p) | |
3222 | subtype |= RELAX_DELAY_SLOT; | |
3223 | ||
3224 | if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4) | |
3225 | { | |
3226 | /* Either the macro has a single implementation or both | |
3227 | implementations are longer than 4 bytes. Emit the | |
3228 | warning now. */ | |
3229 | const char *msg = macro_warning (subtype); | |
3230 | if (msg != 0) | |
3231 | as_warn (msg); | |
3232 | } | |
3233 | else | |
3234 | { | |
3235 | /* One implementation might need a warning but the other | |
3236 | definitely doesn't. */ | |
3237 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
3238 | } | |
3239 | } | |
3240 | } | |
3241 | ||
6e1304d8 RS |
3242 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
3243 | The first argument in *ARGS will be either the code for a single | |
3244 | relocation or -1 followed by the three codes that make up a | |
3245 | composite relocation. */ | |
3246 | ||
3247 | static void | |
3248 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
3249 | { | |
3250 | int i, next; | |
3251 | ||
3252 | next = va_arg (*args, int); | |
3253 | if (next >= 0) | |
3254 | r[0] = (bfd_reloc_code_real_type) next; | |
3255 | else | |
3256 | for (i = 0; i < 3; i++) | |
3257 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
3258 | } | |
3259 | ||
252b5132 RH |
3260 | /* Build an instruction created by a macro expansion. This is passed |
3261 | a pointer to the count of instructions created so far, an | |
3262 | expression, the name of the instruction to build, an operand format | |
3263 | string, and corresponding arguments. */ | |
3264 | ||
252b5132 | 3265 | static void |
67c0d1eb | 3266 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 | 3267 | { |
1e915849 | 3268 | const struct mips_opcode *mo; |
252b5132 | 3269 | struct mips_cl_insn insn; |
f6688943 | 3270 | bfd_reloc_code_real_type r[3]; |
252b5132 | 3271 | va_list args; |
252b5132 | 3272 | |
252b5132 | 3273 | va_start (args, fmt); |
252b5132 | 3274 | |
252b5132 RH |
3275 | if (mips_opts.mips16) |
3276 | { | |
67c0d1eb | 3277 | mips16_macro_build (ep, name, fmt, args); |
252b5132 RH |
3278 | va_end (args); |
3279 | return; | |
3280 | } | |
3281 | ||
f6688943 TS |
3282 | r[0] = BFD_RELOC_UNUSED; |
3283 | r[1] = BFD_RELOC_UNUSED; | |
3284 | r[2] = BFD_RELOC_UNUSED; | |
1e915849 RS |
3285 | mo = (struct mips_opcode *) hash_find (op_hash, name); |
3286 | assert (mo); | |
3287 | assert (strcmp (name, mo->name) == 0); | |
3288 | ||
3289 | /* Search until we get a match for NAME. It is assumed here that | |
65263ce3 | 3290 | macros will never generate MDMX, MIPS-3D, DSP or MT instructions. */ |
1e915849 RS |
3291 | while (strcmp (fmt, mo->args) != 0 |
3292 | || mo->pinfo == INSN_MACRO | |
3293 | || !OPCODE_IS_MEMBER (mo, | |
3294 | (mips_opts.isa | |
9b3f89ee | 3295 | | (mips_opts.mips16 ? INSN_MIPS16 : 0) |
e16bfa71 | 3296 | | (mips_opts.ase_smartmips ? INSN_SMARTMIPS : 0)), |
fef14a42 | 3297 | mips_opts.arch) |
1e915849 RS |
3298 | || (mips_opts.arch == CPU_R4650 && (mo->pinfo & FP_D) != 0)) |
3299 | { | |
3300 | ++mo; | |
3301 | assert (mo->name); | |
3302 | assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
3303 | } |
3304 | ||
1e915849 | 3305 | create_insn (&insn, mo); |
252b5132 RH |
3306 | for (;;) |
3307 | { | |
3308 | switch (*fmt++) | |
3309 | { | |
3310 | case '\0': | |
3311 | break; | |
3312 | ||
3313 | case ',': | |
3314 | case '(': | |
3315 | case ')': | |
3316 | continue; | |
3317 | ||
5f74bc13 CD |
3318 | case '+': |
3319 | switch (*fmt++) | |
3320 | { | |
3321 | case 'A': | |
3322 | case 'E': | |
bf12938e | 3323 | INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); |
5f74bc13 CD |
3324 | continue; |
3325 | ||
3326 | case 'B': | |
3327 | case 'F': | |
3328 | /* Note that in the macro case, these arguments are already | |
3329 | in MSB form. (When handling the instruction in the | |
3330 | non-macro case, these arguments are sizes from which | |
3331 | MSB values must be calculated.) */ | |
bf12938e | 3332 | INSERT_OPERAND (INSMSB, insn, va_arg (args, int)); |
5f74bc13 CD |
3333 | continue; |
3334 | ||
3335 | case 'C': | |
3336 | case 'G': | |
3337 | case 'H': | |
3338 | /* Note that in the macro case, these arguments are already | |
3339 | in MSBD form. (When handling the instruction in the | |
3340 | non-macro case, these arguments are sizes from which | |
3341 | MSBD values must be calculated.) */ | |
bf12938e | 3342 | INSERT_OPERAND (EXTMSBD, insn, va_arg (args, int)); |
5f74bc13 CD |
3343 | continue; |
3344 | ||
3345 | default: | |
3346 | internalError (); | |
3347 | } | |
3348 | continue; | |
3349 | ||
252b5132 RH |
3350 | case 't': |
3351 | case 'w': | |
3352 | case 'E': | |
bf12938e | 3353 | INSERT_OPERAND (RT, insn, va_arg (args, int)); |
252b5132 RH |
3354 | continue; |
3355 | ||
3356 | case 'c': | |
bf12938e | 3357 | INSERT_OPERAND (CODE, insn, va_arg (args, int)); |
38487616 TS |
3358 | continue; |
3359 | ||
252b5132 RH |
3360 | case 'T': |
3361 | case 'W': | |
bf12938e | 3362 | INSERT_OPERAND (FT, insn, va_arg (args, int)); |
252b5132 RH |
3363 | continue; |
3364 | ||
3365 | case 'd': | |
3366 | case 'G': | |
af7ee8bf | 3367 | case 'K': |
bf12938e | 3368 | INSERT_OPERAND (RD, insn, va_arg (args, int)); |
252b5132 RH |
3369 | continue; |
3370 | ||
4372b673 NC |
3371 | case 'U': |
3372 | { | |
3373 | int tmp = va_arg (args, int); | |
3374 | ||
bf12938e RS |
3375 | INSERT_OPERAND (RT, insn, tmp); |
3376 | INSERT_OPERAND (RD, insn, tmp); | |
beae10d5 | 3377 | continue; |
4372b673 NC |
3378 | } |
3379 | ||
252b5132 RH |
3380 | case 'V': |
3381 | case 'S': | |
bf12938e | 3382 | INSERT_OPERAND (FS, insn, va_arg (args, int)); |
252b5132 RH |
3383 | continue; |
3384 | ||
3385 | case 'z': | |
3386 | continue; | |
3387 | ||
3388 | case '<': | |
bf12938e | 3389 | INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); |
252b5132 RH |
3390 | continue; |
3391 | ||
3392 | case 'D': | |
bf12938e | 3393 | INSERT_OPERAND (FD, insn, va_arg (args, int)); |
252b5132 RH |
3394 | continue; |
3395 | ||
3396 | case 'B': | |
bf12938e | 3397 | INSERT_OPERAND (CODE20, insn, va_arg (args, int)); |
252b5132 RH |
3398 | continue; |
3399 | ||
4372b673 | 3400 | case 'J': |
bf12938e | 3401 | INSERT_OPERAND (CODE19, insn, va_arg (args, int)); |
4372b673 NC |
3402 | continue; |
3403 | ||
252b5132 | 3404 | case 'q': |
bf12938e | 3405 | INSERT_OPERAND (CODE2, insn, va_arg (args, int)); |
252b5132 RH |
3406 | continue; |
3407 | ||
3408 | case 'b': | |
3409 | case 's': | |
3410 | case 'r': | |
3411 | case 'v': | |
bf12938e | 3412 | INSERT_OPERAND (RS, insn, va_arg (args, int)); |
252b5132 RH |
3413 | continue; |
3414 | ||
3415 | case 'i': | |
3416 | case 'j': | |
3417 | case 'o': | |
6e1304d8 | 3418 | macro_read_relocs (&args, r); |
cdf6fd85 | 3419 | assert (*r == BFD_RELOC_GPREL16 |
f6688943 TS |
3420 | || *r == BFD_RELOC_MIPS_LITERAL |
3421 | || *r == BFD_RELOC_MIPS_HIGHER | |
3422 | || *r == BFD_RELOC_HI16_S | |
3423 | || *r == BFD_RELOC_LO16 | |
3424 | || *r == BFD_RELOC_MIPS_GOT16 | |
3425 | || *r == BFD_RELOC_MIPS_CALL16 | |
438c16b8 TS |
3426 | || *r == BFD_RELOC_MIPS_GOT_DISP |
3427 | || *r == BFD_RELOC_MIPS_GOT_PAGE | |
3428 | || *r == BFD_RELOC_MIPS_GOT_OFST | |
f6688943 | 3429 | || *r == BFD_RELOC_MIPS_GOT_LO16 |
3e722fb5 | 3430 | || *r == BFD_RELOC_MIPS_CALL_LO16); |
252b5132 RH |
3431 | continue; |
3432 | ||
3433 | case 'u': | |
6e1304d8 | 3434 | macro_read_relocs (&args, r); |
252b5132 RH |
3435 | assert (ep != NULL |
3436 | && (ep->X_op == O_constant | |
3437 | || (ep->X_op == O_symbol | |
f6688943 TS |
3438 | && (*r == BFD_RELOC_MIPS_HIGHEST |
3439 | || *r == BFD_RELOC_HI16_S | |
3440 | || *r == BFD_RELOC_HI16 | |
3441 | || *r == BFD_RELOC_GPREL16 | |
3442 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
3e722fb5 | 3443 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); |
252b5132 RH |
3444 | continue; |
3445 | ||
3446 | case 'p': | |
3447 | assert (ep != NULL); | |
bad36eac | 3448 | |
252b5132 RH |
3449 | /* |
3450 | * This allows macro() to pass an immediate expression for | |
3451 | * creating short branches without creating a symbol. | |
bad36eac DJ |
3452 | * |
3453 | * We don't allow branch relaxation for these branches, as | |
3454 | * they should only appear in ".set nomacro" anyway. | |
252b5132 RH |
3455 | */ |
3456 | if (ep->X_op == O_constant) | |
3457 | { | |
bad36eac DJ |
3458 | if ((ep->X_add_number & 3) != 0) |
3459 | as_bad (_("branch to misaligned address (0x%lx)"), | |
3460 | (unsigned long) ep->X_add_number); | |
3461 | if ((ep->X_add_number + 0x20000) & ~0x3ffff) | |
3462 | as_bad (_("branch address range overflow (0x%lx)"), | |
3463 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
3464 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; |
3465 | ep = NULL; | |
3466 | } | |
3467 | else | |
0b25d3e6 | 3468 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
3469 | continue; |
3470 | ||
3471 | case 'a': | |
3472 | assert (ep != NULL); | |
f6688943 | 3473 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
3474 | continue; |
3475 | ||
3476 | case 'C': | |
a9e24354 | 3477 | INSERT_OPERAND (COPZ, insn, va_arg (args, unsigned long)); |
252b5132 RH |
3478 | continue; |
3479 | ||
d43b4baf | 3480 | case 'k': |
a9e24354 | 3481 | INSERT_OPERAND (CACHE, insn, va_arg (args, unsigned long)); |
d43b4baf TS |
3482 | continue; |
3483 | ||
252b5132 RH |
3484 | default: |
3485 | internalError (); | |
3486 | } | |
3487 | break; | |
3488 | } | |
3489 | va_end (args); | |
f6688943 | 3490 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3491 | |
4d7206a2 | 3492 | append_insn (&insn, ep, r); |
252b5132 RH |
3493 | } |
3494 | ||
3495 | static void | |
67c0d1eb | 3496 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
17a2f251 | 3497 | va_list args) |
252b5132 | 3498 | { |
1e915849 | 3499 | struct mips_opcode *mo; |
252b5132 | 3500 | struct mips_cl_insn insn; |
f6688943 TS |
3501 | bfd_reloc_code_real_type r[3] |
3502 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 3503 | |
1e915849 RS |
3504 | mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
3505 | assert (mo); | |
3506 | assert (strcmp (name, mo->name) == 0); | |
252b5132 | 3507 | |
1e915849 | 3508 | while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) |
252b5132 | 3509 | { |
1e915849 RS |
3510 | ++mo; |
3511 | assert (mo->name); | |
3512 | assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
3513 | } |
3514 | ||
1e915849 | 3515 | create_insn (&insn, mo); |
252b5132 RH |
3516 | for (;;) |
3517 | { | |
3518 | int c; | |
3519 | ||
3520 | c = *fmt++; | |
3521 | switch (c) | |
3522 | { | |
3523 | case '\0': | |
3524 | break; | |
3525 | ||
3526 | case ',': | |
3527 | case '(': | |
3528 | case ')': | |
3529 | continue; | |
3530 | ||
3531 | case 'y': | |
3532 | case 'w': | |
bf12938e | 3533 | MIPS16_INSERT_OPERAND (RY, insn, va_arg (args, int)); |
252b5132 RH |
3534 | continue; |
3535 | ||
3536 | case 'x': | |
3537 | case 'v': | |
bf12938e | 3538 | MIPS16_INSERT_OPERAND (RX, insn, va_arg (args, int)); |
252b5132 RH |
3539 | continue; |
3540 | ||
3541 | case 'z': | |
bf12938e | 3542 | MIPS16_INSERT_OPERAND (RZ, insn, va_arg (args, int)); |
252b5132 RH |
3543 | continue; |
3544 | ||
3545 | case 'Z': | |
bf12938e | 3546 | MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (args, int)); |
252b5132 RH |
3547 | continue; |
3548 | ||
3549 | case '0': | |
3550 | case 'S': | |
3551 | case 'P': | |
3552 | case 'R': | |
3553 | continue; | |
3554 | ||
3555 | case 'X': | |
bf12938e | 3556 | MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (args, int)); |
252b5132 RH |
3557 | continue; |
3558 | ||
3559 | case 'Y': | |
3560 | { | |
3561 | int regno; | |
3562 | ||
3563 | regno = va_arg (args, int); | |
3564 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
a9e24354 | 3565 | MIPS16_INSERT_OPERAND (REG32R, insn, regno); |
252b5132 RH |
3566 | } |
3567 | continue; | |
3568 | ||
3569 | case '<': | |
3570 | case '>': | |
3571 | case '4': | |
3572 | case '5': | |
3573 | case 'H': | |
3574 | case 'W': | |
3575 | case 'D': | |
3576 | case 'j': | |
3577 | case '8': | |
3578 | case 'V': | |
3579 | case 'C': | |
3580 | case 'U': | |
3581 | case 'k': | |
3582 | case 'K': | |
3583 | case 'p': | |
3584 | case 'q': | |
3585 | { | |
3586 | assert (ep != NULL); | |
3587 | ||
3588 | if (ep->X_op != O_constant) | |
874e8986 | 3589 | *r = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
3590 | else |
3591 | { | |
b34976b6 AM |
3592 | mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE, |
3593 | FALSE, &insn.insn_opcode, &insn.use_extend, | |
c4e7957c | 3594 | &insn.extend); |
252b5132 | 3595 | ep = NULL; |
f6688943 | 3596 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
3597 | } |
3598 | } | |
3599 | continue; | |
3600 | ||
3601 | case '6': | |
bf12938e | 3602 | MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (args, int)); |
252b5132 RH |
3603 | continue; |
3604 | } | |
3605 | ||
3606 | break; | |
3607 | } | |
3608 | ||
f6688943 | 3609 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3610 | |
4d7206a2 | 3611 | append_insn (&insn, ep, r); |
252b5132 RH |
3612 | } |
3613 | ||
2051e8c4 MR |
3614 | /* |
3615 | * Sign-extend 32-bit mode constants that have bit 31 set and all | |
3616 | * higher bits unset. | |
3617 | */ | |
9f872bbe | 3618 | static void |
2051e8c4 MR |
3619 | normalize_constant_expr (expressionS *ex) |
3620 | { | |
9ee2a2d4 | 3621 | if (ex->X_op == O_constant |
2051e8c4 MR |
3622 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) |
3623 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
3624 | - 0x80000000); | |
3625 | } | |
3626 | ||
3627 | /* | |
3628 | * Sign-extend 32-bit mode address offsets that have bit 31 set and | |
3629 | * all higher bits unset. | |
3630 | */ | |
3631 | static void | |
3632 | normalize_address_expr (expressionS *ex) | |
3633 | { | |
3634 | if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) | |
3635 | || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) | |
3636 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
3637 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
3638 | - 0x80000000); | |
3639 | } | |
3640 | ||
438c16b8 TS |
3641 | /* |
3642 | * Generate a "jalr" instruction with a relocation hint to the called | |
3643 | * function. This occurs in NewABI PIC code. | |
3644 | */ | |
3645 | static void | |
67c0d1eb | 3646 | macro_build_jalr (expressionS *ep) |
438c16b8 | 3647 | { |
685736be | 3648 | char *f = NULL; |
b34976b6 | 3649 | |
438c16b8 | 3650 | if (HAVE_NEWABI) |
f21f8242 | 3651 | { |
cc3d92a5 | 3652 | frag_grow (8); |
f21f8242 AO |
3653 | f = frag_more (0); |
3654 | } | |
67c0d1eb | 3655 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); |
438c16b8 | 3656 | if (HAVE_NEWABI) |
f21f8242 | 3657 | fix_new_exp (frag_now, f - frag_now->fr_literal, |
a105a300 | 3658 | 4, ep, FALSE, BFD_RELOC_MIPS_JALR); |
438c16b8 TS |
3659 | } |
3660 | ||
252b5132 RH |
3661 | /* |
3662 | * Generate a "lui" instruction. | |
3663 | */ | |
3664 | static void | |
67c0d1eb | 3665 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 RH |
3666 | { |
3667 | expressionS high_expr; | |
1e915849 | 3668 | const struct mips_opcode *mo; |
252b5132 | 3669 | struct mips_cl_insn insn; |
f6688943 TS |
3670 | bfd_reloc_code_real_type r[3] |
3671 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
5a38dc70 AM |
3672 | const char *name = "lui"; |
3673 | const char *fmt = "t,u"; | |
252b5132 RH |
3674 | |
3675 | assert (! mips_opts.mips16); | |
3676 | ||
4d7206a2 | 3677 | high_expr = *ep; |
252b5132 RH |
3678 | |
3679 | if (high_expr.X_op == O_constant) | |
3680 | { | |
3681 | /* we can compute the instruction now without a relocation entry */ | |
e7d556df TS |
3682 | high_expr.X_add_number = ((high_expr.X_add_number + 0x8000) |
3683 | >> 16) & 0xffff; | |
f6688943 | 3684 | *r = BFD_RELOC_UNUSED; |
252b5132 | 3685 | } |
78e1bb40 | 3686 | else |
252b5132 RH |
3687 | { |
3688 | assert (ep->X_op == O_symbol); | |
bbe506e8 TS |
3689 | /* _gp_disp is a special case, used from s_cpload. |
3690 | __gnu_local_gp is used if mips_no_shared. */ | |
252b5132 | 3691 | assert (mips_pic == NO_PIC |
78e1bb40 | 3692 | || (! HAVE_NEWABI |
aa6975fb ILT |
3693 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
3694 | || (! mips_in_shared | |
bbe506e8 TS |
3695 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
3696 | "__gnu_local_gp") == 0)); | |
f6688943 | 3697 | *r = BFD_RELOC_HI16_S; |
252b5132 RH |
3698 | } |
3699 | ||
1e915849 RS |
3700 | mo = hash_find (op_hash, name); |
3701 | assert (strcmp (name, mo->name) == 0); | |
3702 | assert (strcmp (fmt, mo->args) == 0); | |
3703 | create_insn (&insn, mo); | |
252b5132 | 3704 | |
bf12938e RS |
3705 | insn.insn_opcode = insn.insn_mo->match; |
3706 | INSERT_OPERAND (RT, insn, regnum); | |
f6688943 | 3707 | if (*r == BFD_RELOC_UNUSED) |
252b5132 RH |
3708 | { |
3709 | insn.insn_opcode |= high_expr.X_add_number; | |
4d7206a2 | 3710 | append_insn (&insn, NULL, r); |
252b5132 RH |
3711 | } |
3712 | else | |
4d7206a2 | 3713 | append_insn (&insn, &high_expr, r); |
252b5132 RH |
3714 | } |
3715 | ||
885add95 CD |
3716 | /* Generate a sequence of instructions to do a load or store from a constant |
3717 | offset off of a base register (breg) into/from a target register (treg), | |
3718 | using AT if necessary. */ | |
3719 | static void | |
67c0d1eb RS |
3720 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
3721 | int treg, int breg, int dbl) | |
885add95 CD |
3722 | { |
3723 | assert (ep->X_op == O_constant); | |
3724 | ||
256ab948 | 3725 | /* Sign-extending 32-bit constants makes their handling easier. */ |
2051e8c4 MR |
3726 | if (!dbl) |
3727 | normalize_constant_expr (ep); | |
256ab948 | 3728 | |
67c1ffbe | 3729 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 3730 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
3731 | as_warn (_("operand overflow")); |
3732 | ||
3733 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
3734 | { | |
3735 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 3736 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
3737 | } |
3738 | else | |
3739 | { | |
3740 | /* 32-bit offset, need multiple instructions and AT, like: | |
3741 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
3742 | addu $tempreg,$tempreg,$breg | |
3743 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
3744 | to handle the complete offset. */ | |
67c0d1eb RS |
3745 | macro_build_lui (ep, AT); |
3746 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
3747 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 CD |
3748 | |
3749 | if (mips_opts.noat) | |
8fc2e39e | 3750 | as_bad (_("Macro used $at after \".set noat\"")); |
885add95 CD |
3751 | } |
3752 | } | |
3753 | ||
252b5132 RH |
3754 | /* set_at() |
3755 | * Generates code to set the $at register to true (one) | |
3756 | * if reg is less than the immediate expression. | |
3757 | */ | |
3758 | static void | |
67c0d1eb | 3759 | set_at (int reg, int unsignedp) |
252b5132 RH |
3760 | { |
3761 | if (imm_expr.X_op == O_constant | |
3762 | && imm_expr.X_add_number >= -0x8000 | |
3763 | && imm_expr.X_add_number < 0x8000) | |
67c0d1eb RS |
3764 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
3765 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
3766 | else |
3767 | { | |
67c0d1eb RS |
3768 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
3769 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); | |
252b5132 RH |
3770 | } |
3771 | } | |
3772 | ||
3773 | /* Warn if an expression is not a constant. */ | |
3774 | ||
3775 | static void | |
17a2f251 | 3776 | check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) |
252b5132 RH |
3777 | { |
3778 | if (ex->X_op == O_big) | |
3779 | as_bad (_("unsupported large constant")); | |
3780 | else if (ex->X_op != O_constant) | |
9ee2a2d4 MR |
3781 | as_bad (_("Instruction %s requires absolute expression"), |
3782 | ip->insn_mo->name); | |
13757d0c | 3783 | |
9ee2a2d4 MR |
3784 | if (HAVE_32BIT_GPRS) |
3785 | normalize_constant_expr (ex); | |
252b5132 RH |
3786 | } |
3787 | ||
3788 | /* Count the leading zeroes by performing a binary chop. This is a | |
3789 | bulky bit of source, but performance is a LOT better for the | |
3790 | majority of values than a simple loop to count the bits: | |
3791 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
3792 | if ((v) & (1 << (31 - lcnt))) | |
3793 | break; | |
3794 | However it is not code size friendly, and the gain will drop a bit | |
3795 | on certain cached systems. | |
3796 | */ | |
3797 | #define COUNT_TOP_ZEROES(v) \ | |
3798 | (((v) & ~0xffff) == 0 \ | |
3799 | ? ((v) & ~0xff) == 0 \ | |
3800 | ? ((v) & ~0xf) == 0 \ | |
3801 | ? ((v) & ~0x3) == 0 \ | |
3802 | ? ((v) & ~0x1) == 0 \ | |
3803 | ? !(v) \ | |
3804 | ? 32 \ | |
3805 | : 31 \ | |
3806 | : 30 \ | |
3807 | : ((v) & ~0x7) == 0 \ | |
3808 | ? 29 \ | |
3809 | : 28 \ | |
3810 | : ((v) & ~0x3f) == 0 \ | |
3811 | ? ((v) & ~0x1f) == 0 \ | |
3812 | ? 27 \ | |
3813 | : 26 \ | |
3814 | : ((v) & ~0x7f) == 0 \ | |
3815 | ? 25 \ | |
3816 | : 24 \ | |
3817 | : ((v) & ~0xfff) == 0 \ | |
3818 | ? ((v) & ~0x3ff) == 0 \ | |
3819 | ? ((v) & ~0x1ff) == 0 \ | |
3820 | ? 23 \ | |
3821 | : 22 \ | |
3822 | : ((v) & ~0x7ff) == 0 \ | |
3823 | ? 21 \ | |
3824 | : 20 \ | |
3825 | : ((v) & ~0x3fff) == 0 \ | |
3826 | ? ((v) & ~0x1fff) == 0 \ | |
3827 | ? 19 \ | |
3828 | : 18 \ | |
3829 | : ((v) & ~0x7fff) == 0 \ | |
3830 | ? 17 \ | |
3831 | : 16 \ | |
3832 | : ((v) & ~0xffffff) == 0 \ | |
3833 | ? ((v) & ~0xfffff) == 0 \ | |
3834 | ? ((v) & ~0x3ffff) == 0 \ | |
3835 | ? ((v) & ~0x1ffff) == 0 \ | |
3836 | ? 15 \ | |
3837 | : 14 \ | |
3838 | : ((v) & ~0x7ffff) == 0 \ | |
3839 | ? 13 \ | |
3840 | : 12 \ | |
3841 | : ((v) & ~0x3fffff) == 0 \ | |
3842 | ? ((v) & ~0x1fffff) == 0 \ | |
3843 | ? 11 \ | |
3844 | : 10 \ | |
3845 | : ((v) & ~0x7fffff) == 0 \ | |
3846 | ? 9 \ | |
3847 | : 8 \ | |
3848 | : ((v) & ~0xfffffff) == 0 \ | |
3849 | ? ((v) & ~0x3ffffff) == 0 \ | |
3850 | ? ((v) & ~0x1ffffff) == 0 \ | |
3851 | ? 7 \ | |
3852 | : 6 \ | |
3853 | : ((v) & ~0x7ffffff) == 0 \ | |
3854 | ? 5 \ | |
3855 | : 4 \ | |
3856 | : ((v) & ~0x3fffffff) == 0 \ | |
3857 | ? ((v) & ~0x1fffffff) == 0 \ | |
3858 | ? 3 \ | |
3859 | : 2 \ | |
3860 | : ((v) & ~0x7fffffff) == 0 \ | |
3861 | ? 1 \ | |
3862 | : 0) | |
3863 | ||
3864 | /* load_register() | |
67c1ffbe | 3865 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
3866 | * an absolute expression value into a register. |
3867 | */ | |
3868 | static void | |
67c0d1eb | 3869 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
3870 | { |
3871 | int freg; | |
3872 | expressionS hi32, lo32; | |
3873 | ||
3874 | if (ep->X_op != O_big) | |
3875 | { | |
3876 | assert (ep->X_op == O_constant); | |
256ab948 TS |
3877 | |
3878 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
2051e8c4 MR |
3879 | if (!dbl) |
3880 | normalize_constant_expr (ep); | |
256ab948 TS |
3881 | |
3882 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
3883 | { |
3884 | /* We can handle 16 bit signed values with an addiu to | |
3885 | $zero. No need to ever use daddiu here, since $zero and | |
3886 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 3887 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3888 | return; |
3889 | } | |
3890 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
3891 | { | |
3892 | /* We can handle 16 bit unsigned values with an ori to | |
3893 | $zero. */ | |
67c0d1eb | 3894 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3895 | return; |
3896 | } | |
256ab948 | 3897 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
3898 | { |
3899 | /* 32 bit values require an lui. */ | |
67c0d1eb | 3900 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 3901 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 3902 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
3903 | return; |
3904 | } | |
3905 | } | |
3906 | ||
3907 | /* The value is larger than 32 bits. */ | |
3908 | ||
2051e8c4 | 3909 | if (!dbl || HAVE_32BIT_GPRS) |
252b5132 | 3910 | { |
55e08f71 NC |
3911 | char value[32]; |
3912 | ||
3913 | sprintf_vma (value, ep->X_add_number); | |
20e1fcfd | 3914 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
67c0d1eb | 3915 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3916 | return; |
3917 | } | |
3918 | ||
3919 | if (ep->X_op != O_big) | |
3920 | { | |
3921 | hi32 = *ep; | |
3922 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3923 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3924 | hi32.X_add_number &= 0xffffffff; | |
3925 | lo32 = *ep; | |
3926 | lo32.X_add_number &= 0xffffffff; | |
3927 | } | |
3928 | else | |
3929 | { | |
3930 | assert (ep->X_add_number > 2); | |
3931 | if (ep->X_add_number == 3) | |
3932 | generic_bignum[3] = 0; | |
3933 | else if (ep->X_add_number > 4) | |
3934 | as_bad (_("Number larger than 64 bits")); | |
3935 | lo32.X_op = O_constant; | |
3936 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
3937 | hi32.X_op = O_constant; | |
3938 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
3939 | } | |
3940 | ||
3941 | if (hi32.X_add_number == 0) | |
3942 | freg = 0; | |
3943 | else | |
3944 | { | |
3945 | int shift, bit; | |
3946 | unsigned long hi, lo; | |
3947 | ||
956cd1d6 | 3948 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
3949 | { |
3950 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
3951 | { | |
67c0d1eb | 3952 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
3953 | return; |
3954 | } | |
3955 | if (lo32.X_add_number & 0x80000000) | |
3956 | { | |
67c0d1eb | 3957 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 3958 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 3959 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
3960 | return; |
3961 | } | |
3962 | } | |
252b5132 RH |
3963 | |
3964 | /* Check for 16bit shifted constant. We know that hi32 is | |
3965 | non-zero, so start the mask on the first bit of the hi32 | |
3966 | value. */ | |
3967 | shift = 17; | |
3968 | do | |
beae10d5 KH |
3969 | { |
3970 | unsigned long himask, lomask; | |
3971 | ||
3972 | if (shift < 32) | |
3973 | { | |
3974 | himask = 0xffff >> (32 - shift); | |
3975 | lomask = (0xffff << shift) & 0xffffffff; | |
3976 | } | |
3977 | else | |
3978 | { | |
3979 | himask = 0xffff << (shift - 32); | |
3980 | lomask = 0; | |
3981 | } | |
3982 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
3983 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
3984 | { | |
3985 | expressionS tmp; | |
3986 | ||
3987 | tmp.X_op = O_constant; | |
3988 | if (shift < 32) | |
3989 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
3990 | | (lo32.X_add_number >> shift)); | |
3991 | else | |
3992 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb RS |
3993 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
3994 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<", | |
3995 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
3996 | return; |
3997 | } | |
f9419b05 | 3998 | ++shift; |
beae10d5 KH |
3999 | } |
4000 | while (shift <= (64 - 16)); | |
252b5132 RH |
4001 | |
4002 | /* Find the bit number of the lowest one bit, and store the | |
4003 | shifted value in hi/lo. */ | |
4004 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
4005 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
4006 | if (lo != 0) | |
4007 | { | |
4008 | bit = 0; | |
4009 | while ((lo & 1) == 0) | |
4010 | { | |
4011 | lo >>= 1; | |
4012 | ++bit; | |
4013 | } | |
4014 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
4015 | hi >>= bit; | |
4016 | } | |
4017 | else | |
4018 | { | |
4019 | bit = 32; | |
4020 | while ((hi & 1) == 0) | |
4021 | { | |
4022 | hi >>= 1; | |
4023 | ++bit; | |
4024 | } | |
4025 | lo = hi; | |
4026 | hi = 0; | |
4027 | } | |
4028 | ||
4029 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
4030 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
4031 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
4032 | { |
4033 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 4034 | if (shift != 0) |
beae10d5 | 4035 | { |
252b5132 RH |
4036 | expressionS tmp; |
4037 | ||
4038 | /* This instruction will set the register to be all | |
4039 | ones. */ | |
beae10d5 KH |
4040 | tmp.X_op = O_constant; |
4041 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 4042 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
4043 | if (bit != 0) |
4044 | { | |
4045 | bit += shift; | |
67c0d1eb RS |
4046 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<", |
4047 | reg, reg, (bit >= 32) ? bit - 32 : bit); | |
beae10d5 | 4048 | } |
67c0d1eb RS |
4049 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<", |
4050 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
4051 | return; |
4052 | } | |
4053 | } | |
252b5132 RH |
4054 | |
4055 | /* Sign extend hi32 before calling load_register, because we can | |
4056 | generally get better code when we load a sign extended value. */ | |
4057 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 4058 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 4059 | load_register (reg, &hi32, 0); |
252b5132 RH |
4060 | freg = reg; |
4061 | } | |
4062 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
4063 | { | |
4064 | if (freg != 0) | |
4065 | { | |
67c0d1eb | 4066 | macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0); |
252b5132 RH |
4067 | freg = reg; |
4068 | } | |
4069 | } | |
4070 | else | |
4071 | { | |
4072 | expressionS mid16; | |
4073 | ||
956cd1d6 | 4074 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 4075 | { |
67c0d1eb RS |
4076 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
4077 | macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0); | |
beae10d5 KH |
4078 | return; |
4079 | } | |
252b5132 RH |
4080 | |
4081 | if (freg != 0) | |
4082 | { | |
67c0d1eb | 4083 | macro_build (NULL, "dsll", "d,w,<", reg, freg, 16); |
252b5132 RH |
4084 | freg = reg; |
4085 | } | |
4086 | mid16 = lo32; | |
4087 | mid16.X_add_number >>= 16; | |
67c0d1eb RS |
4088 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
4089 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
252b5132 RH |
4090 | freg = reg; |
4091 | } | |
4092 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 4093 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
4094 | } |
4095 | ||
269137b2 TS |
4096 | static inline void |
4097 | load_delay_nop (void) | |
4098 | { | |
4099 | if (!gpr_interlocks) | |
4100 | macro_build (NULL, "nop", ""); | |
4101 | } | |
4102 | ||
252b5132 RH |
4103 | /* Load an address into a register. */ |
4104 | ||
4105 | static void | |
67c0d1eb | 4106 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 4107 | { |
252b5132 RH |
4108 | if (ep->X_op != O_constant |
4109 | && ep->X_op != O_symbol) | |
4110 | { | |
4111 | as_bad (_("expression too complex")); | |
4112 | ep->X_op = O_constant; | |
4113 | } | |
4114 | ||
4115 | if (ep->X_op == O_constant) | |
4116 | { | |
67c0d1eb | 4117 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
4118 | return; |
4119 | } | |
4120 | ||
4121 | if (mips_pic == NO_PIC) | |
4122 | { | |
4123 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 4124 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
4125 | Otherwise we want |
4126 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
4127 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 4128 | If we have an addend, we always use the latter form. |
76b3015f | 4129 | |
d6bc6245 TS |
4130 | With 64bit address space and a usable $at we want |
4131 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4132 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
4133 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4134 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
4135 | dsll32 $reg,0 | |
3a482fd5 | 4136 | daddu $reg,$reg,$at |
76b3015f | 4137 | |
c03099e6 | 4138 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
4139 | on superscalar processors. |
4140 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4141 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4142 | dsll $reg,16 | |
4143 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
4144 | dsll $reg,16 | |
4145 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
6caf9ef4 TS |
4146 | |
4147 | For GP relative symbols in 64bit address space we can use | |
4148 | the same sequence as in 32bit address space. */ | |
aed1a261 | 4149 | if (HAVE_64BIT_SYMBOLS) |
d6bc6245 | 4150 | { |
6caf9ef4 TS |
4151 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
4152 | && !nopic_need_relax (ep->X_add_symbol, 1)) | |
4153 | { | |
4154 | relax_start (ep->X_add_symbol); | |
4155 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
4156 | mips_gp_register, BFD_RELOC_GPREL16); | |
4157 | relax_switch (); | |
4158 | } | |
d6bc6245 | 4159 | |
b8285c27 | 4160 | if (*used_at == 0 && !mips_opts.noat) |
d6bc6245 | 4161 | { |
67c0d1eb RS |
4162 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
4163 | macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S); | |
4164 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
4165 | BFD_RELOC_MIPS_HIGHER); | |
4166 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
4167 | macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0); | |
4168 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); | |
d6bc6245 TS |
4169 | *used_at = 1; |
4170 | } | |
4171 | else | |
4172 | { | |
67c0d1eb RS |
4173 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
4174 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
4175 | BFD_RELOC_MIPS_HIGHER); | |
4176 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
4177 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); | |
4178 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
4179 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); | |
d6bc6245 | 4180 | } |
6caf9ef4 TS |
4181 | |
4182 | if (mips_relax.sequence) | |
4183 | relax_end (); | |
d6bc6245 | 4184 | } |
252b5132 RH |
4185 | else |
4186 | { | |
d6bc6245 | 4187 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 4188 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
d6bc6245 | 4189 | { |
4d7206a2 | 4190 | relax_start (ep->X_add_symbol); |
67c0d1eb | 4191 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 4192 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 4193 | relax_switch (); |
d6bc6245 | 4194 | } |
67c0d1eb RS |
4195 | macro_build_lui (ep, reg); |
4196 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
4197 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
4198 | if (mips_relax.sequence) |
4199 | relax_end (); | |
d6bc6245 | 4200 | } |
252b5132 | 4201 | } |
0a44bf69 | 4202 | else if (!mips_big_got) |
252b5132 RH |
4203 | { |
4204 | expressionS ex; | |
4205 | ||
4206 | /* If this is a reference to an external symbol, we want | |
4207 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4208 | Otherwise we want | |
4209 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4210 | nop | |
4211 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
4212 | If there is a constant, it must be added in after. |
4213 | ||
ed6fb7bd | 4214 | If we have NewABI, we want |
f5040a92 AO |
4215 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
4216 | unless we're referencing a global symbol with a non-zero | |
4217 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
4218 | if (HAVE_NEWABI) |
4219 | { | |
f5040a92 AO |
4220 | if (ep->X_add_number) |
4221 | { | |
4d7206a2 | 4222 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 4223 | ep->X_add_number = 0; |
4d7206a2 | 4224 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4225 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
4226 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
4227 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
4228 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4229 | ex.X_op = O_constant; | |
67c0d1eb | 4230 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 4231 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 4232 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 4233 | relax_switch (); |
f5040a92 | 4234 | } |
67c0d1eb | 4235 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4236 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
4237 | if (mips_relax.sequence) |
4238 | relax_end (); | |
ed6fb7bd SC |
4239 | } |
4240 | else | |
4241 | { | |
f5040a92 AO |
4242 | ex.X_add_number = ep->X_add_number; |
4243 | ep->X_add_number = 0; | |
67c0d1eb RS |
4244 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
4245 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 4246 | load_delay_nop (); |
4d7206a2 RS |
4247 | relax_start (ep->X_add_symbol); |
4248 | relax_switch (); | |
67c0d1eb | 4249 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 4250 | BFD_RELOC_LO16); |
4d7206a2 | 4251 | relax_end (); |
ed6fb7bd | 4252 | |
f5040a92 AO |
4253 | if (ex.X_add_number != 0) |
4254 | { | |
4255 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
4256 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4257 | ex.X_op = O_constant; | |
67c0d1eb | 4258 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 4259 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 4260 | } |
252b5132 RH |
4261 | } |
4262 | } | |
0a44bf69 | 4263 | else if (mips_big_got) |
252b5132 RH |
4264 | { |
4265 | expressionS ex; | |
252b5132 RH |
4266 | |
4267 | /* This is the large GOT case. If this is a reference to an | |
4268 | external symbol, we want | |
4269 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4270 | addu $reg,$reg,$gp | |
4271 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
4272 | |
4273 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
4274 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
4275 | nop | |
4276 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 4277 | If there is a constant, it must be added in after. |
f5040a92 AO |
4278 | |
4279 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
4280 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
4281 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 4282 | */ |
438c16b8 TS |
4283 | if (HAVE_NEWABI) |
4284 | { | |
4d7206a2 | 4285 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 4286 | ep->X_add_number = 0; |
4d7206a2 | 4287 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4288 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
4289 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
4290 | reg, reg, mips_gp_register); | |
4291 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
4292 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
4293 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
4294 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4295 | else if (ex.X_add_number) | |
4296 | { | |
4297 | ex.X_op = O_constant; | |
67c0d1eb RS |
4298 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4299 | BFD_RELOC_LO16); | |
f5040a92 AO |
4300 | } |
4301 | ||
4302 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 4303 | relax_switch (); |
67c0d1eb | 4304 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4305 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
4306 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4307 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 4308 | relax_end (); |
438c16b8 | 4309 | } |
252b5132 | 4310 | else |
438c16b8 | 4311 | { |
f5040a92 AO |
4312 | ex.X_add_number = ep->X_add_number; |
4313 | ep->X_add_number = 0; | |
4d7206a2 | 4314 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4315 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
4316 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
4317 | reg, reg, mips_gp_register); | |
4318 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
4319 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
4320 | relax_switch (); |
4321 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
4322 | { |
4323 | /* We need a nop before loading from $gp. This special | |
4324 | check is required because the lui which starts the main | |
4325 | instruction stream does not refer to $gp, and so will not | |
4326 | insert the nop which may be required. */ | |
67c0d1eb | 4327 | macro_build (NULL, "nop", ""); |
438c16b8 | 4328 | } |
67c0d1eb | 4329 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4330 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 4331 | load_delay_nop (); |
67c0d1eb | 4332 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 4333 | BFD_RELOC_LO16); |
4d7206a2 | 4334 | relax_end (); |
438c16b8 | 4335 | |
f5040a92 AO |
4336 | if (ex.X_add_number != 0) |
4337 | { | |
4338 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
4339 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4340 | ex.X_op = O_constant; | |
67c0d1eb RS |
4341 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4342 | BFD_RELOC_LO16); | |
f5040a92 | 4343 | } |
252b5132 RH |
4344 | } |
4345 | } | |
252b5132 RH |
4346 | else |
4347 | abort (); | |
8fc2e39e TS |
4348 | |
4349 | if (mips_opts.noat && *used_at == 1) | |
4350 | as_bad (_("Macro used $at after \".set noat\"")); | |
252b5132 RH |
4351 | } |
4352 | ||
ea1fb5dc RS |
4353 | /* Move the contents of register SOURCE into register DEST. */ |
4354 | ||
4355 | static void | |
67c0d1eb | 4356 | move_register (int dest, int source) |
ea1fb5dc | 4357 | { |
67c0d1eb RS |
4358 | macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", |
4359 | dest, source, 0); | |
ea1fb5dc RS |
4360 | } |
4361 | ||
4d7206a2 | 4362 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
4363 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
4364 | The two alternatives are: | |
4d7206a2 RS |
4365 | |
4366 | Global symbol Local sybmol | |
4367 | ------------- ------------ | |
4368 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
4369 | ... ... | |
4370 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
4371 | ||
4372 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
4373 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
4374 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
4375 | |
4376 | static void | |
67c0d1eb | 4377 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4378 | { |
4379 | expressionS global; | |
4380 | ||
4381 | global = *local; | |
4382 | global.X_add_number = 0; | |
4383 | ||
4384 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
4385 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4386 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 4387 | relax_switch (); |
67c0d1eb RS |
4388 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4389 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
4390 | relax_end (); |
4391 | } | |
4392 | ||
4393 | static void | |
67c0d1eb | 4394 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4395 | { |
4396 | expressionS global; | |
4397 | ||
4398 | global.X_op = O_constant; | |
4399 | global.X_op_symbol = NULL; | |
4400 | global.X_add_symbol = NULL; | |
4401 | global.X_add_number = local->X_add_number; | |
4402 | ||
4403 | relax_start (local->X_add_symbol); | |
67c0d1eb | 4404 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
4405 | dest, dest, BFD_RELOC_LO16); |
4406 | relax_switch (); | |
67c0d1eb | 4407 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
4408 | relax_end (); |
4409 | } | |
4410 | ||
f6a22291 MR |
4411 | static void |
4412 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
4413 | { | |
4414 | expressionS global; | |
4415 | int hold_mips_optimize; | |
4416 | ||
4417 | global.X_op = O_constant; | |
4418 | global.X_op_symbol = NULL; | |
4419 | global.X_add_symbol = NULL; | |
4420 | global.X_add_number = local->X_add_number; | |
4421 | ||
4422 | relax_start (local->X_add_symbol); | |
4423 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
4424 | relax_switch (); | |
4425 | /* Set mips_optimize around the lui instruction to avoid | |
4426 | inserting an unnecessary nop after the lw. */ | |
4427 | hold_mips_optimize = mips_optimize; | |
4428 | mips_optimize = 2; | |
4429 | macro_build_lui (&global, tmp); | |
4430 | mips_optimize = hold_mips_optimize; | |
4431 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
4432 | relax_end (); | |
4433 | ||
4434 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
4435 | } | |
4436 | ||
252b5132 RH |
4437 | /* |
4438 | * Build macros | |
4439 | * This routine implements the seemingly endless macro or synthesized | |
4440 | * instructions and addressing modes in the mips assembly language. Many | |
4441 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 4442 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
4443 | * this verbose method. Others are not simple macros but are more like |
4444 | * optimizing code generation. | |
4445 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 4446 | * consecutively that would load AT with the upper half of the same address. |
252b5132 RH |
4447 | * The ensuing load upper instructions are ommited. This implies some kind |
4448 | * of global optimization. We currently only optimize within a single macro. | |
4449 | * For many of the load and store macros if the address is specified as a | |
4450 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
4451 | * first load register 'at' with zero and use it as the base register. The | |
4452 | * mips assembler simply uses register $zero. Just one tiny optimization | |
4453 | * we're missing. | |
4454 | */ | |
4455 | static void | |
17a2f251 | 4456 | macro (struct mips_cl_insn *ip) |
252b5132 RH |
4457 | { |
4458 | register int treg, sreg, dreg, breg; | |
4459 | int tempreg; | |
4460 | int mask; | |
43841e91 | 4461 | int used_at = 0; |
252b5132 RH |
4462 | expressionS expr1; |
4463 | const char *s; | |
4464 | const char *s2; | |
4465 | const char *fmt; | |
4466 | int likely = 0; | |
4467 | int dbl = 0; | |
4468 | int coproc = 0; | |
4469 | int lr = 0; | |
4470 | int imm = 0; | |
1abe91b1 | 4471 | int call = 0; |
252b5132 | 4472 | int off; |
67c0d1eb | 4473 | offsetT maxnum; |
252b5132 | 4474 | bfd_reloc_code_real_type r; |
252b5132 RH |
4475 | int hold_mips_optimize; |
4476 | ||
4477 | assert (! mips_opts.mips16); | |
4478 | ||
4479 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
4480 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
4481 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
4482 | mask = ip->insn_mo->mask; | |
4483 | ||
4484 | expr1.X_op = O_constant; | |
4485 | expr1.X_op_symbol = NULL; | |
4486 | expr1.X_add_symbol = NULL; | |
4487 | expr1.X_add_number = 1; | |
4488 | ||
4489 | switch (mask) | |
4490 | { | |
4491 | case M_DABS: | |
4492 | dbl = 1; | |
4493 | case M_ABS: | |
4494 | /* bgez $a0,.+12 | |
4495 | move v0,$a0 | |
4496 | sub v0,$zero,$a0 | |
4497 | */ | |
4498 | ||
7d10b47d | 4499 | start_noreorder (); |
252b5132 RH |
4500 | |
4501 | expr1.X_add_number = 8; | |
67c0d1eb | 4502 | macro_build (&expr1, "bgez", "s,p", sreg); |
252b5132 | 4503 | if (dreg == sreg) |
67c0d1eb | 4504 | macro_build (NULL, "nop", "", 0); |
252b5132 | 4505 | else |
67c0d1eb RS |
4506 | move_register (dreg, sreg); |
4507 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); | |
252b5132 | 4508 | |
7d10b47d | 4509 | end_noreorder (); |
8fc2e39e | 4510 | break; |
252b5132 RH |
4511 | |
4512 | case M_ADD_I: | |
4513 | s = "addi"; | |
4514 | s2 = "add"; | |
4515 | goto do_addi; | |
4516 | case M_ADDU_I: | |
4517 | s = "addiu"; | |
4518 | s2 = "addu"; | |
4519 | goto do_addi; | |
4520 | case M_DADD_I: | |
4521 | dbl = 1; | |
4522 | s = "daddi"; | |
4523 | s2 = "dadd"; | |
4524 | goto do_addi; | |
4525 | case M_DADDU_I: | |
4526 | dbl = 1; | |
4527 | s = "daddiu"; | |
4528 | s2 = "daddu"; | |
4529 | do_addi: | |
4530 | if (imm_expr.X_op == O_constant | |
4531 | && imm_expr.X_add_number >= -0x8000 | |
4532 | && imm_expr.X_add_number < 0x8000) | |
4533 | { | |
67c0d1eb | 4534 | macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 4535 | break; |
252b5132 | 4536 | } |
8fc2e39e | 4537 | used_at = 1; |
67c0d1eb RS |
4538 | load_register (AT, &imm_expr, dbl); |
4539 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4540 | break; |
4541 | ||
4542 | case M_AND_I: | |
4543 | s = "andi"; | |
4544 | s2 = "and"; | |
4545 | goto do_bit; | |
4546 | case M_OR_I: | |
4547 | s = "ori"; | |
4548 | s2 = "or"; | |
4549 | goto do_bit; | |
4550 | case M_NOR_I: | |
4551 | s = ""; | |
4552 | s2 = "nor"; | |
4553 | goto do_bit; | |
4554 | case M_XOR_I: | |
4555 | s = "xori"; | |
4556 | s2 = "xor"; | |
4557 | do_bit: | |
4558 | if (imm_expr.X_op == O_constant | |
4559 | && imm_expr.X_add_number >= 0 | |
4560 | && imm_expr.X_add_number < 0x10000) | |
4561 | { | |
4562 | if (mask != M_NOR_I) | |
67c0d1eb | 4563 | macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
4564 | else |
4565 | { | |
67c0d1eb RS |
4566 | macro_build (&imm_expr, "ori", "t,r,i", |
4567 | treg, sreg, BFD_RELOC_LO16); | |
4568 | macro_build (NULL, "nor", "d,v,t", treg, treg, 0); | |
252b5132 | 4569 | } |
8fc2e39e | 4570 | break; |
252b5132 RH |
4571 | } |
4572 | ||
8fc2e39e | 4573 | used_at = 1; |
67c0d1eb RS |
4574 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4575 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4576 | break; |
4577 | ||
4578 | case M_BEQ_I: | |
4579 | s = "beq"; | |
4580 | goto beq_i; | |
4581 | case M_BEQL_I: | |
4582 | s = "beql"; | |
4583 | likely = 1; | |
4584 | goto beq_i; | |
4585 | case M_BNE_I: | |
4586 | s = "bne"; | |
4587 | goto beq_i; | |
4588 | case M_BNEL_I: | |
4589 | s = "bnel"; | |
4590 | likely = 1; | |
4591 | beq_i: | |
4592 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4593 | { | |
67c0d1eb | 4594 | macro_build (&offset_expr, s, "s,t,p", sreg, 0); |
8fc2e39e | 4595 | break; |
252b5132 | 4596 | } |
8fc2e39e | 4597 | used_at = 1; |
67c0d1eb RS |
4598 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4599 | macro_build (&offset_expr, s, "s,t,p", sreg, AT); | |
252b5132 RH |
4600 | break; |
4601 | ||
4602 | case M_BGEL: | |
4603 | likely = 1; | |
4604 | case M_BGE: | |
4605 | if (treg == 0) | |
4606 | { | |
67c0d1eb | 4607 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
8fc2e39e | 4608 | break; |
252b5132 RH |
4609 | } |
4610 | if (sreg == 0) | |
4611 | { | |
67c0d1eb | 4612 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg); |
8fc2e39e | 4613 | break; |
252b5132 | 4614 | } |
8fc2e39e | 4615 | used_at = 1; |
67c0d1eb RS |
4616 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
4617 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4618 | break; |
4619 | ||
4620 | case M_BGTL_I: | |
4621 | likely = 1; | |
4622 | case M_BGT_I: | |
4623 | /* check for > max integer */ | |
4624 | maxnum = 0x7fffffff; | |
ca4e0257 | 4625 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4626 | { |
4627 | maxnum <<= 16; | |
4628 | maxnum |= 0xffff; | |
4629 | maxnum <<= 16; | |
4630 | maxnum |= 0xffff; | |
4631 | } | |
4632 | if (imm_expr.X_op == O_constant | |
4633 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4634 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4635 | { |
4636 | do_false: | |
4637 | /* result is always false */ | |
4638 | if (! likely) | |
67c0d1eb | 4639 | macro_build (NULL, "nop", "", 0); |
252b5132 | 4640 | else |
67c0d1eb | 4641 | macro_build (&offset_expr, "bnel", "s,t,p", 0, 0); |
8fc2e39e | 4642 | break; |
252b5132 RH |
4643 | } |
4644 | if (imm_expr.X_op != O_constant) | |
4645 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4646 | ++imm_expr.X_add_number; |
252b5132 RH |
4647 | /* FALLTHROUGH */ |
4648 | case M_BGE_I: | |
4649 | case M_BGEL_I: | |
4650 | if (mask == M_BGEL_I) | |
4651 | likely = 1; | |
4652 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4653 | { | |
67c0d1eb | 4654 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
8fc2e39e | 4655 | break; |
252b5132 RH |
4656 | } |
4657 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4658 | { | |
67c0d1eb | 4659 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
8fc2e39e | 4660 | break; |
252b5132 RH |
4661 | } |
4662 | maxnum = 0x7fffffff; | |
ca4e0257 | 4663 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4664 | { |
4665 | maxnum <<= 16; | |
4666 | maxnum |= 0xffff; | |
4667 | maxnum <<= 16; | |
4668 | maxnum |= 0xffff; | |
4669 | } | |
4670 | maxnum = - maxnum - 1; | |
4671 | if (imm_expr.X_op == O_constant | |
4672 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 4673 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4674 | { |
4675 | do_true: | |
4676 | /* result is always true */ | |
4677 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
67c0d1eb | 4678 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 4679 | break; |
252b5132 | 4680 | } |
8fc2e39e | 4681 | used_at = 1; |
67c0d1eb RS |
4682 | set_at (sreg, 0); |
4683 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4684 | break; |
4685 | ||
4686 | case M_BGEUL: | |
4687 | likely = 1; | |
4688 | case M_BGEU: | |
4689 | if (treg == 0) | |
4690 | goto do_true; | |
4691 | if (sreg == 0) | |
4692 | { | |
67c0d1eb | 4693 | macro_build (&offset_expr, likely ? "beql" : "beq", |
17a2f251 | 4694 | "s,t,p", 0, treg); |
8fc2e39e | 4695 | break; |
252b5132 | 4696 | } |
8fc2e39e | 4697 | used_at = 1; |
67c0d1eb RS |
4698 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
4699 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4700 | break; |
4701 | ||
4702 | case M_BGTUL_I: | |
4703 | likely = 1; | |
4704 | case M_BGTU_I: | |
4705 | if (sreg == 0 | |
ca4e0257 | 4706 | || (HAVE_32BIT_GPRS |
252b5132 | 4707 | && imm_expr.X_op == O_constant |
956cd1d6 | 4708 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4709 | goto do_false; |
4710 | if (imm_expr.X_op != O_constant) | |
4711 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4712 | ++imm_expr.X_add_number; |
252b5132 RH |
4713 | /* FALLTHROUGH */ |
4714 | case M_BGEU_I: | |
4715 | case M_BGEUL_I: | |
4716 | if (mask == M_BGEUL_I) | |
4717 | likely = 1; | |
4718 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4719 | goto do_true; | |
4720 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4721 | { | |
67c0d1eb | 4722 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4723 | "s,t,p", sreg, 0); |
8fc2e39e | 4724 | break; |
252b5132 | 4725 | } |
8fc2e39e | 4726 | used_at = 1; |
67c0d1eb RS |
4727 | set_at (sreg, 1); |
4728 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4729 | break; |
4730 | ||
4731 | case M_BGTL: | |
4732 | likely = 1; | |
4733 | case M_BGT: | |
4734 | if (treg == 0) | |
4735 | { | |
67c0d1eb | 4736 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
8fc2e39e | 4737 | break; |
252b5132 RH |
4738 | } |
4739 | if (sreg == 0) | |
4740 | { | |
67c0d1eb | 4741 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg); |
8fc2e39e | 4742 | break; |
252b5132 | 4743 | } |
8fc2e39e | 4744 | used_at = 1; |
67c0d1eb RS |
4745 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
4746 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4747 | break; |
4748 | ||
4749 | case M_BGTUL: | |
4750 | likely = 1; | |
4751 | case M_BGTU: | |
4752 | if (treg == 0) | |
4753 | { | |
67c0d1eb | 4754 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4755 | "s,t,p", sreg, 0); |
8fc2e39e | 4756 | break; |
252b5132 RH |
4757 | } |
4758 | if (sreg == 0) | |
4759 | goto do_false; | |
8fc2e39e | 4760 | used_at = 1; |
67c0d1eb RS |
4761 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
4762 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4763 | break; |
4764 | ||
4765 | case M_BLEL: | |
4766 | likely = 1; | |
4767 | case M_BLE: | |
4768 | if (treg == 0) | |
4769 | { | |
67c0d1eb | 4770 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
8fc2e39e | 4771 | break; |
252b5132 RH |
4772 | } |
4773 | if (sreg == 0) | |
4774 | { | |
67c0d1eb | 4775 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg); |
8fc2e39e | 4776 | break; |
252b5132 | 4777 | } |
8fc2e39e | 4778 | used_at = 1; |
67c0d1eb RS |
4779 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
4780 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4781 | break; |
4782 | ||
4783 | case M_BLEL_I: | |
4784 | likely = 1; | |
4785 | case M_BLE_I: | |
4786 | maxnum = 0x7fffffff; | |
ca4e0257 | 4787 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4788 | { |
4789 | maxnum <<= 16; | |
4790 | maxnum |= 0xffff; | |
4791 | maxnum <<= 16; | |
4792 | maxnum |= 0xffff; | |
4793 | } | |
4794 | if (imm_expr.X_op == O_constant | |
4795 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4796 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4797 | goto do_true; |
4798 | if (imm_expr.X_op != O_constant) | |
4799 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4800 | ++imm_expr.X_add_number; |
252b5132 RH |
4801 | /* FALLTHROUGH */ |
4802 | case M_BLT_I: | |
4803 | case M_BLTL_I: | |
4804 | if (mask == M_BLTL_I) | |
4805 | likely = 1; | |
4806 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4807 | { | |
67c0d1eb | 4808 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
8fc2e39e | 4809 | break; |
252b5132 RH |
4810 | } |
4811 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4812 | { | |
67c0d1eb | 4813 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
8fc2e39e | 4814 | break; |
252b5132 | 4815 | } |
8fc2e39e | 4816 | used_at = 1; |
67c0d1eb RS |
4817 | set_at (sreg, 0); |
4818 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4819 | break; |
4820 | ||
4821 | case M_BLEUL: | |
4822 | likely = 1; | |
4823 | case M_BLEU: | |
4824 | if (treg == 0) | |
4825 | { | |
67c0d1eb | 4826 | macro_build (&offset_expr, likely ? "beql" : "beq", |
17a2f251 | 4827 | "s,t,p", sreg, 0); |
8fc2e39e | 4828 | break; |
252b5132 RH |
4829 | } |
4830 | if (sreg == 0) | |
4831 | goto do_true; | |
8fc2e39e | 4832 | used_at = 1; |
67c0d1eb RS |
4833 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
4834 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4835 | break; |
4836 | ||
4837 | case M_BLEUL_I: | |
4838 | likely = 1; | |
4839 | case M_BLEU_I: | |
4840 | if (sreg == 0 | |
ca4e0257 | 4841 | || (HAVE_32BIT_GPRS |
252b5132 | 4842 | && imm_expr.X_op == O_constant |
956cd1d6 | 4843 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4844 | goto do_true; |
4845 | if (imm_expr.X_op != O_constant) | |
4846 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4847 | ++imm_expr.X_add_number; |
252b5132 RH |
4848 | /* FALLTHROUGH */ |
4849 | case M_BLTU_I: | |
4850 | case M_BLTUL_I: | |
4851 | if (mask == M_BLTUL_I) | |
4852 | likely = 1; | |
4853 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4854 | goto do_false; | |
4855 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4856 | { | |
67c0d1eb | 4857 | macro_build (&offset_expr, likely ? "beql" : "beq", |
252b5132 | 4858 | "s,t,p", sreg, 0); |
8fc2e39e | 4859 | break; |
252b5132 | 4860 | } |
8fc2e39e | 4861 | used_at = 1; |
67c0d1eb RS |
4862 | set_at (sreg, 1); |
4863 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4864 | break; |
4865 | ||
4866 | case M_BLTL: | |
4867 | likely = 1; | |
4868 | case M_BLT: | |
4869 | if (treg == 0) | |
4870 | { | |
67c0d1eb | 4871 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
8fc2e39e | 4872 | break; |
252b5132 RH |
4873 | } |
4874 | if (sreg == 0) | |
4875 | { | |
67c0d1eb | 4876 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg); |
8fc2e39e | 4877 | break; |
252b5132 | 4878 | } |
8fc2e39e | 4879 | used_at = 1; |
67c0d1eb RS |
4880 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
4881 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4882 | break; |
4883 | ||
4884 | case M_BLTUL: | |
4885 | likely = 1; | |
4886 | case M_BLTU: | |
4887 | if (treg == 0) | |
4888 | goto do_false; | |
4889 | if (sreg == 0) | |
4890 | { | |
67c0d1eb | 4891 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4892 | "s,t,p", 0, treg); |
8fc2e39e | 4893 | break; |
252b5132 | 4894 | } |
8fc2e39e | 4895 | used_at = 1; |
67c0d1eb RS |
4896 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
4897 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4898 | break; |
4899 | ||
5f74bc13 CD |
4900 | case M_DEXT: |
4901 | { | |
4902 | unsigned long pos; | |
4903 | unsigned long size; | |
4904 | ||
4905 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
4906 | { | |
4907 | as_bad (_("Unsupported large constant")); | |
4908 | pos = size = 1; | |
4909 | } | |
4910 | else | |
4911 | { | |
4912 | pos = (unsigned long) imm_expr.X_add_number; | |
4913 | size = (unsigned long) imm2_expr.X_add_number; | |
4914 | } | |
4915 | ||
4916 | if (pos > 63) | |
4917 | { | |
4918 | as_bad (_("Improper position (%lu)"), pos); | |
4919 | pos = 1; | |
4920 | } | |
4921 | if (size == 0 || size > 64 | |
4922 | || (pos + size - 1) > 63) | |
4923 | { | |
4924 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
4925 | size, pos); | |
4926 | size = 1; | |
4927 | } | |
4928 | ||
4929 | if (size <= 32 && pos < 32) | |
4930 | { | |
4931 | s = "dext"; | |
4932 | fmt = "t,r,+A,+C"; | |
4933 | } | |
4934 | else if (size <= 32) | |
4935 | { | |
4936 | s = "dextu"; | |
4937 | fmt = "t,r,+E,+H"; | |
4938 | } | |
4939 | else | |
4940 | { | |
4941 | s = "dextm"; | |
4942 | fmt = "t,r,+A,+G"; | |
4943 | } | |
67c0d1eb | 4944 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, size - 1); |
5f74bc13 | 4945 | } |
8fc2e39e | 4946 | break; |
5f74bc13 CD |
4947 | |
4948 | case M_DINS: | |
4949 | { | |
4950 | unsigned long pos; | |
4951 | unsigned long size; | |
4952 | ||
4953 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
4954 | { | |
4955 | as_bad (_("Unsupported large constant")); | |
4956 | pos = size = 1; | |
4957 | } | |
4958 | else | |
4959 | { | |
4960 | pos = (unsigned long) imm_expr.X_add_number; | |
4961 | size = (unsigned long) imm2_expr.X_add_number; | |
4962 | } | |
4963 | ||
4964 | if (pos > 63) | |
4965 | { | |
4966 | as_bad (_("Improper position (%lu)"), pos); | |
4967 | pos = 1; | |
4968 | } | |
4969 | if (size == 0 || size > 64 | |
4970 | || (pos + size - 1) > 63) | |
4971 | { | |
4972 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
4973 | size, pos); | |
4974 | size = 1; | |
4975 | } | |
4976 | ||
4977 | if (pos < 32 && (pos + size - 1) < 32) | |
4978 | { | |
4979 | s = "dins"; | |
4980 | fmt = "t,r,+A,+B"; | |
4981 | } | |
4982 | else if (pos >= 32) | |
4983 | { | |
4984 | s = "dinsu"; | |
4985 | fmt = "t,r,+E,+F"; | |
4986 | } | |
4987 | else | |
4988 | { | |
4989 | s = "dinsm"; | |
4990 | fmt = "t,r,+A,+F"; | |
4991 | } | |
67c0d1eb RS |
4992 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, |
4993 | pos + size - 1); | |
5f74bc13 | 4994 | } |
8fc2e39e | 4995 | break; |
5f74bc13 | 4996 | |
252b5132 RH |
4997 | case M_DDIV_3: |
4998 | dbl = 1; | |
4999 | case M_DIV_3: | |
5000 | s = "mflo"; | |
5001 | goto do_div3; | |
5002 | case M_DREM_3: | |
5003 | dbl = 1; | |
5004 | case M_REM_3: | |
5005 | s = "mfhi"; | |
5006 | do_div3: | |
5007 | if (treg == 0) | |
5008 | { | |
5009 | as_warn (_("Divide by zero.")); | |
5010 | if (mips_trap) | |
67c0d1eb | 5011 | macro_build (NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 5012 | else |
67c0d1eb | 5013 | macro_build (NULL, "break", "c", 7); |
8fc2e39e | 5014 | break; |
252b5132 RH |
5015 | } |
5016 | ||
7d10b47d | 5017 | start_noreorder (); |
252b5132 RH |
5018 | if (mips_trap) |
5019 | { | |
67c0d1eb RS |
5020 | macro_build (NULL, "teq", "s,t,q", treg, 0, 7); |
5021 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); | |
252b5132 RH |
5022 | } |
5023 | else | |
5024 | { | |
5025 | expr1.X_add_number = 8; | |
67c0d1eb RS |
5026 | macro_build (&expr1, "bne", "s,t,p", treg, 0); |
5027 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); | |
5028 | macro_build (NULL, "break", "c", 7); | |
252b5132 RH |
5029 | } |
5030 | expr1.X_add_number = -1; | |
8fc2e39e | 5031 | used_at = 1; |
f6a22291 | 5032 | load_register (AT, &expr1, dbl); |
252b5132 | 5033 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
67c0d1eb | 5034 | macro_build (&expr1, "bne", "s,t,p", treg, AT); |
252b5132 RH |
5035 | if (dbl) |
5036 | { | |
5037 | expr1.X_add_number = 1; | |
f6a22291 | 5038 | load_register (AT, &expr1, dbl); |
67c0d1eb | 5039 | macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31); |
252b5132 RH |
5040 | } |
5041 | else | |
5042 | { | |
5043 | expr1.X_add_number = 0x80000000; | |
67c0d1eb | 5044 | macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16); |
252b5132 RH |
5045 | } |
5046 | if (mips_trap) | |
5047 | { | |
67c0d1eb | 5048 | macro_build (NULL, "teq", "s,t,q", sreg, AT, 6); |
252b5132 RH |
5049 | /* We want to close the noreorder block as soon as possible, so |
5050 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5051 | end_noreorder (); |
252b5132 RH |
5052 | } |
5053 | else | |
5054 | { | |
5055 | expr1.X_add_number = 8; | |
67c0d1eb RS |
5056 | macro_build (&expr1, "bne", "s,t,p", sreg, AT); |
5057 | macro_build (NULL, "nop", "", 0); | |
252b5132 RH |
5058 | |
5059 | /* We want to close the noreorder block as soon as possible, so | |
5060 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5061 | end_noreorder (); |
252b5132 | 5062 | |
67c0d1eb | 5063 | macro_build (NULL, "break", "c", 6); |
252b5132 | 5064 | } |
67c0d1eb | 5065 | macro_build (NULL, s, "d", dreg); |
252b5132 RH |
5066 | break; |
5067 | ||
5068 | case M_DIV_3I: | |
5069 | s = "div"; | |
5070 | s2 = "mflo"; | |
5071 | goto do_divi; | |
5072 | case M_DIVU_3I: | |
5073 | s = "divu"; | |
5074 | s2 = "mflo"; | |
5075 | goto do_divi; | |
5076 | case M_REM_3I: | |
5077 | s = "div"; | |
5078 | s2 = "mfhi"; | |
5079 | goto do_divi; | |
5080 | case M_REMU_3I: | |
5081 | s = "divu"; | |
5082 | s2 = "mfhi"; | |
5083 | goto do_divi; | |
5084 | case M_DDIV_3I: | |
5085 | dbl = 1; | |
5086 | s = "ddiv"; | |
5087 | s2 = "mflo"; | |
5088 | goto do_divi; | |
5089 | case M_DDIVU_3I: | |
5090 | dbl = 1; | |
5091 | s = "ddivu"; | |
5092 | s2 = "mflo"; | |
5093 | goto do_divi; | |
5094 | case M_DREM_3I: | |
5095 | dbl = 1; | |
5096 | s = "ddiv"; | |
5097 | s2 = "mfhi"; | |
5098 | goto do_divi; | |
5099 | case M_DREMU_3I: | |
5100 | dbl = 1; | |
5101 | s = "ddivu"; | |
5102 | s2 = "mfhi"; | |
5103 | do_divi: | |
5104 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5105 | { | |
5106 | as_warn (_("Divide by zero.")); | |
5107 | if (mips_trap) | |
67c0d1eb | 5108 | macro_build (NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 5109 | else |
67c0d1eb | 5110 | macro_build (NULL, "break", "c", 7); |
8fc2e39e | 5111 | break; |
252b5132 RH |
5112 | } |
5113 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
5114 | { | |
5115 | if (strcmp (s2, "mflo") == 0) | |
67c0d1eb | 5116 | move_register (dreg, sreg); |
252b5132 | 5117 | else |
67c0d1eb | 5118 | move_register (dreg, 0); |
8fc2e39e | 5119 | break; |
252b5132 RH |
5120 | } |
5121 | if (imm_expr.X_op == O_constant | |
5122 | && imm_expr.X_add_number == -1 | |
5123 | && s[strlen (s) - 1] != 'u') | |
5124 | { | |
5125 | if (strcmp (s2, "mflo") == 0) | |
5126 | { | |
67c0d1eb | 5127 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg); |
252b5132 RH |
5128 | } |
5129 | else | |
67c0d1eb | 5130 | move_register (dreg, 0); |
8fc2e39e | 5131 | break; |
252b5132 RH |
5132 | } |
5133 | ||
8fc2e39e | 5134 | used_at = 1; |
67c0d1eb RS |
5135 | load_register (AT, &imm_expr, dbl); |
5136 | macro_build (NULL, s, "z,s,t", sreg, AT); | |
5137 | macro_build (NULL, s2, "d", dreg); | |
252b5132 RH |
5138 | break; |
5139 | ||
5140 | case M_DIVU_3: | |
5141 | s = "divu"; | |
5142 | s2 = "mflo"; | |
5143 | goto do_divu3; | |
5144 | case M_REMU_3: | |
5145 | s = "divu"; | |
5146 | s2 = "mfhi"; | |
5147 | goto do_divu3; | |
5148 | case M_DDIVU_3: | |
5149 | s = "ddivu"; | |
5150 | s2 = "mflo"; | |
5151 | goto do_divu3; | |
5152 | case M_DREMU_3: | |
5153 | s = "ddivu"; | |
5154 | s2 = "mfhi"; | |
5155 | do_divu3: | |
7d10b47d | 5156 | start_noreorder (); |
252b5132 RH |
5157 | if (mips_trap) |
5158 | { | |
67c0d1eb RS |
5159 | macro_build (NULL, "teq", "s,t,q", treg, 0, 7); |
5160 | macro_build (NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
5161 | /* We want to close the noreorder block as soon as possible, so |
5162 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5163 | end_noreorder (); |
252b5132 RH |
5164 | } |
5165 | else | |
5166 | { | |
5167 | expr1.X_add_number = 8; | |
67c0d1eb RS |
5168 | macro_build (&expr1, "bne", "s,t,p", treg, 0); |
5169 | macro_build (NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
5170 | |
5171 | /* We want to close the noreorder block as soon as possible, so | |
5172 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5173 | end_noreorder (); |
67c0d1eb | 5174 | macro_build (NULL, "break", "c", 7); |
252b5132 | 5175 | } |
67c0d1eb | 5176 | macro_build (NULL, s2, "d", dreg); |
8fc2e39e | 5177 | break; |
252b5132 | 5178 | |
1abe91b1 MR |
5179 | case M_DLCA_AB: |
5180 | dbl = 1; | |
5181 | case M_LCA_AB: | |
5182 | call = 1; | |
5183 | goto do_la; | |
252b5132 RH |
5184 | case M_DLA_AB: |
5185 | dbl = 1; | |
5186 | case M_LA_AB: | |
1abe91b1 | 5187 | do_la: |
252b5132 RH |
5188 | /* Load the address of a symbol into a register. If breg is not |
5189 | zero, we then add a base register to it. */ | |
5190 | ||
3bec30a8 TS |
5191 | if (dbl && HAVE_32BIT_GPRS) |
5192 | as_warn (_("dla used to load 32-bit register")); | |
5193 | ||
c90bbe5b | 5194 | if (! dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
5195 | as_warn (_("la used to load 64-bit address")); |
5196 | ||
0c11417f MR |
5197 | if (offset_expr.X_op == O_constant |
5198 | && offset_expr.X_add_number >= -0x8000 | |
5199 | && offset_expr.X_add_number < 0x8000) | |
5200 | { | |
aed1a261 | 5201 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
17a2f251 | 5202 | "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 5203 | break; |
0c11417f MR |
5204 | } |
5205 | ||
b8285c27 | 5206 | if (!mips_opts.noat && (treg == breg)) |
afdbd6d0 CD |
5207 | { |
5208 | tempreg = AT; | |
5209 | used_at = 1; | |
5210 | } | |
5211 | else | |
5212 | { | |
5213 | tempreg = treg; | |
afdbd6d0 CD |
5214 | } |
5215 | ||
252b5132 RH |
5216 | if (offset_expr.X_op != O_symbol |
5217 | && offset_expr.X_op != O_constant) | |
5218 | { | |
5219 | as_bad (_("expression too complex")); | |
5220 | offset_expr.X_op = O_constant; | |
5221 | } | |
5222 | ||
252b5132 | 5223 | if (offset_expr.X_op == O_constant) |
aed1a261 | 5224 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
5225 | else if (mips_pic == NO_PIC) |
5226 | { | |
d6bc6245 | 5227 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 5228 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
5229 | Otherwise we want |
5230 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5231 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5232 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 5233 | so we may as well always use the latter form. |
76b3015f | 5234 | |
6caf9ef4 TS |
5235 | With 64bit address space and a usable $at we want |
5236 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5237 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5238 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5239 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
5240 | dsll32 $tempreg,0 | |
5241 | daddu $tempreg,$tempreg,$at | |
5242 | ||
5243 | If $at is already in use, we use a path which is suboptimal | |
5244 | on superscalar processors. | |
5245 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5246 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5247 | dsll $tempreg,16 | |
5248 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5249 | dsll $tempreg,16 | |
5250 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
5251 | ||
5252 | For GP relative symbols in 64bit address space we can use | |
5253 | the same sequence as in 32bit address space. */ | |
aed1a261 | 5254 | if (HAVE_64BIT_SYMBOLS) |
252b5132 | 5255 | { |
6caf9ef4 TS |
5256 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
5257 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
5258 | { | |
5259 | relax_start (offset_expr.X_add_symbol); | |
5260 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5261 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
5262 | relax_switch (); | |
5263 | } | |
d6bc6245 | 5264 | |
b8285c27 | 5265 | if (used_at == 0 && !mips_opts.noat) |
98d3f06f | 5266 | { |
67c0d1eb | 5267 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 5268 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 5269 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 5270 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 5271 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5272 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 5273 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5274 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb RS |
5275 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); |
5276 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
98d3f06f KH |
5277 | used_at = 1; |
5278 | } | |
5279 | else | |
5280 | { | |
67c0d1eb | 5281 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 5282 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 5283 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5284 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb RS |
5285 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
5286 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 5287 | tempreg, tempreg, BFD_RELOC_HI16_S); |
67c0d1eb RS |
5288 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
5289 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 5290 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 5291 | } |
6caf9ef4 TS |
5292 | |
5293 | if (mips_relax.sequence) | |
5294 | relax_end (); | |
98d3f06f KH |
5295 | } |
5296 | else | |
5297 | { | |
5298 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 5299 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
98d3f06f | 5300 | { |
4d7206a2 | 5301 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5302 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5303 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 5304 | relax_switch (); |
98d3f06f | 5305 | } |
6943caf0 ILT |
5306 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
5307 | as_bad (_("offset too large")); | |
67c0d1eb RS |
5308 | macro_build_lui (&offset_expr, tempreg); |
5309 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5310 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
5311 | if (mips_relax.sequence) |
5312 | relax_end (); | |
98d3f06f | 5313 | } |
252b5132 | 5314 | } |
0a44bf69 | 5315 | else if (!mips_big_got && !HAVE_NEWABI) |
252b5132 | 5316 | { |
9117d219 NC |
5317 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
5318 | ||
252b5132 RH |
5319 | /* If this is a reference to an external symbol, and there |
5320 | is no constant, we want | |
5321 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 5322 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 5323 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
5324 | For a local symbol, we want |
5325 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5326 | nop | |
5327 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5328 | ||
5329 | If we have a small constant, and this is a reference to | |
5330 | an external symbol, we want | |
5331 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5332 | nop | |
5333 | addiu $tempreg,$tempreg,<constant> | |
5334 | For a local symbol, we want the same instruction | |
5335 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
5336 | addiu instruction. | |
5337 | ||
5338 | If we have a large constant, and this is a reference to | |
5339 | an external symbol, we want | |
5340 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5341 | lui $at,<hiconstant> | |
5342 | addiu $at,$at,<loconstant> | |
5343 | addu $tempreg,$tempreg,$at | |
5344 | For a local symbol, we want the same instruction | |
5345 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 5346 | addiu instruction. |
ed6fb7bd SC |
5347 | */ |
5348 | ||
4d7206a2 | 5349 | if (offset_expr.X_add_number == 0) |
252b5132 | 5350 | { |
0a44bf69 RS |
5351 | if (mips_pic == SVR4_PIC |
5352 | && breg == 0 | |
5353 | && (call || tempreg == PIC_CALL_REG)) | |
4d7206a2 RS |
5354 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; |
5355 | ||
5356 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
5357 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5358 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 5359 | if (breg != 0) |
252b5132 RH |
5360 | { |
5361 | /* We're going to put in an addu instruction using | |
5362 | tempreg, so we may as well insert the nop right | |
5363 | now. */ | |
269137b2 | 5364 | load_delay_nop (); |
252b5132 | 5365 | } |
4d7206a2 | 5366 | relax_switch (); |
67c0d1eb RS |
5367 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5368 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 5369 | load_delay_nop (); |
67c0d1eb RS |
5370 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5371 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 5372 | relax_end (); |
252b5132 RH |
5373 | /* FIXME: If breg == 0, and the next instruction uses |
5374 | $tempreg, then if this variant case is used an extra | |
5375 | nop will be generated. */ | |
5376 | } | |
4d7206a2 RS |
5377 | else if (offset_expr.X_add_number >= -0x8000 |
5378 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 5379 | { |
67c0d1eb | 5380 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 5381 | load_delay_nop (); |
67c0d1eb | 5382 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
5383 | } |
5384 | else | |
5385 | { | |
4d7206a2 RS |
5386 | expr1.X_add_number = offset_expr.X_add_number; |
5387 | offset_expr.X_add_number = | |
5388 | ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
67c0d1eb | 5389 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 5390 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
5391 | /* If we are going to add in a base register, and the |
5392 | target register and the base register are the same, | |
5393 | then we are using AT as a temporary register. Since | |
5394 | we want to load the constant into AT, we add our | |
5395 | current AT (from the global offset table) and the | |
5396 | register into the register now, and pretend we were | |
5397 | not using a base register. */ | |
67c0d1eb | 5398 | if (breg == treg) |
252b5132 | 5399 | { |
269137b2 | 5400 | load_delay_nop (); |
67c0d1eb | 5401 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5402 | treg, AT, breg); |
252b5132 RH |
5403 | breg = 0; |
5404 | tempreg = treg; | |
252b5132 | 5405 | } |
f6a22291 | 5406 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
5407 | used_at = 1; |
5408 | } | |
5409 | } | |
0a44bf69 | 5410 | else if (!mips_big_got && HAVE_NEWABI) |
f5040a92 | 5411 | { |
67c0d1eb | 5412 | int add_breg_early = 0; |
f5040a92 AO |
5413 | |
5414 | /* If this is a reference to an external, and there is no | |
5415 | constant, or local symbol (*), with or without a | |
5416 | constant, we want | |
5417 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 5418 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5419 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
5420 | ||
5421 | If we have a small constant, and this is a reference to | |
5422 | an external symbol, we want | |
5423 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5424 | addiu $tempreg,$tempreg,<constant> | |
5425 | ||
5426 | If we have a large constant, and this is a reference to | |
5427 | an external symbol, we want | |
5428 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5429 | lui $at,<hiconstant> | |
5430 | addiu $at,$at,<loconstant> | |
5431 | addu $tempreg,$tempreg,$at | |
5432 | ||
5433 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
5434 | local symbols, even though it introduces an additional | |
5435 | instruction. */ | |
5436 | ||
f5040a92 AO |
5437 | if (offset_expr.X_add_number) |
5438 | { | |
4d7206a2 | 5439 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5440 | offset_expr.X_add_number = 0; |
5441 | ||
4d7206a2 | 5442 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5443 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5444 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5445 | |
5446 | if (expr1.X_add_number >= -0x8000 | |
5447 | && expr1.X_add_number < 0x8000) | |
5448 | { | |
67c0d1eb RS |
5449 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
5450 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 5451 | } |
ecd13cd3 | 5452 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 AO |
5453 | { |
5454 | int dreg; | |
5455 | ||
5456 | /* If we are going to add in a base register, and the | |
5457 | target register and the base register are the same, | |
5458 | then we are using AT as a temporary register. Since | |
5459 | we want to load the constant into AT, we add our | |
5460 | current AT (from the global offset table) and the | |
5461 | register into the register now, and pretend we were | |
5462 | not using a base register. */ | |
5463 | if (breg != treg) | |
5464 | dreg = tempreg; | |
5465 | else | |
5466 | { | |
5467 | assert (tempreg == AT); | |
67c0d1eb RS |
5468 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
5469 | treg, AT, breg); | |
f5040a92 | 5470 | dreg = treg; |
67c0d1eb | 5471 | add_breg_early = 1; |
f5040a92 AO |
5472 | } |
5473 | ||
f6a22291 | 5474 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5475 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5476 | dreg, dreg, AT); |
f5040a92 | 5477 | |
f5040a92 AO |
5478 | used_at = 1; |
5479 | } | |
5480 | else | |
5481 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5482 | ||
4d7206a2 | 5483 | relax_switch (); |
f5040a92 AO |
5484 | offset_expr.X_add_number = expr1.X_add_number; |
5485 | ||
67c0d1eb RS |
5486 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5487 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
5488 | if (add_breg_early) | |
f5040a92 | 5489 | { |
67c0d1eb | 5490 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
f899b4b8 | 5491 | treg, tempreg, breg); |
f5040a92 AO |
5492 | breg = 0; |
5493 | tempreg = treg; | |
5494 | } | |
4d7206a2 | 5495 | relax_end (); |
f5040a92 | 5496 | } |
4d7206a2 | 5497 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 5498 | { |
4d7206a2 | 5499 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5500 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5501 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 5502 | relax_switch (); |
67c0d1eb RS |
5503 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5504 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 5505 | relax_end (); |
f5040a92 | 5506 | } |
4d7206a2 | 5507 | else |
f5040a92 | 5508 | { |
67c0d1eb RS |
5509 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5510 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5511 | } |
5512 | } | |
0a44bf69 | 5513 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 5514 | { |
67c0d1eb | 5515 | int gpdelay; |
9117d219 NC |
5516 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5517 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 5518 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
5519 | |
5520 | /* This is the large GOT case. If this is a reference to an | |
5521 | external symbol, and there is no constant, we want | |
5522 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5523 | addu $tempreg,$tempreg,$gp | |
5524 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5525 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
5526 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5527 | addu $tempreg,$tempreg,$gp | |
5528 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
5529 | For a local symbol, we want |
5530 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5531 | nop | |
5532 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5533 | ||
5534 | If we have a small constant, and this is a reference to | |
5535 | an external symbol, we want | |
5536 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5537 | addu $tempreg,$tempreg,$gp | |
5538 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5539 | nop | |
5540 | addiu $tempreg,$tempreg,<constant> | |
5541 | For a local symbol, we want | |
5542 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5543 | nop | |
5544 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
5545 | ||
5546 | If we have a large constant, and this is a reference to | |
5547 | an external symbol, we want | |
5548 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5549 | addu $tempreg,$tempreg,$gp | |
5550 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5551 | lui $at,<hiconstant> | |
5552 | addiu $at,$at,<loconstant> | |
5553 | addu $tempreg,$tempreg,$at | |
5554 | For a local symbol, we want | |
5555 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5556 | lui $at,<hiconstant> | |
5557 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
5558 | addu $tempreg,$tempreg,$at | |
f5040a92 | 5559 | */ |
438c16b8 | 5560 | |
252b5132 RH |
5561 | expr1.X_add_number = offset_expr.X_add_number; |
5562 | offset_expr.X_add_number = 0; | |
4d7206a2 | 5563 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 5564 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
5565 | if (expr1.X_add_number == 0 && breg == 0 |
5566 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
5567 | { |
5568 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5569 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5570 | } | |
67c0d1eb RS |
5571 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
5572 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5573 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 5574 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 5575 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
5576 | if (expr1.X_add_number == 0) |
5577 | { | |
67c0d1eb | 5578 | if (breg != 0) |
252b5132 RH |
5579 | { |
5580 | /* We're going to put in an addu instruction using | |
5581 | tempreg, so we may as well insert the nop right | |
5582 | now. */ | |
269137b2 | 5583 | load_delay_nop (); |
252b5132 | 5584 | } |
252b5132 RH |
5585 | } |
5586 | else if (expr1.X_add_number >= -0x8000 | |
5587 | && expr1.X_add_number < 0x8000) | |
5588 | { | |
269137b2 | 5589 | load_delay_nop (); |
67c0d1eb | 5590 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5591 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
5592 | } |
5593 | else | |
5594 | { | |
67c0d1eb | 5595 | int dreg; |
252b5132 RH |
5596 | |
5597 | /* If we are going to add in a base register, and the | |
5598 | target register and the base register are the same, | |
5599 | then we are using AT as a temporary register. Since | |
5600 | we want to load the constant into AT, we add our | |
5601 | current AT (from the global offset table) and the | |
5602 | register into the register now, and pretend we were | |
5603 | not using a base register. */ | |
5604 | if (breg != treg) | |
67c0d1eb | 5605 | dreg = tempreg; |
252b5132 RH |
5606 | else |
5607 | { | |
5608 | assert (tempreg == AT); | |
269137b2 | 5609 | load_delay_nop (); |
67c0d1eb | 5610 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5611 | treg, AT, breg); |
252b5132 | 5612 | dreg = treg; |
252b5132 RH |
5613 | } |
5614 | ||
f6a22291 | 5615 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5616 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 5617 | |
252b5132 RH |
5618 | used_at = 1; |
5619 | } | |
4d7206a2 RS |
5620 | offset_expr.X_add_number = |
5621 | ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
5622 | relax_switch (); | |
252b5132 | 5623 | |
67c0d1eb | 5624 | if (gpdelay) |
252b5132 RH |
5625 | { |
5626 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 5627 | the first instruction on the main stream does not. */ |
67c0d1eb | 5628 | macro_build (NULL, "nop", ""); |
252b5132 | 5629 | } |
ed6fb7bd | 5630 | |
67c0d1eb RS |
5631 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5632 | local_reloc_type, mips_gp_register); | |
f5040a92 | 5633 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
5634 | && expr1.X_add_number < 0x8000) |
5635 | { | |
269137b2 | 5636 | load_delay_nop (); |
67c0d1eb RS |
5637 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5638 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 5639 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
5640 | register, the external symbol case ended with a load, |
5641 | so if the symbol turns out to not be external, and | |
5642 | the next instruction uses tempreg, an unnecessary nop | |
5643 | will be inserted. */ | |
252b5132 RH |
5644 | } |
5645 | else | |
5646 | { | |
5647 | if (breg == treg) | |
5648 | { | |
5649 | /* We must add in the base register now, as in the | |
f5040a92 | 5650 | external symbol case. */ |
252b5132 | 5651 | assert (tempreg == AT); |
269137b2 | 5652 | load_delay_nop (); |
67c0d1eb | 5653 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5654 | treg, AT, breg); |
252b5132 RH |
5655 | tempreg = treg; |
5656 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 5657 | it in in both cases. */ |
252b5132 RH |
5658 | breg = 0; |
5659 | } | |
5660 | ||
67c0d1eb RS |
5661 | macro_build_lui (&expr1, AT); |
5662 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 5663 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 5664 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5665 | tempreg, tempreg, AT); |
8fc2e39e | 5666 | used_at = 1; |
252b5132 | 5667 | } |
4d7206a2 | 5668 | relax_end (); |
252b5132 | 5669 | } |
0a44bf69 | 5670 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 5671 | { |
f5040a92 AO |
5672 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5673 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 5674 | int add_breg_early = 0; |
f5040a92 AO |
5675 | |
5676 | /* This is the large GOT case. If this is a reference to an | |
5677 | external symbol, and there is no constant, we want | |
5678 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5679 | add $tempreg,$tempreg,$gp | |
5680 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5681 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5682 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5683 | add $tempreg,$tempreg,$gp | |
5684 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
5685 | ||
5686 | If we have a small constant, and this is a reference to | |
5687 | an external symbol, we want | |
5688 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5689 | add $tempreg,$tempreg,$gp | |
5690 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5691 | addi $tempreg,$tempreg,<constant> | |
5692 | ||
5693 | If we have a large constant, and this is a reference to | |
5694 | an external symbol, we want | |
5695 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5696 | addu $tempreg,$tempreg,$gp | |
5697 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5698 | lui $at,<hiconstant> | |
5699 | addi $at,$at,<loconstant> | |
5700 | add $tempreg,$tempreg,$at | |
5701 | ||
5702 | If we have NewABI, and we know it's a local symbol, we want | |
5703 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
5704 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
5705 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
5706 | ||
4d7206a2 | 5707 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 5708 | |
4d7206a2 | 5709 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5710 | offset_expr.X_add_number = 0; |
5711 | ||
1abe91b1 MR |
5712 | if (expr1.X_add_number == 0 && breg == 0 |
5713 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
5714 | { |
5715 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5716 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5717 | } | |
67c0d1eb RS |
5718 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
5719 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5720 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
5721 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5722 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
5723 | |
5724 | if (expr1.X_add_number == 0) | |
4d7206a2 | 5725 | ; |
f5040a92 AO |
5726 | else if (expr1.X_add_number >= -0x8000 |
5727 | && expr1.X_add_number < 0x8000) | |
5728 | { | |
67c0d1eb | 5729 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5730 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 5731 | } |
ecd13cd3 | 5732 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 AO |
5733 | { |
5734 | int dreg; | |
5735 | ||
5736 | /* If we are going to add in a base register, and the | |
5737 | target register and the base register are the same, | |
5738 | then we are using AT as a temporary register. Since | |
5739 | we want to load the constant into AT, we add our | |
5740 | current AT (from the global offset table) and the | |
5741 | register into the register now, and pretend we were | |
5742 | not using a base register. */ | |
5743 | if (breg != treg) | |
5744 | dreg = tempreg; | |
5745 | else | |
5746 | { | |
5747 | assert (tempreg == AT); | |
67c0d1eb | 5748 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5749 | treg, AT, breg); |
f5040a92 | 5750 | dreg = treg; |
67c0d1eb | 5751 | add_breg_early = 1; |
f5040a92 AO |
5752 | } |
5753 | ||
f6a22291 | 5754 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5755 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 5756 | |
f5040a92 AO |
5757 | used_at = 1; |
5758 | } | |
5759 | else | |
5760 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5761 | ||
4d7206a2 | 5762 | relax_switch (); |
f5040a92 | 5763 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
5764 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5765 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
5766 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
5767 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
5768 | if (add_breg_early) | |
f5040a92 | 5769 | { |
67c0d1eb | 5770 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5771 | treg, tempreg, breg); |
f5040a92 AO |
5772 | breg = 0; |
5773 | tempreg = treg; | |
5774 | } | |
4d7206a2 | 5775 | relax_end (); |
f5040a92 | 5776 | } |
252b5132 RH |
5777 | else |
5778 | abort (); | |
5779 | ||
5780 | if (breg != 0) | |
aed1a261 | 5781 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg); |
252b5132 RH |
5782 | break; |
5783 | ||
5784 | case M_J_A: | |
5785 | /* The j instruction may not be used in PIC code, since it | |
5786 | requires an absolute address. We convert it to a b | |
5787 | instruction. */ | |
5788 | if (mips_pic == NO_PIC) | |
67c0d1eb | 5789 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 5790 | else |
67c0d1eb | 5791 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 5792 | break; |
252b5132 RH |
5793 | |
5794 | /* The jal instructions must be handled as macros because when | |
5795 | generating PIC code they expand to multi-instruction | |
5796 | sequences. Normally they are simple instructions. */ | |
5797 | case M_JAL_1: | |
5798 | dreg = RA; | |
5799 | /* Fall through. */ | |
5800 | case M_JAL_2: | |
3e722fb5 | 5801 | if (mips_pic == NO_PIC) |
67c0d1eb | 5802 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
0a44bf69 | 5803 | else |
252b5132 RH |
5804 | { |
5805 | if (sreg != PIC_CALL_REG) | |
5806 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 5807 | |
67c0d1eb | 5808 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
0a44bf69 | 5809 | if (mips_pic == SVR4_PIC && !HAVE_NEWABI) |
252b5132 | 5810 | { |
6478892d TS |
5811 | if (mips_cprestore_offset < 0) |
5812 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5813 | else | |
5814 | { | |
7a621144 DJ |
5815 | if (! mips_frame_reg_valid) |
5816 | { | |
5817 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5818 | /* Quiet this warning. */ | |
5819 | mips_frame_reg_valid = 1; | |
5820 | } | |
5821 | if (! mips_cprestore_valid) | |
5822 | { | |
5823 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5824 | /* Quiet this warning. */ | |
5825 | mips_cprestore_valid = 1; | |
5826 | } | |
6478892d | 5827 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 5828 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 5829 | mips_gp_register, |
256ab948 TS |
5830 | mips_frame_reg, |
5831 | HAVE_64BIT_ADDRESSES); | |
6478892d | 5832 | } |
252b5132 RH |
5833 | } |
5834 | } | |
252b5132 | 5835 | |
8fc2e39e | 5836 | break; |
252b5132 RH |
5837 | |
5838 | case M_JAL_A: | |
5839 | if (mips_pic == NO_PIC) | |
67c0d1eb | 5840 | macro_build (&offset_expr, "jal", "a"); |
252b5132 RH |
5841 | else if (mips_pic == SVR4_PIC) |
5842 | { | |
5843 | /* If this is a reference to an external symbol, and we are | |
5844 | using a small GOT, we want | |
5845 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
5846 | nop | |
f9419b05 | 5847 | jalr $ra,$25 |
252b5132 RH |
5848 | nop |
5849 | lw $gp,cprestore($sp) | |
5850 | The cprestore value is set using the .cprestore | |
5851 | pseudo-op. If we are using a big GOT, we want | |
5852 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
5853 | addu $25,$25,$gp | |
5854 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
5855 | nop | |
f9419b05 | 5856 | jalr $ra,$25 |
252b5132 RH |
5857 | nop |
5858 | lw $gp,cprestore($sp) | |
5859 | If the symbol is not external, we want | |
5860 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5861 | nop | |
5862 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 5863 | jalr $ra,$25 |
252b5132 | 5864 | nop |
438c16b8 | 5865 | lw $gp,cprestore($sp) |
f5040a92 AO |
5866 | |
5867 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
5868 | sequences above, minus nops, unless the symbol is local, | |
5869 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
5870 | GOT_DISP. */ | |
438c16b8 | 5871 | if (HAVE_NEWABI) |
252b5132 | 5872 | { |
f5040a92 AO |
5873 | if (! mips_big_got) |
5874 | { | |
4d7206a2 | 5875 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5876 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5877 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 5878 | mips_gp_register); |
4d7206a2 | 5879 | relax_switch (); |
67c0d1eb RS |
5880 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5881 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
5882 | mips_gp_register); |
5883 | relax_end (); | |
f5040a92 AO |
5884 | } |
5885 | else | |
5886 | { | |
4d7206a2 | 5887 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5888 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, |
5889 | BFD_RELOC_MIPS_CALL_HI16); | |
5890 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
5891 | PIC_CALL_REG, mips_gp_register); | |
5892 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
5893 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
5894 | PIC_CALL_REG); | |
4d7206a2 | 5895 | relax_switch (); |
67c0d1eb RS |
5896 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5897 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
5898 | mips_gp_register); | |
5899 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5900 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 5901 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 5902 | relax_end (); |
f5040a92 | 5903 | } |
684022ea | 5904 | |
67c0d1eb | 5905 | macro_build_jalr (&offset_expr); |
252b5132 RH |
5906 | } |
5907 | else | |
5908 | { | |
4d7206a2 | 5909 | relax_start (offset_expr.X_add_symbol); |
438c16b8 TS |
5910 | if (! mips_big_got) |
5911 | { | |
67c0d1eb RS |
5912 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5913 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 5914 | mips_gp_register); |
269137b2 | 5915 | load_delay_nop (); |
4d7206a2 | 5916 | relax_switch (); |
438c16b8 | 5917 | } |
252b5132 | 5918 | else |
252b5132 | 5919 | { |
67c0d1eb RS |
5920 | int gpdelay; |
5921 | ||
5922 | gpdelay = reg_needs_delay (mips_gp_register); | |
5923 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, | |
5924 | BFD_RELOC_MIPS_CALL_HI16); | |
5925 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
5926 | PIC_CALL_REG, mips_gp_register); | |
5927 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
5928 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
5929 | PIC_CALL_REG); | |
269137b2 | 5930 | load_delay_nop (); |
4d7206a2 | 5931 | relax_switch (); |
67c0d1eb RS |
5932 | if (gpdelay) |
5933 | macro_build (NULL, "nop", ""); | |
252b5132 | 5934 | } |
67c0d1eb RS |
5935 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5936 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 5937 | mips_gp_register); |
269137b2 | 5938 | load_delay_nop (); |
67c0d1eb RS |
5939 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5940 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 5941 | relax_end (); |
67c0d1eb | 5942 | macro_build_jalr (&offset_expr); |
438c16b8 | 5943 | |
6478892d TS |
5944 | if (mips_cprestore_offset < 0) |
5945 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5946 | else | |
5947 | { | |
7a621144 DJ |
5948 | if (! mips_frame_reg_valid) |
5949 | { | |
5950 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5951 | /* Quiet this warning. */ | |
5952 | mips_frame_reg_valid = 1; | |
5953 | } | |
5954 | if (! mips_cprestore_valid) | |
5955 | { | |
5956 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5957 | /* Quiet this warning. */ | |
5958 | mips_cprestore_valid = 1; | |
5959 | } | |
6478892d | 5960 | if (mips_opts.noreorder) |
67c0d1eb | 5961 | macro_build (NULL, "nop", ""); |
6478892d | 5962 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 5963 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 5964 | mips_gp_register, |
256ab948 TS |
5965 | mips_frame_reg, |
5966 | HAVE_64BIT_ADDRESSES); | |
6478892d | 5967 | } |
252b5132 RH |
5968 | } |
5969 | } | |
0a44bf69 RS |
5970 | else if (mips_pic == VXWORKS_PIC) |
5971 | as_bad (_("Non-PIC jump used in PIC library")); | |
252b5132 RH |
5972 | else |
5973 | abort (); | |
5974 | ||
8fc2e39e | 5975 | break; |
252b5132 RH |
5976 | |
5977 | case M_LB_AB: | |
5978 | s = "lb"; | |
5979 | goto ld; | |
5980 | case M_LBU_AB: | |
5981 | s = "lbu"; | |
5982 | goto ld; | |
5983 | case M_LH_AB: | |
5984 | s = "lh"; | |
5985 | goto ld; | |
5986 | case M_LHU_AB: | |
5987 | s = "lhu"; | |
5988 | goto ld; | |
5989 | case M_LW_AB: | |
5990 | s = "lw"; | |
5991 | goto ld; | |
5992 | case M_LWC0_AB: | |
5993 | s = "lwc0"; | |
bdaaa2e1 | 5994 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5995 | coproc = 1; |
5996 | goto ld; | |
5997 | case M_LWC1_AB: | |
5998 | s = "lwc1"; | |
bdaaa2e1 | 5999 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6000 | coproc = 1; |
6001 | goto ld; | |
6002 | case M_LWC2_AB: | |
6003 | s = "lwc2"; | |
bdaaa2e1 | 6004 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6005 | coproc = 1; |
6006 | goto ld; | |
6007 | case M_LWC3_AB: | |
6008 | s = "lwc3"; | |
bdaaa2e1 | 6009 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6010 | coproc = 1; |
6011 | goto ld; | |
6012 | case M_LWL_AB: | |
6013 | s = "lwl"; | |
6014 | lr = 1; | |
6015 | goto ld; | |
6016 | case M_LWR_AB: | |
6017 | s = "lwr"; | |
6018 | lr = 1; | |
6019 | goto ld; | |
6020 | case M_LDC1_AB: | |
fef14a42 | 6021 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6022 | { |
6023 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6024 | break; |
252b5132 RH |
6025 | } |
6026 | s = "ldc1"; | |
bdaaa2e1 | 6027 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6028 | coproc = 1; |
6029 | goto ld; | |
6030 | case M_LDC2_AB: | |
6031 | s = "ldc2"; | |
bdaaa2e1 | 6032 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6033 | coproc = 1; |
6034 | goto ld; | |
6035 | case M_LDC3_AB: | |
6036 | s = "ldc3"; | |
bdaaa2e1 | 6037 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6038 | coproc = 1; |
6039 | goto ld; | |
6040 | case M_LDL_AB: | |
6041 | s = "ldl"; | |
6042 | lr = 1; | |
6043 | goto ld; | |
6044 | case M_LDR_AB: | |
6045 | s = "ldr"; | |
6046 | lr = 1; | |
6047 | goto ld; | |
6048 | case M_LL_AB: | |
6049 | s = "ll"; | |
6050 | goto ld; | |
6051 | case M_LLD_AB: | |
6052 | s = "lld"; | |
6053 | goto ld; | |
6054 | case M_LWU_AB: | |
6055 | s = "lwu"; | |
6056 | ld: | |
8fc2e39e | 6057 | if (breg == treg || coproc || lr) |
252b5132 RH |
6058 | { |
6059 | tempreg = AT; | |
6060 | used_at = 1; | |
6061 | } | |
6062 | else | |
6063 | { | |
6064 | tempreg = treg; | |
252b5132 RH |
6065 | } |
6066 | goto ld_st; | |
6067 | case M_SB_AB: | |
6068 | s = "sb"; | |
6069 | goto st; | |
6070 | case M_SH_AB: | |
6071 | s = "sh"; | |
6072 | goto st; | |
6073 | case M_SW_AB: | |
6074 | s = "sw"; | |
6075 | goto st; | |
6076 | case M_SWC0_AB: | |
6077 | s = "swc0"; | |
bdaaa2e1 | 6078 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6079 | coproc = 1; |
6080 | goto st; | |
6081 | case M_SWC1_AB: | |
6082 | s = "swc1"; | |
bdaaa2e1 | 6083 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6084 | coproc = 1; |
6085 | goto st; | |
6086 | case M_SWC2_AB: | |
6087 | s = "swc2"; | |
bdaaa2e1 | 6088 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6089 | coproc = 1; |
6090 | goto st; | |
6091 | case M_SWC3_AB: | |
6092 | s = "swc3"; | |
bdaaa2e1 | 6093 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6094 | coproc = 1; |
6095 | goto st; | |
6096 | case M_SWL_AB: | |
6097 | s = "swl"; | |
6098 | goto st; | |
6099 | case M_SWR_AB: | |
6100 | s = "swr"; | |
6101 | goto st; | |
6102 | case M_SC_AB: | |
6103 | s = "sc"; | |
6104 | goto st; | |
6105 | case M_SCD_AB: | |
6106 | s = "scd"; | |
6107 | goto st; | |
d43b4baf TS |
6108 | case M_CACHE_AB: |
6109 | s = "cache"; | |
6110 | goto st; | |
252b5132 | 6111 | case M_SDC1_AB: |
fef14a42 | 6112 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6113 | { |
6114 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6115 | break; |
252b5132 RH |
6116 | } |
6117 | s = "sdc1"; | |
6118 | coproc = 1; | |
bdaaa2e1 | 6119 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6120 | goto st; |
6121 | case M_SDC2_AB: | |
6122 | s = "sdc2"; | |
bdaaa2e1 | 6123 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6124 | coproc = 1; |
6125 | goto st; | |
6126 | case M_SDC3_AB: | |
6127 | s = "sdc3"; | |
bdaaa2e1 | 6128 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6129 | coproc = 1; |
6130 | goto st; | |
6131 | case M_SDL_AB: | |
6132 | s = "sdl"; | |
6133 | goto st; | |
6134 | case M_SDR_AB: | |
6135 | s = "sdr"; | |
6136 | st: | |
8fc2e39e TS |
6137 | tempreg = AT; |
6138 | used_at = 1; | |
252b5132 | 6139 | ld_st: |
bdaaa2e1 | 6140 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6141 | if (mask == M_LWC1_AB |
6142 | || mask == M_SWC1_AB | |
6143 | || mask == M_LDC1_AB | |
6144 | || mask == M_SDC1_AB | |
6145 | || mask == M_L_DAB | |
6146 | || mask == M_S_DAB) | |
6147 | fmt = "T,o(b)"; | |
d43b4baf TS |
6148 | else if (mask == M_CACHE_AB) |
6149 | fmt = "k,o(b)"; | |
252b5132 RH |
6150 | else if (coproc) |
6151 | fmt = "E,o(b)"; | |
6152 | else | |
6153 | fmt = "t,o(b)"; | |
6154 | ||
6155 | if (offset_expr.X_op != O_constant | |
6156 | && offset_expr.X_op != O_symbol) | |
6157 | { | |
6158 | as_bad (_("expression too complex")); | |
6159 | offset_expr.X_op = O_constant; | |
6160 | } | |
6161 | ||
2051e8c4 MR |
6162 | if (HAVE_32BIT_ADDRESSES |
6163 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
6164 | { |
6165 | char value [32]; | |
6166 | ||
6167 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 6168 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 6169 | } |
2051e8c4 | 6170 | |
252b5132 RH |
6171 | /* A constant expression in PIC code can be handled just as it |
6172 | is in non PIC code. */ | |
aed1a261 RS |
6173 | if (offset_expr.X_op == O_constant) |
6174 | { | |
aed1a261 RS |
6175 | expr1.X_add_number = ((offset_expr.X_add_number + 0x8000) |
6176 | & ~(bfd_vma) 0xffff); | |
2051e8c4 | 6177 | normalize_address_expr (&expr1); |
aed1a261 RS |
6178 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); |
6179 | if (breg != 0) | |
6180 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
6181 | tempreg, tempreg, breg); | |
6182 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, tempreg); | |
6183 | } | |
6184 | else if (mips_pic == NO_PIC) | |
252b5132 RH |
6185 | { |
6186 | /* If this is a reference to a GP relative symbol, and there | |
6187 | is no base register, we want | |
cdf6fd85 | 6188 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
6189 | Otherwise, if there is no base register, we want |
6190 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6191 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6192 | If we have a constant, we need two instructions anyhow, | |
6193 | so we always use the latter form. | |
6194 | ||
6195 | If we have a base register, and this is a reference to a | |
6196 | GP relative symbol, we want | |
6197 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 6198 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
6199 | Otherwise we want |
6200 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6201 | addu $tempreg,$tempreg,$breg | |
6202 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 6203 | With a constant we always use the latter case. |
76b3015f | 6204 | |
d6bc6245 TS |
6205 | With 64bit address space and no base register and $at usable, |
6206 | we want | |
6207 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6208 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6209 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6210 | dsll32 $tempreg,0 | |
6211 | daddu $tempreg,$at | |
6212 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6213 | If we have a base register, we want | |
6214 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6215 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6216 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6217 | daddu $at,$breg | |
6218 | dsll32 $tempreg,0 | |
6219 | daddu $tempreg,$at | |
6220 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6221 | ||
6222 | Without $at we can't generate the optimal path for superscalar | |
6223 | processors here since this would require two temporary registers. | |
6224 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6225 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6226 | dsll $tempreg,16 | |
6227 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6228 | dsll $tempreg,16 | |
6229 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6230 | If we have a base register, we want | |
6231 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6232 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6233 | dsll $tempreg,16 | |
6234 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6235 | dsll $tempreg,16 | |
6236 | daddu $tempreg,$tempreg,$breg | |
6237 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 | 6238 | |
6caf9ef4 | 6239 | For GP relative symbols in 64bit address space we can use |
aed1a261 RS |
6240 | the same sequence as in 32bit address space. */ |
6241 | if (HAVE_64BIT_SYMBOLS) | |
d6bc6245 | 6242 | { |
aed1a261 | 6243 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 TS |
6244 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
6245 | { | |
6246 | relax_start (offset_expr.X_add_symbol); | |
6247 | if (breg == 0) | |
6248 | { | |
6249 | macro_build (&offset_expr, s, fmt, treg, | |
6250 | BFD_RELOC_GPREL16, mips_gp_register); | |
6251 | } | |
6252 | else | |
6253 | { | |
6254 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
6255 | tempreg, breg, mips_gp_register); | |
6256 | macro_build (&offset_expr, s, fmt, treg, | |
6257 | BFD_RELOC_GPREL16, tempreg); | |
6258 | } | |
6259 | relax_switch (); | |
6260 | } | |
d6bc6245 | 6261 | |
b8285c27 | 6262 | if (used_at == 0 && !mips_opts.noat) |
d6bc6245 | 6263 | { |
67c0d1eb RS |
6264 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
6265 | BFD_RELOC_MIPS_HIGHEST); | |
6266 | macro_build (&offset_expr, "lui", "t,u", AT, | |
6267 | BFD_RELOC_HI16_S); | |
6268 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6269 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 6270 | if (breg != 0) |
67c0d1eb RS |
6271 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
6272 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); | |
6273 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
6274 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, | |
6275 | tempreg); | |
d6bc6245 TS |
6276 | used_at = 1; |
6277 | } | |
6278 | else | |
6279 | { | |
67c0d1eb RS |
6280 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
6281 | BFD_RELOC_MIPS_HIGHEST); | |
6282 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6283 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
6284 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
6285 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6286 | tempreg, BFD_RELOC_HI16_S); | |
6287 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
d6bc6245 | 6288 | if (breg != 0) |
67c0d1eb | 6289 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 6290 | tempreg, tempreg, breg); |
67c0d1eb | 6291 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6292 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 6293 | } |
6caf9ef4 TS |
6294 | |
6295 | if (mips_relax.sequence) | |
6296 | relax_end (); | |
8fc2e39e | 6297 | break; |
d6bc6245 | 6298 | } |
256ab948 | 6299 | |
252b5132 RH |
6300 | if (breg == 0) |
6301 | { | |
67c0d1eb | 6302 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 6303 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 6304 | { |
4d7206a2 | 6305 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6306 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, |
6307 | mips_gp_register); | |
4d7206a2 | 6308 | relax_switch (); |
252b5132 | 6309 | } |
67c0d1eb RS |
6310 | macro_build_lui (&offset_expr, tempreg); |
6311 | macro_build (&offset_expr, s, fmt, treg, | |
17a2f251 | 6312 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
6313 | if (mips_relax.sequence) |
6314 | relax_end (); | |
252b5132 RH |
6315 | } |
6316 | else | |
6317 | { | |
67c0d1eb | 6318 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 6319 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 6320 | { |
4d7206a2 | 6321 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6322 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6323 | tempreg, breg, mips_gp_register); |
67c0d1eb | 6324 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6325 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 6326 | relax_switch (); |
252b5132 | 6327 | } |
67c0d1eb RS |
6328 | macro_build_lui (&offset_expr, tempreg); |
6329 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6330 | tempreg, tempreg, breg); |
67c0d1eb | 6331 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6332 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
6333 | if (mips_relax.sequence) |
6334 | relax_end (); | |
252b5132 RH |
6335 | } |
6336 | } | |
0a44bf69 | 6337 | else if (!mips_big_got) |
252b5132 | 6338 | { |
ed6fb7bd | 6339 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 6340 | |
252b5132 RH |
6341 | /* If this is a reference to an external symbol, we want |
6342 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6343 | nop | |
6344 | <op> $treg,0($tempreg) | |
6345 | Otherwise we want | |
6346 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6347 | nop | |
6348 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6349 | <op> $treg,0($tempreg) | |
f5040a92 AO |
6350 | |
6351 | For NewABI, we want | |
6352 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6353 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
6354 | ||
252b5132 RH |
6355 | If there is a base register, we add it to $tempreg before |
6356 | the <op>. If there is a constant, we stick it in the | |
6357 | <op> instruction. We don't handle constants larger than | |
6358 | 16 bits, because we have no way to load the upper 16 bits | |
6359 | (actually, we could handle them for the subset of cases | |
6360 | in which we are not using $at). */ | |
6361 | assert (offset_expr.X_op == O_symbol); | |
f5040a92 AO |
6362 | if (HAVE_NEWABI) |
6363 | { | |
67c0d1eb RS |
6364 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6365 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6366 | if (breg != 0) |
67c0d1eb | 6367 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6368 | tempreg, tempreg, breg); |
67c0d1eb | 6369 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6370 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
6371 | break; |
6372 | } | |
252b5132 RH |
6373 | expr1.X_add_number = offset_expr.X_add_number; |
6374 | offset_expr.X_add_number = 0; | |
6375 | if (expr1.X_add_number < -0x8000 | |
6376 | || expr1.X_add_number >= 0x8000) | |
6377 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
6378 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6379 | lw_reloc_type, mips_gp_register); | |
269137b2 | 6380 | load_delay_nop (); |
4d7206a2 RS |
6381 | relax_start (offset_expr.X_add_symbol); |
6382 | relax_switch (); | |
67c0d1eb RS |
6383 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6384 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 6385 | relax_end (); |
252b5132 | 6386 | if (breg != 0) |
67c0d1eb | 6387 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6388 | tempreg, tempreg, breg); |
67c0d1eb | 6389 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6390 | } |
0a44bf69 | 6391 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 6392 | { |
67c0d1eb | 6393 | int gpdelay; |
252b5132 RH |
6394 | |
6395 | /* If this is a reference to an external symbol, we want | |
6396 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6397 | addu $tempreg,$tempreg,$gp | |
6398 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6399 | <op> $treg,0($tempreg) | |
6400 | Otherwise we want | |
6401 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6402 | nop | |
6403 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6404 | <op> $treg,0($tempreg) | |
6405 | If there is a base register, we add it to $tempreg before | |
6406 | the <op>. If there is a constant, we stick it in the | |
6407 | <op> instruction. We don't handle constants larger than | |
6408 | 16 bits, because we have no way to load the upper 16 bits | |
6409 | (actually, we could handle them for the subset of cases | |
f5040a92 | 6410 | in which we are not using $at). */ |
252b5132 RH |
6411 | assert (offset_expr.X_op == O_symbol); |
6412 | expr1.X_add_number = offset_expr.X_add_number; | |
6413 | offset_expr.X_add_number = 0; | |
6414 | if (expr1.X_add_number < -0x8000 | |
6415 | || expr1.X_add_number >= 0x8000) | |
6416 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6417 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 6418 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6419 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6420 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6421 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6422 | mips_gp_register); | |
6423 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6424 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 6425 | relax_switch (); |
67c0d1eb RS |
6426 | if (gpdelay) |
6427 | macro_build (NULL, "nop", ""); | |
6428 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6429 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6430 | load_delay_nop (); |
67c0d1eb RS |
6431 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6432 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
6433 | relax_end (); |
6434 | ||
252b5132 | 6435 | if (breg != 0) |
67c0d1eb | 6436 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6437 | tempreg, tempreg, breg); |
67c0d1eb | 6438 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6439 | } |
0a44bf69 | 6440 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 6441 | { |
f5040a92 AO |
6442 | /* If this is a reference to an external symbol, we want |
6443 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6444 | add $tempreg,$tempreg,$gp | |
6445 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6446 | <op> $treg,<ofst>($tempreg) | |
6447 | Otherwise, for local symbols, we want: | |
6448 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6449 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
6450 | assert (offset_expr.X_op == O_symbol); | |
4d7206a2 | 6451 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
6452 | offset_expr.X_add_number = 0; |
6453 | if (expr1.X_add_number < -0x8000 | |
6454 | || expr1.X_add_number >= 0x8000) | |
6455 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 6456 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6457 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6458 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6459 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6460 | mips_gp_register); | |
6461 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6462 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 6463 | if (breg != 0) |
67c0d1eb | 6464 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6465 | tempreg, tempreg, breg); |
67c0d1eb | 6466 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
684022ea | 6467 | |
4d7206a2 | 6468 | relax_switch (); |
f5040a92 | 6469 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
6470 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6471 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6472 | if (breg != 0) |
67c0d1eb | 6473 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6474 | tempreg, tempreg, breg); |
67c0d1eb | 6475 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6476 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 6477 | relax_end (); |
f5040a92 | 6478 | } |
252b5132 RH |
6479 | else |
6480 | abort (); | |
6481 | ||
252b5132 RH |
6482 | break; |
6483 | ||
6484 | case M_LI: | |
6485 | case M_LI_S: | |
67c0d1eb | 6486 | load_register (treg, &imm_expr, 0); |
8fc2e39e | 6487 | break; |
252b5132 RH |
6488 | |
6489 | case M_DLI: | |
67c0d1eb | 6490 | load_register (treg, &imm_expr, 1); |
8fc2e39e | 6491 | break; |
252b5132 RH |
6492 | |
6493 | case M_LI_SS: | |
6494 | if (imm_expr.X_op == O_constant) | |
6495 | { | |
8fc2e39e | 6496 | used_at = 1; |
67c0d1eb RS |
6497 | load_register (AT, &imm_expr, 0); |
6498 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6499 | break; |
6500 | } | |
6501 | else | |
6502 | { | |
6503 | assert (offset_expr.X_op == O_symbol | |
6504 | && strcmp (segment_name (S_GET_SEGMENT | |
6505 | (offset_expr.X_add_symbol)), | |
6506 | ".lit4") == 0 | |
6507 | && offset_expr.X_add_number == 0); | |
67c0d1eb | 6508 | macro_build (&offset_expr, "lwc1", "T,o(b)", treg, |
17a2f251 | 6509 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 6510 | break; |
252b5132 RH |
6511 | } |
6512 | ||
6513 | case M_LI_D: | |
ca4e0257 RS |
6514 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
6515 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
6516 | order 32 bits of the value and the low order 32 bits are either | |
6517 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
6518 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6519 | { | |
ca4e0257 | 6520 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 6521 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
6522 | else |
6523 | { | |
6524 | int hreg, lreg; | |
6525 | ||
6526 | if (target_big_endian) | |
6527 | { | |
6528 | hreg = treg; | |
6529 | lreg = treg + 1; | |
6530 | } | |
6531 | else | |
6532 | { | |
6533 | hreg = treg + 1; | |
6534 | lreg = treg; | |
6535 | } | |
6536 | ||
6537 | if (hreg <= 31) | |
67c0d1eb | 6538 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
6539 | if (lreg <= 31) |
6540 | { | |
6541 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 6542 | move_register (lreg, 0); |
252b5132 RH |
6543 | else |
6544 | { | |
6545 | assert (offset_expr.X_op == O_constant); | |
67c0d1eb | 6546 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
6547 | } |
6548 | } | |
6549 | } | |
8fc2e39e | 6550 | break; |
252b5132 RH |
6551 | } |
6552 | ||
6553 | /* We know that sym is in the .rdata section. First we get the | |
6554 | upper 16 bits of the address. */ | |
6555 | if (mips_pic == NO_PIC) | |
6556 | { | |
67c0d1eb | 6557 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 6558 | used_at = 1; |
252b5132 | 6559 | } |
0a44bf69 | 6560 | else |
252b5132 | 6561 | { |
67c0d1eb RS |
6562 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6563 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 6564 | used_at = 1; |
252b5132 | 6565 | } |
bdaaa2e1 | 6566 | |
252b5132 | 6567 | /* Now we load the register(s). */ |
ca4e0257 | 6568 | if (HAVE_64BIT_GPRS) |
8fc2e39e TS |
6569 | { |
6570 | used_at = 1; | |
6571 | macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
6572 | } | |
252b5132 RH |
6573 | else |
6574 | { | |
8fc2e39e | 6575 | used_at = 1; |
67c0d1eb | 6576 | macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
f9419b05 | 6577 | if (treg != RA) |
252b5132 RH |
6578 | { |
6579 | /* FIXME: How in the world do we deal with the possible | |
6580 | overflow here? */ | |
6581 | offset_expr.X_add_number += 4; | |
67c0d1eb | 6582 | macro_build (&offset_expr, "lw", "t,o(b)", |
17a2f251 | 6583 | treg + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
6584 | } |
6585 | } | |
252b5132 RH |
6586 | break; |
6587 | ||
6588 | case M_LI_DD: | |
ca4e0257 RS |
6589 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
6590 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
6591 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
6592 | the value and the low order 32 bits are either zero or in | |
6593 | OFFSET_EXPR. */ | |
252b5132 RH |
6594 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6595 | { | |
8fc2e39e | 6596 | used_at = 1; |
67c0d1eb | 6597 | load_register (AT, &imm_expr, HAVE_64BIT_FPRS); |
ca4e0257 RS |
6598 | if (HAVE_64BIT_FPRS) |
6599 | { | |
6600 | assert (HAVE_64BIT_GPRS); | |
67c0d1eb | 6601 | macro_build (NULL, "dmtc1", "t,S", AT, treg); |
ca4e0257 | 6602 | } |
252b5132 RH |
6603 | else |
6604 | { | |
67c0d1eb | 6605 | macro_build (NULL, "mtc1", "t,G", AT, treg + 1); |
252b5132 | 6606 | if (offset_expr.X_op == O_absent) |
67c0d1eb | 6607 | macro_build (NULL, "mtc1", "t,G", 0, treg); |
252b5132 RH |
6608 | else |
6609 | { | |
6610 | assert (offset_expr.X_op == O_constant); | |
67c0d1eb RS |
6611 | load_register (AT, &offset_expr, 0); |
6612 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6613 | } |
6614 | } | |
6615 | break; | |
6616 | } | |
6617 | ||
6618 | assert (offset_expr.X_op == O_symbol | |
6619 | && offset_expr.X_add_number == 0); | |
6620 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
6621 | if (strcmp (s, ".lit8") == 0) | |
6622 | { | |
e7af610e | 6623 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6624 | { |
67c0d1eb | 6625 | macro_build (&offset_expr, "ldc1", "T,o(b)", treg, |
17a2f251 | 6626 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 6627 | break; |
252b5132 | 6628 | } |
c9914766 | 6629 | breg = mips_gp_register; |
252b5132 RH |
6630 | r = BFD_RELOC_MIPS_LITERAL; |
6631 | goto dob; | |
6632 | } | |
6633 | else | |
6634 | { | |
6635 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); | |
8fc2e39e | 6636 | used_at = 1; |
0a44bf69 | 6637 | if (mips_pic != NO_PIC) |
67c0d1eb RS |
6638 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6639 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
6640 | else |
6641 | { | |
6642 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 6643 | macro_build_lui (&offset_expr, AT); |
252b5132 | 6644 | } |
bdaaa2e1 | 6645 | |
e7af610e | 6646 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6647 | { |
67c0d1eb RS |
6648 | macro_build (&offset_expr, "ldc1", "T,o(b)", |
6649 | treg, BFD_RELOC_LO16, AT); | |
252b5132 RH |
6650 | break; |
6651 | } | |
6652 | breg = AT; | |
6653 | r = BFD_RELOC_LO16; | |
6654 | goto dob; | |
6655 | } | |
6656 | ||
6657 | case M_L_DOB: | |
fef14a42 | 6658 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6659 | { |
6660 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6661 | break; |
252b5132 RH |
6662 | } |
6663 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6664 | to adjust when loading from memory. */ | |
6665 | r = BFD_RELOC_LO16; | |
6666 | dob: | |
e7af610e | 6667 | assert (mips_opts.isa == ISA_MIPS1); |
67c0d1eb | 6668 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 6669 | target_big_endian ? treg + 1 : treg, r, breg); |
252b5132 RH |
6670 | /* FIXME: A possible overflow which I don't know how to deal |
6671 | with. */ | |
6672 | offset_expr.X_add_number += 4; | |
67c0d1eb | 6673 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 6674 | target_big_endian ? treg : treg + 1, r, breg); |
252b5132 RH |
6675 | break; |
6676 | ||
6677 | case M_L_DAB: | |
6678 | /* | |
6679 | * The MIPS assembler seems to check for X_add_number not | |
6680 | * being double aligned and generating: | |
6681 | * lui at,%hi(foo+1) | |
6682 | * addu at,at,v1 | |
6683 | * addiu at,at,%lo(foo+1) | |
6684 | * lwc1 f2,0(at) | |
6685 | * lwc1 f3,4(at) | |
6686 | * But, the resulting address is the same after relocation so why | |
6687 | * generate the extra instruction? | |
6688 | */ | |
fef14a42 | 6689 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6690 | { |
6691 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6692 | break; |
252b5132 | 6693 | } |
bdaaa2e1 | 6694 | /* Itbl support may require additional care here. */ |
252b5132 | 6695 | coproc = 1; |
e7af610e | 6696 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6697 | { |
6698 | s = "ldc1"; | |
6699 | goto ld; | |
6700 | } | |
6701 | ||
6702 | s = "lwc1"; | |
6703 | fmt = "T,o(b)"; | |
6704 | goto ldd_std; | |
6705 | ||
6706 | case M_S_DAB: | |
fef14a42 | 6707 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6708 | { |
6709 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6710 | break; |
252b5132 RH |
6711 | } |
6712 | ||
e7af610e | 6713 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6714 | { |
6715 | s = "sdc1"; | |
6716 | goto st; | |
6717 | } | |
6718 | ||
6719 | s = "swc1"; | |
6720 | fmt = "T,o(b)"; | |
bdaaa2e1 | 6721 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6722 | coproc = 1; |
6723 | goto ldd_std; | |
6724 | ||
6725 | case M_LD_AB: | |
ca4e0257 | 6726 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6727 | { |
6728 | s = "ld"; | |
6729 | goto ld; | |
6730 | } | |
6731 | ||
6732 | s = "lw"; | |
6733 | fmt = "t,o(b)"; | |
6734 | goto ldd_std; | |
6735 | ||
6736 | case M_SD_AB: | |
ca4e0257 | 6737 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6738 | { |
6739 | s = "sd"; | |
6740 | goto st; | |
6741 | } | |
6742 | ||
6743 | s = "sw"; | |
6744 | fmt = "t,o(b)"; | |
6745 | ||
6746 | ldd_std: | |
6747 | if (offset_expr.X_op != O_symbol | |
6748 | && offset_expr.X_op != O_constant) | |
6749 | { | |
6750 | as_bad (_("expression too complex")); | |
6751 | offset_expr.X_op = O_constant; | |
6752 | } | |
6753 | ||
2051e8c4 MR |
6754 | if (HAVE_32BIT_ADDRESSES |
6755 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
6756 | { |
6757 | char value [32]; | |
6758 | ||
6759 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 6760 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 6761 | } |
2051e8c4 | 6762 | |
252b5132 RH |
6763 | /* Even on a big endian machine $fn comes before $fn+1. We have |
6764 | to adjust when loading from memory. We set coproc if we must | |
6765 | load $fn+1 first. */ | |
bdaaa2e1 | 6766 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6767 | if (! target_big_endian) |
6768 | coproc = 0; | |
6769 | ||
6770 | if (mips_pic == NO_PIC | |
6771 | || offset_expr.X_op == O_constant) | |
6772 | { | |
6773 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 TS |
6774 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
6775 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6776 | If we have a base register, we use this |
6777 | addu $at,$breg,$gp | |
cdf6fd85 TS |
6778 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
6779 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6780 | If this is not a GP relative symbol, we want |
6781 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6782 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6783 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6784 | If there is a base register, we add it to $at after the | |
6785 | lui instruction. If there is a constant, we always use | |
6786 | the last case. */ | |
39a59cf8 MR |
6787 | if (offset_expr.X_op == O_symbol |
6788 | && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 6789 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 6790 | { |
4d7206a2 | 6791 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
6792 | if (breg == 0) |
6793 | { | |
c9914766 | 6794 | tempreg = mips_gp_register; |
252b5132 RH |
6795 | } |
6796 | else | |
6797 | { | |
67c0d1eb | 6798 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6799 | AT, breg, mips_gp_register); |
252b5132 | 6800 | tempreg = AT; |
252b5132 RH |
6801 | used_at = 1; |
6802 | } | |
6803 | ||
beae10d5 | 6804 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6805 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6806 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6807 | offset_expr.X_add_number += 4; |
6808 | ||
6809 | /* Set mips_optimize to 2 to avoid inserting an | |
6810 | undesired nop. */ | |
6811 | hold_mips_optimize = mips_optimize; | |
6812 | mips_optimize = 2; | |
beae10d5 | 6813 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6814 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6815 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6816 | mips_optimize = hold_mips_optimize; |
6817 | ||
4d7206a2 | 6818 | relax_switch (); |
252b5132 RH |
6819 | |
6820 | /* We just generated two relocs. When tc_gen_reloc | |
6821 | handles this case, it will skip the first reloc and | |
6822 | handle the second. The second reloc already has an | |
6823 | extra addend of 4, which we added above. We must | |
6824 | subtract it out, and then subtract another 4 to make | |
6825 | the first reloc come out right. The second reloc | |
6826 | will come out right because we are going to add 4 to | |
6827 | offset_expr when we build its instruction below. | |
6828 | ||
6829 | If we have a symbol, then we don't want to include | |
6830 | the offset, because it will wind up being included | |
6831 | when we generate the reloc. */ | |
6832 | ||
6833 | if (offset_expr.X_op == O_constant) | |
6834 | offset_expr.X_add_number -= 8; | |
6835 | else | |
6836 | { | |
6837 | offset_expr.X_add_number = -4; | |
6838 | offset_expr.X_op = O_constant; | |
6839 | } | |
6840 | } | |
8fc2e39e | 6841 | used_at = 1; |
67c0d1eb | 6842 | macro_build_lui (&offset_expr, AT); |
252b5132 | 6843 | if (breg != 0) |
67c0d1eb | 6844 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6845 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6846 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6847 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6848 | /* FIXME: How do we handle overflow here? */ |
6849 | offset_expr.X_add_number += 4; | |
beae10d5 | 6850 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6851 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6852 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
6853 | if (mips_relax.sequence) |
6854 | relax_end (); | |
bdaaa2e1 | 6855 | } |
0a44bf69 | 6856 | else if (!mips_big_got) |
252b5132 | 6857 | { |
252b5132 RH |
6858 | /* If this is a reference to an external symbol, we want |
6859 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6860 | nop | |
6861 | <op> $treg,0($at) | |
6862 | <op> $treg+1,4($at) | |
6863 | Otherwise we want | |
6864 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6865 | nop | |
6866 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6867 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6868 | If there is a base register we add it to $at before the | |
6869 | lwc1 instructions. If there is a constant we include it | |
6870 | in the lwc1 instructions. */ | |
6871 | used_at = 1; | |
6872 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
6873 | if (expr1.X_add_number < -0x8000 |
6874 | || expr1.X_add_number >= 0x8000 - 4) | |
6875 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6876 | load_got_offset (AT, &offset_expr); |
269137b2 | 6877 | load_delay_nop (); |
252b5132 | 6878 | if (breg != 0) |
67c0d1eb | 6879 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
6880 | |
6881 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6882 | nop. */ | |
6883 | hold_mips_optimize = mips_optimize; | |
6884 | mips_optimize = 2; | |
4d7206a2 | 6885 | |
beae10d5 | 6886 | /* Itbl support may require additional care here. */ |
4d7206a2 | 6887 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6888 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
6889 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6890 | expr1.X_add_number += 4; |
67c0d1eb RS |
6891 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
6892 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6893 | relax_switch (); |
67c0d1eb RS |
6894 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
6895 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6896 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
6897 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
6898 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6899 | relax_end (); |
252b5132 | 6900 | |
4d7206a2 | 6901 | mips_optimize = hold_mips_optimize; |
252b5132 | 6902 | } |
0a44bf69 | 6903 | else if (mips_big_got) |
252b5132 | 6904 | { |
67c0d1eb | 6905 | int gpdelay; |
252b5132 RH |
6906 | |
6907 | /* If this is a reference to an external symbol, we want | |
6908 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6909 | addu $at,$at,$gp | |
6910 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
6911 | nop | |
6912 | <op> $treg,0($at) | |
6913 | <op> $treg+1,4($at) | |
6914 | Otherwise we want | |
6915 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6916 | nop | |
6917 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6918 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6919 | If there is a base register we add it to $at before the | |
6920 | lwc1 instructions. If there is a constant we include it | |
6921 | in the lwc1 instructions. */ | |
6922 | used_at = 1; | |
6923 | expr1.X_add_number = offset_expr.X_add_number; | |
6924 | offset_expr.X_add_number = 0; | |
6925 | if (expr1.X_add_number < -0x8000 | |
6926 | || expr1.X_add_number >= 0x8000 - 4) | |
6927 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6928 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 6929 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6930 | macro_build (&offset_expr, "lui", "t,u", |
6931 | AT, BFD_RELOC_MIPS_GOT_HI16); | |
6932 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6933 | AT, AT, mips_gp_register); |
67c0d1eb | 6934 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 6935 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 6936 | load_delay_nop (); |
252b5132 | 6937 | if (breg != 0) |
67c0d1eb | 6938 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6939 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6940 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6941 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6942 | expr1.X_add_number += 4; |
6943 | ||
6944 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6945 | nop. */ | |
6946 | hold_mips_optimize = mips_optimize; | |
6947 | mips_optimize = 2; | |
beae10d5 | 6948 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6949 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6950 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6951 | mips_optimize = hold_mips_optimize; |
6952 | expr1.X_add_number -= 4; | |
6953 | ||
4d7206a2 RS |
6954 | relax_switch (); |
6955 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
6956 | if (gpdelay) |
6957 | macro_build (NULL, "nop", ""); | |
6958 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
6959 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6960 | load_delay_nop (); |
252b5132 | 6961 | if (breg != 0) |
67c0d1eb | 6962 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6963 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
6964 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
6965 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6966 | offset_expr.X_add_number += 4; |
252b5132 RH |
6967 | |
6968 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6969 | nop. */ | |
6970 | hold_mips_optimize = mips_optimize; | |
6971 | mips_optimize = 2; | |
beae10d5 | 6972 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
6973 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
6974 | BFD_RELOC_LO16, AT); | |
252b5132 | 6975 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 6976 | relax_end (); |
252b5132 | 6977 | } |
252b5132 RH |
6978 | else |
6979 | abort (); | |
6980 | ||
252b5132 RH |
6981 | break; |
6982 | ||
6983 | case M_LD_OB: | |
6984 | s = "lw"; | |
6985 | goto sd_ob; | |
6986 | case M_SD_OB: | |
6987 | s = "sw"; | |
6988 | sd_ob: | |
ca4e0257 | 6989 | assert (HAVE_32BIT_ADDRESSES); |
67c0d1eb | 6990 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 | 6991 | offset_expr.X_add_number += 4; |
67c0d1eb | 6992 | macro_build (&offset_expr, s, "t,o(b)", treg + 1, BFD_RELOC_LO16, breg); |
8fc2e39e | 6993 | break; |
252b5132 RH |
6994 | |
6995 | /* New code added to support COPZ instructions. | |
6996 | This code builds table entries out of the macros in mip_opcodes. | |
6997 | R4000 uses interlocks to handle coproc delays. | |
6998 | Other chips (like the R3000) require nops to be inserted for delays. | |
6999 | ||
f72c8c98 | 7000 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
7001 | In order to fill delay slots for non-interlocked chips, |
7002 | we must have a way to specify delays based on the coprocessor. | |
7003 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
7004 | What are the side-effects of the cop instruction? | |
7005 | What cache support might we have and what are its effects? | |
7006 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 7007 | What registers are read/set/modified? |
252b5132 RH |
7008 | |
7009 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 7010 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
7011 | |
7012 | case M_COP0: | |
7013 | s = "c0"; | |
7014 | goto copz; | |
7015 | case M_COP1: | |
7016 | s = "c1"; | |
7017 | goto copz; | |
7018 | case M_COP2: | |
7019 | s = "c2"; | |
7020 | goto copz; | |
7021 | case M_COP3: | |
7022 | s = "c3"; | |
7023 | copz: | |
7024 | /* For now we just do C (same as Cz). The parameter will be | |
7025 | stored in insn_opcode by mips_ip. */ | |
67c0d1eb | 7026 | macro_build (NULL, s, "C", ip->insn_opcode); |
8fc2e39e | 7027 | break; |
252b5132 | 7028 | |
ea1fb5dc | 7029 | case M_MOVE: |
67c0d1eb | 7030 | move_register (dreg, sreg); |
8fc2e39e | 7031 | break; |
ea1fb5dc | 7032 | |
252b5132 RH |
7033 | #ifdef LOSING_COMPILER |
7034 | default: | |
7035 | /* Try and see if this is a new itbl instruction. | |
7036 | This code builds table entries out of the macros in mip_opcodes. | |
7037 | FIXME: For now we just assemble the expression and pass it's | |
7038 | value along as a 32-bit immediate. | |
bdaaa2e1 | 7039 | We may want to have the assembler assemble this value, |
252b5132 RH |
7040 | so that we gain the assembler's knowledge of delay slots, |
7041 | symbols, etc. | |
7042 | Would it be more efficient to use mask (id) here? */ | |
bdaaa2e1 | 7043 | if (itbl_have_entries |
252b5132 | 7044 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
beae10d5 | 7045 | { |
252b5132 RH |
7046 | s = ip->insn_mo->name; |
7047 | s2 = "cop3"; | |
7048 | coproc = ITBL_DECODE_PNUM (immed_expr);; | |
67c0d1eb | 7049 | macro_build (&immed_expr, s, "C"); |
8fc2e39e | 7050 | break; |
beae10d5 | 7051 | } |
252b5132 | 7052 | macro2 (ip); |
8fc2e39e | 7053 | break; |
252b5132 | 7054 | } |
8fc2e39e TS |
7055 | if (mips_opts.noat && used_at) |
7056 | as_bad (_("Macro used $at after \".set noat\"")); | |
252b5132 | 7057 | } |
bdaaa2e1 | 7058 | |
252b5132 | 7059 | static void |
17a2f251 | 7060 | macro2 (struct mips_cl_insn *ip) |
252b5132 RH |
7061 | { |
7062 | register int treg, sreg, dreg, breg; | |
7063 | int tempreg; | |
7064 | int mask; | |
252b5132 RH |
7065 | int used_at; |
7066 | expressionS expr1; | |
7067 | const char *s; | |
7068 | const char *s2; | |
7069 | const char *fmt; | |
7070 | int likely = 0; | |
7071 | int dbl = 0; | |
7072 | int coproc = 0; | |
7073 | int lr = 0; | |
7074 | int imm = 0; | |
7075 | int off; | |
7076 | offsetT maxnum; | |
7077 | bfd_reloc_code_real_type r; | |
bdaaa2e1 | 7078 | |
252b5132 RH |
7079 | treg = (ip->insn_opcode >> 16) & 0x1f; |
7080 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
7081 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
7082 | mask = ip->insn_mo->mask; | |
bdaaa2e1 | 7083 | |
252b5132 RH |
7084 | expr1.X_op = O_constant; |
7085 | expr1.X_op_symbol = NULL; | |
7086 | expr1.X_add_symbol = NULL; | |
7087 | expr1.X_add_number = 1; | |
bdaaa2e1 | 7088 | |
252b5132 RH |
7089 | switch (mask) |
7090 | { | |
7091 | #endif /* LOSING_COMPILER */ | |
7092 | ||
7093 | case M_DMUL: | |
7094 | dbl = 1; | |
7095 | case M_MUL: | |
67c0d1eb RS |
7096 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg); |
7097 | macro_build (NULL, "mflo", "d", dreg); | |
8fc2e39e | 7098 | break; |
252b5132 RH |
7099 | |
7100 | case M_DMUL_I: | |
7101 | dbl = 1; | |
7102 | case M_MUL_I: | |
7103 | /* The MIPS assembler some times generates shifts and adds. I'm | |
7104 | not trying to be that fancy. GCC should do this for us | |
7105 | anyway. */ | |
8fc2e39e | 7106 | used_at = 1; |
67c0d1eb RS |
7107 | load_register (AT, &imm_expr, dbl); |
7108 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT); | |
7109 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 RH |
7110 | break; |
7111 | ||
7112 | case M_DMULO_I: | |
7113 | dbl = 1; | |
7114 | case M_MULO_I: | |
7115 | imm = 1; | |
7116 | goto do_mulo; | |
7117 | ||
7118 | case M_DMULO: | |
7119 | dbl = 1; | |
7120 | case M_MULO: | |
7121 | do_mulo: | |
7d10b47d | 7122 | start_noreorder (); |
8fc2e39e | 7123 | used_at = 1; |
252b5132 | 7124 | if (imm) |
67c0d1eb RS |
7125 | load_register (AT, &imm_expr, dbl); |
7126 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); | |
7127 | macro_build (NULL, "mflo", "d", dreg); | |
7128 | macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA); | |
7129 | macro_build (NULL, "mfhi", "d", AT); | |
252b5132 | 7130 | if (mips_trap) |
67c0d1eb | 7131 | macro_build (NULL, "tne", "s,t,q", dreg, AT, 6); |
252b5132 RH |
7132 | else |
7133 | { | |
7134 | expr1.X_add_number = 8; | |
67c0d1eb RS |
7135 | macro_build (&expr1, "beq", "s,t,p", dreg, AT); |
7136 | macro_build (NULL, "nop", "", 0); | |
7137 | macro_build (NULL, "break", "c", 6); | |
252b5132 | 7138 | } |
7d10b47d | 7139 | end_noreorder (); |
67c0d1eb | 7140 | macro_build (NULL, "mflo", "d", dreg); |
252b5132 RH |
7141 | break; |
7142 | ||
7143 | case M_DMULOU_I: | |
7144 | dbl = 1; | |
7145 | case M_MULOU_I: | |
7146 | imm = 1; | |
7147 | goto do_mulou; | |
7148 | ||
7149 | case M_DMULOU: | |
7150 | dbl = 1; | |
7151 | case M_MULOU: | |
7152 | do_mulou: | |
7d10b47d | 7153 | start_noreorder (); |
8fc2e39e | 7154 | used_at = 1; |
252b5132 | 7155 | if (imm) |
67c0d1eb RS |
7156 | load_register (AT, &imm_expr, dbl); |
7157 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
17a2f251 | 7158 | sreg, imm ? AT : treg); |
67c0d1eb RS |
7159 | macro_build (NULL, "mfhi", "d", AT); |
7160 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 | 7161 | if (mips_trap) |
67c0d1eb | 7162 | macro_build (NULL, "tne", "s,t,q", AT, 0, 6); |
252b5132 RH |
7163 | else |
7164 | { | |
7165 | expr1.X_add_number = 8; | |
67c0d1eb RS |
7166 | macro_build (&expr1, "beq", "s,t,p", AT, 0); |
7167 | macro_build (NULL, "nop", "", 0); | |
7168 | macro_build (NULL, "break", "c", 6); | |
252b5132 | 7169 | } |
7d10b47d | 7170 | end_noreorder (); |
252b5132 RH |
7171 | break; |
7172 | ||
771c7ce4 | 7173 | case M_DROL: |
fef14a42 | 7174 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
7175 | { |
7176 | if (dreg == sreg) | |
7177 | { | |
7178 | tempreg = AT; | |
7179 | used_at = 1; | |
7180 | } | |
7181 | else | |
7182 | { | |
7183 | tempreg = dreg; | |
82dd0097 | 7184 | } |
67c0d1eb RS |
7185 | macro_build (NULL, "dnegu", "d,w", tempreg, treg); |
7186 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 7187 | break; |
82dd0097 | 7188 | } |
8fc2e39e | 7189 | used_at = 1; |
67c0d1eb RS |
7190 | macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); |
7191 | macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT); | |
7192 | macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg); | |
7193 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7194 | break; |
7195 | ||
252b5132 | 7196 | case M_ROL: |
fef14a42 | 7197 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 CD |
7198 | { |
7199 | if (dreg == sreg) | |
7200 | { | |
7201 | tempreg = AT; | |
7202 | used_at = 1; | |
7203 | } | |
7204 | else | |
7205 | { | |
7206 | tempreg = dreg; | |
82dd0097 | 7207 | } |
67c0d1eb RS |
7208 | macro_build (NULL, "negu", "d,w", tempreg, treg); |
7209 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 7210 | break; |
82dd0097 | 7211 | } |
8fc2e39e | 7212 | used_at = 1; |
67c0d1eb RS |
7213 | macro_build (NULL, "subu", "d,v,t", AT, 0, treg); |
7214 | macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT); | |
7215 | macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg); | |
7216 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7217 | break; |
7218 | ||
771c7ce4 TS |
7219 | case M_DROL_I: |
7220 | { | |
7221 | unsigned int rot; | |
82dd0097 | 7222 | char *l, *r; |
771c7ce4 TS |
7223 | |
7224 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7225 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7226 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 7227 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
7228 | { |
7229 | rot = (64 - rot) & 0x3f; | |
7230 | if (rot >= 32) | |
67c0d1eb | 7231 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
60b63b72 | 7232 | else |
67c0d1eb | 7233 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7234 | break; |
60b63b72 | 7235 | } |
483fc7cd | 7236 | if (rot == 0) |
483fc7cd | 7237 | { |
67c0d1eb | 7238 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7239 | break; |
483fc7cd | 7240 | } |
82dd0097 CD |
7241 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
7242 | r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; | |
7243 | rot &= 0x1f; | |
8fc2e39e | 7244 | used_at = 1; |
67c0d1eb RS |
7245 | macro_build (NULL, l, "d,w,<", AT, sreg, rot); |
7246 | macro_build (NULL, r, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7247 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7248 | } |
7249 | break; | |
7250 | ||
252b5132 | 7251 | case M_ROL_I: |
771c7ce4 TS |
7252 | { |
7253 | unsigned int rot; | |
7254 | ||
7255 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7256 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7257 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 7258 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 7259 | { |
67c0d1eb | 7260 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f); |
8fc2e39e | 7261 | break; |
60b63b72 | 7262 | } |
483fc7cd | 7263 | if (rot == 0) |
483fc7cd | 7264 | { |
67c0d1eb | 7265 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7266 | break; |
483fc7cd | 7267 | } |
8fc2e39e | 7268 | used_at = 1; |
67c0d1eb RS |
7269 | macro_build (NULL, "sll", "d,w,<", AT, sreg, rot); |
7270 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7271 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7272 | } |
7273 | break; | |
7274 | ||
7275 | case M_DROR: | |
fef14a42 | 7276 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 7277 | { |
67c0d1eb | 7278 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 7279 | break; |
82dd0097 | 7280 | } |
8fc2e39e | 7281 | used_at = 1; |
67c0d1eb RS |
7282 | macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); |
7283 | macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT); | |
7284 | macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg); | |
7285 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7286 | break; |
7287 | ||
7288 | case M_ROR: | |
fef14a42 | 7289 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7290 | { |
67c0d1eb | 7291 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 7292 | break; |
82dd0097 | 7293 | } |
8fc2e39e | 7294 | used_at = 1; |
67c0d1eb RS |
7295 | macro_build (NULL, "subu", "d,v,t", AT, 0, treg); |
7296 | macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT); | |
7297 | macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg); | |
7298 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7299 | break; |
7300 | ||
771c7ce4 TS |
7301 | case M_DROR_I: |
7302 | { | |
7303 | unsigned int rot; | |
82dd0097 | 7304 | char *l, *r; |
771c7ce4 TS |
7305 | |
7306 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7307 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7308 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 7309 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
7310 | { |
7311 | if (rot >= 32) | |
67c0d1eb | 7312 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
82dd0097 | 7313 | else |
67c0d1eb | 7314 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7315 | break; |
82dd0097 | 7316 | } |
483fc7cd | 7317 | if (rot == 0) |
483fc7cd | 7318 | { |
67c0d1eb | 7319 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7320 | break; |
483fc7cd | 7321 | } |
82dd0097 CD |
7322 | r = (rot < 0x20) ? "dsrl" : "dsrl32"; |
7323 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; | |
7324 | rot &= 0x1f; | |
8fc2e39e | 7325 | used_at = 1; |
67c0d1eb RS |
7326 | macro_build (NULL, r, "d,w,<", AT, sreg, rot); |
7327 | macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7328 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7329 | } |
7330 | break; | |
7331 | ||
252b5132 | 7332 | case M_ROR_I: |
771c7ce4 TS |
7333 | { |
7334 | unsigned int rot; | |
7335 | ||
7336 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7337 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7338 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 7339 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7340 | { |
67c0d1eb | 7341 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7342 | break; |
82dd0097 | 7343 | } |
483fc7cd | 7344 | if (rot == 0) |
483fc7cd | 7345 | { |
67c0d1eb | 7346 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7347 | break; |
483fc7cd | 7348 | } |
8fc2e39e | 7349 | used_at = 1; |
67c0d1eb RS |
7350 | macro_build (NULL, "srl", "d,w,<", AT, sreg, rot); |
7351 | macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7352 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 | 7353 | } |
252b5132 RH |
7354 | break; |
7355 | ||
7356 | case M_S_DOB: | |
fef14a42 | 7357 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
7358 | { |
7359 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 7360 | break; |
252b5132 | 7361 | } |
e7af610e | 7362 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
7363 | /* Even on a big endian machine $fn comes before $fn+1. We have |
7364 | to adjust when storing to memory. */ | |
67c0d1eb RS |
7365 | macro_build (&offset_expr, "swc1", "T,o(b)", |
7366 | target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg); | |
252b5132 | 7367 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
7368 | macro_build (&offset_expr, "swc1", "T,o(b)", |
7369 | target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg); | |
8fc2e39e | 7370 | break; |
252b5132 RH |
7371 | |
7372 | case M_SEQ: | |
7373 | if (sreg == 0) | |
67c0d1eb | 7374 | macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16); |
252b5132 | 7375 | else if (treg == 0) |
67c0d1eb | 7376 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7377 | else |
7378 | { | |
67c0d1eb RS |
7379 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7380 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 | 7381 | } |
8fc2e39e | 7382 | break; |
252b5132 RH |
7383 | |
7384 | case M_SEQ_I: | |
7385 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7386 | { | |
67c0d1eb | 7387 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7388 | break; |
252b5132 RH |
7389 | } |
7390 | if (sreg == 0) | |
7391 | { | |
7392 | as_warn (_("Instruction %s: result is always false"), | |
7393 | ip->insn_mo->name); | |
67c0d1eb | 7394 | move_register (dreg, 0); |
8fc2e39e | 7395 | break; |
252b5132 RH |
7396 | } |
7397 | if (imm_expr.X_op == O_constant | |
7398 | && imm_expr.X_add_number >= 0 | |
7399 | && imm_expr.X_add_number < 0x10000) | |
7400 | { | |
67c0d1eb | 7401 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7402 | } |
7403 | else if (imm_expr.X_op == O_constant | |
7404 | && imm_expr.X_add_number > -0x8000 | |
7405 | && imm_expr.X_add_number < 0) | |
7406 | { | |
7407 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7408 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7409 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7410 | } |
7411 | else | |
7412 | { | |
67c0d1eb RS |
7413 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7414 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7415 | used_at = 1; |
7416 | } | |
67c0d1eb | 7417 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 7418 | break; |
252b5132 RH |
7419 | |
7420 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
7421 | s = "slt"; | |
7422 | goto sge; | |
7423 | case M_SGEU: | |
7424 | s = "sltu"; | |
7425 | sge: | |
67c0d1eb RS |
7426 | macro_build (NULL, s, "d,v,t", dreg, sreg, treg); |
7427 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 7428 | break; |
252b5132 RH |
7429 | |
7430 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
7431 | case M_SGEU_I: | |
7432 | if (imm_expr.X_op == O_constant | |
7433 | && imm_expr.X_add_number >= -0x8000 | |
7434 | && imm_expr.X_add_number < 0x8000) | |
7435 | { | |
67c0d1eb RS |
7436 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
7437 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
7438 | } |
7439 | else | |
7440 | { | |
67c0d1eb RS |
7441 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7442 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", | |
7443 | dreg, sreg, AT); | |
252b5132 RH |
7444 | used_at = 1; |
7445 | } | |
67c0d1eb | 7446 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 7447 | break; |
252b5132 RH |
7448 | |
7449 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
7450 | s = "slt"; | |
7451 | goto sgt; | |
7452 | case M_SGTU: | |
7453 | s = "sltu"; | |
7454 | sgt: | |
67c0d1eb | 7455 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
8fc2e39e | 7456 | break; |
252b5132 RH |
7457 | |
7458 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
7459 | s = "slt"; | |
7460 | goto sgti; | |
7461 | case M_SGTU_I: | |
7462 | s = "sltu"; | |
7463 | sgti: | |
8fc2e39e | 7464 | used_at = 1; |
67c0d1eb RS |
7465 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7466 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
252b5132 RH |
7467 | break; |
7468 | ||
2396cfb9 | 7469 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
7470 | s = "slt"; |
7471 | goto sle; | |
7472 | case M_SLEU: | |
7473 | s = "sltu"; | |
7474 | sle: | |
67c0d1eb RS |
7475 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
7476 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 7477 | break; |
252b5132 | 7478 | |
2396cfb9 | 7479 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
7480 | s = "slt"; |
7481 | goto slei; | |
7482 | case M_SLEU_I: | |
7483 | s = "sltu"; | |
7484 | slei: | |
8fc2e39e | 7485 | used_at = 1; |
67c0d1eb RS |
7486 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7487 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
7488 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
7489 | break; |
7490 | ||
7491 | case M_SLT_I: | |
7492 | if (imm_expr.X_op == O_constant | |
7493 | && imm_expr.X_add_number >= -0x8000 | |
7494 | && imm_expr.X_add_number < 0x8000) | |
7495 | { | |
67c0d1eb | 7496 | macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7497 | break; |
252b5132 | 7498 | } |
8fc2e39e | 7499 | used_at = 1; |
67c0d1eb RS |
7500 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7501 | macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7502 | break; |
7503 | ||
7504 | case M_SLTU_I: | |
7505 | if (imm_expr.X_op == O_constant | |
7506 | && imm_expr.X_add_number >= -0x8000 | |
7507 | && imm_expr.X_add_number < 0x8000) | |
7508 | { | |
67c0d1eb | 7509 | macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg, |
17a2f251 | 7510 | BFD_RELOC_LO16); |
8fc2e39e | 7511 | break; |
252b5132 | 7512 | } |
8fc2e39e | 7513 | used_at = 1; |
67c0d1eb RS |
7514 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7515 | macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7516 | break; |
7517 | ||
7518 | case M_SNE: | |
7519 | if (sreg == 0) | |
67c0d1eb | 7520 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg); |
252b5132 | 7521 | else if (treg == 0) |
67c0d1eb | 7522 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
7523 | else |
7524 | { | |
67c0d1eb RS |
7525 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7526 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
252b5132 | 7527 | } |
8fc2e39e | 7528 | break; |
252b5132 RH |
7529 | |
7530 | case M_SNE_I: | |
7531 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7532 | { | |
67c0d1eb | 7533 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
8fc2e39e | 7534 | break; |
252b5132 RH |
7535 | } |
7536 | if (sreg == 0) | |
7537 | { | |
7538 | as_warn (_("Instruction %s: result is always true"), | |
7539 | ip->insn_mo->name); | |
67c0d1eb RS |
7540 | macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", |
7541 | dreg, 0, BFD_RELOC_LO16); | |
8fc2e39e | 7542 | break; |
252b5132 RH |
7543 | } |
7544 | if (imm_expr.X_op == O_constant | |
7545 | && imm_expr.X_add_number >= 0 | |
7546 | && imm_expr.X_add_number < 0x10000) | |
7547 | { | |
67c0d1eb | 7548 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7549 | } |
7550 | else if (imm_expr.X_op == O_constant | |
7551 | && imm_expr.X_add_number > -0x8000 | |
7552 | && imm_expr.X_add_number < 0) | |
7553 | { | |
7554 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7555 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7556 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7557 | } |
7558 | else | |
7559 | { | |
67c0d1eb RS |
7560 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7561 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7562 | used_at = 1; |
7563 | } | |
67c0d1eb | 7564 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); |
8fc2e39e | 7565 | break; |
252b5132 RH |
7566 | |
7567 | case M_DSUB_I: | |
7568 | dbl = 1; | |
7569 | case M_SUB_I: | |
7570 | if (imm_expr.X_op == O_constant | |
7571 | && imm_expr.X_add_number > -0x8000 | |
7572 | && imm_expr.X_add_number <= 0x8000) | |
7573 | { | |
7574 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7575 | macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j", |
7576 | dreg, sreg, BFD_RELOC_LO16); | |
8fc2e39e | 7577 | break; |
252b5132 | 7578 | } |
8fc2e39e | 7579 | used_at = 1; |
67c0d1eb RS |
7580 | load_register (AT, &imm_expr, dbl); |
7581 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7582 | break; |
7583 | ||
7584 | case M_DSUBU_I: | |
7585 | dbl = 1; | |
7586 | case M_SUBU_I: | |
7587 | if (imm_expr.X_op == O_constant | |
7588 | && imm_expr.X_add_number > -0x8000 | |
7589 | && imm_expr.X_add_number <= 0x8000) | |
7590 | { | |
7591 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7592 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j", |
7593 | dreg, sreg, BFD_RELOC_LO16); | |
8fc2e39e | 7594 | break; |
252b5132 | 7595 | } |
8fc2e39e | 7596 | used_at = 1; |
67c0d1eb RS |
7597 | load_register (AT, &imm_expr, dbl); |
7598 | macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7599 | break; |
7600 | ||
7601 | case M_TEQ_I: | |
7602 | s = "teq"; | |
7603 | goto trap; | |
7604 | case M_TGE_I: | |
7605 | s = "tge"; | |
7606 | goto trap; | |
7607 | case M_TGEU_I: | |
7608 | s = "tgeu"; | |
7609 | goto trap; | |
7610 | case M_TLT_I: | |
7611 | s = "tlt"; | |
7612 | goto trap; | |
7613 | case M_TLTU_I: | |
7614 | s = "tltu"; | |
7615 | goto trap; | |
7616 | case M_TNE_I: | |
7617 | s = "tne"; | |
7618 | trap: | |
8fc2e39e | 7619 | used_at = 1; |
67c0d1eb RS |
7620 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7621 | macro_build (NULL, s, "s,t", sreg, AT); | |
252b5132 RH |
7622 | break; |
7623 | ||
252b5132 | 7624 | case M_TRUNCWS: |
43841e91 | 7625 | case M_TRUNCWD: |
e7af610e | 7626 | assert (mips_opts.isa == ISA_MIPS1); |
8fc2e39e | 7627 | used_at = 1; |
252b5132 RH |
7628 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
7629 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
7630 | ||
7631 | /* | |
7632 | * Is the double cfc1 instruction a bug in the mips assembler; | |
7633 | * or is there a reason for it? | |
7634 | */ | |
7d10b47d | 7635 | start_noreorder (); |
67c0d1eb RS |
7636 | macro_build (NULL, "cfc1", "t,G", treg, RA); |
7637 | macro_build (NULL, "cfc1", "t,G", treg, RA); | |
7638 | macro_build (NULL, "nop", ""); | |
252b5132 | 7639 | expr1.X_add_number = 3; |
67c0d1eb | 7640 | macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16); |
252b5132 | 7641 | expr1.X_add_number = 2; |
67c0d1eb RS |
7642 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
7643 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
7644 | macro_build (NULL, "nop", ""); | |
7645 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
7646 | dreg, sreg); | |
7647 | macro_build (NULL, "ctc1", "t,G", treg, RA); | |
7648 | macro_build (NULL, "nop", ""); | |
7d10b47d | 7649 | end_noreorder (); |
252b5132 RH |
7650 | break; |
7651 | ||
7652 | case M_ULH: | |
7653 | s = "lb"; | |
7654 | goto ulh; | |
7655 | case M_ULHU: | |
7656 | s = "lbu"; | |
7657 | ulh: | |
8fc2e39e | 7658 | used_at = 1; |
252b5132 RH |
7659 | if (offset_expr.X_add_number >= 0x7fff) |
7660 | as_bad (_("operand overflow")); | |
252b5132 | 7661 | if (! target_big_endian) |
f9419b05 | 7662 | ++offset_expr.X_add_number; |
67c0d1eb | 7663 | macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 | 7664 | if (! target_big_endian) |
f9419b05 | 7665 | --offset_expr.X_add_number; |
252b5132 | 7666 | else |
f9419b05 | 7667 | ++offset_expr.X_add_number; |
67c0d1eb RS |
7668 | macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
7669 | macro_build (NULL, "sll", "d,w,<", AT, AT, 8); | |
7670 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7671 | break; |
7672 | ||
7673 | case M_ULD: | |
7674 | s = "ldl"; | |
7675 | s2 = "ldr"; | |
7676 | off = 7; | |
7677 | goto ulw; | |
7678 | case M_ULW: | |
7679 | s = "lwl"; | |
7680 | s2 = "lwr"; | |
7681 | off = 3; | |
7682 | ulw: | |
7683 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7684 | as_bad (_("operand overflow")); | |
af22f5b2 CD |
7685 | if (treg != breg) |
7686 | tempreg = treg; | |
7687 | else | |
8fc2e39e TS |
7688 | { |
7689 | used_at = 1; | |
7690 | tempreg = AT; | |
7691 | } | |
252b5132 RH |
7692 | if (! target_big_endian) |
7693 | offset_expr.X_add_number += off; | |
67c0d1eb | 7694 | macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7695 | if (! target_big_endian) |
7696 | offset_expr.X_add_number -= off; | |
7697 | else | |
7698 | offset_expr.X_add_number += off; | |
67c0d1eb | 7699 | macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
af22f5b2 CD |
7700 | |
7701 | /* If necessary, move the result in tempreg the final destination. */ | |
7702 | if (treg == tempreg) | |
8fc2e39e | 7703 | break; |
af22f5b2 | 7704 | /* Protect second load's delay slot. */ |
017315e4 | 7705 | load_delay_nop (); |
67c0d1eb | 7706 | move_register (treg, tempreg); |
af22f5b2 | 7707 | break; |
252b5132 RH |
7708 | |
7709 | case M_ULD_A: | |
7710 | s = "ldl"; | |
7711 | s2 = "ldr"; | |
7712 | off = 7; | |
7713 | goto ulwa; | |
7714 | case M_ULW_A: | |
7715 | s = "lwl"; | |
7716 | s2 = "lwr"; | |
7717 | off = 3; | |
7718 | ulwa: | |
d6bc6245 | 7719 | used_at = 1; |
67c0d1eb | 7720 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7721 | if (breg != 0) |
67c0d1eb | 7722 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7723 | if (! target_big_endian) |
7724 | expr1.X_add_number = off; | |
7725 | else | |
7726 | expr1.X_add_number = 0; | |
67c0d1eb | 7727 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7728 | if (! target_big_endian) |
7729 | expr1.X_add_number = 0; | |
7730 | else | |
7731 | expr1.X_add_number = off; | |
67c0d1eb | 7732 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7733 | break; |
7734 | ||
7735 | case M_ULH_A: | |
7736 | case M_ULHU_A: | |
d6bc6245 | 7737 | used_at = 1; |
67c0d1eb | 7738 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7739 | if (breg != 0) |
67c0d1eb | 7740 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7741 | if (target_big_endian) |
7742 | expr1.X_add_number = 0; | |
67c0d1eb | 7743 | macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", |
17a2f251 | 7744 | treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7745 | if (target_big_endian) |
7746 | expr1.X_add_number = 1; | |
7747 | else | |
7748 | expr1.X_add_number = 0; | |
67c0d1eb RS |
7749 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
7750 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
7751 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7752 | break; |
7753 | ||
7754 | case M_USH: | |
8fc2e39e | 7755 | used_at = 1; |
252b5132 RH |
7756 | if (offset_expr.X_add_number >= 0x7fff) |
7757 | as_bad (_("operand overflow")); | |
7758 | if (target_big_endian) | |
f9419b05 | 7759 | ++offset_expr.X_add_number; |
67c0d1eb RS |
7760 | macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
7761 | macro_build (NULL, "srl", "d,w,<", AT, treg, 8); | |
252b5132 | 7762 | if (target_big_endian) |
f9419b05 | 7763 | --offset_expr.X_add_number; |
252b5132 | 7764 | else |
f9419b05 | 7765 | ++offset_expr.X_add_number; |
67c0d1eb | 7766 | macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 RH |
7767 | break; |
7768 | ||
7769 | case M_USD: | |
7770 | s = "sdl"; | |
7771 | s2 = "sdr"; | |
7772 | off = 7; | |
7773 | goto usw; | |
7774 | case M_USW: | |
7775 | s = "swl"; | |
7776 | s2 = "swr"; | |
7777 | off = 3; | |
7778 | usw: | |
7779 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7780 | as_bad (_("operand overflow")); | |
7781 | if (! target_big_endian) | |
7782 | offset_expr.X_add_number += off; | |
67c0d1eb | 7783 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7784 | if (! target_big_endian) |
7785 | offset_expr.X_add_number -= off; | |
7786 | else | |
7787 | offset_expr.X_add_number += off; | |
67c0d1eb | 7788 | macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
8fc2e39e | 7789 | break; |
252b5132 RH |
7790 | |
7791 | case M_USD_A: | |
7792 | s = "sdl"; | |
7793 | s2 = "sdr"; | |
7794 | off = 7; | |
7795 | goto uswa; | |
7796 | case M_USW_A: | |
7797 | s = "swl"; | |
7798 | s2 = "swr"; | |
7799 | off = 3; | |
7800 | uswa: | |
d6bc6245 | 7801 | used_at = 1; |
67c0d1eb | 7802 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7803 | if (breg != 0) |
67c0d1eb | 7804 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7805 | if (! target_big_endian) |
7806 | expr1.X_add_number = off; | |
7807 | else | |
7808 | expr1.X_add_number = 0; | |
67c0d1eb | 7809 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7810 | if (! target_big_endian) |
7811 | expr1.X_add_number = 0; | |
7812 | else | |
7813 | expr1.X_add_number = off; | |
67c0d1eb | 7814 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7815 | break; |
7816 | ||
7817 | case M_USH_A: | |
d6bc6245 | 7818 | used_at = 1; |
67c0d1eb | 7819 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7820 | if (breg != 0) |
67c0d1eb | 7821 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7822 | if (! target_big_endian) |
7823 | expr1.X_add_number = 0; | |
67c0d1eb RS |
7824 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
7825 | macro_build (NULL, "srl", "d,w,<", treg, treg, 8); | |
252b5132 RH |
7826 | if (! target_big_endian) |
7827 | expr1.X_add_number = 1; | |
7828 | else | |
7829 | expr1.X_add_number = 0; | |
67c0d1eb | 7830 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7831 | if (! target_big_endian) |
7832 | expr1.X_add_number = 0; | |
7833 | else | |
7834 | expr1.X_add_number = 1; | |
67c0d1eb RS |
7835 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
7836 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
7837 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7838 | break; |
7839 | ||
7840 | default: | |
7841 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 7842 | are added dynamically. */ |
252b5132 RH |
7843 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
7844 | break; | |
7845 | } | |
8fc2e39e TS |
7846 | if (mips_opts.noat && used_at) |
7847 | as_bad (_("Macro used $at after \".set noat\"")); | |
252b5132 RH |
7848 | } |
7849 | ||
7850 | /* Implement macros in mips16 mode. */ | |
7851 | ||
7852 | static void | |
17a2f251 | 7853 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 RH |
7854 | { |
7855 | int mask; | |
7856 | int xreg, yreg, zreg, tmp; | |
252b5132 RH |
7857 | expressionS expr1; |
7858 | int dbl; | |
7859 | const char *s, *s2, *s3; | |
7860 | ||
7861 | mask = ip->insn_mo->mask; | |
7862 | ||
bf12938e RS |
7863 | xreg = MIPS16_EXTRACT_OPERAND (RX, *ip); |
7864 | yreg = MIPS16_EXTRACT_OPERAND (RY, *ip); | |
7865 | zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip); | |
252b5132 | 7866 | |
252b5132 RH |
7867 | expr1.X_op = O_constant; |
7868 | expr1.X_op_symbol = NULL; | |
7869 | expr1.X_add_symbol = NULL; | |
7870 | expr1.X_add_number = 1; | |
7871 | ||
7872 | dbl = 0; | |
7873 | ||
7874 | switch (mask) | |
7875 | { | |
7876 | default: | |
7877 | internalError (); | |
7878 | ||
7879 | case M_DDIV_3: | |
7880 | dbl = 1; | |
7881 | case M_DIV_3: | |
7882 | s = "mflo"; | |
7883 | goto do_div3; | |
7884 | case M_DREM_3: | |
7885 | dbl = 1; | |
7886 | case M_REM_3: | |
7887 | s = "mfhi"; | |
7888 | do_div3: | |
7d10b47d | 7889 | start_noreorder (); |
67c0d1eb | 7890 | macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg); |
252b5132 | 7891 | expr1.X_add_number = 2; |
67c0d1eb RS |
7892 | macro_build (&expr1, "bnez", "x,p", yreg); |
7893 | macro_build (NULL, "break", "6", 7); | |
bdaaa2e1 | 7894 | |
252b5132 RH |
7895 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
7896 | since that causes an overflow. We should do that as well, | |
7897 | but I don't see how to do the comparisons without a temporary | |
7898 | register. */ | |
7d10b47d | 7899 | end_noreorder (); |
67c0d1eb | 7900 | macro_build (NULL, s, "x", zreg); |
252b5132 RH |
7901 | break; |
7902 | ||
7903 | case M_DIVU_3: | |
7904 | s = "divu"; | |
7905 | s2 = "mflo"; | |
7906 | goto do_divu3; | |
7907 | case M_REMU_3: | |
7908 | s = "divu"; | |
7909 | s2 = "mfhi"; | |
7910 | goto do_divu3; | |
7911 | case M_DDIVU_3: | |
7912 | s = "ddivu"; | |
7913 | s2 = "mflo"; | |
7914 | goto do_divu3; | |
7915 | case M_DREMU_3: | |
7916 | s = "ddivu"; | |
7917 | s2 = "mfhi"; | |
7918 | do_divu3: | |
7d10b47d | 7919 | start_noreorder (); |
67c0d1eb | 7920 | macro_build (NULL, s, "0,x,y", xreg, yreg); |
252b5132 | 7921 | expr1.X_add_number = 2; |
67c0d1eb RS |
7922 | macro_build (&expr1, "bnez", "x,p", yreg); |
7923 | macro_build (NULL, "break", "6", 7); | |
7d10b47d | 7924 | end_noreorder (); |
67c0d1eb | 7925 | macro_build (NULL, s2, "x", zreg); |
252b5132 RH |
7926 | break; |
7927 | ||
7928 | case M_DMUL: | |
7929 | dbl = 1; | |
7930 | case M_MUL: | |
67c0d1eb RS |
7931 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
7932 | macro_build (NULL, "mflo", "x", zreg); | |
8fc2e39e | 7933 | break; |
252b5132 RH |
7934 | |
7935 | case M_DSUBU_I: | |
7936 | dbl = 1; | |
7937 | goto do_subu; | |
7938 | case M_SUBU_I: | |
7939 | do_subu: | |
7940 | if (imm_expr.X_op != O_constant) | |
7941 | as_bad (_("Unsupported large constant")); | |
7942 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7943 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
7944 | break; |
7945 | ||
7946 | case M_SUBU_I_2: | |
7947 | if (imm_expr.X_op != O_constant) | |
7948 | as_bad (_("Unsupported large constant")); | |
7949 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7950 | macro_build (&imm_expr, "addiu", "x,k", xreg); |
252b5132 RH |
7951 | break; |
7952 | ||
7953 | case M_DSUBU_I_2: | |
7954 | if (imm_expr.X_op != O_constant) | |
7955 | as_bad (_("Unsupported large constant")); | |
7956 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7957 | macro_build (&imm_expr, "daddiu", "y,j", yreg); |
252b5132 RH |
7958 | break; |
7959 | ||
7960 | case M_BEQ: | |
7961 | s = "cmp"; | |
7962 | s2 = "bteqz"; | |
7963 | goto do_branch; | |
7964 | case M_BNE: | |
7965 | s = "cmp"; | |
7966 | s2 = "btnez"; | |
7967 | goto do_branch; | |
7968 | case M_BLT: | |
7969 | s = "slt"; | |
7970 | s2 = "btnez"; | |
7971 | goto do_branch; | |
7972 | case M_BLTU: | |
7973 | s = "sltu"; | |
7974 | s2 = "btnez"; | |
7975 | goto do_branch; | |
7976 | case M_BLE: | |
7977 | s = "slt"; | |
7978 | s2 = "bteqz"; | |
7979 | goto do_reverse_branch; | |
7980 | case M_BLEU: | |
7981 | s = "sltu"; | |
7982 | s2 = "bteqz"; | |
7983 | goto do_reverse_branch; | |
7984 | case M_BGE: | |
7985 | s = "slt"; | |
7986 | s2 = "bteqz"; | |
7987 | goto do_branch; | |
7988 | case M_BGEU: | |
7989 | s = "sltu"; | |
7990 | s2 = "bteqz"; | |
7991 | goto do_branch; | |
7992 | case M_BGT: | |
7993 | s = "slt"; | |
7994 | s2 = "btnez"; | |
7995 | goto do_reverse_branch; | |
7996 | case M_BGTU: | |
7997 | s = "sltu"; | |
7998 | s2 = "btnez"; | |
7999 | ||
8000 | do_reverse_branch: | |
8001 | tmp = xreg; | |
8002 | xreg = yreg; | |
8003 | yreg = tmp; | |
8004 | ||
8005 | do_branch: | |
67c0d1eb RS |
8006 | macro_build (NULL, s, "x,y", xreg, yreg); |
8007 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
8008 | break; |
8009 | ||
8010 | case M_BEQ_I: | |
8011 | s = "cmpi"; | |
8012 | s2 = "bteqz"; | |
8013 | s3 = "x,U"; | |
8014 | goto do_branch_i; | |
8015 | case M_BNE_I: | |
8016 | s = "cmpi"; | |
8017 | s2 = "btnez"; | |
8018 | s3 = "x,U"; | |
8019 | goto do_branch_i; | |
8020 | case M_BLT_I: | |
8021 | s = "slti"; | |
8022 | s2 = "btnez"; | |
8023 | s3 = "x,8"; | |
8024 | goto do_branch_i; | |
8025 | case M_BLTU_I: | |
8026 | s = "sltiu"; | |
8027 | s2 = "btnez"; | |
8028 | s3 = "x,8"; | |
8029 | goto do_branch_i; | |
8030 | case M_BLE_I: | |
8031 | s = "slti"; | |
8032 | s2 = "btnez"; | |
8033 | s3 = "x,8"; | |
8034 | goto do_addone_branch_i; | |
8035 | case M_BLEU_I: | |
8036 | s = "sltiu"; | |
8037 | s2 = "btnez"; | |
8038 | s3 = "x,8"; | |
8039 | goto do_addone_branch_i; | |
8040 | case M_BGE_I: | |
8041 | s = "slti"; | |
8042 | s2 = "bteqz"; | |
8043 | s3 = "x,8"; | |
8044 | goto do_branch_i; | |
8045 | case M_BGEU_I: | |
8046 | s = "sltiu"; | |
8047 | s2 = "bteqz"; | |
8048 | s3 = "x,8"; | |
8049 | goto do_branch_i; | |
8050 | case M_BGT_I: | |
8051 | s = "slti"; | |
8052 | s2 = "bteqz"; | |
8053 | s3 = "x,8"; | |
8054 | goto do_addone_branch_i; | |
8055 | case M_BGTU_I: | |
8056 | s = "sltiu"; | |
8057 | s2 = "bteqz"; | |
8058 | s3 = "x,8"; | |
8059 | ||
8060 | do_addone_branch_i: | |
8061 | if (imm_expr.X_op != O_constant) | |
8062 | as_bad (_("Unsupported large constant")); | |
8063 | ++imm_expr.X_add_number; | |
8064 | ||
8065 | do_branch_i: | |
67c0d1eb RS |
8066 | macro_build (&imm_expr, s, s3, xreg); |
8067 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
8068 | break; |
8069 | ||
8070 | case M_ABS: | |
8071 | expr1.X_add_number = 0; | |
67c0d1eb | 8072 | macro_build (&expr1, "slti", "x,8", yreg); |
252b5132 | 8073 | if (xreg != yreg) |
67c0d1eb | 8074 | move_register (xreg, yreg); |
252b5132 | 8075 | expr1.X_add_number = 2; |
67c0d1eb RS |
8076 | macro_build (&expr1, "bteqz", "p"); |
8077 | macro_build (NULL, "neg", "x,w", xreg, xreg); | |
252b5132 RH |
8078 | } |
8079 | } | |
8080 | ||
8081 | /* For consistency checking, verify that all bits are specified either | |
8082 | by the match/mask part of the instruction definition, or by the | |
8083 | operand list. */ | |
8084 | static int | |
17a2f251 | 8085 | validate_mips_insn (const struct mips_opcode *opc) |
252b5132 RH |
8086 | { |
8087 | const char *p = opc->args; | |
8088 | char c; | |
8089 | unsigned long used_bits = opc->mask; | |
8090 | ||
8091 | if ((used_bits & opc->match) != opc->match) | |
8092 | { | |
8093 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
8094 | opc->name, opc->args); | |
8095 | return 0; | |
8096 | } | |
8097 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
8098 | while (*p) | |
8099 | switch (c = *p++) | |
8100 | { | |
8101 | case ',': break; | |
8102 | case '(': break; | |
8103 | case ')': break; | |
af7ee8bf CD |
8104 | case '+': |
8105 | switch (c = *p++) | |
8106 | { | |
9bcd4f99 TS |
8107 | case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break; |
8108 | case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break; | |
8109 | case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break; | |
8110 | case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break; | |
af7ee8bf CD |
8111 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8112 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
8113 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
bbcc0807 CD |
8114 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); |
8115 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
5f74bc13 CD |
8116 | case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8117 | case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
8118 | case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
8119 | case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
8120 | case 'I': break; | |
ef2e4d86 CF |
8121 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; |
8122 | case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT); | |
8123 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
af7ee8bf CD |
8124 | default: |
8125 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
8126 | c, opc->name, opc->args); | |
8127 | return 0; | |
8128 | } | |
8129 | break; | |
252b5132 RH |
8130 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8131 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
8132 | case 'A': break; | |
4372b673 | 8133 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
8134 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
8135 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
8136 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8137 | case 'F': break; | |
8138 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 8139 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 8140 | case 'I': break; |
e972090a | 8141 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 8142 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
8143 | case 'L': break; |
8144 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
8145 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
8146 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
8147 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
8148 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
8149 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
8150 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8151 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
8152 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8153 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
8154 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
8155 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8156 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
8157 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
8158 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8159 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
8160 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
8161 | case 'f': break; | |
8162 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
8163 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
8164 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8165 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
8166 | case 'l': break; | |
8167 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8168 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8169 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
8170 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8171 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8172 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8173 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
8174 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8175 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8176 | case 'x': break; | |
8177 | case 'z': break; | |
8178 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
8179 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
8180 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
8181 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
8182 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
8183 | case '[': break; | |
8184 | case ']': break; | |
74cd071d CF |
8185 | case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break; |
8186 | case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break; | |
8187 | case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break; | |
8188 | case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8189 | case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break; | |
8190 | case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break; | |
8191 | case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break; | |
8192 | case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break; | |
8193 | case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break; | |
8194 | case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break; | |
8195 | case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break; | |
ef2e4d86 CF |
8196 | case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break; |
8197 | case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break; | |
8198 | case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break; | |
8199 | case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break; | |
8200 | case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
252b5132 RH |
8201 | default: |
8202 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
8203 | c, opc->name, opc->args); | |
8204 | return 0; | |
8205 | } | |
8206 | #undef USE_BITS | |
8207 | if (used_bits != 0xffffffff) | |
8208 | { | |
8209 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
8210 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
8211 | return 0; | |
8212 | } | |
8213 | return 1; | |
8214 | } | |
8215 | ||
9bcd4f99 TS |
8216 | /* UDI immediates. */ |
8217 | struct mips_immed { | |
8218 | char type; | |
8219 | unsigned int shift; | |
8220 | unsigned long mask; | |
8221 | const char * desc; | |
8222 | }; | |
8223 | ||
8224 | static const struct mips_immed mips_immed[] = { | |
8225 | { '1', OP_SH_UDI1, OP_MASK_UDI1, 0}, | |
8226 | { '2', OP_SH_UDI2, OP_MASK_UDI2, 0}, | |
8227 | { '3', OP_SH_UDI3, OP_MASK_UDI3, 0}, | |
8228 | { '4', OP_SH_UDI4, OP_MASK_UDI4, 0}, | |
8229 | { 0,0,0,0 } | |
8230 | }; | |
8231 | ||
7455baf8 TS |
8232 | /* Check whether an odd floating-point register is allowed. */ |
8233 | static int | |
8234 | mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum) | |
8235 | { | |
8236 | const char *s = insn->name; | |
8237 | ||
8238 | if (insn->pinfo == INSN_MACRO) | |
8239 | /* Let a macro pass, we'll catch it later when it is expanded. */ | |
8240 | return 1; | |
8241 | ||
8242 | if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa)) | |
8243 | { | |
8244 | /* Allow odd registers for single-precision ops. */ | |
8245 | switch (insn->pinfo & (FP_S | FP_D)) | |
8246 | { | |
8247 | case FP_S: | |
8248 | case 0: | |
8249 | return 1; /* both single precision - ok */ | |
8250 | case FP_D: | |
8251 | return 0; /* both double precision - fail */ | |
8252 | default: | |
8253 | break; | |
8254 | } | |
8255 | ||
8256 | /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ | |
8257 | s = strchr (insn->name, '.'); | |
8258 | if (argnum == 2) | |
8259 | s = s != NULL ? strchr (s + 1, '.') : NULL; | |
8260 | return (s != NULL && (s[1] == 'w' || s[1] == 's')); | |
8261 | } | |
8262 | ||
8263 | /* Single-precision coprocessor loads and moves are OK too. */ | |
8264 | if ((insn->pinfo & FP_S) | |
8265 | && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY | |
8266 | | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY))) | |
8267 | return 1; | |
8268 | ||
8269 | return 0; | |
8270 | } | |
8271 | ||
252b5132 RH |
8272 | /* This routine assembles an instruction into its binary format. As a |
8273 | side effect, it sets one of the global variables imm_reloc or | |
8274 | offset_reloc to the type of relocation to do if one of the operands | |
8275 | is an address expression. */ | |
8276 | ||
8277 | static void | |
17a2f251 | 8278 | mips_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
8279 | { |
8280 | char *s; | |
8281 | const char *args; | |
43841e91 | 8282 | char c = 0; |
252b5132 RH |
8283 | struct mips_opcode *insn; |
8284 | char *argsStart; | |
8285 | unsigned int regno; | |
8286 | unsigned int lastregno = 0; | |
af7ee8bf | 8287 | unsigned int lastpos = 0; |
071742cf | 8288 | unsigned int limlo, limhi; |
252b5132 RH |
8289 | char *s_reset; |
8290 | char save_c = 0; | |
74cd071d | 8291 | offsetT min_range, max_range; |
707bfff6 TS |
8292 | int argnum; |
8293 | unsigned int rtype; | |
252b5132 RH |
8294 | |
8295 | insn_error = NULL; | |
8296 | ||
8297 | /* If the instruction contains a '.', we first try to match an instruction | |
8298 | including the '.'. Then we try again without the '.'. */ | |
8299 | insn = NULL; | |
3882b010 | 8300 | for (s = str; *s != '\0' && !ISSPACE (*s); ++s) |
252b5132 RH |
8301 | continue; |
8302 | ||
8303 | /* If we stopped on whitespace, then replace the whitespace with null for | |
8304 | the call to hash_find. Save the character we replaced just in case we | |
8305 | have to re-parse the instruction. */ | |
3882b010 | 8306 | if (ISSPACE (*s)) |
252b5132 RH |
8307 | { |
8308 | save_c = *s; | |
8309 | *s++ = '\0'; | |
8310 | } | |
bdaaa2e1 | 8311 | |
252b5132 RH |
8312 | insn = (struct mips_opcode *) hash_find (op_hash, str); |
8313 | ||
8314 | /* If we didn't find the instruction in the opcode table, try again, but | |
8315 | this time with just the instruction up to, but not including the | |
8316 | first '.'. */ | |
8317 | if (insn == NULL) | |
8318 | { | |
bdaaa2e1 | 8319 | /* Restore the character we overwrite above (if any). */ |
252b5132 RH |
8320 | if (save_c) |
8321 | *(--s) = save_c; | |
8322 | ||
8323 | /* Scan up to the first '.' or whitespace. */ | |
3882b010 L |
8324 | for (s = str; |
8325 | *s != '\0' && *s != '.' && !ISSPACE (*s); | |
8326 | ++s) | |
252b5132 RH |
8327 | continue; |
8328 | ||
8329 | /* If we did not find a '.', then we can quit now. */ | |
8330 | if (*s != '.') | |
8331 | { | |
8332 | insn_error = "unrecognized opcode"; | |
8333 | return; | |
8334 | } | |
8335 | ||
8336 | /* Lookup the instruction in the hash table. */ | |
8337 | *s++ = '\0'; | |
8338 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
8339 | { | |
8340 | insn_error = "unrecognized opcode"; | |
8341 | return; | |
8342 | } | |
252b5132 RH |
8343 | } |
8344 | ||
8345 | argsStart = s; | |
8346 | for (;;) | |
8347 | { | |
b34976b6 | 8348 | bfd_boolean ok; |
252b5132 RH |
8349 | |
8350 | assert (strcmp (insn->name, str) == 0); | |
8351 | ||
1f25f5d3 CD |
8352 | if (OPCODE_IS_MEMBER (insn, |
8353 | (mips_opts.isa | |
9b3f89ee TS |
8354 | /* We don't check for mips_opts.mips16 here since |
8355 | we want to allow jalx if -mips16 was specified | |
8356 | on the command line. */ | |
3396de36 | 8357 | | (file_ase_mips16 ? INSN_MIPS16 : 0) |
deec1734 | 8358 | | (mips_opts.ase_mdmx ? INSN_MDMX : 0) |
74cd071d | 8359 | | (mips_opts.ase_dsp ? INSN_DSP : 0) |
65263ce3 TS |
8360 | | ((mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE) |
8361 | ? INSN_DSP64 : 0) | |
ef2e4d86 | 8362 | | (mips_opts.ase_mt ? INSN_MT : 0) |
e16bfa71 TS |
8363 | | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0) |
8364 | | (mips_opts.ase_smartmips ? INSN_SMARTMIPS : 0)), | |
fef14a42 | 8365 | mips_opts.arch)) |
b34976b6 | 8366 | ok = TRUE; |
bdaaa2e1 | 8367 | else |
b34976b6 | 8368 | ok = FALSE; |
bdaaa2e1 | 8369 | |
252b5132 RH |
8370 | if (insn->pinfo != INSN_MACRO) |
8371 | { | |
fef14a42 | 8372 | if (mips_opts.arch == CPU_R4650 && (insn->pinfo & FP_D) != 0) |
b34976b6 | 8373 | ok = FALSE; |
252b5132 RH |
8374 | } |
8375 | ||
8376 | if (! ok) | |
8377 | { | |
8378 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
8379 | && strcmp (insn->name, insn[1].name) == 0) | |
8380 | { | |
8381 | ++insn; | |
8382 | continue; | |
8383 | } | |
252b5132 | 8384 | else |
beae10d5 | 8385 | { |
268f6bed L |
8386 | if (!insn_error) |
8387 | { | |
8388 | static char buf[100]; | |
fef14a42 TS |
8389 | sprintf (buf, |
8390 | _("opcode not supported on this processor: %s (%s)"), | |
8391 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
8392 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
268f6bed L |
8393 | insn_error = buf; |
8394 | } | |
8395 | if (save_c) | |
8396 | *(--s) = save_c; | |
2bd7f1f3 | 8397 | return; |
252b5132 | 8398 | } |
252b5132 RH |
8399 | } |
8400 | ||
1e915849 | 8401 | create_insn (ip, insn); |
268f6bed | 8402 | insn_error = NULL; |
707bfff6 | 8403 | argnum = 1; |
252b5132 RH |
8404 | for (args = insn->args;; ++args) |
8405 | { | |
deec1734 CD |
8406 | int is_mdmx; |
8407 | ||
ad8d3bb3 | 8408 | s += strspn (s, " \t"); |
deec1734 | 8409 | is_mdmx = 0; |
252b5132 RH |
8410 | switch (*args) |
8411 | { | |
8412 | case '\0': /* end of args */ | |
8413 | if (*s == '\0') | |
8414 | return; | |
8415 | break; | |
8416 | ||
74cd071d CF |
8417 | case '3': /* dsp 3-bit unsigned immediate in bit 21 */ |
8418 | my_getExpression (&imm_expr, s); | |
8419 | check_absolute_expr (ip, &imm_expr); | |
8420 | if (imm_expr.X_add_number & ~OP_MASK_SA3) | |
8421 | { | |
a9e24354 TS |
8422 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8423 | OP_MASK_SA3, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8424 | } |
a9e24354 | 8425 | INSERT_OPERAND (SA3, *ip, imm_expr.X_add_number); |
74cd071d CF |
8426 | imm_expr.X_op = O_absent; |
8427 | s = expr_end; | |
8428 | continue; | |
8429 | ||
8430 | case '4': /* dsp 4-bit unsigned immediate in bit 21 */ | |
8431 | my_getExpression (&imm_expr, s); | |
8432 | check_absolute_expr (ip, &imm_expr); | |
8433 | if (imm_expr.X_add_number & ~OP_MASK_SA4) | |
8434 | { | |
a9e24354 TS |
8435 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8436 | OP_MASK_SA4, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8437 | } |
a9e24354 | 8438 | INSERT_OPERAND (SA4, *ip, imm_expr.X_add_number); |
74cd071d CF |
8439 | imm_expr.X_op = O_absent; |
8440 | s = expr_end; | |
8441 | continue; | |
8442 | ||
8443 | case '5': /* dsp 8-bit unsigned immediate in bit 16 */ | |
8444 | my_getExpression (&imm_expr, s); | |
8445 | check_absolute_expr (ip, &imm_expr); | |
8446 | if (imm_expr.X_add_number & ~OP_MASK_IMM8) | |
8447 | { | |
a9e24354 TS |
8448 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8449 | OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8450 | } |
a9e24354 | 8451 | INSERT_OPERAND (IMM8, *ip, imm_expr.X_add_number); |
74cd071d CF |
8452 | imm_expr.X_op = O_absent; |
8453 | s = expr_end; | |
8454 | continue; | |
8455 | ||
8456 | case '6': /* dsp 5-bit unsigned immediate in bit 21 */ | |
8457 | my_getExpression (&imm_expr, s); | |
8458 | check_absolute_expr (ip, &imm_expr); | |
8459 | if (imm_expr.X_add_number & ~OP_MASK_RS) | |
8460 | { | |
a9e24354 TS |
8461 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8462 | OP_MASK_RS, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8463 | } |
a9e24354 | 8464 | INSERT_OPERAND (RS, *ip, imm_expr.X_add_number); |
74cd071d CF |
8465 | imm_expr.X_op = O_absent; |
8466 | s = expr_end; | |
8467 | continue; | |
8468 | ||
8469 | case '7': /* four dsp accumulators in bits 11,12 */ | |
8470 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
8471 | s[3] >= '0' && s[3] <= '3') | |
8472 | { | |
8473 | regno = s[3] - '0'; | |
8474 | s += 4; | |
a9e24354 | 8475 | INSERT_OPERAND (DSPACC, *ip, regno); |
74cd071d CF |
8476 | continue; |
8477 | } | |
8478 | else | |
8479 | as_bad (_("Invalid dsp acc register")); | |
8480 | break; | |
8481 | ||
8482 | case '8': /* dsp 6-bit unsigned immediate in bit 11 */ | |
8483 | my_getExpression (&imm_expr, s); | |
8484 | check_absolute_expr (ip, &imm_expr); | |
8485 | if (imm_expr.X_add_number & ~OP_MASK_WRDSP) | |
8486 | { | |
a9e24354 TS |
8487 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8488 | OP_MASK_WRDSP, | |
8489 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8490 | } |
a9e24354 | 8491 | INSERT_OPERAND (WRDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
8492 | imm_expr.X_op = O_absent; |
8493 | s = expr_end; | |
8494 | continue; | |
8495 | ||
8496 | case '9': /* four dsp accumulators in bits 21,22 */ | |
8497 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
8498 | s[3] >= '0' && s[3] <= '3') | |
8499 | { | |
8500 | regno = s[3] - '0'; | |
8501 | s += 4; | |
a9e24354 | 8502 | INSERT_OPERAND (DSPACC_S, *ip, regno); |
74cd071d CF |
8503 | continue; |
8504 | } | |
8505 | else | |
8506 | as_bad (_("Invalid dsp acc register")); | |
8507 | break; | |
8508 | ||
8509 | case '0': /* dsp 6-bit signed immediate in bit 20 */ | |
8510 | my_getExpression (&imm_expr, s); | |
8511 | check_absolute_expr (ip, &imm_expr); | |
8512 | min_range = -((OP_MASK_DSPSFT + 1) >> 1); | |
8513 | max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1; | |
8514 | if (imm_expr.X_add_number < min_range || | |
8515 | imm_expr.X_add_number > max_range) | |
8516 | { | |
a9e24354 TS |
8517 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
8518 | (long) min_range, (long) max_range, | |
8519 | (long) imm_expr.X_add_number); | |
74cd071d | 8520 | } |
a9e24354 | 8521 | INSERT_OPERAND (DSPSFT, *ip, imm_expr.X_add_number); |
74cd071d CF |
8522 | imm_expr.X_op = O_absent; |
8523 | s = expr_end; | |
8524 | continue; | |
8525 | ||
8526 | case '\'': /* dsp 6-bit unsigned immediate in bit 16 */ | |
8527 | my_getExpression (&imm_expr, s); | |
8528 | check_absolute_expr (ip, &imm_expr); | |
8529 | if (imm_expr.X_add_number & ~OP_MASK_RDDSP) | |
8530 | { | |
a9e24354 TS |
8531 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8532 | OP_MASK_RDDSP, | |
8533 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8534 | } |
a9e24354 | 8535 | INSERT_OPERAND (RDDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
8536 | imm_expr.X_op = O_absent; |
8537 | s = expr_end; | |
8538 | continue; | |
8539 | ||
8540 | case ':': /* dsp 7-bit signed immediate in bit 19 */ | |
8541 | my_getExpression (&imm_expr, s); | |
8542 | check_absolute_expr (ip, &imm_expr); | |
8543 | min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1); | |
8544 | max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1; | |
8545 | if (imm_expr.X_add_number < min_range || | |
8546 | imm_expr.X_add_number > max_range) | |
8547 | { | |
a9e24354 TS |
8548 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
8549 | (long) min_range, (long) max_range, | |
8550 | (long) imm_expr.X_add_number); | |
74cd071d | 8551 | } |
a9e24354 | 8552 | INSERT_OPERAND (DSPSFT_7, *ip, imm_expr.X_add_number); |
74cd071d CF |
8553 | imm_expr.X_op = O_absent; |
8554 | s = expr_end; | |
8555 | continue; | |
8556 | ||
8557 | case '@': /* dsp 10-bit signed immediate in bit 16 */ | |
8558 | my_getExpression (&imm_expr, s); | |
8559 | check_absolute_expr (ip, &imm_expr); | |
8560 | min_range = -((OP_MASK_IMM10 + 1) >> 1); | |
8561 | max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1; | |
8562 | if (imm_expr.X_add_number < min_range || | |
8563 | imm_expr.X_add_number > max_range) | |
8564 | { | |
a9e24354 TS |
8565 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
8566 | (long) min_range, (long) max_range, | |
8567 | (long) imm_expr.X_add_number); | |
74cd071d | 8568 | } |
a9e24354 | 8569 | INSERT_OPERAND (IMM10, *ip, imm_expr.X_add_number); |
74cd071d CF |
8570 | imm_expr.X_op = O_absent; |
8571 | s = expr_end; | |
8572 | continue; | |
8573 | ||
a9e24354 | 8574 | case '!': /* MT usermode flag bit. */ |
ef2e4d86 CF |
8575 | my_getExpression (&imm_expr, s); |
8576 | check_absolute_expr (ip, &imm_expr); | |
8577 | if (imm_expr.X_add_number & ~OP_MASK_MT_U) | |
a9e24354 TS |
8578 | as_bad (_("MT usermode bit not 0 or 1 (%lu)"), |
8579 | (unsigned long) imm_expr.X_add_number); | |
8580 | INSERT_OPERAND (MT_U, *ip, imm_expr.X_add_number); | |
ef2e4d86 CF |
8581 | imm_expr.X_op = O_absent; |
8582 | s = expr_end; | |
8583 | continue; | |
8584 | ||
a9e24354 | 8585 | case '$': /* MT load high flag bit. */ |
ef2e4d86 CF |
8586 | my_getExpression (&imm_expr, s); |
8587 | check_absolute_expr (ip, &imm_expr); | |
8588 | if (imm_expr.X_add_number & ~OP_MASK_MT_H) | |
a9e24354 TS |
8589 | as_bad (_("MT load high bit not 0 or 1 (%lu)"), |
8590 | (unsigned long) imm_expr.X_add_number); | |
8591 | INSERT_OPERAND (MT_H, *ip, imm_expr.X_add_number); | |
ef2e4d86 CF |
8592 | imm_expr.X_op = O_absent; |
8593 | s = expr_end; | |
8594 | continue; | |
8595 | ||
8596 | case '*': /* four dsp accumulators in bits 18,19 */ | |
8597 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
8598 | s[3] >= '0' && s[3] <= '3') | |
8599 | { | |
8600 | regno = s[3] - '0'; | |
8601 | s += 4; | |
a9e24354 | 8602 | INSERT_OPERAND (MTACC_T, *ip, regno); |
ef2e4d86 CF |
8603 | continue; |
8604 | } | |
8605 | else | |
8606 | as_bad (_("Invalid dsp/smartmips acc register")); | |
8607 | break; | |
8608 | ||
8609 | case '&': /* four dsp accumulators in bits 13,14 */ | |
8610 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
8611 | s[3] >= '0' && s[3] <= '3') | |
8612 | { | |
8613 | regno = s[3] - '0'; | |
8614 | s += 4; | |
a9e24354 | 8615 | INSERT_OPERAND (MTACC_D, *ip, regno); |
ef2e4d86 CF |
8616 | continue; |
8617 | } | |
8618 | else | |
8619 | as_bad (_("Invalid dsp/smartmips acc register")); | |
8620 | break; | |
8621 | ||
252b5132 RH |
8622 | case ',': |
8623 | if (*s++ == *args) | |
8624 | continue; | |
8625 | s--; | |
8626 | switch (*++args) | |
8627 | { | |
8628 | case 'r': | |
8629 | case 'v': | |
bf12938e | 8630 | INSERT_OPERAND (RS, *ip, lastregno); |
252b5132 RH |
8631 | continue; |
8632 | ||
8633 | case 'w': | |
bf12938e | 8634 | INSERT_OPERAND (RT, *ip, lastregno); |
38487616 TS |
8635 | continue; |
8636 | ||
252b5132 | 8637 | case 'W': |
bf12938e | 8638 | INSERT_OPERAND (FT, *ip, lastregno); |
252b5132 RH |
8639 | continue; |
8640 | ||
8641 | case 'V': | |
bf12938e | 8642 | INSERT_OPERAND (FS, *ip, lastregno); |
252b5132 RH |
8643 | continue; |
8644 | } | |
8645 | break; | |
8646 | ||
8647 | case '(': | |
8648 | /* Handle optional base register. | |
8649 | Either the base register is omitted or | |
bdaaa2e1 | 8650 | we must have a left paren. */ |
252b5132 RH |
8651 | /* This is dependent on the next operand specifier |
8652 | is a base register specification. */ | |
8653 | assert (args[1] == 'b' || args[1] == '5' | |
8654 | || args[1] == '-' || args[1] == '4'); | |
8655 | if (*s == '\0') | |
8656 | return; | |
8657 | ||
8658 | case ')': /* these must match exactly */ | |
60b63b72 RS |
8659 | case '[': |
8660 | case ']': | |
252b5132 RH |
8661 | if (*s++ == *args) |
8662 | continue; | |
8663 | break; | |
8664 | ||
af7ee8bf CD |
8665 | case '+': /* Opcode extension character. */ |
8666 | switch (*++args) | |
8667 | { | |
9bcd4f99 TS |
8668 | case '1': /* UDI immediates. */ |
8669 | case '2': | |
8670 | case '3': | |
8671 | case '4': | |
8672 | { | |
8673 | const struct mips_immed *imm = mips_immed; | |
8674 | ||
8675 | while (imm->type && imm->type != *args) | |
8676 | ++imm; | |
8677 | if (! imm->type) | |
8678 | internalError (); | |
8679 | my_getExpression (&imm_expr, s); | |
8680 | check_absolute_expr (ip, &imm_expr); | |
8681 | if ((unsigned long) imm_expr.X_add_number & ~imm->mask) | |
8682 | { | |
8683 | as_warn (_("Illegal %s number (%lu, 0x%lx)"), | |
8684 | imm->desc ? imm->desc : ip->insn_mo->name, | |
8685 | (unsigned long) imm_expr.X_add_number, | |
8686 | (unsigned long) imm_expr.X_add_number); | |
8687 | imm_expr.X_add_number &= imm->mask; | |
8688 | } | |
8689 | ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number | |
8690 | << imm->shift); | |
8691 | imm_expr.X_op = O_absent; | |
8692 | s = expr_end; | |
8693 | } | |
8694 | continue; | |
8695 | ||
071742cf CD |
8696 | case 'A': /* ins/ext position, becomes LSB. */ |
8697 | limlo = 0; | |
8698 | limhi = 31; | |
5f74bc13 CD |
8699 | goto do_lsb; |
8700 | case 'E': | |
8701 | limlo = 32; | |
8702 | limhi = 63; | |
8703 | goto do_lsb; | |
8704 | do_lsb: | |
071742cf CD |
8705 | my_getExpression (&imm_expr, s); |
8706 | check_absolute_expr (ip, &imm_expr); | |
8707 | if ((unsigned long) imm_expr.X_add_number < limlo | |
8708 | || (unsigned long) imm_expr.X_add_number > limhi) | |
8709 | { | |
8710 | as_bad (_("Improper position (%lu)"), | |
8711 | (unsigned long) imm_expr.X_add_number); | |
8712 | imm_expr.X_add_number = limlo; | |
8713 | } | |
8714 | lastpos = imm_expr.X_add_number; | |
bf12938e | 8715 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); |
071742cf CD |
8716 | imm_expr.X_op = O_absent; |
8717 | s = expr_end; | |
8718 | continue; | |
8719 | ||
8720 | case 'B': /* ins size, becomes MSB. */ | |
8721 | limlo = 1; | |
8722 | limhi = 32; | |
5f74bc13 CD |
8723 | goto do_msb; |
8724 | case 'F': | |
8725 | limlo = 33; | |
8726 | limhi = 64; | |
8727 | goto do_msb; | |
8728 | do_msb: | |
071742cf CD |
8729 | my_getExpression (&imm_expr, s); |
8730 | check_absolute_expr (ip, &imm_expr); | |
8731 | /* Check for negative input so that small negative numbers | |
8732 | will not succeed incorrectly. The checks against | |
8733 | (pos+size) transitively check "size" itself, | |
8734 | assuming that "pos" is reasonable. */ | |
8735 | if ((long) imm_expr.X_add_number < 0 | |
8736 | || ((unsigned long) imm_expr.X_add_number | |
8737 | + lastpos) < limlo | |
8738 | || ((unsigned long) imm_expr.X_add_number | |
8739 | + lastpos) > limhi) | |
8740 | { | |
8741 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
8742 | (unsigned long) imm_expr.X_add_number, | |
8743 | (unsigned long) lastpos); | |
8744 | imm_expr.X_add_number = limlo - lastpos; | |
8745 | } | |
bf12938e RS |
8746 | INSERT_OPERAND (INSMSB, *ip, |
8747 | lastpos + imm_expr.X_add_number - 1); | |
071742cf CD |
8748 | imm_expr.X_op = O_absent; |
8749 | s = expr_end; | |
8750 | continue; | |
8751 | ||
8752 | case 'C': /* ext size, becomes MSBD. */ | |
8753 | limlo = 1; | |
8754 | limhi = 32; | |
5f74bc13 CD |
8755 | goto do_msbd; |
8756 | case 'G': | |
8757 | limlo = 33; | |
8758 | limhi = 64; | |
8759 | goto do_msbd; | |
8760 | case 'H': | |
8761 | limlo = 33; | |
8762 | limhi = 64; | |
8763 | goto do_msbd; | |
8764 | do_msbd: | |
071742cf CD |
8765 | my_getExpression (&imm_expr, s); |
8766 | check_absolute_expr (ip, &imm_expr); | |
8767 | /* Check for negative input so that small negative numbers | |
8768 | will not succeed incorrectly. The checks against | |
8769 | (pos+size) transitively check "size" itself, | |
8770 | assuming that "pos" is reasonable. */ | |
8771 | if ((long) imm_expr.X_add_number < 0 | |
8772 | || ((unsigned long) imm_expr.X_add_number | |
8773 | + lastpos) < limlo | |
8774 | || ((unsigned long) imm_expr.X_add_number | |
8775 | + lastpos) > limhi) | |
8776 | { | |
8777 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
8778 | (unsigned long) imm_expr.X_add_number, | |
8779 | (unsigned long) lastpos); | |
8780 | imm_expr.X_add_number = limlo - lastpos; | |
8781 | } | |
bf12938e | 8782 | INSERT_OPERAND (EXTMSBD, *ip, imm_expr.X_add_number - 1); |
071742cf CD |
8783 | imm_expr.X_op = O_absent; |
8784 | s = expr_end; | |
8785 | continue; | |
af7ee8bf | 8786 | |
bbcc0807 CD |
8787 | case 'D': |
8788 | /* +D is for disassembly only; never match. */ | |
8789 | break; | |
8790 | ||
5f74bc13 CD |
8791 | case 'I': |
8792 | /* "+I" is like "I", except that imm2_expr is used. */ | |
8793 | my_getExpression (&imm2_expr, s); | |
8794 | if (imm2_expr.X_op != O_big | |
8795 | && imm2_expr.X_op != O_constant) | |
8796 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
8797 | if (HAVE_32BIT_GPRS) |
8798 | normalize_constant_expr (&imm2_expr); | |
5f74bc13 CD |
8799 | s = expr_end; |
8800 | continue; | |
8801 | ||
707bfff6 | 8802 | case 'T': /* Coprocessor register. */ |
ef2e4d86 CF |
8803 | /* +T is for disassembly only; never match. */ |
8804 | break; | |
8805 | ||
707bfff6 | 8806 | case 't': /* Coprocessor register number. */ |
ef2e4d86 CF |
8807 | if (s[0] == '$' && ISDIGIT (s[1])) |
8808 | { | |
8809 | ++s; | |
8810 | regno = 0; | |
8811 | do | |
8812 | { | |
8813 | regno *= 10; | |
8814 | regno += *s - '0'; | |
8815 | ++s; | |
8816 | } | |
8817 | while (ISDIGIT (*s)); | |
8818 | if (regno > 31) | |
8819 | as_bad (_("Invalid register number (%d)"), regno); | |
8820 | else | |
8821 | { | |
a9e24354 | 8822 | INSERT_OPERAND (RT, *ip, regno); |
ef2e4d86 CF |
8823 | continue; |
8824 | } | |
8825 | } | |
8826 | else | |
8827 | as_bad (_("Invalid coprocessor 0 register number")); | |
8828 | break; | |
8829 | ||
af7ee8bf CD |
8830 | default: |
8831 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
8832 | *args, insn->name, insn->args); | |
8833 | /* Further processing is fruitless. */ | |
8834 | return; | |
8835 | } | |
8836 | break; | |
8837 | ||
252b5132 RH |
8838 | case '<': /* must be at least one digit */ |
8839 | /* | |
8840 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
8841 | * than 31 or less than 0, then the shift amount should be |
8842 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
8843 | * We issue a warning and mask out all but the low 5 bits. |
8844 | */ | |
8845 | my_getExpression (&imm_expr, s); | |
8846 | check_absolute_expr (ip, &imm_expr); | |
8847 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
8848 | as_warn (_("Improper shift amount (%lu)"), |
8849 | (unsigned long) imm_expr.X_add_number); | |
8850 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); | |
252b5132 RH |
8851 | imm_expr.X_op = O_absent; |
8852 | s = expr_end; | |
8853 | continue; | |
8854 | ||
8855 | case '>': /* shift amount minus 32 */ | |
8856 | my_getExpression (&imm_expr, s); | |
8857 | check_absolute_expr (ip, &imm_expr); | |
8858 | if ((unsigned long) imm_expr.X_add_number < 32 | |
8859 | || (unsigned long) imm_expr.X_add_number > 63) | |
8860 | break; | |
bf12938e | 8861 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number - 32); |
252b5132 RH |
8862 | imm_expr.X_op = O_absent; |
8863 | s = expr_end; | |
8864 | continue; | |
8865 | ||
252b5132 RH |
8866 | case 'k': /* cache code */ |
8867 | case 'h': /* prefx code */ | |
8868 | my_getExpression (&imm_expr, s); | |
8869 | check_absolute_expr (ip, &imm_expr); | |
8870 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
8871 | as_warn (_("Invalid value for `%s' (%lu)"), |
8872 | ip->insn_mo->name, | |
8873 | (unsigned long) imm_expr.X_add_number); | |
252b5132 | 8874 | if (*args == 'k') |
bf12938e | 8875 | INSERT_OPERAND (CACHE, *ip, imm_expr.X_add_number); |
252b5132 | 8876 | else |
bf12938e | 8877 | INSERT_OPERAND (PREFX, *ip, imm_expr.X_add_number); |
252b5132 RH |
8878 | imm_expr.X_op = O_absent; |
8879 | s = expr_end; | |
8880 | continue; | |
8881 | ||
8882 | case 'c': /* break code */ | |
8883 | my_getExpression (&imm_expr, s); | |
8884 | check_absolute_expr (ip, &imm_expr); | |
a9e24354 TS |
8885 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE) |
8886 | as_warn (_("Code for %s not in range 0..1023 (%lu)"), | |
8887 | ip->insn_mo->name, | |
bf12938e RS |
8888 | (unsigned long) imm_expr.X_add_number); |
8889 | INSERT_OPERAND (CODE, *ip, imm_expr.X_add_number); | |
252b5132 RH |
8890 | imm_expr.X_op = O_absent; |
8891 | s = expr_end; | |
8892 | continue; | |
8893 | ||
8894 | case 'q': /* lower break code */ | |
8895 | my_getExpression (&imm_expr, s); | |
8896 | check_absolute_expr (ip, &imm_expr); | |
a9e24354 TS |
8897 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE2) |
8898 | as_warn (_("Lower code for %s not in range 0..1023 (%lu)"), | |
8899 | ip->insn_mo->name, | |
bf12938e RS |
8900 | (unsigned long) imm_expr.X_add_number); |
8901 | INSERT_OPERAND (CODE2, *ip, imm_expr.X_add_number); | |
252b5132 RH |
8902 | imm_expr.X_op = O_absent; |
8903 | s = expr_end; | |
8904 | continue; | |
8905 | ||
4372b673 | 8906 | case 'B': /* 20-bit syscall/break code. */ |
156c2f8b | 8907 | my_getExpression (&imm_expr, s); |
156c2f8b | 8908 | check_absolute_expr (ip, &imm_expr); |
793b27f4 | 8909 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20) |
a9e24354 TS |
8910 | as_warn (_("Code for %s not in range 0..1048575 (%lu)"), |
8911 | ip->insn_mo->name, | |
793b27f4 | 8912 | (unsigned long) imm_expr.X_add_number); |
bf12938e | 8913 | INSERT_OPERAND (CODE20, *ip, imm_expr.X_add_number); |
252b5132 RH |
8914 | imm_expr.X_op = O_absent; |
8915 | s = expr_end; | |
8916 | continue; | |
8917 | ||
98d3f06f | 8918 | case 'C': /* Coprocessor code */ |
beae10d5 | 8919 | my_getExpression (&imm_expr, s); |
252b5132 | 8920 | check_absolute_expr (ip, &imm_expr); |
a9e24354 | 8921 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_COPZ) |
252b5132 | 8922 | { |
793b27f4 TS |
8923 | as_warn (_("Coproccesor code > 25 bits (%lu)"), |
8924 | (unsigned long) imm_expr.X_add_number); | |
a9e24354 | 8925 | imm_expr.X_add_number &= OP_MASK_COPZ; |
252b5132 | 8926 | } |
a9e24354 | 8927 | INSERT_OPERAND (COPZ, *ip, imm_expr.X_add_number); |
beae10d5 KH |
8928 | imm_expr.X_op = O_absent; |
8929 | s = expr_end; | |
8930 | continue; | |
252b5132 | 8931 | |
4372b673 NC |
8932 | case 'J': /* 19-bit wait code. */ |
8933 | my_getExpression (&imm_expr, s); | |
8934 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 8935 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
a9e24354 TS |
8936 | { |
8937 | as_warn (_("Illegal 19-bit code (%lu)"), | |
8938 | (unsigned long) imm_expr.X_add_number); | |
8939 | imm_expr.X_add_number &= OP_MASK_CODE19; | |
8940 | } | |
bf12938e | 8941 | INSERT_OPERAND (CODE19, *ip, imm_expr.X_add_number); |
4372b673 NC |
8942 | imm_expr.X_op = O_absent; |
8943 | s = expr_end; | |
8944 | continue; | |
8945 | ||
707bfff6 | 8946 | case 'P': /* Performance register. */ |
beae10d5 | 8947 | my_getExpression (&imm_expr, s); |
252b5132 | 8948 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 8949 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
bf12938e RS |
8950 | as_warn (_("Invalid performance register (%lu)"), |
8951 | (unsigned long) imm_expr.X_add_number); | |
8952 | INSERT_OPERAND (PERFREG, *ip, imm_expr.X_add_number); | |
beae10d5 KH |
8953 | imm_expr.X_op = O_absent; |
8954 | s = expr_end; | |
8955 | continue; | |
252b5132 | 8956 | |
707bfff6 TS |
8957 | case 'G': /* Coprocessor destination register. */ |
8958 | if (((ip->insn_opcode >> OP_SH_OP) & OP_MASK_OP) == OP_OP_COP0) | |
8959 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_CP0, ®no); | |
8960 | else | |
8961 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
a9e24354 | 8962 | INSERT_OPERAND (RD, *ip, regno); |
707bfff6 TS |
8963 | if (ok) |
8964 | { | |
8965 | lastregno = regno; | |
8966 | continue; | |
8967 | } | |
8968 | else | |
8969 | break; | |
8970 | ||
252b5132 RH |
8971 | case 'b': /* base register */ |
8972 | case 'd': /* destination register */ | |
8973 | case 's': /* source register */ | |
8974 | case 't': /* target register */ | |
8975 | case 'r': /* both target and source */ | |
8976 | case 'v': /* both dest and source */ | |
8977 | case 'w': /* both dest and target */ | |
8978 | case 'E': /* coprocessor target register */ | |
af7ee8bf | 8979 | case 'K': /* 'rdhwr' destination register */ |
252b5132 RH |
8980 | case 'x': /* ignore register name */ |
8981 | case 'z': /* must be zero register */ | |
4372b673 | 8982 | case 'U': /* destination register (clo/clz). */ |
ef2e4d86 | 8983 | case 'g': /* coprocessor destination register */ |
707bfff6 TS |
8984 | s_reset = s; |
8985 | if (*args == 'E' || *args == 'K') | |
8986 | ok = reg_lookup (&s, RTYPE_NUM, ®no); | |
8987 | else | |
8988 | { | |
8989 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
8990 | if (regno == AT && ! mips_opts.noat) | |
8991 | as_warn ("Used $at without \".set noat\""); | |
8992 | } | |
8993 | if (ok) | |
252b5132 | 8994 | { |
252b5132 RH |
8995 | c = *args; |
8996 | if (*s == ' ') | |
f9419b05 | 8997 | ++s; |
252b5132 RH |
8998 | if (args[1] != *s) |
8999 | { | |
9000 | if (c == 'r' || c == 'v' || c == 'w') | |
9001 | { | |
9002 | regno = lastregno; | |
9003 | s = s_reset; | |
f9419b05 | 9004 | ++args; |
252b5132 RH |
9005 | } |
9006 | } | |
9007 | /* 'z' only matches $0. */ | |
9008 | if (c == 'z' && regno != 0) | |
9009 | break; | |
9010 | ||
bdaaa2e1 KH |
9011 | /* Now that we have assembled one operand, we use the args string |
9012 | * to figure out where it goes in the instruction. */ | |
252b5132 RH |
9013 | switch (c) |
9014 | { | |
9015 | case 'r': | |
9016 | case 's': | |
9017 | case 'v': | |
9018 | case 'b': | |
bf12938e | 9019 | INSERT_OPERAND (RS, *ip, regno); |
252b5132 RH |
9020 | break; |
9021 | case 'd': | |
9022 | case 'G': | |
af7ee8bf | 9023 | case 'K': |
ef2e4d86 | 9024 | case 'g': |
bf12938e | 9025 | INSERT_OPERAND (RD, *ip, regno); |
252b5132 | 9026 | break; |
4372b673 | 9027 | case 'U': |
bf12938e RS |
9028 | INSERT_OPERAND (RD, *ip, regno); |
9029 | INSERT_OPERAND (RT, *ip, regno); | |
4372b673 | 9030 | break; |
252b5132 RH |
9031 | case 'w': |
9032 | case 't': | |
9033 | case 'E': | |
bf12938e | 9034 | INSERT_OPERAND (RT, *ip, regno); |
252b5132 RH |
9035 | break; |
9036 | case 'x': | |
9037 | /* This case exists because on the r3000 trunc | |
9038 | expands into a macro which requires a gp | |
9039 | register. On the r6000 or r4000 it is | |
9040 | assembled into a single instruction which | |
9041 | ignores the register. Thus the insn version | |
9042 | is MIPS_ISA2 and uses 'x', and the macro | |
9043 | version is MIPS_ISA1 and uses 't'. */ | |
9044 | break; | |
9045 | case 'z': | |
9046 | /* This case is for the div instruction, which | |
9047 | acts differently if the destination argument | |
9048 | is $0. This only matches $0, and is checked | |
9049 | outside the switch. */ | |
9050 | break; | |
9051 | case 'D': | |
9052 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
9053 | break; | |
9054 | /* What about all other operands like 'i', which | |
9055 | can be specified in the opcode table? */ | |
9056 | } | |
9057 | lastregno = regno; | |
9058 | continue; | |
9059 | } | |
252b5132 RH |
9060 | switch (*args++) |
9061 | { | |
9062 | case 'r': | |
9063 | case 'v': | |
bf12938e | 9064 | INSERT_OPERAND (RS, *ip, lastregno); |
252b5132 RH |
9065 | continue; |
9066 | case 'w': | |
bf12938e | 9067 | INSERT_OPERAND (RT, *ip, lastregno); |
252b5132 RH |
9068 | continue; |
9069 | } | |
9070 | break; | |
9071 | ||
deec1734 CD |
9072 | case 'O': /* MDMX alignment immediate constant. */ |
9073 | my_getExpression (&imm_expr, s); | |
9074 | check_absolute_expr (ip, &imm_expr); | |
9075 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
bf12938e RS |
9076 | as_warn ("Improper align amount (%ld), using low bits", |
9077 | (long) imm_expr.X_add_number); | |
9078 | INSERT_OPERAND (ALN, *ip, imm_expr.X_add_number); | |
deec1734 CD |
9079 | imm_expr.X_op = O_absent; |
9080 | s = expr_end; | |
9081 | continue; | |
9082 | ||
9083 | case 'Q': /* MDMX vector, element sel, or const. */ | |
9084 | if (s[0] != '$') | |
9085 | { | |
9086 | /* MDMX Immediate. */ | |
9087 | my_getExpression (&imm_expr, s); | |
9088 | check_absolute_expr (ip, &imm_expr); | |
9089 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
bf12938e RS |
9090 | as_warn (_("Invalid MDMX Immediate (%ld)"), |
9091 | (long) imm_expr.X_add_number); | |
9092 | INSERT_OPERAND (FT, *ip, imm_expr.X_add_number); | |
deec1734 CD |
9093 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) |
9094 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
9095 | else | |
9096 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
deec1734 CD |
9097 | imm_expr.X_op = O_absent; |
9098 | s = expr_end; | |
9099 | continue; | |
9100 | } | |
9101 | /* Not MDMX Immediate. Fall through. */ | |
9102 | case 'X': /* MDMX destination register. */ | |
9103 | case 'Y': /* MDMX source register. */ | |
9104 | case 'Z': /* MDMX target register. */ | |
9105 | is_mdmx = 1; | |
252b5132 RH |
9106 | case 'D': /* floating point destination register */ |
9107 | case 'S': /* floating point source register */ | |
9108 | case 'T': /* floating point target register */ | |
9109 | case 'R': /* floating point source register */ | |
9110 | case 'V': | |
9111 | case 'W': | |
707bfff6 TS |
9112 | rtype = RTYPE_FPU; |
9113 | if (is_mdmx | |
9114 | || (mips_opts.ase_mdmx | |
9115 | && (ip->insn_mo->pinfo & FP_D) | |
9116 | && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY | |
9117 | | INSN_COPROC_MEMORY_DELAY | |
9118 | | INSN_LOAD_COPROC_DELAY | |
9119 | | INSN_LOAD_MEMORY_DELAY | |
9120 | | INSN_STORE_MEMORY)))) | |
9121 | rtype |= RTYPE_VEC; | |
252b5132 | 9122 | s_reset = s; |
707bfff6 | 9123 | if (reg_lookup (&s, rtype, ®no)) |
252b5132 | 9124 | { |
252b5132 | 9125 | if ((regno & 1) != 0 |
ca4e0257 | 9126 | && HAVE_32BIT_FPRS |
7455baf8 | 9127 | && ! mips_oddfpreg_ok (ip->insn_mo, argnum)) |
252b5132 RH |
9128 | as_warn (_("Float register should be even, was %d"), |
9129 | regno); | |
9130 | ||
9131 | c = *args; | |
9132 | if (*s == ' ') | |
f9419b05 | 9133 | ++s; |
252b5132 RH |
9134 | if (args[1] != *s) |
9135 | { | |
9136 | if (c == 'V' || c == 'W') | |
9137 | { | |
9138 | regno = lastregno; | |
9139 | s = s_reset; | |
f9419b05 | 9140 | ++args; |
252b5132 RH |
9141 | } |
9142 | } | |
9143 | switch (c) | |
9144 | { | |
9145 | case 'D': | |
deec1734 | 9146 | case 'X': |
bf12938e | 9147 | INSERT_OPERAND (FD, *ip, regno); |
252b5132 RH |
9148 | break; |
9149 | case 'V': | |
9150 | case 'S': | |
deec1734 | 9151 | case 'Y': |
bf12938e | 9152 | INSERT_OPERAND (FS, *ip, regno); |
252b5132 | 9153 | break; |
deec1734 CD |
9154 | case 'Q': |
9155 | /* This is like 'Z', but also needs to fix the MDMX | |
9156 | vector/scalar select bits. Note that the | |
9157 | scalar immediate case is handled above. */ | |
9158 | if (*s == '[') | |
9159 | { | |
9160 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
9161 | int max_el = (is_qh ? 3 : 7); | |
9162 | s++; | |
9163 | my_getExpression(&imm_expr, s); | |
9164 | check_absolute_expr (ip, &imm_expr); | |
9165 | s = expr_end; | |
9166 | if (imm_expr.X_add_number > max_el) | |
9167 | as_bad(_("Bad element selector %ld"), | |
9168 | (long) imm_expr.X_add_number); | |
9169 | imm_expr.X_add_number &= max_el; | |
9170 | ip->insn_opcode |= (imm_expr.X_add_number | |
9171 | << (OP_SH_VSEL + | |
9172 | (is_qh ? 2 : 1))); | |
01a3f561 | 9173 | imm_expr.X_op = O_absent; |
deec1734 CD |
9174 | if (*s != ']') |
9175 | as_warn(_("Expecting ']' found '%s'"), s); | |
9176 | else | |
9177 | s++; | |
9178 | } | |
9179 | else | |
9180 | { | |
9181 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
9182 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
9183 | << OP_SH_VSEL); | |
9184 | else | |
9185 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
9186 | OP_SH_VSEL); | |
9187 | } | |
9188 | /* Fall through */ | |
252b5132 RH |
9189 | case 'W': |
9190 | case 'T': | |
deec1734 | 9191 | case 'Z': |
bf12938e | 9192 | INSERT_OPERAND (FT, *ip, regno); |
252b5132 RH |
9193 | break; |
9194 | case 'R': | |
bf12938e | 9195 | INSERT_OPERAND (FR, *ip, regno); |
252b5132 RH |
9196 | break; |
9197 | } | |
9198 | lastregno = regno; | |
9199 | continue; | |
9200 | } | |
9201 | ||
252b5132 RH |
9202 | switch (*args++) |
9203 | { | |
9204 | case 'V': | |
bf12938e | 9205 | INSERT_OPERAND (FS, *ip, lastregno); |
252b5132 RH |
9206 | continue; |
9207 | case 'W': | |
bf12938e | 9208 | INSERT_OPERAND (FT, *ip, lastregno); |
252b5132 RH |
9209 | continue; |
9210 | } | |
9211 | break; | |
9212 | ||
9213 | case 'I': | |
9214 | my_getExpression (&imm_expr, s); | |
9215 | if (imm_expr.X_op != O_big | |
9216 | && imm_expr.X_op != O_constant) | |
9217 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
9218 | if (HAVE_32BIT_GPRS) |
9219 | normalize_constant_expr (&imm_expr); | |
252b5132 RH |
9220 | s = expr_end; |
9221 | continue; | |
9222 | ||
9223 | case 'A': | |
9224 | my_getExpression (&offset_expr, s); | |
2051e8c4 | 9225 | normalize_address_expr (&offset_expr); |
f6688943 | 9226 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
9227 | s = expr_end; |
9228 | continue; | |
9229 | ||
9230 | case 'F': | |
9231 | case 'L': | |
9232 | case 'f': | |
9233 | case 'l': | |
9234 | { | |
9235 | int f64; | |
ca4e0257 | 9236 | int using_gprs; |
252b5132 RH |
9237 | char *save_in; |
9238 | char *err; | |
9239 | unsigned char temp[8]; | |
9240 | int len; | |
9241 | unsigned int length; | |
9242 | segT seg; | |
9243 | subsegT subseg; | |
9244 | char *p; | |
9245 | ||
9246 | /* These only appear as the last operand in an | |
9247 | instruction, and every instruction that accepts | |
9248 | them in any variant accepts them in all variants. | |
9249 | This means we don't have to worry about backing out | |
9250 | any changes if the instruction does not match. | |
9251 | ||
9252 | The difference between them is the size of the | |
9253 | floating point constant and where it goes. For 'F' | |
9254 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
9255 | is 32 bits. Where the constant is placed is based | |
9256 | on how the MIPS assembler does things: | |
9257 | F -- .rdata | |
9258 | L -- .lit8 | |
9259 | f -- immediate value | |
9260 | l -- .lit4 | |
9261 | ||
9262 | The .lit4 and .lit8 sections are only used if | |
9263 | permitted by the -G argument. | |
9264 | ||
ca4e0257 RS |
9265 | The code below needs to know whether the target register |
9266 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
9267 | 'F' are used with GPR-based instructions and 'l' and | |
9268 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
9269 | |
9270 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 9271 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
9272 | |
9273 | save_in = input_line_pointer; | |
9274 | input_line_pointer = s; | |
9275 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
9276 | length = len; | |
9277 | s = input_line_pointer; | |
9278 | input_line_pointer = save_in; | |
9279 | if (err != NULL && *err != '\0') | |
9280 | { | |
9281 | as_bad (_("Bad floating point constant: %s"), err); | |
9282 | memset (temp, '\0', sizeof temp); | |
9283 | length = f64 ? 8 : 4; | |
9284 | } | |
9285 | ||
156c2f8b | 9286 | assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
9287 | |
9288 | if (*args == 'f' | |
9289 | || (*args == 'l' | |
3e722fb5 | 9290 | && (g_switch_value < 4 |
252b5132 RH |
9291 | || (temp[0] == 0 && temp[1] == 0) |
9292 | || (temp[2] == 0 && temp[3] == 0)))) | |
9293 | { | |
9294 | imm_expr.X_op = O_constant; | |
9295 | if (! target_big_endian) | |
9296 | imm_expr.X_add_number = bfd_getl32 (temp); | |
9297 | else | |
9298 | imm_expr.X_add_number = bfd_getb32 (temp); | |
9299 | } | |
9300 | else if (length > 4 | |
119d663a | 9301 | && ! mips_disable_float_construction |
ca4e0257 RS |
9302 | /* Constants can only be constructed in GPRs and |
9303 | copied to FPRs if the GPRs are at least as wide | |
9304 | as the FPRs. Force the constant into memory if | |
9305 | we are using 64-bit FPRs but the GPRs are only | |
9306 | 32 bits wide. */ | |
9307 | && (using_gprs | |
9308 | || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) | |
252b5132 RH |
9309 | && ((temp[0] == 0 && temp[1] == 0) |
9310 | || (temp[2] == 0 && temp[3] == 0)) | |
9311 | && ((temp[4] == 0 && temp[5] == 0) | |
9312 | || (temp[6] == 0 && temp[7] == 0))) | |
9313 | { | |
ca4e0257 RS |
9314 | /* The value is simple enough to load with a couple of |
9315 | instructions. If using 32-bit registers, set | |
9316 | imm_expr to the high order 32 bits and offset_expr to | |
9317 | the low order 32 bits. Otherwise, set imm_expr to | |
9318 | the entire 64 bit constant. */ | |
9319 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) | |
252b5132 RH |
9320 | { |
9321 | imm_expr.X_op = O_constant; | |
9322 | offset_expr.X_op = O_constant; | |
9323 | if (! target_big_endian) | |
9324 | { | |
9325 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
9326 | offset_expr.X_add_number = bfd_getl32 (temp); | |
9327 | } | |
9328 | else | |
9329 | { | |
9330 | imm_expr.X_add_number = bfd_getb32 (temp); | |
9331 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
9332 | } | |
9333 | if (offset_expr.X_add_number == 0) | |
9334 | offset_expr.X_op = O_absent; | |
9335 | } | |
9336 | else if (sizeof (imm_expr.X_add_number) > 4) | |
9337 | { | |
9338 | imm_expr.X_op = O_constant; | |
9339 | if (! target_big_endian) | |
9340 | imm_expr.X_add_number = bfd_getl64 (temp); | |
9341 | else | |
9342 | imm_expr.X_add_number = bfd_getb64 (temp); | |
9343 | } | |
9344 | else | |
9345 | { | |
9346 | imm_expr.X_op = O_big; | |
9347 | imm_expr.X_add_number = 4; | |
9348 | if (! target_big_endian) | |
9349 | { | |
9350 | generic_bignum[0] = bfd_getl16 (temp); | |
9351 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
9352 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
9353 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
9354 | } | |
9355 | else | |
9356 | { | |
9357 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
9358 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
9359 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
9360 | generic_bignum[3] = bfd_getb16 (temp); | |
9361 | } | |
9362 | } | |
9363 | } | |
9364 | else | |
9365 | { | |
9366 | const char *newname; | |
9367 | segT new_seg; | |
9368 | ||
9369 | /* Switch to the right section. */ | |
9370 | seg = now_seg; | |
9371 | subseg = now_subseg; | |
9372 | switch (*args) | |
9373 | { | |
9374 | default: /* unused default case avoids warnings. */ | |
9375 | case 'L': | |
9376 | newname = RDATA_SECTION_NAME; | |
3e722fb5 | 9377 | if (g_switch_value >= 8) |
252b5132 RH |
9378 | newname = ".lit8"; |
9379 | break; | |
9380 | case 'F': | |
3e722fb5 | 9381 | newname = RDATA_SECTION_NAME; |
252b5132 RH |
9382 | break; |
9383 | case 'l': | |
4d0d148d | 9384 | assert (g_switch_value >= 4); |
252b5132 RH |
9385 | newname = ".lit4"; |
9386 | break; | |
9387 | } | |
9388 | new_seg = subseg_new (newname, (subsegT) 0); | |
9389 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
9390 | bfd_set_section_flags (stdoutput, new_seg, | |
9391 | (SEC_ALLOC | |
9392 | | SEC_LOAD | |
9393 | | SEC_READONLY | |
9394 | | SEC_DATA)); | |
9395 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
9396 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
9397 | && strcmp (TARGET_OS, "elf") != 0) | |
9398 | record_alignment (new_seg, 4); | |
9399 | else | |
9400 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
9401 | if (seg == now_seg) | |
9402 | as_bad (_("Can't use floating point insn in this section")); | |
9403 | ||
9404 | /* Set the argument to the current address in the | |
9405 | section. */ | |
9406 | offset_expr.X_op = O_symbol; | |
9407 | offset_expr.X_add_symbol = | |
9408 | symbol_new ("L0\001", now_seg, | |
9409 | (valueT) frag_now_fix (), frag_now); | |
9410 | offset_expr.X_add_number = 0; | |
9411 | ||
9412 | /* Put the floating point number into the section. */ | |
9413 | p = frag_more ((int) length); | |
9414 | memcpy (p, temp, length); | |
9415 | ||
9416 | /* Switch back to the original section. */ | |
9417 | subseg_set (seg, subseg); | |
9418 | } | |
9419 | } | |
9420 | continue; | |
9421 | ||
9422 | case 'i': /* 16 bit unsigned immediate */ | |
9423 | case 'j': /* 16 bit signed immediate */ | |
f6688943 | 9424 | *imm_reloc = BFD_RELOC_LO16; |
5e0116d5 | 9425 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) |
252b5132 RH |
9426 | { |
9427 | int more; | |
5e0116d5 RS |
9428 | offsetT minval, maxval; |
9429 | ||
9430 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] | |
9431 | && strcmp (insn->name, insn[1].name) == 0); | |
9432 | ||
9433 | /* If the expression was written as an unsigned number, | |
9434 | only treat it as signed if there are no more | |
9435 | alternatives. */ | |
9436 | if (more | |
9437 | && *args == 'j' | |
9438 | && sizeof (imm_expr.X_add_number) <= 4 | |
9439 | && imm_expr.X_op == O_constant | |
9440 | && imm_expr.X_add_number < 0 | |
9441 | && imm_expr.X_unsigned | |
9442 | && HAVE_64BIT_GPRS) | |
9443 | break; | |
9444 | ||
9445 | /* For compatibility with older assemblers, we accept | |
9446 | 0x8000-0xffff as signed 16-bit numbers when only | |
9447 | signed numbers are allowed. */ | |
9448 | if (*args == 'i') | |
9449 | minval = 0, maxval = 0xffff; | |
9450 | else if (more) | |
9451 | minval = -0x8000, maxval = 0x7fff; | |
252b5132 | 9452 | else |
5e0116d5 RS |
9453 | minval = -0x8000, maxval = 0xffff; |
9454 | ||
9455 | if (imm_expr.X_op != O_constant | |
9456 | || imm_expr.X_add_number < minval | |
9457 | || imm_expr.X_add_number > maxval) | |
252b5132 RH |
9458 | { |
9459 | if (more) | |
9460 | break; | |
2ae7e77b AH |
9461 | if (imm_expr.X_op == O_constant |
9462 | || imm_expr.X_op == O_big) | |
5e0116d5 | 9463 | as_bad (_("expression out of range")); |
252b5132 RH |
9464 | } |
9465 | } | |
9466 | s = expr_end; | |
9467 | continue; | |
9468 | ||
9469 | case 'o': /* 16 bit offset */ | |
5e0116d5 RS |
9470 | /* Check whether there is only a single bracketed expression |
9471 | left. If so, it must be the base register and the | |
9472 | constant must be zero. */ | |
9473 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
9474 | { | |
9475 | offset_expr.X_op = O_constant; | |
9476 | offset_expr.X_add_number = 0; | |
9477 | continue; | |
9478 | } | |
252b5132 RH |
9479 | |
9480 | /* If this value won't fit into a 16 bit offset, then go | |
9481 | find a macro that will generate the 32 bit offset | |
afdbd6d0 | 9482 | code pattern. */ |
5e0116d5 | 9483 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 |
252b5132 RH |
9484 | && (offset_expr.X_op != O_constant |
9485 | || offset_expr.X_add_number >= 0x8000 | |
afdbd6d0 | 9486 | || offset_expr.X_add_number < -0x8000)) |
252b5132 RH |
9487 | break; |
9488 | ||
252b5132 RH |
9489 | s = expr_end; |
9490 | continue; | |
9491 | ||
9492 | case 'p': /* pc relative offset */ | |
0b25d3e6 | 9493 | *offset_reloc = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
9494 | my_getExpression (&offset_expr, s); |
9495 | s = expr_end; | |
9496 | continue; | |
9497 | ||
9498 | case 'u': /* upper 16 bits */ | |
5e0116d5 RS |
9499 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 |
9500 | && imm_expr.X_op == O_constant | |
9501 | && (imm_expr.X_add_number < 0 | |
9502 | || imm_expr.X_add_number >= 0x10000)) | |
252b5132 RH |
9503 | as_bad (_("lui expression not in range 0..65535")); |
9504 | s = expr_end; | |
9505 | continue; | |
9506 | ||
9507 | case 'a': /* 26 bit address */ | |
9508 | my_getExpression (&offset_expr, s); | |
9509 | s = expr_end; | |
f6688943 | 9510 | *offset_reloc = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
9511 | continue; |
9512 | ||
9513 | case 'N': /* 3 bit branch condition code */ | |
9514 | case 'M': /* 3 bit compare condition code */ | |
707bfff6 TS |
9515 | rtype = RTYPE_CCC; |
9516 | if (ip->insn_mo->pinfo & (FP_D| FP_S)) | |
9517 | rtype |= RTYPE_FCC; | |
9518 | if (!reg_lookup (&s, rtype, ®no)) | |
252b5132 | 9519 | break; |
30c378fd CD |
9520 | if ((strcmp(str + strlen(str) - 3, ".ps") == 0 |
9521 | || strcmp(str + strlen(str) - 5, "any2f") == 0 | |
9522 | || strcmp(str + strlen(str) - 5, "any2t") == 0) | |
9523 | && (regno & 1) != 0) | |
9524 | as_warn(_("Condition code register should be even for %s, was %d"), | |
9525 | str, regno); | |
9526 | if ((strcmp(str + strlen(str) - 5, "any4f") == 0 | |
9527 | || strcmp(str + strlen(str) - 5, "any4t") == 0) | |
9528 | && (regno & 3) != 0) | |
9529 | as_warn(_("Condition code register should be 0 or 4 for %s, was %d"), | |
9530 | str, regno); | |
252b5132 | 9531 | if (*args == 'N') |
bf12938e | 9532 | INSERT_OPERAND (BCC, *ip, regno); |
252b5132 | 9533 | else |
bf12938e | 9534 | INSERT_OPERAND (CCC, *ip, regno); |
beae10d5 | 9535 | continue; |
252b5132 | 9536 | |
156c2f8b NC |
9537 | case 'H': |
9538 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
9539 | s += 2; | |
3882b010 | 9540 | if (ISDIGIT (*s)) |
156c2f8b NC |
9541 | { |
9542 | c = 0; | |
9543 | do | |
9544 | { | |
9545 | c *= 10; | |
9546 | c += *s - '0'; | |
9547 | ++s; | |
9548 | } | |
3882b010 | 9549 | while (ISDIGIT (*s)); |
156c2f8b NC |
9550 | } |
9551 | else | |
9552 | c = 8; /* Invalid sel value. */ | |
9553 | ||
9554 | if (c > 7) | |
9555 | as_bad (_("invalid coprocessor sub-selection value (0-7)")); | |
9556 | ip->insn_opcode |= c; | |
9557 | continue; | |
9558 | ||
60b63b72 RS |
9559 | case 'e': |
9560 | /* Must be at least one digit. */ | |
9561 | my_getExpression (&imm_expr, s); | |
9562 | check_absolute_expr (ip, &imm_expr); | |
9563 | ||
9564 | if ((unsigned long) imm_expr.X_add_number | |
9565 | > (unsigned long) OP_MASK_VECBYTE) | |
9566 | { | |
9567 | as_bad (_("bad byte vector index (%ld)"), | |
9568 | (long) imm_expr.X_add_number); | |
9569 | imm_expr.X_add_number = 0; | |
9570 | } | |
9571 | ||
bf12938e | 9572 | INSERT_OPERAND (VECBYTE, *ip, imm_expr.X_add_number); |
60b63b72 RS |
9573 | imm_expr.X_op = O_absent; |
9574 | s = expr_end; | |
9575 | continue; | |
9576 | ||
9577 | case '%': | |
9578 | my_getExpression (&imm_expr, s); | |
9579 | check_absolute_expr (ip, &imm_expr); | |
9580 | ||
9581 | if ((unsigned long) imm_expr.X_add_number | |
9582 | > (unsigned long) OP_MASK_VECALIGN) | |
9583 | { | |
9584 | as_bad (_("bad byte vector index (%ld)"), | |
9585 | (long) imm_expr.X_add_number); | |
9586 | imm_expr.X_add_number = 0; | |
9587 | } | |
9588 | ||
bf12938e | 9589 | INSERT_OPERAND (VECALIGN, *ip, imm_expr.X_add_number); |
60b63b72 RS |
9590 | imm_expr.X_op = O_absent; |
9591 | s = expr_end; | |
9592 | continue; | |
9593 | ||
252b5132 RH |
9594 | default: |
9595 | as_bad (_("bad char = '%c'\n"), *args); | |
9596 | internalError (); | |
9597 | } | |
9598 | break; | |
9599 | } | |
9600 | /* Args don't match. */ | |
9601 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
9602 | !strcmp (insn->name, insn[1].name)) | |
9603 | { | |
9604 | ++insn; | |
9605 | s = argsStart; | |
268f6bed | 9606 | insn_error = _("illegal operands"); |
252b5132 RH |
9607 | continue; |
9608 | } | |
268f6bed L |
9609 | if (save_c) |
9610 | *(--s) = save_c; | |
252b5132 RH |
9611 | insn_error = _("illegal operands"); |
9612 | return; | |
9613 | } | |
9614 | } | |
9615 | ||
0499d65b TS |
9616 | #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); } |
9617 | ||
252b5132 RH |
9618 | /* This routine assembles an instruction into its binary format when |
9619 | assembling for the mips16. As a side effect, it sets one of the | |
9620 | global variables imm_reloc or offset_reloc to the type of | |
9621 | relocation to do if one of the operands is an address expression. | |
9622 | It also sets mips16_small and mips16_ext if the user explicitly | |
9623 | requested a small or extended instruction. */ | |
9624 | ||
9625 | static void | |
17a2f251 | 9626 | mips16_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
9627 | { |
9628 | char *s; | |
9629 | const char *args; | |
9630 | struct mips_opcode *insn; | |
9631 | char *argsstart; | |
9632 | unsigned int regno; | |
9633 | unsigned int lastregno = 0; | |
9634 | char *s_reset; | |
d6f16593 | 9635 | size_t i; |
252b5132 RH |
9636 | |
9637 | insn_error = NULL; | |
9638 | ||
b34976b6 AM |
9639 | mips16_small = FALSE; |
9640 | mips16_ext = FALSE; | |
252b5132 | 9641 | |
3882b010 | 9642 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
9643 | ; |
9644 | switch (*s) | |
9645 | { | |
9646 | case '\0': | |
9647 | break; | |
9648 | ||
9649 | case ' ': | |
9650 | *s++ = '\0'; | |
9651 | break; | |
9652 | ||
9653 | case '.': | |
9654 | if (s[1] == 't' && s[2] == ' ') | |
9655 | { | |
9656 | *s = '\0'; | |
b34976b6 | 9657 | mips16_small = TRUE; |
252b5132 RH |
9658 | s += 3; |
9659 | break; | |
9660 | } | |
9661 | else if (s[1] == 'e' && s[2] == ' ') | |
9662 | { | |
9663 | *s = '\0'; | |
b34976b6 | 9664 | mips16_ext = TRUE; |
252b5132 RH |
9665 | s += 3; |
9666 | break; | |
9667 | } | |
9668 | /* Fall through. */ | |
9669 | default: | |
9670 | insn_error = _("unknown opcode"); | |
9671 | return; | |
9672 | } | |
9673 | ||
9674 | if (mips_opts.noautoextend && ! mips16_ext) | |
b34976b6 | 9675 | mips16_small = TRUE; |
252b5132 RH |
9676 | |
9677 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
9678 | { | |
9679 | insn_error = _("unrecognized opcode"); | |
9680 | return; | |
9681 | } | |
9682 | ||
9683 | argsstart = s; | |
9684 | for (;;) | |
9685 | { | |
9b3f89ee TS |
9686 | bfd_boolean ok; |
9687 | ||
252b5132 RH |
9688 | assert (strcmp (insn->name, str) == 0); |
9689 | ||
9b3f89ee TS |
9690 | if (OPCODE_IS_MEMBER (insn, mips_opts.isa, mips_opts.arch)) |
9691 | ok = TRUE; | |
9692 | else | |
9693 | ok = FALSE; | |
9694 | ||
9695 | if (! ok) | |
9696 | { | |
9697 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] | |
9698 | && strcmp (insn->name, insn[1].name) == 0) | |
9699 | { | |
9700 | ++insn; | |
9701 | continue; | |
9702 | } | |
9703 | else | |
9704 | { | |
9705 | if (!insn_error) | |
9706 | { | |
9707 | static char buf[100]; | |
9708 | sprintf (buf, | |
9709 | _("opcode not supported on this processor: %s (%s)"), | |
9710 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
9711 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
9712 | insn_error = buf; | |
9713 | } | |
9714 | return; | |
9715 | } | |
9716 | } | |
9717 | ||
1e915849 | 9718 | create_insn (ip, insn); |
252b5132 | 9719 | imm_expr.X_op = O_absent; |
f6688943 TS |
9720 | imm_reloc[0] = BFD_RELOC_UNUSED; |
9721 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
9722 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
5f74bc13 | 9723 | imm2_expr.X_op = O_absent; |
252b5132 | 9724 | offset_expr.X_op = O_absent; |
f6688943 TS |
9725 | offset_reloc[0] = BFD_RELOC_UNUSED; |
9726 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
9727 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
9728 | for (args = insn->args; 1; ++args) |
9729 | { | |
9730 | int c; | |
9731 | ||
9732 | if (*s == ' ') | |
9733 | ++s; | |
9734 | ||
9735 | /* In this switch statement we call break if we did not find | |
9736 | a match, continue if we did find a match, or return if we | |
9737 | are done. */ | |
9738 | ||
9739 | c = *args; | |
9740 | switch (c) | |
9741 | { | |
9742 | case '\0': | |
9743 | if (*s == '\0') | |
9744 | { | |
9745 | /* Stuff the immediate value in now, if we can. */ | |
9746 | if (imm_expr.X_op == O_constant | |
f6688943 | 9747 | && *imm_reloc > BFD_RELOC_UNUSED |
252b5132 RH |
9748 | && insn->pinfo != INSN_MACRO) |
9749 | { | |
d6f16593 MR |
9750 | valueT tmp; |
9751 | ||
9752 | switch (*offset_reloc) | |
9753 | { | |
9754 | case BFD_RELOC_MIPS16_HI16_S: | |
9755 | tmp = (imm_expr.X_add_number + 0x8000) >> 16; | |
9756 | break; | |
9757 | ||
9758 | case BFD_RELOC_MIPS16_HI16: | |
9759 | tmp = imm_expr.X_add_number >> 16; | |
9760 | break; | |
9761 | ||
9762 | case BFD_RELOC_MIPS16_LO16: | |
9763 | tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff) | |
9764 | - 0x8000; | |
9765 | break; | |
9766 | ||
9767 | case BFD_RELOC_UNUSED: | |
9768 | tmp = imm_expr.X_add_number; | |
9769 | break; | |
9770 | ||
9771 | default: | |
9772 | internalError (); | |
9773 | } | |
9774 | *offset_reloc = BFD_RELOC_UNUSED; | |
9775 | ||
c4e7957c | 9776 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
d6f16593 | 9777 | tmp, TRUE, mips16_small, |
252b5132 RH |
9778 | mips16_ext, &ip->insn_opcode, |
9779 | &ip->use_extend, &ip->extend); | |
9780 | imm_expr.X_op = O_absent; | |
f6688943 | 9781 | *imm_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
9782 | } |
9783 | ||
9784 | return; | |
9785 | } | |
9786 | break; | |
9787 | ||
9788 | case ',': | |
9789 | if (*s++ == c) | |
9790 | continue; | |
9791 | s--; | |
9792 | switch (*++args) | |
9793 | { | |
9794 | case 'v': | |
bf12938e | 9795 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 RH |
9796 | continue; |
9797 | case 'w': | |
bf12938e | 9798 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
9799 | continue; |
9800 | } | |
9801 | break; | |
9802 | ||
9803 | case '(': | |
9804 | case ')': | |
9805 | if (*s++ == c) | |
9806 | continue; | |
9807 | break; | |
9808 | ||
9809 | case 'v': | |
9810 | case 'w': | |
9811 | if (s[0] != '$') | |
9812 | { | |
9813 | if (c == 'v') | |
bf12938e | 9814 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 | 9815 | else |
bf12938e | 9816 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
9817 | ++args; |
9818 | continue; | |
9819 | } | |
9820 | /* Fall through. */ | |
9821 | case 'x': | |
9822 | case 'y': | |
9823 | case 'z': | |
9824 | case 'Z': | |
9825 | case '0': | |
9826 | case 'S': | |
9827 | case 'R': | |
9828 | case 'X': | |
9829 | case 'Y': | |
707bfff6 TS |
9830 | s_reset = s; |
9831 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) | |
252b5132 | 9832 | { |
707bfff6 | 9833 | if (c == 'v' || c == 'w') |
85b51719 | 9834 | { |
707bfff6 | 9835 | if (c == 'v') |
a9e24354 | 9836 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
707bfff6 | 9837 | else |
a9e24354 | 9838 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
707bfff6 TS |
9839 | ++args; |
9840 | continue; | |
85b51719 | 9841 | } |
707bfff6 | 9842 | break; |
252b5132 RH |
9843 | } |
9844 | ||
9845 | if (*s == ' ') | |
9846 | ++s; | |
9847 | if (args[1] != *s) | |
9848 | { | |
9849 | if (c == 'v' || c == 'w') | |
9850 | { | |
9851 | regno = mips16_to_32_reg_map[lastregno]; | |
9852 | s = s_reset; | |
f9419b05 | 9853 | ++args; |
252b5132 RH |
9854 | } |
9855 | } | |
9856 | ||
9857 | switch (c) | |
9858 | { | |
9859 | case 'x': | |
9860 | case 'y': | |
9861 | case 'z': | |
9862 | case 'v': | |
9863 | case 'w': | |
9864 | case 'Z': | |
9865 | regno = mips32_to_16_reg_map[regno]; | |
9866 | break; | |
9867 | ||
9868 | case '0': | |
9869 | if (regno != 0) | |
9870 | regno = ILLEGAL_REG; | |
9871 | break; | |
9872 | ||
9873 | case 'S': | |
9874 | if (regno != SP) | |
9875 | regno = ILLEGAL_REG; | |
9876 | break; | |
9877 | ||
9878 | case 'R': | |
9879 | if (regno != RA) | |
9880 | regno = ILLEGAL_REG; | |
9881 | break; | |
9882 | ||
9883 | case 'X': | |
9884 | case 'Y': | |
9885 | if (regno == AT && ! mips_opts.noat) | |
9886 | as_warn (_("used $at without \".set noat\"")); | |
9887 | break; | |
9888 | ||
9889 | default: | |
9890 | internalError (); | |
9891 | } | |
9892 | ||
9893 | if (regno == ILLEGAL_REG) | |
9894 | break; | |
9895 | ||
9896 | switch (c) | |
9897 | { | |
9898 | case 'x': | |
9899 | case 'v': | |
bf12938e | 9900 | MIPS16_INSERT_OPERAND (RX, *ip, regno); |
252b5132 RH |
9901 | break; |
9902 | case 'y': | |
9903 | case 'w': | |
bf12938e | 9904 | MIPS16_INSERT_OPERAND (RY, *ip, regno); |
252b5132 RH |
9905 | break; |
9906 | case 'z': | |
bf12938e | 9907 | MIPS16_INSERT_OPERAND (RZ, *ip, regno); |
252b5132 RH |
9908 | break; |
9909 | case 'Z': | |
bf12938e | 9910 | MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno); |
252b5132 RH |
9911 | case '0': |
9912 | case 'S': | |
9913 | case 'R': | |
9914 | break; | |
9915 | case 'X': | |
bf12938e | 9916 | MIPS16_INSERT_OPERAND (REGR32, *ip, regno); |
252b5132 RH |
9917 | break; |
9918 | case 'Y': | |
9919 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
bf12938e | 9920 | MIPS16_INSERT_OPERAND (REG32R, *ip, regno); |
252b5132 RH |
9921 | break; |
9922 | default: | |
9923 | internalError (); | |
9924 | } | |
9925 | ||
9926 | lastregno = regno; | |
9927 | continue; | |
9928 | ||
9929 | case 'P': | |
9930 | if (strncmp (s, "$pc", 3) == 0) | |
9931 | { | |
9932 | s += 3; | |
9933 | continue; | |
9934 | } | |
9935 | break; | |
9936 | ||
252b5132 RH |
9937 | case '5': |
9938 | case 'H': | |
9939 | case 'W': | |
9940 | case 'D': | |
9941 | case 'j': | |
252b5132 RH |
9942 | case 'V': |
9943 | case 'C': | |
9944 | case 'U': | |
9945 | case 'k': | |
9946 | case 'K': | |
d6f16593 MR |
9947 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); |
9948 | if (i > 0) | |
252b5132 | 9949 | { |
d6f16593 | 9950 | if (imm_expr.X_op != O_constant) |
252b5132 | 9951 | { |
b34976b6 | 9952 | mips16_ext = TRUE; |
b34976b6 | 9953 | ip->use_extend = TRUE; |
252b5132 | 9954 | ip->extend = 0; |
252b5132 | 9955 | } |
d6f16593 MR |
9956 | else |
9957 | { | |
9958 | /* We need to relax this instruction. */ | |
9959 | *offset_reloc = *imm_reloc; | |
9960 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
9961 | } | |
9962 | s = expr_end; | |
9963 | continue; | |
252b5132 | 9964 | } |
d6f16593 MR |
9965 | *imm_reloc = BFD_RELOC_UNUSED; |
9966 | /* Fall through. */ | |
9967 | case '<': | |
9968 | case '>': | |
9969 | case '[': | |
9970 | case ']': | |
9971 | case '4': | |
9972 | case '8': | |
9973 | my_getExpression (&imm_expr, s); | |
252b5132 RH |
9974 | if (imm_expr.X_op == O_register) |
9975 | { | |
9976 | /* What we thought was an expression turned out to | |
9977 | be a register. */ | |
9978 | ||
9979 | if (s[0] == '(' && args[1] == '(') | |
9980 | { | |
9981 | /* It looks like the expression was omitted | |
9982 | before a register indirection, which means | |
9983 | that the expression is implicitly zero. We | |
9984 | still set up imm_expr, so that we handle | |
9985 | explicit extensions correctly. */ | |
9986 | imm_expr.X_op = O_constant; | |
9987 | imm_expr.X_add_number = 0; | |
f6688943 | 9988 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9989 | continue; |
9990 | } | |
9991 | ||
9992 | break; | |
9993 | } | |
9994 | ||
9995 | /* We need to relax this instruction. */ | |
f6688943 | 9996 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9997 | s = expr_end; |
9998 | continue; | |
9999 | ||
10000 | case 'p': | |
10001 | case 'q': | |
10002 | case 'A': | |
10003 | case 'B': | |
10004 | case 'E': | |
10005 | /* We use offset_reloc rather than imm_reloc for the PC | |
10006 | relative operands. This lets macros with both | |
10007 | immediate and address operands work correctly. */ | |
10008 | my_getExpression (&offset_expr, s); | |
10009 | ||
10010 | if (offset_expr.X_op == O_register) | |
10011 | break; | |
10012 | ||
10013 | /* We need to relax this instruction. */ | |
f6688943 | 10014 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
10015 | s = expr_end; |
10016 | continue; | |
10017 | ||
10018 | case '6': /* break code */ | |
10019 | my_getExpression (&imm_expr, s); | |
10020 | check_absolute_expr (ip, &imm_expr); | |
10021 | if ((unsigned long) imm_expr.X_add_number > 63) | |
bf12938e RS |
10022 | as_warn (_("Invalid value for `%s' (%lu)"), |
10023 | ip->insn_mo->name, | |
10024 | (unsigned long) imm_expr.X_add_number); | |
10025 | MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number); | |
252b5132 RH |
10026 | imm_expr.X_op = O_absent; |
10027 | s = expr_end; | |
10028 | continue; | |
10029 | ||
10030 | case 'a': /* 26 bit address */ | |
10031 | my_getExpression (&offset_expr, s); | |
10032 | s = expr_end; | |
f6688943 | 10033 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
10034 | ip->insn_opcode <<= 16; |
10035 | continue; | |
10036 | ||
10037 | case 'l': /* register list for entry macro */ | |
10038 | case 'L': /* register list for exit macro */ | |
10039 | { | |
10040 | int mask; | |
10041 | ||
10042 | if (c == 'l') | |
10043 | mask = 0; | |
10044 | else | |
10045 | mask = 7 << 3; | |
10046 | while (*s != '\0') | |
10047 | { | |
707bfff6 | 10048 | unsigned int freg, reg1, reg2; |
252b5132 RH |
10049 | |
10050 | while (*s == ' ' || *s == ',') | |
10051 | ++s; | |
707bfff6 | 10052 | if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
252b5132 | 10053 | freg = 0; |
707bfff6 TS |
10054 | else if (reg_lookup (&s, RTYPE_FPU, ®1)) |
10055 | freg = 1; | |
252b5132 RH |
10056 | else |
10057 | { | |
707bfff6 TS |
10058 | as_bad (_("can't parse register list")); |
10059 | break; | |
252b5132 RH |
10060 | } |
10061 | if (*s == ' ') | |
10062 | ++s; | |
10063 | if (*s != '-') | |
10064 | reg2 = reg1; | |
10065 | else | |
10066 | { | |
10067 | ++s; | |
707bfff6 TS |
10068 | if (!reg_lookup (&s, freg ? RTYPE_FPU |
10069 | : (RTYPE_GP | RTYPE_NUM), ®2)) | |
252b5132 | 10070 | { |
707bfff6 TS |
10071 | as_bad (_("invalid register list")); |
10072 | break; | |
252b5132 RH |
10073 | } |
10074 | } | |
10075 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
10076 | { | |
10077 | mask &= ~ (7 << 3); | |
10078 | mask |= 5 << 3; | |
10079 | } | |
10080 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
10081 | { | |
10082 | mask &= ~ (7 << 3); | |
10083 | mask |= 6 << 3; | |
10084 | } | |
10085 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
10086 | mask |= (reg2 - 3) << 3; | |
10087 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
10088 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 10089 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
10090 | mask |= 1; |
10091 | else | |
10092 | { | |
10093 | as_bad (_("invalid register list")); | |
10094 | break; | |
10095 | } | |
10096 | } | |
10097 | /* The mask is filled in in the opcode table for the | |
10098 | benefit of the disassembler. We remove it before | |
10099 | applying the actual mask. */ | |
10100 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
10101 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
10102 | } | |
10103 | continue; | |
10104 | ||
0499d65b TS |
10105 | case 'm': /* Register list for save insn. */ |
10106 | case 'M': /* Register list for restore insn. */ | |
10107 | { | |
10108 | int opcode = 0; | |
10109 | int framesz = 0, seen_framesz = 0; | |
10110 | int args = 0, statics = 0, sregs = 0; | |
10111 | ||
10112 | while (*s != '\0') | |
10113 | { | |
10114 | unsigned int reg1, reg2; | |
10115 | ||
10116 | SKIP_SPACE_TABS (s); | |
10117 | while (*s == ',') | |
10118 | ++s; | |
10119 | SKIP_SPACE_TABS (s); | |
10120 | ||
10121 | my_getExpression (&imm_expr, s); | |
10122 | if (imm_expr.X_op == O_constant) | |
10123 | { | |
10124 | /* Handle the frame size. */ | |
10125 | if (seen_framesz) | |
10126 | { | |
10127 | as_bad (_("more than one frame size in list")); | |
10128 | break; | |
10129 | } | |
10130 | seen_framesz = 1; | |
10131 | framesz = imm_expr.X_add_number; | |
10132 | imm_expr.X_op = O_absent; | |
10133 | s = expr_end; | |
10134 | continue; | |
10135 | } | |
10136 | ||
707bfff6 | 10137 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
0499d65b TS |
10138 | { |
10139 | as_bad (_("can't parse register list")); | |
10140 | break; | |
10141 | } | |
0499d65b | 10142 | |
707bfff6 TS |
10143 | while (*s == ' ') |
10144 | ++s; | |
10145 | ||
0499d65b TS |
10146 | if (*s != '-') |
10147 | reg2 = reg1; | |
10148 | else | |
10149 | { | |
10150 | ++s; | |
707bfff6 TS |
10151 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2) |
10152 | || reg2 < reg1) | |
0499d65b TS |
10153 | { |
10154 | as_bad (_("can't parse register list")); | |
10155 | break; | |
10156 | } | |
0499d65b TS |
10157 | } |
10158 | ||
10159 | while (reg1 <= reg2) | |
10160 | { | |
10161 | if (reg1 >= 4 && reg1 <= 7) | |
10162 | { | |
10163 | if (c == 'm' && !seen_framesz) | |
10164 | /* args $a0-$a3 */ | |
10165 | args |= 1 << (reg1 - 4); | |
10166 | else | |
10167 | /* statics $a0-$a3 */ | |
10168 | statics |= 1 << (reg1 - 4); | |
10169 | } | |
10170 | else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30) | |
10171 | { | |
10172 | /* $s0-$s8 */ | |
10173 | sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16)); | |
10174 | } | |
10175 | else if (reg1 == 31) | |
10176 | { | |
10177 | /* Add $ra to insn. */ | |
10178 | opcode |= 0x40; | |
10179 | } | |
10180 | else | |
10181 | { | |
10182 | as_bad (_("unexpected register in list")); | |
10183 | break; | |
10184 | } | |
10185 | if (++reg1 == 24) | |
10186 | reg1 = 30; | |
10187 | } | |
10188 | } | |
10189 | ||
10190 | /* Encode args/statics combination. */ | |
10191 | if (args & statics) | |
10192 | as_bad (_("arg/static registers overlap")); | |
10193 | else if (args == 0xf) | |
10194 | /* All $a0-$a3 are args. */ | |
10195 | opcode |= MIPS16_ALL_ARGS << 16; | |
10196 | else if (statics == 0xf) | |
10197 | /* All $a0-$a3 are statics. */ | |
10198 | opcode |= MIPS16_ALL_STATICS << 16; | |
10199 | else | |
10200 | { | |
10201 | int narg = 0, nstat = 0; | |
10202 | ||
10203 | /* Count arg registers. */ | |
10204 | while (args & 0x1) | |
10205 | { | |
10206 | args >>= 1; | |
10207 | narg++; | |
10208 | } | |
10209 | if (args != 0) | |
10210 | as_bad (_("invalid arg register list")); | |
10211 | ||
10212 | /* Count static registers. */ | |
10213 | while (statics & 0x8) | |
10214 | { | |
10215 | statics = (statics << 1) & 0xf; | |
10216 | nstat++; | |
10217 | } | |
10218 | if (statics != 0) | |
10219 | as_bad (_("invalid static register list")); | |
10220 | ||
10221 | /* Encode args/statics. */ | |
10222 | opcode |= ((narg << 2) | nstat) << 16; | |
10223 | } | |
10224 | ||
10225 | /* Encode $s0/$s1. */ | |
10226 | if (sregs & (1 << 0)) /* $s0 */ | |
10227 | opcode |= 0x20; | |
10228 | if (sregs & (1 << 1)) /* $s1 */ | |
10229 | opcode |= 0x10; | |
10230 | sregs >>= 2; | |
10231 | ||
10232 | if (sregs != 0) | |
10233 | { | |
10234 | /* Count regs $s2-$s8. */ | |
10235 | int nsreg = 0; | |
10236 | while (sregs & 1) | |
10237 | { | |
10238 | sregs >>= 1; | |
10239 | nsreg++; | |
10240 | } | |
10241 | if (sregs != 0) | |
10242 | as_bad (_("invalid static register list")); | |
10243 | /* Encode $s2-$s8. */ | |
10244 | opcode |= nsreg << 24; | |
10245 | } | |
10246 | ||
10247 | /* Encode frame size. */ | |
10248 | if (!seen_framesz) | |
10249 | as_bad (_("missing frame size")); | |
10250 | else if ((framesz & 7) != 0 || framesz < 0 | |
10251 | || framesz > 0xff * 8) | |
10252 | as_bad (_("invalid frame size")); | |
10253 | else if (framesz != 128 || (opcode >> 16) != 0) | |
10254 | { | |
10255 | framesz /= 8; | |
10256 | opcode |= (((framesz & 0xf0) << 16) | |
10257 | | (framesz & 0x0f)); | |
10258 | } | |
10259 | ||
10260 | /* Finally build the instruction. */ | |
10261 | if ((opcode >> 16) != 0 || framesz == 0) | |
10262 | { | |
10263 | ip->use_extend = TRUE; | |
10264 | ip->extend = opcode >> 16; | |
10265 | } | |
10266 | ip->insn_opcode |= opcode & 0x7f; | |
10267 | } | |
10268 | continue; | |
10269 | ||
252b5132 RH |
10270 | case 'e': /* extend code */ |
10271 | my_getExpression (&imm_expr, s); | |
10272 | check_absolute_expr (ip, &imm_expr); | |
10273 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
10274 | { | |
10275 | as_warn (_("Invalid value for `%s' (%lu)"), | |
10276 | ip->insn_mo->name, | |
10277 | (unsigned long) imm_expr.X_add_number); | |
10278 | imm_expr.X_add_number &= 0x7ff; | |
10279 | } | |
10280 | ip->insn_opcode |= imm_expr.X_add_number; | |
10281 | imm_expr.X_op = O_absent; | |
10282 | s = expr_end; | |
10283 | continue; | |
10284 | ||
10285 | default: | |
10286 | internalError (); | |
10287 | } | |
10288 | break; | |
10289 | } | |
10290 | ||
10291 | /* Args don't match. */ | |
10292 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
10293 | strcmp (insn->name, insn[1].name) == 0) | |
10294 | { | |
10295 | ++insn; | |
10296 | s = argsstart; | |
10297 | continue; | |
10298 | } | |
10299 | ||
10300 | insn_error = _("illegal operands"); | |
10301 | ||
10302 | return; | |
10303 | } | |
10304 | } | |
10305 | ||
10306 | /* This structure holds information we know about a mips16 immediate | |
10307 | argument type. */ | |
10308 | ||
e972090a NC |
10309 | struct mips16_immed_operand |
10310 | { | |
252b5132 RH |
10311 | /* The type code used in the argument string in the opcode table. */ |
10312 | int type; | |
10313 | /* The number of bits in the short form of the opcode. */ | |
10314 | int nbits; | |
10315 | /* The number of bits in the extended form of the opcode. */ | |
10316 | int extbits; | |
10317 | /* The amount by which the short form is shifted when it is used; | |
10318 | for example, the sw instruction has a shift count of 2. */ | |
10319 | int shift; | |
10320 | /* The amount by which the short form is shifted when it is stored | |
10321 | into the instruction code. */ | |
10322 | int op_shift; | |
10323 | /* Non-zero if the short form is unsigned. */ | |
10324 | int unsp; | |
10325 | /* Non-zero if the extended form is unsigned. */ | |
10326 | int extu; | |
10327 | /* Non-zero if the value is PC relative. */ | |
10328 | int pcrel; | |
10329 | }; | |
10330 | ||
10331 | /* The mips16 immediate operand types. */ | |
10332 | ||
10333 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
10334 | { | |
10335 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
10336 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
10337 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
10338 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
10339 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
10340 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10341 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10342 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10343 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10344 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
10345 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10346 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10347 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10348 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
10349 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
10350 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
10351 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
10352 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
10353 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
10354 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
10355 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
10356 | }; | |
10357 | ||
10358 | #define MIPS16_NUM_IMMED \ | |
10359 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
10360 | ||
10361 | /* Handle a mips16 instruction with an immediate value. This or's the | |
10362 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
10363 | whether an extended value is needed; if one is needed, it sets | |
10364 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
10365 | If SMALL is true, an unextended opcode was explicitly requested. | |
10366 | If EXT is true, an extended opcode was explicitly requested. If | |
10367 | WARN is true, warn if EXT does not match reality. */ | |
10368 | ||
10369 | static void | |
17a2f251 TS |
10370 | mips16_immed (char *file, unsigned int line, int type, offsetT val, |
10371 | bfd_boolean warn, bfd_boolean small, bfd_boolean ext, | |
10372 | unsigned long *insn, bfd_boolean *use_extend, | |
10373 | unsigned short *extend) | |
252b5132 RH |
10374 | { |
10375 | register const struct mips16_immed_operand *op; | |
10376 | int mintiny, maxtiny; | |
b34976b6 | 10377 | bfd_boolean needext; |
252b5132 RH |
10378 | |
10379 | op = mips16_immed_operands; | |
10380 | while (op->type != type) | |
10381 | { | |
10382 | ++op; | |
10383 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
10384 | } | |
10385 | ||
10386 | if (op->unsp) | |
10387 | { | |
10388 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
10389 | { | |
10390 | mintiny = 1; | |
10391 | maxtiny = 1 << op->nbits; | |
10392 | } | |
10393 | else | |
10394 | { | |
10395 | mintiny = 0; | |
10396 | maxtiny = (1 << op->nbits) - 1; | |
10397 | } | |
10398 | } | |
10399 | else | |
10400 | { | |
10401 | mintiny = - (1 << (op->nbits - 1)); | |
10402 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
10403 | } | |
10404 | ||
10405 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
10406 | if (type == 'p' || type == 'q') | |
10407 | val /= 2; | |
10408 | ||
10409 | if ((val & ((1 << op->shift) - 1)) != 0 | |
10410 | || val < (mintiny << op->shift) | |
10411 | || val > (maxtiny << op->shift)) | |
b34976b6 | 10412 | needext = TRUE; |
252b5132 | 10413 | else |
b34976b6 | 10414 | needext = FALSE; |
252b5132 RH |
10415 | |
10416 | if (warn && ext && ! needext) | |
beae10d5 KH |
10417 | as_warn_where (file, line, |
10418 | _("extended operand requested but not required")); | |
252b5132 RH |
10419 | if (small && needext) |
10420 | as_bad_where (file, line, _("invalid unextended operand value")); | |
10421 | ||
10422 | if (small || (! ext && ! needext)) | |
10423 | { | |
10424 | int insnval; | |
10425 | ||
b34976b6 | 10426 | *use_extend = FALSE; |
252b5132 RH |
10427 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
10428 | insnval <<= op->op_shift; | |
10429 | *insn |= insnval; | |
10430 | } | |
10431 | else | |
10432 | { | |
10433 | long minext, maxext; | |
10434 | int extval; | |
10435 | ||
10436 | if (op->extu) | |
10437 | { | |
10438 | minext = 0; | |
10439 | maxext = (1 << op->extbits) - 1; | |
10440 | } | |
10441 | else | |
10442 | { | |
10443 | minext = - (1 << (op->extbits - 1)); | |
10444 | maxext = (1 << (op->extbits - 1)) - 1; | |
10445 | } | |
10446 | if (val < minext || val > maxext) | |
10447 | as_bad_where (file, line, | |
10448 | _("operand value out of range for instruction")); | |
10449 | ||
b34976b6 | 10450 | *use_extend = TRUE; |
252b5132 RH |
10451 | if (op->extbits == 16) |
10452 | { | |
10453 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
10454 | val &= 0x1f; | |
10455 | } | |
10456 | else if (op->extbits == 15) | |
10457 | { | |
10458 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
10459 | val &= 0xf; | |
10460 | } | |
10461 | else | |
10462 | { | |
10463 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
10464 | val = 0; | |
10465 | } | |
10466 | ||
10467 | *extend = (unsigned short) extval; | |
10468 | *insn |= val; | |
10469 | } | |
10470 | } | |
10471 | \f | |
d6f16593 | 10472 | struct percent_op_match |
ad8d3bb3 | 10473 | { |
5e0116d5 RS |
10474 | const char *str; |
10475 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
10476 | }; |
10477 | ||
10478 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 10479 | { |
5e0116d5 | 10480 | {"%lo", BFD_RELOC_LO16}, |
ad8d3bb3 | 10481 | #ifdef OBJ_ELF |
5e0116d5 RS |
10482 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
10483 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
10484 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
10485 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
10486 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
10487 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
10488 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
10489 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
10490 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
10491 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
10492 | {"%half", BFD_RELOC_16}, | |
10493 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
10494 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
10495 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
10496 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
10497 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
10498 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
10499 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
10500 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
10501 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
10502 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
ad8d3bb3 | 10503 | #endif |
5e0116d5 | 10504 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
10505 | }; |
10506 | ||
d6f16593 MR |
10507 | static const struct percent_op_match mips16_percent_op[] = |
10508 | { | |
10509 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
10510 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, | |
10511 | {"%hi", BFD_RELOC_MIPS16_HI16_S} | |
10512 | }; | |
10513 | ||
252b5132 | 10514 | |
5e0116d5 RS |
10515 | /* Return true if *STR points to a relocation operator. When returning true, |
10516 | move *STR over the operator and store its relocation code in *RELOC. | |
10517 | Leave both *STR and *RELOC alone when returning false. */ | |
10518 | ||
10519 | static bfd_boolean | |
17a2f251 | 10520 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 10521 | { |
d6f16593 MR |
10522 | const struct percent_op_match *percent_op; |
10523 | size_t limit, i; | |
10524 | ||
10525 | if (mips_opts.mips16) | |
10526 | { | |
10527 | percent_op = mips16_percent_op; | |
10528 | limit = ARRAY_SIZE (mips16_percent_op); | |
10529 | } | |
10530 | else | |
10531 | { | |
10532 | percent_op = mips_percent_op; | |
10533 | limit = ARRAY_SIZE (mips_percent_op); | |
10534 | } | |
76b3015f | 10535 | |
d6f16593 | 10536 | for (i = 0; i < limit; i++) |
5e0116d5 | 10537 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 10538 | { |
3f98094e DJ |
10539 | int len = strlen (percent_op[i].str); |
10540 | ||
10541 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
10542 | continue; | |
10543 | ||
5e0116d5 RS |
10544 | *str += strlen (percent_op[i].str); |
10545 | *reloc = percent_op[i].reloc; | |
394f9b3a | 10546 | |
5e0116d5 RS |
10547 | /* Check whether the output BFD supports this relocation. |
10548 | If not, issue an error and fall back on something safe. */ | |
10549 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 10550 | { |
5e0116d5 RS |
10551 | as_bad ("relocation %s isn't supported by the current ABI", |
10552 | percent_op[i].str); | |
01a3f561 | 10553 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 10554 | } |
5e0116d5 | 10555 | return TRUE; |
394f9b3a | 10556 | } |
5e0116d5 | 10557 | return FALSE; |
394f9b3a | 10558 | } |
ad8d3bb3 | 10559 | |
ad8d3bb3 | 10560 | |
5e0116d5 RS |
10561 | /* Parse string STR as a 16-bit relocatable operand. Store the |
10562 | expression in *EP and the relocations in the array starting | |
10563 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 10564 | |
01a3f561 | 10565 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 10566 | |
5e0116d5 | 10567 | static size_t |
17a2f251 TS |
10568 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
10569 | char *str) | |
ad8d3bb3 | 10570 | { |
5e0116d5 RS |
10571 | bfd_reloc_code_real_type reversed_reloc[3]; |
10572 | size_t reloc_index, i; | |
09b8f35a RS |
10573 | int crux_depth, str_depth; |
10574 | char *crux; | |
5e0116d5 RS |
10575 | |
10576 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
10577 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
10578 | of the main expression and with CRUX_DEPTH containing the number | |
10579 | of open brackets at that point. */ | |
10580 | reloc_index = -1; | |
10581 | str_depth = 0; | |
10582 | do | |
fb1b3232 | 10583 | { |
09b8f35a RS |
10584 | reloc_index++; |
10585 | crux = str; | |
10586 | crux_depth = str_depth; | |
10587 | ||
10588 | /* Skip over whitespace and brackets, keeping count of the number | |
10589 | of brackets. */ | |
10590 | while (*str == ' ' || *str == '\t' || *str == '(') | |
10591 | if (*str++ == '(') | |
10592 | str_depth++; | |
5e0116d5 | 10593 | } |
09b8f35a RS |
10594 | while (*str == '%' |
10595 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
10596 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 10597 | |
09b8f35a | 10598 | my_getExpression (ep, crux); |
5e0116d5 | 10599 | str = expr_end; |
394f9b3a | 10600 | |
5e0116d5 | 10601 | /* Match every open bracket. */ |
09b8f35a | 10602 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 10603 | if (*str++ == ')') |
09b8f35a | 10604 | crux_depth--; |
394f9b3a | 10605 | |
09b8f35a | 10606 | if (crux_depth > 0) |
5e0116d5 | 10607 | as_bad ("unclosed '('"); |
394f9b3a | 10608 | |
5e0116d5 | 10609 | expr_end = str; |
252b5132 | 10610 | |
01a3f561 | 10611 | if (reloc_index != 0) |
64bdfcaf RS |
10612 | { |
10613 | prev_reloc_op_frag = frag_now; | |
10614 | for (i = 0; i < reloc_index; i++) | |
10615 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
10616 | } | |
fb1b3232 | 10617 | |
5e0116d5 | 10618 | return reloc_index; |
252b5132 RH |
10619 | } |
10620 | ||
10621 | static void | |
17a2f251 | 10622 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
10623 | { |
10624 | char *save_in; | |
98aa84af | 10625 | valueT val; |
252b5132 RH |
10626 | |
10627 | save_in = input_line_pointer; | |
10628 | input_line_pointer = str; | |
10629 | expression (ep); | |
10630 | expr_end = input_line_pointer; | |
10631 | input_line_pointer = save_in; | |
10632 | ||
10633 | /* If we are in mips16 mode, and this is an expression based on `.', | |
10634 | then we bump the value of the symbol by 1 since that is how other | |
10635 | text symbols are handled. We don't bother to handle complex | |
10636 | expressions, just `.' plus or minus a constant. */ | |
10637 | if (mips_opts.mips16 | |
10638 | && ep->X_op == O_symbol | |
10639 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
10640 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
49309057 ILT |
10641 | && symbol_get_frag (ep->X_add_symbol) == frag_now |
10642 | && symbol_constant_p (ep->X_add_symbol) | |
98aa84af AM |
10643 | && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ()) |
10644 | S_SET_VALUE (ep->X_add_symbol, val + 1); | |
252b5132 RH |
10645 | } |
10646 | ||
10647 | /* Turn a string in input_line_pointer into a floating point constant | |
bc0d738a NC |
10648 | of type TYPE, and store the appropriate bytes in *LITP. The number |
10649 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
252b5132 RH |
10650 | returned, or NULL on OK. */ |
10651 | ||
10652 | char * | |
17a2f251 | 10653 | md_atof (int type, char *litP, int *sizeP) |
252b5132 RH |
10654 | { |
10655 | int prec; | |
10656 | LITTLENUM_TYPE words[4]; | |
10657 | char *t; | |
10658 | int i; | |
10659 | ||
10660 | switch (type) | |
10661 | { | |
10662 | case 'f': | |
10663 | prec = 2; | |
10664 | break; | |
10665 | ||
10666 | case 'd': | |
10667 | prec = 4; | |
10668 | break; | |
10669 | ||
10670 | default: | |
10671 | *sizeP = 0; | |
10672 | return _("bad call to md_atof"); | |
10673 | } | |
10674 | ||
10675 | t = atof_ieee (input_line_pointer, type, words); | |
10676 | if (t) | |
10677 | input_line_pointer = t; | |
10678 | ||
10679 | *sizeP = prec * 2; | |
10680 | ||
10681 | if (! target_big_endian) | |
10682 | { | |
10683 | for (i = prec - 1; i >= 0; i--) | |
10684 | { | |
17a2f251 | 10685 | md_number_to_chars (litP, words[i], 2); |
252b5132 RH |
10686 | litP += 2; |
10687 | } | |
10688 | } | |
10689 | else | |
10690 | { | |
10691 | for (i = 0; i < prec; i++) | |
10692 | { | |
17a2f251 | 10693 | md_number_to_chars (litP, words[i], 2); |
252b5132 RH |
10694 | litP += 2; |
10695 | } | |
10696 | } | |
bdaaa2e1 | 10697 | |
252b5132 RH |
10698 | return NULL; |
10699 | } | |
10700 | ||
10701 | void | |
17a2f251 | 10702 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
10703 | { |
10704 | if (target_big_endian) | |
10705 | number_to_chars_bigendian (buf, val, n); | |
10706 | else | |
10707 | number_to_chars_littleendian (buf, val, n); | |
10708 | } | |
10709 | \f | |
ae948b86 | 10710 | #ifdef OBJ_ELF |
e013f690 TS |
10711 | static int support_64bit_objects(void) |
10712 | { | |
10713 | const char **list, **l; | |
aa3d8fdf | 10714 | int yes; |
e013f690 TS |
10715 | |
10716 | list = bfd_target_list (); | |
10717 | for (l = list; *l != NULL; l++) | |
10718 | #ifdef TE_TMIPS | |
10719 | /* This is traditional mips */ | |
10720 | if (strcmp (*l, "elf64-tradbigmips") == 0 | |
10721 | || strcmp (*l, "elf64-tradlittlemips") == 0) | |
10722 | #else | |
10723 | if (strcmp (*l, "elf64-bigmips") == 0 | |
10724 | || strcmp (*l, "elf64-littlemips") == 0) | |
10725 | #endif | |
10726 | break; | |
aa3d8fdf | 10727 | yes = (*l != NULL); |
e013f690 | 10728 | free (list); |
aa3d8fdf | 10729 | return yes; |
e013f690 | 10730 | } |
ae948b86 | 10731 | #endif /* OBJ_ELF */ |
e013f690 | 10732 | |
78849248 | 10733 | const char *md_shortopts = "O::g::G:"; |
252b5132 | 10734 | |
e972090a NC |
10735 | struct option md_longopts[] = |
10736 | { | |
f9b4148d CD |
10737 | /* Options which specify architecture. */ |
10738 | #define OPTION_ARCH_BASE (OPTION_MD_BASE) | |
10739 | #define OPTION_MARCH (OPTION_ARCH_BASE + 0) | |
10740 | {"march", required_argument, NULL, OPTION_MARCH}, | |
10741 | #define OPTION_MTUNE (OPTION_ARCH_BASE + 1) | |
10742 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
10743 | #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2) | |
252b5132 RH |
10744 | {"mips0", no_argument, NULL, OPTION_MIPS1}, |
10745 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
f9b4148d | 10746 | #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3) |
252b5132 | 10747 | {"mips2", no_argument, NULL, OPTION_MIPS2}, |
f9b4148d | 10748 | #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4) |
252b5132 | 10749 | {"mips3", no_argument, NULL, OPTION_MIPS3}, |
f9b4148d | 10750 | #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5) |
252b5132 | 10751 | {"mips4", no_argument, NULL, OPTION_MIPS4}, |
f9b4148d | 10752 | #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6) |
ae948b86 | 10753 | {"mips5", no_argument, NULL, OPTION_MIPS5}, |
f9b4148d | 10754 | #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7) |
ae948b86 | 10755 | {"mips32", no_argument, NULL, OPTION_MIPS32}, |
f9b4148d | 10756 | #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8) |
ae948b86 | 10757 | {"mips64", no_argument, NULL, OPTION_MIPS64}, |
f9b4148d CD |
10758 | #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9) |
10759 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, | |
5f74bc13 CD |
10760 | #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10) |
10761 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, | |
f9b4148d CD |
10762 | |
10763 | /* Options which specify Application Specific Extensions (ASEs). */ | |
5f74bc13 | 10764 | #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11) |
f9b4148d CD |
10765 | #define OPTION_MIPS16 (OPTION_ASE_BASE + 0) |
10766 | {"mips16", no_argument, NULL, OPTION_MIPS16}, | |
10767 | #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1) | |
10768 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, | |
10769 | #define OPTION_MIPS3D (OPTION_ASE_BASE + 2) | |
10770 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, | |
10771 | #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3) | |
10772 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, | |
10773 | #define OPTION_MDMX (OPTION_ASE_BASE + 4) | |
10774 | {"mdmx", no_argument, NULL, OPTION_MDMX}, | |
10775 | #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5) | |
10776 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, | |
74cd071d CF |
10777 | #define OPTION_DSP (OPTION_ASE_BASE + 6) |
10778 | {"mdsp", no_argument, NULL, OPTION_DSP}, | |
10779 | #define OPTION_NO_DSP (OPTION_ASE_BASE + 7) | |
10780 | {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, | |
ef2e4d86 CF |
10781 | #define OPTION_MT (OPTION_ASE_BASE + 8) |
10782 | {"mmt", no_argument, NULL, OPTION_MT}, | |
10783 | #define OPTION_NO_MT (OPTION_ASE_BASE + 9) | |
10784 | {"mno-mt", no_argument, NULL, OPTION_NO_MT}, | |
e16bfa71 TS |
10785 | #define OPTION_SMARTMIPS (OPTION_ASE_BASE + 10) |
10786 | {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS}, | |
10787 | #define OPTION_NO_SMARTMIPS (OPTION_ASE_BASE + 11) | |
10788 | {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS}, | |
f9b4148d CD |
10789 | |
10790 | /* Old-style architecture options. Don't add more of these. */ | |
e16bfa71 | 10791 | #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 12) |
f9b4148d CD |
10792 | #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0) |
10793 | {"m4650", no_argument, NULL, OPTION_M4650}, | |
10794 | #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1) | |
10795 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, | |
10796 | #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2) | |
10797 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
10798 | #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3) | |
10799 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
10800 | #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4) | |
10801 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
10802 | #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5) | |
10803 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
10804 | #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6) | |
10805 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
10806 | #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7) | |
10807 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
10808 | ||
10809 | /* Options which enable bug fixes. */ | |
10810 | #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8) | |
10811 | #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0) | |
10812 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, | |
10813 | #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1) | |
10814 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
10815 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
d766e8ec RS |
10816 | #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2) |
10817 | #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3) | |
10818 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, | |
10819 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
7d8e00cf RS |
10820 | #define OPTION_FIX_VR4130 (OPTION_FIX_BASE + 4) |
10821 | #define OPTION_NO_FIX_VR4130 (OPTION_FIX_BASE + 5) | |
10822 | {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, | |
10823 | {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, | |
f9b4148d CD |
10824 | |
10825 | /* Miscellaneous options. */ | |
7d8e00cf | 10826 | #define OPTION_MISC_BASE (OPTION_FIX_BASE + 6) |
1ffcab4b | 10827 | #define OPTION_TRAP (OPTION_MISC_BASE + 0) |
252b5132 RH |
10828 | {"trap", no_argument, NULL, OPTION_TRAP}, |
10829 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
1ffcab4b | 10830 | #define OPTION_BREAK (OPTION_MISC_BASE + 1) |
252b5132 RH |
10831 | {"break", no_argument, NULL, OPTION_BREAK}, |
10832 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
1ffcab4b | 10833 | #define OPTION_EB (OPTION_MISC_BASE + 2) |
252b5132 | 10834 | {"EB", no_argument, NULL, OPTION_EB}, |
1ffcab4b | 10835 | #define OPTION_EL (OPTION_MISC_BASE + 3) |
252b5132 | 10836 | {"EL", no_argument, NULL, OPTION_EL}, |
1ffcab4b | 10837 | #define OPTION_FP32 (OPTION_MISC_BASE + 4) |
ae948b86 | 10838 | {"mfp32", no_argument, NULL, OPTION_FP32}, |
1ffcab4b | 10839 | #define OPTION_GP32 (OPTION_MISC_BASE + 5) |
c97ef257 | 10840 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
1ffcab4b | 10841 | #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6) |
119d663a | 10842 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
1ffcab4b | 10843 | #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7) |
119d663a | 10844 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
1ffcab4b | 10845 | #define OPTION_FP64 (OPTION_MISC_BASE + 8) |
316f5878 | 10846 | {"mfp64", no_argument, NULL, OPTION_FP64}, |
1ffcab4b | 10847 | #define OPTION_GP64 (OPTION_MISC_BASE + 9) |
ae948b86 | 10848 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
1ffcab4b CD |
10849 | #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10) |
10850 | #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11) | |
4a6a3df4 AO |
10851 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, |
10852 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
aa6975fb ILT |
10853 | #define OPTION_MSHARED (OPTION_MISC_BASE + 12) |
10854 | #define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13) | |
10855 | {"mshared", no_argument, NULL, OPTION_MSHARED}, | |
10856 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
aed1a261 RS |
10857 | #define OPTION_MSYM32 (OPTION_MISC_BASE + 14) |
10858 | #define OPTION_MNO_SYM32 (OPTION_MISC_BASE + 15) | |
10859 | {"msym32", no_argument, NULL, OPTION_MSYM32}, | |
10860 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, | |
f9b4148d CD |
10861 | |
10862 | /* ELF-specific options. */ | |
156c2f8b | 10863 | #ifdef OBJ_ELF |
aed1a261 | 10864 | #define OPTION_ELF_BASE (OPTION_MISC_BASE + 16) |
156c2f8b | 10865 | #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0) |
156c2f8b NC |
10866 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
10867 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
ae948b86 | 10868 | #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1) |
156c2f8b | 10869 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
ae948b86 | 10870 | #define OPTION_XGOT (OPTION_ELF_BASE + 2) |
156c2f8b | 10871 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
ae948b86 TS |
10872 | #define OPTION_MABI (OPTION_ELF_BASE + 3) |
10873 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
10874 | #define OPTION_32 (OPTION_ELF_BASE + 4) | |
156c2f8b | 10875 | {"32", no_argument, NULL, OPTION_32}, |
ae948b86 | 10876 | #define OPTION_N32 (OPTION_ELF_BASE + 5) |
e013f690 | 10877 | {"n32", no_argument, NULL, OPTION_N32}, |
ae948b86 | 10878 | #define OPTION_64 (OPTION_ELF_BASE + 6) |
156c2f8b | 10879 | {"64", no_argument, NULL, OPTION_64}, |
ecb4347a DJ |
10880 | #define OPTION_MDEBUG (OPTION_ELF_BASE + 7) |
10881 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, | |
10882 | #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8) | |
10883 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, | |
dcd410fe RO |
10884 | #define OPTION_PDR (OPTION_ELF_BASE + 9) |
10885 | {"mpdr", no_argument, NULL, OPTION_PDR}, | |
10886 | #define OPTION_NO_PDR (OPTION_ELF_BASE + 10) | |
10887 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, | |
0a44bf69 RS |
10888 | #define OPTION_MVXWORKS_PIC (OPTION_ELF_BASE + 11) |
10889 | {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, | |
ae948b86 | 10890 | #endif /* OBJ_ELF */ |
f9b4148d | 10891 | |
252b5132 RH |
10892 | {NULL, no_argument, NULL, 0} |
10893 | }; | |
156c2f8b | 10894 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 10895 | |
316f5878 RS |
10896 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
10897 | NEW_VALUE. Warn if another value was already specified. Note: | |
10898 | we have to defer parsing the -march and -mtune arguments in order | |
10899 | to handle 'from-abi' correctly, since the ABI might be specified | |
10900 | in a later argument. */ | |
10901 | ||
10902 | static void | |
17a2f251 | 10903 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
10904 | { |
10905 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
10906 | as_warn (_("A different %s was already specified, is now %s"), | |
10907 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
10908 | new_value); | |
10909 | ||
10910 | *string_ptr = new_value; | |
10911 | } | |
10912 | ||
252b5132 | 10913 | int |
17a2f251 | 10914 | md_parse_option (int c, char *arg) |
252b5132 RH |
10915 | { |
10916 | switch (c) | |
10917 | { | |
119d663a NC |
10918 | case OPTION_CONSTRUCT_FLOATS: |
10919 | mips_disable_float_construction = 0; | |
10920 | break; | |
bdaaa2e1 | 10921 | |
119d663a NC |
10922 | case OPTION_NO_CONSTRUCT_FLOATS: |
10923 | mips_disable_float_construction = 1; | |
10924 | break; | |
bdaaa2e1 | 10925 | |
252b5132 RH |
10926 | case OPTION_TRAP: |
10927 | mips_trap = 1; | |
10928 | break; | |
10929 | ||
10930 | case OPTION_BREAK: | |
10931 | mips_trap = 0; | |
10932 | break; | |
10933 | ||
10934 | case OPTION_EB: | |
10935 | target_big_endian = 1; | |
10936 | break; | |
10937 | ||
10938 | case OPTION_EL: | |
10939 | target_big_endian = 0; | |
10940 | break; | |
10941 | ||
10942 | case 'O': | |
10943 | if (arg && arg[1] == '0') | |
10944 | mips_optimize = 1; | |
10945 | else | |
10946 | mips_optimize = 2; | |
10947 | break; | |
10948 | ||
10949 | case 'g': | |
10950 | if (arg == NULL) | |
10951 | mips_debug = 2; | |
10952 | else | |
10953 | mips_debug = atoi (arg); | |
10954 | /* When the MIPS assembler sees -g or -g2, it does not do | |
10955 | optimizations which limit full symbolic debugging. We take | |
10956 | that to be equivalent to -O0. */ | |
10957 | if (mips_debug == 2) | |
10958 | mips_optimize = 1; | |
10959 | break; | |
10960 | ||
10961 | case OPTION_MIPS1: | |
316f5878 | 10962 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
10963 | break; |
10964 | ||
10965 | case OPTION_MIPS2: | |
316f5878 | 10966 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
10967 | break; |
10968 | ||
10969 | case OPTION_MIPS3: | |
316f5878 | 10970 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
10971 | break; |
10972 | ||
10973 | case OPTION_MIPS4: | |
316f5878 | 10974 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
10975 | break; |
10976 | ||
84ea6cf2 | 10977 | case OPTION_MIPS5: |
316f5878 | 10978 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
10979 | break; |
10980 | ||
e7af610e | 10981 | case OPTION_MIPS32: |
316f5878 | 10982 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
10983 | break; |
10984 | ||
af7ee8bf CD |
10985 | case OPTION_MIPS32R2: |
10986 | file_mips_isa = ISA_MIPS32R2; | |
10987 | break; | |
10988 | ||
5f74bc13 CD |
10989 | case OPTION_MIPS64R2: |
10990 | file_mips_isa = ISA_MIPS64R2; | |
10991 | break; | |
10992 | ||
84ea6cf2 | 10993 | case OPTION_MIPS64: |
316f5878 | 10994 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
10995 | break; |
10996 | ||
ec68c924 | 10997 | case OPTION_MTUNE: |
316f5878 RS |
10998 | mips_set_option_string (&mips_tune_string, arg); |
10999 | break; | |
ec68c924 | 11000 | |
316f5878 RS |
11001 | case OPTION_MARCH: |
11002 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
11003 | break; |
11004 | ||
11005 | case OPTION_M4650: | |
316f5878 RS |
11006 | mips_set_option_string (&mips_arch_string, "4650"); |
11007 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
11008 | break; |
11009 | ||
11010 | case OPTION_NO_M4650: | |
11011 | break; | |
11012 | ||
11013 | case OPTION_M4010: | |
316f5878 RS |
11014 | mips_set_option_string (&mips_arch_string, "4010"); |
11015 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
11016 | break; |
11017 | ||
11018 | case OPTION_NO_M4010: | |
11019 | break; | |
11020 | ||
11021 | case OPTION_M4100: | |
316f5878 RS |
11022 | mips_set_option_string (&mips_arch_string, "4100"); |
11023 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
11024 | break; |
11025 | ||
11026 | case OPTION_NO_M4100: | |
11027 | break; | |
11028 | ||
252b5132 | 11029 | case OPTION_M3900: |
316f5878 RS |
11030 | mips_set_option_string (&mips_arch_string, "3900"); |
11031 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 11032 | break; |
bdaaa2e1 | 11033 | |
252b5132 RH |
11034 | case OPTION_NO_M3900: |
11035 | break; | |
11036 | ||
deec1734 CD |
11037 | case OPTION_MDMX: |
11038 | mips_opts.ase_mdmx = 1; | |
11039 | break; | |
11040 | ||
11041 | case OPTION_NO_MDMX: | |
11042 | mips_opts.ase_mdmx = 0; | |
11043 | break; | |
11044 | ||
74cd071d CF |
11045 | case OPTION_DSP: |
11046 | mips_opts.ase_dsp = 1; | |
11047 | break; | |
11048 | ||
11049 | case OPTION_NO_DSP: | |
11050 | mips_opts.ase_dsp = 0; | |
11051 | break; | |
11052 | ||
ef2e4d86 CF |
11053 | case OPTION_MT: |
11054 | mips_opts.ase_mt = 1; | |
11055 | break; | |
11056 | ||
11057 | case OPTION_NO_MT: | |
11058 | mips_opts.ase_mt = 0; | |
11059 | break; | |
11060 | ||
252b5132 RH |
11061 | case OPTION_MIPS16: |
11062 | mips_opts.mips16 = 1; | |
7d10b47d | 11063 | mips_no_prev_insn (); |
252b5132 RH |
11064 | break; |
11065 | ||
11066 | case OPTION_NO_MIPS16: | |
11067 | mips_opts.mips16 = 0; | |
7d10b47d | 11068 | mips_no_prev_insn (); |
252b5132 RH |
11069 | break; |
11070 | ||
1f25f5d3 CD |
11071 | case OPTION_MIPS3D: |
11072 | mips_opts.ase_mips3d = 1; | |
11073 | break; | |
11074 | ||
11075 | case OPTION_NO_MIPS3D: | |
11076 | mips_opts.ase_mips3d = 0; | |
11077 | break; | |
11078 | ||
e16bfa71 TS |
11079 | case OPTION_SMARTMIPS: |
11080 | mips_opts.ase_smartmips = 1; | |
11081 | break; | |
11082 | ||
11083 | case OPTION_NO_SMARTMIPS: | |
11084 | mips_opts.ase_smartmips = 0; | |
11085 | break; | |
11086 | ||
d766e8ec RS |
11087 | case OPTION_FIX_VR4120: |
11088 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
11089 | break; |
11090 | ||
d766e8ec RS |
11091 | case OPTION_NO_FIX_VR4120: |
11092 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
11093 | break; |
11094 | ||
7d8e00cf RS |
11095 | case OPTION_FIX_VR4130: |
11096 | mips_fix_vr4130 = 1; | |
11097 | break; | |
11098 | ||
11099 | case OPTION_NO_FIX_VR4130: | |
11100 | mips_fix_vr4130 = 0; | |
11101 | break; | |
11102 | ||
4a6a3df4 AO |
11103 | case OPTION_RELAX_BRANCH: |
11104 | mips_relax_branch = 1; | |
11105 | break; | |
11106 | ||
11107 | case OPTION_NO_RELAX_BRANCH: | |
11108 | mips_relax_branch = 0; | |
11109 | break; | |
11110 | ||
aa6975fb ILT |
11111 | case OPTION_MSHARED: |
11112 | mips_in_shared = TRUE; | |
11113 | break; | |
11114 | ||
11115 | case OPTION_MNO_SHARED: | |
11116 | mips_in_shared = FALSE; | |
11117 | break; | |
11118 | ||
aed1a261 RS |
11119 | case OPTION_MSYM32: |
11120 | mips_opts.sym32 = TRUE; | |
11121 | break; | |
11122 | ||
11123 | case OPTION_MNO_SYM32: | |
11124 | mips_opts.sym32 = FALSE; | |
11125 | break; | |
11126 | ||
0f074f60 | 11127 | #ifdef OBJ_ELF |
252b5132 RH |
11128 | /* When generating ELF code, we permit -KPIC and -call_shared to |
11129 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
11130 | intended to be compatible with Irix 5. */ | |
11131 | case OPTION_CALL_SHARED: | |
11132 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
11133 | { | |
11134 | as_bad (_("-call_shared is supported only for ELF format")); | |
11135 | return 0; | |
11136 | } | |
11137 | mips_pic = SVR4_PIC; | |
143d77c5 | 11138 | mips_abicalls = TRUE; |
252b5132 RH |
11139 | break; |
11140 | ||
11141 | case OPTION_NON_SHARED: | |
11142 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
11143 | { | |
11144 | as_bad (_("-non_shared is supported only for ELF format")); | |
11145 | return 0; | |
11146 | } | |
11147 | mips_pic = NO_PIC; | |
143d77c5 | 11148 | mips_abicalls = FALSE; |
252b5132 RH |
11149 | break; |
11150 | ||
44075ae2 TS |
11151 | /* The -xgot option tells the assembler to use 32 bit offsets |
11152 | when accessing the got in SVR4_PIC mode. It is for Irix | |
252b5132 RH |
11153 | compatibility. */ |
11154 | case OPTION_XGOT: | |
11155 | mips_big_got = 1; | |
11156 | break; | |
0f074f60 | 11157 | #endif /* OBJ_ELF */ |
252b5132 RH |
11158 | |
11159 | case 'G': | |
6caf9ef4 TS |
11160 | g_switch_value = atoi (arg); |
11161 | g_switch_seen = 1; | |
252b5132 RH |
11162 | break; |
11163 | ||
0f074f60 | 11164 | #ifdef OBJ_ELF |
34ba82a8 TS |
11165 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
11166 | and -mabi=64. */ | |
252b5132 | 11167 | case OPTION_32: |
34ba82a8 TS |
11168 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
11169 | { | |
11170 | as_bad (_("-32 is supported for ELF format only")); | |
11171 | return 0; | |
11172 | } | |
316f5878 | 11173 | mips_abi = O32_ABI; |
252b5132 RH |
11174 | break; |
11175 | ||
e013f690 | 11176 | case OPTION_N32: |
34ba82a8 TS |
11177 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
11178 | { | |
11179 | as_bad (_("-n32 is supported for ELF format only")); | |
11180 | return 0; | |
11181 | } | |
316f5878 | 11182 | mips_abi = N32_ABI; |
e013f690 | 11183 | break; |
252b5132 | 11184 | |
e013f690 | 11185 | case OPTION_64: |
34ba82a8 TS |
11186 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
11187 | { | |
11188 | as_bad (_("-64 is supported for ELF format only")); | |
11189 | return 0; | |
11190 | } | |
316f5878 | 11191 | mips_abi = N64_ABI; |
e013f690 TS |
11192 | if (! support_64bit_objects()) |
11193 | as_fatal (_("No compiled in support for 64 bit object file format")); | |
252b5132 | 11194 | break; |
ae948b86 | 11195 | #endif /* OBJ_ELF */ |
252b5132 | 11196 | |
c97ef257 | 11197 | case OPTION_GP32: |
a325df1d | 11198 | file_mips_gp32 = 1; |
c97ef257 AH |
11199 | break; |
11200 | ||
11201 | case OPTION_GP64: | |
a325df1d | 11202 | file_mips_gp32 = 0; |
c97ef257 | 11203 | break; |
252b5132 | 11204 | |
ca4e0257 | 11205 | case OPTION_FP32: |
a325df1d | 11206 | file_mips_fp32 = 1; |
316f5878 RS |
11207 | break; |
11208 | ||
11209 | case OPTION_FP64: | |
11210 | file_mips_fp32 = 0; | |
ca4e0257 RS |
11211 | break; |
11212 | ||
ae948b86 | 11213 | #ifdef OBJ_ELF |
252b5132 | 11214 | case OPTION_MABI: |
34ba82a8 TS |
11215 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
11216 | { | |
11217 | as_bad (_("-mabi is supported for ELF format only")); | |
11218 | return 0; | |
11219 | } | |
e013f690 | 11220 | if (strcmp (arg, "32") == 0) |
316f5878 | 11221 | mips_abi = O32_ABI; |
e013f690 | 11222 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 11223 | mips_abi = O64_ABI; |
e013f690 | 11224 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 11225 | mips_abi = N32_ABI; |
e013f690 TS |
11226 | else if (strcmp (arg, "64") == 0) |
11227 | { | |
316f5878 | 11228 | mips_abi = N64_ABI; |
e013f690 TS |
11229 | if (! support_64bit_objects()) |
11230 | as_fatal (_("No compiled in support for 64 bit object file " | |
11231 | "format")); | |
11232 | } | |
11233 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 11234 | mips_abi = EABI_ABI; |
e013f690 | 11235 | else |
da0e507f TS |
11236 | { |
11237 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
11238 | return 0; | |
11239 | } | |
252b5132 | 11240 | break; |
e013f690 | 11241 | #endif /* OBJ_ELF */ |
252b5132 | 11242 | |
6b76fefe | 11243 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 11244 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
11245 | break; |
11246 | ||
9ee72ff1 | 11247 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 11248 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
11249 | break; |
11250 | ||
ecb4347a DJ |
11251 | #ifdef OBJ_ELF |
11252 | case OPTION_MDEBUG: | |
b34976b6 | 11253 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
11254 | break; |
11255 | ||
11256 | case OPTION_NO_MDEBUG: | |
b34976b6 | 11257 | mips_flag_mdebug = FALSE; |
ecb4347a | 11258 | break; |
dcd410fe RO |
11259 | |
11260 | case OPTION_PDR: | |
11261 | mips_flag_pdr = TRUE; | |
11262 | break; | |
11263 | ||
11264 | case OPTION_NO_PDR: | |
11265 | mips_flag_pdr = FALSE; | |
11266 | break; | |
0a44bf69 RS |
11267 | |
11268 | case OPTION_MVXWORKS_PIC: | |
11269 | mips_pic = VXWORKS_PIC; | |
11270 | break; | |
ecb4347a DJ |
11271 | #endif /* OBJ_ELF */ |
11272 | ||
252b5132 RH |
11273 | default: |
11274 | return 0; | |
11275 | } | |
11276 | ||
11277 | return 1; | |
11278 | } | |
316f5878 RS |
11279 | \f |
11280 | /* Set up globals to generate code for the ISA or processor | |
11281 | described by INFO. */ | |
252b5132 | 11282 | |
252b5132 | 11283 | static void |
17a2f251 | 11284 | mips_set_architecture (const struct mips_cpu_info *info) |
252b5132 | 11285 | { |
316f5878 | 11286 | if (info != 0) |
252b5132 | 11287 | { |
fef14a42 TS |
11288 | file_mips_arch = info->cpu; |
11289 | mips_opts.arch = info->cpu; | |
316f5878 | 11290 | mips_opts.isa = info->isa; |
252b5132 | 11291 | } |
252b5132 RH |
11292 | } |
11293 | ||
252b5132 | 11294 | |
316f5878 | 11295 | /* Likewise for tuning. */ |
252b5132 | 11296 | |
316f5878 | 11297 | static void |
17a2f251 | 11298 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
11299 | { |
11300 | if (info != 0) | |
fef14a42 | 11301 | mips_tune = info->cpu; |
316f5878 | 11302 | } |
80cc45a5 | 11303 | |
34ba82a8 | 11304 | |
252b5132 | 11305 | void |
17a2f251 | 11306 | mips_after_parse_args (void) |
e9670677 | 11307 | { |
fef14a42 TS |
11308 | const struct mips_cpu_info *arch_info = 0; |
11309 | const struct mips_cpu_info *tune_info = 0; | |
11310 | ||
e9670677 | 11311 | /* GP relative stuff not working for PE */ |
6caf9ef4 | 11312 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
e9670677 | 11313 | { |
6caf9ef4 | 11314 | if (g_switch_seen && g_switch_value != 0) |
e9670677 MR |
11315 | as_bad (_("-G not supported in this configuration.")); |
11316 | g_switch_value = 0; | |
11317 | } | |
11318 | ||
cac012d6 AO |
11319 | if (mips_abi == NO_ABI) |
11320 | mips_abi = MIPS_DEFAULT_ABI; | |
11321 | ||
22923709 RS |
11322 | /* The following code determines the architecture and register size. |
11323 | Similar code was added to GCC 3.3 (see override_options() in | |
11324 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
11325 | as much as possible. */ | |
e9670677 | 11326 | |
316f5878 | 11327 | if (mips_arch_string != 0) |
fef14a42 | 11328 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 11329 | |
316f5878 | 11330 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 11331 | { |
316f5878 | 11332 | /* Handle -mipsN. At this point, file_mips_isa contains the |
fef14a42 | 11333 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 11334 | the -march selection (if any). */ |
fef14a42 | 11335 | if (arch_info != 0) |
e9670677 | 11336 | { |
316f5878 RS |
11337 | /* -march takes precedence over -mipsN, since it is more descriptive. |
11338 | There's no harm in specifying both as long as the ISA levels | |
11339 | are the same. */ | |
fef14a42 | 11340 | if (file_mips_isa != arch_info->isa) |
316f5878 RS |
11341 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), |
11342 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
fef14a42 | 11343 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 11344 | } |
316f5878 | 11345 | else |
fef14a42 | 11346 | arch_info = mips_cpu_info_from_isa (file_mips_isa); |
e9670677 MR |
11347 | } |
11348 | ||
fef14a42 TS |
11349 | if (arch_info == 0) |
11350 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
e9670677 | 11351 | |
fef14a42 | 11352 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
316f5878 | 11353 | as_bad ("-march=%s is not compatible with the selected ABI", |
fef14a42 TS |
11354 | arch_info->name); |
11355 | ||
11356 | mips_set_architecture (arch_info); | |
11357 | ||
11358 | /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ | |
11359 | if (mips_tune_string != 0) | |
11360 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 11361 | |
fef14a42 TS |
11362 | if (tune_info == 0) |
11363 | mips_set_tune (arch_info); | |
11364 | else | |
11365 | mips_set_tune (tune_info); | |
e9670677 | 11366 | |
316f5878 | 11367 | if (file_mips_gp32 >= 0) |
e9670677 | 11368 | { |
316f5878 RS |
11369 | /* The user specified the size of the integer registers. Make sure |
11370 | it agrees with the ABI and ISA. */ | |
11371 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
11372 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
11373 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
11374 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
11375 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
11376 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
11377 | } |
11378 | else | |
11379 | { | |
316f5878 RS |
11380 | /* Infer the integer register size from the ABI and processor. |
11381 | Restrict ourselves to 32-bit registers if that's all the | |
11382 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
11383 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
11384 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
11385 | } |
11386 | ||
ad3fea08 TS |
11387 | switch (file_mips_fp32) |
11388 | { | |
11389 | default: | |
11390 | case -1: | |
11391 | /* No user specified float register size. | |
11392 | ??? GAS treats single-float processors as though they had 64-bit | |
11393 | float registers (although it complains when double-precision | |
11394 | instructions are used). As things stand, saying they have 32-bit | |
11395 | registers would lead to spurious "register must be even" messages. | |
11396 | So here we assume float registers are never smaller than the | |
11397 | integer ones. */ | |
11398 | if (file_mips_gp32 == 0) | |
11399 | /* 64-bit integer registers implies 64-bit float registers. */ | |
11400 | file_mips_fp32 = 0; | |
11401 | else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0) | |
11402 | && ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
11403 | /* -mips3d and -mdmx imply 64-bit float registers, if possible. */ | |
11404 | file_mips_fp32 = 0; | |
11405 | else | |
11406 | /* 32-bit float registers. */ | |
11407 | file_mips_fp32 = 1; | |
11408 | break; | |
11409 | ||
11410 | /* The user specified the size of the float registers. Check if it | |
11411 | agrees with the ABI and ISA. */ | |
11412 | case 0: | |
11413 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
11414 | as_bad (_("-mfp64 used with a 32-bit fpu")); | |
11415 | else if (ABI_NEEDS_32BIT_REGS (mips_abi) | |
11416 | && !ISA_HAS_MXHC1 (mips_opts.isa)) | |
11417 | as_warn (_("-mfp64 used with a 32-bit ABI")); | |
11418 | break; | |
11419 | case 1: | |
11420 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
11421 | as_warn (_("-mfp32 used with a 64-bit ABI")); | |
11422 | break; | |
11423 | } | |
e9670677 | 11424 | |
316f5878 | 11425 | /* End of GCC-shared inference code. */ |
e9670677 | 11426 | |
17a2f251 TS |
11427 | /* This flag is set when we have a 64-bit capable CPU but use only |
11428 | 32-bit wide registers. Note that EABI does not use it. */ | |
11429 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) | |
11430 | && ((mips_abi == NO_ABI && file_mips_gp32 == 1) | |
11431 | || mips_abi == O32_ABI)) | |
316f5878 | 11432 | mips_32bitmode = 1; |
e9670677 MR |
11433 | |
11434 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
11435 | as_bad (_("trap exception not supported at ISA 1")); | |
11436 | ||
e9670677 MR |
11437 | /* If the selected architecture includes support for ASEs, enable |
11438 | generation of code for them. */ | |
a4672219 | 11439 | if (mips_opts.mips16 == -1) |
fef14a42 | 11440 | mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 11441 | if (mips_opts.ase_mips3d == -1) |
65263ce3 | 11442 | mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D) |
ad3fea08 TS |
11443 | && file_mips_fp32 == 0) ? 1 : 0; |
11444 | if (mips_opts.ase_mips3d && file_mips_fp32 == 1) | |
11445 | as_bad (_("-mfp32 used with -mips3d")); | |
11446 | ||
ffdefa66 | 11447 | if (mips_opts.ase_mdmx == -1) |
65263ce3 | 11448 | mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX) |
ad3fea08 TS |
11449 | && file_mips_fp32 == 0) ? 1 : 0; |
11450 | if (mips_opts.ase_mdmx && file_mips_fp32 == 1) | |
11451 | as_bad (_("-mfp32 used with -mdmx")); | |
11452 | ||
11453 | if (mips_opts.ase_smartmips == -1) | |
11454 | mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0; | |
11455 | if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS) | |
11456 | as_warn ("%s ISA does not support SmartMIPS", | |
11457 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
11458 | ||
74cd071d | 11459 | if (mips_opts.ase_dsp == -1) |
ad3fea08 TS |
11460 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; |
11461 | if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE) | |
11462 | as_warn ("%s ISA does not support DSP ASE", | |
11463 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
11464 | ||
ef2e4d86 | 11465 | if (mips_opts.ase_mt == -1) |
ad3fea08 TS |
11466 | mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0; |
11467 | if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE) | |
11468 | as_warn ("%s ISA does not support MT ASE", | |
11469 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
e9670677 | 11470 | |
e9670677 | 11471 | file_mips_isa = mips_opts.isa; |
a4672219 | 11472 | file_ase_mips16 = mips_opts.mips16; |
e9670677 MR |
11473 | file_ase_mips3d = mips_opts.ase_mips3d; |
11474 | file_ase_mdmx = mips_opts.ase_mdmx; | |
e16bfa71 | 11475 | file_ase_smartmips = mips_opts.ase_smartmips; |
74cd071d | 11476 | file_ase_dsp = mips_opts.ase_dsp; |
ef2e4d86 | 11477 | file_ase_mt = mips_opts.ase_mt; |
e9670677 MR |
11478 | mips_opts.gp32 = file_mips_gp32; |
11479 | mips_opts.fp32 = file_mips_fp32; | |
11480 | ||
ecb4347a DJ |
11481 | if (mips_flag_mdebug < 0) |
11482 | { | |
11483 | #ifdef OBJ_MAYBE_ECOFF | |
11484 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) | |
11485 | mips_flag_mdebug = 1; | |
11486 | else | |
11487 | #endif /* OBJ_MAYBE_ECOFF */ | |
11488 | mips_flag_mdebug = 0; | |
11489 | } | |
e9670677 MR |
11490 | } |
11491 | \f | |
11492 | void | |
17a2f251 | 11493 | mips_init_after_args (void) |
252b5132 RH |
11494 | { |
11495 | /* initialize opcodes */ | |
11496 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 11497 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
11498 | } |
11499 | ||
11500 | long | |
17a2f251 | 11501 | md_pcrel_from (fixS *fixP) |
252b5132 | 11502 | { |
a7ebbfdf TS |
11503 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
11504 | switch (fixP->fx_r_type) | |
11505 | { | |
11506 | case BFD_RELOC_16_PCREL_S2: | |
11507 | case BFD_RELOC_MIPS_JMP: | |
11508 | /* Return the address of the delay slot. */ | |
11509 | return addr + 4; | |
11510 | default: | |
11511 | return addr; | |
11512 | } | |
252b5132 RH |
11513 | } |
11514 | ||
252b5132 RH |
11515 | /* This is called before the symbol table is processed. In order to |
11516 | work with gcc when using mips-tfile, we must keep all local labels. | |
11517 | However, in other cases, we want to discard them. If we were | |
11518 | called with -g, but we didn't see any debugging information, it may | |
11519 | mean that gcc is smuggling debugging information through to | |
11520 | mips-tfile, in which case we must generate all local labels. */ | |
11521 | ||
11522 | void | |
17a2f251 | 11523 | mips_frob_file_before_adjust (void) |
252b5132 RH |
11524 | { |
11525 | #ifndef NO_ECOFF_DEBUGGING | |
11526 | if (ECOFF_DEBUGGING | |
11527 | && mips_debug != 0 | |
11528 | && ! ecoff_debugging_seen) | |
11529 | flag_keep_locals = 1; | |
11530 | #endif | |
11531 | } | |
11532 | ||
3b91255e | 11533 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
55cf6793 | 11534 | the corresponding LO16 reloc. This is called before md_apply_fix and |
3b91255e RS |
11535 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit |
11536 | relocation operators. | |
11537 | ||
11538 | For our purposes, a %lo() expression matches a %got() or %hi() | |
11539 | expression if: | |
11540 | ||
11541 | (a) it refers to the same symbol; and | |
11542 | (b) the offset applied in the %lo() expression is no lower than | |
11543 | the offset applied in the %got() or %hi(). | |
11544 | ||
11545 | (b) allows us to cope with code like: | |
11546 | ||
11547 | lui $4,%hi(foo) | |
11548 | lh $4,%lo(foo+2)($4) | |
11549 | ||
11550 | ...which is legal on RELA targets, and has a well-defined behaviour | |
11551 | if the user knows that adding 2 to "foo" will not induce a carry to | |
11552 | the high 16 bits. | |
11553 | ||
11554 | When several %lo()s match a particular %got() or %hi(), we use the | |
11555 | following rules to distinguish them: | |
11556 | ||
11557 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
11558 | higher offsets. | |
11559 | ||
11560 | (2) %lo()s with no matching %got() or %hi() are better than those | |
11561 | that already have a matching %got() or %hi(). | |
11562 | ||
11563 | (3) later %lo()s are better than earlier %lo()s. | |
11564 | ||
11565 | These rules are applied in order. | |
11566 | ||
11567 | (1) means, among other things, that %lo()s with identical offsets are | |
11568 | chosen if they exist. | |
11569 | ||
11570 | (2) means that we won't associate several high-part relocations with | |
11571 | the same low-part relocation unless there's no alternative. Having | |
11572 | several high parts for the same low part is a GNU extension; this rule | |
11573 | allows careful users to avoid it. | |
11574 | ||
11575 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
11576 | with the last high-part relocation being at the front of the list. | |
11577 | It therefore makes sense to choose the last matching low-part | |
11578 | relocation, all other things being equal. It's also easier | |
11579 | to code that way. */ | |
252b5132 RH |
11580 | |
11581 | void | |
17a2f251 | 11582 | mips_frob_file (void) |
252b5132 RH |
11583 | { |
11584 | struct mips_hi_fixup *l; | |
11585 | ||
11586 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
11587 | { | |
11588 | segment_info_type *seginfo; | |
3b91255e RS |
11589 | bfd_boolean matched_lo_p; |
11590 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 11591 | |
5919d012 | 11592 | assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 11593 | |
5919d012 RS |
11594 | /* If a GOT16 relocation turns out to be against a global symbol, |
11595 | there isn't supposed to be a matching LO. */ | |
11596 | if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
11597 | && !pic_need_relax (l->fixp->fx_addsy, l->seg)) | |
11598 | continue; | |
11599 | ||
11600 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
11601 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
11602 | continue; |
11603 | ||
252b5132 | 11604 | seginfo = seg_info (l->seg); |
252b5132 | 11605 | |
3b91255e RS |
11606 | /* Set HI_POS to the position of this relocation in the chain. |
11607 | Set LO_POS to the position of the chosen low-part relocation. | |
11608 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
11609 | relocation that matches an immediately-preceding high-part | |
11610 | relocation. */ | |
11611 | hi_pos = NULL; | |
11612 | lo_pos = NULL; | |
11613 | matched_lo_p = FALSE; | |
11614 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) | |
11615 | { | |
11616 | if (*pos == l->fixp) | |
11617 | hi_pos = pos; | |
11618 | ||
704803a9 MR |
11619 | if (((*pos)->fx_r_type == BFD_RELOC_LO16 |
11620 | || (*pos)->fx_r_type == BFD_RELOC_MIPS16_LO16) | |
3b91255e RS |
11621 | && (*pos)->fx_addsy == l->fixp->fx_addsy |
11622 | && (*pos)->fx_offset >= l->fixp->fx_offset | |
11623 | && (lo_pos == NULL | |
11624 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
11625 | || (!matched_lo_p | |
11626 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
11627 | lo_pos = pos; | |
11628 | ||
11629 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
11630 | && fixup_has_matching_lo_p (*pos)); | |
11631 | } | |
11632 | ||
11633 | /* If we found a match, remove the high-part relocation from its | |
11634 | current position and insert it before the low-part relocation. | |
11635 | Make the offsets match so that fixup_has_matching_lo_p() | |
11636 | will return true. | |
11637 | ||
11638 | We don't warn about unmatched high-part relocations since some | |
11639 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
11640 | instructions. */ | |
11641 | if (lo_pos != NULL) | |
11642 | { | |
11643 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
11644 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 11645 | { |
3b91255e RS |
11646 | *hi_pos = l->fixp->fx_next; |
11647 | l->fixp->fx_next = *lo_pos; | |
11648 | *lo_pos = l->fixp; | |
252b5132 | 11649 | } |
252b5132 RH |
11650 | } |
11651 | } | |
11652 | } | |
11653 | ||
3e722fb5 | 11654 | /* We may have combined relocations without symbols in the N32/N64 ABI. |
f6688943 | 11655 | We have to prevent gas from dropping them. */ |
252b5132 | 11656 | |
252b5132 | 11657 | int |
17a2f251 | 11658 | mips_force_relocation (fixS *fixp) |
252b5132 | 11659 | { |
ae6063d4 | 11660 | if (generic_force_reloc (fixp)) |
252b5132 RH |
11661 | return 1; |
11662 | ||
f6688943 TS |
11663 | if (HAVE_NEWABI |
11664 | && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr | |
11665 | && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB | |
11666 | || fixp->fx_r_type == BFD_RELOC_HI16_S | |
11667 | || fixp->fx_r_type == BFD_RELOC_LO16)) | |
11668 | return 1; | |
11669 | ||
3e722fb5 | 11670 | return 0; |
252b5132 RH |
11671 | } |
11672 | ||
11673 | /* Apply a fixup to the object file. */ | |
11674 | ||
94f592af | 11675 | void |
55cf6793 | 11676 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 11677 | { |
874e8986 | 11678 | bfd_byte *buf; |
98aa84af | 11679 | long insn; |
a7ebbfdf | 11680 | reloc_howto_type *howto; |
252b5132 | 11681 | |
a7ebbfdf TS |
11682 | /* We ignore generic BFD relocations we don't know about. */ |
11683 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
11684 | if (! howto) | |
11685 | return; | |
65551fa4 | 11686 | |
252b5132 RH |
11687 | assert (fixP->fx_size == 4 |
11688 | || fixP->fx_r_type == BFD_RELOC_16 | |
11689 | || fixP->fx_r_type == BFD_RELOC_64 | |
f6688943 TS |
11690 | || fixP->fx_r_type == BFD_RELOC_CTOR |
11691 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
252b5132 | 11692 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
a7ebbfdf | 11693 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY); |
252b5132 | 11694 | |
a7ebbfdf | 11695 | buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); |
252b5132 | 11696 | |
bad36eac | 11697 | assert (! fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2); |
b1dca8ee RS |
11698 | |
11699 | /* Don't treat parts of a composite relocation as done. There are two | |
11700 | reasons for this: | |
11701 | ||
11702 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
11703 | should nevertheless be emitted if the first part is. | |
11704 | ||
11705 | (2) In normal usage, composite relocations are never assembly-time | |
11706 | constants. The easiest way of dealing with the pathological | |
11707 | exceptions is to generate a relocation against STN_UNDEF and | |
11708 | leave everything up to the linker. */ | |
bad36eac | 11709 | if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel && fixP->fx_tcbit == 0) |
252b5132 RH |
11710 | fixP->fx_done = 1; |
11711 | ||
11712 | switch (fixP->fx_r_type) | |
11713 | { | |
3f98094e DJ |
11714 | case BFD_RELOC_MIPS_TLS_GD: |
11715 | case BFD_RELOC_MIPS_TLS_LDM: | |
11716 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: | |
11717 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
11718 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
11719 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: | |
11720 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
11721 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
11722 | /* fall through */ | |
11723 | ||
252b5132 | 11724 | case BFD_RELOC_MIPS_JMP: |
e369bcce TS |
11725 | case BFD_RELOC_MIPS_SHIFT5: |
11726 | case BFD_RELOC_MIPS_SHIFT6: | |
11727 | case BFD_RELOC_MIPS_GOT_DISP: | |
11728 | case BFD_RELOC_MIPS_GOT_PAGE: | |
11729 | case BFD_RELOC_MIPS_GOT_OFST: | |
11730 | case BFD_RELOC_MIPS_SUB: | |
11731 | case BFD_RELOC_MIPS_INSERT_A: | |
11732 | case BFD_RELOC_MIPS_INSERT_B: | |
11733 | case BFD_RELOC_MIPS_DELETE: | |
11734 | case BFD_RELOC_MIPS_HIGHEST: | |
11735 | case BFD_RELOC_MIPS_HIGHER: | |
11736 | case BFD_RELOC_MIPS_SCN_DISP: | |
11737 | case BFD_RELOC_MIPS_REL16: | |
11738 | case BFD_RELOC_MIPS_RELGOT: | |
11739 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
11740 | case BFD_RELOC_HI16: |
11741 | case BFD_RELOC_HI16_S: | |
cdf6fd85 | 11742 | case BFD_RELOC_GPREL16: |
252b5132 RH |
11743 | case BFD_RELOC_MIPS_LITERAL: |
11744 | case BFD_RELOC_MIPS_CALL16: | |
11745 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 11746 | case BFD_RELOC_GPREL32: |
252b5132 RH |
11747 | case BFD_RELOC_MIPS_GOT_HI16: |
11748 | case BFD_RELOC_MIPS_GOT_LO16: | |
11749 | case BFD_RELOC_MIPS_CALL_HI16: | |
11750 | case BFD_RELOC_MIPS_CALL_LO16: | |
11751 | case BFD_RELOC_MIPS16_GPREL: | |
d6f16593 MR |
11752 | case BFD_RELOC_MIPS16_HI16: |
11753 | case BFD_RELOC_MIPS16_HI16_S: | |
252b5132 RH |
11754 | /* Nothing needed to do. The value comes from the reloc entry */ |
11755 | break; | |
11756 | ||
11757 | case BFD_RELOC_MIPS16_JMP: | |
11758 | /* We currently always generate a reloc against a symbol, which | |
11759 | means that we don't want an addend even if the symbol is | |
11760 | defined. */ | |
a7ebbfdf | 11761 | *valP = 0; |
252b5132 RH |
11762 | break; |
11763 | ||
252b5132 RH |
11764 | case BFD_RELOC_64: |
11765 | /* This is handled like BFD_RELOC_32, but we output a sign | |
11766 | extended value if we are only 32 bits. */ | |
3e722fb5 | 11767 | if (fixP->fx_done) |
252b5132 RH |
11768 | { |
11769 | if (8 <= sizeof (valueT)) | |
2132e3a3 | 11770 | md_number_to_chars ((char *) buf, *valP, 8); |
252b5132 RH |
11771 | else |
11772 | { | |
a7ebbfdf | 11773 | valueT hiv; |
252b5132 | 11774 | |
a7ebbfdf | 11775 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
11776 | hiv = 0xffffffff; |
11777 | else | |
11778 | hiv = 0; | |
b215186b | 11779 | md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)), |
a7ebbfdf | 11780 | *valP, 4); |
b215186b | 11781 | md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)), |
a7ebbfdf | 11782 | hiv, 4); |
252b5132 RH |
11783 | } |
11784 | } | |
11785 | break; | |
11786 | ||
056350c6 | 11787 | case BFD_RELOC_RVA: |
252b5132 RH |
11788 | case BFD_RELOC_32: |
11789 | /* If we are deleting this reloc entry, we must fill in the | |
11790 | value now. This can happen if we have a .word which is not | |
3e722fb5 CD |
11791 | resolved when it appears but is later defined. */ |
11792 | if (fixP->fx_done) | |
2132e3a3 | 11793 | md_number_to_chars ((char *) buf, *valP, 4); |
252b5132 RH |
11794 | break; |
11795 | ||
11796 | case BFD_RELOC_16: | |
11797 | /* If we are deleting this reloc entry, we must fill in the | |
11798 | value now. */ | |
252b5132 | 11799 | if (fixP->fx_done) |
2132e3a3 | 11800 | md_number_to_chars ((char *) buf, *valP, 2); |
252b5132 RH |
11801 | break; |
11802 | ||
11803 | case BFD_RELOC_LO16: | |
d6f16593 | 11804 | case BFD_RELOC_MIPS16_LO16: |
3e722fb5 CD |
11805 | /* FIXME: Now that embedded-PIC is gone, some of this code/comment |
11806 | may be safe to remove, but if so it's not obvious. */ | |
252b5132 RH |
11807 | /* When handling an embedded PIC switch statement, we can wind |
11808 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
11809 | if (fixP->fx_done) | |
11810 | { | |
a7ebbfdf | 11811 | if (*valP + 0x8000 > 0xffff) |
252b5132 RH |
11812 | as_bad_where (fixP->fx_file, fixP->fx_line, |
11813 | _("relocation overflow")); | |
252b5132 RH |
11814 | if (target_big_endian) |
11815 | buf += 2; | |
2132e3a3 | 11816 | md_number_to_chars ((char *) buf, *valP, 2); |
252b5132 RH |
11817 | } |
11818 | break; | |
11819 | ||
11820 | case BFD_RELOC_16_PCREL_S2: | |
a7ebbfdf | 11821 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 11822 | as_bad_where (fixP->fx_file, fixP->fx_line, |
bad36eac | 11823 | _("Branch to misaligned address (%lx)"), (long) *valP); |
cb56d3d3 | 11824 | |
252b5132 RH |
11825 | /* |
11826 | * We need to save the bits in the instruction since fixup_segment() | |
11827 | * might be deleting the relocation entry (i.e., a branch within | |
11828 | * the current segment). | |
11829 | */ | |
a7ebbfdf | 11830 | if (! fixP->fx_done) |
bb2d6cd7 | 11831 | break; |
252b5132 RH |
11832 | |
11833 | /* update old instruction data */ | |
252b5132 RH |
11834 | if (target_big_endian) |
11835 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
11836 | else | |
11837 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
11838 | ||
a7ebbfdf TS |
11839 | if (*valP + 0x20000 <= 0x3ffff) |
11840 | { | |
11841 | insn |= (*valP >> 2) & 0xffff; | |
2132e3a3 | 11842 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
11843 | } |
11844 | else if (mips_pic == NO_PIC | |
11845 | && fixP->fx_done | |
11846 | && fixP->fx_frag->fr_address >= text_section->vma | |
11847 | && (fixP->fx_frag->fr_address | |
587aac4e | 11848 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
11849 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
11850 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
11851 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
11852 | { |
11853 | /* The branch offset is too large. If this is an | |
11854 | unconditional branch, and we are not generating PIC code, | |
11855 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
11856 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
11857 | insn = 0x0c000000; /* jal */ | |
252b5132 | 11858 | else |
a7ebbfdf TS |
11859 | insn = 0x08000000; /* j */ |
11860 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
11861 | fixP->fx_done = 0; | |
11862 | fixP->fx_addsy = section_symbol (text_section); | |
11863 | *valP += md_pcrel_from (fixP); | |
2132e3a3 | 11864 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
11865 | } |
11866 | else | |
11867 | { | |
11868 | /* If we got here, we have branch-relaxation disabled, | |
11869 | and there's nothing we can do to fix this instruction | |
11870 | without turning it into a longer sequence. */ | |
11871 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11872 | _("Branch out of range")); | |
252b5132 | 11873 | } |
252b5132 RH |
11874 | break; |
11875 | ||
11876 | case BFD_RELOC_VTABLE_INHERIT: | |
11877 | fixP->fx_done = 0; | |
11878 | if (fixP->fx_addsy | |
11879 | && !S_IS_DEFINED (fixP->fx_addsy) | |
11880 | && !S_IS_WEAK (fixP->fx_addsy)) | |
11881 | S_SET_WEAK (fixP->fx_addsy); | |
11882 | break; | |
11883 | ||
11884 | case BFD_RELOC_VTABLE_ENTRY: | |
11885 | fixP->fx_done = 0; | |
11886 | break; | |
11887 | ||
11888 | default: | |
11889 | internalError (); | |
11890 | } | |
a7ebbfdf TS |
11891 | |
11892 | /* Remember value for tc_gen_reloc. */ | |
11893 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
11894 | } |
11895 | ||
252b5132 | 11896 | static symbolS * |
17a2f251 | 11897 | get_symbol (void) |
252b5132 RH |
11898 | { |
11899 | int c; | |
11900 | char *name; | |
11901 | symbolS *p; | |
11902 | ||
11903 | name = input_line_pointer; | |
11904 | c = get_symbol_end (); | |
11905 | p = (symbolS *) symbol_find_or_make (name); | |
11906 | *input_line_pointer = c; | |
11907 | return p; | |
11908 | } | |
11909 | ||
11910 | /* Align the current frag to a given power of two. The MIPS assembler | |
11911 | also automatically adjusts any preceding label. */ | |
11912 | ||
11913 | static void | |
17a2f251 | 11914 | mips_align (int to, int fill, symbolS *label) |
252b5132 | 11915 | { |
7d10b47d | 11916 | mips_emit_delays (); |
252b5132 RH |
11917 | frag_align (to, fill, 0); |
11918 | record_alignment (now_seg, to); | |
11919 | if (label != NULL) | |
11920 | { | |
11921 | assert (S_GET_SEGMENT (label) == now_seg); | |
49309057 | 11922 | symbol_set_frag (label, frag_now); |
252b5132 RH |
11923 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
11924 | } | |
11925 | } | |
11926 | ||
11927 | /* Align to a given power of two. .align 0 turns off the automatic | |
11928 | alignment used by the data creating pseudo-ops. */ | |
11929 | ||
11930 | static void | |
17a2f251 | 11931 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11932 | { |
11933 | register int temp; | |
11934 | register long temp_fill; | |
11935 | long max_alignment = 15; | |
11936 | ||
11937 | /* | |
11938 | ||
67c1ffbe | 11939 | o Note that the assembler pulls down any immediately preceding label |
252b5132 RH |
11940 | to the aligned address. |
11941 | o It's not documented but auto alignment is reinstated by | |
11942 | a .align pseudo instruction. | |
11943 | o Note also that after auto alignment is turned off the mips assembler | |
11944 | issues an error on attempt to assemble an improperly aligned data item. | |
11945 | We don't. | |
11946 | ||
11947 | */ | |
11948 | ||
11949 | temp = get_absolute_expression (); | |
11950 | if (temp > max_alignment) | |
11951 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
11952 | else if (temp < 0) | |
11953 | { | |
11954 | as_warn (_("Alignment negative: 0 assumed.")); | |
11955 | temp = 0; | |
11956 | } | |
11957 | if (*input_line_pointer == ',') | |
11958 | { | |
f9419b05 | 11959 | ++input_line_pointer; |
252b5132 RH |
11960 | temp_fill = get_absolute_expression (); |
11961 | } | |
11962 | else | |
11963 | temp_fill = 0; | |
11964 | if (temp) | |
11965 | { | |
11966 | auto_align = 1; | |
11967 | mips_align (temp, (int) temp_fill, | |
11968 | insn_labels != NULL ? insn_labels->label : NULL); | |
11969 | } | |
11970 | else | |
11971 | { | |
11972 | auto_align = 0; | |
11973 | } | |
11974 | ||
11975 | demand_empty_rest_of_line (); | |
11976 | } | |
11977 | ||
252b5132 | 11978 | static void |
17a2f251 | 11979 | s_change_sec (int sec) |
252b5132 RH |
11980 | { |
11981 | segT seg; | |
11982 | ||
252b5132 RH |
11983 | #ifdef OBJ_ELF |
11984 | /* The ELF backend needs to know that we are changing sections, so | |
11985 | that .previous works correctly. We could do something like check | |
b6ff326e | 11986 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
11987 | as it would not be appropriate to use it in the section changing |
11988 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
11989 | This should be cleaner, somehow. */ | |
11990 | obj_elf_section_change_hook (); | |
11991 | #endif | |
11992 | ||
7d10b47d | 11993 | mips_emit_delays (); |
252b5132 RH |
11994 | switch (sec) |
11995 | { | |
11996 | case 't': | |
11997 | s_text (0); | |
11998 | break; | |
11999 | case 'd': | |
12000 | s_data (0); | |
12001 | break; | |
12002 | case 'b': | |
12003 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
12004 | demand_empty_rest_of_line (); | |
12005 | break; | |
12006 | ||
12007 | case 'r': | |
4d0d148d TS |
12008 | seg = subseg_new (RDATA_SECTION_NAME, |
12009 | (subsegT) get_absolute_expression ()); | |
12010 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
252b5132 | 12011 | { |
4d0d148d TS |
12012 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
12013 | | SEC_READONLY | SEC_RELOC | |
12014 | | SEC_DATA)); | |
12015 | if (strcmp (TARGET_OS, "elf") != 0) | |
12016 | record_alignment (seg, 4); | |
252b5132 | 12017 | } |
4d0d148d | 12018 | demand_empty_rest_of_line (); |
252b5132 RH |
12019 | break; |
12020 | ||
12021 | case 's': | |
4d0d148d TS |
12022 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
12023 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
252b5132 | 12024 | { |
4d0d148d TS |
12025 | bfd_set_section_flags (stdoutput, seg, |
12026 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
12027 | if (strcmp (TARGET_OS, "elf") != 0) | |
12028 | record_alignment (seg, 4); | |
252b5132 | 12029 | } |
4d0d148d TS |
12030 | demand_empty_rest_of_line (); |
12031 | break; | |
252b5132 RH |
12032 | } |
12033 | ||
12034 | auto_align = 1; | |
12035 | } | |
b34976b6 | 12036 | |
cca86cc8 | 12037 | void |
17a2f251 | 12038 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 12039 | { |
7ed4a06a | 12040 | #ifdef OBJ_ELF |
cca86cc8 SC |
12041 | char *section_name; |
12042 | char c; | |
684022ea | 12043 | char next_c = 0; |
cca86cc8 SC |
12044 | int section_type; |
12045 | int section_flag; | |
12046 | int section_entry_size; | |
12047 | int section_alignment; | |
b34976b6 | 12048 | |
7ed4a06a TS |
12049 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
12050 | return; | |
12051 | ||
cca86cc8 SC |
12052 | section_name = input_line_pointer; |
12053 | c = get_symbol_end (); | |
a816d1ed AO |
12054 | if (c) |
12055 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 12056 | |
4cf0dd0d TS |
12057 | /* Do we have .section Name<,"flags">? */ |
12058 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 12059 | { |
4cf0dd0d TS |
12060 | /* just after name is now '\0'. */ |
12061 | *input_line_pointer = c; | |
cca86cc8 SC |
12062 | input_line_pointer = section_name; |
12063 | obj_elf_section (ignore); | |
12064 | return; | |
12065 | } | |
12066 | input_line_pointer++; | |
12067 | ||
12068 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
12069 | if (c == ',') | |
12070 | section_type = get_absolute_expression (); | |
12071 | else | |
12072 | section_type = 0; | |
12073 | if (*input_line_pointer++ == ',') | |
12074 | section_flag = get_absolute_expression (); | |
12075 | else | |
12076 | section_flag = 0; | |
12077 | if (*input_line_pointer++ == ',') | |
12078 | section_entry_size = get_absolute_expression (); | |
12079 | else | |
12080 | section_entry_size = 0; | |
12081 | if (*input_line_pointer++ == ',') | |
12082 | section_alignment = get_absolute_expression (); | |
12083 | else | |
12084 | section_alignment = 0; | |
12085 | ||
a816d1ed AO |
12086 | section_name = xstrdup (section_name); |
12087 | ||
8ab8a5c8 RS |
12088 | /* When using the generic form of .section (as implemented by obj-elf.c), |
12089 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
12090 | traditionally had to fall back on the more common @progbits instead. | |
12091 | ||
12092 | There's nothing really harmful in this, since bfd will correct | |
12093 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
708587a4 | 12094 | means that, for backwards compatibility, the special_section entries |
8ab8a5c8 RS |
12095 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. |
12096 | ||
12097 | Even so, we shouldn't force users of the MIPS .section syntax to | |
12098 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
12099 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
12100 | generic type-checking code. */ | |
12101 | if (section_type == SHT_MIPS_DWARF) | |
12102 | section_type = SHT_PROGBITS; | |
12103 | ||
cca86cc8 SC |
12104 | obj_elf_change_section (section_name, section_type, section_flag, |
12105 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
12106 | |
12107 | if (now_seg->name != section_name) | |
12108 | free (section_name); | |
7ed4a06a | 12109 | #endif /* OBJ_ELF */ |
cca86cc8 | 12110 | } |
252b5132 RH |
12111 | |
12112 | void | |
17a2f251 | 12113 | mips_enable_auto_align (void) |
252b5132 RH |
12114 | { |
12115 | auto_align = 1; | |
12116 | } | |
12117 | ||
12118 | static void | |
17a2f251 | 12119 | s_cons (int log_size) |
252b5132 RH |
12120 | { |
12121 | symbolS *label; | |
12122 | ||
12123 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
7d10b47d | 12124 | mips_emit_delays (); |
252b5132 RH |
12125 | if (log_size > 0 && auto_align) |
12126 | mips_align (log_size, 0, label); | |
12127 | mips_clear_insn_labels (); | |
12128 | cons (1 << log_size); | |
12129 | } | |
12130 | ||
12131 | static void | |
17a2f251 | 12132 | s_float_cons (int type) |
252b5132 RH |
12133 | { |
12134 | symbolS *label; | |
12135 | ||
12136 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
12137 | ||
7d10b47d | 12138 | mips_emit_delays (); |
252b5132 RH |
12139 | |
12140 | if (auto_align) | |
49309057 ILT |
12141 | { |
12142 | if (type == 'd') | |
12143 | mips_align (3, 0, label); | |
12144 | else | |
12145 | mips_align (2, 0, label); | |
12146 | } | |
252b5132 RH |
12147 | |
12148 | mips_clear_insn_labels (); | |
12149 | ||
12150 | float_cons (type); | |
12151 | } | |
12152 | ||
12153 | /* Handle .globl. We need to override it because on Irix 5 you are | |
12154 | permitted to say | |
12155 | .globl foo .text | |
12156 | where foo is an undefined symbol, to mean that foo should be | |
12157 | considered to be the address of a function. */ | |
12158 | ||
12159 | static void | |
17a2f251 | 12160 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
12161 | { |
12162 | char *name; | |
12163 | int c; | |
12164 | symbolS *symbolP; | |
12165 | flagword flag; | |
12166 | ||
8a06b769 | 12167 | do |
252b5132 | 12168 | { |
8a06b769 | 12169 | name = input_line_pointer; |
252b5132 | 12170 | c = get_symbol_end (); |
8a06b769 TS |
12171 | symbolP = symbol_find_or_make (name); |
12172 | S_SET_EXTERNAL (symbolP); | |
12173 | ||
252b5132 | 12174 | *input_line_pointer = c; |
8a06b769 | 12175 | SKIP_WHITESPACE (); |
252b5132 | 12176 | |
8a06b769 TS |
12177 | /* On Irix 5, every global symbol that is not explicitly labelled as |
12178 | being a function is apparently labelled as being an object. */ | |
12179 | flag = BSF_OBJECT; | |
252b5132 | 12180 | |
8a06b769 TS |
12181 | if (!is_end_of_line[(unsigned char) *input_line_pointer] |
12182 | && (*input_line_pointer != ',')) | |
12183 | { | |
12184 | char *secname; | |
12185 | asection *sec; | |
12186 | ||
12187 | secname = input_line_pointer; | |
12188 | c = get_symbol_end (); | |
12189 | sec = bfd_get_section_by_name (stdoutput, secname); | |
12190 | if (sec == NULL) | |
12191 | as_bad (_("%s: no such section"), secname); | |
12192 | *input_line_pointer = c; | |
12193 | ||
12194 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
12195 | flag = BSF_FUNCTION; | |
12196 | } | |
12197 | ||
12198 | symbol_get_bfdsym (symbolP)->flags |= flag; | |
12199 | ||
12200 | c = *input_line_pointer; | |
12201 | if (c == ',') | |
12202 | { | |
12203 | input_line_pointer++; | |
12204 | SKIP_WHITESPACE (); | |
12205 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
12206 | c = '\n'; | |
12207 | } | |
12208 | } | |
12209 | while (c == ','); | |
252b5132 | 12210 | |
252b5132 RH |
12211 | demand_empty_rest_of_line (); |
12212 | } | |
12213 | ||
12214 | static void | |
17a2f251 | 12215 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
12216 | { |
12217 | char *opt; | |
12218 | char c; | |
12219 | ||
12220 | opt = input_line_pointer; | |
12221 | c = get_symbol_end (); | |
12222 | ||
12223 | if (*opt == 'O') | |
12224 | { | |
12225 | /* FIXME: What does this mean? */ | |
12226 | } | |
12227 | else if (strncmp (opt, "pic", 3) == 0) | |
12228 | { | |
12229 | int i; | |
12230 | ||
12231 | i = atoi (opt + 3); | |
12232 | if (i == 0) | |
12233 | mips_pic = NO_PIC; | |
12234 | else if (i == 2) | |
143d77c5 | 12235 | { |
252b5132 | 12236 | mips_pic = SVR4_PIC; |
143d77c5 EC |
12237 | mips_abicalls = TRUE; |
12238 | } | |
252b5132 RH |
12239 | else |
12240 | as_bad (_(".option pic%d not supported"), i); | |
12241 | ||
4d0d148d | 12242 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
12243 | { |
12244 | if (g_switch_seen && g_switch_value != 0) | |
12245 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
12246 | g_switch_value = 0; | |
12247 | bfd_set_gp_size (stdoutput, 0); | |
12248 | } | |
12249 | } | |
12250 | else | |
12251 | as_warn (_("Unrecognized option \"%s\""), opt); | |
12252 | ||
12253 | *input_line_pointer = c; | |
12254 | demand_empty_rest_of_line (); | |
12255 | } | |
12256 | ||
12257 | /* This structure is used to hold a stack of .set values. */ | |
12258 | ||
e972090a NC |
12259 | struct mips_option_stack |
12260 | { | |
252b5132 RH |
12261 | struct mips_option_stack *next; |
12262 | struct mips_set_options options; | |
12263 | }; | |
12264 | ||
12265 | static struct mips_option_stack *mips_opts_stack; | |
12266 | ||
12267 | /* Handle the .set pseudo-op. */ | |
12268 | ||
12269 | static void | |
17a2f251 | 12270 | s_mipsset (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
12271 | { |
12272 | char *name = input_line_pointer, ch; | |
12273 | ||
12274 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 12275 | ++input_line_pointer; |
252b5132 RH |
12276 | ch = *input_line_pointer; |
12277 | *input_line_pointer = '\0'; | |
12278 | ||
12279 | if (strcmp (name, "reorder") == 0) | |
12280 | { | |
7d10b47d RS |
12281 | if (mips_opts.noreorder) |
12282 | end_noreorder (); | |
252b5132 RH |
12283 | } |
12284 | else if (strcmp (name, "noreorder") == 0) | |
12285 | { | |
7d10b47d RS |
12286 | if (!mips_opts.noreorder) |
12287 | start_noreorder (); | |
252b5132 RH |
12288 | } |
12289 | else if (strcmp (name, "at") == 0) | |
12290 | { | |
12291 | mips_opts.noat = 0; | |
12292 | } | |
12293 | else if (strcmp (name, "noat") == 0) | |
12294 | { | |
12295 | mips_opts.noat = 1; | |
12296 | } | |
12297 | else if (strcmp (name, "macro") == 0) | |
12298 | { | |
12299 | mips_opts.warn_about_macros = 0; | |
12300 | } | |
12301 | else if (strcmp (name, "nomacro") == 0) | |
12302 | { | |
12303 | if (mips_opts.noreorder == 0) | |
12304 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
12305 | mips_opts.warn_about_macros = 1; | |
12306 | } | |
12307 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
12308 | { | |
12309 | mips_opts.nomove = 0; | |
12310 | } | |
12311 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
12312 | { | |
12313 | mips_opts.nomove = 1; | |
12314 | } | |
12315 | else if (strcmp (name, "bopt") == 0) | |
12316 | { | |
12317 | mips_opts.nobopt = 0; | |
12318 | } | |
12319 | else if (strcmp (name, "nobopt") == 0) | |
12320 | { | |
12321 | mips_opts.nobopt = 1; | |
12322 | } | |
ad3fea08 TS |
12323 | else if (strcmp (name, "gp=default") == 0) |
12324 | mips_opts.gp32 = file_mips_gp32; | |
12325 | else if (strcmp (name, "gp=32") == 0) | |
12326 | mips_opts.gp32 = 1; | |
12327 | else if (strcmp (name, "gp=64") == 0) | |
12328 | { | |
12329 | if (!ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
12330 | as_warn ("%s isa does not support 64-bit registers", | |
12331 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
12332 | mips_opts.gp32 = 0; | |
12333 | } | |
12334 | else if (strcmp (name, "fp=default") == 0) | |
12335 | mips_opts.fp32 = file_mips_fp32; | |
12336 | else if (strcmp (name, "fp=32") == 0) | |
12337 | mips_opts.fp32 = 1; | |
12338 | else if (strcmp (name, "fp=64") == 0) | |
12339 | { | |
12340 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
12341 | as_warn ("%s isa does not support 64-bit floating point registers", | |
12342 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
12343 | mips_opts.fp32 = 0; | |
12344 | } | |
252b5132 RH |
12345 | else if (strcmp (name, "mips16") == 0 |
12346 | || strcmp (name, "MIPS-16") == 0) | |
12347 | mips_opts.mips16 = 1; | |
12348 | else if (strcmp (name, "nomips16") == 0 | |
12349 | || strcmp (name, "noMIPS-16") == 0) | |
12350 | mips_opts.mips16 = 0; | |
e16bfa71 TS |
12351 | else if (strcmp (name, "smartmips") == 0) |
12352 | { | |
ad3fea08 | 12353 | if (!ISA_SUPPORTS_SMARTMIPS) |
e16bfa71 TS |
12354 | as_warn ("%s ISA does not support SmartMIPS ASE", |
12355 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
12356 | mips_opts.ase_smartmips = 1; | |
12357 | } | |
12358 | else if (strcmp (name, "nosmartmips") == 0) | |
12359 | mips_opts.ase_smartmips = 0; | |
1f25f5d3 CD |
12360 | else if (strcmp (name, "mips3d") == 0) |
12361 | mips_opts.ase_mips3d = 1; | |
12362 | else if (strcmp (name, "nomips3d") == 0) | |
12363 | mips_opts.ase_mips3d = 0; | |
a4672219 TS |
12364 | else if (strcmp (name, "mdmx") == 0) |
12365 | mips_opts.ase_mdmx = 1; | |
12366 | else if (strcmp (name, "nomdmx") == 0) | |
12367 | mips_opts.ase_mdmx = 0; | |
74cd071d | 12368 | else if (strcmp (name, "dsp") == 0) |
ad3fea08 TS |
12369 | { |
12370 | if (!ISA_SUPPORTS_DSP_ASE) | |
12371 | as_warn ("%s ISA does not support DSP ASE", | |
12372 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
12373 | mips_opts.ase_dsp = 1; | |
12374 | } | |
74cd071d CF |
12375 | else if (strcmp (name, "nodsp") == 0) |
12376 | mips_opts.ase_dsp = 0; | |
ef2e4d86 | 12377 | else if (strcmp (name, "mt") == 0) |
ad3fea08 TS |
12378 | { |
12379 | if (!ISA_SUPPORTS_MT_ASE) | |
12380 | as_warn ("%s ISA does not support MT ASE", | |
12381 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
12382 | mips_opts.ase_mt = 1; | |
12383 | } | |
ef2e4d86 CF |
12384 | else if (strcmp (name, "nomt") == 0) |
12385 | mips_opts.ase_mt = 0; | |
1a2c1fad | 12386 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 12387 | { |
af7ee8bf | 12388 | int reset = 0; |
252b5132 | 12389 | |
1a2c1fad CD |
12390 | /* Permit the user to change the ISA and architecture on the fly. |
12391 | Needless to say, misuse can cause serious problems. */ | |
81a21e38 | 12392 | if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) |
af7ee8bf CD |
12393 | { |
12394 | reset = 1; | |
12395 | mips_opts.isa = file_mips_isa; | |
1a2c1fad | 12396 | mips_opts.arch = file_mips_arch; |
1a2c1fad CD |
12397 | } |
12398 | else if (strncmp (name, "arch=", 5) == 0) | |
12399 | { | |
12400 | const struct mips_cpu_info *p; | |
12401 | ||
12402 | p = mips_parse_cpu("internal use", name + 5); | |
12403 | if (!p) | |
12404 | as_bad (_("unknown architecture %s"), name + 5); | |
12405 | else | |
12406 | { | |
12407 | mips_opts.arch = p->cpu; | |
12408 | mips_opts.isa = p->isa; | |
12409 | } | |
12410 | } | |
81a21e38 TS |
12411 | else if (strncmp (name, "mips", 4) == 0) |
12412 | { | |
12413 | const struct mips_cpu_info *p; | |
12414 | ||
12415 | p = mips_parse_cpu("internal use", name); | |
12416 | if (!p) | |
12417 | as_bad (_("unknown ISA level %s"), name + 4); | |
12418 | else | |
12419 | { | |
12420 | mips_opts.arch = p->cpu; | |
12421 | mips_opts.isa = p->isa; | |
12422 | } | |
12423 | } | |
af7ee8bf | 12424 | else |
81a21e38 | 12425 | as_bad (_("unknown ISA or architecture %s"), name); |
af7ee8bf CD |
12426 | |
12427 | switch (mips_opts.isa) | |
98d3f06f KH |
12428 | { |
12429 | case 0: | |
98d3f06f | 12430 | break; |
af7ee8bf CD |
12431 | case ISA_MIPS1: |
12432 | case ISA_MIPS2: | |
12433 | case ISA_MIPS32: | |
12434 | case ISA_MIPS32R2: | |
98d3f06f KH |
12435 | mips_opts.gp32 = 1; |
12436 | mips_opts.fp32 = 1; | |
12437 | break; | |
af7ee8bf CD |
12438 | case ISA_MIPS3: |
12439 | case ISA_MIPS4: | |
12440 | case ISA_MIPS5: | |
12441 | case ISA_MIPS64: | |
5f74bc13 | 12442 | case ISA_MIPS64R2: |
98d3f06f KH |
12443 | mips_opts.gp32 = 0; |
12444 | mips_opts.fp32 = 0; | |
12445 | break; | |
12446 | default: | |
12447 | as_bad (_("unknown ISA level %s"), name + 4); | |
12448 | break; | |
12449 | } | |
af7ee8bf | 12450 | if (reset) |
98d3f06f | 12451 | { |
af7ee8bf CD |
12452 | mips_opts.gp32 = file_mips_gp32; |
12453 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 12454 | } |
252b5132 RH |
12455 | } |
12456 | else if (strcmp (name, "autoextend") == 0) | |
12457 | mips_opts.noautoextend = 0; | |
12458 | else if (strcmp (name, "noautoextend") == 0) | |
12459 | mips_opts.noautoextend = 1; | |
12460 | else if (strcmp (name, "push") == 0) | |
12461 | { | |
12462 | struct mips_option_stack *s; | |
12463 | ||
12464 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
12465 | s->next = mips_opts_stack; | |
12466 | s->options = mips_opts; | |
12467 | mips_opts_stack = s; | |
12468 | } | |
12469 | else if (strcmp (name, "pop") == 0) | |
12470 | { | |
12471 | struct mips_option_stack *s; | |
12472 | ||
12473 | s = mips_opts_stack; | |
12474 | if (s == NULL) | |
12475 | as_bad (_(".set pop with no .set push")); | |
12476 | else | |
12477 | { | |
12478 | /* If we're changing the reorder mode we need to handle | |
12479 | delay slots correctly. */ | |
12480 | if (s->options.noreorder && ! mips_opts.noreorder) | |
7d10b47d | 12481 | start_noreorder (); |
252b5132 | 12482 | else if (! s->options.noreorder && mips_opts.noreorder) |
7d10b47d | 12483 | end_noreorder (); |
252b5132 RH |
12484 | |
12485 | mips_opts = s->options; | |
12486 | mips_opts_stack = s->next; | |
12487 | free (s); | |
12488 | } | |
12489 | } | |
aed1a261 RS |
12490 | else if (strcmp (name, "sym32") == 0) |
12491 | mips_opts.sym32 = TRUE; | |
12492 | else if (strcmp (name, "nosym32") == 0) | |
12493 | mips_opts.sym32 = FALSE; | |
252b5132 RH |
12494 | else |
12495 | { | |
12496 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
12497 | } | |
12498 | *input_line_pointer = ch; | |
12499 | demand_empty_rest_of_line (); | |
12500 | } | |
12501 | ||
12502 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
12503 | .option pic2. It means to generate SVR4 PIC calls. */ | |
12504 | ||
12505 | static void | |
17a2f251 | 12506 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12507 | { |
12508 | mips_pic = SVR4_PIC; | |
143d77c5 | 12509 | mips_abicalls = TRUE; |
4d0d148d TS |
12510 | |
12511 | if (g_switch_seen && g_switch_value != 0) | |
12512 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
12513 | g_switch_value = 0; | |
12514 | ||
252b5132 RH |
12515 | bfd_set_gp_size (stdoutput, 0); |
12516 | demand_empty_rest_of_line (); | |
12517 | } | |
12518 | ||
12519 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
12520 | PIC code. It sets the $gp register for the function based on the | |
12521 | function address, which is in the register named in the argument. | |
12522 | This uses a relocation against _gp_disp, which is handled specially | |
12523 | by the linker. The result is: | |
12524 | lui $gp,%hi(_gp_disp) | |
12525 | addiu $gp,$gp,%lo(_gp_disp) | |
12526 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
12527 | The .cpload argument is normally $25 == $t9. |
12528 | ||
12529 | The -mno-shared option changes this to: | |
bbe506e8 TS |
12530 | lui $gp,%hi(__gnu_local_gp) |
12531 | addiu $gp,$gp,%lo(__gnu_local_gp) | |
aa6975fb ILT |
12532 | and the argument is ignored. This saves an instruction, but the |
12533 | resulting code is not position independent; it uses an absolute | |
bbe506e8 TS |
12534 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
12535 | can go into an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
12536 | |
12537 | static void | |
17a2f251 | 12538 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12539 | { |
12540 | expressionS ex; | |
aa6975fb ILT |
12541 | int reg; |
12542 | int in_shared; | |
252b5132 | 12543 | |
6478892d TS |
12544 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
12545 | .cpload is ignored. */ | |
12546 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
12547 | { |
12548 | s_ignore (0); | |
12549 | return; | |
12550 | } | |
12551 | ||
d3ecfc59 | 12552 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
12553 | if (mips_opts.noreorder == 0) |
12554 | as_warn (_(".cpload not in noreorder section")); | |
12555 | ||
aa6975fb ILT |
12556 | reg = tc_get_register (0); |
12557 | ||
12558 | /* If we need to produce a 64-bit address, we are better off using | |
12559 | the default instruction sequence. */ | |
aed1a261 | 12560 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
aa6975fb | 12561 | |
252b5132 | 12562 | ex.X_op = O_symbol; |
bbe506e8 TS |
12563 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
12564 | "__gnu_local_gp"); | |
252b5132 RH |
12565 | ex.X_op_symbol = NULL; |
12566 | ex.X_add_number = 0; | |
12567 | ||
12568 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 12569 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 12570 | |
584892a6 | 12571 | macro_start (); |
67c0d1eb RS |
12572 | macro_build_lui (&ex, mips_gp_register); |
12573 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 12574 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
12575 | if (in_shared) |
12576 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
12577 | mips_gp_register, reg); | |
584892a6 | 12578 | macro_end (); |
252b5132 RH |
12579 | |
12580 | demand_empty_rest_of_line (); | |
12581 | } | |
12582 | ||
6478892d TS |
12583 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
12584 | .cpsetup $reg1, offset|$reg2, label | |
12585 | ||
12586 | If offset is given, this results in: | |
12587 | sd $gp, offset($sp) | |
956cd1d6 | 12588 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
12589 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
12590 | daddu $gp, $gp, $reg1 | |
6478892d TS |
12591 | |
12592 | If $reg2 is given, this results in: | |
12593 | daddu $reg2, $gp, $0 | |
956cd1d6 | 12594 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
12595 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
12596 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
12597 | $reg1 is normally $25 == $t9. |
12598 | ||
12599 | The -mno-shared option replaces the last three instructions with | |
12600 | lui $gp,%hi(_gp) | |
12601 | addiu $gp,$gp,%lo(_gp) | |
12602 | */ | |
12603 | ||
6478892d | 12604 | static void |
17a2f251 | 12605 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12606 | { |
12607 | expressionS ex_off; | |
12608 | expressionS ex_sym; | |
12609 | int reg1; | |
6478892d | 12610 | |
8586fc66 | 12611 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
12612 | We also need NewABI support. */ |
12613 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12614 | { | |
12615 | s_ignore (0); | |
12616 | return; | |
12617 | } | |
12618 | ||
12619 | reg1 = tc_get_register (0); | |
12620 | SKIP_WHITESPACE (); | |
12621 | if (*input_line_pointer != ',') | |
12622 | { | |
12623 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
12624 | return; | |
12625 | } | |
12626 | else | |
80245285 | 12627 | ++input_line_pointer; |
6478892d TS |
12628 | SKIP_WHITESPACE (); |
12629 | if (*input_line_pointer == '$') | |
80245285 TS |
12630 | { |
12631 | mips_cpreturn_register = tc_get_register (0); | |
12632 | mips_cpreturn_offset = -1; | |
12633 | } | |
6478892d | 12634 | else |
80245285 TS |
12635 | { |
12636 | mips_cpreturn_offset = get_absolute_expression (); | |
12637 | mips_cpreturn_register = -1; | |
12638 | } | |
6478892d TS |
12639 | SKIP_WHITESPACE (); |
12640 | if (*input_line_pointer != ',') | |
12641 | { | |
12642 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
12643 | return; | |
12644 | } | |
12645 | else | |
f9419b05 | 12646 | ++input_line_pointer; |
6478892d | 12647 | SKIP_WHITESPACE (); |
f21f8242 | 12648 | expression (&ex_sym); |
6478892d | 12649 | |
584892a6 | 12650 | macro_start (); |
6478892d TS |
12651 | if (mips_cpreturn_register == -1) |
12652 | { | |
12653 | ex_off.X_op = O_constant; | |
12654 | ex_off.X_add_symbol = NULL; | |
12655 | ex_off.X_op_symbol = NULL; | |
12656 | ex_off.X_add_number = mips_cpreturn_offset; | |
12657 | ||
67c0d1eb | 12658 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 12659 | BFD_RELOC_LO16, SP); |
6478892d TS |
12660 | } |
12661 | else | |
67c0d1eb | 12662 | macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, |
17a2f251 | 12663 | mips_gp_register, 0); |
6478892d | 12664 | |
aed1a261 | 12665 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
aa6975fb ILT |
12666 | { |
12667 | macro_build (&ex_sym, "lui", "t,u", mips_gp_register, | |
12668 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, | |
12669 | BFD_RELOC_HI16_S); | |
12670 | ||
12671 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
12672 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
12673 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
12674 | ||
12675 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
12676 | mips_gp_register, reg1); | |
12677 | } | |
12678 | else | |
12679 | { | |
12680 | expressionS ex; | |
12681 | ||
12682 | ex.X_op = O_symbol; | |
4184909a | 12683 | ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); |
aa6975fb ILT |
12684 | ex.X_op_symbol = NULL; |
12685 | ex.X_add_number = 0; | |
6e1304d8 | 12686 | |
aa6975fb ILT |
12687 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
12688 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
12689 | ||
12690 | macro_build_lui (&ex, mips_gp_register); | |
12691 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
12692 | mips_gp_register, BFD_RELOC_LO16); | |
12693 | } | |
f21f8242 | 12694 | |
584892a6 | 12695 | macro_end (); |
6478892d TS |
12696 | |
12697 | demand_empty_rest_of_line (); | |
12698 | } | |
12699 | ||
12700 | static void | |
17a2f251 | 12701 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12702 | { |
12703 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
12704 | .cplocal is ignored. */ | |
12705 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12706 | { | |
12707 | s_ignore (0); | |
12708 | return; | |
12709 | } | |
12710 | ||
12711 | mips_gp_register = tc_get_register (0); | |
85b51719 | 12712 | demand_empty_rest_of_line (); |
6478892d TS |
12713 | } |
12714 | ||
252b5132 RH |
12715 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
12716 | offset from $sp. The offset is remembered, and after making a PIC | |
12717 | call $gp is restored from that location. */ | |
12718 | ||
12719 | static void | |
17a2f251 | 12720 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12721 | { |
12722 | expressionS ex; | |
252b5132 | 12723 | |
6478892d | 12724 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 12725 | .cprestore is ignored. */ |
6478892d | 12726 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
12727 | { |
12728 | s_ignore (0); | |
12729 | return; | |
12730 | } | |
12731 | ||
12732 | mips_cprestore_offset = get_absolute_expression (); | |
7a621144 | 12733 | mips_cprestore_valid = 1; |
252b5132 RH |
12734 | |
12735 | ex.X_op = O_constant; | |
12736 | ex.X_add_symbol = NULL; | |
12737 | ex.X_op_symbol = NULL; | |
12738 | ex.X_add_number = mips_cprestore_offset; | |
12739 | ||
584892a6 | 12740 | macro_start (); |
67c0d1eb RS |
12741 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
12742 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 12743 | macro_end (); |
252b5132 RH |
12744 | |
12745 | demand_empty_rest_of_line (); | |
12746 | } | |
12747 | ||
6478892d | 12748 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 12749 | was given in the preceding .cpsetup, it results in: |
6478892d | 12750 | ld $gp, offset($sp) |
76b3015f | 12751 | |
6478892d | 12752 | If a register $reg2 was given there, it results in: |
609f23f4 | 12753 | daddu $gp, $reg2, $0 |
6478892d TS |
12754 | */ |
12755 | static void | |
17a2f251 | 12756 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12757 | { |
12758 | expressionS ex; | |
6478892d TS |
12759 | |
12760 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
12761 | We also need NewABI support. */ | |
12762 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12763 | { | |
12764 | s_ignore (0); | |
12765 | return; | |
12766 | } | |
12767 | ||
584892a6 | 12768 | macro_start (); |
6478892d TS |
12769 | if (mips_cpreturn_register == -1) |
12770 | { | |
12771 | ex.X_op = O_constant; | |
12772 | ex.X_add_symbol = NULL; | |
12773 | ex.X_op_symbol = NULL; | |
12774 | ex.X_add_number = mips_cpreturn_offset; | |
12775 | ||
67c0d1eb | 12776 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
12777 | } |
12778 | else | |
67c0d1eb | 12779 | macro_build (NULL, "daddu", "d,v,t", mips_gp_register, |
17a2f251 | 12780 | mips_cpreturn_register, 0); |
584892a6 | 12781 | macro_end (); |
6478892d TS |
12782 | |
12783 | demand_empty_rest_of_line (); | |
12784 | } | |
12785 | ||
12786 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC | |
12787 | code. It sets the offset to use in gp_rel relocations. */ | |
12788 | ||
12789 | static void | |
17a2f251 | 12790 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12791 | { |
12792 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
12793 | We also need NewABI support. */ | |
12794 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12795 | { | |
12796 | s_ignore (0); | |
12797 | return; | |
12798 | } | |
12799 | ||
def2e0dd | 12800 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
12801 | |
12802 | demand_empty_rest_of_line (); | |
12803 | } | |
12804 | ||
252b5132 RH |
12805 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
12806 | code. It generates a 32 bit GP relative reloc. */ | |
12807 | ||
12808 | static void | |
17a2f251 | 12809 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12810 | { |
12811 | symbolS *label; | |
12812 | expressionS ex; | |
12813 | char *p; | |
12814 | ||
12815 | /* When not generating PIC code, this is treated as .word. */ | |
12816 | if (mips_pic != SVR4_PIC) | |
12817 | { | |
12818 | s_cons (2); | |
12819 | return; | |
12820 | } | |
12821 | ||
12822 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
7d10b47d | 12823 | mips_emit_delays (); |
252b5132 RH |
12824 | if (auto_align) |
12825 | mips_align (2, 0, label); | |
12826 | mips_clear_insn_labels (); | |
12827 | ||
12828 | expression (&ex); | |
12829 | ||
12830 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
12831 | { | |
12832 | as_bad (_("Unsupported use of .gpword")); | |
12833 | ignore_rest_of_line (); | |
12834 | } | |
12835 | ||
12836 | p = frag_more (4); | |
17a2f251 | 12837 | md_number_to_chars (p, 0, 4); |
b34976b6 | 12838 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 12839 | BFD_RELOC_GPREL32); |
252b5132 RH |
12840 | |
12841 | demand_empty_rest_of_line (); | |
12842 | } | |
12843 | ||
10181a0d | 12844 | static void |
17a2f251 | 12845 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d AO |
12846 | { |
12847 | symbolS *label; | |
12848 | expressionS ex; | |
12849 | char *p; | |
12850 | ||
12851 | /* When not generating PIC code, this is treated as .dword. */ | |
12852 | if (mips_pic != SVR4_PIC) | |
12853 | { | |
12854 | s_cons (3); | |
12855 | return; | |
12856 | } | |
12857 | ||
12858 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
7d10b47d | 12859 | mips_emit_delays (); |
10181a0d AO |
12860 | if (auto_align) |
12861 | mips_align (3, 0, label); | |
12862 | mips_clear_insn_labels (); | |
12863 | ||
12864 | expression (&ex); | |
12865 | ||
12866 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
12867 | { | |
12868 | as_bad (_("Unsupported use of .gpdword")); | |
12869 | ignore_rest_of_line (); | |
12870 | } | |
12871 | ||
12872 | p = frag_more (8); | |
17a2f251 | 12873 | md_number_to_chars (p, 0, 8); |
a105a300 | 12874 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 12875 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
12876 | |
12877 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
12878 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
12879 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
12880 | |
12881 | demand_empty_rest_of_line (); | |
12882 | } | |
12883 | ||
252b5132 RH |
12884 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
12885 | tables in SVR4 PIC code. */ | |
12886 | ||
12887 | static void | |
17a2f251 | 12888 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 12889 | { |
252b5132 RH |
12890 | int reg; |
12891 | ||
10181a0d AO |
12892 | /* This is ignored when not generating SVR4 PIC code. */ |
12893 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
12894 | { |
12895 | s_ignore (0); | |
12896 | return; | |
12897 | } | |
12898 | ||
12899 | /* Add $gp to the register named as an argument. */ | |
584892a6 | 12900 | macro_start (); |
252b5132 | 12901 | reg = tc_get_register (0); |
67c0d1eb | 12902 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 12903 | macro_end (); |
252b5132 | 12904 | |
bdaaa2e1 | 12905 | demand_empty_rest_of_line (); |
252b5132 RH |
12906 | } |
12907 | ||
12908 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
12909 | mips16 mode. This permits the linker to handle them specially, | |
12910 | such as generating jalx instructions when needed. We also make | |
12911 | them odd for the duration of the assembly, in order to generate the | |
12912 | right sort of code. We will make them even in the adjust_symtab | |
12913 | routine, while leaving them marked. This is convenient for the | |
12914 | debugger and the disassembler. The linker knows to make them odd | |
12915 | again. */ | |
12916 | ||
12917 | static void | |
17a2f251 | 12918 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 12919 | { |
f9419b05 | 12920 | mips16_mark_labels (); |
252b5132 RH |
12921 | |
12922 | demand_empty_rest_of_line (); | |
12923 | } | |
12924 | ||
12925 | /* Handle a .stabn directive. We need these in order to mark a label | |
12926 | as being a mips16 text label correctly. Sometimes the compiler | |
12927 | will emit a label, followed by a .stabn, and then switch sections. | |
12928 | If the label and .stabn are in mips16 mode, then the label is | |
12929 | really a mips16 text label. */ | |
12930 | ||
12931 | static void | |
17a2f251 | 12932 | s_mips_stab (int type) |
252b5132 | 12933 | { |
f9419b05 | 12934 | if (type == 'n') |
252b5132 RH |
12935 | mips16_mark_labels (); |
12936 | ||
12937 | s_stab (type); | |
12938 | } | |
12939 | ||
12940 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. | |
12941 | */ | |
12942 | ||
12943 | static void | |
17a2f251 | 12944 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12945 | { |
12946 | char *name; | |
12947 | int c; | |
12948 | symbolS *symbolP; | |
12949 | expressionS exp; | |
12950 | ||
12951 | name = input_line_pointer; | |
12952 | c = get_symbol_end (); | |
12953 | symbolP = symbol_find_or_make (name); | |
12954 | S_SET_WEAK (symbolP); | |
12955 | *input_line_pointer = c; | |
12956 | ||
12957 | SKIP_WHITESPACE (); | |
12958 | ||
12959 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
12960 | { | |
12961 | if (S_IS_DEFINED (symbolP)) | |
12962 | { | |
956cd1d6 | 12963 | as_bad ("ignoring attempt to redefine symbol %s", |
252b5132 RH |
12964 | S_GET_NAME (symbolP)); |
12965 | ignore_rest_of_line (); | |
12966 | return; | |
12967 | } | |
bdaaa2e1 | 12968 | |
252b5132 RH |
12969 | if (*input_line_pointer == ',') |
12970 | { | |
12971 | ++input_line_pointer; | |
12972 | SKIP_WHITESPACE (); | |
12973 | } | |
bdaaa2e1 | 12974 | |
252b5132 RH |
12975 | expression (&exp); |
12976 | if (exp.X_op != O_symbol) | |
12977 | { | |
12978 | as_bad ("bad .weakext directive"); | |
98d3f06f | 12979 | ignore_rest_of_line (); |
252b5132 RH |
12980 | return; |
12981 | } | |
49309057 | 12982 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
12983 | } |
12984 | ||
12985 | demand_empty_rest_of_line (); | |
12986 | } | |
12987 | ||
12988 | /* Parse a register string into a number. Called from the ECOFF code | |
12989 | to parse .frame. The argument is non-zero if this is the frame | |
12990 | register, so that we can record it in mips_frame_reg. */ | |
12991 | ||
12992 | int | |
17a2f251 | 12993 | tc_get_register (int frame) |
252b5132 | 12994 | { |
707bfff6 | 12995 | unsigned int reg; |
252b5132 RH |
12996 | |
12997 | SKIP_WHITESPACE (); | |
707bfff6 TS |
12998 | if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®)) |
12999 | reg = 0; | |
252b5132 | 13000 | if (frame) |
7a621144 DJ |
13001 | { |
13002 | mips_frame_reg = reg != 0 ? reg : SP; | |
13003 | mips_frame_reg_valid = 1; | |
13004 | mips_cprestore_valid = 0; | |
13005 | } | |
252b5132 RH |
13006 | return reg; |
13007 | } | |
13008 | ||
13009 | valueT | |
17a2f251 | 13010 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
13011 | { |
13012 | int align = bfd_get_section_alignment (stdoutput, seg); | |
13013 | ||
13014 | #ifdef OBJ_ELF | |
13015 | /* We don't need to align ELF sections to the full alignment. | |
13016 | However, Irix 5 may prefer that we align them at least to a 16 | |
13017 | byte boundary. We don't bother to align the sections if we are | |
13018 | targeted for an embedded system. */ | |
13019 | if (strcmp (TARGET_OS, "elf") == 0) | |
13020 | return addr; | |
13021 | if (align > 4) | |
13022 | align = 4; | |
13023 | #endif | |
13024 | ||
13025 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
13026 | } | |
13027 | ||
13028 | /* Utility routine, called from above as well. If called while the | |
13029 | input file is still being read, it's only an approximation. (For | |
13030 | example, a symbol may later become defined which appeared to be | |
13031 | undefined earlier.) */ | |
13032 | ||
13033 | static int | |
17a2f251 | 13034 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
13035 | { |
13036 | if (sym == 0) | |
13037 | return 0; | |
13038 | ||
4d0d148d | 13039 | if (g_switch_value > 0) |
252b5132 RH |
13040 | { |
13041 | const char *symname; | |
13042 | int change; | |
13043 | ||
c9914766 | 13044 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
13045 | register. It can be if it is smaller than the -G size or if |
13046 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 13047 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
13048 | they can. */ |
13049 | symname = S_GET_NAME (sym); | |
13050 | if (symname != (const char *) NULL | |
13051 | && (strcmp (symname, "eprol") == 0 | |
13052 | || strcmp (symname, "etext") == 0 | |
13053 | || strcmp (symname, "_gp") == 0 | |
13054 | || strcmp (symname, "edata") == 0 | |
13055 | || strcmp (symname, "_fbss") == 0 | |
13056 | || strcmp (symname, "_fdata") == 0 | |
13057 | || strcmp (symname, "_ftext") == 0 | |
13058 | || strcmp (symname, "end") == 0 | |
13059 | || strcmp (symname, "_gp_disp") == 0)) | |
13060 | change = 1; | |
13061 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
13062 | && (0 | |
13063 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
13064 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
13065 | && (symbol_get_obj (sym)->ecoff_extern_size | |
13066 | <= g_switch_value)) | |
252b5132 RH |
13067 | #endif |
13068 | /* We must defer this decision until after the whole | |
13069 | file has been read, since there might be a .extern | |
13070 | after the first use of this symbol. */ | |
13071 | || (before_relaxing | |
13072 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 13073 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
13074 | #endif |
13075 | && S_GET_VALUE (sym) == 0) | |
13076 | || (S_GET_VALUE (sym) != 0 | |
13077 | && S_GET_VALUE (sym) <= g_switch_value))) | |
13078 | change = 0; | |
13079 | else | |
13080 | { | |
13081 | const char *segname; | |
13082 | ||
13083 | segname = segment_name (S_GET_SEGMENT (sym)); | |
13084 | assert (strcmp (segname, ".lit8") != 0 | |
13085 | && strcmp (segname, ".lit4") != 0); | |
13086 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
13087 | && strcmp (segname, ".sbss") != 0 |
13088 | && strncmp (segname, ".sdata.", 7) != 0 | |
13089 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); | |
252b5132 RH |
13090 | } |
13091 | return change; | |
13092 | } | |
13093 | else | |
c9914766 | 13094 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
13095 | return 1; |
13096 | } | |
13097 | ||
5919d012 RS |
13098 | |
13099 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
13100 | ||
13101 | static bfd_boolean | |
17a2f251 | 13102 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
13103 | { |
13104 | asection *symsec; | |
13105 | bfd_boolean linkonce; | |
13106 | ||
13107 | /* Handle the case of a symbol equated to another symbol. */ | |
13108 | while (symbol_equated_reloc_p (sym)) | |
13109 | { | |
13110 | symbolS *n; | |
13111 | ||
13112 | /* It's possible to get a loop here in a badly written | |
13113 | program. */ | |
13114 | n = symbol_get_value_expression (sym)->X_add_symbol; | |
13115 | if (n == sym) | |
13116 | break; | |
13117 | sym = n; | |
13118 | } | |
13119 | ||
13120 | symsec = S_GET_SEGMENT (sym); | |
13121 | ||
13122 | /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */ | |
13123 | linkonce = FALSE; | |
13124 | if (symsec != segtype && ! S_IS_LOCAL (sym)) | |
13125 | { | |
13126 | if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE) | |
13127 | != 0) | |
13128 | linkonce = TRUE; | |
13129 | ||
13130 | /* The GNU toolchain uses an extension for ELF: a section | |
13131 | beginning with the magic string .gnu.linkonce is a linkonce | |
13132 | section. */ | |
13133 | if (strncmp (segment_name (symsec), ".gnu.linkonce", | |
13134 | sizeof ".gnu.linkonce" - 1) == 0) | |
13135 | linkonce = TRUE; | |
13136 | } | |
13137 | ||
13138 | /* This must duplicate the test in adjust_reloc_syms. */ | |
13139 | return (symsec != &bfd_und_section | |
13140 | && symsec != &bfd_abs_section | |
13141 | && ! bfd_is_com_section (symsec) | |
13142 | && !linkonce | |
13143 | #ifdef OBJ_ELF | |
13144 | /* A global or weak symbol is treated as external. */ | |
13145 | && (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
3e722fb5 | 13146 | || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym))) |
5919d012 RS |
13147 | #endif |
13148 | ); | |
13149 | } | |
13150 | ||
13151 | ||
252b5132 RH |
13152 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
13153 | extended opcode. SEC is the section the frag is in. */ | |
13154 | ||
13155 | static int | |
17a2f251 | 13156 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
13157 | { |
13158 | int type; | |
13159 | register const struct mips16_immed_operand *op; | |
13160 | offsetT val; | |
13161 | int mintiny, maxtiny; | |
13162 | segT symsec; | |
98aa84af | 13163 | fragS *sym_frag; |
252b5132 RH |
13164 | |
13165 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
13166 | return 0; | |
13167 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
13168 | return 1; | |
13169 | ||
13170 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
13171 | op = mips16_immed_operands; | |
13172 | while (op->type != type) | |
13173 | { | |
13174 | ++op; | |
13175 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
13176 | } | |
13177 | ||
13178 | if (op->unsp) | |
13179 | { | |
13180 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
13181 | { | |
13182 | mintiny = 1; | |
13183 | maxtiny = 1 << op->nbits; | |
13184 | } | |
13185 | else | |
13186 | { | |
13187 | mintiny = 0; | |
13188 | maxtiny = (1 << op->nbits) - 1; | |
13189 | } | |
13190 | } | |
13191 | else | |
13192 | { | |
13193 | mintiny = - (1 << (op->nbits - 1)); | |
13194 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
13195 | } | |
13196 | ||
98aa84af | 13197 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 13198 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 13199 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
13200 | |
13201 | if (op->pcrel) | |
13202 | { | |
13203 | addressT addr; | |
13204 | ||
13205 | /* We won't have the section when we are called from | |
13206 | mips_relax_frag. However, we will always have been called | |
13207 | from md_estimate_size_before_relax first. If this is a | |
13208 | branch to a different section, we mark it as such. If SEC is | |
13209 | NULL, and the frag is not marked, then it must be a branch to | |
13210 | the same section. */ | |
13211 | if (sec == NULL) | |
13212 | { | |
13213 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
13214 | return 1; | |
13215 | } | |
13216 | else | |
13217 | { | |
98aa84af | 13218 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
13219 | if (symsec != sec) |
13220 | { | |
13221 | fragp->fr_subtype = | |
13222 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
13223 | ||
13224 | /* FIXME: We should support this, and let the linker | |
13225 | catch branches and loads that are out of range. */ | |
13226 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
13227 | _("unsupported PC relative reference to different section")); | |
13228 | ||
13229 | return 1; | |
13230 | } | |
98aa84af AM |
13231 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
13232 | /* Assume non-extended on the first relaxation pass. | |
13233 | The address we have calculated will be bogus if this is | |
13234 | a forward branch to another frag, as the forward frag | |
13235 | will have fr_address == 0. */ | |
13236 | return 0; | |
252b5132 RH |
13237 | } |
13238 | ||
13239 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
13240 | the same section. If the relax_marker of the symbol fragment |
13241 | differs from the relax_marker of this fragment, we have not | |
13242 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
13243 | in STRETCH in order to get a better estimate of the address. |
13244 | This particularly matters because of the shift bits. */ | |
13245 | if (stretch != 0 | |
98aa84af | 13246 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
13247 | { |
13248 | fragS *f; | |
13249 | ||
13250 | /* Adjust stretch for any alignment frag. Note that if have | |
13251 | been expanding the earlier code, the symbol may be | |
13252 | defined in what appears to be an earlier frag. FIXME: | |
13253 | This doesn't handle the fr_subtype field, which specifies | |
13254 | a maximum number of bytes to skip when doing an | |
13255 | alignment. */ | |
98aa84af | 13256 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
13257 | { |
13258 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
13259 | { | |
13260 | if (stretch < 0) | |
13261 | stretch = - ((- stretch) | |
13262 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
13263 | else | |
13264 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
13265 | if (stretch == 0) | |
13266 | break; | |
13267 | } | |
13268 | } | |
13269 | if (f != NULL) | |
13270 | val += stretch; | |
13271 | } | |
13272 | ||
13273 | addr = fragp->fr_address + fragp->fr_fix; | |
13274 | ||
13275 | /* The base address rules are complicated. The base address of | |
13276 | a branch is the following instruction. The base address of a | |
13277 | PC relative load or add is the instruction itself, but if it | |
13278 | is in a delay slot (in which case it can not be extended) use | |
13279 | the address of the instruction whose delay slot it is in. */ | |
13280 | if (type == 'p' || type == 'q') | |
13281 | { | |
13282 | addr += 2; | |
13283 | ||
13284 | /* If we are currently assuming that this frag should be | |
13285 | extended, then, the current address is two bytes | |
bdaaa2e1 | 13286 | higher. */ |
252b5132 RH |
13287 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
13288 | addr += 2; | |
13289 | ||
13290 | /* Ignore the low bit in the target, since it will be set | |
13291 | for a text label. */ | |
13292 | if ((val & 1) != 0) | |
13293 | --val; | |
13294 | } | |
13295 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
13296 | addr -= 4; | |
13297 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
13298 | addr -= 2; | |
13299 | ||
13300 | val -= addr & ~ ((1 << op->shift) - 1); | |
13301 | ||
13302 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
13303 | if (type == 'p' || type == 'q') | |
13304 | val /= 2; | |
13305 | ||
13306 | /* If any of the shifted bits are set, we must use an extended | |
13307 | opcode. If the address depends on the size of this | |
13308 | instruction, this can lead to a loop, so we arrange to always | |
13309 | use an extended opcode. We only check this when we are in | |
13310 | the main relaxation loop, when SEC is NULL. */ | |
13311 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
13312 | { | |
13313 | fragp->fr_subtype = | |
13314 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
13315 | return 1; | |
13316 | } | |
13317 | ||
13318 | /* If we are about to mark a frag as extended because the value | |
13319 | is precisely maxtiny + 1, then there is a chance of an | |
13320 | infinite loop as in the following code: | |
13321 | la $4,foo | |
13322 | .skip 1020 | |
13323 | .align 2 | |
13324 | foo: | |
13325 | In this case when the la is extended, foo is 0x3fc bytes | |
13326 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
13327 | the la must be extended. To avoid this loop, we mark the | |
13328 | frag as extended if it was small, and is about to become | |
13329 | extended with a value of maxtiny + 1. */ | |
13330 | if (val == ((maxtiny + 1) << op->shift) | |
13331 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
13332 | && sec == NULL) | |
13333 | { | |
13334 | fragp->fr_subtype = | |
13335 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
13336 | return 1; | |
13337 | } | |
13338 | } | |
13339 | else if (symsec != absolute_section && sec != NULL) | |
13340 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
13341 | ||
13342 | if ((val & ((1 << op->shift) - 1)) != 0 | |
13343 | || val < (mintiny << op->shift) | |
13344 | || val > (maxtiny << op->shift)) | |
13345 | return 1; | |
13346 | else | |
13347 | return 0; | |
13348 | } | |
13349 | ||
4a6a3df4 AO |
13350 | /* Compute the length of a branch sequence, and adjust the |
13351 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
13352 | worst-case length is computed, with UPDATE being used to indicate | |
13353 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
13354 | branch is to be computed. */ | |
13355 | static int | |
17a2f251 | 13356 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 13357 | { |
b34976b6 | 13358 | bfd_boolean toofar; |
4a6a3df4 AO |
13359 | int length; |
13360 | ||
13361 | if (fragp | |
13362 | && S_IS_DEFINED (fragp->fr_symbol) | |
13363 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
13364 | { | |
13365 | addressT addr; | |
13366 | offsetT val; | |
13367 | ||
13368 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
13369 | ||
13370 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
13371 | ||
13372 | val -= addr; | |
13373 | ||
13374 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
13375 | } | |
13376 | else if (fragp) | |
13377 | /* If the symbol is not defined or it's in a different segment, | |
13378 | assume the user knows what's going on and emit a short | |
13379 | branch. */ | |
b34976b6 | 13380 | toofar = FALSE; |
4a6a3df4 | 13381 | else |
b34976b6 | 13382 | toofar = TRUE; |
4a6a3df4 AO |
13383 | |
13384 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
13385 | fragp->fr_subtype | |
af6ae2ad | 13386 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype), |
4a6a3df4 AO |
13387 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
13388 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
13389 | toofar); | |
13390 | ||
13391 | length = 4; | |
13392 | if (toofar) | |
13393 | { | |
13394 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
13395 | length += 8; | |
13396 | ||
13397 | if (mips_pic != NO_PIC) | |
13398 | { | |
13399 | /* Additional space for PIC loading of target address. */ | |
13400 | length += 8; | |
13401 | if (mips_opts.isa == ISA_MIPS1) | |
13402 | /* Additional space for $at-stabilizing nop. */ | |
13403 | length += 4; | |
13404 | } | |
13405 | ||
13406 | /* If branch is conditional. */ | |
13407 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
13408 | length += 8; | |
13409 | } | |
b34976b6 | 13410 | |
4a6a3df4 AO |
13411 | return length; |
13412 | } | |
13413 | ||
252b5132 RH |
13414 | /* Estimate the size of a frag before relaxing. Unless this is the |
13415 | mips16, we are not really relaxing here, and the final size is | |
13416 | encoded in the subtype information. For the mips16, we have to | |
13417 | decide whether we are using an extended opcode or not. */ | |
13418 | ||
252b5132 | 13419 | int |
17a2f251 | 13420 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 13421 | { |
5919d012 | 13422 | int change; |
252b5132 | 13423 | |
4a6a3df4 AO |
13424 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13425 | { | |
13426 | ||
b34976b6 AM |
13427 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
13428 | ||
4a6a3df4 AO |
13429 | return fragp->fr_var; |
13430 | } | |
13431 | ||
252b5132 | 13432 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
13433 | /* We don't want to modify the EXTENDED bit here; it might get us |
13434 | into infinite loops. We change it only in mips_relax_frag(). */ | |
13435 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 RH |
13436 | |
13437 | if (mips_pic == NO_PIC) | |
5919d012 | 13438 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 13439 | else if (mips_pic == SVR4_PIC) |
5919d012 | 13440 | change = pic_need_relax (fragp->fr_symbol, segtype); |
0a44bf69 RS |
13441 | else if (mips_pic == VXWORKS_PIC) |
13442 | /* For vxworks, GOT16 relocations never have a corresponding LO16. */ | |
13443 | change = 0; | |
252b5132 RH |
13444 | else |
13445 | abort (); | |
13446 | ||
13447 | if (change) | |
13448 | { | |
4d7206a2 | 13449 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 13450 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 13451 | } |
4d7206a2 RS |
13452 | else |
13453 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
13454 | } |
13455 | ||
13456 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 13457 | should be converted into a reloc against a section. */ |
252b5132 RH |
13458 | |
13459 | int | |
17a2f251 | 13460 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 13461 | { |
de7e6852 RS |
13462 | /* Don't adjust MIPS16 jump relocations, so we don't have to worry |
13463 | about the format of the offset in the .o file. */ | |
252b5132 RH |
13464 | if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) |
13465 | return 0; | |
a161fe53 | 13466 | |
252b5132 RH |
13467 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
13468 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
13469 | return 0; | |
a161fe53 | 13470 | |
252b5132 RH |
13471 | if (fixp->fx_addsy == NULL) |
13472 | return 1; | |
a161fe53 | 13473 | |
de7e6852 RS |
13474 | /* If symbol SYM is in a mergeable section, relocations of the form |
13475 | SYM + 0 can usually be made section-relative. The mergeable data | |
13476 | is then identified by the section offset rather than by the symbol. | |
13477 | ||
13478 | However, if we're generating REL LO16 relocations, the offset is split | |
13479 | between the LO16 and parterning high part relocation. The linker will | |
13480 | need to recalculate the complete offset in order to correctly identify | |
13481 | the merge data. | |
13482 | ||
13483 | The linker has traditionally not looked for the parterning high part | |
13484 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be | |
13485 | placed anywhere. Rather than break backwards compatibility by changing | |
13486 | this, it seems better not to force the issue, and instead keep the | |
13487 | original symbol. This will work with either linker behavior. */ | |
704803a9 MR |
13488 | if ((fixp->fx_r_type == BFD_RELOC_LO16 |
13489 | || fixp->fx_r_type == BFD_RELOC_MIPS16_LO16 | |
13490 | || reloc_needs_lo_p (fixp->fx_r_type)) | |
de7e6852 RS |
13491 | && HAVE_IN_PLACE_ADDENDS |
13492 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
13493 | return 0; | |
13494 | ||
252b5132 | 13495 | #ifdef OBJ_ELF |
de7e6852 RS |
13496 | /* Don't adjust relocations against mips16 symbols, so that the linker |
13497 | can find them if it needs to set up a stub. */ | |
252b5132 RH |
13498 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
13499 | && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 | |
13500 | && fixp->fx_subsy == NULL) | |
13501 | return 0; | |
13502 | #endif | |
a161fe53 | 13503 | |
252b5132 RH |
13504 | return 1; |
13505 | } | |
13506 | ||
13507 | /* Translate internal representation of relocation info to BFD target | |
13508 | format. */ | |
13509 | ||
13510 | arelent ** | |
17a2f251 | 13511 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
13512 | { |
13513 | static arelent *retval[4]; | |
13514 | arelent *reloc; | |
13515 | bfd_reloc_code_real_type code; | |
13516 | ||
4b0cff4e TS |
13517 | memset (retval, 0, sizeof(retval)); |
13518 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
13519 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
13520 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
13521 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
13522 | ||
bad36eac DJ |
13523 | if (fixp->fx_pcrel) |
13524 | { | |
13525 | assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2); | |
13526 | ||
13527 | /* At this point, fx_addnumber is "symbol offset - pcrel address". | |
13528 | Relocations want only the symbol offset. */ | |
13529 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
13530 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
13531 | { | |
13532 | /* A gruesome hack which is a result of the gruesome gas | |
13533 | reloc handling. What's worse, for COFF (as opposed to | |
13534 | ECOFF), we might need yet another copy of reloc->address. | |
13535 | See bfd_install_relocation. */ | |
13536 | reloc->addend += reloc->address; | |
13537 | } | |
13538 | } | |
13539 | else | |
13540 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 13541 | |
438c16b8 TS |
13542 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
13543 | entry to be used in the relocation's section offset. */ | |
13544 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
13545 | { |
13546 | reloc->address = reloc->addend; | |
13547 | reloc->addend = 0; | |
13548 | } | |
13549 | ||
252b5132 | 13550 | code = fixp->fx_r_type; |
252b5132 | 13551 | |
bad36eac | 13552 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
252b5132 RH |
13553 | if (reloc->howto == NULL) |
13554 | { | |
13555 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
13556 | _("Can not represent %s relocation in this object file format"), | |
13557 | bfd_get_reloc_code_name (code)); | |
13558 | retval[0] = NULL; | |
13559 | } | |
13560 | ||
13561 | return retval; | |
13562 | } | |
13563 | ||
13564 | /* Relax a machine dependent frag. This returns the amount by which | |
13565 | the current size of the frag should change. */ | |
13566 | ||
13567 | int | |
17a2f251 | 13568 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 13569 | { |
4a6a3df4 AO |
13570 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13571 | { | |
13572 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
13573 | |
13574 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
13575 | |
13576 | return fragp->fr_var - old_var; | |
13577 | } | |
13578 | ||
252b5132 RH |
13579 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
13580 | return 0; | |
13581 | ||
c4e7957c | 13582 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
13583 | { |
13584 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13585 | return 0; | |
13586 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
13587 | return 2; | |
13588 | } | |
13589 | else | |
13590 | { | |
13591 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13592 | return 0; | |
13593 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
13594 | return -2; | |
13595 | } | |
13596 | ||
13597 | return 0; | |
13598 | } | |
13599 | ||
13600 | /* Convert a machine dependent frag. */ | |
13601 | ||
13602 | void | |
17a2f251 | 13603 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 13604 | { |
4a6a3df4 AO |
13605 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13606 | { | |
13607 | bfd_byte *buf; | |
13608 | unsigned long insn; | |
13609 | expressionS exp; | |
13610 | fixS *fixp; | |
b34976b6 | 13611 | |
4a6a3df4 AO |
13612 | buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; |
13613 | ||
13614 | if (target_big_endian) | |
13615 | insn = bfd_getb32 (buf); | |
13616 | else | |
13617 | insn = bfd_getl32 (buf); | |
b34976b6 | 13618 | |
4a6a3df4 AO |
13619 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
13620 | { | |
13621 | /* We generate a fixup instead of applying it right now | |
13622 | because, if there are linker relaxations, we're going to | |
13623 | need the relocations. */ | |
13624 | exp.X_op = O_symbol; | |
13625 | exp.X_add_symbol = fragp->fr_symbol; | |
13626 | exp.X_add_number = fragp->fr_offset; | |
13627 | ||
13628 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
bad36eac | 13629 | 4, &exp, 1, BFD_RELOC_16_PCREL_S2); |
4a6a3df4 AO |
13630 | fixp->fx_file = fragp->fr_file; |
13631 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 13632 | |
2132e3a3 | 13633 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13634 | buf += 4; |
13635 | } | |
13636 | else | |
13637 | { | |
13638 | int i; | |
13639 | ||
13640 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
13641 | _("relaxed out-of-range branch into a jump")); | |
13642 | ||
13643 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
13644 | goto uncond; | |
13645 | ||
13646 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13647 | { | |
13648 | /* Reverse the branch. */ | |
13649 | switch ((insn >> 28) & 0xf) | |
13650 | { | |
13651 | case 4: | |
13652 | /* bc[0-3][tf]l? and bc1any[24][ft] instructions can | |
13653 | have the condition reversed by tweaking a single | |
13654 | bit, and their opcodes all have 0x4???????. */ | |
13655 | assert ((insn & 0xf1000000) == 0x41000000); | |
13656 | insn ^= 0x00010000; | |
13657 | break; | |
13658 | ||
13659 | case 0: | |
13660 | /* bltz 0x04000000 bgez 0x04010000 | |
13661 | bltzal 0x04100000 bgezal 0x04110000 */ | |
13662 | assert ((insn & 0xfc0e0000) == 0x04000000); | |
13663 | insn ^= 0x00010000; | |
13664 | break; | |
b34976b6 | 13665 | |
4a6a3df4 AO |
13666 | case 1: |
13667 | /* beq 0x10000000 bne 0x14000000 | |
13668 | blez 0x18000000 bgtz 0x1c000000 */ | |
13669 | insn ^= 0x04000000; | |
13670 | break; | |
13671 | ||
13672 | default: | |
13673 | abort (); | |
13674 | } | |
13675 | } | |
13676 | ||
13677 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
13678 | { | |
13679 | /* Clear the and-link bit. */ | |
13680 | assert ((insn & 0xfc1c0000) == 0x04100000); | |
13681 | ||
13682 | /* bltzal 0x04100000 bgezal 0x04110000 | |
13683 | bltzall 0x04120000 bgezall 0x04130000 */ | |
13684 | insn &= ~0x00100000; | |
13685 | } | |
13686 | ||
13687 | /* Branch over the branch (if the branch was likely) or the | |
13688 | full jump (not likely case). Compute the offset from the | |
13689 | current instruction to branch to. */ | |
13690 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13691 | i = 16; | |
13692 | else | |
13693 | { | |
13694 | /* How many bytes in instructions we've already emitted? */ | |
13695 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
13696 | /* How many bytes in instructions from here to the end? */ | |
13697 | i = fragp->fr_var - i; | |
13698 | } | |
13699 | /* Convert to instruction count. */ | |
13700 | i >>= 2; | |
13701 | /* Branch counts from the next instruction. */ | |
b34976b6 | 13702 | i--; |
4a6a3df4 AO |
13703 | insn |= i; |
13704 | /* Branch over the jump. */ | |
2132e3a3 | 13705 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13706 | buf += 4; |
13707 | ||
13708 | /* Nop */ | |
2132e3a3 | 13709 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
13710 | buf += 4; |
13711 | ||
13712 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13713 | { | |
13714 | /* beql $0, $0, 2f */ | |
13715 | insn = 0x50000000; | |
13716 | /* Compute the PC offset from the current instruction to | |
13717 | the end of the variable frag. */ | |
13718 | /* How many bytes in instructions we've already emitted? */ | |
13719 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
13720 | /* How many bytes in instructions from here to the end? */ | |
13721 | i = fragp->fr_var - i; | |
13722 | /* Convert to instruction count. */ | |
13723 | i >>= 2; | |
13724 | /* Don't decrement i, because we want to branch over the | |
13725 | delay slot. */ | |
13726 | ||
13727 | insn |= i; | |
2132e3a3 | 13728 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13729 | buf += 4; |
13730 | ||
2132e3a3 | 13731 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
13732 | buf += 4; |
13733 | } | |
13734 | ||
13735 | uncond: | |
13736 | if (mips_pic == NO_PIC) | |
13737 | { | |
13738 | /* j or jal. */ | |
13739 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
13740 | ? 0x0c000000 : 0x08000000); | |
13741 | exp.X_op = O_symbol; | |
13742 | exp.X_add_symbol = fragp->fr_symbol; | |
13743 | exp.X_add_number = fragp->fr_offset; | |
13744 | ||
13745 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13746 | 4, &exp, 0, BFD_RELOC_MIPS_JMP); | |
13747 | fixp->fx_file = fragp->fr_file; | |
13748 | fixp->fx_line = fragp->fr_line; | |
13749 | ||
2132e3a3 | 13750 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13751 | buf += 4; |
13752 | } | |
13753 | else | |
13754 | { | |
13755 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ | |
13756 | insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000; | |
13757 | exp.X_op = O_symbol; | |
13758 | exp.X_add_symbol = fragp->fr_symbol; | |
13759 | exp.X_add_number = fragp->fr_offset; | |
13760 | ||
13761 | if (fragp->fr_offset) | |
13762 | { | |
13763 | exp.X_add_symbol = make_expr_symbol (&exp); | |
13764 | exp.X_add_number = 0; | |
13765 | } | |
13766 | ||
13767 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13768 | 4, &exp, 0, BFD_RELOC_MIPS_GOT16); | |
13769 | fixp->fx_file = fragp->fr_file; | |
13770 | fixp->fx_line = fragp->fr_line; | |
13771 | ||
2132e3a3 | 13772 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 | 13773 | buf += 4; |
b34976b6 | 13774 | |
4a6a3df4 AO |
13775 | if (mips_opts.isa == ISA_MIPS1) |
13776 | { | |
13777 | /* nop */ | |
2132e3a3 | 13778 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
13779 | buf += 4; |
13780 | } | |
13781 | ||
13782 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
13783 | insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000; | |
13784 | ||
13785 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
13786 | 4, &exp, 0, BFD_RELOC_LO16); | |
13787 | fixp->fx_file = fragp->fr_file; | |
13788 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 13789 | |
2132e3a3 | 13790 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13791 | buf += 4; |
13792 | ||
13793 | /* j(al)r $at. */ | |
13794 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
13795 | insn = 0x0020f809; | |
13796 | else | |
13797 | insn = 0x00200008; | |
13798 | ||
2132e3a3 | 13799 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13800 | buf += 4; |
13801 | } | |
13802 | } | |
13803 | ||
13804 | assert (buf == (bfd_byte *)fragp->fr_literal | |
13805 | + fragp->fr_fix + fragp->fr_var); | |
13806 | ||
13807 | fragp->fr_fix += fragp->fr_var; | |
13808 | ||
13809 | return; | |
13810 | } | |
13811 | ||
252b5132 RH |
13812 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
13813 | { | |
13814 | int type; | |
13815 | register const struct mips16_immed_operand *op; | |
b34976b6 | 13816 | bfd_boolean small, ext; |
252b5132 RH |
13817 | offsetT val; |
13818 | bfd_byte *buf; | |
13819 | unsigned long insn; | |
b34976b6 | 13820 | bfd_boolean use_extend; |
252b5132 RH |
13821 | unsigned short extend; |
13822 | ||
13823 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
13824 | op = mips16_immed_operands; | |
13825 | while (op->type != type) | |
13826 | ++op; | |
13827 | ||
13828 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13829 | { | |
b34976b6 AM |
13830 | small = FALSE; |
13831 | ext = TRUE; | |
252b5132 RH |
13832 | } |
13833 | else | |
13834 | { | |
b34976b6 AM |
13835 | small = TRUE; |
13836 | ext = FALSE; | |
252b5132 RH |
13837 | } |
13838 | ||
6386f3a7 | 13839 | resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
13840 | val = S_GET_VALUE (fragp->fr_symbol); |
13841 | if (op->pcrel) | |
13842 | { | |
13843 | addressT addr; | |
13844 | ||
13845 | addr = fragp->fr_address + fragp->fr_fix; | |
13846 | ||
13847 | /* The rules for the base address of a PC relative reloc are | |
13848 | complicated; see mips16_extended_frag. */ | |
13849 | if (type == 'p' || type == 'q') | |
13850 | { | |
13851 | addr += 2; | |
13852 | if (ext) | |
13853 | addr += 2; | |
13854 | /* Ignore the low bit in the target, since it will be | |
13855 | set for a text label. */ | |
13856 | if ((val & 1) != 0) | |
13857 | --val; | |
13858 | } | |
13859 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
13860 | addr -= 4; | |
13861 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
13862 | addr -= 2; | |
13863 | ||
13864 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
13865 | val -= addr; | |
13866 | ||
13867 | /* Make sure the section winds up with the alignment we have | |
13868 | assumed. */ | |
13869 | if (op->shift > 0) | |
13870 | record_alignment (asec, op->shift); | |
13871 | } | |
13872 | ||
13873 | if (ext | |
13874 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
13875 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
13876 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
13877 | _("extended instruction in delay slot")); | |
13878 | ||
13879 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
13880 | ||
13881 | if (target_big_endian) | |
13882 | insn = bfd_getb16 (buf); | |
13883 | else | |
13884 | insn = bfd_getl16 (buf); | |
13885 | ||
13886 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
13887 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
13888 | small, ext, &insn, &use_extend, &extend); | |
13889 | ||
13890 | if (use_extend) | |
13891 | { | |
2132e3a3 | 13892 | md_number_to_chars ((char *) buf, 0xf000 | extend, 2); |
252b5132 RH |
13893 | fragp->fr_fix += 2; |
13894 | buf += 2; | |
13895 | } | |
13896 | ||
2132e3a3 | 13897 | md_number_to_chars ((char *) buf, insn, 2); |
252b5132 RH |
13898 | fragp->fr_fix += 2; |
13899 | buf += 2; | |
13900 | } | |
13901 | else | |
13902 | { | |
4d7206a2 RS |
13903 | int first, second; |
13904 | fixS *fixp; | |
252b5132 | 13905 | |
4d7206a2 RS |
13906 | first = RELAX_FIRST (fragp->fr_subtype); |
13907 | second = RELAX_SECOND (fragp->fr_subtype); | |
13908 | fixp = (fixS *) fragp->fr_opcode; | |
252b5132 | 13909 | |
584892a6 RS |
13910 | /* Possibly emit a warning if we've chosen the longer option. */ |
13911 | if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0) | |
13912 | == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0)) | |
13913 | { | |
13914 | const char *msg = macro_warning (fragp->fr_subtype); | |
13915 | if (msg != 0) | |
13916 | as_warn_where (fragp->fr_file, fragp->fr_line, msg); | |
13917 | } | |
13918 | ||
4d7206a2 RS |
13919 | /* Go through all the fixups for the first sequence. Disable them |
13920 | (by marking them as done) if we're going to use the second | |
13921 | sequence instead. */ | |
13922 | while (fixp | |
13923 | && fixp->fx_frag == fragp | |
13924 | && fixp->fx_where < fragp->fr_fix - second) | |
13925 | { | |
13926 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13927 | fixp->fx_done = 1; | |
13928 | fixp = fixp->fx_next; | |
13929 | } | |
252b5132 | 13930 | |
4d7206a2 RS |
13931 | /* Go through the fixups for the second sequence. Disable them if |
13932 | we're going to use the first sequence, otherwise adjust their | |
13933 | addresses to account for the relaxation. */ | |
13934 | while (fixp && fixp->fx_frag == fragp) | |
13935 | { | |
13936 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13937 | fixp->fx_where -= first; | |
13938 | else | |
13939 | fixp->fx_done = 1; | |
13940 | fixp = fixp->fx_next; | |
13941 | } | |
13942 | ||
13943 | /* Now modify the frag contents. */ | |
13944 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13945 | { | |
13946 | char *start; | |
13947 | ||
13948 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
13949 | memmove (start, start + first, second); | |
13950 | fragp->fr_fix -= first; | |
13951 | } | |
13952 | else | |
13953 | fragp->fr_fix -= second; | |
252b5132 RH |
13954 | } |
13955 | } | |
13956 | ||
13957 | #ifdef OBJ_ELF | |
13958 | ||
13959 | /* This function is called after the relocs have been generated. | |
13960 | We've been storing mips16 text labels as odd. Here we convert them | |
13961 | back to even for the convenience of the debugger. */ | |
13962 | ||
13963 | void | |
17a2f251 | 13964 | mips_frob_file_after_relocs (void) |
252b5132 RH |
13965 | { |
13966 | asymbol **syms; | |
13967 | unsigned int count, i; | |
13968 | ||
13969 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
13970 | return; | |
13971 | ||
13972 | syms = bfd_get_outsymbols (stdoutput); | |
13973 | count = bfd_get_symcount (stdoutput); | |
13974 | for (i = 0; i < count; i++, syms++) | |
13975 | { | |
13976 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
13977 | && ((*syms)->value & 1) != 0) | |
13978 | { | |
13979 | (*syms)->value &= ~1; | |
13980 | /* If the symbol has an odd size, it was probably computed | |
13981 | incorrectly, so adjust that as well. */ | |
13982 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
13983 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
13984 | } | |
13985 | } | |
13986 | } | |
13987 | ||
13988 | #endif | |
13989 | ||
13990 | /* This function is called whenever a label is defined. It is used | |
13991 | when handling branch delays; if a branch has a label, we assume we | |
13992 | can not move it. */ | |
13993 | ||
13994 | void | |
17a2f251 | 13995 | mips_define_label (symbolS *sym) |
252b5132 RH |
13996 | { |
13997 | struct insn_label_list *l; | |
13998 | ||
13999 | if (free_insn_labels == NULL) | |
14000 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
14001 | else | |
14002 | { | |
14003 | l = free_insn_labels; | |
14004 | free_insn_labels = l->next; | |
14005 | } | |
14006 | ||
14007 | l->label = sym; | |
14008 | l->next = insn_labels; | |
14009 | insn_labels = l; | |
07a53e5c RH |
14010 | |
14011 | #ifdef OBJ_ELF | |
14012 | dwarf2_emit_label (sym); | |
14013 | #endif | |
252b5132 RH |
14014 | } |
14015 | \f | |
14016 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
14017 | ||
14018 | /* Some special processing for a MIPS ELF file. */ | |
14019 | ||
14020 | void | |
17a2f251 | 14021 | mips_elf_final_processing (void) |
252b5132 RH |
14022 | { |
14023 | /* Write out the register information. */ | |
316f5878 | 14024 | if (mips_abi != N64_ABI) |
252b5132 RH |
14025 | { |
14026 | Elf32_RegInfo s; | |
14027 | ||
14028 | s.ri_gprmask = mips_gprmask; | |
14029 | s.ri_cprmask[0] = mips_cprmask[0]; | |
14030 | s.ri_cprmask[1] = mips_cprmask[1]; | |
14031 | s.ri_cprmask[2] = mips_cprmask[2]; | |
14032 | s.ri_cprmask[3] = mips_cprmask[3]; | |
14033 | /* The gp_value field is set by the MIPS ELF backend. */ | |
14034 | ||
14035 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
14036 | ((Elf32_External_RegInfo *) | |
14037 | mips_regmask_frag)); | |
14038 | } | |
14039 | else | |
14040 | { | |
14041 | Elf64_Internal_RegInfo s; | |
14042 | ||
14043 | s.ri_gprmask = mips_gprmask; | |
14044 | s.ri_pad = 0; | |
14045 | s.ri_cprmask[0] = mips_cprmask[0]; | |
14046 | s.ri_cprmask[1] = mips_cprmask[1]; | |
14047 | s.ri_cprmask[2] = mips_cprmask[2]; | |
14048 | s.ri_cprmask[3] = mips_cprmask[3]; | |
14049 | /* The gp_value field is set by the MIPS ELF backend. */ | |
14050 | ||
14051 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
14052 | ((Elf64_External_RegInfo *) | |
14053 | mips_regmask_frag)); | |
14054 | } | |
14055 | ||
14056 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
14057 | sort of BFD interface for this. */ | |
14058 | if (mips_any_noreorder) | |
14059 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
14060 | if (mips_pic != NO_PIC) | |
143d77c5 | 14061 | { |
252b5132 | 14062 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
14063 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
14064 | } | |
14065 | if (mips_abicalls) | |
14066 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 14067 | |
98d3f06f | 14068 | /* Set MIPS ELF flags for ASEs. */ |
74cd071d CF |
14069 | /* We may need to define a new flag for DSP ASE, and set this flag when |
14070 | file_ase_dsp is true. */ | |
ef2e4d86 CF |
14071 | /* We may need to define a new flag for MT ASE, and set this flag when |
14072 | file_ase_mt is true. */ | |
a4672219 TS |
14073 | if (file_ase_mips16) |
14074 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
1f25f5d3 CD |
14075 | #if 0 /* XXX FIXME */ |
14076 | if (file_ase_mips3d) | |
14077 | elf_elfheader (stdoutput)->e_flags |= ???; | |
14078 | #endif | |
deec1734 CD |
14079 | if (file_ase_mdmx) |
14080 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; | |
1f25f5d3 | 14081 | |
bdaaa2e1 | 14082 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 14083 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 14084 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 14085 | else if (mips_abi == O64_ABI) |
252b5132 | 14086 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 14087 | else if (mips_abi == EABI_ABI) |
252b5132 | 14088 | { |
316f5878 | 14089 | if (!file_mips_gp32) |
252b5132 RH |
14090 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
14091 | else | |
14092 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
14093 | } | |
316f5878 | 14094 | else if (mips_abi == N32_ABI) |
be00bddd TS |
14095 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
14096 | ||
c9914766 | 14097 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
14098 | |
14099 | if (mips_32bitmode) | |
14100 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
ad3fea08 TS |
14101 | |
14102 | #if 0 /* XXX FIXME */ | |
14103 | /* 32 bit code with 64 bit FP registers. */ | |
14104 | if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
14105 | elf_elfheader (stdoutput)->e_flags |= ???; | |
14106 | #endif | |
252b5132 RH |
14107 | } |
14108 | ||
14109 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
14110 | \f | |
beae10d5 | 14111 | typedef struct proc { |
9b2f1d35 EC |
14112 | symbolS *func_sym; |
14113 | symbolS *func_end_sym; | |
beae10d5 KH |
14114 | unsigned long reg_mask; |
14115 | unsigned long reg_offset; | |
14116 | unsigned long fpreg_mask; | |
14117 | unsigned long fpreg_offset; | |
14118 | unsigned long frame_offset; | |
14119 | unsigned long frame_reg; | |
14120 | unsigned long pc_reg; | |
14121 | } procS; | |
252b5132 RH |
14122 | |
14123 | static procS cur_proc; | |
14124 | static procS *cur_proc_ptr; | |
14125 | static int numprocs; | |
14126 | ||
0a9ef439 | 14127 | /* Fill in an rs_align_code fragment. */ |
a19d8eb0 | 14128 | |
0a9ef439 | 14129 | void |
17a2f251 | 14130 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 14131 | { |
0a9ef439 RH |
14132 | if (fragp->fr_type != rs_align_code) |
14133 | return; | |
14134 | ||
14135 | if (mips_opts.mips16) | |
a19d8eb0 CP |
14136 | { |
14137 | static const unsigned char be_nop[] = { 0x65, 0x00 }; | |
14138 | static const unsigned char le_nop[] = { 0x00, 0x65 }; | |
14139 | ||
0a9ef439 RH |
14140 | int bytes; |
14141 | char *p; | |
a19d8eb0 | 14142 | |
0a9ef439 RH |
14143 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
14144 | p = fragp->fr_literal + fragp->fr_fix; | |
14145 | ||
14146 | if (bytes & 1) | |
14147 | { | |
14148 | *p++ = 0; | |
f9419b05 | 14149 | fragp->fr_fix++; |
0a9ef439 RH |
14150 | } |
14151 | ||
14152 | memcpy (p, (target_big_endian ? be_nop : le_nop), 2); | |
14153 | fragp->fr_var = 2; | |
a19d8eb0 CP |
14154 | } |
14155 | ||
0a9ef439 | 14156 | /* For mips32, a nop is a zero, which we trivially get by doing nothing. */ |
a19d8eb0 CP |
14157 | } |
14158 | ||
252b5132 | 14159 | static void |
17a2f251 | 14160 | md_obj_begin (void) |
252b5132 RH |
14161 | { |
14162 | } | |
14163 | ||
14164 | static void | |
17a2f251 | 14165 | md_obj_end (void) |
252b5132 RH |
14166 | { |
14167 | /* check for premature end, nesting errors, etc */ | |
14168 | if (cur_proc_ptr) | |
9a41af64 | 14169 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
14170 | } |
14171 | ||
14172 | static long | |
17a2f251 | 14173 | get_number (void) |
252b5132 RH |
14174 | { |
14175 | int negative = 0; | |
14176 | long val = 0; | |
14177 | ||
14178 | if (*input_line_pointer == '-') | |
14179 | { | |
14180 | ++input_line_pointer; | |
14181 | negative = 1; | |
14182 | } | |
3882b010 | 14183 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 14184 | as_bad (_("expected simple number")); |
252b5132 RH |
14185 | if (input_line_pointer[0] == '0') |
14186 | { | |
14187 | if (input_line_pointer[1] == 'x') | |
14188 | { | |
14189 | input_line_pointer += 2; | |
3882b010 | 14190 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
14191 | { |
14192 | val <<= 4; | |
14193 | val |= hex_value (*input_line_pointer++); | |
14194 | } | |
14195 | return negative ? -val : val; | |
14196 | } | |
14197 | else | |
14198 | { | |
14199 | ++input_line_pointer; | |
3882b010 | 14200 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
14201 | { |
14202 | val <<= 3; | |
14203 | val |= *input_line_pointer++ - '0'; | |
14204 | } | |
14205 | return negative ? -val : val; | |
14206 | } | |
14207 | } | |
3882b010 | 14208 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
14209 | { |
14210 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
14211 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 14212 | as_warn (_("invalid number")); |
252b5132 RH |
14213 | return -1; |
14214 | } | |
3882b010 | 14215 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
14216 | { |
14217 | val *= 10; | |
14218 | val += *input_line_pointer++ - '0'; | |
14219 | } | |
14220 | return negative ? -val : val; | |
14221 | } | |
14222 | ||
14223 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
14224 | is an initial number which is the ECOFF file index. In the non-ECOFF |
14225 | case .file implies DWARF-2. */ | |
14226 | ||
14227 | static void | |
17a2f251 | 14228 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 14229 | { |
ecb4347a DJ |
14230 | static int first_file_directive = 0; |
14231 | ||
c5dd6aab DJ |
14232 | if (ECOFF_DEBUGGING) |
14233 | { | |
14234 | get_number (); | |
14235 | s_app_file (0); | |
14236 | } | |
14237 | else | |
ecb4347a DJ |
14238 | { |
14239 | char *filename; | |
14240 | ||
14241 | filename = dwarf2_directive_file (0); | |
14242 | ||
14243 | /* Versions of GCC up to 3.1 start files with a ".file" | |
14244 | directive even for stabs output. Make sure that this | |
14245 | ".file" is handled. Note that you need a version of GCC | |
14246 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
14247 | if (filename != NULL && ! first_file_directive) | |
14248 | { | |
14249 | (void) new_logical_line (filename, -1); | |
c04f5787 | 14250 | s_app_file_string (filename, 0); |
ecb4347a DJ |
14251 | } |
14252 | first_file_directive = 1; | |
14253 | } | |
c5dd6aab DJ |
14254 | } |
14255 | ||
14256 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
14257 | |
14258 | static void | |
17a2f251 | 14259 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 14260 | { |
c5dd6aab DJ |
14261 | if (!ECOFF_DEBUGGING) |
14262 | dwarf2_directive_loc (0); | |
252b5132 RH |
14263 | } |
14264 | ||
252b5132 RH |
14265 | /* The .end directive. */ |
14266 | ||
14267 | static void | |
17a2f251 | 14268 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
14269 | { |
14270 | symbolS *p; | |
252b5132 | 14271 | |
7a621144 DJ |
14272 | /* Following functions need their own .frame and .cprestore directives. */ |
14273 | mips_frame_reg_valid = 0; | |
14274 | mips_cprestore_valid = 0; | |
14275 | ||
252b5132 RH |
14276 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
14277 | { | |
14278 | p = get_symbol (); | |
14279 | demand_empty_rest_of_line (); | |
14280 | } | |
14281 | else | |
14282 | p = NULL; | |
14283 | ||
14949570 | 14284 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
14285 | as_warn (_(".end not in text section")); |
14286 | ||
14287 | if (!cur_proc_ptr) | |
14288 | { | |
14289 | as_warn (_(".end directive without a preceding .ent directive.")); | |
14290 | demand_empty_rest_of_line (); | |
14291 | return; | |
14292 | } | |
14293 | ||
14294 | if (p != NULL) | |
14295 | { | |
14296 | assert (S_GET_NAME (p)); | |
9b2f1d35 | 14297 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
252b5132 | 14298 | as_warn (_(".end symbol does not match .ent symbol.")); |
ecb4347a DJ |
14299 | |
14300 | if (debug_type == DEBUG_STABS) | |
14301 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
14302 | S_GET_NAME (p)); | |
252b5132 RH |
14303 | } |
14304 | else | |
14305 | as_warn (_(".end directive missing or unknown symbol")); | |
14306 | ||
2132e3a3 | 14307 | #ifdef OBJ_ELF |
9b2f1d35 EC |
14308 | /* Create an expression to calculate the size of the function. */ |
14309 | if (p && cur_proc_ptr) | |
14310 | { | |
14311 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
14312 | expressionS *exp = xmalloc (sizeof (expressionS)); | |
14313 | ||
14314 | obj->size = exp; | |
14315 | exp->X_op = O_subtract; | |
14316 | exp->X_add_symbol = symbol_temp_new_now (); | |
14317 | exp->X_op_symbol = p; | |
14318 | exp->X_add_number = 0; | |
14319 | ||
14320 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
14321 | } | |
14322 | ||
ecb4347a | 14323 | /* Generate a .pdr section. */ |
dcd410fe RO |
14324 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING |
14325 | && mips_flag_pdr) | |
ecb4347a DJ |
14326 | { |
14327 | segT saved_seg = now_seg; | |
14328 | subsegT saved_subseg = now_subseg; | |
14329 | valueT dot; | |
14330 | expressionS exp; | |
14331 | char *fragp; | |
252b5132 | 14332 | |
ecb4347a | 14333 | dot = frag_now_fix (); |
252b5132 RH |
14334 | |
14335 | #ifdef md_flush_pending_output | |
ecb4347a | 14336 | md_flush_pending_output (); |
252b5132 RH |
14337 | #endif |
14338 | ||
ecb4347a DJ |
14339 | assert (pdr_seg); |
14340 | subseg_set (pdr_seg, 0); | |
252b5132 | 14341 | |
ecb4347a DJ |
14342 | /* Write the symbol. */ |
14343 | exp.X_op = O_symbol; | |
14344 | exp.X_add_symbol = p; | |
14345 | exp.X_add_number = 0; | |
14346 | emit_expr (&exp, 4); | |
252b5132 | 14347 | |
ecb4347a | 14348 | fragp = frag_more (7 * 4); |
252b5132 | 14349 | |
17a2f251 TS |
14350 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
14351 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
14352 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
14353 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
14354 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
14355 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
14356 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 14357 | |
ecb4347a DJ |
14358 | subseg_set (saved_seg, saved_subseg); |
14359 | } | |
14360 | #endif /* OBJ_ELF */ | |
252b5132 RH |
14361 | |
14362 | cur_proc_ptr = NULL; | |
14363 | } | |
14364 | ||
14365 | /* The .aent and .ent directives. */ | |
14366 | ||
14367 | static void | |
17a2f251 | 14368 | s_mips_ent (int aent) |
252b5132 | 14369 | { |
252b5132 | 14370 | symbolS *symbolP; |
252b5132 RH |
14371 | |
14372 | symbolP = get_symbol (); | |
14373 | if (*input_line_pointer == ',') | |
f9419b05 | 14374 | ++input_line_pointer; |
252b5132 | 14375 | SKIP_WHITESPACE (); |
3882b010 | 14376 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 14377 | || *input_line_pointer == '-') |
874e8986 | 14378 | get_number (); |
252b5132 | 14379 | |
14949570 | 14380 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
14381 | as_warn (_(".ent or .aent not in text section.")); |
14382 | ||
14383 | if (!aent && cur_proc_ptr) | |
9a41af64 | 14384 | as_warn (_("missing .end")); |
252b5132 RH |
14385 | |
14386 | if (!aent) | |
14387 | { | |
7a621144 DJ |
14388 | /* This function needs its own .frame and .cprestore directives. */ |
14389 | mips_frame_reg_valid = 0; | |
14390 | mips_cprestore_valid = 0; | |
14391 | ||
252b5132 RH |
14392 | cur_proc_ptr = &cur_proc; |
14393 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
14394 | ||
9b2f1d35 | 14395 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 14396 | |
49309057 | 14397 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
252b5132 | 14398 | |
f9419b05 | 14399 | ++numprocs; |
ecb4347a DJ |
14400 | |
14401 | if (debug_type == DEBUG_STABS) | |
14402 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
14403 | S_GET_NAME (symbolP)); | |
252b5132 RH |
14404 | } |
14405 | ||
14406 | demand_empty_rest_of_line (); | |
14407 | } | |
14408 | ||
14409 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 14410 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 14411 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 14412 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
14413 | symbol table (in the mdebug section). */ |
14414 | ||
14415 | static void | |
17a2f251 | 14416 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 14417 | { |
ecb4347a DJ |
14418 | #ifdef OBJ_ELF |
14419 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
14420 | { | |
14421 | long val; | |
252b5132 | 14422 | |
ecb4347a DJ |
14423 | if (cur_proc_ptr == (procS *) NULL) |
14424 | { | |
14425 | as_warn (_(".frame outside of .ent")); | |
14426 | demand_empty_rest_of_line (); | |
14427 | return; | |
14428 | } | |
252b5132 | 14429 | |
ecb4347a DJ |
14430 | cur_proc_ptr->frame_reg = tc_get_register (1); |
14431 | ||
14432 | SKIP_WHITESPACE (); | |
14433 | if (*input_line_pointer++ != ',' | |
14434 | || get_absolute_expression_and_terminator (&val) != ',') | |
14435 | { | |
14436 | as_warn (_("Bad .frame directive")); | |
14437 | --input_line_pointer; | |
14438 | demand_empty_rest_of_line (); | |
14439 | return; | |
14440 | } | |
252b5132 | 14441 | |
ecb4347a DJ |
14442 | cur_proc_ptr->frame_offset = val; |
14443 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 14444 | |
252b5132 | 14445 | demand_empty_rest_of_line (); |
252b5132 | 14446 | } |
ecb4347a DJ |
14447 | else |
14448 | #endif /* OBJ_ELF */ | |
14449 | s_ignore (ignore); | |
252b5132 RH |
14450 | } |
14451 | ||
bdaaa2e1 KH |
14452 | /* The .fmask and .mask directives. If the mdebug section is present |
14453 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 14454 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 14455 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
14456 | make reference to the ecoff symbol table (in the mdebug section). */ |
14457 | ||
14458 | static void | |
17a2f251 | 14459 | s_mips_mask (int reg_type) |
252b5132 | 14460 | { |
ecb4347a DJ |
14461 | #ifdef OBJ_ELF |
14462 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
252b5132 | 14463 | { |
ecb4347a | 14464 | long mask, off; |
252b5132 | 14465 | |
ecb4347a DJ |
14466 | if (cur_proc_ptr == (procS *) NULL) |
14467 | { | |
14468 | as_warn (_(".mask/.fmask outside of .ent")); | |
14469 | demand_empty_rest_of_line (); | |
14470 | return; | |
14471 | } | |
252b5132 | 14472 | |
ecb4347a DJ |
14473 | if (get_absolute_expression_and_terminator (&mask) != ',') |
14474 | { | |
14475 | as_warn (_("Bad .mask/.fmask directive")); | |
14476 | --input_line_pointer; | |
14477 | demand_empty_rest_of_line (); | |
14478 | return; | |
14479 | } | |
252b5132 | 14480 | |
ecb4347a DJ |
14481 | off = get_absolute_expression (); |
14482 | ||
14483 | if (reg_type == 'F') | |
14484 | { | |
14485 | cur_proc_ptr->fpreg_mask = mask; | |
14486 | cur_proc_ptr->fpreg_offset = off; | |
14487 | } | |
14488 | else | |
14489 | { | |
14490 | cur_proc_ptr->reg_mask = mask; | |
14491 | cur_proc_ptr->reg_offset = off; | |
14492 | } | |
14493 | ||
14494 | demand_empty_rest_of_line (); | |
252b5132 RH |
14495 | } |
14496 | else | |
ecb4347a DJ |
14497 | #endif /* OBJ_ELF */ |
14498 | s_ignore (reg_type); | |
252b5132 RH |
14499 | } |
14500 | ||
316f5878 RS |
14501 | /* A table describing all the processors gas knows about. Names are |
14502 | matched in the order listed. | |
e7af610e | 14503 | |
316f5878 RS |
14504 | To ease comparison, please keep this table in the same order as |
14505 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
14506 | static const struct mips_cpu_info mips_cpu_info_table[] = |
14507 | { | |
316f5878 | 14508 | /* Entries for generic ISAs */ |
ad3fea08 TS |
14509 | { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 }, |
14510 | { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 }, | |
14511 | { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 }, | |
14512 | { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 }, | |
14513 | { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 }, | |
14514 | { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 }, | |
14515 | { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14516 | { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 }, | |
14517 | { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 }, | |
316f5878 RS |
14518 | |
14519 | /* MIPS I */ | |
ad3fea08 TS |
14520 | { "r3000", 0, ISA_MIPS1, CPU_R3000 }, |
14521 | { "r2000", 0, ISA_MIPS1, CPU_R3000 }, | |
14522 | { "r3900", 0, ISA_MIPS1, CPU_R3900 }, | |
316f5878 RS |
14523 | |
14524 | /* MIPS II */ | |
ad3fea08 | 14525 | { "r6000", 0, ISA_MIPS2, CPU_R6000 }, |
316f5878 RS |
14526 | |
14527 | /* MIPS III */ | |
ad3fea08 TS |
14528 | { "r4000", 0, ISA_MIPS3, CPU_R4000 }, |
14529 | { "r4010", 0, ISA_MIPS2, CPU_R4010 }, | |
14530 | { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, | |
14531 | { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, | |
14532 | { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, | |
14533 | { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, | |
14534 | { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, | |
14535 | { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, | |
14536 | { "r4400", 0, ISA_MIPS3, CPU_R4400 }, | |
14537 | { "r4600", 0, ISA_MIPS3, CPU_R4600 }, | |
14538 | { "orion", 0, ISA_MIPS3, CPU_R4600 }, | |
14539 | { "r4650", 0, ISA_MIPS3, CPU_R4650 }, | |
316f5878 RS |
14540 | |
14541 | /* MIPS IV */ | |
ad3fea08 TS |
14542 | { "r8000", 0, ISA_MIPS4, CPU_R8000 }, |
14543 | { "r10000", 0, ISA_MIPS4, CPU_R10000 }, | |
14544 | { "r12000", 0, ISA_MIPS4, CPU_R12000 }, | |
14545 | { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, | |
14546 | { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, | |
14547 | { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, | |
14548 | { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, | |
14549 | { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, | |
14550 | { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, | |
14551 | { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, | |
14552 | { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, | |
14553 | { "rm7000", 0, ISA_MIPS4, CPU_RM7000 }, | |
14554 | { "rm9000", 0, ISA_MIPS4, CPU_RM9000 }, | |
316f5878 RS |
14555 | |
14556 | /* MIPS 32 */ | |
ad3fea08 TS |
14557 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32 }, |
14558 | { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, | |
14559 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, | |
14560 | { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 }, | |
14561 | ||
14562 | /* MIPS 32 Release 2 */ | |
14563 | { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14564 | { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14565 | { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14566 | { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14567 | { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14568 | { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14569 | { "24k", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14570 | { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14571 | { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14572 | { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14573 | /* 24ke is a 24k with DSP ASE, other ASEs are optional. */ | |
14574 | { "24ke", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14575 | { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14576 | { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
65263ce3 | 14577 | { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
ad3fea08 TS |
14578 | /* 34k is a 24k with MT ASE, other ASEs are optional. */ |
14579 | { "34kc", MIPS_CPU_ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14580 | { "34kf", MIPS_CPU_ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
65263ce3 | 14581 | { "34kx", MIPS_CPU_ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
32b26a03 | 14582 | |
316f5878 | 14583 | /* MIPS 64 */ |
ad3fea08 TS |
14584 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, |
14585 | { "5kf", 0, ISA_MIPS64, CPU_MIPS64 }, | |
14586 | { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
14587 | ||
14588 | /* MIPS 64 Release 2 */ | |
14589 | { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64R2, CPU_MIPS64R2 }, | |
e7af610e | 14590 | |
c7a23324 | 14591 | /* Broadcom SB-1 CPU core */ |
65263ce3 TS |
14592 | { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, |
14593 | ISA_MIPS64, CPU_SB1 }, | |
e7af610e | 14594 | |
316f5878 RS |
14595 | /* End marker */ |
14596 | { NULL, 0, 0, 0 } | |
14597 | }; | |
e7af610e | 14598 | |
84ea6cf2 | 14599 | |
316f5878 RS |
14600 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
14601 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 14602 | |
316f5878 | 14603 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 14604 | |
b34976b6 | 14605 | static bfd_boolean |
17a2f251 | 14606 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
14607 | { |
14608 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
14609 | given++, canonical++; | |
14610 | ||
14611 | return ((*given == 0 && *canonical == 0) | |
14612 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
14613 | } | |
14614 | ||
14615 | ||
14616 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
14617 | CPU name. We've traditionally allowed a lot of variation here. | |
14618 | ||
14619 | Note: this function is shared between GCC and GAS. */ | |
14620 | ||
b34976b6 | 14621 | static bfd_boolean |
17a2f251 | 14622 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
14623 | { |
14624 | /* First see if the name matches exactly, or with a final "000" | |
14625 | turned into "k". */ | |
14626 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 14627 | return TRUE; |
316f5878 RS |
14628 | |
14629 | /* If not, try comparing based on numerical designation alone. | |
14630 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
14631 | if (TOLOWER (*given) == 'r') | |
14632 | given++; | |
14633 | if (!ISDIGIT (*given)) | |
b34976b6 | 14634 | return FALSE; |
316f5878 RS |
14635 | |
14636 | /* Skip over some well-known prefixes in the canonical name, | |
14637 | hoping to find a number there too. */ | |
14638 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
14639 | canonical += 2; | |
14640 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
14641 | canonical += 2; | |
14642 | else if (TOLOWER (canonical[0]) == 'r') | |
14643 | canonical += 1; | |
14644 | ||
14645 | return mips_strict_matching_cpu_name_p (canonical, given); | |
14646 | } | |
14647 | ||
14648 | ||
14649 | /* Parse an option that takes the name of a processor as its argument. | |
14650 | OPTION is the name of the option and CPU_STRING is the argument. | |
14651 | Return the corresponding processor enumeration if the CPU_STRING is | |
14652 | recognized, otherwise report an error and return null. | |
14653 | ||
14654 | A similar function exists in GCC. */ | |
e7af610e NC |
14655 | |
14656 | static const struct mips_cpu_info * | |
17a2f251 | 14657 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 14658 | { |
316f5878 | 14659 | const struct mips_cpu_info *p; |
e7af610e | 14660 | |
316f5878 RS |
14661 | /* 'from-abi' selects the most compatible architecture for the given |
14662 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
14663 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
14664 | version. Look first at the -mgp options, if given, otherwise base | |
14665 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 14666 | |
316f5878 RS |
14667 | Treat NO_ABI like the EABIs. One reason to do this is that the |
14668 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
14669 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
14670 | 'mips64', just as we did in the days before 'from-abi'. */ | |
14671 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
14672 | { | |
14673 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
14674 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
14675 | ||
14676 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
14677 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
14678 | ||
14679 | if (file_mips_gp32 >= 0) | |
14680 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
14681 | ||
14682 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
14683 | ? ISA_MIPS3 | |
14684 | : ISA_MIPS1); | |
14685 | } | |
14686 | ||
14687 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
14688 | if (strcasecmp (cpu_string, "default") == 0) | |
14689 | return 0; | |
14690 | ||
14691 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
14692 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
14693 | return p; | |
14694 | ||
14695 | as_bad ("Bad value (%s) for %s", cpu_string, option); | |
14696 | return 0; | |
e7af610e NC |
14697 | } |
14698 | ||
316f5878 RS |
14699 | /* Return the canonical processor information for ISA (a member of the |
14700 | ISA_MIPS* enumeration). */ | |
14701 | ||
e7af610e | 14702 | static const struct mips_cpu_info * |
17a2f251 | 14703 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
14704 | { |
14705 | int i; | |
14706 | ||
14707 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
ad3fea08 | 14708 | if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA) |
316f5878 | 14709 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
14710 | return (&mips_cpu_info_table[i]); |
14711 | ||
e972090a | 14712 | return NULL; |
e7af610e | 14713 | } |
fef14a42 TS |
14714 | |
14715 | static const struct mips_cpu_info * | |
17a2f251 | 14716 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
14717 | { |
14718 | int i; | |
14719 | ||
14720 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
14721 | if (arch == mips_cpu_info_table[i].cpu) | |
14722 | return (&mips_cpu_info_table[i]); | |
14723 | ||
14724 | return NULL; | |
14725 | } | |
316f5878 RS |
14726 | \f |
14727 | static void | |
17a2f251 | 14728 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
14729 | { |
14730 | if (*first_p) | |
14731 | { | |
14732 | fprintf (stream, "%24s", ""); | |
14733 | *col_p = 24; | |
14734 | } | |
14735 | else | |
14736 | { | |
14737 | fprintf (stream, ", "); | |
14738 | *col_p += 2; | |
14739 | } | |
e7af610e | 14740 | |
316f5878 RS |
14741 | if (*col_p + strlen (string) > 72) |
14742 | { | |
14743 | fprintf (stream, "\n%24s", ""); | |
14744 | *col_p = 24; | |
14745 | } | |
14746 | ||
14747 | fprintf (stream, "%s", string); | |
14748 | *col_p += strlen (string); | |
14749 | ||
14750 | *first_p = 0; | |
14751 | } | |
14752 | ||
14753 | void | |
17a2f251 | 14754 | md_show_usage (FILE *stream) |
e7af610e | 14755 | { |
316f5878 RS |
14756 | int column, first; |
14757 | size_t i; | |
14758 | ||
14759 | fprintf (stream, _("\ | |
14760 | MIPS options:\n\ | |
316f5878 RS |
14761 | -EB generate big endian output\n\ |
14762 | -EL generate little endian output\n\ | |
14763 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
14764 | -G NUM allow referencing objects up to NUM bytes\n\ | |
14765 | implicitly with the gp register [default 8]\n")); | |
14766 | fprintf (stream, _("\ | |
14767 | -mips1 generate MIPS ISA I instructions\n\ | |
14768 | -mips2 generate MIPS ISA II instructions\n\ | |
14769 | -mips3 generate MIPS ISA III instructions\n\ | |
14770 | -mips4 generate MIPS ISA IV instructions\n\ | |
14771 | -mips5 generate MIPS ISA V instructions\n\ | |
14772 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 14773 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 | 14774 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 14775 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
316f5878 RS |
14776 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
14777 | ||
14778 | first = 1; | |
e7af610e NC |
14779 | |
14780 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
14781 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
14782 | show (stream, "from-abi", &column, &first); | |
14783 | fputc ('\n', stream); | |
e7af610e | 14784 | |
316f5878 RS |
14785 | fprintf (stream, _("\ |
14786 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
14787 | -no-mCPU don't generate code specific to CPU.\n\ | |
14788 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
14789 | ||
14790 | first = 1; | |
14791 | ||
14792 | show (stream, "3900", &column, &first); | |
14793 | show (stream, "4010", &column, &first); | |
14794 | show (stream, "4100", &column, &first); | |
14795 | show (stream, "4650", &column, &first); | |
14796 | fputc ('\n', stream); | |
14797 | ||
14798 | fprintf (stream, _("\ | |
14799 | -mips16 generate mips16 instructions\n\ | |
14800 | -no-mips16 do not generate mips16 instructions\n")); | |
14801 | fprintf (stream, _("\ | |
e16bfa71 TS |
14802 | -msmartmips generate smartmips instructions\n\ |
14803 | -mno-smartmips do not generate smartmips instructions\n")); | |
14804 | fprintf (stream, _("\ | |
74cd071d CF |
14805 | -mdsp generate DSP instructions\n\ |
14806 | -mno-dsp do not generate DSP instructions\n")); | |
14807 | fprintf (stream, _("\ | |
ef2e4d86 CF |
14808 | -mmt generate MT instructions\n\ |
14809 | -mno-mt do not generate MT instructions\n")); | |
14810 | fprintf (stream, _("\ | |
d766e8ec | 14811 | -mfix-vr4120 work around certain VR4120 errata\n\ |
7d8e00cf | 14812 | -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ |
316f5878 RS |
14813 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
14814 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
aed1a261 RS |
14815 | -mno-shared optimize output for executables\n\ |
14816 | -msym32 assume all symbols have 32-bit values\n\ | |
316f5878 RS |
14817 | -O0 remove unneeded NOPs, do not swap branches\n\ |
14818 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
14819 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ |
14820 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ | |
14821 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
14822 | #ifdef OBJ_ELF | |
14823 | fprintf (stream, _("\ | |
14824 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
14825 | -non_shared do not generate position independent code\n\ | |
14826 | -xgot assume a 32 bit GOT\n\ | |
dcd410fe | 14827 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
bbe506e8 TS |
14828 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
14829 | non-shared code\n\ | |
316f5878 RS |
14830 | -mabi=ABI create ABI conformant object file for:\n")); |
14831 | ||
14832 | first = 1; | |
14833 | ||
14834 | show (stream, "32", &column, &first); | |
14835 | show (stream, "o64", &column, &first); | |
14836 | show (stream, "n32", &column, &first); | |
14837 | show (stream, "64", &column, &first); | |
14838 | show (stream, "eabi", &column, &first); | |
14839 | ||
14840 | fputc ('\n', stream); | |
14841 | ||
14842 | fprintf (stream, _("\ | |
14843 | -32 create o32 ABI object file (default)\n\ | |
14844 | -n32 create n32 ABI object file\n\ | |
14845 | -64 create 64 ABI object file\n")); | |
14846 | #endif | |
e7af610e | 14847 | } |
14e777e0 KB |
14848 | |
14849 | enum dwarf2_format | |
17a2f251 | 14850 | mips_dwarf2_format (void) |
14e777e0 KB |
14851 | { |
14852 | if (mips_abi == N64_ABI) | |
1de5b6a1 AO |
14853 | { |
14854 | #ifdef TE_IRIX | |
14855 | return dwarf2_format_64bit_irix; | |
14856 | #else | |
14857 | return dwarf2_format_64bit; | |
14858 | #endif | |
14859 | } | |
14e777e0 KB |
14860 | else |
14861 | return dwarf2_format_32bit; | |
14862 | } | |
73369e65 EC |
14863 | |
14864 | int | |
14865 | mips_dwarf2_addr_size (void) | |
14866 | { | |
14867 | if (mips_abi == N64_ABI) | |
14868 | return 8; | |
73369e65 EC |
14869 | else |
14870 | return 4; | |
14871 | } | |
5862107c EC |
14872 | |
14873 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
14874 | void | |
14875 | mips_cfi_frame_initial_instructions (void) | |
14876 | { | |
14877 | cfi_add_CFA_def_cfa_register (SP); | |
14878 | } | |
14879 | ||
707bfff6 TS |
14880 | int |
14881 | tc_mips_regname_to_dw2regnum (char *regname) | |
14882 | { | |
14883 | unsigned int regnum = -1; | |
14884 | unsigned int reg; | |
14885 | ||
14886 | if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®)) | |
14887 | regnum = reg; | |
14888 | ||
14889 | return regnum; | |
14890 | } |