Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
81912461 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
ebd1c875 | 3 | 2003, 2004, 2005, 2006 Free Software Foundation, Inc. |
252b5132 RH |
4 | Contributed by the OSF and Ralph Campbell. |
5 | Written by Keith Knowles and Ralph Campbell, working independently. | |
6 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
7 | Support. | |
8 | ||
9 | This file is part of GAS. | |
10 | ||
11 | GAS is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2, or (at your option) | |
14 | any later version. | |
15 | ||
16 | GAS is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
23 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
24 | 02110-1301, USA. */ | |
252b5132 RH |
25 | |
26 | #include "as.h" | |
27 | #include "config.h" | |
28 | #include "subsegs.h" | |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | |
252b5132 RH |
31 | #include "opcode/mips.h" |
32 | #include "itbl-ops.h" | |
c5dd6aab | 33 | #include "dwarf2dbg.h" |
5862107c | 34 | #include "dw2gencfi.h" |
252b5132 RH |
35 | |
36 | #ifdef DEBUG | |
37 | #define DBG(x) printf x | |
38 | #else | |
39 | #define DBG(x) | |
40 | #endif | |
41 | ||
42 | #ifdef OBJ_MAYBE_ELF | |
43 | /* Clean up namespace so we can include obj-elf.h too. */ | |
17a2f251 TS |
44 | static int mips_output_flavor (void); |
45 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
46 | #undef OBJ_PROCESS_STAB |
47 | #undef OUTPUT_FLAVOR | |
48 | #undef S_GET_ALIGN | |
49 | #undef S_GET_SIZE | |
50 | #undef S_SET_ALIGN | |
51 | #undef S_SET_SIZE | |
252b5132 RH |
52 | #undef obj_frob_file |
53 | #undef obj_frob_file_after_relocs | |
54 | #undef obj_frob_symbol | |
55 | #undef obj_pop_insert | |
56 | #undef obj_sec_sym_ok_for_reloc | |
57 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
58 | ||
59 | #include "obj-elf.h" | |
60 | /* Fix any of them that we actually care about. */ | |
61 | #undef OUTPUT_FLAVOR | |
62 | #define OUTPUT_FLAVOR mips_output_flavor() | |
63 | #endif | |
64 | ||
65 | #if defined (OBJ_ELF) | |
66 | #include "elf/mips.h" | |
67 | #endif | |
68 | ||
69 | #ifndef ECOFF_DEBUGGING | |
70 | #define NO_ECOFF_DEBUGGING | |
71 | #define ECOFF_DEBUGGING 0 | |
72 | #endif | |
73 | ||
ecb4347a DJ |
74 | int mips_flag_mdebug = -1; |
75 | ||
dcd410fe RO |
76 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
77 | linker doesn't know about and discards them, but relocations against them | |
78 | remain, leading to rld crashes. */ | |
79 | #ifdef TE_IRIX | |
80 | int mips_flag_pdr = FALSE; | |
81 | #else | |
82 | int mips_flag_pdr = TRUE; | |
83 | #endif | |
84 | ||
252b5132 RH |
85 | #include "ecoff.h" |
86 | ||
87 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
88 | static char *mips_regmask_frag; | |
89 | #endif | |
90 | ||
85b51719 | 91 | #define ZERO 0 |
252b5132 RH |
92 | #define AT 1 |
93 | #define TREG 24 | |
94 | #define PIC_CALL_REG 25 | |
95 | #define KT0 26 | |
96 | #define KT1 27 | |
97 | #define GP 28 | |
98 | #define SP 29 | |
99 | #define FP 30 | |
100 | #define RA 31 | |
101 | ||
102 | #define ILLEGAL_REG (32) | |
103 | ||
104 | /* Allow override of standard little-endian ECOFF format. */ | |
105 | ||
106 | #ifndef ECOFF_LITTLE_FORMAT | |
107 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
108 | #endif | |
109 | ||
110 | extern int target_big_endian; | |
111 | ||
252b5132 | 112 | /* The name of the readonly data section. */ |
4d0d148d | 113 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ |
252b5132 | 114 | ? ".rdata" \ |
056350c6 NC |
115 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
116 | ? ".rdata" \ | |
252b5132 RH |
117 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
118 | ? ".rodata" \ | |
119 | : (abort (), "")) | |
120 | ||
47e39b9d RS |
121 | /* Information about an instruction, including its format, operands |
122 | and fixups. */ | |
123 | struct mips_cl_insn | |
124 | { | |
125 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ | |
126 | const struct mips_opcode *insn_mo; | |
127 | ||
128 | /* True if this is a mips16 instruction and if we want the extended | |
129 | form of INSN_MO. */ | |
130 | bfd_boolean use_extend; | |
131 | ||
132 | /* The 16-bit extension instruction to use when USE_EXTEND is true. */ | |
133 | unsigned short extend; | |
134 | ||
135 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is | |
136 | a copy of INSN_MO->match with the operands filled in. */ | |
137 | unsigned long insn_opcode; | |
138 | ||
139 | /* The frag that contains the instruction. */ | |
140 | struct frag *frag; | |
141 | ||
142 | /* The offset into FRAG of the first instruction byte. */ | |
143 | long where; | |
144 | ||
145 | /* The relocs associated with the instruction, if any. */ | |
146 | fixS *fixp[3]; | |
147 | ||
a38419a5 RS |
148 | /* True if this entry cannot be moved from its current position. */ |
149 | unsigned int fixed_p : 1; | |
47e39b9d | 150 | |
708587a4 | 151 | /* True if this instruction occurred in a .set noreorder block. */ |
47e39b9d RS |
152 | unsigned int noreorder_p : 1; |
153 | ||
2fa15973 RS |
154 | /* True for mips16 instructions that jump to an absolute address. */ |
155 | unsigned int mips16_absolute_jump_p : 1; | |
47e39b9d RS |
156 | }; |
157 | ||
a325df1d TS |
158 | /* The ABI to use. */ |
159 | enum mips_abi_level | |
160 | { | |
161 | NO_ABI = 0, | |
162 | O32_ABI, | |
163 | O64_ABI, | |
164 | N32_ABI, | |
165 | N64_ABI, | |
166 | EABI_ABI | |
167 | }; | |
168 | ||
169 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 170 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 171 | |
143d77c5 EC |
172 | /* Whether or not we have code that can call pic code. */ |
173 | int mips_abicalls = FALSE; | |
174 | ||
aa6975fb ILT |
175 | /* Whether or not we have code which can be put into a shared |
176 | library. */ | |
177 | static bfd_boolean mips_in_shared = TRUE; | |
178 | ||
252b5132 RH |
179 | /* This is the set of options which may be modified by the .set |
180 | pseudo-op. We use a struct so that .set push and .set pop are more | |
181 | reliable. */ | |
182 | ||
e972090a NC |
183 | struct mips_set_options |
184 | { | |
252b5132 RH |
185 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
186 | if it has not been initialized. Changed by `.set mipsN', and the | |
187 | -mipsN command line option, and the default CPU. */ | |
188 | int isa; | |
1f25f5d3 CD |
189 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
190 | if they have not been initialized. Changed by `.set <asename>', by | |
191 | command line options, and based on the default architecture. */ | |
192 | int ase_mips3d; | |
deec1734 | 193 | int ase_mdmx; |
e16bfa71 | 194 | int ase_smartmips; |
74cd071d | 195 | int ase_dsp; |
ef2e4d86 | 196 | int ase_mt; |
252b5132 RH |
197 | /* Whether we are assembling for the mips16 processor. 0 if we are |
198 | not, 1 if we are, and -1 if the value has not been initialized. | |
199 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
200 | -nomips16 command line options, and the default CPU. */ | |
201 | int mips16; | |
202 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
203 | reorder' and `.set noreorder'. */ | |
204 | int noreorder; | |
205 | /* Non-zero if we should not permit the $at ($1) register to be used | |
206 | in instructions. Changed by `.set at' and `.set noat'. */ | |
207 | int noat; | |
208 | /* Non-zero if we should warn when a macro instruction expands into | |
209 | more than one machine instruction. Changed by `.set nomacro' and | |
210 | `.set macro'. */ | |
211 | int warn_about_macros; | |
212 | /* Non-zero if we should not move instructions. Changed by `.set | |
213 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
214 | int nomove; | |
215 | /* Non-zero if we should not optimize branches by moving the target | |
216 | of the branch into the delay slot. Actually, we don't perform | |
217 | this optimization anyhow. Changed by `.set bopt' and `.set | |
218 | nobopt'. */ | |
219 | int nobopt; | |
220 | /* Non-zero if we should not autoextend mips16 instructions. | |
221 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
222 | int noautoextend; | |
a325df1d TS |
223 | /* Restrict general purpose registers and floating point registers |
224 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
225 | is passed but can changed if the assembler code uses .set mipsN. */ | |
226 | int gp32; | |
227 | int fp32; | |
fef14a42 TS |
228 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
229 | command line option, and the default CPU. */ | |
230 | int arch; | |
aed1a261 RS |
231 | /* True if ".set sym32" is in effect. */ |
232 | bfd_boolean sym32; | |
252b5132 RH |
233 | }; |
234 | ||
a325df1d | 235 | /* True if -mgp32 was passed. */ |
a8e8e863 | 236 | static int file_mips_gp32 = -1; |
a325df1d TS |
237 | |
238 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 239 | static int file_mips_fp32 = -1; |
a325df1d | 240 | |
252b5132 | 241 | /* This is the struct we use to hold the current set of options. Note |
a4672219 | 242 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to |
e7af610e | 243 | -1 to indicate that they have not been initialized. */ |
252b5132 | 244 | |
e972090a NC |
245 | static struct mips_set_options mips_opts = |
246 | { | |
e16bfa71 | 247 | ISA_UNKNOWN, -1, -1, 0, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN, FALSE |
e7af610e | 248 | }; |
252b5132 RH |
249 | |
250 | /* These variables are filled in with the masks of registers used. | |
251 | The object format code reads them and puts them in the appropriate | |
252 | place. */ | |
253 | unsigned long mips_gprmask; | |
254 | unsigned long mips_cprmask[4]; | |
255 | ||
256 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 257 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 258 | |
a4672219 TS |
259 | /* True if -mips16 was passed or implied by arguments passed on the |
260 | command line (e.g., by -march). */ | |
261 | static int file_ase_mips16; | |
262 | ||
3994f87e TS |
263 | #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \ |
264 | || mips_opts.isa == ISA_MIPS32R2 \ | |
265 | || mips_opts.isa == ISA_MIPS64 \ | |
266 | || mips_opts.isa == ISA_MIPS64R2) | |
267 | ||
1f25f5d3 CD |
268 | /* True if -mips3d was passed or implied by arguments passed on the |
269 | command line (e.g., by -march). */ | |
270 | static int file_ase_mips3d; | |
271 | ||
deec1734 CD |
272 | /* True if -mdmx was passed or implied by arguments passed on the |
273 | command line (e.g., by -march). */ | |
274 | static int file_ase_mdmx; | |
275 | ||
e16bfa71 TS |
276 | /* True if -msmartmips was passed or implied by arguments passed on the |
277 | command line (e.g., by -march). */ | |
278 | static int file_ase_smartmips; | |
279 | ||
ad3fea08 TS |
280 | #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \ |
281 | || mips_opts.isa == ISA_MIPS32R2) | |
e16bfa71 | 282 | |
74cd071d CF |
283 | /* True if -mdsp was passed or implied by arguments passed on the |
284 | command line (e.g., by -march). */ | |
285 | static int file_ase_dsp; | |
286 | ||
ad3fea08 TS |
287 | #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
288 | || mips_opts.isa == ISA_MIPS64R2) | |
289 | ||
65263ce3 TS |
290 | #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2) |
291 | ||
ef2e4d86 CF |
292 | /* True if -mmt was passed or implied by arguments passed on the |
293 | command line (e.g., by -march). */ | |
294 | static int file_ase_mt; | |
295 | ||
ad3fea08 TS |
296 | #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \ |
297 | || mips_opts.isa == ISA_MIPS64R2) | |
298 | ||
ec68c924 | 299 | /* The argument of the -march= flag. The architecture we are assembling. */ |
fef14a42 | 300 | static int file_mips_arch = CPU_UNKNOWN; |
316f5878 | 301 | static const char *mips_arch_string; |
ec68c924 EC |
302 | |
303 | /* The argument of the -mtune= flag. The architecture for which we | |
304 | are optimizing. */ | |
305 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 306 | static const char *mips_tune_string; |
ec68c924 | 307 | |
316f5878 | 308 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
309 | static int mips_32bitmode = 0; |
310 | ||
316f5878 RS |
311 | /* True if the given ABI requires 32-bit registers. */ |
312 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
313 | ||
314 | /* Likewise 64-bit registers. */ | |
707bfff6 TS |
315 | #define ABI_NEEDS_64BIT_REGS(ABI) \ |
316 | ((ABI) == N32_ABI \ | |
317 | || (ABI) == N64_ABI \ | |
316f5878 RS |
318 | || (ABI) == O64_ABI) |
319 | ||
ad3fea08 | 320 | /* Return true if ISA supports 64 bit wide gp registers. */ |
707bfff6 TS |
321 | #define ISA_HAS_64BIT_REGS(ISA) \ |
322 | ((ISA) == ISA_MIPS3 \ | |
323 | || (ISA) == ISA_MIPS4 \ | |
324 | || (ISA) == ISA_MIPS5 \ | |
325 | || (ISA) == ISA_MIPS64 \ | |
326 | || (ISA) == ISA_MIPS64R2) | |
9ce8a5dd | 327 | |
ad3fea08 TS |
328 | /* Return true if ISA supports 64 bit wide float registers. */ |
329 | #define ISA_HAS_64BIT_FPRS(ISA) \ | |
330 | ((ISA) == ISA_MIPS3 \ | |
331 | || (ISA) == ISA_MIPS4 \ | |
332 | || (ISA) == ISA_MIPS5 \ | |
333 | || (ISA) == ISA_MIPS32R2 \ | |
334 | || (ISA) == ISA_MIPS64 \ | |
335 | || (ISA) == ISA_MIPS64R2) | |
336 | ||
af7ee8bf CD |
337 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
338 | instructions. */ | |
707bfff6 TS |
339 | #define ISA_HAS_DROR(ISA) \ |
340 | ((ISA) == ISA_MIPS64R2) | |
af7ee8bf CD |
341 | |
342 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
343 | instructions. */ | |
707bfff6 TS |
344 | #define ISA_HAS_ROR(ISA) \ |
345 | ((ISA) == ISA_MIPS32R2 \ | |
346 | || (ISA) == ISA_MIPS64R2 \ | |
347 | || mips_opts.ase_smartmips) | |
348 | ||
7455baf8 TS |
349 | /* Return true if ISA supports single-precision floats in odd registers. */ |
350 | #define ISA_HAS_ODD_SINGLE_FPR(ISA) \ | |
351 | ((ISA) == ISA_MIPS32 \ | |
352 | || (ISA) == ISA_MIPS32R2 \ | |
353 | || (ISA) == ISA_MIPS64 \ | |
354 | || (ISA) == ISA_MIPS64R2) | |
af7ee8bf | 355 | |
ad3fea08 TS |
356 | /* Return true if ISA supports move to/from high part of a 64-bit |
357 | floating-point register. */ | |
358 | #define ISA_HAS_MXHC1(ISA) \ | |
359 | ((ISA) == ISA_MIPS32R2 \ | |
360 | || (ISA) == ISA_MIPS64R2) | |
361 | ||
e013f690 | 362 | #define HAVE_32BIT_GPRS \ |
ad3fea08 | 363 | (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 364 | |
e013f690 | 365 | #define HAVE_32BIT_FPRS \ |
ad3fea08 | 366 | (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa)) |
ca4e0257 | 367 | |
ad3fea08 TS |
368 | #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS) |
369 | #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS) | |
ca4e0257 | 370 | |
316f5878 | 371 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 372 | |
316f5878 | 373 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 374 | |
3b91255e RS |
375 | /* True if relocations are stored in-place. */ |
376 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
377 | ||
aed1a261 RS |
378 | /* The ABI-derived address size. */ |
379 | #define HAVE_64BIT_ADDRESSES \ | |
380 | (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) | |
381 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) | |
e013f690 | 382 | |
aed1a261 RS |
383 | /* The size of symbolic constants (i.e., expressions of the form |
384 | "SYMBOL" or "SYMBOL + OFFSET"). */ | |
385 | #define HAVE_32BIT_SYMBOLS \ | |
386 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) | |
387 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) | |
ca4e0257 | 388 | |
b7c7d6c1 TS |
389 | /* Addresses are loaded in different ways, depending on the address size |
390 | in use. The n32 ABI Documentation also mandates the use of additions | |
391 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 392 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 393 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
394 | |
395 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 396 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
397 | |
398 | #define ADDRESS_LOAD_INSN \ | |
399 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
400 | ||
401 | #define ADDRESS_STORE_INSN \ | |
402 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
403 | ||
a4672219 | 404 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
405 | #define CPU_HAS_MIPS16(cpu) \ |
406 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
407 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 408 | |
60b63b72 RS |
409 | /* True if CPU has a dror instruction. */ |
410 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
411 | ||
412 | /* True if CPU has a ror instruction. */ | |
413 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
414 | ||
c8978940 CD |
415 | /* True if mflo and mfhi can be immediately followed by instructions |
416 | which write to the HI and LO registers. | |
417 | ||
418 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
419 | (at least) two instructions between the reads of HI/LO and | |
420 | instructions which write them, and later ISAs do not. Contradicting | |
421 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
422 | the UM for the NEC Vr5000) document needing the instructions between | |
423 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
424 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
425 | earlier-ISA CPUs for which CPU documentation declares that the | |
426 | instructions are really interlocked. */ | |
427 | #define hilo_interlocks \ | |
428 | (mips_opts.isa == ISA_MIPS32 \ | |
429 | || mips_opts.isa == ISA_MIPS32R2 \ | |
430 | || mips_opts.isa == ISA_MIPS64 \ | |
431 | || mips_opts.isa == ISA_MIPS64R2 \ | |
432 | || mips_opts.arch == CPU_R4010 \ | |
433 | || mips_opts.arch == CPU_R10000 \ | |
434 | || mips_opts.arch == CPU_R12000 \ | |
435 | || mips_opts.arch == CPU_RM7000 \ | |
c8978940 CD |
436 | || mips_opts.arch == CPU_VR5500 \ |
437 | ) | |
252b5132 RH |
438 | |
439 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
440 | from the GPRs after they are loaded from memory, and thus does not |
441 | require nops to be inserted. This applies to instructions marked | |
442 | INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA | |
443 | level I. */ | |
252b5132 | 444 | #define gpr_interlocks \ |
e7af610e | 445 | (mips_opts.isa != ISA_MIPS1 \ |
fef14a42 | 446 | || mips_opts.arch == CPU_R3900) |
252b5132 | 447 | |
81912461 ILT |
448 | /* Whether the processor uses hardware interlocks to avoid delays |
449 | required by coprocessor instructions, and thus does not require | |
450 | nops to be inserted. This applies to instructions marked | |
451 | INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays | |
452 | between instructions marked INSN_WRITE_COND_CODE and ones marked | |
453 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA | |
454 | levels I, II, and III. */ | |
bdaaa2e1 | 455 | /* Itbl support may require additional care here. */ |
81912461 ILT |
456 | #define cop_interlocks \ |
457 | ((mips_opts.isa != ISA_MIPS1 \ | |
458 | && mips_opts.isa != ISA_MIPS2 \ | |
459 | && mips_opts.isa != ISA_MIPS3) \ | |
460 | || mips_opts.arch == CPU_R4300 \ | |
81912461 ILT |
461 | ) |
462 | ||
463 | /* Whether the processor uses hardware interlocks to protect reads | |
464 | from coprocessor registers after they are loaded from memory, and | |
465 | thus does not require nops to be inserted. This applies to | |
466 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
467 | requires at MIPS ISA level I. */ | |
468 | #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1) | |
252b5132 | 469 | |
6b76fefe CM |
470 | /* Is this a mfhi or mflo instruction? */ |
471 | #define MF_HILO_INSN(PINFO) \ | |
472 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) | |
473 | ||
252b5132 RH |
474 | /* MIPS PIC level. */ |
475 | ||
a161fe53 | 476 | enum mips_pic_level mips_pic; |
252b5132 | 477 | |
c9914766 | 478 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 479 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 480 | static int mips_big_got = 0; |
252b5132 RH |
481 | |
482 | /* 1 if trap instructions should used for overflow rather than break | |
483 | instructions. */ | |
c9914766 | 484 | static int mips_trap = 0; |
252b5132 | 485 | |
119d663a | 486 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 487 | by assembling two single width halves into two single width floating |
119d663a NC |
488 | point registers which just happen to alias the double width destination |
489 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 490 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
491 | automatically at assemble time. */ |
492 | static int mips_disable_float_construction; | |
493 | ||
252b5132 RH |
494 | /* Non-zero if any .set noreorder directives were used. */ |
495 | ||
496 | static int mips_any_noreorder; | |
497 | ||
6b76fefe CM |
498 | /* Non-zero if nops should be inserted when the register referenced in |
499 | an mfhi/mflo instruction is read in the next two instructions. */ | |
500 | static int mips_7000_hilo_fix; | |
501 | ||
252b5132 | 502 | /* The size of the small data section. */ |
156c2f8b | 503 | static unsigned int g_switch_value = 8; |
252b5132 RH |
504 | /* Whether the -G option was used. */ |
505 | static int g_switch_seen = 0; | |
506 | ||
507 | #define N_RMASK 0xc4 | |
508 | #define N_VFP 0xd4 | |
509 | ||
510 | /* If we can determine in advance that GP optimization won't be | |
511 | possible, we can skip the relaxation stuff that tries to produce | |
512 | GP-relative references. This makes delay slot optimization work | |
513 | better. | |
514 | ||
515 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
516 | gcc output. It needs to guess right for gcc, otherwise gcc |
517 | will put what it thinks is a GP-relative instruction in a branch | |
518 | delay slot. | |
252b5132 RH |
519 | |
520 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
521 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 522 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
523 | |
524 | /* handle of the OPCODE hash table */ | |
525 | static struct hash_control *op_hash = NULL; | |
526 | ||
527 | /* The opcode hash table we use for the mips16. */ | |
528 | static struct hash_control *mips16_op_hash = NULL; | |
529 | ||
530 | /* This array holds the chars that always start a comment. If the | |
531 | pre-processor is disabled, these aren't very useful */ | |
532 | const char comment_chars[] = "#"; | |
533 | ||
534 | /* This array holds the chars that only start a comment at the beginning of | |
535 | a line. If the line seems to have the form '# 123 filename' | |
536 | .line and .file directives will appear in the pre-processed output */ | |
537 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
538 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 539 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
540 | /* Also note that C style comments are always supported. */ |
541 | const char line_comment_chars[] = "#"; | |
542 | ||
bdaaa2e1 | 543 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 544 | const char line_separator_chars[] = ";"; |
252b5132 RH |
545 | |
546 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
547 | const char EXP_CHARS[] = "eE"; | |
548 | ||
549 | /* Chars that mean this number is a floating point constant */ | |
550 | /* As in 0f12.456 */ | |
551 | /* or 0d1.2345e12 */ | |
552 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
553 | ||
554 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
555 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
556 | but nothing is ideal around here. | |
557 | */ | |
558 | ||
559 | static char *insn_error; | |
560 | ||
561 | static int auto_align = 1; | |
562 | ||
563 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
564 | offset in the stack frame from which to restore the $gp register. | |
565 | This is set by the .cprestore pseudo-op, and saved in this | |
566 | variable. */ | |
567 | static offsetT mips_cprestore_offset = -1; | |
568 | ||
67c1ffbe | 569 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 570 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 571 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
572 | static offsetT mips_cpreturn_offset = -1; |
573 | static int mips_cpreturn_register = -1; | |
574 | static int mips_gp_register = GP; | |
def2e0dd | 575 | static int mips_gprel_offset = 0; |
6478892d | 576 | |
7a621144 DJ |
577 | /* Whether mips_cprestore_offset has been set in the current function |
578 | (or whether it has already been warned about, if not). */ | |
579 | static int mips_cprestore_valid = 0; | |
580 | ||
252b5132 RH |
581 | /* This is the register which holds the stack frame, as set by the |
582 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
583 | static int mips_frame_reg = SP; | |
584 | ||
7a621144 DJ |
585 | /* Whether mips_frame_reg has been set in the current function |
586 | (or whether it has already been warned about, if not). */ | |
587 | static int mips_frame_reg_valid = 0; | |
588 | ||
252b5132 RH |
589 | /* To output NOP instructions correctly, we need to keep information |
590 | about the previous two instructions. */ | |
591 | ||
592 | /* Whether we are optimizing. The default value of 2 means to remove | |
593 | unneeded NOPs and swap branch instructions when possible. A value | |
594 | of 1 means to not swap branches. A value of 0 means to always | |
595 | insert NOPs. */ | |
596 | static int mips_optimize = 2; | |
597 | ||
598 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
599 | equivalent to seeing no -g option at all. */ | |
600 | static int mips_debug = 0; | |
601 | ||
7d8e00cf RS |
602 | /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ |
603 | #define MAX_VR4130_NOPS 4 | |
604 | ||
605 | /* The maximum number of NOPs needed to fill delay slots. */ | |
606 | #define MAX_DELAY_NOPS 2 | |
607 | ||
608 | /* The maximum number of NOPs needed for any purpose. */ | |
609 | #define MAX_NOPS 4 | |
71400594 RS |
610 | |
611 | /* A list of previous instructions, with index 0 being the most recent. | |
612 | We need to look back MAX_NOPS instructions when filling delay slots | |
613 | or working around processor errata. We need to look back one | |
614 | instruction further if we're thinking about using history[0] to | |
615 | fill a branch delay slot. */ | |
616 | static struct mips_cl_insn history[1 + MAX_NOPS]; | |
252b5132 | 617 | |
1e915849 RS |
618 | /* Nop instructions used by emit_nop. */ |
619 | static struct mips_cl_insn nop_insn, mips16_nop_insn; | |
620 | ||
621 | /* The appropriate nop for the current mode. */ | |
622 | #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn) | |
252b5132 | 623 | |
252b5132 RH |
624 | /* If this is set, it points to a frag holding nop instructions which |
625 | were inserted before the start of a noreorder section. If those | |
626 | nops turn out to be unnecessary, the size of the frag can be | |
627 | decreased. */ | |
628 | static fragS *prev_nop_frag; | |
629 | ||
630 | /* The number of nop instructions we created in prev_nop_frag. */ | |
631 | static int prev_nop_frag_holds; | |
632 | ||
633 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 634 | prev_nop_frag. */ |
252b5132 RH |
635 | static int prev_nop_frag_required; |
636 | ||
637 | /* The number of instructions we've seen since prev_nop_frag. */ | |
638 | static int prev_nop_frag_since; | |
639 | ||
640 | /* For ECOFF and ELF, relocations against symbols are done in two | |
641 | parts, with a HI relocation and a LO relocation. Each relocation | |
642 | has only 16 bits of space to store an addend. This means that in | |
643 | order for the linker to handle carries correctly, it must be able | |
644 | to locate both the HI and the LO relocation. This means that the | |
645 | relocations must appear in order in the relocation table. | |
646 | ||
647 | In order to implement this, we keep track of each unmatched HI | |
648 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 649 | corresponding LO relocation. */ |
252b5132 | 650 | |
e972090a NC |
651 | struct mips_hi_fixup |
652 | { | |
252b5132 RH |
653 | /* Next HI fixup. */ |
654 | struct mips_hi_fixup *next; | |
655 | /* This fixup. */ | |
656 | fixS *fixp; | |
657 | /* The section this fixup is in. */ | |
658 | segT seg; | |
659 | }; | |
660 | ||
661 | /* The list of unmatched HI relocs. */ | |
662 | ||
663 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
664 | ||
64bdfcaf RS |
665 | /* The frag containing the last explicit relocation operator. |
666 | Null if explicit relocations have not been used. */ | |
667 | ||
668 | static fragS *prev_reloc_op_frag; | |
669 | ||
252b5132 RH |
670 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
671 | ||
672 | #define X ILLEGAL_REG | |
e972090a NC |
673 | static const int mips32_to_16_reg_map[] = |
674 | { | |
252b5132 RH |
675 | X, X, 2, 3, 4, 5, 6, 7, |
676 | X, X, X, X, X, X, X, X, | |
677 | 0, 1, X, X, X, X, X, X, | |
678 | X, X, X, X, X, X, X, X | |
679 | }; | |
680 | #undef X | |
681 | ||
682 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
683 | ||
e972090a NC |
684 | static const unsigned int mips16_to_32_reg_map[] = |
685 | { | |
252b5132 RH |
686 | 16, 17, 2, 3, 4, 5, 6, 7 |
687 | }; | |
60b63b72 | 688 | |
71400594 RS |
689 | /* Classifies the kind of instructions we're interested in when |
690 | implementing -mfix-vr4120. */ | |
691 | enum fix_vr4120_class { | |
692 | FIX_VR4120_MACC, | |
693 | FIX_VR4120_DMACC, | |
694 | FIX_VR4120_MULT, | |
695 | FIX_VR4120_DMULT, | |
696 | FIX_VR4120_DIV, | |
697 | FIX_VR4120_MTHILO, | |
698 | NUM_FIX_VR4120_CLASSES | |
699 | }; | |
700 | ||
701 | /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if | |
702 | there must be at least one other instruction between an instruction | |
703 | of type X and an instruction of type Y. */ | |
704 | static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; | |
705 | ||
706 | /* True if -mfix-vr4120 is in force. */ | |
d766e8ec | 707 | static int mips_fix_vr4120; |
4a6a3df4 | 708 | |
7d8e00cf RS |
709 | /* ...likewise -mfix-vr4130. */ |
710 | static int mips_fix_vr4130; | |
711 | ||
4a6a3df4 AO |
712 | /* We don't relax branches by default, since this causes us to expand |
713 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
714 | fail to compute the offset before expanding the macro to the most | |
715 | efficient expansion. */ | |
716 | ||
717 | static int mips_relax_branch; | |
252b5132 | 718 | \f |
4d7206a2 RS |
719 | /* The expansion of many macros depends on the type of symbol that |
720 | they refer to. For example, when generating position-dependent code, | |
721 | a macro that refers to a symbol may have two different expansions, | |
722 | one which uses GP-relative addresses and one which uses absolute | |
723 | addresses. When generating SVR4-style PIC, a macro may have | |
724 | different expansions for local and global symbols. | |
725 | ||
726 | We handle these situations by generating both sequences and putting | |
727 | them in variant frags. In position-dependent code, the first sequence | |
728 | will be the GP-relative one and the second sequence will be the | |
729 | absolute one. In SVR4 PIC, the first sequence will be for global | |
730 | symbols and the second will be for local symbols. | |
731 | ||
584892a6 RS |
732 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
733 | SECOND are the lengths of the two sequences in bytes. These fields | |
734 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
735 | the subtype has the following flags: | |
4d7206a2 | 736 | |
584892a6 RS |
737 | RELAX_USE_SECOND |
738 | Set if it has been decided that we should use the second | |
739 | sequence instead of the first. | |
740 | ||
741 | RELAX_SECOND_LONGER | |
742 | Set in the first variant frag if the macro's second implementation | |
743 | is longer than its first. This refers to the macro as a whole, | |
744 | not an individual relaxation. | |
745 | ||
746 | RELAX_NOMACRO | |
747 | Set in the first variant frag if the macro appeared in a .set nomacro | |
748 | block and if one alternative requires a warning but the other does not. | |
749 | ||
750 | RELAX_DELAY_SLOT | |
751 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
752 | delay slot. | |
4d7206a2 RS |
753 | |
754 | The frag's "opcode" points to the first fixup for relaxable code. | |
755 | ||
756 | Relaxable macros are generated using a sequence such as: | |
757 | ||
758 | relax_start (SYMBOL); | |
759 | ... generate first expansion ... | |
760 | relax_switch (); | |
761 | ... generate second expansion ... | |
762 | relax_end (); | |
763 | ||
764 | The code and fixups for the unwanted alternative are discarded | |
765 | by md_convert_frag. */ | |
584892a6 | 766 | #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) |
4d7206a2 | 767 | |
584892a6 RS |
768 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
769 | #define RELAX_SECOND(X) ((X) & 0xff) | |
770 | #define RELAX_USE_SECOND 0x10000 | |
771 | #define RELAX_SECOND_LONGER 0x20000 | |
772 | #define RELAX_NOMACRO 0x40000 | |
773 | #define RELAX_DELAY_SLOT 0x80000 | |
252b5132 | 774 | |
4a6a3df4 AO |
775 | /* Branch without likely bit. If label is out of range, we turn: |
776 | ||
777 | beq reg1, reg2, label | |
778 | delay slot | |
779 | ||
780 | into | |
781 | ||
782 | bne reg1, reg2, 0f | |
783 | nop | |
784 | j label | |
785 | 0: delay slot | |
786 | ||
787 | with the following opcode replacements: | |
788 | ||
789 | beq <-> bne | |
790 | blez <-> bgtz | |
791 | bltz <-> bgez | |
792 | bc1f <-> bc1t | |
793 | ||
794 | bltzal <-> bgezal (with jal label instead of j label) | |
795 | ||
796 | Even though keeping the delay slot instruction in the delay slot of | |
797 | the branch would be more efficient, it would be very tricky to do | |
798 | correctly, because we'd have to introduce a variable frag *after* | |
799 | the delay slot instruction, and expand that instead. Let's do it | |
800 | the easy way for now, even if the branch-not-taken case now costs | |
801 | one additional instruction. Out-of-range branches are not supposed | |
802 | to be common, anyway. | |
803 | ||
804 | Branch likely. If label is out of range, we turn: | |
805 | ||
806 | beql reg1, reg2, label | |
807 | delay slot (annulled if branch not taken) | |
808 | ||
809 | into | |
810 | ||
811 | beql reg1, reg2, 1f | |
812 | nop | |
813 | beql $0, $0, 2f | |
814 | nop | |
815 | 1: j[al] label | |
816 | delay slot (executed only if branch taken) | |
817 | 2: | |
818 | ||
819 | It would be possible to generate a shorter sequence by losing the | |
820 | likely bit, generating something like: | |
b34976b6 | 821 | |
4a6a3df4 AO |
822 | bne reg1, reg2, 0f |
823 | nop | |
824 | j[al] label | |
825 | delay slot (executed only if branch taken) | |
826 | 0: | |
827 | ||
828 | beql -> bne | |
829 | bnel -> beq | |
830 | blezl -> bgtz | |
831 | bgtzl -> blez | |
832 | bltzl -> bgez | |
833 | bgezl -> bltz | |
834 | bc1fl -> bc1t | |
835 | bc1tl -> bc1f | |
836 | ||
837 | bltzall -> bgezal (with jal label instead of j label) | |
838 | bgezall -> bltzal (ditto) | |
839 | ||
840 | ||
841 | but it's not clear that it would actually improve performance. */ | |
af6ae2ad | 842 | #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \ |
4a6a3df4 AO |
843 | ((relax_substateT) \ |
844 | (0xc0000000 \ | |
845 | | ((toofar) ? 1 : 0) \ | |
846 | | ((link) ? 2 : 0) \ | |
847 | | ((likely) ? 4 : 0) \ | |
af6ae2ad | 848 | | ((uncond) ? 8 : 0))) |
4a6a3df4 | 849 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
4a6a3df4 AO |
850 | #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0) |
851 | #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0) | |
852 | #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0) | |
ae6063d4 | 853 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0) |
4a6a3df4 | 854 | |
252b5132 RH |
855 | /* For mips16 code, we use an entirely different form of relaxation. |
856 | mips16 supports two versions of most instructions which take | |
857 | immediate values: a small one which takes some small value, and a | |
858 | larger one which takes a 16 bit value. Since branches also follow | |
859 | this pattern, relaxing these values is required. | |
860 | ||
861 | We can assemble both mips16 and normal MIPS code in a single | |
862 | object. Therefore, we need to support this type of relaxation at | |
863 | the same time that we support the relaxation described above. We | |
864 | use the high bit of the subtype field to distinguish these cases. | |
865 | ||
866 | The information we store for this type of relaxation is the | |
867 | argument code found in the opcode file for this relocation, whether | |
868 | the user explicitly requested a small or extended form, and whether | |
869 | the relocation is in a jump or jal delay slot. That tells us the | |
870 | size of the value, and how it should be stored. We also store | |
871 | whether the fragment is considered to be extended or not. We also | |
872 | store whether this is known to be a branch to a different section, | |
873 | whether we have tried to relax this frag yet, and whether we have | |
874 | ever extended a PC relative fragment because of a shift count. */ | |
875 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
876 | (0x80000000 \ | |
877 | | ((type) & 0xff) \ | |
878 | | ((small) ? 0x100 : 0) \ | |
879 | | ((ext) ? 0x200 : 0) \ | |
880 | | ((dslot) ? 0x400 : 0) \ | |
881 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 882 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
883 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
884 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
885 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
886 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
887 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
888 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
889 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
890 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
891 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
892 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
893 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 CD |
894 | |
895 | /* Is the given value a sign-extended 32-bit value? */ | |
896 | #define IS_SEXT_32BIT_NUM(x) \ | |
897 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
898 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
899 | ||
900 | /* Is the given value a sign-extended 16-bit value? */ | |
901 | #define IS_SEXT_16BIT_NUM(x) \ | |
902 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
903 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
904 | ||
2051e8c4 MR |
905 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ |
906 | #define IS_ZEXT_32BIT_NUM(x) \ | |
907 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
908 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
909 | ||
bf12938e RS |
910 | /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in |
911 | VALUE << SHIFT. VALUE is evaluated exactly once. */ | |
912 | #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \ | |
913 | (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \ | |
914 | | (((VALUE) & (MASK)) << (SHIFT))) | |
915 | ||
916 | /* Extract bits MASK << SHIFT from STRUCT and shift them right | |
917 | SHIFT places. */ | |
918 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
919 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
920 | ||
921 | /* Change INSN's opcode so that the operand given by FIELD has value VALUE. | |
922 | INSN is a mips_cl_insn structure and VALUE is evaluated exactly once. | |
923 | ||
924 | include/opcode/mips.h specifies operand fields using the macros | |
925 | OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start | |
926 | with "MIPS16OP" instead of "OP". */ | |
927 | #define INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
928 | INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD) | |
929 | #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
930 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
931 | MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD) | |
932 | ||
933 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ | |
934 | #define EXTRACT_OPERAND(FIELD, INSN) \ | |
935 | EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) | |
936 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ | |
937 | EXTRACT_BITS ((INSN).insn_opcode, \ | |
938 | MIPS16OP_MASK_##FIELD, \ | |
939 | MIPS16OP_SH_##FIELD) | |
4d7206a2 RS |
940 | \f |
941 | /* Global variables used when generating relaxable macros. See the | |
942 | comment above RELAX_ENCODE for more details about how relaxation | |
943 | is used. */ | |
944 | static struct { | |
945 | /* 0 if we're not emitting a relaxable macro. | |
946 | 1 if we're emitting the first of the two relaxation alternatives. | |
947 | 2 if we're emitting the second alternative. */ | |
948 | int sequence; | |
949 | ||
950 | /* The first relaxable fixup in the current frag. (In other words, | |
951 | the first fixup that refers to relaxable code.) */ | |
952 | fixS *first_fixup; | |
953 | ||
954 | /* sizes[0] says how many bytes of the first alternative are stored in | |
955 | the current frag. Likewise sizes[1] for the second alternative. */ | |
956 | unsigned int sizes[2]; | |
957 | ||
958 | /* The symbol on which the choice of sequence depends. */ | |
959 | symbolS *symbol; | |
960 | } mips_relax; | |
252b5132 | 961 | \f |
584892a6 RS |
962 | /* Global variables used to decide whether a macro needs a warning. */ |
963 | static struct { | |
964 | /* True if the macro is in a branch delay slot. */ | |
965 | bfd_boolean delay_slot_p; | |
966 | ||
967 | /* For relaxable macros, sizes[0] is the length of the first alternative | |
968 | in bytes and sizes[1] is the length of the second alternative. | |
969 | For non-relaxable macros, both elements give the length of the | |
970 | macro in bytes. */ | |
971 | unsigned int sizes[2]; | |
972 | ||
973 | /* The first variant frag for this macro. */ | |
974 | fragS *first_frag; | |
975 | } mips_macro_warning; | |
976 | \f | |
252b5132 RH |
977 | /* Prototypes for static functions. */ |
978 | ||
17a2f251 | 979 | #define internalError() \ |
252b5132 | 980 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) |
252b5132 RH |
981 | |
982 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
983 | ||
b34976b6 | 984 | static void append_insn |
4d7206a2 | 985 | (struct mips_cl_insn *ip, expressionS *p, bfd_reloc_code_real_type *r); |
7d10b47d | 986 | static void mips_no_prev_insn (void); |
b34976b6 | 987 | static void mips16_macro_build |
67c0d1eb RS |
988 | (expressionS *, const char *, const char *, va_list); |
989 | static void load_register (int, expressionS *, int); | |
584892a6 RS |
990 | static void macro_start (void); |
991 | static void macro_end (void); | |
17a2f251 TS |
992 | static void macro (struct mips_cl_insn * ip); |
993 | static void mips16_macro (struct mips_cl_insn * ip); | |
252b5132 | 994 | #ifdef LOSING_COMPILER |
17a2f251 | 995 | static void macro2 (struct mips_cl_insn * ip); |
252b5132 | 996 | #endif |
17a2f251 TS |
997 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
998 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 999 | static void mips16_immed |
17a2f251 TS |
1000 | (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean, |
1001 | unsigned long *, bfd_boolean *, unsigned short *); | |
5e0116d5 | 1002 | static size_t my_getSmallExpression |
17a2f251 TS |
1003 | (expressionS *, bfd_reloc_code_real_type *, char *); |
1004 | static void my_getExpression (expressionS *, char *); | |
1005 | static void s_align (int); | |
1006 | static void s_change_sec (int); | |
1007 | static void s_change_section (int); | |
1008 | static void s_cons (int); | |
1009 | static void s_float_cons (int); | |
1010 | static void s_mips_globl (int); | |
1011 | static void s_option (int); | |
1012 | static void s_mipsset (int); | |
1013 | static void s_abicalls (int); | |
1014 | static void s_cpload (int); | |
1015 | static void s_cpsetup (int); | |
1016 | static void s_cplocal (int); | |
1017 | static void s_cprestore (int); | |
1018 | static void s_cpreturn (int); | |
1019 | static void s_gpvalue (int); | |
1020 | static void s_gpword (int); | |
1021 | static void s_gpdword (int); | |
1022 | static void s_cpadd (int); | |
1023 | static void s_insn (int); | |
1024 | static void md_obj_begin (void); | |
1025 | static void md_obj_end (void); | |
1026 | static void s_mips_ent (int); | |
1027 | static void s_mips_end (int); | |
1028 | static void s_mips_frame (int); | |
1029 | static void s_mips_mask (int reg_type); | |
1030 | static void s_mips_stab (int); | |
1031 | static void s_mips_weakext (int); | |
1032 | static void s_mips_file (int); | |
1033 | static void s_mips_loc (int); | |
1034 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 1035 | static int relaxed_branch_length (fragS *, asection *, int); |
17a2f251 | 1036 | static int validate_mips_insn (const struct mips_opcode *); |
e7af610e NC |
1037 | |
1038 | /* Table and functions used to map between CPU/ISA names, and | |
1039 | ISA levels, and CPU numbers. */ | |
1040 | ||
e972090a NC |
1041 | struct mips_cpu_info |
1042 | { | |
e7af610e | 1043 | const char *name; /* CPU or ISA name. */ |
ad3fea08 | 1044 | int flags; /* ASEs available, or ISA flag. */ |
e7af610e NC |
1045 | int isa; /* ISA level. */ |
1046 | int cpu; /* CPU number (default CPU if ISA). */ | |
1047 | }; | |
1048 | ||
ad3fea08 TS |
1049 | #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ |
1050 | #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */ | |
1051 | #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */ | |
1052 | #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */ | |
1053 | #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */ | |
1054 | #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */ | |
1055 | ||
17a2f251 TS |
1056 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
1057 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
1058 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 RH |
1059 | \f |
1060 | /* Pseudo-op table. | |
1061 | ||
1062 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
1063 | should be defined here, but are currently unsupported: .alias, | |
1064 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
1065 | ||
1066 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1067 | specific to the type of debugging information being generated, and | |
1068 | should be defined by the object format: .aent, .begin, .bend, | |
1069 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
1070 | .vreg. | |
1071 | ||
1072 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1073 | not MIPS CPU specific, but are also not specific to the object file | |
1074 | format. This file is probably the best place to define them, but | |
1075 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
1076 | .struct. */ | |
1077 | ||
e972090a NC |
1078 | static const pseudo_typeS mips_pseudo_table[] = |
1079 | { | |
beae10d5 | 1080 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1081 | {"option", s_option, 0}, |
1082 | {"set", s_mipsset, 0}, | |
1083 | {"rdata", s_change_sec, 'r'}, | |
1084 | {"sdata", s_change_sec, 's'}, | |
1085 | {"livereg", s_ignore, 0}, | |
1086 | {"abicalls", s_abicalls, 0}, | |
1087 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1088 | {"cpsetup", s_cpsetup, 0}, |
1089 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1090 | {"cprestore", s_cprestore, 0}, |
6478892d TS |
1091 | {"cpreturn", s_cpreturn, 0}, |
1092 | {"gpvalue", s_gpvalue, 0}, | |
252b5132 | 1093 | {"gpword", s_gpword, 0}, |
10181a0d | 1094 | {"gpdword", s_gpdword, 0}, |
252b5132 RH |
1095 | {"cpadd", s_cpadd, 0}, |
1096 | {"insn", s_insn, 0}, | |
1097 | ||
beae10d5 | 1098 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 RH |
1099 | chips. */ |
1100 | {"asciiz", stringer, 1}, | |
1101 | {"bss", s_change_sec, 'b'}, | |
1102 | {"err", s_err, 0}, | |
1103 | {"half", s_cons, 1}, | |
1104 | {"dword", s_cons, 3}, | |
1105 | {"weakext", s_mips_weakext, 0}, | |
7c752c2a TS |
1106 | {"origin", s_org, 0}, |
1107 | {"repeat", s_rept, 0}, | |
252b5132 | 1108 | |
beae10d5 | 1109 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1110 | here for one reason or another. */ |
1111 | {"align", s_align, 0}, | |
1112 | {"byte", s_cons, 0}, | |
1113 | {"data", s_change_sec, 'd'}, | |
1114 | {"double", s_float_cons, 'd'}, | |
1115 | {"float", s_float_cons, 'f'}, | |
1116 | {"globl", s_mips_globl, 0}, | |
1117 | {"global", s_mips_globl, 0}, | |
1118 | {"hword", s_cons, 1}, | |
1119 | {"int", s_cons, 2}, | |
1120 | {"long", s_cons, 2}, | |
1121 | {"octa", s_cons, 4}, | |
1122 | {"quad", s_cons, 3}, | |
cca86cc8 | 1123 | {"section", s_change_section, 0}, |
252b5132 RH |
1124 | {"short", s_cons, 1}, |
1125 | {"single", s_float_cons, 'f'}, | |
1126 | {"stabn", s_mips_stab, 'n'}, | |
1127 | {"text", s_change_sec, 't'}, | |
1128 | {"word", s_cons, 2}, | |
add56521 | 1129 | |
add56521 | 1130 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1131 | |
43841e91 | 1132 | { NULL, NULL, 0 }, |
252b5132 RH |
1133 | }; |
1134 | ||
e972090a NC |
1135 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1136 | { | |
beae10d5 KH |
1137 | /* These pseudo-ops should be defined by the object file format. |
1138 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1139 | {"aent", s_mips_ent, 1}, |
1140 | {"bgnb", s_ignore, 0}, | |
1141 | {"end", s_mips_end, 0}, | |
1142 | {"endb", s_ignore, 0}, | |
1143 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1144 | {"file", s_mips_file, 0}, |
252b5132 RH |
1145 | {"fmask", s_mips_mask, 'F'}, |
1146 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1147 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1148 | {"mask", s_mips_mask, 'R'}, |
1149 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1150 | { NULL, NULL, 0 }, |
252b5132 RH |
1151 | }; |
1152 | ||
17a2f251 | 1153 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1154 | |
1155 | void | |
17a2f251 | 1156 | mips_pop_insert (void) |
252b5132 RH |
1157 | { |
1158 | pop_insert (mips_pseudo_table); | |
1159 | if (! ECOFF_DEBUGGING) | |
1160 | pop_insert (mips_nonecoff_pseudo_table); | |
1161 | } | |
1162 | \f | |
1163 | /* Symbols labelling the current insn. */ | |
1164 | ||
e972090a NC |
1165 | struct insn_label_list |
1166 | { | |
252b5132 RH |
1167 | struct insn_label_list *next; |
1168 | symbolS *label; | |
1169 | }; | |
1170 | ||
252b5132 | 1171 | static struct insn_label_list *free_insn_labels; |
a8dbcb85 | 1172 | #define label_list tc_segment_info_data |
252b5132 | 1173 | |
17a2f251 | 1174 | static void mips_clear_insn_labels (void); |
252b5132 RH |
1175 | |
1176 | static inline void | |
17a2f251 | 1177 | mips_clear_insn_labels (void) |
252b5132 RH |
1178 | { |
1179 | register struct insn_label_list **pl; | |
a8dbcb85 | 1180 | segment_info_type *si; |
252b5132 | 1181 | |
a8dbcb85 TS |
1182 | if (now_seg) |
1183 | { | |
1184 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1185 | ; | |
1186 | ||
1187 | si = seg_info (now_seg); | |
1188 | *pl = si->label_list; | |
1189 | si->label_list = NULL; | |
1190 | } | |
252b5132 | 1191 | } |
a8dbcb85 | 1192 | |
252b5132 RH |
1193 | \f |
1194 | static char *expr_end; | |
1195 | ||
1196 | /* Expressions which appear in instructions. These are set by | |
1197 | mips_ip. */ | |
1198 | ||
1199 | static expressionS imm_expr; | |
5f74bc13 | 1200 | static expressionS imm2_expr; |
252b5132 RH |
1201 | static expressionS offset_expr; |
1202 | ||
1203 | /* Relocs associated with imm_expr and offset_expr. */ | |
1204 | ||
f6688943 TS |
1205 | static bfd_reloc_code_real_type imm_reloc[3] |
1206 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1207 | static bfd_reloc_code_real_type offset_reloc[3] | |
1208 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1209 | |
252b5132 RH |
1210 | /* These are set by mips16_ip if an explicit extension is used. */ |
1211 | ||
b34976b6 | 1212 | static bfd_boolean mips16_small, mips16_ext; |
252b5132 | 1213 | |
7ed4a06a | 1214 | #ifdef OBJ_ELF |
ecb4347a DJ |
1215 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1216 | ECOFF debugging. */ | |
252b5132 RH |
1217 | |
1218 | static segT pdr_seg; | |
7ed4a06a | 1219 | #endif |
252b5132 | 1220 | |
e013f690 TS |
1221 | /* The default target format to use. */ |
1222 | ||
1223 | const char * | |
17a2f251 | 1224 | mips_target_format (void) |
e013f690 TS |
1225 | { |
1226 | switch (OUTPUT_FLAVOR) | |
1227 | { | |
e013f690 TS |
1228 | case bfd_target_ecoff_flavour: |
1229 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1230 | case bfd_target_coff_flavour: | |
1231 | return "pe-mips"; | |
1232 | case bfd_target_elf_flavour: | |
0a44bf69 RS |
1233 | #ifdef TE_VXWORKS |
1234 | if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI) | |
1235 | return (target_big_endian | |
1236 | ? "elf32-bigmips-vxworks" | |
1237 | : "elf32-littlemips-vxworks"); | |
1238 | #endif | |
e013f690 | 1239 | #ifdef TE_TMIPS |
cfe86eaa | 1240 | /* This is traditional mips. */ |
e013f690 | 1241 | return (target_big_endian |
cfe86eaa TS |
1242 | ? (HAVE_64BIT_OBJECTS |
1243 | ? "elf64-tradbigmips" | |
1244 | : (HAVE_NEWABI | |
1245 | ? "elf32-ntradbigmips" : "elf32-tradbigmips")) | |
1246 | : (HAVE_64BIT_OBJECTS | |
1247 | ? "elf64-tradlittlemips" | |
1248 | : (HAVE_NEWABI | |
1249 | ? "elf32-ntradlittlemips" : "elf32-tradlittlemips"))); | |
e013f690 TS |
1250 | #else |
1251 | return (target_big_endian | |
cfe86eaa TS |
1252 | ? (HAVE_64BIT_OBJECTS |
1253 | ? "elf64-bigmips" | |
1254 | : (HAVE_NEWABI | |
1255 | ? "elf32-nbigmips" : "elf32-bigmips")) | |
1256 | : (HAVE_64BIT_OBJECTS | |
1257 | ? "elf64-littlemips" | |
1258 | : (HAVE_NEWABI | |
1259 | ? "elf32-nlittlemips" : "elf32-littlemips"))); | |
e013f690 TS |
1260 | #endif |
1261 | default: | |
1262 | abort (); | |
1263 | return NULL; | |
1264 | } | |
1265 | } | |
1266 | ||
1e915849 RS |
1267 | /* Return the length of instruction INSN. */ |
1268 | ||
1269 | static inline unsigned int | |
1270 | insn_length (const struct mips_cl_insn *insn) | |
1271 | { | |
1272 | if (!mips_opts.mips16) | |
1273 | return 4; | |
1274 | return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2; | |
1275 | } | |
1276 | ||
1277 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
1278 | ||
1279 | static void | |
1280 | create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) | |
1281 | { | |
1282 | size_t i; | |
1283 | ||
1284 | insn->insn_mo = mo; | |
1285 | insn->use_extend = FALSE; | |
1286 | insn->extend = 0; | |
1287 | insn->insn_opcode = mo->match; | |
1288 | insn->frag = NULL; | |
1289 | insn->where = 0; | |
1290 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1291 | insn->fixp[i] = NULL; | |
1292 | insn->fixed_p = (mips_opts.noreorder > 0); | |
1293 | insn->noreorder_p = (mips_opts.noreorder > 0); | |
1294 | insn->mips16_absolute_jump_p = 0; | |
1295 | } | |
1296 | ||
1297 | /* Install INSN at the location specified by its "frag" and "where" fields. */ | |
1298 | ||
1299 | static void | |
1300 | install_insn (const struct mips_cl_insn *insn) | |
1301 | { | |
1302 | char *f = insn->frag->fr_literal + insn->where; | |
1303 | if (!mips_opts.mips16) | |
1304 | md_number_to_chars (f, insn->insn_opcode, 4); | |
1305 | else if (insn->mips16_absolute_jump_p) | |
1306 | { | |
1307 | md_number_to_chars (f, insn->insn_opcode >> 16, 2); | |
1308 | md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2); | |
1309 | } | |
1310 | else | |
1311 | { | |
1312 | if (insn->use_extend) | |
1313 | { | |
1314 | md_number_to_chars (f, 0xf000 | insn->extend, 2); | |
1315 | f += 2; | |
1316 | } | |
1317 | md_number_to_chars (f, insn->insn_opcode, 2); | |
1318 | } | |
1319 | } | |
1320 | ||
1321 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
1322 | and install the opcode in the new location. */ | |
1323 | ||
1324 | static void | |
1325 | move_insn (struct mips_cl_insn *insn, fragS *frag, long where) | |
1326 | { | |
1327 | size_t i; | |
1328 | ||
1329 | insn->frag = frag; | |
1330 | insn->where = where; | |
1331 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1332 | if (insn->fixp[i] != NULL) | |
1333 | { | |
1334 | insn->fixp[i]->fx_frag = frag; | |
1335 | insn->fixp[i]->fx_where = where; | |
1336 | } | |
1337 | install_insn (insn); | |
1338 | } | |
1339 | ||
1340 | /* Add INSN to the end of the output. */ | |
1341 | ||
1342 | static void | |
1343 | add_fixed_insn (struct mips_cl_insn *insn) | |
1344 | { | |
1345 | char *f = frag_more (insn_length (insn)); | |
1346 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
1347 | } | |
1348 | ||
1349 | /* Start a variant frag and move INSN to the start of the variant part, | |
1350 | marking it as fixed. The other arguments are as for frag_var. */ | |
1351 | ||
1352 | static void | |
1353 | add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, | |
1354 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
1355 | { | |
1356 | frag_grow (max_chars); | |
1357 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
1358 | insn->fixed_p = 1; | |
1359 | frag_var (rs_machine_dependent, max_chars, var, | |
1360 | subtype, symbol, offset, NULL); | |
1361 | } | |
1362 | ||
1363 | /* Insert N copies of INSN into the history buffer, starting at | |
1364 | position FIRST. Neither FIRST nor N need to be clipped. */ | |
1365 | ||
1366 | static void | |
1367 | insert_into_history (unsigned int first, unsigned int n, | |
1368 | const struct mips_cl_insn *insn) | |
1369 | { | |
1370 | if (mips_relax.sequence != 2) | |
1371 | { | |
1372 | unsigned int i; | |
1373 | ||
1374 | for (i = ARRAY_SIZE (history); i-- > first;) | |
1375 | if (i >= first + n) | |
1376 | history[i] = history[i - n]; | |
1377 | else | |
1378 | history[i] = *insn; | |
1379 | } | |
1380 | } | |
1381 | ||
1382 | /* Emit a nop instruction, recording it in the history buffer. */ | |
1383 | ||
1384 | static void | |
1385 | emit_nop (void) | |
1386 | { | |
1387 | add_fixed_insn (NOP_INSN); | |
1388 | insert_into_history (0, 1, NOP_INSN); | |
1389 | } | |
1390 | ||
71400594 RS |
1391 | /* Initialize vr4120_conflicts. There is a bit of duplication here: |
1392 | the idea is to make it obvious at a glance that each errata is | |
1393 | included. */ | |
1394 | ||
1395 | static void | |
1396 | init_vr4120_conflicts (void) | |
1397 | { | |
1398 | #define CONFLICT(FIRST, SECOND) \ | |
1399 | vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND | |
1400 | ||
1401 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
1402 | CONFLICT (MACC, DIV); | |
1403 | CONFLICT (DMACC, DIV); | |
1404 | ||
1405 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ | |
1406 | CONFLICT (DMULT, DMULT); | |
1407 | CONFLICT (DMULT, DMACC); | |
1408 | CONFLICT (DMACC, DMULT); | |
1409 | CONFLICT (DMACC, DMACC); | |
1410 | ||
1411 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
1412 | CONFLICT (MACC, MTHILO); | |
1413 | CONFLICT (DMACC, MTHILO); | |
1414 | ||
1415 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU | |
1416 | instruction is executed immediately after a MACC or DMACC | |
1417 | instruction, the result of [either instruction] is incorrect." */ | |
1418 | CONFLICT (MACC, MULT); | |
1419 | CONFLICT (MACC, DMULT); | |
1420 | CONFLICT (DMACC, MULT); | |
1421 | CONFLICT (DMACC, DMULT); | |
1422 | ||
1423 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
1424 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
1425 | DDIV or DDIVU instruction, the result of the MACC or | |
1426 | DMACC instruction is incorrect.". */ | |
1427 | CONFLICT (DMULT, MACC); | |
1428 | CONFLICT (DMULT, DMACC); | |
1429 | CONFLICT (DIV, MACC); | |
1430 | CONFLICT (DIV, DMACC); | |
1431 | ||
1432 | #undef CONFLICT | |
1433 | } | |
1434 | ||
707bfff6 TS |
1435 | struct regname { |
1436 | const char *name; | |
1437 | unsigned int num; | |
1438 | }; | |
1439 | ||
1440 | #define RTYPE_MASK 0x1ff00 | |
1441 | #define RTYPE_NUM 0x00100 | |
1442 | #define RTYPE_FPU 0x00200 | |
1443 | #define RTYPE_FCC 0x00400 | |
1444 | #define RTYPE_VEC 0x00800 | |
1445 | #define RTYPE_GP 0x01000 | |
1446 | #define RTYPE_CP0 0x02000 | |
1447 | #define RTYPE_PC 0x04000 | |
1448 | #define RTYPE_ACC 0x08000 | |
1449 | #define RTYPE_CCC 0x10000 | |
1450 | #define RNUM_MASK 0x000ff | |
1451 | #define RWARN 0x80000 | |
1452 | ||
1453 | #define GENERIC_REGISTER_NUMBERS \ | |
1454 | {"$0", RTYPE_NUM | 0}, \ | |
1455 | {"$1", RTYPE_NUM | 1}, \ | |
1456 | {"$2", RTYPE_NUM | 2}, \ | |
1457 | {"$3", RTYPE_NUM | 3}, \ | |
1458 | {"$4", RTYPE_NUM | 4}, \ | |
1459 | {"$5", RTYPE_NUM | 5}, \ | |
1460 | {"$6", RTYPE_NUM | 6}, \ | |
1461 | {"$7", RTYPE_NUM | 7}, \ | |
1462 | {"$8", RTYPE_NUM | 8}, \ | |
1463 | {"$9", RTYPE_NUM | 9}, \ | |
1464 | {"$10", RTYPE_NUM | 10}, \ | |
1465 | {"$11", RTYPE_NUM | 11}, \ | |
1466 | {"$12", RTYPE_NUM | 12}, \ | |
1467 | {"$13", RTYPE_NUM | 13}, \ | |
1468 | {"$14", RTYPE_NUM | 14}, \ | |
1469 | {"$15", RTYPE_NUM | 15}, \ | |
1470 | {"$16", RTYPE_NUM | 16}, \ | |
1471 | {"$17", RTYPE_NUM | 17}, \ | |
1472 | {"$18", RTYPE_NUM | 18}, \ | |
1473 | {"$19", RTYPE_NUM | 19}, \ | |
1474 | {"$20", RTYPE_NUM | 20}, \ | |
1475 | {"$21", RTYPE_NUM | 21}, \ | |
1476 | {"$22", RTYPE_NUM | 22}, \ | |
1477 | {"$23", RTYPE_NUM | 23}, \ | |
1478 | {"$24", RTYPE_NUM | 24}, \ | |
1479 | {"$25", RTYPE_NUM | 25}, \ | |
1480 | {"$26", RTYPE_NUM | 26}, \ | |
1481 | {"$27", RTYPE_NUM | 27}, \ | |
1482 | {"$28", RTYPE_NUM | 28}, \ | |
1483 | {"$29", RTYPE_NUM | 29}, \ | |
1484 | {"$30", RTYPE_NUM | 30}, \ | |
1485 | {"$31", RTYPE_NUM | 31} | |
1486 | ||
1487 | #define FPU_REGISTER_NAMES \ | |
1488 | {"$f0", RTYPE_FPU | 0}, \ | |
1489 | {"$f1", RTYPE_FPU | 1}, \ | |
1490 | {"$f2", RTYPE_FPU | 2}, \ | |
1491 | {"$f3", RTYPE_FPU | 3}, \ | |
1492 | {"$f4", RTYPE_FPU | 4}, \ | |
1493 | {"$f5", RTYPE_FPU | 5}, \ | |
1494 | {"$f6", RTYPE_FPU | 6}, \ | |
1495 | {"$f7", RTYPE_FPU | 7}, \ | |
1496 | {"$f8", RTYPE_FPU | 8}, \ | |
1497 | {"$f9", RTYPE_FPU | 9}, \ | |
1498 | {"$f10", RTYPE_FPU | 10}, \ | |
1499 | {"$f11", RTYPE_FPU | 11}, \ | |
1500 | {"$f12", RTYPE_FPU | 12}, \ | |
1501 | {"$f13", RTYPE_FPU | 13}, \ | |
1502 | {"$f14", RTYPE_FPU | 14}, \ | |
1503 | {"$f15", RTYPE_FPU | 15}, \ | |
1504 | {"$f16", RTYPE_FPU | 16}, \ | |
1505 | {"$f17", RTYPE_FPU | 17}, \ | |
1506 | {"$f18", RTYPE_FPU | 18}, \ | |
1507 | {"$f19", RTYPE_FPU | 19}, \ | |
1508 | {"$f20", RTYPE_FPU | 20}, \ | |
1509 | {"$f21", RTYPE_FPU | 21}, \ | |
1510 | {"$f22", RTYPE_FPU | 22}, \ | |
1511 | {"$f23", RTYPE_FPU | 23}, \ | |
1512 | {"$f24", RTYPE_FPU | 24}, \ | |
1513 | {"$f25", RTYPE_FPU | 25}, \ | |
1514 | {"$f26", RTYPE_FPU | 26}, \ | |
1515 | {"$f27", RTYPE_FPU | 27}, \ | |
1516 | {"$f28", RTYPE_FPU | 28}, \ | |
1517 | {"$f29", RTYPE_FPU | 29}, \ | |
1518 | {"$f30", RTYPE_FPU | 30}, \ | |
1519 | {"$f31", RTYPE_FPU | 31} | |
1520 | ||
1521 | #define FPU_CONDITION_CODE_NAMES \ | |
1522 | {"$fcc0", RTYPE_FCC | 0}, \ | |
1523 | {"$fcc1", RTYPE_FCC | 1}, \ | |
1524 | {"$fcc2", RTYPE_FCC | 2}, \ | |
1525 | {"$fcc3", RTYPE_FCC | 3}, \ | |
1526 | {"$fcc4", RTYPE_FCC | 4}, \ | |
1527 | {"$fcc5", RTYPE_FCC | 5}, \ | |
1528 | {"$fcc6", RTYPE_FCC | 6}, \ | |
1529 | {"$fcc7", RTYPE_FCC | 7} | |
1530 | ||
1531 | #define COPROC_CONDITION_CODE_NAMES \ | |
1532 | {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \ | |
1533 | {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \ | |
1534 | {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \ | |
1535 | {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \ | |
1536 | {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \ | |
1537 | {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \ | |
1538 | {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \ | |
1539 | {"$cc7", RTYPE_FCC | RTYPE_CCC | 7} | |
1540 | ||
1541 | #define N32N64_SYMBOLIC_REGISTER_NAMES \ | |
1542 | {"$a4", RTYPE_GP | 8}, \ | |
1543 | {"$a5", RTYPE_GP | 9}, \ | |
1544 | {"$a6", RTYPE_GP | 10}, \ | |
1545 | {"$a7", RTYPE_GP | 11}, \ | |
1546 | {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \ | |
1547 | {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \ | |
1548 | {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \ | |
1549 | {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \ | |
1550 | {"$t0", RTYPE_GP | 12}, \ | |
1551 | {"$t1", RTYPE_GP | 13}, \ | |
1552 | {"$t2", RTYPE_GP | 14}, \ | |
1553 | {"$t3", RTYPE_GP | 15} | |
1554 | ||
1555 | #define O32_SYMBOLIC_REGISTER_NAMES \ | |
1556 | {"$t0", RTYPE_GP | 8}, \ | |
1557 | {"$t1", RTYPE_GP | 9}, \ | |
1558 | {"$t2", RTYPE_GP | 10}, \ | |
1559 | {"$t3", RTYPE_GP | 11}, \ | |
1560 | {"$t4", RTYPE_GP | 12}, \ | |
1561 | {"$t5", RTYPE_GP | 13}, \ | |
1562 | {"$t6", RTYPE_GP | 14}, \ | |
1563 | {"$t7", RTYPE_GP | 15}, \ | |
1564 | {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \ | |
1565 | {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \ | |
1566 | {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \ | |
1567 | {"$ta3", RTYPE_GP | 15} /* alias for $t7 */ | |
1568 | ||
1569 | /* Remaining symbolic register names */ | |
1570 | #define SYMBOLIC_REGISTER_NAMES \ | |
1571 | {"$zero", RTYPE_GP | 0}, \ | |
1572 | {"$at", RTYPE_GP | 1}, \ | |
1573 | {"$AT", RTYPE_GP | 1}, \ | |
1574 | {"$v0", RTYPE_GP | 2}, \ | |
1575 | {"$v1", RTYPE_GP | 3}, \ | |
1576 | {"$a0", RTYPE_GP | 4}, \ | |
1577 | {"$a1", RTYPE_GP | 5}, \ | |
1578 | {"$a2", RTYPE_GP | 6}, \ | |
1579 | {"$a3", RTYPE_GP | 7}, \ | |
1580 | {"$s0", RTYPE_GP | 16}, \ | |
1581 | {"$s1", RTYPE_GP | 17}, \ | |
1582 | {"$s2", RTYPE_GP | 18}, \ | |
1583 | {"$s3", RTYPE_GP | 19}, \ | |
1584 | {"$s4", RTYPE_GP | 20}, \ | |
1585 | {"$s5", RTYPE_GP | 21}, \ | |
1586 | {"$s6", RTYPE_GP | 22}, \ | |
1587 | {"$s7", RTYPE_GP | 23}, \ | |
1588 | {"$t8", RTYPE_GP | 24}, \ | |
1589 | {"$t9", RTYPE_GP | 25}, \ | |
1590 | {"$k0", RTYPE_GP | 26}, \ | |
1591 | {"$kt0", RTYPE_GP | 26}, \ | |
1592 | {"$k1", RTYPE_GP | 27}, \ | |
1593 | {"$kt1", RTYPE_GP | 27}, \ | |
1594 | {"$gp", RTYPE_GP | 28}, \ | |
1595 | {"$sp", RTYPE_GP | 29}, \ | |
1596 | {"$s8", RTYPE_GP | 30}, \ | |
1597 | {"$fp", RTYPE_GP | 30}, \ | |
1598 | {"$ra", RTYPE_GP | 31} | |
1599 | ||
1600 | #define MIPS16_SPECIAL_REGISTER_NAMES \ | |
1601 | {"$pc", RTYPE_PC | 0} | |
1602 | ||
1603 | #define MDMX_VECTOR_REGISTER_NAMES \ | |
1604 | /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \ | |
1605 | /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \ | |
1606 | {"$v2", RTYPE_VEC | 2}, \ | |
1607 | {"$v3", RTYPE_VEC | 3}, \ | |
1608 | {"$v4", RTYPE_VEC | 4}, \ | |
1609 | {"$v5", RTYPE_VEC | 5}, \ | |
1610 | {"$v6", RTYPE_VEC | 6}, \ | |
1611 | {"$v7", RTYPE_VEC | 7}, \ | |
1612 | {"$v8", RTYPE_VEC | 8}, \ | |
1613 | {"$v9", RTYPE_VEC | 9}, \ | |
1614 | {"$v10", RTYPE_VEC | 10}, \ | |
1615 | {"$v11", RTYPE_VEC | 11}, \ | |
1616 | {"$v12", RTYPE_VEC | 12}, \ | |
1617 | {"$v13", RTYPE_VEC | 13}, \ | |
1618 | {"$v14", RTYPE_VEC | 14}, \ | |
1619 | {"$v15", RTYPE_VEC | 15}, \ | |
1620 | {"$v16", RTYPE_VEC | 16}, \ | |
1621 | {"$v17", RTYPE_VEC | 17}, \ | |
1622 | {"$v18", RTYPE_VEC | 18}, \ | |
1623 | {"$v19", RTYPE_VEC | 19}, \ | |
1624 | {"$v20", RTYPE_VEC | 20}, \ | |
1625 | {"$v21", RTYPE_VEC | 21}, \ | |
1626 | {"$v22", RTYPE_VEC | 22}, \ | |
1627 | {"$v23", RTYPE_VEC | 23}, \ | |
1628 | {"$v24", RTYPE_VEC | 24}, \ | |
1629 | {"$v25", RTYPE_VEC | 25}, \ | |
1630 | {"$v26", RTYPE_VEC | 26}, \ | |
1631 | {"$v27", RTYPE_VEC | 27}, \ | |
1632 | {"$v28", RTYPE_VEC | 28}, \ | |
1633 | {"$v29", RTYPE_VEC | 29}, \ | |
1634 | {"$v30", RTYPE_VEC | 30}, \ | |
1635 | {"$v31", RTYPE_VEC | 31} | |
1636 | ||
1637 | #define MIPS_DSP_ACCUMULATOR_NAMES \ | |
1638 | {"$ac0", RTYPE_ACC | 0}, \ | |
1639 | {"$ac1", RTYPE_ACC | 1}, \ | |
1640 | {"$ac2", RTYPE_ACC | 2}, \ | |
1641 | {"$ac3", RTYPE_ACC | 3} | |
1642 | ||
1643 | static const struct regname reg_names[] = { | |
1644 | GENERIC_REGISTER_NUMBERS, | |
1645 | FPU_REGISTER_NAMES, | |
1646 | FPU_CONDITION_CODE_NAMES, | |
1647 | COPROC_CONDITION_CODE_NAMES, | |
1648 | ||
1649 | /* The $txx registers depends on the abi, | |
1650 | these will be added later into the symbol table from | |
1651 | one of the tables below once mips_abi is set after | |
1652 | parsing of arguments from the command line. */ | |
1653 | SYMBOLIC_REGISTER_NAMES, | |
1654 | ||
1655 | MIPS16_SPECIAL_REGISTER_NAMES, | |
1656 | MDMX_VECTOR_REGISTER_NAMES, | |
1657 | MIPS_DSP_ACCUMULATOR_NAMES, | |
1658 | {0, 0} | |
1659 | }; | |
1660 | ||
1661 | static const struct regname reg_names_o32[] = { | |
1662 | O32_SYMBOLIC_REGISTER_NAMES, | |
1663 | {0, 0} | |
1664 | }; | |
1665 | ||
1666 | static const struct regname reg_names_n32n64[] = { | |
1667 | N32N64_SYMBOLIC_REGISTER_NAMES, | |
1668 | {0, 0} | |
1669 | }; | |
1670 | ||
1671 | static int | |
1672 | reg_lookup (char **s, unsigned int types, unsigned int *regnop) | |
1673 | { | |
1674 | symbolS *symbolP; | |
1675 | char *e; | |
1676 | char save_c; | |
1677 | int reg = -1; | |
1678 | ||
1679 | /* Find end of name. */ | |
1680 | e = *s; | |
1681 | if (is_name_beginner (*e)) | |
1682 | ++e; | |
1683 | while (is_part_of_name (*e)) | |
1684 | ++e; | |
1685 | ||
1686 | /* Terminate name. */ | |
1687 | save_c = *e; | |
1688 | *e = '\0'; | |
1689 | ||
1690 | /* Look for a register symbol. */ | |
1691 | if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section) | |
1692 | { | |
1693 | int r = S_GET_VALUE (symbolP); | |
1694 | if (r & types) | |
1695 | reg = r & RNUM_MASK; | |
1696 | else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2)) | |
1697 | /* Convert GP reg $v0/1 to MDMX reg $v0/1! */ | |
1698 | reg = (r & RNUM_MASK) - 2; | |
1699 | } | |
1700 | /* Else see if this is a register defined in an itbl entry. */ | |
1701 | else if ((types & RTYPE_GP) && itbl_have_entries) | |
1702 | { | |
1703 | char *n = *s; | |
1704 | unsigned long r; | |
1705 | ||
1706 | if (*n == '$') | |
1707 | ++n; | |
1708 | if (itbl_get_reg_val (n, &r)) | |
1709 | reg = r & RNUM_MASK; | |
1710 | } | |
1711 | ||
1712 | /* Advance to next token if a register was recognised. */ | |
1713 | if (reg >= 0) | |
1714 | *s = e; | |
1715 | else if (types & RWARN) | |
1716 | as_warn ("Unrecognized register name `%s'", *s); | |
1717 | ||
1718 | *e = save_c; | |
1719 | if (regnop) | |
1720 | *regnop = reg; | |
1721 | return reg >= 0; | |
1722 | } | |
1723 | ||
1724 | /* This function is called once, at assembler startup time. It should set up | |
1725 | all the tables, etc. that the MD part of the assembler will need. */ | |
156c2f8b | 1726 | |
252b5132 | 1727 | void |
17a2f251 | 1728 | md_begin (void) |
252b5132 | 1729 | { |
3994f87e | 1730 | const char *retval = NULL; |
156c2f8b | 1731 | int i = 0; |
252b5132 | 1732 | int broken = 0; |
1f25f5d3 | 1733 | |
0a44bf69 RS |
1734 | if (mips_pic != NO_PIC) |
1735 | { | |
1736 | if (g_switch_seen && g_switch_value != 0) | |
1737 | as_bad (_("-G may not be used in position-independent code")); | |
1738 | g_switch_value = 0; | |
1739 | } | |
1740 | ||
fef14a42 | 1741 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) |
252b5132 RH |
1742 | as_warn (_("Could not set architecture and machine")); |
1743 | ||
252b5132 RH |
1744 | op_hash = hash_new (); |
1745 | ||
1746 | for (i = 0; i < NUMOPCODES;) | |
1747 | { | |
1748 | const char *name = mips_opcodes[i].name; | |
1749 | ||
17a2f251 | 1750 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
1751 | if (retval != NULL) |
1752 | { | |
1753 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
1754 | mips_opcodes[i].name, retval); | |
1755 | /* Probably a memory allocation problem? Give up now. */ | |
1756 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1757 | } | |
1758 | do | |
1759 | { | |
1760 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
1761 | { | |
1762 | if (!validate_mips_insn (&mips_opcodes[i])) | |
1763 | broken = 1; | |
1e915849 RS |
1764 | if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
1765 | { | |
1766 | create_insn (&nop_insn, mips_opcodes + i); | |
1767 | nop_insn.fixed_p = 1; | |
1768 | } | |
252b5132 RH |
1769 | } |
1770 | ++i; | |
1771 | } | |
1772 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
1773 | } | |
1774 | ||
1775 | mips16_op_hash = hash_new (); | |
1776 | ||
1777 | i = 0; | |
1778 | while (i < bfd_mips16_num_opcodes) | |
1779 | { | |
1780 | const char *name = mips16_opcodes[i].name; | |
1781 | ||
17a2f251 | 1782 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
1783 | if (retval != NULL) |
1784 | as_fatal (_("internal: can't hash `%s': %s"), | |
1785 | mips16_opcodes[i].name, retval); | |
1786 | do | |
1787 | { | |
1788 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1789 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1790 | != mips16_opcodes[i].match)) | |
1791 | { | |
1792 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
1793 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1794 | broken = 1; | |
1795 | } | |
1e915849 RS |
1796 | if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
1797 | { | |
1798 | create_insn (&mips16_nop_insn, mips16_opcodes + i); | |
1799 | mips16_nop_insn.fixed_p = 1; | |
1800 | } | |
252b5132 RH |
1801 | ++i; |
1802 | } | |
1803 | while (i < bfd_mips16_num_opcodes | |
1804 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1805 | } | |
1806 | ||
1807 | if (broken) | |
1808 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1809 | ||
1810 | /* We add all the general register names to the symbol table. This | |
1811 | helps us detect invalid uses of them. */ | |
707bfff6 TS |
1812 | for (i = 0; reg_names[i].name; i++) |
1813 | symbol_table_insert (symbol_new (reg_names[i].name, reg_section, | |
1814 | reg_names[i].num, // & RNUM_MASK, | |
1815 | &zero_address_frag)); | |
1816 | if (HAVE_NEWABI) | |
1817 | for (i = 0; reg_names_n32n64[i].name; i++) | |
1818 | symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section, | |
1819 | reg_names_n32n64[i].num, // & RNUM_MASK, | |
252b5132 | 1820 | &zero_address_frag)); |
707bfff6 TS |
1821 | else |
1822 | for (i = 0; reg_names_o32[i].name; i++) | |
1823 | symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section, | |
1824 | reg_names_o32[i].num, // & RNUM_MASK, | |
6047c971 | 1825 | &zero_address_frag)); |
6047c971 | 1826 | |
7d10b47d | 1827 | mips_no_prev_insn (); |
252b5132 RH |
1828 | |
1829 | mips_gprmask = 0; | |
1830 | mips_cprmask[0] = 0; | |
1831 | mips_cprmask[1] = 0; | |
1832 | mips_cprmask[2] = 0; | |
1833 | mips_cprmask[3] = 0; | |
1834 | ||
1835 | /* set the default alignment for the text section (2**2) */ | |
1836 | record_alignment (text_section, 2); | |
1837 | ||
4d0d148d | 1838 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 | 1839 | |
707bfff6 | 1840 | #ifdef OBJ_ELF |
f43abd2b | 1841 | if (IS_ELF) |
252b5132 | 1842 | { |
0a44bf69 RS |
1843 | /* On a native system other than VxWorks, sections must be aligned |
1844 | to 16 byte boundaries. When configured for an embedded ELF | |
1845 | target, we don't bother. */ | |
1846 | if (strcmp (TARGET_OS, "elf") != 0 | |
1847 | && strcmp (TARGET_OS, "vxworks") != 0) | |
252b5132 RH |
1848 | { |
1849 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
1850 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
1851 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
1852 | } | |
1853 | ||
1854 | /* Create a .reginfo section for register masks and a .mdebug | |
1855 | section for debugging information. */ | |
1856 | { | |
1857 | segT seg; | |
1858 | subsegT subseg; | |
1859 | flagword flags; | |
1860 | segT sec; | |
1861 | ||
1862 | seg = now_seg; | |
1863 | subseg = now_subseg; | |
1864 | ||
1865 | /* The ABI says this section should be loaded so that the | |
1866 | running program can access it. However, we don't load it | |
1867 | if we are configured for an embedded target */ | |
1868 | flags = SEC_READONLY | SEC_DATA; | |
1869 | if (strcmp (TARGET_OS, "elf") != 0) | |
1870 | flags |= SEC_ALLOC | SEC_LOAD; | |
1871 | ||
316f5878 | 1872 | if (mips_abi != N64_ABI) |
252b5132 RH |
1873 | { |
1874 | sec = subseg_new (".reginfo", (subsegT) 0); | |
1875 | ||
195325d2 TS |
1876 | bfd_set_section_flags (stdoutput, sec, flags); |
1877 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 1878 | |
252b5132 | 1879 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
252b5132 RH |
1880 | } |
1881 | else | |
1882 | { | |
1883 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
1884 | .reginfo section. */ | |
1885 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
1886 | bfd_set_section_flags (stdoutput, sec, flags); |
1887 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 | 1888 | |
252b5132 RH |
1889 | /* Set up the option header. */ |
1890 | { | |
1891 | Elf_Internal_Options opthdr; | |
1892 | char *f; | |
1893 | ||
1894 | opthdr.kind = ODK_REGINFO; | |
1895 | opthdr.size = (sizeof (Elf_External_Options) | |
1896 | + sizeof (Elf64_External_RegInfo)); | |
1897 | opthdr.section = 0; | |
1898 | opthdr.info = 0; | |
1899 | f = frag_more (sizeof (Elf_External_Options)); | |
1900 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
1901 | (Elf_External_Options *) f); | |
1902 | ||
1903 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
1904 | } | |
252b5132 RH |
1905 | } |
1906 | ||
1907 | if (ECOFF_DEBUGGING) | |
1908 | { | |
1909 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1910 | (void) bfd_set_section_flags (stdoutput, sec, | |
1911 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1912 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1913 | } | |
f43abd2b | 1914 | else if (mips_flag_pdr) |
ecb4347a DJ |
1915 | { |
1916 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
1917 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
1918 | SEC_READONLY | SEC_RELOC | |
1919 | | SEC_DEBUGGING); | |
1920 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
1921 | } | |
252b5132 RH |
1922 | |
1923 | subseg_set (seg, subseg); | |
1924 | } | |
1925 | } | |
707bfff6 | 1926 | #endif /* OBJ_ELF */ |
252b5132 RH |
1927 | |
1928 | if (! ECOFF_DEBUGGING) | |
1929 | md_obj_begin (); | |
71400594 RS |
1930 | |
1931 | if (mips_fix_vr4120) | |
1932 | init_vr4120_conflicts (); | |
252b5132 RH |
1933 | } |
1934 | ||
1935 | void | |
17a2f251 | 1936 | md_mips_end (void) |
252b5132 RH |
1937 | { |
1938 | if (! ECOFF_DEBUGGING) | |
1939 | md_obj_end (); | |
1940 | } | |
1941 | ||
1942 | void | |
17a2f251 | 1943 | md_assemble (char *str) |
252b5132 RH |
1944 | { |
1945 | struct mips_cl_insn insn; | |
f6688943 TS |
1946 | bfd_reloc_code_real_type unused_reloc[3] |
1947 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
1948 | |
1949 | imm_expr.X_op = O_absent; | |
5f74bc13 | 1950 | imm2_expr.X_op = O_absent; |
252b5132 | 1951 | offset_expr.X_op = O_absent; |
f6688943 TS |
1952 | imm_reloc[0] = BFD_RELOC_UNUSED; |
1953 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
1954 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
1955 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
1956 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
1957 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
1958 | |
1959 | if (mips_opts.mips16) | |
1960 | mips16_ip (str, &insn); | |
1961 | else | |
1962 | { | |
1963 | mips_ip (str, &insn); | |
beae10d5 KH |
1964 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
1965 | str, insn.insn_opcode)); | |
252b5132 RH |
1966 | } |
1967 | ||
1968 | if (insn_error) | |
1969 | { | |
1970 | as_bad ("%s `%s'", insn_error, str); | |
1971 | return; | |
1972 | } | |
1973 | ||
1974 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
1975 | { | |
584892a6 | 1976 | macro_start (); |
252b5132 RH |
1977 | if (mips_opts.mips16) |
1978 | mips16_macro (&insn); | |
1979 | else | |
1980 | macro (&insn); | |
584892a6 | 1981 | macro_end (); |
252b5132 RH |
1982 | } |
1983 | else | |
1984 | { | |
1985 | if (imm_expr.X_op != O_absent) | |
4d7206a2 | 1986 | append_insn (&insn, &imm_expr, imm_reloc); |
252b5132 | 1987 | else if (offset_expr.X_op != O_absent) |
4d7206a2 | 1988 | append_insn (&insn, &offset_expr, offset_reloc); |
252b5132 | 1989 | else |
4d7206a2 | 1990 | append_insn (&insn, NULL, unused_reloc); |
252b5132 RH |
1991 | } |
1992 | } | |
1993 | ||
5919d012 | 1994 | /* Return true if the given relocation might need a matching %lo(). |
0a44bf69 RS |
1995 | This is only "might" because SVR4 R_MIPS_GOT16 relocations only |
1996 | need a matching %lo() when applied to local symbols. */ | |
5919d012 RS |
1997 | |
1998 | static inline bfd_boolean | |
17a2f251 | 1999 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 2000 | { |
3b91255e RS |
2001 | return (HAVE_IN_PLACE_ADDENDS |
2002 | && (reloc == BFD_RELOC_HI16_S | |
0a44bf69 RS |
2003 | || reloc == BFD_RELOC_MIPS16_HI16_S |
2004 | /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo(); | |
2005 | all GOT16 relocations evaluate to "G". */ | |
2006 | || (reloc == BFD_RELOC_MIPS_GOT16 && mips_pic != VXWORKS_PIC))); | |
5919d012 RS |
2007 | } |
2008 | ||
2009 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
2010 | relocation. */ | |
2011 | ||
2012 | static inline bfd_boolean | |
17a2f251 | 2013 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
2014 | { |
2015 | return (fixp->fx_next != NULL | |
d6f16593 MR |
2016 | && (fixp->fx_next->fx_r_type == BFD_RELOC_LO16 |
2017 | || fixp->fx_next->fx_r_type == BFD_RELOC_MIPS16_LO16) | |
5919d012 RS |
2018 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
2019 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
2020 | } | |
2021 | ||
252b5132 RH |
2022 | /* See whether instruction IP reads register REG. CLASS is the type |
2023 | of register. */ | |
2024 | ||
2025 | static int | |
71400594 | 2026 | insn_uses_reg (const struct mips_cl_insn *ip, unsigned int reg, |
17a2f251 | 2027 | enum mips_regclass class) |
252b5132 RH |
2028 | { |
2029 | if (class == MIPS16_REG) | |
2030 | { | |
2031 | assert (mips_opts.mips16); | |
2032 | reg = mips16_to_32_reg_map[reg]; | |
2033 | class = MIPS_GR_REG; | |
2034 | } | |
2035 | ||
85b51719 TS |
2036 | /* Don't report on general register ZERO, since it never changes. */ |
2037 | if (class == MIPS_GR_REG && reg == ZERO) | |
252b5132 RH |
2038 | return 0; |
2039 | ||
2040 | if (class == MIPS_FP_REG) | |
2041 | { | |
2042 | assert (! mips_opts.mips16); | |
2043 | /* If we are called with either $f0 or $f1, we must check $f0. | |
2044 | This is not optimal, because it will introduce an unnecessary | |
2045 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
2046 | need to distinguish reading both $f0 and $f1 or just one of | |
2047 | them. Note that we don't have to check the other way, | |
2048 | because there is no instruction that sets both $f0 and $f1 | |
2049 | and requires a delay. */ | |
2050 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
bf12938e | 2051 | && ((EXTRACT_OPERAND (FS, *ip) & ~(unsigned) 1) |
252b5132 RH |
2052 | == (reg &~ (unsigned) 1))) |
2053 | return 1; | |
2054 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
bf12938e | 2055 | && ((EXTRACT_OPERAND (FT, *ip) & ~(unsigned) 1) |
252b5132 RH |
2056 | == (reg &~ (unsigned) 1))) |
2057 | return 1; | |
2058 | } | |
2059 | else if (! mips_opts.mips16) | |
2060 | { | |
2061 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
bf12938e | 2062 | && EXTRACT_OPERAND (RS, *ip) == reg) |
252b5132 RH |
2063 | return 1; |
2064 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
bf12938e | 2065 | && EXTRACT_OPERAND (RT, *ip) == reg) |
252b5132 RH |
2066 | return 1; |
2067 | } | |
2068 | else | |
2069 | { | |
2070 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
bf12938e | 2071 | && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)] == reg) |
252b5132 RH |
2072 | return 1; |
2073 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
bf12938e | 2074 | && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)] == reg) |
252b5132 RH |
2075 | return 1; |
2076 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
bf12938e | 2077 | && (mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)] |
252b5132 RH |
2078 | == reg)) |
2079 | return 1; | |
2080 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
2081 | return 1; | |
2082 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
2083 | return 1; | |
2084 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
2085 | return 1; | |
2086 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
bf12938e | 2087 | && MIPS16_EXTRACT_OPERAND (REGR32, *ip) == reg) |
252b5132 RH |
2088 | return 1; |
2089 | } | |
2090 | ||
2091 | return 0; | |
2092 | } | |
2093 | ||
2094 | /* This function returns true if modifying a register requires a | |
2095 | delay. */ | |
2096 | ||
2097 | static int | |
17a2f251 | 2098 | reg_needs_delay (unsigned int reg) |
252b5132 RH |
2099 | { |
2100 | unsigned long prev_pinfo; | |
2101 | ||
47e39b9d | 2102 | prev_pinfo = history[0].insn_mo->pinfo; |
252b5132 | 2103 | if (! mips_opts.noreorder |
81912461 ILT |
2104 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
2105 | && ! gpr_interlocks) | |
2106 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
2107 | && ! cop_interlocks))) | |
252b5132 | 2108 | { |
81912461 ILT |
2109 | /* A load from a coprocessor or from memory. All load delays |
2110 | delay the use of general register rt for one instruction. */ | |
bdaaa2e1 | 2111 | /* Itbl support may require additional care here. */ |
252b5132 | 2112 | know (prev_pinfo & INSN_WRITE_GPR_T); |
bf12938e | 2113 | if (reg == EXTRACT_OPERAND (RT, history[0])) |
252b5132 RH |
2114 | return 1; |
2115 | } | |
2116 | ||
2117 | return 0; | |
2118 | } | |
2119 | ||
404a8071 RS |
2120 | /* Move all labels in insn_labels to the current insertion point. */ |
2121 | ||
2122 | static void | |
2123 | mips_move_labels (void) | |
2124 | { | |
a8dbcb85 | 2125 | segment_info_type *si = seg_info (now_seg); |
404a8071 RS |
2126 | struct insn_label_list *l; |
2127 | valueT val; | |
2128 | ||
a8dbcb85 | 2129 | for (l = si->label_list; l != NULL; l = l->next) |
404a8071 RS |
2130 | { |
2131 | assert (S_GET_SEGMENT (l->label) == now_seg); | |
2132 | symbol_set_frag (l->label, frag_now); | |
2133 | val = (valueT) frag_now_fix (); | |
2134 | /* mips16 text labels are stored as odd. */ | |
2135 | if (mips_opts.mips16) | |
2136 | ++val; | |
2137 | S_SET_VALUE (l->label, val); | |
2138 | } | |
2139 | } | |
2140 | ||
5f0fe04b TS |
2141 | static bfd_boolean |
2142 | s_is_linkonce (symbolS *sym, segT from_seg) | |
2143 | { | |
2144 | bfd_boolean linkonce = FALSE; | |
2145 | segT symseg = S_GET_SEGMENT (sym); | |
2146 | ||
2147 | if (symseg != from_seg && !S_IS_LOCAL (sym)) | |
2148 | { | |
2149 | if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE)) | |
2150 | linkonce = TRUE; | |
2151 | #ifdef OBJ_ELF | |
2152 | /* The GNU toolchain uses an extension for ELF: a section | |
2153 | beginning with the magic string .gnu.linkonce is a | |
2154 | linkonce section. */ | |
2155 | if (strncmp (segment_name (symseg), ".gnu.linkonce", | |
2156 | sizeof ".gnu.linkonce" - 1) == 0) | |
2157 | linkonce = TRUE; | |
2158 | #endif | |
2159 | } | |
2160 | return linkonce; | |
2161 | } | |
2162 | ||
252b5132 RH |
2163 | /* Mark instruction labels in mips16 mode. This permits the linker to |
2164 | handle them specially, such as generating jalx instructions when | |
2165 | needed. We also make them odd for the duration of the assembly, in | |
2166 | order to generate the right sort of code. We will make them even | |
2167 | in the adjust_symtab routine, while leaving them marked. This is | |
2168 | convenient for the debugger and the disassembler. The linker knows | |
2169 | to make them odd again. */ | |
2170 | ||
2171 | static void | |
17a2f251 | 2172 | mips16_mark_labels (void) |
252b5132 | 2173 | { |
a8dbcb85 TS |
2174 | segment_info_type *si = seg_info (now_seg); |
2175 | struct insn_label_list *l; | |
252b5132 | 2176 | |
a8dbcb85 TS |
2177 | if (!mips_opts.mips16) |
2178 | return; | |
2179 | ||
2180 | for (l = si->label_list; l != NULL; l = l->next) | |
2181 | { | |
2182 | symbolS *label = l->label; | |
2183 | ||
2184 | #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF) | |
f43abd2b | 2185 | if (IS_ELF) |
a8dbcb85 | 2186 | S_SET_OTHER (label, STO_MIPS16); |
252b5132 | 2187 | #endif |
5f0fe04b TS |
2188 | if ((S_GET_VALUE (label) & 1) == 0 |
2189 | /* Don't adjust the address if the label is global or weak, or | |
2190 | in a link-once section, since we'll be emitting symbol reloc | |
2191 | references to it which will be patched up by the linker, and | |
2192 | the final value of the symbol may or may not be MIPS16. */ | |
2193 | && ! S_IS_WEAK (label) | |
2194 | && ! S_IS_EXTERNAL (label) | |
2195 | && ! s_is_linkonce (label, now_seg)) | |
a8dbcb85 | 2196 | S_SET_VALUE (label, S_GET_VALUE (label) | 1); |
252b5132 RH |
2197 | } |
2198 | } | |
2199 | ||
4d7206a2 RS |
2200 | /* End the current frag. Make it a variant frag and record the |
2201 | relaxation info. */ | |
2202 | ||
2203 | static void | |
2204 | relax_close_frag (void) | |
2205 | { | |
584892a6 | 2206 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 2207 | frag_var (rs_machine_dependent, 0, 0, |
584892a6 | 2208 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), |
4d7206a2 RS |
2209 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
2210 | ||
2211 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
2212 | mips_relax.first_fixup = 0; | |
2213 | } | |
2214 | ||
2215 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
2216 | See the comment above RELAX_ENCODE for more details. */ | |
2217 | ||
2218 | static void | |
2219 | relax_start (symbolS *symbol) | |
2220 | { | |
2221 | assert (mips_relax.sequence == 0); | |
2222 | mips_relax.sequence = 1; | |
2223 | mips_relax.symbol = symbol; | |
2224 | } | |
2225 | ||
2226 | /* Start generating the second version of a relaxable sequence. | |
2227 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
2228 | |
2229 | static void | |
4d7206a2 RS |
2230 | relax_switch (void) |
2231 | { | |
2232 | assert (mips_relax.sequence == 1); | |
2233 | mips_relax.sequence = 2; | |
2234 | } | |
2235 | ||
2236 | /* End the current relaxable sequence. */ | |
2237 | ||
2238 | static void | |
2239 | relax_end (void) | |
2240 | { | |
2241 | assert (mips_relax.sequence == 2); | |
2242 | relax_close_frag (); | |
2243 | mips_relax.sequence = 0; | |
2244 | } | |
2245 | ||
71400594 RS |
2246 | /* Classify an instruction according to the FIX_VR4120_* enumeration. |
2247 | Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected | |
2248 | by VR4120 errata. */ | |
4d7206a2 | 2249 | |
71400594 RS |
2250 | static unsigned int |
2251 | classify_vr4120_insn (const char *name) | |
252b5132 | 2252 | { |
71400594 RS |
2253 | if (strncmp (name, "macc", 4) == 0) |
2254 | return FIX_VR4120_MACC; | |
2255 | if (strncmp (name, "dmacc", 5) == 0) | |
2256 | return FIX_VR4120_DMACC; | |
2257 | if (strncmp (name, "mult", 4) == 0) | |
2258 | return FIX_VR4120_MULT; | |
2259 | if (strncmp (name, "dmult", 5) == 0) | |
2260 | return FIX_VR4120_DMULT; | |
2261 | if (strstr (name, "div")) | |
2262 | return FIX_VR4120_DIV; | |
2263 | if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) | |
2264 | return FIX_VR4120_MTHILO; | |
2265 | return NUM_FIX_VR4120_CLASSES; | |
2266 | } | |
252b5132 | 2267 | |
71400594 RS |
2268 | /* Return the number of instructions that must separate INSN1 and INSN2, |
2269 | where INSN1 is the earlier instruction. Return the worst-case value | |
2270 | for any INSN2 if INSN2 is null. */ | |
252b5132 | 2271 | |
71400594 RS |
2272 | static unsigned int |
2273 | insns_between (const struct mips_cl_insn *insn1, | |
2274 | const struct mips_cl_insn *insn2) | |
2275 | { | |
2276 | unsigned long pinfo1, pinfo2; | |
2277 | ||
2278 | /* This function needs to know which pinfo flags are set for INSN2 | |
2279 | and which registers INSN2 uses. The former is stored in PINFO2 and | |
2280 | the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2 | |
2281 | will have every flag set and INSN2_USES_REG will always return true. */ | |
2282 | pinfo1 = insn1->insn_mo->pinfo; | |
2283 | pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; | |
252b5132 | 2284 | |
71400594 RS |
2285 | #define INSN2_USES_REG(REG, CLASS) \ |
2286 | (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS)) | |
2287 | ||
2288 | /* For most targets, write-after-read dependencies on the HI and LO | |
2289 | registers must be separated by at least two instructions. */ | |
2290 | if (!hilo_interlocks) | |
252b5132 | 2291 | { |
71400594 RS |
2292 | if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) |
2293 | return 2; | |
2294 | if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) | |
2295 | return 2; | |
2296 | } | |
2297 | ||
2298 | /* If we're working around r7000 errata, there must be two instructions | |
2299 | between an mfhi or mflo and any instruction that uses the result. */ | |
2300 | if (mips_7000_hilo_fix | |
2301 | && MF_HILO_INSN (pinfo1) | |
2302 | && INSN2_USES_REG (EXTRACT_OPERAND (RD, *insn1), MIPS_GR_REG)) | |
2303 | return 2; | |
2304 | ||
2305 | /* If working around VR4120 errata, check for combinations that need | |
2306 | a single intervening instruction. */ | |
2307 | if (mips_fix_vr4120) | |
2308 | { | |
2309 | unsigned int class1, class2; | |
252b5132 | 2310 | |
71400594 RS |
2311 | class1 = classify_vr4120_insn (insn1->insn_mo->name); |
2312 | if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) | |
252b5132 | 2313 | { |
71400594 RS |
2314 | if (insn2 == NULL) |
2315 | return 1; | |
2316 | class2 = classify_vr4120_insn (insn2->insn_mo->name); | |
2317 | if (vr4120_conflicts[class1] & (1 << class2)) | |
2318 | return 1; | |
252b5132 | 2319 | } |
71400594 RS |
2320 | } |
2321 | ||
2322 | if (!mips_opts.mips16) | |
2323 | { | |
2324 | /* Check for GPR or coprocessor load delays. All such delays | |
2325 | are on the RT register. */ | |
2326 | /* Itbl support may require additional care here. */ | |
2327 | if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY)) | |
2328 | || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY))) | |
252b5132 | 2329 | { |
71400594 RS |
2330 | know (pinfo1 & INSN_WRITE_GPR_T); |
2331 | if (INSN2_USES_REG (EXTRACT_OPERAND (RT, *insn1), MIPS_GR_REG)) | |
2332 | return 1; | |
2333 | } | |
2334 | ||
2335 | /* Check for generic coprocessor hazards. | |
2336 | ||
2337 | This case is not handled very well. There is no special | |
2338 | knowledge of CP0 handling, and the coprocessors other than | |
2339 | the floating point unit are not distinguished at all. */ | |
2340 | /* Itbl support may require additional care here. FIXME! | |
2341 | Need to modify this to include knowledge about | |
2342 | user specified delays! */ | |
2343 | else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY)) | |
2344 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) | |
2345 | { | |
2346 | /* Handle cases where INSN1 writes to a known general coprocessor | |
2347 | register. There must be a one instruction delay before INSN2 | |
2348 | if INSN2 reads that register, otherwise no delay is needed. */ | |
2349 | if (pinfo1 & INSN_WRITE_FPR_T) | |
252b5132 | 2350 | { |
71400594 RS |
2351 | if (INSN2_USES_REG (EXTRACT_OPERAND (FT, *insn1), MIPS_FP_REG)) |
2352 | return 1; | |
252b5132 | 2353 | } |
71400594 | 2354 | else if (pinfo1 & INSN_WRITE_FPR_S) |
252b5132 | 2355 | { |
71400594 RS |
2356 | if (INSN2_USES_REG (EXTRACT_OPERAND (FS, *insn1), MIPS_FP_REG)) |
2357 | return 1; | |
252b5132 RH |
2358 | } |
2359 | else | |
2360 | { | |
71400594 RS |
2361 | /* Read-after-write dependencies on the control registers |
2362 | require a two-instruction gap. */ | |
2363 | if ((pinfo1 & INSN_WRITE_COND_CODE) | |
2364 | && (pinfo2 & INSN_READ_COND_CODE)) | |
2365 | return 2; | |
2366 | ||
2367 | /* We don't know exactly what INSN1 does. If INSN2 is | |
2368 | also a coprocessor instruction, assume there must be | |
2369 | a one instruction gap. */ | |
2370 | if (pinfo2 & INSN_COP) | |
2371 | return 1; | |
252b5132 RH |
2372 | } |
2373 | } | |
6b76fefe | 2374 | |
71400594 RS |
2375 | /* Check for read-after-write dependencies on the coprocessor |
2376 | control registers in cases where INSN1 does not need a general | |
2377 | coprocessor delay. This means that INSN1 is a floating point | |
2378 | comparison instruction. */ | |
2379 | /* Itbl support may require additional care here. */ | |
2380 | else if (!cop_interlocks | |
2381 | && (pinfo1 & INSN_WRITE_COND_CODE) | |
2382 | && (pinfo2 & INSN_READ_COND_CODE)) | |
2383 | return 1; | |
2384 | } | |
6b76fefe | 2385 | |
71400594 | 2386 | #undef INSN2_USES_REG |
6b76fefe | 2387 | |
71400594 RS |
2388 | return 0; |
2389 | } | |
6b76fefe | 2390 | |
7d8e00cf RS |
2391 | /* Return the number of nops that would be needed to work around the |
2392 | VR4130 mflo/mfhi errata if instruction INSN immediately followed | |
2393 | the MAX_VR4130_NOPS instructions described by HISTORY. */ | |
2394 | ||
2395 | static int | |
2396 | nops_for_vr4130 (const struct mips_cl_insn *history, | |
2397 | const struct mips_cl_insn *insn) | |
2398 | { | |
2399 | int i, j, reg; | |
2400 | ||
2401 | /* Check if the instruction writes to HI or LO. MTHI and MTLO | |
2402 | are not affected by the errata. */ | |
2403 | if (insn != 0 | |
2404 | && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 | |
2405 | || strcmp (insn->insn_mo->name, "mtlo") == 0 | |
2406 | || strcmp (insn->insn_mo->name, "mthi") == 0)) | |
2407 | return 0; | |
2408 | ||
2409 | /* Search for the first MFLO or MFHI. */ | |
2410 | for (i = 0; i < MAX_VR4130_NOPS; i++) | |
2411 | if (!history[i].noreorder_p && MF_HILO_INSN (history[i].insn_mo->pinfo)) | |
2412 | { | |
2413 | /* Extract the destination register. */ | |
2414 | if (mips_opts.mips16) | |
2415 | reg = mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, history[i])]; | |
2416 | else | |
2417 | reg = EXTRACT_OPERAND (RD, history[i]); | |
2418 | ||
2419 | /* No nops are needed if INSN reads that register. */ | |
2420 | if (insn != NULL && insn_uses_reg (insn, reg, MIPS_GR_REG)) | |
2421 | return 0; | |
2422 | ||
2423 | /* ...or if any of the intervening instructions do. */ | |
2424 | for (j = 0; j < i; j++) | |
2425 | if (insn_uses_reg (&history[j], reg, MIPS_GR_REG)) | |
2426 | return 0; | |
2427 | ||
2428 | return MAX_VR4130_NOPS - i; | |
2429 | } | |
2430 | return 0; | |
2431 | } | |
2432 | ||
71400594 RS |
2433 | /* Return the number of nops that would be needed if instruction INSN |
2434 | immediately followed the MAX_NOPS instructions given by HISTORY, | |
2435 | where HISTORY[0] is the most recent instruction. If INSN is null, | |
2436 | return the worse-case number of nops for any instruction. */ | |
bdaaa2e1 | 2437 | |
71400594 RS |
2438 | static int |
2439 | nops_for_insn (const struct mips_cl_insn *history, | |
2440 | const struct mips_cl_insn *insn) | |
2441 | { | |
2442 | int i, nops, tmp_nops; | |
bdaaa2e1 | 2443 | |
71400594 | 2444 | nops = 0; |
7d8e00cf | 2445 | for (i = 0; i < MAX_DELAY_NOPS; i++) |
71400594 RS |
2446 | if (!history[i].noreorder_p) |
2447 | { | |
2448 | tmp_nops = insns_between (history + i, insn) - i; | |
2449 | if (tmp_nops > nops) | |
2450 | nops = tmp_nops; | |
2451 | } | |
7d8e00cf RS |
2452 | |
2453 | if (mips_fix_vr4130) | |
2454 | { | |
2455 | tmp_nops = nops_for_vr4130 (history, insn); | |
2456 | if (tmp_nops > nops) | |
2457 | nops = tmp_nops; | |
2458 | } | |
2459 | ||
71400594 RS |
2460 | return nops; |
2461 | } | |
252b5132 | 2462 | |
71400594 RS |
2463 | /* The variable arguments provide NUM_INSNS extra instructions that |
2464 | might be added to HISTORY. Return the largest number of nops that | |
2465 | would be needed after the extended sequence. */ | |
252b5132 | 2466 | |
71400594 RS |
2467 | static int |
2468 | nops_for_sequence (int num_insns, const struct mips_cl_insn *history, ...) | |
2469 | { | |
2470 | va_list args; | |
2471 | struct mips_cl_insn buffer[MAX_NOPS]; | |
2472 | struct mips_cl_insn *cursor; | |
2473 | int nops; | |
2474 | ||
2475 | va_start (args, history); | |
2476 | cursor = buffer + num_insns; | |
2477 | memcpy (cursor, history, (MAX_NOPS - num_insns) * sizeof (*cursor)); | |
2478 | while (cursor > buffer) | |
2479 | *--cursor = *va_arg (args, const struct mips_cl_insn *); | |
2480 | ||
2481 | nops = nops_for_insn (buffer, NULL); | |
2482 | va_end (args); | |
2483 | return nops; | |
2484 | } | |
252b5132 | 2485 | |
71400594 RS |
2486 | /* Like nops_for_insn, but if INSN is a branch, take into account the |
2487 | worst-case delay for the branch target. */ | |
252b5132 | 2488 | |
71400594 RS |
2489 | static int |
2490 | nops_for_insn_or_target (const struct mips_cl_insn *history, | |
2491 | const struct mips_cl_insn *insn) | |
2492 | { | |
2493 | int nops, tmp_nops; | |
60b63b72 | 2494 | |
71400594 RS |
2495 | nops = nops_for_insn (history, insn); |
2496 | if (insn->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY | |
2497 | | INSN_COND_BRANCH_DELAY | |
2498 | | INSN_COND_BRANCH_LIKELY)) | |
2499 | { | |
2500 | tmp_nops = nops_for_sequence (2, history, insn, NOP_INSN); | |
2501 | if (tmp_nops > nops) | |
2502 | nops = tmp_nops; | |
2503 | } | |
2504 | else if (mips_opts.mips16 && (insn->insn_mo->pinfo & MIPS16_INSN_BRANCH)) | |
2505 | { | |
2506 | tmp_nops = nops_for_sequence (1, history, insn); | |
2507 | if (tmp_nops > nops) | |
2508 | nops = tmp_nops; | |
2509 | } | |
2510 | return nops; | |
2511 | } | |
2512 | ||
2513 | /* Output an instruction. IP is the instruction information. | |
2514 | ADDRESS_EXPR is an operand of the instruction to be used with | |
2515 | RELOC_TYPE. */ | |
2516 | ||
2517 | static void | |
2518 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
2519 | bfd_reloc_code_real_type *reloc_type) | |
2520 | { | |
3994f87e | 2521 | unsigned long prev_pinfo, pinfo; |
71400594 RS |
2522 | relax_stateT prev_insn_frag_type = 0; |
2523 | bfd_boolean relaxed_branch = FALSE; | |
a8dbcb85 | 2524 | segment_info_type *si = seg_info (now_seg); |
71400594 RS |
2525 | |
2526 | /* Mark instruction labels in mips16 mode. */ | |
2527 | mips16_mark_labels (); | |
2528 | ||
2529 | prev_pinfo = history[0].insn_mo->pinfo; | |
2530 | pinfo = ip->insn_mo->pinfo; | |
2531 | ||
2532 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) | |
2533 | { | |
2534 | /* There are a lot of optimizations we could do that we don't. | |
2535 | In particular, we do not, in general, reorder instructions. | |
2536 | If you use gcc with optimization, it will reorder | |
2537 | instructions and generally do much more optimization then we | |
2538 | do here; repeating all that work in the assembler would only | |
2539 | benefit hand written assembly code, and does not seem worth | |
2540 | it. */ | |
2541 | int nops = (mips_optimize == 0 | |
2542 | ? nops_for_insn (history, NULL) | |
2543 | : nops_for_insn_or_target (history, ip)); | |
2544 | if (nops > 0) | |
252b5132 RH |
2545 | { |
2546 | fragS *old_frag; | |
2547 | unsigned long old_frag_offset; | |
2548 | int i; | |
252b5132 RH |
2549 | |
2550 | old_frag = frag_now; | |
2551 | old_frag_offset = frag_now_fix (); | |
2552 | ||
2553 | for (i = 0; i < nops; i++) | |
2554 | emit_nop (); | |
2555 | ||
2556 | if (listing) | |
2557 | { | |
2558 | listing_prev_line (); | |
2559 | /* We may be at the start of a variant frag. In case we | |
2560 | are, make sure there is enough space for the frag | |
2561 | after the frags created by listing_prev_line. The | |
2562 | argument to frag_grow here must be at least as large | |
2563 | as the argument to all other calls to frag_grow in | |
2564 | this file. We don't have to worry about being in the | |
2565 | middle of a variant frag, because the variants insert | |
2566 | all needed nop instructions themselves. */ | |
2567 | frag_grow (40); | |
2568 | } | |
2569 | ||
404a8071 | 2570 | mips_move_labels (); |
252b5132 RH |
2571 | |
2572 | #ifndef NO_ECOFF_DEBUGGING | |
2573 | if (ECOFF_DEBUGGING) | |
2574 | ecoff_fix_loc (old_frag, old_frag_offset); | |
2575 | #endif | |
2576 | } | |
71400594 RS |
2577 | } |
2578 | else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) | |
2579 | { | |
2580 | /* Work out how many nops in prev_nop_frag are needed by IP. */ | |
2581 | int nops = nops_for_insn_or_target (history, ip); | |
2582 | assert (nops <= prev_nop_frag_holds); | |
252b5132 | 2583 | |
71400594 RS |
2584 | /* Enforce NOPS as a minimum. */ |
2585 | if (nops > prev_nop_frag_required) | |
2586 | prev_nop_frag_required = nops; | |
252b5132 | 2587 | |
71400594 RS |
2588 | if (prev_nop_frag_holds == prev_nop_frag_required) |
2589 | { | |
2590 | /* Settle for the current number of nops. Update the history | |
2591 | accordingly (for the benefit of any future .set reorder code). */ | |
2592 | prev_nop_frag = NULL; | |
2593 | insert_into_history (prev_nop_frag_since, | |
2594 | prev_nop_frag_holds, NOP_INSN); | |
2595 | } | |
2596 | else | |
2597 | { | |
2598 | /* Allow this instruction to replace one of the nops that was | |
2599 | tentatively added to prev_nop_frag. */ | |
2600 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
2601 | prev_nop_frag_holds--; | |
2602 | prev_nop_frag_since++; | |
252b5132 RH |
2603 | } |
2604 | } | |
2605 | ||
58e2ea4d MR |
2606 | #ifdef OBJ_ELF |
2607 | /* The value passed to dwarf2_emit_insn is the distance between | |
2608 | the beginning of the current instruction and the address that | |
2609 | should be recorded in the debug tables. For MIPS16 debug info | |
2610 | we want to use ISA-encoded addresses, so we pass -1 for an | |
2611 | address higher by one than the current. */ | |
2612 | dwarf2_emit_insn (mips_opts.mips16 ? -1 : 0); | |
2613 | #endif | |
2614 | ||
895921c9 | 2615 | /* Record the frag type before frag_var. */ |
47e39b9d RS |
2616 | if (history[0].frag) |
2617 | prev_insn_frag_type = history[0].frag->fr_type; | |
895921c9 | 2618 | |
4d7206a2 | 2619 | if (address_expr |
0b25d3e6 | 2620 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
4a6a3df4 AO |
2621 | && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY |
2622 | || pinfo & INSN_COND_BRANCH_LIKELY) | |
2623 | && mips_relax_branch | |
2624 | /* Don't try branch relaxation within .set nomacro, or within | |
2625 | .set noat if we use $at for PIC computations. If it turns | |
2626 | out that the branch was out-of-range, we'll get an error. */ | |
2627 | && !mips_opts.warn_about_macros | |
2628 | && !(mips_opts.noat && mips_pic != NO_PIC) | |
2629 | && !mips_opts.mips16) | |
2630 | { | |
895921c9 | 2631 | relaxed_branch = TRUE; |
1e915849 RS |
2632 | add_relaxed_insn (ip, (relaxed_branch_length |
2633 | (NULL, NULL, | |
2634 | (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1 | |
2635 | : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 | |
2636 | : 0)), 4, | |
2637 | RELAX_BRANCH_ENCODE | |
2638 | (pinfo & INSN_UNCOND_BRANCH_DELAY, | |
2639 | pinfo & INSN_COND_BRANCH_LIKELY, | |
2640 | pinfo & INSN_WRITE_GPR_31, | |
2641 | 0), | |
2642 | address_expr->X_add_symbol, | |
2643 | address_expr->X_add_number); | |
4a6a3df4 AO |
2644 | *reloc_type = BFD_RELOC_UNUSED; |
2645 | } | |
2646 | else if (*reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
2647 | { |
2648 | /* We need to set up a variant frag. */ | |
2649 | assert (mips_opts.mips16 && address_expr != NULL); | |
1e915849 RS |
2650 | add_relaxed_insn (ip, 4, 0, |
2651 | RELAX_MIPS16_ENCODE | |
2652 | (*reloc_type - BFD_RELOC_UNUSED, | |
2653 | mips16_small, mips16_ext, | |
2654 | prev_pinfo & INSN_UNCOND_BRANCH_DELAY, | |
2655 | history[0].mips16_absolute_jump_p), | |
2656 | make_expr_symbol (address_expr), 0); | |
252b5132 | 2657 | } |
252b5132 RH |
2658 | else if (mips_opts.mips16 |
2659 | && ! ip->use_extend | |
f6688943 | 2660 | && *reloc_type != BFD_RELOC_MIPS16_JMP) |
9497f5ac | 2661 | { |
b8ee1a6e DU |
2662 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) == 0) |
2663 | /* Make sure there is enough room to swap this instruction with | |
2664 | a following jump instruction. */ | |
2665 | frag_grow (6); | |
1e915849 | 2666 | add_fixed_insn (ip); |
252b5132 RH |
2667 | } |
2668 | else | |
2669 | { | |
2670 | if (mips_opts.mips16 | |
2671 | && mips_opts.noreorder | |
2672 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
2673 | as_warn (_("extended instruction in delay slot")); | |
2674 | ||
4d7206a2 RS |
2675 | if (mips_relax.sequence) |
2676 | { | |
2677 | /* If we've reached the end of this frag, turn it into a variant | |
2678 | frag and record the information for the instructions we've | |
2679 | written so far. */ | |
2680 | if (frag_room () < 4) | |
2681 | relax_close_frag (); | |
2682 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
2683 | } | |
2684 | ||
584892a6 RS |
2685 | if (mips_relax.sequence != 2) |
2686 | mips_macro_warning.sizes[0] += 4; | |
2687 | if (mips_relax.sequence != 1) | |
2688 | mips_macro_warning.sizes[1] += 4; | |
2689 | ||
1e915849 RS |
2690 | if (mips_opts.mips16) |
2691 | { | |
2692 | ip->fixed_p = 1; | |
2693 | ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); | |
2694 | } | |
2695 | add_fixed_insn (ip); | |
252b5132 RH |
2696 | } |
2697 | ||
01a3f561 | 2698 | if (address_expr != NULL && *reloc_type <= BFD_RELOC_UNUSED) |
252b5132 RH |
2699 | { |
2700 | if (address_expr->X_op == O_constant) | |
2701 | { | |
f17c130b | 2702 | unsigned int tmp; |
f6688943 TS |
2703 | |
2704 | switch (*reloc_type) | |
252b5132 RH |
2705 | { |
2706 | case BFD_RELOC_32: | |
2707 | ip->insn_opcode |= address_expr->X_add_number; | |
2708 | break; | |
2709 | ||
f6688943 | 2710 | case BFD_RELOC_MIPS_HIGHEST: |
f17c130b AM |
2711 | tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48; |
2712 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2713 | break; |
2714 | ||
2715 | case BFD_RELOC_MIPS_HIGHER: | |
f17c130b AM |
2716 | tmp = (address_expr->X_add_number + 0x80008000ull) >> 32; |
2717 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2718 | break; |
2719 | ||
2720 | case BFD_RELOC_HI16_S: | |
f17c130b AM |
2721 | tmp = (address_expr->X_add_number + 0x8000) >> 16; |
2722 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2723 | break; |
2724 | ||
2725 | case BFD_RELOC_HI16: | |
2726 | ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; | |
2727 | break; | |
2728 | ||
01a3f561 | 2729 | case BFD_RELOC_UNUSED: |
252b5132 | 2730 | case BFD_RELOC_LO16: |
ed6fb7bd | 2731 | case BFD_RELOC_MIPS_GOT_DISP: |
252b5132 RH |
2732 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
2733 | break; | |
2734 | ||
2735 | case BFD_RELOC_MIPS_JMP: | |
2736 | if ((address_expr->X_add_number & 3) != 0) | |
2737 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2738 | (unsigned long) address_expr->X_add_number); | |
2739 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; | |
2740 | break; | |
2741 | ||
2742 | case BFD_RELOC_MIPS16_JMP: | |
2743 | if ((address_expr->X_add_number & 3) != 0) | |
2744 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2745 | (unsigned long) address_expr->X_add_number); | |
2746 | ip->insn_opcode |= | |
2747 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
2748 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
2749 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
2750 | break; | |
2751 | ||
252b5132 | 2752 | case BFD_RELOC_16_PCREL_S2: |
bad36eac DJ |
2753 | if ((address_expr->X_add_number & 3) != 0) |
2754 | as_bad (_("branch to misaligned address (0x%lx)"), | |
2755 | (unsigned long) address_expr->X_add_number); | |
2756 | if (mips_relax_branch) | |
2757 | goto need_reloc; | |
2758 | if ((address_expr->X_add_number + 0x20000) & ~0x3ffff) | |
2759 | as_bad (_("branch address range overflow (0x%lx)"), | |
2760 | (unsigned long) address_expr->X_add_number); | |
2761 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0xffff; | |
2762 | break; | |
252b5132 RH |
2763 | |
2764 | default: | |
2765 | internalError (); | |
2766 | } | |
2767 | } | |
01a3f561 | 2768 | else if (*reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 2769 | need_reloc: |
4d7206a2 RS |
2770 | { |
2771 | reloc_howto_type *howto; | |
2772 | int i; | |
34ce925e | 2773 | |
4d7206a2 RS |
2774 | /* In a compound relocation, it is the final (outermost) |
2775 | operator that determines the relocated field. */ | |
2776 | for (i = 1; i < 3; i++) | |
2777 | if (reloc_type[i] == BFD_RELOC_UNUSED) | |
2778 | break; | |
34ce925e | 2779 | |
4d7206a2 | 2780 | howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]); |
1e915849 RS |
2781 | ip->fixp[0] = fix_new_exp (ip->frag, ip->where, |
2782 | bfd_get_reloc_size (howto), | |
2783 | address_expr, | |
2784 | reloc_type[0] == BFD_RELOC_16_PCREL_S2, | |
2785 | reloc_type[0]); | |
4d7206a2 RS |
2786 | |
2787 | /* These relocations can have an addend that won't fit in | |
2788 | 4 octets for 64bit assembly. */ | |
2789 | if (HAVE_64BIT_GPRS | |
2790 | && ! howto->partial_inplace | |
2791 | && (reloc_type[0] == BFD_RELOC_16 | |
2792 | || reloc_type[0] == BFD_RELOC_32 | |
2793 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
2794 | || reloc_type[0] == BFD_RELOC_HI16_S | |
2795 | || reloc_type[0] == BFD_RELOC_LO16 | |
2796 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
2797 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
2798 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
2799 | || reloc_type[0] == BFD_RELOC_64 | |
2800 | || reloc_type[0] == BFD_RELOC_CTOR | |
2801 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
2802 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
2803 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
2804 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
2805 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
d6f16593 MR |
2806 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT |
2807 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
2808 | || reloc_type[0] == BFD_RELOC_MIPS16_HI16_S | |
2809 | || reloc_type[0] == BFD_RELOC_MIPS16_LO16)) | |
1e915849 | 2810 | ip->fixp[0]->fx_no_overflow = 1; |
4d7206a2 RS |
2811 | |
2812 | if (mips_relax.sequence) | |
2813 | { | |
2814 | if (mips_relax.first_fixup == 0) | |
1e915849 | 2815 | mips_relax.first_fixup = ip->fixp[0]; |
4d7206a2 RS |
2816 | } |
2817 | else if (reloc_needs_lo_p (*reloc_type)) | |
2818 | { | |
2819 | struct mips_hi_fixup *hi_fixup; | |
252b5132 | 2820 | |
4d7206a2 RS |
2821 | /* Reuse the last entry if it already has a matching %lo. */ |
2822 | hi_fixup = mips_hi_fixup_list; | |
2823 | if (hi_fixup == 0 | |
2824 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
2825 | { | |
2826 | hi_fixup = ((struct mips_hi_fixup *) | |
2827 | xmalloc (sizeof (struct mips_hi_fixup))); | |
2828 | hi_fixup->next = mips_hi_fixup_list; | |
2829 | mips_hi_fixup_list = hi_fixup; | |
252b5132 | 2830 | } |
1e915849 | 2831 | hi_fixup->fixp = ip->fixp[0]; |
4d7206a2 RS |
2832 | hi_fixup->seg = now_seg; |
2833 | } | |
f6688943 | 2834 | |
4d7206a2 RS |
2835 | /* Add fixups for the second and third relocations, if given. |
2836 | Note that the ABI allows the second relocation to be | |
2837 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
2838 | moment we only use RSS_UNDEF, but we could add support | |
2839 | for the others if it ever becomes necessary. */ | |
2840 | for (i = 1; i < 3; i++) | |
2841 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
2842 | { | |
1e915849 RS |
2843 | ip->fixp[i] = fix_new (ip->frag, ip->where, |
2844 | ip->fixp[0]->fx_size, NULL, 0, | |
2845 | FALSE, reloc_type[i]); | |
b1dca8ee RS |
2846 | |
2847 | /* Use fx_tcbit to mark compound relocs. */ | |
1e915849 RS |
2848 | ip->fixp[0]->fx_tcbit = 1; |
2849 | ip->fixp[i]->fx_tcbit = 1; | |
4d7206a2 | 2850 | } |
252b5132 RH |
2851 | } |
2852 | } | |
1e915849 | 2853 | install_insn (ip); |
252b5132 RH |
2854 | |
2855 | /* Update the register mask information. */ | |
2856 | if (! mips_opts.mips16) | |
2857 | { | |
2858 | if (pinfo & INSN_WRITE_GPR_D) | |
bf12938e | 2859 | mips_gprmask |= 1 << EXTRACT_OPERAND (RD, *ip); |
252b5132 | 2860 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) |
bf12938e | 2861 | mips_gprmask |= 1 << EXTRACT_OPERAND (RT, *ip); |
252b5132 | 2862 | if (pinfo & INSN_READ_GPR_S) |
bf12938e | 2863 | mips_gprmask |= 1 << EXTRACT_OPERAND (RS, *ip); |
252b5132 | 2864 | if (pinfo & INSN_WRITE_GPR_31) |
f9419b05 | 2865 | mips_gprmask |= 1 << RA; |
252b5132 | 2866 | if (pinfo & INSN_WRITE_FPR_D) |
bf12938e | 2867 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FD, *ip); |
252b5132 | 2868 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) |
bf12938e | 2869 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FS, *ip); |
252b5132 | 2870 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) |
bf12938e | 2871 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FT, *ip); |
252b5132 | 2872 | if ((pinfo & INSN_READ_FPR_R) != 0) |
bf12938e | 2873 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FR, *ip); |
252b5132 RH |
2874 | if (pinfo & INSN_COP) |
2875 | { | |
bdaaa2e1 KH |
2876 | /* We don't keep enough information to sort these cases out. |
2877 | The itbl support does keep this information however, although | |
2878 | we currently don't support itbl fprmats as part of the cop | |
2879 | instruction. May want to add this support in the future. */ | |
252b5132 RH |
2880 | } |
2881 | /* Never set the bit for $0, which is always zero. */ | |
beae10d5 | 2882 | mips_gprmask &= ~1 << 0; |
252b5132 RH |
2883 | } |
2884 | else | |
2885 | { | |
2886 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) | |
bf12938e | 2887 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RX, *ip); |
252b5132 | 2888 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) |
bf12938e | 2889 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RY, *ip); |
252b5132 | 2890 | if (pinfo & MIPS16_INSN_WRITE_Z) |
bf12938e | 2891 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RZ, *ip); |
252b5132 RH |
2892 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) |
2893 | mips_gprmask |= 1 << TREG; | |
2894 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
2895 | mips_gprmask |= 1 << SP; | |
2896 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
2897 | mips_gprmask |= 1 << RA; | |
2898 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2899 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
2900 | if (pinfo & MIPS16_INSN_READ_Z) | |
bf12938e | 2901 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip); |
252b5132 | 2902 | if (pinfo & MIPS16_INSN_READ_GPR_X) |
bf12938e | 2903 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip); |
252b5132 RH |
2904 | } |
2905 | ||
4d7206a2 | 2906 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
252b5132 RH |
2907 | { |
2908 | /* Filling the branch delay slot is more complex. We try to | |
2909 | switch the branch with the previous instruction, which we can | |
2910 | do if the previous instruction does not set up a condition | |
2911 | that the branch tests and if the branch is not itself the | |
2912 | target of any branch. */ | |
2913 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2914 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
2915 | { | |
2916 | if (mips_optimize < 2 | |
2917 | /* If we have seen .set volatile or .set nomove, don't | |
2918 | optimize. */ | |
2919 | || mips_opts.nomove != 0 | |
a38419a5 RS |
2920 | /* We can't swap if the previous instruction's position |
2921 | is fixed. */ | |
2922 | || history[0].fixed_p | |
252b5132 RH |
2923 | /* If the previous previous insn was in a .set |
2924 | noreorder, we can't swap. Actually, the MIPS | |
2925 | assembler will swap in this situation. However, gcc | |
2926 | configured -with-gnu-as will generate code like | |
2927 | .set noreorder | |
2928 | lw $4,XXX | |
2929 | .set reorder | |
2930 | INSN | |
2931 | bne $4,$0,foo | |
2932 | in which we can not swap the bne and INSN. If gcc is | |
2933 | not configured -with-gnu-as, it does not output the | |
a38419a5 | 2934 | .set pseudo-ops. */ |
47e39b9d | 2935 | || history[1].noreorder_p |
252b5132 RH |
2936 | /* If the branch is itself the target of a branch, we |
2937 | can not swap. We cheat on this; all we check for is | |
2938 | whether there is a label on this instruction. If | |
2939 | there are any branches to anything other than a | |
2940 | label, users must use .set noreorder. */ | |
a8dbcb85 | 2941 | || si->label_list != NULL |
895921c9 MR |
2942 | /* If the previous instruction is in a variant frag |
2943 | other than this branch's one, we cannot do the swap. | |
2944 | This does not apply to the mips16, which uses variant | |
2945 | frags for different purposes. */ | |
252b5132 | 2946 | || (! mips_opts.mips16 |
895921c9 | 2947 | && prev_insn_frag_type == rs_machine_dependent) |
71400594 RS |
2948 | /* Check for conflicts between the branch and the instructions |
2949 | before the candidate delay slot. */ | |
2950 | || nops_for_insn (history + 1, ip) > 0 | |
2951 | /* Check for conflicts between the swapped sequence and the | |
2952 | target of the branch. */ | |
2953 | || nops_for_sequence (2, history + 1, ip, history) > 0 | |
252b5132 RH |
2954 | /* We do not swap with a trap instruction, since it |
2955 | complicates trap handlers to have the trap | |
2956 | instruction be in a delay slot. */ | |
2957 | || (prev_pinfo & INSN_TRAP) | |
2958 | /* If the branch reads a register that the previous | |
2959 | instruction sets, we can not swap. */ | |
2960 | || (! mips_opts.mips16 | |
2961 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
bf12938e | 2962 | && insn_uses_reg (ip, EXTRACT_OPERAND (RT, history[0]), |
252b5132 RH |
2963 | MIPS_GR_REG)) |
2964 | || (! mips_opts.mips16 | |
2965 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
bf12938e | 2966 | && insn_uses_reg (ip, EXTRACT_OPERAND (RD, history[0]), |
252b5132 RH |
2967 | MIPS_GR_REG)) |
2968 | || (mips_opts.mips16 | |
2969 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
bf12938e RS |
2970 | && (insn_uses_reg |
2971 | (ip, MIPS16_EXTRACT_OPERAND (RX, history[0]), | |
2972 | MIPS16_REG))) | |
252b5132 | 2973 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) |
bf12938e RS |
2974 | && (insn_uses_reg |
2975 | (ip, MIPS16_EXTRACT_OPERAND (RY, history[0]), | |
2976 | MIPS16_REG))) | |
252b5132 | 2977 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) |
bf12938e RS |
2978 | && (insn_uses_reg |
2979 | (ip, MIPS16_EXTRACT_OPERAND (RZ, history[0]), | |
2980 | MIPS16_REG))) | |
252b5132 RH |
2981 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) |
2982 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
2983 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2984 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
2985 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2986 | && insn_uses_reg (ip, | |
47e39b9d RS |
2987 | MIPS16OP_EXTRACT_REG32R |
2988 | (history[0].insn_opcode), | |
252b5132 RH |
2989 | MIPS_GR_REG)))) |
2990 | /* If the branch writes a register that the previous | |
2991 | instruction sets, we can not swap (we know that | |
2992 | branches write only to RD or to $31). */ | |
2993 | || (! mips_opts.mips16 | |
2994 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2995 | && (((pinfo & INSN_WRITE_GPR_D) | |
bf12938e RS |
2996 | && (EXTRACT_OPERAND (RT, history[0]) |
2997 | == EXTRACT_OPERAND (RD, *ip))) | |
252b5132 | 2998 | || ((pinfo & INSN_WRITE_GPR_31) |
bf12938e | 2999 | && EXTRACT_OPERAND (RT, history[0]) == RA))) |
252b5132 RH |
3000 | || (! mips_opts.mips16 |
3001 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
3002 | && (((pinfo & INSN_WRITE_GPR_D) | |
bf12938e RS |
3003 | && (EXTRACT_OPERAND (RD, history[0]) |
3004 | == EXTRACT_OPERAND (RD, *ip))) | |
252b5132 | 3005 | || ((pinfo & INSN_WRITE_GPR_31) |
bf12938e | 3006 | && EXTRACT_OPERAND (RD, history[0]) == RA))) |
252b5132 RH |
3007 | || (mips_opts.mips16 |
3008 | && (pinfo & MIPS16_INSN_WRITE_31) | |
3009 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
3010 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
47e39b9d | 3011 | && (MIPS16OP_EXTRACT_REG32R (history[0].insn_opcode) |
252b5132 RH |
3012 | == RA)))) |
3013 | /* If the branch writes a register that the previous | |
3014 | instruction reads, we can not swap (we know that | |
3015 | branches only write to RD or to $31). */ | |
3016 | || (! mips_opts.mips16 | |
3017 | && (pinfo & INSN_WRITE_GPR_D) | |
47e39b9d | 3018 | && insn_uses_reg (&history[0], |
bf12938e | 3019 | EXTRACT_OPERAND (RD, *ip), |
252b5132 RH |
3020 | MIPS_GR_REG)) |
3021 | || (! mips_opts.mips16 | |
3022 | && (pinfo & INSN_WRITE_GPR_31) | |
47e39b9d | 3023 | && insn_uses_reg (&history[0], RA, MIPS_GR_REG)) |
252b5132 RH |
3024 | || (mips_opts.mips16 |
3025 | && (pinfo & MIPS16_INSN_WRITE_31) | |
47e39b9d | 3026 | && insn_uses_reg (&history[0], RA, MIPS_GR_REG)) |
252b5132 RH |
3027 | /* If one instruction sets a condition code and the |
3028 | other one uses a condition code, we can not swap. */ | |
3029 | || ((pinfo & INSN_READ_COND_CODE) | |
3030 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
3031 | || ((pinfo & INSN_WRITE_COND_CODE) | |
3032 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
3033 | /* If the previous instruction uses the PC, we can not | |
3034 | swap. */ | |
3035 | || (mips_opts.mips16 | |
3036 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
252b5132 RH |
3037 | /* If the previous instruction had a fixup in mips16 |
3038 | mode, we can not swap. This normally means that the | |
3039 | previous instruction was a 4 byte branch anyhow. */ | |
47e39b9d | 3040 | || (mips_opts.mips16 && history[0].fixp[0]) |
bdaaa2e1 KH |
3041 | /* If the previous instruction is a sync, sync.l, or |
3042 | sync.p, we can not swap. */ | |
f173e82e | 3043 | || (prev_pinfo & INSN_SYNC)) |
252b5132 | 3044 | { |
29024861 DU |
3045 | if (mips_opts.mips16 |
3046 | && (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
3047 | && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31)) | |
3994f87e | 3048 | && ISA_SUPPORTS_MIPS16E) |
29024861 DU |
3049 | { |
3050 | /* Convert MIPS16 jr/jalr into a "compact" jump. */ | |
3051 | ip->insn_opcode |= 0x0080; | |
3052 | install_insn (ip); | |
3053 | insert_into_history (0, 1, ip); | |
3054 | } | |
3055 | else | |
3056 | { | |
3057 | /* We could do even better for unconditional branches to | |
3058 | portions of this object file; we could pick up the | |
3059 | instruction at the destination, put it in the delay | |
3060 | slot, and bump the destination address. */ | |
3061 | insert_into_history (0, 1, ip); | |
3062 | emit_nop (); | |
3063 | } | |
3064 | ||
dd22970f ILT |
3065 | if (mips_relax.sequence) |
3066 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
252b5132 RH |
3067 | } |
3068 | else | |
3069 | { | |
3070 | /* It looks like we can actually do the swap. */ | |
1e915849 RS |
3071 | struct mips_cl_insn delay = history[0]; |
3072 | if (mips_opts.mips16) | |
252b5132 | 3073 | { |
b8ee1a6e DU |
3074 | know (delay.frag == ip->frag); |
3075 | move_insn (ip, delay.frag, delay.where); | |
3076 | move_insn (&delay, ip->frag, ip->where + insn_length (ip)); | |
1e915849 RS |
3077 | } |
3078 | else if (relaxed_branch) | |
3079 | { | |
3080 | /* Add the delay slot instruction to the end of the | |
3081 | current frag and shrink the fixed part of the | |
3082 | original frag. If the branch occupies the tail of | |
3083 | the latter, move it backwards to cover the gap. */ | |
3084 | delay.frag->fr_fix -= 4; | |
3085 | if (delay.frag == ip->frag) | |
3086 | move_insn (ip, ip->frag, ip->where - 4); | |
3087 | add_fixed_insn (&delay); | |
252b5132 RH |
3088 | } |
3089 | else | |
3090 | { | |
1e915849 RS |
3091 | move_insn (&delay, ip->frag, ip->where); |
3092 | move_insn (ip, history[0].frag, history[0].where); | |
252b5132 | 3093 | } |
1e915849 RS |
3094 | history[0] = *ip; |
3095 | delay.fixed_p = 1; | |
3096 | insert_into_history (0, 1, &delay); | |
252b5132 | 3097 | } |
252b5132 RH |
3098 | |
3099 | /* If that was an unconditional branch, forget the previous | |
3100 | insn information. */ | |
3101 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
7d10b47d | 3102 | mips_no_prev_insn (); |
252b5132 RH |
3103 | } |
3104 | else if (pinfo & INSN_COND_BRANCH_LIKELY) | |
3105 | { | |
3106 | /* We don't yet optimize a branch likely. What we should do | |
3107 | is look at the target, copy the instruction found there | |
3108 | into the delay slot, and increment the branch to jump to | |
3109 | the next instruction. */ | |
1e915849 | 3110 | insert_into_history (0, 1, ip); |
252b5132 | 3111 | emit_nop (); |
252b5132 RH |
3112 | } |
3113 | else | |
1e915849 | 3114 | insert_into_history (0, 1, ip); |
252b5132 | 3115 | } |
1e915849 RS |
3116 | else |
3117 | insert_into_history (0, 1, ip); | |
252b5132 RH |
3118 | |
3119 | /* We just output an insn, so the next one doesn't have a label. */ | |
3120 | mips_clear_insn_labels (); | |
252b5132 RH |
3121 | } |
3122 | ||
7d10b47d | 3123 | /* Forget that there was any previous instruction or label. */ |
252b5132 RH |
3124 | |
3125 | static void | |
7d10b47d | 3126 | mips_no_prev_insn (void) |
252b5132 | 3127 | { |
7d10b47d RS |
3128 | prev_nop_frag = NULL; |
3129 | insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); | |
252b5132 RH |
3130 | mips_clear_insn_labels (); |
3131 | } | |
3132 | ||
7d10b47d RS |
3133 | /* This function must be called before we emit something other than |
3134 | instructions. It is like mips_no_prev_insn except that it inserts | |
3135 | any NOPS that might be needed by previous instructions. */ | |
252b5132 | 3136 | |
7d10b47d RS |
3137 | void |
3138 | mips_emit_delays (void) | |
252b5132 RH |
3139 | { |
3140 | if (! mips_opts.noreorder) | |
3141 | { | |
71400594 | 3142 | int nops = nops_for_insn (history, NULL); |
252b5132 RH |
3143 | if (nops > 0) |
3144 | { | |
7d10b47d RS |
3145 | while (nops-- > 0) |
3146 | add_fixed_insn (NOP_INSN); | |
3147 | mips_move_labels (); | |
3148 | } | |
3149 | } | |
3150 | mips_no_prev_insn (); | |
3151 | } | |
3152 | ||
3153 | /* Start a (possibly nested) noreorder block. */ | |
3154 | ||
3155 | static void | |
3156 | start_noreorder (void) | |
3157 | { | |
3158 | if (mips_opts.noreorder == 0) | |
3159 | { | |
3160 | unsigned int i; | |
3161 | int nops; | |
3162 | ||
3163 | /* None of the instructions before the .set noreorder can be moved. */ | |
3164 | for (i = 0; i < ARRAY_SIZE (history); i++) | |
3165 | history[i].fixed_p = 1; | |
3166 | ||
3167 | /* Insert any nops that might be needed between the .set noreorder | |
3168 | block and the previous instructions. We will later remove any | |
3169 | nops that turn out not to be needed. */ | |
3170 | nops = nops_for_insn (history, NULL); | |
3171 | if (nops > 0) | |
3172 | { | |
3173 | if (mips_optimize != 0) | |
252b5132 RH |
3174 | { |
3175 | /* Record the frag which holds the nop instructions, so | |
3176 | that we can remove them if we don't need them. */ | |
3177 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); | |
3178 | prev_nop_frag = frag_now; | |
3179 | prev_nop_frag_holds = nops; | |
3180 | prev_nop_frag_required = 0; | |
3181 | prev_nop_frag_since = 0; | |
3182 | } | |
3183 | ||
3184 | for (; nops > 0; --nops) | |
1e915849 | 3185 | add_fixed_insn (NOP_INSN); |
252b5132 | 3186 | |
7d10b47d RS |
3187 | /* Move on to a new frag, so that it is safe to simply |
3188 | decrease the size of prev_nop_frag. */ | |
3189 | frag_wane (frag_now); | |
3190 | frag_new (0); | |
404a8071 | 3191 | mips_move_labels (); |
252b5132 | 3192 | } |
7d10b47d RS |
3193 | mips16_mark_labels (); |
3194 | mips_clear_insn_labels (); | |
252b5132 | 3195 | } |
7d10b47d RS |
3196 | mips_opts.noreorder++; |
3197 | mips_any_noreorder = 1; | |
3198 | } | |
252b5132 | 3199 | |
7d10b47d | 3200 | /* End a nested noreorder block. */ |
252b5132 | 3201 | |
7d10b47d RS |
3202 | static void |
3203 | end_noreorder (void) | |
3204 | { | |
3205 | mips_opts.noreorder--; | |
3206 | if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) | |
3207 | { | |
3208 | /* Commit to inserting prev_nop_frag_required nops and go back to | |
3209 | handling nop insertion the .set reorder way. */ | |
3210 | prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) | |
3211 | * (mips_opts.mips16 ? 2 : 4)); | |
3212 | insert_into_history (prev_nop_frag_since, | |
3213 | prev_nop_frag_required, NOP_INSN); | |
3214 | prev_nop_frag = NULL; | |
3215 | } | |
252b5132 RH |
3216 | } |
3217 | ||
584892a6 RS |
3218 | /* Set up global variables for the start of a new macro. */ |
3219 | ||
3220 | static void | |
3221 | macro_start (void) | |
3222 | { | |
3223 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
3224 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder | |
47e39b9d | 3225 | && (history[0].insn_mo->pinfo |
584892a6 RS |
3226 | & (INSN_UNCOND_BRANCH_DELAY |
3227 | | INSN_COND_BRANCH_DELAY | |
3228 | | INSN_COND_BRANCH_LIKELY)) != 0); | |
3229 | } | |
3230 | ||
3231 | /* Given that a macro is longer than 4 bytes, return the appropriate warning | |
3232 | for it. Return null if no warning is needed. SUBTYPE is a bitmask of | |
3233 | RELAX_DELAY_SLOT and RELAX_NOMACRO. */ | |
3234 | ||
3235 | static const char * | |
3236 | macro_warning (relax_substateT subtype) | |
3237 | { | |
3238 | if (subtype & RELAX_DELAY_SLOT) | |
3239 | return _("Macro instruction expanded into multiple instructions" | |
3240 | " in a branch delay slot"); | |
3241 | else if (subtype & RELAX_NOMACRO) | |
3242 | return _("Macro instruction expanded into multiple instructions"); | |
3243 | else | |
3244 | return 0; | |
3245 | } | |
3246 | ||
3247 | /* Finish up a macro. Emit warnings as appropriate. */ | |
3248 | ||
3249 | static void | |
3250 | macro_end (void) | |
3251 | { | |
3252 | if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4) | |
3253 | { | |
3254 | relax_substateT subtype; | |
3255 | ||
3256 | /* Set up the relaxation warning flags. */ | |
3257 | subtype = 0; | |
3258 | if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0]) | |
3259 | subtype |= RELAX_SECOND_LONGER; | |
3260 | if (mips_opts.warn_about_macros) | |
3261 | subtype |= RELAX_NOMACRO; | |
3262 | if (mips_macro_warning.delay_slot_p) | |
3263 | subtype |= RELAX_DELAY_SLOT; | |
3264 | ||
3265 | if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4) | |
3266 | { | |
3267 | /* Either the macro has a single implementation or both | |
3268 | implementations are longer than 4 bytes. Emit the | |
3269 | warning now. */ | |
3270 | const char *msg = macro_warning (subtype); | |
3271 | if (msg != 0) | |
3272 | as_warn (msg); | |
3273 | } | |
3274 | else | |
3275 | { | |
3276 | /* One implementation might need a warning but the other | |
3277 | definitely doesn't. */ | |
3278 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
3279 | } | |
3280 | } | |
3281 | } | |
3282 | ||
6e1304d8 RS |
3283 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
3284 | The first argument in *ARGS will be either the code for a single | |
3285 | relocation or -1 followed by the three codes that make up a | |
3286 | composite relocation. */ | |
3287 | ||
3288 | static void | |
3289 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
3290 | { | |
3291 | int i, next; | |
3292 | ||
3293 | next = va_arg (*args, int); | |
3294 | if (next >= 0) | |
3295 | r[0] = (bfd_reloc_code_real_type) next; | |
3296 | else | |
3297 | for (i = 0; i < 3; i++) | |
3298 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
3299 | } | |
3300 | ||
252b5132 RH |
3301 | /* Build an instruction created by a macro expansion. This is passed |
3302 | a pointer to the count of instructions created so far, an | |
3303 | expression, the name of the instruction to build, an operand format | |
3304 | string, and corresponding arguments. */ | |
3305 | ||
252b5132 | 3306 | static void |
67c0d1eb | 3307 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 | 3308 | { |
1e915849 | 3309 | const struct mips_opcode *mo; |
252b5132 | 3310 | struct mips_cl_insn insn; |
f6688943 | 3311 | bfd_reloc_code_real_type r[3]; |
252b5132 | 3312 | va_list args; |
252b5132 | 3313 | |
252b5132 | 3314 | va_start (args, fmt); |
252b5132 | 3315 | |
252b5132 RH |
3316 | if (mips_opts.mips16) |
3317 | { | |
67c0d1eb | 3318 | mips16_macro_build (ep, name, fmt, args); |
252b5132 RH |
3319 | va_end (args); |
3320 | return; | |
3321 | } | |
3322 | ||
f6688943 TS |
3323 | r[0] = BFD_RELOC_UNUSED; |
3324 | r[1] = BFD_RELOC_UNUSED; | |
3325 | r[2] = BFD_RELOC_UNUSED; | |
1e915849 RS |
3326 | mo = (struct mips_opcode *) hash_find (op_hash, name); |
3327 | assert (mo); | |
3328 | assert (strcmp (name, mo->name) == 0); | |
3329 | ||
3330 | /* Search until we get a match for NAME. It is assumed here that | |
65263ce3 | 3331 | macros will never generate MDMX, MIPS-3D, DSP or MT instructions. */ |
1e915849 RS |
3332 | while (strcmp (fmt, mo->args) != 0 |
3333 | || mo->pinfo == INSN_MACRO | |
3334 | || !OPCODE_IS_MEMBER (mo, | |
3335 | (mips_opts.isa | |
9b3f89ee | 3336 | | (mips_opts.mips16 ? INSN_MIPS16 : 0) |
e16bfa71 | 3337 | | (mips_opts.ase_smartmips ? INSN_SMARTMIPS : 0)), |
fef14a42 | 3338 | mips_opts.arch) |
1e915849 RS |
3339 | || (mips_opts.arch == CPU_R4650 && (mo->pinfo & FP_D) != 0)) |
3340 | { | |
3341 | ++mo; | |
3342 | assert (mo->name); | |
3343 | assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
3344 | } |
3345 | ||
1e915849 | 3346 | create_insn (&insn, mo); |
252b5132 RH |
3347 | for (;;) |
3348 | { | |
3349 | switch (*fmt++) | |
3350 | { | |
3351 | case '\0': | |
3352 | break; | |
3353 | ||
3354 | case ',': | |
3355 | case '(': | |
3356 | case ')': | |
3357 | continue; | |
3358 | ||
5f74bc13 CD |
3359 | case '+': |
3360 | switch (*fmt++) | |
3361 | { | |
3362 | case 'A': | |
3363 | case 'E': | |
bf12938e | 3364 | INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); |
5f74bc13 CD |
3365 | continue; |
3366 | ||
3367 | case 'B': | |
3368 | case 'F': | |
3369 | /* Note that in the macro case, these arguments are already | |
3370 | in MSB form. (When handling the instruction in the | |
3371 | non-macro case, these arguments are sizes from which | |
3372 | MSB values must be calculated.) */ | |
bf12938e | 3373 | INSERT_OPERAND (INSMSB, insn, va_arg (args, int)); |
5f74bc13 CD |
3374 | continue; |
3375 | ||
3376 | case 'C': | |
3377 | case 'G': | |
3378 | case 'H': | |
3379 | /* Note that in the macro case, these arguments are already | |
3380 | in MSBD form. (When handling the instruction in the | |
3381 | non-macro case, these arguments are sizes from which | |
3382 | MSBD values must be calculated.) */ | |
bf12938e | 3383 | INSERT_OPERAND (EXTMSBD, insn, va_arg (args, int)); |
5f74bc13 CD |
3384 | continue; |
3385 | ||
3386 | default: | |
3387 | internalError (); | |
3388 | } | |
3389 | continue; | |
3390 | ||
252b5132 RH |
3391 | case 't': |
3392 | case 'w': | |
3393 | case 'E': | |
bf12938e | 3394 | INSERT_OPERAND (RT, insn, va_arg (args, int)); |
252b5132 RH |
3395 | continue; |
3396 | ||
3397 | case 'c': | |
bf12938e | 3398 | INSERT_OPERAND (CODE, insn, va_arg (args, int)); |
38487616 TS |
3399 | continue; |
3400 | ||
252b5132 RH |
3401 | case 'T': |
3402 | case 'W': | |
bf12938e | 3403 | INSERT_OPERAND (FT, insn, va_arg (args, int)); |
252b5132 RH |
3404 | continue; |
3405 | ||
3406 | case 'd': | |
3407 | case 'G': | |
af7ee8bf | 3408 | case 'K': |
bf12938e | 3409 | INSERT_OPERAND (RD, insn, va_arg (args, int)); |
252b5132 RH |
3410 | continue; |
3411 | ||
4372b673 NC |
3412 | case 'U': |
3413 | { | |
3414 | int tmp = va_arg (args, int); | |
3415 | ||
bf12938e RS |
3416 | INSERT_OPERAND (RT, insn, tmp); |
3417 | INSERT_OPERAND (RD, insn, tmp); | |
beae10d5 | 3418 | continue; |
4372b673 NC |
3419 | } |
3420 | ||
252b5132 RH |
3421 | case 'V': |
3422 | case 'S': | |
bf12938e | 3423 | INSERT_OPERAND (FS, insn, va_arg (args, int)); |
252b5132 RH |
3424 | continue; |
3425 | ||
3426 | case 'z': | |
3427 | continue; | |
3428 | ||
3429 | case '<': | |
bf12938e | 3430 | INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); |
252b5132 RH |
3431 | continue; |
3432 | ||
3433 | case 'D': | |
bf12938e | 3434 | INSERT_OPERAND (FD, insn, va_arg (args, int)); |
252b5132 RH |
3435 | continue; |
3436 | ||
3437 | case 'B': | |
bf12938e | 3438 | INSERT_OPERAND (CODE20, insn, va_arg (args, int)); |
252b5132 RH |
3439 | continue; |
3440 | ||
4372b673 | 3441 | case 'J': |
bf12938e | 3442 | INSERT_OPERAND (CODE19, insn, va_arg (args, int)); |
4372b673 NC |
3443 | continue; |
3444 | ||
252b5132 | 3445 | case 'q': |
bf12938e | 3446 | INSERT_OPERAND (CODE2, insn, va_arg (args, int)); |
252b5132 RH |
3447 | continue; |
3448 | ||
3449 | case 'b': | |
3450 | case 's': | |
3451 | case 'r': | |
3452 | case 'v': | |
bf12938e | 3453 | INSERT_OPERAND (RS, insn, va_arg (args, int)); |
252b5132 RH |
3454 | continue; |
3455 | ||
3456 | case 'i': | |
3457 | case 'j': | |
3458 | case 'o': | |
6e1304d8 | 3459 | macro_read_relocs (&args, r); |
cdf6fd85 | 3460 | assert (*r == BFD_RELOC_GPREL16 |
f6688943 TS |
3461 | || *r == BFD_RELOC_MIPS_LITERAL |
3462 | || *r == BFD_RELOC_MIPS_HIGHER | |
3463 | || *r == BFD_RELOC_HI16_S | |
3464 | || *r == BFD_RELOC_LO16 | |
3465 | || *r == BFD_RELOC_MIPS_GOT16 | |
3466 | || *r == BFD_RELOC_MIPS_CALL16 | |
438c16b8 TS |
3467 | || *r == BFD_RELOC_MIPS_GOT_DISP |
3468 | || *r == BFD_RELOC_MIPS_GOT_PAGE | |
3469 | || *r == BFD_RELOC_MIPS_GOT_OFST | |
f6688943 | 3470 | || *r == BFD_RELOC_MIPS_GOT_LO16 |
3e722fb5 | 3471 | || *r == BFD_RELOC_MIPS_CALL_LO16); |
252b5132 RH |
3472 | continue; |
3473 | ||
3474 | case 'u': | |
6e1304d8 | 3475 | macro_read_relocs (&args, r); |
252b5132 RH |
3476 | assert (ep != NULL |
3477 | && (ep->X_op == O_constant | |
3478 | || (ep->X_op == O_symbol | |
f6688943 TS |
3479 | && (*r == BFD_RELOC_MIPS_HIGHEST |
3480 | || *r == BFD_RELOC_HI16_S | |
3481 | || *r == BFD_RELOC_HI16 | |
3482 | || *r == BFD_RELOC_GPREL16 | |
3483 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
3e722fb5 | 3484 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); |
252b5132 RH |
3485 | continue; |
3486 | ||
3487 | case 'p': | |
3488 | assert (ep != NULL); | |
bad36eac | 3489 | |
252b5132 RH |
3490 | /* |
3491 | * This allows macro() to pass an immediate expression for | |
3492 | * creating short branches without creating a symbol. | |
bad36eac DJ |
3493 | * |
3494 | * We don't allow branch relaxation for these branches, as | |
3495 | * they should only appear in ".set nomacro" anyway. | |
252b5132 RH |
3496 | */ |
3497 | if (ep->X_op == O_constant) | |
3498 | { | |
bad36eac DJ |
3499 | if ((ep->X_add_number & 3) != 0) |
3500 | as_bad (_("branch to misaligned address (0x%lx)"), | |
3501 | (unsigned long) ep->X_add_number); | |
3502 | if ((ep->X_add_number + 0x20000) & ~0x3ffff) | |
3503 | as_bad (_("branch address range overflow (0x%lx)"), | |
3504 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
3505 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; |
3506 | ep = NULL; | |
3507 | } | |
3508 | else | |
0b25d3e6 | 3509 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
3510 | continue; |
3511 | ||
3512 | case 'a': | |
3513 | assert (ep != NULL); | |
f6688943 | 3514 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
3515 | continue; |
3516 | ||
3517 | case 'C': | |
a9e24354 | 3518 | INSERT_OPERAND (COPZ, insn, va_arg (args, unsigned long)); |
252b5132 RH |
3519 | continue; |
3520 | ||
d43b4baf | 3521 | case 'k': |
a9e24354 | 3522 | INSERT_OPERAND (CACHE, insn, va_arg (args, unsigned long)); |
d43b4baf TS |
3523 | continue; |
3524 | ||
252b5132 RH |
3525 | default: |
3526 | internalError (); | |
3527 | } | |
3528 | break; | |
3529 | } | |
3530 | va_end (args); | |
f6688943 | 3531 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3532 | |
4d7206a2 | 3533 | append_insn (&insn, ep, r); |
252b5132 RH |
3534 | } |
3535 | ||
3536 | static void | |
67c0d1eb | 3537 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
17a2f251 | 3538 | va_list args) |
252b5132 | 3539 | { |
1e915849 | 3540 | struct mips_opcode *mo; |
252b5132 | 3541 | struct mips_cl_insn insn; |
f6688943 TS |
3542 | bfd_reloc_code_real_type r[3] |
3543 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 3544 | |
1e915849 RS |
3545 | mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
3546 | assert (mo); | |
3547 | assert (strcmp (name, mo->name) == 0); | |
252b5132 | 3548 | |
1e915849 | 3549 | while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) |
252b5132 | 3550 | { |
1e915849 RS |
3551 | ++mo; |
3552 | assert (mo->name); | |
3553 | assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
3554 | } |
3555 | ||
1e915849 | 3556 | create_insn (&insn, mo); |
252b5132 RH |
3557 | for (;;) |
3558 | { | |
3559 | int c; | |
3560 | ||
3561 | c = *fmt++; | |
3562 | switch (c) | |
3563 | { | |
3564 | case '\0': | |
3565 | break; | |
3566 | ||
3567 | case ',': | |
3568 | case '(': | |
3569 | case ')': | |
3570 | continue; | |
3571 | ||
3572 | case 'y': | |
3573 | case 'w': | |
bf12938e | 3574 | MIPS16_INSERT_OPERAND (RY, insn, va_arg (args, int)); |
252b5132 RH |
3575 | continue; |
3576 | ||
3577 | case 'x': | |
3578 | case 'v': | |
bf12938e | 3579 | MIPS16_INSERT_OPERAND (RX, insn, va_arg (args, int)); |
252b5132 RH |
3580 | continue; |
3581 | ||
3582 | case 'z': | |
bf12938e | 3583 | MIPS16_INSERT_OPERAND (RZ, insn, va_arg (args, int)); |
252b5132 RH |
3584 | continue; |
3585 | ||
3586 | case 'Z': | |
bf12938e | 3587 | MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (args, int)); |
252b5132 RH |
3588 | continue; |
3589 | ||
3590 | case '0': | |
3591 | case 'S': | |
3592 | case 'P': | |
3593 | case 'R': | |
3594 | continue; | |
3595 | ||
3596 | case 'X': | |
bf12938e | 3597 | MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (args, int)); |
252b5132 RH |
3598 | continue; |
3599 | ||
3600 | case 'Y': | |
3601 | { | |
3602 | int regno; | |
3603 | ||
3604 | regno = va_arg (args, int); | |
3605 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
a9e24354 | 3606 | MIPS16_INSERT_OPERAND (REG32R, insn, regno); |
252b5132 RH |
3607 | } |
3608 | continue; | |
3609 | ||
3610 | case '<': | |
3611 | case '>': | |
3612 | case '4': | |
3613 | case '5': | |
3614 | case 'H': | |
3615 | case 'W': | |
3616 | case 'D': | |
3617 | case 'j': | |
3618 | case '8': | |
3619 | case 'V': | |
3620 | case 'C': | |
3621 | case 'U': | |
3622 | case 'k': | |
3623 | case 'K': | |
3624 | case 'p': | |
3625 | case 'q': | |
3626 | { | |
3627 | assert (ep != NULL); | |
3628 | ||
3629 | if (ep->X_op != O_constant) | |
874e8986 | 3630 | *r = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
3631 | else |
3632 | { | |
b34976b6 AM |
3633 | mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE, |
3634 | FALSE, &insn.insn_opcode, &insn.use_extend, | |
c4e7957c | 3635 | &insn.extend); |
252b5132 | 3636 | ep = NULL; |
f6688943 | 3637 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
3638 | } |
3639 | } | |
3640 | continue; | |
3641 | ||
3642 | case '6': | |
bf12938e | 3643 | MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (args, int)); |
252b5132 RH |
3644 | continue; |
3645 | } | |
3646 | ||
3647 | break; | |
3648 | } | |
3649 | ||
f6688943 | 3650 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3651 | |
4d7206a2 | 3652 | append_insn (&insn, ep, r); |
252b5132 RH |
3653 | } |
3654 | ||
2051e8c4 MR |
3655 | /* |
3656 | * Sign-extend 32-bit mode constants that have bit 31 set and all | |
3657 | * higher bits unset. | |
3658 | */ | |
9f872bbe | 3659 | static void |
2051e8c4 MR |
3660 | normalize_constant_expr (expressionS *ex) |
3661 | { | |
9ee2a2d4 | 3662 | if (ex->X_op == O_constant |
2051e8c4 MR |
3663 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) |
3664 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
3665 | - 0x80000000); | |
3666 | } | |
3667 | ||
3668 | /* | |
3669 | * Sign-extend 32-bit mode address offsets that have bit 31 set and | |
3670 | * all higher bits unset. | |
3671 | */ | |
3672 | static void | |
3673 | normalize_address_expr (expressionS *ex) | |
3674 | { | |
3675 | if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) | |
3676 | || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) | |
3677 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
3678 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
3679 | - 0x80000000); | |
3680 | } | |
3681 | ||
438c16b8 TS |
3682 | /* |
3683 | * Generate a "jalr" instruction with a relocation hint to the called | |
3684 | * function. This occurs in NewABI PIC code. | |
3685 | */ | |
3686 | static void | |
67c0d1eb | 3687 | macro_build_jalr (expressionS *ep) |
438c16b8 | 3688 | { |
685736be | 3689 | char *f = NULL; |
b34976b6 | 3690 | |
438c16b8 | 3691 | if (HAVE_NEWABI) |
f21f8242 | 3692 | { |
cc3d92a5 | 3693 | frag_grow (8); |
f21f8242 AO |
3694 | f = frag_more (0); |
3695 | } | |
67c0d1eb | 3696 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); |
438c16b8 | 3697 | if (HAVE_NEWABI) |
f21f8242 | 3698 | fix_new_exp (frag_now, f - frag_now->fr_literal, |
a105a300 | 3699 | 4, ep, FALSE, BFD_RELOC_MIPS_JALR); |
438c16b8 TS |
3700 | } |
3701 | ||
252b5132 RH |
3702 | /* |
3703 | * Generate a "lui" instruction. | |
3704 | */ | |
3705 | static void | |
67c0d1eb | 3706 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 RH |
3707 | { |
3708 | expressionS high_expr; | |
1e915849 | 3709 | const struct mips_opcode *mo; |
252b5132 | 3710 | struct mips_cl_insn insn; |
f6688943 TS |
3711 | bfd_reloc_code_real_type r[3] |
3712 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
5a38dc70 AM |
3713 | const char *name = "lui"; |
3714 | const char *fmt = "t,u"; | |
252b5132 RH |
3715 | |
3716 | assert (! mips_opts.mips16); | |
3717 | ||
4d7206a2 | 3718 | high_expr = *ep; |
252b5132 RH |
3719 | |
3720 | if (high_expr.X_op == O_constant) | |
3721 | { | |
54f4ddb3 | 3722 | /* We can compute the instruction now without a relocation entry. */ |
e7d556df TS |
3723 | high_expr.X_add_number = ((high_expr.X_add_number + 0x8000) |
3724 | >> 16) & 0xffff; | |
f6688943 | 3725 | *r = BFD_RELOC_UNUSED; |
252b5132 | 3726 | } |
78e1bb40 | 3727 | else |
252b5132 RH |
3728 | { |
3729 | assert (ep->X_op == O_symbol); | |
bbe506e8 TS |
3730 | /* _gp_disp is a special case, used from s_cpload. |
3731 | __gnu_local_gp is used if mips_no_shared. */ | |
252b5132 | 3732 | assert (mips_pic == NO_PIC |
78e1bb40 | 3733 | || (! HAVE_NEWABI |
aa6975fb ILT |
3734 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
3735 | || (! mips_in_shared | |
bbe506e8 TS |
3736 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
3737 | "__gnu_local_gp") == 0)); | |
f6688943 | 3738 | *r = BFD_RELOC_HI16_S; |
252b5132 RH |
3739 | } |
3740 | ||
1e915849 RS |
3741 | mo = hash_find (op_hash, name); |
3742 | assert (strcmp (name, mo->name) == 0); | |
3743 | assert (strcmp (fmt, mo->args) == 0); | |
3744 | create_insn (&insn, mo); | |
252b5132 | 3745 | |
bf12938e RS |
3746 | insn.insn_opcode = insn.insn_mo->match; |
3747 | INSERT_OPERAND (RT, insn, regnum); | |
f6688943 | 3748 | if (*r == BFD_RELOC_UNUSED) |
252b5132 RH |
3749 | { |
3750 | insn.insn_opcode |= high_expr.X_add_number; | |
4d7206a2 | 3751 | append_insn (&insn, NULL, r); |
252b5132 RH |
3752 | } |
3753 | else | |
4d7206a2 | 3754 | append_insn (&insn, &high_expr, r); |
252b5132 RH |
3755 | } |
3756 | ||
885add95 CD |
3757 | /* Generate a sequence of instructions to do a load or store from a constant |
3758 | offset off of a base register (breg) into/from a target register (treg), | |
3759 | using AT if necessary. */ | |
3760 | static void | |
67c0d1eb RS |
3761 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
3762 | int treg, int breg, int dbl) | |
885add95 CD |
3763 | { |
3764 | assert (ep->X_op == O_constant); | |
3765 | ||
256ab948 | 3766 | /* Sign-extending 32-bit constants makes their handling easier. */ |
2051e8c4 MR |
3767 | if (!dbl) |
3768 | normalize_constant_expr (ep); | |
256ab948 | 3769 | |
67c1ffbe | 3770 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 3771 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
3772 | as_warn (_("operand overflow")); |
3773 | ||
3774 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
3775 | { | |
3776 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 3777 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
3778 | } |
3779 | else | |
3780 | { | |
3781 | /* 32-bit offset, need multiple instructions and AT, like: | |
3782 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
3783 | addu $tempreg,$tempreg,$breg | |
3784 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
3785 | to handle the complete offset. */ | |
67c0d1eb RS |
3786 | macro_build_lui (ep, AT); |
3787 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
3788 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 CD |
3789 | |
3790 | if (mips_opts.noat) | |
8fc2e39e | 3791 | as_bad (_("Macro used $at after \".set noat\"")); |
885add95 CD |
3792 | } |
3793 | } | |
3794 | ||
252b5132 RH |
3795 | /* set_at() |
3796 | * Generates code to set the $at register to true (one) | |
3797 | * if reg is less than the immediate expression. | |
3798 | */ | |
3799 | static void | |
67c0d1eb | 3800 | set_at (int reg, int unsignedp) |
252b5132 RH |
3801 | { |
3802 | if (imm_expr.X_op == O_constant | |
3803 | && imm_expr.X_add_number >= -0x8000 | |
3804 | && imm_expr.X_add_number < 0x8000) | |
67c0d1eb RS |
3805 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
3806 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
3807 | else |
3808 | { | |
67c0d1eb RS |
3809 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
3810 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); | |
252b5132 RH |
3811 | } |
3812 | } | |
3813 | ||
3814 | /* Warn if an expression is not a constant. */ | |
3815 | ||
3816 | static void | |
17a2f251 | 3817 | check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) |
252b5132 RH |
3818 | { |
3819 | if (ex->X_op == O_big) | |
3820 | as_bad (_("unsupported large constant")); | |
3821 | else if (ex->X_op != O_constant) | |
9ee2a2d4 MR |
3822 | as_bad (_("Instruction %s requires absolute expression"), |
3823 | ip->insn_mo->name); | |
13757d0c | 3824 | |
9ee2a2d4 MR |
3825 | if (HAVE_32BIT_GPRS) |
3826 | normalize_constant_expr (ex); | |
252b5132 RH |
3827 | } |
3828 | ||
3829 | /* Count the leading zeroes by performing a binary chop. This is a | |
3830 | bulky bit of source, but performance is a LOT better for the | |
3831 | majority of values than a simple loop to count the bits: | |
3832 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
3833 | if ((v) & (1 << (31 - lcnt))) | |
3834 | break; | |
3835 | However it is not code size friendly, and the gain will drop a bit | |
3836 | on certain cached systems. | |
3837 | */ | |
3838 | #define COUNT_TOP_ZEROES(v) \ | |
3839 | (((v) & ~0xffff) == 0 \ | |
3840 | ? ((v) & ~0xff) == 0 \ | |
3841 | ? ((v) & ~0xf) == 0 \ | |
3842 | ? ((v) & ~0x3) == 0 \ | |
3843 | ? ((v) & ~0x1) == 0 \ | |
3844 | ? !(v) \ | |
3845 | ? 32 \ | |
3846 | : 31 \ | |
3847 | : 30 \ | |
3848 | : ((v) & ~0x7) == 0 \ | |
3849 | ? 29 \ | |
3850 | : 28 \ | |
3851 | : ((v) & ~0x3f) == 0 \ | |
3852 | ? ((v) & ~0x1f) == 0 \ | |
3853 | ? 27 \ | |
3854 | : 26 \ | |
3855 | : ((v) & ~0x7f) == 0 \ | |
3856 | ? 25 \ | |
3857 | : 24 \ | |
3858 | : ((v) & ~0xfff) == 0 \ | |
3859 | ? ((v) & ~0x3ff) == 0 \ | |
3860 | ? ((v) & ~0x1ff) == 0 \ | |
3861 | ? 23 \ | |
3862 | : 22 \ | |
3863 | : ((v) & ~0x7ff) == 0 \ | |
3864 | ? 21 \ | |
3865 | : 20 \ | |
3866 | : ((v) & ~0x3fff) == 0 \ | |
3867 | ? ((v) & ~0x1fff) == 0 \ | |
3868 | ? 19 \ | |
3869 | : 18 \ | |
3870 | : ((v) & ~0x7fff) == 0 \ | |
3871 | ? 17 \ | |
3872 | : 16 \ | |
3873 | : ((v) & ~0xffffff) == 0 \ | |
3874 | ? ((v) & ~0xfffff) == 0 \ | |
3875 | ? ((v) & ~0x3ffff) == 0 \ | |
3876 | ? ((v) & ~0x1ffff) == 0 \ | |
3877 | ? 15 \ | |
3878 | : 14 \ | |
3879 | : ((v) & ~0x7ffff) == 0 \ | |
3880 | ? 13 \ | |
3881 | : 12 \ | |
3882 | : ((v) & ~0x3fffff) == 0 \ | |
3883 | ? ((v) & ~0x1fffff) == 0 \ | |
3884 | ? 11 \ | |
3885 | : 10 \ | |
3886 | : ((v) & ~0x7fffff) == 0 \ | |
3887 | ? 9 \ | |
3888 | : 8 \ | |
3889 | : ((v) & ~0xfffffff) == 0 \ | |
3890 | ? ((v) & ~0x3ffffff) == 0 \ | |
3891 | ? ((v) & ~0x1ffffff) == 0 \ | |
3892 | ? 7 \ | |
3893 | : 6 \ | |
3894 | : ((v) & ~0x7ffffff) == 0 \ | |
3895 | ? 5 \ | |
3896 | : 4 \ | |
3897 | : ((v) & ~0x3fffffff) == 0 \ | |
3898 | ? ((v) & ~0x1fffffff) == 0 \ | |
3899 | ? 3 \ | |
3900 | : 2 \ | |
3901 | : ((v) & ~0x7fffffff) == 0 \ | |
3902 | ? 1 \ | |
3903 | : 0) | |
3904 | ||
3905 | /* load_register() | |
67c1ffbe | 3906 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
3907 | * an absolute expression value into a register. |
3908 | */ | |
3909 | static void | |
67c0d1eb | 3910 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
3911 | { |
3912 | int freg; | |
3913 | expressionS hi32, lo32; | |
3914 | ||
3915 | if (ep->X_op != O_big) | |
3916 | { | |
3917 | assert (ep->X_op == O_constant); | |
256ab948 TS |
3918 | |
3919 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
2051e8c4 MR |
3920 | if (!dbl) |
3921 | normalize_constant_expr (ep); | |
256ab948 TS |
3922 | |
3923 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
3924 | { |
3925 | /* We can handle 16 bit signed values with an addiu to | |
3926 | $zero. No need to ever use daddiu here, since $zero and | |
3927 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 3928 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3929 | return; |
3930 | } | |
3931 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
3932 | { | |
3933 | /* We can handle 16 bit unsigned values with an ori to | |
3934 | $zero. */ | |
67c0d1eb | 3935 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3936 | return; |
3937 | } | |
256ab948 | 3938 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
3939 | { |
3940 | /* 32 bit values require an lui. */ | |
67c0d1eb | 3941 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 3942 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 3943 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
3944 | return; |
3945 | } | |
3946 | } | |
3947 | ||
3948 | /* The value is larger than 32 bits. */ | |
3949 | ||
2051e8c4 | 3950 | if (!dbl || HAVE_32BIT_GPRS) |
252b5132 | 3951 | { |
55e08f71 NC |
3952 | char value[32]; |
3953 | ||
3954 | sprintf_vma (value, ep->X_add_number); | |
20e1fcfd | 3955 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
67c0d1eb | 3956 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3957 | return; |
3958 | } | |
3959 | ||
3960 | if (ep->X_op != O_big) | |
3961 | { | |
3962 | hi32 = *ep; | |
3963 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3964 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3965 | hi32.X_add_number &= 0xffffffff; | |
3966 | lo32 = *ep; | |
3967 | lo32.X_add_number &= 0xffffffff; | |
3968 | } | |
3969 | else | |
3970 | { | |
3971 | assert (ep->X_add_number > 2); | |
3972 | if (ep->X_add_number == 3) | |
3973 | generic_bignum[3] = 0; | |
3974 | else if (ep->X_add_number > 4) | |
3975 | as_bad (_("Number larger than 64 bits")); | |
3976 | lo32.X_op = O_constant; | |
3977 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
3978 | hi32.X_op = O_constant; | |
3979 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
3980 | } | |
3981 | ||
3982 | if (hi32.X_add_number == 0) | |
3983 | freg = 0; | |
3984 | else | |
3985 | { | |
3986 | int shift, bit; | |
3987 | unsigned long hi, lo; | |
3988 | ||
956cd1d6 | 3989 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
3990 | { |
3991 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
3992 | { | |
67c0d1eb | 3993 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
3994 | return; |
3995 | } | |
3996 | if (lo32.X_add_number & 0x80000000) | |
3997 | { | |
67c0d1eb | 3998 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 3999 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 4000 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
4001 | return; |
4002 | } | |
4003 | } | |
252b5132 RH |
4004 | |
4005 | /* Check for 16bit shifted constant. We know that hi32 is | |
4006 | non-zero, so start the mask on the first bit of the hi32 | |
4007 | value. */ | |
4008 | shift = 17; | |
4009 | do | |
beae10d5 KH |
4010 | { |
4011 | unsigned long himask, lomask; | |
4012 | ||
4013 | if (shift < 32) | |
4014 | { | |
4015 | himask = 0xffff >> (32 - shift); | |
4016 | lomask = (0xffff << shift) & 0xffffffff; | |
4017 | } | |
4018 | else | |
4019 | { | |
4020 | himask = 0xffff << (shift - 32); | |
4021 | lomask = 0; | |
4022 | } | |
4023 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
4024 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
4025 | { | |
4026 | expressionS tmp; | |
4027 | ||
4028 | tmp.X_op = O_constant; | |
4029 | if (shift < 32) | |
4030 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
4031 | | (lo32.X_add_number >> shift)); | |
4032 | else | |
4033 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb RS |
4034 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
4035 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<", | |
4036 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
4037 | return; |
4038 | } | |
f9419b05 | 4039 | ++shift; |
beae10d5 KH |
4040 | } |
4041 | while (shift <= (64 - 16)); | |
252b5132 RH |
4042 | |
4043 | /* Find the bit number of the lowest one bit, and store the | |
4044 | shifted value in hi/lo. */ | |
4045 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
4046 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
4047 | if (lo != 0) | |
4048 | { | |
4049 | bit = 0; | |
4050 | while ((lo & 1) == 0) | |
4051 | { | |
4052 | lo >>= 1; | |
4053 | ++bit; | |
4054 | } | |
4055 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
4056 | hi >>= bit; | |
4057 | } | |
4058 | else | |
4059 | { | |
4060 | bit = 32; | |
4061 | while ((hi & 1) == 0) | |
4062 | { | |
4063 | hi >>= 1; | |
4064 | ++bit; | |
4065 | } | |
4066 | lo = hi; | |
4067 | hi = 0; | |
4068 | } | |
4069 | ||
4070 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
4071 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
4072 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
4073 | { |
4074 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 4075 | if (shift != 0) |
beae10d5 | 4076 | { |
252b5132 RH |
4077 | expressionS tmp; |
4078 | ||
4079 | /* This instruction will set the register to be all | |
4080 | ones. */ | |
beae10d5 KH |
4081 | tmp.X_op = O_constant; |
4082 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 4083 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
4084 | if (bit != 0) |
4085 | { | |
4086 | bit += shift; | |
67c0d1eb RS |
4087 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<", |
4088 | reg, reg, (bit >= 32) ? bit - 32 : bit); | |
beae10d5 | 4089 | } |
67c0d1eb RS |
4090 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<", |
4091 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
4092 | return; |
4093 | } | |
4094 | } | |
252b5132 RH |
4095 | |
4096 | /* Sign extend hi32 before calling load_register, because we can | |
4097 | generally get better code when we load a sign extended value. */ | |
4098 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 4099 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 4100 | load_register (reg, &hi32, 0); |
252b5132 RH |
4101 | freg = reg; |
4102 | } | |
4103 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
4104 | { | |
4105 | if (freg != 0) | |
4106 | { | |
67c0d1eb | 4107 | macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0); |
252b5132 RH |
4108 | freg = reg; |
4109 | } | |
4110 | } | |
4111 | else | |
4112 | { | |
4113 | expressionS mid16; | |
4114 | ||
956cd1d6 | 4115 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 4116 | { |
67c0d1eb RS |
4117 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
4118 | macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0); | |
beae10d5 KH |
4119 | return; |
4120 | } | |
252b5132 RH |
4121 | |
4122 | if (freg != 0) | |
4123 | { | |
67c0d1eb | 4124 | macro_build (NULL, "dsll", "d,w,<", reg, freg, 16); |
252b5132 RH |
4125 | freg = reg; |
4126 | } | |
4127 | mid16 = lo32; | |
4128 | mid16.X_add_number >>= 16; | |
67c0d1eb RS |
4129 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
4130 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
252b5132 RH |
4131 | freg = reg; |
4132 | } | |
4133 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 4134 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
4135 | } |
4136 | ||
269137b2 TS |
4137 | static inline void |
4138 | load_delay_nop (void) | |
4139 | { | |
4140 | if (!gpr_interlocks) | |
4141 | macro_build (NULL, "nop", ""); | |
4142 | } | |
4143 | ||
252b5132 RH |
4144 | /* Load an address into a register. */ |
4145 | ||
4146 | static void | |
67c0d1eb | 4147 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 4148 | { |
252b5132 RH |
4149 | if (ep->X_op != O_constant |
4150 | && ep->X_op != O_symbol) | |
4151 | { | |
4152 | as_bad (_("expression too complex")); | |
4153 | ep->X_op = O_constant; | |
4154 | } | |
4155 | ||
4156 | if (ep->X_op == O_constant) | |
4157 | { | |
67c0d1eb | 4158 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
4159 | return; |
4160 | } | |
4161 | ||
4162 | if (mips_pic == NO_PIC) | |
4163 | { | |
4164 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 4165 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
4166 | Otherwise we want |
4167 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
4168 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 4169 | If we have an addend, we always use the latter form. |
76b3015f | 4170 | |
d6bc6245 TS |
4171 | With 64bit address space and a usable $at we want |
4172 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4173 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
4174 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4175 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
4176 | dsll32 $reg,0 | |
3a482fd5 | 4177 | daddu $reg,$reg,$at |
76b3015f | 4178 | |
c03099e6 | 4179 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
4180 | on superscalar processors. |
4181 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4182 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4183 | dsll $reg,16 | |
4184 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
4185 | dsll $reg,16 | |
4186 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
6caf9ef4 TS |
4187 | |
4188 | For GP relative symbols in 64bit address space we can use | |
4189 | the same sequence as in 32bit address space. */ | |
aed1a261 | 4190 | if (HAVE_64BIT_SYMBOLS) |
d6bc6245 | 4191 | { |
6caf9ef4 TS |
4192 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
4193 | && !nopic_need_relax (ep->X_add_symbol, 1)) | |
4194 | { | |
4195 | relax_start (ep->X_add_symbol); | |
4196 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
4197 | mips_gp_register, BFD_RELOC_GPREL16); | |
4198 | relax_switch (); | |
4199 | } | |
d6bc6245 | 4200 | |
b8285c27 | 4201 | if (*used_at == 0 && !mips_opts.noat) |
d6bc6245 | 4202 | { |
67c0d1eb RS |
4203 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
4204 | macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S); | |
4205 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
4206 | BFD_RELOC_MIPS_HIGHER); | |
4207 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
4208 | macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0); | |
4209 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); | |
d6bc6245 TS |
4210 | *used_at = 1; |
4211 | } | |
4212 | else | |
4213 | { | |
67c0d1eb RS |
4214 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
4215 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
4216 | BFD_RELOC_MIPS_HIGHER); | |
4217 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
4218 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); | |
4219 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
4220 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); | |
d6bc6245 | 4221 | } |
6caf9ef4 TS |
4222 | |
4223 | if (mips_relax.sequence) | |
4224 | relax_end (); | |
d6bc6245 | 4225 | } |
252b5132 RH |
4226 | else |
4227 | { | |
d6bc6245 | 4228 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 4229 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
d6bc6245 | 4230 | { |
4d7206a2 | 4231 | relax_start (ep->X_add_symbol); |
67c0d1eb | 4232 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 4233 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 4234 | relax_switch (); |
d6bc6245 | 4235 | } |
67c0d1eb RS |
4236 | macro_build_lui (ep, reg); |
4237 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
4238 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
4239 | if (mips_relax.sequence) |
4240 | relax_end (); | |
d6bc6245 | 4241 | } |
252b5132 | 4242 | } |
0a44bf69 | 4243 | else if (!mips_big_got) |
252b5132 RH |
4244 | { |
4245 | expressionS ex; | |
4246 | ||
4247 | /* If this is a reference to an external symbol, we want | |
4248 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4249 | Otherwise we want | |
4250 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4251 | nop | |
4252 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
4253 | If there is a constant, it must be added in after. |
4254 | ||
ed6fb7bd | 4255 | If we have NewABI, we want |
f5040a92 AO |
4256 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
4257 | unless we're referencing a global symbol with a non-zero | |
4258 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
4259 | if (HAVE_NEWABI) |
4260 | { | |
f5040a92 AO |
4261 | if (ep->X_add_number) |
4262 | { | |
4d7206a2 | 4263 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 4264 | ep->X_add_number = 0; |
4d7206a2 | 4265 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4266 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
4267 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
4268 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
4269 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4270 | ex.X_op = O_constant; | |
67c0d1eb | 4271 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 4272 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 4273 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 4274 | relax_switch (); |
f5040a92 | 4275 | } |
67c0d1eb | 4276 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4277 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
4278 | if (mips_relax.sequence) |
4279 | relax_end (); | |
ed6fb7bd SC |
4280 | } |
4281 | else | |
4282 | { | |
f5040a92 AO |
4283 | ex.X_add_number = ep->X_add_number; |
4284 | ep->X_add_number = 0; | |
67c0d1eb RS |
4285 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
4286 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 4287 | load_delay_nop (); |
4d7206a2 RS |
4288 | relax_start (ep->X_add_symbol); |
4289 | relax_switch (); | |
67c0d1eb | 4290 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 4291 | BFD_RELOC_LO16); |
4d7206a2 | 4292 | relax_end (); |
ed6fb7bd | 4293 | |
f5040a92 AO |
4294 | if (ex.X_add_number != 0) |
4295 | { | |
4296 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
4297 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4298 | ex.X_op = O_constant; | |
67c0d1eb | 4299 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 4300 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 4301 | } |
252b5132 RH |
4302 | } |
4303 | } | |
0a44bf69 | 4304 | else if (mips_big_got) |
252b5132 RH |
4305 | { |
4306 | expressionS ex; | |
252b5132 RH |
4307 | |
4308 | /* This is the large GOT case. If this is a reference to an | |
4309 | external symbol, we want | |
4310 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4311 | addu $reg,$reg,$gp | |
4312 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
4313 | |
4314 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
4315 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
4316 | nop | |
4317 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 4318 | If there is a constant, it must be added in after. |
f5040a92 AO |
4319 | |
4320 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
4321 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
4322 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 4323 | */ |
438c16b8 TS |
4324 | if (HAVE_NEWABI) |
4325 | { | |
4d7206a2 | 4326 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 4327 | ep->X_add_number = 0; |
4d7206a2 | 4328 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4329 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
4330 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
4331 | reg, reg, mips_gp_register); | |
4332 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
4333 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
4334 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
4335 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4336 | else if (ex.X_add_number) | |
4337 | { | |
4338 | ex.X_op = O_constant; | |
67c0d1eb RS |
4339 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4340 | BFD_RELOC_LO16); | |
f5040a92 AO |
4341 | } |
4342 | ||
4343 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 4344 | relax_switch (); |
67c0d1eb | 4345 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4346 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
4347 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4348 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 4349 | relax_end (); |
438c16b8 | 4350 | } |
252b5132 | 4351 | else |
438c16b8 | 4352 | { |
f5040a92 AO |
4353 | ex.X_add_number = ep->X_add_number; |
4354 | ep->X_add_number = 0; | |
4d7206a2 | 4355 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
4356 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
4357 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
4358 | reg, reg, mips_gp_register); | |
4359 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
4360 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
4361 | relax_switch (); |
4362 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
4363 | { |
4364 | /* We need a nop before loading from $gp. This special | |
4365 | check is required because the lui which starts the main | |
4366 | instruction stream does not refer to $gp, and so will not | |
4367 | insert the nop which may be required. */ | |
67c0d1eb | 4368 | macro_build (NULL, "nop", ""); |
438c16b8 | 4369 | } |
67c0d1eb | 4370 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 4371 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 4372 | load_delay_nop (); |
67c0d1eb | 4373 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 4374 | BFD_RELOC_LO16); |
4d7206a2 | 4375 | relax_end (); |
438c16b8 | 4376 | |
f5040a92 AO |
4377 | if (ex.X_add_number != 0) |
4378 | { | |
4379 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
4380 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4381 | ex.X_op = O_constant; | |
67c0d1eb RS |
4382 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
4383 | BFD_RELOC_LO16); | |
f5040a92 | 4384 | } |
252b5132 RH |
4385 | } |
4386 | } | |
252b5132 RH |
4387 | else |
4388 | abort (); | |
8fc2e39e TS |
4389 | |
4390 | if (mips_opts.noat && *used_at == 1) | |
4391 | as_bad (_("Macro used $at after \".set noat\"")); | |
252b5132 RH |
4392 | } |
4393 | ||
ea1fb5dc RS |
4394 | /* Move the contents of register SOURCE into register DEST. */ |
4395 | ||
4396 | static void | |
67c0d1eb | 4397 | move_register (int dest, int source) |
ea1fb5dc | 4398 | { |
67c0d1eb RS |
4399 | macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", |
4400 | dest, source, 0); | |
ea1fb5dc RS |
4401 | } |
4402 | ||
4d7206a2 | 4403 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
4404 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
4405 | The two alternatives are: | |
4d7206a2 RS |
4406 | |
4407 | Global symbol Local sybmol | |
4408 | ------------- ------------ | |
4409 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
4410 | ... ... | |
4411 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
4412 | ||
4413 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
4414 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
4415 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
4416 | |
4417 | static void | |
67c0d1eb | 4418 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4419 | { |
4420 | expressionS global; | |
4421 | ||
4422 | global = *local; | |
4423 | global.X_add_number = 0; | |
4424 | ||
4425 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
4426 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4427 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 4428 | relax_switch (); |
67c0d1eb RS |
4429 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
4430 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
4431 | relax_end (); |
4432 | } | |
4433 | ||
4434 | static void | |
67c0d1eb | 4435 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
4436 | { |
4437 | expressionS global; | |
4438 | ||
4439 | global.X_op = O_constant; | |
4440 | global.X_op_symbol = NULL; | |
4441 | global.X_add_symbol = NULL; | |
4442 | global.X_add_number = local->X_add_number; | |
4443 | ||
4444 | relax_start (local->X_add_symbol); | |
67c0d1eb | 4445 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
4446 | dest, dest, BFD_RELOC_LO16); |
4447 | relax_switch (); | |
67c0d1eb | 4448 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
4449 | relax_end (); |
4450 | } | |
4451 | ||
f6a22291 MR |
4452 | static void |
4453 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
4454 | { | |
4455 | expressionS global; | |
4456 | int hold_mips_optimize; | |
4457 | ||
4458 | global.X_op = O_constant; | |
4459 | global.X_op_symbol = NULL; | |
4460 | global.X_add_symbol = NULL; | |
4461 | global.X_add_number = local->X_add_number; | |
4462 | ||
4463 | relax_start (local->X_add_symbol); | |
4464 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
4465 | relax_switch (); | |
4466 | /* Set mips_optimize around the lui instruction to avoid | |
4467 | inserting an unnecessary nop after the lw. */ | |
4468 | hold_mips_optimize = mips_optimize; | |
4469 | mips_optimize = 2; | |
4470 | macro_build_lui (&global, tmp); | |
4471 | mips_optimize = hold_mips_optimize; | |
4472 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
4473 | relax_end (); | |
4474 | ||
4475 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
4476 | } | |
4477 | ||
252b5132 RH |
4478 | /* |
4479 | * Build macros | |
4480 | * This routine implements the seemingly endless macro or synthesized | |
4481 | * instructions and addressing modes in the mips assembly language. Many | |
4482 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 4483 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
4484 | * this verbose method. Others are not simple macros but are more like |
4485 | * optimizing code generation. | |
4486 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 4487 | * consecutively that would load AT with the upper half of the same address. |
252b5132 RH |
4488 | * The ensuing load upper instructions are ommited. This implies some kind |
4489 | * of global optimization. We currently only optimize within a single macro. | |
4490 | * For many of the load and store macros if the address is specified as a | |
4491 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
4492 | * first load register 'at' with zero and use it as the base register. The | |
4493 | * mips assembler simply uses register $zero. Just one tiny optimization | |
4494 | * we're missing. | |
4495 | */ | |
4496 | static void | |
17a2f251 | 4497 | macro (struct mips_cl_insn *ip) |
252b5132 | 4498 | { |
3994f87e | 4499 | int treg, sreg, dreg, breg; |
252b5132 RH |
4500 | int tempreg; |
4501 | int mask; | |
43841e91 | 4502 | int used_at = 0; |
252b5132 RH |
4503 | expressionS expr1; |
4504 | const char *s; | |
4505 | const char *s2; | |
4506 | const char *fmt; | |
4507 | int likely = 0; | |
4508 | int dbl = 0; | |
4509 | int coproc = 0; | |
4510 | int lr = 0; | |
4511 | int imm = 0; | |
1abe91b1 | 4512 | int call = 0; |
252b5132 | 4513 | int off; |
67c0d1eb | 4514 | offsetT maxnum; |
252b5132 | 4515 | bfd_reloc_code_real_type r; |
252b5132 RH |
4516 | int hold_mips_optimize; |
4517 | ||
4518 | assert (! mips_opts.mips16); | |
4519 | ||
4520 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
4521 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
4522 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
4523 | mask = ip->insn_mo->mask; | |
4524 | ||
4525 | expr1.X_op = O_constant; | |
4526 | expr1.X_op_symbol = NULL; | |
4527 | expr1.X_add_symbol = NULL; | |
4528 | expr1.X_add_number = 1; | |
4529 | ||
4530 | switch (mask) | |
4531 | { | |
4532 | case M_DABS: | |
4533 | dbl = 1; | |
4534 | case M_ABS: | |
4535 | /* bgez $a0,.+12 | |
4536 | move v0,$a0 | |
4537 | sub v0,$zero,$a0 | |
4538 | */ | |
4539 | ||
7d10b47d | 4540 | start_noreorder (); |
252b5132 RH |
4541 | |
4542 | expr1.X_add_number = 8; | |
67c0d1eb | 4543 | macro_build (&expr1, "bgez", "s,p", sreg); |
252b5132 | 4544 | if (dreg == sreg) |
67c0d1eb | 4545 | macro_build (NULL, "nop", "", 0); |
252b5132 | 4546 | else |
67c0d1eb RS |
4547 | move_register (dreg, sreg); |
4548 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); | |
252b5132 | 4549 | |
7d10b47d | 4550 | end_noreorder (); |
8fc2e39e | 4551 | break; |
252b5132 RH |
4552 | |
4553 | case M_ADD_I: | |
4554 | s = "addi"; | |
4555 | s2 = "add"; | |
4556 | goto do_addi; | |
4557 | case M_ADDU_I: | |
4558 | s = "addiu"; | |
4559 | s2 = "addu"; | |
4560 | goto do_addi; | |
4561 | case M_DADD_I: | |
4562 | dbl = 1; | |
4563 | s = "daddi"; | |
4564 | s2 = "dadd"; | |
4565 | goto do_addi; | |
4566 | case M_DADDU_I: | |
4567 | dbl = 1; | |
4568 | s = "daddiu"; | |
4569 | s2 = "daddu"; | |
4570 | do_addi: | |
4571 | if (imm_expr.X_op == O_constant | |
4572 | && imm_expr.X_add_number >= -0x8000 | |
4573 | && imm_expr.X_add_number < 0x8000) | |
4574 | { | |
67c0d1eb | 4575 | macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 4576 | break; |
252b5132 | 4577 | } |
8fc2e39e | 4578 | used_at = 1; |
67c0d1eb RS |
4579 | load_register (AT, &imm_expr, dbl); |
4580 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4581 | break; |
4582 | ||
4583 | case M_AND_I: | |
4584 | s = "andi"; | |
4585 | s2 = "and"; | |
4586 | goto do_bit; | |
4587 | case M_OR_I: | |
4588 | s = "ori"; | |
4589 | s2 = "or"; | |
4590 | goto do_bit; | |
4591 | case M_NOR_I: | |
4592 | s = ""; | |
4593 | s2 = "nor"; | |
4594 | goto do_bit; | |
4595 | case M_XOR_I: | |
4596 | s = "xori"; | |
4597 | s2 = "xor"; | |
4598 | do_bit: | |
4599 | if (imm_expr.X_op == O_constant | |
4600 | && imm_expr.X_add_number >= 0 | |
4601 | && imm_expr.X_add_number < 0x10000) | |
4602 | { | |
4603 | if (mask != M_NOR_I) | |
67c0d1eb | 4604 | macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
4605 | else |
4606 | { | |
67c0d1eb RS |
4607 | macro_build (&imm_expr, "ori", "t,r,i", |
4608 | treg, sreg, BFD_RELOC_LO16); | |
4609 | macro_build (NULL, "nor", "d,v,t", treg, treg, 0); | |
252b5132 | 4610 | } |
8fc2e39e | 4611 | break; |
252b5132 RH |
4612 | } |
4613 | ||
8fc2e39e | 4614 | used_at = 1; |
67c0d1eb RS |
4615 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4616 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4617 | break; |
4618 | ||
4619 | case M_BEQ_I: | |
4620 | s = "beq"; | |
4621 | goto beq_i; | |
4622 | case M_BEQL_I: | |
4623 | s = "beql"; | |
4624 | likely = 1; | |
4625 | goto beq_i; | |
4626 | case M_BNE_I: | |
4627 | s = "bne"; | |
4628 | goto beq_i; | |
4629 | case M_BNEL_I: | |
4630 | s = "bnel"; | |
4631 | likely = 1; | |
4632 | beq_i: | |
4633 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4634 | { | |
67c0d1eb | 4635 | macro_build (&offset_expr, s, "s,t,p", sreg, 0); |
8fc2e39e | 4636 | break; |
252b5132 | 4637 | } |
8fc2e39e | 4638 | used_at = 1; |
67c0d1eb RS |
4639 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4640 | macro_build (&offset_expr, s, "s,t,p", sreg, AT); | |
252b5132 RH |
4641 | break; |
4642 | ||
4643 | case M_BGEL: | |
4644 | likely = 1; | |
4645 | case M_BGE: | |
4646 | if (treg == 0) | |
4647 | { | |
67c0d1eb | 4648 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
8fc2e39e | 4649 | break; |
252b5132 RH |
4650 | } |
4651 | if (sreg == 0) | |
4652 | { | |
67c0d1eb | 4653 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg); |
8fc2e39e | 4654 | break; |
252b5132 | 4655 | } |
8fc2e39e | 4656 | used_at = 1; |
67c0d1eb RS |
4657 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
4658 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4659 | break; |
4660 | ||
4661 | case M_BGTL_I: | |
4662 | likely = 1; | |
4663 | case M_BGT_I: | |
4664 | /* check for > max integer */ | |
4665 | maxnum = 0x7fffffff; | |
ca4e0257 | 4666 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4667 | { |
4668 | maxnum <<= 16; | |
4669 | maxnum |= 0xffff; | |
4670 | maxnum <<= 16; | |
4671 | maxnum |= 0xffff; | |
4672 | } | |
4673 | if (imm_expr.X_op == O_constant | |
4674 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4675 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4676 | { |
4677 | do_false: | |
4678 | /* result is always false */ | |
4679 | if (! likely) | |
67c0d1eb | 4680 | macro_build (NULL, "nop", "", 0); |
252b5132 | 4681 | else |
67c0d1eb | 4682 | macro_build (&offset_expr, "bnel", "s,t,p", 0, 0); |
8fc2e39e | 4683 | break; |
252b5132 RH |
4684 | } |
4685 | if (imm_expr.X_op != O_constant) | |
4686 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4687 | ++imm_expr.X_add_number; |
252b5132 RH |
4688 | /* FALLTHROUGH */ |
4689 | case M_BGE_I: | |
4690 | case M_BGEL_I: | |
4691 | if (mask == M_BGEL_I) | |
4692 | likely = 1; | |
4693 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4694 | { | |
67c0d1eb | 4695 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
8fc2e39e | 4696 | break; |
252b5132 RH |
4697 | } |
4698 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4699 | { | |
67c0d1eb | 4700 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
8fc2e39e | 4701 | break; |
252b5132 RH |
4702 | } |
4703 | maxnum = 0x7fffffff; | |
ca4e0257 | 4704 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4705 | { |
4706 | maxnum <<= 16; | |
4707 | maxnum |= 0xffff; | |
4708 | maxnum <<= 16; | |
4709 | maxnum |= 0xffff; | |
4710 | } | |
4711 | maxnum = - maxnum - 1; | |
4712 | if (imm_expr.X_op == O_constant | |
4713 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 4714 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4715 | { |
4716 | do_true: | |
4717 | /* result is always true */ | |
4718 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
67c0d1eb | 4719 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 4720 | break; |
252b5132 | 4721 | } |
8fc2e39e | 4722 | used_at = 1; |
67c0d1eb RS |
4723 | set_at (sreg, 0); |
4724 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4725 | break; |
4726 | ||
4727 | case M_BGEUL: | |
4728 | likely = 1; | |
4729 | case M_BGEU: | |
4730 | if (treg == 0) | |
4731 | goto do_true; | |
4732 | if (sreg == 0) | |
4733 | { | |
67c0d1eb | 4734 | macro_build (&offset_expr, likely ? "beql" : "beq", |
17a2f251 | 4735 | "s,t,p", 0, treg); |
8fc2e39e | 4736 | break; |
252b5132 | 4737 | } |
8fc2e39e | 4738 | used_at = 1; |
67c0d1eb RS |
4739 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
4740 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4741 | break; |
4742 | ||
4743 | case M_BGTUL_I: | |
4744 | likely = 1; | |
4745 | case M_BGTU_I: | |
4746 | if (sreg == 0 | |
ca4e0257 | 4747 | || (HAVE_32BIT_GPRS |
252b5132 | 4748 | && imm_expr.X_op == O_constant |
956cd1d6 | 4749 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4750 | goto do_false; |
4751 | if (imm_expr.X_op != O_constant) | |
4752 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4753 | ++imm_expr.X_add_number; |
252b5132 RH |
4754 | /* FALLTHROUGH */ |
4755 | case M_BGEU_I: | |
4756 | case M_BGEUL_I: | |
4757 | if (mask == M_BGEUL_I) | |
4758 | likely = 1; | |
4759 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4760 | goto do_true; | |
4761 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4762 | { | |
67c0d1eb | 4763 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4764 | "s,t,p", sreg, 0); |
8fc2e39e | 4765 | break; |
252b5132 | 4766 | } |
8fc2e39e | 4767 | used_at = 1; |
67c0d1eb RS |
4768 | set_at (sreg, 1); |
4769 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4770 | break; |
4771 | ||
4772 | case M_BGTL: | |
4773 | likely = 1; | |
4774 | case M_BGT: | |
4775 | if (treg == 0) | |
4776 | { | |
67c0d1eb | 4777 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
8fc2e39e | 4778 | break; |
252b5132 RH |
4779 | } |
4780 | if (sreg == 0) | |
4781 | { | |
67c0d1eb | 4782 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg); |
8fc2e39e | 4783 | break; |
252b5132 | 4784 | } |
8fc2e39e | 4785 | used_at = 1; |
67c0d1eb RS |
4786 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
4787 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4788 | break; |
4789 | ||
4790 | case M_BGTUL: | |
4791 | likely = 1; | |
4792 | case M_BGTU: | |
4793 | if (treg == 0) | |
4794 | { | |
67c0d1eb | 4795 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4796 | "s,t,p", sreg, 0); |
8fc2e39e | 4797 | break; |
252b5132 RH |
4798 | } |
4799 | if (sreg == 0) | |
4800 | goto do_false; | |
8fc2e39e | 4801 | used_at = 1; |
67c0d1eb RS |
4802 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
4803 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4804 | break; |
4805 | ||
4806 | case M_BLEL: | |
4807 | likely = 1; | |
4808 | case M_BLE: | |
4809 | if (treg == 0) | |
4810 | { | |
67c0d1eb | 4811 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
8fc2e39e | 4812 | break; |
252b5132 RH |
4813 | } |
4814 | if (sreg == 0) | |
4815 | { | |
67c0d1eb | 4816 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg); |
8fc2e39e | 4817 | break; |
252b5132 | 4818 | } |
8fc2e39e | 4819 | used_at = 1; |
67c0d1eb RS |
4820 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
4821 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4822 | break; |
4823 | ||
4824 | case M_BLEL_I: | |
4825 | likely = 1; | |
4826 | case M_BLE_I: | |
4827 | maxnum = 0x7fffffff; | |
ca4e0257 | 4828 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4829 | { |
4830 | maxnum <<= 16; | |
4831 | maxnum |= 0xffff; | |
4832 | maxnum <<= 16; | |
4833 | maxnum |= 0xffff; | |
4834 | } | |
4835 | if (imm_expr.X_op == O_constant | |
4836 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4837 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4838 | goto do_true; |
4839 | if (imm_expr.X_op != O_constant) | |
4840 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4841 | ++imm_expr.X_add_number; |
252b5132 RH |
4842 | /* FALLTHROUGH */ |
4843 | case M_BLT_I: | |
4844 | case M_BLTL_I: | |
4845 | if (mask == M_BLTL_I) | |
4846 | likely = 1; | |
4847 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4848 | { | |
67c0d1eb | 4849 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
8fc2e39e | 4850 | break; |
252b5132 RH |
4851 | } |
4852 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4853 | { | |
67c0d1eb | 4854 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
8fc2e39e | 4855 | break; |
252b5132 | 4856 | } |
8fc2e39e | 4857 | used_at = 1; |
67c0d1eb RS |
4858 | set_at (sreg, 0); |
4859 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4860 | break; |
4861 | ||
4862 | case M_BLEUL: | |
4863 | likely = 1; | |
4864 | case M_BLEU: | |
4865 | if (treg == 0) | |
4866 | { | |
67c0d1eb | 4867 | macro_build (&offset_expr, likely ? "beql" : "beq", |
17a2f251 | 4868 | "s,t,p", sreg, 0); |
8fc2e39e | 4869 | break; |
252b5132 RH |
4870 | } |
4871 | if (sreg == 0) | |
4872 | goto do_true; | |
8fc2e39e | 4873 | used_at = 1; |
67c0d1eb RS |
4874 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
4875 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4876 | break; |
4877 | ||
4878 | case M_BLEUL_I: | |
4879 | likely = 1; | |
4880 | case M_BLEU_I: | |
4881 | if (sreg == 0 | |
ca4e0257 | 4882 | || (HAVE_32BIT_GPRS |
252b5132 | 4883 | && imm_expr.X_op == O_constant |
956cd1d6 | 4884 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4885 | goto do_true; |
4886 | if (imm_expr.X_op != O_constant) | |
4887 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4888 | ++imm_expr.X_add_number; |
252b5132 RH |
4889 | /* FALLTHROUGH */ |
4890 | case M_BLTU_I: | |
4891 | case M_BLTUL_I: | |
4892 | if (mask == M_BLTUL_I) | |
4893 | likely = 1; | |
4894 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4895 | goto do_false; | |
4896 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4897 | { | |
67c0d1eb | 4898 | macro_build (&offset_expr, likely ? "beql" : "beq", |
252b5132 | 4899 | "s,t,p", sreg, 0); |
8fc2e39e | 4900 | break; |
252b5132 | 4901 | } |
8fc2e39e | 4902 | used_at = 1; |
67c0d1eb RS |
4903 | set_at (sreg, 1); |
4904 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4905 | break; |
4906 | ||
4907 | case M_BLTL: | |
4908 | likely = 1; | |
4909 | case M_BLT: | |
4910 | if (treg == 0) | |
4911 | { | |
67c0d1eb | 4912 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
8fc2e39e | 4913 | break; |
252b5132 RH |
4914 | } |
4915 | if (sreg == 0) | |
4916 | { | |
67c0d1eb | 4917 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg); |
8fc2e39e | 4918 | break; |
252b5132 | 4919 | } |
8fc2e39e | 4920 | used_at = 1; |
67c0d1eb RS |
4921 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
4922 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4923 | break; |
4924 | ||
4925 | case M_BLTUL: | |
4926 | likely = 1; | |
4927 | case M_BLTU: | |
4928 | if (treg == 0) | |
4929 | goto do_false; | |
4930 | if (sreg == 0) | |
4931 | { | |
67c0d1eb | 4932 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4933 | "s,t,p", 0, treg); |
8fc2e39e | 4934 | break; |
252b5132 | 4935 | } |
8fc2e39e | 4936 | used_at = 1; |
67c0d1eb RS |
4937 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
4938 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4939 | break; |
4940 | ||
5f74bc13 CD |
4941 | case M_DEXT: |
4942 | { | |
4943 | unsigned long pos; | |
4944 | unsigned long size; | |
4945 | ||
4946 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
4947 | { | |
4948 | as_bad (_("Unsupported large constant")); | |
4949 | pos = size = 1; | |
4950 | } | |
4951 | else | |
4952 | { | |
4953 | pos = (unsigned long) imm_expr.X_add_number; | |
4954 | size = (unsigned long) imm2_expr.X_add_number; | |
4955 | } | |
4956 | ||
4957 | if (pos > 63) | |
4958 | { | |
4959 | as_bad (_("Improper position (%lu)"), pos); | |
4960 | pos = 1; | |
4961 | } | |
4962 | if (size == 0 || size > 64 | |
4963 | || (pos + size - 1) > 63) | |
4964 | { | |
4965 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
4966 | size, pos); | |
4967 | size = 1; | |
4968 | } | |
4969 | ||
4970 | if (size <= 32 && pos < 32) | |
4971 | { | |
4972 | s = "dext"; | |
4973 | fmt = "t,r,+A,+C"; | |
4974 | } | |
4975 | else if (size <= 32) | |
4976 | { | |
4977 | s = "dextu"; | |
4978 | fmt = "t,r,+E,+H"; | |
4979 | } | |
4980 | else | |
4981 | { | |
4982 | s = "dextm"; | |
4983 | fmt = "t,r,+A,+G"; | |
4984 | } | |
67c0d1eb | 4985 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, size - 1); |
5f74bc13 | 4986 | } |
8fc2e39e | 4987 | break; |
5f74bc13 CD |
4988 | |
4989 | case M_DINS: | |
4990 | { | |
4991 | unsigned long pos; | |
4992 | unsigned long size; | |
4993 | ||
4994 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
4995 | { | |
4996 | as_bad (_("Unsupported large constant")); | |
4997 | pos = size = 1; | |
4998 | } | |
4999 | else | |
5000 | { | |
5001 | pos = (unsigned long) imm_expr.X_add_number; | |
5002 | size = (unsigned long) imm2_expr.X_add_number; | |
5003 | } | |
5004 | ||
5005 | if (pos > 63) | |
5006 | { | |
5007 | as_bad (_("Improper position (%lu)"), pos); | |
5008 | pos = 1; | |
5009 | } | |
5010 | if (size == 0 || size > 64 | |
5011 | || (pos + size - 1) > 63) | |
5012 | { | |
5013 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
5014 | size, pos); | |
5015 | size = 1; | |
5016 | } | |
5017 | ||
5018 | if (pos < 32 && (pos + size - 1) < 32) | |
5019 | { | |
5020 | s = "dins"; | |
5021 | fmt = "t,r,+A,+B"; | |
5022 | } | |
5023 | else if (pos >= 32) | |
5024 | { | |
5025 | s = "dinsu"; | |
5026 | fmt = "t,r,+E,+F"; | |
5027 | } | |
5028 | else | |
5029 | { | |
5030 | s = "dinsm"; | |
5031 | fmt = "t,r,+A,+F"; | |
5032 | } | |
67c0d1eb RS |
5033 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, |
5034 | pos + size - 1); | |
5f74bc13 | 5035 | } |
8fc2e39e | 5036 | break; |
5f74bc13 | 5037 | |
252b5132 RH |
5038 | case M_DDIV_3: |
5039 | dbl = 1; | |
5040 | case M_DIV_3: | |
5041 | s = "mflo"; | |
5042 | goto do_div3; | |
5043 | case M_DREM_3: | |
5044 | dbl = 1; | |
5045 | case M_REM_3: | |
5046 | s = "mfhi"; | |
5047 | do_div3: | |
5048 | if (treg == 0) | |
5049 | { | |
5050 | as_warn (_("Divide by zero.")); | |
5051 | if (mips_trap) | |
67c0d1eb | 5052 | macro_build (NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 5053 | else |
67c0d1eb | 5054 | macro_build (NULL, "break", "c", 7); |
8fc2e39e | 5055 | break; |
252b5132 RH |
5056 | } |
5057 | ||
7d10b47d | 5058 | start_noreorder (); |
252b5132 RH |
5059 | if (mips_trap) |
5060 | { | |
67c0d1eb RS |
5061 | macro_build (NULL, "teq", "s,t,q", treg, 0, 7); |
5062 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); | |
252b5132 RH |
5063 | } |
5064 | else | |
5065 | { | |
5066 | expr1.X_add_number = 8; | |
67c0d1eb RS |
5067 | macro_build (&expr1, "bne", "s,t,p", treg, 0); |
5068 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); | |
5069 | macro_build (NULL, "break", "c", 7); | |
252b5132 RH |
5070 | } |
5071 | expr1.X_add_number = -1; | |
8fc2e39e | 5072 | used_at = 1; |
f6a22291 | 5073 | load_register (AT, &expr1, dbl); |
252b5132 | 5074 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
67c0d1eb | 5075 | macro_build (&expr1, "bne", "s,t,p", treg, AT); |
252b5132 RH |
5076 | if (dbl) |
5077 | { | |
5078 | expr1.X_add_number = 1; | |
f6a22291 | 5079 | load_register (AT, &expr1, dbl); |
67c0d1eb | 5080 | macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31); |
252b5132 RH |
5081 | } |
5082 | else | |
5083 | { | |
5084 | expr1.X_add_number = 0x80000000; | |
67c0d1eb | 5085 | macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16); |
252b5132 RH |
5086 | } |
5087 | if (mips_trap) | |
5088 | { | |
67c0d1eb | 5089 | macro_build (NULL, "teq", "s,t,q", sreg, AT, 6); |
252b5132 RH |
5090 | /* We want to close the noreorder block as soon as possible, so |
5091 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5092 | end_noreorder (); |
252b5132 RH |
5093 | } |
5094 | else | |
5095 | { | |
5096 | expr1.X_add_number = 8; | |
67c0d1eb RS |
5097 | macro_build (&expr1, "bne", "s,t,p", sreg, AT); |
5098 | macro_build (NULL, "nop", "", 0); | |
252b5132 RH |
5099 | |
5100 | /* We want to close the noreorder block as soon as possible, so | |
5101 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5102 | end_noreorder (); |
252b5132 | 5103 | |
67c0d1eb | 5104 | macro_build (NULL, "break", "c", 6); |
252b5132 | 5105 | } |
67c0d1eb | 5106 | macro_build (NULL, s, "d", dreg); |
252b5132 RH |
5107 | break; |
5108 | ||
5109 | case M_DIV_3I: | |
5110 | s = "div"; | |
5111 | s2 = "mflo"; | |
5112 | goto do_divi; | |
5113 | case M_DIVU_3I: | |
5114 | s = "divu"; | |
5115 | s2 = "mflo"; | |
5116 | goto do_divi; | |
5117 | case M_REM_3I: | |
5118 | s = "div"; | |
5119 | s2 = "mfhi"; | |
5120 | goto do_divi; | |
5121 | case M_REMU_3I: | |
5122 | s = "divu"; | |
5123 | s2 = "mfhi"; | |
5124 | goto do_divi; | |
5125 | case M_DDIV_3I: | |
5126 | dbl = 1; | |
5127 | s = "ddiv"; | |
5128 | s2 = "mflo"; | |
5129 | goto do_divi; | |
5130 | case M_DDIVU_3I: | |
5131 | dbl = 1; | |
5132 | s = "ddivu"; | |
5133 | s2 = "mflo"; | |
5134 | goto do_divi; | |
5135 | case M_DREM_3I: | |
5136 | dbl = 1; | |
5137 | s = "ddiv"; | |
5138 | s2 = "mfhi"; | |
5139 | goto do_divi; | |
5140 | case M_DREMU_3I: | |
5141 | dbl = 1; | |
5142 | s = "ddivu"; | |
5143 | s2 = "mfhi"; | |
5144 | do_divi: | |
5145 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
5146 | { | |
5147 | as_warn (_("Divide by zero.")); | |
5148 | if (mips_trap) | |
67c0d1eb | 5149 | macro_build (NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 5150 | else |
67c0d1eb | 5151 | macro_build (NULL, "break", "c", 7); |
8fc2e39e | 5152 | break; |
252b5132 RH |
5153 | } |
5154 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
5155 | { | |
5156 | if (strcmp (s2, "mflo") == 0) | |
67c0d1eb | 5157 | move_register (dreg, sreg); |
252b5132 | 5158 | else |
67c0d1eb | 5159 | move_register (dreg, 0); |
8fc2e39e | 5160 | break; |
252b5132 RH |
5161 | } |
5162 | if (imm_expr.X_op == O_constant | |
5163 | && imm_expr.X_add_number == -1 | |
5164 | && s[strlen (s) - 1] != 'u') | |
5165 | { | |
5166 | if (strcmp (s2, "mflo") == 0) | |
5167 | { | |
67c0d1eb | 5168 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg); |
252b5132 RH |
5169 | } |
5170 | else | |
67c0d1eb | 5171 | move_register (dreg, 0); |
8fc2e39e | 5172 | break; |
252b5132 RH |
5173 | } |
5174 | ||
8fc2e39e | 5175 | used_at = 1; |
67c0d1eb RS |
5176 | load_register (AT, &imm_expr, dbl); |
5177 | macro_build (NULL, s, "z,s,t", sreg, AT); | |
5178 | macro_build (NULL, s2, "d", dreg); | |
252b5132 RH |
5179 | break; |
5180 | ||
5181 | case M_DIVU_3: | |
5182 | s = "divu"; | |
5183 | s2 = "mflo"; | |
5184 | goto do_divu3; | |
5185 | case M_REMU_3: | |
5186 | s = "divu"; | |
5187 | s2 = "mfhi"; | |
5188 | goto do_divu3; | |
5189 | case M_DDIVU_3: | |
5190 | s = "ddivu"; | |
5191 | s2 = "mflo"; | |
5192 | goto do_divu3; | |
5193 | case M_DREMU_3: | |
5194 | s = "ddivu"; | |
5195 | s2 = "mfhi"; | |
5196 | do_divu3: | |
7d10b47d | 5197 | start_noreorder (); |
252b5132 RH |
5198 | if (mips_trap) |
5199 | { | |
67c0d1eb RS |
5200 | macro_build (NULL, "teq", "s,t,q", treg, 0, 7); |
5201 | macro_build (NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
5202 | /* We want to close the noreorder block as soon as possible, so |
5203 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5204 | end_noreorder (); |
252b5132 RH |
5205 | } |
5206 | else | |
5207 | { | |
5208 | expr1.X_add_number = 8; | |
67c0d1eb RS |
5209 | macro_build (&expr1, "bne", "s,t,p", treg, 0); |
5210 | macro_build (NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
5211 | |
5212 | /* We want to close the noreorder block as soon as possible, so | |
5213 | that later insns are available for delay slot filling. */ | |
7d10b47d | 5214 | end_noreorder (); |
67c0d1eb | 5215 | macro_build (NULL, "break", "c", 7); |
252b5132 | 5216 | } |
67c0d1eb | 5217 | macro_build (NULL, s2, "d", dreg); |
8fc2e39e | 5218 | break; |
252b5132 | 5219 | |
1abe91b1 MR |
5220 | case M_DLCA_AB: |
5221 | dbl = 1; | |
5222 | case M_LCA_AB: | |
5223 | call = 1; | |
5224 | goto do_la; | |
252b5132 RH |
5225 | case M_DLA_AB: |
5226 | dbl = 1; | |
5227 | case M_LA_AB: | |
1abe91b1 | 5228 | do_la: |
252b5132 RH |
5229 | /* Load the address of a symbol into a register. If breg is not |
5230 | zero, we then add a base register to it. */ | |
5231 | ||
3bec30a8 TS |
5232 | if (dbl && HAVE_32BIT_GPRS) |
5233 | as_warn (_("dla used to load 32-bit register")); | |
5234 | ||
c90bbe5b | 5235 | if (! dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
5236 | as_warn (_("la used to load 64-bit address")); |
5237 | ||
0c11417f MR |
5238 | if (offset_expr.X_op == O_constant |
5239 | && offset_expr.X_add_number >= -0x8000 | |
5240 | && offset_expr.X_add_number < 0x8000) | |
5241 | { | |
aed1a261 | 5242 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
17a2f251 | 5243 | "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 5244 | break; |
0c11417f MR |
5245 | } |
5246 | ||
b8285c27 | 5247 | if (!mips_opts.noat && (treg == breg)) |
afdbd6d0 CD |
5248 | { |
5249 | tempreg = AT; | |
5250 | used_at = 1; | |
5251 | } | |
5252 | else | |
5253 | { | |
5254 | tempreg = treg; | |
afdbd6d0 CD |
5255 | } |
5256 | ||
252b5132 RH |
5257 | if (offset_expr.X_op != O_symbol |
5258 | && offset_expr.X_op != O_constant) | |
5259 | { | |
5260 | as_bad (_("expression too complex")); | |
5261 | offset_expr.X_op = O_constant; | |
5262 | } | |
5263 | ||
252b5132 | 5264 | if (offset_expr.X_op == O_constant) |
aed1a261 | 5265 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
5266 | else if (mips_pic == NO_PIC) |
5267 | { | |
d6bc6245 | 5268 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 5269 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
5270 | Otherwise we want |
5271 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5272 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5273 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 5274 | so we may as well always use the latter form. |
76b3015f | 5275 | |
6caf9ef4 TS |
5276 | With 64bit address space and a usable $at we want |
5277 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5278 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5279 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5280 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
5281 | dsll32 $tempreg,0 | |
5282 | daddu $tempreg,$tempreg,$at | |
5283 | ||
5284 | If $at is already in use, we use a path which is suboptimal | |
5285 | on superscalar processors. | |
5286 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5287 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5288 | dsll $tempreg,16 | |
5289 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5290 | dsll $tempreg,16 | |
5291 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
5292 | ||
5293 | For GP relative symbols in 64bit address space we can use | |
5294 | the same sequence as in 32bit address space. */ | |
aed1a261 | 5295 | if (HAVE_64BIT_SYMBOLS) |
252b5132 | 5296 | { |
6caf9ef4 TS |
5297 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
5298 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
5299 | { | |
5300 | relax_start (offset_expr.X_add_symbol); | |
5301 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5302 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
5303 | relax_switch (); | |
5304 | } | |
d6bc6245 | 5305 | |
b8285c27 | 5306 | if (used_at == 0 && !mips_opts.noat) |
98d3f06f | 5307 | { |
67c0d1eb | 5308 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 5309 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 5310 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 5311 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 5312 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5313 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 5314 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5315 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb RS |
5316 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); |
5317 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
98d3f06f KH |
5318 | used_at = 1; |
5319 | } | |
5320 | else | |
5321 | { | |
67c0d1eb | 5322 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 5323 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 5324 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 5325 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb RS |
5326 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
5327 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 5328 | tempreg, tempreg, BFD_RELOC_HI16_S); |
67c0d1eb RS |
5329 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
5330 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 5331 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 5332 | } |
6caf9ef4 TS |
5333 | |
5334 | if (mips_relax.sequence) | |
5335 | relax_end (); | |
98d3f06f KH |
5336 | } |
5337 | else | |
5338 | { | |
5339 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 5340 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
98d3f06f | 5341 | { |
4d7206a2 | 5342 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5343 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5344 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 5345 | relax_switch (); |
98d3f06f | 5346 | } |
6943caf0 ILT |
5347 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
5348 | as_bad (_("offset too large")); | |
67c0d1eb RS |
5349 | macro_build_lui (&offset_expr, tempreg); |
5350 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5351 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
5352 | if (mips_relax.sequence) |
5353 | relax_end (); | |
98d3f06f | 5354 | } |
252b5132 | 5355 | } |
0a44bf69 | 5356 | else if (!mips_big_got && !HAVE_NEWABI) |
252b5132 | 5357 | { |
9117d219 NC |
5358 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
5359 | ||
252b5132 RH |
5360 | /* If this is a reference to an external symbol, and there |
5361 | is no constant, we want | |
5362 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 5363 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 5364 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
5365 | For a local symbol, we want |
5366 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5367 | nop | |
5368 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5369 | ||
5370 | If we have a small constant, and this is a reference to | |
5371 | an external symbol, we want | |
5372 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5373 | nop | |
5374 | addiu $tempreg,$tempreg,<constant> | |
5375 | For a local symbol, we want the same instruction | |
5376 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
5377 | addiu instruction. | |
5378 | ||
5379 | If we have a large constant, and this is a reference to | |
5380 | an external symbol, we want | |
5381 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5382 | lui $at,<hiconstant> | |
5383 | addiu $at,$at,<loconstant> | |
5384 | addu $tempreg,$tempreg,$at | |
5385 | For a local symbol, we want the same instruction | |
5386 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 5387 | addiu instruction. |
ed6fb7bd SC |
5388 | */ |
5389 | ||
4d7206a2 | 5390 | if (offset_expr.X_add_number == 0) |
252b5132 | 5391 | { |
0a44bf69 RS |
5392 | if (mips_pic == SVR4_PIC |
5393 | && breg == 0 | |
5394 | && (call || tempreg == PIC_CALL_REG)) | |
4d7206a2 RS |
5395 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; |
5396 | ||
5397 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
5398 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5399 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 5400 | if (breg != 0) |
252b5132 RH |
5401 | { |
5402 | /* We're going to put in an addu instruction using | |
5403 | tempreg, so we may as well insert the nop right | |
5404 | now. */ | |
269137b2 | 5405 | load_delay_nop (); |
252b5132 | 5406 | } |
4d7206a2 | 5407 | relax_switch (); |
67c0d1eb RS |
5408 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5409 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 5410 | load_delay_nop (); |
67c0d1eb RS |
5411 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5412 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 5413 | relax_end (); |
252b5132 RH |
5414 | /* FIXME: If breg == 0, and the next instruction uses |
5415 | $tempreg, then if this variant case is used an extra | |
5416 | nop will be generated. */ | |
5417 | } | |
4d7206a2 RS |
5418 | else if (offset_expr.X_add_number >= -0x8000 |
5419 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 5420 | { |
67c0d1eb | 5421 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 5422 | load_delay_nop (); |
67c0d1eb | 5423 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
5424 | } |
5425 | else | |
5426 | { | |
4d7206a2 RS |
5427 | expr1.X_add_number = offset_expr.X_add_number; |
5428 | offset_expr.X_add_number = | |
5429 | ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
67c0d1eb | 5430 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 5431 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
5432 | /* If we are going to add in a base register, and the |
5433 | target register and the base register are the same, | |
5434 | then we are using AT as a temporary register. Since | |
5435 | we want to load the constant into AT, we add our | |
5436 | current AT (from the global offset table) and the | |
5437 | register into the register now, and pretend we were | |
5438 | not using a base register. */ | |
67c0d1eb | 5439 | if (breg == treg) |
252b5132 | 5440 | { |
269137b2 | 5441 | load_delay_nop (); |
67c0d1eb | 5442 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5443 | treg, AT, breg); |
252b5132 RH |
5444 | breg = 0; |
5445 | tempreg = treg; | |
252b5132 | 5446 | } |
f6a22291 | 5447 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
5448 | used_at = 1; |
5449 | } | |
5450 | } | |
0a44bf69 | 5451 | else if (!mips_big_got && HAVE_NEWABI) |
f5040a92 | 5452 | { |
67c0d1eb | 5453 | int add_breg_early = 0; |
f5040a92 AO |
5454 | |
5455 | /* If this is a reference to an external, and there is no | |
5456 | constant, or local symbol (*), with or without a | |
5457 | constant, we want | |
5458 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 5459 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5460 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
5461 | ||
5462 | If we have a small constant, and this is a reference to | |
5463 | an external symbol, we want | |
5464 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5465 | addiu $tempreg,$tempreg,<constant> | |
5466 | ||
5467 | If we have a large constant, and this is a reference to | |
5468 | an external symbol, we want | |
5469 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5470 | lui $at,<hiconstant> | |
5471 | addiu $at,$at,<loconstant> | |
5472 | addu $tempreg,$tempreg,$at | |
5473 | ||
5474 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
5475 | local symbols, even though it introduces an additional | |
5476 | instruction. */ | |
5477 | ||
f5040a92 AO |
5478 | if (offset_expr.X_add_number) |
5479 | { | |
4d7206a2 | 5480 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5481 | offset_expr.X_add_number = 0; |
5482 | ||
4d7206a2 | 5483 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5484 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5485 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5486 | |
5487 | if (expr1.X_add_number >= -0x8000 | |
5488 | && expr1.X_add_number < 0x8000) | |
5489 | { | |
67c0d1eb RS |
5490 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
5491 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 5492 | } |
ecd13cd3 | 5493 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 AO |
5494 | { |
5495 | int dreg; | |
5496 | ||
5497 | /* If we are going to add in a base register, and the | |
5498 | target register and the base register are the same, | |
5499 | then we are using AT as a temporary register. Since | |
5500 | we want to load the constant into AT, we add our | |
5501 | current AT (from the global offset table) and the | |
5502 | register into the register now, and pretend we were | |
5503 | not using a base register. */ | |
5504 | if (breg != treg) | |
5505 | dreg = tempreg; | |
5506 | else | |
5507 | { | |
5508 | assert (tempreg == AT); | |
67c0d1eb RS |
5509 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
5510 | treg, AT, breg); | |
f5040a92 | 5511 | dreg = treg; |
67c0d1eb | 5512 | add_breg_early = 1; |
f5040a92 AO |
5513 | } |
5514 | ||
f6a22291 | 5515 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5516 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5517 | dreg, dreg, AT); |
f5040a92 | 5518 | |
f5040a92 AO |
5519 | used_at = 1; |
5520 | } | |
5521 | else | |
5522 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5523 | ||
4d7206a2 | 5524 | relax_switch (); |
f5040a92 AO |
5525 | offset_expr.X_add_number = expr1.X_add_number; |
5526 | ||
67c0d1eb RS |
5527 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5528 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
5529 | if (add_breg_early) | |
f5040a92 | 5530 | { |
67c0d1eb | 5531 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
f899b4b8 | 5532 | treg, tempreg, breg); |
f5040a92 AO |
5533 | breg = 0; |
5534 | tempreg = treg; | |
5535 | } | |
4d7206a2 | 5536 | relax_end (); |
f5040a92 | 5537 | } |
4d7206a2 | 5538 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 5539 | { |
4d7206a2 | 5540 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5541 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5542 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 5543 | relax_switch (); |
67c0d1eb RS |
5544 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5545 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 5546 | relax_end (); |
f5040a92 | 5547 | } |
4d7206a2 | 5548 | else |
f5040a92 | 5549 | { |
67c0d1eb RS |
5550 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5551 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5552 | } |
5553 | } | |
0a44bf69 | 5554 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 5555 | { |
67c0d1eb | 5556 | int gpdelay; |
9117d219 NC |
5557 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5558 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 5559 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
5560 | |
5561 | /* This is the large GOT case. If this is a reference to an | |
5562 | external symbol, and there is no constant, we want | |
5563 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5564 | addu $tempreg,$tempreg,$gp | |
5565 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5566 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
5567 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5568 | addu $tempreg,$tempreg,$gp | |
5569 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
5570 | For a local symbol, we want |
5571 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5572 | nop | |
5573 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5574 | ||
5575 | If we have a small constant, and this is a reference to | |
5576 | an external symbol, we want | |
5577 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5578 | addu $tempreg,$tempreg,$gp | |
5579 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5580 | nop | |
5581 | addiu $tempreg,$tempreg,<constant> | |
5582 | For a local symbol, we want | |
5583 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5584 | nop | |
5585 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
5586 | ||
5587 | If we have a large constant, and this is a reference to | |
5588 | an external symbol, we want | |
5589 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5590 | addu $tempreg,$tempreg,$gp | |
5591 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5592 | lui $at,<hiconstant> | |
5593 | addiu $at,$at,<loconstant> | |
5594 | addu $tempreg,$tempreg,$at | |
5595 | For a local symbol, we want | |
5596 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5597 | lui $at,<hiconstant> | |
5598 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
5599 | addu $tempreg,$tempreg,$at | |
f5040a92 | 5600 | */ |
438c16b8 | 5601 | |
252b5132 RH |
5602 | expr1.X_add_number = offset_expr.X_add_number; |
5603 | offset_expr.X_add_number = 0; | |
4d7206a2 | 5604 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 5605 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
5606 | if (expr1.X_add_number == 0 && breg == 0 |
5607 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
5608 | { |
5609 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5610 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5611 | } | |
67c0d1eb RS |
5612 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
5613 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5614 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 5615 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 5616 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
5617 | if (expr1.X_add_number == 0) |
5618 | { | |
67c0d1eb | 5619 | if (breg != 0) |
252b5132 RH |
5620 | { |
5621 | /* We're going to put in an addu instruction using | |
5622 | tempreg, so we may as well insert the nop right | |
5623 | now. */ | |
269137b2 | 5624 | load_delay_nop (); |
252b5132 | 5625 | } |
252b5132 RH |
5626 | } |
5627 | else if (expr1.X_add_number >= -0x8000 | |
5628 | && expr1.X_add_number < 0x8000) | |
5629 | { | |
269137b2 | 5630 | load_delay_nop (); |
67c0d1eb | 5631 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5632 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
5633 | } |
5634 | else | |
5635 | { | |
67c0d1eb | 5636 | int dreg; |
252b5132 RH |
5637 | |
5638 | /* If we are going to add in a base register, and the | |
5639 | target register and the base register are the same, | |
5640 | then we are using AT as a temporary register. Since | |
5641 | we want to load the constant into AT, we add our | |
5642 | current AT (from the global offset table) and the | |
5643 | register into the register now, and pretend we were | |
5644 | not using a base register. */ | |
5645 | if (breg != treg) | |
67c0d1eb | 5646 | dreg = tempreg; |
252b5132 RH |
5647 | else |
5648 | { | |
5649 | assert (tempreg == AT); | |
269137b2 | 5650 | load_delay_nop (); |
67c0d1eb | 5651 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5652 | treg, AT, breg); |
252b5132 | 5653 | dreg = treg; |
252b5132 RH |
5654 | } |
5655 | ||
f6a22291 | 5656 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5657 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 5658 | |
252b5132 RH |
5659 | used_at = 1; |
5660 | } | |
4d7206a2 RS |
5661 | offset_expr.X_add_number = |
5662 | ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
5663 | relax_switch (); | |
252b5132 | 5664 | |
67c0d1eb | 5665 | if (gpdelay) |
252b5132 RH |
5666 | { |
5667 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 5668 | the first instruction on the main stream does not. */ |
67c0d1eb | 5669 | macro_build (NULL, "nop", ""); |
252b5132 | 5670 | } |
ed6fb7bd | 5671 | |
67c0d1eb RS |
5672 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5673 | local_reloc_type, mips_gp_register); | |
f5040a92 | 5674 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
5675 | && expr1.X_add_number < 0x8000) |
5676 | { | |
269137b2 | 5677 | load_delay_nop (); |
67c0d1eb RS |
5678 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5679 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 5680 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
5681 | register, the external symbol case ended with a load, |
5682 | so if the symbol turns out to not be external, and | |
5683 | the next instruction uses tempreg, an unnecessary nop | |
5684 | will be inserted. */ | |
252b5132 RH |
5685 | } |
5686 | else | |
5687 | { | |
5688 | if (breg == treg) | |
5689 | { | |
5690 | /* We must add in the base register now, as in the | |
f5040a92 | 5691 | external symbol case. */ |
252b5132 | 5692 | assert (tempreg == AT); |
269137b2 | 5693 | load_delay_nop (); |
67c0d1eb | 5694 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5695 | treg, AT, breg); |
252b5132 RH |
5696 | tempreg = treg; |
5697 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 5698 | it in in both cases. */ |
252b5132 RH |
5699 | breg = 0; |
5700 | } | |
5701 | ||
67c0d1eb RS |
5702 | macro_build_lui (&expr1, AT); |
5703 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 5704 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 5705 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5706 | tempreg, tempreg, AT); |
8fc2e39e | 5707 | used_at = 1; |
252b5132 | 5708 | } |
4d7206a2 | 5709 | relax_end (); |
252b5132 | 5710 | } |
0a44bf69 | 5711 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 5712 | { |
f5040a92 AO |
5713 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5714 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 5715 | int add_breg_early = 0; |
f5040a92 AO |
5716 | |
5717 | /* This is the large GOT case. If this is a reference to an | |
5718 | external symbol, and there is no constant, we want | |
5719 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5720 | add $tempreg,$tempreg,$gp | |
5721 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5722 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5723 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5724 | add $tempreg,$tempreg,$gp | |
5725 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
5726 | ||
5727 | If we have a small constant, and this is a reference to | |
5728 | an external symbol, we want | |
5729 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5730 | add $tempreg,$tempreg,$gp | |
5731 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5732 | addi $tempreg,$tempreg,<constant> | |
5733 | ||
5734 | If we have a large constant, and this is a reference to | |
5735 | an external symbol, we want | |
5736 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5737 | addu $tempreg,$tempreg,$gp | |
5738 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5739 | lui $at,<hiconstant> | |
5740 | addi $at,$at,<loconstant> | |
5741 | add $tempreg,$tempreg,$at | |
5742 | ||
5743 | If we have NewABI, and we know it's a local symbol, we want | |
5744 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
5745 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
5746 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
5747 | ||
4d7206a2 | 5748 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 5749 | |
4d7206a2 | 5750 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5751 | offset_expr.X_add_number = 0; |
5752 | ||
1abe91b1 MR |
5753 | if (expr1.X_add_number == 0 && breg == 0 |
5754 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
5755 | { |
5756 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5757 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5758 | } | |
67c0d1eb RS |
5759 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
5760 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5761 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
5762 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5763 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
5764 | |
5765 | if (expr1.X_add_number == 0) | |
4d7206a2 | 5766 | ; |
f5040a92 AO |
5767 | else if (expr1.X_add_number >= -0x8000 |
5768 | && expr1.X_add_number < 0x8000) | |
5769 | { | |
67c0d1eb | 5770 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5771 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 5772 | } |
ecd13cd3 | 5773 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 AO |
5774 | { |
5775 | int dreg; | |
5776 | ||
5777 | /* If we are going to add in a base register, and the | |
5778 | target register and the base register are the same, | |
5779 | then we are using AT as a temporary register. Since | |
5780 | we want to load the constant into AT, we add our | |
5781 | current AT (from the global offset table) and the | |
5782 | register into the register now, and pretend we were | |
5783 | not using a base register. */ | |
5784 | if (breg != treg) | |
5785 | dreg = tempreg; | |
5786 | else | |
5787 | { | |
5788 | assert (tempreg == AT); | |
67c0d1eb | 5789 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5790 | treg, AT, breg); |
f5040a92 | 5791 | dreg = treg; |
67c0d1eb | 5792 | add_breg_early = 1; |
f5040a92 AO |
5793 | } |
5794 | ||
f6a22291 | 5795 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5796 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 5797 | |
f5040a92 AO |
5798 | used_at = 1; |
5799 | } | |
5800 | else | |
5801 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5802 | ||
4d7206a2 | 5803 | relax_switch (); |
f5040a92 | 5804 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
5805 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5806 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
5807 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
5808 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
5809 | if (add_breg_early) | |
f5040a92 | 5810 | { |
67c0d1eb | 5811 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5812 | treg, tempreg, breg); |
f5040a92 AO |
5813 | breg = 0; |
5814 | tempreg = treg; | |
5815 | } | |
4d7206a2 | 5816 | relax_end (); |
f5040a92 | 5817 | } |
252b5132 RH |
5818 | else |
5819 | abort (); | |
5820 | ||
5821 | if (breg != 0) | |
aed1a261 | 5822 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg); |
252b5132 RH |
5823 | break; |
5824 | ||
5825 | case M_J_A: | |
5826 | /* The j instruction may not be used in PIC code, since it | |
5827 | requires an absolute address. We convert it to a b | |
5828 | instruction. */ | |
5829 | if (mips_pic == NO_PIC) | |
67c0d1eb | 5830 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 5831 | else |
67c0d1eb | 5832 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 5833 | break; |
252b5132 RH |
5834 | |
5835 | /* The jal instructions must be handled as macros because when | |
5836 | generating PIC code they expand to multi-instruction | |
5837 | sequences. Normally they are simple instructions. */ | |
5838 | case M_JAL_1: | |
5839 | dreg = RA; | |
5840 | /* Fall through. */ | |
5841 | case M_JAL_2: | |
3e722fb5 | 5842 | if (mips_pic == NO_PIC) |
67c0d1eb | 5843 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
0a44bf69 | 5844 | else |
252b5132 RH |
5845 | { |
5846 | if (sreg != PIC_CALL_REG) | |
5847 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 5848 | |
67c0d1eb | 5849 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
0a44bf69 | 5850 | if (mips_pic == SVR4_PIC && !HAVE_NEWABI) |
252b5132 | 5851 | { |
6478892d TS |
5852 | if (mips_cprestore_offset < 0) |
5853 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5854 | else | |
5855 | { | |
7a621144 DJ |
5856 | if (! mips_frame_reg_valid) |
5857 | { | |
5858 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5859 | /* Quiet this warning. */ | |
5860 | mips_frame_reg_valid = 1; | |
5861 | } | |
5862 | if (! mips_cprestore_valid) | |
5863 | { | |
5864 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5865 | /* Quiet this warning. */ | |
5866 | mips_cprestore_valid = 1; | |
5867 | } | |
6478892d | 5868 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 5869 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 5870 | mips_gp_register, |
256ab948 TS |
5871 | mips_frame_reg, |
5872 | HAVE_64BIT_ADDRESSES); | |
6478892d | 5873 | } |
252b5132 RH |
5874 | } |
5875 | } | |
252b5132 | 5876 | |
8fc2e39e | 5877 | break; |
252b5132 RH |
5878 | |
5879 | case M_JAL_A: | |
5880 | if (mips_pic == NO_PIC) | |
67c0d1eb | 5881 | macro_build (&offset_expr, "jal", "a"); |
252b5132 RH |
5882 | else if (mips_pic == SVR4_PIC) |
5883 | { | |
5884 | /* If this is a reference to an external symbol, and we are | |
5885 | using a small GOT, we want | |
5886 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
5887 | nop | |
f9419b05 | 5888 | jalr $ra,$25 |
252b5132 RH |
5889 | nop |
5890 | lw $gp,cprestore($sp) | |
5891 | The cprestore value is set using the .cprestore | |
5892 | pseudo-op. If we are using a big GOT, we want | |
5893 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
5894 | addu $25,$25,$gp | |
5895 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
5896 | nop | |
f9419b05 | 5897 | jalr $ra,$25 |
252b5132 RH |
5898 | nop |
5899 | lw $gp,cprestore($sp) | |
5900 | If the symbol is not external, we want | |
5901 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5902 | nop | |
5903 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 5904 | jalr $ra,$25 |
252b5132 | 5905 | nop |
438c16b8 | 5906 | lw $gp,cprestore($sp) |
f5040a92 AO |
5907 | |
5908 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
5909 | sequences above, minus nops, unless the symbol is local, | |
5910 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
5911 | GOT_DISP. */ | |
438c16b8 | 5912 | if (HAVE_NEWABI) |
252b5132 | 5913 | { |
f5040a92 AO |
5914 | if (! mips_big_got) |
5915 | { | |
4d7206a2 | 5916 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5917 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5918 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 5919 | mips_gp_register); |
4d7206a2 | 5920 | relax_switch (); |
67c0d1eb RS |
5921 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5922 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
5923 | mips_gp_register); |
5924 | relax_end (); | |
f5040a92 AO |
5925 | } |
5926 | else | |
5927 | { | |
4d7206a2 | 5928 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5929 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, |
5930 | BFD_RELOC_MIPS_CALL_HI16); | |
5931 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
5932 | PIC_CALL_REG, mips_gp_register); | |
5933 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
5934 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
5935 | PIC_CALL_REG); | |
4d7206a2 | 5936 | relax_switch (); |
67c0d1eb RS |
5937 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5938 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
5939 | mips_gp_register); | |
5940 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5941 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 5942 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 5943 | relax_end (); |
f5040a92 | 5944 | } |
684022ea | 5945 | |
67c0d1eb | 5946 | macro_build_jalr (&offset_expr); |
252b5132 RH |
5947 | } |
5948 | else | |
5949 | { | |
4d7206a2 | 5950 | relax_start (offset_expr.X_add_symbol); |
438c16b8 TS |
5951 | if (! mips_big_got) |
5952 | { | |
67c0d1eb RS |
5953 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5954 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 5955 | mips_gp_register); |
269137b2 | 5956 | load_delay_nop (); |
4d7206a2 | 5957 | relax_switch (); |
438c16b8 | 5958 | } |
252b5132 | 5959 | else |
252b5132 | 5960 | { |
67c0d1eb RS |
5961 | int gpdelay; |
5962 | ||
5963 | gpdelay = reg_needs_delay (mips_gp_register); | |
5964 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, | |
5965 | BFD_RELOC_MIPS_CALL_HI16); | |
5966 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
5967 | PIC_CALL_REG, mips_gp_register); | |
5968 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
5969 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
5970 | PIC_CALL_REG); | |
269137b2 | 5971 | load_delay_nop (); |
4d7206a2 | 5972 | relax_switch (); |
67c0d1eb RS |
5973 | if (gpdelay) |
5974 | macro_build (NULL, "nop", ""); | |
252b5132 | 5975 | } |
67c0d1eb RS |
5976 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5977 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 5978 | mips_gp_register); |
269137b2 | 5979 | load_delay_nop (); |
67c0d1eb RS |
5980 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5981 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 5982 | relax_end (); |
67c0d1eb | 5983 | macro_build_jalr (&offset_expr); |
438c16b8 | 5984 | |
6478892d TS |
5985 | if (mips_cprestore_offset < 0) |
5986 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5987 | else | |
5988 | { | |
7a621144 DJ |
5989 | if (! mips_frame_reg_valid) |
5990 | { | |
5991 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5992 | /* Quiet this warning. */ | |
5993 | mips_frame_reg_valid = 1; | |
5994 | } | |
5995 | if (! mips_cprestore_valid) | |
5996 | { | |
5997 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5998 | /* Quiet this warning. */ | |
5999 | mips_cprestore_valid = 1; | |
6000 | } | |
6478892d | 6001 | if (mips_opts.noreorder) |
67c0d1eb | 6002 | macro_build (NULL, "nop", ""); |
6478892d | 6003 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 6004 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 6005 | mips_gp_register, |
256ab948 TS |
6006 | mips_frame_reg, |
6007 | HAVE_64BIT_ADDRESSES); | |
6478892d | 6008 | } |
252b5132 RH |
6009 | } |
6010 | } | |
0a44bf69 RS |
6011 | else if (mips_pic == VXWORKS_PIC) |
6012 | as_bad (_("Non-PIC jump used in PIC library")); | |
252b5132 RH |
6013 | else |
6014 | abort (); | |
6015 | ||
8fc2e39e | 6016 | break; |
252b5132 RH |
6017 | |
6018 | case M_LB_AB: | |
6019 | s = "lb"; | |
6020 | goto ld; | |
6021 | case M_LBU_AB: | |
6022 | s = "lbu"; | |
6023 | goto ld; | |
6024 | case M_LH_AB: | |
6025 | s = "lh"; | |
6026 | goto ld; | |
6027 | case M_LHU_AB: | |
6028 | s = "lhu"; | |
6029 | goto ld; | |
6030 | case M_LW_AB: | |
6031 | s = "lw"; | |
6032 | goto ld; | |
6033 | case M_LWC0_AB: | |
6034 | s = "lwc0"; | |
bdaaa2e1 | 6035 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6036 | coproc = 1; |
6037 | goto ld; | |
6038 | case M_LWC1_AB: | |
6039 | s = "lwc1"; | |
bdaaa2e1 | 6040 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6041 | coproc = 1; |
6042 | goto ld; | |
6043 | case M_LWC2_AB: | |
6044 | s = "lwc2"; | |
bdaaa2e1 | 6045 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6046 | coproc = 1; |
6047 | goto ld; | |
6048 | case M_LWC3_AB: | |
6049 | s = "lwc3"; | |
bdaaa2e1 | 6050 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6051 | coproc = 1; |
6052 | goto ld; | |
6053 | case M_LWL_AB: | |
6054 | s = "lwl"; | |
6055 | lr = 1; | |
6056 | goto ld; | |
6057 | case M_LWR_AB: | |
6058 | s = "lwr"; | |
6059 | lr = 1; | |
6060 | goto ld; | |
6061 | case M_LDC1_AB: | |
fef14a42 | 6062 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6063 | { |
6064 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6065 | break; |
252b5132 RH |
6066 | } |
6067 | s = "ldc1"; | |
bdaaa2e1 | 6068 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6069 | coproc = 1; |
6070 | goto ld; | |
6071 | case M_LDC2_AB: | |
6072 | s = "ldc2"; | |
bdaaa2e1 | 6073 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6074 | coproc = 1; |
6075 | goto ld; | |
6076 | case M_LDC3_AB: | |
6077 | s = "ldc3"; | |
bdaaa2e1 | 6078 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6079 | coproc = 1; |
6080 | goto ld; | |
6081 | case M_LDL_AB: | |
6082 | s = "ldl"; | |
6083 | lr = 1; | |
6084 | goto ld; | |
6085 | case M_LDR_AB: | |
6086 | s = "ldr"; | |
6087 | lr = 1; | |
6088 | goto ld; | |
6089 | case M_LL_AB: | |
6090 | s = "ll"; | |
6091 | goto ld; | |
6092 | case M_LLD_AB: | |
6093 | s = "lld"; | |
6094 | goto ld; | |
6095 | case M_LWU_AB: | |
6096 | s = "lwu"; | |
6097 | ld: | |
8fc2e39e | 6098 | if (breg == treg || coproc || lr) |
252b5132 RH |
6099 | { |
6100 | tempreg = AT; | |
6101 | used_at = 1; | |
6102 | } | |
6103 | else | |
6104 | { | |
6105 | tempreg = treg; | |
252b5132 RH |
6106 | } |
6107 | goto ld_st; | |
6108 | case M_SB_AB: | |
6109 | s = "sb"; | |
6110 | goto st; | |
6111 | case M_SH_AB: | |
6112 | s = "sh"; | |
6113 | goto st; | |
6114 | case M_SW_AB: | |
6115 | s = "sw"; | |
6116 | goto st; | |
6117 | case M_SWC0_AB: | |
6118 | s = "swc0"; | |
bdaaa2e1 | 6119 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6120 | coproc = 1; |
6121 | goto st; | |
6122 | case M_SWC1_AB: | |
6123 | s = "swc1"; | |
bdaaa2e1 | 6124 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6125 | coproc = 1; |
6126 | goto st; | |
6127 | case M_SWC2_AB: | |
6128 | s = "swc2"; | |
bdaaa2e1 | 6129 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6130 | coproc = 1; |
6131 | goto st; | |
6132 | case M_SWC3_AB: | |
6133 | s = "swc3"; | |
bdaaa2e1 | 6134 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6135 | coproc = 1; |
6136 | goto st; | |
6137 | case M_SWL_AB: | |
6138 | s = "swl"; | |
6139 | goto st; | |
6140 | case M_SWR_AB: | |
6141 | s = "swr"; | |
6142 | goto st; | |
6143 | case M_SC_AB: | |
6144 | s = "sc"; | |
6145 | goto st; | |
6146 | case M_SCD_AB: | |
6147 | s = "scd"; | |
6148 | goto st; | |
d43b4baf TS |
6149 | case M_CACHE_AB: |
6150 | s = "cache"; | |
6151 | goto st; | |
252b5132 | 6152 | case M_SDC1_AB: |
fef14a42 | 6153 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6154 | { |
6155 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6156 | break; |
252b5132 RH |
6157 | } |
6158 | s = "sdc1"; | |
6159 | coproc = 1; | |
bdaaa2e1 | 6160 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6161 | goto st; |
6162 | case M_SDC2_AB: | |
6163 | s = "sdc2"; | |
bdaaa2e1 | 6164 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6165 | coproc = 1; |
6166 | goto st; | |
6167 | case M_SDC3_AB: | |
6168 | s = "sdc3"; | |
bdaaa2e1 | 6169 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6170 | coproc = 1; |
6171 | goto st; | |
6172 | case M_SDL_AB: | |
6173 | s = "sdl"; | |
6174 | goto st; | |
6175 | case M_SDR_AB: | |
6176 | s = "sdr"; | |
6177 | st: | |
8fc2e39e TS |
6178 | tempreg = AT; |
6179 | used_at = 1; | |
252b5132 | 6180 | ld_st: |
bdaaa2e1 | 6181 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6182 | if (mask == M_LWC1_AB |
6183 | || mask == M_SWC1_AB | |
6184 | || mask == M_LDC1_AB | |
6185 | || mask == M_SDC1_AB | |
6186 | || mask == M_L_DAB | |
6187 | || mask == M_S_DAB) | |
6188 | fmt = "T,o(b)"; | |
d43b4baf TS |
6189 | else if (mask == M_CACHE_AB) |
6190 | fmt = "k,o(b)"; | |
252b5132 RH |
6191 | else if (coproc) |
6192 | fmt = "E,o(b)"; | |
6193 | else | |
6194 | fmt = "t,o(b)"; | |
6195 | ||
6196 | if (offset_expr.X_op != O_constant | |
6197 | && offset_expr.X_op != O_symbol) | |
6198 | { | |
6199 | as_bad (_("expression too complex")); | |
6200 | offset_expr.X_op = O_constant; | |
6201 | } | |
6202 | ||
2051e8c4 MR |
6203 | if (HAVE_32BIT_ADDRESSES |
6204 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
6205 | { |
6206 | char value [32]; | |
6207 | ||
6208 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 6209 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 6210 | } |
2051e8c4 | 6211 | |
252b5132 RH |
6212 | /* A constant expression in PIC code can be handled just as it |
6213 | is in non PIC code. */ | |
aed1a261 RS |
6214 | if (offset_expr.X_op == O_constant) |
6215 | { | |
aed1a261 RS |
6216 | expr1.X_add_number = ((offset_expr.X_add_number + 0x8000) |
6217 | & ~(bfd_vma) 0xffff); | |
2051e8c4 | 6218 | normalize_address_expr (&expr1); |
aed1a261 RS |
6219 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); |
6220 | if (breg != 0) | |
6221 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
6222 | tempreg, tempreg, breg); | |
6223 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, tempreg); | |
6224 | } | |
6225 | else if (mips_pic == NO_PIC) | |
252b5132 RH |
6226 | { |
6227 | /* If this is a reference to a GP relative symbol, and there | |
6228 | is no base register, we want | |
cdf6fd85 | 6229 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
6230 | Otherwise, if there is no base register, we want |
6231 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6232 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6233 | If we have a constant, we need two instructions anyhow, | |
6234 | so we always use the latter form. | |
6235 | ||
6236 | If we have a base register, and this is a reference to a | |
6237 | GP relative symbol, we want | |
6238 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 6239 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
6240 | Otherwise we want |
6241 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6242 | addu $tempreg,$tempreg,$breg | |
6243 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 6244 | With a constant we always use the latter case. |
76b3015f | 6245 | |
d6bc6245 TS |
6246 | With 64bit address space and no base register and $at usable, |
6247 | we want | |
6248 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6249 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6250 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6251 | dsll32 $tempreg,0 | |
6252 | daddu $tempreg,$at | |
6253 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6254 | If we have a base register, we want | |
6255 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6256 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6257 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6258 | daddu $at,$breg | |
6259 | dsll32 $tempreg,0 | |
6260 | daddu $tempreg,$at | |
6261 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6262 | ||
6263 | Without $at we can't generate the optimal path for superscalar | |
6264 | processors here since this would require two temporary registers. | |
6265 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6266 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6267 | dsll $tempreg,16 | |
6268 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6269 | dsll $tempreg,16 | |
6270 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6271 | If we have a base register, we want | |
6272 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6273 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6274 | dsll $tempreg,16 | |
6275 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
6276 | dsll $tempreg,16 | |
6277 | daddu $tempreg,$tempreg,$breg | |
6278 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 | 6279 | |
6caf9ef4 | 6280 | For GP relative symbols in 64bit address space we can use |
aed1a261 RS |
6281 | the same sequence as in 32bit address space. */ |
6282 | if (HAVE_64BIT_SYMBOLS) | |
d6bc6245 | 6283 | { |
aed1a261 | 6284 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 TS |
6285 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
6286 | { | |
6287 | relax_start (offset_expr.X_add_symbol); | |
6288 | if (breg == 0) | |
6289 | { | |
6290 | macro_build (&offset_expr, s, fmt, treg, | |
6291 | BFD_RELOC_GPREL16, mips_gp_register); | |
6292 | } | |
6293 | else | |
6294 | { | |
6295 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
6296 | tempreg, breg, mips_gp_register); | |
6297 | macro_build (&offset_expr, s, fmt, treg, | |
6298 | BFD_RELOC_GPREL16, tempreg); | |
6299 | } | |
6300 | relax_switch (); | |
6301 | } | |
d6bc6245 | 6302 | |
b8285c27 | 6303 | if (used_at == 0 && !mips_opts.noat) |
d6bc6245 | 6304 | { |
67c0d1eb RS |
6305 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
6306 | BFD_RELOC_MIPS_HIGHEST); | |
6307 | macro_build (&offset_expr, "lui", "t,u", AT, | |
6308 | BFD_RELOC_HI16_S); | |
6309 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6310 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 6311 | if (breg != 0) |
67c0d1eb RS |
6312 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
6313 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); | |
6314 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
6315 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, | |
6316 | tempreg); | |
d6bc6245 TS |
6317 | used_at = 1; |
6318 | } | |
6319 | else | |
6320 | { | |
67c0d1eb RS |
6321 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
6322 | BFD_RELOC_MIPS_HIGHEST); | |
6323 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6324 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
6325 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
6326 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
6327 | tempreg, BFD_RELOC_HI16_S); | |
6328 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
d6bc6245 | 6329 | if (breg != 0) |
67c0d1eb | 6330 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 6331 | tempreg, tempreg, breg); |
67c0d1eb | 6332 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6333 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 6334 | } |
6caf9ef4 TS |
6335 | |
6336 | if (mips_relax.sequence) | |
6337 | relax_end (); | |
8fc2e39e | 6338 | break; |
d6bc6245 | 6339 | } |
256ab948 | 6340 | |
252b5132 RH |
6341 | if (breg == 0) |
6342 | { | |
67c0d1eb | 6343 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 6344 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 6345 | { |
4d7206a2 | 6346 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6347 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, |
6348 | mips_gp_register); | |
4d7206a2 | 6349 | relax_switch (); |
252b5132 | 6350 | } |
67c0d1eb RS |
6351 | macro_build_lui (&offset_expr, tempreg); |
6352 | macro_build (&offset_expr, s, fmt, treg, | |
17a2f251 | 6353 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
6354 | if (mips_relax.sequence) |
6355 | relax_end (); | |
252b5132 RH |
6356 | } |
6357 | else | |
6358 | { | |
67c0d1eb | 6359 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 6360 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 6361 | { |
4d7206a2 | 6362 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6363 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6364 | tempreg, breg, mips_gp_register); |
67c0d1eb | 6365 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6366 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 6367 | relax_switch (); |
252b5132 | 6368 | } |
67c0d1eb RS |
6369 | macro_build_lui (&offset_expr, tempreg); |
6370 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6371 | tempreg, tempreg, breg); |
67c0d1eb | 6372 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6373 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
6374 | if (mips_relax.sequence) |
6375 | relax_end (); | |
252b5132 RH |
6376 | } |
6377 | } | |
0a44bf69 | 6378 | else if (!mips_big_got) |
252b5132 | 6379 | { |
ed6fb7bd | 6380 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 6381 | |
252b5132 RH |
6382 | /* If this is a reference to an external symbol, we want |
6383 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6384 | nop | |
6385 | <op> $treg,0($tempreg) | |
6386 | Otherwise we want | |
6387 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6388 | nop | |
6389 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6390 | <op> $treg,0($tempreg) | |
f5040a92 AO |
6391 | |
6392 | For NewABI, we want | |
6393 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6394 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
6395 | ||
252b5132 RH |
6396 | If there is a base register, we add it to $tempreg before |
6397 | the <op>. If there is a constant, we stick it in the | |
6398 | <op> instruction. We don't handle constants larger than | |
6399 | 16 bits, because we have no way to load the upper 16 bits | |
6400 | (actually, we could handle them for the subset of cases | |
6401 | in which we are not using $at). */ | |
6402 | assert (offset_expr.X_op == O_symbol); | |
f5040a92 AO |
6403 | if (HAVE_NEWABI) |
6404 | { | |
67c0d1eb RS |
6405 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6406 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6407 | if (breg != 0) |
67c0d1eb | 6408 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6409 | tempreg, tempreg, breg); |
67c0d1eb | 6410 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6411 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
6412 | break; |
6413 | } | |
252b5132 RH |
6414 | expr1.X_add_number = offset_expr.X_add_number; |
6415 | offset_expr.X_add_number = 0; | |
6416 | if (expr1.X_add_number < -0x8000 | |
6417 | || expr1.X_add_number >= 0x8000) | |
6418 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
6419 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6420 | lw_reloc_type, mips_gp_register); | |
269137b2 | 6421 | load_delay_nop (); |
4d7206a2 RS |
6422 | relax_start (offset_expr.X_add_symbol); |
6423 | relax_switch (); | |
67c0d1eb RS |
6424 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6425 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 6426 | relax_end (); |
252b5132 | 6427 | if (breg != 0) |
67c0d1eb | 6428 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6429 | tempreg, tempreg, breg); |
67c0d1eb | 6430 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6431 | } |
0a44bf69 | 6432 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 6433 | { |
67c0d1eb | 6434 | int gpdelay; |
252b5132 RH |
6435 | |
6436 | /* If this is a reference to an external symbol, we want | |
6437 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6438 | addu $tempreg,$tempreg,$gp | |
6439 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6440 | <op> $treg,0($tempreg) | |
6441 | Otherwise we want | |
6442 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6443 | nop | |
6444 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
6445 | <op> $treg,0($tempreg) | |
6446 | If there is a base register, we add it to $tempreg before | |
6447 | the <op>. If there is a constant, we stick it in the | |
6448 | <op> instruction. We don't handle constants larger than | |
6449 | 16 bits, because we have no way to load the upper 16 bits | |
6450 | (actually, we could handle them for the subset of cases | |
f5040a92 | 6451 | in which we are not using $at). */ |
252b5132 RH |
6452 | assert (offset_expr.X_op == O_symbol); |
6453 | expr1.X_add_number = offset_expr.X_add_number; | |
6454 | offset_expr.X_add_number = 0; | |
6455 | if (expr1.X_add_number < -0x8000 | |
6456 | || expr1.X_add_number >= 0x8000) | |
6457 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6458 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 6459 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6460 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6461 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6462 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6463 | mips_gp_register); | |
6464 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6465 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 6466 | relax_switch (); |
67c0d1eb RS |
6467 | if (gpdelay) |
6468 | macro_build (NULL, "nop", ""); | |
6469 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6470 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6471 | load_delay_nop (); |
67c0d1eb RS |
6472 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
6473 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
6474 | relax_end (); |
6475 | ||
252b5132 | 6476 | if (breg != 0) |
67c0d1eb | 6477 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6478 | tempreg, tempreg, breg); |
67c0d1eb | 6479 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6480 | } |
0a44bf69 | 6481 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 6482 | { |
f5040a92 AO |
6483 | /* If this is a reference to an external symbol, we want |
6484 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6485 | add $tempreg,$tempreg,$gp | |
6486 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6487 | <op> $treg,<ofst>($tempreg) | |
6488 | Otherwise, for local symbols, we want: | |
6489 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6490 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
6491 | assert (offset_expr.X_op == O_symbol); | |
4d7206a2 | 6492 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
6493 | offset_expr.X_add_number = 0; |
6494 | if (expr1.X_add_number < -0x8000 | |
6495 | || expr1.X_add_number >= 0x8000) | |
6496 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 6497 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6498 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6499 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6500 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6501 | mips_gp_register); | |
6502 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6503 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 6504 | if (breg != 0) |
67c0d1eb | 6505 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6506 | tempreg, tempreg, breg); |
67c0d1eb | 6507 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
684022ea | 6508 | |
4d7206a2 | 6509 | relax_switch (); |
f5040a92 | 6510 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
6511 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6512 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6513 | if (breg != 0) |
67c0d1eb | 6514 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6515 | tempreg, tempreg, breg); |
67c0d1eb | 6516 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6517 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 6518 | relax_end (); |
f5040a92 | 6519 | } |
252b5132 RH |
6520 | else |
6521 | abort (); | |
6522 | ||
252b5132 RH |
6523 | break; |
6524 | ||
6525 | case M_LI: | |
6526 | case M_LI_S: | |
67c0d1eb | 6527 | load_register (treg, &imm_expr, 0); |
8fc2e39e | 6528 | break; |
252b5132 RH |
6529 | |
6530 | case M_DLI: | |
67c0d1eb | 6531 | load_register (treg, &imm_expr, 1); |
8fc2e39e | 6532 | break; |
252b5132 RH |
6533 | |
6534 | case M_LI_SS: | |
6535 | if (imm_expr.X_op == O_constant) | |
6536 | { | |
8fc2e39e | 6537 | used_at = 1; |
67c0d1eb RS |
6538 | load_register (AT, &imm_expr, 0); |
6539 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6540 | break; |
6541 | } | |
6542 | else | |
6543 | { | |
6544 | assert (offset_expr.X_op == O_symbol | |
6545 | && strcmp (segment_name (S_GET_SEGMENT | |
6546 | (offset_expr.X_add_symbol)), | |
6547 | ".lit4") == 0 | |
6548 | && offset_expr.X_add_number == 0); | |
67c0d1eb | 6549 | macro_build (&offset_expr, "lwc1", "T,o(b)", treg, |
17a2f251 | 6550 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 6551 | break; |
252b5132 RH |
6552 | } |
6553 | ||
6554 | case M_LI_D: | |
ca4e0257 RS |
6555 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
6556 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
6557 | order 32 bits of the value and the low order 32 bits are either | |
6558 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
6559 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6560 | { | |
ca4e0257 | 6561 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 6562 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
6563 | else |
6564 | { | |
6565 | int hreg, lreg; | |
6566 | ||
6567 | if (target_big_endian) | |
6568 | { | |
6569 | hreg = treg; | |
6570 | lreg = treg + 1; | |
6571 | } | |
6572 | else | |
6573 | { | |
6574 | hreg = treg + 1; | |
6575 | lreg = treg; | |
6576 | } | |
6577 | ||
6578 | if (hreg <= 31) | |
67c0d1eb | 6579 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
6580 | if (lreg <= 31) |
6581 | { | |
6582 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 6583 | move_register (lreg, 0); |
252b5132 RH |
6584 | else |
6585 | { | |
6586 | assert (offset_expr.X_op == O_constant); | |
67c0d1eb | 6587 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
6588 | } |
6589 | } | |
6590 | } | |
8fc2e39e | 6591 | break; |
252b5132 RH |
6592 | } |
6593 | ||
6594 | /* We know that sym is in the .rdata section. First we get the | |
6595 | upper 16 bits of the address. */ | |
6596 | if (mips_pic == NO_PIC) | |
6597 | { | |
67c0d1eb | 6598 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 6599 | used_at = 1; |
252b5132 | 6600 | } |
0a44bf69 | 6601 | else |
252b5132 | 6602 | { |
67c0d1eb RS |
6603 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6604 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 6605 | used_at = 1; |
252b5132 | 6606 | } |
bdaaa2e1 | 6607 | |
252b5132 | 6608 | /* Now we load the register(s). */ |
ca4e0257 | 6609 | if (HAVE_64BIT_GPRS) |
8fc2e39e TS |
6610 | { |
6611 | used_at = 1; | |
6612 | macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
6613 | } | |
252b5132 RH |
6614 | else |
6615 | { | |
8fc2e39e | 6616 | used_at = 1; |
67c0d1eb | 6617 | macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
f9419b05 | 6618 | if (treg != RA) |
252b5132 RH |
6619 | { |
6620 | /* FIXME: How in the world do we deal with the possible | |
6621 | overflow here? */ | |
6622 | offset_expr.X_add_number += 4; | |
67c0d1eb | 6623 | macro_build (&offset_expr, "lw", "t,o(b)", |
17a2f251 | 6624 | treg + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
6625 | } |
6626 | } | |
252b5132 RH |
6627 | break; |
6628 | ||
6629 | case M_LI_DD: | |
ca4e0257 RS |
6630 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
6631 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
6632 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
6633 | the value and the low order 32 bits are either zero or in | |
6634 | OFFSET_EXPR. */ | |
252b5132 RH |
6635 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6636 | { | |
8fc2e39e | 6637 | used_at = 1; |
67c0d1eb | 6638 | load_register (AT, &imm_expr, HAVE_64BIT_FPRS); |
ca4e0257 RS |
6639 | if (HAVE_64BIT_FPRS) |
6640 | { | |
6641 | assert (HAVE_64BIT_GPRS); | |
67c0d1eb | 6642 | macro_build (NULL, "dmtc1", "t,S", AT, treg); |
ca4e0257 | 6643 | } |
252b5132 RH |
6644 | else |
6645 | { | |
67c0d1eb | 6646 | macro_build (NULL, "mtc1", "t,G", AT, treg + 1); |
252b5132 | 6647 | if (offset_expr.X_op == O_absent) |
67c0d1eb | 6648 | macro_build (NULL, "mtc1", "t,G", 0, treg); |
252b5132 RH |
6649 | else |
6650 | { | |
6651 | assert (offset_expr.X_op == O_constant); | |
67c0d1eb RS |
6652 | load_register (AT, &offset_expr, 0); |
6653 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6654 | } |
6655 | } | |
6656 | break; | |
6657 | } | |
6658 | ||
6659 | assert (offset_expr.X_op == O_symbol | |
6660 | && offset_expr.X_add_number == 0); | |
6661 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
6662 | if (strcmp (s, ".lit8") == 0) | |
6663 | { | |
e7af610e | 6664 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6665 | { |
67c0d1eb | 6666 | macro_build (&offset_expr, "ldc1", "T,o(b)", treg, |
17a2f251 | 6667 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 6668 | break; |
252b5132 | 6669 | } |
c9914766 | 6670 | breg = mips_gp_register; |
252b5132 RH |
6671 | r = BFD_RELOC_MIPS_LITERAL; |
6672 | goto dob; | |
6673 | } | |
6674 | else | |
6675 | { | |
6676 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); | |
8fc2e39e | 6677 | used_at = 1; |
0a44bf69 | 6678 | if (mips_pic != NO_PIC) |
67c0d1eb RS |
6679 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6680 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
6681 | else |
6682 | { | |
6683 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 6684 | macro_build_lui (&offset_expr, AT); |
252b5132 | 6685 | } |
bdaaa2e1 | 6686 | |
e7af610e | 6687 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6688 | { |
67c0d1eb RS |
6689 | macro_build (&offset_expr, "ldc1", "T,o(b)", |
6690 | treg, BFD_RELOC_LO16, AT); | |
252b5132 RH |
6691 | break; |
6692 | } | |
6693 | breg = AT; | |
6694 | r = BFD_RELOC_LO16; | |
6695 | goto dob; | |
6696 | } | |
6697 | ||
6698 | case M_L_DOB: | |
fef14a42 | 6699 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6700 | { |
6701 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6702 | break; |
252b5132 RH |
6703 | } |
6704 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6705 | to adjust when loading from memory. */ | |
6706 | r = BFD_RELOC_LO16; | |
6707 | dob: | |
e7af610e | 6708 | assert (mips_opts.isa == ISA_MIPS1); |
67c0d1eb | 6709 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 6710 | target_big_endian ? treg + 1 : treg, r, breg); |
252b5132 RH |
6711 | /* FIXME: A possible overflow which I don't know how to deal |
6712 | with. */ | |
6713 | offset_expr.X_add_number += 4; | |
67c0d1eb | 6714 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 6715 | target_big_endian ? treg : treg + 1, r, breg); |
252b5132 RH |
6716 | break; |
6717 | ||
6718 | case M_L_DAB: | |
6719 | /* | |
6720 | * The MIPS assembler seems to check for X_add_number not | |
6721 | * being double aligned and generating: | |
6722 | * lui at,%hi(foo+1) | |
6723 | * addu at,at,v1 | |
6724 | * addiu at,at,%lo(foo+1) | |
6725 | * lwc1 f2,0(at) | |
6726 | * lwc1 f3,4(at) | |
6727 | * But, the resulting address is the same after relocation so why | |
6728 | * generate the extra instruction? | |
6729 | */ | |
fef14a42 | 6730 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6731 | { |
6732 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6733 | break; |
252b5132 | 6734 | } |
bdaaa2e1 | 6735 | /* Itbl support may require additional care here. */ |
252b5132 | 6736 | coproc = 1; |
e7af610e | 6737 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6738 | { |
6739 | s = "ldc1"; | |
6740 | goto ld; | |
6741 | } | |
6742 | ||
6743 | s = "lwc1"; | |
6744 | fmt = "T,o(b)"; | |
6745 | goto ldd_std; | |
6746 | ||
6747 | case M_S_DAB: | |
fef14a42 | 6748 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6749 | { |
6750 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6751 | break; |
252b5132 RH |
6752 | } |
6753 | ||
e7af610e | 6754 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6755 | { |
6756 | s = "sdc1"; | |
6757 | goto st; | |
6758 | } | |
6759 | ||
6760 | s = "swc1"; | |
6761 | fmt = "T,o(b)"; | |
bdaaa2e1 | 6762 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6763 | coproc = 1; |
6764 | goto ldd_std; | |
6765 | ||
6766 | case M_LD_AB: | |
ca4e0257 | 6767 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6768 | { |
6769 | s = "ld"; | |
6770 | goto ld; | |
6771 | } | |
6772 | ||
6773 | s = "lw"; | |
6774 | fmt = "t,o(b)"; | |
6775 | goto ldd_std; | |
6776 | ||
6777 | case M_SD_AB: | |
ca4e0257 | 6778 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6779 | { |
6780 | s = "sd"; | |
6781 | goto st; | |
6782 | } | |
6783 | ||
6784 | s = "sw"; | |
6785 | fmt = "t,o(b)"; | |
6786 | ||
6787 | ldd_std: | |
6788 | if (offset_expr.X_op != O_symbol | |
6789 | && offset_expr.X_op != O_constant) | |
6790 | { | |
6791 | as_bad (_("expression too complex")); | |
6792 | offset_expr.X_op = O_constant; | |
6793 | } | |
6794 | ||
2051e8c4 MR |
6795 | if (HAVE_32BIT_ADDRESSES |
6796 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
6797 | { |
6798 | char value [32]; | |
6799 | ||
6800 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 6801 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 6802 | } |
2051e8c4 | 6803 | |
252b5132 RH |
6804 | /* Even on a big endian machine $fn comes before $fn+1. We have |
6805 | to adjust when loading from memory. We set coproc if we must | |
6806 | load $fn+1 first. */ | |
bdaaa2e1 | 6807 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6808 | if (! target_big_endian) |
6809 | coproc = 0; | |
6810 | ||
6811 | if (mips_pic == NO_PIC | |
6812 | || offset_expr.X_op == O_constant) | |
6813 | { | |
6814 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 TS |
6815 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
6816 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6817 | If we have a base register, we use this |
6818 | addu $at,$breg,$gp | |
cdf6fd85 TS |
6819 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
6820 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6821 | If this is not a GP relative symbol, we want |
6822 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6823 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6824 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6825 | If there is a base register, we add it to $at after the | |
6826 | lui instruction. If there is a constant, we always use | |
6827 | the last case. */ | |
39a59cf8 MR |
6828 | if (offset_expr.X_op == O_symbol |
6829 | && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 6830 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 6831 | { |
4d7206a2 | 6832 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
6833 | if (breg == 0) |
6834 | { | |
c9914766 | 6835 | tempreg = mips_gp_register; |
252b5132 RH |
6836 | } |
6837 | else | |
6838 | { | |
67c0d1eb | 6839 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6840 | AT, breg, mips_gp_register); |
252b5132 | 6841 | tempreg = AT; |
252b5132 RH |
6842 | used_at = 1; |
6843 | } | |
6844 | ||
beae10d5 | 6845 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6846 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6847 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6848 | offset_expr.X_add_number += 4; |
6849 | ||
6850 | /* Set mips_optimize to 2 to avoid inserting an | |
6851 | undesired nop. */ | |
6852 | hold_mips_optimize = mips_optimize; | |
6853 | mips_optimize = 2; | |
beae10d5 | 6854 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6855 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6856 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6857 | mips_optimize = hold_mips_optimize; |
6858 | ||
4d7206a2 | 6859 | relax_switch (); |
252b5132 RH |
6860 | |
6861 | /* We just generated two relocs. When tc_gen_reloc | |
6862 | handles this case, it will skip the first reloc and | |
6863 | handle the second. The second reloc already has an | |
6864 | extra addend of 4, which we added above. We must | |
6865 | subtract it out, and then subtract another 4 to make | |
6866 | the first reloc come out right. The second reloc | |
6867 | will come out right because we are going to add 4 to | |
6868 | offset_expr when we build its instruction below. | |
6869 | ||
6870 | If we have a symbol, then we don't want to include | |
6871 | the offset, because it will wind up being included | |
6872 | when we generate the reloc. */ | |
6873 | ||
6874 | if (offset_expr.X_op == O_constant) | |
6875 | offset_expr.X_add_number -= 8; | |
6876 | else | |
6877 | { | |
6878 | offset_expr.X_add_number = -4; | |
6879 | offset_expr.X_op = O_constant; | |
6880 | } | |
6881 | } | |
8fc2e39e | 6882 | used_at = 1; |
67c0d1eb | 6883 | macro_build_lui (&offset_expr, AT); |
252b5132 | 6884 | if (breg != 0) |
67c0d1eb | 6885 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6886 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6887 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6888 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6889 | /* FIXME: How do we handle overflow here? */ |
6890 | offset_expr.X_add_number += 4; | |
beae10d5 | 6891 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6892 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6893 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
6894 | if (mips_relax.sequence) |
6895 | relax_end (); | |
bdaaa2e1 | 6896 | } |
0a44bf69 | 6897 | else if (!mips_big_got) |
252b5132 | 6898 | { |
252b5132 RH |
6899 | /* If this is a reference to an external symbol, we want |
6900 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6901 | nop | |
6902 | <op> $treg,0($at) | |
6903 | <op> $treg+1,4($at) | |
6904 | Otherwise we want | |
6905 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6906 | nop | |
6907 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6908 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6909 | If there is a base register we add it to $at before the | |
6910 | lwc1 instructions. If there is a constant we include it | |
6911 | in the lwc1 instructions. */ | |
6912 | used_at = 1; | |
6913 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
6914 | if (expr1.X_add_number < -0x8000 |
6915 | || expr1.X_add_number >= 0x8000 - 4) | |
6916 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6917 | load_got_offset (AT, &offset_expr); |
269137b2 | 6918 | load_delay_nop (); |
252b5132 | 6919 | if (breg != 0) |
67c0d1eb | 6920 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
6921 | |
6922 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6923 | nop. */ | |
6924 | hold_mips_optimize = mips_optimize; | |
6925 | mips_optimize = 2; | |
4d7206a2 | 6926 | |
beae10d5 | 6927 | /* Itbl support may require additional care here. */ |
4d7206a2 | 6928 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6929 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
6930 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6931 | expr1.X_add_number += 4; |
67c0d1eb RS |
6932 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
6933 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6934 | relax_switch (); |
67c0d1eb RS |
6935 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
6936 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6937 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
6938 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
6939 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6940 | relax_end (); |
252b5132 | 6941 | |
4d7206a2 | 6942 | mips_optimize = hold_mips_optimize; |
252b5132 | 6943 | } |
0a44bf69 | 6944 | else if (mips_big_got) |
252b5132 | 6945 | { |
67c0d1eb | 6946 | int gpdelay; |
252b5132 RH |
6947 | |
6948 | /* If this is a reference to an external symbol, we want | |
6949 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6950 | addu $at,$at,$gp | |
6951 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
6952 | nop | |
6953 | <op> $treg,0($at) | |
6954 | <op> $treg+1,4($at) | |
6955 | Otherwise we want | |
6956 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6957 | nop | |
6958 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6959 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6960 | If there is a base register we add it to $at before the | |
6961 | lwc1 instructions. If there is a constant we include it | |
6962 | in the lwc1 instructions. */ | |
6963 | used_at = 1; | |
6964 | expr1.X_add_number = offset_expr.X_add_number; | |
6965 | offset_expr.X_add_number = 0; | |
6966 | if (expr1.X_add_number < -0x8000 | |
6967 | || expr1.X_add_number >= 0x8000 - 4) | |
6968 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6969 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 6970 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6971 | macro_build (&offset_expr, "lui", "t,u", |
6972 | AT, BFD_RELOC_MIPS_GOT_HI16); | |
6973 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6974 | AT, AT, mips_gp_register); |
67c0d1eb | 6975 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 6976 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 6977 | load_delay_nop (); |
252b5132 | 6978 | if (breg != 0) |
67c0d1eb | 6979 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6980 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6981 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6982 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6983 | expr1.X_add_number += 4; |
6984 | ||
6985 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6986 | nop. */ | |
6987 | hold_mips_optimize = mips_optimize; | |
6988 | mips_optimize = 2; | |
beae10d5 | 6989 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6990 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6991 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6992 | mips_optimize = hold_mips_optimize; |
6993 | expr1.X_add_number -= 4; | |
6994 | ||
4d7206a2 RS |
6995 | relax_switch (); |
6996 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
6997 | if (gpdelay) |
6998 | macro_build (NULL, "nop", ""); | |
6999 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
7000 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 7001 | load_delay_nop (); |
252b5132 | 7002 | if (breg != 0) |
67c0d1eb | 7003 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 7004 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
7005 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
7006 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 7007 | offset_expr.X_add_number += 4; |
252b5132 RH |
7008 | |
7009 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
7010 | nop. */ | |
7011 | hold_mips_optimize = mips_optimize; | |
7012 | mips_optimize = 2; | |
beae10d5 | 7013 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
7014 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
7015 | BFD_RELOC_LO16, AT); | |
252b5132 | 7016 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 7017 | relax_end (); |
252b5132 | 7018 | } |
252b5132 RH |
7019 | else |
7020 | abort (); | |
7021 | ||
252b5132 RH |
7022 | break; |
7023 | ||
7024 | case M_LD_OB: | |
7025 | s = "lw"; | |
7026 | goto sd_ob; | |
7027 | case M_SD_OB: | |
7028 | s = "sw"; | |
7029 | sd_ob: | |
ca4e0257 | 7030 | assert (HAVE_32BIT_ADDRESSES); |
67c0d1eb | 7031 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 | 7032 | offset_expr.X_add_number += 4; |
67c0d1eb | 7033 | macro_build (&offset_expr, s, "t,o(b)", treg + 1, BFD_RELOC_LO16, breg); |
8fc2e39e | 7034 | break; |
252b5132 RH |
7035 | |
7036 | /* New code added to support COPZ instructions. | |
7037 | This code builds table entries out of the macros in mip_opcodes. | |
7038 | R4000 uses interlocks to handle coproc delays. | |
7039 | Other chips (like the R3000) require nops to be inserted for delays. | |
7040 | ||
f72c8c98 | 7041 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
7042 | In order to fill delay slots for non-interlocked chips, |
7043 | we must have a way to specify delays based on the coprocessor. | |
7044 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
7045 | What are the side-effects of the cop instruction? | |
7046 | What cache support might we have and what are its effects? | |
7047 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 7048 | What registers are read/set/modified? |
252b5132 RH |
7049 | |
7050 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 7051 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
7052 | |
7053 | case M_COP0: | |
7054 | s = "c0"; | |
7055 | goto copz; | |
7056 | case M_COP1: | |
7057 | s = "c1"; | |
7058 | goto copz; | |
7059 | case M_COP2: | |
7060 | s = "c2"; | |
7061 | goto copz; | |
7062 | case M_COP3: | |
7063 | s = "c3"; | |
7064 | copz: | |
7065 | /* For now we just do C (same as Cz). The parameter will be | |
7066 | stored in insn_opcode by mips_ip. */ | |
67c0d1eb | 7067 | macro_build (NULL, s, "C", ip->insn_opcode); |
8fc2e39e | 7068 | break; |
252b5132 | 7069 | |
ea1fb5dc | 7070 | case M_MOVE: |
67c0d1eb | 7071 | move_register (dreg, sreg); |
8fc2e39e | 7072 | break; |
ea1fb5dc | 7073 | |
252b5132 RH |
7074 | #ifdef LOSING_COMPILER |
7075 | default: | |
7076 | /* Try and see if this is a new itbl instruction. | |
7077 | This code builds table entries out of the macros in mip_opcodes. | |
7078 | FIXME: For now we just assemble the expression and pass it's | |
7079 | value along as a 32-bit immediate. | |
bdaaa2e1 | 7080 | We may want to have the assembler assemble this value, |
252b5132 RH |
7081 | so that we gain the assembler's knowledge of delay slots, |
7082 | symbols, etc. | |
7083 | Would it be more efficient to use mask (id) here? */ | |
bdaaa2e1 | 7084 | if (itbl_have_entries |
252b5132 | 7085 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
beae10d5 | 7086 | { |
252b5132 RH |
7087 | s = ip->insn_mo->name; |
7088 | s2 = "cop3"; | |
7089 | coproc = ITBL_DECODE_PNUM (immed_expr);; | |
67c0d1eb | 7090 | macro_build (&immed_expr, s, "C"); |
8fc2e39e | 7091 | break; |
beae10d5 | 7092 | } |
252b5132 | 7093 | macro2 (ip); |
8fc2e39e | 7094 | break; |
252b5132 | 7095 | } |
8fc2e39e TS |
7096 | if (mips_opts.noat && used_at) |
7097 | as_bad (_("Macro used $at after \".set noat\"")); | |
252b5132 | 7098 | } |
bdaaa2e1 | 7099 | |
252b5132 | 7100 | static void |
17a2f251 | 7101 | macro2 (struct mips_cl_insn *ip) |
252b5132 | 7102 | { |
3994f87e | 7103 | int treg, sreg, dreg, breg; |
252b5132 RH |
7104 | int tempreg; |
7105 | int mask; | |
252b5132 RH |
7106 | int used_at; |
7107 | expressionS expr1; | |
7108 | const char *s; | |
7109 | const char *s2; | |
7110 | const char *fmt; | |
7111 | int likely = 0; | |
7112 | int dbl = 0; | |
7113 | int coproc = 0; | |
7114 | int lr = 0; | |
7115 | int imm = 0; | |
7116 | int off; | |
7117 | offsetT maxnum; | |
7118 | bfd_reloc_code_real_type r; | |
bdaaa2e1 | 7119 | |
252b5132 RH |
7120 | treg = (ip->insn_opcode >> 16) & 0x1f; |
7121 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
7122 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
7123 | mask = ip->insn_mo->mask; | |
bdaaa2e1 | 7124 | |
252b5132 RH |
7125 | expr1.X_op = O_constant; |
7126 | expr1.X_op_symbol = NULL; | |
7127 | expr1.X_add_symbol = NULL; | |
7128 | expr1.X_add_number = 1; | |
bdaaa2e1 | 7129 | |
252b5132 RH |
7130 | switch (mask) |
7131 | { | |
7132 | #endif /* LOSING_COMPILER */ | |
7133 | ||
7134 | case M_DMUL: | |
7135 | dbl = 1; | |
7136 | case M_MUL: | |
67c0d1eb RS |
7137 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg); |
7138 | macro_build (NULL, "mflo", "d", dreg); | |
8fc2e39e | 7139 | break; |
252b5132 RH |
7140 | |
7141 | case M_DMUL_I: | |
7142 | dbl = 1; | |
7143 | case M_MUL_I: | |
7144 | /* The MIPS assembler some times generates shifts and adds. I'm | |
7145 | not trying to be that fancy. GCC should do this for us | |
7146 | anyway. */ | |
8fc2e39e | 7147 | used_at = 1; |
67c0d1eb RS |
7148 | load_register (AT, &imm_expr, dbl); |
7149 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT); | |
7150 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 RH |
7151 | break; |
7152 | ||
7153 | case M_DMULO_I: | |
7154 | dbl = 1; | |
7155 | case M_MULO_I: | |
7156 | imm = 1; | |
7157 | goto do_mulo; | |
7158 | ||
7159 | case M_DMULO: | |
7160 | dbl = 1; | |
7161 | case M_MULO: | |
7162 | do_mulo: | |
7d10b47d | 7163 | start_noreorder (); |
8fc2e39e | 7164 | used_at = 1; |
252b5132 | 7165 | if (imm) |
67c0d1eb RS |
7166 | load_register (AT, &imm_expr, dbl); |
7167 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); | |
7168 | macro_build (NULL, "mflo", "d", dreg); | |
7169 | macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA); | |
7170 | macro_build (NULL, "mfhi", "d", AT); | |
252b5132 | 7171 | if (mips_trap) |
67c0d1eb | 7172 | macro_build (NULL, "tne", "s,t,q", dreg, AT, 6); |
252b5132 RH |
7173 | else |
7174 | { | |
7175 | expr1.X_add_number = 8; | |
67c0d1eb RS |
7176 | macro_build (&expr1, "beq", "s,t,p", dreg, AT); |
7177 | macro_build (NULL, "nop", "", 0); | |
7178 | macro_build (NULL, "break", "c", 6); | |
252b5132 | 7179 | } |
7d10b47d | 7180 | end_noreorder (); |
67c0d1eb | 7181 | macro_build (NULL, "mflo", "d", dreg); |
252b5132 RH |
7182 | break; |
7183 | ||
7184 | case M_DMULOU_I: | |
7185 | dbl = 1; | |
7186 | case M_MULOU_I: | |
7187 | imm = 1; | |
7188 | goto do_mulou; | |
7189 | ||
7190 | case M_DMULOU: | |
7191 | dbl = 1; | |
7192 | case M_MULOU: | |
7193 | do_mulou: | |
7d10b47d | 7194 | start_noreorder (); |
8fc2e39e | 7195 | used_at = 1; |
252b5132 | 7196 | if (imm) |
67c0d1eb RS |
7197 | load_register (AT, &imm_expr, dbl); |
7198 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
17a2f251 | 7199 | sreg, imm ? AT : treg); |
67c0d1eb RS |
7200 | macro_build (NULL, "mfhi", "d", AT); |
7201 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 | 7202 | if (mips_trap) |
67c0d1eb | 7203 | macro_build (NULL, "tne", "s,t,q", AT, 0, 6); |
252b5132 RH |
7204 | else |
7205 | { | |
7206 | expr1.X_add_number = 8; | |
67c0d1eb RS |
7207 | macro_build (&expr1, "beq", "s,t,p", AT, 0); |
7208 | macro_build (NULL, "nop", "", 0); | |
7209 | macro_build (NULL, "break", "c", 6); | |
252b5132 | 7210 | } |
7d10b47d | 7211 | end_noreorder (); |
252b5132 RH |
7212 | break; |
7213 | ||
771c7ce4 | 7214 | case M_DROL: |
fef14a42 | 7215 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
7216 | { |
7217 | if (dreg == sreg) | |
7218 | { | |
7219 | tempreg = AT; | |
7220 | used_at = 1; | |
7221 | } | |
7222 | else | |
7223 | { | |
7224 | tempreg = dreg; | |
82dd0097 | 7225 | } |
67c0d1eb RS |
7226 | macro_build (NULL, "dnegu", "d,w", tempreg, treg); |
7227 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 7228 | break; |
82dd0097 | 7229 | } |
8fc2e39e | 7230 | used_at = 1; |
67c0d1eb RS |
7231 | macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); |
7232 | macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT); | |
7233 | macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg); | |
7234 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7235 | break; |
7236 | ||
252b5132 | 7237 | case M_ROL: |
fef14a42 | 7238 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 CD |
7239 | { |
7240 | if (dreg == sreg) | |
7241 | { | |
7242 | tempreg = AT; | |
7243 | used_at = 1; | |
7244 | } | |
7245 | else | |
7246 | { | |
7247 | tempreg = dreg; | |
82dd0097 | 7248 | } |
67c0d1eb RS |
7249 | macro_build (NULL, "negu", "d,w", tempreg, treg); |
7250 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 7251 | break; |
82dd0097 | 7252 | } |
8fc2e39e | 7253 | used_at = 1; |
67c0d1eb RS |
7254 | macro_build (NULL, "subu", "d,v,t", AT, 0, treg); |
7255 | macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT); | |
7256 | macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg); | |
7257 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7258 | break; |
7259 | ||
771c7ce4 TS |
7260 | case M_DROL_I: |
7261 | { | |
7262 | unsigned int rot; | |
82dd0097 | 7263 | char *l, *r; |
771c7ce4 TS |
7264 | |
7265 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7266 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7267 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 7268 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
7269 | { |
7270 | rot = (64 - rot) & 0x3f; | |
7271 | if (rot >= 32) | |
67c0d1eb | 7272 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
60b63b72 | 7273 | else |
67c0d1eb | 7274 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7275 | break; |
60b63b72 | 7276 | } |
483fc7cd | 7277 | if (rot == 0) |
483fc7cd | 7278 | { |
67c0d1eb | 7279 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7280 | break; |
483fc7cd | 7281 | } |
82dd0097 CD |
7282 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
7283 | r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; | |
7284 | rot &= 0x1f; | |
8fc2e39e | 7285 | used_at = 1; |
67c0d1eb RS |
7286 | macro_build (NULL, l, "d,w,<", AT, sreg, rot); |
7287 | macro_build (NULL, r, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7288 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7289 | } |
7290 | break; | |
7291 | ||
252b5132 | 7292 | case M_ROL_I: |
771c7ce4 TS |
7293 | { |
7294 | unsigned int rot; | |
7295 | ||
7296 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7297 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7298 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 7299 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 7300 | { |
67c0d1eb | 7301 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f); |
8fc2e39e | 7302 | break; |
60b63b72 | 7303 | } |
483fc7cd | 7304 | if (rot == 0) |
483fc7cd | 7305 | { |
67c0d1eb | 7306 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7307 | break; |
483fc7cd | 7308 | } |
8fc2e39e | 7309 | used_at = 1; |
67c0d1eb RS |
7310 | macro_build (NULL, "sll", "d,w,<", AT, sreg, rot); |
7311 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7312 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7313 | } |
7314 | break; | |
7315 | ||
7316 | case M_DROR: | |
fef14a42 | 7317 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 7318 | { |
67c0d1eb | 7319 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 7320 | break; |
82dd0097 | 7321 | } |
8fc2e39e | 7322 | used_at = 1; |
67c0d1eb RS |
7323 | macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); |
7324 | macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT); | |
7325 | macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg); | |
7326 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7327 | break; |
7328 | ||
7329 | case M_ROR: | |
fef14a42 | 7330 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7331 | { |
67c0d1eb | 7332 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 7333 | break; |
82dd0097 | 7334 | } |
8fc2e39e | 7335 | used_at = 1; |
67c0d1eb RS |
7336 | macro_build (NULL, "subu", "d,v,t", AT, 0, treg); |
7337 | macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT); | |
7338 | macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg); | |
7339 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
7340 | break; |
7341 | ||
771c7ce4 TS |
7342 | case M_DROR_I: |
7343 | { | |
7344 | unsigned int rot; | |
82dd0097 | 7345 | char *l, *r; |
771c7ce4 TS |
7346 | |
7347 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7348 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7349 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 7350 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
7351 | { |
7352 | if (rot >= 32) | |
67c0d1eb | 7353 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
82dd0097 | 7354 | else |
67c0d1eb | 7355 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7356 | break; |
82dd0097 | 7357 | } |
483fc7cd | 7358 | if (rot == 0) |
483fc7cd | 7359 | { |
67c0d1eb | 7360 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7361 | break; |
483fc7cd | 7362 | } |
82dd0097 CD |
7363 | r = (rot < 0x20) ? "dsrl" : "dsrl32"; |
7364 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; | |
7365 | rot &= 0x1f; | |
8fc2e39e | 7366 | used_at = 1; |
67c0d1eb RS |
7367 | macro_build (NULL, r, "d,w,<", AT, sreg, rot); |
7368 | macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7369 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
7370 | } |
7371 | break; | |
7372 | ||
252b5132 | 7373 | case M_ROR_I: |
771c7ce4 TS |
7374 | { |
7375 | unsigned int rot; | |
7376 | ||
7377 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 7378 | as_bad (_("Improper rotate count")); |
771c7ce4 | 7379 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 7380 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 7381 | { |
67c0d1eb | 7382 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 7383 | break; |
82dd0097 | 7384 | } |
483fc7cd | 7385 | if (rot == 0) |
483fc7cd | 7386 | { |
67c0d1eb | 7387 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 7388 | break; |
483fc7cd | 7389 | } |
8fc2e39e | 7390 | used_at = 1; |
67c0d1eb RS |
7391 | macro_build (NULL, "srl", "d,w,<", AT, sreg, rot); |
7392 | macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
7393 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 | 7394 | } |
252b5132 RH |
7395 | break; |
7396 | ||
7397 | case M_S_DOB: | |
fef14a42 | 7398 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
7399 | { |
7400 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 7401 | break; |
252b5132 | 7402 | } |
e7af610e | 7403 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
7404 | /* Even on a big endian machine $fn comes before $fn+1. We have |
7405 | to adjust when storing to memory. */ | |
67c0d1eb RS |
7406 | macro_build (&offset_expr, "swc1", "T,o(b)", |
7407 | target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg); | |
252b5132 | 7408 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
7409 | macro_build (&offset_expr, "swc1", "T,o(b)", |
7410 | target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg); | |
8fc2e39e | 7411 | break; |
252b5132 RH |
7412 | |
7413 | case M_SEQ: | |
7414 | if (sreg == 0) | |
67c0d1eb | 7415 | macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16); |
252b5132 | 7416 | else if (treg == 0) |
67c0d1eb | 7417 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7418 | else |
7419 | { | |
67c0d1eb RS |
7420 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7421 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 | 7422 | } |
8fc2e39e | 7423 | break; |
252b5132 RH |
7424 | |
7425 | case M_SEQ_I: | |
7426 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7427 | { | |
67c0d1eb | 7428 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7429 | break; |
252b5132 RH |
7430 | } |
7431 | if (sreg == 0) | |
7432 | { | |
7433 | as_warn (_("Instruction %s: result is always false"), | |
7434 | ip->insn_mo->name); | |
67c0d1eb | 7435 | move_register (dreg, 0); |
8fc2e39e | 7436 | break; |
252b5132 RH |
7437 | } |
7438 | if (imm_expr.X_op == O_constant | |
7439 | && imm_expr.X_add_number >= 0 | |
7440 | && imm_expr.X_add_number < 0x10000) | |
7441 | { | |
67c0d1eb | 7442 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7443 | } |
7444 | else if (imm_expr.X_op == O_constant | |
7445 | && imm_expr.X_add_number > -0x8000 | |
7446 | && imm_expr.X_add_number < 0) | |
7447 | { | |
7448 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7449 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7450 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7451 | } |
7452 | else | |
7453 | { | |
67c0d1eb RS |
7454 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7455 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7456 | used_at = 1; |
7457 | } | |
67c0d1eb | 7458 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 7459 | break; |
252b5132 RH |
7460 | |
7461 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
7462 | s = "slt"; | |
7463 | goto sge; | |
7464 | case M_SGEU: | |
7465 | s = "sltu"; | |
7466 | sge: | |
67c0d1eb RS |
7467 | macro_build (NULL, s, "d,v,t", dreg, sreg, treg); |
7468 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 7469 | break; |
252b5132 RH |
7470 | |
7471 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
7472 | case M_SGEU_I: | |
7473 | if (imm_expr.X_op == O_constant | |
7474 | && imm_expr.X_add_number >= -0x8000 | |
7475 | && imm_expr.X_add_number < 0x8000) | |
7476 | { | |
67c0d1eb RS |
7477 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
7478 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
7479 | } |
7480 | else | |
7481 | { | |
67c0d1eb RS |
7482 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7483 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", | |
7484 | dreg, sreg, AT); | |
252b5132 RH |
7485 | used_at = 1; |
7486 | } | |
67c0d1eb | 7487 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 7488 | break; |
252b5132 RH |
7489 | |
7490 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
7491 | s = "slt"; | |
7492 | goto sgt; | |
7493 | case M_SGTU: | |
7494 | s = "sltu"; | |
7495 | sgt: | |
67c0d1eb | 7496 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
8fc2e39e | 7497 | break; |
252b5132 RH |
7498 | |
7499 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
7500 | s = "slt"; | |
7501 | goto sgti; | |
7502 | case M_SGTU_I: | |
7503 | s = "sltu"; | |
7504 | sgti: | |
8fc2e39e | 7505 | used_at = 1; |
67c0d1eb RS |
7506 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7507 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
252b5132 RH |
7508 | break; |
7509 | ||
2396cfb9 | 7510 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
7511 | s = "slt"; |
7512 | goto sle; | |
7513 | case M_SLEU: | |
7514 | s = "sltu"; | |
7515 | sle: | |
67c0d1eb RS |
7516 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
7517 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 7518 | break; |
252b5132 | 7519 | |
2396cfb9 | 7520 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
7521 | s = "slt"; |
7522 | goto slei; | |
7523 | case M_SLEU_I: | |
7524 | s = "sltu"; | |
7525 | slei: | |
8fc2e39e | 7526 | used_at = 1; |
67c0d1eb RS |
7527 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7528 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
7529 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
7530 | break; |
7531 | ||
7532 | case M_SLT_I: | |
7533 | if (imm_expr.X_op == O_constant | |
7534 | && imm_expr.X_add_number >= -0x8000 | |
7535 | && imm_expr.X_add_number < 0x8000) | |
7536 | { | |
67c0d1eb | 7537 | macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7538 | break; |
252b5132 | 7539 | } |
8fc2e39e | 7540 | used_at = 1; |
67c0d1eb RS |
7541 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7542 | macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7543 | break; |
7544 | ||
7545 | case M_SLTU_I: | |
7546 | if (imm_expr.X_op == O_constant | |
7547 | && imm_expr.X_add_number >= -0x8000 | |
7548 | && imm_expr.X_add_number < 0x8000) | |
7549 | { | |
67c0d1eb | 7550 | macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg, |
17a2f251 | 7551 | BFD_RELOC_LO16); |
8fc2e39e | 7552 | break; |
252b5132 | 7553 | } |
8fc2e39e | 7554 | used_at = 1; |
67c0d1eb RS |
7555 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7556 | macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7557 | break; |
7558 | ||
7559 | case M_SNE: | |
7560 | if (sreg == 0) | |
67c0d1eb | 7561 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg); |
252b5132 | 7562 | else if (treg == 0) |
67c0d1eb | 7563 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
7564 | else |
7565 | { | |
67c0d1eb RS |
7566 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7567 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
252b5132 | 7568 | } |
8fc2e39e | 7569 | break; |
252b5132 RH |
7570 | |
7571 | case M_SNE_I: | |
7572 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7573 | { | |
67c0d1eb | 7574 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
8fc2e39e | 7575 | break; |
252b5132 RH |
7576 | } |
7577 | if (sreg == 0) | |
7578 | { | |
7579 | as_warn (_("Instruction %s: result is always true"), | |
7580 | ip->insn_mo->name); | |
67c0d1eb RS |
7581 | macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", |
7582 | dreg, 0, BFD_RELOC_LO16); | |
8fc2e39e | 7583 | break; |
252b5132 RH |
7584 | } |
7585 | if (imm_expr.X_op == O_constant | |
7586 | && imm_expr.X_add_number >= 0 | |
7587 | && imm_expr.X_add_number < 0x10000) | |
7588 | { | |
67c0d1eb | 7589 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7590 | } |
7591 | else if (imm_expr.X_op == O_constant | |
7592 | && imm_expr.X_add_number > -0x8000 | |
7593 | && imm_expr.X_add_number < 0) | |
7594 | { | |
7595 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7596 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7597 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7598 | } |
7599 | else | |
7600 | { | |
67c0d1eb RS |
7601 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7602 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7603 | used_at = 1; |
7604 | } | |
67c0d1eb | 7605 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); |
8fc2e39e | 7606 | break; |
252b5132 RH |
7607 | |
7608 | case M_DSUB_I: | |
7609 | dbl = 1; | |
7610 | case M_SUB_I: | |
7611 | if (imm_expr.X_op == O_constant | |
7612 | && imm_expr.X_add_number > -0x8000 | |
7613 | && imm_expr.X_add_number <= 0x8000) | |
7614 | { | |
7615 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7616 | macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j", |
7617 | dreg, sreg, BFD_RELOC_LO16); | |
8fc2e39e | 7618 | break; |
252b5132 | 7619 | } |
8fc2e39e | 7620 | used_at = 1; |
67c0d1eb RS |
7621 | load_register (AT, &imm_expr, dbl); |
7622 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7623 | break; |
7624 | ||
7625 | case M_DSUBU_I: | |
7626 | dbl = 1; | |
7627 | case M_SUBU_I: | |
7628 | if (imm_expr.X_op == O_constant | |
7629 | && imm_expr.X_add_number > -0x8000 | |
7630 | && imm_expr.X_add_number <= 0x8000) | |
7631 | { | |
7632 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7633 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j", |
7634 | dreg, sreg, BFD_RELOC_LO16); | |
8fc2e39e | 7635 | break; |
252b5132 | 7636 | } |
8fc2e39e | 7637 | used_at = 1; |
67c0d1eb RS |
7638 | load_register (AT, &imm_expr, dbl); |
7639 | macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7640 | break; |
7641 | ||
7642 | case M_TEQ_I: | |
7643 | s = "teq"; | |
7644 | goto trap; | |
7645 | case M_TGE_I: | |
7646 | s = "tge"; | |
7647 | goto trap; | |
7648 | case M_TGEU_I: | |
7649 | s = "tgeu"; | |
7650 | goto trap; | |
7651 | case M_TLT_I: | |
7652 | s = "tlt"; | |
7653 | goto trap; | |
7654 | case M_TLTU_I: | |
7655 | s = "tltu"; | |
7656 | goto trap; | |
7657 | case M_TNE_I: | |
7658 | s = "tne"; | |
7659 | trap: | |
8fc2e39e | 7660 | used_at = 1; |
67c0d1eb RS |
7661 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7662 | macro_build (NULL, s, "s,t", sreg, AT); | |
252b5132 RH |
7663 | break; |
7664 | ||
252b5132 | 7665 | case M_TRUNCWS: |
43841e91 | 7666 | case M_TRUNCWD: |
e7af610e | 7667 | assert (mips_opts.isa == ISA_MIPS1); |
8fc2e39e | 7668 | used_at = 1; |
252b5132 RH |
7669 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
7670 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
7671 | ||
7672 | /* | |
7673 | * Is the double cfc1 instruction a bug in the mips assembler; | |
7674 | * or is there a reason for it? | |
7675 | */ | |
7d10b47d | 7676 | start_noreorder (); |
67c0d1eb RS |
7677 | macro_build (NULL, "cfc1", "t,G", treg, RA); |
7678 | macro_build (NULL, "cfc1", "t,G", treg, RA); | |
7679 | macro_build (NULL, "nop", ""); | |
252b5132 | 7680 | expr1.X_add_number = 3; |
67c0d1eb | 7681 | macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16); |
252b5132 | 7682 | expr1.X_add_number = 2; |
67c0d1eb RS |
7683 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
7684 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
7685 | macro_build (NULL, "nop", ""); | |
7686 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
7687 | dreg, sreg); | |
7688 | macro_build (NULL, "ctc1", "t,G", treg, RA); | |
7689 | macro_build (NULL, "nop", ""); | |
7d10b47d | 7690 | end_noreorder (); |
252b5132 RH |
7691 | break; |
7692 | ||
7693 | case M_ULH: | |
7694 | s = "lb"; | |
7695 | goto ulh; | |
7696 | case M_ULHU: | |
7697 | s = "lbu"; | |
7698 | ulh: | |
8fc2e39e | 7699 | used_at = 1; |
252b5132 RH |
7700 | if (offset_expr.X_add_number >= 0x7fff) |
7701 | as_bad (_("operand overflow")); | |
252b5132 | 7702 | if (! target_big_endian) |
f9419b05 | 7703 | ++offset_expr.X_add_number; |
67c0d1eb | 7704 | macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 | 7705 | if (! target_big_endian) |
f9419b05 | 7706 | --offset_expr.X_add_number; |
252b5132 | 7707 | else |
f9419b05 | 7708 | ++offset_expr.X_add_number; |
67c0d1eb RS |
7709 | macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
7710 | macro_build (NULL, "sll", "d,w,<", AT, AT, 8); | |
7711 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7712 | break; |
7713 | ||
7714 | case M_ULD: | |
7715 | s = "ldl"; | |
7716 | s2 = "ldr"; | |
7717 | off = 7; | |
7718 | goto ulw; | |
7719 | case M_ULW: | |
7720 | s = "lwl"; | |
7721 | s2 = "lwr"; | |
7722 | off = 3; | |
7723 | ulw: | |
7724 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7725 | as_bad (_("operand overflow")); | |
af22f5b2 CD |
7726 | if (treg != breg) |
7727 | tempreg = treg; | |
7728 | else | |
8fc2e39e TS |
7729 | { |
7730 | used_at = 1; | |
7731 | tempreg = AT; | |
7732 | } | |
252b5132 RH |
7733 | if (! target_big_endian) |
7734 | offset_expr.X_add_number += off; | |
67c0d1eb | 7735 | macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7736 | if (! target_big_endian) |
7737 | offset_expr.X_add_number -= off; | |
7738 | else | |
7739 | offset_expr.X_add_number += off; | |
67c0d1eb | 7740 | macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
af22f5b2 CD |
7741 | |
7742 | /* If necessary, move the result in tempreg the final destination. */ | |
7743 | if (treg == tempreg) | |
8fc2e39e | 7744 | break; |
af22f5b2 | 7745 | /* Protect second load's delay slot. */ |
017315e4 | 7746 | load_delay_nop (); |
67c0d1eb | 7747 | move_register (treg, tempreg); |
af22f5b2 | 7748 | break; |
252b5132 RH |
7749 | |
7750 | case M_ULD_A: | |
7751 | s = "ldl"; | |
7752 | s2 = "ldr"; | |
7753 | off = 7; | |
7754 | goto ulwa; | |
7755 | case M_ULW_A: | |
7756 | s = "lwl"; | |
7757 | s2 = "lwr"; | |
7758 | off = 3; | |
7759 | ulwa: | |
d6bc6245 | 7760 | used_at = 1; |
67c0d1eb | 7761 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7762 | if (breg != 0) |
67c0d1eb | 7763 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7764 | if (! target_big_endian) |
7765 | expr1.X_add_number = off; | |
7766 | else | |
7767 | expr1.X_add_number = 0; | |
67c0d1eb | 7768 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7769 | if (! target_big_endian) |
7770 | expr1.X_add_number = 0; | |
7771 | else | |
7772 | expr1.X_add_number = off; | |
67c0d1eb | 7773 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7774 | break; |
7775 | ||
7776 | case M_ULH_A: | |
7777 | case M_ULHU_A: | |
d6bc6245 | 7778 | used_at = 1; |
67c0d1eb | 7779 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7780 | if (breg != 0) |
67c0d1eb | 7781 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7782 | if (target_big_endian) |
7783 | expr1.X_add_number = 0; | |
67c0d1eb | 7784 | macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", |
17a2f251 | 7785 | treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7786 | if (target_big_endian) |
7787 | expr1.X_add_number = 1; | |
7788 | else | |
7789 | expr1.X_add_number = 0; | |
67c0d1eb RS |
7790 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
7791 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
7792 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7793 | break; |
7794 | ||
7795 | case M_USH: | |
8fc2e39e | 7796 | used_at = 1; |
252b5132 RH |
7797 | if (offset_expr.X_add_number >= 0x7fff) |
7798 | as_bad (_("operand overflow")); | |
7799 | if (target_big_endian) | |
f9419b05 | 7800 | ++offset_expr.X_add_number; |
67c0d1eb RS |
7801 | macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
7802 | macro_build (NULL, "srl", "d,w,<", AT, treg, 8); | |
252b5132 | 7803 | if (target_big_endian) |
f9419b05 | 7804 | --offset_expr.X_add_number; |
252b5132 | 7805 | else |
f9419b05 | 7806 | ++offset_expr.X_add_number; |
67c0d1eb | 7807 | macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 RH |
7808 | break; |
7809 | ||
7810 | case M_USD: | |
7811 | s = "sdl"; | |
7812 | s2 = "sdr"; | |
7813 | off = 7; | |
7814 | goto usw; | |
7815 | case M_USW: | |
7816 | s = "swl"; | |
7817 | s2 = "swr"; | |
7818 | off = 3; | |
7819 | usw: | |
7820 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7821 | as_bad (_("operand overflow")); | |
7822 | if (! target_big_endian) | |
7823 | offset_expr.X_add_number += off; | |
67c0d1eb | 7824 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7825 | if (! target_big_endian) |
7826 | offset_expr.X_add_number -= off; | |
7827 | else | |
7828 | offset_expr.X_add_number += off; | |
67c0d1eb | 7829 | macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
8fc2e39e | 7830 | break; |
252b5132 RH |
7831 | |
7832 | case M_USD_A: | |
7833 | s = "sdl"; | |
7834 | s2 = "sdr"; | |
7835 | off = 7; | |
7836 | goto uswa; | |
7837 | case M_USW_A: | |
7838 | s = "swl"; | |
7839 | s2 = "swr"; | |
7840 | off = 3; | |
7841 | uswa: | |
d6bc6245 | 7842 | used_at = 1; |
67c0d1eb | 7843 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7844 | if (breg != 0) |
67c0d1eb | 7845 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7846 | if (! target_big_endian) |
7847 | expr1.X_add_number = off; | |
7848 | else | |
7849 | expr1.X_add_number = 0; | |
67c0d1eb | 7850 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7851 | if (! target_big_endian) |
7852 | expr1.X_add_number = 0; | |
7853 | else | |
7854 | expr1.X_add_number = off; | |
67c0d1eb | 7855 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7856 | break; |
7857 | ||
7858 | case M_USH_A: | |
d6bc6245 | 7859 | used_at = 1; |
67c0d1eb | 7860 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7861 | if (breg != 0) |
67c0d1eb | 7862 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7863 | if (! target_big_endian) |
7864 | expr1.X_add_number = 0; | |
67c0d1eb RS |
7865 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
7866 | macro_build (NULL, "srl", "d,w,<", treg, treg, 8); | |
252b5132 RH |
7867 | if (! target_big_endian) |
7868 | expr1.X_add_number = 1; | |
7869 | else | |
7870 | expr1.X_add_number = 0; | |
67c0d1eb | 7871 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7872 | if (! target_big_endian) |
7873 | expr1.X_add_number = 0; | |
7874 | else | |
7875 | expr1.X_add_number = 1; | |
67c0d1eb RS |
7876 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
7877 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
7878 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7879 | break; |
7880 | ||
7881 | default: | |
7882 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 7883 | are added dynamically. */ |
252b5132 RH |
7884 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
7885 | break; | |
7886 | } | |
8fc2e39e TS |
7887 | if (mips_opts.noat && used_at) |
7888 | as_bad (_("Macro used $at after \".set noat\"")); | |
252b5132 RH |
7889 | } |
7890 | ||
7891 | /* Implement macros in mips16 mode. */ | |
7892 | ||
7893 | static void | |
17a2f251 | 7894 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 RH |
7895 | { |
7896 | int mask; | |
7897 | int xreg, yreg, zreg, tmp; | |
252b5132 RH |
7898 | expressionS expr1; |
7899 | int dbl; | |
7900 | const char *s, *s2, *s3; | |
7901 | ||
7902 | mask = ip->insn_mo->mask; | |
7903 | ||
bf12938e RS |
7904 | xreg = MIPS16_EXTRACT_OPERAND (RX, *ip); |
7905 | yreg = MIPS16_EXTRACT_OPERAND (RY, *ip); | |
7906 | zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip); | |
252b5132 | 7907 | |
252b5132 RH |
7908 | expr1.X_op = O_constant; |
7909 | expr1.X_op_symbol = NULL; | |
7910 | expr1.X_add_symbol = NULL; | |
7911 | expr1.X_add_number = 1; | |
7912 | ||
7913 | dbl = 0; | |
7914 | ||
7915 | switch (mask) | |
7916 | { | |
7917 | default: | |
7918 | internalError (); | |
7919 | ||
7920 | case M_DDIV_3: | |
7921 | dbl = 1; | |
7922 | case M_DIV_3: | |
7923 | s = "mflo"; | |
7924 | goto do_div3; | |
7925 | case M_DREM_3: | |
7926 | dbl = 1; | |
7927 | case M_REM_3: | |
7928 | s = "mfhi"; | |
7929 | do_div3: | |
7d10b47d | 7930 | start_noreorder (); |
67c0d1eb | 7931 | macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg); |
252b5132 | 7932 | expr1.X_add_number = 2; |
67c0d1eb RS |
7933 | macro_build (&expr1, "bnez", "x,p", yreg); |
7934 | macro_build (NULL, "break", "6", 7); | |
bdaaa2e1 | 7935 | |
252b5132 RH |
7936 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
7937 | since that causes an overflow. We should do that as well, | |
7938 | but I don't see how to do the comparisons without a temporary | |
7939 | register. */ | |
7d10b47d | 7940 | end_noreorder (); |
67c0d1eb | 7941 | macro_build (NULL, s, "x", zreg); |
252b5132 RH |
7942 | break; |
7943 | ||
7944 | case M_DIVU_3: | |
7945 | s = "divu"; | |
7946 | s2 = "mflo"; | |
7947 | goto do_divu3; | |
7948 | case M_REMU_3: | |
7949 | s = "divu"; | |
7950 | s2 = "mfhi"; | |
7951 | goto do_divu3; | |
7952 | case M_DDIVU_3: | |
7953 | s = "ddivu"; | |
7954 | s2 = "mflo"; | |
7955 | goto do_divu3; | |
7956 | case M_DREMU_3: | |
7957 | s = "ddivu"; | |
7958 | s2 = "mfhi"; | |
7959 | do_divu3: | |
7d10b47d | 7960 | start_noreorder (); |
67c0d1eb | 7961 | macro_build (NULL, s, "0,x,y", xreg, yreg); |
252b5132 | 7962 | expr1.X_add_number = 2; |
67c0d1eb RS |
7963 | macro_build (&expr1, "bnez", "x,p", yreg); |
7964 | macro_build (NULL, "break", "6", 7); | |
7d10b47d | 7965 | end_noreorder (); |
67c0d1eb | 7966 | macro_build (NULL, s2, "x", zreg); |
252b5132 RH |
7967 | break; |
7968 | ||
7969 | case M_DMUL: | |
7970 | dbl = 1; | |
7971 | case M_MUL: | |
67c0d1eb RS |
7972 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
7973 | macro_build (NULL, "mflo", "x", zreg); | |
8fc2e39e | 7974 | break; |
252b5132 RH |
7975 | |
7976 | case M_DSUBU_I: | |
7977 | dbl = 1; | |
7978 | goto do_subu; | |
7979 | case M_SUBU_I: | |
7980 | do_subu: | |
7981 | if (imm_expr.X_op != O_constant) | |
7982 | as_bad (_("Unsupported large constant")); | |
7983 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7984 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
7985 | break; |
7986 | ||
7987 | case M_SUBU_I_2: | |
7988 | if (imm_expr.X_op != O_constant) | |
7989 | as_bad (_("Unsupported large constant")); | |
7990 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7991 | macro_build (&imm_expr, "addiu", "x,k", xreg); |
252b5132 RH |
7992 | break; |
7993 | ||
7994 | case M_DSUBU_I_2: | |
7995 | if (imm_expr.X_op != O_constant) | |
7996 | as_bad (_("Unsupported large constant")); | |
7997 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7998 | macro_build (&imm_expr, "daddiu", "y,j", yreg); |
252b5132 RH |
7999 | break; |
8000 | ||
8001 | case M_BEQ: | |
8002 | s = "cmp"; | |
8003 | s2 = "bteqz"; | |
8004 | goto do_branch; | |
8005 | case M_BNE: | |
8006 | s = "cmp"; | |
8007 | s2 = "btnez"; | |
8008 | goto do_branch; | |
8009 | case M_BLT: | |
8010 | s = "slt"; | |
8011 | s2 = "btnez"; | |
8012 | goto do_branch; | |
8013 | case M_BLTU: | |
8014 | s = "sltu"; | |
8015 | s2 = "btnez"; | |
8016 | goto do_branch; | |
8017 | case M_BLE: | |
8018 | s = "slt"; | |
8019 | s2 = "bteqz"; | |
8020 | goto do_reverse_branch; | |
8021 | case M_BLEU: | |
8022 | s = "sltu"; | |
8023 | s2 = "bteqz"; | |
8024 | goto do_reverse_branch; | |
8025 | case M_BGE: | |
8026 | s = "slt"; | |
8027 | s2 = "bteqz"; | |
8028 | goto do_branch; | |
8029 | case M_BGEU: | |
8030 | s = "sltu"; | |
8031 | s2 = "bteqz"; | |
8032 | goto do_branch; | |
8033 | case M_BGT: | |
8034 | s = "slt"; | |
8035 | s2 = "btnez"; | |
8036 | goto do_reverse_branch; | |
8037 | case M_BGTU: | |
8038 | s = "sltu"; | |
8039 | s2 = "btnez"; | |
8040 | ||
8041 | do_reverse_branch: | |
8042 | tmp = xreg; | |
8043 | xreg = yreg; | |
8044 | yreg = tmp; | |
8045 | ||
8046 | do_branch: | |
67c0d1eb RS |
8047 | macro_build (NULL, s, "x,y", xreg, yreg); |
8048 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
8049 | break; |
8050 | ||
8051 | case M_BEQ_I: | |
8052 | s = "cmpi"; | |
8053 | s2 = "bteqz"; | |
8054 | s3 = "x,U"; | |
8055 | goto do_branch_i; | |
8056 | case M_BNE_I: | |
8057 | s = "cmpi"; | |
8058 | s2 = "btnez"; | |
8059 | s3 = "x,U"; | |
8060 | goto do_branch_i; | |
8061 | case M_BLT_I: | |
8062 | s = "slti"; | |
8063 | s2 = "btnez"; | |
8064 | s3 = "x,8"; | |
8065 | goto do_branch_i; | |
8066 | case M_BLTU_I: | |
8067 | s = "sltiu"; | |
8068 | s2 = "btnez"; | |
8069 | s3 = "x,8"; | |
8070 | goto do_branch_i; | |
8071 | case M_BLE_I: | |
8072 | s = "slti"; | |
8073 | s2 = "btnez"; | |
8074 | s3 = "x,8"; | |
8075 | goto do_addone_branch_i; | |
8076 | case M_BLEU_I: | |
8077 | s = "sltiu"; | |
8078 | s2 = "btnez"; | |
8079 | s3 = "x,8"; | |
8080 | goto do_addone_branch_i; | |
8081 | case M_BGE_I: | |
8082 | s = "slti"; | |
8083 | s2 = "bteqz"; | |
8084 | s3 = "x,8"; | |
8085 | goto do_branch_i; | |
8086 | case M_BGEU_I: | |
8087 | s = "sltiu"; | |
8088 | s2 = "bteqz"; | |
8089 | s3 = "x,8"; | |
8090 | goto do_branch_i; | |
8091 | case M_BGT_I: | |
8092 | s = "slti"; | |
8093 | s2 = "bteqz"; | |
8094 | s3 = "x,8"; | |
8095 | goto do_addone_branch_i; | |
8096 | case M_BGTU_I: | |
8097 | s = "sltiu"; | |
8098 | s2 = "bteqz"; | |
8099 | s3 = "x,8"; | |
8100 | ||
8101 | do_addone_branch_i: | |
8102 | if (imm_expr.X_op != O_constant) | |
8103 | as_bad (_("Unsupported large constant")); | |
8104 | ++imm_expr.X_add_number; | |
8105 | ||
8106 | do_branch_i: | |
67c0d1eb RS |
8107 | macro_build (&imm_expr, s, s3, xreg); |
8108 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
8109 | break; |
8110 | ||
8111 | case M_ABS: | |
8112 | expr1.X_add_number = 0; | |
67c0d1eb | 8113 | macro_build (&expr1, "slti", "x,8", yreg); |
252b5132 | 8114 | if (xreg != yreg) |
67c0d1eb | 8115 | move_register (xreg, yreg); |
252b5132 | 8116 | expr1.X_add_number = 2; |
67c0d1eb RS |
8117 | macro_build (&expr1, "bteqz", "p"); |
8118 | macro_build (NULL, "neg", "x,w", xreg, xreg); | |
252b5132 RH |
8119 | } |
8120 | } | |
8121 | ||
8122 | /* For consistency checking, verify that all bits are specified either | |
8123 | by the match/mask part of the instruction definition, or by the | |
8124 | operand list. */ | |
8125 | static int | |
17a2f251 | 8126 | validate_mips_insn (const struct mips_opcode *opc) |
252b5132 RH |
8127 | { |
8128 | const char *p = opc->args; | |
8129 | char c; | |
8130 | unsigned long used_bits = opc->mask; | |
8131 | ||
8132 | if ((used_bits & opc->match) != opc->match) | |
8133 | { | |
8134 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
8135 | opc->name, opc->args); | |
8136 | return 0; | |
8137 | } | |
8138 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
8139 | while (*p) | |
8140 | switch (c = *p++) | |
8141 | { | |
8142 | case ',': break; | |
8143 | case '(': break; | |
8144 | case ')': break; | |
af7ee8bf CD |
8145 | case '+': |
8146 | switch (c = *p++) | |
8147 | { | |
9bcd4f99 TS |
8148 | case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break; |
8149 | case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break; | |
8150 | case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break; | |
8151 | case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break; | |
af7ee8bf CD |
8152 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8153 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
8154 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
bbcc0807 CD |
8155 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); |
8156 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
5f74bc13 CD |
8157 | case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8158 | case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
8159 | case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
8160 | case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
8161 | case 'I': break; | |
ef2e4d86 CF |
8162 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; |
8163 | case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT); | |
8164 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
af7ee8bf CD |
8165 | default: |
8166 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
8167 | c, opc->name, opc->args); | |
8168 | return 0; | |
8169 | } | |
8170 | break; | |
252b5132 RH |
8171 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
8172 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
8173 | case 'A': break; | |
4372b673 | 8174 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
8175 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
8176 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
8177 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8178 | case 'F': break; | |
8179 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 8180 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 8181 | case 'I': break; |
e972090a | 8182 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 8183 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
8184 | case 'L': break; |
8185 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
8186 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
8187 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
8188 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
8189 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
8190 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
8191 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8192 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
8193 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8194 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
8195 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
8196 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
8197 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
8198 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
8199 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8200 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
8201 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
8202 | case 'f': break; | |
8203 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
8204 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
8205 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8206 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
8207 | case 'l': break; | |
8208 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8209 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
8210 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
8211 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8212 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8213 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8214 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
8215 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8216 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
8217 | case 'x': break; | |
8218 | case 'z': break; | |
8219 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
8220 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
8221 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
8222 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
8223 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
8224 | case '[': break; | |
8225 | case ']': break; | |
74cd071d CF |
8226 | case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break; |
8227 | case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break; | |
8228 | case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break; | |
8229 | case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
8230 | case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break; | |
8231 | case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break; | |
8232 | case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break; | |
8233 | case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break; | |
8234 | case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break; | |
8235 | case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break; | |
8236 | case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break; | |
ef2e4d86 CF |
8237 | case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break; |
8238 | case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break; | |
8239 | case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break; | |
8240 | case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break; | |
8241 | case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
252b5132 RH |
8242 | default: |
8243 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
8244 | c, opc->name, opc->args); | |
8245 | return 0; | |
8246 | } | |
8247 | #undef USE_BITS | |
8248 | if (used_bits != 0xffffffff) | |
8249 | { | |
8250 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
8251 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
8252 | return 0; | |
8253 | } | |
8254 | return 1; | |
8255 | } | |
8256 | ||
9bcd4f99 TS |
8257 | /* UDI immediates. */ |
8258 | struct mips_immed { | |
8259 | char type; | |
8260 | unsigned int shift; | |
8261 | unsigned long mask; | |
8262 | const char * desc; | |
8263 | }; | |
8264 | ||
8265 | static const struct mips_immed mips_immed[] = { | |
8266 | { '1', OP_SH_UDI1, OP_MASK_UDI1, 0}, | |
8267 | { '2', OP_SH_UDI2, OP_MASK_UDI2, 0}, | |
8268 | { '3', OP_SH_UDI3, OP_MASK_UDI3, 0}, | |
8269 | { '4', OP_SH_UDI4, OP_MASK_UDI4, 0}, | |
8270 | { 0,0,0,0 } | |
8271 | }; | |
8272 | ||
7455baf8 TS |
8273 | /* Check whether an odd floating-point register is allowed. */ |
8274 | static int | |
8275 | mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum) | |
8276 | { | |
8277 | const char *s = insn->name; | |
8278 | ||
8279 | if (insn->pinfo == INSN_MACRO) | |
8280 | /* Let a macro pass, we'll catch it later when it is expanded. */ | |
8281 | return 1; | |
8282 | ||
8283 | if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa)) | |
8284 | { | |
8285 | /* Allow odd registers for single-precision ops. */ | |
8286 | switch (insn->pinfo & (FP_S | FP_D)) | |
8287 | { | |
8288 | case FP_S: | |
8289 | case 0: | |
8290 | return 1; /* both single precision - ok */ | |
8291 | case FP_D: | |
8292 | return 0; /* both double precision - fail */ | |
8293 | default: | |
8294 | break; | |
8295 | } | |
8296 | ||
8297 | /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ | |
8298 | s = strchr (insn->name, '.'); | |
8299 | if (argnum == 2) | |
8300 | s = s != NULL ? strchr (s + 1, '.') : NULL; | |
8301 | return (s != NULL && (s[1] == 'w' || s[1] == 's')); | |
8302 | } | |
8303 | ||
8304 | /* Single-precision coprocessor loads and moves are OK too. */ | |
8305 | if ((insn->pinfo & FP_S) | |
8306 | && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY | |
8307 | | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY))) | |
8308 | return 1; | |
8309 | ||
8310 | return 0; | |
8311 | } | |
8312 | ||
252b5132 RH |
8313 | /* This routine assembles an instruction into its binary format. As a |
8314 | side effect, it sets one of the global variables imm_reloc or | |
8315 | offset_reloc to the type of relocation to do if one of the operands | |
8316 | is an address expression. */ | |
8317 | ||
8318 | static void | |
17a2f251 | 8319 | mips_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
8320 | { |
8321 | char *s; | |
8322 | const char *args; | |
43841e91 | 8323 | char c = 0; |
252b5132 RH |
8324 | struct mips_opcode *insn; |
8325 | char *argsStart; | |
8326 | unsigned int regno; | |
8327 | unsigned int lastregno = 0; | |
af7ee8bf | 8328 | unsigned int lastpos = 0; |
071742cf | 8329 | unsigned int limlo, limhi; |
252b5132 RH |
8330 | char *s_reset; |
8331 | char save_c = 0; | |
74cd071d | 8332 | offsetT min_range, max_range; |
707bfff6 TS |
8333 | int argnum; |
8334 | unsigned int rtype; | |
252b5132 RH |
8335 | |
8336 | insn_error = NULL; | |
8337 | ||
8338 | /* If the instruction contains a '.', we first try to match an instruction | |
8339 | including the '.'. Then we try again without the '.'. */ | |
8340 | insn = NULL; | |
3882b010 | 8341 | for (s = str; *s != '\0' && !ISSPACE (*s); ++s) |
252b5132 RH |
8342 | continue; |
8343 | ||
8344 | /* If we stopped on whitespace, then replace the whitespace with null for | |
8345 | the call to hash_find. Save the character we replaced just in case we | |
8346 | have to re-parse the instruction. */ | |
3882b010 | 8347 | if (ISSPACE (*s)) |
252b5132 RH |
8348 | { |
8349 | save_c = *s; | |
8350 | *s++ = '\0'; | |
8351 | } | |
bdaaa2e1 | 8352 | |
252b5132 RH |
8353 | insn = (struct mips_opcode *) hash_find (op_hash, str); |
8354 | ||
8355 | /* If we didn't find the instruction in the opcode table, try again, but | |
8356 | this time with just the instruction up to, but not including the | |
8357 | first '.'. */ | |
8358 | if (insn == NULL) | |
8359 | { | |
bdaaa2e1 | 8360 | /* Restore the character we overwrite above (if any). */ |
252b5132 RH |
8361 | if (save_c) |
8362 | *(--s) = save_c; | |
8363 | ||
8364 | /* Scan up to the first '.' or whitespace. */ | |
3882b010 L |
8365 | for (s = str; |
8366 | *s != '\0' && *s != '.' && !ISSPACE (*s); | |
8367 | ++s) | |
252b5132 RH |
8368 | continue; |
8369 | ||
8370 | /* If we did not find a '.', then we can quit now. */ | |
8371 | if (*s != '.') | |
8372 | { | |
8373 | insn_error = "unrecognized opcode"; | |
8374 | return; | |
8375 | } | |
8376 | ||
8377 | /* Lookup the instruction in the hash table. */ | |
8378 | *s++ = '\0'; | |
8379 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
8380 | { | |
8381 | insn_error = "unrecognized opcode"; | |
8382 | return; | |
8383 | } | |
252b5132 RH |
8384 | } |
8385 | ||
8386 | argsStart = s; | |
8387 | for (;;) | |
8388 | { | |
b34976b6 | 8389 | bfd_boolean ok; |
252b5132 RH |
8390 | |
8391 | assert (strcmp (insn->name, str) == 0); | |
8392 | ||
1f25f5d3 CD |
8393 | if (OPCODE_IS_MEMBER (insn, |
8394 | (mips_opts.isa | |
9b3f89ee TS |
8395 | /* We don't check for mips_opts.mips16 here since |
8396 | we want to allow jalx if -mips16 was specified | |
8397 | on the command line. */ | |
3396de36 | 8398 | | (file_ase_mips16 ? INSN_MIPS16 : 0) |
deec1734 | 8399 | | (mips_opts.ase_mdmx ? INSN_MDMX : 0) |
74cd071d | 8400 | | (mips_opts.ase_dsp ? INSN_DSP : 0) |
65263ce3 TS |
8401 | | ((mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE) |
8402 | ? INSN_DSP64 : 0) | |
ef2e4d86 | 8403 | | (mips_opts.ase_mt ? INSN_MT : 0) |
e16bfa71 TS |
8404 | | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0) |
8405 | | (mips_opts.ase_smartmips ? INSN_SMARTMIPS : 0)), | |
fef14a42 | 8406 | mips_opts.arch)) |
b34976b6 | 8407 | ok = TRUE; |
bdaaa2e1 | 8408 | else |
b34976b6 | 8409 | ok = FALSE; |
bdaaa2e1 | 8410 | |
252b5132 RH |
8411 | if (insn->pinfo != INSN_MACRO) |
8412 | { | |
fef14a42 | 8413 | if (mips_opts.arch == CPU_R4650 && (insn->pinfo & FP_D) != 0) |
b34976b6 | 8414 | ok = FALSE; |
252b5132 RH |
8415 | } |
8416 | ||
8417 | if (! ok) | |
8418 | { | |
8419 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
8420 | && strcmp (insn->name, insn[1].name) == 0) | |
8421 | { | |
8422 | ++insn; | |
8423 | continue; | |
8424 | } | |
252b5132 | 8425 | else |
beae10d5 | 8426 | { |
268f6bed L |
8427 | if (!insn_error) |
8428 | { | |
8429 | static char buf[100]; | |
fef14a42 TS |
8430 | sprintf (buf, |
8431 | _("opcode not supported on this processor: %s (%s)"), | |
8432 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
8433 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
268f6bed L |
8434 | insn_error = buf; |
8435 | } | |
8436 | if (save_c) | |
8437 | *(--s) = save_c; | |
2bd7f1f3 | 8438 | return; |
252b5132 | 8439 | } |
252b5132 RH |
8440 | } |
8441 | ||
1e915849 | 8442 | create_insn (ip, insn); |
268f6bed | 8443 | insn_error = NULL; |
707bfff6 | 8444 | argnum = 1; |
252b5132 RH |
8445 | for (args = insn->args;; ++args) |
8446 | { | |
deec1734 CD |
8447 | int is_mdmx; |
8448 | ||
ad8d3bb3 | 8449 | s += strspn (s, " \t"); |
deec1734 | 8450 | is_mdmx = 0; |
252b5132 RH |
8451 | switch (*args) |
8452 | { | |
8453 | case '\0': /* end of args */ | |
8454 | if (*s == '\0') | |
8455 | return; | |
8456 | break; | |
8457 | ||
74cd071d CF |
8458 | case '3': /* dsp 3-bit unsigned immediate in bit 21 */ |
8459 | my_getExpression (&imm_expr, s); | |
8460 | check_absolute_expr (ip, &imm_expr); | |
8461 | if (imm_expr.X_add_number & ~OP_MASK_SA3) | |
8462 | { | |
a9e24354 TS |
8463 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8464 | OP_MASK_SA3, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8465 | } |
a9e24354 | 8466 | INSERT_OPERAND (SA3, *ip, imm_expr.X_add_number); |
74cd071d CF |
8467 | imm_expr.X_op = O_absent; |
8468 | s = expr_end; | |
8469 | continue; | |
8470 | ||
8471 | case '4': /* dsp 4-bit unsigned immediate in bit 21 */ | |
8472 | my_getExpression (&imm_expr, s); | |
8473 | check_absolute_expr (ip, &imm_expr); | |
8474 | if (imm_expr.X_add_number & ~OP_MASK_SA4) | |
8475 | { | |
a9e24354 TS |
8476 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8477 | OP_MASK_SA4, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8478 | } |
a9e24354 | 8479 | INSERT_OPERAND (SA4, *ip, imm_expr.X_add_number); |
74cd071d CF |
8480 | imm_expr.X_op = O_absent; |
8481 | s = expr_end; | |
8482 | continue; | |
8483 | ||
8484 | case '5': /* dsp 8-bit unsigned immediate in bit 16 */ | |
8485 | my_getExpression (&imm_expr, s); | |
8486 | check_absolute_expr (ip, &imm_expr); | |
8487 | if (imm_expr.X_add_number & ~OP_MASK_IMM8) | |
8488 | { | |
a9e24354 TS |
8489 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8490 | OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8491 | } |
a9e24354 | 8492 | INSERT_OPERAND (IMM8, *ip, imm_expr.X_add_number); |
74cd071d CF |
8493 | imm_expr.X_op = O_absent; |
8494 | s = expr_end; | |
8495 | continue; | |
8496 | ||
8497 | case '6': /* dsp 5-bit unsigned immediate in bit 21 */ | |
8498 | my_getExpression (&imm_expr, s); | |
8499 | check_absolute_expr (ip, &imm_expr); | |
8500 | if (imm_expr.X_add_number & ~OP_MASK_RS) | |
8501 | { | |
a9e24354 TS |
8502 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8503 | OP_MASK_RS, (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8504 | } |
a9e24354 | 8505 | INSERT_OPERAND (RS, *ip, imm_expr.X_add_number); |
74cd071d CF |
8506 | imm_expr.X_op = O_absent; |
8507 | s = expr_end; | |
8508 | continue; | |
8509 | ||
8510 | case '7': /* four dsp accumulators in bits 11,12 */ | |
8511 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
8512 | s[3] >= '0' && s[3] <= '3') | |
8513 | { | |
8514 | regno = s[3] - '0'; | |
8515 | s += 4; | |
a9e24354 | 8516 | INSERT_OPERAND (DSPACC, *ip, regno); |
74cd071d CF |
8517 | continue; |
8518 | } | |
8519 | else | |
8520 | as_bad (_("Invalid dsp acc register")); | |
8521 | break; | |
8522 | ||
8523 | case '8': /* dsp 6-bit unsigned immediate in bit 11 */ | |
8524 | my_getExpression (&imm_expr, s); | |
8525 | check_absolute_expr (ip, &imm_expr); | |
8526 | if (imm_expr.X_add_number & ~OP_MASK_WRDSP) | |
8527 | { | |
a9e24354 TS |
8528 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8529 | OP_MASK_WRDSP, | |
8530 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8531 | } |
a9e24354 | 8532 | INSERT_OPERAND (WRDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
8533 | imm_expr.X_op = O_absent; |
8534 | s = expr_end; | |
8535 | continue; | |
8536 | ||
8537 | case '9': /* four dsp accumulators in bits 21,22 */ | |
8538 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
8539 | s[3] >= '0' && s[3] <= '3') | |
8540 | { | |
8541 | regno = s[3] - '0'; | |
8542 | s += 4; | |
a9e24354 | 8543 | INSERT_OPERAND (DSPACC_S, *ip, regno); |
74cd071d CF |
8544 | continue; |
8545 | } | |
8546 | else | |
8547 | as_bad (_("Invalid dsp acc register")); | |
8548 | break; | |
8549 | ||
8550 | case '0': /* dsp 6-bit signed immediate in bit 20 */ | |
8551 | my_getExpression (&imm_expr, s); | |
8552 | check_absolute_expr (ip, &imm_expr); | |
8553 | min_range = -((OP_MASK_DSPSFT + 1) >> 1); | |
8554 | max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1; | |
8555 | if (imm_expr.X_add_number < min_range || | |
8556 | imm_expr.X_add_number > max_range) | |
8557 | { | |
a9e24354 TS |
8558 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
8559 | (long) min_range, (long) max_range, | |
8560 | (long) imm_expr.X_add_number); | |
74cd071d | 8561 | } |
a9e24354 | 8562 | INSERT_OPERAND (DSPSFT, *ip, imm_expr.X_add_number); |
74cd071d CF |
8563 | imm_expr.X_op = O_absent; |
8564 | s = expr_end; | |
8565 | continue; | |
8566 | ||
8567 | case '\'': /* dsp 6-bit unsigned immediate in bit 16 */ | |
8568 | my_getExpression (&imm_expr, s); | |
8569 | check_absolute_expr (ip, &imm_expr); | |
8570 | if (imm_expr.X_add_number & ~OP_MASK_RDDSP) | |
8571 | { | |
a9e24354 TS |
8572 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
8573 | OP_MASK_RDDSP, | |
8574 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 8575 | } |
a9e24354 | 8576 | INSERT_OPERAND (RDDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
8577 | imm_expr.X_op = O_absent; |
8578 | s = expr_end; | |
8579 | continue; | |
8580 | ||
8581 | case ':': /* dsp 7-bit signed immediate in bit 19 */ | |
8582 | my_getExpression (&imm_expr, s); | |
8583 | check_absolute_expr (ip, &imm_expr); | |
8584 | min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1); | |
8585 | max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1; | |
8586 | if (imm_expr.X_add_number < min_range || | |
8587 | imm_expr.X_add_number > max_range) | |
8588 | { | |
a9e24354 TS |
8589 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
8590 | (long) min_range, (long) max_range, | |
8591 | (long) imm_expr.X_add_number); | |
74cd071d | 8592 | } |
a9e24354 | 8593 | INSERT_OPERAND (DSPSFT_7, *ip, imm_expr.X_add_number); |
74cd071d CF |
8594 | imm_expr.X_op = O_absent; |
8595 | s = expr_end; | |
8596 | continue; | |
8597 | ||
8598 | case '@': /* dsp 10-bit signed immediate in bit 16 */ | |
8599 | my_getExpression (&imm_expr, s); | |
8600 | check_absolute_expr (ip, &imm_expr); | |
8601 | min_range = -((OP_MASK_IMM10 + 1) >> 1); | |
8602 | max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1; | |
8603 | if (imm_expr.X_add_number < min_range || | |
8604 | imm_expr.X_add_number > max_range) | |
8605 | { | |
a9e24354 TS |
8606 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
8607 | (long) min_range, (long) max_range, | |
8608 | (long) imm_expr.X_add_number); | |
74cd071d | 8609 | } |
a9e24354 | 8610 | INSERT_OPERAND (IMM10, *ip, imm_expr.X_add_number); |
74cd071d CF |
8611 | imm_expr.X_op = O_absent; |
8612 | s = expr_end; | |
8613 | continue; | |
8614 | ||
a9e24354 | 8615 | case '!': /* MT usermode flag bit. */ |
ef2e4d86 CF |
8616 | my_getExpression (&imm_expr, s); |
8617 | check_absolute_expr (ip, &imm_expr); | |
8618 | if (imm_expr.X_add_number & ~OP_MASK_MT_U) | |
a9e24354 TS |
8619 | as_bad (_("MT usermode bit not 0 or 1 (%lu)"), |
8620 | (unsigned long) imm_expr.X_add_number); | |
8621 | INSERT_OPERAND (MT_U, *ip, imm_expr.X_add_number); | |
ef2e4d86 CF |
8622 | imm_expr.X_op = O_absent; |
8623 | s = expr_end; | |
8624 | continue; | |
8625 | ||
a9e24354 | 8626 | case '$': /* MT load high flag bit. */ |
ef2e4d86 CF |
8627 | my_getExpression (&imm_expr, s); |
8628 | check_absolute_expr (ip, &imm_expr); | |
8629 | if (imm_expr.X_add_number & ~OP_MASK_MT_H) | |
a9e24354 TS |
8630 | as_bad (_("MT load high bit not 0 or 1 (%lu)"), |
8631 | (unsigned long) imm_expr.X_add_number); | |
8632 | INSERT_OPERAND (MT_H, *ip, imm_expr.X_add_number); | |
ef2e4d86 CF |
8633 | imm_expr.X_op = O_absent; |
8634 | s = expr_end; | |
8635 | continue; | |
8636 | ||
8637 | case '*': /* four dsp accumulators in bits 18,19 */ | |
8638 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
8639 | s[3] >= '0' && s[3] <= '3') | |
8640 | { | |
8641 | regno = s[3] - '0'; | |
8642 | s += 4; | |
a9e24354 | 8643 | INSERT_OPERAND (MTACC_T, *ip, regno); |
ef2e4d86 CF |
8644 | continue; |
8645 | } | |
8646 | else | |
8647 | as_bad (_("Invalid dsp/smartmips acc register")); | |
8648 | break; | |
8649 | ||
8650 | case '&': /* four dsp accumulators in bits 13,14 */ | |
8651 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && | |
8652 | s[3] >= '0' && s[3] <= '3') | |
8653 | { | |
8654 | regno = s[3] - '0'; | |
8655 | s += 4; | |
a9e24354 | 8656 | INSERT_OPERAND (MTACC_D, *ip, regno); |
ef2e4d86 CF |
8657 | continue; |
8658 | } | |
8659 | else | |
8660 | as_bad (_("Invalid dsp/smartmips acc register")); | |
8661 | break; | |
8662 | ||
252b5132 | 8663 | case ',': |
a339155f | 8664 | ++argnum; |
252b5132 RH |
8665 | if (*s++ == *args) |
8666 | continue; | |
8667 | s--; | |
8668 | switch (*++args) | |
8669 | { | |
8670 | case 'r': | |
8671 | case 'v': | |
bf12938e | 8672 | INSERT_OPERAND (RS, *ip, lastregno); |
252b5132 RH |
8673 | continue; |
8674 | ||
8675 | case 'w': | |
bf12938e | 8676 | INSERT_OPERAND (RT, *ip, lastregno); |
38487616 TS |
8677 | continue; |
8678 | ||
252b5132 | 8679 | case 'W': |
bf12938e | 8680 | INSERT_OPERAND (FT, *ip, lastregno); |
252b5132 RH |
8681 | continue; |
8682 | ||
8683 | case 'V': | |
bf12938e | 8684 | INSERT_OPERAND (FS, *ip, lastregno); |
252b5132 RH |
8685 | continue; |
8686 | } | |
8687 | break; | |
8688 | ||
8689 | case '(': | |
8690 | /* Handle optional base register. | |
8691 | Either the base register is omitted or | |
bdaaa2e1 | 8692 | we must have a left paren. */ |
252b5132 RH |
8693 | /* This is dependent on the next operand specifier |
8694 | is a base register specification. */ | |
8695 | assert (args[1] == 'b' || args[1] == '5' | |
8696 | || args[1] == '-' || args[1] == '4'); | |
8697 | if (*s == '\0') | |
8698 | return; | |
8699 | ||
8700 | case ')': /* these must match exactly */ | |
60b63b72 RS |
8701 | case '[': |
8702 | case ']': | |
252b5132 RH |
8703 | if (*s++ == *args) |
8704 | continue; | |
8705 | break; | |
8706 | ||
af7ee8bf CD |
8707 | case '+': /* Opcode extension character. */ |
8708 | switch (*++args) | |
8709 | { | |
9bcd4f99 TS |
8710 | case '1': /* UDI immediates. */ |
8711 | case '2': | |
8712 | case '3': | |
8713 | case '4': | |
8714 | { | |
8715 | const struct mips_immed *imm = mips_immed; | |
8716 | ||
8717 | while (imm->type && imm->type != *args) | |
8718 | ++imm; | |
8719 | if (! imm->type) | |
8720 | internalError (); | |
8721 | my_getExpression (&imm_expr, s); | |
8722 | check_absolute_expr (ip, &imm_expr); | |
8723 | if ((unsigned long) imm_expr.X_add_number & ~imm->mask) | |
8724 | { | |
8725 | as_warn (_("Illegal %s number (%lu, 0x%lx)"), | |
8726 | imm->desc ? imm->desc : ip->insn_mo->name, | |
8727 | (unsigned long) imm_expr.X_add_number, | |
8728 | (unsigned long) imm_expr.X_add_number); | |
8729 | imm_expr.X_add_number &= imm->mask; | |
8730 | } | |
8731 | ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number | |
8732 | << imm->shift); | |
8733 | imm_expr.X_op = O_absent; | |
8734 | s = expr_end; | |
8735 | } | |
8736 | continue; | |
8737 | ||
071742cf CD |
8738 | case 'A': /* ins/ext position, becomes LSB. */ |
8739 | limlo = 0; | |
8740 | limhi = 31; | |
5f74bc13 CD |
8741 | goto do_lsb; |
8742 | case 'E': | |
8743 | limlo = 32; | |
8744 | limhi = 63; | |
8745 | goto do_lsb; | |
8746 | do_lsb: | |
071742cf CD |
8747 | my_getExpression (&imm_expr, s); |
8748 | check_absolute_expr (ip, &imm_expr); | |
8749 | if ((unsigned long) imm_expr.X_add_number < limlo | |
8750 | || (unsigned long) imm_expr.X_add_number > limhi) | |
8751 | { | |
8752 | as_bad (_("Improper position (%lu)"), | |
8753 | (unsigned long) imm_expr.X_add_number); | |
8754 | imm_expr.X_add_number = limlo; | |
8755 | } | |
8756 | lastpos = imm_expr.X_add_number; | |
bf12938e | 8757 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); |
071742cf CD |
8758 | imm_expr.X_op = O_absent; |
8759 | s = expr_end; | |
8760 | continue; | |
8761 | ||
8762 | case 'B': /* ins size, becomes MSB. */ | |
8763 | limlo = 1; | |
8764 | limhi = 32; | |
5f74bc13 CD |
8765 | goto do_msb; |
8766 | case 'F': | |
8767 | limlo = 33; | |
8768 | limhi = 64; | |
8769 | goto do_msb; | |
8770 | do_msb: | |
071742cf CD |
8771 | my_getExpression (&imm_expr, s); |
8772 | check_absolute_expr (ip, &imm_expr); | |
8773 | /* Check for negative input so that small negative numbers | |
8774 | will not succeed incorrectly. The checks against | |
8775 | (pos+size) transitively check "size" itself, | |
8776 | assuming that "pos" is reasonable. */ | |
8777 | if ((long) imm_expr.X_add_number < 0 | |
8778 | || ((unsigned long) imm_expr.X_add_number | |
8779 | + lastpos) < limlo | |
8780 | || ((unsigned long) imm_expr.X_add_number | |
8781 | + lastpos) > limhi) | |
8782 | { | |
8783 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
8784 | (unsigned long) imm_expr.X_add_number, | |
8785 | (unsigned long) lastpos); | |
8786 | imm_expr.X_add_number = limlo - lastpos; | |
8787 | } | |
bf12938e RS |
8788 | INSERT_OPERAND (INSMSB, *ip, |
8789 | lastpos + imm_expr.X_add_number - 1); | |
071742cf CD |
8790 | imm_expr.X_op = O_absent; |
8791 | s = expr_end; | |
8792 | continue; | |
8793 | ||
8794 | case 'C': /* ext size, becomes MSBD. */ | |
8795 | limlo = 1; | |
8796 | limhi = 32; | |
5f74bc13 CD |
8797 | goto do_msbd; |
8798 | case 'G': | |
8799 | limlo = 33; | |
8800 | limhi = 64; | |
8801 | goto do_msbd; | |
8802 | case 'H': | |
8803 | limlo = 33; | |
8804 | limhi = 64; | |
8805 | goto do_msbd; | |
8806 | do_msbd: | |
071742cf CD |
8807 | my_getExpression (&imm_expr, s); |
8808 | check_absolute_expr (ip, &imm_expr); | |
8809 | /* Check for negative input so that small negative numbers | |
8810 | will not succeed incorrectly. The checks against | |
8811 | (pos+size) transitively check "size" itself, | |
8812 | assuming that "pos" is reasonable. */ | |
8813 | if ((long) imm_expr.X_add_number < 0 | |
8814 | || ((unsigned long) imm_expr.X_add_number | |
8815 | + lastpos) < limlo | |
8816 | || ((unsigned long) imm_expr.X_add_number | |
8817 | + lastpos) > limhi) | |
8818 | { | |
8819 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
8820 | (unsigned long) imm_expr.X_add_number, | |
8821 | (unsigned long) lastpos); | |
8822 | imm_expr.X_add_number = limlo - lastpos; | |
8823 | } | |
bf12938e | 8824 | INSERT_OPERAND (EXTMSBD, *ip, imm_expr.X_add_number - 1); |
071742cf CD |
8825 | imm_expr.X_op = O_absent; |
8826 | s = expr_end; | |
8827 | continue; | |
af7ee8bf | 8828 | |
bbcc0807 CD |
8829 | case 'D': |
8830 | /* +D is for disassembly only; never match. */ | |
8831 | break; | |
8832 | ||
5f74bc13 CD |
8833 | case 'I': |
8834 | /* "+I" is like "I", except that imm2_expr is used. */ | |
8835 | my_getExpression (&imm2_expr, s); | |
8836 | if (imm2_expr.X_op != O_big | |
8837 | && imm2_expr.X_op != O_constant) | |
8838 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
8839 | if (HAVE_32BIT_GPRS) |
8840 | normalize_constant_expr (&imm2_expr); | |
5f74bc13 CD |
8841 | s = expr_end; |
8842 | continue; | |
8843 | ||
707bfff6 | 8844 | case 'T': /* Coprocessor register. */ |
ef2e4d86 CF |
8845 | /* +T is for disassembly only; never match. */ |
8846 | break; | |
8847 | ||
707bfff6 | 8848 | case 't': /* Coprocessor register number. */ |
ef2e4d86 CF |
8849 | if (s[0] == '$' && ISDIGIT (s[1])) |
8850 | { | |
8851 | ++s; | |
8852 | regno = 0; | |
8853 | do | |
8854 | { | |
8855 | regno *= 10; | |
8856 | regno += *s - '0'; | |
8857 | ++s; | |
8858 | } | |
8859 | while (ISDIGIT (*s)); | |
8860 | if (regno > 31) | |
8861 | as_bad (_("Invalid register number (%d)"), regno); | |
8862 | else | |
8863 | { | |
a9e24354 | 8864 | INSERT_OPERAND (RT, *ip, regno); |
ef2e4d86 CF |
8865 | continue; |
8866 | } | |
8867 | } | |
8868 | else | |
8869 | as_bad (_("Invalid coprocessor 0 register number")); | |
8870 | break; | |
8871 | ||
af7ee8bf CD |
8872 | default: |
8873 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
8874 | *args, insn->name, insn->args); | |
8875 | /* Further processing is fruitless. */ | |
8876 | return; | |
8877 | } | |
8878 | break; | |
8879 | ||
252b5132 RH |
8880 | case '<': /* must be at least one digit */ |
8881 | /* | |
8882 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
8883 | * than 31 or less than 0, then the shift amount should be |
8884 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
8885 | * We issue a warning and mask out all but the low 5 bits. |
8886 | */ | |
8887 | my_getExpression (&imm_expr, s); | |
8888 | check_absolute_expr (ip, &imm_expr); | |
8889 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
8890 | as_warn (_("Improper shift amount (%lu)"), |
8891 | (unsigned long) imm_expr.X_add_number); | |
8892 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); | |
252b5132 RH |
8893 | imm_expr.X_op = O_absent; |
8894 | s = expr_end; | |
8895 | continue; | |
8896 | ||
8897 | case '>': /* shift amount minus 32 */ | |
8898 | my_getExpression (&imm_expr, s); | |
8899 | check_absolute_expr (ip, &imm_expr); | |
8900 | if ((unsigned long) imm_expr.X_add_number < 32 | |
8901 | || (unsigned long) imm_expr.X_add_number > 63) | |
8902 | break; | |
bf12938e | 8903 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number - 32); |
252b5132 RH |
8904 | imm_expr.X_op = O_absent; |
8905 | s = expr_end; | |
8906 | continue; | |
8907 | ||
252b5132 RH |
8908 | case 'k': /* cache code */ |
8909 | case 'h': /* prefx code */ | |
8910 | my_getExpression (&imm_expr, s); | |
8911 | check_absolute_expr (ip, &imm_expr); | |
8912 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
8913 | as_warn (_("Invalid value for `%s' (%lu)"), |
8914 | ip->insn_mo->name, | |
8915 | (unsigned long) imm_expr.X_add_number); | |
252b5132 | 8916 | if (*args == 'k') |
bf12938e | 8917 | INSERT_OPERAND (CACHE, *ip, imm_expr.X_add_number); |
252b5132 | 8918 | else |
bf12938e | 8919 | INSERT_OPERAND (PREFX, *ip, imm_expr.X_add_number); |
252b5132 RH |
8920 | imm_expr.X_op = O_absent; |
8921 | s = expr_end; | |
8922 | continue; | |
8923 | ||
8924 | case 'c': /* break code */ | |
8925 | my_getExpression (&imm_expr, s); | |
8926 | check_absolute_expr (ip, &imm_expr); | |
a9e24354 TS |
8927 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE) |
8928 | as_warn (_("Code for %s not in range 0..1023 (%lu)"), | |
8929 | ip->insn_mo->name, | |
bf12938e RS |
8930 | (unsigned long) imm_expr.X_add_number); |
8931 | INSERT_OPERAND (CODE, *ip, imm_expr.X_add_number); | |
252b5132 RH |
8932 | imm_expr.X_op = O_absent; |
8933 | s = expr_end; | |
8934 | continue; | |
8935 | ||
8936 | case 'q': /* lower break code */ | |
8937 | my_getExpression (&imm_expr, s); | |
8938 | check_absolute_expr (ip, &imm_expr); | |
a9e24354 TS |
8939 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE2) |
8940 | as_warn (_("Lower code for %s not in range 0..1023 (%lu)"), | |
8941 | ip->insn_mo->name, | |
bf12938e RS |
8942 | (unsigned long) imm_expr.X_add_number); |
8943 | INSERT_OPERAND (CODE2, *ip, imm_expr.X_add_number); | |
252b5132 RH |
8944 | imm_expr.X_op = O_absent; |
8945 | s = expr_end; | |
8946 | continue; | |
8947 | ||
4372b673 | 8948 | case 'B': /* 20-bit syscall/break code. */ |
156c2f8b | 8949 | my_getExpression (&imm_expr, s); |
156c2f8b | 8950 | check_absolute_expr (ip, &imm_expr); |
793b27f4 | 8951 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20) |
a9e24354 TS |
8952 | as_warn (_("Code for %s not in range 0..1048575 (%lu)"), |
8953 | ip->insn_mo->name, | |
793b27f4 | 8954 | (unsigned long) imm_expr.X_add_number); |
bf12938e | 8955 | INSERT_OPERAND (CODE20, *ip, imm_expr.X_add_number); |
252b5132 RH |
8956 | imm_expr.X_op = O_absent; |
8957 | s = expr_end; | |
8958 | continue; | |
8959 | ||
98d3f06f | 8960 | case 'C': /* Coprocessor code */ |
beae10d5 | 8961 | my_getExpression (&imm_expr, s); |
252b5132 | 8962 | check_absolute_expr (ip, &imm_expr); |
a9e24354 | 8963 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_COPZ) |
252b5132 | 8964 | { |
793b27f4 TS |
8965 | as_warn (_("Coproccesor code > 25 bits (%lu)"), |
8966 | (unsigned long) imm_expr.X_add_number); | |
a9e24354 | 8967 | imm_expr.X_add_number &= OP_MASK_COPZ; |
252b5132 | 8968 | } |
a9e24354 | 8969 | INSERT_OPERAND (COPZ, *ip, imm_expr.X_add_number); |
beae10d5 KH |
8970 | imm_expr.X_op = O_absent; |
8971 | s = expr_end; | |
8972 | continue; | |
252b5132 | 8973 | |
4372b673 NC |
8974 | case 'J': /* 19-bit wait code. */ |
8975 | my_getExpression (&imm_expr, s); | |
8976 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 8977 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
a9e24354 TS |
8978 | { |
8979 | as_warn (_("Illegal 19-bit code (%lu)"), | |
8980 | (unsigned long) imm_expr.X_add_number); | |
8981 | imm_expr.X_add_number &= OP_MASK_CODE19; | |
8982 | } | |
bf12938e | 8983 | INSERT_OPERAND (CODE19, *ip, imm_expr.X_add_number); |
4372b673 NC |
8984 | imm_expr.X_op = O_absent; |
8985 | s = expr_end; | |
8986 | continue; | |
8987 | ||
707bfff6 | 8988 | case 'P': /* Performance register. */ |
beae10d5 | 8989 | my_getExpression (&imm_expr, s); |
252b5132 | 8990 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 8991 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
bf12938e RS |
8992 | as_warn (_("Invalid performance register (%lu)"), |
8993 | (unsigned long) imm_expr.X_add_number); | |
8994 | INSERT_OPERAND (PERFREG, *ip, imm_expr.X_add_number); | |
beae10d5 KH |
8995 | imm_expr.X_op = O_absent; |
8996 | s = expr_end; | |
8997 | continue; | |
252b5132 | 8998 | |
707bfff6 TS |
8999 | case 'G': /* Coprocessor destination register. */ |
9000 | if (((ip->insn_opcode >> OP_SH_OP) & OP_MASK_OP) == OP_OP_COP0) | |
9001 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_CP0, ®no); | |
9002 | else | |
9003 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
a9e24354 | 9004 | INSERT_OPERAND (RD, *ip, regno); |
707bfff6 TS |
9005 | if (ok) |
9006 | { | |
9007 | lastregno = regno; | |
9008 | continue; | |
9009 | } | |
9010 | else | |
9011 | break; | |
9012 | ||
252b5132 RH |
9013 | case 'b': /* base register */ |
9014 | case 'd': /* destination register */ | |
9015 | case 's': /* source register */ | |
9016 | case 't': /* target register */ | |
9017 | case 'r': /* both target and source */ | |
9018 | case 'v': /* both dest and source */ | |
9019 | case 'w': /* both dest and target */ | |
9020 | case 'E': /* coprocessor target register */ | |
af7ee8bf | 9021 | case 'K': /* 'rdhwr' destination register */ |
252b5132 RH |
9022 | case 'x': /* ignore register name */ |
9023 | case 'z': /* must be zero register */ | |
4372b673 | 9024 | case 'U': /* destination register (clo/clz). */ |
ef2e4d86 | 9025 | case 'g': /* coprocessor destination register */ |
707bfff6 TS |
9026 | s_reset = s; |
9027 | if (*args == 'E' || *args == 'K') | |
9028 | ok = reg_lookup (&s, RTYPE_NUM, ®no); | |
9029 | else | |
9030 | { | |
9031 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
9032 | if (regno == AT && ! mips_opts.noat) | |
9033 | as_warn ("Used $at without \".set noat\""); | |
9034 | } | |
9035 | if (ok) | |
252b5132 | 9036 | { |
252b5132 RH |
9037 | c = *args; |
9038 | if (*s == ' ') | |
f9419b05 | 9039 | ++s; |
252b5132 RH |
9040 | if (args[1] != *s) |
9041 | { | |
9042 | if (c == 'r' || c == 'v' || c == 'w') | |
9043 | { | |
9044 | regno = lastregno; | |
9045 | s = s_reset; | |
f9419b05 | 9046 | ++args; |
252b5132 RH |
9047 | } |
9048 | } | |
9049 | /* 'z' only matches $0. */ | |
9050 | if (c == 'z' && regno != 0) | |
9051 | break; | |
9052 | ||
bdaaa2e1 KH |
9053 | /* Now that we have assembled one operand, we use the args string |
9054 | * to figure out where it goes in the instruction. */ | |
252b5132 RH |
9055 | switch (c) |
9056 | { | |
9057 | case 'r': | |
9058 | case 's': | |
9059 | case 'v': | |
9060 | case 'b': | |
bf12938e | 9061 | INSERT_OPERAND (RS, *ip, regno); |
252b5132 RH |
9062 | break; |
9063 | case 'd': | |
9064 | case 'G': | |
af7ee8bf | 9065 | case 'K': |
ef2e4d86 | 9066 | case 'g': |
bf12938e | 9067 | INSERT_OPERAND (RD, *ip, regno); |
252b5132 | 9068 | break; |
4372b673 | 9069 | case 'U': |
bf12938e RS |
9070 | INSERT_OPERAND (RD, *ip, regno); |
9071 | INSERT_OPERAND (RT, *ip, regno); | |
4372b673 | 9072 | break; |
252b5132 RH |
9073 | case 'w': |
9074 | case 't': | |
9075 | case 'E': | |
bf12938e | 9076 | INSERT_OPERAND (RT, *ip, regno); |
252b5132 RH |
9077 | break; |
9078 | case 'x': | |
9079 | /* This case exists because on the r3000 trunc | |
9080 | expands into a macro which requires a gp | |
9081 | register. On the r6000 or r4000 it is | |
9082 | assembled into a single instruction which | |
9083 | ignores the register. Thus the insn version | |
9084 | is MIPS_ISA2 and uses 'x', and the macro | |
9085 | version is MIPS_ISA1 and uses 't'. */ | |
9086 | break; | |
9087 | case 'z': | |
9088 | /* This case is for the div instruction, which | |
9089 | acts differently if the destination argument | |
9090 | is $0. This only matches $0, and is checked | |
9091 | outside the switch. */ | |
9092 | break; | |
9093 | case 'D': | |
9094 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
9095 | break; | |
9096 | /* What about all other operands like 'i', which | |
9097 | can be specified in the opcode table? */ | |
9098 | } | |
9099 | lastregno = regno; | |
9100 | continue; | |
9101 | } | |
252b5132 RH |
9102 | switch (*args++) |
9103 | { | |
9104 | case 'r': | |
9105 | case 'v': | |
bf12938e | 9106 | INSERT_OPERAND (RS, *ip, lastregno); |
252b5132 RH |
9107 | continue; |
9108 | case 'w': | |
bf12938e | 9109 | INSERT_OPERAND (RT, *ip, lastregno); |
252b5132 RH |
9110 | continue; |
9111 | } | |
9112 | break; | |
9113 | ||
deec1734 CD |
9114 | case 'O': /* MDMX alignment immediate constant. */ |
9115 | my_getExpression (&imm_expr, s); | |
9116 | check_absolute_expr (ip, &imm_expr); | |
9117 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
bf12938e RS |
9118 | as_warn ("Improper align amount (%ld), using low bits", |
9119 | (long) imm_expr.X_add_number); | |
9120 | INSERT_OPERAND (ALN, *ip, imm_expr.X_add_number); | |
deec1734 CD |
9121 | imm_expr.X_op = O_absent; |
9122 | s = expr_end; | |
9123 | continue; | |
9124 | ||
9125 | case 'Q': /* MDMX vector, element sel, or const. */ | |
9126 | if (s[0] != '$') | |
9127 | { | |
9128 | /* MDMX Immediate. */ | |
9129 | my_getExpression (&imm_expr, s); | |
9130 | check_absolute_expr (ip, &imm_expr); | |
9131 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
bf12938e RS |
9132 | as_warn (_("Invalid MDMX Immediate (%ld)"), |
9133 | (long) imm_expr.X_add_number); | |
9134 | INSERT_OPERAND (FT, *ip, imm_expr.X_add_number); | |
deec1734 CD |
9135 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) |
9136 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
9137 | else | |
9138 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
deec1734 CD |
9139 | imm_expr.X_op = O_absent; |
9140 | s = expr_end; | |
9141 | continue; | |
9142 | } | |
9143 | /* Not MDMX Immediate. Fall through. */ | |
9144 | case 'X': /* MDMX destination register. */ | |
9145 | case 'Y': /* MDMX source register. */ | |
9146 | case 'Z': /* MDMX target register. */ | |
9147 | is_mdmx = 1; | |
252b5132 RH |
9148 | case 'D': /* floating point destination register */ |
9149 | case 'S': /* floating point source register */ | |
9150 | case 'T': /* floating point target register */ | |
9151 | case 'R': /* floating point source register */ | |
9152 | case 'V': | |
9153 | case 'W': | |
707bfff6 TS |
9154 | rtype = RTYPE_FPU; |
9155 | if (is_mdmx | |
9156 | || (mips_opts.ase_mdmx | |
9157 | && (ip->insn_mo->pinfo & FP_D) | |
9158 | && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY | |
9159 | | INSN_COPROC_MEMORY_DELAY | |
9160 | | INSN_LOAD_COPROC_DELAY | |
9161 | | INSN_LOAD_MEMORY_DELAY | |
9162 | | INSN_STORE_MEMORY)))) | |
9163 | rtype |= RTYPE_VEC; | |
252b5132 | 9164 | s_reset = s; |
707bfff6 | 9165 | if (reg_lookup (&s, rtype, ®no)) |
252b5132 | 9166 | { |
252b5132 | 9167 | if ((regno & 1) != 0 |
ca4e0257 | 9168 | && HAVE_32BIT_FPRS |
7455baf8 | 9169 | && ! mips_oddfpreg_ok (ip->insn_mo, argnum)) |
252b5132 RH |
9170 | as_warn (_("Float register should be even, was %d"), |
9171 | regno); | |
9172 | ||
9173 | c = *args; | |
9174 | if (*s == ' ') | |
f9419b05 | 9175 | ++s; |
252b5132 RH |
9176 | if (args[1] != *s) |
9177 | { | |
9178 | if (c == 'V' || c == 'W') | |
9179 | { | |
9180 | regno = lastregno; | |
9181 | s = s_reset; | |
f9419b05 | 9182 | ++args; |
252b5132 RH |
9183 | } |
9184 | } | |
9185 | switch (c) | |
9186 | { | |
9187 | case 'D': | |
deec1734 | 9188 | case 'X': |
bf12938e | 9189 | INSERT_OPERAND (FD, *ip, regno); |
252b5132 RH |
9190 | break; |
9191 | case 'V': | |
9192 | case 'S': | |
deec1734 | 9193 | case 'Y': |
bf12938e | 9194 | INSERT_OPERAND (FS, *ip, regno); |
252b5132 | 9195 | break; |
deec1734 CD |
9196 | case 'Q': |
9197 | /* This is like 'Z', but also needs to fix the MDMX | |
9198 | vector/scalar select bits. Note that the | |
9199 | scalar immediate case is handled above. */ | |
9200 | if (*s == '[') | |
9201 | { | |
9202 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
9203 | int max_el = (is_qh ? 3 : 7); | |
9204 | s++; | |
9205 | my_getExpression(&imm_expr, s); | |
9206 | check_absolute_expr (ip, &imm_expr); | |
9207 | s = expr_end; | |
9208 | if (imm_expr.X_add_number > max_el) | |
9209 | as_bad(_("Bad element selector %ld"), | |
9210 | (long) imm_expr.X_add_number); | |
9211 | imm_expr.X_add_number &= max_el; | |
9212 | ip->insn_opcode |= (imm_expr.X_add_number | |
9213 | << (OP_SH_VSEL + | |
9214 | (is_qh ? 2 : 1))); | |
01a3f561 | 9215 | imm_expr.X_op = O_absent; |
deec1734 CD |
9216 | if (*s != ']') |
9217 | as_warn(_("Expecting ']' found '%s'"), s); | |
9218 | else | |
9219 | s++; | |
9220 | } | |
9221 | else | |
9222 | { | |
9223 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
9224 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
9225 | << OP_SH_VSEL); | |
9226 | else | |
9227 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
9228 | OP_SH_VSEL); | |
9229 | } | |
9230 | /* Fall through */ | |
252b5132 RH |
9231 | case 'W': |
9232 | case 'T': | |
deec1734 | 9233 | case 'Z': |
bf12938e | 9234 | INSERT_OPERAND (FT, *ip, regno); |
252b5132 RH |
9235 | break; |
9236 | case 'R': | |
bf12938e | 9237 | INSERT_OPERAND (FR, *ip, regno); |
252b5132 RH |
9238 | break; |
9239 | } | |
9240 | lastregno = regno; | |
9241 | continue; | |
9242 | } | |
9243 | ||
252b5132 RH |
9244 | switch (*args++) |
9245 | { | |
9246 | case 'V': | |
bf12938e | 9247 | INSERT_OPERAND (FS, *ip, lastregno); |
252b5132 RH |
9248 | continue; |
9249 | case 'W': | |
bf12938e | 9250 | INSERT_OPERAND (FT, *ip, lastregno); |
252b5132 RH |
9251 | continue; |
9252 | } | |
9253 | break; | |
9254 | ||
9255 | case 'I': | |
9256 | my_getExpression (&imm_expr, s); | |
9257 | if (imm_expr.X_op != O_big | |
9258 | && imm_expr.X_op != O_constant) | |
9259 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
9260 | if (HAVE_32BIT_GPRS) |
9261 | normalize_constant_expr (&imm_expr); | |
252b5132 RH |
9262 | s = expr_end; |
9263 | continue; | |
9264 | ||
9265 | case 'A': | |
9266 | my_getExpression (&offset_expr, s); | |
2051e8c4 | 9267 | normalize_address_expr (&offset_expr); |
f6688943 | 9268 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
9269 | s = expr_end; |
9270 | continue; | |
9271 | ||
9272 | case 'F': | |
9273 | case 'L': | |
9274 | case 'f': | |
9275 | case 'l': | |
9276 | { | |
9277 | int f64; | |
ca4e0257 | 9278 | int using_gprs; |
252b5132 RH |
9279 | char *save_in; |
9280 | char *err; | |
9281 | unsigned char temp[8]; | |
9282 | int len; | |
9283 | unsigned int length; | |
9284 | segT seg; | |
9285 | subsegT subseg; | |
9286 | char *p; | |
9287 | ||
9288 | /* These only appear as the last operand in an | |
9289 | instruction, and every instruction that accepts | |
9290 | them in any variant accepts them in all variants. | |
9291 | This means we don't have to worry about backing out | |
9292 | any changes if the instruction does not match. | |
9293 | ||
9294 | The difference between them is the size of the | |
9295 | floating point constant and where it goes. For 'F' | |
9296 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
9297 | is 32 bits. Where the constant is placed is based | |
9298 | on how the MIPS assembler does things: | |
9299 | F -- .rdata | |
9300 | L -- .lit8 | |
9301 | f -- immediate value | |
9302 | l -- .lit4 | |
9303 | ||
9304 | The .lit4 and .lit8 sections are only used if | |
9305 | permitted by the -G argument. | |
9306 | ||
ca4e0257 RS |
9307 | The code below needs to know whether the target register |
9308 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
9309 | 'F' are used with GPR-based instructions and 'l' and | |
9310 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
9311 | |
9312 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 9313 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
9314 | |
9315 | save_in = input_line_pointer; | |
9316 | input_line_pointer = s; | |
9317 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
9318 | length = len; | |
9319 | s = input_line_pointer; | |
9320 | input_line_pointer = save_in; | |
9321 | if (err != NULL && *err != '\0') | |
9322 | { | |
9323 | as_bad (_("Bad floating point constant: %s"), err); | |
9324 | memset (temp, '\0', sizeof temp); | |
9325 | length = f64 ? 8 : 4; | |
9326 | } | |
9327 | ||
156c2f8b | 9328 | assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
9329 | |
9330 | if (*args == 'f' | |
9331 | || (*args == 'l' | |
3e722fb5 | 9332 | && (g_switch_value < 4 |
252b5132 RH |
9333 | || (temp[0] == 0 && temp[1] == 0) |
9334 | || (temp[2] == 0 && temp[3] == 0)))) | |
9335 | { | |
9336 | imm_expr.X_op = O_constant; | |
9337 | if (! target_big_endian) | |
9338 | imm_expr.X_add_number = bfd_getl32 (temp); | |
9339 | else | |
9340 | imm_expr.X_add_number = bfd_getb32 (temp); | |
9341 | } | |
9342 | else if (length > 4 | |
119d663a | 9343 | && ! mips_disable_float_construction |
ca4e0257 RS |
9344 | /* Constants can only be constructed in GPRs and |
9345 | copied to FPRs if the GPRs are at least as wide | |
9346 | as the FPRs. Force the constant into memory if | |
9347 | we are using 64-bit FPRs but the GPRs are only | |
9348 | 32 bits wide. */ | |
9349 | && (using_gprs | |
9350 | || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) | |
252b5132 RH |
9351 | && ((temp[0] == 0 && temp[1] == 0) |
9352 | || (temp[2] == 0 && temp[3] == 0)) | |
9353 | && ((temp[4] == 0 && temp[5] == 0) | |
9354 | || (temp[6] == 0 && temp[7] == 0))) | |
9355 | { | |
ca4e0257 RS |
9356 | /* The value is simple enough to load with a couple of |
9357 | instructions. If using 32-bit registers, set | |
9358 | imm_expr to the high order 32 bits and offset_expr to | |
9359 | the low order 32 bits. Otherwise, set imm_expr to | |
9360 | the entire 64 bit constant. */ | |
9361 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) | |
252b5132 RH |
9362 | { |
9363 | imm_expr.X_op = O_constant; | |
9364 | offset_expr.X_op = O_constant; | |
9365 | if (! target_big_endian) | |
9366 | { | |
9367 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
9368 | offset_expr.X_add_number = bfd_getl32 (temp); | |
9369 | } | |
9370 | else | |
9371 | { | |
9372 | imm_expr.X_add_number = bfd_getb32 (temp); | |
9373 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
9374 | } | |
9375 | if (offset_expr.X_add_number == 0) | |
9376 | offset_expr.X_op = O_absent; | |
9377 | } | |
9378 | else if (sizeof (imm_expr.X_add_number) > 4) | |
9379 | { | |
9380 | imm_expr.X_op = O_constant; | |
9381 | if (! target_big_endian) | |
9382 | imm_expr.X_add_number = bfd_getl64 (temp); | |
9383 | else | |
9384 | imm_expr.X_add_number = bfd_getb64 (temp); | |
9385 | } | |
9386 | else | |
9387 | { | |
9388 | imm_expr.X_op = O_big; | |
9389 | imm_expr.X_add_number = 4; | |
9390 | if (! target_big_endian) | |
9391 | { | |
9392 | generic_bignum[0] = bfd_getl16 (temp); | |
9393 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
9394 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
9395 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
9396 | } | |
9397 | else | |
9398 | { | |
9399 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
9400 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
9401 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
9402 | generic_bignum[3] = bfd_getb16 (temp); | |
9403 | } | |
9404 | } | |
9405 | } | |
9406 | else | |
9407 | { | |
9408 | const char *newname; | |
9409 | segT new_seg; | |
9410 | ||
9411 | /* Switch to the right section. */ | |
9412 | seg = now_seg; | |
9413 | subseg = now_subseg; | |
9414 | switch (*args) | |
9415 | { | |
9416 | default: /* unused default case avoids warnings. */ | |
9417 | case 'L': | |
9418 | newname = RDATA_SECTION_NAME; | |
3e722fb5 | 9419 | if (g_switch_value >= 8) |
252b5132 RH |
9420 | newname = ".lit8"; |
9421 | break; | |
9422 | case 'F': | |
3e722fb5 | 9423 | newname = RDATA_SECTION_NAME; |
252b5132 RH |
9424 | break; |
9425 | case 'l': | |
4d0d148d | 9426 | assert (g_switch_value >= 4); |
252b5132 RH |
9427 | newname = ".lit4"; |
9428 | break; | |
9429 | } | |
9430 | new_seg = subseg_new (newname, (subsegT) 0); | |
f43abd2b | 9431 | if (IS_ELF) |
252b5132 RH |
9432 | bfd_set_section_flags (stdoutput, new_seg, |
9433 | (SEC_ALLOC | |
9434 | | SEC_LOAD | |
9435 | | SEC_READONLY | |
9436 | | SEC_DATA)); | |
9437 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
f43abd2b | 9438 | if (IS_ELF && strcmp (TARGET_OS, "elf") != 0) |
252b5132 RH |
9439 | record_alignment (new_seg, 4); |
9440 | else | |
9441 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
9442 | if (seg == now_seg) | |
9443 | as_bad (_("Can't use floating point insn in this section")); | |
9444 | ||
9445 | /* Set the argument to the current address in the | |
9446 | section. */ | |
9447 | offset_expr.X_op = O_symbol; | |
9448 | offset_expr.X_add_symbol = | |
9449 | symbol_new ("L0\001", now_seg, | |
9450 | (valueT) frag_now_fix (), frag_now); | |
9451 | offset_expr.X_add_number = 0; | |
9452 | ||
9453 | /* Put the floating point number into the section. */ | |
9454 | p = frag_more ((int) length); | |
9455 | memcpy (p, temp, length); | |
9456 | ||
9457 | /* Switch back to the original section. */ | |
9458 | subseg_set (seg, subseg); | |
9459 | } | |
9460 | } | |
9461 | continue; | |
9462 | ||
9463 | case 'i': /* 16 bit unsigned immediate */ | |
9464 | case 'j': /* 16 bit signed immediate */ | |
f6688943 | 9465 | *imm_reloc = BFD_RELOC_LO16; |
5e0116d5 | 9466 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) |
252b5132 RH |
9467 | { |
9468 | int more; | |
5e0116d5 RS |
9469 | offsetT minval, maxval; |
9470 | ||
9471 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] | |
9472 | && strcmp (insn->name, insn[1].name) == 0); | |
9473 | ||
9474 | /* If the expression was written as an unsigned number, | |
9475 | only treat it as signed if there are no more | |
9476 | alternatives. */ | |
9477 | if (more | |
9478 | && *args == 'j' | |
9479 | && sizeof (imm_expr.X_add_number) <= 4 | |
9480 | && imm_expr.X_op == O_constant | |
9481 | && imm_expr.X_add_number < 0 | |
9482 | && imm_expr.X_unsigned | |
9483 | && HAVE_64BIT_GPRS) | |
9484 | break; | |
9485 | ||
9486 | /* For compatibility with older assemblers, we accept | |
9487 | 0x8000-0xffff as signed 16-bit numbers when only | |
9488 | signed numbers are allowed. */ | |
9489 | if (*args == 'i') | |
9490 | minval = 0, maxval = 0xffff; | |
9491 | else if (more) | |
9492 | minval = -0x8000, maxval = 0x7fff; | |
252b5132 | 9493 | else |
5e0116d5 RS |
9494 | minval = -0x8000, maxval = 0xffff; |
9495 | ||
9496 | if (imm_expr.X_op != O_constant | |
9497 | || imm_expr.X_add_number < minval | |
9498 | || imm_expr.X_add_number > maxval) | |
252b5132 RH |
9499 | { |
9500 | if (more) | |
9501 | break; | |
2ae7e77b AH |
9502 | if (imm_expr.X_op == O_constant |
9503 | || imm_expr.X_op == O_big) | |
5e0116d5 | 9504 | as_bad (_("expression out of range")); |
252b5132 RH |
9505 | } |
9506 | } | |
9507 | s = expr_end; | |
9508 | continue; | |
9509 | ||
9510 | case 'o': /* 16 bit offset */ | |
5e0116d5 RS |
9511 | /* Check whether there is only a single bracketed expression |
9512 | left. If so, it must be the base register and the | |
9513 | constant must be zero. */ | |
9514 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
9515 | { | |
9516 | offset_expr.X_op = O_constant; | |
9517 | offset_expr.X_add_number = 0; | |
9518 | continue; | |
9519 | } | |
252b5132 RH |
9520 | |
9521 | /* If this value won't fit into a 16 bit offset, then go | |
9522 | find a macro that will generate the 32 bit offset | |
afdbd6d0 | 9523 | code pattern. */ |
5e0116d5 | 9524 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 |
252b5132 RH |
9525 | && (offset_expr.X_op != O_constant |
9526 | || offset_expr.X_add_number >= 0x8000 | |
afdbd6d0 | 9527 | || offset_expr.X_add_number < -0x8000)) |
252b5132 RH |
9528 | break; |
9529 | ||
252b5132 RH |
9530 | s = expr_end; |
9531 | continue; | |
9532 | ||
9533 | case 'p': /* pc relative offset */ | |
0b25d3e6 | 9534 | *offset_reloc = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
9535 | my_getExpression (&offset_expr, s); |
9536 | s = expr_end; | |
9537 | continue; | |
9538 | ||
9539 | case 'u': /* upper 16 bits */ | |
5e0116d5 RS |
9540 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 |
9541 | && imm_expr.X_op == O_constant | |
9542 | && (imm_expr.X_add_number < 0 | |
9543 | || imm_expr.X_add_number >= 0x10000)) | |
252b5132 RH |
9544 | as_bad (_("lui expression not in range 0..65535")); |
9545 | s = expr_end; | |
9546 | continue; | |
9547 | ||
9548 | case 'a': /* 26 bit address */ | |
9549 | my_getExpression (&offset_expr, s); | |
9550 | s = expr_end; | |
f6688943 | 9551 | *offset_reloc = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
9552 | continue; |
9553 | ||
9554 | case 'N': /* 3 bit branch condition code */ | |
9555 | case 'M': /* 3 bit compare condition code */ | |
707bfff6 TS |
9556 | rtype = RTYPE_CCC; |
9557 | if (ip->insn_mo->pinfo & (FP_D| FP_S)) | |
9558 | rtype |= RTYPE_FCC; | |
9559 | if (!reg_lookup (&s, rtype, ®no)) | |
252b5132 | 9560 | break; |
30c378fd CD |
9561 | if ((strcmp(str + strlen(str) - 3, ".ps") == 0 |
9562 | || strcmp(str + strlen(str) - 5, "any2f") == 0 | |
9563 | || strcmp(str + strlen(str) - 5, "any2t") == 0) | |
9564 | && (regno & 1) != 0) | |
9565 | as_warn(_("Condition code register should be even for %s, was %d"), | |
9566 | str, regno); | |
9567 | if ((strcmp(str + strlen(str) - 5, "any4f") == 0 | |
9568 | || strcmp(str + strlen(str) - 5, "any4t") == 0) | |
9569 | && (regno & 3) != 0) | |
9570 | as_warn(_("Condition code register should be 0 or 4 for %s, was %d"), | |
9571 | str, regno); | |
252b5132 | 9572 | if (*args == 'N') |
bf12938e | 9573 | INSERT_OPERAND (BCC, *ip, regno); |
252b5132 | 9574 | else |
bf12938e | 9575 | INSERT_OPERAND (CCC, *ip, regno); |
beae10d5 | 9576 | continue; |
252b5132 | 9577 | |
156c2f8b NC |
9578 | case 'H': |
9579 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
9580 | s += 2; | |
3882b010 | 9581 | if (ISDIGIT (*s)) |
156c2f8b NC |
9582 | { |
9583 | c = 0; | |
9584 | do | |
9585 | { | |
9586 | c *= 10; | |
9587 | c += *s - '0'; | |
9588 | ++s; | |
9589 | } | |
3882b010 | 9590 | while (ISDIGIT (*s)); |
156c2f8b NC |
9591 | } |
9592 | else | |
9593 | c = 8; /* Invalid sel value. */ | |
9594 | ||
9595 | if (c > 7) | |
9596 | as_bad (_("invalid coprocessor sub-selection value (0-7)")); | |
9597 | ip->insn_opcode |= c; | |
9598 | continue; | |
9599 | ||
60b63b72 RS |
9600 | case 'e': |
9601 | /* Must be at least one digit. */ | |
9602 | my_getExpression (&imm_expr, s); | |
9603 | check_absolute_expr (ip, &imm_expr); | |
9604 | ||
9605 | if ((unsigned long) imm_expr.X_add_number | |
9606 | > (unsigned long) OP_MASK_VECBYTE) | |
9607 | { | |
9608 | as_bad (_("bad byte vector index (%ld)"), | |
9609 | (long) imm_expr.X_add_number); | |
9610 | imm_expr.X_add_number = 0; | |
9611 | } | |
9612 | ||
bf12938e | 9613 | INSERT_OPERAND (VECBYTE, *ip, imm_expr.X_add_number); |
60b63b72 RS |
9614 | imm_expr.X_op = O_absent; |
9615 | s = expr_end; | |
9616 | continue; | |
9617 | ||
9618 | case '%': | |
9619 | my_getExpression (&imm_expr, s); | |
9620 | check_absolute_expr (ip, &imm_expr); | |
9621 | ||
9622 | if ((unsigned long) imm_expr.X_add_number | |
9623 | > (unsigned long) OP_MASK_VECALIGN) | |
9624 | { | |
9625 | as_bad (_("bad byte vector index (%ld)"), | |
9626 | (long) imm_expr.X_add_number); | |
9627 | imm_expr.X_add_number = 0; | |
9628 | } | |
9629 | ||
bf12938e | 9630 | INSERT_OPERAND (VECALIGN, *ip, imm_expr.X_add_number); |
60b63b72 RS |
9631 | imm_expr.X_op = O_absent; |
9632 | s = expr_end; | |
9633 | continue; | |
9634 | ||
252b5132 RH |
9635 | default: |
9636 | as_bad (_("bad char = '%c'\n"), *args); | |
9637 | internalError (); | |
9638 | } | |
9639 | break; | |
9640 | } | |
9641 | /* Args don't match. */ | |
9642 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
9643 | !strcmp (insn->name, insn[1].name)) | |
9644 | { | |
9645 | ++insn; | |
9646 | s = argsStart; | |
268f6bed | 9647 | insn_error = _("illegal operands"); |
252b5132 RH |
9648 | continue; |
9649 | } | |
268f6bed L |
9650 | if (save_c) |
9651 | *(--s) = save_c; | |
252b5132 RH |
9652 | insn_error = _("illegal operands"); |
9653 | return; | |
9654 | } | |
9655 | } | |
9656 | ||
0499d65b TS |
9657 | #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); } |
9658 | ||
252b5132 RH |
9659 | /* This routine assembles an instruction into its binary format when |
9660 | assembling for the mips16. As a side effect, it sets one of the | |
9661 | global variables imm_reloc or offset_reloc to the type of | |
9662 | relocation to do if one of the operands is an address expression. | |
9663 | It also sets mips16_small and mips16_ext if the user explicitly | |
9664 | requested a small or extended instruction. */ | |
9665 | ||
9666 | static void | |
17a2f251 | 9667 | mips16_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
9668 | { |
9669 | char *s; | |
9670 | const char *args; | |
9671 | struct mips_opcode *insn; | |
9672 | char *argsstart; | |
9673 | unsigned int regno; | |
9674 | unsigned int lastregno = 0; | |
9675 | char *s_reset; | |
d6f16593 | 9676 | size_t i; |
252b5132 RH |
9677 | |
9678 | insn_error = NULL; | |
9679 | ||
b34976b6 AM |
9680 | mips16_small = FALSE; |
9681 | mips16_ext = FALSE; | |
252b5132 | 9682 | |
3882b010 | 9683 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
9684 | ; |
9685 | switch (*s) | |
9686 | { | |
9687 | case '\0': | |
9688 | break; | |
9689 | ||
9690 | case ' ': | |
9691 | *s++ = '\0'; | |
9692 | break; | |
9693 | ||
9694 | case '.': | |
9695 | if (s[1] == 't' && s[2] == ' ') | |
9696 | { | |
9697 | *s = '\0'; | |
b34976b6 | 9698 | mips16_small = TRUE; |
252b5132 RH |
9699 | s += 3; |
9700 | break; | |
9701 | } | |
9702 | else if (s[1] == 'e' && s[2] == ' ') | |
9703 | { | |
9704 | *s = '\0'; | |
b34976b6 | 9705 | mips16_ext = TRUE; |
252b5132 RH |
9706 | s += 3; |
9707 | break; | |
9708 | } | |
9709 | /* Fall through. */ | |
9710 | default: | |
9711 | insn_error = _("unknown opcode"); | |
9712 | return; | |
9713 | } | |
9714 | ||
9715 | if (mips_opts.noautoextend && ! mips16_ext) | |
b34976b6 | 9716 | mips16_small = TRUE; |
252b5132 RH |
9717 | |
9718 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
9719 | { | |
9720 | insn_error = _("unrecognized opcode"); | |
9721 | return; | |
9722 | } | |
9723 | ||
9724 | argsstart = s; | |
9725 | for (;;) | |
9726 | { | |
9b3f89ee TS |
9727 | bfd_boolean ok; |
9728 | ||
252b5132 RH |
9729 | assert (strcmp (insn->name, str) == 0); |
9730 | ||
9b3f89ee TS |
9731 | if (OPCODE_IS_MEMBER (insn, mips_opts.isa, mips_opts.arch)) |
9732 | ok = TRUE; | |
9733 | else | |
9734 | ok = FALSE; | |
9735 | ||
9736 | if (! ok) | |
9737 | { | |
9738 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] | |
9739 | && strcmp (insn->name, insn[1].name) == 0) | |
9740 | { | |
9741 | ++insn; | |
9742 | continue; | |
9743 | } | |
9744 | else | |
9745 | { | |
9746 | if (!insn_error) | |
9747 | { | |
9748 | static char buf[100]; | |
9749 | sprintf (buf, | |
9750 | _("opcode not supported on this processor: %s (%s)"), | |
9751 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
9752 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
9753 | insn_error = buf; | |
9754 | } | |
9755 | return; | |
9756 | } | |
9757 | } | |
9758 | ||
1e915849 | 9759 | create_insn (ip, insn); |
252b5132 | 9760 | imm_expr.X_op = O_absent; |
f6688943 TS |
9761 | imm_reloc[0] = BFD_RELOC_UNUSED; |
9762 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
9763 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
5f74bc13 | 9764 | imm2_expr.X_op = O_absent; |
252b5132 | 9765 | offset_expr.X_op = O_absent; |
f6688943 TS |
9766 | offset_reloc[0] = BFD_RELOC_UNUSED; |
9767 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
9768 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
9769 | for (args = insn->args; 1; ++args) |
9770 | { | |
9771 | int c; | |
9772 | ||
9773 | if (*s == ' ') | |
9774 | ++s; | |
9775 | ||
9776 | /* In this switch statement we call break if we did not find | |
9777 | a match, continue if we did find a match, or return if we | |
9778 | are done. */ | |
9779 | ||
9780 | c = *args; | |
9781 | switch (c) | |
9782 | { | |
9783 | case '\0': | |
9784 | if (*s == '\0') | |
9785 | { | |
9786 | /* Stuff the immediate value in now, if we can. */ | |
9787 | if (imm_expr.X_op == O_constant | |
f6688943 | 9788 | && *imm_reloc > BFD_RELOC_UNUSED |
252b5132 RH |
9789 | && insn->pinfo != INSN_MACRO) |
9790 | { | |
d6f16593 MR |
9791 | valueT tmp; |
9792 | ||
9793 | switch (*offset_reloc) | |
9794 | { | |
9795 | case BFD_RELOC_MIPS16_HI16_S: | |
9796 | tmp = (imm_expr.X_add_number + 0x8000) >> 16; | |
9797 | break; | |
9798 | ||
9799 | case BFD_RELOC_MIPS16_HI16: | |
9800 | tmp = imm_expr.X_add_number >> 16; | |
9801 | break; | |
9802 | ||
9803 | case BFD_RELOC_MIPS16_LO16: | |
9804 | tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff) | |
9805 | - 0x8000; | |
9806 | break; | |
9807 | ||
9808 | case BFD_RELOC_UNUSED: | |
9809 | tmp = imm_expr.X_add_number; | |
9810 | break; | |
9811 | ||
9812 | default: | |
9813 | internalError (); | |
9814 | } | |
9815 | *offset_reloc = BFD_RELOC_UNUSED; | |
9816 | ||
c4e7957c | 9817 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
d6f16593 | 9818 | tmp, TRUE, mips16_small, |
252b5132 RH |
9819 | mips16_ext, &ip->insn_opcode, |
9820 | &ip->use_extend, &ip->extend); | |
9821 | imm_expr.X_op = O_absent; | |
f6688943 | 9822 | *imm_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
9823 | } |
9824 | ||
9825 | return; | |
9826 | } | |
9827 | break; | |
9828 | ||
9829 | case ',': | |
9830 | if (*s++ == c) | |
9831 | continue; | |
9832 | s--; | |
9833 | switch (*++args) | |
9834 | { | |
9835 | case 'v': | |
bf12938e | 9836 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 RH |
9837 | continue; |
9838 | case 'w': | |
bf12938e | 9839 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
9840 | continue; |
9841 | } | |
9842 | break; | |
9843 | ||
9844 | case '(': | |
9845 | case ')': | |
9846 | if (*s++ == c) | |
9847 | continue; | |
9848 | break; | |
9849 | ||
9850 | case 'v': | |
9851 | case 'w': | |
9852 | if (s[0] != '$') | |
9853 | { | |
9854 | if (c == 'v') | |
bf12938e | 9855 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 | 9856 | else |
bf12938e | 9857 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
9858 | ++args; |
9859 | continue; | |
9860 | } | |
9861 | /* Fall through. */ | |
9862 | case 'x': | |
9863 | case 'y': | |
9864 | case 'z': | |
9865 | case 'Z': | |
9866 | case '0': | |
9867 | case 'S': | |
9868 | case 'R': | |
9869 | case 'X': | |
9870 | case 'Y': | |
707bfff6 TS |
9871 | s_reset = s; |
9872 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) | |
252b5132 | 9873 | { |
707bfff6 | 9874 | if (c == 'v' || c == 'w') |
85b51719 | 9875 | { |
707bfff6 | 9876 | if (c == 'v') |
a9e24354 | 9877 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
707bfff6 | 9878 | else |
a9e24354 | 9879 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
707bfff6 TS |
9880 | ++args; |
9881 | continue; | |
85b51719 | 9882 | } |
707bfff6 | 9883 | break; |
252b5132 RH |
9884 | } |
9885 | ||
9886 | if (*s == ' ') | |
9887 | ++s; | |
9888 | if (args[1] != *s) | |
9889 | { | |
9890 | if (c == 'v' || c == 'w') | |
9891 | { | |
9892 | regno = mips16_to_32_reg_map[lastregno]; | |
9893 | s = s_reset; | |
f9419b05 | 9894 | ++args; |
252b5132 RH |
9895 | } |
9896 | } | |
9897 | ||
9898 | switch (c) | |
9899 | { | |
9900 | case 'x': | |
9901 | case 'y': | |
9902 | case 'z': | |
9903 | case 'v': | |
9904 | case 'w': | |
9905 | case 'Z': | |
9906 | regno = mips32_to_16_reg_map[regno]; | |
9907 | break; | |
9908 | ||
9909 | case '0': | |
9910 | if (regno != 0) | |
9911 | regno = ILLEGAL_REG; | |
9912 | break; | |
9913 | ||
9914 | case 'S': | |
9915 | if (regno != SP) | |
9916 | regno = ILLEGAL_REG; | |
9917 | break; | |
9918 | ||
9919 | case 'R': | |
9920 | if (regno != RA) | |
9921 | regno = ILLEGAL_REG; | |
9922 | break; | |
9923 | ||
9924 | case 'X': | |
9925 | case 'Y': | |
9926 | if (regno == AT && ! mips_opts.noat) | |
9927 | as_warn (_("used $at without \".set noat\"")); | |
9928 | break; | |
9929 | ||
9930 | default: | |
9931 | internalError (); | |
9932 | } | |
9933 | ||
9934 | if (regno == ILLEGAL_REG) | |
9935 | break; | |
9936 | ||
9937 | switch (c) | |
9938 | { | |
9939 | case 'x': | |
9940 | case 'v': | |
bf12938e | 9941 | MIPS16_INSERT_OPERAND (RX, *ip, regno); |
252b5132 RH |
9942 | break; |
9943 | case 'y': | |
9944 | case 'w': | |
bf12938e | 9945 | MIPS16_INSERT_OPERAND (RY, *ip, regno); |
252b5132 RH |
9946 | break; |
9947 | case 'z': | |
bf12938e | 9948 | MIPS16_INSERT_OPERAND (RZ, *ip, regno); |
252b5132 RH |
9949 | break; |
9950 | case 'Z': | |
bf12938e | 9951 | MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno); |
252b5132 RH |
9952 | case '0': |
9953 | case 'S': | |
9954 | case 'R': | |
9955 | break; | |
9956 | case 'X': | |
bf12938e | 9957 | MIPS16_INSERT_OPERAND (REGR32, *ip, regno); |
252b5132 RH |
9958 | break; |
9959 | case 'Y': | |
9960 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
bf12938e | 9961 | MIPS16_INSERT_OPERAND (REG32R, *ip, regno); |
252b5132 RH |
9962 | break; |
9963 | default: | |
9964 | internalError (); | |
9965 | } | |
9966 | ||
9967 | lastregno = regno; | |
9968 | continue; | |
9969 | ||
9970 | case 'P': | |
9971 | if (strncmp (s, "$pc", 3) == 0) | |
9972 | { | |
9973 | s += 3; | |
9974 | continue; | |
9975 | } | |
9976 | break; | |
9977 | ||
252b5132 RH |
9978 | case '5': |
9979 | case 'H': | |
9980 | case 'W': | |
9981 | case 'D': | |
9982 | case 'j': | |
252b5132 RH |
9983 | case 'V': |
9984 | case 'C': | |
9985 | case 'U': | |
9986 | case 'k': | |
9987 | case 'K': | |
d6f16593 MR |
9988 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); |
9989 | if (i > 0) | |
252b5132 | 9990 | { |
d6f16593 | 9991 | if (imm_expr.X_op != O_constant) |
252b5132 | 9992 | { |
b34976b6 | 9993 | mips16_ext = TRUE; |
b34976b6 | 9994 | ip->use_extend = TRUE; |
252b5132 | 9995 | ip->extend = 0; |
252b5132 | 9996 | } |
d6f16593 MR |
9997 | else |
9998 | { | |
9999 | /* We need to relax this instruction. */ | |
10000 | *offset_reloc = *imm_reloc; | |
10001 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
10002 | } | |
10003 | s = expr_end; | |
10004 | continue; | |
252b5132 | 10005 | } |
d6f16593 MR |
10006 | *imm_reloc = BFD_RELOC_UNUSED; |
10007 | /* Fall through. */ | |
10008 | case '<': | |
10009 | case '>': | |
10010 | case '[': | |
10011 | case ']': | |
10012 | case '4': | |
10013 | case '8': | |
10014 | my_getExpression (&imm_expr, s); | |
252b5132 RH |
10015 | if (imm_expr.X_op == O_register) |
10016 | { | |
10017 | /* What we thought was an expression turned out to | |
10018 | be a register. */ | |
10019 | ||
10020 | if (s[0] == '(' && args[1] == '(') | |
10021 | { | |
10022 | /* It looks like the expression was omitted | |
10023 | before a register indirection, which means | |
10024 | that the expression is implicitly zero. We | |
10025 | still set up imm_expr, so that we handle | |
10026 | explicit extensions correctly. */ | |
10027 | imm_expr.X_op = O_constant; | |
10028 | imm_expr.X_add_number = 0; | |
f6688943 | 10029 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
10030 | continue; |
10031 | } | |
10032 | ||
10033 | break; | |
10034 | } | |
10035 | ||
10036 | /* We need to relax this instruction. */ | |
f6688943 | 10037 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
10038 | s = expr_end; |
10039 | continue; | |
10040 | ||
10041 | case 'p': | |
10042 | case 'q': | |
10043 | case 'A': | |
10044 | case 'B': | |
10045 | case 'E': | |
10046 | /* We use offset_reloc rather than imm_reloc for the PC | |
10047 | relative operands. This lets macros with both | |
10048 | immediate and address operands work correctly. */ | |
10049 | my_getExpression (&offset_expr, s); | |
10050 | ||
10051 | if (offset_expr.X_op == O_register) | |
10052 | break; | |
10053 | ||
10054 | /* We need to relax this instruction. */ | |
f6688943 | 10055 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
10056 | s = expr_end; |
10057 | continue; | |
10058 | ||
10059 | case '6': /* break code */ | |
10060 | my_getExpression (&imm_expr, s); | |
10061 | check_absolute_expr (ip, &imm_expr); | |
10062 | if ((unsigned long) imm_expr.X_add_number > 63) | |
bf12938e RS |
10063 | as_warn (_("Invalid value for `%s' (%lu)"), |
10064 | ip->insn_mo->name, | |
10065 | (unsigned long) imm_expr.X_add_number); | |
10066 | MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number); | |
252b5132 RH |
10067 | imm_expr.X_op = O_absent; |
10068 | s = expr_end; | |
10069 | continue; | |
10070 | ||
10071 | case 'a': /* 26 bit address */ | |
10072 | my_getExpression (&offset_expr, s); | |
10073 | s = expr_end; | |
f6688943 | 10074 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
10075 | ip->insn_opcode <<= 16; |
10076 | continue; | |
10077 | ||
10078 | case 'l': /* register list for entry macro */ | |
10079 | case 'L': /* register list for exit macro */ | |
10080 | { | |
10081 | int mask; | |
10082 | ||
10083 | if (c == 'l') | |
10084 | mask = 0; | |
10085 | else | |
10086 | mask = 7 << 3; | |
10087 | while (*s != '\0') | |
10088 | { | |
707bfff6 | 10089 | unsigned int freg, reg1, reg2; |
252b5132 RH |
10090 | |
10091 | while (*s == ' ' || *s == ',') | |
10092 | ++s; | |
707bfff6 | 10093 | if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
252b5132 | 10094 | freg = 0; |
707bfff6 TS |
10095 | else if (reg_lookup (&s, RTYPE_FPU, ®1)) |
10096 | freg = 1; | |
252b5132 RH |
10097 | else |
10098 | { | |
707bfff6 TS |
10099 | as_bad (_("can't parse register list")); |
10100 | break; | |
252b5132 RH |
10101 | } |
10102 | if (*s == ' ') | |
10103 | ++s; | |
10104 | if (*s != '-') | |
10105 | reg2 = reg1; | |
10106 | else | |
10107 | { | |
10108 | ++s; | |
707bfff6 TS |
10109 | if (!reg_lookup (&s, freg ? RTYPE_FPU |
10110 | : (RTYPE_GP | RTYPE_NUM), ®2)) | |
252b5132 | 10111 | { |
707bfff6 TS |
10112 | as_bad (_("invalid register list")); |
10113 | break; | |
252b5132 RH |
10114 | } |
10115 | } | |
10116 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
10117 | { | |
10118 | mask &= ~ (7 << 3); | |
10119 | mask |= 5 << 3; | |
10120 | } | |
10121 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
10122 | { | |
10123 | mask &= ~ (7 << 3); | |
10124 | mask |= 6 << 3; | |
10125 | } | |
10126 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
10127 | mask |= (reg2 - 3) << 3; | |
10128 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
10129 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 10130 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
10131 | mask |= 1; |
10132 | else | |
10133 | { | |
10134 | as_bad (_("invalid register list")); | |
10135 | break; | |
10136 | } | |
10137 | } | |
10138 | /* The mask is filled in in the opcode table for the | |
10139 | benefit of the disassembler. We remove it before | |
10140 | applying the actual mask. */ | |
10141 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
10142 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
10143 | } | |
10144 | continue; | |
10145 | ||
0499d65b TS |
10146 | case 'm': /* Register list for save insn. */ |
10147 | case 'M': /* Register list for restore insn. */ | |
10148 | { | |
10149 | int opcode = 0; | |
10150 | int framesz = 0, seen_framesz = 0; | |
10151 | int args = 0, statics = 0, sregs = 0; | |
10152 | ||
10153 | while (*s != '\0') | |
10154 | { | |
10155 | unsigned int reg1, reg2; | |
10156 | ||
10157 | SKIP_SPACE_TABS (s); | |
10158 | while (*s == ',') | |
10159 | ++s; | |
10160 | SKIP_SPACE_TABS (s); | |
10161 | ||
10162 | my_getExpression (&imm_expr, s); | |
10163 | if (imm_expr.X_op == O_constant) | |
10164 | { | |
10165 | /* Handle the frame size. */ | |
10166 | if (seen_framesz) | |
10167 | { | |
10168 | as_bad (_("more than one frame size in list")); | |
10169 | break; | |
10170 | } | |
10171 | seen_framesz = 1; | |
10172 | framesz = imm_expr.X_add_number; | |
10173 | imm_expr.X_op = O_absent; | |
10174 | s = expr_end; | |
10175 | continue; | |
10176 | } | |
10177 | ||
707bfff6 | 10178 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
0499d65b TS |
10179 | { |
10180 | as_bad (_("can't parse register list")); | |
10181 | break; | |
10182 | } | |
0499d65b | 10183 | |
707bfff6 TS |
10184 | while (*s == ' ') |
10185 | ++s; | |
10186 | ||
0499d65b TS |
10187 | if (*s != '-') |
10188 | reg2 = reg1; | |
10189 | else | |
10190 | { | |
10191 | ++s; | |
707bfff6 TS |
10192 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2) |
10193 | || reg2 < reg1) | |
0499d65b TS |
10194 | { |
10195 | as_bad (_("can't parse register list")); | |
10196 | break; | |
10197 | } | |
0499d65b TS |
10198 | } |
10199 | ||
10200 | while (reg1 <= reg2) | |
10201 | { | |
10202 | if (reg1 >= 4 && reg1 <= 7) | |
10203 | { | |
3a93f742 | 10204 | if (!seen_framesz) |
0499d65b TS |
10205 | /* args $a0-$a3 */ |
10206 | args |= 1 << (reg1 - 4); | |
10207 | else | |
10208 | /* statics $a0-$a3 */ | |
10209 | statics |= 1 << (reg1 - 4); | |
10210 | } | |
10211 | else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30) | |
10212 | { | |
10213 | /* $s0-$s8 */ | |
10214 | sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16)); | |
10215 | } | |
10216 | else if (reg1 == 31) | |
10217 | { | |
10218 | /* Add $ra to insn. */ | |
10219 | opcode |= 0x40; | |
10220 | } | |
10221 | else | |
10222 | { | |
10223 | as_bad (_("unexpected register in list")); | |
10224 | break; | |
10225 | } | |
10226 | if (++reg1 == 24) | |
10227 | reg1 = 30; | |
10228 | } | |
10229 | } | |
10230 | ||
10231 | /* Encode args/statics combination. */ | |
10232 | if (args & statics) | |
10233 | as_bad (_("arg/static registers overlap")); | |
10234 | else if (args == 0xf) | |
10235 | /* All $a0-$a3 are args. */ | |
10236 | opcode |= MIPS16_ALL_ARGS << 16; | |
10237 | else if (statics == 0xf) | |
10238 | /* All $a0-$a3 are statics. */ | |
10239 | opcode |= MIPS16_ALL_STATICS << 16; | |
10240 | else | |
10241 | { | |
10242 | int narg = 0, nstat = 0; | |
10243 | ||
10244 | /* Count arg registers. */ | |
10245 | while (args & 0x1) | |
10246 | { | |
10247 | args >>= 1; | |
10248 | narg++; | |
10249 | } | |
10250 | if (args != 0) | |
10251 | as_bad (_("invalid arg register list")); | |
10252 | ||
10253 | /* Count static registers. */ | |
10254 | while (statics & 0x8) | |
10255 | { | |
10256 | statics = (statics << 1) & 0xf; | |
10257 | nstat++; | |
10258 | } | |
10259 | if (statics != 0) | |
10260 | as_bad (_("invalid static register list")); | |
10261 | ||
10262 | /* Encode args/statics. */ | |
10263 | opcode |= ((narg << 2) | nstat) << 16; | |
10264 | } | |
10265 | ||
10266 | /* Encode $s0/$s1. */ | |
10267 | if (sregs & (1 << 0)) /* $s0 */ | |
10268 | opcode |= 0x20; | |
10269 | if (sregs & (1 << 1)) /* $s1 */ | |
10270 | opcode |= 0x10; | |
10271 | sregs >>= 2; | |
10272 | ||
10273 | if (sregs != 0) | |
10274 | { | |
10275 | /* Count regs $s2-$s8. */ | |
10276 | int nsreg = 0; | |
10277 | while (sregs & 1) | |
10278 | { | |
10279 | sregs >>= 1; | |
10280 | nsreg++; | |
10281 | } | |
10282 | if (sregs != 0) | |
10283 | as_bad (_("invalid static register list")); | |
10284 | /* Encode $s2-$s8. */ | |
10285 | opcode |= nsreg << 24; | |
10286 | } | |
10287 | ||
10288 | /* Encode frame size. */ | |
10289 | if (!seen_framesz) | |
10290 | as_bad (_("missing frame size")); | |
10291 | else if ((framesz & 7) != 0 || framesz < 0 | |
10292 | || framesz > 0xff * 8) | |
10293 | as_bad (_("invalid frame size")); | |
10294 | else if (framesz != 128 || (opcode >> 16) != 0) | |
10295 | { | |
10296 | framesz /= 8; | |
10297 | opcode |= (((framesz & 0xf0) << 16) | |
10298 | | (framesz & 0x0f)); | |
10299 | } | |
10300 | ||
10301 | /* Finally build the instruction. */ | |
10302 | if ((opcode >> 16) != 0 || framesz == 0) | |
10303 | { | |
10304 | ip->use_extend = TRUE; | |
10305 | ip->extend = opcode >> 16; | |
10306 | } | |
10307 | ip->insn_opcode |= opcode & 0x7f; | |
10308 | } | |
10309 | continue; | |
10310 | ||
252b5132 RH |
10311 | case 'e': /* extend code */ |
10312 | my_getExpression (&imm_expr, s); | |
10313 | check_absolute_expr (ip, &imm_expr); | |
10314 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
10315 | { | |
10316 | as_warn (_("Invalid value for `%s' (%lu)"), | |
10317 | ip->insn_mo->name, | |
10318 | (unsigned long) imm_expr.X_add_number); | |
10319 | imm_expr.X_add_number &= 0x7ff; | |
10320 | } | |
10321 | ip->insn_opcode |= imm_expr.X_add_number; | |
10322 | imm_expr.X_op = O_absent; | |
10323 | s = expr_end; | |
10324 | continue; | |
10325 | ||
10326 | default: | |
10327 | internalError (); | |
10328 | } | |
10329 | break; | |
10330 | } | |
10331 | ||
10332 | /* Args don't match. */ | |
10333 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
10334 | strcmp (insn->name, insn[1].name) == 0) | |
10335 | { | |
10336 | ++insn; | |
10337 | s = argsstart; | |
10338 | continue; | |
10339 | } | |
10340 | ||
10341 | insn_error = _("illegal operands"); | |
10342 | ||
10343 | return; | |
10344 | } | |
10345 | } | |
10346 | ||
10347 | /* This structure holds information we know about a mips16 immediate | |
10348 | argument type. */ | |
10349 | ||
e972090a NC |
10350 | struct mips16_immed_operand |
10351 | { | |
252b5132 RH |
10352 | /* The type code used in the argument string in the opcode table. */ |
10353 | int type; | |
10354 | /* The number of bits in the short form of the opcode. */ | |
10355 | int nbits; | |
10356 | /* The number of bits in the extended form of the opcode. */ | |
10357 | int extbits; | |
10358 | /* The amount by which the short form is shifted when it is used; | |
10359 | for example, the sw instruction has a shift count of 2. */ | |
10360 | int shift; | |
10361 | /* The amount by which the short form is shifted when it is stored | |
10362 | into the instruction code. */ | |
10363 | int op_shift; | |
10364 | /* Non-zero if the short form is unsigned. */ | |
10365 | int unsp; | |
10366 | /* Non-zero if the extended form is unsigned. */ | |
10367 | int extu; | |
10368 | /* Non-zero if the value is PC relative. */ | |
10369 | int pcrel; | |
10370 | }; | |
10371 | ||
10372 | /* The mips16 immediate operand types. */ | |
10373 | ||
10374 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
10375 | { | |
10376 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
10377 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
10378 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
10379 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
10380 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
10381 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10382 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10383 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10384 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
10385 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
10386 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10387 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10388 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
10389 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
10390 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
10391 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
10392 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
10393 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
10394 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
10395 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
10396 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
10397 | }; | |
10398 | ||
10399 | #define MIPS16_NUM_IMMED \ | |
10400 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
10401 | ||
10402 | /* Handle a mips16 instruction with an immediate value. This or's the | |
10403 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
10404 | whether an extended value is needed; if one is needed, it sets | |
10405 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
10406 | If SMALL is true, an unextended opcode was explicitly requested. | |
10407 | If EXT is true, an extended opcode was explicitly requested. If | |
10408 | WARN is true, warn if EXT does not match reality. */ | |
10409 | ||
10410 | static void | |
17a2f251 TS |
10411 | mips16_immed (char *file, unsigned int line, int type, offsetT val, |
10412 | bfd_boolean warn, bfd_boolean small, bfd_boolean ext, | |
10413 | unsigned long *insn, bfd_boolean *use_extend, | |
10414 | unsigned short *extend) | |
252b5132 | 10415 | { |
3994f87e | 10416 | const struct mips16_immed_operand *op; |
252b5132 | 10417 | int mintiny, maxtiny; |
b34976b6 | 10418 | bfd_boolean needext; |
252b5132 RH |
10419 | |
10420 | op = mips16_immed_operands; | |
10421 | while (op->type != type) | |
10422 | { | |
10423 | ++op; | |
10424 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
10425 | } | |
10426 | ||
10427 | if (op->unsp) | |
10428 | { | |
10429 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
10430 | { | |
10431 | mintiny = 1; | |
10432 | maxtiny = 1 << op->nbits; | |
10433 | } | |
10434 | else | |
10435 | { | |
10436 | mintiny = 0; | |
10437 | maxtiny = (1 << op->nbits) - 1; | |
10438 | } | |
10439 | } | |
10440 | else | |
10441 | { | |
10442 | mintiny = - (1 << (op->nbits - 1)); | |
10443 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
10444 | } | |
10445 | ||
10446 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
10447 | if (type == 'p' || type == 'q') | |
10448 | val /= 2; | |
10449 | ||
10450 | if ((val & ((1 << op->shift) - 1)) != 0 | |
10451 | || val < (mintiny << op->shift) | |
10452 | || val > (maxtiny << op->shift)) | |
b34976b6 | 10453 | needext = TRUE; |
252b5132 | 10454 | else |
b34976b6 | 10455 | needext = FALSE; |
252b5132 RH |
10456 | |
10457 | if (warn && ext && ! needext) | |
beae10d5 KH |
10458 | as_warn_where (file, line, |
10459 | _("extended operand requested but not required")); | |
252b5132 RH |
10460 | if (small && needext) |
10461 | as_bad_where (file, line, _("invalid unextended operand value")); | |
10462 | ||
10463 | if (small || (! ext && ! needext)) | |
10464 | { | |
10465 | int insnval; | |
10466 | ||
b34976b6 | 10467 | *use_extend = FALSE; |
252b5132 RH |
10468 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
10469 | insnval <<= op->op_shift; | |
10470 | *insn |= insnval; | |
10471 | } | |
10472 | else | |
10473 | { | |
10474 | long minext, maxext; | |
10475 | int extval; | |
10476 | ||
10477 | if (op->extu) | |
10478 | { | |
10479 | minext = 0; | |
10480 | maxext = (1 << op->extbits) - 1; | |
10481 | } | |
10482 | else | |
10483 | { | |
10484 | minext = - (1 << (op->extbits - 1)); | |
10485 | maxext = (1 << (op->extbits - 1)) - 1; | |
10486 | } | |
10487 | if (val < minext || val > maxext) | |
10488 | as_bad_where (file, line, | |
10489 | _("operand value out of range for instruction")); | |
10490 | ||
b34976b6 | 10491 | *use_extend = TRUE; |
252b5132 RH |
10492 | if (op->extbits == 16) |
10493 | { | |
10494 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
10495 | val &= 0x1f; | |
10496 | } | |
10497 | else if (op->extbits == 15) | |
10498 | { | |
10499 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
10500 | val &= 0xf; | |
10501 | } | |
10502 | else | |
10503 | { | |
10504 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
10505 | val = 0; | |
10506 | } | |
10507 | ||
10508 | *extend = (unsigned short) extval; | |
10509 | *insn |= val; | |
10510 | } | |
10511 | } | |
10512 | \f | |
d6f16593 | 10513 | struct percent_op_match |
ad8d3bb3 | 10514 | { |
5e0116d5 RS |
10515 | const char *str; |
10516 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
10517 | }; |
10518 | ||
10519 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 10520 | { |
5e0116d5 | 10521 | {"%lo", BFD_RELOC_LO16}, |
ad8d3bb3 | 10522 | #ifdef OBJ_ELF |
5e0116d5 RS |
10523 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
10524 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
10525 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
10526 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
10527 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
10528 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
10529 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
10530 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
10531 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
10532 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
10533 | {"%half", BFD_RELOC_16}, | |
10534 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
10535 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
10536 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
10537 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
10538 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
10539 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
10540 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
10541 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
10542 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
10543 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
ad8d3bb3 | 10544 | #endif |
5e0116d5 | 10545 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
10546 | }; |
10547 | ||
d6f16593 MR |
10548 | static const struct percent_op_match mips16_percent_op[] = |
10549 | { | |
10550 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
10551 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, | |
10552 | {"%hi", BFD_RELOC_MIPS16_HI16_S} | |
10553 | }; | |
10554 | ||
252b5132 | 10555 | |
5e0116d5 RS |
10556 | /* Return true if *STR points to a relocation operator. When returning true, |
10557 | move *STR over the operator and store its relocation code in *RELOC. | |
10558 | Leave both *STR and *RELOC alone when returning false. */ | |
10559 | ||
10560 | static bfd_boolean | |
17a2f251 | 10561 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 10562 | { |
d6f16593 MR |
10563 | const struct percent_op_match *percent_op; |
10564 | size_t limit, i; | |
10565 | ||
10566 | if (mips_opts.mips16) | |
10567 | { | |
10568 | percent_op = mips16_percent_op; | |
10569 | limit = ARRAY_SIZE (mips16_percent_op); | |
10570 | } | |
10571 | else | |
10572 | { | |
10573 | percent_op = mips_percent_op; | |
10574 | limit = ARRAY_SIZE (mips_percent_op); | |
10575 | } | |
76b3015f | 10576 | |
d6f16593 | 10577 | for (i = 0; i < limit; i++) |
5e0116d5 | 10578 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 10579 | { |
3f98094e DJ |
10580 | int len = strlen (percent_op[i].str); |
10581 | ||
10582 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
10583 | continue; | |
10584 | ||
5e0116d5 RS |
10585 | *str += strlen (percent_op[i].str); |
10586 | *reloc = percent_op[i].reloc; | |
394f9b3a | 10587 | |
5e0116d5 RS |
10588 | /* Check whether the output BFD supports this relocation. |
10589 | If not, issue an error and fall back on something safe. */ | |
10590 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 10591 | { |
5e0116d5 RS |
10592 | as_bad ("relocation %s isn't supported by the current ABI", |
10593 | percent_op[i].str); | |
01a3f561 | 10594 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 10595 | } |
5e0116d5 | 10596 | return TRUE; |
394f9b3a | 10597 | } |
5e0116d5 | 10598 | return FALSE; |
394f9b3a | 10599 | } |
ad8d3bb3 | 10600 | |
ad8d3bb3 | 10601 | |
5e0116d5 RS |
10602 | /* Parse string STR as a 16-bit relocatable operand. Store the |
10603 | expression in *EP and the relocations in the array starting | |
10604 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 10605 | |
01a3f561 | 10606 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 10607 | |
5e0116d5 | 10608 | static size_t |
17a2f251 TS |
10609 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
10610 | char *str) | |
ad8d3bb3 | 10611 | { |
5e0116d5 RS |
10612 | bfd_reloc_code_real_type reversed_reloc[3]; |
10613 | size_t reloc_index, i; | |
09b8f35a RS |
10614 | int crux_depth, str_depth; |
10615 | char *crux; | |
5e0116d5 RS |
10616 | |
10617 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
10618 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
10619 | of the main expression and with CRUX_DEPTH containing the number | |
10620 | of open brackets at that point. */ | |
10621 | reloc_index = -1; | |
10622 | str_depth = 0; | |
10623 | do | |
fb1b3232 | 10624 | { |
09b8f35a RS |
10625 | reloc_index++; |
10626 | crux = str; | |
10627 | crux_depth = str_depth; | |
10628 | ||
10629 | /* Skip over whitespace and brackets, keeping count of the number | |
10630 | of brackets. */ | |
10631 | while (*str == ' ' || *str == '\t' || *str == '(') | |
10632 | if (*str++ == '(') | |
10633 | str_depth++; | |
5e0116d5 | 10634 | } |
09b8f35a RS |
10635 | while (*str == '%' |
10636 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
10637 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 10638 | |
09b8f35a | 10639 | my_getExpression (ep, crux); |
5e0116d5 | 10640 | str = expr_end; |
394f9b3a | 10641 | |
5e0116d5 | 10642 | /* Match every open bracket. */ |
09b8f35a | 10643 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 10644 | if (*str++ == ')') |
09b8f35a | 10645 | crux_depth--; |
394f9b3a | 10646 | |
09b8f35a | 10647 | if (crux_depth > 0) |
5e0116d5 | 10648 | as_bad ("unclosed '('"); |
394f9b3a | 10649 | |
5e0116d5 | 10650 | expr_end = str; |
252b5132 | 10651 | |
01a3f561 | 10652 | if (reloc_index != 0) |
64bdfcaf RS |
10653 | { |
10654 | prev_reloc_op_frag = frag_now; | |
10655 | for (i = 0; i < reloc_index; i++) | |
10656 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
10657 | } | |
fb1b3232 | 10658 | |
5e0116d5 | 10659 | return reloc_index; |
252b5132 RH |
10660 | } |
10661 | ||
10662 | static void | |
17a2f251 | 10663 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
10664 | { |
10665 | char *save_in; | |
98aa84af | 10666 | valueT val; |
252b5132 RH |
10667 | |
10668 | save_in = input_line_pointer; | |
10669 | input_line_pointer = str; | |
10670 | expression (ep); | |
10671 | expr_end = input_line_pointer; | |
10672 | input_line_pointer = save_in; | |
10673 | ||
10674 | /* If we are in mips16 mode, and this is an expression based on `.', | |
10675 | then we bump the value of the symbol by 1 since that is how other | |
10676 | text symbols are handled. We don't bother to handle complex | |
10677 | expressions, just `.' plus or minus a constant. */ | |
10678 | if (mips_opts.mips16 | |
10679 | && ep->X_op == O_symbol | |
10680 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
10681 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
49309057 ILT |
10682 | && symbol_get_frag (ep->X_add_symbol) == frag_now |
10683 | && symbol_constant_p (ep->X_add_symbol) | |
98aa84af AM |
10684 | && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ()) |
10685 | S_SET_VALUE (ep->X_add_symbol, val + 1); | |
252b5132 RH |
10686 | } |
10687 | ||
10688 | /* Turn a string in input_line_pointer into a floating point constant | |
bc0d738a NC |
10689 | of type TYPE, and store the appropriate bytes in *LITP. The number |
10690 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
252b5132 RH |
10691 | returned, or NULL on OK. */ |
10692 | ||
10693 | char * | |
17a2f251 | 10694 | md_atof (int type, char *litP, int *sizeP) |
252b5132 RH |
10695 | { |
10696 | int prec; | |
10697 | LITTLENUM_TYPE words[4]; | |
10698 | char *t; | |
10699 | int i; | |
10700 | ||
10701 | switch (type) | |
10702 | { | |
10703 | case 'f': | |
10704 | prec = 2; | |
10705 | break; | |
10706 | ||
10707 | case 'd': | |
10708 | prec = 4; | |
10709 | break; | |
10710 | ||
10711 | default: | |
10712 | *sizeP = 0; | |
10713 | return _("bad call to md_atof"); | |
10714 | } | |
10715 | ||
10716 | t = atof_ieee (input_line_pointer, type, words); | |
10717 | if (t) | |
10718 | input_line_pointer = t; | |
10719 | ||
10720 | *sizeP = prec * 2; | |
10721 | ||
10722 | if (! target_big_endian) | |
10723 | { | |
10724 | for (i = prec - 1; i >= 0; i--) | |
10725 | { | |
17a2f251 | 10726 | md_number_to_chars (litP, words[i], 2); |
252b5132 RH |
10727 | litP += 2; |
10728 | } | |
10729 | } | |
10730 | else | |
10731 | { | |
10732 | for (i = 0; i < prec; i++) | |
10733 | { | |
17a2f251 | 10734 | md_number_to_chars (litP, words[i], 2); |
252b5132 RH |
10735 | litP += 2; |
10736 | } | |
10737 | } | |
bdaaa2e1 | 10738 | |
252b5132 RH |
10739 | return NULL; |
10740 | } | |
10741 | ||
10742 | void | |
17a2f251 | 10743 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
10744 | { |
10745 | if (target_big_endian) | |
10746 | number_to_chars_bigendian (buf, val, n); | |
10747 | else | |
10748 | number_to_chars_littleendian (buf, val, n); | |
10749 | } | |
10750 | \f | |
ae948b86 | 10751 | #ifdef OBJ_ELF |
e013f690 TS |
10752 | static int support_64bit_objects(void) |
10753 | { | |
10754 | const char **list, **l; | |
aa3d8fdf | 10755 | int yes; |
e013f690 TS |
10756 | |
10757 | list = bfd_target_list (); | |
10758 | for (l = list; *l != NULL; l++) | |
10759 | #ifdef TE_TMIPS | |
10760 | /* This is traditional mips */ | |
10761 | if (strcmp (*l, "elf64-tradbigmips") == 0 | |
10762 | || strcmp (*l, "elf64-tradlittlemips") == 0) | |
10763 | #else | |
10764 | if (strcmp (*l, "elf64-bigmips") == 0 | |
10765 | || strcmp (*l, "elf64-littlemips") == 0) | |
10766 | #endif | |
10767 | break; | |
aa3d8fdf | 10768 | yes = (*l != NULL); |
e013f690 | 10769 | free (list); |
aa3d8fdf | 10770 | return yes; |
e013f690 | 10771 | } |
ae948b86 | 10772 | #endif /* OBJ_ELF */ |
e013f690 | 10773 | |
78849248 | 10774 | const char *md_shortopts = "O::g::G:"; |
252b5132 | 10775 | |
e972090a NC |
10776 | struct option md_longopts[] = |
10777 | { | |
f9b4148d CD |
10778 | /* Options which specify architecture. */ |
10779 | #define OPTION_ARCH_BASE (OPTION_MD_BASE) | |
10780 | #define OPTION_MARCH (OPTION_ARCH_BASE + 0) | |
10781 | {"march", required_argument, NULL, OPTION_MARCH}, | |
10782 | #define OPTION_MTUNE (OPTION_ARCH_BASE + 1) | |
10783 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
10784 | #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2) | |
252b5132 RH |
10785 | {"mips0", no_argument, NULL, OPTION_MIPS1}, |
10786 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
f9b4148d | 10787 | #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3) |
252b5132 | 10788 | {"mips2", no_argument, NULL, OPTION_MIPS2}, |
f9b4148d | 10789 | #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4) |
252b5132 | 10790 | {"mips3", no_argument, NULL, OPTION_MIPS3}, |
f9b4148d | 10791 | #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5) |
252b5132 | 10792 | {"mips4", no_argument, NULL, OPTION_MIPS4}, |
f9b4148d | 10793 | #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6) |
ae948b86 | 10794 | {"mips5", no_argument, NULL, OPTION_MIPS5}, |
f9b4148d | 10795 | #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7) |
ae948b86 | 10796 | {"mips32", no_argument, NULL, OPTION_MIPS32}, |
f9b4148d | 10797 | #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8) |
ae948b86 | 10798 | {"mips64", no_argument, NULL, OPTION_MIPS64}, |
f9b4148d CD |
10799 | #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9) |
10800 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, | |
5f74bc13 CD |
10801 | #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10) |
10802 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, | |
f9b4148d CD |
10803 | |
10804 | /* Options which specify Application Specific Extensions (ASEs). */ | |
5f74bc13 | 10805 | #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11) |
f9b4148d CD |
10806 | #define OPTION_MIPS16 (OPTION_ASE_BASE + 0) |
10807 | {"mips16", no_argument, NULL, OPTION_MIPS16}, | |
10808 | #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1) | |
10809 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, | |
10810 | #define OPTION_MIPS3D (OPTION_ASE_BASE + 2) | |
10811 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, | |
10812 | #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3) | |
10813 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, | |
10814 | #define OPTION_MDMX (OPTION_ASE_BASE + 4) | |
10815 | {"mdmx", no_argument, NULL, OPTION_MDMX}, | |
10816 | #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5) | |
10817 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, | |
74cd071d CF |
10818 | #define OPTION_DSP (OPTION_ASE_BASE + 6) |
10819 | {"mdsp", no_argument, NULL, OPTION_DSP}, | |
10820 | #define OPTION_NO_DSP (OPTION_ASE_BASE + 7) | |
10821 | {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, | |
ef2e4d86 CF |
10822 | #define OPTION_MT (OPTION_ASE_BASE + 8) |
10823 | {"mmt", no_argument, NULL, OPTION_MT}, | |
10824 | #define OPTION_NO_MT (OPTION_ASE_BASE + 9) | |
10825 | {"mno-mt", no_argument, NULL, OPTION_NO_MT}, | |
e16bfa71 TS |
10826 | #define OPTION_SMARTMIPS (OPTION_ASE_BASE + 10) |
10827 | {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS}, | |
10828 | #define OPTION_NO_SMARTMIPS (OPTION_ASE_BASE + 11) | |
10829 | {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS}, | |
f9b4148d CD |
10830 | |
10831 | /* Old-style architecture options. Don't add more of these. */ | |
e16bfa71 | 10832 | #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 12) |
f9b4148d CD |
10833 | #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0) |
10834 | {"m4650", no_argument, NULL, OPTION_M4650}, | |
10835 | #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1) | |
10836 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, | |
10837 | #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2) | |
10838 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
10839 | #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3) | |
10840 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
10841 | #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4) | |
10842 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
10843 | #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5) | |
10844 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
10845 | #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6) | |
10846 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
10847 | #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7) | |
10848 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
10849 | ||
10850 | /* Options which enable bug fixes. */ | |
10851 | #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8) | |
10852 | #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0) | |
10853 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, | |
10854 | #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1) | |
10855 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
10856 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
d766e8ec RS |
10857 | #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2) |
10858 | #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3) | |
10859 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, | |
10860 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
7d8e00cf RS |
10861 | #define OPTION_FIX_VR4130 (OPTION_FIX_BASE + 4) |
10862 | #define OPTION_NO_FIX_VR4130 (OPTION_FIX_BASE + 5) | |
10863 | {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, | |
10864 | {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, | |
f9b4148d CD |
10865 | |
10866 | /* Miscellaneous options. */ | |
7d8e00cf | 10867 | #define OPTION_MISC_BASE (OPTION_FIX_BASE + 6) |
1ffcab4b | 10868 | #define OPTION_TRAP (OPTION_MISC_BASE + 0) |
252b5132 RH |
10869 | {"trap", no_argument, NULL, OPTION_TRAP}, |
10870 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
1ffcab4b | 10871 | #define OPTION_BREAK (OPTION_MISC_BASE + 1) |
252b5132 RH |
10872 | {"break", no_argument, NULL, OPTION_BREAK}, |
10873 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
1ffcab4b | 10874 | #define OPTION_EB (OPTION_MISC_BASE + 2) |
252b5132 | 10875 | {"EB", no_argument, NULL, OPTION_EB}, |
1ffcab4b | 10876 | #define OPTION_EL (OPTION_MISC_BASE + 3) |
252b5132 | 10877 | {"EL", no_argument, NULL, OPTION_EL}, |
1ffcab4b | 10878 | #define OPTION_FP32 (OPTION_MISC_BASE + 4) |
ae948b86 | 10879 | {"mfp32", no_argument, NULL, OPTION_FP32}, |
1ffcab4b | 10880 | #define OPTION_GP32 (OPTION_MISC_BASE + 5) |
c97ef257 | 10881 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
1ffcab4b | 10882 | #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6) |
119d663a | 10883 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
1ffcab4b | 10884 | #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7) |
119d663a | 10885 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
1ffcab4b | 10886 | #define OPTION_FP64 (OPTION_MISC_BASE + 8) |
316f5878 | 10887 | {"mfp64", no_argument, NULL, OPTION_FP64}, |
1ffcab4b | 10888 | #define OPTION_GP64 (OPTION_MISC_BASE + 9) |
ae948b86 | 10889 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
1ffcab4b CD |
10890 | #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10) |
10891 | #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11) | |
4a6a3df4 AO |
10892 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, |
10893 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
aa6975fb ILT |
10894 | #define OPTION_MSHARED (OPTION_MISC_BASE + 12) |
10895 | #define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13) | |
10896 | {"mshared", no_argument, NULL, OPTION_MSHARED}, | |
10897 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
aed1a261 RS |
10898 | #define OPTION_MSYM32 (OPTION_MISC_BASE + 14) |
10899 | #define OPTION_MNO_SYM32 (OPTION_MISC_BASE + 15) | |
10900 | {"msym32", no_argument, NULL, OPTION_MSYM32}, | |
10901 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, | |
f9b4148d CD |
10902 | |
10903 | /* ELF-specific options. */ | |
156c2f8b | 10904 | #ifdef OBJ_ELF |
aed1a261 | 10905 | #define OPTION_ELF_BASE (OPTION_MISC_BASE + 16) |
156c2f8b | 10906 | #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0) |
156c2f8b NC |
10907 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
10908 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
ae948b86 | 10909 | #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1) |
156c2f8b | 10910 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
ae948b86 | 10911 | #define OPTION_XGOT (OPTION_ELF_BASE + 2) |
156c2f8b | 10912 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
ae948b86 TS |
10913 | #define OPTION_MABI (OPTION_ELF_BASE + 3) |
10914 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
10915 | #define OPTION_32 (OPTION_ELF_BASE + 4) | |
156c2f8b | 10916 | {"32", no_argument, NULL, OPTION_32}, |
ae948b86 | 10917 | #define OPTION_N32 (OPTION_ELF_BASE + 5) |
e013f690 | 10918 | {"n32", no_argument, NULL, OPTION_N32}, |
ae948b86 | 10919 | #define OPTION_64 (OPTION_ELF_BASE + 6) |
156c2f8b | 10920 | {"64", no_argument, NULL, OPTION_64}, |
ecb4347a DJ |
10921 | #define OPTION_MDEBUG (OPTION_ELF_BASE + 7) |
10922 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, | |
10923 | #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8) | |
10924 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, | |
dcd410fe RO |
10925 | #define OPTION_PDR (OPTION_ELF_BASE + 9) |
10926 | {"mpdr", no_argument, NULL, OPTION_PDR}, | |
10927 | #define OPTION_NO_PDR (OPTION_ELF_BASE + 10) | |
10928 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, | |
0a44bf69 RS |
10929 | #define OPTION_MVXWORKS_PIC (OPTION_ELF_BASE + 11) |
10930 | {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, | |
ae948b86 | 10931 | #endif /* OBJ_ELF */ |
f9b4148d | 10932 | |
252b5132 RH |
10933 | {NULL, no_argument, NULL, 0} |
10934 | }; | |
156c2f8b | 10935 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 10936 | |
316f5878 RS |
10937 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
10938 | NEW_VALUE. Warn if another value was already specified. Note: | |
10939 | we have to defer parsing the -march and -mtune arguments in order | |
10940 | to handle 'from-abi' correctly, since the ABI might be specified | |
10941 | in a later argument. */ | |
10942 | ||
10943 | static void | |
17a2f251 | 10944 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
10945 | { |
10946 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
10947 | as_warn (_("A different %s was already specified, is now %s"), | |
10948 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
10949 | new_value); | |
10950 | ||
10951 | *string_ptr = new_value; | |
10952 | } | |
10953 | ||
252b5132 | 10954 | int |
17a2f251 | 10955 | md_parse_option (int c, char *arg) |
252b5132 RH |
10956 | { |
10957 | switch (c) | |
10958 | { | |
119d663a NC |
10959 | case OPTION_CONSTRUCT_FLOATS: |
10960 | mips_disable_float_construction = 0; | |
10961 | break; | |
bdaaa2e1 | 10962 | |
119d663a NC |
10963 | case OPTION_NO_CONSTRUCT_FLOATS: |
10964 | mips_disable_float_construction = 1; | |
10965 | break; | |
bdaaa2e1 | 10966 | |
252b5132 RH |
10967 | case OPTION_TRAP: |
10968 | mips_trap = 1; | |
10969 | break; | |
10970 | ||
10971 | case OPTION_BREAK: | |
10972 | mips_trap = 0; | |
10973 | break; | |
10974 | ||
10975 | case OPTION_EB: | |
10976 | target_big_endian = 1; | |
10977 | break; | |
10978 | ||
10979 | case OPTION_EL: | |
10980 | target_big_endian = 0; | |
10981 | break; | |
10982 | ||
10983 | case 'O': | |
10984 | if (arg && arg[1] == '0') | |
10985 | mips_optimize = 1; | |
10986 | else | |
10987 | mips_optimize = 2; | |
10988 | break; | |
10989 | ||
10990 | case 'g': | |
10991 | if (arg == NULL) | |
10992 | mips_debug = 2; | |
10993 | else | |
10994 | mips_debug = atoi (arg); | |
252b5132 RH |
10995 | break; |
10996 | ||
10997 | case OPTION_MIPS1: | |
316f5878 | 10998 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
10999 | break; |
11000 | ||
11001 | case OPTION_MIPS2: | |
316f5878 | 11002 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
11003 | break; |
11004 | ||
11005 | case OPTION_MIPS3: | |
316f5878 | 11006 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
11007 | break; |
11008 | ||
11009 | case OPTION_MIPS4: | |
316f5878 | 11010 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
11011 | break; |
11012 | ||
84ea6cf2 | 11013 | case OPTION_MIPS5: |
316f5878 | 11014 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
11015 | break; |
11016 | ||
e7af610e | 11017 | case OPTION_MIPS32: |
316f5878 | 11018 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
11019 | break; |
11020 | ||
af7ee8bf CD |
11021 | case OPTION_MIPS32R2: |
11022 | file_mips_isa = ISA_MIPS32R2; | |
11023 | break; | |
11024 | ||
5f74bc13 CD |
11025 | case OPTION_MIPS64R2: |
11026 | file_mips_isa = ISA_MIPS64R2; | |
11027 | break; | |
11028 | ||
84ea6cf2 | 11029 | case OPTION_MIPS64: |
316f5878 | 11030 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
11031 | break; |
11032 | ||
ec68c924 | 11033 | case OPTION_MTUNE: |
316f5878 RS |
11034 | mips_set_option_string (&mips_tune_string, arg); |
11035 | break; | |
ec68c924 | 11036 | |
316f5878 RS |
11037 | case OPTION_MARCH: |
11038 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
11039 | break; |
11040 | ||
11041 | case OPTION_M4650: | |
316f5878 RS |
11042 | mips_set_option_string (&mips_arch_string, "4650"); |
11043 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
11044 | break; |
11045 | ||
11046 | case OPTION_NO_M4650: | |
11047 | break; | |
11048 | ||
11049 | case OPTION_M4010: | |
316f5878 RS |
11050 | mips_set_option_string (&mips_arch_string, "4010"); |
11051 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
11052 | break; |
11053 | ||
11054 | case OPTION_NO_M4010: | |
11055 | break; | |
11056 | ||
11057 | case OPTION_M4100: | |
316f5878 RS |
11058 | mips_set_option_string (&mips_arch_string, "4100"); |
11059 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
11060 | break; |
11061 | ||
11062 | case OPTION_NO_M4100: | |
11063 | break; | |
11064 | ||
252b5132 | 11065 | case OPTION_M3900: |
316f5878 RS |
11066 | mips_set_option_string (&mips_arch_string, "3900"); |
11067 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 11068 | break; |
bdaaa2e1 | 11069 | |
252b5132 RH |
11070 | case OPTION_NO_M3900: |
11071 | break; | |
11072 | ||
deec1734 CD |
11073 | case OPTION_MDMX: |
11074 | mips_opts.ase_mdmx = 1; | |
11075 | break; | |
11076 | ||
11077 | case OPTION_NO_MDMX: | |
11078 | mips_opts.ase_mdmx = 0; | |
11079 | break; | |
11080 | ||
74cd071d CF |
11081 | case OPTION_DSP: |
11082 | mips_opts.ase_dsp = 1; | |
11083 | break; | |
11084 | ||
11085 | case OPTION_NO_DSP: | |
11086 | mips_opts.ase_dsp = 0; | |
11087 | break; | |
11088 | ||
ef2e4d86 CF |
11089 | case OPTION_MT: |
11090 | mips_opts.ase_mt = 1; | |
11091 | break; | |
11092 | ||
11093 | case OPTION_NO_MT: | |
11094 | mips_opts.ase_mt = 0; | |
11095 | break; | |
11096 | ||
252b5132 RH |
11097 | case OPTION_MIPS16: |
11098 | mips_opts.mips16 = 1; | |
7d10b47d | 11099 | mips_no_prev_insn (); |
252b5132 RH |
11100 | break; |
11101 | ||
11102 | case OPTION_NO_MIPS16: | |
11103 | mips_opts.mips16 = 0; | |
7d10b47d | 11104 | mips_no_prev_insn (); |
252b5132 RH |
11105 | break; |
11106 | ||
1f25f5d3 CD |
11107 | case OPTION_MIPS3D: |
11108 | mips_opts.ase_mips3d = 1; | |
11109 | break; | |
11110 | ||
11111 | case OPTION_NO_MIPS3D: | |
11112 | mips_opts.ase_mips3d = 0; | |
11113 | break; | |
11114 | ||
e16bfa71 TS |
11115 | case OPTION_SMARTMIPS: |
11116 | mips_opts.ase_smartmips = 1; | |
11117 | break; | |
11118 | ||
11119 | case OPTION_NO_SMARTMIPS: | |
11120 | mips_opts.ase_smartmips = 0; | |
11121 | break; | |
11122 | ||
d766e8ec RS |
11123 | case OPTION_FIX_VR4120: |
11124 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
11125 | break; |
11126 | ||
d766e8ec RS |
11127 | case OPTION_NO_FIX_VR4120: |
11128 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
11129 | break; |
11130 | ||
7d8e00cf RS |
11131 | case OPTION_FIX_VR4130: |
11132 | mips_fix_vr4130 = 1; | |
11133 | break; | |
11134 | ||
11135 | case OPTION_NO_FIX_VR4130: | |
11136 | mips_fix_vr4130 = 0; | |
11137 | break; | |
11138 | ||
4a6a3df4 AO |
11139 | case OPTION_RELAX_BRANCH: |
11140 | mips_relax_branch = 1; | |
11141 | break; | |
11142 | ||
11143 | case OPTION_NO_RELAX_BRANCH: | |
11144 | mips_relax_branch = 0; | |
11145 | break; | |
11146 | ||
aa6975fb ILT |
11147 | case OPTION_MSHARED: |
11148 | mips_in_shared = TRUE; | |
11149 | break; | |
11150 | ||
11151 | case OPTION_MNO_SHARED: | |
11152 | mips_in_shared = FALSE; | |
11153 | break; | |
11154 | ||
aed1a261 RS |
11155 | case OPTION_MSYM32: |
11156 | mips_opts.sym32 = TRUE; | |
11157 | break; | |
11158 | ||
11159 | case OPTION_MNO_SYM32: | |
11160 | mips_opts.sym32 = FALSE; | |
11161 | break; | |
11162 | ||
0f074f60 | 11163 | #ifdef OBJ_ELF |
252b5132 RH |
11164 | /* When generating ELF code, we permit -KPIC and -call_shared to |
11165 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
11166 | intended to be compatible with Irix 5. */ | |
11167 | case OPTION_CALL_SHARED: | |
f43abd2b | 11168 | if (!IS_ELF) |
252b5132 RH |
11169 | { |
11170 | as_bad (_("-call_shared is supported only for ELF format")); | |
11171 | return 0; | |
11172 | } | |
11173 | mips_pic = SVR4_PIC; | |
143d77c5 | 11174 | mips_abicalls = TRUE; |
252b5132 RH |
11175 | break; |
11176 | ||
11177 | case OPTION_NON_SHARED: | |
f43abd2b | 11178 | if (!IS_ELF) |
252b5132 RH |
11179 | { |
11180 | as_bad (_("-non_shared is supported only for ELF format")); | |
11181 | return 0; | |
11182 | } | |
11183 | mips_pic = NO_PIC; | |
143d77c5 | 11184 | mips_abicalls = FALSE; |
252b5132 RH |
11185 | break; |
11186 | ||
44075ae2 TS |
11187 | /* The -xgot option tells the assembler to use 32 bit offsets |
11188 | when accessing the got in SVR4_PIC mode. It is for Irix | |
252b5132 RH |
11189 | compatibility. */ |
11190 | case OPTION_XGOT: | |
11191 | mips_big_got = 1; | |
11192 | break; | |
0f074f60 | 11193 | #endif /* OBJ_ELF */ |
252b5132 RH |
11194 | |
11195 | case 'G': | |
6caf9ef4 TS |
11196 | g_switch_value = atoi (arg); |
11197 | g_switch_seen = 1; | |
252b5132 RH |
11198 | break; |
11199 | ||
0f074f60 | 11200 | #ifdef OBJ_ELF |
34ba82a8 TS |
11201 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
11202 | and -mabi=64. */ | |
252b5132 | 11203 | case OPTION_32: |
f43abd2b | 11204 | if (!IS_ELF) |
34ba82a8 TS |
11205 | { |
11206 | as_bad (_("-32 is supported for ELF format only")); | |
11207 | return 0; | |
11208 | } | |
316f5878 | 11209 | mips_abi = O32_ABI; |
252b5132 RH |
11210 | break; |
11211 | ||
e013f690 | 11212 | case OPTION_N32: |
f43abd2b | 11213 | if (!IS_ELF) |
34ba82a8 TS |
11214 | { |
11215 | as_bad (_("-n32 is supported for ELF format only")); | |
11216 | return 0; | |
11217 | } | |
316f5878 | 11218 | mips_abi = N32_ABI; |
e013f690 | 11219 | break; |
252b5132 | 11220 | |
e013f690 | 11221 | case OPTION_64: |
f43abd2b | 11222 | if (!IS_ELF) |
34ba82a8 TS |
11223 | { |
11224 | as_bad (_("-64 is supported for ELF format only")); | |
11225 | return 0; | |
11226 | } | |
316f5878 | 11227 | mips_abi = N64_ABI; |
f43abd2b | 11228 | if (!support_64bit_objects()) |
e013f690 | 11229 | as_fatal (_("No compiled in support for 64 bit object file format")); |
252b5132 | 11230 | break; |
ae948b86 | 11231 | #endif /* OBJ_ELF */ |
252b5132 | 11232 | |
c97ef257 | 11233 | case OPTION_GP32: |
a325df1d | 11234 | file_mips_gp32 = 1; |
c97ef257 AH |
11235 | break; |
11236 | ||
11237 | case OPTION_GP64: | |
a325df1d | 11238 | file_mips_gp32 = 0; |
c97ef257 | 11239 | break; |
252b5132 | 11240 | |
ca4e0257 | 11241 | case OPTION_FP32: |
a325df1d | 11242 | file_mips_fp32 = 1; |
316f5878 RS |
11243 | break; |
11244 | ||
11245 | case OPTION_FP64: | |
11246 | file_mips_fp32 = 0; | |
ca4e0257 RS |
11247 | break; |
11248 | ||
ae948b86 | 11249 | #ifdef OBJ_ELF |
252b5132 | 11250 | case OPTION_MABI: |
f43abd2b | 11251 | if (!IS_ELF) |
34ba82a8 TS |
11252 | { |
11253 | as_bad (_("-mabi is supported for ELF format only")); | |
11254 | return 0; | |
11255 | } | |
e013f690 | 11256 | if (strcmp (arg, "32") == 0) |
316f5878 | 11257 | mips_abi = O32_ABI; |
e013f690 | 11258 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 11259 | mips_abi = O64_ABI; |
e013f690 | 11260 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 11261 | mips_abi = N32_ABI; |
e013f690 TS |
11262 | else if (strcmp (arg, "64") == 0) |
11263 | { | |
316f5878 | 11264 | mips_abi = N64_ABI; |
e013f690 TS |
11265 | if (! support_64bit_objects()) |
11266 | as_fatal (_("No compiled in support for 64 bit object file " | |
11267 | "format")); | |
11268 | } | |
11269 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 11270 | mips_abi = EABI_ABI; |
e013f690 | 11271 | else |
da0e507f TS |
11272 | { |
11273 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
11274 | return 0; | |
11275 | } | |
252b5132 | 11276 | break; |
e013f690 | 11277 | #endif /* OBJ_ELF */ |
252b5132 | 11278 | |
6b76fefe | 11279 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 11280 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
11281 | break; |
11282 | ||
9ee72ff1 | 11283 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 11284 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
11285 | break; |
11286 | ||
ecb4347a DJ |
11287 | #ifdef OBJ_ELF |
11288 | case OPTION_MDEBUG: | |
b34976b6 | 11289 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
11290 | break; |
11291 | ||
11292 | case OPTION_NO_MDEBUG: | |
b34976b6 | 11293 | mips_flag_mdebug = FALSE; |
ecb4347a | 11294 | break; |
dcd410fe RO |
11295 | |
11296 | case OPTION_PDR: | |
11297 | mips_flag_pdr = TRUE; | |
11298 | break; | |
11299 | ||
11300 | case OPTION_NO_PDR: | |
11301 | mips_flag_pdr = FALSE; | |
11302 | break; | |
0a44bf69 RS |
11303 | |
11304 | case OPTION_MVXWORKS_PIC: | |
11305 | mips_pic = VXWORKS_PIC; | |
11306 | break; | |
ecb4347a DJ |
11307 | #endif /* OBJ_ELF */ |
11308 | ||
252b5132 RH |
11309 | default: |
11310 | return 0; | |
11311 | } | |
11312 | ||
11313 | return 1; | |
11314 | } | |
316f5878 RS |
11315 | \f |
11316 | /* Set up globals to generate code for the ISA or processor | |
11317 | described by INFO. */ | |
252b5132 | 11318 | |
252b5132 | 11319 | static void |
17a2f251 | 11320 | mips_set_architecture (const struct mips_cpu_info *info) |
252b5132 | 11321 | { |
316f5878 | 11322 | if (info != 0) |
252b5132 | 11323 | { |
fef14a42 TS |
11324 | file_mips_arch = info->cpu; |
11325 | mips_opts.arch = info->cpu; | |
316f5878 | 11326 | mips_opts.isa = info->isa; |
252b5132 | 11327 | } |
252b5132 RH |
11328 | } |
11329 | ||
252b5132 | 11330 | |
316f5878 | 11331 | /* Likewise for tuning. */ |
252b5132 | 11332 | |
316f5878 | 11333 | static void |
17a2f251 | 11334 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
11335 | { |
11336 | if (info != 0) | |
fef14a42 | 11337 | mips_tune = info->cpu; |
316f5878 | 11338 | } |
80cc45a5 | 11339 | |
34ba82a8 | 11340 | |
252b5132 | 11341 | void |
17a2f251 | 11342 | mips_after_parse_args (void) |
e9670677 | 11343 | { |
fef14a42 TS |
11344 | const struct mips_cpu_info *arch_info = 0; |
11345 | const struct mips_cpu_info *tune_info = 0; | |
11346 | ||
e9670677 | 11347 | /* GP relative stuff not working for PE */ |
6caf9ef4 | 11348 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
e9670677 | 11349 | { |
6caf9ef4 | 11350 | if (g_switch_seen && g_switch_value != 0) |
e9670677 MR |
11351 | as_bad (_("-G not supported in this configuration.")); |
11352 | g_switch_value = 0; | |
11353 | } | |
11354 | ||
cac012d6 AO |
11355 | if (mips_abi == NO_ABI) |
11356 | mips_abi = MIPS_DEFAULT_ABI; | |
11357 | ||
22923709 RS |
11358 | /* The following code determines the architecture and register size. |
11359 | Similar code was added to GCC 3.3 (see override_options() in | |
11360 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
11361 | as much as possible. */ | |
e9670677 | 11362 | |
316f5878 | 11363 | if (mips_arch_string != 0) |
fef14a42 | 11364 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 11365 | |
316f5878 | 11366 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 11367 | { |
316f5878 | 11368 | /* Handle -mipsN. At this point, file_mips_isa contains the |
fef14a42 | 11369 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 11370 | the -march selection (if any). */ |
fef14a42 | 11371 | if (arch_info != 0) |
e9670677 | 11372 | { |
316f5878 RS |
11373 | /* -march takes precedence over -mipsN, since it is more descriptive. |
11374 | There's no harm in specifying both as long as the ISA levels | |
11375 | are the same. */ | |
fef14a42 | 11376 | if (file_mips_isa != arch_info->isa) |
316f5878 RS |
11377 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), |
11378 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
fef14a42 | 11379 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 11380 | } |
316f5878 | 11381 | else |
fef14a42 | 11382 | arch_info = mips_cpu_info_from_isa (file_mips_isa); |
e9670677 MR |
11383 | } |
11384 | ||
fef14a42 TS |
11385 | if (arch_info == 0) |
11386 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
e9670677 | 11387 | |
fef14a42 | 11388 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
316f5878 | 11389 | as_bad ("-march=%s is not compatible with the selected ABI", |
fef14a42 TS |
11390 | arch_info->name); |
11391 | ||
11392 | mips_set_architecture (arch_info); | |
11393 | ||
11394 | /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ | |
11395 | if (mips_tune_string != 0) | |
11396 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 11397 | |
fef14a42 TS |
11398 | if (tune_info == 0) |
11399 | mips_set_tune (arch_info); | |
11400 | else | |
11401 | mips_set_tune (tune_info); | |
e9670677 | 11402 | |
316f5878 | 11403 | if (file_mips_gp32 >= 0) |
e9670677 | 11404 | { |
316f5878 RS |
11405 | /* The user specified the size of the integer registers. Make sure |
11406 | it agrees with the ABI and ISA. */ | |
11407 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
11408 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
11409 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
11410 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
11411 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
11412 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
11413 | } |
11414 | else | |
11415 | { | |
316f5878 RS |
11416 | /* Infer the integer register size from the ABI and processor. |
11417 | Restrict ourselves to 32-bit registers if that's all the | |
11418 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
11419 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
11420 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
11421 | } |
11422 | ||
ad3fea08 TS |
11423 | switch (file_mips_fp32) |
11424 | { | |
11425 | default: | |
11426 | case -1: | |
11427 | /* No user specified float register size. | |
11428 | ??? GAS treats single-float processors as though they had 64-bit | |
11429 | float registers (although it complains when double-precision | |
11430 | instructions are used). As things stand, saying they have 32-bit | |
11431 | registers would lead to spurious "register must be even" messages. | |
11432 | So here we assume float registers are never smaller than the | |
11433 | integer ones. */ | |
11434 | if (file_mips_gp32 == 0) | |
11435 | /* 64-bit integer registers implies 64-bit float registers. */ | |
11436 | file_mips_fp32 = 0; | |
11437 | else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0) | |
11438 | && ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
11439 | /* -mips3d and -mdmx imply 64-bit float registers, if possible. */ | |
11440 | file_mips_fp32 = 0; | |
11441 | else | |
11442 | /* 32-bit float registers. */ | |
11443 | file_mips_fp32 = 1; | |
11444 | break; | |
11445 | ||
11446 | /* The user specified the size of the float registers. Check if it | |
11447 | agrees with the ABI and ISA. */ | |
11448 | case 0: | |
11449 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
11450 | as_bad (_("-mfp64 used with a 32-bit fpu")); | |
11451 | else if (ABI_NEEDS_32BIT_REGS (mips_abi) | |
11452 | && !ISA_HAS_MXHC1 (mips_opts.isa)) | |
11453 | as_warn (_("-mfp64 used with a 32-bit ABI")); | |
11454 | break; | |
11455 | case 1: | |
11456 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
11457 | as_warn (_("-mfp32 used with a 64-bit ABI")); | |
11458 | break; | |
11459 | } | |
e9670677 | 11460 | |
316f5878 | 11461 | /* End of GCC-shared inference code. */ |
e9670677 | 11462 | |
17a2f251 TS |
11463 | /* This flag is set when we have a 64-bit capable CPU but use only |
11464 | 32-bit wide registers. Note that EABI does not use it. */ | |
11465 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) | |
11466 | && ((mips_abi == NO_ABI && file_mips_gp32 == 1) | |
11467 | || mips_abi == O32_ABI)) | |
316f5878 | 11468 | mips_32bitmode = 1; |
e9670677 MR |
11469 | |
11470 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
11471 | as_bad (_("trap exception not supported at ISA 1")); | |
11472 | ||
e9670677 MR |
11473 | /* If the selected architecture includes support for ASEs, enable |
11474 | generation of code for them. */ | |
a4672219 | 11475 | if (mips_opts.mips16 == -1) |
fef14a42 | 11476 | mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 11477 | if (mips_opts.ase_mips3d == -1) |
65263ce3 | 11478 | mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D) |
ad3fea08 TS |
11479 | && file_mips_fp32 == 0) ? 1 : 0; |
11480 | if (mips_opts.ase_mips3d && file_mips_fp32 == 1) | |
11481 | as_bad (_("-mfp32 used with -mips3d")); | |
11482 | ||
ffdefa66 | 11483 | if (mips_opts.ase_mdmx == -1) |
65263ce3 | 11484 | mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX) |
ad3fea08 TS |
11485 | && file_mips_fp32 == 0) ? 1 : 0; |
11486 | if (mips_opts.ase_mdmx && file_mips_fp32 == 1) | |
11487 | as_bad (_("-mfp32 used with -mdmx")); | |
11488 | ||
11489 | if (mips_opts.ase_smartmips == -1) | |
11490 | mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0; | |
11491 | if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS) | |
11492 | as_warn ("%s ISA does not support SmartMIPS", | |
11493 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
11494 | ||
74cd071d | 11495 | if (mips_opts.ase_dsp == -1) |
ad3fea08 TS |
11496 | mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0; |
11497 | if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE) | |
11498 | as_warn ("%s ISA does not support DSP ASE", | |
11499 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
11500 | ||
ef2e4d86 | 11501 | if (mips_opts.ase_mt == -1) |
ad3fea08 TS |
11502 | mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0; |
11503 | if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE) | |
11504 | as_warn ("%s ISA does not support MT ASE", | |
11505 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
e9670677 | 11506 | |
e9670677 | 11507 | file_mips_isa = mips_opts.isa; |
a4672219 | 11508 | file_ase_mips16 = mips_opts.mips16; |
e9670677 MR |
11509 | file_ase_mips3d = mips_opts.ase_mips3d; |
11510 | file_ase_mdmx = mips_opts.ase_mdmx; | |
e16bfa71 | 11511 | file_ase_smartmips = mips_opts.ase_smartmips; |
74cd071d | 11512 | file_ase_dsp = mips_opts.ase_dsp; |
ef2e4d86 | 11513 | file_ase_mt = mips_opts.ase_mt; |
e9670677 MR |
11514 | mips_opts.gp32 = file_mips_gp32; |
11515 | mips_opts.fp32 = file_mips_fp32; | |
11516 | ||
ecb4347a DJ |
11517 | if (mips_flag_mdebug < 0) |
11518 | { | |
11519 | #ifdef OBJ_MAYBE_ECOFF | |
11520 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) | |
11521 | mips_flag_mdebug = 1; | |
11522 | else | |
11523 | #endif /* OBJ_MAYBE_ECOFF */ | |
11524 | mips_flag_mdebug = 0; | |
11525 | } | |
e9670677 MR |
11526 | } |
11527 | \f | |
11528 | void | |
17a2f251 | 11529 | mips_init_after_args (void) |
252b5132 RH |
11530 | { |
11531 | /* initialize opcodes */ | |
11532 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 11533 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
11534 | } |
11535 | ||
11536 | long | |
17a2f251 | 11537 | md_pcrel_from (fixS *fixP) |
252b5132 | 11538 | { |
a7ebbfdf TS |
11539 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
11540 | switch (fixP->fx_r_type) | |
11541 | { | |
11542 | case BFD_RELOC_16_PCREL_S2: | |
11543 | case BFD_RELOC_MIPS_JMP: | |
11544 | /* Return the address of the delay slot. */ | |
11545 | return addr + 4; | |
11546 | default: | |
58ea3d6a | 11547 | /* We have no relocation type for PC relative MIPS16 instructions. */ |
64817874 TS |
11548 | if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg) |
11549 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11550 | _("PC relative MIPS16 instruction references a different section")); | |
a7ebbfdf TS |
11551 | return addr; |
11552 | } | |
252b5132 RH |
11553 | } |
11554 | ||
252b5132 RH |
11555 | /* This is called before the symbol table is processed. In order to |
11556 | work with gcc when using mips-tfile, we must keep all local labels. | |
11557 | However, in other cases, we want to discard them. If we were | |
11558 | called with -g, but we didn't see any debugging information, it may | |
11559 | mean that gcc is smuggling debugging information through to | |
11560 | mips-tfile, in which case we must generate all local labels. */ | |
11561 | ||
11562 | void | |
17a2f251 | 11563 | mips_frob_file_before_adjust (void) |
252b5132 RH |
11564 | { |
11565 | #ifndef NO_ECOFF_DEBUGGING | |
11566 | if (ECOFF_DEBUGGING | |
11567 | && mips_debug != 0 | |
11568 | && ! ecoff_debugging_seen) | |
11569 | flag_keep_locals = 1; | |
11570 | #endif | |
11571 | } | |
11572 | ||
3b91255e | 11573 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
55cf6793 | 11574 | the corresponding LO16 reloc. This is called before md_apply_fix and |
3b91255e RS |
11575 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit |
11576 | relocation operators. | |
11577 | ||
11578 | For our purposes, a %lo() expression matches a %got() or %hi() | |
11579 | expression if: | |
11580 | ||
11581 | (a) it refers to the same symbol; and | |
11582 | (b) the offset applied in the %lo() expression is no lower than | |
11583 | the offset applied in the %got() or %hi(). | |
11584 | ||
11585 | (b) allows us to cope with code like: | |
11586 | ||
11587 | lui $4,%hi(foo) | |
11588 | lh $4,%lo(foo+2)($4) | |
11589 | ||
11590 | ...which is legal on RELA targets, and has a well-defined behaviour | |
11591 | if the user knows that adding 2 to "foo" will not induce a carry to | |
11592 | the high 16 bits. | |
11593 | ||
11594 | When several %lo()s match a particular %got() or %hi(), we use the | |
11595 | following rules to distinguish them: | |
11596 | ||
11597 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
11598 | higher offsets. | |
11599 | ||
11600 | (2) %lo()s with no matching %got() or %hi() are better than those | |
11601 | that already have a matching %got() or %hi(). | |
11602 | ||
11603 | (3) later %lo()s are better than earlier %lo()s. | |
11604 | ||
11605 | These rules are applied in order. | |
11606 | ||
11607 | (1) means, among other things, that %lo()s with identical offsets are | |
11608 | chosen if they exist. | |
11609 | ||
11610 | (2) means that we won't associate several high-part relocations with | |
11611 | the same low-part relocation unless there's no alternative. Having | |
11612 | several high parts for the same low part is a GNU extension; this rule | |
11613 | allows careful users to avoid it. | |
11614 | ||
11615 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
11616 | with the last high-part relocation being at the front of the list. | |
11617 | It therefore makes sense to choose the last matching low-part | |
11618 | relocation, all other things being equal. It's also easier | |
11619 | to code that way. */ | |
252b5132 RH |
11620 | |
11621 | void | |
17a2f251 | 11622 | mips_frob_file (void) |
252b5132 RH |
11623 | { |
11624 | struct mips_hi_fixup *l; | |
11625 | ||
11626 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
11627 | { | |
11628 | segment_info_type *seginfo; | |
3b91255e RS |
11629 | bfd_boolean matched_lo_p; |
11630 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 11631 | |
5919d012 | 11632 | assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 11633 | |
5919d012 RS |
11634 | /* If a GOT16 relocation turns out to be against a global symbol, |
11635 | there isn't supposed to be a matching LO. */ | |
11636 | if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
11637 | && !pic_need_relax (l->fixp->fx_addsy, l->seg)) | |
11638 | continue; | |
11639 | ||
11640 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
11641 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
11642 | continue; |
11643 | ||
252b5132 | 11644 | seginfo = seg_info (l->seg); |
252b5132 | 11645 | |
3b91255e RS |
11646 | /* Set HI_POS to the position of this relocation in the chain. |
11647 | Set LO_POS to the position of the chosen low-part relocation. | |
11648 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
11649 | relocation that matches an immediately-preceding high-part | |
11650 | relocation. */ | |
11651 | hi_pos = NULL; | |
11652 | lo_pos = NULL; | |
11653 | matched_lo_p = FALSE; | |
11654 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) | |
11655 | { | |
11656 | if (*pos == l->fixp) | |
11657 | hi_pos = pos; | |
11658 | ||
704803a9 MR |
11659 | if (((*pos)->fx_r_type == BFD_RELOC_LO16 |
11660 | || (*pos)->fx_r_type == BFD_RELOC_MIPS16_LO16) | |
3b91255e RS |
11661 | && (*pos)->fx_addsy == l->fixp->fx_addsy |
11662 | && (*pos)->fx_offset >= l->fixp->fx_offset | |
11663 | && (lo_pos == NULL | |
11664 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
11665 | || (!matched_lo_p | |
11666 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
11667 | lo_pos = pos; | |
11668 | ||
11669 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
11670 | && fixup_has_matching_lo_p (*pos)); | |
11671 | } | |
11672 | ||
11673 | /* If we found a match, remove the high-part relocation from its | |
11674 | current position and insert it before the low-part relocation. | |
11675 | Make the offsets match so that fixup_has_matching_lo_p() | |
11676 | will return true. | |
11677 | ||
11678 | We don't warn about unmatched high-part relocations since some | |
11679 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
11680 | instructions. */ | |
11681 | if (lo_pos != NULL) | |
11682 | { | |
11683 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
11684 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 11685 | { |
3b91255e RS |
11686 | *hi_pos = l->fixp->fx_next; |
11687 | l->fixp->fx_next = *lo_pos; | |
11688 | *lo_pos = l->fixp; | |
252b5132 | 11689 | } |
252b5132 RH |
11690 | } |
11691 | } | |
11692 | } | |
11693 | ||
3e722fb5 | 11694 | /* We may have combined relocations without symbols in the N32/N64 ABI. |
f6688943 | 11695 | We have to prevent gas from dropping them. */ |
252b5132 | 11696 | |
252b5132 | 11697 | int |
17a2f251 | 11698 | mips_force_relocation (fixS *fixp) |
252b5132 | 11699 | { |
ae6063d4 | 11700 | if (generic_force_reloc (fixp)) |
252b5132 RH |
11701 | return 1; |
11702 | ||
f6688943 TS |
11703 | if (HAVE_NEWABI |
11704 | && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr | |
11705 | && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB | |
11706 | || fixp->fx_r_type == BFD_RELOC_HI16_S | |
11707 | || fixp->fx_r_type == BFD_RELOC_LO16)) | |
11708 | return 1; | |
11709 | ||
3e722fb5 | 11710 | return 0; |
252b5132 RH |
11711 | } |
11712 | ||
11713 | /* Apply a fixup to the object file. */ | |
11714 | ||
94f592af | 11715 | void |
55cf6793 | 11716 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 11717 | { |
874e8986 | 11718 | bfd_byte *buf; |
98aa84af | 11719 | long insn; |
a7ebbfdf | 11720 | reloc_howto_type *howto; |
252b5132 | 11721 | |
a7ebbfdf TS |
11722 | /* We ignore generic BFD relocations we don't know about. */ |
11723 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
11724 | if (! howto) | |
11725 | return; | |
65551fa4 | 11726 | |
252b5132 RH |
11727 | assert (fixP->fx_size == 4 |
11728 | || fixP->fx_r_type == BFD_RELOC_16 | |
11729 | || fixP->fx_r_type == BFD_RELOC_64 | |
f6688943 TS |
11730 | || fixP->fx_r_type == BFD_RELOC_CTOR |
11731 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
252b5132 | 11732 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
a7ebbfdf | 11733 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY); |
252b5132 | 11734 | |
a7ebbfdf | 11735 | buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); |
252b5132 | 11736 | |
3994f87e | 11737 | assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2); |
b1dca8ee RS |
11738 | |
11739 | /* Don't treat parts of a composite relocation as done. There are two | |
11740 | reasons for this: | |
11741 | ||
11742 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
11743 | should nevertheless be emitted if the first part is. | |
11744 | ||
11745 | (2) In normal usage, composite relocations are never assembly-time | |
11746 | constants. The easiest way of dealing with the pathological | |
11747 | exceptions is to generate a relocation against STN_UNDEF and | |
11748 | leave everything up to the linker. */ | |
3994f87e | 11749 | if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0) |
252b5132 RH |
11750 | fixP->fx_done = 1; |
11751 | ||
11752 | switch (fixP->fx_r_type) | |
11753 | { | |
3f98094e DJ |
11754 | case BFD_RELOC_MIPS_TLS_GD: |
11755 | case BFD_RELOC_MIPS_TLS_LDM: | |
11756 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: | |
11757 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
11758 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
11759 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: | |
11760 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
11761 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
11762 | /* fall through */ | |
11763 | ||
252b5132 | 11764 | case BFD_RELOC_MIPS_JMP: |
e369bcce TS |
11765 | case BFD_RELOC_MIPS_SHIFT5: |
11766 | case BFD_RELOC_MIPS_SHIFT6: | |
11767 | case BFD_RELOC_MIPS_GOT_DISP: | |
11768 | case BFD_RELOC_MIPS_GOT_PAGE: | |
11769 | case BFD_RELOC_MIPS_GOT_OFST: | |
11770 | case BFD_RELOC_MIPS_SUB: | |
11771 | case BFD_RELOC_MIPS_INSERT_A: | |
11772 | case BFD_RELOC_MIPS_INSERT_B: | |
11773 | case BFD_RELOC_MIPS_DELETE: | |
11774 | case BFD_RELOC_MIPS_HIGHEST: | |
11775 | case BFD_RELOC_MIPS_HIGHER: | |
11776 | case BFD_RELOC_MIPS_SCN_DISP: | |
11777 | case BFD_RELOC_MIPS_REL16: | |
11778 | case BFD_RELOC_MIPS_RELGOT: | |
11779 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
11780 | case BFD_RELOC_HI16: |
11781 | case BFD_RELOC_HI16_S: | |
cdf6fd85 | 11782 | case BFD_RELOC_GPREL16: |
252b5132 RH |
11783 | case BFD_RELOC_MIPS_LITERAL: |
11784 | case BFD_RELOC_MIPS_CALL16: | |
11785 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 11786 | case BFD_RELOC_GPREL32: |
252b5132 RH |
11787 | case BFD_RELOC_MIPS_GOT_HI16: |
11788 | case BFD_RELOC_MIPS_GOT_LO16: | |
11789 | case BFD_RELOC_MIPS_CALL_HI16: | |
11790 | case BFD_RELOC_MIPS_CALL_LO16: | |
11791 | case BFD_RELOC_MIPS16_GPREL: | |
d6f16593 MR |
11792 | case BFD_RELOC_MIPS16_HI16: |
11793 | case BFD_RELOC_MIPS16_HI16_S: | |
252b5132 | 11794 | case BFD_RELOC_MIPS16_JMP: |
54f4ddb3 | 11795 | /* Nothing needed to do. The value comes from the reloc entry. */ |
252b5132 RH |
11796 | break; |
11797 | ||
252b5132 RH |
11798 | case BFD_RELOC_64: |
11799 | /* This is handled like BFD_RELOC_32, but we output a sign | |
11800 | extended value if we are only 32 bits. */ | |
3e722fb5 | 11801 | if (fixP->fx_done) |
252b5132 RH |
11802 | { |
11803 | if (8 <= sizeof (valueT)) | |
2132e3a3 | 11804 | md_number_to_chars ((char *) buf, *valP, 8); |
252b5132 RH |
11805 | else |
11806 | { | |
a7ebbfdf | 11807 | valueT hiv; |
252b5132 | 11808 | |
a7ebbfdf | 11809 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
11810 | hiv = 0xffffffff; |
11811 | else | |
11812 | hiv = 0; | |
b215186b | 11813 | md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)), |
a7ebbfdf | 11814 | *valP, 4); |
b215186b | 11815 | md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)), |
a7ebbfdf | 11816 | hiv, 4); |
252b5132 RH |
11817 | } |
11818 | } | |
11819 | break; | |
11820 | ||
056350c6 | 11821 | case BFD_RELOC_RVA: |
252b5132 | 11822 | case BFD_RELOC_32: |
252b5132 RH |
11823 | case BFD_RELOC_16: |
11824 | /* If we are deleting this reloc entry, we must fill in the | |
54f4ddb3 TS |
11825 | value now. This can happen if we have a .word which is not |
11826 | resolved when it appears but is later defined. */ | |
252b5132 | 11827 | if (fixP->fx_done) |
54f4ddb3 | 11828 | md_number_to_chars ((char *) buf, *valP, fixP->fx_size); |
252b5132 RH |
11829 | break; |
11830 | ||
11831 | case BFD_RELOC_LO16: | |
d6f16593 | 11832 | case BFD_RELOC_MIPS16_LO16: |
3e722fb5 CD |
11833 | /* FIXME: Now that embedded-PIC is gone, some of this code/comment |
11834 | may be safe to remove, but if so it's not obvious. */ | |
252b5132 RH |
11835 | /* When handling an embedded PIC switch statement, we can wind |
11836 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
11837 | if (fixP->fx_done) | |
11838 | { | |
a7ebbfdf | 11839 | if (*valP + 0x8000 > 0xffff) |
252b5132 RH |
11840 | as_bad_where (fixP->fx_file, fixP->fx_line, |
11841 | _("relocation overflow")); | |
252b5132 RH |
11842 | if (target_big_endian) |
11843 | buf += 2; | |
2132e3a3 | 11844 | md_number_to_chars ((char *) buf, *valP, 2); |
252b5132 RH |
11845 | } |
11846 | break; | |
11847 | ||
11848 | case BFD_RELOC_16_PCREL_S2: | |
a7ebbfdf | 11849 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 11850 | as_bad_where (fixP->fx_file, fixP->fx_line, |
bad36eac | 11851 | _("Branch to misaligned address (%lx)"), (long) *valP); |
cb56d3d3 | 11852 | |
54f4ddb3 TS |
11853 | /* We need to save the bits in the instruction since fixup_segment() |
11854 | might be deleting the relocation entry (i.e., a branch within | |
11855 | the current segment). */ | |
a7ebbfdf | 11856 | if (! fixP->fx_done) |
bb2d6cd7 | 11857 | break; |
252b5132 | 11858 | |
54f4ddb3 | 11859 | /* Update old instruction data. */ |
252b5132 RH |
11860 | if (target_big_endian) |
11861 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
11862 | else | |
11863 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
11864 | ||
a7ebbfdf TS |
11865 | if (*valP + 0x20000 <= 0x3ffff) |
11866 | { | |
11867 | insn |= (*valP >> 2) & 0xffff; | |
2132e3a3 | 11868 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
11869 | } |
11870 | else if (mips_pic == NO_PIC | |
11871 | && fixP->fx_done | |
11872 | && fixP->fx_frag->fr_address >= text_section->vma | |
11873 | && (fixP->fx_frag->fr_address | |
587aac4e | 11874 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
11875 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
11876 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
11877 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
11878 | { |
11879 | /* The branch offset is too large. If this is an | |
11880 | unconditional branch, and we are not generating PIC code, | |
11881 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
11882 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
11883 | insn = 0x0c000000; /* jal */ | |
252b5132 | 11884 | else |
a7ebbfdf TS |
11885 | insn = 0x08000000; /* j */ |
11886 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
11887 | fixP->fx_done = 0; | |
11888 | fixP->fx_addsy = section_symbol (text_section); | |
11889 | *valP += md_pcrel_from (fixP); | |
2132e3a3 | 11890 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
11891 | } |
11892 | else | |
11893 | { | |
11894 | /* If we got here, we have branch-relaxation disabled, | |
11895 | and there's nothing we can do to fix this instruction | |
11896 | without turning it into a longer sequence. */ | |
11897 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11898 | _("Branch out of range")); | |
252b5132 | 11899 | } |
252b5132 RH |
11900 | break; |
11901 | ||
11902 | case BFD_RELOC_VTABLE_INHERIT: | |
11903 | fixP->fx_done = 0; | |
11904 | if (fixP->fx_addsy | |
11905 | && !S_IS_DEFINED (fixP->fx_addsy) | |
11906 | && !S_IS_WEAK (fixP->fx_addsy)) | |
11907 | S_SET_WEAK (fixP->fx_addsy); | |
11908 | break; | |
11909 | ||
11910 | case BFD_RELOC_VTABLE_ENTRY: | |
11911 | fixP->fx_done = 0; | |
11912 | break; | |
11913 | ||
11914 | default: | |
11915 | internalError (); | |
11916 | } | |
a7ebbfdf TS |
11917 | |
11918 | /* Remember value for tc_gen_reloc. */ | |
11919 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
11920 | } |
11921 | ||
252b5132 | 11922 | static symbolS * |
17a2f251 | 11923 | get_symbol (void) |
252b5132 RH |
11924 | { |
11925 | int c; | |
11926 | char *name; | |
11927 | symbolS *p; | |
11928 | ||
11929 | name = input_line_pointer; | |
11930 | c = get_symbol_end (); | |
11931 | p = (symbolS *) symbol_find_or_make (name); | |
11932 | *input_line_pointer = c; | |
11933 | return p; | |
11934 | } | |
11935 | ||
11936 | /* Align the current frag to a given power of two. The MIPS assembler | |
11937 | also automatically adjusts any preceding label. */ | |
11938 | ||
11939 | static void | |
17a2f251 | 11940 | mips_align (int to, int fill, symbolS *label) |
252b5132 | 11941 | { |
7d10b47d | 11942 | mips_emit_delays (); |
252b5132 RH |
11943 | frag_align (to, fill, 0); |
11944 | record_alignment (now_seg, to); | |
11945 | if (label != NULL) | |
11946 | { | |
11947 | assert (S_GET_SEGMENT (label) == now_seg); | |
49309057 | 11948 | symbol_set_frag (label, frag_now); |
252b5132 RH |
11949 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
11950 | } | |
11951 | } | |
11952 | ||
11953 | /* Align to a given power of two. .align 0 turns off the automatic | |
11954 | alignment used by the data creating pseudo-ops. */ | |
11955 | ||
11956 | static void | |
17a2f251 | 11957 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 | 11958 | { |
3994f87e TS |
11959 | int temp; |
11960 | long temp_fill; | |
252b5132 RH |
11961 | long max_alignment = 15; |
11962 | ||
54f4ddb3 | 11963 | /* o Note that the assembler pulls down any immediately preceding label |
252b5132 | 11964 | to the aligned address. |
54f4ddb3 | 11965 | o It's not documented but auto alignment is reinstated by |
252b5132 | 11966 | a .align pseudo instruction. |
54f4ddb3 | 11967 | o Note also that after auto alignment is turned off the mips assembler |
252b5132 | 11968 | issues an error on attempt to assemble an improperly aligned data item. |
54f4ddb3 | 11969 | We don't. */ |
252b5132 RH |
11970 | |
11971 | temp = get_absolute_expression (); | |
11972 | if (temp > max_alignment) | |
11973 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
11974 | else if (temp < 0) | |
11975 | { | |
11976 | as_warn (_("Alignment negative: 0 assumed.")); | |
11977 | temp = 0; | |
11978 | } | |
11979 | if (*input_line_pointer == ',') | |
11980 | { | |
f9419b05 | 11981 | ++input_line_pointer; |
252b5132 RH |
11982 | temp_fill = get_absolute_expression (); |
11983 | } | |
11984 | else | |
11985 | temp_fill = 0; | |
11986 | if (temp) | |
11987 | { | |
a8dbcb85 TS |
11988 | segment_info_type *si = seg_info (now_seg); |
11989 | struct insn_label_list *l = si->label_list; | |
54f4ddb3 | 11990 | /* Auto alignment should be switched on by next section change. */ |
252b5132 | 11991 | auto_align = 1; |
a8dbcb85 | 11992 | mips_align (temp, (int) temp_fill, l != NULL ? l->label : NULL); |
252b5132 RH |
11993 | } |
11994 | else | |
11995 | { | |
11996 | auto_align = 0; | |
11997 | } | |
11998 | ||
11999 | demand_empty_rest_of_line (); | |
12000 | } | |
12001 | ||
252b5132 | 12002 | static void |
17a2f251 | 12003 | s_change_sec (int sec) |
252b5132 RH |
12004 | { |
12005 | segT seg; | |
12006 | ||
252b5132 RH |
12007 | #ifdef OBJ_ELF |
12008 | /* The ELF backend needs to know that we are changing sections, so | |
12009 | that .previous works correctly. We could do something like check | |
b6ff326e | 12010 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
12011 | as it would not be appropriate to use it in the section changing |
12012 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
12013 | This should be cleaner, somehow. */ | |
f43abd2b TS |
12014 | if (IS_ELF) |
12015 | obj_elf_section_change_hook (); | |
252b5132 RH |
12016 | #endif |
12017 | ||
7d10b47d | 12018 | mips_emit_delays (); |
252b5132 RH |
12019 | switch (sec) |
12020 | { | |
12021 | case 't': | |
12022 | s_text (0); | |
12023 | break; | |
12024 | case 'd': | |
12025 | s_data (0); | |
12026 | break; | |
12027 | case 'b': | |
12028 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
12029 | demand_empty_rest_of_line (); | |
12030 | break; | |
12031 | ||
12032 | case 'r': | |
4d0d148d TS |
12033 | seg = subseg_new (RDATA_SECTION_NAME, |
12034 | (subsegT) get_absolute_expression ()); | |
f43abd2b | 12035 | if (IS_ELF) |
252b5132 | 12036 | { |
4d0d148d TS |
12037 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
12038 | | SEC_READONLY | SEC_RELOC | |
12039 | | SEC_DATA)); | |
12040 | if (strcmp (TARGET_OS, "elf") != 0) | |
12041 | record_alignment (seg, 4); | |
252b5132 | 12042 | } |
4d0d148d | 12043 | demand_empty_rest_of_line (); |
252b5132 RH |
12044 | break; |
12045 | ||
12046 | case 's': | |
4d0d148d | 12047 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
f43abd2b | 12048 | if (IS_ELF) |
252b5132 | 12049 | { |
4d0d148d TS |
12050 | bfd_set_section_flags (stdoutput, seg, |
12051 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
12052 | if (strcmp (TARGET_OS, "elf") != 0) | |
12053 | record_alignment (seg, 4); | |
252b5132 | 12054 | } |
4d0d148d TS |
12055 | demand_empty_rest_of_line (); |
12056 | break; | |
252b5132 RH |
12057 | } |
12058 | ||
12059 | auto_align = 1; | |
12060 | } | |
b34976b6 | 12061 | |
cca86cc8 | 12062 | void |
17a2f251 | 12063 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 12064 | { |
7ed4a06a | 12065 | #ifdef OBJ_ELF |
cca86cc8 SC |
12066 | char *section_name; |
12067 | char c; | |
684022ea | 12068 | char next_c = 0; |
cca86cc8 SC |
12069 | int section_type; |
12070 | int section_flag; | |
12071 | int section_entry_size; | |
12072 | int section_alignment; | |
b34976b6 | 12073 | |
f43abd2b | 12074 | if (!IS_ELF) |
7ed4a06a TS |
12075 | return; |
12076 | ||
cca86cc8 SC |
12077 | section_name = input_line_pointer; |
12078 | c = get_symbol_end (); | |
a816d1ed AO |
12079 | if (c) |
12080 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 12081 | |
4cf0dd0d TS |
12082 | /* Do we have .section Name<,"flags">? */ |
12083 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 12084 | { |
4cf0dd0d TS |
12085 | /* just after name is now '\0'. */ |
12086 | *input_line_pointer = c; | |
cca86cc8 SC |
12087 | input_line_pointer = section_name; |
12088 | obj_elf_section (ignore); | |
12089 | return; | |
12090 | } | |
12091 | input_line_pointer++; | |
12092 | ||
12093 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
12094 | if (c == ',') | |
12095 | section_type = get_absolute_expression (); | |
12096 | else | |
12097 | section_type = 0; | |
12098 | if (*input_line_pointer++ == ',') | |
12099 | section_flag = get_absolute_expression (); | |
12100 | else | |
12101 | section_flag = 0; | |
12102 | if (*input_line_pointer++ == ',') | |
12103 | section_entry_size = get_absolute_expression (); | |
12104 | else | |
12105 | section_entry_size = 0; | |
12106 | if (*input_line_pointer++ == ',') | |
12107 | section_alignment = get_absolute_expression (); | |
12108 | else | |
12109 | section_alignment = 0; | |
12110 | ||
a816d1ed AO |
12111 | section_name = xstrdup (section_name); |
12112 | ||
8ab8a5c8 RS |
12113 | /* When using the generic form of .section (as implemented by obj-elf.c), |
12114 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
12115 | traditionally had to fall back on the more common @progbits instead. | |
12116 | ||
12117 | There's nothing really harmful in this, since bfd will correct | |
12118 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
708587a4 | 12119 | means that, for backwards compatibility, the special_section entries |
8ab8a5c8 RS |
12120 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. |
12121 | ||
12122 | Even so, we shouldn't force users of the MIPS .section syntax to | |
12123 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
12124 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
12125 | generic type-checking code. */ | |
12126 | if (section_type == SHT_MIPS_DWARF) | |
12127 | section_type = SHT_PROGBITS; | |
12128 | ||
cca86cc8 SC |
12129 | obj_elf_change_section (section_name, section_type, section_flag, |
12130 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
12131 | |
12132 | if (now_seg->name != section_name) | |
12133 | free (section_name); | |
7ed4a06a | 12134 | #endif /* OBJ_ELF */ |
cca86cc8 | 12135 | } |
252b5132 RH |
12136 | |
12137 | void | |
17a2f251 | 12138 | mips_enable_auto_align (void) |
252b5132 RH |
12139 | { |
12140 | auto_align = 1; | |
12141 | } | |
12142 | ||
12143 | static void | |
17a2f251 | 12144 | s_cons (int log_size) |
252b5132 | 12145 | { |
a8dbcb85 TS |
12146 | segment_info_type *si = seg_info (now_seg); |
12147 | struct insn_label_list *l = si->label_list; | |
252b5132 RH |
12148 | symbolS *label; |
12149 | ||
a8dbcb85 | 12150 | label = l != NULL ? l->label : NULL; |
7d10b47d | 12151 | mips_emit_delays (); |
252b5132 RH |
12152 | if (log_size > 0 && auto_align) |
12153 | mips_align (log_size, 0, label); | |
12154 | mips_clear_insn_labels (); | |
12155 | cons (1 << log_size); | |
12156 | } | |
12157 | ||
12158 | static void | |
17a2f251 | 12159 | s_float_cons (int type) |
252b5132 | 12160 | { |
a8dbcb85 TS |
12161 | segment_info_type *si = seg_info (now_seg); |
12162 | struct insn_label_list *l = si->label_list; | |
252b5132 RH |
12163 | symbolS *label; |
12164 | ||
a8dbcb85 | 12165 | label = l != NULL ? l->label : NULL; |
252b5132 | 12166 | |
7d10b47d | 12167 | mips_emit_delays (); |
252b5132 RH |
12168 | |
12169 | if (auto_align) | |
49309057 ILT |
12170 | { |
12171 | if (type == 'd') | |
12172 | mips_align (3, 0, label); | |
12173 | else | |
12174 | mips_align (2, 0, label); | |
12175 | } | |
252b5132 RH |
12176 | |
12177 | mips_clear_insn_labels (); | |
12178 | ||
12179 | float_cons (type); | |
12180 | } | |
12181 | ||
12182 | /* Handle .globl. We need to override it because on Irix 5 you are | |
12183 | permitted to say | |
12184 | .globl foo .text | |
12185 | where foo is an undefined symbol, to mean that foo should be | |
12186 | considered to be the address of a function. */ | |
12187 | ||
12188 | static void | |
17a2f251 | 12189 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
12190 | { |
12191 | char *name; | |
12192 | int c; | |
12193 | symbolS *symbolP; | |
12194 | flagword flag; | |
12195 | ||
8a06b769 | 12196 | do |
252b5132 | 12197 | { |
8a06b769 | 12198 | name = input_line_pointer; |
252b5132 | 12199 | c = get_symbol_end (); |
8a06b769 TS |
12200 | symbolP = symbol_find_or_make (name); |
12201 | S_SET_EXTERNAL (symbolP); | |
12202 | ||
252b5132 | 12203 | *input_line_pointer = c; |
8a06b769 | 12204 | SKIP_WHITESPACE (); |
252b5132 | 12205 | |
8a06b769 TS |
12206 | /* On Irix 5, every global symbol that is not explicitly labelled as |
12207 | being a function is apparently labelled as being an object. */ | |
12208 | flag = BSF_OBJECT; | |
252b5132 | 12209 | |
8a06b769 TS |
12210 | if (!is_end_of_line[(unsigned char) *input_line_pointer] |
12211 | && (*input_line_pointer != ',')) | |
12212 | { | |
12213 | char *secname; | |
12214 | asection *sec; | |
12215 | ||
12216 | secname = input_line_pointer; | |
12217 | c = get_symbol_end (); | |
12218 | sec = bfd_get_section_by_name (stdoutput, secname); | |
12219 | if (sec == NULL) | |
12220 | as_bad (_("%s: no such section"), secname); | |
12221 | *input_line_pointer = c; | |
12222 | ||
12223 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
12224 | flag = BSF_FUNCTION; | |
12225 | } | |
12226 | ||
12227 | symbol_get_bfdsym (symbolP)->flags |= flag; | |
12228 | ||
12229 | c = *input_line_pointer; | |
12230 | if (c == ',') | |
12231 | { | |
12232 | input_line_pointer++; | |
12233 | SKIP_WHITESPACE (); | |
12234 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
12235 | c = '\n'; | |
12236 | } | |
12237 | } | |
12238 | while (c == ','); | |
252b5132 | 12239 | |
252b5132 RH |
12240 | demand_empty_rest_of_line (); |
12241 | } | |
12242 | ||
12243 | static void | |
17a2f251 | 12244 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
12245 | { |
12246 | char *opt; | |
12247 | char c; | |
12248 | ||
12249 | opt = input_line_pointer; | |
12250 | c = get_symbol_end (); | |
12251 | ||
12252 | if (*opt == 'O') | |
12253 | { | |
12254 | /* FIXME: What does this mean? */ | |
12255 | } | |
12256 | else if (strncmp (opt, "pic", 3) == 0) | |
12257 | { | |
12258 | int i; | |
12259 | ||
12260 | i = atoi (opt + 3); | |
12261 | if (i == 0) | |
12262 | mips_pic = NO_PIC; | |
12263 | else if (i == 2) | |
143d77c5 | 12264 | { |
252b5132 | 12265 | mips_pic = SVR4_PIC; |
143d77c5 EC |
12266 | mips_abicalls = TRUE; |
12267 | } | |
252b5132 RH |
12268 | else |
12269 | as_bad (_(".option pic%d not supported"), i); | |
12270 | ||
4d0d148d | 12271 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
12272 | { |
12273 | if (g_switch_seen && g_switch_value != 0) | |
12274 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
12275 | g_switch_value = 0; | |
12276 | bfd_set_gp_size (stdoutput, 0); | |
12277 | } | |
12278 | } | |
12279 | else | |
12280 | as_warn (_("Unrecognized option \"%s\""), opt); | |
12281 | ||
12282 | *input_line_pointer = c; | |
12283 | demand_empty_rest_of_line (); | |
12284 | } | |
12285 | ||
12286 | /* This structure is used to hold a stack of .set values. */ | |
12287 | ||
e972090a NC |
12288 | struct mips_option_stack |
12289 | { | |
252b5132 RH |
12290 | struct mips_option_stack *next; |
12291 | struct mips_set_options options; | |
12292 | }; | |
12293 | ||
12294 | static struct mips_option_stack *mips_opts_stack; | |
12295 | ||
12296 | /* Handle the .set pseudo-op. */ | |
12297 | ||
12298 | static void | |
17a2f251 | 12299 | s_mipsset (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
12300 | { |
12301 | char *name = input_line_pointer, ch; | |
12302 | ||
12303 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 12304 | ++input_line_pointer; |
252b5132 RH |
12305 | ch = *input_line_pointer; |
12306 | *input_line_pointer = '\0'; | |
12307 | ||
12308 | if (strcmp (name, "reorder") == 0) | |
12309 | { | |
7d10b47d RS |
12310 | if (mips_opts.noreorder) |
12311 | end_noreorder (); | |
252b5132 RH |
12312 | } |
12313 | else if (strcmp (name, "noreorder") == 0) | |
12314 | { | |
7d10b47d RS |
12315 | if (!mips_opts.noreorder) |
12316 | start_noreorder (); | |
252b5132 RH |
12317 | } |
12318 | else if (strcmp (name, "at") == 0) | |
12319 | { | |
12320 | mips_opts.noat = 0; | |
12321 | } | |
12322 | else if (strcmp (name, "noat") == 0) | |
12323 | { | |
12324 | mips_opts.noat = 1; | |
12325 | } | |
12326 | else if (strcmp (name, "macro") == 0) | |
12327 | { | |
12328 | mips_opts.warn_about_macros = 0; | |
12329 | } | |
12330 | else if (strcmp (name, "nomacro") == 0) | |
12331 | { | |
12332 | if (mips_opts.noreorder == 0) | |
12333 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
12334 | mips_opts.warn_about_macros = 1; | |
12335 | } | |
12336 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
12337 | { | |
12338 | mips_opts.nomove = 0; | |
12339 | } | |
12340 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
12341 | { | |
12342 | mips_opts.nomove = 1; | |
12343 | } | |
12344 | else if (strcmp (name, "bopt") == 0) | |
12345 | { | |
12346 | mips_opts.nobopt = 0; | |
12347 | } | |
12348 | else if (strcmp (name, "nobopt") == 0) | |
12349 | { | |
12350 | mips_opts.nobopt = 1; | |
12351 | } | |
ad3fea08 TS |
12352 | else if (strcmp (name, "gp=default") == 0) |
12353 | mips_opts.gp32 = file_mips_gp32; | |
12354 | else if (strcmp (name, "gp=32") == 0) | |
12355 | mips_opts.gp32 = 1; | |
12356 | else if (strcmp (name, "gp=64") == 0) | |
12357 | { | |
12358 | if (!ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
12359 | as_warn ("%s isa does not support 64-bit registers", | |
12360 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
12361 | mips_opts.gp32 = 0; | |
12362 | } | |
12363 | else if (strcmp (name, "fp=default") == 0) | |
12364 | mips_opts.fp32 = file_mips_fp32; | |
12365 | else if (strcmp (name, "fp=32") == 0) | |
12366 | mips_opts.fp32 = 1; | |
12367 | else if (strcmp (name, "fp=64") == 0) | |
12368 | { | |
12369 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
12370 | as_warn ("%s isa does not support 64-bit floating point registers", | |
12371 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
12372 | mips_opts.fp32 = 0; | |
12373 | } | |
252b5132 RH |
12374 | else if (strcmp (name, "mips16") == 0 |
12375 | || strcmp (name, "MIPS-16") == 0) | |
12376 | mips_opts.mips16 = 1; | |
12377 | else if (strcmp (name, "nomips16") == 0 | |
12378 | || strcmp (name, "noMIPS-16") == 0) | |
12379 | mips_opts.mips16 = 0; | |
e16bfa71 TS |
12380 | else if (strcmp (name, "smartmips") == 0) |
12381 | { | |
ad3fea08 | 12382 | if (!ISA_SUPPORTS_SMARTMIPS) |
e16bfa71 TS |
12383 | as_warn ("%s ISA does not support SmartMIPS ASE", |
12384 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
12385 | mips_opts.ase_smartmips = 1; | |
12386 | } | |
12387 | else if (strcmp (name, "nosmartmips") == 0) | |
12388 | mips_opts.ase_smartmips = 0; | |
1f25f5d3 CD |
12389 | else if (strcmp (name, "mips3d") == 0) |
12390 | mips_opts.ase_mips3d = 1; | |
12391 | else if (strcmp (name, "nomips3d") == 0) | |
12392 | mips_opts.ase_mips3d = 0; | |
a4672219 TS |
12393 | else if (strcmp (name, "mdmx") == 0) |
12394 | mips_opts.ase_mdmx = 1; | |
12395 | else if (strcmp (name, "nomdmx") == 0) | |
12396 | mips_opts.ase_mdmx = 0; | |
74cd071d | 12397 | else if (strcmp (name, "dsp") == 0) |
ad3fea08 TS |
12398 | { |
12399 | if (!ISA_SUPPORTS_DSP_ASE) | |
12400 | as_warn ("%s ISA does not support DSP ASE", | |
12401 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
12402 | mips_opts.ase_dsp = 1; | |
12403 | } | |
74cd071d CF |
12404 | else if (strcmp (name, "nodsp") == 0) |
12405 | mips_opts.ase_dsp = 0; | |
ef2e4d86 | 12406 | else if (strcmp (name, "mt") == 0) |
ad3fea08 TS |
12407 | { |
12408 | if (!ISA_SUPPORTS_MT_ASE) | |
12409 | as_warn ("%s ISA does not support MT ASE", | |
12410 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
12411 | mips_opts.ase_mt = 1; | |
12412 | } | |
ef2e4d86 CF |
12413 | else if (strcmp (name, "nomt") == 0) |
12414 | mips_opts.ase_mt = 0; | |
1a2c1fad | 12415 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 12416 | { |
af7ee8bf | 12417 | int reset = 0; |
252b5132 | 12418 | |
1a2c1fad CD |
12419 | /* Permit the user to change the ISA and architecture on the fly. |
12420 | Needless to say, misuse can cause serious problems. */ | |
81a21e38 | 12421 | if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) |
af7ee8bf CD |
12422 | { |
12423 | reset = 1; | |
12424 | mips_opts.isa = file_mips_isa; | |
1a2c1fad | 12425 | mips_opts.arch = file_mips_arch; |
1a2c1fad CD |
12426 | } |
12427 | else if (strncmp (name, "arch=", 5) == 0) | |
12428 | { | |
12429 | const struct mips_cpu_info *p; | |
12430 | ||
12431 | p = mips_parse_cpu("internal use", name + 5); | |
12432 | if (!p) | |
12433 | as_bad (_("unknown architecture %s"), name + 5); | |
12434 | else | |
12435 | { | |
12436 | mips_opts.arch = p->cpu; | |
12437 | mips_opts.isa = p->isa; | |
12438 | } | |
12439 | } | |
81a21e38 TS |
12440 | else if (strncmp (name, "mips", 4) == 0) |
12441 | { | |
12442 | const struct mips_cpu_info *p; | |
12443 | ||
12444 | p = mips_parse_cpu("internal use", name); | |
12445 | if (!p) | |
12446 | as_bad (_("unknown ISA level %s"), name + 4); | |
12447 | else | |
12448 | { | |
12449 | mips_opts.arch = p->cpu; | |
12450 | mips_opts.isa = p->isa; | |
12451 | } | |
12452 | } | |
af7ee8bf | 12453 | else |
81a21e38 | 12454 | as_bad (_("unknown ISA or architecture %s"), name); |
af7ee8bf CD |
12455 | |
12456 | switch (mips_opts.isa) | |
98d3f06f KH |
12457 | { |
12458 | case 0: | |
98d3f06f | 12459 | break; |
af7ee8bf CD |
12460 | case ISA_MIPS1: |
12461 | case ISA_MIPS2: | |
12462 | case ISA_MIPS32: | |
12463 | case ISA_MIPS32R2: | |
98d3f06f KH |
12464 | mips_opts.gp32 = 1; |
12465 | mips_opts.fp32 = 1; | |
12466 | break; | |
af7ee8bf CD |
12467 | case ISA_MIPS3: |
12468 | case ISA_MIPS4: | |
12469 | case ISA_MIPS5: | |
12470 | case ISA_MIPS64: | |
5f74bc13 | 12471 | case ISA_MIPS64R2: |
98d3f06f KH |
12472 | mips_opts.gp32 = 0; |
12473 | mips_opts.fp32 = 0; | |
12474 | break; | |
12475 | default: | |
12476 | as_bad (_("unknown ISA level %s"), name + 4); | |
12477 | break; | |
12478 | } | |
af7ee8bf | 12479 | if (reset) |
98d3f06f | 12480 | { |
af7ee8bf CD |
12481 | mips_opts.gp32 = file_mips_gp32; |
12482 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 12483 | } |
252b5132 RH |
12484 | } |
12485 | else if (strcmp (name, "autoextend") == 0) | |
12486 | mips_opts.noautoextend = 0; | |
12487 | else if (strcmp (name, "noautoextend") == 0) | |
12488 | mips_opts.noautoextend = 1; | |
12489 | else if (strcmp (name, "push") == 0) | |
12490 | { | |
12491 | struct mips_option_stack *s; | |
12492 | ||
12493 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
12494 | s->next = mips_opts_stack; | |
12495 | s->options = mips_opts; | |
12496 | mips_opts_stack = s; | |
12497 | } | |
12498 | else if (strcmp (name, "pop") == 0) | |
12499 | { | |
12500 | struct mips_option_stack *s; | |
12501 | ||
12502 | s = mips_opts_stack; | |
12503 | if (s == NULL) | |
12504 | as_bad (_(".set pop with no .set push")); | |
12505 | else | |
12506 | { | |
12507 | /* If we're changing the reorder mode we need to handle | |
12508 | delay slots correctly. */ | |
12509 | if (s->options.noreorder && ! mips_opts.noreorder) | |
7d10b47d | 12510 | start_noreorder (); |
252b5132 | 12511 | else if (! s->options.noreorder && mips_opts.noreorder) |
7d10b47d | 12512 | end_noreorder (); |
252b5132 RH |
12513 | |
12514 | mips_opts = s->options; | |
12515 | mips_opts_stack = s->next; | |
12516 | free (s); | |
12517 | } | |
12518 | } | |
aed1a261 RS |
12519 | else if (strcmp (name, "sym32") == 0) |
12520 | mips_opts.sym32 = TRUE; | |
12521 | else if (strcmp (name, "nosym32") == 0) | |
12522 | mips_opts.sym32 = FALSE; | |
252b5132 RH |
12523 | else |
12524 | { | |
12525 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
12526 | } | |
12527 | *input_line_pointer = ch; | |
12528 | demand_empty_rest_of_line (); | |
12529 | } | |
12530 | ||
12531 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
12532 | .option pic2. It means to generate SVR4 PIC calls. */ | |
12533 | ||
12534 | static void | |
17a2f251 | 12535 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12536 | { |
12537 | mips_pic = SVR4_PIC; | |
143d77c5 | 12538 | mips_abicalls = TRUE; |
4d0d148d TS |
12539 | |
12540 | if (g_switch_seen && g_switch_value != 0) | |
12541 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
12542 | g_switch_value = 0; | |
12543 | ||
252b5132 RH |
12544 | bfd_set_gp_size (stdoutput, 0); |
12545 | demand_empty_rest_of_line (); | |
12546 | } | |
12547 | ||
12548 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
12549 | PIC code. It sets the $gp register for the function based on the | |
12550 | function address, which is in the register named in the argument. | |
12551 | This uses a relocation against _gp_disp, which is handled specially | |
12552 | by the linker. The result is: | |
12553 | lui $gp,%hi(_gp_disp) | |
12554 | addiu $gp,$gp,%lo(_gp_disp) | |
12555 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
12556 | The .cpload argument is normally $25 == $t9. |
12557 | ||
12558 | The -mno-shared option changes this to: | |
bbe506e8 TS |
12559 | lui $gp,%hi(__gnu_local_gp) |
12560 | addiu $gp,$gp,%lo(__gnu_local_gp) | |
aa6975fb ILT |
12561 | and the argument is ignored. This saves an instruction, but the |
12562 | resulting code is not position independent; it uses an absolute | |
bbe506e8 TS |
12563 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
12564 | can go into an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
12565 | |
12566 | static void | |
17a2f251 | 12567 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12568 | { |
12569 | expressionS ex; | |
aa6975fb ILT |
12570 | int reg; |
12571 | int in_shared; | |
252b5132 | 12572 | |
6478892d TS |
12573 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
12574 | .cpload is ignored. */ | |
12575 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
12576 | { |
12577 | s_ignore (0); | |
12578 | return; | |
12579 | } | |
12580 | ||
d3ecfc59 | 12581 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
12582 | if (mips_opts.noreorder == 0) |
12583 | as_warn (_(".cpload not in noreorder section")); | |
12584 | ||
aa6975fb ILT |
12585 | reg = tc_get_register (0); |
12586 | ||
12587 | /* If we need to produce a 64-bit address, we are better off using | |
12588 | the default instruction sequence. */ | |
aed1a261 | 12589 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
aa6975fb | 12590 | |
252b5132 | 12591 | ex.X_op = O_symbol; |
bbe506e8 TS |
12592 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
12593 | "__gnu_local_gp"); | |
252b5132 RH |
12594 | ex.X_op_symbol = NULL; |
12595 | ex.X_add_number = 0; | |
12596 | ||
12597 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 12598 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 12599 | |
584892a6 | 12600 | macro_start (); |
67c0d1eb RS |
12601 | macro_build_lui (&ex, mips_gp_register); |
12602 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 12603 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
12604 | if (in_shared) |
12605 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
12606 | mips_gp_register, reg); | |
584892a6 | 12607 | macro_end (); |
252b5132 RH |
12608 | |
12609 | demand_empty_rest_of_line (); | |
12610 | } | |
12611 | ||
6478892d TS |
12612 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
12613 | .cpsetup $reg1, offset|$reg2, label | |
12614 | ||
12615 | If offset is given, this results in: | |
12616 | sd $gp, offset($sp) | |
956cd1d6 | 12617 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
12618 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
12619 | daddu $gp, $gp, $reg1 | |
6478892d TS |
12620 | |
12621 | If $reg2 is given, this results in: | |
12622 | daddu $reg2, $gp, $0 | |
956cd1d6 | 12623 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
12624 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
12625 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
12626 | $reg1 is normally $25 == $t9. |
12627 | ||
12628 | The -mno-shared option replaces the last three instructions with | |
12629 | lui $gp,%hi(_gp) | |
54f4ddb3 | 12630 | addiu $gp,$gp,%lo(_gp) */ |
aa6975fb | 12631 | |
6478892d | 12632 | static void |
17a2f251 | 12633 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12634 | { |
12635 | expressionS ex_off; | |
12636 | expressionS ex_sym; | |
12637 | int reg1; | |
6478892d | 12638 | |
8586fc66 | 12639 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
12640 | We also need NewABI support. */ |
12641 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12642 | { | |
12643 | s_ignore (0); | |
12644 | return; | |
12645 | } | |
12646 | ||
12647 | reg1 = tc_get_register (0); | |
12648 | SKIP_WHITESPACE (); | |
12649 | if (*input_line_pointer != ',') | |
12650 | { | |
12651 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
12652 | return; | |
12653 | } | |
12654 | else | |
80245285 | 12655 | ++input_line_pointer; |
6478892d TS |
12656 | SKIP_WHITESPACE (); |
12657 | if (*input_line_pointer == '$') | |
80245285 TS |
12658 | { |
12659 | mips_cpreturn_register = tc_get_register (0); | |
12660 | mips_cpreturn_offset = -1; | |
12661 | } | |
6478892d | 12662 | else |
80245285 TS |
12663 | { |
12664 | mips_cpreturn_offset = get_absolute_expression (); | |
12665 | mips_cpreturn_register = -1; | |
12666 | } | |
6478892d TS |
12667 | SKIP_WHITESPACE (); |
12668 | if (*input_line_pointer != ',') | |
12669 | { | |
12670 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
12671 | return; | |
12672 | } | |
12673 | else | |
f9419b05 | 12674 | ++input_line_pointer; |
6478892d | 12675 | SKIP_WHITESPACE (); |
f21f8242 | 12676 | expression (&ex_sym); |
6478892d | 12677 | |
584892a6 | 12678 | macro_start (); |
6478892d TS |
12679 | if (mips_cpreturn_register == -1) |
12680 | { | |
12681 | ex_off.X_op = O_constant; | |
12682 | ex_off.X_add_symbol = NULL; | |
12683 | ex_off.X_op_symbol = NULL; | |
12684 | ex_off.X_add_number = mips_cpreturn_offset; | |
12685 | ||
67c0d1eb | 12686 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 12687 | BFD_RELOC_LO16, SP); |
6478892d TS |
12688 | } |
12689 | else | |
67c0d1eb | 12690 | macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, |
17a2f251 | 12691 | mips_gp_register, 0); |
6478892d | 12692 | |
aed1a261 | 12693 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
aa6975fb ILT |
12694 | { |
12695 | macro_build (&ex_sym, "lui", "t,u", mips_gp_register, | |
12696 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, | |
12697 | BFD_RELOC_HI16_S); | |
12698 | ||
12699 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
12700 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
12701 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
12702 | ||
12703 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
12704 | mips_gp_register, reg1); | |
12705 | } | |
12706 | else | |
12707 | { | |
12708 | expressionS ex; | |
12709 | ||
12710 | ex.X_op = O_symbol; | |
4184909a | 12711 | ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); |
aa6975fb ILT |
12712 | ex.X_op_symbol = NULL; |
12713 | ex.X_add_number = 0; | |
6e1304d8 | 12714 | |
aa6975fb ILT |
12715 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
12716 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
12717 | ||
12718 | macro_build_lui (&ex, mips_gp_register); | |
12719 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
12720 | mips_gp_register, BFD_RELOC_LO16); | |
12721 | } | |
f21f8242 | 12722 | |
584892a6 | 12723 | macro_end (); |
6478892d TS |
12724 | |
12725 | demand_empty_rest_of_line (); | |
12726 | } | |
12727 | ||
12728 | static void | |
17a2f251 | 12729 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12730 | { |
12731 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
54f4ddb3 | 12732 | .cplocal is ignored. */ |
6478892d TS |
12733 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) |
12734 | { | |
12735 | s_ignore (0); | |
12736 | return; | |
12737 | } | |
12738 | ||
12739 | mips_gp_register = tc_get_register (0); | |
85b51719 | 12740 | demand_empty_rest_of_line (); |
6478892d TS |
12741 | } |
12742 | ||
252b5132 RH |
12743 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
12744 | offset from $sp. The offset is remembered, and after making a PIC | |
12745 | call $gp is restored from that location. */ | |
12746 | ||
12747 | static void | |
17a2f251 | 12748 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12749 | { |
12750 | expressionS ex; | |
252b5132 | 12751 | |
6478892d | 12752 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 12753 | .cprestore is ignored. */ |
6478892d | 12754 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
12755 | { |
12756 | s_ignore (0); | |
12757 | return; | |
12758 | } | |
12759 | ||
12760 | mips_cprestore_offset = get_absolute_expression (); | |
7a621144 | 12761 | mips_cprestore_valid = 1; |
252b5132 RH |
12762 | |
12763 | ex.X_op = O_constant; | |
12764 | ex.X_add_symbol = NULL; | |
12765 | ex.X_op_symbol = NULL; | |
12766 | ex.X_add_number = mips_cprestore_offset; | |
12767 | ||
584892a6 | 12768 | macro_start (); |
67c0d1eb RS |
12769 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
12770 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 12771 | macro_end (); |
252b5132 RH |
12772 | |
12773 | demand_empty_rest_of_line (); | |
12774 | } | |
12775 | ||
6478892d | 12776 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 12777 | was given in the preceding .cpsetup, it results in: |
6478892d | 12778 | ld $gp, offset($sp) |
76b3015f | 12779 | |
6478892d | 12780 | If a register $reg2 was given there, it results in: |
54f4ddb3 TS |
12781 | daddu $gp, $reg2, $0 */ |
12782 | ||
6478892d | 12783 | static void |
17a2f251 | 12784 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12785 | { |
12786 | expressionS ex; | |
6478892d TS |
12787 | |
12788 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
12789 | We also need NewABI support. */ | |
12790 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12791 | { | |
12792 | s_ignore (0); | |
12793 | return; | |
12794 | } | |
12795 | ||
584892a6 | 12796 | macro_start (); |
6478892d TS |
12797 | if (mips_cpreturn_register == -1) |
12798 | { | |
12799 | ex.X_op = O_constant; | |
12800 | ex.X_add_symbol = NULL; | |
12801 | ex.X_op_symbol = NULL; | |
12802 | ex.X_add_number = mips_cpreturn_offset; | |
12803 | ||
67c0d1eb | 12804 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
12805 | } |
12806 | else | |
67c0d1eb | 12807 | macro_build (NULL, "daddu", "d,v,t", mips_gp_register, |
17a2f251 | 12808 | mips_cpreturn_register, 0); |
584892a6 | 12809 | macro_end (); |
6478892d TS |
12810 | |
12811 | demand_empty_rest_of_line (); | |
12812 | } | |
12813 | ||
12814 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC | |
12815 | code. It sets the offset to use in gp_rel relocations. */ | |
12816 | ||
12817 | static void | |
17a2f251 | 12818 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
12819 | { |
12820 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
12821 | We also need NewABI support. */ | |
12822 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
12823 | { | |
12824 | s_ignore (0); | |
12825 | return; | |
12826 | } | |
12827 | ||
def2e0dd | 12828 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
12829 | |
12830 | demand_empty_rest_of_line (); | |
12831 | } | |
12832 | ||
252b5132 RH |
12833 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
12834 | code. It generates a 32 bit GP relative reloc. */ | |
12835 | ||
12836 | static void | |
17a2f251 | 12837 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 12838 | { |
a8dbcb85 TS |
12839 | segment_info_type *si; |
12840 | struct insn_label_list *l; | |
252b5132 RH |
12841 | symbolS *label; |
12842 | expressionS ex; | |
12843 | char *p; | |
12844 | ||
12845 | /* When not generating PIC code, this is treated as .word. */ | |
12846 | if (mips_pic != SVR4_PIC) | |
12847 | { | |
12848 | s_cons (2); | |
12849 | return; | |
12850 | } | |
12851 | ||
a8dbcb85 TS |
12852 | si = seg_info (now_seg); |
12853 | l = si->label_list; | |
12854 | label = l != NULL ? l->label : NULL; | |
7d10b47d | 12855 | mips_emit_delays (); |
252b5132 RH |
12856 | if (auto_align) |
12857 | mips_align (2, 0, label); | |
12858 | mips_clear_insn_labels (); | |
12859 | ||
12860 | expression (&ex); | |
12861 | ||
12862 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
12863 | { | |
12864 | as_bad (_("Unsupported use of .gpword")); | |
12865 | ignore_rest_of_line (); | |
12866 | } | |
12867 | ||
12868 | p = frag_more (4); | |
17a2f251 | 12869 | md_number_to_chars (p, 0, 4); |
b34976b6 | 12870 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 12871 | BFD_RELOC_GPREL32); |
252b5132 RH |
12872 | |
12873 | demand_empty_rest_of_line (); | |
12874 | } | |
12875 | ||
10181a0d | 12876 | static void |
17a2f251 | 12877 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d | 12878 | { |
a8dbcb85 TS |
12879 | segment_info_type *si; |
12880 | struct insn_label_list *l; | |
10181a0d AO |
12881 | symbolS *label; |
12882 | expressionS ex; | |
12883 | char *p; | |
12884 | ||
12885 | /* When not generating PIC code, this is treated as .dword. */ | |
12886 | if (mips_pic != SVR4_PIC) | |
12887 | { | |
12888 | s_cons (3); | |
12889 | return; | |
12890 | } | |
12891 | ||
a8dbcb85 TS |
12892 | si = seg_info (now_seg); |
12893 | l = si->label_list; | |
12894 | label = l != NULL ? l->label : NULL; | |
7d10b47d | 12895 | mips_emit_delays (); |
10181a0d AO |
12896 | if (auto_align) |
12897 | mips_align (3, 0, label); | |
12898 | mips_clear_insn_labels (); | |
12899 | ||
12900 | expression (&ex); | |
12901 | ||
12902 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
12903 | { | |
12904 | as_bad (_("Unsupported use of .gpdword")); | |
12905 | ignore_rest_of_line (); | |
12906 | } | |
12907 | ||
12908 | p = frag_more (8); | |
17a2f251 | 12909 | md_number_to_chars (p, 0, 8); |
a105a300 | 12910 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 12911 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
12912 | |
12913 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
12914 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
12915 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
12916 | |
12917 | demand_empty_rest_of_line (); | |
12918 | } | |
12919 | ||
252b5132 RH |
12920 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
12921 | tables in SVR4 PIC code. */ | |
12922 | ||
12923 | static void | |
17a2f251 | 12924 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 12925 | { |
252b5132 RH |
12926 | int reg; |
12927 | ||
10181a0d AO |
12928 | /* This is ignored when not generating SVR4 PIC code. */ |
12929 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
12930 | { |
12931 | s_ignore (0); | |
12932 | return; | |
12933 | } | |
12934 | ||
12935 | /* Add $gp to the register named as an argument. */ | |
584892a6 | 12936 | macro_start (); |
252b5132 | 12937 | reg = tc_get_register (0); |
67c0d1eb | 12938 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 12939 | macro_end (); |
252b5132 | 12940 | |
bdaaa2e1 | 12941 | demand_empty_rest_of_line (); |
252b5132 RH |
12942 | } |
12943 | ||
12944 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
12945 | mips16 mode. This permits the linker to handle them specially, | |
12946 | such as generating jalx instructions when needed. We also make | |
12947 | them odd for the duration of the assembly, in order to generate the | |
12948 | right sort of code. We will make them even in the adjust_symtab | |
12949 | routine, while leaving them marked. This is convenient for the | |
12950 | debugger and the disassembler. The linker knows to make them odd | |
12951 | again. */ | |
12952 | ||
12953 | static void | |
17a2f251 | 12954 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 12955 | { |
f9419b05 | 12956 | mips16_mark_labels (); |
252b5132 RH |
12957 | |
12958 | demand_empty_rest_of_line (); | |
12959 | } | |
12960 | ||
12961 | /* Handle a .stabn directive. We need these in order to mark a label | |
12962 | as being a mips16 text label correctly. Sometimes the compiler | |
12963 | will emit a label, followed by a .stabn, and then switch sections. | |
12964 | If the label and .stabn are in mips16 mode, then the label is | |
12965 | really a mips16 text label. */ | |
12966 | ||
12967 | static void | |
17a2f251 | 12968 | s_mips_stab (int type) |
252b5132 | 12969 | { |
f9419b05 | 12970 | if (type == 'n') |
252b5132 RH |
12971 | mips16_mark_labels (); |
12972 | ||
12973 | s_stab (type); | |
12974 | } | |
12975 | ||
54f4ddb3 | 12976 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */ |
252b5132 RH |
12977 | |
12978 | static void | |
17a2f251 | 12979 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12980 | { |
12981 | char *name; | |
12982 | int c; | |
12983 | symbolS *symbolP; | |
12984 | expressionS exp; | |
12985 | ||
12986 | name = input_line_pointer; | |
12987 | c = get_symbol_end (); | |
12988 | symbolP = symbol_find_or_make (name); | |
12989 | S_SET_WEAK (symbolP); | |
12990 | *input_line_pointer = c; | |
12991 | ||
12992 | SKIP_WHITESPACE (); | |
12993 | ||
12994 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
12995 | { | |
12996 | if (S_IS_DEFINED (symbolP)) | |
12997 | { | |
956cd1d6 | 12998 | as_bad ("ignoring attempt to redefine symbol %s", |
252b5132 RH |
12999 | S_GET_NAME (symbolP)); |
13000 | ignore_rest_of_line (); | |
13001 | return; | |
13002 | } | |
bdaaa2e1 | 13003 | |
252b5132 RH |
13004 | if (*input_line_pointer == ',') |
13005 | { | |
13006 | ++input_line_pointer; | |
13007 | SKIP_WHITESPACE (); | |
13008 | } | |
bdaaa2e1 | 13009 | |
252b5132 RH |
13010 | expression (&exp); |
13011 | if (exp.X_op != O_symbol) | |
13012 | { | |
13013 | as_bad ("bad .weakext directive"); | |
98d3f06f | 13014 | ignore_rest_of_line (); |
252b5132 RH |
13015 | return; |
13016 | } | |
49309057 | 13017 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
13018 | } |
13019 | ||
13020 | demand_empty_rest_of_line (); | |
13021 | } | |
13022 | ||
13023 | /* Parse a register string into a number. Called from the ECOFF code | |
13024 | to parse .frame. The argument is non-zero if this is the frame | |
13025 | register, so that we can record it in mips_frame_reg. */ | |
13026 | ||
13027 | int | |
17a2f251 | 13028 | tc_get_register (int frame) |
252b5132 | 13029 | { |
707bfff6 | 13030 | unsigned int reg; |
252b5132 RH |
13031 | |
13032 | SKIP_WHITESPACE (); | |
707bfff6 TS |
13033 | if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®)) |
13034 | reg = 0; | |
252b5132 | 13035 | if (frame) |
7a621144 DJ |
13036 | { |
13037 | mips_frame_reg = reg != 0 ? reg : SP; | |
13038 | mips_frame_reg_valid = 1; | |
13039 | mips_cprestore_valid = 0; | |
13040 | } | |
252b5132 RH |
13041 | return reg; |
13042 | } | |
13043 | ||
13044 | valueT | |
17a2f251 | 13045 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
13046 | { |
13047 | int align = bfd_get_section_alignment (stdoutput, seg); | |
13048 | ||
b4c71f56 TS |
13049 | if (IS_ELF) |
13050 | { | |
13051 | /* We don't need to align ELF sections to the full alignment. | |
13052 | However, Irix 5 may prefer that we align them at least to a 16 | |
13053 | byte boundary. We don't bother to align the sections if we | |
13054 | are targeted for an embedded system. */ | |
13055 | if (strcmp (TARGET_OS, "elf") == 0) | |
13056 | return addr; | |
13057 | if (align > 4) | |
13058 | align = 4; | |
13059 | } | |
252b5132 RH |
13060 | |
13061 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
13062 | } | |
13063 | ||
13064 | /* Utility routine, called from above as well. If called while the | |
13065 | input file is still being read, it's only an approximation. (For | |
13066 | example, a symbol may later become defined which appeared to be | |
13067 | undefined earlier.) */ | |
13068 | ||
13069 | static int | |
17a2f251 | 13070 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
13071 | { |
13072 | if (sym == 0) | |
13073 | return 0; | |
13074 | ||
4d0d148d | 13075 | if (g_switch_value > 0) |
252b5132 RH |
13076 | { |
13077 | const char *symname; | |
13078 | int change; | |
13079 | ||
c9914766 | 13080 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
13081 | register. It can be if it is smaller than the -G size or if |
13082 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 13083 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
13084 | they can. */ |
13085 | symname = S_GET_NAME (sym); | |
13086 | if (symname != (const char *) NULL | |
13087 | && (strcmp (symname, "eprol") == 0 | |
13088 | || strcmp (symname, "etext") == 0 | |
13089 | || strcmp (symname, "_gp") == 0 | |
13090 | || strcmp (symname, "edata") == 0 | |
13091 | || strcmp (symname, "_fbss") == 0 | |
13092 | || strcmp (symname, "_fdata") == 0 | |
13093 | || strcmp (symname, "_ftext") == 0 | |
13094 | || strcmp (symname, "end") == 0 | |
13095 | || strcmp (symname, "_gp_disp") == 0)) | |
13096 | change = 1; | |
13097 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
13098 | && (0 | |
13099 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
13100 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
13101 | && (symbol_get_obj (sym)->ecoff_extern_size | |
13102 | <= g_switch_value)) | |
252b5132 RH |
13103 | #endif |
13104 | /* We must defer this decision until after the whole | |
13105 | file has been read, since there might be a .extern | |
13106 | after the first use of this symbol. */ | |
13107 | || (before_relaxing | |
13108 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 13109 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
13110 | #endif |
13111 | && S_GET_VALUE (sym) == 0) | |
13112 | || (S_GET_VALUE (sym) != 0 | |
13113 | && S_GET_VALUE (sym) <= g_switch_value))) | |
13114 | change = 0; | |
13115 | else | |
13116 | { | |
13117 | const char *segname; | |
13118 | ||
13119 | segname = segment_name (S_GET_SEGMENT (sym)); | |
13120 | assert (strcmp (segname, ".lit8") != 0 | |
13121 | && strcmp (segname, ".lit4") != 0); | |
13122 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
13123 | && strcmp (segname, ".sbss") != 0 |
13124 | && strncmp (segname, ".sdata.", 7) != 0 | |
d4dc2f22 TS |
13125 | && strncmp (segname, ".sbss.", 6) != 0 |
13126 | && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0 | |
fba2b7f9 | 13127 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); |
252b5132 RH |
13128 | } |
13129 | return change; | |
13130 | } | |
13131 | else | |
c9914766 | 13132 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
13133 | return 1; |
13134 | } | |
13135 | ||
5919d012 RS |
13136 | |
13137 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
13138 | ||
13139 | static bfd_boolean | |
17a2f251 | 13140 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
13141 | { |
13142 | asection *symsec; | |
5919d012 RS |
13143 | |
13144 | /* Handle the case of a symbol equated to another symbol. */ | |
13145 | while (symbol_equated_reloc_p (sym)) | |
13146 | { | |
13147 | symbolS *n; | |
13148 | ||
5f0fe04b | 13149 | /* It's possible to get a loop here in a badly written program. */ |
5919d012 RS |
13150 | n = symbol_get_value_expression (sym)->X_add_symbol; |
13151 | if (n == sym) | |
13152 | break; | |
13153 | sym = n; | |
13154 | } | |
13155 | ||
df1f3cda DD |
13156 | if (symbol_section_p (sym)) |
13157 | return TRUE; | |
13158 | ||
5919d012 RS |
13159 | symsec = S_GET_SEGMENT (sym); |
13160 | ||
5919d012 RS |
13161 | /* This must duplicate the test in adjust_reloc_syms. */ |
13162 | return (symsec != &bfd_und_section | |
13163 | && symsec != &bfd_abs_section | |
5f0fe04b TS |
13164 | && !bfd_is_com_section (symsec) |
13165 | && !s_is_linkonce (sym, segtype) | |
5919d012 RS |
13166 | #ifdef OBJ_ELF |
13167 | /* A global or weak symbol is treated as external. */ | |
f43abd2b | 13168 | && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym))) |
5919d012 RS |
13169 | #endif |
13170 | ); | |
13171 | } | |
13172 | ||
13173 | ||
252b5132 RH |
13174 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
13175 | extended opcode. SEC is the section the frag is in. */ | |
13176 | ||
13177 | static int | |
17a2f251 | 13178 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
13179 | { |
13180 | int type; | |
3994f87e | 13181 | const struct mips16_immed_operand *op; |
252b5132 RH |
13182 | offsetT val; |
13183 | int mintiny, maxtiny; | |
13184 | segT symsec; | |
98aa84af | 13185 | fragS *sym_frag; |
252b5132 RH |
13186 | |
13187 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
13188 | return 0; | |
13189 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
13190 | return 1; | |
13191 | ||
13192 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
13193 | op = mips16_immed_operands; | |
13194 | while (op->type != type) | |
13195 | { | |
13196 | ++op; | |
13197 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
13198 | } | |
13199 | ||
13200 | if (op->unsp) | |
13201 | { | |
13202 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
13203 | { | |
13204 | mintiny = 1; | |
13205 | maxtiny = 1 << op->nbits; | |
13206 | } | |
13207 | else | |
13208 | { | |
13209 | mintiny = 0; | |
13210 | maxtiny = (1 << op->nbits) - 1; | |
13211 | } | |
13212 | } | |
13213 | else | |
13214 | { | |
13215 | mintiny = - (1 << (op->nbits - 1)); | |
13216 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
13217 | } | |
13218 | ||
98aa84af | 13219 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 13220 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 13221 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
13222 | |
13223 | if (op->pcrel) | |
13224 | { | |
13225 | addressT addr; | |
13226 | ||
13227 | /* We won't have the section when we are called from | |
13228 | mips_relax_frag. However, we will always have been called | |
13229 | from md_estimate_size_before_relax first. If this is a | |
13230 | branch to a different section, we mark it as such. If SEC is | |
13231 | NULL, and the frag is not marked, then it must be a branch to | |
13232 | the same section. */ | |
13233 | if (sec == NULL) | |
13234 | { | |
13235 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
13236 | return 1; | |
13237 | } | |
13238 | else | |
13239 | { | |
98aa84af | 13240 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
13241 | if (symsec != sec) |
13242 | { | |
13243 | fragp->fr_subtype = | |
13244 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
13245 | ||
13246 | /* FIXME: We should support this, and let the linker | |
13247 | catch branches and loads that are out of range. */ | |
13248 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
13249 | _("unsupported PC relative reference to different section")); | |
13250 | ||
13251 | return 1; | |
13252 | } | |
98aa84af AM |
13253 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
13254 | /* Assume non-extended on the first relaxation pass. | |
13255 | The address we have calculated will be bogus if this is | |
13256 | a forward branch to another frag, as the forward frag | |
13257 | will have fr_address == 0. */ | |
13258 | return 0; | |
252b5132 RH |
13259 | } |
13260 | ||
13261 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
13262 | the same section. If the relax_marker of the symbol fragment |
13263 | differs from the relax_marker of this fragment, we have not | |
13264 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
13265 | in STRETCH in order to get a better estimate of the address. |
13266 | This particularly matters because of the shift bits. */ | |
13267 | if (stretch != 0 | |
98aa84af | 13268 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
13269 | { |
13270 | fragS *f; | |
13271 | ||
13272 | /* Adjust stretch for any alignment frag. Note that if have | |
13273 | been expanding the earlier code, the symbol may be | |
13274 | defined in what appears to be an earlier frag. FIXME: | |
13275 | This doesn't handle the fr_subtype field, which specifies | |
13276 | a maximum number of bytes to skip when doing an | |
13277 | alignment. */ | |
98aa84af | 13278 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
13279 | { |
13280 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
13281 | { | |
13282 | if (stretch < 0) | |
13283 | stretch = - ((- stretch) | |
13284 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
13285 | else | |
13286 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
13287 | if (stretch == 0) | |
13288 | break; | |
13289 | } | |
13290 | } | |
13291 | if (f != NULL) | |
13292 | val += stretch; | |
13293 | } | |
13294 | ||
13295 | addr = fragp->fr_address + fragp->fr_fix; | |
13296 | ||
13297 | /* The base address rules are complicated. The base address of | |
13298 | a branch is the following instruction. The base address of a | |
13299 | PC relative load or add is the instruction itself, but if it | |
13300 | is in a delay slot (in which case it can not be extended) use | |
13301 | the address of the instruction whose delay slot it is in. */ | |
13302 | if (type == 'p' || type == 'q') | |
13303 | { | |
13304 | addr += 2; | |
13305 | ||
13306 | /* If we are currently assuming that this frag should be | |
13307 | extended, then, the current address is two bytes | |
bdaaa2e1 | 13308 | higher. */ |
252b5132 RH |
13309 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
13310 | addr += 2; | |
13311 | ||
13312 | /* Ignore the low bit in the target, since it will be set | |
13313 | for a text label. */ | |
13314 | if ((val & 1) != 0) | |
13315 | --val; | |
13316 | } | |
13317 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
13318 | addr -= 4; | |
13319 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
13320 | addr -= 2; | |
13321 | ||
13322 | val -= addr & ~ ((1 << op->shift) - 1); | |
13323 | ||
13324 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
13325 | if (type == 'p' || type == 'q') | |
13326 | val /= 2; | |
13327 | ||
13328 | /* If any of the shifted bits are set, we must use an extended | |
13329 | opcode. If the address depends on the size of this | |
13330 | instruction, this can lead to a loop, so we arrange to always | |
13331 | use an extended opcode. We only check this when we are in | |
13332 | the main relaxation loop, when SEC is NULL. */ | |
13333 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
13334 | { | |
13335 | fragp->fr_subtype = | |
13336 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
13337 | return 1; | |
13338 | } | |
13339 | ||
13340 | /* If we are about to mark a frag as extended because the value | |
13341 | is precisely maxtiny + 1, then there is a chance of an | |
13342 | infinite loop as in the following code: | |
13343 | la $4,foo | |
13344 | .skip 1020 | |
13345 | .align 2 | |
13346 | foo: | |
13347 | In this case when the la is extended, foo is 0x3fc bytes | |
13348 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
13349 | the la must be extended. To avoid this loop, we mark the | |
13350 | frag as extended if it was small, and is about to become | |
13351 | extended with a value of maxtiny + 1. */ | |
13352 | if (val == ((maxtiny + 1) << op->shift) | |
13353 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
13354 | && sec == NULL) | |
13355 | { | |
13356 | fragp->fr_subtype = | |
13357 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
13358 | return 1; | |
13359 | } | |
13360 | } | |
13361 | else if (symsec != absolute_section && sec != NULL) | |
13362 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
13363 | ||
13364 | if ((val & ((1 << op->shift) - 1)) != 0 | |
13365 | || val < (mintiny << op->shift) | |
13366 | || val > (maxtiny << op->shift)) | |
13367 | return 1; | |
13368 | else | |
13369 | return 0; | |
13370 | } | |
13371 | ||
4a6a3df4 AO |
13372 | /* Compute the length of a branch sequence, and adjust the |
13373 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
13374 | worst-case length is computed, with UPDATE being used to indicate | |
13375 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
13376 | branch is to be computed. */ | |
13377 | static int | |
17a2f251 | 13378 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 13379 | { |
b34976b6 | 13380 | bfd_boolean toofar; |
4a6a3df4 AO |
13381 | int length; |
13382 | ||
13383 | if (fragp | |
13384 | && S_IS_DEFINED (fragp->fr_symbol) | |
13385 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
13386 | { | |
13387 | addressT addr; | |
13388 | offsetT val; | |
13389 | ||
13390 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
13391 | ||
13392 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
13393 | ||
13394 | val -= addr; | |
13395 | ||
13396 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
13397 | } | |
13398 | else if (fragp) | |
13399 | /* If the symbol is not defined or it's in a different segment, | |
13400 | assume the user knows what's going on and emit a short | |
13401 | branch. */ | |
b34976b6 | 13402 | toofar = FALSE; |
4a6a3df4 | 13403 | else |
b34976b6 | 13404 | toofar = TRUE; |
4a6a3df4 AO |
13405 | |
13406 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
13407 | fragp->fr_subtype | |
af6ae2ad | 13408 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype), |
4a6a3df4 AO |
13409 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
13410 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
13411 | toofar); | |
13412 | ||
13413 | length = 4; | |
13414 | if (toofar) | |
13415 | { | |
13416 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
13417 | length += 8; | |
13418 | ||
13419 | if (mips_pic != NO_PIC) | |
13420 | { | |
13421 | /* Additional space for PIC loading of target address. */ | |
13422 | length += 8; | |
13423 | if (mips_opts.isa == ISA_MIPS1) | |
13424 | /* Additional space for $at-stabilizing nop. */ | |
13425 | length += 4; | |
13426 | } | |
13427 | ||
13428 | /* If branch is conditional. */ | |
13429 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
13430 | length += 8; | |
13431 | } | |
b34976b6 | 13432 | |
4a6a3df4 AO |
13433 | return length; |
13434 | } | |
13435 | ||
252b5132 RH |
13436 | /* Estimate the size of a frag before relaxing. Unless this is the |
13437 | mips16, we are not really relaxing here, and the final size is | |
13438 | encoded in the subtype information. For the mips16, we have to | |
13439 | decide whether we are using an extended opcode or not. */ | |
13440 | ||
252b5132 | 13441 | int |
17a2f251 | 13442 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 13443 | { |
5919d012 | 13444 | int change; |
252b5132 | 13445 | |
4a6a3df4 AO |
13446 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13447 | { | |
13448 | ||
b34976b6 AM |
13449 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
13450 | ||
4a6a3df4 AO |
13451 | return fragp->fr_var; |
13452 | } | |
13453 | ||
252b5132 | 13454 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
13455 | /* We don't want to modify the EXTENDED bit here; it might get us |
13456 | into infinite loops. We change it only in mips_relax_frag(). */ | |
13457 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 RH |
13458 | |
13459 | if (mips_pic == NO_PIC) | |
5919d012 | 13460 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 13461 | else if (mips_pic == SVR4_PIC) |
5919d012 | 13462 | change = pic_need_relax (fragp->fr_symbol, segtype); |
0a44bf69 RS |
13463 | else if (mips_pic == VXWORKS_PIC) |
13464 | /* For vxworks, GOT16 relocations never have a corresponding LO16. */ | |
13465 | change = 0; | |
252b5132 RH |
13466 | else |
13467 | abort (); | |
13468 | ||
13469 | if (change) | |
13470 | { | |
4d7206a2 | 13471 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 13472 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 13473 | } |
4d7206a2 RS |
13474 | else |
13475 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
13476 | } |
13477 | ||
13478 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 13479 | should be converted into a reloc against a section. */ |
252b5132 RH |
13480 | |
13481 | int | |
17a2f251 | 13482 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 13483 | { |
252b5132 RH |
13484 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
13485 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
13486 | return 0; | |
a161fe53 | 13487 | |
252b5132 RH |
13488 | if (fixp->fx_addsy == NULL) |
13489 | return 1; | |
a161fe53 | 13490 | |
de7e6852 RS |
13491 | /* If symbol SYM is in a mergeable section, relocations of the form |
13492 | SYM + 0 can usually be made section-relative. The mergeable data | |
13493 | is then identified by the section offset rather than by the symbol. | |
13494 | ||
13495 | However, if we're generating REL LO16 relocations, the offset is split | |
13496 | between the LO16 and parterning high part relocation. The linker will | |
13497 | need to recalculate the complete offset in order to correctly identify | |
13498 | the merge data. | |
13499 | ||
13500 | The linker has traditionally not looked for the parterning high part | |
13501 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be | |
13502 | placed anywhere. Rather than break backwards compatibility by changing | |
13503 | this, it seems better not to force the issue, and instead keep the | |
13504 | original symbol. This will work with either linker behavior. */ | |
704803a9 MR |
13505 | if ((fixp->fx_r_type == BFD_RELOC_LO16 |
13506 | || fixp->fx_r_type == BFD_RELOC_MIPS16_LO16 | |
13507 | || reloc_needs_lo_p (fixp->fx_r_type)) | |
de7e6852 RS |
13508 | && HAVE_IN_PLACE_ADDENDS |
13509 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
13510 | return 0; | |
13511 | ||
252b5132 | 13512 | #ifdef OBJ_ELF |
de7e6852 RS |
13513 | /* Don't adjust relocations against mips16 symbols, so that the linker |
13514 | can find them if it needs to set up a stub. */ | |
f43abd2b | 13515 | if (IS_ELF |
252b5132 RH |
13516 | && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 |
13517 | && fixp->fx_subsy == NULL) | |
13518 | return 0; | |
13519 | #endif | |
a161fe53 | 13520 | |
252b5132 RH |
13521 | return 1; |
13522 | } | |
13523 | ||
13524 | /* Translate internal representation of relocation info to BFD target | |
13525 | format. */ | |
13526 | ||
13527 | arelent ** | |
17a2f251 | 13528 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
13529 | { |
13530 | static arelent *retval[4]; | |
13531 | arelent *reloc; | |
13532 | bfd_reloc_code_real_type code; | |
13533 | ||
4b0cff4e TS |
13534 | memset (retval, 0, sizeof(retval)); |
13535 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
13536 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
13537 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
13538 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
13539 | ||
bad36eac DJ |
13540 | if (fixp->fx_pcrel) |
13541 | { | |
13542 | assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2); | |
13543 | ||
13544 | /* At this point, fx_addnumber is "symbol offset - pcrel address". | |
13545 | Relocations want only the symbol offset. */ | |
13546 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
f43abd2b | 13547 | if (!IS_ELF) |
bad36eac DJ |
13548 | { |
13549 | /* A gruesome hack which is a result of the gruesome gas | |
13550 | reloc handling. What's worse, for COFF (as opposed to | |
13551 | ECOFF), we might need yet another copy of reloc->address. | |
13552 | See bfd_install_relocation. */ | |
13553 | reloc->addend += reloc->address; | |
13554 | } | |
13555 | } | |
13556 | else | |
13557 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 13558 | |
438c16b8 TS |
13559 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
13560 | entry to be used in the relocation's section offset. */ | |
13561 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
13562 | { |
13563 | reloc->address = reloc->addend; | |
13564 | reloc->addend = 0; | |
13565 | } | |
13566 | ||
252b5132 | 13567 | code = fixp->fx_r_type; |
252b5132 | 13568 | |
bad36eac | 13569 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
252b5132 RH |
13570 | if (reloc->howto == NULL) |
13571 | { | |
13572 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
13573 | _("Can not represent %s relocation in this object file format"), | |
13574 | bfd_get_reloc_code_name (code)); | |
13575 | retval[0] = NULL; | |
13576 | } | |
13577 | ||
13578 | return retval; | |
13579 | } | |
13580 | ||
13581 | /* Relax a machine dependent frag. This returns the amount by which | |
13582 | the current size of the frag should change. */ | |
13583 | ||
13584 | int | |
17a2f251 | 13585 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 13586 | { |
4a6a3df4 AO |
13587 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13588 | { | |
13589 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
13590 | |
13591 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
13592 | |
13593 | return fragp->fr_var - old_var; | |
13594 | } | |
13595 | ||
252b5132 RH |
13596 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
13597 | return 0; | |
13598 | ||
c4e7957c | 13599 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
13600 | { |
13601 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13602 | return 0; | |
13603 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
13604 | return 2; | |
13605 | } | |
13606 | else | |
13607 | { | |
13608 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13609 | return 0; | |
13610 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
13611 | return -2; | |
13612 | } | |
13613 | ||
13614 | return 0; | |
13615 | } | |
13616 | ||
13617 | /* Convert a machine dependent frag. */ | |
13618 | ||
13619 | void | |
17a2f251 | 13620 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 13621 | { |
4a6a3df4 AO |
13622 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
13623 | { | |
13624 | bfd_byte *buf; | |
13625 | unsigned long insn; | |
13626 | expressionS exp; | |
13627 | fixS *fixp; | |
b34976b6 | 13628 | |
4a6a3df4 AO |
13629 | buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; |
13630 | ||
13631 | if (target_big_endian) | |
13632 | insn = bfd_getb32 (buf); | |
13633 | else | |
13634 | insn = bfd_getl32 (buf); | |
b34976b6 | 13635 | |
4a6a3df4 AO |
13636 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
13637 | { | |
13638 | /* We generate a fixup instead of applying it right now | |
13639 | because, if there are linker relaxations, we're going to | |
13640 | need the relocations. */ | |
13641 | exp.X_op = O_symbol; | |
13642 | exp.X_add_symbol = fragp->fr_symbol; | |
13643 | exp.X_add_number = fragp->fr_offset; | |
13644 | ||
13645 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 13646 | 4, &exp, TRUE, BFD_RELOC_16_PCREL_S2); |
4a6a3df4 AO |
13647 | fixp->fx_file = fragp->fr_file; |
13648 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 13649 | |
2132e3a3 | 13650 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13651 | buf += 4; |
13652 | } | |
13653 | else | |
13654 | { | |
13655 | int i; | |
13656 | ||
13657 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
13658 | _("relaxed out-of-range branch into a jump")); | |
13659 | ||
13660 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
13661 | goto uncond; | |
13662 | ||
13663 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13664 | { | |
13665 | /* Reverse the branch. */ | |
13666 | switch ((insn >> 28) & 0xf) | |
13667 | { | |
13668 | case 4: | |
13669 | /* bc[0-3][tf]l? and bc1any[24][ft] instructions can | |
13670 | have the condition reversed by tweaking a single | |
13671 | bit, and their opcodes all have 0x4???????. */ | |
13672 | assert ((insn & 0xf1000000) == 0x41000000); | |
13673 | insn ^= 0x00010000; | |
13674 | break; | |
13675 | ||
13676 | case 0: | |
13677 | /* bltz 0x04000000 bgez 0x04010000 | |
54f4ddb3 | 13678 | bltzal 0x04100000 bgezal 0x04110000 */ |
4a6a3df4 AO |
13679 | assert ((insn & 0xfc0e0000) == 0x04000000); |
13680 | insn ^= 0x00010000; | |
13681 | break; | |
b34976b6 | 13682 | |
4a6a3df4 AO |
13683 | case 1: |
13684 | /* beq 0x10000000 bne 0x14000000 | |
54f4ddb3 | 13685 | blez 0x18000000 bgtz 0x1c000000 */ |
4a6a3df4 AO |
13686 | insn ^= 0x04000000; |
13687 | break; | |
13688 | ||
13689 | default: | |
13690 | abort (); | |
13691 | } | |
13692 | } | |
13693 | ||
13694 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
13695 | { | |
13696 | /* Clear the and-link bit. */ | |
13697 | assert ((insn & 0xfc1c0000) == 0x04100000); | |
13698 | ||
54f4ddb3 TS |
13699 | /* bltzal 0x04100000 bgezal 0x04110000 |
13700 | bltzall 0x04120000 bgezall 0x04130000 */ | |
4a6a3df4 AO |
13701 | insn &= ~0x00100000; |
13702 | } | |
13703 | ||
13704 | /* Branch over the branch (if the branch was likely) or the | |
13705 | full jump (not likely case). Compute the offset from the | |
13706 | current instruction to branch to. */ | |
13707 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13708 | i = 16; | |
13709 | else | |
13710 | { | |
13711 | /* How many bytes in instructions we've already emitted? */ | |
13712 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
13713 | /* How many bytes in instructions from here to the end? */ | |
13714 | i = fragp->fr_var - i; | |
13715 | } | |
13716 | /* Convert to instruction count. */ | |
13717 | i >>= 2; | |
13718 | /* Branch counts from the next instruction. */ | |
b34976b6 | 13719 | i--; |
4a6a3df4 AO |
13720 | insn |= i; |
13721 | /* Branch over the jump. */ | |
2132e3a3 | 13722 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13723 | buf += 4; |
13724 | ||
54f4ddb3 | 13725 | /* nop */ |
2132e3a3 | 13726 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
13727 | buf += 4; |
13728 | ||
13729 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
13730 | { | |
13731 | /* beql $0, $0, 2f */ | |
13732 | insn = 0x50000000; | |
13733 | /* Compute the PC offset from the current instruction to | |
13734 | the end of the variable frag. */ | |
13735 | /* How many bytes in instructions we've already emitted? */ | |
13736 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
13737 | /* How many bytes in instructions from here to the end? */ | |
13738 | i = fragp->fr_var - i; | |
13739 | /* Convert to instruction count. */ | |
13740 | i >>= 2; | |
13741 | /* Don't decrement i, because we want to branch over the | |
13742 | delay slot. */ | |
13743 | ||
13744 | insn |= i; | |
2132e3a3 | 13745 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13746 | buf += 4; |
13747 | ||
2132e3a3 | 13748 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
13749 | buf += 4; |
13750 | } | |
13751 | ||
13752 | uncond: | |
13753 | if (mips_pic == NO_PIC) | |
13754 | { | |
13755 | /* j or jal. */ | |
13756 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
13757 | ? 0x0c000000 : 0x08000000); | |
13758 | exp.X_op = O_symbol; | |
13759 | exp.X_add_symbol = fragp->fr_symbol; | |
13760 | exp.X_add_number = fragp->fr_offset; | |
13761 | ||
13762 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 13763 | 4, &exp, FALSE, BFD_RELOC_MIPS_JMP); |
4a6a3df4 AO |
13764 | fixp->fx_file = fragp->fr_file; |
13765 | fixp->fx_line = fragp->fr_line; | |
13766 | ||
2132e3a3 | 13767 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13768 | buf += 4; |
13769 | } | |
13770 | else | |
13771 | { | |
13772 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ | |
13773 | insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000; | |
13774 | exp.X_op = O_symbol; | |
13775 | exp.X_add_symbol = fragp->fr_symbol; | |
13776 | exp.X_add_number = fragp->fr_offset; | |
13777 | ||
13778 | if (fragp->fr_offset) | |
13779 | { | |
13780 | exp.X_add_symbol = make_expr_symbol (&exp); | |
13781 | exp.X_add_number = 0; | |
13782 | } | |
13783 | ||
13784 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 13785 | 4, &exp, FALSE, BFD_RELOC_MIPS_GOT16); |
4a6a3df4 AO |
13786 | fixp->fx_file = fragp->fr_file; |
13787 | fixp->fx_line = fragp->fr_line; | |
13788 | ||
2132e3a3 | 13789 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 | 13790 | buf += 4; |
b34976b6 | 13791 | |
4a6a3df4 AO |
13792 | if (mips_opts.isa == ISA_MIPS1) |
13793 | { | |
13794 | /* nop */ | |
2132e3a3 | 13795 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
13796 | buf += 4; |
13797 | } | |
13798 | ||
13799 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
13800 | insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000; | |
13801 | ||
13802 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
3994f87e | 13803 | 4, &exp, FALSE, BFD_RELOC_LO16); |
4a6a3df4 AO |
13804 | fixp->fx_file = fragp->fr_file; |
13805 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 13806 | |
2132e3a3 | 13807 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13808 | buf += 4; |
13809 | ||
13810 | /* j(al)r $at. */ | |
13811 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
13812 | insn = 0x0020f809; | |
13813 | else | |
13814 | insn = 0x00200008; | |
13815 | ||
2132e3a3 | 13816 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
13817 | buf += 4; |
13818 | } | |
13819 | } | |
13820 | ||
13821 | assert (buf == (bfd_byte *)fragp->fr_literal | |
13822 | + fragp->fr_fix + fragp->fr_var); | |
13823 | ||
13824 | fragp->fr_fix += fragp->fr_var; | |
13825 | ||
13826 | return; | |
13827 | } | |
13828 | ||
252b5132 RH |
13829 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
13830 | { | |
13831 | int type; | |
3994f87e | 13832 | const struct mips16_immed_operand *op; |
b34976b6 | 13833 | bfd_boolean small, ext; |
252b5132 RH |
13834 | offsetT val; |
13835 | bfd_byte *buf; | |
13836 | unsigned long insn; | |
b34976b6 | 13837 | bfd_boolean use_extend; |
252b5132 RH |
13838 | unsigned short extend; |
13839 | ||
13840 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
13841 | op = mips16_immed_operands; | |
13842 | while (op->type != type) | |
13843 | ++op; | |
13844 | ||
13845 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
13846 | { | |
b34976b6 AM |
13847 | small = FALSE; |
13848 | ext = TRUE; | |
252b5132 RH |
13849 | } |
13850 | else | |
13851 | { | |
b34976b6 AM |
13852 | small = TRUE; |
13853 | ext = FALSE; | |
252b5132 RH |
13854 | } |
13855 | ||
6386f3a7 | 13856 | resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
13857 | val = S_GET_VALUE (fragp->fr_symbol); |
13858 | if (op->pcrel) | |
13859 | { | |
13860 | addressT addr; | |
13861 | ||
13862 | addr = fragp->fr_address + fragp->fr_fix; | |
13863 | ||
13864 | /* The rules for the base address of a PC relative reloc are | |
13865 | complicated; see mips16_extended_frag. */ | |
13866 | if (type == 'p' || type == 'q') | |
13867 | { | |
13868 | addr += 2; | |
13869 | if (ext) | |
13870 | addr += 2; | |
13871 | /* Ignore the low bit in the target, since it will be | |
13872 | set for a text label. */ | |
13873 | if ((val & 1) != 0) | |
13874 | --val; | |
13875 | } | |
13876 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
13877 | addr -= 4; | |
13878 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
13879 | addr -= 2; | |
13880 | ||
13881 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
13882 | val -= addr; | |
13883 | ||
13884 | /* Make sure the section winds up with the alignment we have | |
13885 | assumed. */ | |
13886 | if (op->shift > 0) | |
13887 | record_alignment (asec, op->shift); | |
13888 | } | |
13889 | ||
13890 | if (ext | |
13891 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
13892 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
13893 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
13894 | _("extended instruction in delay slot")); | |
13895 | ||
13896 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
13897 | ||
13898 | if (target_big_endian) | |
13899 | insn = bfd_getb16 (buf); | |
13900 | else | |
13901 | insn = bfd_getl16 (buf); | |
13902 | ||
13903 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
13904 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
13905 | small, ext, &insn, &use_extend, &extend); | |
13906 | ||
13907 | if (use_extend) | |
13908 | { | |
2132e3a3 | 13909 | md_number_to_chars ((char *) buf, 0xf000 | extend, 2); |
252b5132 RH |
13910 | fragp->fr_fix += 2; |
13911 | buf += 2; | |
13912 | } | |
13913 | ||
2132e3a3 | 13914 | md_number_to_chars ((char *) buf, insn, 2); |
252b5132 RH |
13915 | fragp->fr_fix += 2; |
13916 | buf += 2; | |
13917 | } | |
13918 | else | |
13919 | { | |
4d7206a2 RS |
13920 | int first, second; |
13921 | fixS *fixp; | |
252b5132 | 13922 | |
4d7206a2 RS |
13923 | first = RELAX_FIRST (fragp->fr_subtype); |
13924 | second = RELAX_SECOND (fragp->fr_subtype); | |
13925 | fixp = (fixS *) fragp->fr_opcode; | |
252b5132 | 13926 | |
584892a6 RS |
13927 | /* Possibly emit a warning if we've chosen the longer option. */ |
13928 | if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0) | |
13929 | == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0)) | |
13930 | { | |
13931 | const char *msg = macro_warning (fragp->fr_subtype); | |
13932 | if (msg != 0) | |
13933 | as_warn_where (fragp->fr_file, fragp->fr_line, msg); | |
13934 | } | |
13935 | ||
4d7206a2 RS |
13936 | /* Go through all the fixups for the first sequence. Disable them |
13937 | (by marking them as done) if we're going to use the second | |
13938 | sequence instead. */ | |
13939 | while (fixp | |
13940 | && fixp->fx_frag == fragp | |
13941 | && fixp->fx_where < fragp->fr_fix - second) | |
13942 | { | |
13943 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13944 | fixp->fx_done = 1; | |
13945 | fixp = fixp->fx_next; | |
13946 | } | |
252b5132 | 13947 | |
4d7206a2 RS |
13948 | /* Go through the fixups for the second sequence. Disable them if |
13949 | we're going to use the first sequence, otherwise adjust their | |
13950 | addresses to account for the relaxation. */ | |
13951 | while (fixp && fixp->fx_frag == fragp) | |
13952 | { | |
13953 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13954 | fixp->fx_where -= first; | |
13955 | else | |
13956 | fixp->fx_done = 1; | |
13957 | fixp = fixp->fx_next; | |
13958 | } | |
13959 | ||
13960 | /* Now modify the frag contents. */ | |
13961 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13962 | { | |
13963 | char *start; | |
13964 | ||
13965 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
13966 | memmove (start, start + first, second); | |
13967 | fragp->fr_fix -= first; | |
13968 | } | |
13969 | else | |
13970 | fragp->fr_fix -= second; | |
252b5132 RH |
13971 | } |
13972 | } | |
13973 | ||
13974 | #ifdef OBJ_ELF | |
13975 | ||
13976 | /* This function is called after the relocs have been generated. | |
13977 | We've been storing mips16 text labels as odd. Here we convert them | |
13978 | back to even for the convenience of the debugger. */ | |
13979 | ||
13980 | void | |
17a2f251 | 13981 | mips_frob_file_after_relocs (void) |
252b5132 RH |
13982 | { |
13983 | asymbol **syms; | |
13984 | unsigned int count, i; | |
13985 | ||
f43abd2b | 13986 | if (!IS_ELF) |
252b5132 RH |
13987 | return; |
13988 | ||
13989 | syms = bfd_get_outsymbols (stdoutput); | |
13990 | count = bfd_get_symcount (stdoutput); | |
13991 | for (i = 0; i < count; i++, syms++) | |
13992 | { | |
13993 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
13994 | && ((*syms)->value & 1) != 0) | |
13995 | { | |
13996 | (*syms)->value &= ~1; | |
13997 | /* If the symbol has an odd size, it was probably computed | |
13998 | incorrectly, so adjust that as well. */ | |
13999 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
14000 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
14001 | } | |
14002 | } | |
14003 | } | |
14004 | ||
14005 | #endif | |
14006 | ||
14007 | /* This function is called whenever a label is defined. It is used | |
14008 | when handling branch delays; if a branch has a label, we assume we | |
14009 | can not move it. */ | |
14010 | ||
14011 | void | |
17a2f251 | 14012 | mips_define_label (symbolS *sym) |
252b5132 | 14013 | { |
a8dbcb85 | 14014 | segment_info_type *si = seg_info (now_seg); |
252b5132 RH |
14015 | struct insn_label_list *l; |
14016 | ||
14017 | if (free_insn_labels == NULL) | |
14018 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
14019 | else | |
14020 | { | |
14021 | l = free_insn_labels; | |
14022 | free_insn_labels = l->next; | |
14023 | } | |
14024 | ||
14025 | l->label = sym; | |
a8dbcb85 TS |
14026 | l->next = si->label_list; |
14027 | si->label_list = l; | |
07a53e5c RH |
14028 | |
14029 | #ifdef OBJ_ELF | |
14030 | dwarf2_emit_label (sym); | |
14031 | #endif | |
252b5132 RH |
14032 | } |
14033 | \f | |
14034 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
14035 | ||
14036 | /* Some special processing for a MIPS ELF file. */ | |
14037 | ||
14038 | void | |
17a2f251 | 14039 | mips_elf_final_processing (void) |
252b5132 RH |
14040 | { |
14041 | /* Write out the register information. */ | |
316f5878 | 14042 | if (mips_abi != N64_ABI) |
252b5132 RH |
14043 | { |
14044 | Elf32_RegInfo s; | |
14045 | ||
14046 | s.ri_gprmask = mips_gprmask; | |
14047 | s.ri_cprmask[0] = mips_cprmask[0]; | |
14048 | s.ri_cprmask[1] = mips_cprmask[1]; | |
14049 | s.ri_cprmask[2] = mips_cprmask[2]; | |
14050 | s.ri_cprmask[3] = mips_cprmask[3]; | |
14051 | /* The gp_value field is set by the MIPS ELF backend. */ | |
14052 | ||
14053 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
14054 | ((Elf32_External_RegInfo *) | |
14055 | mips_regmask_frag)); | |
14056 | } | |
14057 | else | |
14058 | { | |
14059 | Elf64_Internal_RegInfo s; | |
14060 | ||
14061 | s.ri_gprmask = mips_gprmask; | |
14062 | s.ri_pad = 0; | |
14063 | s.ri_cprmask[0] = mips_cprmask[0]; | |
14064 | s.ri_cprmask[1] = mips_cprmask[1]; | |
14065 | s.ri_cprmask[2] = mips_cprmask[2]; | |
14066 | s.ri_cprmask[3] = mips_cprmask[3]; | |
14067 | /* The gp_value field is set by the MIPS ELF backend. */ | |
14068 | ||
14069 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
14070 | ((Elf64_External_RegInfo *) | |
14071 | mips_regmask_frag)); | |
14072 | } | |
14073 | ||
14074 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
14075 | sort of BFD interface for this. */ | |
14076 | if (mips_any_noreorder) | |
14077 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
14078 | if (mips_pic != NO_PIC) | |
143d77c5 | 14079 | { |
252b5132 | 14080 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
14081 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
14082 | } | |
14083 | if (mips_abicalls) | |
14084 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 14085 | |
98d3f06f | 14086 | /* Set MIPS ELF flags for ASEs. */ |
74cd071d CF |
14087 | /* We may need to define a new flag for DSP ASE, and set this flag when |
14088 | file_ase_dsp is true. */ | |
ef2e4d86 CF |
14089 | /* We may need to define a new flag for MT ASE, and set this flag when |
14090 | file_ase_mt is true. */ | |
a4672219 TS |
14091 | if (file_ase_mips16) |
14092 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
1f25f5d3 CD |
14093 | #if 0 /* XXX FIXME */ |
14094 | if (file_ase_mips3d) | |
14095 | elf_elfheader (stdoutput)->e_flags |= ???; | |
14096 | #endif | |
deec1734 CD |
14097 | if (file_ase_mdmx) |
14098 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; | |
1f25f5d3 | 14099 | |
bdaaa2e1 | 14100 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 14101 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 14102 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 14103 | else if (mips_abi == O64_ABI) |
252b5132 | 14104 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 14105 | else if (mips_abi == EABI_ABI) |
252b5132 | 14106 | { |
316f5878 | 14107 | if (!file_mips_gp32) |
252b5132 RH |
14108 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
14109 | else | |
14110 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
14111 | } | |
316f5878 | 14112 | else if (mips_abi == N32_ABI) |
be00bddd TS |
14113 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
14114 | ||
c9914766 | 14115 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
14116 | |
14117 | if (mips_32bitmode) | |
14118 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
ad3fea08 TS |
14119 | |
14120 | #if 0 /* XXX FIXME */ | |
14121 | /* 32 bit code with 64 bit FP registers. */ | |
14122 | if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
14123 | elf_elfheader (stdoutput)->e_flags |= ???; | |
14124 | #endif | |
252b5132 RH |
14125 | } |
14126 | ||
14127 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
14128 | \f | |
beae10d5 | 14129 | typedef struct proc { |
9b2f1d35 EC |
14130 | symbolS *func_sym; |
14131 | symbolS *func_end_sym; | |
beae10d5 KH |
14132 | unsigned long reg_mask; |
14133 | unsigned long reg_offset; | |
14134 | unsigned long fpreg_mask; | |
14135 | unsigned long fpreg_offset; | |
14136 | unsigned long frame_offset; | |
14137 | unsigned long frame_reg; | |
14138 | unsigned long pc_reg; | |
14139 | } procS; | |
252b5132 RH |
14140 | |
14141 | static procS cur_proc; | |
14142 | static procS *cur_proc_ptr; | |
14143 | static int numprocs; | |
14144 | ||
0a9ef439 | 14145 | /* Fill in an rs_align_code fragment. */ |
a19d8eb0 | 14146 | |
0a9ef439 | 14147 | void |
17a2f251 | 14148 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 14149 | { |
0a9ef439 RH |
14150 | if (fragp->fr_type != rs_align_code) |
14151 | return; | |
14152 | ||
14153 | if (mips_opts.mips16) | |
a19d8eb0 CP |
14154 | { |
14155 | static const unsigned char be_nop[] = { 0x65, 0x00 }; | |
14156 | static const unsigned char le_nop[] = { 0x00, 0x65 }; | |
14157 | ||
0a9ef439 RH |
14158 | int bytes; |
14159 | char *p; | |
a19d8eb0 | 14160 | |
0a9ef439 RH |
14161 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
14162 | p = fragp->fr_literal + fragp->fr_fix; | |
14163 | ||
14164 | if (bytes & 1) | |
14165 | { | |
14166 | *p++ = 0; | |
f9419b05 | 14167 | fragp->fr_fix++; |
0a9ef439 RH |
14168 | } |
14169 | ||
14170 | memcpy (p, (target_big_endian ? be_nop : le_nop), 2); | |
14171 | fragp->fr_var = 2; | |
a19d8eb0 CP |
14172 | } |
14173 | ||
0a9ef439 | 14174 | /* For mips32, a nop is a zero, which we trivially get by doing nothing. */ |
a19d8eb0 CP |
14175 | } |
14176 | ||
252b5132 | 14177 | static void |
17a2f251 | 14178 | md_obj_begin (void) |
252b5132 RH |
14179 | { |
14180 | } | |
14181 | ||
14182 | static void | |
17a2f251 | 14183 | md_obj_end (void) |
252b5132 | 14184 | { |
54f4ddb3 | 14185 | /* Check for premature end, nesting errors, etc. */ |
252b5132 | 14186 | if (cur_proc_ptr) |
9a41af64 | 14187 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
14188 | } |
14189 | ||
14190 | static long | |
17a2f251 | 14191 | get_number (void) |
252b5132 RH |
14192 | { |
14193 | int negative = 0; | |
14194 | long val = 0; | |
14195 | ||
14196 | if (*input_line_pointer == '-') | |
14197 | { | |
14198 | ++input_line_pointer; | |
14199 | negative = 1; | |
14200 | } | |
3882b010 | 14201 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 14202 | as_bad (_("expected simple number")); |
252b5132 RH |
14203 | if (input_line_pointer[0] == '0') |
14204 | { | |
14205 | if (input_line_pointer[1] == 'x') | |
14206 | { | |
14207 | input_line_pointer += 2; | |
3882b010 | 14208 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
14209 | { |
14210 | val <<= 4; | |
14211 | val |= hex_value (*input_line_pointer++); | |
14212 | } | |
14213 | return negative ? -val : val; | |
14214 | } | |
14215 | else | |
14216 | { | |
14217 | ++input_line_pointer; | |
3882b010 | 14218 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
14219 | { |
14220 | val <<= 3; | |
14221 | val |= *input_line_pointer++ - '0'; | |
14222 | } | |
14223 | return negative ? -val : val; | |
14224 | } | |
14225 | } | |
3882b010 | 14226 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
14227 | { |
14228 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
14229 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 14230 | as_warn (_("invalid number")); |
252b5132 RH |
14231 | return -1; |
14232 | } | |
3882b010 | 14233 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
14234 | { |
14235 | val *= 10; | |
14236 | val += *input_line_pointer++ - '0'; | |
14237 | } | |
14238 | return negative ? -val : val; | |
14239 | } | |
14240 | ||
14241 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
14242 | is an initial number which is the ECOFF file index. In the non-ECOFF |
14243 | case .file implies DWARF-2. */ | |
14244 | ||
14245 | static void | |
17a2f251 | 14246 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 14247 | { |
ecb4347a DJ |
14248 | static int first_file_directive = 0; |
14249 | ||
c5dd6aab DJ |
14250 | if (ECOFF_DEBUGGING) |
14251 | { | |
14252 | get_number (); | |
14253 | s_app_file (0); | |
14254 | } | |
14255 | else | |
ecb4347a DJ |
14256 | { |
14257 | char *filename; | |
14258 | ||
14259 | filename = dwarf2_directive_file (0); | |
14260 | ||
14261 | /* Versions of GCC up to 3.1 start files with a ".file" | |
14262 | directive even for stabs output. Make sure that this | |
14263 | ".file" is handled. Note that you need a version of GCC | |
14264 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
14265 | if (filename != NULL && ! first_file_directive) | |
14266 | { | |
14267 | (void) new_logical_line (filename, -1); | |
c04f5787 | 14268 | s_app_file_string (filename, 0); |
ecb4347a DJ |
14269 | } |
14270 | first_file_directive = 1; | |
14271 | } | |
c5dd6aab DJ |
14272 | } |
14273 | ||
14274 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
14275 | |
14276 | static void | |
17a2f251 | 14277 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 14278 | { |
c5dd6aab DJ |
14279 | if (!ECOFF_DEBUGGING) |
14280 | dwarf2_directive_loc (0); | |
252b5132 RH |
14281 | } |
14282 | ||
252b5132 RH |
14283 | /* The .end directive. */ |
14284 | ||
14285 | static void | |
17a2f251 | 14286 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
14287 | { |
14288 | symbolS *p; | |
252b5132 | 14289 | |
7a621144 DJ |
14290 | /* Following functions need their own .frame and .cprestore directives. */ |
14291 | mips_frame_reg_valid = 0; | |
14292 | mips_cprestore_valid = 0; | |
14293 | ||
252b5132 RH |
14294 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
14295 | { | |
14296 | p = get_symbol (); | |
14297 | demand_empty_rest_of_line (); | |
14298 | } | |
14299 | else | |
14300 | p = NULL; | |
14301 | ||
14949570 | 14302 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
14303 | as_warn (_(".end not in text section")); |
14304 | ||
14305 | if (!cur_proc_ptr) | |
14306 | { | |
14307 | as_warn (_(".end directive without a preceding .ent directive.")); | |
14308 | demand_empty_rest_of_line (); | |
14309 | return; | |
14310 | } | |
14311 | ||
14312 | if (p != NULL) | |
14313 | { | |
14314 | assert (S_GET_NAME (p)); | |
9b2f1d35 | 14315 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
252b5132 | 14316 | as_warn (_(".end symbol does not match .ent symbol.")); |
ecb4347a DJ |
14317 | |
14318 | if (debug_type == DEBUG_STABS) | |
14319 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
14320 | S_GET_NAME (p)); | |
252b5132 RH |
14321 | } |
14322 | else | |
14323 | as_warn (_(".end directive missing or unknown symbol")); | |
14324 | ||
2132e3a3 | 14325 | #ifdef OBJ_ELF |
9b2f1d35 EC |
14326 | /* Create an expression to calculate the size of the function. */ |
14327 | if (p && cur_proc_ptr) | |
14328 | { | |
14329 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
14330 | expressionS *exp = xmalloc (sizeof (expressionS)); | |
14331 | ||
14332 | obj->size = exp; | |
14333 | exp->X_op = O_subtract; | |
14334 | exp->X_add_symbol = symbol_temp_new_now (); | |
14335 | exp->X_op_symbol = p; | |
14336 | exp->X_add_number = 0; | |
14337 | ||
14338 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
14339 | } | |
14340 | ||
ecb4347a | 14341 | /* Generate a .pdr section. */ |
f43abd2b | 14342 | if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr) |
ecb4347a DJ |
14343 | { |
14344 | segT saved_seg = now_seg; | |
14345 | subsegT saved_subseg = now_subseg; | |
14346 | valueT dot; | |
14347 | expressionS exp; | |
14348 | char *fragp; | |
252b5132 | 14349 | |
ecb4347a | 14350 | dot = frag_now_fix (); |
252b5132 RH |
14351 | |
14352 | #ifdef md_flush_pending_output | |
ecb4347a | 14353 | md_flush_pending_output (); |
252b5132 RH |
14354 | #endif |
14355 | ||
ecb4347a DJ |
14356 | assert (pdr_seg); |
14357 | subseg_set (pdr_seg, 0); | |
252b5132 | 14358 | |
ecb4347a DJ |
14359 | /* Write the symbol. */ |
14360 | exp.X_op = O_symbol; | |
14361 | exp.X_add_symbol = p; | |
14362 | exp.X_add_number = 0; | |
14363 | emit_expr (&exp, 4); | |
252b5132 | 14364 | |
ecb4347a | 14365 | fragp = frag_more (7 * 4); |
252b5132 | 14366 | |
17a2f251 TS |
14367 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
14368 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
14369 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
14370 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
14371 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
14372 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
14373 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 14374 | |
ecb4347a DJ |
14375 | subseg_set (saved_seg, saved_subseg); |
14376 | } | |
14377 | #endif /* OBJ_ELF */ | |
252b5132 RH |
14378 | |
14379 | cur_proc_ptr = NULL; | |
14380 | } | |
14381 | ||
14382 | /* The .aent and .ent directives. */ | |
14383 | ||
14384 | static void | |
17a2f251 | 14385 | s_mips_ent (int aent) |
252b5132 | 14386 | { |
252b5132 | 14387 | symbolS *symbolP; |
252b5132 RH |
14388 | |
14389 | symbolP = get_symbol (); | |
14390 | if (*input_line_pointer == ',') | |
f9419b05 | 14391 | ++input_line_pointer; |
252b5132 | 14392 | SKIP_WHITESPACE (); |
3882b010 | 14393 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 14394 | || *input_line_pointer == '-') |
874e8986 | 14395 | get_number (); |
252b5132 | 14396 | |
14949570 | 14397 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
14398 | as_warn (_(".ent or .aent not in text section.")); |
14399 | ||
14400 | if (!aent && cur_proc_ptr) | |
9a41af64 | 14401 | as_warn (_("missing .end")); |
252b5132 RH |
14402 | |
14403 | if (!aent) | |
14404 | { | |
7a621144 DJ |
14405 | /* This function needs its own .frame and .cprestore directives. */ |
14406 | mips_frame_reg_valid = 0; | |
14407 | mips_cprestore_valid = 0; | |
14408 | ||
252b5132 RH |
14409 | cur_proc_ptr = &cur_proc; |
14410 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
14411 | ||
9b2f1d35 | 14412 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 14413 | |
49309057 | 14414 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
252b5132 | 14415 | |
f9419b05 | 14416 | ++numprocs; |
ecb4347a DJ |
14417 | |
14418 | if (debug_type == DEBUG_STABS) | |
14419 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
14420 | S_GET_NAME (symbolP)); | |
252b5132 RH |
14421 | } |
14422 | ||
14423 | demand_empty_rest_of_line (); | |
14424 | } | |
14425 | ||
14426 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 14427 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 14428 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 14429 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
14430 | symbol table (in the mdebug section). */ |
14431 | ||
14432 | static void | |
17a2f251 | 14433 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 14434 | { |
ecb4347a | 14435 | #ifdef OBJ_ELF |
f43abd2b | 14436 | if (IS_ELF && !ECOFF_DEBUGGING) |
ecb4347a DJ |
14437 | { |
14438 | long val; | |
252b5132 | 14439 | |
ecb4347a DJ |
14440 | if (cur_proc_ptr == (procS *) NULL) |
14441 | { | |
14442 | as_warn (_(".frame outside of .ent")); | |
14443 | demand_empty_rest_of_line (); | |
14444 | return; | |
14445 | } | |
252b5132 | 14446 | |
ecb4347a DJ |
14447 | cur_proc_ptr->frame_reg = tc_get_register (1); |
14448 | ||
14449 | SKIP_WHITESPACE (); | |
14450 | if (*input_line_pointer++ != ',' | |
14451 | || get_absolute_expression_and_terminator (&val) != ',') | |
14452 | { | |
14453 | as_warn (_("Bad .frame directive")); | |
14454 | --input_line_pointer; | |
14455 | demand_empty_rest_of_line (); | |
14456 | return; | |
14457 | } | |
252b5132 | 14458 | |
ecb4347a DJ |
14459 | cur_proc_ptr->frame_offset = val; |
14460 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 14461 | |
252b5132 | 14462 | demand_empty_rest_of_line (); |
252b5132 | 14463 | } |
ecb4347a DJ |
14464 | else |
14465 | #endif /* OBJ_ELF */ | |
14466 | s_ignore (ignore); | |
252b5132 RH |
14467 | } |
14468 | ||
bdaaa2e1 KH |
14469 | /* The .fmask and .mask directives. If the mdebug section is present |
14470 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 14471 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 14472 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
14473 | make reference to the ecoff symbol table (in the mdebug section). */ |
14474 | ||
14475 | static void | |
17a2f251 | 14476 | s_mips_mask (int reg_type) |
252b5132 | 14477 | { |
ecb4347a | 14478 | #ifdef OBJ_ELF |
f43abd2b | 14479 | if (IS_ELF && !ECOFF_DEBUGGING) |
252b5132 | 14480 | { |
ecb4347a | 14481 | long mask, off; |
252b5132 | 14482 | |
ecb4347a DJ |
14483 | if (cur_proc_ptr == (procS *) NULL) |
14484 | { | |
14485 | as_warn (_(".mask/.fmask outside of .ent")); | |
14486 | demand_empty_rest_of_line (); | |
14487 | return; | |
14488 | } | |
252b5132 | 14489 | |
ecb4347a DJ |
14490 | if (get_absolute_expression_and_terminator (&mask) != ',') |
14491 | { | |
14492 | as_warn (_("Bad .mask/.fmask directive")); | |
14493 | --input_line_pointer; | |
14494 | demand_empty_rest_of_line (); | |
14495 | return; | |
14496 | } | |
252b5132 | 14497 | |
ecb4347a DJ |
14498 | off = get_absolute_expression (); |
14499 | ||
14500 | if (reg_type == 'F') | |
14501 | { | |
14502 | cur_proc_ptr->fpreg_mask = mask; | |
14503 | cur_proc_ptr->fpreg_offset = off; | |
14504 | } | |
14505 | else | |
14506 | { | |
14507 | cur_proc_ptr->reg_mask = mask; | |
14508 | cur_proc_ptr->reg_offset = off; | |
14509 | } | |
14510 | ||
14511 | demand_empty_rest_of_line (); | |
252b5132 RH |
14512 | } |
14513 | else | |
ecb4347a DJ |
14514 | #endif /* OBJ_ELF */ |
14515 | s_ignore (reg_type); | |
252b5132 RH |
14516 | } |
14517 | ||
316f5878 RS |
14518 | /* A table describing all the processors gas knows about. Names are |
14519 | matched in the order listed. | |
e7af610e | 14520 | |
316f5878 RS |
14521 | To ease comparison, please keep this table in the same order as |
14522 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
14523 | static const struct mips_cpu_info mips_cpu_info_table[] = |
14524 | { | |
316f5878 | 14525 | /* Entries for generic ISAs */ |
ad3fea08 TS |
14526 | { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 }, |
14527 | { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 }, | |
14528 | { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 }, | |
14529 | { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 }, | |
14530 | { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 }, | |
14531 | { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 }, | |
14532 | { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14533 | { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 }, | |
14534 | { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 }, | |
316f5878 RS |
14535 | |
14536 | /* MIPS I */ | |
ad3fea08 TS |
14537 | { "r3000", 0, ISA_MIPS1, CPU_R3000 }, |
14538 | { "r2000", 0, ISA_MIPS1, CPU_R3000 }, | |
14539 | { "r3900", 0, ISA_MIPS1, CPU_R3900 }, | |
316f5878 RS |
14540 | |
14541 | /* MIPS II */ | |
ad3fea08 | 14542 | { "r6000", 0, ISA_MIPS2, CPU_R6000 }, |
316f5878 RS |
14543 | |
14544 | /* MIPS III */ | |
ad3fea08 TS |
14545 | { "r4000", 0, ISA_MIPS3, CPU_R4000 }, |
14546 | { "r4010", 0, ISA_MIPS2, CPU_R4010 }, | |
14547 | { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, | |
14548 | { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, | |
14549 | { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, | |
14550 | { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, | |
14551 | { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, | |
14552 | { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, | |
14553 | { "r4400", 0, ISA_MIPS3, CPU_R4400 }, | |
14554 | { "r4600", 0, ISA_MIPS3, CPU_R4600 }, | |
14555 | { "orion", 0, ISA_MIPS3, CPU_R4600 }, | |
14556 | { "r4650", 0, ISA_MIPS3, CPU_R4650 }, | |
316f5878 RS |
14557 | |
14558 | /* MIPS IV */ | |
ad3fea08 TS |
14559 | { "r8000", 0, ISA_MIPS4, CPU_R8000 }, |
14560 | { "r10000", 0, ISA_MIPS4, CPU_R10000 }, | |
14561 | { "r12000", 0, ISA_MIPS4, CPU_R12000 }, | |
14562 | { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, | |
14563 | { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, | |
14564 | { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, | |
14565 | { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, | |
14566 | { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, | |
14567 | { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, | |
14568 | { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, | |
14569 | { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, | |
14570 | { "rm7000", 0, ISA_MIPS4, CPU_RM7000 }, | |
14571 | { "rm9000", 0, ISA_MIPS4, CPU_RM9000 }, | |
316f5878 RS |
14572 | |
14573 | /* MIPS 32 */ | |
ad3fea08 TS |
14574 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32 }, |
14575 | { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, | |
14576 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, | |
14577 | { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 }, | |
14578 | ||
14579 | /* MIPS 32 Release 2 */ | |
14580 | { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14581 | { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14582 | { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14583 | { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14584 | { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14585 | { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ad3fea08 TS |
14586 | { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
14587 | { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14588 | { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14589 | /* 24ke is a 24k with DSP ASE, other ASEs are optional. */ | |
ad3fea08 TS |
14590 | { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
14591 | { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
65263ce3 | 14592 | { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
a360e743 TS |
14593 | /* 34k is a 24k with DSP and MT ASE, other ASEs are optional. */ |
14594 | { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
14595 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14596 | { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
14597 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
14598 | { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, | |
14599 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
32b26a03 | 14600 | |
316f5878 | 14601 | /* MIPS 64 */ |
ad3fea08 TS |
14602 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, |
14603 | { "5kf", 0, ISA_MIPS64, CPU_MIPS64 }, | |
14604 | { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
7764b395 | 14605 | { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, |
ad3fea08 TS |
14606 | |
14607 | /* MIPS 64 Release 2 */ | |
e7af610e | 14608 | |
c7a23324 | 14609 | /* Broadcom SB-1 CPU core */ |
65263ce3 TS |
14610 | { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, |
14611 | ISA_MIPS64, CPU_SB1 }, | |
1e85aad8 JW |
14612 | /* Broadcom SB-1A CPU core */ |
14613 | { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX, | |
14614 | ISA_MIPS64, CPU_SB1 }, | |
e7af610e | 14615 | |
316f5878 RS |
14616 | /* End marker */ |
14617 | { NULL, 0, 0, 0 } | |
14618 | }; | |
e7af610e | 14619 | |
84ea6cf2 | 14620 | |
316f5878 RS |
14621 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
14622 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 14623 | |
316f5878 | 14624 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 14625 | |
b34976b6 | 14626 | static bfd_boolean |
17a2f251 | 14627 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
14628 | { |
14629 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
14630 | given++, canonical++; | |
14631 | ||
14632 | return ((*given == 0 && *canonical == 0) | |
14633 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
14634 | } | |
14635 | ||
14636 | ||
14637 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
14638 | CPU name. We've traditionally allowed a lot of variation here. | |
14639 | ||
14640 | Note: this function is shared between GCC and GAS. */ | |
14641 | ||
b34976b6 | 14642 | static bfd_boolean |
17a2f251 | 14643 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
14644 | { |
14645 | /* First see if the name matches exactly, or with a final "000" | |
14646 | turned into "k". */ | |
14647 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 14648 | return TRUE; |
316f5878 RS |
14649 | |
14650 | /* If not, try comparing based on numerical designation alone. | |
14651 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
14652 | if (TOLOWER (*given) == 'r') | |
14653 | given++; | |
14654 | if (!ISDIGIT (*given)) | |
b34976b6 | 14655 | return FALSE; |
316f5878 RS |
14656 | |
14657 | /* Skip over some well-known prefixes in the canonical name, | |
14658 | hoping to find a number there too. */ | |
14659 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
14660 | canonical += 2; | |
14661 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
14662 | canonical += 2; | |
14663 | else if (TOLOWER (canonical[0]) == 'r') | |
14664 | canonical += 1; | |
14665 | ||
14666 | return mips_strict_matching_cpu_name_p (canonical, given); | |
14667 | } | |
14668 | ||
14669 | ||
14670 | /* Parse an option that takes the name of a processor as its argument. | |
14671 | OPTION is the name of the option and CPU_STRING is the argument. | |
14672 | Return the corresponding processor enumeration if the CPU_STRING is | |
14673 | recognized, otherwise report an error and return null. | |
14674 | ||
14675 | A similar function exists in GCC. */ | |
e7af610e NC |
14676 | |
14677 | static const struct mips_cpu_info * | |
17a2f251 | 14678 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 14679 | { |
316f5878 | 14680 | const struct mips_cpu_info *p; |
e7af610e | 14681 | |
316f5878 RS |
14682 | /* 'from-abi' selects the most compatible architecture for the given |
14683 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
14684 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
14685 | version. Look first at the -mgp options, if given, otherwise base | |
14686 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 14687 | |
316f5878 RS |
14688 | Treat NO_ABI like the EABIs. One reason to do this is that the |
14689 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
14690 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
14691 | 'mips64', just as we did in the days before 'from-abi'. */ | |
14692 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
14693 | { | |
14694 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
14695 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
14696 | ||
14697 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
14698 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
14699 | ||
14700 | if (file_mips_gp32 >= 0) | |
14701 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
14702 | ||
14703 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
14704 | ? ISA_MIPS3 | |
14705 | : ISA_MIPS1); | |
14706 | } | |
14707 | ||
14708 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
14709 | if (strcasecmp (cpu_string, "default") == 0) | |
14710 | return 0; | |
14711 | ||
14712 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
14713 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
14714 | return p; | |
14715 | ||
14716 | as_bad ("Bad value (%s) for %s", cpu_string, option); | |
14717 | return 0; | |
e7af610e NC |
14718 | } |
14719 | ||
316f5878 RS |
14720 | /* Return the canonical processor information for ISA (a member of the |
14721 | ISA_MIPS* enumeration). */ | |
14722 | ||
e7af610e | 14723 | static const struct mips_cpu_info * |
17a2f251 | 14724 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
14725 | { |
14726 | int i; | |
14727 | ||
14728 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
ad3fea08 | 14729 | if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA) |
316f5878 | 14730 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
14731 | return (&mips_cpu_info_table[i]); |
14732 | ||
e972090a | 14733 | return NULL; |
e7af610e | 14734 | } |
fef14a42 TS |
14735 | |
14736 | static const struct mips_cpu_info * | |
17a2f251 | 14737 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
14738 | { |
14739 | int i; | |
14740 | ||
14741 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
14742 | if (arch == mips_cpu_info_table[i].cpu) | |
14743 | return (&mips_cpu_info_table[i]); | |
14744 | ||
14745 | return NULL; | |
14746 | } | |
316f5878 RS |
14747 | \f |
14748 | static void | |
17a2f251 | 14749 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
14750 | { |
14751 | if (*first_p) | |
14752 | { | |
14753 | fprintf (stream, "%24s", ""); | |
14754 | *col_p = 24; | |
14755 | } | |
14756 | else | |
14757 | { | |
14758 | fprintf (stream, ", "); | |
14759 | *col_p += 2; | |
14760 | } | |
e7af610e | 14761 | |
316f5878 RS |
14762 | if (*col_p + strlen (string) > 72) |
14763 | { | |
14764 | fprintf (stream, "\n%24s", ""); | |
14765 | *col_p = 24; | |
14766 | } | |
14767 | ||
14768 | fprintf (stream, "%s", string); | |
14769 | *col_p += strlen (string); | |
14770 | ||
14771 | *first_p = 0; | |
14772 | } | |
14773 | ||
14774 | void | |
17a2f251 | 14775 | md_show_usage (FILE *stream) |
e7af610e | 14776 | { |
316f5878 RS |
14777 | int column, first; |
14778 | size_t i; | |
14779 | ||
14780 | fprintf (stream, _("\ | |
14781 | MIPS options:\n\ | |
316f5878 RS |
14782 | -EB generate big endian output\n\ |
14783 | -EL generate little endian output\n\ | |
14784 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
14785 | -G NUM allow referencing objects up to NUM bytes\n\ | |
14786 | implicitly with the gp register [default 8]\n")); | |
14787 | fprintf (stream, _("\ | |
14788 | -mips1 generate MIPS ISA I instructions\n\ | |
14789 | -mips2 generate MIPS ISA II instructions\n\ | |
14790 | -mips3 generate MIPS ISA III instructions\n\ | |
14791 | -mips4 generate MIPS ISA IV instructions\n\ | |
14792 | -mips5 generate MIPS ISA V instructions\n\ | |
14793 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 14794 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 | 14795 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 14796 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
316f5878 RS |
14797 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
14798 | ||
14799 | first = 1; | |
e7af610e NC |
14800 | |
14801 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
14802 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
14803 | show (stream, "from-abi", &column, &first); | |
14804 | fputc ('\n', stream); | |
e7af610e | 14805 | |
316f5878 RS |
14806 | fprintf (stream, _("\ |
14807 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
14808 | -no-mCPU don't generate code specific to CPU.\n\ | |
14809 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
14810 | ||
14811 | first = 1; | |
14812 | ||
14813 | show (stream, "3900", &column, &first); | |
14814 | show (stream, "4010", &column, &first); | |
14815 | show (stream, "4100", &column, &first); | |
14816 | show (stream, "4650", &column, &first); | |
14817 | fputc ('\n', stream); | |
14818 | ||
14819 | fprintf (stream, _("\ | |
14820 | -mips16 generate mips16 instructions\n\ | |
14821 | -no-mips16 do not generate mips16 instructions\n")); | |
14822 | fprintf (stream, _("\ | |
e16bfa71 TS |
14823 | -msmartmips generate smartmips instructions\n\ |
14824 | -mno-smartmips do not generate smartmips instructions\n")); | |
14825 | fprintf (stream, _("\ | |
74cd071d CF |
14826 | -mdsp generate DSP instructions\n\ |
14827 | -mno-dsp do not generate DSP instructions\n")); | |
14828 | fprintf (stream, _("\ | |
ef2e4d86 CF |
14829 | -mmt generate MT instructions\n\ |
14830 | -mno-mt do not generate MT instructions\n")); | |
14831 | fprintf (stream, _("\ | |
d766e8ec | 14832 | -mfix-vr4120 work around certain VR4120 errata\n\ |
7d8e00cf | 14833 | -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ |
316f5878 RS |
14834 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
14835 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
aed1a261 RS |
14836 | -mno-shared optimize output for executables\n\ |
14837 | -msym32 assume all symbols have 32-bit values\n\ | |
316f5878 RS |
14838 | -O0 remove unneeded NOPs, do not swap branches\n\ |
14839 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
14840 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ |
14841 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ | |
14842 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
14843 | #ifdef OBJ_ELF | |
14844 | fprintf (stream, _("\ | |
14845 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
14846 | -non_shared do not generate position independent code\n\ | |
14847 | -xgot assume a 32 bit GOT\n\ | |
dcd410fe | 14848 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
bbe506e8 TS |
14849 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
14850 | non-shared code\n\ | |
316f5878 RS |
14851 | -mabi=ABI create ABI conformant object file for:\n")); |
14852 | ||
14853 | first = 1; | |
14854 | ||
14855 | show (stream, "32", &column, &first); | |
14856 | show (stream, "o64", &column, &first); | |
14857 | show (stream, "n32", &column, &first); | |
14858 | show (stream, "64", &column, &first); | |
14859 | show (stream, "eabi", &column, &first); | |
14860 | ||
14861 | fputc ('\n', stream); | |
14862 | ||
14863 | fprintf (stream, _("\ | |
14864 | -32 create o32 ABI object file (default)\n\ | |
14865 | -n32 create n32 ABI object file\n\ | |
14866 | -64 create 64 ABI object file\n")); | |
14867 | #endif | |
e7af610e | 14868 | } |
14e777e0 KB |
14869 | |
14870 | enum dwarf2_format | |
17a2f251 | 14871 | mips_dwarf2_format (void) |
14e777e0 KB |
14872 | { |
14873 | if (mips_abi == N64_ABI) | |
1de5b6a1 AO |
14874 | { |
14875 | #ifdef TE_IRIX | |
14876 | return dwarf2_format_64bit_irix; | |
14877 | #else | |
14878 | return dwarf2_format_64bit; | |
14879 | #endif | |
14880 | } | |
14e777e0 KB |
14881 | else |
14882 | return dwarf2_format_32bit; | |
14883 | } | |
73369e65 EC |
14884 | |
14885 | int | |
14886 | mips_dwarf2_addr_size (void) | |
14887 | { | |
14888 | if (mips_abi == N64_ABI) | |
14889 | return 8; | |
73369e65 EC |
14890 | else |
14891 | return 4; | |
14892 | } | |
5862107c EC |
14893 | |
14894 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
14895 | void | |
14896 | mips_cfi_frame_initial_instructions (void) | |
14897 | { | |
14898 | cfi_add_CFA_def_cfa_register (SP); | |
14899 | } | |
14900 | ||
707bfff6 TS |
14901 | int |
14902 | tc_mips_regname_to_dw2regnum (char *regname) | |
14903 | { | |
14904 | unsigned int regnum = -1; | |
14905 | unsigned int reg; | |
14906 | ||
14907 | if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®)) | |
14908 | regnum = reg; | |
14909 | ||
14910 | return regnum; | |
14911 | } |