Commit | Line | Data |
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252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
82704155 | 2 | Copyright (C) 1993-2019 Free Software Foundation, Inc. |
252b5132 RH |
3 | Contributed by the OSF and Ralph Campbell. |
4 | Written by Keith Knowles and Ralph Campbell, working independently. | |
5 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
6 | Support. | |
7 | ||
8 | This file is part of GAS. | |
9 | ||
10 | GAS is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 12 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
13 | any later version. |
14 | ||
15 | GAS is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
21 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
22 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
23 | 02110-1301, USA. */ | |
252b5132 RH |
24 | |
25 | #include "as.h" | |
26 | #include "config.h" | |
27 | #include "subsegs.h" | |
3882b010 | 28 | #include "safe-ctype.h" |
252b5132 | 29 | |
252b5132 RH |
30 | #include "opcode/mips.h" |
31 | #include "itbl-ops.h" | |
c5dd6aab | 32 | #include "dwarf2dbg.h" |
5862107c | 33 | #include "dw2gencfi.h" |
252b5132 | 34 | |
42429eac RS |
35 | /* Check assumptions made in this file. */ |
36 | typedef char static_assert1[sizeof (offsetT) < 8 ? -1 : 1]; | |
37 | typedef char static_assert2[sizeof (valueT) < 8 ? -1 : 1]; | |
38 | ||
252b5132 RH |
39 | #ifdef DEBUG |
40 | #define DBG(x) printf x | |
41 | #else | |
42 | #define DBG(x) | |
43 | #endif | |
44 | ||
263b2574 | 45 | #define streq(a, b) (strcmp (a, b) == 0) |
46 | ||
9e12b7a2 RS |
47 | #define SKIP_SPACE_TABS(S) \ |
48 | do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0) | |
49 | ||
252b5132 | 50 | /* Clean up namespace so we can include obj-elf.h too. */ |
17a2f251 TS |
51 | static int mips_output_flavor (void); |
52 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
53 | #undef OBJ_PROCESS_STAB |
54 | #undef OUTPUT_FLAVOR | |
55 | #undef S_GET_ALIGN | |
56 | #undef S_GET_SIZE | |
57 | #undef S_SET_ALIGN | |
58 | #undef S_SET_SIZE | |
252b5132 RH |
59 | #undef obj_frob_file |
60 | #undef obj_frob_file_after_relocs | |
61 | #undef obj_frob_symbol | |
62 | #undef obj_pop_insert | |
63 | #undef obj_sec_sym_ok_for_reloc | |
64 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
65 | ||
66 | #include "obj-elf.h" | |
67 | /* Fix any of them that we actually care about. */ | |
68 | #undef OUTPUT_FLAVOR | |
69 | #define OUTPUT_FLAVOR mips_output_flavor() | |
252b5132 | 70 | |
252b5132 | 71 | #include "elf/mips.h" |
252b5132 RH |
72 | |
73 | #ifndef ECOFF_DEBUGGING | |
74 | #define NO_ECOFF_DEBUGGING | |
75 | #define ECOFF_DEBUGGING 0 | |
76 | #endif | |
77 | ||
ecb4347a DJ |
78 | int mips_flag_mdebug = -1; |
79 | ||
dcd410fe RO |
80 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
81 | linker doesn't know about and discards them, but relocations against them | |
82 | remain, leading to rld crashes. */ | |
83 | #ifdef TE_IRIX | |
84 | int mips_flag_pdr = FALSE; | |
85 | #else | |
86 | int mips_flag_pdr = TRUE; | |
87 | #endif | |
88 | ||
252b5132 RH |
89 | #include "ecoff.h" |
90 | ||
252b5132 | 91 | static char *mips_regmask_frag; |
351cdf24 | 92 | static char *mips_flags_frag; |
252b5132 | 93 | |
85b51719 | 94 | #define ZERO 0 |
741fe287 | 95 | #define ATREG 1 |
df58fc94 RS |
96 | #define S0 16 |
97 | #define S7 23 | |
252b5132 RH |
98 | #define TREG 24 |
99 | #define PIC_CALL_REG 25 | |
100 | #define KT0 26 | |
101 | #define KT1 27 | |
102 | #define GP 28 | |
103 | #define SP 29 | |
104 | #define FP 30 | |
105 | #define RA 31 | |
106 | ||
107 | #define ILLEGAL_REG (32) | |
108 | ||
741fe287 MR |
109 | #define AT mips_opts.at |
110 | ||
252b5132 RH |
111 | extern int target_big_endian; |
112 | ||
252b5132 | 113 | /* The name of the readonly data section. */ |
e8044f35 | 114 | #define RDATA_SECTION_NAME ".rodata" |
252b5132 | 115 | |
a4e06468 RS |
116 | /* Ways in which an instruction can be "appended" to the output. */ |
117 | enum append_method { | |
118 | /* Just add it normally. */ | |
119 | APPEND_ADD, | |
120 | ||
121 | /* Add it normally and then add a nop. */ | |
122 | APPEND_ADD_WITH_NOP, | |
123 | ||
124 | /* Turn an instruction with a delay slot into a "compact" version. */ | |
125 | APPEND_ADD_COMPACT, | |
126 | ||
127 | /* Insert the instruction before the last one. */ | |
128 | APPEND_SWAP | |
129 | }; | |
130 | ||
47e39b9d RS |
131 | /* Information about an instruction, including its format, operands |
132 | and fixups. */ | |
133 | struct mips_cl_insn | |
134 | { | |
135 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ | |
136 | const struct mips_opcode *insn_mo; | |
137 | ||
47e39b9d | 138 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is |
5c04167a RS |
139 | a copy of INSN_MO->match with the operands filled in. If we have |
140 | decided to use an extended MIPS16 instruction, this includes the | |
141 | extension. */ | |
47e39b9d RS |
142 | unsigned long insn_opcode; |
143 | ||
6f2117ba PH |
144 | /* The name if this is an label. */ |
145 | char label[16]; | |
146 | ||
147 | /* The target label name if this is an branch. */ | |
148 | char target[16]; | |
149 | ||
47e39b9d RS |
150 | /* The frag that contains the instruction. */ |
151 | struct frag *frag; | |
152 | ||
153 | /* The offset into FRAG of the first instruction byte. */ | |
154 | long where; | |
155 | ||
156 | /* The relocs associated with the instruction, if any. */ | |
157 | fixS *fixp[3]; | |
158 | ||
a38419a5 RS |
159 | /* True if this entry cannot be moved from its current position. */ |
160 | unsigned int fixed_p : 1; | |
47e39b9d | 161 | |
708587a4 | 162 | /* True if this instruction occurred in a .set noreorder block. */ |
47e39b9d RS |
163 | unsigned int noreorder_p : 1; |
164 | ||
2fa15973 RS |
165 | /* True for mips16 instructions that jump to an absolute address. */ |
166 | unsigned int mips16_absolute_jump_p : 1; | |
15be625d CM |
167 | |
168 | /* True if this instruction is complete. */ | |
169 | unsigned int complete_p : 1; | |
e407c74b NC |
170 | |
171 | /* True if this instruction is cleared from history by unconditional | |
172 | branch. */ | |
173 | unsigned int cleared_p : 1; | |
47e39b9d RS |
174 | }; |
175 | ||
a325df1d TS |
176 | /* The ABI to use. */ |
177 | enum mips_abi_level | |
178 | { | |
179 | NO_ABI = 0, | |
180 | O32_ABI, | |
181 | O64_ABI, | |
182 | N32_ABI, | |
183 | N64_ABI, | |
184 | EABI_ABI | |
185 | }; | |
186 | ||
187 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 188 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 189 | |
143d77c5 EC |
190 | /* Whether or not we have code that can call pic code. */ |
191 | int mips_abicalls = FALSE; | |
192 | ||
aa6975fb ILT |
193 | /* Whether or not we have code which can be put into a shared |
194 | library. */ | |
195 | static bfd_boolean mips_in_shared = TRUE; | |
196 | ||
252b5132 RH |
197 | /* This is the set of options which may be modified by the .set |
198 | pseudo-op. We use a struct so that .set push and .set pop are more | |
199 | reliable. */ | |
200 | ||
e972090a NC |
201 | struct mips_set_options |
202 | { | |
252b5132 RH |
203 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
204 | if it has not been initialized. Changed by `.set mipsN', and the | |
205 | -mipsN command line option, and the default CPU. */ | |
206 | int isa; | |
846ef2d0 RS |
207 | /* Enabled Application Specific Extensions (ASEs). Changed by `.set |
208 | <asename>', by command line options, and based on the default | |
209 | architecture. */ | |
210 | int ase; | |
252b5132 RH |
211 | /* Whether we are assembling for the mips16 processor. 0 if we are |
212 | not, 1 if we are, and -1 if the value has not been initialized. | |
213 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
214 | -nomips16 command line options, and the default CPU. */ | |
215 | int mips16; | |
df58fc94 RS |
216 | /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not, |
217 | 1 if we are, and -1 if the value has not been initialized. Changed | |
218 | by `.set micromips' and `.set nomicromips', and the -mmicromips | |
219 | and -mno-micromips command line options, and the default CPU. */ | |
220 | int micromips; | |
252b5132 RH |
221 | /* Non-zero if we should not reorder instructions. Changed by `.set |
222 | reorder' and `.set noreorder'. */ | |
223 | int noreorder; | |
741fe287 MR |
224 | /* Non-zero if we should not permit the register designated "assembler |
225 | temporary" to be used in instructions. The value is the register | |
226 | number, normally $at ($1). Changed by `.set at=REG', `.set noat' | |
227 | (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */ | |
228 | unsigned int at; | |
252b5132 RH |
229 | /* Non-zero if we should warn when a macro instruction expands into |
230 | more than one machine instruction. Changed by `.set nomacro' and | |
231 | `.set macro'. */ | |
232 | int warn_about_macros; | |
233 | /* Non-zero if we should not move instructions. Changed by `.set | |
234 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
235 | int nomove; | |
236 | /* Non-zero if we should not optimize branches by moving the target | |
237 | of the branch into the delay slot. Actually, we don't perform | |
238 | this optimization anyhow. Changed by `.set bopt' and `.set | |
239 | nobopt'. */ | |
240 | int nobopt; | |
241 | /* Non-zero if we should not autoextend mips16 instructions. | |
242 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
243 | int noautoextend; | |
833794fc MR |
244 | /* True if we should only emit 32-bit microMIPS instructions. |
245 | Changed by `.set insn32' and `.set noinsn32', and the -minsn32 | |
246 | and -mno-insn32 command line options. */ | |
247 | bfd_boolean insn32; | |
a325df1d TS |
248 | /* Restrict general purpose registers and floating point registers |
249 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
250 | is passed but can changed if the assembler code uses .set mipsN. */ | |
bad1aba3 | 251 | int gp; |
0b35dfee | 252 | int fp; |
fef14a42 TS |
253 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
254 | command line option, and the default CPU. */ | |
255 | int arch; | |
aed1a261 RS |
256 | /* True if ".set sym32" is in effect. */ |
257 | bfd_boolean sym32; | |
037b32b9 AN |
258 | /* True if floating-point operations are not allowed. Changed by .set |
259 | softfloat or .set hardfloat, by command line options -msoft-float or | |
260 | -mhard-float. The default is false. */ | |
261 | bfd_boolean soft_float; | |
262 | ||
263 | /* True if only single-precision floating-point operations are allowed. | |
264 | Changed by .set singlefloat or .set doublefloat, command-line options | |
265 | -msingle-float or -mdouble-float. The default is false. */ | |
266 | bfd_boolean single_float; | |
351cdf24 MF |
267 | |
268 | /* 1 if single-precision operations on odd-numbered registers are | |
269 | allowed. */ | |
270 | int oddspreg; | |
252b5132 RH |
271 | }; |
272 | ||
919731af | 273 | /* Specifies whether module level options have been checked yet. */ |
274 | static bfd_boolean file_mips_opts_checked = FALSE; | |
275 | ||
7361da2c AB |
276 | /* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the |
277 | value has not been initialized. Changed by `.nan legacy' and | |
278 | `.nan 2008', and the -mnan=legacy and -mnan=2008 command line | |
279 | options, and the default CPU. */ | |
280 | static int mips_nan2008 = -1; | |
a325df1d | 281 | |
0b35dfee | 282 | /* This is the struct we use to hold the module level set of options. |
bad1aba3 | 283 | Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and |
0b35dfee | 284 | fp fields to -1 to indicate that they have not been initialized. */ |
037b32b9 | 285 | |
0b35dfee | 286 | static struct mips_set_options file_mips_opts = |
287 | { | |
288 | /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1, | |
289 | /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0, | |
290 | /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE, | |
bad1aba3 | 291 | /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE, |
351cdf24 | 292 | /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1 |
0b35dfee | 293 | }; |
252b5132 | 294 | |
0b35dfee | 295 | /* This is similar to file_mips_opts, but for the current set of options. */ |
ba92f887 | 296 | |
e972090a NC |
297 | static struct mips_set_options mips_opts = |
298 | { | |
846ef2d0 | 299 | /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1, |
b015e599 | 300 | /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0, |
833794fc | 301 | /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE, |
bad1aba3 | 302 | /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE, |
351cdf24 | 303 | /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1 |
e7af610e | 304 | }; |
252b5132 | 305 | |
846ef2d0 RS |
306 | /* Which bits of file_ase were explicitly set or cleared by ASE options. */ |
307 | static unsigned int file_ase_explicit; | |
308 | ||
252b5132 RH |
309 | /* These variables are filled in with the masks of registers used. |
310 | The object format code reads them and puts them in the appropriate | |
311 | place. */ | |
312 | unsigned long mips_gprmask; | |
313 | unsigned long mips_cprmask[4]; | |
314 | ||
738f4d98 | 315 | /* True if any MIPS16 code was produced. */ |
a4672219 TS |
316 | static int file_ase_mips16; |
317 | ||
3994f87e TS |
318 | #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \ |
319 | || mips_opts.isa == ISA_MIPS32R2 \ | |
ae52f483 AB |
320 | || mips_opts.isa == ISA_MIPS32R3 \ |
321 | || mips_opts.isa == ISA_MIPS32R5 \ | |
3994f87e | 322 | || mips_opts.isa == ISA_MIPS64 \ |
ae52f483 AB |
323 | || mips_opts.isa == ISA_MIPS64R2 \ |
324 | || mips_opts.isa == ISA_MIPS64R3 \ | |
325 | || mips_opts.isa == ISA_MIPS64R5) | |
3994f87e | 326 | |
df58fc94 RS |
327 | /* True if any microMIPS code was produced. */ |
328 | static int file_ase_micromips; | |
329 | ||
b12dd2e4 CF |
330 | /* True if we want to create R_MIPS_JALR for jalr $25. */ |
331 | #ifdef TE_IRIX | |
1180b5a4 | 332 | #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI |
b12dd2e4 | 333 | #else |
1180b5a4 RS |
334 | /* As a GNU extension, we use R_MIPS_JALR for o32 too. However, |
335 | because there's no place for any addend, the only acceptable | |
336 | expression is a bare symbol. */ | |
337 | #define MIPS_JALR_HINT_P(EXPR) \ | |
338 | (!HAVE_IN_PLACE_ADDENDS \ | |
339 | || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0)) | |
b12dd2e4 CF |
340 | #endif |
341 | ||
ec68c924 | 342 | /* The argument of the -march= flag. The architecture we are assembling. */ |
316f5878 | 343 | static const char *mips_arch_string; |
ec68c924 EC |
344 | |
345 | /* The argument of the -mtune= flag. The architecture for which we | |
346 | are optimizing. */ | |
347 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 348 | static const char *mips_tune_string; |
ec68c924 | 349 | |
316f5878 | 350 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
351 | static int mips_32bitmode = 0; |
352 | ||
316f5878 RS |
353 | /* True if the given ABI requires 32-bit registers. */ |
354 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
355 | ||
356 | /* Likewise 64-bit registers. */ | |
707bfff6 | 357 | #define ABI_NEEDS_64BIT_REGS(ABI) \ |
134c0c8b | 358 | ((ABI) == N32_ABI \ |
707bfff6 | 359 | || (ABI) == N64_ABI \ |
316f5878 RS |
360 | || (ABI) == O64_ABI) |
361 | ||
7361da2c AB |
362 | #define ISA_IS_R6(ISA) \ |
363 | ((ISA) == ISA_MIPS32R6 \ | |
364 | || (ISA) == ISA_MIPS64R6) | |
365 | ||
ad3fea08 | 366 | /* Return true if ISA supports 64 bit wide gp registers. */ |
707bfff6 TS |
367 | #define ISA_HAS_64BIT_REGS(ISA) \ |
368 | ((ISA) == ISA_MIPS3 \ | |
369 | || (ISA) == ISA_MIPS4 \ | |
370 | || (ISA) == ISA_MIPS5 \ | |
371 | || (ISA) == ISA_MIPS64 \ | |
ae52f483 AB |
372 | || (ISA) == ISA_MIPS64R2 \ |
373 | || (ISA) == ISA_MIPS64R3 \ | |
7361da2c AB |
374 | || (ISA) == ISA_MIPS64R5 \ |
375 | || (ISA) == ISA_MIPS64R6) | |
9ce8a5dd | 376 | |
ad3fea08 TS |
377 | /* Return true if ISA supports 64 bit wide float registers. */ |
378 | #define ISA_HAS_64BIT_FPRS(ISA) \ | |
379 | ((ISA) == ISA_MIPS3 \ | |
380 | || (ISA) == ISA_MIPS4 \ | |
381 | || (ISA) == ISA_MIPS5 \ | |
382 | || (ISA) == ISA_MIPS32R2 \ | |
ae52f483 AB |
383 | || (ISA) == ISA_MIPS32R3 \ |
384 | || (ISA) == ISA_MIPS32R5 \ | |
7361da2c | 385 | || (ISA) == ISA_MIPS32R6 \ |
ad3fea08 | 386 | || (ISA) == ISA_MIPS64 \ |
ae52f483 AB |
387 | || (ISA) == ISA_MIPS64R2 \ |
388 | || (ISA) == ISA_MIPS64R3 \ | |
7361da2c AB |
389 | || (ISA) == ISA_MIPS64R5 \ |
390 | || (ISA) == ISA_MIPS64R6) | |
ad3fea08 | 391 | |
af7ee8bf CD |
392 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
393 | instructions. */ | |
707bfff6 | 394 | #define ISA_HAS_DROR(ISA) \ |
df58fc94 | 395 | ((ISA) == ISA_MIPS64R2 \ |
ae52f483 AB |
396 | || (ISA) == ISA_MIPS64R3 \ |
397 | || (ISA) == ISA_MIPS64R5 \ | |
7361da2c | 398 | || (ISA) == ISA_MIPS64R6 \ |
df58fc94 RS |
399 | || (mips_opts.micromips \ |
400 | && ISA_HAS_64BIT_REGS (ISA)) \ | |
401 | ) | |
af7ee8bf CD |
402 | |
403 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
404 | instructions. */ | |
707bfff6 TS |
405 | #define ISA_HAS_ROR(ISA) \ |
406 | ((ISA) == ISA_MIPS32R2 \ | |
ae52f483 AB |
407 | || (ISA) == ISA_MIPS32R3 \ |
408 | || (ISA) == ISA_MIPS32R5 \ | |
7361da2c | 409 | || (ISA) == ISA_MIPS32R6 \ |
707bfff6 | 410 | || (ISA) == ISA_MIPS64R2 \ |
ae52f483 AB |
411 | || (ISA) == ISA_MIPS64R3 \ |
412 | || (ISA) == ISA_MIPS64R5 \ | |
7361da2c | 413 | || (ISA) == ISA_MIPS64R6 \ |
846ef2d0 | 414 | || (mips_opts.ase & ASE_SMARTMIPS) \ |
df58fc94 RS |
415 | || mips_opts.micromips \ |
416 | ) | |
707bfff6 | 417 | |
7455baf8 | 418 | /* Return true if ISA supports single-precision floats in odd registers. */ |
351cdf24 MF |
419 | #define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\ |
420 | (((ISA) == ISA_MIPS32 \ | |
421 | || (ISA) == ISA_MIPS32R2 \ | |
422 | || (ISA) == ISA_MIPS32R3 \ | |
423 | || (ISA) == ISA_MIPS32R5 \ | |
7361da2c | 424 | || (ISA) == ISA_MIPS32R6 \ |
351cdf24 MF |
425 | || (ISA) == ISA_MIPS64 \ |
426 | || (ISA) == ISA_MIPS64R2 \ | |
427 | || (ISA) == ISA_MIPS64R3 \ | |
428 | || (ISA) == ISA_MIPS64R5 \ | |
7361da2c | 429 | || (ISA) == ISA_MIPS64R6 \ |
351cdf24 | 430 | || (CPU) == CPU_R5900) \ |
bd782c07 | 431 | && ((CPU) != CPU_GS464 \ |
9108bc33 CX |
432 | || (CPU) != CPU_GS464E \ |
433 | || (CPU) != CPU_GS264E)) | |
af7ee8bf | 434 | |
ad3fea08 TS |
435 | /* Return true if ISA supports move to/from high part of a 64-bit |
436 | floating-point register. */ | |
437 | #define ISA_HAS_MXHC1(ISA) \ | |
438 | ((ISA) == ISA_MIPS32R2 \ | |
ae52f483 AB |
439 | || (ISA) == ISA_MIPS32R3 \ |
440 | || (ISA) == ISA_MIPS32R5 \ | |
7361da2c AB |
441 | || (ISA) == ISA_MIPS32R6 \ |
442 | || (ISA) == ISA_MIPS64R2 \ | |
443 | || (ISA) == ISA_MIPS64R3 \ | |
444 | || (ISA) == ISA_MIPS64R5 \ | |
445 | || (ISA) == ISA_MIPS64R6) | |
446 | ||
447 | /* Return true if ISA supports legacy NAN. */ | |
448 | #define ISA_HAS_LEGACY_NAN(ISA) \ | |
449 | ((ISA) == ISA_MIPS1 \ | |
450 | || (ISA) == ISA_MIPS2 \ | |
451 | || (ISA) == ISA_MIPS3 \ | |
452 | || (ISA) == ISA_MIPS4 \ | |
453 | || (ISA) == ISA_MIPS5 \ | |
454 | || (ISA) == ISA_MIPS32 \ | |
455 | || (ISA) == ISA_MIPS32R2 \ | |
456 | || (ISA) == ISA_MIPS32R3 \ | |
457 | || (ISA) == ISA_MIPS32R5 \ | |
458 | || (ISA) == ISA_MIPS64 \ | |
ae52f483 AB |
459 | || (ISA) == ISA_MIPS64R2 \ |
460 | || (ISA) == ISA_MIPS64R3 \ | |
461 | || (ISA) == ISA_MIPS64R5) | |
ad3fea08 | 462 | |
bad1aba3 | 463 | #define GPR_SIZE \ |
464 | (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \ | |
465 | ? 32 \ | |
466 | : mips_opts.gp) | |
ca4e0257 | 467 | |
bad1aba3 | 468 | #define FPR_SIZE \ |
469 | (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \ | |
470 | ? 32 \ | |
471 | : mips_opts.fp) | |
ca4e0257 | 472 | |
316f5878 | 473 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 474 | |
316f5878 | 475 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 476 | |
3b91255e RS |
477 | /* True if relocations are stored in-place. */ |
478 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
479 | ||
aed1a261 RS |
480 | /* The ABI-derived address size. */ |
481 | #define HAVE_64BIT_ADDRESSES \ | |
bad1aba3 | 482 | (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) |
aed1a261 | 483 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) |
e013f690 | 484 | |
aed1a261 RS |
485 | /* The size of symbolic constants (i.e., expressions of the form |
486 | "SYMBOL" or "SYMBOL + OFFSET"). */ | |
487 | #define HAVE_32BIT_SYMBOLS \ | |
488 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) | |
489 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) | |
ca4e0257 | 490 | |
b7c7d6c1 TS |
491 | /* Addresses are loaded in different ways, depending on the address size |
492 | in use. The n32 ABI Documentation also mandates the use of additions | |
493 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 494 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 495 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
496 | |
497 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 498 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
499 | |
500 | #define ADDRESS_LOAD_INSN \ | |
501 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
502 | ||
503 | #define ADDRESS_STORE_INSN \ | |
504 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
505 | ||
a4672219 | 506 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
507 | #define CPU_HAS_MIPS16(cpu) \ |
508 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
509 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 510 | |
2309ddf2 | 511 | /* Return true if the given CPU supports the microMIPS ASE. */ |
df58fc94 RS |
512 | #define CPU_HAS_MICROMIPS(cpu) 0 |
513 | ||
60b63b72 RS |
514 | /* True if CPU has a dror instruction. */ |
515 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
516 | ||
517 | /* True if CPU has a ror instruction. */ | |
518 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
519 | ||
6f2117ba | 520 | /* True if CPU is in the Octeon family. */ |
2c629856 N |
521 | #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \ |
522 | || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3) | |
dd6a37e7 | 523 | |
dd3cbb7e | 524 | /* True if CPU has seq/sne and seqi/snei instructions. */ |
dd6a37e7 | 525 | #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU)) |
dd3cbb7e | 526 | |
0aa27725 RS |
527 | /* True, if CPU has support for ldc1 and sdc1. */ |
528 | #define CPU_HAS_LDC1_SDC1(CPU) \ | |
529 | ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900)) | |
530 | ||
c8978940 CD |
531 | /* True if mflo and mfhi can be immediately followed by instructions |
532 | which write to the HI and LO registers. | |
533 | ||
534 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
535 | (at least) two instructions between the reads of HI/LO and | |
536 | instructions which write them, and later ISAs do not. Contradicting | |
537 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
538 | the UM for the NEC Vr5000) document needing the instructions between | |
539 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
540 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
541 | earlier-ISA CPUs for which CPU documentation declares that the | |
542 | instructions are really interlocked. */ | |
543 | #define hilo_interlocks \ | |
544 | (mips_opts.isa == ISA_MIPS32 \ | |
545 | || mips_opts.isa == ISA_MIPS32R2 \ | |
ae52f483 AB |
546 | || mips_opts.isa == ISA_MIPS32R3 \ |
547 | || mips_opts.isa == ISA_MIPS32R5 \ | |
7361da2c | 548 | || mips_opts.isa == ISA_MIPS32R6 \ |
c8978940 CD |
549 | || mips_opts.isa == ISA_MIPS64 \ |
550 | || mips_opts.isa == ISA_MIPS64R2 \ | |
ae52f483 AB |
551 | || mips_opts.isa == ISA_MIPS64R3 \ |
552 | || mips_opts.isa == ISA_MIPS64R5 \ | |
7361da2c | 553 | || mips_opts.isa == ISA_MIPS64R6 \ |
c8978940 | 554 | || mips_opts.arch == CPU_R4010 \ |
e407c74b | 555 | || mips_opts.arch == CPU_R5900 \ |
c8978940 CD |
556 | || mips_opts.arch == CPU_R10000 \ |
557 | || mips_opts.arch == CPU_R12000 \ | |
3aa3176b TS |
558 | || mips_opts.arch == CPU_R14000 \ |
559 | || mips_opts.arch == CPU_R16000 \ | |
c8978940 | 560 | || mips_opts.arch == CPU_RM7000 \ |
c8978940 | 561 | || mips_opts.arch == CPU_VR5500 \ |
df58fc94 | 562 | || mips_opts.micromips \ |
c8978940 | 563 | ) |
252b5132 RH |
564 | |
565 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
566 | from the GPRs after they are loaded from memory, and thus does not |
567 | require nops to be inserted. This applies to instructions marked | |
67dc82bc | 568 | INSN_LOAD_MEMORY. These nops are only required at MIPS ISA |
df58fc94 RS |
569 | level I and microMIPS mode instructions are always interlocked. */ |
570 | #define gpr_interlocks \ | |
571 | (mips_opts.isa != ISA_MIPS1 \ | |
572 | || mips_opts.arch == CPU_R3900 \ | |
e407c74b | 573 | || mips_opts.arch == CPU_R5900 \ |
df58fc94 RS |
574 | || mips_opts.micromips \ |
575 | ) | |
252b5132 | 576 | |
81912461 ILT |
577 | /* Whether the processor uses hardware interlocks to avoid delays |
578 | required by coprocessor instructions, and thus does not require | |
579 | nops to be inserted. This applies to instructions marked | |
43885403 MF |
580 | INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between |
581 | instructions marked INSN_WRITE_COND_CODE and ones marked | |
81912461 | 582 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA |
df58fc94 RS |
583 | levels I, II, and III and microMIPS mode instructions are always |
584 | interlocked. */ | |
bdaaa2e1 | 585 | /* Itbl support may require additional care here. */ |
81912461 ILT |
586 | #define cop_interlocks \ |
587 | ((mips_opts.isa != ISA_MIPS1 \ | |
588 | && mips_opts.isa != ISA_MIPS2 \ | |
589 | && mips_opts.isa != ISA_MIPS3) \ | |
590 | || mips_opts.arch == CPU_R4300 \ | |
df58fc94 | 591 | || mips_opts.micromips \ |
81912461 ILT |
592 | ) |
593 | ||
594 | /* Whether the processor uses hardware interlocks to protect reads | |
595 | from coprocessor registers after they are loaded from memory, and | |
596 | thus does not require nops to be inserted. This applies to | |
597 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
df58fc94 RS |
598 | requires at MIPS ISA level I and microMIPS mode instructions are |
599 | always interlocked. */ | |
600 | #define cop_mem_interlocks \ | |
601 | (mips_opts.isa != ISA_MIPS1 \ | |
602 | || mips_opts.micromips \ | |
603 | ) | |
252b5132 | 604 | |
6b76fefe CM |
605 | /* Is this a mfhi or mflo instruction? */ |
606 | #define MF_HILO_INSN(PINFO) \ | |
b19e8a9b AN |
607 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) |
608 | ||
df58fc94 RS |
609 | /* Whether code compression (either of the MIPS16 or the microMIPS ASEs) |
610 | has been selected. This implies, in particular, that addresses of text | |
611 | labels have their LSB set. */ | |
612 | #define HAVE_CODE_COMPRESSION \ | |
613 | ((mips_opts.mips16 | mips_opts.micromips) != 0) | |
614 | ||
42429eac | 615 | /* The minimum and maximum signed values that can be stored in a GPR. */ |
bad1aba3 | 616 | #define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1)) |
42429eac RS |
617 | #define GPR_SMIN (-GPR_SMAX - 1) |
618 | ||
252b5132 RH |
619 | /* MIPS PIC level. */ |
620 | ||
a161fe53 | 621 | enum mips_pic_level mips_pic; |
252b5132 | 622 | |
c9914766 | 623 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 624 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 625 | static int mips_big_got = 0; |
252b5132 RH |
626 | |
627 | /* 1 if trap instructions should used for overflow rather than break | |
628 | instructions. */ | |
c9914766 | 629 | static int mips_trap = 0; |
252b5132 | 630 | |
119d663a | 631 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 632 | by assembling two single width halves into two single width floating |
119d663a NC |
633 | point registers which just happen to alias the double width destination |
634 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 635 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
636 | automatically at assemble time. */ |
637 | static int mips_disable_float_construction; | |
638 | ||
252b5132 RH |
639 | /* Non-zero if any .set noreorder directives were used. */ |
640 | ||
641 | static int mips_any_noreorder; | |
642 | ||
6b76fefe CM |
643 | /* Non-zero if nops should be inserted when the register referenced in |
644 | an mfhi/mflo instruction is read in the next two instructions. */ | |
645 | static int mips_7000_hilo_fix; | |
646 | ||
02ffd3e4 | 647 | /* The size of objects in the small data section. */ |
156c2f8b | 648 | static unsigned int g_switch_value = 8; |
252b5132 RH |
649 | /* Whether the -G option was used. */ |
650 | static int g_switch_seen = 0; | |
651 | ||
652 | #define N_RMASK 0xc4 | |
653 | #define N_VFP 0xd4 | |
654 | ||
655 | /* If we can determine in advance that GP optimization won't be | |
656 | possible, we can skip the relaxation stuff that tries to produce | |
657 | GP-relative references. This makes delay slot optimization work | |
658 | better. | |
659 | ||
660 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
661 | gcc output. It needs to guess right for gcc, otherwise gcc |
662 | will put what it thinks is a GP-relative instruction in a branch | |
663 | delay slot. | |
252b5132 RH |
664 | |
665 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
666 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 667 | static int nopic_need_relax (symbolS *, int); |
252b5132 | 668 | |
6f2117ba | 669 | /* Handle of the OPCODE hash table. */ |
252b5132 RH |
670 | static struct hash_control *op_hash = NULL; |
671 | ||
672 | /* The opcode hash table we use for the mips16. */ | |
673 | static struct hash_control *mips16_op_hash = NULL; | |
674 | ||
df58fc94 RS |
675 | /* The opcode hash table we use for the microMIPS ASE. */ |
676 | static struct hash_control *micromips_op_hash = NULL; | |
677 | ||
252b5132 | 678 | /* This array holds the chars that always start a comment. If the |
6f2117ba | 679 | pre-processor is disabled, these aren't very useful. */ |
252b5132 RH |
680 | const char comment_chars[] = "#"; |
681 | ||
682 | /* This array holds the chars that only start a comment at the beginning of | |
683 | a line. If the line seems to have the form '# 123 filename' | |
6f2117ba | 684 | .line and .file directives will appear in the pre-processed output. */ |
252b5132 RH |
685 | /* Note that input_file.c hand checks for '#' at the beginning of the |
686 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 687 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
688 | /* Also note that C style comments are always supported. */ |
689 | const char line_comment_chars[] = "#"; | |
690 | ||
bdaaa2e1 | 691 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 692 | const char line_separator_chars[] = ";"; |
252b5132 | 693 | |
6f2117ba | 694 | /* Chars that can be used to separate mant from exp in floating point nums. */ |
252b5132 RH |
695 | const char EXP_CHARS[] = "eE"; |
696 | ||
6f2117ba PH |
697 | /* Chars that mean this number is a floating point constant. |
698 | As in 0f12.456 | |
699 | or 0d1.2345e12. */ | |
252b5132 RH |
700 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; |
701 | ||
702 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
703 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
6f2117ba | 704 | but nothing is ideal around here. */ |
252b5132 | 705 | |
e3de51ce | 706 | /* Types of printf format used for instruction-related error messages. |
6f2117ba PH |
707 | "I" means int ("%d") and "S" means string ("%s"). */ |
708 | enum mips_insn_error_format | |
709 | { | |
e3de51ce RS |
710 | ERR_FMT_PLAIN, |
711 | ERR_FMT_I, | |
712 | ERR_FMT_SS, | |
713 | }; | |
714 | ||
715 | /* Information about an error that was found while assembling the current | |
716 | instruction. */ | |
6f2117ba PH |
717 | struct mips_insn_error |
718 | { | |
e3de51ce RS |
719 | /* We sometimes need to match an instruction against more than one |
720 | opcode table entry. Errors found during this matching are reported | |
721 | against a particular syntactic argument rather than against the | |
722 | instruction as a whole. We grade these messages so that errors | |
723 | against argument N have a greater priority than an error against | |
724 | any argument < N, since the former implies that arguments up to N | |
725 | were acceptable and that the opcode entry was therefore a closer match. | |
726 | If several matches report an error against the same argument, | |
727 | we only use that error if it is the same in all cases. | |
728 | ||
729 | min_argnum is the minimum argument number for which an error message | |
730 | should be accepted. It is 0 if MSG is against the instruction as | |
731 | a whole. */ | |
732 | int min_argnum; | |
733 | ||
734 | /* The printf()-style message, including its format and arguments. */ | |
735 | enum mips_insn_error_format format; | |
736 | const char *msg; | |
6f2117ba PH |
737 | union |
738 | { | |
e3de51ce RS |
739 | int i; |
740 | const char *ss[2]; | |
741 | } u; | |
742 | }; | |
743 | ||
744 | /* The error that should be reported for the current instruction. */ | |
745 | static struct mips_insn_error insn_error; | |
252b5132 RH |
746 | |
747 | static int auto_align = 1; | |
748 | ||
749 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
750 | offset in the stack frame from which to restore the $gp register. | |
751 | This is set by the .cprestore pseudo-op, and saved in this | |
752 | variable. */ | |
753 | static offsetT mips_cprestore_offset = -1; | |
754 | ||
67c1ffbe | 755 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 756 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 757 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
758 | static offsetT mips_cpreturn_offset = -1; |
759 | static int mips_cpreturn_register = -1; | |
760 | static int mips_gp_register = GP; | |
def2e0dd | 761 | static int mips_gprel_offset = 0; |
6478892d | 762 | |
7a621144 DJ |
763 | /* Whether mips_cprestore_offset has been set in the current function |
764 | (or whether it has already been warned about, if not). */ | |
765 | static int mips_cprestore_valid = 0; | |
766 | ||
252b5132 RH |
767 | /* This is the register which holds the stack frame, as set by the |
768 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
769 | static int mips_frame_reg = SP; | |
770 | ||
7a621144 DJ |
771 | /* Whether mips_frame_reg has been set in the current function |
772 | (or whether it has already been warned about, if not). */ | |
773 | static int mips_frame_reg_valid = 0; | |
774 | ||
252b5132 RH |
775 | /* To output NOP instructions correctly, we need to keep information |
776 | about the previous two instructions. */ | |
777 | ||
778 | /* Whether we are optimizing. The default value of 2 means to remove | |
779 | unneeded NOPs and swap branch instructions when possible. A value | |
780 | of 1 means to not swap branches. A value of 0 means to always | |
781 | insert NOPs. */ | |
782 | static int mips_optimize = 2; | |
783 | ||
784 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
785 | equivalent to seeing no -g option at all. */ | |
786 | static int mips_debug = 0; | |
787 | ||
7d8e00cf RS |
788 | /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ |
789 | #define MAX_VR4130_NOPS 4 | |
790 | ||
791 | /* The maximum number of NOPs needed to fill delay slots. */ | |
792 | #define MAX_DELAY_NOPS 2 | |
793 | ||
794 | /* The maximum number of NOPs needed for any purpose. */ | |
795 | #define MAX_NOPS 4 | |
71400594 | 796 | |
6f2117ba PH |
797 | /* The maximum range of context length of ll/sc. */ |
798 | #define MAX_LLSC_RANGE 20 | |
799 | ||
71400594 RS |
800 | /* A list of previous instructions, with index 0 being the most recent. |
801 | We need to look back MAX_NOPS instructions when filling delay slots | |
802 | or working around processor errata. We need to look back one | |
803 | instruction further if we're thinking about using history[0] to | |
804 | fill a branch delay slot. */ | |
6f2117ba | 805 | static struct mips_cl_insn history[1 + MAX_NOPS + MAX_LLSC_RANGE]; |
252b5132 | 806 | |
fc76e730 | 807 | /* Arrays of operands for each instruction. */ |
14daeee3 | 808 | #define MAX_OPERANDS 6 |
6f2117ba PH |
809 | struct mips_operand_array |
810 | { | |
fc76e730 RS |
811 | const struct mips_operand *operand[MAX_OPERANDS]; |
812 | }; | |
813 | static struct mips_operand_array *mips_operands; | |
814 | static struct mips_operand_array *mips16_operands; | |
815 | static struct mips_operand_array *micromips_operands; | |
816 | ||
1e915849 | 817 | /* Nop instructions used by emit_nop. */ |
df58fc94 RS |
818 | static struct mips_cl_insn nop_insn; |
819 | static struct mips_cl_insn mips16_nop_insn; | |
820 | static struct mips_cl_insn micromips_nop16_insn; | |
821 | static struct mips_cl_insn micromips_nop32_insn; | |
1e915849 | 822 | |
6f2117ba PH |
823 | /* Sync instructions used by insert sync. */ |
824 | static struct mips_cl_insn sync_insn; | |
825 | ||
1e915849 | 826 | /* The appropriate nop for the current mode. */ |
833794fc MR |
827 | #define NOP_INSN (mips_opts.mips16 \ |
828 | ? &mips16_nop_insn \ | |
829 | : (mips_opts.micromips \ | |
830 | ? (mips_opts.insn32 \ | |
831 | ? µmips_nop32_insn \ | |
832 | : µmips_nop16_insn) \ | |
833 | : &nop_insn)) | |
df58fc94 RS |
834 | |
835 | /* The size of NOP_INSN in bytes. */ | |
833794fc MR |
836 | #define NOP_INSN_SIZE ((mips_opts.mips16 \ |
837 | || (mips_opts.micromips && !mips_opts.insn32)) \ | |
838 | ? 2 : 4) | |
252b5132 | 839 | |
252b5132 RH |
840 | /* If this is set, it points to a frag holding nop instructions which |
841 | were inserted before the start of a noreorder section. If those | |
842 | nops turn out to be unnecessary, the size of the frag can be | |
843 | decreased. */ | |
844 | static fragS *prev_nop_frag; | |
845 | ||
846 | /* The number of nop instructions we created in prev_nop_frag. */ | |
847 | static int prev_nop_frag_holds; | |
848 | ||
849 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 850 | prev_nop_frag. */ |
252b5132 RH |
851 | static int prev_nop_frag_required; |
852 | ||
853 | /* The number of instructions we've seen since prev_nop_frag. */ | |
854 | static int prev_nop_frag_since; | |
855 | ||
e8044f35 RS |
856 | /* Relocations against symbols are sometimes done in two parts, with a HI |
857 | relocation and a LO relocation. Each relocation has only 16 bits of | |
858 | space to store an addend. This means that in order for the linker to | |
859 | handle carries correctly, it must be able to locate both the HI and | |
860 | the LO relocation. This means that the relocations must appear in | |
861 | order in the relocation table. | |
252b5132 RH |
862 | |
863 | In order to implement this, we keep track of each unmatched HI | |
864 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 865 | corresponding LO relocation. */ |
252b5132 | 866 | |
e972090a NC |
867 | struct mips_hi_fixup |
868 | { | |
252b5132 RH |
869 | /* Next HI fixup. */ |
870 | struct mips_hi_fixup *next; | |
871 | /* This fixup. */ | |
872 | fixS *fixp; | |
873 | /* The section this fixup is in. */ | |
874 | segT seg; | |
875 | }; | |
876 | ||
877 | /* The list of unmatched HI relocs. */ | |
878 | ||
879 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
880 | ||
64bdfcaf RS |
881 | /* The frag containing the last explicit relocation operator. |
882 | Null if explicit relocations have not been used. */ | |
883 | ||
884 | static fragS *prev_reloc_op_frag; | |
885 | ||
252b5132 RH |
886 | /* Map mips16 register numbers to normal MIPS register numbers. */ |
887 | ||
e972090a NC |
888 | static const unsigned int mips16_to_32_reg_map[] = |
889 | { | |
252b5132 RH |
890 | 16, 17, 2, 3, 4, 5, 6, 7 |
891 | }; | |
60b63b72 | 892 | |
df58fc94 RS |
893 | /* Map microMIPS register numbers to normal MIPS register numbers. */ |
894 | ||
df58fc94 | 895 | #define micromips_to_32_reg_d_map mips16_to_32_reg_map |
df58fc94 RS |
896 | |
897 | /* The microMIPS registers with type h. */ | |
e76ff5ab | 898 | static const unsigned int micromips_to_32_reg_h_map1[] = |
df58fc94 RS |
899 | { |
900 | 5, 5, 6, 4, 4, 4, 4, 4 | |
901 | }; | |
e76ff5ab | 902 | static const unsigned int micromips_to_32_reg_h_map2[] = |
df58fc94 RS |
903 | { |
904 | 6, 7, 7, 21, 22, 5, 6, 7 | |
905 | }; | |
906 | ||
df58fc94 RS |
907 | /* The microMIPS registers with type m. */ |
908 | static const unsigned int micromips_to_32_reg_m_map[] = | |
909 | { | |
910 | 0, 17, 2, 3, 16, 18, 19, 20 | |
911 | }; | |
912 | ||
913 | #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map | |
914 | ||
71400594 RS |
915 | /* Classifies the kind of instructions we're interested in when |
916 | implementing -mfix-vr4120. */ | |
c67a084a NC |
917 | enum fix_vr4120_class |
918 | { | |
71400594 RS |
919 | FIX_VR4120_MACC, |
920 | FIX_VR4120_DMACC, | |
921 | FIX_VR4120_MULT, | |
922 | FIX_VR4120_DMULT, | |
923 | FIX_VR4120_DIV, | |
924 | FIX_VR4120_MTHILO, | |
925 | NUM_FIX_VR4120_CLASSES | |
926 | }; | |
927 | ||
c67a084a NC |
928 | /* ...likewise -mfix-loongson2f-jump. */ |
929 | static bfd_boolean mips_fix_loongson2f_jump; | |
930 | ||
931 | /* ...likewise -mfix-loongson2f-nop. */ | |
932 | static bfd_boolean mips_fix_loongson2f_nop; | |
933 | ||
934 | /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */ | |
935 | static bfd_boolean mips_fix_loongson2f; | |
936 | ||
71400594 RS |
937 | /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if |
938 | there must be at least one other instruction between an instruction | |
939 | of type X and an instruction of type Y. */ | |
940 | static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; | |
941 | ||
942 | /* True if -mfix-vr4120 is in force. */ | |
d766e8ec | 943 | static int mips_fix_vr4120; |
4a6a3df4 | 944 | |
7d8e00cf RS |
945 | /* ...likewise -mfix-vr4130. */ |
946 | static int mips_fix_vr4130; | |
947 | ||
6a32d874 CM |
948 | /* ...likewise -mfix-24k. */ |
949 | static int mips_fix_24k; | |
950 | ||
a8d14a88 CM |
951 | /* ...likewise -mfix-rm7000 */ |
952 | static int mips_fix_rm7000; | |
953 | ||
d954098f DD |
954 | /* ...likewise -mfix-cn63xxp1 */ |
955 | static bfd_boolean mips_fix_cn63xxp1; | |
956 | ||
27c634e0 FN |
957 | /* ...likewise -mfix-r5900 */ |
958 | static bfd_boolean mips_fix_r5900; | |
959 | static bfd_boolean mips_fix_r5900_explicit; | |
960 | ||
6f2117ba PH |
961 | /* ...likewise -mfix-loongson3-llsc. */ |
962 | static bfd_boolean mips_fix_loongson3_llsc = DEFAULT_MIPS_FIX_LOONGSON3_LLSC; | |
963 | ||
4a6a3df4 AO |
964 | /* We don't relax branches by default, since this causes us to expand |
965 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
966 | fail to compute the offset before expanding the macro to the most | |
967 | efficient expansion. */ | |
968 | ||
969 | static int mips_relax_branch; | |
8b10b0b3 MR |
970 | |
971 | /* TRUE if checks are suppressed for invalid branches between ISA modes. | |
972 | Needed for broken assembly produced by some GCC versions and some | |
973 | sloppy code out there, where branches to data labels are present. */ | |
974 | static bfd_boolean mips_ignore_branch_isa; | |
252b5132 | 975 | \f |
4d7206a2 RS |
976 | /* The expansion of many macros depends on the type of symbol that |
977 | they refer to. For example, when generating position-dependent code, | |
978 | a macro that refers to a symbol may have two different expansions, | |
979 | one which uses GP-relative addresses and one which uses absolute | |
980 | addresses. When generating SVR4-style PIC, a macro may have | |
981 | different expansions for local and global symbols. | |
982 | ||
983 | We handle these situations by generating both sequences and putting | |
984 | them in variant frags. In position-dependent code, the first sequence | |
985 | will be the GP-relative one and the second sequence will be the | |
986 | absolute one. In SVR4 PIC, the first sequence will be for global | |
987 | symbols and the second will be for local symbols. | |
988 | ||
584892a6 RS |
989 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
990 | SECOND are the lengths of the two sequences in bytes. These fields | |
991 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
992 | the subtype has the following flags: | |
4d7206a2 | 993 | |
ce8ad872 MR |
994 | RELAX_PIC |
995 | Set if generating PIC code. | |
996 | ||
584892a6 RS |
997 | RELAX_USE_SECOND |
998 | Set if it has been decided that we should use the second | |
999 | sequence instead of the first. | |
1000 | ||
1001 | RELAX_SECOND_LONGER | |
1002 | Set in the first variant frag if the macro's second implementation | |
1003 | is longer than its first. This refers to the macro as a whole, | |
1004 | not an individual relaxation. | |
1005 | ||
1006 | RELAX_NOMACRO | |
1007 | Set in the first variant frag if the macro appeared in a .set nomacro | |
1008 | block and if one alternative requires a warning but the other does not. | |
1009 | ||
1010 | RELAX_DELAY_SLOT | |
1011 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
1012 | delay slot. | |
4d7206a2 | 1013 | |
df58fc94 RS |
1014 | RELAX_DELAY_SLOT_16BIT |
1015 | Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a | |
1016 | 16-bit instruction. | |
1017 | ||
1018 | RELAX_DELAY_SLOT_SIZE_FIRST | |
1019 | Like RELAX_DELAY_SLOT, but indicates that the first implementation of | |
1020 | the macro is of the wrong size for the branch delay slot. | |
1021 | ||
1022 | RELAX_DELAY_SLOT_SIZE_SECOND | |
1023 | Like RELAX_DELAY_SLOT, but indicates that the second implementation of | |
1024 | the macro is of the wrong size for the branch delay slot. | |
1025 | ||
4d7206a2 RS |
1026 | The frag's "opcode" points to the first fixup for relaxable code. |
1027 | ||
1028 | Relaxable macros are generated using a sequence such as: | |
1029 | ||
1030 | relax_start (SYMBOL); | |
1031 | ... generate first expansion ... | |
1032 | relax_switch (); | |
1033 | ... generate second expansion ... | |
1034 | relax_end (); | |
1035 | ||
1036 | The code and fixups for the unwanted alternative are discarded | |
1037 | by md_convert_frag. */ | |
ce8ad872 MR |
1038 | #define RELAX_ENCODE(FIRST, SECOND, PIC) \ |
1039 | (((FIRST) << 8) | (SECOND) | ((PIC) ? 0x10000 : 0)) | |
4d7206a2 | 1040 | |
584892a6 RS |
1041 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
1042 | #define RELAX_SECOND(X) ((X) & 0xff) | |
ce8ad872 MR |
1043 | #define RELAX_PIC(X) (((X) & 0x10000) != 0) |
1044 | #define RELAX_USE_SECOND 0x20000 | |
1045 | #define RELAX_SECOND_LONGER 0x40000 | |
1046 | #define RELAX_NOMACRO 0x80000 | |
1047 | #define RELAX_DELAY_SLOT 0x100000 | |
1048 | #define RELAX_DELAY_SLOT_16BIT 0x200000 | |
1049 | #define RELAX_DELAY_SLOT_SIZE_FIRST 0x400000 | |
1050 | #define RELAX_DELAY_SLOT_SIZE_SECOND 0x800000 | |
252b5132 | 1051 | |
4a6a3df4 AO |
1052 | /* Branch without likely bit. If label is out of range, we turn: |
1053 | ||
134c0c8b | 1054 | beq reg1, reg2, label |
4a6a3df4 AO |
1055 | delay slot |
1056 | ||
1057 | into | |
1058 | ||
1059 | bne reg1, reg2, 0f | |
1060 | nop | |
1061 | j label | |
1062 | 0: delay slot | |
1063 | ||
1064 | with the following opcode replacements: | |
1065 | ||
1066 | beq <-> bne | |
1067 | blez <-> bgtz | |
1068 | bltz <-> bgez | |
1069 | bc1f <-> bc1t | |
1070 | ||
1071 | bltzal <-> bgezal (with jal label instead of j label) | |
1072 | ||
1073 | Even though keeping the delay slot instruction in the delay slot of | |
1074 | the branch would be more efficient, it would be very tricky to do | |
1075 | correctly, because we'd have to introduce a variable frag *after* | |
1076 | the delay slot instruction, and expand that instead. Let's do it | |
1077 | the easy way for now, even if the branch-not-taken case now costs | |
1078 | one additional instruction. Out-of-range branches are not supposed | |
1079 | to be common, anyway. | |
1080 | ||
1081 | Branch likely. If label is out of range, we turn: | |
1082 | ||
1083 | beql reg1, reg2, label | |
1084 | delay slot (annulled if branch not taken) | |
1085 | ||
1086 | into | |
1087 | ||
1088 | beql reg1, reg2, 1f | |
1089 | nop | |
1090 | beql $0, $0, 2f | |
1091 | nop | |
1092 | 1: j[al] label | |
1093 | delay slot (executed only if branch taken) | |
1094 | 2: | |
1095 | ||
1096 | It would be possible to generate a shorter sequence by losing the | |
1097 | likely bit, generating something like: | |
b34976b6 | 1098 | |
4a6a3df4 AO |
1099 | bne reg1, reg2, 0f |
1100 | nop | |
1101 | j[al] label | |
1102 | delay slot (executed only if branch taken) | |
1103 | 0: | |
1104 | ||
1105 | beql -> bne | |
1106 | bnel -> beq | |
1107 | blezl -> bgtz | |
1108 | bgtzl -> blez | |
1109 | bltzl -> bgez | |
1110 | bgezl -> bltz | |
1111 | bc1fl -> bc1t | |
1112 | bc1tl -> bc1f | |
1113 | ||
1114 | bltzall -> bgezal (with jal label instead of j label) | |
1115 | bgezall -> bltzal (ditto) | |
1116 | ||
1117 | ||
1118 | but it's not clear that it would actually improve performance. */ | |
ce8ad872 MR |
1119 | #define RELAX_BRANCH_ENCODE(at, pic, \ |
1120 | uncond, likely, link, toofar) \ | |
66b3e8da MR |
1121 | ((relax_substateT) \ |
1122 | (0xc0000000 \ | |
1123 | | ((at) & 0x1f) \ | |
ce8ad872 MR |
1124 | | ((pic) ? 0x20 : 0) \ |
1125 | | ((toofar) ? 0x40 : 0) \ | |
1126 | | ((link) ? 0x80 : 0) \ | |
1127 | | ((likely) ? 0x100 : 0) \ | |
1128 | | ((uncond) ? 0x200 : 0))) | |
4a6a3df4 | 1129 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
ce8ad872 MR |
1130 | #define RELAX_BRANCH_UNCOND(i) (((i) & 0x200) != 0) |
1131 | #define RELAX_BRANCH_LIKELY(i) (((i) & 0x100) != 0) | |
1132 | #define RELAX_BRANCH_LINK(i) (((i) & 0x80) != 0) | |
1133 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x40) != 0) | |
1134 | #define RELAX_BRANCH_PIC(i) (((i) & 0x20) != 0) | |
66b3e8da | 1135 | #define RELAX_BRANCH_AT(i) ((i) & 0x1f) |
4a6a3df4 | 1136 | |
252b5132 RH |
1137 | /* For mips16 code, we use an entirely different form of relaxation. |
1138 | mips16 supports two versions of most instructions which take | |
1139 | immediate values: a small one which takes some small value, and a | |
1140 | larger one which takes a 16 bit value. Since branches also follow | |
1141 | this pattern, relaxing these values is required. | |
1142 | ||
1143 | We can assemble both mips16 and normal MIPS code in a single | |
1144 | object. Therefore, we need to support this type of relaxation at | |
1145 | the same time that we support the relaxation described above. We | |
1146 | use the high bit of the subtype field to distinguish these cases. | |
1147 | ||
1148 | The information we store for this type of relaxation is the | |
1149 | argument code found in the opcode file for this relocation, whether | |
1150 | the user explicitly requested a small or extended form, and whether | |
1151 | the relocation is in a jump or jal delay slot. That tells us the | |
1152 | size of the value, and how it should be stored. We also store | |
1153 | whether the fragment is considered to be extended or not. We also | |
1154 | store whether this is known to be a branch to a different section, | |
1155 | whether we have tried to relax this frag yet, and whether we have | |
1156 | ever extended a PC relative fragment because of a shift count. */ | |
25499ac7 | 1157 | #define RELAX_MIPS16_ENCODE(type, e2, pic, sym32, nomacro, \ |
8507b6e7 MR |
1158 | small, ext, \ |
1159 | dslot, jal_dslot) \ | |
252b5132 RH |
1160 | (0x80000000 \ |
1161 | | ((type) & 0xff) \ | |
25499ac7 MR |
1162 | | ((e2) ? 0x100 : 0) \ |
1163 | | ((pic) ? 0x200 : 0) \ | |
1164 | | ((sym32) ? 0x400 : 0) \ | |
1165 | | ((nomacro) ? 0x800 : 0) \ | |
1166 | | ((small) ? 0x1000 : 0) \ | |
1167 | | ((ext) ? 0x2000 : 0) \ | |
1168 | | ((dslot) ? 0x4000 : 0) \ | |
1169 | | ((jal_dslot) ? 0x8000 : 0)) | |
8507b6e7 | 1170 | |
4a6a3df4 | 1171 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 | 1172 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
25499ac7 MR |
1173 | #define RELAX_MIPS16_E2(i) (((i) & 0x100) != 0) |
1174 | #define RELAX_MIPS16_PIC(i) (((i) & 0x200) != 0) | |
1175 | #define RELAX_MIPS16_SYM32(i) (((i) & 0x400) != 0) | |
1176 | #define RELAX_MIPS16_NOMACRO(i) (((i) & 0x800) != 0) | |
1177 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x1000) != 0) | |
1178 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x2000) != 0) | |
1179 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x4000) != 0) | |
1180 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x8000) != 0) | |
1181 | ||
1182 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x10000) != 0) | |
1183 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x10000) | |
1184 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) & ~0x10000) | |
1185 | #define RELAX_MIPS16_ALWAYS_EXTENDED(i) (((i) & 0x20000) != 0) | |
1186 | #define RELAX_MIPS16_MARK_ALWAYS_EXTENDED(i) ((i) | 0x20000) | |
1187 | #define RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED(i) ((i) & ~0x20000) | |
1188 | #define RELAX_MIPS16_MACRO(i) (((i) & 0x40000) != 0) | |
1189 | #define RELAX_MIPS16_MARK_MACRO(i) ((i) | 0x40000) | |
1190 | #define RELAX_MIPS16_CLEAR_MACRO(i) ((i) & ~0x40000) | |
885add95 | 1191 | |
df58fc94 RS |
1192 | /* For microMIPS code, we use relaxation similar to one we use for |
1193 | MIPS16 code. Some instructions that take immediate values support | |
1194 | two encodings: a small one which takes some small value, and a | |
1195 | larger one which takes a 16 bit value. As some branches also follow | |
1196 | this pattern, relaxing these values is required. | |
1197 | ||
1198 | We can assemble both microMIPS and normal MIPS code in a single | |
1199 | object. Therefore, we need to support this type of relaxation at | |
1200 | the same time that we support the relaxation described above. We | |
1201 | use one of the high bits of the subtype field to distinguish these | |
1202 | cases. | |
1203 | ||
1204 | The information we store for this type of relaxation is the argument | |
1205 | code found in the opcode file for this relocation, the register | |
8484fb75 MR |
1206 | selected as the assembler temporary, whether in the 32-bit |
1207 | instruction mode, whether the branch is unconditional, whether it is | |
7bd374a4 MR |
1208 | compact, whether there is no delay-slot instruction available to fill |
1209 | in, whether it stores the link address implicitly in $ra, whether | |
1210 | relaxation of out-of-range 32-bit branches to a sequence of | |
8484fb75 MR |
1211 | instructions is enabled, and whether the displacement of a branch is |
1212 | too large to fit as an immediate argument of a 16-bit and a 32-bit | |
1213 | branch, respectively. */ | |
ce8ad872 | 1214 | #define RELAX_MICROMIPS_ENCODE(type, at, insn32, pic, \ |
7bd374a4 | 1215 | uncond, compact, link, nods, \ |
40209cad MR |
1216 | relax32, toofar16, toofar32) \ |
1217 | (0x40000000 \ | |
1218 | | ((type) & 0xff) \ | |
1219 | | (((at) & 0x1f) << 8) \ | |
8484fb75 | 1220 | | ((insn32) ? 0x2000 : 0) \ |
ce8ad872 MR |
1221 | | ((pic) ? 0x4000 : 0) \ |
1222 | | ((uncond) ? 0x8000 : 0) \ | |
1223 | | ((compact) ? 0x10000 : 0) \ | |
1224 | | ((link) ? 0x20000 : 0) \ | |
1225 | | ((nods) ? 0x40000 : 0) \ | |
1226 | | ((relax32) ? 0x80000 : 0) \ | |
1227 | | ((toofar16) ? 0x100000 : 0) \ | |
1228 | | ((toofar32) ? 0x200000 : 0)) | |
df58fc94 RS |
1229 | #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000) |
1230 | #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff) | |
1231 | #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f) | |
8484fb75 | 1232 | #define RELAX_MICROMIPS_INSN32(i) (((i) & 0x2000) != 0) |
ce8ad872 MR |
1233 | #define RELAX_MICROMIPS_PIC(i) (((i) & 0x4000) != 0) |
1234 | #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x8000) != 0) | |
1235 | #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x10000) != 0) | |
1236 | #define RELAX_MICROMIPS_LINK(i) (((i) & 0x20000) != 0) | |
1237 | #define RELAX_MICROMIPS_NODS(i) (((i) & 0x40000) != 0) | |
1238 | #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x80000) != 0) | |
1239 | ||
1240 | #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x100000) != 0) | |
1241 | #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x100000) | |
1242 | #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x100000) | |
1243 | #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x200000) != 0) | |
1244 | #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x200000) | |
1245 | #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x200000) | |
df58fc94 | 1246 | |
43c0598f RS |
1247 | /* Sign-extend 16-bit value X. */ |
1248 | #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000) | |
1249 | ||
885add95 CD |
1250 | /* Is the given value a sign-extended 32-bit value? */ |
1251 | #define IS_SEXT_32BIT_NUM(x) \ | |
1252 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
1253 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
1254 | ||
1255 | /* Is the given value a sign-extended 16-bit value? */ | |
1256 | #define IS_SEXT_16BIT_NUM(x) \ | |
1257 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
1258 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
1259 | ||
df58fc94 RS |
1260 | /* Is the given value a sign-extended 12-bit value? */ |
1261 | #define IS_SEXT_12BIT_NUM(x) \ | |
1262 | (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x)) | |
1263 | ||
7f3c4072 CM |
1264 | /* Is the given value a sign-extended 9-bit value? */ |
1265 | #define IS_SEXT_9BIT_NUM(x) \ | |
1266 | (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x)) | |
1267 | ||
2051e8c4 MR |
1268 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ |
1269 | #define IS_ZEXT_32BIT_NUM(x) \ | |
1270 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
1271 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
1272 | ||
bf12938e RS |
1273 | /* Extract bits MASK << SHIFT from STRUCT and shift them right |
1274 | SHIFT places. */ | |
1275 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
1276 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
1277 | ||
bf12938e | 1278 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ |
df58fc94 RS |
1279 | #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \ |
1280 | (!(MICROMIPS) \ | |
1281 | ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \ | |
1282 | : EXTRACT_BITS ((INSN).insn_opcode, \ | |
1283 | MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD)) | |
bf12938e RS |
1284 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ |
1285 | EXTRACT_BITS ((INSN).insn_opcode, \ | |
1286 | MIPS16OP_MASK_##FIELD, \ | |
1287 | MIPS16OP_SH_##FIELD) | |
5c04167a RS |
1288 | |
1289 | /* The MIPS16 EXTEND opcode, shifted left 16 places. */ | |
1290 | #define MIPS16_EXTEND (0xf000U << 16) | |
4d7206a2 | 1291 | \f |
df58fc94 RS |
1292 | /* Whether or not we are emitting a branch-likely macro. */ |
1293 | static bfd_boolean emit_branch_likely_macro = FALSE; | |
1294 | ||
4d7206a2 RS |
1295 | /* Global variables used when generating relaxable macros. See the |
1296 | comment above RELAX_ENCODE for more details about how relaxation | |
1297 | is used. */ | |
1298 | static struct { | |
1299 | /* 0 if we're not emitting a relaxable macro. | |
1300 | 1 if we're emitting the first of the two relaxation alternatives. | |
1301 | 2 if we're emitting the second alternative. */ | |
1302 | int sequence; | |
1303 | ||
1304 | /* The first relaxable fixup in the current frag. (In other words, | |
1305 | the first fixup that refers to relaxable code.) */ | |
1306 | fixS *first_fixup; | |
1307 | ||
1308 | /* sizes[0] says how many bytes of the first alternative are stored in | |
1309 | the current frag. Likewise sizes[1] for the second alternative. */ | |
1310 | unsigned int sizes[2]; | |
1311 | ||
1312 | /* The symbol on which the choice of sequence depends. */ | |
1313 | symbolS *symbol; | |
1314 | } mips_relax; | |
252b5132 | 1315 | \f |
584892a6 RS |
1316 | /* Global variables used to decide whether a macro needs a warning. */ |
1317 | static struct { | |
1318 | /* True if the macro is in a branch delay slot. */ | |
1319 | bfd_boolean delay_slot_p; | |
1320 | ||
df58fc94 RS |
1321 | /* Set to the length in bytes required if the macro is in a delay slot |
1322 | that requires a specific length of instruction, otherwise zero. */ | |
1323 | unsigned int delay_slot_length; | |
1324 | ||
584892a6 RS |
1325 | /* For relaxable macros, sizes[0] is the length of the first alternative |
1326 | in bytes and sizes[1] is the length of the second alternative. | |
1327 | For non-relaxable macros, both elements give the length of the | |
1328 | macro in bytes. */ | |
1329 | unsigned int sizes[2]; | |
1330 | ||
df58fc94 RS |
1331 | /* For relaxable macros, first_insn_sizes[0] is the length of the first |
1332 | instruction of the first alternative in bytes and first_insn_sizes[1] | |
1333 | is the length of the first instruction of the second alternative. | |
1334 | For non-relaxable macros, both elements give the length of the first | |
1335 | instruction in bytes. | |
1336 | ||
1337 | Set to zero if we haven't yet seen the first instruction. */ | |
1338 | unsigned int first_insn_sizes[2]; | |
1339 | ||
1340 | /* For relaxable macros, insns[0] is the number of instructions for the | |
1341 | first alternative and insns[1] is the number of instructions for the | |
1342 | second alternative. | |
1343 | ||
1344 | For non-relaxable macros, both elements give the number of | |
1345 | instructions for the macro. */ | |
1346 | unsigned int insns[2]; | |
1347 | ||
584892a6 RS |
1348 | /* The first variant frag for this macro. */ |
1349 | fragS *first_frag; | |
1350 | } mips_macro_warning; | |
1351 | \f | |
252b5132 RH |
1352 | /* Prototypes for static functions. */ |
1353 | ||
252b5132 RH |
1354 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; |
1355 | ||
b34976b6 | 1356 | static void append_insn |
df58fc94 RS |
1357 | (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *, |
1358 | bfd_boolean expansionp); | |
7d10b47d | 1359 | static void mips_no_prev_insn (void); |
c67a084a | 1360 | static void macro_build (expressionS *, const char *, const char *, ...); |
b34976b6 | 1361 | static void mips16_macro_build |
03ea81db | 1362 | (expressionS *, const char *, const char *, va_list *); |
67c0d1eb | 1363 | static void load_register (int, expressionS *, int); |
584892a6 RS |
1364 | static void macro_start (void); |
1365 | static void macro_end (void); | |
833794fc | 1366 | static void macro (struct mips_cl_insn *ip, char *str); |
17a2f251 | 1367 | static void mips16_macro (struct mips_cl_insn * ip); |
17a2f251 TS |
1368 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
1369 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
25499ac7 | 1370 | static unsigned long mips16_immed_extend (offsetT, unsigned int); |
b34976b6 | 1371 | static void mips16_immed |
3b4dbbbf | 1372 | (const char *, unsigned int, int, bfd_reloc_code_real_type, offsetT, |
43c0598f | 1373 | unsigned int, unsigned long *); |
5e0116d5 | 1374 | static size_t my_getSmallExpression |
17a2f251 TS |
1375 | (expressionS *, bfd_reloc_code_real_type *, char *); |
1376 | static void my_getExpression (expressionS *, char *); | |
1377 | static void s_align (int); | |
1378 | static void s_change_sec (int); | |
1379 | static void s_change_section (int); | |
1380 | static void s_cons (int); | |
1381 | static void s_float_cons (int); | |
1382 | static void s_mips_globl (int); | |
1383 | static void s_option (int); | |
1384 | static void s_mipsset (int); | |
1385 | static void s_abicalls (int); | |
1386 | static void s_cpload (int); | |
1387 | static void s_cpsetup (int); | |
1388 | static void s_cplocal (int); | |
1389 | static void s_cprestore (int); | |
1390 | static void s_cpreturn (int); | |
741d6ea8 JM |
1391 | static void s_dtprelword (int); |
1392 | static void s_dtpreldword (int); | |
d0f13682 CLT |
1393 | static void s_tprelword (int); |
1394 | static void s_tpreldword (int); | |
17a2f251 TS |
1395 | static void s_gpvalue (int); |
1396 | static void s_gpword (int); | |
1397 | static void s_gpdword (int); | |
a3f278e2 | 1398 | static void s_ehword (int); |
17a2f251 TS |
1399 | static void s_cpadd (int); |
1400 | static void s_insn (int); | |
ba92f887 | 1401 | static void s_nan (int); |
919731af | 1402 | static void s_module (int); |
17a2f251 TS |
1403 | static void s_mips_ent (int); |
1404 | static void s_mips_end (int); | |
1405 | static void s_mips_frame (int); | |
1406 | static void s_mips_mask (int reg_type); | |
1407 | static void s_mips_stab (int); | |
1408 | static void s_mips_weakext (int); | |
1409 | static void s_mips_file (int); | |
1410 | static void s_mips_loc (int); | |
9e009953 | 1411 | static bfd_boolean pic_need_relax (symbolS *); |
4a6a3df4 | 1412 | static int relaxed_branch_length (fragS *, asection *, int); |
df58fc94 RS |
1413 | static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int); |
1414 | static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int); | |
919731af | 1415 | static void file_mips_check_options (void); |
e7af610e NC |
1416 | |
1417 | /* Table and functions used to map between CPU/ISA names, and | |
1418 | ISA levels, and CPU numbers. */ | |
1419 | ||
e972090a NC |
1420 | struct mips_cpu_info |
1421 | { | |
e7af610e | 1422 | const char *name; /* CPU or ISA name. */ |
d16afab6 RS |
1423 | int flags; /* MIPS_CPU_* flags. */ |
1424 | int ase; /* Set of ASEs implemented by the CPU. */ | |
e7af610e NC |
1425 | int isa; /* ISA level. */ |
1426 | int cpu; /* CPU number (default CPU if ISA). */ | |
1427 | }; | |
1428 | ||
ad3fea08 | 1429 | #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ |
ad3fea08 | 1430 | |
17a2f251 TS |
1431 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
1432 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
1433 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 | 1434 | \f |
c31f3936 RS |
1435 | /* Command-line options. */ |
1436 | const char *md_shortopts = "O::g::G:"; | |
1437 | ||
1438 | enum options | |
1439 | { | |
1440 | OPTION_MARCH = OPTION_MD_BASE, | |
1441 | OPTION_MTUNE, | |
1442 | OPTION_MIPS1, | |
1443 | OPTION_MIPS2, | |
1444 | OPTION_MIPS3, | |
1445 | OPTION_MIPS4, | |
1446 | OPTION_MIPS5, | |
1447 | OPTION_MIPS32, | |
1448 | OPTION_MIPS64, | |
1449 | OPTION_MIPS32R2, | |
ae52f483 AB |
1450 | OPTION_MIPS32R3, |
1451 | OPTION_MIPS32R5, | |
7361da2c | 1452 | OPTION_MIPS32R6, |
c31f3936 | 1453 | OPTION_MIPS64R2, |
ae52f483 AB |
1454 | OPTION_MIPS64R3, |
1455 | OPTION_MIPS64R5, | |
7361da2c | 1456 | OPTION_MIPS64R6, |
c31f3936 RS |
1457 | OPTION_MIPS16, |
1458 | OPTION_NO_MIPS16, | |
1459 | OPTION_MIPS3D, | |
1460 | OPTION_NO_MIPS3D, | |
1461 | OPTION_MDMX, | |
1462 | OPTION_NO_MDMX, | |
1463 | OPTION_DSP, | |
1464 | OPTION_NO_DSP, | |
1465 | OPTION_MT, | |
1466 | OPTION_NO_MT, | |
1467 | OPTION_VIRT, | |
1468 | OPTION_NO_VIRT, | |
56d438b1 CF |
1469 | OPTION_MSA, |
1470 | OPTION_NO_MSA, | |
c31f3936 RS |
1471 | OPTION_SMARTMIPS, |
1472 | OPTION_NO_SMARTMIPS, | |
1473 | OPTION_DSPR2, | |
1474 | OPTION_NO_DSPR2, | |
8f4f9071 MF |
1475 | OPTION_DSPR3, |
1476 | OPTION_NO_DSPR3, | |
c31f3936 RS |
1477 | OPTION_EVA, |
1478 | OPTION_NO_EVA, | |
7d64c587 AB |
1479 | OPTION_XPA, |
1480 | OPTION_NO_XPA, | |
c31f3936 RS |
1481 | OPTION_MICROMIPS, |
1482 | OPTION_NO_MICROMIPS, | |
1483 | OPTION_MCU, | |
1484 | OPTION_NO_MCU, | |
25499ac7 MR |
1485 | OPTION_MIPS16E2, |
1486 | OPTION_NO_MIPS16E2, | |
730c3174 SE |
1487 | OPTION_CRC, |
1488 | OPTION_NO_CRC, | |
c31f3936 RS |
1489 | OPTION_M4650, |
1490 | OPTION_NO_M4650, | |
1491 | OPTION_M4010, | |
1492 | OPTION_NO_M4010, | |
1493 | OPTION_M4100, | |
1494 | OPTION_NO_M4100, | |
1495 | OPTION_M3900, | |
1496 | OPTION_NO_M3900, | |
1497 | OPTION_M7000_HILO_FIX, | |
1498 | OPTION_MNO_7000_HILO_FIX, | |
1499 | OPTION_FIX_24K, | |
1500 | OPTION_NO_FIX_24K, | |
a8d14a88 CM |
1501 | OPTION_FIX_RM7000, |
1502 | OPTION_NO_FIX_RM7000, | |
6f2117ba PH |
1503 | OPTION_FIX_LOONGSON3_LLSC, |
1504 | OPTION_NO_FIX_LOONGSON3_LLSC, | |
c31f3936 RS |
1505 | OPTION_FIX_LOONGSON2F_JUMP, |
1506 | OPTION_NO_FIX_LOONGSON2F_JUMP, | |
1507 | OPTION_FIX_LOONGSON2F_NOP, | |
1508 | OPTION_NO_FIX_LOONGSON2F_NOP, | |
1509 | OPTION_FIX_VR4120, | |
1510 | OPTION_NO_FIX_VR4120, | |
1511 | OPTION_FIX_VR4130, | |
1512 | OPTION_NO_FIX_VR4130, | |
1513 | OPTION_FIX_CN63XXP1, | |
1514 | OPTION_NO_FIX_CN63XXP1, | |
27c634e0 FN |
1515 | OPTION_FIX_R5900, |
1516 | OPTION_NO_FIX_R5900, | |
c31f3936 RS |
1517 | OPTION_TRAP, |
1518 | OPTION_BREAK, | |
1519 | OPTION_EB, | |
1520 | OPTION_EL, | |
1521 | OPTION_FP32, | |
1522 | OPTION_GP32, | |
1523 | OPTION_CONSTRUCT_FLOATS, | |
1524 | OPTION_NO_CONSTRUCT_FLOATS, | |
1525 | OPTION_FP64, | |
351cdf24 | 1526 | OPTION_FPXX, |
c31f3936 RS |
1527 | OPTION_GP64, |
1528 | OPTION_RELAX_BRANCH, | |
1529 | OPTION_NO_RELAX_BRANCH, | |
8b10b0b3 MR |
1530 | OPTION_IGNORE_BRANCH_ISA, |
1531 | OPTION_NO_IGNORE_BRANCH_ISA, | |
833794fc MR |
1532 | OPTION_INSN32, |
1533 | OPTION_NO_INSN32, | |
c31f3936 RS |
1534 | OPTION_MSHARED, |
1535 | OPTION_MNO_SHARED, | |
1536 | OPTION_MSYM32, | |
1537 | OPTION_MNO_SYM32, | |
1538 | OPTION_SOFT_FLOAT, | |
1539 | OPTION_HARD_FLOAT, | |
1540 | OPTION_SINGLE_FLOAT, | |
1541 | OPTION_DOUBLE_FLOAT, | |
1542 | OPTION_32, | |
c31f3936 RS |
1543 | OPTION_CALL_SHARED, |
1544 | OPTION_CALL_NONPIC, | |
1545 | OPTION_NON_SHARED, | |
1546 | OPTION_XGOT, | |
1547 | OPTION_MABI, | |
1548 | OPTION_N32, | |
1549 | OPTION_64, | |
1550 | OPTION_MDEBUG, | |
1551 | OPTION_NO_MDEBUG, | |
1552 | OPTION_PDR, | |
1553 | OPTION_NO_PDR, | |
1554 | OPTION_MVXWORKS_PIC, | |
ba92f887 | 1555 | OPTION_NAN, |
351cdf24 MF |
1556 | OPTION_ODD_SPREG, |
1557 | OPTION_NO_ODD_SPREG, | |
6f20c942 FS |
1558 | OPTION_GINV, |
1559 | OPTION_NO_GINV, | |
8095d2f7 CX |
1560 | OPTION_LOONGSON_MMI, |
1561 | OPTION_NO_LOONGSON_MMI, | |
716c08de CX |
1562 | OPTION_LOONGSON_CAM, |
1563 | OPTION_NO_LOONGSON_CAM, | |
bdc6c06e CX |
1564 | OPTION_LOONGSON_EXT, |
1565 | OPTION_NO_LOONGSON_EXT, | |
a693765e CX |
1566 | OPTION_LOONGSON_EXT2, |
1567 | OPTION_NO_LOONGSON_EXT2, | |
c31f3936 RS |
1568 | OPTION_END_OF_ENUM |
1569 | }; | |
1570 | ||
1571 | struct option md_longopts[] = | |
1572 | { | |
1573 | /* Options which specify architecture. */ | |
1574 | {"march", required_argument, NULL, OPTION_MARCH}, | |
1575 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
1576 | {"mips0", no_argument, NULL, OPTION_MIPS1}, | |
1577 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
1578 | {"mips2", no_argument, NULL, OPTION_MIPS2}, | |
1579 | {"mips3", no_argument, NULL, OPTION_MIPS3}, | |
1580 | {"mips4", no_argument, NULL, OPTION_MIPS4}, | |
1581 | {"mips5", no_argument, NULL, OPTION_MIPS5}, | |
1582 | {"mips32", no_argument, NULL, OPTION_MIPS32}, | |
1583 | {"mips64", no_argument, NULL, OPTION_MIPS64}, | |
1584 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, | |
ae52f483 AB |
1585 | {"mips32r3", no_argument, NULL, OPTION_MIPS32R3}, |
1586 | {"mips32r5", no_argument, NULL, OPTION_MIPS32R5}, | |
7361da2c | 1587 | {"mips32r6", no_argument, NULL, OPTION_MIPS32R6}, |
c31f3936 | 1588 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, |
ae52f483 AB |
1589 | {"mips64r3", no_argument, NULL, OPTION_MIPS64R3}, |
1590 | {"mips64r5", no_argument, NULL, OPTION_MIPS64R5}, | |
7361da2c | 1591 | {"mips64r6", no_argument, NULL, OPTION_MIPS64R6}, |
c31f3936 RS |
1592 | |
1593 | /* Options which specify Application Specific Extensions (ASEs). */ | |
1594 | {"mips16", no_argument, NULL, OPTION_MIPS16}, | |
1595 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, | |
1596 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, | |
1597 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, | |
1598 | {"mdmx", no_argument, NULL, OPTION_MDMX}, | |
1599 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, | |
1600 | {"mdsp", no_argument, NULL, OPTION_DSP}, | |
1601 | {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, | |
1602 | {"mmt", no_argument, NULL, OPTION_MT}, | |
1603 | {"mno-mt", no_argument, NULL, OPTION_NO_MT}, | |
1604 | {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS}, | |
1605 | {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS}, | |
1606 | {"mdspr2", no_argument, NULL, OPTION_DSPR2}, | |
1607 | {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2}, | |
8f4f9071 MF |
1608 | {"mdspr3", no_argument, NULL, OPTION_DSPR3}, |
1609 | {"mno-dspr3", no_argument, NULL, OPTION_NO_DSPR3}, | |
c31f3936 RS |
1610 | {"meva", no_argument, NULL, OPTION_EVA}, |
1611 | {"mno-eva", no_argument, NULL, OPTION_NO_EVA}, | |
1612 | {"mmicromips", no_argument, NULL, OPTION_MICROMIPS}, | |
1613 | {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS}, | |
1614 | {"mmcu", no_argument, NULL, OPTION_MCU}, | |
1615 | {"mno-mcu", no_argument, NULL, OPTION_NO_MCU}, | |
1616 | {"mvirt", no_argument, NULL, OPTION_VIRT}, | |
1617 | {"mno-virt", no_argument, NULL, OPTION_NO_VIRT}, | |
56d438b1 CF |
1618 | {"mmsa", no_argument, NULL, OPTION_MSA}, |
1619 | {"mno-msa", no_argument, NULL, OPTION_NO_MSA}, | |
7d64c587 AB |
1620 | {"mxpa", no_argument, NULL, OPTION_XPA}, |
1621 | {"mno-xpa", no_argument, NULL, OPTION_NO_XPA}, | |
25499ac7 MR |
1622 | {"mmips16e2", no_argument, NULL, OPTION_MIPS16E2}, |
1623 | {"mno-mips16e2", no_argument, NULL, OPTION_NO_MIPS16E2}, | |
730c3174 SE |
1624 | {"mcrc", no_argument, NULL, OPTION_CRC}, |
1625 | {"mno-crc", no_argument, NULL, OPTION_NO_CRC}, | |
6f20c942 FS |
1626 | {"mginv", no_argument, NULL, OPTION_GINV}, |
1627 | {"mno-ginv", no_argument, NULL, OPTION_NO_GINV}, | |
8095d2f7 CX |
1628 | {"mloongson-mmi", no_argument, NULL, OPTION_LOONGSON_MMI}, |
1629 | {"mno-loongson-mmi", no_argument, NULL, OPTION_NO_LOONGSON_MMI}, | |
716c08de CX |
1630 | {"mloongson-cam", no_argument, NULL, OPTION_LOONGSON_CAM}, |
1631 | {"mno-loongson-cam", no_argument, NULL, OPTION_NO_LOONGSON_CAM}, | |
bdc6c06e CX |
1632 | {"mloongson-ext", no_argument, NULL, OPTION_LOONGSON_EXT}, |
1633 | {"mno-loongson-ext", no_argument, NULL, OPTION_NO_LOONGSON_EXT}, | |
a693765e CX |
1634 | {"mloongson-ext2", no_argument, NULL, OPTION_LOONGSON_EXT2}, |
1635 | {"mno-loongson-ext2", no_argument, NULL, OPTION_NO_LOONGSON_EXT2}, | |
c31f3936 RS |
1636 | |
1637 | /* Old-style architecture options. Don't add more of these. */ | |
1638 | {"m4650", no_argument, NULL, OPTION_M4650}, | |
1639 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, | |
1640 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
1641 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
1642 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
1643 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
1644 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
1645 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
1646 | ||
1647 | /* Options which enable bug fixes. */ | |
1648 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, | |
1649 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
1650 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
6f2117ba PH |
1651 | {"mfix-loongson3-llsc", no_argument, NULL, OPTION_FIX_LOONGSON3_LLSC}, |
1652 | {"mno-fix-loongson3-llsc", no_argument, NULL, OPTION_NO_FIX_LOONGSON3_LLSC}, | |
c31f3936 RS |
1653 | {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP}, |
1654 | {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP}, | |
1655 | {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP}, | |
1656 | {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP}, | |
1657 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, | |
1658 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
1659 | {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, | |
1660 | {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, | |
1661 | {"mfix-24k", no_argument, NULL, OPTION_FIX_24K}, | |
1662 | {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K}, | |
a8d14a88 CM |
1663 | {"mfix-rm7000", no_argument, NULL, OPTION_FIX_RM7000}, |
1664 | {"mno-fix-rm7000", no_argument, NULL, OPTION_NO_FIX_RM7000}, | |
c31f3936 RS |
1665 | {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1}, |
1666 | {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1}, | |
27c634e0 FN |
1667 | {"mfix-r5900", no_argument, NULL, OPTION_FIX_R5900}, |
1668 | {"mno-fix-r5900", no_argument, NULL, OPTION_NO_FIX_R5900}, | |
c31f3936 RS |
1669 | |
1670 | /* Miscellaneous options. */ | |
1671 | {"trap", no_argument, NULL, OPTION_TRAP}, | |
1672 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
1673 | {"break", no_argument, NULL, OPTION_BREAK}, | |
1674 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
1675 | {"EB", no_argument, NULL, OPTION_EB}, | |
1676 | {"EL", no_argument, NULL, OPTION_EL}, | |
1677 | {"mfp32", no_argument, NULL, OPTION_FP32}, | |
1678 | {"mgp32", no_argument, NULL, OPTION_GP32}, | |
1679 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, | |
1680 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, | |
1681 | {"mfp64", no_argument, NULL, OPTION_FP64}, | |
351cdf24 | 1682 | {"mfpxx", no_argument, NULL, OPTION_FPXX}, |
c31f3936 RS |
1683 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
1684 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, | |
1685 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
8b10b0b3 MR |
1686 | {"mignore-branch-isa", no_argument, NULL, OPTION_IGNORE_BRANCH_ISA}, |
1687 | {"mno-ignore-branch-isa", no_argument, NULL, OPTION_NO_IGNORE_BRANCH_ISA}, | |
833794fc MR |
1688 | {"minsn32", no_argument, NULL, OPTION_INSN32}, |
1689 | {"mno-insn32", no_argument, NULL, OPTION_NO_INSN32}, | |
c31f3936 RS |
1690 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
1691 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
1692 | {"msym32", no_argument, NULL, OPTION_MSYM32}, | |
1693 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, | |
1694 | {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT}, | |
1695 | {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT}, | |
1696 | {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT}, | |
1697 | {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT}, | |
351cdf24 MF |
1698 | {"modd-spreg", no_argument, NULL, OPTION_ODD_SPREG}, |
1699 | {"mno-odd-spreg", no_argument, NULL, OPTION_NO_ODD_SPREG}, | |
c31f3936 RS |
1700 | |
1701 | /* Strictly speaking this next option is ELF specific, | |
1702 | but we allow it for other ports as well in order to | |
1703 | make testing easier. */ | |
1704 | {"32", no_argument, NULL, OPTION_32}, | |
1705 | ||
1706 | /* ELF-specific options. */ | |
c31f3936 RS |
1707 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
1708 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
1709 | {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC}, | |
1710 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, | |
1711 | {"xgot", no_argument, NULL, OPTION_XGOT}, | |
1712 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
1713 | {"n32", no_argument, NULL, OPTION_N32}, | |
1714 | {"64", no_argument, NULL, OPTION_64}, | |
1715 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, | |
1716 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, | |
1717 | {"mpdr", no_argument, NULL, OPTION_PDR}, | |
1718 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, | |
1719 | {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, | |
ba92f887 | 1720 | {"mnan", required_argument, NULL, OPTION_NAN}, |
c31f3936 RS |
1721 | |
1722 | {NULL, no_argument, NULL, 0} | |
1723 | }; | |
1724 | size_t md_longopts_size = sizeof (md_longopts); | |
1725 | \f | |
c6278170 RS |
1726 | /* Information about either an Application Specific Extension or an |
1727 | optional architecture feature that, for simplicity, we treat in the | |
1728 | same way as an ASE. */ | |
1729 | struct mips_ase | |
1730 | { | |
1731 | /* The name of the ASE, used in both the command-line and .set options. */ | |
1732 | const char *name; | |
1733 | ||
1734 | /* The associated ASE_* flags. If the ASE is available on both 32-bit | |
1735 | and 64-bit architectures, the flags here refer to the subset that | |
1736 | is available on both. */ | |
1737 | unsigned int flags; | |
1738 | ||
1739 | /* The ASE_* flag used for instructions that are available on 64-bit | |
1740 | architectures but that are not included in FLAGS. */ | |
1741 | unsigned int flags64; | |
1742 | ||
1743 | /* The command-line options that turn the ASE on and off. */ | |
1744 | int option_on; | |
1745 | int option_off; | |
1746 | ||
1747 | /* The minimum required architecture revisions for MIPS32, MIPS64, | |
1748 | microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */ | |
1749 | int mips32_rev; | |
1750 | int mips64_rev; | |
1751 | int micromips32_rev; | |
1752 | int micromips64_rev; | |
7361da2c AB |
1753 | |
1754 | /* The architecture where the ASE was removed or -1 if the extension has not | |
1755 | been removed. */ | |
1756 | int rem_rev; | |
c6278170 RS |
1757 | }; |
1758 | ||
1759 | /* A table of all supported ASEs. */ | |
1760 | static const struct mips_ase mips_ases[] = { | |
1761 | { "dsp", ASE_DSP, ASE_DSP64, | |
1762 | OPTION_DSP, OPTION_NO_DSP, | |
7361da2c AB |
1763 | 2, 2, 2, 2, |
1764 | -1 }, | |
c6278170 RS |
1765 | |
1766 | { "dspr2", ASE_DSP | ASE_DSPR2, 0, | |
1767 | OPTION_DSPR2, OPTION_NO_DSPR2, | |
7361da2c AB |
1768 | 2, 2, 2, 2, |
1769 | -1 }, | |
c6278170 | 1770 | |
8f4f9071 MF |
1771 | { "dspr3", ASE_DSP | ASE_DSPR2 | ASE_DSPR3, 0, |
1772 | OPTION_DSPR3, OPTION_NO_DSPR3, | |
1773 | 6, 6, -1, -1, | |
1774 | -1 }, | |
1775 | ||
c6278170 RS |
1776 | { "eva", ASE_EVA, 0, |
1777 | OPTION_EVA, OPTION_NO_EVA, | |
7361da2c AB |
1778 | 2, 2, 2, 2, |
1779 | -1 }, | |
c6278170 RS |
1780 | |
1781 | { "mcu", ASE_MCU, 0, | |
1782 | OPTION_MCU, OPTION_NO_MCU, | |
7361da2c AB |
1783 | 2, 2, 2, 2, |
1784 | -1 }, | |
c6278170 RS |
1785 | |
1786 | /* Deprecated in MIPS64r5, but we don't implement that yet. */ | |
1787 | { "mdmx", ASE_MDMX, 0, | |
1788 | OPTION_MDMX, OPTION_NO_MDMX, | |
7361da2c AB |
1789 | -1, 1, -1, -1, |
1790 | 6 }, | |
c6278170 RS |
1791 | |
1792 | /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */ | |
1793 | { "mips3d", ASE_MIPS3D, 0, | |
1794 | OPTION_MIPS3D, OPTION_NO_MIPS3D, | |
7361da2c AB |
1795 | 2, 1, -1, -1, |
1796 | 6 }, | |
c6278170 RS |
1797 | |
1798 | { "mt", ASE_MT, 0, | |
1799 | OPTION_MT, OPTION_NO_MT, | |
7361da2c AB |
1800 | 2, 2, -1, -1, |
1801 | -1 }, | |
c6278170 RS |
1802 | |
1803 | { "smartmips", ASE_SMARTMIPS, 0, | |
1804 | OPTION_SMARTMIPS, OPTION_NO_SMARTMIPS, | |
7361da2c AB |
1805 | 1, -1, -1, -1, |
1806 | 6 }, | |
c6278170 RS |
1807 | |
1808 | { "virt", ASE_VIRT, ASE_VIRT64, | |
1809 | OPTION_VIRT, OPTION_NO_VIRT, | |
7361da2c AB |
1810 | 2, 2, 2, 2, |
1811 | -1 }, | |
56d438b1 CF |
1812 | |
1813 | { "msa", ASE_MSA, ASE_MSA64, | |
1814 | OPTION_MSA, OPTION_NO_MSA, | |
7361da2c AB |
1815 | 2, 2, 2, 2, |
1816 | -1 }, | |
7d64c587 AB |
1817 | |
1818 | { "xpa", ASE_XPA, 0, | |
1819 | OPTION_XPA, OPTION_NO_XPA, | |
909b4e3d | 1820 | 2, 2, 2, 2, |
7361da2c | 1821 | -1 }, |
25499ac7 MR |
1822 | |
1823 | { "mips16e2", ASE_MIPS16E2, 0, | |
1824 | OPTION_MIPS16E2, OPTION_NO_MIPS16E2, | |
1825 | 2, 2, -1, -1, | |
1826 | 6 }, | |
730c3174 SE |
1827 | |
1828 | { "crc", ASE_CRC, ASE_CRC64, | |
1829 | OPTION_CRC, OPTION_NO_CRC, | |
1830 | 6, 6, -1, -1, | |
1831 | -1 }, | |
6f20c942 FS |
1832 | |
1833 | { "ginv", ASE_GINV, 0, | |
1834 | OPTION_GINV, OPTION_NO_GINV, | |
1835 | 6, 6, 6, 6, | |
1836 | -1 }, | |
8095d2f7 CX |
1837 | |
1838 | { "loongson-mmi", ASE_LOONGSON_MMI, 0, | |
1839 | OPTION_LOONGSON_MMI, OPTION_NO_LOONGSON_MMI, | |
1840 | 0, 0, -1, -1, | |
1841 | -1 }, | |
716c08de CX |
1842 | |
1843 | { "loongson-cam", ASE_LOONGSON_CAM, 0, | |
1844 | OPTION_LOONGSON_CAM, OPTION_NO_LOONGSON_CAM, | |
1845 | 0, 0, -1, -1, | |
1846 | -1 }, | |
bdc6c06e CX |
1847 | |
1848 | { "loongson-ext", ASE_LOONGSON_EXT, 0, | |
1849 | OPTION_LOONGSON_EXT, OPTION_NO_LOONGSON_EXT, | |
1850 | 0, 0, -1, -1, | |
1851 | -1 }, | |
a693765e CX |
1852 | |
1853 | { "loongson-ext2", ASE_LOONGSON_EXT | ASE_LOONGSON_EXT2, 0, | |
1854 | OPTION_LOONGSON_EXT2, OPTION_NO_LOONGSON_EXT2, | |
1855 | 0, 0, -1, -1, | |
1856 | -1 }, | |
c6278170 RS |
1857 | }; |
1858 | ||
1859 | /* The set of ASEs that require -mfp64. */ | |
82bda27b | 1860 | #define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA) |
c6278170 RS |
1861 | |
1862 | /* Groups of ASE_* flags that represent different revisions of an ASE. */ | |
1863 | static const unsigned int mips_ase_groups[] = { | |
a693765e CX |
1864 | ASE_DSP | ASE_DSPR2 | ASE_DSPR3, |
1865 | ASE_LOONGSON_EXT | ASE_LOONGSON_EXT2 | |
c6278170 RS |
1866 | }; |
1867 | \f | |
252b5132 RH |
1868 | /* Pseudo-op table. |
1869 | ||
1870 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
1871 | should be defined here, but are currently unsupported: .alias, | |
1872 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
1873 | ||
1874 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1875 | specific to the type of debugging information being generated, and | |
1876 | should be defined by the object format: .aent, .begin, .bend, | |
1877 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
1878 | .vreg. | |
1879 | ||
1880 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1881 | not MIPS CPU specific, but are also not specific to the object file | |
1882 | format. This file is probably the best place to define them, but | |
d84bcf09 | 1883 | they are not currently supported: .asm0, .endr, .lab, .struct. */ |
252b5132 | 1884 | |
e972090a NC |
1885 | static const pseudo_typeS mips_pseudo_table[] = |
1886 | { | |
beae10d5 | 1887 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1888 | {"option", s_option, 0}, |
1889 | {"set", s_mipsset, 0}, | |
1890 | {"rdata", s_change_sec, 'r'}, | |
1891 | {"sdata", s_change_sec, 's'}, | |
1892 | {"livereg", s_ignore, 0}, | |
1893 | {"abicalls", s_abicalls, 0}, | |
1894 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1895 | {"cpsetup", s_cpsetup, 0}, |
1896 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1897 | {"cprestore", s_cprestore, 0}, |
6478892d | 1898 | {"cpreturn", s_cpreturn, 0}, |
741d6ea8 JM |
1899 | {"dtprelword", s_dtprelword, 0}, |
1900 | {"dtpreldword", s_dtpreldword, 0}, | |
d0f13682 CLT |
1901 | {"tprelword", s_tprelword, 0}, |
1902 | {"tpreldword", s_tpreldword, 0}, | |
6478892d | 1903 | {"gpvalue", s_gpvalue, 0}, |
252b5132 | 1904 | {"gpword", s_gpword, 0}, |
10181a0d | 1905 | {"gpdword", s_gpdword, 0}, |
a3f278e2 | 1906 | {"ehword", s_ehword, 0}, |
252b5132 RH |
1907 | {"cpadd", s_cpadd, 0}, |
1908 | {"insn", s_insn, 0}, | |
ba92f887 | 1909 | {"nan", s_nan, 0}, |
919731af | 1910 | {"module", s_module, 0}, |
252b5132 | 1911 | |
beae10d5 | 1912 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 | 1913 | chips. */ |
38a57ae7 | 1914 | {"asciiz", stringer, 8 + 1}, |
252b5132 RH |
1915 | {"bss", s_change_sec, 'b'}, |
1916 | {"err", s_err, 0}, | |
1917 | {"half", s_cons, 1}, | |
1918 | {"dword", s_cons, 3}, | |
1919 | {"weakext", s_mips_weakext, 0}, | |
7c752c2a TS |
1920 | {"origin", s_org, 0}, |
1921 | {"repeat", s_rept, 0}, | |
252b5132 | 1922 | |
998b3c36 MR |
1923 | /* For MIPS this is non-standard, but we define it for consistency. */ |
1924 | {"sbss", s_change_sec, 'B'}, | |
1925 | ||
beae10d5 | 1926 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1927 | here for one reason or another. */ |
1928 | {"align", s_align, 0}, | |
1929 | {"byte", s_cons, 0}, | |
1930 | {"data", s_change_sec, 'd'}, | |
1931 | {"double", s_float_cons, 'd'}, | |
1932 | {"float", s_float_cons, 'f'}, | |
1933 | {"globl", s_mips_globl, 0}, | |
1934 | {"global", s_mips_globl, 0}, | |
1935 | {"hword", s_cons, 1}, | |
1936 | {"int", s_cons, 2}, | |
1937 | {"long", s_cons, 2}, | |
1938 | {"octa", s_cons, 4}, | |
1939 | {"quad", s_cons, 3}, | |
cca86cc8 | 1940 | {"section", s_change_section, 0}, |
252b5132 RH |
1941 | {"short", s_cons, 1}, |
1942 | {"single", s_float_cons, 'f'}, | |
754e2bb9 | 1943 | {"stabd", s_mips_stab, 'd'}, |
252b5132 | 1944 | {"stabn", s_mips_stab, 'n'}, |
754e2bb9 | 1945 | {"stabs", s_mips_stab, 's'}, |
252b5132 RH |
1946 | {"text", s_change_sec, 't'}, |
1947 | {"word", s_cons, 2}, | |
add56521 | 1948 | |
add56521 | 1949 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1950 | |
43841e91 | 1951 | { NULL, NULL, 0 }, |
252b5132 RH |
1952 | }; |
1953 | ||
e972090a NC |
1954 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1955 | { | |
beae10d5 KH |
1956 | /* These pseudo-ops should be defined by the object file format. |
1957 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1958 | {"aent", s_mips_ent, 1}, |
1959 | {"bgnb", s_ignore, 0}, | |
1960 | {"end", s_mips_end, 0}, | |
1961 | {"endb", s_ignore, 0}, | |
1962 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1963 | {"file", s_mips_file, 0}, |
252b5132 RH |
1964 | {"fmask", s_mips_mask, 'F'}, |
1965 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1966 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1967 | {"mask", s_mips_mask, 'R'}, |
1968 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1969 | { NULL, NULL, 0 }, |
252b5132 RH |
1970 | }; |
1971 | ||
3ae8dd8d MR |
1972 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
1973 | purpose of the `.dc.a' internal pseudo-op. */ | |
1974 | ||
1975 | int | |
1976 | mips_address_bytes (void) | |
1977 | { | |
919731af | 1978 | file_mips_check_options (); |
3ae8dd8d MR |
1979 | return HAVE_64BIT_ADDRESSES ? 8 : 4; |
1980 | } | |
1981 | ||
17a2f251 | 1982 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1983 | |
1984 | void | |
17a2f251 | 1985 | mips_pop_insert (void) |
252b5132 RH |
1986 | { |
1987 | pop_insert (mips_pseudo_table); | |
1988 | if (! ECOFF_DEBUGGING) | |
1989 | pop_insert (mips_nonecoff_pseudo_table); | |
1990 | } | |
1991 | \f | |
1992 | /* Symbols labelling the current insn. */ | |
1993 | ||
e972090a NC |
1994 | struct insn_label_list |
1995 | { | |
252b5132 RH |
1996 | struct insn_label_list *next; |
1997 | symbolS *label; | |
1998 | }; | |
1999 | ||
252b5132 | 2000 | static struct insn_label_list *free_insn_labels; |
742a56fe | 2001 | #define label_list tc_segment_info_data.labels |
252b5132 | 2002 | |
17a2f251 | 2003 | static void mips_clear_insn_labels (void); |
df58fc94 RS |
2004 | static void mips_mark_labels (void); |
2005 | static void mips_compressed_mark_labels (void); | |
252b5132 RH |
2006 | |
2007 | static inline void | |
17a2f251 | 2008 | mips_clear_insn_labels (void) |
252b5132 | 2009 | { |
ed9e98c2 | 2010 | struct insn_label_list **pl; |
a8dbcb85 | 2011 | segment_info_type *si; |
252b5132 | 2012 | |
a8dbcb85 TS |
2013 | if (now_seg) |
2014 | { | |
2015 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
2016 | ; | |
3739860c | 2017 | |
a8dbcb85 TS |
2018 | si = seg_info (now_seg); |
2019 | *pl = si->label_list; | |
2020 | si->label_list = NULL; | |
2021 | } | |
252b5132 | 2022 | } |
a8dbcb85 | 2023 | |
df58fc94 RS |
2024 | /* Mark instruction labels in MIPS16/microMIPS mode. */ |
2025 | ||
2026 | static inline void | |
2027 | mips_mark_labels (void) | |
2028 | { | |
2029 | if (HAVE_CODE_COMPRESSION) | |
2030 | mips_compressed_mark_labels (); | |
2031 | } | |
252b5132 RH |
2032 | \f |
2033 | static char *expr_end; | |
2034 | ||
e423441d | 2035 | /* An expression in a macro instruction. This is set by mips_ip and |
b0e6f033 | 2036 | mips16_ip and when populated is always an O_constant. */ |
252b5132 RH |
2037 | |
2038 | static expressionS imm_expr; | |
252b5132 | 2039 | |
77bd4346 RS |
2040 | /* The relocatable field in an instruction and the relocs associated |
2041 | with it. These variables are used for instructions like LUI and | |
2042 | JAL as well as true offsets. They are also used for address | |
2043 | operands in macros. */ | |
252b5132 | 2044 | |
77bd4346 | 2045 | static expressionS offset_expr; |
f6688943 TS |
2046 | static bfd_reloc_code_real_type offset_reloc[3] |
2047 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 2048 | |
df58fc94 RS |
2049 | /* This is set to the resulting size of the instruction to be produced |
2050 | by mips16_ip if an explicit extension is used or by mips_ip if an | |
2051 | explicit size is supplied. */ | |
252b5132 | 2052 | |
df58fc94 | 2053 | static unsigned int forced_insn_length; |
252b5132 | 2054 | |
e1b47bd5 RS |
2055 | /* True if we are assembling an instruction. All dot symbols defined during |
2056 | this time should be treated as code labels. */ | |
2057 | ||
2058 | static bfd_boolean mips_assembling_insn; | |
2059 | ||
ecb4347a DJ |
2060 | /* The pdr segment for per procedure frame/regmask info. Not used for |
2061 | ECOFF debugging. */ | |
252b5132 RH |
2062 | |
2063 | static segT pdr_seg; | |
252b5132 | 2064 | |
e013f690 TS |
2065 | /* The default target format to use. */ |
2066 | ||
aeffff67 RS |
2067 | #if defined (TE_FreeBSD) |
2068 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd" | |
2069 | #elif defined (TE_TMIPS) | |
2070 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips" | |
2071 | #else | |
2072 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips" | |
2073 | #endif | |
2074 | ||
e013f690 | 2075 | const char * |
17a2f251 | 2076 | mips_target_format (void) |
e013f690 TS |
2077 | { |
2078 | switch (OUTPUT_FLAVOR) | |
2079 | { | |
e013f690 | 2080 | case bfd_target_elf_flavour: |
0a44bf69 RS |
2081 | #ifdef TE_VXWORKS |
2082 | if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI) | |
2083 | return (target_big_endian | |
2084 | ? "elf32-bigmips-vxworks" | |
2085 | : "elf32-littlemips-vxworks"); | |
2086 | #endif | |
e013f690 | 2087 | return (target_big_endian |
cfe86eaa | 2088 | ? (HAVE_64BIT_OBJECTS |
aeffff67 | 2089 | ? ELF_TARGET ("elf64-", "big") |
cfe86eaa | 2090 | : (HAVE_NEWABI |
aeffff67 RS |
2091 | ? ELF_TARGET ("elf32-n", "big") |
2092 | : ELF_TARGET ("elf32-", "big"))) | |
cfe86eaa | 2093 | : (HAVE_64BIT_OBJECTS |
aeffff67 | 2094 | ? ELF_TARGET ("elf64-", "little") |
cfe86eaa | 2095 | : (HAVE_NEWABI |
aeffff67 RS |
2096 | ? ELF_TARGET ("elf32-n", "little") |
2097 | : ELF_TARGET ("elf32-", "little")))); | |
e013f690 TS |
2098 | default: |
2099 | abort (); | |
2100 | return NULL; | |
2101 | } | |
2102 | } | |
2103 | ||
c6278170 RS |
2104 | /* Return the ISA revision that is currently in use, or 0 if we are |
2105 | generating code for MIPS V or below. */ | |
2106 | ||
2107 | static int | |
2108 | mips_isa_rev (void) | |
2109 | { | |
2110 | if (mips_opts.isa == ISA_MIPS32R2 || mips_opts.isa == ISA_MIPS64R2) | |
2111 | return 2; | |
2112 | ||
ae52f483 AB |
2113 | if (mips_opts.isa == ISA_MIPS32R3 || mips_opts.isa == ISA_MIPS64R3) |
2114 | return 3; | |
2115 | ||
2116 | if (mips_opts.isa == ISA_MIPS32R5 || mips_opts.isa == ISA_MIPS64R5) | |
2117 | return 5; | |
2118 | ||
7361da2c AB |
2119 | if (mips_opts.isa == ISA_MIPS32R6 || mips_opts.isa == ISA_MIPS64R6) |
2120 | return 6; | |
2121 | ||
c6278170 RS |
2122 | /* microMIPS implies revision 2 or above. */ |
2123 | if (mips_opts.micromips) | |
2124 | return 2; | |
2125 | ||
2126 | if (mips_opts.isa == ISA_MIPS32 || mips_opts.isa == ISA_MIPS64) | |
2127 | return 1; | |
2128 | ||
2129 | return 0; | |
2130 | } | |
2131 | ||
2132 | /* Return the mask of all ASEs that are revisions of those in FLAGS. */ | |
2133 | ||
2134 | static unsigned int | |
2135 | mips_ase_mask (unsigned int flags) | |
2136 | { | |
2137 | unsigned int i; | |
2138 | ||
2139 | for (i = 0; i < ARRAY_SIZE (mips_ase_groups); i++) | |
2140 | if (flags & mips_ase_groups[i]) | |
2141 | flags |= mips_ase_groups[i]; | |
2142 | return flags; | |
2143 | } | |
2144 | ||
2145 | /* Check whether the current ISA supports ASE. Issue a warning if | |
2146 | appropriate. */ | |
2147 | ||
2148 | static void | |
2149 | mips_check_isa_supports_ase (const struct mips_ase *ase) | |
2150 | { | |
2151 | const char *base; | |
2152 | int min_rev, size; | |
2153 | static unsigned int warned_isa; | |
2154 | static unsigned int warned_fp32; | |
2155 | ||
2156 | if (ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
2157 | min_rev = mips_opts.micromips ? ase->micromips64_rev : ase->mips64_rev; | |
2158 | else | |
2159 | min_rev = mips_opts.micromips ? ase->micromips32_rev : ase->mips32_rev; | |
2160 | if ((min_rev < 0 || mips_isa_rev () < min_rev) | |
2161 | && (warned_isa & ase->flags) != ase->flags) | |
2162 | { | |
2163 | warned_isa |= ase->flags; | |
2164 | base = mips_opts.micromips ? "microMIPS" : "MIPS"; | |
2165 | size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32; | |
2166 | if (min_rev < 0) | |
1661c76c | 2167 | as_warn (_("the %d-bit %s architecture does not support the" |
c6278170 RS |
2168 | " `%s' extension"), size, base, ase->name); |
2169 | else | |
1661c76c | 2170 | as_warn (_("the `%s' extension requires %s%d revision %d or greater"), |
c6278170 RS |
2171 | ase->name, base, size, min_rev); |
2172 | } | |
7361da2c AB |
2173 | else if ((ase->rem_rev > 0 && mips_isa_rev () >= ase->rem_rev) |
2174 | && (warned_isa & ase->flags) != ase->flags) | |
2175 | { | |
2176 | warned_isa |= ase->flags; | |
2177 | base = mips_opts.micromips ? "microMIPS" : "MIPS"; | |
2178 | size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32; | |
2179 | as_warn (_("the `%s' extension was removed in %s%d revision %d"), | |
2180 | ase->name, base, size, ase->rem_rev); | |
2181 | } | |
2182 | ||
c6278170 | 2183 | if ((ase->flags & FP64_ASES) |
0b35dfee | 2184 | && mips_opts.fp != 64 |
c6278170 RS |
2185 | && (warned_fp32 & ase->flags) != ase->flags) |
2186 | { | |
2187 | warned_fp32 |= ase->flags; | |
1661c76c | 2188 | as_warn (_("the `%s' extension requires 64-bit FPRs"), ase->name); |
c6278170 RS |
2189 | } |
2190 | } | |
2191 | ||
2192 | /* Check all enabled ASEs to see whether they are supported by the | |
2193 | chosen architecture. */ | |
2194 | ||
2195 | static void | |
2196 | mips_check_isa_supports_ases (void) | |
2197 | { | |
2198 | unsigned int i, mask; | |
2199 | ||
2200 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
2201 | { | |
2202 | mask = mips_ase_mask (mips_ases[i].flags); | |
2203 | if ((mips_opts.ase & mask) == mips_ases[i].flags) | |
2204 | mips_check_isa_supports_ase (&mips_ases[i]); | |
2205 | } | |
2206 | } | |
2207 | ||
2208 | /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags | |
2209 | that were affected. */ | |
2210 | ||
2211 | static unsigned int | |
919731af | 2212 | mips_set_ase (const struct mips_ase *ase, struct mips_set_options *opts, |
2213 | bfd_boolean enabled_p) | |
c6278170 RS |
2214 | { |
2215 | unsigned int mask; | |
2216 | ||
2217 | mask = mips_ase_mask (ase->flags); | |
919731af | 2218 | opts->ase &= ~mask; |
92cebb3d MR |
2219 | |
2220 | /* Clear combination ASE flags, which need to be recalculated based on | |
2221 | updated regular ASE settings. */ | |
9785fc2a | 2222 | opts->ase &= ~(ASE_MIPS16E2_MT | ASE_XPA_VIRT); |
92cebb3d | 2223 | |
c6278170 | 2224 | if (enabled_p) |
919731af | 2225 | opts->ase |= ase->flags; |
25499ac7 | 2226 | |
9785fc2a MR |
2227 | /* The Virtualization ASE has eXtended Physical Addressing (XPA) |
2228 | instructions which are only valid when both ASEs are enabled. | |
2229 | This sets the ASE_XPA_VIRT flag when both ASEs are present. */ | |
2230 | if ((opts->ase & (ASE_XPA | ASE_VIRT)) == (ASE_XPA | ASE_VIRT)) | |
2231 | { | |
2232 | opts->ase |= ASE_XPA_VIRT; | |
2233 | mask |= ASE_XPA_VIRT; | |
2234 | } | |
25499ac7 MR |
2235 | if ((opts->ase & (ASE_MIPS16E2 | ASE_MT)) == (ASE_MIPS16E2 | ASE_MT)) |
2236 | { | |
2237 | opts->ase |= ASE_MIPS16E2_MT; | |
2238 | mask |= ASE_MIPS16E2_MT; | |
2239 | } | |
2240 | ||
c6278170 RS |
2241 | return mask; |
2242 | } | |
2243 | ||
2244 | /* Return the ASE called NAME, or null if none. */ | |
2245 | ||
2246 | static const struct mips_ase * | |
2247 | mips_lookup_ase (const char *name) | |
2248 | { | |
2249 | unsigned int i; | |
2250 | ||
2251 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
2252 | if (strcmp (name, mips_ases[i].name) == 0) | |
2253 | return &mips_ases[i]; | |
2254 | return NULL; | |
2255 | } | |
2256 | ||
df58fc94 | 2257 | /* Return the length of a microMIPS instruction in bytes. If bits of |
100b4f2e MR |
2258 | the mask beyond the low 16 are 0, then it is a 16-bit instruction, |
2259 | otherwise it is a 32-bit instruction. */ | |
df58fc94 RS |
2260 | |
2261 | static inline unsigned int | |
2262 | micromips_insn_length (const struct mips_opcode *mo) | |
2263 | { | |
7fd53920 | 2264 | return mips_opcode_32bit_p (mo) ? 4 : 2; |
df58fc94 RS |
2265 | } |
2266 | ||
5c04167a RS |
2267 | /* Return the length of MIPS16 instruction OPCODE. */ |
2268 | ||
2269 | static inline unsigned int | |
2270 | mips16_opcode_length (unsigned long opcode) | |
2271 | { | |
2272 | return (opcode >> 16) == 0 ? 2 : 4; | |
2273 | } | |
2274 | ||
1e915849 RS |
2275 | /* Return the length of instruction INSN. */ |
2276 | ||
2277 | static inline unsigned int | |
2278 | insn_length (const struct mips_cl_insn *insn) | |
2279 | { | |
df58fc94 RS |
2280 | if (mips_opts.micromips) |
2281 | return micromips_insn_length (insn->insn_mo); | |
2282 | else if (mips_opts.mips16) | |
5c04167a | 2283 | return mips16_opcode_length (insn->insn_opcode); |
df58fc94 | 2284 | else |
1e915849 | 2285 | return 4; |
1e915849 RS |
2286 | } |
2287 | ||
2288 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
2289 | ||
2290 | static void | |
2291 | create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) | |
2292 | { | |
2293 | size_t i; | |
2294 | ||
2295 | insn->insn_mo = mo; | |
1e915849 RS |
2296 | insn->insn_opcode = mo->match; |
2297 | insn->frag = NULL; | |
2298 | insn->where = 0; | |
2299 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
2300 | insn->fixp[i] = NULL; | |
2301 | insn->fixed_p = (mips_opts.noreorder > 0); | |
2302 | insn->noreorder_p = (mips_opts.noreorder > 0); | |
2303 | insn->mips16_absolute_jump_p = 0; | |
15be625d | 2304 | insn->complete_p = 0; |
e407c74b | 2305 | insn->cleared_p = 0; |
1e915849 RS |
2306 | } |
2307 | ||
fc76e730 RS |
2308 | /* Get a list of all the operands in INSN. */ |
2309 | ||
2310 | static const struct mips_operand_array * | |
2311 | insn_operands (const struct mips_cl_insn *insn) | |
2312 | { | |
2313 | if (insn->insn_mo >= &mips_opcodes[0] | |
2314 | && insn->insn_mo < &mips_opcodes[NUMOPCODES]) | |
2315 | return &mips_operands[insn->insn_mo - &mips_opcodes[0]]; | |
2316 | ||
2317 | if (insn->insn_mo >= &mips16_opcodes[0] | |
2318 | && insn->insn_mo < &mips16_opcodes[bfd_mips16_num_opcodes]) | |
2319 | return &mips16_operands[insn->insn_mo - &mips16_opcodes[0]]; | |
2320 | ||
2321 | if (insn->insn_mo >= µmips_opcodes[0] | |
2322 | && insn->insn_mo < µmips_opcodes[bfd_micromips_num_opcodes]) | |
2323 | return µmips_operands[insn->insn_mo - µmips_opcodes[0]]; | |
2324 | ||
2325 | abort (); | |
2326 | } | |
2327 | ||
2328 | /* Get a description of operand OPNO of INSN. */ | |
2329 | ||
2330 | static const struct mips_operand * | |
2331 | insn_opno (const struct mips_cl_insn *insn, unsigned opno) | |
2332 | { | |
2333 | const struct mips_operand_array *operands; | |
2334 | ||
2335 | operands = insn_operands (insn); | |
2336 | if (opno >= MAX_OPERANDS || !operands->operand[opno]) | |
2337 | abort (); | |
2338 | return operands->operand[opno]; | |
2339 | } | |
2340 | ||
e077a1c8 RS |
2341 | /* Install UVAL as the value of OPERAND in INSN. */ |
2342 | ||
2343 | static inline void | |
2344 | insn_insert_operand (struct mips_cl_insn *insn, | |
2345 | const struct mips_operand *operand, unsigned int uval) | |
2346 | { | |
25499ac7 MR |
2347 | if (mips_opts.mips16 |
2348 | && operand->type == OP_INT && operand->lsb == 0 | |
2349 | && mips_opcode_32bit_p (insn->insn_mo)) | |
2350 | insn->insn_opcode |= mips16_immed_extend (uval, operand->size); | |
2351 | else | |
2352 | insn->insn_opcode = mips_insert_operand (operand, insn->insn_opcode, uval); | |
e077a1c8 RS |
2353 | } |
2354 | ||
fc76e730 RS |
2355 | /* Extract the value of OPERAND from INSN. */ |
2356 | ||
2357 | static inline unsigned | |
2358 | insn_extract_operand (const struct mips_cl_insn *insn, | |
2359 | const struct mips_operand *operand) | |
2360 | { | |
2361 | return mips_extract_operand (operand, insn->insn_opcode); | |
2362 | } | |
2363 | ||
df58fc94 | 2364 | /* Record the current MIPS16/microMIPS mode in now_seg. */ |
742a56fe RS |
2365 | |
2366 | static void | |
df58fc94 | 2367 | mips_record_compressed_mode (void) |
742a56fe RS |
2368 | { |
2369 | segment_info_type *si; | |
2370 | ||
2371 | si = seg_info (now_seg); | |
2372 | if (si->tc_segment_info_data.mips16 != mips_opts.mips16) | |
2373 | si->tc_segment_info_data.mips16 = mips_opts.mips16; | |
df58fc94 RS |
2374 | if (si->tc_segment_info_data.micromips != mips_opts.micromips) |
2375 | si->tc_segment_info_data.micromips = mips_opts.micromips; | |
742a56fe RS |
2376 | } |
2377 | ||
4d68580a RS |
2378 | /* Read a standard MIPS instruction from BUF. */ |
2379 | ||
2380 | static unsigned long | |
2381 | read_insn (char *buf) | |
2382 | { | |
2383 | if (target_big_endian) | |
2384 | return bfd_getb32 ((bfd_byte *) buf); | |
2385 | else | |
2386 | return bfd_getl32 ((bfd_byte *) buf); | |
2387 | } | |
2388 | ||
2389 | /* Write standard MIPS instruction INSN to BUF. Return a pointer to | |
2390 | the next byte. */ | |
2391 | ||
2392 | static char * | |
2393 | write_insn (char *buf, unsigned int insn) | |
2394 | { | |
2395 | md_number_to_chars (buf, insn, 4); | |
2396 | return buf + 4; | |
2397 | } | |
2398 | ||
2399 | /* Read a microMIPS or MIPS16 opcode from BUF, given that it | |
2400 | has length LENGTH. */ | |
2401 | ||
2402 | static unsigned long | |
2403 | read_compressed_insn (char *buf, unsigned int length) | |
2404 | { | |
2405 | unsigned long insn; | |
2406 | unsigned int i; | |
2407 | ||
2408 | insn = 0; | |
2409 | for (i = 0; i < length; i += 2) | |
2410 | { | |
2411 | insn <<= 16; | |
2412 | if (target_big_endian) | |
2413 | insn |= bfd_getb16 ((char *) buf); | |
2414 | else | |
2415 | insn |= bfd_getl16 ((char *) buf); | |
2416 | buf += 2; | |
2417 | } | |
2418 | return insn; | |
2419 | } | |
2420 | ||
5c04167a RS |
2421 | /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the |
2422 | instruction is LENGTH bytes long. Return a pointer to the next byte. */ | |
2423 | ||
2424 | static char * | |
2425 | write_compressed_insn (char *buf, unsigned int insn, unsigned int length) | |
2426 | { | |
2427 | unsigned int i; | |
2428 | ||
2429 | for (i = 0; i < length; i += 2) | |
2430 | md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2); | |
2431 | return buf + length; | |
2432 | } | |
2433 | ||
1e915849 RS |
2434 | /* Install INSN at the location specified by its "frag" and "where" fields. */ |
2435 | ||
2436 | static void | |
2437 | install_insn (const struct mips_cl_insn *insn) | |
2438 | { | |
2439 | char *f = insn->frag->fr_literal + insn->where; | |
5c04167a RS |
2440 | if (HAVE_CODE_COMPRESSION) |
2441 | write_compressed_insn (f, insn->insn_opcode, insn_length (insn)); | |
1e915849 | 2442 | else |
4d68580a | 2443 | write_insn (f, insn->insn_opcode); |
df58fc94 | 2444 | mips_record_compressed_mode (); |
1e915849 RS |
2445 | } |
2446 | ||
2447 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
2448 | and install the opcode in the new location. */ | |
2449 | ||
2450 | static void | |
2451 | move_insn (struct mips_cl_insn *insn, fragS *frag, long where) | |
2452 | { | |
2453 | size_t i; | |
2454 | ||
2455 | insn->frag = frag; | |
2456 | insn->where = where; | |
2457 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
2458 | if (insn->fixp[i] != NULL) | |
2459 | { | |
2460 | insn->fixp[i]->fx_frag = frag; | |
2461 | insn->fixp[i]->fx_where = where; | |
2462 | } | |
2463 | install_insn (insn); | |
2464 | } | |
2465 | ||
2466 | /* Add INSN to the end of the output. */ | |
2467 | ||
2468 | static void | |
2469 | add_fixed_insn (struct mips_cl_insn *insn) | |
2470 | { | |
2471 | char *f = frag_more (insn_length (insn)); | |
2472 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
2473 | } | |
2474 | ||
2475 | /* Start a variant frag and move INSN to the start of the variant part, | |
2476 | marking it as fixed. The other arguments are as for frag_var. */ | |
2477 | ||
2478 | static void | |
2479 | add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, | |
2480 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
2481 | { | |
2482 | frag_grow (max_chars); | |
2483 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
2484 | insn->fixed_p = 1; | |
2485 | frag_var (rs_machine_dependent, max_chars, var, | |
2486 | subtype, symbol, offset, NULL); | |
2487 | } | |
2488 | ||
2489 | /* Insert N copies of INSN into the history buffer, starting at | |
2490 | position FIRST. Neither FIRST nor N need to be clipped. */ | |
2491 | ||
2492 | static void | |
2493 | insert_into_history (unsigned int first, unsigned int n, | |
2494 | const struct mips_cl_insn *insn) | |
2495 | { | |
2496 | if (mips_relax.sequence != 2) | |
2497 | { | |
2498 | unsigned int i; | |
2499 | ||
2500 | for (i = ARRAY_SIZE (history); i-- > first;) | |
2501 | if (i >= first + n) | |
2502 | history[i] = history[i - n]; | |
2503 | else | |
2504 | history[i] = *insn; | |
2505 | } | |
2506 | } | |
2507 | ||
e3de51ce RS |
2508 | /* Clear the error in insn_error. */ |
2509 | ||
2510 | static void | |
2511 | clear_insn_error (void) | |
2512 | { | |
2513 | memset (&insn_error, 0, sizeof (insn_error)); | |
2514 | } | |
2515 | ||
2516 | /* Possibly record error message MSG for the current instruction. | |
2517 | If the error is about a particular argument, ARGNUM is the 1-based | |
2518 | number of that argument, otherwise it is 0. FORMAT is the format | |
2519 | of MSG. Return true if MSG was used, false if the current message | |
2520 | was kept. */ | |
2521 | ||
2522 | static bfd_boolean | |
2523 | set_insn_error_format (int argnum, enum mips_insn_error_format format, | |
2524 | const char *msg) | |
2525 | { | |
2526 | if (argnum == 0) | |
2527 | { | |
2528 | /* Give priority to errors against specific arguments, and to | |
2529 | the first whole-instruction message. */ | |
2530 | if (insn_error.msg) | |
2531 | return FALSE; | |
2532 | } | |
2533 | else | |
2534 | { | |
2535 | /* Keep insn_error if it is against a later argument. */ | |
2536 | if (argnum < insn_error.min_argnum) | |
2537 | return FALSE; | |
2538 | ||
2539 | /* If both errors are against the same argument but are different, | |
2540 | give up on reporting a specific error for this argument. | |
2541 | See the comment about mips_insn_error for details. */ | |
2542 | if (argnum == insn_error.min_argnum | |
2543 | && insn_error.msg | |
2544 | && strcmp (insn_error.msg, msg) != 0) | |
2545 | { | |
2546 | insn_error.msg = 0; | |
2547 | insn_error.min_argnum += 1; | |
2548 | return FALSE; | |
2549 | } | |
2550 | } | |
2551 | insn_error.min_argnum = argnum; | |
2552 | insn_error.format = format; | |
2553 | insn_error.msg = msg; | |
2554 | return TRUE; | |
2555 | } | |
2556 | ||
2557 | /* Record an instruction error with no % format fields. ARGNUM and MSG are | |
2558 | as for set_insn_error_format. */ | |
2559 | ||
2560 | static void | |
2561 | set_insn_error (int argnum, const char *msg) | |
2562 | { | |
2563 | set_insn_error_format (argnum, ERR_FMT_PLAIN, msg); | |
2564 | } | |
2565 | ||
2566 | /* Record an instruction error with one %d field I. ARGNUM and MSG are | |
2567 | as for set_insn_error_format. */ | |
2568 | ||
2569 | static void | |
2570 | set_insn_error_i (int argnum, const char *msg, int i) | |
2571 | { | |
2572 | if (set_insn_error_format (argnum, ERR_FMT_I, msg)) | |
2573 | insn_error.u.i = i; | |
2574 | } | |
2575 | ||
2576 | /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG | |
2577 | are as for set_insn_error_format. */ | |
2578 | ||
2579 | static void | |
2580 | set_insn_error_ss (int argnum, const char *msg, const char *s1, const char *s2) | |
2581 | { | |
2582 | if (set_insn_error_format (argnum, ERR_FMT_SS, msg)) | |
2583 | { | |
2584 | insn_error.u.ss[0] = s1; | |
2585 | insn_error.u.ss[1] = s2; | |
2586 | } | |
2587 | } | |
2588 | ||
2589 | /* Report the error in insn_error, which is against assembly code STR. */ | |
2590 | ||
2591 | static void | |
2592 | report_insn_error (const char *str) | |
2593 | { | |
e1fa0163 | 2594 | const char *msg = concat (insn_error.msg, " `%s'", NULL); |
e3de51ce | 2595 | |
e3de51ce RS |
2596 | switch (insn_error.format) |
2597 | { | |
2598 | case ERR_FMT_PLAIN: | |
2599 | as_bad (msg, str); | |
2600 | break; | |
2601 | ||
2602 | case ERR_FMT_I: | |
2603 | as_bad (msg, insn_error.u.i, str); | |
2604 | break; | |
2605 | ||
2606 | case ERR_FMT_SS: | |
2607 | as_bad (msg, insn_error.u.ss[0], insn_error.u.ss[1], str); | |
2608 | break; | |
2609 | } | |
e1fa0163 NC |
2610 | |
2611 | free ((char *) msg); | |
e3de51ce RS |
2612 | } |
2613 | ||
71400594 RS |
2614 | /* Initialize vr4120_conflicts. There is a bit of duplication here: |
2615 | the idea is to make it obvious at a glance that each errata is | |
2616 | included. */ | |
2617 | ||
2618 | static void | |
2619 | init_vr4120_conflicts (void) | |
2620 | { | |
2621 | #define CONFLICT(FIRST, SECOND) \ | |
2622 | vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND | |
2623 | ||
2624 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
2625 | CONFLICT (MACC, DIV); | |
2626 | CONFLICT (DMACC, DIV); | |
2627 | ||
2628 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ | |
2629 | CONFLICT (DMULT, DMULT); | |
2630 | CONFLICT (DMULT, DMACC); | |
2631 | CONFLICT (DMACC, DMULT); | |
2632 | CONFLICT (DMACC, DMACC); | |
2633 | ||
2634 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
2635 | CONFLICT (MACC, MTHILO); | |
2636 | CONFLICT (DMACC, MTHILO); | |
2637 | ||
2638 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU | |
2639 | instruction is executed immediately after a MACC or DMACC | |
2640 | instruction, the result of [either instruction] is incorrect." */ | |
2641 | CONFLICT (MACC, MULT); | |
2642 | CONFLICT (MACC, DMULT); | |
2643 | CONFLICT (DMACC, MULT); | |
2644 | CONFLICT (DMACC, DMULT); | |
2645 | ||
2646 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
2647 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
2648 | DDIV or DDIVU instruction, the result of the MACC or | |
2649 | DMACC instruction is incorrect.". */ | |
2650 | CONFLICT (DMULT, MACC); | |
2651 | CONFLICT (DMULT, DMACC); | |
2652 | CONFLICT (DIV, MACC); | |
2653 | CONFLICT (DIV, DMACC); | |
2654 | ||
2655 | #undef CONFLICT | |
2656 | } | |
2657 | ||
707bfff6 TS |
2658 | struct regname { |
2659 | const char *name; | |
2660 | unsigned int num; | |
2661 | }; | |
2662 | ||
14daeee3 | 2663 | #define RNUM_MASK 0x00000ff |
56d438b1 | 2664 | #define RTYPE_MASK 0x0ffff00 |
14daeee3 RS |
2665 | #define RTYPE_NUM 0x0000100 |
2666 | #define RTYPE_FPU 0x0000200 | |
2667 | #define RTYPE_FCC 0x0000400 | |
2668 | #define RTYPE_VEC 0x0000800 | |
2669 | #define RTYPE_GP 0x0001000 | |
2670 | #define RTYPE_CP0 0x0002000 | |
2671 | #define RTYPE_PC 0x0004000 | |
2672 | #define RTYPE_ACC 0x0008000 | |
2673 | #define RTYPE_CCC 0x0010000 | |
2674 | #define RTYPE_VI 0x0020000 | |
2675 | #define RTYPE_VF 0x0040000 | |
2676 | #define RTYPE_R5900_I 0x0080000 | |
2677 | #define RTYPE_R5900_Q 0x0100000 | |
2678 | #define RTYPE_R5900_R 0x0200000 | |
2679 | #define RTYPE_R5900_ACC 0x0400000 | |
56d438b1 | 2680 | #define RTYPE_MSA 0x0800000 |
14daeee3 | 2681 | #define RWARN 0x8000000 |
707bfff6 TS |
2682 | |
2683 | #define GENERIC_REGISTER_NUMBERS \ | |
2684 | {"$0", RTYPE_NUM | 0}, \ | |
2685 | {"$1", RTYPE_NUM | 1}, \ | |
2686 | {"$2", RTYPE_NUM | 2}, \ | |
2687 | {"$3", RTYPE_NUM | 3}, \ | |
2688 | {"$4", RTYPE_NUM | 4}, \ | |
2689 | {"$5", RTYPE_NUM | 5}, \ | |
2690 | {"$6", RTYPE_NUM | 6}, \ | |
2691 | {"$7", RTYPE_NUM | 7}, \ | |
2692 | {"$8", RTYPE_NUM | 8}, \ | |
2693 | {"$9", RTYPE_NUM | 9}, \ | |
2694 | {"$10", RTYPE_NUM | 10}, \ | |
2695 | {"$11", RTYPE_NUM | 11}, \ | |
2696 | {"$12", RTYPE_NUM | 12}, \ | |
2697 | {"$13", RTYPE_NUM | 13}, \ | |
2698 | {"$14", RTYPE_NUM | 14}, \ | |
2699 | {"$15", RTYPE_NUM | 15}, \ | |
2700 | {"$16", RTYPE_NUM | 16}, \ | |
2701 | {"$17", RTYPE_NUM | 17}, \ | |
2702 | {"$18", RTYPE_NUM | 18}, \ | |
2703 | {"$19", RTYPE_NUM | 19}, \ | |
2704 | {"$20", RTYPE_NUM | 20}, \ | |
2705 | {"$21", RTYPE_NUM | 21}, \ | |
2706 | {"$22", RTYPE_NUM | 22}, \ | |
2707 | {"$23", RTYPE_NUM | 23}, \ | |
2708 | {"$24", RTYPE_NUM | 24}, \ | |
2709 | {"$25", RTYPE_NUM | 25}, \ | |
2710 | {"$26", RTYPE_NUM | 26}, \ | |
2711 | {"$27", RTYPE_NUM | 27}, \ | |
2712 | {"$28", RTYPE_NUM | 28}, \ | |
2713 | {"$29", RTYPE_NUM | 29}, \ | |
2714 | {"$30", RTYPE_NUM | 30}, \ | |
3739860c | 2715 | {"$31", RTYPE_NUM | 31} |
707bfff6 TS |
2716 | |
2717 | #define FPU_REGISTER_NAMES \ | |
2718 | {"$f0", RTYPE_FPU | 0}, \ | |
2719 | {"$f1", RTYPE_FPU | 1}, \ | |
2720 | {"$f2", RTYPE_FPU | 2}, \ | |
2721 | {"$f3", RTYPE_FPU | 3}, \ | |
2722 | {"$f4", RTYPE_FPU | 4}, \ | |
2723 | {"$f5", RTYPE_FPU | 5}, \ | |
2724 | {"$f6", RTYPE_FPU | 6}, \ | |
2725 | {"$f7", RTYPE_FPU | 7}, \ | |
2726 | {"$f8", RTYPE_FPU | 8}, \ | |
2727 | {"$f9", RTYPE_FPU | 9}, \ | |
2728 | {"$f10", RTYPE_FPU | 10}, \ | |
2729 | {"$f11", RTYPE_FPU | 11}, \ | |
2730 | {"$f12", RTYPE_FPU | 12}, \ | |
2731 | {"$f13", RTYPE_FPU | 13}, \ | |
2732 | {"$f14", RTYPE_FPU | 14}, \ | |
2733 | {"$f15", RTYPE_FPU | 15}, \ | |
2734 | {"$f16", RTYPE_FPU | 16}, \ | |
2735 | {"$f17", RTYPE_FPU | 17}, \ | |
2736 | {"$f18", RTYPE_FPU | 18}, \ | |
2737 | {"$f19", RTYPE_FPU | 19}, \ | |
2738 | {"$f20", RTYPE_FPU | 20}, \ | |
2739 | {"$f21", RTYPE_FPU | 21}, \ | |
2740 | {"$f22", RTYPE_FPU | 22}, \ | |
2741 | {"$f23", RTYPE_FPU | 23}, \ | |
2742 | {"$f24", RTYPE_FPU | 24}, \ | |
2743 | {"$f25", RTYPE_FPU | 25}, \ | |
2744 | {"$f26", RTYPE_FPU | 26}, \ | |
2745 | {"$f27", RTYPE_FPU | 27}, \ | |
2746 | {"$f28", RTYPE_FPU | 28}, \ | |
2747 | {"$f29", RTYPE_FPU | 29}, \ | |
2748 | {"$f30", RTYPE_FPU | 30}, \ | |
2749 | {"$f31", RTYPE_FPU | 31} | |
2750 | ||
2751 | #define FPU_CONDITION_CODE_NAMES \ | |
2752 | {"$fcc0", RTYPE_FCC | 0}, \ | |
2753 | {"$fcc1", RTYPE_FCC | 1}, \ | |
2754 | {"$fcc2", RTYPE_FCC | 2}, \ | |
2755 | {"$fcc3", RTYPE_FCC | 3}, \ | |
2756 | {"$fcc4", RTYPE_FCC | 4}, \ | |
2757 | {"$fcc5", RTYPE_FCC | 5}, \ | |
2758 | {"$fcc6", RTYPE_FCC | 6}, \ | |
2759 | {"$fcc7", RTYPE_FCC | 7} | |
2760 | ||
2761 | #define COPROC_CONDITION_CODE_NAMES \ | |
2762 | {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \ | |
2763 | {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \ | |
2764 | {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \ | |
2765 | {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \ | |
2766 | {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \ | |
2767 | {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \ | |
2768 | {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \ | |
2769 | {"$cc7", RTYPE_FCC | RTYPE_CCC | 7} | |
2770 | ||
2771 | #define N32N64_SYMBOLIC_REGISTER_NAMES \ | |
2772 | {"$a4", RTYPE_GP | 8}, \ | |
2773 | {"$a5", RTYPE_GP | 9}, \ | |
2774 | {"$a6", RTYPE_GP | 10}, \ | |
2775 | {"$a7", RTYPE_GP | 11}, \ | |
2776 | {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \ | |
2777 | {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \ | |
2778 | {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \ | |
2779 | {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \ | |
2780 | {"$t0", RTYPE_GP | 12}, \ | |
2781 | {"$t1", RTYPE_GP | 13}, \ | |
2782 | {"$t2", RTYPE_GP | 14}, \ | |
2783 | {"$t3", RTYPE_GP | 15} | |
2784 | ||
2785 | #define O32_SYMBOLIC_REGISTER_NAMES \ | |
2786 | {"$t0", RTYPE_GP | 8}, \ | |
2787 | {"$t1", RTYPE_GP | 9}, \ | |
2788 | {"$t2", RTYPE_GP | 10}, \ | |
2789 | {"$t3", RTYPE_GP | 11}, \ | |
2790 | {"$t4", RTYPE_GP | 12}, \ | |
2791 | {"$t5", RTYPE_GP | 13}, \ | |
2792 | {"$t6", RTYPE_GP | 14}, \ | |
2793 | {"$t7", RTYPE_GP | 15}, \ | |
2794 | {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \ | |
2795 | {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \ | |
2796 | {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \ | |
3739860c | 2797 | {"$ta3", RTYPE_GP | 15} /* alias for $t7 */ |
707bfff6 | 2798 | |
6f2117ba | 2799 | /* Remaining symbolic register names. */ |
707bfff6 TS |
2800 | #define SYMBOLIC_REGISTER_NAMES \ |
2801 | {"$zero", RTYPE_GP | 0}, \ | |
2802 | {"$at", RTYPE_GP | 1}, \ | |
2803 | {"$AT", RTYPE_GP | 1}, \ | |
2804 | {"$v0", RTYPE_GP | 2}, \ | |
2805 | {"$v1", RTYPE_GP | 3}, \ | |
2806 | {"$a0", RTYPE_GP | 4}, \ | |
2807 | {"$a1", RTYPE_GP | 5}, \ | |
2808 | {"$a2", RTYPE_GP | 6}, \ | |
2809 | {"$a3", RTYPE_GP | 7}, \ | |
2810 | {"$s0", RTYPE_GP | 16}, \ | |
2811 | {"$s1", RTYPE_GP | 17}, \ | |
2812 | {"$s2", RTYPE_GP | 18}, \ | |
2813 | {"$s3", RTYPE_GP | 19}, \ | |
2814 | {"$s4", RTYPE_GP | 20}, \ | |
2815 | {"$s5", RTYPE_GP | 21}, \ | |
2816 | {"$s6", RTYPE_GP | 22}, \ | |
2817 | {"$s7", RTYPE_GP | 23}, \ | |
2818 | {"$t8", RTYPE_GP | 24}, \ | |
2819 | {"$t9", RTYPE_GP | 25}, \ | |
2820 | {"$k0", RTYPE_GP | 26}, \ | |
2821 | {"$kt0", RTYPE_GP | 26}, \ | |
2822 | {"$k1", RTYPE_GP | 27}, \ | |
2823 | {"$kt1", RTYPE_GP | 27}, \ | |
2824 | {"$gp", RTYPE_GP | 28}, \ | |
2825 | {"$sp", RTYPE_GP | 29}, \ | |
2826 | {"$s8", RTYPE_GP | 30}, \ | |
2827 | {"$fp", RTYPE_GP | 30}, \ | |
2828 | {"$ra", RTYPE_GP | 31} | |
2829 | ||
2830 | #define MIPS16_SPECIAL_REGISTER_NAMES \ | |
2831 | {"$pc", RTYPE_PC | 0} | |
2832 | ||
2833 | #define MDMX_VECTOR_REGISTER_NAMES \ | |
6f2117ba PH |
2834 | /* {"$v0", RTYPE_VEC | 0}, Clash with REG 2 above. */ \ |
2835 | /* {"$v1", RTYPE_VEC | 1}, Clash with REG 3 above. */ \ | |
707bfff6 TS |
2836 | {"$v2", RTYPE_VEC | 2}, \ |
2837 | {"$v3", RTYPE_VEC | 3}, \ | |
2838 | {"$v4", RTYPE_VEC | 4}, \ | |
2839 | {"$v5", RTYPE_VEC | 5}, \ | |
2840 | {"$v6", RTYPE_VEC | 6}, \ | |
2841 | {"$v7", RTYPE_VEC | 7}, \ | |
2842 | {"$v8", RTYPE_VEC | 8}, \ | |
2843 | {"$v9", RTYPE_VEC | 9}, \ | |
2844 | {"$v10", RTYPE_VEC | 10}, \ | |
2845 | {"$v11", RTYPE_VEC | 11}, \ | |
2846 | {"$v12", RTYPE_VEC | 12}, \ | |
2847 | {"$v13", RTYPE_VEC | 13}, \ | |
2848 | {"$v14", RTYPE_VEC | 14}, \ | |
2849 | {"$v15", RTYPE_VEC | 15}, \ | |
2850 | {"$v16", RTYPE_VEC | 16}, \ | |
2851 | {"$v17", RTYPE_VEC | 17}, \ | |
2852 | {"$v18", RTYPE_VEC | 18}, \ | |
2853 | {"$v19", RTYPE_VEC | 19}, \ | |
2854 | {"$v20", RTYPE_VEC | 20}, \ | |
2855 | {"$v21", RTYPE_VEC | 21}, \ | |
2856 | {"$v22", RTYPE_VEC | 22}, \ | |
2857 | {"$v23", RTYPE_VEC | 23}, \ | |
2858 | {"$v24", RTYPE_VEC | 24}, \ | |
2859 | {"$v25", RTYPE_VEC | 25}, \ | |
2860 | {"$v26", RTYPE_VEC | 26}, \ | |
2861 | {"$v27", RTYPE_VEC | 27}, \ | |
2862 | {"$v28", RTYPE_VEC | 28}, \ | |
2863 | {"$v29", RTYPE_VEC | 29}, \ | |
2864 | {"$v30", RTYPE_VEC | 30}, \ | |
2865 | {"$v31", RTYPE_VEC | 31} | |
2866 | ||
14daeee3 RS |
2867 | #define R5900_I_NAMES \ |
2868 | {"$I", RTYPE_R5900_I | 0} | |
2869 | ||
2870 | #define R5900_Q_NAMES \ | |
2871 | {"$Q", RTYPE_R5900_Q | 0} | |
2872 | ||
2873 | #define R5900_R_NAMES \ | |
2874 | {"$R", RTYPE_R5900_R | 0} | |
2875 | ||
2876 | #define R5900_ACC_NAMES \ | |
2877 | {"$ACC", RTYPE_R5900_ACC | 0 } | |
2878 | ||
707bfff6 TS |
2879 | #define MIPS_DSP_ACCUMULATOR_NAMES \ |
2880 | {"$ac0", RTYPE_ACC | 0}, \ | |
2881 | {"$ac1", RTYPE_ACC | 1}, \ | |
2882 | {"$ac2", RTYPE_ACC | 2}, \ | |
2883 | {"$ac3", RTYPE_ACC | 3} | |
2884 | ||
2885 | static const struct regname reg_names[] = { | |
2886 | GENERIC_REGISTER_NUMBERS, | |
2887 | FPU_REGISTER_NAMES, | |
2888 | FPU_CONDITION_CODE_NAMES, | |
2889 | COPROC_CONDITION_CODE_NAMES, | |
2890 | ||
2891 | /* The $txx registers depends on the abi, | |
2892 | these will be added later into the symbol table from | |
3739860c | 2893 | one of the tables below once mips_abi is set after |
707bfff6 TS |
2894 | parsing of arguments from the command line. */ |
2895 | SYMBOLIC_REGISTER_NAMES, | |
2896 | ||
2897 | MIPS16_SPECIAL_REGISTER_NAMES, | |
2898 | MDMX_VECTOR_REGISTER_NAMES, | |
14daeee3 RS |
2899 | R5900_I_NAMES, |
2900 | R5900_Q_NAMES, | |
2901 | R5900_R_NAMES, | |
2902 | R5900_ACC_NAMES, | |
707bfff6 TS |
2903 | MIPS_DSP_ACCUMULATOR_NAMES, |
2904 | {0, 0} | |
2905 | }; | |
2906 | ||
2907 | static const struct regname reg_names_o32[] = { | |
2908 | O32_SYMBOLIC_REGISTER_NAMES, | |
2909 | {0, 0} | |
2910 | }; | |
2911 | ||
2912 | static const struct regname reg_names_n32n64[] = { | |
2913 | N32N64_SYMBOLIC_REGISTER_NAMES, | |
2914 | {0, 0} | |
2915 | }; | |
2916 | ||
a92713e6 RS |
2917 | /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be |
2918 | interpreted as vector registers 0 and 1. If SYMVAL is the value of one | |
2919 | of these register symbols, return the associated vector register, | |
2920 | otherwise return SYMVAL itself. */ | |
df58fc94 | 2921 | |
a92713e6 RS |
2922 | static unsigned int |
2923 | mips_prefer_vec_regno (unsigned int symval) | |
707bfff6 | 2924 | { |
a92713e6 RS |
2925 | if ((symval & -2) == (RTYPE_GP | 2)) |
2926 | return RTYPE_VEC | (symval & 1); | |
2927 | return symval; | |
2928 | } | |
2929 | ||
14daeee3 RS |
2930 | /* Return true if string [S, E) is a valid register name, storing its |
2931 | symbol value in *SYMVAL_PTR if so. */ | |
a92713e6 RS |
2932 | |
2933 | static bfd_boolean | |
14daeee3 | 2934 | mips_parse_register_1 (char *s, char *e, unsigned int *symval_ptr) |
a92713e6 | 2935 | { |
707bfff6 | 2936 | char save_c; |
14daeee3 | 2937 | symbolS *symbol; |
707bfff6 TS |
2938 | |
2939 | /* Terminate name. */ | |
2940 | save_c = *e; | |
2941 | *e = '\0'; | |
2942 | ||
a92713e6 RS |
2943 | /* Look up the name. */ |
2944 | symbol = symbol_find (s); | |
2945 | *e = save_c; | |
2946 | ||
2947 | if (!symbol || S_GET_SEGMENT (symbol) != reg_section) | |
2948 | return FALSE; | |
2949 | ||
14daeee3 RS |
2950 | *symval_ptr = S_GET_VALUE (symbol); |
2951 | return TRUE; | |
2952 | } | |
2953 | ||
2954 | /* Return true if the string at *SPTR is a valid register name. Allow it | |
2955 | to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR | |
2956 | is nonnull. | |
2957 | ||
2958 | When returning true, move *SPTR past the register, store the | |
2959 | register's symbol value in *SYMVAL_PTR and the channel mask in | |
2960 | *CHANNELS_PTR (if nonnull). The symbol value includes the register | |
2961 | number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask | |
2962 | is a 4-bit value of the form XYZW and is 0 if no suffix was given. */ | |
2963 | ||
2964 | static bfd_boolean | |
2965 | mips_parse_register (char **sptr, unsigned int *symval_ptr, | |
2966 | unsigned int *channels_ptr) | |
2967 | { | |
2968 | char *s, *e, *m; | |
2969 | const char *q; | |
2970 | unsigned int channels, symval, bit; | |
2971 | ||
2972 | /* Find end of name. */ | |
2973 | s = e = *sptr; | |
2974 | if (is_name_beginner (*e)) | |
2975 | ++e; | |
2976 | while (is_part_of_name (*e)) | |
2977 | ++e; | |
2978 | ||
2979 | channels = 0; | |
2980 | if (!mips_parse_register_1 (s, e, &symval)) | |
2981 | { | |
2982 | if (!channels_ptr) | |
2983 | return FALSE; | |
2984 | ||
2985 | /* Eat characters from the end of the string that are valid | |
2986 | channel suffixes. The preceding register must be $ACC or | |
2987 | end with a digit, so there is no ambiguity. */ | |
2988 | bit = 1; | |
2989 | m = e; | |
2990 | for (q = "wzyx"; *q; q++, bit <<= 1) | |
2991 | if (m > s && m[-1] == *q) | |
2992 | { | |
2993 | --m; | |
2994 | channels |= bit; | |
2995 | } | |
2996 | ||
2997 | if (channels == 0 | |
2998 | || !mips_parse_register_1 (s, m, &symval) | |
2999 | || (symval & (RTYPE_VI | RTYPE_VF | RTYPE_R5900_ACC)) == 0) | |
3000 | return FALSE; | |
3001 | } | |
3002 | ||
a92713e6 | 3003 | *sptr = e; |
14daeee3 RS |
3004 | *symval_ptr = symval; |
3005 | if (channels_ptr) | |
3006 | *channels_ptr = channels; | |
a92713e6 RS |
3007 | return TRUE; |
3008 | } | |
3009 | ||
3010 | /* Check if SPTR points at a valid register specifier according to TYPES. | |
3011 | If so, then return 1, advance S to consume the specifier and store | |
3012 | the register's number in REGNOP, otherwise return 0. */ | |
3013 | ||
3014 | static int | |
3015 | reg_lookup (char **s, unsigned int types, unsigned int *regnop) | |
3016 | { | |
3017 | unsigned int regno; | |
3018 | ||
14daeee3 | 3019 | if (mips_parse_register (s, ®no, NULL)) |
707bfff6 | 3020 | { |
a92713e6 RS |
3021 | if (types & RTYPE_VEC) |
3022 | regno = mips_prefer_vec_regno (regno); | |
3023 | if (regno & types) | |
3024 | regno &= RNUM_MASK; | |
3025 | else | |
3026 | regno = ~0; | |
707bfff6 | 3027 | } |
a92713e6 | 3028 | else |
707bfff6 | 3029 | { |
a92713e6 | 3030 | if (types & RWARN) |
1661c76c | 3031 | as_warn (_("unrecognized register name `%s'"), *s); |
a92713e6 | 3032 | regno = ~0; |
707bfff6 | 3033 | } |
707bfff6 | 3034 | if (regnop) |
a92713e6 RS |
3035 | *regnop = regno; |
3036 | return regno <= RNUM_MASK; | |
707bfff6 TS |
3037 | } |
3038 | ||
14daeee3 RS |
3039 | /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated |
3040 | mask in *CHANNELS. Return a pointer to the first unconsumed character. */ | |
3041 | ||
3042 | static char * | |
3043 | mips_parse_vu0_channels (char *s, unsigned int *channels) | |
3044 | { | |
3045 | unsigned int i; | |
3046 | ||
3047 | *channels = 0; | |
3048 | for (i = 0; i < 4; i++) | |
3049 | if (*s == "xyzw"[i]) | |
3050 | { | |
3051 | *channels |= 1 << (3 - i); | |
3052 | ++s; | |
3053 | } | |
3054 | return s; | |
3055 | } | |
3056 | ||
a92713e6 RS |
3057 | /* Token types for parsed operand lists. */ |
3058 | enum mips_operand_token_type { | |
3059 | /* A plain register, e.g. $f2. */ | |
3060 | OT_REG, | |
df58fc94 | 3061 | |
14daeee3 RS |
3062 | /* A 4-bit XYZW channel mask. */ |
3063 | OT_CHANNELS, | |
3064 | ||
56d438b1 CF |
3065 | /* A constant vector index, e.g. [1]. */ |
3066 | OT_INTEGER_INDEX, | |
3067 | ||
3068 | /* A register vector index, e.g. [$2]. */ | |
3069 | OT_REG_INDEX, | |
df58fc94 | 3070 | |
a92713e6 RS |
3071 | /* A continuous range of registers, e.g. $s0-$s4. */ |
3072 | OT_REG_RANGE, | |
3073 | ||
3074 | /* A (possibly relocated) expression. */ | |
3075 | OT_INTEGER, | |
3076 | ||
3077 | /* A floating-point value. */ | |
3078 | OT_FLOAT, | |
3079 | ||
3080 | /* A single character. This can be '(', ')' or ',', but '(' only appears | |
3081 | before OT_REGs. */ | |
3082 | OT_CHAR, | |
3083 | ||
14daeee3 RS |
3084 | /* A doubled character, either "--" or "++". */ |
3085 | OT_DOUBLE_CHAR, | |
3086 | ||
a92713e6 RS |
3087 | /* The end of the operand list. */ |
3088 | OT_END | |
3089 | }; | |
3090 | ||
3091 | /* A parsed operand token. */ | |
3092 | struct mips_operand_token | |
3093 | { | |
3094 | /* The type of token. */ | |
3095 | enum mips_operand_token_type type; | |
3096 | union | |
3097 | { | |
56d438b1 | 3098 | /* The register symbol value for an OT_REG or OT_REG_INDEX. */ |
a92713e6 RS |
3099 | unsigned int regno; |
3100 | ||
14daeee3 RS |
3101 | /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */ |
3102 | unsigned int channels; | |
3103 | ||
56d438b1 CF |
3104 | /* The integer value of an OT_INTEGER_INDEX. */ |
3105 | addressT index; | |
a92713e6 RS |
3106 | |
3107 | /* The two register symbol values involved in an OT_REG_RANGE. */ | |
3108 | struct { | |
3109 | unsigned int regno1; | |
3110 | unsigned int regno2; | |
3111 | } reg_range; | |
3112 | ||
3113 | /* The value of an OT_INTEGER. The value is represented as an | |
3114 | expression and the relocation operators that were applied to | |
3115 | that expression. The reloc entries are BFD_RELOC_UNUSED if no | |
3116 | relocation operators were used. */ | |
3117 | struct { | |
3118 | expressionS value; | |
3119 | bfd_reloc_code_real_type relocs[3]; | |
3120 | } integer; | |
3121 | ||
3122 | /* The binary data for an OT_FLOAT constant, and the number of bytes | |
3123 | in the constant. */ | |
3124 | struct { | |
3125 | unsigned char data[8]; | |
3126 | int length; | |
3127 | } flt; | |
3128 | ||
14daeee3 | 3129 | /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */ |
a92713e6 RS |
3130 | char ch; |
3131 | } u; | |
3132 | }; | |
3133 | ||
3134 | /* An obstack used to construct lists of mips_operand_tokens. */ | |
3135 | static struct obstack mips_operand_tokens; | |
3136 | ||
3137 | /* Give TOKEN type TYPE and add it to mips_operand_tokens. */ | |
3138 | ||
3139 | static void | |
3140 | mips_add_token (struct mips_operand_token *token, | |
3141 | enum mips_operand_token_type type) | |
3142 | { | |
3143 | token->type = type; | |
3144 | obstack_grow (&mips_operand_tokens, token, sizeof (*token)); | |
3145 | } | |
3146 | ||
3147 | /* Check whether S is '(' followed by a register name. Add OT_CHAR | |
3148 | and OT_REG tokens for them if so, and return a pointer to the first | |
3149 | unconsumed character. Return null otherwise. */ | |
3150 | ||
3151 | static char * | |
3152 | mips_parse_base_start (char *s) | |
3153 | { | |
3154 | struct mips_operand_token token; | |
14daeee3 RS |
3155 | unsigned int regno, channels; |
3156 | bfd_boolean decrement_p; | |
df58fc94 | 3157 | |
a92713e6 RS |
3158 | if (*s != '(') |
3159 | return 0; | |
3160 | ||
3161 | ++s; | |
3162 | SKIP_SPACE_TABS (s); | |
14daeee3 RS |
3163 | |
3164 | /* Only match "--" as part of a base expression. In other contexts "--X" | |
3165 | is a double negative. */ | |
3166 | decrement_p = (s[0] == '-' && s[1] == '-'); | |
3167 | if (decrement_p) | |
3168 | { | |
3169 | s += 2; | |
3170 | SKIP_SPACE_TABS (s); | |
3171 | } | |
3172 | ||
3173 | /* Allow a channel specifier because that leads to better error messages | |
3174 | than treating something like "$vf0x++" as an expression. */ | |
3175 | if (!mips_parse_register (&s, ®no, &channels)) | |
a92713e6 RS |
3176 | return 0; |
3177 | ||
3178 | token.u.ch = '('; | |
3179 | mips_add_token (&token, OT_CHAR); | |
3180 | ||
14daeee3 RS |
3181 | if (decrement_p) |
3182 | { | |
3183 | token.u.ch = '-'; | |
3184 | mips_add_token (&token, OT_DOUBLE_CHAR); | |
3185 | } | |
3186 | ||
a92713e6 RS |
3187 | token.u.regno = regno; |
3188 | mips_add_token (&token, OT_REG); | |
3189 | ||
14daeee3 RS |
3190 | if (channels) |
3191 | { | |
3192 | token.u.channels = channels; | |
3193 | mips_add_token (&token, OT_CHANNELS); | |
3194 | } | |
3195 | ||
3196 | /* For consistency, only match "++" as part of base expressions too. */ | |
3197 | SKIP_SPACE_TABS (s); | |
3198 | if (s[0] == '+' && s[1] == '+') | |
3199 | { | |
3200 | s += 2; | |
3201 | token.u.ch = '+'; | |
3202 | mips_add_token (&token, OT_DOUBLE_CHAR); | |
3203 | } | |
3204 | ||
a92713e6 RS |
3205 | return s; |
3206 | } | |
3207 | ||
3208 | /* Parse one or more tokens from S. Return a pointer to the first | |
3209 | unconsumed character on success. Return null if an error was found | |
3210 | and store the error text in insn_error. FLOAT_FORMAT is as for | |
3211 | mips_parse_arguments. */ | |
3212 | ||
3213 | static char * | |
3214 | mips_parse_argument_token (char *s, char float_format) | |
3215 | { | |
6d4af3c2 AM |
3216 | char *end, *save_in; |
3217 | const char *err; | |
14daeee3 | 3218 | unsigned int regno1, regno2, channels; |
a92713e6 RS |
3219 | struct mips_operand_token token; |
3220 | ||
3221 | /* First look for "($reg", since we want to treat that as an | |
3222 | OT_CHAR and OT_REG rather than an expression. */ | |
3223 | end = mips_parse_base_start (s); | |
3224 | if (end) | |
3225 | return end; | |
3226 | ||
3227 | /* Handle other characters that end up as OT_CHARs. */ | |
3228 | if (*s == ')' || *s == ',') | |
3229 | { | |
3230 | token.u.ch = *s; | |
3231 | mips_add_token (&token, OT_CHAR); | |
3232 | ++s; | |
3233 | return s; | |
3234 | } | |
3235 | ||
3236 | /* Handle tokens that start with a register. */ | |
14daeee3 | 3237 | if (mips_parse_register (&s, ®no1, &channels)) |
df58fc94 | 3238 | { |
14daeee3 RS |
3239 | if (channels) |
3240 | { | |
3241 | /* A register and a VU0 channel suffix. */ | |
3242 | token.u.regno = regno1; | |
3243 | mips_add_token (&token, OT_REG); | |
3244 | ||
3245 | token.u.channels = channels; | |
3246 | mips_add_token (&token, OT_CHANNELS); | |
3247 | return s; | |
3248 | } | |
3249 | ||
a92713e6 RS |
3250 | SKIP_SPACE_TABS (s); |
3251 | if (*s == '-') | |
df58fc94 | 3252 | { |
a92713e6 RS |
3253 | /* A register range. */ |
3254 | ++s; | |
3255 | SKIP_SPACE_TABS (s); | |
14daeee3 | 3256 | if (!mips_parse_register (&s, ®no2, NULL)) |
a92713e6 | 3257 | { |
1661c76c | 3258 | set_insn_error (0, _("invalid register range")); |
a92713e6 RS |
3259 | return 0; |
3260 | } | |
df58fc94 | 3261 | |
a92713e6 RS |
3262 | token.u.reg_range.regno1 = regno1; |
3263 | token.u.reg_range.regno2 = regno2; | |
3264 | mips_add_token (&token, OT_REG_RANGE); | |
3265 | return s; | |
3266 | } | |
a92713e6 | 3267 | |
56d438b1 CF |
3268 | /* Add the register itself. */ |
3269 | token.u.regno = regno1; | |
3270 | mips_add_token (&token, OT_REG); | |
3271 | ||
3272 | /* Check for a vector index. */ | |
3273 | if (*s == '[') | |
3274 | { | |
a92713e6 RS |
3275 | ++s; |
3276 | SKIP_SPACE_TABS (s); | |
56d438b1 CF |
3277 | if (mips_parse_register (&s, &token.u.regno, NULL)) |
3278 | mips_add_token (&token, OT_REG_INDEX); | |
3279 | else | |
a92713e6 | 3280 | { |
56d438b1 CF |
3281 | expressionS element; |
3282 | ||
3283 | my_getExpression (&element, s); | |
3284 | if (element.X_op != O_constant) | |
3285 | { | |
3286 | set_insn_error (0, _("vector element must be constant")); | |
3287 | return 0; | |
3288 | } | |
3289 | s = expr_end; | |
3290 | token.u.index = element.X_add_number; | |
3291 | mips_add_token (&token, OT_INTEGER_INDEX); | |
a92713e6 | 3292 | } |
a92713e6 RS |
3293 | SKIP_SPACE_TABS (s); |
3294 | if (*s != ']') | |
3295 | { | |
1661c76c | 3296 | set_insn_error (0, _("missing `]'")); |
a92713e6 RS |
3297 | return 0; |
3298 | } | |
3299 | ++s; | |
df58fc94 | 3300 | } |
a92713e6 | 3301 | return s; |
df58fc94 RS |
3302 | } |
3303 | ||
a92713e6 RS |
3304 | if (float_format) |
3305 | { | |
3306 | /* First try to treat expressions as floats. */ | |
3307 | save_in = input_line_pointer; | |
3308 | input_line_pointer = s; | |
3309 | err = md_atof (float_format, (char *) token.u.flt.data, | |
3310 | &token.u.flt.length); | |
3311 | end = input_line_pointer; | |
3312 | input_line_pointer = save_in; | |
3313 | if (err && *err) | |
3314 | { | |
e3de51ce | 3315 | set_insn_error (0, err); |
a92713e6 RS |
3316 | return 0; |
3317 | } | |
3318 | if (s != end) | |
3319 | { | |
3320 | mips_add_token (&token, OT_FLOAT); | |
3321 | return end; | |
3322 | } | |
3323 | } | |
3324 | ||
3325 | /* Treat everything else as an integer expression. */ | |
3326 | token.u.integer.relocs[0] = BFD_RELOC_UNUSED; | |
3327 | token.u.integer.relocs[1] = BFD_RELOC_UNUSED; | |
3328 | token.u.integer.relocs[2] = BFD_RELOC_UNUSED; | |
3329 | my_getSmallExpression (&token.u.integer.value, token.u.integer.relocs, s); | |
3330 | s = expr_end; | |
3331 | mips_add_token (&token, OT_INTEGER); | |
3332 | return s; | |
3333 | } | |
3334 | ||
3335 | /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f' | |
3336 | if expressions should be treated as 32-bit floating-point constants, | |
3337 | 'd' if they should be treated as 64-bit floating-point constants, | |
3338 | or 0 if they should be treated as integer expressions (the usual case). | |
3339 | ||
3340 | Return a list of tokens on success, otherwise return 0. The caller | |
3341 | must obstack_free the list after use. */ | |
3342 | ||
3343 | static struct mips_operand_token * | |
3344 | mips_parse_arguments (char *s, char float_format) | |
3345 | { | |
3346 | struct mips_operand_token token; | |
3347 | ||
3348 | SKIP_SPACE_TABS (s); | |
3349 | while (*s) | |
3350 | { | |
3351 | s = mips_parse_argument_token (s, float_format); | |
3352 | if (!s) | |
3353 | { | |
3354 | obstack_free (&mips_operand_tokens, | |
3355 | obstack_finish (&mips_operand_tokens)); | |
3356 | return 0; | |
3357 | } | |
3358 | SKIP_SPACE_TABS (s); | |
3359 | } | |
3360 | mips_add_token (&token, OT_END); | |
3361 | return (struct mips_operand_token *) obstack_finish (&mips_operand_tokens); | |
df58fc94 RS |
3362 | } |
3363 | ||
d301a56b RS |
3364 | /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE |
3365 | and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */ | |
037b32b9 AN |
3366 | |
3367 | static bfd_boolean | |
f79e2745 | 3368 | is_opcode_valid (const struct mips_opcode *mo) |
037b32b9 AN |
3369 | { |
3370 | int isa = mips_opts.isa; | |
846ef2d0 | 3371 | int ase = mips_opts.ase; |
037b32b9 | 3372 | int fp_s, fp_d; |
c6278170 | 3373 | unsigned int i; |
037b32b9 | 3374 | |
be0fcbee | 3375 | if (ISA_HAS_64BIT_REGS (isa)) |
c6278170 RS |
3376 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) |
3377 | if ((ase & mips_ases[i].flags) == mips_ases[i].flags) | |
3378 | ase |= mips_ases[i].flags64; | |
037b32b9 | 3379 | |
d301a56b | 3380 | if (!opcode_is_member (mo, isa, ase, mips_opts.arch)) |
037b32b9 AN |
3381 | return FALSE; |
3382 | ||
3383 | /* Check whether the instruction or macro requires single-precision or | |
3384 | double-precision floating-point support. Note that this information is | |
3385 | stored differently in the opcode table for insns and macros. */ | |
3386 | if (mo->pinfo == INSN_MACRO) | |
3387 | { | |
3388 | fp_s = mo->pinfo2 & INSN2_M_FP_S; | |
3389 | fp_d = mo->pinfo2 & INSN2_M_FP_D; | |
3390 | } | |
3391 | else | |
3392 | { | |
3393 | fp_s = mo->pinfo & FP_S; | |
3394 | fp_d = mo->pinfo & FP_D; | |
3395 | } | |
3396 | ||
3397 | if (fp_d && (mips_opts.soft_float || mips_opts.single_float)) | |
3398 | return FALSE; | |
3399 | ||
3400 | if (fp_s && mips_opts.soft_float) | |
3401 | return FALSE; | |
3402 | ||
3403 | return TRUE; | |
3404 | } | |
3405 | ||
3406 | /* Return TRUE if the MIPS16 opcode MO is valid on the currently | |
3407 | selected ISA and architecture. */ | |
3408 | ||
3409 | static bfd_boolean | |
3410 | is_opcode_valid_16 (const struct mips_opcode *mo) | |
3411 | { | |
25499ac7 MR |
3412 | int isa = mips_opts.isa; |
3413 | int ase = mips_opts.ase; | |
3414 | unsigned int i; | |
3415 | ||
3416 | if (ISA_HAS_64BIT_REGS (isa)) | |
3417 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
3418 | if ((ase & mips_ases[i].flags) == mips_ases[i].flags) | |
3419 | ase |= mips_ases[i].flags64; | |
3420 | ||
3421 | return opcode_is_member (mo, isa, ase, mips_opts.arch); | |
037b32b9 AN |
3422 | } |
3423 | ||
df58fc94 | 3424 | /* Return TRUE if the size of the microMIPS opcode MO matches one |
7fd53920 MR |
3425 | explicitly requested. Always TRUE in the standard MIPS mode. |
3426 | Use is_size_valid_16 for MIPS16 opcodes. */ | |
df58fc94 RS |
3427 | |
3428 | static bfd_boolean | |
3429 | is_size_valid (const struct mips_opcode *mo) | |
3430 | { | |
3431 | if (!mips_opts.micromips) | |
3432 | return TRUE; | |
3433 | ||
833794fc MR |
3434 | if (mips_opts.insn32) |
3435 | { | |
3436 | if (mo->pinfo != INSN_MACRO && micromips_insn_length (mo) != 4) | |
3437 | return FALSE; | |
3438 | if ((mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0) | |
3439 | return FALSE; | |
3440 | } | |
df58fc94 RS |
3441 | if (!forced_insn_length) |
3442 | return TRUE; | |
3443 | if (mo->pinfo == INSN_MACRO) | |
3444 | return FALSE; | |
3445 | return forced_insn_length == micromips_insn_length (mo); | |
3446 | } | |
3447 | ||
7fd53920 MR |
3448 | /* Return TRUE if the size of the MIPS16 opcode MO matches one |
3449 | explicitly requested. */ | |
3450 | ||
3451 | static bfd_boolean | |
3452 | is_size_valid_16 (const struct mips_opcode *mo) | |
3453 | { | |
3454 | if (!forced_insn_length) | |
3455 | return TRUE; | |
3456 | if (mo->pinfo == INSN_MACRO) | |
3457 | return FALSE; | |
3458 | if (forced_insn_length == 2 && mips_opcode_32bit_p (mo)) | |
3459 | return FALSE; | |
0674ee5d MR |
3460 | if (forced_insn_length == 4 && (mo->pinfo2 & INSN2_SHORT_ONLY)) |
3461 | return FALSE; | |
7fd53920 MR |
3462 | return TRUE; |
3463 | } | |
3464 | ||
df58fc94 | 3465 | /* Return TRUE if the microMIPS opcode MO is valid for the delay slot |
e64af278 MR |
3466 | of the preceding instruction. Always TRUE in the standard MIPS mode. |
3467 | ||
3468 | We don't accept macros in 16-bit delay slots to avoid a case where | |
3469 | a macro expansion fails because it relies on a preceding 32-bit real | |
3470 | instruction to have matched and does not handle the operands correctly. | |
3471 | The only macros that may expand to 16-bit instructions are JAL that | |
3472 | cannot be placed in a delay slot anyway, and corner cases of BALIGN | |
3473 | and BGT (that likewise cannot be placed in a delay slot) that decay to | |
3474 | a NOP. In all these cases the macros precede any corresponding real | |
3475 | instruction definitions in the opcode table, so they will match in the | |
3476 | second pass where the size of the delay slot is ignored and therefore | |
3477 | produce correct code. */ | |
df58fc94 RS |
3478 | |
3479 | static bfd_boolean | |
3480 | is_delay_slot_valid (const struct mips_opcode *mo) | |
3481 | { | |
3482 | if (!mips_opts.micromips) | |
3483 | return TRUE; | |
3484 | ||
3485 | if (mo->pinfo == INSN_MACRO) | |
c06dec14 | 3486 | return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0; |
df58fc94 RS |
3487 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 |
3488 | && micromips_insn_length (mo) != 4) | |
3489 | return FALSE; | |
3490 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 | |
3491 | && micromips_insn_length (mo) != 2) | |
3492 | return FALSE; | |
3493 | ||
3494 | return TRUE; | |
3495 | } | |
3496 | ||
fc76e730 RS |
3497 | /* For consistency checking, verify that all bits of OPCODE are specified |
3498 | either by the match/mask part of the instruction definition, or by the | |
3499 | operand list. Also build up a list of operands in OPERANDS. | |
3500 | ||
3501 | INSN_BITS says which bits of the instruction are significant. | |
3502 | If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND | |
3503 | provides the mips_operand description of each operand. DECODE_OPERAND | |
3504 | is null for MIPS16 instructions. */ | |
ab902481 RS |
3505 | |
3506 | static int | |
3507 | validate_mips_insn (const struct mips_opcode *opcode, | |
3508 | unsigned long insn_bits, | |
fc76e730 RS |
3509 | const struct mips_operand *(*decode_operand) (const char *), |
3510 | struct mips_operand_array *operands) | |
ab902481 RS |
3511 | { |
3512 | const char *s; | |
fc76e730 | 3513 | unsigned long used_bits, doubled, undefined, opno, mask; |
ab902481 RS |
3514 | const struct mips_operand *operand; |
3515 | ||
fc76e730 RS |
3516 | mask = (opcode->pinfo == INSN_MACRO ? 0 : opcode->mask); |
3517 | if ((mask & opcode->match) != opcode->match) | |
ab902481 RS |
3518 | { |
3519 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
3520 | opcode->name, opcode->args); | |
3521 | return 0; | |
3522 | } | |
3523 | used_bits = 0; | |
fc76e730 | 3524 | opno = 0; |
14daeee3 RS |
3525 | if (opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) |
3526 | used_bits = mips_insert_operand (&mips_vu0_channel_mask, used_bits, -1); | |
ab902481 RS |
3527 | for (s = opcode->args; *s; ++s) |
3528 | switch (*s) | |
3529 | { | |
3530 | case ',': | |
3531 | case '(': | |
3532 | case ')': | |
3533 | break; | |
3534 | ||
14daeee3 RS |
3535 | case '#': |
3536 | s++; | |
3537 | break; | |
3538 | ||
ab902481 | 3539 | default: |
fc76e730 | 3540 | if (!decode_operand) |
7fd53920 | 3541 | operand = decode_mips16_operand (*s, mips_opcode_32bit_p (opcode)); |
fc76e730 RS |
3542 | else |
3543 | operand = decode_operand (s); | |
3544 | if (!operand && opcode->pinfo != INSN_MACRO) | |
ab902481 RS |
3545 | { |
3546 | as_bad (_("internal: unknown operand type: %s %s"), | |
3547 | opcode->name, opcode->args); | |
3548 | return 0; | |
3549 | } | |
fc76e730 RS |
3550 | gas_assert (opno < MAX_OPERANDS); |
3551 | operands->operand[opno] = operand; | |
25499ac7 MR |
3552 | if (!decode_operand && operand |
3553 | && operand->type == OP_INT && operand->lsb == 0 | |
3554 | && mips_opcode_32bit_p (opcode)) | |
3555 | used_bits |= mips16_immed_extend (-1, operand->size); | |
3556 | else if (operand && operand->type != OP_VU0_MATCH_SUFFIX) | |
fc76e730 | 3557 | { |
14daeee3 | 3558 | used_bits = mips_insert_operand (operand, used_bits, -1); |
fc76e730 RS |
3559 | if (operand->type == OP_MDMX_IMM_REG) |
3560 | /* Bit 5 is the format selector (OB vs QH). The opcode table | |
3561 | has separate entries for each format. */ | |
3562 | used_bits &= ~(1 << (operand->lsb + 5)); | |
3563 | if (operand->type == OP_ENTRY_EXIT_LIST) | |
3564 | used_bits &= ~(mask & 0x700); | |
38bf472a MR |
3565 | /* interAptiv MR2 SAVE/RESTORE instructions have a discontiguous |
3566 | operand field that cannot be fully described with LSB/SIZE. */ | |
3567 | if (operand->type == OP_SAVE_RESTORE_LIST && operand->lsb == 6) | |
3568 | used_bits &= ~0x6000; | |
fc76e730 | 3569 | } |
ab902481 | 3570 | /* Skip prefix characters. */ |
7361da2c | 3571 | if (decode_operand && (*s == '+' || *s == 'm' || *s == '-')) |
ab902481 | 3572 | ++s; |
fc76e730 | 3573 | opno += 1; |
ab902481 RS |
3574 | break; |
3575 | } | |
fc76e730 | 3576 | doubled = used_bits & mask & insn_bits; |
ab902481 RS |
3577 | if (doubled) |
3578 | { | |
3579 | as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):" | |
3580 | " %s %s"), doubled, opcode->name, opcode->args); | |
3581 | return 0; | |
3582 | } | |
fc76e730 | 3583 | used_bits |= mask; |
ab902481 | 3584 | undefined = ~used_bits & insn_bits; |
fc76e730 | 3585 | if (opcode->pinfo != INSN_MACRO && undefined) |
ab902481 RS |
3586 | { |
3587 | as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"), | |
3588 | undefined, opcode->name, opcode->args); | |
3589 | return 0; | |
3590 | } | |
3591 | used_bits &= ~insn_bits; | |
3592 | if (used_bits) | |
3593 | { | |
3594 | as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"), | |
3595 | used_bits, opcode->name, opcode->args); | |
3596 | return 0; | |
3597 | } | |
3598 | return 1; | |
3599 | } | |
3600 | ||
fc76e730 RS |
3601 | /* The MIPS16 version of validate_mips_insn. */ |
3602 | ||
3603 | static int | |
3604 | validate_mips16_insn (const struct mips_opcode *opcode, | |
3605 | struct mips_operand_array *operands) | |
3606 | { | |
7fd53920 | 3607 | unsigned long insn_bits = mips_opcode_32bit_p (opcode) ? 0xffffffff : 0xffff; |
fc76e730 | 3608 | |
7fd53920 | 3609 | return validate_mips_insn (opcode, insn_bits, 0, operands); |
fc76e730 RS |
3610 | } |
3611 | ||
ab902481 RS |
3612 | /* The microMIPS version of validate_mips_insn. */ |
3613 | ||
3614 | static int | |
fc76e730 RS |
3615 | validate_micromips_insn (const struct mips_opcode *opc, |
3616 | struct mips_operand_array *operands) | |
ab902481 RS |
3617 | { |
3618 | unsigned long insn_bits; | |
3619 | unsigned long major; | |
3620 | unsigned int length; | |
3621 | ||
fc76e730 RS |
3622 | if (opc->pinfo == INSN_MACRO) |
3623 | return validate_mips_insn (opc, 0xffffffff, decode_micromips_operand, | |
3624 | operands); | |
3625 | ||
ab902481 RS |
3626 | length = micromips_insn_length (opc); |
3627 | if (length != 2 && length != 4) | |
3628 | { | |
1661c76c | 3629 | as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): " |
ab902481 RS |
3630 | "%s %s"), length, opc->name, opc->args); |
3631 | return 0; | |
3632 | } | |
3633 | major = opc->match >> (10 + 8 * (length - 2)); | |
3634 | if ((length == 2 && (major & 7) != 1 && (major & 6) != 2) | |
3635 | || (length == 4 && (major & 7) != 0 && (major & 4) != 4)) | |
3636 | { | |
1661c76c | 3637 | as_bad (_("internal error: bad microMIPS opcode " |
ab902481 RS |
3638 | "(opcode/length mismatch): %s %s"), opc->name, opc->args); |
3639 | return 0; | |
3640 | } | |
3641 | ||
3642 | /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */ | |
3643 | insn_bits = 1 << 4 * length; | |
3644 | insn_bits <<= 4 * length; | |
3645 | insn_bits -= 1; | |
fc76e730 RS |
3646 | return validate_mips_insn (opc, insn_bits, decode_micromips_operand, |
3647 | operands); | |
ab902481 RS |
3648 | } |
3649 | ||
707bfff6 TS |
3650 | /* This function is called once, at assembler startup time. It should set up |
3651 | all the tables, etc. that the MD part of the assembler will need. */ | |
156c2f8b | 3652 | |
252b5132 | 3653 | void |
17a2f251 | 3654 | md_begin (void) |
252b5132 | 3655 | { |
3994f87e | 3656 | const char *retval = NULL; |
156c2f8b | 3657 | int i = 0; |
252b5132 | 3658 | int broken = 0; |
1f25f5d3 | 3659 | |
0a44bf69 RS |
3660 | if (mips_pic != NO_PIC) |
3661 | { | |
3662 | if (g_switch_seen && g_switch_value != 0) | |
3663 | as_bad (_("-G may not be used in position-independent code")); | |
3664 | g_switch_value = 0; | |
3665 | } | |
00acd688 CM |
3666 | else if (mips_abicalls) |
3667 | { | |
3668 | if (g_switch_seen && g_switch_value != 0) | |
3669 | as_bad (_("-G may not be used with abicalls")); | |
3670 | g_switch_value = 0; | |
3671 | } | |
0a44bf69 | 3672 | |
0b35dfee | 3673 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch)) |
1661c76c | 3674 | as_warn (_("could not set architecture and machine")); |
252b5132 | 3675 | |
252b5132 RH |
3676 | op_hash = hash_new (); |
3677 | ||
fc76e730 | 3678 | mips_operands = XCNEWVEC (struct mips_operand_array, NUMOPCODES); |
252b5132 RH |
3679 | for (i = 0; i < NUMOPCODES;) |
3680 | { | |
3681 | const char *name = mips_opcodes[i].name; | |
3682 | ||
17a2f251 | 3683 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
3684 | if (retval != NULL) |
3685 | { | |
3686 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
3687 | mips_opcodes[i].name, retval); | |
3688 | /* Probably a memory allocation problem? Give up now. */ | |
1661c76c | 3689 | as_fatal (_("broken assembler, no assembly attempted")); |
252b5132 RH |
3690 | } |
3691 | do | |
3692 | { | |
fc76e730 RS |
3693 | if (!validate_mips_insn (&mips_opcodes[i], 0xffffffff, |
3694 | decode_mips_operand, &mips_operands[i])) | |
3695 | broken = 1; | |
6f2117ba | 3696 | |
fc76e730 | 3697 | if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
252b5132 | 3698 | { |
fc76e730 RS |
3699 | create_insn (&nop_insn, mips_opcodes + i); |
3700 | if (mips_fix_loongson2f_nop) | |
3701 | nop_insn.insn_opcode = LOONGSON2F_NOP_INSN; | |
3702 | nop_insn.fixed_p = 1; | |
252b5132 | 3703 | } |
6f2117ba PH |
3704 | |
3705 | if (sync_insn.insn_mo == NULL && strcmp (name, "sync") == 0) | |
3706 | create_insn (&sync_insn, mips_opcodes + i); | |
3707 | ||
252b5132 RH |
3708 | ++i; |
3709 | } | |
3710 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
3711 | } | |
3712 | ||
3713 | mips16_op_hash = hash_new (); | |
fc76e730 RS |
3714 | mips16_operands = XCNEWVEC (struct mips_operand_array, |
3715 | bfd_mips16_num_opcodes); | |
252b5132 RH |
3716 | |
3717 | i = 0; | |
3718 | while (i < bfd_mips16_num_opcodes) | |
3719 | { | |
3720 | const char *name = mips16_opcodes[i].name; | |
3721 | ||
17a2f251 | 3722 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
3723 | if (retval != NULL) |
3724 | as_fatal (_("internal: can't hash `%s': %s"), | |
3725 | mips16_opcodes[i].name, retval); | |
3726 | do | |
3727 | { | |
fc76e730 RS |
3728 | if (!validate_mips16_insn (&mips16_opcodes[i], &mips16_operands[i])) |
3729 | broken = 1; | |
1e915849 RS |
3730 | if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
3731 | { | |
3732 | create_insn (&mips16_nop_insn, mips16_opcodes + i); | |
3733 | mips16_nop_insn.fixed_p = 1; | |
3734 | } | |
252b5132 RH |
3735 | ++i; |
3736 | } | |
3737 | while (i < bfd_mips16_num_opcodes | |
3738 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
3739 | } | |
3740 | ||
df58fc94 | 3741 | micromips_op_hash = hash_new (); |
fc76e730 RS |
3742 | micromips_operands = XCNEWVEC (struct mips_operand_array, |
3743 | bfd_micromips_num_opcodes); | |
df58fc94 RS |
3744 | |
3745 | i = 0; | |
3746 | while (i < bfd_micromips_num_opcodes) | |
3747 | { | |
3748 | const char *name = micromips_opcodes[i].name; | |
3749 | ||
3750 | retval = hash_insert (micromips_op_hash, name, | |
3751 | (void *) µmips_opcodes[i]); | |
3752 | if (retval != NULL) | |
3753 | as_fatal (_("internal: can't hash `%s': %s"), | |
3754 | micromips_opcodes[i].name, retval); | |
3755 | do | |
fc76e730 RS |
3756 | { |
3757 | struct mips_cl_insn *micromips_nop_insn; | |
3758 | ||
3759 | if (!validate_micromips_insn (µmips_opcodes[i], | |
3760 | µmips_operands[i])) | |
3761 | broken = 1; | |
3762 | ||
3763 | if (micromips_opcodes[i].pinfo != INSN_MACRO) | |
3764 | { | |
3765 | if (micromips_insn_length (micromips_opcodes + i) == 2) | |
3766 | micromips_nop_insn = µmips_nop16_insn; | |
3767 | else if (micromips_insn_length (micromips_opcodes + i) == 4) | |
3768 | micromips_nop_insn = µmips_nop32_insn; | |
3769 | else | |
3770 | continue; | |
3771 | ||
3772 | if (micromips_nop_insn->insn_mo == NULL | |
3773 | && strcmp (name, "nop") == 0) | |
3774 | { | |
3775 | create_insn (micromips_nop_insn, micromips_opcodes + i); | |
3776 | micromips_nop_insn->fixed_p = 1; | |
3777 | } | |
3778 | } | |
3779 | } | |
df58fc94 RS |
3780 | while (++i < bfd_micromips_num_opcodes |
3781 | && strcmp (micromips_opcodes[i].name, name) == 0); | |
3782 | } | |
3783 | ||
252b5132 | 3784 | if (broken) |
1661c76c | 3785 | as_fatal (_("broken assembler, no assembly attempted")); |
252b5132 RH |
3786 | |
3787 | /* We add all the general register names to the symbol table. This | |
3788 | helps us detect invalid uses of them. */ | |
3739860c | 3789 | for (i = 0; reg_names[i].name; i++) |
707bfff6 | 3790 | symbol_table_insert (symbol_new (reg_names[i].name, reg_section, |
8fc4ee9b | 3791 | reg_names[i].num, /* & RNUM_MASK, */ |
707bfff6 TS |
3792 | &zero_address_frag)); |
3793 | if (HAVE_NEWABI) | |
3739860c | 3794 | for (i = 0; reg_names_n32n64[i].name; i++) |
707bfff6 | 3795 | symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section, |
8fc4ee9b | 3796 | reg_names_n32n64[i].num, /* & RNUM_MASK, */ |
252b5132 | 3797 | &zero_address_frag)); |
707bfff6 | 3798 | else |
3739860c | 3799 | for (i = 0; reg_names_o32[i].name; i++) |
707bfff6 | 3800 | symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section, |
8fc4ee9b | 3801 | reg_names_o32[i].num, /* & RNUM_MASK, */ |
6047c971 | 3802 | &zero_address_frag)); |
6047c971 | 3803 | |
14daeee3 RS |
3804 | for (i = 0; i < 32; i++) |
3805 | { | |
92fce9bd | 3806 | char regname[6]; |
14daeee3 RS |
3807 | |
3808 | /* R5900 VU0 floating-point register. */ | |
92fce9bd | 3809 | sprintf (regname, "$vf%d", i); |
14daeee3 RS |
3810 | symbol_table_insert (symbol_new (regname, reg_section, |
3811 | RTYPE_VF | i, &zero_address_frag)); | |
3812 | ||
3813 | /* R5900 VU0 integer register. */ | |
92fce9bd | 3814 | sprintf (regname, "$vi%d", i); |
14daeee3 RS |
3815 | symbol_table_insert (symbol_new (regname, reg_section, |
3816 | RTYPE_VI | i, &zero_address_frag)); | |
3817 | ||
56d438b1 | 3818 | /* MSA register. */ |
92fce9bd | 3819 | sprintf (regname, "$w%d", i); |
56d438b1 CF |
3820 | symbol_table_insert (symbol_new (regname, reg_section, |
3821 | RTYPE_MSA | i, &zero_address_frag)); | |
14daeee3 RS |
3822 | } |
3823 | ||
a92713e6 RS |
3824 | obstack_init (&mips_operand_tokens); |
3825 | ||
7d10b47d | 3826 | mips_no_prev_insn (); |
252b5132 RH |
3827 | |
3828 | mips_gprmask = 0; | |
3829 | mips_cprmask[0] = 0; | |
3830 | mips_cprmask[1] = 0; | |
3831 | mips_cprmask[2] = 0; | |
3832 | mips_cprmask[3] = 0; | |
3833 | ||
3834 | /* set the default alignment for the text section (2**2) */ | |
3835 | record_alignment (text_section, 2); | |
3836 | ||
4d0d148d | 3837 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 | 3838 | |
f3ded42a RS |
3839 | /* On a native system other than VxWorks, sections must be aligned |
3840 | to 16 byte boundaries. When configured for an embedded ELF | |
3841 | target, we don't bother. */ | |
3842 | if (strncmp (TARGET_OS, "elf", 3) != 0 | |
3843 | && strncmp (TARGET_OS, "vxworks", 7) != 0) | |
252b5132 | 3844 | { |
f3ded42a RS |
3845 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); |
3846 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
3847 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
3848 | } | |
252b5132 | 3849 | |
f3ded42a RS |
3850 | /* Create a .reginfo section for register masks and a .mdebug |
3851 | section for debugging information. */ | |
3852 | { | |
3853 | segT seg; | |
3854 | subsegT subseg; | |
3855 | flagword flags; | |
3856 | segT sec; | |
3857 | ||
3858 | seg = now_seg; | |
3859 | subseg = now_subseg; | |
3860 | ||
3861 | /* The ABI says this section should be loaded so that the | |
3862 | running program can access it. However, we don't load it | |
6f2117ba | 3863 | if we are configured for an embedded target. */ |
f3ded42a RS |
3864 | flags = SEC_READONLY | SEC_DATA; |
3865 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
3866 | flags |= SEC_ALLOC | SEC_LOAD; | |
3867 | ||
3868 | if (mips_abi != N64_ABI) | |
252b5132 | 3869 | { |
f3ded42a | 3870 | sec = subseg_new (".reginfo", (subsegT) 0); |
bdaaa2e1 | 3871 | |
f3ded42a RS |
3872 | bfd_set_section_flags (stdoutput, sec, flags); |
3873 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
252b5132 | 3874 | |
f3ded42a RS |
3875 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
3876 | } | |
3877 | else | |
3878 | { | |
3879 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
3880 | .reginfo section. */ | |
3881 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
3882 | bfd_set_section_flags (stdoutput, sec, flags); | |
3883 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 | 3884 | |
f3ded42a RS |
3885 | /* Set up the option header. */ |
3886 | { | |
3887 | Elf_Internal_Options opthdr; | |
3888 | char *f; | |
3889 | ||
3890 | opthdr.kind = ODK_REGINFO; | |
3891 | opthdr.size = (sizeof (Elf_External_Options) | |
3892 | + sizeof (Elf64_External_RegInfo)); | |
3893 | opthdr.section = 0; | |
3894 | opthdr.info = 0; | |
3895 | f = frag_more (sizeof (Elf_External_Options)); | |
3896 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
3897 | (Elf_External_Options *) f); | |
3898 | ||
3899 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
3900 | } | |
3901 | } | |
252b5132 | 3902 | |
351cdf24 MF |
3903 | sec = subseg_new (".MIPS.abiflags", (subsegT) 0); |
3904 | bfd_set_section_flags (stdoutput, sec, | |
3905 | SEC_READONLY | SEC_DATA | SEC_ALLOC | SEC_LOAD); | |
3906 | bfd_set_section_alignment (stdoutput, sec, 3); | |
3907 | mips_flags_frag = frag_more (sizeof (Elf_External_ABIFlags_v0)); | |
3908 | ||
f3ded42a RS |
3909 | if (ECOFF_DEBUGGING) |
3910 | { | |
3911 | sec = subseg_new (".mdebug", (subsegT) 0); | |
3912 | (void) bfd_set_section_flags (stdoutput, sec, | |
3913 | SEC_HAS_CONTENTS | SEC_READONLY); | |
3914 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
252b5132 | 3915 | } |
f3ded42a RS |
3916 | else if (mips_flag_pdr) |
3917 | { | |
3918 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
3919 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
3920 | SEC_READONLY | SEC_RELOC | |
3921 | | SEC_DEBUGGING); | |
3922 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
3923 | } | |
3924 | ||
3925 | subseg_set (seg, subseg); | |
3926 | } | |
252b5132 | 3927 | |
71400594 RS |
3928 | if (mips_fix_vr4120) |
3929 | init_vr4120_conflicts (); | |
252b5132 RH |
3930 | } |
3931 | ||
351cdf24 MF |
3932 | static inline void |
3933 | fpabi_incompatible_with (int fpabi, const char *what) | |
3934 | { | |
3935 | as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"), | |
3936 | Tag_GNU_MIPS_ABI_FP, fpabi, what); | |
3937 | } | |
3938 | ||
3939 | static inline void | |
3940 | fpabi_requires (int fpabi, const char *what) | |
3941 | { | |
3942 | as_warn (_(".gnu_attribute %d,%d requires `%s'"), | |
3943 | Tag_GNU_MIPS_ABI_FP, fpabi, what); | |
3944 | } | |
3945 | ||
3946 | /* Check -mabi and register sizes against the specified FP ABI. */ | |
3947 | static void | |
3948 | check_fpabi (int fpabi) | |
3949 | { | |
351cdf24 MF |
3950 | switch (fpabi) |
3951 | { | |
3952 | case Val_GNU_MIPS_ABI_FP_DOUBLE: | |
ea79f94a MF |
3953 | if (file_mips_opts.soft_float) |
3954 | fpabi_incompatible_with (fpabi, "softfloat"); | |
3955 | else if (file_mips_opts.single_float) | |
3956 | fpabi_incompatible_with (fpabi, "singlefloat"); | |
351cdf24 MF |
3957 | if (file_mips_opts.gp == 64 && file_mips_opts.fp == 32) |
3958 | fpabi_incompatible_with (fpabi, "gp=64 fp=32"); | |
3959 | else if (file_mips_opts.gp == 32 && file_mips_opts.fp == 64) | |
3960 | fpabi_incompatible_with (fpabi, "gp=32 fp=64"); | |
351cdf24 MF |
3961 | break; |
3962 | ||
3963 | case Val_GNU_MIPS_ABI_FP_XX: | |
3964 | if (mips_abi != O32_ABI) | |
3965 | fpabi_requires (fpabi, "-mabi=32"); | |
ea79f94a MF |
3966 | else if (file_mips_opts.soft_float) |
3967 | fpabi_incompatible_with (fpabi, "softfloat"); | |
3968 | else if (file_mips_opts.single_float) | |
3969 | fpabi_incompatible_with (fpabi, "singlefloat"); | |
351cdf24 MF |
3970 | else if (file_mips_opts.fp != 0) |
3971 | fpabi_requires (fpabi, "fp=xx"); | |
351cdf24 MF |
3972 | break; |
3973 | ||
3974 | case Val_GNU_MIPS_ABI_FP_64A: | |
3975 | case Val_GNU_MIPS_ABI_FP_64: | |
3976 | if (mips_abi != O32_ABI) | |
3977 | fpabi_requires (fpabi, "-mabi=32"); | |
ea79f94a MF |
3978 | else if (file_mips_opts.soft_float) |
3979 | fpabi_incompatible_with (fpabi, "softfloat"); | |
3980 | else if (file_mips_opts.single_float) | |
3981 | fpabi_incompatible_with (fpabi, "singlefloat"); | |
351cdf24 MF |
3982 | else if (file_mips_opts.fp != 64) |
3983 | fpabi_requires (fpabi, "fp=64"); | |
3984 | else if (fpabi == Val_GNU_MIPS_ABI_FP_64 && !file_mips_opts.oddspreg) | |
3985 | fpabi_incompatible_with (fpabi, "nooddspreg"); | |
3986 | else if (fpabi == Val_GNU_MIPS_ABI_FP_64A && file_mips_opts.oddspreg) | |
3987 | fpabi_requires (fpabi, "nooddspreg"); | |
351cdf24 MF |
3988 | break; |
3989 | ||
3990 | case Val_GNU_MIPS_ABI_FP_SINGLE: | |
3991 | if (file_mips_opts.soft_float) | |
3992 | fpabi_incompatible_with (fpabi, "softfloat"); | |
3993 | else if (!file_mips_opts.single_float) | |
3994 | fpabi_requires (fpabi, "singlefloat"); | |
3995 | break; | |
3996 | ||
3997 | case Val_GNU_MIPS_ABI_FP_SOFT: | |
3998 | if (!file_mips_opts.soft_float) | |
3999 | fpabi_requires (fpabi, "softfloat"); | |
4000 | break; | |
4001 | ||
4002 | case Val_GNU_MIPS_ABI_FP_OLD_64: | |
4003 | as_warn (_(".gnu_attribute %d,%d is no longer supported"), | |
4004 | Tag_GNU_MIPS_ABI_FP, fpabi); | |
4005 | break; | |
4006 | ||
3350cc01 CM |
4007 | case Val_GNU_MIPS_ABI_FP_NAN2008: |
4008 | /* Silently ignore compatibility value. */ | |
4009 | break; | |
4010 | ||
351cdf24 MF |
4011 | default: |
4012 | as_warn (_(".gnu_attribute %d,%d is not a recognized" | |
4013 | " floating-point ABI"), Tag_GNU_MIPS_ABI_FP, fpabi); | |
4014 | break; | |
4015 | } | |
351cdf24 MF |
4016 | } |
4017 | ||
919731af | 4018 | /* Perform consistency checks on the current options. */ |
4019 | ||
4020 | static void | |
4021 | mips_check_options (struct mips_set_options *opts, bfd_boolean abi_checks) | |
4022 | { | |
4023 | /* Check the size of integer registers agrees with the ABI and ISA. */ | |
4024 | if (opts->gp == 64 && !ISA_HAS_64BIT_REGS (opts->isa)) | |
4025 | as_bad (_("`gp=64' used with a 32-bit processor")); | |
4026 | else if (abi_checks | |
4027 | && opts->gp == 32 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
4028 | as_bad (_("`gp=32' used with a 64-bit ABI")); | |
4029 | else if (abi_checks | |
4030 | && opts->gp == 64 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
4031 | as_bad (_("`gp=64' used with a 32-bit ABI")); | |
4032 | ||
4033 | /* Check the size of the float registers agrees with the ABI and ISA. */ | |
4034 | switch (opts->fp) | |
4035 | { | |
351cdf24 MF |
4036 | case 0: |
4037 | if (!CPU_HAS_LDC1_SDC1 (opts->arch)) | |
4038 | as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions")); | |
4039 | else if (opts->single_float == 1) | |
4040 | as_bad (_("`fp=xx' cannot be used with `singlefloat'")); | |
4041 | break; | |
919731af | 4042 | case 64: |
4043 | if (!ISA_HAS_64BIT_FPRS (opts->isa)) | |
4044 | as_bad (_("`fp=64' used with a 32-bit fpu")); | |
4045 | else if (abi_checks | |
4046 | && ABI_NEEDS_32BIT_REGS (mips_abi) | |
4047 | && !ISA_HAS_MXHC1 (opts->isa)) | |
4048 | as_warn (_("`fp=64' used with a 32-bit ABI")); | |
4049 | break; | |
4050 | case 32: | |
4051 | if (abi_checks | |
4052 | && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
4053 | as_warn (_("`fp=32' used with a 64-bit ABI")); | |
5f4678bb | 4054 | if (ISA_IS_R6 (opts->isa) && opts->single_float == 0) |
7361da2c | 4055 | as_bad (_("`fp=32' used with a MIPS R6 cpu")); |
919731af | 4056 | break; |
4057 | default: | |
4058 | as_bad (_("Unknown size of floating point registers")); | |
4059 | break; | |
4060 | } | |
4061 | ||
351cdf24 MF |
4062 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !opts->oddspreg) |
4063 | as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI")); | |
4064 | ||
919731af | 4065 | if (opts->micromips == 1 && opts->mips16 == 1) |
1357373c | 4066 | as_bad (_("`%s' cannot be used with `%s'"), "mips16", "micromips"); |
5f4678bb | 4067 | else if (ISA_IS_R6 (opts->isa) |
7361da2c AB |
4068 | && (opts->micromips == 1 |
4069 | || opts->mips16 == 1)) | |
1357373c | 4070 | as_fatal (_("`%s' cannot be used with `%s'"), |
7361da2c | 4071 | opts->micromips ? "micromips" : "mips16", |
5f4678bb | 4072 | mips_cpu_info_from_isa (opts->isa)->name); |
7361da2c AB |
4073 | |
4074 | if (ISA_IS_R6 (opts->isa) && mips_relax_branch) | |
4075 | as_fatal (_("branch relaxation is not supported in `%s'"), | |
4076 | mips_cpu_info_from_isa (opts->isa)->name); | |
919731af | 4077 | } |
4078 | ||
4079 | /* Perform consistency checks on the module level options exactly once. | |
4080 | This is a deferred check that happens: | |
4081 | at the first .set directive | |
4082 | or, at the first pseudo op that generates code (inc .dc.a) | |
4083 | or, at the first instruction | |
4084 | or, at the end. */ | |
4085 | ||
4086 | static void | |
4087 | file_mips_check_options (void) | |
4088 | { | |
4089 | const struct mips_cpu_info *arch_info = 0; | |
4090 | ||
4091 | if (file_mips_opts_checked) | |
4092 | return; | |
4093 | ||
4094 | /* The following code determines the register size. | |
4095 | Similar code was added to GCC 3.3 (see override_options() in | |
4096 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
4097 | as much as possible. */ | |
4098 | ||
4099 | if (file_mips_opts.gp < 0) | |
4100 | { | |
4101 | /* Infer the integer register size from the ABI and processor. | |
4102 | Restrict ourselves to 32-bit registers if that's all the | |
4103 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
4104 | file_mips_opts.gp = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
4105 | || !ISA_HAS_64BIT_REGS (file_mips_opts.isa)) | |
4106 | ? 32 : 64; | |
4107 | } | |
4108 | ||
4109 | if (file_mips_opts.fp < 0) | |
4110 | { | |
4111 | /* No user specified float register size. | |
4112 | ??? GAS treats single-float processors as though they had 64-bit | |
4113 | float registers (although it complains when double-precision | |
4114 | instructions are used). As things stand, saying they have 32-bit | |
4115 | registers would lead to spurious "register must be even" messages. | |
4116 | So here we assume float registers are never smaller than the | |
4117 | integer ones. */ | |
4118 | if (file_mips_opts.gp == 64) | |
4119 | /* 64-bit integer registers implies 64-bit float registers. */ | |
4120 | file_mips_opts.fp = 64; | |
4121 | else if ((file_mips_opts.ase & FP64_ASES) | |
4122 | && ISA_HAS_64BIT_FPRS (file_mips_opts.isa)) | |
4123 | /* Handle ASEs that require 64-bit float registers, if possible. */ | |
4124 | file_mips_opts.fp = 64; | |
7361da2c AB |
4125 | else if (ISA_IS_R6 (mips_opts.isa)) |
4126 | /* R6 implies 64-bit float registers. */ | |
4127 | file_mips_opts.fp = 64; | |
919731af | 4128 | else |
4129 | /* 32-bit float registers. */ | |
4130 | file_mips_opts.fp = 32; | |
4131 | } | |
4132 | ||
4133 | arch_info = mips_cpu_info_from_arch (file_mips_opts.arch); | |
4134 | ||
351cdf24 MF |
4135 | /* Disable operations on odd-numbered floating-point registers by default |
4136 | when using the FPXX ABI. */ | |
4137 | if (file_mips_opts.oddspreg < 0) | |
4138 | { | |
4139 | if (file_mips_opts.fp == 0) | |
4140 | file_mips_opts.oddspreg = 0; | |
4141 | else | |
4142 | file_mips_opts.oddspreg = 1; | |
4143 | } | |
4144 | ||
919731af | 4145 | /* End of GCC-shared inference code. */ |
4146 | ||
4147 | /* This flag is set when we have a 64-bit capable CPU but use only | |
4148 | 32-bit wide registers. Note that EABI does not use it. */ | |
4149 | if (ISA_HAS_64BIT_REGS (file_mips_opts.isa) | |
4150 | && ((mips_abi == NO_ABI && file_mips_opts.gp == 32) | |
4151 | || mips_abi == O32_ABI)) | |
4152 | mips_32bitmode = 1; | |
4153 | ||
4154 | if (file_mips_opts.isa == ISA_MIPS1 && mips_trap) | |
4155 | as_bad (_("trap exception not supported at ISA 1")); | |
4156 | ||
4157 | /* If the selected architecture includes support for ASEs, enable | |
4158 | generation of code for them. */ | |
4159 | if (file_mips_opts.mips16 == -1) | |
4160 | file_mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_opts.arch)) ? 1 : 0; | |
4161 | if (file_mips_opts.micromips == -1) | |
4162 | file_mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_opts.arch)) | |
4163 | ? 1 : 0; | |
4164 | ||
7361da2c AB |
4165 | if (mips_nan2008 == -1) |
4166 | mips_nan2008 = (ISA_HAS_LEGACY_NAN (file_mips_opts.isa)) ? 0 : 1; | |
4167 | else if (!ISA_HAS_LEGACY_NAN (file_mips_opts.isa) && mips_nan2008 == 0) | |
4168 | as_fatal (_("`%s' does not support legacy NaN"), | |
4169 | mips_cpu_info_from_arch (file_mips_opts.arch)->name); | |
4170 | ||
919731af | 4171 | /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from |
4172 | being selected implicitly. */ | |
4173 | if (file_mips_opts.fp != 64) | |
4174 | file_ase_explicit |= ASE_MIPS3D | ASE_MDMX | ASE_MSA; | |
4175 | ||
4176 | /* If the user didn't explicitly select or deselect a particular ASE, | |
4177 | use the default setting for the CPU. */ | |
4178 | file_mips_opts.ase |= (arch_info->ase & ~file_ase_explicit); | |
4179 | ||
4180 | /* Set up the current options. These may change throughout assembly. */ | |
4181 | mips_opts = file_mips_opts; | |
4182 | ||
4183 | mips_check_isa_supports_ases (); | |
4184 | mips_check_options (&file_mips_opts, TRUE); | |
4185 | file_mips_opts_checked = TRUE; | |
4186 | ||
4187 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch)) | |
4188 | as_warn (_("could not set architecture and machine")); | |
4189 | } | |
4190 | ||
252b5132 | 4191 | void |
17a2f251 | 4192 | md_assemble (char *str) |
252b5132 RH |
4193 | { |
4194 | struct mips_cl_insn insn; | |
f6688943 TS |
4195 | bfd_reloc_code_real_type unused_reloc[3] |
4196 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 4197 | |
919731af | 4198 | file_mips_check_options (); |
4199 | ||
252b5132 | 4200 | imm_expr.X_op = O_absent; |
252b5132 | 4201 | offset_expr.X_op = O_absent; |
f6688943 TS |
4202 | offset_reloc[0] = BFD_RELOC_UNUSED; |
4203 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
4204 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 | 4205 | |
e1b47bd5 RS |
4206 | mips_mark_labels (); |
4207 | mips_assembling_insn = TRUE; | |
e3de51ce | 4208 | clear_insn_error (); |
e1b47bd5 | 4209 | |
252b5132 RH |
4210 | if (mips_opts.mips16) |
4211 | mips16_ip (str, &insn); | |
4212 | else | |
4213 | { | |
4214 | mips_ip (str, &insn); | |
beae10d5 KH |
4215 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
4216 | str, insn.insn_opcode)); | |
252b5132 RH |
4217 | } |
4218 | ||
e3de51ce RS |
4219 | if (insn_error.msg) |
4220 | report_insn_error (str); | |
e1b47bd5 | 4221 | else if (insn.insn_mo->pinfo == INSN_MACRO) |
252b5132 | 4222 | { |
584892a6 | 4223 | macro_start (); |
252b5132 RH |
4224 | if (mips_opts.mips16) |
4225 | mips16_macro (&insn); | |
4226 | else | |
833794fc | 4227 | macro (&insn, str); |
584892a6 | 4228 | macro_end (); |
252b5132 RH |
4229 | } |
4230 | else | |
4231 | { | |
77bd4346 | 4232 | if (offset_expr.X_op != O_absent) |
df58fc94 | 4233 | append_insn (&insn, &offset_expr, offset_reloc, FALSE); |
252b5132 | 4234 | else |
df58fc94 | 4235 | append_insn (&insn, NULL, unused_reloc, FALSE); |
252b5132 | 4236 | } |
e1b47bd5 RS |
4237 | |
4238 | mips_assembling_insn = FALSE; | |
252b5132 RH |
4239 | } |
4240 | ||
738e5348 RS |
4241 | /* Convenience functions for abstracting away the differences between |
4242 | MIPS16 and non-MIPS16 relocations. */ | |
4243 | ||
4244 | static inline bfd_boolean | |
4245 | mips16_reloc_p (bfd_reloc_code_real_type reloc) | |
4246 | { | |
4247 | switch (reloc) | |
4248 | { | |
4249 | case BFD_RELOC_MIPS16_JMP: | |
4250 | case BFD_RELOC_MIPS16_GPREL: | |
4251 | case BFD_RELOC_MIPS16_GOT16: | |
4252 | case BFD_RELOC_MIPS16_CALL16: | |
4253 | case BFD_RELOC_MIPS16_HI16_S: | |
4254 | case BFD_RELOC_MIPS16_HI16: | |
4255 | case BFD_RELOC_MIPS16_LO16: | |
c9775dde | 4256 | case BFD_RELOC_MIPS16_16_PCREL_S1: |
738e5348 RS |
4257 | return TRUE; |
4258 | ||
4259 | default: | |
4260 | return FALSE; | |
4261 | } | |
4262 | } | |
4263 | ||
df58fc94 RS |
4264 | static inline bfd_boolean |
4265 | micromips_reloc_p (bfd_reloc_code_real_type reloc) | |
4266 | { | |
4267 | switch (reloc) | |
4268 | { | |
4269 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: | |
4270 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
4271 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
4272 | case BFD_RELOC_MICROMIPS_GPREL16: | |
4273 | case BFD_RELOC_MICROMIPS_JMP: | |
4274 | case BFD_RELOC_MICROMIPS_HI16: | |
4275 | case BFD_RELOC_MICROMIPS_HI16_S: | |
4276 | case BFD_RELOC_MICROMIPS_LO16: | |
4277 | case BFD_RELOC_MICROMIPS_LITERAL: | |
4278 | case BFD_RELOC_MICROMIPS_GOT16: | |
4279 | case BFD_RELOC_MICROMIPS_CALL16: | |
4280 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
4281 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
4282 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
4283 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
4284 | case BFD_RELOC_MICROMIPS_SUB: | |
4285 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
4286 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
4287 | case BFD_RELOC_MICROMIPS_GOT_DISP: | |
4288 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
4289 | case BFD_RELOC_MICROMIPS_HIGHER: | |
4290 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
4291 | case BFD_RELOC_MICROMIPS_JALR: | |
4292 | return TRUE; | |
4293 | ||
4294 | default: | |
4295 | return FALSE; | |
4296 | } | |
4297 | } | |
4298 | ||
2309ddf2 MR |
4299 | static inline bfd_boolean |
4300 | jmp_reloc_p (bfd_reloc_code_real_type reloc) | |
4301 | { | |
4302 | return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP; | |
4303 | } | |
4304 | ||
0e9c5a5c MR |
4305 | static inline bfd_boolean |
4306 | b_reloc_p (bfd_reloc_code_real_type reloc) | |
4307 | { | |
4308 | return (reloc == BFD_RELOC_MIPS_26_PCREL_S2 | |
4309 | || reloc == BFD_RELOC_MIPS_21_PCREL_S2 | |
4310 | || reloc == BFD_RELOC_16_PCREL_S2 | |
c9775dde | 4311 | || reloc == BFD_RELOC_MIPS16_16_PCREL_S1 |
0e9c5a5c MR |
4312 | || reloc == BFD_RELOC_MICROMIPS_16_PCREL_S1 |
4313 | || reloc == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
4314 | || reloc == BFD_RELOC_MICROMIPS_7_PCREL_S1); | |
4315 | } | |
4316 | ||
738e5348 RS |
4317 | static inline bfd_boolean |
4318 | got16_reloc_p (bfd_reloc_code_real_type reloc) | |
4319 | { | |
2309ddf2 | 4320 | return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16 |
df58fc94 | 4321 | || reloc == BFD_RELOC_MICROMIPS_GOT16); |
738e5348 RS |
4322 | } |
4323 | ||
4324 | static inline bfd_boolean | |
4325 | hi16_reloc_p (bfd_reloc_code_real_type reloc) | |
4326 | { | |
2309ddf2 | 4327 | return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S |
df58fc94 | 4328 | || reloc == BFD_RELOC_MICROMIPS_HI16_S); |
738e5348 RS |
4329 | } |
4330 | ||
4331 | static inline bfd_boolean | |
4332 | lo16_reloc_p (bfd_reloc_code_real_type reloc) | |
4333 | { | |
2309ddf2 | 4334 | return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16 |
df58fc94 RS |
4335 | || reloc == BFD_RELOC_MICROMIPS_LO16); |
4336 | } | |
4337 | ||
df58fc94 RS |
4338 | static inline bfd_boolean |
4339 | jalr_reloc_p (bfd_reloc_code_real_type reloc) | |
4340 | { | |
2309ddf2 | 4341 | return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR; |
738e5348 RS |
4342 | } |
4343 | ||
f2ae14a1 RS |
4344 | static inline bfd_boolean |
4345 | gprel16_reloc_p (bfd_reloc_code_real_type reloc) | |
4346 | { | |
4347 | return (reloc == BFD_RELOC_GPREL16 || reloc == BFD_RELOC_MIPS16_GPREL | |
4348 | || reloc == BFD_RELOC_MICROMIPS_GPREL16); | |
4349 | } | |
4350 | ||
2de39019 CM |
4351 | /* Return true if RELOC is a PC-relative relocation that does not have |
4352 | full address range. */ | |
4353 | ||
4354 | static inline bfd_boolean | |
4355 | limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc) | |
4356 | { | |
4357 | switch (reloc) | |
4358 | { | |
4359 | case BFD_RELOC_16_PCREL_S2: | |
c9775dde | 4360 | case BFD_RELOC_MIPS16_16_PCREL_S1: |
2de39019 CM |
4361 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
4362 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
4363 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
7361da2c AB |
4364 | case BFD_RELOC_MIPS_21_PCREL_S2: |
4365 | case BFD_RELOC_MIPS_26_PCREL_S2: | |
4366 | case BFD_RELOC_MIPS_18_PCREL_S3: | |
4367 | case BFD_RELOC_MIPS_19_PCREL_S2: | |
2de39019 CM |
4368 | return TRUE; |
4369 | ||
b47468a6 | 4370 | case BFD_RELOC_32_PCREL: |
7361da2c AB |
4371 | case BFD_RELOC_HI16_S_PCREL: |
4372 | case BFD_RELOC_LO16_PCREL: | |
b47468a6 CM |
4373 | return HAVE_64BIT_ADDRESSES; |
4374 | ||
2de39019 CM |
4375 | default: |
4376 | return FALSE; | |
4377 | } | |
4378 | } | |
b47468a6 | 4379 | |
5919d012 | 4380 | /* Return true if the given relocation might need a matching %lo(). |
0a44bf69 RS |
4381 | This is only "might" because SVR4 R_MIPS_GOT16 relocations only |
4382 | need a matching %lo() when applied to local symbols. */ | |
5919d012 RS |
4383 | |
4384 | static inline bfd_boolean | |
17a2f251 | 4385 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 4386 | { |
3b91255e | 4387 | return (HAVE_IN_PLACE_ADDENDS |
738e5348 | 4388 | && (hi16_reloc_p (reloc) |
0a44bf69 RS |
4389 | /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo(); |
4390 | all GOT16 relocations evaluate to "G". */ | |
738e5348 RS |
4391 | || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC))); |
4392 | } | |
4393 | ||
4394 | /* Return the type of %lo() reloc needed by RELOC, given that | |
4395 | reloc_needs_lo_p. */ | |
4396 | ||
4397 | static inline bfd_reloc_code_real_type | |
4398 | matching_lo_reloc (bfd_reloc_code_real_type reloc) | |
4399 | { | |
df58fc94 RS |
4400 | return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 |
4401 | : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16 | |
4402 | : BFD_RELOC_LO16)); | |
5919d012 RS |
4403 | } |
4404 | ||
4405 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
4406 | relocation. */ | |
4407 | ||
4408 | static inline bfd_boolean | |
17a2f251 | 4409 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
4410 | { |
4411 | return (fixp->fx_next != NULL | |
738e5348 | 4412 | && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type) |
5919d012 RS |
4413 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
4414 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
4415 | } | |
4416 | ||
462427c4 RS |
4417 | /* Move all labels in LABELS to the current insertion point. TEXT_P |
4418 | says whether the labels refer to text or data. */ | |
404a8071 RS |
4419 | |
4420 | static void | |
462427c4 | 4421 | mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p) |
404a8071 RS |
4422 | { |
4423 | struct insn_label_list *l; | |
4424 | valueT val; | |
4425 | ||
462427c4 | 4426 | for (l = labels; l != NULL; l = l->next) |
404a8071 | 4427 | { |
9c2799c2 | 4428 | gas_assert (S_GET_SEGMENT (l->label) == now_seg); |
404a8071 RS |
4429 | symbol_set_frag (l->label, frag_now); |
4430 | val = (valueT) frag_now_fix (); | |
df58fc94 | 4431 | /* MIPS16/microMIPS text labels are stored as odd. */ |
462427c4 | 4432 | if (text_p && HAVE_CODE_COMPRESSION) |
404a8071 RS |
4433 | ++val; |
4434 | S_SET_VALUE (l->label, val); | |
4435 | } | |
4436 | } | |
4437 | ||
462427c4 RS |
4438 | /* Move all labels in insn_labels to the current insertion point |
4439 | and treat them as text labels. */ | |
4440 | ||
4441 | static void | |
4442 | mips_move_text_labels (void) | |
4443 | { | |
4444 | mips_move_labels (seg_info (now_seg)->label_list, TRUE); | |
4445 | } | |
4446 | ||
9e009953 MR |
4447 | /* Duplicate the test for LINK_ONCE sections as in `adjust_reloc_syms'. */ |
4448 | ||
5f0fe04b TS |
4449 | static bfd_boolean |
4450 | s_is_linkonce (symbolS *sym, segT from_seg) | |
4451 | { | |
4452 | bfd_boolean linkonce = FALSE; | |
4453 | segT symseg = S_GET_SEGMENT (sym); | |
4454 | ||
4455 | if (symseg != from_seg && !S_IS_LOCAL (sym)) | |
4456 | { | |
4457 | if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE)) | |
4458 | linkonce = TRUE; | |
5f0fe04b TS |
4459 | /* The GNU toolchain uses an extension for ELF: a section |
4460 | beginning with the magic string .gnu.linkonce is a | |
4461 | linkonce section. */ | |
4462 | if (strncmp (segment_name (symseg), ".gnu.linkonce", | |
4463 | sizeof ".gnu.linkonce" - 1) == 0) | |
4464 | linkonce = TRUE; | |
5f0fe04b TS |
4465 | } |
4466 | return linkonce; | |
4467 | } | |
4468 | ||
e1b47bd5 | 4469 | /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the |
df58fc94 RS |
4470 | linker to handle them specially, such as generating jalx instructions |
4471 | when needed. We also make them odd for the duration of the assembly, | |
4472 | in order to generate the right sort of code. We will make them even | |
252b5132 RH |
4473 | in the adjust_symtab routine, while leaving them marked. This is |
4474 | convenient for the debugger and the disassembler. The linker knows | |
4475 | to make them odd again. */ | |
4476 | ||
4477 | static void | |
e1b47bd5 | 4478 | mips_compressed_mark_label (symbolS *label) |
252b5132 | 4479 | { |
df58fc94 | 4480 | gas_assert (HAVE_CODE_COMPRESSION); |
a8dbcb85 | 4481 | |
f3ded42a RS |
4482 | if (mips_opts.mips16) |
4483 | S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label))); | |
4484 | else | |
4485 | S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label))); | |
e1b47bd5 RS |
4486 | if ((S_GET_VALUE (label) & 1) == 0 |
4487 | /* Don't adjust the address if the label is global or weak, or | |
4488 | in a link-once section, since we'll be emitting symbol reloc | |
4489 | references to it which will be patched up by the linker, and | |
4490 | the final value of the symbol may or may not be MIPS16/microMIPS. */ | |
4491 | && !S_IS_WEAK (label) | |
4492 | && !S_IS_EXTERNAL (label) | |
4493 | && !s_is_linkonce (label, now_seg)) | |
4494 | S_SET_VALUE (label, S_GET_VALUE (label) | 1); | |
4495 | } | |
4496 | ||
4497 | /* Mark preceding MIPS16 or microMIPS instruction labels. */ | |
4498 | ||
4499 | static void | |
4500 | mips_compressed_mark_labels (void) | |
4501 | { | |
4502 | struct insn_label_list *l; | |
4503 | ||
4504 | for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next) | |
4505 | mips_compressed_mark_label (l->label); | |
252b5132 RH |
4506 | } |
4507 | ||
4d7206a2 RS |
4508 | /* End the current frag. Make it a variant frag and record the |
4509 | relaxation info. */ | |
4510 | ||
4511 | static void | |
4512 | relax_close_frag (void) | |
4513 | { | |
584892a6 | 4514 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 4515 | frag_var (rs_machine_dependent, 0, 0, |
ce8ad872 MR |
4516 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1], |
4517 | mips_pic != NO_PIC), | |
4d7206a2 RS |
4518 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
4519 | ||
4520 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
4521 | mips_relax.first_fixup = 0; | |
4522 | } | |
4523 | ||
4524 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
4525 | See the comment above RELAX_ENCODE for more details. */ | |
4526 | ||
4527 | static void | |
4528 | relax_start (symbolS *symbol) | |
4529 | { | |
9c2799c2 | 4530 | gas_assert (mips_relax.sequence == 0); |
4d7206a2 RS |
4531 | mips_relax.sequence = 1; |
4532 | mips_relax.symbol = symbol; | |
4533 | } | |
4534 | ||
4535 | /* Start generating the second version of a relaxable sequence. | |
4536 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
4537 | |
4538 | static void | |
4d7206a2 RS |
4539 | relax_switch (void) |
4540 | { | |
9c2799c2 | 4541 | gas_assert (mips_relax.sequence == 1); |
4d7206a2 RS |
4542 | mips_relax.sequence = 2; |
4543 | } | |
4544 | ||
4545 | /* End the current relaxable sequence. */ | |
4546 | ||
4547 | static void | |
4548 | relax_end (void) | |
4549 | { | |
9c2799c2 | 4550 | gas_assert (mips_relax.sequence == 2); |
4d7206a2 RS |
4551 | relax_close_frag (); |
4552 | mips_relax.sequence = 0; | |
4553 | } | |
4554 | ||
11625dd8 RS |
4555 | /* Return true if IP is a delayed branch or jump. */ |
4556 | ||
4557 | static inline bfd_boolean | |
4558 | delayed_branch_p (const struct mips_cl_insn *ip) | |
4559 | { | |
4560 | return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY | |
4561 | | INSN_COND_BRANCH_DELAY | |
4562 | | INSN_COND_BRANCH_LIKELY)) != 0; | |
4563 | } | |
4564 | ||
4565 | /* Return true if IP is a compact branch or jump. */ | |
4566 | ||
4567 | static inline bfd_boolean | |
4568 | compact_branch_p (const struct mips_cl_insn *ip) | |
4569 | { | |
26545944 RS |
4570 | return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH |
4571 | | INSN2_COND_BRANCH)) != 0; | |
11625dd8 RS |
4572 | } |
4573 | ||
4574 | /* Return true if IP is an unconditional branch or jump. */ | |
4575 | ||
4576 | static inline bfd_boolean | |
4577 | uncond_branch_p (const struct mips_cl_insn *ip) | |
4578 | { | |
4579 | return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0 | |
26545944 | 4580 | || (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0); |
11625dd8 RS |
4581 | } |
4582 | ||
4583 | /* Return true if IP is a branch-likely instruction. */ | |
4584 | ||
4585 | static inline bfd_boolean | |
4586 | branch_likely_p (const struct mips_cl_insn *ip) | |
4587 | { | |
4588 | return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0; | |
4589 | } | |
4590 | ||
14fe068b RS |
4591 | /* Return the type of nop that should be used to fill the delay slot |
4592 | of delayed branch IP. */ | |
4593 | ||
4594 | static struct mips_cl_insn * | |
4595 | get_delay_slot_nop (const struct mips_cl_insn *ip) | |
4596 | { | |
4597 | if (mips_opts.micromips | |
4598 | && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
4599 | return µmips_nop32_insn; | |
4600 | return NOP_INSN; | |
4601 | } | |
4602 | ||
fc76e730 RS |
4603 | /* Return a mask that has bit N set if OPCODE reads the register(s) |
4604 | in operand N. */ | |
df58fc94 RS |
4605 | |
4606 | static unsigned int | |
fc76e730 | 4607 | insn_read_mask (const struct mips_opcode *opcode) |
df58fc94 | 4608 | { |
fc76e730 RS |
4609 | return (opcode->pinfo & INSN_READ_ALL) >> INSN_READ_SHIFT; |
4610 | } | |
df58fc94 | 4611 | |
fc76e730 RS |
4612 | /* Return a mask that has bit N set if OPCODE writes to the register(s) |
4613 | in operand N. */ | |
4614 | ||
4615 | static unsigned int | |
4616 | insn_write_mask (const struct mips_opcode *opcode) | |
4617 | { | |
4618 | return (opcode->pinfo & INSN_WRITE_ALL) >> INSN_WRITE_SHIFT; | |
4619 | } | |
4620 | ||
4621 | /* Return a mask of the registers specified by operand OPERAND of INSN. | |
4622 | Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK | |
4623 | is set. */ | |
4624 | ||
4625 | static unsigned int | |
4626 | operand_reg_mask (const struct mips_cl_insn *insn, | |
4627 | const struct mips_operand *operand, | |
4628 | unsigned int type_mask) | |
4629 | { | |
4630 | unsigned int uval, vsel; | |
4631 | ||
4632 | switch (operand->type) | |
df58fc94 | 4633 | { |
fc76e730 RS |
4634 | case OP_INT: |
4635 | case OP_MAPPED_INT: | |
4636 | case OP_MSB: | |
4637 | case OP_PCREL: | |
4638 | case OP_PERF_REG: | |
4639 | case OP_ADDIUSP_INT: | |
4640 | case OP_ENTRY_EXIT_LIST: | |
4641 | case OP_REPEAT_DEST_REG: | |
4642 | case OP_REPEAT_PREV_REG: | |
4643 | case OP_PC: | |
14daeee3 RS |
4644 | case OP_VU0_SUFFIX: |
4645 | case OP_VU0_MATCH_SUFFIX: | |
56d438b1 | 4646 | case OP_IMM_INDEX: |
fc76e730 RS |
4647 | abort (); |
4648 | ||
25499ac7 MR |
4649 | case OP_REG28: |
4650 | return 1 << 28; | |
4651 | ||
fc76e730 | 4652 | case OP_REG: |
0f35dbc4 | 4653 | case OP_OPTIONAL_REG: |
fc76e730 RS |
4654 | { |
4655 | const struct mips_reg_operand *reg_op; | |
4656 | ||
4657 | reg_op = (const struct mips_reg_operand *) operand; | |
4658 | if (!(type_mask & (1 << reg_op->reg_type))) | |
4659 | return 0; | |
4660 | uval = insn_extract_operand (insn, operand); | |
4661 | return 1 << mips_decode_reg_operand (reg_op, uval); | |
4662 | } | |
4663 | ||
4664 | case OP_REG_PAIR: | |
4665 | { | |
4666 | const struct mips_reg_pair_operand *pair_op; | |
4667 | ||
4668 | pair_op = (const struct mips_reg_pair_operand *) operand; | |
4669 | if (!(type_mask & (1 << pair_op->reg_type))) | |
4670 | return 0; | |
4671 | uval = insn_extract_operand (insn, operand); | |
4672 | return (1 << pair_op->reg1_map[uval]) | (1 << pair_op->reg2_map[uval]); | |
4673 | } | |
4674 | ||
4675 | case OP_CLO_CLZ_DEST: | |
4676 | if (!(type_mask & (1 << OP_REG_GP))) | |
4677 | return 0; | |
4678 | uval = insn_extract_operand (insn, operand); | |
4679 | return (1 << (uval & 31)) | (1 << (uval >> 5)); | |
4680 | ||
7361da2c AB |
4681 | case OP_SAME_RS_RT: |
4682 | if (!(type_mask & (1 << OP_REG_GP))) | |
4683 | return 0; | |
4684 | uval = insn_extract_operand (insn, operand); | |
4685 | gas_assert ((uval & 31) == (uval >> 5)); | |
4686 | return 1 << (uval & 31); | |
4687 | ||
4688 | case OP_CHECK_PREV: | |
4689 | case OP_NON_ZERO_REG: | |
4690 | if (!(type_mask & (1 << OP_REG_GP))) | |
4691 | return 0; | |
4692 | uval = insn_extract_operand (insn, operand); | |
4693 | return 1 << (uval & 31); | |
4694 | ||
fc76e730 RS |
4695 | case OP_LWM_SWM_LIST: |
4696 | abort (); | |
4697 | ||
4698 | case OP_SAVE_RESTORE_LIST: | |
4699 | abort (); | |
4700 | ||
4701 | case OP_MDMX_IMM_REG: | |
4702 | if (!(type_mask & (1 << OP_REG_VEC))) | |
4703 | return 0; | |
4704 | uval = insn_extract_operand (insn, operand); | |
4705 | vsel = uval >> 5; | |
4706 | if ((vsel & 0x18) == 0x18) | |
4707 | return 0; | |
4708 | return 1 << (uval & 31); | |
56d438b1 CF |
4709 | |
4710 | case OP_REG_INDEX: | |
4711 | if (!(type_mask & (1 << OP_REG_GP))) | |
4712 | return 0; | |
4713 | return 1 << insn_extract_operand (insn, operand); | |
df58fc94 | 4714 | } |
fc76e730 RS |
4715 | abort (); |
4716 | } | |
4717 | ||
4718 | /* Return a mask of the registers specified by operands OPNO_MASK of INSN, | |
4719 | where bit N of OPNO_MASK is set if operand N should be included. | |
4720 | Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK | |
4721 | is set. */ | |
4722 | ||
4723 | static unsigned int | |
4724 | insn_reg_mask (const struct mips_cl_insn *insn, | |
4725 | unsigned int type_mask, unsigned int opno_mask) | |
4726 | { | |
4727 | unsigned int opno, reg_mask; | |
4728 | ||
4729 | opno = 0; | |
4730 | reg_mask = 0; | |
4731 | while (opno_mask != 0) | |
4732 | { | |
4733 | if (opno_mask & 1) | |
4734 | reg_mask |= operand_reg_mask (insn, insn_opno (insn, opno), type_mask); | |
4735 | opno_mask >>= 1; | |
4736 | opno += 1; | |
4737 | } | |
4738 | return reg_mask; | |
df58fc94 RS |
4739 | } |
4740 | ||
4c260379 RS |
4741 | /* Return the mask of core registers that IP reads. */ |
4742 | ||
4743 | static unsigned int | |
4744 | gpr_read_mask (const struct mips_cl_insn *ip) | |
4745 | { | |
4746 | unsigned long pinfo, pinfo2; | |
4747 | unsigned int mask; | |
4748 | ||
fc76e730 | 4749 | mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_read_mask (ip->insn_mo)); |
4c260379 RS |
4750 | pinfo = ip->insn_mo->pinfo; |
4751 | pinfo2 = ip->insn_mo->pinfo2; | |
fc76e730 | 4752 | if (pinfo & INSN_UDI) |
4c260379 | 4753 | { |
fc76e730 RS |
4754 | /* UDI instructions have traditionally been assumed to read RS |
4755 | and RT. */ | |
4756 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); | |
4757 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); | |
4c260379 | 4758 | } |
fc76e730 RS |
4759 | if (pinfo & INSN_READ_GPR_24) |
4760 | mask |= 1 << 24; | |
4761 | if (pinfo2 & INSN2_READ_GPR_16) | |
4762 | mask |= 1 << 16; | |
4763 | if (pinfo2 & INSN2_READ_SP) | |
4764 | mask |= 1 << SP; | |
26545944 | 4765 | if (pinfo2 & INSN2_READ_GPR_31) |
fc76e730 | 4766 | mask |= 1 << 31; |
fe35f09f RS |
4767 | /* Don't include register 0. */ |
4768 | return mask & ~1; | |
4c260379 RS |
4769 | } |
4770 | ||
4771 | /* Return the mask of core registers that IP writes. */ | |
4772 | ||
4773 | static unsigned int | |
4774 | gpr_write_mask (const struct mips_cl_insn *ip) | |
4775 | { | |
4776 | unsigned long pinfo, pinfo2; | |
4777 | unsigned int mask; | |
4778 | ||
fc76e730 | 4779 | mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_write_mask (ip->insn_mo)); |
4c260379 RS |
4780 | pinfo = ip->insn_mo->pinfo; |
4781 | pinfo2 = ip->insn_mo->pinfo2; | |
fc76e730 RS |
4782 | if (pinfo & INSN_WRITE_GPR_24) |
4783 | mask |= 1 << 24; | |
4784 | if (pinfo & INSN_WRITE_GPR_31) | |
4785 | mask |= 1 << 31; | |
4786 | if (pinfo & INSN_UDI) | |
4787 | /* UDI instructions have traditionally been assumed to write to RD. */ | |
4788 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); | |
4789 | if (pinfo2 & INSN2_WRITE_SP) | |
4790 | mask |= 1 << SP; | |
fe35f09f RS |
4791 | /* Don't include register 0. */ |
4792 | return mask & ~1; | |
4c260379 RS |
4793 | } |
4794 | ||
4795 | /* Return the mask of floating-point registers that IP reads. */ | |
4796 | ||
4797 | static unsigned int | |
4798 | fpr_read_mask (const struct mips_cl_insn *ip) | |
4799 | { | |
fc76e730 | 4800 | unsigned long pinfo; |
4c260379 RS |
4801 | unsigned int mask; |
4802 | ||
9d5de888 CF |
4803 | mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC) |
4804 | | (1 << OP_REG_MSA)), | |
fc76e730 | 4805 | insn_read_mask (ip->insn_mo)); |
4c260379 | 4806 | pinfo = ip->insn_mo->pinfo; |
4c260379 RS |
4807 | /* Conservatively treat all operands to an FP_D instruction are doubles. |
4808 | (This is overly pessimistic for things like cvt.d.s.) */ | |
bad1aba3 | 4809 | if (FPR_SIZE != 64 && (pinfo & FP_D)) |
4c260379 RS |
4810 | mask |= mask << 1; |
4811 | return mask; | |
4812 | } | |
4813 | ||
4814 | /* Return the mask of floating-point registers that IP writes. */ | |
4815 | ||
4816 | static unsigned int | |
4817 | fpr_write_mask (const struct mips_cl_insn *ip) | |
4818 | { | |
fc76e730 | 4819 | unsigned long pinfo; |
4c260379 RS |
4820 | unsigned int mask; |
4821 | ||
9d5de888 CF |
4822 | mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC) |
4823 | | (1 << OP_REG_MSA)), | |
fc76e730 | 4824 | insn_write_mask (ip->insn_mo)); |
4c260379 | 4825 | pinfo = ip->insn_mo->pinfo; |
4c260379 RS |
4826 | /* Conservatively treat all operands to an FP_D instruction are doubles. |
4827 | (This is overly pessimistic for things like cvt.s.d.) */ | |
bad1aba3 | 4828 | if (FPR_SIZE != 64 && (pinfo & FP_D)) |
4c260379 RS |
4829 | mask |= mask << 1; |
4830 | return mask; | |
4831 | } | |
4832 | ||
a1d78564 RS |
4833 | /* Operand OPNUM of INSN is an odd-numbered floating-point register. |
4834 | Check whether that is allowed. */ | |
4835 | ||
4836 | static bfd_boolean | |
4837 | mips_oddfpreg_ok (const struct mips_opcode *insn, int opnum) | |
4838 | { | |
4839 | const char *s = insn->name; | |
351cdf24 MF |
4840 | bfd_boolean oddspreg = (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa, mips_opts.arch) |
4841 | || FPR_SIZE == 64) | |
4842 | && mips_opts.oddspreg; | |
a1d78564 RS |
4843 | |
4844 | if (insn->pinfo == INSN_MACRO) | |
4845 | /* Let a macro pass, we'll catch it later when it is expanded. */ | |
4846 | return TRUE; | |
4847 | ||
351cdf24 MF |
4848 | /* Single-precision coprocessor loads and moves are OK for 32-bit registers, |
4849 | otherwise it depends on oddspreg. */ | |
4850 | if ((insn->pinfo & FP_S) | |
4851 | && (insn->pinfo & (INSN_LOAD_MEMORY | INSN_STORE_MEMORY | |
43885403 | 4852 | | INSN_LOAD_COPROC | INSN_COPROC_MOVE))) |
351cdf24 | 4853 | return FPR_SIZE == 32 || oddspreg; |
a1d78564 | 4854 | |
351cdf24 MF |
4855 | /* Allow odd registers for single-precision ops and double-precision if the |
4856 | floating-point registers are 64-bit wide. */ | |
4857 | switch (insn->pinfo & (FP_S | FP_D)) | |
4858 | { | |
4859 | case FP_S: | |
4860 | case 0: | |
4861 | return oddspreg; | |
4862 | case FP_D: | |
4863 | return FPR_SIZE == 64; | |
4864 | default: | |
4865 | break; | |
a1d78564 RS |
4866 | } |
4867 | ||
351cdf24 MF |
4868 | /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ |
4869 | s = strchr (insn->name, '.'); | |
4870 | if (s != NULL && opnum == 2) | |
4871 | s = strchr (s + 1, '.'); | |
4872 | if (s != NULL && (s[1] == 'w' || s[1] == 's')) | |
4873 | return oddspreg; | |
a1d78564 | 4874 | |
351cdf24 | 4875 | return FPR_SIZE == 64; |
a1d78564 RS |
4876 | } |
4877 | ||
a1d78564 RS |
4878 | /* Information about an instruction argument that we're trying to match. */ |
4879 | struct mips_arg_info | |
4880 | { | |
4881 | /* The instruction so far. */ | |
4882 | struct mips_cl_insn *insn; | |
4883 | ||
a92713e6 RS |
4884 | /* The first unconsumed operand token. */ |
4885 | struct mips_operand_token *token; | |
4886 | ||
a1d78564 RS |
4887 | /* The 1-based operand number, in terms of insn->insn_mo->args. */ |
4888 | int opnum; | |
4889 | ||
4890 | /* The 1-based argument number, for error reporting. This does not | |
4891 | count elided optional registers, etc.. */ | |
4892 | int argnum; | |
4893 | ||
4894 | /* The last OP_REG operand seen, or ILLEGAL_REG if none. */ | |
4895 | unsigned int last_regno; | |
4896 | ||
4897 | /* If the first operand was an OP_REG, this is the register that it | |
4898 | specified, otherwise it is ILLEGAL_REG. */ | |
4899 | unsigned int dest_regno; | |
4900 | ||
4901 | /* The value of the last OP_INT operand. Only used for OP_MSB, | |
4902 | where it gives the lsb position. */ | |
4903 | unsigned int last_op_int; | |
4904 | ||
60f20e8b | 4905 | /* If true, match routines should assume that no later instruction |
2b0f3761 | 4906 | alternative matches and should therefore be as accommodating as |
60f20e8b RS |
4907 | possible. Match routines should not report errors if something |
4908 | is only invalid for !LAX_MATCH. */ | |
4909 | bfd_boolean lax_match; | |
a1d78564 | 4910 | |
a1d78564 RS |
4911 | /* True if a reference to the current AT register was seen. */ |
4912 | bfd_boolean seen_at; | |
4913 | }; | |
4914 | ||
1a00e612 RS |
4915 | /* Record that the argument is out of range. */ |
4916 | ||
4917 | static void | |
4918 | match_out_of_range (struct mips_arg_info *arg) | |
4919 | { | |
4920 | set_insn_error_i (arg->argnum, _("operand %d out of range"), arg->argnum); | |
4921 | } | |
4922 | ||
4923 | /* Record that the argument isn't constant but needs to be. */ | |
4924 | ||
4925 | static void | |
4926 | match_not_constant (struct mips_arg_info *arg) | |
4927 | { | |
4928 | set_insn_error_i (arg->argnum, _("operand %d must be constant"), | |
4929 | arg->argnum); | |
4930 | } | |
4931 | ||
a92713e6 RS |
4932 | /* Try to match an OT_CHAR token for character CH. Consume the token |
4933 | and return true on success, otherwise return false. */ | |
a1d78564 | 4934 | |
a92713e6 RS |
4935 | static bfd_boolean |
4936 | match_char (struct mips_arg_info *arg, char ch) | |
a1d78564 | 4937 | { |
a92713e6 RS |
4938 | if (arg->token->type == OT_CHAR && arg->token->u.ch == ch) |
4939 | { | |
4940 | ++arg->token; | |
4941 | if (ch == ',') | |
4942 | arg->argnum += 1; | |
4943 | return TRUE; | |
4944 | } | |
4945 | return FALSE; | |
4946 | } | |
a1d78564 | 4947 | |
a92713e6 RS |
4948 | /* Try to get an expression from the next tokens in ARG. Consume the |
4949 | tokens and return true on success, storing the expression value in | |
4950 | VALUE and relocation types in R. */ | |
4951 | ||
4952 | static bfd_boolean | |
4953 | match_expression (struct mips_arg_info *arg, expressionS *value, | |
4954 | bfd_reloc_code_real_type *r) | |
4955 | { | |
d436c1c2 RS |
4956 | /* If the next token is a '(' that was parsed as being part of a base |
4957 | expression, assume we have an elided offset. The later match will fail | |
4958 | if this turns out to be wrong. */ | |
4959 | if (arg->token->type == OT_CHAR && arg->token->u.ch == '(') | |
a1d78564 | 4960 | { |
d436c1c2 RS |
4961 | value->X_op = O_constant; |
4962 | value->X_add_number = 0; | |
4963 | r[0] = r[1] = r[2] = BFD_RELOC_UNUSED; | |
a92713e6 RS |
4964 | return TRUE; |
4965 | } | |
4966 | ||
d436c1c2 RS |
4967 | /* Reject register-based expressions such as "0+$2" and "(($2))". |
4968 | For plain registers the default error seems more appropriate. */ | |
4969 | if (arg->token->type == OT_INTEGER | |
4970 | && arg->token->u.integer.value.X_op == O_register) | |
a92713e6 | 4971 | { |
d436c1c2 RS |
4972 | set_insn_error (arg->argnum, _("register value used as expression")); |
4973 | return FALSE; | |
a1d78564 | 4974 | } |
d436c1c2 RS |
4975 | |
4976 | if (arg->token->type == OT_INTEGER) | |
a92713e6 | 4977 | { |
d436c1c2 RS |
4978 | *value = arg->token->u.integer.value; |
4979 | memcpy (r, arg->token->u.integer.relocs, 3 * sizeof (*r)); | |
4980 | ++arg->token; | |
4981 | return TRUE; | |
a92713e6 | 4982 | } |
a92713e6 | 4983 | |
d436c1c2 RS |
4984 | set_insn_error_i |
4985 | (arg->argnum, _("operand %d must be an immediate expression"), | |
4986 | arg->argnum); | |
4987 | return FALSE; | |
a92713e6 RS |
4988 | } |
4989 | ||
4990 | /* Try to get a constant expression from the next tokens in ARG. Consume | |
de194d85 | 4991 | the tokens and return true on success, storing the constant value |
a54d5f8b | 4992 | in *VALUE. */ |
a92713e6 RS |
4993 | |
4994 | static bfd_boolean | |
1a00e612 | 4995 | match_const_int (struct mips_arg_info *arg, offsetT *value) |
a92713e6 RS |
4996 | { |
4997 | expressionS ex; | |
4998 | bfd_reloc_code_real_type r[3]; | |
a1d78564 | 4999 | |
a92713e6 RS |
5000 | if (!match_expression (arg, &ex, r)) |
5001 | return FALSE; | |
5002 | ||
5003 | if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_constant) | |
a1d78564 RS |
5004 | *value = ex.X_add_number; |
5005 | else | |
5006 | { | |
c96425c5 MR |
5007 | if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_big) |
5008 | match_out_of_range (arg); | |
5009 | else | |
5010 | match_not_constant (arg); | |
1a00e612 | 5011 | return FALSE; |
a1d78564 | 5012 | } |
a92713e6 | 5013 | return TRUE; |
a1d78564 RS |
5014 | } |
5015 | ||
5016 | /* Return the RTYPE_* flags for a register operand of type TYPE that | |
5017 | appears in instruction OPCODE. */ | |
5018 | ||
5019 | static unsigned int | |
5020 | convert_reg_type (const struct mips_opcode *opcode, | |
5021 | enum mips_reg_operand_type type) | |
5022 | { | |
5023 | switch (type) | |
5024 | { | |
5025 | case OP_REG_GP: | |
5026 | return RTYPE_NUM | RTYPE_GP; | |
5027 | ||
5028 | case OP_REG_FP: | |
5029 | /* Allow vector register names for MDMX if the instruction is a 64-bit | |
5030 | FPR load, store or move (including moves to and from GPRs). */ | |
5031 | if ((mips_opts.ase & ASE_MDMX) | |
5032 | && (opcode->pinfo & FP_D) | |
43885403 | 5033 | && (opcode->pinfo & (INSN_COPROC_MOVE |
a1d78564 | 5034 | | INSN_COPROC_MEMORY_DELAY |
43885403 | 5035 | | INSN_LOAD_COPROC |
67dc82bc | 5036 | | INSN_LOAD_MEMORY |
a1d78564 RS |
5037 | | INSN_STORE_MEMORY))) |
5038 | return RTYPE_FPU | RTYPE_VEC; | |
5039 | return RTYPE_FPU; | |
5040 | ||
5041 | case OP_REG_CCC: | |
5042 | if (opcode->pinfo & (FP_D | FP_S)) | |
5043 | return RTYPE_CCC | RTYPE_FCC; | |
5044 | return RTYPE_CCC; | |
5045 | ||
5046 | case OP_REG_VEC: | |
5047 | if (opcode->membership & INSN_5400) | |
5048 | return RTYPE_FPU; | |
5049 | return RTYPE_FPU | RTYPE_VEC; | |
5050 | ||
5051 | case OP_REG_ACC: | |
5052 | return RTYPE_ACC; | |
5053 | ||
5054 | case OP_REG_COPRO: | |
5055 | if (opcode->name[strlen (opcode->name) - 1] == '0') | |
5056 | return RTYPE_NUM | RTYPE_CP0; | |
5057 | return RTYPE_NUM; | |
5058 | ||
5059 | case OP_REG_HW: | |
5060 | return RTYPE_NUM; | |
14daeee3 RS |
5061 | |
5062 | case OP_REG_VI: | |
5063 | return RTYPE_NUM | RTYPE_VI; | |
5064 | ||
5065 | case OP_REG_VF: | |
5066 | return RTYPE_NUM | RTYPE_VF; | |
5067 | ||
5068 | case OP_REG_R5900_I: | |
5069 | return RTYPE_R5900_I; | |
5070 | ||
5071 | case OP_REG_R5900_Q: | |
5072 | return RTYPE_R5900_Q; | |
5073 | ||
5074 | case OP_REG_R5900_R: | |
5075 | return RTYPE_R5900_R; | |
5076 | ||
5077 | case OP_REG_R5900_ACC: | |
5078 | return RTYPE_R5900_ACC; | |
56d438b1 CF |
5079 | |
5080 | case OP_REG_MSA: | |
5081 | return RTYPE_MSA; | |
5082 | ||
5083 | case OP_REG_MSA_CTRL: | |
5084 | return RTYPE_NUM; | |
a1d78564 RS |
5085 | } |
5086 | abort (); | |
5087 | } | |
5088 | ||
5089 | /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */ | |
5090 | ||
5091 | static void | |
5092 | check_regno (struct mips_arg_info *arg, | |
5093 | enum mips_reg_operand_type type, unsigned int regno) | |
5094 | { | |
5095 | if (AT && type == OP_REG_GP && regno == AT) | |
5096 | arg->seen_at = TRUE; | |
5097 | ||
5098 | if (type == OP_REG_FP | |
5099 | && (regno & 1) != 0 | |
a1d78564 | 5100 | && !mips_oddfpreg_ok (arg->insn->insn_mo, arg->opnum)) |
351cdf24 MF |
5101 | { |
5102 | /* This was a warning prior to introducing O32 FPXX and FP64 support | |
5103 | so maintain a warning for FP32 but raise an error for the new | |
5104 | cases. */ | |
5105 | if (FPR_SIZE == 32) | |
5106 | as_warn (_("float register should be even, was %d"), regno); | |
5107 | else | |
5108 | as_bad (_("float register should be even, was %d"), regno); | |
5109 | } | |
a1d78564 RS |
5110 | |
5111 | if (type == OP_REG_CCC) | |
5112 | { | |
5113 | const char *name; | |
5114 | size_t length; | |
5115 | ||
5116 | name = arg->insn->insn_mo->name; | |
5117 | length = strlen (name); | |
5118 | if ((regno & 1) != 0 | |
5119 | && ((length >= 3 && strcmp (name + length - 3, ".ps") == 0) | |
5120 | || (length >= 5 && strncmp (name + length - 5, "any2", 4) == 0))) | |
1661c76c | 5121 | as_warn (_("condition code register should be even for %s, was %d"), |
a1d78564 RS |
5122 | name, regno); |
5123 | ||
5124 | if ((regno & 3) != 0 | |
5125 | && (length >= 5 && strncmp (name + length - 5, "any4", 4) == 0)) | |
1661c76c | 5126 | as_warn (_("condition code register should be 0 or 4 for %s, was %d"), |
a1d78564 RS |
5127 | name, regno); |
5128 | } | |
5129 | } | |
5130 | ||
a92713e6 RS |
5131 | /* ARG is a register with symbol value SYMVAL. Try to interpret it as |
5132 | a register of type TYPE. Return true on success, storing the register | |
5133 | number in *REGNO and warning about any dubious uses. */ | |
5134 | ||
5135 | static bfd_boolean | |
5136 | match_regno (struct mips_arg_info *arg, enum mips_reg_operand_type type, | |
5137 | unsigned int symval, unsigned int *regno) | |
5138 | { | |
5139 | if (type == OP_REG_VEC) | |
5140 | symval = mips_prefer_vec_regno (symval); | |
5141 | if (!(symval & convert_reg_type (arg->insn->insn_mo, type))) | |
5142 | return FALSE; | |
5143 | ||
5144 | *regno = symval & RNUM_MASK; | |
5145 | check_regno (arg, type, *regno); | |
5146 | return TRUE; | |
5147 | } | |
5148 | ||
5149 | /* Try to interpret the next token in ARG as a register of type TYPE. | |
5150 | Consume the token and return true on success, storing the register | |
5151 | number in *REGNO. Return false on failure. */ | |
5152 | ||
5153 | static bfd_boolean | |
5154 | match_reg (struct mips_arg_info *arg, enum mips_reg_operand_type type, | |
5155 | unsigned int *regno) | |
5156 | { | |
5157 | if (arg->token->type == OT_REG | |
5158 | && match_regno (arg, type, arg->token->u.regno, regno)) | |
5159 | { | |
5160 | ++arg->token; | |
5161 | return TRUE; | |
5162 | } | |
5163 | return FALSE; | |
5164 | } | |
5165 | ||
5166 | /* Try to interpret the next token in ARG as a range of registers of type TYPE. | |
5167 | Consume the token and return true on success, storing the register numbers | |
5168 | in *REGNO1 and *REGNO2. Return false on failure. */ | |
5169 | ||
5170 | static bfd_boolean | |
5171 | match_reg_range (struct mips_arg_info *arg, enum mips_reg_operand_type type, | |
5172 | unsigned int *regno1, unsigned int *regno2) | |
5173 | { | |
5174 | if (match_reg (arg, type, regno1)) | |
5175 | { | |
5176 | *regno2 = *regno1; | |
5177 | return TRUE; | |
5178 | } | |
5179 | if (arg->token->type == OT_REG_RANGE | |
5180 | && match_regno (arg, type, arg->token->u.reg_range.regno1, regno1) | |
5181 | && match_regno (arg, type, arg->token->u.reg_range.regno2, regno2) | |
5182 | && *regno1 <= *regno2) | |
5183 | { | |
5184 | ++arg->token; | |
5185 | return TRUE; | |
5186 | } | |
5187 | return FALSE; | |
5188 | } | |
5189 | ||
a1d78564 RS |
5190 | /* OP_INT matcher. */ |
5191 | ||
a92713e6 | 5192 | static bfd_boolean |
a1d78564 | 5193 | match_int_operand (struct mips_arg_info *arg, |
a92713e6 | 5194 | const struct mips_operand *operand_base) |
a1d78564 RS |
5195 | { |
5196 | const struct mips_int_operand *operand; | |
3ccad066 | 5197 | unsigned int uval; |
a1d78564 RS |
5198 | int min_val, max_val, factor; |
5199 | offsetT sval; | |
a1d78564 RS |
5200 | |
5201 | operand = (const struct mips_int_operand *) operand_base; | |
5202 | factor = 1 << operand->shift; | |
3ccad066 RS |
5203 | min_val = mips_int_operand_min (operand); |
5204 | max_val = mips_int_operand_max (operand); | |
a1d78564 | 5205 | |
d436c1c2 RS |
5206 | if (operand_base->lsb == 0 |
5207 | && operand_base->size == 16 | |
5208 | && operand->shift == 0 | |
5209 | && operand->bias == 0 | |
5210 | && (operand->max_val == 32767 || operand->max_val == 65535)) | |
a1d78564 RS |
5211 | { |
5212 | /* The operand can be relocated. */ | |
a92713e6 RS |
5213 | if (!match_expression (arg, &offset_expr, offset_reloc)) |
5214 | return FALSE; | |
5215 | ||
c96425c5 MR |
5216 | if (offset_expr.X_op == O_big) |
5217 | { | |
5218 | match_out_of_range (arg); | |
5219 | return FALSE; | |
5220 | } | |
5221 | ||
a92713e6 | 5222 | if (offset_reloc[0] != BFD_RELOC_UNUSED) |
33eaf5de | 5223 | /* Relocation operators were used. Accept the argument and |
a1d78564 RS |
5224 | leave the relocation value in offset_expr and offset_relocs |
5225 | for the caller to process. */ | |
a92713e6 RS |
5226 | return TRUE; |
5227 | ||
5228 | if (offset_expr.X_op != O_constant) | |
a1d78564 | 5229 | { |
60f20e8b RS |
5230 | /* Accept non-constant operands if no later alternative matches, |
5231 | leaving it for the caller to process. */ | |
5232 | if (!arg->lax_match) | |
602b88e3 MR |
5233 | { |
5234 | match_not_constant (arg); | |
5235 | return FALSE; | |
5236 | } | |
a92713e6 RS |
5237 | offset_reloc[0] = BFD_RELOC_LO16; |
5238 | return TRUE; | |
a1d78564 | 5239 | } |
a92713e6 | 5240 | |
a1d78564 RS |
5241 | /* Clear the global state; we're going to install the operand |
5242 | ourselves. */ | |
a92713e6 | 5243 | sval = offset_expr.X_add_number; |
a1d78564 | 5244 | offset_expr.X_op = O_absent; |
60f20e8b RS |
5245 | |
5246 | /* For compatibility with older assemblers, we accept | |
5247 | 0x8000-0xffff as signed 16-bit numbers when only | |
5248 | signed numbers are allowed. */ | |
5249 | if (sval > max_val) | |
5250 | { | |
5251 | max_val = ((1 << operand_base->size) - 1) << operand->shift; | |
5252 | if (!arg->lax_match && sval <= max_val) | |
20c59b84 MR |
5253 | { |
5254 | match_out_of_range (arg); | |
5255 | return FALSE; | |
5256 | } | |
60f20e8b | 5257 | } |
a1d78564 RS |
5258 | } |
5259 | else | |
5260 | { | |
1a00e612 | 5261 | if (!match_const_int (arg, &sval)) |
a92713e6 | 5262 | return FALSE; |
a1d78564 RS |
5263 | } |
5264 | ||
5265 | arg->last_op_int = sval; | |
5266 | ||
1a00e612 | 5267 | if (sval < min_val || sval > max_val || sval % factor) |
a1d78564 | 5268 | { |
1a00e612 RS |
5269 | match_out_of_range (arg); |
5270 | return FALSE; | |
a1d78564 RS |
5271 | } |
5272 | ||
5273 | uval = (unsigned int) sval >> operand->shift; | |
5274 | uval -= operand->bias; | |
5275 | ||
5276 | /* Handle -mfix-cn63xxp1. */ | |
5277 | if (arg->opnum == 1 | |
5278 | && mips_fix_cn63xxp1 | |
5279 | && !mips_opts.micromips | |
5280 | && strcmp ("pref", arg->insn->insn_mo->name) == 0) | |
5281 | switch (uval) | |
5282 | { | |
5283 | case 5: | |
5284 | case 25: | |
5285 | case 26: | |
5286 | case 27: | |
5287 | case 28: | |
5288 | case 29: | |
5289 | case 30: | |
5290 | case 31: | |
5291 | /* These are ok. */ | |
5292 | break; | |
5293 | ||
5294 | default: | |
5295 | /* The rest must be changed to 28. */ | |
5296 | uval = 28; | |
5297 | break; | |
5298 | } | |
5299 | ||
5300 | insn_insert_operand (arg->insn, operand_base, uval); | |
a92713e6 | 5301 | return TRUE; |
a1d78564 RS |
5302 | } |
5303 | ||
5304 | /* OP_MAPPED_INT matcher. */ | |
5305 | ||
a92713e6 | 5306 | static bfd_boolean |
a1d78564 | 5307 | match_mapped_int_operand (struct mips_arg_info *arg, |
a92713e6 | 5308 | const struct mips_operand *operand_base) |
a1d78564 RS |
5309 | { |
5310 | const struct mips_mapped_int_operand *operand; | |
5311 | unsigned int uval, num_vals; | |
5312 | offsetT sval; | |
5313 | ||
5314 | operand = (const struct mips_mapped_int_operand *) operand_base; | |
1a00e612 | 5315 | if (!match_const_int (arg, &sval)) |
a92713e6 | 5316 | return FALSE; |
a1d78564 RS |
5317 | |
5318 | num_vals = 1 << operand_base->size; | |
5319 | for (uval = 0; uval < num_vals; uval++) | |
5320 | if (operand->int_map[uval] == sval) | |
5321 | break; | |
5322 | if (uval == num_vals) | |
1a00e612 RS |
5323 | { |
5324 | match_out_of_range (arg); | |
5325 | return FALSE; | |
5326 | } | |
a1d78564 RS |
5327 | |
5328 | insn_insert_operand (arg->insn, operand_base, uval); | |
a92713e6 | 5329 | return TRUE; |
a1d78564 RS |
5330 | } |
5331 | ||
5332 | /* OP_MSB matcher. */ | |
5333 | ||
a92713e6 | 5334 | static bfd_boolean |
a1d78564 | 5335 | match_msb_operand (struct mips_arg_info *arg, |
a92713e6 | 5336 | const struct mips_operand *operand_base) |
a1d78564 RS |
5337 | { |
5338 | const struct mips_msb_operand *operand; | |
5339 | int min_val, max_val, max_high; | |
5340 | offsetT size, sval, high; | |
5341 | ||
5342 | operand = (const struct mips_msb_operand *) operand_base; | |
5343 | min_val = operand->bias; | |
5344 | max_val = min_val + (1 << operand_base->size) - 1; | |
5345 | max_high = operand->opsize; | |
5346 | ||
1a00e612 | 5347 | if (!match_const_int (arg, &size)) |
a92713e6 | 5348 | return FALSE; |
a1d78564 RS |
5349 | |
5350 | high = size + arg->last_op_int; | |
5351 | sval = operand->add_lsb ? high : size; | |
5352 | ||
5353 | if (size < 0 || high > max_high || sval < min_val || sval > max_val) | |
5354 | { | |
1a00e612 RS |
5355 | match_out_of_range (arg); |
5356 | return FALSE; | |
a1d78564 RS |
5357 | } |
5358 | insn_insert_operand (arg->insn, operand_base, sval - min_val); | |
a92713e6 | 5359 | return TRUE; |
a1d78564 RS |
5360 | } |
5361 | ||
5362 | /* OP_REG matcher. */ | |
5363 | ||
a92713e6 | 5364 | static bfd_boolean |
a1d78564 | 5365 | match_reg_operand (struct mips_arg_info *arg, |
a92713e6 | 5366 | const struct mips_operand *operand_base) |
a1d78564 RS |
5367 | { |
5368 | const struct mips_reg_operand *operand; | |
a92713e6 | 5369 | unsigned int regno, uval, num_vals; |
a1d78564 RS |
5370 | |
5371 | operand = (const struct mips_reg_operand *) operand_base; | |
a92713e6 RS |
5372 | if (!match_reg (arg, operand->reg_type, ®no)) |
5373 | return FALSE; | |
a1d78564 RS |
5374 | |
5375 | if (operand->reg_map) | |
5376 | { | |
5377 | num_vals = 1 << operand->root.size; | |
5378 | for (uval = 0; uval < num_vals; uval++) | |
5379 | if (operand->reg_map[uval] == regno) | |
5380 | break; | |
5381 | if (num_vals == uval) | |
a92713e6 | 5382 | return FALSE; |
a1d78564 RS |
5383 | } |
5384 | else | |
5385 | uval = regno; | |
5386 | ||
a1d78564 RS |
5387 | arg->last_regno = regno; |
5388 | if (arg->opnum == 1) | |
5389 | arg->dest_regno = regno; | |
5390 | insn_insert_operand (arg->insn, operand_base, uval); | |
a92713e6 | 5391 | return TRUE; |
a1d78564 RS |
5392 | } |
5393 | ||
5394 | /* OP_REG_PAIR matcher. */ | |
5395 | ||
a92713e6 | 5396 | static bfd_boolean |
a1d78564 | 5397 | match_reg_pair_operand (struct mips_arg_info *arg, |
a92713e6 | 5398 | const struct mips_operand *operand_base) |
a1d78564 RS |
5399 | { |
5400 | const struct mips_reg_pair_operand *operand; | |
a92713e6 | 5401 | unsigned int regno1, regno2, uval, num_vals; |
a1d78564 RS |
5402 | |
5403 | operand = (const struct mips_reg_pair_operand *) operand_base; | |
a92713e6 RS |
5404 | if (!match_reg (arg, operand->reg_type, ®no1) |
5405 | || !match_char (arg, ',') | |
5406 | || !match_reg (arg, operand->reg_type, ®no2)) | |
5407 | return FALSE; | |
a1d78564 RS |
5408 | |
5409 | num_vals = 1 << operand_base->size; | |
5410 | for (uval = 0; uval < num_vals; uval++) | |
5411 | if (operand->reg1_map[uval] == regno1 && operand->reg2_map[uval] == regno2) | |
5412 | break; | |
5413 | if (uval == num_vals) | |
a92713e6 | 5414 | return FALSE; |
a1d78564 | 5415 | |
a1d78564 | 5416 | insn_insert_operand (arg->insn, operand_base, uval); |
a92713e6 | 5417 | return TRUE; |
a1d78564 RS |
5418 | } |
5419 | ||
5420 | /* OP_PCREL matcher. The caller chooses the relocation type. */ | |
5421 | ||
a92713e6 RS |
5422 | static bfd_boolean |
5423 | match_pcrel_operand (struct mips_arg_info *arg) | |
a1d78564 | 5424 | { |
a92713e6 RS |
5425 | bfd_reloc_code_real_type r[3]; |
5426 | ||
5427 | return match_expression (arg, &offset_expr, r) && r[0] == BFD_RELOC_UNUSED; | |
a1d78564 RS |
5428 | } |
5429 | ||
5430 | /* OP_PERF_REG matcher. */ | |
5431 | ||
a92713e6 | 5432 | static bfd_boolean |
a1d78564 | 5433 | match_perf_reg_operand (struct mips_arg_info *arg, |
a92713e6 | 5434 | const struct mips_operand *operand) |
a1d78564 RS |
5435 | { |
5436 | offsetT sval; | |
5437 | ||
1a00e612 | 5438 | if (!match_const_int (arg, &sval)) |
a92713e6 | 5439 | return FALSE; |
a1d78564 RS |
5440 | |
5441 | if (sval != 0 | |
5442 | && (sval != 1 | |
5443 | || (mips_opts.arch == CPU_R5900 | |
5444 | && (strcmp (arg->insn->insn_mo->name, "mfps") == 0 | |
5445 | || strcmp (arg->insn->insn_mo->name, "mtps") == 0)))) | |
5446 | { | |
1a00e612 RS |
5447 | set_insn_error (arg->argnum, _("invalid performance register")); |
5448 | return FALSE; | |
a1d78564 RS |
5449 | } |
5450 | ||
5451 | insn_insert_operand (arg->insn, operand, sval); | |
a92713e6 | 5452 | return TRUE; |
a1d78564 RS |
5453 | } |
5454 | ||
5455 | /* OP_ADDIUSP matcher. */ | |
5456 | ||
a92713e6 | 5457 | static bfd_boolean |
a1d78564 | 5458 | match_addiusp_operand (struct mips_arg_info *arg, |
a92713e6 | 5459 | const struct mips_operand *operand) |
a1d78564 RS |
5460 | { |
5461 | offsetT sval; | |
5462 | unsigned int uval; | |
5463 | ||
1a00e612 | 5464 | if (!match_const_int (arg, &sval)) |
a92713e6 | 5465 | return FALSE; |
a1d78564 RS |
5466 | |
5467 | if (sval % 4) | |
1a00e612 RS |
5468 | { |
5469 | match_out_of_range (arg); | |
5470 | return FALSE; | |
5471 | } | |
a1d78564 RS |
5472 | |
5473 | sval /= 4; | |
5474 | if (!(sval >= -258 && sval <= 257) || (sval >= -2 && sval <= 1)) | |
1a00e612 RS |
5475 | { |
5476 | match_out_of_range (arg); | |
5477 | return FALSE; | |
5478 | } | |
a1d78564 RS |
5479 | |
5480 | uval = (unsigned int) sval; | |
5481 | uval = ((uval >> 1) & ~0xff) | (uval & 0xff); | |
5482 | insn_insert_operand (arg->insn, operand, uval); | |
a92713e6 | 5483 | return TRUE; |
a1d78564 RS |
5484 | } |
5485 | ||
5486 | /* OP_CLO_CLZ_DEST matcher. */ | |
5487 | ||
a92713e6 | 5488 | static bfd_boolean |
a1d78564 | 5489 | match_clo_clz_dest_operand (struct mips_arg_info *arg, |
a92713e6 | 5490 | const struct mips_operand *operand) |
a1d78564 RS |
5491 | { |
5492 | unsigned int regno; | |
5493 | ||
a92713e6 RS |
5494 | if (!match_reg (arg, OP_REG_GP, ®no)) |
5495 | return FALSE; | |
a1d78564 | 5496 | |
a1d78564 | 5497 | insn_insert_operand (arg->insn, operand, regno | (regno << 5)); |
a92713e6 | 5498 | return TRUE; |
a1d78564 RS |
5499 | } |
5500 | ||
7361da2c AB |
5501 | /* OP_CHECK_PREV matcher. */ |
5502 | ||
5503 | static bfd_boolean | |
5504 | match_check_prev_operand (struct mips_arg_info *arg, | |
5505 | const struct mips_operand *operand_base) | |
5506 | { | |
5507 | const struct mips_check_prev_operand *operand; | |
5508 | unsigned int regno; | |
5509 | ||
5510 | operand = (const struct mips_check_prev_operand *) operand_base; | |
5511 | ||
5512 | if (!match_reg (arg, OP_REG_GP, ®no)) | |
5513 | return FALSE; | |
5514 | ||
5515 | if (!operand->zero_ok && regno == 0) | |
5516 | return FALSE; | |
5517 | ||
5518 | if ((operand->less_than_ok && regno < arg->last_regno) | |
5519 | || (operand->greater_than_ok && regno > arg->last_regno) | |
5520 | || (operand->equal_ok && regno == arg->last_regno)) | |
5521 | { | |
5522 | arg->last_regno = regno; | |
5523 | insn_insert_operand (arg->insn, operand_base, regno); | |
5524 | return TRUE; | |
5525 | } | |
5526 | ||
5527 | return FALSE; | |
5528 | } | |
5529 | ||
5530 | /* OP_SAME_RS_RT matcher. */ | |
5531 | ||
5532 | static bfd_boolean | |
5533 | match_same_rs_rt_operand (struct mips_arg_info *arg, | |
5534 | const struct mips_operand *operand) | |
5535 | { | |
5536 | unsigned int regno; | |
5537 | ||
5538 | if (!match_reg (arg, OP_REG_GP, ®no)) | |
5539 | return FALSE; | |
5540 | ||
5541 | if (regno == 0) | |
5542 | { | |
5543 | set_insn_error (arg->argnum, _("the source register must not be $0")); | |
5544 | return FALSE; | |
5545 | } | |
5546 | ||
5547 | arg->last_regno = regno; | |
5548 | ||
5549 | insn_insert_operand (arg->insn, operand, regno | (regno << 5)); | |
5550 | return TRUE; | |
5551 | } | |
5552 | ||
a1d78564 RS |
5553 | /* OP_LWM_SWM_LIST matcher. */ |
5554 | ||
a92713e6 | 5555 | static bfd_boolean |
a1d78564 | 5556 | match_lwm_swm_list_operand (struct mips_arg_info *arg, |
a92713e6 | 5557 | const struct mips_operand *operand) |
a1d78564 | 5558 | { |
a92713e6 RS |
5559 | unsigned int reglist, sregs, ra, regno1, regno2; |
5560 | struct mips_arg_info reset; | |
a1d78564 | 5561 | |
a92713e6 RS |
5562 | reglist = 0; |
5563 | if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2)) | |
5564 | return FALSE; | |
5565 | do | |
5566 | { | |
5567 | if (regno2 == FP && regno1 >= S0 && regno1 <= S7) | |
5568 | { | |
5569 | reglist |= 1 << FP; | |
5570 | regno2 = S7; | |
5571 | } | |
5572 | reglist |= ((1U << regno2 << 1) - 1) & -(1U << regno1); | |
5573 | reset = *arg; | |
5574 | } | |
5575 | while (match_char (arg, ',') | |
5576 | && match_reg_range (arg, OP_REG_GP, ®no1, ®no2)); | |
5577 | *arg = reset; | |
a1d78564 RS |
5578 | |
5579 | if (operand->size == 2) | |
5580 | { | |
5581 | /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.: | |
5582 | ||
5583 | s0, ra | |
5584 | s0, s1, ra, s2, s3 | |
5585 | s0-s2, ra | |
5586 | ||
5587 | and any permutations of these. */ | |
5588 | if ((reglist & 0xfff1ffff) != 0x80010000) | |
a92713e6 | 5589 | return FALSE; |
a1d78564 RS |
5590 | |
5591 | sregs = (reglist >> 17) & 7; | |
5592 | ra = 0; | |
5593 | } | |
5594 | else | |
5595 | { | |
5596 | /* The list must include at least one of ra and s0-sN, | |
5597 | for 0 <= N <= 8. (Note that there is a gap between s7 and s8, | |
5598 | which are $23 and $30 respectively.) E.g.: | |
5599 | ||
5600 | ra | |
5601 | s0 | |
5602 | ra, s0, s1, s2 | |
5603 | s0-s8 | |
5604 | s0-s5, ra | |
5605 | ||
5606 | and any permutations of these. */ | |
5607 | if ((reglist & 0x3f00ffff) != 0) | |
a92713e6 | 5608 | return FALSE; |
a1d78564 RS |
5609 | |
5610 | ra = (reglist >> 27) & 0x10; | |
5611 | sregs = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff); | |
5612 | } | |
5613 | sregs += 1; | |
5614 | if ((sregs & -sregs) != sregs) | |
a92713e6 | 5615 | return FALSE; |
a1d78564 RS |
5616 | |
5617 | insn_insert_operand (arg->insn, operand, (ffs (sregs) - 1) | ra); | |
a92713e6 | 5618 | return TRUE; |
a1d78564 RS |
5619 | } |
5620 | ||
364215c8 RS |
5621 | /* OP_ENTRY_EXIT_LIST matcher. */ |
5622 | ||
a92713e6 | 5623 | static unsigned int |
364215c8 | 5624 | match_entry_exit_operand (struct mips_arg_info *arg, |
a92713e6 | 5625 | const struct mips_operand *operand) |
364215c8 RS |
5626 | { |
5627 | unsigned int mask; | |
5628 | bfd_boolean is_exit; | |
5629 | ||
5630 | /* The format is the same for both ENTRY and EXIT, but the constraints | |
5631 | are different. */ | |
5632 | is_exit = strcmp (arg->insn->insn_mo->name, "exit") == 0; | |
5633 | mask = (is_exit ? 7 << 3 : 0); | |
a92713e6 | 5634 | do |
364215c8 RS |
5635 | { |
5636 | unsigned int regno1, regno2; | |
5637 | bfd_boolean is_freg; | |
5638 | ||
a92713e6 | 5639 | if (match_reg_range (arg, OP_REG_GP, ®no1, ®no2)) |
364215c8 | 5640 | is_freg = FALSE; |
a92713e6 | 5641 | else if (match_reg_range (arg, OP_REG_FP, ®no1, ®no2)) |
364215c8 RS |
5642 | is_freg = TRUE; |
5643 | else | |
a92713e6 | 5644 | return FALSE; |
364215c8 RS |
5645 | |
5646 | if (is_exit && is_freg && regno1 == 0 && regno2 < 2) | |
5647 | { | |
5648 | mask &= ~(7 << 3); | |
5649 | mask |= (5 + regno2) << 3; | |
5650 | } | |
5651 | else if (!is_exit && regno1 == 4 && regno2 >= 4 && regno2 <= 7) | |
5652 | mask |= (regno2 - 3) << 3; | |
5653 | else if (regno1 == 16 && regno2 >= 16 && regno2 <= 17) | |
5654 | mask |= (regno2 - 15) << 1; | |
5655 | else if (regno1 == RA && regno2 == RA) | |
5656 | mask |= 1; | |
5657 | else | |
a92713e6 | 5658 | return FALSE; |
364215c8 | 5659 | } |
a92713e6 RS |
5660 | while (match_char (arg, ',')); |
5661 | ||
364215c8 | 5662 | insn_insert_operand (arg->insn, operand, mask); |
a92713e6 | 5663 | return TRUE; |
364215c8 RS |
5664 | } |
5665 | ||
38bf472a MR |
5666 | /* Encode regular MIPS SAVE/RESTORE instruction operands according to |
5667 | the argument register mask AMASK, the number of static registers | |
5668 | saved NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1 | |
5669 | respectively, and the frame size FRAME_SIZE. */ | |
5670 | ||
5671 | static unsigned int | |
5672 | mips_encode_save_restore (unsigned int amask, unsigned int nsreg, | |
5673 | unsigned int ra, unsigned int s0, unsigned int s1, | |
5674 | unsigned int frame_size) | |
5675 | { | |
5676 | return ((nsreg << 23) | ((frame_size & 0xf0) << 15) | (amask << 15) | |
5677 | | (ra << 12) | (s0 << 11) | (s1 << 10) | ((frame_size & 0xf) << 6)); | |
5678 | } | |
5679 | ||
5680 | /* Encode MIPS16 SAVE/RESTORE instruction operands according to the | |
5681 | argument register mask AMASK, the number of static registers saved | |
5682 | NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1 | |
5683 | respectively, and the frame size FRAME_SIZE. */ | |
5684 | ||
5685 | static unsigned int | |
5686 | mips16_encode_save_restore (unsigned int amask, unsigned int nsreg, | |
5687 | unsigned int ra, unsigned int s0, unsigned int s1, | |
5688 | unsigned int frame_size) | |
5689 | { | |
5690 | unsigned int args; | |
5691 | ||
5692 | args = (ra << 6) | (s0 << 5) | (s1 << 4) | (frame_size & 0xf); | |
5693 | if (nsreg || amask || frame_size == 0 || frame_size > 16) | |
5694 | args |= (MIPS16_EXTEND | (nsreg << 24) | (amask << 16) | |
5695 | | ((frame_size & 0xf0) << 16)); | |
5696 | return args; | |
5697 | } | |
5698 | ||
364215c8 RS |
5699 | /* OP_SAVE_RESTORE_LIST matcher. */ |
5700 | ||
a92713e6 RS |
5701 | static bfd_boolean |
5702 | match_save_restore_list_operand (struct mips_arg_info *arg) | |
364215c8 RS |
5703 | { |
5704 | unsigned int opcode, args, statics, sregs; | |
5705 | unsigned int num_frame_sizes, num_args, num_statics, num_sregs; | |
38bf472a | 5706 | unsigned int arg_mask, ra, s0, s1; |
364215c8 | 5707 | offsetT frame_size; |
364215c8 | 5708 | |
364215c8 RS |
5709 | opcode = arg->insn->insn_opcode; |
5710 | frame_size = 0; | |
5711 | num_frame_sizes = 0; | |
5712 | args = 0; | |
5713 | statics = 0; | |
5714 | sregs = 0; | |
38bf472a MR |
5715 | ra = 0; |
5716 | s0 = 0; | |
5717 | s1 = 0; | |
a92713e6 | 5718 | do |
364215c8 RS |
5719 | { |
5720 | unsigned int regno1, regno2; | |
5721 | ||
a92713e6 | 5722 | if (arg->token->type == OT_INTEGER) |
364215c8 RS |
5723 | { |
5724 | /* Handle the frame size. */ | |
1a00e612 | 5725 | if (!match_const_int (arg, &frame_size)) |
a92713e6 | 5726 | return FALSE; |
364215c8 | 5727 | num_frame_sizes += 1; |
364215c8 RS |
5728 | } |
5729 | else | |
5730 | { | |
a92713e6 RS |
5731 | if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2)) |
5732 | return FALSE; | |
364215c8 RS |
5733 | |
5734 | while (regno1 <= regno2) | |
5735 | { | |
5736 | if (regno1 >= 4 && regno1 <= 7) | |
5737 | { | |
5738 | if (num_frame_sizes == 0) | |
5739 | /* args $a0-$a3 */ | |
5740 | args |= 1 << (regno1 - 4); | |
5741 | else | |
5742 | /* statics $a0-$a3 */ | |
5743 | statics |= 1 << (regno1 - 4); | |
5744 | } | |
5745 | else if (regno1 >= 16 && regno1 <= 23) | |
5746 | /* $s0-$s7 */ | |
5747 | sregs |= 1 << (regno1 - 16); | |
5748 | else if (regno1 == 30) | |
5749 | /* $s8 */ | |
5750 | sregs |= 1 << 8; | |
5751 | else if (regno1 == 31) | |
5752 | /* Add $ra to insn. */ | |
38bf472a | 5753 | ra = 1; |
364215c8 | 5754 | else |
a92713e6 | 5755 | return FALSE; |
364215c8 RS |
5756 | regno1 += 1; |
5757 | if (regno1 == 24) | |
5758 | regno1 = 30; | |
5759 | } | |
5760 | } | |
364215c8 | 5761 | } |
a92713e6 | 5762 | while (match_char (arg, ',')); |
364215c8 RS |
5763 | |
5764 | /* Encode args/statics combination. */ | |
5765 | if (args & statics) | |
a92713e6 | 5766 | return FALSE; |
364215c8 RS |
5767 | else if (args == 0xf) |
5768 | /* All $a0-$a3 are args. */ | |
38bf472a | 5769 | arg_mask = MIPS_SVRS_ALL_ARGS; |
364215c8 RS |
5770 | else if (statics == 0xf) |
5771 | /* All $a0-$a3 are statics. */ | |
38bf472a | 5772 | arg_mask = MIPS_SVRS_ALL_STATICS; |
364215c8 RS |
5773 | else |
5774 | { | |
5775 | /* Count arg registers. */ | |
5776 | num_args = 0; | |
5777 | while (args & 0x1) | |
5778 | { | |
5779 | args >>= 1; | |
5780 | num_args += 1; | |
5781 | } | |
5782 | if (args != 0) | |
a92713e6 | 5783 | return FALSE; |
364215c8 RS |
5784 | |
5785 | /* Count static registers. */ | |
5786 | num_statics = 0; | |
5787 | while (statics & 0x8) | |
5788 | { | |
5789 | statics = (statics << 1) & 0xf; | |
5790 | num_statics += 1; | |
5791 | } | |
5792 | if (statics != 0) | |
a92713e6 | 5793 | return FALSE; |
364215c8 RS |
5794 | |
5795 | /* Encode args/statics. */ | |
38bf472a | 5796 | arg_mask = (num_args << 2) | num_statics; |
364215c8 RS |
5797 | } |
5798 | ||
5799 | /* Encode $s0/$s1. */ | |
5800 | if (sregs & (1 << 0)) /* $s0 */ | |
38bf472a | 5801 | s0 = 1; |
364215c8 | 5802 | if (sregs & (1 << 1)) /* $s1 */ |
38bf472a | 5803 | s1 = 1; |
364215c8 RS |
5804 | sregs >>= 2; |
5805 | ||
5806 | /* Encode $s2-$s8. */ | |
5807 | num_sregs = 0; | |
5808 | while (sregs & 1) | |
5809 | { | |
5810 | sregs >>= 1; | |
5811 | num_sregs += 1; | |
5812 | } | |
5813 | if (sregs != 0) | |
a92713e6 | 5814 | return FALSE; |
364215c8 RS |
5815 | |
5816 | /* Encode frame size. */ | |
5817 | if (num_frame_sizes == 0) | |
1a00e612 RS |
5818 | { |
5819 | set_insn_error (arg->argnum, _("missing frame size")); | |
5820 | return FALSE; | |
5821 | } | |
5822 | if (num_frame_sizes > 1) | |
5823 | { | |
5824 | set_insn_error (arg->argnum, _("frame size specified twice")); | |
5825 | return FALSE; | |
5826 | } | |
5827 | if ((frame_size & 7) != 0 || frame_size < 0 || frame_size > 0xff * 8) | |
5828 | { | |
5829 | set_insn_error (arg->argnum, _("invalid frame size")); | |
5830 | return FALSE; | |
5831 | } | |
38bf472a | 5832 | frame_size /= 8; |
364215c8 | 5833 | |
364215c8 | 5834 | /* Finally build the instruction. */ |
38bf472a MR |
5835 | if (mips_opts.mips16) |
5836 | opcode |= mips16_encode_save_restore (arg_mask, num_sregs, ra, s0, s1, | |
5837 | frame_size); | |
5838 | else if (!mips_opts.micromips) | |
5839 | opcode |= mips_encode_save_restore (arg_mask, num_sregs, ra, s0, s1, | |
5840 | frame_size); | |
5841 | else | |
5842 | abort (); | |
5843 | ||
364215c8 | 5844 | arg->insn->insn_opcode = opcode; |
a92713e6 | 5845 | return TRUE; |
364215c8 RS |
5846 | } |
5847 | ||
a1d78564 RS |
5848 | /* OP_MDMX_IMM_REG matcher. */ |
5849 | ||
a92713e6 | 5850 | static bfd_boolean |
a1d78564 | 5851 | match_mdmx_imm_reg_operand (struct mips_arg_info *arg, |
a92713e6 | 5852 | const struct mips_operand *operand) |
a1d78564 | 5853 | { |
a92713e6 | 5854 | unsigned int regno, uval; |
a1d78564 RS |
5855 | bfd_boolean is_qh; |
5856 | const struct mips_opcode *opcode; | |
5857 | ||
5858 | /* The mips_opcode records whether this is an octobyte or quadhalf | |
5859 | instruction. Start out with that bit in place. */ | |
5860 | opcode = arg->insn->insn_mo; | |
5861 | uval = mips_extract_operand (operand, opcode->match); | |
5862 | is_qh = (uval != 0); | |
5863 | ||
56d438b1 | 5864 | if (arg->token->type == OT_REG) |
a1d78564 RS |
5865 | { |
5866 | if ((opcode->membership & INSN_5400) | |
5867 | && strcmp (opcode->name, "rzu.ob") == 0) | |
5868 | { | |
1a00e612 RS |
5869 | set_insn_error_i (arg->argnum, _("operand %d must be an immediate"), |
5870 | arg->argnum); | |
5871 | return FALSE; | |
a1d78564 RS |
5872 | } |
5873 | ||
56d438b1 CF |
5874 | if (!match_regno (arg, OP_REG_VEC, arg->token->u.regno, ®no)) |
5875 | return FALSE; | |
5876 | ++arg->token; | |
5877 | ||
a1d78564 RS |
5878 | /* Check whether this is a vector register or a broadcast of |
5879 | a single element. */ | |
56d438b1 | 5880 | if (arg->token->type == OT_INTEGER_INDEX) |
a1d78564 | 5881 | { |
56d438b1 | 5882 | if (arg->token->u.index > (is_qh ? 3 : 7)) |
a1d78564 | 5883 | { |
1a00e612 RS |
5884 | set_insn_error (arg->argnum, _("invalid element selector")); |
5885 | return FALSE; | |
a1d78564 | 5886 | } |
56d438b1 CF |
5887 | uval |= arg->token->u.index << (is_qh ? 2 : 1) << 5; |
5888 | ++arg->token; | |
a1d78564 RS |
5889 | } |
5890 | else | |
5891 | { | |
5892 | /* A full vector. */ | |
5893 | if ((opcode->membership & INSN_5400) | |
5894 | && (strcmp (opcode->name, "sll.ob") == 0 | |
5895 | || strcmp (opcode->name, "srl.ob") == 0)) | |
5896 | { | |
1a00e612 RS |
5897 | set_insn_error_i (arg->argnum, _("operand %d must be scalar"), |
5898 | arg->argnum); | |
5899 | return FALSE; | |
a1d78564 RS |
5900 | } |
5901 | ||
5902 | if (is_qh) | |
5903 | uval |= MDMX_FMTSEL_VEC_QH << 5; | |
5904 | else | |
5905 | uval |= MDMX_FMTSEL_VEC_OB << 5; | |
5906 | } | |
a1d78564 RS |
5907 | uval |= regno; |
5908 | } | |
5909 | else | |
5910 | { | |
5911 | offsetT sval; | |
5912 | ||
1a00e612 | 5913 | if (!match_const_int (arg, &sval)) |
a92713e6 | 5914 | return FALSE; |
a1d78564 RS |
5915 | if (sval < 0 || sval > 31) |
5916 | { | |
1a00e612 RS |
5917 | match_out_of_range (arg); |
5918 | return FALSE; | |
a1d78564 RS |
5919 | } |
5920 | uval |= (sval & 31); | |
5921 | if (is_qh) | |
5922 | uval |= MDMX_FMTSEL_IMM_QH << 5; | |
5923 | else | |
5924 | uval |= MDMX_FMTSEL_IMM_OB << 5; | |
5925 | } | |
5926 | insn_insert_operand (arg->insn, operand, uval); | |
a92713e6 | 5927 | return TRUE; |
a1d78564 RS |
5928 | } |
5929 | ||
56d438b1 CF |
5930 | /* OP_IMM_INDEX matcher. */ |
5931 | ||
5932 | static bfd_boolean | |
5933 | match_imm_index_operand (struct mips_arg_info *arg, | |
5934 | const struct mips_operand *operand) | |
5935 | { | |
5936 | unsigned int max_val; | |
5937 | ||
5938 | if (arg->token->type != OT_INTEGER_INDEX) | |
5939 | return FALSE; | |
5940 | ||
5941 | max_val = (1 << operand->size) - 1; | |
5942 | if (arg->token->u.index > max_val) | |
5943 | { | |
5944 | match_out_of_range (arg); | |
5945 | return FALSE; | |
5946 | } | |
5947 | insn_insert_operand (arg->insn, operand, arg->token->u.index); | |
5948 | ++arg->token; | |
5949 | return TRUE; | |
5950 | } | |
5951 | ||
5952 | /* OP_REG_INDEX matcher. */ | |
5953 | ||
5954 | static bfd_boolean | |
5955 | match_reg_index_operand (struct mips_arg_info *arg, | |
5956 | const struct mips_operand *operand) | |
5957 | { | |
5958 | unsigned int regno; | |
5959 | ||
5960 | if (arg->token->type != OT_REG_INDEX) | |
5961 | return FALSE; | |
5962 | ||
5963 | if (!match_regno (arg, OP_REG_GP, arg->token->u.regno, ®no)) | |
5964 | return FALSE; | |
5965 | ||
5966 | insn_insert_operand (arg->insn, operand, regno); | |
5967 | ++arg->token; | |
5968 | return TRUE; | |
5969 | } | |
5970 | ||
a1d78564 RS |
5971 | /* OP_PC matcher. */ |
5972 | ||
a92713e6 RS |
5973 | static bfd_boolean |
5974 | match_pc_operand (struct mips_arg_info *arg) | |
a1d78564 | 5975 | { |
a92713e6 RS |
5976 | if (arg->token->type == OT_REG && (arg->token->u.regno & RTYPE_PC)) |
5977 | { | |
5978 | ++arg->token; | |
5979 | return TRUE; | |
5980 | } | |
5981 | return FALSE; | |
a1d78564 RS |
5982 | } |
5983 | ||
25499ac7 MR |
5984 | /* OP_REG28 matcher. */ |
5985 | ||
5986 | static bfd_boolean | |
5987 | match_reg28_operand (struct mips_arg_info *arg) | |
5988 | { | |
5989 | unsigned int regno; | |
5990 | ||
5991 | if (arg->token->type == OT_REG | |
5992 | && match_regno (arg, OP_REG_GP, arg->token->u.regno, ®no) | |
5993 | && regno == GP) | |
5994 | { | |
5995 | ++arg->token; | |
5996 | return TRUE; | |
5997 | } | |
5998 | return FALSE; | |
5999 | } | |
6000 | ||
7361da2c AB |
6001 | /* OP_NON_ZERO_REG matcher. */ |
6002 | ||
6003 | static bfd_boolean | |
6004 | match_non_zero_reg_operand (struct mips_arg_info *arg, | |
6005 | const struct mips_operand *operand) | |
6006 | { | |
6007 | unsigned int regno; | |
6008 | ||
6009 | if (!match_reg (arg, OP_REG_GP, ®no)) | |
6010 | return FALSE; | |
6011 | ||
6012 | if (regno == 0) | |
6013 | return FALSE; | |
6014 | ||
6015 | arg->last_regno = regno; | |
6016 | insn_insert_operand (arg->insn, operand, regno); | |
6017 | return TRUE; | |
6018 | } | |
6019 | ||
a1d78564 RS |
6020 | /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the |
6021 | register that we need to match. */ | |
6022 | ||
a92713e6 RS |
6023 | static bfd_boolean |
6024 | match_tied_reg_operand (struct mips_arg_info *arg, unsigned int other_regno) | |
a1d78564 RS |
6025 | { |
6026 | unsigned int regno; | |
6027 | ||
a92713e6 | 6028 | return match_reg (arg, OP_REG_GP, ®no) && regno == other_regno; |
a1d78564 RS |
6029 | } |
6030 | ||
33f46696 MR |
6031 | /* Try to match a floating-point constant from ARG for LI.S or LI.D. |
6032 | LENGTH is the length of the value in bytes (4 for float, 8 for double) | |
6033 | and USING_GPRS says whether the destination is a GPR rather than an FPR. | |
89565f1b RS |
6034 | |
6035 | Return the constant in IMM and OFFSET as follows: | |
6036 | ||
6037 | - If the constant should be loaded via memory, set IMM to O_absent and | |
6038 | OFFSET to the memory address. | |
6039 | ||
6040 | - Otherwise, if the constant should be loaded into two 32-bit registers, | |
6041 | set IMM to the O_constant to load into the high register and OFFSET | |
6042 | to the corresponding value for the low register. | |
6043 | ||
6044 | - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent. | |
6045 | ||
6046 | These constants only appear as the last operand in an instruction, | |
6047 | and every instruction that accepts them in any variant accepts them | |
6048 | in all variants. This means we don't have to worry about backing out | |
6049 | any changes if the instruction does not match. We just match | |
6050 | unconditionally and report an error if the constant is invalid. */ | |
6051 | ||
a92713e6 RS |
6052 | static bfd_boolean |
6053 | match_float_constant (struct mips_arg_info *arg, expressionS *imm, | |
6054 | expressionS *offset, int length, bfd_boolean using_gprs) | |
89565f1b | 6055 | { |
a92713e6 | 6056 | char *p; |
89565f1b RS |
6057 | segT seg, new_seg; |
6058 | subsegT subseg; | |
6059 | const char *newname; | |
a92713e6 | 6060 | unsigned char *data; |
89565f1b RS |
6061 | |
6062 | /* Where the constant is placed is based on how the MIPS assembler | |
6063 | does things: | |
6064 | ||
6065 | length == 4 && using_gprs -- immediate value only | |
6066 | length == 8 && using_gprs -- .rdata or immediate value | |
6067 | length == 4 && !using_gprs -- .lit4 or immediate value | |
6068 | length == 8 && !using_gprs -- .lit8 or immediate value | |
6069 | ||
6070 | The .lit4 and .lit8 sections are only used if permitted by the | |
6071 | -G argument. */ | |
a92713e6 | 6072 | if (arg->token->type != OT_FLOAT) |
1a00e612 RS |
6073 | { |
6074 | set_insn_error (arg->argnum, _("floating-point expression required")); | |
6075 | return FALSE; | |
6076 | } | |
a92713e6 RS |
6077 | |
6078 | gas_assert (arg->token->u.flt.length == length); | |
6079 | data = arg->token->u.flt.data; | |
6080 | ++arg->token; | |
89565f1b RS |
6081 | |
6082 | /* Handle 32-bit constants for which an immediate value is best. */ | |
6083 | if (length == 4 | |
6084 | && (using_gprs | |
6085 | || g_switch_value < 4 | |
6086 | || (data[0] == 0 && data[1] == 0) | |
6087 | || (data[2] == 0 && data[3] == 0))) | |
6088 | { | |
6089 | imm->X_op = O_constant; | |
6090 | if (!target_big_endian) | |
6091 | imm->X_add_number = bfd_getl32 (data); | |
6092 | else | |
6093 | imm->X_add_number = bfd_getb32 (data); | |
6094 | offset->X_op = O_absent; | |
a92713e6 | 6095 | return TRUE; |
89565f1b RS |
6096 | } |
6097 | ||
6098 | /* Handle 64-bit constants for which an immediate value is best. */ | |
6099 | if (length == 8 | |
6100 | && !mips_disable_float_construction | |
351cdf24 MF |
6101 | /* Constants can only be constructed in GPRs and copied to FPRs if the |
6102 | GPRs are at least as wide as the FPRs or MTHC1 is available. | |
6103 | Unlike most tests for 32-bit floating-point registers this check | |
6104 | specifically looks for GPR_SIZE == 32 as the FPXX ABI does not | |
6105 | permit 64-bit moves without MXHC1. | |
6106 | Force the constant into memory otherwise. */ | |
6107 | && (using_gprs | |
6108 | || GPR_SIZE == 64 | |
6109 | || ISA_HAS_MXHC1 (mips_opts.isa) | |
6110 | || FPR_SIZE == 32) | |
89565f1b RS |
6111 | && ((data[0] == 0 && data[1] == 0) |
6112 | || (data[2] == 0 && data[3] == 0)) | |
6113 | && ((data[4] == 0 && data[5] == 0) | |
6114 | || (data[6] == 0 && data[7] == 0))) | |
6115 | { | |
6116 | /* The value is simple enough to load with a couple of instructions. | |
6117 | If using 32-bit registers, set IMM to the high order 32 bits and | |
6118 | OFFSET to the low order 32 bits. Otherwise, set IMM to the entire | |
6119 | 64 bit constant. */ | |
351cdf24 | 6120 | if (GPR_SIZE == 32 || (!using_gprs && FPR_SIZE != 64)) |
89565f1b RS |
6121 | { |
6122 | imm->X_op = O_constant; | |
6123 | offset->X_op = O_constant; | |
6124 | if (!target_big_endian) | |
6125 | { | |
6126 | imm->X_add_number = bfd_getl32 (data + 4); | |
6127 | offset->X_add_number = bfd_getl32 (data); | |
6128 | } | |
6129 | else | |
6130 | { | |
6131 | imm->X_add_number = bfd_getb32 (data); | |
6132 | offset->X_add_number = bfd_getb32 (data + 4); | |
6133 | } | |
6134 | if (offset->X_add_number == 0) | |
6135 | offset->X_op = O_absent; | |
6136 | } | |
6137 | else | |
6138 | { | |
6139 | imm->X_op = O_constant; | |
6140 | if (!target_big_endian) | |
6141 | imm->X_add_number = bfd_getl64 (data); | |
6142 | else | |
6143 | imm->X_add_number = bfd_getb64 (data); | |
6144 | offset->X_op = O_absent; | |
6145 | } | |
a92713e6 | 6146 | return TRUE; |
89565f1b RS |
6147 | } |
6148 | ||
6149 | /* Switch to the right section. */ | |
6150 | seg = now_seg; | |
6151 | subseg = now_subseg; | |
6152 | if (length == 4) | |
6153 | { | |
6154 | gas_assert (!using_gprs && g_switch_value >= 4); | |
6155 | newname = ".lit4"; | |
6156 | } | |
6157 | else | |
6158 | { | |
6159 | if (using_gprs || g_switch_value < 8) | |
6160 | newname = RDATA_SECTION_NAME; | |
6161 | else | |
6162 | newname = ".lit8"; | |
6163 | } | |
6164 | ||
6165 | new_seg = subseg_new (newname, (subsegT) 0); | |
6166 | bfd_set_section_flags (stdoutput, new_seg, | |
6167 | SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_DATA); | |
6168 | frag_align (length == 4 ? 2 : 3, 0, 0); | |
6169 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
6170 | record_alignment (new_seg, 4); | |
6171 | else | |
6172 | record_alignment (new_seg, length == 4 ? 2 : 3); | |
6173 | if (seg == now_seg) | |
1661c76c | 6174 | as_bad (_("cannot use `%s' in this section"), arg->insn->insn_mo->name); |
89565f1b RS |
6175 | |
6176 | /* Set the argument to the current address in the section. */ | |
6177 | imm->X_op = O_absent; | |
6178 | offset->X_op = O_symbol; | |
6179 | offset->X_add_symbol = symbol_temp_new_now (); | |
6180 | offset->X_add_number = 0; | |
6181 | ||
6182 | /* Put the floating point number into the section. */ | |
6183 | p = frag_more (length); | |
6184 | memcpy (p, data, length); | |
6185 | ||
6186 | /* Switch back to the original section. */ | |
6187 | subseg_set (seg, subseg); | |
a92713e6 | 6188 | return TRUE; |
89565f1b RS |
6189 | } |
6190 | ||
14daeee3 RS |
6191 | /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between |
6192 | them. */ | |
6193 | ||
6194 | static bfd_boolean | |
6195 | match_vu0_suffix_operand (struct mips_arg_info *arg, | |
6196 | const struct mips_operand *operand, | |
6197 | bfd_boolean match_p) | |
6198 | { | |
6199 | unsigned int uval; | |
6200 | ||
6201 | /* The operand can be an XYZW mask or a single 2-bit channel index | |
6202 | (with X being 0). */ | |
6203 | gas_assert (operand->size == 2 || operand->size == 4); | |
6204 | ||
ee5734f0 | 6205 | /* The suffix can be omitted when it is already part of the opcode. */ |
14daeee3 | 6206 | if (arg->token->type != OT_CHANNELS) |
ee5734f0 | 6207 | return match_p; |
14daeee3 RS |
6208 | |
6209 | uval = arg->token->u.channels; | |
6210 | if (operand->size == 2) | |
6211 | { | |
6212 | /* Check that a single bit is set and convert it into a 2-bit index. */ | |
6213 | if ((uval & -uval) != uval) | |
6214 | return FALSE; | |
6215 | uval = 4 - ffs (uval); | |
6216 | } | |
6217 | ||
6218 | if (match_p && insn_extract_operand (arg->insn, operand) != uval) | |
6219 | return FALSE; | |
6220 | ||
6221 | ++arg->token; | |
6222 | if (!match_p) | |
6223 | insn_insert_operand (arg->insn, operand, uval); | |
6224 | return TRUE; | |
6225 | } | |
6226 | ||
33f46696 MR |
6227 | /* Try to match a token from ARG against OPERAND. Consume the token |
6228 | and return true on success, otherwise return false. */ | |
a1d78564 | 6229 | |
a92713e6 | 6230 | static bfd_boolean |
a1d78564 | 6231 | match_operand (struct mips_arg_info *arg, |
a92713e6 | 6232 | const struct mips_operand *operand) |
a1d78564 RS |
6233 | { |
6234 | switch (operand->type) | |
6235 | { | |
6236 | case OP_INT: | |
a92713e6 | 6237 | return match_int_operand (arg, operand); |
a1d78564 RS |
6238 | |
6239 | case OP_MAPPED_INT: | |
a92713e6 | 6240 | return match_mapped_int_operand (arg, operand); |
a1d78564 RS |
6241 | |
6242 | case OP_MSB: | |
a92713e6 | 6243 | return match_msb_operand (arg, operand); |
a1d78564 RS |
6244 | |
6245 | case OP_REG: | |
0f35dbc4 | 6246 | case OP_OPTIONAL_REG: |
a92713e6 | 6247 | return match_reg_operand (arg, operand); |
a1d78564 RS |
6248 | |
6249 | case OP_REG_PAIR: | |
a92713e6 | 6250 | return match_reg_pair_operand (arg, operand); |
a1d78564 RS |
6251 | |
6252 | case OP_PCREL: | |
a92713e6 | 6253 | return match_pcrel_operand (arg); |
a1d78564 RS |
6254 | |
6255 | case OP_PERF_REG: | |
a92713e6 | 6256 | return match_perf_reg_operand (arg, operand); |
a1d78564 RS |
6257 | |
6258 | case OP_ADDIUSP_INT: | |
a92713e6 | 6259 | return match_addiusp_operand (arg, operand); |
a1d78564 RS |
6260 | |
6261 | case OP_CLO_CLZ_DEST: | |
a92713e6 | 6262 | return match_clo_clz_dest_operand (arg, operand); |
a1d78564 RS |
6263 | |
6264 | case OP_LWM_SWM_LIST: | |
a92713e6 | 6265 | return match_lwm_swm_list_operand (arg, operand); |
a1d78564 RS |
6266 | |
6267 | case OP_ENTRY_EXIT_LIST: | |
a92713e6 | 6268 | return match_entry_exit_operand (arg, operand); |
364215c8 | 6269 | |
a1d78564 | 6270 | case OP_SAVE_RESTORE_LIST: |
a92713e6 | 6271 | return match_save_restore_list_operand (arg); |
a1d78564 RS |
6272 | |
6273 | case OP_MDMX_IMM_REG: | |
a92713e6 | 6274 | return match_mdmx_imm_reg_operand (arg, operand); |
a1d78564 RS |
6275 | |
6276 | case OP_REPEAT_DEST_REG: | |
a92713e6 | 6277 | return match_tied_reg_operand (arg, arg->dest_regno); |
a1d78564 RS |
6278 | |
6279 | case OP_REPEAT_PREV_REG: | |
a92713e6 | 6280 | return match_tied_reg_operand (arg, arg->last_regno); |
a1d78564 RS |
6281 | |
6282 | case OP_PC: | |
a92713e6 | 6283 | return match_pc_operand (arg); |
14daeee3 | 6284 | |
25499ac7 MR |
6285 | case OP_REG28: |
6286 | return match_reg28_operand (arg); | |
6287 | ||
14daeee3 RS |
6288 | case OP_VU0_SUFFIX: |
6289 | return match_vu0_suffix_operand (arg, operand, FALSE); | |
6290 | ||
6291 | case OP_VU0_MATCH_SUFFIX: | |
6292 | return match_vu0_suffix_operand (arg, operand, TRUE); | |
56d438b1 CF |
6293 | |
6294 | case OP_IMM_INDEX: | |
6295 | return match_imm_index_operand (arg, operand); | |
6296 | ||
6297 | case OP_REG_INDEX: | |
6298 | return match_reg_index_operand (arg, operand); | |
7361da2c AB |
6299 | |
6300 | case OP_SAME_RS_RT: | |
6301 | return match_same_rs_rt_operand (arg, operand); | |
6302 | ||
6303 | case OP_CHECK_PREV: | |
6304 | return match_check_prev_operand (arg, operand); | |
6305 | ||
6306 | case OP_NON_ZERO_REG: | |
6307 | return match_non_zero_reg_operand (arg, operand); | |
a1d78564 RS |
6308 | } |
6309 | abort (); | |
6310 | } | |
6311 | ||
6312 | /* ARG is the state after successfully matching an instruction. | |
6313 | Issue any queued-up warnings. */ | |
6314 | ||
6315 | static void | |
6316 | check_completed_insn (struct mips_arg_info *arg) | |
6317 | { | |
6318 | if (arg->seen_at) | |
6319 | { | |
6320 | if (AT == ATREG) | |
1661c76c | 6321 | as_warn (_("used $at without \".set noat\"")); |
a1d78564 | 6322 | else |
1661c76c | 6323 | as_warn (_("used $%u with \".set at=$%u\""), AT, AT); |
a1d78564 RS |
6324 | } |
6325 | } | |
a1d78564 | 6326 | |
85fcb30f RS |
6327 | /* Return true if modifying general-purpose register REG needs a delay. */ |
6328 | ||
6329 | static bfd_boolean | |
6330 | reg_needs_delay (unsigned int reg) | |
6331 | { | |
6332 | unsigned long prev_pinfo; | |
6333 | ||
6334 | prev_pinfo = history[0].insn_mo->pinfo; | |
6335 | if (!mips_opts.noreorder | |
67dc82bc | 6336 | && (((prev_pinfo & INSN_LOAD_MEMORY) && !gpr_interlocks) |
43885403 | 6337 | || ((prev_pinfo & INSN_LOAD_COPROC) && !cop_interlocks)) |
85fcb30f RS |
6338 | && (gpr_write_mask (&history[0]) & (1 << reg))) |
6339 | return TRUE; | |
6340 | ||
6341 | return FALSE; | |
6342 | } | |
6343 | ||
71400594 RS |
6344 | /* Classify an instruction according to the FIX_VR4120_* enumeration. |
6345 | Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected | |
6346 | by VR4120 errata. */ | |
4d7206a2 | 6347 | |
71400594 RS |
6348 | static unsigned int |
6349 | classify_vr4120_insn (const char *name) | |
252b5132 | 6350 | { |
71400594 RS |
6351 | if (strncmp (name, "macc", 4) == 0) |
6352 | return FIX_VR4120_MACC; | |
6353 | if (strncmp (name, "dmacc", 5) == 0) | |
6354 | return FIX_VR4120_DMACC; | |
6355 | if (strncmp (name, "mult", 4) == 0) | |
6356 | return FIX_VR4120_MULT; | |
6357 | if (strncmp (name, "dmult", 5) == 0) | |
6358 | return FIX_VR4120_DMULT; | |
6359 | if (strstr (name, "div")) | |
6360 | return FIX_VR4120_DIV; | |
6361 | if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) | |
6362 | return FIX_VR4120_MTHILO; | |
6363 | return NUM_FIX_VR4120_CLASSES; | |
6364 | } | |
252b5132 | 6365 | |
a8d14a88 CM |
6366 | #define INSN_ERET 0x42000018 |
6367 | #define INSN_DERET 0x4200001f | |
6368 | #define INSN_DMULT 0x1c | |
6369 | #define INSN_DMULTU 0x1d | |
ff239038 | 6370 | |
71400594 RS |
6371 | /* Return the number of instructions that must separate INSN1 and INSN2, |
6372 | where INSN1 is the earlier instruction. Return the worst-case value | |
6373 | for any INSN2 if INSN2 is null. */ | |
252b5132 | 6374 | |
71400594 RS |
6375 | static unsigned int |
6376 | insns_between (const struct mips_cl_insn *insn1, | |
6377 | const struct mips_cl_insn *insn2) | |
6378 | { | |
6379 | unsigned long pinfo1, pinfo2; | |
4c260379 | 6380 | unsigned int mask; |
71400594 | 6381 | |
85fcb30f RS |
6382 | /* If INFO2 is null, pessimistically assume that all flags are set for |
6383 | the second instruction. */ | |
71400594 RS |
6384 | pinfo1 = insn1->insn_mo->pinfo; |
6385 | pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; | |
252b5132 | 6386 | |
71400594 RS |
6387 | /* For most targets, write-after-read dependencies on the HI and LO |
6388 | registers must be separated by at least two instructions. */ | |
6389 | if (!hilo_interlocks) | |
252b5132 | 6390 | { |
71400594 RS |
6391 | if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) |
6392 | return 2; | |
6393 | if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) | |
6394 | return 2; | |
6395 | } | |
6396 | ||
6397 | /* If we're working around r7000 errata, there must be two instructions | |
6398 | between an mfhi or mflo and any instruction that uses the result. */ | |
6399 | if (mips_7000_hilo_fix | |
df58fc94 | 6400 | && !mips_opts.micromips |
71400594 | 6401 | && MF_HILO_INSN (pinfo1) |
85fcb30f | 6402 | && (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1)))) |
71400594 RS |
6403 | return 2; |
6404 | ||
ff239038 CM |
6405 | /* If we're working around 24K errata, one instruction is required |
6406 | if an ERET or DERET is followed by a branch instruction. */ | |
df58fc94 | 6407 | if (mips_fix_24k && !mips_opts.micromips) |
ff239038 CM |
6408 | { |
6409 | if (insn1->insn_opcode == INSN_ERET | |
6410 | || insn1->insn_opcode == INSN_DERET) | |
6411 | { | |
6412 | if (insn2 == NULL | |
6413 | || insn2->insn_opcode == INSN_ERET | |
6414 | || insn2->insn_opcode == INSN_DERET | |
11625dd8 | 6415 | || delayed_branch_p (insn2)) |
ff239038 CM |
6416 | return 1; |
6417 | } | |
6418 | } | |
6419 | ||
a8d14a88 CM |
6420 | /* If we're working around PMC RM7000 errata, there must be three |
6421 | nops between a dmult and a load instruction. */ | |
6422 | if (mips_fix_rm7000 && !mips_opts.micromips) | |
6423 | { | |
6424 | if ((insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULT | |
6425 | || (insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULTU) | |
6426 | { | |
6427 | if (pinfo2 & INSN_LOAD_MEMORY) | |
6428 | return 3; | |
6429 | } | |
6430 | } | |
6431 | ||
71400594 RS |
6432 | /* If working around VR4120 errata, check for combinations that need |
6433 | a single intervening instruction. */ | |
df58fc94 | 6434 | if (mips_fix_vr4120 && !mips_opts.micromips) |
71400594 RS |
6435 | { |
6436 | unsigned int class1, class2; | |
252b5132 | 6437 | |
71400594 RS |
6438 | class1 = classify_vr4120_insn (insn1->insn_mo->name); |
6439 | if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) | |
252b5132 | 6440 | { |
71400594 RS |
6441 | if (insn2 == NULL) |
6442 | return 1; | |
6443 | class2 = classify_vr4120_insn (insn2->insn_mo->name); | |
6444 | if (vr4120_conflicts[class1] & (1 << class2)) | |
6445 | return 1; | |
252b5132 | 6446 | } |
71400594 RS |
6447 | } |
6448 | ||
df58fc94 | 6449 | if (!HAVE_CODE_COMPRESSION) |
71400594 RS |
6450 | { |
6451 | /* Check for GPR or coprocessor load delays. All such delays | |
6452 | are on the RT register. */ | |
6453 | /* Itbl support may require additional care here. */ | |
67dc82bc | 6454 | if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY)) |
43885403 | 6455 | || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC))) |
252b5132 | 6456 | { |
85fcb30f | 6457 | if (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1))) |
71400594 RS |
6458 | return 1; |
6459 | } | |
6460 | ||
6461 | /* Check for generic coprocessor hazards. | |
6462 | ||
6463 | This case is not handled very well. There is no special | |
6464 | knowledge of CP0 handling, and the coprocessors other than | |
6465 | the floating point unit are not distinguished at all. */ | |
6466 | /* Itbl support may require additional care here. FIXME! | |
6467 | Need to modify this to include knowledge about | |
6468 | user specified delays! */ | |
43885403 | 6469 | else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE)) |
71400594 RS |
6470 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) |
6471 | { | |
6472 | /* Handle cases where INSN1 writes to a known general coprocessor | |
6473 | register. There must be a one instruction delay before INSN2 | |
6474 | if INSN2 reads that register, otherwise no delay is needed. */ | |
4c260379 RS |
6475 | mask = fpr_write_mask (insn1); |
6476 | if (mask != 0) | |
252b5132 | 6477 | { |
4c260379 | 6478 | if (!insn2 || (mask & fpr_read_mask (insn2)) != 0) |
71400594 | 6479 | return 1; |
252b5132 RH |
6480 | } |
6481 | else | |
6482 | { | |
71400594 RS |
6483 | /* Read-after-write dependencies on the control registers |
6484 | require a two-instruction gap. */ | |
6485 | if ((pinfo1 & INSN_WRITE_COND_CODE) | |
6486 | && (pinfo2 & INSN_READ_COND_CODE)) | |
6487 | return 2; | |
6488 | ||
6489 | /* We don't know exactly what INSN1 does. If INSN2 is | |
6490 | also a coprocessor instruction, assume there must be | |
6491 | a one instruction gap. */ | |
6492 | if (pinfo2 & INSN_COP) | |
6493 | return 1; | |
252b5132 RH |
6494 | } |
6495 | } | |
6b76fefe | 6496 | |
71400594 RS |
6497 | /* Check for read-after-write dependencies on the coprocessor |
6498 | control registers in cases where INSN1 does not need a general | |
6499 | coprocessor delay. This means that INSN1 is a floating point | |
6500 | comparison instruction. */ | |
6501 | /* Itbl support may require additional care here. */ | |
6502 | else if (!cop_interlocks | |
6503 | && (pinfo1 & INSN_WRITE_COND_CODE) | |
6504 | && (pinfo2 & INSN_READ_COND_CODE)) | |
6505 | return 1; | |
6506 | } | |
6b76fefe | 6507 | |
7361da2c AB |
6508 | /* Forbidden slots can not contain Control Transfer Instructions (CTIs) |
6509 | CTIs include all branches and jumps, nal, eret, eretnc, deret, wait | |
6510 | and pause. */ | |
6511 | if ((insn1->insn_mo->pinfo2 & INSN2_FORBIDDEN_SLOT) | |
6512 | && ((pinfo2 & INSN_NO_DELAY_SLOT) | |
6513 | || (insn2 && delayed_branch_p (insn2)))) | |
6514 | return 1; | |
6515 | ||
71400594 RS |
6516 | return 0; |
6517 | } | |
6b76fefe | 6518 | |
7d8e00cf RS |
6519 | /* Return the number of nops that would be needed to work around the |
6520 | VR4130 mflo/mfhi errata if instruction INSN immediately followed | |
932d1a1b RS |
6521 | the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards |
6522 | that are contained within the first IGNORE instructions of HIST. */ | |
7d8e00cf RS |
6523 | |
6524 | static int | |
932d1a1b | 6525 | nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist, |
7d8e00cf RS |
6526 | const struct mips_cl_insn *insn) |
6527 | { | |
4c260379 RS |
6528 | int i, j; |
6529 | unsigned int mask; | |
7d8e00cf RS |
6530 | |
6531 | /* Check if the instruction writes to HI or LO. MTHI and MTLO | |
6532 | are not affected by the errata. */ | |
6533 | if (insn != 0 | |
6534 | && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 | |
6535 | || strcmp (insn->insn_mo->name, "mtlo") == 0 | |
6536 | || strcmp (insn->insn_mo->name, "mthi") == 0)) | |
6537 | return 0; | |
6538 | ||
6539 | /* Search for the first MFLO or MFHI. */ | |
6540 | for (i = 0; i < MAX_VR4130_NOPS; i++) | |
91d6fa6a | 6541 | if (MF_HILO_INSN (hist[i].insn_mo->pinfo)) |
7d8e00cf RS |
6542 | { |
6543 | /* Extract the destination register. */ | |
4c260379 | 6544 | mask = gpr_write_mask (&hist[i]); |
7d8e00cf RS |
6545 | |
6546 | /* No nops are needed if INSN reads that register. */ | |
4c260379 | 6547 | if (insn != NULL && (gpr_read_mask (insn) & mask) != 0) |
7d8e00cf RS |
6548 | return 0; |
6549 | ||
6550 | /* ...or if any of the intervening instructions do. */ | |
6551 | for (j = 0; j < i; j++) | |
4c260379 | 6552 | if (gpr_read_mask (&hist[j]) & mask) |
7d8e00cf RS |
6553 | return 0; |
6554 | ||
932d1a1b RS |
6555 | if (i >= ignore) |
6556 | return MAX_VR4130_NOPS - i; | |
7d8e00cf RS |
6557 | } |
6558 | return 0; | |
6559 | } | |
6560 | ||
134c0c8b MR |
6561 | #define BASE_REG_EQ(INSN1, INSN2) \ |
6562 | ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \ | |
15be625d CM |
6563 | == (((INSN2) >> OP_SH_RS) & OP_MASK_RS)) |
6564 | ||
6565 | /* Return the minimum alignment for this store instruction. */ | |
6566 | ||
6567 | static int | |
6568 | fix_24k_align_to (const struct mips_opcode *mo) | |
6569 | { | |
6570 | if (strcmp (mo->name, "sh") == 0) | |
6571 | return 2; | |
6572 | ||
6573 | if (strcmp (mo->name, "swc1") == 0 | |
6574 | || strcmp (mo->name, "swc2") == 0 | |
6575 | || strcmp (mo->name, "sw") == 0 | |
6576 | || strcmp (mo->name, "sc") == 0 | |
6577 | || strcmp (mo->name, "s.s") == 0) | |
6578 | return 4; | |
6579 | ||
6580 | if (strcmp (mo->name, "sdc1") == 0 | |
6581 | || strcmp (mo->name, "sdc2") == 0 | |
6582 | || strcmp (mo->name, "s.d") == 0) | |
6583 | return 8; | |
6584 | ||
6585 | /* sb, swl, swr */ | |
6586 | return 1; | |
6587 | } | |
6588 | ||
6589 | struct fix_24k_store_info | |
6590 | { | |
6591 | /* Immediate offset, if any, for this store instruction. */ | |
6592 | short off; | |
6593 | /* Alignment required by this store instruction. */ | |
6594 | int align_to; | |
6595 | /* True for register offsets. */ | |
6596 | int register_offset; | |
6597 | }; | |
6598 | ||
6599 | /* Comparison function used by qsort. */ | |
6600 | ||
6601 | static int | |
6602 | fix_24k_sort (const void *a, const void *b) | |
6603 | { | |
6604 | const struct fix_24k_store_info *pos1 = a; | |
6605 | const struct fix_24k_store_info *pos2 = b; | |
6606 | ||
6607 | return (pos1->off - pos2->off); | |
6608 | } | |
6609 | ||
6610 | /* INSN is a store instruction. Try to record the store information | |
6611 | in STINFO. Return false if the information isn't known. */ | |
6612 | ||
6613 | static bfd_boolean | |
6614 | fix_24k_record_store_info (struct fix_24k_store_info *stinfo, | |
ab9794cf | 6615 | const struct mips_cl_insn *insn) |
15be625d CM |
6616 | { |
6617 | /* The instruction must have a known offset. */ | |
6618 | if (!insn->complete_p || !strstr (insn->insn_mo->args, "o(")) | |
6619 | return FALSE; | |
6620 | ||
6621 | stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE; | |
6622 | stinfo->align_to = fix_24k_align_to (insn->insn_mo); | |
6623 | return TRUE; | |
6624 | } | |
6625 | ||
932d1a1b RS |
6626 | /* Return the number of nops that would be needed to work around the 24k |
6627 | "lost data on stores during refill" errata if instruction INSN | |
6628 | immediately followed the 2 instructions described by HIST. | |
6629 | Ignore hazards that are contained within the first IGNORE | |
6630 | instructions of HIST. | |
6631 | ||
6632 | Problem: The FSB (fetch store buffer) acts as an intermediate buffer | |
6633 | for the data cache refills and store data. The following describes | |
6634 | the scenario where the store data could be lost. | |
6635 | ||
6636 | * A data cache miss, due to either a load or a store, causing fill | |
6637 | data to be supplied by the memory subsystem | |
6638 | * The first three doublewords of fill data are returned and written | |
6639 | into the cache | |
6640 | * A sequence of four stores occurs in consecutive cycles around the | |
6641 | final doubleword of the fill: | |
6642 | * Store A | |
6643 | * Store B | |
6644 | * Store C | |
6645 | * Zero, One or more instructions | |
6646 | * Store D | |
6647 | ||
6648 | The four stores A-D must be to different doublewords of the line that | |
6649 | is being filled. The fourth instruction in the sequence above permits | |
6650 | the fill of the final doubleword to be transferred from the FSB into | |
6651 | the cache. In the sequence above, the stores may be either integer | |
6652 | (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2, | |
6653 | swxc1, sdxc1, suxc1) stores, as long as the four stores are to | |
6654 | different doublewords on the line. If the floating point unit is | |
6655 | running in 1:2 mode, it is not possible to create the sequence above | |
6656 | using only floating point store instructions. | |
15be625d CM |
6657 | |
6658 | In this case, the cache line being filled is incorrectly marked | |
6659 | invalid, thereby losing the data from any store to the line that | |
6660 | occurs between the original miss and the completion of the five | |
6661 | cycle sequence shown above. | |
6662 | ||
932d1a1b | 6663 | The workarounds are: |
15be625d | 6664 | |
932d1a1b RS |
6665 | * Run the data cache in write-through mode. |
6666 | * Insert a non-store instruction between | |
6667 | Store A and Store B or Store B and Store C. */ | |
3739860c | 6668 | |
15be625d | 6669 | static int |
932d1a1b | 6670 | nops_for_24k (int ignore, const struct mips_cl_insn *hist, |
15be625d CM |
6671 | const struct mips_cl_insn *insn) |
6672 | { | |
6673 | struct fix_24k_store_info pos[3]; | |
6674 | int align, i, base_offset; | |
6675 | ||
932d1a1b RS |
6676 | if (ignore >= 2) |
6677 | return 0; | |
6678 | ||
ab9794cf RS |
6679 | /* If the previous instruction wasn't a store, there's nothing to |
6680 | worry about. */ | |
15be625d CM |
6681 | if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) |
6682 | return 0; | |
6683 | ||
ab9794cf RS |
6684 | /* If the instructions after the previous one are unknown, we have |
6685 | to assume the worst. */ | |
6686 | if (!insn) | |
15be625d CM |
6687 | return 1; |
6688 | ||
ab9794cf RS |
6689 | /* Check whether we are dealing with three consecutive stores. */ |
6690 | if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0 | |
6691 | || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) | |
15be625d CM |
6692 | return 0; |
6693 | ||
6694 | /* If we don't know the relationship between the store addresses, | |
6695 | assume the worst. */ | |
ab9794cf | 6696 | if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode) |
15be625d CM |
6697 | || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode)) |
6698 | return 1; | |
6699 | ||
6700 | if (!fix_24k_record_store_info (&pos[0], insn) | |
6701 | || !fix_24k_record_store_info (&pos[1], &hist[0]) | |
6702 | || !fix_24k_record_store_info (&pos[2], &hist[1])) | |
6703 | return 1; | |
6704 | ||
6705 | qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort); | |
6706 | ||
6707 | /* Pick a value of ALIGN and X such that all offsets are adjusted by | |
6708 | X bytes and such that the base register + X is known to be aligned | |
6709 | to align bytes. */ | |
6710 | ||
6711 | if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP) | |
6712 | align = 8; | |
6713 | else | |
6714 | { | |
6715 | align = pos[0].align_to; | |
6716 | base_offset = pos[0].off; | |
6717 | for (i = 1; i < 3; i++) | |
6718 | if (align < pos[i].align_to) | |
6719 | { | |
6720 | align = pos[i].align_to; | |
6721 | base_offset = pos[i].off; | |
6722 | } | |
6723 | for (i = 0; i < 3; i++) | |
6724 | pos[i].off -= base_offset; | |
6725 | } | |
6726 | ||
6727 | pos[0].off &= ~align + 1; | |
6728 | pos[1].off &= ~align + 1; | |
6729 | pos[2].off &= ~align + 1; | |
6730 | ||
6731 | /* If any two stores write to the same chunk, they also write to the | |
6732 | same doubleword. The offsets are still sorted at this point. */ | |
6733 | if (pos[0].off == pos[1].off || pos[1].off == pos[2].off) | |
6734 | return 0; | |
6735 | ||
6736 | /* A range of at least 9 bytes is needed for the stores to be in | |
6737 | non-overlapping doublewords. */ | |
6738 | if (pos[2].off - pos[0].off <= 8) | |
6739 | return 0; | |
6740 | ||
6741 | if (pos[2].off - pos[1].off >= 24 | |
6742 | || pos[1].off - pos[0].off >= 24 | |
6743 | || pos[2].off - pos[0].off >= 32) | |
6744 | return 0; | |
6745 | ||
6746 | return 1; | |
6747 | } | |
6748 | ||
71400594 | 6749 | /* Return the number of nops that would be needed if instruction INSN |
91d6fa6a | 6750 | immediately followed the MAX_NOPS instructions given by HIST, |
932d1a1b RS |
6751 | where HIST[0] is the most recent instruction. Ignore hazards |
6752 | between INSN and the first IGNORE instructions in HIST. | |
6753 | ||
6754 | If INSN is null, return the worse-case number of nops for any | |
6755 | instruction. */ | |
bdaaa2e1 | 6756 | |
71400594 | 6757 | static int |
932d1a1b | 6758 | nops_for_insn (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
6759 | const struct mips_cl_insn *insn) |
6760 | { | |
6761 | int i, nops, tmp_nops; | |
bdaaa2e1 | 6762 | |
71400594 | 6763 | nops = 0; |
932d1a1b | 6764 | for (i = ignore; i < MAX_DELAY_NOPS; i++) |
65b02341 | 6765 | { |
91d6fa6a | 6766 | tmp_nops = insns_between (hist + i, insn) - i; |
65b02341 RS |
6767 | if (tmp_nops > nops) |
6768 | nops = tmp_nops; | |
6769 | } | |
7d8e00cf | 6770 | |
df58fc94 | 6771 | if (mips_fix_vr4130 && !mips_opts.micromips) |
7d8e00cf | 6772 | { |
932d1a1b | 6773 | tmp_nops = nops_for_vr4130 (ignore, hist, insn); |
7d8e00cf RS |
6774 | if (tmp_nops > nops) |
6775 | nops = tmp_nops; | |
6776 | } | |
6777 | ||
df58fc94 | 6778 | if (mips_fix_24k && !mips_opts.micromips) |
15be625d | 6779 | { |
932d1a1b | 6780 | tmp_nops = nops_for_24k (ignore, hist, insn); |
15be625d CM |
6781 | if (tmp_nops > nops) |
6782 | nops = tmp_nops; | |
6783 | } | |
6784 | ||
71400594 RS |
6785 | return nops; |
6786 | } | |
252b5132 | 6787 | |
71400594 | 6788 | /* The variable arguments provide NUM_INSNS extra instructions that |
91d6fa6a | 6789 | might be added to HIST. Return the largest number of nops that |
932d1a1b RS |
6790 | would be needed after the extended sequence, ignoring hazards |
6791 | in the first IGNORE instructions. */ | |
252b5132 | 6792 | |
71400594 | 6793 | static int |
932d1a1b RS |
6794 | nops_for_sequence (int num_insns, int ignore, |
6795 | const struct mips_cl_insn *hist, ...) | |
71400594 RS |
6796 | { |
6797 | va_list args; | |
6798 | struct mips_cl_insn buffer[MAX_NOPS]; | |
6799 | struct mips_cl_insn *cursor; | |
6800 | int nops; | |
6801 | ||
91d6fa6a | 6802 | va_start (args, hist); |
71400594 | 6803 | cursor = buffer + num_insns; |
91d6fa6a | 6804 | memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor)); |
71400594 RS |
6805 | while (cursor > buffer) |
6806 | *--cursor = *va_arg (args, const struct mips_cl_insn *); | |
6807 | ||
932d1a1b | 6808 | nops = nops_for_insn (ignore, buffer, NULL); |
71400594 RS |
6809 | va_end (args); |
6810 | return nops; | |
6811 | } | |
252b5132 | 6812 | |
71400594 RS |
6813 | /* Like nops_for_insn, but if INSN is a branch, take into account the |
6814 | worst-case delay for the branch target. */ | |
252b5132 | 6815 | |
71400594 | 6816 | static int |
932d1a1b | 6817 | nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
6818 | const struct mips_cl_insn *insn) |
6819 | { | |
6820 | int nops, tmp_nops; | |
60b63b72 | 6821 | |
932d1a1b | 6822 | nops = nops_for_insn (ignore, hist, insn); |
11625dd8 | 6823 | if (delayed_branch_p (insn)) |
71400594 | 6824 | { |
932d1a1b | 6825 | tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0, |
14fe068b | 6826 | hist, insn, get_delay_slot_nop (insn)); |
71400594 RS |
6827 | if (tmp_nops > nops) |
6828 | nops = tmp_nops; | |
6829 | } | |
11625dd8 | 6830 | else if (compact_branch_p (insn)) |
71400594 | 6831 | { |
932d1a1b | 6832 | tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn); |
71400594 RS |
6833 | if (tmp_nops > nops) |
6834 | nops = tmp_nops; | |
6835 | } | |
6836 | return nops; | |
6837 | } | |
6838 | ||
c67a084a NC |
6839 | /* Fix NOP issue: Replace nops by "or at,at,zero". */ |
6840 | ||
6841 | static void | |
6842 | fix_loongson2f_nop (struct mips_cl_insn * ip) | |
6843 | { | |
df58fc94 | 6844 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
6845 | if (strcmp (ip->insn_mo->name, "nop") == 0) |
6846 | ip->insn_opcode = LOONGSON2F_NOP_INSN; | |
6847 | } | |
6848 | ||
6849 | /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region | |
6850 | jr target pc &= 'hffff_ffff_cfff_ffff. */ | |
6851 | ||
6852 | static void | |
6853 | fix_loongson2f_jump (struct mips_cl_insn * ip) | |
6854 | { | |
df58fc94 | 6855 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
6856 | if (strcmp (ip->insn_mo->name, "j") == 0 |
6857 | || strcmp (ip->insn_mo->name, "jr") == 0 | |
6858 | || strcmp (ip->insn_mo->name, "jalr") == 0) | |
6859 | { | |
6860 | int sreg; | |
6861 | expressionS ep; | |
6862 | ||
6863 | if (! mips_opts.at) | |
6864 | return; | |
6865 | ||
df58fc94 | 6866 | sreg = EXTRACT_OPERAND (0, RS, *ip); |
c67a084a NC |
6867 | if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG) |
6868 | return; | |
6869 | ||
6870 | ep.X_op = O_constant; | |
6871 | ep.X_add_number = 0xcfff0000; | |
6872 | macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16); | |
6873 | ep.X_add_number = 0xffff; | |
6874 | macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16); | |
6875 | macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG); | |
6876 | } | |
6877 | } | |
6878 | ||
6879 | static void | |
6880 | fix_loongson2f (struct mips_cl_insn * ip) | |
6881 | { | |
6882 | if (mips_fix_loongson2f_nop) | |
6883 | fix_loongson2f_nop (ip); | |
6884 | ||
6885 | if (mips_fix_loongson2f_jump) | |
6886 | fix_loongson2f_jump (ip); | |
6887 | } | |
6888 | ||
6f2117ba PH |
6889 | /* Fix loongson3 llsc errata: Insert sync before ll/lld. */ |
6890 | ||
6891 | static void | |
6892 | fix_loongson3_llsc (struct mips_cl_insn * ip) | |
6893 | { | |
6894 | gas_assert (!HAVE_CODE_COMPRESSION); | |
6895 | ||
6896 | /* If is an local label and the insn is not sync, | |
6897 | look forward that whether an branch between ll/sc jump to here | |
6898 | if so, insert a sync. */ | |
6899 | if (seg_info (now_seg)->label_list | |
6900 | && S_IS_LOCAL (seg_info (now_seg)->label_list->label) | |
6901 | && (strcmp (ip->insn_mo->name, "sync") != 0)) | |
6902 | { | |
6903 | const char *label_name = S_GET_NAME (seg_info (now_seg)->label_list->label); | |
6904 | unsigned long lookback = ARRAY_SIZE (history); | |
6905 | unsigned long i; | |
6906 | ||
6907 | for (i = 0; i < lookback; i++) | |
6908 | { | |
6909 | if (streq (history[i].insn_mo->name, "ll") | |
6910 | || streq (history[i].insn_mo->name, "lld")) | |
6911 | break; | |
6912 | ||
6913 | if (streq (history[i].insn_mo->name, "sc") | |
6914 | || streq (history[i].insn_mo->name, "scd")) | |
6915 | { | |
6916 | unsigned long j; | |
6917 | ||
6918 | for (j = i + 1; j < lookback; j++) | |
6919 | { | |
6920 | if (streq (history[i].insn_mo->name, "ll") | |
6921 | || streq (history[i].insn_mo->name, "lld")) | |
6922 | break; | |
6923 | ||
6924 | if (delayed_branch_p (&history[j])) | |
6925 | { | |
6926 | if (streq (history[j].target, label_name)) | |
6927 | { | |
6928 | add_fixed_insn (&sync_insn); | |
6929 | insert_into_history (0, 1, &sync_insn); | |
6930 | i = lookback; | |
6931 | break; | |
6932 | } | |
6933 | } | |
6934 | } | |
6935 | } | |
6936 | } | |
6937 | } | |
6938 | /* If we find a sc, we look forward to look for an branch insn, | |
6939 | and see whether it jump back and out of ll/sc. */ | |
6940 | else if (streq(ip->insn_mo->name, "sc") || streq(ip->insn_mo->name, "scd")) | |
6941 | { | |
6942 | unsigned long lookback = ARRAY_SIZE (history) - 1; | |
6943 | unsigned long i; | |
6944 | ||
6945 | for (i = 0; i < lookback; i++) | |
6946 | { | |
6947 | if (streq (history[i].insn_mo->name, "ll") | |
6948 | || streq (history[i].insn_mo->name, "lld")) | |
6949 | break; | |
6950 | ||
6951 | if (delayed_branch_p (&history[i])) | |
6952 | { | |
6953 | unsigned long j; | |
6954 | ||
6955 | for (j = i + 1; j < lookback; j++) | |
6956 | { | |
6957 | if (streq (history[j].insn_mo->name, "ll") | |
6958 | || streq (history[i].insn_mo->name, "lld")) | |
6959 | break; | |
6960 | } | |
6961 | ||
6962 | for (; j < lookback; j++) | |
6963 | { | |
6964 | if (history[j].label[0] != '\0' | |
6965 | && streq (history[j].label, history[i].target) | |
6966 | && strcmp (history[j+1].insn_mo->name, "sync") != 0) | |
6967 | { | |
6968 | add_fixed_insn (&sync_insn); | |
6969 | insert_into_history (++j, 1, &sync_insn); | |
6970 | } | |
6971 | } | |
6972 | } | |
6973 | } | |
6974 | } | |
6975 | ||
6976 | /* Skip if there is a sync before ll/lld. */ | |
6977 | if ((strcmp (ip->insn_mo->name, "ll") == 0 | |
6978 | || strcmp (ip->insn_mo->name, "lld") == 0) | |
6979 | && (strcmp (history[0].insn_mo->name, "sync") != 0)) | |
6980 | { | |
6981 | add_fixed_insn (&sync_insn); | |
6982 | insert_into_history (0, 1, &sync_insn); | |
6983 | } | |
6984 | } | |
6985 | ||
a4e06468 RS |
6986 | /* IP is a branch that has a delay slot, and we need to fill it |
6987 | automatically. Return true if we can do that by swapping IP | |
e407c74b NC |
6988 | with the previous instruction. |
6989 | ADDRESS_EXPR is an operand of the instruction to be used with | |
6990 | RELOC_TYPE. */ | |
a4e06468 RS |
6991 | |
6992 | static bfd_boolean | |
e407c74b | 6993 | can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr, |
26545944 | 6994 | bfd_reloc_code_real_type *reloc_type) |
a4e06468 | 6995 | { |
2b0c8b40 | 6996 | unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2; |
a4e06468 | 6997 | unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write; |
9d5de888 | 6998 | unsigned int fpr_read, prev_fpr_write; |
a4e06468 RS |
6999 | |
7000 | /* -O2 and above is required for this optimization. */ | |
7001 | if (mips_optimize < 2) | |
7002 | return FALSE; | |
7003 | ||
7004 | /* If we have seen .set volatile or .set nomove, don't optimize. */ | |
7005 | if (mips_opts.nomove) | |
7006 | return FALSE; | |
7007 | ||
7008 | /* We can't swap if the previous instruction's position is fixed. */ | |
7009 | if (history[0].fixed_p) | |
7010 | return FALSE; | |
7011 | ||
7012 | /* If the previous previous insn was in a .set noreorder, we can't | |
7013 | swap. Actually, the MIPS assembler will swap in this situation. | |
7014 | However, gcc configured -with-gnu-as will generate code like | |
7015 | ||
7016 | .set noreorder | |
7017 | lw $4,XXX | |
7018 | .set reorder | |
7019 | INSN | |
7020 | bne $4,$0,foo | |
7021 | ||
7022 | in which we can not swap the bne and INSN. If gcc is not configured | |
7023 | -with-gnu-as, it does not output the .set pseudo-ops. */ | |
7024 | if (history[1].noreorder_p) | |
7025 | return FALSE; | |
7026 | ||
87333bb7 MR |
7027 | /* If the previous instruction had a fixup in mips16 mode, we can not swap. |
7028 | This means that the previous instruction was a 4-byte one anyhow. */ | |
a4e06468 RS |
7029 | if (mips_opts.mips16 && history[0].fixp[0]) |
7030 | return FALSE; | |
7031 | ||
7032 | /* If the branch is itself the target of a branch, we can not swap. | |
7033 | We cheat on this; all we check for is whether there is a label on | |
7034 | this instruction. If there are any branches to anything other than | |
7035 | a label, users must use .set noreorder. */ | |
7036 | if (seg_info (now_seg)->label_list) | |
7037 | return FALSE; | |
7038 | ||
7039 | /* If the previous instruction is in a variant frag other than this | |
2309ddf2 | 7040 | branch's one, we cannot do the swap. This does not apply to |
9301f9c3 MR |
7041 | MIPS16 code, which uses variant frags for different purposes. */ |
7042 | if (!mips_opts.mips16 | |
a4e06468 RS |
7043 | && history[0].frag |
7044 | && history[0].frag->fr_type == rs_machine_dependent) | |
7045 | return FALSE; | |
7046 | ||
bcd530a7 RS |
7047 | /* We do not swap with instructions that cannot architecturally |
7048 | be placed in a branch delay slot, such as SYNC or ERET. We | |
7049 | also refrain from swapping with a trap instruction, since it | |
7050 | complicates trap handlers to have the trap instruction be in | |
7051 | a delay slot. */ | |
a4e06468 | 7052 | prev_pinfo = history[0].insn_mo->pinfo; |
bcd530a7 | 7053 | if (prev_pinfo & INSN_NO_DELAY_SLOT) |
a4e06468 RS |
7054 | return FALSE; |
7055 | ||
7056 | /* Check for conflicts between the branch and the instructions | |
7057 | before the candidate delay slot. */ | |
7058 | if (nops_for_insn (0, history + 1, ip) > 0) | |
7059 | return FALSE; | |
7060 | ||
7061 | /* Check for conflicts between the swapped sequence and the | |
7062 | target of the branch. */ | |
7063 | if (nops_for_sequence (2, 0, history + 1, ip, history) > 0) | |
7064 | return FALSE; | |
7065 | ||
7066 | /* If the branch reads a register that the previous | |
7067 | instruction sets, we can not swap. */ | |
7068 | gpr_read = gpr_read_mask (ip); | |
7069 | prev_gpr_write = gpr_write_mask (&history[0]); | |
7070 | if (gpr_read & prev_gpr_write) | |
7071 | return FALSE; | |
7072 | ||
9d5de888 CF |
7073 | fpr_read = fpr_read_mask (ip); |
7074 | prev_fpr_write = fpr_write_mask (&history[0]); | |
7075 | if (fpr_read & prev_fpr_write) | |
7076 | return FALSE; | |
7077 | ||
a4e06468 RS |
7078 | /* If the branch writes a register that the previous |
7079 | instruction sets, we can not swap. */ | |
7080 | gpr_write = gpr_write_mask (ip); | |
7081 | if (gpr_write & prev_gpr_write) | |
7082 | return FALSE; | |
7083 | ||
7084 | /* If the branch writes a register that the previous | |
7085 | instruction reads, we can not swap. */ | |
7086 | prev_gpr_read = gpr_read_mask (&history[0]); | |
7087 | if (gpr_write & prev_gpr_read) | |
7088 | return FALSE; | |
7089 | ||
7090 | /* If one instruction sets a condition code and the | |
7091 | other one uses a condition code, we can not swap. */ | |
7092 | pinfo = ip->insn_mo->pinfo; | |
7093 | if ((pinfo & INSN_READ_COND_CODE) | |
7094 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
7095 | return FALSE; | |
7096 | if ((pinfo & INSN_WRITE_COND_CODE) | |
7097 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
7098 | return FALSE; | |
7099 | ||
7100 | /* If the previous instruction uses the PC, we can not swap. */ | |
2b0c8b40 | 7101 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
26545944 | 7102 | if (prev_pinfo2 & INSN2_READ_PC) |
2b0c8b40 | 7103 | return FALSE; |
a4e06468 | 7104 | |
df58fc94 RS |
7105 | /* If the previous instruction has an incorrect size for a fixed |
7106 | branch delay slot in microMIPS mode, we cannot swap. */ | |
2309ddf2 MR |
7107 | pinfo2 = ip->insn_mo->pinfo2; |
7108 | if (mips_opts.micromips | |
7109 | && (pinfo2 & INSN2_BRANCH_DELAY_16BIT) | |
7110 | && insn_length (history) != 2) | |
7111 | return FALSE; | |
7112 | if (mips_opts.micromips | |
7113 | && (pinfo2 & INSN2_BRANCH_DELAY_32BIT) | |
7114 | && insn_length (history) != 4) | |
7115 | return FALSE; | |
7116 | ||
33d64ca5 FN |
7117 | /* On the R5900 short loops need to be fixed by inserting a NOP in the |
7118 | branch delay slot. | |
7119 | ||
7120 | The short loop bug under certain conditions causes loops to execute | |
7121 | only once or twice. We must ensure that the assembler never | |
7122 | generates loops that satisfy all of the following conditions: | |
7123 | ||
7124 | - a loop consists of less than or equal to six instructions | |
7125 | (including the branch delay slot); | |
7126 | - a loop contains only one conditional branch instruction at the end | |
7127 | of the loop; | |
7128 | - a loop does not contain any other branch or jump instructions; | |
7129 | - a branch delay slot of the loop is not NOP (EE 2.9 or later). | |
7130 | ||
7131 | We need to do this because of a hardware bug in the R5900 chip. */ | |
27c634e0 | 7132 | if (mips_fix_r5900 |
e407c74b NC |
7133 | /* Check if instruction has a parameter, ignore "j $31". */ |
7134 | && (address_expr != NULL) | |
7135 | /* Parameter must be 16 bit. */ | |
7136 | && (*reloc_type == BFD_RELOC_16_PCREL_S2) | |
7137 | /* Branch to same segment. */ | |
41065f5e | 7138 | && (S_GET_SEGMENT (address_expr->X_add_symbol) == now_seg) |
e407c74b | 7139 | /* Branch to same code fragment. */ |
41065f5e | 7140 | && (symbol_get_frag (address_expr->X_add_symbol) == frag_now) |
e407c74b | 7141 | /* Can only calculate branch offset if value is known. */ |
41065f5e | 7142 | && symbol_constant_p (address_expr->X_add_symbol) |
e407c74b NC |
7143 | /* Check if branch is really conditional. */ |
7144 | && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
7145 | || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
7146 | || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
7147 | { | |
7148 | int distance; | |
33d64ca5 FN |
7149 | /* Check if loop is shorter than or equal to 6 instructions |
7150 | including branch and delay slot. */ | |
41065f5e | 7151 | distance = frag_now_fix () - S_GET_VALUE (address_expr->X_add_symbol); |
e407c74b NC |
7152 | if (distance <= 20) |
7153 | { | |
7154 | int i; | |
7155 | int rv; | |
7156 | ||
7157 | rv = FALSE; | |
7158 | /* When the loop includes branches or jumps, | |
7159 | it is not a short loop. */ | |
7160 | for (i = 0; i < (distance / 4); i++) | |
7161 | { | |
7162 | if ((history[i].cleared_p) | |
41065f5e | 7163 | || delayed_branch_p (&history[i])) |
e407c74b NC |
7164 | { |
7165 | rv = TRUE; | |
7166 | break; | |
7167 | } | |
7168 | } | |
535b785f | 7169 | if (!rv) |
e407c74b NC |
7170 | { |
7171 | /* Insert nop after branch to fix short loop. */ | |
7172 | return FALSE; | |
7173 | } | |
7174 | } | |
7175 | } | |
7176 | ||
a4e06468 RS |
7177 | return TRUE; |
7178 | } | |
7179 | ||
e407c74b NC |
7180 | /* Decide how we should add IP to the instruction stream. |
7181 | ADDRESS_EXPR is an operand of the instruction to be used with | |
7182 | RELOC_TYPE. */ | |
a4e06468 RS |
7183 | |
7184 | static enum append_method | |
e407c74b | 7185 | get_append_method (struct mips_cl_insn *ip, expressionS *address_expr, |
26545944 | 7186 | bfd_reloc_code_real_type *reloc_type) |
a4e06468 | 7187 | { |
a4e06468 RS |
7188 | /* The relaxed version of a macro sequence must be inherently |
7189 | hazard-free. */ | |
7190 | if (mips_relax.sequence == 2) | |
7191 | return APPEND_ADD; | |
7192 | ||
3b821a28 | 7193 | /* We must not dabble with instructions in a ".set noreorder" block. */ |
a4e06468 RS |
7194 | if (mips_opts.noreorder) |
7195 | return APPEND_ADD; | |
7196 | ||
7197 | /* Otherwise, it's our responsibility to fill branch delay slots. */ | |
11625dd8 | 7198 | if (delayed_branch_p (ip)) |
a4e06468 | 7199 | { |
e407c74b NC |
7200 | if (!branch_likely_p (ip) |
7201 | && can_swap_branch_p (ip, address_expr, reloc_type)) | |
a4e06468 RS |
7202 | return APPEND_SWAP; |
7203 | ||
7204 | if (mips_opts.mips16 | |
7205 | && ISA_SUPPORTS_MIPS16E | |
fc76e730 | 7206 | && gpr_read_mask (ip) != 0) |
a4e06468 RS |
7207 | return APPEND_ADD_COMPACT; |
7208 | ||
7bd374a4 MR |
7209 | if (mips_opts.micromips |
7210 | && ((ip->insn_opcode & 0xffe0) == 0x4580 | |
7211 | || (!forced_insn_length | |
7212 | && ((ip->insn_opcode & 0xfc00) == 0xcc00 | |
7213 | || (ip->insn_opcode & 0xdc00) == 0x8c00)) | |
7214 | || (ip->insn_opcode & 0xdfe00000) == 0x94000000 | |
7215 | || (ip->insn_opcode & 0xdc1f0000) == 0x94000000)) | |
7216 | return APPEND_ADD_COMPACT; | |
7217 | ||
a4e06468 RS |
7218 | return APPEND_ADD_WITH_NOP; |
7219 | } | |
7220 | ||
a4e06468 RS |
7221 | return APPEND_ADD; |
7222 | } | |
7223 | ||
7bd374a4 MR |
7224 | /* IP is an instruction whose opcode we have just changed, END points |
7225 | to the end of the opcode table processed. Point IP->insn_mo to the | |
7226 | new opcode's definition. */ | |
ceb94aa5 RS |
7227 | |
7228 | static void | |
7bd374a4 | 7229 | find_altered_opcode (struct mips_cl_insn *ip, const struct mips_opcode *end) |
ceb94aa5 | 7230 | { |
7bd374a4 | 7231 | const struct mips_opcode *mo; |
ceb94aa5 | 7232 | |
ceb94aa5 | 7233 | for (mo = ip->insn_mo; mo < end; mo++) |
7bd374a4 MR |
7234 | if (mo->pinfo != INSN_MACRO |
7235 | && (ip->insn_opcode & mo->mask) == mo->match) | |
ceb94aa5 RS |
7236 | { |
7237 | ip->insn_mo = mo; | |
7238 | return; | |
7239 | } | |
7240 | abort (); | |
7241 | } | |
7242 | ||
7bd374a4 MR |
7243 | /* IP is a MIPS16 instruction whose opcode we have just changed. |
7244 | Point IP->insn_mo to the new opcode's definition. */ | |
7245 | ||
7246 | static void | |
7247 | find_altered_mips16_opcode (struct mips_cl_insn *ip) | |
7248 | { | |
7249 | find_altered_opcode (ip, &mips16_opcodes[bfd_mips16_num_opcodes]); | |
7250 | } | |
7251 | ||
7252 | /* IP is a microMIPS instruction whose opcode we have just changed. | |
7253 | Point IP->insn_mo to the new opcode's definition. */ | |
7254 | ||
7255 | static void | |
7256 | find_altered_micromips_opcode (struct mips_cl_insn *ip) | |
7257 | { | |
7258 | find_altered_opcode (ip, µmips_opcodes[bfd_micromips_num_opcodes]); | |
7259 | } | |
7260 | ||
df58fc94 RS |
7261 | /* For microMIPS macros, we need to generate a local number label |
7262 | as the target of branches. */ | |
7263 | #define MICROMIPS_LABEL_CHAR '\037' | |
7264 | static unsigned long micromips_target_label; | |
7265 | static char micromips_target_name[32]; | |
7266 | ||
7267 | static char * | |
7268 | micromips_label_name (void) | |
7269 | { | |
7270 | char *p = micromips_target_name; | |
7271 | char symbol_name_temporary[24]; | |
7272 | unsigned long l; | |
7273 | int i; | |
7274 | ||
7275 | if (*p) | |
7276 | return p; | |
7277 | ||
7278 | i = 0; | |
7279 | l = micromips_target_label; | |
7280 | #ifdef LOCAL_LABEL_PREFIX | |
7281 | *p++ = LOCAL_LABEL_PREFIX; | |
7282 | #endif | |
7283 | *p++ = 'L'; | |
7284 | *p++ = MICROMIPS_LABEL_CHAR; | |
7285 | do | |
7286 | { | |
7287 | symbol_name_temporary[i++] = l % 10 + '0'; | |
7288 | l /= 10; | |
7289 | } | |
7290 | while (l != 0); | |
7291 | while (i > 0) | |
7292 | *p++ = symbol_name_temporary[--i]; | |
7293 | *p = '\0'; | |
7294 | ||
7295 | return micromips_target_name; | |
7296 | } | |
7297 | ||
7298 | static void | |
7299 | micromips_label_expr (expressionS *label_expr) | |
7300 | { | |
7301 | label_expr->X_op = O_symbol; | |
7302 | label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ()); | |
7303 | label_expr->X_add_number = 0; | |
7304 | } | |
7305 | ||
7306 | static void | |
7307 | micromips_label_inc (void) | |
7308 | { | |
7309 | micromips_target_label++; | |
7310 | *micromips_target_name = '\0'; | |
7311 | } | |
7312 | ||
7313 | static void | |
7314 | micromips_add_label (void) | |
7315 | { | |
7316 | symbolS *s; | |
7317 | ||
7318 | s = colon (micromips_label_name ()); | |
7319 | micromips_label_inc (); | |
f3ded42a | 7320 | S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s))); |
df58fc94 RS |
7321 | } |
7322 | ||
7323 | /* If assembling microMIPS code, then return the microMIPS reloc | |
7324 | corresponding to the requested one if any. Otherwise return | |
7325 | the reloc unchanged. */ | |
7326 | ||
7327 | static bfd_reloc_code_real_type | |
7328 | micromips_map_reloc (bfd_reloc_code_real_type reloc) | |
7329 | { | |
7330 | static const bfd_reloc_code_real_type relocs[][2] = | |
7331 | { | |
7332 | /* Keep sorted incrementally by the left-hand key. */ | |
7333 | { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 }, | |
7334 | { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 }, | |
7335 | { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP }, | |
7336 | { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 }, | |
7337 | { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S }, | |
7338 | { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 }, | |
7339 | { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL }, | |
7340 | { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 }, | |
7341 | { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 }, | |
7342 | { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 }, | |
7343 | { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 }, | |
7344 | { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 }, | |
7345 | { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 }, | |
7346 | { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB }, | |
7347 | { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE }, | |
7348 | { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST }, | |
7349 | { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP }, | |
7350 | { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST }, | |
7351 | { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER }, | |
7352 | { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP }, | |
7353 | { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD }, | |
7354 | { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM }, | |
7355 | { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 }, | |
7356 | { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 }, | |
7357 | { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL }, | |
7358 | { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 }, | |
7359 | { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 } | |
7360 | }; | |
7361 | bfd_reloc_code_real_type r; | |
7362 | size_t i; | |
7363 | ||
7364 | if (!mips_opts.micromips) | |
7365 | return reloc; | |
7366 | for (i = 0; i < ARRAY_SIZE (relocs); i++) | |
7367 | { | |
7368 | r = relocs[i][0]; | |
7369 | if (r > reloc) | |
7370 | return reloc; | |
7371 | if (r == reloc) | |
7372 | return relocs[i][1]; | |
7373 | } | |
7374 | return reloc; | |
7375 | } | |
7376 | ||
b886a2ab RS |
7377 | /* Try to resolve relocation RELOC against constant OPERAND at assembly time. |
7378 | Return true on success, storing the resolved value in RESULT. */ | |
7379 | ||
7380 | static bfd_boolean | |
7381 | calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand, | |
7382 | offsetT *result) | |
7383 | { | |
7384 | switch (reloc) | |
7385 | { | |
7386 | case BFD_RELOC_MIPS_HIGHEST: | |
7387 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
7388 | *result = ((operand + 0x800080008000ull) >> 48) & 0xffff; | |
7389 | return TRUE; | |
7390 | ||
7391 | case BFD_RELOC_MIPS_HIGHER: | |
7392 | case BFD_RELOC_MICROMIPS_HIGHER: | |
7393 | *result = ((operand + 0x80008000ull) >> 32) & 0xffff; | |
7394 | return TRUE; | |
7395 | ||
7396 | case BFD_RELOC_HI16_S: | |
41947d9e | 7397 | case BFD_RELOC_HI16_S_PCREL: |
b886a2ab RS |
7398 | case BFD_RELOC_MICROMIPS_HI16_S: |
7399 | case BFD_RELOC_MIPS16_HI16_S: | |
7400 | *result = ((operand + 0x8000) >> 16) & 0xffff; | |
7401 | return TRUE; | |
7402 | ||
7403 | case BFD_RELOC_HI16: | |
7404 | case BFD_RELOC_MICROMIPS_HI16: | |
7405 | case BFD_RELOC_MIPS16_HI16: | |
7406 | *result = (operand >> 16) & 0xffff; | |
7407 | return TRUE; | |
7408 | ||
7409 | case BFD_RELOC_LO16: | |
41947d9e | 7410 | case BFD_RELOC_LO16_PCREL: |
b886a2ab RS |
7411 | case BFD_RELOC_MICROMIPS_LO16: |
7412 | case BFD_RELOC_MIPS16_LO16: | |
7413 | *result = operand & 0xffff; | |
7414 | return TRUE; | |
7415 | ||
7416 | case BFD_RELOC_UNUSED: | |
7417 | *result = operand; | |
7418 | return TRUE; | |
7419 | ||
7420 | default: | |
7421 | return FALSE; | |
7422 | } | |
7423 | } | |
7424 | ||
71400594 RS |
7425 | /* Output an instruction. IP is the instruction information. |
7426 | ADDRESS_EXPR is an operand of the instruction to be used with | |
df58fc94 RS |
7427 | RELOC_TYPE. EXPANSIONP is true if the instruction is part of |
7428 | a macro expansion. */ | |
71400594 RS |
7429 | |
7430 | static void | |
7431 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
df58fc94 | 7432 | bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp) |
71400594 | 7433 | { |
14fe068b | 7434 | unsigned long prev_pinfo2, pinfo; |
71400594 | 7435 | bfd_boolean relaxed_branch = FALSE; |
a4e06468 | 7436 | enum append_method method; |
2309ddf2 | 7437 | bfd_boolean relax32; |
2b0c8b40 | 7438 | int branch_disp; |
71400594 | 7439 | |
2309ddf2 | 7440 | if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION) |
c67a084a NC |
7441 | fix_loongson2f (ip); |
7442 | ||
6f2117ba PH |
7443 | ip->target[0] = '\0'; |
7444 | if (offset_expr.X_op == O_symbol) | |
7445 | strncpy (ip->target, S_GET_NAME (offset_expr.X_add_symbol), 15); | |
7446 | ip->label[0] = '\0'; | |
7447 | if (seg_info (now_seg)->label_list) | |
7448 | strncpy (ip->label, S_GET_NAME (seg_info (now_seg)->label_list->label), 15); | |
7449 | if (mips_fix_loongson3_llsc && !HAVE_CODE_COMPRESSION) | |
7450 | fix_loongson3_llsc (ip); | |
7451 | ||
738f4d98 | 7452 | file_ase_mips16 |= mips_opts.mips16; |
df58fc94 | 7453 | file_ase_micromips |= mips_opts.micromips; |
738f4d98 | 7454 | |
df58fc94 | 7455 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
71400594 | 7456 | pinfo = ip->insn_mo->pinfo; |
df58fc94 | 7457 | |
7bd374a4 MR |
7458 | /* Don't raise alarm about `nods' frags as they'll fill in the right |
7459 | kind of nop in relaxation if required. */ | |
df58fc94 RS |
7460 | if (mips_opts.micromips |
7461 | && !expansionp | |
7bd374a4 MR |
7462 | && !(history[0].frag |
7463 | && history[0].frag->fr_type == rs_machine_dependent | |
7464 | && RELAX_MICROMIPS_P (history[0].frag->fr_subtype) | |
7465 | && RELAX_MICROMIPS_NODS (history[0].frag->fr_subtype)) | |
df58fc94 RS |
7466 | && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 |
7467 | && micromips_insn_length (ip->insn_mo) != 2) | |
7468 | || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 | |
7469 | && micromips_insn_length (ip->insn_mo) != 4))) | |
1661c76c | 7470 | as_warn (_("wrong size instruction in a %u-bit branch delay slot"), |
df58fc94 | 7471 | (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32); |
71400594 | 7472 | |
15be625d CM |
7473 | if (address_expr == NULL) |
7474 | ip->complete_p = 1; | |
b886a2ab RS |
7475 | else if (reloc_type[0] <= BFD_RELOC_UNUSED |
7476 | && reloc_type[1] == BFD_RELOC_UNUSED | |
7477 | && reloc_type[2] == BFD_RELOC_UNUSED | |
15be625d CM |
7478 | && address_expr->X_op == O_constant) |
7479 | { | |
15be625d CM |
7480 | switch (*reloc_type) |
7481 | { | |
15be625d | 7482 | case BFD_RELOC_MIPS_JMP: |
df58fc94 RS |
7483 | { |
7484 | int shift; | |
7485 | ||
17c6c9d9 MR |
7486 | /* Shift is 2, unusually, for microMIPS JALX. */ |
7487 | shift = (mips_opts.micromips | |
7488 | && strcmp (ip->insn_mo->name, "jalx") != 0) ? 1 : 2; | |
df58fc94 RS |
7489 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) |
7490 | as_bad (_("jump to misaligned address (0x%lx)"), | |
7491 | (unsigned long) address_expr->X_add_number); | |
7492 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
7493 | & 0x3ffffff); | |
335574df | 7494 | ip->complete_p = 1; |
df58fc94 | 7495 | } |
15be625d CM |
7496 | break; |
7497 | ||
7498 | case BFD_RELOC_MIPS16_JMP: | |
7499 | if ((address_expr->X_add_number & 3) != 0) | |
7500 | as_bad (_("jump to misaligned address (0x%lx)"), | |
7501 | (unsigned long) address_expr->X_add_number); | |
7502 | ip->insn_opcode |= | |
7503 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
7504 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
7505 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
335574df | 7506 | ip->complete_p = 1; |
15be625d CM |
7507 | break; |
7508 | ||
7509 | case BFD_RELOC_16_PCREL_S2: | |
df58fc94 RS |
7510 | { |
7511 | int shift; | |
7512 | ||
7513 | shift = mips_opts.micromips ? 1 : 2; | |
7514 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
7515 | as_bad (_("branch to misaligned address (0x%lx)"), | |
7516 | (unsigned long) address_expr->X_add_number); | |
7517 | if (!mips_relax_branch) | |
7518 | { | |
7519 | if ((address_expr->X_add_number + (1 << (shift + 15))) | |
7520 | & ~((1 << (shift + 16)) - 1)) | |
7521 | as_bad (_("branch address range overflow (0x%lx)"), | |
7522 | (unsigned long) address_expr->X_add_number); | |
7523 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
7524 | & 0xffff); | |
7525 | } | |
df58fc94 | 7526 | } |
15be625d CM |
7527 | break; |
7528 | ||
7361da2c AB |
7529 | case BFD_RELOC_MIPS_21_PCREL_S2: |
7530 | { | |
7531 | int shift; | |
7532 | ||
7533 | shift = 2; | |
7534 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
7535 | as_bad (_("branch to misaligned address (0x%lx)"), | |
7536 | (unsigned long) address_expr->X_add_number); | |
7537 | if ((address_expr->X_add_number + (1 << (shift + 20))) | |
7538 | & ~((1 << (shift + 21)) - 1)) | |
7539 | as_bad (_("branch address range overflow (0x%lx)"), | |
7540 | (unsigned long) address_expr->X_add_number); | |
7541 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
7542 | & 0x1fffff); | |
7543 | } | |
7544 | break; | |
7545 | ||
7546 | case BFD_RELOC_MIPS_26_PCREL_S2: | |
7547 | { | |
7548 | int shift; | |
7549 | ||
7550 | shift = 2; | |
7551 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
7552 | as_bad (_("branch to misaligned address (0x%lx)"), | |
7553 | (unsigned long) address_expr->X_add_number); | |
7554 | if ((address_expr->X_add_number + (1 << (shift + 25))) | |
7555 | & ~((1 << (shift + 26)) - 1)) | |
7556 | as_bad (_("branch address range overflow (0x%lx)"), | |
7557 | (unsigned long) address_expr->X_add_number); | |
7558 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
7559 | & 0x3ffffff); | |
7560 | } | |
7561 | break; | |
7562 | ||
15be625d | 7563 | default: |
b886a2ab RS |
7564 | { |
7565 | offsetT value; | |
7566 | ||
7567 | if (calculate_reloc (*reloc_type, address_expr->X_add_number, | |
7568 | &value)) | |
7569 | { | |
7570 | ip->insn_opcode |= value & 0xffff; | |
7571 | ip->complete_p = 1; | |
7572 | } | |
7573 | } | |
7574 | break; | |
7575 | } | |
15be625d CM |
7576 | } |
7577 | ||
71400594 RS |
7578 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
7579 | { | |
7580 | /* There are a lot of optimizations we could do that we don't. | |
7581 | In particular, we do not, in general, reorder instructions. | |
7582 | If you use gcc with optimization, it will reorder | |
7583 | instructions and generally do much more optimization then we | |
7584 | do here; repeating all that work in the assembler would only | |
7585 | benefit hand written assembly code, and does not seem worth | |
7586 | it. */ | |
7587 | int nops = (mips_optimize == 0 | |
932d1a1b RS |
7588 | ? nops_for_insn (0, history, NULL) |
7589 | : nops_for_insn_or_target (0, history, ip)); | |
71400594 | 7590 | if (nops > 0) |
252b5132 RH |
7591 | { |
7592 | fragS *old_frag; | |
7593 | unsigned long old_frag_offset; | |
7594 | int i; | |
252b5132 RH |
7595 | |
7596 | old_frag = frag_now; | |
7597 | old_frag_offset = frag_now_fix (); | |
7598 | ||
7599 | for (i = 0; i < nops; i++) | |
14fe068b RS |
7600 | add_fixed_insn (NOP_INSN); |
7601 | insert_into_history (0, nops, NOP_INSN); | |
252b5132 RH |
7602 | |
7603 | if (listing) | |
7604 | { | |
7605 | listing_prev_line (); | |
7606 | /* We may be at the start of a variant frag. In case we | |
7607 | are, make sure there is enough space for the frag | |
7608 | after the frags created by listing_prev_line. The | |
7609 | argument to frag_grow here must be at least as large | |
7610 | as the argument to all other calls to frag_grow in | |
7611 | this file. We don't have to worry about being in the | |
7612 | middle of a variant frag, because the variants insert | |
7613 | all needed nop instructions themselves. */ | |
7614 | frag_grow (40); | |
7615 | } | |
7616 | ||
462427c4 | 7617 | mips_move_text_labels (); |
252b5132 RH |
7618 | |
7619 | #ifndef NO_ECOFF_DEBUGGING | |
7620 | if (ECOFF_DEBUGGING) | |
7621 | ecoff_fix_loc (old_frag, old_frag_offset); | |
7622 | #endif | |
7623 | } | |
71400594 RS |
7624 | } |
7625 | else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) | |
7626 | { | |
932d1a1b RS |
7627 | int nops; |
7628 | ||
7629 | /* Work out how many nops in prev_nop_frag are needed by IP, | |
7630 | ignoring hazards generated by the first prev_nop_frag_since | |
7631 | instructions. */ | |
7632 | nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip); | |
9c2799c2 | 7633 | gas_assert (nops <= prev_nop_frag_holds); |
252b5132 | 7634 | |
71400594 RS |
7635 | /* Enforce NOPS as a minimum. */ |
7636 | if (nops > prev_nop_frag_required) | |
7637 | prev_nop_frag_required = nops; | |
252b5132 | 7638 | |
71400594 RS |
7639 | if (prev_nop_frag_holds == prev_nop_frag_required) |
7640 | { | |
7641 | /* Settle for the current number of nops. Update the history | |
7642 | accordingly (for the benefit of any future .set reorder code). */ | |
7643 | prev_nop_frag = NULL; | |
7644 | insert_into_history (prev_nop_frag_since, | |
7645 | prev_nop_frag_holds, NOP_INSN); | |
7646 | } | |
7647 | else | |
7648 | { | |
7649 | /* Allow this instruction to replace one of the nops that was | |
7650 | tentatively added to prev_nop_frag. */ | |
df58fc94 | 7651 | prev_nop_frag->fr_fix -= NOP_INSN_SIZE; |
71400594 RS |
7652 | prev_nop_frag_holds--; |
7653 | prev_nop_frag_since++; | |
252b5132 RH |
7654 | } |
7655 | } | |
7656 | ||
e407c74b | 7657 | method = get_append_method (ip, address_expr, reloc_type); |
2b0c8b40 | 7658 | branch_disp = method == APPEND_SWAP ? insn_length (history) : 0; |
a4e06468 | 7659 | |
e410add4 RS |
7660 | dwarf2_emit_insn (0); |
7661 | /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses, | |
7662 | so "move" the instruction address accordingly. | |
7663 | ||
7664 | Also, it doesn't seem appropriate for the assembler to reorder .loc | |
7665 | entries. If this instruction is a branch that we are going to swap | |
7666 | with the previous instruction, the two instructions should be | |
7667 | treated as a unit, and the debug information for both instructions | |
7668 | should refer to the start of the branch sequence. Using the | |
7669 | current position is certainly wrong when swapping a 32-bit branch | |
7670 | and a 16-bit delay slot, since the current position would then be | |
7671 | in the middle of a branch. */ | |
7672 | dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp); | |
58e2ea4d | 7673 | |
df58fc94 RS |
7674 | relax32 = (mips_relax_branch |
7675 | /* Don't try branch relaxation within .set nomacro, or within | |
7676 | .set noat if we use $at for PIC computations. If it turns | |
7677 | out that the branch was out-of-range, we'll get an error. */ | |
7678 | && !mips_opts.warn_about_macros | |
7679 | && (mips_opts.at || mips_pic == NO_PIC) | |
3bf0dbfb MR |
7680 | /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F |
7681 | as they have no complementing branches. */ | |
7682 | && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP))); | |
df58fc94 RS |
7683 | |
7684 | if (!HAVE_CODE_COMPRESSION | |
7685 | && address_expr | |
7686 | && relax32 | |
0b25d3e6 | 7687 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
11625dd8 | 7688 | && delayed_branch_p (ip)) |
4a6a3df4 | 7689 | { |
895921c9 | 7690 | relaxed_branch = TRUE; |
1e915849 RS |
7691 | add_relaxed_insn (ip, (relaxed_branch_length |
7692 | (NULL, NULL, | |
11625dd8 RS |
7693 | uncond_branch_p (ip) ? -1 |
7694 | : branch_likely_p (ip) ? 1 | |
1e915849 RS |
7695 | : 0)), 4, |
7696 | RELAX_BRANCH_ENCODE | |
ce8ad872 | 7697 | (AT, mips_pic != NO_PIC, |
11625dd8 RS |
7698 | uncond_branch_p (ip), |
7699 | branch_likely_p (ip), | |
1e915849 RS |
7700 | pinfo & INSN_WRITE_GPR_31, |
7701 | 0), | |
7702 | address_expr->X_add_symbol, | |
7703 | address_expr->X_add_number); | |
4a6a3df4 AO |
7704 | *reloc_type = BFD_RELOC_UNUSED; |
7705 | } | |
df58fc94 RS |
7706 | else if (mips_opts.micromips |
7707 | && address_expr | |
7708 | && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2) | |
7709 | || *reloc_type > BFD_RELOC_UNUSED) | |
40209cad MR |
7710 | && (delayed_branch_p (ip) || compact_branch_p (ip)) |
7711 | /* Don't try branch relaxation when users specify | |
7712 | 16-bit/32-bit instructions. */ | |
7713 | && !forced_insn_length) | |
df58fc94 | 7714 | { |
7bd374a4 MR |
7715 | bfd_boolean relax16 = (method != APPEND_ADD_COMPACT |
7716 | && *reloc_type > BFD_RELOC_UNUSED); | |
df58fc94 | 7717 | int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0; |
11625dd8 | 7718 | int uncond = uncond_branch_p (ip) ? -1 : 0; |
7bd374a4 MR |
7719 | int compact = compact_branch_p (ip) || method == APPEND_ADD_COMPACT; |
7720 | int nods = method == APPEND_ADD_WITH_NOP; | |
df58fc94 | 7721 | int al = pinfo & INSN_WRITE_GPR_31; |
7bd374a4 | 7722 | int length32 = nods ? 8 : 4; |
df58fc94 RS |
7723 | |
7724 | gas_assert (address_expr != NULL); | |
7725 | gas_assert (!mips_relax.sequence); | |
7726 | ||
2b0c8b40 | 7727 | relaxed_branch = TRUE; |
7bd374a4 MR |
7728 | if (nods) |
7729 | method = APPEND_ADD; | |
7730 | if (relax32) | |
7731 | length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond); | |
7732 | add_relaxed_insn (ip, length32, relax16 ? 2 : 4, | |
8484fb75 | 7733 | RELAX_MICROMIPS_ENCODE (type, AT, mips_opts.insn32, |
ce8ad872 | 7734 | mips_pic != NO_PIC, |
7bd374a4 | 7735 | uncond, compact, al, nods, |
40209cad | 7736 | relax32, 0, 0), |
df58fc94 RS |
7737 | address_expr->X_add_symbol, |
7738 | address_expr->X_add_number); | |
7739 | *reloc_type = BFD_RELOC_UNUSED; | |
7740 | } | |
7741 | else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED) | |
252b5132 | 7742 | { |
7fd53920 MR |
7743 | bfd_boolean require_unextended; |
7744 | bfd_boolean require_extended; | |
88a7ef16 MR |
7745 | symbolS *symbol; |
7746 | offsetT offset; | |
7747 | ||
7fd53920 MR |
7748 | if (forced_insn_length != 0) |
7749 | { | |
7750 | require_unextended = forced_insn_length == 2; | |
7751 | require_extended = forced_insn_length == 4; | |
7752 | } | |
7753 | else | |
7754 | { | |
7755 | require_unextended = (mips_opts.noautoextend | |
7756 | && !mips_opcode_32bit_p (ip->insn_mo)); | |
7757 | require_extended = 0; | |
7758 | } | |
7759 | ||
252b5132 | 7760 | /* We need to set up a variant frag. */ |
df58fc94 | 7761 | gas_assert (address_expr != NULL); |
88a7ef16 MR |
7762 | /* Pass any `O_symbol' expression unchanged as an `expr_section' |
7763 | symbol created by `make_expr_symbol' may not get a necessary | |
7764 | external relocation produced. */ | |
7765 | if (address_expr->X_op == O_symbol) | |
7766 | { | |
7767 | symbol = address_expr->X_add_symbol; | |
7768 | offset = address_expr->X_add_number; | |
7769 | } | |
7770 | else | |
7771 | { | |
7772 | symbol = make_expr_symbol (address_expr); | |
82d808ed | 7773 | symbol_append (symbol, symbol_lastP, &symbol_rootP, &symbol_lastP); |
88a7ef16 MR |
7774 | offset = 0; |
7775 | } | |
8507b6e7 | 7776 | add_relaxed_insn (ip, 12, 0, |
1e915849 RS |
7777 | RELAX_MIPS16_ENCODE |
7778 | (*reloc_type - BFD_RELOC_UNUSED, | |
25499ac7 | 7779 | mips_opts.ase & ASE_MIPS16E2, |
8507b6e7 MR |
7780 | mips_pic != NO_PIC, |
7781 | HAVE_32BIT_SYMBOLS, | |
7782 | mips_opts.warn_about_macros, | |
7fd53920 | 7783 | require_unextended, require_extended, |
11625dd8 | 7784 | delayed_branch_p (&history[0]), |
1e915849 | 7785 | history[0].mips16_absolute_jump_p), |
88a7ef16 | 7786 | symbol, offset); |
252b5132 | 7787 | } |
5c04167a | 7788 | else if (mips_opts.mips16 && insn_length (ip) == 2) |
9497f5ac | 7789 | { |
11625dd8 | 7790 | if (!delayed_branch_p (ip)) |
b8ee1a6e DU |
7791 | /* Make sure there is enough room to swap this instruction with |
7792 | a following jump instruction. */ | |
7793 | frag_grow (6); | |
1e915849 | 7794 | add_fixed_insn (ip); |
252b5132 RH |
7795 | } |
7796 | else | |
7797 | { | |
7798 | if (mips_opts.mips16 | |
7799 | && mips_opts.noreorder | |
11625dd8 | 7800 | && delayed_branch_p (&history[0])) |
252b5132 RH |
7801 | as_warn (_("extended instruction in delay slot")); |
7802 | ||
4d7206a2 RS |
7803 | if (mips_relax.sequence) |
7804 | { | |
7805 | /* If we've reached the end of this frag, turn it into a variant | |
7806 | frag and record the information for the instructions we've | |
7807 | written so far. */ | |
7808 | if (frag_room () < 4) | |
7809 | relax_close_frag (); | |
df58fc94 | 7810 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip); |
4d7206a2 RS |
7811 | } |
7812 | ||
584892a6 | 7813 | if (mips_relax.sequence != 2) |
df58fc94 RS |
7814 | { |
7815 | if (mips_macro_warning.first_insn_sizes[0] == 0) | |
7816 | mips_macro_warning.first_insn_sizes[0] = insn_length (ip); | |
7817 | mips_macro_warning.sizes[0] += insn_length (ip); | |
7818 | mips_macro_warning.insns[0]++; | |
7819 | } | |
584892a6 | 7820 | if (mips_relax.sequence != 1) |
df58fc94 RS |
7821 | { |
7822 | if (mips_macro_warning.first_insn_sizes[1] == 0) | |
7823 | mips_macro_warning.first_insn_sizes[1] = insn_length (ip); | |
7824 | mips_macro_warning.sizes[1] += insn_length (ip); | |
7825 | mips_macro_warning.insns[1]++; | |
7826 | } | |
584892a6 | 7827 | |
1e915849 RS |
7828 | if (mips_opts.mips16) |
7829 | { | |
7830 | ip->fixed_p = 1; | |
7831 | ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); | |
7832 | } | |
7833 | add_fixed_insn (ip); | |
252b5132 RH |
7834 | } |
7835 | ||
9fe77896 | 7836 | if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 7837 | { |
df58fc94 | 7838 | bfd_reloc_code_real_type final_type[3]; |
2309ddf2 | 7839 | reloc_howto_type *howto0; |
9fe77896 RS |
7840 | reloc_howto_type *howto; |
7841 | int i; | |
34ce925e | 7842 | |
df58fc94 RS |
7843 | /* Perform any necessary conversion to microMIPS relocations |
7844 | and find out how many relocations there actually are. */ | |
7845 | for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++) | |
7846 | final_type[i] = micromips_map_reloc (reloc_type[i]); | |
7847 | ||
9fe77896 RS |
7848 | /* In a compound relocation, it is the final (outermost) |
7849 | operator that determines the relocated field. */ | |
2309ddf2 | 7850 | howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]); |
e8044f35 RS |
7851 | if (!howto) |
7852 | abort (); | |
2309ddf2 MR |
7853 | |
7854 | if (i > 1) | |
7855 | howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]); | |
9fe77896 RS |
7856 | ip->fixp[0] = fix_new_exp (ip->frag, ip->where, |
7857 | bfd_get_reloc_size (howto), | |
7858 | address_expr, | |
2309ddf2 MR |
7859 | howto0 && howto0->pc_relative, |
7860 | final_type[0]); | |
ce8ad872 MR |
7861 | /* Record non-PIC mode in `fx_tcbit2' for `md_apply_fix'. */ |
7862 | ip->fixp[0]->fx_tcbit2 = mips_pic == NO_PIC; | |
9fe77896 RS |
7863 | |
7864 | /* Tag symbols that have a R_MIPS16_26 relocation against them. */ | |
2309ddf2 | 7865 | if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy) |
9fe77896 RS |
7866 | *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1; |
7867 | ||
7868 | /* These relocations can have an addend that won't fit in | |
7869 | 4 octets for 64bit assembly. */ | |
bad1aba3 | 7870 | if (GPR_SIZE == 64 |
9fe77896 RS |
7871 | && ! howto->partial_inplace |
7872 | && (reloc_type[0] == BFD_RELOC_16 | |
7873 | || reloc_type[0] == BFD_RELOC_32 | |
7874 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
7875 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
7876 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
7877 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
7878 | || reloc_type[0] == BFD_RELOC_64 | |
7879 | || reloc_type[0] == BFD_RELOC_CTOR | |
7880 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
7881 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
7882 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
7883 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
7884 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
7885 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT | |
7886 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
7887 | || hi16_reloc_p (reloc_type[0]) | |
7888 | || lo16_reloc_p (reloc_type[0]))) | |
7889 | ip->fixp[0]->fx_no_overflow = 1; | |
7890 | ||
ddaf2c41 MR |
7891 | /* These relocations can have an addend that won't fit in 2 octets. */ |
7892 | if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
7893 | || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1) | |
7894 | ip->fixp[0]->fx_no_overflow = 1; | |
7895 | ||
9fe77896 RS |
7896 | if (mips_relax.sequence) |
7897 | { | |
7898 | if (mips_relax.first_fixup == 0) | |
7899 | mips_relax.first_fixup = ip->fixp[0]; | |
7900 | } | |
7901 | else if (reloc_needs_lo_p (*reloc_type)) | |
7902 | { | |
7903 | struct mips_hi_fixup *hi_fixup; | |
7904 | ||
7905 | /* Reuse the last entry if it already has a matching %lo. */ | |
7906 | hi_fixup = mips_hi_fixup_list; | |
7907 | if (hi_fixup == 0 | |
7908 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
4d7206a2 | 7909 | { |
325801bd | 7910 | hi_fixup = XNEW (struct mips_hi_fixup); |
9fe77896 RS |
7911 | hi_fixup->next = mips_hi_fixup_list; |
7912 | mips_hi_fixup_list = hi_fixup; | |
4d7206a2 | 7913 | } |
9fe77896 RS |
7914 | hi_fixup->fixp = ip->fixp[0]; |
7915 | hi_fixup->seg = now_seg; | |
7916 | } | |
252b5132 | 7917 | |
9fe77896 RS |
7918 | /* Add fixups for the second and third relocations, if given. |
7919 | Note that the ABI allows the second relocation to be | |
7920 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
7921 | moment we only use RSS_UNDEF, but we could add support | |
7922 | for the others if it ever becomes necessary. */ | |
7923 | for (i = 1; i < 3; i++) | |
7924 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
7925 | { | |
7926 | ip->fixp[i] = fix_new (ip->frag, ip->where, | |
7927 | ip->fixp[0]->fx_size, NULL, 0, | |
df58fc94 | 7928 | FALSE, final_type[i]); |
f6688943 | 7929 | |
9fe77896 RS |
7930 | /* Use fx_tcbit to mark compound relocs. */ |
7931 | ip->fixp[0]->fx_tcbit = 1; | |
7932 | ip->fixp[i]->fx_tcbit = 1; | |
7933 | } | |
252b5132 | 7934 | } |
252b5132 RH |
7935 | |
7936 | /* Update the register mask information. */ | |
4c260379 RS |
7937 | mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip); |
7938 | mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip); | |
252b5132 | 7939 | |
a4e06468 | 7940 | switch (method) |
252b5132 | 7941 | { |
a4e06468 RS |
7942 | case APPEND_ADD: |
7943 | insert_into_history (0, 1, ip); | |
7944 | break; | |
7945 | ||
7946 | case APPEND_ADD_WITH_NOP: | |
14fe068b RS |
7947 | { |
7948 | struct mips_cl_insn *nop; | |
7949 | ||
7950 | insert_into_history (0, 1, ip); | |
7951 | nop = get_delay_slot_nop (ip); | |
7952 | add_fixed_insn (nop); | |
7953 | insert_into_history (0, 1, nop); | |
7954 | if (mips_relax.sequence) | |
7955 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop); | |
7956 | } | |
a4e06468 RS |
7957 | break; |
7958 | ||
7959 | case APPEND_ADD_COMPACT: | |
7960 | /* Convert MIPS16 jr/jalr into a "compact" jump. */ | |
7bd374a4 MR |
7961 | if (mips_opts.mips16) |
7962 | { | |
7963 | ip->insn_opcode |= 0x0080; | |
7964 | find_altered_mips16_opcode (ip); | |
7965 | } | |
7966 | /* Convert microMIPS instructions. */ | |
7967 | else if (mips_opts.micromips) | |
7968 | { | |
7969 | /* jr16->jrc */ | |
7970 | if ((ip->insn_opcode & 0xffe0) == 0x4580) | |
7971 | ip->insn_opcode |= 0x0020; | |
7972 | /* b16->bc */ | |
7973 | else if ((ip->insn_opcode & 0xfc00) == 0xcc00) | |
7974 | ip->insn_opcode = 0x40e00000; | |
7975 | /* beqz16->beqzc, bnez16->bnezc */ | |
7976 | else if ((ip->insn_opcode & 0xdc00) == 0x8c00) | |
7977 | { | |
7978 | unsigned long regno; | |
7979 | ||
7980 | regno = ip->insn_opcode >> MICROMIPSOP_SH_MD; | |
7981 | regno &= MICROMIPSOP_MASK_MD; | |
7982 | regno = micromips_to_32_reg_d_map[regno]; | |
7983 | ip->insn_opcode = (((ip->insn_opcode << 9) & 0x00400000) | |
7984 | | (regno << MICROMIPSOP_SH_RS) | |
7985 | | 0x40a00000) ^ 0x00400000; | |
7986 | } | |
7987 | /* beqz->beqzc, bnez->bnezc */ | |
7988 | else if ((ip->insn_opcode & 0xdfe00000) == 0x94000000) | |
7989 | ip->insn_opcode = ((ip->insn_opcode & 0x001f0000) | |
7990 | | ((ip->insn_opcode >> 7) & 0x00400000) | |
7991 | | 0x40a00000) ^ 0x00400000; | |
7992 | /* beq $0->beqzc, bne $0->bnezc */ | |
7993 | else if ((ip->insn_opcode & 0xdc1f0000) == 0x94000000) | |
7994 | ip->insn_opcode = (((ip->insn_opcode >> | |
7995 | (MICROMIPSOP_SH_RT - MICROMIPSOP_SH_RS)) | |
7996 | & (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS)) | |
7997 | | ((ip->insn_opcode >> 7) & 0x00400000) | |
7998 | | 0x40a00000) ^ 0x00400000; | |
7999 | else | |
8000 | abort (); | |
8001 | find_altered_micromips_opcode (ip); | |
8002 | } | |
8003 | else | |
8004 | abort (); | |
a4e06468 RS |
8005 | install_insn (ip); |
8006 | insert_into_history (0, 1, ip); | |
8007 | break; | |
8008 | ||
8009 | case APPEND_SWAP: | |
8010 | { | |
8011 | struct mips_cl_insn delay = history[0]; | |
99e7978b MF |
8012 | |
8013 | if (relaxed_branch || delay.frag != ip->frag) | |
a4e06468 RS |
8014 | { |
8015 | /* Add the delay slot instruction to the end of the | |
8016 | current frag and shrink the fixed part of the | |
8017 | original frag. If the branch occupies the tail of | |
8018 | the latter, move it backwards to cover the gap. */ | |
2b0c8b40 | 8019 | delay.frag->fr_fix -= branch_disp; |
a4e06468 | 8020 | if (delay.frag == ip->frag) |
2b0c8b40 | 8021 | move_insn (ip, ip->frag, ip->where - branch_disp); |
a4e06468 RS |
8022 | add_fixed_insn (&delay); |
8023 | } | |
8024 | else | |
8025 | { | |
5e35670b MR |
8026 | /* If this is not a relaxed branch and we are in the |
8027 | same frag, then just swap the instructions. */ | |
8028 | move_insn (ip, delay.frag, delay.where); | |
8029 | move_insn (&delay, ip->frag, ip->where + insn_length (ip)); | |
a4e06468 RS |
8030 | } |
8031 | history[0] = *ip; | |
8032 | delay.fixed_p = 1; | |
8033 | insert_into_history (0, 1, &delay); | |
8034 | } | |
8035 | break; | |
252b5132 RH |
8036 | } |
8037 | ||
13408f1e | 8038 | /* If we have just completed an unconditional branch, clear the history. */ |
11625dd8 RS |
8039 | if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1])) |
8040 | || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0]))) | |
e407c74b NC |
8041 | { |
8042 | unsigned int i; | |
8043 | ||
79850f26 | 8044 | mips_no_prev_insn (); |
13408f1e | 8045 | |
e407c74b | 8046 | for (i = 0; i < ARRAY_SIZE (history); i++) |
79850f26 | 8047 | history[i].cleared_p = 1; |
e407c74b NC |
8048 | } |
8049 | ||
df58fc94 RS |
8050 | /* We need to emit a label at the end of branch-likely macros. */ |
8051 | if (emit_branch_likely_macro) | |
8052 | { | |
8053 | emit_branch_likely_macro = FALSE; | |
8054 | micromips_add_label (); | |
8055 | } | |
8056 | ||
252b5132 RH |
8057 | /* We just output an insn, so the next one doesn't have a label. */ |
8058 | mips_clear_insn_labels (); | |
252b5132 RH |
8059 | } |
8060 | ||
e407c74b NC |
8061 | /* Forget that there was any previous instruction or label. |
8062 | When BRANCH is true, the branch history is also flushed. */ | |
252b5132 RH |
8063 | |
8064 | static void | |
7d10b47d | 8065 | mips_no_prev_insn (void) |
252b5132 | 8066 | { |
7d10b47d RS |
8067 | prev_nop_frag = NULL; |
8068 | insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); | |
252b5132 RH |
8069 | mips_clear_insn_labels (); |
8070 | } | |
8071 | ||
7d10b47d RS |
8072 | /* This function must be called before we emit something other than |
8073 | instructions. It is like mips_no_prev_insn except that it inserts | |
8074 | any NOPS that might be needed by previous instructions. */ | |
252b5132 | 8075 | |
7d10b47d RS |
8076 | void |
8077 | mips_emit_delays (void) | |
252b5132 RH |
8078 | { |
8079 | if (! mips_opts.noreorder) | |
8080 | { | |
932d1a1b | 8081 | int nops = nops_for_insn (0, history, NULL); |
252b5132 RH |
8082 | if (nops > 0) |
8083 | { | |
7d10b47d RS |
8084 | while (nops-- > 0) |
8085 | add_fixed_insn (NOP_INSN); | |
462427c4 | 8086 | mips_move_text_labels (); |
7d10b47d RS |
8087 | } |
8088 | } | |
8089 | mips_no_prev_insn (); | |
8090 | } | |
8091 | ||
8092 | /* Start a (possibly nested) noreorder block. */ | |
8093 | ||
8094 | static void | |
8095 | start_noreorder (void) | |
8096 | { | |
8097 | if (mips_opts.noreorder == 0) | |
8098 | { | |
8099 | unsigned int i; | |
8100 | int nops; | |
8101 | ||
8102 | /* None of the instructions before the .set noreorder can be moved. */ | |
8103 | for (i = 0; i < ARRAY_SIZE (history); i++) | |
8104 | history[i].fixed_p = 1; | |
8105 | ||
8106 | /* Insert any nops that might be needed between the .set noreorder | |
8107 | block and the previous instructions. We will later remove any | |
8108 | nops that turn out not to be needed. */ | |
932d1a1b | 8109 | nops = nops_for_insn (0, history, NULL); |
7d10b47d RS |
8110 | if (nops > 0) |
8111 | { | |
8112 | if (mips_optimize != 0) | |
252b5132 RH |
8113 | { |
8114 | /* Record the frag which holds the nop instructions, so | |
8115 | that we can remove them if we don't need them. */ | |
df58fc94 | 8116 | frag_grow (nops * NOP_INSN_SIZE); |
252b5132 RH |
8117 | prev_nop_frag = frag_now; |
8118 | prev_nop_frag_holds = nops; | |
8119 | prev_nop_frag_required = 0; | |
8120 | prev_nop_frag_since = 0; | |
8121 | } | |
8122 | ||
8123 | for (; nops > 0; --nops) | |
1e915849 | 8124 | add_fixed_insn (NOP_INSN); |
252b5132 | 8125 | |
7d10b47d RS |
8126 | /* Move on to a new frag, so that it is safe to simply |
8127 | decrease the size of prev_nop_frag. */ | |
8128 | frag_wane (frag_now); | |
8129 | frag_new (0); | |
462427c4 | 8130 | mips_move_text_labels (); |
252b5132 | 8131 | } |
df58fc94 | 8132 | mips_mark_labels (); |
7d10b47d | 8133 | mips_clear_insn_labels (); |
252b5132 | 8134 | } |
7d10b47d RS |
8135 | mips_opts.noreorder++; |
8136 | mips_any_noreorder = 1; | |
8137 | } | |
252b5132 | 8138 | |
7d10b47d | 8139 | /* End a nested noreorder block. */ |
252b5132 | 8140 | |
7d10b47d RS |
8141 | static void |
8142 | end_noreorder (void) | |
8143 | { | |
8144 | mips_opts.noreorder--; | |
8145 | if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) | |
8146 | { | |
8147 | /* Commit to inserting prev_nop_frag_required nops and go back to | |
8148 | handling nop insertion the .set reorder way. */ | |
8149 | prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) | |
df58fc94 | 8150 | * NOP_INSN_SIZE); |
7d10b47d RS |
8151 | insert_into_history (prev_nop_frag_since, |
8152 | prev_nop_frag_required, NOP_INSN); | |
8153 | prev_nop_frag = NULL; | |
8154 | } | |
252b5132 RH |
8155 | } |
8156 | ||
97d87491 RS |
8157 | /* Sign-extend 32-bit mode constants that have bit 31 set and all |
8158 | higher bits unset. */ | |
8159 | ||
8160 | static void | |
8161 | normalize_constant_expr (expressionS *ex) | |
8162 | { | |
8163 | if (ex->X_op == O_constant | |
8164 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
8165 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
8166 | - 0x80000000); | |
8167 | } | |
8168 | ||
8169 | /* Sign-extend 32-bit mode address offsets that have bit 31 set and | |
8170 | all higher bits unset. */ | |
8171 | ||
8172 | static void | |
8173 | normalize_address_expr (expressionS *ex) | |
8174 | { | |
8175 | if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) | |
8176 | || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) | |
8177 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
8178 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
8179 | - 0x80000000); | |
8180 | } | |
8181 | ||
8182 | /* Try to match TOKENS against OPCODE, storing the result in INSN. | |
8183 | Return true if the match was successful. | |
8184 | ||
8185 | OPCODE_EXTRA is a value that should be ORed into the opcode | |
8186 | (used for VU0 channel suffixes, etc.). MORE_ALTS is true if | |
8187 | there are more alternatives after OPCODE and SOFT_MATCH is | |
8188 | as for mips_arg_info. */ | |
8189 | ||
8190 | static bfd_boolean | |
8191 | match_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode, | |
8192 | struct mips_operand_token *tokens, unsigned int opcode_extra, | |
60f20e8b | 8193 | bfd_boolean lax_match, bfd_boolean complete_p) |
97d87491 RS |
8194 | { |
8195 | const char *args; | |
8196 | struct mips_arg_info arg; | |
8197 | const struct mips_operand *operand; | |
8198 | char c; | |
8199 | ||
8200 | imm_expr.X_op = O_absent; | |
97d87491 RS |
8201 | offset_expr.X_op = O_absent; |
8202 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
8203 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
8204 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
8205 | ||
8206 | create_insn (insn, opcode); | |
60f20e8b RS |
8207 | /* When no opcode suffix is specified, assume ".xyzw". */ |
8208 | if ((opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0 && opcode_extra == 0) | |
8209 | insn->insn_opcode |= 0xf << mips_vu0_channel_mask.lsb; | |
8210 | else | |
8211 | insn->insn_opcode |= opcode_extra; | |
97d87491 RS |
8212 | memset (&arg, 0, sizeof (arg)); |
8213 | arg.insn = insn; | |
8214 | arg.token = tokens; | |
8215 | arg.argnum = 1; | |
8216 | arg.last_regno = ILLEGAL_REG; | |
8217 | arg.dest_regno = ILLEGAL_REG; | |
60f20e8b | 8218 | arg.lax_match = lax_match; |
97d87491 RS |
8219 | for (args = opcode->args;; ++args) |
8220 | { | |
8221 | if (arg.token->type == OT_END) | |
8222 | { | |
8223 | /* Handle unary instructions in which only one operand is given. | |
8224 | The source is then the same as the destination. */ | |
8225 | if (arg.opnum == 1 && *args == ',') | |
8226 | { | |
8227 | operand = (mips_opts.micromips | |
8228 | ? decode_micromips_operand (args + 1) | |
8229 | : decode_mips_operand (args + 1)); | |
8230 | if (operand && mips_optional_operand_p (operand)) | |
8231 | { | |
8232 | arg.token = tokens; | |
8233 | arg.argnum = 1; | |
8234 | continue; | |
8235 | } | |
8236 | } | |
8237 | ||
8238 | /* Treat elided base registers as $0. */ | |
8239 | if (strcmp (args, "(b)") == 0) | |
8240 | args += 3; | |
8241 | ||
8242 | if (args[0] == '+') | |
8243 | switch (args[1]) | |
8244 | { | |
8245 | case 'K': | |
8246 | case 'N': | |
8247 | /* The register suffix is optional. */ | |
8248 | args += 2; | |
8249 | break; | |
8250 | } | |
8251 | ||
8252 | /* Fail the match if there were too few operands. */ | |
8253 | if (*args) | |
8254 | return FALSE; | |
8255 | ||
8256 | /* Successful match. */ | |
60f20e8b RS |
8257 | if (!complete_p) |
8258 | return TRUE; | |
e3de51ce | 8259 | clear_insn_error (); |
97d87491 RS |
8260 | if (arg.dest_regno == arg.last_regno |
8261 | && strncmp (insn->insn_mo->name, "jalr", 4) == 0) | |
8262 | { | |
8263 | if (arg.opnum == 2) | |
e3de51ce | 8264 | set_insn_error |
1661c76c | 8265 | (0, _("source and destination must be different")); |
97d87491 | 8266 | else if (arg.last_regno == 31) |
e3de51ce | 8267 | set_insn_error |
1661c76c | 8268 | (0, _("a destination register must be supplied")); |
97d87491 | 8269 | } |
173d3447 CF |
8270 | else if (arg.last_regno == 31 |
8271 | && (strncmp (insn->insn_mo->name, "bltzal", 6) == 0 | |
8272 | || strncmp (insn->insn_mo->name, "bgezal", 6) == 0)) | |
8273 | set_insn_error (0, _("the source register must not be $31")); | |
97d87491 RS |
8274 | check_completed_insn (&arg); |
8275 | return TRUE; | |
8276 | } | |
8277 | ||
8278 | /* Fail the match if the line has too many operands. */ | |
8279 | if (*args == 0) | |
8280 | return FALSE; | |
8281 | ||
8282 | /* Handle characters that need to match exactly. */ | |
8283 | if (*args == '(' || *args == ')' || *args == ',') | |
8284 | { | |
8285 | if (match_char (&arg, *args)) | |
8286 | continue; | |
8287 | return FALSE; | |
8288 | } | |
8289 | if (*args == '#') | |
8290 | { | |
8291 | ++args; | |
8292 | if (arg.token->type == OT_DOUBLE_CHAR | |
8293 | && arg.token->u.ch == *args) | |
8294 | { | |
8295 | ++arg.token; | |
8296 | continue; | |
8297 | } | |
8298 | return FALSE; | |
8299 | } | |
8300 | ||
8301 | /* Handle special macro operands. Work out the properties of | |
8302 | other operands. */ | |
8303 | arg.opnum += 1; | |
97d87491 RS |
8304 | switch (*args) |
8305 | { | |
7361da2c AB |
8306 | case '-': |
8307 | switch (args[1]) | |
8308 | { | |
8309 | case 'A': | |
8310 | *offset_reloc = BFD_RELOC_MIPS_19_PCREL_S2; | |
8311 | break; | |
8312 | ||
8313 | case 'B': | |
8314 | *offset_reloc = BFD_RELOC_MIPS_18_PCREL_S3; | |
8315 | break; | |
8316 | } | |
8317 | break; | |
8318 | ||
97d87491 RS |
8319 | case '+': |
8320 | switch (args[1]) | |
8321 | { | |
97d87491 RS |
8322 | case 'i': |
8323 | *offset_reloc = BFD_RELOC_MIPS_JMP; | |
8324 | break; | |
7361da2c AB |
8325 | |
8326 | case '\'': | |
8327 | *offset_reloc = BFD_RELOC_MIPS_26_PCREL_S2; | |
8328 | break; | |
8329 | ||
8330 | case '\"': | |
8331 | *offset_reloc = BFD_RELOC_MIPS_21_PCREL_S2; | |
8332 | break; | |
97d87491 RS |
8333 | } |
8334 | break; | |
8335 | ||
97d87491 | 8336 | case 'I': |
1a00e612 RS |
8337 | if (!match_const_int (&arg, &imm_expr.X_add_number)) |
8338 | return FALSE; | |
8339 | imm_expr.X_op = O_constant; | |
bad1aba3 | 8340 | if (GPR_SIZE == 32) |
97d87491 RS |
8341 | normalize_constant_expr (&imm_expr); |
8342 | continue; | |
8343 | ||
8344 | case 'A': | |
8345 | if (arg.token->type == OT_CHAR && arg.token->u.ch == '(') | |
8346 | { | |
8347 | /* Assume that the offset has been elided and that what | |
8348 | we saw was a base register. The match will fail later | |
8349 | if that assumption turns out to be wrong. */ | |
8350 | offset_expr.X_op = O_constant; | |
8351 | offset_expr.X_add_number = 0; | |
8352 | } | |
97d87491 | 8353 | else |
1a00e612 RS |
8354 | { |
8355 | if (!match_expression (&arg, &offset_expr, offset_reloc)) | |
8356 | return FALSE; | |
8357 | normalize_address_expr (&offset_expr); | |
8358 | } | |
97d87491 RS |
8359 | continue; |
8360 | ||
8361 | case 'F': | |
8362 | if (!match_float_constant (&arg, &imm_expr, &offset_expr, | |
8363 | 8, TRUE)) | |
1a00e612 | 8364 | return FALSE; |
97d87491 RS |
8365 | continue; |
8366 | ||
8367 | case 'L': | |
8368 | if (!match_float_constant (&arg, &imm_expr, &offset_expr, | |
8369 | 8, FALSE)) | |
1a00e612 | 8370 | return FALSE; |
97d87491 RS |
8371 | continue; |
8372 | ||
8373 | case 'f': | |
8374 | if (!match_float_constant (&arg, &imm_expr, &offset_expr, | |
8375 | 4, TRUE)) | |
1a00e612 | 8376 | return FALSE; |
97d87491 RS |
8377 | continue; |
8378 | ||
8379 | case 'l': | |
8380 | if (!match_float_constant (&arg, &imm_expr, &offset_expr, | |
8381 | 4, FALSE)) | |
1a00e612 | 8382 | return FALSE; |
97d87491 RS |
8383 | continue; |
8384 | ||
97d87491 RS |
8385 | case 'p': |
8386 | *offset_reloc = BFD_RELOC_16_PCREL_S2; | |
8387 | break; | |
8388 | ||
8389 | case 'a': | |
8390 | *offset_reloc = BFD_RELOC_MIPS_JMP; | |
8391 | break; | |
8392 | ||
8393 | case 'm': | |
8394 | gas_assert (mips_opts.micromips); | |
8395 | c = args[1]; | |
8396 | switch (c) | |
8397 | { | |
8398 | case 'D': | |
8399 | case 'E': | |
8400 | if (!forced_insn_length) | |
8401 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; | |
8402 | else if (c == 'D') | |
8403 | *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1; | |
8404 | else | |
8405 | *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1; | |
8406 | break; | |
8407 | } | |
8408 | break; | |
8409 | } | |
8410 | ||
8411 | operand = (mips_opts.micromips | |
8412 | ? decode_micromips_operand (args) | |
8413 | : decode_mips_operand (args)); | |
8414 | if (!operand) | |
8415 | abort (); | |
8416 | ||
8417 | /* Skip prefixes. */ | |
7361da2c | 8418 | if (*args == '+' || *args == 'm' || *args == '-') |
97d87491 RS |
8419 | args++; |
8420 | ||
8421 | if (mips_optional_operand_p (operand) | |
8422 | && args[1] == ',' | |
8423 | && (arg.token[0].type != OT_REG | |
8424 | || arg.token[1].type == OT_END)) | |
8425 | { | |
8426 | /* Assume that the register has been elided and is the | |
8427 | same as the first operand. */ | |
8428 | arg.token = tokens; | |
8429 | arg.argnum = 1; | |
8430 | } | |
8431 | ||
8432 | if (!match_operand (&arg, operand)) | |
8433 | return FALSE; | |
8434 | } | |
8435 | } | |
8436 | ||
8437 | /* Like match_insn, but for MIPS16. */ | |
8438 | ||
8439 | static bfd_boolean | |
8440 | match_mips16_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode, | |
1a00e612 | 8441 | struct mips_operand_token *tokens) |
97d87491 RS |
8442 | { |
8443 | const char *args; | |
8444 | const struct mips_operand *operand; | |
8445 | const struct mips_operand *ext_operand; | |
82d808ed | 8446 | bfd_boolean pcrel = FALSE; |
7fd53920 | 8447 | int required_insn_length; |
97d87491 RS |
8448 | struct mips_arg_info arg; |
8449 | int relax_char; | |
8450 | ||
7fd53920 MR |
8451 | if (forced_insn_length) |
8452 | required_insn_length = forced_insn_length; | |
8453 | else if (mips_opts.noautoextend && !mips_opcode_32bit_p (opcode)) | |
8454 | required_insn_length = 2; | |
8455 | else | |
8456 | required_insn_length = 0; | |
8457 | ||
97d87491 RS |
8458 | create_insn (insn, opcode); |
8459 | imm_expr.X_op = O_absent; | |
97d87491 RS |
8460 | offset_expr.X_op = O_absent; |
8461 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
8462 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
8463 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
8464 | relax_char = 0; | |
8465 | ||
8466 | memset (&arg, 0, sizeof (arg)); | |
8467 | arg.insn = insn; | |
8468 | arg.token = tokens; | |
8469 | arg.argnum = 1; | |
8470 | arg.last_regno = ILLEGAL_REG; | |
8471 | arg.dest_regno = ILLEGAL_REG; | |
97d87491 RS |
8472 | relax_char = 0; |
8473 | for (args = opcode->args;; ++args) | |
8474 | { | |
8475 | int c; | |
8476 | ||
8477 | if (arg.token->type == OT_END) | |
8478 | { | |
8479 | offsetT value; | |
8480 | ||
8481 | /* Handle unary instructions in which only one operand is given. | |
8482 | The source is then the same as the destination. */ | |
8483 | if (arg.opnum == 1 && *args == ',') | |
8484 | { | |
8485 | operand = decode_mips16_operand (args[1], FALSE); | |
8486 | if (operand && mips_optional_operand_p (operand)) | |
8487 | { | |
8488 | arg.token = tokens; | |
8489 | arg.argnum = 1; | |
8490 | continue; | |
8491 | } | |
8492 | } | |
8493 | ||
8494 | /* Fail the match if there were too few operands. */ | |
8495 | if (*args) | |
8496 | return FALSE; | |
8497 | ||
8498 | /* Successful match. Stuff the immediate value in now, if | |
8499 | we can. */ | |
e3de51ce | 8500 | clear_insn_error (); |
97d87491 RS |
8501 | if (opcode->pinfo == INSN_MACRO) |
8502 | { | |
8503 | gas_assert (relax_char == 0 || relax_char == 'p'); | |
8504 | gas_assert (*offset_reloc == BFD_RELOC_UNUSED); | |
8505 | } | |
8506 | else if (relax_char | |
8507 | && offset_expr.X_op == O_constant | |
82d808ed | 8508 | && !pcrel |
97d87491 RS |
8509 | && calculate_reloc (*offset_reloc, |
8510 | offset_expr.X_add_number, | |
8511 | &value)) | |
8512 | { | |
8513 | mips16_immed (NULL, 0, relax_char, *offset_reloc, value, | |
7fd53920 | 8514 | required_insn_length, &insn->insn_opcode); |
97d87491 RS |
8515 | offset_expr.X_op = O_absent; |
8516 | *offset_reloc = BFD_RELOC_UNUSED; | |
8517 | } | |
8518 | else if (relax_char && *offset_reloc != BFD_RELOC_UNUSED) | |
8519 | { | |
7fd53920 | 8520 | if (required_insn_length == 2) |
e3de51ce | 8521 | set_insn_error (0, _("invalid unextended operand value")); |
25499ac7 | 8522 | else if (!mips_opcode_32bit_p (opcode)) |
1da43acc MR |
8523 | { |
8524 | forced_insn_length = 4; | |
8525 | insn->insn_opcode |= MIPS16_EXTEND; | |
8526 | } | |
97d87491 RS |
8527 | } |
8528 | else if (relax_char) | |
8529 | *offset_reloc = (int) BFD_RELOC_UNUSED + relax_char; | |
8530 | ||
8531 | check_completed_insn (&arg); | |
8532 | return TRUE; | |
8533 | } | |
8534 | ||
8535 | /* Fail the match if the line has too many operands. */ | |
8536 | if (*args == 0) | |
8537 | return FALSE; | |
8538 | ||
8539 | /* Handle characters that need to match exactly. */ | |
8540 | if (*args == '(' || *args == ')' || *args == ',') | |
8541 | { | |
8542 | if (match_char (&arg, *args)) | |
8543 | continue; | |
8544 | return FALSE; | |
8545 | } | |
8546 | ||
8547 | arg.opnum += 1; | |
8548 | c = *args; | |
8549 | switch (c) | |
8550 | { | |
8551 | case 'p': | |
8552 | case 'q': | |
8553 | case 'A': | |
8554 | case 'B': | |
8555 | case 'E': | |
25499ac7 MR |
8556 | case 'V': |
8557 | case 'u': | |
97d87491 RS |
8558 | relax_char = c; |
8559 | break; | |
8560 | ||
8561 | case 'I': | |
1a00e612 RS |
8562 | if (!match_const_int (&arg, &imm_expr.X_add_number)) |
8563 | return FALSE; | |
8564 | imm_expr.X_op = O_constant; | |
bad1aba3 | 8565 | if (GPR_SIZE == 32) |
97d87491 RS |
8566 | normalize_constant_expr (&imm_expr); |
8567 | continue; | |
8568 | ||
8569 | case 'a': | |
8570 | case 'i': | |
8571 | *offset_reloc = BFD_RELOC_MIPS16_JMP; | |
97d87491 RS |
8572 | break; |
8573 | } | |
8574 | ||
7fd53920 | 8575 | operand = decode_mips16_operand (c, mips_opcode_32bit_p (opcode)); |
97d87491 RS |
8576 | if (!operand) |
8577 | abort (); | |
8578 | ||
82d808ed MR |
8579 | if (operand->type == OP_PCREL) |
8580 | pcrel = TRUE; | |
8581 | else | |
97d87491 RS |
8582 | { |
8583 | ext_operand = decode_mips16_operand (c, TRUE); | |
8584 | if (operand != ext_operand) | |
8585 | { | |
8586 | if (arg.token->type == OT_CHAR && arg.token->u.ch == '(') | |
8587 | { | |
8588 | offset_expr.X_op = O_constant; | |
8589 | offset_expr.X_add_number = 0; | |
8590 | relax_char = c; | |
8591 | continue; | |
8592 | } | |
8593 | ||
1a7bf198 | 8594 | if (!match_expression (&arg, &offset_expr, offset_reloc)) |
97d87491 RS |
8595 | return FALSE; |
8596 | ||
8597 | /* '8' is used for SLTI(U) and has traditionally not | |
8598 | been allowed to take relocation operators. */ | |
8599 | if (offset_reloc[0] != BFD_RELOC_UNUSED | |
8600 | && (ext_operand->size != 16 || c == '8')) | |
e295202f MR |
8601 | { |
8602 | match_not_constant (&arg); | |
8603 | return FALSE; | |
8604 | } | |
97d87491 | 8605 | |
c96425c5 MR |
8606 | if (offset_expr.X_op == O_big) |
8607 | { | |
8608 | match_out_of_range (&arg); | |
8609 | return FALSE; | |
8610 | } | |
8611 | ||
97d87491 RS |
8612 | relax_char = c; |
8613 | continue; | |
8614 | } | |
8615 | } | |
8616 | ||
8617 | if (mips_optional_operand_p (operand) | |
8618 | && args[1] == ',' | |
8619 | && (arg.token[0].type != OT_REG | |
8620 | || arg.token[1].type == OT_END)) | |
8621 | { | |
8622 | /* Assume that the register has been elided and is the | |
8623 | same as the first operand. */ | |
8624 | arg.token = tokens; | |
8625 | arg.argnum = 1; | |
8626 | } | |
8627 | ||
8628 | if (!match_operand (&arg, operand)) | |
8629 | return FALSE; | |
8630 | } | |
8631 | } | |
8632 | ||
60f20e8b RS |
8633 | /* Record that the current instruction is invalid for the current ISA. */ |
8634 | ||
8635 | static void | |
8636 | match_invalid_for_isa (void) | |
8637 | { | |
8638 | set_insn_error_ss | |
1661c76c | 8639 | (0, _("opcode not supported on this processor: %s (%s)"), |
60f20e8b RS |
8640 | mips_cpu_info_from_arch (mips_opts.arch)->name, |
8641 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
8642 | } | |
8643 | ||
8644 | /* Try to match TOKENS against a series of opcode entries, starting at FIRST. | |
8645 | Return true if a definite match or failure was found, storing any match | |
8646 | in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode | |
8647 | (to handle things like VU0 suffixes). LAX_MATCH is true if we have already | |
8648 | tried and failed to match under normal conditions and now want to try a | |
8649 | more relaxed match. */ | |
8650 | ||
8651 | static bfd_boolean | |
8652 | match_insns (struct mips_cl_insn *insn, const struct mips_opcode *first, | |
8653 | const struct mips_opcode *past, struct mips_operand_token *tokens, | |
8654 | int opcode_extra, bfd_boolean lax_match) | |
8655 | { | |
8656 | const struct mips_opcode *opcode; | |
8657 | const struct mips_opcode *invalid_delay_slot; | |
8658 | bfd_boolean seen_valid_for_isa, seen_valid_for_size; | |
8659 | ||
8660 | /* Search for a match, ignoring alternatives that don't satisfy the | |
8661 | current ISA or forced_length. */ | |
8662 | invalid_delay_slot = 0; | |
8663 | seen_valid_for_isa = FALSE; | |
8664 | seen_valid_for_size = FALSE; | |
8665 | opcode = first; | |
8666 | do | |
8667 | { | |
8668 | gas_assert (strcmp (opcode->name, first->name) == 0); | |
8669 | if (is_opcode_valid (opcode)) | |
8670 | { | |
8671 | seen_valid_for_isa = TRUE; | |
8672 | if (is_size_valid (opcode)) | |
8673 | { | |
8674 | bfd_boolean delay_slot_ok; | |
8675 | ||
8676 | seen_valid_for_size = TRUE; | |
8677 | delay_slot_ok = is_delay_slot_valid (opcode); | |
8678 | if (match_insn (insn, opcode, tokens, opcode_extra, | |
8679 | lax_match, delay_slot_ok)) | |
8680 | { | |
8681 | if (!delay_slot_ok) | |
8682 | { | |
8683 | if (!invalid_delay_slot) | |
8684 | invalid_delay_slot = opcode; | |
8685 | } | |
8686 | else | |
8687 | return TRUE; | |
8688 | } | |
8689 | } | |
8690 | } | |
8691 | ++opcode; | |
8692 | } | |
8693 | while (opcode < past && strcmp (opcode->name, first->name) == 0); | |
8694 | ||
8695 | /* If the only matches we found had the wrong length for the delay slot, | |
8696 | pick the first such match. We'll issue an appropriate warning later. */ | |
8697 | if (invalid_delay_slot) | |
8698 | { | |
8699 | if (match_insn (insn, invalid_delay_slot, tokens, opcode_extra, | |
8700 | lax_match, TRUE)) | |
8701 | return TRUE; | |
8702 | abort (); | |
8703 | } | |
8704 | ||
8705 | /* Handle the case where we didn't try to match an instruction because | |
8706 | all the alternatives were incompatible with the current ISA. */ | |
8707 | if (!seen_valid_for_isa) | |
8708 | { | |
8709 | match_invalid_for_isa (); | |
8710 | return TRUE; | |
8711 | } | |
8712 | ||
8713 | /* Handle the case where we didn't try to match an instruction because | |
8714 | all the alternatives were of the wrong size. */ | |
8715 | if (!seen_valid_for_size) | |
8716 | { | |
8717 | if (mips_opts.insn32) | |
1661c76c | 8718 | set_insn_error (0, _("opcode not supported in the `insn32' mode")); |
60f20e8b RS |
8719 | else |
8720 | set_insn_error_i | |
1661c76c | 8721 | (0, _("unrecognized %d-bit version of microMIPS opcode"), |
60f20e8b RS |
8722 | 8 * forced_insn_length); |
8723 | return TRUE; | |
8724 | } | |
8725 | ||
8726 | return FALSE; | |
8727 | } | |
8728 | ||
8729 | /* Like match_insns, but for MIPS16. */ | |
8730 | ||
8731 | static bfd_boolean | |
8732 | match_mips16_insns (struct mips_cl_insn *insn, const struct mips_opcode *first, | |
8733 | struct mips_operand_token *tokens) | |
8734 | { | |
8735 | const struct mips_opcode *opcode; | |
8736 | bfd_boolean seen_valid_for_isa; | |
7fd53920 | 8737 | bfd_boolean seen_valid_for_size; |
60f20e8b RS |
8738 | |
8739 | /* Search for a match, ignoring alternatives that don't satisfy the | |
8740 | current ISA. There are no separate entries for extended forms so | |
8741 | we deal with forced_length later. */ | |
8742 | seen_valid_for_isa = FALSE; | |
7fd53920 | 8743 | seen_valid_for_size = FALSE; |
60f20e8b RS |
8744 | opcode = first; |
8745 | do | |
8746 | { | |
8747 | gas_assert (strcmp (opcode->name, first->name) == 0); | |
8748 | if (is_opcode_valid_16 (opcode)) | |
8749 | { | |
8750 | seen_valid_for_isa = TRUE; | |
7fd53920 MR |
8751 | if (is_size_valid_16 (opcode)) |
8752 | { | |
8753 | seen_valid_for_size = TRUE; | |
8754 | if (match_mips16_insn (insn, opcode, tokens)) | |
8755 | return TRUE; | |
8756 | } | |
60f20e8b RS |
8757 | } |
8758 | ++opcode; | |
8759 | } | |
8760 | while (opcode < &mips16_opcodes[bfd_mips16_num_opcodes] | |
8761 | && strcmp (opcode->name, first->name) == 0); | |
8762 | ||
8763 | /* Handle the case where we didn't try to match an instruction because | |
8764 | all the alternatives were incompatible with the current ISA. */ | |
8765 | if (!seen_valid_for_isa) | |
8766 | { | |
8767 | match_invalid_for_isa (); | |
8768 | return TRUE; | |
8769 | } | |
8770 | ||
7fd53920 MR |
8771 | /* Handle the case where we didn't try to match an instruction because |
8772 | all the alternatives were of the wrong size. */ | |
8773 | if (!seen_valid_for_size) | |
8774 | { | |
8775 | if (forced_insn_length == 2) | |
8776 | set_insn_error | |
8777 | (0, _("unrecognized unextended version of MIPS16 opcode")); | |
8778 | else | |
8779 | set_insn_error | |
8780 | (0, _("unrecognized extended version of MIPS16 opcode")); | |
8781 | return TRUE; | |
8782 | } | |
8783 | ||
60f20e8b RS |
8784 | return FALSE; |
8785 | } | |
8786 | ||
584892a6 RS |
8787 | /* Set up global variables for the start of a new macro. */ |
8788 | ||
8789 | static void | |
8790 | macro_start (void) | |
8791 | { | |
8792 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
df58fc94 RS |
8793 | memset (&mips_macro_warning.first_insn_sizes, 0, |
8794 | sizeof (mips_macro_warning.first_insn_sizes)); | |
8795 | memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns)); | |
584892a6 | 8796 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder |
11625dd8 | 8797 | && delayed_branch_p (&history[0])); |
7bd374a4 MR |
8798 | if (history[0].frag |
8799 | && history[0].frag->fr_type == rs_machine_dependent | |
8800 | && RELAX_MICROMIPS_P (history[0].frag->fr_subtype) | |
8801 | && RELAX_MICROMIPS_NODS (history[0].frag->fr_subtype)) | |
8802 | mips_macro_warning.delay_slot_length = 0; | |
8803 | else | |
8804 | switch (history[0].insn_mo->pinfo2 | |
8805 | & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT)) | |
8806 | { | |
8807 | case INSN2_BRANCH_DELAY_32BIT: | |
8808 | mips_macro_warning.delay_slot_length = 4; | |
8809 | break; | |
8810 | case INSN2_BRANCH_DELAY_16BIT: | |
8811 | mips_macro_warning.delay_slot_length = 2; | |
8812 | break; | |
8813 | default: | |
8814 | mips_macro_warning.delay_slot_length = 0; | |
8815 | break; | |
8816 | } | |
df58fc94 | 8817 | mips_macro_warning.first_frag = NULL; |
584892a6 RS |
8818 | } |
8819 | ||
df58fc94 RS |
8820 | /* Given that a macro is longer than one instruction or of the wrong size, |
8821 | return the appropriate warning for it. Return null if no warning is | |
8822 | needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT, | |
8823 | RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND, | |
8824 | and RELAX_NOMACRO. */ | |
584892a6 RS |
8825 | |
8826 | static const char * | |
8827 | macro_warning (relax_substateT subtype) | |
8828 | { | |
8829 | if (subtype & RELAX_DELAY_SLOT) | |
1661c76c | 8830 | return _("macro instruction expanded into multiple instructions" |
584892a6 RS |
8831 | " in a branch delay slot"); |
8832 | else if (subtype & RELAX_NOMACRO) | |
1661c76c | 8833 | return _("macro instruction expanded into multiple instructions"); |
df58fc94 RS |
8834 | else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST |
8835 | | RELAX_DELAY_SLOT_SIZE_SECOND)) | |
8836 | return ((subtype & RELAX_DELAY_SLOT_16BIT) | |
1661c76c | 8837 | ? _("macro instruction expanded into a wrong size instruction" |
df58fc94 | 8838 | " in a 16-bit branch delay slot") |
1661c76c | 8839 | : _("macro instruction expanded into a wrong size instruction" |
df58fc94 | 8840 | " in a 32-bit branch delay slot")); |
584892a6 RS |
8841 | else |
8842 | return 0; | |
8843 | } | |
8844 | ||
8845 | /* Finish up a macro. Emit warnings as appropriate. */ | |
8846 | ||
8847 | static void | |
8848 | macro_end (void) | |
8849 | { | |
df58fc94 RS |
8850 | /* Relaxation warning flags. */ |
8851 | relax_substateT subtype = 0; | |
8852 | ||
8853 | /* Check delay slot size requirements. */ | |
8854 | if (mips_macro_warning.delay_slot_length == 2) | |
8855 | subtype |= RELAX_DELAY_SLOT_16BIT; | |
8856 | if (mips_macro_warning.delay_slot_length != 0) | |
584892a6 | 8857 | { |
df58fc94 RS |
8858 | if (mips_macro_warning.delay_slot_length |
8859 | != mips_macro_warning.first_insn_sizes[0]) | |
8860 | subtype |= RELAX_DELAY_SLOT_SIZE_FIRST; | |
8861 | if (mips_macro_warning.delay_slot_length | |
8862 | != mips_macro_warning.first_insn_sizes[1]) | |
8863 | subtype |= RELAX_DELAY_SLOT_SIZE_SECOND; | |
8864 | } | |
584892a6 | 8865 | |
df58fc94 RS |
8866 | /* Check instruction count requirements. */ |
8867 | if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1) | |
8868 | { | |
8869 | if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0]) | |
584892a6 RS |
8870 | subtype |= RELAX_SECOND_LONGER; |
8871 | if (mips_opts.warn_about_macros) | |
8872 | subtype |= RELAX_NOMACRO; | |
8873 | if (mips_macro_warning.delay_slot_p) | |
8874 | subtype |= RELAX_DELAY_SLOT; | |
df58fc94 | 8875 | } |
584892a6 | 8876 | |
df58fc94 RS |
8877 | /* If both alternatives fail to fill a delay slot correctly, |
8878 | emit the warning now. */ | |
8879 | if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0 | |
8880 | && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0) | |
8881 | { | |
8882 | relax_substateT s; | |
8883 | const char *msg; | |
8884 | ||
8885 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
8886 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
8887 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
8888 | msg = macro_warning (s); | |
8889 | if (msg != NULL) | |
8890 | as_warn ("%s", msg); | |
8891 | subtype &= ~s; | |
8892 | } | |
8893 | ||
8894 | /* If both implementations are longer than 1 instruction, then emit the | |
8895 | warning now. */ | |
8896 | if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1) | |
8897 | { | |
8898 | relax_substateT s; | |
8899 | const char *msg; | |
8900 | ||
8901 | s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT); | |
8902 | msg = macro_warning (s); | |
8903 | if (msg != NULL) | |
8904 | as_warn ("%s", msg); | |
8905 | subtype &= ~s; | |
584892a6 | 8906 | } |
df58fc94 RS |
8907 | |
8908 | /* If any flags still set, then one implementation might need a warning | |
8909 | and the other either will need one of a different kind or none at all. | |
8910 | Pass any remaining flags over to relaxation. */ | |
8911 | if (mips_macro_warning.first_frag != NULL) | |
8912 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
584892a6 RS |
8913 | } |
8914 | ||
df58fc94 RS |
8915 | /* Instruction operand formats used in macros that vary between |
8916 | standard MIPS and microMIPS code. */ | |
8917 | ||
833794fc | 8918 | static const char * const brk_fmt[2][2] = { { "c", "c" }, { "mF", "c" } }; |
df58fc94 RS |
8919 | static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" }; |
8920 | static const char * const jalr_fmt[2] = { "d,s", "t,s" }; | |
8921 | static const char * const lui_fmt[2] = { "t,u", "s,u" }; | |
8922 | static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" }; | |
833794fc | 8923 | static const char * const mfhl_fmt[2][2] = { { "d", "d" }, { "mj", "s" } }; |
df58fc94 RS |
8924 | static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" }; |
8925 | static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" }; | |
8926 | ||
833794fc | 8927 | #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32]) |
7361da2c AB |
8928 | #define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \ |
8929 | : cop12_fmt[mips_opts.micromips]) | |
df58fc94 RS |
8930 | #define JALR_FMT (jalr_fmt[mips_opts.micromips]) |
8931 | #define LUI_FMT (lui_fmt[mips_opts.micromips]) | |
8932 | #define MEM12_FMT (mem12_fmt[mips_opts.micromips]) | |
7361da2c AB |
8933 | #define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \ |
8934 | : mem12_fmt[mips_opts.micromips]) | |
833794fc | 8935 | #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32]) |
df58fc94 RS |
8936 | #define SHFT_FMT (shft_fmt[mips_opts.micromips]) |
8937 | #define TRAP_FMT (trap_fmt[mips_opts.micromips]) | |
8938 | ||
6e1304d8 RS |
8939 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
8940 | The first argument in *ARGS will be either the code for a single | |
8941 | relocation or -1 followed by the three codes that make up a | |
8942 | composite relocation. */ | |
8943 | ||
8944 | static void | |
8945 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
8946 | { | |
8947 | int i, next; | |
8948 | ||
8949 | next = va_arg (*args, int); | |
8950 | if (next >= 0) | |
8951 | r[0] = (bfd_reloc_code_real_type) next; | |
8952 | else | |
f2ae14a1 RS |
8953 | { |
8954 | for (i = 0; i < 3; i++) | |
8955 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
8956 | /* This function is only used for 16-bit relocation fields. | |
8957 | To make the macro code simpler, treat an unrelocated value | |
8958 | in the same way as BFD_RELOC_LO16. */ | |
8959 | if (r[0] == BFD_RELOC_UNUSED) | |
8960 | r[0] = BFD_RELOC_LO16; | |
8961 | } | |
6e1304d8 RS |
8962 | } |
8963 | ||
252b5132 RH |
8964 | /* Build an instruction created by a macro expansion. This is passed |
8965 | a pointer to the count of instructions created so far, an | |
8966 | expression, the name of the instruction to build, an operand format | |
8967 | string, and corresponding arguments. */ | |
8968 | ||
252b5132 | 8969 | static void |
67c0d1eb | 8970 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 | 8971 | { |
df58fc94 | 8972 | const struct mips_opcode *mo = NULL; |
f6688943 | 8973 | bfd_reloc_code_real_type r[3]; |
df58fc94 | 8974 | const struct mips_opcode *amo; |
e077a1c8 | 8975 | const struct mips_operand *operand; |
df58fc94 RS |
8976 | struct hash_control *hash; |
8977 | struct mips_cl_insn insn; | |
252b5132 | 8978 | va_list args; |
e077a1c8 | 8979 | unsigned int uval; |
252b5132 | 8980 | |
252b5132 | 8981 | va_start (args, fmt); |
252b5132 | 8982 | |
252b5132 RH |
8983 | if (mips_opts.mips16) |
8984 | { | |
03ea81db | 8985 | mips16_macro_build (ep, name, fmt, &args); |
252b5132 RH |
8986 | va_end (args); |
8987 | return; | |
8988 | } | |
8989 | ||
f6688943 TS |
8990 | r[0] = BFD_RELOC_UNUSED; |
8991 | r[1] = BFD_RELOC_UNUSED; | |
8992 | r[2] = BFD_RELOC_UNUSED; | |
df58fc94 RS |
8993 | hash = mips_opts.micromips ? micromips_op_hash : op_hash; |
8994 | amo = (struct mips_opcode *) hash_find (hash, name); | |
8995 | gas_assert (amo); | |
8996 | gas_assert (strcmp (name, amo->name) == 0); | |
1e915849 | 8997 | |
df58fc94 | 8998 | do |
8b082fb1 TS |
8999 | { |
9000 | /* Search until we get a match for NAME. It is assumed here that | |
df58fc94 | 9001 | macros will never generate MDMX, MIPS-3D, or MT instructions. |
33eaf5de | 9002 | We try to match an instruction that fulfills the branch delay |
df58fc94 RS |
9003 | slot instruction length requirement (if any) of the previous |
9004 | instruction. While doing this we record the first instruction | |
9005 | seen that matches all the other conditions and use it anyway | |
9006 | if the requirement cannot be met; we will issue an appropriate | |
9007 | warning later on. */ | |
9008 | if (strcmp (fmt, amo->args) == 0 | |
9009 | && amo->pinfo != INSN_MACRO | |
9010 | && is_opcode_valid (amo) | |
9011 | && is_size_valid (amo)) | |
9012 | { | |
9013 | if (is_delay_slot_valid (amo)) | |
9014 | { | |
9015 | mo = amo; | |
9016 | break; | |
9017 | } | |
9018 | else if (!mo) | |
9019 | mo = amo; | |
9020 | } | |
8b082fb1 | 9021 | |
df58fc94 RS |
9022 | ++amo; |
9023 | gas_assert (amo->name); | |
252b5132 | 9024 | } |
df58fc94 | 9025 | while (strcmp (name, amo->name) == 0); |
252b5132 | 9026 | |
df58fc94 | 9027 | gas_assert (mo); |
1e915849 | 9028 | create_insn (&insn, mo); |
e077a1c8 | 9029 | for (; *fmt; ++fmt) |
252b5132 | 9030 | { |
e077a1c8 | 9031 | switch (*fmt) |
252b5132 | 9032 | { |
252b5132 RH |
9033 | case ',': |
9034 | case '(': | |
9035 | case ')': | |
252b5132 | 9036 | case 'z': |
e077a1c8 | 9037 | break; |
252b5132 RH |
9038 | |
9039 | case 'i': | |
9040 | case 'j': | |
6e1304d8 | 9041 | macro_read_relocs (&args, r); |
9c2799c2 | 9042 | gas_assert (*r == BFD_RELOC_GPREL16 |
e391c024 RS |
9043 | || *r == BFD_RELOC_MIPS_HIGHER |
9044 | || *r == BFD_RELOC_HI16_S | |
9045 | || *r == BFD_RELOC_LO16 | |
14c80123 MR |
9046 | || *r == BFD_RELOC_MIPS_GOT_OFST |
9047 | || (mips_opts.micromips | |
9048 | && (*r == BFD_RELOC_16 | |
9049 | || *r == BFD_RELOC_MIPS_GOT16 | |
9050 | || *r == BFD_RELOC_MIPS_CALL16 | |
9051 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
9052 | || *r == BFD_RELOC_MIPS_GOT_LO16 | |
9053 | || *r == BFD_RELOC_MIPS_CALL_HI16 | |
9054 | || *r == BFD_RELOC_MIPS_CALL_LO16 | |
9055 | || *r == BFD_RELOC_MIPS_SUB | |
9056 | || *r == BFD_RELOC_MIPS_GOT_PAGE | |
9057 | || *r == BFD_RELOC_MIPS_HIGHEST | |
9058 | || *r == BFD_RELOC_MIPS_GOT_DISP | |
9059 | || *r == BFD_RELOC_MIPS_TLS_GD | |
9060 | || *r == BFD_RELOC_MIPS_TLS_LDM | |
9061 | || *r == BFD_RELOC_MIPS_TLS_DTPREL_HI16 | |
9062 | || *r == BFD_RELOC_MIPS_TLS_DTPREL_LO16 | |
9063 | || *r == BFD_RELOC_MIPS_TLS_GOTTPREL | |
9064 | || *r == BFD_RELOC_MIPS_TLS_TPREL_HI16 | |
9065 | || *r == BFD_RELOC_MIPS_TLS_TPREL_LO16))); | |
e077a1c8 | 9066 | break; |
e391c024 RS |
9067 | |
9068 | case 'o': | |
9069 | macro_read_relocs (&args, r); | |
e077a1c8 | 9070 | break; |
252b5132 RH |
9071 | |
9072 | case 'u': | |
6e1304d8 | 9073 | macro_read_relocs (&args, r); |
9c2799c2 | 9074 | gas_assert (ep != NULL |
90ecf173 MR |
9075 | && (ep->X_op == O_constant |
9076 | || (ep->X_op == O_symbol | |
9077 | && (*r == BFD_RELOC_MIPS_HIGHEST | |
9078 | || *r == BFD_RELOC_HI16_S | |
9079 | || *r == BFD_RELOC_HI16 | |
9080 | || *r == BFD_RELOC_GPREL16 | |
9081 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
9082 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); | |
e077a1c8 | 9083 | break; |
252b5132 RH |
9084 | |
9085 | case 'p': | |
9c2799c2 | 9086 | gas_assert (ep != NULL); |
bad36eac | 9087 | |
252b5132 RH |
9088 | /* |
9089 | * This allows macro() to pass an immediate expression for | |
9090 | * creating short branches without creating a symbol. | |
bad36eac DJ |
9091 | * |
9092 | * We don't allow branch relaxation for these branches, as | |
9093 | * they should only appear in ".set nomacro" anyway. | |
252b5132 RH |
9094 | */ |
9095 | if (ep->X_op == O_constant) | |
9096 | { | |
df58fc94 RS |
9097 | /* For microMIPS we always use relocations for branches. |
9098 | So we should not resolve immediate values. */ | |
9099 | gas_assert (!mips_opts.micromips); | |
9100 | ||
bad36eac DJ |
9101 | if ((ep->X_add_number & 3) != 0) |
9102 | as_bad (_("branch to misaligned address (0x%lx)"), | |
9103 | (unsigned long) ep->X_add_number); | |
9104 | if ((ep->X_add_number + 0x20000) & ~0x3ffff) | |
9105 | as_bad (_("branch address range overflow (0x%lx)"), | |
9106 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
9107 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; |
9108 | ep = NULL; | |
9109 | } | |
9110 | else | |
0b25d3e6 | 9111 | *r = BFD_RELOC_16_PCREL_S2; |
e077a1c8 | 9112 | break; |
252b5132 RH |
9113 | |
9114 | case 'a': | |
9c2799c2 | 9115 | gas_assert (ep != NULL); |
f6688943 | 9116 | *r = BFD_RELOC_MIPS_JMP; |
e077a1c8 | 9117 | break; |
d43b4baf | 9118 | |
252b5132 | 9119 | default: |
e077a1c8 RS |
9120 | operand = (mips_opts.micromips |
9121 | ? decode_micromips_operand (fmt) | |
9122 | : decode_mips_operand (fmt)); | |
9123 | if (!operand) | |
9124 | abort (); | |
9125 | ||
9126 | uval = va_arg (args, int); | |
9127 | if (operand->type == OP_CLO_CLZ_DEST) | |
9128 | uval |= (uval << 5); | |
9129 | insn_insert_operand (&insn, operand, uval); | |
9130 | ||
7361da2c | 9131 | if (*fmt == '+' || *fmt == 'm' || *fmt == '-') |
e077a1c8 RS |
9132 | ++fmt; |
9133 | break; | |
252b5132 | 9134 | } |
252b5132 RH |
9135 | } |
9136 | va_end (args); | |
9c2799c2 | 9137 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 9138 | |
df58fc94 | 9139 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
9140 | } |
9141 | ||
9142 | static void | |
67c0d1eb | 9143 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
03ea81db | 9144 | va_list *args) |
252b5132 | 9145 | { |
1e915849 | 9146 | struct mips_opcode *mo; |
252b5132 | 9147 | struct mips_cl_insn insn; |
e077a1c8 | 9148 | const struct mips_operand *operand; |
f6688943 TS |
9149 | bfd_reloc_code_real_type r[3] |
9150 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 9151 | |
1e915849 | 9152 | mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
9c2799c2 NC |
9153 | gas_assert (mo); |
9154 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 | 9155 | |
1e915849 | 9156 | while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) |
252b5132 | 9157 | { |
1e915849 | 9158 | ++mo; |
9c2799c2 NC |
9159 | gas_assert (mo->name); |
9160 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
9161 | } |
9162 | ||
1e915849 | 9163 | create_insn (&insn, mo); |
e077a1c8 | 9164 | for (; *fmt; ++fmt) |
252b5132 RH |
9165 | { |
9166 | int c; | |
9167 | ||
e077a1c8 | 9168 | c = *fmt; |
252b5132 RH |
9169 | switch (c) |
9170 | { | |
252b5132 RH |
9171 | case ',': |
9172 | case '(': | |
9173 | case ')': | |
e077a1c8 | 9174 | break; |
252b5132 | 9175 | |
d8722d76 | 9176 | case '.': |
252b5132 RH |
9177 | case 'S': |
9178 | case 'P': | |
9179 | case 'R': | |
e077a1c8 | 9180 | break; |
252b5132 RH |
9181 | |
9182 | case '<': | |
252b5132 | 9183 | case '5': |
d8722d76 | 9184 | case 'F': |
252b5132 RH |
9185 | case 'H': |
9186 | case 'W': | |
9187 | case 'D': | |
9188 | case 'j': | |
9189 | case '8': | |
9190 | case 'V': | |
9191 | case 'C': | |
9192 | case 'U': | |
9193 | case 'k': | |
9194 | case 'K': | |
9195 | case 'p': | |
9196 | case 'q': | |
9197 | { | |
b886a2ab RS |
9198 | offsetT value; |
9199 | ||
9c2799c2 | 9200 | gas_assert (ep != NULL); |
252b5132 RH |
9201 | |
9202 | if (ep->X_op != O_constant) | |
874e8986 | 9203 | *r = (int) BFD_RELOC_UNUSED + c; |
b886a2ab | 9204 | else if (calculate_reloc (*r, ep->X_add_number, &value)) |
252b5132 | 9205 | { |
b886a2ab | 9206 | mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode); |
252b5132 | 9207 | ep = NULL; |
f6688943 | 9208 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
9209 | } |
9210 | } | |
e077a1c8 | 9211 | break; |
252b5132 | 9212 | |
e077a1c8 RS |
9213 | default: |
9214 | operand = decode_mips16_operand (c, FALSE); | |
9215 | if (!operand) | |
9216 | abort (); | |
252b5132 | 9217 | |
4a06e5a2 | 9218 | insn_insert_operand (&insn, operand, va_arg (*args, int)); |
e077a1c8 RS |
9219 | break; |
9220 | } | |
252b5132 RH |
9221 | } |
9222 | ||
9c2799c2 | 9223 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 9224 | |
df58fc94 | 9225 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
9226 | } |
9227 | ||
438c16b8 TS |
9228 | /* |
9229 | * Generate a "jalr" instruction with a relocation hint to the called | |
9230 | * function. This occurs in NewABI PIC code. | |
9231 | */ | |
9232 | static void | |
df58fc94 | 9233 | macro_build_jalr (expressionS *ep, int cprestore) |
438c16b8 | 9234 | { |
df58fc94 RS |
9235 | static const bfd_reloc_code_real_type jalr_relocs[2] |
9236 | = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR }; | |
9237 | bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips]; | |
9238 | const char *jalr; | |
685736be | 9239 | char *f = NULL; |
b34976b6 | 9240 | |
1180b5a4 | 9241 | if (MIPS_JALR_HINT_P (ep)) |
f21f8242 | 9242 | { |
cc3d92a5 | 9243 | frag_grow (8); |
f21f8242 AO |
9244 | f = frag_more (0); |
9245 | } | |
2906b037 | 9246 | if (mips_opts.micromips) |
df58fc94 | 9247 | { |
833794fc MR |
9248 | jalr = ((mips_opts.noreorder && !cprestore) || mips_opts.insn32 |
9249 | ? "jalr" : "jalrs"); | |
e64af278 | 9250 | if (MIPS_JALR_HINT_P (ep) |
833794fc | 9251 | || mips_opts.insn32 |
e64af278 | 9252 | || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
df58fc94 RS |
9253 | macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG); |
9254 | else | |
9255 | macro_build (NULL, jalr, "mj", PIC_CALL_REG); | |
9256 | } | |
2906b037 MR |
9257 | else |
9258 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); | |
1180b5a4 | 9259 | if (MIPS_JALR_HINT_P (ep)) |
df58fc94 | 9260 | fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc); |
438c16b8 TS |
9261 | } |
9262 | ||
252b5132 RH |
9263 | /* |
9264 | * Generate a "lui" instruction. | |
9265 | */ | |
9266 | static void | |
67c0d1eb | 9267 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 | 9268 | { |
9c2799c2 | 9269 | gas_assert (! mips_opts.mips16); |
252b5132 | 9270 | |
df58fc94 | 9271 | if (ep->X_op != O_constant) |
252b5132 | 9272 | { |
9c2799c2 | 9273 | gas_assert (ep->X_op == O_symbol); |
bbe506e8 TS |
9274 | /* _gp_disp is a special case, used from s_cpload. |
9275 | __gnu_local_gp is used if mips_no_shared. */ | |
9c2799c2 | 9276 | gas_assert (mips_pic == NO_PIC |
78e1bb40 | 9277 | || (! HAVE_NEWABI |
aa6975fb ILT |
9278 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
9279 | || (! mips_in_shared | |
bbe506e8 TS |
9280 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
9281 | "__gnu_local_gp") == 0)); | |
252b5132 RH |
9282 | } |
9283 | ||
df58fc94 | 9284 | macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S); |
252b5132 RH |
9285 | } |
9286 | ||
885add95 CD |
9287 | /* Generate a sequence of instructions to do a load or store from a constant |
9288 | offset off of a base register (breg) into/from a target register (treg), | |
9289 | using AT if necessary. */ | |
9290 | static void | |
67c0d1eb RS |
9291 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
9292 | int treg, int breg, int dbl) | |
885add95 | 9293 | { |
9c2799c2 | 9294 | gas_assert (ep->X_op == O_constant); |
885add95 | 9295 | |
256ab948 | 9296 | /* Sign-extending 32-bit constants makes their handling easier. */ |
2051e8c4 MR |
9297 | if (!dbl) |
9298 | normalize_constant_expr (ep); | |
256ab948 | 9299 | |
67c1ffbe | 9300 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 9301 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
9302 | as_warn (_("operand overflow")); |
9303 | ||
9304 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
9305 | { | |
9306 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 9307 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
9308 | } |
9309 | else | |
9310 | { | |
9311 | /* 32-bit offset, need multiple instructions and AT, like: | |
9312 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
9313 | addu $tempreg,$tempreg,$breg | |
9314 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
9315 | to handle the complete offset. */ | |
67c0d1eb RS |
9316 | macro_build_lui (ep, AT); |
9317 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
9318 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 | 9319 | |
741fe287 | 9320 | if (!mips_opts.at) |
1661c76c | 9321 | as_bad (_("macro used $at after \".set noat\"")); |
885add95 CD |
9322 | } |
9323 | } | |
9324 | ||
252b5132 RH |
9325 | /* set_at() |
9326 | * Generates code to set the $at register to true (one) | |
9327 | * if reg is less than the immediate expression. | |
9328 | */ | |
9329 | static void | |
67c0d1eb | 9330 | set_at (int reg, int unsignedp) |
252b5132 | 9331 | { |
b0e6f033 | 9332 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 | 9333 | && imm_expr.X_add_number < 0x8000) |
67c0d1eb RS |
9334 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
9335 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
9336 | else |
9337 | { | |
bad1aba3 | 9338 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
67c0d1eb | 9339 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); |
252b5132 RH |
9340 | } |
9341 | } | |
9342 | ||
252b5132 RH |
9343 | /* Count the leading zeroes by performing a binary chop. This is a |
9344 | bulky bit of source, but performance is a LOT better for the | |
9345 | majority of values than a simple loop to count the bits: | |
9346 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
9347 | if ((v) & (1 << (31 - lcnt))) | |
9348 | break; | |
9349 | However it is not code size friendly, and the gain will drop a bit | |
9350 | on certain cached systems. | |
9351 | */ | |
9352 | #define COUNT_TOP_ZEROES(v) \ | |
9353 | (((v) & ~0xffff) == 0 \ | |
9354 | ? ((v) & ~0xff) == 0 \ | |
9355 | ? ((v) & ~0xf) == 0 \ | |
9356 | ? ((v) & ~0x3) == 0 \ | |
9357 | ? ((v) & ~0x1) == 0 \ | |
9358 | ? !(v) \ | |
9359 | ? 32 \ | |
9360 | : 31 \ | |
9361 | : 30 \ | |
9362 | : ((v) & ~0x7) == 0 \ | |
9363 | ? 29 \ | |
9364 | : 28 \ | |
9365 | : ((v) & ~0x3f) == 0 \ | |
9366 | ? ((v) & ~0x1f) == 0 \ | |
9367 | ? 27 \ | |
9368 | : 26 \ | |
9369 | : ((v) & ~0x7f) == 0 \ | |
9370 | ? 25 \ | |
9371 | : 24 \ | |
9372 | : ((v) & ~0xfff) == 0 \ | |
9373 | ? ((v) & ~0x3ff) == 0 \ | |
9374 | ? ((v) & ~0x1ff) == 0 \ | |
9375 | ? 23 \ | |
9376 | : 22 \ | |
9377 | : ((v) & ~0x7ff) == 0 \ | |
9378 | ? 21 \ | |
9379 | : 20 \ | |
9380 | : ((v) & ~0x3fff) == 0 \ | |
9381 | ? ((v) & ~0x1fff) == 0 \ | |
9382 | ? 19 \ | |
9383 | : 18 \ | |
9384 | : ((v) & ~0x7fff) == 0 \ | |
9385 | ? 17 \ | |
9386 | : 16 \ | |
9387 | : ((v) & ~0xffffff) == 0 \ | |
9388 | ? ((v) & ~0xfffff) == 0 \ | |
9389 | ? ((v) & ~0x3ffff) == 0 \ | |
9390 | ? ((v) & ~0x1ffff) == 0 \ | |
9391 | ? 15 \ | |
9392 | : 14 \ | |
9393 | : ((v) & ~0x7ffff) == 0 \ | |
9394 | ? 13 \ | |
9395 | : 12 \ | |
9396 | : ((v) & ~0x3fffff) == 0 \ | |
9397 | ? ((v) & ~0x1fffff) == 0 \ | |
9398 | ? 11 \ | |
9399 | : 10 \ | |
9400 | : ((v) & ~0x7fffff) == 0 \ | |
9401 | ? 9 \ | |
9402 | : 8 \ | |
9403 | : ((v) & ~0xfffffff) == 0 \ | |
9404 | ? ((v) & ~0x3ffffff) == 0 \ | |
9405 | ? ((v) & ~0x1ffffff) == 0 \ | |
9406 | ? 7 \ | |
9407 | : 6 \ | |
9408 | : ((v) & ~0x7ffffff) == 0 \ | |
9409 | ? 5 \ | |
9410 | : 4 \ | |
9411 | : ((v) & ~0x3fffffff) == 0 \ | |
9412 | ? ((v) & ~0x1fffffff) == 0 \ | |
9413 | ? 3 \ | |
9414 | : 2 \ | |
9415 | : ((v) & ~0x7fffffff) == 0 \ | |
9416 | ? 1 \ | |
9417 | : 0) | |
9418 | ||
9419 | /* load_register() | |
67c1ffbe | 9420 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
9421 | * an absolute expression value into a register. |
9422 | */ | |
9423 | static void | |
67c0d1eb | 9424 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
9425 | { |
9426 | int freg; | |
9427 | expressionS hi32, lo32; | |
9428 | ||
9429 | if (ep->X_op != O_big) | |
9430 | { | |
9c2799c2 | 9431 | gas_assert (ep->X_op == O_constant); |
256ab948 TS |
9432 | |
9433 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
2051e8c4 MR |
9434 | if (!dbl) |
9435 | normalize_constant_expr (ep); | |
256ab948 TS |
9436 | |
9437 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
9438 | { |
9439 | /* We can handle 16 bit signed values with an addiu to | |
9440 | $zero. No need to ever use daddiu here, since $zero and | |
9441 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 9442 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
9443 | return; |
9444 | } | |
9445 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
9446 | { | |
9447 | /* We can handle 16 bit unsigned values with an ori to | |
9448 | $zero. */ | |
67c0d1eb | 9449 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
9450 | return; |
9451 | } | |
256ab948 | 9452 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
9453 | { |
9454 | /* 32 bit values require an lui. */ | |
df58fc94 | 9455 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 9456 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 9457 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
9458 | return; |
9459 | } | |
9460 | } | |
9461 | ||
9462 | /* The value is larger than 32 bits. */ | |
9463 | ||
bad1aba3 | 9464 | if (!dbl || GPR_SIZE == 32) |
252b5132 | 9465 | { |
55e08f71 NC |
9466 | char value[32]; |
9467 | ||
9468 | sprintf_vma (value, ep->X_add_number); | |
1661c76c | 9469 | as_bad (_("number (0x%s) larger than 32 bits"), value); |
67c0d1eb | 9470 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
9471 | return; |
9472 | } | |
9473 | ||
9474 | if (ep->X_op != O_big) | |
9475 | { | |
9476 | hi32 = *ep; | |
9477 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
9478 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
9479 | hi32.X_add_number &= 0xffffffff; | |
9480 | lo32 = *ep; | |
9481 | lo32.X_add_number &= 0xffffffff; | |
9482 | } | |
9483 | else | |
9484 | { | |
9c2799c2 | 9485 | gas_assert (ep->X_add_number > 2); |
252b5132 RH |
9486 | if (ep->X_add_number == 3) |
9487 | generic_bignum[3] = 0; | |
9488 | else if (ep->X_add_number > 4) | |
1661c76c | 9489 | as_bad (_("number larger than 64 bits")); |
252b5132 RH |
9490 | lo32.X_op = O_constant; |
9491 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
9492 | hi32.X_op = O_constant; | |
9493 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
9494 | } | |
9495 | ||
9496 | if (hi32.X_add_number == 0) | |
9497 | freg = 0; | |
9498 | else | |
9499 | { | |
9500 | int shift, bit; | |
9501 | unsigned long hi, lo; | |
9502 | ||
956cd1d6 | 9503 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
9504 | { |
9505 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
9506 | { | |
67c0d1eb | 9507 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
9508 | return; |
9509 | } | |
9510 | if (lo32.X_add_number & 0x80000000) | |
9511 | { | |
df58fc94 | 9512 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 9513 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 9514 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
9515 | return; |
9516 | } | |
9517 | } | |
252b5132 RH |
9518 | |
9519 | /* Check for 16bit shifted constant. We know that hi32 is | |
9520 | non-zero, so start the mask on the first bit of the hi32 | |
9521 | value. */ | |
9522 | shift = 17; | |
9523 | do | |
beae10d5 KH |
9524 | { |
9525 | unsigned long himask, lomask; | |
9526 | ||
9527 | if (shift < 32) | |
9528 | { | |
9529 | himask = 0xffff >> (32 - shift); | |
9530 | lomask = (0xffff << shift) & 0xffffffff; | |
9531 | } | |
9532 | else | |
9533 | { | |
9534 | himask = 0xffff << (shift - 32); | |
9535 | lomask = 0; | |
9536 | } | |
9537 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
9538 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
9539 | { | |
9540 | expressionS tmp; | |
9541 | ||
9542 | tmp.X_op = O_constant; | |
9543 | if (shift < 32) | |
9544 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
9545 | | (lo32.X_add_number >> shift)); | |
9546 | else | |
9547 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb | 9548 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
df58fc94 | 9549 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 9550 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
9551 | return; |
9552 | } | |
f9419b05 | 9553 | ++shift; |
beae10d5 KH |
9554 | } |
9555 | while (shift <= (64 - 16)); | |
252b5132 RH |
9556 | |
9557 | /* Find the bit number of the lowest one bit, and store the | |
9558 | shifted value in hi/lo. */ | |
9559 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
9560 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
9561 | if (lo != 0) | |
9562 | { | |
9563 | bit = 0; | |
9564 | while ((lo & 1) == 0) | |
9565 | { | |
9566 | lo >>= 1; | |
9567 | ++bit; | |
9568 | } | |
9569 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
9570 | hi >>= bit; | |
9571 | } | |
9572 | else | |
9573 | { | |
9574 | bit = 32; | |
9575 | while ((hi & 1) == 0) | |
9576 | { | |
9577 | hi >>= 1; | |
9578 | ++bit; | |
9579 | } | |
9580 | lo = hi; | |
9581 | hi = 0; | |
9582 | } | |
9583 | ||
9584 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
9585 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
9586 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
9587 | { |
9588 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 9589 | if (shift != 0) |
beae10d5 | 9590 | { |
252b5132 RH |
9591 | expressionS tmp; |
9592 | ||
9593 | /* This instruction will set the register to be all | |
9594 | ones. */ | |
beae10d5 KH |
9595 | tmp.X_op = O_constant; |
9596 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 9597 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
9598 | if (bit != 0) |
9599 | { | |
9600 | bit += shift; | |
df58fc94 | 9601 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 9602 | reg, reg, (bit >= 32) ? bit - 32 : bit); |
beae10d5 | 9603 | } |
df58fc94 | 9604 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT, |
67c0d1eb | 9605 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
9606 | return; |
9607 | } | |
9608 | } | |
252b5132 RH |
9609 | |
9610 | /* Sign extend hi32 before calling load_register, because we can | |
9611 | generally get better code when we load a sign extended value. */ | |
9612 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 9613 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 9614 | load_register (reg, &hi32, 0); |
252b5132 RH |
9615 | freg = reg; |
9616 | } | |
9617 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
9618 | { | |
9619 | if (freg != 0) | |
9620 | { | |
df58fc94 | 9621 | macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0); |
252b5132 RH |
9622 | freg = reg; |
9623 | } | |
9624 | } | |
9625 | else | |
9626 | { | |
9627 | expressionS mid16; | |
9628 | ||
956cd1d6 | 9629 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 9630 | { |
df58fc94 RS |
9631 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
9632 | macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0); | |
beae10d5 KH |
9633 | return; |
9634 | } | |
252b5132 RH |
9635 | |
9636 | if (freg != 0) | |
9637 | { | |
df58fc94 | 9638 | macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16); |
252b5132 RH |
9639 | freg = reg; |
9640 | } | |
9641 | mid16 = lo32; | |
9642 | mid16.X_add_number >>= 16; | |
67c0d1eb | 9643 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
df58fc94 | 9644 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
252b5132 RH |
9645 | freg = reg; |
9646 | } | |
9647 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 9648 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
9649 | } |
9650 | ||
269137b2 TS |
9651 | static inline void |
9652 | load_delay_nop (void) | |
9653 | { | |
9654 | if (!gpr_interlocks) | |
9655 | macro_build (NULL, "nop", ""); | |
9656 | } | |
9657 | ||
252b5132 RH |
9658 | /* Load an address into a register. */ |
9659 | ||
9660 | static void | |
67c0d1eb | 9661 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 9662 | { |
252b5132 RH |
9663 | if (ep->X_op != O_constant |
9664 | && ep->X_op != O_symbol) | |
9665 | { | |
9666 | as_bad (_("expression too complex")); | |
9667 | ep->X_op = O_constant; | |
9668 | } | |
9669 | ||
9670 | if (ep->X_op == O_constant) | |
9671 | { | |
67c0d1eb | 9672 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
9673 | return; |
9674 | } | |
9675 | ||
9676 | if (mips_pic == NO_PIC) | |
9677 | { | |
9678 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 9679 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
9680 | Otherwise we want |
9681 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
9682 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 9683 | If we have an addend, we always use the latter form. |
76b3015f | 9684 | |
d6bc6245 TS |
9685 | With 64bit address space and a usable $at we want |
9686 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
9687 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
9688 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
9689 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
9690 | dsll32 $reg,0 | |
3a482fd5 | 9691 | daddu $reg,$reg,$at |
76b3015f | 9692 | |
c03099e6 | 9693 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
9694 | on superscalar processors. |
9695 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
9696 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
9697 | dsll $reg,16 | |
9698 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
9699 | dsll $reg,16 | |
9700 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
6caf9ef4 TS |
9701 | |
9702 | For GP relative symbols in 64bit address space we can use | |
9703 | the same sequence as in 32bit address space. */ | |
aed1a261 | 9704 | if (HAVE_64BIT_SYMBOLS) |
d6bc6245 | 9705 | { |
6caf9ef4 TS |
9706 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
9707 | && !nopic_need_relax (ep->X_add_symbol, 1)) | |
9708 | { | |
9709 | relax_start (ep->X_add_symbol); | |
9710 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
9711 | mips_gp_register, BFD_RELOC_GPREL16); | |
9712 | relax_switch (); | |
9713 | } | |
d6bc6245 | 9714 | |
741fe287 | 9715 | if (*used_at == 0 && mips_opts.at) |
d6bc6245 | 9716 | { |
df58fc94 RS |
9717 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
9718 | macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S); | |
67c0d1eb RS |
9719 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
9720 | BFD_RELOC_MIPS_HIGHER); | |
9721 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
df58fc94 | 9722 | macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0); |
67c0d1eb | 9723 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); |
d6bc6245 TS |
9724 | *used_at = 1; |
9725 | } | |
9726 | else | |
9727 | { | |
df58fc94 | 9728 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb RS |
9729 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
9730 | BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 9731 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 9732 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); |
df58fc94 | 9733 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 9734 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); |
d6bc6245 | 9735 | } |
6caf9ef4 TS |
9736 | |
9737 | if (mips_relax.sequence) | |
9738 | relax_end (); | |
d6bc6245 | 9739 | } |
252b5132 RH |
9740 | else |
9741 | { | |
d6bc6245 | 9742 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 9743 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
d6bc6245 | 9744 | { |
4d7206a2 | 9745 | relax_start (ep->X_add_symbol); |
67c0d1eb | 9746 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 9747 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 9748 | relax_switch (); |
d6bc6245 | 9749 | } |
67c0d1eb RS |
9750 | macro_build_lui (ep, reg); |
9751 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
9752 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
9753 | if (mips_relax.sequence) |
9754 | relax_end (); | |
d6bc6245 | 9755 | } |
252b5132 | 9756 | } |
0a44bf69 | 9757 | else if (!mips_big_got) |
252b5132 RH |
9758 | { |
9759 | expressionS ex; | |
9760 | ||
9761 | /* If this is a reference to an external symbol, we want | |
9762 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9763 | Otherwise we want | |
9764 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9765 | nop | |
9766 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
9767 | If there is a constant, it must be added in after. |
9768 | ||
ed6fb7bd | 9769 | If we have NewABI, we want |
f5040a92 AO |
9770 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
9771 | unless we're referencing a global symbol with a non-zero | |
9772 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
9773 | if (HAVE_NEWABI) |
9774 | { | |
f5040a92 AO |
9775 | if (ep->X_add_number) |
9776 | { | |
4d7206a2 | 9777 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 9778 | ep->X_add_number = 0; |
4d7206a2 | 9779 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
9780 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
9781 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
9782 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
9783 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
9784 | ex.X_op = O_constant; | |
67c0d1eb | 9785 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 9786 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 9787 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 9788 | relax_switch (); |
f5040a92 | 9789 | } |
67c0d1eb | 9790 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 9791 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
9792 | if (mips_relax.sequence) |
9793 | relax_end (); | |
ed6fb7bd SC |
9794 | } |
9795 | else | |
9796 | { | |
f5040a92 AO |
9797 | ex.X_add_number = ep->X_add_number; |
9798 | ep->X_add_number = 0; | |
67c0d1eb RS |
9799 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
9800 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 9801 | load_delay_nop (); |
4d7206a2 RS |
9802 | relax_start (ep->X_add_symbol); |
9803 | relax_switch (); | |
67c0d1eb | 9804 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 9805 | BFD_RELOC_LO16); |
4d7206a2 | 9806 | relax_end (); |
ed6fb7bd | 9807 | |
f5040a92 AO |
9808 | if (ex.X_add_number != 0) |
9809 | { | |
9810 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
9811 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
9812 | ex.X_op = O_constant; | |
67c0d1eb | 9813 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 9814 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 9815 | } |
252b5132 RH |
9816 | } |
9817 | } | |
0a44bf69 | 9818 | else if (mips_big_got) |
252b5132 RH |
9819 | { |
9820 | expressionS ex; | |
252b5132 RH |
9821 | |
9822 | /* This is the large GOT case. If this is a reference to an | |
9823 | external symbol, we want | |
9824 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
9825 | addu $reg,$reg,$gp | |
9826 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
9827 | |
9828 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
9829 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
9830 | nop | |
9831 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 9832 | If there is a constant, it must be added in after. |
f5040a92 AO |
9833 | |
9834 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
9835 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
9836 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 9837 | */ |
438c16b8 TS |
9838 | if (HAVE_NEWABI) |
9839 | { | |
4d7206a2 | 9840 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 9841 | ep->X_add_number = 0; |
4d7206a2 | 9842 | relax_start (ep->X_add_symbol); |
df58fc94 | 9843 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
9844 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
9845 | reg, reg, mips_gp_register); | |
9846 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
9847 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
9848 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
9849 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
9850 | else if (ex.X_add_number) | |
9851 | { | |
9852 | ex.X_op = O_constant; | |
67c0d1eb RS |
9853 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
9854 | BFD_RELOC_LO16); | |
f5040a92 AO |
9855 | } |
9856 | ||
9857 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 9858 | relax_switch (); |
67c0d1eb | 9859 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 9860 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
9861 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
9862 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 9863 | relax_end (); |
438c16b8 | 9864 | } |
252b5132 | 9865 | else |
438c16b8 | 9866 | { |
f5040a92 AO |
9867 | ex.X_add_number = ep->X_add_number; |
9868 | ep->X_add_number = 0; | |
4d7206a2 | 9869 | relax_start (ep->X_add_symbol); |
df58fc94 | 9870 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
9871 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
9872 | reg, reg, mips_gp_register); | |
9873 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
9874 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
9875 | relax_switch (); |
9876 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
9877 | { |
9878 | /* We need a nop before loading from $gp. This special | |
9879 | check is required because the lui which starts the main | |
9880 | instruction stream does not refer to $gp, and so will not | |
9881 | insert the nop which may be required. */ | |
67c0d1eb | 9882 | macro_build (NULL, "nop", ""); |
438c16b8 | 9883 | } |
67c0d1eb | 9884 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 9885 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 9886 | load_delay_nop (); |
67c0d1eb | 9887 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 9888 | BFD_RELOC_LO16); |
4d7206a2 | 9889 | relax_end (); |
438c16b8 | 9890 | |
f5040a92 AO |
9891 | if (ex.X_add_number != 0) |
9892 | { | |
9893 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
9894 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
9895 | ex.X_op = O_constant; | |
67c0d1eb RS |
9896 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
9897 | BFD_RELOC_LO16); | |
f5040a92 | 9898 | } |
252b5132 RH |
9899 | } |
9900 | } | |
252b5132 RH |
9901 | else |
9902 | abort (); | |
8fc2e39e | 9903 | |
741fe287 | 9904 | if (!mips_opts.at && *used_at == 1) |
1661c76c | 9905 | as_bad (_("macro used $at after \".set noat\"")); |
252b5132 RH |
9906 | } |
9907 | ||
ea1fb5dc RS |
9908 | /* Move the contents of register SOURCE into register DEST. */ |
9909 | ||
9910 | static void | |
67c0d1eb | 9911 | move_register (int dest, int source) |
ea1fb5dc | 9912 | { |
df58fc94 RS |
9913 | /* Prefer to use a 16-bit microMIPS instruction unless the previous |
9914 | instruction specifically requires a 32-bit one. */ | |
9915 | if (mips_opts.micromips | |
833794fc | 9916 | && !mips_opts.insn32 |
df58fc94 | 9917 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
7951ca42 | 9918 | macro_build (NULL, "move", "mp,mj", dest, source); |
df58fc94 | 9919 | else |
40fc1451 | 9920 | macro_build (NULL, "or", "d,v,t", dest, source, 0); |
ea1fb5dc RS |
9921 | } |
9922 | ||
4d7206a2 | 9923 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
9924 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
9925 | The two alternatives are: | |
4d7206a2 | 9926 | |
33eaf5de | 9927 | Global symbol Local symbol |
4d7206a2 RS |
9928 | ------------- ------------ |
9929 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
9930 | ... ... | |
9931 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
9932 | ||
9933 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
9934 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
9935 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
9936 | |
9937 | static void | |
67c0d1eb | 9938 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
9939 | { |
9940 | expressionS global; | |
9941 | ||
9942 | global = *local; | |
9943 | global.X_add_number = 0; | |
9944 | ||
9945 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
9946 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
9947 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 9948 | relax_switch (); |
67c0d1eb RS |
9949 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
9950 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
9951 | relax_end (); |
9952 | } | |
9953 | ||
9954 | static void | |
67c0d1eb | 9955 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
9956 | { |
9957 | expressionS global; | |
9958 | ||
9959 | global.X_op = O_constant; | |
9960 | global.X_op_symbol = NULL; | |
9961 | global.X_add_symbol = NULL; | |
9962 | global.X_add_number = local->X_add_number; | |
9963 | ||
9964 | relax_start (local->X_add_symbol); | |
67c0d1eb | 9965 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
9966 | dest, dest, BFD_RELOC_LO16); |
9967 | relax_switch (); | |
67c0d1eb | 9968 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
9969 | relax_end (); |
9970 | } | |
9971 | ||
f6a22291 MR |
9972 | static void |
9973 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
9974 | { | |
9975 | expressionS global; | |
9976 | int hold_mips_optimize; | |
9977 | ||
9978 | global.X_op = O_constant; | |
9979 | global.X_op_symbol = NULL; | |
9980 | global.X_add_symbol = NULL; | |
9981 | global.X_add_number = local->X_add_number; | |
9982 | ||
9983 | relax_start (local->X_add_symbol); | |
9984 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
9985 | relax_switch (); | |
9986 | /* Set mips_optimize around the lui instruction to avoid | |
9987 | inserting an unnecessary nop after the lw. */ | |
9988 | hold_mips_optimize = mips_optimize; | |
9989 | mips_optimize = 2; | |
9990 | macro_build_lui (&global, tmp); | |
9991 | mips_optimize = hold_mips_optimize; | |
9992 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
9993 | relax_end (); | |
9994 | ||
9995 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
9996 | } | |
9997 | ||
df58fc94 RS |
9998 | /* Emit a sequence of instructions to emulate a branch likely operation. |
9999 | BR is an ordinary branch corresponding to one to be emulated. BRNEG | |
10000 | is its complementing branch with the original condition negated. | |
10001 | CALL is set if the original branch specified the link operation. | |
10002 | EP, FMT, SREG and TREG specify the usual macro_build() parameters. | |
10003 | ||
10004 | Code like this is produced in the noreorder mode: | |
10005 | ||
10006 | BRNEG <args>, 1f | |
10007 | nop | |
10008 | b <sym> | |
10009 | delay slot (executed only if branch taken) | |
10010 | 1: | |
10011 | ||
10012 | or, if CALL is set: | |
10013 | ||
10014 | BRNEG <args>, 1f | |
10015 | nop | |
10016 | bal <sym> | |
10017 | delay slot (executed only if branch taken) | |
10018 | 1: | |
10019 | ||
10020 | In the reorder mode the delay slot would be filled with a nop anyway, | |
10021 | so code produced is simply: | |
10022 | ||
10023 | BR <args>, <sym> | |
10024 | nop | |
10025 | ||
10026 | This function is used when producing code for the microMIPS ASE that | |
10027 | does not implement branch likely instructions in hardware. */ | |
10028 | ||
10029 | static void | |
10030 | macro_build_branch_likely (const char *br, const char *brneg, | |
10031 | int call, expressionS *ep, const char *fmt, | |
10032 | unsigned int sreg, unsigned int treg) | |
10033 | { | |
10034 | int noreorder = mips_opts.noreorder; | |
10035 | expressionS expr1; | |
10036 | ||
10037 | gas_assert (mips_opts.micromips); | |
10038 | start_noreorder (); | |
10039 | if (noreorder) | |
10040 | { | |
10041 | micromips_label_expr (&expr1); | |
10042 | macro_build (&expr1, brneg, fmt, sreg, treg); | |
10043 | macro_build (NULL, "nop", ""); | |
10044 | macro_build (ep, call ? "bal" : "b", "p"); | |
10045 | ||
10046 | /* Set to true so that append_insn adds a label. */ | |
10047 | emit_branch_likely_macro = TRUE; | |
10048 | } | |
10049 | else | |
10050 | { | |
10051 | macro_build (ep, br, fmt, sreg, treg); | |
10052 | macro_build (NULL, "nop", ""); | |
10053 | } | |
10054 | end_noreorder (); | |
10055 | } | |
10056 | ||
10057 | /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as | |
10058 | the condition code tested. EP specifies the branch target. */ | |
10059 | ||
10060 | static void | |
10061 | macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc) | |
10062 | { | |
10063 | const int call = 0; | |
10064 | const char *brneg; | |
10065 | const char *br; | |
10066 | ||
10067 | switch (type) | |
10068 | { | |
10069 | case M_BC1FL: | |
10070 | br = "bc1f"; | |
10071 | brneg = "bc1t"; | |
10072 | break; | |
10073 | case M_BC1TL: | |
10074 | br = "bc1t"; | |
10075 | brneg = "bc1f"; | |
10076 | break; | |
10077 | case M_BC2FL: | |
10078 | br = "bc2f"; | |
10079 | brneg = "bc2t"; | |
10080 | break; | |
10081 | case M_BC2TL: | |
10082 | br = "bc2t"; | |
10083 | brneg = "bc2f"; | |
10084 | break; | |
10085 | default: | |
10086 | abort (); | |
10087 | } | |
10088 | macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO); | |
10089 | } | |
10090 | ||
10091 | /* Emit a two-argument branch macro specified by TYPE, using SREG as | |
10092 | the register tested. EP specifies the branch target. */ | |
10093 | ||
10094 | static void | |
10095 | macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg) | |
10096 | { | |
10097 | const char *brneg = NULL; | |
10098 | const char *br; | |
10099 | int call = 0; | |
10100 | ||
10101 | switch (type) | |
10102 | { | |
10103 | case M_BGEZ: | |
10104 | br = "bgez"; | |
10105 | break; | |
10106 | case M_BGEZL: | |
10107 | br = mips_opts.micromips ? "bgez" : "bgezl"; | |
10108 | brneg = "bltz"; | |
10109 | break; | |
10110 | case M_BGEZALL: | |
10111 | gas_assert (mips_opts.micromips); | |
833794fc | 10112 | br = mips_opts.insn32 ? "bgezal" : "bgezals"; |
df58fc94 RS |
10113 | brneg = "bltz"; |
10114 | call = 1; | |
10115 | break; | |
10116 | case M_BGTZ: | |
10117 | br = "bgtz"; | |
10118 | break; | |
10119 | case M_BGTZL: | |
10120 | br = mips_opts.micromips ? "bgtz" : "bgtzl"; | |
10121 | brneg = "blez"; | |
10122 | break; | |
10123 | case M_BLEZ: | |
10124 | br = "blez"; | |
10125 | break; | |
10126 | case M_BLEZL: | |
10127 | br = mips_opts.micromips ? "blez" : "blezl"; | |
10128 | brneg = "bgtz"; | |
10129 | break; | |
10130 | case M_BLTZ: | |
10131 | br = "bltz"; | |
10132 | break; | |
10133 | case M_BLTZL: | |
10134 | br = mips_opts.micromips ? "bltz" : "bltzl"; | |
10135 | brneg = "bgez"; | |
10136 | break; | |
10137 | case M_BLTZALL: | |
10138 | gas_assert (mips_opts.micromips); | |
833794fc | 10139 | br = mips_opts.insn32 ? "bltzal" : "bltzals"; |
df58fc94 RS |
10140 | brneg = "bgez"; |
10141 | call = 1; | |
10142 | break; | |
10143 | default: | |
10144 | abort (); | |
10145 | } | |
10146 | if (mips_opts.micromips && brneg) | |
10147 | macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO); | |
10148 | else | |
10149 | macro_build (ep, br, "s,p", sreg); | |
10150 | } | |
10151 | ||
10152 | /* Emit a three-argument branch macro specified by TYPE, using SREG and | |
10153 | TREG as the registers tested. EP specifies the branch target. */ | |
10154 | ||
10155 | static void | |
10156 | macro_build_branch_rsrt (int type, expressionS *ep, | |
10157 | unsigned int sreg, unsigned int treg) | |
10158 | { | |
10159 | const char *brneg = NULL; | |
10160 | const int call = 0; | |
10161 | const char *br; | |
10162 | ||
10163 | switch (type) | |
10164 | { | |
10165 | case M_BEQ: | |
10166 | case M_BEQ_I: | |
10167 | br = "beq"; | |
10168 | break; | |
10169 | case M_BEQL: | |
10170 | case M_BEQL_I: | |
10171 | br = mips_opts.micromips ? "beq" : "beql"; | |
10172 | brneg = "bne"; | |
10173 | break; | |
10174 | case M_BNE: | |
10175 | case M_BNE_I: | |
10176 | br = "bne"; | |
10177 | break; | |
10178 | case M_BNEL: | |
10179 | case M_BNEL_I: | |
10180 | br = mips_opts.micromips ? "bne" : "bnel"; | |
10181 | brneg = "beq"; | |
10182 | break; | |
10183 | default: | |
10184 | abort (); | |
10185 | } | |
10186 | if (mips_opts.micromips && brneg) | |
10187 | macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg); | |
10188 | else | |
10189 | macro_build (ep, br, "s,t,p", sreg, treg); | |
10190 | } | |
10191 | ||
f2ae14a1 RS |
10192 | /* Return the high part that should be loaded in order to make the low |
10193 | part of VALUE accessible using an offset of OFFBITS bits. */ | |
10194 | ||
10195 | static offsetT | |
10196 | offset_high_part (offsetT value, unsigned int offbits) | |
10197 | { | |
10198 | offsetT bias; | |
10199 | addressT low_mask; | |
10200 | ||
10201 | if (offbits == 0) | |
10202 | return value; | |
10203 | bias = 1 << (offbits - 1); | |
10204 | low_mask = bias * 2 - 1; | |
10205 | return (value + bias) & ~low_mask; | |
10206 | } | |
10207 | ||
10208 | /* Return true if the value stored in offset_expr and offset_reloc | |
10209 | fits into a signed offset of OFFBITS bits. RANGE is the maximum | |
10210 | amount that the caller wants to add without inducing overflow | |
10211 | and ALIGN is the known alignment of the value in bytes. */ | |
10212 | ||
10213 | static bfd_boolean | |
10214 | small_offset_p (unsigned int range, unsigned int align, unsigned int offbits) | |
10215 | { | |
10216 | if (offbits == 16) | |
10217 | { | |
10218 | /* Accept any relocation operator if overflow isn't a concern. */ | |
10219 | if (range < align && *offset_reloc != BFD_RELOC_UNUSED) | |
10220 | return TRUE; | |
10221 | ||
10222 | /* These relocations are guaranteed not to overflow in correct links. */ | |
10223 | if (*offset_reloc == BFD_RELOC_MIPS_LITERAL | |
10224 | || gprel16_reloc_p (*offset_reloc)) | |
10225 | return TRUE; | |
10226 | } | |
10227 | if (offset_expr.X_op == O_constant | |
10228 | && offset_high_part (offset_expr.X_add_number, offbits) == 0 | |
10229 | && offset_high_part (offset_expr.X_add_number + range, offbits) == 0) | |
10230 | return TRUE; | |
10231 | return FALSE; | |
10232 | } | |
10233 | ||
252b5132 RH |
10234 | /* |
10235 | * Build macros | |
10236 | * This routine implements the seemingly endless macro or synthesized | |
10237 | * instructions and addressing modes in the mips assembly language. Many | |
10238 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 10239 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
10240 | * this verbose method. Others are not simple macros but are more like |
10241 | * optimizing code generation. | |
10242 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 10243 | * consecutively that would load AT with the upper half of the same address. |
2b0f3761 | 10244 | * The ensuing load upper instructions are omitted. This implies some kind |
252b5132 RH |
10245 | * of global optimization. We currently only optimize within a single macro. |
10246 | * For many of the load and store macros if the address is specified as a | |
10247 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
10248 | * first load register 'at' with zero and use it as the base register. The | |
10249 | * mips assembler simply uses register $zero. Just one tiny optimization | |
10250 | * we're missing. | |
10251 | */ | |
10252 | static void | |
833794fc | 10253 | macro (struct mips_cl_insn *ip, char *str) |
252b5132 | 10254 | { |
c0ebe874 RS |
10255 | const struct mips_operand_array *operands; |
10256 | unsigned int breg, i; | |
741fe287 | 10257 | unsigned int tempreg; |
252b5132 | 10258 | int mask; |
43841e91 | 10259 | int used_at = 0; |
df58fc94 | 10260 | expressionS label_expr; |
252b5132 | 10261 | expressionS expr1; |
df58fc94 | 10262 | expressionS *ep; |
252b5132 RH |
10263 | const char *s; |
10264 | const char *s2; | |
10265 | const char *fmt; | |
10266 | int likely = 0; | |
252b5132 | 10267 | int coproc = 0; |
7f3c4072 | 10268 | int offbits = 16; |
1abe91b1 | 10269 | int call = 0; |
df58fc94 RS |
10270 | int jals = 0; |
10271 | int dbl = 0; | |
10272 | int imm = 0; | |
10273 | int ust = 0; | |
10274 | int lp = 0; | |
f2ae14a1 | 10275 | bfd_boolean large_offset; |
252b5132 | 10276 | int off; |
252b5132 | 10277 | int hold_mips_optimize; |
f2ae14a1 | 10278 | unsigned int align; |
c0ebe874 | 10279 | unsigned int op[MAX_OPERANDS]; |
252b5132 | 10280 | |
9c2799c2 | 10281 | gas_assert (! mips_opts.mips16); |
252b5132 | 10282 | |
c0ebe874 RS |
10283 | operands = insn_operands (ip); |
10284 | for (i = 0; i < MAX_OPERANDS; i++) | |
10285 | if (operands->operand[i]) | |
10286 | op[i] = insn_extract_operand (ip, operands->operand[i]); | |
10287 | else | |
10288 | op[i] = -1; | |
10289 | ||
252b5132 RH |
10290 | mask = ip->insn_mo->mask; |
10291 | ||
df58fc94 RS |
10292 | label_expr.X_op = O_constant; |
10293 | label_expr.X_op_symbol = NULL; | |
10294 | label_expr.X_add_symbol = NULL; | |
10295 | label_expr.X_add_number = 0; | |
10296 | ||
252b5132 RH |
10297 | expr1.X_op = O_constant; |
10298 | expr1.X_op_symbol = NULL; | |
10299 | expr1.X_add_symbol = NULL; | |
10300 | expr1.X_add_number = 1; | |
f2ae14a1 | 10301 | align = 1; |
252b5132 RH |
10302 | |
10303 | switch (mask) | |
10304 | { | |
10305 | case M_DABS: | |
10306 | dbl = 1; | |
1a0670f3 | 10307 | /* Fall through. */ |
252b5132 | 10308 | case M_ABS: |
df58fc94 RS |
10309 | /* bgez $a0,1f |
10310 | move v0,$a0 | |
10311 | sub v0,$zero,$a0 | |
10312 | 1: | |
10313 | */ | |
252b5132 | 10314 | |
7d10b47d | 10315 | start_noreorder (); |
252b5132 | 10316 | |
df58fc94 RS |
10317 | if (mips_opts.micromips) |
10318 | micromips_label_expr (&label_expr); | |
10319 | else | |
10320 | label_expr.X_add_number = 8; | |
c0ebe874 RS |
10321 | macro_build (&label_expr, "bgez", "s,p", op[1]); |
10322 | if (op[0] == op[1]) | |
a605d2b3 | 10323 | macro_build (NULL, "nop", ""); |
252b5132 | 10324 | else |
c0ebe874 RS |
10325 | move_register (op[0], op[1]); |
10326 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", op[0], 0, op[1]); | |
df58fc94 RS |
10327 | if (mips_opts.micromips) |
10328 | micromips_add_label (); | |
252b5132 | 10329 | |
7d10b47d | 10330 | end_noreorder (); |
8fc2e39e | 10331 | break; |
252b5132 RH |
10332 | |
10333 | case M_ADD_I: | |
10334 | s = "addi"; | |
10335 | s2 = "add"; | |
10336 | goto do_addi; | |
10337 | case M_ADDU_I: | |
10338 | s = "addiu"; | |
10339 | s2 = "addu"; | |
10340 | goto do_addi; | |
10341 | case M_DADD_I: | |
10342 | dbl = 1; | |
10343 | s = "daddi"; | |
10344 | s2 = "dadd"; | |
df58fc94 RS |
10345 | if (!mips_opts.micromips) |
10346 | goto do_addi; | |
b0e6f033 | 10347 | if (imm_expr.X_add_number >= -0x200 |
df58fc94 RS |
10348 | && imm_expr.X_add_number < 0x200) |
10349 | { | |
b0e6f033 RS |
10350 | macro_build (NULL, s, "t,r,.", op[0], op[1], |
10351 | (int) imm_expr.X_add_number); | |
df58fc94 RS |
10352 | break; |
10353 | } | |
10354 | goto do_addi_i; | |
252b5132 RH |
10355 | case M_DADDU_I: |
10356 | dbl = 1; | |
10357 | s = "daddiu"; | |
10358 | s2 = "daddu"; | |
10359 | do_addi: | |
b0e6f033 | 10360 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 RH |
10361 | && imm_expr.X_add_number < 0x8000) |
10362 | { | |
c0ebe874 | 10363 | macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
8fc2e39e | 10364 | break; |
252b5132 | 10365 | } |
df58fc94 | 10366 | do_addi_i: |
8fc2e39e | 10367 | used_at = 1; |
67c0d1eb | 10368 | load_register (AT, &imm_expr, dbl); |
c0ebe874 | 10369 | macro_build (NULL, s2, "d,v,t", op[0], op[1], AT); |
252b5132 RH |
10370 | break; |
10371 | ||
10372 | case M_AND_I: | |
10373 | s = "andi"; | |
10374 | s2 = "and"; | |
10375 | goto do_bit; | |
10376 | case M_OR_I: | |
10377 | s = "ori"; | |
10378 | s2 = "or"; | |
10379 | goto do_bit; | |
10380 | case M_NOR_I: | |
10381 | s = ""; | |
10382 | s2 = "nor"; | |
10383 | goto do_bit; | |
10384 | case M_XOR_I: | |
10385 | s = "xori"; | |
10386 | s2 = "xor"; | |
10387 | do_bit: | |
b0e6f033 | 10388 | if (imm_expr.X_add_number >= 0 |
252b5132 RH |
10389 | && imm_expr.X_add_number < 0x10000) |
10390 | { | |
10391 | if (mask != M_NOR_I) | |
c0ebe874 | 10392 | macro_build (&imm_expr, s, "t,r,i", op[0], op[1], BFD_RELOC_LO16); |
252b5132 RH |
10393 | else |
10394 | { | |
67c0d1eb | 10395 | macro_build (&imm_expr, "ori", "t,r,i", |
c0ebe874 RS |
10396 | op[0], op[1], BFD_RELOC_LO16); |
10397 | macro_build (NULL, "nor", "d,v,t", op[0], op[0], 0); | |
252b5132 | 10398 | } |
8fc2e39e | 10399 | break; |
252b5132 RH |
10400 | } |
10401 | ||
8fc2e39e | 10402 | used_at = 1; |
bad1aba3 | 10403 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 10404 | macro_build (NULL, s2, "d,v,t", op[0], op[1], AT); |
252b5132 RH |
10405 | break; |
10406 | ||
8b082fb1 TS |
10407 | case M_BALIGN: |
10408 | switch (imm_expr.X_add_number) | |
10409 | { | |
10410 | case 0: | |
10411 | macro_build (NULL, "nop", ""); | |
10412 | break; | |
10413 | case 2: | |
c0ebe874 | 10414 | macro_build (NULL, "packrl.ph", "d,s,t", op[0], op[0], op[1]); |
8b082fb1 | 10415 | break; |
03f66e8a MR |
10416 | case 1: |
10417 | case 3: | |
c0ebe874 | 10418 | macro_build (NULL, "balign", "t,s,2", op[0], op[1], |
90ecf173 | 10419 | (int) imm_expr.X_add_number); |
8b082fb1 | 10420 | break; |
03f66e8a MR |
10421 | default: |
10422 | as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"), | |
10423 | (unsigned long) imm_expr.X_add_number); | |
10424 | break; | |
8b082fb1 TS |
10425 | } |
10426 | break; | |
10427 | ||
df58fc94 RS |
10428 | case M_BC1FL: |
10429 | case M_BC1TL: | |
10430 | case M_BC2FL: | |
10431 | case M_BC2TL: | |
10432 | gas_assert (mips_opts.micromips); | |
10433 | macro_build_branch_ccl (mask, &offset_expr, | |
10434 | EXTRACT_OPERAND (1, BCC, *ip)); | |
10435 | break; | |
10436 | ||
252b5132 | 10437 | case M_BEQ_I: |
252b5132 | 10438 | case M_BEQL_I: |
252b5132 | 10439 | case M_BNE_I: |
252b5132 | 10440 | case M_BNEL_I: |
b0e6f033 | 10441 | if (imm_expr.X_add_number == 0) |
c0ebe874 | 10442 | op[1] = 0; |
df58fc94 | 10443 | else |
252b5132 | 10444 | { |
c0ebe874 | 10445 | op[1] = AT; |
df58fc94 | 10446 | used_at = 1; |
bad1aba3 | 10447 | load_register (op[1], &imm_expr, GPR_SIZE == 64); |
252b5132 | 10448 | } |
df58fc94 RS |
10449 | /* Fall through. */ |
10450 | case M_BEQL: | |
10451 | case M_BNEL: | |
c0ebe874 | 10452 | macro_build_branch_rsrt (mask, &offset_expr, op[0], op[1]); |
252b5132 RH |
10453 | break; |
10454 | ||
10455 | case M_BGEL: | |
10456 | likely = 1; | |
1a0670f3 | 10457 | /* Fall through. */ |
252b5132 | 10458 | case M_BGE: |
c0ebe874 RS |
10459 | if (op[1] == 0) |
10460 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[0]); | |
10461 | else if (op[0] == 0) | |
10462 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[1]); | |
df58fc94 | 10463 | else |
252b5132 | 10464 | { |
df58fc94 | 10465 | used_at = 1; |
c0ebe874 | 10466 | macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]); |
df58fc94 RS |
10467 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10468 | &offset_expr, AT, ZERO); | |
252b5132 | 10469 | } |
df58fc94 RS |
10470 | break; |
10471 | ||
10472 | case M_BGEZL: | |
10473 | case M_BGEZALL: | |
10474 | case M_BGTZL: | |
10475 | case M_BLEZL: | |
10476 | case M_BLTZL: | |
10477 | case M_BLTZALL: | |
c0ebe874 | 10478 | macro_build_branch_rs (mask, &offset_expr, op[0]); |
252b5132 RH |
10479 | break; |
10480 | ||
10481 | case M_BGTL_I: | |
10482 | likely = 1; | |
1a0670f3 | 10483 | /* Fall through. */ |
252b5132 | 10484 | case M_BGT_I: |
90ecf173 | 10485 | /* Check for > max integer. */ |
b0e6f033 | 10486 | if (imm_expr.X_add_number >= GPR_SMAX) |
252b5132 RH |
10487 | { |
10488 | do_false: | |
90ecf173 | 10489 | /* Result is always false. */ |
252b5132 | 10490 | if (! likely) |
a605d2b3 | 10491 | macro_build (NULL, "nop", ""); |
252b5132 | 10492 | else |
df58fc94 | 10493 | macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO); |
8fc2e39e | 10494 | break; |
252b5132 | 10495 | } |
f9419b05 | 10496 | ++imm_expr.X_add_number; |
6f2117ba | 10497 | /* Fall through. */ |
252b5132 RH |
10498 | case M_BGE_I: |
10499 | case M_BGEL_I: | |
10500 | if (mask == M_BGEL_I) | |
10501 | likely = 1; | |
b0e6f033 | 10502 | if (imm_expr.X_add_number == 0) |
252b5132 | 10503 | { |
df58fc94 | 10504 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, |
c0ebe874 | 10505 | &offset_expr, op[0]); |
8fc2e39e | 10506 | break; |
252b5132 | 10507 | } |
b0e6f033 | 10508 | if (imm_expr.X_add_number == 1) |
252b5132 | 10509 | { |
df58fc94 | 10510 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, |
c0ebe874 | 10511 | &offset_expr, op[0]); |
8fc2e39e | 10512 | break; |
252b5132 | 10513 | } |
b0e6f033 | 10514 | if (imm_expr.X_add_number <= GPR_SMIN) |
252b5132 RH |
10515 | { |
10516 | do_true: | |
6f2117ba | 10517 | /* Result is always true. */ |
1661c76c | 10518 | as_warn (_("branch %s is always true"), ip->insn_mo->name); |
67c0d1eb | 10519 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 10520 | break; |
252b5132 | 10521 | } |
8fc2e39e | 10522 | used_at = 1; |
c0ebe874 | 10523 | set_at (op[0], 0); |
df58fc94 RS |
10524 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10525 | &offset_expr, AT, ZERO); | |
252b5132 RH |
10526 | break; |
10527 | ||
10528 | case M_BGEUL: | |
10529 | likely = 1; | |
1a0670f3 | 10530 | /* Fall through. */ |
252b5132 | 10531 | case M_BGEU: |
c0ebe874 | 10532 | if (op[1] == 0) |
252b5132 | 10533 | goto do_true; |
c0ebe874 | 10534 | else if (op[0] == 0) |
df58fc94 | 10535 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
c0ebe874 | 10536 | &offset_expr, ZERO, op[1]); |
df58fc94 | 10537 | else |
252b5132 | 10538 | { |
df58fc94 | 10539 | used_at = 1; |
c0ebe874 | 10540 | macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]); |
df58fc94 RS |
10541 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10542 | &offset_expr, AT, ZERO); | |
252b5132 | 10543 | } |
252b5132 RH |
10544 | break; |
10545 | ||
10546 | case M_BGTUL_I: | |
10547 | likely = 1; | |
1a0670f3 | 10548 | /* Fall through. */ |
252b5132 | 10549 | case M_BGTU_I: |
c0ebe874 | 10550 | if (op[0] == 0 |
bad1aba3 | 10551 | || (GPR_SIZE == 32 |
f01dc953 | 10552 | && imm_expr.X_add_number == -1)) |
252b5132 | 10553 | goto do_false; |
f9419b05 | 10554 | ++imm_expr.X_add_number; |
6f2117ba | 10555 | /* Fall through. */ |
252b5132 RH |
10556 | case M_BGEU_I: |
10557 | case M_BGEUL_I: | |
10558 | if (mask == M_BGEUL_I) | |
10559 | likely = 1; | |
b0e6f033 | 10560 | if (imm_expr.X_add_number == 0) |
252b5132 | 10561 | goto do_true; |
b0e6f033 | 10562 | else if (imm_expr.X_add_number == 1) |
df58fc94 | 10563 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
c0ebe874 | 10564 | &offset_expr, op[0], ZERO); |
df58fc94 | 10565 | else |
252b5132 | 10566 | { |
df58fc94 | 10567 | used_at = 1; |
c0ebe874 | 10568 | set_at (op[0], 1); |
df58fc94 RS |
10569 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10570 | &offset_expr, AT, ZERO); | |
252b5132 | 10571 | } |
252b5132 RH |
10572 | break; |
10573 | ||
10574 | case M_BGTL: | |
10575 | likely = 1; | |
1a0670f3 | 10576 | /* Fall through. */ |
252b5132 | 10577 | case M_BGT: |
c0ebe874 RS |
10578 | if (op[1] == 0) |
10579 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[0]); | |
10580 | else if (op[0] == 0) | |
10581 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[1]); | |
df58fc94 | 10582 | else |
252b5132 | 10583 | { |
df58fc94 | 10584 | used_at = 1; |
c0ebe874 | 10585 | macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]); |
df58fc94 RS |
10586 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10587 | &offset_expr, AT, ZERO); | |
252b5132 | 10588 | } |
252b5132 RH |
10589 | break; |
10590 | ||
10591 | case M_BGTUL: | |
10592 | likely = 1; | |
1a0670f3 | 10593 | /* Fall through. */ |
252b5132 | 10594 | case M_BGTU: |
c0ebe874 | 10595 | if (op[1] == 0) |
df58fc94 | 10596 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
c0ebe874 RS |
10597 | &offset_expr, op[0], ZERO); |
10598 | else if (op[0] == 0) | |
df58fc94 RS |
10599 | goto do_false; |
10600 | else | |
252b5132 | 10601 | { |
df58fc94 | 10602 | used_at = 1; |
c0ebe874 | 10603 | macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]); |
df58fc94 RS |
10604 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10605 | &offset_expr, AT, ZERO); | |
252b5132 | 10606 | } |
252b5132 RH |
10607 | break; |
10608 | ||
10609 | case M_BLEL: | |
10610 | likely = 1; | |
1a0670f3 | 10611 | /* Fall through. */ |
252b5132 | 10612 | case M_BLE: |
c0ebe874 RS |
10613 | if (op[1] == 0) |
10614 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]); | |
10615 | else if (op[0] == 0) | |
10616 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[1]); | |
df58fc94 | 10617 | else |
252b5132 | 10618 | { |
df58fc94 | 10619 | used_at = 1; |
c0ebe874 | 10620 | macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]); |
df58fc94 RS |
10621 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10622 | &offset_expr, AT, ZERO); | |
252b5132 | 10623 | } |
252b5132 RH |
10624 | break; |
10625 | ||
10626 | case M_BLEL_I: | |
10627 | likely = 1; | |
1a0670f3 | 10628 | /* Fall through. */ |
252b5132 | 10629 | case M_BLE_I: |
b0e6f033 | 10630 | if (imm_expr.X_add_number >= GPR_SMAX) |
252b5132 | 10631 | goto do_true; |
f9419b05 | 10632 | ++imm_expr.X_add_number; |
6f2117ba | 10633 | /* Fall through. */ |
252b5132 RH |
10634 | case M_BLT_I: |
10635 | case M_BLTL_I: | |
10636 | if (mask == M_BLTL_I) | |
10637 | likely = 1; | |
b0e6f033 | 10638 | if (imm_expr.X_add_number == 0) |
c0ebe874 | 10639 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]); |
b0e6f033 | 10640 | else if (imm_expr.X_add_number == 1) |
c0ebe874 | 10641 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]); |
df58fc94 | 10642 | else |
252b5132 | 10643 | { |
df58fc94 | 10644 | used_at = 1; |
c0ebe874 | 10645 | set_at (op[0], 0); |
df58fc94 RS |
10646 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10647 | &offset_expr, AT, ZERO); | |
252b5132 | 10648 | } |
252b5132 RH |
10649 | break; |
10650 | ||
10651 | case M_BLEUL: | |
10652 | likely = 1; | |
1a0670f3 | 10653 | /* Fall through. */ |
252b5132 | 10654 | case M_BLEU: |
c0ebe874 | 10655 | if (op[1] == 0) |
df58fc94 | 10656 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
c0ebe874 RS |
10657 | &offset_expr, op[0], ZERO); |
10658 | else if (op[0] == 0) | |
df58fc94 RS |
10659 | goto do_true; |
10660 | else | |
252b5132 | 10661 | { |
df58fc94 | 10662 | used_at = 1; |
c0ebe874 | 10663 | macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]); |
df58fc94 RS |
10664 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10665 | &offset_expr, AT, ZERO); | |
252b5132 | 10666 | } |
252b5132 RH |
10667 | break; |
10668 | ||
10669 | case M_BLEUL_I: | |
10670 | likely = 1; | |
1a0670f3 | 10671 | /* Fall through. */ |
252b5132 | 10672 | case M_BLEU_I: |
c0ebe874 | 10673 | if (op[0] == 0 |
bad1aba3 | 10674 | || (GPR_SIZE == 32 |
f01dc953 | 10675 | && imm_expr.X_add_number == -1)) |
252b5132 | 10676 | goto do_true; |
f9419b05 | 10677 | ++imm_expr.X_add_number; |
6f2117ba | 10678 | /* Fall through. */ |
252b5132 RH |
10679 | case M_BLTU_I: |
10680 | case M_BLTUL_I: | |
10681 | if (mask == M_BLTUL_I) | |
10682 | likely = 1; | |
b0e6f033 | 10683 | if (imm_expr.X_add_number == 0) |
252b5132 | 10684 | goto do_false; |
b0e6f033 | 10685 | else if (imm_expr.X_add_number == 1) |
df58fc94 | 10686 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
c0ebe874 | 10687 | &offset_expr, op[0], ZERO); |
df58fc94 | 10688 | else |
252b5132 | 10689 | { |
df58fc94 | 10690 | used_at = 1; |
c0ebe874 | 10691 | set_at (op[0], 1); |
df58fc94 RS |
10692 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10693 | &offset_expr, AT, ZERO); | |
252b5132 | 10694 | } |
252b5132 RH |
10695 | break; |
10696 | ||
10697 | case M_BLTL: | |
10698 | likely = 1; | |
1a0670f3 | 10699 | /* Fall through. */ |
252b5132 | 10700 | case M_BLT: |
c0ebe874 RS |
10701 | if (op[1] == 0) |
10702 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]); | |
10703 | else if (op[0] == 0) | |
10704 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[1]); | |
df58fc94 | 10705 | else |
252b5132 | 10706 | { |
df58fc94 | 10707 | used_at = 1; |
c0ebe874 | 10708 | macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]); |
df58fc94 RS |
10709 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10710 | &offset_expr, AT, ZERO); | |
252b5132 | 10711 | } |
252b5132 RH |
10712 | break; |
10713 | ||
10714 | case M_BLTUL: | |
10715 | likely = 1; | |
1a0670f3 | 10716 | /* Fall through. */ |
252b5132 | 10717 | case M_BLTU: |
c0ebe874 | 10718 | if (op[1] == 0) |
252b5132 | 10719 | goto do_false; |
c0ebe874 | 10720 | else if (op[0] == 0) |
df58fc94 | 10721 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
c0ebe874 | 10722 | &offset_expr, ZERO, op[1]); |
df58fc94 | 10723 | else |
252b5132 | 10724 | { |
df58fc94 | 10725 | used_at = 1; |
c0ebe874 | 10726 | macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]); |
df58fc94 RS |
10727 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10728 | &offset_expr, AT, ZERO); | |
252b5132 | 10729 | } |
252b5132 RH |
10730 | break; |
10731 | ||
10732 | case M_DDIV_3: | |
10733 | dbl = 1; | |
1a0670f3 | 10734 | /* Fall through. */ |
252b5132 RH |
10735 | case M_DIV_3: |
10736 | s = "mflo"; | |
10737 | goto do_div3; | |
10738 | case M_DREM_3: | |
10739 | dbl = 1; | |
1a0670f3 | 10740 | /* Fall through. */ |
252b5132 RH |
10741 | case M_REM_3: |
10742 | s = "mfhi"; | |
10743 | do_div3: | |
c0ebe874 | 10744 | if (op[2] == 0) |
252b5132 | 10745 | { |
1661c76c | 10746 | as_warn (_("divide by zero")); |
252b5132 | 10747 | if (mips_trap) |
df58fc94 | 10748 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 10749 | else |
df58fc94 | 10750 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 10751 | break; |
252b5132 RH |
10752 | } |
10753 | ||
7d10b47d | 10754 | start_noreorder (); |
252b5132 RH |
10755 | if (mips_trap) |
10756 | { | |
c0ebe874 RS |
10757 | macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7); |
10758 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]); | |
252b5132 RH |
10759 | } |
10760 | else | |
10761 | { | |
df58fc94 RS |
10762 | if (mips_opts.micromips) |
10763 | micromips_label_expr (&label_expr); | |
10764 | else | |
10765 | label_expr.X_add_number = 8; | |
c0ebe874 RS |
10766 | macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO); |
10767 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]); | |
df58fc94 RS |
10768 | macro_build (NULL, "break", BRK_FMT, 7); |
10769 | if (mips_opts.micromips) | |
10770 | micromips_add_label (); | |
252b5132 RH |
10771 | } |
10772 | expr1.X_add_number = -1; | |
8fc2e39e | 10773 | used_at = 1; |
f6a22291 | 10774 | load_register (AT, &expr1, dbl); |
df58fc94 RS |
10775 | if (mips_opts.micromips) |
10776 | micromips_label_expr (&label_expr); | |
10777 | else | |
10778 | label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); | |
c0ebe874 | 10779 | macro_build (&label_expr, "bne", "s,t,p", op[2], AT); |
252b5132 RH |
10780 | if (dbl) |
10781 | { | |
10782 | expr1.X_add_number = 1; | |
f6a22291 | 10783 | load_register (AT, &expr1, dbl); |
df58fc94 | 10784 | macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31); |
252b5132 RH |
10785 | } |
10786 | else | |
10787 | { | |
10788 | expr1.X_add_number = 0x80000000; | |
df58fc94 | 10789 | macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16); |
252b5132 RH |
10790 | } |
10791 | if (mips_trap) | |
10792 | { | |
c0ebe874 | 10793 | macro_build (NULL, "teq", TRAP_FMT, op[1], AT, 6); |
252b5132 RH |
10794 | /* We want to close the noreorder block as soon as possible, so |
10795 | that later insns are available for delay slot filling. */ | |
7d10b47d | 10796 | end_noreorder (); |
252b5132 RH |
10797 | } |
10798 | else | |
10799 | { | |
df58fc94 RS |
10800 | if (mips_opts.micromips) |
10801 | micromips_label_expr (&label_expr); | |
10802 | else | |
10803 | label_expr.X_add_number = 8; | |
c0ebe874 | 10804 | macro_build (&label_expr, "bne", "s,t,p", op[1], AT); |
a605d2b3 | 10805 | macro_build (NULL, "nop", ""); |
252b5132 RH |
10806 | |
10807 | /* We want to close the noreorder block as soon as possible, so | |
10808 | that later insns are available for delay slot filling. */ | |
7d10b47d | 10809 | end_noreorder (); |
252b5132 | 10810 | |
df58fc94 | 10811 | macro_build (NULL, "break", BRK_FMT, 6); |
252b5132 | 10812 | } |
df58fc94 RS |
10813 | if (mips_opts.micromips) |
10814 | micromips_add_label (); | |
c0ebe874 | 10815 | macro_build (NULL, s, MFHL_FMT, op[0]); |
252b5132 RH |
10816 | break; |
10817 | ||
10818 | case M_DIV_3I: | |
10819 | s = "div"; | |
10820 | s2 = "mflo"; | |
10821 | goto do_divi; | |
10822 | case M_DIVU_3I: | |
10823 | s = "divu"; | |
10824 | s2 = "mflo"; | |
10825 | goto do_divi; | |
10826 | case M_REM_3I: | |
10827 | s = "div"; | |
10828 | s2 = "mfhi"; | |
10829 | goto do_divi; | |
10830 | case M_REMU_3I: | |
10831 | s = "divu"; | |
10832 | s2 = "mfhi"; | |
10833 | goto do_divi; | |
10834 | case M_DDIV_3I: | |
10835 | dbl = 1; | |
10836 | s = "ddiv"; | |
10837 | s2 = "mflo"; | |
10838 | goto do_divi; | |
10839 | case M_DDIVU_3I: | |
10840 | dbl = 1; | |
10841 | s = "ddivu"; | |
10842 | s2 = "mflo"; | |
10843 | goto do_divi; | |
10844 | case M_DREM_3I: | |
10845 | dbl = 1; | |
10846 | s = "ddiv"; | |
10847 | s2 = "mfhi"; | |
10848 | goto do_divi; | |
10849 | case M_DREMU_3I: | |
10850 | dbl = 1; | |
10851 | s = "ddivu"; | |
10852 | s2 = "mfhi"; | |
10853 | do_divi: | |
b0e6f033 | 10854 | if (imm_expr.X_add_number == 0) |
252b5132 | 10855 | { |
1661c76c | 10856 | as_warn (_("divide by zero")); |
252b5132 | 10857 | if (mips_trap) |
df58fc94 | 10858 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 10859 | else |
df58fc94 | 10860 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 10861 | break; |
252b5132 | 10862 | } |
b0e6f033 | 10863 | if (imm_expr.X_add_number == 1) |
252b5132 RH |
10864 | { |
10865 | if (strcmp (s2, "mflo") == 0) | |
c0ebe874 | 10866 | move_register (op[0], op[1]); |
252b5132 | 10867 | else |
c0ebe874 | 10868 | move_register (op[0], ZERO); |
8fc2e39e | 10869 | break; |
252b5132 | 10870 | } |
b0e6f033 | 10871 | if (imm_expr.X_add_number == -1 && s[strlen (s) - 1] != 'u') |
252b5132 RH |
10872 | { |
10873 | if (strcmp (s2, "mflo") == 0) | |
c0ebe874 | 10874 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", op[0], op[1]); |
252b5132 | 10875 | else |
c0ebe874 | 10876 | move_register (op[0], ZERO); |
8fc2e39e | 10877 | break; |
252b5132 RH |
10878 | } |
10879 | ||
8fc2e39e | 10880 | used_at = 1; |
67c0d1eb | 10881 | load_register (AT, &imm_expr, dbl); |
c0ebe874 RS |
10882 | macro_build (NULL, s, "z,s,t", op[1], AT); |
10883 | macro_build (NULL, s2, MFHL_FMT, op[0]); | |
252b5132 RH |
10884 | break; |
10885 | ||
10886 | case M_DIVU_3: | |
10887 | s = "divu"; | |
10888 | s2 = "mflo"; | |
10889 | goto do_divu3; | |
10890 | case M_REMU_3: | |
10891 | s = "divu"; | |
10892 | s2 = "mfhi"; | |
10893 | goto do_divu3; | |
10894 | case M_DDIVU_3: | |
10895 | s = "ddivu"; | |
10896 | s2 = "mflo"; | |
10897 | goto do_divu3; | |
10898 | case M_DREMU_3: | |
10899 | s = "ddivu"; | |
10900 | s2 = "mfhi"; | |
10901 | do_divu3: | |
7d10b47d | 10902 | start_noreorder (); |
252b5132 RH |
10903 | if (mips_trap) |
10904 | { | |
c0ebe874 RS |
10905 | macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7); |
10906 | macro_build (NULL, s, "z,s,t", op[1], op[2]); | |
252b5132 RH |
10907 | /* We want to close the noreorder block as soon as possible, so |
10908 | that later insns are available for delay slot filling. */ | |
7d10b47d | 10909 | end_noreorder (); |
252b5132 RH |
10910 | } |
10911 | else | |
10912 | { | |
df58fc94 RS |
10913 | if (mips_opts.micromips) |
10914 | micromips_label_expr (&label_expr); | |
10915 | else | |
10916 | label_expr.X_add_number = 8; | |
c0ebe874 RS |
10917 | macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO); |
10918 | macro_build (NULL, s, "z,s,t", op[1], op[2]); | |
252b5132 RH |
10919 | |
10920 | /* We want to close the noreorder block as soon as possible, so | |
10921 | that later insns are available for delay slot filling. */ | |
7d10b47d | 10922 | end_noreorder (); |
df58fc94 RS |
10923 | macro_build (NULL, "break", BRK_FMT, 7); |
10924 | if (mips_opts.micromips) | |
10925 | micromips_add_label (); | |
252b5132 | 10926 | } |
c0ebe874 | 10927 | macro_build (NULL, s2, MFHL_FMT, op[0]); |
8fc2e39e | 10928 | break; |
252b5132 | 10929 | |
1abe91b1 MR |
10930 | case M_DLCA_AB: |
10931 | dbl = 1; | |
1a0670f3 | 10932 | /* Fall through. */ |
1abe91b1 MR |
10933 | case M_LCA_AB: |
10934 | call = 1; | |
10935 | goto do_la; | |
252b5132 RH |
10936 | case M_DLA_AB: |
10937 | dbl = 1; | |
1a0670f3 | 10938 | /* Fall through. */ |
252b5132 | 10939 | case M_LA_AB: |
1abe91b1 | 10940 | do_la: |
252b5132 RH |
10941 | /* Load the address of a symbol into a register. If breg is not |
10942 | zero, we then add a base register to it. */ | |
10943 | ||
c0ebe874 | 10944 | breg = op[2]; |
bad1aba3 | 10945 | if (dbl && GPR_SIZE == 32) |
ece794d9 MF |
10946 | as_warn (_("dla used to load 32-bit register; recommend using la " |
10947 | "instead")); | |
3bec30a8 | 10948 | |
90ecf173 | 10949 | if (!dbl && HAVE_64BIT_OBJECTS) |
ece794d9 MF |
10950 | as_warn (_("la used to load 64-bit address; recommend using dla " |
10951 | "instead")); | |
3bec30a8 | 10952 | |
f2ae14a1 | 10953 | if (small_offset_p (0, align, 16)) |
0c11417f | 10954 | { |
c0ebe874 | 10955 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", op[0], breg, |
f2ae14a1 | 10956 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]); |
8fc2e39e | 10957 | break; |
0c11417f MR |
10958 | } |
10959 | ||
c0ebe874 | 10960 | if (mips_opts.at && (op[0] == breg)) |
afdbd6d0 CD |
10961 | { |
10962 | tempreg = AT; | |
10963 | used_at = 1; | |
10964 | } | |
10965 | else | |
c0ebe874 | 10966 | tempreg = op[0]; |
afdbd6d0 | 10967 | |
252b5132 RH |
10968 | if (offset_expr.X_op != O_symbol |
10969 | && offset_expr.X_op != O_constant) | |
10970 | { | |
1661c76c | 10971 | as_bad (_("expression too complex")); |
252b5132 RH |
10972 | offset_expr.X_op = O_constant; |
10973 | } | |
10974 | ||
252b5132 | 10975 | if (offset_expr.X_op == O_constant) |
aed1a261 | 10976 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
10977 | else if (mips_pic == NO_PIC) |
10978 | { | |
d6bc6245 | 10979 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 10980 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
10981 | Otherwise we want |
10982 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
10983 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
10984 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 10985 | so we may as well always use the latter form. |
76b3015f | 10986 | |
6caf9ef4 TS |
10987 | With 64bit address space and a usable $at we want |
10988 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
10989 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
10990 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
10991 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
10992 | dsll32 $tempreg,0 | |
10993 | daddu $tempreg,$tempreg,$at | |
10994 | ||
10995 | If $at is already in use, we use a path which is suboptimal | |
10996 | on superscalar processors. | |
10997 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
10998 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
10999 | dsll $tempreg,16 | |
11000 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
11001 | dsll $tempreg,16 | |
11002 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
11003 | ||
11004 | For GP relative symbols in 64bit address space we can use | |
11005 | the same sequence as in 32bit address space. */ | |
aed1a261 | 11006 | if (HAVE_64BIT_SYMBOLS) |
252b5132 | 11007 | { |
6caf9ef4 TS |
11008 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
11009 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
11010 | { | |
11011 | relax_start (offset_expr.X_add_symbol); | |
11012 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
11013 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
11014 | relax_switch (); | |
11015 | } | |
d6bc6245 | 11016 | |
741fe287 | 11017 | if (used_at == 0 && mips_opts.at) |
98d3f06f | 11018 | { |
df58fc94 | 11019 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 11020 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 11021 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 11022 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 11023 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 11024 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 11025 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 11026 | AT, AT, BFD_RELOC_LO16); |
df58fc94 | 11027 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb | 11028 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
98d3f06f KH |
11029 | used_at = 1; |
11030 | } | |
11031 | else | |
11032 | { | |
df58fc94 | 11033 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 11034 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 11035 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 11036 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
df58fc94 | 11037 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 11038 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 11039 | tempreg, tempreg, BFD_RELOC_HI16_S); |
df58fc94 | 11040 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 11041 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 11042 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 11043 | } |
6caf9ef4 TS |
11044 | |
11045 | if (mips_relax.sequence) | |
11046 | relax_end (); | |
98d3f06f KH |
11047 | } |
11048 | else | |
11049 | { | |
11050 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 11051 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
98d3f06f | 11052 | { |
4d7206a2 | 11053 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
11054 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
11055 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 11056 | relax_switch (); |
98d3f06f | 11057 | } |
6943caf0 | 11058 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
1661c76c | 11059 | as_bad (_("offset too large")); |
67c0d1eb RS |
11060 | macro_build_lui (&offset_expr, tempreg); |
11061 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
11062 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
11063 | if (mips_relax.sequence) |
11064 | relax_end (); | |
98d3f06f | 11065 | } |
252b5132 | 11066 | } |
0a44bf69 | 11067 | else if (!mips_big_got && !HAVE_NEWABI) |
252b5132 | 11068 | { |
9117d219 NC |
11069 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
11070 | ||
252b5132 RH |
11071 | /* If this is a reference to an external symbol, and there |
11072 | is no constant, we want | |
11073 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 11074 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 11075 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
11076 | For a local symbol, we want |
11077 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
11078 | nop | |
11079 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
11080 | ||
11081 | If we have a small constant, and this is a reference to | |
11082 | an external symbol, we want | |
11083 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
11084 | nop | |
11085 | addiu $tempreg,$tempreg,<constant> | |
11086 | For a local symbol, we want the same instruction | |
11087 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
11088 | addiu instruction. | |
11089 | ||
11090 | If we have a large constant, and this is a reference to | |
11091 | an external symbol, we want | |
11092 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
11093 | lui $at,<hiconstant> | |
11094 | addiu $at,$at,<loconstant> | |
11095 | addu $tempreg,$tempreg,$at | |
11096 | For a local symbol, we want the same instruction | |
11097 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 11098 | addiu instruction. |
ed6fb7bd SC |
11099 | */ |
11100 | ||
4d7206a2 | 11101 | if (offset_expr.X_add_number == 0) |
252b5132 | 11102 | { |
0a44bf69 RS |
11103 | if (mips_pic == SVR4_PIC |
11104 | && breg == 0 | |
11105 | && (call || tempreg == PIC_CALL_REG)) | |
4d7206a2 RS |
11106 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; |
11107 | ||
11108 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
11109 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11110 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 11111 | if (breg != 0) |
252b5132 RH |
11112 | { |
11113 | /* We're going to put in an addu instruction using | |
11114 | tempreg, so we may as well insert the nop right | |
11115 | now. */ | |
269137b2 | 11116 | load_delay_nop (); |
252b5132 | 11117 | } |
4d7206a2 | 11118 | relax_switch (); |
67c0d1eb RS |
11119 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11120 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 11121 | load_delay_nop (); |
67c0d1eb RS |
11122 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
11123 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 11124 | relax_end (); |
252b5132 RH |
11125 | /* FIXME: If breg == 0, and the next instruction uses |
11126 | $tempreg, then if this variant case is used an extra | |
11127 | nop will be generated. */ | |
11128 | } | |
4d7206a2 RS |
11129 | else if (offset_expr.X_add_number >= -0x8000 |
11130 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 11131 | { |
67c0d1eb | 11132 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 11133 | load_delay_nop (); |
67c0d1eb | 11134 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
11135 | } |
11136 | else | |
11137 | { | |
4d7206a2 RS |
11138 | expr1.X_add_number = offset_expr.X_add_number; |
11139 | offset_expr.X_add_number = | |
43c0598f | 11140 | SEXT_16BIT (offset_expr.X_add_number); |
67c0d1eb | 11141 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 11142 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
11143 | /* If we are going to add in a base register, and the |
11144 | target register and the base register are the same, | |
11145 | then we are using AT as a temporary register. Since | |
11146 | we want to load the constant into AT, we add our | |
11147 | current AT (from the global offset table) and the | |
11148 | register into the register now, and pretend we were | |
11149 | not using a base register. */ | |
c0ebe874 | 11150 | if (breg == op[0]) |
252b5132 | 11151 | { |
269137b2 | 11152 | load_delay_nop (); |
67c0d1eb | 11153 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 | 11154 | op[0], AT, breg); |
252b5132 | 11155 | breg = 0; |
c0ebe874 | 11156 | tempreg = op[0]; |
252b5132 | 11157 | } |
f6a22291 | 11158 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
11159 | used_at = 1; |
11160 | } | |
11161 | } | |
0a44bf69 | 11162 | else if (!mips_big_got && HAVE_NEWABI) |
f5040a92 | 11163 | { |
67c0d1eb | 11164 | int add_breg_early = 0; |
f5040a92 AO |
11165 | |
11166 | /* If this is a reference to an external, and there is no | |
11167 | constant, or local symbol (*), with or without a | |
11168 | constant, we want | |
11169 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 11170 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
11171 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
11172 | ||
11173 | If we have a small constant, and this is a reference to | |
11174 | an external symbol, we want | |
11175 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
11176 | addiu $tempreg,$tempreg,<constant> | |
11177 | ||
11178 | If we have a large constant, and this is a reference to | |
11179 | an external symbol, we want | |
11180 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
11181 | lui $at,<hiconstant> | |
11182 | addiu $at,$at,<loconstant> | |
11183 | addu $tempreg,$tempreg,$at | |
11184 | ||
11185 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
11186 | local symbols, even though it introduces an additional | |
11187 | instruction. */ | |
11188 | ||
f5040a92 AO |
11189 | if (offset_expr.X_add_number) |
11190 | { | |
4d7206a2 | 11191 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
11192 | offset_expr.X_add_number = 0; |
11193 | ||
4d7206a2 | 11194 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
11195 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11196 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
11197 | |
11198 | if (expr1.X_add_number >= -0x8000 | |
11199 | && expr1.X_add_number < 0x8000) | |
11200 | { | |
67c0d1eb RS |
11201 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
11202 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 11203 | } |
ecd13cd3 | 11204 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 11205 | { |
c0ebe874 RS |
11206 | unsigned int dreg; |
11207 | ||
f5040a92 AO |
11208 | /* If we are going to add in a base register, and the |
11209 | target register and the base register are the same, | |
11210 | then we are using AT as a temporary register. Since | |
11211 | we want to load the constant into AT, we add our | |
11212 | current AT (from the global offset table) and the | |
11213 | register into the register now, and pretend we were | |
11214 | not using a base register. */ | |
c0ebe874 | 11215 | if (breg != op[0]) |
f5040a92 AO |
11216 | dreg = tempreg; |
11217 | else | |
11218 | { | |
9c2799c2 | 11219 | gas_assert (tempreg == AT); |
67c0d1eb | 11220 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 RS |
11221 | op[0], AT, breg); |
11222 | dreg = op[0]; | |
67c0d1eb | 11223 | add_breg_early = 1; |
f5040a92 AO |
11224 | } |
11225 | ||
f6a22291 | 11226 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 11227 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 11228 | dreg, dreg, AT); |
f5040a92 | 11229 | |
f5040a92 AO |
11230 | used_at = 1; |
11231 | } | |
11232 | else | |
11233 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
11234 | ||
4d7206a2 | 11235 | relax_switch (); |
f5040a92 AO |
11236 | offset_expr.X_add_number = expr1.X_add_number; |
11237 | ||
67c0d1eb RS |
11238 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11239 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
11240 | if (add_breg_early) | |
f5040a92 | 11241 | { |
67c0d1eb | 11242 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 | 11243 | op[0], tempreg, breg); |
f5040a92 | 11244 | breg = 0; |
c0ebe874 | 11245 | tempreg = op[0]; |
f5040a92 | 11246 | } |
4d7206a2 | 11247 | relax_end (); |
f5040a92 | 11248 | } |
4d7206a2 | 11249 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 11250 | { |
4d7206a2 | 11251 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
11252 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11253 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 11254 | relax_switch (); |
67c0d1eb RS |
11255 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11256 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 11257 | relax_end (); |
f5040a92 | 11258 | } |
4d7206a2 | 11259 | else |
f5040a92 | 11260 | { |
67c0d1eb RS |
11261 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11262 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
11263 | } |
11264 | } | |
0a44bf69 | 11265 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 11266 | { |
67c0d1eb | 11267 | int gpdelay; |
9117d219 NC |
11268 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
11269 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 11270 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
11271 | |
11272 | /* This is the large GOT case. If this is a reference to an | |
11273 | external symbol, and there is no constant, we want | |
11274 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11275 | addu $tempreg,$tempreg,$gp | |
11276 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 11277 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
11278 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
11279 | addu $tempreg,$tempreg,$gp | |
11280 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
11281 | For a local symbol, we want |
11282 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
11283 | nop | |
11284 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
11285 | ||
11286 | If we have a small constant, and this is a reference to | |
11287 | an external symbol, we want | |
11288 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11289 | addu $tempreg,$tempreg,$gp | |
11290 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
11291 | nop | |
11292 | addiu $tempreg,$tempreg,<constant> | |
11293 | For a local symbol, we want | |
11294 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
11295 | nop | |
11296 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
11297 | ||
11298 | If we have a large constant, and this is a reference to | |
11299 | an external symbol, we want | |
11300 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11301 | addu $tempreg,$tempreg,$gp | |
11302 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
11303 | lui $at,<hiconstant> | |
11304 | addiu $at,$at,<loconstant> | |
11305 | addu $tempreg,$tempreg,$at | |
11306 | For a local symbol, we want | |
11307 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
11308 | lui $at,<hiconstant> | |
11309 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
11310 | addu $tempreg,$tempreg,$at | |
f5040a92 | 11311 | */ |
438c16b8 | 11312 | |
252b5132 RH |
11313 | expr1.X_add_number = offset_expr.X_add_number; |
11314 | offset_expr.X_add_number = 0; | |
4d7206a2 | 11315 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 11316 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
11317 | if (expr1.X_add_number == 0 && breg == 0 |
11318 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
11319 | { |
11320 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
11321 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
11322 | } | |
df58fc94 | 11323 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 11324 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 11325 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 11326 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 11327 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
11328 | if (expr1.X_add_number == 0) |
11329 | { | |
67c0d1eb | 11330 | if (breg != 0) |
252b5132 RH |
11331 | { |
11332 | /* We're going to put in an addu instruction using | |
11333 | tempreg, so we may as well insert the nop right | |
11334 | now. */ | |
269137b2 | 11335 | load_delay_nop (); |
252b5132 | 11336 | } |
252b5132 RH |
11337 | } |
11338 | else if (expr1.X_add_number >= -0x8000 | |
11339 | && expr1.X_add_number < 0x8000) | |
11340 | { | |
269137b2 | 11341 | load_delay_nop (); |
67c0d1eb | 11342 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 11343 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
11344 | } |
11345 | else | |
11346 | { | |
c0ebe874 RS |
11347 | unsigned int dreg; |
11348 | ||
252b5132 RH |
11349 | /* If we are going to add in a base register, and the |
11350 | target register and the base register are the same, | |
11351 | then we are using AT as a temporary register. Since | |
11352 | we want to load the constant into AT, we add our | |
11353 | current AT (from the global offset table) and the | |
11354 | register into the register now, and pretend we were | |
11355 | not using a base register. */ | |
c0ebe874 | 11356 | if (breg != op[0]) |
67c0d1eb | 11357 | dreg = tempreg; |
252b5132 RH |
11358 | else |
11359 | { | |
9c2799c2 | 11360 | gas_assert (tempreg == AT); |
269137b2 | 11361 | load_delay_nop (); |
67c0d1eb | 11362 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 RS |
11363 | op[0], AT, breg); |
11364 | dreg = op[0]; | |
252b5132 RH |
11365 | } |
11366 | ||
f6a22291 | 11367 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 11368 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 11369 | |
252b5132 RH |
11370 | used_at = 1; |
11371 | } | |
43c0598f | 11372 | offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number); |
4d7206a2 | 11373 | relax_switch (); |
252b5132 | 11374 | |
67c0d1eb | 11375 | if (gpdelay) |
252b5132 RH |
11376 | { |
11377 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 11378 | the first instruction on the main stream does not. */ |
67c0d1eb | 11379 | macro_build (NULL, "nop", ""); |
252b5132 | 11380 | } |
ed6fb7bd | 11381 | |
67c0d1eb RS |
11382 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11383 | local_reloc_type, mips_gp_register); | |
f5040a92 | 11384 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
11385 | && expr1.X_add_number < 0x8000) |
11386 | { | |
269137b2 | 11387 | load_delay_nop (); |
67c0d1eb RS |
11388 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
11389 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 11390 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
11391 | register, the external symbol case ended with a load, |
11392 | so if the symbol turns out to not be external, and | |
11393 | the next instruction uses tempreg, an unnecessary nop | |
11394 | will be inserted. */ | |
252b5132 RH |
11395 | } |
11396 | else | |
11397 | { | |
c0ebe874 | 11398 | if (breg == op[0]) |
252b5132 RH |
11399 | { |
11400 | /* We must add in the base register now, as in the | |
f5040a92 | 11401 | external symbol case. */ |
9c2799c2 | 11402 | gas_assert (tempreg == AT); |
269137b2 | 11403 | load_delay_nop (); |
67c0d1eb | 11404 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 RS |
11405 | op[0], AT, breg); |
11406 | tempreg = op[0]; | |
252b5132 | 11407 | /* We set breg to 0 because we have arranged to add |
f5040a92 | 11408 | it in in both cases. */ |
252b5132 RH |
11409 | breg = 0; |
11410 | } | |
11411 | ||
67c0d1eb RS |
11412 | macro_build_lui (&expr1, AT); |
11413 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 11414 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 11415 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 11416 | tempreg, tempreg, AT); |
8fc2e39e | 11417 | used_at = 1; |
252b5132 | 11418 | } |
4d7206a2 | 11419 | relax_end (); |
252b5132 | 11420 | } |
0a44bf69 | 11421 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 11422 | { |
f5040a92 AO |
11423 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
11424 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 11425 | int add_breg_early = 0; |
f5040a92 AO |
11426 | |
11427 | /* This is the large GOT case. If this is a reference to an | |
11428 | external symbol, and there is no constant, we want | |
11429 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11430 | add $tempreg,$tempreg,$gp | |
11431 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 11432 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
11433 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
11434 | add $tempreg,$tempreg,$gp | |
11435 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
11436 | ||
11437 | If we have a small constant, and this is a reference to | |
11438 | an external symbol, we want | |
11439 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11440 | add $tempreg,$tempreg,$gp | |
11441 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
11442 | addi $tempreg,$tempreg,<constant> | |
11443 | ||
11444 | If we have a large constant, and this is a reference to | |
11445 | an external symbol, we want | |
11446 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11447 | addu $tempreg,$tempreg,$gp | |
11448 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
11449 | lui $at,<hiconstant> | |
11450 | addi $at,$at,<loconstant> | |
11451 | add $tempreg,$tempreg,$at | |
11452 | ||
11453 | If we have NewABI, and we know it's a local symbol, we want | |
11454 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
11455 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
11456 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
11457 | ||
4d7206a2 | 11458 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 11459 | |
4d7206a2 | 11460 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
11461 | offset_expr.X_add_number = 0; |
11462 | ||
1abe91b1 MR |
11463 | if (expr1.X_add_number == 0 && breg == 0 |
11464 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
11465 | { |
11466 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
11467 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
11468 | } | |
df58fc94 | 11469 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 11470 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 11471 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
11472 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11473 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
11474 | |
11475 | if (expr1.X_add_number == 0) | |
4d7206a2 | 11476 | ; |
f5040a92 AO |
11477 | else if (expr1.X_add_number >= -0x8000 |
11478 | && expr1.X_add_number < 0x8000) | |
11479 | { | |
67c0d1eb | 11480 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 11481 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 11482 | } |
ecd13cd3 | 11483 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 11484 | { |
c0ebe874 RS |
11485 | unsigned int dreg; |
11486 | ||
f5040a92 AO |
11487 | /* If we are going to add in a base register, and the |
11488 | target register and the base register are the same, | |
11489 | then we are using AT as a temporary register. Since | |
11490 | we want to load the constant into AT, we add our | |
11491 | current AT (from the global offset table) and the | |
11492 | register into the register now, and pretend we were | |
11493 | not using a base register. */ | |
c0ebe874 | 11494 | if (breg != op[0]) |
f5040a92 AO |
11495 | dreg = tempreg; |
11496 | else | |
11497 | { | |
9c2799c2 | 11498 | gas_assert (tempreg == AT); |
67c0d1eb | 11499 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 RS |
11500 | op[0], AT, breg); |
11501 | dreg = op[0]; | |
67c0d1eb | 11502 | add_breg_early = 1; |
f5040a92 AO |
11503 | } |
11504 | ||
f6a22291 | 11505 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 11506 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 11507 | |
f5040a92 AO |
11508 | used_at = 1; |
11509 | } | |
11510 | else | |
11511 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
11512 | ||
4d7206a2 | 11513 | relax_switch (); |
f5040a92 | 11514 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
11515 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11516 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
11517 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
11518 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
11519 | if (add_breg_early) | |
f5040a92 | 11520 | { |
67c0d1eb | 11521 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 | 11522 | op[0], tempreg, breg); |
f5040a92 | 11523 | breg = 0; |
c0ebe874 | 11524 | tempreg = op[0]; |
f5040a92 | 11525 | } |
4d7206a2 | 11526 | relax_end (); |
f5040a92 | 11527 | } |
252b5132 RH |
11528 | else |
11529 | abort (); | |
11530 | ||
11531 | if (breg != 0) | |
c0ebe874 | 11532 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", op[0], tempreg, breg); |
252b5132 RH |
11533 | break; |
11534 | ||
52b6b6b9 | 11535 | case M_MSGSND: |
df58fc94 | 11536 | gas_assert (!mips_opts.micromips); |
c0ebe874 | 11537 | macro_build (NULL, "c2", "C", (op[0] << 16) | 0x01); |
c7af4273 | 11538 | break; |
52b6b6b9 JM |
11539 | |
11540 | case M_MSGLD: | |
df58fc94 | 11541 | gas_assert (!mips_opts.micromips); |
c8276761 | 11542 | macro_build (NULL, "c2", "C", 0x02); |
c7af4273 | 11543 | break; |
52b6b6b9 JM |
11544 | |
11545 | case M_MSGLD_T: | |
df58fc94 | 11546 | gas_assert (!mips_opts.micromips); |
c0ebe874 | 11547 | macro_build (NULL, "c2", "C", (op[0] << 16) | 0x02); |
c7af4273 | 11548 | break; |
52b6b6b9 JM |
11549 | |
11550 | case M_MSGWAIT: | |
df58fc94 | 11551 | gas_assert (!mips_opts.micromips); |
52b6b6b9 | 11552 | macro_build (NULL, "c2", "C", 3); |
c7af4273 | 11553 | break; |
52b6b6b9 JM |
11554 | |
11555 | case M_MSGWAIT_T: | |
df58fc94 | 11556 | gas_assert (!mips_opts.micromips); |
c0ebe874 | 11557 | macro_build (NULL, "c2", "C", (op[0] << 16) | 0x03); |
c7af4273 | 11558 | break; |
52b6b6b9 | 11559 | |
252b5132 RH |
11560 | case M_J_A: |
11561 | /* The j instruction may not be used in PIC code, since it | |
11562 | requires an absolute address. We convert it to a b | |
11563 | instruction. */ | |
11564 | if (mips_pic == NO_PIC) | |
67c0d1eb | 11565 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 11566 | else |
67c0d1eb | 11567 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 11568 | break; |
252b5132 RH |
11569 | |
11570 | /* The jal instructions must be handled as macros because when | |
11571 | generating PIC code they expand to multi-instruction | |
11572 | sequences. Normally they are simple instructions. */ | |
df58fc94 | 11573 | case M_JALS_1: |
c0ebe874 RS |
11574 | op[1] = op[0]; |
11575 | op[0] = RA; | |
df58fc94 RS |
11576 | /* Fall through. */ |
11577 | case M_JALS_2: | |
11578 | gas_assert (mips_opts.micromips); | |
833794fc MR |
11579 | if (mips_opts.insn32) |
11580 | { | |
1661c76c | 11581 | as_bad (_("opcode not supported in the `insn32' mode `%s'"), str); |
833794fc MR |
11582 | break; |
11583 | } | |
df58fc94 RS |
11584 | jals = 1; |
11585 | goto jal; | |
252b5132 | 11586 | case M_JAL_1: |
c0ebe874 RS |
11587 | op[1] = op[0]; |
11588 | op[0] = RA; | |
252b5132 RH |
11589 | /* Fall through. */ |
11590 | case M_JAL_2: | |
df58fc94 | 11591 | jal: |
3e722fb5 | 11592 | if (mips_pic == NO_PIC) |
df58fc94 RS |
11593 | { |
11594 | s = jals ? "jalrs" : "jalr"; | |
e64af278 | 11595 | if (mips_opts.micromips |
833794fc | 11596 | && !mips_opts.insn32 |
c0ebe874 | 11597 | && op[0] == RA |
e64af278 | 11598 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
c0ebe874 | 11599 | macro_build (NULL, s, "mj", op[1]); |
df58fc94 | 11600 | else |
c0ebe874 | 11601 | macro_build (NULL, s, JALR_FMT, op[0], op[1]); |
df58fc94 | 11602 | } |
0a44bf69 | 11603 | else |
252b5132 | 11604 | { |
df58fc94 RS |
11605 | int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI |
11606 | && mips_cprestore_offset >= 0); | |
11607 | ||
c0ebe874 | 11608 | if (op[1] != PIC_CALL_REG) |
252b5132 | 11609 | as_warn (_("MIPS PIC call to register other than $25")); |
bdaaa2e1 | 11610 | |
833794fc MR |
11611 | s = ((mips_opts.micromips |
11612 | && !mips_opts.insn32 | |
11613 | && (!mips_opts.noreorder || cprestore)) | |
df58fc94 | 11614 | ? "jalrs" : "jalr"); |
e64af278 | 11615 | if (mips_opts.micromips |
833794fc | 11616 | && !mips_opts.insn32 |
c0ebe874 | 11617 | && op[0] == RA |
e64af278 | 11618 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
c0ebe874 | 11619 | macro_build (NULL, s, "mj", op[1]); |
df58fc94 | 11620 | else |
c0ebe874 | 11621 | macro_build (NULL, s, JALR_FMT, op[0], op[1]); |
0a44bf69 | 11622 | if (mips_pic == SVR4_PIC && !HAVE_NEWABI) |
252b5132 | 11623 | { |
6478892d | 11624 | if (mips_cprestore_offset < 0) |
1661c76c | 11625 | as_warn (_("no .cprestore pseudo-op used in PIC code")); |
6478892d TS |
11626 | else |
11627 | { | |
90ecf173 | 11628 | if (!mips_frame_reg_valid) |
7a621144 | 11629 | { |
1661c76c | 11630 | as_warn (_("no .frame pseudo-op used in PIC code")); |
7a621144 DJ |
11631 | /* Quiet this warning. */ |
11632 | mips_frame_reg_valid = 1; | |
11633 | } | |
90ecf173 | 11634 | if (!mips_cprestore_valid) |
7a621144 | 11635 | { |
1661c76c | 11636 | as_warn (_("no .cprestore pseudo-op used in PIC code")); |
7a621144 DJ |
11637 | /* Quiet this warning. */ |
11638 | mips_cprestore_valid = 1; | |
11639 | } | |
d3fca0b5 MR |
11640 | if (mips_opts.noreorder) |
11641 | macro_build (NULL, "nop", ""); | |
6478892d | 11642 | expr1.X_add_number = mips_cprestore_offset; |
134c0c8b | 11643 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 11644 | mips_gp_register, |
256ab948 TS |
11645 | mips_frame_reg, |
11646 | HAVE_64BIT_ADDRESSES); | |
6478892d | 11647 | } |
252b5132 RH |
11648 | } |
11649 | } | |
252b5132 | 11650 | |
8fc2e39e | 11651 | break; |
252b5132 | 11652 | |
df58fc94 RS |
11653 | case M_JALS_A: |
11654 | gas_assert (mips_opts.micromips); | |
833794fc MR |
11655 | if (mips_opts.insn32) |
11656 | { | |
1661c76c | 11657 | as_bad (_("opcode not supported in the `insn32' mode `%s'"), str); |
833794fc MR |
11658 | break; |
11659 | } | |
df58fc94 RS |
11660 | jals = 1; |
11661 | /* Fall through. */ | |
252b5132 RH |
11662 | case M_JAL_A: |
11663 | if (mips_pic == NO_PIC) | |
df58fc94 | 11664 | macro_build (&offset_expr, jals ? "jals" : "jal", "a"); |
252b5132 RH |
11665 | else if (mips_pic == SVR4_PIC) |
11666 | { | |
11667 | /* If this is a reference to an external symbol, and we are | |
11668 | using a small GOT, we want | |
11669 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
11670 | nop | |
f9419b05 | 11671 | jalr $ra,$25 |
252b5132 RH |
11672 | nop |
11673 | lw $gp,cprestore($sp) | |
11674 | The cprestore value is set using the .cprestore | |
11675 | pseudo-op. If we are using a big GOT, we want | |
11676 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
11677 | addu $25,$25,$gp | |
11678 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
11679 | nop | |
f9419b05 | 11680 | jalr $ra,$25 |
252b5132 RH |
11681 | nop |
11682 | lw $gp,cprestore($sp) | |
11683 | If the symbol is not external, we want | |
11684 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
11685 | nop | |
11686 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 11687 | jalr $ra,$25 |
252b5132 | 11688 | nop |
438c16b8 | 11689 | lw $gp,cprestore($sp) |
f5040a92 AO |
11690 | |
11691 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
11692 | sequences above, minus nops, unless the symbol is local, | |
11693 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
11694 | GOT_DISP. */ | |
438c16b8 | 11695 | if (HAVE_NEWABI) |
252b5132 | 11696 | { |
90ecf173 | 11697 | if (!mips_big_got) |
f5040a92 | 11698 | { |
4d7206a2 | 11699 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
11700 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11701 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 11702 | mips_gp_register); |
4d7206a2 | 11703 | relax_switch (); |
67c0d1eb RS |
11704 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11705 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
11706 | mips_gp_register); |
11707 | relax_end (); | |
f5040a92 AO |
11708 | } |
11709 | else | |
11710 | { | |
4d7206a2 | 11711 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 11712 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
11713 | BFD_RELOC_MIPS_CALL_HI16); |
11714 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
11715 | PIC_CALL_REG, mips_gp_register); | |
11716 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
11717 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
11718 | PIC_CALL_REG); | |
4d7206a2 | 11719 | relax_switch (); |
67c0d1eb RS |
11720 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11721 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
11722 | mips_gp_register); | |
11723 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
11724 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 11725 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 11726 | relax_end (); |
f5040a92 | 11727 | } |
684022ea | 11728 | |
df58fc94 | 11729 | macro_build_jalr (&offset_expr, 0); |
252b5132 RH |
11730 | } |
11731 | else | |
11732 | { | |
4d7206a2 | 11733 | relax_start (offset_expr.X_add_symbol); |
90ecf173 | 11734 | if (!mips_big_got) |
438c16b8 | 11735 | { |
67c0d1eb RS |
11736 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11737 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 11738 | mips_gp_register); |
269137b2 | 11739 | load_delay_nop (); |
4d7206a2 | 11740 | relax_switch (); |
438c16b8 | 11741 | } |
252b5132 | 11742 | else |
252b5132 | 11743 | { |
67c0d1eb RS |
11744 | int gpdelay; |
11745 | ||
11746 | gpdelay = reg_needs_delay (mips_gp_register); | |
df58fc94 | 11747 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
11748 | BFD_RELOC_MIPS_CALL_HI16); |
11749 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
11750 | PIC_CALL_REG, mips_gp_register); | |
11751 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
11752 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
11753 | PIC_CALL_REG); | |
269137b2 | 11754 | load_delay_nop (); |
4d7206a2 | 11755 | relax_switch (); |
67c0d1eb RS |
11756 | if (gpdelay) |
11757 | macro_build (NULL, "nop", ""); | |
252b5132 | 11758 | } |
67c0d1eb RS |
11759 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11760 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 11761 | mips_gp_register); |
269137b2 | 11762 | load_delay_nop (); |
67c0d1eb RS |
11763 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
11764 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 11765 | relax_end (); |
df58fc94 | 11766 | macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0); |
438c16b8 | 11767 | |
6478892d | 11768 | if (mips_cprestore_offset < 0) |
1661c76c | 11769 | as_warn (_("no .cprestore pseudo-op used in PIC code")); |
6478892d TS |
11770 | else |
11771 | { | |
90ecf173 | 11772 | if (!mips_frame_reg_valid) |
7a621144 | 11773 | { |
1661c76c | 11774 | as_warn (_("no .frame pseudo-op used in PIC code")); |
7a621144 DJ |
11775 | /* Quiet this warning. */ |
11776 | mips_frame_reg_valid = 1; | |
11777 | } | |
90ecf173 | 11778 | if (!mips_cprestore_valid) |
7a621144 | 11779 | { |
1661c76c | 11780 | as_warn (_("no .cprestore pseudo-op used in PIC code")); |
7a621144 DJ |
11781 | /* Quiet this warning. */ |
11782 | mips_cprestore_valid = 1; | |
11783 | } | |
6478892d | 11784 | if (mips_opts.noreorder) |
67c0d1eb | 11785 | macro_build (NULL, "nop", ""); |
6478892d | 11786 | expr1.X_add_number = mips_cprestore_offset; |
134c0c8b | 11787 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 11788 | mips_gp_register, |
256ab948 TS |
11789 | mips_frame_reg, |
11790 | HAVE_64BIT_ADDRESSES); | |
6478892d | 11791 | } |
252b5132 RH |
11792 | } |
11793 | } | |
0a44bf69 | 11794 | else if (mips_pic == VXWORKS_PIC) |
1661c76c | 11795 | as_bad (_("non-PIC jump used in PIC library")); |
252b5132 RH |
11796 | else |
11797 | abort (); | |
11798 | ||
8fc2e39e | 11799 | break; |
252b5132 | 11800 | |
7f3c4072 | 11801 | case M_LBUE_AB: |
7f3c4072 CM |
11802 | s = "lbue"; |
11803 | fmt = "t,+j(b)"; | |
11804 | offbits = 9; | |
11805 | goto ld_st; | |
11806 | case M_LHUE_AB: | |
7f3c4072 CM |
11807 | s = "lhue"; |
11808 | fmt = "t,+j(b)"; | |
11809 | offbits = 9; | |
11810 | goto ld_st; | |
11811 | case M_LBE_AB: | |
7f3c4072 CM |
11812 | s = "lbe"; |
11813 | fmt = "t,+j(b)"; | |
11814 | offbits = 9; | |
11815 | goto ld_st; | |
11816 | case M_LHE_AB: | |
7f3c4072 CM |
11817 | s = "lhe"; |
11818 | fmt = "t,+j(b)"; | |
11819 | offbits = 9; | |
11820 | goto ld_st; | |
11821 | case M_LLE_AB: | |
7f3c4072 CM |
11822 | s = "lle"; |
11823 | fmt = "t,+j(b)"; | |
11824 | offbits = 9; | |
11825 | goto ld_st; | |
11826 | case M_LWE_AB: | |
7f3c4072 CM |
11827 | s = "lwe"; |
11828 | fmt = "t,+j(b)"; | |
11829 | offbits = 9; | |
11830 | goto ld_st; | |
11831 | case M_LWLE_AB: | |
7f3c4072 CM |
11832 | s = "lwle"; |
11833 | fmt = "t,+j(b)"; | |
11834 | offbits = 9; | |
11835 | goto ld_st; | |
11836 | case M_LWRE_AB: | |
7f3c4072 CM |
11837 | s = "lwre"; |
11838 | fmt = "t,+j(b)"; | |
11839 | offbits = 9; | |
11840 | goto ld_st; | |
11841 | case M_SBE_AB: | |
7f3c4072 CM |
11842 | s = "sbe"; |
11843 | fmt = "t,+j(b)"; | |
11844 | offbits = 9; | |
11845 | goto ld_st; | |
11846 | case M_SCE_AB: | |
7f3c4072 CM |
11847 | s = "sce"; |
11848 | fmt = "t,+j(b)"; | |
11849 | offbits = 9; | |
11850 | goto ld_st; | |
11851 | case M_SHE_AB: | |
7f3c4072 CM |
11852 | s = "she"; |
11853 | fmt = "t,+j(b)"; | |
11854 | offbits = 9; | |
11855 | goto ld_st; | |
11856 | case M_SWE_AB: | |
7f3c4072 CM |
11857 | s = "swe"; |
11858 | fmt = "t,+j(b)"; | |
11859 | offbits = 9; | |
11860 | goto ld_st; | |
11861 | case M_SWLE_AB: | |
7f3c4072 CM |
11862 | s = "swle"; |
11863 | fmt = "t,+j(b)"; | |
11864 | offbits = 9; | |
11865 | goto ld_st; | |
11866 | case M_SWRE_AB: | |
7f3c4072 CM |
11867 | s = "swre"; |
11868 | fmt = "t,+j(b)"; | |
11869 | offbits = 9; | |
11870 | goto ld_st; | |
dec0624d | 11871 | case M_ACLR_AB: |
dec0624d | 11872 | s = "aclr"; |
dec0624d | 11873 | fmt = "\\,~(b)"; |
7f3c4072 | 11874 | offbits = 12; |
dec0624d MR |
11875 | goto ld_st; |
11876 | case M_ASET_AB: | |
dec0624d | 11877 | s = "aset"; |
dec0624d | 11878 | fmt = "\\,~(b)"; |
7f3c4072 | 11879 | offbits = 12; |
dec0624d | 11880 | goto ld_st; |
252b5132 RH |
11881 | case M_LB_AB: |
11882 | s = "lb"; | |
df58fc94 | 11883 | fmt = "t,o(b)"; |
252b5132 RH |
11884 | goto ld; |
11885 | case M_LBU_AB: | |
11886 | s = "lbu"; | |
df58fc94 | 11887 | fmt = "t,o(b)"; |
252b5132 RH |
11888 | goto ld; |
11889 | case M_LH_AB: | |
11890 | s = "lh"; | |
df58fc94 | 11891 | fmt = "t,o(b)"; |
252b5132 RH |
11892 | goto ld; |
11893 | case M_LHU_AB: | |
11894 | s = "lhu"; | |
df58fc94 | 11895 | fmt = "t,o(b)"; |
252b5132 RH |
11896 | goto ld; |
11897 | case M_LW_AB: | |
11898 | s = "lw"; | |
df58fc94 | 11899 | fmt = "t,o(b)"; |
252b5132 RH |
11900 | goto ld; |
11901 | case M_LWC0_AB: | |
df58fc94 | 11902 | gas_assert (!mips_opts.micromips); |
252b5132 | 11903 | s = "lwc0"; |
df58fc94 | 11904 | fmt = "E,o(b)"; |
bdaaa2e1 | 11905 | /* Itbl support may require additional care here. */ |
252b5132 | 11906 | coproc = 1; |
df58fc94 | 11907 | goto ld_st; |
252b5132 RH |
11908 | case M_LWC1_AB: |
11909 | s = "lwc1"; | |
df58fc94 | 11910 | fmt = "T,o(b)"; |
bdaaa2e1 | 11911 | /* Itbl support may require additional care here. */ |
252b5132 | 11912 | coproc = 1; |
df58fc94 | 11913 | goto ld_st; |
252b5132 RH |
11914 | case M_LWC2_AB: |
11915 | s = "lwc2"; | |
df58fc94 | 11916 | fmt = COP12_FMT; |
7361da2c AB |
11917 | offbits = (mips_opts.micromips ? 12 |
11918 | : ISA_IS_R6 (mips_opts.isa) ? 11 | |
11919 | : 16); | |
bdaaa2e1 | 11920 | /* Itbl support may require additional care here. */ |
252b5132 | 11921 | coproc = 1; |
df58fc94 | 11922 | goto ld_st; |
252b5132 | 11923 | case M_LWC3_AB: |
df58fc94 | 11924 | gas_assert (!mips_opts.micromips); |
252b5132 | 11925 | s = "lwc3"; |
df58fc94 | 11926 | fmt = "E,o(b)"; |
bdaaa2e1 | 11927 | /* Itbl support may require additional care here. */ |
252b5132 | 11928 | coproc = 1; |
df58fc94 | 11929 | goto ld_st; |
252b5132 RH |
11930 | case M_LWL_AB: |
11931 | s = "lwl"; | |
df58fc94 | 11932 | fmt = MEM12_FMT; |
7f3c4072 | 11933 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11934 | goto ld_st; |
252b5132 RH |
11935 | case M_LWR_AB: |
11936 | s = "lwr"; | |
df58fc94 | 11937 | fmt = MEM12_FMT; |
7f3c4072 | 11938 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11939 | goto ld_st; |
252b5132 | 11940 | case M_LDC1_AB: |
252b5132 | 11941 | s = "ldc1"; |
df58fc94 | 11942 | fmt = "T,o(b)"; |
bdaaa2e1 | 11943 | /* Itbl support may require additional care here. */ |
252b5132 | 11944 | coproc = 1; |
df58fc94 | 11945 | goto ld_st; |
252b5132 RH |
11946 | case M_LDC2_AB: |
11947 | s = "ldc2"; | |
df58fc94 | 11948 | fmt = COP12_FMT; |
7361da2c AB |
11949 | offbits = (mips_opts.micromips ? 12 |
11950 | : ISA_IS_R6 (mips_opts.isa) ? 11 | |
11951 | : 16); | |
bdaaa2e1 | 11952 | /* Itbl support may require additional care here. */ |
252b5132 | 11953 | coproc = 1; |
df58fc94 | 11954 | goto ld_st; |
c77c0862 | 11955 | case M_LQC2_AB: |
c77c0862 | 11956 | s = "lqc2"; |
14daeee3 | 11957 | fmt = "+7,o(b)"; |
c77c0862 RS |
11958 | /* Itbl support may require additional care here. */ |
11959 | coproc = 1; | |
11960 | goto ld_st; | |
252b5132 RH |
11961 | case M_LDC3_AB: |
11962 | s = "ldc3"; | |
df58fc94 | 11963 | fmt = "E,o(b)"; |
bdaaa2e1 | 11964 | /* Itbl support may require additional care here. */ |
252b5132 | 11965 | coproc = 1; |
df58fc94 | 11966 | goto ld_st; |
252b5132 RH |
11967 | case M_LDL_AB: |
11968 | s = "ldl"; | |
df58fc94 | 11969 | fmt = MEM12_FMT; |
7f3c4072 | 11970 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11971 | goto ld_st; |
252b5132 RH |
11972 | case M_LDR_AB: |
11973 | s = "ldr"; | |
df58fc94 | 11974 | fmt = MEM12_FMT; |
7f3c4072 | 11975 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11976 | goto ld_st; |
252b5132 RH |
11977 | case M_LL_AB: |
11978 | s = "ll"; | |
7361da2c AB |
11979 | fmt = LL_SC_FMT; |
11980 | offbits = (mips_opts.micromips ? 12 | |
11981 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
11982 | : 16); | |
252b5132 RH |
11983 | goto ld; |
11984 | case M_LLD_AB: | |
11985 | s = "lld"; | |
7361da2c AB |
11986 | fmt = LL_SC_FMT; |
11987 | offbits = (mips_opts.micromips ? 12 | |
11988 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
11989 | : 16); | |
252b5132 RH |
11990 | goto ld; |
11991 | case M_LWU_AB: | |
11992 | s = "lwu"; | |
df58fc94 | 11993 | fmt = MEM12_FMT; |
7f3c4072 | 11994 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
11995 | goto ld; |
11996 | case M_LWP_AB: | |
df58fc94 RS |
11997 | gas_assert (mips_opts.micromips); |
11998 | s = "lwp"; | |
11999 | fmt = "t,~(b)"; | |
7f3c4072 | 12000 | offbits = 12; |
df58fc94 RS |
12001 | lp = 1; |
12002 | goto ld; | |
12003 | case M_LDP_AB: | |
df58fc94 RS |
12004 | gas_assert (mips_opts.micromips); |
12005 | s = "ldp"; | |
12006 | fmt = "t,~(b)"; | |
7f3c4072 | 12007 | offbits = 12; |
df58fc94 RS |
12008 | lp = 1; |
12009 | goto ld; | |
12010 | case M_LWM_AB: | |
df58fc94 RS |
12011 | gas_assert (mips_opts.micromips); |
12012 | s = "lwm"; | |
12013 | fmt = "n,~(b)"; | |
7f3c4072 | 12014 | offbits = 12; |
df58fc94 RS |
12015 | goto ld_st; |
12016 | case M_LDM_AB: | |
df58fc94 RS |
12017 | gas_assert (mips_opts.micromips); |
12018 | s = "ldm"; | |
12019 | fmt = "n,~(b)"; | |
7f3c4072 | 12020 | offbits = 12; |
df58fc94 RS |
12021 | goto ld_st; |
12022 | ||
252b5132 | 12023 | ld: |
f19ccbda | 12024 | /* We don't want to use $0 as tempreg. */ |
c0ebe874 | 12025 | if (op[2] == op[0] + lp || op[0] + lp == ZERO) |
df58fc94 | 12026 | goto ld_st; |
252b5132 | 12027 | else |
c0ebe874 | 12028 | tempreg = op[0] + lp; |
df58fc94 RS |
12029 | goto ld_noat; |
12030 | ||
252b5132 RH |
12031 | case M_SB_AB: |
12032 | s = "sb"; | |
df58fc94 RS |
12033 | fmt = "t,o(b)"; |
12034 | goto ld_st; | |
252b5132 RH |
12035 | case M_SH_AB: |
12036 | s = "sh"; | |
df58fc94 RS |
12037 | fmt = "t,o(b)"; |
12038 | goto ld_st; | |
252b5132 RH |
12039 | case M_SW_AB: |
12040 | s = "sw"; | |
df58fc94 RS |
12041 | fmt = "t,o(b)"; |
12042 | goto ld_st; | |
252b5132 | 12043 | case M_SWC0_AB: |
df58fc94 | 12044 | gas_assert (!mips_opts.micromips); |
252b5132 | 12045 | s = "swc0"; |
df58fc94 | 12046 | fmt = "E,o(b)"; |
bdaaa2e1 | 12047 | /* Itbl support may require additional care here. */ |
252b5132 | 12048 | coproc = 1; |
df58fc94 | 12049 | goto ld_st; |
252b5132 RH |
12050 | case M_SWC1_AB: |
12051 | s = "swc1"; | |
df58fc94 | 12052 | fmt = "T,o(b)"; |
bdaaa2e1 | 12053 | /* Itbl support may require additional care here. */ |
252b5132 | 12054 | coproc = 1; |
df58fc94 | 12055 | goto ld_st; |
252b5132 RH |
12056 | case M_SWC2_AB: |
12057 | s = "swc2"; | |
df58fc94 | 12058 | fmt = COP12_FMT; |
7361da2c AB |
12059 | offbits = (mips_opts.micromips ? 12 |
12060 | : ISA_IS_R6 (mips_opts.isa) ? 11 | |
12061 | : 16); | |
bdaaa2e1 | 12062 | /* Itbl support may require additional care here. */ |
252b5132 | 12063 | coproc = 1; |
df58fc94 | 12064 | goto ld_st; |
252b5132 | 12065 | case M_SWC3_AB: |
df58fc94 | 12066 | gas_assert (!mips_opts.micromips); |
252b5132 | 12067 | s = "swc3"; |
df58fc94 | 12068 | fmt = "E,o(b)"; |
bdaaa2e1 | 12069 | /* Itbl support may require additional care here. */ |
252b5132 | 12070 | coproc = 1; |
df58fc94 | 12071 | goto ld_st; |
252b5132 RH |
12072 | case M_SWL_AB: |
12073 | s = "swl"; | |
df58fc94 | 12074 | fmt = MEM12_FMT; |
7f3c4072 | 12075 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 12076 | goto ld_st; |
252b5132 RH |
12077 | case M_SWR_AB: |
12078 | s = "swr"; | |
df58fc94 | 12079 | fmt = MEM12_FMT; |
7f3c4072 | 12080 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 12081 | goto ld_st; |
252b5132 RH |
12082 | case M_SC_AB: |
12083 | s = "sc"; | |
7361da2c AB |
12084 | fmt = LL_SC_FMT; |
12085 | offbits = (mips_opts.micromips ? 12 | |
12086 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
12087 | : 16); | |
df58fc94 | 12088 | goto ld_st; |
252b5132 RH |
12089 | case M_SCD_AB: |
12090 | s = "scd"; | |
7361da2c AB |
12091 | fmt = LL_SC_FMT; |
12092 | offbits = (mips_opts.micromips ? 12 | |
12093 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
12094 | : 16); | |
df58fc94 | 12095 | goto ld_st; |
d43b4baf TS |
12096 | case M_CACHE_AB: |
12097 | s = "cache"; | |
7361da2c AB |
12098 | fmt = (mips_opts.micromips ? "k,~(b)" |
12099 | : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)" | |
12100 | : "k,o(b)"); | |
12101 | offbits = (mips_opts.micromips ? 12 | |
12102 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
12103 | : 16); | |
7f3c4072 CM |
12104 | goto ld_st; |
12105 | case M_CACHEE_AB: | |
7f3c4072 CM |
12106 | s = "cachee"; |
12107 | fmt = "k,+j(b)"; | |
12108 | offbits = 9; | |
df58fc94 | 12109 | goto ld_st; |
3eebd5eb MR |
12110 | case M_PREF_AB: |
12111 | s = "pref"; | |
7361da2c AB |
12112 | fmt = (mips_opts.micromips ? "k,~(b)" |
12113 | : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)" | |
12114 | : "k,o(b)"); | |
12115 | offbits = (mips_opts.micromips ? 12 | |
12116 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
12117 | : 16); | |
7f3c4072 CM |
12118 | goto ld_st; |
12119 | case M_PREFE_AB: | |
7f3c4072 CM |
12120 | s = "prefe"; |
12121 | fmt = "k,+j(b)"; | |
12122 | offbits = 9; | |
df58fc94 | 12123 | goto ld_st; |
252b5132 | 12124 | case M_SDC1_AB: |
252b5132 | 12125 | s = "sdc1"; |
df58fc94 | 12126 | fmt = "T,o(b)"; |
252b5132 | 12127 | coproc = 1; |
bdaaa2e1 | 12128 | /* Itbl support may require additional care here. */ |
df58fc94 | 12129 | goto ld_st; |
252b5132 RH |
12130 | case M_SDC2_AB: |
12131 | s = "sdc2"; | |
df58fc94 | 12132 | fmt = COP12_FMT; |
7361da2c AB |
12133 | offbits = (mips_opts.micromips ? 12 |
12134 | : ISA_IS_R6 (mips_opts.isa) ? 11 | |
12135 | : 16); | |
c77c0862 RS |
12136 | /* Itbl support may require additional care here. */ |
12137 | coproc = 1; | |
12138 | goto ld_st; | |
12139 | case M_SQC2_AB: | |
c77c0862 | 12140 | s = "sqc2"; |
14daeee3 | 12141 | fmt = "+7,o(b)"; |
bdaaa2e1 | 12142 | /* Itbl support may require additional care here. */ |
252b5132 | 12143 | coproc = 1; |
df58fc94 | 12144 | goto ld_st; |
252b5132 | 12145 | case M_SDC3_AB: |
df58fc94 | 12146 | gas_assert (!mips_opts.micromips); |
252b5132 | 12147 | s = "sdc3"; |
df58fc94 | 12148 | fmt = "E,o(b)"; |
bdaaa2e1 | 12149 | /* Itbl support may require additional care here. */ |
252b5132 | 12150 | coproc = 1; |
df58fc94 | 12151 | goto ld_st; |
252b5132 RH |
12152 | case M_SDL_AB: |
12153 | s = "sdl"; | |
df58fc94 | 12154 | fmt = MEM12_FMT; |
7f3c4072 | 12155 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 12156 | goto ld_st; |
252b5132 RH |
12157 | case M_SDR_AB: |
12158 | s = "sdr"; | |
df58fc94 | 12159 | fmt = MEM12_FMT; |
7f3c4072 | 12160 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
12161 | goto ld_st; |
12162 | case M_SWP_AB: | |
df58fc94 RS |
12163 | gas_assert (mips_opts.micromips); |
12164 | s = "swp"; | |
12165 | fmt = "t,~(b)"; | |
7f3c4072 | 12166 | offbits = 12; |
df58fc94 RS |
12167 | goto ld_st; |
12168 | case M_SDP_AB: | |
df58fc94 RS |
12169 | gas_assert (mips_opts.micromips); |
12170 | s = "sdp"; | |
12171 | fmt = "t,~(b)"; | |
7f3c4072 | 12172 | offbits = 12; |
df58fc94 RS |
12173 | goto ld_st; |
12174 | case M_SWM_AB: | |
df58fc94 RS |
12175 | gas_assert (mips_opts.micromips); |
12176 | s = "swm"; | |
12177 | fmt = "n,~(b)"; | |
7f3c4072 | 12178 | offbits = 12; |
df58fc94 RS |
12179 | goto ld_st; |
12180 | case M_SDM_AB: | |
df58fc94 RS |
12181 | gas_assert (mips_opts.micromips); |
12182 | s = "sdm"; | |
12183 | fmt = "n,~(b)"; | |
7f3c4072 | 12184 | offbits = 12; |
df58fc94 RS |
12185 | |
12186 | ld_st: | |
8fc2e39e | 12187 | tempreg = AT; |
df58fc94 | 12188 | ld_noat: |
c0ebe874 | 12189 | breg = op[2]; |
f2ae14a1 RS |
12190 | if (small_offset_p (0, align, 16)) |
12191 | { | |
12192 | /* The first case exists for M_LD_AB and M_SD_AB, which are | |
12193 | macros for o32 but which should act like normal instructions | |
12194 | otherwise. */ | |
12195 | if (offbits == 16) | |
c0ebe874 | 12196 | macro_build (&offset_expr, s, fmt, op[0], -1, offset_reloc[0], |
f2ae14a1 RS |
12197 | offset_reloc[1], offset_reloc[2], breg); |
12198 | else if (small_offset_p (0, align, offbits)) | |
12199 | { | |
12200 | if (offbits == 0) | |
c0ebe874 | 12201 | macro_build (NULL, s, fmt, op[0], breg); |
f2ae14a1 | 12202 | else |
c0ebe874 | 12203 | macro_build (NULL, s, fmt, op[0], |
c8276761 | 12204 | (int) offset_expr.X_add_number, breg); |
f2ae14a1 RS |
12205 | } |
12206 | else | |
12207 | { | |
12208 | if (tempreg == AT) | |
12209 | used_at = 1; | |
12210 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
12211 | tempreg, breg, -1, offset_reloc[0], | |
12212 | offset_reloc[1], offset_reloc[2]); | |
12213 | if (offbits == 0) | |
c0ebe874 | 12214 | macro_build (NULL, s, fmt, op[0], tempreg); |
f2ae14a1 | 12215 | else |
c0ebe874 | 12216 | macro_build (NULL, s, fmt, op[0], 0, tempreg); |
f2ae14a1 RS |
12217 | } |
12218 | break; | |
12219 | } | |
12220 | ||
12221 | if (tempreg == AT) | |
12222 | used_at = 1; | |
12223 | ||
252b5132 RH |
12224 | if (offset_expr.X_op != O_constant |
12225 | && offset_expr.X_op != O_symbol) | |
12226 | { | |
1661c76c | 12227 | as_bad (_("expression too complex")); |
252b5132 RH |
12228 | offset_expr.X_op = O_constant; |
12229 | } | |
12230 | ||
2051e8c4 MR |
12231 | if (HAVE_32BIT_ADDRESSES |
12232 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
12233 | { |
12234 | char value [32]; | |
12235 | ||
12236 | sprintf_vma (value, offset_expr.X_add_number); | |
1661c76c | 12237 | as_bad (_("number (0x%s) larger than 32 bits"), value); |
55e08f71 | 12238 | } |
2051e8c4 | 12239 | |
252b5132 RH |
12240 | /* A constant expression in PIC code can be handled just as it |
12241 | is in non PIC code. */ | |
aed1a261 RS |
12242 | if (offset_expr.X_op == O_constant) |
12243 | { | |
f2ae14a1 RS |
12244 | expr1.X_add_number = offset_high_part (offset_expr.X_add_number, |
12245 | offbits == 0 ? 16 : offbits); | |
12246 | offset_expr.X_add_number -= expr1.X_add_number; | |
df58fc94 | 12247 | |
f2ae14a1 RS |
12248 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); |
12249 | if (breg != 0) | |
12250 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
12251 | tempreg, tempreg, breg); | |
7f3c4072 | 12252 | if (offbits == 0) |
dd6a37e7 | 12253 | { |
f2ae14a1 | 12254 | if (offset_expr.X_add_number != 0) |
dd6a37e7 | 12255 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
f2ae14a1 | 12256 | "t,r,j", tempreg, tempreg, BFD_RELOC_LO16); |
c0ebe874 | 12257 | macro_build (NULL, s, fmt, op[0], tempreg); |
dd6a37e7 | 12258 | } |
7f3c4072 | 12259 | else if (offbits == 16) |
c0ebe874 | 12260 | macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, tempreg); |
df58fc94 | 12261 | else |
c0ebe874 | 12262 | macro_build (NULL, s, fmt, op[0], |
c8276761 | 12263 | (int) offset_expr.X_add_number, tempreg); |
df58fc94 | 12264 | } |
7f3c4072 | 12265 | else if (offbits != 16) |
df58fc94 | 12266 | { |
7f3c4072 | 12267 | /* The offset field is too narrow to be used for a low-part |
2b0f3761 | 12268 | relocation, so load the whole address into the auxiliary |
f2ae14a1 RS |
12269 | register. */ |
12270 | load_address (tempreg, &offset_expr, &used_at); | |
12271 | if (breg != 0) | |
12272 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
12273 | tempreg, tempreg, breg); | |
7f3c4072 | 12274 | if (offbits == 0) |
c0ebe874 | 12275 | macro_build (NULL, s, fmt, op[0], tempreg); |
dd6a37e7 | 12276 | else |
c0ebe874 | 12277 | macro_build (NULL, s, fmt, op[0], 0, tempreg); |
aed1a261 RS |
12278 | } |
12279 | else if (mips_pic == NO_PIC) | |
252b5132 RH |
12280 | { |
12281 | /* If this is a reference to a GP relative symbol, and there | |
12282 | is no base register, we want | |
c0ebe874 | 12283 | <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
12284 | Otherwise, if there is no base register, we want |
12285 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
c0ebe874 | 12286 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
252b5132 RH |
12287 | If we have a constant, we need two instructions anyhow, |
12288 | so we always use the latter form. | |
12289 | ||
12290 | If we have a base register, and this is a reference to a | |
12291 | GP relative symbol, we want | |
12292 | addu $tempreg,$breg,$gp | |
c0ebe874 | 12293 | <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
12294 | Otherwise we want |
12295 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
12296 | addu $tempreg,$tempreg,$breg | |
c0ebe874 | 12297 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
d6bc6245 | 12298 | With a constant we always use the latter case. |
76b3015f | 12299 | |
d6bc6245 TS |
12300 | With 64bit address space and no base register and $at usable, |
12301 | we want | |
12302 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
12303 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
12304 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
12305 | dsll32 $tempreg,0 | |
12306 | daddu $tempreg,$at | |
c0ebe874 | 12307 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
d6bc6245 TS |
12308 | If we have a base register, we want |
12309 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
12310 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
12311 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
12312 | daddu $at,$breg | |
12313 | dsll32 $tempreg,0 | |
12314 | daddu $tempreg,$at | |
c0ebe874 | 12315 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
d6bc6245 TS |
12316 | |
12317 | Without $at we can't generate the optimal path for superscalar | |
12318 | processors here since this would require two temporary registers. | |
12319 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
12320 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
12321 | dsll $tempreg,16 | |
12322 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
12323 | dsll $tempreg,16 | |
c0ebe874 | 12324 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
d6bc6245 TS |
12325 | If we have a base register, we want |
12326 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
12327 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
12328 | dsll $tempreg,16 | |
12329 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
12330 | dsll $tempreg,16 | |
12331 | daddu $tempreg,$tempreg,$breg | |
c0ebe874 | 12332 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
6373ee54 | 12333 | |
6caf9ef4 | 12334 | For GP relative symbols in 64bit address space we can use |
aed1a261 RS |
12335 | the same sequence as in 32bit address space. */ |
12336 | if (HAVE_64BIT_SYMBOLS) | |
d6bc6245 | 12337 | { |
aed1a261 | 12338 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 TS |
12339 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
12340 | { | |
12341 | relax_start (offset_expr.X_add_symbol); | |
12342 | if (breg == 0) | |
12343 | { | |
c0ebe874 | 12344 | macro_build (&offset_expr, s, fmt, op[0], |
6caf9ef4 TS |
12345 | BFD_RELOC_GPREL16, mips_gp_register); |
12346 | } | |
12347 | else | |
12348 | { | |
12349 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
12350 | tempreg, breg, mips_gp_register); | |
c0ebe874 | 12351 | macro_build (&offset_expr, s, fmt, op[0], |
6caf9ef4 TS |
12352 | BFD_RELOC_GPREL16, tempreg); |
12353 | } | |
12354 | relax_switch (); | |
12355 | } | |
d6bc6245 | 12356 | |
741fe287 | 12357 | if (used_at == 0 && mips_opts.at) |
d6bc6245 | 12358 | { |
df58fc94 | 12359 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb | 12360 | BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 12361 | macro_build (&offset_expr, "lui", LUI_FMT, AT, |
67c0d1eb RS |
12362 | BFD_RELOC_HI16_S); |
12363 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
12364 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 12365 | if (breg != 0) |
67c0d1eb | 12366 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
df58fc94 | 12367 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb | 12368 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
c0ebe874 | 12369 | macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, |
67c0d1eb | 12370 | tempreg); |
d6bc6245 TS |
12371 | used_at = 1; |
12372 | } | |
12373 | else | |
12374 | { | |
df58fc94 | 12375 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb RS |
12376 | BFD_RELOC_MIPS_HIGHEST); |
12377 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
12378 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 12379 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb RS |
12380 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, |
12381 | tempreg, BFD_RELOC_HI16_S); | |
df58fc94 | 12382 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
d6bc6245 | 12383 | if (breg != 0) |
67c0d1eb | 12384 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 12385 | tempreg, tempreg, breg); |
c0ebe874 | 12386 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12387 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 12388 | } |
6caf9ef4 TS |
12389 | |
12390 | if (mips_relax.sequence) | |
12391 | relax_end (); | |
8fc2e39e | 12392 | break; |
d6bc6245 | 12393 | } |
256ab948 | 12394 | |
252b5132 RH |
12395 | if (breg == 0) |
12396 | { | |
67c0d1eb | 12397 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 12398 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 12399 | { |
4d7206a2 | 12400 | relax_start (offset_expr.X_add_symbol); |
c0ebe874 | 12401 | macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_GPREL16, |
67c0d1eb | 12402 | mips_gp_register); |
4d7206a2 | 12403 | relax_switch (); |
252b5132 | 12404 | } |
67c0d1eb | 12405 | macro_build_lui (&offset_expr, tempreg); |
c0ebe874 | 12406 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12407 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
12408 | if (mips_relax.sequence) |
12409 | relax_end (); | |
252b5132 RH |
12410 | } |
12411 | else | |
12412 | { | |
67c0d1eb | 12413 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 12414 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 12415 | { |
4d7206a2 | 12416 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 12417 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12418 | tempreg, breg, mips_gp_register); |
c0ebe874 | 12419 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12420 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 12421 | relax_switch (); |
252b5132 | 12422 | } |
67c0d1eb RS |
12423 | macro_build_lui (&offset_expr, tempreg); |
12424 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 12425 | tempreg, tempreg, breg); |
c0ebe874 | 12426 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12427 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
12428 | if (mips_relax.sequence) |
12429 | relax_end (); | |
252b5132 RH |
12430 | } |
12431 | } | |
0a44bf69 | 12432 | else if (!mips_big_got) |
252b5132 | 12433 | { |
ed6fb7bd | 12434 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 12435 | |
252b5132 RH |
12436 | /* If this is a reference to an external symbol, we want |
12437 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
12438 | nop | |
c0ebe874 | 12439 | <op> op[0],0($tempreg) |
252b5132 RH |
12440 | Otherwise we want |
12441 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
12442 | nop | |
12443 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
c0ebe874 | 12444 | <op> op[0],0($tempreg) |
f5040a92 AO |
12445 | |
12446 | For NewABI, we want | |
12447 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
c0ebe874 | 12448 | <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) |
f5040a92 | 12449 | |
252b5132 RH |
12450 | If there is a base register, we add it to $tempreg before |
12451 | the <op>. If there is a constant, we stick it in the | |
12452 | <op> instruction. We don't handle constants larger than | |
12453 | 16 bits, because we have no way to load the upper 16 bits | |
12454 | (actually, we could handle them for the subset of cases | |
12455 | in which we are not using $at). */ | |
9c2799c2 | 12456 | gas_assert (offset_expr.X_op == O_symbol); |
f5040a92 AO |
12457 | if (HAVE_NEWABI) |
12458 | { | |
67c0d1eb RS |
12459 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
12460 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 12461 | if (breg != 0) |
67c0d1eb | 12462 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12463 | tempreg, tempreg, breg); |
c0ebe874 | 12464 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12465 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
12466 | break; |
12467 | } | |
252b5132 RH |
12468 | expr1.X_add_number = offset_expr.X_add_number; |
12469 | offset_expr.X_add_number = 0; | |
12470 | if (expr1.X_add_number < -0x8000 | |
12471 | || expr1.X_add_number >= 0x8000) | |
12472 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
12473 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
12474 | lw_reloc_type, mips_gp_register); | |
269137b2 | 12475 | load_delay_nop (); |
4d7206a2 RS |
12476 | relax_start (offset_expr.X_add_symbol); |
12477 | relax_switch (); | |
67c0d1eb RS |
12478 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
12479 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 12480 | relax_end (); |
252b5132 | 12481 | if (breg != 0) |
67c0d1eb | 12482 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12483 | tempreg, tempreg, breg); |
c0ebe874 | 12484 | macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg); |
252b5132 | 12485 | } |
0a44bf69 | 12486 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 12487 | { |
67c0d1eb | 12488 | int gpdelay; |
252b5132 RH |
12489 | |
12490 | /* If this is a reference to an external symbol, we want | |
12491 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
12492 | addu $tempreg,$tempreg,$gp | |
12493 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
c0ebe874 | 12494 | <op> op[0],0($tempreg) |
252b5132 RH |
12495 | Otherwise we want |
12496 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
12497 | nop | |
12498 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
c0ebe874 | 12499 | <op> op[0],0($tempreg) |
252b5132 RH |
12500 | If there is a base register, we add it to $tempreg before |
12501 | the <op>. If there is a constant, we stick it in the | |
12502 | <op> instruction. We don't handle constants larger than | |
12503 | 16 bits, because we have no way to load the upper 16 bits | |
12504 | (actually, we could handle them for the subset of cases | |
f5040a92 | 12505 | in which we are not using $at). */ |
9c2799c2 | 12506 | gas_assert (offset_expr.X_op == O_symbol); |
252b5132 RH |
12507 | expr1.X_add_number = offset_expr.X_add_number; |
12508 | offset_expr.X_add_number = 0; | |
12509 | if (expr1.X_add_number < -0x8000 | |
12510 | || expr1.X_add_number >= 0x8000) | |
12511 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 12512 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 12513 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 12514 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 12515 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
12516 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
12517 | mips_gp_register); | |
12518 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
12519 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 12520 | relax_switch (); |
67c0d1eb RS |
12521 | if (gpdelay) |
12522 | macro_build (NULL, "nop", ""); | |
12523 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
12524 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 12525 | load_delay_nop (); |
67c0d1eb RS |
12526 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
12527 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
12528 | relax_end (); |
12529 | ||
252b5132 | 12530 | if (breg != 0) |
67c0d1eb | 12531 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12532 | tempreg, tempreg, breg); |
c0ebe874 | 12533 | macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg); |
252b5132 | 12534 | } |
0a44bf69 | 12535 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 12536 | { |
f5040a92 AO |
12537 | /* If this is a reference to an external symbol, we want |
12538 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
12539 | add $tempreg,$tempreg,$gp | |
12540 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
c0ebe874 | 12541 | <op> op[0],<ofst>($tempreg) |
f5040a92 AO |
12542 | Otherwise, for local symbols, we want: |
12543 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
c0ebe874 | 12544 | <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ |
9c2799c2 | 12545 | gas_assert (offset_expr.X_op == O_symbol); |
4d7206a2 | 12546 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
12547 | offset_expr.X_add_number = 0; |
12548 | if (expr1.X_add_number < -0x8000 | |
12549 | || expr1.X_add_number >= 0x8000) | |
12550 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 12551 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 12552 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 12553 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
12554 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
12555 | mips_gp_register); | |
12556 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
12557 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 12558 | if (breg != 0) |
67c0d1eb | 12559 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12560 | tempreg, tempreg, breg); |
c0ebe874 | 12561 | macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg); |
684022ea | 12562 | |
4d7206a2 | 12563 | relax_switch (); |
f5040a92 | 12564 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
12565 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
12566 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 12567 | if (breg != 0) |
67c0d1eb | 12568 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12569 | tempreg, tempreg, breg); |
c0ebe874 | 12570 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12571 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 12572 | relax_end (); |
f5040a92 | 12573 | } |
252b5132 RH |
12574 | else |
12575 | abort (); | |
12576 | ||
252b5132 RH |
12577 | break; |
12578 | ||
833794fc MR |
12579 | case M_JRADDIUSP: |
12580 | gas_assert (mips_opts.micromips); | |
12581 | gas_assert (mips_opts.insn32); | |
12582 | start_noreorder (); | |
12583 | macro_build (NULL, "jr", "s", RA); | |
c0ebe874 | 12584 | expr1.X_add_number = op[0] << 2; |
833794fc MR |
12585 | macro_build (&expr1, "addiu", "t,r,j", SP, SP, BFD_RELOC_LO16); |
12586 | end_noreorder (); | |
12587 | break; | |
12588 | ||
12589 | case M_JRC: | |
12590 | gas_assert (mips_opts.micromips); | |
12591 | gas_assert (mips_opts.insn32); | |
c0ebe874 | 12592 | macro_build (NULL, "jr", "s", op[0]); |
833794fc MR |
12593 | if (mips_opts.noreorder) |
12594 | macro_build (NULL, "nop", ""); | |
12595 | break; | |
12596 | ||
252b5132 RH |
12597 | case M_LI: |
12598 | case M_LI_S: | |
c0ebe874 | 12599 | load_register (op[0], &imm_expr, 0); |
8fc2e39e | 12600 | break; |
252b5132 RH |
12601 | |
12602 | case M_DLI: | |
c0ebe874 | 12603 | load_register (op[0], &imm_expr, 1); |
8fc2e39e | 12604 | break; |
252b5132 RH |
12605 | |
12606 | case M_LI_SS: | |
12607 | if (imm_expr.X_op == O_constant) | |
12608 | { | |
8fc2e39e | 12609 | used_at = 1; |
67c0d1eb | 12610 | load_register (AT, &imm_expr, 0); |
c0ebe874 | 12611 | macro_build (NULL, "mtc1", "t,G", AT, op[0]); |
252b5132 RH |
12612 | break; |
12613 | } | |
12614 | else | |
12615 | { | |
b0e6f033 RS |
12616 | gas_assert (imm_expr.X_op == O_absent |
12617 | && offset_expr.X_op == O_symbol | |
90ecf173 MR |
12618 | && strcmp (segment_name (S_GET_SEGMENT |
12619 | (offset_expr.X_add_symbol)), | |
12620 | ".lit4") == 0 | |
12621 | && offset_expr.X_add_number == 0); | |
c0ebe874 | 12622 | macro_build (&offset_expr, "lwc1", "T,o(b)", op[0], |
17a2f251 | 12623 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 12624 | break; |
252b5132 RH |
12625 | } |
12626 | ||
12627 | case M_LI_D: | |
ca4e0257 RS |
12628 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
12629 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
12630 | order 32 bits of the value and the low order 32 bits are either | |
12631 | zero or in OFFSET_EXPR. */ | |
b0e6f033 | 12632 | if (imm_expr.X_op == O_constant) |
252b5132 | 12633 | { |
bad1aba3 | 12634 | if (GPR_SIZE == 64) |
c0ebe874 | 12635 | load_register (op[0], &imm_expr, 1); |
252b5132 RH |
12636 | else |
12637 | { | |
12638 | int hreg, lreg; | |
12639 | ||
12640 | if (target_big_endian) | |
12641 | { | |
c0ebe874 RS |
12642 | hreg = op[0]; |
12643 | lreg = op[0] + 1; | |
252b5132 RH |
12644 | } |
12645 | else | |
12646 | { | |
c0ebe874 RS |
12647 | hreg = op[0] + 1; |
12648 | lreg = op[0]; | |
252b5132 RH |
12649 | } |
12650 | ||
12651 | if (hreg <= 31) | |
67c0d1eb | 12652 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
12653 | if (lreg <= 31) |
12654 | { | |
12655 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 12656 | move_register (lreg, 0); |
252b5132 RH |
12657 | else |
12658 | { | |
9c2799c2 | 12659 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb | 12660 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
12661 | } |
12662 | } | |
12663 | } | |
8fc2e39e | 12664 | break; |
252b5132 | 12665 | } |
b0e6f033 | 12666 | gas_assert (imm_expr.X_op == O_absent); |
252b5132 RH |
12667 | |
12668 | /* We know that sym is in the .rdata section. First we get the | |
12669 | upper 16 bits of the address. */ | |
12670 | if (mips_pic == NO_PIC) | |
12671 | { | |
67c0d1eb | 12672 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 12673 | used_at = 1; |
252b5132 | 12674 | } |
0a44bf69 | 12675 | else |
252b5132 | 12676 | { |
67c0d1eb RS |
12677 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
12678 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 12679 | used_at = 1; |
252b5132 | 12680 | } |
bdaaa2e1 | 12681 | |
252b5132 | 12682 | /* Now we load the register(s). */ |
bad1aba3 | 12683 | if (GPR_SIZE == 64) |
8fc2e39e TS |
12684 | { |
12685 | used_at = 1; | |
c0ebe874 RS |
12686 | macro_build (&offset_expr, "ld", "t,o(b)", op[0], |
12687 | BFD_RELOC_LO16, AT); | |
8fc2e39e | 12688 | } |
252b5132 RH |
12689 | else |
12690 | { | |
8fc2e39e | 12691 | used_at = 1; |
c0ebe874 RS |
12692 | macro_build (&offset_expr, "lw", "t,o(b)", op[0], |
12693 | BFD_RELOC_LO16, AT); | |
12694 | if (op[0] != RA) | |
252b5132 RH |
12695 | { |
12696 | /* FIXME: How in the world do we deal with the possible | |
12697 | overflow here? */ | |
12698 | offset_expr.X_add_number += 4; | |
67c0d1eb | 12699 | macro_build (&offset_expr, "lw", "t,o(b)", |
c0ebe874 | 12700 | op[0] + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
12701 | } |
12702 | } | |
252b5132 RH |
12703 | break; |
12704 | ||
12705 | case M_LI_DD: | |
ca4e0257 RS |
12706 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
12707 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
12708 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
12709 | the value and the low order 32 bits are either zero or in | |
12710 | OFFSET_EXPR. */ | |
b0e6f033 | 12711 | if (imm_expr.X_op == O_constant) |
252b5132 | 12712 | { |
8fc2e39e | 12713 | used_at = 1; |
bad1aba3 | 12714 | load_register (AT, &imm_expr, FPR_SIZE == 64); |
351cdf24 MF |
12715 | if (FPR_SIZE == 64 && GPR_SIZE == 64) |
12716 | macro_build (NULL, "dmtc1", "t,S", AT, op[0]); | |
252b5132 RH |
12717 | else |
12718 | { | |
351cdf24 MF |
12719 | if (ISA_HAS_MXHC1 (mips_opts.isa)) |
12720 | macro_build (NULL, "mthc1", "t,G", AT, op[0]); | |
12721 | else if (FPR_SIZE != 32) | |
12722 | as_bad (_("Unable to generate `%s' compliant code " | |
12723 | "without mthc1"), | |
12724 | (FPR_SIZE == 64) ? "fp64" : "fpxx"); | |
12725 | else | |
12726 | macro_build (NULL, "mtc1", "t,G", AT, op[0] + 1); | |
252b5132 | 12727 | if (offset_expr.X_op == O_absent) |
c0ebe874 | 12728 | macro_build (NULL, "mtc1", "t,G", 0, op[0]); |
252b5132 RH |
12729 | else |
12730 | { | |
9c2799c2 | 12731 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb | 12732 | load_register (AT, &offset_expr, 0); |
c0ebe874 | 12733 | macro_build (NULL, "mtc1", "t,G", AT, op[0]); |
252b5132 RH |
12734 | } |
12735 | } | |
12736 | break; | |
12737 | } | |
12738 | ||
b0e6f033 RS |
12739 | gas_assert (imm_expr.X_op == O_absent |
12740 | && offset_expr.X_op == O_symbol | |
90ecf173 | 12741 | && offset_expr.X_add_number == 0); |
252b5132 RH |
12742 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); |
12743 | if (strcmp (s, ".lit8") == 0) | |
134c0c8b MR |
12744 | { |
12745 | op[2] = mips_gp_register; | |
f2ae14a1 RS |
12746 | offset_reloc[0] = BFD_RELOC_MIPS_LITERAL; |
12747 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
12748 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
12749 | } |
12750 | else | |
12751 | { | |
9c2799c2 | 12752 | gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
8fc2e39e | 12753 | used_at = 1; |
0a44bf69 | 12754 | if (mips_pic != NO_PIC) |
67c0d1eb RS |
12755 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
12756 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
12757 | else |
12758 | { | |
12759 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 12760 | macro_build_lui (&offset_expr, AT); |
252b5132 | 12761 | } |
bdaaa2e1 | 12762 | |
c0ebe874 | 12763 | op[2] = AT; |
f2ae14a1 RS |
12764 | offset_reloc[0] = BFD_RELOC_LO16; |
12765 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
12766 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
134c0c8b | 12767 | } |
f2ae14a1 | 12768 | align = 8; |
6f2117ba | 12769 | /* Fall through. */ |
c4a68bea | 12770 | |
252b5132 | 12771 | case M_L_DAB: |
6f2117ba PH |
12772 | /* The MIPS assembler seems to check for X_add_number not |
12773 | being double aligned and generating: | |
12774 | lui at,%hi(foo+1) | |
12775 | addu at,at,v1 | |
12776 | addiu at,at,%lo(foo+1) | |
12777 | lwc1 f2,0(at) | |
12778 | lwc1 f3,4(at) | |
12779 | But, the resulting address is the same after relocation so why | |
12780 | generate the extra instruction? */ | |
bdaaa2e1 | 12781 | /* Itbl support may require additional care here. */ |
252b5132 | 12782 | coproc = 1; |
df58fc94 | 12783 | fmt = "T,o(b)"; |
0aa27725 | 12784 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch)) |
252b5132 RH |
12785 | { |
12786 | s = "ldc1"; | |
df58fc94 | 12787 | goto ld_st; |
252b5132 | 12788 | } |
252b5132 | 12789 | s = "lwc1"; |
252b5132 RH |
12790 | goto ldd_std; |
12791 | ||
12792 | case M_S_DAB: | |
df58fc94 RS |
12793 | gas_assert (!mips_opts.micromips); |
12794 | /* Itbl support may require additional care here. */ | |
12795 | coproc = 1; | |
12796 | fmt = "T,o(b)"; | |
0aa27725 | 12797 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch)) |
252b5132 RH |
12798 | { |
12799 | s = "sdc1"; | |
df58fc94 | 12800 | goto ld_st; |
252b5132 | 12801 | } |
252b5132 | 12802 | s = "swc1"; |
252b5132 RH |
12803 | goto ldd_std; |
12804 | ||
e407c74b NC |
12805 | case M_LQ_AB: |
12806 | fmt = "t,o(b)"; | |
12807 | s = "lq"; | |
12808 | goto ld; | |
12809 | ||
12810 | case M_SQ_AB: | |
12811 | fmt = "t,o(b)"; | |
12812 | s = "sq"; | |
12813 | goto ld_st; | |
12814 | ||
252b5132 | 12815 | case M_LD_AB: |
df58fc94 | 12816 | fmt = "t,o(b)"; |
bad1aba3 | 12817 | if (GPR_SIZE == 64) |
252b5132 RH |
12818 | { |
12819 | s = "ld"; | |
12820 | goto ld; | |
12821 | } | |
252b5132 | 12822 | s = "lw"; |
252b5132 RH |
12823 | goto ldd_std; |
12824 | ||
12825 | case M_SD_AB: | |
df58fc94 | 12826 | fmt = "t,o(b)"; |
bad1aba3 | 12827 | if (GPR_SIZE == 64) |
252b5132 RH |
12828 | { |
12829 | s = "sd"; | |
df58fc94 | 12830 | goto ld_st; |
252b5132 | 12831 | } |
252b5132 | 12832 | s = "sw"; |
252b5132 RH |
12833 | |
12834 | ldd_std: | |
f2ae14a1 RS |
12835 | /* Even on a big endian machine $fn comes before $fn+1. We have |
12836 | to adjust when loading from memory. We set coproc if we must | |
12837 | load $fn+1 first. */ | |
12838 | /* Itbl support may require additional care here. */ | |
12839 | if (!target_big_endian) | |
12840 | coproc = 0; | |
12841 | ||
c0ebe874 | 12842 | breg = op[2]; |
f2ae14a1 RS |
12843 | if (small_offset_p (0, align, 16)) |
12844 | { | |
12845 | ep = &offset_expr; | |
12846 | if (!small_offset_p (4, align, 16)) | |
12847 | { | |
12848 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT, breg, | |
12849 | -1, offset_reloc[0], offset_reloc[1], | |
12850 | offset_reloc[2]); | |
12851 | expr1.X_add_number = 0; | |
12852 | ep = &expr1; | |
12853 | breg = AT; | |
12854 | used_at = 1; | |
12855 | offset_reloc[0] = BFD_RELOC_LO16; | |
12856 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
12857 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
12858 | } | |
c0ebe874 | 12859 | if (strcmp (s, "lw") == 0 && op[0] == breg) |
f2ae14a1 RS |
12860 | { |
12861 | ep->X_add_number += 4; | |
c0ebe874 | 12862 | macro_build (ep, s, fmt, op[0] + 1, -1, offset_reloc[0], |
f2ae14a1 RS |
12863 | offset_reloc[1], offset_reloc[2], breg); |
12864 | ep->X_add_number -= 4; | |
c0ebe874 | 12865 | macro_build (ep, s, fmt, op[0], -1, offset_reloc[0], |
f2ae14a1 RS |
12866 | offset_reloc[1], offset_reloc[2], breg); |
12867 | } | |
12868 | else | |
12869 | { | |
c0ebe874 | 12870 | macro_build (ep, s, fmt, coproc ? op[0] + 1 : op[0], -1, |
f2ae14a1 RS |
12871 | offset_reloc[0], offset_reloc[1], offset_reloc[2], |
12872 | breg); | |
12873 | ep->X_add_number += 4; | |
c0ebe874 | 12874 | macro_build (ep, s, fmt, coproc ? op[0] : op[0] + 1, -1, |
f2ae14a1 RS |
12875 | offset_reloc[0], offset_reloc[1], offset_reloc[2], |
12876 | breg); | |
12877 | } | |
12878 | break; | |
12879 | } | |
12880 | ||
252b5132 RH |
12881 | if (offset_expr.X_op != O_symbol |
12882 | && offset_expr.X_op != O_constant) | |
12883 | { | |
1661c76c | 12884 | as_bad (_("expression too complex")); |
252b5132 RH |
12885 | offset_expr.X_op = O_constant; |
12886 | } | |
12887 | ||
2051e8c4 MR |
12888 | if (HAVE_32BIT_ADDRESSES |
12889 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
12890 | { |
12891 | char value [32]; | |
12892 | ||
12893 | sprintf_vma (value, offset_expr.X_add_number); | |
1661c76c | 12894 | as_bad (_("number (0x%s) larger than 32 bits"), value); |
55e08f71 | 12895 | } |
2051e8c4 | 12896 | |
90ecf173 | 12897 | if (mips_pic == NO_PIC || offset_expr.X_op == O_constant) |
252b5132 RH |
12898 | { |
12899 | /* If this is a reference to a GP relative symbol, we want | |
c0ebe874 RS |
12900 | <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16) |
12901 | <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
12902 | If we have a base register, we use this |
12903 | addu $at,$breg,$gp | |
c0ebe874 RS |
12904 | <op> op[0],<sym>($at) (BFD_RELOC_GPREL16) |
12905 | <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
12906 | If this is not a GP relative symbol, we want |
12907 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
c0ebe874 RS |
12908 | <op> op[0],<sym>($at) (BFD_RELOC_LO16) |
12909 | <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16) | |
252b5132 RH |
12910 | If there is a base register, we add it to $at after the |
12911 | lui instruction. If there is a constant, we always use | |
12912 | the last case. */ | |
39a59cf8 MR |
12913 | if (offset_expr.X_op == O_symbol |
12914 | && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 12915 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 12916 | { |
4d7206a2 | 12917 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
12918 | if (breg == 0) |
12919 | { | |
c9914766 | 12920 | tempreg = mips_gp_register; |
252b5132 RH |
12921 | } |
12922 | else | |
12923 | { | |
67c0d1eb | 12924 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12925 | AT, breg, mips_gp_register); |
252b5132 | 12926 | tempreg = AT; |
252b5132 RH |
12927 | used_at = 1; |
12928 | } | |
12929 | ||
beae10d5 | 12930 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12931 | macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], |
17a2f251 | 12932 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
12933 | offset_expr.X_add_number += 4; |
12934 | ||
12935 | /* Set mips_optimize to 2 to avoid inserting an | |
12936 | undesired nop. */ | |
12937 | hold_mips_optimize = mips_optimize; | |
12938 | mips_optimize = 2; | |
beae10d5 | 12939 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12940 | macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, |
17a2f251 | 12941 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
12942 | mips_optimize = hold_mips_optimize; |
12943 | ||
4d7206a2 | 12944 | relax_switch (); |
252b5132 | 12945 | |
0970e49e | 12946 | offset_expr.X_add_number -= 4; |
252b5132 | 12947 | } |
8fc2e39e | 12948 | used_at = 1; |
f2ae14a1 RS |
12949 | if (offset_high_part (offset_expr.X_add_number, 16) |
12950 | != offset_high_part (offset_expr.X_add_number + 4, 16)) | |
12951 | { | |
12952 | load_address (AT, &offset_expr, &used_at); | |
12953 | offset_expr.X_op = O_constant; | |
12954 | offset_expr.X_add_number = 0; | |
12955 | } | |
12956 | else | |
12957 | macro_build_lui (&offset_expr, AT); | |
252b5132 | 12958 | if (breg != 0) |
67c0d1eb | 12959 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 12960 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12961 | macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], |
17a2f251 | 12962 | BFD_RELOC_LO16, AT); |
252b5132 RH |
12963 | /* FIXME: How do we handle overflow here? */ |
12964 | offset_expr.X_add_number += 4; | |
beae10d5 | 12965 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12966 | macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, |
17a2f251 | 12967 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
12968 | if (mips_relax.sequence) |
12969 | relax_end (); | |
bdaaa2e1 | 12970 | } |
0a44bf69 | 12971 | else if (!mips_big_got) |
252b5132 | 12972 | { |
252b5132 RH |
12973 | /* If this is a reference to an external symbol, we want |
12974 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
12975 | nop | |
c0ebe874 RS |
12976 | <op> op[0],0($at) |
12977 | <op> op[0]+1,4($at) | |
252b5132 RH |
12978 | Otherwise we want |
12979 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
12980 | nop | |
c0ebe874 RS |
12981 | <op> op[0],<sym>($at) (BFD_RELOC_LO16) |
12982 | <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16) | |
252b5132 RH |
12983 | If there is a base register we add it to $at before the |
12984 | lwc1 instructions. If there is a constant we include it | |
12985 | in the lwc1 instructions. */ | |
12986 | used_at = 1; | |
12987 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
12988 | if (expr1.X_add_number < -0x8000 |
12989 | || expr1.X_add_number >= 0x8000 - 4) | |
12990 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 12991 | load_got_offset (AT, &offset_expr); |
269137b2 | 12992 | load_delay_nop (); |
252b5132 | 12993 | if (breg != 0) |
67c0d1eb | 12994 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
12995 | |
12996 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
12997 | nop. */ | |
12998 | hold_mips_optimize = mips_optimize; | |
12999 | mips_optimize = 2; | |
4d7206a2 | 13000 | |
beae10d5 | 13001 | /* Itbl support may require additional care here. */ |
4d7206a2 | 13002 | relax_start (offset_expr.X_add_symbol); |
c0ebe874 | 13003 | macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0], |
67c0d1eb | 13004 | BFD_RELOC_LO16, AT); |
4d7206a2 | 13005 | expr1.X_add_number += 4; |
c0ebe874 | 13006 | macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1, |
67c0d1eb | 13007 | BFD_RELOC_LO16, AT); |
4d7206a2 | 13008 | relax_switch (); |
c0ebe874 | 13009 | macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], |
67c0d1eb | 13010 | BFD_RELOC_LO16, AT); |
4d7206a2 | 13011 | offset_expr.X_add_number += 4; |
c0ebe874 | 13012 | macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, |
67c0d1eb | 13013 | BFD_RELOC_LO16, AT); |
4d7206a2 | 13014 | relax_end (); |
252b5132 | 13015 | |
4d7206a2 | 13016 | mips_optimize = hold_mips_optimize; |
252b5132 | 13017 | } |
0a44bf69 | 13018 | else if (mips_big_got) |
252b5132 | 13019 | { |
67c0d1eb | 13020 | int gpdelay; |
252b5132 RH |
13021 | |
13022 | /* If this is a reference to an external symbol, we want | |
13023 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
13024 | addu $at,$at,$gp | |
13025 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
13026 | nop | |
c0ebe874 RS |
13027 | <op> op[0],0($at) |
13028 | <op> op[0]+1,4($at) | |
252b5132 RH |
13029 | Otherwise we want |
13030 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
13031 | nop | |
c0ebe874 RS |
13032 | <op> op[0],<sym>($at) (BFD_RELOC_LO16) |
13033 | <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16) | |
252b5132 RH |
13034 | If there is a base register we add it to $at before the |
13035 | lwc1 instructions. If there is a constant we include it | |
13036 | in the lwc1 instructions. */ | |
13037 | used_at = 1; | |
13038 | expr1.X_add_number = offset_expr.X_add_number; | |
13039 | offset_expr.X_add_number = 0; | |
13040 | if (expr1.X_add_number < -0x8000 | |
13041 | || expr1.X_add_number >= 0x8000 - 4) | |
13042 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 13043 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 13044 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 13045 | macro_build (&offset_expr, "lui", LUI_FMT, |
67c0d1eb RS |
13046 | AT, BFD_RELOC_MIPS_GOT_HI16); |
13047 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 13048 | AT, AT, mips_gp_register); |
67c0d1eb | 13049 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 13050 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 13051 | load_delay_nop (); |
252b5132 | 13052 | if (breg != 0) |
67c0d1eb | 13053 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 13054 | /* Itbl support may require additional care here. */ |
c0ebe874 | 13055 | macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0], |
17a2f251 | 13056 | BFD_RELOC_LO16, AT); |
252b5132 RH |
13057 | expr1.X_add_number += 4; |
13058 | ||
13059 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
13060 | nop. */ | |
13061 | hold_mips_optimize = mips_optimize; | |
13062 | mips_optimize = 2; | |
beae10d5 | 13063 | /* Itbl support may require additional care here. */ |
c0ebe874 | 13064 | macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1, |
17a2f251 | 13065 | BFD_RELOC_LO16, AT); |
252b5132 RH |
13066 | mips_optimize = hold_mips_optimize; |
13067 | expr1.X_add_number -= 4; | |
13068 | ||
4d7206a2 RS |
13069 | relax_switch (); |
13070 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
13071 | if (gpdelay) |
13072 | macro_build (NULL, "nop", ""); | |
13073 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
13074 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 13075 | load_delay_nop (); |
252b5132 | 13076 | if (breg != 0) |
67c0d1eb | 13077 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 13078 | /* Itbl support may require additional care here. */ |
c0ebe874 | 13079 | macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], |
67c0d1eb | 13080 | BFD_RELOC_LO16, AT); |
4d7206a2 | 13081 | offset_expr.X_add_number += 4; |
252b5132 RH |
13082 | |
13083 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
13084 | nop. */ | |
13085 | hold_mips_optimize = mips_optimize; | |
13086 | mips_optimize = 2; | |
beae10d5 | 13087 | /* Itbl support may require additional care here. */ |
c0ebe874 | 13088 | macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, |
67c0d1eb | 13089 | BFD_RELOC_LO16, AT); |
252b5132 | 13090 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 13091 | relax_end (); |
252b5132 | 13092 | } |
252b5132 RH |
13093 | else |
13094 | abort (); | |
13095 | ||
252b5132 | 13096 | break; |
3739860c | 13097 | |
dd6a37e7 | 13098 | case M_SAA_AB: |
dd6a37e7 | 13099 | s = "saa"; |
0db377d0 | 13100 | goto saa_saad; |
dd6a37e7 | 13101 | case M_SAAD_AB: |
dd6a37e7 | 13102 | s = "saad"; |
0db377d0 MR |
13103 | saa_saad: |
13104 | gas_assert (!mips_opts.micromips); | |
7f3c4072 | 13105 | offbits = 0; |
dd6a37e7 AP |
13106 | fmt = "t,(b)"; |
13107 | goto ld_st; | |
13108 | ||
252b5132 RH |
13109 | /* New code added to support COPZ instructions. |
13110 | This code builds table entries out of the macros in mip_opcodes. | |
13111 | R4000 uses interlocks to handle coproc delays. | |
13112 | Other chips (like the R3000) require nops to be inserted for delays. | |
13113 | ||
f72c8c98 | 13114 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
13115 | In order to fill delay slots for non-interlocked chips, |
13116 | we must have a way to specify delays based on the coprocessor. | |
13117 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
13118 | What are the side-effects of the cop instruction? | |
13119 | What cache support might we have and what are its effects? | |
13120 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 13121 | What registers are read/set/modified? |
252b5132 RH |
13122 | |
13123 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 13124 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
13125 | |
13126 | case M_COP0: | |
13127 | s = "c0"; | |
13128 | goto copz; | |
13129 | case M_COP1: | |
13130 | s = "c1"; | |
13131 | goto copz; | |
13132 | case M_COP2: | |
13133 | s = "c2"; | |
13134 | goto copz; | |
13135 | case M_COP3: | |
13136 | s = "c3"; | |
13137 | copz: | |
df58fc94 | 13138 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
13139 | /* For now we just do C (same as Cz). The parameter will be |
13140 | stored in insn_opcode by mips_ip. */ | |
c8276761 | 13141 | macro_build (NULL, s, "C", (int) ip->insn_opcode); |
8fc2e39e | 13142 | break; |
252b5132 | 13143 | |
ea1fb5dc | 13144 | case M_MOVE: |
c0ebe874 | 13145 | move_register (op[0], op[1]); |
8fc2e39e | 13146 | break; |
ea1fb5dc | 13147 | |
833794fc MR |
13148 | case M_MOVEP: |
13149 | gas_assert (mips_opts.micromips); | |
13150 | gas_assert (mips_opts.insn32); | |
c0ebe874 RS |
13151 | move_register (micromips_to_32_reg_h_map1[op[0]], |
13152 | micromips_to_32_reg_m_map[op[1]]); | |
13153 | move_register (micromips_to_32_reg_h_map2[op[0]], | |
13154 | micromips_to_32_reg_n_map[op[2]]); | |
833794fc MR |
13155 | break; |
13156 | ||
252b5132 RH |
13157 | case M_DMUL: |
13158 | dbl = 1; | |
1a0670f3 | 13159 | /* Fall through. */ |
252b5132 | 13160 | case M_MUL: |
e407c74b | 13161 | if (mips_opts.arch == CPU_R5900) |
c0ebe874 RS |
13162 | macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", op[0], op[1], |
13163 | op[2]); | |
e407c74b NC |
13164 | else |
13165 | { | |
c0ebe874 RS |
13166 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", op[1], op[2]); |
13167 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); | |
e407c74b | 13168 | } |
8fc2e39e | 13169 | break; |
252b5132 RH |
13170 | |
13171 | case M_DMUL_I: | |
13172 | dbl = 1; | |
1a0670f3 | 13173 | /* Fall through. */ |
252b5132 RH |
13174 | case M_MUL_I: |
13175 | /* The MIPS assembler some times generates shifts and adds. I'm | |
13176 | not trying to be that fancy. GCC should do this for us | |
13177 | anyway. */ | |
8fc2e39e | 13178 | used_at = 1; |
67c0d1eb | 13179 | load_register (AT, &imm_expr, dbl); |
c0ebe874 RS |
13180 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", op[1], AT); |
13181 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); | |
252b5132 RH |
13182 | break; |
13183 | ||
13184 | case M_DMULO_I: | |
13185 | dbl = 1; | |
1a0670f3 | 13186 | /* Fall through. */ |
252b5132 RH |
13187 | case M_MULO_I: |
13188 | imm = 1; | |
13189 | goto do_mulo; | |
13190 | ||
13191 | case M_DMULO: | |
13192 | dbl = 1; | |
1a0670f3 | 13193 | /* Fall through. */ |
252b5132 RH |
13194 | case M_MULO: |
13195 | do_mulo: | |
7d10b47d | 13196 | start_noreorder (); |
8fc2e39e | 13197 | used_at = 1; |
252b5132 | 13198 | if (imm) |
67c0d1eb | 13199 | load_register (AT, &imm_expr, dbl); |
c0ebe874 RS |
13200 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", |
13201 | op[1], imm ? AT : op[2]); | |
13202 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); | |
13203 | macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, op[0], op[0], 31); | |
df58fc94 | 13204 | macro_build (NULL, "mfhi", MFHL_FMT, AT); |
252b5132 | 13205 | if (mips_trap) |
c0ebe874 | 13206 | macro_build (NULL, "tne", TRAP_FMT, op[0], AT, 6); |
252b5132 RH |
13207 | else |
13208 | { | |
df58fc94 RS |
13209 | if (mips_opts.micromips) |
13210 | micromips_label_expr (&label_expr); | |
13211 | else | |
13212 | label_expr.X_add_number = 8; | |
c0ebe874 | 13213 | macro_build (&label_expr, "beq", "s,t,p", op[0], AT); |
a605d2b3 | 13214 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
13215 | macro_build (NULL, "break", BRK_FMT, 6); |
13216 | if (mips_opts.micromips) | |
13217 | micromips_add_label (); | |
252b5132 | 13218 | } |
7d10b47d | 13219 | end_noreorder (); |
c0ebe874 | 13220 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); |
252b5132 RH |
13221 | break; |
13222 | ||
13223 | case M_DMULOU_I: | |
13224 | dbl = 1; | |
1a0670f3 | 13225 | /* Fall through. */ |
252b5132 RH |
13226 | case M_MULOU_I: |
13227 | imm = 1; | |
13228 | goto do_mulou; | |
13229 | ||
13230 | case M_DMULOU: | |
13231 | dbl = 1; | |
1a0670f3 | 13232 | /* Fall through. */ |
252b5132 RH |
13233 | case M_MULOU: |
13234 | do_mulou: | |
7d10b47d | 13235 | start_noreorder (); |
8fc2e39e | 13236 | used_at = 1; |
252b5132 | 13237 | if (imm) |
67c0d1eb RS |
13238 | load_register (AT, &imm_expr, dbl); |
13239 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
c0ebe874 | 13240 | op[1], imm ? AT : op[2]); |
df58fc94 | 13241 | macro_build (NULL, "mfhi", MFHL_FMT, AT); |
c0ebe874 | 13242 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); |
252b5132 | 13243 | if (mips_trap) |
df58fc94 | 13244 | macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6); |
252b5132 RH |
13245 | else |
13246 | { | |
df58fc94 RS |
13247 | if (mips_opts.micromips) |
13248 | micromips_label_expr (&label_expr); | |
13249 | else | |
13250 | label_expr.X_add_number = 8; | |
13251 | macro_build (&label_expr, "beq", "s,t,p", AT, ZERO); | |
a605d2b3 | 13252 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
13253 | macro_build (NULL, "break", BRK_FMT, 6); |
13254 | if (mips_opts.micromips) | |
13255 | micromips_add_label (); | |
252b5132 | 13256 | } |
7d10b47d | 13257 | end_noreorder (); |
252b5132 RH |
13258 | break; |
13259 | ||
771c7ce4 | 13260 | case M_DROL: |
fef14a42 | 13261 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 13262 | { |
c0ebe874 | 13263 | if (op[0] == op[1]) |
82dd0097 CD |
13264 | { |
13265 | tempreg = AT; | |
13266 | used_at = 1; | |
13267 | } | |
13268 | else | |
c0ebe874 RS |
13269 | tempreg = op[0]; |
13270 | macro_build (NULL, "dnegu", "d,w", tempreg, op[2]); | |
13271 | macro_build (NULL, "drorv", "d,t,s", op[0], op[1], tempreg); | |
8fc2e39e | 13272 | break; |
82dd0097 | 13273 | } |
8fc2e39e | 13274 | used_at = 1; |
c0ebe874 RS |
13275 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]); |
13276 | macro_build (NULL, "dsrlv", "d,t,s", AT, op[1], AT); | |
13277 | macro_build (NULL, "dsllv", "d,t,s", op[0], op[1], op[2]); | |
13278 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 TS |
13279 | break; |
13280 | ||
252b5132 | 13281 | case M_ROL: |
fef14a42 | 13282 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 13283 | { |
c0ebe874 | 13284 | if (op[0] == op[1]) |
82dd0097 CD |
13285 | { |
13286 | tempreg = AT; | |
13287 | used_at = 1; | |
13288 | } | |
13289 | else | |
c0ebe874 RS |
13290 | tempreg = op[0]; |
13291 | macro_build (NULL, "negu", "d,w", tempreg, op[2]); | |
13292 | macro_build (NULL, "rorv", "d,t,s", op[0], op[1], tempreg); | |
8fc2e39e | 13293 | break; |
82dd0097 | 13294 | } |
8fc2e39e | 13295 | used_at = 1; |
c0ebe874 RS |
13296 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]); |
13297 | macro_build (NULL, "srlv", "d,t,s", AT, op[1], AT); | |
13298 | macro_build (NULL, "sllv", "d,t,s", op[0], op[1], op[2]); | |
13299 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
252b5132 RH |
13300 | break; |
13301 | ||
771c7ce4 TS |
13302 | case M_DROL_I: |
13303 | { | |
13304 | unsigned int rot; | |
e0471c16 TS |
13305 | const char *l; |
13306 | const char *rr; | |
771c7ce4 | 13307 | |
771c7ce4 | 13308 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 13309 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
13310 | { |
13311 | rot = (64 - rot) & 0x3f; | |
13312 | if (rot >= 32) | |
c0ebe874 | 13313 | macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32); |
60b63b72 | 13314 | else |
c0ebe874 | 13315 | macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot); |
8fc2e39e | 13316 | break; |
60b63b72 | 13317 | } |
483fc7cd | 13318 | if (rot == 0) |
483fc7cd | 13319 | { |
c0ebe874 | 13320 | macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0); |
8fc2e39e | 13321 | break; |
483fc7cd | 13322 | } |
82dd0097 | 13323 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
91d6fa6a | 13324 | rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 | 13325 | rot &= 0x1f; |
8fc2e39e | 13326 | used_at = 1; |
c0ebe874 RS |
13327 | macro_build (NULL, l, SHFT_FMT, AT, op[1], rot); |
13328 | macro_build (NULL, rr, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); | |
13329 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 TS |
13330 | } |
13331 | break; | |
13332 | ||
252b5132 | 13333 | case M_ROL_I: |
771c7ce4 TS |
13334 | { |
13335 | unsigned int rot; | |
13336 | ||
771c7ce4 | 13337 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 13338 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 13339 | { |
c0ebe874 RS |
13340 | macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], |
13341 | (32 - rot) & 0x1f); | |
8fc2e39e | 13342 | break; |
60b63b72 | 13343 | } |
483fc7cd | 13344 | if (rot == 0) |
483fc7cd | 13345 | { |
c0ebe874 | 13346 | macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0); |
8fc2e39e | 13347 | break; |
483fc7cd | 13348 | } |
8fc2e39e | 13349 | used_at = 1; |
c0ebe874 RS |
13350 | macro_build (NULL, "sll", SHFT_FMT, AT, op[1], rot); |
13351 | macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); | |
13352 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 TS |
13353 | } |
13354 | break; | |
13355 | ||
13356 | case M_DROR: | |
fef14a42 | 13357 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 13358 | { |
c0ebe874 | 13359 | macro_build (NULL, "drorv", "d,t,s", op[0], op[1], op[2]); |
8fc2e39e | 13360 | break; |
82dd0097 | 13361 | } |
8fc2e39e | 13362 | used_at = 1; |
c0ebe874 RS |
13363 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]); |
13364 | macro_build (NULL, "dsllv", "d,t,s", AT, op[1], AT); | |
13365 | macro_build (NULL, "dsrlv", "d,t,s", op[0], op[1], op[2]); | |
13366 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
252b5132 RH |
13367 | break; |
13368 | ||
13369 | case M_ROR: | |
fef14a42 | 13370 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 13371 | { |
c0ebe874 | 13372 | macro_build (NULL, "rorv", "d,t,s", op[0], op[1], op[2]); |
8fc2e39e | 13373 | break; |
82dd0097 | 13374 | } |
8fc2e39e | 13375 | used_at = 1; |
c0ebe874 RS |
13376 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]); |
13377 | macro_build (NULL, "sllv", "d,t,s", AT, op[1], AT); | |
13378 | macro_build (NULL, "srlv", "d,t,s", op[0], op[1], op[2]); | |
13379 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
252b5132 RH |
13380 | break; |
13381 | ||
771c7ce4 TS |
13382 | case M_DROR_I: |
13383 | { | |
13384 | unsigned int rot; | |
e0471c16 TS |
13385 | const char *l; |
13386 | const char *rr; | |
771c7ce4 | 13387 | |
771c7ce4 | 13388 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 13389 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
13390 | { |
13391 | if (rot >= 32) | |
c0ebe874 | 13392 | macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32); |
82dd0097 | 13393 | else |
c0ebe874 | 13394 | macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot); |
8fc2e39e | 13395 | break; |
82dd0097 | 13396 | } |
483fc7cd | 13397 | if (rot == 0) |
483fc7cd | 13398 | { |
c0ebe874 | 13399 | macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0); |
8fc2e39e | 13400 | break; |
483fc7cd | 13401 | } |
91d6fa6a | 13402 | rr = (rot < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 CD |
13403 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; |
13404 | rot &= 0x1f; | |
8fc2e39e | 13405 | used_at = 1; |
c0ebe874 RS |
13406 | macro_build (NULL, rr, SHFT_FMT, AT, op[1], rot); |
13407 | macro_build (NULL, l, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); | |
13408 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 TS |
13409 | } |
13410 | break; | |
13411 | ||
252b5132 | 13412 | case M_ROR_I: |
771c7ce4 TS |
13413 | { |
13414 | unsigned int rot; | |
13415 | ||
771c7ce4 | 13416 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 13417 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 13418 | { |
c0ebe874 | 13419 | macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], rot); |
8fc2e39e | 13420 | break; |
82dd0097 | 13421 | } |
483fc7cd | 13422 | if (rot == 0) |
483fc7cd | 13423 | { |
c0ebe874 | 13424 | macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0); |
8fc2e39e | 13425 | break; |
483fc7cd | 13426 | } |
8fc2e39e | 13427 | used_at = 1; |
c0ebe874 RS |
13428 | macro_build (NULL, "srl", SHFT_FMT, AT, op[1], rot); |
13429 | macro_build (NULL, "sll", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); | |
13430 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 | 13431 | } |
252b5132 RH |
13432 | break; |
13433 | ||
252b5132 | 13434 | case M_SEQ: |
c0ebe874 RS |
13435 | if (op[1] == 0) |
13436 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[2], BFD_RELOC_LO16); | |
13437 | else if (op[2] == 0) | |
13438 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16); | |
252b5132 RH |
13439 | else |
13440 | { | |
c0ebe874 RS |
13441 | macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]); |
13442 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16); | |
252b5132 | 13443 | } |
8fc2e39e | 13444 | break; |
252b5132 RH |
13445 | |
13446 | case M_SEQ_I: | |
b0e6f033 | 13447 | if (imm_expr.X_add_number == 0) |
252b5132 | 13448 | { |
c0ebe874 | 13449 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
8fc2e39e | 13450 | break; |
252b5132 | 13451 | } |
c0ebe874 | 13452 | if (op[1] == 0) |
252b5132 | 13453 | { |
1661c76c | 13454 | as_warn (_("instruction %s: result is always false"), |
252b5132 | 13455 | ip->insn_mo->name); |
c0ebe874 | 13456 | move_register (op[0], 0); |
8fc2e39e | 13457 | break; |
252b5132 | 13458 | } |
dd3cbb7e NC |
13459 | if (CPU_HAS_SEQ (mips_opts.arch) |
13460 | && -512 <= imm_expr.X_add_number | |
13461 | && imm_expr.X_add_number < 512) | |
13462 | { | |
c0ebe874 | 13463 | macro_build (NULL, "seqi", "t,r,+Q", op[0], op[1], |
750bdd57 | 13464 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
13465 | break; |
13466 | } | |
b0e6f033 | 13467 | if (imm_expr.X_add_number >= 0 |
252b5132 | 13468 | && imm_expr.X_add_number < 0x10000) |
c0ebe874 | 13469 | macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1], BFD_RELOC_LO16); |
b0e6f033 | 13470 | else if (imm_expr.X_add_number > -0x8000 |
252b5132 RH |
13471 | && imm_expr.X_add_number < 0) |
13472 | { | |
13473 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
bad1aba3 | 13474 | macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu", |
c0ebe874 | 13475 | "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
252b5132 | 13476 | } |
dd3cbb7e NC |
13477 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
13478 | { | |
13479 | used_at = 1; | |
bad1aba3 | 13480 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13481 | macro_build (NULL, "seq", "d,v,t", op[0], op[1], AT); |
dd3cbb7e NC |
13482 | break; |
13483 | } | |
252b5132 RH |
13484 | else |
13485 | { | |
bad1aba3 | 13486 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13487 | macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT); |
252b5132 RH |
13488 | used_at = 1; |
13489 | } | |
c0ebe874 | 13490 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16); |
8fc2e39e | 13491 | break; |
252b5132 | 13492 | |
c0ebe874 | 13493 | case M_SGE: /* X >= Y <==> not (X < Y) */ |
252b5132 RH |
13494 | s = "slt"; |
13495 | goto sge; | |
13496 | case M_SGEU: | |
13497 | s = "sltu"; | |
13498 | sge: | |
c0ebe874 RS |
13499 | macro_build (NULL, s, "d,v,t", op[0], op[1], op[2]); |
13500 | macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); | |
8fc2e39e | 13501 | break; |
252b5132 | 13502 | |
6f2117ba | 13503 | case M_SGE_I: /* X >= I <==> not (X < I). */ |
252b5132 | 13504 | case M_SGEU_I: |
b0e6f033 | 13505 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 | 13506 | && imm_expr.X_add_number < 0x8000) |
c0ebe874 RS |
13507 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
13508 | op[0], op[1], BFD_RELOC_LO16); | |
252b5132 RH |
13509 | else |
13510 | { | |
bad1aba3 | 13511 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
67c0d1eb | 13512 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", |
c0ebe874 | 13513 | op[0], op[1], AT); |
252b5132 RH |
13514 | used_at = 1; |
13515 | } | |
c0ebe874 | 13516 | macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); |
8fc2e39e | 13517 | break; |
252b5132 | 13518 | |
6f2117ba | 13519 | case M_SGT: /* X > Y <==> Y < X. */ |
252b5132 RH |
13520 | s = "slt"; |
13521 | goto sgt; | |
13522 | case M_SGTU: | |
13523 | s = "sltu"; | |
13524 | sgt: | |
c0ebe874 | 13525 | macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]); |
8fc2e39e | 13526 | break; |
252b5132 | 13527 | |
6f2117ba | 13528 | case M_SGT_I: /* X > I <==> I < X. */ |
252b5132 RH |
13529 | s = "slt"; |
13530 | goto sgti; | |
13531 | case M_SGTU_I: | |
13532 | s = "sltu"; | |
13533 | sgti: | |
8fc2e39e | 13534 | used_at = 1; |
bad1aba3 | 13535 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13536 | macro_build (NULL, s, "d,v,t", op[0], AT, op[1]); |
252b5132 RH |
13537 | break; |
13538 | ||
6f2117ba | 13539 | case M_SLE: /* X <= Y <==> Y >= X <==> not (Y < X). */ |
252b5132 RH |
13540 | s = "slt"; |
13541 | goto sle; | |
13542 | case M_SLEU: | |
13543 | s = "sltu"; | |
13544 | sle: | |
c0ebe874 RS |
13545 | macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]); |
13546 | macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); | |
8fc2e39e | 13547 | break; |
252b5132 | 13548 | |
c0ebe874 | 13549 | case M_SLE_I: /* X <= I <==> I >= X <==> not (I < X) */ |
252b5132 RH |
13550 | s = "slt"; |
13551 | goto slei; | |
13552 | case M_SLEU_I: | |
13553 | s = "sltu"; | |
13554 | slei: | |
8fc2e39e | 13555 | used_at = 1; |
bad1aba3 | 13556 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 RS |
13557 | macro_build (NULL, s, "d,v,t", op[0], AT, op[1]); |
13558 | macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); | |
252b5132 RH |
13559 | break; |
13560 | ||
13561 | case M_SLT_I: | |
b0e6f033 | 13562 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 RH |
13563 | && imm_expr.X_add_number < 0x8000) |
13564 | { | |
c0ebe874 RS |
13565 | macro_build (&imm_expr, "slti", "t,r,j", op[0], op[1], |
13566 | BFD_RELOC_LO16); | |
8fc2e39e | 13567 | break; |
252b5132 | 13568 | } |
8fc2e39e | 13569 | used_at = 1; |
bad1aba3 | 13570 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13571 | macro_build (NULL, "slt", "d,v,t", op[0], op[1], AT); |
252b5132 RH |
13572 | break; |
13573 | ||
13574 | case M_SLTU_I: | |
b0e6f033 | 13575 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 RH |
13576 | && imm_expr.X_add_number < 0x8000) |
13577 | { | |
c0ebe874 | 13578 | macro_build (&imm_expr, "sltiu", "t,r,j", op[0], op[1], |
17a2f251 | 13579 | BFD_RELOC_LO16); |
8fc2e39e | 13580 | break; |
252b5132 | 13581 | } |
8fc2e39e | 13582 | used_at = 1; |
bad1aba3 | 13583 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13584 | macro_build (NULL, "sltu", "d,v,t", op[0], op[1], AT); |
252b5132 RH |
13585 | break; |
13586 | ||
13587 | case M_SNE: | |
c0ebe874 RS |
13588 | if (op[1] == 0) |
13589 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[2]); | |
13590 | else if (op[2] == 0) | |
13591 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]); | |
252b5132 RH |
13592 | else |
13593 | { | |
c0ebe874 RS |
13594 | macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]); |
13595 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]); | |
252b5132 | 13596 | } |
8fc2e39e | 13597 | break; |
252b5132 RH |
13598 | |
13599 | case M_SNE_I: | |
b0e6f033 | 13600 | if (imm_expr.X_add_number == 0) |
252b5132 | 13601 | { |
c0ebe874 | 13602 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]); |
8fc2e39e | 13603 | break; |
252b5132 | 13604 | } |
c0ebe874 | 13605 | if (op[1] == 0) |
252b5132 | 13606 | { |
1661c76c | 13607 | as_warn (_("instruction %s: result is always true"), |
252b5132 | 13608 | ip->insn_mo->name); |
bad1aba3 | 13609 | macro_build (&expr1, GPR_SIZE == 32 ? "addiu" : "daddiu", "t,r,j", |
c0ebe874 | 13610 | op[0], 0, BFD_RELOC_LO16); |
8fc2e39e | 13611 | break; |
252b5132 | 13612 | } |
dd3cbb7e NC |
13613 | if (CPU_HAS_SEQ (mips_opts.arch) |
13614 | && -512 <= imm_expr.X_add_number | |
13615 | && imm_expr.X_add_number < 512) | |
13616 | { | |
c0ebe874 | 13617 | macro_build (NULL, "snei", "t,r,+Q", op[0], op[1], |
750bdd57 | 13618 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
13619 | break; |
13620 | } | |
b0e6f033 | 13621 | if (imm_expr.X_add_number >= 0 |
252b5132 RH |
13622 | && imm_expr.X_add_number < 0x10000) |
13623 | { | |
c0ebe874 RS |
13624 | macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1], |
13625 | BFD_RELOC_LO16); | |
252b5132 | 13626 | } |
b0e6f033 | 13627 | else if (imm_expr.X_add_number > -0x8000 |
252b5132 RH |
13628 | && imm_expr.X_add_number < 0) |
13629 | { | |
13630 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
bad1aba3 | 13631 | macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu", |
c0ebe874 | 13632 | "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
252b5132 | 13633 | } |
dd3cbb7e NC |
13634 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
13635 | { | |
13636 | used_at = 1; | |
bad1aba3 | 13637 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13638 | macro_build (NULL, "sne", "d,v,t", op[0], op[1], AT); |
dd3cbb7e NC |
13639 | break; |
13640 | } | |
252b5132 RH |
13641 | else |
13642 | { | |
bad1aba3 | 13643 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13644 | macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT); |
252b5132 RH |
13645 | used_at = 1; |
13646 | } | |
c0ebe874 | 13647 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]); |
8fc2e39e | 13648 | break; |
252b5132 | 13649 | |
df58fc94 RS |
13650 | case M_SUB_I: |
13651 | s = "addi"; | |
13652 | s2 = "sub"; | |
13653 | goto do_subi; | |
13654 | case M_SUBU_I: | |
13655 | s = "addiu"; | |
13656 | s2 = "subu"; | |
13657 | goto do_subi; | |
252b5132 RH |
13658 | case M_DSUB_I: |
13659 | dbl = 1; | |
df58fc94 RS |
13660 | s = "daddi"; |
13661 | s2 = "dsub"; | |
13662 | if (!mips_opts.micromips) | |
13663 | goto do_subi; | |
b0e6f033 | 13664 | if (imm_expr.X_add_number > -0x200 |
df58fc94 | 13665 | && imm_expr.X_add_number <= 0x200) |
252b5132 | 13666 | { |
b0e6f033 RS |
13667 | macro_build (NULL, s, "t,r,.", op[0], op[1], |
13668 | (int) -imm_expr.X_add_number); | |
8fc2e39e | 13669 | break; |
252b5132 | 13670 | } |
df58fc94 | 13671 | goto do_subi_i; |
252b5132 RH |
13672 | case M_DSUBU_I: |
13673 | dbl = 1; | |
df58fc94 RS |
13674 | s = "daddiu"; |
13675 | s2 = "dsubu"; | |
13676 | do_subi: | |
b0e6f033 | 13677 | if (imm_expr.X_add_number > -0x8000 |
252b5132 RH |
13678 | && imm_expr.X_add_number <= 0x8000) |
13679 | { | |
13680 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
c0ebe874 | 13681 | macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
8fc2e39e | 13682 | break; |
252b5132 | 13683 | } |
df58fc94 | 13684 | do_subi_i: |
8fc2e39e | 13685 | used_at = 1; |
67c0d1eb | 13686 | load_register (AT, &imm_expr, dbl); |
c0ebe874 | 13687 | macro_build (NULL, s2, "d,v,t", op[0], op[1], AT); |
252b5132 RH |
13688 | break; |
13689 | ||
13690 | case M_TEQ_I: | |
13691 | s = "teq"; | |
13692 | goto trap; | |
13693 | case M_TGE_I: | |
13694 | s = "tge"; | |
13695 | goto trap; | |
13696 | case M_TGEU_I: | |
13697 | s = "tgeu"; | |
13698 | goto trap; | |
13699 | case M_TLT_I: | |
13700 | s = "tlt"; | |
13701 | goto trap; | |
13702 | case M_TLTU_I: | |
13703 | s = "tltu"; | |
13704 | goto trap; | |
13705 | case M_TNE_I: | |
13706 | s = "tne"; | |
13707 | trap: | |
8fc2e39e | 13708 | used_at = 1; |
bad1aba3 | 13709 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13710 | macro_build (NULL, s, "s,t", op[0], AT); |
252b5132 RH |
13711 | break; |
13712 | ||
252b5132 | 13713 | case M_TRUNCWS: |
43841e91 | 13714 | case M_TRUNCWD: |
df58fc94 | 13715 | gas_assert (!mips_opts.micromips); |
0aa27725 | 13716 | gas_assert (mips_opts.isa == ISA_MIPS1); |
8fc2e39e | 13717 | used_at = 1; |
252b5132 RH |
13718 | |
13719 | /* | |
13720 | * Is the double cfc1 instruction a bug in the mips assembler; | |
13721 | * or is there a reason for it? | |
13722 | */ | |
7d10b47d | 13723 | start_noreorder (); |
c0ebe874 RS |
13724 | macro_build (NULL, "cfc1", "t,G", op[2], RA); |
13725 | macro_build (NULL, "cfc1", "t,G", op[2], RA); | |
67c0d1eb | 13726 | macro_build (NULL, "nop", ""); |
252b5132 | 13727 | expr1.X_add_number = 3; |
c0ebe874 | 13728 | macro_build (&expr1, "ori", "t,r,i", AT, op[2], BFD_RELOC_LO16); |
252b5132 | 13729 | expr1.X_add_number = 2; |
67c0d1eb RS |
13730 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
13731 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
13732 | macro_build (NULL, "nop", ""); | |
13733 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
c0ebe874 RS |
13734 | op[0], op[1]); |
13735 | macro_build (NULL, "ctc1", "t,G", op[2], RA); | |
67c0d1eb | 13736 | macro_build (NULL, "nop", ""); |
7d10b47d | 13737 | end_noreorder (); |
252b5132 RH |
13738 | break; |
13739 | ||
f2ae14a1 | 13740 | case M_ULH_AB: |
252b5132 | 13741 | s = "lb"; |
df58fc94 RS |
13742 | s2 = "lbu"; |
13743 | off = 1; | |
13744 | goto uld_st; | |
f2ae14a1 | 13745 | case M_ULHU_AB: |
252b5132 | 13746 | s = "lbu"; |
df58fc94 RS |
13747 | s2 = "lbu"; |
13748 | off = 1; | |
13749 | goto uld_st; | |
f2ae14a1 | 13750 | case M_ULW_AB: |
df58fc94 RS |
13751 | s = "lwl"; |
13752 | s2 = "lwr"; | |
7f3c4072 | 13753 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
13754 | off = 3; |
13755 | goto uld_st; | |
f2ae14a1 | 13756 | case M_ULD_AB: |
252b5132 RH |
13757 | s = "ldl"; |
13758 | s2 = "ldr"; | |
7f3c4072 | 13759 | offbits = (mips_opts.micromips ? 12 : 16); |
252b5132 | 13760 | off = 7; |
df58fc94 | 13761 | goto uld_st; |
f2ae14a1 | 13762 | case M_USH_AB: |
df58fc94 RS |
13763 | s = "sb"; |
13764 | s2 = "sb"; | |
13765 | off = 1; | |
13766 | ust = 1; | |
13767 | goto uld_st; | |
f2ae14a1 | 13768 | case M_USW_AB: |
df58fc94 RS |
13769 | s = "swl"; |
13770 | s2 = "swr"; | |
7f3c4072 | 13771 | offbits = (mips_opts.micromips ? 12 : 16); |
252b5132 | 13772 | off = 3; |
df58fc94 RS |
13773 | ust = 1; |
13774 | goto uld_st; | |
f2ae14a1 | 13775 | case M_USD_AB: |
df58fc94 RS |
13776 | s = "sdl"; |
13777 | s2 = "sdr"; | |
7f3c4072 | 13778 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
13779 | off = 7; |
13780 | ust = 1; | |
13781 | ||
13782 | uld_st: | |
c0ebe874 | 13783 | breg = op[2]; |
f2ae14a1 | 13784 | large_offset = !small_offset_p (off, align, offbits); |
df58fc94 RS |
13785 | ep = &offset_expr; |
13786 | expr1.X_add_number = 0; | |
f2ae14a1 | 13787 | if (large_offset) |
df58fc94 RS |
13788 | { |
13789 | used_at = 1; | |
13790 | tempreg = AT; | |
f2ae14a1 RS |
13791 | if (small_offset_p (0, align, 16)) |
13792 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, -1, | |
13793 | offset_reloc[0], offset_reloc[1], offset_reloc[2]); | |
13794 | else | |
13795 | { | |
13796 | load_address (tempreg, ep, &used_at); | |
13797 | if (breg != 0) | |
13798 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
13799 | tempreg, tempreg, breg); | |
13800 | } | |
13801 | offset_reloc[0] = BFD_RELOC_LO16; | |
13802 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
13803 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
df58fc94 | 13804 | breg = tempreg; |
c0ebe874 | 13805 | tempreg = op[0]; |
df58fc94 RS |
13806 | ep = &expr1; |
13807 | } | |
c0ebe874 | 13808 | else if (!ust && op[0] == breg) |
8fc2e39e TS |
13809 | { |
13810 | used_at = 1; | |
13811 | tempreg = AT; | |
13812 | } | |
252b5132 | 13813 | else |
c0ebe874 | 13814 | tempreg = op[0]; |
af22f5b2 | 13815 | |
df58fc94 RS |
13816 | if (off == 1) |
13817 | goto ulh_sh; | |
252b5132 | 13818 | |
90ecf173 | 13819 | if (!target_big_endian) |
df58fc94 | 13820 | ep->X_add_number += off; |
f2ae14a1 | 13821 | if (offbits == 12) |
c8276761 | 13822 | macro_build (NULL, s, "t,~(b)", tempreg, (int) ep->X_add_number, breg); |
f2ae14a1 RS |
13823 | else |
13824 | macro_build (ep, s, "t,o(b)", tempreg, -1, | |
13825 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); | |
df58fc94 | 13826 | |
90ecf173 | 13827 | if (!target_big_endian) |
df58fc94 | 13828 | ep->X_add_number -= off; |
252b5132 | 13829 | else |
df58fc94 | 13830 | ep->X_add_number += off; |
f2ae14a1 | 13831 | if (offbits == 12) |
df58fc94 | 13832 | macro_build (NULL, s2, "t,~(b)", |
c8276761 | 13833 | tempreg, (int) ep->X_add_number, breg); |
f2ae14a1 RS |
13834 | else |
13835 | macro_build (ep, s2, "t,o(b)", tempreg, -1, | |
13836 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); | |
252b5132 | 13837 | |
df58fc94 | 13838 | /* If necessary, move the result in tempreg to the final destination. */ |
c0ebe874 | 13839 | if (!ust && op[0] != tempreg) |
df58fc94 RS |
13840 | { |
13841 | /* Protect second load's delay slot. */ | |
13842 | load_delay_nop (); | |
c0ebe874 | 13843 | move_register (op[0], tempreg); |
df58fc94 | 13844 | } |
8fc2e39e | 13845 | break; |
252b5132 | 13846 | |
df58fc94 | 13847 | ulh_sh: |
d6bc6245 | 13848 | used_at = 1; |
df58fc94 RS |
13849 | if (target_big_endian == ust) |
13850 | ep->X_add_number += off; | |
c0ebe874 | 13851 | tempreg = ust || large_offset ? op[0] : AT; |
f2ae14a1 RS |
13852 | macro_build (ep, s, "t,o(b)", tempreg, -1, |
13853 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); | |
df58fc94 RS |
13854 | |
13855 | /* For halfword transfers we need a temporary register to shuffle | |
13856 | bytes. Unfortunately for M_USH_A we have none available before | |
13857 | the next store as AT holds the base address. We deal with this | |
13858 | case by clobbering TREG and then restoring it as with ULH. */ | |
c0ebe874 | 13859 | tempreg = ust == large_offset ? op[0] : AT; |
df58fc94 | 13860 | if (ust) |
c0ebe874 | 13861 | macro_build (NULL, "srl", SHFT_FMT, tempreg, op[0], 8); |
df58fc94 RS |
13862 | |
13863 | if (target_big_endian == ust) | |
13864 | ep->X_add_number -= off; | |
252b5132 | 13865 | else |
df58fc94 | 13866 | ep->X_add_number += off; |
f2ae14a1 RS |
13867 | macro_build (ep, s2, "t,o(b)", tempreg, -1, |
13868 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); | |
252b5132 | 13869 | |
df58fc94 | 13870 | /* For M_USH_A re-retrieve the LSB. */ |
f2ae14a1 | 13871 | if (ust && large_offset) |
df58fc94 RS |
13872 | { |
13873 | if (target_big_endian) | |
13874 | ep->X_add_number += off; | |
13875 | else | |
13876 | ep->X_add_number -= off; | |
f2ae14a1 RS |
13877 | macro_build (&expr1, "lbu", "t,o(b)", AT, -1, |
13878 | offset_reloc[0], offset_reloc[1], offset_reloc[2], AT); | |
df58fc94 RS |
13879 | } |
13880 | /* For ULH and M_USH_A OR the LSB in. */ | |
f2ae14a1 | 13881 | if (!ust || large_offset) |
df58fc94 | 13882 | { |
c0ebe874 | 13883 | tempreg = !large_offset ? AT : op[0]; |
df58fc94 | 13884 | macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8); |
c0ebe874 | 13885 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); |
df58fc94 | 13886 | } |
252b5132 RH |
13887 | break; |
13888 | ||
13889 | default: | |
13890 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 13891 | are added dynamically. */ |
1661c76c | 13892 | as_bad (_("macro %s not implemented yet"), ip->insn_mo->name); |
252b5132 RH |
13893 | break; |
13894 | } | |
741fe287 | 13895 | if (!mips_opts.at && used_at) |
1661c76c | 13896 | as_bad (_("macro used $at after \".set noat\"")); |
252b5132 RH |
13897 | } |
13898 | ||
13899 | /* Implement macros in mips16 mode. */ | |
13900 | ||
13901 | static void | |
17a2f251 | 13902 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 | 13903 | { |
c0ebe874 | 13904 | const struct mips_operand_array *operands; |
252b5132 | 13905 | int mask; |
c0ebe874 | 13906 | int tmp; |
252b5132 RH |
13907 | expressionS expr1; |
13908 | int dbl; | |
13909 | const char *s, *s2, *s3; | |
c0ebe874 RS |
13910 | unsigned int op[MAX_OPERANDS]; |
13911 | unsigned int i; | |
252b5132 RH |
13912 | |
13913 | mask = ip->insn_mo->mask; | |
13914 | ||
c0ebe874 RS |
13915 | operands = insn_operands (ip); |
13916 | for (i = 0; i < MAX_OPERANDS; i++) | |
13917 | if (operands->operand[i]) | |
13918 | op[i] = insn_extract_operand (ip, operands->operand[i]); | |
13919 | else | |
13920 | op[i] = -1; | |
252b5132 | 13921 | |
252b5132 RH |
13922 | expr1.X_op = O_constant; |
13923 | expr1.X_op_symbol = NULL; | |
13924 | expr1.X_add_symbol = NULL; | |
13925 | expr1.X_add_number = 1; | |
13926 | ||
13927 | dbl = 0; | |
13928 | ||
13929 | switch (mask) | |
13930 | { | |
13931 | default: | |
b37df7c4 | 13932 | abort (); |
252b5132 RH |
13933 | |
13934 | case M_DDIV_3: | |
13935 | dbl = 1; | |
1a0670f3 | 13936 | /* Fall through. */ |
252b5132 RH |
13937 | case M_DIV_3: |
13938 | s = "mflo"; | |
13939 | goto do_div3; | |
13940 | case M_DREM_3: | |
13941 | dbl = 1; | |
1a0670f3 | 13942 | /* Fall through. */ |
252b5132 RH |
13943 | case M_REM_3: |
13944 | s = "mfhi"; | |
13945 | do_div3: | |
7d10b47d | 13946 | start_noreorder (); |
d8722d76 | 13947 | macro_build (NULL, dbl ? "ddiv" : "div", ".,x,y", op[1], op[2]); |
252b5132 | 13948 | expr1.X_add_number = 2; |
c0ebe874 | 13949 | macro_build (&expr1, "bnez", "x,p", op[2]); |
67c0d1eb | 13950 | macro_build (NULL, "break", "6", 7); |
bdaaa2e1 | 13951 | |
252b5132 RH |
13952 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
13953 | since that causes an overflow. We should do that as well, | |
13954 | but I don't see how to do the comparisons without a temporary | |
13955 | register. */ | |
7d10b47d | 13956 | end_noreorder (); |
c0ebe874 | 13957 | macro_build (NULL, s, "x", op[0]); |
252b5132 RH |
13958 | break; |
13959 | ||
13960 | case M_DIVU_3: | |
13961 | s = "divu"; | |
13962 | s2 = "mflo"; | |
13963 | goto do_divu3; | |
13964 | case M_REMU_3: | |
13965 | s = "divu"; | |
13966 | s2 = "mfhi"; | |
13967 | goto do_divu3; | |
13968 | case M_DDIVU_3: | |
13969 | s = "ddivu"; | |
13970 | s2 = "mflo"; | |
13971 | goto do_divu3; | |
13972 | case M_DREMU_3: | |
13973 | s = "ddivu"; | |
13974 | s2 = "mfhi"; | |
13975 | do_divu3: | |
7d10b47d | 13976 | start_noreorder (); |
d8722d76 | 13977 | macro_build (NULL, s, ".,x,y", op[1], op[2]); |
252b5132 | 13978 | expr1.X_add_number = 2; |
c0ebe874 | 13979 | macro_build (&expr1, "bnez", "x,p", op[2]); |
67c0d1eb | 13980 | macro_build (NULL, "break", "6", 7); |
7d10b47d | 13981 | end_noreorder (); |
c0ebe874 | 13982 | macro_build (NULL, s2, "x", op[0]); |
252b5132 RH |
13983 | break; |
13984 | ||
13985 | case M_DMUL: | |
13986 | dbl = 1; | |
1a0670f3 | 13987 | /* Fall through. */ |
252b5132 | 13988 | case M_MUL: |
c0ebe874 RS |
13989 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", op[1], op[2]); |
13990 | macro_build (NULL, "mflo", "x", op[0]); | |
8fc2e39e | 13991 | break; |
252b5132 RH |
13992 | |
13993 | case M_DSUBU_I: | |
13994 | dbl = 1; | |
13995 | goto do_subu; | |
13996 | case M_SUBU_I: | |
13997 | do_subu: | |
252b5132 | 13998 | imm_expr.X_add_number = -imm_expr.X_add_number; |
d8722d76 | 13999 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,F", op[0], op[1]); |
252b5132 RH |
14000 | break; |
14001 | ||
14002 | case M_SUBU_I_2: | |
252b5132 | 14003 | imm_expr.X_add_number = -imm_expr.X_add_number; |
c0ebe874 | 14004 | macro_build (&imm_expr, "addiu", "x,k", op[0]); |
252b5132 RH |
14005 | break; |
14006 | ||
14007 | case M_DSUBU_I_2: | |
252b5132 | 14008 | imm_expr.X_add_number = -imm_expr.X_add_number; |
c0ebe874 | 14009 | macro_build (&imm_expr, "daddiu", "y,j", op[0]); |
252b5132 RH |
14010 | break; |
14011 | ||
14012 | case M_BEQ: | |
14013 | s = "cmp"; | |
14014 | s2 = "bteqz"; | |
14015 | goto do_branch; | |
14016 | case M_BNE: | |
14017 | s = "cmp"; | |
14018 | s2 = "btnez"; | |
14019 | goto do_branch; | |
14020 | case M_BLT: | |
14021 | s = "slt"; | |
14022 | s2 = "btnez"; | |
14023 | goto do_branch; | |
14024 | case M_BLTU: | |
14025 | s = "sltu"; | |
14026 | s2 = "btnez"; | |
14027 | goto do_branch; | |
14028 | case M_BLE: | |
14029 | s = "slt"; | |
14030 | s2 = "bteqz"; | |
14031 | goto do_reverse_branch; | |
14032 | case M_BLEU: | |
14033 | s = "sltu"; | |
14034 | s2 = "bteqz"; | |
14035 | goto do_reverse_branch; | |
14036 | case M_BGE: | |
14037 | s = "slt"; | |
14038 | s2 = "bteqz"; | |
14039 | goto do_branch; | |
14040 | case M_BGEU: | |
14041 | s = "sltu"; | |
14042 | s2 = "bteqz"; | |
14043 | goto do_branch; | |
14044 | case M_BGT: | |
14045 | s = "slt"; | |
14046 | s2 = "btnez"; | |
14047 | goto do_reverse_branch; | |
14048 | case M_BGTU: | |
14049 | s = "sltu"; | |
14050 | s2 = "btnez"; | |
14051 | ||
14052 | do_reverse_branch: | |
c0ebe874 RS |
14053 | tmp = op[1]; |
14054 | op[1] = op[0]; | |
14055 | op[0] = tmp; | |
252b5132 RH |
14056 | |
14057 | do_branch: | |
c0ebe874 | 14058 | macro_build (NULL, s, "x,y", op[0], op[1]); |
67c0d1eb | 14059 | macro_build (&offset_expr, s2, "p"); |
252b5132 RH |
14060 | break; |
14061 | ||
14062 | case M_BEQ_I: | |
14063 | s = "cmpi"; | |
14064 | s2 = "bteqz"; | |
14065 | s3 = "x,U"; | |
14066 | goto do_branch_i; | |
14067 | case M_BNE_I: | |
14068 | s = "cmpi"; | |
14069 | s2 = "btnez"; | |
14070 | s3 = "x,U"; | |
14071 | goto do_branch_i; | |
14072 | case M_BLT_I: | |
14073 | s = "slti"; | |
14074 | s2 = "btnez"; | |
14075 | s3 = "x,8"; | |
14076 | goto do_branch_i; | |
14077 | case M_BLTU_I: | |
14078 | s = "sltiu"; | |
14079 | s2 = "btnez"; | |
14080 | s3 = "x,8"; | |
14081 | goto do_branch_i; | |
14082 | case M_BLE_I: | |
14083 | s = "slti"; | |
14084 | s2 = "btnez"; | |
14085 | s3 = "x,8"; | |
14086 | goto do_addone_branch_i; | |
14087 | case M_BLEU_I: | |
14088 | s = "sltiu"; | |
14089 | s2 = "btnez"; | |
14090 | s3 = "x,8"; | |
14091 | goto do_addone_branch_i; | |
14092 | case M_BGE_I: | |
14093 | s = "slti"; | |
14094 | s2 = "bteqz"; | |
14095 | s3 = "x,8"; | |
14096 | goto do_branch_i; | |
14097 | case M_BGEU_I: | |
14098 | s = "sltiu"; | |
14099 | s2 = "bteqz"; | |
14100 | s3 = "x,8"; | |
14101 | goto do_branch_i; | |
14102 | case M_BGT_I: | |
14103 | s = "slti"; | |
14104 | s2 = "bteqz"; | |
14105 | s3 = "x,8"; | |
14106 | goto do_addone_branch_i; | |
14107 | case M_BGTU_I: | |
14108 | s = "sltiu"; | |
14109 | s2 = "bteqz"; | |
14110 | s3 = "x,8"; | |
14111 | ||
14112 | do_addone_branch_i: | |
252b5132 RH |
14113 | ++imm_expr.X_add_number; |
14114 | ||
14115 | do_branch_i: | |
c0ebe874 | 14116 | macro_build (&imm_expr, s, s3, op[0]); |
67c0d1eb | 14117 | macro_build (&offset_expr, s2, "p"); |
252b5132 RH |
14118 | break; |
14119 | ||
14120 | case M_ABS: | |
14121 | expr1.X_add_number = 0; | |
c0ebe874 RS |
14122 | macro_build (&expr1, "slti", "x,8", op[1]); |
14123 | if (op[0] != op[1]) | |
14124 | macro_build (NULL, "move", "y,X", op[0], mips16_to_32_reg_map[op[1]]); | |
252b5132 | 14125 | expr1.X_add_number = 2; |
67c0d1eb | 14126 | macro_build (&expr1, "bteqz", "p"); |
c0ebe874 | 14127 | macro_build (NULL, "neg", "x,w", op[0], op[0]); |
0acfaea6 | 14128 | break; |
252b5132 RH |
14129 | } |
14130 | } | |
14131 | ||
14daeee3 RS |
14132 | /* Look up instruction [START, START + LENGTH) in HASH. Record any extra |
14133 | opcode bits in *OPCODE_EXTRA. */ | |
14134 | ||
14135 | static struct mips_opcode * | |
14136 | mips_lookup_insn (struct hash_control *hash, const char *start, | |
da8bca91 | 14137 | ssize_t length, unsigned int *opcode_extra) |
14daeee3 RS |
14138 | { |
14139 | char *name, *dot, *p; | |
14140 | unsigned int mask, suffix; | |
da8bca91 | 14141 | ssize_t opend; |
14daeee3 RS |
14142 | struct mips_opcode *insn; |
14143 | ||
14144 | /* Make a copy of the instruction so that we can fiddle with it. */ | |
4ec9d7d5 | 14145 | name = xstrndup (start, length); |
14daeee3 RS |
14146 | |
14147 | /* Look up the instruction as-is. */ | |
14148 | insn = (struct mips_opcode *) hash_find (hash, name); | |
ee5734f0 | 14149 | if (insn) |
e1fa0163 | 14150 | goto end; |
14daeee3 RS |
14151 | |
14152 | dot = strchr (name, '.'); | |
14153 | if (dot && dot[1]) | |
14154 | { | |
14155 | /* Try to interpret the text after the dot as a VU0 channel suffix. */ | |
14156 | p = mips_parse_vu0_channels (dot + 1, &mask); | |
14157 | if (*p == 0 && mask != 0) | |
14158 | { | |
14159 | *dot = 0; | |
14160 | insn = (struct mips_opcode *) hash_find (hash, name); | |
14161 | *dot = '.'; | |
14162 | if (insn && (insn->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0) | |
14163 | { | |
14164 | *opcode_extra |= mask << mips_vu0_channel_mask.lsb; | |
e1fa0163 | 14165 | goto end; |
14daeee3 RS |
14166 | } |
14167 | } | |
14168 | } | |
14169 | ||
14170 | if (mips_opts.micromips) | |
14171 | { | |
14172 | /* See if there's an instruction size override suffix, | |
14173 | either `16' or `32', at the end of the mnemonic proper, | |
14174 | that defines the operation, i.e. before the first `.' | |
14175 | character if any. Strip it and retry. */ | |
14176 | opend = dot != NULL ? dot - name : length; | |
14177 | if (opend >= 3 && name[opend - 2] == '1' && name[opend - 1] == '6') | |
14178 | suffix = 2; | |
14179 | else if (name[opend - 2] == '3' && name[opend - 1] == '2') | |
14180 | suffix = 4; | |
14181 | else | |
14182 | suffix = 0; | |
14183 | if (suffix) | |
14184 | { | |
39334a61 | 14185 | memmove (name + opend - 2, name + opend, length - opend + 1); |
14daeee3 | 14186 | insn = (struct mips_opcode *) hash_find (hash, name); |
ee5734f0 | 14187 | if (insn) |
14daeee3 RS |
14188 | { |
14189 | forced_insn_length = suffix; | |
e1fa0163 | 14190 | goto end; |
14daeee3 RS |
14191 | } |
14192 | } | |
14193 | } | |
14194 | ||
e1fa0163 NC |
14195 | insn = NULL; |
14196 | end: | |
14197 | free (name); | |
14198 | return insn; | |
14daeee3 RS |
14199 | } |
14200 | ||
77bd4346 | 14201 | /* Assemble an instruction into its binary format. If the instruction |
e423441d RS |
14202 | is a macro, set imm_expr and offset_expr to the values associated |
14203 | with "I" and "A" operands respectively. Otherwise store the value | |
14204 | of the relocatable field (if any) in offset_expr. In both cases | |
14205 | set offset_reloc to the relocation operators applied to offset_expr. */ | |
252b5132 RH |
14206 | |
14207 | static void | |
60f20e8b | 14208 | mips_ip (char *str, struct mips_cl_insn *insn) |
252b5132 | 14209 | { |
60f20e8b | 14210 | const struct mips_opcode *first, *past; |
df58fc94 | 14211 | struct hash_control *hash; |
a92713e6 | 14212 | char format; |
14daeee3 | 14213 | size_t end; |
a92713e6 | 14214 | struct mips_operand_token *tokens; |
14daeee3 | 14215 | unsigned int opcode_extra; |
252b5132 | 14216 | |
df58fc94 RS |
14217 | if (mips_opts.micromips) |
14218 | { | |
14219 | hash = micromips_op_hash; | |
14220 | past = µmips_opcodes[bfd_micromips_num_opcodes]; | |
14221 | } | |
14222 | else | |
14223 | { | |
14224 | hash = op_hash; | |
14225 | past = &mips_opcodes[NUMOPCODES]; | |
14226 | } | |
14227 | forced_insn_length = 0; | |
14daeee3 | 14228 | opcode_extra = 0; |
252b5132 | 14229 | |
df58fc94 | 14230 | /* We first try to match an instruction up to a space or to the end. */ |
a40bc9dd RS |
14231 | for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++) |
14232 | continue; | |
bdaaa2e1 | 14233 | |
60f20e8b RS |
14234 | first = mips_lookup_insn (hash, str, end, &opcode_extra); |
14235 | if (first == NULL) | |
252b5132 | 14236 | { |
1661c76c | 14237 | set_insn_error (0, _("unrecognized opcode")); |
a40bc9dd | 14238 | return; |
252b5132 RH |
14239 | } |
14240 | ||
60f20e8b | 14241 | if (strcmp (first->name, "li.s") == 0) |
a92713e6 | 14242 | format = 'f'; |
60f20e8b | 14243 | else if (strcmp (first->name, "li.d") == 0) |
a92713e6 RS |
14244 | format = 'd'; |
14245 | else | |
14246 | format = 0; | |
14247 | tokens = mips_parse_arguments (str + end, format); | |
14248 | if (!tokens) | |
14249 | return; | |
14250 | ||
60f20e8b RS |
14251 | if (!match_insns (insn, first, past, tokens, opcode_extra, FALSE) |
14252 | && !match_insns (insn, first, past, tokens, opcode_extra, TRUE)) | |
1661c76c | 14253 | set_insn_error (0, _("invalid operands")); |
df58fc94 | 14254 | |
e3de51ce | 14255 | obstack_free (&mips_operand_tokens, tokens); |
252b5132 RH |
14256 | } |
14257 | ||
77bd4346 RS |
14258 | /* As for mips_ip, but used when assembling MIPS16 code. |
14259 | Also set forced_insn_length to the resulting instruction size in | |
14260 | bytes if the user explicitly requested a small or extended instruction. */ | |
252b5132 RH |
14261 | |
14262 | static void | |
60f20e8b | 14263 | mips16_ip (char *str, struct mips_cl_insn *insn) |
252b5132 | 14264 | { |
1a00e612 | 14265 | char *end, *s, c; |
60f20e8b | 14266 | struct mips_opcode *first; |
a92713e6 | 14267 | struct mips_operand_token *tokens; |
3fb49709 | 14268 | unsigned int l; |
252b5132 | 14269 | |
25499ac7 | 14270 | for (s = str; *s != '\0' && *s != '.' && *s != ' '; ++s) |
252b5132 | 14271 | ; |
1a00e612 RS |
14272 | end = s; |
14273 | c = *end; | |
3fb49709 MR |
14274 | |
14275 | l = 0; | |
1a00e612 | 14276 | switch (c) |
252b5132 RH |
14277 | { |
14278 | case '\0': | |
14279 | break; | |
14280 | ||
14281 | case ' ': | |
1a00e612 | 14282 | s++; |
252b5132 RH |
14283 | break; |
14284 | ||
14285 | case '.': | |
3fb49709 MR |
14286 | s++; |
14287 | if (*s == 't') | |
252b5132 | 14288 | { |
3fb49709 MR |
14289 | l = 2; |
14290 | s++; | |
252b5132 | 14291 | } |
3fb49709 | 14292 | else if (*s == 'e') |
252b5132 | 14293 | { |
3fb49709 MR |
14294 | l = 4; |
14295 | s++; | |
252b5132 | 14296 | } |
3fb49709 MR |
14297 | if (*s == '\0') |
14298 | break; | |
14299 | else if (*s++ == ' ') | |
14300 | break; | |
1661c76c | 14301 | set_insn_error (0, _("unrecognized opcode")); |
252b5132 RH |
14302 | return; |
14303 | } | |
3fb49709 | 14304 | forced_insn_length = l; |
252b5132 | 14305 | |
1a00e612 | 14306 | *end = 0; |
60f20e8b | 14307 | first = (struct mips_opcode *) hash_find (mips16_op_hash, str); |
1a00e612 RS |
14308 | *end = c; |
14309 | ||
60f20e8b | 14310 | if (!first) |
252b5132 | 14311 | { |
1661c76c | 14312 | set_insn_error (0, _("unrecognized opcode")); |
252b5132 RH |
14313 | return; |
14314 | } | |
14315 | ||
a92713e6 RS |
14316 | tokens = mips_parse_arguments (s, 0); |
14317 | if (!tokens) | |
14318 | return; | |
14319 | ||
60f20e8b | 14320 | if (!match_mips16_insns (insn, first, tokens)) |
1661c76c | 14321 | set_insn_error (0, _("invalid operands")); |
252b5132 | 14322 | |
e3de51ce | 14323 | obstack_free (&mips_operand_tokens, tokens); |
252b5132 RH |
14324 | } |
14325 | ||
b886a2ab RS |
14326 | /* Marshal immediate value VAL for an extended MIPS16 instruction. |
14327 | NBITS is the number of significant bits in VAL. */ | |
14328 | ||
14329 | static unsigned long | |
14330 | mips16_immed_extend (offsetT val, unsigned int nbits) | |
14331 | { | |
14332 | int extval; | |
25499ac7 MR |
14333 | |
14334 | extval = 0; | |
14335 | val &= (1U << nbits) - 1; | |
14336 | if (nbits == 16 || nbits == 9) | |
b886a2ab RS |
14337 | { |
14338 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
14339 | val &= 0x1f; | |
14340 | } | |
14341 | else if (nbits == 15) | |
14342 | { | |
14343 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
14344 | val &= 0xf; | |
14345 | } | |
25499ac7 | 14346 | else if (nbits == 6) |
b886a2ab RS |
14347 | { |
14348 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
14349 | val = 0; | |
14350 | } | |
14351 | return (extval << 16) | val; | |
14352 | } | |
14353 | ||
3ccad066 RS |
14354 | /* Like decode_mips16_operand, but require the operand to be defined and |
14355 | require it to be an integer. */ | |
14356 | ||
14357 | static const struct mips_int_operand * | |
14358 | mips16_immed_operand (int type, bfd_boolean extended_p) | |
14359 | { | |
14360 | const struct mips_operand *operand; | |
14361 | ||
14362 | operand = decode_mips16_operand (type, extended_p); | |
14363 | if (!operand || (operand->type != OP_INT && operand->type != OP_PCREL)) | |
14364 | abort (); | |
14365 | return (const struct mips_int_operand *) operand; | |
14366 | } | |
14367 | ||
14368 | /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */ | |
14369 | ||
14370 | static bfd_boolean | |
14371 | mips16_immed_in_range_p (const struct mips_int_operand *operand, | |
14372 | bfd_reloc_code_real_type reloc, offsetT sval) | |
14373 | { | |
14374 | int min_val, max_val; | |
14375 | ||
14376 | min_val = mips_int_operand_min (operand); | |
14377 | max_val = mips_int_operand_max (operand); | |
14378 | if (reloc != BFD_RELOC_UNUSED) | |
14379 | { | |
14380 | if (min_val < 0) | |
14381 | sval = SEXT_16BIT (sval); | |
14382 | else | |
14383 | sval &= 0xffff; | |
14384 | } | |
14385 | ||
14386 | return (sval >= min_val | |
14387 | && sval <= max_val | |
14388 | && (sval & ((1 << operand->shift) - 1)) == 0); | |
14389 | } | |
14390 | ||
5c04167a RS |
14391 | /* Install immediate value VAL into MIPS16 instruction *INSN, |
14392 | extending it if necessary. The instruction in *INSN may | |
14393 | already be extended. | |
14394 | ||
43c0598f RS |
14395 | RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED |
14396 | if none. In the former case, VAL is a 16-bit number with no | |
14397 | defined signedness. | |
14398 | ||
14399 | TYPE is the type of the immediate field. USER_INSN_LENGTH | |
14400 | is the length that the user requested, or 0 if none. */ | |
252b5132 RH |
14401 | |
14402 | static void | |
3b4dbbbf | 14403 | mips16_immed (const char *file, unsigned int line, int type, |
43c0598f | 14404 | bfd_reloc_code_real_type reloc, offsetT val, |
5c04167a | 14405 | unsigned int user_insn_length, unsigned long *insn) |
252b5132 | 14406 | { |
3ccad066 RS |
14407 | const struct mips_int_operand *operand; |
14408 | unsigned int uval, length; | |
252b5132 | 14409 | |
3ccad066 RS |
14410 | operand = mips16_immed_operand (type, FALSE); |
14411 | if (!mips16_immed_in_range_p (operand, reloc, val)) | |
5c04167a RS |
14412 | { |
14413 | /* We need an extended instruction. */ | |
14414 | if (user_insn_length == 2) | |
14415 | as_bad_where (file, line, _("invalid unextended operand value")); | |
14416 | else | |
14417 | *insn |= MIPS16_EXTEND; | |
14418 | } | |
14419 | else if (user_insn_length == 4) | |
14420 | { | |
14421 | /* The operand doesn't force an unextended instruction to be extended. | |
14422 | Warn if the user wanted an extended instruction anyway. */ | |
14423 | *insn |= MIPS16_EXTEND; | |
14424 | as_warn_where (file, line, | |
14425 | _("extended operand requested but not required")); | |
14426 | } | |
252b5132 | 14427 | |
3ccad066 RS |
14428 | length = mips16_opcode_length (*insn); |
14429 | if (length == 4) | |
252b5132 | 14430 | { |
3ccad066 RS |
14431 | operand = mips16_immed_operand (type, TRUE); |
14432 | if (!mips16_immed_in_range_p (operand, reloc, val)) | |
14433 | as_bad_where (file, line, | |
14434 | _("operand value out of range for instruction")); | |
252b5132 | 14435 | } |
3ccad066 | 14436 | uval = ((unsigned int) val >> operand->shift) - operand->bias; |
bdd15286 | 14437 | if (length == 2 || operand->root.lsb != 0) |
3ccad066 | 14438 | *insn = mips_insert_operand (&operand->root, *insn, uval); |
252b5132 | 14439 | else |
3ccad066 | 14440 | *insn |= mips16_immed_extend (uval, operand->root.size); |
252b5132 RH |
14441 | } |
14442 | \f | |
d6f16593 | 14443 | struct percent_op_match |
ad8d3bb3 | 14444 | { |
5e0116d5 RS |
14445 | const char *str; |
14446 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
14447 | }; |
14448 | ||
14449 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 14450 | { |
5e0116d5 | 14451 | {"%lo", BFD_RELOC_LO16}, |
5e0116d5 RS |
14452 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
14453 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
14454 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
14455 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
14456 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
14457 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
14458 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
14459 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
14460 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
14461 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
be3f1006 | 14462 | {"%gprel", BFD_RELOC_GPREL16}, |
5e0116d5 RS |
14463 | {"%half", BFD_RELOC_16}, |
14464 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
14465 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
14466 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
14467 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
14468 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
14469 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
14470 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
14471 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
14472 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
14473 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
7361da2c AB |
14474 | {"%hi", BFD_RELOC_HI16_S}, |
14475 | {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL}, | |
14476 | {"%pcrel_lo", BFD_RELOC_LO16_PCREL} | |
ad8d3bb3 TS |
14477 | }; |
14478 | ||
d6f16593 MR |
14479 | static const struct percent_op_match mips16_percent_op[] = |
14480 | { | |
14481 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
be3f1006 | 14482 | {"%gp_rel", BFD_RELOC_MIPS16_GPREL}, |
d6f16593 | 14483 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, |
738e5348 RS |
14484 | {"%got", BFD_RELOC_MIPS16_GOT16}, |
14485 | {"%call16", BFD_RELOC_MIPS16_CALL16}, | |
d0f13682 CLT |
14486 | {"%hi", BFD_RELOC_MIPS16_HI16_S}, |
14487 | {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD}, | |
14488 | {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM}, | |
14489 | {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16}, | |
14490 | {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16}, | |
14491 | {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16}, | |
14492 | {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16}, | |
14493 | {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL} | |
d6f16593 MR |
14494 | }; |
14495 | ||
252b5132 | 14496 | |
5e0116d5 RS |
14497 | /* Return true if *STR points to a relocation operator. When returning true, |
14498 | move *STR over the operator and store its relocation code in *RELOC. | |
14499 | Leave both *STR and *RELOC alone when returning false. */ | |
14500 | ||
14501 | static bfd_boolean | |
17a2f251 | 14502 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 14503 | { |
d6f16593 MR |
14504 | const struct percent_op_match *percent_op; |
14505 | size_t limit, i; | |
14506 | ||
14507 | if (mips_opts.mips16) | |
14508 | { | |
14509 | percent_op = mips16_percent_op; | |
14510 | limit = ARRAY_SIZE (mips16_percent_op); | |
14511 | } | |
14512 | else | |
14513 | { | |
14514 | percent_op = mips_percent_op; | |
14515 | limit = ARRAY_SIZE (mips_percent_op); | |
14516 | } | |
76b3015f | 14517 | |
d6f16593 | 14518 | for (i = 0; i < limit; i++) |
5e0116d5 | 14519 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 14520 | { |
3f98094e DJ |
14521 | int len = strlen (percent_op[i].str); |
14522 | ||
14523 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
14524 | continue; | |
14525 | ||
5e0116d5 RS |
14526 | *str += strlen (percent_op[i].str); |
14527 | *reloc = percent_op[i].reloc; | |
394f9b3a | 14528 | |
5e0116d5 RS |
14529 | /* Check whether the output BFD supports this relocation. |
14530 | If not, issue an error and fall back on something safe. */ | |
14531 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 14532 | { |
20203fb9 | 14533 | as_bad (_("relocation %s isn't supported by the current ABI"), |
5e0116d5 | 14534 | percent_op[i].str); |
01a3f561 | 14535 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 14536 | } |
5e0116d5 | 14537 | return TRUE; |
394f9b3a | 14538 | } |
5e0116d5 | 14539 | return FALSE; |
394f9b3a | 14540 | } |
ad8d3bb3 | 14541 | |
ad8d3bb3 | 14542 | |
5e0116d5 RS |
14543 | /* Parse string STR as a 16-bit relocatable operand. Store the |
14544 | expression in *EP and the relocations in the array starting | |
14545 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 14546 | |
01a3f561 | 14547 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 14548 | |
5e0116d5 | 14549 | static size_t |
17a2f251 TS |
14550 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
14551 | char *str) | |
ad8d3bb3 | 14552 | { |
5e0116d5 RS |
14553 | bfd_reloc_code_real_type reversed_reloc[3]; |
14554 | size_t reloc_index, i; | |
09b8f35a RS |
14555 | int crux_depth, str_depth; |
14556 | char *crux; | |
5e0116d5 RS |
14557 | |
14558 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
14559 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
14560 | of the main expression and with CRUX_DEPTH containing the number | |
14561 | of open brackets at that point. */ | |
14562 | reloc_index = -1; | |
14563 | str_depth = 0; | |
14564 | do | |
fb1b3232 | 14565 | { |
09b8f35a RS |
14566 | reloc_index++; |
14567 | crux = str; | |
14568 | crux_depth = str_depth; | |
14569 | ||
14570 | /* Skip over whitespace and brackets, keeping count of the number | |
14571 | of brackets. */ | |
14572 | while (*str == ' ' || *str == '\t' || *str == '(') | |
14573 | if (*str++ == '(') | |
14574 | str_depth++; | |
5e0116d5 | 14575 | } |
09b8f35a RS |
14576 | while (*str == '%' |
14577 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
14578 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 14579 | |
09b8f35a | 14580 | my_getExpression (ep, crux); |
5e0116d5 | 14581 | str = expr_end; |
394f9b3a | 14582 | |
5e0116d5 | 14583 | /* Match every open bracket. */ |
09b8f35a | 14584 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 14585 | if (*str++ == ')') |
09b8f35a | 14586 | crux_depth--; |
394f9b3a | 14587 | |
09b8f35a | 14588 | if (crux_depth > 0) |
20203fb9 | 14589 | as_bad (_("unclosed '('")); |
394f9b3a | 14590 | |
5e0116d5 | 14591 | expr_end = str; |
252b5132 | 14592 | |
01a3f561 | 14593 | if (reloc_index != 0) |
64bdfcaf RS |
14594 | { |
14595 | prev_reloc_op_frag = frag_now; | |
14596 | for (i = 0; i < reloc_index; i++) | |
14597 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
14598 | } | |
fb1b3232 | 14599 | |
5e0116d5 | 14600 | return reloc_index; |
252b5132 RH |
14601 | } |
14602 | ||
14603 | static void | |
17a2f251 | 14604 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
14605 | { |
14606 | char *save_in; | |
14607 | ||
14608 | save_in = input_line_pointer; | |
14609 | input_line_pointer = str; | |
14610 | expression (ep); | |
14611 | expr_end = input_line_pointer; | |
14612 | input_line_pointer = save_in; | |
252b5132 RH |
14613 | } |
14614 | ||
6d4af3c2 | 14615 | const char * |
17a2f251 | 14616 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 14617 | { |
499ac353 | 14618 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
252b5132 RH |
14619 | } |
14620 | ||
14621 | void | |
17a2f251 | 14622 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
14623 | { |
14624 | if (target_big_endian) | |
14625 | number_to_chars_bigendian (buf, val, n); | |
14626 | else | |
14627 | number_to_chars_littleendian (buf, val, n); | |
14628 | } | |
14629 | \f | |
e013f690 TS |
14630 | static int support_64bit_objects(void) |
14631 | { | |
14632 | const char **list, **l; | |
aa3d8fdf | 14633 | int yes; |
e013f690 TS |
14634 | |
14635 | list = bfd_target_list (); | |
14636 | for (l = list; *l != NULL; l++) | |
aeffff67 RS |
14637 | if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0 |
14638 | || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0) | |
e013f690 | 14639 | break; |
aa3d8fdf | 14640 | yes = (*l != NULL); |
e013f690 | 14641 | free (list); |
aa3d8fdf | 14642 | return yes; |
e013f690 TS |
14643 | } |
14644 | ||
316f5878 RS |
14645 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
14646 | NEW_VALUE. Warn if another value was already specified. Note: | |
14647 | we have to defer parsing the -march and -mtune arguments in order | |
14648 | to handle 'from-abi' correctly, since the ABI might be specified | |
14649 | in a later argument. */ | |
14650 | ||
14651 | static void | |
17a2f251 | 14652 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
14653 | { |
14654 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
1661c76c | 14655 | as_warn (_("a different %s was already specified, is now %s"), |
316f5878 RS |
14656 | string_ptr == &mips_arch_string ? "-march" : "-mtune", |
14657 | new_value); | |
14658 | ||
14659 | *string_ptr = new_value; | |
14660 | } | |
14661 | ||
252b5132 | 14662 | int |
17b9d67d | 14663 | md_parse_option (int c, const char *arg) |
252b5132 | 14664 | { |
c6278170 RS |
14665 | unsigned int i; |
14666 | ||
14667 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
14668 | if (c == mips_ases[i].option_on || c == mips_ases[i].option_off) | |
14669 | { | |
919731af | 14670 | file_ase_explicit |= mips_set_ase (&mips_ases[i], &file_mips_opts, |
c6278170 RS |
14671 | c == mips_ases[i].option_on); |
14672 | return 1; | |
14673 | } | |
14674 | ||
252b5132 RH |
14675 | switch (c) |
14676 | { | |
119d663a NC |
14677 | case OPTION_CONSTRUCT_FLOATS: |
14678 | mips_disable_float_construction = 0; | |
14679 | break; | |
bdaaa2e1 | 14680 | |
119d663a NC |
14681 | case OPTION_NO_CONSTRUCT_FLOATS: |
14682 | mips_disable_float_construction = 1; | |
14683 | break; | |
bdaaa2e1 | 14684 | |
252b5132 RH |
14685 | case OPTION_TRAP: |
14686 | mips_trap = 1; | |
14687 | break; | |
14688 | ||
14689 | case OPTION_BREAK: | |
14690 | mips_trap = 0; | |
14691 | break; | |
14692 | ||
14693 | case OPTION_EB: | |
14694 | target_big_endian = 1; | |
14695 | break; | |
14696 | ||
14697 | case OPTION_EL: | |
14698 | target_big_endian = 0; | |
14699 | break; | |
14700 | ||
14701 | case 'O': | |
4ffff32f TS |
14702 | if (arg == NULL) |
14703 | mips_optimize = 1; | |
14704 | else if (arg[0] == '0') | |
14705 | mips_optimize = 0; | |
14706 | else if (arg[0] == '1') | |
252b5132 RH |
14707 | mips_optimize = 1; |
14708 | else | |
14709 | mips_optimize = 2; | |
14710 | break; | |
14711 | ||
14712 | case 'g': | |
14713 | if (arg == NULL) | |
14714 | mips_debug = 2; | |
14715 | else | |
14716 | mips_debug = atoi (arg); | |
252b5132 RH |
14717 | break; |
14718 | ||
14719 | case OPTION_MIPS1: | |
0b35dfee | 14720 | file_mips_opts.isa = ISA_MIPS1; |
252b5132 RH |
14721 | break; |
14722 | ||
14723 | case OPTION_MIPS2: | |
0b35dfee | 14724 | file_mips_opts.isa = ISA_MIPS2; |
252b5132 RH |
14725 | break; |
14726 | ||
14727 | case OPTION_MIPS3: | |
0b35dfee | 14728 | file_mips_opts.isa = ISA_MIPS3; |
252b5132 RH |
14729 | break; |
14730 | ||
14731 | case OPTION_MIPS4: | |
0b35dfee | 14732 | file_mips_opts.isa = ISA_MIPS4; |
e7af610e NC |
14733 | break; |
14734 | ||
84ea6cf2 | 14735 | case OPTION_MIPS5: |
0b35dfee | 14736 | file_mips_opts.isa = ISA_MIPS5; |
84ea6cf2 NC |
14737 | break; |
14738 | ||
e7af610e | 14739 | case OPTION_MIPS32: |
0b35dfee | 14740 | file_mips_opts.isa = ISA_MIPS32; |
252b5132 RH |
14741 | break; |
14742 | ||
af7ee8bf | 14743 | case OPTION_MIPS32R2: |
0b35dfee | 14744 | file_mips_opts.isa = ISA_MIPS32R2; |
af7ee8bf CD |
14745 | break; |
14746 | ||
ae52f483 | 14747 | case OPTION_MIPS32R3: |
0ae19f05 | 14748 | file_mips_opts.isa = ISA_MIPS32R3; |
ae52f483 AB |
14749 | break; |
14750 | ||
14751 | case OPTION_MIPS32R5: | |
0ae19f05 | 14752 | file_mips_opts.isa = ISA_MIPS32R5; |
ae52f483 AB |
14753 | break; |
14754 | ||
7361da2c AB |
14755 | case OPTION_MIPS32R6: |
14756 | file_mips_opts.isa = ISA_MIPS32R6; | |
14757 | break; | |
14758 | ||
5f74bc13 | 14759 | case OPTION_MIPS64R2: |
0b35dfee | 14760 | file_mips_opts.isa = ISA_MIPS64R2; |
5f74bc13 CD |
14761 | break; |
14762 | ||
ae52f483 | 14763 | case OPTION_MIPS64R3: |
0ae19f05 | 14764 | file_mips_opts.isa = ISA_MIPS64R3; |
ae52f483 AB |
14765 | break; |
14766 | ||
14767 | case OPTION_MIPS64R5: | |
0ae19f05 | 14768 | file_mips_opts.isa = ISA_MIPS64R5; |
ae52f483 AB |
14769 | break; |
14770 | ||
7361da2c AB |
14771 | case OPTION_MIPS64R6: |
14772 | file_mips_opts.isa = ISA_MIPS64R6; | |
14773 | break; | |
14774 | ||
84ea6cf2 | 14775 | case OPTION_MIPS64: |
0b35dfee | 14776 | file_mips_opts.isa = ISA_MIPS64; |
84ea6cf2 NC |
14777 | break; |
14778 | ||
ec68c924 | 14779 | case OPTION_MTUNE: |
316f5878 RS |
14780 | mips_set_option_string (&mips_tune_string, arg); |
14781 | break; | |
ec68c924 | 14782 | |
316f5878 RS |
14783 | case OPTION_MARCH: |
14784 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
14785 | break; |
14786 | ||
14787 | case OPTION_M4650: | |
316f5878 RS |
14788 | mips_set_option_string (&mips_arch_string, "4650"); |
14789 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
14790 | break; |
14791 | ||
14792 | case OPTION_NO_M4650: | |
14793 | break; | |
14794 | ||
14795 | case OPTION_M4010: | |
316f5878 RS |
14796 | mips_set_option_string (&mips_arch_string, "4010"); |
14797 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
14798 | break; |
14799 | ||
14800 | case OPTION_NO_M4010: | |
14801 | break; | |
14802 | ||
14803 | case OPTION_M4100: | |
316f5878 RS |
14804 | mips_set_option_string (&mips_arch_string, "4100"); |
14805 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
14806 | break; |
14807 | ||
14808 | case OPTION_NO_M4100: | |
14809 | break; | |
14810 | ||
252b5132 | 14811 | case OPTION_M3900: |
316f5878 RS |
14812 | mips_set_option_string (&mips_arch_string, "3900"); |
14813 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 14814 | break; |
bdaaa2e1 | 14815 | |
252b5132 RH |
14816 | case OPTION_NO_M3900: |
14817 | break; | |
14818 | ||
df58fc94 | 14819 | case OPTION_MICROMIPS: |
919731af | 14820 | if (file_mips_opts.mips16 == 1) |
df58fc94 RS |
14821 | { |
14822 | as_bad (_("-mmicromips cannot be used with -mips16")); | |
14823 | return 0; | |
14824 | } | |
919731af | 14825 | file_mips_opts.micromips = 1; |
df58fc94 RS |
14826 | mips_no_prev_insn (); |
14827 | break; | |
14828 | ||
14829 | case OPTION_NO_MICROMIPS: | |
919731af | 14830 | file_mips_opts.micromips = 0; |
df58fc94 RS |
14831 | mips_no_prev_insn (); |
14832 | break; | |
14833 | ||
252b5132 | 14834 | case OPTION_MIPS16: |
919731af | 14835 | if (file_mips_opts.micromips == 1) |
df58fc94 RS |
14836 | { |
14837 | as_bad (_("-mips16 cannot be used with -micromips")); | |
14838 | return 0; | |
14839 | } | |
919731af | 14840 | file_mips_opts.mips16 = 1; |
7d10b47d | 14841 | mips_no_prev_insn (); |
252b5132 RH |
14842 | break; |
14843 | ||
14844 | case OPTION_NO_MIPS16: | |
919731af | 14845 | file_mips_opts.mips16 = 0; |
7d10b47d | 14846 | mips_no_prev_insn (); |
252b5132 RH |
14847 | break; |
14848 | ||
6a32d874 CM |
14849 | case OPTION_FIX_24K: |
14850 | mips_fix_24k = 1; | |
14851 | break; | |
14852 | ||
14853 | case OPTION_NO_FIX_24K: | |
14854 | mips_fix_24k = 0; | |
14855 | break; | |
14856 | ||
a8d14a88 CM |
14857 | case OPTION_FIX_RM7000: |
14858 | mips_fix_rm7000 = 1; | |
14859 | break; | |
14860 | ||
14861 | case OPTION_NO_FIX_RM7000: | |
14862 | mips_fix_rm7000 = 0; | |
14863 | break; | |
14864 | ||
6f2117ba PH |
14865 | case OPTION_FIX_LOONGSON3_LLSC: |
14866 | mips_fix_loongson3_llsc = TRUE; | |
14867 | break; | |
14868 | ||
14869 | case OPTION_NO_FIX_LOONGSON3_LLSC: | |
14870 | mips_fix_loongson3_llsc = FALSE; | |
14871 | break; | |
14872 | ||
c67a084a NC |
14873 | case OPTION_FIX_LOONGSON2F_JUMP: |
14874 | mips_fix_loongson2f_jump = TRUE; | |
14875 | break; | |
14876 | ||
14877 | case OPTION_NO_FIX_LOONGSON2F_JUMP: | |
14878 | mips_fix_loongson2f_jump = FALSE; | |
14879 | break; | |
14880 | ||
14881 | case OPTION_FIX_LOONGSON2F_NOP: | |
14882 | mips_fix_loongson2f_nop = TRUE; | |
14883 | break; | |
14884 | ||
14885 | case OPTION_NO_FIX_LOONGSON2F_NOP: | |
14886 | mips_fix_loongson2f_nop = FALSE; | |
14887 | break; | |
14888 | ||
d766e8ec RS |
14889 | case OPTION_FIX_VR4120: |
14890 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
14891 | break; |
14892 | ||
d766e8ec RS |
14893 | case OPTION_NO_FIX_VR4120: |
14894 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
14895 | break; |
14896 | ||
7d8e00cf RS |
14897 | case OPTION_FIX_VR4130: |
14898 | mips_fix_vr4130 = 1; | |
14899 | break; | |
14900 | ||
14901 | case OPTION_NO_FIX_VR4130: | |
14902 | mips_fix_vr4130 = 0; | |
14903 | break; | |
14904 | ||
d954098f DD |
14905 | case OPTION_FIX_CN63XXP1: |
14906 | mips_fix_cn63xxp1 = TRUE; | |
14907 | break; | |
14908 | ||
14909 | case OPTION_NO_FIX_CN63XXP1: | |
14910 | mips_fix_cn63xxp1 = FALSE; | |
14911 | break; | |
14912 | ||
27c634e0 FN |
14913 | case OPTION_FIX_R5900: |
14914 | mips_fix_r5900 = TRUE; | |
14915 | mips_fix_r5900_explicit = TRUE; | |
14916 | break; | |
14917 | ||
14918 | case OPTION_NO_FIX_R5900: | |
14919 | mips_fix_r5900 = FALSE; | |
14920 | mips_fix_r5900_explicit = TRUE; | |
14921 | break; | |
14922 | ||
4a6a3df4 AO |
14923 | case OPTION_RELAX_BRANCH: |
14924 | mips_relax_branch = 1; | |
14925 | break; | |
14926 | ||
14927 | case OPTION_NO_RELAX_BRANCH: | |
14928 | mips_relax_branch = 0; | |
14929 | break; | |
14930 | ||
8b10b0b3 MR |
14931 | case OPTION_IGNORE_BRANCH_ISA: |
14932 | mips_ignore_branch_isa = TRUE; | |
14933 | break; | |
14934 | ||
14935 | case OPTION_NO_IGNORE_BRANCH_ISA: | |
14936 | mips_ignore_branch_isa = FALSE; | |
14937 | break; | |
14938 | ||
833794fc | 14939 | case OPTION_INSN32: |
919731af | 14940 | file_mips_opts.insn32 = TRUE; |
833794fc MR |
14941 | break; |
14942 | ||
14943 | case OPTION_NO_INSN32: | |
919731af | 14944 | file_mips_opts.insn32 = FALSE; |
833794fc MR |
14945 | break; |
14946 | ||
aa6975fb ILT |
14947 | case OPTION_MSHARED: |
14948 | mips_in_shared = TRUE; | |
14949 | break; | |
14950 | ||
14951 | case OPTION_MNO_SHARED: | |
14952 | mips_in_shared = FALSE; | |
14953 | break; | |
14954 | ||
aed1a261 | 14955 | case OPTION_MSYM32: |
919731af | 14956 | file_mips_opts.sym32 = TRUE; |
aed1a261 RS |
14957 | break; |
14958 | ||
14959 | case OPTION_MNO_SYM32: | |
919731af | 14960 | file_mips_opts.sym32 = FALSE; |
aed1a261 RS |
14961 | break; |
14962 | ||
252b5132 RH |
14963 | /* When generating ELF code, we permit -KPIC and -call_shared to |
14964 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
14965 | intended to be compatible with Irix 5. */ | |
14966 | case OPTION_CALL_SHARED: | |
252b5132 | 14967 | mips_pic = SVR4_PIC; |
143d77c5 | 14968 | mips_abicalls = TRUE; |
252b5132 RH |
14969 | break; |
14970 | ||
861fb55a | 14971 | case OPTION_CALL_NONPIC: |
861fb55a DJ |
14972 | mips_pic = NO_PIC; |
14973 | mips_abicalls = TRUE; | |
14974 | break; | |
14975 | ||
252b5132 | 14976 | case OPTION_NON_SHARED: |
252b5132 | 14977 | mips_pic = NO_PIC; |
143d77c5 | 14978 | mips_abicalls = FALSE; |
252b5132 RH |
14979 | break; |
14980 | ||
44075ae2 TS |
14981 | /* The -xgot option tells the assembler to use 32 bit offsets |
14982 | when accessing the got in SVR4_PIC mode. It is for Irix | |
252b5132 RH |
14983 | compatibility. */ |
14984 | case OPTION_XGOT: | |
14985 | mips_big_got = 1; | |
14986 | break; | |
14987 | ||
14988 | case 'G': | |
6caf9ef4 TS |
14989 | g_switch_value = atoi (arg); |
14990 | g_switch_seen = 1; | |
252b5132 RH |
14991 | break; |
14992 | ||
34ba82a8 TS |
14993 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
14994 | and -mabi=64. */ | |
252b5132 | 14995 | case OPTION_32: |
f3ded42a | 14996 | mips_abi = O32_ABI; |
252b5132 RH |
14997 | break; |
14998 | ||
e013f690 | 14999 | case OPTION_N32: |
316f5878 | 15000 | mips_abi = N32_ABI; |
e013f690 | 15001 | break; |
252b5132 | 15002 | |
e013f690 | 15003 | case OPTION_64: |
316f5878 | 15004 | mips_abi = N64_ABI; |
f43abd2b | 15005 | if (!support_64bit_objects()) |
1661c76c | 15006 | as_fatal (_("no compiled in support for 64 bit object file format")); |
252b5132 RH |
15007 | break; |
15008 | ||
c97ef257 | 15009 | case OPTION_GP32: |
bad1aba3 | 15010 | file_mips_opts.gp = 32; |
c97ef257 AH |
15011 | break; |
15012 | ||
15013 | case OPTION_GP64: | |
bad1aba3 | 15014 | file_mips_opts.gp = 64; |
c97ef257 | 15015 | break; |
252b5132 | 15016 | |
ca4e0257 | 15017 | case OPTION_FP32: |
0b35dfee | 15018 | file_mips_opts.fp = 32; |
316f5878 RS |
15019 | break; |
15020 | ||
351cdf24 MF |
15021 | case OPTION_FPXX: |
15022 | file_mips_opts.fp = 0; | |
15023 | break; | |
15024 | ||
316f5878 | 15025 | case OPTION_FP64: |
0b35dfee | 15026 | file_mips_opts.fp = 64; |
ca4e0257 RS |
15027 | break; |
15028 | ||
351cdf24 MF |
15029 | case OPTION_ODD_SPREG: |
15030 | file_mips_opts.oddspreg = 1; | |
15031 | break; | |
15032 | ||
15033 | case OPTION_NO_ODD_SPREG: | |
15034 | file_mips_opts.oddspreg = 0; | |
15035 | break; | |
15036 | ||
037b32b9 | 15037 | case OPTION_SINGLE_FLOAT: |
0b35dfee | 15038 | file_mips_opts.single_float = 1; |
037b32b9 AN |
15039 | break; |
15040 | ||
15041 | case OPTION_DOUBLE_FLOAT: | |
0b35dfee | 15042 | file_mips_opts.single_float = 0; |
037b32b9 AN |
15043 | break; |
15044 | ||
15045 | case OPTION_SOFT_FLOAT: | |
0b35dfee | 15046 | file_mips_opts.soft_float = 1; |
037b32b9 AN |
15047 | break; |
15048 | ||
15049 | case OPTION_HARD_FLOAT: | |
0b35dfee | 15050 | file_mips_opts.soft_float = 0; |
037b32b9 AN |
15051 | break; |
15052 | ||
252b5132 | 15053 | case OPTION_MABI: |
e013f690 | 15054 | if (strcmp (arg, "32") == 0) |
316f5878 | 15055 | mips_abi = O32_ABI; |
e013f690 | 15056 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 15057 | mips_abi = O64_ABI; |
e013f690 | 15058 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 15059 | mips_abi = N32_ABI; |
e013f690 TS |
15060 | else if (strcmp (arg, "64") == 0) |
15061 | { | |
316f5878 | 15062 | mips_abi = N64_ABI; |
e013f690 | 15063 | if (! support_64bit_objects()) |
1661c76c | 15064 | as_fatal (_("no compiled in support for 64 bit object file " |
e013f690 TS |
15065 | "format")); |
15066 | } | |
15067 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 15068 | mips_abi = EABI_ABI; |
e013f690 | 15069 | else |
da0e507f TS |
15070 | { |
15071 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
15072 | return 0; | |
15073 | } | |
252b5132 RH |
15074 | break; |
15075 | ||
6b76fefe | 15076 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 15077 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
15078 | break; |
15079 | ||
9ee72ff1 | 15080 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 15081 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
15082 | break; |
15083 | ||
ecb4347a | 15084 | case OPTION_MDEBUG: |
b34976b6 | 15085 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
15086 | break; |
15087 | ||
15088 | case OPTION_NO_MDEBUG: | |
b34976b6 | 15089 | mips_flag_mdebug = FALSE; |
ecb4347a | 15090 | break; |
dcd410fe RO |
15091 | |
15092 | case OPTION_PDR: | |
15093 | mips_flag_pdr = TRUE; | |
15094 | break; | |
15095 | ||
15096 | case OPTION_NO_PDR: | |
15097 | mips_flag_pdr = FALSE; | |
15098 | break; | |
0a44bf69 RS |
15099 | |
15100 | case OPTION_MVXWORKS_PIC: | |
15101 | mips_pic = VXWORKS_PIC; | |
15102 | break; | |
ecb4347a | 15103 | |
ba92f887 MR |
15104 | case OPTION_NAN: |
15105 | if (strcmp (arg, "2008") == 0) | |
7361da2c | 15106 | mips_nan2008 = 1; |
ba92f887 | 15107 | else if (strcmp (arg, "legacy") == 0) |
7361da2c | 15108 | mips_nan2008 = 0; |
ba92f887 MR |
15109 | else |
15110 | { | |
1661c76c | 15111 | as_fatal (_("invalid NaN setting -mnan=%s"), arg); |
ba92f887 MR |
15112 | return 0; |
15113 | } | |
15114 | break; | |
15115 | ||
252b5132 RH |
15116 | default: |
15117 | return 0; | |
15118 | } | |
15119 | ||
c67a084a NC |
15120 | mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump; |
15121 | ||
252b5132 RH |
15122 | return 1; |
15123 | } | |
316f5878 | 15124 | \f |
919731af | 15125 | /* Set up globals to tune for the ISA or processor described by INFO. */ |
252b5132 | 15126 | |
316f5878 | 15127 | static void |
17a2f251 | 15128 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
15129 | { |
15130 | if (info != 0) | |
fef14a42 | 15131 | mips_tune = info->cpu; |
316f5878 | 15132 | } |
80cc45a5 | 15133 | |
34ba82a8 | 15134 | |
252b5132 | 15135 | void |
17a2f251 | 15136 | mips_after_parse_args (void) |
e9670677 | 15137 | { |
fef14a42 TS |
15138 | const struct mips_cpu_info *arch_info = 0; |
15139 | const struct mips_cpu_info *tune_info = 0; | |
15140 | ||
6f2117ba | 15141 | /* GP relative stuff not working for PE. */ |
6caf9ef4 | 15142 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
e9670677 | 15143 | { |
6caf9ef4 | 15144 | if (g_switch_seen && g_switch_value != 0) |
1661c76c | 15145 | as_bad (_("-G not supported in this configuration")); |
e9670677 MR |
15146 | g_switch_value = 0; |
15147 | } | |
15148 | ||
cac012d6 AO |
15149 | if (mips_abi == NO_ABI) |
15150 | mips_abi = MIPS_DEFAULT_ABI; | |
15151 | ||
919731af | 15152 | /* The following code determines the architecture. |
22923709 RS |
15153 | Similar code was added to GCC 3.3 (see override_options() in |
15154 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
15155 | as much as possible. */ | |
e9670677 | 15156 | |
316f5878 | 15157 | if (mips_arch_string != 0) |
fef14a42 | 15158 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 15159 | |
0b35dfee | 15160 | if (file_mips_opts.isa != ISA_UNKNOWN) |
e9670677 | 15161 | { |
0b35dfee | 15162 | /* Handle -mipsN. At this point, file_mips_opts.isa contains the |
fef14a42 | 15163 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 15164 | the -march selection (if any). */ |
fef14a42 | 15165 | if (arch_info != 0) |
e9670677 | 15166 | { |
316f5878 RS |
15167 | /* -march takes precedence over -mipsN, since it is more descriptive. |
15168 | There's no harm in specifying both as long as the ISA levels | |
15169 | are the same. */ | |
0b35dfee | 15170 | if (file_mips_opts.isa != arch_info->isa) |
1661c76c RS |
15171 | as_bad (_("-%s conflicts with the other architecture options," |
15172 | " which imply -%s"), | |
0b35dfee | 15173 | mips_cpu_info_from_isa (file_mips_opts.isa)->name, |
fef14a42 | 15174 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 15175 | } |
316f5878 | 15176 | else |
0b35dfee | 15177 | arch_info = mips_cpu_info_from_isa (file_mips_opts.isa); |
e9670677 MR |
15178 | } |
15179 | ||
fef14a42 | 15180 | if (arch_info == 0) |
95bfe26e MF |
15181 | { |
15182 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
15183 | gas_assert (arch_info); | |
15184 | } | |
e9670677 | 15185 | |
fef14a42 | 15186 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
20203fb9 | 15187 | as_bad (_("-march=%s is not compatible with the selected ABI"), |
fef14a42 TS |
15188 | arch_info->name); |
15189 | ||
919731af | 15190 | file_mips_opts.arch = arch_info->cpu; |
15191 | file_mips_opts.isa = arch_info->isa; | |
15192 | ||
15193 | /* Set up initial mips_opts state. */ | |
15194 | mips_opts = file_mips_opts; | |
15195 | ||
27c634e0 FN |
15196 | /* For the R5900 default to `-mfix-r5900' unless the user told otherwise. */ |
15197 | if (!mips_fix_r5900_explicit) | |
15198 | mips_fix_r5900 = file_mips_opts.arch == CPU_R5900; | |
15199 | ||
919731af | 15200 | /* The register size inference code is now placed in |
15201 | file_mips_check_options. */ | |
fef14a42 | 15202 | |
0b35dfee | 15203 | /* Optimize for file_mips_opts.arch, unless -mtune selects a different |
15204 | processor. */ | |
fef14a42 TS |
15205 | if (mips_tune_string != 0) |
15206 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 15207 | |
fef14a42 TS |
15208 | if (tune_info == 0) |
15209 | mips_set_tune (arch_info); | |
15210 | else | |
15211 | mips_set_tune (tune_info); | |
e9670677 | 15212 | |
ecb4347a | 15213 | if (mips_flag_mdebug < 0) |
e8044f35 | 15214 | mips_flag_mdebug = 0; |
e9670677 MR |
15215 | } |
15216 | \f | |
15217 | void | |
17a2f251 | 15218 | mips_init_after_args (void) |
252b5132 | 15219 | { |
6f2117ba | 15220 | /* Initialize opcodes. */ |
252b5132 | 15221 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; |
beae10d5 | 15222 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
15223 | } |
15224 | ||
15225 | long | |
17a2f251 | 15226 | md_pcrel_from (fixS *fixP) |
252b5132 | 15227 | { |
a7ebbfdf | 15228 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
6f2117ba | 15229 | |
a7ebbfdf TS |
15230 | switch (fixP->fx_r_type) |
15231 | { | |
df58fc94 RS |
15232 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15233 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15234 | /* Return the address of the delay slot. */ | |
15235 | return addr + 2; | |
15236 | ||
15237 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15238 | case BFD_RELOC_MICROMIPS_JMP: | |
c9775dde | 15239 | case BFD_RELOC_MIPS16_16_PCREL_S1: |
a7ebbfdf | 15240 | case BFD_RELOC_16_PCREL_S2: |
7361da2c AB |
15241 | case BFD_RELOC_MIPS_21_PCREL_S2: |
15242 | case BFD_RELOC_MIPS_26_PCREL_S2: | |
a7ebbfdf TS |
15243 | case BFD_RELOC_MIPS_JMP: |
15244 | /* Return the address of the delay slot. */ | |
15245 | return addr + 4; | |
df58fc94 | 15246 | |
51f6035b MR |
15247 | case BFD_RELOC_MIPS_18_PCREL_S3: |
15248 | /* Return the aligned address of the doubleword containing | |
15249 | the instruction. */ | |
15250 | return addr & ~7; | |
15251 | ||
a7ebbfdf TS |
15252 | default: |
15253 | return addr; | |
15254 | } | |
252b5132 RH |
15255 | } |
15256 | ||
252b5132 RH |
15257 | /* This is called before the symbol table is processed. In order to |
15258 | work with gcc when using mips-tfile, we must keep all local labels. | |
15259 | However, in other cases, we want to discard them. If we were | |
15260 | called with -g, but we didn't see any debugging information, it may | |
15261 | mean that gcc is smuggling debugging information through to | |
15262 | mips-tfile, in which case we must generate all local labels. */ | |
15263 | ||
15264 | void | |
17a2f251 | 15265 | mips_frob_file_before_adjust (void) |
252b5132 RH |
15266 | { |
15267 | #ifndef NO_ECOFF_DEBUGGING | |
15268 | if (ECOFF_DEBUGGING | |
15269 | && mips_debug != 0 | |
15270 | && ! ecoff_debugging_seen) | |
15271 | flag_keep_locals = 1; | |
15272 | #endif | |
15273 | } | |
15274 | ||
3b91255e | 15275 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
55cf6793 | 15276 | the corresponding LO16 reloc. This is called before md_apply_fix and |
3b91255e RS |
15277 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit |
15278 | relocation operators. | |
15279 | ||
15280 | For our purposes, a %lo() expression matches a %got() or %hi() | |
15281 | expression if: | |
15282 | ||
15283 | (a) it refers to the same symbol; and | |
15284 | (b) the offset applied in the %lo() expression is no lower than | |
15285 | the offset applied in the %got() or %hi(). | |
15286 | ||
15287 | (b) allows us to cope with code like: | |
15288 | ||
15289 | lui $4,%hi(foo) | |
15290 | lh $4,%lo(foo+2)($4) | |
15291 | ||
15292 | ...which is legal on RELA targets, and has a well-defined behaviour | |
15293 | if the user knows that adding 2 to "foo" will not induce a carry to | |
15294 | the high 16 bits. | |
15295 | ||
15296 | When several %lo()s match a particular %got() or %hi(), we use the | |
15297 | following rules to distinguish them: | |
15298 | ||
15299 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
15300 | higher offsets. | |
15301 | ||
15302 | (2) %lo()s with no matching %got() or %hi() are better than those | |
15303 | that already have a matching %got() or %hi(). | |
15304 | ||
15305 | (3) later %lo()s are better than earlier %lo()s. | |
15306 | ||
15307 | These rules are applied in order. | |
15308 | ||
15309 | (1) means, among other things, that %lo()s with identical offsets are | |
15310 | chosen if they exist. | |
15311 | ||
15312 | (2) means that we won't associate several high-part relocations with | |
15313 | the same low-part relocation unless there's no alternative. Having | |
15314 | several high parts for the same low part is a GNU extension; this rule | |
15315 | allows careful users to avoid it. | |
15316 | ||
15317 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
15318 | with the last high-part relocation being at the front of the list. | |
15319 | It therefore makes sense to choose the last matching low-part | |
15320 | relocation, all other things being equal. It's also easier | |
15321 | to code that way. */ | |
252b5132 RH |
15322 | |
15323 | void | |
17a2f251 | 15324 | mips_frob_file (void) |
252b5132 RH |
15325 | { |
15326 | struct mips_hi_fixup *l; | |
35903be0 | 15327 | bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED; |
252b5132 RH |
15328 | |
15329 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
15330 | { | |
15331 | segment_info_type *seginfo; | |
3b91255e RS |
15332 | bfd_boolean matched_lo_p; |
15333 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 15334 | |
9c2799c2 | 15335 | gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 15336 | |
5919d012 | 15337 | /* If a GOT16 relocation turns out to be against a global symbol, |
b886a2ab RS |
15338 | there isn't supposed to be a matching LO. Ignore %gots against |
15339 | constants; we'll report an error for those later. */ | |
738e5348 | 15340 | if (got16_reloc_p (l->fixp->fx_r_type) |
b886a2ab | 15341 | && !(l->fixp->fx_addsy |
9e009953 | 15342 | && pic_need_relax (l->fixp->fx_addsy))) |
5919d012 RS |
15343 | continue; |
15344 | ||
15345 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
15346 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
15347 | continue; |
15348 | ||
252b5132 | 15349 | seginfo = seg_info (l->seg); |
252b5132 | 15350 | |
3b91255e RS |
15351 | /* Set HI_POS to the position of this relocation in the chain. |
15352 | Set LO_POS to the position of the chosen low-part relocation. | |
15353 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
15354 | relocation that matches an immediately-preceding high-part | |
15355 | relocation. */ | |
15356 | hi_pos = NULL; | |
15357 | lo_pos = NULL; | |
15358 | matched_lo_p = FALSE; | |
738e5348 | 15359 | looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type); |
35903be0 | 15360 | |
3b91255e RS |
15361 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) |
15362 | { | |
15363 | if (*pos == l->fixp) | |
15364 | hi_pos = pos; | |
15365 | ||
35903be0 | 15366 | if ((*pos)->fx_r_type == looking_for_rtype |
30cfc97a | 15367 | && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy) |
3b91255e RS |
15368 | && (*pos)->fx_offset >= l->fixp->fx_offset |
15369 | && (lo_pos == NULL | |
15370 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
15371 | || (!matched_lo_p | |
15372 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
15373 | lo_pos = pos; | |
15374 | ||
15375 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
15376 | && fixup_has_matching_lo_p (*pos)); | |
15377 | } | |
15378 | ||
15379 | /* If we found a match, remove the high-part relocation from its | |
15380 | current position and insert it before the low-part relocation. | |
15381 | Make the offsets match so that fixup_has_matching_lo_p() | |
15382 | will return true. | |
15383 | ||
15384 | We don't warn about unmatched high-part relocations since some | |
15385 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
15386 | instructions. */ | |
15387 | if (lo_pos != NULL) | |
15388 | { | |
15389 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
15390 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 15391 | { |
3b91255e RS |
15392 | *hi_pos = l->fixp->fx_next; |
15393 | l->fixp->fx_next = *lo_pos; | |
15394 | *lo_pos = l->fixp; | |
252b5132 | 15395 | } |
252b5132 RH |
15396 | } |
15397 | } | |
15398 | } | |
15399 | ||
252b5132 | 15400 | int |
17a2f251 | 15401 | mips_force_relocation (fixS *fixp) |
252b5132 | 15402 | { |
ae6063d4 | 15403 | if (generic_force_reloc (fixp)) |
252b5132 RH |
15404 | return 1; |
15405 | ||
df58fc94 RS |
15406 | /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation, |
15407 | so that the linker relaxation can update targets. */ | |
15408 | if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
15409 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
15410 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1) | |
15411 | return 1; | |
15412 | ||
5caa2b07 MR |
15413 | /* We want to keep BFD_RELOC_16_PCREL_S2 BFD_RELOC_MIPS_21_PCREL_S2 |
15414 | and BFD_RELOC_MIPS_26_PCREL_S2 relocations against MIPS16 and | |
15415 | microMIPS symbols so that we can do cross-mode branch diagnostics | |
15416 | and BAL to JALX conversion by the linker. */ | |
15417 | if ((fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 | |
9d862524 MR |
15418 | || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2 |
15419 | || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2) | |
15420 | && fixp->fx_addsy | |
15421 | && ELF_ST_IS_COMPRESSED (S_GET_OTHER (fixp->fx_addsy))) | |
15422 | return 1; | |
15423 | ||
7361da2c | 15424 | /* We want all PC-relative relocations to be kept for R6 relaxation. */ |
912815f0 | 15425 | if (ISA_IS_R6 (file_mips_opts.isa) |
7361da2c AB |
15426 | && (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 |
15427 | || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2 | |
15428 | || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2 | |
15429 | || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3 | |
15430 | || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2 | |
15431 | || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL | |
15432 | || fixp->fx_r_type == BFD_RELOC_LO16_PCREL)) | |
15433 | return 1; | |
15434 | ||
3e722fb5 | 15435 | return 0; |
252b5132 RH |
15436 | } |
15437 | ||
b416ba9b MR |
15438 | /* Implement TC_FORCE_RELOCATION_ABS. */ |
15439 | ||
15440 | bfd_boolean | |
15441 | mips_force_relocation_abs (fixS *fixp) | |
15442 | { | |
15443 | if (generic_force_reloc (fixp)) | |
15444 | return TRUE; | |
15445 | ||
15446 | /* These relocations do not have enough bits in the in-place addend | |
15447 | to hold an arbitrary absolute section's offset. */ | |
15448 | if (HAVE_IN_PLACE_ADDENDS && limited_pcrel_reloc_p (fixp->fx_r_type)) | |
15449 | return TRUE; | |
15450 | ||
15451 | return FALSE; | |
15452 | } | |
15453 | ||
b886a2ab RS |
15454 | /* Read the instruction associated with RELOC from BUF. */ |
15455 | ||
15456 | static unsigned int | |
15457 | read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc) | |
15458 | { | |
15459 | if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) | |
15460 | return read_compressed_insn (buf, 4); | |
15461 | else | |
15462 | return read_insn (buf); | |
15463 | } | |
15464 | ||
15465 | /* Write instruction INSN to BUF, given that it has been relocated | |
15466 | by RELOC. */ | |
15467 | ||
15468 | static void | |
15469 | write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc, | |
15470 | unsigned long insn) | |
15471 | { | |
15472 | if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) | |
15473 | write_compressed_insn (buf, insn, 4); | |
15474 | else | |
15475 | write_insn (buf, insn); | |
15476 | } | |
15477 | ||
9d862524 MR |
15478 | /* Return TRUE if the instruction pointed to by FIXP is an invalid jump |
15479 | to a symbol in another ISA mode, which cannot be converted to JALX. */ | |
15480 | ||
15481 | static bfd_boolean | |
15482 | fix_bad_cross_mode_jump_p (fixS *fixP) | |
15483 | { | |
15484 | unsigned long opcode; | |
15485 | int other; | |
15486 | char *buf; | |
15487 | ||
15488 | if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) | |
15489 | return FALSE; | |
15490 | ||
15491 | other = S_GET_OTHER (fixP->fx_addsy); | |
15492 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; | |
15493 | opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 26; | |
15494 | switch (fixP->fx_r_type) | |
15495 | { | |
15496 | case BFD_RELOC_MIPS_JMP: | |
15497 | return opcode != 0x1d && opcode != 0x03 && ELF_ST_IS_COMPRESSED (other); | |
15498 | case BFD_RELOC_MICROMIPS_JMP: | |
15499 | return opcode != 0x3c && opcode != 0x3d && !ELF_ST_IS_MICROMIPS (other); | |
15500 | default: | |
15501 | return FALSE; | |
15502 | } | |
15503 | } | |
15504 | ||
15505 | /* Return TRUE if the instruction pointed to by FIXP is an invalid JALX | |
15506 | jump to a symbol in the same ISA mode. */ | |
15507 | ||
15508 | static bfd_boolean | |
15509 | fix_bad_same_mode_jalx_p (fixS *fixP) | |
15510 | { | |
15511 | unsigned long opcode; | |
15512 | int other; | |
15513 | char *buf; | |
15514 | ||
15515 | if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) | |
15516 | return FALSE; | |
15517 | ||
15518 | other = S_GET_OTHER (fixP->fx_addsy); | |
15519 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; | |
15520 | opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 26; | |
15521 | switch (fixP->fx_r_type) | |
15522 | { | |
15523 | case BFD_RELOC_MIPS_JMP: | |
15524 | return opcode == 0x1d && !ELF_ST_IS_COMPRESSED (other); | |
15525 | case BFD_RELOC_MIPS16_JMP: | |
15526 | return opcode == 0x07 && ELF_ST_IS_COMPRESSED (other); | |
15527 | case BFD_RELOC_MICROMIPS_JMP: | |
15528 | return opcode == 0x3c && ELF_ST_IS_COMPRESSED (other); | |
15529 | default: | |
15530 | return FALSE; | |
15531 | } | |
15532 | } | |
15533 | ||
15534 | /* Return TRUE if the instruction pointed to by FIXP is an invalid jump | |
15535 | to a symbol whose value plus addend is not aligned according to the | |
15536 | ultimate (after linker relaxation) jump instruction's immediate field | |
15537 | requirement, either to (1 << SHIFT), or, for jumps from microMIPS to | |
15538 | regular MIPS code, to (1 << 2). */ | |
15539 | ||
15540 | static bfd_boolean | |
15541 | fix_bad_misaligned_jump_p (fixS *fixP, int shift) | |
15542 | { | |
15543 | bfd_boolean micro_to_mips_p; | |
15544 | valueT val; | |
15545 | int other; | |
15546 | ||
15547 | if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) | |
15548 | return FALSE; | |
15549 | ||
15550 | other = S_GET_OTHER (fixP->fx_addsy); | |
15551 | val = S_GET_VALUE (fixP->fx_addsy) | ELF_ST_IS_COMPRESSED (other); | |
15552 | val += fixP->fx_offset; | |
15553 | micro_to_mips_p = (fixP->fx_r_type == BFD_RELOC_MICROMIPS_JMP | |
15554 | && !ELF_ST_IS_MICROMIPS (other)); | |
15555 | return ((val & ((1 << (micro_to_mips_p ? 2 : shift)) - 1)) | |
15556 | != ELF_ST_IS_COMPRESSED (other)); | |
15557 | } | |
15558 | ||
15559 | /* Return TRUE if the instruction pointed to by FIXP is an invalid branch | |
15560 | to a symbol whose annotation indicates another ISA mode. For absolute | |
a6ebf616 MR |
15561 | symbols check the ISA bit instead. |
15562 | ||
15563 | We accept BFD_RELOC_16_PCREL_S2 relocations against MIPS16 and microMIPS | |
15564 | symbols or BFD_RELOC_MICROMIPS_16_PCREL_S1 relocations against regular | |
15565 | MIPS symbols and associated with BAL instructions as these instructions | |
de194d85 | 15566 | may be converted to JALX by the linker. */ |
9d862524 MR |
15567 | |
15568 | static bfd_boolean | |
15569 | fix_bad_cross_mode_branch_p (fixS *fixP) | |
15570 | { | |
15571 | bfd_boolean absolute_p; | |
15572 | unsigned long opcode; | |
15573 | asection *symsec; | |
15574 | valueT val; | |
15575 | int other; | |
15576 | char *buf; | |
15577 | ||
8b10b0b3 MR |
15578 | if (mips_ignore_branch_isa) |
15579 | return FALSE; | |
15580 | ||
9d862524 MR |
15581 | if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) |
15582 | return FALSE; | |
15583 | ||
15584 | symsec = S_GET_SEGMENT (fixP->fx_addsy); | |
15585 | absolute_p = bfd_is_abs_section (symsec); | |
15586 | ||
15587 | val = S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset; | |
15588 | other = S_GET_OTHER (fixP->fx_addsy); | |
15589 | ||
15590 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; | |
15591 | opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 16; | |
15592 | switch (fixP->fx_r_type) | |
15593 | { | |
15594 | case BFD_RELOC_16_PCREL_S2: | |
a6ebf616 MR |
15595 | return ((absolute_p ? val & 1 : ELF_ST_IS_COMPRESSED (other)) |
15596 | && opcode != 0x0411); | |
15597 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15598 | return ((absolute_p ? !(val & 1) : !ELF_ST_IS_MICROMIPS (other)) | |
15599 | && opcode != 0x4060); | |
9d862524 MR |
15600 | case BFD_RELOC_MIPS_21_PCREL_S2: |
15601 | case BFD_RELOC_MIPS_26_PCREL_S2: | |
15602 | return absolute_p ? val & 1 : ELF_ST_IS_COMPRESSED (other); | |
15603 | case BFD_RELOC_MIPS16_16_PCREL_S1: | |
15604 | return absolute_p ? !(val & 1) : !ELF_ST_IS_MIPS16 (other); | |
15605 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: | |
15606 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
9d862524 MR |
15607 | return absolute_p ? !(val & 1) : !ELF_ST_IS_MICROMIPS (other); |
15608 | default: | |
15609 | abort (); | |
15610 | } | |
15611 | } | |
15612 | ||
15613 | /* Return TRUE if the symbol plus addend associated with a regular MIPS | |
15614 | branch instruction pointed to by FIXP is not aligned according to the | |
15615 | branch instruction's immediate field requirement. We need the addend | |
15616 | to preserve the ISA bit and also the sum must not have bit 2 set. We | |
15617 | must explicitly OR in the ISA bit from symbol annotation as the bit | |
15618 | won't be set in the symbol's value then. */ | |
15619 | ||
15620 | static bfd_boolean | |
15621 | fix_bad_misaligned_branch_p (fixS *fixP) | |
15622 | { | |
15623 | bfd_boolean absolute_p; | |
15624 | asection *symsec; | |
15625 | valueT isa_bit; | |
15626 | valueT val; | |
15627 | valueT off; | |
15628 | int other; | |
15629 | ||
15630 | if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) | |
15631 | return FALSE; | |
15632 | ||
15633 | symsec = S_GET_SEGMENT (fixP->fx_addsy); | |
15634 | absolute_p = bfd_is_abs_section (symsec); | |
15635 | ||
15636 | val = S_GET_VALUE (fixP->fx_addsy); | |
15637 | other = S_GET_OTHER (fixP->fx_addsy); | |
15638 | off = fixP->fx_offset; | |
15639 | ||
15640 | isa_bit = absolute_p ? (val + off) & 1 : ELF_ST_IS_COMPRESSED (other); | |
15641 | val |= ELF_ST_IS_COMPRESSED (other); | |
15642 | val += off; | |
15643 | return (val & 0x3) != isa_bit; | |
15644 | } | |
15645 | ||
15646 | /* Make the necessary checks on a regular MIPS branch pointed to by FIXP | |
15647 | and its calculated value VAL. */ | |
15648 | ||
15649 | static void | |
15650 | fix_validate_branch (fixS *fixP, valueT val) | |
15651 | { | |
15652 | if (fixP->fx_done && (val & 0x3) != 0) | |
15653 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15654 | _("branch to misaligned address (0x%lx)"), | |
15655 | (long) (val + md_pcrel_from (fixP))); | |
15656 | else if (fix_bad_cross_mode_branch_p (fixP)) | |
15657 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15658 | _("branch to a symbol in another ISA mode")); | |
15659 | else if (fix_bad_misaligned_branch_p (fixP)) | |
15660 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15661 | _("branch to misaligned address (0x%lx)"), | |
15662 | (long) (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset)); | |
15663 | else if (HAVE_IN_PLACE_ADDENDS && (fixP->fx_offset & 0x3) != 0) | |
15664 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15665 | _("cannot encode misaligned addend " | |
15666 | "in the relocatable field (0x%lx)"), | |
15667 | (long) fixP->fx_offset); | |
15668 | } | |
15669 | ||
252b5132 RH |
15670 | /* Apply a fixup to the object file. */ |
15671 | ||
94f592af | 15672 | void |
55cf6793 | 15673 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 15674 | { |
4d68580a | 15675 | char *buf; |
b886a2ab | 15676 | unsigned long insn; |
a7ebbfdf | 15677 | reloc_howto_type *howto; |
252b5132 | 15678 | |
d56a8dda RS |
15679 | if (fixP->fx_pcrel) |
15680 | switch (fixP->fx_r_type) | |
15681 | { | |
15682 | case BFD_RELOC_16_PCREL_S2: | |
c9775dde | 15683 | case BFD_RELOC_MIPS16_16_PCREL_S1: |
d56a8dda RS |
15684 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15685 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15686 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15687 | case BFD_RELOC_32_PCREL: | |
7361da2c AB |
15688 | case BFD_RELOC_MIPS_21_PCREL_S2: |
15689 | case BFD_RELOC_MIPS_26_PCREL_S2: | |
15690 | case BFD_RELOC_MIPS_18_PCREL_S3: | |
15691 | case BFD_RELOC_MIPS_19_PCREL_S2: | |
15692 | case BFD_RELOC_HI16_S_PCREL: | |
15693 | case BFD_RELOC_LO16_PCREL: | |
d56a8dda RS |
15694 | break; |
15695 | ||
15696 | case BFD_RELOC_32: | |
15697 | fixP->fx_r_type = BFD_RELOC_32_PCREL; | |
15698 | break; | |
15699 | ||
15700 | default: | |
15701 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15702 | _("PC-relative reference to a different section")); | |
15703 | break; | |
15704 | } | |
15705 | ||
15706 | /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations | |
15707 | that have no MIPS ELF equivalent. */ | |
15708 | if (fixP->fx_r_type != BFD_RELOC_8) | |
15709 | { | |
15710 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
15711 | if (!howto) | |
15712 | return; | |
15713 | } | |
65551fa4 | 15714 | |
df58fc94 RS |
15715 | gas_assert (fixP->fx_size == 2 |
15716 | || fixP->fx_size == 4 | |
d56a8dda | 15717 | || fixP->fx_r_type == BFD_RELOC_8 |
90ecf173 MR |
15718 | || fixP->fx_r_type == BFD_RELOC_16 |
15719 | || fixP->fx_r_type == BFD_RELOC_64 | |
15720 | || fixP->fx_r_type == BFD_RELOC_CTOR | |
15721 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
df58fc94 | 15722 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB |
90ecf173 MR |
15723 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
15724 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY | |
2f0c68f2 CM |
15725 | || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64 |
15726 | || fixP->fx_r_type == BFD_RELOC_NONE); | |
252b5132 | 15727 | |
4d68580a | 15728 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; |
252b5132 | 15729 | |
b1dca8ee RS |
15730 | /* Don't treat parts of a composite relocation as done. There are two |
15731 | reasons for this: | |
15732 | ||
15733 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
15734 | should nevertheless be emitted if the first part is. | |
15735 | ||
15736 | (2) In normal usage, composite relocations are never assembly-time | |
15737 | constants. The easiest way of dealing with the pathological | |
15738 | exceptions is to generate a relocation against STN_UNDEF and | |
15739 | leave everything up to the linker. */ | |
3994f87e | 15740 | if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0) |
252b5132 RH |
15741 | fixP->fx_done = 1; |
15742 | ||
15743 | switch (fixP->fx_r_type) | |
15744 | { | |
3f98094e DJ |
15745 | case BFD_RELOC_MIPS_TLS_GD: |
15746 | case BFD_RELOC_MIPS_TLS_LDM: | |
741d6ea8 JM |
15747 | case BFD_RELOC_MIPS_TLS_DTPREL32: |
15748 | case BFD_RELOC_MIPS_TLS_DTPREL64: | |
3f98094e DJ |
15749 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: |
15750 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
15751 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
d0f13682 CLT |
15752 | case BFD_RELOC_MIPS_TLS_TPREL32: |
15753 | case BFD_RELOC_MIPS_TLS_TPREL64: | |
3f98094e DJ |
15754 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: |
15755 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
df58fc94 RS |
15756 | case BFD_RELOC_MICROMIPS_TLS_GD: |
15757 | case BFD_RELOC_MICROMIPS_TLS_LDM: | |
15758 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16: | |
15759 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16: | |
15760 | case BFD_RELOC_MICROMIPS_TLS_GOTTPREL: | |
15761 | case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16: | |
15762 | case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16: | |
d0f13682 CLT |
15763 | case BFD_RELOC_MIPS16_TLS_GD: |
15764 | case BFD_RELOC_MIPS16_TLS_LDM: | |
15765 | case BFD_RELOC_MIPS16_TLS_DTPREL_HI16: | |
15766 | case BFD_RELOC_MIPS16_TLS_DTPREL_LO16: | |
15767 | case BFD_RELOC_MIPS16_TLS_GOTTPREL: | |
15768 | case BFD_RELOC_MIPS16_TLS_TPREL_HI16: | |
15769 | case BFD_RELOC_MIPS16_TLS_TPREL_LO16: | |
4512dafa MR |
15770 | if (fixP->fx_addsy) |
15771 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
15772 | else | |
15773 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15774 | _("TLS relocation against a constant")); | |
15775 | break; | |
3f98094e | 15776 | |
252b5132 | 15777 | case BFD_RELOC_MIPS_JMP: |
9d862524 MR |
15778 | case BFD_RELOC_MIPS16_JMP: |
15779 | case BFD_RELOC_MICROMIPS_JMP: | |
15780 | { | |
15781 | int shift; | |
15782 | ||
15783 | gas_assert (!fixP->fx_done); | |
15784 | ||
15785 | /* Shift is 2, unusually, for microMIPS JALX. */ | |
15786 | if (fixP->fx_r_type == BFD_RELOC_MICROMIPS_JMP | |
15787 | && (read_compressed_insn (buf, 4) >> 26) != 0x3c) | |
15788 | shift = 1; | |
15789 | else | |
15790 | shift = 2; | |
15791 | ||
15792 | if (fix_bad_cross_mode_jump_p (fixP)) | |
15793 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15794 | _("jump to a symbol in another ISA mode")); | |
15795 | else if (fix_bad_same_mode_jalx_p (fixP)) | |
15796 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15797 | _("JALX to a symbol in the same ISA mode")); | |
15798 | else if (fix_bad_misaligned_jump_p (fixP, shift)) | |
15799 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15800 | _("jump to misaligned address (0x%lx)"), | |
15801 | (long) (S_GET_VALUE (fixP->fx_addsy) | |
15802 | + fixP->fx_offset)); | |
15803 | else if (HAVE_IN_PLACE_ADDENDS | |
15804 | && (fixP->fx_offset & ((1 << shift) - 1)) != 0) | |
15805 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15806 | _("cannot encode misaligned addend " | |
15807 | "in the relocatable field (0x%lx)"), | |
15808 | (long) fixP->fx_offset); | |
15809 | } | |
15810 | /* Fall through. */ | |
15811 | ||
e369bcce TS |
15812 | case BFD_RELOC_MIPS_SHIFT5: |
15813 | case BFD_RELOC_MIPS_SHIFT6: | |
15814 | case BFD_RELOC_MIPS_GOT_DISP: | |
15815 | case BFD_RELOC_MIPS_GOT_PAGE: | |
15816 | case BFD_RELOC_MIPS_GOT_OFST: | |
15817 | case BFD_RELOC_MIPS_SUB: | |
15818 | case BFD_RELOC_MIPS_INSERT_A: | |
15819 | case BFD_RELOC_MIPS_INSERT_B: | |
15820 | case BFD_RELOC_MIPS_DELETE: | |
15821 | case BFD_RELOC_MIPS_HIGHEST: | |
15822 | case BFD_RELOC_MIPS_HIGHER: | |
15823 | case BFD_RELOC_MIPS_SCN_DISP: | |
15824 | case BFD_RELOC_MIPS_REL16: | |
15825 | case BFD_RELOC_MIPS_RELGOT: | |
15826 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
15827 | case BFD_RELOC_HI16: |
15828 | case BFD_RELOC_HI16_S: | |
b886a2ab | 15829 | case BFD_RELOC_LO16: |
cdf6fd85 | 15830 | case BFD_RELOC_GPREL16: |
252b5132 RH |
15831 | case BFD_RELOC_MIPS_LITERAL: |
15832 | case BFD_RELOC_MIPS_CALL16: | |
15833 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 15834 | case BFD_RELOC_GPREL32: |
252b5132 RH |
15835 | case BFD_RELOC_MIPS_GOT_HI16: |
15836 | case BFD_RELOC_MIPS_GOT_LO16: | |
15837 | case BFD_RELOC_MIPS_CALL_HI16: | |
15838 | case BFD_RELOC_MIPS_CALL_LO16: | |
41947d9e MR |
15839 | case BFD_RELOC_HI16_S_PCREL: |
15840 | case BFD_RELOC_LO16_PCREL: | |
252b5132 | 15841 | case BFD_RELOC_MIPS16_GPREL: |
738e5348 RS |
15842 | case BFD_RELOC_MIPS16_GOT16: |
15843 | case BFD_RELOC_MIPS16_CALL16: | |
d6f16593 MR |
15844 | case BFD_RELOC_MIPS16_HI16: |
15845 | case BFD_RELOC_MIPS16_HI16_S: | |
b886a2ab | 15846 | case BFD_RELOC_MIPS16_LO16: |
df58fc94 RS |
15847 | case BFD_RELOC_MICROMIPS_GOT_DISP: |
15848 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
15849 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
15850 | case BFD_RELOC_MICROMIPS_SUB: | |
15851 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
15852 | case BFD_RELOC_MICROMIPS_HIGHER: | |
15853 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
15854 | case BFD_RELOC_MICROMIPS_JALR: | |
15855 | case BFD_RELOC_MICROMIPS_HI16: | |
15856 | case BFD_RELOC_MICROMIPS_HI16_S: | |
b886a2ab | 15857 | case BFD_RELOC_MICROMIPS_LO16: |
df58fc94 RS |
15858 | case BFD_RELOC_MICROMIPS_GPREL16: |
15859 | case BFD_RELOC_MICROMIPS_LITERAL: | |
15860 | case BFD_RELOC_MICROMIPS_CALL16: | |
15861 | case BFD_RELOC_MICROMIPS_GOT16: | |
15862 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
15863 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
15864 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
15865 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
067ec077 | 15866 | case BFD_RELOC_MIPS_EH: |
b886a2ab RS |
15867 | if (fixP->fx_done) |
15868 | { | |
15869 | offsetT value; | |
15870 | ||
15871 | if (calculate_reloc (fixP->fx_r_type, *valP, &value)) | |
15872 | { | |
15873 | insn = read_reloc_insn (buf, fixP->fx_r_type); | |
15874 | if (mips16_reloc_p (fixP->fx_r_type)) | |
15875 | insn |= mips16_immed_extend (value, 16); | |
15876 | else | |
15877 | insn |= (value & 0xffff); | |
15878 | write_reloc_insn (buf, fixP->fx_r_type, insn); | |
15879 | } | |
15880 | else | |
15881 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
1661c76c | 15882 | _("unsupported constant in relocation")); |
b886a2ab | 15883 | } |
252b5132 RH |
15884 | break; |
15885 | ||
252b5132 RH |
15886 | case BFD_RELOC_64: |
15887 | /* This is handled like BFD_RELOC_32, but we output a sign | |
15888 | extended value if we are only 32 bits. */ | |
3e722fb5 | 15889 | if (fixP->fx_done) |
252b5132 RH |
15890 | { |
15891 | if (8 <= sizeof (valueT)) | |
4d68580a | 15892 | md_number_to_chars (buf, *valP, 8); |
252b5132 RH |
15893 | else |
15894 | { | |
a7ebbfdf | 15895 | valueT hiv; |
252b5132 | 15896 | |
a7ebbfdf | 15897 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
15898 | hiv = 0xffffffff; |
15899 | else | |
15900 | hiv = 0; | |
4d68580a RS |
15901 | md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4); |
15902 | md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4); | |
252b5132 RH |
15903 | } |
15904 | } | |
15905 | break; | |
15906 | ||
056350c6 | 15907 | case BFD_RELOC_RVA: |
252b5132 | 15908 | case BFD_RELOC_32: |
b47468a6 | 15909 | case BFD_RELOC_32_PCREL: |
252b5132 | 15910 | case BFD_RELOC_16: |
d56a8dda | 15911 | case BFD_RELOC_8: |
252b5132 | 15912 | /* If we are deleting this reloc entry, we must fill in the |
54f4ddb3 TS |
15913 | value now. This can happen if we have a .word which is not |
15914 | resolved when it appears but is later defined. */ | |
252b5132 | 15915 | if (fixP->fx_done) |
4d68580a | 15916 | md_number_to_chars (buf, *valP, fixP->fx_size); |
252b5132 RH |
15917 | break; |
15918 | ||
7361da2c | 15919 | case BFD_RELOC_MIPS_21_PCREL_S2: |
9d862524 | 15920 | fix_validate_branch (fixP, *valP); |
41947d9e MR |
15921 | if (!fixP->fx_done) |
15922 | break; | |
15923 | ||
15924 | if (*valP + 0x400000 <= 0x7fffff) | |
15925 | { | |
15926 | insn = read_insn (buf); | |
15927 | insn |= (*valP >> 2) & 0x1fffff; | |
15928 | write_insn (buf, insn); | |
15929 | } | |
15930 | else | |
15931 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15932 | _("branch out of range")); | |
15933 | break; | |
15934 | ||
7361da2c | 15935 | case BFD_RELOC_MIPS_26_PCREL_S2: |
9d862524 | 15936 | fix_validate_branch (fixP, *valP); |
41947d9e MR |
15937 | if (!fixP->fx_done) |
15938 | break; | |
7361da2c | 15939 | |
41947d9e MR |
15940 | if (*valP + 0x8000000 <= 0xfffffff) |
15941 | { | |
15942 | insn = read_insn (buf); | |
15943 | insn |= (*valP >> 2) & 0x3ffffff; | |
15944 | write_insn (buf, insn); | |
15945 | } | |
15946 | else | |
15947 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15948 | _("branch out of range")); | |
7361da2c AB |
15949 | break; |
15950 | ||
15951 | case BFD_RELOC_MIPS_18_PCREL_S3: | |
717ba204 | 15952 | if (fixP->fx_addsy && (S_GET_VALUE (fixP->fx_addsy) & 0x7) != 0) |
7361da2c | 15953 | as_bad_where (fixP->fx_file, fixP->fx_line, |
0866e94c MF |
15954 | _("PC-relative access using misaligned symbol (%lx)"), |
15955 | (long) S_GET_VALUE (fixP->fx_addsy)); | |
15956 | if ((fixP->fx_offset & 0x7) != 0) | |
15957 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15958 | _("PC-relative access using misaligned offset (%lx)"), | |
15959 | (long) fixP->fx_offset); | |
41947d9e MR |
15960 | if (!fixP->fx_done) |
15961 | break; | |
7361da2c | 15962 | |
41947d9e MR |
15963 | if (*valP + 0x100000 <= 0x1fffff) |
15964 | { | |
15965 | insn = read_insn (buf); | |
15966 | insn |= (*valP >> 3) & 0x3ffff; | |
15967 | write_insn (buf, insn); | |
15968 | } | |
15969 | else | |
15970 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15971 | _("PC-relative access out of range")); | |
7361da2c AB |
15972 | break; |
15973 | ||
15974 | case BFD_RELOC_MIPS_19_PCREL_S2: | |
15975 | if ((*valP & 0x3) != 0) | |
15976 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15977 | _("PC-relative access to misaligned address (%lx)"), | |
717ba204 | 15978 | (long) *valP); |
41947d9e MR |
15979 | if (!fixP->fx_done) |
15980 | break; | |
7361da2c | 15981 | |
41947d9e MR |
15982 | if (*valP + 0x100000 <= 0x1fffff) |
15983 | { | |
15984 | insn = read_insn (buf); | |
15985 | insn |= (*valP >> 2) & 0x7ffff; | |
15986 | write_insn (buf, insn); | |
15987 | } | |
15988 | else | |
15989 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15990 | _("PC-relative access out of range")); | |
7361da2c AB |
15991 | break; |
15992 | ||
252b5132 | 15993 | case BFD_RELOC_16_PCREL_S2: |
9d862524 | 15994 | fix_validate_branch (fixP, *valP); |
cb56d3d3 | 15995 | |
54f4ddb3 TS |
15996 | /* We need to save the bits in the instruction since fixup_segment() |
15997 | might be deleting the relocation entry (i.e., a branch within | |
15998 | the current segment). */ | |
a7ebbfdf | 15999 | if (! fixP->fx_done) |
bb2d6cd7 | 16000 | break; |
252b5132 | 16001 | |
54f4ddb3 | 16002 | /* Update old instruction data. */ |
4d68580a | 16003 | insn = read_insn (buf); |
252b5132 | 16004 | |
a7ebbfdf TS |
16005 | if (*valP + 0x20000 <= 0x3ffff) |
16006 | { | |
16007 | insn |= (*valP >> 2) & 0xffff; | |
4d68580a | 16008 | write_insn (buf, insn); |
a7ebbfdf | 16009 | } |
ce8ad872 | 16010 | else if (fixP->fx_tcbit2 |
a7ebbfdf TS |
16011 | && fixP->fx_done |
16012 | && fixP->fx_frag->fr_address >= text_section->vma | |
16013 | && (fixP->fx_frag->fr_address | |
587aac4e | 16014 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
16015 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
16016 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
16017 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
16018 | { |
16019 | /* The branch offset is too large. If this is an | |
16020 | unconditional branch, and we are not generating PIC code, | |
16021 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
16022 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
16023 | insn = 0x0c000000; /* jal */ | |
252b5132 | 16024 | else |
a7ebbfdf TS |
16025 | insn = 0x08000000; /* j */ |
16026 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
16027 | fixP->fx_done = 0; | |
16028 | fixP->fx_addsy = section_symbol (text_section); | |
16029 | *valP += md_pcrel_from (fixP); | |
4d68580a | 16030 | write_insn (buf, insn); |
a7ebbfdf TS |
16031 | } |
16032 | else | |
16033 | { | |
16034 | /* If we got here, we have branch-relaxation disabled, | |
16035 | and there's nothing we can do to fix this instruction | |
16036 | without turning it into a longer sequence. */ | |
16037 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
1661c76c | 16038 | _("branch out of range")); |
252b5132 | 16039 | } |
252b5132 RH |
16040 | break; |
16041 | ||
c9775dde | 16042 | case BFD_RELOC_MIPS16_16_PCREL_S1: |
df58fc94 RS |
16043 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
16044 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
16045 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
96e9ba5f | 16046 | gas_assert (!fixP->fx_done); |
9d862524 MR |
16047 | if (fix_bad_cross_mode_branch_p (fixP)) |
16048 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
16049 | _("branch to a symbol in another ISA mode")); | |
16050 | else if (fixP->fx_addsy | |
16051 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) | |
16052 | && !bfd_is_abs_section (S_GET_SEGMENT (fixP->fx_addsy)) | |
16053 | && (fixP->fx_offset & 0x1) != 0) | |
16054 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
16055 | _("branch to misaligned address (0x%lx)"), | |
16056 | (long) (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset)); | |
16057 | else if (HAVE_IN_PLACE_ADDENDS && (fixP->fx_offset & 0x1) != 0) | |
16058 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
16059 | _("cannot encode misaligned addend " | |
16060 | "in the relocatable field (0x%lx)"), | |
16061 | (long) fixP->fx_offset); | |
df58fc94 RS |
16062 | break; |
16063 | ||
252b5132 RH |
16064 | case BFD_RELOC_VTABLE_INHERIT: |
16065 | fixP->fx_done = 0; | |
16066 | if (fixP->fx_addsy | |
16067 | && !S_IS_DEFINED (fixP->fx_addsy) | |
16068 | && !S_IS_WEAK (fixP->fx_addsy)) | |
16069 | S_SET_WEAK (fixP->fx_addsy); | |
16070 | break; | |
16071 | ||
2f0c68f2 | 16072 | case BFD_RELOC_NONE: |
252b5132 RH |
16073 | case BFD_RELOC_VTABLE_ENTRY: |
16074 | fixP->fx_done = 0; | |
16075 | break; | |
16076 | ||
16077 | default: | |
b37df7c4 | 16078 | abort (); |
252b5132 | 16079 | } |
a7ebbfdf TS |
16080 | |
16081 | /* Remember value for tc_gen_reloc. */ | |
16082 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
16083 | } |
16084 | ||
252b5132 | 16085 | static symbolS * |
17a2f251 | 16086 | get_symbol (void) |
252b5132 RH |
16087 | { |
16088 | int c; | |
16089 | char *name; | |
16090 | symbolS *p; | |
16091 | ||
d02603dc | 16092 | c = get_symbol_name (&name); |
252b5132 | 16093 | p = (symbolS *) symbol_find_or_make (name); |
d02603dc | 16094 | (void) restore_line_pointer (c); |
252b5132 RH |
16095 | return p; |
16096 | } | |
16097 | ||
742a56fe RS |
16098 | /* Align the current frag to a given power of two. If a particular |
16099 | fill byte should be used, FILL points to an integer that contains | |
16100 | that byte, otherwise FILL is null. | |
16101 | ||
462427c4 RS |
16102 | This function used to have the comment: |
16103 | ||
16104 | The MIPS assembler also automatically adjusts any preceding label. | |
16105 | ||
16106 | The implementation therefore applied the adjustment to a maximum of | |
16107 | one label. However, other label adjustments are applied to batches | |
16108 | of labels, and adjusting just one caused problems when new labels | |
16109 | were added for the sake of debugging or unwind information. | |
16110 | We therefore adjust all preceding labels (given as LABELS) instead. */ | |
252b5132 RH |
16111 | |
16112 | static void | |
462427c4 | 16113 | mips_align (int to, int *fill, struct insn_label_list *labels) |
252b5132 | 16114 | { |
7d10b47d | 16115 | mips_emit_delays (); |
df58fc94 | 16116 | mips_record_compressed_mode (); |
742a56fe RS |
16117 | if (fill == NULL && subseg_text_p (now_seg)) |
16118 | frag_align_code (to, 0); | |
16119 | else | |
16120 | frag_align (to, fill ? *fill : 0, 0); | |
252b5132 | 16121 | record_alignment (now_seg, to); |
462427c4 | 16122 | mips_move_labels (labels, FALSE); |
252b5132 RH |
16123 | } |
16124 | ||
16125 | /* Align to a given power of two. .align 0 turns off the automatic | |
16126 | alignment used by the data creating pseudo-ops. */ | |
16127 | ||
16128 | static void | |
17a2f251 | 16129 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 | 16130 | { |
742a56fe | 16131 | int temp, fill_value, *fill_ptr; |
49954fb4 | 16132 | long max_alignment = 28; |
252b5132 | 16133 | |
54f4ddb3 | 16134 | /* o Note that the assembler pulls down any immediately preceding label |
252b5132 | 16135 | to the aligned address. |
54f4ddb3 | 16136 | o It's not documented but auto alignment is reinstated by |
252b5132 | 16137 | a .align pseudo instruction. |
54f4ddb3 | 16138 | o Note also that after auto alignment is turned off the mips assembler |
252b5132 | 16139 | issues an error on attempt to assemble an improperly aligned data item. |
54f4ddb3 | 16140 | We don't. */ |
252b5132 RH |
16141 | |
16142 | temp = get_absolute_expression (); | |
16143 | if (temp > max_alignment) | |
1661c76c | 16144 | as_bad (_("alignment too large, %d assumed"), temp = max_alignment); |
252b5132 RH |
16145 | else if (temp < 0) |
16146 | { | |
1661c76c | 16147 | as_warn (_("alignment negative, 0 assumed")); |
252b5132 RH |
16148 | temp = 0; |
16149 | } | |
16150 | if (*input_line_pointer == ',') | |
16151 | { | |
f9419b05 | 16152 | ++input_line_pointer; |
742a56fe RS |
16153 | fill_value = get_absolute_expression (); |
16154 | fill_ptr = &fill_value; | |
252b5132 RH |
16155 | } |
16156 | else | |
742a56fe | 16157 | fill_ptr = 0; |
252b5132 RH |
16158 | if (temp) |
16159 | { | |
a8dbcb85 TS |
16160 | segment_info_type *si = seg_info (now_seg); |
16161 | struct insn_label_list *l = si->label_list; | |
54f4ddb3 | 16162 | /* Auto alignment should be switched on by next section change. */ |
252b5132 | 16163 | auto_align = 1; |
462427c4 | 16164 | mips_align (temp, fill_ptr, l); |
252b5132 RH |
16165 | } |
16166 | else | |
16167 | { | |
16168 | auto_align = 0; | |
16169 | } | |
16170 | ||
16171 | demand_empty_rest_of_line (); | |
16172 | } | |
16173 | ||
252b5132 | 16174 | static void |
17a2f251 | 16175 | s_change_sec (int sec) |
252b5132 RH |
16176 | { |
16177 | segT seg; | |
16178 | ||
252b5132 RH |
16179 | /* The ELF backend needs to know that we are changing sections, so |
16180 | that .previous works correctly. We could do something like check | |
b6ff326e | 16181 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
16182 | as it would not be appropriate to use it in the section changing |
16183 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
16184 | This should be cleaner, somehow. */ | |
f3ded42a | 16185 | obj_elf_section_change_hook (); |
252b5132 | 16186 | |
7d10b47d | 16187 | mips_emit_delays (); |
6a32d874 | 16188 | |
252b5132 RH |
16189 | switch (sec) |
16190 | { | |
16191 | case 't': | |
16192 | s_text (0); | |
16193 | break; | |
16194 | case 'd': | |
16195 | s_data (0); | |
16196 | break; | |
16197 | case 'b': | |
16198 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
16199 | demand_empty_rest_of_line (); | |
16200 | break; | |
16201 | ||
16202 | case 'r': | |
4d0d148d TS |
16203 | seg = subseg_new (RDATA_SECTION_NAME, |
16204 | (subsegT) get_absolute_expression ()); | |
f3ded42a RS |
16205 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
16206 | | SEC_READONLY | SEC_RELOC | |
16207 | | SEC_DATA)); | |
16208 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
16209 | record_alignment (seg, 4); | |
4d0d148d | 16210 | demand_empty_rest_of_line (); |
252b5132 RH |
16211 | break; |
16212 | ||
16213 | case 's': | |
4d0d148d | 16214 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
f3ded42a RS |
16215 | bfd_set_section_flags (stdoutput, seg, |
16216 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
16217 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
16218 | record_alignment (seg, 4); | |
4d0d148d TS |
16219 | demand_empty_rest_of_line (); |
16220 | break; | |
998b3c36 MR |
16221 | |
16222 | case 'B': | |
16223 | seg = subseg_new (".sbss", (subsegT) get_absolute_expression ()); | |
f3ded42a RS |
16224 | bfd_set_section_flags (stdoutput, seg, SEC_ALLOC); |
16225 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
16226 | record_alignment (seg, 4); | |
998b3c36 MR |
16227 | demand_empty_rest_of_line (); |
16228 | break; | |
252b5132 RH |
16229 | } |
16230 | ||
16231 | auto_align = 1; | |
16232 | } | |
b34976b6 | 16233 | |
cca86cc8 | 16234 | void |
17a2f251 | 16235 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 16236 | { |
d02603dc | 16237 | char *saved_ilp; |
cca86cc8 | 16238 | char *section_name; |
d02603dc | 16239 | char c, endc; |
684022ea | 16240 | char next_c = 0; |
cca86cc8 SC |
16241 | int section_type; |
16242 | int section_flag; | |
16243 | int section_entry_size; | |
16244 | int section_alignment; | |
b34976b6 | 16245 | |
d02603dc NC |
16246 | saved_ilp = input_line_pointer; |
16247 | endc = get_symbol_name (§ion_name); | |
16248 | c = (endc == '"' ? input_line_pointer[1] : endc); | |
a816d1ed | 16249 | if (c) |
d02603dc | 16250 | next_c = input_line_pointer [(endc == '"' ? 2 : 1)]; |
cca86cc8 | 16251 | |
4cf0dd0d TS |
16252 | /* Do we have .section Name<,"flags">? */ |
16253 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 16254 | { |
d02603dc NC |
16255 | /* Just after name is now '\0'. */ |
16256 | (void) restore_line_pointer (endc); | |
16257 | input_line_pointer = saved_ilp; | |
cca86cc8 SC |
16258 | obj_elf_section (ignore); |
16259 | return; | |
16260 | } | |
d02603dc NC |
16261 | |
16262 | section_name = xstrdup (section_name); | |
16263 | c = restore_line_pointer (endc); | |
16264 | ||
cca86cc8 SC |
16265 | input_line_pointer++; |
16266 | ||
16267 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
16268 | if (c == ',') | |
16269 | section_type = get_absolute_expression (); | |
16270 | else | |
16271 | section_type = 0; | |
d02603dc | 16272 | |
cca86cc8 SC |
16273 | if (*input_line_pointer++ == ',') |
16274 | section_flag = get_absolute_expression (); | |
16275 | else | |
16276 | section_flag = 0; | |
d02603dc | 16277 | |
cca86cc8 SC |
16278 | if (*input_line_pointer++ == ',') |
16279 | section_entry_size = get_absolute_expression (); | |
16280 | else | |
16281 | section_entry_size = 0; | |
d02603dc | 16282 | |
cca86cc8 SC |
16283 | if (*input_line_pointer++ == ',') |
16284 | section_alignment = get_absolute_expression (); | |
16285 | else | |
16286 | section_alignment = 0; | |
d02603dc | 16287 | |
87975d2a AM |
16288 | /* FIXME: really ignore? */ |
16289 | (void) section_alignment; | |
cca86cc8 | 16290 | |
8ab8a5c8 RS |
16291 | /* When using the generic form of .section (as implemented by obj-elf.c), |
16292 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
16293 | traditionally had to fall back on the more common @progbits instead. | |
16294 | ||
16295 | There's nothing really harmful in this, since bfd will correct | |
16296 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
708587a4 | 16297 | means that, for backwards compatibility, the special_section entries |
8ab8a5c8 RS |
16298 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. |
16299 | ||
16300 | Even so, we shouldn't force users of the MIPS .section syntax to | |
16301 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
16302 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
16303 | generic type-checking code. */ | |
16304 | if (section_type == SHT_MIPS_DWARF) | |
16305 | section_type = SHT_PROGBITS; | |
16306 | ||
a91e1603 | 16307 | obj_elf_change_section (section_name, section_type, 0, section_flag, |
cca86cc8 | 16308 | section_entry_size, 0, 0, 0); |
a816d1ed AO |
16309 | |
16310 | if (now_seg->name != section_name) | |
16311 | free (section_name); | |
cca86cc8 | 16312 | } |
252b5132 RH |
16313 | |
16314 | void | |
17a2f251 | 16315 | mips_enable_auto_align (void) |
252b5132 RH |
16316 | { |
16317 | auto_align = 1; | |
16318 | } | |
16319 | ||
16320 | static void | |
17a2f251 | 16321 | s_cons (int log_size) |
252b5132 | 16322 | { |
a8dbcb85 TS |
16323 | segment_info_type *si = seg_info (now_seg); |
16324 | struct insn_label_list *l = si->label_list; | |
252b5132 | 16325 | |
7d10b47d | 16326 | mips_emit_delays (); |
252b5132 | 16327 | if (log_size > 0 && auto_align) |
462427c4 | 16328 | mips_align (log_size, 0, l); |
252b5132 | 16329 | cons (1 << log_size); |
a1facbec | 16330 | mips_clear_insn_labels (); |
252b5132 RH |
16331 | } |
16332 | ||
16333 | static void | |
17a2f251 | 16334 | s_float_cons (int type) |
252b5132 | 16335 | { |
a8dbcb85 TS |
16336 | segment_info_type *si = seg_info (now_seg); |
16337 | struct insn_label_list *l = si->label_list; | |
252b5132 | 16338 | |
7d10b47d | 16339 | mips_emit_delays (); |
252b5132 RH |
16340 | |
16341 | if (auto_align) | |
49309057 ILT |
16342 | { |
16343 | if (type == 'd') | |
462427c4 | 16344 | mips_align (3, 0, l); |
49309057 | 16345 | else |
462427c4 | 16346 | mips_align (2, 0, l); |
49309057 | 16347 | } |
252b5132 | 16348 | |
252b5132 | 16349 | float_cons (type); |
a1facbec | 16350 | mips_clear_insn_labels (); |
252b5132 RH |
16351 | } |
16352 | ||
16353 | /* Handle .globl. We need to override it because on Irix 5 you are | |
16354 | permitted to say | |
16355 | .globl foo .text | |
16356 | where foo is an undefined symbol, to mean that foo should be | |
16357 | considered to be the address of a function. */ | |
16358 | ||
16359 | static void | |
17a2f251 | 16360 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16361 | { |
16362 | char *name; | |
16363 | int c; | |
16364 | symbolS *symbolP; | |
16365 | flagword flag; | |
16366 | ||
8a06b769 | 16367 | do |
252b5132 | 16368 | { |
d02603dc | 16369 | c = get_symbol_name (&name); |
8a06b769 TS |
16370 | symbolP = symbol_find_or_make (name); |
16371 | S_SET_EXTERNAL (symbolP); | |
16372 | ||
252b5132 | 16373 | *input_line_pointer = c; |
d02603dc | 16374 | SKIP_WHITESPACE_AFTER_NAME (); |
252b5132 | 16375 | |
8a06b769 TS |
16376 | /* On Irix 5, every global symbol that is not explicitly labelled as |
16377 | being a function is apparently labelled as being an object. */ | |
16378 | flag = BSF_OBJECT; | |
252b5132 | 16379 | |
8a06b769 TS |
16380 | if (!is_end_of_line[(unsigned char) *input_line_pointer] |
16381 | && (*input_line_pointer != ',')) | |
16382 | { | |
16383 | char *secname; | |
16384 | asection *sec; | |
16385 | ||
d02603dc | 16386 | c = get_symbol_name (&secname); |
8a06b769 TS |
16387 | sec = bfd_get_section_by_name (stdoutput, secname); |
16388 | if (sec == NULL) | |
16389 | as_bad (_("%s: no such section"), secname); | |
d02603dc | 16390 | (void) restore_line_pointer (c); |
8a06b769 TS |
16391 | |
16392 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
16393 | flag = BSF_FUNCTION; | |
16394 | } | |
16395 | ||
16396 | symbol_get_bfdsym (symbolP)->flags |= flag; | |
16397 | ||
16398 | c = *input_line_pointer; | |
16399 | if (c == ',') | |
16400 | { | |
16401 | input_line_pointer++; | |
16402 | SKIP_WHITESPACE (); | |
16403 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
16404 | c = '\n'; | |
16405 | } | |
16406 | } | |
16407 | while (c == ','); | |
252b5132 | 16408 | |
252b5132 RH |
16409 | demand_empty_rest_of_line (); |
16410 | } | |
16411 | ||
16412 | static void | |
17a2f251 | 16413 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16414 | { |
16415 | char *opt; | |
16416 | char c; | |
16417 | ||
d02603dc | 16418 | c = get_symbol_name (&opt); |
252b5132 RH |
16419 | |
16420 | if (*opt == 'O') | |
16421 | { | |
16422 | /* FIXME: What does this mean? */ | |
16423 | } | |
41a1578e | 16424 | else if (strncmp (opt, "pic", 3) == 0 && ISDIGIT (opt[3]) && opt[4] == '\0') |
252b5132 RH |
16425 | { |
16426 | int i; | |
16427 | ||
16428 | i = atoi (opt + 3); | |
668c5ebc MR |
16429 | if (i != 0 && i != 2) |
16430 | as_bad (_(".option pic%d not supported"), i); | |
16431 | else if (mips_pic == VXWORKS_PIC) | |
16432 | as_bad (_(".option pic%d not supported in VxWorks PIC mode"), i); | |
16433 | else if (i == 0) | |
252b5132 RH |
16434 | mips_pic = NO_PIC; |
16435 | else if (i == 2) | |
143d77c5 | 16436 | { |
8b828383 | 16437 | mips_pic = SVR4_PIC; |
143d77c5 EC |
16438 | mips_abicalls = TRUE; |
16439 | } | |
252b5132 | 16440 | |
4d0d148d | 16441 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
16442 | { |
16443 | if (g_switch_seen && g_switch_value != 0) | |
16444 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
16445 | g_switch_value = 0; | |
16446 | bfd_set_gp_size (stdoutput, 0); | |
16447 | } | |
16448 | } | |
16449 | else | |
1661c76c | 16450 | as_warn (_("unrecognized option \"%s\""), opt); |
252b5132 | 16451 | |
d02603dc | 16452 | (void) restore_line_pointer (c); |
252b5132 RH |
16453 | demand_empty_rest_of_line (); |
16454 | } | |
16455 | ||
16456 | /* This structure is used to hold a stack of .set values. */ | |
16457 | ||
e972090a NC |
16458 | struct mips_option_stack |
16459 | { | |
252b5132 RH |
16460 | struct mips_option_stack *next; |
16461 | struct mips_set_options options; | |
16462 | }; | |
16463 | ||
16464 | static struct mips_option_stack *mips_opts_stack; | |
16465 | ||
22522f88 MR |
16466 | /* Return status for .set/.module option handling. */ |
16467 | ||
16468 | enum code_option_type | |
16469 | { | |
16470 | /* Unrecognized option. */ | |
16471 | OPTION_TYPE_BAD = -1, | |
16472 | ||
16473 | /* Ordinary option. */ | |
16474 | OPTION_TYPE_NORMAL, | |
16475 | ||
16476 | /* ISA changing option. */ | |
16477 | OPTION_TYPE_ISA | |
16478 | }; | |
16479 | ||
16480 | /* Handle common .set/.module options. Return status indicating option | |
16481 | type. */ | |
16482 | ||
16483 | static enum code_option_type | |
919731af | 16484 | parse_code_option (char * name) |
252b5132 | 16485 | { |
22522f88 | 16486 | bfd_boolean isa_set = FALSE; |
c6278170 | 16487 | const struct mips_ase *ase; |
22522f88 | 16488 | |
919731af | 16489 | if (strncmp (name, "at=", 3) == 0) |
741fe287 MR |
16490 | { |
16491 | char *s = name + 3; | |
16492 | ||
16493 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at)) | |
1661c76c | 16494 | as_bad (_("unrecognized register name `%s'"), s); |
741fe287 | 16495 | } |
252b5132 | 16496 | else if (strcmp (name, "at") == 0) |
919731af | 16497 | mips_opts.at = ATREG; |
252b5132 | 16498 | else if (strcmp (name, "noat") == 0) |
919731af | 16499 | mips_opts.at = ZERO; |
252b5132 | 16500 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) |
919731af | 16501 | mips_opts.nomove = 0; |
252b5132 | 16502 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) |
919731af | 16503 | mips_opts.nomove = 1; |
252b5132 | 16504 | else if (strcmp (name, "bopt") == 0) |
919731af | 16505 | mips_opts.nobopt = 0; |
252b5132 | 16506 | else if (strcmp (name, "nobopt") == 0) |
919731af | 16507 | mips_opts.nobopt = 1; |
ad3fea08 | 16508 | else if (strcmp (name, "gp=32") == 0) |
bad1aba3 | 16509 | mips_opts.gp = 32; |
ad3fea08 | 16510 | else if (strcmp (name, "gp=64") == 0) |
919731af | 16511 | mips_opts.gp = 64; |
ad3fea08 | 16512 | else if (strcmp (name, "fp=32") == 0) |
0b35dfee | 16513 | mips_opts.fp = 32; |
351cdf24 MF |
16514 | else if (strcmp (name, "fp=xx") == 0) |
16515 | mips_opts.fp = 0; | |
ad3fea08 | 16516 | else if (strcmp (name, "fp=64") == 0) |
919731af | 16517 | mips_opts.fp = 64; |
037b32b9 AN |
16518 | else if (strcmp (name, "softfloat") == 0) |
16519 | mips_opts.soft_float = 1; | |
16520 | else if (strcmp (name, "hardfloat") == 0) | |
16521 | mips_opts.soft_float = 0; | |
16522 | else if (strcmp (name, "singlefloat") == 0) | |
16523 | mips_opts.single_float = 1; | |
16524 | else if (strcmp (name, "doublefloat") == 0) | |
16525 | mips_opts.single_float = 0; | |
351cdf24 MF |
16526 | else if (strcmp (name, "nooddspreg") == 0) |
16527 | mips_opts.oddspreg = 0; | |
16528 | else if (strcmp (name, "oddspreg") == 0) | |
16529 | mips_opts.oddspreg = 1; | |
252b5132 RH |
16530 | else if (strcmp (name, "mips16") == 0 |
16531 | || strcmp (name, "MIPS-16") == 0) | |
919731af | 16532 | mips_opts.mips16 = 1; |
252b5132 RH |
16533 | else if (strcmp (name, "nomips16") == 0 |
16534 | || strcmp (name, "noMIPS-16") == 0) | |
16535 | mips_opts.mips16 = 0; | |
df58fc94 | 16536 | else if (strcmp (name, "micromips") == 0) |
919731af | 16537 | mips_opts.micromips = 1; |
df58fc94 RS |
16538 | else if (strcmp (name, "nomicromips") == 0) |
16539 | mips_opts.micromips = 0; | |
c6278170 RS |
16540 | else if (name[0] == 'n' |
16541 | && name[1] == 'o' | |
16542 | && (ase = mips_lookup_ase (name + 2))) | |
919731af | 16543 | mips_set_ase (ase, &mips_opts, FALSE); |
c6278170 | 16544 | else if ((ase = mips_lookup_ase (name))) |
919731af | 16545 | mips_set_ase (ase, &mips_opts, TRUE); |
1a2c1fad | 16546 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 16547 | { |
1a2c1fad CD |
16548 | /* Permit the user to change the ISA and architecture on the fly. |
16549 | Needless to say, misuse can cause serious problems. */ | |
919731af | 16550 | if (strncmp (name, "arch=", 5) == 0) |
1a2c1fad CD |
16551 | { |
16552 | const struct mips_cpu_info *p; | |
16553 | ||
919731af | 16554 | p = mips_parse_cpu ("internal use", name + 5); |
1a2c1fad CD |
16555 | if (!p) |
16556 | as_bad (_("unknown architecture %s"), name + 5); | |
16557 | else | |
16558 | { | |
16559 | mips_opts.arch = p->cpu; | |
16560 | mips_opts.isa = p->isa; | |
22522f88 | 16561 | isa_set = TRUE; |
1a2c1fad CD |
16562 | } |
16563 | } | |
81a21e38 TS |
16564 | else if (strncmp (name, "mips", 4) == 0) |
16565 | { | |
16566 | const struct mips_cpu_info *p; | |
16567 | ||
919731af | 16568 | p = mips_parse_cpu ("internal use", name); |
81a21e38 TS |
16569 | if (!p) |
16570 | as_bad (_("unknown ISA level %s"), name + 4); | |
16571 | else | |
16572 | { | |
16573 | mips_opts.arch = p->cpu; | |
16574 | mips_opts.isa = p->isa; | |
22522f88 | 16575 | isa_set = TRUE; |
81a21e38 TS |
16576 | } |
16577 | } | |
af7ee8bf | 16578 | else |
81a21e38 | 16579 | as_bad (_("unknown ISA or architecture %s"), name); |
252b5132 RH |
16580 | } |
16581 | else if (strcmp (name, "autoextend") == 0) | |
16582 | mips_opts.noautoextend = 0; | |
16583 | else if (strcmp (name, "noautoextend") == 0) | |
16584 | mips_opts.noautoextend = 1; | |
833794fc MR |
16585 | else if (strcmp (name, "insn32") == 0) |
16586 | mips_opts.insn32 = TRUE; | |
16587 | else if (strcmp (name, "noinsn32") == 0) | |
16588 | mips_opts.insn32 = FALSE; | |
919731af | 16589 | else if (strcmp (name, "sym32") == 0) |
16590 | mips_opts.sym32 = TRUE; | |
16591 | else if (strcmp (name, "nosym32") == 0) | |
16592 | mips_opts.sym32 = FALSE; | |
16593 | else | |
22522f88 MR |
16594 | return OPTION_TYPE_BAD; |
16595 | ||
16596 | return isa_set ? OPTION_TYPE_ISA : OPTION_TYPE_NORMAL; | |
919731af | 16597 | } |
16598 | ||
16599 | /* Handle the .set pseudo-op. */ | |
16600 | ||
16601 | static void | |
16602 | s_mipsset (int x ATTRIBUTE_UNUSED) | |
16603 | { | |
22522f88 | 16604 | enum code_option_type type = OPTION_TYPE_NORMAL; |
919731af | 16605 | char *name = input_line_pointer, ch; |
919731af | 16606 | |
16607 | file_mips_check_options (); | |
16608 | ||
16609 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
16610 | ++input_line_pointer; | |
16611 | ch = *input_line_pointer; | |
16612 | *input_line_pointer = '\0'; | |
16613 | ||
16614 | if (strchr (name, ',')) | |
16615 | { | |
16616 | /* Generic ".set" directive; use the generic handler. */ | |
16617 | *input_line_pointer = ch; | |
16618 | input_line_pointer = name; | |
16619 | s_set (0); | |
16620 | return; | |
16621 | } | |
16622 | ||
16623 | if (strcmp (name, "reorder") == 0) | |
16624 | { | |
16625 | if (mips_opts.noreorder) | |
16626 | end_noreorder (); | |
16627 | } | |
16628 | else if (strcmp (name, "noreorder") == 0) | |
16629 | { | |
16630 | if (!mips_opts.noreorder) | |
16631 | start_noreorder (); | |
16632 | } | |
16633 | else if (strcmp (name, "macro") == 0) | |
16634 | mips_opts.warn_about_macros = 0; | |
16635 | else if (strcmp (name, "nomacro") == 0) | |
16636 | { | |
16637 | if (mips_opts.noreorder == 0) | |
16638 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
16639 | mips_opts.warn_about_macros = 1; | |
16640 | } | |
16641 | else if (strcmp (name, "gp=default") == 0) | |
16642 | mips_opts.gp = file_mips_opts.gp; | |
16643 | else if (strcmp (name, "fp=default") == 0) | |
16644 | mips_opts.fp = file_mips_opts.fp; | |
16645 | else if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) | |
16646 | { | |
16647 | mips_opts.isa = file_mips_opts.isa; | |
16648 | mips_opts.arch = file_mips_opts.arch; | |
16649 | mips_opts.gp = file_mips_opts.gp; | |
16650 | mips_opts.fp = file_mips_opts.fp; | |
16651 | } | |
252b5132 RH |
16652 | else if (strcmp (name, "push") == 0) |
16653 | { | |
16654 | struct mips_option_stack *s; | |
16655 | ||
325801bd | 16656 | s = XNEW (struct mips_option_stack); |
252b5132 RH |
16657 | s->next = mips_opts_stack; |
16658 | s->options = mips_opts; | |
16659 | mips_opts_stack = s; | |
16660 | } | |
16661 | else if (strcmp (name, "pop") == 0) | |
16662 | { | |
16663 | struct mips_option_stack *s; | |
16664 | ||
16665 | s = mips_opts_stack; | |
16666 | if (s == NULL) | |
16667 | as_bad (_(".set pop with no .set push")); | |
16668 | else | |
16669 | { | |
16670 | /* If we're changing the reorder mode we need to handle | |
16671 | delay slots correctly. */ | |
16672 | if (s->options.noreorder && ! mips_opts.noreorder) | |
7d10b47d | 16673 | start_noreorder (); |
252b5132 | 16674 | else if (! s->options.noreorder && mips_opts.noreorder) |
7d10b47d | 16675 | end_noreorder (); |
252b5132 RH |
16676 | |
16677 | mips_opts = s->options; | |
16678 | mips_opts_stack = s->next; | |
16679 | free (s); | |
16680 | } | |
16681 | } | |
22522f88 MR |
16682 | else |
16683 | { | |
16684 | type = parse_code_option (name); | |
16685 | if (type == OPTION_TYPE_BAD) | |
16686 | as_warn (_("tried to set unrecognized symbol: %s\n"), name); | |
16687 | } | |
919731af | 16688 | |
16689 | /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp | |
16690 | registers based on what is supported by the arch/cpu. */ | |
22522f88 | 16691 | if (type == OPTION_TYPE_ISA) |
e6559e01 | 16692 | { |
919731af | 16693 | switch (mips_opts.isa) |
16694 | { | |
16695 | case 0: | |
16696 | break; | |
16697 | case ISA_MIPS1: | |
351cdf24 MF |
16698 | /* MIPS I cannot support FPXX. */ |
16699 | mips_opts.fp = 32; | |
16700 | /* fall-through. */ | |
919731af | 16701 | case ISA_MIPS2: |
16702 | case ISA_MIPS32: | |
16703 | case ISA_MIPS32R2: | |
16704 | case ISA_MIPS32R3: | |
16705 | case ISA_MIPS32R5: | |
16706 | mips_opts.gp = 32; | |
351cdf24 MF |
16707 | if (mips_opts.fp != 0) |
16708 | mips_opts.fp = 32; | |
919731af | 16709 | break; |
7361da2c AB |
16710 | case ISA_MIPS32R6: |
16711 | mips_opts.gp = 32; | |
16712 | mips_opts.fp = 64; | |
16713 | break; | |
919731af | 16714 | case ISA_MIPS3: |
16715 | case ISA_MIPS4: | |
16716 | case ISA_MIPS5: | |
16717 | case ISA_MIPS64: | |
16718 | case ISA_MIPS64R2: | |
16719 | case ISA_MIPS64R3: | |
16720 | case ISA_MIPS64R5: | |
7361da2c | 16721 | case ISA_MIPS64R6: |
919731af | 16722 | mips_opts.gp = 64; |
351cdf24 MF |
16723 | if (mips_opts.fp != 0) |
16724 | { | |
16725 | if (mips_opts.arch == CPU_R5900) | |
16726 | mips_opts.fp = 32; | |
16727 | else | |
16728 | mips_opts.fp = 64; | |
16729 | } | |
919731af | 16730 | break; |
16731 | default: | |
16732 | as_bad (_("unknown ISA level %s"), name + 4); | |
16733 | break; | |
16734 | } | |
e6559e01 | 16735 | } |
919731af | 16736 | |
16737 | mips_check_options (&mips_opts, FALSE); | |
16738 | ||
16739 | mips_check_isa_supports_ases (); | |
16740 | *input_line_pointer = ch; | |
16741 | demand_empty_rest_of_line (); | |
16742 | } | |
16743 | ||
16744 | /* Handle the .module pseudo-op. */ | |
16745 | ||
16746 | static void | |
16747 | s_module (int ignore ATTRIBUTE_UNUSED) | |
16748 | { | |
16749 | char *name = input_line_pointer, ch; | |
16750 | ||
16751 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
16752 | ++input_line_pointer; | |
16753 | ch = *input_line_pointer; | |
16754 | *input_line_pointer = '\0'; | |
16755 | ||
16756 | if (!file_mips_opts_checked) | |
252b5132 | 16757 | { |
22522f88 | 16758 | if (parse_code_option (name) == OPTION_TYPE_BAD) |
919731af | 16759 | as_bad (_(".module used with unrecognized symbol: %s\n"), name); |
16760 | ||
16761 | /* Update module level settings from mips_opts. */ | |
16762 | file_mips_opts = mips_opts; | |
252b5132 | 16763 | } |
919731af | 16764 | else |
16765 | as_bad (_(".module is not permitted after generating code")); | |
16766 | ||
252b5132 RH |
16767 | *input_line_pointer = ch; |
16768 | demand_empty_rest_of_line (); | |
16769 | } | |
16770 | ||
16771 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
16772 | .option pic2. It means to generate SVR4 PIC calls. */ | |
16773 | ||
16774 | static void | |
17a2f251 | 16775 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16776 | { |
16777 | mips_pic = SVR4_PIC; | |
143d77c5 | 16778 | mips_abicalls = TRUE; |
4d0d148d TS |
16779 | |
16780 | if (g_switch_seen && g_switch_value != 0) | |
16781 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
16782 | g_switch_value = 0; | |
16783 | ||
252b5132 RH |
16784 | bfd_set_gp_size (stdoutput, 0); |
16785 | demand_empty_rest_of_line (); | |
16786 | } | |
16787 | ||
16788 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
16789 | PIC code. It sets the $gp register for the function based on the | |
16790 | function address, which is in the register named in the argument. | |
16791 | This uses a relocation against _gp_disp, which is handled specially | |
16792 | by the linker. The result is: | |
16793 | lui $gp,%hi(_gp_disp) | |
16794 | addiu $gp,$gp,%lo(_gp_disp) | |
16795 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
16796 | The .cpload argument is normally $25 == $t9. |
16797 | ||
16798 | The -mno-shared option changes this to: | |
bbe506e8 TS |
16799 | lui $gp,%hi(__gnu_local_gp) |
16800 | addiu $gp,$gp,%lo(__gnu_local_gp) | |
aa6975fb ILT |
16801 | and the argument is ignored. This saves an instruction, but the |
16802 | resulting code is not position independent; it uses an absolute | |
bbe506e8 TS |
16803 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
16804 | can go into an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
16805 | |
16806 | static void | |
17a2f251 | 16807 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16808 | { |
16809 | expressionS ex; | |
aa6975fb ILT |
16810 | int reg; |
16811 | int in_shared; | |
252b5132 | 16812 | |
919731af | 16813 | file_mips_check_options (); |
16814 | ||
6478892d TS |
16815 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
16816 | .cpload is ignored. */ | |
16817 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
16818 | { |
16819 | s_ignore (0); | |
16820 | return; | |
16821 | } | |
16822 | ||
a276b80c MR |
16823 | if (mips_opts.mips16) |
16824 | { | |
16825 | as_bad (_("%s not supported in MIPS16 mode"), ".cpload"); | |
16826 | ignore_rest_of_line (); | |
16827 | return; | |
16828 | } | |
16829 | ||
d3ecfc59 | 16830 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
16831 | if (mips_opts.noreorder == 0) |
16832 | as_warn (_(".cpload not in noreorder section")); | |
16833 | ||
aa6975fb ILT |
16834 | reg = tc_get_register (0); |
16835 | ||
16836 | /* If we need to produce a 64-bit address, we are better off using | |
16837 | the default instruction sequence. */ | |
aed1a261 | 16838 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
aa6975fb | 16839 | |
252b5132 | 16840 | ex.X_op = O_symbol; |
bbe506e8 TS |
16841 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
16842 | "__gnu_local_gp"); | |
252b5132 RH |
16843 | ex.X_op_symbol = NULL; |
16844 | ex.X_add_number = 0; | |
16845 | ||
16846 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 16847 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 16848 | |
8a75745d MR |
16849 | mips_mark_labels (); |
16850 | mips_assembling_insn = TRUE; | |
16851 | ||
584892a6 | 16852 | macro_start (); |
67c0d1eb RS |
16853 | macro_build_lui (&ex, mips_gp_register); |
16854 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 16855 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
16856 | if (in_shared) |
16857 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
16858 | mips_gp_register, reg); | |
584892a6 | 16859 | macro_end (); |
252b5132 | 16860 | |
8a75745d | 16861 | mips_assembling_insn = FALSE; |
252b5132 RH |
16862 | demand_empty_rest_of_line (); |
16863 | } | |
16864 | ||
6478892d TS |
16865 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
16866 | .cpsetup $reg1, offset|$reg2, label | |
16867 | ||
16868 | If offset is given, this results in: | |
16869 | sd $gp, offset($sp) | |
956cd1d6 | 16870 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
16871 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
16872 | daddu $gp, $gp, $reg1 | |
6478892d TS |
16873 | |
16874 | If $reg2 is given, this results in: | |
40fc1451 | 16875 | or $reg2, $gp, $0 |
956cd1d6 | 16876 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
16877 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
16878 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
16879 | $reg1 is normally $25 == $t9. |
16880 | ||
16881 | The -mno-shared option replaces the last three instructions with | |
16882 | lui $gp,%hi(_gp) | |
54f4ddb3 | 16883 | addiu $gp,$gp,%lo(_gp) */ |
aa6975fb | 16884 | |
6478892d | 16885 | static void |
17a2f251 | 16886 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16887 | { |
16888 | expressionS ex_off; | |
16889 | expressionS ex_sym; | |
16890 | int reg1; | |
6478892d | 16891 | |
919731af | 16892 | file_mips_check_options (); |
16893 | ||
8586fc66 | 16894 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
16895 | We also need NewABI support. */ |
16896 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16897 | { | |
16898 | s_ignore (0); | |
16899 | return; | |
16900 | } | |
16901 | ||
a276b80c MR |
16902 | if (mips_opts.mips16) |
16903 | { | |
16904 | as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup"); | |
16905 | ignore_rest_of_line (); | |
16906 | return; | |
16907 | } | |
16908 | ||
6478892d TS |
16909 | reg1 = tc_get_register (0); |
16910 | SKIP_WHITESPACE (); | |
16911 | if (*input_line_pointer != ',') | |
16912 | { | |
16913 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
16914 | return; | |
16915 | } | |
16916 | else | |
80245285 | 16917 | ++input_line_pointer; |
6478892d TS |
16918 | SKIP_WHITESPACE (); |
16919 | if (*input_line_pointer == '$') | |
80245285 TS |
16920 | { |
16921 | mips_cpreturn_register = tc_get_register (0); | |
16922 | mips_cpreturn_offset = -1; | |
16923 | } | |
6478892d | 16924 | else |
80245285 TS |
16925 | { |
16926 | mips_cpreturn_offset = get_absolute_expression (); | |
16927 | mips_cpreturn_register = -1; | |
16928 | } | |
6478892d TS |
16929 | SKIP_WHITESPACE (); |
16930 | if (*input_line_pointer != ',') | |
16931 | { | |
16932 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
16933 | return; | |
16934 | } | |
16935 | else | |
f9419b05 | 16936 | ++input_line_pointer; |
6478892d | 16937 | SKIP_WHITESPACE (); |
f21f8242 | 16938 | expression (&ex_sym); |
6478892d | 16939 | |
8a75745d MR |
16940 | mips_mark_labels (); |
16941 | mips_assembling_insn = TRUE; | |
16942 | ||
584892a6 | 16943 | macro_start (); |
6478892d TS |
16944 | if (mips_cpreturn_register == -1) |
16945 | { | |
16946 | ex_off.X_op = O_constant; | |
16947 | ex_off.X_add_symbol = NULL; | |
16948 | ex_off.X_op_symbol = NULL; | |
16949 | ex_off.X_add_number = mips_cpreturn_offset; | |
16950 | ||
67c0d1eb | 16951 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 16952 | BFD_RELOC_LO16, SP); |
6478892d TS |
16953 | } |
16954 | else | |
40fc1451 | 16955 | move_register (mips_cpreturn_register, mips_gp_register); |
6478892d | 16956 | |
aed1a261 | 16957 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
aa6975fb | 16958 | { |
df58fc94 | 16959 | macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register, |
aa6975fb ILT |
16960 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, |
16961 | BFD_RELOC_HI16_S); | |
16962 | ||
16963 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
16964 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
16965 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
16966 | ||
16967 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
16968 | mips_gp_register, reg1); | |
16969 | } | |
16970 | else | |
16971 | { | |
16972 | expressionS ex; | |
16973 | ||
16974 | ex.X_op = O_symbol; | |
4184909a | 16975 | ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); |
aa6975fb ILT |
16976 | ex.X_op_symbol = NULL; |
16977 | ex.X_add_number = 0; | |
6e1304d8 | 16978 | |
aa6975fb ILT |
16979 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
16980 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
16981 | ||
16982 | macro_build_lui (&ex, mips_gp_register); | |
16983 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
16984 | mips_gp_register, BFD_RELOC_LO16); | |
16985 | } | |
f21f8242 | 16986 | |
584892a6 | 16987 | macro_end (); |
6478892d | 16988 | |
8a75745d | 16989 | mips_assembling_insn = FALSE; |
6478892d TS |
16990 | demand_empty_rest_of_line (); |
16991 | } | |
16992 | ||
16993 | static void | |
17a2f251 | 16994 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d | 16995 | { |
919731af | 16996 | file_mips_check_options (); |
16997 | ||
6478892d | 16998 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, |
54f4ddb3 | 16999 | .cplocal is ignored. */ |
6478892d TS |
17000 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) |
17001 | { | |
17002 | s_ignore (0); | |
17003 | return; | |
17004 | } | |
17005 | ||
a276b80c MR |
17006 | if (mips_opts.mips16) |
17007 | { | |
17008 | as_bad (_("%s not supported in MIPS16 mode"), ".cplocal"); | |
17009 | ignore_rest_of_line (); | |
17010 | return; | |
17011 | } | |
17012 | ||
6478892d | 17013 | mips_gp_register = tc_get_register (0); |
85b51719 | 17014 | demand_empty_rest_of_line (); |
6478892d TS |
17015 | } |
17016 | ||
252b5132 RH |
17017 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
17018 | offset from $sp. The offset is remembered, and after making a PIC | |
17019 | call $gp is restored from that location. */ | |
17020 | ||
17021 | static void | |
17a2f251 | 17022 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
17023 | { |
17024 | expressionS ex; | |
252b5132 | 17025 | |
919731af | 17026 | file_mips_check_options (); |
17027 | ||
6478892d | 17028 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 17029 | .cprestore is ignored. */ |
6478892d | 17030 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
17031 | { |
17032 | s_ignore (0); | |
17033 | return; | |
17034 | } | |
17035 | ||
a276b80c MR |
17036 | if (mips_opts.mips16) |
17037 | { | |
17038 | as_bad (_("%s not supported in MIPS16 mode"), ".cprestore"); | |
17039 | ignore_rest_of_line (); | |
17040 | return; | |
17041 | } | |
17042 | ||
252b5132 | 17043 | mips_cprestore_offset = get_absolute_expression (); |
7a621144 | 17044 | mips_cprestore_valid = 1; |
252b5132 RH |
17045 | |
17046 | ex.X_op = O_constant; | |
17047 | ex.X_add_symbol = NULL; | |
17048 | ex.X_op_symbol = NULL; | |
17049 | ex.X_add_number = mips_cprestore_offset; | |
17050 | ||
8a75745d MR |
17051 | mips_mark_labels (); |
17052 | mips_assembling_insn = TRUE; | |
17053 | ||
584892a6 | 17054 | macro_start (); |
67c0d1eb RS |
17055 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
17056 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 17057 | macro_end (); |
252b5132 | 17058 | |
8a75745d | 17059 | mips_assembling_insn = FALSE; |
252b5132 RH |
17060 | demand_empty_rest_of_line (); |
17061 | } | |
17062 | ||
6478892d | 17063 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 17064 | was given in the preceding .cpsetup, it results in: |
6478892d | 17065 | ld $gp, offset($sp) |
76b3015f | 17066 | |
6478892d | 17067 | If a register $reg2 was given there, it results in: |
40fc1451 | 17068 | or $gp, $reg2, $0 */ |
54f4ddb3 | 17069 | |
6478892d | 17070 | static void |
17a2f251 | 17071 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
17072 | { |
17073 | expressionS ex; | |
6478892d | 17074 | |
919731af | 17075 | file_mips_check_options (); |
17076 | ||
6478892d TS |
17077 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. |
17078 | We also need NewABI support. */ | |
17079 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
17080 | { | |
17081 | s_ignore (0); | |
17082 | return; | |
17083 | } | |
17084 | ||
a276b80c MR |
17085 | if (mips_opts.mips16) |
17086 | { | |
17087 | as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn"); | |
17088 | ignore_rest_of_line (); | |
17089 | return; | |
17090 | } | |
17091 | ||
8a75745d MR |
17092 | mips_mark_labels (); |
17093 | mips_assembling_insn = TRUE; | |
17094 | ||
584892a6 | 17095 | macro_start (); |
6478892d TS |
17096 | if (mips_cpreturn_register == -1) |
17097 | { | |
17098 | ex.X_op = O_constant; | |
17099 | ex.X_add_symbol = NULL; | |
17100 | ex.X_op_symbol = NULL; | |
17101 | ex.X_add_number = mips_cpreturn_offset; | |
17102 | ||
67c0d1eb | 17103 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
17104 | } |
17105 | else | |
40fc1451 SD |
17106 | move_register (mips_gp_register, mips_cpreturn_register); |
17107 | ||
584892a6 | 17108 | macro_end (); |
6478892d | 17109 | |
8a75745d | 17110 | mips_assembling_insn = FALSE; |
6478892d TS |
17111 | demand_empty_rest_of_line (); |
17112 | } | |
17113 | ||
d0f13682 CLT |
17114 | /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword |
17115 | pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size | |
17116 | DTP- or TP-relative relocation of type RTYPE, for use in either DWARF | |
17117 | debug information or MIPS16 TLS. */ | |
741d6ea8 JM |
17118 | |
17119 | static void | |
d0f13682 CLT |
17120 | s_tls_rel_directive (const size_t bytes, const char *dirstr, |
17121 | bfd_reloc_code_real_type rtype) | |
741d6ea8 JM |
17122 | { |
17123 | expressionS ex; | |
17124 | char *p; | |
17125 | ||
17126 | expression (&ex); | |
17127 | ||
17128 | if (ex.X_op != O_symbol) | |
17129 | { | |
1661c76c | 17130 | as_bad (_("unsupported use of %s"), dirstr); |
741d6ea8 JM |
17131 | ignore_rest_of_line (); |
17132 | } | |
17133 | ||
17134 | p = frag_more (bytes); | |
17135 | md_number_to_chars (p, 0, bytes); | |
d0f13682 | 17136 | fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype); |
741d6ea8 | 17137 | demand_empty_rest_of_line (); |
de64cffd | 17138 | mips_clear_insn_labels (); |
741d6ea8 JM |
17139 | } |
17140 | ||
17141 | /* Handle .dtprelword. */ | |
17142 | ||
17143 | static void | |
17144 | s_dtprelword (int ignore ATTRIBUTE_UNUSED) | |
17145 | { | |
d0f13682 | 17146 | s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32); |
741d6ea8 JM |
17147 | } |
17148 | ||
17149 | /* Handle .dtpreldword. */ | |
17150 | ||
17151 | static void | |
17152 | s_dtpreldword (int ignore ATTRIBUTE_UNUSED) | |
17153 | { | |
d0f13682 CLT |
17154 | s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64); |
17155 | } | |
17156 | ||
17157 | /* Handle .tprelword. */ | |
17158 | ||
17159 | static void | |
17160 | s_tprelword (int ignore ATTRIBUTE_UNUSED) | |
17161 | { | |
17162 | s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32); | |
17163 | } | |
17164 | ||
17165 | /* Handle .tpreldword. */ | |
17166 | ||
17167 | static void | |
17168 | s_tpreldword (int ignore ATTRIBUTE_UNUSED) | |
17169 | { | |
17170 | s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64); | |
741d6ea8 JM |
17171 | } |
17172 | ||
6478892d TS |
17173 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC |
17174 | code. It sets the offset to use in gp_rel relocations. */ | |
17175 | ||
17176 | static void | |
17a2f251 | 17177 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
17178 | { |
17179 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
17180 | We also need NewABI support. */ | |
17181 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
17182 | { | |
17183 | s_ignore (0); | |
17184 | return; | |
17185 | } | |
17186 | ||
def2e0dd | 17187 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
17188 | |
17189 | demand_empty_rest_of_line (); | |
17190 | } | |
17191 | ||
252b5132 RH |
17192 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
17193 | code. It generates a 32 bit GP relative reloc. */ | |
17194 | ||
17195 | static void | |
17a2f251 | 17196 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 17197 | { |
a8dbcb85 TS |
17198 | segment_info_type *si; |
17199 | struct insn_label_list *l; | |
252b5132 RH |
17200 | expressionS ex; |
17201 | char *p; | |
17202 | ||
17203 | /* When not generating PIC code, this is treated as .word. */ | |
17204 | if (mips_pic != SVR4_PIC) | |
17205 | { | |
17206 | s_cons (2); | |
17207 | return; | |
17208 | } | |
17209 | ||
a8dbcb85 TS |
17210 | si = seg_info (now_seg); |
17211 | l = si->label_list; | |
7d10b47d | 17212 | mips_emit_delays (); |
252b5132 | 17213 | if (auto_align) |
462427c4 | 17214 | mips_align (2, 0, l); |
252b5132 RH |
17215 | |
17216 | expression (&ex); | |
a1facbec | 17217 | mips_clear_insn_labels (); |
252b5132 RH |
17218 | |
17219 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
17220 | { | |
1661c76c | 17221 | as_bad (_("unsupported use of .gpword")); |
252b5132 RH |
17222 | ignore_rest_of_line (); |
17223 | } | |
17224 | ||
17225 | p = frag_more (4); | |
17a2f251 | 17226 | md_number_to_chars (p, 0, 4); |
b34976b6 | 17227 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 17228 | BFD_RELOC_GPREL32); |
252b5132 RH |
17229 | |
17230 | demand_empty_rest_of_line (); | |
17231 | } | |
17232 | ||
10181a0d | 17233 | static void |
17a2f251 | 17234 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d | 17235 | { |
a8dbcb85 TS |
17236 | segment_info_type *si; |
17237 | struct insn_label_list *l; | |
10181a0d AO |
17238 | expressionS ex; |
17239 | char *p; | |
17240 | ||
17241 | /* When not generating PIC code, this is treated as .dword. */ | |
17242 | if (mips_pic != SVR4_PIC) | |
17243 | { | |
17244 | s_cons (3); | |
17245 | return; | |
17246 | } | |
17247 | ||
a8dbcb85 TS |
17248 | si = seg_info (now_seg); |
17249 | l = si->label_list; | |
7d10b47d | 17250 | mips_emit_delays (); |
10181a0d | 17251 | if (auto_align) |
462427c4 | 17252 | mips_align (3, 0, l); |
10181a0d AO |
17253 | |
17254 | expression (&ex); | |
a1facbec | 17255 | mips_clear_insn_labels (); |
10181a0d AO |
17256 | |
17257 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
17258 | { | |
1661c76c | 17259 | as_bad (_("unsupported use of .gpdword")); |
10181a0d AO |
17260 | ignore_rest_of_line (); |
17261 | } | |
17262 | ||
17263 | p = frag_more (8); | |
17a2f251 | 17264 | md_number_to_chars (p, 0, 8); |
a105a300 | 17265 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 17266 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
17267 | |
17268 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
17269 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
17270 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
17271 | |
17272 | demand_empty_rest_of_line (); | |
17273 | } | |
17274 | ||
a3f278e2 CM |
17275 | /* Handle the .ehword pseudo-op. This is used when generating unwinding |
17276 | tables. It generates a R_MIPS_EH reloc. */ | |
17277 | ||
17278 | static void | |
17279 | s_ehword (int ignore ATTRIBUTE_UNUSED) | |
17280 | { | |
17281 | expressionS ex; | |
17282 | char *p; | |
17283 | ||
17284 | mips_emit_delays (); | |
17285 | ||
17286 | expression (&ex); | |
17287 | mips_clear_insn_labels (); | |
17288 | ||
17289 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
17290 | { | |
1661c76c | 17291 | as_bad (_("unsupported use of .ehword")); |
a3f278e2 CM |
17292 | ignore_rest_of_line (); |
17293 | } | |
17294 | ||
17295 | p = frag_more (4); | |
17296 | md_number_to_chars (p, 0, 4); | |
17297 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, | |
2f0c68f2 | 17298 | BFD_RELOC_32_PCREL); |
a3f278e2 CM |
17299 | |
17300 | demand_empty_rest_of_line (); | |
17301 | } | |
17302 | ||
252b5132 RH |
17303 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
17304 | tables in SVR4 PIC code. */ | |
17305 | ||
17306 | static void | |
17a2f251 | 17307 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 17308 | { |
252b5132 RH |
17309 | int reg; |
17310 | ||
919731af | 17311 | file_mips_check_options (); |
17312 | ||
10181a0d AO |
17313 | /* This is ignored when not generating SVR4 PIC code. */ |
17314 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
17315 | { |
17316 | s_ignore (0); | |
17317 | return; | |
17318 | } | |
17319 | ||
8a75745d MR |
17320 | mips_mark_labels (); |
17321 | mips_assembling_insn = TRUE; | |
17322 | ||
252b5132 | 17323 | /* Add $gp to the register named as an argument. */ |
584892a6 | 17324 | macro_start (); |
252b5132 | 17325 | reg = tc_get_register (0); |
67c0d1eb | 17326 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 17327 | macro_end (); |
252b5132 | 17328 | |
8a75745d | 17329 | mips_assembling_insn = FALSE; |
bdaaa2e1 | 17330 | demand_empty_rest_of_line (); |
252b5132 RH |
17331 | } |
17332 | ||
17333 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
df58fc94 | 17334 | mips16/micromips mode. This permits the linker to handle them specially, |
252b5132 RH |
17335 | such as generating jalx instructions when needed. We also make |
17336 | them odd for the duration of the assembly, in order to generate the | |
17337 | right sort of code. We will make them even in the adjust_symtab | |
17338 | routine, while leaving them marked. This is convenient for the | |
17339 | debugger and the disassembler. The linker knows to make them odd | |
17340 | again. */ | |
17341 | ||
17342 | static void | |
17a2f251 | 17343 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 17344 | { |
7bb01e2d MR |
17345 | file_mips_check_options (); |
17346 | file_ase_mips16 |= mips_opts.mips16; | |
17347 | file_ase_micromips |= mips_opts.micromips; | |
17348 | ||
df58fc94 | 17349 | mips_mark_labels (); |
252b5132 RH |
17350 | |
17351 | demand_empty_rest_of_line (); | |
17352 | } | |
17353 | ||
ba92f887 MR |
17354 | /* Handle the .nan pseudo-op. */ |
17355 | ||
17356 | static void | |
17357 | s_nan (int ignore ATTRIBUTE_UNUSED) | |
17358 | { | |
17359 | static const char str_legacy[] = "legacy"; | |
17360 | static const char str_2008[] = "2008"; | |
17361 | size_t i; | |
17362 | ||
17363 | for (i = 0; !is_end_of_line[(unsigned char) input_line_pointer[i]]; i++); | |
17364 | ||
17365 | if (i == sizeof (str_2008) - 1 | |
17366 | && memcmp (input_line_pointer, str_2008, i) == 0) | |
7361da2c | 17367 | mips_nan2008 = 1; |
ba92f887 MR |
17368 | else if (i == sizeof (str_legacy) - 1 |
17369 | && memcmp (input_line_pointer, str_legacy, i) == 0) | |
7361da2c AB |
17370 | { |
17371 | if (ISA_HAS_LEGACY_NAN (file_mips_opts.isa)) | |
17372 | mips_nan2008 = 0; | |
17373 | else | |
17374 | as_bad (_("`%s' does not support legacy NaN"), | |
17375 | mips_cpu_info_from_isa (file_mips_opts.isa)->name); | |
17376 | } | |
ba92f887 | 17377 | else |
1661c76c | 17378 | as_bad (_("bad .nan directive")); |
ba92f887 MR |
17379 | |
17380 | input_line_pointer += i; | |
17381 | demand_empty_rest_of_line (); | |
17382 | } | |
17383 | ||
754e2bb9 RS |
17384 | /* Handle a .stab[snd] directive. Ideally these directives would be |
17385 | implemented in a transparent way, so that removing them would not | |
17386 | have any effect on the generated instructions. However, s_stab | |
17387 | internally changes the section, so in practice we need to decide | |
17388 | now whether the preceding label marks compressed code. We do not | |
17389 | support changing the compression mode of a label after a .stab* | |
17390 | directive, such as in: | |
17391 | ||
17392 | foo: | |
134c0c8b | 17393 | .stabs ... |
754e2bb9 RS |
17394 | .set mips16 |
17395 | ||
17396 | so the current mode wins. */ | |
252b5132 RH |
17397 | |
17398 | static void | |
17a2f251 | 17399 | s_mips_stab (int type) |
252b5132 | 17400 | { |
42c0794e | 17401 | file_mips_check_options (); |
754e2bb9 | 17402 | mips_mark_labels (); |
252b5132 RH |
17403 | s_stab (type); |
17404 | } | |
17405 | ||
54f4ddb3 | 17406 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */ |
252b5132 RH |
17407 | |
17408 | static void | |
17a2f251 | 17409 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
17410 | { |
17411 | char *name; | |
17412 | int c; | |
17413 | symbolS *symbolP; | |
17414 | expressionS exp; | |
17415 | ||
d02603dc | 17416 | c = get_symbol_name (&name); |
252b5132 RH |
17417 | symbolP = symbol_find_or_make (name); |
17418 | S_SET_WEAK (symbolP); | |
17419 | *input_line_pointer = c; | |
17420 | ||
d02603dc | 17421 | SKIP_WHITESPACE_AFTER_NAME (); |
252b5132 RH |
17422 | |
17423 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
17424 | { | |
17425 | if (S_IS_DEFINED (symbolP)) | |
17426 | { | |
20203fb9 | 17427 | as_bad (_("ignoring attempt to redefine symbol %s"), |
252b5132 RH |
17428 | S_GET_NAME (symbolP)); |
17429 | ignore_rest_of_line (); | |
17430 | return; | |
17431 | } | |
bdaaa2e1 | 17432 | |
252b5132 RH |
17433 | if (*input_line_pointer == ',') |
17434 | { | |
17435 | ++input_line_pointer; | |
17436 | SKIP_WHITESPACE (); | |
17437 | } | |
bdaaa2e1 | 17438 | |
252b5132 RH |
17439 | expression (&exp); |
17440 | if (exp.X_op != O_symbol) | |
17441 | { | |
20203fb9 | 17442 | as_bad (_("bad .weakext directive")); |
98d3f06f | 17443 | ignore_rest_of_line (); |
252b5132 RH |
17444 | return; |
17445 | } | |
49309057 | 17446 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
17447 | } |
17448 | ||
17449 | demand_empty_rest_of_line (); | |
17450 | } | |
17451 | ||
17452 | /* Parse a register string into a number. Called from the ECOFF code | |
17453 | to parse .frame. The argument is non-zero if this is the frame | |
17454 | register, so that we can record it in mips_frame_reg. */ | |
17455 | ||
17456 | int | |
17a2f251 | 17457 | tc_get_register (int frame) |
252b5132 | 17458 | { |
707bfff6 | 17459 | unsigned int reg; |
252b5132 RH |
17460 | |
17461 | SKIP_WHITESPACE (); | |
707bfff6 TS |
17462 | if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®)) |
17463 | reg = 0; | |
252b5132 | 17464 | if (frame) |
7a621144 DJ |
17465 | { |
17466 | mips_frame_reg = reg != 0 ? reg : SP; | |
17467 | mips_frame_reg_valid = 1; | |
17468 | mips_cprestore_valid = 0; | |
17469 | } | |
252b5132 RH |
17470 | return reg; |
17471 | } | |
17472 | ||
17473 | valueT | |
17a2f251 | 17474 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
17475 | { |
17476 | int align = bfd_get_section_alignment (stdoutput, seg); | |
17477 | ||
f3ded42a RS |
17478 | /* We don't need to align ELF sections to the full alignment. |
17479 | However, Irix 5 may prefer that we align them at least to a 16 | |
17480 | byte boundary. We don't bother to align the sections if we | |
17481 | are targeted for an embedded system. */ | |
17482 | if (strncmp (TARGET_OS, "elf", 3) == 0) | |
17483 | return addr; | |
17484 | if (align > 4) | |
17485 | align = 4; | |
252b5132 | 17486 | |
8d3842cd | 17487 | return ((addr + (1 << align) - 1) & -(1 << align)); |
252b5132 RH |
17488 | } |
17489 | ||
17490 | /* Utility routine, called from above as well. If called while the | |
17491 | input file is still being read, it's only an approximation. (For | |
17492 | example, a symbol may later become defined which appeared to be | |
17493 | undefined earlier.) */ | |
17494 | ||
17495 | static int | |
17a2f251 | 17496 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
17497 | { |
17498 | if (sym == 0) | |
17499 | return 0; | |
17500 | ||
4d0d148d | 17501 | if (g_switch_value > 0) |
252b5132 RH |
17502 | { |
17503 | const char *symname; | |
17504 | int change; | |
17505 | ||
c9914766 | 17506 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
17507 | register. It can be if it is smaller than the -G size or if |
17508 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 17509 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
17510 | they can. */ |
17511 | symname = S_GET_NAME (sym); | |
17512 | if (symname != (const char *) NULL | |
17513 | && (strcmp (symname, "eprol") == 0 | |
17514 | || strcmp (symname, "etext") == 0 | |
17515 | || strcmp (symname, "_gp") == 0 | |
17516 | || strcmp (symname, "edata") == 0 | |
17517 | || strcmp (symname, "_fbss") == 0 | |
17518 | || strcmp (symname, "_fdata") == 0 | |
17519 | || strcmp (symname, "_ftext") == 0 | |
17520 | || strcmp (symname, "end") == 0 | |
17521 | || strcmp (symname, "_gp_disp") == 0)) | |
17522 | change = 1; | |
17523 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
17524 | && (0 | |
17525 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
17526 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
17527 | && (symbol_get_obj (sym)->ecoff_extern_size | |
17528 | <= g_switch_value)) | |
252b5132 RH |
17529 | #endif |
17530 | /* We must defer this decision until after the whole | |
17531 | file has been read, since there might be a .extern | |
17532 | after the first use of this symbol. */ | |
17533 | || (before_relaxing | |
17534 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 17535 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
17536 | #endif |
17537 | && S_GET_VALUE (sym) == 0) | |
17538 | || (S_GET_VALUE (sym) != 0 | |
17539 | && S_GET_VALUE (sym) <= g_switch_value))) | |
17540 | change = 0; | |
17541 | else | |
17542 | { | |
17543 | const char *segname; | |
17544 | ||
17545 | segname = segment_name (S_GET_SEGMENT (sym)); | |
9c2799c2 | 17546 | gas_assert (strcmp (segname, ".lit8") != 0 |
252b5132 RH |
17547 | && strcmp (segname, ".lit4") != 0); |
17548 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
17549 | && strcmp (segname, ".sbss") != 0 |
17550 | && strncmp (segname, ".sdata.", 7) != 0 | |
d4dc2f22 TS |
17551 | && strncmp (segname, ".sbss.", 6) != 0 |
17552 | && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0 | |
fba2b7f9 | 17553 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); |
252b5132 RH |
17554 | } |
17555 | return change; | |
17556 | } | |
17557 | else | |
c9914766 | 17558 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
17559 | return 1; |
17560 | } | |
17561 | ||
5919d012 RS |
17562 | |
17563 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
17564 | ||
17565 | static bfd_boolean | |
9e009953 | 17566 | pic_need_relax (symbolS *sym) |
5919d012 RS |
17567 | { |
17568 | asection *symsec; | |
5919d012 RS |
17569 | |
17570 | /* Handle the case of a symbol equated to another symbol. */ | |
17571 | while (symbol_equated_reloc_p (sym)) | |
17572 | { | |
17573 | symbolS *n; | |
17574 | ||
5f0fe04b | 17575 | /* It's possible to get a loop here in a badly written program. */ |
5919d012 RS |
17576 | n = symbol_get_value_expression (sym)->X_add_symbol; |
17577 | if (n == sym) | |
17578 | break; | |
17579 | sym = n; | |
17580 | } | |
17581 | ||
df1f3cda DD |
17582 | if (symbol_section_p (sym)) |
17583 | return TRUE; | |
17584 | ||
5919d012 RS |
17585 | symsec = S_GET_SEGMENT (sym); |
17586 | ||
5919d012 | 17587 | /* This must duplicate the test in adjust_reloc_syms. */ |
45dfa85a AM |
17588 | return (!bfd_is_und_section (symsec) |
17589 | && !bfd_is_abs_section (symsec) | |
5f0fe04b | 17590 | && !bfd_is_com_section (symsec) |
5919d012 | 17591 | /* A global or weak symbol is treated as external. */ |
f3ded42a | 17592 | && (!S_IS_WEAK (sym) && !S_IS_EXTERNAL (sym))); |
5919d012 | 17593 | } |
14f72d45 MR |
17594 | \f |
17595 | /* Given a MIPS16 variant frag FRAGP and PC-relative operand PCREL_OP | |
17596 | convert a section-relative value VAL to the equivalent PC-relative | |
17597 | value. */ | |
17598 | ||
17599 | static offsetT | |
17600 | mips16_pcrel_val (fragS *fragp, const struct mips_pcrel_operand *pcrel_op, | |
17601 | offsetT val, long stretch) | |
17602 | { | |
17603 | fragS *sym_frag; | |
17604 | addressT addr; | |
17605 | ||
17606 | gas_assert (pcrel_op->root.root.type == OP_PCREL); | |
17607 | ||
17608 | sym_frag = symbol_get_frag (fragp->fr_symbol); | |
17609 | ||
17610 | /* If the relax_marker of the symbol fragment differs from the | |
17611 | relax_marker of this fragment, we have not yet adjusted the | |
17612 | symbol fragment fr_address. We want to add in STRETCH in | |
17613 | order to get a better estimate of the address. This | |
17614 | particularly matters because of the shift bits. */ | |
17615 | if (stretch != 0 && sym_frag->relax_marker != fragp->relax_marker) | |
17616 | { | |
17617 | fragS *f; | |
17618 | ||
17619 | /* Adjust stretch for any alignment frag. Note that if have | |
17620 | been expanding the earlier code, the symbol may be | |
17621 | defined in what appears to be an earlier frag. FIXME: | |
17622 | This doesn't handle the fr_subtype field, which specifies | |
17623 | a maximum number of bytes to skip when doing an | |
17624 | alignment. */ | |
17625 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) | |
17626 | { | |
17627 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
17628 | { | |
17629 | if (stretch < 0) | |
17630 | stretch = -(-stretch & ~((1 << (int) f->fr_offset) - 1)); | |
17631 | else | |
17632 | stretch &= ~((1 << (int) f->fr_offset) - 1); | |
17633 | if (stretch == 0) | |
17634 | break; | |
17635 | } | |
17636 | } | |
17637 | if (f != NULL) | |
17638 | val += stretch; | |
17639 | } | |
17640 | ||
17641 | addr = fragp->fr_address + fragp->fr_fix; | |
17642 | ||
17643 | /* The base address rules are complicated. The base address of | |
17644 | a branch is the following instruction. The base address of a | |
17645 | PC relative load or add is the instruction itself, but if it | |
17646 | is in a delay slot (in which case it can not be extended) use | |
17647 | the address of the instruction whose delay slot it is in. */ | |
17648 | if (pcrel_op->include_isa_bit) | |
17649 | { | |
17650 | addr += 2; | |
17651 | ||
17652 | /* If we are currently assuming that this frag should be | |
17653 | extended, then the current address is two bytes higher. */ | |
17654 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
17655 | addr += 2; | |
17656 | ||
17657 | /* Ignore the low bit in the target, since it will be set | |
17658 | for a text label. */ | |
17659 | val &= -2; | |
17660 | } | |
17661 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
17662 | addr -= 4; | |
17663 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
17664 | addr -= 2; | |
5919d012 | 17665 | |
14f72d45 MR |
17666 | val -= addr & -(1 << pcrel_op->align_log2); |
17667 | ||
17668 | return val; | |
17669 | } | |
5919d012 | 17670 | |
252b5132 RH |
17671 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
17672 | extended opcode. SEC is the section the frag is in. */ | |
17673 | ||
17674 | static int | |
17a2f251 | 17675 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 | 17676 | { |
3ccad066 | 17677 | const struct mips_int_operand *operand; |
252b5132 | 17678 | offsetT val; |
252b5132 | 17679 | segT symsec; |
14f72d45 | 17680 | int type; |
252b5132 RH |
17681 | |
17682 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
17683 | return 0; | |
17684 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
17685 | return 1; | |
17686 | ||
88a7ef16 | 17687 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 | 17688 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); |
3ccad066 | 17689 | operand = mips16_immed_operand (type, FALSE); |
88a7ef16 MR |
17690 | if (S_FORCE_RELOC (fragp->fr_symbol, TRUE) |
17691 | || (operand->root.type == OP_PCREL | |
17692 | ? sec != symsec | |
17693 | : !bfd_is_abs_section (symsec))) | |
17694 | return 1; | |
252b5132 | 17695 | |
88a7ef16 | 17696 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; |
252b5132 | 17697 | |
3ccad066 | 17698 | if (operand->root.type == OP_PCREL) |
252b5132 | 17699 | { |
3ccad066 | 17700 | const struct mips_pcrel_operand *pcrel_op; |
3ccad066 | 17701 | offsetT maxtiny; |
252b5132 | 17702 | |
1425c41d | 17703 | if (RELAX_MIPS16_ALWAYS_EXTENDED (fragp->fr_subtype)) |
88a7ef16 | 17704 | return 1; |
252b5132 | 17705 | |
88a7ef16 | 17706 | pcrel_op = (const struct mips_pcrel_operand *) operand; |
14f72d45 | 17707 | val = mips16_pcrel_val (fragp, pcrel_op, val, stretch); |
252b5132 RH |
17708 | |
17709 | /* If any of the shifted bits are set, we must use an extended | |
17710 | opcode. If the address depends on the size of this | |
17711 | instruction, this can lead to a loop, so we arrange to always | |
88a7ef16 MR |
17712 | use an extended opcode. */ |
17713 | if ((val & ((1 << operand->shift) - 1)) != 0) | |
252b5132 RH |
17714 | { |
17715 | fragp->fr_subtype = | |
1425c41d | 17716 | RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp->fr_subtype); |
252b5132 RH |
17717 | return 1; |
17718 | } | |
17719 | ||
17720 | /* If we are about to mark a frag as extended because the value | |
3ccad066 RS |
17721 | is precisely the next value above maxtiny, then there is a |
17722 | chance of an infinite loop as in the following code: | |
252b5132 RH |
17723 | la $4,foo |
17724 | .skip 1020 | |
17725 | .align 2 | |
17726 | foo: | |
17727 | In this case when the la is extended, foo is 0x3fc bytes | |
17728 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
17729 | the la must be extended. To avoid this loop, we mark the | |
17730 | frag as extended if it was small, and is about to become | |
3ccad066 RS |
17731 | extended with the next value above maxtiny. */ |
17732 | maxtiny = mips_int_operand_max (operand); | |
17733 | if (val == maxtiny + (1 << operand->shift) | |
88a7ef16 | 17734 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
252b5132 RH |
17735 | { |
17736 | fragp->fr_subtype = | |
1425c41d | 17737 | RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp->fr_subtype); |
252b5132 RH |
17738 | return 1; |
17739 | } | |
17740 | } | |
252b5132 | 17741 | |
3ccad066 | 17742 | return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val); |
252b5132 RH |
17743 | } |
17744 | ||
8507b6e7 MR |
17745 | /* Given a MIPS16 variant frag FRAGP, return non-zero if it needs |
17746 | macro expansion. SEC is the section the frag is in. We only | |
17747 | support PC-relative instructions (LA, DLA, LW, LD) here, in | |
17748 | non-PIC code using 32-bit addressing. */ | |
17749 | ||
17750 | static int | |
17751 | mips16_macro_frag (fragS *fragp, asection *sec, long stretch) | |
17752 | { | |
17753 | const struct mips_pcrel_operand *pcrel_op; | |
17754 | const struct mips_int_operand *operand; | |
17755 | offsetT val; | |
17756 | segT symsec; | |
17757 | int type; | |
17758 | ||
17759 | gas_assert (!RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)); | |
17760 | ||
17761 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
17762 | return 0; | |
17763 | if (!RELAX_MIPS16_SYM32 (fragp->fr_subtype)) | |
17764 | return 0; | |
17765 | ||
17766 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
17767 | switch (type) | |
17768 | { | |
17769 | case 'A': | |
17770 | case 'B': | |
17771 | case 'E': | |
17772 | symsec = S_GET_SEGMENT (fragp->fr_symbol); | |
17773 | if (bfd_is_abs_section (symsec)) | |
17774 | return 1; | |
17775 | if (RELAX_MIPS16_PIC (fragp->fr_subtype)) | |
17776 | return 0; | |
17777 | if (S_FORCE_RELOC (fragp->fr_symbol, TRUE) || sec != symsec) | |
17778 | return 1; | |
17779 | ||
17780 | operand = mips16_immed_operand (type, TRUE); | |
17781 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17782 | pcrel_op = (const struct mips_pcrel_operand *) operand; | |
17783 | val = mips16_pcrel_val (fragp, pcrel_op, val, stretch); | |
17784 | ||
17785 | return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val); | |
17786 | ||
17787 | default: | |
17788 | return 0; | |
17789 | } | |
17790 | } | |
17791 | ||
4a6a3df4 AO |
17792 | /* Compute the length of a branch sequence, and adjust the |
17793 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
17794 | worst-case length is computed, with UPDATE being used to indicate | |
17795 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
17796 | branch is to be computed. */ | |
17797 | static int | |
17a2f251 | 17798 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 17799 | { |
b34976b6 | 17800 | bfd_boolean toofar; |
4a6a3df4 AO |
17801 | int length; |
17802 | ||
17803 | if (fragp | |
17804 | && S_IS_DEFINED (fragp->fr_symbol) | |
991f40a9 | 17805 | && !S_IS_WEAK (fragp->fr_symbol) |
4a6a3df4 AO |
17806 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) |
17807 | { | |
17808 | addressT addr; | |
17809 | offsetT val; | |
17810 | ||
17811 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17812 | ||
17813 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
17814 | ||
17815 | val -= addr; | |
17816 | ||
17817 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
17818 | } | |
4a6a3df4 | 17819 | else |
c1f61bd2 MR |
17820 | /* If the symbol is not defined or it's in a different segment, |
17821 | we emit the long sequence. */ | |
b34976b6 | 17822 | toofar = TRUE; |
4a6a3df4 AO |
17823 | |
17824 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
17825 | fragp->fr_subtype | |
66b3e8da | 17826 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype), |
ce8ad872 | 17827 | RELAX_BRANCH_PIC (fragp->fr_subtype), |
66b3e8da | 17828 | RELAX_BRANCH_UNCOND (fragp->fr_subtype), |
4a6a3df4 AO |
17829 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
17830 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
17831 | toofar); | |
17832 | ||
17833 | length = 4; | |
17834 | if (toofar) | |
17835 | { | |
17836 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
17837 | length += 8; | |
17838 | ||
ce8ad872 | 17839 | if (!fragp || RELAX_BRANCH_PIC (fragp->fr_subtype)) |
4a6a3df4 AO |
17840 | { |
17841 | /* Additional space for PIC loading of target address. */ | |
17842 | length += 8; | |
17843 | if (mips_opts.isa == ISA_MIPS1) | |
17844 | /* Additional space for $at-stabilizing nop. */ | |
17845 | length += 4; | |
17846 | } | |
17847 | ||
17848 | /* If branch is conditional. */ | |
17849 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
17850 | length += 8; | |
17851 | } | |
b34976b6 | 17852 | |
4a6a3df4 AO |
17853 | return length; |
17854 | } | |
17855 | ||
7bd374a4 MR |
17856 | /* Get a FRAG's branch instruction delay slot size, either from the |
17857 | short-delay-slot bit of a branch-and-link instruction if AL is TRUE, | |
17858 | or SHORT_INSN_SIZE otherwise. */ | |
17859 | ||
17860 | static int | |
17861 | frag_branch_delay_slot_size (fragS *fragp, bfd_boolean al, int short_insn_size) | |
17862 | { | |
17863 | char *buf = fragp->fr_literal + fragp->fr_fix; | |
17864 | ||
17865 | if (al) | |
17866 | return (read_compressed_insn (buf, 4) & 0x02000000) ? 2 : 4; | |
17867 | else | |
17868 | return short_insn_size; | |
17869 | } | |
17870 | ||
df58fc94 RS |
17871 | /* Compute the length of a branch sequence, and adjust the |
17872 | RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the | |
17873 | worst-case length is computed, with UPDATE being used to indicate | |
17874 | whether an unconditional (-1), or regular (0) branch is to be | |
17875 | computed. */ | |
17876 | ||
17877 | static int | |
17878 | relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update) | |
17879 | { | |
7bd374a4 MR |
17880 | bfd_boolean insn32 = TRUE; |
17881 | bfd_boolean nods = TRUE; | |
ce8ad872 | 17882 | bfd_boolean pic = TRUE; |
7bd374a4 MR |
17883 | bfd_boolean al = TRUE; |
17884 | int short_insn_size; | |
df58fc94 RS |
17885 | bfd_boolean toofar; |
17886 | int length; | |
17887 | ||
7bd374a4 MR |
17888 | if (fragp) |
17889 | { | |
17890 | insn32 = RELAX_MICROMIPS_INSN32 (fragp->fr_subtype); | |
17891 | nods = RELAX_MICROMIPS_NODS (fragp->fr_subtype); | |
ce8ad872 | 17892 | pic = RELAX_MICROMIPS_PIC (fragp->fr_subtype); |
7bd374a4 MR |
17893 | al = RELAX_MICROMIPS_LINK (fragp->fr_subtype); |
17894 | } | |
17895 | short_insn_size = insn32 ? 4 : 2; | |
17896 | ||
df58fc94 RS |
17897 | if (fragp |
17898 | && S_IS_DEFINED (fragp->fr_symbol) | |
991f40a9 | 17899 | && !S_IS_WEAK (fragp->fr_symbol) |
df58fc94 RS |
17900 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) |
17901 | { | |
17902 | addressT addr; | |
17903 | offsetT val; | |
17904 | ||
17905 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17906 | /* Ignore the low bit in the target, since it will be set | |
17907 | for a text label. */ | |
17908 | if ((val & 1) != 0) | |
17909 | --val; | |
17910 | ||
17911 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
17912 | ||
17913 | val -= addr; | |
17914 | ||
17915 | toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1); | |
17916 | } | |
df58fc94 | 17917 | else |
c1f61bd2 MR |
17918 | /* If the symbol is not defined or it's in a different segment, |
17919 | we emit the long sequence. */ | |
df58fc94 RS |
17920 | toofar = TRUE; |
17921 | ||
17922 | if (fragp && update | |
17923 | && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
17924 | fragp->fr_subtype = (toofar | |
17925 | ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype) | |
17926 | : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype)); | |
17927 | ||
17928 | length = 4; | |
17929 | if (toofar) | |
17930 | { | |
17931 | bfd_boolean compact_known = fragp != NULL; | |
17932 | bfd_boolean compact = FALSE; | |
17933 | bfd_boolean uncond; | |
17934 | ||
df58fc94 | 17935 | if (fragp) |
8484fb75 MR |
17936 | { |
17937 | compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); | |
17938 | uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype); | |
8484fb75 | 17939 | } |
df58fc94 RS |
17940 | else |
17941 | uncond = update < 0; | |
17942 | ||
17943 | /* If label is out of range, we turn branch <br>: | |
17944 | ||
17945 | <br> label # 4 bytes | |
17946 | 0: | |
17947 | ||
17948 | into: | |
17949 | ||
17950 | j label # 4 bytes | |
8484fb75 MR |
17951 | nop # 2/4 bytes if |
17952 | # compact && (!PIC || insn32) | |
df58fc94 RS |
17953 | 0: |
17954 | */ | |
ce8ad872 | 17955 | if ((!pic || insn32) && (!compact_known || compact)) |
8484fb75 | 17956 | length += short_insn_size; |
df58fc94 RS |
17957 | |
17958 | /* If assembling PIC code, we further turn: | |
17959 | ||
17960 | j label # 4 bytes | |
17961 | ||
17962 | into: | |
17963 | ||
17964 | lw/ld at, %got(label)(gp) # 4 bytes | |
17965 | d/addiu at, %lo(label) # 4 bytes | |
8484fb75 | 17966 | jr/c at # 2/4 bytes |
df58fc94 | 17967 | */ |
ce8ad872 | 17968 | if (pic) |
8484fb75 | 17969 | length += 4 + short_insn_size; |
df58fc94 | 17970 | |
7bd374a4 MR |
17971 | /* Add an extra nop if the jump has no compact form and we need |
17972 | to fill the delay slot. */ | |
ce8ad872 | 17973 | if ((!pic || al) && nods) |
7bd374a4 MR |
17974 | length += (fragp |
17975 | ? frag_branch_delay_slot_size (fragp, al, short_insn_size) | |
17976 | : short_insn_size); | |
17977 | ||
df58fc94 RS |
17978 | /* If branch <br> is conditional, we prepend negated branch <brneg>: |
17979 | ||
17980 | <brneg> 0f # 4 bytes | |
8484fb75 | 17981 | nop # 2/4 bytes if !compact |
df58fc94 RS |
17982 | */ |
17983 | if (!uncond) | |
8484fb75 | 17984 | length += (compact_known && compact) ? 4 : 4 + short_insn_size; |
df58fc94 | 17985 | } |
7bd374a4 MR |
17986 | else if (nods) |
17987 | { | |
17988 | /* Add an extra nop to fill the delay slot. */ | |
17989 | gas_assert (fragp); | |
17990 | length += frag_branch_delay_slot_size (fragp, al, short_insn_size); | |
17991 | } | |
df58fc94 RS |
17992 | |
17993 | return length; | |
17994 | } | |
17995 | ||
17996 | /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16 | |
17997 | bit accordingly. */ | |
17998 | ||
17999 | static int | |
18000 | relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update) | |
18001 | { | |
18002 | bfd_boolean toofar; | |
18003 | ||
df58fc94 RS |
18004 | if (fragp |
18005 | && S_IS_DEFINED (fragp->fr_symbol) | |
991f40a9 | 18006 | && !S_IS_WEAK (fragp->fr_symbol) |
df58fc94 RS |
18007 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) |
18008 | { | |
18009 | addressT addr; | |
18010 | offsetT val; | |
18011 | int type; | |
18012 | ||
18013 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
18014 | /* Ignore the low bit in the target, since it will be set | |
18015 | for a text label. */ | |
18016 | if ((val & 1) != 0) | |
18017 | --val; | |
18018 | ||
18019 | /* Assume this is a 2-byte branch. */ | |
18020 | addr = fragp->fr_address + fragp->fr_fix + 2; | |
18021 | ||
18022 | /* We try to avoid the infinite loop by not adding 2 more bytes for | |
18023 | long branches. */ | |
18024 | ||
18025 | val -= addr; | |
18026 | ||
18027 | type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
18028 | if (type == 'D') | |
18029 | toofar = val < - (0x200 << 1) || val >= (0x200 << 1); | |
18030 | else if (type == 'E') | |
18031 | toofar = val < - (0x40 << 1) || val >= (0x40 << 1); | |
18032 | else | |
18033 | abort (); | |
18034 | } | |
18035 | else | |
18036 | /* If the symbol is not defined or it's in a different segment, | |
18037 | we emit a normal 32-bit branch. */ | |
18038 | toofar = TRUE; | |
18039 | ||
18040 | if (fragp && update | |
18041 | && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
18042 | fragp->fr_subtype | |
18043 | = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype) | |
18044 | : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype); | |
18045 | ||
18046 | if (toofar) | |
18047 | return 4; | |
18048 | ||
18049 | return 2; | |
18050 | } | |
18051 | ||
252b5132 RH |
18052 | /* Estimate the size of a frag before relaxing. Unless this is the |
18053 | mips16, we are not really relaxing here, and the final size is | |
18054 | encoded in the subtype information. For the mips16, we have to | |
18055 | decide whether we are using an extended opcode or not. */ | |
18056 | ||
252b5132 | 18057 | int |
17a2f251 | 18058 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 18059 | { |
5919d012 | 18060 | int change; |
252b5132 | 18061 | |
4a6a3df4 AO |
18062 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
18063 | { | |
18064 | ||
b34976b6 AM |
18065 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
18066 | ||
4a6a3df4 AO |
18067 | return fragp->fr_var; |
18068 | } | |
18069 | ||
252b5132 | 18070 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
8507b6e7 MR |
18071 | { |
18072 | /* We don't want to modify the EXTENDED bit here; it might get us | |
18073 | into infinite loops. We change it only in mips_relax_frag(). */ | |
18074 | if (RELAX_MIPS16_MACRO (fragp->fr_subtype)) | |
25499ac7 | 18075 | return RELAX_MIPS16_E2 (fragp->fr_subtype) ? 8 : 12; |
8507b6e7 MR |
18076 | else |
18077 | return RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2; | |
18078 | } | |
252b5132 | 18079 | |
df58fc94 RS |
18080 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
18081 | { | |
18082 | int length = 4; | |
18083 | ||
18084 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
18085 | length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE); | |
18086 | if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
18087 | length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE); | |
18088 | fragp->fr_var = length; | |
18089 | ||
18090 | return length; | |
18091 | } | |
18092 | ||
ce8ad872 | 18093 | if (mips_pic == VXWORKS_PIC) |
0a44bf69 RS |
18094 | /* For vxworks, GOT16 relocations never have a corresponding LO16. */ |
18095 | change = 0; | |
ce8ad872 MR |
18096 | else if (RELAX_PIC (fragp->fr_subtype)) |
18097 | change = pic_need_relax (fragp->fr_symbol); | |
252b5132 | 18098 | else |
ce8ad872 | 18099 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 RH |
18100 | |
18101 | if (change) | |
18102 | { | |
4d7206a2 | 18103 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 18104 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 18105 | } |
4d7206a2 RS |
18106 | else |
18107 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
18108 | } |
18109 | ||
18110 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 18111 | should be converted into a reloc against a section. */ |
252b5132 RH |
18112 | |
18113 | int | |
17a2f251 | 18114 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 18115 | { |
252b5132 RH |
18116 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
18117 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
18118 | return 0; | |
a161fe53 | 18119 | |
252b5132 RH |
18120 | if (fixp->fx_addsy == NULL) |
18121 | return 1; | |
a161fe53 | 18122 | |
2f0c68f2 CM |
18123 | /* Allow relocs used for EH tables. */ |
18124 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) | |
18125 | return 1; | |
18126 | ||
de7e6852 RS |
18127 | /* If symbol SYM is in a mergeable section, relocations of the form |
18128 | SYM + 0 can usually be made section-relative. The mergeable data | |
18129 | is then identified by the section offset rather than by the symbol. | |
18130 | ||
18131 | However, if we're generating REL LO16 relocations, the offset is split | |
33eaf5de | 18132 | between the LO16 and partnering high part relocation. The linker will |
de7e6852 RS |
18133 | need to recalculate the complete offset in order to correctly identify |
18134 | the merge data. | |
18135 | ||
33eaf5de | 18136 | The linker has traditionally not looked for the partnering high part |
de7e6852 RS |
18137 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be |
18138 | placed anywhere. Rather than break backwards compatibility by changing | |
18139 | this, it seems better not to force the issue, and instead keep the | |
18140 | original symbol. This will work with either linker behavior. */ | |
738e5348 | 18141 | if ((lo16_reloc_p (fixp->fx_r_type) |
704803a9 | 18142 | || reloc_needs_lo_p (fixp->fx_r_type)) |
de7e6852 RS |
18143 | && HAVE_IN_PLACE_ADDENDS |
18144 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
18145 | return 0; | |
18146 | ||
97f50151 MR |
18147 | /* There is no place to store an in-place offset for JALR relocations. */ |
18148 | if (jalr_reloc_p (fixp->fx_r_type) && HAVE_IN_PLACE_ADDENDS) | |
18149 | return 0; | |
18150 | ||
18151 | /* Likewise an in-range offset of limited PC-relative relocations may | |
2de39019 | 18152 | overflow the in-place relocatable field if recalculated against the |
7361da2c AB |
18153 | start address of the symbol's containing section. |
18154 | ||
18155 | Also, PC relative relocations for MIPS R6 need to be symbol rather than | |
18156 | section relative to allow linker relaxations to be performed later on. */ | |
97f50151 | 18157 | if (limited_pcrel_reloc_p (fixp->fx_r_type) |
912815f0 | 18158 | && (HAVE_IN_PLACE_ADDENDS || ISA_IS_R6 (file_mips_opts.isa))) |
1180b5a4 RS |
18159 | return 0; |
18160 | ||
b314ec0e RS |
18161 | /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve |
18162 | to a floating-point stub. The same is true for non-R_MIPS16_26 | |
18163 | relocations against MIPS16 functions; in this case, the stub becomes | |
18164 | the function's canonical address. | |
18165 | ||
18166 | Floating-point stubs are stored in unique .mips16.call.* or | |
18167 | .mips16.fn.* sections. If a stub T for function F is in section S, | |
18168 | the first relocation in section S must be against F; this is how the | |
18169 | linker determines the target function. All relocations that might | |
18170 | resolve to T must also be against F. We therefore have the following | |
18171 | restrictions, which are given in an intentionally-redundant way: | |
18172 | ||
18173 | 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16 | |
18174 | symbols. | |
18175 | ||
18176 | 2. We cannot reduce a stub's relocations against non-MIPS16 symbols | |
18177 | if that stub might be used. | |
18178 | ||
18179 | 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16 | |
18180 | symbols. | |
18181 | ||
18182 | 4. We cannot reduce a stub's relocations against MIPS16 symbols if | |
18183 | that stub might be used. | |
18184 | ||
18185 | There is a further restriction: | |
18186 | ||
df58fc94 | 18187 | 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or |
0e9c5a5c | 18188 | R_MICROMIPS_26_S1) or branch relocations (R_MIPS_PC26_S2, |
c9775dde MR |
18189 | R_MIPS_PC21_S2, R_MIPS_PC16, R_MIPS16_PC16_S1, |
18190 | R_MICROMIPS_PC16_S1, R_MICROMIPS_PC10_S1 or R_MICROMIPS_PC7_S1) | |
18191 | against MIPS16 or microMIPS symbols because we need to keep the | |
18192 | MIPS16 or microMIPS symbol for the purpose of mode mismatch | |
a6ebf616 MR |
18193 | detection and JAL or BAL to JALX instruction conversion in the |
18194 | linker. | |
b314ec0e | 18195 | |
df58fc94 | 18196 | For simplicity, we deal with (3)-(4) by not reducing _any_ relocation |
507dcb32 | 18197 | against a MIPS16 symbol. We deal with (5) by additionally leaving |
0e9c5a5c | 18198 | alone any jump and branch relocations against a microMIPS symbol. |
b314ec0e RS |
18199 | |
18200 | We deal with (1)-(2) by saying that, if there's a R_MIPS16_26 | |
18201 | relocation against some symbol R, no relocation against R may be | |
18202 | reduced. (Note that this deals with (2) as well as (1) because | |
18203 | relocations against global symbols will never be reduced on ELF | |
18204 | targets.) This approach is a little simpler than trying to detect | |
18205 | stub sections, and gives the "all or nothing" per-symbol consistency | |
18206 | that we have for MIPS16 symbols. */ | |
f3ded42a | 18207 | if (fixp->fx_subsy == NULL |
30c09090 | 18208 | && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy)) |
44d3da23 | 18209 | || (ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy)) |
0e9c5a5c MR |
18210 | && (jmp_reloc_p (fixp->fx_r_type) |
18211 | || b_reloc_p (fixp->fx_r_type))) | |
44d3da23 | 18212 | || *symbol_get_tc (fixp->fx_addsy))) |
252b5132 | 18213 | return 0; |
a161fe53 | 18214 | |
252b5132 RH |
18215 | return 1; |
18216 | } | |
18217 | ||
18218 | /* Translate internal representation of relocation info to BFD target | |
18219 | format. */ | |
18220 | ||
18221 | arelent ** | |
17a2f251 | 18222 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
18223 | { |
18224 | static arelent *retval[4]; | |
18225 | arelent *reloc; | |
18226 | bfd_reloc_code_real_type code; | |
18227 | ||
4b0cff4e | 18228 | memset (retval, 0, sizeof(retval)); |
325801bd TS |
18229 | reloc = retval[0] = XCNEW (arelent); |
18230 | reloc->sym_ptr_ptr = XNEW (asymbol *); | |
49309057 | 18231 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
252b5132 RH |
18232 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
18233 | ||
bad36eac DJ |
18234 | if (fixp->fx_pcrel) |
18235 | { | |
df58fc94 | 18236 | gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 |
c9775dde | 18237 | || fixp->fx_r_type == BFD_RELOC_MIPS16_16_PCREL_S1 |
df58fc94 RS |
18238 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 |
18239 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
b47468a6 | 18240 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1 |
7361da2c AB |
18241 | || fixp->fx_r_type == BFD_RELOC_32_PCREL |
18242 | || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2 | |
18243 | || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2 | |
18244 | || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3 | |
18245 | || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2 | |
18246 | || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL | |
18247 | || fixp->fx_r_type == BFD_RELOC_LO16_PCREL); | |
bad36eac DJ |
18248 | |
18249 | /* At this point, fx_addnumber is "symbol offset - pcrel address". | |
18250 | Relocations want only the symbol offset. */ | |
51f6035b MR |
18251 | switch (fixp->fx_r_type) |
18252 | { | |
18253 | case BFD_RELOC_MIPS_18_PCREL_S3: | |
18254 | reloc->addend = fixp->fx_addnumber + (reloc->address & ~7); | |
18255 | break; | |
18256 | default: | |
18257 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
18258 | break; | |
18259 | } | |
bad36eac | 18260 | } |
17c6c9d9 MR |
18261 | else if (HAVE_IN_PLACE_ADDENDS |
18262 | && fixp->fx_r_type == BFD_RELOC_MICROMIPS_JMP | |
18263 | && (read_compressed_insn (fixp->fx_frag->fr_literal | |
18264 | + fixp->fx_where, 4) >> 26) == 0x3c) | |
18265 | { | |
18266 | /* Shift is 2, unusually, for microMIPS JALX. Adjust the in-place | |
18267 | addend accordingly. */ | |
18268 | reloc->addend = fixp->fx_addnumber >> 1; | |
18269 | } | |
bad36eac DJ |
18270 | else |
18271 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 18272 | |
438c16b8 TS |
18273 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
18274 | entry to be used in the relocation's section offset. */ | |
18275 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
18276 | { |
18277 | reloc->address = reloc->addend; | |
18278 | reloc->addend = 0; | |
18279 | } | |
18280 | ||
252b5132 | 18281 | code = fixp->fx_r_type; |
252b5132 | 18282 | |
bad36eac | 18283 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
252b5132 RH |
18284 | if (reloc->howto == NULL) |
18285 | { | |
18286 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
1661c76c RS |
18287 | _("cannot represent %s relocation in this object file" |
18288 | " format"), | |
252b5132 RH |
18289 | bfd_get_reloc_code_name (code)); |
18290 | retval[0] = NULL; | |
18291 | } | |
18292 | ||
18293 | return retval; | |
18294 | } | |
18295 | ||
18296 | /* Relax a machine dependent frag. This returns the amount by which | |
18297 | the current size of the frag should change. */ | |
18298 | ||
18299 | int | |
17a2f251 | 18300 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 18301 | { |
4a6a3df4 AO |
18302 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
18303 | { | |
18304 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
18305 | |
18306 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
18307 | |
18308 | return fragp->fr_var - old_var; | |
18309 | } | |
18310 | ||
df58fc94 RS |
18311 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
18312 | { | |
18313 | offsetT old_var = fragp->fr_var; | |
18314 | offsetT new_var = 4; | |
18315 | ||
18316 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
18317 | new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE); | |
18318 | if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
18319 | new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE); | |
18320 | fragp->fr_var = new_var; | |
18321 | ||
18322 | return new_var - old_var; | |
18323 | } | |
18324 | ||
252b5132 RH |
18325 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
18326 | return 0; | |
18327 | ||
8507b6e7 | 18328 | if (!mips16_extended_frag (fragp, sec, stretch)) |
252b5132 | 18329 | { |
8507b6e7 MR |
18330 | if (RELAX_MIPS16_MACRO (fragp->fr_subtype)) |
18331 | { | |
18332 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_MACRO (fragp->fr_subtype); | |
25499ac7 | 18333 | return RELAX_MIPS16_E2 (fragp->fr_subtype) ? -6 : -10; |
8507b6e7 MR |
18334 | } |
18335 | else if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
18336 | { | |
18337 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
18338 | return -2; | |
18339 | } | |
18340 | else | |
18341 | return 0; | |
18342 | } | |
18343 | else if (!mips16_macro_frag (fragp, sec, stretch)) | |
18344 | { | |
18345 | if (RELAX_MIPS16_MACRO (fragp->fr_subtype)) | |
18346 | { | |
18347 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_MACRO (fragp->fr_subtype); | |
18348 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
25499ac7 | 18349 | return RELAX_MIPS16_E2 (fragp->fr_subtype) ? -4 : -8; |
8507b6e7 MR |
18350 | } |
18351 | else if (!RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
18352 | { | |
18353 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
18354 | return 2; | |
18355 | } | |
18356 | else | |
252b5132 | 18357 | return 0; |
252b5132 RH |
18358 | } |
18359 | else | |
18360 | { | |
8507b6e7 | 18361 | if (RELAX_MIPS16_MACRO (fragp->fr_subtype)) |
252b5132 | 18362 | return 0; |
8507b6e7 MR |
18363 | else if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
18364 | { | |
18365 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
18366 | fragp->fr_subtype = RELAX_MIPS16_MARK_MACRO (fragp->fr_subtype); | |
25499ac7 | 18367 | return RELAX_MIPS16_E2 (fragp->fr_subtype) ? 4 : 8; |
8507b6e7 MR |
18368 | } |
18369 | else | |
18370 | { | |
18371 | fragp->fr_subtype = RELAX_MIPS16_MARK_MACRO (fragp->fr_subtype); | |
25499ac7 | 18372 | return RELAX_MIPS16_E2 (fragp->fr_subtype) ? 6 : 10; |
8507b6e7 | 18373 | } |
252b5132 RH |
18374 | } |
18375 | ||
18376 | return 0; | |
18377 | } | |
18378 | ||
18379 | /* Convert a machine dependent frag. */ | |
18380 | ||
18381 | void | |
17a2f251 | 18382 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 18383 | { |
4a6a3df4 AO |
18384 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
18385 | { | |
4d68580a | 18386 | char *buf; |
4a6a3df4 | 18387 | unsigned long insn; |
4a6a3df4 | 18388 | fixS *fixp; |
b34976b6 | 18389 | |
4d68580a RS |
18390 | buf = fragp->fr_literal + fragp->fr_fix; |
18391 | insn = read_insn (buf); | |
b34976b6 | 18392 | |
4a6a3df4 AO |
18393 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
18394 | { | |
18395 | /* We generate a fixup instead of applying it right now | |
18396 | because, if there are linker relaxations, we're going to | |
18397 | need the relocations. */ | |
bbd27b76 MR |
18398 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18399 | fragp->fr_symbol, fragp->fr_offset, | |
18400 | TRUE, BFD_RELOC_16_PCREL_S2); | |
4a6a3df4 AO |
18401 | fixp->fx_file = fragp->fr_file; |
18402 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 18403 | |
4d68580a | 18404 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18405 | } |
18406 | else | |
18407 | { | |
18408 | int i; | |
18409 | ||
18410 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
1661c76c | 18411 | _("relaxed out-of-range branch into a jump")); |
4a6a3df4 AO |
18412 | |
18413 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
18414 | goto uncond; | |
18415 | ||
18416 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18417 | { | |
18418 | /* Reverse the branch. */ | |
18419 | switch ((insn >> 28) & 0xf) | |
18420 | { | |
18421 | case 4: | |
56d438b1 CF |
18422 | if ((insn & 0xff000000) == 0x47000000 |
18423 | || (insn & 0xff600000) == 0x45600000) | |
18424 | { | |
18425 | /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition | |
18426 | reversed by tweaking bit 23. */ | |
18427 | insn ^= 0x00800000; | |
18428 | } | |
18429 | else | |
18430 | { | |
18431 | /* bc[0-3][tf]l? instructions can have the condition | |
18432 | reversed by tweaking a single TF bit, and their | |
18433 | opcodes all have 0x4???????. */ | |
18434 | gas_assert ((insn & 0xf3e00000) == 0x41000000); | |
18435 | insn ^= 0x00010000; | |
18436 | } | |
4a6a3df4 AO |
18437 | break; |
18438 | ||
18439 | case 0: | |
18440 | /* bltz 0x04000000 bgez 0x04010000 | |
54f4ddb3 | 18441 | bltzal 0x04100000 bgezal 0x04110000 */ |
9c2799c2 | 18442 | gas_assert ((insn & 0xfc0e0000) == 0x04000000); |
4a6a3df4 AO |
18443 | insn ^= 0x00010000; |
18444 | break; | |
b34976b6 | 18445 | |
4a6a3df4 AO |
18446 | case 1: |
18447 | /* beq 0x10000000 bne 0x14000000 | |
54f4ddb3 | 18448 | blez 0x18000000 bgtz 0x1c000000 */ |
4a6a3df4 AO |
18449 | insn ^= 0x04000000; |
18450 | break; | |
18451 | ||
18452 | default: | |
18453 | abort (); | |
18454 | } | |
18455 | } | |
18456 | ||
18457 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
18458 | { | |
18459 | /* Clear the and-link bit. */ | |
9c2799c2 | 18460 | gas_assert ((insn & 0xfc1c0000) == 0x04100000); |
4a6a3df4 | 18461 | |
54f4ddb3 TS |
18462 | /* bltzal 0x04100000 bgezal 0x04110000 |
18463 | bltzall 0x04120000 bgezall 0x04130000 */ | |
4a6a3df4 AO |
18464 | insn &= ~0x00100000; |
18465 | } | |
18466 | ||
18467 | /* Branch over the branch (if the branch was likely) or the | |
18468 | full jump (not likely case). Compute the offset from the | |
18469 | current instruction to branch to. */ | |
18470 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18471 | i = 16; | |
18472 | else | |
18473 | { | |
18474 | /* How many bytes in instructions we've already emitted? */ | |
4d68580a | 18475 | i = buf - fragp->fr_literal - fragp->fr_fix; |
4a6a3df4 AO |
18476 | /* How many bytes in instructions from here to the end? */ |
18477 | i = fragp->fr_var - i; | |
18478 | } | |
18479 | /* Convert to instruction count. */ | |
18480 | i >>= 2; | |
18481 | /* Branch counts from the next instruction. */ | |
b34976b6 | 18482 | i--; |
4a6a3df4 AO |
18483 | insn |= i; |
18484 | /* Branch over the jump. */ | |
4d68580a | 18485 | buf = write_insn (buf, insn); |
4a6a3df4 | 18486 | |
54f4ddb3 | 18487 | /* nop */ |
4d68580a | 18488 | buf = write_insn (buf, 0); |
4a6a3df4 AO |
18489 | |
18490 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18491 | { | |
18492 | /* beql $0, $0, 2f */ | |
18493 | insn = 0x50000000; | |
18494 | /* Compute the PC offset from the current instruction to | |
18495 | the end of the variable frag. */ | |
18496 | /* How many bytes in instructions we've already emitted? */ | |
4d68580a | 18497 | i = buf - fragp->fr_literal - fragp->fr_fix; |
4a6a3df4 AO |
18498 | /* How many bytes in instructions from here to the end? */ |
18499 | i = fragp->fr_var - i; | |
18500 | /* Convert to instruction count. */ | |
18501 | i >>= 2; | |
18502 | /* Don't decrement i, because we want to branch over the | |
18503 | delay slot. */ | |
4a6a3df4 | 18504 | insn |= i; |
4a6a3df4 | 18505 | |
4d68580a RS |
18506 | buf = write_insn (buf, insn); |
18507 | buf = write_insn (buf, 0); | |
4a6a3df4 AO |
18508 | } |
18509 | ||
18510 | uncond: | |
ce8ad872 | 18511 | if (!RELAX_BRANCH_PIC (fragp->fr_subtype)) |
4a6a3df4 AO |
18512 | { |
18513 | /* j or jal. */ | |
18514 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
18515 | ? 0x0c000000 : 0x08000000); | |
4a6a3df4 | 18516 | |
bbd27b76 MR |
18517 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18518 | fragp->fr_symbol, fragp->fr_offset, | |
18519 | FALSE, BFD_RELOC_MIPS_JMP); | |
4a6a3df4 AO |
18520 | fixp->fx_file = fragp->fr_file; |
18521 | fixp->fx_line = fragp->fr_line; | |
18522 | ||
4d68580a | 18523 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18524 | } |
18525 | else | |
18526 | { | |
66b3e8da MR |
18527 | unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype); |
18528 | ||
4a6a3df4 | 18529 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ |
66b3e8da MR |
18530 | insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000; |
18531 | insn |= at << OP_SH_RT; | |
4a6a3df4 | 18532 | |
bbd27b76 MR |
18533 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18534 | fragp->fr_symbol, fragp->fr_offset, | |
18535 | FALSE, BFD_RELOC_MIPS_GOT16); | |
4a6a3df4 AO |
18536 | fixp->fx_file = fragp->fr_file; |
18537 | fixp->fx_line = fragp->fr_line; | |
18538 | ||
4d68580a | 18539 | buf = write_insn (buf, insn); |
b34976b6 | 18540 | |
4a6a3df4 | 18541 | if (mips_opts.isa == ISA_MIPS1) |
4d68580a RS |
18542 | /* nop */ |
18543 | buf = write_insn (buf, 0); | |
4a6a3df4 AO |
18544 | |
18545 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
66b3e8da MR |
18546 | insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000; |
18547 | insn |= at << OP_SH_RS | at << OP_SH_RT; | |
4a6a3df4 | 18548 | |
bbd27b76 MR |
18549 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18550 | fragp->fr_symbol, fragp->fr_offset, | |
18551 | FALSE, BFD_RELOC_LO16); | |
4a6a3df4 AO |
18552 | fixp->fx_file = fragp->fr_file; |
18553 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 18554 | |
4d68580a | 18555 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18556 | |
18557 | /* j(al)r $at. */ | |
18558 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
66b3e8da | 18559 | insn = 0x0000f809; |
4a6a3df4 | 18560 | else |
66b3e8da MR |
18561 | insn = 0x00000008; |
18562 | insn |= at << OP_SH_RS; | |
4a6a3df4 | 18563 | |
4d68580a | 18564 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18565 | } |
18566 | } | |
18567 | ||
4a6a3df4 | 18568 | fragp->fr_fix += fragp->fr_var; |
4d68580a | 18569 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
4a6a3df4 AO |
18570 | return; |
18571 | } | |
18572 | ||
df58fc94 RS |
18573 | /* Relax microMIPS branches. */ |
18574 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) | |
18575 | { | |
4d68580a | 18576 | char *buf = fragp->fr_literal + fragp->fr_fix; |
df58fc94 | 18577 | bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); |
8484fb75 | 18578 | bfd_boolean insn32 = RELAX_MICROMIPS_INSN32 (fragp->fr_subtype); |
7bd374a4 | 18579 | bfd_boolean nods = RELAX_MICROMIPS_NODS (fragp->fr_subtype); |
ce8ad872 | 18580 | bfd_boolean pic = RELAX_MICROMIPS_PIC (fragp->fr_subtype); |
df58fc94 RS |
18581 | bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype); |
18582 | int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
2309ddf2 | 18583 | bfd_boolean short_ds; |
df58fc94 | 18584 | unsigned long insn; |
df58fc94 RS |
18585 | fixS *fixp; |
18586 | ||
df58fc94 RS |
18587 | fragp->fr_fix += fragp->fr_var; |
18588 | ||
18589 | /* Handle 16-bit branches that fit or are forced to fit. */ | |
18590 | if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
18591 | { | |
18592 | /* We generate a fixup instead of applying it right now, | |
18593 | because if there is linker relaxation, we're going to | |
18594 | need the relocations. */ | |
834a65aa MR |
18595 | switch (type) |
18596 | { | |
18597 | case 'D': | |
18598 | fixp = fix_new (fragp, buf - fragp->fr_literal, 2, | |
18599 | fragp->fr_symbol, fragp->fr_offset, | |
18600 | TRUE, BFD_RELOC_MICROMIPS_10_PCREL_S1); | |
18601 | break; | |
18602 | case 'E': | |
18603 | fixp = fix_new (fragp, buf - fragp->fr_literal, 2, | |
18604 | fragp->fr_symbol, fragp->fr_offset, | |
18605 | TRUE, BFD_RELOC_MICROMIPS_7_PCREL_S1); | |
18606 | break; | |
18607 | default: | |
18608 | abort (); | |
18609 | } | |
df58fc94 RS |
18610 | |
18611 | fixp->fx_file = fragp->fr_file; | |
18612 | fixp->fx_line = fragp->fr_line; | |
18613 | ||
18614 | /* These relocations can have an addend that won't fit in | |
18615 | 2 octets. */ | |
18616 | fixp->fx_no_overflow = 1; | |
18617 | ||
18618 | return; | |
18619 | } | |
18620 | ||
2309ddf2 | 18621 | /* Handle 32-bit branches that fit or are forced to fit. */ |
df58fc94 RS |
18622 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) |
18623 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
18624 | { | |
18625 | /* We generate a fixup instead of applying it right now, | |
18626 | because if there is linker relaxation, we're going to | |
18627 | need the relocations. */ | |
bbd27b76 MR |
18628 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18629 | fragp->fr_symbol, fragp->fr_offset, | |
18630 | TRUE, BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
df58fc94 RS |
18631 | fixp->fx_file = fragp->fr_file; |
18632 | fixp->fx_line = fragp->fr_line; | |
18633 | ||
18634 | if (type == 0) | |
7bd374a4 MR |
18635 | { |
18636 | insn = read_compressed_insn (buf, 4); | |
18637 | buf += 4; | |
18638 | ||
18639 | if (nods) | |
18640 | { | |
18641 | /* Check the short-delay-slot bit. */ | |
18642 | if (!al || (insn & 0x02000000) != 0) | |
18643 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
18644 | else | |
18645 | buf = write_compressed_insn (buf, 0x00000000, 4); | |
18646 | } | |
18647 | ||
18648 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); | |
18649 | return; | |
18650 | } | |
df58fc94 RS |
18651 | } |
18652 | ||
18653 | /* Relax 16-bit branches to 32-bit branches. */ | |
18654 | if (type != 0) | |
18655 | { | |
4d68580a | 18656 | insn = read_compressed_insn (buf, 2); |
df58fc94 RS |
18657 | |
18658 | if ((insn & 0xfc00) == 0xcc00) /* b16 */ | |
18659 | insn = 0x94000000; /* beq */ | |
18660 | else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */ | |
18661 | { | |
18662 | unsigned long regno; | |
18663 | ||
18664 | regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD; | |
18665 | regno = micromips_to_32_reg_d_map [regno]; | |
18666 | insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */ | |
18667 | insn |= regno << MICROMIPSOP_SH_RS; | |
18668 | } | |
18669 | else | |
18670 | abort (); | |
18671 | ||
18672 | /* Nothing else to do, just write it out. */ | |
18673 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) | |
18674 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
18675 | { | |
4d68580a | 18676 | buf = write_compressed_insn (buf, insn, 4); |
7bd374a4 MR |
18677 | if (nods) |
18678 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
4d68580a | 18679 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
df58fc94 RS |
18680 | return; |
18681 | } | |
18682 | } | |
18683 | else | |
4d68580a | 18684 | insn = read_compressed_insn (buf, 4); |
df58fc94 RS |
18685 | |
18686 | /* Relax 32-bit branches to a sequence of instructions. */ | |
18687 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
1661c76c | 18688 | _("relaxed out-of-range branch into a jump")); |
df58fc94 | 18689 | |
2309ddf2 | 18690 | /* Set the short-delay-slot bit. */ |
7bd374a4 | 18691 | short_ds = !al || (insn & 0x02000000) != 0; |
df58fc94 RS |
18692 | |
18693 | if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype)) | |
18694 | { | |
18695 | symbolS *l; | |
18696 | ||
18697 | /* Reverse the branch. */ | |
18698 | if ((insn & 0xfc000000) == 0x94000000 /* beq */ | |
18699 | || (insn & 0xfc000000) == 0xb4000000) /* bne */ | |
18700 | insn ^= 0x20000000; | |
18701 | else if ((insn & 0xffe00000) == 0x40000000 /* bltz */ | |
18702 | || (insn & 0xffe00000) == 0x40400000 /* bgez */ | |
18703 | || (insn & 0xffe00000) == 0x40800000 /* blez */ | |
18704 | || (insn & 0xffe00000) == 0x40c00000 /* bgtz */ | |
18705 | || (insn & 0xffe00000) == 0x40a00000 /* bnezc */ | |
18706 | || (insn & 0xffe00000) == 0x40e00000 /* beqzc */ | |
18707 | || (insn & 0xffe00000) == 0x40200000 /* bltzal */ | |
18708 | || (insn & 0xffe00000) == 0x40600000 /* bgezal */ | |
18709 | || (insn & 0xffe00000) == 0x42200000 /* bltzals */ | |
18710 | || (insn & 0xffe00000) == 0x42600000) /* bgezals */ | |
18711 | insn ^= 0x00400000; | |
18712 | else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */ | |
18713 | || (insn & 0xffe30000) == 0x43a00000 /* bc1t */ | |
18714 | || (insn & 0xffe30000) == 0x42800000 /* bc2f */ | |
18715 | || (insn & 0xffe30000) == 0x42a00000) /* bc2t */ | |
18716 | insn ^= 0x00200000; | |
56d438b1 CF |
18717 | else if ((insn & 0xff000000) == 0x83000000 /* BZ.df |
18718 | BNZ.df */ | |
18719 | || (insn & 0xff600000) == 0x81600000) /* BZ.V | |
18720 | BNZ.V */ | |
18721 | insn ^= 0x00800000; | |
df58fc94 RS |
18722 | else |
18723 | abort (); | |
18724 | ||
18725 | if (al) | |
18726 | { | |
18727 | /* Clear the and-link and short-delay-slot bits. */ | |
18728 | gas_assert ((insn & 0xfda00000) == 0x40200000); | |
18729 | ||
18730 | /* bltzal 0x40200000 bgezal 0x40600000 */ | |
18731 | /* bltzals 0x42200000 bgezals 0x42600000 */ | |
18732 | insn &= ~0x02200000; | |
18733 | } | |
18734 | ||
18735 | /* Make a label at the end for use with the branch. */ | |
18736 | l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp); | |
18737 | micromips_label_inc (); | |
f3ded42a | 18738 | S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l))); |
df58fc94 RS |
18739 | |
18740 | /* Refer to it. */ | |
4d68580a RS |
18741 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE, |
18742 | BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
df58fc94 RS |
18743 | fixp->fx_file = fragp->fr_file; |
18744 | fixp->fx_line = fragp->fr_line; | |
18745 | ||
18746 | /* Branch over the jump. */ | |
4d68580a | 18747 | buf = write_compressed_insn (buf, insn, 4); |
8484fb75 | 18748 | |
df58fc94 | 18749 | if (!compact) |
8484fb75 MR |
18750 | { |
18751 | /* nop */ | |
18752 | if (insn32) | |
18753 | buf = write_compressed_insn (buf, 0x00000000, 4); | |
18754 | else | |
18755 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
18756 | } | |
df58fc94 RS |
18757 | } |
18758 | ||
ce8ad872 | 18759 | if (!pic) |
df58fc94 | 18760 | { |
7bd374a4 MR |
18761 | unsigned long jal = (short_ds || nods |
18762 | ? 0x74000000 : 0xf4000000); /* jal/s */ | |
2309ddf2 | 18763 | |
df58fc94 RS |
18764 | /* j/jal/jals <sym> R_MICROMIPS_26_S1 */ |
18765 | insn = al ? jal : 0xd4000000; | |
18766 | ||
bbd27b76 MR |
18767 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18768 | fragp->fr_symbol, fragp->fr_offset, | |
18769 | FALSE, BFD_RELOC_MICROMIPS_JMP); | |
df58fc94 RS |
18770 | fixp->fx_file = fragp->fr_file; |
18771 | fixp->fx_line = fragp->fr_line; | |
18772 | ||
4d68580a | 18773 | buf = write_compressed_insn (buf, insn, 4); |
8484fb75 | 18774 | |
7bd374a4 | 18775 | if (compact || nods) |
8484fb75 MR |
18776 | { |
18777 | /* nop */ | |
18778 | if (insn32) | |
18779 | buf = write_compressed_insn (buf, 0x00000000, 4); | |
18780 | else | |
18781 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
18782 | } | |
df58fc94 RS |
18783 | } |
18784 | else | |
18785 | { | |
18786 | unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype); | |
18787 | ||
18788 | /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */ | |
18789 | insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000; | |
18790 | insn |= at << MICROMIPSOP_SH_RT; | |
18791 | ||
bbd27b76 MR |
18792 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18793 | fragp->fr_symbol, fragp->fr_offset, | |
18794 | FALSE, BFD_RELOC_MICROMIPS_GOT16); | |
df58fc94 RS |
18795 | fixp->fx_file = fragp->fr_file; |
18796 | fixp->fx_line = fragp->fr_line; | |
18797 | ||
4d68580a | 18798 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 RS |
18799 | |
18800 | /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */ | |
18801 | insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000; | |
18802 | insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS; | |
18803 | ||
bbd27b76 MR |
18804 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18805 | fragp->fr_symbol, fragp->fr_offset, | |
18806 | FALSE, BFD_RELOC_MICROMIPS_LO16); | |
df58fc94 RS |
18807 | fixp->fx_file = fragp->fr_file; |
18808 | fixp->fx_line = fragp->fr_line; | |
18809 | ||
4d68580a | 18810 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 | 18811 | |
8484fb75 MR |
18812 | if (insn32) |
18813 | { | |
18814 | /* jr/jalr $at */ | |
18815 | insn = 0x00000f3c | (al ? RA : ZERO) << MICROMIPSOP_SH_RT; | |
18816 | insn |= at << MICROMIPSOP_SH_RS; | |
18817 | ||
18818 | buf = write_compressed_insn (buf, insn, 4); | |
df58fc94 | 18819 | |
7bd374a4 | 18820 | if (compact || nods) |
8484fb75 MR |
18821 | /* nop */ |
18822 | buf = write_compressed_insn (buf, 0x00000000, 4); | |
18823 | } | |
18824 | else | |
18825 | { | |
18826 | /* jr/jrc/jalr/jalrs $at */ | |
18827 | unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */ | |
7bd374a4 | 18828 | unsigned long jr = compact || nods ? 0x45a0 : 0x4580; /* jr/c */ |
8484fb75 MR |
18829 | |
18830 | insn = al ? jalr : jr; | |
18831 | insn |= at << MICROMIPSOP_SH_MJ; | |
18832 | ||
18833 | buf = write_compressed_insn (buf, insn, 2); | |
7bd374a4 MR |
18834 | if (al && nods) |
18835 | { | |
18836 | /* nop */ | |
18837 | if (short_ds) | |
18838 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
18839 | else | |
18840 | buf = write_compressed_insn (buf, 0x00000000, 4); | |
18841 | } | |
8484fb75 | 18842 | } |
df58fc94 RS |
18843 | } |
18844 | ||
4d68580a | 18845 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
df58fc94 RS |
18846 | return; |
18847 | } | |
18848 | ||
252b5132 RH |
18849 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
18850 | { | |
18851 | int type; | |
3ccad066 | 18852 | const struct mips_int_operand *operand; |
252b5132 | 18853 | offsetT val; |
5c04167a | 18854 | char *buf; |
8507b6e7 | 18855 | unsigned int user_length; |
9d862524 | 18856 | bfd_boolean need_reloc; |
252b5132 | 18857 | unsigned long insn; |
8507b6e7 | 18858 | bfd_boolean mac; |
5c04167a | 18859 | bfd_boolean ext; |
88a7ef16 | 18860 | segT symsec; |
252b5132 RH |
18861 | |
18862 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
3ccad066 | 18863 | operand = mips16_immed_operand (type, FALSE); |
252b5132 | 18864 | |
8507b6e7 | 18865 | mac = RELAX_MIPS16_MACRO (fragp->fr_subtype); |
5c04167a | 18866 | ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype); |
88a7ef16 | 18867 | val = resolve_symbol_value (fragp->fr_symbol) + fragp->fr_offset; |
9d862524 MR |
18868 | |
18869 | symsec = S_GET_SEGMENT (fragp->fr_symbol); | |
18870 | need_reloc = (S_FORCE_RELOC (fragp->fr_symbol, TRUE) | |
8507b6e7 | 18871 | || (operand->root.type == OP_PCREL && !mac |
9d862524 MR |
18872 | ? asec != symsec |
18873 | : !bfd_is_abs_section (symsec))); | |
18874 | ||
8507b6e7 | 18875 | if (operand->root.type == OP_PCREL && !mac) |
252b5132 | 18876 | { |
3ccad066 | 18877 | const struct mips_pcrel_operand *pcrel_op; |
252b5132 | 18878 | |
3ccad066 | 18879 | pcrel_op = (const struct mips_pcrel_operand *) operand; |
252b5132 | 18880 | |
14f72d45 | 18881 | if (pcrel_op->include_isa_bit && !need_reloc) |
252b5132 | 18882 | { |
37b2d327 MR |
18883 | if (!mips_ignore_branch_isa |
18884 | && !ELF_ST_IS_MIPS16 (S_GET_OTHER (fragp->fr_symbol))) | |
14f72d45 MR |
18885 | as_bad_where (fragp->fr_file, fragp->fr_line, |
18886 | _("branch to a symbol in another ISA mode")); | |
18887 | else if ((fragp->fr_offset & 0x1) != 0) | |
18888 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
18889 | _("branch to misaligned address (0x%lx)"), | |
18890 | (long) val); | |
252b5132 | 18891 | } |
252b5132 | 18892 | |
14f72d45 | 18893 | val = mips16_pcrel_val (fragp, pcrel_op, val, 0); |
252b5132 RH |
18894 | |
18895 | /* Make sure the section winds up with the alignment we have | |
18896 | assumed. */ | |
3ccad066 RS |
18897 | if (operand->shift > 0) |
18898 | record_alignment (asec, operand->shift); | |
252b5132 RH |
18899 | } |
18900 | ||
8507b6e7 MR |
18901 | if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) |
18902 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
18903 | { | |
18904 | if (mac) | |
18905 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
18906 | _("macro instruction expanded into multiple " | |
18907 | "instructions in a branch delay slot")); | |
18908 | else if (ext) | |
18909 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
18910 | _("extended instruction in a branch delay slot")); | |
18911 | } | |
18912 | else if (RELAX_MIPS16_NOMACRO (fragp->fr_subtype) && mac) | |
252b5132 | 18913 | as_warn_where (fragp->fr_file, fragp->fr_line, |
8507b6e7 MR |
18914 | _("macro instruction expanded into multiple " |
18915 | "instructions")); | |
252b5132 | 18916 | |
5c04167a | 18917 | buf = fragp->fr_literal + fragp->fr_fix; |
252b5132 | 18918 | |
4d68580a | 18919 | insn = read_compressed_insn (buf, 2); |
5c04167a RS |
18920 | if (ext) |
18921 | insn |= MIPS16_EXTEND; | |
252b5132 | 18922 | |
5c04167a RS |
18923 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) |
18924 | user_length = 4; | |
18925 | else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
18926 | user_length = 2; | |
18927 | else | |
18928 | user_length = 0; | |
18929 | ||
8507b6e7 | 18930 | if (mac) |
c9775dde | 18931 | { |
8507b6e7 MR |
18932 | unsigned long reg; |
18933 | unsigned long new; | |
18934 | unsigned long op; | |
25499ac7 | 18935 | bfd_boolean e2; |
8507b6e7 MR |
18936 | |
18937 | gas_assert (type == 'A' || type == 'B' || type == 'E'); | |
18938 | gas_assert (RELAX_MIPS16_SYM32 (fragp->fr_subtype)); | |
c9775dde | 18939 | |
25499ac7 MR |
18940 | e2 = RELAX_MIPS16_E2 (fragp->fr_subtype); |
18941 | ||
8507b6e7 | 18942 | if (need_reloc) |
c9775dde | 18943 | { |
8507b6e7 MR |
18944 | fixS *fixp; |
18945 | ||
18946 | gas_assert (!RELAX_MIPS16_PIC (fragp->fr_subtype)); | |
18947 | ||
18948 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, | |
18949 | fragp->fr_symbol, fragp->fr_offset, | |
18950 | FALSE, BFD_RELOC_MIPS16_HI16_S); | |
18951 | fixp->fx_file = fragp->fr_file; | |
18952 | fixp->fx_line = fragp->fr_line; | |
18953 | ||
25499ac7 | 18954 | fixp = fix_new (fragp, buf - fragp->fr_literal + (e2 ? 4 : 8), 4, |
8507b6e7 MR |
18955 | fragp->fr_symbol, fragp->fr_offset, |
18956 | FALSE, BFD_RELOC_MIPS16_LO16); | |
18957 | fixp->fx_file = fragp->fr_file; | |
18958 | fixp->fx_line = fragp->fr_line; | |
18959 | ||
18960 | val = 0; | |
18961 | } | |
18962 | ||
18963 | switch (insn & 0xf800) | |
18964 | { | |
18965 | case 0x0800: /* ADDIU */ | |
18966 | reg = (insn >> 8) & 0x7; | |
18967 | op = 0xf0004800 | (reg << 8); | |
c9775dde | 18968 | break; |
8507b6e7 MR |
18969 | case 0xb000: /* LW */ |
18970 | reg = (insn >> 8) & 0x7; | |
18971 | op = 0xf0009800 | (reg << 8) | (reg << 5); | |
c9775dde | 18972 | break; |
8507b6e7 MR |
18973 | case 0xf800: /* I64 */ |
18974 | reg = (insn >> 5) & 0x7; | |
18975 | switch (insn & 0x0700) | |
18976 | { | |
18977 | case 0x0400: /* LD */ | |
18978 | op = 0xf0003800 | (reg << 8) | (reg << 5); | |
18979 | break; | |
18980 | case 0x0600: /* DADDIU */ | |
18981 | op = 0xf000fd00 | (reg << 5); | |
18982 | break; | |
18983 | default: | |
18984 | abort (); | |
18985 | } | |
18986 | break; | |
18987 | default: | |
18988 | abort (); | |
c9775dde | 18989 | } |
8507b6e7 | 18990 | |
25499ac7 | 18991 | new = (e2 ? 0xf0006820 : 0xf0006800) | (reg << 8); /* LUI/LI */ |
8507b6e7 MR |
18992 | new |= mips16_immed_extend ((val + 0x8000) >> 16, 16); |
18993 | buf = write_compressed_insn (buf, new, 4); | |
25499ac7 MR |
18994 | if (!e2) |
18995 | { | |
18996 | new = 0xf4003000 | (reg << 8) | (reg << 5); /* SLL */ | |
18997 | buf = write_compressed_insn (buf, new, 4); | |
18998 | } | |
8507b6e7 MR |
18999 | op |= mips16_immed_extend (val, 16); |
19000 | buf = write_compressed_insn (buf, op, 4); | |
19001 | ||
25499ac7 | 19002 | fragp->fr_fix += e2 ? 8 : 12; |
8507b6e7 MR |
19003 | } |
19004 | else | |
19005 | { | |
19006 | unsigned int length = ext ? 4 : 2; | |
19007 | ||
19008 | if (need_reloc) | |
c9775dde | 19009 | { |
8507b6e7 | 19010 | bfd_reloc_code_real_type reloc = BFD_RELOC_NONE; |
8507b6e7 | 19011 | fixS *fixp; |
c9775dde | 19012 | |
8507b6e7 MR |
19013 | switch (type) |
19014 | { | |
19015 | case 'p': | |
19016 | case 'q': | |
19017 | reloc = BFD_RELOC_MIPS16_16_PCREL_S1; | |
19018 | break; | |
19019 | default: | |
19020 | break; | |
19021 | } | |
19022 | if (mac || reloc == BFD_RELOC_NONE) | |
19023 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
19024 | _("unsupported relocation")); | |
19025 | else if (ext) | |
19026 | { | |
bbd27b76 MR |
19027 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
19028 | fragp->fr_symbol, fragp->fr_offset, | |
19029 | TRUE, reloc); | |
8507b6e7 MR |
19030 | fixp->fx_file = fragp->fr_file; |
19031 | fixp->fx_line = fragp->fr_line; | |
19032 | } | |
19033 | else | |
19034 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
19035 | _("invalid unextended operand value")); | |
c9775dde | 19036 | } |
eefc3365 | 19037 | else |
8507b6e7 MR |
19038 | mips16_immed (fragp->fr_file, fragp->fr_line, type, |
19039 | BFD_RELOC_UNUSED, val, user_length, &insn); | |
252b5132 | 19040 | |
8507b6e7 MR |
19041 | gas_assert (mips16_opcode_length (insn) == length); |
19042 | write_compressed_insn (buf, insn, length); | |
19043 | fragp->fr_fix += length; | |
19044 | } | |
252b5132 RH |
19045 | } |
19046 | else | |
19047 | { | |
df58fc94 RS |
19048 | relax_substateT subtype = fragp->fr_subtype; |
19049 | bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0; | |
19050 | bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0; | |
4d7206a2 RS |
19051 | int first, second; |
19052 | fixS *fixp; | |
252b5132 | 19053 | |
df58fc94 RS |
19054 | first = RELAX_FIRST (subtype); |
19055 | second = RELAX_SECOND (subtype); | |
4d7206a2 | 19056 | fixp = (fixS *) fragp->fr_opcode; |
252b5132 | 19057 | |
df58fc94 RS |
19058 | /* If the delay slot chosen does not match the size of the instruction, |
19059 | then emit a warning. */ | |
19060 | if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0) | |
19061 | || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)) | |
19062 | { | |
19063 | relax_substateT s; | |
19064 | const char *msg; | |
19065 | ||
19066 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
19067 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
19068 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
19069 | msg = macro_warning (s); | |
19070 | if (msg != NULL) | |
db9b2be4 | 19071 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
df58fc94 RS |
19072 | subtype &= ~s; |
19073 | } | |
19074 | ||
584892a6 | 19075 | /* Possibly emit a warning if we've chosen the longer option. */ |
df58fc94 | 19076 | if (use_second == second_longer) |
584892a6 | 19077 | { |
df58fc94 RS |
19078 | relax_substateT s; |
19079 | const char *msg; | |
19080 | ||
19081 | s = (subtype | |
19082 | & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT)); | |
19083 | msg = macro_warning (s); | |
19084 | if (msg != NULL) | |
db9b2be4 | 19085 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
df58fc94 | 19086 | subtype &= ~s; |
584892a6 RS |
19087 | } |
19088 | ||
4d7206a2 RS |
19089 | /* Go through all the fixups for the first sequence. Disable them |
19090 | (by marking them as done) if we're going to use the second | |
19091 | sequence instead. */ | |
19092 | while (fixp | |
19093 | && fixp->fx_frag == fragp | |
19094 | && fixp->fx_where < fragp->fr_fix - second) | |
19095 | { | |
df58fc94 | 19096 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
19097 | fixp->fx_done = 1; |
19098 | fixp = fixp->fx_next; | |
19099 | } | |
252b5132 | 19100 | |
4d7206a2 RS |
19101 | /* Go through the fixups for the second sequence. Disable them if |
19102 | we're going to use the first sequence, otherwise adjust their | |
19103 | addresses to account for the relaxation. */ | |
19104 | while (fixp && fixp->fx_frag == fragp) | |
19105 | { | |
df58fc94 | 19106 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
19107 | fixp->fx_where -= first; |
19108 | else | |
19109 | fixp->fx_done = 1; | |
19110 | fixp = fixp->fx_next; | |
19111 | } | |
19112 | ||
19113 | /* Now modify the frag contents. */ | |
df58fc94 | 19114 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
19115 | { |
19116 | char *start; | |
19117 | ||
19118 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
19119 | memmove (start, start + first, second); | |
19120 | fragp->fr_fix -= first; | |
19121 | } | |
19122 | else | |
19123 | fragp->fr_fix -= second; | |
252b5132 RH |
19124 | } |
19125 | } | |
19126 | ||
252b5132 RH |
19127 | /* This function is called after the relocs have been generated. |
19128 | We've been storing mips16 text labels as odd. Here we convert them | |
19129 | back to even for the convenience of the debugger. */ | |
19130 | ||
19131 | void | |
17a2f251 | 19132 | mips_frob_file_after_relocs (void) |
252b5132 RH |
19133 | { |
19134 | asymbol **syms; | |
19135 | unsigned int count, i; | |
19136 | ||
252b5132 RH |
19137 | syms = bfd_get_outsymbols (stdoutput); |
19138 | count = bfd_get_symcount (stdoutput); | |
19139 | for (i = 0; i < count; i++, syms++) | |
df58fc94 RS |
19140 | if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other) |
19141 | && ((*syms)->value & 1) != 0) | |
19142 | { | |
19143 | (*syms)->value &= ~1; | |
19144 | /* If the symbol has an odd size, it was probably computed | |
19145 | incorrectly, so adjust that as well. */ | |
19146 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
19147 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
19148 | } | |
252b5132 RH |
19149 | } |
19150 | ||
a1facbec MR |
19151 | /* This function is called whenever a label is defined, including fake |
19152 | labels instantiated off the dot special symbol. It is used when | |
19153 | handling branch delays; if a branch has a label, we assume we cannot | |
19154 | move it. This also bumps the value of the symbol by 1 in compressed | |
19155 | code. */ | |
252b5132 | 19156 | |
e1b47bd5 | 19157 | static void |
a1facbec | 19158 | mips_record_label (symbolS *sym) |
252b5132 | 19159 | { |
a8dbcb85 | 19160 | segment_info_type *si = seg_info (now_seg); |
252b5132 RH |
19161 | struct insn_label_list *l; |
19162 | ||
19163 | if (free_insn_labels == NULL) | |
325801bd | 19164 | l = XNEW (struct insn_label_list); |
252b5132 RH |
19165 | else |
19166 | { | |
19167 | l = free_insn_labels; | |
19168 | free_insn_labels = l->next; | |
19169 | } | |
19170 | ||
19171 | l->label = sym; | |
a8dbcb85 TS |
19172 | l->next = si->label_list; |
19173 | si->label_list = l; | |
a1facbec | 19174 | } |
07a53e5c | 19175 | |
a1facbec MR |
19176 | /* This function is called as tc_frob_label() whenever a label is defined |
19177 | and adds a DWARF-2 record we only want for true labels. */ | |
19178 | ||
19179 | void | |
19180 | mips_define_label (symbolS *sym) | |
19181 | { | |
19182 | mips_record_label (sym); | |
07a53e5c | 19183 | dwarf2_emit_label (sym); |
252b5132 | 19184 | } |
e1b47bd5 RS |
19185 | |
19186 | /* This function is called by tc_new_dot_label whenever a new dot symbol | |
19187 | is defined. */ | |
19188 | ||
19189 | void | |
19190 | mips_add_dot_label (symbolS *sym) | |
19191 | { | |
19192 | mips_record_label (sym); | |
19193 | if (mips_assembling_insn && HAVE_CODE_COMPRESSION) | |
19194 | mips_compressed_mark_label (sym); | |
19195 | } | |
252b5132 | 19196 | \f |
351cdf24 MF |
19197 | /* Converting ASE flags from internal to .MIPS.abiflags values. */ |
19198 | static unsigned int | |
19199 | mips_convert_ase_flags (int ase) | |
19200 | { | |
19201 | unsigned int ext_ases = 0; | |
19202 | ||
19203 | if (ase & ASE_DSP) | |
19204 | ext_ases |= AFL_ASE_DSP; | |
19205 | if (ase & ASE_DSPR2) | |
19206 | ext_ases |= AFL_ASE_DSPR2; | |
8f4f9071 MF |
19207 | if (ase & ASE_DSPR3) |
19208 | ext_ases |= AFL_ASE_DSPR3; | |
351cdf24 MF |
19209 | if (ase & ASE_EVA) |
19210 | ext_ases |= AFL_ASE_EVA; | |
19211 | if (ase & ASE_MCU) | |
19212 | ext_ases |= AFL_ASE_MCU; | |
19213 | if (ase & ASE_MDMX) | |
19214 | ext_ases |= AFL_ASE_MDMX; | |
19215 | if (ase & ASE_MIPS3D) | |
19216 | ext_ases |= AFL_ASE_MIPS3D; | |
19217 | if (ase & ASE_MT) | |
19218 | ext_ases |= AFL_ASE_MT; | |
19219 | if (ase & ASE_SMARTMIPS) | |
19220 | ext_ases |= AFL_ASE_SMARTMIPS; | |
19221 | if (ase & ASE_VIRT) | |
19222 | ext_ases |= AFL_ASE_VIRT; | |
19223 | if (ase & ASE_MSA) | |
19224 | ext_ases |= AFL_ASE_MSA; | |
19225 | if (ase & ASE_XPA) | |
19226 | ext_ases |= AFL_ASE_XPA; | |
25499ac7 MR |
19227 | if (ase & ASE_MIPS16E2) |
19228 | ext_ases |= file_ase_mips16 ? AFL_ASE_MIPS16E2 : 0; | |
730c3174 SE |
19229 | if (ase & ASE_CRC) |
19230 | ext_ases |= AFL_ASE_CRC; | |
6f20c942 FS |
19231 | if (ase & ASE_GINV) |
19232 | ext_ases |= AFL_ASE_GINV; | |
8095d2f7 CX |
19233 | if (ase & ASE_LOONGSON_MMI) |
19234 | ext_ases |= AFL_ASE_LOONGSON_MMI; | |
716c08de CX |
19235 | if (ase & ASE_LOONGSON_CAM) |
19236 | ext_ases |= AFL_ASE_LOONGSON_CAM; | |
bdc6c06e CX |
19237 | if (ase & ASE_LOONGSON_EXT) |
19238 | ext_ases |= AFL_ASE_LOONGSON_EXT; | |
a693765e CX |
19239 | if (ase & ASE_LOONGSON_EXT2) |
19240 | ext_ases |= AFL_ASE_LOONGSON_EXT2; | |
351cdf24 MF |
19241 | |
19242 | return ext_ases; | |
19243 | } | |
252b5132 RH |
19244 | /* Some special processing for a MIPS ELF file. */ |
19245 | ||
19246 | void | |
17a2f251 | 19247 | mips_elf_final_processing (void) |
252b5132 | 19248 | { |
351cdf24 MF |
19249 | int fpabi; |
19250 | Elf_Internal_ABIFlags_v0 flags; | |
19251 | ||
19252 | flags.version = 0; | |
19253 | flags.isa_rev = 0; | |
19254 | switch (file_mips_opts.isa) | |
19255 | { | |
19256 | case INSN_ISA1: | |
19257 | flags.isa_level = 1; | |
19258 | break; | |
19259 | case INSN_ISA2: | |
19260 | flags.isa_level = 2; | |
19261 | break; | |
19262 | case INSN_ISA3: | |
19263 | flags.isa_level = 3; | |
19264 | break; | |
19265 | case INSN_ISA4: | |
19266 | flags.isa_level = 4; | |
19267 | break; | |
19268 | case INSN_ISA5: | |
19269 | flags.isa_level = 5; | |
19270 | break; | |
19271 | case INSN_ISA32: | |
19272 | flags.isa_level = 32; | |
19273 | flags.isa_rev = 1; | |
19274 | break; | |
19275 | case INSN_ISA32R2: | |
19276 | flags.isa_level = 32; | |
19277 | flags.isa_rev = 2; | |
19278 | break; | |
19279 | case INSN_ISA32R3: | |
19280 | flags.isa_level = 32; | |
19281 | flags.isa_rev = 3; | |
19282 | break; | |
19283 | case INSN_ISA32R5: | |
19284 | flags.isa_level = 32; | |
19285 | flags.isa_rev = 5; | |
19286 | break; | |
09c14161 MF |
19287 | case INSN_ISA32R6: |
19288 | flags.isa_level = 32; | |
19289 | flags.isa_rev = 6; | |
19290 | break; | |
351cdf24 MF |
19291 | case INSN_ISA64: |
19292 | flags.isa_level = 64; | |
19293 | flags.isa_rev = 1; | |
19294 | break; | |
19295 | case INSN_ISA64R2: | |
19296 | flags.isa_level = 64; | |
19297 | flags.isa_rev = 2; | |
19298 | break; | |
19299 | case INSN_ISA64R3: | |
19300 | flags.isa_level = 64; | |
19301 | flags.isa_rev = 3; | |
19302 | break; | |
19303 | case INSN_ISA64R5: | |
19304 | flags.isa_level = 64; | |
19305 | flags.isa_rev = 5; | |
19306 | break; | |
09c14161 MF |
19307 | case INSN_ISA64R6: |
19308 | flags.isa_level = 64; | |
19309 | flags.isa_rev = 6; | |
19310 | break; | |
351cdf24 MF |
19311 | } |
19312 | ||
19313 | flags.gpr_size = file_mips_opts.gp == 32 ? AFL_REG_32 : AFL_REG_64; | |
19314 | flags.cpr1_size = file_mips_opts.soft_float ? AFL_REG_NONE | |
19315 | : (file_mips_opts.ase & ASE_MSA) ? AFL_REG_128 | |
19316 | : (file_mips_opts.fp == 64) ? AFL_REG_64 | |
19317 | : AFL_REG_32; | |
19318 | flags.cpr2_size = AFL_REG_NONE; | |
19319 | flags.fp_abi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, | |
19320 | Tag_GNU_MIPS_ABI_FP); | |
19321 | flags.isa_ext = bfd_mips_isa_ext (stdoutput); | |
19322 | flags.ases = mips_convert_ase_flags (file_mips_opts.ase); | |
19323 | if (file_ase_mips16) | |
19324 | flags.ases |= AFL_ASE_MIPS16; | |
19325 | if (file_ase_micromips) | |
19326 | flags.ases |= AFL_ASE_MICROMIPS; | |
19327 | flags.flags1 = 0; | |
19328 | if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts.isa, file_mips_opts.arch) | |
19329 | || file_mips_opts.fp == 64) | |
19330 | && file_mips_opts.oddspreg) | |
19331 | flags.flags1 |= AFL_FLAGS1_ODDSPREG; | |
19332 | flags.flags2 = 0; | |
19333 | ||
19334 | bfd_mips_elf_swap_abiflags_v0_out (stdoutput, &flags, | |
19335 | ((Elf_External_ABIFlags_v0 *) | |
19336 | mips_flags_frag)); | |
19337 | ||
252b5132 | 19338 | /* Write out the register information. */ |
316f5878 | 19339 | if (mips_abi != N64_ABI) |
252b5132 RH |
19340 | { |
19341 | Elf32_RegInfo s; | |
19342 | ||
19343 | s.ri_gprmask = mips_gprmask; | |
19344 | s.ri_cprmask[0] = mips_cprmask[0]; | |
19345 | s.ri_cprmask[1] = mips_cprmask[1]; | |
19346 | s.ri_cprmask[2] = mips_cprmask[2]; | |
19347 | s.ri_cprmask[3] = mips_cprmask[3]; | |
19348 | /* The gp_value field is set by the MIPS ELF backend. */ | |
19349 | ||
19350 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
19351 | ((Elf32_External_RegInfo *) | |
19352 | mips_regmask_frag)); | |
19353 | } | |
19354 | else | |
19355 | { | |
19356 | Elf64_Internal_RegInfo s; | |
19357 | ||
19358 | s.ri_gprmask = mips_gprmask; | |
19359 | s.ri_pad = 0; | |
19360 | s.ri_cprmask[0] = mips_cprmask[0]; | |
19361 | s.ri_cprmask[1] = mips_cprmask[1]; | |
19362 | s.ri_cprmask[2] = mips_cprmask[2]; | |
19363 | s.ri_cprmask[3] = mips_cprmask[3]; | |
19364 | /* The gp_value field is set by the MIPS ELF backend. */ | |
19365 | ||
19366 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
19367 | ((Elf64_External_RegInfo *) | |
19368 | mips_regmask_frag)); | |
19369 | } | |
19370 | ||
19371 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
19372 | sort of BFD interface for this. */ | |
19373 | if (mips_any_noreorder) | |
19374 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
19375 | if (mips_pic != NO_PIC) | |
143d77c5 | 19376 | { |
8b828383 | 19377 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
19378 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
19379 | } | |
19380 | if (mips_abicalls) | |
19381 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 19382 | |
b015e599 AP |
19383 | /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags |
19384 | defined at present; this might need to change in future. */ | |
a4672219 TS |
19385 | if (file_ase_mips16) |
19386 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
df58fc94 RS |
19387 | if (file_ase_micromips) |
19388 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS; | |
919731af | 19389 | if (file_mips_opts.ase & ASE_MDMX) |
deec1734 | 19390 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; |
1f25f5d3 | 19391 | |
bdaaa2e1 | 19392 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 19393 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 19394 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 19395 | else if (mips_abi == O64_ABI) |
252b5132 | 19396 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 19397 | else if (mips_abi == EABI_ABI) |
252b5132 | 19398 | { |
bad1aba3 | 19399 | if (file_mips_opts.gp == 64) |
252b5132 RH |
19400 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
19401 | else | |
19402 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
19403 | } | |
be00bddd | 19404 | |
defc8e2b | 19405 | /* Nothing to do for N32_ABI or N64_ABI. */ |
252b5132 RH |
19406 | |
19407 | if (mips_32bitmode) | |
19408 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
ad3fea08 | 19409 | |
7361da2c | 19410 | if (mips_nan2008 == 1) |
ba92f887 MR |
19411 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NAN2008; |
19412 | ||
ad3fea08 | 19413 | /* 32 bit code with 64 bit FP registers. */ |
351cdf24 MF |
19414 | fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, |
19415 | Tag_GNU_MIPS_ABI_FP); | |
19416 | if (fpabi == Val_GNU_MIPS_ABI_FP_OLD_64) | |
f1c38003 | 19417 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_FP64; |
252b5132 | 19418 | } |
252b5132 | 19419 | \f |
beae10d5 | 19420 | typedef struct proc { |
9b2f1d35 EC |
19421 | symbolS *func_sym; |
19422 | symbolS *func_end_sym; | |
beae10d5 KH |
19423 | unsigned long reg_mask; |
19424 | unsigned long reg_offset; | |
19425 | unsigned long fpreg_mask; | |
19426 | unsigned long fpreg_offset; | |
19427 | unsigned long frame_offset; | |
19428 | unsigned long frame_reg; | |
19429 | unsigned long pc_reg; | |
19430 | } procS; | |
252b5132 RH |
19431 | |
19432 | static procS cur_proc; | |
19433 | static procS *cur_proc_ptr; | |
19434 | static int numprocs; | |
19435 | ||
df58fc94 RS |
19436 | /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop |
19437 | as "2", and a normal nop as "0". */ | |
19438 | ||
19439 | #define NOP_OPCODE_MIPS 0 | |
19440 | #define NOP_OPCODE_MIPS16 1 | |
19441 | #define NOP_OPCODE_MICROMIPS 2 | |
742a56fe RS |
19442 | |
19443 | char | |
19444 | mips_nop_opcode (void) | |
19445 | { | |
df58fc94 RS |
19446 | if (seg_info (now_seg)->tc_segment_info_data.micromips) |
19447 | return NOP_OPCODE_MICROMIPS; | |
19448 | else if (seg_info (now_seg)->tc_segment_info_data.mips16) | |
19449 | return NOP_OPCODE_MIPS16; | |
19450 | else | |
19451 | return NOP_OPCODE_MIPS; | |
742a56fe RS |
19452 | } |
19453 | ||
df58fc94 RS |
19454 | /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use |
19455 | 32-bit microMIPS NOPs here (if applicable). */ | |
a19d8eb0 | 19456 | |
0a9ef439 | 19457 | void |
17a2f251 | 19458 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 19459 | { |
df58fc94 | 19460 | char nop_opcode; |
742a56fe | 19461 | char *p; |
c67a084a NC |
19462 | int bytes, size, excess; |
19463 | valueT opcode; | |
742a56fe | 19464 | |
0a9ef439 RH |
19465 | if (fragp->fr_type != rs_align_code) |
19466 | return; | |
19467 | ||
742a56fe | 19468 | p = fragp->fr_literal + fragp->fr_fix; |
df58fc94 RS |
19469 | nop_opcode = *p; |
19470 | switch (nop_opcode) | |
a19d8eb0 | 19471 | { |
df58fc94 RS |
19472 | case NOP_OPCODE_MICROMIPS: |
19473 | opcode = micromips_nop32_insn.insn_opcode; | |
19474 | size = 4; | |
19475 | break; | |
19476 | case NOP_OPCODE_MIPS16: | |
c67a084a NC |
19477 | opcode = mips16_nop_insn.insn_opcode; |
19478 | size = 2; | |
df58fc94 RS |
19479 | break; |
19480 | case NOP_OPCODE_MIPS: | |
19481 | default: | |
c67a084a NC |
19482 | opcode = nop_insn.insn_opcode; |
19483 | size = 4; | |
df58fc94 | 19484 | break; |
c67a084a | 19485 | } |
a19d8eb0 | 19486 | |
c67a084a NC |
19487 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
19488 | excess = bytes % size; | |
df58fc94 RS |
19489 | |
19490 | /* Handle the leading part if we're not inserting a whole number of | |
19491 | instructions, and make it the end of the fixed part of the frag. | |
19492 | Try to fit in a short microMIPS NOP if applicable and possible, | |
19493 | and use zeroes otherwise. */ | |
19494 | gas_assert (excess < 4); | |
19495 | fragp->fr_fix += excess; | |
19496 | switch (excess) | |
c67a084a | 19497 | { |
df58fc94 RS |
19498 | case 3: |
19499 | *p++ = '\0'; | |
19500 | /* Fall through. */ | |
19501 | case 2: | |
833794fc | 19502 | if (nop_opcode == NOP_OPCODE_MICROMIPS && !mips_opts.insn32) |
df58fc94 | 19503 | { |
4d68580a | 19504 | p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2); |
df58fc94 RS |
19505 | break; |
19506 | } | |
19507 | *p++ = '\0'; | |
19508 | /* Fall through. */ | |
19509 | case 1: | |
19510 | *p++ = '\0'; | |
19511 | /* Fall through. */ | |
19512 | case 0: | |
19513 | break; | |
a19d8eb0 | 19514 | } |
c67a084a NC |
19515 | |
19516 | md_number_to_chars (p, opcode, size); | |
19517 | fragp->fr_var = size; | |
a19d8eb0 CP |
19518 | } |
19519 | ||
252b5132 | 19520 | static long |
17a2f251 | 19521 | get_number (void) |
252b5132 RH |
19522 | { |
19523 | int negative = 0; | |
19524 | long val = 0; | |
19525 | ||
19526 | if (*input_line_pointer == '-') | |
19527 | { | |
19528 | ++input_line_pointer; | |
19529 | negative = 1; | |
19530 | } | |
3882b010 | 19531 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 19532 | as_bad (_("expected simple number")); |
252b5132 RH |
19533 | if (input_line_pointer[0] == '0') |
19534 | { | |
19535 | if (input_line_pointer[1] == 'x') | |
19536 | { | |
19537 | input_line_pointer += 2; | |
3882b010 | 19538 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
19539 | { |
19540 | val <<= 4; | |
19541 | val |= hex_value (*input_line_pointer++); | |
19542 | } | |
19543 | return negative ? -val : val; | |
19544 | } | |
19545 | else | |
19546 | { | |
19547 | ++input_line_pointer; | |
3882b010 | 19548 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
19549 | { |
19550 | val <<= 3; | |
19551 | val |= *input_line_pointer++ - '0'; | |
19552 | } | |
19553 | return negative ? -val : val; | |
19554 | } | |
19555 | } | |
3882b010 | 19556 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
19557 | { |
19558 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
19559 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 19560 | as_warn (_("invalid number")); |
252b5132 RH |
19561 | return -1; |
19562 | } | |
3882b010 | 19563 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
19564 | { |
19565 | val *= 10; | |
19566 | val += *input_line_pointer++ - '0'; | |
19567 | } | |
19568 | return negative ? -val : val; | |
19569 | } | |
19570 | ||
19571 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
19572 | is an initial number which is the ECOFF file index. In the non-ECOFF |
19573 | case .file implies DWARF-2. */ | |
19574 | ||
19575 | static void | |
17a2f251 | 19576 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 19577 | { |
ecb4347a DJ |
19578 | static int first_file_directive = 0; |
19579 | ||
c5dd6aab DJ |
19580 | if (ECOFF_DEBUGGING) |
19581 | { | |
19582 | get_number (); | |
19583 | s_app_file (0); | |
19584 | } | |
19585 | else | |
ecb4347a DJ |
19586 | { |
19587 | char *filename; | |
19588 | ||
68d20676 | 19589 | filename = dwarf2_directive_filename (); |
ecb4347a DJ |
19590 | |
19591 | /* Versions of GCC up to 3.1 start files with a ".file" | |
19592 | directive even for stabs output. Make sure that this | |
19593 | ".file" is handled. Note that you need a version of GCC | |
19594 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
19595 | if (filename != NULL && ! first_file_directive) | |
19596 | { | |
19597 | (void) new_logical_line (filename, -1); | |
c04f5787 | 19598 | s_app_file_string (filename, 0); |
ecb4347a DJ |
19599 | } |
19600 | first_file_directive = 1; | |
19601 | } | |
c5dd6aab DJ |
19602 | } |
19603 | ||
19604 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
19605 | |
19606 | static void | |
17a2f251 | 19607 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 19608 | { |
c5dd6aab DJ |
19609 | if (!ECOFF_DEBUGGING) |
19610 | dwarf2_directive_loc (0); | |
252b5132 RH |
19611 | } |
19612 | ||
252b5132 RH |
19613 | /* The .end directive. */ |
19614 | ||
19615 | static void | |
17a2f251 | 19616 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
19617 | { |
19618 | symbolS *p; | |
252b5132 | 19619 | |
7a621144 DJ |
19620 | /* Following functions need their own .frame and .cprestore directives. */ |
19621 | mips_frame_reg_valid = 0; | |
19622 | mips_cprestore_valid = 0; | |
19623 | ||
252b5132 RH |
19624 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
19625 | { | |
19626 | p = get_symbol (); | |
19627 | demand_empty_rest_of_line (); | |
19628 | } | |
19629 | else | |
19630 | p = NULL; | |
19631 | ||
14949570 | 19632 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
19633 | as_warn (_(".end not in text section")); |
19634 | ||
19635 | if (!cur_proc_ptr) | |
19636 | { | |
1661c76c | 19637 | as_warn (_(".end directive without a preceding .ent directive")); |
252b5132 RH |
19638 | demand_empty_rest_of_line (); |
19639 | return; | |
19640 | } | |
19641 | ||
19642 | if (p != NULL) | |
19643 | { | |
9c2799c2 | 19644 | gas_assert (S_GET_NAME (p)); |
9b2f1d35 | 19645 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
1661c76c | 19646 | as_warn (_(".end symbol does not match .ent symbol")); |
ecb4347a DJ |
19647 | |
19648 | if (debug_type == DEBUG_STABS) | |
19649 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
19650 | S_GET_NAME (p)); | |
252b5132 RH |
19651 | } |
19652 | else | |
19653 | as_warn (_(".end directive missing or unknown symbol")); | |
19654 | ||
9b2f1d35 EC |
19655 | /* Create an expression to calculate the size of the function. */ |
19656 | if (p && cur_proc_ptr) | |
19657 | { | |
19658 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
325801bd | 19659 | expressionS *exp = XNEW (expressionS); |
9b2f1d35 EC |
19660 | |
19661 | obj->size = exp; | |
19662 | exp->X_op = O_subtract; | |
19663 | exp->X_add_symbol = symbol_temp_new_now (); | |
19664 | exp->X_op_symbol = p; | |
19665 | exp->X_add_number = 0; | |
19666 | ||
19667 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
19668 | } | |
19669 | ||
5ff6a06c MR |
19670 | #ifdef md_flush_pending_output |
19671 | md_flush_pending_output (); | |
19672 | #endif | |
19673 | ||
ecb4347a | 19674 | /* Generate a .pdr section. */ |
f3ded42a | 19675 | if (!ECOFF_DEBUGGING && mips_flag_pdr) |
ecb4347a DJ |
19676 | { |
19677 | segT saved_seg = now_seg; | |
19678 | subsegT saved_subseg = now_subseg; | |
ecb4347a DJ |
19679 | expressionS exp; |
19680 | char *fragp; | |
252b5132 | 19681 | |
9c2799c2 | 19682 | gas_assert (pdr_seg); |
ecb4347a | 19683 | subseg_set (pdr_seg, 0); |
252b5132 | 19684 | |
ecb4347a DJ |
19685 | /* Write the symbol. */ |
19686 | exp.X_op = O_symbol; | |
19687 | exp.X_add_symbol = p; | |
19688 | exp.X_add_number = 0; | |
19689 | emit_expr (&exp, 4); | |
252b5132 | 19690 | |
ecb4347a | 19691 | fragp = frag_more (7 * 4); |
252b5132 | 19692 | |
17a2f251 TS |
19693 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
19694 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
19695 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
19696 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
19697 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
19698 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
19699 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 19700 | |
ecb4347a DJ |
19701 | subseg_set (saved_seg, saved_subseg); |
19702 | } | |
252b5132 RH |
19703 | |
19704 | cur_proc_ptr = NULL; | |
19705 | } | |
19706 | ||
19707 | /* The .aent and .ent directives. */ | |
19708 | ||
19709 | static void | |
17a2f251 | 19710 | s_mips_ent (int aent) |
252b5132 | 19711 | { |
252b5132 | 19712 | symbolS *symbolP; |
252b5132 RH |
19713 | |
19714 | symbolP = get_symbol (); | |
19715 | if (*input_line_pointer == ',') | |
f9419b05 | 19716 | ++input_line_pointer; |
252b5132 | 19717 | SKIP_WHITESPACE (); |
3882b010 | 19718 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 19719 | || *input_line_pointer == '-') |
874e8986 | 19720 | get_number (); |
252b5132 | 19721 | |
14949570 | 19722 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
1661c76c | 19723 | as_warn (_(".ent or .aent not in text section")); |
252b5132 RH |
19724 | |
19725 | if (!aent && cur_proc_ptr) | |
9a41af64 | 19726 | as_warn (_("missing .end")); |
252b5132 RH |
19727 | |
19728 | if (!aent) | |
19729 | { | |
7a621144 DJ |
19730 | /* This function needs its own .frame and .cprestore directives. */ |
19731 | mips_frame_reg_valid = 0; | |
19732 | mips_cprestore_valid = 0; | |
19733 | ||
252b5132 RH |
19734 | cur_proc_ptr = &cur_proc; |
19735 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
19736 | ||
9b2f1d35 | 19737 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 19738 | |
f9419b05 | 19739 | ++numprocs; |
ecb4347a DJ |
19740 | |
19741 | if (debug_type == DEBUG_STABS) | |
19742 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
19743 | S_GET_NAME (symbolP)); | |
252b5132 RH |
19744 | } |
19745 | ||
7c0fc524 MR |
19746 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
19747 | ||
252b5132 RH |
19748 | demand_empty_rest_of_line (); |
19749 | } | |
19750 | ||
19751 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 19752 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 19753 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 19754 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
19755 | symbol table (in the mdebug section). */ |
19756 | ||
19757 | static void | |
17a2f251 | 19758 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 19759 | { |
f3ded42a RS |
19760 | if (ECOFF_DEBUGGING) |
19761 | s_ignore (ignore); | |
19762 | else | |
ecb4347a DJ |
19763 | { |
19764 | long val; | |
252b5132 | 19765 | |
ecb4347a DJ |
19766 | if (cur_proc_ptr == (procS *) NULL) |
19767 | { | |
19768 | as_warn (_(".frame outside of .ent")); | |
19769 | demand_empty_rest_of_line (); | |
19770 | return; | |
19771 | } | |
252b5132 | 19772 | |
ecb4347a DJ |
19773 | cur_proc_ptr->frame_reg = tc_get_register (1); |
19774 | ||
19775 | SKIP_WHITESPACE (); | |
19776 | if (*input_line_pointer++ != ',' | |
19777 | || get_absolute_expression_and_terminator (&val) != ',') | |
19778 | { | |
1661c76c | 19779 | as_warn (_("bad .frame directive")); |
ecb4347a DJ |
19780 | --input_line_pointer; |
19781 | demand_empty_rest_of_line (); | |
19782 | return; | |
19783 | } | |
252b5132 | 19784 | |
ecb4347a DJ |
19785 | cur_proc_ptr->frame_offset = val; |
19786 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 19787 | |
252b5132 | 19788 | demand_empty_rest_of_line (); |
252b5132 | 19789 | } |
252b5132 RH |
19790 | } |
19791 | ||
bdaaa2e1 KH |
19792 | /* The .fmask and .mask directives. If the mdebug section is present |
19793 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 19794 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 19795 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
19796 | make reference to the ecoff symbol table (in the mdebug section). */ |
19797 | ||
19798 | static void | |
17a2f251 | 19799 | s_mips_mask (int reg_type) |
252b5132 | 19800 | { |
f3ded42a RS |
19801 | if (ECOFF_DEBUGGING) |
19802 | s_ignore (reg_type); | |
19803 | else | |
252b5132 | 19804 | { |
ecb4347a | 19805 | long mask, off; |
252b5132 | 19806 | |
ecb4347a DJ |
19807 | if (cur_proc_ptr == (procS *) NULL) |
19808 | { | |
19809 | as_warn (_(".mask/.fmask outside of .ent")); | |
19810 | demand_empty_rest_of_line (); | |
19811 | return; | |
19812 | } | |
252b5132 | 19813 | |
ecb4347a DJ |
19814 | if (get_absolute_expression_and_terminator (&mask) != ',') |
19815 | { | |
1661c76c | 19816 | as_warn (_("bad .mask/.fmask directive")); |
ecb4347a DJ |
19817 | --input_line_pointer; |
19818 | demand_empty_rest_of_line (); | |
19819 | return; | |
19820 | } | |
252b5132 | 19821 | |
ecb4347a DJ |
19822 | off = get_absolute_expression (); |
19823 | ||
19824 | if (reg_type == 'F') | |
19825 | { | |
19826 | cur_proc_ptr->fpreg_mask = mask; | |
19827 | cur_proc_ptr->fpreg_offset = off; | |
19828 | } | |
19829 | else | |
19830 | { | |
19831 | cur_proc_ptr->reg_mask = mask; | |
19832 | cur_proc_ptr->reg_offset = off; | |
19833 | } | |
19834 | ||
19835 | demand_empty_rest_of_line (); | |
252b5132 | 19836 | } |
252b5132 RH |
19837 | } |
19838 | ||
316f5878 RS |
19839 | /* A table describing all the processors gas knows about. Names are |
19840 | matched in the order listed. | |
e7af610e | 19841 | |
316f5878 RS |
19842 | To ease comparison, please keep this table in the same order as |
19843 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
19844 | static const struct mips_cpu_info mips_cpu_info_table[] = |
19845 | { | |
6f2117ba | 19846 | /* Entries for generic ISAs. */ |
d16afab6 RS |
19847 | { "mips1", MIPS_CPU_IS_ISA, 0, ISA_MIPS1, CPU_R3000 }, |
19848 | { "mips2", MIPS_CPU_IS_ISA, 0, ISA_MIPS2, CPU_R6000 }, | |
19849 | { "mips3", MIPS_CPU_IS_ISA, 0, ISA_MIPS3, CPU_R4000 }, | |
19850 | { "mips4", MIPS_CPU_IS_ISA, 0, ISA_MIPS4, CPU_R8000 }, | |
19851 | { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 }, | |
19852 | { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 }, | |
19853 | { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ae52f483 AB |
19854 | { "mips32r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R3, CPU_MIPS32R3 }, |
19855 | { "mips32r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R5, CPU_MIPS32R5 }, | |
7361da2c | 19856 | { "mips32r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R6, CPU_MIPS32R6 }, |
d16afab6 RS |
19857 | { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 }, |
19858 | { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 }, | |
ae52f483 AB |
19859 | { "mips64r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R3, CPU_MIPS64R3 }, |
19860 | { "mips64r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R5, CPU_MIPS64R5 }, | |
7361da2c | 19861 | { "mips64r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R6, CPU_MIPS64R6 }, |
316f5878 RS |
19862 | |
19863 | /* MIPS I */ | |
d16afab6 RS |
19864 | { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 }, |
19865 | { "r2000", 0, 0, ISA_MIPS1, CPU_R3000 }, | |
19866 | { "r3900", 0, 0, ISA_MIPS1, CPU_R3900 }, | |
316f5878 RS |
19867 | |
19868 | /* MIPS II */ | |
d16afab6 | 19869 | { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 }, |
316f5878 RS |
19870 | |
19871 | /* MIPS III */ | |
d16afab6 RS |
19872 | { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 }, |
19873 | { "r4010", 0, 0, ISA_MIPS2, CPU_R4010 }, | |
19874 | { "vr4100", 0, 0, ISA_MIPS3, CPU_VR4100 }, | |
19875 | { "vr4111", 0, 0, ISA_MIPS3, CPU_R4111 }, | |
19876 | { "vr4120", 0, 0, ISA_MIPS3, CPU_VR4120 }, | |
19877 | { "vr4130", 0, 0, ISA_MIPS3, CPU_VR4120 }, | |
19878 | { "vr4181", 0, 0, ISA_MIPS3, CPU_R4111 }, | |
19879 | { "vr4300", 0, 0, ISA_MIPS3, CPU_R4300 }, | |
19880 | { "r4400", 0, 0, ISA_MIPS3, CPU_R4400 }, | |
19881 | { "r4600", 0, 0, ISA_MIPS3, CPU_R4600 }, | |
19882 | { "orion", 0, 0, ISA_MIPS3, CPU_R4600 }, | |
19883 | { "r4650", 0, 0, ISA_MIPS3, CPU_R4650 }, | |
19884 | { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 }, | |
6f2117ba | 19885 | /* ST Microelectronics Loongson 2E and 2F cores. */ |
d16afab6 | 19886 | { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E }, |
8095d2f7 | 19887 | { "loongson2f", 0, ASE_LOONGSON_MMI, ISA_MIPS3, CPU_LOONGSON_2F }, |
316f5878 RS |
19888 | |
19889 | /* MIPS IV */ | |
d16afab6 RS |
19890 | { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 }, |
19891 | { "r10000", 0, 0, ISA_MIPS4, CPU_R10000 }, | |
19892 | { "r12000", 0, 0, ISA_MIPS4, CPU_R12000 }, | |
19893 | { "r14000", 0, 0, ISA_MIPS4, CPU_R14000 }, | |
19894 | { "r16000", 0, 0, ISA_MIPS4, CPU_R16000 }, | |
19895 | { "vr5000", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19896 | { "vr5400", 0, 0, ISA_MIPS4, CPU_VR5400 }, | |
19897 | { "vr5500", 0, 0, ISA_MIPS4, CPU_VR5500 }, | |
19898 | { "rm5200", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19899 | { "rm5230", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19900 | { "rm5231", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19901 | { "rm5261", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19902 | { "rm5721", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19903 | { "rm7000", 0, 0, ISA_MIPS4, CPU_RM7000 }, | |
19904 | { "rm9000", 0, 0, ISA_MIPS4, CPU_RM9000 }, | |
316f5878 RS |
19905 | |
19906 | /* MIPS 32 */ | |
d16afab6 RS |
19907 | { "4kc", 0, 0, ISA_MIPS32, CPU_MIPS32 }, |
19908 | { "4km", 0, 0, ISA_MIPS32, CPU_MIPS32 }, | |
19909 | { "4kp", 0, 0, ISA_MIPS32, CPU_MIPS32 }, | |
19910 | { "4ksc", 0, ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 }, | |
ad3fea08 TS |
19911 | |
19912 | /* MIPS 32 Release 2 */ | |
d16afab6 RS |
19913 | { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19914 | { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19915 | { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19916 | { "4ksd", 0, ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19917 | { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19918 | { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19919 | { "m14k", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19920 | { "m14kc", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19921 | { "m14ke", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU, | |
19922 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19923 | { "m14kec", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU, | |
19924 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19925 | { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19926 | { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19927 | { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19928 | { "24kf1_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 19929 | /* Deprecated forms of the above. */ |
d16afab6 RS |
19930 | { "24kfx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19931 | { "24kx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f | 19932 | /* 24KE is a 24K with DSP ASE, other ASEs are optional. */ |
d16afab6 RS |
19933 | { "24kec", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19934 | { "24kef2_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19935 | { "24kef", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19936 | { "24kef1_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 19937 | /* Deprecated forms of the above. */ |
d16afab6 RS |
19938 | { "24kefx", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19939 | { "24kex", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f | 19940 | /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */ |
d16afab6 RS |
19941 | { "34kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19942 | { "34kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19943 | { "34kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19944 | { "34kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 19945 | /* Deprecated forms of the above. */ |
d16afab6 RS |
19946 | { "34kfx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19947 | { "34kx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
711eefe4 | 19948 | /* 34Kn is a 34kc without DSP. */ |
d16afab6 | 19949 | { "34kn", 0, ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 19950 | /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */ |
d16afab6 RS |
19951 | { "74kc", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19952 | { "74kf2_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19953 | { "74kf", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19954 | { "74kf1_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19955 | { "74kf3_2", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 19956 | /* Deprecated forms of the above. */ |
d16afab6 RS |
19957 | { "74kfx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19958 | { "74kx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
30f8113a | 19959 | /* 1004K cores are multiprocessor versions of the 34K. */ |
d16afab6 RS |
19960 | { "1004kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19961 | { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19962 | { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19963 | { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
6f2117ba | 19964 | /* interaptiv is the new name for 1004kf. */ |
77403ce9 | 19965 | { "interaptiv", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
38bf472a MR |
19966 | { "interaptiv-mr2", 0, |
19967 | ASE_DSP | ASE_EVA | ASE_MT | ASE_MIPS16E2 | ASE_MIPS16E2_MT, | |
19968 | ISA_MIPS32R3, CPU_INTERAPTIV_MR2 }, | |
6f2117ba | 19969 | /* M5100 family. */ |
c6e5c03a RS |
19970 | { "m5100", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 }, |
19971 | { "m5101", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 }, | |
bbaa46c0 | 19972 | /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */ |
134c0c8b | 19973 | { "p5600", 0, ASE_VIRT | ASE_EVA | ASE_XPA, ISA_MIPS32R5, CPU_MIPS32R5 }, |
32b26a03 | 19974 | |
316f5878 | 19975 | /* MIPS 64 */ |
d16afab6 RS |
19976 | { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 }, |
19977 | { "5kf", 0, 0, ISA_MIPS64, CPU_MIPS64 }, | |
19978 | { "20kc", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
19979 | { "25kf", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
ad3fea08 | 19980 | |
6f2117ba | 19981 | /* Broadcom SB-1 CPU core. */ |
d16afab6 | 19982 | { "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 }, |
6f2117ba | 19983 | /* Broadcom SB-1A CPU core. */ |
d16afab6 | 19984 | { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 }, |
3739860c | 19985 | |
6f2117ba PH |
19986 | /* MIPS 64 Release 2. */ |
19987 | /* Loongson CPU core. */ | |
19988 | /* -march=loongson3a is an alias of -march=gs464 for compatibility. */ | |
bdc6c06e | 19989 | { "loongson3a", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT, |
ac8cb70f CX |
19990 | ISA_MIPS64R2, CPU_GS464 }, |
19991 | { "gs464", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT, | |
19992 | ISA_MIPS64R2, CPU_GS464 }, | |
bd782c07 CX |
19993 | { "gs464e", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT |
19994 | | ASE_LOONGSON_EXT2, ISA_MIPS64R2, CPU_GS464E }, | |
9108bc33 CX |
19995 | { "gs264e", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT |
19996 | | ASE_LOONGSON_EXT2 | ASE_MSA | ASE_MSA64, ISA_MIPS64R2, CPU_GS264E }, | |
ed163775 | 19997 | |
6f2117ba | 19998 | /* Cavium Networks Octeon CPU core. */ |
d16afab6 RS |
19999 | { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON }, |
20000 | { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP }, | |
20001 | { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 }, | |
2c629856 | 20002 | { "octeon3", 0, ASE_VIRT | ASE_VIRT64, ISA_MIPS64R5, CPU_OCTEON3 }, |
967344c6 | 20003 | |
52b6b6b9 | 20004 | /* RMI Xlr */ |
d16afab6 | 20005 | { "xlr", 0, 0, ISA_MIPS64, CPU_XLR }, |
52b6b6b9 | 20006 | |
55a36193 MK |
20007 | /* Broadcom XLP. |
20008 | XLP is mostly like XLR, with the prominent exception that it is | |
20009 | MIPS64R2 rather than MIPS64. */ | |
d16afab6 | 20010 | { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR }, |
55a36193 | 20011 | |
6f2117ba | 20012 | /* MIPS 64 Release 6. */ |
7ef0d297 | 20013 | { "i6400", 0, ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6}, |
a4968f42 | 20014 | { "p6600", 0, ASE_VIRT | ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6}, |
7ef0d297 | 20015 | |
6f2117ba | 20016 | /* End marker. */ |
d16afab6 | 20017 | { NULL, 0, 0, 0, 0 } |
316f5878 | 20018 | }; |
e7af610e | 20019 | |
84ea6cf2 | 20020 | |
316f5878 RS |
20021 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
20022 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 20023 | |
316f5878 | 20024 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 20025 | |
b34976b6 | 20026 | static bfd_boolean |
17a2f251 | 20027 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
20028 | { |
20029 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
20030 | given++, canonical++; | |
20031 | ||
20032 | return ((*given == 0 && *canonical == 0) | |
20033 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
20034 | } | |
20035 | ||
20036 | ||
20037 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
20038 | CPU name. We've traditionally allowed a lot of variation here. | |
20039 | ||
20040 | Note: this function is shared between GCC and GAS. */ | |
20041 | ||
b34976b6 | 20042 | static bfd_boolean |
17a2f251 | 20043 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
20044 | { |
20045 | /* First see if the name matches exactly, or with a final "000" | |
20046 | turned into "k". */ | |
20047 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 20048 | return TRUE; |
316f5878 RS |
20049 | |
20050 | /* If not, try comparing based on numerical designation alone. | |
20051 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
20052 | if (TOLOWER (*given) == 'r') | |
20053 | given++; | |
20054 | if (!ISDIGIT (*given)) | |
b34976b6 | 20055 | return FALSE; |
316f5878 RS |
20056 | |
20057 | /* Skip over some well-known prefixes in the canonical name, | |
20058 | hoping to find a number there too. */ | |
20059 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
20060 | canonical += 2; | |
20061 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
20062 | canonical += 2; | |
20063 | else if (TOLOWER (canonical[0]) == 'r') | |
20064 | canonical += 1; | |
20065 | ||
20066 | return mips_strict_matching_cpu_name_p (canonical, given); | |
20067 | } | |
20068 | ||
20069 | ||
20070 | /* Parse an option that takes the name of a processor as its argument. | |
20071 | OPTION is the name of the option and CPU_STRING is the argument. | |
20072 | Return the corresponding processor enumeration if the CPU_STRING is | |
20073 | recognized, otherwise report an error and return null. | |
20074 | ||
20075 | A similar function exists in GCC. */ | |
e7af610e NC |
20076 | |
20077 | static const struct mips_cpu_info * | |
17a2f251 | 20078 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 20079 | { |
316f5878 | 20080 | const struct mips_cpu_info *p; |
e7af610e | 20081 | |
316f5878 RS |
20082 | /* 'from-abi' selects the most compatible architecture for the given |
20083 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
20084 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
20085 | version. Look first at the -mgp options, if given, otherwise base | |
20086 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 20087 | |
316f5878 RS |
20088 | Treat NO_ABI like the EABIs. One reason to do this is that the |
20089 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
20090 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
20091 | 'mips64', just as we did in the days before 'from-abi'. */ | |
20092 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
20093 | { | |
20094 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
20095 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
20096 | ||
20097 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
20098 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
20099 | ||
bad1aba3 | 20100 | if (file_mips_opts.gp >= 0) |
20101 | return mips_cpu_info_from_isa (file_mips_opts.gp == 32 | |
0b35dfee | 20102 | ? ISA_MIPS1 : ISA_MIPS3); |
316f5878 RS |
20103 | |
20104 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
20105 | ? ISA_MIPS3 | |
20106 | : ISA_MIPS1); | |
20107 | } | |
20108 | ||
20109 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
20110 | if (strcasecmp (cpu_string, "default") == 0) | |
20111 | return 0; | |
20112 | ||
20113 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
20114 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
20115 | return p; | |
20116 | ||
1661c76c | 20117 | as_bad (_("bad value (%s) for %s"), cpu_string, option); |
316f5878 | 20118 | return 0; |
e7af610e NC |
20119 | } |
20120 | ||
316f5878 RS |
20121 | /* Return the canonical processor information for ISA (a member of the |
20122 | ISA_MIPS* enumeration). */ | |
20123 | ||
e7af610e | 20124 | static const struct mips_cpu_info * |
17a2f251 | 20125 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
20126 | { |
20127 | int i; | |
20128 | ||
20129 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
ad3fea08 | 20130 | if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA) |
316f5878 | 20131 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
20132 | return (&mips_cpu_info_table[i]); |
20133 | ||
e972090a | 20134 | return NULL; |
e7af610e | 20135 | } |
fef14a42 TS |
20136 | |
20137 | static const struct mips_cpu_info * | |
17a2f251 | 20138 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
20139 | { |
20140 | int i; | |
20141 | ||
20142 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
20143 | if (arch == mips_cpu_info_table[i].cpu) | |
20144 | return (&mips_cpu_info_table[i]); | |
20145 | ||
20146 | return NULL; | |
20147 | } | |
316f5878 RS |
20148 | \f |
20149 | static void | |
17a2f251 | 20150 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
20151 | { |
20152 | if (*first_p) | |
20153 | { | |
20154 | fprintf (stream, "%24s", ""); | |
20155 | *col_p = 24; | |
20156 | } | |
20157 | else | |
20158 | { | |
20159 | fprintf (stream, ", "); | |
20160 | *col_p += 2; | |
20161 | } | |
e7af610e | 20162 | |
316f5878 RS |
20163 | if (*col_p + strlen (string) > 72) |
20164 | { | |
20165 | fprintf (stream, "\n%24s", ""); | |
20166 | *col_p = 24; | |
20167 | } | |
20168 | ||
20169 | fprintf (stream, "%s", string); | |
20170 | *col_p += strlen (string); | |
20171 | ||
20172 | *first_p = 0; | |
20173 | } | |
20174 | ||
20175 | void | |
17a2f251 | 20176 | md_show_usage (FILE *stream) |
e7af610e | 20177 | { |
316f5878 RS |
20178 | int column, first; |
20179 | size_t i; | |
20180 | ||
20181 | fprintf (stream, _("\ | |
20182 | MIPS options:\n\ | |
316f5878 RS |
20183 | -EB generate big endian output\n\ |
20184 | -EL generate little endian output\n\ | |
20185 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
20186 | -G NUM allow referencing objects up to NUM bytes\n\ | |
20187 | implicitly with the gp register [default 8]\n")); | |
20188 | fprintf (stream, _("\ | |
20189 | -mips1 generate MIPS ISA I instructions\n\ | |
20190 | -mips2 generate MIPS ISA II instructions\n\ | |
20191 | -mips3 generate MIPS ISA III instructions\n\ | |
20192 | -mips4 generate MIPS ISA IV instructions\n\ | |
20193 | -mips5 generate MIPS ISA V instructions\n\ | |
20194 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 20195 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
ae52f483 AB |
20196 | -mips32r3 generate MIPS32 release 3 ISA instructions\n\ |
20197 | -mips32r5 generate MIPS32 release 5 ISA instructions\n\ | |
7361da2c | 20198 | -mips32r6 generate MIPS32 release 6 ISA instructions\n\ |
316f5878 | 20199 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 20200 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
ae52f483 AB |
20201 | -mips64r3 generate MIPS64 release 3 ISA instructions\n\ |
20202 | -mips64r5 generate MIPS64 release 5 ISA instructions\n\ | |
7361da2c | 20203 | -mips64r6 generate MIPS64 release 6 ISA instructions\n\ |
316f5878 RS |
20204 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
20205 | ||
20206 | first = 1; | |
e7af610e NC |
20207 | |
20208 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
20209 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
20210 | show (stream, "from-abi", &column, &first); | |
20211 | fputc ('\n', stream); | |
e7af610e | 20212 | |
316f5878 RS |
20213 | fprintf (stream, _("\ |
20214 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
20215 | -no-mCPU don't generate code specific to CPU.\n\ | |
20216 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
20217 | ||
20218 | first = 1; | |
20219 | ||
20220 | show (stream, "3900", &column, &first); | |
20221 | show (stream, "4010", &column, &first); | |
20222 | show (stream, "4100", &column, &first); | |
20223 | show (stream, "4650", &column, &first); | |
20224 | fputc ('\n', stream); | |
20225 | ||
20226 | fprintf (stream, _("\ | |
20227 | -mips16 generate mips16 instructions\n\ | |
20228 | -no-mips16 do not generate mips16 instructions\n")); | |
20229 | fprintf (stream, _("\ | |
f866b262 MR |
20230 | -mmips16e2 generate MIPS16e2 instructions\n\ |
20231 | -mno-mips16e2 do not generate MIPS16e2 instructions\n")); | |
20232 | fprintf (stream, _("\ | |
df58fc94 RS |
20233 | -mmicromips generate microMIPS instructions\n\ |
20234 | -mno-micromips do not generate microMIPS instructions\n")); | |
20235 | fprintf (stream, _("\ | |
e16bfa71 | 20236 | -msmartmips generate smartmips instructions\n\ |
3739860c | 20237 | -mno-smartmips do not generate smartmips instructions\n")); |
e16bfa71 | 20238 | fprintf (stream, _("\ |
74cd071d CF |
20239 | -mdsp generate DSP instructions\n\ |
20240 | -mno-dsp do not generate DSP instructions\n")); | |
20241 | fprintf (stream, _("\ | |
8b082fb1 TS |
20242 | -mdspr2 generate DSP R2 instructions\n\ |
20243 | -mno-dspr2 do not generate DSP R2 instructions\n")); | |
20244 | fprintf (stream, _("\ | |
8f4f9071 MF |
20245 | -mdspr3 generate DSP R3 instructions\n\ |
20246 | -mno-dspr3 do not generate DSP R3 instructions\n")); | |
20247 | fprintf (stream, _("\ | |
ef2e4d86 CF |
20248 | -mmt generate MT instructions\n\ |
20249 | -mno-mt do not generate MT instructions\n")); | |
20250 | fprintf (stream, _("\ | |
dec0624d MR |
20251 | -mmcu generate MCU instructions\n\ |
20252 | -mno-mcu do not generate MCU instructions\n")); | |
20253 | fprintf (stream, _("\ | |
56d438b1 CF |
20254 | -mmsa generate MSA instructions\n\ |
20255 | -mno-msa do not generate MSA instructions\n")); | |
20256 | fprintf (stream, _("\ | |
7d64c587 AB |
20257 | -mxpa generate eXtended Physical Address (XPA) instructions\n\ |
20258 | -mno-xpa do not generate eXtended Physical Address (XPA) instructions\n")); | |
20259 | fprintf (stream, _("\ | |
b015e599 AP |
20260 | -mvirt generate Virtualization instructions\n\ |
20261 | -mno-virt do not generate Virtualization instructions\n")); | |
20262 | fprintf (stream, _("\ | |
730c3174 SE |
20263 | -mcrc generate CRC instructions\n\ |
20264 | -mno-crc do not generate CRC instructions\n")); | |
20265 | fprintf (stream, _("\ | |
6f20c942 FS |
20266 | -mginv generate Global INValidate (GINV) instructions\n\ |
20267 | -mno-ginv do not generate Global INValidate instructions\n")); | |
20268 | fprintf (stream, _("\ | |
8095d2f7 CX |
20269 | -mloongson-mmi generate Loongson MultiMedia extensions Instructions (MMI) instructions\n\ |
20270 | -mno-loongson-mmi do not generate Loongson MultiMedia extensions Instructions\n")); | |
20271 | fprintf (stream, _("\ | |
716c08de CX |
20272 | -mloongson-cam generate Loongson Content Address Memory (CAM) instructions\n\ |
20273 | -mno-loongson-cam do not generate Loongson Content Address Memory Instructions\n")); | |
20274 | fprintf (stream, _("\ | |
bdc6c06e CX |
20275 | -mloongson-ext generate Loongson EXTensions (EXT) instructions\n\ |
20276 | -mno-loongson-ext do not generate Loongson EXTensions Instructions\n")); | |
20277 | fprintf (stream, _("\ | |
a693765e CX |
20278 | -mloongson-ext2 generate Loongson EXTensions R2 (EXT2) instructions\n\ |
20279 | -mno-loongson-ext2 do not generate Loongson EXTensions R2 Instructions\n")); | |
20280 | fprintf (stream, _("\ | |
833794fc MR |
20281 | -minsn32 only generate 32-bit microMIPS instructions\n\ |
20282 | -mno-insn32 generate all microMIPS instructions\n")); | |
6f2117ba PH |
20283 | #if DEFAULT_MIPS_FIX_LOONGSON3_LLSC |
20284 | fprintf (stream, _("\ | |
20285 | -mfix-loongson3-llsc work around Loongson3 LL/SC errata, default\n\ | |
20286 | -mno-fix-loongson3-llsc disable work around Loongson3 LL/SC errata\n")); | |
20287 | #else | |
20288 | fprintf (stream, _("\ | |
20289 | -mfix-loongson3-llsc work around Loongson3 LL/SC errata\n\ | |
20290 | -mno-fix-loongson3-llsc disable work around Loongson3 LL/SC errata, default\n")); | |
20291 | #endif | |
833794fc | 20292 | fprintf (stream, _("\ |
c67a084a NC |
20293 | -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\ |
20294 | -mfix-loongson2f-nop work around Loongson2F NOP errata\n\ | |
6f2117ba PH |
20295 | -mfix-loongson3-llsc work around Loongson3 LL/SC errata\n\ |
20296 | -mno-fix-loongson3-llsc disable work around Loongson3 LL/SC errata\n\ | |
d766e8ec | 20297 | -mfix-vr4120 work around certain VR4120 errata\n\ |
7d8e00cf | 20298 | -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ |
6a32d874 | 20299 | -mfix-24k insert a nop after ERET and DERET instructions\n\ |
d954098f | 20300 | -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\ |
27c634e0 | 20301 | -mfix-r5900 work around R5900 short loop errata\n\ |
316f5878 RS |
20302 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
20303 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
aed1a261 | 20304 | -msym32 assume all symbols have 32-bit values\n\ |
092a534f MR |
20305 | -O0 do not remove unneeded NOPs, do not swap branches\n\ |
20306 | -O, -O1 remove unneeded NOPs, do not swap branches\n\ | |
20307 | -O2 remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
20308 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ |
20309 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
037b32b9 AN |
20310 | fprintf (stream, _("\ |
20311 | -mhard-float allow floating-point instructions\n\ | |
20312 | -msoft-float do not allow floating-point instructions\n\ | |
20313 | -msingle-float only allow 32-bit floating-point operations\n\ | |
20314 | -mdouble-float allow 32-bit and 64-bit floating-point operations\n\ | |
3bf0dbfb | 20315 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ |
ba92f887 | 20316 | --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\ |
8b10b0b3 MR |
20317 | -mignore-branch-isa accept invalid branches requiring an ISA mode switch\n\ |
20318 | -mno-ignore-branch-isa reject invalid branches requiring an ISA mode switch\n\ | |
ba92f887 MR |
20319 | -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n")); |
20320 | ||
20321 | first = 1; | |
20322 | ||
20323 | show (stream, "legacy", &column, &first); | |
20324 | show (stream, "2008", &column, &first); | |
20325 | ||
20326 | fputc ('\n', stream); | |
20327 | ||
316f5878 RS |
20328 | fprintf (stream, _("\ |
20329 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
861fb55a | 20330 | -call_nonpic generate non-PIC code that can operate with DSOs\n\ |
0c000745 | 20331 | -mvxworks-pic generate VxWorks position independent code\n\ |
861fb55a | 20332 | -non_shared do not generate code that can operate with DSOs\n\ |
316f5878 | 20333 | -xgot assume a 32 bit GOT\n\ |
dcd410fe | 20334 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
bbe506e8 | 20335 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
d821e36b | 20336 | position dependent (non shared) code\n\ |
316f5878 RS |
20337 | -mabi=ABI create ABI conformant object file for:\n")); |
20338 | ||
20339 | first = 1; | |
20340 | ||
20341 | show (stream, "32", &column, &first); | |
20342 | show (stream, "o64", &column, &first); | |
20343 | show (stream, "n32", &column, &first); | |
20344 | show (stream, "64", &column, &first); | |
20345 | show (stream, "eabi", &column, &first); | |
20346 | ||
20347 | fputc ('\n', stream); | |
20348 | ||
20349 | fprintf (stream, _("\ | |
b4f6242e MR |
20350 | -32 create o32 ABI object file%s\n"), |
20351 | MIPS_DEFAULT_ABI == O32_ABI ? _(" (default)") : ""); | |
20352 | fprintf (stream, _("\ | |
20353 | -n32 create n32 ABI object file%s\n"), | |
20354 | MIPS_DEFAULT_ABI == N32_ABI ? _(" (default)") : ""); | |
20355 | fprintf (stream, _("\ | |
20356 | -64 create 64 ABI object file%s\n"), | |
20357 | MIPS_DEFAULT_ABI == N64_ABI ? _(" (default)") : ""); | |
e7af610e | 20358 | } |
14e777e0 | 20359 | |
1575952e | 20360 | #ifdef TE_IRIX |
14e777e0 | 20361 | enum dwarf2_format |
413a266c | 20362 | mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED) |
14e777e0 | 20363 | { |
369943fe | 20364 | if (HAVE_64BIT_SYMBOLS) |
1575952e | 20365 | return dwarf2_format_64bit_irix; |
14e777e0 KB |
20366 | else |
20367 | return dwarf2_format_32bit; | |
20368 | } | |
1575952e | 20369 | #endif |
73369e65 EC |
20370 | |
20371 | int | |
20372 | mips_dwarf2_addr_size (void) | |
20373 | { | |
6b6b3450 | 20374 | if (HAVE_64BIT_OBJECTS) |
73369e65 | 20375 | return 8; |
73369e65 EC |
20376 | else |
20377 | return 4; | |
20378 | } | |
5862107c EC |
20379 | |
20380 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
20381 | void | |
20382 | mips_cfi_frame_initial_instructions (void) | |
20383 | { | |
20384 | cfi_add_CFA_def_cfa_register (SP); | |
20385 | } | |
20386 | ||
707bfff6 TS |
20387 | int |
20388 | tc_mips_regname_to_dw2regnum (char *regname) | |
20389 | { | |
20390 | unsigned int regnum = -1; | |
20391 | unsigned int reg; | |
20392 | ||
20393 | if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®)) | |
20394 | regnum = reg; | |
20395 | ||
20396 | return regnum; | |
20397 | } | |
263b2574 | 20398 | |
20399 | /* Implement CONVERT_SYMBOLIC_ATTRIBUTE. | |
20400 | Given a symbolic attribute NAME, return the proper integer value. | |
20401 | Returns -1 if the attribute is not known. */ | |
20402 | ||
20403 | int | |
20404 | mips_convert_symbolic_attribute (const char *name) | |
20405 | { | |
20406 | static const struct | |
20407 | { | |
20408 | const char * name; | |
20409 | const int tag; | |
20410 | } | |
20411 | attribute_table[] = | |
20412 | { | |
20413 | #define T(tag) {#tag, tag} | |
20414 | T (Tag_GNU_MIPS_ABI_FP), | |
20415 | T (Tag_GNU_MIPS_ABI_MSA), | |
20416 | #undef T | |
20417 | }; | |
20418 | unsigned int i; | |
20419 | ||
20420 | if (name == NULL) | |
20421 | return -1; | |
20422 | ||
20423 | for (i = 0; i < ARRAY_SIZE (attribute_table); i++) | |
20424 | if (streq (name, attribute_table[i].name)) | |
20425 | return attribute_table[i].tag; | |
20426 | ||
20427 | return -1; | |
20428 | } | |
fd5c94ab RS |
20429 | |
20430 | void | |
20431 | md_mips_end (void) | |
20432 | { | |
351cdf24 MF |
20433 | int fpabi = Val_GNU_MIPS_ABI_FP_ANY; |
20434 | ||
fd5c94ab RS |
20435 | mips_emit_delays (); |
20436 | if (cur_proc_ptr) | |
20437 | as_warn (_("missing .end at end of assembly")); | |
919731af | 20438 | |
20439 | /* Just in case no code was emitted, do the consistency check. */ | |
20440 | file_mips_check_options (); | |
351cdf24 MF |
20441 | |
20442 | /* Set a floating-point ABI if the user did not. */ | |
20443 | if (obj_elf_seen_attribute (OBJ_ATTR_GNU, Tag_GNU_MIPS_ABI_FP)) | |
20444 | { | |
20445 | /* Perform consistency checks on the floating-point ABI. */ | |
20446 | fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, | |
20447 | Tag_GNU_MIPS_ABI_FP); | |
20448 | if (fpabi != Val_GNU_MIPS_ABI_FP_ANY) | |
20449 | check_fpabi (fpabi); | |
20450 | } | |
20451 | else | |
20452 | { | |
20453 | /* Soft-float gets precedence over single-float, the two options should | |
20454 | not be used together so this should not matter. */ | |
20455 | if (file_mips_opts.soft_float == 1) | |
20456 | fpabi = Val_GNU_MIPS_ABI_FP_SOFT; | |
20457 | /* Single-float gets precedence over all double_float cases. */ | |
20458 | else if (file_mips_opts.single_float == 1) | |
20459 | fpabi = Val_GNU_MIPS_ABI_FP_SINGLE; | |
20460 | else | |
20461 | { | |
20462 | switch (file_mips_opts.fp) | |
20463 | { | |
20464 | case 32: | |
20465 | if (file_mips_opts.gp == 32) | |
20466 | fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE; | |
20467 | break; | |
20468 | case 0: | |
20469 | fpabi = Val_GNU_MIPS_ABI_FP_XX; | |
20470 | break; | |
20471 | case 64: | |
20472 | if (file_mips_opts.gp == 32 && !file_mips_opts.oddspreg) | |
20473 | fpabi = Val_GNU_MIPS_ABI_FP_64A; | |
20474 | else if (file_mips_opts.gp == 32) | |
20475 | fpabi = Val_GNU_MIPS_ABI_FP_64; | |
20476 | else | |
20477 | fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE; | |
20478 | break; | |
20479 | } | |
20480 | } | |
20481 | ||
20482 | bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, | |
20483 | Tag_GNU_MIPS_ABI_FP, fpabi); | |
20484 | } | |
fd5c94ab | 20485 | } |
2f0c68f2 CM |
20486 | |
20487 | /* Returns the relocation type required for a particular CFI encoding. */ | |
20488 | ||
20489 | bfd_reloc_code_real_type | |
20490 | mips_cfi_reloc_for_encoding (int encoding) | |
20491 | { | |
20492 | if (encoding == (DW_EH_PE_sdata4 | DW_EH_PE_pcrel)) | |
20493 | return BFD_RELOC_32_PCREL; | |
20494 | else return BFD_RELOC_NONE; | |
20495 | } |