Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
81912461 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
f17c130b | 3 | 2003, 2004, 2005 Free Software Foundation, Inc. |
252b5132 RH |
4 | Contributed by the OSF and Ralph Campbell. |
5 | Written by Keith Knowles and Ralph Campbell, working independently. | |
6 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
7 | Support. | |
8 | ||
9 | This file is part of GAS. | |
10 | ||
11 | GAS is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2, or (at your option) | |
14 | any later version. | |
15 | ||
16 | GAS is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with GAS; see the file COPYING. If not, write to the Free | |
23 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
24 | 02111-1307, USA. */ | |
25 | ||
26 | #include "as.h" | |
27 | #include "config.h" | |
28 | #include "subsegs.h" | |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | |
252b5132 | 31 | #include <stdarg.h> |
252b5132 RH |
32 | |
33 | #include "opcode/mips.h" | |
34 | #include "itbl-ops.h" | |
c5dd6aab | 35 | #include "dwarf2dbg.h" |
252b5132 RH |
36 | |
37 | #ifdef DEBUG | |
38 | #define DBG(x) printf x | |
39 | #else | |
40 | #define DBG(x) | |
41 | #endif | |
42 | ||
43 | #ifdef OBJ_MAYBE_ELF | |
44 | /* Clean up namespace so we can include obj-elf.h too. */ | |
17a2f251 TS |
45 | static int mips_output_flavor (void); |
46 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
47 | #undef OBJ_PROCESS_STAB |
48 | #undef OUTPUT_FLAVOR | |
49 | #undef S_GET_ALIGN | |
50 | #undef S_GET_SIZE | |
51 | #undef S_SET_ALIGN | |
52 | #undef S_SET_SIZE | |
252b5132 RH |
53 | #undef obj_frob_file |
54 | #undef obj_frob_file_after_relocs | |
55 | #undef obj_frob_symbol | |
56 | #undef obj_pop_insert | |
57 | #undef obj_sec_sym_ok_for_reloc | |
58 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
59 | ||
60 | #include "obj-elf.h" | |
61 | /* Fix any of them that we actually care about. */ | |
62 | #undef OUTPUT_FLAVOR | |
63 | #define OUTPUT_FLAVOR mips_output_flavor() | |
64 | #endif | |
65 | ||
66 | #if defined (OBJ_ELF) | |
67 | #include "elf/mips.h" | |
68 | #endif | |
69 | ||
70 | #ifndef ECOFF_DEBUGGING | |
71 | #define NO_ECOFF_DEBUGGING | |
72 | #define ECOFF_DEBUGGING 0 | |
73 | #endif | |
74 | ||
ecb4347a DJ |
75 | int mips_flag_mdebug = -1; |
76 | ||
dcd410fe RO |
77 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
78 | linker doesn't know about and discards them, but relocations against them | |
79 | remain, leading to rld crashes. */ | |
80 | #ifdef TE_IRIX | |
81 | int mips_flag_pdr = FALSE; | |
82 | #else | |
83 | int mips_flag_pdr = TRUE; | |
84 | #endif | |
85 | ||
252b5132 RH |
86 | #include "ecoff.h" |
87 | ||
88 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
89 | static char *mips_regmask_frag; | |
90 | #endif | |
91 | ||
85b51719 | 92 | #define ZERO 0 |
252b5132 RH |
93 | #define AT 1 |
94 | #define TREG 24 | |
95 | #define PIC_CALL_REG 25 | |
96 | #define KT0 26 | |
97 | #define KT1 27 | |
98 | #define GP 28 | |
99 | #define SP 29 | |
100 | #define FP 30 | |
101 | #define RA 31 | |
102 | ||
103 | #define ILLEGAL_REG (32) | |
104 | ||
105 | /* Allow override of standard little-endian ECOFF format. */ | |
106 | ||
107 | #ifndef ECOFF_LITTLE_FORMAT | |
108 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
109 | #endif | |
110 | ||
111 | extern int target_big_endian; | |
112 | ||
252b5132 | 113 | /* The name of the readonly data section. */ |
4d0d148d | 114 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ |
252b5132 | 115 | ? ".rdata" \ |
056350c6 NC |
116 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
117 | ? ".rdata" \ | |
252b5132 RH |
118 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
119 | ? ".rodata" \ | |
120 | : (abort (), "")) | |
121 | ||
47e39b9d RS |
122 | /* Information about an instruction, including its format, operands |
123 | and fixups. */ | |
124 | struct mips_cl_insn | |
125 | { | |
126 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ | |
127 | const struct mips_opcode *insn_mo; | |
128 | ||
129 | /* True if this is a mips16 instruction and if we want the extended | |
130 | form of INSN_MO. */ | |
131 | bfd_boolean use_extend; | |
132 | ||
133 | /* The 16-bit extension instruction to use when USE_EXTEND is true. */ | |
134 | unsigned short extend; | |
135 | ||
136 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is | |
137 | a copy of INSN_MO->match with the operands filled in. */ | |
138 | unsigned long insn_opcode; | |
139 | ||
140 | /* The frag that contains the instruction. */ | |
141 | struct frag *frag; | |
142 | ||
143 | /* The offset into FRAG of the first instruction byte. */ | |
144 | long where; | |
145 | ||
146 | /* The relocs associated with the instruction, if any. */ | |
147 | fixS *fixp[3]; | |
148 | ||
a38419a5 RS |
149 | /* True if this entry cannot be moved from its current position. */ |
150 | unsigned int fixed_p : 1; | |
47e39b9d RS |
151 | |
152 | /* True if this instruction occured in a .set noreorder block. */ | |
153 | unsigned int noreorder_p : 1; | |
154 | ||
2fa15973 RS |
155 | /* True for mips16 instructions that jump to an absolute address. */ |
156 | unsigned int mips16_absolute_jump_p : 1; | |
47e39b9d RS |
157 | }; |
158 | ||
a325df1d TS |
159 | /* The ABI to use. */ |
160 | enum mips_abi_level | |
161 | { | |
162 | NO_ABI = 0, | |
163 | O32_ABI, | |
164 | O64_ABI, | |
165 | N32_ABI, | |
166 | N64_ABI, | |
167 | EABI_ABI | |
168 | }; | |
169 | ||
170 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 171 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 172 | |
143d77c5 EC |
173 | /* Whether or not we have code that can call pic code. */ |
174 | int mips_abicalls = FALSE; | |
175 | ||
aa6975fb ILT |
176 | /* Whether or not we have code which can be put into a shared |
177 | library. */ | |
178 | static bfd_boolean mips_in_shared = TRUE; | |
179 | ||
252b5132 RH |
180 | /* This is the set of options which may be modified by the .set |
181 | pseudo-op. We use a struct so that .set push and .set pop are more | |
182 | reliable. */ | |
183 | ||
e972090a NC |
184 | struct mips_set_options |
185 | { | |
252b5132 RH |
186 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
187 | if it has not been initialized. Changed by `.set mipsN', and the | |
188 | -mipsN command line option, and the default CPU. */ | |
189 | int isa; | |
1f25f5d3 CD |
190 | /* Enabled Application Specific Extensions (ASEs). These are set to -1 |
191 | if they have not been initialized. Changed by `.set <asename>', by | |
192 | command line options, and based on the default architecture. */ | |
193 | int ase_mips3d; | |
deec1734 | 194 | int ase_mdmx; |
252b5132 RH |
195 | /* Whether we are assembling for the mips16 processor. 0 if we are |
196 | not, 1 if we are, and -1 if the value has not been initialized. | |
197 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
198 | -nomips16 command line options, and the default CPU. */ | |
199 | int mips16; | |
200 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
201 | reorder' and `.set noreorder'. */ | |
202 | int noreorder; | |
203 | /* Non-zero if we should not permit the $at ($1) register to be used | |
204 | in instructions. Changed by `.set at' and `.set noat'. */ | |
205 | int noat; | |
206 | /* Non-zero if we should warn when a macro instruction expands into | |
207 | more than one machine instruction. Changed by `.set nomacro' and | |
208 | `.set macro'. */ | |
209 | int warn_about_macros; | |
210 | /* Non-zero if we should not move instructions. Changed by `.set | |
211 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
212 | int nomove; | |
213 | /* Non-zero if we should not optimize branches by moving the target | |
214 | of the branch into the delay slot. Actually, we don't perform | |
215 | this optimization anyhow. Changed by `.set bopt' and `.set | |
216 | nobopt'. */ | |
217 | int nobopt; | |
218 | /* Non-zero if we should not autoextend mips16 instructions. | |
219 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
220 | int noautoextend; | |
a325df1d TS |
221 | /* Restrict general purpose registers and floating point registers |
222 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
223 | is passed but can changed if the assembler code uses .set mipsN. */ | |
224 | int gp32; | |
225 | int fp32; | |
fef14a42 TS |
226 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
227 | command line option, and the default CPU. */ | |
228 | int arch; | |
aed1a261 RS |
229 | /* True if ".set sym32" is in effect. */ |
230 | bfd_boolean sym32; | |
252b5132 RH |
231 | }; |
232 | ||
a325df1d | 233 | /* True if -mgp32 was passed. */ |
a8e8e863 | 234 | static int file_mips_gp32 = -1; |
a325df1d TS |
235 | |
236 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 237 | static int file_mips_fp32 = -1; |
a325df1d | 238 | |
252b5132 | 239 | /* This is the struct we use to hold the current set of options. Note |
a4672219 | 240 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to |
e7af610e | 241 | -1 to indicate that they have not been initialized. */ |
252b5132 | 242 | |
e972090a NC |
243 | static struct mips_set_options mips_opts = |
244 | { | |
aed1a261 | 245 | ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN, FALSE |
e7af610e | 246 | }; |
252b5132 RH |
247 | |
248 | /* These variables are filled in with the masks of registers used. | |
249 | The object format code reads them and puts them in the appropriate | |
250 | place. */ | |
251 | unsigned long mips_gprmask; | |
252 | unsigned long mips_cprmask[4]; | |
253 | ||
254 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 255 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 256 | |
a4672219 TS |
257 | /* True if -mips16 was passed or implied by arguments passed on the |
258 | command line (e.g., by -march). */ | |
259 | static int file_ase_mips16; | |
260 | ||
1f25f5d3 CD |
261 | /* True if -mips3d was passed or implied by arguments passed on the |
262 | command line (e.g., by -march). */ | |
263 | static int file_ase_mips3d; | |
264 | ||
deec1734 CD |
265 | /* True if -mdmx was passed or implied by arguments passed on the |
266 | command line (e.g., by -march). */ | |
267 | static int file_ase_mdmx; | |
268 | ||
ec68c924 | 269 | /* The argument of the -march= flag. The architecture we are assembling. */ |
fef14a42 | 270 | static int file_mips_arch = CPU_UNKNOWN; |
316f5878 | 271 | static const char *mips_arch_string; |
ec68c924 EC |
272 | |
273 | /* The argument of the -mtune= flag. The architecture for which we | |
274 | are optimizing. */ | |
275 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 276 | static const char *mips_tune_string; |
ec68c924 | 277 | |
316f5878 | 278 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
279 | static int mips_32bitmode = 0; |
280 | ||
316f5878 RS |
281 | /* True if the given ABI requires 32-bit registers. */ |
282 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
283 | ||
284 | /* Likewise 64-bit registers. */ | |
285 | #define ABI_NEEDS_64BIT_REGS(ABI) \ | |
286 | ((ABI) == N32_ABI \ | |
287 | || (ABI) == N64_ABI \ | |
288 | || (ABI) == O64_ABI) | |
289 | ||
bdaaa2e1 | 290 | /* Return true if ISA supports 64 bit gp register instructions. */ |
9ce8a5dd | 291 | #define ISA_HAS_64BIT_REGS(ISA) ( \ |
e7af610e NC |
292 | (ISA) == ISA_MIPS3 \ |
293 | || (ISA) == ISA_MIPS4 \ | |
84ea6cf2 | 294 | || (ISA) == ISA_MIPS5 \ |
d1cf510e | 295 | || (ISA) == ISA_MIPS64 \ |
5f74bc13 | 296 | || (ISA) == ISA_MIPS64R2 \ |
9ce8a5dd GRK |
297 | ) |
298 | ||
af7ee8bf CD |
299 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
300 | instructions. */ | |
301 | #define ISA_HAS_DROR(ISA) ( \ | |
5f74bc13 | 302 | (ISA) == ISA_MIPS64R2 \ |
af7ee8bf CD |
303 | ) |
304 | ||
305 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
306 | instructions. */ | |
307 | #define ISA_HAS_ROR(ISA) ( \ | |
308 | (ISA) == ISA_MIPS32R2 \ | |
5f74bc13 | 309 | || (ISA) == ISA_MIPS64R2 \ |
af7ee8bf CD |
310 | ) |
311 | ||
e013f690 | 312 | #define HAVE_32BIT_GPRS \ |
316f5878 | 313 | (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 314 | |
e013f690 | 315 | #define HAVE_32BIT_FPRS \ |
316f5878 | 316 | (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 RS |
317 | |
318 | #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS) | |
319 | #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS) | |
320 | ||
316f5878 | 321 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 322 | |
316f5878 | 323 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 324 | |
3b91255e RS |
325 | /* True if relocations are stored in-place. */ |
326 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
327 | ||
aed1a261 RS |
328 | /* The ABI-derived address size. */ |
329 | #define HAVE_64BIT_ADDRESSES \ | |
330 | (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) | |
331 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) | |
e013f690 | 332 | |
aed1a261 RS |
333 | /* The size of symbolic constants (i.e., expressions of the form |
334 | "SYMBOL" or "SYMBOL + OFFSET"). */ | |
335 | #define HAVE_32BIT_SYMBOLS \ | |
336 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) | |
337 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) | |
ca4e0257 | 338 | |
b7c7d6c1 TS |
339 | /* Addresses are loaded in different ways, depending on the address size |
340 | in use. The n32 ABI Documentation also mandates the use of additions | |
341 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 342 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 343 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
344 | |
345 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 346 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
347 | |
348 | #define ADDRESS_LOAD_INSN \ | |
349 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
350 | ||
351 | #define ADDRESS_STORE_INSN \ | |
352 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
353 | ||
a4672219 | 354 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
355 | #define CPU_HAS_MIPS16(cpu) \ |
356 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
357 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 358 | |
1f25f5d3 CD |
359 | /* Return true if the given CPU supports the MIPS3D ASE. */ |
360 | #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \ | |
361 | ) | |
362 | ||
deec1734 | 363 | /* Return true if the given CPU supports the MDMX ASE. */ |
b34976b6 | 364 | #define CPU_HAS_MDMX(cpu) (FALSE \ |
deec1734 CD |
365 | ) |
366 | ||
60b63b72 RS |
367 | /* True if CPU has a dror instruction. */ |
368 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
369 | ||
370 | /* True if CPU has a ror instruction. */ | |
371 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
372 | ||
c8978940 CD |
373 | /* True if mflo and mfhi can be immediately followed by instructions |
374 | which write to the HI and LO registers. | |
375 | ||
376 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
377 | (at least) two instructions between the reads of HI/LO and | |
378 | instructions which write them, and later ISAs do not. Contradicting | |
379 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
380 | the UM for the NEC Vr5000) document needing the instructions between | |
381 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
382 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
383 | earlier-ISA CPUs for which CPU documentation declares that the | |
384 | instructions are really interlocked. */ | |
385 | #define hilo_interlocks \ | |
386 | (mips_opts.isa == ISA_MIPS32 \ | |
387 | || mips_opts.isa == ISA_MIPS32R2 \ | |
388 | || mips_opts.isa == ISA_MIPS64 \ | |
389 | || mips_opts.isa == ISA_MIPS64R2 \ | |
390 | || mips_opts.arch == CPU_R4010 \ | |
391 | || mips_opts.arch == CPU_R10000 \ | |
392 | || mips_opts.arch == CPU_R12000 \ | |
393 | || mips_opts.arch == CPU_RM7000 \ | |
c8978940 CD |
394 | || mips_opts.arch == CPU_VR5500 \ |
395 | ) | |
252b5132 RH |
396 | |
397 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
398 | from the GPRs after they are loaded from memory, and thus does not |
399 | require nops to be inserted. This applies to instructions marked | |
400 | INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA | |
401 | level I. */ | |
252b5132 | 402 | #define gpr_interlocks \ |
e7af610e | 403 | (mips_opts.isa != ISA_MIPS1 \ |
fef14a42 | 404 | || mips_opts.arch == CPU_R3900) |
252b5132 | 405 | |
81912461 ILT |
406 | /* Whether the processor uses hardware interlocks to avoid delays |
407 | required by coprocessor instructions, and thus does not require | |
408 | nops to be inserted. This applies to instructions marked | |
409 | INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays | |
410 | between instructions marked INSN_WRITE_COND_CODE and ones marked | |
411 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA | |
412 | levels I, II, and III. */ | |
bdaaa2e1 | 413 | /* Itbl support may require additional care here. */ |
81912461 ILT |
414 | #define cop_interlocks \ |
415 | ((mips_opts.isa != ISA_MIPS1 \ | |
416 | && mips_opts.isa != ISA_MIPS2 \ | |
417 | && mips_opts.isa != ISA_MIPS3) \ | |
418 | || mips_opts.arch == CPU_R4300 \ | |
81912461 ILT |
419 | ) |
420 | ||
421 | /* Whether the processor uses hardware interlocks to protect reads | |
422 | from coprocessor registers after they are loaded from memory, and | |
423 | thus does not require nops to be inserted. This applies to | |
424 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
425 | requires at MIPS ISA level I. */ | |
426 | #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1) | |
252b5132 | 427 | |
6b76fefe CM |
428 | /* Is this a mfhi or mflo instruction? */ |
429 | #define MF_HILO_INSN(PINFO) \ | |
430 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) | |
431 | ||
252b5132 RH |
432 | /* MIPS PIC level. */ |
433 | ||
a161fe53 | 434 | enum mips_pic_level mips_pic; |
252b5132 | 435 | |
c9914766 | 436 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 437 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 438 | static int mips_big_got = 0; |
252b5132 RH |
439 | |
440 | /* 1 if trap instructions should used for overflow rather than break | |
441 | instructions. */ | |
c9914766 | 442 | static int mips_trap = 0; |
252b5132 | 443 | |
119d663a | 444 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 445 | by assembling two single width halves into two single width floating |
119d663a NC |
446 | point registers which just happen to alias the double width destination |
447 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 448 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
449 | automatically at assemble time. */ |
450 | static int mips_disable_float_construction; | |
451 | ||
252b5132 RH |
452 | /* Non-zero if any .set noreorder directives were used. */ |
453 | ||
454 | static int mips_any_noreorder; | |
455 | ||
6b76fefe CM |
456 | /* Non-zero if nops should be inserted when the register referenced in |
457 | an mfhi/mflo instruction is read in the next two instructions. */ | |
458 | static int mips_7000_hilo_fix; | |
459 | ||
252b5132 | 460 | /* The size of the small data section. */ |
156c2f8b | 461 | static unsigned int g_switch_value = 8; |
252b5132 RH |
462 | /* Whether the -G option was used. */ |
463 | static int g_switch_seen = 0; | |
464 | ||
465 | #define N_RMASK 0xc4 | |
466 | #define N_VFP 0xd4 | |
467 | ||
468 | /* If we can determine in advance that GP optimization won't be | |
469 | possible, we can skip the relaxation stuff that tries to produce | |
470 | GP-relative references. This makes delay slot optimization work | |
471 | better. | |
472 | ||
473 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
474 | gcc output. It needs to guess right for gcc, otherwise gcc |
475 | will put what it thinks is a GP-relative instruction in a branch | |
476 | delay slot. | |
252b5132 RH |
477 | |
478 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
479 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 480 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
481 | |
482 | /* handle of the OPCODE hash table */ | |
483 | static struct hash_control *op_hash = NULL; | |
484 | ||
485 | /* The opcode hash table we use for the mips16. */ | |
486 | static struct hash_control *mips16_op_hash = NULL; | |
487 | ||
488 | /* This array holds the chars that always start a comment. If the | |
489 | pre-processor is disabled, these aren't very useful */ | |
490 | const char comment_chars[] = "#"; | |
491 | ||
492 | /* This array holds the chars that only start a comment at the beginning of | |
493 | a line. If the line seems to have the form '# 123 filename' | |
494 | .line and .file directives will appear in the pre-processed output */ | |
495 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
496 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 497 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
498 | /* Also note that C style comments are always supported. */ |
499 | const char line_comment_chars[] = "#"; | |
500 | ||
bdaaa2e1 | 501 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 502 | const char line_separator_chars[] = ";"; |
252b5132 RH |
503 | |
504 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
505 | const char EXP_CHARS[] = "eE"; | |
506 | ||
507 | /* Chars that mean this number is a floating point constant */ | |
508 | /* As in 0f12.456 */ | |
509 | /* or 0d1.2345e12 */ | |
510 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
511 | ||
512 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
513 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
514 | but nothing is ideal around here. | |
515 | */ | |
516 | ||
517 | static char *insn_error; | |
518 | ||
519 | static int auto_align = 1; | |
520 | ||
521 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
522 | offset in the stack frame from which to restore the $gp register. | |
523 | This is set by the .cprestore pseudo-op, and saved in this | |
524 | variable. */ | |
525 | static offsetT mips_cprestore_offset = -1; | |
526 | ||
67c1ffbe | 527 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 528 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 529 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
530 | static offsetT mips_cpreturn_offset = -1; |
531 | static int mips_cpreturn_register = -1; | |
532 | static int mips_gp_register = GP; | |
def2e0dd | 533 | static int mips_gprel_offset = 0; |
6478892d | 534 | |
7a621144 DJ |
535 | /* Whether mips_cprestore_offset has been set in the current function |
536 | (or whether it has already been warned about, if not). */ | |
537 | static int mips_cprestore_valid = 0; | |
538 | ||
252b5132 RH |
539 | /* This is the register which holds the stack frame, as set by the |
540 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
541 | static int mips_frame_reg = SP; | |
542 | ||
7a621144 DJ |
543 | /* Whether mips_frame_reg has been set in the current function |
544 | (or whether it has already been warned about, if not). */ | |
545 | static int mips_frame_reg_valid = 0; | |
546 | ||
252b5132 RH |
547 | /* To output NOP instructions correctly, we need to keep information |
548 | about the previous two instructions. */ | |
549 | ||
550 | /* Whether we are optimizing. The default value of 2 means to remove | |
551 | unneeded NOPs and swap branch instructions when possible. A value | |
552 | of 1 means to not swap branches. A value of 0 means to always | |
553 | insert NOPs. */ | |
554 | static int mips_optimize = 2; | |
555 | ||
556 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
557 | equivalent to seeing no -g option at all. */ | |
558 | static int mips_debug = 0; | |
559 | ||
71400594 RS |
560 | /* The maximum number of NOPs needed to satisfy a hardware hazard |
561 | or processor errata. */ | |
562 | #define MAX_NOPS 2 | |
563 | ||
564 | /* A list of previous instructions, with index 0 being the most recent. | |
565 | We need to look back MAX_NOPS instructions when filling delay slots | |
566 | or working around processor errata. We need to look back one | |
567 | instruction further if we're thinking about using history[0] to | |
568 | fill a branch delay slot. */ | |
569 | static struct mips_cl_insn history[1 + MAX_NOPS]; | |
252b5132 | 570 | |
1e915849 RS |
571 | /* Nop instructions used by emit_nop. */ |
572 | static struct mips_cl_insn nop_insn, mips16_nop_insn; | |
573 | ||
574 | /* The appropriate nop for the current mode. */ | |
575 | #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn) | |
252b5132 | 576 | |
252b5132 RH |
577 | /* If this is set, it points to a frag holding nop instructions which |
578 | were inserted before the start of a noreorder section. If those | |
579 | nops turn out to be unnecessary, the size of the frag can be | |
580 | decreased. */ | |
581 | static fragS *prev_nop_frag; | |
582 | ||
583 | /* The number of nop instructions we created in prev_nop_frag. */ | |
584 | static int prev_nop_frag_holds; | |
585 | ||
586 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 587 | prev_nop_frag. */ |
252b5132 RH |
588 | static int prev_nop_frag_required; |
589 | ||
590 | /* The number of instructions we've seen since prev_nop_frag. */ | |
591 | static int prev_nop_frag_since; | |
592 | ||
593 | /* For ECOFF and ELF, relocations against symbols are done in two | |
594 | parts, with a HI relocation and a LO relocation. Each relocation | |
595 | has only 16 bits of space to store an addend. This means that in | |
596 | order for the linker to handle carries correctly, it must be able | |
597 | to locate both the HI and the LO relocation. This means that the | |
598 | relocations must appear in order in the relocation table. | |
599 | ||
600 | In order to implement this, we keep track of each unmatched HI | |
601 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 602 | corresponding LO relocation. */ |
252b5132 | 603 | |
e972090a NC |
604 | struct mips_hi_fixup |
605 | { | |
252b5132 RH |
606 | /* Next HI fixup. */ |
607 | struct mips_hi_fixup *next; | |
608 | /* This fixup. */ | |
609 | fixS *fixp; | |
610 | /* The section this fixup is in. */ | |
611 | segT seg; | |
612 | }; | |
613 | ||
614 | /* The list of unmatched HI relocs. */ | |
615 | ||
616 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
617 | ||
64bdfcaf RS |
618 | /* The frag containing the last explicit relocation operator. |
619 | Null if explicit relocations have not been used. */ | |
620 | ||
621 | static fragS *prev_reloc_op_frag; | |
622 | ||
252b5132 RH |
623 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
624 | ||
625 | #define X ILLEGAL_REG | |
e972090a NC |
626 | static const int mips32_to_16_reg_map[] = |
627 | { | |
252b5132 RH |
628 | X, X, 2, 3, 4, 5, 6, 7, |
629 | X, X, X, X, X, X, X, X, | |
630 | 0, 1, X, X, X, X, X, X, | |
631 | X, X, X, X, X, X, X, X | |
632 | }; | |
633 | #undef X | |
634 | ||
635 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
636 | ||
e972090a NC |
637 | static const unsigned int mips16_to_32_reg_map[] = |
638 | { | |
252b5132 RH |
639 | 16, 17, 2, 3, 4, 5, 6, 7 |
640 | }; | |
60b63b72 | 641 | |
71400594 RS |
642 | /* Classifies the kind of instructions we're interested in when |
643 | implementing -mfix-vr4120. */ | |
644 | enum fix_vr4120_class { | |
645 | FIX_VR4120_MACC, | |
646 | FIX_VR4120_DMACC, | |
647 | FIX_VR4120_MULT, | |
648 | FIX_VR4120_DMULT, | |
649 | FIX_VR4120_DIV, | |
650 | FIX_VR4120_MTHILO, | |
651 | NUM_FIX_VR4120_CLASSES | |
652 | }; | |
653 | ||
654 | /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if | |
655 | there must be at least one other instruction between an instruction | |
656 | of type X and an instruction of type Y. */ | |
657 | static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; | |
658 | ||
659 | /* True if -mfix-vr4120 is in force. */ | |
d766e8ec | 660 | static int mips_fix_vr4120; |
4a6a3df4 AO |
661 | |
662 | /* We don't relax branches by default, since this causes us to expand | |
663 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
664 | fail to compute the offset before expanding the macro to the most | |
665 | efficient expansion. */ | |
666 | ||
667 | static int mips_relax_branch; | |
252b5132 | 668 | \f |
4d7206a2 RS |
669 | /* The expansion of many macros depends on the type of symbol that |
670 | they refer to. For example, when generating position-dependent code, | |
671 | a macro that refers to a symbol may have two different expansions, | |
672 | one which uses GP-relative addresses and one which uses absolute | |
673 | addresses. When generating SVR4-style PIC, a macro may have | |
674 | different expansions for local and global symbols. | |
675 | ||
676 | We handle these situations by generating both sequences and putting | |
677 | them in variant frags. In position-dependent code, the first sequence | |
678 | will be the GP-relative one and the second sequence will be the | |
679 | absolute one. In SVR4 PIC, the first sequence will be for global | |
680 | symbols and the second will be for local symbols. | |
681 | ||
584892a6 RS |
682 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
683 | SECOND are the lengths of the two sequences in bytes. These fields | |
684 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
685 | the subtype has the following flags: | |
4d7206a2 | 686 | |
584892a6 RS |
687 | RELAX_USE_SECOND |
688 | Set if it has been decided that we should use the second | |
689 | sequence instead of the first. | |
690 | ||
691 | RELAX_SECOND_LONGER | |
692 | Set in the first variant frag if the macro's second implementation | |
693 | is longer than its first. This refers to the macro as a whole, | |
694 | not an individual relaxation. | |
695 | ||
696 | RELAX_NOMACRO | |
697 | Set in the first variant frag if the macro appeared in a .set nomacro | |
698 | block and if one alternative requires a warning but the other does not. | |
699 | ||
700 | RELAX_DELAY_SLOT | |
701 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
702 | delay slot. | |
4d7206a2 RS |
703 | |
704 | The frag's "opcode" points to the first fixup for relaxable code. | |
705 | ||
706 | Relaxable macros are generated using a sequence such as: | |
707 | ||
708 | relax_start (SYMBOL); | |
709 | ... generate first expansion ... | |
710 | relax_switch (); | |
711 | ... generate second expansion ... | |
712 | relax_end (); | |
713 | ||
714 | The code and fixups for the unwanted alternative are discarded | |
715 | by md_convert_frag. */ | |
584892a6 | 716 | #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) |
4d7206a2 | 717 | |
584892a6 RS |
718 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
719 | #define RELAX_SECOND(X) ((X) & 0xff) | |
720 | #define RELAX_USE_SECOND 0x10000 | |
721 | #define RELAX_SECOND_LONGER 0x20000 | |
722 | #define RELAX_NOMACRO 0x40000 | |
723 | #define RELAX_DELAY_SLOT 0x80000 | |
252b5132 | 724 | |
4a6a3df4 AO |
725 | /* Branch without likely bit. If label is out of range, we turn: |
726 | ||
727 | beq reg1, reg2, label | |
728 | delay slot | |
729 | ||
730 | into | |
731 | ||
732 | bne reg1, reg2, 0f | |
733 | nop | |
734 | j label | |
735 | 0: delay slot | |
736 | ||
737 | with the following opcode replacements: | |
738 | ||
739 | beq <-> bne | |
740 | blez <-> bgtz | |
741 | bltz <-> bgez | |
742 | bc1f <-> bc1t | |
743 | ||
744 | bltzal <-> bgezal (with jal label instead of j label) | |
745 | ||
746 | Even though keeping the delay slot instruction in the delay slot of | |
747 | the branch would be more efficient, it would be very tricky to do | |
748 | correctly, because we'd have to introduce a variable frag *after* | |
749 | the delay slot instruction, and expand that instead. Let's do it | |
750 | the easy way for now, even if the branch-not-taken case now costs | |
751 | one additional instruction. Out-of-range branches are not supposed | |
752 | to be common, anyway. | |
753 | ||
754 | Branch likely. If label is out of range, we turn: | |
755 | ||
756 | beql reg1, reg2, label | |
757 | delay slot (annulled if branch not taken) | |
758 | ||
759 | into | |
760 | ||
761 | beql reg1, reg2, 1f | |
762 | nop | |
763 | beql $0, $0, 2f | |
764 | nop | |
765 | 1: j[al] label | |
766 | delay slot (executed only if branch taken) | |
767 | 2: | |
768 | ||
769 | It would be possible to generate a shorter sequence by losing the | |
770 | likely bit, generating something like: | |
b34976b6 | 771 | |
4a6a3df4 AO |
772 | bne reg1, reg2, 0f |
773 | nop | |
774 | j[al] label | |
775 | delay slot (executed only if branch taken) | |
776 | 0: | |
777 | ||
778 | beql -> bne | |
779 | bnel -> beq | |
780 | blezl -> bgtz | |
781 | bgtzl -> blez | |
782 | bltzl -> bgez | |
783 | bgezl -> bltz | |
784 | bc1fl -> bc1t | |
785 | bc1tl -> bc1f | |
786 | ||
787 | bltzall -> bgezal (with jal label instead of j label) | |
788 | bgezall -> bltzal (ditto) | |
789 | ||
790 | ||
791 | but it's not clear that it would actually improve performance. */ | |
af6ae2ad | 792 | #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \ |
4a6a3df4 AO |
793 | ((relax_substateT) \ |
794 | (0xc0000000 \ | |
795 | | ((toofar) ? 1 : 0) \ | |
796 | | ((link) ? 2 : 0) \ | |
797 | | ((likely) ? 4 : 0) \ | |
af6ae2ad | 798 | | ((uncond) ? 8 : 0))) |
4a6a3df4 | 799 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
4a6a3df4 AO |
800 | #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0) |
801 | #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0) | |
802 | #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0) | |
ae6063d4 | 803 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0) |
4a6a3df4 | 804 | |
252b5132 RH |
805 | /* For mips16 code, we use an entirely different form of relaxation. |
806 | mips16 supports two versions of most instructions which take | |
807 | immediate values: a small one which takes some small value, and a | |
808 | larger one which takes a 16 bit value. Since branches also follow | |
809 | this pattern, relaxing these values is required. | |
810 | ||
811 | We can assemble both mips16 and normal MIPS code in a single | |
812 | object. Therefore, we need to support this type of relaxation at | |
813 | the same time that we support the relaxation described above. We | |
814 | use the high bit of the subtype field to distinguish these cases. | |
815 | ||
816 | The information we store for this type of relaxation is the | |
817 | argument code found in the opcode file for this relocation, whether | |
818 | the user explicitly requested a small or extended form, and whether | |
819 | the relocation is in a jump or jal delay slot. That tells us the | |
820 | size of the value, and how it should be stored. We also store | |
821 | whether the fragment is considered to be extended or not. We also | |
822 | store whether this is known to be a branch to a different section, | |
823 | whether we have tried to relax this frag yet, and whether we have | |
824 | ever extended a PC relative fragment because of a shift count. */ | |
825 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
826 | (0x80000000 \ | |
827 | | ((type) & 0xff) \ | |
828 | | ((small) ? 0x100 : 0) \ | |
829 | | ((ext) ? 0x200 : 0) \ | |
830 | | ((dslot) ? 0x400 : 0) \ | |
831 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 832 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
833 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
834 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
835 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
836 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
837 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
838 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
839 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
840 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
841 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
842 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
843 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 CD |
844 | |
845 | /* Is the given value a sign-extended 32-bit value? */ | |
846 | #define IS_SEXT_32BIT_NUM(x) \ | |
847 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
848 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
849 | ||
850 | /* Is the given value a sign-extended 16-bit value? */ | |
851 | #define IS_SEXT_16BIT_NUM(x) \ | |
852 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
853 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
854 | ||
bf12938e RS |
855 | /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in |
856 | VALUE << SHIFT. VALUE is evaluated exactly once. */ | |
857 | #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \ | |
858 | (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \ | |
859 | | (((VALUE) & (MASK)) << (SHIFT))) | |
860 | ||
861 | /* Extract bits MASK << SHIFT from STRUCT and shift them right | |
862 | SHIFT places. */ | |
863 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
864 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
865 | ||
866 | /* Change INSN's opcode so that the operand given by FIELD has value VALUE. | |
867 | INSN is a mips_cl_insn structure and VALUE is evaluated exactly once. | |
868 | ||
869 | include/opcode/mips.h specifies operand fields using the macros | |
870 | OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start | |
871 | with "MIPS16OP" instead of "OP". */ | |
872 | #define INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
873 | INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD) | |
874 | #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
875 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
876 | MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD) | |
877 | ||
878 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ | |
879 | #define EXTRACT_OPERAND(FIELD, INSN) \ | |
880 | EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) | |
881 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ | |
882 | EXTRACT_BITS ((INSN).insn_opcode, \ | |
883 | MIPS16OP_MASK_##FIELD, \ | |
884 | MIPS16OP_SH_##FIELD) | |
4d7206a2 RS |
885 | \f |
886 | /* Global variables used when generating relaxable macros. See the | |
887 | comment above RELAX_ENCODE for more details about how relaxation | |
888 | is used. */ | |
889 | static struct { | |
890 | /* 0 if we're not emitting a relaxable macro. | |
891 | 1 if we're emitting the first of the two relaxation alternatives. | |
892 | 2 if we're emitting the second alternative. */ | |
893 | int sequence; | |
894 | ||
895 | /* The first relaxable fixup in the current frag. (In other words, | |
896 | the first fixup that refers to relaxable code.) */ | |
897 | fixS *first_fixup; | |
898 | ||
899 | /* sizes[0] says how many bytes of the first alternative are stored in | |
900 | the current frag. Likewise sizes[1] for the second alternative. */ | |
901 | unsigned int sizes[2]; | |
902 | ||
903 | /* The symbol on which the choice of sequence depends. */ | |
904 | symbolS *symbol; | |
905 | } mips_relax; | |
252b5132 | 906 | \f |
584892a6 RS |
907 | /* Global variables used to decide whether a macro needs a warning. */ |
908 | static struct { | |
909 | /* True if the macro is in a branch delay slot. */ | |
910 | bfd_boolean delay_slot_p; | |
911 | ||
912 | /* For relaxable macros, sizes[0] is the length of the first alternative | |
913 | in bytes and sizes[1] is the length of the second alternative. | |
914 | For non-relaxable macros, both elements give the length of the | |
915 | macro in bytes. */ | |
916 | unsigned int sizes[2]; | |
917 | ||
918 | /* The first variant frag for this macro. */ | |
919 | fragS *first_frag; | |
920 | } mips_macro_warning; | |
921 | \f | |
252b5132 RH |
922 | /* Prototypes for static functions. */ |
923 | ||
17a2f251 | 924 | #define internalError() \ |
252b5132 | 925 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) |
252b5132 RH |
926 | |
927 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
928 | ||
b34976b6 | 929 | static void append_insn |
4d7206a2 | 930 | (struct mips_cl_insn *ip, expressionS *p, bfd_reloc_code_real_type *r); |
17a2f251 | 931 | static void mips_no_prev_insn (int); |
b34976b6 | 932 | static void mips16_macro_build |
67c0d1eb RS |
933 | (expressionS *, const char *, const char *, va_list); |
934 | static void load_register (int, expressionS *, int); | |
584892a6 RS |
935 | static void macro_start (void); |
936 | static void macro_end (void); | |
17a2f251 TS |
937 | static void macro (struct mips_cl_insn * ip); |
938 | static void mips16_macro (struct mips_cl_insn * ip); | |
252b5132 | 939 | #ifdef LOSING_COMPILER |
17a2f251 | 940 | static void macro2 (struct mips_cl_insn * ip); |
252b5132 | 941 | #endif |
17a2f251 TS |
942 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
943 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 944 | static void mips16_immed |
17a2f251 TS |
945 | (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean, |
946 | unsigned long *, bfd_boolean *, unsigned short *); | |
5e0116d5 | 947 | static size_t my_getSmallExpression |
17a2f251 TS |
948 | (expressionS *, bfd_reloc_code_real_type *, char *); |
949 | static void my_getExpression (expressionS *, char *); | |
950 | static void s_align (int); | |
951 | static void s_change_sec (int); | |
952 | static void s_change_section (int); | |
953 | static void s_cons (int); | |
954 | static void s_float_cons (int); | |
955 | static void s_mips_globl (int); | |
956 | static void s_option (int); | |
957 | static void s_mipsset (int); | |
958 | static void s_abicalls (int); | |
959 | static void s_cpload (int); | |
960 | static void s_cpsetup (int); | |
961 | static void s_cplocal (int); | |
962 | static void s_cprestore (int); | |
963 | static void s_cpreturn (int); | |
964 | static void s_gpvalue (int); | |
965 | static void s_gpword (int); | |
966 | static void s_gpdword (int); | |
967 | static void s_cpadd (int); | |
968 | static void s_insn (int); | |
969 | static void md_obj_begin (void); | |
970 | static void md_obj_end (void); | |
971 | static void s_mips_ent (int); | |
972 | static void s_mips_end (int); | |
973 | static void s_mips_frame (int); | |
974 | static void s_mips_mask (int reg_type); | |
975 | static void s_mips_stab (int); | |
976 | static void s_mips_weakext (int); | |
977 | static void s_mips_file (int); | |
978 | static void s_mips_loc (int); | |
979 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 980 | static int relaxed_branch_length (fragS *, asection *, int); |
17a2f251 | 981 | static int validate_mips_insn (const struct mips_opcode *); |
e7af610e NC |
982 | |
983 | /* Table and functions used to map between CPU/ISA names, and | |
984 | ISA levels, and CPU numbers. */ | |
985 | ||
e972090a NC |
986 | struct mips_cpu_info |
987 | { | |
e7af610e NC |
988 | const char *name; /* CPU or ISA name. */ |
989 | int is_isa; /* Is this an ISA? (If 0, a CPU.) */ | |
990 | int isa; /* ISA level. */ | |
991 | int cpu; /* CPU number (default CPU if ISA). */ | |
992 | }; | |
993 | ||
17a2f251 TS |
994 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
995 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
996 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 RH |
997 | \f |
998 | /* Pseudo-op table. | |
999 | ||
1000 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
1001 | should be defined here, but are currently unsupported: .alias, | |
1002 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
1003 | ||
1004 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1005 | specific to the type of debugging information being generated, and | |
1006 | should be defined by the object format: .aent, .begin, .bend, | |
1007 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
1008 | .vreg. | |
1009 | ||
1010 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1011 | not MIPS CPU specific, but are also not specific to the object file | |
1012 | format. This file is probably the best place to define them, but | |
1013 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
1014 | .struct. */ | |
1015 | ||
e972090a NC |
1016 | static const pseudo_typeS mips_pseudo_table[] = |
1017 | { | |
beae10d5 | 1018 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1019 | {"option", s_option, 0}, |
1020 | {"set", s_mipsset, 0}, | |
1021 | {"rdata", s_change_sec, 'r'}, | |
1022 | {"sdata", s_change_sec, 's'}, | |
1023 | {"livereg", s_ignore, 0}, | |
1024 | {"abicalls", s_abicalls, 0}, | |
1025 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1026 | {"cpsetup", s_cpsetup, 0}, |
1027 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1028 | {"cprestore", s_cprestore, 0}, |
6478892d TS |
1029 | {"cpreturn", s_cpreturn, 0}, |
1030 | {"gpvalue", s_gpvalue, 0}, | |
252b5132 | 1031 | {"gpword", s_gpword, 0}, |
10181a0d | 1032 | {"gpdword", s_gpdword, 0}, |
252b5132 RH |
1033 | {"cpadd", s_cpadd, 0}, |
1034 | {"insn", s_insn, 0}, | |
1035 | ||
beae10d5 | 1036 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 RH |
1037 | chips. */ |
1038 | {"asciiz", stringer, 1}, | |
1039 | {"bss", s_change_sec, 'b'}, | |
1040 | {"err", s_err, 0}, | |
1041 | {"half", s_cons, 1}, | |
1042 | {"dword", s_cons, 3}, | |
1043 | {"weakext", s_mips_weakext, 0}, | |
1044 | ||
beae10d5 | 1045 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1046 | here for one reason or another. */ |
1047 | {"align", s_align, 0}, | |
1048 | {"byte", s_cons, 0}, | |
1049 | {"data", s_change_sec, 'd'}, | |
1050 | {"double", s_float_cons, 'd'}, | |
1051 | {"float", s_float_cons, 'f'}, | |
1052 | {"globl", s_mips_globl, 0}, | |
1053 | {"global", s_mips_globl, 0}, | |
1054 | {"hword", s_cons, 1}, | |
1055 | {"int", s_cons, 2}, | |
1056 | {"long", s_cons, 2}, | |
1057 | {"octa", s_cons, 4}, | |
1058 | {"quad", s_cons, 3}, | |
cca86cc8 | 1059 | {"section", s_change_section, 0}, |
252b5132 RH |
1060 | {"short", s_cons, 1}, |
1061 | {"single", s_float_cons, 'f'}, | |
1062 | {"stabn", s_mips_stab, 'n'}, | |
1063 | {"text", s_change_sec, 't'}, | |
1064 | {"word", s_cons, 2}, | |
add56521 | 1065 | |
add56521 | 1066 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1067 | |
43841e91 | 1068 | { NULL, NULL, 0 }, |
252b5132 RH |
1069 | }; |
1070 | ||
e972090a NC |
1071 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1072 | { | |
beae10d5 KH |
1073 | /* These pseudo-ops should be defined by the object file format. |
1074 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1075 | {"aent", s_mips_ent, 1}, |
1076 | {"bgnb", s_ignore, 0}, | |
1077 | {"end", s_mips_end, 0}, | |
1078 | {"endb", s_ignore, 0}, | |
1079 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1080 | {"file", s_mips_file, 0}, |
252b5132 RH |
1081 | {"fmask", s_mips_mask, 'F'}, |
1082 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1083 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1084 | {"mask", s_mips_mask, 'R'}, |
1085 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1086 | { NULL, NULL, 0 }, |
252b5132 RH |
1087 | }; |
1088 | ||
17a2f251 | 1089 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1090 | |
1091 | void | |
17a2f251 | 1092 | mips_pop_insert (void) |
252b5132 RH |
1093 | { |
1094 | pop_insert (mips_pseudo_table); | |
1095 | if (! ECOFF_DEBUGGING) | |
1096 | pop_insert (mips_nonecoff_pseudo_table); | |
1097 | } | |
1098 | \f | |
1099 | /* Symbols labelling the current insn. */ | |
1100 | ||
e972090a NC |
1101 | struct insn_label_list |
1102 | { | |
252b5132 RH |
1103 | struct insn_label_list *next; |
1104 | symbolS *label; | |
1105 | }; | |
1106 | ||
1107 | static struct insn_label_list *insn_labels; | |
1108 | static struct insn_label_list *free_insn_labels; | |
1109 | ||
17a2f251 | 1110 | static void mips_clear_insn_labels (void); |
252b5132 RH |
1111 | |
1112 | static inline void | |
17a2f251 | 1113 | mips_clear_insn_labels (void) |
252b5132 RH |
1114 | { |
1115 | register struct insn_label_list **pl; | |
1116 | ||
1117 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1118 | ; | |
1119 | *pl = insn_labels; | |
1120 | insn_labels = NULL; | |
1121 | } | |
1122 | \f | |
1123 | static char *expr_end; | |
1124 | ||
1125 | /* Expressions which appear in instructions. These are set by | |
1126 | mips_ip. */ | |
1127 | ||
1128 | static expressionS imm_expr; | |
5f74bc13 | 1129 | static expressionS imm2_expr; |
252b5132 RH |
1130 | static expressionS offset_expr; |
1131 | ||
1132 | /* Relocs associated with imm_expr and offset_expr. */ | |
1133 | ||
f6688943 TS |
1134 | static bfd_reloc_code_real_type imm_reloc[3] |
1135 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
1136 | static bfd_reloc_code_real_type offset_reloc[3] | |
1137 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1138 | |
252b5132 RH |
1139 | /* These are set by mips16_ip if an explicit extension is used. */ |
1140 | ||
b34976b6 | 1141 | static bfd_boolean mips16_small, mips16_ext; |
252b5132 | 1142 | |
7ed4a06a | 1143 | #ifdef OBJ_ELF |
ecb4347a DJ |
1144 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1145 | ECOFF debugging. */ | |
252b5132 RH |
1146 | |
1147 | static segT pdr_seg; | |
7ed4a06a | 1148 | #endif |
252b5132 | 1149 | |
e013f690 TS |
1150 | /* The default target format to use. */ |
1151 | ||
1152 | const char * | |
17a2f251 | 1153 | mips_target_format (void) |
e013f690 TS |
1154 | { |
1155 | switch (OUTPUT_FLAVOR) | |
1156 | { | |
e013f690 TS |
1157 | case bfd_target_ecoff_flavour: |
1158 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
1159 | case bfd_target_coff_flavour: | |
1160 | return "pe-mips"; | |
1161 | case bfd_target_elf_flavour: | |
1162 | #ifdef TE_TMIPS | |
cfe86eaa | 1163 | /* This is traditional mips. */ |
e013f690 | 1164 | return (target_big_endian |
cfe86eaa TS |
1165 | ? (HAVE_64BIT_OBJECTS |
1166 | ? "elf64-tradbigmips" | |
1167 | : (HAVE_NEWABI | |
1168 | ? "elf32-ntradbigmips" : "elf32-tradbigmips")) | |
1169 | : (HAVE_64BIT_OBJECTS | |
1170 | ? "elf64-tradlittlemips" | |
1171 | : (HAVE_NEWABI | |
1172 | ? "elf32-ntradlittlemips" : "elf32-tradlittlemips"))); | |
e013f690 TS |
1173 | #else |
1174 | return (target_big_endian | |
cfe86eaa TS |
1175 | ? (HAVE_64BIT_OBJECTS |
1176 | ? "elf64-bigmips" | |
1177 | : (HAVE_NEWABI | |
1178 | ? "elf32-nbigmips" : "elf32-bigmips")) | |
1179 | : (HAVE_64BIT_OBJECTS | |
1180 | ? "elf64-littlemips" | |
1181 | : (HAVE_NEWABI | |
1182 | ? "elf32-nlittlemips" : "elf32-littlemips"))); | |
e013f690 TS |
1183 | #endif |
1184 | default: | |
1185 | abort (); | |
1186 | return NULL; | |
1187 | } | |
1188 | } | |
1189 | ||
1e915849 RS |
1190 | /* Return the length of instruction INSN. */ |
1191 | ||
1192 | static inline unsigned int | |
1193 | insn_length (const struct mips_cl_insn *insn) | |
1194 | { | |
1195 | if (!mips_opts.mips16) | |
1196 | return 4; | |
1197 | return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2; | |
1198 | } | |
1199 | ||
1200 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
1201 | ||
1202 | static void | |
1203 | create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) | |
1204 | { | |
1205 | size_t i; | |
1206 | ||
1207 | insn->insn_mo = mo; | |
1208 | insn->use_extend = FALSE; | |
1209 | insn->extend = 0; | |
1210 | insn->insn_opcode = mo->match; | |
1211 | insn->frag = NULL; | |
1212 | insn->where = 0; | |
1213 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1214 | insn->fixp[i] = NULL; | |
1215 | insn->fixed_p = (mips_opts.noreorder > 0); | |
1216 | insn->noreorder_p = (mips_opts.noreorder > 0); | |
1217 | insn->mips16_absolute_jump_p = 0; | |
1218 | } | |
1219 | ||
1220 | /* Install INSN at the location specified by its "frag" and "where" fields. */ | |
1221 | ||
1222 | static void | |
1223 | install_insn (const struct mips_cl_insn *insn) | |
1224 | { | |
1225 | char *f = insn->frag->fr_literal + insn->where; | |
1226 | if (!mips_opts.mips16) | |
1227 | md_number_to_chars (f, insn->insn_opcode, 4); | |
1228 | else if (insn->mips16_absolute_jump_p) | |
1229 | { | |
1230 | md_number_to_chars (f, insn->insn_opcode >> 16, 2); | |
1231 | md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2); | |
1232 | } | |
1233 | else | |
1234 | { | |
1235 | if (insn->use_extend) | |
1236 | { | |
1237 | md_number_to_chars (f, 0xf000 | insn->extend, 2); | |
1238 | f += 2; | |
1239 | } | |
1240 | md_number_to_chars (f, insn->insn_opcode, 2); | |
1241 | } | |
1242 | } | |
1243 | ||
1244 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
1245 | and install the opcode in the new location. */ | |
1246 | ||
1247 | static void | |
1248 | move_insn (struct mips_cl_insn *insn, fragS *frag, long where) | |
1249 | { | |
1250 | size_t i; | |
1251 | ||
1252 | insn->frag = frag; | |
1253 | insn->where = where; | |
1254 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
1255 | if (insn->fixp[i] != NULL) | |
1256 | { | |
1257 | insn->fixp[i]->fx_frag = frag; | |
1258 | insn->fixp[i]->fx_where = where; | |
1259 | } | |
1260 | install_insn (insn); | |
1261 | } | |
1262 | ||
1263 | /* Add INSN to the end of the output. */ | |
1264 | ||
1265 | static void | |
1266 | add_fixed_insn (struct mips_cl_insn *insn) | |
1267 | { | |
1268 | char *f = frag_more (insn_length (insn)); | |
1269 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
1270 | } | |
1271 | ||
1272 | /* Start a variant frag and move INSN to the start of the variant part, | |
1273 | marking it as fixed. The other arguments are as for frag_var. */ | |
1274 | ||
1275 | static void | |
1276 | add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, | |
1277 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
1278 | { | |
1279 | frag_grow (max_chars); | |
1280 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
1281 | insn->fixed_p = 1; | |
1282 | frag_var (rs_machine_dependent, max_chars, var, | |
1283 | subtype, symbol, offset, NULL); | |
1284 | } | |
1285 | ||
1286 | /* Insert N copies of INSN into the history buffer, starting at | |
1287 | position FIRST. Neither FIRST nor N need to be clipped. */ | |
1288 | ||
1289 | static void | |
1290 | insert_into_history (unsigned int first, unsigned int n, | |
1291 | const struct mips_cl_insn *insn) | |
1292 | { | |
1293 | if (mips_relax.sequence != 2) | |
1294 | { | |
1295 | unsigned int i; | |
1296 | ||
1297 | for (i = ARRAY_SIZE (history); i-- > first;) | |
1298 | if (i >= first + n) | |
1299 | history[i] = history[i - n]; | |
1300 | else | |
1301 | history[i] = *insn; | |
1302 | } | |
1303 | } | |
1304 | ||
1305 | /* Emit a nop instruction, recording it in the history buffer. */ | |
1306 | ||
1307 | static void | |
1308 | emit_nop (void) | |
1309 | { | |
1310 | add_fixed_insn (NOP_INSN); | |
1311 | insert_into_history (0, 1, NOP_INSN); | |
1312 | } | |
1313 | ||
71400594 RS |
1314 | /* Initialize vr4120_conflicts. There is a bit of duplication here: |
1315 | the idea is to make it obvious at a glance that each errata is | |
1316 | included. */ | |
1317 | ||
1318 | static void | |
1319 | init_vr4120_conflicts (void) | |
1320 | { | |
1321 | #define CONFLICT(FIRST, SECOND) \ | |
1322 | vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND | |
1323 | ||
1324 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
1325 | CONFLICT (MACC, DIV); | |
1326 | CONFLICT (DMACC, DIV); | |
1327 | ||
1328 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ | |
1329 | CONFLICT (DMULT, DMULT); | |
1330 | CONFLICT (DMULT, DMACC); | |
1331 | CONFLICT (DMACC, DMULT); | |
1332 | CONFLICT (DMACC, DMACC); | |
1333 | ||
1334 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
1335 | CONFLICT (MACC, MTHILO); | |
1336 | CONFLICT (DMACC, MTHILO); | |
1337 | ||
1338 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU | |
1339 | instruction is executed immediately after a MACC or DMACC | |
1340 | instruction, the result of [either instruction] is incorrect." */ | |
1341 | CONFLICT (MACC, MULT); | |
1342 | CONFLICT (MACC, DMULT); | |
1343 | CONFLICT (DMACC, MULT); | |
1344 | CONFLICT (DMACC, DMULT); | |
1345 | ||
1346 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
1347 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
1348 | DDIV or DDIVU instruction, the result of the MACC or | |
1349 | DMACC instruction is incorrect.". */ | |
1350 | CONFLICT (DMULT, MACC); | |
1351 | CONFLICT (DMULT, DMACC); | |
1352 | CONFLICT (DIV, MACC); | |
1353 | CONFLICT (DIV, DMACC); | |
1354 | ||
1355 | #undef CONFLICT | |
1356 | } | |
1357 | ||
156c2f8b NC |
1358 | /* This function is called once, at assembler startup time. It should |
1359 | set up all the tables, etc. that the MD part of the assembler will need. */ | |
1360 | ||
252b5132 | 1361 | void |
17a2f251 | 1362 | md_begin (void) |
252b5132 | 1363 | { |
252b5132 | 1364 | register const char *retval = NULL; |
156c2f8b | 1365 | int i = 0; |
252b5132 | 1366 | int broken = 0; |
1f25f5d3 | 1367 | |
fef14a42 | 1368 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) |
252b5132 RH |
1369 | as_warn (_("Could not set architecture and machine")); |
1370 | ||
252b5132 RH |
1371 | op_hash = hash_new (); |
1372 | ||
1373 | for (i = 0; i < NUMOPCODES;) | |
1374 | { | |
1375 | const char *name = mips_opcodes[i].name; | |
1376 | ||
17a2f251 | 1377 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
1378 | if (retval != NULL) |
1379 | { | |
1380 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
1381 | mips_opcodes[i].name, retval); | |
1382 | /* Probably a memory allocation problem? Give up now. */ | |
1383 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1384 | } | |
1385 | do | |
1386 | { | |
1387 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
1388 | { | |
1389 | if (!validate_mips_insn (&mips_opcodes[i])) | |
1390 | broken = 1; | |
1e915849 RS |
1391 | if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
1392 | { | |
1393 | create_insn (&nop_insn, mips_opcodes + i); | |
1394 | nop_insn.fixed_p = 1; | |
1395 | } | |
252b5132 RH |
1396 | } |
1397 | ++i; | |
1398 | } | |
1399 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
1400 | } | |
1401 | ||
1402 | mips16_op_hash = hash_new (); | |
1403 | ||
1404 | i = 0; | |
1405 | while (i < bfd_mips16_num_opcodes) | |
1406 | { | |
1407 | const char *name = mips16_opcodes[i].name; | |
1408 | ||
17a2f251 | 1409 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
1410 | if (retval != NULL) |
1411 | as_fatal (_("internal: can't hash `%s': %s"), | |
1412 | mips16_opcodes[i].name, retval); | |
1413 | do | |
1414 | { | |
1415 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1416 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1417 | != mips16_opcodes[i].match)) | |
1418 | { | |
1419 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
1420 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1421 | broken = 1; | |
1422 | } | |
1e915849 RS |
1423 | if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
1424 | { | |
1425 | create_insn (&mips16_nop_insn, mips16_opcodes + i); | |
1426 | mips16_nop_insn.fixed_p = 1; | |
1427 | } | |
252b5132 RH |
1428 | ++i; |
1429 | } | |
1430 | while (i < bfd_mips16_num_opcodes | |
1431 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1432 | } | |
1433 | ||
1434 | if (broken) | |
1435 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1436 | ||
1437 | /* We add all the general register names to the symbol table. This | |
1438 | helps us detect invalid uses of them. */ | |
1439 | for (i = 0; i < 32; i++) | |
1440 | { | |
1441 | char buf[5]; | |
1442 | ||
1443 | sprintf (buf, "$%d", i); | |
1444 | symbol_table_insert (symbol_new (buf, reg_section, i, | |
1445 | &zero_address_frag)); | |
1446 | } | |
76db943d TS |
1447 | symbol_table_insert (symbol_new ("$ra", reg_section, RA, |
1448 | &zero_address_frag)); | |
252b5132 RH |
1449 | symbol_table_insert (symbol_new ("$fp", reg_section, FP, |
1450 | &zero_address_frag)); | |
1451 | symbol_table_insert (symbol_new ("$sp", reg_section, SP, | |
1452 | &zero_address_frag)); | |
1453 | symbol_table_insert (symbol_new ("$gp", reg_section, GP, | |
1454 | &zero_address_frag)); | |
1455 | symbol_table_insert (symbol_new ("$at", reg_section, AT, | |
1456 | &zero_address_frag)); | |
1457 | symbol_table_insert (symbol_new ("$kt0", reg_section, KT0, | |
1458 | &zero_address_frag)); | |
1459 | symbol_table_insert (symbol_new ("$kt1", reg_section, KT1, | |
1460 | &zero_address_frag)); | |
85b51719 TS |
1461 | symbol_table_insert (symbol_new ("$zero", reg_section, ZERO, |
1462 | &zero_address_frag)); | |
252b5132 RH |
1463 | symbol_table_insert (symbol_new ("$pc", reg_section, -1, |
1464 | &zero_address_frag)); | |
1465 | ||
6047c971 AO |
1466 | /* If we don't add these register names to the symbol table, they |
1467 | may end up being added as regular symbols by operand(), and then | |
1468 | make it to the object file as undefined in case they're not | |
1469 | regarded as local symbols. They're local in o32, since `$' is a | |
1470 | local symbol prefix, but not in n32 or n64. */ | |
1471 | for (i = 0; i < 8; i++) | |
1472 | { | |
1473 | char buf[6]; | |
1474 | ||
1475 | sprintf (buf, "$fcc%i", i); | |
1476 | symbol_table_insert (symbol_new (buf, reg_section, -1, | |
1477 | &zero_address_frag)); | |
1478 | } | |
1479 | ||
b34976b6 | 1480 | mips_no_prev_insn (FALSE); |
252b5132 RH |
1481 | |
1482 | mips_gprmask = 0; | |
1483 | mips_cprmask[0] = 0; | |
1484 | mips_cprmask[1] = 0; | |
1485 | mips_cprmask[2] = 0; | |
1486 | mips_cprmask[3] = 0; | |
1487 | ||
1488 | /* set the default alignment for the text section (2**2) */ | |
1489 | record_alignment (text_section, 2); | |
1490 | ||
4d0d148d | 1491 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 RH |
1492 | |
1493 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1494 | { | |
1495 | /* On a native system, sections must be aligned to 16 byte | |
1496 | boundaries. When configured for an embedded ELF target, we | |
1497 | don't bother. */ | |
1498 | if (strcmp (TARGET_OS, "elf") != 0) | |
1499 | { | |
1500 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
1501 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
1502 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
1503 | } | |
1504 | ||
1505 | /* Create a .reginfo section for register masks and a .mdebug | |
1506 | section for debugging information. */ | |
1507 | { | |
1508 | segT seg; | |
1509 | subsegT subseg; | |
1510 | flagword flags; | |
1511 | segT sec; | |
1512 | ||
1513 | seg = now_seg; | |
1514 | subseg = now_subseg; | |
1515 | ||
1516 | /* The ABI says this section should be loaded so that the | |
1517 | running program can access it. However, we don't load it | |
1518 | if we are configured for an embedded target */ | |
1519 | flags = SEC_READONLY | SEC_DATA; | |
1520 | if (strcmp (TARGET_OS, "elf") != 0) | |
1521 | flags |= SEC_ALLOC | SEC_LOAD; | |
1522 | ||
316f5878 | 1523 | if (mips_abi != N64_ABI) |
252b5132 RH |
1524 | { |
1525 | sec = subseg_new (".reginfo", (subsegT) 0); | |
1526 | ||
195325d2 TS |
1527 | bfd_set_section_flags (stdoutput, sec, flags); |
1528 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
bdaaa2e1 | 1529 | |
252b5132 RH |
1530 | #ifdef OBJ_ELF |
1531 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); | |
1532 | #endif | |
1533 | } | |
1534 | else | |
1535 | { | |
1536 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
1537 | .reginfo section. */ | |
1538 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
195325d2 TS |
1539 | bfd_set_section_flags (stdoutput, sec, flags); |
1540 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 RH |
1541 | |
1542 | #ifdef OBJ_ELF | |
1543 | /* Set up the option header. */ | |
1544 | { | |
1545 | Elf_Internal_Options opthdr; | |
1546 | char *f; | |
1547 | ||
1548 | opthdr.kind = ODK_REGINFO; | |
1549 | opthdr.size = (sizeof (Elf_External_Options) | |
1550 | + sizeof (Elf64_External_RegInfo)); | |
1551 | opthdr.section = 0; | |
1552 | opthdr.info = 0; | |
1553 | f = frag_more (sizeof (Elf_External_Options)); | |
1554 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
1555 | (Elf_External_Options *) f); | |
1556 | ||
1557 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
1558 | } | |
1559 | #endif | |
1560 | } | |
1561 | ||
1562 | if (ECOFF_DEBUGGING) | |
1563 | { | |
1564 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1565 | (void) bfd_set_section_flags (stdoutput, sec, | |
1566 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1567 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1568 | } | |
ecb4347a | 1569 | #ifdef OBJ_ELF |
dcd410fe | 1570 | else if (OUTPUT_FLAVOR == bfd_target_elf_flavour && mips_flag_pdr) |
ecb4347a DJ |
1571 | { |
1572 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
1573 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
1574 | SEC_READONLY | SEC_RELOC | |
1575 | | SEC_DEBUGGING); | |
1576 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
1577 | } | |
252b5132 RH |
1578 | #endif |
1579 | ||
1580 | subseg_set (seg, subseg); | |
1581 | } | |
1582 | } | |
1583 | ||
1584 | if (! ECOFF_DEBUGGING) | |
1585 | md_obj_begin (); | |
71400594 RS |
1586 | |
1587 | if (mips_fix_vr4120) | |
1588 | init_vr4120_conflicts (); | |
252b5132 RH |
1589 | } |
1590 | ||
1591 | void | |
17a2f251 | 1592 | md_mips_end (void) |
252b5132 RH |
1593 | { |
1594 | if (! ECOFF_DEBUGGING) | |
1595 | md_obj_end (); | |
1596 | } | |
1597 | ||
1598 | void | |
17a2f251 | 1599 | md_assemble (char *str) |
252b5132 RH |
1600 | { |
1601 | struct mips_cl_insn insn; | |
f6688943 TS |
1602 | bfd_reloc_code_real_type unused_reloc[3] |
1603 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
1604 | |
1605 | imm_expr.X_op = O_absent; | |
5f74bc13 | 1606 | imm2_expr.X_op = O_absent; |
252b5132 | 1607 | offset_expr.X_op = O_absent; |
f6688943 TS |
1608 | imm_reloc[0] = BFD_RELOC_UNUSED; |
1609 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
1610 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
1611 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
1612 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
1613 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
1614 | |
1615 | if (mips_opts.mips16) | |
1616 | mips16_ip (str, &insn); | |
1617 | else | |
1618 | { | |
1619 | mips_ip (str, &insn); | |
beae10d5 KH |
1620 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
1621 | str, insn.insn_opcode)); | |
252b5132 RH |
1622 | } |
1623 | ||
1624 | if (insn_error) | |
1625 | { | |
1626 | as_bad ("%s `%s'", insn_error, str); | |
1627 | return; | |
1628 | } | |
1629 | ||
1630 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
1631 | { | |
584892a6 | 1632 | macro_start (); |
252b5132 RH |
1633 | if (mips_opts.mips16) |
1634 | mips16_macro (&insn); | |
1635 | else | |
1636 | macro (&insn); | |
584892a6 | 1637 | macro_end (); |
252b5132 RH |
1638 | } |
1639 | else | |
1640 | { | |
1641 | if (imm_expr.X_op != O_absent) | |
4d7206a2 | 1642 | append_insn (&insn, &imm_expr, imm_reloc); |
252b5132 | 1643 | else if (offset_expr.X_op != O_absent) |
4d7206a2 | 1644 | append_insn (&insn, &offset_expr, offset_reloc); |
252b5132 | 1645 | else |
4d7206a2 | 1646 | append_insn (&insn, NULL, unused_reloc); |
252b5132 RH |
1647 | } |
1648 | } | |
1649 | ||
5919d012 RS |
1650 | /* Return true if the given relocation might need a matching %lo(). |
1651 | Note that R_MIPS_GOT16 relocations only need a matching %lo() when | |
1652 | applied to local symbols. */ | |
1653 | ||
1654 | static inline bfd_boolean | |
17a2f251 | 1655 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 1656 | { |
3b91255e RS |
1657 | return (HAVE_IN_PLACE_ADDENDS |
1658 | && (reloc == BFD_RELOC_HI16_S | |
d6f16593 MR |
1659 | || reloc == BFD_RELOC_MIPS_GOT16 |
1660 | || reloc == BFD_RELOC_MIPS16_HI16_S)); | |
5919d012 RS |
1661 | } |
1662 | ||
1663 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
1664 | relocation. */ | |
1665 | ||
1666 | static inline bfd_boolean | |
17a2f251 | 1667 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
1668 | { |
1669 | return (fixp->fx_next != NULL | |
d6f16593 MR |
1670 | && (fixp->fx_next->fx_r_type == BFD_RELOC_LO16 |
1671 | || fixp->fx_next->fx_r_type == BFD_RELOC_MIPS16_LO16) | |
5919d012 RS |
1672 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
1673 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
1674 | } | |
1675 | ||
252b5132 RH |
1676 | /* See whether instruction IP reads register REG. CLASS is the type |
1677 | of register. */ | |
1678 | ||
1679 | static int | |
71400594 | 1680 | insn_uses_reg (const struct mips_cl_insn *ip, unsigned int reg, |
17a2f251 | 1681 | enum mips_regclass class) |
252b5132 RH |
1682 | { |
1683 | if (class == MIPS16_REG) | |
1684 | { | |
1685 | assert (mips_opts.mips16); | |
1686 | reg = mips16_to_32_reg_map[reg]; | |
1687 | class = MIPS_GR_REG; | |
1688 | } | |
1689 | ||
85b51719 TS |
1690 | /* Don't report on general register ZERO, since it never changes. */ |
1691 | if (class == MIPS_GR_REG && reg == ZERO) | |
252b5132 RH |
1692 | return 0; |
1693 | ||
1694 | if (class == MIPS_FP_REG) | |
1695 | { | |
1696 | assert (! mips_opts.mips16); | |
1697 | /* If we are called with either $f0 or $f1, we must check $f0. | |
1698 | This is not optimal, because it will introduce an unnecessary | |
1699 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
1700 | need to distinguish reading both $f0 and $f1 or just one of | |
1701 | them. Note that we don't have to check the other way, | |
1702 | because there is no instruction that sets both $f0 and $f1 | |
1703 | and requires a delay. */ | |
1704 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
bf12938e | 1705 | && ((EXTRACT_OPERAND (FS, *ip) & ~(unsigned) 1) |
252b5132 RH |
1706 | == (reg &~ (unsigned) 1))) |
1707 | return 1; | |
1708 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
bf12938e | 1709 | && ((EXTRACT_OPERAND (FT, *ip) & ~(unsigned) 1) |
252b5132 RH |
1710 | == (reg &~ (unsigned) 1))) |
1711 | return 1; | |
1712 | } | |
1713 | else if (! mips_opts.mips16) | |
1714 | { | |
1715 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
bf12938e | 1716 | && EXTRACT_OPERAND (RS, *ip) == reg) |
252b5132 RH |
1717 | return 1; |
1718 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
bf12938e | 1719 | && EXTRACT_OPERAND (RT, *ip) == reg) |
252b5132 RH |
1720 | return 1; |
1721 | } | |
1722 | else | |
1723 | { | |
1724 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
bf12938e | 1725 | && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)] == reg) |
252b5132 RH |
1726 | return 1; |
1727 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
bf12938e | 1728 | && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)] == reg) |
252b5132 RH |
1729 | return 1; |
1730 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
bf12938e | 1731 | && (mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)] |
252b5132 RH |
1732 | == reg)) |
1733 | return 1; | |
1734 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
1735 | return 1; | |
1736 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
1737 | return 1; | |
1738 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
1739 | return 1; | |
1740 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
bf12938e | 1741 | && MIPS16_EXTRACT_OPERAND (REGR32, *ip) == reg) |
252b5132 RH |
1742 | return 1; |
1743 | } | |
1744 | ||
1745 | return 0; | |
1746 | } | |
1747 | ||
1748 | /* This function returns true if modifying a register requires a | |
1749 | delay. */ | |
1750 | ||
1751 | static int | |
17a2f251 | 1752 | reg_needs_delay (unsigned int reg) |
252b5132 RH |
1753 | { |
1754 | unsigned long prev_pinfo; | |
1755 | ||
47e39b9d | 1756 | prev_pinfo = history[0].insn_mo->pinfo; |
252b5132 | 1757 | if (! mips_opts.noreorder |
81912461 ILT |
1758 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
1759 | && ! gpr_interlocks) | |
1760 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
1761 | && ! cop_interlocks))) | |
252b5132 | 1762 | { |
81912461 ILT |
1763 | /* A load from a coprocessor or from memory. All load delays |
1764 | delay the use of general register rt for one instruction. */ | |
bdaaa2e1 | 1765 | /* Itbl support may require additional care here. */ |
252b5132 | 1766 | know (prev_pinfo & INSN_WRITE_GPR_T); |
bf12938e | 1767 | if (reg == EXTRACT_OPERAND (RT, history[0])) |
252b5132 RH |
1768 | return 1; |
1769 | } | |
1770 | ||
1771 | return 0; | |
1772 | } | |
1773 | ||
1774 | /* Mark instruction labels in mips16 mode. This permits the linker to | |
1775 | handle them specially, such as generating jalx instructions when | |
1776 | needed. We also make them odd for the duration of the assembly, in | |
1777 | order to generate the right sort of code. We will make them even | |
1778 | in the adjust_symtab routine, while leaving them marked. This is | |
1779 | convenient for the debugger and the disassembler. The linker knows | |
1780 | to make them odd again. */ | |
1781 | ||
1782 | static void | |
17a2f251 | 1783 | mips16_mark_labels (void) |
252b5132 RH |
1784 | { |
1785 | if (mips_opts.mips16) | |
1786 | { | |
1787 | struct insn_label_list *l; | |
98aa84af | 1788 | valueT val; |
252b5132 RH |
1789 | |
1790 | for (l = insn_labels; l != NULL; l = l->next) | |
1791 | { | |
1792 | #ifdef OBJ_ELF | |
1793 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1794 | S_SET_OTHER (l->label, STO_MIPS16); | |
1795 | #endif | |
98aa84af AM |
1796 | val = S_GET_VALUE (l->label); |
1797 | if ((val & 1) == 0) | |
1798 | S_SET_VALUE (l->label, val + 1); | |
252b5132 RH |
1799 | } |
1800 | } | |
1801 | } | |
1802 | ||
4d7206a2 RS |
1803 | /* End the current frag. Make it a variant frag and record the |
1804 | relaxation info. */ | |
1805 | ||
1806 | static void | |
1807 | relax_close_frag (void) | |
1808 | { | |
584892a6 | 1809 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 1810 | frag_var (rs_machine_dependent, 0, 0, |
584892a6 | 1811 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), |
4d7206a2 RS |
1812 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
1813 | ||
1814 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
1815 | mips_relax.first_fixup = 0; | |
1816 | } | |
1817 | ||
1818 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
1819 | See the comment above RELAX_ENCODE for more details. */ | |
1820 | ||
1821 | static void | |
1822 | relax_start (symbolS *symbol) | |
1823 | { | |
1824 | assert (mips_relax.sequence == 0); | |
1825 | mips_relax.sequence = 1; | |
1826 | mips_relax.symbol = symbol; | |
1827 | } | |
1828 | ||
1829 | /* Start generating the second version of a relaxable sequence. | |
1830 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
1831 | |
1832 | static void | |
4d7206a2 RS |
1833 | relax_switch (void) |
1834 | { | |
1835 | assert (mips_relax.sequence == 1); | |
1836 | mips_relax.sequence = 2; | |
1837 | } | |
1838 | ||
1839 | /* End the current relaxable sequence. */ | |
1840 | ||
1841 | static void | |
1842 | relax_end (void) | |
1843 | { | |
1844 | assert (mips_relax.sequence == 2); | |
1845 | relax_close_frag (); | |
1846 | mips_relax.sequence = 0; | |
1847 | } | |
1848 | ||
71400594 RS |
1849 | /* Classify an instruction according to the FIX_VR4120_* enumeration. |
1850 | Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected | |
1851 | by VR4120 errata. */ | |
4d7206a2 | 1852 | |
71400594 RS |
1853 | static unsigned int |
1854 | classify_vr4120_insn (const char *name) | |
252b5132 | 1855 | { |
71400594 RS |
1856 | if (strncmp (name, "macc", 4) == 0) |
1857 | return FIX_VR4120_MACC; | |
1858 | if (strncmp (name, "dmacc", 5) == 0) | |
1859 | return FIX_VR4120_DMACC; | |
1860 | if (strncmp (name, "mult", 4) == 0) | |
1861 | return FIX_VR4120_MULT; | |
1862 | if (strncmp (name, "dmult", 5) == 0) | |
1863 | return FIX_VR4120_DMULT; | |
1864 | if (strstr (name, "div")) | |
1865 | return FIX_VR4120_DIV; | |
1866 | if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) | |
1867 | return FIX_VR4120_MTHILO; | |
1868 | return NUM_FIX_VR4120_CLASSES; | |
1869 | } | |
252b5132 | 1870 | |
71400594 RS |
1871 | /* Return the number of instructions that must separate INSN1 and INSN2, |
1872 | where INSN1 is the earlier instruction. Return the worst-case value | |
1873 | for any INSN2 if INSN2 is null. */ | |
252b5132 | 1874 | |
71400594 RS |
1875 | static unsigned int |
1876 | insns_between (const struct mips_cl_insn *insn1, | |
1877 | const struct mips_cl_insn *insn2) | |
1878 | { | |
1879 | unsigned long pinfo1, pinfo2; | |
1880 | ||
1881 | /* This function needs to know which pinfo flags are set for INSN2 | |
1882 | and which registers INSN2 uses. The former is stored in PINFO2 and | |
1883 | the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2 | |
1884 | will have every flag set and INSN2_USES_REG will always return true. */ | |
1885 | pinfo1 = insn1->insn_mo->pinfo; | |
1886 | pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; | |
252b5132 | 1887 | |
71400594 RS |
1888 | #define INSN2_USES_REG(REG, CLASS) \ |
1889 | (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS)) | |
1890 | ||
1891 | /* For most targets, write-after-read dependencies on the HI and LO | |
1892 | registers must be separated by at least two instructions. */ | |
1893 | if (!hilo_interlocks) | |
252b5132 | 1894 | { |
71400594 RS |
1895 | if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) |
1896 | return 2; | |
1897 | if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) | |
1898 | return 2; | |
1899 | } | |
1900 | ||
1901 | /* If we're working around r7000 errata, there must be two instructions | |
1902 | between an mfhi or mflo and any instruction that uses the result. */ | |
1903 | if (mips_7000_hilo_fix | |
1904 | && MF_HILO_INSN (pinfo1) | |
1905 | && INSN2_USES_REG (EXTRACT_OPERAND (RD, *insn1), MIPS_GR_REG)) | |
1906 | return 2; | |
1907 | ||
1908 | /* If working around VR4120 errata, check for combinations that need | |
1909 | a single intervening instruction. */ | |
1910 | if (mips_fix_vr4120) | |
1911 | { | |
1912 | unsigned int class1, class2; | |
252b5132 | 1913 | |
71400594 RS |
1914 | class1 = classify_vr4120_insn (insn1->insn_mo->name); |
1915 | if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) | |
252b5132 | 1916 | { |
71400594 RS |
1917 | if (insn2 == NULL) |
1918 | return 1; | |
1919 | class2 = classify_vr4120_insn (insn2->insn_mo->name); | |
1920 | if (vr4120_conflicts[class1] & (1 << class2)) | |
1921 | return 1; | |
252b5132 | 1922 | } |
71400594 RS |
1923 | } |
1924 | ||
1925 | if (!mips_opts.mips16) | |
1926 | { | |
1927 | /* Check for GPR or coprocessor load delays. All such delays | |
1928 | are on the RT register. */ | |
1929 | /* Itbl support may require additional care here. */ | |
1930 | if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY)) | |
1931 | || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY))) | |
252b5132 | 1932 | { |
71400594 RS |
1933 | know (pinfo1 & INSN_WRITE_GPR_T); |
1934 | if (INSN2_USES_REG (EXTRACT_OPERAND (RT, *insn1), MIPS_GR_REG)) | |
1935 | return 1; | |
1936 | } | |
1937 | ||
1938 | /* Check for generic coprocessor hazards. | |
1939 | ||
1940 | This case is not handled very well. There is no special | |
1941 | knowledge of CP0 handling, and the coprocessors other than | |
1942 | the floating point unit are not distinguished at all. */ | |
1943 | /* Itbl support may require additional care here. FIXME! | |
1944 | Need to modify this to include knowledge about | |
1945 | user specified delays! */ | |
1946 | else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY)) | |
1947 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) | |
1948 | { | |
1949 | /* Handle cases where INSN1 writes to a known general coprocessor | |
1950 | register. There must be a one instruction delay before INSN2 | |
1951 | if INSN2 reads that register, otherwise no delay is needed. */ | |
1952 | if (pinfo1 & INSN_WRITE_FPR_T) | |
252b5132 | 1953 | { |
71400594 RS |
1954 | if (INSN2_USES_REG (EXTRACT_OPERAND (FT, *insn1), MIPS_FP_REG)) |
1955 | return 1; | |
252b5132 | 1956 | } |
71400594 | 1957 | else if (pinfo1 & INSN_WRITE_FPR_S) |
252b5132 | 1958 | { |
71400594 RS |
1959 | if (INSN2_USES_REG (EXTRACT_OPERAND (FS, *insn1), MIPS_FP_REG)) |
1960 | return 1; | |
252b5132 RH |
1961 | } |
1962 | else | |
1963 | { | |
71400594 RS |
1964 | /* Read-after-write dependencies on the control registers |
1965 | require a two-instruction gap. */ | |
1966 | if ((pinfo1 & INSN_WRITE_COND_CODE) | |
1967 | && (pinfo2 & INSN_READ_COND_CODE)) | |
1968 | return 2; | |
1969 | ||
1970 | /* We don't know exactly what INSN1 does. If INSN2 is | |
1971 | also a coprocessor instruction, assume there must be | |
1972 | a one instruction gap. */ | |
1973 | if (pinfo2 & INSN_COP) | |
1974 | return 1; | |
252b5132 RH |
1975 | } |
1976 | } | |
6b76fefe | 1977 | |
71400594 RS |
1978 | /* Check for read-after-write dependencies on the coprocessor |
1979 | control registers in cases where INSN1 does not need a general | |
1980 | coprocessor delay. This means that INSN1 is a floating point | |
1981 | comparison instruction. */ | |
1982 | /* Itbl support may require additional care here. */ | |
1983 | else if (!cop_interlocks | |
1984 | && (pinfo1 & INSN_WRITE_COND_CODE) | |
1985 | && (pinfo2 & INSN_READ_COND_CODE)) | |
1986 | return 1; | |
1987 | } | |
6b76fefe | 1988 | |
71400594 | 1989 | #undef INSN2_USES_REG |
6b76fefe | 1990 | |
71400594 RS |
1991 | return 0; |
1992 | } | |
6b76fefe | 1993 | |
71400594 RS |
1994 | /* Return the number of nops that would be needed if instruction INSN |
1995 | immediately followed the MAX_NOPS instructions given by HISTORY, | |
1996 | where HISTORY[0] is the most recent instruction. If INSN is null, | |
1997 | return the worse-case number of nops for any instruction. */ | |
bdaaa2e1 | 1998 | |
71400594 RS |
1999 | static int |
2000 | nops_for_insn (const struct mips_cl_insn *history, | |
2001 | const struct mips_cl_insn *insn) | |
2002 | { | |
2003 | int i, nops, tmp_nops; | |
bdaaa2e1 | 2004 | |
71400594 RS |
2005 | nops = 0; |
2006 | for (i = 0; i < MAX_NOPS; i++) | |
2007 | if (!history[i].noreorder_p) | |
2008 | { | |
2009 | tmp_nops = insns_between (history + i, insn) - i; | |
2010 | if (tmp_nops > nops) | |
2011 | nops = tmp_nops; | |
2012 | } | |
2013 | return nops; | |
2014 | } | |
252b5132 | 2015 | |
71400594 RS |
2016 | /* The variable arguments provide NUM_INSNS extra instructions that |
2017 | might be added to HISTORY. Return the largest number of nops that | |
2018 | would be needed after the extended sequence. */ | |
252b5132 | 2019 | |
71400594 RS |
2020 | static int |
2021 | nops_for_sequence (int num_insns, const struct mips_cl_insn *history, ...) | |
2022 | { | |
2023 | va_list args; | |
2024 | struct mips_cl_insn buffer[MAX_NOPS]; | |
2025 | struct mips_cl_insn *cursor; | |
2026 | int nops; | |
2027 | ||
2028 | va_start (args, history); | |
2029 | cursor = buffer + num_insns; | |
2030 | memcpy (cursor, history, (MAX_NOPS - num_insns) * sizeof (*cursor)); | |
2031 | while (cursor > buffer) | |
2032 | *--cursor = *va_arg (args, const struct mips_cl_insn *); | |
2033 | ||
2034 | nops = nops_for_insn (buffer, NULL); | |
2035 | va_end (args); | |
2036 | return nops; | |
2037 | } | |
252b5132 | 2038 | |
71400594 RS |
2039 | /* Like nops_for_insn, but if INSN is a branch, take into account the |
2040 | worst-case delay for the branch target. */ | |
252b5132 | 2041 | |
71400594 RS |
2042 | static int |
2043 | nops_for_insn_or_target (const struct mips_cl_insn *history, | |
2044 | const struct mips_cl_insn *insn) | |
2045 | { | |
2046 | int nops, tmp_nops; | |
60b63b72 | 2047 | |
71400594 RS |
2048 | nops = nops_for_insn (history, insn); |
2049 | if (insn->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY | |
2050 | | INSN_COND_BRANCH_DELAY | |
2051 | | INSN_COND_BRANCH_LIKELY)) | |
2052 | { | |
2053 | tmp_nops = nops_for_sequence (2, history, insn, NOP_INSN); | |
2054 | if (tmp_nops > nops) | |
2055 | nops = tmp_nops; | |
2056 | } | |
2057 | else if (mips_opts.mips16 && (insn->insn_mo->pinfo & MIPS16_INSN_BRANCH)) | |
2058 | { | |
2059 | tmp_nops = nops_for_sequence (1, history, insn); | |
2060 | if (tmp_nops > nops) | |
2061 | nops = tmp_nops; | |
2062 | } | |
2063 | return nops; | |
2064 | } | |
2065 | ||
2066 | /* Output an instruction. IP is the instruction information. | |
2067 | ADDRESS_EXPR is an operand of the instruction to be used with | |
2068 | RELOC_TYPE. */ | |
2069 | ||
2070 | static void | |
2071 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
2072 | bfd_reloc_code_real_type *reloc_type) | |
2073 | { | |
2074 | register unsigned long prev_pinfo, pinfo; | |
2075 | relax_stateT prev_insn_frag_type = 0; | |
2076 | bfd_boolean relaxed_branch = FALSE; | |
2077 | ||
2078 | /* Mark instruction labels in mips16 mode. */ | |
2079 | mips16_mark_labels (); | |
2080 | ||
2081 | prev_pinfo = history[0].insn_mo->pinfo; | |
2082 | pinfo = ip->insn_mo->pinfo; | |
2083 | ||
2084 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) | |
2085 | { | |
2086 | /* There are a lot of optimizations we could do that we don't. | |
2087 | In particular, we do not, in general, reorder instructions. | |
2088 | If you use gcc with optimization, it will reorder | |
2089 | instructions and generally do much more optimization then we | |
2090 | do here; repeating all that work in the assembler would only | |
2091 | benefit hand written assembly code, and does not seem worth | |
2092 | it. */ | |
2093 | int nops = (mips_optimize == 0 | |
2094 | ? nops_for_insn (history, NULL) | |
2095 | : nops_for_insn_or_target (history, ip)); | |
2096 | if (nops > 0) | |
252b5132 RH |
2097 | { |
2098 | fragS *old_frag; | |
2099 | unsigned long old_frag_offset; | |
2100 | int i; | |
2101 | struct insn_label_list *l; | |
2102 | ||
2103 | old_frag = frag_now; | |
2104 | old_frag_offset = frag_now_fix (); | |
2105 | ||
2106 | for (i = 0; i < nops; i++) | |
2107 | emit_nop (); | |
2108 | ||
2109 | if (listing) | |
2110 | { | |
2111 | listing_prev_line (); | |
2112 | /* We may be at the start of a variant frag. In case we | |
2113 | are, make sure there is enough space for the frag | |
2114 | after the frags created by listing_prev_line. The | |
2115 | argument to frag_grow here must be at least as large | |
2116 | as the argument to all other calls to frag_grow in | |
2117 | this file. We don't have to worry about being in the | |
2118 | middle of a variant frag, because the variants insert | |
2119 | all needed nop instructions themselves. */ | |
2120 | frag_grow (40); | |
2121 | } | |
2122 | ||
2123 | for (l = insn_labels; l != NULL; l = l->next) | |
2124 | { | |
98aa84af AM |
2125 | valueT val; |
2126 | ||
252b5132 | 2127 | assert (S_GET_SEGMENT (l->label) == now_seg); |
49309057 | 2128 | symbol_set_frag (l->label, frag_now); |
98aa84af | 2129 | val = (valueT) frag_now_fix (); |
252b5132 RH |
2130 | /* mips16 text labels are stored as odd. */ |
2131 | if (mips_opts.mips16) | |
f9419b05 | 2132 | ++val; |
98aa84af | 2133 | S_SET_VALUE (l->label, val); |
252b5132 RH |
2134 | } |
2135 | ||
2136 | #ifndef NO_ECOFF_DEBUGGING | |
2137 | if (ECOFF_DEBUGGING) | |
2138 | ecoff_fix_loc (old_frag, old_frag_offset); | |
2139 | #endif | |
2140 | } | |
71400594 RS |
2141 | } |
2142 | else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) | |
2143 | { | |
2144 | /* Work out how many nops in prev_nop_frag are needed by IP. */ | |
2145 | int nops = nops_for_insn_or_target (history, ip); | |
2146 | assert (nops <= prev_nop_frag_holds); | |
252b5132 | 2147 | |
71400594 RS |
2148 | /* Enforce NOPS as a minimum. */ |
2149 | if (nops > prev_nop_frag_required) | |
2150 | prev_nop_frag_required = nops; | |
252b5132 | 2151 | |
71400594 RS |
2152 | if (prev_nop_frag_holds == prev_nop_frag_required) |
2153 | { | |
2154 | /* Settle for the current number of nops. Update the history | |
2155 | accordingly (for the benefit of any future .set reorder code). */ | |
2156 | prev_nop_frag = NULL; | |
2157 | insert_into_history (prev_nop_frag_since, | |
2158 | prev_nop_frag_holds, NOP_INSN); | |
2159 | } | |
2160 | else | |
2161 | { | |
2162 | /* Allow this instruction to replace one of the nops that was | |
2163 | tentatively added to prev_nop_frag. */ | |
2164 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
2165 | prev_nop_frag_holds--; | |
2166 | prev_nop_frag_since++; | |
252b5132 RH |
2167 | } |
2168 | } | |
2169 | ||
58e2ea4d MR |
2170 | #ifdef OBJ_ELF |
2171 | /* The value passed to dwarf2_emit_insn is the distance between | |
2172 | the beginning of the current instruction and the address that | |
2173 | should be recorded in the debug tables. For MIPS16 debug info | |
2174 | we want to use ISA-encoded addresses, so we pass -1 for an | |
2175 | address higher by one than the current. */ | |
2176 | dwarf2_emit_insn (mips_opts.mips16 ? -1 : 0); | |
2177 | #endif | |
2178 | ||
895921c9 | 2179 | /* Record the frag type before frag_var. */ |
47e39b9d RS |
2180 | if (history[0].frag) |
2181 | prev_insn_frag_type = history[0].frag->fr_type; | |
895921c9 | 2182 | |
4d7206a2 | 2183 | if (address_expr |
0b25d3e6 | 2184 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
4a6a3df4 AO |
2185 | && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY |
2186 | || pinfo & INSN_COND_BRANCH_LIKELY) | |
2187 | && mips_relax_branch | |
2188 | /* Don't try branch relaxation within .set nomacro, or within | |
2189 | .set noat if we use $at for PIC computations. If it turns | |
2190 | out that the branch was out-of-range, we'll get an error. */ | |
2191 | && !mips_opts.warn_about_macros | |
2192 | && !(mips_opts.noat && mips_pic != NO_PIC) | |
2193 | && !mips_opts.mips16) | |
2194 | { | |
895921c9 | 2195 | relaxed_branch = TRUE; |
1e915849 RS |
2196 | add_relaxed_insn (ip, (relaxed_branch_length |
2197 | (NULL, NULL, | |
2198 | (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1 | |
2199 | : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 | |
2200 | : 0)), 4, | |
2201 | RELAX_BRANCH_ENCODE | |
2202 | (pinfo & INSN_UNCOND_BRANCH_DELAY, | |
2203 | pinfo & INSN_COND_BRANCH_LIKELY, | |
2204 | pinfo & INSN_WRITE_GPR_31, | |
2205 | 0), | |
2206 | address_expr->X_add_symbol, | |
2207 | address_expr->X_add_number); | |
4a6a3df4 AO |
2208 | *reloc_type = BFD_RELOC_UNUSED; |
2209 | } | |
2210 | else if (*reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
2211 | { |
2212 | /* We need to set up a variant frag. */ | |
2213 | assert (mips_opts.mips16 && address_expr != NULL); | |
1e915849 RS |
2214 | add_relaxed_insn (ip, 4, 0, |
2215 | RELAX_MIPS16_ENCODE | |
2216 | (*reloc_type - BFD_RELOC_UNUSED, | |
2217 | mips16_small, mips16_ext, | |
2218 | prev_pinfo & INSN_UNCOND_BRANCH_DELAY, | |
2219 | history[0].mips16_absolute_jump_p), | |
2220 | make_expr_symbol (address_expr), 0); | |
252b5132 | 2221 | } |
252b5132 RH |
2222 | else if (mips_opts.mips16 |
2223 | && ! ip->use_extend | |
f6688943 | 2224 | && *reloc_type != BFD_RELOC_MIPS16_JMP) |
252b5132 RH |
2225 | { |
2226 | /* Make sure there is enough room to swap this instruction with | |
2227 | a following jump instruction. */ | |
2228 | frag_grow (6); | |
1e915849 | 2229 | add_fixed_insn (ip); |
252b5132 RH |
2230 | } |
2231 | else | |
2232 | { | |
2233 | if (mips_opts.mips16 | |
2234 | && mips_opts.noreorder | |
2235 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
2236 | as_warn (_("extended instruction in delay slot")); | |
2237 | ||
4d7206a2 RS |
2238 | if (mips_relax.sequence) |
2239 | { | |
2240 | /* If we've reached the end of this frag, turn it into a variant | |
2241 | frag and record the information for the instructions we've | |
2242 | written so far. */ | |
2243 | if (frag_room () < 4) | |
2244 | relax_close_frag (); | |
2245 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
2246 | } | |
2247 | ||
584892a6 RS |
2248 | if (mips_relax.sequence != 2) |
2249 | mips_macro_warning.sizes[0] += 4; | |
2250 | if (mips_relax.sequence != 1) | |
2251 | mips_macro_warning.sizes[1] += 4; | |
2252 | ||
1e915849 RS |
2253 | if (mips_opts.mips16) |
2254 | { | |
2255 | ip->fixed_p = 1; | |
2256 | ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); | |
2257 | } | |
2258 | add_fixed_insn (ip); | |
252b5132 RH |
2259 | } |
2260 | ||
01a3f561 | 2261 | if (address_expr != NULL && *reloc_type <= BFD_RELOC_UNUSED) |
252b5132 RH |
2262 | { |
2263 | if (address_expr->X_op == O_constant) | |
2264 | { | |
f17c130b | 2265 | unsigned int tmp; |
f6688943 TS |
2266 | |
2267 | switch (*reloc_type) | |
252b5132 RH |
2268 | { |
2269 | case BFD_RELOC_32: | |
2270 | ip->insn_opcode |= address_expr->X_add_number; | |
2271 | break; | |
2272 | ||
f6688943 | 2273 | case BFD_RELOC_MIPS_HIGHEST: |
f17c130b AM |
2274 | tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48; |
2275 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2276 | break; |
2277 | ||
2278 | case BFD_RELOC_MIPS_HIGHER: | |
f17c130b AM |
2279 | tmp = (address_expr->X_add_number + 0x80008000ull) >> 32; |
2280 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2281 | break; |
2282 | ||
2283 | case BFD_RELOC_HI16_S: | |
f17c130b AM |
2284 | tmp = (address_expr->X_add_number + 0x8000) >> 16; |
2285 | ip->insn_opcode |= tmp & 0xffff; | |
f6688943 TS |
2286 | break; |
2287 | ||
2288 | case BFD_RELOC_HI16: | |
2289 | ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; | |
2290 | break; | |
2291 | ||
01a3f561 | 2292 | case BFD_RELOC_UNUSED: |
252b5132 | 2293 | case BFD_RELOC_LO16: |
ed6fb7bd | 2294 | case BFD_RELOC_MIPS_GOT_DISP: |
252b5132 RH |
2295 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
2296 | break; | |
2297 | ||
2298 | case BFD_RELOC_MIPS_JMP: | |
2299 | if ((address_expr->X_add_number & 3) != 0) | |
2300 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2301 | (unsigned long) address_expr->X_add_number); | |
f3c0ec86 | 2302 | if (address_expr->X_add_number & ~0xfffffff) |
7496292d TS |
2303 | as_bad (_("jump address range overflow (0x%lx)"), |
2304 | (unsigned long) address_expr->X_add_number); | |
252b5132 RH |
2305 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; |
2306 | break; | |
2307 | ||
2308 | case BFD_RELOC_MIPS16_JMP: | |
2309 | if ((address_expr->X_add_number & 3) != 0) | |
2310 | as_bad (_("jump to misaligned address (0x%lx)"), | |
2311 | (unsigned long) address_expr->X_add_number); | |
f3c0ec86 | 2312 | if (address_expr->X_add_number & ~0xfffffff) |
7496292d TS |
2313 | as_bad (_("jump address range overflow (0x%lx)"), |
2314 | (unsigned long) address_expr->X_add_number); | |
252b5132 RH |
2315 | ip->insn_opcode |= |
2316 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
2317 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
2318 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
2319 | break; | |
2320 | ||
252b5132 RH |
2321 | case BFD_RELOC_16_PCREL_S2: |
2322 | goto need_reloc; | |
2323 | ||
2324 | default: | |
2325 | internalError (); | |
2326 | } | |
2327 | } | |
01a3f561 | 2328 | else if (*reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 2329 | need_reloc: |
4d7206a2 RS |
2330 | { |
2331 | reloc_howto_type *howto; | |
2332 | int i; | |
34ce925e | 2333 | |
4d7206a2 RS |
2334 | /* In a compound relocation, it is the final (outermost) |
2335 | operator that determines the relocated field. */ | |
2336 | for (i = 1; i < 3; i++) | |
2337 | if (reloc_type[i] == BFD_RELOC_UNUSED) | |
2338 | break; | |
34ce925e | 2339 | |
4d7206a2 | 2340 | howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]); |
1e915849 RS |
2341 | ip->fixp[0] = fix_new_exp (ip->frag, ip->where, |
2342 | bfd_get_reloc_size (howto), | |
2343 | address_expr, | |
2344 | reloc_type[0] == BFD_RELOC_16_PCREL_S2, | |
2345 | reloc_type[0]); | |
4d7206a2 RS |
2346 | |
2347 | /* These relocations can have an addend that won't fit in | |
2348 | 4 octets for 64bit assembly. */ | |
2349 | if (HAVE_64BIT_GPRS | |
2350 | && ! howto->partial_inplace | |
2351 | && (reloc_type[0] == BFD_RELOC_16 | |
2352 | || reloc_type[0] == BFD_RELOC_32 | |
2353 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
2354 | || reloc_type[0] == BFD_RELOC_HI16_S | |
2355 | || reloc_type[0] == BFD_RELOC_LO16 | |
2356 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
2357 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
2358 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
2359 | || reloc_type[0] == BFD_RELOC_64 | |
2360 | || reloc_type[0] == BFD_RELOC_CTOR | |
2361 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
2362 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
2363 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
2364 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
2365 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
d6f16593 MR |
2366 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT |
2367 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
2368 | || reloc_type[0] == BFD_RELOC_MIPS16_HI16_S | |
2369 | || reloc_type[0] == BFD_RELOC_MIPS16_LO16)) | |
1e915849 | 2370 | ip->fixp[0]->fx_no_overflow = 1; |
4d7206a2 RS |
2371 | |
2372 | if (mips_relax.sequence) | |
2373 | { | |
2374 | if (mips_relax.first_fixup == 0) | |
1e915849 | 2375 | mips_relax.first_fixup = ip->fixp[0]; |
4d7206a2 RS |
2376 | } |
2377 | else if (reloc_needs_lo_p (*reloc_type)) | |
2378 | { | |
2379 | struct mips_hi_fixup *hi_fixup; | |
252b5132 | 2380 | |
4d7206a2 RS |
2381 | /* Reuse the last entry if it already has a matching %lo. */ |
2382 | hi_fixup = mips_hi_fixup_list; | |
2383 | if (hi_fixup == 0 | |
2384 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
2385 | { | |
2386 | hi_fixup = ((struct mips_hi_fixup *) | |
2387 | xmalloc (sizeof (struct mips_hi_fixup))); | |
2388 | hi_fixup->next = mips_hi_fixup_list; | |
2389 | mips_hi_fixup_list = hi_fixup; | |
252b5132 | 2390 | } |
1e915849 | 2391 | hi_fixup->fixp = ip->fixp[0]; |
4d7206a2 RS |
2392 | hi_fixup->seg = now_seg; |
2393 | } | |
f6688943 | 2394 | |
4d7206a2 RS |
2395 | /* Add fixups for the second and third relocations, if given. |
2396 | Note that the ABI allows the second relocation to be | |
2397 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
2398 | moment we only use RSS_UNDEF, but we could add support | |
2399 | for the others if it ever becomes necessary. */ | |
2400 | for (i = 1; i < 3; i++) | |
2401 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
2402 | { | |
1e915849 RS |
2403 | ip->fixp[i] = fix_new (ip->frag, ip->where, |
2404 | ip->fixp[0]->fx_size, NULL, 0, | |
2405 | FALSE, reloc_type[i]); | |
b1dca8ee RS |
2406 | |
2407 | /* Use fx_tcbit to mark compound relocs. */ | |
1e915849 RS |
2408 | ip->fixp[0]->fx_tcbit = 1; |
2409 | ip->fixp[i]->fx_tcbit = 1; | |
4d7206a2 | 2410 | } |
252b5132 RH |
2411 | } |
2412 | } | |
1e915849 | 2413 | install_insn (ip); |
252b5132 RH |
2414 | |
2415 | /* Update the register mask information. */ | |
2416 | if (! mips_opts.mips16) | |
2417 | { | |
2418 | if (pinfo & INSN_WRITE_GPR_D) | |
bf12938e | 2419 | mips_gprmask |= 1 << EXTRACT_OPERAND (RD, *ip); |
252b5132 | 2420 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) |
bf12938e | 2421 | mips_gprmask |= 1 << EXTRACT_OPERAND (RT, *ip); |
252b5132 | 2422 | if (pinfo & INSN_READ_GPR_S) |
bf12938e | 2423 | mips_gprmask |= 1 << EXTRACT_OPERAND (RS, *ip); |
252b5132 | 2424 | if (pinfo & INSN_WRITE_GPR_31) |
f9419b05 | 2425 | mips_gprmask |= 1 << RA; |
252b5132 | 2426 | if (pinfo & INSN_WRITE_FPR_D) |
bf12938e | 2427 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FD, *ip); |
252b5132 | 2428 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) |
bf12938e | 2429 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FS, *ip); |
252b5132 | 2430 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) |
bf12938e | 2431 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FT, *ip); |
252b5132 | 2432 | if ((pinfo & INSN_READ_FPR_R) != 0) |
bf12938e | 2433 | mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FR, *ip); |
252b5132 RH |
2434 | if (pinfo & INSN_COP) |
2435 | { | |
bdaaa2e1 KH |
2436 | /* We don't keep enough information to sort these cases out. |
2437 | The itbl support does keep this information however, although | |
2438 | we currently don't support itbl fprmats as part of the cop | |
2439 | instruction. May want to add this support in the future. */ | |
252b5132 RH |
2440 | } |
2441 | /* Never set the bit for $0, which is always zero. */ | |
beae10d5 | 2442 | mips_gprmask &= ~1 << 0; |
252b5132 RH |
2443 | } |
2444 | else | |
2445 | { | |
2446 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) | |
bf12938e | 2447 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RX, *ip); |
252b5132 | 2448 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) |
bf12938e | 2449 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RY, *ip); |
252b5132 | 2450 | if (pinfo & MIPS16_INSN_WRITE_Z) |
bf12938e | 2451 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RZ, *ip); |
252b5132 RH |
2452 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) |
2453 | mips_gprmask |= 1 << TREG; | |
2454 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
2455 | mips_gprmask |= 1 << SP; | |
2456 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
2457 | mips_gprmask |= 1 << RA; | |
2458 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2459 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
2460 | if (pinfo & MIPS16_INSN_READ_Z) | |
bf12938e | 2461 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip); |
252b5132 | 2462 | if (pinfo & MIPS16_INSN_READ_GPR_X) |
bf12938e | 2463 | mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip); |
252b5132 RH |
2464 | } |
2465 | ||
4d7206a2 | 2466 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
252b5132 RH |
2467 | { |
2468 | /* Filling the branch delay slot is more complex. We try to | |
2469 | switch the branch with the previous instruction, which we can | |
2470 | do if the previous instruction does not set up a condition | |
2471 | that the branch tests and if the branch is not itself the | |
2472 | target of any branch. */ | |
2473 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2474 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
2475 | { | |
2476 | if (mips_optimize < 2 | |
2477 | /* If we have seen .set volatile or .set nomove, don't | |
2478 | optimize. */ | |
2479 | || mips_opts.nomove != 0 | |
a38419a5 RS |
2480 | /* We can't swap if the previous instruction's position |
2481 | is fixed. */ | |
2482 | || history[0].fixed_p | |
252b5132 RH |
2483 | /* If the previous previous insn was in a .set |
2484 | noreorder, we can't swap. Actually, the MIPS | |
2485 | assembler will swap in this situation. However, gcc | |
2486 | configured -with-gnu-as will generate code like | |
2487 | .set noreorder | |
2488 | lw $4,XXX | |
2489 | .set reorder | |
2490 | INSN | |
2491 | bne $4,$0,foo | |
2492 | in which we can not swap the bne and INSN. If gcc is | |
2493 | not configured -with-gnu-as, it does not output the | |
a38419a5 | 2494 | .set pseudo-ops. */ |
47e39b9d | 2495 | || history[1].noreorder_p |
252b5132 RH |
2496 | /* If the branch is itself the target of a branch, we |
2497 | can not swap. We cheat on this; all we check for is | |
2498 | whether there is a label on this instruction. If | |
2499 | there are any branches to anything other than a | |
2500 | label, users must use .set noreorder. */ | |
2501 | || insn_labels != NULL | |
895921c9 MR |
2502 | /* If the previous instruction is in a variant frag |
2503 | other than this branch's one, we cannot do the swap. | |
2504 | This does not apply to the mips16, which uses variant | |
2505 | frags for different purposes. */ | |
252b5132 | 2506 | || (! mips_opts.mips16 |
895921c9 | 2507 | && prev_insn_frag_type == rs_machine_dependent) |
252b5132 RH |
2508 | /* If the branch reads the condition codes, we don't |
2509 | even try to swap, because in the sequence | |
2510 | ctc1 $X,$31 | |
2511 | INSN | |
2512 | INSN | |
2513 | bc1t LABEL | |
2514 | we can not swap, and I don't feel like handling that | |
2515 | case. */ | |
2516 | || (! mips_opts.mips16 | |
81912461 ILT |
2517 | && (pinfo & INSN_READ_COND_CODE) |
2518 | && ! cop_interlocks) | |
71400594 RS |
2519 | /* Check for conflicts between the branch and the instructions |
2520 | before the candidate delay slot. */ | |
2521 | || nops_for_insn (history + 1, ip) > 0 | |
2522 | /* Check for conflicts between the swapped sequence and the | |
2523 | target of the branch. */ | |
2524 | || nops_for_sequence (2, history + 1, ip, history) > 0 | |
252b5132 RH |
2525 | /* We do not swap with a trap instruction, since it |
2526 | complicates trap handlers to have the trap | |
2527 | instruction be in a delay slot. */ | |
2528 | || (prev_pinfo & INSN_TRAP) | |
2529 | /* If the branch reads a register that the previous | |
2530 | instruction sets, we can not swap. */ | |
2531 | || (! mips_opts.mips16 | |
2532 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
bf12938e | 2533 | && insn_uses_reg (ip, EXTRACT_OPERAND (RT, history[0]), |
252b5132 RH |
2534 | MIPS_GR_REG)) |
2535 | || (! mips_opts.mips16 | |
2536 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
bf12938e | 2537 | && insn_uses_reg (ip, EXTRACT_OPERAND (RD, history[0]), |
252b5132 RH |
2538 | MIPS_GR_REG)) |
2539 | || (mips_opts.mips16 | |
2540 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
bf12938e RS |
2541 | && (insn_uses_reg |
2542 | (ip, MIPS16_EXTRACT_OPERAND (RX, history[0]), | |
2543 | MIPS16_REG))) | |
252b5132 | 2544 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) |
bf12938e RS |
2545 | && (insn_uses_reg |
2546 | (ip, MIPS16_EXTRACT_OPERAND (RY, history[0]), | |
2547 | MIPS16_REG))) | |
252b5132 | 2548 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) |
bf12938e RS |
2549 | && (insn_uses_reg |
2550 | (ip, MIPS16_EXTRACT_OPERAND (RZ, history[0]), | |
2551 | MIPS16_REG))) | |
252b5132 RH |
2552 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) |
2553 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
2554 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2555 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
2556 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2557 | && insn_uses_reg (ip, | |
47e39b9d RS |
2558 | MIPS16OP_EXTRACT_REG32R |
2559 | (history[0].insn_opcode), | |
252b5132 RH |
2560 | MIPS_GR_REG)))) |
2561 | /* If the branch writes a register that the previous | |
2562 | instruction sets, we can not swap (we know that | |
2563 | branches write only to RD or to $31). */ | |
2564 | || (! mips_opts.mips16 | |
2565 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2566 | && (((pinfo & INSN_WRITE_GPR_D) | |
bf12938e RS |
2567 | && (EXTRACT_OPERAND (RT, history[0]) |
2568 | == EXTRACT_OPERAND (RD, *ip))) | |
252b5132 | 2569 | || ((pinfo & INSN_WRITE_GPR_31) |
bf12938e | 2570 | && EXTRACT_OPERAND (RT, history[0]) == RA))) |
252b5132 RH |
2571 | || (! mips_opts.mips16 |
2572 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2573 | && (((pinfo & INSN_WRITE_GPR_D) | |
bf12938e RS |
2574 | && (EXTRACT_OPERAND (RD, history[0]) |
2575 | == EXTRACT_OPERAND (RD, *ip))) | |
252b5132 | 2576 | || ((pinfo & INSN_WRITE_GPR_31) |
bf12938e | 2577 | && EXTRACT_OPERAND (RD, history[0]) == RA))) |
252b5132 RH |
2578 | || (mips_opts.mips16 |
2579 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2580 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2581 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
47e39b9d | 2582 | && (MIPS16OP_EXTRACT_REG32R (history[0].insn_opcode) |
252b5132 RH |
2583 | == RA)))) |
2584 | /* If the branch writes a register that the previous | |
2585 | instruction reads, we can not swap (we know that | |
2586 | branches only write to RD or to $31). */ | |
2587 | || (! mips_opts.mips16 | |
2588 | && (pinfo & INSN_WRITE_GPR_D) | |
47e39b9d | 2589 | && insn_uses_reg (&history[0], |
bf12938e | 2590 | EXTRACT_OPERAND (RD, *ip), |
252b5132 RH |
2591 | MIPS_GR_REG)) |
2592 | || (! mips_opts.mips16 | |
2593 | && (pinfo & INSN_WRITE_GPR_31) | |
47e39b9d | 2594 | && insn_uses_reg (&history[0], RA, MIPS_GR_REG)) |
252b5132 RH |
2595 | || (mips_opts.mips16 |
2596 | && (pinfo & MIPS16_INSN_WRITE_31) | |
47e39b9d | 2597 | && insn_uses_reg (&history[0], RA, MIPS_GR_REG)) |
252b5132 RH |
2598 | /* If one instruction sets a condition code and the |
2599 | other one uses a condition code, we can not swap. */ | |
2600 | || ((pinfo & INSN_READ_COND_CODE) | |
2601 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
2602 | || ((pinfo & INSN_WRITE_COND_CODE) | |
2603 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
2604 | /* If the previous instruction uses the PC, we can not | |
2605 | swap. */ | |
2606 | || (mips_opts.mips16 | |
2607 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
252b5132 RH |
2608 | /* If the previous instruction had a fixup in mips16 |
2609 | mode, we can not swap. This normally means that the | |
2610 | previous instruction was a 4 byte branch anyhow. */ | |
47e39b9d | 2611 | || (mips_opts.mips16 && history[0].fixp[0]) |
bdaaa2e1 KH |
2612 | /* If the previous instruction is a sync, sync.l, or |
2613 | sync.p, we can not swap. */ | |
f173e82e | 2614 | || (prev_pinfo & INSN_SYNC)) |
252b5132 RH |
2615 | { |
2616 | /* We could do even better for unconditional branches to | |
2617 | portions of this object file; we could pick up the | |
2618 | instruction at the destination, put it in the delay | |
2619 | slot, and bump the destination address. */ | |
1e915849 | 2620 | insert_into_history (0, 1, ip); |
252b5132 | 2621 | emit_nop (); |
dd22970f ILT |
2622 | if (mips_relax.sequence) |
2623 | mips_relax.sizes[mips_relax.sequence - 1] += 4; | |
252b5132 RH |
2624 | } |
2625 | else | |
2626 | { | |
2627 | /* It looks like we can actually do the swap. */ | |
1e915849 RS |
2628 | struct mips_cl_insn delay = history[0]; |
2629 | if (mips_opts.mips16) | |
252b5132 | 2630 | { |
1e915849 RS |
2631 | know (delay.frag == ip->frag); |
2632 | move_insn (ip, delay.frag, delay.where); | |
2633 | move_insn (&delay, ip->frag, ip->where + insn_length (ip)); | |
2634 | } | |
2635 | else if (relaxed_branch) | |
2636 | { | |
2637 | /* Add the delay slot instruction to the end of the | |
2638 | current frag and shrink the fixed part of the | |
2639 | original frag. If the branch occupies the tail of | |
2640 | the latter, move it backwards to cover the gap. */ | |
2641 | delay.frag->fr_fix -= 4; | |
2642 | if (delay.frag == ip->frag) | |
2643 | move_insn (ip, ip->frag, ip->where - 4); | |
2644 | add_fixed_insn (&delay); | |
252b5132 RH |
2645 | } |
2646 | else | |
2647 | { | |
1e915849 RS |
2648 | move_insn (&delay, ip->frag, ip->where); |
2649 | move_insn (ip, history[0].frag, history[0].where); | |
252b5132 | 2650 | } |
1e915849 RS |
2651 | history[0] = *ip; |
2652 | delay.fixed_p = 1; | |
2653 | insert_into_history (0, 1, &delay); | |
252b5132 | 2654 | } |
252b5132 RH |
2655 | |
2656 | /* If that was an unconditional branch, forget the previous | |
2657 | insn information. */ | |
2658 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
1e915849 | 2659 | mips_no_prev_insn (FALSE); |
252b5132 RH |
2660 | } |
2661 | else if (pinfo & INSN_COND_BRANCH_LIKELY) | |
2662 | { | |
2663 | /* We don't yet optimize a branch likely. What we should do | |
2664 | is look at the target, copy the instruction found there | |
2665 | into the delay slot, and increment the branch to jump to | |
2666 | the next instruction. */ | |
1e915849 | 2667 | insert_into_history (0, 1, ip); |
252b5132 | 2668 | emit_nop (); |
252b5132 RH |
2669 | } |
2670 | else | |
1e915849 | 2671 | insert_into_history (0, 1, ip); |
252b5132 | 2672 | } |
1e915849 RS |
2673 | else |
2674 | insert_into_history (0, 1, ip); | |
252b5132 RH |
2675 | |
2676 | /* We just output an insn, so the next one doesn't have a label. */ | |
2677 | mips_clear_insn_labels (); | |
252b5132 RH |
2678 | } |
2679 | ||
2680 | /* This function forgets that there was any previous instruction or | |
2681 | label. If PRESERVE is non-zero, it remembers enough information to | |
bdaaa2e1 | 2682 | know whether nops are needed before a noreorder section. */ |
252b5132 RH |
2683 | |
2684 | static void | |
17a2f251 | 2685 | mips_no_prev_insn (int preserve) |
252b5132 | 2686 | { |
1e915849 RS |
2687 | size_t i; |
2688 | ||
252b5132 RH |
2689 | if (! preserve) |
2690 | { | |
252b5132 RH |
2691 | prev_nop_frag = NULL; |
2692 | prev_nop_frag_holds = 0; | |
2693 | prev_nop_frag_required = 0; | |
2694 | prev_nop_frag_since = 0; | |
1e915849 RS |
2695 | for (i = 0; i < ARRAY_SIZE (history); i++) |
2696 | history[i] = (mips_opts.mips16 ? mips16_nop_insn : nop_insn); | |
252b5132 | 2697 | } |
1e915849 RS |
2698 | else |
2699 | for (i = 0; i < ARRAY_SIZE (history); i++) | |
2700 | { | |
2701 | history[i].fixed_p = 1; | |
2702 | history[i].noreorder_p = 0; | |
2703 | history[i].mips16_absolute_jump_p = 0; | |
2704 | } | |
252b5132 RH |
2705 | mips_clear_insn_labels (); |
2706 | } | |
2707 | ||
2708 | /* This function must be called whenever we turn on noreorder or emit | |
2709 | something other than instructions. It inserts any NOPS which might | |
2710 | be needed by the previous instruction, and clears the information | |
2711 | kept for the previous instructions. The INSNS parameter is true if | |
bdaaa2e1 | 2712 | instructions are to follow. */ |
252b5132 RH |
2713 | |
2714 | static void | |
17a2f251 | 2715 | mips_emit_delays (bfd_boolean insns) |
252b5132 RH |
2716 | { |
2717 | if (! mips_opts.noreorder) | |
2718 | { | |
71400594 | 2719 | int nops = nops_for_insn (history, NULL); |
252b5132 RH |
2720 | if (nops > 0) |
2721 | { | |
2722 | struct insn_label_list *l; | |
2723 | ||
71400594 | 2724 | if (insns && mips_optimize != 0) |
252b5132 RH |
2725 | { |
2726 | /* Record the frag which holds the nop instructions, so | |
2727 | that we can remove them if we don't need them. */ | |
2728 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); | |
2729 | prev_nop_frag = frag_now; | |
2730 | prev_nop_frag_holds = nops; | |
2731 | prev_nop_frag_required = 0; | |
2732 | prev_nop_frag_since = 0; | |
2733 | } | |
2734 | ||
2735 | for (; nops > 0; --nops) | |
1e915849 | 2736 | add_fixed_insn (NOP_INSN); |
252b5132 RH |
2737 | |
2738 | if (insns) | |
2739 | { | |
2740 | /* Move on to a new frag, so that it is safe to simply | |
bdaaa2e1 | 2741 | decrease the size of prev_nop_frag. */ |
252b5132 RH |
2742 | frag_wane (frag_now); |
2743 | frag_new (0); | |
2744 | } | |
2745 | ||
2746 | for (l = insn_labels; l != NULL; l = l->next) | |
2747 | { | |
98aa84af AM |
2748 | valueT val; |
2749 | ||
252b5132 | 2750 | assert (S_GET_SEGMENT (l->label) == now_seg); |
49309057 | 2751 | symbol_set_frag (l->label, frag_now); |
98aa84af | 2752 | val = (valueT) frag_now_fix (); |
252b5132 RH |
2753 | /* mips16 text labels are stored as odd. */ |
2754 | if (mips_opts.mips16) | |
f9419b05 | 2755 | ++val; |
98aa84af | 2756 | S_SET_VALUE (l->label, val); |
252b5132 RH |
2757 | } |
2758 | } | |
2759 | } | |
2760 | ||
2761 | /* Mark instruction labels in mips16 mode. */ | |
f9419b05 | 2762 | if (insns) |
252b5132 RH |
2763 | mips16_mark_labels (); |
2764 | ||
2765 | mips_no_prev_insn (insns); | |
2766 | } | |
2767 | ||
584892a6 RS |
2768 | /* Set up global variables for the start of a new macro. */ |
2769 | ||
2770 | static void | |
2771 | macro_start (void) | |
2772 | { | |
2773 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
2774 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder | |
47e39b9d | 2775 | && (history[0].insn_mo->pinfo |
584892a6 RS |
2776 | & (INSN_UNCOND_BRANCH_DELAY |
2777 | | INSN_COND_BRANCH_DELAY | |
2778 | | INSN_COND_BRANCH_LIKELY)) != 0); | |
2779 | } | |
2780 | ||
2781 | /* Given that a macro is longer than 4 bytes, return the appropriate warning | |
2782 | for it. Return null if no warning is needed. SUBTYPE is a bitmask of | |
2783 | RELAX_DELAY_SLOT and RELAX_NOMACRO. */ | |
2784 | ||
2785 | static const char * | |
2786 | macro_warning (relax_substateT subtype) | |
2787 | { | |
2788 | if (subtype & RELAX_DELAY_SLOT) | |
2789 | return _("Macro instruction expanded into multiple instructions" | |
2790 | " in a branch delay slot"); | |
2791 | else if (subtype & RELAX_NOMACRO) | |
2792 | return _("Macro instruction expanded into multiple instructions"); | |
2793 | else | |
2794 | return 0; | |
2795 | } | |
2796 | ||
2797 | /* Finish up a macro. Emit warnings as appropriate. */ | |
2798 | ||
2799 | static void | |
2800 | macro_end (void) | |
2801 | { | |
2802 | if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4) | |
2803 | { | |
2804 | relax_substateT subtype; | |
2805 | ||
2806 | /* Set up the relaxation warning flags. */ | |
2807 | subtype = 0; | |
2808 | if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0]) | |
2809 | subtype |= RELAX_SECOND_LONGER; | |
2810 | if (mips_opts.warn_about_macros) | |
2811 | subtype |= RELAX_NOMACRO; | |
2812 | if (mips_macro_warning.delay_slot_p) | |
2813 | subtype |= RELAX_DELAY_SLOT; | |
2814 | ||
2815 | if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4) | |
2816 | { | |
2817 | /* Either the macro has a single implementation or both | |
2818 | implementations are longer than 4 bytes. Emit the | |
2819 | warning now. */ | |
2820 | const char *msg = macro_warning (subtype); | |
2821 | if (msg != 0) | |
2822 | as_warn (msg); | |
2823 | } | |
2824 | else | |
2825 | { | |
2826 | /* One implementation might need a warning but the other | |
2827 | definitely doesn't. */ | |
2828 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
2829 | } | |
2830 | } | |
2831 | } | |
2832 | ||
6e1304d8 RS |
2833 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
2834 | The first argument in *ARGS will be either the code for a single | |
2835 | relocation or -1 followed by the three codes that make up a | |
2836 | composite relocation. */ | |
2837 | ||
2838 | static void | |
2839 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
2840 | { | |
2841 | int i, next; | |
2842 | ||
2843 | next = va_arg (*args, int); | |
2844 | if (next >= 0) | |
2845 | r[0] = (bfd_reloc_code_real_type) next; | |
2846 | else | |
2847 | for (i = 0; i < 3; i++) | |
2848 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
2849 | } | |
2850 | ||
252b5132 RH |
2851 | /* Build an instruction created by a macro expansion. This is passed |
2852 | a pointer to the count of instructions created so far, an | |
2853 | expression, the name of the instruction to build, an operand format | |
2854 | string, and corresponding arguments. */ | |
2855 | ||
252b5132 | 2856 | static void |
67c0d1eb | 2857 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 | 2858 | { |
1e915849 | 2859 | const struct mips_opcode *mo; |
252b5132 | 2860 | struct mips_cl_insn insn; |
f6688943 | 2861 | bfd_reloc_code_real_type r[3]; |
252b5132 | 2862 | va_list args; |
252b5132 | 2863 | |
252b5132 | 2864 | va_start (args, fmt); |
252b5132 | 2865 | |
252b5132 RH |
2866 | if (mips_opts.mips16) |
2867 | { | |
67c0d1eb | 2868 | mips16_macro_build (ep, name, fmt, args); |
252b5132 RH |
2869 | va_end (args); |
2870 | return; | |
2871 | } | |
2872 | ||
f6688943 TS |
2873 | r[0] = BFD_RELOC_UNUSED; |
2874 | r[1] = BFD_RELOC_UNUSED; | |
2875 | r[2] = BFD_RELOC_UNUSED; | |
1e915849 RS |
2876 | mo = (struct mips_opcode *) hash_find (op_hash, name); |
2877 | assert (mo); | |
2878 | assert (strcmp (name, mo->name) == 0); | |
2879 | ||
2880 | /* Search until we get a match for NAME. It is assumed here that | |
2881 | macros will never generate MDMX or MIPS-3D instructions. */ | |
2882 | while (strcmp (fmt, mo->args) != 0 | |
2883 | || mo->pinfo == INSN_MACRO | |
2884 | || !OPCODE_IS_MEMBER (mo, | |
2885 | (mips_opts.isa | |
2886 | | (file_ase_mips16 ? INSN_MIPS16 : 0)), | |
fef14a42 | 2887 | mips_opts.arch) |
1e915849 RS |
2888 | || (mips_opts.arch == CPU_R4650 && (mo->pinfo & FP_D) != 0)) |
2889 | { | |
2890 | ++mo; | |
2891 | assert (mo->name); | |
2892 | assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
2893 | } |
2894 | ||
1e915849 | 2895 | create_insn (&insn, mo); |
252b5132 RH |
2896 | for (;;) |
2897 | { | |
2898 | switch (*fmt++) | |
2899 | { | |
2900 | case '\0': | |
2901 | break; | |
2902 | ||
2903 | case ',': | |
2904 | case '(': | |
2905 | case ')': | |
2906 | continue; | |
2907 | ||
5f74bc13 CD |
2908 | case '+': |
2909 | switch (*fmt++) | |
2910 | { | |
2911 | case 'A': | |
2912 | case 'E': | |
bf12938e | 2913 | INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); |
5f74bc13 CD |
2914 | continue; |
2915 | ||
2916 | case 'B': | |
2917 | case 'F': | |
2918 | /* Note that in the macro case, these arguments are already | |
2919 | in MSB form. (When handling the instruction in the | |
2920 | non-macro case, these arguments are sizes from which | |
2921 | MSB values must be calculated.) */ | |
bf12938e | 2922 | INSERT_OPERAND (INSMSB, insn, va_arg (args, int)); |
5f74bc13 CD |
2923 | continue; |
2924 | ||
2925 | case 'C': | |
2926 | case 'G': | |
2927 | case 'H': | |
2928 | /* Note that in the macro case, these arguments are already | |
2929 | in MSBD form. (When handling the instruction in the | |
2930 | non-macro case, these arguments are sizes from which | |
2931 | MSBD values must be calculated.) */ | |
bf12938e | 2932 | INSERT_OPERAND (EXTMSBD, insn, va_arg (args, int)); |
5f74bc13 CD |
2933 | continue; |
2934 | ||
2935 | default: | |
2936 | internalError (); | |
2937 | } | |
2938 | continue; | |
2939 | ||
252b5132 RH |
2940 | case 't': |
2941 | case 'w': | |
2942 | case 'E': | |
bf12938e | 2943 | INSERT_OPERAND (RT, insn, va_arg (args, int)); |
252b5132 RH |
2944 | continue; |
2945 | ||
2946 | case 'c': | |
bf12938e | 2947 | INSERT_OPERAND (CODE, insn, va_arg (args, int)); |
38487616 TS |
2948 | continue; |
2949 | ||
252b5132 RH |
2950 | case 'T': |
2951 | case 'W': | |
bf12938e | 2952 | INSERT_OPERAND (FT, insn, va_arg (args, int)); |
252b5132 RH |
2953 | continue; |
2954 | ||
2955 | case 'd': | |
2956 | case 'G': | |
af7ee8bf | 2957 | case 'K': |
bf12938e | 2958 | INSERT_OPERAND (RD, insn, va_arg (args, int)); |
252b5132 RH |
2959 | continue; |
2960 | ||
4372b673 NC |
2961 | case 'U': |
2962 | { | |
2963 | int tmp = va_arg (args, int); | |
2964 | ||
bf12938e RS |
2965 | INSERT_OPERAND (RT, insn, tmp); |
2966 | INSERT_OPERAND (RD, insn, tmp); | |
beae10d5 | 2967 | continue; |
4372b673 NC |
2968 | } |
2969 | ||
252b5132 RH |
2970 | case 'V': |
2971 | case 'S': | |
bf12938e | 2972 | INSERT_OPERAND (FS, insn, va_arg (args, int)); |
252b5132 RH |
2973 | continue; |
2974 | ||
2975 | case 'z': | |
2976 | continue; | |
2977 | ||
2978 | case '<': | |
bf12938e | 2979 | INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); |
252b5132 RH |
2980 | continue; |
2981 | ||
2982 | case 'D': | |
bf12938e | 2983 | INSERT_OPERAND (FD, insn, va_arg (args, int)); |
252b5132 RH |
2984 | continue; |
2985 | ||
2986 | case 'B': | |
bf12938e | 2987 | INSERT_OPERAND (CODE20, insn, va_arg (args, int)); |
252b5132 RH |
2988 | continue; |
2989 | ||
4372b673 | 2990 | case 'J': |
bf12938e | 2991 | INSERT_OPERAND (CODE19, insn, va_arg (args, int)); |
4372b673 NC |
2992 | continue; |
2993 | ||
252b5132 | 2994 | case 'q': |
bf12938e | 2995 | INSERT_OPERAND (CODE2, insn, va_arg (args, int)); |
252b5132 RH |
2996 | continue; |
2997 | ||
2998 | case 'b': | |
2999 | case 's': | |
3000 | case 'r': | |
3001 | case 'v': | |
bf12938e | 3002 | INSERT_OPERAND (RS, insn, va_arg (args, int)); |
252b5132 RH |
3003 | continue; |
3004 | ||
3005 | case 'i': | |
3006 | case 'j': | |
3007 | case 'o': | |
6e1304d8 | 3008 | macro_read_relocs (&args, r); |
cdf6fd85 | 3009 | assert (*r == BFD_RELOC_GPREL16 |
f6688943 TS |
3010 | || *r == BFD_RELOC_MIPS_LITERAL |
3011 | || *r == BFD_RELOC_MIPS_HIGHER | |
3012 | || *r == BFD_RELOC_HI16_S | |
3013 | || *r == BFD_RELOC_LO16 | |
3014 | || *r == BFD_RELOC_MIPS_GOT16 | |
3015 | || *r == BFD_RELOC_MIPS_CALL16 | |
438c16b8 TS |
3016 | || *r == BFD_RELOC_MIPS_GOT_DISP |
3017 | || *r == BFD_RELOC_MIPS_GOT_PAGE | |
3018 | || *r == BFD_RELOC_MIPS_GOT_OFST | |
f6688943 | 3019 | || *r == BFD_RELOC_MIPS_GOT_LO16 |
3e722fb5 | 3020 | || *r == BFD_RELOC_MIPS_CALL_LO16); |
252b5132 RH |
3021 | continue; |
3022 | ||
3023 | case 'u': | |
6e1304d8 | 3024 | macro_read_relocs (&args, r); |
252b5132 RH |
3025 | assert (ep != NULL |
3026 | && (ep->X_op == O_constant | |
3027 | || (ep->X_op == O_symbol | |
f6688943 TS |
3028 | && (*r == BFD_RELOC_MIPS_HIGHEST |
3029 | || *r == BFD_RELOC_HI16_S | |
3030 | || *r == BFD_RELOC_HI16 | |
3031 | || *r == BFD_RELOC_GPREL16 | |
3032 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
3e722fb5 | 3033 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); |
252b5132 RH |
3034 | continue; |
3035 | ||
3036 | case 'p': | |
3037 | assert (ep != NULL); | |
3038 | /* | |
3039 | * This allows macro() to pass an immediate expression for | |
3040 | * creating short branches without creating a symbol. | |
0b25d3e6 AO |
3041 | * Note that the expression still might come from the assembly |
3042 | * input, in which case the value is not checked for range nor | |
3043 | * is a relocation entry generated (yuck). | |
252b5132 RH |
3044 | */ |
3045 | if (ep->X_op == O_constant) | |
3046 | { | |
3047 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
3048 | ep = NULL; | |
3049 | } | |
3050 | else | |
0b25d3e6 | 3051 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
3052 | continue; |
3053 | ||
3054 | case 'a': | |
3055 | assert (ep != NULL); | |
f6688943 | 3056 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
3057 | continue; |
3058 | ||
3059 | case 'C': | |
3060 | insn.insn_opcode |= va_arg (args, unsigned long); | |
3061 | continue; | |
3062 | ||
3063 | default: | |
3064 | internalError (); | |
3065 | } | |
3066 | break; | |
3067 | } | |
3068 | va_end (args); | |
f6688943 | 3069 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3070 | |
4d7206a2 | 3071 | append_insn (&insn, ep, r); |
252b5132 RH |
3072 | } |
3073 | ||
3074 | static void | |
67c0d1eb | 3075 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
17a2f251 | 3076 | va_list args) |
252b5132 | 3077 | { |
1e915849 | 3078 | struct mips_opcode *mo; |
252b5132 | 3079 | struct mips_cl_insn insn; |
f6688943 TS |
3080 | bfd_reloc_code_real_type r[3] |
3081 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 3082 | |
1e915849 RS |
3083 | mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
3084 | assert (mo); | |
3085 | assert (strcmp (name, mo->name) == 0); | |
252b5132 | 3086 | |
1e915849 | 3087 | while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) |
252b5132 | 3088 | { |
1e915849 RS |
3089 | ++mo; |
3090 | assert (mo->name); | |
3091 | assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
3092 | } |
3093 | ||
1e915849 | 3094 | create_insn (&insn, mo); |
252b5132 RH |
3095 | for (;;) |
3096 | { | |
3097 | int c; | |
3098 | ||
3099 | c = *fmt++; | |
3100 | switch (c) | |
3101 | { | |
3102 | case '\0': | |
3103 | break; | |
3104 | ||
3105 | case ',': | |
3106 | case '(': | |
3107 | case ')': | |
3108 | continue; | |
3109 | ||
3110 | case 'y': | |
3111 | case 'w': | |
bf12938e | 3112 | MIPS16_INSERT_OPERAND (RY, insn, va_arg (args, int)); |
252b5132 RH |
3113 | continue; |
3114 | ||
3115 | case 'x': | |
3116 | case 'v': | |
bf12938e | 3117 | MIPS16_INSERT_OPERAND (RX, insn, va_arg (args, int)); |
252b5132 RH |
3118 | continue; |
3119 | ||
3120 | case 'z': | |
bf12938e | 3121 | MIPS16_INSERT_OPERAND (RZ, insn, va_arg (args, int)); |
252b5132 RH |
3122 | continue; |
3123 | ||
3124 | case 'Z': | |
bf12938e | 3125 | MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (args, int)); |
252b5132 RH |
3126 | continue; |
3127 | ||
3128 | case '0': | |
3129 | case 'S': | |
3130 | case 'P': | |
3131 | case 'R': | |
3132 | continue; | |
3133 | ||
3134 | case 'X': | |
bf12938e | 3135 | MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (args, int)); |
252b5132 RH |
3136 | continue; |
3137 | ||
3138 | case 'Y': | |
3139 | { | |
3140 | int regno; | |
3141 | ||
3142 | regno = va_arg (args, int); | |
3143 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
3144 | insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
3145 | } | |
3146 | continue; | |
3147 | ||
3148 | case '<': | |
3149 | case '>': | |
3150 | case '4': | |
3151 | case '5': | |
3152 | case 'H': | |
3153 | case 'W': | |
3154 | case 'D': | |
3155 | case 'j': | |
3156 | case '8': | |
3157 | case 'V': | |
3158 | case 'C': | |
3159 | case 'U': | |
3160 | case 'k': | |
3161 | case 'K': | |
3162 | case 'p': | |
3163 | case 'q': | |
3164 | { | |
3165 | assert (ep != NULL); | |
3166 | ||
3167 | if (ep->X_op != O_constant) | |
874e8986 | 3168 | *r = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
3169 | else |
3170 | { | |
b34976b6 AM |
3171 | mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE, |
3172 | FALSE, &insn.insn_opcode, &insn.use_extend, | |
c4e7957c | 3173 | &insn.extend); |
252b5132 | 3174 | ep = NULL; |
f6688943 | 3175 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
3176 | } |
3177 | } | |
3178 | continue; | |
3179 | ||
3180 | case '6': | |
bf12938e | 3181 | MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (args, int)); |
252b5132 RH |
3182 | continue; |
3183 | } | |
3184 | ||
3185 | break; | |
3186 | } | |
3187 | ||
f6688943 | 3188 | assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 3189 | |
4d7206a2 | 3190 | append_insn (&insn, ep, r); |
252b5132 RH |
3191 | } |
3192 | ||
438c16b8 TS |
3193 | /* |
3194 | * Generate a "jalr" instruction with a relocation hint to the called | |
3195 | * function. This occurs in NewABI PIC code. | |
3196 | */ | |
3197 | static void | |
67c0d1eb | 3198 | macro_build_jalr (expressionS *ep) |
438c16b8 | 3199 | { |
685736be | 3200 | char *f = NULL; |
b34976b6 | 3201 | |
438c16b8 | 3202 | if (HAVE_NEWABI) |
f21f8242 | 3203 | { |
cc3d92a5 | 3204 | frag_grow (8); |
f21f8242 AO |
3205 | f = frag_more (0); |
3206 | } | |
67c0d1eb | 3207 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); |
438c16b8 | 3208 | if (HAVE_NEWABI) |
f21f8242 | 3209 | fix_new_exp (frag_now, f - frag_now->fr_literal, |
a105a300 | 3210 | 4, ep, FALSE, BFD_RELOC_MIPS_JALR); |
438c16b8 TS |
3211 | } |
3212 | ||
252b5132 RH |
3213 | /* |
3214 | * Generate a "lui" instruction. | |
3215 | */ | |
3216 | static void | |
67c0d1eb | 3217 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 RH |
3218 | { |
3219 | expressionS high_expr; | |
1e915849 | 3220 | const struct mips_opcode *mo; |
252b5132 | 3221 | struct mips_cl_insn insn; |
f6688943 TS |
3222 | bfd_reloc_code_real_type r[3] |
3223 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
5a38dc70 AM |
3224 | const char *name = "lui"; |
3225 | const char *fmt = "t,u"; | |
252b5132 RH |
3226 | |
3227 | assert (! mips_opts.mips16); | |
3228 | ||
4d7206a2 | 3229 | high_expr = *ep; |
252b5132 RH |
3230 | |
3231 | if (high_expr.X_op == O_constant) | |
3232 | { | |
3233 | /* we can compute the instruction now without a relocation entry */ | |
e7d556df TS |
3234 | high_expr.X_add_number = ((high_expr.X_add_number + 0x8000) |
3235 | >> 16) & 0xffff; | |
f6688943 | 3236 | *r = BFD_RELOC_UNUSED; |
252b5132 | 3237 | } |
78e1bb40 | 3238 | else |
252b5132 RH |
3239 | { |
3240 | assert (ep->X_op == O_symbol); | |
bbe506e8 TS |
3241 | /* _gp_disp is a special case, used from s_cpload. |
3242 | __gnu_local_gp is used if mips_no_shared. */ | |
252b5132 | 3243 | assert (mips_pic == NO_PIC |
78e1bb40 | 3244 | || (! HAVE_NEWABI |
aa6975fb ILT |
3245 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
3246 | || (! mips_in_shared | |
bbe506e8 TS |
3247 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
3248 | "__gnu_local_gp") == 0)); | |
f6688943 | 3249 | *r = BFD_RELOC_HI16_S; |
252b5132 RH |
3250 | } |
3251 | ||
1e915849 RS |
3252 | mo = hash_find (op_hash, name); |
3253 | assert (strcmp (name, mo->name) == 0); | |
3254 | assert (strcmp (fmt, mo->args) == 0); | |
3255 | create_insn (&insn, mo); | |
252b5132 | 3256 | |
bf12938e RS |
3257 | insn.insn_opcode = insn.insn_mo->match; |
3258 | INSERT_OPERAND (RT, insn, regnum); | |
f6688943 | 3259 | if (*r == BFD_RELOC_UNUSED) |
252b5132 RH |
3260 | { |
3261 | insn.insn_opcode |= high_expr.X_add_number; | |
4d7206a2 | 3262 | append_insn (&insn, NULL, r); |
252b5132 RH |
3263 | } |
3264 | else | |
4d7206a2 | 3265 | append_insn (&insn, &high_expr, r); |
252b5132 RH |
3266 | } |
3267 | ||
885add95 CD |
3268 | /* Generate a sequence of instructions to do a load or store from a constant |
3269 | offset off of a base register (breg) into/from a target register (treg), | |
3270 | using AT if necessary. */ | |
3271 | static void | |
67c0d1eb RS |
3272 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
3273 | int treg, int breg, int dbl) | |
885add95 CD |
3274 | { |
3275 | assert (ep->X_op == O_constant); | |
3276 | ||
256ab948 | 3277 | /* Sign-extending 32-bit constants makes their handling easier. */ |
d17e7bce TS |
3278 | if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff)) |
3279 | == ~((bfd_vma) 0x7fffffff))) | |
ae826530 | 3280 | { |
d17e7bce | 3281 | if (ep->X_add_number & ~((bfd_vma) 0xffffffff)) |
1b8e29e5 | 3282 | as_bad (_("constant too large")); |
ae826530 | 3283 | |
1b8e29e5 TS |
3284 | ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000) |
3285 | - 0x80000000); | |
ae826530 | 3286 | } |
256ab948 | 3287 | |
67c1ffbe | 3288 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 3289 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
3290 | as_warn (_("operand overflow")); |
3291 | ||
3292 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
3293 | { | |
3294 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 3295 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
3296 | } |
3297 | else | |
3298 | { | |
3299 | /* 32-bit offset, need multiple instructions and AT, like: | |
3300 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
3301 | addu $tempreg,$tempreg,$breg | |
3302 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
3303 | to handle the complete offset. */ | |
67c0d1eb RS |
3304 | macro_build_lui (ep, AT); |
3305 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
3306 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 CD |
3307 | |
3308 | if (mips_opts.noat) | |
8fc2e39e | 3309 | as_bad (_("Macro used $at after \".set noat\"")); |
885add95 CD |
3310 | } |
3311 | } | |
3312 | ||
252b5132 RH |
3313 | /* set_at() |
3314 | * Generates code to set the $at register to true (one) | |
3315 | * if reg is less than the immediate expression. | |
3316 | */ | |
3317 | static void | |
67c0d1eb | 3318 | set_at (int reg, int unsignedp) |
252b5132 RH |
3319 | { |
3320 | if (imm_expr.X_op == O_constant | |
3321 | && imm_expr.X_add_number >= -0x8000 | |
3322 | && imm_expr.X_add_number < 0x8000) | |
67c0d1eb RS |
3323 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
3324 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
3325 | else |
3326 | { | |
67c0d1eb RS |
3327 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
3328 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); | |
252b5132 RH |
3329 | } |
3330 | } | |
3331 | ||
13757d0c TS |
3332 | static void |
3333 | normalize_constant_expr (expressionS *ex) | |
3334 | { | |
3335 | if (ex->X_op == O_constant && HAVE_32BIT_GPRS) | |
3336 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
3337 | - 0x80000000); | |
3338 | } | |
3339 | ||
252b5132 RH |
3340 | /* Warn if an expression is not a constant. */ |
3341 | ||
3342 | static void | |
17a2f251 | 3343 | check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) |
252b5132 RH |
3344 | { |
3345 | if (ex->X_op == O_big) | |
3346 | as_bad (_("unsupported large constant")); | |
3347 | else if (ex->X_op != O_constant) | |
3348 | as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name); | |
13757d0c TS |
3349 | |
3350 | normalize_constant_expr (ex); | |
252b5132 RH |
3351 | } |
3352 | ||
3353 | /* Count the leading zeroes by performing a binary chop. This is a | |
3354 | bulky bit of source, but performance is a LOT better for the | |
3355 | majority of values than a simple loop to count the bits: | |
3356 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
3357 | if ((v) & (1 << (31 - lcnt))) | |
3358 | break; | |
3359 | However it is not code size friendly, and the gain will drop a bit | |
3360 | on certain cached systems. | |
3361 | */ | |
3362 | #define COUNT_TOP_ZEROES(v) \ | |
3363 | (((v) & ~0xffff) == 0 \ | |
3364 | ? ((v) & ~0xff) == 0 \ | |
3365 | ? ((v) & ~0xf) == 0 \ | |
3366 | ? ((v) & ~0x3) == 0 \ | |
3367 | ? ((v) & ~0x1) == 0 \ | |
3368 | ? !(v) \ | |
3369 | ? 32 \ | |
3370 | : 31 \ | |
3371 | : 30 \ | |
3372 | : ((v) & ~0x7) == 0 \ | |
3373 | ? 29 \ | |
3374 | : 28 \ | |
3375 | : ((v) & ~0x3f) == 0 \ | |
3376 | ? ((v) & ~0x1f) == 0 \ | |
3377 | ? 27 \ | |
3378 | : 26 \ | |
3379 | : ((v) & ~0x7f) == 0 \ | |
3380 | ? 25 \ | |
3381 | : 24 \ | |
3382 | : ((v) & ~0xfff) == 0 \ | |
3383 | ? ((v) & ~0x3ff) == 0 \ | |
3384 | ? ((v) & ~0x1ff) == 0 \ | |
3385 | ? 23 \ | |
3386 | : 22 \ | |
3387 | : ((v) & ~0x7ff) == 0 \ | |
3388 | ? 21 \ | |
3389 | : 20 \ | |
3390 | : ((v) & ~0x3fff) == 0 \ | |
3391 | ? ((v) & ~0x1fff) == 0 \ | |
3392 | ? 19 \ | |
3393 | : 18 \ | |
3394 | : ((v) & ~0x7fff) == 0 \ | |
3395 | ? 17 \ | |
3396 | : 16 \ | |
3397 | : ((v) & ~0xffffff) == 0 \ | |
3398 | ? ((v) & ~0xfffff) == 0 \ | |
3399 | ? ((v) & ~0x3ffff) == 0 \ | |
3400 | ? ((v) & ~0x1ffff) == 0 \ | |
3401 | ? 15 \ | |
3402 | : 14 \ | |
3403 | : ((v) & ~0x7ffff) == 0 \ | |
3404 | ? 13 \ | |
3405 | : 12 \ | |
3406 | : ((v) & ~0x3fffff) == 0 \ | |
3407 | ? ((v) & ~0x1fffff) == 0 \ | |
3408 | ? 11 \ | |
3409 | : 10 \ | |
3410 | : ((v) & ~0x7fffff) == 0 \ | |
3411 | ? 9 \ | |
3412 | : 8 \ | |
3413 | : ((v) & ~0xfffffff) == 0 \ | |
3414 | ? ((v) & ~0x3ffffff) == 0 \ | |
3415 | ? ((v) & ~0x1ffffff) == 0 \ | |
3416 | ? 7 \ | |
3417 | : 6 \ | |
3418 | : ((v) & ~0x7ffffff) == 0 \ | |
3419 | ? 5 \ | |
3420 | : 4 \ | |
3421 | : ((v) & ~0x3fffffff) == 0 \ | |
3422 | ? ((v) & ~0x1fffffff) == 0 \ | |
3423 | ? 3 \ | |
3424 | : 2 \ | |
3425 | : ((v) & ~0x7fffffff) == 0 \ | |
3426 | ? 1 \ | |
3427 | : 0) | |
3428 | ||
3429 | /* load_register() | |
67c1ffbe | 3430 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
3431 | * an absolute expression value into a register. |
3432 | */ | |
3433 | static void | |
67c0d1eb | 3434 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
3435 | { |
3436 | int freg; | |
3437 | expressionS hi32, lo32; | |
3438 | ||
3439 | if (ep->X_op != O_big) | |
3440 | { | |
3441 | assert (ep->X_op == O_constant); | |
256ab948 TS |
3442 | |
3443 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
d17e7bce TS |
3444 | if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff)) |
3445 | == ~((bfd_vma) 0x7fffffff))) | |
ae826530 | 3446 | { |
d17e7bce | 3447 | if (ep->X_add_number & ~((bfd_vma) 0xffffffff)) |
1b8e29e5 | 3448 | as_bad (_("constant too large")); |
ae826530 | 3449 | |
1b8e29e5 TS |
3450 | ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000) |
3451 | - 0x80000000); | |
ae826530 | 3452 | } |
256ab948 TS |
3453 | |
3454 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
3455 | { |
3456 | /* We can handle 16 bit signed values with an addiu to | |
3457 | $zero. No need to ever use daddiu here, since $zero and | |
3458 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 3459 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3460 | return; |
3461 | } | |
3462 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
3463 | { | |
3464 | /* We can handle 16 bit unsigned values with an ori to | |
3465 | $zero. */ | |
67c0d1eb | 3466 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3467 | return; |
3468 | } | |
256ab948 | 3469 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
3470 | { |
3471 | /* 32 bit values require an lui. */ | |
67c0d1eb | 3472 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 3473 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 3474 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
3475 | return; |
3476 | } | |
3477 | } | |
3478 | ||
3479 | /* The value is larger than 32 bits. */ | |
3480 | ||
ca4e0257 | 3481 | if (HAVE_32BIT_GPRS) |
252b5132 | 3482 | { |
956cd1d6 TS |
3483 | as_bad (_("Number (0x%lx) larger than 32 bits"), |
3484 | (unsigned long) ep->X_add_number); | |
67c0d1eb | 3485 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
3486 | return; |
3487 | } | |
3488 | ||
3489 | if (ep->X_op != O_big) | |
3490 | { | |
3491 | hi32 = *ep; | |
3492 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3493 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3494 | hi32.X_add_number &= 0xffffffff; | |
3495 | lo32 = *ep; | |
3496 | lo32.X_add_number &= 0xffffffff; | |
3497 | } | |
3498 | else | |
3499 | { | |
3500 | assert (ep->X_add_number > 2); | |
3501 | if (ep->X_add_number == 3) | |
3502 | generic_bignum[3] = 0; | |
3503 | else if (ep->X_add_number > 4) | |
3504 | as_bad (_("Number larger than 64 bits")); | |
3505 | lo32.X_op = O_constant; | |
3506 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
3507 | hi32.X_op = O_constant; | |
3508 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
3509 | } | |
3510 | ||
3511 | if (hi32.X_add_number == 0) | |
3512 | freg = 0; | |
3513 | else | |
3514 | { | |
3515 | int shift, bit; | |
3516 | unsigned long hi, lo; | |
3517 | ||
956cd1d6 | 3518 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
3519 | { |
3520 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
3521 | { | |
67c0d1eb | 3522 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
3523 | return; |
3524 | } | |
3525 | if (lo32.X_add_number & 0x80000000) | |
3526 | { | |
67c0d1eb | 3527 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
252b5132 | 3528 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 3529 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
3530 | return; |
3531 | } | |
3532 | } | |
252b5132 RH |
3533 | |
3534 | /* Check for 16bit shifted constant. We know that hi32 is | |
3535 | non-zero, so start the mask on the first bit of the hi32 | |
3536 | value. */ | |
3537 | shift = 17; | |
3538 | do | |
beae10d5 KH |
3539 | { |
3540 | unsigned long himask, lomask; | |
3541 | ||
3542 | if (shift < 32) | |
3543 | { | |
3544 | himask = 0xffff >> (32 - shift); | |
3545 | lomask = (0xffff << shift) & 0xffffffff; | |
3546 | } | |
3547 | else | |
3548 | { | |
3549 | himask = 0xffff << (shift - 32); | |
3550 | lomask = 0; | |
3551 | } | |
3552 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
3553 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
3554 | { | |
3555 | expressionS tmp; | |
3556 | ||
3557 | tmp.X_op = O_constant; | |
3558 | if (shift < 32) | |
3559 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
3560 | | (lo32.X_add_number >> shift)); | |
3561 | else | |
3562 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb RS |
3563 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
3564 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<", | |
3565 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
3566 | return; |
3567 | } | |
f9419b05 | 3568 | ++shift; |
beae10d5 KH |
3569 | } |
3570 | while (shift <= (64 - 16)); | |
252b5132 RH |
3571 | |
3572 | /* Find the bit number of the lowest one bit, and store the | |
3573 | shifted value in hi/lo. */ | |
3574 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
3575 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
3576 | if (lo != 0) | |
3577 | { | |
3578 | bit = 0; | |
3579 | while ((lo & 1) == 0) | |
3580 | { | |
3581 | lo >>= 1; | |
3582 | ++bit; | |
3583 | } | |
3584 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
3585 | hi >>= bit; | |
3586 | } | |
3587 | else | |
3588 | { | |
3589 | bit = 32; | |
3590 | while ((hi & 1) == 0) | |
3591 | { | |
3592 | hi >>= 1; | |
3593 | ++bit; | |
3594 | } | |
3595 | lo = hi; | |
3596 | hi = 0; | |
3597 | } | |
3598 | ||
3599 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
3600 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
3601 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
3602 | { |
3603 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 3604 | if (shift != 0) |
beae10d5 | 3605 | { |
252b5132 RH |
3606 | expressionS tmp; |
3607 | ||
3608 | /* This instruction will set the register to be all | |
3609 | ones. */ | |
beae10d5 KH |
3610 | tmp.X_op = O_constant; |
3611 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 3612 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
3613 | if (bit != 0) |
3614 | { | |
3615 | bit += shift; | |
67c0d1eb RS |
3616 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<", |
3617 | reg, reg, (bit >= 32) ? bit - 32 : bit); | |
beae10d5 | 3618 | } |
67c0d1eb RS |
3619 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<", |
3620 | reg, reg, (shift >= 32) ? shift - 32 : shift); | |
beae10d5 KH |
3621 | return; |
3622 | } | |
3623 | } | |
252b5132 RH |
3624 | |
3625 | /* Sign extend hi32 before calling load_register, because we can | |
3626 | generally get better code when we load a sign extended value. */ | |
3627 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 3628 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 3629 | load_register (reg, &hi32, 0); |
252b5132 RH |
3630 | freg = reg; |
3631 | } | |
3632 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
3633 | { | |
3634 | if (freg != 0) | |
3635 | { | |
67c0d1eb | 3636 | macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0); |
252b5132 RH |
3637 | freg = reg; |
3638 | } | |
3639 | } | |
3640 | else | |
3641 | { | |
3642 | expressionS mid16; | |
3643 | ||
956cd1d6 | 3644 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 3645 | { |
67c0d1eb RS |
3646 | macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); |
3647 | macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0); | |
beae10d5 KH |
3648 | return; |
3649 | } | |
252b5132 RH |
3650 | |
3651 | if (freg != 0) | |
3652 | { | |
67c0d1eb | 3653 | macro_build (NULL, "dsll", "d,w,<", reg, freg, 16); |
252b5132 RH |
3654 | freg = reg; |
3655 | } | |
3656 | mid16 = lo32; | |
3657 | mid16.X_add_number >>= 16; | |
67c0d1eb RS |
3658 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
3659 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
252b5132 RH |
3660 | freg = reg; |
3661 | } | |
3662 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 3663 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
3664 | } |
3665 | ||
269137b2 TS |
3666 | static inline void |
3667 | load_delay_nop (void) | |
3668 | { | |
3669 | if (!gpr_interlocks) | |
3670 | macro_build (NULL, "nop", ""); | |
3671 | } | |
3672 | ||
252b5132 RH |
3673 | /* Load an address into a register. */ |
3674 | ||
3675 | static void | |
67c0d1eb | 3676 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 3677 | { |
252b5132 RH |
3678 | if (ep->X_op != O_constant |
3679 | && ep->X_op != O_symbol) | |
3680 | { | |
3681 | as_bad (_("expression too complex")); | |
3682 | ep->X_op = O_constant; | |
3683 | } | |
3684 | ||
3685 | if (ep->X_op == O_constant) | |
3686 | { | |
67c0d1eb | 3687 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
3688 | return; |
3689 | } | |
3690 | ||
3691 | if (mips_pic == NO_PIC) | |
3692 | { | |
3693 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 3694 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
3695 | Otherwise we want |
3696 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
3697 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 3698 | If we have an addend, we always use the latter form. |
76b3015f | 3699 | |
d6bc6245 TS |
3700 | With 64bit address space and a usable $at we want |
3701 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3702 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
3703 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3704 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
3705 | dsll32 $reg,0 | |
3a482fd5 | 3706 | daddu $reg,$reg,$at |
76b3015f | 3707 | |
c03099e6 | 3708 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
3709 | on superscalar processors. |
3710 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
3711 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
3712 | dsll $reg,16 | |
3713 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
3714 | dsll $reg,16 | |
3715 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
6caf9ef4 TS |
3716 | |
3717 | For GP relative symbols in 64bit address space we can use | |
3718 | the same sequence as in 32bit address space. */ | |
aed1a261 | 3719 | if (HAVE_64BIT_SYMBOLS) |
d6bc6245 | 3720 | { |
6caf9ef4 TS |
3721 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
3722 | && !nopic_need_relax (ep->X_add_symbol, 1)) | |
3723 | { | |
3724 | relax_start (ep->X_add_symbol); | |
3725 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
3726 | mips_gp_register, BFD_RELOC_GPREL16); | |
3727 | relax_switch (); | |
3728 | } | |
d6bc6245 | 3729 | |
b8285c27 | 3730 | if (*used_at == 0 && !mips_opts.noat) |
d6bc6245 | 3731 | { |
67c0d1eb RS |
3732 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
3733 | macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S); | |
3734 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
3735 | BFD_RELOC_MIPS_HIGHER); | |
3736 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
3737 | macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0); | |
3738 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); | |
d6bc6245 TS |
3739 | *used_at = 1; |
3740 | } | |
3741 | else | |
3742 | { | |
67c0d1eb RS |
3743 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); |
3744 | macro_build (ep, "daddiu", "t,r,j", reg, reg, | |
3745 | BFD_RELOC_MIPS_HIGHER); | |
3746 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
3747 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); | |
3748 | macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); | |
3749 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); | |
d6bc6245 | 3750 | } |
6caf9ef4 TS |
3751 | |
3752 | if (mips_relax.sequence) | |
3753 | relax_end (); | |
d6bc6245 | 3754 | } |
252b5132 RH |
3755 | else |
3756 | { | |
d6bc6245 | 3757 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 3758 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
d6bc6245 | 3759 | { |
4d7206a2 | 3760 | relax_start (ep->X_add_symbol); |
67c0d1eb | 3761 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 3762 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 3763 | relax_switch (); |
d6bc6245 | 3764 | } |
67c0d1eb RS |
3765 | macro_build_lui (ep, reg); |
3766 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
3767 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
3768 | if (mips_relax.sequence) |
3769 | relax_end (); | |
d6bc6245 | 3770 | } |
252b5132 RH |
3771 | } |
3772 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
3773 | { | |
3774 | expressionS ex; | |
3775 | ||
3776 | /* If this is a reference to an external symbol, we want | |
3777 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3778 | Otherwise we want | |
3779 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3780 | nop | |
3781 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
3782 | If there is a constant, it must be added in after. |
3783 | ||
ed6fb7bd | 3784 | If we have NewABI, we want |
f5040a92 AO |
3785 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
3786 | unless we're referencing a global symbol with a non-zero | |
3787 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
3788 | if (HAVE_NEWABI) |
3789 | { | |
f5040a92 AO |
3790 | if (ep->X_add_number) |
3791 | { | |
4d7206a2 | 3792 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 3793 | ep->X_add_number = 0; |
4d7206a2 | 3794 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
3795 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
3796 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
3797 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
3798 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3799 | ex.X_op = O_constant; | |
67c0d1eb | 3800 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 3801 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 3802 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 3803 | relax_switch (); |
f5040a92 | 3804 | } |
67c0d1eb | 3805 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 3806 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
3807 | if (mips_relax.sequence) |
3808 | relax_end (); | |
ed6fb7bd SC |
3809 | } |
3810 | else | |
3811 | { | |
f5040a92 AO |
3812 | ex.X_add_number = ep->X_add_number; |
3813 | ep->X_add_number = 0; | |
67c0d1eb RS |
3814 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
3815 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 3816 | load_delay_nop (); |
4d7206a2 RS |
3817 | relax_start (ep->X_add_symbol); |
3818 | relax_switch (); | |
67c0d1eb | 3819 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 3820 | BFD_RELOC_LO16); |
4d7206a2 | 3821 | relax_end (); |
ed6fb7bd | 3822 | |
f5040a92 AO |
3823 | if (ex.X_add_number != 0) |
3824 | { | |
3825 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3826 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3827 | ex.X_op = O_constant; | |
67c0d1eb | 3828 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 3829 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 3830 | } |
252b5132 RH |
3831 | } |
3832 | } | |
3833 | else if (mips_pic == SVR4_PIC) | |
3834 | { | |
3835 | expressionS ex; | |
252b5132 RH |
3836 | |
3837 | /* This is the large GOT case. If this is a reference to an | |
3838 | external symbol, we want | |
3839 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3840 | addu $reg,$reg,$gp | |
3841 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
3842 | |
3843 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
3844 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
3845 | nop | |
3846 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 3847 | If there is a constant, it must be added in after. |
f5040a92 AO |
3848 | |
3849 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
3850 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
3851 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 3852 | */ |
438c16b8 TS |
3853 | if (HAVE_NEWABI) |
3854 | { | |
4d7206a2 | 3855 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 3856 | ep->X_add_number = 0; |
4d7206a2 | 3857 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
3858 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
3859 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
3860 | reg, reg, mips_gp_register); | |
3861 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
3862 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
3863 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
3864 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3865 | else if (ex.X_add_number) | |
3866 | { | |
3867 | ex.X_op = O_constant; | |
67c0d1eb RS |
3868 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
3869 | BFD_RELOC_LO16); | |
f5040a92 AO |
3870 | } |
3871 | ||
3872 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 3873 | relax_switch (); |
67c0d1eb | 3874 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 3875 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
3876 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
3877 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 3878 | relax_end (); |
438c16b8 | 3879 | } |
252b5132 | 3880 | else |
438c16b8 | 3881 | { |
f5040a92 AO |
3882 | ex.X_add_number = ep->X_add_number; |
3883 | ep->X_add_number = 0; | |
4d7206a2 | 3884 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
3885 | macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); |
3886 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
3887 | reg, reg, mips_gp_register); | |
3888 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
3889 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
3890 | relax_switch (); |
3891 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
3892 | { |
3893 | /* We need a nop before loading from $gp. This special | |
3894 | check is required because the lui which starts the main | |
3895 | instruction stream does not refer to $gp, and so will not | |
3896 | insert the nop which may be required. */ | |
67c0d1eb | 3897 | macro_build (NULL, "nop", ""); |
438c16b8 | 3898 | } |
67c0d1eb | 3899 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 3900 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 3901 | load_delay_nop (); |
67c0d1eb | 3902 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 3903 | BFD_RELOC_LO16); |
4d7206a2 | 3904 | relax_end (); |
438c16b8 | 3905 | |
f5040a92 AO |
3906 | if (ex.X_add_number != 0) |
3907 | { | |
3908 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3909 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3910 | ex.X_op = O_constant; | |
67c0d1eb RS |
3911 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
3912 | BFD_RELOC_LO16); | |
f5040a92 | 3913 | } |
252b5132 RH |
3914 | } |
3915 | } | |
252b5132 RH |
3916 | else |
3917 | abort (); | |
8fc2e39e TS |
3918 | |
3919 | if (mips_opts.noat && *used_at == 1) | |
3920 | as_bad (_("Macro used $at after \".set noat\"")); | |
252b5132 RH |
3921 | } |
3922 | ||
ea1fb5dc RS |
3923 | /* Move the contents of register SOURCE into register DEST. */ |
3924 | ||
3925 | static void | |
67c0d1eb | 3926 | move_register (int dest, int source) |
ea1fb5dc | 3927 | { |
67c0d1eb RS |
3928 | macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", |
3929 | dest, source, 0); | |
ea1fb5dc RS |
3930 | } |
3931 | ||
4d7206a2 | 3932 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
3933 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
3934 | The two alternatives are: | |
4d7206a2 RS |
3935 | |
3936 | Global symbol Local sybmol | |
3937 | ------------- ------------ | |
3938 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
3939 | ... ... | |
3940 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
3941 | ||
3942 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
3943 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
3944 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
3945 | |
3946 | static void | |
67c0d1eb | 3947 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
3948 | { |
3949 | expressionS global; | |
3950 | ||
3951 | global = *local; | |
3952 | global.X_add_number = 0; | |
3953 | ||
3954 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
3955 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
3956 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 3957 | relax_switch (); |
67c0d1eb RS |
3958 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
3959 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
3960 | relax_end (); |
3961 | } | |
3962 | ||
3963 | static void | |
67c0d1eb | 3964 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
3965 | { |
3966 | expressionS global; | |
3967 | ||
3968 | global.X_op = O_constant; | |
3969 | global.X_op_symbol = NULL; | |
3970 | global.X_add_symbol = NULL; | |
3971 | global.X_add_number = local->X_add_number; | |
3972 | ||
3973 | relax_start (local->X_add_symbol); | |
67c0d1eb | 3974 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
3975 | dest, dest, BFD_RELOC_LO16); |
3976 | relax_switch (); | |
67c0d1eb | 3977 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
3978 | relax_end (); |
3979 | } | |
3980 | ||
f6a22291 MR |
3981 | static void |
3982 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
3983 | { | |
3984 | expressionS global; | |
3985 | int hold_mips_optimize; | |
3986 | ||
3987 | global.X_op = O_constant; | |
3988 | global.X_op_symbol = NULL; | |
3989 | global.X_add_symbol = NULL; | |
3990 | global.X_add_number = local->X_add_number; | |
3991 | ||
3992 | relax_start (local->X_add_symbol); | |
3993 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
3994 | relax_switch (); | |
3995 | /* Set mips_optimize around the lui instruction to avoid | |
3996 | inserting an unnecessary nop after the lw. */ | |
3997 | hold_mips_optimize = mips_optimize; | |
3998 | mips_optimize = 2; | |
3999 | macro_build_lui (&global, tmp); | |
4000 | mips_optimize = hold_mips_optimize; | |
4001 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
4002 | relax_end (); | |
4003 | ||
4004 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
4005 | } | |
4006 | ||
252b5132 RH |
4007 | /* |
4008 | * Build macros | |
4009 | * This routine implements the seemingly endless macro or synthesized | |
4010 | * instructions and addressing modes in the mips assembly language. Many | |
4011 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 4012 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
4013 | * this verbose method. Others are not simple macros but are more like |
4014 | * optimizing code generation. | |
4015 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 4016 | * consecutively that would load AT with the upper half of the same address. |
252b5132 RH |
4017 | * The ensuing load upper instructions are ommited. This implies some kind |
4018 | * of global optimization. We currently only optimize within a single macro. | |
4019 | * For many of the load and store macros if the address is specified as a | |
4020 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
4021 | * first load register 'at' with zero and use it as the base register. The | |
4022 | * mips assembler simply uses register $zero. Just one tiny optimization | |
4023 | * we're missing. | |
4024 | */ | |
4025 | static void | |
17a2f251 | 4026 | macro (struct mips_cl_insn *ip) |
252b5132 RH |
4027 | { |
4028 | register int treg, sreg, dreg, breg; | |
4029 | int tempreg; | |
4030 | int mask; | |
43841e91 | 4031 | int used_at = 0; |
252b5132 RH |
4032 | expressionS expr1; |
4033 | const char *s; | |
4034 | const char *s2; | |
4035 | const char *fmt; | |
4036 | int likely = 0; | |
4037 | int dbl = 0; | |
4038 | int coproc = 0; | |
4039 | int lr = 0; | |
4040 | int imm = 0; | |
1abe91b1 | 4041 | int call = 0; |
252b5132 | 4042 | int off; |
67c0d1eb | 4043 | offsetT maxnum; |
252b5132 | 4044 | bfd_reloc_code_real_type r; |
252b5132 RH |
4045 | int hold_mips_optimize; |
4046 | ||
4047 | assert (! mips_opts.mips16); | |
4048 | ||
4049 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
4050 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
4051 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
4052 | mask = ip->insn_mo->mask; | |
4053 | ||
4054 | expr1.X_op = O_constant; | |
4055 | expr1.X_op_symbol = NULL; | |
4056 | expr1.X_add_symbol = NULL; | |
4057 | expr1.X_add_number = 1; | |
4058 | ||
4059 | switch (mask) | |
4060 | { | |
4061 | case M_DABS: | |
4062 | dbl = 1; | |
4063 | case M_ABS: | |
4064 | /* bgez $a0,.+12 | |
4065 | move v0,$a0 | |
4066 | sub v0,$zero,$a0 | |
4067 | */ | |
4068 | ||
b34976b6 | 4069 | mips_emit_delays (TRUE); |
252b5132 RH |
4070 | ++mips_opts.noreorder; |
4071 | mips_any_noreorder = 1; | |
4072 | ||
4073 | expr1.X_add_number = 8; | |
67c0d1eb | 4074 | macro_build (&expr1, "bgez", "s,p", sreg); |
252b5132 | 4075 | if (dreg == sreg) |
67c0d1eb | 4076 | macro_build (NULL, "nop", "", 0); |
252b5132 | 4077 | else |
67c0d1eb RS |
4078 | move_register (dreg, sreg); |
4079 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); | |
252b5132 RH |
4080 | |
4081 | --mips_opts.noreorder; | |
8fc2e39e | 4082 | break; |
252b5132 RH |
4083 | |
4084 | case M_ADD_I: | |
4085 | s = "addi"; | |
4086 | s2 = "add"; | |
4087 | goto do_addi; | |
4088 | case M_ADDU_I: | |
4089 | s = "addiu"; | |
4090 | s2 = "addu"; | |
4091 | goto do_addi; | |
4092 | case M_DADD_I: | |
4093 | dbl = 1; | |
4094 | s = "daddi"; | |
4095 | s2 = "dadd"; | |
4096 | goto do_addi; | |
4097 | case M_DADDU_I: | |
4098 | dbl = 1; | |
4099 | s = "daddiu"; | |
4100 | s2 = "daddu"; | |
4101 | do_addi: | |
4102 | if (imm_expr.X_op == O_constant | |
4103 | && imm_expr.X_add_number >= -0x8000 | |
4104 | && imm_expr.X_add_number < 0x8000) | |
4105 | { | |
67c0d1eb | 4106 | macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 4107 | break; |
252b5132 | 4108 | } |
8fc2e39e | 4109 | used_at = 1; |
67c0d1eb RS |
4110 | load_register (AT, &imm_expr, dbl); |
4111 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4112 | break; |
4113 | ||
4114 | case M_AND_I: | |
4115 | s = "andi"; | |
4116 | s2 = "and"; | |
4117 | goto do_bit; | |
4118 | case M_OR_I: | |
4119 | s = "ori"; | |
4120 | s2 = "or"; | |
4121 | goto do_bit; | |
4122 | case M_NOR_I: | |
4123 | s = ""; | |
4124 | s2 = "nor"; | |
4125 | goto do_bit; | |
4126 | case M_XOR_I: | |
4127 | s = "xori"; | |
4128 | s2 = "xor"; | |
4129 | do_bit: | |
4130 | if (imm_expr.X_op == O_constant | |
4131 | && imm_expr.X_add_number >= 0 | |
4132 | && imm_expr.X_add_number < 0x10000) | |
4133 | { | |
4134 | if (mask != M_NOR_I) | |
67c0d1eb | 4135 | macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
4136 | else |
4137 | { | |
67c0d1eb RS |
4138 | macro_build (&imm_expr, "ori", "t,r,i", |
4139 | treg, sreg, BFD_RELOC_LO16); | |
4140 | macro_build (NULL, "nor", "d,v,t", treg, treg, 0); | |
252b5132 | 4141 | } |
8fc2e39e | 4142 | break; |
252b5132 RH |
4143 | } |
4144 | ||
8fc2e39e | 4145 | used_at = 1; |
67c0d1eb RS |
4146 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4147 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
4148 | break; |
4149 | ||
4150 | case M_BEQ_I: | |
4151 | s = "beq"; | |
4152 | goto beq_i; | |
4153 | case M_BEQL_I: | |
4154 | s = "beql"; | |
4155 | likely = 1; | |
4156 | goto beq_i; | |
4157 | case M_BNE_I: | |
4158 | s = "bne"; | |
4159 | goto beq_i; | |
4160 | case M_BNEL_I: | |
4161 | s = "bnel"; | |
4162 | likely = 1; | |
4163 | beq_i: | |
4164 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4165 | { | |
67c0d1eb | 4166 | macro_build (&offset_expr, s, "s,t,p", sreg, 0); |
8fc2e39e | 4167 | break; |
252b5132 | 4168 | } |
8fc2e39e | 4169 | used_at = 1; |
67c0d1eb RS |
4170 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
4171 | macro_build (&offset_expr, s, "s,t,p", sreg, AT); | |
252b5132 RH |
4172 | break; |
4173 | ||
4174 | case M_BGEL: | |
4175 | likely = 1; | |
4176 | case M_BGE: | |
4177 | if (treg == 0) | |
4178 | { | |
67c0d1eb | 4179 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
8fc2e39e | 4180 | break; |
252b5132 RH |
4181 | } |
4182 | if (sreg == 0) | |
4183 | { | |
67c0d1eb | 4184 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg); |
8fc2e39e | 4185 | break; |
252b5132 | 4186 | } |
8fc2e39e | 4187 | used_at = 1; |
67c0d1eb RS |
4188 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
4189 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4190 | break; |
4191 | ||
4192 | case M_BGTL_I: | |
4193 | likely = 1; | |
4194 | case M_BGT_I: | |
4195 | /* check for > max integer */ | |
4196 | maxnum = 0x7fffffff; | |
ca4e0257 | 4197 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4198 | { |
4199 | maxnum <<= 16; | |
4200 | maxnum |= 0xffff; | |
4201 | maxnum <<= 16; | |
4202 | maxnum |= 0xffff; | |
4203 | } | |
4204 | if (imm_expr.X_op == O_constant | |
4205 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4206 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4207 | { |
4208 | do_false: | |
4209 | /* result is always false */ | |
4210 | if (! likely) | |
67c0d1eb | 4211 | macro_build (NULL, "nop", "", 0); |
252b5132 | 4212 | else |
67c0d1eb | 4213 | macro_build (&offset_expr, "bnel", "s,t,p", 0, 0); |
8fc2e39e | 4214 | break; |
252b5132 RH |
4215 | } |
4216 | if (imm_expr.X_op != O_constant) | |
4217 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4218 | ++imm_expr.X_add_number; |
252b5132 RH |
4219 | /* FALLTHROUGH */ |
4220 | case M_BGE_I: | |
4221 | case M_BGEL_I: | |
4222 | if (mask == M_BGEL_I) | |
4223 | likely = 1; | |
4224 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4225 | { | |
67c0d1eb | 4226 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); |
8fc2e39e | 4227 | break; |
252b5132 RH |
4228 | } |
4229 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4230 | { | |
67c0d1eb | 4231 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
8fc2e39e | 4232 | break; |
252b5132 RH |
4233 | } |
4234 | maxnum = 0x7fffffff; | |
ca4e0257 | 4235 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4236 | { |
4237 | maxnum <<= 16; | |
4238 | maxnum |= 0xffff; | |
4239 | maxnum <<= 16; | |
4240 | maxnum |= 0xffff; | |
4241 | } | |
4242 | maxnum = - maxnum - 1; | |
4243 | if (imm_expr.X_op == O_constant | |
4244 | && imm_expr.X_add_number <= maxnum | |
ca4e0257 | 4245 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4246 | { |
4247 | do_true: | |
4248 | /* result is always true */ | |
4249 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
67c0d1eb | 4250 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 4251 | break; |
252b5132 | 4252 | } |
8fc2e39e | 4253 | used_at = 1; |
67c0d1eb RS |
4254 | set_at (sreg, 0); |
4255 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4256 | break; |
4257 | ||
4258 | case M_BGEUL: | |
4259 | likely = 1; | |
4260 | case M_BGEU: | |
4261 | if (treg == 0) | |
4262 | goto do_true; | |
4263 | if (sreg == 0) | |
4264 | { | |
67c0d1eb | 4265 | macro_build (&offset_expr, likely ? "beql" : "beq", |
17a2f251 | 4266 | "s,t,p", 0, treg); |
8fc2e39e | 4267 | break; |
252b5132 | 4268 | } |
8fc2e39e | 4269 | used_at = 1; |
67c0d1eb RS |
4270 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
4271 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4272 | break; |
4273 | ||
4274 | case M_BGTUL_I: | |
4275 | likely = 1; | |
4276 | case M_BGTU_I: | |
4277 | if (sreg == 0 | |
ca4e0257 | 4278 | || (HAVE_32BIT_GPRS |
252b5132 | 4279 | && imm_expr.X_op == O_constant |
956cd1d6 | 4280 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4281 | goto do_false; |
4282 | if (imm_expr.X_op != O_constant) | |
4283 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4284 | ++imm_expr.X_add_number; |
252b5132 RH |
4285 | /* FALLTHROUGH */ |
4286 | case M_BGEU_I: | |
4287 | case M_BGEUL_I: | |
4288 | if (mask == M_BGEUL_I) | |
4289 | likely = 1; | |
4290 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4291 | goto do_true; | |
4292 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4293 | { | |
67c0d1eb | 4294 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4295 | "s,t,p", sreg, 0); |
8fc2e39e | 4296 | break; |
252b5132 | 4297 | } |
8fc2e39e | 4298 | used_at = 1; |
67c0d1eb RS |
4299 | set_at (sreg, 1); |
4300 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4301 | break; |
4302 | ||
4303 | case M_BGTL: | |
4304 | likely = 1; | |
4305 | case M_BGT: | |
4306 | if (treg == 0) | |
4307 | { | |
67c0d1eb | 4308 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); |
8fc2e39e | 4309 | break; |
252b5132 RH |
4310 | } |
4311 | if (sreg == 0) | |
4312 | { | |
67c0d1eb | 4313 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg); |
8fc2e39e | 4314 | break; |
252b5132 | 4315 | } |
8fc2e39e | 4316 | used_at = 1; |
67c0d1eb RS |
4317 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
4318 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4319 | break; |
4320 | ||
4321 | case M_BGTUL: | |
4322 | likely = 1; | |
4323 | case M_BGTU: | |
4324 | if (treg == 0) | |
4325 | { | |
67c0d1eb | 4326 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4327 | "s,t,p", sreg, 0); |
8fc2e39e | 4328 | break; |
252b5132 RH |
4329 | } |
4330 | if (sreg == 0) | |
4331 | goto do_false; | |
8fc2e39e | 4332 | used_at = 1; |
67c0d1eb RS |
4333 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
4334 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4335 | break; |
4336 | ||
4337 | case M_BLEL: | |
4338 | likely = 1; | |
4339 | case M_BLE: | |
4340 | if (treg == 0) | |
4341 | { | |
67c0d1eb | 4342 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
8fc2e39e | 4343 | break; |
252b5132 RH |
4344 | } |
4345 | if (sreg == 0) | |
4346 | { | |
67c0d1eb | 4347 | macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg); |
8fc2e39e | 4348 | break; |
252b5132 | 4349 | } |
8fc2e39e | 4350 | used_at = 1; |
67c0d1eb RS |
4351 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); |
4352 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4353 | break; |
4354 | ||
4355 | case M_BLEL_I: | |
4356 | likely = 1; | |
4357 | case M_BLE_I: | |
4358 | maxnum = 0x7fffffff; | |
ca4e0257 | 4359 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
252b5132 RH |
4360 | { |
4361 | maxnum <<= 16; | |
4362 | maxnum |= 0xffff; | |
4363 | maxnum <<= 16; | |
4364 | maxnum |= 0xffff; | |
4365 | } | |
4366 | if (imm_expr.X_op == O_constant | |
4367 | && imm_expr.X_add_number >= maxnum | |
ca4e0257 | 4368 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
252b5132 RH |
4369 | goto do_true; |
4370 | if (imm_expr.X_op != O_constant) | |
4371 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4372 | ++imm_expr.X_add_number; |
252b5132 RH |
4373 | /* FALLTHROUGH */ |
4374 | case M_BLT_I: | |
4375 | case M_BLTL_I: | |
4376 | if (mask == M_BLTL_I) | |
4377 | likely = 1; | |
4378 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4379 | { | |
67c0d1eb | 4380 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
8fc2e39e | 4381 | break; |
252b5132 RH |
4382 | } |
4383 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4384 | { | |
67c0d1eb | 4385 | macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); |
8fc2e39e | 4386 | break; |
252b5132 | 4387 | } |
8fc2e39e | 4388 | used_at = 1; |
67c0d1eb RS |
4389 | set_at (sreg, 0); |
4390 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4391 | break; |
4392 | ||
4393 | case M_BLEUL: | |
4394 | likely = 1; | |
4395 | case M_BLEU: | |
4396 | if (treg == 0) | |
4397 | { | |
67c0d1eb | 4398 | macro_build (&offset_expr, likely ? "beql" : "beq", |
17a2f251 | 4399 | "s,t,p", sreg, 0); |
8fc2e39e | 4400 | break; |
252b5132 RH |
4401 | } |
4402 | if (sreg == 0) | |
4403 | goto do_true; | |
8fc2e39e | 4404 | used_at = 1; |
67c0d1eb RS |
4405 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); |
4406 | macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); | |
252b5132 RH |
4407 | break; |
4408 | ||
4409 | case M_BLEUL_I: | |
4410 | likely = 1; | |
4411 | case M_BLEU_I: | |
4412 | if (sreg == 0 | |
ca4e0257 | 4413 | || (HAVE_32BIT_GPRS |
252b5132 | 4414 | && imm_expr.X_op == O_constant |
956cd1d6 | 4415 | && imm_expr.X_add_number == (offsetT) 0xffffffff)) |
252b5132 RH |
4416 | goto do_true; |
4417 | if (imm_expr.X_op != O_constant) | |
4418 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 4419 | ++imm_expr.X_add_number; |
252b5132 RH |
4420 | /* FALLTHROUGH */ |
4421 | case M_BLTU_I: | |
4422 | case M_BLTUL_I: | |
4423 | if (mask == M_BLTUL_I) | |
4424 | likely = 1; | |
4425 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4426 | goto do_false; | |
4427 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4428 | { | |
67c0d1eb | 4429 | macro_build (&offset_expr, likely ? "beql" : "beq", |
252b5132 | 4430 | "s,t,p", sreg, 0); |
8fc2e39e | 4431 | break; |
252b5132 | 4432 | } |
8fc2e39e | 4433 | used_at = 1; |
67c0d1eb RS |
4434 | set_at (sreg, 1); |
4435 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4436 | break; |
4437 | ||
4438 | case M_BLTL: | |
4439 | likely = 1; | |
4440 | case M_BLT: | |
4441 | if (treg == 0) | |
4442 | { | |
67c0d1eb | 4443 | macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); |
8fc2e39e | 4444 | break; |
252b5132 RH |
4445 | } |
4446 | if (sreg == 0) | |
4447 | { | |
67c0d1eb | 4448 | macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg); |
8fc2e39e | 4449 | break; |
252b5132 | 4450 | } |
8fc2e39e | 4451 | used_at = 1; |
67c0d1eb RS |
4452 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); |
4453 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4454 | break; |
4455 | ||
4456 | case M_BLTUL: | |
4457 | likely = 1; | |
4458 | case M_BLTU: | |
4459 | if (treg == 0) | |
4460 | goto do_false; | |
4461 | if (sreg == 0) | |
4462 | { | |
67c0d1eb | 4463 | macro_build (&offset_expr, likely ? "bnel" : "bne", |
17a2f251 | 4464 | "s,t,p", 0, treg); |
8fc2e39e | 4465 | break; |
252b5132 | 4466 | } |
8fc2e39e | 4467 | used_at = 1; |
67c0d1eb RS |
4468 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); |
4469 | macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); | |
252b5132 RH |
4470 | break; |
4471 | ||
5f74bc13 CD |
4472 | case M_DEXT: |
4473 | { | |
4474 | unsigned long pos; | |
4475 | unsigned long size; | |
4476 | ||
4477 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
4478 | { | |
4479 | as_bad (_("Unsupported large constant")); | |
4480 | pos = size = 1; | |
4481 | } | |
4482 | else | |
4483 | { | |
4484 | pos = (unsigned long) imm_expr.X_add_number; | |
4485 | size = (unsigned long) imm2_expr.X_add_number; | |
4486 | } | |
4487 | ||
4488 | if (pos > 63) | |
4489 | { | |
4490 | as_bad (_("Improper position (%lu)"), pos); | |
4491 | pos = 1; | |
4492 | } | |
4493 | if (size == 0 || size > 64 | |
4494 | || (pos + size - 1) > 63) | |
4495 | { | |
4496 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
4497 | size, pos); | |
4498 | size = 1; | |
4499 | } | |
4500 | ||
4501 | if (size <= 32 && pos < 32) | |
4502 | { | |
4503 | s = "dext"; | |
4504 | fmt = "t,r,+A,+C"; | |
4505 | } | |
4506 | else if (size <= 32) | |
4507 | { | |
4508 | s = "dextu"; | |
4509 | fmt = "t,r,+E,+H"; | |
4510 | } | |
4511 | else | |
4512 | { | |
4513 | s = "dextm"; | |
4514 | fmt = "t,r,+A,+G"; | |
4515 | } | |
67c0d1eb | 4516 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, size - 1); |
5f74bc13 | 4517 | } |
8fc2e39e | 4518 | break; |
5f74bc13 CD |
4519 | |
4520 | case M_DINS: | |
4521 | { | |
4522 | unsigned long pos; | |
4523 | unsigned long size; | |
4524 | ||
4525 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) | |
4526 | { | |
4527 | as_bad (_("Unsupported large constant")); | |
4528 | pos = size = 1; | |
4529 | } | |
4530 | else | |
4531 | { | |
4532 | pos = (unsigned long) imm_expr.X_add_number; | |
4533 | size = (unsigned long) imm2_expr.X_add_number; | |
4534 | } | |
4535 | ||
4536 | if (pos > 63) | |
4537 | { | |
4538 | as_bad (_("Improper position (%lu)"), pos); | |
4539 | pos = 1; | |
4540 | } | |
4541 | if (size == 0 || size > 64 | |
4542 | || (pos + size - 1) > 63) | |
4543 | { | |
4544 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
4545 | size, pos); | |
4546 | size = 1; | |
4547 | } | |
4548 | ||
4549 | if (pos < 32 && (pos + size - 1) < 32) | |
4550 | { | |
4551 | s = "dins"; | |
4552 | fmt = "t,r,+A,+B"; | |
4553 | } | |
4554 | else if (pos >= 32) | |
4555 | { | |
4556 | s = "dinsu"; | |
4557 | fmt = "t,r,+E,+F"; | |
4558 | } | |
4559 | else | |
4560 | { | |
4561 | s = "dinsm"; | |
4562 | fmt = "t,r,+A,+F"; | |
4563 | } | |
67c0d1eb RS |
4564 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, |
4565 | pos + size - 1); | |
5f74bc13 | 4566 | } |
8fc2e39e | 4567 | break; |
5f74bc13 | 4568 | |
252b5132 RH |
4569 | case M_DDIV_3: |
4570 | dbl = 1; | |
4571 | case M_DIV_3: | |
4572 | s = "mflo"; | |
4573 | goto do_div3; | |
4574 | case M_DREM_3: | |
4575 | dbl = 1; | |
4576 | case M_REM_3: | |
4577 | s = "mfhi"; | |
4578 | do_div3: | |
4579 | if (treg == 0) | |
4580 | { | |
4581 | as_warn (_("Divide by zero.")); | |
4582 | if (mips_trap) | |
67c0d1eb | 4583 | macro_build (NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 4584 | else |
67c0d1eb | 4585 | macro_build (NULL, "break", "c", 7); |
8fc2e39e | 4586 | break; |
252b5132 RH |
4587 | } |
4588 | ||
b34976b6 | 4589 | mips_emit_delays (TRUE); |
252b5132 RH |
4590 | ++mips_opts.noreorder; |
4591 | mips_any_noreorder = 1; | |
4592 | if (mips_trap) | |
4593 | { | |
67c0d1eb RS |
4594 | macro_build (NULL, "teq", "s,t,q", treg, 0, 7); |
4595 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); | |
252b5132 RH |
4596 | } |
4597 | else | |
4598 | { | |
4599 | expr1.X_add_number = 8; | |
67c0d1eb RS |
4600 | macro_build (&expr1, "bne", "s,t,p", treg, 0); |
4601 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); | |
4602 | macro_build (NULL, "break", "c", 7); | |
252b5132 RH |
4603 | } |
4604 | expr1.X_add_number = -1; | |
8fc2e39e | 4605 | used_at = 1; |
f6a22291 | 4606 | load_register (AT, &expr1, dbl); |
252b5132 | 4607 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
67c0d1eb | 4608 | macro_build (&expr1, "bne", "s,t,p", treg, AT); |
252b5132 RH |
4609 | if (dbl) |
4610 | { | |
4611 | expr1.X_add_number = 1; | |
f6a22291 | 4612 | load_register (AT, &expr1, dbl); |
67c0d1eb | 4613 | macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31); |
252b5132 RH |
4614 | } |
4615 | else | |
4616 | { | |
4617 | expr1.X_add_number = 0x80000000; | |
67c0d1eb | 4618 | macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16); |
252b5132 RH |
4619 | } |
4620 | if (mips_trap) | |
4621 | { | |
67c0d1eb | 4622 | macro_build (NULL, "teq", "s,t,q", sreg, AT, 6); |
252b5132 RH |
4623 | /* We want to close the noreorder block as soon as possible, so |
4624 | that later insns are available for delay slot filling. */ | |
4625 | --mips_opts.noreorder; | |
4626 | } | |
4627 | else | |
4628 | { | |
4629 | expr1.X_add_number = 8; | |
67c0d1eb RS |
4630 | macro_build (&expr1, "bne", "s,t,p", sreg, AT); |
4631 | macro_build (NULL, "nop", "", 0); | |
252b5132 RH |
4632 | |
4633 | /* We want to close the noreorder block as soon as possible, so | |
4634 | that later insns are available for delay slot filling. */ | |
4635 | --mips_opts.noreorder; | |
4636 | ||
67c0d1eb | 4637 | macro_build (NULL, "break", "c", 6); |
252b5132 | 4638 | } |
67c0d1eb | 4639 | macro_build (NULL, s, "d", dreg); |
252b5132 RH |
4640 | break; |
4641 | ||
4642 | case M_DIV_3I: | |
4643 | s = "div"; | |
4644 | s2 = "mflo"; | |
4645 | goto do_divi; | |
4646 | case M_DIVU_3I: | |
4647 | s = "divu"; | |
4648 | s2 = "mflo"; | |
4649 | goto do_divi; | |
4650 | case M_REM_3I: | |
4651 | s = "div"; | |
4652 | s2 = "mfhi"; | |
4653 | goto do_divi; | |
4654 | case M_REMU_3I: | |
4655 | s = "divu"; | |
4656 | s2 = "mfhi"; | |
4657 | goto do_divi; | |
4658 | case M_DDIV_3I: | |
4659 | dbl = 1; | |
4660 | s = "ddiv"; | |
4661 | s2 = "mflo"; | |
4662 | goto do_divi; | |
4663 | case M_DDIVU_3I: | |
4664 | dbl = 1; | |
4665 | s = "ddivu"; | |
4666 | s2 = "mflo"; | |
4667 | goto do_divi; | |
4668 | case M_DREM_3I: | |
4669 | dbl = 1; | |
4670 | s = "ddiv"; | |
4671 | s2 = "mfhi"; | |
4672 | goto do_divi; | |
4673 | case M_DREMU_3I: | |
4674 | dbl = 1; | |
4675 | s = "ddivu"; | |
4676 | s2 = "mfhi"; | |
4677 | do_divi: | |
4678 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4679 | { | |
4680 | as_warn (_("Divide by zero.")); | |
4681 | if (mips_trap) | |
67c0d1eb | 4682 | macro_build (NULL, "teq", "s,t,q", 0, 0, 7); |
252b5132 | 4683 | else |
67c0d1eb | 4684 | macro_build (NULL, "break", "c", 7); |
8fc2e39e | 4685 | break; |
252b5132 RH |
4686 | } |
4687 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4688 | { | |
4689 | if (strcmp (s2, "mflo") == 0) | |
67c0d1eb | 4690 | move_register (dreg, sreg); |
252b5132 | 4691 | else |
67c0d1eb | 4692 | move_register (dreg, 0); |
8fc2e39e | 4693 | break; |
252b5132 RH |
4694 | } |
4695 | if (imm_expr.X_op == O_constant | |
4696 | && imm_expr.X_add_number == -1 | |
4697 | && s[strlen (s) - 1] != 'u') | |
4698 | { | |
4699 | if (strcmp (s2, "mflo") == 0) | |
4700 | { | |
67c0d1eb | 4701 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg); |
252b5132 RH |
4702 | } |
4703 | else | |
67c0d1eb | 4704 | move_register (dreg, 0); |
8fc2e39e | 4705 | break; |
252b5132 RH |
4706 | } |
4707 | ||
8fc2e39e | 4708 | used_at = 1; |
67c0d1eb RS |
4709 | load_register (AT, &imm_expr, dbl); |
4710 | macro_build (NULL, s, "z,s,t", sreg, AT); | |
4711 | macro_build (NULL, s2, "d", dreg); | |
252b5132 RH |
4712 | break; |
4713 | ||
4714 | case M_DIVU_3: | |
4715 | s = "divu"; | |
4716 | s2 = "mflo"; | |
4717 | goto do_divu3; | |
4718 | case M_REMU_3: | |
4719 | s = "divu"; | |
4720 | s2 = "mfhi"; | |
4721 | goto do_divu3; | |
4722 | case M_DDIVU_3: | |
4723 | s = "ddivu"; | |
4724 | s2 = "mflo"; | |
4725 | goto do_divu3; | |
4726 | case M_DREMU_3: | |
4727 | s = "ddivu"; | |
4728 | s2 = "mfhi"; | |
4729 | do_divu3: | |
b34976b6 | 4730 | mips_emit_delays (TRUE); |
252b5132 RH |
4731 | ++mips_opts.noreorder; |
4732 | mips_any_noreorder = 1; | |
4733 | if (mips_trap) | |
4734 | { | |
67c0d1eb RS |
4735 | macro_build (NULL, "teq", "s,t,q", treg, 0, 7); |
4736 | macro_build (NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
4737 | /* We want to close the noreorder block as soon as possible, so |
4738 | that later insns are available for delay slot filling. */ | |
4739 | --mips_opts.noreorder; | |
4740 | } | |
4741 | else | |
4742 | { | |
4743 | expr1.X_add_number = 8; | |
67c0d1eb RS |
4744 | macro_build (&expr1, "bne", "s,t,p", treg, 0); |
4745 | macro_build (NULL, s, "z,s,t", sreg, treg); | |
252b5132 RH |
4746 | |
4747 | /* We want to close the noreorder block as soon as possible, so | |
4748 | that later insns are available for delay slot filling. */ | |
4749 | --mips_opts.noreorder; | |
67c0d1eb | 4750 | macro_build (NULL, "break", "c", 7); |
252b5132 | 4751 | } |
67c0d1eb | 4752 | macro_build (NULL, s2, "d", dreg); |
8fc2e39e | 4753 | break; |
252b5132 | 4754 | |
1abe91b1 MR |
4755 | case M_DLCA_AB: |
4756 | dbl = 1; | |
4757 | case M_LCA_AB: | |
4758 | call = 1; | |
4759 | goto do_la; | |
252b5132 RH |
4760 | case M_DLA_AB: |
4761 | dbl = 1; | |
4762 | case M_LA_AB: | |
1abe91b1 | 4763 | do_la: |
252b5132 RH |
4764 | /* Load the address of a symbol into a register. If breg is not |
4765 | zero, we then add a base register to it. */ | |
4766 | ||
3bec30a8 TS |
4767 | if (dbl && HAVE_32BIT_GPRS) |
4768 | as_warn (_("dla used to load 32-bit register")); | |
4769 | ||
c90bbe5b | 4770 | if (! dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
4771 | as_warn (_("la used to load 64-bit address")); |
4772 | ||
0c11417f MR |
4773 | if (offset_expr.X_op == O_constant |
4774 | && offset_expr.X_add_number >= -0x8000 | |
4775 | && offset_expr.X_add_number < 0x8000) | |
4776 | { | |
aed1a261 | 4777 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
17a2f251 | 4778 | "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 4779 | break; |
0c11417f MR |
4780 | } |
4781 | ||
b8285c27 | 4782 | if (!mips_opts.noat && (treg == breg)) |
afdbd6d0 CD |
4783 | { |
4784 | tempreg = AT; | |
4785 | used_at = 1; | |
4786 | } | |
4787 | else | |
4788 | { | |
4789 | tempreg = treg; | |
afdbd6d0 CD |
4790 | } |
4791 | ||
252b5132 RH |
4792 | if (offset_expr.X_op != O_symbol |
4793 | && offset_expr.X_op != O_constant) | |
4794 | { | |
4795 | as_bad (_("expression too complex")); | |
4796 | offset_expr.X_op = O_constant; | |
4797 | } | |
4798 | ||
252b5132 | 4799 | if (offset_expr.X_op == O_constant) |
aed1a261 | 4800 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
4801 | else if (mips_pic == NO_PIC) |
4802 | { | |
d6bc6245 | 4803 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 4804 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
4805 | Otherwise we want |
4806 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4807 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4808 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 4809 | so we may as well always use the latter form. |
76b3015f | 4810 | |
6caf9ef4 TS |
4811 | With 64bit address space and a usable $at we want |
4812 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4813 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
4814 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4815 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
4816 | dsll32 $tempreg,0 | |
4817 | daddu $tempreg,$tempreg,$at | |
4818 | ||
4819 | If $at is already in use, we use a path which is suboptimal | |
4820 | on superscalar processors. | |
4821 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
4822 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
4823 | dsll $tempreg,16 | |
4824 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4825 | dsll $tempreg,16 | |
4826 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
4827 | ||
4828 | For GP relative symbols in 64bit address space we can use | |
4829 | the same sequence as in 32bit address space. */ | |
aed1a261 | 4830 | if (HAVE_64BIT_SYMBOLS) |
252b5132 | 4831 | { |
6caf9ef4 TS |
4832 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
4833 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
4834 | { | |
4835 | relax_start (offset_expr.X_add_symbol); | |
4836 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
4837 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4838 | relax_switch (); | |
4839 | } | |
d6bc6245 | 4840 | |
b8285c27 | 4841 | if (used_at == 0 && !mips_opts.noat) |
98d3f06f | 4842 | { |
67c0d1eb | 4843 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 4844 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 4845 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 4846 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 4847 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 4848 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 4849 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 4850 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb RS |
4851 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); |
4852 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
98d3f06f KH |
4853 | used_at = 1; |
4854 | } | |
4855 | else | |
4856 | { | |
67c0d1eb | 4857 | macro_build (&offset_expr, "lui", "t,u", |
17a2f251 | 4858 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 4859 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 4860 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb RS |
4861 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
4862 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 4863 | tempreg, tempreg, BFD_RELOC_HI16_S); |
67c0d1eb RS |
4864 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); |
4865 | macro_build (&offset_expr, "daddiu", "t,r,j", | |
17a2f251 | 4866 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 4867 | } |
6caf9ef4 TS |
4868 | |
4869 | if (mips_relax.sequence) | |
4870 | relax_end (); | |
98d3f06f KH |
4871 | } |
4872 | else | |
4873 | { | |
4874 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 4875 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
98d3f06f | 4876 | { |
4d7206a2 | 4877 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
4878 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
4879 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 4880 | relax_switch (); |
98d3f06f | 4881 | } |
6943caf0 ILT |
4882 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
4883 | as_bad (_("offset too large")); | |
67c0d1eb RS |
4884 | macro_build_lui (&offset_expr, tempreg); |
4885 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
4886 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
4887 | if (mips_relax.sequence) |
4888 | relax_end (); | |
98d3f06f | 4889 | } |
252b5132 | 4890 | } |
f5040a92 | 4891 | else if (mips_pic == SVR4_PIC && ! mips_big_got && ! HAVE_NEWABI) |
252b5132 | 4892 | { |
9117d219 NC |
4893 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
4894 | ||
252b5132 RH |
4895 | /* If this is a reference to an external symbol, and there |
4896 | is no constant, we want | |
4897 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 4898 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 4899 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
4900 | For a local symbol, we want |
4901 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4902 | nop | |
4903 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4904 | ||
4905 | If we have a small constant, and this is a reference to | |
4906 | an external symbol, we want | |
4907 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4908 | nop | |
4909 | addiu $tempreg,$tempreg,<constant> | |
4910 | For a local symbol, we want the same instruction | |
4911 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
4912 | addiu instruction. | |
4913 | ||
4914 | If we have a large constant, and this is a reference to | |
4915 | an external symbol, we want | |
4916 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4917 | lui $at,<hiconstant> | |
4918 | addiu $at,$at,<loconstant> | |
4919 | addu $tempreg,$tempreg,$at | |
4920 | For a local symbol, we want the same instruction | |
4921 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 4922 | addiu instruction. |
ed6fb7bd SC |
4923 | */ |
4924 | ||
4d7206a2 | 4925 | if (offset_expr.X_add_number == 0) |
252b5132 | 4926 | { |
4d7206a2 RS |
4927 | if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
4928 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; | |
4929 | ||
4930 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
4931 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
4932 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 4933 | if (breg != 0) |
252b5132 RH |
4934 | { |
4935 | /* We're going to put in an addu instruction using | |
4936 | tempreg, so we may as well insert the nop right | |
4937 | now. */ | |
269137b2 | 4938 | load_delay_nop (); |
252b5132 | 4939 | } |
4d7206a2 | 4940 | relax_switch (); |
67c0d1eb RS |
4941 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
4942 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 4943 | load_delay_nop (); |
67c0d1eb RS |
4944 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
4945 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 4946 | relax_end (); |
252b5132 RH |
4947 | /* FIXME: If breg == 0, and the next instruction uses |
4948 | $tempreg, then if this variant case is used an extra | |
4949 | nop will be generated. */ | |
4950 | } | |
4d7206a2 RS |
4951 | else if (offset_expr.X_add_number >= -0x8000 |
4952 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 4953 | { |
67c0d1eb | 4954 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 4955 | load_delay_nop (); |
67c0d1eb | 4956 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
4957 | } |
4958 | else | |
4959 | { | |
4d7206a2 RS |
4960 | expr1.X_add_number = offset_expr.X_add_number; |
4961 | offset_expr.X_add_number = | |
4962 | ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
67c0d1eb | 4963 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 4964 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
4965 | /* If we are going to add in a base register, and the |
4966 | target register and the base register are the same, | |
4967 | then we are using AT as a temporary register. Since | |
4968 | we want to load the constant into AT, we add our | |
4969 | current AT (from the global offset table) and the | |
4970 | register into the register now, and pretend we were | |
4971 | not using a base register. */ | |
67c0d1eb | 4972 | if (breg == treg) |
252b5132 | 4973 | { |
269137b2 | 4974 | load_delay_nop (); |
67c0d1eb | 4975 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 4976 | treg, AT, breg); |
252b5132 RH |
4977 | breg = 0; |
4978 | tempreg = treg; | |
252b5132 | 4979 | } |
f6a22291 | 4980 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
4981 | used_at = 1; |
4982 | } | |
4983 | } | |
f5040a92 AO |
4984 | else if (mips_pic == SVR4_PIC && ! mips_big_got && HAVE_NEWABI) |
4985 | { | |
67c0d1eb | 4986 | int add_breg_early = 0; |
f5040a92 AO |
4987 | |
4988 | /* If this is a reference to an external, and there is no | |
4989 | constant, or local symbol (*), with or without a | |
4990 | constant, we want | |
4991 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 4992 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
4993 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
4994 | ||
4995 | If we have a small constant, and this is a reference to | |
4996 | an external symbol, we want | |
4997 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
4998 | addiu $tempreg,$tempreg,<constant> | |
4999 | ||
5000 | If we have a large constant, and this is a reference to | |
5001 | an external symbol, we want | |
5002 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
5003 | lui $at,<hiconstant> | |
5004 | addiu $at,$at,<loconstant> | |
5005 | addu $tempreg,$tempreg,$at | |
5006 | ||
5007 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
5008 | local symbols, even though it introduces an additional | |
5009 | instruction. */ | |
5010 | ||
f5040a92 AO |
5011 | if (offset_expr.X_add_number) |
5012 | { | |
4d7206a2 | 5013 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5014 | offset_expr.X_add_number = 0; |
5015 | ||
4d7206a2 | 5016 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5017 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5018 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5019 | |
5020 | if (expr1.X_add_number >= -0x8000 | |
5021 | && expr1.X_add_number < 0x8000) | |
5022 | { | |
67c0d1eb RS |
5023 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
5024 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 5025 | } |
ecd13cd3 | 5026 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 AO |
5027 | { |
5028 | int dreg; | |
5029 | ||
5030 | /* If we are going to add in a base register, and the | |
5031 | target register and the base register are the same, | |
5032 | then we are using AT as a temporary register. Since | |
5033 | we want to load the constant into AT, we add our | |
5034 | current AT (from the global offset table) and the | |
5035 | register into the register now, and pretend we were | |
5036 | not using a base register. */ | |
5037 | if (breg != treg) | |
5038 | dreg = tempreg; | |
5039 | else | |
5040 | { | |
5041 | assert (tempreg == AT); | |
67c0d1eb RS |
5042 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
5043 | treg, AT, breg); | |
f5040a92 | 5044 | dreg = treg; |
67c0d1eb | 5045 | add_breg_early = 1; |
f5040a92 AO |
5046 | } |
5047 | ||
f6a22291 | 5048 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5049 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5050 | dreg, dreg, AT); |
f5040a92 | 5051 | |
f5040a92 AO |
5052 | used_at = 1; |
5053 | } | |
5054 | else | |
5055 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5056 | ||
4d7206a2 | 5057 | relax_switch (); |
f5040a92 AO |
5058 | offset_expr.X_add_number = expr1.X_add_number; |
5059 | ||
67c0d1eb RS |
5060 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5061 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
5062 | if (add_breg_early) | |
f5040a92 | 5063 | { |
67c0d1eb | 5064 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
f899b4b8 | 5065 | treg, tempreg, breg); |
f5040a92 AO |
5066 | breg = 0; |
5067 | tempreg = treg; | |
5068 | } | |
4d7206a2 | 5069 | relax_end (); |
f5040a92 | 5070 | } |
4d7206a2 | 5071 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 5072 | { |
4d7206a2 | 5073 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5074 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5075 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 5076 | relax_switch (); |
67c0d1eb RS |
5077 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5078 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 5079 | relax_end (); |
f5040a92 | 5080 | } |
4d7206a2 | 5081 | else |
f5040a92 | 5082 | { |
67c0d1eb RS |
5083 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5084 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
5085 | } |
5086 | } | |
5087 | else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI) | |
252b5132 | 5088 | { |
67c0d1eb | 5089 | int gpdelay; |
9117d219 NC |
5090 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5091 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 5092 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
5093 | |
5094 | /* This is the large GOT case. If this is a reference to an | |
5095 | external symbol, and there is no constant, we want | |
5096 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5097 | addu $tempreg,$tempreg,$gp | |
5098 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5099 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
5100 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5101 | addu $tempreg,$tempreg,$gp | |
5102 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
5103 | For a local symbol, we want |
5104 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5105 | nop | |
5106 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5107 | ||
5108 | If we have a small constant, and this is a reference to | |
5109 | an external symbol, we want | |
5110 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5111 | addu $tempreg,$tempreg,$gp | |
5112 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5113 | nop | |
5114 | addiu $tempreg,$tempreg,<constant> | |
5115 | For a local symbol, we want | |
5116 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5117 | nop | |
5118 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
5119 | ||
5120 | If we have a large constant, and this is a reference to | |
5121 | an external symbol, we want | |
5122 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5123 | addu $tempreg,$tempreg,$gp | |
5124 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5125 | lui $at,<hiconstant> | |
5126 | addiu $at,$at,<loconstant> | |
5127 | addu $tempreg,$tempreg,$at | |
5128 | For a local symbol, we want | |
5129 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5130 | lui $at,<hiconstant> | |
5131 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
5132 | addu $tempreg,$tempreg,$at | |
f5040a92 | 5133 | */ |
438c16b8 | 5134 | |
252b5132 RH |
5135 | expr1.X_add_number = offset_expr.X_add_number; |
5136 | offset_expr.X_add_number = 0; | |
4d7206a2 | 5137 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 5138 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
5139 | if (expr1.X_add_number == 0 && breg == 0 |
5140 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
5141 | { |
5142 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5143 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5144 | } | |
67c0d1eb RS |
5145 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
5146 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5147 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 5148 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 5149 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
5150 | if (expr1.X_add_number == 0) |
5151 | { | |
67c0d1eb | 5152 | if (breg != 0) |
252b5132 RH |
5153 | { |
5154 | /* We're going to put in an addu instruction using | |
5155 | tempreg, so we may as well insert the nop right | |
5156 | now. */ | |
269137b2 | 5157 | load_delay_nop (); |
252b5132 | 5158 | } |
252b5132 RH |
5159 | } |
5160 | else if (expr1.X_add_number >= -0x8000 | |
5161 | && expr1.X_add_number < 0x8000) | |
5162 | { | |
269137b2 | 5163 | load_delay_nop (); |
67c0d1eb | 5164 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5165 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
5166 | } |
5167 | else | |
5168 | { | |
67c0d1eb | 5169 | int dreg; |
252b5132 RH |
5170 | |
5171 | /* If we are going to add in a base register, and the | |
5172 | target register and the base register are the same, | |
5173 | then we are using AT as a temporary register. Since | |
5174 | we want to load the constant into AT, we add our | |
5175 | current AT (from the global offset table) and the | |
5176 | register into the register now, and pretend we were | |
5177 | not using a base register. */ | |
5178 | if (breg != treg) | |
67c0d1eb | 5179 | dreg = tempreg; |
252b5132 RH |
5180 | else |
5181 | { | |
5182 | assert (tempreg == AT); | |
269137b2 | 5183 | load_delay_nop (); |
67c0d1eb | 5184 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5185 | treg, AT, breg); |
252b5132 | 5186 | dreg = treg; |
252b5132 RH |
5187 | } |
5188 | ||
f6a22291 | 5189 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5190 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 5191 | |
252b5132 RH |
5192 | used_at = 1; |
5193 | } | |
4d7206a2 RS |
5194 | offset_expr.X_add_number = |
5195 | ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000; | |
5196 | relax_switch (); | |
252b5132 | 5197 | |
67c0d1eb | 5198 | if (gpdelay) |
252b5132 RH |
5199 | { |
5200 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 5201 | the first instruction on the main stream does not. */ |
67c0d1eb | 5202 | macro_build (NULL, "nop", ""); |
252b5132 | 5203 | } |
ed6fb7bd | 5204 | |
67c0d1eb RS |
5205 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5206 | local_reloc_type, mips_gp_register); | |
f5040a92 | 5207 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
5208 | && expr1.X_add_number < 0x8000) |
5209 | { | |
269137b2 | 5210 | load_delay_nop (); |
67c0d1eb RS |
5211 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5212 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 5213 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
5214 | register, the external symbol case ended with a load, |
5215 | so if the symbol turns out to not be external, and | |
5216 | the next instruction uses tempreg, an unnecessary nop | |
5217 | will be inserted. */ | |
252b5132 RH |
5218 | } |
5219 | else | |
5220 | { | |
5221 | if (breg == treg) | |
5222 | { | |
5223 | /* We must add in the base register now, as in the | |
f5040a92 | 5224 | external symbol case. */ |
252b5132 | 5225 | assert (tempreg == AT); |
269137b2 | 5226 | load_delay_nop (); |
67c0d1eb | 5227 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5228 | treg, AT, breg); |
252b5132 RH |
5229 | tempreg = treg; |
5230 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 5231 | it in in both cases. */ |
252b5132 RH |
5232 | breg = 0; |
5233 | } | |
5234 | ||
67c0d1eb RS |
5235 | macro_build_lui (&expr1, AT); |
5236 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 5237 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 5238 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5239 | tempreg, tempreg, AT); |
8fc2e39e | 5240 | used_at = 1; |
252b5132 | 5241 | } |
4d7206a2 | 5242 | relax_end (); |
252b5132 | 5243 | } |
f5040a92 AO |
5244 | else if (mips_pic == SVR4_PIC && HAVE_NEWABI) |
5245 | { | |
f5040a92 AO |
5246 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
5247 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 5248 | int add_breg_early = 0; |
f5040a92 AO |
5249 | |
5250 | /* This is the large GOT case. If this is a reference to an | |
5251 | external symbol, and there is no constant, we want | |
5252 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5253 | add $tempreg,$tempreg,$gp | |
5254 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 5255 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
5256 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
5257 | add $tempreg,$tempreg,$gp | |
5258 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
5259 | ||
5260 | If we have a small constant, and this is a reference to | |
5261 | an external symbol, we want | |
5262 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5263 | add $tempreg,$tempreg,$gp | |
5264 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5265 | addi $tempreg,$tempreg,<constant> | |
5266 | ||
5267 | If we have a large constant, and this is a reference to | |
5268 | an external symbol, we want | |
5269 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5270 | addu $tempreg,$tempreg,$gp | |
5271 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5272 | lui $at,<hiconstant> | |
5273 | addi $at,$at,<loconstant> | |
5274 | add $tempreg,$tempreg,$at | |
5275 | ||
5276 | If we have NewABI, and we know it's a local symbol, we want | |
5277 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
5278 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
5279 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
5280 | ||
4d7206a2 | 5281 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 5282 | |
4d7206a2 | 5283 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
5284 | offset_expr.X_add_number = 0; |
5285 | ||
1abe91b1 MR |
5286 | if (expr1.X_add_number == 0 && breg == 0 |
5287 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
5288 | { |
5289 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
5290 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
5291 | } | |
67c0d1eb RS |
5292 | macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); |
5293 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5294 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
5295 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5296 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
5297 | |
5298 | if (expr1.X_add_number == 0) | |
4d7206a2 | 5299 | ; |
f5040a92 AO |
5300 | else if (expr1.X_add_number >= -0x8000 |
5301 | && expr1.X_add_number < 0x8000) | |
5302 | { | |
67c0d1eb | 5303 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 5304 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 5305 | } |
ecd13cd3 | 5306 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 AO |
5307 | { |
5308 | int dreg; | |
5309 | ||
5310 | /* If we are going to add in a base register, and the | |
5311 | target register and the base register are the same, | |
5312 | then we are using AT as a temporary register. Since | |
5313 | we want to load the constant into AT, we add our | |
5314 | current AT (from the global offset table) and the | |
5315 | register into the register now, and pretend we were | |
5316 | not using a base register. */ | |
5317 | if (breg != treg) | |
5318 | dreg = tempreg; | |
5319 | else | |
5320 | { | |
5321 | assert (tempreg == AT); | |
67c0d1eb | 5322 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5323 | treg, AT, breg); |
f5040a92 | 5324 | dreg = treg; |
67c0d1eb | 5325 | add_breg_early = 1; |
f5040a92 AO |
5326 | } |
5327 | ||
f6a22291 | 5328 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 5329 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 5330 | |
f5040a92 AO |
5331 | used_at = 1; |
5332 | } | |
5333 | else | |
5334 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
5335 | ||
4d7206a2 | 5336 | relax_switch (); |
f5040a92 | 5337 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
5338 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5339 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
5340 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
5341 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
5342 | if (add_breg_early) | |
f5040a92 | 5343 | { |
67c0d1eb | 5344 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5345 | treg, tempreg, breg); |
f5040a92 AO |
5346 | breg = 0; |
5347 | tempreg = treg; | |
5348 | } | |
4d7206a2 | 5349 | relax_end (); |
f5040a92 | 5350 | } |
252b5132 RH |
5351 | else |
5352 | abort (); | |
5353 | ||
5354 | if (breg != 0) | |
aed1a261 | 5355 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg); |
252b5132 RH |
5356 | break; |
5357 | ||
5358 | case M_J_A: | |
5359 | /* The j instruction may not be used in PIC code, since it | |
5360 | requires an absolute address. We convert it to a b | |
5361 | instruction. */ | |
5362 | if (mips_pic == NO_PIC) | |
67c0d1eb | 5363 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 5364 | else |
67c0d1eb | 5365 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 5366 | break; |
252b5132 RH |
5367 | |
5368 | /* The jal instructions must be handled as macros because when | |
5369 | generating PIC code they expand to multi-instruction | |
5370 | sequences. Normally they are simple instructions. */ | |
5371 | case M_JAL_1: | |
5372 | dreg = RA; | |
5373 | /* Fall through. */ | |
5374 | case M_JAL_2: | |
3e722fb5 | 5375 | if (mips_pic == NO_PIC) |
67c0d1eb | 5376 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
252b5132 RH |
5377 | else if (mips_pic == SVR4_PIC) |
5378 | { | |
5379 | if (sreg != PIC_CALL_REG) | |
5380 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 5381 | |
67c0d1eb | 5382 | macro_build (NULL, "jalr", "d,s", dreg, sreg); |
6478892d | 5383 | if (! HAVE_NEWABI) |
252b5132 | 5384 | { |
6478892d TS |
5385 | if (mips_cprestore_offset < 0) |
5386 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5387 | else | |
5388 | { | |
7a621144 DJ |
5389 | if (! mips_frame_reg_valid) |
5390 | { | |
5391 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5392 | /* Quiet this warning. */ | |
5393 | mips_frame_reg_valid = 1; | |
5394 | } | |
5395 | if (! mips_cprestore_valid) | |
5396 | { | |
5397 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5398 | /* Quiet this warning. */ | |
5399 | mips_cprestore_valid = 1; | |
5400 | } | |
6478892d | 5401 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 5402 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 5403 | mips_gp_register, |
256ab948 TS |
5404 | mips_frame_reg, |
5405 | HAVE_64BIT_ADDRESSES); | |
6478892d | 5406 | } |
252b5132 RH |
5407 | } |
5408 | } | |
5409 | else | |
5410 | abort (); | |
5411 | ||
8fc2e39e | 5412 | break; |
252b5132 RH |
5413 | |
5414 | case M_JAL_A: | |
5415 | if (mips_pic == NO_PIC) | |
67c0d1eb | 5416 | macro_build (&offset_expr, "jal", "a"); |
252b5132 RH |
5417 | else if (mips_pic == SVR4_PIC) |
5418 | { | |
5419 | /* If this is a reference to an external symbol, and we are | |
5420 | using a small GOT, we want | |
5421 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
5422 | nop | |
f9419b05 | 5423 | jalr $ra,$25 |
252b5132 RH |
5424 | nop |
5425 | lw $gp,cprestore($sp) | |
5426 | The cprestore value is set using the .cprestore | |
5427 | pseudo-op. If we are using a big GOT, we want | |
5428 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
5429 | addu $25,$25,$gp | |
5430 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
5431 | nop | |
f9419b05 | 5432 | jalr $ra,$25 |
252b5132 RH |
5433 | nop |
5434 | lw $gp,cprestore($sp) | |
5435 | If the symbol is not external, we want | |
5436 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5437 | nop | |
5438 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 5439 | jalr $ra,$25 |
252b5132 | 5440 | nop |
438c16b8 | 5441 | lw $gp,cprestore($sp) |
f5040a92 AO |
5442 | |
5443 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
5444 | sequences above, minus nops, unless the symbol is local, | |
5445 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
5446 | GOT_DISP. */ | |
438c16b8 | 5447 | if (HAVE_NEWABI) |
252b5132 | 5448 | { |
f5040a92 AO |
5449 | if (! mips_big_got) |
5450 | { | |
4d7206a2 | 5451 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5452 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5453 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 5454 | mips_gp_register); |
4d7206a2 | 5455 | relax_switch (); |
67c0d1eb RS |
5456 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5457 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
5458 | mips_gp_register); |
5459 | relax_end (); | |
f5040a92 AO |
5460 | } |
5461 | else | |
5462 | { | |
4d7206a2 | 5463 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5464 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, |
5465 | BFD_RELOC_MIPS_CALL_HI16); | |
5466 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
5467 | PIC_CALL_REG, mips_gp_register); | |
5468 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
5469 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
5470 | PIC_CALL_REG); | |
4d7206a2 | 5471 | relax_switch (); |
67c0d1eb RS |
5472 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5473 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
5474 | mips_gp_register); | |
5475 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
5476 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 5477 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 5478 | relax_end (); |
f5040a92 | 5479 | } |
684022ea | 5480 | |
67c0d1eb | 5481 | macro_build_jalr (&offset_expr); |
252b5132 RH |
5482 | } |
5483 | else | |
5484 | { | |
4d7206a2 | 5485 | relax_start (offset_expr.X_add_symbol); |
438c16b8 TS |
5486 | if (! mips_big_got) |
5487 | { | |
67c0d1eb RS |
5488 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5489 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 5490 | mips_gp_register); |
269137b2 | 5491 | load_delay_nop (); |
4d7206a2 | 5492 | relax_switch (); |
438c16b8 | 5493 | } |
252b5132 | 5494 | else |
252b5132 | 5495 | { |
67c0d1eb RS |
5496 | int gpdelay; |
5497 | ||
5498 | gpdelay = reg_needs_delay (mips_gp_register); | |
5499 | macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, | |
5500 | BFD_RELOC_MIPS_CALL_HI16); | |
5501 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
5502 | PIC_CALL_REG, mips_gp_register); | |
5503 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
5504 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
5505 | PIC_CALL_REG); | |
269137b2 | 5506 | load_delay_nop (); |
4d7206a2 | 5507 | relax_switch (); |
67c0d1eb RS |
5508 | if (gpdelay) |
5509 | macro_build (NULL, "nop", ""); | |
252b5132 | 5510 | } |
67c0d1eb RS |
5511 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
5512 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 5513 | mips_gp_register); |
269137b2 | 5514 | load_delay_nop (); |
67c0d1eb RS |
5515 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
5516 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 5517 | relax_end (); |
67c0d1eb | 5518 | macro_build_jalr (&offset_expr); |
438c16b8 | 5519 | |
6478892d TS |
5520 | if (mips_cprestore_offset < 0) |
5521 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5522 | else | |
5523 | { | |
7a621144 DJ |
5524 | if (! mips_frame_reg_valid) |
5525 | { | |
5526 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
5527 | /* Quiet this warning. */ | |
5528 | mips_frame_reg_valid = 1; | |
5529 | } | |
5530 | if (! mips_cprestore_valid) | |
5531 | { | |
5532 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
5533 | /* Quiet this warning. */ | |
5534 | mips_cprestore_valid = 1; | |
5535 | } | |
6478892d | 5536 | if (mips_opts.noreorder) |
67c0d1eb | 5537 | macro_build (NULL, "nop", ""); |
6478892d | 5538 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 5539 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 5540 | mips_gp_register, |
256ab948 TS |
5541 | mips_frame_reg, |
5542 | HAVE_64BIT_ADDRESSES); | |
6478892d | 5543 | } |
252b5132 RH |
5544 | } |
5545 | } | |
252b5132 RH |
5546 | else |
5547 | abort (); | |
5548 | ||
8fc2e39e | 5549 | break; |
252b5132 RH |
5550 | |
5551 | case M_LB_AB: | |
5552 | s = "lb"; | |
5553 | goto ld; | |
5554 | case M_LBU_AB: | |
5555 | s = "lbu"; | |
5556 | goto ld; | |
5557 | case M_LH_AB: | |
5558 | s = "lh"; | |
5559 | goto ld; | |
5560 | case M_LHU_AB: | |
5561 | s = "lhu"; | |
5562 | goto ld; | |
5563 | case M_LW_AB: | |
5564 | s = "lw"; | |
5565 | goto ld; | |
5566 | case M_LWC0_AB: | |
5567 | s = "lwc0"; | |
bdaaa2e1 | 5568 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5569 | coproc = 1; |
5570 | goto ld; | |
5571 | case M_LWC1_AB: | |
5572 | s = "lwc1"; | |
bdaaa2e1 | 5573 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5574 | coproc = 1; |
5575 | goto ld; | |
5576 | case M_LWC2_AB: | |
5577 | s = "lwc2"; | |
bdaaa2e1 | 5578 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5579 | coproc = 1; |
5580 | goto ld; | |
5581 | case M_LWC3_AB: | |
5582 | s = "lwc3"; | |
bdaaa2e1 | 5583 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5584 | coproc = 1; |
5585 | goto ld; | |
5586 | case M_LWL_AB: | |
5587 | s = "lwl"; | |
5588 | lr = 1; | |
5589 | goto ld; | |
5590 | case M_LWR_AB: | |
5591 | s = "lwr"; | |
5592 | lr = 1; | |
5593 | goto ld; | |
5594 | case M_LDC1_AB: | |
fef14a42 | 5595 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
5596 | { |
5597 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 5598 | break; |
252b5132 RH |
5599 | } |
5600 | s = "ldc1"; | |
bdaaa2e1 | 5601 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5602 | coproc = 1; |
5603 | goto ld; | |
5604 | case M_LDC2_AB: | |
5605 | s = "ldc2"; | |
bdaaa2e1 | 5606 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5607 | coproc = 1; |
5608 | goto ld; | |
5609 | case M_LDC3_AB: | |
5610 | s = "ldc3"; | |
bdaaa2e1 | 5611 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5612 | coproc = 1; |
5613 | goto ld; | |
5614 | case M_LDL_AB: | |
5615 | s = "ldl"; | |
5616 | lr = 1; | |
5617 | goto ld; | |
5618 | case M_LDR_AB: | |
5619 | s = "ldr"; | |
5620 | lr = 1; | |
5621 | goto ld; | |
5622 | case M_LL_AB: | |
5623 | s = "ll"; | |
5624 | goto ld; | |
5625 | case M_LLD_AB: | |
5626 | s = "lld"; | |
5627 | goto ld; | |
5628 | case M_LWU_AB: | |
5629 | s = "lwu"; | |
5630 | ld: | |
8fc2e39e | 5631 | if (breg == treg || coproc || lr) |
252b5132 RH |
5632 | { |
5633 | tempreg = AT; | |
5634 | used_at = 1; | |
5635 | } | |
5636 | else | |
5637 | { | |
5638 | tempreg = treg; | |
252b5132 RH |
5639 | } |
5640 | goto ld_st; | |
5641 | case M_SB_AB: | |
5642 | s = "sb"; | |
5643 | goto st; | |
5644 | case M_SH_AB: | |
5645 | s = "sh"; | |
5646 | goto st; | |
5647 | case M_SW_AB: | |
5648 | s = "sw"; | |
5649 | goto st; | |
5650 | case M_SWC0_AB: | |
5651 | s = "swc0"; | |
bdaaa2e1 | 5652 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5653 | coproc = 1; |
5654 | goto st; | |
5655 | case M_SWC1_AB: | |
5656 | s = "swc1"; | |
bdaaa2e1 | 5657 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5658 | coproc = 1; |
5659 | goto st; | |
5660 | case M_SWC2_AB: | |
5661 | s = "swc2"; | |
bdaaa2e1 | 5662 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5663 | coproc = 1; |
5664 | goto st; | |
5665 | case M_SWC3_AB: | |
5666 | s = "swc3"; | |
bdaaa2e1 | 5667 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5668 | coproc = 1; |
5669 | goto st; | |
5670 | case M_SWL_AB: | |
5671 | s = "swl"; | |
5672 | goto st; | |
5673 | case M_SWR_AB: | |
5674 | s = "swr"; | |
5675 | goto st; | |
5676 | case M_SC_AB: | |
5677 | s = "sc"; | |
5678 | goto st; | |
5679 | case M_SCD_AB: | |
5680 | s = "scd"; | |
5681 | goto st; | |
5682 | case M_SDC1_AB: | |
fef14a42 | 5683 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
5684 | { |
5685 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 5686 | break; |
252b5132 RH |
5687 | } |
5688 | s = "sdc1"; | |
5689 | coproc = 1; | |
bdaaa2e1 | 5690 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5691 | goto st; |
5692 | case M_SDC2_AB: | |
5693 | s = "sdc2"; | |
bdaaa2e1 | 5694 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5695 | coproc = 1; |
5696 | goto st; | |
5697 | case M_SDC3_AB: | |
5698 | s = "sdc3"; | |
bdaaa2e1 | 5699 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5700 | coproc = 1; |
5701 | goto st; | |
5702 | case M_SDL_AB: | |
5703 | s = "sdl"; | |
5704 | goto st; | |
5705 | case M_SDR_AB: | |
5706 | s = "sdr"; | |
5707 | st: | |
8fc2e39e TS |
5708 | tempreg = AT; |
5709 | used_at = 1; | |
252b5132 | 5710 | ld_st: |
bdaaa2e1 | 5711 | /* Itbl support may require additional care here. */ |
252b5132 RH |
5712 | if (mask == M_LWC1_AB |
5713 | || mask == M_SWC1_AB | |
5714 | || mask == M_LDC1_AB | |
5715 | || mask == M_SDC1_AB | |
5716 | || mask == M_L_DAB | |
5717 | || mask == M_S_DAB) | |
5718 | fmt = "T,o(b)"; | |
5719 | else if (coproc) | |
5720 | fmt = "E,o(b)"; | |
5721 | else | |
5722 | fmt = "t,o(b)"; | |
5723 | ||
5724 | if (offset_expr.X_op != O_constant | |
5725 | && offset_expr.X_op != O_symbol) | |
5726 | { | |
5727 | as_bad (_("expression too complex")); | |
5728 | offset_expr.X_op = O_constant; | |
5729 | } | |
5730 | ||
5731 | /* A constant expression in PIC code can be handled just as it | |
5732 | is in non PIC code. */ | |
aed1a261 RS |
5733 | if (offset_expr.X_op == O_constant) |
5734 | { | |
5735 | if (HAVE_32BIT_ADDRESSES | |
5736 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
5737 | as_bad (_("constant too large")); | |
5738 | ||
5739 | expr1.X_add_number = ((offset_expr.X_add_number + 0x8000) | |
5740 | & ~(bfd_vma) 0xffff); | |
5741 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); | |
5742 | if (breg != 0) | |
5743 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
5744 | tempreg, tempreg, breg); | |
5745 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, tempreg); | |
5746 | } | |
5747 | else if (mips_pic == NO_PIC) | |
252b5132 RH |
5748 | { |
5749 | /* If this is a reference to a GP relative symbol, and there | |
5750 | is no base register, we want | |
cdf6fd85 | 5751 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
5752 | Otherwise, if there is no base register, we want |
5753 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5754 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5755 | If we have a constant, we need two instructions anyhow, | |
5756 | so we always use the latter form. | |
5757 | ||
5758 | If we have a base register, and this is a reference to a | |
5759 | GP relative symbol, we want | |
5760 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 5761 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
5762 | Otherwise we want |
5763 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5764 | addu $tempreg,$tempreg,$breg | |
5765 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 5766 | With a constant we always use the latter case. |
76b3015f | 5767 | |
d6bc6245 TS |
5768 | With 64bit address space and no base register and $at usable, |
5769 | we want | |
5770 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5771 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5772 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5773 | dsll32 $tempreg,0 | |
5774 | daddu $tempreg,$at | |
5775 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5776 | If we have a base register, we want | |
5777 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5778 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5779 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5780 | daddu $at,$breg | |
5781 | dsll32 $tempreg,0 | |
5782 | daddu $tempreg,$at | |
5783 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5784 | ||
5785 | Without $at we can't generate the optimal path for superscalar | |
5786 | processors here since this would require two temporary registers. | |
5787 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5788 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5789 | dsll $tempreg,16 | |
5790 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5791 | dsll $tempreg,16 | |
5792 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
5793 | If we have a base register, we want | |
5794 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
5795 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
5796 | dsll $tempreg,16 | |
5797 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
5798 | dsll $tempreg,16 | |
5799 | daddu $tempreg,$tempreg,$breg | |
5800 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 | 5801 | |
6caf9ef4 | 5802 | For GP relative symbols in 64bit address space we can use |
aed1a261 RS |
5803 | the same sequence as in 32bit address space. */ |
5804 | if (HAVE_64BIT_SYMBOLS) | |
d6bc6245 | 5805 | { |
aed1a261 | 5806 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 TS |
5807 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
5808 | { | |
5809 | relax_start (offset_expr.X_add_symbol); | |
5810 | if (breg == 0) | |
5811 | { | |
5812 | macro_build (&offset_expr, s, fmt, treg, | |
5813 | BFD_RELOC_GPREL16, mips_gp_register); | |
5814 | } | |
5815 | else | |
5816 | { | |
5817 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
5818 | tempreg, breg, mips_gp_register); | |
5819 | macro_build (&offset_expr, s, fmt, treg, | |
5820 | BFD_RELOC_GPREL16, tempreg); | |
5821 | } | |
5822 | relax_switch (); | |
5823 | } | |
d6bc6245 | 5824 | |
b8285c27 | 5825 | if (used_at == 0 && !mips_opts.noat) |
d6bc6245 | 5826 | { |
67c0d1eb RS |
5827 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
5828 | BFD_RELOC_MIPS_HIGHEST); | |
5829 | macro_build (&offset_expr, "lui", "t,u", AT, | |
5830 | BFD_RELOC_HI16_S); | |
5831 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
5832 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 5833 | if (breg != 0) |
67c0d1eb RS |
5834 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
5835 | macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); | |
5836 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); | |
5837 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, | |
5838 | tempreg); | |
d6bc6245 TS |
5839 | used_at = 1; |
5840 | } | |
5841 | else | |
5842 | { | |
67c0d1eb RS |
5843 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
5844 | BFD_RELOC_MIPS_HIGHEST); | |
5845 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
5846 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
5847 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
5848 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
5849 | tempreg, BFD_RELOC_HI16_S); | |
5850 | macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); | |
d6bc6245 | 5851 | if (breg != 0) |
67c0d1eb | 5852 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 5853 | tempreg, tempreg, breg); |
67c0d1eb | 5854 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 5855 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 5856 | } |
6caf9ef4 TS |
5857 | |
5858 | if (mips_relax.sequence) | |
5859 | relax_end (); | |
8fc2e39e | 5860 | break; |
d6bc6245 | 5861 | } |
256ab948 | 5862 | |
252b5132 RH |
5863 | if (breg == 0) |
5864 | { | |
67c0d1eb | 5865 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 5866 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 5867 | { |
4d7206a2 | 5868 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
5869 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, |
5870 | mips_gp_register); | |
4d7206a2 | 5871 | relax_switch (); |
252b5132 | 5872 | } |
67c0d1eb RS |
5873 | macro_build_lui (&offset_expr, tempreg); |
5874 | macro_build (&offset_expr, s, fmt, treg, | |
17a2f251 | 5875 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
5876 | if (mips_relax.sequence) |
5877 | relax_end (); | |
252b5132 RH |
5878 | } |
5879 | else | |
5880 | { | |
67c0d1eb | 5881 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 5882 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 5883 | { |
4d7206a2 | 5884 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 5885 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5886 | tempreg, breg, mips_gp_register); |
67c0d1eb | 5887 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 5888 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 5889 | relax_switch (); |
252b5132 | 5890 | } |
67c0d1eb RS |
5891 | macro_build_lui (&offset_expr, tempreg); |
5892 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 5893 | tempreg, tempreg, breg); |
67c0d1eb | 5894 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 5895 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
5896 | if (mips_relax.sequence) |
5897 | relax_end (); | |
252b5132 RH |
5898 | } |
5899 | } | |
5900 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
5901 | { | |
ed6fb7bd | 5902 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 5903 | |
252b5132 RH |
5904 | /* If this is a reference to an external symbol, we want |
5905 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5906 | nop | |
5907 | <op> $treg,0($tempreg) | |
5908 | Otherwise we want | |
5909 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5910 | nop | |
5911 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5912 | <op> $treg,0($tempreg) | |
f5040a92 AO |
5913 | |
5914 | For NewABI, we want | |
5915 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
5916 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
5917 | ||
252b5132 RH |
5918 | If there is a base register, we add it to $tempreg before |
5919 | the <op>. If there is a constant, we stick it in the | |
5920 | <op> instruction. We don't handle constants larger than | |
5921 | 16 bits, because we have no way to load the upper 16 bits | |
5922 | (actually, we could handle them for the subset of cases | |
5923 | in which we are not using $at). */ | |
5924 | assert (offset_expr.X_op == O_symbol); | |
f5040a92 AO |
5925 | if (HAVE_NEWABI) |
5926 | { | |
67c0d1eb RS |
5927 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5928 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 5929 | if (breg != 0) |
67c0d1eb | 5930 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5931 | tempreg, tempreg, breg); |
67c0d1eb | 5932 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 5933 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
5934 | break; |
5935 | } | |
252b5132 RH |
5936 | expr1.X_add_number = offset_expr.X_add_number; |
5937 | offset_expr.X_add_number = 0; | |
5938 | if (expr1.X_add_number < -0x8000 | |
5939 | || expr1.X_add_number >= 0x8000) | |
5940 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
5941 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
5942 | lw_reloc_type, mips_gp_register); | |
269137b2 | 5943 | load_delay_nop (); |
4d7206a2 RS |
5944 | relax_start (offset_expr.X_add_symbol); |
5945 | relax_switch (); | |
67c0d1eb RS |
5946 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
5947 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 5948 | relax_end (); |
252b5132 | 5949 | if (breg != 0) |
67c0d1eb | 5950 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 5951 | tempreg, tempreg, breg); |
67c0d1eb | 5952 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 5953 | } |
f5040a92 | 5954 | else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI) |
252b5132 | 5955 | { |
67c0d1eb | 5956 | int gpdelay; |
252b5132 RH |
5957 | |
5958 | /* If this is a reference to an external symbol, we want | |
5959 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5960 | addu $tempreg,$tempreg,$gp | |
5961 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5962 | <op> $treg,0($tempreg) | |
5963 | Otherwise we want | |
5964 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5965 | nop | |
5966 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5967 | <op> $treg,0($tempreg) | |
5968 | If there is a base register, we add it to $tempreg before | |
5969 | the <op>. If there is a constant, we stick it in the | |
5970 | <op> instruction. We don't handle constants larger than | |
5971 | 16 bits, because we have no way to load the upper 16 bits | |
5972 | (actually, we could handle them for the subset of cases | |
f5040a92 | 5973 | in which we are not using $at). */ |
252b5132 RH |
5974 | assert (offset_expr.X_op == O_symbol); |
5975 | expr1.X_add_number = offset_expr.X_add_number; | |
5976 | offset_expr.X_add_number = 0; | |
5977 | if (expr1.X_add_number < -0x8000 | |
5978 | || expr1.X_add_number >= 0x8000) | |
5979 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 5980 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 5981 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 5982 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 5983 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
5984 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
5985 | mips_gp_register); | |
5986 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
5987 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 5988 | relax_switch (); |
67c0d1eb RS |
5989 | if (gpdelay) |
5990 | macro_build (NULL, "nop", ""); | |
5991 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
5992 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 5993 | load_delay_nop (); |
67c0d1eb RS |
5994 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
5995 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
5996 | relax_end (); |
5997 | ||
252b5132 | 5998 | if (breg != 0) |
67c0d1eb | 5999 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6000 | tempreg, tempreg, breg); |
67c0d1eb | 6001 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 6002 | } |
f5040a92 AO |
6003 | else if (mips_pic == SVR4_PIC && HAVE_NEWABI) |
6004 | { | |
f5040a92 AO |
6005 | /* If this is a reference to an external symbol, we want |
6006 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6007 | add $tempreg,$tempreg,$gp | |
6008 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
6009 | <op> $treg,<ofst>($tempreg) | |
6010 | Otherwise, for local symbols, we want: | |
6011 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
6012 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
6013 | assert (offset_expr.X_op == O_symbol); | |
4d7206a2 | 6014 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
6015 | offset_expr.X_add_number = 0; |
6016 | if (expr1.X_add_number < -0x8000 | |
6017 | || expr1.X_add_number >= 0x8000) | |
6018 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 6019 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 6020 | macro_build (&offset_expr, "lui", "t,u", tempreg, |
17a2f251 | 6021 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6022 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
6023 | mips_gp_register); | |
6024 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
6025 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 6026 | if (breg != 0) |
67c0d1eb | 6027 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6028 | tempreg, tempreg, breg); |
67c0d1eb | 6029 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
684022ea | 6030 | |
4d7206a2 | 6031 | relax_switch (); |
f5040a92 | 6032 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
6033 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
6034 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 6035 | if (breg != 0) |
67c0d1eb | 6036 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6037 | tempreg, tempreg, breg); |
67c0d1eb | 6038 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 6039 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 6040 | relax_end (); |
f5040a92 | 6041 | } |
252b5132 RH |
6042 | else |
6043 | abort (); | |
6044 | ||
252b5132 RH |
6045 | break; |
6046 | ||
6047 | case M_LI: | |
6048 | case M_LI_S: | |
67c0d1eb | 6049 | load_register (treg, &imm_expr, 0); |
8fc2e39e | 6050 | break; |
252b5132 RH |
6051 | |
6052 | case M_DLI: | |
67c0d1eb | 6053 | load_register (treg, &imm_expr, 1); |
8fc2e39e | 6054 | break; |
252b5132 RH |
6055 | |
6056 | case M_LI_SS: | |
6057 | if (imm_expr.X_op == O_constant) | |
6058 | { | |
8fc2e39e | 6059 | used_at = 1; |
67c0d1eb RS |
6060 | load_register (AT, &imm_expr, 0); |
6061 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6062 | break; |
6063 | } | |
6064 | else | |
6065 | { | |
6066 | assert (offset_expr.X_op == O_symbol | |
6067 | && strcmp (segment_name (S_GET_SEGMENT | |
6068 | (offset_expr.X_add_symbol)), | |
6069 | ".lit4") == 0 | |
6070 | && offset_expr.X_add_number == 0); | |
67c0d1eb | 6071 | macro_build (&offset_expr, "lwc1", "T,o(b)", treg, |
17a2f251 | 6072 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 6073 | break; |
252b5132 RH |
6074 | } |
6075 | ||
6076 | case M_LI_D: | |
ca4e0257 RS |
6077 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
6078 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
6079 | order 32 bits of the value and the low order 32 bits are either | |
6080 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
6081 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6082 | { | |
ca4e0257 | 6083 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 6084 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
6085 | else |
6086 | { | |
6087 | int hreg, lreg; | |
6088 | ||
6089 | if (target_big_endian) | |
6090 | { | |
6091 | hreg = treg; | |
6092 | lreg = treg + 1; | |
6093 | } | |
6094 | else | |
6095 | { | |
6096 | hreg = treg + 1; | |
6097 | lreg = treg; | |
6098 | } | |
6099 | ||
6100 | if (hreg <= 31) | |
67c0d1eb | 6101 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
6102 | if (lreg <= 31) |
6103 | { | |
6104 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 6105 | move_register (lreg, 0); |
252b5132 RH |
6106 | else |
6107 | { | |
6108 | assert (offset_expr.X_op == O_constant); | |
67c0d1eb | 6109 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
6110 | } |
6111 | } | |
6112 | } | |
8fc2e39e | 6113 | break; |
252b5132 RH |
6114 | } |
6115 | ||
6116 | /* We know that sym is in the .rdata section. First we get the | |
6117 | upper 16 bits of the address. */ | |
6118 | if (mips_pic == NO_PIC) | |
6119 | { | |
67c0d1eb | 6120 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 6121 | used_at = 1; |
252b5132 RH |
6122 | } |
6123 | else if (mips_pic == SVR4_PIC) | |
6124 | { | |
67c0d1eb RS |
6125 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6126 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 6127 | used_at = 1; |
252b5132 | 6128 | } |
252b5132 RH |
6129 | else |
6130 | abort (); | |
bdaaa2e1 | 6131 | |
252b5132 | 6132 | /* Now we load the register(s). */ |
ca4e0257 | 6133 | if (HAVE_64BIT_GPRS) |
8fc2e39e TS |
6134 | { |
6135 | used_at = 1; | |
6136 | macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
6137 | } | |
252b5132 RH |
6138 | else |
6139 | { | |
8fc2e39e | 6140 | used_at = 1; |
67c0d1eb | 6141 | macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
f9419b05 | 6142 | if (treg != RA) |
252b5132 RH |
6143 | { |
6144 | /* FIXME: How in the world do we deal with the possible | |
6145 | overflow here? */ | |
6146 | offset_expr.X_add_number += 4; | |
67c0d1eb | 6147 | macro_build (&offset_expr, "lw", "t,o(b)", |
17a2f251 | 6148 | treg + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
6149 | } |
6150 | } | |
252b5132 RH |
6151 | break; |
6152 | ||
6153 | case M_LI_DD: | |
ca4e0257 RS |
6154 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
6155 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
6156 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
6157 | the value and the low order 32 bits are either zero or in | |
6158 | OFFSET_EXPR. */ | |
252b5132 RH |
6159 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
6160 | { | |
8fc2e39e | 6161 | used_at = 1; |
67c0d1eb | 6162 | load_register (AT, &imm_expr, HAVE_64BIT_FPRS); |
ca4e0257 RS |
6163 | if (HAVE_64BIT_FPRS) |
6164 | { | |
6165 | assert (HAVE_64BIT_GPRS); | |
67c0d1eb | 6166 | macro_build (NULL, "dmtc1", "t,S", AT, treg); |
ca4e0257 | 6167 | } |
252b5132 RH |
6168 | else |
6169 | { | |
67c0d1eb | 6170 | macro_build (NULL, "mtc1", "t,G", AT, treg + 1); |
252b5132 | 6171 | if (offset_expr.X_op == O_absent) |
67c0d1eb | 6172 | macro_build (NULL, "mtc1", "t,G", 0, treg); |
252b5132 RH |
6173 | else |
6174 | { | |
6175 | assert (offset_expr.X_op == O_constant); | |
67c0d1eb RS |
6176 | load_register (AT, &offset_expr, 0); |
6177 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
6178 | } |
6179 | } | |
6180 | break; | |
6181 | } | |
6182 | ||
6183 | assert (offset_expr.X_op == O_symbol | |
6184 | && offset_expr.X_add_number == 0); | |
6185 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
6186 | if (strcmp (s, ".lit8") == 0) | |
6187 | { | |
e7af610e | 6188 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6189 | { |
67c0d1eb | 6190 | macro_build (&offset_expr, "ldc1", "T,o(b)", treg, |
17a2f251 | 6191 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 6192 | break; |
252b5132 | 6193 | } |
c9914766 | 6194 | breg = mips_gp_register; |
252b5132 RH |
6195 | r = BFD_RELOC_MIPS_LITERAL; |
6196 | goto dob; | |
6197 | } | |
6198 | else | |
6199 | { | |
6200 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); | |
8fc2e39e | 6201 | used_at = 1; |
252b5132 | 6202 | if (mips_pic == SVR4_PIC) |
67c0d1eb RS |
6203 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
6204 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
6205 | else |
6206 | { | |
6207 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 6208 | macro_build_lui (&offset_expr, AT); |
252b5132 | 6209 | } |
bdaaa2e1 | 6210 | |
e7af610e | 6211 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 | 6212 | { |
67c0d1eb RS |
6213 | macro_build (&offset_expr, "ldc1", "T,o(b)", |
6214 | treg, BFD_RELOC_LO16, AT); | |
252b5132 RH |
6215 | break; |
6216 | } | |
6217 | breg = AT; | |
6218 | r = BFD_RELOC_LO16; | |
6219 | goto dob; | |
6220 | } | |
6221 | ||
6222 | case M_L_DOB: | |
fef14a42 | 6223 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6224 | { |
6225 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6226 | break; |
252b5132 RH |
6227 | } |
6228 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6229 | to adjust when loading from memory. */ | |
6230 | r = BFD_RELOC_LO16; | |
6231 | dob: | |
e7af610e | 6232 | assert (mips_opts.isa == ISA_MIPS1); |
67c0d1eb | 6233 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 6234 | target_big_endian ? treg + 1 : treg, r, breg); |
252b5132 RH |
6235 | /* FIXME: A possible overflow which I don't know how to deal |
6236 | with. */ | |
6237 | offset_expr.X_add_number += 4; | |
67c0d1eb | 6238 | macro_build (&offset_expr, "lwc1", "T,o(b)", |
17a2f251 | 6239 | target_big_endian ? treg : treg + 1, r, breg); |
252b5132 RH |
6240 | break; |
6241 | ||
6242 | case M_L_DAB: | |
6243 | /* | |
6244 | * The MIPS assembler seems to check for X_add_number not | |
6245 | * being double aligned and generating: | |
6246 | * lui at,%hi(foo+1) | |
6247 | * addu at,at,v1 | |
6248 | * addiu at,at,%lo(foo+1) | |
6249 | * lwc1 f2,0(at) | |
6250 | * lwc1 f3,4(at) | |
6251 | * But, the resulting address is the same after relocation so why | |
6252 | * generate the extra instruction? | |
6253 | */ | |
fef14a42 | 6254 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6255 | { |
6256 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6257 | break; |
252b5132 | 6258 | } |
bdaaa2e1 | 6259 | /* Itbl support may require additional care here. */ |
252b5132 | 6260 | coproc = 1; |
e7af610e | 6261 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6262 | { |
6263 | s = "ldc1"; | |
6264 | goto ld; | |
6265 | } | |
6266 | ||
6267 | s = "lwc1"; | |
6268 | fmt = "T,o(b)"; | |
6269 | goto ldd_std; | |
6270 | ||
6271 | case M_S_DAB: | |
fef14a42 | 6272 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6273 | { |
6274 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6275 | break; |
252b5132 RH |
6276 | } |
6277 | ||
e7af610e | 6278 | if (mips_opts.isa != ISA_MIPS1) |
252b5132 RH |
6279 | { |
6280 | s = "sdc1"; | |
6281 | goto st; | |
6282 | } | |
6283 | ||
6284 | s = "swc1"; | |
6285 | fmt = "T,o(b)"; | |
bdaaa2e1 | 6286 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6287 | coproc = 1; |
6288 | goto ldd_std; | |
6289 | ||
6290 | case M_LD_AB: | |
ca4e0257 | 6291 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6292 | { |
6293 | s = "ld"; | |
6294 | goto ld; | |
6295 | } | |
6296 | ||
6297 | s = "lw"; | |
6298 | fmt = "t,o(b)"; | |
6299 | goto ldd_std; | |
6300 | ||
6301 | case M_SD_AB: | |
ca4e0257 | 6302 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
6303 | { |
6304 | s = "sd"; | |
6305 | goto st; | |
6306 | } | |
6307 | ||
6308 | s = "sw"; | |
6309 | fmt = "t,o(b)"; | |
6310 | ||
6311 | ldd_std: | |
6312 | if (offset_expr.X_op != O_symbol | |
6313 | && offset_expr.X_op != O_constant) | |
6314 | { | |
6315 | as_bad (_("expression too complex")); | |
6316 | offset_expr.X_op = O_constant; | |
6317 | } | |
6318 | ||
6319 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
6320 | to adjust when loading from memory. We set coproc if we must | |
6321 | load $fn+1 first. */ | |
bdaaa2e1 | 6322 | /* Itbl support may require additional care here. */ |
252b5132 RH |
6323 | if (! target_big_endian) |
6324 | coproc = 0; | |
6325 | ||
6326 | if (mips_pic == NO_PIC | |
6327 | || offset_expr.X_op == O_constant) | |
6328 | { | |
6329 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 TS |
6330 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
6331 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6332 | If we have a base register, we use this |
6333 | addu $at,$breg,$gp | |
cdf6fd85 TS |
6334 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
6335 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
6336 | If this is not a GP relative symbol, we want |
6337 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6338 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6339 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6340 | If there is a base register, we add it to $at after the | |
6341 | lui instruction. If there is a constant, we always use | |
6342 | the last case. */ | |
6caf9ef4 TS |
6343 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6344 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
252b5132 | 6345 | { |
4d7206a2 | 6346 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
6347 | if (breg == 0) |
6348 | { | |
c9914766 | 6349 | tempreg = mips_gp_register; |
252b5132 RH |
6350 | } |
6351 | else | |
6352 | { | |
67c0d1eb | 6353 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 6354 | AT, breg, mips_gp_register); |
252b5132 | 6355 | tempreg = AT; |
252b5132 RH |
6356 | used_at = 1; |
6357 | } | |
6358 | ||
beae10d5 | 6359 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6360 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6361 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6362 | offset_expr.X_add_number += 4; |
6363 | ||
6364 | /* Set mips_optimize to 2 to avoid inserting an | |
6365 | undesired nop. */ | |
6366 | hold_mips_optimize = mips_optimize; | |
6367 | mips_optimize = 2; | |
beae10d5 | 6368 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6369 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6370 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
6371 | mips_optimize = hold_mips_optimize; |
6372 | ||
4d7206a2 | 6373 | relax_switch (); |
252b5132 RH |
6374 | |
6375 | /* We just generated two relocs. When tc_gen_reloc | |
6376 | handles this case, it will skip the first reloc and | |
6377 | handle the second. The second reloc already has an | |
6378 | extra addend of 4, which we added above. We must | |
6379 | subtract it out, and then subtract another 4 to make | |
6380 | the first reloc come out right. The second reloc | |
6381 | will come out right because we are going to add 4 to | |
6382 | offset_expr when we build its instruction below. | |
6383 | ||
6384 | If we have a symbol, then we don't want to include | |
6385 | the offset, because it will wind up being included | |
6386 | when we generate the reloc. */ | |
6387 | ||
6388 | if (offset_expr.X_op == O_constant) | |
6389 | offset_expr.X_add_number -= 8; | |
6390 | else | |
6391 | { | |
6392 | offset_expr.X_add_number = -4; | |
6393 | offset_expr.X_op = O_constant; | |
6394 | } | |
6395 | } | |
8fc2e39e | 6396 | used_at = 1; |
67c0d1eb | 6397 | macro_build_lui (&offset_expr, AT); |
252b5132 | 6398 | if (breg != 0) |
67c0d1eb | 6399 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6400 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6401 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6402 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6403 | /* FIXME: How do we handle overflow here? */ |
6404 | offset_expr.X_add_number += 4; | |
beae10d5 | 6405 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6406 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6407 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
6408 | if (mips_relax.sequence) |
6409 | relax_end (); | |
bdaaa2e1 | 6410 | } |
252b5132 RH |
6411 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
6412 | { | |
252b5132 RH |
6413 | /* If this is a reference to an external symbol, we want |
6414 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6415 | nop | |
6416 | <op> $treg,0($at) | |
6417 | <op> $treg+1,4($at) | |
6418 | Otherwise we want | |
6419 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6420 | nop | |
6421 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6422 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6423 | If there is a base register we add it to $at before the | |
6424 | lwc1 instructions. If there is a constant we include it | |
6425 | in the lwc1 instructions. */ | |
6426 | used_at = 1; | |
6427 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
6428 | if (expr1.X_add_number < -0x8000 |
6429 | || expr1.X_add_number >= 0x8000 - 4) | |
6430 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6431 | load_got_offset (AT, &offset_expr); |
269137b2 | 6432 | load_delay_nop (); |
252b5132 | 6433 | if (breg != 0) |
67c0d1eb | 6434 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
6435 | |
6436 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6437 | nop. */ | |
6438 | hold_mips_optimize = mips_optimize; | |
6439 | mips_optimize = 2; | |
4d7206a2 | 6440 | |
beae10d5 | 6441 | /* Itbl support may require additional care here. */ |
4d7206a2 | 6442 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6443 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
6444 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6445 | expr1.X_add_number += 4; |
67c0d1eb RS |
6446 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
6447 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6448 | relax_switch (); |
67c0d1eb RS |
6449 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
6450 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6451 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
6452 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
6453 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6454 | relax_end (); |
252b5132 | 6455 | |
4d7206a2 | 6456 | mips_optimize = hold_mips_optimize; |
252b5132 RH |
6457 | } |
6458 | else if (mips_pic == SVR4_PIC) | |
6459 | { | |
67c0d1eb | 6460 | int gpdelay; |
252b5132 RH |
6461 | |
6462 | /* If this is a reference to an external symbol, we want | |
6463 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6464 | addu $at,$at,$gp | |
6465 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
6466 | nop | |
6467 | <op> $treg,0($at) | |
6468 | <op> $treg+1,4($at) | |
6469 | Otherwise we want | |
6470 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6471 | nop | |
6472 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
6473 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
6474 | If there is a base register we add it to $at before the | |
6475 | lwc1 instructions. If there is a constant we include it | |
6476 | in the lwc1 instructions. */ | |
6477 | used_at = 1; | |
6478 | expr1.X_add_number = offset_expr.X_add_number; | |
6479 | offset_expr.X_add_number = 0; | |
6480 | if (expr1.X_add_number < -0x8000 | |
6481 | || expr1.X_add_number >= 0x8000 - 4) | |
6482 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 6483 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 6484 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
6485 | macro_build (&offset_expr, "lui", "t,u", |
6486 | AT, BFD_RELOC_MIPS_GOT_HI16); | |
6487 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 6488 | AT, AT, mips_gp_register); |
67c0d1eb | 6489 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 6490 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 6491 | load_delay_nop (); |
252b5132 | 6492 | if (breg != 0) |
67c0d1eb | 6493 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6494 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6495 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 6496 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6497 | expr1.X_add_number += 4; |
6498 | ||
6499 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6500 | nop. */ | |
6501 | hold_mips_optimize = mips_optimize; | |
6502 | mips_optimize = 2; | |
beae10d5 | 6503 | /* Itbl support may require additional care here. */ |
67c0d1eb | 6504 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 6505 | BFD_RELOC_LO16, AT); |
252b5132 RH |
6506 | mips_optimize = hold_mips_optimize; |
6507 | expr1.X_add_number -= 4; | |
6508 | ||
4d7206a2 RS |
6509 | relax_switch (); |
6510 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
6511 | if (gpdelay) |
6512 | macro_build (NULL, "nop", ""); | |
6513 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
6514 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6515 | load_delay_nop (); |
252b5132 | 6516 | if (breg != 0) |
67c0d1eb | 6517 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 6518 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
6519 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
6520 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 6521 | offset_expr.X_add_number += 4; |
252b5132 RH |
6522 | |
6523 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
6524 | nop. */ | |
6525 | hold_mips_optimize = mips_optimize; | |
6526 | mips_optimize = 2; | |
beae10d5 | 6527 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
6528 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
6529 | BFD_RELOC_LO16, AT); | |
252b5132 | 6530 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 6531 | relax_end (); |
252b5132 | 6532 | } |
252b5132 RH |
6533 | else |
6534 | abort (); | |
6535 | ||
252b5132 RH |
6536 | break; |
6537 | ||
6538 | case M_LD_OB: | |
6539 | s = "lw"; | |
6540 | goto sd_ob; | |
6541 | case M_SD_OB: | |
6542 | s = "sw"; | |
6543 | sd_ob: | |
ca4e0257 | 6544 | assert (HAVE_32BIT_ADDRESSES); |
67c0d1eb | 6545 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 | 6546 | offset_expr.X_add_number += 4; |
67c0d1eb | 6547 | macro_build (&offset_expr, s, "t,o(b)", treg + 1, BFD_RELOC_LO16, breg); |
8fc2e39e | 6548 | break; |
252b5132 RH |
6549 | |
6550 | /* New code added to support COPZ instructions. | |
6551 | This code builds table entries out of the macros in mip_opcodes. | |
6552 | R4000 uses interlocks to handle coproc delays. | |
6553 | Other chips (like the R3000) require nops to be inserted for delays. | |
6554 | ||
f72c8c98 | 6555 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
6556 | In order to fill delay slots for non-interlocked chips, |
6557 | we must have a way to specify delays based on the coprocessor. | |
6558 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
6559 | What are the side-effects of the cop instruction? | |
6560 | What cache support might we have and what are its effects? | |
6561 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 6562 | What registers are read/set/modified? |
252b5132 RH |
6563 | |
6564 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 6565 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
6566 | |
6567 | case M_COP0: | |
6568 | s = "c0"; | |
6569 | goto copz; | |
6570 | case M_COP1: | |
6571 | s = "c1"; | |
6572 | goto copz; | |
6573 | case M_COP2: | |
6574 | s = "c2"; | |
6575 | goto copz; | |
6576 | case M_COP3: | |
6577 | s = "c3"; | |
6578 | copz: | |
6579 | /* For now we just do C (same as Cz). The parameter will be | |
6580 | stored in insn_opcode by mips_ip. */ | |
67c0d1eb | 6581 | macro_build (NULL, s, "C", ip->insn_opcode); |
8fc2e39e | 6582 | break; |
252b5132 | 6583 | |
ea1fb5dc | 6584 | case M_MOVE: |
67c0d1eb | 6585 | move_register (dreg, sreg); |
8fc2e39e | 6586 | break; |
ea1fb5dc | 6587 | |
252b5132 RH |
6588 | #ifdef LOSING_COMPILER |
6589 | default: | |
6590 | /* Try and see if this is a new itbl instruction. | |
6591 | This code builds table entries out of the macros in mip_opcodes. | |
6592 | FIXME: For now we just assemble the expression and pass it's | |
6593 | value along as a 32-bit immediate. | |
bdaaa2e1 | 6594 | We may want to have the assembler assemble this value, |
252b5132 RH |
6595 | so that we gain the assembler's knowledge of delay slots, |
6596 | symbols, etc. | |
6597 | Would it be more efficient to use mask (id) here? */ | |
bdaaa2e1 | 6598 | if (itbl_have_entries |
252b5132 | 6599 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
beae10d5 | 6600 | { |
252b5132 RH |
6601 | s = ip->insn_mo->name; |
6602 | s2 = "cop3"; | |
6603 | coproc = ITBL_DECODE_PNUM (immed_expr);; | |
67c0d1eb | 6604 | macro_build (&immed_expr, s, "C"); |
8fc2e39e | 6605 | break; |
beae10d5 | 6606 | } |
252b5132 | 6607 | macro2 (ip); |
8fc2e39e | 6608 | break; |
252b5132 | 6609 | } |
8fc2e39e TS |
6610 | if (mips_opts.noat && used_at) |
6611 | as_bad (_("Macro used $at after \".set noat\"")); | |
252b5132 | 6612 | } |
bdaaa2e1 | 6613 | |
252b5132 | 6614 | static void |
17a2f251 | 6615 | macro2 (struct mips_cl_insn *ip) |
252b5132 RH |
6616 | { |
6617 | register int treg, sreg, dreg, breg; | |
6618 | int tempreg; | |
6619 | int mask; | |
252b5132 RH |
6620 | int used_at; |
6621 | expressionS expr1; | |
6622 | const char *s; | |
6623 | const char *s2; | |
6624 | const char *fmt; | |
6625 | int likely = 0; | |
6626 | int dbl = 0; | |
6627 | int coproc = 0; | |
6628 | int lr = 0; | |
6629 | int imm = 0; | |
6630 | int off; | |
6631 | offsetT maxnum; | |
6632 | bfd_reloc_code_real_type r; | |
bdaaa2e1 | 6633 | |
252b5132 RH |
6634 | treg = (ip->insn_opcode >> 16) & 0x1f; |
6635 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
6636 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
6637 | mask = ip->insn_mo->mask; | |
bdaaa2e1 | 6638 | |
252b5132 RH |
6639 | expr1.X_op = O_constant; |
6640 | expr1.X_op_symbol = NULL; | |
6641 | expr1.X_add_symbol = NULL; | |
6642 | expr1.X_add_number = 1; | |
bdaaa2e1 | 6643 | |
252b5132 RH |
6644 | switch (mask) |
6645 | { | |
6646 | #endif /* LOSING_COMPILER */ | |
6647 | ||
6648 | case M_DMUL: | |
6649 | dbl = 1; | |
6650 | case M_MUL: | |
67c0d1eb RS |
6651 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg); |
6652 | macro_build (NULL, "mflo", "d", dreg); | |
8fc2e39e | 6653 | break; |
252b5132 RH |
6654 | |
6655 | case M_DMUL_I: | |
6656 | dbl = 1; | |
6657 | case M_MUL_I: | |
6658 | /* The MIPS assembler some times generates shifts and adds. I'm | |
6659 | not trying to be that fancy. GCC should do this for us | |
6660 | anyway. */ | |
8fc2e39e | 6661 | used_at = 1; |
67c0d1eb RS |
6662 | load_register (AT, &imm_expr, dbl); |
6663 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT); | |
6664 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 RH |
6665 | break; |
6666 | ||
6667 | case M_DMULO_I: | |
6668 | dbl = 1; | |
6669 | case M_MULO_I: | |
6670 | imm = 1; | |
6671 | goto do_mulo; | |
6672 | ||
6673 | case M_DMULO: | |
6674 | dbl = 1; | |
6675 | case M_MULO: | |
6676 | do_mulo: | |
b34976b6 | 6677 | mips_emit_delays (TRUE); |
252b5132 RH |
6678 | ++mips_opts.noreorder; |
6679 | mips_any_noreorder = 1; | |
8fc2e39e | 6680 | used_at = 1; |
252b5132 | 6681 | if (imm) |
67c0d1eb RS |
6682 | load_register (AT, &imm_expr, dbl); |
6683 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); | |
6684 | macro_build (NULL, "mflo", "d", dreg); | |
6685 | macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA); | |
6686 | macro_build (NULL, "mfhi", "d", AT); | |
252b5132 | 6687 | if (mips_trap) |
67c0d1eb | 6688 | macro_build (NULL, "tne", "s,t,q", dreg, AT, 6); |
252b5132 RH |
6689 | else |
6690 | { | |
6691 | expr1.X_add_number = 8; | |
67c0d1eb RS |
6692 | macro_build (&expr1, "beq", "s,t,p", dreg, AT); |
6693 | macro_build (NULL, "nop", "", 0); | |
6694 | macro_build (NULL, "break", "c", 6); | |
252b5132 RH |
6695 | } |
6696 | --mips_opts.noreorder; | |
67c0d1eb | 6697 | macro_build (NULL, "mflo", "d", dreg); |
252b5132 RH |
6698 | break; |
6699 | ||
6700 | case M_DMULOU_I: | |
6701 | dbl = 1; | |
6702 | case M_MULOU_I: | |
6703 | imm = 1; | |
6704 | goto do_mulou; | |
6705 | ||
6706 | case M_DMULOU: | |
6707 | dbl = 1; | |
6708 | case M_MULOU: | |
6709 | do_mulou: | |
b34976b6 | 6710 | mips_emit_delays (TRUE); |
252b5132 RH |
6711 | ++mips_opts.noreorder; |
6712 | mips_any_noreorder = 1; | |
8fc2e39e | 6713 | used_at = 1; |
252b5132 | 6714 | if (imm) |
67c0d1eb RS |
6715 | load_register (AT, &imm_expr, dbl); |
6716 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
17a2f251 | 6717 | sreg, imm ? AT : treg); |
67c0d1eb RS |
6718 | macro_build (NULL, "mfhi", "d", AT); |
6719 | macro_build (NULL, "mflo", "d", dreg); | |
252b5132 | 6720 | if (mips_trap) |
67c0d1eb | 6721 | macro_build (NULL, "tne", "s,t,q", AT, 0, 6); |
252b5132 RH |
6722 | else |
6723 | { | |
6724 | expr1.X_add_number = 8; | |
67c0d1eb RS |
6725 | macro_build (&expr1, "beq", "s,t,p", AT, 0); |
6726 | macro_build (NULL, "nop", "", 0); | |
6727 | macro_build (NULL, "break", "c", 6); | |
252b5132 RH |
6728 | } |
6729 | --mips_opts.noreorder; | |
6730 | break; | |
6731 | ||
771c7ce4 | 6732 | case M_DROL: |
fef14a42 | 6733 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
6734 | { |
6735 | if (dreg == sreg) | |
6736 | { | |
6737 | tempreg = AT; | |
6738 | used_at = 1; | |
6739 | } | |
6740 | else | |
6741 | { | |
6742 | tempreg = dreg; | |
82dd0097 | 6743 | } |
67c0d1eb RS |
6744 | macro_build (NULL, "dnegu", "d,w", tempreg, treg); |
6745 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 6746 | break; |
82dd0097 | 6747 | } |
8fc2e39e | 6748 | used_at = 1; |
67c0d1eb RS |
6749 | macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); |
6750 | macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT); | |
6751 | macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg); | |
6752 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
6753 | break; |
6754 | ||
252b5132 | 6755 | case M_ROL: |
fef14a42 | 6756 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 CD |
6757 | { |
6758 | if (dreg == sreg) | |
6759 | { | |
6760 | tempreg = AT; | |
6761 | used_at = 1; | |
6762 | } | |
6763 | else | |
6764 | { | |
6765 | tempreg = dreg; | |
82dd0097 | 6766 | } |
67c0d1eb RS |
6767 | macro_build (NULL, "negu", "d,w", tempreg, treg); |
6768 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 6769 | break; |
82dd0097 | 6770 | } |
8fc2e39e | 6771 | used_at = 1; |
67c0d1eb RS |
6772 | macro_build (NULL, "subu", "d,v,t", AT, 0, treg); |
6773 | macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT); | |
6774 | macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg); | |
6775 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
6776 | break; |
6777 | ||
771c7ce4 TS |
6778 | case M_DROL_I: |
6779 | { | |
6780 | unsigned int rot; | |
82dd0097 | 6781 | char *l, *r; |
771c7ce4 TS |
6782 | |
6783 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 6784 | as_bad (_("Improper rotate count")); |
771c7ce4 | 6785 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 6786 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
6787 | { |
6788 | rot = (64 - rot) & 0x3f; | |
6789 | if (rot >= 32) | |
67c0d1eb | 6790 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
60b63b72 | 6791 | else |
67c0d1eb | 6792 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 6793 | break; |
60b63b72 | 6794 | } |
483fc7cd | 6795 | if (rot == 0) |
483fc7cd | 6796 | { |
67c0d1eb | 6797 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 6798 | break; |
483fc7cd | 6799 | } |
82dd0097 CD |
6800 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
6801 | r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; | |
6802 | rot &= 0x1f; | |
8fc2e39e | 6803 | used_at = 1; |
67c0d1eb RS |
6804 | macro_build (NULL, l, "d,w,<", AT, sreg, rot); |
6805 | macro_build (NULL, r, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
6806 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
6807 | } |
6808 | break; | |
6809 | ||
252b5132 | 6810 | case M_ROL_I: |
771c7ce4 TS |
6811 | { |
6812 | unsigned int rot; | |
6813 | ||
6814 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 6815 | as_bad (_("Improper rotate count")); |
771c7ce4 | 6816 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 6817 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 6818 | { |
67c0d1eb | 6819 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f); |
8fc2e39e | 6820 | break; |
60b63b72 | 6821 | } |
483fc7cd | 6822 | if (rot == 0) |
483fc7cd | 6823 | { |
67c0d1eb | 6824 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 6825 | break; |
483fc7cd | 6826 | } |
8fc2e39e | 6827 | used_at = 1; |
67c0d1eb RS |
6828 | macro_build (NULL, "sll", "d,w,<", AT, sreg, rot); |
6829 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
6830 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
6831 | } |
6832 | break; | |
6833 | ||
6834 | case M_DROR: | |
fef14a42 | 6835 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 6836 | { |
67c0d1eb | 6837 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 6838 | break; |
82dd0097 | 6839 | } |
8fc2e39e | 6840 | used_at = 1; |
67c0d1eb RS |
6841 | macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); |
6842 | macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT); | |
6843 | macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg); | |
6844 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
6845 | break; |
6846 | ||
6847 | case M_ROR: | |
fef14a42 | 6848 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 6849 | { |
67c0d1eb | 6850 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 6851 | break; |
82dd0097 | 6852 | } |
8fc2e39e | 6853 | used_at = 1; |
67c0d1eb RS |
6854 | macro_build (NULL, "subu", "d,v,t", AT, 0, treg); |
6855 | macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT); | |
6856 | macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg); | |
6857 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
6858 | break; |
6859 | ||
771c7ce4 TS |
6860 | case M_DROR_I: |
6861 | { | |
6862 | unsigned int rot; | |
82dd0097 | 6863 | char *l, *r; |
771c7ce4 TS |
6864 | |
6865 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 6866 | as_bad (_("Improper rotate count")); |
771c7ce4 | 6867 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 6868 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
6869 | { |
6870 | if (rot >= 32) | |
67c0d1eb | 6871 | macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); |
82dd0097 | 6872 | else |
67c0d1eb | 6873 | macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 6874 | break; |
82dd0097 | 6875 | } |
483fc7cd | 6876 | if (rot == 0) |
483fc7cd | 6877 | { |
67c0d1eb | 6878 | macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 6879 | break; |
483fc7cd | 6880 | } |
82dd0097 CD |
6881 | r = (rot < 0x20) ? "dsrl" : "dsrl32"; |
6882 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; | |
6883 | rot &= 0x1f; | |
8fc2e39e | 6884 | used_at = 1; |
67c0d1eb RS |
6885 | macro_build (NULL, r, "d,w,<", AT, sreg, rot); |
6886 | macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
6887 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
6888 | } |
6889 | break; | |
6890 | ||
252b5132 | 6891 | case M_ROR_I: |
771c7ce4 TS |
6892 | { |
6893 | unsigned int rot; | |
6894 | ||
6895 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 6896 | as_bad (_("Improper rotate count")); |
771c7ce4 | 6897 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 6898 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 6899 | { |
67c0d1eb | 6900 | macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot); |
8fc2e39e | 6901 | break; |
82dd0097 | 6902 | } |
483fc7cd | 6903 | if (rot == 0) |
483fc7cd | 6904 | { |
67c0d1eb | 6905 | macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); |
8fc2e39e | 6906 | break; |
483fc7cd | 6907 | } |
8fc2e39e | 6908 | used_at = 1; |
67c0d1eb RS |
6909 | macro_build (NULL, "srl", "d,w,<", AT, sreg, rot); |
6910 | macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); | |
6911 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 | 6912 | } |
252b5132 RH |
6913 | break; |
6914 | ||
6915 | case M_S_DOB: | |
fef14a42 | 6916 | if (mips_opts.arch == CPU_R4650) |
252b5132 RH |
6917 | { |
6918 | as_bad (_("opcode not supported on this processor")); | |
8fc2e39e | 6919 | break; |
252b5132 | 6920 | } |
e7af610e | 6921 | assert (mips_opts.isa == ISA_MIPS1); |
252b5132 RH |
6922 | /* Even on a big endian machine $fn comes before $fn+1. We have |
6923 | to adjust when storing to memory. */ | |
67c0d1eb RS |
6924 | macro_build (&offset_expr, "swc1", "T,o(b)", |
6925 | target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg); | |
252b5132 | 6926 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
6927 | macro_build (&offset_expr, "swc1", "T,o(b)", |
6928 | target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg); | |
8fc2e39e | 6929 | break; |
252b5132 RH |
6930 | |
6931 | case M_SEQ: | |
6932 | if (sreg == 0) | |
67c0d1eb | 6933 | macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16); |
252b5132 | 6934 | else if (treg == 0) |
67c0d1eb | 6935 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
6936 | else |
6937 | { | |
67c0d1eb RS |
6938 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
6939 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 | 6940 | } |
8fc2e39e | 6941 | break; |
252b5132 RH |
6942 | |
6943 | case M_SEQ_I: | |
6944 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6945 | { | |
67c0d1eb | 6946 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 6947 | break; |
252b5132 RH |
6948 | } |
6949 | if (sreg == 0) | |
6950 | { | |
6951 | as_warn (_("Instruction %s: result is always false"), | |
6952 | ip->insn_mo->name); | |
67c0d1eb | 6953 | move_register (dreg, 0); |
8fc2e39e | 6954 | break; |
252b5132 RH |
6955 | } |
6956 | if (imm_expr.X_op == O_constant | |
6957 | && imm_expr.X_add_number >= 0 | |
6958 | && imm_expr.X_add_number < 0x10000) | |
6959 | { | |
67c0d1eb | 6960 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
6961 | } |
6962 | else if (imm_expr.X_op == O_constant | |
6963 | && imm_expr.X_add_number > -0x8000 | |
6964 | && imm_expr.X_add_number < 0) | |
6965 | { | |
6966 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 6967 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 6968 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
6969 | } |
6970 | else | |
6971 | { | |
67c0d1eb RS |
6972 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
6973 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
6974 | used_at = 1; |
6975 | } | |
67c0d1eb | 6976 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 6977 | break; |
252b5132 RH |
6978 | |
6979 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
6980 | s = "slt"; | |
6981 | goto sge; | |
6982 | case M_SGEU: | |
6983 | s = "sltu"; | |
6984 | sge: | |
67c0d1eb RS |
6985 | macro_build (NULL, s, "d,v,t", dreg, sreg, treg); |
6986 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 6987 | break; |
252b5132 RH |
6988 | |
6989 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
6990 | case M_SGEU_I: | |
6991 | if (imm_expr.X_op == O_constant | |
6992 | && imm_expr.X_add_number >= -0x8000 | |
6993 | && imm_expr.X_add_number < 0x8000) | |
6994 | { | |
67c0d1eb RS |
6995 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
6996 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
6997 | } |
6998 | else | |
6999 | { | |
67c0d1eb RS |
7000 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7001 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", | |
7002 | dreg, sreg, AT); | |
252b5132 RH |
7003 | used_at = 1; |
7004 | } | |
67c0d1eb | 7005 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 7006 | break; |
252b5132 RH |
7007 | |
7008 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
7009 | s = "slt"; | |
7010 | goto sgt; | |
7011 | case M_SGTU: | |
7012 | s = "sltu"; | |
7013 | sgt: | |
67c0d1eb | 7014 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
8fc2e39e | 7015 | break; |
252b5132 RH |
7016 | |
7017 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
7018 | s = "slt"; | |
7019 | goto sgti; | |
7020 | case M_SGTU_I: | |
7021 | s = "sltu"; | |
7022 | sgti: | |
8fc2e39e | 7023 | used_at = 1; |
67c0d1eb RS |
7024 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7025 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
252b5132 RH |
7026 | break; |
7027 | ||
2396cfb9 | 7028 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
7029 | s = "slt"; |
7030 | goto sle; | |
7031 | case M_SLEU: | |
7032 | s = "sltu"; | |
7033 | sle: | |
67c0d1eb RS |
7034 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
7035 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 7036 | break; |
252b5132 | 7037 | |
2396cfb9 | 7038 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
7039 | s = "slt"; |
7040 | goto slei; | |
7041 | case M_SLEU_I: | |
7042 | s = "sltu"; | |
7043 | slei: | |
8fc2e39e | 7044 | used_at = 1; |
67c0d1eb RS |
7045 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7046 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
7047 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
7048 | break; |
7049 | ||
7050 | case M_SLT_I: | |
7051 | if (imm_expr.X_op == O_constant | |
7052 | && imm_expr.X_add_number >= -0x8000 | |
7053 | && imm_expr.X_add_number < 0x8000) | |
7054 | { | |
67c0d1eb | 7055 | macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 7056 | break; |
252b5132 | 7057 | } |
8fc2e39e | 7058 | used_at = 1; |
67c0d1eb RS |
7059 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7060 | macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7061 | break; |
7062 | ||
7063 | case M_SLTU_I: | |
7064 | if (imm_expr.X_op == O_constant | |
7065 | && imm_expr.X_add_number >= -0x8000 | |
7066 | && imm_expr.X_add_number < 0x8000) | |
7067 | { | |
67c0d1eb | 7068 | macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg, |
17a2f251 | 7069 | BFD_RELOC_LO16); |
8fc2e39e | 7070 | break; |
252b5132 | 7071 | } |
8fc2e39e | 7072 | used_at = 1; |
67c0d1eb RS |
7073 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7074 | macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7075 | break; |
7076 | ||
7077 | case M_SNE: | |
7078 | if (sreg == 0) | |
67c0d1eb | 7079 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg); |
252b5132 | 7080 | else if (treg == 0) |
67c0d1eb | 7081 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
7082 | else |
7083 | { | |
67c0d1eb RS |
7084 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
7085 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
252b5132 | 7086 | } |
8fc2e39e | 7087 | break; |
252b5132 RH |
7088 | |
7089 | case M_SNE_I: | |
7090 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7091 | { | |
67c0d1eb | 7092 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
8fc2e39e | 7093 | break; |
252b5132 RH |
7094 | } |
7095 | if (sreg == 0) | |
7096 | { | |
7097 | as_warn (_("Instruction %s: result is always true"), | |
7098 | ip->insn_mo->name); | |
67c0d1eb RS |
7099 | macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", |
7100 | dreg, 0, BFD_RELOC_LO16); | |
8fc2e39e | 7101 | break; |
252b5132 RH |
7102 | } |
7103 | if (imm_expr.X_op == O_constant | |
7104 | && imm_expr.X_add_number >= 0 | |
7105 | && imm_expr.X_add_number < 0x10000) | |
7106 | { | |
67c0d1eb | 7107 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7108 | } |
7109 | else if (imm_expr.X_op == O_constant | |
7110 | && imm_expr.X_add_number > -0x8000 | |
7111 | && imm_expr.X_add_number < 0) | |
7112 | { | |
7113 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7114 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 7115 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
7116 | } |
7117 | else | |
7118 | { | |
67c0d1eb RS |
7119 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7120 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7121 | used_at = 1; |
7122 | } | |
67c0d1eb | 7123 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); |
8fc2e39e | 7124 | break; |
252b5132 RH |
7125 | |
7126 | case M_DSUB_I: | |
7127 | dbl = 1; | |
7128 | case M_SUB_I: | |
7129 | if (imm_expr.X_op == O_constant | |
7130 | && imm_expr.X_add_number > -0x8000 | |
7131 | && imm_expr.X_add_number <= 0x8000) | |
7132 | { | |
7133 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7134 | macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j", |
7135 | dreg, sreg, BFD_RELOC_LO16); | |
8fc2e39e | 7136 | break; |
252b5132 | 7137 | } |
8fc2e39e | 7138 | used_at = 1; |
67c0d1eb RS |
7139 | load_register (AT, &imm_expr, dbl); |
7140 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7141 | break; |
7142 | ||
7143 | case M_DSUBU_I: | |
7144 | dbl = 1; | |
7145 | case M_SUBU_I: | |
7146 | if (imm_expr.X_op == O_constant | |
7147 | && imm_expr.X_add_number > -0x8000 | |
7148 | && imm_expr.X_add_number <= 0x8000) | |
7149 | { | |
7150 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb RS |
7151 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j", |
7152 | dreg, sreg, BFD_RELOC_LO16); | |
8fc2e39e | 7153 | break; |
252b5132 | 7154 | } |
8fc2e39e | 7155 | used_at = 1; |
67c0d1eb RS |
7156 | load_register (AT, &imm_expr, dbl); |
7157 | macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
7158 | break; |
7159 | ||
7160 | case M_TEQ_I: | |
7161 | s = "teq"; | |
7162 | goto trap; | |
7163 | case M_TGE_I: | |
7164 | s = "tge"; | |
7165 | goto trap; | |
7166 | case M_TGEU_I: | |
7167 | s = "tgeu"; | |
7168 | goto trap; | |
7169 | case M_TLT_I: | |
7170 | s = "tlt"; | |
7171 | goto trap; | |
7172 | case M_TLTU_I: | |
7173 | s = "tltu"; | |
7174 | goto trap; | |
7175 | case M_TNE_I: | |
7176 | s = "tne"; | |
7177 | trap: | |
8fc2e39e | 7178 | used_at = 1; |
67c0d1eb RS |
7179 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
7180 | macro_build (NULL, s, "s,t", sreg, AT); | |
252b5132 RH |
7181 | break; |
7182 | ||
252b5132 | 7183 | case M_TRUNCWS: |
43841e91 | 7184 | case M_TRUNCWD: |
e7af610e | 7185 | assert (mips_opts.isa == ISA_MIPS1); |
8fc2e39e | 7186 | used_at = 1; |
252b5132 RH |
7187 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
7188 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
7189 | ||
7190 | /* | |
7191 | * Is the double cfc1 instruction a bug in the mips assembler; | |
7192 | * or is there a reason for it? | |
7193 | */ | |
b34976b6 | 7194 | mips_emit_delays (TRUE); |
252b5132 RH |
7195 | ++mips_opts.noreorder; |
7196 | mips_any_noreorder = 1; | |
67c0d1eb RS |
7197 | macro_build (NULL, "cfc1", "t,G", treg, RA); |
7198 | macro_build (NULL, "cfc1", "t,G", treg, RA); | |
7199 | macro_build (NULL, "nop", ""); | |
252b5132 | 7200 | expr1.X_add_number = 3; |
67c0d1eb | 7201 | macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16); |
252b5132 | 7202 | expr1.X_add_number = 2; |
67c0d1eb RS |
7203 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
7204 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
7205 | macro_build (NULL, "nop", ""); | |
7206 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
7207 | dreg, sreg); | |
7208 | macro_build (NULL, "ctc1", "t,G", treg, RA); | |
7209 | macro_build (NULL, "nop", ""); | |
252b5132 RH |
7210 | --mips_opts.noreorder; |
7211 | break; | |
7212 | ||
7213 | case M_ULH: | |
7214 | s = "lb"; | |
7215 | goto ulh; | |
7216 | case M_ULHU: | |
7217 | s = "lbu"; | |
7218 | ulh: | |
8fc2e39e | 7219 | used_at = 1; |
252b5132 RH |
7220 | if (offset_expr.X_add_number >= 0x7fff) |
7221 | as_bad (_("operand overflow")); | |
252b5132 | 7222 | if (! target_big_endian) |
f9419b05 | 7223 | ++offset_expr.X_add_number; |
67c0d1eb | 7224 | macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 | 7225 | if (! target_big_endian) |
f9419b05 | 7226 | --offset_expr.X_add_number; |
252b5132 | 7227 | else |
f9419b05 | 7228 | ++offset_expr.X_add_number; |
67c0d1eb RS |
7229 | macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
7230 | macro_build (NULL, "sll", "d,w,<", AT, AT, 8); | |
7231 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7232 | break; |
7233 | ||
7234 | case M_ULD: | |
7235 | s = "ldl"; | |
7236 | s2 = "ldr"; | |
7237 | off = 7; | |
7238 | goto ulw; | |
7239 | case M_ULW: | |
7240 | s = "lwl"; | |
7241 | s2 = "lwr"; | |
7242 | off = 3; | |
7243 | ulw: | |
7244 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7245 | as_bad (_("operand overflow")); | |
af22f5b2 CD |
7246 | if (treg != breg) |
7247 | tempreg = treg; | |
7248 | else | |
8fc2e39e TS |
7249 | { |
7250 | used_at = 1; | |
7251 | tempreg = AT; | |
7252 | } | |
252b5132 RH |
7253 | if (! target_big_endian) |
7254 | offset_expr.X_add_number += off; | |
67c0d1eb | 7255 | macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7256 | if (! target_big_endian) |
7257 | offset_expr.X_add_number -= off; | |
7258 | else | |
7259 | offset_expr.X_add_number += off; | |
67c0d1eb | 7260 | macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); |
af22f5b2 CD |
7261 | |
7262 | /* If necessary, move the result in tempreg the final destination. */ | |
7263 | if (treg == tempreg) | |
8fc2e39e | 7264 | break; |
af22f5b2 | 7265 | /* Protect second load's delay slot. */ |
017315e4 | 7266 | load_delay_nop (); |
67c0d1eb | 7267 | move_register (treg, tempreg); |
af22f5b2 | 7268 | break; |
252b5132 RH |
7269 | |
7270 | case M_ULD_A: | |
7271 | s = "ldl"; | |
7272 | s2 = "ldr"; | |
7273 | off = 7; | |
7274 | goto ulwa; | |
7275 | case M_ULW_A: | |
7276 | s = "lwl"; | |
7277 | s2 = "lwr"; | |
7278 | off = 3; | |
7279 | ulwa: | |
d6bc6245 | 7280 | used_at = 1; |
67c0d1eb | 7281 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7282 | if (breg != 0) |
67c0d1eb | 7283 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7284 | if (! target_big_endian) |
7285 | expr1.X_add_number = off; | |
7286 | else | |
7287 | expr1.X_add_number = 0; | |
67c0d1eb | 7288 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7289 | if (! target_big_endian) |
7290 | expr1.X_add_number = 0; | |
7291 | else | |
7292 | expr1.X_add_number = off; | |
67c0d1eb | 7293 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7294 | break; |
7295 | ||
7296 | case M_ULH_A: | |
7297 | case M_ULHU_A: | |
d6bc6245 | 7298 | used_at = 1; |
67c0d1eb | 7299 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7300 | if (breg != 0) |
67c0d1eb | 7301 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7302 | if (target_big_endian) |
7303 | expr1.X_add_number = 0; | |
67c0d1eb | 7304 | macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", |
17a2f251 | 7305 | treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7306 | if (target_big_endian) |
7307 | expr1.X_add_number = 1; | |
7308 | else | |
7309 | expr1.X_add_number = 0; | |
67c0d1eb RS |
7310 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
7311 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
7312 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7313 | break; |
7314 | ||
7315 | case M_USH: | |
8fc2e39e | 7316 | used_at = 1; |
252b5132 RH |
7317 | if (offset_expr.X_add_number >= 0x7fff) |
7318 | as_bad (_("operand overflow")); | |
7319 | if (target_big_endian) | |
f9419b05 | 7320 | ++offset_expr.X_add_number; |
67c0d1eb RS |
7321 | macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg); |
7322 | macro_build (NULL, "srl", "d,w,<", AT, treg, 8); | |
252b5132 | 7323 | if (target_big_endian) |
f9419b05 | 7324 | --offset_expr.X_add_number; |
252b5132 | 7325 | else |
f9419b05 | 7326 | ++offset_expr.X_add_number; |
67c0d1eb | 7327 | macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg); |
252b5132 RH |
7328 | break; |
7329 | ||
7330 | case M_USD: | |
7331 | s = "sdl"; | |
7332 | s2 = "sdr"; | |
7333 | off = 7; | |
7334 | goto usw; | |
7335 | case M_USW: | |
7336 | s = "swl"; | |
7337 | s2 = "swr"; | |
7338 | off = 3; | |
7339 | usw: | |
7340 | if (offset_expr.X_add_number >= 0x8000 - off) | |
7341 | as_bad (_("operand overflow")); | |
7342 | if (! target_big_endian) | |
7343 | offset_expr.X_add_number += off; | |
67c0d1eb | 7344 | macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
252b5132 RH |
7345 | if (! target_big_endian) |
7346 | offset_expr.X_add_number -= off; | |
7347 | else | |
7348 | offset_expr.X_add_number += off; | |
67c0d1eb | 7349 | macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
8fc2e39e | 7350 | break; |
252b5132 RH |
7351 | |
7352 | case M_USD_A: | |
7353 | s = "sdl"; | |
7354 | s2 = "sdr"; | |
7355 | off = 7; | |
7356 | goto uswa; | |
7357 | case M_USW_A: | |
7358 | s = "swl"; | |
7359 | s2 = "swr"; | |
7360 | off = 3; | |
7361 | uswa: | |
d6bc6245 | 7362 | used_at = 1; |
67c0d1eb | 7363 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7364 | if (breg != 0) |
67c0d1eb | 7365 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7366 | if (! target_big_endian) |
7367 | expr1.X_add_number = off; | |
7368 | else | |
7369 | expr1.X_add_number = 0; | |
67c0d1eb | 7370 | macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7371 | if (! target_big_endian) |
7372 | expr1.X_add_number = 0; | |
7373 | else | |
7374 | expr1.X_add_number = off; | |
67c0d1eb | 7375 | macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7376 | break; |
7377 | ||
7378 | case M_USH_A: | |
d6bc6245 | 7379 | used_at = 1; |
67c0d1eb | 7380 | load_address (AT, &offset_expr, &used_at); |
252b5132 | 7381 | if (breg != 0) |
67c0d1eb | 7382 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
252b5132 RH |
7383 | if (! target_big_endian) |
7384 | expr1.X_add_number = 0; | |
67c0d1eb RS |
7385 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
7386 | macro_build (NULL, "srl", "d,w,<", treg, treg, 8); | |
252b5132 RH |
7387 | if (! target_big_endian) |
7388 | expr1.X_add_number = 1; | |
7389 | else | |
7390 | expr1.X_add_number = 0; | |
67c0d1eb | 7391 | macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
252b5132 RH |
7392 | if (! target_big_endian) |
7393 | expr1.X_add_number = 0; | |
7394 | else | |
7395 | expr1.X_add_number = 1; | |
67c0d1eb RS |
7396 | macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); |
7397 | macro_build (NULL, "sll", "d,w,<", treg, treg, 8); | |
7398 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
252b5132 RH |
7399 | break; |
7400 | ||
7401 | default: | |
7402 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 7403 | are added dynamically. */ |
252b5132 RH |
7404 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
7405 | break; | |
7406 | } | |
8fc2e39e TS |
7407 | if (mips_opts.noat && used_at) |
7408 | as_bad (_("Macro used $at after \".set noat\"")); | |
252b5132 RH |
7409 | } |
7410 | ||
7411 | /* Implement macros in mips16 mode. */ | |
7412 | ||
7413 | static void | |
17a2f251 | 7414 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 RH |
7415 | { |
7416 | int mask; | |
7417 | int xreg, yreg, zreg, tmp; | |
252b5132 RH |
7418 | expressionS expr1; |
7419 | int dbl; | |
7420 | const char *s, *s2, *s3; | |
7421 | ||
7422 | mask = ip->insn_mo->mask; | |
7423 | ||
bf12938e RS |
7424 | xreg = MIPS16_EXTRACT_OPERAND (RX, *ip); |
7425 | yreg = MIPS16_EXTRACT_OPERAND (RY, *ip); | |
7426 | zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip); | |
252b5132 | 7427 | |
252b5132 RH |
7428 | expr1.X_op = O_constant; |
7429 | expr1.X_op_symbol = NULL; | |
7430 | expr1.X_add_symbol = NULL; | |
7431 | expr1.X_add_number = 1; | |
7432 | ||
7433 | dbl = 0; | |
7434 | ||
7435 | switch (mask) | |
7436 | { | |
7437 | default: | |
7438 | internalError (); | |
7439 | ||
7440 | case M_DDIV_3: | |
7441 | dbl = 1; | |
7442 | case M_DIV_3: | |
7443 | s = "mflo"; | |
7444 | goto do_div3; | |
7445 | case M_DREM_3: | |
7446 | dbl = 1; | |
7447 | case M_REM_3: | |
7448 | s = "mfhi"; | |
7449 | do_div3: | |
b34976b6 | 7450 | mips_emit_delays (TRUE); |
252b5132 RH |
7451 | ++mips_opts.noreorder; |
7452 | mips_any_noreorder = 1; | |
67c0d1eb | 7453 | macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg); |
252b5132 | 7454 | expr1.X_add_number = 2; |
67c0d1eb RS |
7455 | macro_build (&expr1, "bnez", "x,p", yreg); |
7456 | macro_build (NULL, "break", "6", 7); | |
bdaaa2e1 | 7457 | |
252b5132 RH |
7458 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
7459 | since that causes an overflow. We should do that as well, | |
7460 | but I don't see how to do the comparisons without a temporary | |
7461 | register. */ | |
7462 | --mips_opts.noreorder; | |
67c0d1eb | 7463 | macro_build (NULL, s, "x", zreg); |
252b5132 RH |
7464 | break; |
7465 | ||
7466 | case M_DIVU_3: | |
7467 | s = "divu"; | |
7468 | s2 = "mflo"; | |
7469 | goto do_divu3; | |
7470 | case M_REMU_3: | |
7471 | s = "divu"; | |
7472 | s2 = "mfhi"; | |
7473 | goto do_divu3; | |
7474 | case M_DDIVU_3: | |
7475 | s = "ddivu"; | |
7476 | s2 = "mflo"; | |
7477 | goto do_divu3; | |
7478 | case M_DREMU_3: | |
7479 | s = "ddivu"; | |
7480 | s2 = "mfhi"; | |
7481 | do_divu3: | |
b34976b6 | 7482 | mips_emit_delays (TRUE); |
252b5132 RH |
7483 | ++mips_opts.noreorder; |
7484 | mips_any_noreorder = 1; | |
67c0d1eb | 7485 | macro_build (NULL, s, "0,x,y", xreg, yreg); |
252b5132 | 7486 | expr1.X_add_number = 2; |
67c0d1eb RS |
7487 | macro_build (&expr1, "bnez", "x,p", yreg); |
7488 | macro_build (NULL, "break", "6", 7); | |
252b5132 | 7489 | --mips_opts.noreorder; |
67c0d1eb | 7490 | macro_build (NULL, s2, "x", zreg); |
252b5132 RH |
7491 | break; |
7492 | ||
7493 | case M_DMUL: | |
7494 | dbl = 1; | |
7495 | case M_MUL: | |
67c0d1eb RS |
7496 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
7497 | macro_build (NULL, "mflo", "x", zreg); | |
8fc2e39e | 7498 | break; |
252b5132 RH |
7499 | |
7500 | case M_DSUBU_I: | |
7501 | dbl = 1; | |
7502 | goto do_subu; | |
7503 | case M_SUBU_I: | |
7504 | do_subu: | |
7505 | if (imm_expr.X_op != O_constant) | |
7506 | as_bad (_("Unsupported large constant")); | |
7507 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7508 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
7509 | break; |
7510 | ||
7511 | case M_SUBU_I_2: | |
7512 | if (imm_expr.X_op != O_constant) | |
7513 | as_bad (_("Unsupported large constant")); | |
7514 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7515 | macro_build (&imm_expr, "addiu", "x,k", xreg); |
252b5132 RH |
7516 | break; |
7517 | ||
7518 | case M_DSUBU_I_2: | |
7519 | if (imm_expr.X_op != O_constant) | |
7520 | as_bad (_("Unsupported large constant")); | |
7521 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 7522 | macro_build (&imm_expr, "daddiu", "y,j", yreg); |
252b5132 RH |
7523 | break; |
7524 | ||
7525 | case M_BEQ: | |
7526 | s = "cmp"; | |
7527 | s2 = "bteqz"; | |
7528 | goto do_branch; | |
7529 | case M_BNE: | |
7530 | s = "cmp"; | |
7531 | s2 = "btnez"; | |
7532 | goto do_branch; | |
7533 | case M_BLT: | |
7534 | s = "slt"; | |
7535 | s2 = "btnez"; | |
7536 | goto do_branch; | |
7537 | case M_BLTU: | |
7538 | s = "sltu"; | |
7539 | s2 = "btnez"; | |
7540 | goto do_branch; | |
7541 | case M_BLE: | |
7542 | s = "slt"; | |
7543 | s2 = "bteqz"; | |
7544 | goto do_reverse_branch; | |
7545 | case M_BLEU: | |
7546 | s = "sltu"; | |
7547 | s2 = "bteqz"; | |
7548 | goto do_reverse_branch; | |
7549 | case M_BGE: | |
7550 | s = "slt"; | |
7551 | s2 = "bteqz"; | |
7552 | goto do_branch; | |
7553 | case M_BGEU: | |
7554 | s = "sltu"; | |
7555 | s2 = "bteqz"; | |
7556 | goto do_branch; | |
7557 | case M_BGT: | |
7558 | s = "slt"; | |
7559 | s2 = "btnez"; | |
7560 | goto do_reverse_branch; | |
7561 | case M_BGTU: | |
7562 | s = "sltu"; | |
7563 | s2 = "btnez"; | |
7564 | ||
7565 | do_reverse_branch: | |
7566 | tmp = xreg; | |
7567 | xreg = yreg; | |
7568 | yreg = tmp; | |
7569 | ||
7570 | do_branch: | |
67c0d1eb RS |
7571 | macro_build (NULL, s, "x,y", xreg, yreg); |
7572 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
7573 | break; |
7574 | ||
7575 | case M_BEQ_I: | |
7576 | s = "cmpi"; | |
7577 | s2 = "bteqz"; | |
7578 | s3 = "x,U"; | |
7579 | goto do_branch_i; | |
7580 | case M_BNE_I: | |
7581 | s = "cmpi"; | |
7582 | s2 = "btnez"; | |
7583 | s3 = "x,U"; | |
7584 | goto do_branch_i; | |
7585 | case M_BLT_I: | |
7586 | s = "slti"; | |
7587 | s2 = "btnez"; | |
7588 | s3 = "x,8"; | |
7589 | goto do_branch_i; | |
7590 | case M_BLTU_I: | |
7591 | s = "sltiu"; | |
7592 | s2 = "btnez"; | |
7593 | s3 = "x,8"; | |
7594 | goto do_branch_i; | |
7595 | case M_BLE_I: | |
7596 | s = "slti"; | |
7597 | s2 = "btnez"; | |
7598 | s3 = "x,8"; | |
7599 | goto do_addone_branch_i; | |
7600 | case M_BLEU_I: | |
7601 | s = "sltiu"; | |
7602 | s2 = "btnez"; | |
7603 | s3 = "x,8"; | |
7604 | goto do_addone_branch_i; | |
7605 | case M_BGE_I: | |
7606 | s = "slti"; | |
7607 | s2 = "bteqz"; | |
7608 | s3 = "x,8"; | |
7609 | goto do_branch_i; | |
7610 | case M_BGEU_I: | |
7611 | s = "sltiu"; | |
7612 | s2 = "bteqz"; | |
7613 | s3 = "x,8"; | |
7614 | goto do_branch_i; | |
7615 | case M_BGT_I: | |
7616 | s = "slti"; | |
7617 | s2 = "bteqz"; | |
7618 | s3 = "x,8"; | |
7619 | goto do_addone_branch_i; | |
7620 | case M_BGTU_I: | |
7621 | s = "sltiu"; | |
7622 | s2 = "bteqz"; | |
7623 | s3 = "x,8"; | |
7624 | ||
7625 | do_addone_branch_i: | |
7626 | if (imm_expr.X_op != O_constant) | |
7627 | as_bad (_("Unsupported large constant")); | |
7628 | ++imm_expr.X_add_number; | |
7629 | ||
7630 | do_branch_i: | |
67c0d1eb RS |
7631 | macro_build (&imm_expr, s, s3, xreg); |
7632 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
7633 | break; |
7634 | ||
7635 | case M_ABS: | |
7636 | expr1.X_add_number = 0; | |
67c0d1eb | 7637 | macro_build (&expr1, "slti", "x,8", yreg); |
252b5132 | 7638 | if (xreg != yreg) |
67c0d1eb | 7639 | move_register (xreg, yreg); |
252b5132 | 7640 | expr1.X_add_number = 2; |
67c0d1eb RS |
7641 | macro_build (&expr1, "bteqz", "p"); |
7642 | macro_build (NULL, "neg", "x,w", xreg, xreg); | |
252b5132 RH |
7643 | } |
7644 | } | |
7645 | ||
7646 | /* For consistency checking, verify that all bits are specified either | |
7647 | by the match/mask part of the instruction definition, or by the | |
7648 | operand list. */ | |
7649 | static int | |
17a2f251 | 7650 | validate_mips_insn (const struct mips_opcode *opc) |
252b5132 RH |
7651 | { |
7652 | const char *p = opc->args; | |
7653 | char c; | |
7654 | unsigned long used_bits = opc->mask; | |
7655 | ||
7656 | if ((used_bits & opc->match) != opc->match) | |
7657 | { | |
7658 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
7659 | opc->name, opc->args); | |
7660 | return 0; | |
7661 | } | |
7662 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
7663 | while (*p) | |
7664 | switch (c = *p++) | |
7665 | { | |
7666 | case ',': break; | |
7667 | case '(': break; | |
7668 | case ')': break; | |
af7ee8bf CD |
7669 | case '+': |
7670 | switch (c = *p++) | |
7671 | { | |
7672 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
7673 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
7674 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
bbcc0807 CD |
7675 | case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); |
7676 | USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; | |
5f74bc13 CD |
7677 | case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
7678 | case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
7679 | case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
7680 | case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
7681 | case 'I': break; | |
af7ee8bf CD |
7682 | default: |
7683 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
7684 | c, opc->name, opc->args); | |
7685 | return 0; | |
7686 | } | |
7687 | break; | |
252b5132 RH |
7688 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
7689 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
7690 | case 'A': break; | |
4372b673 | 7691 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
7692 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
7693 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
7694 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7695 | case 'F': break; | |
7696 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 7697 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 7698 | case 'I': break; |
e972090a | 7699 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 7700 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
7701 | case 'L': break; |
7702 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
7703 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
7704 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
7705 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
7706 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
7707 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
7708 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7709 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
7710 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7711 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
7712 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
7713 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
7714 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
7715 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
7716 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7717 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
7718 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
7719 | case 'f': break; | |
7720 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
7721 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
7722 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7723 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
7724 | case 'l': break; | |
7725 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7726 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
7727 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
7728 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7729 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7730 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7731 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
7732 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
7733 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
7734 | case 'x': break; | |
7735 | case 'z': break; | |
7736 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
7737 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
7738 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
7739 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
7740 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
7741 | case '[': break; | |
7742 | case ']': break; | |
252b5132 RH |
7743 | default: |
7744 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
7745 | c, opc->name, opc->args); | |
7746 | return 0; | |
7747 | } | |
7748 | #undef USE_BITS | |
7749 | if (used_bits != 0xffffffff) | |
7750 | { | |
7751 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
7752 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
7753 | return 0; | |
7754 | } | |
7755 | return 1; | |
7756 | } | |
7757 | ||
7758 | /* This routine assembles an instruction into its binary format. As a | |
7759 | side effect, it sets one of the global variables imm_reloc or | |
7760 | offset_reloc to the type of relocation to do if one of the operands | |
7761 | is an address expression. */ | |
7762 | ||
7763 | static void | |
17a2f251 | 7764 | mips_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
7765 | { |
7766 | char *s; | |
7767 | const char *args; | |
43841e91 | 7768 | char c = 0; |
252b5132 RH |
7769 | struct mips_opcode *insn; |
7770 | char *argsStart; | |
7771 | unsigned int regno; | |
7772 | unsigned int lastregno = 0; | |
af7ee8bf | 7773 | unsigned int lastpos = 0; |
071742cf | 7774 | unsigned int limlo, limhi; |
252b5132 RH |
7775 | char *s_reset; |
7776 | char save_c = 0; | |
252b5132 RH |
7777 | |
7778 | insn_error = NULL; | |
7779 | ||
7780 | /* If the instruction contains a '.', we first try to match an instruction | |
7781 | including the '.'. Then we try again without the '.'. */ | |
7782 | insn = NULL; | |
3882b010 | 7783 | for (s = str; *s != '\0' && !ISSPACE (*s); ++s) |
252b5132 RH |
7784 | continue; |
7785 | ||
7786 | /* If we stopped on whitespace, then replace the whitespace with null for | |
7787 | the call to hash_find. Save the character we replaced just in case we | |
7788 | have to re-parse the instruction. */ | |
3882b010 | 7789 | if (ISSPACE (*s)) |
252b5132 RH |
7790 | { |
7791 | save_c = *s; | |
7792 | *s++ = '\0'; | |
7793 | } | |
bdaaa2e1 | 7794 | |
252b5132 RH |
7795 | insn = (struct mips_opcode *) hash_find (op_hash, str); |
7796 | ||
7797 | /* If we didn't find the instruction in the opcode table, try again, but | |
7798 | this time with just the instruction up to, but not including the | |
7799 | first '.'. */ | |
7800 | if (insn == NULL) | |
7801 | { | |
bdaaa2e1 | 7802 | /* Restore the character we overwrite above (if any). */ |
252b5132 RH |
7803 | if (save_c) |
7804 | *(--s) = save_c; | |
7805 | ||
7806 | /* Scan up to the first '.' or whitespace. */ | |
3882b010 L |
7807 | for (s = str; |
7808 | *s != '\0' && *s != '.' && !ISSPACE (*s); | |
7809 | ++s) | |
252b5132 RH |
7810 | continue; |
7811 | ||
7812 | /* If we did not find a '.', then we can quit now. */ | |
7813 | if (*s != '.') | |
7814 | { | |
7815 | insn_error = "unrecognized opcode"; | |
7816 | return; | |
7817 | } | |
7818 | ||
7819 | /* Lookup the instruction in the hash table. */ | |
7820 | *s++ = '\0'; | |
7821 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
7822 | { | |
7823 | insn_error = "unrecognized opcode"; | |
7824 | return; | |
7825 | } | |
252b5132 RH |
7826 | } |
7827 | ||
7828 | argsStart = s; | |
7829 | for (;;) | |
7830 | { | |
b34976b6 | 7831 | bfd_boolean ok; |
252b5132 RH |
7832 | |
7833 | assert (strcmp (insn->name, str) == 0); | |
7834 | ||
1f25f5d3 CD |
7835 | if (OPCODE_IS_MEMBER (insn, |
7836 | (mips_opts.isa | |
3396de36 | 7837 | | (file_ase_mips16 ? INSN_MIPS16 : 0) |
deec1734 | 7838 | | (mips_opts.ase_mdmx ? INSN_MDMX : 0) |
98d3f06f | 7839 | | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)), |
fef14a42 | 7840 | mips_opts.arch)) |
b34976b6 | 7841 | ok = TRUE; |
bdaaa2e1 | 7842 | else |
b34976b6 | 7843 | ok = FALSE; |
bdaaa2e1 | 7844 | |
252b5132 RH |
7845 | if (insn->pinfo != INSN_MACRO) |
7846 | { | |
fef14a42 | 7847 | if (mips_opts.arch == CPU_R4650 && (insn->pinfo & FP_D) != 0) |
b34976b6 | 7848 | ok = FALSE; |
252b5132 RH |
7849 | } |
7850 | ||
7851 | if (! ok) | |
7852 | { | |
7853 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
7854 | && strcmp (insn->name, insn[1].name) == 0) | |
7855 | { | |
7856 | ++insn; | |
7857 | continue; | |
7858 | } | |
252b5132 | 7859 | else |
beae10d5 | 7860 | { |
268f6bed L |
7861 | if (!insn_error) |
7862 | { | |
7863 | static char buf[100]; | |
fef14a42 TS |
7864 | sprintf (buf, |
7865 | _("opcode not supported on this processor: %s (%s)"), | |
7866 | mips_cpu_info_from_arch (mips_opts.arch)->name, | |
7867 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
268f6bed L |
7868 | insn_error = buf; |
7869 | } | |
7870 | if (save_c) | |
7871 | *(--s) = save_c; | |
2bd7f1f3 | 7872 | return; |
252b5132 | 7873 | } |
252b5132 RH |
7874 | } |
7875 | ||
1e915849 | 7876 | create_insn (ip, insn); |
268f6bed | 7877 | insn_error = NULL; |
252b5132 RH |
7878 | for (args = insn->args;; ++args) |
7879 | { | |
deec1734 CD |
7880 | int is_mdmx; |
7881 | ||
ad8d3bb3 | 7882 | s += strspn (s, " \t"); |
deec1734 | 7883 | is_mdmx = 0; |
252b5132 RH |
7884 | switch (*args) |
7885 | { | |
7886 | case '\0': /* end of args */ | |
7887 | if (*s == '\0') | |
7888 | return; | |
7889 | break; | |
7890 | ||
7891 | case ',': | |
7892 | if (*s++ == *args) | |
7893 | continue; | |
7894 | s--; | |
7895 | switch (*++args) | |
7896 | { | |
7897 | case 'r': | |
7898 | case 'v': | |
bf12938e | 7899 | INSERT_OPERAND (RS, *ip, lastregno); |
252b5132 RH |
7900 | continue; |
7901 | ||
7902 | case 'w': | |
bf12938e | 7903 | INSERT_OPERAND (RT, *ip, lastregno); |
38487616 TS |
7904 | continue; |
7905 | ||
252b5132 | 7906 | case 'W': |
bf12938e | 7907 | INSERT_OPERAND (FT, *ip, lastregno); |
252b5132 RH |
7908 | continue; |
7909 | ||
7910 | case 'V': | |
bf12938e | 7911 | INSERT_OPERAND (FS, *ip, lastregno); |
252b5132 RH |
7912 | continue; |
7913 | } | |
7914 | break; | |
7915 | ||
7916 | case '(': | |
7917 | /* Handle optional base register. | |
7918 | Either the base register is omitted or | |
bdaaa2e1 | 7919 | we must have a left paren. */ |
252b5132 RH |
7920 | /* This is dependent on the next operand specifier |
7921 | is a base register specification. */ | |
7922 | assert (args[1] == 'b' || args[1] == '5' | |
7923 | || args[1] == '-' || args[1] == '4'); | |
7924 | if (*s == '\0') | |
7925 | return; | |
7926 | ||
7927 | case ')': /* these must match exactly */ | |
60b63b72 RS |
7928 | case '[': |
7929 | case ']': | |
252b5132 RH |
7930 | if (*s++ == *args) |
7931 | continue; | |
7932 | break; | |
7933 | ||
af7ee8bf CD |
7934 | case '+': /* Opcode extension character. */ |
7935 | switch (*++args) | |
7936 | { | |
071742cf CD |
7937 | case 'A': /* ins/ext position, becomes LSB. */ |
7938 | limlo = 0; | |
7939 | limhi = 31; | |
5f74bc13 CD |
7940 | goto do_lsb; |
7941 | case 'E': | |
7942 | limlo = 32; | |
7943 | limhi = 63; | |
7944 | goto do_lsb; | |
7945 | do_lsb: | |
071742cf CD |
7946 | my_getExpression (&imm_expr, s); |
7947 | check_absolute_expr (ip, &imm_expr); | |
7948 | if ((unsigned long) imm_expr.X_add_number < limlo | |
7949 | || (unsigned long) imm_expr.X_add_number > limhi) | |
7950 | { | |
7951 | as_bad (_("Improper position (%lu)"), | |
7952 | (unsigned long) imm_expr.X_add_number); | |
7953 | imm_expr.X_add_number = limlo; | |
7954 | } | |
7955 | lastpos = imm_expr.X_add_number; | |
bf12938e | 7956 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); |
071742cf CD |
7957 | imm_expr.X_op = O_absent; |
7958 | s = expr_end; | |
7959 | continue; | |
7960 | ||
7961 | case 'B': /* ins size, becomes MSB. */ | |
7962 | limlo = 1; | |
7963 | limhi = 32; | |
5f74bc13 CD |
7964 | goto do_msb; |
7965 | case 'F': | |
7966 | limlo = 33; | |
7967 | limhi = 64; | |
7968 | goto do_msb; | |
7969 | do_msb: | |
071742cf CD |
7970 | my_getExpression (&imm_expr, s); |
7971 | check_absolute_expr (ip, &imm_expr); | |
7972 | /* Check for negative input so that small negative numbers | |
7973 | will not succeed incorrectly. The checks against | |
7974 | (pos+size) transitively check "size" itself, | |
7975 | assuming that "pos" is reasonable. */ | |
7976 | if ((long) imm_expr.X_add_number < 0 | |
7977 | || ((unsigned long) imm_expr.X_add_number | |
7978 | + lastpos) < limlo | |
7979 | || ((unsigned long) imm_expr.X_add_number | |
7980 | + lastpos) > limhi) | |
7981 | { | |
7982 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
7983 | (unsigned long) imm_expr.X_add_number, | |
7984 | (unsigned long) lastpos); | |
7985 | imm_expr.X_add_number = limlo - lastpos; | |
7986 | } | |
bf12938e RS |
7987 | INSERT_OPERAND (INSMSB, *ip, |
7988 | lastpos + imm_expr.X_add_number - 1); | |
071742cf CD |
7989 | imm_expr.X_op = O_absent; |
7990 | s = expr_end; | |
7991 | continue; | |
7992 | ||
7993 | case 'C': /* ext size, becomes MSBD. */ | |
7994 | limlo = 1; | |
7995 | limhi = 32; | |
5f74bc13 CD |
7996 | goto do_msbd; |
7997 | case 'G': | |
7998 | limlo = 33; | |
7999 | limhi = 64; | |
8000 | goto do_msbd; | |
8001 | case 'H': | |
8002 | limlo = 33; | |
8003 | limhi = 64; | |
8004 | goto do_msbd; | |
8005 | do_msbd: | |
071742cf CD |
8006 | my_getExpression (&imm_expr, s); |
8007 | check_absolute_expr (ip, &imm_expr); | |
8008 | /* Check for negative input so that small negative numbers | |
8009 | will not succeed incorrectly. The checks against | |
8010 | (pos+size) transitively check "size" itself, | |
8011 | assuming that "pos" is reasonable. */ | |
8012 | if ((long) imm_expr.X_add_number < 0 | |
8013 | || ((unsigned long) imm_expr.X_add_number | |
8014 | + lastpos) < limlo | |
8015 | || ((unsigned long) imm_expr.X_add_number | |
8016 | + lastpos) > limhi) | |
8017 | { | |
8018 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
8019 | (unsigned long) imm_expr.X_add_number, | |
8020 | (unsigned long) lastpos); | |
8021 | imm_expr.X_add_number = limlo - lastpos; | |
8022 | } | |
bf12938e | 8023 | INSERT_OPERAND (EXTMSBD, *ip, imm_expr.X_add_number - 1); |
071742cf CD |
8024 | imm_expr.X_op = O_absent; |
8025 | s = expr_end; | |
8026 | continue; | |
af7ee8bf | 8027 | |
bbcc0807 CD |
8028 | case 'D': |
8029 | /* +D is for disassembly only; never match. */ | |
8030 | break; | |
8031 | ||
5f74bc13 CD |
8032 | case 'I': |
8033 | /* "+I" is like "I", except that imm2_expr is used. */ | |
8034 | my_getExpression (&imm2_expr, s); | |
8035 | if (imm2_expr.X_op != O_big | |
8036 | && imm2_expr.X_op != O_constant) | |
8037 | insn_error = _("absolute expression required"); | |
13757d0c | 8038 | normalize_constant_expr (&imm2_expr); |
5f74bc13 CD |
8039 | s = expr_end; |
8040 | continue; | |
8041 | ||
af7ee8bf CD |
8042 | default: |
8043 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
8044 | *args, insn->name, insn->args); | |
8045 | /* Further processing is fruitless. */ | |
8046 | return; | |
8047 | } | |
8048 | break; | |
8049 | ||
252b5132 RH |
8050 | case '<': /* must be at least one digit */ |
8051 | /* | |
8052 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
8053 | * than 31 or less than 0, then the shift amount should be |
8054 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
8055 | * We issue a warning and mask out all but the low 5 bits. |
8056 | */ | |
8057 | my_getExpression (&imm_expr, s); | |
8058 | check_absolute_expr (ip, &imm_expr); | |
8059 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
8060 | as_warn (_("Improper shift amount (%lu)"), |
8061 | (unsigned long) imm_expr.X_add_number); | |
8062 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number); | |
252b5132 RH |
8063 | imm_expr.X_op = O_absent; |
8064 | s = expr_end; | |
8065 | continue; | |
8066 | ||
8067 | case '>': /* shift amount minus 32 */ | |
8068 | my_getExpression (&imm_expr, s); | |
8069 | check_absolute_expr (ip, &imm_expr); | |
8070 | if ((unsigned long) imm_expr.X_add_number < 32 | |
8071 | || (unsigned long) imm_expr.X_add_number > 63) | |
8072 | break; | |
bf12938e | 8073 | INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number - 32); |
252b5132 RH |
8074 | imm_expr.X_op = O_absent; |
8075 | s = expr_end; | |
8076 | continue; | |
8077 | ||
252b5132 RH |
8078 | case 'k': /* cache code */ |
8079 | case 'h': /* prefx code */ | |
8080 | my_getExpression (&imm_expr, s); | |
8081 | check_absolute_expr (ip, &imm_expr); | |
8082 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
8083 | as_warn (_("Invalid value for `%s' (%lu)"), |
8084 | ip->insn_mo->name, | |
8085 | (unsigned long) imm_expr.X_add_number); | |
252b5132 | 8086 | if (*args == 'k') |
bf12938e | 8087 | INSERT_OPERAND (CACHE, *ip, imm_expr.X_add_number); |
252b5132 | 8088 | else |
bf12938e | 8089 | INSERT_OPERAND (PREFX, *ip, imm_expr.X_add_number); |
252b5132 RH |
8090 | imm_expr.X_op = O_absent; |
8091 | s = expr_end; | |
8092 | continue; | |
8093 | ||
8094 | case 'c': /* break code */ | |
8095 | my_getExpression (&imm_expr, s); | |
8096 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 8097 | if ((unsigned long) imm_expr.X_add_number > 1023) |
bf12938e RS |
8098 | as_warn (_("Illegal break code (%lu)"), |
8099 | (unsigned long) imm_expr.X_add_number); | |
8100 | INSERT_OPERAND (CODE, *ip, imm_expr.X_add_number); | |
252b5132 RH |
8101 | imm_expr.X_op = O_absent; |
8102 | s = expr_end; | |
8103 | continue; | |
8104 | ||
8105 | case 'q': /* lower break code */ | |
8106 | my_getExpression (&imm_expr, s); | |
8107 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 8108 | if ((unsigned long) imm_expr.X_add_number > 1023) |
bf12938e RS |
8109 | as_warn (_("Illegal lower break code (%lu)"), |
8110 | (unsigned long) imm_expr.X_add_number); | |
8111 | INSERT_OPERAND (CODE2, *ip, imm_expr.X_add_number); | |
252b5132 RH |
8112 | imm_expr.X_op = O_absent; |
8113 | s = expr_end; | |
8114 | continue; | |
8115 | ||
4372b673 | 8116 | case 'B': /* 20-bit syscall/break code. */ |
156c2f8b | 8117 | my_getExpression (&imm_expr, s); |
156c2f8b | 8118 | check_absolute_expr (ip, &imm_expr); |
793b27f4 TS |
8119 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20) |
8120 | as_warn (_("Illegal 20-bit code (%lu)"), | |
8121 | (unsigned long) imm_expr.X_add_number); | |
bf12938e | 8122 | INSERT_OPERAND (CODE20, *ip, imm_expr.X_add_number); |
252b5132 RH |
8123 | imm_expr.X_op = O_absent; |
8124 | s = expr_end; | |
8125 | continue; | |
8126 | ||
98d3f06f | 8127 | case 'C': /* Coprocessor code */ |
beae10d5 | 8128 | my_getExpression (&imm_expr, s); |
252b5132 | 8129 | check_absolute_expr (ip, &imm_expr); |
98d3f06f | 8130 | if ((unsigned long) imm_expr.X_add_number >= (1 << 25)) |
252b5132 | 8131 | { |
793b27f4 TS |
8132 | as_warn (_("Coproccesor code > 25 bits (%lu)"), |
8133 | (unsigned long) imm_expr.X_add_number); | |
98d3f06f | 8134 | imm_expr.X_add_number &= ((1 << 25) - 1); |
252b5132 | 8135 | } |
beae10d5 KH |
8136 | ip->insn_opcode |= imm_expr.X_add_number; |
8137 | imm_expr.X_op = O_absent; | |
8138 | s = expr_end; | |
8139 | continue; | |
252b5132 | 8140 | |
4372b673 NC |
8141 | case 'J': /* 19-bit wait code. */ |
8142 | my_getExpression (&imm_expr, s); | |
8143 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 TS |
8144 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
8145 | as_warn (_("Illegal 19-bit code (%lu)"), | |
8146 | (unsigned long) imm_expr.X_add_number); | |
bf12938e | 8147 | INSERT_OPERAND (CODE19, *ip, imm_expr.X_add_number); |
4372b673 NC |
8148 | imm_expr.X_op = O_absent; |
8149 | s = expr_end; | |
8150 | continue; | |
8151 | ||
252b5132 | 8152 | case 'P': /* Performance register */ |
beae10d5 | 8153 | my_getExpression (&imm_expr, s); |
252b5132 | 8154 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 8155 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
bf12938e RS |
8156 | as_warn (_("Invalid performance register (%lu)"), |
8157 | (unsigned long) imm_expr.X_add_number); | |
8158 | INSERT_OPERAND (PERFREG, *ip, imm_expr.X_add_number); | |
beae10d5 KH |
8159 | imm_expr.X_op = O_absent; |
8160 | s = expr_end; | |
8161 | continue; | |
252b5132 RH |
8162 | |
8163 | case 'b': /* base register */ | |
8164 | case 'd': /* destination register */ | |
8165 | case 's': /* source register */ | |
8166 | case 't': /* target register */ | |
8167 | case 'r': /* both target and source */ | |
8168 | case 'v': /* both dest and source */ | |
8169 | case 'w': /* both dest and target */ | |
8170 | case 'E': /* coprocessor target register */ | |
8171 | case 'G': /* coprocessor destination register */ | |
af7ee8bf | 8172 | case 'K': /* 'rdhwr' destination register */ |
252b5132 RH |
8173 | case 'x': /* ignore register name */ |
8174 | case 'z': /* must be zero register */ | |
4372b673 | 8175 | case 'U': /* destination register (clo/clz). */ |
252b5132 RH |
8176 | s_reset = s; |
8177 | if (s[0] == '$') | |
8178 | { | |
8179 | ||
3882b010 | 8180 | if (ISDIGIT (s[1])) |
252b5132 RH |
8181 | { |
8182 | ++s; | |
8183 | regno = 0; | |
8184 | do | |
8185 | { | |
8186 | regno *= 10; | |
8187 | regno += *s - '0'; | |
8188 | ++s; | |
8189 | } | |
3882b010 | 8190 | while (ISDIGIT (*s)); |
252b5132 RH |
8191 | if (regno > 31) |
8192 | as_bad (_("Invalid register number (%d)"), regno); | |
8193 | } | |
af7ee8bf | 8194 | else if (*args == 'E' || *args == 'G' || *args == 'K') |
252b5132 RH |
8195 | goto notreg; |
8196 | else | |
8197 | { | |
76db943d TS |
8198 | if (s[1] == 'r' && s[2] == 'a') |
8199 | { | |
8200 | s += 3; | |
8201 | regno = RA; | |
8202 | } | |
8203 | else if (s[1] == 'f' && s[2] == 'p') | |
252b5132 RH |
8204 | { |
8205 | s += 3; | |
8206 | regno = FP; | |
8207 | } | |
8208 | else if (s[1] == 's' && s[2] == 'p') | |
8209 | { | |
8210 | s += 3; | |
8211 | regno = SP; | |
8212 | } | |
8213 | else if (s[1] == 'g' && s[2] == 'p') | |
8214 | { | |
8215 | s += 3; | |
8216 | regno = GP; | |
8217 | } | |
8218 | else if (s[1] == 'a' && s[2] == 't') | |
8219 | { | |
8220 | s += 3; | |
8221 | regno = AT; | |
8222 | } | |
8223 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
8224 | { | |
8225 | s += 4; | |
8226 | regno = KT0; | |
8227 | } | |
8228 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
8229 | { | |
8230 | s += 4; | |
8231 | regno = KT1; | |
8232 | } | |
85b51719 TS |
8233 | else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o') |
8234 | { | |
8235 | s += 5; | |
8236 | regno = ZERO; | |
8237 | } | |
252b5132 RH |
8238 | else if (itbl_have_entries) |
8239 | { | |
8240 | char *p, *n; | |
d7ba4a77 | 8241 | unsigned long r; |
252b5132 | 8242 | |
d7ba4a77 | 8243 | p = s + 1; /* advance past '$' */ |
252b5132 RH |
8244 | n = itbl_get_field (&p); /* n is name */ |
8245 | ||
d7ba4a77 ILT |
8246 | /* See if this is a register defined in an |
8247 | itbl entry. */ | |
8248 | if (itbl_get_reg_val (n, &r)) | |
252b5132 RH |
8249 | { |
8250 | /* Get_field advances to the start of | |
8251 | the next field, so we need to back | |
d7ba4a77 | 8252 | rack to the end of the last field. */ |
bdaaa2e1 | 8253 | if (p) |
252b5132 | 8254 | s = p - 1; |
bdaaa2e1 | 8255 | else |
d7ba4a77 | 8256 | s = strchr (s, '\0'); |
252b5132 RH |
8257 | regno = r; |
8258 | } | |
8259 | else | |
8260 | goto notreg; | |
beae10d5 | 8261 | } |
252b5132 RH |
8262 | else |
8263 | goto notreg; | |
8264 | } | |
8265 | if (regno == AT | |
8266 | && ! mips_opts.noat | |
8267 | && *args != 'E' | |
af7ee8bf CD |
8268 | && *args != 'G' |
8269 | && *args != 'K') | |
252b5132 RH |
8270 | as_warn (_("Used $at without \".set noat\"")); |
8271 | c = *args; | |
8272 | if (*s == ' ') | |
f9419b05 | 8273 | ++s; |
252b5132 RH |
8274 | if (args[1] != *s) |
8275 | { | |
8276 | if (c == 'r' || c == 'v' || c == 'w') | |
8277 | { | |
8278 | regno = lastregno; | |
8279 | s = s_reset; | |
f9419b05 | 8280 | ++args; |
252b5132 RH |
8281 | } |
8282 | } | |
8283 | /* 'z' only matches $0. */ | |
8284 | if (c == 'z' && regno != 0) | |
8285 | break; | |
8286 | ||
bdaaa2e1 KH |
8287 | /* Now that we have assembled one operand, we use the args string |
8288 | * to figure out where it goes in the instruction. */ | |
252b5132 RH |
8289 | switch (c) |
8290 | { | |
8291 | case 'r': | |
8292 | case 's': | |
8293 | case 'v': | |
8294 | case 'b': | |
bf12938e | 8295 | INSERT_OPERAND (RS, *ip, regno); |
252b5132 RH |
8296 | break; |
8297 | case 'd': | |
8298 | case 'G': | |
af7ee8bf | 8299 | case 'K': |
bf12938e | 8300 | INSERT_OPERAND (RD, *ip, regno); |
252b5132 | 8301 | break; |
4372b673 | 8302 | case 'U': |
bf12938e RS |
8303 | INSERT_OPERAND (RD, *ip, regno); |
8304 | INSERT_OPERAND (RT, *ip, regno); | |
4372b673 | 8305 | break; |
252b5132 RH |
8306 | case 'w': |
8307 | case 't': | |
8308 | case 'E': | |
bf12938e | 8309 | INSERT_OPERAND (RT, *ip, regno); |
252b5132 RH |
8310 | break; |
8311 | case 'x': | |
8312 | /* This case exists because on the r3000 trunc | |
8313 | expands into a macro which requires a gp | |
8314 | register. On the r6000 or r4000 it is | |
8315 | assembled into a single instruction which | |
8316 | ignores the register. Thus the insn version | |
8317 | is MIPS_ISA2 and uses 'x', and the macro | |
8318 | version is MIPS_ISA1 and uses 't'. */ | |
8319 | break; | |
8320 | case 'z': | |
8321 | /* This case is for the div instruction, which | |
8322 | acts differently if the destination argument | |
8323 | is $0. This only matches $0, and is checked | |
8324 | outside the switch. */ | |
8325 | break; | |
8326 | case 'D': | |
8327 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
8328 | break; | |
8329 | /* What about all other operands like 'i', which | |
8330 | can be specified in the opcode table? */ | |
8331 | } | |
8332 | lastregno = regno; | |
8333 | continue; | |
8334 | } | |
8335 | notreg: | |
8336 | switch (*args++) | |
8337 | { | |
8338 | case 'r': | |
8339 | case 'v': | |
bf12938e | 8340 | INSERT_OPERAND (RS, *ip, lastregno); |
252b5132 RH |
8341 | continue; |
8342 | case 'w': | |
bf12938e | 8343 | INSERT_OPERAND (RT, *ip, lastregno); |
252b5132 RH |
8344 | continue; |
8345 | } | |
8346 | break; | |
8347 | ||
deec1734 CD |
8348 | case 'O': /* MDMX alignment immediate constant. */ |
8349 | my_getExpression (&imm_expr, s); | |
8350 | check_absolute_expr (ip, &imm_expr); | |
8351 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
bf12938e RS |
8352 | as_warn ("Improper align amount (%ld), using low bits", |
8353 | (long) imm_expr.X_add_number); | |
8354 | INSERT_OPERAND (ALN, *ip, imm_expr.X_add_number); | |
deec1734 CD |
8355 | imm_expr.X_op = O_absent; |
8356 | s = expr_end; | |
8357 | continue; | |
8358 | ||
8359 | case 'Q': /* MDMX vector, element sel, or const. */ | |
8360 | if (s[0] != '$') | |
8361 | { | |
8362 | /* MDMX Immediate. */ | |
8363 | my_getExpression (&imm_expr, s); | |
8364 | check_absolute_expr (ip, &imm_expr); | |
8365 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
bf12938e RS |
8366 | as_warn (_("Invalid MDMX Immediate (%ld)"), |
8367 | (long) imm_expr.X_add_number); | |
8368 | INSERT_OPERAND (FT, *ip, imm_expr.X_add_number); | |
deec1734 CD |
8369 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) |
8370 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
8371 | else | |
8372 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
deec1734 CD |
8373 | imm_expr.X_op = O_absent; |
8374 | s = expr_end; | |
8375 | continue; | |
8376 | } | |
8377 | /* Not MDMX Immediate. Fall through. */ | |
8378 | case 'X': /* MDMX destination register. */ | |
8379 | case 'Y': /* MDMX source register. */ | |
8380 | case 'Z': /* MDMX target register. */ | |
8381 | is_mdmx = 1; | |
252b5132 RH |
8382 | case 'D': /* floating point destination register */ |
8383 | case 'S': /* floating point source register */ | |
8384 | case 'T': /* floating point target register */ | |
8385 | case 'R': /* floating point source register */ | |
8386 | case 'V': | |
8387 | case 'W': | |
8388 | s_reset = s; | |
deec1734 CD |
8389 | /* Accept $fN for FP and MDMX register numbers, and in |
8390 | addition accept $vN for MDMX register numbers. */ | |
8391 | if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2])) | |
8392 | || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v' | |
8393 | && ISDIGIT (s[2]))) | |
252b5132 RH |
8394 | { |
8395 | s += 2; | |
8396 | regno = 0; | |
8397 | do | |
8398 | { | |
8399 | regno *= 10; | |
8400 | regno += *s - '0'; | |
8401 | ++s; | |
8402 | } | |
3882b010 | 8403 | while (ISDIGIT (*s)); |
252b5132 RH |
8404 | |
8405 | if (regno > 31) | |
8406 | as_bad (_("Invalid float register number (%d)"), regno); | |
8407 | ||
8408 | if ((regno & 1) != 0 | |
ca4e0257 | 8409 | && HAVE_32BIT_FPRS |
252b5132 RH |
8410 | && ! (strcmp (str, "mtc1") == 0 |
8411 | || strcmp (str, "mfc1") == 0 | |
8412 | || strcmp (str, "lwc1") == 0 | |
8413 | || strcmp (str, "swc1") == 0 | |
8414 | || strcmp (str, "l.s") == 0 | |
8415 | || strcmp (str, "s.s") == 0)) | |
8416 | as_warn (_("Float register should be even, was %d"), | |
8417 | regno); | |
8418 | ||
8419 | c = *args; | |
8420 | if (*s == ' ') | |
f9419b05 | 8421 | ++s; |
252b5132 RH |
8422 | if (args[1] != *s) |
8423 | { | |
8424 | if (c == 'V' || c == 'W') | |
8425 | { | |
8426 | regno = lastregno; | |
8427 | s = s_reset; | |
f9419b05 | 8428 | ++args; |
252b5132 RH |
8429 | } |
8430 | } | |
8431 | switch (c) | |
8432 | { | |
8433 | case 'D': | |
deec1734 | 8434 | case 'X': |
bf12938e | 8435 | INSERT_OPERAND (FD, *ip, regno); |
252b5132 RH |
8436 | break; |
8437 | case 'V': | |
8438 | case 'S': | |
deec1734 | 8439 | case 'Y': |
bf12938e | 8440 | INSERT_OPERAND (FS, *ip, regno); |
252b5132 | 8441 | break; |
deec1734 CD |
8442 | case 'Q': |
8443 | /* This is like 'Z', but also needs to fix the MDMX | |
8444 | vector/scalar select bits. Note that the | |
8445 | scalar immediate case is handled above. */ | |
8446 | if (*s == '[') | |
8447 | { | |
8448 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
8449 | int max_el = (is_qh ? 3 : 7); | |
8450 | s++; | |
8451 | my_getExpression(&imm_expr, s); | |
8452 | check_absolute_expr (ip, &imm_expr); | |
8453 | s = expr_end; | |
8454 | if (imm_expr.X_add_number > max_el) | |
8455 | as_bad(_("Bad element selector %ld"), | |
8456 | (long) imm_expr.X_add_number); | |
8457 | imm_expr.X_add_number &= max_el; | |
8458 | ip->insn_opcode |= (imm_expr.X_add_number | |
8459 | << (OP_SH_VSEL + | |
8460 | (is_qh ? 2 : 1))); | |
01a3f561 | 8461 | imm_expr.X_op = O_absent; |
deec1734 CD |
8462 | if (*s != ']') |
8463 | as_warn(_("Expecting ']' found '%s'"), s); | |
8464 | else | |
8465 | s++; | |
8466 | } | |
8467 | else | |
8468 | { | |
8469 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) | |
8470 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
8471 | << OP_SH_VSEL); | |
8472 | else | |
8473 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
8474 | OP_SH_VSEL); | |
8475 | } | |
8476 | /* Fall through */ | |
252b5132 RH |
8477 | case 'W': |
8478 | case 'T': | |
deec1734 | 8479 | case 'Z': |
bf12938e | 8480 | INSERT_OPERAND (FT, *ip, regno); |
252b5132 RH |
8481 | break; |
8482 | case 'R': | |
bf12938e | 8483 | INSERT_OPERAND (FR, *ip, regno); |
252b5132 RH |
8484 | break; |
8485 | } | |
8486 | lastregno = regno; | |
8487 | continue; | |
8488 | } | |
8489 | ||
252b5132 RH |
8490 | switch (*args++) |
8491 | { | |
8492 | case 'V': | |
bf12938e | 8493 | INSERT_OPERAND (FS, *ip, lastregno); |
252b5132 RH |
8494 | continue; |
8495 | case 'W': | |
bf12938e | 8496 | INSERT_OPERAND (FT, *ip, lastregno); |
252b5132 RH |
8497 | continue; |
8498 | } | |
8499 | break; | |
8500 | ||
8501 | case 'I': | |
8502 | my_getExpression (&imm_expr, s); | |
8503 | if (imm_expr.X_op != O_big | |
8504 | && imm_expr.X_op != O_constant) | |
8505 | insn_error = _("absolute expression required"); | |
13757d0c | 8506 | normalize_constant_expr (&imm_expr); |
252b5132 RH |
8507 | s = expr_end; |
8508 | continue; | |
8509 | ||
8510 | case 'A': | |
8511 | my_getExpression (&offset_expr, s); | |
f6688943 | 8512 | *imm_reloc = BFD_RELOC_32; |
252b5132 RH |
8513 | s = expr_end; |
8514 | continue; | |
8515 | ||
8516 | case 'F': | |
8517 | case 'L': | |
8518 | case 'f': | |
8519 | case 'l': | |
8520 | { | |
8521 | int f64; | |
ca4e0257 | 8522 | int using_gprs; |
252b5132 RH |
8523 | char *save_in; |
8524 | char *err; | |
8525 | unsigned char temp[8]; | |
8526 | int len; | |
8527 | unsigned int length; | |
8528 | segT seg; | |
8529 | subsegT subseg; | |
8530 | char *p; | |
8531 | ||
8532 | /* These only appear as the last operand in an | |
8533 | instruction, and every instruction that accepts | |
8534 | them in any variant accepts them in all variants. | |
8535 | This means we don't have to worry about backing out | |
8536 | any changes if the instruction does not match. | |
8537 | ||
8538 | The difference between them is the size of the | |
8539 | floating point constant and where it goes. For 'F' | |
8540 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
8541 | is 32 bits. Where the constant is placed is based | |
8542 | on how the MIPS assembler does things: | |
8543 | F -- .rdata | |
8544 | L -- .lit8 | |
8545 | f -- immediate value | |
8546 | l -- .lit4 | |
8547 | ||
8548 | The .lit4 and .lit8 sections are only used if | |
8549 | permitted by the -G argument. | |
8550 | ||
ca4e0257 RS |
8551 | The code below needs to know whether the target register |
8552 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
8553 | 'F' are used with GPR-based instructions and 'l' and | |
8554 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
8555 | |
8556 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 8557 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
8558 | |
8559 | save_in = input_line_pointer; | |
8560 | input_line_pointer = s; | |
8561 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
8562 | length = len; | |
8563 | s = input_line_pointer; | |
8564 | input_line_pointer = save_in; | |
8565 | if (err != NULL && *err != '\0') | |
8566 | { | |
8567 | as_bad (_("Bad floating point constant: %s"), err); | |
8568 | memset (temp, '\0', sizeof temp); | |
8569 | length = f64 ? 8 : 4; | |
8570 | } | |
8571 | ||
156c2f8b | 8572 | assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
8573 | |
8574 | if (*args == 'f' | |
8575 | || (*args == 'l' | |
3e722fb5 | 8576 | && (g_switch_value < 4 |
252b5132 RH |
8577 | || (temp[0] == 0 && temp[1] == 0) |
8578 | || (temp[2] == 0 && temp[3] == 0)))) | |
8579 | { | |
8580 | imm_expr.X_op = O_constant; | |
8581 | if (! target_big_endian) | |
8582 | imm_expr.X_add_number = bfd_getl32 (temp); | |
8583 | else | |
8584 | imm_expr.X_add_number = bfd_getb32 (temp); | |
8585 | } | |
8586 | else if (length > 4 | |
119d663a | 8587 | && ! mips_disable_float_construction |
ca4e0257 RS |
8588 | /* Constants can only be constructed in GPRs and |
8589 | copied to FPRs if the GPRs are at least as wide | |
8590 | as the FPRs. Force the constant into memory if | |
8591 | we are using 64-bit FPRs but the GPRs are only | |
8592 | 32 bits wide. */ | |
8593 | && (using_gprs | |
8594 | || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) | |
252b5132 RH |
8595 | && ((temp[0] == 0 && temp[1] == 0) |
8596 | || (temp[2] == 0 && temp[3] == 0)) | |
8597 | && ((temp[4] == 0 && temp[5] == 0) | |
8598 | || (temp[6] == 0 && temp[7] == 0))) | |
8599 | { | |
ca4e0257 RS |
8600 | /* The value is simple enough to load with a couple of |
8601 | instructions. If using 32-bit registers, set | |
8602 | imm_expr to the high order 32 bits and offset_expr to | |
8603 | the low order 32 bits. Otherwise, set imm_expr to | |
8604 | the entire 64 bit constant. */ | |
8605 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) | |
252b5132 RH |
8606 | { |
8607 | imm_expr.X_op = O_constant; | |
8608 | offset_expr.X_op = O_constant; | |
8609 | if (! target_big_endian) | |
8610 | { | |
8611 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
8612 | offset_expr.X_add_number = bfd_getl32 (temp); | |
8613 | } | |
8614 | else | |
8615 | { | |
8616 | imm_expr.X_add_number = bfd_getb32 (temp); | |
8617 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
8618 | } | |
8619 | if (offset_expr.X_add_number == 0) | |
8620 | offset_expr.X_op = O_absent; | |
8621 | } | |
8622 | else if (sizeof (imm_expr.X_add_number) > 4) | |
8623 | { | |
8624 | imm_expr.X_op = O_constant; | |
8625 | if (! target_big_endian) | |
8626 | imm_expr.X_add_number = bfd_getl64 (temp); | |
8627 | else | |
8628 | imm_expr.X_add_number = bfd_getb64 (temp); | |
8629 | } | |
8630 | else | |
8631 | { | |
8632 | imm_expr.X_op = O_big; | |
8633 | imm_expr.X_add_number = 4; | |
8634 | if (! target_big_endian) | |
8635 | { | |
8636 | generic_bignum[0] = bfd_getl16 (temp); | |
8637 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
8638 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
8639 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
8640 | } | |
8641 | else | |
8642 | { | |
8643 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
8644 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
8645 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
8646 | generic_bignum[3] = bfd_getb16 (temp); | |
8647 | } | |
8648 | } | |
8649 | } | |
8650 | else | |
8651 | { | |
8652 | const char *newname; | |
8653 | segT new_seg; | |
8654 | ||
8655 | /* Switch to the right section. */ | |
8656 | seg = now_seg; | |
8657 | subseg = now_subseg; | |
8658 | switch (*args) | |
8659 | { | |
8660 | default: /* unused default case avoids warnings. */ | |
8661 | case 'L': | |
8662 | newname = RDATA_SECTION_NAME; | |
3e722fb5 | 8663 | if (g_switch_value >= 8) |
252b5132 RH |
8664 | newname = ".lit8"; |
8665 | break; | |
8666 | case 'F': | |
3e722fb5 | 8667 | newname = RDATA_SECTION_NAME; |
252b5132 RH |
8668 | break; |
8669 | case 'l': | |
4d0d148d | 8670 | assert (g_switch_value >= 4); |
252b5132 RH |
8671 | newname = ".lit4"; |
8672 | break; | |
8673 | } | |
8674 | new_seg = subseg_new (newname, (subsegT) 0); | |
8675 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
8676 | bfd_set_section_flags (stdoutput, new_seg, | |
8677 | (SEC_ALLOC | |
8678 | | SEC_LOAD | |
8679 | | SEC_READONLY | |
8680 | | SEC_DATA)); | |
8681 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
8682 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
8683 | && strcmp (TARGET_OS, "elf") != 0) | |
8684 | record_alignment (new_seg, 4); | |
8685 | else | |
8686 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
8687 | if (seg == now_seg) | |
8688 | as_bad (_("Can't use floating point insn in this section")); | |
8689 | ||
8690 | /* Set the argument to the current address in the | |
8691 | section. */ | |
8692 | offset_expr.X_op = O_symbol; | |
8693 | offset_expr.X_add_symbol = | |
8694 | symbol_new ("L0\001", now_seg, | |
8695 | (valueT) frag_now_fix (), frag_now); | |
8696 | offset_expr.X_add_number = 0; | |
8697 | ||
8698 | /* Put the floating point number into the section. */ | |
8699 | p = frag_more ((int) length); | |
8700 | memcpy (p, temp, length); | |
8701 | ||
8702 | /* Switch back to the original section. */ | |
8703 | subseg_set (seg, subseg); | |
8704 | } | |
8705 | } | |
8706 | continue; | |
8707 | ||
8708 | case 'i': /* 16 bit unsigned immediate */ | |
8709 | case 'j': /* 16 bit signed immediate */ | |
f6688943 | 8710 | *imm_reloc = BFD_RELOC_LO16; |
5e0116d5 | 8711 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) |
252b5132 RH |
8712 | { |
8713 | int more; | |
5e0116d5 RS |
8714 | offsetT minval, maxval; |
8715 | ||
8716 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] | |
8717 | && strcmp (insn->name, insn[1].name) == 0); | |
8718 | ||
8719 | /* If the expression was written as an unsigned number, | |
8720 | only treat it as signed if there are no more | |
8721 | alternatives. */ | |
8722 | if (more | |
8723 | && *args == 'j' | |
8724 | && sizeof (imm_expr.X_add_number) <= 4 | |
8725 | && imm_expr.X_op == O_constant | |
8726 | && imm_expr.X_add_number < 0 | |
8727 | && imm_expr.X_unsigned | |
8728 | && HAVE_64BIT_GPRS) | |
8729 | break; | |
8730 | ||
8731 | /* For compatibility with older assemblers, we accept | |
8732 | 0x8000-0xffff as signed 16-bit numbers when only | |
8733 | signed numbers are allowed. */ | |
8734 | if (*args == 'i') | |
8735 | minval = 0, maxval = 0xffff; | |
8736 | else if (more) | |
8737 | minval = -0x8000, maxval = 0x7fff; | |
252b5132 | 8738 | else |
5e0116d5 RS |
8739 | minval = -0x8000, maxval = 0xffff; |
8740 | ||
8741 | if (imm_expr.X_op != O_constant | |
8742 | || imm_expr.X_add_number < minval | |
8743 | || imm_expr.X_add_number > maxval) | |
252b5132 RH |
8744 | { |
8745 | if (more) | |
8746 | break; | |
2ae7e77b AH |
8747 | if (imm_expr.X_op == O_constant |
8748 | || imm_expr.X_op == O_big) | |
5e0116d5 | 8749 | as_bad (_("expression out of range")); |
252b5132 RH |
8750 | } |
8751 | } | |
8752 | s = expr_end; | |
8753 | continue; | |
8754 | ||
8755 | case 'o': /* 16 bit offset */ | |
5e0116d5 RS |
8756 | /* Check whether there is only a single bracketed expression |
8757 | left. If so, it must be the base register and the | |
8758 | constant must be zero. */ | |
8759 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
8760 | { | |
8761 | offset_expr.X_op = O_constant; | |
8762 | offset_expr.X_add_number = 0; | |
8763 | continue; | |
8764 | } | |
252b5132 RH |
8765 | |
8766 | /* If this value won't fit into a 16 bit offset, then go | |
8767 | find a macro that will generate the 32 bit offset | |
afdbd6d0 | 8768 | code pattern. */ |
5e0116d5 | 8769 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 |
252b5132 RH |
8770 | && (offset_expr.X_op != O_constant |
8771 | || offset_expr.X_add_number >= 0x8000 | |
afdbd6d0 | 8772 | || offset_expr.X_add_number < -0x8000)) |
252b5132 RH |
8773 | break; |
8774 | ||
252b5132 RH |
8775 | s = expr_end; |
8776 | continue; | |
8777 | ||
8778 | case 'p': /* pc relative offset */ | |
0b25d3e6 | 8779 | *offset_reloc = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
8780 | my_getExpression (&offset_expr, s); |
8781 | s = expr_end; | |
8782 | continue; | |
8783 | ||
8784 | case 'u': /* upper 16 bits */ | |
5e0116d5 RS |
8785 | if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 |
8786 | && imm_expr.X_op == O_constant | |
8787 | && (imm_expr.X_add_number < 0 | |
8788 | || imm_expr.X_add_number >= 0x10000)) | |
252b5132 RH |
8789 | as_bad (_("lui expression not in range 0..65535")); |
8790 | s = expr_end; | |
8791 | continue; | |
8792 | ||
8793 | case 'a': /* 26 bit address */ | |
8794 | my_getExpression (&offset_expr, s); | |
8795 | s = expr_end; | |
f6688943 | 8796 | *offset_reloc = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
8797 | continue; |
8798 | ||
8799 | case 'N': /* 3 bit branch condition code */ | |
8800 | case 'M': /* 3 bit compare condition code */ | |
8801 | if (strncmp (s, "$fcc", 4) != 0) | |
8802 | break; | |
8803 | s += 4; | |
8804 | regno = 0; | |
8805 | do | |
8806 | { | |
8807 | regno *= 10; | |
8808 | regno += *s - '0'; | |
8809 | ++s; | |
8810 | } | |
3882b010 | 8811 | while (ISDIGIT (*s)); |
252b5132 | 8812 | if (regno > 7) |
30c378fd CD |
8813 | as_bad (_("Invalid condition code register $fcc%d"), regno); |
8814 | if ((strcmp(str + strlen(str) - 3, ".ps") == 0 | |
8815 | || strcmp(str + strlen(str) - 5, "any2f") == 0 | |
8816 | || strcmp(str + strlen(str) - 5, "any2t") == 0) | |
8817 | && (regno & 1) != 0) | |
8818 | as_warn(_("Condition code register should be even for %s, was %d"), | |
8819 | str, regno); | |
8820 | if ((strcmp(str + strlen(str) - 5, "any4f") == 0 | |
8821 | || strcmp(str + strlen(str) - 5, "any4t") == 0) | |
8822 | && (regno & 3) != 0) | |
8823 | as_warn(_("Condition code register should be 0 or 4 for %s, was %d"), | |
8824 | str, regno); | |
252b5132 | 8825 | if (*args == 'N') |
bf12938e | 8826 | INSERT_OPERAND (BCC, *ip, regno); |
252b5132 | 8827 | else |
bf12938e | 8828 | INSERT_OPERAND (CCC, *ip, regno); |
beae10d5 | 8829 | continue; |
252b5132 | 8830 | |
156c2f8b NC |
8831 | case 'H': |
8832 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
8833 | s += 2; | |
3882b010 | 8834 | if (ISDIGIT (*s)) |
156c2f8b NC |
8835 | { |
8836 | c = 0; | |
8837 | do | |
8838 | { | |
8839 | c *= 10; | |
8840 | c += *s - '0'; | |
8841 | ++s; | |
8842 | } | |
3882b010 | 8843 | while (ISDIGIT (*s)); |
156c2f8b NC |
8844 | } |
8845 | else | |
8846 | c = 8; /* Invalid sel value. */ | |
8847 | ||
8848 | if (c > 7) | |
8849 | as_bad (_("invalid coprocessor sub-selection value (0-7)")); | |
8850 | ip->insn_opcode |= c; | |
8851 | continue; | |
8852 | ||
60b63b72 RS |
8853 | case 'e': |
8854 | /* Must be at least one digit. */ | |
8855 | my_getExpression (&imm_expr, s); | |
8856 | check_absolute_expr (ip, &imm_expr); | |
8857 | ||
8858 | if ((unsigned long) imm_expr.X_add_number | |
8859 | > (unsigned long) OP_MASK_VECBYTE) | |
8860 | { | |
8861 | as_bad (_("bad byte vector index (%ld)"), | |
8862 | (long) imm_expr.X_add_number); | |
8863 | imm_expr.X_add_number = 0; | |
8864 | } | |
8865 | ||
bf12938e | 8866 | INSERT_OPERAND (VECBYTE, *ip, imm_expr.X_add_number); |
60b63b72 RS |
8867 | imm_expr.X_op = O_absent; |
8868 | s = expr_end; | |
8869 | continue; | |
8870 | ||
8871 | case '%': | |
8872 | my_getExpression (&imm_expr, s); | |
8873 | check_absolute_expr (ip, &imm_expr); | |
8874 | ||
8875 | if ((unsigned long) imm_expr.X_add_number | |
8876 | > (unsigned long) OP_MASK_VECALIGN) | |
8877 | { | |
8878 | as_bad (_("bad byte vector index (%ld)"), | |
8879 | (long) imm_expr.X_add_number); | |
8880 | imm_expr.X_add_number = 0; | |
8881 | } | |
8882 | ||
bf12938e | 8883 | INSERT_OPERAND (VECALIGN, *ip, imm_expr.X_add_number); |
60b63b72 RS |
8884 | imm_expr.X_op = O_absent; |
8885 | s = expr_end; | |
8886 | continue; | |
8887 | ||
252b5132 RH |
8888 | default: |
8889 | as_bad (_("bad char = '%c'\n"), *args); | |
8890 | internalError (); | |
8891 | } | |
8892 | break; | |
8893 | } | |
8894 | /* Args don't match. */ | |
8895 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
8896 | !strcmp (insn->name, insn[1].name)) | |
8897 | { | |
8898 | ++insn; | |
8899 | s = argsStart; | |
268f6bed | 8900 | insn_error = _("illegal operands"); |
252b5132 RH |
8901 | continue; |
8902 | } | |
268f6bed L |
8903 | if (save_c) |
8904 | *(--s) = save_c; | |
252b5132 RH |
8905 | insn_error = _("illegal operands"); |
8906 | return; | |
8907 | } | |
8908 | } | |
8909 | ||
8910 | /* This routine assembles an instruction into its binary format when | |
8911 | assembling for the mips16. As a side effect, it sets one of the | |
8912 | global variables imm_reloc or offset_reloc to the type of | |
8913 | relocation to do if one of the operands is an address expression. | |
8914 | It also sets mips16_small and mips16_ext if the user explicitly | |
8915 | requested a small or extended instruction. */ | |
8916 | ||
8917 | static void | |
17a2f251 | 8918 | mips16_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
8919 | { |
8920 | char *s; | |
8921 | const char *args; | |
8922 | struct mips_opcode *insn; | |
8923 | char *argsstart; | |
8924 | unsigned int regno; | |
8925 | unsigned int lastregno = 0; | |
8926 | char *s_reset; | |
d6f16593 | 8927 | size_t i; |
252b5132 RH |
8928 | |
8929 | insn_error = NULL; | |
8930 | ||
b34976b6 AM |
8931 | mips16_small = FALSE; |
8932 | mips16_ext = FALSE; | |
252b5132 | 8933 | |
3882b010 | 8934 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
8935 | ; |
8936 | switch (*s) | |
8937 | { | |
8938 | case '\0': | |
8939 | break; | |
8940 | ||
8941 | case ' ': | |
8942 | *s++ = '\0'; | |
8943 | break; | |
8944 | ||
8945 | case '.': | |
8946 | if (s[1] == 't' && s[2] == ' ') | |
8947 | { | |
8948 | *s = '\0'; | |
b34976b6 | 8949 | mips16_small = TRUE; |
252b5132 RH |
8950 | s += 3; |
8951 | break; | |
8952 | } | |
8953 | else if (s[1] == 'e' && s[2] == ' ') | |
8954 | { | |
8955 | *s = '\0'; | |
b34976b6 | 8956 | mips16_ext = TRUE; |
252b5132 RH |
8957 | s += 3; |
8958 | break; | |
8959 | } | |
8960 | /* Fall through. */ | |
8961 | default: | |
8962 | insn_error = _("unknown opcode"); | |
8963 | return; | |
8964 | } | |
8965 | ||
8966 | if (mips_opts.noautoextend && ! mips16_ext) | |
b34976b6 | 8967 | mips16_small = TRUE; |
252b5132 RH |
8968 | |
8969 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
8970 | { | |
8971 | insn_error = _("unrecognized opcode"); | |
8972 | return; | |
8973 | } | |
8974 | ||
8975 | argsstart = s; | |
8976 | for (;;) | |
8977 | { | |
8978 | assert (strcmp (insn->name, str) == 0); | |
8979 | ||
1e915849 | 8980 | create_insn (ip, insn); |
252b5132 | 8981 | imm_expr.X_op = O_absent; |
f6688943 TS |
8982 | imm_reloc[0] = BFD_RELOC_UNUSED; |
8983 | imm_reloc[1] = BFD_RELOC_UNUSED; | |
8984 | imm_reloc[2] = BFD_RELOC_UNUSED; | |
5f74bc13 | 8985 | imm2_expr.X_op = O_absent; |
252b5132 | 8986 | offset_expr.X_op = O_absent; |
f6688943 TS |
8987 | offset_reloc[0] = BFD_RELOC_UNUSED; |
8988 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
8989 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
8990 | for (args = insn->args; 1; ++args) |
8991 | { | |
8992 | int c; | |
8993 | ||
8994 | if (*s == ' ') | |
8995 | ++s; | |
8996 | ||
8997 | /* In this switch statement we call break if we did not find | |
8998 | a match, continue if we did find a match, or return if we | |
8999 | are done. */ | |
9000 | ||
9001 | c = *args; | |
9002 | switch (c) | |
9003 | { | |
9004 | case '\0': | |
9005 | if (*s == '\0') | |
9006 | { | |
9007 | /* Stuff the immediate value in now, if we can. */ | |
9008 | if (imm_expr.X_op == O_constant | |
f6688943 | 9009 | && *imm_reloc > BFD_RELOC_UNUSED |
252b5132 RH |
9010 | && insn->pinfo != INSN_MACRO) |
9011 | { | |
d6f16593 MR |
9012 | valueT tmp; |
9013 | ||
9014 | switch (*offset_reloc) | |
9015 | { | |
9016 | case BFD_RELOC_MIPS16_HI16_S: | |
9017 | tmp = (imm_expr.X_add_number + 0x8000) >> 16; | |
9018 | break; | |
9019 | ||
9020 | case BFD_RELOC_MIPS16_HI16: | |
9021 | tmp = imm_expr.X_add_number >> 16; | |
9022 | break; | |
9023 | ||
9024 | case BFD_RELOC_MIPS16_LO16: | |
9025 | tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff) | |
9026 | - 0x8000; | |
9027 | break; | |
9028 | ||
9029 | case BFD_RELOC_UNUSED: | |
9030 | tmp = imm_expr.X_add_number; | |
9031 | break; | |
9032 | ||
9033 | default: | |
9034 | internalError (); | |
9035 | } | |
9036 | *offset_reloc = BFD_RELOC_UNUSED; | |
9037 | ||
c4e7957c | 9038 | mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, |
d6f16593 | 9039 | tmp, TRUE, mips16_small, |
252b5132 RH |
9040 | mips16_ext, &ip->insn_opcode, |
9041 | &ip->use_extend, &ip->extend); | |
9042 | imm_expr.X_op = O_absent; | |
f6688943 | 9043 | *imm_reloc = BFD_RELOC_UNUSED; |
252b5132 RH |
9044 | } |
9045 | ||
9046 | return; | |
9047 | } | |
9048 | break; | |
9049 | ||
9050 | case ',': | |
9051 | if (*s++ == c) | |
9052 | continue; | |
9053 | s--; | |
9054 | switch (*++args) | |
9055 | { | |
9056 | case 'v': | |
bf12938e | 9057 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 RH |
9058 | continue; |
9059 | case 'w': | |
bf12938e | 9060 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
9061 | continue; |
9062 | } | |
9063 | break; | |
9064 | ||
9065 | case '(': | |
9066 | case ')': | |
9067 | if (*s++ == c) | |
9068 | continue; | |
9069 | break; | |
9070 | ||
9071 | case 'v': | |
9072 | case 'w': | |
9073 | if (s[0] != '$') | |
9074 | { | |
9075 | if (c == 'v') | |
bf12938e | 9076 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 | 9077 | else |
bf12938e | 9078 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
9079 | ++args; |
9080 | continue; | |
9081 | } | |
9082 | /* Fall through. */ | |
9083 | case 'x': | |
9084 | case 'y': | |
9085 | case 'z': | |
9086 | case 'Z': | |
9087 | case '0': | |
9088 | case 'S': | |
9089 | case 'R': | |
9090 | case 'X': | |
9091 | case 'Y': | |
9092 | if (s[0] != '$') | |
9093 | break; | |
9094 | s_reset = s; | |
3882b010 | 9095 | if (ISDIGIT (s[1])) |
252b5132 RH |
9096 | { |
9097 | ++s; | |
9098 | regno = 0; | |
9099 | do | |
9100 | { | |
9101 | regno *= 10; | |
9102 | regno += *s - '0'; | |
9103 | ++s; | |
9104 | } | |
3882b010 | 9105 | while (ISDIGIT (*s)); |
252b5132 RH |
9106 | if (regno > 31) |
9107 | { | |
9108 | as_bad (_("invalid register number (%d)"), regno); | |
9109 | regno = 2; | |
9110 | } | |
9111 | } | |
9112 | else | |
9113 | { | |
76db943d TS |
9114 | if (s[1] == 'r' && s[2] == 'a') |
9115 | { | |
9116 | s += 3; | |
9117 | regno = RA; | |
9118 | } | |
9119 | else if (s[1] == 'f' && s[2] == 'p') | |
252b5132 RH |
9120 | { |
9121 | s += 3; | |
9122 | regno = FP; | |
9123 | } | |
9124 | else if (s[1] == 's' && s[2] == 'p') | |
9125 | { | |
9126 | s += 3; | |
9127 | regno = SP; | |
9128 | } | |
9129 | else if (s[1] == 'g' && s[2] == 'p') | |
9130 | { | |
9131 | s += 3; | |
9132 | regno = GP; | |
9133 | } | |
9134 | else if (s[1] == 'a' && s[2] == 't') | |
9135 | { | |
9136 | s += 3; | |
9137 | regno = AT; | |
9138 | } | |
9139 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
9140 | { | |
9141 | s += 4; | |
9142 | regno = KT0; | |
9143 | } | |
9144 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
9145 | { | |
9146 | s += 4; | |
9147 | regno = KT1; | |
9148 | } | |
85b51719 TS |
9149 | else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o') |
9150 | { | |
9151 | s += 5; | |
9152 | regno = ZERO; | |
9153 | } | |
252b5132 RH |
9154 | else |
9155 | break; | |
9156 | } | |
9157 | ||
9158 | if (*s == ' ') | |
9159 | ++s; | |
9160 | if (args[1] != *s) | |
9161 | { | |
9162 | if (c == 'v' || c == 'w') | |
9163 | { | |
9164 | regno = mips16_to_32_reg_map[lastregno]; | |
9165 | s = s_reset; | |
f9419b05 | 9166 | ++args; |
252b5132 RH |
9167 | } |
9168 | } | |
9169 | ||
9170 | switch (c) | |
9171 | { | |
9172 | case 'x': | |
9173 | case 'y': | |
9174 | case 'z': | |
9175 | case 'v': | |
9176 | case 'w': | |
9177 | case 'Z': | |
9178 | regno = mips32_to_16_reg_map[regno]; | |
9179 | break; | |
9180 | ||
9181 | case '0': | |
9182 | if (regno != 0) | |
9183 | regno = ILLEGAL_REG; | |
9184 | break; | |
9185 | ||
9186 | case 'S': | |
9187 | if (regno != SP) | |
9188 | regno = ILLEGAL_REG; | |
9189 | break; | |
9190 | ||
9191 | case 'R': | |
9192 | if (regno != RA) | |
9193 | regno = ILLEGAL_REG; | |
9194 | break; | |
9195 | ||
9196 | case 'X': | |
9197 | case 'Y': | |
9198 | if (regno == AT && ! mips_opts.noat) | |
9199 | as_warn (_("used $at without \".set noat\"")); | |
9200 | break; | |
9201 | ||
9202 | default: | |
9203 | internalError (); | |
9204 | } | |
9205 | ||
9206 | if (regno == ILLEGAL_REG) | |
9207 | break; | |
9208 | ||
9209 | switch (c) | |
9210 | { | |
9211 | case 'x': | |
9212 | case 'v': | |
bf12938e | 9213 | MIPS16_INSERT_OPERAND (RX, *ip, regno); |
252b5132 RH |
9214 | break; |
9215 | case 'y': | |
9216 | case 'w': | |
bf12938e | 9217 | MIPS16_INSERT_OPERAND (RY, *ip, regno); |
252b5132 RH |
9218 | break; |
9219 | case 'z': | |
bf12938e | 9220 | MIPS16_INSERT_OPERAND (RZ, *ip, regno); |
252b5132 RH |
9221 | break; |
9222 | case 'Z': | |
bf12938e | 9223 | MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno); |
252b5132 RH |
9224 | case '0': |
9225 | case 'S': | |
9226 | case 'R': | |
9227 | break; | |
9228 | case 'X': | |
bf12938e | 9229 | MIPS16_INSERT_OPERAND (REGR32, *ip, regno); |
252b5132 RH |
9230 | break; |
9231 | case 'Y': | |
9232 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
bf12938e | 9233 | MIPS16_INSERT_OPERAND (REG32R, *ip, regno); |
252b5132 RH |
9234 | break; |
9235 | default: | |
9236 | internalError (); | |
9237 | } | |
9238 | ||
9239 | lastregno = regno; | |
9240 | continue; | |
9241 | ||
9242 | case 'P': | |
9243 | if (strncmp (s, "$pc", 3) == 0) | |
9244 | { | |
9245 | s += 3; | |
9246 | continue; | |
9247 | } | |
9248 | break; | |
9249 | ||
252b5132 RH |
9250 | case '5': |
9251 | case 'H': | |
9252 | case 'W': | |
9253 | case 'D': | |
9254 | case 'j': | |
252b5132 RH |
9255 | case 'V': |
9256 | case 'C': | |
9257 | case 'U': | |
9258 | case 'k': | |
9259 | case 'K': | |
d6f16593 MR |
9260 | i = my_getSmallExpression (&imm_expr, imm_reloc, s); |
9261 | if (i > 0) | |
252b5132 | 9262 | { |
d6f16593 | 9263 | if (imm_expr.X_op != O_constant) |
252b5132 | 9264 | { |
b34976b6 | 9265 | mips16_ext = TRUE; |
b34976b6 | 9266 | ip->use_extend = TRUE; |
252b5132 | 9267 | ip->extend = 0; |
252b5132 | 9268 | } |
d6f16593 MR |
9269 | else |
9270 | { | |
9271 | /* We need to relax this instruction. */ | |
9272 | *offset_reloc = *imm_reloc; | |
9273 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
9274 | } | |
9275 | s = expr_end; | |
9276 | continue; | |
252b5132 | 9277 | } |
d6f16593 MR |
9278 | *imm_reloc = BFD_RELOC_UNUSED; |
9279 | /* Fall through. */ | |
9280 | case '<': | |
9281 | case '>': | |
9282 | case '[': | |
9283 | case ']': | |
9284 | case '4': | |
9285 | case '8': | |
9286 | my_getExpression (&imm_expr, s); | |
252b5132 RH |
9287 | if (imm_expr.X_op == O_register) |
9288 | { | |
9289 | /* What we thought was an expression turned out to | |
9290 | be a register. */ | |
9291 | ||
9292 | if (s[0] == '(' && args[1] == '(') | |
9293 | { | |
9294 | /* It looks like the expression was omitted | |
9295 | before a register indirection, which means | |
9296 | that the expression is implicitly zero. We | |
9297 | still set up imm_expr, so that we handle | |
9298 | explicit extensions correctly. */ | |
9299 | imm_expr.X_op = O_constant; | |
9300 | imm_expr.X_add_number = 0; | |
f6688943 | 9301 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9302 | continue; |
9303 | } | |
9304 | ||
9305 | break; | |
9306 | } | |
9307 | ||
9308 | /* We need to relax this instruction. */ | |
f6688943 | 9309 | *imm_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9310 | s = expr_end; |
9311 | continue; | |
9312 | ||
9313 | case 'p': | |
9314 | case 'q': | |
9315 | case 'A': | |
9316 | case 'B': | |
9317 | case 'E': | |
9318 | /* We use offset_reloc rather than imm_reloc for the PC | |
9319 | relative operands. This lets macros with both | |
9320 | immediate and address operands work correctly. */ | |
9321 | my_getExpression (&offset_expr, s); | |
9322 | ||
9323 | if (offset_expr.X_op == O_register) | |
9324 | break; | |
9325 | ||
9326 | /* We need to relax this instruction. */ | |
f6688943 | 9327 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
252b5132 RH |
9328 | s = expr_end; |
9329 | continue; | |
9330 | ||
9331 | case '6': /* break code */ | |
9332 | my_getExpression (&imm_expr, s); | |
9333 | check_absolute_expr (ip, &imm_expr); | |
9334 | if ((unsigned long) imm_expr.X_add_number > 63) | |
bf12938e RS |
9335 | as_warn (_("Invalid value for `%s' (%lu)"), |
9336 | ip->insn_mo->name, | |
9337 | (unsigned long) imm_expr.X_add_number); | |
9338 | MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number); | |
252b5132 RH |
9339 | imm_expr.X_op = O_absent; |
9340 | s = expr_end; | |
9341 | continue; | |
9342 | ||
9343 | case 'a': /* 26 bit address */ | |
9344 | my_getExpression (&offset_expr, s); | |
9345 | s = expr_end; | |
f6688943 | 9346 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
9347 | ip->insn_opcode <<= 16; |
9348 | continue; | |
9349 | ||
9350 | case 'l': /* register list for entry macro */ | |
9351 | case 'L': /* register list for exit macro */ | |
9352 | { | |
9353 | int mask; | |
9354 | ||
9355 | if (c == 'l') | |
9356 | mask = 0; | |
9357 | else | |
9358 | mask = 7 << 3; | |
9359 | while (*s != '\0') | |
9360 | { | |
9361 | int freg, reg1, reg2; | |
9362 | ||
9363 | while (*s == ' ' || *s == ',') | |
9364 | ++s; | |
9365 | if (*s != '$') | |
9366 | { | |
9367 | as_bad (_("can't parse register list")); | |
9368 | break; | |
9369 | } | |
9370 | ++s; | |
9371 | if (*s != 'f') | |
9372 | freg = 0; | |
9373 | else | |
9374 | { | |
9375 | freg = 1; | |
9376 | ++s; | |
9377 | } | |
9378 | reg1 = 0; | |
3882b010 | 9379 | while (ISDIGIT (*s)) |
252b5132 RH |
9380 | { |
9381 | reg1 *= 10; | |
9382 | reg1 += *s - '0'; | |
9383 | ++s; | |
9384 | } | |
9385 | if (*s == ' ') | |
9386 | ++s; | |
9387 | if (*s != '-') | |
9388 | reg2 = reg1; | |
9389 | else | |
9390 | { | |
9391 | ++s; | |
9392 | if (*s != '$') | |
9393 | break; | |
9394 | ++s; | |
9395 | if (freg) | |
9396 | { | |
9397 | if (*s == 'f') | |
9398 | ++s; | |
9399 | else | |
9400 | { | |
9401 | as_bad (_("invalid register list")); | |
9402 | break; | |
9403 | } | |
9404 | } | |
9405 | reg2 = 0; | |
3882b010 | 9406 | while (ISDIGIT (*s)) |
252b5132 RH |
9407 | { |
9408 | reg2 *= 10; | |
9409 | reg2 += *s - '0'; | |
9410 | ++s; | |
9411 | } | |
9412 | } | |
9413 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
9414 | { | |
9415 | mask &= ~ (7 << 3); | |
9416 | mask |= 5 << 3; | |
9417 | } | |
9418 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
9419 | { | |
9420 | mask &= ~ (7 << 3); | |
9421 | mask |= 6 << 3; | |
9422 | } | |
9423 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
9424 | mask |= (reg2 - 3) << 3; | |
9425 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
9426 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 9427 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
9428 | mask |= 1; |
9429 | else | |
9430 | { | |
9431 | as_bad (_("invalid register list")); | |
9432 | break; | |
9433 | } | |
9434 | } | |
9435 | /* The mask is filled in in the opcode table for the | |
9436 | benefit of the disassembler. We remove it before | |
9437 | applying the actual mask. */ | |
9438 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
9439 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
9440 | } | |
9441 | continue; | |
9442 | ||
9443 | case 'e': /* extend code */ | |
9444 | my_getExpression (&imm_expr, s); | |
9445 | check_absolute_expr (ip, &imm_expr); | |
9446 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
9447 | { | |
9448 | as_warn (_("Invalid value for `%s' (%lu)"), | |
9449 | ip->insn_mo->name, | |
9450 | (unsigned long) imm_expr.X_add_number); | |
9451 | imm_expr.X_add_number &= 0x7ff; | |
9452 | } | |
9453 | ip->insn_opcode |= imm_expr.X_add_number; | |
9454 | imm_expr.X_op = O_absent; | |
9455 | s = expr_end; | |
9456 | continue; | |
9457 | ||
9458 | default: | |
9459 | internalError (); | |
9460 | } | |
9461 | break; | |
9462 | } | |
9463 | ||
9464 | /* Args don't match. */ | |
9465 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
9466 | strcmp (insn->name, insn[1].name) == 0) | |
9467 | { | |
9468 | ++insn; | |
9469 | s = argsstart; | |
9470 | continue; | |
9471 | } | |
9472 | ||
9473 | insn_error = _("illegal operands"); | |
9474 | ||
9475 | return; | |
9476 | } | |
9477 | } | |
9478 | ||
9479 | /* This structure holds information we know about a mips16 immediate | |
9480 | argument type. */ | |
9481 | ||
e972090a NC |
9482 | struct mips16_immed_operand |
9483 | { | |
252b5132 RH |
9484 | /* The type code used in the argument string in the opcode table. */ |
9485 | int type; | |
9486 | /* The number of bits in the short form of the opcode. */ | |
9487 | int nbits; | |
9488 | /* The number of bits in the extended form of the opcode. */ | |
9489 | int extbits; | |
9490 | /* The amount by which the short form is shifted when it is used; | |
9491 | for example, the sw instruction has a shift count of 2. */ | |
9492 | int shift; | |
9493 | /* The amount by which the short form is shifted when it is stored | |
9494 | into the instruction code. */ | |
9495 | int op_shift; | |
9496 | /* Non-zero if the short form is unsigned. */ | |
9497 | int unsp; | |
9498 | /* Non-zero if the extended form is unsigned. */ | |
9499 | int extu; | |
9500 | /* Non-zero if the value is PC relative. */ | |
9501 | int pcrel; | |
9502 | }; | |
9503 | ||
9504 | /* The mips16 immediate operand types. */ | |
9505 | ||
9506 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
9507 | { | |
9508 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
9509 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
9510 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
9511 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
9512 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
9513 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9514 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9515 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9516 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
9517 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
9518 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9519 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9520 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
9521 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
9522 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
9523 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
9524 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
9525 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
9526 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
9527 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
9528 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
9529 | }; | |
9530 | ||
9531 | #define MIPS16_NUM_IMMED \ | |
9532 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
9533 | ||
9534 | /* Handle a mips16 instruction with an immediate value. This or's the | |
9535 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
9536 | whether an extended value is needed; if one is needed, it sets | |
9537 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
9538 | If SMALL is true, an unextended opcode was explicitly requested. | |
9539 | If EXT is true, an extended opcode was explicitly requested. If | |
9540 | WARN is true, warn if EXT does not match reality. */ | |
9541 | ||
9542 | static void | |
17a2f251 TS |
9543 | mips16_immed (char *file, unsigned int line, int type, offsetT val, |
9544 | bfd_boolean warn, bfd_boolean small, bfd_boolean ext, | |
9545 | unsigned long *insn, bfd_boolean *use_extend, | |
9546 | unsigned short *extend) | |
252b5132 RH |
9547 | { |
9548 | register const struct mips16_immed_operand *op; | |
9549 | int mintiny, maxtiny; | |
b34976b6 | 9550 | bfd_boolean needext; |
252b5132 RH |
9551 | |
9552 | op = mips16_immed_operands; | |
9553 | while (op->type != type) | |
9554 | { | |
9555 | ++op; | |
9556 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
9557 | } | |
9558 | ||
9559 | if (op->unsp) | |
9560 | { | |
9561 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
9562 | { | |
9563 | mintiny = 1; | |
9564 | maxtiny = 1 << op->nbits; | |
9565 | } | |
9566 | else | |
9567 | { | |
9568 | mintiny = 0; | |
9569 | maxtiny = (1 << op->nbits) - 1; | |
9570 | } | |
9571 | } | |
9572 | else | |
9573 | { | |
9574 | mintiny = - (1 << (op->nbits - 1)); | |
9575 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
9576 | } | |
9577 | ||
9578 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
9579 | if (type == 'p' || type == 'q') | |
9580 | val /= 2; | |
9581 | ||
9582 | if ((val & ((1 << op->shift) - 1)) != 0 | |
9583 | || val < (mintiny << op->shift) | |
9584 | || val > (maxtiny << op->shift)) | |
b34976b6 | 9585 | needext = TRUE; |
252b5132 | 9586 | else |
b34976b6 | 9587 | needext = FALSE; |
252b5132 RH |
9588 | |
9589 | if (warn && ext && ! needext) | |
beae10d5 KH |
9590 | as_warn_where (file, line, |
9591 | _("extended operand requested but not required")); | |
252b5132 RH |
9592 | if (small && needext) |
9593 | as_bad_where (file, line, _("invalid unextended operand value")); | |
9594 | ||
9595 | if (small || (! ext && ! needext)) | |
9596 | { | |
9597 | int insnval; | |
9598 | ||
b34976b6 | 9599 | *use_extend = FALSE; |
252b5132 RH |
9600 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
9601 | insnval <<= op->op_shift; | |
9602 | *insn |= insnval; | |
9603 | } | |
9604 | else | |
9605 | { | |
9606 | long minext, maxext; | |
9607 | int extval; | |
9608 | ||
9609 | if (op->extu) | |
9610 | { | |
9611 | minext = 0; | |
9612 | maxext = (1 << op->extbits) - 1; | |
9613 | } | |
9614 | else | |
9615 | { | |
9616 | minext = - (1 << (op->extbits - 1)); | |
9617 | maxext = (1 << (op->extbits - 1)) - 1; | |
9618 | } | |
9619 | if (val < minext || val > maxext) | |
9620 | as_bad_where (file, line, | |
9621 | _("operand value out of range for instruction")); | |
9622 | ||
b34976b6 | 9623 | *use_extend = TRUE; |
252b5132 RH |
9624 | if (op->extbits == 16) |
9625 | { | |
9626 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
9627 | val &= 0x1f; | |
9628 | } | |
9629 | else if (op->extbits == 15) | |
9630 | { | |
9631 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
9632 | val &= 0xf; | |
9633 | } | |
9634 | else | |
9635 | { | |
9636 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
9637 | val = 0; | |
9638 | } | |
9639 | ||
9640 | *extend = (unsigned short) extval; | |
9641 | *insn |= val; | |
9642 | } | |
9643 | } | |
9644 | \f | |
d6f16593 | 9645 | struct percent_op_match |
ad8d3bb3 | 9646 | { |
5e0116d5 RS |
9647 | const char *str; |
9648 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
9649 | }; |
9650 | ||
9651 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 9652 | { |
5e0116d5 | 9653 | {"%lo", BFD_RELOC_LO16}, |
ad8d3bb3 | 9654 | #ifdef OBJ_ELF |
5e0116d5 RS |
9655 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
9656 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
9657 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
9658 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
9659 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
9660 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
9661 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
9662 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
9663 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
9664 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
9665 | {"%half", BFD_RELOC_16}, | |
9666 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
9667 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
9668 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
9669 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
9670 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
9671 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
9672 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
9673 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
9674 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
9675 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
ad8d3bb3 | 9676 | #endif |
5e0116d5 | 9677 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
9678 | }; |
9679 | ||
d6f16593 MR |
9680 | static const struct percent_op_match mips16_percent_op[] = |
9681 | { | |
9682 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
9683 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, | |
9684 | {"%hi", BFD_RELOC_MIPS16_HI16_S} | |
9685 | }; | |
9686 | ||
252b5132 | 9687 | |
5e0116d5 RS |
9688 | /* Return true if *STR points to a relocation operator. When returning true, |
9689 | move *STR over the operator and store its relocation code in *RELOC. | |
9690 | Leave both *STR and *RELOC alone when returning false. */ | |
9691 | ||
9692 | static bfd_boolean | |
17a2f251 | 9693 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 9694 | { |
d6f16593 MR |
9695 | const struct percent_op_match *percent_op; |
9696 | size_t limit, i; | |
9697 | ||
9698 | if (mips_opts.mips16) | |
9699 | { | |
9700 | percent_op = mips16_percent_op; | |
9701 | limit = ARRAY_SIZE (mips16_percent_op); | |
9702 | } | |
9703 | else | |
9704 | { | |
9705 | percent_op = mips_percent_op; | |
9706 | limit = ARRAY_SIZE (mips_percent_op); | |
9707 | } | |
76b3015f | 9708 | |
d6f16593 | 9709 | for (i = 0; i < limit; i++) |
5e0116d5 | 9710 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 9711 | { |
3f98094e DJ |
9712 | int len = strlen (percent_op[i].str); |
9713 | ||
9714 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
9715 | continue; | |
9716 | ||
5e0116d5 RS |
9717 | *str += strlen (percent_op[i].str); |
9718 | *reloc = percent_op[i].reloc; | |
394f9b3a | 9719 | |
5e0116d5 RS |
9720 | /* Check whether the output BFD supports this relocation. |
9721 | If not, issue an error and fall back on something safe. */ | |
9722 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 9723 | { |
5e0116d5 RS |
9724 | as_bad ("relocation %s isn't supported by the current ABI", |
9725 | percent_op[i].str); | |
01a3f561 | 9726 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 9727 | } |
5e0116d5 | 9728 | return TRUE; |
394f9b3a | 9729 | } |
5e0116d5 | 9730 | return FALSE; |
394f9b3a | 9731 | } |
ad8d3bb3 | 9732 | |
ad8d3bb3 | 9733 | |
5e0116d5 RS |
9734 | /* Parse string STR as a 16-bit relocatable operand. Store the |
9735 | expression in *EP and the relocations in the array starting | |
9736 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 9737 | |
01a3f561 | 9738 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 9739 | |
5e0116d5 | 9740 | static size_t |
17a2f251 TS |
9741 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
9742 | char *str) | |
ad8d3bb3 | 9743 | { |
5e0116d5 RS |
9744 | bfd_reloc_code_real_type reversed_reloc[3]; |
9745 | size_t reloc_index, i; | |
09b8f35a RS |
9746 | int crux_depth, str_depth; |
9747 | char *crux; | |
5e0116d5 RS |
9748 | |
9749 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
9750 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
9751 | of the main expression and with CRUX_DEPTH containing the number | |
9752 | of open brackets at that point. */ | |
9753 | reloc_index = -1; | |
9754 | str_depth = 0; | |
9755 | do | |
fb1b3232 | 9756 | { |
09b8f35a RS |
9757 | reloc_index++; |
9758 | crux = str; | |
9759 | crux_depth = str_depth; | |
9760 | ||
9761 | /* Skip over whitespace and brackets, keeping count of the number | |
9762 | of brackets. */ | |
9763 | while (*str == ' ' || *str == '\t' || *str == '(') | |
9764 | if (*str++ == '(') | |
9765 | str_depth++; | |
5e0116d5 | 9766 | } |
09b8f35a RS |
9767 | while (*str == '%' |
9768 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
9769 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 9770 | |
09b8f35a | 9771 | my_getExpression (ep, crux); |
5e0116d5 | 9772 | str = expr_end; |
394f9b3a | 9773 | |
5e0116d5 | 9774 | /* Match every open bracket. */ |
09b8f35a | 9775 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 9776 | if (*str++ == ')') |
09b8f35a | 9777 | crux_depth--; |
394f9b3a | 9778 | |
09b8f35a | 9779 | if (crux_depth > 0) |
5e0116d5 | 9780 | as_bad ("unclosed '('"); |
394f9b3a | 9781 | |
5e0116d5 | 9782 | expr_end = str; |
252b5132 | 9783 | |
01a3f561 | 9784 | if (reloc_index != 0) |
64bdfcaf RS |
9785 | { |
9786 | prev_reloc_op_frag = frag_now; | |
9787 | for (i = 0; i < reloc_index; i++) | |
9788 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
9789 | } | |
fb1b3232 | 9790 | |
5e0116d5 | 9791 | return reloc_index; |
252b5132 RH |
9792 | } |
9793 | ||
9794 | static void | |
17a2f251 | 9795 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
9796 | { |
9797 | char *save_in; | |
98aa84af | 9798 | valueT val; |
252b5132 RH |
9799 | |
9800 | save_in = input_line_pointer; | |
9801 | input_line_pointer = str; | |
9802 | expression (ep); | |
9803 | expr_end = input_line_pointer; | |
9804 | input_line_pointer = save_in; | |
9805 | ||
9806 | /* If we are in mips16 mode, and this is an expression based on `.', | |
9807 | then we bump the value of the symbol by 1 since that is how other | |
9808 | text symbols are handled. We don't bother to handle complex | |
9809 | expressions, just `.' plus or minus a constant. */ | |
9810 | if (mips_opts.mips16 | |
9811 | && ep->X_op == O_symbol | |
9812 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
9813 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
49309057 ILT |
9814 | && symbol_get_frag (ep->X_add_symbol) == frag_now |
9815 | && symbol_constant_p (ep->X_add_symbol) | |
98aa84af AM |
9816 | && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ()) |
9817 | S_SET_VALUE (ep->X_add_symbol, val + 1); | |
252b5132 RH |
9818 | } |
9819 | ||
9820 | /* Turn a string in input_line_pointer into a floating point constant | |
bc0d738a NC |
9821 | of type TYPE, and store the appropriate bytes in *LITP. The number |
9822 | of LITTLENUMS emitted is stored in *SIZEP. An error message is | |
252b5132 RH |
9823 | returned, or NULL on OK. */ |
9824 | ||
9825 | char * | |
17a2f251 | 9826 | md_atof (int type, char *litP, int *sizeP) |
252b5132 RH |
9827 | { |
9828 | int prec; | |
9829 | LITTLENUM_TYPE words[4]; | |
9830 | char *t; | |
9831 | int i; | |
9832 | ||
9833 | switch (type) | |
9834 | { | |
9835 | case 'f': | |
9836 | prec = 2; | |
9837 | break; | |
9838 | ||
9839 | case 'd': | |
9840 | prec = 4; | |
9841 | break; | |
9842 | ||
9843 | default: | |
9844 | *sizeP = 0; | |
9845 | return _("bad call to md_atof"); | |
9846 | } | |
9847 | ||
9848 | t = atof_ieee (input_line_pointer, type, words); | |
9849 | if (t) | |
9850 | input_line_pointer = t; | |
9851 | ||
9852 | *sizeP = prec * 2; | |
9853 | ||
9854 | if (! target_big_endian) | |
9855 | { | |
9856 | for (i = prec - 1; i >= 0; i--) | |
9857 | { | |
17a2f251 | 9858 | md_number_to_chars (litP, words[i], 2); |
252b5132 RH |
9859 | litP += 2; |
9860 | } | |
9861 | } | |
9862 | else | |
9863 | { | |
9864 | for (i = 0; i < prec; i++) | |
9865 | { | |
17a2f251 | 9866 | md_number_to_chars (litP, words[i], 2); |
252b5132 RH |
9867 | litP += 2; |
9868 | } | |
9869 | } | |
bdaaa2e1 | 9870 | |
252b5132 RH |
9871 | return NULL; |
9872 | } | |
9873 | ||
9874 | void | |
17a2f251 | 9875 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
9876 | { |
9877 | if (target_big_endian) | |
9878 | number_to_chars_bigendian (buf, val, n); | |
9879 | else | |
9880 | number_to_chars_littleendian (buf, val, n); | |
9881 | } | |
9882 | \f | |
ae948b86 | 9883 | #ifdef OBJ_ELF |
e013f690 TS |
9884 | static int support_64bit_objects(void) |
9885 | { | |
9886 | const char **list, **l; | |
aa3d8fdf | 9887 | int yes; |
e013f690 TS |
9888 | |
9889 | list = bfd_target_list (); | |
9890 | for (l = list; *l != NULL; l++) | |
9891 | #ifdef TE_TMIPS | |
9892 | /* This is traditional mips */ | |
9893 | if (strcmp (*l, "elf64-tradbigmips") == 0 | |
9894 | || strcmp (*l, "elf64-tradlittlemips") == 0) | |
9895 | #else | |
9896 | if (strcmp (*l, "elf64-bigmips") == 0 | |
9897 | || strcmp (*l, "elf64-littlemips") == 0) | |
9898 | #endif | |
9899 | break; | |
aa3d8fdf | 9900 | yes = (*l != NULL); |
e013f690 | 9901 | free (list); |
aa3d8fdf | 9902 | return yes; |
e013f690 | 9903 | } |
ae948b86 | 9904 | #endif /* OBJ_ELF */ |
e013f690 | 9905 | |
78849248 | 9906 | const char *md_shortopts = "O::g::G:"; |
252b5132 | 9907 | |
e972090a NC |
9908 | struct option md_longopts[] = |
9909 | { | |
f9b4148d CD |
9910 | /* Options which specify architecture. */ |
9911 | #define OPTION_ARCH_BASE (OPTION_MD_BASE) | |
9912 | #define OPTION_MARCH (OPTION_ARCH_BASE + 0) | |
9913 | {"march", required_argument, NULL, OPTION_MARCH}, | |
9914 | #define OPTION_MTUNE (OPTION_ARCH_BASE + 1) | |
9915 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
9916 | #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2) | |
252b5132 RH |
9917 | {"mips0", no_argument, NULL, OPTION_MIPS1}, |
9918 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
f9b4148d | 9919 | #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3) |
252b5132 | 9920 | {"mips2", no_argument, NULL, OPTION_MIPS2}, |
f9b4148d | 9921 | #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4) |
252b5132 | 9922 | {"mips3", no_argument, NULL, OPTION_MIPS3}, |
f9b4148d | 9923 | #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5) |
252b5132 | 9924 | {"mips4", no_argument, NULL, OPTION_MIPS4}, |
f9b4148d | 9925 | #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6) |
ae948b86 | 9926 | {"mips5", no_argument, NULL, OPTION_MIPS5}, |
f9b4148d | 9927 | #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7) |
ae948b86 | 9928 | {"mips32", no_argument, NULL, OPTION_MIPS32}, |
f9b4148d | 9929 | #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8) |
ae948b86 | 9930 | {"mips64", no_argument, NULL, OPTION_MIPS64}, |
f9b4148d CD |
9931 | #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9) |
9932 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, | |
5f74bc13 CD |
9933 | #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10) |
9934 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, | |
f9b4148d CD |
9935 | |
9936 | /* Options which specify Application Specific Extensions (ASEs). */ | |
5f74bc13 | 9937 | #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11) |
f9b4148d CD |
9938 | #define OPTION_MIPS16 (OPTION_ASE_BASE + 0) |
9939 | {"mips16", no_argument, NULL, OPTION_MIPS16}, | |
9940 | #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1) | |
9941 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, | |
9942 | #define OPTION_MIPS3D (OPTION_ASE_BASE + 2) | |
9943 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, | |
9944 | #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3) | |
9945 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, | |
9946 | #define OPTION_MDMX (OPTION_ASE_BASE + 4) | |
9947 | {"mdmx", no_argument, NULL, OPTION_MDMX}, | |
9948 | #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5) | |
9949 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, | |
9950 | ||
9951 | /* Old-style architecture options. Don't add more of these. */ | |
9952 | #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6) | |
9953 | #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0) | |
9954 | {"m4650", no_argument, NULL, OPTION_M4650}, | |
9955 | #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1) | |
9956 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, | |
9957 | #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2) | |
9958 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
9959 | #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3) | |
9960 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
9961 | #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4) | |
9962 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
9963 | #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5) | |
9964 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
9965 | #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6) | |
9966 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
9967 | #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7) | |
9968 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
9969 | ||
9970 | /* Options which enable bug fixes. */ | |
9971 | #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8) | |
9972 | #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0) | |
9973 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, | |
9974 | #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1) | |
9975 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
9976 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
d766e8ec RS |
9977 | #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2) |
9978 | #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3) | |
9979 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, | |
9980 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
f9b4148d CD |
9981 | |
9982 | /* Miscellaneous options. */ | |
9983 | #define OPTION_MISC_BASE (OPTION_FIX_BASE + 4) | |
1ffcab4b | 9984 | #define OPTION_TRAP (OPTION_MISC_BASE + 0) |
252b5132 RH |
9985 | {"trap", no_argument, NULL, OPTION_TRAP}, |
9986 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
1ffcab4b | 9987 | #define OPTION_BREAK (OPTION_MISC_BASE + 1) |
252b5132 RH |
9988 | {"break", no_argument, NULL, OPTION_BREAK}, |
9989 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
1ffcab4b | 9990 | #define OPTION_EB (OPTION_MISC_BASE + 2) |
252b5132 | 9991 | {"EB", no_argument, NULL, OPTION_EB}, |
1ffcab4b | 9992 | #define OPTION_EL (OPTION_MISC_BASE + 3) |
252b5132 | 9993 | {"EL", no_argument, NULL, OPTION_EL}, |
1ffcab4b | 9994 | #define OPTION_FP32 (OPTION_MISC_BASE + 4) |
ae948b86 | 9995 | {"mfp32", no_argument, NULL, OPTION_FP32}, |
1ffcab4b | 9996 | #define OPTION_GP32 (OPTION_MISC_BASE + 5) |
c97ef257 | 9997 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
1ffcab4b | 9998 | #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6) |
119d663a | 9999 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
1ffcab4b | 10000 | #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7) |
119d663a | 10001 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
1ffcab4b | 10002 | #define OPTION_FP64 (OPTION_MISC_BASE + 8) |
316f5878 | 10003 | {"mfp64", no_argument, NULL, OPTION_FP64}, |
1ffcab4b | 10004 | #define OPTION_GP64 (OPTION_MISC_BASE + 9) |
ae948b86 | 10005 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
1ffcab4b CD |
10006 | #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10) |
10007 | #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11) | |
4a6a3df4 AO |
10008 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, |
10009 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
aa6975fb ILT |
10010 | #define OPTION_MSHARED (OPTION_MISC_BASE + 12) |
10011 | #define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13) | |
10012 | {"mshared", no_argument, NULL, OPTION_MSHARED}, | |
10013 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
aed1a261 RS |
10014 | #define OPTION_MSYM32 (OPTION_MISC_BASE + 14) |
10015 | #define OPTION_MNO_SYM32 (OPTION_MISC_BASE + 15) | |
10016 | {"msym32", no_argument, NULL, OPTION_MSYM32}, | |
10017 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, | |
f9b4148d CD |
10018 | |
10019 | /* ELF-specific options. */ | |
156c2f8b | 10020 | #ifdef OBJ_ELF |
aed1a261 | 10021 | #define OPTION_ELF_BASE (OPTION_MISC_BASE + 16) |
156c2f8b | 10022 | #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0) |
156c2f8b NC |
10023 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
10024 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
ae948b86 | 10025 | #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1) |
156c2f8b | 10026 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
ae948b86 | 10027 | #define OPTION_XGOT (OPTION_ELF_BASE + 2) |
156c2f8b | 10028 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
ae948b86 TS |
10029 | #define OPTION_MABI (OPTION_ELF_BASE + 3) |
10030 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
10031 | #define OPTION_32 (OPTION_ELF_BASE + 4) | |
156c2f8b | 10032 | {"32", no_argument, NULL, OPTION_32}, |
ae948b86 | 10033 | #define OPTION_N32 (OPTION_ELF_BASE + 5) |
e013f690 | 10034 | {"n32", no_argument, NULL, OPTION_N32}, |
ae948b86 | 10035 | #define OPTION_64 (OPTION_ELF_BASE + 6) |
156c2f8b | 10036 | {"64", no_argument, NULL, OPTION_64}, |
ecb4347a DJ |
10037 | #define OPTION_MDEBUG (OPTION_ELF_BASE + 7) |
10038 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, | |
10039 | #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8) | |
10040 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, | |
dcd410fe RO |
10041 | #define OPTION_PDR (OPTION_ELF_BASE + 9) |
10042 | {"mpdr", no_argument, NULL, OPTION_PDR}, | |
10043 | #define OPTION_NO_PDR (OPTION_ELF_BASE + 10) | |
10044 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, | |
ae948b86 | 10045 | #endif /* OBJ_ELF */ |
f9b4148d | 10046 | |
252b5132 RH |
10047 | {NULL, no_argument, NULL, 0} |
10048 | }; | |
156c2f8b | 10049 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 10050 | |
316f5878 RS |
10051 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
10052 | NEW_VALUE. Warn if another value was already specified. Note: | |
10053 | we have to defer parsing the -march and -mtune arguments in order | |
10054 | to handle 'from-abi' correctly, since the ABI might be specified | |
10055 | in a later argument. */ | |
10056 | ||
10057 | static void | |
17a2f251 | 10058 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
10059 | { |
10060 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
10061 | as_warn (_("A different %s was already specified, is now %s"), | |
10062 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
10063 | new_value); | |
10064 | ||
10065 | *string_ptr = new_value; | |
10066 | } | |
10067 | ||
252b5132 | 10068 | int |
17a2f251 | 10069 | md_parse_option (int c, char *arg) |
252b5132 RH |
10070 | { |
10071 | switch (c) | |
10072 | { | |
119d663a NC |
10073 | case OPTION_CONSTRUCT_FLOATS: |
10074 | mips_disable_float_construction = 0; | |
10075 | break; | |
bdaaa2e1 | 10076 | |
119d663a NC |
10077 | case OPTION_NO_CONSTRUCT_FLOATS: |
10078 | mips_disable_float_construction = 1; | |
10079 | break; | |
bdaaa2e1 | 10080 | |
252b5132 RH |
10081 | case OPTION_TRAP: |
10082 | mips_trap = 1; | |
10083 | break; | |
10084 | ||
10085 | case OPTION_BREAK: | |
10086 | mips_trap = 0; | |
10087 | break; | |
10088 | ||
10089 | case OPTION_EB: | |
10090 | target_big_endian = 1; | |
10091 | break; | |
10092 | ||
10093 | case OPTION_EL: | |
10094 | target_big_endian = 0; | |
10095 | break; | |
10096 | ||
10097 | case 'O': | |
10098 | if (arg && arg[1] == '0') | |
10099 | mips_optimize = 1; | |
10100 | else | |
10101 | mips_optimize = 2; | |
10102 | break; | |
10103 | ||
10104 | case 'g': | |
10105 | if (arg == NULL) | |
10106 | mips_debug = 2; | |
10107 | else | |
10108 | mips_debug = atoi (arg); | |
10109 | /* When the MIPS assembler sees -g or -g2, it does not do | |
10110 | optimizations which limit full symbolic debugging. We take | |
10111 | that to be equivalent to -O0. */ | |
10112 | if (mips_debug == 2) | |
10113 | mips_optimize = 1; | |
10114 | break; | |
10115 | ||
10116 | case OPTION_MIPS1: | |
316f5878 | 10117 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
10118 | break; |
10119 | ||
10120 | case OPTION_MIPS2: | |
316f5878 | 10121 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
10122 | break; |
10123 | ||
10124 | case OPTION_MIPS3: | |
316f5878 | 10125 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
10126 | break; |
10127 | ||
10128 | case OPTION_MIPS4: | |
316f5878 | 10129 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
10130 | break; |
10131 | ||
84ea6cf2 | 10132 | case OPTION_MIPS5: |
316f5878 | 10133 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
10134 | break; |
10135 | ||
e7af610e | 10136 | case OPTION_MIPS32: |
316f5878 | 10137 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
10138 | break; |
10139 | ||
af7ee8bf CD |
10140 | case OPTION_MIPS32R2: |
10141 | file_mips_isa = ISA_MIPS32R2; | |
10142 | break; | |
10143 | ||
5f74bc13 CD |
10144 | case OPTION_MIPS64R2: |
10145 | file_mips_isa = ISA_MIPS64R2; | |
10146 | break; | |
10147 | ||
84ea6cf2 | 10148 | case OPTION_MIPS64: |
316f5878 | 10149 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
10150 | break; |
10151 | ||
ec68c924 | 10152 | case OPTION_MTUNE: |
316f5878 RS |
10153 | mips_set_option_string (&mips_tune_string, arg); |
10154 | break; | |
ec68c924 | 10155 | |
316f5878 RS |
10156 | case OPTION_MARCH: |
10157 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
10158 | break; |
10159 | ||
10160 | case OPTION_M4650: | |
316f5878 RS |
10161 | mips_set_option_string (&mips_arch_string, "4650"); |
10162 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
10163 | break; |
10164 | ||
10165 | case OPTION_NO_M4650: | |
10166 | break; | |
10167 | ||
10168 | case OPTION_M4010: | |
316f5878 RS |
10169 | mips_set_option_string (&mips_arch_string, "4010"); |
10170 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
10171 | break; |
10172 | ||
10173 | case OPTION_NO_M4010: | |
10174 | break; | |
10175 | ||
10176 | case OPTION_M4100: | |
316f5878 RS |
10177 | mips_set_option_string (&mips_arch_string, "4100"); |
10178 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
10179 | break; |
10180 | ||
10181 | case OPTION_NO_M4100: | |
10182 | break; | |
10183 | ||
252b5132 | 10184 | case OPTION_M3900: |
316f5878 RS |
10185 | mips_set_option_string (&mips_arch_string, "3900"); |
10186 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 10187 | break; |
bdaaa2e1 | 10188 | |
252b5132 RH |
10189 | case OPTION_NO_M3900: |
10190 | break; | |
10191 | ||
deec1734 CD |
10192 | case OPTION_MDMX: |
10193 | mips_opts.ase_mdmx = 1; | |
10194 | break; | |
10195 | ||
10196 | case OPTION_NO_MDMX: | |
10197 | mips_opts.ase_mdmx = 0; | |
10198 | break; | |
10199 | ||
252b5132 RH |
10200 | case OPTION_MIPS16: |
10201 | mips_opts.mips16 = 1; | |
b34976b6 | 10202 | mips_no_prev_insn (FALSE); |
252b5132 RH |
10203 | break; |
10204 | ||
10205 | case OPTION_NO_MIPS16: | |
10206 | mips_opts.mips16 = 0; | |
b34976b6 | 10207 | mips_no_prev_insn (FALSE); |
252b5132 RH |
10208 | break; |
10209 | ||
1f25f5d3 CD |
10210 | case OPTION_MIPS3D: |
10211 | mips_opts.ase_mips3d = 1; | |
10212 | break; | |
10213 | ||
10214 | case OPTION_NO_MIPS3D: | |
10215 | mips_opts.ase_mips3d = 0; | |
10216 | break; | |
10217 | ||
d766e8ec RS |
10218 | case OPTION_FIX_VR4120: |
10219 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
10220 | break; |
10221 | ||
d766e8ec RS |
10222 | case OPTION_NO_FIX_VR4120: |
10223 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
10224 | break; |
10225 | ||
4a6a3df4 AO |
10226 | case OPTION_RELAX_BRANCH: |
10227 | mips_relax_branch = 1; | |
10228 | break; | |
10229 | ||
10230 | case OPTION_NO_RELAX_BRANCH: | |
10231 | mips_relax_branch = 0; | |
10232 | break; | |
10233 | ||
aa6975fb ILT |
10234 | case OPTION_MSHARED: |
10235 | mips_in_shared = TRUE; | |
10236 | break; | |
10237 | ||
10238 | case OPTION_MNO_SHARED: | |
10239 | mips_in_shared = FALSE; | |
10240 | break; | |
10241 | ||
aed1a261 RS |
10242 | case OPTION_MSYM32: |
10243 | mips_opts.sym32 = TRUE; | |
10244 | break; | |
10245 | ||
10246 | case OPTION_MNO_SYM32: | |
10247 | mips_opts.sym32 = FALSE; | |
10248 | break; | |
10249 | ||
0f074f60 | 10250 | #ifdef OBJ_ELF |
252b5132 RH |
10251 | /* When generating ELF code, we permit -KPIC and -call_shared to |
10252 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
10253 | intended to be compatible with Irix 5. */ | |
10254 | case OPTION_CALL_SHARED: | |
10255 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10256 | { | |
10257 | as_bad (_("-call_shared is supported only for ELF format")); | |
10258 | return 0; | |
10259 | } | |
10260 | mips_pic = SVR4_PIC; | |
143d77c5 | 10261 | mips_abicalls = TRUE; |
252b5132 RH |
10262 | if (g_switch_seen && g_switch_value != 0) |
10263 | { | |
10264 | as_bad (_("-G may not be used with SVR4 PIC code")); | |
10265 | return 0; | |
10266 | } | |
10267 | g_switch_value = 0; | |
10268 | break; | |
10269 | ||
10270 | case OPTION_NON_SHARED: | |
10271 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
10272 | { | |
10273 | as_bad (_("-non_shared is supported only for ELF format")); | |
10274 | return 0; | |
10275 | } | |
10276 | mips_pic = NO_PIC; | |
143d77c5 | 10277 | mips_abicalls = FALSE; |
252b5132 RH |
10278 | break; |
10279 | ||
10280 | /* The -xgot option tells the assembler to use 32 offsets when | |
10281 | accessing the got in SVR4_PIC mode. It is for Irix | |
10282 | compatibility. */ | |
10283 | case OPTION_XGOT: | |
10284 | mips_big_got = 1; | |
10285 | break; | |
0f074f60 | 10286 | #endif /* OBJ_ELF */ |
252b5132 RH |
10287 | |
10288 | case 'G': | |
6caf9ef4 TS |
10289 | g_switch_value = atoi (arg); |
10290 | g_switch_seen = 1; | |
10291 | if (mips_pic == SVR4_PIC && g_switch_value != 0) | |
252b5132 | 10292 | { |
3e722fb5 | 10293 | as_bad (_("-G may not be used with SVR4 PIC code")); |
252b5132 RH |
10294 | return 0; |
10295 | } | |
252b5132 RH |
10296 | break; |
10297 | ||
0f074f60 | 10298 | #ifdef OBJ_ELF |
34ba82a8 TS |
10299 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
10300 | and -mabi=64. */ | |
252b5132 | 10301 | case OPTION_32: |
34ba82a8 TS |
10302 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10303 | { | |
10304 | as_bad (_("-32 is supported for ELF format only")); | |
10305 | return 0; | |
10306 | } | |
316f5878 | 10307 | mips_abi = O32_ABI; |
252b5132 RH |
10308 | break; |
10309 | ||
e013f690 | 10310 | case OPTION_N32: |
34ba82a8 TS |
10311 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10312 | { | |
10313 | as_bad (_("-n32 is supported for ELF format only")); | |
10314 | return 0; | |
10315 | } | |
316f5878 | 10316 | mips_abi = N32_ABI; |
e013f690 | 10317 | break; |
252b5132 | 10318 | |
e013f690 | 10319 | case OPTION_64: |
34ba82a8 TS |
10320 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10321 | { | |
10322 | as_bad (_("-64 is supported for ELF format only")); | |
10323 | return 0; | |
10324 | } | |
316f5878 | 10325 | mips_abi = N64_ABI; |
e013f690 TS |
10326 | if (! support_64bit_objects()) |
10327 | as_fatal (_("No compiled in support for 64 bit object file format")); | |
252b5132 | 10328 | break; |
ae948b86 | 10329 | #endif /* OBJ_ELF */ |
252b5132 | 10330 | |
c97ef257 | 10331 | case OPTION_GP32: |
a325df1d | 10332 | file_mips_gp32 = 1; |
c97ef257 AH |
10333 | break; |
10334 | ||
10335 | case OPTION_GP64: | |
a325df1d | 10336 | file_mips_gp32 = 0; |
c97ef257 | 10337 | break; |
252b5132 | 10338 | |
ca4e0257 | 10339 | case OPTION_FP32: |
a325df1d | 10340 | file_mips_fp32 = 1; |
316f5878 RS |
10341 | break; |
10342 | ||
10343 | case OPTION_FP64: | |
10344 | file_mips_fp32 = 0; | |
ca4e0257 RS |
10345 | break; |
10346 | ||
ae948b86 | 10347 | #ifdef OBJ_ELF |
252b5132 | 10348 | case OPTION_MABI: |
34ba82a8 TS |
10349 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
10350 | { | |
10351 | as_bad (_("-mabi is supported for ELF format only")); | |
10352 | return 0; | |
10353 | } | |
e013f690 | 10354 | if (strcmp (arg, "32") == 0) |
316f5878 | 10355 | mips_abi = O32_ABI; |
e013f690 | 10356 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 10357 | mips_abi = O64_ABI; |
e013f690 | 10358 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 10359 | mips_abi = N32_ABI; |
e013f690 TS |
10360 | else if (strcmp (arg, "64") == 0) |
10361 | { | |
316f5878 | 10362 | mips_abi = N64_ABI; |
e013f690 TS |
10363 | if (! support_64bit_objects()) |
10364 | as_fatal (_("No compiled in support for 64 bit object file " | |
10365 | "format")); | |
10366 | } | |
10367 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 10368 | mips_abi = EABI_ABI; |
e013f690 | 10369 | else |
da0e507f TS |
10370 | { |
10371 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
10372 | return 0; | |
10373 | } | |
252b5132 | 10374 | break; |
e013f690 | 10375 | #endif /* OBJ_ELF */ |
252b5132 | 10376 | |
6b76fefe | 10377 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 10378 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
10379 | break; |
10380 | ||
9ee72ff1 | 10381 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 10382 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
10383 | break; |
10384 | ||
ecb4347a DJ |
10385 | #ifdef OBJ_ELF |
10386 | case OPTION_MDEBUG: | |
b34976b6 | 10387 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
10388 | break; |
10389 | ||
10390 | case OPTION_NO_MDEBUG: | |
b34976b6 | 10391 | mips_flag_mdebug = FALSE; |
ecb4347a | 10392 | break; |
dcd410fe RO |
10393 | |
10394 | case OPTION_PDR: | |
10395 | mips_flag_pdr = TRUE; | |
10396 | break; | |
10397 | ||
10398 | case OPTION_NO_PDR: | |
10399 | mips_flag_pdr = FALSE; | |
10400 | break; | |
ecb4347a DJ |
10401 | #endif /* OBJ_ELF */ |
10402 | ||
252b5132 RH |
10403 | default: |
10404 | return 0; | |
10405 | } | |
10406 | ||
10407 | return 1; | |
10408 | } | |
316f5878 RS |
10409 | \f |
10410 | /* Set up globals to generate code for the ISA or processor | |
10411 | described by INFO. */ | |
252b5132 | 10412 | |
252b5132 | 10413 | static void |
17a2f251 | 10414 | mips_set_architecture (const struct mips_cpu_info *info) |
252b5132 | 10415 | { |
316f5878 | 10416 | if (info != 0) |
252b5132 | 10417 | { |
fef14a42 TS |
10418 | file_mips_arch = info->cpu; |
10419 | mips_opts.arch = info->cpu; | |
316f5878 | 10420 | mips_opts.isa = info->isa; |
252b5132 | 10421 | } |
252b5132 RH |
10422 | } |
10423 | ||
252b5132 | 10424 | |
316f5878 | 10425 | /* Likewise for tuning. */ |
252b5132 | 10426 | |
316f5878 | 10427 | static void |
17a2f251 | 10428 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
10429 | { |
10430 | if (info != 0) | |
fef14a42 | 10431 | mips_tune = info->cpu; |
316f5878 | 10432 | } |
80cc45a5 | 10433 | |
34ba82a8 | 10434 | |
252b5132 | 10435 | void |
17a2f251 | 10436 | mips_after_parse_args (void) |
e9670677 | 10437 | { |
fef14a42 TS |
10438 | const struct mips_cpu_info *arch_info = 0; |
10439 | const struct mips_cpu_info *tune_info = 0; | |
10440 | ||
e9670677 | 10441 | /* GP relative stuff not working for PE */ |
6caf9ef4 | 10442 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
e9670677 | 10443 | { |
6caf9ef4 | 10444 | if (g_switch_seen && g_switch_value != 0) |
e9670677 MR |
10445 | as_bad (_("-G not supported in this configuration.")); |
10446 | g_switch_value = 0; | |
10447 | } | |
10448 | ||
cac012d6 AO |
10449 | if (mips_abi == NO_ABI) |
10450 | mips_abi = MIPS_DEFAULT_ABI; | |
10451 | ||
22923709 RS |
10452 | /* The following code determines the architecture and register size. |
10453 | Similar code was added to GCC 3.3 (see override_options() in | |
10454 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
10455 | as much as possible. */ | |
e9670677 | 10456 | |
316f5878 | 10457 | if (mips_arch_string != 0) |
fef14a42 | 10458 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 10459 | |
316f5878 | 10460 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 10461 | { |
316f5878 | 10462 | /* Handle -mipsN. At this point, file_mips_isa contains the |
fef14a42 | 10463 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 10464 | the -march selection (if any). */ |
fef14a42 | 10465 | if (arch_info != 0) |
e9670677 | 10466 | { |
316f5878 RS |
10467 | /* -march takes precedence over -mipsN, since it is more descriptive. |
10468 | There's no harm in specifying both as long as the ISA levels | |
10469 | are the same. */ | |
fef14a42 | 10470 | if (file_mips_isa != arch_info->isa) |
316f5878 RS |
10471 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), |
10472 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
fef14a42 | 10473 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 10474 | } |
316f5878 | 10475 | else |
fef14a42 | 10476 | arch_info = mips_cpu_info_from_isa (file_mips_isa); |
e9670677 MR |
10477 | } |
10478 | ||
fef14a42 TS |
10479 | if (arch_info == 0) |
10480 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
e9670677 | 10481 | |
fef14a42 | 10482 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
316f5878 | 10483 | as_bad ("-march=%s is not compatible with the selected ABI", |
fef14a42 TS |
10484 | arch_info->name); |
10485 | ||
10486 | mips_set_architecture (arch_info); | |
10487 | ||
10488 | /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ | |
10489 | if (mips_tune_string != 0) | |
10490 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 10491 | |
fef14a42 TS |
10492 | if (tune_info == 0) |
10493 | mips_set_tune (arch_info); | |
10494 | else | |
10495 | mips_set_tune (tune_info); | |
e9670677 | 10496 | |
316f5878 | 10497 | if (file_mips_gp32 >= 0) |
e9670677 | 10498 | { |
316f5878 RS |
10499 | /* The user specified the size of the integer registers. Make sure |
10500 | it agrees with the ABI and ISA. */ | |
10501 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
10502 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
10503 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
10504 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
10505 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
10506 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
10507 | } |
10508 | else | |
10509 | { | |
316f5878 RS |
10510 | /* Infer the integer register size from the ABI and processor. |
10511 | Restrict ourselves to 32-bit registers if that's all the | |
10512 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
10513 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
10514 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
10515 | } |
10516 | ||
316f5878 RS |
10517 | /* ??? GAS treats single-float processors as though they had 64-bit |
10518 | float registers (although it complains when double-precision | |
10519 | instructions are used). As things stand, saying they have 32-bit | |
10520 | registers would lead to spurious "register must be even" messages. | |
10521 | So here we assume float registers are always the same size as | |
10522 | integer ones, unless the user says otherwise. */ | |
10523 | if (file_mips_fp32 < 0) | |
10524 | file_mips_fp32 = file_mips_gp32; | |
e9670677 | 10525 | |
316f5878 | 10526 | /* End of GCC-shared inference code. */ |
e9670677 | 10527 | |
17a2f251 TS |
10528 | /* This flag is set when we have a 64-bit capable CPU but use only |
10529 | 32-bit wide registers. Note that EABI does not use it. */ | |
10530 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) | |
10531 | && ((mips_abi == NO_ABI && file_mips_gp32 == 1) | |
10532 | || mips_abi == O32_ABI)) | |
316f5878 | 10533 | mips_32bitmode = 1; |
e9670677 MR |
10534 | |
10535 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
10536 | as_bad (_("trap exception not supported at ISA 1")); | |
10537 | ||
e9670677 MR |
10538 | /* If the selected architecture includes support for ASEs, enable |
10539 | generation of code for them. */ | |
a4672219 | 10540 | if (mips_opts.mips16 == -1) |
fef14a42 | 10541 | mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 10542 | if (mips_opts.ase_mips3d == -1) |
fef14a42 | 10543 | mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (file_mips_arch)) ? 1 : 0; |
ffdefa66 | 10544 | if (mips_opts.ase_mdmx == -1) |
fef14a42 | 10545 | mips_opts.ase_mdmx = (CPU_HAS_MDMX (file_mips_arch)) ? 1 : 0; |
e9670677 | 10546 | |
e9670677 | 10547 | file_mips_isa = mips_opts.isa; |
a4672219 | 10548 | file_ase_mips16 = mips_opts.mips16; |
e9670677 MR |
10549 | file_ase_mips3d = mips_opts.ase_mips3d; |
10550 | file_ase_mdmx = mips_opts.ase_mdmx; | |
10551 | mips_opts.gp32 = file_mips_gp32; | |
10552 | mips_opts.fp32 = file_mips_fp32; | |
10553 | ||
ecb4347a DJ |
10554 | if (mips_flag_mdebug < 0) |
10555 | { | |
10556 | #ifdef OBJ_MAYBE_ECOFF | |
10557 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) | |
10558 | mips_flag_mdebug = 1; | |
10559 | else | |
10560 | #endif /* OBJ_MAYBE_ECOFF */ | |
10561 | mips_flag_mdebug = 0; | |
10562 | } | |
e9670677 MR |
10563 | } |
10564 | \f | |
10565 | void | |
17a2f251 | 10566 | mips_init_after_args (void) |
252b5132 RH |
10567 | { |
10568 | /* initialize opcodes */ | |
10569 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 10570 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
10571 | } |
10572 | ||
10573 | long | |
17a2f251 | 10574 | md_pcrel_from (fixS *fixP) |
252b5132 | 10575 | { |
a7ebbfdf TS |
10576 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
10577 | switch (fixP->fx_r_type) | |
10578 | { | |
10579 | case BFD_RELOC_16_PCREL_S2: | |
10580 | case BFD_RELOC_MIPS_JMP: | |
10581 | /* Return the address of the delay slot. */ | |
10582 | return addr + 4; | |
10583 | default: | |
10584 | return addr; | |
10585 | } | |
252b5132 RH |
10586 | } |
10587 | ||
252b5132 RH |
10588 | /* This is called before the symbol table is processed. In order to |
10589 | work with gcc when using mips-tfile, we must keep all local labels. | |
10590 | However, in other cases, we want to discard them. If we were | |
10591 | called with -g, but we didn't see any debugging information, it may | |
10592 | mean that gcc is smuggling debugging information through to | |
10593 | mips-tfile, in which case we must generate all local labels. */ | |
10594 | ||
10595 | void | |
17a2f251 | 10596 | mips_frob_file_before_adjust (void) |
252b5132 RH |
10597 | { |
10598 | #ifndef NO_ECOFF_DEBUGGING | |
10599 | if (ECOFF_DEBUGGING | |
10600 | && mips_debug != 0 | |
10601 | && ! ecoff_debugging_seen) | |
10602 | flag_keep_locals = 1; | |
10603 | #endif | |
10604 | } | |
10605 | ||
3b91255e RS |
10606 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
10607 | the corresponding LO16 reloc. This is called before md_apply_fix3 and | |
10608 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit | |
10609 | relocation operators. | |
10610 | ||
10611 | For our purposes, a %lo() expression matches a %got() or %hi() | |
10612 | expression if: | |
10613 | ||
10614 | (a) it refers to the same symbol; and | |
10615 | (b) the offset applied in the %lo() expression is no lower than | |
10616 | the offset applied in the %got() or %hi(). | |
10617 | ||
10618 | (b) allows us to cope with code like: | |
10619 | ||
10620 | lui $4,%hi(foo) | |
10621 | lh $4,%lo(foo+2)($4) | |
10622 | ||
10623 | ...which is legal on RELA targets, and has a well-defined behaviour | |
10624 | if the user knows that adding 2 to "foo" will not induce a carry to | |
10625 | the high 16 bits. | |
10626 | ||
10627 | When several %lo()s match a particular %got() or %hi(), we use the | |
10628 | following rules to distinguish them: | |
10629 | ||
10630 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
10631 | higher offsets. | |
10632 | ||
10633 | (2) %lo()s with no matching %got() or %hi() are better than those | |
10634 | that already have a matching %got() or %hi(). | |
10635 | ||
10636 | (3) later %lo()s are better than earlier %lo()s. | |
10637 | ||
10638 | These rules are applied in order. | |
10639 | ||
10640 | (1) means, among other things, that %lo()s with identical offsets are | |
10641 | chosen if they exist. | |
10642 | ||
10643 | (2) means that we won't associate several high-part relocations with | |
10644 | the same low-part relocation unless there's no alternative. Having | |
10645 | several high parts for the same low part is a GNU extension; this rule | |
10646 | allows careful users to avoid it. | |
10647 | ||
10648 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
10649 | with the last high-part relocation being at the front of the list. | |
10650 | It therefore makes sense to choose the last matching low-part | |
10651 | relocation, all other things being equal. It's also easier | |
10652 | to code that way. */ | |
252b5132 RH |
10653 | |
10654 | void | |
17a2f251 | 10655 | mips_frob_file (void) |
252b5132 RH |
10656 | { |
10657 | struct mips_hi_fixup *l; | |
10658 | ||
10659 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
10660 | { | |
10661 | segment_info_type *seginfo; | |
3b91255e RS |
10662 | bfd_boolean matched_lo_p; |
10663 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 10664 | |
5919d012 | 10665 | assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 10666 | |
5919d012 RS |
10667 | /* If a GOT16 relocation turns out to be against a global symbol, |
10668 | there isn't supposed to be a matching LO. */ | |
10669 | if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
10670 | && !pic_need_relax (l->fixp->fx_addsy, l->seg)) | |
10671 | continue; | |
10672 | ||
10673 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
10674 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
10675 | continue; |
10676 | ||
252b5132 | 10677 | seginfo = seg_info (l->seg); |
252b5132 | 10678 | |
3b91255e RS |
10679 | /* Set HI_POS to the position of this relocation in the chain. |
10680 | Set LO_POS to the position of the chosen low-part relocation. | |
10681 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
10682 | relocation that matches an immediately-preceding high-part | |
10683 | relocation. */ | |
10684 | hi_pos = NULL; | |
10685 | lo_pos = NULL; | |
10686 | matched_lo_p = FALSE; | |
10687 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) | |
10688 | { | |
10689 | if (*pos == l->fixp) | |
10690 | hi_pos = pos; | |
10691 | ||
10692 | if ((*pos)->fx_r_type == BFD_RELOC_LO16 | |
10693 | && (*pos)->fx_addsy == l->fixp->fx_addsy | |
10694 | && (*pos)->fx_offset >= l->fixp->fx_offset | |
10695 | && (lo_pos == NULL | |
10696 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
10697 | || (!matched_lo_p | |
10698 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
10699 | lo_pos = pos; | |
10700 | ||
10701 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
10702 | && fixup_has_matching_lo_p (*pos)); | |
10703 | } | |
10704 | ||
10705 | /* If we found a match, remove the high-part relocation from its | |
10706 | current position and insert it before the low-part relocation. | |
10707 | Make the offsets match so that fixup_has_matching_lo_p() | |
10708 | will return true. | |
10709 | ||
10710 | We don't warn about unmatched high-part relocations since some | |
10711 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
10712 | instructions. */ | |
10713 | if (lo_pos != NULL) | |
10714 | { | |
10715 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
10716 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 10717 | { |
3b91255e RS |
10718 | *hi_pos = l->fixp->fx_next; |
10719 | l->fixp->fx_next = *lo_pos; | |
10720 | *lo_pos = l->fixp; | |
252b5132 | 10721 | } |
252b5132 RH |
10722 | } |
10723 | } | |
10724 | } | |
10725 | ||
3e722fb5 | 10726 | /* We may have combined relocations without symbols in the N32/N64 ABI. |
f6688943 | 10727 | We have to prevent gas from dropping them. */ |
252b5132 | 10728 | |
252b5132 | 10729 | int |
17a2f251 | 10730 | mips_force_relocation (fixS *fixp) |
252b5132 | 10731 | { |
ae6063d4 | 10732 | if (generic_force_reloc (fixp)) |
252b5132 RH |
10733 | return 1; |
10734 | ||
f6688943 TS |
10735 | if (HAVE_NEWABI |
10736 | && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr | |
10737 | && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB | |
10738 | || fixp->fx_r_type == BFD_RELOC_HI16_S | |
10739 | || fixp->fx_r_type == BFD_RELOC_LO16)) | |
10740 | return 1; | |
10741 | ||
3e722fb5 | 10742 | return 0; |
252b5132 RH |
10743 | } |
10744 | ||
45f8dfe8 AO |
10745 | /* This hook is called before a fix is simplified. We don't really |
10746 | decide whether to skip a fix here. Rather, we turn global symbols | |
10747 | used as branch targets into local symbols, such that they undergo | |
10748 | simplification. We can only do this if the symbol is defined and | |
10749 | it is in the same section as the branch. If this doesn't hold, we | |
10750 | emit a better error message than just saying the relocation is not | |
10751 | valid for the selected object format. | |
10752 | ||
10753 | FIXP is the fix-up we're going to try to simplify, SEG is the | |
10754 | segment in which the fix up occurs. The return value should be | |
10755 | non-zero to indicate the fix-up is valid for further | |
10756 | simplifications. */ | |
10757 | ||
10758 | int | |
17a2f251 | 10759 | mips_validate_fix (struct fix *fixP, asection *seg) |
45f8dfe8 AO |
10760 | { |
10761 | /* There's a lot of discussion on whether it should be possible to | |
10762 | use R_MIPS_PC16 to represent branch relocations. The outcome | |
10763 | seems to be that it can, but gas/bfd are very broken in creating | |
10764 | RELA relocations for this, so for now we only accept branches to | |
10765 | symbols in the same section. Anything else is of dubious value, | |
10766 | since there's no guarantee that at link time the symbol would be | |
10767 | in range. Even for branches to local symbols this is arguably | |
10768 | wrong, since it we assume the symbol is not going to be | |
10769 | overridden, which should be possible per ELF library semantics, | |
10770 | but then, there isn't a dynamic relocation that could be used to | |
10771 | this effect, and the target would likely be out of range as well. | |
10772 | ||
10773 | Unfortunately, it seems that there is too much code out there | |
10774 | that relies on branches to symbols that are global to be resolved | |
10775 | as if they were local, like the IRIX tools do, so we do it as | |
10776 | well, but with a warning so that people are reminded to fix their | |
10777 | code. If we ever get back to using R_MIPS_PC16 for branch | |
10778 | targets, this entire block should go away (and probably the | |
10779 | whole function). */ | |
10780 | ||
10781 | if (fixP->fx_r_type == BFD_RELOC_16_PCREL_S2 | |
3e722fb5 CD |
10782 | && ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
10783 | || OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
45f8dfe8 AO |
10784 | || bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16_PCREL_S2) == NULL) |
10785 | && fixP->fx_addsy) | |
10786 | { | |
10787 | if (! S_IS_DEFINED (fixP->fx_addsy)) | |
10788 | { | |
10789 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10790 | _("Cannot branch to undefined symbol.")); | |
10791 | /* Avoid any further errors about this fixup. */ | |
10792 | fixP->fx_done = 1; | |
10793 | } | |
10794 | else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
10795 | { | |
10796 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
10797 | _("Cannot branch to symbol in another section.")); | |
10798 | fixP->fx_done = 1; | |
10799 | } | |
10800 | else if (S_IS_EXTERNAL (fixP->fx_addsy)) | |
10801 | { | |
10802 | symbolS *sym = fixP->fx_addsy; | |
10803 | ||
115695a8 CD |
10804 | if (mips_pic == SVR4_PIC) |
10805 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
10806 | _("Pretending global symbol used as branch target is local.")); | |
45f8dfe8 AO |
10807 | |
10808 | fixP->fx_addsy = symbol_create (S_GET_NAME (sym), | |
10809 | S_GET_SEGMENT (sym), | |
10810 | S_GET_VALUE (sym), | |
10811 | symbol_get_frag (sym)); | |
10812 | copy_symbol_attributes (fixP->fx_addsy, sym); | |
10813 | S_CLEAR_EXTERNAL (fixP->fx_addsy); | |
10814 | assert (symbol_resolved_p (sym)); | |
10815 | symbol_mark_resolved (fixP->fx_addsy); | |
10816 | } | |
10817 | } | |
10818 | ||
10819 | return 1; | |
10820 | } | |
10821 | ||
252b5132 RH |
10822 | /* Apply a fixup to the object file. */ |
10823 | ||
94f592af | 10824 | void |
17a2f251 | 10825 | md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 10826 | { |
874e8986 | 10827 | bfd_byte *buf; |
98aa84af | 10828 | long insn; |
a7ebbfdf | 10829 | reloc_howto_type *howto; |
252b5132 | 10830 | |
a7ebbfdf TS |
10831 | /* We ignore generic BFD relocations we don't know about. */ |
10832 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
10833 | if (! howto) | |
10834 | return; | |
65551fa4 | 10835 | |
252b5132 RH |
10836 | assert (fixP->fx_size == 4 |
10837 | || fixP->fx_r_type == BFD_RELOC_16 | |
10838 | || fixP->fx_r_type == BFD_RELOC_64 | |
f6688943 TS |
10839 | || fixP->fx_r_type == BFD_RELOC_CTOR |
10840 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
252b5132 | 10841 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
a7ebbfdf | 10842 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY); |
252b5132 | 10843 | |
a7ebbfdf | 10844 | buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); |
252b5132 | 10845 | |
3e722fb5 | 10846 | assert (! fixP->fx_pcrel); |
b1dca8ee RS |
10847 | |
10848 | /* Don't treat parts of a composite relocation as done. There are two | |
10849 | reasons for this: | |
10850 | ||
10851 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
10852 | should nevertheless be emitted if the first part is. | |
10853 | ||
10854 | (2) In normal usage, composite relocations are never assembly-time | |
10855 | constants. The easiest way of dealing with the pathological | |
10856 | exceptions is to generate a relocation against STN_UNDEF and | |
10857 | leave everything up to the linker. */ | |
10858 | if (fixP->fx_addsy == NULL && fixP->fx_tcbit == 0) | |
252b5132 RH |
10859 | fixP->fx_done = 1; |
10860 | ||
10861 | switch (fixP->fx_r_type) | |
10862 | { | |
3f98094e DJ |
10863 | case BFD_RELOC_MIPS_TLS_GD: |
10864 | case BFD_RELOC_MIPS_TLS_LDM: | |
10865 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: | |
10866 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
10867 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
10868 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: | |
10869 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
10870 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
10871 | /* fall through */ | |
10872 | ||
252b5132 | 10873 | case BFD_RELOC_MIPS_JMP: |
e369bcce TS |
10874 | case BFD_RELOC_MIPS_SHIFT5: |
10875 | case BFD_RELOC_MIPS_SHIFT6: | |
10876 | case BFD_RELOC_MIPS_GOT_DISP: | |
10877 | case BFD_RELOC_MIPS_GOT_PAGE: | |
10878 | case BFD_RELOC_MIPS_GOT_OFST: | |
10879 | case BFD_RELOC_MIPS_SUB: | |
10880 | case BFD_RELOC_MIPS_INSERT_A: | |
10881 | case BFD_RELOC_MIPS_INSERT_B: | |
10882 | case BFD_RELOC_MIPS_DELETE: | |
10883 | case BFD_RELOC_MIPS_HIGHEST: | |
10884 | case BFD_RELOC_MIPS_HIGHER: | |
10885 | case BFD_RELOC_MIPS_SCN_DISP: | |
10886 | case BFD_RELOC_MIPS_REL16: | |
10887 | case BFD_RELOC_MIPS_RELGOT: | |
10888 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
10889 | case BFD_RELOC_HI16: |
10890 | case BFD_RELOC_HI16_S: | |
cdf6fd85 | 10891 | case BFD_RELOC_GPREL16: |
252b5132 RH |
10892 | case BFD_RELOC_MIPS_LITERAL: |
10893 | case BFD_RELOC_MIPS_CALL16: | |
10894 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 10895 | case BFD_RELOC_GPREL32: |
252b5132 RH |
10896 | case BFD_RELOC_MIPS_GOT_HI16: |
10897 | case BFD_RELOC_MIPS_GOT_LO16: | |
10898 | case BFD_RELOC_MIPS_CALL_HI16: | |
10899 | case BFD_RELOC_MIPS_CALL_LO16: | |
10900 | case BFD_RELOC_MIPS16_GPREL: | |
d6f16593 MR |
10901 | case BFD_RELOC_MIPS16_HI16: |
10902 | case BFD_RELOC_MIPS16_HI16_S: | |
3e722fb5 | 10903 | assert (! fixP->fx_pcrel); |
252b5132 RH |
10904 | /* Nothing needed to do. The value comes from the reloc entry */ |
10905 | break; | |
10906 | ||
10907 | case BFD_RELOC_MIPS16_JMP: | |
10908 | /* We currently always generate a reloc against a symbol, which | |
10909 | means that we don't want an addend even if the symbol is | |
10910 | defined. */ | |
a7ebbfdf | 10911 | *valP = 0; |
252b5132 RH |
10912 | break; |
10913 | ||
252b5132 RH |
10914 | case BFD_RELOC_64: |
10915 | /* This is handled like BFD_RELOC_32, but we output a sign | |
10916 | extended value if we are only 32 bits. */ | |
3e722fb5 | 10917 | if (fixP->fx_done) |
252b5132 RH |
10918 | { |
10919 | if (8 <= sizeof (valueT)) | |
2132e3a3 | 10920 | md_number_to_chars ((char *) buf, *valP, 8); |
252b5132 RH |
10921 | else |
10922 | { | |
a7ebbfdf | 10923 | valueT hiv; |
252b5132 | 10924 | |
a7ebbfdf | 10925 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
10926 | hiv = 0xffffffff; |
10927 | else | |
10928 | hiv = 0; | |
a7ebbfdf TS |
10929 | md_number_to_chars ((char *)(buf + target_big_endian ? 4 : 0), |
10930 | *valP, 4); | |
10931 | md_number_to_chars ((char *)(buf + target_big_endian ? 0 : 4), | |
10932 | hiv, 4); | |
252b5132 RH |
10933 | } |
10934 | } | |
10935 | break; | |
10936 | ||
056350c6 | 10937 | case BFD_RELOC_RVA: |
252b5132 RH |
10938 | case BFD_RELOC_32: |
10939 | /* If we are deleting this reloc entry, we must fill in the | |
10940 | value now. This can happen if we have a .word which is not | |
3e722fb5 CD |
10941 | resolved when it appears but is later defined. */ |
10942 | if (fixP->fx_done) | |
2132e3a3 | 10943 | md_number_to_chars ((char *) buf, *valP, 4); |
252b5132 RH |
10944 | break; |
10945 | ||
10946 | case BFD_RELOC_16: | |
10947 | /* If we are deleting this reloc entry, we must fill in the | |
10948 | value now. */ | |
252b5132 | 10949 | if (fixP->fx_done) |
2132e3a3 | 10950 | md_number_to_chars ((char *) buf, *valP, 2); |
252b5132 RH |
10951 | break; |
10952 | ||
10953 | case BFD_RELOC_LO16: | |
d6f16593 | 10954 | case BFD_RELOC_MIPS16_LO16: |
3e722fb5 CD |
10955 | /* FIXME: Now that embedded-PIC is gone, some of this code/comment |
10956 | may be safe to remove, but if so it's not obvious. */ | |
252b5132 RH |
10957 | /* When handling an embedded PIC switch statement, we can wind |
10958 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
10959 | if (fixP->fx_done) | |
10960 | { | |
a7ebbfdf | 10961 | if (*valP + 0x8000 > 0xffff) |
252b5132 RH |
10962 | as_bad_where (fixP->fx_file, fixP->fx_line, |
10963 | _("relocation overflow")); | |
252b5132 RH |
10964 | if (target_big_endian) |
10965 | buf += 2; | |
2132e3a3 | 10966 | md_number_to_chars ((char *) buf, *valP, 2); |
252b5132 RH |
10967 | } |
10968 | break; | |
10969 | ||
10970 | case BFD_RELOC_16_PCREL_S2: | |
a7ebbfdf | 10971 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 10972 | as_bad_where (fixP->fx_file, fixP->fx_line, |
a7ebbfdf | 10973 | _("Branch to odd address (%lx)"), (long) *valP); |
cb56d3d3 | 10974 | |
252b5132 RH |
10975 | /* |
10976 | * We need to save the bits in the instruction since fixup_segment() | |
10977 | * might be deleting the relocation entry (i.e., a branch within | |
10978 | * the current segment). | |
10979 | */ | |
a7ebbfdf | 10980 | if (! fixP->fx_done) |
bb2d6cd7 | 10981 | break; |
252b5132 RH |
10982 | |
10983 | /* update old instruction data */ | |
252b5132 RH |
10984 | if (target_big_endian) |
10985 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
10986 | else | |
10987 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
10988 | ||
a7ebbfdf TS |
10989 | if (*valP + 0x20000 <= 0x3ffff) |
10990 | { | |
10991 | insn |= (*valP >> 2) & 0xffff; | |
2132e3a3 | 10992 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
10993 | } |
10994 | else if (mips_pic == NO_PIC | |
10995 | && fixP->fx_done | |
10996 | && fixP->fx_frag->fr_address >= text_section->vma | |
10997 | && (fixP->fx_frag->fr_address | |
587aac4e | 10998 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
10999 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
11000 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
11001 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
11002 | { |
11003 | /* The branch offset is too large. If this is an | |
11004 | unconditional branch, and we are not generating PIC code, | |
11005 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
11006 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
11007 | insn = 0x0c000000; /* jal */ | |
252b5132 | 11008 | else |
a7ebbfdf TS |
11009 | insn = 0x08000000; /* j */ |
11010 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
11011 | fixP->fx_done = 0; | |
11012 | fixP->fx_addsy = section_symbol (text_section); | |
11013 | *valP += md_pcrel_from (fixP); | |
2132e3a3 | 11014 | md_number_to_chars ((char *) buf, insn, 4); |
a7ebbfdf TS |
11015 | } |
11016 | else | |
11017 | { | |
11018 | /* If we got here, we have branch-relaxation disabled, | |
11019 | and there's nothing we can do to fix this instruction | |
11020 | without turning it into a longer sequence. */ | |
11021 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
11022 | _("Branch out of range")); | |
252b5132 | 11023 | } |
252b5132 RH |
11024 | break; |
11025 | ||
11026 | case BFD_RELOC_VTABLE_INHERIT: | |
11027 | fixP->fx_done = 0; | |
11028 | if (fixP->fx_addsy | |
11029 | && !S_IS_DEFINED (fixP->fx_addsy) | |
11030 | && !S_IS_WEAK (fixP->fx_addsy)) | |
11031 | S_SET_WEAK (fixP->fx_addsy); | |
11032 | break; | |
11033 | ||
11034 | case BFD_RELOC_VTABLE_ENTRY: | |
11035 | fixP->fx_done = 0; | |
11036 | break; | |
11037 | ||
11038 | default: | |
11039 | internalError (); | |
11040 | } | |
a7ebbfdf TS |
11041 | |
11042 | /* Remember value for tc_gen_reloc. */ | |
11043 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
11044 | } |
11045 | ||
252b5132 | 11046 | static symbolS * |
17a2f251 | 11047 | get_symbol (void) |
252b5132 RH |
11048 | { |
11049 | int c; | |
11050 | char *name; | |
11051 | symbolS *p; | |
11052 | ||
11053 | name = input_line_pointer; | |
11054 | c = get_symbol_end (); | |
11055 | p = (symbolS *) symbol_find_or_make (name); | |
11056 | *input_line_pointer = c; | |
11057 | return p; | |
11058 | } | |
11059 | ||
11060 | /* Align the current frag to a given power of two. The MIPS assembler | |
11061 | also automatically adjusts any preceding label. */ | |
11062 | ||
11063 | static void | |
17a2f251 | 11064 | mips_align (int to, int fill, symbolS *label) |
252b5132 | 11065 | { |
b34976b6 | 11066 | mips_emit_delays (FALSE); |
252b5132 RH |
11067 | frag_align (to, fill, 0); |
11068 | record_alignment (now_seg, to); | |
11069 | if (label != NULL) | |
11070 | { | |
11071 | assert (S_GET_SEGMENT (label) == now_seg); | |
49309057 | 11072 | symbol_set_frag (label, frag_now); |
252b5132 RH |
11073 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
11074 | } | |
11075 | } | |
11076 | ||
11077 | /* Align to a given power of two. .align 0 turns off the automatic | |
11078 | alignment used by the data creating pseudo-ops. */ | |
11079 | ||
11080 | static void | |
17a2f251 | 11081 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11082 | { |
11083 | register int temp; | |
11084 | register long temp_fill; | |
11085 | long max_alignment = 15; | |
11086 | ||
11087 | /* | |
11088 | ||
67c1ffbe | 11089 | o Note that the assembler pulls down any immediately preceding label |
252b5132 RH |
11090 | to the aligned address. |
11091 | o It's not documented but auto alignment is reinstated by | |
11092 | a .align pseudo instruction. | |
11093 | o Note also that after auto alignment is turned off the mips assembler | |
11094 | issues an error on attempt to assemble an improperly aligned data item. | |
11095 | We don't. | |
11096 | ||
11097 | */ | |
11098 | ||
11099 | temp = get_absolute_expression (); | |
11100 | if (temp > max_alignment) | |
11101 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
11102 | else if (temp < 0) | |
11103 | { | |
11104 | as_warn (_("Alignment negative: 0 assumed.")); | |
11105 | temp = 0; | |
11106 | } | |
11107 | if (*input_line_pointer == ',') | |
11108 | { | |
f9419b05 | 11109 | ++input_line_pointer; |
252b5132 RH |
11110 | temp_fill = get_absolute_expression (); |
11111 | } | |
11112 | else | |
11113 | temp_fill = 0; | |
11114 | if (temp) | |
11115 | { | |
11116 | auto_align = 1; | |
11117 | mips_align (temp, (int) temp_fill, | |
11118 | insn_labels != NULL ? insn_labels->label : NULL); | |
11119 | } | |
11120 | else | |
11121 | { | |
11122 | auto_align = 0; | |
11123 | } | |
11124 | ||
11125 | demand_empty_rest_of_line (); | |
11126 | } | |
11127 | ||
11128 | void | |
17a2f251 | 11129 | mips_flush_pending_output (void) |
252b5132 | 11130 | { |
b34976b6 | 11131 | mips_emit_delays (FALSE); |
252b5132 RH |
11132 | mips_clear_insn_labels (); |
11133 | } | |
11134 | ||
11135 | static void | |
17a2f251 | 11136 | s_change_sec (int sec) |
252b5132 RH |
11137 | { |
11138 | segT seg; | |
11139 | ||
252b5132 RH |
11140 | #ifdef OBJ_ELF |
11141 | /* The ELF backend needs to know that we are changing sections, so | |
11142 | that .previous works correctly. We could do something like check | |
b6ff326e | 11143 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
11144 | as it would not be appropriate to use it in the section changing |
11145 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
11146 | This should be cleaner, somehow. */ | |
11147 | obj_elf_section_change_hook (); | |
11148 | #endif | |
11149 | ||
b34976b6 | 11150 | mips_emit_delays (FALSE); |
252b5132 RH |
11151 | switch (sec) |
11152 | { | |
11153 | case 't': | |
11154 | s_text (0); | |
11155 | break; | |
11156 | case 'd': | |
11157 | s_data (0); | |
11158 | break; | |
11159 | case 'b': | |
11160 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
11161 | demand_empty_rest_of_line (); | |
11162 | break; | |
11163 | ||
11164 | case 'r': | |
4d0d148d TS |
11165 | seg = subseg_new (RDATA_SECTION_NAME, |
11166 | (subsegT) get_absolute_expression ()); | |
11167 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
252b5132 | 11168 | { |
4d0d148d TS |
11169 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
11170 | | SEC_READONLY | SEC_RELOC | |
11171 | | SEC_DATA)); | |
11172 | if (strcmp (TARGET_OS, "elf") != 0) | |
11173 | record_alignment (seg, 4); | |
252b5132 | 11174 | } |
4d0d148d | 11175 | demand_empty_rest_of_line (); |
252b5132 RH |
11176 | break; |
11177 | ||
11178 | case 's': | |
4d0d148d TS |
11179 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
11180 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
252b5132 | 11181 | { |
4d0d148d TS |
11182 | bfd_set_section_flags (stdoutput, seg, |
11183 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
11184 | if (strcmp (TARGET_OS, "elf") != 0) | |
11185 | record_alignment (seg, 4); | |
252b5132 | 11186 | } |
4d0d148d TS |
11187 | demand_empty_rest_of_line (); |
11188 | break; | |
252b5132 RH |
11189 | } |
11190 | ||
11191 | auto_align = 1; | |
11192 | } | |
b34976b6 | 11193 | |
cca86cc8 | 11194 | void |
17a2f251 | 11195 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 11196 | { |
7ed4a06a | 11197 | #ifdef OBJ_ELF |
cca86cc8 SC |
11198 | char *section_name; |
11199 | char c; | |
684022ea | 11200 | char next_c = 0; |
cca86cc8 SC |
11201 | int section_type; |
11202 | int section_flag; | |
11203 | int section_entry_size; | |
11204 | int section_alignment; | |
b34976b6 | 11205 | |
7ed4a06a TS |
11206 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
11207 | return; | |
11208 | ||
cca86cc8 SC |
11209 | section_name = input_line_pointer; |
11210 | c = get_symbol_end (); | |
a816d1ed AO |
11211 | if (c) |
11212 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 11213 | |
4cf0dd0d TS |
11214 | /* Do we have .section Name<,"flags">? */ |
11215 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 11216 | { |
4cf0dd0d TS |
11217 | /* just after name is now '\0'. */ |
11218 | *input_line_pointer = c; | |
cca86cc8 SC |
11219 | input_line_pointer = section_name; |
11220 | obj_elf_section (ignore); | |
11221 | return; | |
11222 | } | |
11223 | input_line_pointer++; | |
11224 | ||
11225 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
11226 | if (c == ',') | |
11227 | section_type = get_absolute_expression (); | |
11228 | else | |
11229 | section_type = 0; | |
11230 | if (*input_line_pointer++ == ',') | |
11231 | section_flag = get_absolute_expression (); | |
11232 | else | |
11233 | section_flag = 0; | |
11234 | if (*input_line_pointer++ == ',') | |
11235 | section_entry_size = get_absolute_expression (); | |
11236 | else | |
11237 | section_entry_size = 0; | |
11238 | if (*input_line_pointer++ == ',') | |
11239 | section_alignment = get_absolute_expression (); | |
11240 | else | |
11241 | section_alignment = 0; | |
11242 | ||
a816d1ed AO |
11243 | section_name = xstrdup (section_name); |
11244 | ||
8ab8a5c8 RS |
11245 | /* When using the generic form of .section (as implemented by obj-elf.c), |
11246 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
11247 | traditionally had to fall back on the more common @progbits instead. | |
11248 | ||
11249 | There's nothing really harmful in this, since bfd will correct | |
11250 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
11251 | means that, for backwards compatibiltiy, the special_section entries | |
11252 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. | |
11253 | ||
11254 | Even so, we shouldn't force users of the MIPS .section syntax to | |
11255 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
11256 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
11257 | generic type-checking code. */ | |
11258 | if (section_type == SHT_MIPS_DWARF) | |
11259 | section_type = SHT_PROGBITS; | |
11260 | ||
cca86cc8 SC |
11261 | obj_elf_change_section (section_name, section_type, section_flag, |
11262 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
11263 | |
11264 | if (now_seg->name != section_name) | |
11265 | free (section_name); | |
7ed4a06a | 11266 | #endif /* OBJ_ELF */ |
cca86cc8 | 11267 | } |
252b5132 RH |
11268 | |
11269 | void | |
17a2f251 | 11270 | mips_enable_auto_align (void) |
252b5132 RH |
11271 | { |
11272 | auto_align = 1; | |
11273 | } | |
11274 | ||
11275 | static void | |
17a2f251 | 11276 | s_cons (int log_size) |
252b5132 RH |
11277 | { |
11278 | symbolS *label; | |
11279 | ||
11280 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
b34976b6 | 11281 | mips_emit_delays (FALSE); |
252b5132 RH |
11282 | if (log_size > 0 && auto_align) |
11283 | mips_align (log_size, 0, label); | |
11284 | mips_clear_insn_labels (); | |
11285 | cons (1 << log_size); | |
11286 | } | |
11287 | ||
11288 | static void | |
17a2f251 | 11289 | s_float_cons (int type) |
252b5132 RH |
11290 | { |
11291 | symbolS *label; | |
11292 | ||
11293 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
11294 | ||
b34976b6 | 11295 | mips_emit_delays (FALSE); |
252b5132 RH |
11296 | |
11297 | if (auto_align) | |
49309057 ILT |
11298 | { |
11299 | if (type == 'd') | |
11300 | mips_align (3, 0, label); | |
11301 | else | |
11302 | mips_align (2, 0, label); | |
11303 | } | |
252b5132 RH |
11304 | |
11305 | mips_clear_insn_labels (); | |
11306 | ||
11307 | float_cons (type); | |
11308 | } | |
11309 | ||
11310 | /* Handle .globl. We need to override it because on Irix 5 you are | |
11311 | permitted to say | |
11312 | .globl foo .text | |
11313 | where foo is an undefined symbol, to mean that foo should be | |
11314 | considered to be the address of a function. */ | |
11315 | ||
11316 | static void | |
17a2f251 | 11317 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11318 | { |
11319 | char *name; | |
11320 | int c; | |
11321 | symbolS *symbolP; | |
11322 | flagword flag; | |
11323 | ||
11324 | name = input_line_pointer; | |
11325 | c = get_symbol_end (); | |
11326 | symbolP = symbol_find_or_make (name); | |
11327 | *input_line_pointer = c; | |
11328 | SKIP_WHITESPACE (); | |
11329 | ||
11330 | /* On Irix 5, every global symbol that is not explicitly labelled as | |
11331 | being a function is apparently labelled as being an object. */ | |
11332 | flag = BSF_OBJECT; | |
11333 | ||
11334 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
11335 | { | |
11336 | char *secname; | |
11337 | asection *sec; | |
11338 | ||
11339 | secname = input_line_pointer; | |
11340 | c = get_symbol_end (); | |
11341 | sec = bfd_get_section_by_name (stdoutput, secname); | |
11342 | if (sec == NULL) | |
11343 | as_bad (_("%s: no such section"), secname); | |
11344 | *input_line_pointer = c; | |
11345 | ||
11346 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
11347 | flag = BSF_FUNCTION; | |
11348 | } | |
11349 | ||
49309057 | 11350 | symbol_get_bfdsym (symbolP)->flags |= flag; |
252b5132 RH |
11351 | |
11352 | S_SET_EXTERNAL (symbolP); | |
11353 | demand_empty_rest_of_line (); | |
11354 | } | |
11355 | ||
11356 | static void | |
17a2f251 | 11357 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11358 | { |
11359 | char *opt; | |
11360 | char c; | |
11361 | ||
11362 | opt = input_line_pointer; | |
11363 | c = get_symbol_end (); | |
11364 | ||
11365 | if (*opt == 'O') | |
11366 | { | |
11367 | /* FIXME: What does this mean? */ | |
11368 | } | |
11369 | else if (strncmp (opt, "pic", 3) == 0) | |
11370 | { | |
11371 | int i; | |
11372 | ||
11373 | i = atoi (opt + 3); | |
11374 | if (i == 0) | |
11375 | mips_pic = NO_PIC; | |
11376 | else if (i == 2) | |
143d77c5 | 11377 | { |
252b5132 | 11378 | mips_pic = SVR4_PIC; |
143d77c5 EC |
11379 | mips_abicalls = TRUE; |
11380 | } | |
252b5132 RH |
11381 | else |
11382 | as_bad (_(".option pic%d not supported"), i); | |
11383 | ||
4d0d148d | 11384 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
11385 | { |
11386 | if (g_switch_seen && g_switch_value != 0) | |
11387 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
11388 | g_switch_value = 0; | |
11389 | bfd_set_gp_size (stdoutput, 0); | |
11390 | } | |
11391 | } | |
11392 | else | |
11393 | as_warn (_("Unrecognized option \"%s\""), opt); | |
11394 | ||
11395 | *input_line_pointer = c; | |
11396 | demand_empty_rest_of_line (); | |
11397 | } | |
11398 | ||
11399 | /* This structure is used to hold a stack of .set values. */ | |
11400 | ||
e972090a NC |
11401 | struct mips_option_stack |
11402 | { | |
252b5132 RH |
11403 | struct mips_option_stack *next; |
11404 | struct mips_set_options options; | |
11405 | }; | |
11406 | ||
11407 | static struct mips_option_stack *mips_opts_stack; | |
11408 | ||
11409 | /* Handle the .set pseudo-op. */ | |
11410 | ||
11411 | static void | |
17a2f251 | 11412 | s_mipsset (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
11413 | { |
11414 | char *name = input_line_pointer, ch; | |
11415 | ||
11416 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 11417 | ++input_line_pointer; |
252b5132 RH |
11418 | ch = *input_line_pointer; |
11419 | *input_line_pointer = '\0'; | |
11420 | ||
11421 | if (strcmp (name, "reorder") == 0) | |
11422 | { | |
11423 | if (mips_opts.noreorder && prev_nop_frag != NULL) | |
11424 | { | |
11425 | /* If we still have pending nops, we can discard them. The | |
11426 | usual nop handling will insert any that are still | |
bdaaa2e1 | 11427 | needed. */ |
252b5132 RH |
11428 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds |
11429 | * (mips_opts.mips16 ? 2 : 4)); | |
11430 | prev_nop_frag = NULL; | |
11431 | } | |
11432 | mips_opts.noreorder = 0; | |
11433 | } | |
11434 | else if (strcmp (name, "noreorder") == 0) | |
11435 | { | |
b34976b6 | 11436 | mips_emit_delays (TRUE); |
252b5132 RH |
11437 | mips_opts.noreorder = 1; |
11438 | mips_any_noreorder = 1; | |
11439 | } | |
11440 | else if (strcmp (name, "at") == 0) | |
11441 | { | |
11442 | mips_opts.noat = 0; | |
11443 | } | |
11444 | else if (strcmp (name, "noat") == 0) | |
11445 | { | |
11446 | mips_opts.noat = 1; | |
11447 | } | |
11448 | else if (strcmp (name, "macro") == 0) | |
11449 | { | |
11450 | mips_opts.warn_about_macros = 0; | |
11451 | } | |
11452 | else if (strcmp (name, "nomacro") == 0) | |
11453 | { | |
11454 | if (mips_opts.noreorder == 0) | |
11455 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
11456 | mips_opts.warn_about_macros = 1; | |
11457 | } | |
11458 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
11459 | { | |
11460 | mips_opts.nomove = 0; | |
11461 | } | |
11462 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
11463 | { | |
11464 | mips_opts.nomove = 1; | |
11465 | } | |
11466 | else if (strcmp (name, "bopt") == 0) | |
11467 | { | |
11468 | mips_opts.nobopt = 0; | |
11469 | } | |
11470 | else if (strcmp (name, "nobopt") == 0) | |
11471 | { | |
11472 | mips_opts.nobopt = 1; | |
11473 | } | |
11474 | else if (strcmp (name, "mips16") == 0 | |
11475 | || strcmp (name, "MIPS-16") == 0) | |
11476 | mips_opts.mips16 = 1; | |
11477 | else if (strcmp (name, "nomips16") == 0 | |
11478 | || strcmp (name, "noMIPS-16") == 0) | |
11479 | mips_opts.mips16 = 0; | |
1f25f5d3 CD |
11480 | else if (strcmp (name, "mips3d") == 0) |
11481 | mips_opts.ase_mips3d = 1; | |
11482 | else if (strcmp (name, "nomips3d") == 0) | |
11483 | mips_opts.ase_mips3d = 0; | |
a4672219 TS |
11484 | else if (strcmp (name, "mdmx") == 0) |
11485 | mips_opts.ase_mdmx = 1; | |
11486 | else if (strcmp (name, "nomdmx") == 0) | |
11487 | mips_opts.ase_mdmx = 0; | |
1a2c1fad | 11488 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 11489 | { |
af7ee8bf | 11490 | int reset = 0; |
252b5132 | 11491 | |
1a2c1fad CD |
11492 | /* Permit the user to change the ISA and architecture on the fly. |
11493 | Needless to say, misuse can cause serious problems. */ | |
81a21e38 | 11494 | if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) |
af7ee8bf CD |
11495 | { |
11496 | reset = 1; | |
11497 | mips_opts.isa = file_mips_isa; | |
1a2c1fad | 11498 | mips_opts.arch = file_mips_arch; |
1a2c1fad CD |
11499 | } |
11500 | else if (strncmp (name, "arch=", 5) == 0) | |
11501 | { | |
11502 | const struct mips_cpu_info *p; | |
11503 | ||
11504 | p = mips_parse_cpu("internal use", name + 5); | |
11505 | if (!p) | |
11506 | as_bad (_("unknown architecture %s"), name + 5); | |
11507 | else | |
11508 | { | |
11509 | mips_opts.arch = p->cpu; | |
11510 | mips_opts.isa = p->isa; | |
11511 | } | |
11512 | } | |
81a21e38 TS |
11513 | else if (strncmp (name, "mips", 4) == 0) |
11514 | { | |
11515 | const struct mips_cpu_info *p; | |
11516 | ||
11517 | p = mips_parse_cpu("internal use", name); | |
11518 | if (!p) | |
11519 | as_bad (_("unknown ISA level %s"), name + 4); | |
11520 | else | |
11521 | { | |
11522 | mips_opts.arch = p->cpu; | |
11523 | mips_opts.isa = p->isa; | |
11524 | } | |
11525 | } | |
af7ee8bf | 11526 | else |
81a21e38 | 11527 | as_bad (_("unknown ISA or architecture %s"), name); |
af7ee8bf CD |
11528 | |
11529 | switch (mips_opts.isa) | |
98d3f06f KH |
11530 | { |
11531 | case 0: | |
98d3f06f | 11532 | break; |
af7ee8bf CD |
11533 | case ISA_MIPS1: |
11534 | case ISA_MIPS2: | |
11535 | case ISA_MIPS32: | |
11536 | case ISA_MIPS32R2: | |
98d3f06f KH |
11537 | mips_opts.gp32 = 1; |
11538 | mips_opts.fp32 = 1; | |
11539 | break; | |
af7ee8bf CD |
11540 | case ISA_MIPS3: |
11541 | case ISA_MIPS4: | |
11542 | case ISA_MIPS5: | |
11543 | case ISA_MIPS64: | |
5f74bc13 | 11544 | case ISA_MIPS64R2: |
98d3f06f KH |
11545 | mips_opts.gp32 = 0; |
11546 | mips_opts.fp32 = 0; | |
11547 | break; | |
11548 | default: | |
11549 | as_bad (_("unknown ISA level %s"), name + 4); | |
11550 | break; | |
11551 | } | |
af7ee8bf | 11552 | if (reset) |
98d3f06f | 11553 | { |
af7ee8bf CD |
11554 | mips_opts.gp32 = file_mips_gp32; |
11555 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 11556 | } |
252b5132 RH |
11557 | } |
11558 | else if (strcmp (name, "autoextend") == 0) | |
11559 | mips_opts.noautoextend = 0; | |
11560 | else if (strcmp (name, "noautoextend") == 0) | |
11561 | mips_opts.noautoextend = 1; | |
11562 | else if (strcmp (name, "push") == 0) | |
11563 | { | |
11564 | struct mips_option_stack *s; | |
11565 | ||
11566 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
11567 | s->next = mips_opts_stack; | |
11568 | s->options = mips_opts; | |
11569 | mips_opts_stack = s; | |
11570 | } | |
11571 | else if (strcmp (name, "pop") == 0) | |
11572 | { | |
11573 | struct mips_option_stack *s; | |
11574 | ||
11575 | s = mips_opts_stack; | |
11576 | if (s == NULL) | |
11577 | as_bad (_(".set pop with no .set push")); | |
11578 | else | |
11579 | { | |
11580 | /* If we're changing the reorder mode we need to handle | |
11581 | delay slots correctly. */ | |
11582 | if (s->options.noreorder && ! mips_opts.noreorder) | |
b34976b6 | 11583 | mips_emit_delays (TRUE); |
252b5132 RH |
11584 | else if (! s->options.noreorder && mips_opts.noreorder) |
11585 | { | |
11586 | if (prev_nop_frag != NULL) | |
11587 | { | |
11588 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds | |
11589 | * (mips_opts.mips16 ? 2 : 4)); | |
11590 | prev_nop_frag = NULL; | |
11591 | } | |
11592 | } | |
11593 | ||
11594 | mips_opts = s->options; | |
11595 | mips_opts_stack = s->next; | |
11596 | free (s); | |
11597 | } | |
11598 | } | |
aed1a261 RS |
11599 | else if (strcmp (name, "sym32") == 0) |
11600 | mips_opts.sym32 = TRUE; | |
11601 | else if (strcmp (name, "nosym32") == 0) | |
11602 | mips_opts.sym32 = FALSE; | |
252b5132 RH |
11603 | else |
11604 | { | |
11605 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
11606 | } | |
11607 | *input_line_pointer = ch; | |
11608 | demand_empty_rest_of_line (); | |
11609 | } | |
11610 | ||
11611 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
11612 | .option pic2. It means to generate SVR4 PIC calls. */ | |
11613 | ||
11614 | static void | |
17a2f251 | 11615 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
11616 | { |
11617 | mips_pic = SVR4_PIC; | |
143d77c5 | 11618 | mips_abicalls = TRUE; |
4d0d148d TS |
11619 | |
11620 | if (g_switch_seen && g_switch_value != 0) | |
11621 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
11622 | g_switch_value = 0; | |
11623 | ||
252b5132 RH |
11624 | bfd_set_gp_size (stdoutput, 0); |
11625 | demand_empty_rest_of_line (); | |
11626 | } | |
11627 | ||
11628 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
11629 | PIC code. It sets the $gp register for the function based on the | |
11630 | function address, which is in the register named in the argument. | |
11631 | This uses a relocation against _gp_disp, which is handled specially | |
11632 | by the linker. The result is: | |
11633 | lui $gp,%hi(_gp_disp) | |
11634 | addiu $gp,$gp,%lo(_gp_disp) | |
11635 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
11636 | The .cpload argument is normally $25 == $t9. |
11637 | ||
11638 | The -mno-shared option changes this to: | |
bbe506e8 TS |
11639 | lui $gp,%hi(__gnu_local_gp) |
11640 | addiu $gp,$gp,%lo(__gnu_local_gp) | |
aa6975fb ILT |
11641 | and the argument is ignored. This saves an instruction, but the |
11642 | resulting code is not position independent; it uses an absolute | |
bbe506e8 TS |
11643 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
11644 | can go into an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
11645 | |
11646 | static void | |
17a2f251 | 11647 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
11648 | { |
11649 | expressionS ex; | |
aa6975fb ILT |
11650 | int reg; |
11651 | int in_shared; | |
252b5132 | 11652 | |
6478892d TS |
11653 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
11654 | .cpload is ignored. */ | |
11655 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
11656 | { |
11657 | s_ignore (0); | |
11658 | return; | |
11659 | } | |
11660 | ||
d3ecfc59 | 11661 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
11662 | if (mips_opts.noreorder == 0) |
11663 | as_warn (_(".cpload not in noreorder section")); | |
11664 | ||
aa6975fb ILT |
11665 | reg = tc_get_register (0); |
11666 | ||
11667 | /* If we need to produce a 64-bit address, we are better off using | |
11668 | the default instruction sequence. */ | |
aed1a261 | 11669 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
aa6975fb | 11670 | |
252b5132 | 11671 | ex.X_op = O_symbol; |
bbe506e8 TS |
11672 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
11673 | "__gnu_local_gp"); | |
252b5132 RH |
11674 | ex.X_op_symbol = NULL; |
11675 | ex.X_add_number = 0; | |
11676 | ||
11677 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 11678 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 11679 | |
584892a6 | 11680 | macro_start (); |
67c0d1eb RS |
11681 | macro_build_lui (&ex, mips_gp_register); |
11682 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 11683 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
11684 | if (in_shared) |
11685 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
11686 | mips_gp_register, reg); | |
584892a6 | 11687 | macro_end (); |
252b5132 RH |
11688 | |
11689 | demand_empty_rest_of_line (); | |
11690 | } | |
11691 | ||
6478892d TS |
11692 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
11693 | .cpsetup $reg1, offset|$reg2, label | |
11694 | ||
11695 | If offset is given, this results in: | |
11696 | sd $gp, offset($sp) | |
956cd1d6 | 11697 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
11698 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
11699 | daddu $gp, $gp, $reg1 | |
6478892d TS |
11700 | |
11701 | If $reg2 is given, this results in: | |
11702 | daddu $reg2, $gp, $0 | |
956cd1d6 | 11703 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
11704 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
11705 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
11706 | $reg1 is normally $25 == $t9. |
11707 | ||
11708 | The -mno-shared option replaces the last three instructions with | |
11709 | lui $gp,%hi(_gp) | |
11710 | addiu $gp,$gp,%lo(_gp) | |
11711 | */ | |
11712 | ||
6478892d | 11713 | static void |
17a2f251 | 11714 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
11715 | { |
11716 | expressionS ex_off; | |
11717 | expressionS ex_sym; | |
11718 | int reg1; | |
6478892d | 11719 | |
8586fc66 | 11720 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
11721 | We also need NewABI support. */ |
11722 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11723 | { | |
11724 | s_ignore (0); | |
11725 | return; | |
11726 | } | |
11727 | ||
11728 | reg1 = tc_get_register (0); | |
11729 | SKIP_WHITESPACE (); | |
11730 | if (*input_line_pointer != ',') | |
11731 | { | |
11732 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
11733 | return; | |
11734 | } | |
11735 | else | |
80245285 | 11736 | ++input_line_pointer; |
6478892d TS |
11737 | SKIP_WHITESPACE (); |
11738 | if (*input_line_pointer == '$') | |
80245285 TS |
11739 | { |
11740 | mips_cpreturn_register = tc_get_register (0); | |
11741 | mips_cpreturn_offset = -1; | |
11742 | } | |
6478892d | 11743 | else |
80245285 TS |
11744 | { |
11745 | mips_cpreturn_offset = get_absolute_expression (); | |
11746 | mips_cpreturn_register = -1; | |
11747 | } | |
6478892d TS |
11748 | SKIP_WHITESPACE (); |
11749 | if (*input_line_pointer != ',') | |
11750 | { | |
11751 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
11752 | return; | |
11753 | } | |
11754 | else | |
f9419b05 | 11755 | ++input_line_pointer; |
6478892d | 11756 | SKIP_WHITESPACE (); |
f21f8242 | 11757 | expression (&ex_sym); |
6478892d | 11758 | |
584892a6 | 11759 | macro_start (); |
6478892d TS |
11760 | if (mips_cpreturn_register == -1) |
11761 | { | |
11762 | ex_off.X_op = O_constant; | |
11763 | ex_off.X_add_symbol = NULL; | |
11764 | ex_off.X_op_symbol = NULL; | |
11765 | ex_off.X_add_number = mips_cpreturn_offset; | |
11766 | ||
67c0d1eb | 11767 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 11768 | BFD_RELOC_LO16, SP); |
6478892d TS |
11769 | } |
11770 | else | |
67c0d1eb | 11771 | macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, |
17a2f251 | 11772 | mips_gp_register, 0); |
6478892d | 11773 | |
aed1a261 | 11774 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
aa6975fb ILT |
11775 | { |
11776 | macro_build (&ex_sym, "lui", "t,u", mips_gp_register, | |
11777 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, | |
11778 | BFD_RELOC_HI16_S); | |
11779 | ||
11780 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
11781 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
11782 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
11783 | ||
11784 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
11785 | mips_gp_register, reg1); | |
11786 | } | |
11787 | else | |
11788 | { | |
11789 | expressionS ex; | |
11790 | ||
11791 | ex.X_op = O_symbol; | |
11792 | ex.X_add_symbol = symbol_find_or_make ("_gp"); | |
11793 | ex.X_op_symbol = NULL; | |
11794 | ex.X_add_number = 0; | |
6e1304d8 | 11795 | |
aa6975fb ILT |
11796 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
11797 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
11798 | ||
11799 | macro_build_lui (&ex, mips_gp_register); | |
11800 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
11801 | mips_gp_register, BFD_RELOC_LO16); | |
11802 | } | |
f21f8242 | 11803 | |
584892a6 | 11804 | macro_end (); |
6478892d TS |
11805 | |
11806 | demand_empty_rest_of_line (); | |
11807 | } | |
11808 | ||
11809 | static void | |
17a2f251 | 11810 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
11811 | { |
11812 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
11813 | .cplocal is ignored. */ | |
11814 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11815 | { | |
11816 | s_ignore (0); | |
11817 | return; | |
11818 | } | |
11819 | ||
11820 | mips_gp_register = tc_get_register (0); | |
85b51719 | 11821 | demand_empty_rest_of_line (); |
6478892d TS |
11822 | } |
11823 | ||
252b5132 RH |
11824 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
11825 | offset from $sp. The offset is remembered, and after making a PIC | |
11826 | call $gp is restored from that location. */ | |
11827 | ||
11828 | static void | |
17a2f251 | 11829 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
11830 | { |
11831 | expressionS ex; | |
252b5132 | 11832 | |
6478892d | 11833 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 11834 | .cprestore is ignored. */ |
6478892d | 11835 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
11836 | { |
11837 | s_ignore (0); | |
11838 | return; | |
11839 | } | |
11840 | ||
11841 | mips_cprestore_offset = get_absolute_expression (); | |
7a621144 | 11842 | mips_cprestore_valid = 1; |
252b5132 RH |
11843 | |
11844 | ex.X_op = O_constant; | |
11845 | ex.X_add_symbol = NULL; | |
11846 | ex.X_op_symbol = NULL; | |
11847 | ex.X_add_number = mips_cprestore_offset; | |
11848 | ||
584892a6 | 11849 | macro_start (); |
67c0d1eb RS |
11850 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
11851 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 11852 | macro_end (); |
252b5132 RH |
11853 | |
11854 | demand_empty_rest_of_line (); | |
11855 | } | |
11856 | ||
6478892d | 11857 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 11858 | was given in the preceding .cpsetup, it results in: |
6478892d | 11859 | ld $gp, offset($sp) |
76b3015f | 11860 | |
6478892d | 11861 | If a register $reg2 was given there, it results in: |
609f23f4 | 11862 | daddu $gp, $reg2, $0 |
6478892d TS |
11863 | */ |
11864 | static void | |
17a2f251 | 11865 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
11866 | { |
11867 | expressionS ex; | |
6478892d TS |
11868 | |
11869 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
11870 | We also need NewABI support. */ | |
11871 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11872 | { | |
11873 | s_ignore (0); | |
11874 | return; | |
11875 | } | |
11876 | ||
584892a6 | 11877 | macro_start (); |
6478892d TS |
11878 | if (mips_cpreturn_register == -1) |
11879 | { | |
11880 | ex.X_op = O_constant; | |
11881 | ex.X_add_symbol = NULL; | |
11882 | ex.X_op_symbol = NULL; | |
11883 | ex.X_add_number = mips_cpreturn_offset; | |
11884 | ||
67c0d1eb | 11885 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
11886 | } |
11887 | else | |
67c0d1eb | 11888 | macro_build (NULL, "daddu", "d,v,t", mips_gp_register, |
17a2f251 | 11889 | mips_cpreturn_register, 0); |
584892a6 | 11890 | macro_end (); |
6478892d TS |
11891 | |
11892 | demand_empty_rest_of_line (); | |
11893 | } | |
11894 | ||
11895 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC | |
11896 | code. It sets the offset to use in gp_rel relocations. */ | |
11897 | ||
11898 | static void | |
17a2f251 | 11899 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
11900 | { |
11901 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
11902 | We also need NewABI support. */ | |
11903 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
11904 | { | |
11905 | s_ignore (0); | |
11906 | return; | |
11907 | } | |
11908 | ||
def2e0dd | 11909 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
11910 | |
11911 | demand_empty_rest_of_line (); | |
11912 | } | |
11913 | ||
252b5132 RH |
11914 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
11915 | code. It generates a 32 bit GP relative reloc. */ | |
11916 | ||
11917 | static void | |
17a2f251 | 11918 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
11919 | { |
11920 | symbolS *label; | |
11921 | expressionS ex; | |
11922 | char *p; | |
11923 | ||
11924 | /* When not generating PIC code, this is treated as .word. */ | |
11925 | if (mips_pic != SVR4_PIC) | |
11926 | { | |
11927 | s_cons (2); | |
11928 | return; | |
11929 | } | |
11930 | ||
11931 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
b34976b6 | 11932 | mips_emit_delays (TRUE); |
252b5132 RH |
11933 | if (auto_align) |
11934 | mips_align (2, 0, label); | |
11935 | mips_clear_insn_labels (); | |
11936 | ||
11937 | expression (&ex); | |
11938 | ||
11939 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
11940 | { | |
11941 | as_bad (_("Unsupported use of .gpword")); | |
11942 | ignore_rest_of_line (); | |
11943 | } | |
11944 | ||
11945 | p = frag_more (4); | |
17a2f251 | 11946 | md_number_to_chars (p, 0, 4); |
b34976b6 | 11947 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 11948 | BFD_RELOC_GPREL32); |
252b5132 RH |
11949 | |
11950 | demand_empty_rest_of_line (); | |
11951 | } | |
11952 | ||
10181a0d | 11953 | static void |
17a2f251 | 11954 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d AO |
11955 | { |
11956 | symbolS *label; | |
11957 | expressionS ex; | |
11958 | char *p; | |
11959 | ||
11960 | /* When not generating PIC code, this is treated as .dword. */ | |
11961 | if (mips_pic != SVR4_PIC) | |
11962 | { | |
11963 | s_cons (3); | |
11964 | return; | |
11965 | } | |
11966 | ||
11967 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
b34976b6 | 11968 | mips_emit_delays (TRUE); |
10181a0d AO |
11969 | if (auto_align) |
11970 | mips_align (3, 0, label); | |
11971 | mips_clear_insn_labels (); | |
11972 | ||
11973 | expression (&ex); | |
11974 | ||
11975 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
11976 | { | |
11977 | as_bad (_("Unsupported use of .gpdword")); | |
11978 | ignore_rest_of_line (); | |
11979 | } | |
11980 | ||
11981 | p = frag_more (8); | |
17a2f251 | 11982 | md_number_to_chars (p, 0, 8); |
a105a300 | 11983 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 11984 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
11985 | |
11986 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
11987 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
11988 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
11989 | |
11990 | demand_empty_rest_of_line (); | |
11991 | } | |
11992 | ||
252b5132 RH |
11993 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
11994 | tables in SVR4 PIC code. */ | |
11995 | ||
11996 | static void | |
17a2f251 | 11997 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 11998 | { |
252b5132 RH |
11999 | int reg; |
12000 | ||
10181a0d AO |
12001 | /* This is ignored when not generating SVR4 PIC code. */ |
12002 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
12003 | { |
12004 | s_ignore (0); | |
12005 | return; | |
12006 | } | |
12007 | ||
12008 | /* Add $gp to the register named as an argument. */ | |
584892a6 | 12009 | macro_start (); |
252b5132 | 12010 | reg = tc_get_register (0); |
67c0d1eb | 12011 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 12012 | macro_end (); |
252b5132 | 12013 | |
bdaaa2e1 | 12014 | demand_empty_rest_of_line (); |
252b5132 RH |
12015 | } |
12016 | ||
12017 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
12018 | mips16 mode. This permits the linker to handle them specially, | |
12019 | such as generating jalx instructions when needed. We also make | |
12020 | them odd for the duration of the assembly, in order to generate the | |
12021 | right sort of code. We will make them even in the adjust_symtab | |
12022 | routine, while leaving them marked. This is convenient for the | |
12023 | debugger and the disassembler. The linker knows to make them odd | |
12024 | again. */ | |
12025 | ||
12026 | static void | |
17a2f251 | 12027 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 12028 | { |
f9419b05 | 12029 | mips16_mark_labels (); |
252b5132 RH |
12030 | |
12031 | demand_empty_rest_of_line (); | |
12032 | } | |
12033 | ||
12034 | /* Handle a .stabn directive. We need these in order to mark a label | |
12035 | as being a mips16 text label correctly. Sometimes the compiler | |
12036 | will emit a label, followed by a .stabn, and then switch sections. | |
12037 | If the label and .stabn are in mips16 mode, then the label is | |
12038 | really a mips16 text label. */ | |
12039 | ||
12040 | static void | |
17a2f251 | 12041 | s_mips_stab (int type) |
252b5132 | 12042 | { |
f9419b05 | 12043 | if (type == 'n') |
252b5132 RH |
12044 | mips16_mark_labels (); |
12045 | ||
12046 | s_stab (type); | |
12047 | } | |
12048 | ||
12049 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. | |
12050 | */ | |
12051 | ||
12052 | static void | |
17a2f251 | 12053 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
12054 | { |
12055 | char *name; | |
12056 | int c; | |
12057 | symbolS *symbolP; | |
12058 | expressionS exp; | |
12059 | ||
12060 | name = input_line_pointer; | |
12061 | c = get_symbol_end (); | |
12062 | symbolP = symbol_find_or_make (name); | |
12063 | S_SET_WEAK (symbolP); | |
12064 | *input_line_pointer = c; | |
12065 | ||
12066 | SKIP_WHITESPACE (); | |
12067 | ||
12068 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
12069 | { | |
12070 | if (S_IS_DEFINED (symbolP)) | |
12071 | { | |
956cd1d6 | 12072 | as_bad ("ignoring attempt to redefine symbol %s", |
252b5132 RH |
12073 | S_GET_NAME (symbolP)); |
12074 | ignore_rest_of_line (); | |
12075 | return; | |
12076 | } | |
bdaaa2e1 | 12077 | |
252b5132 RH |
12078 | if (*input_line_pointer == ',') |
12079 | { | |
12080 | ++input_line_pointer; | |
12081 | SKIP_WHITESPACE (); | |
12082 | } | |
bdaaa2e1 | 12083 | |
252b5132 RH |
12084 | expression (&exp); |
12085 | if (exp.X_op != O_symbol) | |
12086 | { | |
12087 | as_bad ("bad .weakext directive"); | |
98d3f06f | 12088 | ignore_rest_of_line (); |
252b5132 RH |
12089 | return; |
12090 | } | |
49309057 | 12091 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
12092 | } |
12093 | ||
12094 | demand_empty_rest_of_line (); | |
12095 | } | |
12096 | ||
12097 | /* Parse a register string into a number. Called from the ECOFF code | |
12098 | to parse .frame. The argument is non-zero if this is the frame | |
12099 | register, so that we can record it in mips_frame_reg. */ | |
12100 | ||
12101 | int | |
17a2f251 | 12102 | tc_get_register (int frame) |
252b5132 RH |
12103 | { |
12104 | int reg; | |
12105 | ||
12106 | SKIP_WHITESPACE (); | |
12107 | if (*input_line_pointer++ != '$') | |
12108 | { | |
12109 | as_warn (_("expected `$'")); | |
85b51719 | 12110 | reg = ZERO; |
252b5132 | 12111 | } |
3882b010 | 12112 | else if (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
12113 | { |
12114 | reg = get_absolute_expression (); | |
12115 | if (reg < 0 || reg >= 32) | |
12116 | { | |
12117 | as_warn (_("Bad register number")); | |
85b51719 | 12118 | reg = ZERO; |
252b5132 RH |
12119 | } |
12120 | } | |
12121 | else | |
12122 | { | |
76db943d | 12123 | if (strncmp (input_line_pointer, "ra", 2) == 0) |
85b51719 TS |
12124 | { |
12125 | reg = RA; | |
12126 | input_line_pointer += 2; | |
12127 | } | |
76db943d | 12128 | else if (strncmp (input_line_pointer, "fp", 2) == 0) |
85b51719 TS |
12129 | { |
12130 | reg = FP; | |
12131 | input_line_pointer += 2; | |
12132 | } | |
252b5132 | 12133 | else if (strncmp (input_line_pointer, "sp", 2) == 0) |
85b51719 TS |
12134 | { |
12135 | reg = SP; | |
12136 | input_line_pointer += 2; | |
12137 | } | |
252b5132 | 12138 | else if (strncmp (input_line_pointer, "gp", 2) == 0) |
85b51719 TS |
12139 | { |
12140 | reg = GP; | |
12141 | input_line_pointer += 2; | |
12142 | } | |
252b5132 | 12143 | else if (strncmp (input_line_pointer, "at", 2) == 0) |
85b51719 TS |
12144 | { |
12145 | reg = AT; | |
12146 | input_line_pointer += 2; | |
12147 | } | |
12148 | else if (strncmp (input_line_pointer, "kt0", 3) == 0) | |
12149 | { | |
12150 | reg = KT0; | |
12151 | input_line_pointer += 3; | |
12152 | } | |
12153 | else if (strncmp (input_line_pointer, "kt1", 3) == 0) | |
12154 | { | |
12155 | reg = KT1; | |
12156 | input_line_pointer += 3; | |
12157 | } | |
12158 | else if (strncmp (input_line_pointer, "zero", 4) == 0) | |
12159 | { | |
12160 | reg = ZERO; | |
12161 | input_line_pointer += 4; | |
12162 | } | |
252b5132 RH |
12163 | else |
12164 | { | |
12165 | as_warn (_("Unrecognized register name")); | |
85b51719 TS |
12166 | reg = ZERO; |
12167 | while (ISALNUM(*input_line_pointer)) | |
12168 | input_line_pointer++; | |
252b5132 | 12169 | } |
252b5132 RH |
12170 | } |
12171 | if (frame) | |
7a621144 DJ |
12172 | { |
12173 | mips_frame_reg = reg != 0 ? reg : SP; | |
12174 | mips_frame_reg_valid = 1; | |
12175 | mips_cprestore_valid = 0; | |
12176 | } | |
252b5132 RH |
12177 | return reg; |
12178 | } | |
12179 | ||
12180 | valueT | |
17a2f251 | 12181 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
12182 | { |
12183 | int align = bfd_get_section_alignment (stdoutput, seg); | |
12184 | ||
12185 | #ifdef OBJ_ELF | |
12186 | /* We don't need to align ELF sections to the full alignment. | |
12187 | However, Irix 5 may prefer that we align them at least to a 16 | |
12188 | byte boundary. We don't bother to align the sections if we are | |
12189 | targeted for an embedded system. */ | |
12190 | if (strcmp (TARGET_OS, "elf") == 0) | |
12191 | return addr; | |
12192 | if (align > 4) | |
12193 | align = 4; | |
12194 | #endif | |
12195 | ||
12196 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
12197 | } | |
12198 | ||
12199 | /* Utility routine, called from above as well. If called while the | |
12200 | input file is still being read, it's only an approximation. (For | |
12201 | example, a symbol may later become defined which appeared to be | |
12202 | undefined earlier.) */ | |
12203 | ||
12204 | static int | |
17a2f251 | 12205 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
12206 | { |
12207 | if (sym == 0) | |
12208 | return 0; | |
12209 | ||
4d0d148d | 12210 | if (g_switch_value > 0) |
252b5132 RH |
12211 | { |
12212 | const char *symname; | |
12213 | int change; | |
12214 | ||
c9914766 | 12215 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
12216 | register. It can be if it is smaller than the -G size or if |
12217 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 12218 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
12219 | they can. */ |
12220 | symname = S_GET_NAME (sym); | |
12221 | if (symname != (const char *) NULL | |
12222 | && (strcmp (symname, "eprol") == 0 | |
12223 | || strcmp (symname, "etext") == 0 | |
12224 | || strcmp (symname, "_gp") == 0 | |
12225 | || strcmp (symname, "edata") == 0 | |
12226 | || strcmp (symname, "_fbss") == 0 | |
12227 | || strcmp (symname, "_fdata") == 0 | |
12228 | || strcmp (symname, "_ftext") == 0 | |
12229 | || strcmp (symname, "end") == 0 | |
12230 | || strcmp (symname, "_gp_disp") == 0)) | |
12231 | change = 1; | |
12232 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
12233 | && (0 | |
12234 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
12235 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
12236 | && (symbol_get_obj (sym)->ecoff_extern_size | |
12237 | <= g_switch_value)) | |
252b5132 RH |
12238 | #endif |
12239 | /* We must defer this decision until after the whole | |
12240 | file has been read, since there might be a .extern | |
12241 | after the first use of this symbol. */ | |
12242 | || (before_relaxing | |
12243 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 12244 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
12245 | #endif |
12246 | && S_GET_VALUE (sym) == 0) | |
12247 | || (S_GET_VALUE (sym) != 0 | |
12248 | && S_GET_VALUE (sym) <= g_switch_value))) | |
12249 | change = 0; | |
12250 | else | |
12251 | { | |
12252 | const char *segname; | |
12253 | ||
12254 | segname = segment_name (S_GET_SEGMENT (sym)); | |
12255 | assert (strcmp (segname, ".lit8") != 0 | |
12256 | && strcmp (segname, ".lit4") != 0); | |
12257 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
12258 | && strcmp (segname, ".sbss") != 0 |
12259 | && strncmp (segname, ".sdata.", 7) != 0 | |
12260 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); | |
252b5132 RH |
12261 | } |
12262 | return change; | |
12263 | } | |
12264 | else | |
c9914766 | 12265 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
12266 | return 1; |
12267 | } | |
12268 | ||
5919d012 RS |
12269 | |
12270 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
12271 | ||
12272 | static bfd_boolean | |
17a2f251 | 12273 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
12274 | { |
12275 | asection *symsec; | |
12276 | bfd_boolean linkonce; | |
12277 | ||
12278 | /* Handle the case of a symbol equated to another symbol. */ | |
12279 | while (symbol_equated_reloc_p (sym)) | |
12280 | { | |
12281 | symbolS *n; | |
12282 | ||
12283 | /* It's possible to get a loop here in a badly written | |
12284 | program. */ | |
12285 | n = symbol_get_value_expression (sym)->X_add_symbol; | |
12286 | if (n == sym) | |
12287 | break; | |
12288 | sym = n; | |
12289 | } | |
12290 | ||
12291 | symsec = S_GET_SEGMENT (sym); | |
12292 | ||
12293 | /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */ | |
12294 | linkonce = FALSE; | |
12295 | if (symsec != segtype && ! S_IS_LOCAL (sym)) | |
12296 | { | |
12297 | if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE) | |
12298 | != 0) | |
12299 | linkonce = TRUE; | |
12300 | ||
12301 | /* The GNU toolchain uses an extension for ELF: a section | |
12302 | beginning with the magic string .gnu.linkonce is a linkonce | |
12303 | section. */ | |
12304 | if (strncmp (segment_name (symsec), ".gnu.linkonce", | |
12305 | sizeof ".gnu.linkonce" - 1) == 0) | |
12306 | linkonce = TRUE; | |
12307 | } | |
12308 | ||
12309 | /* This must duplicate the test in adjust_reloc_syms. */ | |
12310 | return (symsec != &bfd_und_section | |
12311 | && symsec != &bfd_abs_section | |
12312 | && ! bfd_is_com_section (symsec) | |
12313 | && !linkonce | |
12314 | #ifdef OBJ_ELF | |
12315 | /* A global or weak symbol is treated as external. */ | |
12316 | && (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
3e722fb5 | 12317 | || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym))) |
5919d012 RS |
12318 | #endif |
12319 | ); | |
12320 | } | |
12321 | ||
12322 | ||
252b5132 RH |
12323 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
12324 | extended opcode. SEC is the section the frag is in. */ | |
12325 | ||
12326 | static int | |
17a2f251 | 12327 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
12328 | { |
12329 | int type; | |
12330 | register const struct mips16_immed_operand *op; | |
12331 | offsetT val; | |
12332 | int mintiny, maxtiny; | |
12333 | segT symsec; | |
98aa84af | 12334 | fragS *sym_frag; |
252b5132 RH |
12335 | |
12336 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
12337 | return 0; | |
12338 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
12339 | return 1; | |
12340 | ||
12341 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
12342 | op = mips16_immed_operands; | |
12343 | while (op->type != type) | |
12344 | { | |
12345 | ++op; | |
12346 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
12347 | } | |
12348 | ||
12349 | if (op->unsp) | |
12350 | { | |
12351 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
12352 | { | |
12353 | mintiny = 1; | |
12354 | maxtiny = 1 << op->nbits; | |
12355 | } | |
12356 | else | |
12357 | { | |
12358 | mintiny = 0; | |
12359 | maxtiny = (1 << op->nbits) - 1; | |
12360 | } | |
12361 | } | |
12362 | else | |
12363 | { | |
12364 | mintiny = - (1 << (op->nbits - 1)); | |
12365 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
12366 | } | |
12367 | ||
98aa84af | 12368 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 12369 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 12370 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
12371 | |
12372 | if (op->pcrel) | |
12373 | { | |
12374 | addressT addr; | |
12375 | ||
12376 | /* We won't have the section when we are called from | |
12377 | mips_relax_frag. However, we will always have been called | |
12378 | from md_estimate_size_before_relax first. If this is a | |
12379 | branch to a different section, we mark it as such. If SEC is | |
12380 | NULL, and the frag is not marked, then it must be a branch to | |
12381 | the same section. */ | |
12382 | if (sec == NULL) | |
12383 | { | |
12384 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
12385 | return 1; | |
12386 | } | |
12387 | else | |
12388 | { | |
98aa84af | 12389 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
12390 | if (symsec != sec) |
12391 | { | |
12392 | fragp->fr_subtype = | |
12393 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12394 | ||
12395 | /* FIXME: We should support this, and let the linker | |
12396 | catch branches and loads that are out of range. */ | |
12397 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
12398 | _("unsupported PC relative reference to different section")); | |
12399 | ||
12400 | return 1; | |
12401 | } | |
98aa84af AM |
12402 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
12403 | /* Assume non-extended on the first relaxation pass. | |
12404 | The address we have calculated will be bogus if this is | |
12405 | a forward branch to another frag, as the forward frag | |
12406 | will have fr_address == 0. */ | |
12407 | return 0; | |
252b5132 RH |
12408 | } |
12409 | ||
12410 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
12411 | the same section. If the relax_marker of the symbol fragment |
12412 | differs from the relax_marker of this fragment, we have not | |
12413 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
12414 | in STRETCH in order to get a better estimate of the address. |
12415 | This particularly matters because of the shift bits. */ | |
12416 | if (stretch != 0 | |
98aa84af | 12417 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
12418 | { |
12419 | fragS *f; | |
12420 | ||
12421 | /* Adjust stretch for any alignment frag. Note that if have | |
12422 | been expanding the earlier code, the symbol may be | |
12423 | defined in what appears to be an earlier frag. FIXME: | |
12424 | This doesn't handle the fr_subtype field, which specifies | |
12425 | a maximum number of bytes to skip when doing an | |
12426 | alignment. */ | |
98aa84af | 12427 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
12428 | { |
12429 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
12430 | { | |
12431 | if (stretch < 0) | |
12432 | stretch = - ((- stretch) | |
12433 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
12434 | else | |
12435 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
12436 | if (stretch == 0) | |
12437 | break; | |
12438 | } | |
12439 | } | |
12440 | if (f != NULL) | |
12441 | val += stretch; | |
12442 | } | |
12443 | ||
12444 | addr = fragp->fr_address + fragp->fr_fix; | |
12445 | ||
12446 | /* The base address rules are complicated. The base address of | |
12447 | a branch is the following instruction. The base address of a | |
12448 | PC relative load or add is the instruction itself, but if it | |
12449 | is in a delay slot (in which case it can not be extended) use | |
12450 | the address of the instruction whose delay slot it is in. */ | |
12451 | if (type == 'p' || type == 'q') | |
12452 | { | |
12453 | addr += 2; | |
12454 | ||
12455 | /* If we are currently assuming that this frag should be | |
12456 | extended, then, the current address is two bytes | |
bdaaa2e1 | 12457 | higher. */ |
252b5132 RH |
12458 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
12459 | addr += 2; | |
12460 | ||
12461 | /* Ignore the low bit in the target, since it will be set | |
12462 | for a text label. */ | |
12463 | if ((val & 1) != 0) | |
12464 | --val; | |
12465 | } | |
12466 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
12467 | addr -= 4; | |
12468 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
12469 | addr -= 2; | |
12470 | ||
12471 | val -= addr & ~ ((1 << op->shift) - 1); | |
12472 | ||
12473 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
12474 | if (type == 'p' || type == 'q') | |
12475 | val /= 2; | |
12476 | ||
12477 | /* If any of the shifted bits are set, we must use an extended | |
12478 | opcode. If the address depends on the size of this | |
12479 | instruction, this can lead to a loop, so we arrange to always | |
12480 | use an extended opcode. We only check this when we are in | |
12481 | the main relaxation loop, when SEC is NULL. */ | |
12482 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
12483 | { | |
12484 | fragp->fr_subtype = | |
12485 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12486 | return 1; | |
12487 | } | |
12488 | ||
12489 | /* If we are about to mark a frag as extended because the value | |
12490 | is precisely maxtiny + 1, then there is a chance of an | |
12491 | infinite loop as in the following code: | |
12492 | la $4,foo | |
12493 | .skip 1020 | |
12494 | .align 2 | |
12495 | foo: | |
12496 | In this case when the la is extended, foo is 0x3fc bytes | |
12497 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
12498 | the la must be extended. To avoid this loop, we mark the | |
12499 | frag as extended if it was small, and is about to become | |
12500 | extended with a value of maxtiny + 1. */ | |
12501 | if (val == ((maxtiny + 1) << op->shift) | |
12502 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
12503 | && sec == NULL) | |
12504 | { | |
12505 | fragp->fr_subtype = | |
12506 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
12507 | return 1; | |
12508 | } | |
12509 | } | |
12510 | else if (symsec != absolute_section && sec != NULL) | |
12511 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
12512 | ||
12513 | if ((val & ((1 << op->shift) - 1)) != 0 | |
12514 | || val < (mintiny << op->shift) | |
12515 | || val > (maxtiny << op->shift)) | |
12516 | return 1; | |
12517 | else | |
12518 | return 0; | |
12519 | } | |
12520 | ||
4a6a3df4 AO |
12521 | /* Compute the length of a branch sequence, and adjust the |
12522 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
12523 | worst-case length is computed, with UPDATE being used to indicate | |
12524 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
12525 | branch is to be computed. */ | |
12526 | static int | |
17a2f251 | 12527 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 12528 | { |
b34976b6 | 12529 | bfd_boolean toofar; |
4a6a3df4 AO |
12530 | int length; |
12531 | ||
12532 | if (fragp | |
12533 | && S_IS_DEFINED (fragp->fr_symbol) | |
12534 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
12535 | { | |
12536 | addressT addr; | |
12537 | offsetT val; | |
12538 | ||
12539 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
12540 | ||
12541 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
12542 | ||
12543 | val -= addr; | |
12544 | ||
12545 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
12546 | } | |
12547 | else if (fragp) | |
12548 | /* If the symbol is not defined or it's in a different segment, | |
12549 | assume the user knows what's going on and emit a short | |
12550 | branch. */ | |
b34976b6 | 12551 | toofar = FALSE; |
4a6a3df4 | 12552 | else |
b34976b6 | 12553 | toofar = TRUE; |
4a6a3df4 AO |
12554 | |
12555 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
12556 | fragp->fr_subtype | |
af6ae2ad | 12557 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype), |
4a6a3df4 AO |
12558 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
12559 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
12560 | toofar); | |
12561 | ||
12562 | length = 4; | |
12563 | if (toofar) | |
12564 | { | |
12565 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
12566 | length += 8; | |
12567 | ||
12568 | if (mips_pic != NO_PIC) | |
12569 | { | |
12570 | /* Additional space for PIC loading of target address. */ | |
12571 | length += 8; | |
12572 | if (mips_opts.isa == ISA_MIPS1) | |
12573 | /* Additional space for $at-stabilizing nop. */ | |
12574 | length += 4; | |
12575 | } | |
12576 | ||
12577 | /* If branch is conditional. */ | |
12578 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
12579 | length += 8; | |
12580 | } | |
b34976b6 | 12581 | |
4a6a3df4 AO |
12582 | return length; |
12583 | } | |
12584 | ||
252b5132 RH |
12585 | /* Estimate the size of a frag before relaxing. Unless this is the |
12586 | mips16, we are not really relaxing here, and the final size is | |
12587 | encoded in the subtype information. For the mips16, we have to | |
12588 | decide whether we are using an extended opcode or not. */ | |
12589 | ||
252b5132 | 12590 | int |
17a2f251 | 12591 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 12592 | { |
5919d012 | 12593 | int change; |
252b5132 | 12594 | |
4a6a3df4 AO |
12595 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
12596 | { | |
12597 | ||
b34976b6 AM |
12598 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
12599 | ||
4a6a3df4 AO |
12600 | return fragp->fr_var; |
12601 | } | |
12602 | ||
252b5132 | 12603 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
12604 | /* We don't want to modify the EXTENDED bit here; it might get us |
12605 | into infinite loops. We change it only in mips_relax_frag(). */ | |
12606 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 RH |
12607 | |
12608 | if (mips_pic == NO_PIC) | |
5919d012 | 12609 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 12610 | else if (mips_pic == SVR4_PIC) |
5919d012 | 12611 | change = pic_need_relax (fragp->fr_symbol, segtype); |
252b5132 RH |
12612 | else |
12613 | abort (); | |
12614 | ||
12615 | if (change) | |
12616 | { | |
4d7206a2 | 12617 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 12618 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 12619 | } |
4d7206a2 RS |
12620 | else |
12621 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
12622 | } |
12623 | ||
12624 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 12625 | should be converted into a reloc against a section. */ |
252b5132 RH |
12626 | |
12627 | int | |
17a2f251 | 12628 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 12629 | { |
de7e6852 RS |
12630 | /* Don't adjust MIPS16 jump relocations, so we don't have to worry |
12631 | about the format of the offset in the .o file. */ | |
252b5132 RH |
12632 | if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) |
12633 | return 0; | |
a161fe53 | 12634 | |
252b5132 RH |
12635 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
12636 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
12637 | return 0; | |
a161fe53 | 12638 | |
252b5132 RH |
12639 | if (fixp->fx_addsy == NULL) |
12640 | return 1; | |
a161fe53 | 12641 | |
de7e6852 RS |
12642 | /* If symbol SYM is in a mergeable section, relocations of the form |
12643 | SYM + 0 can usually be made section-relative. The mergeable data | |
12644 | is then identified by the section offset rather than by the symbol. | |
12645 | ||
12646 | However, if we're generating REL LO16 relocations, the offset is split | |
12647 | between the LO16 and parterning high part relocation. The linker will | |
12648 | need to recalculate the complete offset in order to correctly identify | |
12649 | the merge data. | |
12650 | ||
12651 | The linker has traditionally not looked for the parterning high part | |
12652 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be | |
12653 | placed anywhere. Rather than break backwards compatibility by changing | |
12654 | this, it seems better not to force the issue, and instead keep the | |
12655 | original symbol. This will work with either linker behavior. */ | |
12656 | if ((fixp->fx_r_type == BFD_RELOC_LO16 || reloc_needs_lo_p (fixp->fx_r_type)) | |
12657 | && HAVE_IN_PLACE_ADDENDS | |
12658 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
12659 | return 0; | |
12660 | ||
252b5132 | 12661 | #ifdef OBJ_ELF |
de7e6852 RS |
12662 | /* Don't adjust relocations against mips16 symbols, so that the linker |
12663 | can find them if it needs to set up a stub. */ | |
252b5132 RH |
12664 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
12665 | && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 | |
12666 | && fixp->fx_subsy == NULL) | |
12667 | return 0; | |
12668 | #endif | |
a161fe53 | 12669 | |
252b5132 RH |
12670 | return 1; |
12671 | } | |
12672 | ||
12673 | /* Translate internal representation of relocation info to BFD target | |
12674 | format. */ | |
12675 | ||
12676 | arelent ** | |
17a2f251 | 12677 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
12678 | { |
12679 | static arelent *retval[4]; | |
12680 | arelent *reloc; | |
12681 | bfd_reloc_code_real_type code; | |
12682 | ||
4b0cff4e TS |
12683 | memset (retval, 0, sizeof(retval)); |
12684 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
12685 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
12686 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
12687 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
12688 | ||
3e722fb5 CD |
12689 | assert (! fixp->fx_pcrel); |
12690 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 12691 | |
438c16b8 TS |
12692 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
12693 | entry to be used in the relocation's section offset. */ | |
12694 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
12695 | { |
12696 | reloc->address = reloc->addend; | |
12697 | reloc->addend = 0; | |
12698 | } | |
12699 | ||
252b5132 | 12700 | code = fixp->fx_r_type; |
252b5132 | 12701 | |
3e722fb5 CD |
12702 | /* To support a PC relative reloc, we used a Cygnus extension. |
12703 | We check for that here to make sure that we don't let such a | |
12704 | reloc escape normally. (FIXME: This was formerly used by | |
12705 | embedded-PIC support, but is now used by branch handling in | |
12706 | general. That probably should be fixed.) */ | |
0b25d3e6 AO |
12707 | if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
12708 | || OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
3e722fb5 | 12709 | && code == BFD_RELOC_16_PCREL_S2) |
0b25d3e6 AO |
12710 | reloc->howto = NULL; |
12711 | else | |
12712 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
12713 | ||
252b5132 RH |
12714 | if (reloc->howto == NULL) |
12715 | { | |
12716 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
12717 | _("Can not represent %s relocation in this object file format"), | |
12718 | bfd_get_reloc_code_name (code)); | |
12719 | retval[0] = NULL; | |
12720 | } | |
12721 | ||
12722 | return retval; | |
12723 | } | |
12724 | ||
12725 | /* Relax a machine dependent frag. This returns the amount by which | |
12726 | the current size of the frag should change. */ | |
12727 | ||
12728 | int | |
17a2f251 | 12729 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 12730 | { |
4a6a3df4 AO |
12731 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
12732 | { | |
12733 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
12734 | |
12735 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
12736 | |
12737 | return fragp->fr_var - old_var; | |
12738 | } | |
12739 | ||
252b5132 RH |
12740 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
12741 | return 0; | |
12742 | ||
c4e7957c | 12743 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
12744 | { |
12745 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
12746 | return 0; | |
12747 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
12748 | return 2; | |
12749 | } | |
12750 | else | |
12751 | { | |
12752 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
12753 | return 0; | |
12754 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
12755 | return -2; | |
12756 | } | |
12757 | ||
12758 | return 0; | |
12759 | } | |
12760 | ||
12761 | /* Convert a machine dependent frag. */ | |
12762 | ||
12763 | void | |
17a2f251 | 12764 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 12765 | { |
4a6a3df4 AO |
12766 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
12767 | { | |
12768 | bfd_byte *buf; | |
12769 | unsigned long insn; | |
12770 | expressionS exp; | |
12771 | fixS *fixp; | |
b34976b6 | 12772 | |
4a6a3df4 AO |
12773 | buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; |
12774 | ||
12775 | if (target_big_endian) | |
12776 | insn = bfd_getb32 (buf); | |
12777 | else | |
12778 | insn = bfd_getl32 (buf); | |
b34976b6 | 12779 | |
4a6a3df4 AO |
12780 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
12781 | { | |
12782 | /* We generate a fixup instead of applying it right now | |
12783 | because, if there are linker relaxations, we're going to | |
12784 | need the relocations. */ | |
12785 | exp.X_op = O_symbol; | |
12786 | exp.X_add_symbol = fragp->fr_symbol; | |
12787 | exp.X_add_number = fragp->fr_offset; | |
12788 | ||
12789 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
0b25d3e6 AO |
12790 | 4, &exp, 1, |
12791 | BFD_RELOC_16_PCREL_S2); | |
4a6a3df4 AO |
12792 | fixp->fx_file = fragp->fr_file; |
12793 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 12794 | |
2132e3a3 | 12795 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
12796 | buf += 4; |
12797 | } | |
12798 | else | |
12799 | { | |
12800 | int i; | |
12801 | ||
12802 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
12803 | _("relaxed out-of-range branch into a jump")); | |
12804 | ||
12805 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
12806 | goto uncond; | |
12807 | ||
12808 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
12809 | { | |
12810 | /* Reverse the branch. */ | |
12811 | switch ((insn >> 28) & 0xf) | |
12812 | { | |
12813 | case 4: | |
12814 | /* bc[0-3][tf]l? and bc1any[24][ft] instructions can | |
12815 | have the condition reversed by tweaking a single | |
12816 | bit, and their opcodes all have 0x4???????. */ | |
12817 | assert ((insn & 0xf1000000) == 0x41000000); | |
12818 | insn ^= 0x00010000; | |
12819 | break; | |
12820 | ||
12821 | case 0: | |
12822 | /* bltz 0x04000000 bgez 0x04010000 | |
12823 | bltzal 0x04100000 bgezal 0x04110000 */ | |
12824 | assert ((insn & 0xfc0e0000) == 0x04000000); | |
12825 | insn ^= 0x00010000; | |
12826 | break; | |
b34976b6 | 12827 | |
4a6a3df4 AO |
12828 | case 1: |
12829 | /* beq 0x10000000 bne 0x14000000 | |
12830 | blez 0x18000000 bgtz 0x1c000000 */ | |
12831 | insn ^= 0x04000000; | |
12832 | break; | |
12833 | ||
12834 | default: | |
12835 | abort (); | |
12836 | } | |
12837 | } | |
12838 | ||
12839 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
12840 | { | |
12841 | /* Clear the and-link bit. */ | |
12842 | assert ((insn & 0xfc1c0000) == 0x04100000); | |
12843 | ||
12844 | /* bltzal 0x04100000 bgezal 0x04110000 | |
12845 | bltzall 0x04120000 bgezall 0x04130000 */ | |
12846 | insn &= ~0x00100000; | |
12847 | } | |
12848 | ||
12849 | /* Branch over the branch (if the branch was likely) or the | |
12850 | full jump (not likely case). Compute the offset from the | |
12851 | current instruction to branch to. */ | |
12852 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
12853 | i = 16; | |
12854 | else | |
12855 | { | |
12856 | /* How many bytes in instructions we've already emitted? */ | |
12857 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
12858 | /* How many bytes in instructions from here to the end? */ | |
12859 | i = fragp->fr_var - i; | |
12860 | } | |
12861 | /* Convert to instruction count. */ | |
12862 | i >>= 2; | |
12863 | /* Branch counts from the next instruction. */ | |
b34976b6 | 12864 | i--; |
4a6a3df4 AO |
12865 | insn |= i; |
12866 | /* Branch over the jump. */ | |
2132e3a3 | 12867 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
12868 | buf += 4; |
12869 | ||
12870 | /* Nop */ | |
2132e3a3 | 12871 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
12872 | buf += 4; |
12873 | ||
12874 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
12875 | { | |
12876 | /* beql $0, $0, 2f */ | |
12877 | insn = 0x50000000; | |
12878 | /* Compute the PC offset from the current instruction to | |
12879 | the end of the variable frag. */ | |
12880 | /* How many bytes in instructions we've already emitted? */ | |
12881 | i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; | |
12882 | /* How many bytes in instructions from here to the end? */ | |
12883 | i = fragp->fr_var - i; | |
12884 | /* Convert to instruction count. */ | |
12885 | i >>= 2; | |
12886 | /* Don't decrement i, because we want to branch over the | |
12887 | delay slot. */ | |
12888 | ||
12889 | insn |= i; | |
2132e3a3 | 12890 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
12891 | buf += 4; |
12892 | ||
2132e3a3 | 12893 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
12894 | buf += 4; |
12895 | } | |
12896 | ||
12897 | uncond: | |
12898 | if (mips_pic == NO_PIC) | |
12899 | { | |
12900 | /* j or jal. */ | |
12901 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
12902 | ? 0x0c000000 : 0x08000000); | |
12903 | exp.X_op = O_symbol; | |
12904 | exp.X_add_symbol = fragp->fr_symbol; | |
12905 | exp.X_add_number = fragp->fr_offset; | |
12906 | ||
12907 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
12908 | 4, &exp, 0, BFD_RELOC_MIPS_JMP); | |
12909 | fixp->fx_file = fragp->fr_file; | |
12910 | fixp->fx_line = fragp->fr_line; | |
12911 | ||
2132e3a3 | 12912 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
12913 | buf += 4; |
12914 | } | |
12915 | else | |
12916 | { | |
12917 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ | |
12918 | insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000; | |
12919 | exp.X_op = O_symbol; | |
12920 | exp.X_add_symbol = fragp->fr_symbol; | |
12921 | exp.X_add_number = fragp->fr_offset; | |
12922 | ||
12923 | if (fragp->fr_offset) | |
12924 | { | |
12925 | exp.X_add_symbol = make_expr_symbol (&exp); | |
12926 | exp.X_add_number = 0; | |
12927 | } | |
12928 | ||
12929 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
12930 | 4, &exp, 0, BFD_RELOC_MIPS_GOT16); | |
12931 | fixp->fx_file = fragp->fr_file; | |
12932 | fixp->fx_line = fragp->fr_line; | |
12933 | ||
2132e3a3 | 12934 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 | 12935 | buf += 4; |
b34976b6 | 12936 | |
4a6a3df4 AO |
12937 | if (mips_opts.isa == ISA_MIPS1) |
12938 | { | |
12939 | /* nop */ | |
2132e3a3 | 12940 | md_number_to_chars ((char *) buf, 0, 4); |
4a6a3df4 AO |
12941 | buf += 4; |
12942 | } | |
12943 | ||
12944 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
12945 | insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000; | |
12946 | ||
12947 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
12948 | 4, &exp, 0, BFD_RELOC_LO16); | |
12949 | fixp->fx_file = fragp->fr_file; | |
12950 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 12951 | |
2132e3a3 | 12952 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
12953 | buf += 4; |
12954 | ||
12955 | /* j(al)r $at. */ | |
12956 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
12957 | insn = 0x0020f809; | |
12958 | else | |
12959 | insn = 0x00200008; | |
12960 | ||
2132e3a3 | 12961 | md_number_to_chars ((char *) buf, insn, 4); |
4a6a3df4 AO |
12962 | buf += 4; |
12963 | } | |
12964 | } | |
12965 | ||
12966 | assert (buf == (bfd_byte *)fragp->fr_literal | |
12967 | + fragp->fr_fix + fragp->fr_var); | |
12968 | ||
12969 | fragp->fr_fix += fragp->fr_var; | |
12970 | ||
12971 | return; | |
12972 | } | |
12973 | ||
252b5132 RH |
12974 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
12975 | { | |
12976 | int type; | |
12977 | register const struct mips16_immed_operand *op; | |
b34976b6 | 12978 | bfd_boolean small, ext; |
252b5132 RH |
12979 | offsetT val; |
12980 | bfd_byte *buf; | |
12981 | unsigned long insn; | |
b34976b6 | 12982 | bfd_boolean use_extend; |
252b5132 RH |
12983 | unsigned short extend; |
12984 | ||
12985 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
12986 | op = mips16_immed_operands; | |
12987 | while (op->type != type) | |
12988 | ++op; | |
12989 | ||
12990 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
12991 | { | |
b34976b6 AM |
12992 | small = FALSE; |
12993 | ext = TRUE; | |
252b5132 RH |
12994 | } |
12995 | else | |
12996 | { | |
b34976b6 AM |
12997 | small = TRUE; |
12998 | ext = FALSE; | |
252b5132 RH |
12999 | } |
13000 | ||
6386f3a7 | 13001 | resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
13002 | val = S_GET_VALUE (fragp->fr_symbol); |
13003 | if (op->pcrel) | |
13004 | { | |
13005 | addressT addr; | |
13006 | ||
13007 | addr = fragp->fr_address + fragp->fr_fix; | |
13008 | ||
13009 | /* The rules for the base address of a PC relative reloc are | |
13010 | complicated; see mips16_extended_frag. */ | |
13011 | if (type == 'p' || type == 'q') | |
13012 | { | |
13013 | addr += 2; | |
13014 | if (ext) | |
13015 | addr += 2; | |
13016 | /* Ignore the low bit in the target, since it will be | |
13017 | set for a text label. */ | |
13018 | if ((val & 1) != 0) | |
13019 | --val; | |
13020 | } | |
13021 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
13022 | addr -= 4; | |
13023 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
13024 | addr -= 2; | |
13025 | ||
13026 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
13027 | val -= addr; | |
13028 | ||
13029 | /* Make sure the section winds up with the alignment we have | |
13030 | assumed. */ | |
13031 | if (op->shift > 0) | |
13032 | record_alignment (asec, op->shift); | |
13033 | } | |
13034 | ||
13035 | if (ext | |
13036 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
13037 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
13038 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
13039 | _("extended instruction in delay slot")); | |
13040 | ||
13041 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
13042 | ||
13043 | if (target_big_endian) | |
13044 | insn = bfd_getb16 (buf); | |
13045 | else | |
13046 | insn = bfd_getl16 (buf); | |
13047 | ||
13048 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
13049 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
13050 | small, ext, &insn, &use_extend, &extend); | |
13051 | ||
13052 | if (use_extend) | |
13053 | { | |
2132e3a3 | 13054 | md_number_to_chars ((char *) buf, 0xf000 | extend, 2); |
252b5132 RH |
13055 | fragp->fr_fix += 2; |
13056 | buf += 2; | |
13057 | } | |
13058 | ||
2132e3a3 | 13059 | md_number_to_chars ((char *) buf, insn, 2); |
252b5132 RH |
13060 | fragp->fr_fix += 2; |
13061 | buf += 2; | |
13062 | } | |
13063 | else | |
13064 | { | |
4d7206a2 RS |
13065 | int first, second; |
13066 | fixS *fixp; | |
252b5132 | 13067 | |
4d7206a2 RS |
13068 | first = RELAX_FIRST (fragp->fr_subtype); |
13069 | second = RELAX_SECOND (fragp->fr_subtype); | |
13070 | fixp = (fixS *) fragp->fr_opcode; | |
252b5132 | 13071 | |
584892a6 RS |
13072 | /* Possibly emit a warning if we've chosen the longer option. */ |
13073 | if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0) | |
13074 | == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0)) | |
13075 | { | |
13076 | const char *msg = macro_warning (fragp->fr_subtype); | |
13077 | if (msg != 0) | |
13078 | as_warn_where (fragp->fr_file, fragp->fr_line, msg); | |
13079 | } | |
13080 | ||
4d7206a2 RS |
13081 | /* Go through all the fixups for the first sequence. Disable them |
13082 | (by marking them as done) if we're going to use the second | |
13083 | sequence instead. */ | |
13084 | while (fixp | |
13085 | && fixp->fx_frag == fragp | |
13086 | && fixp->fx_where < fragp->fr_fix - second) | |
13087 | { | |
13088 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13089 | fixp->fx_done = 1; | |
13090 | fixp = fixp->fx_next; | |
13091 | } | |
252b5132 | 13092 | |
4d7206a2 RS |
13093 | /* Go through the fixups for the second sequence. Disable them if |
13094 | we're going to use the first sequence, otherwise adjust their | |
13095 | addresses to account for the relaxation. */ | |
13096 | while (fixp && fixp->fx_frag == fragp) | |
13097 | { | |
13098 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13099 | fixp->fx_where -= first; | |
13100 | else | |
13101 | fixp->fx_done = 1; | |
13102 | fixp = fixp->fx_next; | |
13103 | } | |
13104 | ||
13105 | /* Now modify the frag contents. */ | |
13106 | if (fragp->fr_subtype & RELAX_USE_SECOND) | |
13107 | { | |
13108 | char *start; | |
13109 | ||
13110 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
13111 | memmove (start, start + first, second); | |
13112 | fragp->fr_fix -= first; | |
13113 | } | |
13114 | else | |
13115 | fragp->fr_fix -= second; | |
252b5132 RH |
13116 | } |
13117 | } | |
13118 | ||
13119 | #ifdef OBJ_ELF | |
13120 | ||
13121 | /* This function is called after the relocs have been generated. | |
13122 | We've been storing mips16 text labels as odd. Here we convert them | |
13123 | back to even for the convenience of the debugger. */ | |
13124 | ||
13125 | void | |
17a2f251 | 13126 | mips_frob_file_after_relocs (void) |
252b5132 RH |
13127 | { |
13128 | asymbol **syms; | |
13129 | unsigned int count, i; | |
13130 | ||
13131 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
13132 | return; | |
13133 | ||
13134 | syms = bfd_get_outsymbols (stdoutput); | |
13135 | count = bfd_get_symcount (stdoutput); | |
13136 | for (i = 0; i < count; i++, syms++) | |
13137 | { | |
13138 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
13139 | && ((*syms)->value & 1) != 0) | |
13140 | { | |
13141 | (*syms)->value &= ~1; | |
13142 | /* If the symbol has an odd size, it was probably computed | |
13143 | incorrectly, so adjust that as well. */ | |
13144 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
13145 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
13146 | } | |
13147 | } | |
13148 | } | |
13149 | ||
13150 | #endif | |
13151 | ||
13152 | /* This function is called whenever a label is defined. It is used | |
13153 | when handling branch delays; if a branch has a label, we assume we | |
13154 | can not move it. */ | |
13155 | ||
13156 | void | |
17a2f251 | 13157 | mips_define_label (symbolS *sym) |
252b5132 RH |
13158 | { |
13159 | struct insn_label_list *l; | |
13160 | ||
13161 | if (free_insn_labels == NULL) | |
13162 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
13163 | else | |
13164 | { | |
13165 | l = free_insn_labels; | |
13166 | free_insn_labels = l->next; | |
13167 | } | |
13168 | ||
13169 | l->label = sym; | |
13170 | l->next = insn_labels; | |
13171 | insn_labels = l; | |
13172 | } | |
13173 | \f | |
13174 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
13175 | ||
13176 | /* Some special processing for a MIPS ELF file. */ | |
13177 | ||
13178 | void | |
17a2f251 | 13179 | mips_elf_final_processing (void) |
252b5132 RH |
13180 | { |
13181 | /* Write out the register information. */ | |
316f5878 | 13182 | if (mips_abi != N64_ABI) |
252b5132 RH |
13183 | { |
13184 | Elf32_RegInfo s; | |
13185 | ||
13186 | s.ri_gprmask = mips_gprmask; | |
13187 | s.ri_cprmask[0] = mips_cprmask[0]; | |
13188 | s.ri_cprmask[1] = mips_cprmask[1]; | |
13189 | s.ri_cprmask[2] = mips_cprmask[2]; | |
13190 | s.ri_cprmask[3] = mips_cprmask[3]; | |
13191 | /* The gp_value field is set by the MIPS ELF backend. */ | |
13192 | ||
13193 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
13194 | ((Elf32_External_RegInfo *) | |
13195 | mips_regmask_frag)); | |
13196 | } | |
13197 | else | |
13198 | { | |
13199 | Elf64_Internal_RegInfo s; | |
13200 | ||
13201 | s.ri_gprmask = mips_gprmask; | |
13202 | s.ri_pad = 0; | |
13203 | s.ri_cprmask[0] = mips_cprmask[0]; | |
13204 | s.ri_cprmask[1] = mips_cprmask[1]; | |
13205 | s.ri_cprmask[2] = mips_cprmask[2]; | |
13206 | s.ri_cprmask[3] = mips_cprmask[3]; | |
13207 | /* The gp_value field is set by the MIPS ELF backend. */ | |
13208 | ||
13209 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
13210 | ((Elf64_External_RegInfo *) | |
13211 | mips_regmask_frag)); | |
13212 | } | |
13213 | ||
13214 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
13215 | sort of BFD interface for this. */ | |
13216 | if (mips_any_noreorder) | |
13217 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
13218 | if (mips_pic != NO_PIC) | |
143d77c5 | 13219 | { |
252b5132 | 13220 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
13221 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
13222 | } | |
13223 | if (mips_abicalls) | |
13224 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 13225 | |
98d3f06f | 13226 | /* Set MIPS ELF flags for ASEs. */ |
a4672219 TS |
13227 | if (file_ase_mips16) |
13228 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
1f25f5d3 CD |
13229 | #if 0 /* XXX FIXME */ |
13230 | if (file_ase_mips3d) | |
13231 | elf_elfheader (stdoutput)->e_flags |= ???; | |
13232 | #endif | |
deec1734 CD |
13233 | if (file_ase_mdmx) |
13234 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; | |
1f25f5d3 | 13235 | |
bdaaa2e1 | 13236 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 13237 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 13238 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 13239 | else if (mips_abi == O64_ABI) |
252b5132 | 13240 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 13241 | else if (mips_abi == EABI_ABI) |
252b5132 | 13242 | { |
316f5878 | 13243 | if (!file_mips_gp32) |
252b5132 RH |
13244 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
13245 | else | |
13246 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
13247 | } | |
316f5878 | 13248 | else if (mips_abi == N32_ABI) |
be00bddd TS |
13249 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
13250 | ||
c9914766 | 13251 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
13252 | |
13253 | if (mips_32bitmode) | |
13254 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
13255 | } | |
13256 | ||
13257 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
13258 | \f | |
beae10d5 | 13259 | typedef struct proc { |
9b2f1d35 EC |
13260 | symbolS *func_sym; |
13261 | symbolS *func_end_sym; | |
beae10d5 KH |
13262 | unsigned long reg_mask; |
13263 | unsigned long reg_offset; | |
13264 | unsigned long fpreg_mask; | |
13265 | unsigned long fpreg_offset; | |
13266 | unsigned long frame_offset; | |
13267 | unsigned long frame_reg; | |
13268 | unsigned long pc_reg; | |
13269 | } procS; | |
252b5132 RH |
13270 | |
13271 | static procS cur_proc; | |
13272 | static procS *cur_proc_ptr; | |
13273 | static int numprocs; | |
13274 | ||
0a9ef439 | 13275 | /* Fill in an rs_align_code fragment. */ |
a19d8eb0 | 13276 | |
0a9ef439 | 13277 | void |
17a2f251 | 13278 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 13279 | { |
0a9ef439 RH |
13280 | if (fragp->fr_type != rs_align_code) |
13281 | return; | |
13282 | ||
13283 | if (mips_opts.mips16) | |
a19d8eb0 CP |
13284 | { |
13285 | static const unsigned char be_nop[] = { 0x65, 0x00 }; | |
13286 | static const unsigned char le_nop[] = { 0x00, 0x65 }; | |
13287 | ||
0a9ef439 RH |
13288 | int bytes; |
13289 | char *p; | |
a19d8eb0 | 13290 | |
0a9ef439 RH |
13291 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
13292 | p = fragp->fr_literal + fragp->fr_fix; | |
13293 | ||
13294 | if (bytes & 1) | |
13295 | { | |
13296 | *p++ = 0; | |
f9419b05 | 13297 | fragp->fr_fix++; |
0a9ef439 RH |
13298 | } |
13299 | ||
13300 | memcpy (p, (target_big_endian ? be_nop : le_nop), 2); | |
13301 | fragp->fr_var = 2; | |
a19d8eb0 CP |
13302 | } |
13303 | ||
0a9ef439 | 13304 | /* For mips32, a nop is a zero, which we trivially get by doing nothing. */ |
a19d8eb0 CP |
13305 | } |
13306 | ||
252b5132 | 13307 | static void |
17a2f251 | 13308 | md_obj_begin (void) |
252b5132 RH |
13309 | { |
13310 | } | |
13311 | ||
13312 | static void | |
17a2f251 | 13313 | md_obj_end (void) |
252b5132 RH |
13314 | { |
13315 | /* check for premature end, nesting errors, etc */ | |
13316 | if (cur_proc_ptr) | |
9a41af64 | 13317 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
13318 | } |
13319 | ||
13320 | static long | |
17a2f251 | 13321 | get_number (void) |
252b5132 RH |
13322 | { |
13323 | int negative = 0; | |
13324 | long val = 0; | |
13325 | ||
13326 | if (*input_line_pointer == '-') | |
13327 | { | |
13328 | ++input_line_pointer; | |
13329 | negative = 1; | |
13330 | } | |
3882b010 | 13331 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 13332 | as_bad (_("expected simple number")); |
252b5132 RH |
13333 | if (input_line_pointer[0] == '0') |
13334 | { | |
13335 | if (input_line_pointer[1] == 'x') | |
13336 | { | |
13337 | input_line_pointer += 2; | |
3882b010 | 13338 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
13339 | { |
13340 | val <<= 4; | |
13341 | val |= hex_value (*input_line_pointer++); | |
13342 | } | |
13343 | return negative ? -val : val; | |
13344 | } | |
13345 | else | |
13346 | { | |
13347 | ++input_line_pointer; | |
3882b010 | 13348 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13349 | { |
13350 | val <<= 3; | |
13351 | val |= *input_line_pointer++ - '0'; | |
13352 | } | |
13353 | return negative ? -val : val; | |
13354 | } | |
13355 | } | |
3882b010 | 13356 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13357 | { |
13358 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
13359 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 13360 | as_warn (_("invalid number")); |
252b5132 RH |
13361 | return -1; |
13362 | } | |
3882b010 | 13363 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
13364 | { |
13365 | val *= 10; | |
13366 | val += *input_line_pointer++ - '0'; | |
13367 | } | |
13368 | return negative ? -val : val; | |
13369 | } | |
13370 | ||
13371 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
13372 | is an initial number which is the ECOFF file index. In the non-ECOFF |
13373 | case .file implies DWARF-2. */ | |
13374 | ||
13375 | static void | |
17a2f251 | 13376 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 13377 | { |
ecb4347a DJ |
13378 | static int first_file_directive = 0; |
13379 | ||
c5dd6aab DJ |
13380 | if (ECOFF_DEBUGGING) |
13381 | { | |
13382 | get_number (); | |
13383 | s_app_file (0); | |
13384 | } | |
13385 | else | |
ecb4347a DJ |
13386 | { |
13387 | char *filename; | |
13388 | ||
13389 | filename = dwarf2_directive_file (0); | |
13390 | ||
13391 | /* Versions of GCC up to 3.1 start files with a ".file" | |
13392 | directive even for stabs output. Make sure that this | |
13393 | ".file" is handled. Note that you need a version of GCC | |
13394 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
13395 | if (filename != NULL && ! first_file_directive) | |
13396 | { | |
13397 | (void) new_logical_line (filename, -1); | |
c04f5787 | 13398 | s_app_file_string (filename, 0); |
ecb4347a DJ |
13399 | } |
13400 | first_file_directive = 1; | |
13401 | } | |
c5dd6aab DJ |
13402 | } |
13403 | ||
13404 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
13405 | |
13406 | static void | |
17a2f251 | 13407 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 13408 | { |
c5dd6aab DJ |
13409 | if (!ECOFF_DEBUGGING) |
13410 | dwarf2_directive_loc (0); | |
252b5132 RH |
13411 | } |
13412 | ||
252b5132 RH |
13413 | /* The .end directive. */ |
13414 | ||
13415 | static void | |
17a2f251 | 13416 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
13417 | { |
13418 | symbolS *p; | |
252b5132 | 13419 | |
7a621144 DJ |
13420 | /* Following functions need their own .frame and .cprestore directives. */ |
13421 | mips_frame_reg_valid = 0; | |
13422 | mips_cprestore_valid = 0; | |
13423 | ||
252b5132 RH |
13424 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
13425 | { | |
13426 | p = get_symbol (); | |
13427 | demand_empty_rest_of_line (); | |
13428 | } | |
13429 | else | |
13430 | p = NULL; | |
13431 | ||
14949570 | 13432 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
13433 | as_warn (_(".end not in text section")); |
13434 | ||
13435 | if (!cur_proc_ptr) | |
13436 | { | |
13437 | as_warn (_(".end directive without a preceding .ent directive.")); | |
13438 | demand_empty_rest_of_line (); | |
13439 | return; | |
13440 | } | |
13441 | ||
13442 | if (p != NULL) | |
13443 | { | |
13444 | assert (S_GET_NAME (p)); | |
9b2f1d35 | 13445 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
252b5132 | 13446 | as_warn (_(".end symbol does not match .ent symbol.")); |
ecb4347a DJ |
13447 | |
13448 | if (debug_type == DEBUG_STABS) | |
13449 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
13450 | S_GET_NAME (p)); | |
252b5132 RH |
13451 | } |
13452 | else | |
13453 | as_warn (_(".end directive missing or unknown symbol")); | |
13454 | ||
2132e3a3 | 13455 | #ifdef OBJ_ELF |
9b2f1d35 EC |
13456 | /* Create an expression to calculate the size of the function. */ |
13457 | if (p && cur_proc_ptr) | |
13458 | { | |
13459 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
13460 | expressionS *exp = xmalloc (sizeof (expressionS)); | |
13461 | ||
13462 | obj->size = exp; | |
13463 | exp->X_op = O_subtract; | |
13464 | exp->X_add_symbol = symbol_temp_new_now (); | |
13465 | exp->X_op_symbol = p; | |
13466 | exp->X_add_number = 0; | |
13467 | ||
13468 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
13469 | } | |
13470 | ||
ecb4347a | 13471 | /* Generate a .pdr section. */ |
dcd410fe RO |
13472 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING |
13473 | && mips_flag_pdr) | |
ecb4347a DJ |
13474 | { |
13475 | segT saved_seg = now_seg; | |
13476 | subsegT saved_subseg = now_subseg; | |
13477 | valueT dot; | |
13478 | expressionS exp; | |
13479 | char *fragp; | |
252b5132 | 13480 | |
ecb4347a | 13481 | dot = frag_now_fix (); |
252b5132 RH |
13482 | |
13483 | #ifdef md_flush_pending_output | |
ecb4347a | 13484 | md_flush_pending_output (); |
252b5132 RH |
13485 | #endif |
13486 | ||
ecb4347a DJ |
13487 | assert (pdr_seg); |
13488 | subseg_set (pdr_seg, 0); | |
252b5132 | 13489 | |
ecb4347a DJ |
13490 | /* Write the symbol. */ |
13491 | exp.X_op = O_symbol; | |
13492 | exp.X_add_symbol = p; | |
13493 | exp.X_add_number = 0; | |
13494 | emit_expr (&exp, 4); | |
252b5132 | 13495 | |
ecb4347a | 13496 | fragp = frag_more (7 * 4); |
252b5132 | 13497 | |
17a2f251 TS |
13498 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
13499 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
13500 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
13501 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
13502 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
13503 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
13504 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 13505 | |
ecb4347a DJ |
13506 | subseg_set (saved_seg, saved_subseg); |
13507 | } | |
13508 | #endif /* OBJ_ELF */ | |
252b5132 RH |
13509 | |
13510 | cur_proc_ptr = NULL; | |
13511 | } | |
13512 | ||
13513 | /* The .aent and .ent directives. */ | |
13514 | ||
13515 | static void | |
17a2f251 | 13516 | s_mips_ent (int aent) |
252b5132 | 13517 | { |
252b5132 | 13518 | symbolS *symbolP; |
252b5132 RH |
13519 | |
13520 | symbolP = get_symbol (); | |
13521 | if (*input_line_pointer == ',') | |
f9419b05 | 13522 | ++input_line_pointer; |
252b5132 | 13523 | SKIP_WHITESPACE (); |
3882b010 | 13524 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 13525 | || *input_line_pointer == '-') |
874e8986 | 13526 | get_number (); |
252b5132 | 13527 | |
14949570 | 13528 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
13529 | as_warn (_(".ent or .aent not in text section.")); |
13530 | ||
13531 | if (!aent && cur_proc_ptr) | |
9a41af64 | 13532 | as_warn (_("missing .end")); |
252b5132 RH |
13533 | |
13534 | if (!aent) | |
13535 | { | |
7a621144 DJ |
13536 | /* This function needs its own .frame and .cprestore directives. */ |
13537 | mips_frame_reg_valid = 0; | |
13538 | mips_cprestore_valid = 0; | |
13539 | ||
252b5132 RH |
13540 | cur_proc_ptr = &cur_proc; |
13541 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
13542 | ||
9b2f1d35 | 13543 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 13544 | |
49309057 | 13545 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
252b5132 | 13546 | |
f9419b05 | 13547 | ++numprocs; |
ecb4347a DJ |
13548 | |
13549 | if (debug_type == DEBUG_STABS) | |
13550 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
13551 | S_GET_NAME (symbolP)); | |
252b5132 RH |
13552 | } |
13553 | ||
13554 | demand_empty_rest_of_line (); | |
13555 | } | |
13556 | ||
13557 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 13558 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 13559 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 13560 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
13561 | symbol table (in the mdebug section). */ |
13562 | ||
13563 | static void | |
17a2f251 | 13564 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13565 | { |
ecb4347a DJ |
13566 | #ifdef OBJ_ELF |
13567 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
13568 | { | |
13569 | long val; | |
252b5132 | 13570 | |
ecb4347a DJ |
13571 | if (cur_proc_ptr == (procS *) NULL) |
13572 | { | |
13573 | as_warn (_(".frame outside of .ent")); | |
13574 | demand_empty_rest_of_line (); | |
13575 | return; | |
13576 | } | |
252b5132 | 13577 | |
ecb4347a DJ |
13578 | cur_proc_ptr->frame_reg = tc_get_register (1); |
13579 | ||
13580 | SKIP_WHITESPACE (); | |
13581 | if (*input_line_pointer++ != ',' | |
13582 | || get_absolute_expression_and_terminator (&val) != ',') | |
13583 | { | |
13584 | as_warn (_("Bad .frame directive")); | |
13585 | --input_line_pointer; | |
13586 | demand_empty_rest_of_line (); | |
13587 | return; | |
13588 | } | |
252b5132 | 13589 | |
ecb4347a DJ |
13590 | cur_proc_ptr->frame_offset = val; |
13591 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 13592 | |
252b5132 | 13593 | demand_empty_rest_of_line (); |
252b5132 | 13594 | } |
ecb4347a DJ |
13595 | else |
13596 | #endif /* OBJ_ELF */ | |
13597 | s_ignore (ignore); | |
252b5132 RH |
13598 | } |
13599 | ||
bdaaa2e1 KH |
13600 | /* The .fmask and .mask directives. If the mdebug section is present |
13601 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 13602 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 13603 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
13604 | make reference to the ecoff symbol table (in the mdebug section). */ |
13605 | ||
13606 | static void | |
17a2f251 | 13607 | s_mips_mask (int reg_type) |
252b5132 | 13608 | { |
ecb4347a DJ |
13609 | #ifdef OBJ_ELF |
13610 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) | |
252b5132 | 13611 | { |
ecb4347a | 13612 | long mask, off; |
252b5132 | 13613 | |
ecb4347a DJ |
13614 | if (cur_proc_ptr == (procS *) NULL) |
13615 | { | |
13616 | as_warn (_(".mask/.fmask outside of .ent")); | |
13617 | demand_empty_rest_of_line (); | |
13618 | return; | |
13619 | } | |
252b5132 | 13620 | |
ecb4347a DJ |
13621 | if (get_absolute_expression_and_terminator (&mask) != ',') |
13622 | { | |
13623 | as_warn (_("Bad .mask/.fmask directive")); | |
13624 | --input_line_pointer; | |
13625 | demand_empty_rest_of_line (); | |
13626 | return; | |
13627 | } | |
252b5132 | 13628 | |
ecb4347a DJ |
13629 | off = get_absolute_expression (); |
13630 | ||
13631 | if (reg_type == 'F') | |
13632 | { | |
13633 | cur_proc_ptr->fpreg_mask = mask; | |
13634 | cur_proc_ptr->fpreg_offset = off; | |
13635 | } | |
13636 | else | |
13637 | { | |
13638 | cur_proc_ptr->reg_mask = mask; | |
13639 | cur_proc_ptr->reg_offset = off; | |
13640 | } | |
13641 | ||
13642 | demand_empty_rest_of_line (); | |
252b5132 RH |
13643 | } |
13644 | else | |
ecb4347a DJ |
13645 | #endif /* OBJ_ELF */ |
13646 | s_ignore (reg_type); | |
252b5132 RH |
13647 | } |
13648 | ||
316f5878 RS |
13649 | /* A table describing all the processors gas knows about. Names are |
13650 | matched in the order listed. | |
e7af610e | 13651 | |
316f5878 RS |
13652 | To ease comparison, please keep this table in the same order as |
13653 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
13654 | static const struct mips_cpu_info mips_cpu_info_table[] = |
13655 | { | |
316f5878 RS |
13656 | /* Entries for generic ISAs */ |
13657 | { "mips1", 1, ISA_MIPS1, CPU_R3000 }, | |
13658 | { "mips2", 1, ISA_MIPS2, CPU_R6000 }, | |
13659 | { "mips3", 1, ISA_MIPS3, CPU_R4000 }, | |
13660 | { "mips4", 1, ISA_MIPS4, CPU_R8000 }, | |
13661 | { "mips5", 1, ISA_MIPS5, CPU_MIPS5 }, | |
13662 | { "mips32", 1, ISA_MIPS32, CPU_MIPS32 }, | |
af7ee8bf | 13663 | { "mips32r2", 1, ISA_MIPS32R2, CPU_MIPS32R2 }, |
316f5878 | 13664 | { "mips64", 1, ISA_MIPS64, CPU_MIPS64 }, |
5f74bc13 | 13665 | { "mips64r2", 1, ISA_MIPS64R2, CPU_MIPS64R2 }, |
316f5878 RS |
13666 | |
13667 | /* MIPS I */ | |
13668 | { "r3000", 0, ISA_MIPS1, CPU_R3000 }, | |
13669 | { "r2000", 0, ISA_MIPS1, CPU_R3000 }, | |
13670 | { "r3900", 0, ISA_MIPS1, CPU_R3900 }, | |
13671 | ||
13672 | /* MIPS II */ | |
13673 | { "r6000", 0, ISA_MIPS2, CPU_R6000 }, | |
13674 | ||
13675 | /* MIPS III */ | |
13676 | { "r4000", 0, ISA_MIPS3, CPU_R4000 }, | |
13677 | { "r4010", 0, ISA_MIPS2, CPU_R4010 }, | |
13678 | { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, | |
13679 | { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, | |
60b63b72 RS |
13680 | { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, |
13681 | { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, | |
13682 | { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, | |
316f5878 RS |
13683 | { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, |
13684 | { "r4400", 0, ISA_MIPS3, CPU_R4400 }, | |
13685 | { "r4600", 0, ISA_MIPS3, CPU_R4600 }, | |
13686 | { "orion", 0, ISA_MIPS3, CPU_R4600 }, | |
13687 | { "r4650", 0, ISA_MIPS3, CPU_R4650 }, | |
13688 | ||
13689 | /* MIPS IV */ | |
13690 | { "r8000", 0, ISA_MIPS4, CPU_R8000 }, | |
13691 | { "r10000", 0, ISA_MIPS4, CPU_R10000 }, | |
13692 | { "r12000", 0, ISA_MIPS4, CPU_R12000 }, | |
13693 | { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, | |
60b63b72 RS |
13694 | { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, |
13695 | { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, | |
316f5878 RS |
13696 | { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, |
13697 | { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, | |
13698 | { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, | |
13699 | { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, | |
13700 | { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, | |
5a7ea749 | 13701 | { "rm7000", 0, ISA_MIPS4, CPU_RM7000 }, |
9a92f48d | 13702 | { "rm9000", 0, ISA_MIPS4, CPU_RM9000 }, |
316f5878 RS |
13703 | |
13704 | /* MIPS 32 */ | |
fef14a42 | 13705 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32 }, |
316f5878 RS |
13706 | { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, |
13707 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, | |
e7af610e | 13708 | |
316f5878 RS |
13709 | /* MIPS 64 */ |
13710 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, | |
13711 | { "20kc", 0, ISA_MIPS64, CPU_MIPS64 }, | |
e7af610e | 13712 | |
c7a23324 | 13713 | /* Broadcom SB-1 CPU core */ |
316f5878 | 13714 | { "sb1", 0, ISA_MIPS64, CPU_SB1 }, |
e7af610e | 13715 | |
316f5878 RS |
13716 | /* End marker */ |
13717 | { NULL, 0, 0, 0 } | |
13718 | }; | |
e7af610e | 13719 | |
84ea6cf2 | 13720 | |
316f5878 RS |
13721 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
13722 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 13723 | |
316f5878 | 13724 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 13725 | |
b34976b6 | 13726 | static bfd_boolean |
17a2f251 | 13727 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
13728 | { |
13729 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
13730 | given++, canonical++; | |
13731 | ||
13732 | return ((*given == 0 && *canonical == 0) | |
13733 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
13734 | } | |
13735 | ||
13736 | ||
13737 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
13738 | CPU name. We've traditionally allowed a lot of variation here. | |
13739 | ||
13740 | Note: this function is shared between GCC and GAS. */ | |
13741 | ||
b34976b6 | 13742 | static bfd_boolean |
17a2f251 | 13743 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
13744 | { |
13745 | /* First see if the name matches exactly, or with a final "000" | |
13746 | turned into "k". */ | |
13747 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 13748 | return TRUE; |
316f5878 RS |
13749 | |
13750 | /* If not, try comparing based on numerical designation alone. | |
13751 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
13752 | if (TOLOWER (*given) == 'r') | |
13753 | given++; | |
13754 | if (!ISDIGIT (*given)) | |
b34976b6 | 13755 | return FALSE; |
316f5878 RS |
13756 | |
13757 | /* Skip over some well-known prefixes in the canonical name, | |
13758 | hoping to find a number there too. */ | |
13759 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
13760 | canonical += 2; | |
13761 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
13762 | canonical += 2; | |
13763 | else if (TOLOWER (canonical[0]) == 'r') | |
13764 | canonical += 1; | |
13765 | ||
13766 | return mips_strict_matching_cpu_name_p (canonical, given); | |
13767 | } | |
13768 | ||
13769 | ||
13770 | /* Parse an option that takes the name of a processor as its argument. | |
13771 | OPTION is the name of the option and CPU_STRING is the argument. | |
13772 | Return the corresponding processor enumeration if the CPU_STRING is | |
13773 | recognized, otherwise report an error and return null. | |
13774 | ||
13775 | A similar function exists in GCC. */ | |
e7af610e NC |
13776 | |
13777 | static const struct mips_cpu_info * | |
17a2f251 | 13778 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 13779 | { |
316f5878 | 13780 | const struct mips_cpu_info *p; |
e7af610e | 13781 | |
316f5878 RS |
13782 | /* 'from-abi' selects the most compatible architecture for the given |
13783 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
13784 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
13785 | version. Look first at the -mgp options, if given, otherwise base | |
13786 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 13787 | |
316f5878 RS |
13788 | Treat NO_ABI like the EABIs. One reason to do this is that the |
13789 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
13790 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
13791 | 'mips64', just as we did in the days before 'from-abi'. */ | |
13792 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
13793 | { | |
13794 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
13795 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
13796 | ||
13797 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
13798 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
13799 | ||
13800 | if (file_mips_gp32 >= 0) | |
13801 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
13802 | ||
13803 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
13804 | ? ISA_MIPS3 | |
13805 | : ISA_MIPS1); | |
13806 | } | |
13807 | ||
13808 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
13809 | if (strcasecmp (cpu_string, "default") == 0) | |
13810 | return 0; | |
13811 | ||
13812 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
13813 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
13814 | return p; | |
13815 | ||
13816 | as_bad ("Bad value (%s) for %s", cpu_string, option); | |
13817 | return 0; | |
e7af610e NC |
13818 | } |
13819 | ||
316f5878 RS |
13820 | /* Return the canonical processor information for ISA (a member of the |
13821 | ISA_MIPS* enumeration). */ | |
13822 | ||
e7af610e | 13823 | static const struct mips_cpu_info * |
17a2f251 | 13824 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
13825 | { |
13826 | int i; | |
13827 | ||
13828 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
13829 | if (mips_cpu_info_table[i].is_isa | |
316f5878 | 13830 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
13831 | return (&mips_cpu_info_table[i]); |
13832 | ||
e972090a | 13833 | return NULL; |
e7af610e | 13834 | } |
fef14a42 TS |
13835 | |
13836 | static const struct mips_cpu_info * | |
17a2f251 | 13837 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
13838 | { |
13839 | int i; | |
13840 | ||
13841 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
13842 | if (arch == mips_cpu_info_table[i].cpu) | |
13843 | return (&mips_cpu_info_table[i]); | |
13844 | ||
13845 | return NULL; | |
13846 | } | |
316f5878 RS |
13847 | \f |
13848 | static void | |
17a2f251 | 13849 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
13850 | { |
13851 | if (*first_p) | |
13852 | { | |
13853 | fprintf (stream, "%24s", ""); | |
13854 | *col_p = 24; | |
13855 | } | |
13856 | else | |
13857 | { | |
13858 | fprintf (stream, ", "); | |
13859 | *col_p += 2; | |
13860 | } | |
e7af610e | 13861 | |
316f5878 RS |
13862 | if (*col_p + strlen (string) > 72) |
13863 | { | |
13864 | fprintf (stream, "\n%24s", ""); | |
13865 | *col_p = 24; | |
13866 | } | |
13867 | ||
13868 | fprintf (stream, "%s", string); | |
13869 | *col_p += strlen (string); | |
13870 | ||
13871 | *first_p = 0; | |
13872 | } | |
13873 | ||
13874 | void | |
17a2f251 | 13875 | md_show_usage (FILE *stream) |
e7af610e | 13876 | { |
316f5878 RS |
13877 | int column, first; |
13878 | size_t i; | |
13879 | ||
13880 | fprintf (stream, _("\ | |
13881 | MIPS options:\n\ | |
316f5878 RS |
13882 | -EB generate big endian output\n\ |
13883 | -EL generate little endian output\n\ | |
13884 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
13885 | -G NUM allow referencing objects up to NUM bytes\n\ | |
13886 | implicitly with the gp register [default 8]\n")); | |
13887 | fprintf (stream, _("\ | |
13888 | -mips1 generate MIPS ISA I instructions\n\ | |
13889 | -mips2 generate MIPS ISA II instructions\n\ | |
13890 | -mips3 generate MIPS ISA III instructions\n\ | |
13891 | -mips4 generate MIPS ISA IV instructions\n\ | |
13892 | -mips5 generate MIPS ISA V instructions\n\ | |
13893 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 13894 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 | 13895 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 13896 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
316f5878 RS |
13897 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
13898 | ||
13899 | first = 1; | |
e7af610e NC |
13900 | |
13901 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
13902 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
13903 | show (stream, "from-abi", &column, &first); | |
13904 | fputc ('\n', stream); | |
e7af610e | 13905 | |
316f5878 RS |
13906 | fprintf (stream, _("\ |
13907 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
13908 | -no-mCPU don't generate code specific to CPU.\n\ | |
13909 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
13910 | ||
13911 | first = 1; | |
13912 | ||
13913 | show (stream, "3900", &column, &first); | |
13914 | show (stream, "4010", &column, &first); | |
13915 | show (stream, "4100", &column, &first); | |
13916 | show (stream, "4650", &column, &first); | |
13917 | fputc ('\n', stream); | |
13918 | ||
13919 | fprintf (stream, _("\ | |
13920 | -mips16 generate mips16 instructions\n\ | |
13921 | -no-mips16 do not generate mips16 instructions\n")); | |
13922 | fprintf (stream, _("\ | |
d766e8ec | 13923 | -mfix-vr4120 work around certain VR4120 errata\n\ |
316f5878 RS |
13924 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
13925 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
aed1a261 RS |
13926 | -mno-shared optimize output for executables\n\ |
13927 | -msym32 assume all symbols have 32-bit values\n\ | |
316f5878 RS |
13928 | -O0 remove unneeded NOPs, do not swap branches\n\ |
13929 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
13930 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ |
13931 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ | |
13932 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
13933 | #ifdef OBJ_ELF | |
13934 | fprintf (stream, _("\ | |
13935 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
13936 | -non_shared do not generate position independent code\n\ | |
13937 | -xgot assume a 32 bit GOT\n\ | |
dcd410fe | 13938 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
bbe506e8 TS |
13939 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
13940 | non-shared code\n\ | |
316f5878 RS |
13941 | -mabi=ABI create ABI conformant object file for:\n")); |
13942 | ||
13943 | first = 1; | |
13944 | ||
13945 | show (stream, "32", &column, &first); | |
13946 | show (stream, "o64", &column, &first); | |
13947 | show (stream, "n32", &column, &first); | |
13948 | show (stream, "64", &column, &first); | |
13949 | show (stream, "eabi", &column, &first); | |
13950 | ||
13951 | fputc ('\n', stream); | |
13952 | ||
13953 | fprintf (stream, _("\ | |
13954 | -32 create o32 ABI object file (default)\n\ | |
13955 | -n32 create n32 ABI object file\n\ | |
13956 | -64 create 64 ABI object file\n")); | |
13957 | #endif | |
e7af610e | 13958 | } |
14e777e0 KB |
13959 | |
13960 | enum dwarf2_format | |
17a2f251 | 13961 | mips_dwarf2_format (void) |
14e777e0 KB |
13962 | { |
13963 | if (mips_abi == N64_ABI) | |
1de5b6a1 AO |
13964 | { |
13965 | #ifdef TE_IRIX | |
13966 | return dwarf2_format_64bit_irix; | |
13967 | #else | |
13968 | return dwarf2_format_64bit; | |
13969 | #endif | |
13970 | } | |
14e777e0 KB |
13971 | else |
13972 | return dwarf2_format_32bit; | |
13973 | } | |
73369e65 EC |
13974 | |
13975 | int | |
13976 | mips_dwarf2_addr_size (void) | |
13977 | { | |
13978 | if (mips_abi == N64_ABI) | |
13979 | return 8; | |
73369e65 EC |
13980 | else |
13981 | return 4; | |
13982 | } |