Commit | Line | Data |
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252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
219d1afa | 2 | Copyright (C) 1993-2018 Free Software Foundation, Inc. |
252b5132 RH |
3 | Contributed by the OSF and Ralph Campbell. |
4 | Written by Keith Knowles and Ralph Campbell, working independently. | |
5 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
6 | Support. | |
7 | ||
8 | This file is part of GAS. | |
9 | ||
10 | GAS is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 12 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
13 | any later version. |
14 | ||
15 | GAS is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
21 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
22 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
23 | 02110-1301, USA. */ | |
252b5132 RH |
24 | |
25 | #include "as.h" | |
26 | #include "config.h" | |
27 | #include "subsegs.h" | |
3882b010 | 28 | #include "safe-ctype.h" |
252b5132 | 29 | |
252b5132 RH |
30 | #include "opcode/mips.h" |
31 | #include "itbl-ops.h" | |
c5dd6aab | 32 | #include "dwarf2dbg.h" |
5862107c | 33 | #include "dw2gencfi.h" |
252b5132 | 34 | |
42429eac RS |
35 | /* Check assumptions made in this file. */ |
36 | typedef char static_assert1[sizeof (offsetT) < 8 ? -1 : 1]; | |
37 | typedef char static_assert2[sizeof (valueT) < 8 ? -1 : 1]; | |
38 | ||
252b5132 RH |
39 | #ifdef DEBUG |
40 | #define DBG(x) printf x | |
41 | #else | |
42 | #define DBG(x) | |
43 | #endif | |
44 | ||
263b2574 | 45 | #define streq(a, b) (strcmp (a, b) == 0) |
46 | ||
9e12b7a2 RS |
47 | #define SKIP_SPACE_TABS(S) \ |
48 | do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0) | |
49 | ||
252b5132 | 50 | /* Clean up namespace so we can include obj-elf.h too. */ |
17a2f251 TS |
51 | static int mips_output_flavor (void); |
52 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
53 | #undef OBJ_PROCESS_STAB |
54 | #undef OUTPUT_FLAVOR | |
55 | #undef S_GET_ALIGN | |
56 | #undef S_GET_SIZE | |
57 | #undef S_SET_ALIGN | |
58 | #undef S_SET_SIZE | |
252b5132 RH |
59 | #undef obj_frob_file |
60 | #undef obj_frob_file_after_relocs | |
61 | #undef obj_frob_symbol | |
62 | #undef obj_pop_insert | |
63 | #undef obj_sec_sym_ok_for_reloc | |
64 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
65 | ||
66 | #include "obj-elf.h" | |
67 | /* Fix any of them that we actually care about. */ | |
68 | #undef OUTPUT_FLAVOR | |
69 | #define OUTPUT_FLAVOR mips_output_flavor() | |
252b5132 | 70 | |
252b5132 | 71 | #include "elf/mips.h" |
252b5132 RH |
72 | |
73 | #ifndef ECOFF_DEBUGGING | |
74 | #define NO_ECOFF_DEBUGGING | |
75 | #define ECOFF_DEBUGGING 0 | |
76 | #endif | |
77 | ||
ecb4347a DJ |
78 | int mips_flag_mdebug = -1; |
79 | ||
dcd410fe RO |
80 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
81 | linker doesn't know about and discards them, but relocations against them | |
82 | remain, leading to rld crashes. */ | |
83 | #ifdef TE_IRIX | |
84 | int mips_flag_pdr = FALSE; | |
85 | #else | |
86 | int mips_flag_pdr = TRUE; | |
87 | #endif | |
88 | ||
252b5132 RH |
89 | #include "ecoff.h" |
90 | ||
252b5132 | 91 | static char *mips_regmask_frag; |
351cdf24 | 92 | static char *mips_flags_frag; |
252b5132 | 93 | |
85b51719 | 94 | #define ZERO 0 |
741fe287 | 95 | #define ATREG 1 |
df58fc94 RS |
96 | #define S0 16 |
97 | #define S7 23 | |
252b5132 RH |
98 | #define TREG 24 |
99 | #define PIC_CALL_REG 25 | |
100 | #define KT0 26 | |
101 | #define KT1 27 | |
102 | #define GP 28 | |
103 | #define SP 29 | |
104 | #define FP 30 | |
105 | #define RA 31 | |
106 | ||
107 | #define ILLEGAL_REG (32) | |
108 | ||
741fe287 MR |
109 | #define AT mips_opts.at |
110 | ||
252b5132 RH |
111 | extern int target_big_endian; |
112 | ||
252b5132 | 113 | /* The name of the readonly data section. */ |
e8044f35 | 114 | #define RDATA_SECTION_NAME ".rodata" |
252b5132 | 115 | |
a4e06468 RS |
116 | /* Ways in which an instruction can be "appended" to the output. */ |
117 | enum append_method { | |
118 | /* Just add it normally. */ | |
119 | APPEND_ADD, | |
120 | ||
121 | /* Add it normally and then add a nop. */ | |
122 | APPEND_ADD_WITH_NOP, | |
123 | ||
124 | /* Turn an instruction with a delay slot into a "compact" version. */ | |
125 | APPEND_ADD_COMPACT, | |
126 | ||
127 | /* Insert the instruction before the last one. */ | |
128 | APPEND_SWAP | |
129 | }; | |
130 | ||
47e39b9d RS |
131 | /* Information about an instruction, including its format, operands |
132 | and fixups. */ | |
133 | struct mips_cl_insn | |
134 | { | |
135 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ | |
136 | const struct mips_opcode *insn_mo; | |
137 | ||
47e39b9d | 138 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is |
5c04167a RS |
139 | a copy of INSN_MO->match with the operands filled in. If we have |
140 | decided to use an extended MIPS16 instruction, this includes the | |
141 | extension. */ | |
47e39b9d RS |
142 | unsigned long insn_opcode; |
143 | ||
144 | /* The frag that contains the instruction. */ | |
145 | struct frag *frag; | |
146 | ||
147 | /* The offset into FRAG of the first instruction byte. */ | |
148 | long where; | |
149 | ||
150 | /* The relocs associated with the instruction, if any. */ | |
151 | fixS *fixp[3]; | |
152 | ||
a38419a5 RS |
153 | /* True if this entry cannot be moved from its current position. */ |
154 | unsigned int fixed_p : 1; | |
47e39b9d | 155 | |
708587a4 | 156 | /* True if this instruction occurred in a .set noreorder block. */ |
47e39b9d RS |
157 | unsigned int noreorder_p : 1; |
158 | ||
2fa15973 RS |
159 | /* True for mips16 instructions that jump to an absolute address. */ |
160 | unsigned int mips16_absolute_jump_p : 1; | |
15be625d CM |
161 | |
162 | /* True if this instruction is complete. */ | |
163 | unsigned int complete_p : 1; | |
e407c74b NC |
164 | |
165 | /* True if this instruction is cleared from history by unconditional | |
166 | branch. */ | |
167 | unsigned int cleared_p : 1; | |
47e39b9d RS |
168 | }; |
169 | ||
a325df1d TS |
170 | /* The ABI to use. */ |
171 | enum mips_abi_level | |
172 | { | |
173 | NO_ABI = 0, | |
174 | O32_ABI, | |
175 | O64_ABI, | |
176 | N32_ABI, | |
177 | N64_ABI, | |
178 | EABI_ABI | |
179 | }; | |
180 | ||
181 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 182 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 183 | |
143d77c5 EC |
184 | /* Whether or not we have code that can call pic code. */ |
185 | int mips_abicalls = FALSE; | |
186 | ||
aa6975fb ILT |
187 | /* Whether or not we have code which can be put into a shared |
188 | library. */ | |
189 | static bfd_boolean mips_in_shared = TRUE; | |
190 | ||
252b5132 RH |
191 | /* This is the set of options which may be modified by the .set |
192 | pseudo-op. We use a struct so that .set push and .set pop are more | |
193 | reliable. */ | |
194 | ||
e972090a NC |
195 | struct mips_set_options |
196 | { | |
252b5132 RH |
197 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
198 | if it has not been initialized. Changed by `.set mipsN', and the | |
199 | -mipsN command line option, and the default CPU. */ | |
200 | int isa; | |
846ef2d0 RS |
201 | /* Enabled Application Specific Extensions (ASEs). Changed by `.set |
202 | <asename>', by command line options, and based on the default | |
203 | architecture. */ | |
204 | int ase; | |
252b5132 RH |
205 | /* Whether we are assembling for the mips16 processor. 0 if we are |
206 | not, 1 if we are, and -1 if the value has not been initialized. | |
207 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
208 | -nomips16 command line options, and the default CPU. */ | |
209 | int mips16; | |
df58fc94 RS |
210 | /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not, |
211 | 1 if we are, and -1 if the value has not been initialized. Changed | |
212 | by `.set micromips' and `.set nomicromips', and the -mmicromips | |
213 | and -mno-micromips command line options, and the default CPU. */ | |
214 | int micromips; | |
252b5132 RH |
215 | /* Non-zero if we should not reorder instructions. Changed by `.set |
216 | reorder' and `.set noreorder'. */ | |
217 | int noreorder; | |
741fe287 MR |
218 | /* Non-zero if we should not permit the register designated "assembler |
219 | temporary" to be used in instructions. The value is the register | |
220 | number, normally $at ($1). Changed by `.set at=REG', `.set noat' | |
221 | (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */ | |
222 | unsigned int at; | |
252b5132 RH |
223 | /* Non-zero if we should warn when a macro instruction expands into |
224 | more than one machine instruction. Changed by `.set nomacro' and | |
225 | `.set macro'. */ | |
226 | int warn_about_macros; | |
227 | /* Non-zero if we should not move instructions. Changed by `.set | |
228 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
229 | int nomove; | |
230 | /* Non-zero if we should not optimize branches by moving the target | |
231 | of the branch into the delay slot. Actually, we don't perform | |
232 | this optimization anyhow. Changed by `.set bopt' and `.set | |
233 | nobopt'. */ | |
234 | int nobopt; | |
235 | /* Non-zero if we should not autoextend mips16 instructions. | |
236 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
237 | int noautoextend; | |
833794fc MR |
238 | /* True if we should only emit 32-bit microMIPS instructions. |
239 | Changed by `.set insn32' and `.set noinsn32', and the -minsn32 | |
240 | and -mno-insn32 command line options. */ | |
241 | bfd_boolean insn32; | |
a325df1d TS |
242 | /* Restrict general purpose registers and floating point registers |
243 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
244 | is passed but can changed if the assembler code uses .set mipsN. */ | |
bad1aba3 | 245 | int gp; |
0b35dfee | 246 | int fp; |
fef14a42 TS |
247 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
248 | command line option, and the default CPU. */ | |
249 | int arch; | |
aed1a261 RS |
250 | /* True if ".set sym32" is in effect. */ |
251 | bfd_boolean sym32; | |
037b32b9 AN |
252 | /* True if floating-point operations are not allowed. Changed by .set |
253 | softfloat or .set hardfloat, by command line options -msoft-float or | |
254 | -mhard-float. The default is false. */ | |
255 | bfd_boolean soft_float; | |
256 | ||
257 | /* True if only single-precision floating-point operations are allowed. | |
258 | Changed by .set singlefloat or .set doublefloat, command-line options | |
259 | -msingle-float or -mdouble-float. The default is false. */ | |
260 | bfd_boolean single_float; | |
351cdf24 MF |
261 | |
262 | /* 1 if single-precision operations on odd-numbered registers are | |
263 | allowed. */ | |
264 | int oddspreg; | |
252b5132 RH |
265 | }; |
266 | ||
919731af | 267 | /* Specifies whether module level options have been checked yet. */ |
268 | static bfd_boolean file_mips_opts_checked = FALSE; | |
269 | ||
7361da2c AB |
270 | /* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the |
271 | value has not been initialized. Changed by `.nan legacy' and | |
272 | `.nan 2008', and the -mnan=legacy and -mnan=2008 command line | |
273 | options, and the default CPU. */ | |
274 | static int mips_nan2008 = -1; | |
a325df1d | 275 | |
0b35dfee | 276 | /* This is the struct we use to hold the module level set of options. |
bad1aba3 | 277 | Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and |
0b35dfee | 278 | fp fields to -1 to indicate that they have not been initialized. */ |
037b32b9 | 279 | |
0b35dfee | 280 | static struct mips_set_options file_mips_opts = |
281 | { | |
282 | /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1, | |
283 | /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0, | |
284 | /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE, | |
bad1aba3 | 285 | /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE, |
351cdf24 | 286 | /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1 |
0b35dfee | 287 | }; |
252b5132 | 288 | |
0b35dfee | 289 | /* This is similar to file_mips_opts, but for the current set of options. */ |
ba92f887 | 290 | |
e972090a NC |
291 | static struct mips_set_options mips_opts = |
292 | { | |
846ef2d0 | 293 | /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1, |
b015e599 | 294 | /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0, |
833794fc | 295 | /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE, |
bad1aba3 | 296 | /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE, |
351cdf24 | 297 | /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1 |
e7af610e | 298 | }; |
252b5132 | 299 | |
846ef2d0 RS |
300 | /* Which bits of file_ase were explicitly set or cleared by ASE options. */ |
301 | static unsigned int file_ase_explicit; | |
302 | ||
252b5132 RH |
303 | /* These variables are filled in with the masks of registers used. |
304 | The object format code reads them and puts them in the appropriate | |
305 | place. */ | |
306 | unsigned long mips_gprmask; | |
307 | unsigned long mips_cprmask[4]; | |
308 | ||
738f4d98 | 309 | /* True if any MIPS16 code was produced. */ |
a4672219 TS |
310 | static int file_ase_mips16; |
311 | ||
3994f87e TS |
312 | #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \ |
313 | || mips_opts.isa == ISA_MIPS32R2 \ | |
ae52f483 AB |
314 | || mips_opts.isa == ISA_MIPS32R3 \ |
315 | || mips_opts.isa == ISA_MIPS32R5 \ | |
3994f87e | 316 | || mips_opts.isa == ISA_MIPS64 \ |
ae52f483 AB |
317 | || mips_opts.isa == ISA_MIPS64R2 \ |
318 | || mips_opts.isa == ISA_MIPS64R3 \ | |
319 | || mips_opts.isa == ISA_MIPS64R5) | |
3994f87e | 320 | |
df58fc94 RS |
321 | /* True if any microMIPS code was produced. */ |
322 | static int file_ase_micromips; | |
323 | ||
b12dd2e4 CF |
324 | /* True if we want to create R_MIPS_JALR for jalr $25. */ |
325 | #ifdef TE_IRIX | |
1180b5a4 | 326 | #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI |
b12dd2e4 | 327 | #else |
1180b5a4 RS |
328 | /* As a GNU extension, we use R_MIPS_JALR for o32 too. However, |
329 | because there's no place for any addend, the only acceptable | |
330 | expression is a bare symbol. */ | |
331 | #define MIPS_JALR_HINT_P(EXPR) \ | |
332 | (!HAVE_IN_PLACE_ADDENDS \ | |
333 | || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0)) | |
b12dd2e4 CF |
334 | #endif |
335 | ||
ec68c924 | 336 | /* The argument of the -march= flag. The architecture we are assembling. */ |
316f5878 | 337 | static const char *mips_arch_string; |
ec68c924 EC |
338 | |
339 | /* The argument of the -mtune= flag. The architecture for which we | |
340 | are optimizing. */ | |
341 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 342 | static const char *mips_tune_string; |
ec68c924 | 343 | |
316f5878 | 344 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
345 | static int mips_32bitmode = 0; |
346 | ||
316f5878 RS |
347 | /* True if the given ABI requires 32-bit registers. */ |
348 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
349 | ||
350 | /* Likewise 64-bit registers. */ | |
707bfff6 | 351 | #define ABI_NEEDS_64BIT_REGS(ABI) \ |
134c0c8b | 352 | ((ABI) == N32_ABI \ |
707bfff6 | 353 | || (ABI) == N64_ABI \ |
316f5878 RS |
354 | || (ABI) == O64_ABI) |
355 | ||
7361da2c AB |
356 | #define ISA_IS_R6(ISA) \ |
357 | ((ISA) == ISA_MIPS32R6 \ | |
358 | || (ISA) == ISA_MIPS64R6) | |
359 | ||
ad3fea08 | 360 | /* Return true if ISA supports 64 bit wide gp registers. */ |
707bfff6 TS |
361 | #define ISA_HAS_64BIT_REGS(ISA) \ |
362 | ((ISA) == ISA_MIPS3 \ | |
363 | || (ISA) == ISA_MIPS4 \ | |
364 | || (ISA) == ISA_MIPS5 \ | |
365 | || (ISA) == ISA_MIPS64 \ | |
ae52f483 AB |
366 | || (ISA) == ISA_MIPS64R2 \ |
367 | || (ISA) == ISA_MIPS64R3 \ | |
7361da2c AB |
368 | || (ISA) == ISA_MIPS64R5 \ |
369 | || (ISA) == ISA_MIPS64R6) | |
9ce8a5dd | 370 | |
ad3fea08 TS |
371 | /* Return true if ISA supports 64 bit wide float registers. */ |
372 | #define ISA_HAS_64BIT_FPRS(ISA) \ | |
373 | ((ISA) == ISA_MIPS3 \ | |
374 | || (ISA) == ISA_MIPS4 \ | |
375 | || (ISA) == ISA_MIPS5 \ | |
376 | || (ISA) == ISA_MIPS32R2 \ | |
ae52f483 AB |
377 | || (ISA) == ISA_MIPS32R3 \ |
378 | || (ISA) == ISA_MIPS32R5 \ | |
7361da2c | 379 | || (ISA) == ISA_MIPS32R6 \ |
ad3fea08 | 380 | || (ISA) == ISA_MIPS64 \ |
ae52f483 AB |
381 | || (ISA) == ISA_MIPS64R2 \ |
382 | || (ISA) == ISA_MIPS64R3 \ | |
7361da2c AB |
383 | || (ISA) == ISA_MIPS64R5 \ |
384 | || (ISA) == ISA_MIPS64R6) | |
ad3fea08 | 385 | |
af7ee8bf CD |
386 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
387 | instructions. */ | |
707bfff6 | 388 | #define ISA_HAS_DROR(ISA) \ |
df58fc94 | 389 | ((ISA) == ISA_MIPS64R2 \ |
ae52f483 AB |
390 | || (ISA) == ISA_MIPS64R3 \ |
391 | || (ISA) == ISA_MIPS64R5 \ | |
7361da2c | 392 | || (ISA) == ISA_MIPS64R6 \ |
df58fc94 RS |
393 | || (mips_opts.micromips \ |
394 | && ISA_HAS_64BIT_REGS (ISA)) \ | |
395 | ) | |
af7ee8bf CD |
396 | |
397 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
398 | instructions. */ | |
707bfff6 TS |
399 | #define ISA_HAS_ROR(ISA) \ |
400 | ((ISA) == ISA_MIPS32R2 \ | |
ae52f483 AB |
401 | || (ISA) == ISA_MIPS32R3 \ |
402 | || (ISA) == ISA_MIPS32R5 \ | |
7361da2c | 403 | || (ISA) == ISA_MIPS32R6 \ |
707bfff6 | 404 | || (ISA) == ISA_MIPS64R2 \ |
ae52f483 AB |
405 | || (ISA) == ISA_MIPS64R3 \ |
406 | || (ISA) == ISA_MIPS64R5 \ | |
7361da2c | 407 | || (ISA) == ISA_MIPS64R6 \ |
846ef2d0 | 408 | || (mips_opts.ase & ASE_SMARTMIPS) \ |
df58fc94 RS |
409 | || mips_opts.micromips \ |
410 | ) | |
707bfff6 | 411 | |
7455baf8 | 412 | /* Return true if ISA supports single-precision floats in odd registers. */ |
351cdf24 MF |
413 | #define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\ |
414 | (((ISA) == ISA_MIPS32 \ | |
415 | || (ISA) == ISA_MIPS32R2 \ | |
416 | || (ISA) == ISA_MIPS32R3 \ | |
417 | || (ISA) == ISA_MIPS32R5 \ | |
7361da2c | 418 | || (ISA) == ISA_MIPS32R6 \ |
351cdf24 MF |
419 | || (ISA) == ISA_MIPS64 \ |
420 | || (ISA) == ISA_MIPS64R2 \ | |
421 | || (ISA) == ISA_MIPS64R3 \ | |
422 | || (ISA) == ISA_MIPS64R5 \ | |
7361da2c | 423 | || (ISA) == ISA_MIPS64R6 \ |
351cdf24 MF |
424 | || (CPU) == CPU_R5900) \ |
425 | && (CPU) != CPU_LOONGSON_3A) | |
af7ee8bf | 426 | |
ad3fea08 TS |
427 | /* Return true if ISA supports move to/from high part of a 64-bit |
428 | floating-point register. */ | |
429 | #define ISA_HAS_MXHC1(ISA) \ | |
430 | ((ISA) == ISA_MIPS32R2 \ | |
ae52f483 AB |
431 | || (ISA) == ISA_MIPS32R3 \ |
432 | || (ISA) == ISA_MIPS32R5 \ | |
7361da2c AB |
433 | || (ISA) == ISA_MIPS32R6 \ |
434 | || (ISA) == ISA_MIPS64R2 \ | |
435 | || (ISA) == ISA_MIPS64R3 \ | |
436 | || (ISA) == ISA_MIPS64R5 \ | |
437 | || (ISA) == ISA_MIPS64R6) | |
438 | ||
439 | /* Return true if ISA supports legacy NAN. */ | |
440 | #define ISA_HAS_LEGACY_NAN(ISA) \ | |
441 | ((ISA) == ISA_MIPS1 \ | |
442 | || (ISA) == ISA_MIPS2 \ | |
443 | || (ISA) == ISA_MIPS3 \ | |
444 | || (ISA) == ISA_MIPS4 \ | |
445 | || (ISA) == ISA_MIPS5 \ | |
446 | || (ISA) == ISA_MIPS32 \ | |
447 | || (ISA) == ISA_MIPS32R2 \ | |
448 | || (ISA) == ISA_MIPS32R3 \ | |
449 | || (ISA) == ISA_MIPS32R5 \ | |
450 | || (ISA) == ISA_MIPS64 \ | |
ae52f483 AB |
451 | || (ISA) == ISA_MIPS64R2 \ |
452 | || (ISA) == ISA_MIPS64R3 \ | |
453 | || (ISA) == ISA_MIPS64R5) | |
ad3fea08 | 454 | |
bad1aba3 | 455 | #define GPR_SIZE \ |
456 | (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \ | |
457 | ? 32 \ | |
458 | : mips_opts.gp) | |
ca4e0257 | 459 | |
bad1aba3 | 460 | #define FPR_SIZE \ |
461 | (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \ | |
462 | ? 32 \ | |
463 | : mips_opts.fp) | |
ca4e0257 | 464 | |
316f5878 | 465 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 466 | |
316f5878 | 467 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 468 | |
3b91255e RS |
469 | /* True if relocations are stored in-place. */ |
470 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
471 | ||
aed1a261 RS |
472 | /* The ABI-derived address size. */ |
473 | #define HAVE_64BIT_ADDRESSES \ | |
bad1aba3 | 474 | (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) |
aed1a261 | 475 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) |
e013f690 | 476 | |
aed1a261 RS |
477 | /* The size of symbolic constants (i.e., expressions of the form |
478 | "SYMBOL" or "SYMBOL + OFFSET"). */ | |
479 | #define HAVE_32BIT_SYMBOLS \ | |
480 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) | |
481 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) | |
ca4e0257 | 482 | |
b7c7d6c1 TS |
483 | /* Addresses are loaded in different ways, depending on the address size |
484 | in use. The n32 ABI Documentation also mandates the use of additions | |
485 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 486 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 487 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
488 | |
489 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 490 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
491 | |
492 | #define ADDRESS_LOAD_INSN \ | |
493 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
494 | ||
495 | #define ADDRESS_STORE_INSN \ | |
496 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
497 | ||
a4672219 | 498 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
499 | #define CPU_HAS_MIPS16(cpu) \ |
500 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
501 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 502 | |
2309ddf2 | 503 | /* Return true if the given CPU supports the microMIPS ASE. */ |
df58fc94 RS |
504 | #define CPU_HAS_MICROMIPS(cpu) 0 |
505 | ||
60b63b72 RS |
506 | /* True if CPU has a dror instruction. */ |
507 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
508 | ||
509 | /* True if CPU has a ror instruction. */ | |
510 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
511 | ||
dd6a37e7 | 512 | /* True if CPU is in the Octeon family */ |
2c629856 N |
513 | #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \ |
514 | || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3) | |
dd6a37e7 | 515 | |
dd3cbb7e | 516 | /* True if CPU has seq/sne and seqi/snei instructions. */ |
dd6a37e7 | 517 | #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU)) |
dd3cbb7e | 518 | |
0aa27725 RS |
519 | /* True, if CPU has support for ldc1 and sdc1. */ |
520 | #define CPU_HAS_LDC1_SDC1(CPU) \ | |
521 | ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900)) | |
522 | ||
c8978940 CD |
523 | /* True if mflo and mfhi can be immediately followed by instructions |
524 | which write to the HI and LO registers. | |
525 | ||
526 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
527 | (at least) two instructions between the reads of HI/LO and | |
528 | instructions which write them, and later ISAs do not. Contradicting | |
529 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
530 | the UM for the NEC Vr5000) document needing the instructions between | |
531 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
532 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
533 | earlier-ISA CPUs for which CPU documentation declares that the | |
534 | instructions are really interlocked. */ | |
535 | #define hilo_interlocks \ | |
536 | (mips_opts.isa == ISA_MIPS32 \ | |
537 | || mips_opts.isa == ISA_MIPS32R2 \ | |
ae52f483 AB |
538 | || mips_opts.isa == ISA_MIPS32R3 \ |
539 | || mips_opts.isa == ISA_MIPS32R5 \ | |
7361da2c | 540 | || mips_opts.isa == ISA_MIPS32R6 \ |
c8978940 CD |
541 | || mips_opts.isa == ISA_MIPS64 \ |
542 | || mips_opts.isa == ISA_MIPS64R2 \ | |
ae52f483 AB |
543 | || mips_opts.isa == ISA_MIPS64R3 \ |
544 | || mips_opts.isa == ISA_MIPS64R5 \ | |
7361da2c | 545 | || mips_opts.isa == ISA_MIPS64R6 \ |
c8978940 | 546 | || mips_opts.arch == CPU_R4010 \ |
e407c74b | 547 | || mips_opts.arch == CPU_R5900 \ |
c8978940 CD |
548 | || mips_opts.arch == CPU_R10000 \ |
549 | || mips_opts.arch == CPU_R12000 \ | |
3aa3176b TS |
550 | || mips_opts.arch == CPU_R14000 \ |
551 | || mips_opts.arch == CPU_R16000 \ | |
c8978940 | 552 | || mips_opts.arch == CPU_RM7000 \ |
c8978940 | 553 | || mips_opts.arch == CPU_VR5500 \ |
df58fc94 | 554 | || mips_opts.micromips \ |
c8978940 | 555 | ) |
252b5132 RH |
556 | |
557 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
558 | from the GPRs after they are loaded from memory, and thus does not |
559 | require nops to be inserted. This applies to instructions marked | |
67dc82bc | 560 | INSN_LOAD_MEMORY. These nops are only required at MIPS ISA |
df58fc94 RS |
561 | level I and microMIPS mode instructions are always interlocked. */ |
562 | #define gpr_interlocks \ | |
563 | (mips_opts.isa != ISA_MIPS1 \ | |
564 | || mips_opts.arch == CPU_R3900 \ | |
e407c74b | 565 | || mips_opts.arch == CPU_R5900 \ |
df58fc94 RS |
566 | || mips_opts.micromips \ |
567 | ) | |
252b5132 | 568 | |
81912461 ILT |
569 | /* Whether the processor uses hardware interlocks to avoid delays |
570 | required by coprocessor instructions, and thus does not require | |
571 | nops to be inserted. This applies to instructions marked | |
43885403 MF |
572 | INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between |
573 | instructions marked INSN_WRITE_COND_CODE and ones marked | |
81912461 | 574 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA |
df58fc94 RS |
575 | levels I, II, and III and microMIPS mode instructions are always |
576 | interlocked. */ | |
bdaaa2e1 | 577 | /* Itbl support may require additional care here. */ |
81912461 ILT |
578 | #define cop_interlocks \ |
579 | ((mips_opts.isa != ISA_MIPS1 \ | |
580 | && mips_opts.isa != ISA_MIPS2 \ | |
581 | && mips_opts.isa != ISA_MIPS3) \ | |
582 | || mips_opts.arch == CPU_R4300 \ | |
df58fc94 | 583 | || mips_opts.micromips \ |
81912461 ILT |
584 | ) |
585 | ||
586 | /* Whether the processor uses hardware interlocks to protect reads | |
587 | from coprocessor registers after they are loaded from memory, and | |
588 | thus does not require nops to be inserted. This applies to | |
589 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
df58fc94 RS |
590 | requires at MIPS ISA level I and microMIPS mode instructions are |
591 | always interlocked. */ | |
592 | #define cop_mem_interlocks \ | |
593 | (mips_opts.isa != ISA_MIPS1 \ | |
594 | || mips_opts.micromips \ | |
595 | ) | |
252b5132 | 596 | |
6b76fefe CM |
597 | /* Is this a mfhi or mflo instruction? */ |
598 | #define MF_HILO_INSN(PINFO) \ | |
b19e8a9b AN |
599 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) |
600 | ||
df58fc94 RS |
601 | /* Whether code compression (either of the MIPS16 or the microMIPS ASEs) |
602 | has been selected. This implies, in particular, that addresses of text | |
603 | labels have their LSB set. */ | |
604 | #define HAVE_CODE_COMPRESSION \ | |
605 | ((mips_opts.mips16 | mips_opts.micromips) != 0) | |
606 | ||
42429eac | 607 | /* The minimum and maximum signed values that can be stored in a GPR. */ |
bad1aba3 | 608 | #define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1)) |
42429eac RS |
609 | #define GPR_SMIN (-GPR_SMAX - 1) |
610 | ||
252b5132 RH |
611 | /* MIPS PIC level. */ |
612 | ||
a161fe53 | 613 | enum mips_pic_level mips_pic; |
252b5132 | 614 | |
c9914766 | 615 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 616 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 617 | static int mips_big_got = 0; |
252b5132 RH |
618 | |
619 | /* 1 if trap instructions should used for overflow rather than break | |
620 | instructions. */ | |
c9914766 | 621 | static int mips_trap = 0; |
252b5132 | 622 | |
119d663a | 623 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 624 | by assembling two single width halves into two single width floating |
119d663a NC |
625 | point registers which just happen to alias the double width destination |
626 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 627 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
628 | automatically at assemble time. */ |
629 | static int mips_disable_float_construction; | |
630 | ||
252b5132 RH |
631 | /* Non-zero if any .set noreorder directives were used. */ |
632 | ||
633 | static int mips_any_noreorder; | |
634 | ||
6b76fefe CM |
635 | /* Non-zero if nops should be inserted when the register referenced in |
636 | an mfhi/mflo instruction is read in the next two instructions. */ | |
637 | static int mips_7000_hilo_fix; | |
638 | ||
02ffd3e4 | 639 | /* The size of objects in the small data section. */ |
156c2f8b | 640 | static unsigned int g_switch_value = 8; |
252b5132 RH |
641 | /* Whether the -G option was used. */ |
642 | static int g_switch_seen = 0; | |
643 | ||
644 | #define N_RMASK 0xc4 | |
645 | #define N_VFP 0xd4 | |
646 | ||
647 | /* If we can determine in advance that GP optimization won't be | |
648 | possible, we can skip the relaxation stuff that tries to produce | |
649 | GP-relative references. This makes delay slot optimization work | |
650 | better. | |
651 | ||
652 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
653 | gcc output. It needs to guess right for gcc, otherwise gcc |
654 | will put what it thinks is a GP-relative instruction in a branch | |
655 | delay slot. | |
252b5132 RH |
656 | |
657 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
658 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 659 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
660 | |
661 | /* handle of the OPCODE hash table */ | |
662 | static struct hash_control *op_hash = NULL; | |
663 | ||
664 | /* The opcode hash table we use for the mips16. */ | |
665 | static struct hash_control *mips16_op_hash = NULL; | |
666 | ||
df58fc94 RS |
667 | /* The opcode hash table we use for the microMIPS ASE. */ |
668 | static struct hash_control *micromips_op_hash = NULL; | |
669 | ||
252b5132 RH |
670 | /* This array holds the chars that always start a comment. If the |
671 | pre-processor is disabled, these aren't very useful */ | |
672 | const char comment_chars[] = "#"; | |
673 | ||
674 | /* This array holds the chars that only start a comment at the beginning of | |
675 | a line. If the line seems to have the form '# 123 filename' | |
676 | .line and .file directives will appear in the pre-processed output */ | |
677 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
678 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 679 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
680 | /* Also note that C style comments are always supported. */ |
681 | const char line_comment_chars[] = "#"; | |
682 | ||
bdaaa2e1 | 683 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 684 | const char line_separator_chars[] = ";"; |
252b5132 RH |
685 | |
686 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
687 | const char EXP_CHARS[] = "eE"; | |
688 | ||
689 | /* Chars that mean this number is a floating point constant */ | |
690 | /* As in 0f12.456 */ | |
691 | /* or 0d1.2345e12 */ | |
692 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
693 | ||
694 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
695 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
696 | but nothing is ideal around here. | |
697 | */ | |
698 | ||
e3de51ce RS |
699 | /* Types of printf format used for instruction-related error messages. |
700 | "I" means int ("%d") and "S" means string ("%s"). */ | |
701 | enum mips_insn_error_format { | |
702 | ERR_FMT_PLAIN, | |
703 | ERR_FMT_I, | |
704 | ERR_FMT_SS, | |
705 | }; | |
706 | ||
707 | /* Information about an error that was found while assembling the current | |
708 | instruction. */ | |
709 | struct mips_insn_error { | |
710 | /* We sometimes need to match an instruction against more than one | |
711 | opcode table entry. Errors found during this matching are reported | |
712 | against a particular syntactic argument rather than against the | |
713 | instruction as a whole. We grade these messages so that errors | |
714 | against argument N have a greater priority than an error against | |
715 | any argument < N, since the former implies that arguments up to N | |
716 | were acceptable and that the opcode entry was therefore a closer match. | |
717 | If several matches report an error against the same argument, | |
718 | we only use that error if it is the same in all cases. | |
719 | ||
720 | min_argnum is the minimum argument number for which an error message | |
721 | should be accepted. It is 0 if MSG is against the instruction as | |
722 | a whole. */ | |
723 | int min_argnum; | |
724 | ||
725 | /* The printf()-style message, including its format and arguments. */ | |
726 | enum mips_insn_error_format format; | |
727 | const char *msg; | |
728 | union { | |
729 | int i; | |
730 | const char *ss[2]; | |
731 | } u; | |
732 | }; | |
733 | ||
734 | /* The error that should be reported for the current instruction. */ | |
735 | static struct mips_insn_error insn_error; | |
252b5132 RH |
736 | |
737 | static int auto_align = 1; | |
738 | ||
739 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
740 | offset in the stack frame from which to restore the $gp register. | |
741 | This is set by the .cprestore pseudo-op, and saved in this | |
742 | variable. */ | |
743 | static offsetT mips_cprestore_offset = -1; | |
744 | ||
67c1ffbe | 745 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 746 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 747 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
748 | static offsetT mips_cpreturn_offset = -1; |
749 | static int mips_cpreturn_register = -1; | |
750 | static int mips_gp_register = GP; | |
def2e0dd | 751 | static int mips_gprel_offset = 0; |
6478892d | 752 | |
7a621144 DJ |
753 | /* Whether mips_cprestore_offset has been set in the current function |
754 | (or whether it has already been warned about, if not). */ | |
755 | static int mips_cprestore_valid = 0; | |
756 | ||
252b5132 RH |
757 | /* This is the register which holds the stack frame, as set by the |
758 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
759 | static int mips_frame_reg = SP; | |
760 | ||
7a621144 DJ |
761 | /* Whether mips_frame_reg has been set in the current function |
762 | (or whether it has already been warned about, if not). */ | |
763 | static int mips_frame_reg_valid = 0; | |
764 | ||
252b5132 RH |
765 | /* To output NOP instructions correctly, we need to keep information |
766 | about the previous two instructions. */ | |
767 | ||
768 | /* Whether we are optimizing. The default value of 2 means to remove | |
769 | unneeded NOPs and swap branch instructions when possible. A value | |
770 | of 1 means to not swap branches. A value of 0 means to always | |
771 | insert NOPs. */ | |
772 | static int mips_optimize = 2; | |
773 | ||
774 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
775 | equivalent to seeing no -g option at all. */ | |
776 | static int mips_debug = 0; | |
777 | ||
7d8e00cf RS |
778 | /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ |
779 | #define MAX_VR4130_NOPS 4 | |
780 | ||
781 | /* The maximum number of NOPs needed to fill delay slots. */ | |
782 | #define MAX_DELAY_NOPS 2 | |
783 | ||
784 | /* The maximum number of NOPs needed for any purpose. */ | |
785 | #define MAX_NOPS 4 | |
71400594 RS |
786 | |
787 | /* A list of previous instructions, with index 0 being the most recent. | |
788 | We need to look back MAX_NOPS instructions when filling delay slots | |
789 | or working around processor errata. We need to look back one | |
790 | instruction further if we're thinking about using history[0] to | |
791 | fill a branch delay slot. */ | |
792 | static struct mips_cl_insn history[1 + MAX_NOPS]; | |
252b5132 | 793 | |
fc76e730 | 794 | /* Arrays of operands for each instruction. */ |
14daeee3 | 795 | #define MAX_OPERANDS 6 |
fc76e730 RS |
796 | struct mips_operand_array { |
797 | const struct mips_operand *operand[MAX_OPERANDS]; | |
798 | }; | |
799 | static struct mips_operand_array *mips_operands; | |
800 | static struct mips_operand_array *mips16_operands; | |
801 | static struct mips_operand_array *micromips_operands; | |
802 | ||
1e915849 | 803 | /* Nop instructions used by emit_nop. */ |
df58fc94 RS |
804 | static struct mips_cl_insn nop_insn; |
805 | static struct mips_cl_insn mips16_nop_insn; | |
806 | static struct mips_cl_insn micromips_nop16_insn; | |
807 | static struct mips_cl_insn micromips_nop32_insn; | |
1e915849 RS |
808 | |
809 | /* The appropriate nop for the current mode. */ | |
833794fc MR |
810 | #define NOP_INSN (mips_opts.mips16 \ |
811 | ? &mips16_nop_insn \ | |
812 | : (mips_opts.micromips \ | |
813 | ? (mips_opts.insn32 \ | |
814 | ? µmips_nop32_insn \ | |
815 | : µmips_nop16_insn) \ | |
816 | : &nop_insn)) | |
df58fc94 RS |
817 | |
818 | /* The size of NOP_INSN in bytes. */ | |
833794fc MR |
819 | #define NOP_INSN_SIZE ((mips_opts.mips16 \ |
820 | || (mips_opts.micromips && !mips_opts.insn32)) \ | |
821 | ? 2 : 4) | |
252b5132 | 822 | |
252b5132 RH |
823 | /* If this is set, it points to a frag holding nop instructions which |
824 | were inserted before the start of a noreorder section. If those | |
825 | nops turn out to be unnecessary, the size of the frag can be | |
826 | decreased. */ | |
827 | static fragS *prev_nop_frag; | |
828 | ||
829 | /* The number of nop instructions we created in prev_nop_frag. */ | |
830 | static int prev_nop_frag_holds; | |
831 | ||
832 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 833 | prev_nop_frag. */ |
252b5132 RH |
834 | static int prev_nop_frag_required; |
835 | ||
836 | /* The number of instructions we've seen since prev_nop_frag. */ | |
837 | static int prev_nop_frag_since; | |
838 | ||
e8044f35 RS |
839 | /* Relocations against symbols are sometimes done in two parts, with a HI |
840 | relocation and a LO relocation. Each relocation has only 16 bits of | |
841 | space to store an addend. This means that in order for the linker to | |
842 | handle carries correctly, it must be able to locate both the HI and | |
843 | the LO relocation. This means that the relocations must appear in | |
844 | order in the relocation table. | |
252b5132 RH |
845 | |
846 | In order to implement this, we keep track of each unmatched HI | |
847 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 848 | corresponding LO relocation. */ |
252b5132 | 849 | |
e972090a NC |
850 | struct mips_hi_fixup |
851 | { | |
252b5132 RH |
852 | /* Next HI fixup. */ |
853 | struct mips_hi_fixup *next; | |
854 | /* This fixup. */ | |
855 | fixS *fixp; | |
856 | /* The section this fixup is in. */ | |
857 | segT seg; | |
858 | }; | |
859 | ||
860 | /* The list of unmatched HI relocs. */ | |
861 | ||
862 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
863 | ||
64bdfcaf RS |
864 | /* The frag containing the last explicit relocation operator. |
865 | Null if explicit relocations have not been used. */ | |
866 | ||
867 | static fragS *prev_reloc_op_frag; | |
868 | ||
252b5132 RH |
869 | /* Map mips16 register numbers to normal MIPS register numbers. */ |
870 | ||
e972090a NC |
871 | static const unsigned int mips16_to_32_reg_map[] = |
872 | { | |
252b5132 RH |
873 | 16, 17, 2, 3, 4, 5, 6, 7 |
874 | }; | |
60b63b72 | 875 | |
df58fc94 RS |
876 | /* Map microMIPS register numbers to normal MIPS register numbers. */ |
877 | ||
df58fc94 | 878 | #define micromips_to_32_reg_d_map mips16_to_32_reg_map |
df58fc94 RS |
879 | |
880 | /* The microMIPS registers with type h. */ | |
e76ff5ab | 881 | static const unsigned int micromips_to_32_reg_h_map1[] = |
df58fc94 RS |
882 | { |
883 | 5, 5, 6, 4, 4, 4, 4, 4 | |
884 | }; | |
e76ff5ab | 885 | static const unsigned int micromips_to_32_reg_h_map2[] = |
df58fc94 RS |
886 | { |
887 | 6, 7, 7, 21, 22, 5, 6, 7 | |
888 | }; | |
889 | ||
df58fc94 RS |
890 | /* The microMIPS registers with type m. */ |
891 | static const unsigned int micromips_to_32_reg_m_map[] = | |
892 | { | |
893 | 0, 17, 2, 3, 16, 18, 19, 20 | |
894 | }; | |
895 | ||
896 | #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map | |
897 | ||
71400594 RS |
898 | /* Classifies the kind of instructions we're interested in when |
899 | implementing -mfix-vr4120. */ | |
c67a084a NC |
900 | enum fix_vr4120_class |
901 | { | |
71400594 RS |
902 | FIX_VR4120_MACC, |
903 | FIX_VR4120_DMACC, | |
904 | FIX_VR4120_MULT, | |
905 | FIX_VR4120_DMULT, | |
906 | FIX_VR4120_DIV, | |
907 | FIX_VR4120_MTHILO, | |
908 | NUM_FIX_VR4120_CLASSES | |
909 | }; | |
910 | ||
c67a084a NC |
911 | /* ...likewise -mfix-loongson2f-jump. */ |
912 | static bfd_boolean mips_fix_loongson2f_jump; | |
913 | ||
914 | /* ...likewise -mfix-loongson2f-nop. */ | |
915 | static bfd_boolean mips_fix_loongson2f_nop; | |
916 | ||
917 | /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */ | |
918 | static bfd_boolean mips_fix_loongson2f; | |
919 | ||
71400594 RS |
920 | /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if |
921 | there must be at least one other instruction between an instruction | |
922 | of type X and an instruction of type Y. */ | |
923 | static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; | |
924 | ||
925 | /* True if -mfix-vr4120 is in force. */ | |
d766e8ec | 926 | static int mips_fix_vr4120; |
4a6a3df4 | 927 | |
7d8e00cf RS |
928 | /* ...likewise -mfix-vr4130. */ |
929 | static int mips_fix_vr4130; | |
930 | ||
6a32d874 CM |
931 | /* ...likewise -mfix-24k. */ |
932 | static int mips_fix_24k; | |
933 | ||
a8d14a88 CM |
934 | /* ...likewise -mfix-rm7000 */ |
935 | static int mips_fix_rm7000; | |
936 | ||
d954098f DD |
937 | /* ...likewise -mfix-cn63xxp1 */ |
938 | static bfd_boolean mips_fix_cn63xxp1; | |
939 | ||
4a6a3df4 AO |
940 | /* We don't relax branches by default, since this causes us to expand |
941 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
942 | fail to compute the offset before expanding the macro to the most | |
943 | efficient expansion. */ | |
944 | ||
945 | static int mips_relax_branch; | |
8b10b0b3 MR |
946 | |
947 | /* TRUE if checks are suppressed for invalid branches between ISA modes. | |
948 | Needed for broken assembly produced by some GCC versions and some | |
949 | sloppy code out there, where branches to data labels are present. */ | |
950 | static bfd_boolean mips_ignore_branch_isa; | |
252b5132 | 951 | \f |
4d7206a2 RS |
952 | /* The expansion of many macros depends on the type of symbol that |
953 | they refer to. For example, when generating position-dependent code, | |
954 | a macro that refers to a symbol may have two different expansions, | |
955 | one which uses GP-relative addresses and one which uses absolute | |
956 | addresses. When generating SVR4-style PIC, a macro may have | |
957 | different expansions for local and global symbols. | |
958 | ||
959 | We handle these situations by generating both sequences and putting | |
960 | them in variant frags. In position-dependent code, the first sequence | |
961 | will be the GP-relative one and the second sequence will be the | |
962 | absolute one. In SVR4 PIC, the first sequence will be for global | |
963 | symbols and the second will be for local symbols. | |
964 | ||
584892a6 RS |
965 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
966 | SECOND are the lengths of the two sequences in bytes. These fields | |
967 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
968 | the subtype has the following flags: | |
4d7206a2 | 969 | |
ce8ad872 MR |
970 | RELAX_PIC |
971 | Set if generating PIC code. | |
972 | ||
584892a6 RS |
973 | RELAX_USE_SECOND |
974 | Set if it has been decided that we should use the second | |
975 | sequence instead of the first. | |
976 | ||
977 | RELAX_SECOND_LONGER | |
978 | Set in the first variant frag if the macro's second implementation | |
979 | is longer than its first. This refers to the macro as a whole, | |
980 | not an individual relaxation. | |
981 | ||
982 | RELAX_NOMACRO | |
983 | Set in the first variant frag if the macro appeared in a .set nomacro | |
984 | block and if one alternative requires a warning but the other does not. | |
985 | ||
986 | RELAX_DELAY_SLOT | |
987 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
988 | delay slot. | |
4d7206a2 | 989 | |
df58fc94 RS |
990 | RELAX_DELAY_SLOT_16BIT |
991 | Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a | |
992 | 16-bit instruction. | |
993 | ||
994 | RELAX_DELAY_SLOT_SIZE_FIRST | |
995 | Like RELAX_DELAY_SLOT, but indicates that the first implementation of | |
996 | the macro is of the wrong size for the branch delay slot. | |
997 | ||
998 | RELAX_DELAY_SLOT_SIZE_SECOND | |
999 | Like RELAX_DELAY_SLOT, but indicates that the second implementation of | |
1000 | the macro is of the wrong size for the branch delay slot. | |
1001 | ||
4d7206a2 RS |
1002 | The frag's "opcode" points to the first fixup for relaxable code. |
1003 | ||
1004 | Relaxable macros are generated using a sequence such as: | |
1005 | ||
1006 | relax_start (SYMBOL); | |
1007 | ... generate first expansion ... | |
1008 | relax_switch (); | |
1009 | ... generate second expansion ... | |
1010 | relax_end (); | |
1011 | ||
1012 | The code and fixups for the unwanted alternative are discarded | |
1013 | by md_convert_frag. */ | |
ce8ad872 MR |
1014 | #define RELAX_ENCODE(FIRST, SECOND, PIC) \ |
1015 | (((FIRST) << 8) | (SECOND) | ((PIC) ? 0x10000 : 0)) | |
4d7206a2 | 1016 | |
584892a6 RS |
1017 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
1018 | #define RELAX_SECOND(X) ((X) & 0xff) | |
ce8ad872 MR |
1019 | #define RELAX_PIC(X) (((X) & 0x10000) != 0) |
1020 | #define RELAX_USE_SECOND 0x20000 | |
1021 | #define RELAX_SECOND_LONGER 0x40000 | |
1022 | #define RELAX_NOMACRO 0x80000 | |
1023 | #define RELAX_DELAY_SLOT 0x100000 | |
1024 | #define RELAX_DELAY_SLOT_16BIT 0x200000 | |
1025 | #define RELAX_DELAY_SLOT_SIZE_FIRST 0x400000 | |
1026 | #define RELAX_DELAY_SLOT_SIZE_SECOND 0x800000 | |
252b5132 | 1027 | |
4a6a3df4 AO |
1028 | /* Branch without likely bit. If label is out of range, we turn: |
1029 | ||
134c0c8b | 1030 | beq reg1, reg2, label |
4a6a3df4 AO |
1031 | delay slot |
1032 | ||
1033 | into | |
1034 | ||
1035 | bne reg1, reg2, 0f | |
1036 | nop | |
1037 | j label | |
1038 | 0: delay slot | |
1039 | ||
1040 | with the following opcode replacements: | |
1041 | ||
1042 | beq <-> bne | |
1043 | blez <-> bgtz | |
1044 | bltz <-> bgez | |
1045 | bc1f <-> bc1t | |
1046 | ||
1047 | bltzal <-> bgezal (with jal label instead of j label) | |
1048 | ||
1049 | Even though keeping the delay slot instruction in the delay slot of | |
1050 | the branch would be more efficient, it would be very tricky to do | |
1051 | correctly, because we'd have to introduce a variable frag *after* | |
1052 | the delay slot instruction, and expand that instead. Let's do it | |
1053 | the easy way for now, even if the branch-not-taken case now costs | |
1054 | one additional instruction. Out-of-range branches are not supposed | |
1055 | to be common, anyway. | |
1056 | ||
1057 | Branch likely. If label is out of range, we turn: | |
1058 | ||
1059 | beql reg1, reg2, label | |
1060 | delay slot (annulled if branch not taken) | |
1061 | ||
1062 | into | |
1063 | ||
1064 | beql reg1, reg2, 1f | |
1065 | nop | |
1066 | beql $0, $0, 2f | |
1067 | nop | |
1068 | 1: j[al] label | |
1069 | delay slot (executed only if branch taken) | |
1070 | 2: | |
1071 | ||
1072 | It would be possible to generate a shorter sequence by losing the | |
1073 | likely bit, generating something like: | |
b34976b6 | 1074 | |
4a6a3df4 AO |
1075 | bne reg1, reg2, 0f |
1076 | nop | |
1077 | j[al] label | |
1078 | delay slot (executed only if branch taken) | |
1079 | 0: | |
1080 | ||
1081 | beql -> bne | |
1082 | bnel -> beq | |
1083 | blezl -> bgtz | |
1084 | bgtzl -> blez | |
1085 | bltzl -> bgez | |
1086 | bgezl -> bltz | |
1087 | bc1fl -> bc1t | |
1088 | bc1tl -> bc1f | |
1089 | ||
1090 | bltzall -> bgezal (with jal label instead of j label) | |
1091 | bgezall -> bltzal (ditto) | |
1092 | ||
1093 | ||
1094 | but it's not clear that it would actually improve performance. */ | |
ce8ad872 MR |
1095 | #define RELAX_BRANCH_ENCODE(at, pic, \ |
1096 | uncond, likely, link, toofar) \ | |
66b3e8da MR |
1097 | ((relax_substateT) \ |
1098 | (0xc0000000 \ | |
1099 | | ((at) & 0x1f) \ | |
ce8ad872 MR |
1100 | | ((pic) ? 0x20 : 0) \ |
1101 | | ((toofar) ? 0x40 : 0) \ | |
1102 | | ((link) ? 0x80 : 0) \ | |
1103 | | ((likely) ? 0x100 : 0) \ | |
1104 | | ((uncond) ? 0x200 : 0))) | |
4a6a3df4 | 1105 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
ce8ad872 MR |
1106 | #define RELAX_BRANCH_UNCOND(i) (((i) & 0x200) != 0) |
1107 | #define RELAX_BRANCH_LIKELY(i) (((i) & 0x100) != 0) | |
1108 | #define RELAX_BRANCH_LINK(i) (((i) & 0x80) != 0) | |
1109 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x40) != 0) | |
1110 | #define RELAX_BRANCH_PIC(i) (((i) & 0x20) != 0) | |
66b3e8da | 1111 | #define RELAX_BRANCH_AT(i) ((i) & 0x1f) |
4a6a3df4 | 1112 | |
252b5132 RH |
1113 | /* For mips16 code, we use an entirely different form of relaxation. |
1114 | mips16 supports two versions of most instructions which take | |
1115 | immediate values: a small one which takes some small value, and a | |
1116 | larger one which takes a 16 bit value. Since branches also follow | |
1117 | this pattern, relaxing these values is required. | |
1118 | ||
1119 | We can assemble both mips16 and normal MIPS code in a single | |
1120 | object. Therefore, we need to support this type of relaxation at | |
1121 | the same time that we support the relaxation described above. We | |
1122 | use the high bit of the subtype field to distinguish these cases. | |
1123 | ||
1124 | The information we store for this type of relaxation is the | |
1125 | argument code found in the opcode file for this relocation, whether | |
1126 | the user explicitly requested a small or extended form, and whether | |
1127 | the relocation is in a jump or jal delay slot. That tells us the | |
1128 | size of the value, and how it should be stored. We also store | |
1129 | whether the fragment is considered to be extended or not. We also | |
1130 | store whether this is known to be a branch to a different section, | |
1131 | whether we have tried to relax this frag yet, and whether we have | |
1132 | ever extended a PC relative fragment because of a shift count. */ | |
25499ac7 | 1133 | #define RELAX_MIPS16_ENCODE(type, e2, pic, sym32, nomacro, \ |
8507b6e7 MR |
1134 | small, ext, \ |
1135 | dslot, jal_dslot) \ | |
252b5132 RH |
1136 | (0x80000000 \ |
1137 | | ((type) & 0xff) \ | |
25499ac7 MR |
1138 | | ((e2) ? 0x100 : 0) \ |
1139 | | ((pic) ? 0x200 : 0) \ | |
1140 | | ((sym32) ? 0x400 : 0) \ | |
1141 | | ((nomacro) ? 0x800 : 0) \ | |
1142 | | ((small) ? 0x1000 : 0) \ | |
1143 | | ((ext) ? 0x2000 : 0) \ | |
1144 | | ((dslot) ? 0x4000 : 0) \ | |
1145 | | ((jal_dslot) ? 0x8000 : 0)) | |
8507b6e7 | 1146 | |
4a6a3df4 | 1147 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 | 1148 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
25499ac7 MR |
1149 | #define RELAX_MIPS16_E2(i) (((i) & 0x100) != 0) |
1150 | #define RELAX_MIPS16_PIC(i) (((i) & 0x200) != 0) | |
1151 | #define RELAX_MIPS16_SYM32(i) (((i) & 0x400) != 0) | |
1152 | #define RELAX_MIPS16_NOMACRO(i) (((i) & 0x800) != 0) | |
1153 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x1000) != 0) | |
1154 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x2000) != 0) | |
1155 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x4000) != 0) | |
1156 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x8000) != 0) | |
1157 | ||
1158 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x10000) != 0) | |
1159 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x10000) | |
1160 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) & ~0x10000) | |
1161 | #define RELAX_MIPS16_ALWAYS_EXTENDED(i) (((i) & 0x20000) != 0) | |
1162 | #define RELAX_MIPS16_MARK_ALWAYS_EXTENDED(i) ((i) | 0x20000) | |
1163 | #define RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED(i) ((i) & ~0x20000) | |
1164 | #define RELAX_MIPS16_MACRO(i) (((i) & 0x40000) != 0) | |
1165 | #define RELAX_MIPS16_MARK_MACRO(i) ((i) | 0x40000) | |
1166 | #define RELAX_MIPS16_CLEAR_MACRO(i) ((i) & ~0x40000) | |
885add95 | 1167 | |
df58fc94 RS |
1168 | /* For microMIPS code, we use relaxation similar to one we use for |
1169 | MIPS16 code. Some instructions that take immediate values support | |
1170 | two encodings: a small one which takes some small value, and a | |
1171 | larger one which takes a 16 bit value. As some branches also follow | |
1172 | this pattern, relaxing these values is required. | |
1173 | ||
1174 | We can assemble both microMIPS and normal MIPS code in a single | |
1175 | object. Therefore, we need to support this type of relaxation at | |
1176 | the same time that we support the relaxation described above. We | |
1177 | use one of the high bits of the subtype field to distinguish these | |
1178 | cases. | |
1179 | ||
1180 | The information we store for this type of relaxation is the argument | |
1181 | code found in the opcode file for this relocation, the register | |
8484fb75 MR |
1182 | selected as the assembler temporary, whether in the 32-bit |
1183 | instruction mode, whether the branch is unconditional, whether it is | |
7bd374a4 MR |
1184 | compact, whether there is no delay-slot instruction available to fill |
1185 | in, whether it stores the link address implicitly in $ra, whether | |
1186 | relaxation of out-of-range 32-bit branches to a sequence of | |
8484fb75 MR |
1187 | instructions is enabled, and whether the displacement of a branch is |
1188 | too large to fit as an immediate argument of a 16-bit and a 32-bit | |
1189 | branch, respectively. */ | |
ce8ad872 | 1190 | #define RELAX_MICROMIPS_ENCODE(type, at, insn32, pic, \ |
7bd374a4 | 1191 | uncond, compact, link, nods, \ |
40209cad MR |
1192 | relax32, toofar16, toofar32) \ |
1193 | (0x40000000 \ | |
1194 | | ((type) & 0xff) \ | |
1195 | | (((at) & 0x1f) << 8) \ | |
8484fb75 | 1196 | | ((insn32) ? 0x2000 : 0) \ |
ce8ad872 MR |
1197 | | ((pic) ? 0x4000 : 0) \ |
1198 | | ((uncond) ? 0x8000 : 0) \ | |
1199 | | ((compact) ? 0x10000 : 0) \ | |
1200 | | ((link) ? 0x20000 : 0) \ | |
1201 | | ((nods) ? 0x40000 : 0) \ | |
1202 | | ((relax32) ? 0x80000 : 0) \ | |
1203 | | ((toofar16) ? 0x100000 : 0) \ | |
1204 | | ((toofar32) ? 0x200000 : 0)) | |
df58fc94 RS |
1205 | #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000) |
1206 | #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff) | |
1207 | #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f) | |
8484fb75 | 1208 | #define RELAX_MICROMIPS_INSN32(i) (((i) & 0x2000) != 0) |
ce8ad872 MR |
1209 | #define RELAX_MICROMIPS_PIC(i) (((i) & 0x4000) != 0) |
1210 | #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x8000) != 0) | |
1211 | #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x10000) != 0) | |
1212 | #define RELAX_MICROMIPS_LINK(i) (((i) & 0x20000) != 0) | |
1213 | #define RELAX_MICROMIPS_NODS(i) (((i) & 0x40000) != 0) | |
1214 | #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x80000) != 0) | |
1215 | ||
1216 | #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x100000) != 0) | |
1217 | #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x100000) | |
1218 | #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x100000) | |
1219 | #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x200000) != 0) | |
1220 | #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x200000) | |
1221 | #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x200000) | |
df58fc94 | 1222 | |
43c0598f RS |
1223 | /* Sign-extend 16-bit value X. */ |
1224 | #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000) | |
1225 | ||
885add95 CD |
1226 | /* Is the given value a sign-extended 32-bit value? */ |
1227 | #define IS_SEXT_32BIT_NUM(x) \ | |
1228 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
1229 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
1230 | ||
1231 | /* Is the given value a sign-extended 16-bit value? */ | |
1232 | #define IS_SEXT_16BIT_NUM(x) \ | |
1233 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
1234 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
1235 | ||
df58fc94 RS |
1236 | /* Is the given value a sign-extended 12-bit value? */ |
1237 | #define IS_SEXT_12BIT_NUM(x) \ | |
1238 | (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x)) | |
1239 | ||
7f3c4072 CM |
1240 | /* Is the given value a sign-extended 9-bit value? */ |
1241 | #define IS_SEXT_9BIT_NUM(x) \ | |
1242 | (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x)) | |
1243 | ||
2051e8c4 MR |
1244 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ |
1245 | #define IS_ZEXT_32BIT_NUM(x) \ | |
1246 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
1247 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
1248 | ||
bf12938e RS |
1249 | /* Extract bits MASK << SHIFT from STRUCT and shift them right |
1250 | SHIFT places. */ | |
1251 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
1252 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
1253 | ||
bf12938e | 1254 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ |
df58fc94 RS |
1255 | #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \ |
1256 | (!(MICROMIPS) \ | |
1257 | ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \ | |
1258 | : EXTRACT_BITS ((INSN).insn_opcode, \ | |
1259 | MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD)) | |
bf12938e RS |
1260 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ |
1261 | EXTRACT_BITS ((INSN).insn_opcode, \ | |
1262 | MIPS16OP_MASK_##FIELD, \ | |
1263 | MIPS16OP_SH_##FIELD) | |
5c04167a RS |
1264 | |
1265 | /* The MIPS16 EXTEND opcode, shifted left 16 places. */ | |
1266 | #define MIPS16_EXTEND (0xf000U << 16) | |
4d7206a2 | 1267 | \f |
df58fc94 RS |
1268 | /* Whether or not we are emitting a branch-likely macro. */ |
1269 | static bfd_boolean emit_branch_likely_macro = FALSE; | |
1270 | ||
4d7206a2 RS |
1271 | /* Global variables used when generating relaxable macros. See the |
1272 | comment above RELAX_ENCODE for more details about how relaxation | |
1273 | is used. */ | |
1274 | static struct { | |
1275 | /* 0 if we're not emitting a relaxable macro. | |
1276 | 1 if we're emitting the first of the two relaxation alternatives. | |
1277 | 2 if we're emitting the second alternative. */ | |
1278 | int sequence; | |
1279 | ||
1280 | /* The first relaxable fixup in the current frag. (In other words, | |
1281 | the first fixup that refers to relaxable code.) */ | |
1282 | fixS *first_fixup; | |
1283 | ||
1284 | /* sizes[0] says how many bytes of the first alternative are stored in | |
1285 | the current frag. Likewise sizes[1] for the second alternative. */ | |
1286 | unsigned int sizes[2]; | |
1287 | ||
1288 | /* The symbol on which the choice of sequence depends. */ | |
1289 | symbolS *symbol; | |
1290 | } mips_relax; | |
252b5132 | 1291 | \f |
584892a6 RS |
1292 | /* Global variables used to decide whether a macro needs a warning. */ |
1293 | static struct { | |
1294 | /* True if the macro is in a branch delay slot. */ | |
1295 | bfd_boolean delay_slot_p; | |
1296 | ||
df58fc94 RS |
1297 | /* Set to the length in bytes required if the macro is in a delay slot |
1298 | that requires a specific length of instruction, otherwise zero. */ | |
1299 | unsigned int delay_slot_length; | |
1300 | ||
584892a6 RS |
1301 | /* For relaxable macros, sizes[0] is the length of the first alternative |
1302 | in bytes and sizes[1] is the length of the second alternative. | |
1303 | For non-relaxable macros, both elements give the length of the | |
1304 | macro in bytes. */ | |
1305 | unsigned int sizes[2]; | |
1306 | ||
df58fc94 RS |
1307 | /* For relaxable macros, first_insn_sizes[0] is the length of the first |
1308 | instruction of the first alternative in bytes and first_insn_sizes[1] | |
1309 | is the length of the first instruction of the second alternative. | |
1310 | For non-relaxable macros, both elements give the length of the first | |
1311 | instruction in bytes. | |
1312 | ||
1313 | Set to zero if we haven't yet seen the first instruction. */ | |
1314 | unsigned int first_insn_sizes[2]; | |
1315 | ||
1316 | /* For relaxable macros, insns[0] is the number of instructions for the | |
1317 | first alternative and insns[1] is the number of instructions for the | |
1318 | second alternative. | |
1319 | ||
1320 | For non-relaxable macros, both elements give the number of | |
1321 | instructions for the macro. */ | |
1322 | unsigned int insns[2]; | |
1323 | ||
584892a6 RS |
1324 | /* The first variant frag for this macro. */ |
1325 | fragS *first_frag; | |
1326 | } mips_macro_warning; | |
1327 | \f | |
252b5132 RH |
1328 | /* Prototypes for static functions. */ |
1329 | ||
252b5132 RH |
1330 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; |
1331 | ||
b34976b6 | 1332 | static void append_insn |
df58fc94 RS |
1333 | (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *, |
1334 | bfd_boolean expansionp); | |
7d10b47d | 1335 | static void mips_no_prev_insn (void); |
c67a084a | 1336 | static void macro_build (expressionS *, const char *, const char *, ...); |
b34976b6 | 1337 | static void mips16_macro_build |
03ea81db | 1338 | (expressionS *, const char *, const char *, va_list *); |
67c0d1eb | 1339 | static void load_register (int, expressionS *, int); |
584892a6 RS |
1340 | static void macro_start (void); |
1341 | static void macro_end (void); | |
833794fc | 1342 | static void macro (struct mips_cl_insn *ip, char *str); |
17a2f251 | 1343 | static void mips16_macro (struct mips_cl_insn * ip); |
17a2f251 TS |
1344 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
1345 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
25499ac7 | 1346 | static unsigned long mips16_immed_extend (offsetT, unsigned int); |
b34976b6 | 1347 | static void mips16_immed |
3b4dbbbf | 1348 | (const char *, unsigned int, int, bfd_reloc_code_real_type, offsetT, |
43c0598f | 1349 | unsigned int, unsigned long *); |
5e0116d5 | 1350 | static size_t my_getSmallExpression |
17a2f251 TS |
1351 | (expressionS *, bfd_reloc_code_real_type *, char *); |
1352 | static void my_getExpression (expressionS *, char *); | |
1353 | static void s_align (int); | |
1354 | static void s_change_sec (int); | |
1355 | static void s_change_section (int); | |
1356 | static void s_cons (int); | |
1357 | static void s_float_cons (int); | |
1358 | static void s_mips_globl (int); | |
1359 | static void s_option (int); | |
1360 | static void s_mipsset (int); | |
1361 | static void s_abicalls (int); | |
1362 | static void s_cpload (int); | |
1363 | static void s_cpsetup (int); | |
1364 | static void s_cplocal (int); | |
1365 | static void s_cprestore (int); | |
1366 | static void s_cpreturn (int); | |
741d6ea8 JM |
1367 | static void s_dtprelword (int); |
1368 | static void s_dtpreldword (int); | |
d0f13682 CLT |
1369 | static void s_tprelword (int); |
1370 | static void s_tpreldword (int); | |
17a2f251 TS |
1371 | static void s_gpvalue (int); |
1372 | static void s_gpword (int); | |
1373 | static void s_gpdword (int); | |
a3f278e2 | 1374 | static void s_ehword (int); |
17a2f251 TS |
1375 | static void s_cpadd (int); |
1376 | static void s_insn (int); | |
ba92f887 | 1377 | static void s_nan (int); |
919731af | 1378 | static void s_module (int); |
17a2f251 TS |
1379 | static void s_mips_ent (int); |
1380 | static void s_mips_end (int); | |
1381 | static void s_mips_frame (int); | |
1382 | static void s_mips_mask (int reg_type); | |
1383 | static void s_mips_stab (int); | |
1384 | static void s_mips_weakext (int); | |
1385 | static void s_mips_file (int); | |
1386 | static void s_mips_loc (int); | |
9e009953 | 1387 | static bfd_boolean pic_need_relax (symbolS *); |
4a6a3df4 | 1388 | static int relaxed_branch_length (fragS *, asection *, int); |
df58fc94 RS |
1389 | static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int); |
1390 | static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int); | |
919731af | 1391 | static void file_mips_check_options (void); |
e7af610e NC |
1392 | |
1393 | /* Table and functions used to map between CPU/ISA names, and | |
1394 | ISA levels, and CPU numbers. */ | |
1395 | ||
e972090a NC |
1396 | struct mips_cpu_info |
1397 | { | |
e7af610e | 1398 | const char *name; /* CPU or ISA name. */ |
d16afab6 RS |
1399 | int flags; /* MIPS_CPU_* flags. */ |
1400 | int ase; /* Set of ASEs implemented by the CPU. */ | |
e7af610e NC |
1401 | int isa; /* ISA level. */ |
1402 | int cpu; /* CPU number (default CPU if ISA). */ | |
1403 | }; | |
1404 | ||
ad3fea08 | 1405 | #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ |
ad3fea08 | 1406 | |
17a2f251 TS |
1407 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
1408 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
1409 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 | 1410 | \f |
c31f3936 RS |
1411 | /* Command-line options. */ |
1412 | const char *md_shortopts = "O::g::G:"; | |
1413 | ||
1414 | enum options | |
1415 | { | |
1416 | OPTION_MARCH = OPTION_MD_BASE, | |
1417 | OPTION_MTUNE, | |
1418 | OPTION_MIPS1, | |
1419 | OPTION_MIPS2, | |
1420 | OPTION_MIPS3, | |
1421 | OPTION_MIPS4, | |
1422 | OPTION_MIPS5, | |
1423 | OPTION_MIPS32, | |
1424 | OPTION_MIPS64, | |
1425 | OPTION_MIPS32R2, | |
ae52f483 AB |
1426 | OPTION_MIPS32R3, |
1427 | OPTION_MIPS32R5, | |
7361da2c | 1428 | OPTION_MIPS32R6, |
c31f3936 | 1429 | OPTION_MIPS64R2, |
ae52f483 AB |
1430 | OPTION_MIPS64R3, |
1431 | OPTION_MIPS64R5, | |
7361da2c | 1432 | OPTION_MIPS64R6, |
c31f3936 RS |
1433 | OPTION_MIPS16, |
1434 | OPTION_NO_MIPS16, | |
1435 | OPTION_MIPS3D, | |
1436 | OPTION_NO_MIPS3D, | |
1437 | OPTION_MDMX, | |
1438 | OPTION_NO_MDMX, | |
1439 | OPTION_DSP, | |
1440 | OPTION_NO_DSP, | |
1441 | OPTION_MT, | |
1442 | OPTION_NO_MT, | |
1443 | OPTION_VIRT, | |
1444 | OPTION_NO_VIRT, | |
56d438b1 CF |
1445 | OPTION_MSA, |
1446 | OPTION_NO_MSA, | |
c31f3936 RS |
1447 | OPTION_SMARTMIPS, |
1448 | OPTION_NO_SMARTMIPS, | |
1449 | OPTION_DSPR2, | |
1450 | OPTION_NO_DSPR2, | |
8f4f9071 MF |
1451 | OPTION_DSPR3, |
1452 | OPTION_NO_DSPR3, | |
c31f3936 RS |
1453 | OPTION_EVA, |
1454 | OPTION_NO_EVA, | |
7d64c587 AB |
1455 | OPTION_XPA, |
1456 | OPTION_NO_XPA, | |
c31f3936 RS |
1457 | OPTION_MICROMIPS, |
1458 | OPTION_NO_MICROMIPS, | |
1459 | OPTION_MCU, | |
1460 | OPTION_NO_MCU, | |
25499ac7 MR |
1461 | OPTION_MIPS16E2, |
1462 | OPTION_NO_MIPS16E2, | |
730c3174 SE |
1463 | OPTION_CRC, |
1464 | OPTION_NO_CRC, | |
c31f3936 RS |
1465 | OPTION_M4650, |
1466 | OPTION_NO_M4650, | |
1467 | OPTION_M4010, | |
1468 | OPTION_NO_M4010, | |
1469 | OPTION_M4100, | |
1470 | OPTION_NO_M4100, | |
1471 | OPTION_M3900, | |
1472 | OPTION_NO_M3900, | |
1473 | OPTION_M7000_HILO_FIX, | |
1474 | OPTION_MNO_7000_HILO_FIX, | |
1475 | OPTION_FIX_24K, | |
1476 | OPTION_NO_FIX_24K, | |
a8d14a88 CM |
1477 | OPTION_FIX_RM7000, |
1478 | OPTION_NO_FIX_RM7000, | |
c31f3936 RS |
1479 | OPTION_FIX_LOONGSON2F_JUMP, |
1480 | OPTION_NO_FIX_LOONGSON2F_JUMP, | |
1481 | OPTION_FIX_LOONGSON2F_NOP, | |
1482 | OPTION_NO_FIX_LOONGSON2F_NOP, | |
1483 | OPTION_FIX_VR4120, | |
1484 | OPTION_NO_FIX_VR4120, | |
1485 | OPTION_FIX_VR4130, | |
1486 | OPTION_NO_FIX_VR4130, | |
1487 | OPTION_FIX_CN63XXP1, | |
1488 | OPTION_NO_FIX_CN63XXP1, | |
1489 | OPTION_TRAP, | |
1490 | OPTION_BREAK, | |
1491 | OPTION_EB, | |
1492 | OPTION_EL, | |
1493 | OPTION_FP32, | |
1494 | OPTION_GP32, | |
1495 | OPTION_CONSTRUCT_FLOATS, | |
1496 | OPTION_NO_CONSTRUCT_FLOATS, | |
1497 | OPTION_FP64, | |
351cdf24 | 1498 | OPTION_FPXX, |
c31f3936 RS |
1499 | OPTION_GP64, |
1500 | OPTION_RELAX_BRANCH, | |
1501 | OPTION_NO_RELAX_BRANCH, | |
8b10b0b3 MR |
1502 | OPTION_IGNORE_BRANCH_ISA, |
1503 | OPTION_NO_IGNORE_BRANCH_ISA, | |
833794fc MR |
1504 | OPTION_INSN32, |
1505 | OPTION_NO_INSN32, | |
c31f3936 RS |
1506 | OPTION_MSHARED, |
1507 | OPTION_MNO_SHARED, | |
1508 | OPTION_MSYM32, | |
1509 | OPTION_MNO_SYM32, | |
1510 | OPTION_SOFT_FLOAT, | |
1511 | OPTION_HARD_FLOAT, | |
1512 | OPTION_SINGLE_FLOAT, | |
1513 | OPTION_DOUBLE_FLOAT, | |
1514 | OPTION_32, | |
c31f3936 RS |
1515 | OPTION_CALL_SHARED, |
1516 | OPTION_CALL_NONPIC, | |
1517 | OPTION_NON_SHARED, | |
1518 | OPTION_XGOT, | |
1519 | OPTION_MABI, | |
1520 | OPTION_N32, | |
1521 | OPTION_64, | |
1522 | OPTION_MDEBUG, | |
1523 | OPTION_NO_MDEBUG, | |
1524 | OPTION_PDR, | |
1525 | OPTION_NO_PDR, | |
1526 | OPTION_MVXWORKS_PIC, | |
ba92f887 | 1527 | OPTION_NAN, |
351cdf24 MF |
1528 | OPTION_ODD_SPREG, |
1529 | OPTION_NO_ODD_SPREG, | |
6f20c942 FS |
1530 | OPTION_GINV, |
1531 | OPTION_NO_GINV, | |
8095d2f7 CX |
1532 | OPTION_LOONGSON_MMI, |
1533 | OPTION_NO_LOONGSON_MMI, | |
716c08de CX |
1534 | OPTION_LOONGSON_CAM, |
1535 | OPTION_NO_LOONGSON_CAM, | |
c31f3936 RS |
1536 | OPTION_END_OF_ENUM |
1537 | }; | |
1538 | ||
1539 | struct option md_longopts[] = | |
1540 | { | |
1541 | /* Options which specify architecture. */ | |
1542 | {"march", required_argument, NULL, OPTION_MARCH}, | |
1543 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
1544 | {"mips0", no_argument, NULL, OPTION_MIPS1}, | |
1545 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
1546 | {"mips2", no_argument, NULL, OPTION_MIPS2}, | |
1547 | {"mips3", no_argument, NULL, OPTION_MIPS3}, | |
1548 | {"mips4", no_argument, NULL, OPTION_MIPS4}, | |
1549 | {"mips5", no_argument, NULL, OPTION_MIPS5}, | |
1550 | {"mips32", no_argument, NULL, OPTION_MIPS32}, | |
1551 | {"mips64", no_argument, NULL, OPTION_MIPS64}, | |
1552 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, | |
ae52f483 AB |
1553 | {"mips32r3", no_argument, NULL, OPTION_MIPS32R3}, |
1554 | {"mips32r5", no_argument, NULL, OPTION_MIPS32R5}, | |
7361da2c | 1555 | {"mips32r6", no_argument, NULL, OPTION_MIPS32R6}, |
c31f3936 | 1556 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, |
ae52f483 AB |
1557 | {"mips64r3", no_argument, NULL, OPTION_MIPS64R3}, |
1558 | {"mips64r5", no_argument, NULL, OPTION_MIPS64R5}, | |
7361da2c | 1559 | {"mips64r6", no_argument, NULL, OPTION_MIPS64R6}, |
c31f3936 RS |
1560 | |
1561 | /* Options which specify Application Specific Extensions (ASEs). */ | |
1562 | {"mips16", no_argument, NULL, OPTION_MIPS16}, | |
1563 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, | |
1564 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, | |
1565 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, | |
1566 | {"mdmx", no_argument, NULL, OPTION_MDMX}, | |
1567 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, | |
1568 | {"mdsp", no_argument, NULL, OPTION_DSP}, | |
1569 | {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, | |
1570 | {"mmt", no_argument, NULL, OPTION_MT}, | |
1571 | {"mno-mt", no_argument, NULL, OPTION_NO_MT}, | |
1572 | {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS}, | |
1573 | {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS}, | |
1574 | {"mdspr2", no_argument, NULL, OPTION_DSPR2}, | |
1575 | {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2}, | |
8f4f9071 MF |
1576 | {"mdspr3", no_argument, NULL, OPTION_DSPR3}, |
1577 | {"mno-dspr3", no_argument, NULL, OPTION_NO_DSPR3}, | |
c31f3936 RS |
1578 | {"meva", no_argument, NULL, OPTION_EVA}, |
1579 | {"mno-eva", no_argument, NULL, OPTION_NO_EVA}, | |
1580 | {"mmicromips", no_argument, NULL, OPTION_MICROMIPS}, | |
1581 | {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS}, | |
1582 | {"mmcu", no_argument, NULL, OPTION_MCU}, | |
1583 | {"mno-mcu", no_argument, NULL, OPTION_NO_MCU}, | |
1584 | {"mvirt", no_argument, NULL, OPTION_VIRT}, | |
1585 | {"mno-virt", no_argument, NULL, OPTION_NO_VIRT}, | |
56d438b1 CF |
1586 | {"mmsa", no_argument, NULL, OPTION_MSA}, |
1587 | {"mno-msa", no_argument, NULL, OPTION_NO_MSA}, | |
7d64c587 AB |
1588 | {"mxpa", no_argument, NULL, OPTION_XPA}, |
1589 | {"mno-xpa", no_argument, NULL, OPTION_NO_XPA}, | |
25499ac7 MR |
1590 | {"mmips16e2", no_argument, NULL, OPTION_MIPS16E2}, |
1591 | {"mno-mips16e2", no_argument, NULL, OPTION_NO_MIPS16E2}, | |
730c3174 SE |
1592 | {"mcrc", no_argument, NULL, OPTION_CRC}, |
1593 | {"mno-crc", no_argument, NULL, OPTION_NO_CRC}, | |
6f20c942 FS |
1594 | {"mginv", no_argument, NULL, OPTION_GINV}, |
1595 | {"mno-ginv", no_argument, NULL, OPTION_NO_GINV}, | |
8095d2f7 CX |
1596 | {"mloongson-mmi", no_argument, NULL, OPTION_LOONGSON_MMI}, |
1597 | {"mno-loongson-mmi", no_argument, NULL, OPTION_NO_LOONGSON_MMI}, | |
716c08de CX |
1598 | {"mloongson-cam", no_argument, NULL, OPTION_LOONGSON_CAM}, |
1599 | {"mno-loongson-cam", no_argument, NULL, OPTION_NO_LOONGSON_CAM}, | |
c31f3936 RS |
1600 | |
1601 | /* Old-style architecture options. Don't add more of these. */ | |
1602 | {"m4650", no_argument, NULL, OPTION_M4650}, | |
1603 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, | |
1604 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
1605 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
1606 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
1607 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
1608 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
1609 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
1610 | ||
1611 | /* Options which enable bug fixes. */ | |
1612 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, | |
1613 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
1614 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
1615 | {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP}, | |
1616 | {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP}, | |
1617 | {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP}, | |
1618 | {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP}, | |
1619 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, | |
1620 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
1621 | {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, | |
1622 | {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, | |
1623 | {"mfix-24k", no_argument, NULL, OPTION_FIX_24K}, | |
1624 | {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K}, | |
a8d14a88 CM |
1625 | {"mfix-rm7000", no_argument, NULL, OPTION_FIX_RM7000}, |
1626 | {"mno-fix-rm7000", no_argument, NULL, OPTION_NO_FIX_RM7000}, | |
c31f3936 RS |
1627 | {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1}, |
1628 | {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1}, | |
1629 | ||
1630 | /* Miscellaneous options. */ | |
1631 | {"trap", no_argument, NULL, OPTION_TRAP}, | |
1632 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
1633 | {"break", no_argument, NULL, OPTION_BREAK}, | |
1634 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
1635 | {"EB", no_argument, NULL, OPTION_EB}, | |
1636 | {"EL", no_argument, NULL, OPTION_EL}, | |
1637 | {"mfp32", no_argument, NULL, OPTION_FP32}, | |
1638 | {"mgp32", no_argument, NULL, OPTION_GP32}, | |
1639 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, | |
1640 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, | |
1641 | {"mfp64", no_argument, NULL, OPTION_FP64}, | |
351cdf24 | 1642 | {"mfpxx", no_argument, NULL, OPTION_FPXX}, |
c31f3936 RS |
1643 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
1644 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, | |
1645 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
8b10b0b3 MR |
1646 | {"mignore-branch-isa", no_argument, NULL, OPTION_IGNORE_BRANCH_ISA}, |
1647 | {"mno-ignore-branch-isa", no_argument, NULL, OPTION_NO_IGNORE_BRANCH_ISA}, | |
833794fc MR |
1648 | {"minsn32", no_argument, NULL, OPTION_INSN32}, |
1649 | {"mno-insn32", no_argument, NULL, OPTION_NO_INSN32}, | |
c31f3936 RS |
1650 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
1651 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
1652 | {"msym32", no_argument, NULL, OPTION_MSYM32}, | |
1653 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, | |
1654 | {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT}, | |
1655 | {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT}, | |
1656 | {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT}, | |
1657 | {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT}, | |
351cdf24 MF |
1658 | {"modd-spreg", no_argument, NULL, OPTION_ODD_SPREG}, |
1659 | {"mno-odd-spreg", no_argument, NULL, OPTION_NO_ODD_SPREG}, | |
c31f3936 RS |
1660 | |
1661 | /* Strictly speaking this next option is ELF specific, | |
1662 | but we allow it for other ports as well in order to | |
1663 | make testing easier. */ | |
1664 | {"32", no_argument, NULL, OPTION_32}, | |
1665 | ||
1666 | /* ELF-specific options. */ | |
c31f3936 RS |
1667 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
1668 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
1669 | {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC}, | |
1670 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, | |
1671 | {"xgot", no_argument, NULL, OPTION_XGOT}, | |
1672 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
1673 | {"n32", no_argument, NULL, OPTION_N32}, | |
1674 | {"64", no_argument, NULL, OPTION_64}, | |
1675 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, | |
1676 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, | |
1677 | {"mpdr", no_argument, NULL, OPTION_PDR}, | |
1678 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, | |
1679 | {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, | |
ba92f887 | 1680 | {"mnan", required_argument, NULL, OPTION_NAN}, |
c31f3936 RS |
1681 | |
1682 | {NULL, no_argument, NULL, 0} | |
1683 | }; | |
1684 | size_t md_longopts_size = sizeof (md_longopts); | |
1685 | \f | |
c6278170 RS |
1686 | /* Information about either an Application Specific Extension or an |
1687 | optional architecture feature that, for simplicity, we treat in the | |
1688 | same way as an ASE. */ | |
1689 | struct mips_ase | |
1690 | { | |
1691 | /* The name of the ASE, used in both the command-line and .set options. */ | |
1692 | const char *name; | |
1693 | ||
1694 | /* The associated ASE_* flags. If the ASE is available on both 32-bit | |
1695 | and 64-bit architectures, the flags here refer to the subset that | |
1696 | is available on both. */ | |
1697 | unsigned int flags; | |
1698 | ||
1699 | /* The ASE_* flag used for instructions that are available on 64-bit | |
1700 | architectures but that are not included in FLAGS. */ | |
1701 | unsigned int flags64; | |
1702 | ||
1703 | /* The command-line options that turn the ASE on and off. */ | |
1704 | int option_on; | |
1705 | int option_off; | |
1706 | ||
1707 | /* The minimum required architecture revisions for MIPS32, MIPS64, | |
1708 | microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */ | |
1709 | int mips32_rev; | |
1710 | int mips64_rev; | |
1711 | int micromips32_rev; | |
1712 | int micromips64_rev; | |
7361da2c AB |
1713 | |
1714 | /* The architecture where the ASE was removed or -1 if the extension has not | |
1715 | been removed. */ | |
1716 | int rem_rev; | |
c6278170 RS |
1717 | }; |
1718 | ||
1719 | /* A table of all supported ASEs. */ | |
1720 | static const struct mips_ase mips_ases[] = { | |
1721 | { "dsp", ASE_DSP, ASE_DSP64, | |
1722 | OPTION_DSP, OPTION_NO_DSP, | |
7361da2c AB |
1723 | 2, 2, 2, 2, |
1724 | -1 }, | |
c6278170 RS |
1725 | |
1726 | { "dspr2", ASE_DSP | ASE_DSPR2, 0, | |
1727 | OPTION_DSPR2, OPTION_NO_DSPR2, | |
7361da2c AB |
1728 | 2, 2, 2, 2, |
1729 | -1 }, | |
c6278170 | 1730 | |
8f4f9071 MF |
1731 | { "dspr3", ASE_DSP | ASE_DSPR2 | ASE_DSPR3, 0, |
1732 | OPTION_DSPR3, OPTION_NO_DSPR3, | |
1733 | 6, 6, -1, -1, | |
1734 | -1 }, | |
1735 | ||
c6278170 RS |
1736 | { "eva", ASE_EVA, 0, |
1737 | OPTION_EVA, OPTION_NO_EVA, | |
7361da2c AB |
1738 | 2, 2, 2, 2, |
1739 | -1 }, | |
c6278170 RS |
1740 | |
1741 | { "mcu", ASE_MCU, 0, | |
1742 | OPTION_MCU, OPTION_NO_MCU, | |
7361da2c AB |
1743 | 2, 2, 2, 2, |
1744 | -1 }, | |
c6278170 RS |
1745 | |
1746 | /* Deprecated in MIPS64r5, but we don't implement that yet. */ | |
1747 | { "mdmx", ASE_MDMX, 0, | |
1748 | OPTION_MDMX, OPTION_NO_MDMX, | |
7361da2c AB |
1749 | -1, 1, -1, -1, |
1750 | 6 }, | |
c6278170 RS |
1751 | |
1752 | /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */ | |
1753 | { "mips3d", ASE_MIPS3D, 0, | |
1754 | OPTION_MIPS3D, OPTION_NO_MIPS3D, | |
7361da2c AB |
1755 | 2, 1, -1, -1, |
1756 | 6 }, | |
c6278170 RS |
1757 | |
1758 | { "mt", ASE_MT, 0, | |
1759 | OPTION_MT, OPTION_NO_MT, | |
7361da2c AB |
1760 | 2, 2, -1, -1, |
1761 | -1 }, | |
c6278170 RS |
1762 | |
1763 | { "smartmips", ASE_SMARTMIPS, 0, | |
1764 | OPTION_SMARTMIPS, OPTION_NO_SMARTMIPS, | |
7361da2c AB |
1765 | 1, -1, -1, -1, |
1766 | 6 }, | |
c6278170 RS |
1767 | |
1768 | { "virt", ASE_VIRT, ASE_VIRT64, | |
1769 | OPTION_VIRT, OPTION_NO_VIRT, | |
7361da2c AB |
1770 | 2, 2, 2, 2, |
1771 | -1 }, | |
56d438b1 CF |
1772 | |
1773 | { "msa", ASE_MSA, ASE_MSA64, | |
1774 | OPTION_MSA, OPTION_NO_MSA, | |
7361da2c AB |
1775 | 2, 2, 2, 2, |
1776 | -1 }, | |
7d64c587 AB |
1777 | |
1778 | { "xpa", ASE_XPA, 0, | |
1779 | OPTION_XPA, OPTION_NO_XPA, | |
909b4e3d | 1780 | 2, 2, 2, 2, |
7361da2c | 1781 | -1 }, |
25499ac7 MR |
1782 | |
1783 | { "mips16e2", ASE_MIPS16E2, 0, | |
1784 | OPTION_MIPS16E2, OPTION_NO_MIPS16E2, | |
1785 | 2, 2, -1, -1, | |
1786 | 6 }, | |
730c3174 SE |
1787 | |
1788 | { "crc", ASE_CRC, ASE_CRC64, | |
1789 | OPTION_CRC, OPTION_NO_CRC, | |
1790 | 6, 6, -1, -1, | |
1791 | -1 }, | |
6f20c942 FS |
1792 | |
1793 | { "ginv", ASE_GINV, 0, | |
1794 | OPTION_GINV, OPTION_NO_GINV, | |
1795 | 6, 6, 6, 6, | |
1796 | -1 }, | |
8095d2f7 CX |
1797 | |
1798 | { "loongson-mmi", ASE_LOONGSON_MMI, 0, | |
1799 | OPTION_LOONGSON_MMI, OPTION_NO_LOONGSON_MMI, | |
1800 | 0, 0, -1, -1, | |
1801 | -1 }, | |
716c08de CX |
1802 | |
1803 | { "loongson-cam", ASE_LOONGSON_CAM, 0, | |
1804 | OPTION_LOONGSON_CAM, OPTION_NO_LOONGSON_CAM, | |
1805 | 0, 0, -1, -1, | |
1806 | -1 }, | |
c6278170 RS |
1807 | }; |
1808 | ||
1809 | /* The set of ASEs that require -mfp64. */ | |
82bda27b | 1810 | #define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA) |
c6278170 RS |
1811 | |
1812 | /* Groups of ASE_* flags that represent different revisions of an ASE. */ | |
1813 | static const unsigned int mips_ase_groups[] = { | |
8f4f9071 | 1814 | ASE_DSP | ASE_DSPR2 | ASE_DSPR3 |
c6278170 RS |
1815 | }; |
1816 | \f | |
252b5132 RH |
1817 | /* Pseudo-op table. |
1818 | ||
1819 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
1820 | should be defined here, but are currently unsupported: .alias, | |
1821 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
1822 | ||
1823 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1824 | specific to the type of debugging information being generated, and | |
1825 | should be defined by the object format: .aent, .begin, .bend, | |
1826 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
1827 | .vreg. | |
1828 | ||
1829 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1830 | not MIPS CPU specific, but are also not specific to the object file | |
1831 | format. This file is probably the best place to define them, but | |
d84bcf09 | 1832 | they are not currently supported: .asm0, .endr, .lab, .struct. */ |
252b5132 | 1833 | |
e972090a NC |
1834 | static const pseudo_typeS mips_pseudo_table[] = |
1835 | { | |
beae10d5 | 1836 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1837 | {"option", s_option, 0}, |
1838 | {"set", s_mipsset, 0}, | |
1839 | {"rdata", s_change_sec, 'r'}, | |
1840 | {"sdata", s_change_sec, 's'}, | |
1841 | {"livereg", s_ignore, 0}, | |
1842 | {"abicalls", s_abicalls, 0}, | |
1843 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1844 | {"cpsetup", s_cpsetup, 0}, |
1845 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1846 | {"cprestore", s_cprestore, 0}, |
6478892d | 1847 | {"cpreturn", s_cpreturn, 0}, |
741d6ea8 JM |
1848 | {"dtprelword", s_dtprelword, 0}, |
1849 | {"dtpreldword", s_dtpreldword, 0}, | |
d0f13682 CLT |
1850 | {"tprelword", s_tprelword, 0}, |
1851 | {"tpreldword", s_tpreldword, 0}, | |
6478892d | 1852 | {"gpvalue", s_gpvalue, 0}, |
252b5132 | 1853 | {"gpword", s_gpword, 0}, |
10181a0d | 1854 | {"gpdword", s_gpdword, 0}, |
a3f278e2 | 1855 | {"ehword", s_ehword, 0}, |
252b5132 RH |
1856 | {"cpadd", s_cpadd, 0}, |
1857 | {"insn", s_insn, 0}, | |
ba92f887 | 1858 | {"nan", s_nan, 0}, |
919731af | 1859 | {"module", s_module, 0}, |
252b5132 | 1860 | |
beae10d5 | 1861 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 | 1862 | chips. */ |
38a57ae7 | 1863 | {"asciiz", stringer, 8 + 1}, |
252b5132 RH |
1864 | {"bss", s_change_sec, 'b'}, |
1865 | {"err", s_err, 0}, | |
1866 | {"half", s_cons, 1}, | |
1867 | {"dword", s_cons, 3}, | |
1868 | {"weakext", s_mips_weakext, 0}, | |
7c752c2a TS |
1869 | {"origin", s_org, 0}, |
1870 | {"repeat", s_rept, 0}, | |
252b5132 | 1871 | |
998b3c36 MR |
1872 | /* For MIPS this is non-standard, but we define it for consistency. */ |
1873 | {"sbss", s_change_sec, 'B'}, | |
1874 | ||
beae10d5 | 1875 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1876 | here for one reason or another. */ |
1877 | {"align", s_align, 0}, | |
1878 | {"byte", s_cons, 0}, | |
1879 | {"data", s_change_sec, 'd'}, | |
1880 | {"double", s_float_cons, 'd'}, | |
1881 | {"float", s_float_cons, 'f'}, | |
1882 | {"globl", s_mips_globl, 0}, | |
1883 | {"global", s_mips_globl, 0}, | |
1884 | {"hword", s_cons, 1}, | |
1885 | {"int", s_cons, 2}, | |
1886 | {"long", s_cons, 2}, | |
1887 | {"octa", s_cons, 4}, | |
1888 | {"quad", s_cons, 3}, | |
cca86cc8 | 1889 | {"section", s_change_section, 0}, |
252b5132 RH |
1890 | {"short", s_cons, 1}, |
1891 | {"single", s_float_cons, 'f'}, | |
754e2bb9 | 1892 | {"stabd", s_mips_stab, 'd'}, |
252b5132 | 1893 | {"stabn", s_mips_stab, 'n'}, |
754e2bb9 | 1894 | {"stabs", s_mips_stab, 's'}, |
252b5132 RH |
1895 | {"text", s_change_sec, 't'}, |
1896 | {"word", s_cons, 2}, | |
add56521 | 1897 | |
add56521 | 1898 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1899 | |
43841e91 | 1900 | { NULL, NULL, 0 }, |
252b5132 RH |
1901 | }; |
1902 | ||
e972090a NC |
1903 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1904 | { | |
beae10d5 KH |
1905 | /* These pseudo-ops should be defined by the object file format. |
1906 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1907 | {"aent", s_mips_ent, 1}, |
1908 | {"bgnb", s_ignore, 0}, | |
1909 | {"end", s_mips_end, 0}, | |
1910 | {"endb", s_ignore, 0}, | |
1911 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1912 | {"file", s_mips_file, 0}, |
252b5132 RH |
1913 | {"fmask", s_mips_mask, 'F'}, |
1914 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1915 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1916 | {"mask", s_mips_mask, 'R'}, |
1917 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1918 | { NULL, NULL, 0 }, |
252b5132 RH |
1919 | }; |
1920 | ||
3ae8dd8d MR |
1921 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
1922 | purpose of the `.dc.a' internal pseudo-op. */ | |
1923 | ||
1924 | int | |
1925 | mips_address_bytes (void) | |
1926 | { | |
919731af | 1927 | file_mips_check_options (); |
3ae8dd8d MR |
1928 | return HAVE_64BIT_ADDRESSES ? 8 : 4; |
1929 | } | |
1930 | ||
17a2f251 | 1931 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1932 | |
1933 | void | |
17a2f251 | 1934 | mips_pop_insert (void) |
252b5132 RH |
1935 | { |
1936 | pop_insert (mips_pseudo_table); | |
1937 | if (! ECOFF_DEBUGGING) | |
1938 | pop_insert (mips_nonecoff_pseudo_table); | |
1939 | } | |
1940 | \f | |
1941 | /* Symbols labelling the current insn. */ | |
1942 | ||
e972090a NC |
1943 | struct insn_label_list |
1944 | { | |
252b5132 RH |
1945 | struct insn_label_list *next; |
1946 | symbolS *label; | |
1947 | }; | |
1948 | ||
252b5132 | 1949 | static struct insn_label_list *free_insn_labels; |
742a56fe | 1950 | #define label_list tc_segment_info_data.labels |
252b5132 | 1951 | |
17a2f251 | 1952 | static void mips_clear_insn_labels (void); |
df58fc94 RS |
1953 | static void mips_mark_labels (void); |
1954 | static void mips_compressed_mark_labels (void); | |
252b5132 RH |
1955 | |
1956 | static inline void | |
17a2f251 | 1957 | mips_clear_insn_labels (void) |
252b5132 | 1958 | { |
ed9e98c2 | 1959 | struct insn_label_list **pl; |
a8dbcb85 | 1960 | segment_info_type *si; |
252b5132 | 1961 | |
a8dbcb85 TS |
1962 | if (now_seg) |
1963 | { | |
1964 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1965 | ; | |
3739860c | 1966 | |
a8dbcb85 TS |
1967 | si = seg_info (now_seg); |
1968 | *pl = si->label_list; | |
1969 | si->label_list = NULL; | |
1970 | } | |
252b5132 | 1971 | } |
a8dbcb85 | 1972 | |
df58fc94 RS |
1973 | /* Mark instruction labels in MIPS16/microMIPS mode. */ |
1974 | ||
1975 | static inline void | |
1976 | mips_mark_labels (void) | |
1977 | { | |
1978 | if (HAVE_CODE_COMPRESSION) | |
1979 | mips_compressed_mark_labels (); | |
1980 | } | |
252b5132 RH |
1981 | \f |
1982 | static char *expr_end; | |
1983 | ||
e423441d | 1984 | /* An expression in a macro instruction. This is set by mips_ip and |
b0e6f033 | 1985 | mips16_ip and when populated is always an O_constant. */ |
252b5132 RH |
1986 | |
1987 | static expressionS imm_expr; | |
252b5132 | 1988 | |
77bd4346 RS |
1989 | /* The relocatable field in an instruction and the relocs associated |
1990 | with it. These variables are used for instructions like LUI and | |
1991 | JAL as well as true offsets. They are also used for address | |
1992 | operands in macros. */ | |
252b5132 | 1993 | |
77bd4346 | 1994 | static expressionS offset_expr; |
f6688943 TS |
1995 | static bfd_reloc_code_real_type offset_reloc[3] |
1996 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1997 | |
df58fc94 RS |
1998 | /* This is set to the resulting size of the instruction to be produced |
1999 | by mips16_ip if an explicit extension is used or by mips_ip if an | |
2000 | explicit size is supplied. */ | |
252b5132 | 2001 | |
df58fc94 | 2002 | static unsigned int forced_insn_length; |
252b5132 | 2003 | |
e1b47bd5 RS |
2004 | /* True if we are assembling an instruction. All dot symbols defined during |
2005 | this time should be treated as code labels. */ | |
2006 | ||
2007 | static bfd_boolean mips_assembling_insn; | |
2008 | ||
ecb4347a DJ |
2009 | /* The pdr segment for per procedure frame/regmask info. Not used for |
2010 | ECOFF debugging. */ | |
252b5132 RH |
2011 | |
2012 | static segT pdr_seg; | |
252b5132 | 2013 | |
e013f690 TS |
2014 | /* The default target format to use. */ |
2015 | ||
aeffff67 RS |
2016 | #if defined (TE_FreeBSD) |
2017 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd" | |
2018 | #elif defined (TE_TMIPS) | |
2019 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips" | |
2020 | #else | |
2021 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips" | |
2022 | #endif | |
2023 | ||
e013f690 | 2024 | const char * |
17a2f251 | 2025 | mips_target_format (void) |
e013f690 TS |
2026 | { |
2027 | switch (OUTPUT_FLAVOR) | |
2028 | { | |
e013f690 | 2029 | case bfd_target_elf_flavour: |
0a44bf69 RS |
2030 | #ifdef TE_VXWORKS |
2031 | if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI) | |
2032 | return (target_big_endian | |
2033 | ? "elf32-bigmips-vxworks" | |
2034 | : "elf32-littlemips-vxworks"); | |
2035 | #endif | |
e013f690 | 2036 | return (target_big_endian |
cfe86eaa | 2037 | ? (HAVE_64BIT_OBJECTS |
aeffff67 | 2038 | ? ELF_TARGET ("elf64-", "big") |
cfe86eaa | 2039 | : (HAVE_NEWABI |
aeffff67 RS |
2040 | ? ELF_TARGET ("elf32-n", "big") |
2041 | : ELF_TARGET ("elf32-", "big"))) | |
cfe86eaa | 2042 | : (HAVE_64BIT_OBJECTS |
aeffff67 | 2043 | ? ELF_TARGET ("elf64-", "little") |
cfe86eaa | 2044 | : (HAVE_NEWABI |
aeffff67 RS |
2045 | ? ELF_TARGET ("elf32-n", "little") |
2046 | : ELF_TARGET ("elf32-", "little")))); | |
e013f690 TS |
2047 | default: |
2048 | abort (); | |
2049 | return NULL; | |
2050 | } | |
2051 | } | |
2052 | ||
c6278170 RS |
2053 | /* Return the ISA revision that is currently in use, or 0 if we are |
2054 | generating code for MIPS V or below. */ | |
2055 | ||
2056 | static int | |
2057 | mips_isa_rev (void) | |
2058 | { | |
2059 | if (mips_opts.isa == ISA_MIPS32R2 || mips_opts.isa == ISA_MIPS64R2) | |
2060 | return 2; | |
2061 | ||
ae52f483 AB |
2062 | if (mips_opts.isa == ISA_MIPS32R3 || mips_opts.isa == ISA_MIPS64R3) |
2063 | return 3; | |
2064 | ||
2065 | if (mips_opts.isa == ISA_MIPS32R5 || mips_opts.isa == ISA_MIPS64R5) | |
2066 | return 5; | |
2067 | ||
7361da2c AB |
2068 | if (mips_opts.isa == ISA_MIPS32R6 || mips_opts.isa == ISA_MIPS64R6) |
2069 | return 6; | |
2070 | ||
c6278170 RS |
2071 | /* microMIPS implies revision 2 or above. */ |
2072 | if (mips_opts.micromips) | |
2073 | return 2; | |
2074 | ||
2075 | if (mips_opts.isa == ISA_MIPS32 || mips_opts.isa == ISA_MIPS64) | |
2076 | return 1; | |
2077 | ||
2078 | return 0; | |
2079 | } | |
2080 | ||
2081 | /* Return the mask of all ASEs that are revisions of those in FLAGS. */ | |
2082 | ||
2083 | static unsigned int | |
2084 | mips_ase_mask (unsigned int flags) | |
2085 | { | |
2086 | unsigned int i; | |
2087 | ||
2088 | for (i = 0; i < ARRAY_SIZE (mips_ase_groups); i++) | |
2089 | if (flags & mips_ase_groups[i]) | |
2090 | flags |= mips_ase_groups[i]; | |
2091 | return flags; | |
2092 | } | |
2093 | ||
2094 | /* Check whether the current ISA supports ASE. Issue a warning if | |
2095 | appropriate. */ | |
2096 | ||
2097 | static void | |
2098 | mips_check_isa_supports_ase (const struct mips_ase *ase) | |
2099 | { | |
2100 | const char *base; | |
2101 | int min_rev, size; | |
2102 | static unsigned int warned_isa; | |
2103 | static unsigned int warned_fp32; | |
2104 | ||
2105 | if (ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
2106 | min_rev = mips_opts.micromips ? ase->micromips64_rev : ase->mips64_rev; | |
2107 | else | |
2108 | min_rev = mips_opts.micromips ? ase->micromips32_rev : ase->mips32_rev; | |
2109 | if ((min_rev < 0 || mips_isa_rev () < min_rev) | |
2110 | && (warned_isa & ase->flags) != ase->flags) | |
2111 | { | |
2112 | warned_isa |= ase->flags; | |
2113 | base = mips_opts.micromips ? "microMIPS" : "MIPS"; | |
2114 | size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32; | |
2115 | if (min_rev < 0) | |
1661c76c | 2116 | as_warn (_("the %d-bit %s architecture does not support the" |
c6278170 RS |
2117 | " `%s' extension"), size, base, ase->name); |
2118 | else | |
1661c76c | 2119 | as_warn (_("the `%s' extension requires %s%d revision %d or greater"), |
c6278170 RS |
2120 | ase->name, base, size, min_rev); |
2121 | } | |
7361da2c AB |
2122 | else if ((ase->rem_rev > 0 && mips_isa_rev () >= ase->rem_rev) |
2123 | && (warned_isa & ase->flags) != ase->flags) | |
2124 | { | |
2125 | warned_isa |= ase->flags; | |
2126 | base = mips_opts.micromips ? "microMIPS" : "MIPS"; | |
2127 | size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32; | |
2128 | as_warn (_("the `%s' extension was removed in %s%d revision %d"), | |
2129 | ase->name, base, size, ase->rem_rev); | |
2130 | } | |
2131 | ||
c6278170 | 2132 | if ((ase->flags & FP64_ASES) |
0b35dfee | 2133 | && mips_opts.fp != 64 |
c6278170 RS |
2134 | && (warned_fp32 & ase->flags) != ase->flags) |
2135 | { | |
2136 | warned_fp32 |= ase->flags; | |
1661c76c | 2137 | as_warn (_("the `%s' extension requires 64-bit FPRs"), ase->name); |
c6278170 RS |
2138 | } |
2139 | } | |
2140 | ||
2141 | /* Check all enabled ASEs to see whether they are supported by the | |
2142 | chosen architecture. */ | |
2143 | ||
2144 | static void | |
2145 | mips_check_isa_supports_ases (void) | |
2146 | { | |
2147 | unsigned int i, mask; | |
2148 | ||
2149 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
2150 | { | |
2151 | mask = mips_ase_mask (mips_ases[i].flags); | |
2152 | if ((mips_opts.ase & mask) == mips_ases[i].flags) | |
2153 | mips_check_isa_supports_ase (&mips_ases[i]); | |
2154 | } | |
2155 | } | |
2156 | ||
2157 | /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags | |
2158 | that were affected. */ | |
2159 | ||
2160 | static unsigned int | |
919731af | 2161 | mips_set_ase (const struct mips_ase *ase, struct mips_set_options *opts, |
2162 | bfd_boolean enabled_p) | |
c6278170 RS |
2163 | { |
2164 | unsigned int mask; | |
2165 | ||
2166 | mask = mips_ase_mask (ase->flags); | |
919731af | 2167 | opts->ase &= ~mask; |
92cebb3d MR |
2168 | |
2169 | /* Clear combination ASE flags, which need to be recalculated based on | |
2170 | updated regular ASE settings. */ | |
9785fc2a | 2171 | opts->ase &= ~(ASE_MIPS16E2_MT | ASE_XPA_VIRT); |
92cebb3d | 2172 | |
c6278170 | 2173 | if (enabled_p) |
919731af | 2174 | opts->ase |= ase->flags; |
25499ac7 | 2175 | |
9785fc2a MR |
2176 | /* The Virtualization ASE has eXtended Physical Addressing (XPA) |
2177 | instructions which are only valid when both ASEs are enabled. | |
2178 | This sets the ASE_XPA_VIRT flag when both ASEs are present. */ | |
2179 | if ((opts->ase & (ASE_XPA | ASE_VIRT)) == (ASE_XPA | ASE_VIRT)) | |
2180 | { | |
2181 | opts->ase |= ASE_XPA_VIRT; | |
2182 | mask |= ASE_XPA_VIRT; | |
2183 | } | |
25499ac7 MR |
2184 | if ((opts->ase & (ASE_MIPS16E2 | ASE_MT)) == (ASE_MIPS16E2 | ASE_MT)) |
2185 | { | |
2186 | opts->ase |= ASE_MIPS16E2_MT; | |
2187 | mask |= ASE_MIPS16E2_MT; | |
2188 | } | |
2189 | ||
c6278170 RS |
2190 | return mask; |
2191 | } | |
2192 | ||
2193 | /* Return the ASE called NAME, or null if none. */ | |
2194 | ||
2195 | static const struct mips_ase * | |
2196 | mips_lookup_ase (const char *name) | |
2197 | { | |
2198 | unsigned int i; | |
2199 | ||
2200 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
2201 | if (strcmp (name, mips_ases[i].name) == 0) | |
2202 | return &mips_ases[i]; | |
2203 | return NULL; | |
2204 | } | |
2205 | ||
df58fc94 | 2206 | /* Return the length of a microMIPS instruction in bytes. If bits of |
100b4f2e MR |
2207 | the mask beyond the low 16 are 0, then it is a 16-bit instruction, |
2208 | otherwise it is a 32-bit instruction. */ | |
df58fc94 RS |
2209 | |
2210 | static inline unsigned int | |
2211 | micromips_insn_length (const struct mips_opcode *mo) | |
2212 | { | |
7fd53920 | 2213 | return mips_opcode_32bit_p (mo) ? 4 : 2; |
df58fc94 RS |
2214 | } |
2215 | ||
5c04167a RS |
2216 | /* Return the length of MIPS16 instruction OPCODE. */ |
2217 | ||
2218 | static inline unsigned int | |
2219 | mips16_opcode_length (unsigned long opcode) | |
2220 | { | |
2221 | return (opcode >> 16) == 0 ? 2 : 4; | |
2222 | } | |
2223 | ||
1e915849 RS |
2224 | /* Return the length of instruction INSN. */ |
2225 | ||
2226 | static inline unsigned int | |
2227 | insn_length (const struct mips_cl_insn *insn) | |
2228 | { | |
df58fc94 RS |
2229 | if (mips_opts.micromips) |
2230 | return micromips_insn_length (insn->insn_mo); | |
2231 | else if (mips_opts.mips16) | |
5c04167a | 2232 | return mips16_opcode_length (insn->insn_opcode); |
df58fc94 | 2233 | else |
1e915849 | 2234 | return 4; |
1e915849 RS |
2235 | } |
2236 | ||
2237 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
2238 | ||
2239 | static void | |
2240 | create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) | |
2241 | { | |
2242 | size_t i; | |
2243 | ||
2244 | insn->insn_mo = mo; | |
1e915849 RS |
2245 | insn->insn_opcode = mo->match; |
2246 | insn->frag = NULL; | |
2247 | insn->where = 0; | |
2248 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
2249 | insn->fixp[i] = NULL; | |
2250 | insn->fixed_p = (mips_opts.noreorder > 0); | |
2251 | insn->noreorder_p = (mips_opts.noreorder > 0); | |
2252 | insn->mips16_absolute_jump_p = 0; | |
15be625d | 2253 | insn->complete_p = 0; |
e407c74b | 2254 | insn->cleared_p = 0; |
1e915849 RS |
2255 | } |
2256 | ||
fc76e730 RS |
2257 | /* Get a list of all the operands in INSN. */ |
2258 | ||
2259 | static const struct mips_operand_array * | |
2260 | insn_operands (const struct mips_cl_insn *insn) | |
2261 | { | |
2262 | if (insn->insn_mo >= &mips_opcodes[0] | |
2263 | && insn->insn_mo < &mips_opcodes[NUMOPCODES]) | |
2264 | return &mips_operands[insn->insn_mo - &mips_opcodes[0]]; | |
2265 | ||
2266 | if (insn->insn_mo >= &mips16_opcodes[0] | |
2267 | && insn->insn_mo < &mips16_opcodes[bfd_mips16_num_opcodes]) | |
2268 | return &mips16_operands[insn->insn_mo - &mips16_opcodes[0]]; | |
2269 | ||
2270 | if (insn->insn_mo >= µmips_opcodes[0] | |
2271 | && insn->insn_mo < µmips_opcodes[bfd_micromips_num_opcodes]) | |
2272 | return µmips_operands[insn->insn_mo - µmips_opcodes[0]]; | |
2273 | ||
2274 | abort (); | |
2275 | } | |
2276 | ||
2277 | /* Get a description of operand OPNO of INSN. */ | |
2278 | ||
2279 | static const struct mips_operand * | |
2280 | insn_opno (const struct mips_cl_insn *insn, unsigned opno) | |
2281 | { | |
2282 | const struct mips_operand_array *operands; | |
2283 | ||
2284 | operands = insn_operands (insn); | |
2285 | if (opno >= MAX_OPERANDS || !operands->operand[opno]) | |
2286 | abort (); | |
2287 | return operands->operand[opno]; | |
2288 | } | |
2289 | ||
e077a1c8 RS |
2290 | /* Install UVAL as the value of OPERAND in INSN. */ |
2291 | ||
2292 | static inline void | |
2293 | insn_insert_operand (struct mips_cl_insn *insn, | |
2294 | const struct mips_operand *operand, unsigned int uval) | |
2295 | { | |
25499ac7 MR |
2296 | if (mips_opts.mips16 |
2297 | && operand->type == OP_INT && operand->lsb == 0 | |
2298 | && mips_opcode_32bit_p (insn->insn_mo)) | |
2299 | insn->insn_opcode |= mips16_immed_extend (uval, operand->size); | |
2300 | else | |
2301 | insn->insn_opcode = mips_insert_operand (operand, insn->insn_opcode, uval); | |
e077a1c8 RS |
2302 | } |
2303 | ||
fc76e730 RS |
2304 | /* Extract the value of OPERAND from INSN. */ |
2305 | ||
2306 | static inline unsigned | |
2307 | insn_extract_operand (const struct mips_cl_insn *insn, | |
2308 | const struct mips_operand *operand) | |
2309 | { | |
2310 | return mips_extract_operand (operand, insn->insn_opcode); | |
2311 | } | |
2312 | ||
df58fc94 | 2313 | /* Record the current MIPS16/microMIPS mode in now_seg. */ |
742a56fe RS |
2314 | |
2315 | static void | |
df58fc94 | 2316 | mips_record_compressed_mode (void) |
742a56fe RS |
2317 | { |
2318 | segment_info_type *si; | |
2319 | ||
2320 | si = seg_info (now_seg); | |
2321 | if (si->tc_segment_info_data.mips16 != mips_opts.mips16) | |
2322 | si->tc_segment_info_data.mips16 = mips_opts.mips16; | |
df58fc94 RS |
2323 | if (si->tc_segment_info_data.micromips != mips_opts.micromips) |
2324 | si->tc_segment_info_data.micromips = mips_opts.micromips; | |
742a56fe RS |
2325 | } |
2326 | ||
4d68580a RS |
2327 | /* Read a standard MIPS instruction from BUF. */ |
2328 | ||
2329 | static unsigned long | |
2330 | read_insn (char *buf) | |
2331 | { | |
2332 | if (target_big_endian) | |
2333 | return bfd_getb32 ((bfd_byte *) buf); | |
2334 | else | |
2335 | return bfd_getl32 ((bfd_byte *) buf); | |
2336 | } | |
2337 | ||
2338 | /* Write standard MIPS instruction INSN to BUF. Return a pointer to | |
2339 | the next byte. */ | |
2340 | ||
2341 | static char * | |
2342 | write_insn (char *buf, unsigned int insn) | |
2343 | { | |
2344 | md_number_to_chars (buf, insn, 4); | |
2345 | return buf + 4; | |
2346 | } | |
2347 | ||
2348 | /* Read a microMIPS or MIPS16 opcode from BUF, given that it | |
2349 | has length LENGTH. */ | |
2350 | ||
2351 | static unsigned long | |
2352 | read_compressed_insn (char *buf, unsigned int length) | |
2353 | { | |
2354 | unsigned long insn; | |
2355 | unsigned int i; | |
2356 | ||
2357 | insn = 0; | |
2358 | for (i = 0; i < length; i += 2) | |
2359 | { | |
2360 | insn <<= 16; | |
2361 | if (target_big_endian) | |
2362 | insn |= bfd_getb16 ((char *) buf); | |
2363 | else | |
2364 | insn |= bfd_getl16 ((char *) buf); | |
2365 | buf += 2; | |
2366 | } | |
2367 | return insn; | |
2368 | } | |
2369 | ||
5c04167a RS |
2370 | /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the |
2371 | instruction is LENGTH bytes long. Return a pointer to the next byte. */ | |
2372 | ||
2373 | static char * | |
2374 | write_compressed_insn (char *buf, unsigned int insn, unsigned int length) | |
2375 | { | |
2376 | unsigned int i; | |
2377 | ||
2378 | for (i = 0; i < length; i += 2) | |
2379 | md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2); | |
2380 | return buf + length; | |
2381 | } | |
2382 | ||
1e915849 RS |
2383 | /* Install INSN at the location specified by its "frag" and "where" fields. */ |
2384 | ||
2385 | static void | |
2386 | install_insn (const struct mips_cl_insn *insn) | |
2387 | { | |
2388 | char *f = insn->frag->fr_literal + insn->where; | |
5c04167a RS |
2389 | if (HAVE_CODE_COMPRESSION) |
2390 | write_compressed_insn (f, insn->insn_opcode, insn_length (insn)); | |
1e915849 | 2391 | else |
4d68580a | 2392 | write_insn (f, insn->insn_opcode); |
df58fc94 | 2393 | mips_record_compressed_mode (); |
1e915849 RS |
2394 | } |
2395 | ||
2396 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
2397 | and install the opcode in the new location. */ | |
2398 | ||
2399 | static void | |
2400 | move_insn (struct mips_cl_insn *insn, fragS *frag, long where) | |
2401 | { | |
2402 | size_t i; | |
2403 | ||
2404 | insn->frag = frag; | |
2405 | insn->where = where; | |
2406 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
2407 | if (insn->fixp[i] != NULL) | |
2408 | { | |
2409 | insn->fixp[i]->fx_frag = frag; | |
2410 | insn->fixp[i]->fx_where = where; | |
2411 | } | |
2412 | install_insn (insn); | |
2413 | } | |
2414 | ||
2415 | /* Add INSN to the end of the output. */ | |
2416 | ||
2417 | static void | |
2418 | add_fixed_insn (struct mips_cl_insn *insn) | |
2419 | { | |
2420 | char *f = frag_more (insn_length (insn)); | |
2421 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
2422 | } | |
2423 | ||
2424 | /* Start a variant frag and move INSN to the start of the variant part, | |
2425 | marking it as fixed. The other arguments are as for frag_var. */ | |
2426 | ||
2427 | static void | |
2428 | add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, | |
2429 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
2430 | { | |
2431 | frag_grow (max_chars); | |
2432 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
2433 | insn->fixed_p = 1; | |
2434 | frag_var (rs_machine_dependent, max_chars, var, | |
2435 | subtype, symbol, offset, NULL); | |
2436 | } | |
2437 | ||
2438 | /* Insert N copies of INSN into the history buffer, starting at | |
2439 | position FIRST. Neither FIRST nor N need to be clipped. */ | |
2440 | ||
2441 | static void | |
2442 | insert_into_history (unsigned int first, unsigned int n, | |
2443 | const struct mips_cl_insn *insn) | |
2444 | { | |
2445 | if (mips_relax.sequence != 2) | |
2446 | { | |
2447 | unsigned int i; | |
2448 | ||
2449 | for (i = ARRAY_SIZE (history); i-- > first;) | |
2450 | if (i >= first + n) | |
2451 | history[i] = history[i - n]; | |
2452 | else | |
2453 | history[i] = *insn; | |
2454 | } | |
2455 | } | |
2456 | ||
e3de51ce RS |
2457 | /* Clear the error in insn_error. */ |
2458 | ||
2459 | static void | |
2460 | clear_insn_error (void) | |
2461 | { | |
2462 | memset (&insn_error, 0, sizeof (insn_error)); | |
2463 | } | |
2464 | ||
2465 | /* Possibly record error message MSG for the current instruction. | |
2466 | If the error is about a particular argument, ARGNUM is the 1-based | |
2467 | number of that argument, otherwise it is 0. FORMAT is the format | |
2468 | of MSG. Return true if MSG was used, false if the current message | |
2469 | was kept. */ | |
2470 | ||
2471 | static bfd_boolean | |
2472 | set_insn_error_format (int argnum, enum mips_insn_error_format format, | |
2473 | const char *msg) | |
2474 | { | |
2475 | if (argnum == 0) | |
2476 | { | |
2477 | /* Give priority to errors against specific arguments, and to | |
2478 | the first whole-instruction message. */ | |
2479 | if (insn_error.msg) | |
2480 | return FALSE; | |
2481 | } | |
2482 | else | |
2483 | { | |
2484 | /* Keep insn_error if it is against a later argument. */ | |
2485 | if (argnum < insn_error.min_argnum) | |
2486 | return FALSE; | |
2487 | ||
2488 | /* If both errors are against the same argument but are different, | |
2489 | give up on reporting a specific error for this argument. | |
2490 | See the comment about mips_insn_error for details. */ | |
2491 | if (argnum == insn_error.min_argnum | |
2492 | && insn_error.msg | |
2493 | && strcmp (insn_error.msg, msg) != 0) | |
2494 | { | |
2495 | insn_error.msg = 0; | |
2496 | insn_error.min_argnum += 1; | |
2497 | return FALSE; | |
2498 | } | |
2499 | } | |
2500 | insn_error.min_argnum = argnum; | |
2501 | insn_error.format = format; | |
2502 | insn_error.msg = msg; | |
2503 | return TRUE; | |
2504 | } | |
2505 | ||
2506 | /* Record an instruction error with no % format fields. ARGNUM and MSG are | |
2507 | as for set_insn_error_format. */ | |
2508 | ||
2509 | static void | |
2510 | set_insn_error (int argnum, const char *msg) | |
2511 | { | |
2512 | set_insn_error_format (argnum, ERR_FMT_PLAIN, msg); | |
2513 | } | |
2514 | ||
2515 | /* Record an instruction error with one %d field I. ARGNUM and MSG are | |
2516 | as for set_insn_error_format. */ | |
2517 | ||
2518 | static void | |
2519 | set_insn_error_i (int argnum, const char *msg, int i) | |
2520 | { | |
2521 | if (set_insn_error_format (argnum, ERR_FMT_I, msg)) | |
2522 | insn_error.u.i = i; | |
2523 | } | |
2524 | ||
2525 | /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG | |
2526 | are as for set_insn_error_format. */ | |
2527 | ||
2528 | static void | |
2529 | set_insn_error_ss (int argnum, const char *msg, const char *s1, const char *s2) | |
2530 | { | |
2531 | if (set_insn_error_format (argnum, ERR_FMT_SS, msg)) | |
2532 | { | |
2533 | insn_error.u.ss[0] = s1; | |
2534 | insn_error.u.ss[1] = s2; | |
2535 | } | |
2536 | } | |
2537 | ||
2538 | /* Report the error in insn_error, which is against assembly code STR. */ | |
2539 | ||
2540 | static void | |
2541 | report_insn_error (const char *str) | |
2542 | { | |
e1fa0163 | 2543 | const char *msg = concat (insn_error.msg, " `%s'", NULL); |
e3de51ce | 2544 | |
e3de51ce RS |
2545 | switch (insn_error.format) |
2546 | { | |
2547 | case ERR_FMT_PLAIN: | |
2548 | as_bad (msg, str); | |
2549 | break; | |
2550 | ||
2551 | case ERR_FMT_I: | |
2552 | as_bad (msg, insn_error.u.i, str); | |
2553 | break; | |
2554 | ||
2555 | case ERR_FMT_SS: | |
2556 | as_bad (msg, insn_error.u.ss[0], insn_error.u.ss[1], str); | |
2557 | break; | |
2558 | } | |
e1fa0163 NC |
2559 | |
2560 | free ((char *) msg); | |
e3de51ce RS |
2561 | } |
2562 | ||
71400594 RS |
2563 | /* Initialize vr4120_conflicts. There is a bit of duplication here: |
2564 | the idea is to make it obvious at a glance that each errata is | |
2565 | included. */ | |
2566 | ||
2567 | static void | |
2568 | init_vr4120_conflicts (void) | |
2569 | { | |
2570 | #define CONFLICT(FIRST, SECOND) \ | |
2571 | vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND | |
2572 | ||
2573 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
2574 | CONFLICT (MACC, DIV); | |
2575 | CONFLICT (DMACC, DIV); | |
2576 | ||
2577 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ | |
2578 | CONFLICT (DMULT, DMULT); | |
2579 | CONFLICT (DMULT, DMACC); | |
2580 | CONFLICT (DMACC, DMULT); | |
2581 | CONFLICT (DMACC, DMACC); | |
2582 | ||
2583 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
2584 | CONFLICT (MACC, MTHILO); | |
2585 | CONFLICT (DMACC, MTHILO); | |
2586 | ||
2587 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU | |
2588 | instruction is executed immediately after a MACC or DMACC | |
2589 | instruction, the result of [either instruction] is incorrect." */ | |
2590 | CONFLICT (MACC, MULT); | |
2591 | CONFLICT (MACC, DMULT); | |
2592 | CONFLICT (DMACC, MULT); | |
2593 | CONFLICT (DMACC, DMULT); | |
2594 | ||
2595 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
2596 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
2597 | DDIV or DDIVU instruction, the result of the MACC or | |
2598 | DMACC instruction is incorrect.". */ | |
2599 | CONFLICT (DMULT, MACC); | |
2600 | CONFLICT (DMULT, DMACC); | |
2601 | CONFLICT (DIV, MACC); | |
2602 | CONFLICT (DIV, DMACC); | |
2603 | ||
2604 | #undef CONFLICT | |
2605 | } | |
2606 | ||
707bfff6 TS |
2607 | struct regname { |
2608 | const char *name; | |
2609 | unsigned int num; | |
2610 | }; | |
2611 | ||
14daeee3 | 2612 | #define RNUM_MASK 0x00000ff |
56d438b1 | 2613 | #define RTYPE_MASK 0x0ffff00 |
14daeee3 RS |
2614 | #define RTYPE_NUM 0x0000100 |
2615 | #define RTYPE_FPU 0x0000200 | |
2616 | #define RTYPE_FCC 0x0000400 | |
2617 | #define RTYPE_VEC 0x0000800 | |
2618 | #define RTYPE_GP 0x0001000 | |
2619 | #define RTYPE_CP0 0x0002000 | |
2620 | #define RTYPE_PC 0x0004000 | |
2621 | #define RTYPE_ACC 0x0008000 | |
2622 | #define RTYPE_CCC 0x0010000 | |
2623 | #define RTYPE_VI 0x0020000 | |
2624 | #define RTYPE_VF 0x0040000 | |
2625 | #define RTYPE_R5900_I 0x0080000 | |
2626 | #define RTYPE_R5900_Q 0x0100000 | |
2627 | #define RTYPE_R5900_R 0x0200000 | |
2628 | #define RTYPE_R5900_ACC 0x0400000 | |
56d438b1 | 2629 | #define RTYPE_MSA 0x0800000 |
14daeee3 | 2630 | #define RWARN 0x8000000 |
707bfff6 TS |
2631 | |
2632 | #define GENERIC_REGISTER_NUMBERS \ | |
2633 | {"$0", RTYPE_NUM | 0}, \ | |
2634 | {"$1", RTYPE_NUM | 1}, \ | |
2635 | {"$2", RTYPE_NUM | 2}, \ | |
2636 | {"$3", RTYPE_NUM | 3}, \ | |
2637 | {"$4", RTYPE_NUM | 4}, \ | |
2638 | {"$5", RTYPE_NUM | 5}, \ | |
2639 | {"$6", RTYPE_NUM | 6}, \ | |
2640 | {"$7", RTYPE_NUM | 7}, \ | |
2641 | {"$8", RTYPE_NUM | 8}, \ | |
2642 | {"$9", RTYPE_NUM | 9}, \ | |
2643 | {"$10", RTYPE_NUM | 10}, \ | |
2644 | {"$11", RTYPE_NUM | 11}, \ | |
2645 | {"$12", RTYPE_NUM | 12}, \ | |
2646 | {"$13", RTYPE_NUM | 13}, \ | |
2647 | {"$14", RTYPE_NUM | 14}, \ | |
2648 | {"$15", RTYPE_NUM | 15}, \ | |
2649 | {"$16", RTYPE_NUM | 16}, \ | |
2650 | {"$17", RTYPE_NUM | 17}, \ | |
2651 | {"$18", RTYPE_NUM | 18}, \ | |
2652 | {"$19", RTYPE_NUM | 19}, \ | |
2653 | {"$20", RTYPE_NUM | 20}, \ | |
2654 | {"$21", RTYPE_NUM | 21}, \ | |
2655 | {"$22", RTYPE_NUM | 22}, \ | |
2656 | {"$23", RTYPE_NUM | 23}, \ | |
2657 | {"$24", RTYPE_NUM | 24}, \ | |
2658 | {"$25", RTYPE_NUM | 25}, \ | |
2659 | {"$26", RTYPE_NUM | 26}, \ | |
2660 | {"$27", RTYPE_NUM | 27}, \ | |
2661 | {"$28", RTYPE_NUM | 28}, \ | |
2662 | {"$29", RTYPE_NUM | 29}, \ | |
2663 | {"$30", RTYPE_NUM | 30}, \ | |
3739860c | 2664 | {"$31", RTYPE_NUM | 31} |
707bfff6 TS |
2665 | |
2666 | #define FPU_REGISTER_NAMES \ | |
2667 | {"$f0", RTYPE_FPU | 0}, \ | |
2668 | {"$f1", RTYPE_FPU | 1}, \ | |
2669 | {"$f2", RTYPE_FPU | 2}, \ | |
2670 | {"$f3", RTYPE_FPU | 3}, \ | |
2671 | {"$f4", RTYPE_FPU | 4}, \ | |
2672 | {"$f5", RTYPE_FPU | 5}, \ | |
2673 | {"$f6", RTYPE_FPU | 6}, \ | |
2674 | {"$f7", RTYPE_FPU | 7}, \ | |
2675 | {"$f8", RTYPE_FPU | 8}, \ | |
2676 | {"$f9", RTYPE_FPU | 9}, \ | |
2677 | {"$f10", RTYPE_FPU | 10}, \ | |
2678 | {"$f11", RTYPE_FPU | 11}, \ | |
2679 | {"$f12", RTYPE_FPU | 12}, \ | |
2680 | {"$f13", RTYPE_FPU | 13}, \ | |
2681 | {"$f14", RTYPE_FPU | 14}, \ | |
2682 | {"$f15", RTYPE_FPU | 15}, \ | |
2683 | {"$f16", RTYPE_FPU | 16}, \ | |
2684 | {"$f17", RTYPE_FPU | 17}, \ | |
2685 | {"$f18", RTYPE_FPU | 18}, \ | |
2686 | {"$f19", RTYPE_FPU | 19}, \ | |
2687 | {"$f20", RTYPE_FPU | 20}, \ | |
2688 | {"$f21", RTYPE_FPU | 21}, \ | |
2689 | {"$f22", RTYPE_FPU | 22}, \ | |
2690 | {"$f23", RTYPE_FPU | 23}, \ | |
2691 | {"$f24", RTYPE_FPU | 24}, \ | |
2692 | {"$f25", RTYPE_FPU | 25}, \ | |
2693 | {"$f26", RTYPE_FPU | 26}, \ | |
2694 | {"$f27", RTYPE_FPU | 27}, \ | |
2695 | {"$f28", RTYPE_FPU | 28}, \ | |
2696 | {"$f29", RTYPE_FPU | 29}, \ | |
2697 | {"$f30", RTYPE_FPU | 30}, \ | |
2698 | {"$f31", RTYPE_FPU | 31} | |
2699 | ||
2700 | #define FPU_CONDITION_CODE_NAMES \ | |
2701 | {"$fcc0", RTYPE_FCC | 0}, \ | |
2702 | {"$fcc1", RTYPE_FCC | 1}, \ | |
2703 | {"$fcc2", RTYPE_FCC | 2}, \ | |
2704 | {"$fcc3", RTYPE_FCC | 3}, \ | |
2705 | {"$fcc4", RTYPE_FCC | 4}, \ | |
2706 | {"$fcc5", RTYPE_FCC | 5}, \ | |
2707 | {"$fcc6", RTYPE_FCC | 6}, \ | |
2708 | {"$fcc7", RTYPE_FCC | 7} | |
2709 | ||
2710 | #define COPROC_CONDITION_CODE_NAMES \ | |
2711 | {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \ | |
2712 | {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \ | |
2713 | {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \ | |
2714 | {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \ | |
2715 | {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \ | |
2716 | {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \ | |
2717 | {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \ | |
2718 | {"$cc7", RTYPE_FCC | RTYPE_CCC | 7} | |
2719 | ||
2720 | #define N32N64_SYMBOLIC_REGISTER_NAMES \ | |
2721 | {"$a4", RTYPE_GP | 8}, \ | |
2722 | {"$a5", RTYPE_GP | 9}, \ | |
2723 | {"$a6", RTYPE_GP | 10}, \ | |
2724 | {"$a7", RTYPE_GP | 11}, \ | |
2725 | {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \ | |
2726 | {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \ | |
2727 | {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \ | |
2728 | {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \ | |
2729 | {"$t0", RTYPE_GP | 12}, \ | |
2730 | {"$t1", RTYPE_GP | 13}, \ | |
2731 | {"$t2", RTYPE_GP | 14}, \ | |
2732 | {"$t3", RTYPE_GP | 15} | |
2733 | ||
2734 | #define O32_SYMBOLIC_REGISTER_NAMES \ | |
2735 | {"$t0", RTYPE_GP | 8}, \ | |
2736 | {"$t1", RTYPE_GP | 9}, \ | |
2737 | {"$t2", RTYPE_GP | 10}, \ | |
2738 | {"$t3", RTYPE_GP | 11}, \ | |
2739 | {"$t4", RTYPE_GP | 12}, \ | |
2740 | {"$t5", RTYPE_GP | 13}, \ | |
2741 | {"$t6", RTYPE_GP | 14}, \ | |
2742 | {"$t7", RTYPE_GP | 15}, \ | |
2743 | {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \ | |
2744 | {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \ | |
2745 | {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \ | |
3739860c | 2746 | {"$ta3", RTYPE_GP | 15} /* alias for $t7 */ |
707bfff6 TS |
2747 | |
2748 | /* Remaining symbolic register names */ | |
2749 | #define SYMBOLIC_REGISTER_NAMES \ | |
2750 | {"$zero", RTYPE_GP | 0}, \ | |
2751 | {"$at", RTYPE_GP | 1}, \ | |
2752 | {"$AT", RTYPE_GP | 1}, \ | |
2753 | {"$v0", RTYPE_GP | 2}, \ | |
2754 | {"$v1", RTYPE_GP | 3}, \ | |
2755 | {"$a0", RTYPE_GP | 4}, \ | |
2756 | {"$a1", RTYPE_GP | 5}, \ | |
2757 | {"$a2", RTYPE_GP | 6}, \ | |
2758 | {"$a3", RTYPE_GP | 7}, \ | |
2759 | {"$s0", RTYPE_GP | 16}, \ | |
2760 | {"$s1", RTYPE_GP | 17}, \ | |
2761 | {"$s2", RTYPE_GP | 18}, \ | |
2762 | {"$s3", RTYPE_GP | 19}, \ | |
2763 | {"$s4", RTYPE_GP | 20}, \ | |
2764 | {"$s5", RTYPE_GP | 21}, \ | |
2765 | {"$s6", RTYPE_GP | 22}, \ | |
2766 | {"$s7", RTYPE_GP | 23}, \ | |
2767 | {"$t8", RTYPE_GP | 24}, \ | |
2768 | {"$t9", RTYPE_GP | 25}, \ | |
2769 | {"$k0", RTYPE_GP | 26}, \ | |
2770 | {"$kt0", RTYPE_GP | 26}, \ | |
2771 | {"$k1", RTYPE_GP | 27}, \ | |
2772 | {"$kt1", RTYPE_GP | 27}, \ | |
2773 | {"$gp", RTYPE_GP | 28}, \ | |
2774 | {"$sp", RTYPE_GP | 29}, \ | |
2775 | {"$s8", RTYPE_GP | 30}, \ | |
2776 | {"$fp", RTYPE_GP | 30}, \ | |
2777 | {"$ra", RTYPE_GP | 31} | |
2778 | ||
2779 | #define MIPS16_SPECIAL_REGISTER_NAMES \ | |
2780 | {"$pc", RTYPE_PC | 0} | |
2781 | ||
2782 | #define MDMX_VECTOR_REGISTER_NAMES \ | |
2783 | /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \ | |
2784 | /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \ | |
2785 | {"$v2", RTYPE_VEC | 2}, \ | |
2786 | {"$v3", RTYPE_VEC | 3}, \ | |
2787 | {"$v4", RTYPE_VEC | 4}, \ | |
2788 | {"$v5", RTYPE_VEC | 5}, \ | |
2789 | {"$v6", RTYPE_VEC | 6}, \ | |
2790 | {"$v7", RTYPE_VEC | 7}, \ | |
2791 | {"$v8", RTYPE_VEC | 8}, \ | |
2792 | {"$v9", RTYPE_VEC | 9}, \ | |
2793 | {"$v10", RTYPE_VEC | 10}, \ | |
2794 | {"$v11", RTYPE_VEC | 11}, \ | |
2795 | {"$v12", RTYPE_VEC | 12}, \ | |
2796 | {"$v13", RTYPE_VEC | 13}, \ | |
2797 | {"$v14", RTYPE_VEC | 14}, \ | |
2798 | {"$v15", RTYPE_VEC | 15}, \ | |
2799 | {"$v16", RTYPE_VEC | 16}, \ | |
2800 | {"$v17", RTYPE_VEC | 17}, \ | |
2801 | {"$v18", RTYPE_VEC | 18}, \ | |
2802 | {"$v19", RTYPE_VEC | 19}, \ | |
2803 | {"$v20", RTYPE_VEC | 20}, \ | |
2804 | {"$v21", RTYPE_VEC | 21}, \ | |
2805 | {"$v22", RTYPE_VEC | 22}, \ | |
2806 | {"$v23", RTYPE_VEC | 23}, \ | |
2807 | {"$v24", RTYPE_VEC | 24}, \ | |
2808 | {"$v25", RTYPE_VEC | 25}, \ | |
2809 | {"$v26", RTYPE_VEC | 26}, \ | |
2810 | {"$v27", RTYPE_VEC | 27}, \ | |
2811 | {"$v28", RTYPE_VEC | 28}, \ | |
2812 | {"$v29", RTYPE_VEC | 29}, \ | |
2813 | {"$v30", RTYPE_VEC | 30}, \ | |
2814 | {"$v31", RTYPE_VEC | 31} | |
2815 | ||
14daeee3 RS |
2816 | #define R5900_I_NAMES \ |
2817 | {"$I", RTYPE_R5900_I | 0} | |
2818 | ||
2819 | #define R5900_Q_NAMES \ | |
2820 | {"$Q", RTYPE_R5900_Q | 0} | |
2821 | ||
2822 | #define R5900_R_NAMES \ | |
2823 | {"$R", RTYPE_R5900_R | 0} | |
2824 | ||
2825 | #define R5900_ACC_NAMES \ | |
2826 | {"$ACC", RTYPE_R5900_ACC | 0 } | |
2827 | ||
707bfff6 TS |
2828 | #define MIPS_DSP_ACCUMULATOR_NAMES \ |
2829 | {"$ac0", RTYPE_ACC | 0}, \ | |
2830 | {"$ac1", RTYPE_ACC | 1}, \ | |
2831 | {"$ac2", RTYPE_ACC | 2}, \ | |
2832 | {"$ac3", RTYPE_ACC | 3} | |
2833 | ||
2834 | static const struct regname reg_names[] = { | |
2835 | GENERIC_REGISTER_NUMBERS, | |
2836 | FPU_REGISTER_NAMES, | |
2837 | FPU_CONDITION_CODE_NAMES, | |
2838 | COPROC_CONDITION_CODE_NAMES, | |
2839 | ||
2840 | /* The $txx registers depends on the abi, | |
2841 | these will be added later into the symbol table from | |
3739860c | 2842 | one of the tables below once mips_abi is set after |
707bfff6 TS |
2843 | parsing of arguments from the command line. */ |
2844 | SYMBOLIC_REGISTER_NAMES, | |
2845 | ||
2846 | MIPS16_SPECIAL_REGISTER_NAMES, | |
2847 | MDMX_VECTOR_REGISTER_NAMES, | |
14daeee3 RS |
2848 | R5900_I_NAMES, |
2849 | R5900_Q_NAMES, | |
2850 | R5900_R_NAMES, | |
2851 | R5900_ACC_NAMES, | |
707bfff6 TS |
2852 | MIPS_DSP_ACCUMULATOR_NAMES, |
2853 | {0, 0} | |
2854 | }; | |
2855 | ||
2856 | static const struct regname reg_names_o32[] = { | |
2857 | O32_SYMBOLIC_REGISTER_NAMES, | |
2858 | {0, 0} | |
2859 | }; | |
2860 | ||
2861 | static const struct regname reg_names_n32n64[] = { | |
2862 | N32N64_SYMBOLIC_REGISTER_NAMES, | |
2863 | {0, 0} | |
2864 | }; | |
2865 | ||
a92713e6 RS |
2866 | /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be |
2867 | interpreted as vector registers 0 and 1. If SYMVAL is the value of one | |
2868 | of these register symbols, return the associated vector register, | |
2869 | otherwise return SYMVAL itself. */ | |
df58fc94 | 2870 | |
a92713e6 RS |
2871 | static unsigned int |
2872 | mips_prefer_vec_regno (unsigned int symval) | |
707bfff6 | 2873 | { |
a92713e6 RS |
2874 | if ((symval & -2) == (RTYPE_GP | 2)) |
2875 | return RTYPE_VEC | (symval & 1); | |
2876 | return symval; | |
2877 | } | |
2878 | ||
14daeee3 RS |
2879 | /* Return true if string [S, E) is a valid register name, storing its |
2880 | symbol value in *SYMVAL_PTR if so. */ | |
a92713e6 RS |
2881 | |
2882 | static bfd_boolean | |
14daeee3 | 2883 | mips_parse_register_1 (char *s, char *e, unsigned int *symval_ptr) |
a92713e6 | 2884 | { |
707bfff6 | 2885 | char save_c; |
14daeee3 | 2886 | symbolS *symbol; |
707bfff6 TS |
2887 | |
2888 | /* Terminate name. */ | |
2889 | save_c = *e; | |
2890 | *e = '\0'; | |
2891 | ||
a92713e6 RS |
2892 | /* Look up the name. */ |
2893 | symbol = symbol_find (s); | |
2894 | *e = save_c; | |
2895 | ||
2896 | if (!symbol || S_GET_SEGMENT (symbol) != reg_section) | |
2897 | return FALSE; | |
2898 | ||
14daeee3 RS |
2899 | *symval_ptr = S_GET_VALUE (symbol); |
2900 | return TRUE; | |
2901 | } | |
2902 | ||
2903 | /* Return true if the string at *SPTR is a valid register name. Allow it | |
2904 | to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR | |
2905 | is nonnull. | |
2906 | ||
2907 | When returning true, move *SPTR past the register, store the | |
2908 | register's symbol value in *SYMVAL_PTR and the channel mask in | |
2909 | *CHANNELS_PTR (if nonnull). The symbol value includes the register | |
2910 | number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask | |
2911 | is a 4-bit value of the form XYZW and is 0 if no suffix was given. */ | |
2912 | ||
2913 | static bfd_boolean | |
2914 | mips_parse_register (char **sptr, unsigned int *symval_ptr, | |
2915 | unsigned int *channels_ptr) | |
2916 | { | |
2917 | char *s, *e, *m; | |
2918 | const char *q; | |
2919 | unsigned int channels, symval, bit; | |
2920 | ||
2921 | /* Find end of name. */ | |
2922 | s = e = *sptr; | |
2923 | if (is_name_beginner (*e)) | |
2924 | ++e; | |
2925 | while (is_part_of_name (*e)) | |
2926 | ++e; | |
2927 | ||
2928 | channels = 0; | |
2929 | if (!mips_parse_register_1 (s, e, &symval)) | |
2930 | { | |
2931 | if (!channels_ptr) | |
2932 | return FALSE; | |
2933 | ||
2934 | /* Eat characters from the end of the string that are valid | |
2935 | channel suffixes. The preceding register must be $ACC or | |
2936 | end with a digit, so there is no ambiguity. */ | |
2937 | bit = 1; | |
2938 | m = e; | |
2939 | for (q = "wzyx"; *q; q++, bit <<= 1) | |
2940 | if (m > s && m[-1] == *q) | |
2941 | { | |
2942 | --m; | |
2943 | channels |= bit; | |
2944 | } | |
2945 | ||
2946 | if (channels == 0 | |
2947 | || !mips_parse_register_1 (s, m, &symval) | |
2948 | || (symval & (RTYPE_VI | RTYPE_VF | RTYPE_R5900_ACC)) == 0) | |
2949 | return FALSE; | |
2950 | } | |
2951 | ||
a92713e6 | 2952 | *sptr = e; |
14daeee3 RS |
2953 | *symval_ptr = symval; |
2954 | if (channels_ptr) | |
2955 | *channels_ptr = channels; | |
a92713e6 RS |
2956 | return TRUE; |
2957 | } | |
2958 | ||
2959 | /* Check if SPTR points at a valid register specifier according to TYPES. | |
2960 | If so, then return 1, advance S to consume the specifier and store | |
2961 | the register's number in REGNOP, otherwise return 0. */ | |
2962 | ||
2963 | static int | |
2964 | reg_lookup (char **s, unsigned int types, unsigned int *regnop) | |
2965 | { | |
2966 | unsigned int regno; | |
2967 | ||
14daeee3 | 2968 | if (mips_parse_register (s, ®no, NULL)) |
707bfff6 | 2969 | { |
a92713e6 RS |
2970 | if (types & RTYPE_VEC) |
2971 | regno = mips_prefer_vec_regno (regno); | |
2972 | if (regno & types) | |
2973 | regno &= RNUM_MASK; | |
2974 | else | |
2975 | regno = ~0; | |
707bfff6 | 2976 | } |
a92713e6 | 2977 | else |
707bfff6 | 2978 | { |
a92713e6 | 2979 | if (types & RWARN) |
1661c76c | 2980 | as_warn (_("unrecognized register name `%s'"), *s); |
a92713e6 | 2981 | regno = ~0; |
707bfff6 | 2982 | } |
707bfff6 | 2983 | if (regnop) |
a92713e6 RS |
2984 | *regnop = regno; |
2985 | return regno <= RNUM_MASK; | |
707bfff6 TS |
2986 | } |
2987 | ||
14daeee3 RS |
2988 | /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated |
2989 | mask in *CHANNELS. Return a pointer to the first unconsumed character. */ | |
2990 | ||
2991 | static char * | |
2992 | mips_parse_vu0_channels (char *s, unsigned int *channels) | |
2993 | { | |
2994 | unsigned int i; | |
2995 | ||
2996 | *channels = 0; | |
2997 | for (i = 0; i < 4; i++) | |
2998 | if (*s == "xyzw"[i]) | |
2999 | { | |
3000 | *channels |= 1 << (3 - i); | |
3001 | ++s; | |
3002 | } | |
3003 | return s; | |
3004 | } | |
3005 | ||
a92713e6 RS |
3006 | /* Token types for parsed operand lists. */ |
3007 | enum mips_operand_token_type { | |
3008 | /* A plain register, e.g. $f2. */ | |
3009 | OT_REG, | |
df58fc94 | 3010 | |
14daeee3 RS |
3011 | /* A 4-bit XYZW channel mask. */ |
3012 | OT_CHANNELS, | |
3013 | ||
56d438b1 CF |
3014 | /* A constant vector index, e.g. [1]. */ |
3015 | OT_INTEGER_INDEX, | |
3016 | ||
3017 | /* A register vector index, e.g. [$2]. */ | |
3018 | OT_REG_INDEX, | |
df58fc94 | 3019 | |
a92713e6 RS |
3020 | /* A continuous range of registers, e.g. $s0-$s4. */ |
3021 | OT_REG_RANGE, | |
3022 | ||
3023 | /* A (possibly relocated) expression. */ | |
3024 | OT_INTEGER, | |
3025 | ||
3026 | /* A floating-point value. */ | |
3027 | OT_FLOAT, | |
3028 | ||
3029 | /* A single character. This can be '(', ')' or ',', but '(' only appears | |
3030 | before OT_REGs. */ | |
3031 | OT_CHAR, | |
3032 | ||
14daeee3 RS |
3033 | /* A doubled character, either "--" or "++". */ |
3034 | OT_DOUBLE_CHAR, | |
3035 | ||
a92713e6 RS |
3036 | /* The end of the operand list. */ |
3037 | OT_END | |
3038 | }; | |
3039 | ||
3040 | /* A parsed operand token. */ | |
3041 | struct mips_operand_token | |
3042 | { | |
3043 | /* The type of token. */ | |
3044 | enum mips_operand_token_type type; | |
3045 | union | |
3046 | { | |
56d438b1 | 3047 | /* The register symbol value for an OT_REG or OT_REG_INDEX. */ |
a92713e6 RS |
3048 | unsigned int regno; |
3049 | ||
14daeee3 RS |
3050 | /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */ |
3051 | unsigned int channels; | |
3052 | ||
56d438b1 CF |
3053 | /* The integer value of an OT_INTEGER_INDEX. */ |
3054 | addressT index; | |
a92713e6 RS |
3055 | |
3056 | /* The two register symbol values involved in an OT_REG_RANGE. */ | |
3057 | struct { | |
3058 | unsigned int regno1; | |
3059 | unsigned int regno2; | |
3060 | } reg_range; | |
3061 | ||
3062 | /* The value of an OT_INTEGER. The value is represented as an | |
3063 | expression and the relocation operators that were applied to | |
3064 | that expression. The reloc entries are BFD_RELOC_UNUSED if no | |
3065 | relocation operators were used. */ | |
3066 | struct { | |
3067 | expressionS value; | |
3068 | bfd_reloc_code_real_type relocs[3]; | |
3069 | } integer; | |
3070 | ||
3071 | /* The binary data for an OT_FLOAT constant, and the number of bytes | |
3072 | in the constant. */ | |
3073 | struct { | |
3074 | unsigned char data[8]; | |
3075 | int length; | |
3076 | } flt; | |
3077 | ||
14daeee3 | 3078 | /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */ |
a92713e6 RS |
3079 | char ch; |
3080 | } u; | |
3081 | }; | |
3082 | ||
3083 | /* An obstack used to construct lists of mips_operand_tokens. */ | |
3084 | static struct obstack mips_operand_tokens; | |
3085 | ||
3086 | /* Give TOKEN type TYPE and add it to mips_operand_tokens. */ | |
3087 | ||
3088 | static void | |
3089 | mips_add_token (struct mips_operand_token *token, | |
3090 | enum mips_operand_token_type type) | |
3091 | { | |
3092 | token->type = type; | |
3093 | obstack_grow (&mips_operand_tokens, token, sizeof (*token)); | |
3094 | } | |
3095 | ||
3096 | /* Check whether S is '(' followed by a register name. Add OT_CHAR | |
3097 | and OT_REG tokens for them if so, and return a pointer to the first | |
3098 | unconsumed character. Return null otherwise. */ | |
3099 | ||
3100 | static char * | |
3101 | mips_parse_base_start (char *s) | |
3102 | { | |
3103 | struct mips_operand_token token; | |
14daeee3 RS |
3104 | unsigned int regno, channels; |
3105 | bfd_boolean decrement_p; | |
df58fc94 | 3106 | |
a92713e6 RS |
3107 | if (*s != '(') |
3108 | return 0; | |
3109 | ||
3110 | ++s; | |
3111 | SKIP_SPACE_TABS (s); | |
14daeee3 RS |
3112 | |
3113 | /* Only match "--" as part of a base expression. In other contexts "--X" | |
3114 | is a double negative. */ | |
3115 | decrement_p = (s[0] == '-' && s[1] == '-'); | |
3116 | if (decrement_p) | |
3117 | { | |
3118 | s += 2; | |
3119 | SKIP_SPACE_TABS (s); | |
3120 | } | |
3121 | ||
3122 | /* Allow a channel specifier because that leads to better error messages | |
3123 | than treating something like "$vf0x++" as an expression. */ | |
3124 | if (!mips_parse_register (&s, ®no, &channels)) | |
a92713e6 RS |
3125 | return 0; |
3126 | ||
3127 | token.u.ch = '('; | |
3128 | mips_add_token (&token, OT_CHAR); | |
3129 | ||
14daeee3 RS |
3130 | if (decrement_p) |
3131 | { | |
3132 | token.u.ch = '-'; | |
3133 | mips_add_token (&token, OT_DOUBLE_CHAR); | |
3134 | } | |
3135 | ||
a92713e6 RS |
3136 | token.u.regno = regno; |
3137 | mips_add_token (&token, OT_REG); | |
3138 | ||
14daeee3 RS |
3139 | if (channels) |
3140 | { | |
3141 | token.u.channels = channels; | |
3142 | mips_add_token (&token, OT_CHANNELS); | |
3143 | } | |
3144 | ||
3145 | /* For consistency, only match "++" as part of base expressions too. */ | |
3146 | SKIP_SPACE_TABS (s); | |
3147 | if (s[0] == '+' && s[1] == '+') | |
3148 | { | |
3149 | s += 2; | |
3150 | token.u.ch = '+'; | |
3151 | mips_add_token (&token, OT_DOUBLE_CHAR); | |
3152 | } | |
3153 | ||
a92713e6 RS |
3154 | return s; |
3155 | } | |
3156 | ||
3157 | /* Parse one or more tokens from S. Return a pointer to the first | |
3158 | unconsumed character on success. Return null if an error was found | |
3159 | and store the error text in insn_error. FLOAT_FORMAT is as for | |
3160 | mips_parse_arguments. */ | |
3161 | ||
3162 | static char * | |
3163 | mips_parse_argument_token (char *s, char float_format) | |
3164 | { | |
6d4af3c2 AM |
3165 | char *end, *save_in; |
3166 | const char *err; | |
14daeee3 | 3167 | unsigned int regno1, regno2, channels; |
a92713e6 RS |
3168 | struct mips_operand_token token; |
3169 | ||
3170 | /* First look for "($reg", since we want to treat that as an | |
3171 | OT_CHAR and OT_REG rather than an expression. */ | |
3172 | end = mips_parse_base_start (s); | |
3173 | if (end) | |
3174 | return end; | |
3175 | ||
3176 | /* Handle other characters that end up as OT_CHARs. */ | |
3177 | if (*s == ')' || *s == ',') | |
3178 | { | |
3179 | token.u.ch = *s; | |
3180 | mips_add_token (&token, OT_CHAR); | |
3181 | ++s; | |
3182 | return s; | |
3183 | } | |
3184 | ||
3185 | /* Handle tokens that start with a register. */ | |
14daeee3 | 3186 | if (mips_parse_register (&s, ®no1, &channels)) |
df58fc94 | 3187 | { |
14daeee3 RS |
3188 | if (channels) |
3189 | { | |
3190 | /* A register and a VU0 channel suffix. */ | |
3191 | token.u.regno = regno1; | |
3192 | mips_add_token (&token, OT_REG); | |
3193 | ||
3194 | token.u.channels = channels; | |
3195 | mips_add_token (&token, OT_CHANNELS); | |
3196 | return s; | |
3197 | } | |
3198 | ||
a92713e6 RS |
3199 | SKIP_SPACE_TABS (s); |
3200 | if (*s == '-') | |
df58fc94 | 3201 | { |
a92713e6 RS |
3202 | /* A register range. */ |
3203 | ++s; | |
3204 | SKIP_SPACE_TABS (s); | |
14daeee3 | 3205 | if (!mips_parse_register (&s, ®no2, NULL)) |
a92713e6 | 3206 | { |
1661c76c | 3207 | set_insn_error (0, _("invalid register range")); |
a92713e6 RS |
3208 | return 0; |
3209 | } | |
df58fc94 | 3210 | |
a92713e6 RS |
3211 | token.u.reg_range.regno1 = regno1; |
3212 | token.u.reg_range.regno2 = regno2; | |
3213 | mips_add_token (&token, OT_REG_RANGE); | |
3214 | return s; | |
3215 | } | |
a92713e6 | 3216 | |
56d438b1 CF |
3217 | /* Add the register itself. */ |
3218 | token.u.regno = regno1; | |
3219 | mips_add_token (&token, OT_REG); | |
3220 | ||
3221 | /* Check for a vector index. */ | |
3222 | if (*s == '[') | |
3223 | { | |
a92713e6 RS |
3224 | ++s; |
3225 | SKIP_SPACE_TABS (s); | |
56d438b1 CF |
3226 | if (mips_parse_register (&s, &token.u.regno, NULL)) |
3227 | mips_add_token (&token, OT_REG_INDEX); | |
3228 | else | |
a92713e6 | 3229 | { |
56d438b1 CF |
3230 | expressionS element; |
3231 | ||
3232 | my_getExpression (&element, s); | |
3233 | if (element.X_op != O_constant) | |
3234 | { | |
3235 | set_insn_error (0, _("vector element must be constant")); | |
3236 | return 0; | |
3237 | } | |
3238 | s = expr_end; | |
3239 | token.u.index = element.X_add_number; | |
3240 | mips_add_token (&token, OT_INTEGER_INDEX); | |
a92713e6 | 3241 | } |
a92713e6 RS |
3242 | SKIP_SPACE_TABS (s); |
3243 | if (*s != ']') | |
3244 | { | |
1661c76c | 3245 | set_insn_error (0, _("missing `]'")); |
a92713e6 RS |
3246 | return 0; |
3247 | } | |
3248 | ++s; | |
df58fc94 | 3249 | } |
a92713e6 | 3250 | return s; |
df58fc94 RS |
3251 | } |
3252 | ||
a92713e6 RS |
3253 | if (float_format) |
3254 | { | |
3255 | /* First try to treat expressions as floats. */ | |
3256 | save_in = input_line_pointer; | |
3257 | input_line_pointer = s; | |
3258 | err = md_atof (float_format, (char *) token.u.flt.data, | |
3259 | &token.u.flt.length); | |
3260 | end = input_line_pointer; | |
3261 | input_line_pointer = save_in; | |
3262 | if (err && *err) | |
3263 | { | |
e3de51ce | 3264 | set_insn_error (0, err); |
a92713e6 RS |
3265 | return 0; |
3266 | } | |
3267 | if (s != end) | |
3268 | { | |
3269 | mips_add_token (&token, OT_FLOAT); | |
3270 | return end; | |
3271 | } | |
3272 | } | |
3273 | ||
3274 | /* Treat everything else as an integer expression. */ | |
3275 | token.u.integer.relocs[0] = BFD_RELOC_UNUSED; | |
3276 | token.u.integer.relocs[1] = BFD_RELOC_UNUSED; | |
3277 | token.u.integer.relocs[2] = BFD_RELOC_UNUSED; | |
3278 | my_getSmallExpression (&token.u.integer.value, token.u.integer.relocs, s); | |
3279 | s = expr_end; | |
3280 | mips_add_token (&token, OT_INTEGER); | |
3281 | return s; | |
3282 | } | |
3283 | ||
3284 | /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f' | |
3285 | if expressions should be treated as 32-bit floating-point constants, | |
3286 | 'd' if they should be treated as 64-bit floating-point constants, | |
3287 | or 0 if they should be treated as integer expressions (the usual case). | |
3288 | ||
3289 | Return a list of tokens on success, otherwise return 0. The caller | |
3290 | must obstack_free the list after use. */ | |
3291 | ||
3292 | static struct mips_operand_token * | |
3293 | mips_parse_arguments (char *s, char float_format) | |
3294 | { | |
3295 | struct mips_operand_token token; | |
3296 | ||
3297 | SKIP_SPACE_TABS (s); | |
3298 | while (*s) | |
3299 | { | |
3300 | s = mips_parse_argument_token (s, float_format); | |
3301 | if (!s) | |
3302 | { | |
3303 | obstack_free (&mips_operand_tokens, | |
3304 | obstack_finish (&mips_operand_tokens)); | |
3305 | return 0; | |
3306 | } | |
3307 | SKIP_SPACE_TABS (s); | |
3308 | } | |
3309 | mips_add_token (&token, OT_END); | |
3310 | return (struct mips_operand_token *) obstack_finish (&mips_operand_tokens); | |
df58fc94 RS |
3311 | } |
3312 | ||
d301a56b RS |
3313 | /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE |
3314 | and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */ | |
037b32b9 AN |
3315 | |
3316 | static bfd_boolean | |
f79e2745 | 3317 | is_opcode_valid (const struct mips_opcode *mo) |
037b32b9 AN |
3318 | { |
3319 | int isa = mips_opts.isa; | |
846ef2d0 | 3320 | int ase = mips_opts.ase; |
037b32b9 | 3321 | int fp_s, fp_d; |
c6278170 | 3322 | unsigned int i; |
037b32b9 | 3323 | |
be0fcbee | 3324 | if (ISA_HAS_64BIT_REGS (isa)) |
c6278170 RS |
3325 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) |
3326 | if ((ase & mips_ases[i].flags) == mips_ases[i].flags) | |
3327 | ase |= mips_ases[i].flags64; | |
037b32b9 | 3328 | |
d301a56b | 3329 | if (!opcode_is_member (mo, isa, ase, mips_opts.arch)) |
037b32b9 AN |
3330 | return FALSE; |
3331 | ||
3332 | /* Check whether the instruction or macro requires single-precision or | |
3333 | double-precision floating-point support. Note that this information is | |
3334 | stored differently in the opcode table for insns and macros. */ | |
3335 | if (mo->pinfo == INSN_MACRO) | |
3336 | { | |
3337 | fp_s = mo->pinfo2 & INSN2_M_FP_S; | |
3338 | fp_d = mo->pinfo2 & INSN2_M_FP_D; | |
3339 | } | |
3340 | else | |
3341 | { | |
3342 | fp_s = mo->pinfo & FP_S; | |
3343 | fp_d = mo->pinfo & FP_D; | |
3344 | } | |
3345 | ||
3346 | if (fp_d && (mips_opts.soft_float || mips_opts.single_float)) | |
3347 | return FALSE; | |
3348 | ||
3349 | if (fp_s && mips_opts.soft_float) | |
3350 | return FALSE; | |
3351 | ||
3352 | return TRUE; | |
3353 | } | |
3354 | ||
3355 | /* Return TRUE if the MIPS16 opcode MO is valid on the currently | |
3356 | selected ISA and architecture. */ | |
3357 | ||
3358 | static bfd_boolean | |
3359 | is_opcode_valid_16 (const struct mips_opcode *mo) | |
3360 | { | |
25499ac7 MR |
3361 | int isa = mips_opts.isa; |
3362 | int ase = mips_opts.ase; | |
3363 | unsigned int i; | |
3364 | ||
3365 | if (ISA_HAS_64BIT_REGS (isa)) | |
3366 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
3367 | if ((ase & mips_ases[i].flags) == mips_ases[i].flags) | |
3368 | ase |= mips_ases[i].flags64; | |
3369 | ||
3370 | return opcode_is_member (mo, isa, ase, mips_opts.arch); | |
037b32b9 AN |
3371 | } |
3372 | ||
df58fc94 | 3373 | /* Return TRUE if the size of the microMIPS opcode MO matches one |
7fd53920 MR |
3374 | explicitly requested. Always TRUE in the standard MIPS mode. |
3375 | Use is_size_valid_16 for MIPS16 opcodes. */ | |
df58fc94 RS |
3376 | |
3377 | static bfd_boolean | |
3378 | is_size_valid (const struct mips_opcode *mo) | |
3379 | { | |
3380 | if (!mips_opts.micromips) | |
3381 | return TRUE; | |
3382 | ||
833794fc MR |
3383 | if (mips_opts.insn32) |
3384 | { | |
3385 | if (mo->pinfo != INSN_MACRO && micromips_insn_length (mo) != 4) | |
3386 | return FALSE; | |
3387 | if ((mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0) | |
3388 | return FALSE; | |
3389 | } | |
df58fc94 RS |
3390 | if (!forced_insn_length) |
3391 | return TRUE; | |
3392 | if (mo->pinfo == INSN_MACRO) | |
3393 | return FALSE; | |
3394 | return forced_insn_length == micromips_insn_length (mo); | |
3395 | } | |
3396 | ||
7fd53920 MR |
3397 | /* Return TRUE if the size of the MIPS16 opcode MO matches one |
3398 | explicitly requested. */ | |
3399 | ||
3400 | static bfd_boolean | |
3401 | is_size_valid_16 (const struct mips_opcode *mo) | |
3402 | { | |
3403 | if (!forced_insn_length) | |
3404 | return TRUE; | |
3405 | if (mo->pinfo == INSN_MACRO) | |
3406 | return FALSE; | |
3407 | if (forced_insn_length == 2 && mips_opcode_32bit_p (mo)) | |
3408 | return FALSE; | |
0674ee5d MR |
3409 | if (forced_insn_length == 4 && (mo->pinfo2 & INSN2_SHORT_ONLY)) |
3410 | return FALSE; | |
7fd53920 MR |
3411 | return TRUE; |
3412 | } | |
3413 | ||
df58fc94 | 3414 | /* Return TRUE if the microMIPS opcode MO is valid for the delay slot |
e64af278 MR |
3415 | of the preceding instruction. Always TRUE in the standard MIPS mode. |
3416 | ||
3417 | We don't accept macros in 16-bit delay slots to avoid a case where | |
3418 | a macro expansion fails because it relies on a preceding 32-bit real | |
3419 | instruction to have matched and does not handle the operands correctly. | |
3420 | The only macros that may expand to 16-bit instructions are JAL that | |
3421 | cannot be placed in a delay slot anyway, and corner cases of BALIGN | |
3422 | and BGT (that likewise cannot be placed in a delay slot) that decay to | |
3423 | a NOP. In all these cases the macros precede any corresponding real | |
3424 | instruction definitions in the opcode table, so they will match in the | |
3425 | second pass where the size of the delay slot is ignored and therefore | |
3426 | produce correct code. */ | |
df58fc94 RS |
3427 | |
3428 | static bfd_boolean | |
3429 | is_delay_slot_valid (const struct mips_opcode *mo) | |
3430 | { | |
3431 | if (!mips_opts.micromips) | |
3432 | return TRUE; | |
3433 | ||
3434 | if (mo->pinfo == INSN_MACRO) | |
c06dec14 | 3435 | return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0; |
df58fc94 RS |
3436 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 |
3437 | && micromips_insn_length (mo) != 4) | |
3438 | return FALSE; | |
3439 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 | |
3440 | && micromips_insn_length (mo) != 2) | |
3441 | return FALSE; | |
3442 | ||
3443 | return TRUE; | |
3444 | } | |
3445 | ||
fc76e730 RS |
3446 | /* For consistency checking, verify that all bits of OPCODE are specified |
3447 | either by the match/mask part of the instruction definition, or by the | |
3448 | operand list. Also build up a list of operands in OPERANDS. | |
3449 | ||
3450 | INSN_BITS says which bits of the instruction are significant. | |
3451 | If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND | |
3452 | provides the mips_operand description of each operand. DECODE_OPERAND | |
3453 | is null for MIPS16 instructions. */ | |
ab902481 RS |
3454 | |
3455 | static int | |
3456 | validate_mips_insn (const struct mips_opcode *opcode, | |
3457 | unsigned long insn_bits, | |
fc76e730 RS |
3458 | const struct mips_operand *(*decode_operand) (const char *), |
3459 | struct mips_operand_array *operands) | |
ab902481 RS |
3460 | { |
3461 | const char *s; | |
fc76e730 | 3462 | unsigned long used_bits, doubled, undefined, opno, mask; |
ab902481 RS |
3463 | const struct mips_operand *operand; |
3464 | ||
fc76e730 RS |
3465 | mask = (opcode->pinfo == INSN_MACRO ? 0 : opcode->mask); |
3466 | if ((mask & opcode->match) != opcode->match) | |
ab902481 RS |
3467 | { |
3468 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
3469 | opcode->name, opcode->args); | |
3470 | return 0; | |
3471 | } | |
3472 | used_bits = 0; | |
fc76e730 | 3473 | opno = 0; |
14daeee3 RS |
3474 | if (opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) |
3475 | used_bits = mips_insert_operand (&mips_vu0_channel_mask, used_bits, -1); | |
ab902481 RS |
3476 | for (s = opcode->args; *s; ++s) |
3477 | switch (*s) | |
3478 | { | |
3479 | case ',': | |
3480 | case '(': | |
3481 | case ')': | |
3482 | break; | |
3483 | ||
14daeee3 RS |
3484 | case '#': |
3485 | s++; | |
3486 | break; | |
3487 | ||
ab902481 | 3488 | default: |
fc76e730 | 3489 | if (!decode_operand) |
7fd53920 | 3490 | operand = decode_mips16_operand (*s, mips_opcode_32bit_p (opcode)); |
fc76e730 RS |
3491 | else |
3492 | operand = decode_operand (s); | |
3493 | if (!operand && opcode->pinfo != INSN_MACRO) | |
ab902481 RS |
3494 | { |
3495 | as_bad (_("internal: unknown operand type: %s %s"), | |
3496 | opcode->name, opcode->args); | |
3497 | return 0; | |
3498 | } | |
fc76e730 RS |
3499 | gas_assert (opno < MAX_OPERANDS); |
3500 | operands->operand[opno] = operand; | |
25499ac7 MR |
3501 | if (!decode_operand && operand |
3502 | && operand->type == OP_INT && operand->lsb == 0 | |
3503 | && mips_opcode_32bit_p (opcode)) | |
3504 | used_bits |= mips16_immed_extend (-1, operand->size); | |
3505 | else if (operand && operand->type != OP_VU0_MATCH_SUFFIX) | |
fc76e730 | 3506 | { |
14daeee3 | 3507 | used_bits = mips_insert_operand (operand, used_bits, -1); |
fc76e730 RS |
3508 | if (operand->type == OP_MDMX_IMM_REG) |
3509 | /* Bit 5 is the format selector (OB vs QH). The opcode table | |
3510 | has separate entries for each format. */ | |
3511 | used_bits &= ~(1 << (operand->lsb + 5)); | |
3512 | if (operand->type == OP_ENTRY_EXIT_LIST) | |
3513 | used_bits &= ~(mask & 0x700); | |
38bf472a MR |
3514 | /* interAptiv MR2 SAVE/RESTORE instructions have a discontiguous |
3515 | operand field that cannot be fully described with LSB/SIZE. */ | |
3516 | if (operand->type == OP_SAVE_RESTORE_LIST && operand->lsb == 6) | |
3517 | used_bits &= ~0x6000; | |
fc76e730 | 3518 | } |
ab902481 | 3519 | /* Skip prefix characters. */ |
7361da2c | 3520 | if (decode_operand && (*s == '+' || *s == 'm' || *s == '-')) |
ab902481 | 3521 | ++s; |
fc76e730 | 3522 | opno += 1; |
ab902481 RS |
3523 | break; |
3524 | } | |
fc76e730 | 3525 | doubled = used_bits & mask & insn_bits; |
ab902481 RS |
3526 | if (doubled) |
3527 | { | |
3528 | as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):" | |
3529 | " %s %s"), doubled, opcode->name, opcode->args); | |
3530 | return 0; | |
3531 | } | |
fc76e730 | 3532 | used_bits |= mask; |
ab902481 | 3533 | undefined = ~used_bits & insn_bits; |
fc76e730 | 3534 | if (opcode->pinfo != INSN_MACRO && undefined) |
ab902481 RS |
3535 | { |
3536 | as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"), | |
3537 | undefined, opcode->name, opcode->args); | |
3538 | return 0; | |
3539 | } | |
3540 | used_bits &= ~insn_bits; | |
3541 | if (used_bits) | |
3542 | { | |
3543 | as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"), | |
3544 | used_bits, opcode->name, opcode->args); | |
3545 | return 0; | |
3546 | } | |
3547 | return 1; | |
3548 | } | |
3549 | ||
fc76e730 RS |
3550 | /* The MIPS16 version of validate_mips_insn. */ |
3551 | ||
3552 | static int | |
3553 | validate_mips16_insn (const struct mips_opcode *opcode, | |
3554 | struct mips_operand_array *operands) | |
3555 | { | |
7fd53920 | 3556 | unsigned long insn_bits = mips_opcode_32bit_p (opcode) ? 0xffffffff : 0xffff; |
fc76e730 | 3557 | |
7fd53920 | 3558 | return validate_mips_insn (opcode, insn_bits, 0, operands); |
fc76e730 RS |
3559 | } |
3560 | ||
ab902481 RS |
3561 | /* The microMIPS version of validate_mips_insn. */ |
3562 | ||
3563 | static int | |
fc76e730 RS |
3564 | validate_micromips_insn (const struct mips_opcode *opc, |
3565 | struct mips_operand_array *operands) | |
ab902481 RS |
3566 | { |
3567 | unsigned long insn_bits; | |
3568 | unsigned long major; | |
3569 | unsigned int length; | |
3570 | ||
fc76e730 RS |
3571 | if (opc->pinfo == INSN_MACRO) |
3572 | return validate_mips_insn (opc, 0xffffffff, decode_micromips_operand, | |
3573 | operands); | |
3574 | ||
ab902481 RS |
3575 | length = micromips_insn_length (opc); |
3576 | if (length != 2 && length != 4) | |
3577 | { | |
1661c76c | 3578 | as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): " |
ab902481 RS |
3579 | "%s %s"), length, opc->name, opc->args); |
3580 | return 0; | |
3581 | } | |
3582 | major = opc->match >> (10 + 8 * (length - 2)); | |
3583 | if ((length == 2 && (major & 7) != 1 && (major & 6) != 2) | |
3584 | || (length == 4 && (major & 7) != 0 && (major & 4) != 4)) | |
3585 | { | |
1661c76c | 3586 | as_bad (_("internal error: bad microMIPS opcode " |
ab902481 RS |
3587 | "(opcode/length mismatch): %s %s"), opc->name, opc->args); |
3588 | return 0; | |
3589 | } | |
3590 | ||
3591 | /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */ | |
3592 | insn_bits = 1 << 4 * length; | |
3593 | insn_bits <<= 4 * length; | |
3594 | insn_bits -= 1; | |
fc76e730 RS |
3595 | return validate_mips_insn (opc, insn_bits, decode_micromips_operand, |
3596 | operands); | |
ab902481 RS |
3597 | } |
3598 | ||
707bfff6 TS |
3599 | /* This function is called once, at assembler startup time. It should set up |
3600 | all the tables, etc. that the MD part of the assembler will need. */ | |
156c2f8b | 3601 | |
252b5132 | 3602 | void |
17a2f251 | 3603 | md_begin (void) |
252b5132 | 3604 | { |
3994f87e | 3605 | const char *retval = NULL; |
156c2f8b | 3606 | int i = 0; |
252b5132 | 3607 | int broken = 0; |
1f25f5d3 | 3608 | |
0a44bf69 RS |
3609 | if (mips_pic != NO_PIC) |
3610 | { | |
3611 | if (g_switch_seen && g_switch_value != 0) | |
3612 | as_bad (_("-G may not be used in position-independent code")); | |
3613 | g_switch_value = 0; | |
3614 | } | |
00acd688 CM |
3615 | else if (mips_abicalls) |
3616 | { | |
3617 | if (g_switch_seen && g_switch_value != 0) | |
3618 | as_bad (_("-G may not be used with abicalls")); | |
3619 | g_switch_value = 0; | |
3620 | } | |
0a44bf69 | 3621 | |
0b35dfee | 3622 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch)) |
1661c76c | 3623 | as_warn (_("could not set architecture and machine")); |
252b5132 | 3624 | |
252b5132 RH |
3625 | op_hash = hash_new (); |
3626 | ||
fc76e730 | 3627 | mips_operands = XCNEWVEC (struct mips_operand_array, NUMOPCODES); |
252b5132 RH |
3628 | for (i = 0; i < NUMOPCODES;) |
3629 | { | |
3630 | const char *name = mips_opcodes[i].name; | |
3631 | ||
17a2f251 | 3632 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
3633 | if (retval != NULL) |
3634 | { | |
3635 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
3636 | mips_opcodes[i].name, retval); | |
3637 | /* Probably a memory allocation problem? Give up now. */ | |
1661c76c | 3638 | as_fatal (_("broken assembler, no assembly attempted")); |
252b5132 RH |
3639 | } |
3640 | do | |
3641 | { | |
fc76e730 RS |
3642 | if (!validate_mips_insn (&mips_opcodes[i], 0xffffffff, |
3643 | decode_mips_operand, &mips_operands[i])) | |
3644 | broken = 1; | |
3645 | if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) | |
252b5132 | 3646 | { |
fc76e730 RS |
3647 | create_insn (&nop_insn, mips_opcodes + i); |
3648 | if (mips_fix_loongson2f_nop) | |
3649 | nop_insn.insn_opcode = LOONGSON2F_NOP_INSN; | |
3650 | nop_insn.fixed_p = 1; | |
252b5132 RH |
3651 | } |
3652 | ++i; | |
3653 | } | |
3654 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
3655 | } | |
3656 | ||
3657 | mips16_op_hash = hash_new (); | |
fc76e730 RS |
3658 | mips16_operands = XCNEWVEC (struct mips_operand_array, |
3659 | bfd_mips16_num_opcodes); | |
252b5132 RH |
3660 | |
3661 | i = 0; | |
3662 | while (i < bfd_mips16_num_opcodes) | |
3663 | { | |
3664 | const char *name = mips16_opcodes[i].name; | |
3665 | ||
17a2f251 | 3666 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
3667 | if (retval != NULL) |
3668 | as_fatal (_("internal: can't hash `%s': %s"), | |
3669 | mips16_opcodes[i].name, retval); | |
3670 | do | |
3671 | { | |
fc76e730 RS |
3672 | if (!validate_mips16_insn (&mips16_opcodes[i], &mips16_operands[i])) |
3673 | broken = 1; | |
1e915849 RS |
3674 | if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
3675 | { | |
3676 | create_insn (&mips16_nop_insn, mips16_opcodes + i); | |
3677 | mips16_nop_insn.fixed_p = 1; | |
3678 | } | |
252b5132 RH |
3679 | ++i; |
3680 | } | |
3681 | while (i < bfd_mips16_num_opcodes | |
3682 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
3683 | } | |
3684 | ||
df58fc94 | 3685 | micromips_op_hash = hash_new (); |
fc76e730 RS |
3686 | micromips_operands = XCNEWVEC (struct mips_operand_array, |
3687 | bfd_micromips_num_opcodes); | |
df58fc94 RS |
3688 | |
3689 | i = 0; | |
3690 | while (i < bfd_micromips_num_opcodes) | |
3691 | { | |
3692 | const char *name = micromips_opcodes[i].name; | |
3693 | ||
3694 | retval = hash_insert (micromips_op_hash, name, | |
3695 | (void *) µmips_opcodes[i]); | |
3696 | if (retval != NULL) | |
3697 | as_fatal (_("internal: can't hash `%s': %s"), | |
3698 | micromips_opcodes[i].name, retval); | |
3699 | do | |
fc76e730 RS |
3700 | { |
3701 | struct mips_cl_insn *micromips_nop_insn; | |
3702 | ||
3703 | if (!validate_micromips_insn (µmips_opcodes[i], | |
3704 | µmips_operands[i])) | |
3705 | broken = 1; | |
3706 | ||
3707 | if (micromips_opcodes[i].pinfo != INSN_MACRO) | |
3708 | { | |
3709 | if (micromips_insn_length (micromips_opcodes + i) == 2) | |
3710 | micromips_nop_insn = µmips_nop16_insn; | |
3711 | else if (micromips_insn_length (micromips_opcodes + i) == 4) | |
3712 | micromips_nop_insn = µmips_nop32_insn; | |
3713 | else | |
3714 | continue; | |
3715 | ||
3716 | if (micromips_nop_insn->insn_mo == NULL | |
3717 | && strcmp (name, "nop") == 0) | |
3718 | { | |
3719 | create_insn (micromips_nop_insn, micromips_opcodes + i); | |
3720 | micromips_nop_insn->fixed_p = 1; | |
3721 | } | |
3722 | } | |
3723 | } | |
df58fc94 RS |
3724 | while (++i < bfd_micromips_num_opcodes |
3725 | && strcmp (micromips_opcodes[i].name, name) == 0); | |
3726 | } | |
3727 | ||
252b5132 | 3728 | if (broken) |
1661c76c | 3729 | as_fatal (_("broken assembler, no assembly attempted")); |
252b5132 RH |
3730 | |
3731 | /* We add all the general register names to the symbol table. This | |
3732 | helps us detect invalid uses of them. */ | |
3739860c | 3733 | for (i = 0; reg_names[i].name; i++) |
707bfff6 | 3734 | symbol_table_insert (symbol_new (reg_names[i].name, reg_section, |
8fc4ee9b | 3735 | reg_names[i].num, /* & RNUM_MASK, */ |
707bfff6 TS |
3736 | &zero_address_frag)); |
3737 | if (HAVE_NEWABI) | |
3739860c | 3738 | for (i = 0; reg_names_n32n64[i].name; i++) |
707bfff6 | 3739 | symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section, |
8fc4ee9b | 3740 | reg_names_n32n64[i].num, /* & RNUM_MASK, */ |
252b5132 | 3741 | &zero_address_frag)); |
707bfff6 | 3742 | else |
3739860c | 3743 | for (i = 0; reg_names_o32[i].name; i++) |
707bfff6 | 3744 | symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section, |
8fc4ee9b | 3745 | reg_names_o32[i].num, /* & RNUM_MASK, */ |
6047c971 | 3746 | &zero_address_frag)); |
6047c971 | 3747 | |
14daeee3 RS |
3748 | for (i = 0; i < 32; i++) |
3749 | { | |
92fce9bd | 3750 | char regname[6]; |
14daeee3 RS |
3751 | |
3752 | /* R5900 VU0 floating-point register. */ | |
92fce9bd | 3753 | sprintf (regname, "$vf%d", i); |
14daeee3 RS |
3754 | symbol_table_insert (symbol_new (regname, reg_section, |
3755 | RTYPE_VF | i, &zero_address_frag)); | |
3756 | ||
3757 | /* R5900 VU0 integer register. */ | |
92fce9bd | 3758 | sprintf (regname, "$vi%d", i); |
14daeee3 RS |
3759 | symbol_table_insert (symbol_new (regname, reg_section, |
3760 | RTYPE_VI | i, &zero_address_frag)); | |
3761 | ||
56d438b1 | 3762 | /* MSA register. */ |
92fce9bd | 3763 | sprintf (regname, "$w%d", i); |
56d438b1 CF |
3764 | symbol_table_insert (symbol_new (regname, reg_section, |
3765 | RTYPE_MSA | i, &zero_address_frag)); | |
14daeee3 RS |
3766 | } |
3767 | ||
a92713e6 RS |
3768 | obstack_init (&mips_operand_tokens); |
3769 | ||
7d10b47d | 3770 | mips_no_prev_insn (); |
252b5132 RH |
3771 | |
3772 | mips_gprmask = 0; | |
3773 | mips_cprmask[0] = 0; | |
3774 | mips_cprmask[1] = 0; | |
3775 | mips_cprmask[2] = 0; | |
3776 | mips_cprmask[3] = 0; | |
3777 | ||
3778 | /* set the default alignment for the text section (2**2) */ | |
3779 | record_alignment (text_section, 2); | |
3780 | ||
4d0d148d | 3781 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 | 3782 | |
f3ded42a RS |
3783 | /* On a native system other than VxWorks, sections must be aligned |
3784 | to 16 byte boundaries. When configured for an embedded ELF | |
3785 | target, we don't bother. */ | |
3786 | if (strncmp (TARGET_OS, "elf", 3) != 0 | |
3787 | && strncmp (TARGET_OS, "vxworks", 7) != 0) | |
252b5132 | 3788 | { |
f3ded42a RS |
3789 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); |
3790 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
3791 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
3792 | } | |
252b5132 | 3793 | |
f3ded42a RS |
3794 | /* Create a .reginfo section for register masks and a .mdebug |
3795 | section for debugging information. */ | |
3796 | { | |
3797 | segT seg; | |
3798 | subsegT subseg; | |
3799 | flagword flags; | |
3800 | segT sec; | |
3801 | ||
3802 | seg = now_seg; | |
3803 | subseg = now_subseg; | |
3804 | ||
3805 | /* The ABI says this section should be loaded so that the | |
3806 | running program can access it. However, we don't load it | |
3807 | if we are configured for an embedded target */ | |
3808 | flags = SEC_READONLY | SEC_DATA; | |
3809 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
3810 | flags |= SEC_ALLOC | SEC_LOAD; | |
3811 | ||
3812 | if (mips_abi != N64_ABI) | |
252b5132 | 3813 | { |
f3ded42a | 3814 | sec = subseg_new (".reginfo", (subsegT) 0); |
bdaaa2e1 | 3815 | |
f3ded42a RS |
3816 | bfd_set_section_flags (stdoutput, sec, flags); |
3817 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
252b5132 | 3818 | |
f3ded42a RS |
3819 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
3820 | } | |
3821 | else | |
3822 | { | |
3823 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
3824 | .reginfo section. */ | |
3825 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
3826 | bfd_set_section_flags (stdoutput, sec, flags); | |
3827 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 | 3828 | |
f3ded42a RS |
3829 | /* Set up the option header. */ |
3830 | { | |
3831 | Elf_Internal_Options opthdr; | |
3832 | char *f; | |
3833 | ||
3834 | opthdr.kind = ODK_REGINFO; | |
3835 | opthdr.size = (sizeof (Elf_External_Options) | |
3836 | + sizeof (Elf64_External_RegInfo)); | |
3837 | opthdr.section = 0; | |
3838 | opthdr.info = 0; | |
3839 | f = frag_more (sizeof (Elf_External_Options)); | |
3840 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
3841 | (Elf_External_Options *) f); | |
3842 | ||
3843 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
3844 | } | |
3845 | } | |
252b5132 | 3846 | |
351cdf24 MF |
3847 | sec = subseg_new (".MIPS.abiflags", (subsegT) 0); |
3848 | bfd_set_section_flags (stdoutput, sec, | |
3849 | SEC_READONLY | SEC_DATA | SEC_ALLOC | SEC_LOAD); | |
3850 | bfd_set_section_alignment (stdoutput, sec, 3); | |
3851 | mips_flags_frag = frag_more (sizeof (Elf_External_ABIFlags_v0)); | |
3852 | ||
f3ded42a RS |
3853 | if (ECOFF_DEBUGGING) |
3854 | { | |
3855 | sec = subseg_new (".mdebug", (subsegT) 0); | |
3856 | (void) bfd_set_section_flags (stdoutput, sec, | |
3857 | SEC_HAS_CONTENTS | SEC_READONLY); | |
3858 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
252b5132 | 3859 | } |
f3ded42a RS |
3860 | else if (mips_flag_pdr) |
3861 | { | |
3862 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
3863 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
3864 | SEC_READONLY | SEC_RELOC | |
3865 | | SEC_DEBUGGING); | |
3866 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
3867 | } | |
3868 | ||
3869 | subseg_set (seg, subseg); | |
3870 | } | |
252b5132 | 3871 | |
71400594 RS |
3872 | if (mips_fix_vr4120) |
3873 | init_vr4120_conflicts (); | |
252b5132 RH |
3874 | } |
3875 | ||
351cdf24 MF |
3876 | static inline void |
3877 | fpabi_incompatible_with (int fpabi, const char *what) | |
3878 | { | |
3879 | as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"), | |
3880 | Tag_GNU_MIPS_ABI_FP, fpabi, what); | |
3881 | } | |
3882 | ||
3883 | static inline void | |
3884 | fpabi_requires (int fpabi, const char *what) | |
3885 | { | |
3886 | as_warn (_(".gnu_attribute %d,%d requires `%s'"), | |
3887 | Tag_GNU_MIPS_ABI_FP, fpabi, what); | |
3888 | } | |
3889 | ||
3890 | /* Check -mabi and register sizes against the specified FP ABI. */ | |
3891 | static void | |
3892 | check_fpabi (int fpabi) | |
3893 | { | |
351cdf24 MF |
3894 | switch (fpabi) |
3895 | { | |
3896 | case Val_GNU_MIPS_ABI_FP_DOUBLE: | |
ea79f94a MF |
3897 | if (file_mips_opts.soft_float) |
3898 | fpabi_incompatible_with (fpabi, "softfloat"); | |
3899 | else if (file_mips_opts.single_float) | |
3900 | fpabi_incompatible_with (fpabi, "singlefloat"); | |
351cdf24 MF |
3901 | if (file_mips_opts.gp == 64 && file_mips_opts.fp == 32) |
3902 | fpabi_incompatible_with (fpabi, "gp=64 fp=32"); | |
3903 | else if (file_mips_opts.gp == 32 && file_mips_opts.fp == 64) | |
3904 | fpabi_incompatible_with (fpabi, "gp=32 fp=64"); | |
351cdf24 MF |
3905 | break; |
3906 | ||
3907 | case Val_GNU_MIPS_ABI_FP_XX: | |
3908 | if (mips_abi != O32_ABI) | |
3909 | fpabi_requires (fpabi, "-mabi=32"); | |
ea79f94a MF |
3910 | else if (file_mips_opts.soft_float) |
3911 | fpabi_incompatible_with (fpabi, "softfloat"); | |
3912 | else if (file_mips_opts.single_float) | |
3913 | fpabi_incompatible_with (fpabi, "singlefloat"); | |
351cdf24 MF |
3914 | else if (file_mips_opts.fp != 0) |
3915 | fpabi_requires (fpabi, "fp=xx"); | |
351cdf24 MF |
3916 | break; |
3917 | ||
3918 | case Val_GNU_MIPS_ABI_FP_64A: | |
3919 | case Val_GNU_MIPS_ABI_FP_64: | |
3920 | if (mips_abi != O32_ABI) | |
3921 | fpabi_requires (fpabi, "-mabi=32"); | |
ea79f94a MF |
3922 | else if (file_mips_opts.soft_float) |
3923 | fpabi_incompatible_with (fpabi, "softfloat"); | |
3924 | else if (file_mips_opts.single_float) | |
3925 | fpabi_incompatible_with (fpabi, "singlefloat"); | |
351cdf24 MF |
3926 | else if (file_mips_opts.fp != 64) |
3927 | fpabi_requires (fpabi, "fp=64"); | |
3928 | else if (fpabi == Val_GNU_MIPS_ABI_FP_64 && !file_mips_opts.oddspreg) | |
3929 | fpabi_incompatible_with (fpabi, "nooddspreg"); | |
3930 | else if (fpabi == Val_GNU_MIPS_ABI_FP_64A && file_mips_opts.oddspreg) | |
3931 | fpabi_requires (fpabi, "nooddspreg"); | |
351cdf24 MF |
3932 | break; |
3933 | ||
3934 | case Val_GNU_MIPS_ABI_FP_SINGLE: | |
3935 | if (file_mips_opts.soft_float) | |
3936 | fpabi_incompatible_with (fpabi, "softfloat"); | |
3937 | else if (!file_mips_opts.single_float) | |
3938 | fpabi_requires (fpabi, "singlefloat"); | |
3939 | break; | |
3940 | ||
3941 | case Val_GNU_MIPS_ABI_FP_SOFT: | |
3942 | if (!file_mips_opts.soft_float) | |
3943 | fpabi_requires (fpabi, "softfloat"); | |
3944 | break; | |
3945 | ||
3946 | case Val_GNU_MIPS_ABI_FP_OLD_64: | |
3947 | as_warn (_(".gnu_attribute %d,%d is no longer supported"), | |
3948 | Tag_GNU_MIPS_ABI_FP, fpabi); | |
3949 | break; | |
3950 | ||
3350cc01 CM |
3951 | case Val_GNU_MIPS_ABI_FP_NAN2008: |
3952 | /* Silently ignore compatibility value. */ | |
3953 | break; | |
3954 | ||
351cdf24 MF |
3955 | default: |
3956 | as_warn (_(".gnu_attribute %d,%d is not a recognized" | |
3957 | " floating-point ABI"), Tag_GNU_MIPS_ABI_FP, fpabi); | |
3958 | break; | |
3959 | } | |
351cdf24 MF |
3960 | } |
3961 | ||
919731af | 3962 | /* Perform consistency checks on the current options. */ |
3963 | ||
3964 | static void | |
3965 | mips_check_options (struct mips_set_options *opts, bfd_boolean abi_checks) | |
3966 | { | |
3967 | /* Check the size of integer registers agrees with the ABI and ISA. */ | |
3968 | if (opts->gp == 64 && !ISA_HAS_64BIT_REGS (opts->isa)) | |
3969 | as_bad (_("`gp=64' used with a 32-bit processor")); | |
3970 | else if (abi_checks | |
3971 | && opts->gp == 32 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
3972 | as_bad (_("`gp=32' used with a 64-bit ABI")); | |
3973 | else if (abi_checks | |
3974 | && opts->gp == 64 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
3975 | as_bad (_("`gp=64' used with a 32-bit ABI")); | |
3976 | ||
3977 | /* Check the size of the float registers agrees with the ABI and ISA. */ | |
3978 | switch (opts->fp) | |
3979 | { | |
351cdf24 MF |
3980 | case 0: |
3981 | if (!CPU_HAS_LDC1_SDC1 (opts->arch)) | |
3982 | as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions")); | |
3983 | else if (opts->single_float == 1) | |
3984 | as_bad (_("`fp=xx' cannot be used with `singlefloat'")); | |
3985 | break; | |
919731af | 3986 | case 64: |
3987 | if (!ISA_HAS_64BIT_FPRS (opts->isa)) | |
3988 | as_bad (_("`fp=64' used with a 32-bit fpu")); | |
3989 | else if (abi_checks | |
3990 | && ABI_NEEDS_32BIT_REGS (mips_abi) | |
3991 | && !ISA_HAS_MXHC1 (opts->isa)) | |
3992 | as_warn (_("`fp=64' used with a 32-bit ABI")); | |
3993 | break; | |
3994 | case 32: | |
3995 | if (abi_checks | |
3996 | && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
3997 | as_warn (_("`fp=32' used with a 64-bit ABI")); | |
5f4678bb | 3998 | if (ISA_IS_R6 (opts->isa) && opts->single_float == 0) |
7361da2c | 3999 | as_bad (_("`fp=32' used with a MIPS R6 cpu")); |
919731af | 4000 | break; |
4001 | default: | |
4002 | as_bad (_("Unknown size of floating point registers")); | |
4003 | break; | |
4004 | } | |
4005 | ||
351cdf24 MF |
4006 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !opts->oddspreg) |
4007 | as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI")); | |
4008 | ||
919731af | 4009 | if (opts->micromips == 1 && opts->mips16 == 1) |
1357373c | 4010 | as_bad (_("`%s' cannot be used with `%s'"), "mips16", "micromips"); |
5f4678bb | 4011 | else if (ISA_IS_R6 (opts->isa) |
7361da2c AB |
4012 | && (opts->micromips == 1 |
4013 | || opts->mips16 == 1)) | |
1357373c | 4014 | as_fatal (_("`%s' cannot be used with `%s'"), |
7361da2c | 4015 | opts->micromips ? "micromips" : "mips16", |
5f4678bb | 4016 | mips_cpu_info_from_isa (opts->isa)->name); |
7361da2c AB |
4017 | |
4018 | if (ISA_IS_R6 (opts->isa) && mips_relax_branch) | |
4019 | as_fatal (_("branch relaxation is not supported in `%s'"), | |
4020 | mips_cpu_info_from_isa (opts->isa)->name); | |
919731af | 4021 | } |
4022 | ||
4023 | /* Perform consistency checks on the module level options exactly once. | |
4024 | This is a deferred check that happens: | |
4025 | at the first .set directive | |
4026 | or, at the first pseudo op that generates code (inc .dc.a) | |
4027 | or, at the first instruction | |
4028 | or, at the end. */ | |
4029 | ||
4030 | static void | |
4031 | file_mips_check_options (void) | |
4032 | { | |
4033 | const struct mips_cpu_info *arch_info = 0; | |
4034 | ||
4035 | if (file_mips_opts_checked) | |
4036 | return; | |
4037 | ||
4038 | /* The following code determines the register size. | |
4039 | Similar code was added to GCC 3.3 (see override_options() in | |
4040 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
4041 | as much as possible. */ | |
4042 | ||
4043 | if (file_mips_opts.gp < 0) | |
4044 | { | |
4045 | /* Infer the integer register size from the ABI and processor. | |
4046 | Restrict ourselves to 32-bit registers if that's all the | |
4047 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
4048 | file_mips_opts.gp = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
4049 | || !ISA_HAS_64BIT_REGS (file_mips_opts.isa)) | |
4050 | ? 32 : 64; | |
4051 | } | |
4052 | ||
4053 | if (file_mips_opts.fp < 0) | |
4054 | { | |
4055 | /* No user specified float register size. | |
4056 | ??? GAS treats single-float processors as though they had 64-bit | |
4057 | float registers (although it complains when double-precision | |
4058 | instructions are used). As things stand, saying they have 32-bit | |
4059 | registers would lead to spurious "register must be even" messages. | |
4060 | So here we assume float registers are never smaller than the | |
4061 | integer ones. */ | |
4062 | if (file_mips_opts.gp == 64) | |
4063 | /* 64-bit integer registers implies 64-bit float registers. */ | |
4064 | file_mips_opts.fp = 64; | |
4065 | else if ((file_mips_opts.ase & FP64_ASES) | |
4066 | && ISA_HAS_64BIT_FPRS (file_mips_opts.isa)) | |
4067 | /* Handle ASEs that require 64-bit float registers, if possible. */ | |
4068 | file_mips_opts.fp = 64; | |
7361da2c AB |
4069 | else if (ISA_IS_R6 (mips_opts.isa)) |
4070 | /* R6 implies 64-bit float registers. */ | |
4071 | file_mips_opts.fp = 64; | |
919731af | 4072 | else |
4073 | /* 32-bit float registers. */ | |
4074 | file_mips_opts.fp = 32; | |
4075 | } | |
4076 | ||
4077 | arch_info = mips_cpu_info_from_arch (file_mips_opts.arch); | |
4078 | ||
351cdf24 MF |
4079 | /* Disable operations on odd-numbered floating-point registers by default |
4080 | when using the FPXX ABI. */ | |
4081 | if (file_mips_opts.oddspreg < 0) | |
4082 | { | |
4083 | if (file_mips_opts.fp == 0) | |
4084 | file_mips_opts.oddspreg = 0; | |
4085 | else | |
4086 | file_mips_opts.oddspreg = 1; | |
4087 | } | |
4088 | ||
919731af | 4089 | /* End of GCC-shared inference code. */ |
4090 | ||
4091 | /* This flag is set when we have a 64-bit capable CPU but use only | |
4092 | 32-bit wide registers. Note that EABI does not use it. */ | |
4093 | if (ISA_HAS_64BIT_REGS (file_mips_opts.isa) | |
4094 | && ((mips_abi == NO_ABI && file_mips_opts.gp == 32) | |
4095 | || mips_abi == O32_ABI)) | |
4096 | mips_32bitmode = 1; | |
4097 | ||
4098 | if (file_mips_opts.isa == ISA_MIPS1 && mips_trap) | |
4099 | as_bad (_("trap exception not supported at ISA 1")); | |
4100 | ||
4101 | /* If the selected architecture includes support for ASEs, enable | |
4102 | generation of code for them. */ | |
4103 | if (file_mips_opts.mips16 == -1) | |
4104 | file_mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_opts.arch)) ? 1 : 0; | |
4105 | if (file_mips_opts.micromips == -1) | |
4106 | file_mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_opts.arch)) | |
4107 | ? 1 : 0; | |
4108 | ||
7361da2c AB |
4109 | if (mips_nan2008 == -1) |
4110 | mips_nan2008 = (ISA_HAS_LEGACY_NAN (file_mips_opts.isa)) ? 0 : 1; | |
4111 | else if (!ISA_HAS_LEGACY_NAN (file_mips_opts.isa) && mips_nan2008 == 0) | |
4112 | as_fatal (_("`%s' does not support legacy NaN"), | |
4113 | mips_cpu_info_from_arch (file_mips_opts.arch)->name); | |
4114 | ||
919731af | 4115 | /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from |
4116 | being selected implicitly. */ | |
4117 | if (file_mips_opts.fp != 64) | |
4118 | file_ase_explicit |= ASE_MIPS3D | ASE_MDMX | ASE_MSA; | |
4119 | ||
4120 | /* If the user didn't explicitly select or deselect a particular ASE, | |
4121 | use the default setting for the CPU. */ | |
4122 | file_mips_opts.ase |= (arch_info->ase & ~file_ase_explicit); | |
4123 | ||
4124 | /* Set up the current options. These may change throughout assembly. */ | |
4125 | mips_opts = file_mips_opts; | |
4126 | ||
4127 | mips_check_isa_supports_ases (); | |
4128 | mips_check_options (&file_mips_opts, TRUE); | |
4129 | file_mips_opts_checked = TRUE; | |
4130 | ||
4131 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch)) | |
4132 | as_warn (_("could not set architecture and machine")); | |
4133 | } | |
4134 | ||
252b5132 | 4135 | void |
17a2f251 | 4136 | md_assemble (char *str) |
252b5132 RH |
4137 | { |
4138 | struct mips_cl_insn insn; | |
f6688943 TS |
4139 | bfd_reloc_code_real_type unused_reloc[3] |
4140 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 4141 | |
919731af | 4142 | file_mips_check_options (); |
4143 | ||
252b5132 | 4144 | imm_expr.X_op = O_absent; |
252b5132 | 4145 | offset_expr.X_op = O_absent; |
f6688943 TS |
4146 | offset_reloc[0] = BFD_RELOC_UNUSED; |
4147 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
4148 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 | 4149 | |
e1b47bd5 RS |
4150 | mips_mark_labels (); |
4151 | mips_assembling_insn = TRUE; | |
e3de51ce | 4152 | clear_insn_error (); |
e1b47bd5 | 4153 | |
252b5132 RH |
4154 | if (mips_opts.mips16) |
4155 | mips16_ip (str, &insn); | |
4156 | else | |
4157 | { | |
4158 | mips_ip (str, &insn); | |
beae10d5 KH |
4159 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
4160 | str, insn.insn_opcode)); | |
252b5132 RH |
4161 | } |
4162 | ||
e3de51ce RS |
4163 | if (insn_error.msg) |
4164 | report_insn_error (str); | |
e1b47bd5 | 4165 | else if (insn.insn_mo->pinfo == INSN_MACRO) |
252b5132 | 4166 | { |
584892a6 | 4167 | macro_start (); |
252b5132 RH |
4168 | if (mips_opts.mips16) |
4169 | mips16_macro (&insn); | |
4170 | else | |
833794fc | 4171 | macro (&insn, str); |
584892a6 | 4172 | macro_end (); |
252b5132 RH |
4173 | } |
4174 | else | |
4175 | { | |
77bd4346 | 4176 | if (offset_expr.X_op != O_absent) |
df58fc94 | 4177 | append_insn (&insn, &offset_expr, offset_reloc, FALSE); |
252b5132 | 4178 | else |
df58fc94 | 4179 | append_insn (&insn, NULL, unused_reloc, FALSE); |
252b5132 | 4180 | } |
e1b47bd5 RS |
4181 | |
4182 | mips_assembling_insn = FALSE; | |
252b5132 RH |
4183 | } |
4184 | ||
738e5348 RS |
4185 | /* Convenience functions for abstracting away the differences between |
4186 | MIPS16 and non-MIPS16 relocations. */ | |
4187 | ||
4188 | static inline bfd_boolean | |
4189 | mips16_reloc_p (bfd_reloc_code_real_type reloc) | |
4190 | { | |
4191 | switch (reloc) | |
4192 | { | |
4193 | case BFD_RELOC_MIPS16_JMP: | |
4194 | case BFD_RELOC_MIPS16_GPREL: | |
4195 | case BFD_RELOC_MIPS16_GOT16: | |
4196 | case BFD_RELOC_MIPS16_CALL16: | |
4197 | case BFD_RELOC_MIPS16_HI16_S: | |
4198 | case BFD_RELOC_MIPS16_HI16: | |
4199 | case BFD_RELOC_MIPS16_LO16: | |
c9775dde | 4200 | case BFD_RELOC_MIPS16_16_PCREL_S1: |
738e5348 RS |
4201 | return TRUE; |
4202 | ||
4203 | default: | |
4204 | return FALSE; | |
4205 | } | |
4206 | } | |
4207 | ||
df58fc94 RS |
4208 | static inline bfd_boolean |
4209 | micromips_reloc_p (bfd_reloc_code_real_type reloc) | |
4210 | { | |
4211 | switch (reloc) | |
4212 | { | |
4213 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: | |
4214 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
4215 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
4216 | case BFD_RELOC_MICROMIPS_GPREL16: | |
4217 | case BFD_RELOC_MICROMIPS_JMP: | |
4218 | case BFD_RELOC_MICROMIPS_HI16: | |
4219 | case BFD_RELOC_MICROMIPS_HI16_S: | |
4220 | case BFD_RELOC_MICROMIPS_LO16: | |
4221 | case BFD_RELOC_MICROMIPS_LITERAL: | |
4222 | case BFD_RELOC_MICROMIPS_GOT16: | |
4223 | case BFD_RELOC_MICROMIPS_CALL16: | |
4224 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
4225 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
4226 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
4227 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
4228 | case BFD_RELOC_MICROMIPS_SUB: | |
4229 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
4230 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
4231 | case BFD_RELOC_MICROMIPS_GOT_DISP: | |
4232 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
4233 | case BFD_RELOC_MICROMIPS_HIGHER: | |
4234 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
4235 | case BFD_RELOC_MICROMIPS_JALR: | |
4236 | return TRUE; | |
4237 | ||
4238 | default: | |
4239 | return FALSE; | |
4240 | } | |
4241 | } | |
4242 | ||
2309ddf2 MR |
4243 | static inline bfd_boolean |
4244 | jmp_reloc_p (bfd_reloc_code_real_type reloc) | |
4245 | { | |
4246 | return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP; | |
4247 | } | |
4248 | ||
0e9c5a5c MR |
4249 | static inline bfd_boolean |
4250 | b_reloc_p (bfd_reloc_code_real_type reloc) | |
4251 | { | |
4252 | return (reloc == BFD_RELOC_MIPS_26_PCREL_S2 | |
4253 | || reloc == BFD_RELOC_MIPS_21_PCREL_S2 | |
4254 | || reloc == BFD_RELOC_16_PCREL_S2 | |
c9775dde | 4255 | || reloc == BFD_RELOC_MIPS16_16_PCREL_S1 |
0e9c5a5c MR |
4256 | || reloc == BFD_RELOC_MICROMIPS_16_PCREL_S1 |
4257 | || reloc == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
4258 | || reloc == BFD_RELOC_MICROMIPS_7_PCREL_S1); | |
4259 | } | |
4260 | ||
738e5348 RS |
4261 | static inline bfd_boolean |
4262 | got16_reloc_p (bfd_reloc_code_real_type reloc) | |
4263 | { | |
2309ddf2 | 4264 | return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16 |
df58fc94 | 4265 | || reloc == BFD_RELOC_MICROMIPS_GOT16); |
738e5348 RS |
4266 | } |
4267 | ||
4268 | static inline bfd_boolean | |
4269 | hi16_reloc_p (bfd_reloc_code_real_type reloc) | |
4270 | { | |
2309ddf2 | 4271 | return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S |
df58fc94 | 4272 | || reloc == BFD_RELOC_MICROMIPS_HI16_S); |
738e5348 RS |
4273 | } |
4274 | ||
4275 | static inline bfd_boolean | |
4276 | lo16_reloc_p (bfd_reloc_code_real_type reloc) | |
4277 | { | |
2309ddf2 | 4278 | return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16 |
df58fc94 RS |
4279 | || reloc == BFD_RELOC_MICROMIPS_LO16); |
4280 | } | |
4281 | ||
df58fc94 RS |
4282 | static inline bfd_boolean |
4283 | jalr_reloc_p (bfd_reloc_code_real_type reloc) | |
4284 | { | |
2309ddf2 | 4285 | return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR; |
738e5348 RS |
4286 | } |
4287 | ||
f2ae14a1 RS |
4288 | static inline bfd_boolean |
4289 | gprel16_reloc_p (bfd_reloc_code_real_type reloc) | |
4290 | { | |
4291 | return (reloc == BFD_RELOC_GPREL16 || reloc == BFD_RELOC_MIPS16_GPREL | |
4292 | || reloc == BFD_RELOC_MICROMIPS_GPREL16); | |
4293 | } | |
4294 | ||
2de39019 CM |
4295 | /* Return true if RELOC is a PC-relative relocation that does not have |
4296 | full address range. */ | |
4297 | ||
4298 | static inline bfd_boolean | |
4299 | limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc) | |
4300 | { | |
4301 | switch (reloc) | |
4302 | { | |
4303 | case BFD_RELOC_16_PCREL_S2: | |
c9775dde | 4304 | case BFD_RELOC_MIPS16_16_PCREL_S1: |
2de39019 CM |
4305 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
4306 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
4307 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
7361da2c AB |
4308 | case BFD_RELOC_MIPS_21_PCREL_S2: |
4309 | case BFD_RELOC_MIPS_26_PCREL_S2: | |
4310 | case BFD_RELOC_MIPS_18_PCREL_S3: | |
4311 | case BFD_RELOC_MIPS_19_PCREL_S2: | |
2de39019 CM |
4312 | return TRUE; |
4313 | ||
b47468a6 | 4314 | case BFD_RELOC_32_PCREL: |
7361da2c AB |
4315 | case BFD_RELOC_HI16_S_PCREL: |
4316 | case BFD_RELOC_LO16_PCREL: | |
b47468a6 CM |
4317 | return HAVE_64BIT_ADDRESSES; |
4318 | ||
2de39019 CM |
4319 | default: |
4320 | return FALSE; | |
4321 | } | |
4322 | } | |
b47468a6 | 4323 | |
5919d012 | 4324 | /* Return true if the given relocation might need a matching %lo(). |
0a44bf69 RS |
4325 | This is only "might" because SVR4 R_MIPS_GOT16 relocations only |
4326 | need a matching %lo() when applied to local symbols. */ | |
5919d012 RS |
4327 | |
4328 | static inline bfd_boolean | |
17a2f251 | 4329 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 4330 | { |
3b91255e | 4331 | return (HAVE_IN_PLACE_ADDENDS |
738e5348 | 4332 | && (hi16_reloc_p (reloc) |
0a44bf69 RS |
4333 | /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo(); |
4334 | all GOT16 relocations evaluate to "G". */ | |
738e5348 RS |
4335 | || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC))); |
4336 | } | |
4337 | ||
4338 | /* Return the type of %lo() reloc needed by RELOC, given that | |
4339 | reloc_needs_lo_p. */ | |
4340 | ||
4341 | static inline bfd_reloc_code_real_type | |
4342 | matching_lo_reloc (bfd_reloc_code_real_type reloc) | |
4343 | { | |
df58fc94 RS |
4344 | return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 |
4345 | : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16 | |
4346 | : BFD_RELOC_LO16)); | |
5919d012 RS |
4347 | } |
4348 | ||
4349 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
4350 | relocation. */ | |
4351 | ||
4352 | static inline bfd_boolean | |
17a2f251 | 4353 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
4354 | { |
4355 | return (fixp->fx_next != NULL | |
738e5348 | 4356 | && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type) |
5919d012 RS |
4357 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
4358 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
4359 | } | |
4360 | ||
462427c4 RS |
4361 | /* Move all labels in LABELS to the current insertion point. TEXT_P |
4362 | says whether the labels refer to text or data. */ | |
404a8071 RS |
4363 | |
4364 | static void | |
462427c4 | 4365 | mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p) |
404a8071 RS |
4366 | { |
4367 | struct insn_label_list *l; | |
4368 | valueT val; | |
4369 | ||
462427c4 | 4370 | for (l = labels; l != NULL; l = l->next) |
404a8071 | 4371 | { |
9c2799c2 | 4372 | gas_assert (S_GET_SEGMENT (l->label) == now_seg); |
404a8071 RS |
4373 | symbol_set_frag (l->label, frag_now); |
4374 | val = (valueT) frag_now_fix (); | |
df58fc94 | 4375 | /* MIPS16/microMIPS text labels are stored as odd. */ |
462427c4 | 4376 | if (text_p && HAVE_CODE_COMPRESSION) |
404a8071 RS |
4377 | ++val; |
4378 | S_SET_VALUE (l->label, val); | |
4379 | } | |
4380 | } | |
4381 | ||
462427c4 RS |
4382 | /* Move all labels in insn_labels to the current insertion point |
4383 | and treat them as text labels. */ | |
4384 | ||
4385 | static void | |
4386 | mips_move_text_labels (void) | |
4387 | { | |
4388 | mips_move_labels (seg_info (now_seg)->label_list, TRUE); | |
4389 | } | |
4390 | ||
9e009953 MR |
4391 | /* Duplicate the test for LINK_ONCE sections as in `adjust_reloc_syms'. */ |
4392 | ||
5f0fe04b TS |
4393 | static bfd_boolean |
4394 | s_is_linkonce (symbolS *sym, segT from_seg) | |
4395 | { | |
4396 | bfd_boolean linkonce = FALSE; | |
4397 | segT symseg = S_GET_SEGMENT (sym); | |
4398 | ||
4399 | if (symseg != from_seg && !S_IS_LOCAL (sym)) | |
4400 | { | |
4401 | if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE)) | |
4402 | linkonce = TRUE; | |
5f0fe04b TS |
4403 | /* The GNU toolchain uses an extension for ELF: a section |
4404 | beginning with the magic string .gnu.linkonce is a | |
4405 | linkonce section. */ | |
4406 | if (strncmp (segment_name (symseg), ".gnu.linkonce", | |
4407 | sizeof ".gnu.linkonce" - 1) == 0) | |
4408 | linkonce = TRUE; | |
5f0fe04b TS |
4409 | } |
4410 | return linkonce; | |
4411 | } | |
4412 | ||
e1b47bd5 | 4413 | /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the |
df58fc94 RS |
4414 | linker to handle them specially, such as generating jalx instructions |
4415 | when needed. We also make them odd for the duration of the assembly, | |
4416 | in order to generate the right sort of code. We will make them even | |
252b5132 RH |
4417 | in the adjust_symtab routine, while leaving them marked. This is |
4418 | convenient for the debugger and the disassembler. The linker knows | |
4419 | to make them odd again. */ | |
4420 | ||
4421 | static void | |
e1b47bd5 | 4422 | mips_compressed_mark_label (symbolS *label) |
252b5132 | 4423 | { |
df58fc94 | 4424 | gas_assert (HAVE_CODE_COMPRESSION); |
a8dbcb85 | 4425 | |
f3ded42a RS |
4426 | if (mips_opts.mips16) |
4427 | S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label))); | |
4428 | else | |
4429 | S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label))); | |
e1b47bd5 RS |
4430 | if ((S_GET_VALUE (label) & 1) == 0 |
4431 | /* Don't adjust the address if the label is global or weak, or | |
4432 | in a link-once section, since we'll be emitting symbol reloc | |
4433 | references to it which will be patched up by the linker, and | |
4434 | the final value of the symbol may or may not be MIPS16/microMIPS. */ | |
4435 | && !S_IS_WEAK (label) | |
4436 | && !S_IS_EXTERNAL (label) | |
4437 | && !s_is_linkonce (label, now_seg)) | |
4438 | S_SET_VALUE (label, S_GET_VALUE (label) | 1); | |
4439 | } | |
4440 | ||
4441 | /* Mark preceding MIPS16 or microMIPS instruction labels. */ | |
4442 | ||
4443 | static void | |
4444 | mips_compressed_mark_labels (void) | |
4445 | { | |
4446 | struct insn_label_list *l; | |
4447 | ||
4448 | for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next) | |
4449 | mips_compressed_mark_label (l->label); | |
252b5132 RH |
4450 | } |
4451 | ||
4d7206a2 RS |
4452 | /* End the current frag. Make it a variant frag and record the |
4453 | relaxation info. */ | |
4454 | ||
4455 | static void | |
4456 | relax_close_frag (void) | |
4457 | { | |
584892a6 | 4458 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 4459 | frag_var (rs_machine_dependent, 0, 0, |
ce8ad872 MR |
4460 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1], |
4461 | mips_pic != NO_PIC), | |
4d7206a2 RS |
4462 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
4463 | ||
4464 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
4465 | mips_relax.first_fixup = 0; | |
4466 | } | |
4467 | ||
4468 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
4469 | See the comment above RELAX_ENCODE for more details. */ | |
4470 | ||
4471 | static void | |
4472 | relax_start (symbolS *symbol) | |
4473 | { | |
9c2799c2 | 4474 | gas_assert (mips_relax.sequence == 0); |
4d7206a2 RS |
4475 | mips_relax.sequence = 1; |
4476 | mips_relax.symbol = symbol; | |
4477 | } | |
4478 | ||
4479 | /* Start generating the second version of a relaxable sequence. | |
4480 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
4481 | |
4482 | static void | |
4d7206a2 RS |
4483 | relax_switch (void) |
4484 | { | |
9c2799c2 | 4485 | gas_assert (mips_relax.sequence == 1); |
4d7206a2 RS |
4486 | mips_relax.sequence = 2; |
4487 | } | |
4488 | ||
4489 | /* End the current relaxable sequence. */ | |
4490 | ||
4491 | static void | |
4492 | relax_end (void) | |
4493 | { | |
9c2799c2 | 4494 | gas_assert (mips_relax.sequence == 2); |
4d7206a2 RS |
4495 | relax_close_frag (); |
4496 | mips_relax.sequence = 0; | |
4497 | } | |
4498 | ||
11625dd8 RS |
4499 | /* Return true if IP is a delayed branch or jump. */ |
4500 | ||
4501 | static inline bfd_boolean | |
4502 | delayed_branch_p (const struct mips_cl_insn *ip) | |
4503 | { | |
4504 | return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY | |
4505 | | INSN_COND_BRANCH_DELAY | |
4506 | | INSN_COND_BRANCH_LIKELY)) != 0; | |
4507 | } | |
4508 | ||
4509 | /* Return true if IP is a compact branch or jump. */ | |
4510 | ||
4511 | static inline bfd_boolean | |
4512 | compact_branch_p (const struct mips_cl_insn *ip) | |
4513 | { | |
26545944 RS |
4514 | return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH |
4515 | | INSN2_COND_BRANCH)) != 0; | |
11625dd8 RS |
4516 | } |
4517 | ||
4518 | /* Return true if IP is an unconditional branch or jump. */ | |
4519 | ||
4520 | static inline bfd_boolean | |
4521 | uncond_branch_p (const struct mips_cl_insn *ip) | |
4522 | { | |
4523 | return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0 | |
26545944 | 4524 | || (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0); |
11625dd8 RS |
4525 | } |
4526 | ||
4527 | /* Return true if IP is a branch-likely instruction. */ | |
4528 | ||
4529 | static inline bfd_boolean | |
4530 | branch_likely_p (const struct mips_cl_insn *ip) | |
4531 | { | |
4532 | return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0; | |
4533 | } | |
4534 | ||
14fe068b RS |
4535 | /* Return the type of nop that should be used to fill the delay slot |
4536 | of delayed branch IP. */ | |
4537 | ||
4538 | static struct mips_cl_insn * | |
4539 | get_delay_slot_nop (const struct mips_cl_insn *ip) | |
4540 | { | |
4541 | if (mips_opts.micromips | |
4542 | && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
4543 | return µmips_nop32_insn; | |
4544 | return NOP_INSN; | |
4545 | } | |
4546 | ||
fc76e730 RS |
4547 | /* Return a mask that has bit N set if OPCODE reads the register(s) |
4548 | in operand N. */ | |
df58fc94 RS |
4549 | |
4550 | static unsigned int | |
fc76e730 | 4551 | insn_read_mask (const struct mips_opcode *opcode) |
df58fc94 | 4552 | { |
fc76e730 RS |
4553 | return (opcode->pinfo & INSN_READ_ALL) >> INSN_READ_SHIFT; |
4554 | } | |
df58fc94 | 4555 | |
fc76e730 RS |
4556 | /* Return a mask that has bit N set if OPCODE writes to the register(s) |
4557 | in operand N. */ | |
4558 | ||
4559 | static unsigned int | |
4560 | insn_write_mask (const struct mips_opcode *opcode) | |
4561 | { | |
4562 | return (opcode->pinfo & INSN_WRITE_ALL) >> INSN_WRITE_SHIFT; | |
4563 | } | |
4564 | ||
4565 | /* Return a mask of the registers specified by operand OPERAND of INSN. | |
4566 | Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK | |
4567 | is set. */ | |
4568 | ||
4569 | static unsigned int | |
4570 | operand_reg_mask (const struct mips_cl_insn *insn, | |
4571 | const struct mips_operand *operand, | |
4572 | unsigned int type_mask) | |
4573 | { | |
4574 | unsigned int uval, vsel; | |
4575 | ||
4576 | switch (operand->type) | |
df58fc94 | 4577 | { |
fc76e730 RS |
4578 | case OP_INT: |
4579 | case OP_MAPPED_INT: | |
4580 | case OP_MSB: | |
4581 | case OP_PCREL: | |
4582 | case OP_PERF_REG: | |
4583 | case OP_ADDIUSP_INT: | |
4584 | case OP_ENTRY_EXIT_LIST: | |
4585 | case OP_REPEAT_DEST_REG: | |
4586 | case OP_REPEAT_PREV_REG: | |
4587 | case OP_PC: | |
14daeee3 RS |
4588 | case OP_VU0_SUFFIX: |
4589 | case OP_VU0_MATCH_SUFFIX: | |
56d438b1 | 4590 | case OP_IMM_INDEX: |
fc76e730 RS |
4591 | abort (); |
4592 | ||
25499ac7 MR |
4593 | case OP_REG28: |
4594 | return 1 << 28; | |
4595 | ||
fc76e730 | 4596 | case OP_REG: |
0f35dbc4 | 4597 | case OP_OPTIONAL_REG: |
fc76e730 RS |
4598 | { |
4599 | const struct mips_reg_operand *reg_op; | |
4600 | ||
4601 | reg_op = (const struct mips_reg_operand *) operand; | |
4602 | if (!(type_mask & (1 << reg_op->reg_type))) | |
4603 | return 0; | |
4604 | uval = insn_extract_operand (insn, operand); | |
4605 | return 1 << mips_decode_reg_operand (reg_op, uval); | |
4606 | } | |
4607 | ||
4608 | case OP_REG_PAIR: | |
4609 | { | |
4610 | const struct mips_reg_pair_operand *pair_op; | |
4611 | ||
4612 | pair_op = (const struct mips_reg_pair_operand *) operand; | |
4613 | if (!(type_mask & (1 << pair_op->reg_type))) | |
4614 | return 0; | |
4615 | uval = insn_extract_operand (insn, operand); | |
4616 | return (1 << pair_op->reg1_map[uval]) | (1 << pair_op->reg2_map[uval]); | |
4617 | } | |
4618 | ||
4619 | case OP_CLO_CLZ_DEST: | |
4620 | if (!(type_mask & (1 << OP_REG_GP))) | |
4621 | return 0; | |
4622 | uval = insn_extract_operand (insn, operand); | |
4623 | return (1 << (uval & 31)) | (1 << (uval >> 5)); | |
4624 | ||
7361da2c AB |
4625 | case OP_SAME_RS_RT: |
4626 | if (!(type_mask & (1 << OP_REG_GP))) | |
4627 | return 0; | |
4628 | uval = insn_extract_operand (insn, operand); | |
4629 | gas_assert ((uval & 31) == (uval >> 5)); | |
4630 | return 1 << (uval & 31); | |
4631 | ||
4632 | case OP_CHECK_PREV: | |
4633 | case OP_NON_ZERO_REG: | |
4634 | if (!(type_mask & (1 << OP_REG_GP))) | |
4635 | return 0; | |
4636 | uval = insn_extract_operand (insn, operand); | |
4637 | return 1 << (uval & 31); | |
4638 | ||
fc76e730 RS |
4639 | case OP_LWM_SWM_LIST: |
4640 | abort (); | |
4641 | ||
4642 | case OP_SAVE_RESTORE_LIST: | |
4643 | abort (); | |
4644 | ||
4645 | case OP_MDMX_IMM_REG: | |
4646 | if (!(type_mask & (1 << OP_REG_VEC))) | |
4647 | return 0; | |
4648 | uval = insn_extract_operand (insn, operand); | |
4649 | vsel = uval >> 5; | |
4650 | if ((vsel & 0x18) == 0x18) | |
4651 | return 0; | |
4652 | return 1 << (uval & 31); | |
56d438b1 CF |
4653 | |
4654 | case OP_REG_INDEX: | |
4655 | if (!(type_mask & (1 << OP_REG_GP))) | |
4656 | return 0; | |
4657 | return 1 << insn_extract_operand (insn, operand); | |
df58fc94 | 4658 | } |
fc76e730 RS |
4659 | abort (); |
4660 | } | |
4661 | ||
4662 | /* Return a mask of the registers specified by operands OPNO_MASK of INSN, | |
4663 | where bit N of OPNO_MASK is set if operand N should be included. | |
4664 | Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK | |
4665 | is set. */ | |
4666 | ||
4667 | static unsigned int | |
4668 | insn_reg_mask (const struct mips_cl_insn *insn, | |
4669 | unsigned int type_mask, unsigned int opno_mask) | |
4670 | { | |
4671 | unsigned int opno, reg_mask; | |
4672 | ||
4673 | opno = 0; | |
4674 | reg_mask = 0; | |
4675 | while (opno_mask != 0) | |
4676 | { | |
4677 | if (opno_mask & 1) | |
4678 | reg_mask |= operand_reg_mask (insn, insn_opno (insn, opno), type_mask); | |
4679 | opno_mask >>= 1; | |
4680 | opno += 1; | |
4681 | } | |
4682 | return reg_mask; | |
df58fc94 RS |
4683 | } |
4684 | ||
4c260379 RS |
4685 | /* Return the mask of core registers that IP reads. */ |
4686 | ||
4687 | static unsigned int | |
4688 | gpr_read_mask (const struct mips_cl_insn *ip) | |
4689 | { | |
4690 | unsigned long pinfo, pinfo2; | |
4691 | unsigned int mask; | |
4692 | ||
fc76e730 | 4693 | mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_read_mask (ip->insn_mo)); |
4c260379 RS |
4694 | pinfo = ip->insn_mo->pinfo; |
4695 | pinfo2 = ip->insn_mo->pinfo2; | |
fc76e730 | 4696 | if (pinfo & INSN_UDI) |
4c260379 | 4697 | { |
fc76e730 RS |
4698 | /* UDI instructions have traditionally been assumed to read RS |
4699 | and RT. */ | |
4700 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); | |
4701 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); | |
4c260379 | 4702 | } |
fc76e730 RS |
4703 | if (pinfo & INSN_READ_GPR_24) |
4704 | mask |= 1 << 24; | |
4705 | if (pinfo2 & INSN2_READ_GPR_16) | |
4706 | mask |= 1 << 16; | |
4707 | if (pinfo2 & INSN2_READ_SP) | |
4708 | mask |= 1 << SP; | |
26545944 | 4709 | if (pinfo2 & INSN2_READ_GPR_31) |
fc76e730 | 4710 | mask |= 1 << 31; |
fe35f09f RS |
4711 | /* Don't include register 0. */ |
4712 | return mask & ~1; | |
4c260379 RS |
4713 | } |
4714 | ||
4715 | /* Return the mask of core registers that IP writes. */ | |
4716 | ||
4717 | static unsigned int | |
4718 | gpr_write_mask (const struct mips_cl_insn *ip) | |
4719 | { | |
4720 | unsigned long pinfo, pinfo2; | |
4721 | unsigned int mask; | |
4722 | ||
fc76e730 | 4723 | mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_write_mask (ip->insn_mo)); |
4c260379 RS |
4724 | pinfo = ip->insn_mo->pinfo; |
4725 | pinfo2 = ip->insn_mo->pinfo2; | |
fc76e730 RS |
4726 | if (pinfo & INSN_WRITE_GPR_24) |
4727 | mask |= 1 << 24; | |
4728 | if (pinfo & INSN_WRITE_GPR_31) | |
4729 | mask |= 1 << 31; | |
4730 | if (pinfo & INSN_UDI) | |
4731 | /* UDI instructions have traditionally been assumed to write to RD. */ | |
4732 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); | |
4733 | if (pinfo2 & INSN2_WRITE_SP) | |
4734 | mask |= 1 << SP; | |
fe35f09f RS |
4735 | /* Don't include register 0. */ |
4736 | return mask & ~1; | |
4c260379 RS |
4737 | } |
4738 | ||
4739 | /* Return the mask of floating-point registers that IP reads. */ | |
4740 | ||
4741 | static unsigned int | |
4742 | fpr_read_mask (const struct mips_cl_insn *ip) | |
4743 | { | |
fc76e730 | 4744 | unsigned long pinfo; |
4c260379 RS |
4745 | unsigned int mask; |
4746 | ||
9d5de888 CF |
4747 | mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC) |
4748 | | (1 << OP_REG_MSA)), | |
fc76e730 | 4749 | insn_read_mask (ip->insn_mo)); |
4c260379 | 4750 | pinfo = ip->insn_mo->pinfo; |
4c260379 RS |
4751 | /* Conservatively treat all operands to an FP_D instruction are doubles. |
4752 | (This is overly pessimistic for things like cvt.d.s.) */ | |
bad1aba3 | 4753 | if (FPR_SIZE != 64 && (pinfo & FP_D)) |
4c260379 RS |
4754 | mask |= mask << 1; |
4755 | return mask; | |
4756 | } | |
4757 | ||
4758 | /* Return the mask of floating-point registers that IP writes. */ | |
4759 | ||
4760 | static unsigned int | |
4761 | fpr_write_mask (const struct mips_cl_insn *ip) | |
4762 | { | |
fc76e730 | 4763 | unsigned long pinfo; |
4c260379 RS |
4764 | unsigned int mask; |
4765 | ||
9d5de888 CF |
4766 | mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC) |
4767 | | (1 << OP_REG_MSA)), | |
fc76e730 | 4768 | insn_write_mask (ip->insn_mo)); |
4c260379 | 4769 | pinfo = ip->insn_mo->pinfo; |
4c260379 RS |
4770 | /* Conservatively treat all operands to an FP_D instruction are doubles. |
4771 | (This is overly pessimistic for things like cvt.s.d.) */ | |
bad1aba3 | 4772 | if (FPR_SIZE != 64 && (pinfo & FP_D)) |
4c260379 RS |
4773 | mask |= mask << 1; |
4774 | return mask; | |
4775 | } | |
4776 | ||
a1d78564 RS |
4777 | /* Operand OPNUM of INSN is an odd-numbered floating-point register. |
4778 | Check whether that is allowed. */ | |
4779 | ||
4780 | static bfd_boolean | |
4781 | mips_oddfpreg_ok (const struct mips_opcode *insn, int opnum) | |
4782 | { | |
4783 | const char *s = insn->name; | |
351cdf24 MF |
4784 | bfd_boolean oddspreg = (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa, mips_opts.arch) |
4785 | || FPR_SIZE == 64) | |
4786 | && mips_opts.oddspreg; | |
a1d78564 RS |
4787 | |
4788 | if (insn->pinfo == INSN_MACRO) | |
4789 | /* Let a macro pass, we'll catch it later when it is expanded. */ | |
4790 | return TRUE; | |
4791 | ||
351cdf24 MF |
4792 | /* Single-precision coprocessor loads and moves are OK for 32-bit registers, |
4793 | otherwise it depends on oddspreg. */ | |
4794 | if ((insn->pinfo & FP_S) | |
4795 | && (insn->pinfo & (INSN_LOAD_MEMORY | INSN_STORE_MEMORY | |
43885403 | 4796 | | INSN_LOAD_COPROC | INSN_COPROC_MOVE))) |
351cdf24 | 4797 | return FPR_SIZE == 32 || oddspreg; |
a1d78564 | 4798 | |
351cdf24 MF |
4799 | /* Allow odd registers for single-precision ops and double-precision if the |
4800 | floating-point registers are 64-bit wide. */ | |
4801 | switch (insn->pinfo & (FP_S | FP_D)) | |
4802 | { | |
4803 | case FP_S: | |
4804 | case 0: | |
4805 | return oddspreg; | |
4806 | case FP_D: | |
4807 | return FPR_SIZE == 64; | |
4808 | default: | |
4809 | break; | |
a1d78564 RS |
4810 | } |
4811 | ||
351cdf24 MF |
4812 | /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ |
4813 | s = strchr (insn->name, '.'); | |
4814 | if (s != NULL && opnum == 2) | |
4815 | s = strchr (s + 1, '.'); | |
4816 | if (s != NULL && (s[1] == 'w' || s[1] == 's')) | |
4817 | return oddspreg; | |
a1d78564 | 4818 | |
351cdf24 | 4819 | return FPR_SIZE == 64; |
a1d78564 RS |
4820 | } |
4821 | ||
a1d78564 RS |
4822 | /* Information about an instruction argument that we're trying to match. */ |
4823 | struct mips_arg_info | |
4824 | { | |
4825 | /* The instruction so far. */ | |
4826 | struct mips_cl_insn *insn; | |
4827 | ||
a92713e6 RS |
4828 | /* The first unconsumed operand token. */ |
4829 | struct mips_operand_token *token; | |
4830 | ||
a1d78564 RS |
4831 | /* The 1-based operand number, in terms of insn->insn_mo->args. */ |
4832 | int opnum; | |
4833 | ||
4834 | /* The 1-based argument number, for error reporting. This does not | |
4835 | count elided optional registers, etc.. */ | |
4836 | int argnum; | |
4837 | ||
4838 | /* The last OP_REG operand seen, or ILLEGAL_REG if none. */ | |
4839 | unsigned int last_regno; | |
4840 | ||
4841 | /* If the first operand was an OP_REG, this is the register that it | |
4842 | specified, otherwise it is ILLEGAL_REG. */ | |
4843 | unsigned int dest_regno; | |
4844 | ||
4845 | /* The value of the last OP_INT operand. Only used for OP_MSB, | |
4846 | where it gives the lsb position. */ | |
4847 | unsigned int last_op_int; | |
4848 | ||
60f20e8b | 4849 | /* If true, match routines should assume that no later instruction |
2b0f3761 | 4850 | alternative matches and should therefore be as accommodating as |
60f20e8b RS |
4851 | possible. Match routines should not report errors if something |
4852 | is only invalid for !LAX_MATCH. */ | |
4853 | bfd_boolean lax_match; | |
a1d78564 | 4854 | |
a1d78564 RS |
4855 | /* True if a reference to the current AT register was seen. */ |
4856 | bfd_boolean seen_at; | |
4857 | }; | |
4858 | ||
1a00e612 RS |
4859 | /* Record that the argument is out of range. */ |
4860 | ||
4861 | static void | |
4862 | match_out_of_range (struct mips_arg_info *arg) | |
4863 | { | |
4864 | set_insn_error_i (arg->argnum, _("operand %d out of range"), arg->argnum); | |
4865 | } | |
4866 | ||
4867 | /* Record that the argument isn't constant but needs to be. */ | |
4868 | ||
4869 | static void | |
4870 | match_not_constant (struct mips_arg_info *arg) | |
4871 | { | |
4872 | set_insn_error_i (arg->argnum, _("operand %d must be constant"), | |
4873 | arg->argnum); | |
4874 | } | |
4875 | ||
a92713e6 RS |
4876 | /* Try to match an OT_CHAR token for character CH. Consume the token |
4877 | and return true on success, otherwise return false. */ | |
a1d78564 | 4878 | |
a92713e6 RS |
4879 | static bfd_boolean |
4880 | match_char (struct mips_arg_info *arg, char ch) | |
a1d78564 | 4881 | { |
a92713e6 RS |
4882 | if (arg->token->type == OT_CHAR && arg->token->u.ch == ch) |
4883 | { | |
4884 | ++arg->token; | |
4885 | if (ch == ',') | |
4886 | arg->argnum += 1; | |
4887 | return TRUE; | |
4888 | } | |
4889 | return FALSE; | |
4890 | } | |
a1d78564 | 4891 | |
a92713e6 RS |
4892 | /* Try to get an expression from the next tokens in ARG. Consume the |
4893 | tokens and return true on success, storing the expression value in | |
4894 | VALUE and relocation types in R. */ | |
4895 | ||
4896 | static bfd_boolean | |
4897 | match_expression (struct mips_arg_info *arg, expressionS *value, | |
4898 | bfd_reloc_code_real_type *r) | |
4899 | { | |
d436c1c2 RS |
4900 | /* If the next token is a '(' that was parsed as being part of a base |
4901 | expression, assume we have an elided offset. The later match will fail | |
4902 | if this turns out to be wrong. */ | |
4903 | if (arg->token->type == OT_CHAR && arg->token->u.ch == '(') | |
a1d78564 | 4904 | { |
d436c1c2 RS |
4905 | value->X_op = O_constant; |
4906 | value->X_add_number = 0; | |
4907 | r[0] = r[1] = r[2] = BFD_RELOC_UNUSED; | |
a92713e6 RS |
4908 | return TRUE; |
4909 | } | |
4910 | ||
d436c1c2 RS |
4911 | /* Reject register-based expressions such as "0+$2" and "(($2))". |
4912 | For plain registers the default error seems more appropriate. */ | |
4913 | if (arg->token->type == OT_INTEGER | |
4914 | && arg->token->u.integer.value.X_op == O_register) | |
a92713e6 | 4915 | { |
d436c1c2 RS |
4916 | set_insn_error (arg->argnum, _("register value used as expression")); |
4917 | return FALSE; | |
a1d78564 | 4918 | } |
d436c1c2 RS |
4919 | |
4920 | if (arg->token->type == OT_INTEGER) | |
a92713e6 | 4921 | { |
d436c1c2 RS |
4922 | *value = arg->token->u.integer.value; |
4923 | memcpy (r, arg->token->u.integer.relocs, 3 * sizeof (*r)); | |
4924 | ++arg->token; | |
4925 | return TRUE; | |
a92713e6 | 4926 | } |
a92713e6 | 4927 | |
d436c1c2 RS |
4928 | set_insn_error_i |
4929 | (arg->argnum, _("operand %d must be an immediate expression"), | |
4930 | arg->argnum); | |
4931 | return FALSE; | |
a92713e6 RS |
4932 | } |
4933 | ||
4934 | /* Try to get a constant expression from the next tokens in ARG. Consume | |
de194d85 | 4935 | the tokens and return true on success, storing the constant value |
a54d5f8b | 4936 | in *VALUE. */ |
a92713e6 RS |
4937 | |
4938 | static bfd_boolean | |
1a00e612 | 4939 | match_const_int (struct mips_arg_info *arg, offsetT *value) |
a92713e6 RS |
4940 | { |
4941 | expressionS ex; | |
4942 | bfd_reloc_code_real_type r[3]; | |
a1d78564 | 4943 | |
a92713e6 RS |
4944 | if (!match_expression (arg, &ex, r)) |
4945 | return FALSE; | |
4946 | ||
4947 | if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_constant) | |
a1d78564 RS |
4948 | *value = ex.X_add_number; |
4949 | else | |
4950 | { | |
c96425c5 MR |
4951 | if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_big) |
4952 | match_out_of_range (arg); | |
4953 | else | |
4954 | match_not_constant (arg); | |
1a00e612 | 4955 | return FALSE; |
a1d78564 | 4956 | } |
a92713e6 | 4957 | return TRUE; |
a1d78564 RS |
4958 | } |
4959 | ||
4960 | /* Return the RTYPE_* flags for a register operand of type TYPE that | |
4961 | appears in instruction OPCODE. */ | |
4962 | ||
4963 | static unsigned int | |
4964 | convert_reg_type (const struct mips_opcode *opcode, | |
4965 | enum mips_reg_operand_type type) | |
4966 | { | |
4967 | switch (type) | |
4968 | { | |
4969 | case OP_REG_GP: | |
4970 | return RTYPE_NUM | RTYPE_GP; | |
4971 | ||
4972 | case OP_REG_FP: | |
4973 | /* Allow vector register names for MDMX if the instruction is a 64-bit | |
4974 | FPR load, store or move (including moves to and from GPRs). */ | |
4975 | if ((mips_opts.ase & ASE_MDMX) | |
4976 | && (opcode->pinfo & FP_D) | |
43885403 | 4977 | && (opcode->pinfo & (INSN_COPROC_MOVE |
a1d78564 | 4978 | | INSN_COPROC_MEMORY_DELAY |
43885403 | 4979 | | INSN_LOAD_COPROC |
67dc82bc | 4980 | | INSN_LOAD_MEMORY |
a1d78564 RS |
4981 | | INSN_STORE_MEMORY))) |
4982 | return RTYPE_FPU | RTYPE_VEC; | |
4983 | return RTYPE_FPU; | |
4984 | ||
4985 | case OP_REG_CCC: | |
4986 | if (opcode->pinfo & (FP_D | FP_S)) | |
4987 | return RTYPE_CCC | RTYPE_FCC; | |
4988 | return RTYPE_CCC; | |
4989 | ||
4990 | case OP_REG_VEC: | |
4991 | if (opcode->membership & INSN_5400) | |
4992 | return RTYPE_FPU; | |
4993 | return RTYPE_FPU | RTYPE_VEC; | |
4994 | ||
4995 | case OP_REG_ACC: | |
4996 | return RTYPE_ACC; | |
4997 | ||
4998 | case OP_REG_COPRO: | |
4999 | if (opcode->name[strlen (opcode->name) - 1] == '0') | |
5000 | return RTYPE_NUM | RTYPE_CP0; | |
5001 | return RTYPE_NUM; | |
5002 | ||
5003 | case OP_REG_HW: | |
5004 | return RTYPE_NUM; | |
14daeee3 RS |
5005 | |
5006 | case OP_REG_VI: | |
5007 | return RTYPE_NUM | RTYPE_VI; | |
5008 | ||
5009 | case OP_REG_VF: | |
5010 | return RTYPE_NUM | RTYPE_VF; | |
5011 | ||
5012 | case OP_REG_R5900_I: | |
5013 | return RTYPE_R5900_I; | |
5014 | ||
5015 | case OP_REG_R5900_Q: | |
5016 | return RTYPE_R5900_Q; | |
5017 | ||
5018 | case OP_REG_R5900_R: | |
5019 | return RTYPE_R5900_R; | |
5020 | ||
5021 | case OP_REG_R5900_ACC: | |
5022 | return RTYPE_R5900_ACC; | |
56d438b1 CF |
5023 | |
5024 | case OP_REG_MSA: | |
5025 | return RTYPE_MSA; | |
5026 | ||
5027 | case OP_REG_MSA_CTRL: | |
5028 | return RTYPE_NUM; | |
a1d78564 RS |
5029 | } |
5030 | abort (); | |
5031 | } | |
5032 | ||
5033 | /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */ | |
5034 | ||
5035 | static void | |
5036 | check_regno (struct mips_arg_info *arg, | |
5037 | enum mips_reg_operand_type type, unsigned int regno) | |
5038 | { | |
5039 | if (AT && type == OP_REG_GP && regno == AT) | |
5040 | arg->seen_at = TRUE; | |
5041 | ||
5042 | if (type == OP_REG_FP | |
5043 | && (regno & 1) != 0 | |
a1d78564 | 5044 | && !mips_oddfpreg_ok (arg->insn->insn_mo, arg->opnum)) |
351cdf24 MF |
5045 | { |
5046 | /* This was a warning prior to introducing O32 FPXX and FP64 support | |
5047 | so maintain a warning for FP32 but raise an error for the new | |
5048 | cases. */ | |
5049 | if (FPR_SIZE == 32) | |
5050 | as_warn (_("float register should be even, was %d"), regno); | |
5051 | else | |
5052 | as_bad (_("float register should be even, was %d"), regno); | |
5053 | } | |
a1d78564 RS |
5054 | |
5055 | if (type == OP_REG_CCC) | |
5056 | { | |
5057 | const char *name; | |
5058 | size_t length; | |
5059 | ||
5060 | name = arg->insn->insn_mo->name; | |
5061 | length = strlen (name); | |
5062 | if ((regno & 1) != 0 | |
5063 | && ((length >= 3 && strcmp (name + length - 3, ".ps") == 0) | |
5064 | || (length >= 5 && strncmp (name + length - 5, "any2", 4) == 0))) | |
1661c76c | 5065 | as_warn (_("condition code register should be even for %s, was %d"), |
a1d78564 RS |
5066 | name, regno); |
5067 | ||
5068 | if ((regno & 3) != 0 | |
5069 | && (length >= 5 && strncmp (name + length - 5, "any4", 4) == 0)) | |
1661c76c | 5070 | as_warn (_("condition code register should be 0 or 4 for %s, was %d"), |
a1d78564 RS |
5071 | name, regno); |
5072 | } | |
5073 | } | |
5074 | ||
a92713e6 RS |
5075 | /* ARG is a register with symbol value SYMVAL. Try to interpret it as |
5076 | a register of type TYPE. Return true on success, storing the register | |
5077 | number in *REGNO and warning about any dubious uses. */ | |
5078 | ||
5079 | static bfd_boolean | |
5080 | match_regno (struct mips_arg_info *arg, enum mips_reg_operand_type type, | |
5081 | unsigned int symval, unsigned int *regno) | |
5082 | { | |
5083 | if (type == OP_REG_VEC) | |
5084 | symval = mips_prefer_vec_regno (symval); | |
5085 | if (!(symval & convert_reg_type (arg->insn->insn_mo, type))) | |
5086 | return FALSE; | |
5087 | ||
5088 | *regno = symval & RNUM_MASK; | |
5089 | check_regno (arg, type, *regno); | |
5090 | return TRUE; | |
5091 | } | |
5092 | ||
5093 | /* Try to interpret the next token in ARG as a register of type TYPE. | |
5094 | Consume the token and return true on success, storing the register | |
5095 | number in *REGNO. Return false on failure. */ | |
5096 | ||
5097 | static bfd_boolean | |
5098 | match_reg (struct mips_arg_info *arg, enum mips_reg_operand_type type, | |
5099 | unsigned int *regno) | |
5100 | { | |
5101 | if (arg->token->type == OT_REG | |
5102 | && match_regno (arg, type, arg->token->u.regno, regno)) | |
5103 | { | |
5104 | ++arg->token; | |
5105 | return TRUE; | |
5106 | } | |
5107 | return FALSE; | |
5108 | } | |
5109 | ||
5110 | /* Try to interpret the next token in ARG as a range of registers of type TYPE. | |
5111 | Consume the token and return true on success, storing the register numbers | |
5112 | in *REGNO1 and *REGNO2. Return false on failure. */ | |
5113 | ||
5114 | static bfd_boolean | |
5115 | match_reg_range (struct mips_arg_info *arg, enum mips_reg_operand_type type, | |
5116 | unsigned int *regno1, unsigned int *regno2) | |
5117 | { | |
5118 | if (match_reg (arg, type, regno1)) | |
5119 | { | |
5120 | *regno2 = *regno1; | |
5121 | return TRUE; | |
5122 | } | |
5123 | if (arg->token->type == OT_REG_RANGE | |
5124 | && match_regno (arg, type, arg->token->u.reg_range.regno1, regno1) | |
5125 | && match_regno (arg, type, arg->token->u.reg_range.regno2, regno2) | |
5126 | && *regno1 <= *regno2) | |
5127 | { | |
5128 | ++arg->token; | |
5129 | return TRUE; | |
5130 | } | |
5131 | return FALSE; | |
5132 | } | |
5133 | ||
a1d78564 RS |
5134 | /* OP_INT matcher. */ |
5135 | ||
a92713e6 | 5136 | static bfd_boolean |
a1d78564 | 5137 | match_int_operand (struct mips_arg_info *arg, |
a92713e6 | 5138 | const struct mips_operand *operand_base) |
a1d78564 RS |
5139 | { |
5140 | const struct mips_int_operand *operand; | |
3ccad066 | 5141 | unsigned int uval; |
a1d78564 RS |
5142 | int min_val, max_val, factor; |
5143 | offsetT sval; | |
a1d78564 RS |
5144 | |
5145 | operand = (const struct mips_int_operand *) operand_base; | |
5146 | factor = 1 << operand->shift; | |
3ccad066 RS |
5147 | min_val = mips_int_operand_min (operand); |
5148 | max_val = mips_int_operand_max (operand); | |
a1d78564 | 5149 | |
d436c1c2 RS |
5150 | if (operand_base->lsb == 0 |
5151 | && operand_base->size == 16 | |
5152 | && operand->shift == 0 | |
5153 | && operand->bias == 0 | |
5154 | && (operand->max_val == 32767 || operand->max_val == 65535)) | |
a1d78564 RS |
5155 | { |
5156 | /* The operand can be relocated. */ | |
a92713e6 RS |
5157 | if (!match_expression (arg, &offset_expr, offset_reloc)) |
5158 | return FALSE; | |
5159 | ||
c96425c5 MR |
5160 | if (offset_expr.X_op == O_big) |
5161 | { | |
5162 | match_out_of_range (arg); | |
5163 | return FALSE; | |
5164 | } | |
5165 | ||
a92713e6 | 5166 | if (offset_reloc[0] != BFD_RELOC_UNUSED) |
33eaf5de | 5167 | /* Relocation operators were used. Accept the argument and |
a1d78564 RS |
5168 | leave the relocation value in offset_expr and offset_relocs |
5169 | for the caller to process. */ | |
a92713e6 RS |
5170 | return TRUE; |
5171 | ||
5172 | if (offset_expr.X_op != O_constant) | |
a1d78564 | 5173 | { |
60f20e8b RS |
5174 | /* Accept non-constant operands if no later alternative matches, |
5175 | leaving it for the caller to process. */ | |
5176 | if (!arg->lax_match) | |
602b88e3 MR |
5177 | { |
5178 | match_not_constant (arg); | |
5179 | return FALSE; | |
5180 | } | |
a92713e6 RS |
5181 | offset_reloc[0] = BFD_RELOC_LO16; |
5182 | return TRUE; | |
a1d78564 | 5183 | } |
a92713e6 | 5184 | |
a1d78564 RS |
5185 | /* Clear the global state; we're going to install the operand |
5186 | ourselves. */ | |
a92713e6 | 5187 | sval = offset_expr.X_add_number; |
a1d78564 | 5188 | offset_expr.X_op = O_absent; |
60f20e8b RS |
5189 | |
5190 | /* For compatibility with older assemblers, we accept | |
5191 | 0x8000-0xffff as signed 16-bit numbers when only | |
5192 | signed numbers are allowed. */ | |
5193 | if (sval > max_val) | |
5194 | { | |
5195 | max_val = ((1 << operand_base->size) - 1) << operand->shift; | |
5196 | if (!arg->lax_match && sval <= max_val) | |
20c59b84 MR |
5197 | { |
5198 | match_out_of_range (arg); | |
5199 | return FALSE; | |
5200 | } | |
60f20e8b | 5201 | } |
a1d78564 RS |
5202 | } |
5203 | else | |
5204 | { | |
1a00e612 | 5205 | if (!match_const_int (arg, &sval)) |
a92713e6 | 5206 | return FALSE; |
a1d78564 RS |
5207 | } |
5208 | ||
5209 | arg->last_op_int = sval; | |
5210 | ||
1a00e612 | 5211 | if (sval < min_val || sval > max_val || sval % factor) |
a1d78564 | 5212 | { |
1a00e612 RS |
5213 | match_out_of_range (arg); |
5214 | return FALSE; | |
a1d78564 RS |
5215 | } |
5216 | ||
5217 | uval = (unsigned int) sval >> operand->shift; | |
5218 | uval -= operand->bias; | |
5219 | ||
5220 | /* Handle -mfix-cn63xxp1. */ | |
5221 | if (arg->opnum == 1 | |
5222 | && mips_fix_cn63xxp1 | |
5223 | && !mips_opts.micromips | |
5224 | && strcmp ("pref", arg->insn->insn_mo->name) == 0) | |
5225 | switch (uval) | |
5226 | { | |
5227 | case 5: | |
5228 | case 25: | |
5229 | case 26: | |
5230 | case 27: | |
5231 | case 28: | |
5232 | case 29: | |
5233 | case 30: | |
5234 | case 31: | |
5235 | /* These are ok. */ | |
5236 | break; | |
5237 | ||
5238 | default: | |
5239 | /* The rest must be changed to 28. */ | |
5240 | uval = 28; | |
5241 | break; | |
5242 | } | |
5243 | ||
5244 | insn_insert_operand (arg->insn, operand_base, uval); | |
a92713e6 | 5245 | return TRUE; |
a1d78564 RS |
5246 | } |
5247 | ||
5248 | /* OP_MAPPED_INT matcher. */ | |
5249 | ||
a92713e6 | 5250 | static bfd_boolean |
a1d78564 | 5251 | match_mapped_int_operand (struct mips_arg_info *arg, |
a92713e6 | 5252 | const struct mips_operand *operand_base) |
a1d78564 RS |
5253 | { |
5254 | const struct mips_mapped_int_operand *operand; | |
5255 | unsigned int uval, num_vals; | |
5256 | offsetT sval; | |
5257 | ||
5258 | operand = (const struct mips_mapped_int_operand *) operand_base; | |
1a00e612 | 5259 | if (!match_const_int (arg, &sval)) |
a92713e6 | 5260 | return FALSE; |
a1d78564 RS |
5261 | |
5262 | num_vals = 1 << operand_base->size; | |
5263 | for (uval = 0; uval < num_vals; uval++) | |
5264 | if (operand->int_map[uval] == sval) | |
5265 | break; | |
5266 | if (uval == num_vals) | |
1a00e612 RS |
5267 | { |
5268 | match_out_of_range (arg); | |
5269 | return FALSE; | |
5270 | } | |
a1d78564 RS |
5271 | |
5272 | insn_insert_operand (arg->insn, operand_base, uval); | |
a92713e6 | 5273 | return TRUE; |
a1d78564 RS |
5274 | } |
5275 | ||
5276 | /* OP_MSB matcher. */ | |
5277 | ||
a92713e6 | 5278 | static bfd_boolean |
a1d78564 | 5279 | match_msb_operand (struct mips_arg_info *arg, |
a92713e6 | 5280 | const struct mips_operand *operand_base) |
a1d78564 RS |
5281 | { |
5282 | const struct mips_msb_operand *operand; | |
5283 | int min_val, max_val, max_high; | |
5284 | offsetT size, sval, high; | |
5285 | ||
5286 | operand = (const struct mips_msb_operand *) operand_base; | |
5287 | min_val = operand->bias; | |
5288 | max_val = min_val + (1 << operand_base->size) - 1; | |
5289 | max_high = operand->opsize; | |
5290 | ||
1a00e612 | 5291 | if (!match_const_int (arg, &size)) |
a92713e6 | 5292 | return FALSE; |
a1d78564 RS |
5293 | |
5294 | high = size + arg->last_op_int; | |
5295 | sval = operand->add_lsb ? high : size; | |
5296 | ||
5297 | if (size < 0 || high > max_high || sval < min_val || sval > max_val) | |
5298 | { | |
1a00e612 RS |
5299 | match_out_of_range (arg); |
5300 | return FALSE; | |
a1d78564 RS |
5301 | } |
5302 | insn_insert_operand (arg->insn, operand_base, sval - min_val); | |
a92713e6 | 5303 | return TRUE; |
a1d78564 RS |
5304 | } |
5305 | ||
5306 | /* OP_REG matcher. */ | |
5307 | ||
a92713e6 | 5308 | static bfd_boolean |
a1d78564 | 5309 | match_reg_operand (struct mips_arg_info *arg, |
a92713e6 | 5310 | const struct mips_operand *operand_base) |
a1d78564 RS |
5311 | { |
5312 | const struct mips_reg_operand *operand; | |
a92713e6 | 5313 | unsigned int regno, uval, num_vals; |
a1d78564 RS |
5314 | |
5315 | operand = (const struct mips_reg_operand *) operand_base; | |
a92713e6 RS |
5316 | if (!match_reg (arg, operand->reg_type, ®no)) |
5317 | return FALSE; | |
a1d78564 RS |
5318 | |
5319 | if (operand->reg_map) | |
5320 | { | |
5321 | num_vals = 1 << operand->root.size; | |
5322 | for (uval = 0; uval < num_vals; uval++) | |
5323 | if (operand->reg_map[uval] == regno) | |
5324 | break; | |
5325 | if (num_vals == uval) | |
a92713e6 | 5326 | return FALSE; |
a1d78564 RS |
5327 | } |
5328 | else | |
5329 | uval = regno; | |
5330 | ||
a1d78564 RS |
5331 | arg->last_regno = regno; |
5332 | if (arg->opnum == 1) | |
5333 | arg->dest_regno = regno; | |
5334 | insn_insert_operand (arg->insn, operand_base, uval); | |
a92713e6 | 5335 | return TRUE; |
a1d78564 RS |
5336 | } |
5337 | ||
5338 | /* OP_REG_PAIR matcher. */ | |
5339 | ||
a92713e6 | 5340 | static bfd_boolean |
a1d78564 | 5341 | match_reg_pair_operand (struct mips_arg_info *arg, |
a92713e6 | 5342 | const struct mips_operand *operand_base) |
a1d78564 RS |
5343 | { |
5344 | const struct mips_reg_pair_operand *operand; | |
a92713e6 | 5345 | unsigned int regno1, regno2, uval, num_vals; |
a1d78564 RS |
5346 | |
5347 | operand = (const struct mips_reg_pair_operand *) operand_base; | |
a92713e6 RS |
5348 | if (!match_reg (arg, operand->reg_type, ®no1) |
5349 | || !match_char (arg, ',') | |
5350 | || !match_reg (arg, operand->reg_type, ®no2)) | |
5351 | return FALSE; | |
a1d78564 RS |
5352 | |
5353 | num_vals = 1 << operand_base->size; | |
5354 | for (uval = 0; uval < num_vals; uval++) | |
5355 | if (operand->reg1_map[uval] == regno1 && operand->reg2_map[uval] == regno2) | |
5356 | break; | |
5357 | if (uval == num_vals) | |
a92713e6 | 5358 | return FALSE; |
a1d78564 | 5359 | |
a1d78564 | 5360 | insn_insert_operand (arg->insn, operand_base, uval); |
a92713e6 | 5361 | return TRUE; |
a1d78564 RS |
5362 | } |
5363 | ||
5364 | /* OP_PCREL matcher. The caller chooses the relocation type. */ | |
5365 | ||
a92713e6 RS |
5366 | static bfd_boolean |
5367 | match_pcrel_operand (struct mips_arg_info *arg) | |
a1d78564 | 5368 | { |
a92713e6 RS |
5369 | bfd_reloc_code_real_type r[3]; |
5370 | ||
5371 | return match_expression (arg, &offset_expr, r) && r[0] == BFD_RELOC_UNUSED; | |
a1d78564 RS |
5372 | } |
5373 | ||
5374 | /* OP_PERF_REG matcher. */ | |
5375 | ||
a92713e6 | 5376 | static bfd_boolean |
a1d78564 | 5377 | match_perf_reg_operand (struct mips_arg_info *arg, |
a92713e6 | 5378 | const struct mips_operand *operand) |
a1d78564 RS |
5379 | { |
5380 | offsetT sval; | |
5381 | ||
1a00e612 | 5382 | if (!match_const_int (arg, &sval)) |
a92713e6 | 5383 | return FALSE; |
a1d78564 RS |
5384 | |
5385 | if (sval != 0 | |
5386 | && (sval != 1 | |
5387 | || (mips_opts.arch == CPU_R5900 | |
5388 | && (strcmp (arg->insn->insn_mo->name, "mfps") == 0 | |
5389 | || strcmp (arg->insn->insn_mo->name, "mtps") == 0)))) | |
5390 | { | |
1a00e612 RS |
5391 | set_insn_error (arg->argnum, _("invalid performance register")); |
5392 | return FALSE; | |
a1d78564 RS |
5393 | } |
5394 | ||
5395 | insn_insert_operand (arg->insn, operand, sval); | |
a92713e6 | 5396 | return TRUE; |
a1d78564 RS |
5397 | } |
5398 | ||
5399 | /* OP_ADDIUSP matcher. */ | |
5400 | ||
a92713e6 | 5401 | static bfd_boolean |
a1d78564 | 5402 | match_addiusp_operand (struct mips_arg_info *arg, |
a92713e6 | 5403 | const struct mips_operand *operand) |
a1d78564 RS |
5404 | { |
5405 | offsetT sval; | |
5406 | unsigned int uval; | |
5407 | ||
1a00e612 | 5408 | if (!match_const_int (arg, &sval)) |
a92713e6 | 5409 | return FALSE; |
a1d78564 RS |
5410 | |
5411 | if (sval % 4) | |
1a00e612 RS |
5412 | { |
5413 | match_out_of_range (arg); | |
5414 | return FALSE; | |
5415 | } | |
a1d78564 RS |
5416 | |
5417 | sval /= 4; | |
5418 | if (!(sval >= -258 && sval <= 257) || (sval >= -2 && sval <= 1)) | |
1a00e612 RS |
5419 | { |
5420 | match_out_of_range (arg); | |
5421 | return FALSE; | |
5422 | } | |
a1d78564 RS |
5423 | |
5424 | uval = (unsigned int) sval; | |
5425 | uval = ((uval >> 1) & ~0xff) | (uval & 0xff); | |
5426 | insn_insert_operand (arg->insn, operand, uval); | |
a92713e6 | 5427 | return TRUE; |
a1d78564 RS |
5428 | } |
5429 | ||
5430 | /* OP_CLO_CLZ_DEST matcher. */ | |
5431 | ||
a92713e6 | 5432 | static bfd_boolean |
a1d78564 | 5433 | match_clo_clz_dest_operand (struct mips_arg_info *arg, |
a92713e6 | 5434 | const struct mips_operand *operand) |
a1d78564 RS |
5435 | { |
5436 | unsigned int regno; | |
5437 | ||
a92713e6 RS |
5438 | if (!match_reg (arg, OP_REG_GP, ®no)) |
5439 | return FALSE; | |
a1d78564 | 5440 | |
a1d78564 | 5441 | insn_insert_operand (arg->insn, operand, regno | (regno << 5)); |
a92713e6 | 5442 | return TRUE; |
a1d78564 RS |
5443 | } |
5444 | ||
7361da2c AB |
5445 | /* OP_CHECK_PREV matcher. */ |
5446 | ||
5447 | static bfd_boolean | |
5448 | match_check_prev_operand (struct mips_arg_info *arg, | |
5449 | const struct mips_operand *operand_base) | |
5450 | { | |
5451 | const struct mips_check_prev_operand *operand; | |
5452 | unsigned int regno; | |
5453 | ||
5454 | operand = (const struct mips_check_prev_operand *) operand_base; | |
5455 | ||
5456 | if (!match_reg (arg, OP_REG_GP, ®no)) | |
5457 | return FALSE; | |
5458 | ||
5459 | if (!operand->zero_ok && regno == 0) | |
5460 | return FALSE; | |
5461 | ||
5462 | if ((operand->less_than_ok && regno < arg->last_regno) | |
5463 | || (operand->greater_than_ok && regno > arg->last_regno) | |
5464 | || (operand->equal_ok && regno == arg->last_regno)) | |
5465 | { | |
5466 | arg->last_regno = regno; | |
5467 | insn_insert_operand (arg->insn, operand_base, regno); | |
5468 | return TRUE; | |
5469 | } | |
5470 | ||
5471 | return FALSE; | |
5472 | } | |
5473 | ||
5474 | /* OP_SAME_RS_RT matcher. */ | |
5475 | ||
5476 | static bfd_boolean | |
5477 | match_same_rs_rt_operand (struct mips_arg_info *arg, | |
5478 | const struct mips_operand *operand) | |
5479 | { | |
5480 | unsigned int regno; | |
5481 | ||
5482 | if (!match_reg (arg, OP_REG_GP, ®no)) | |
5483 | return FALSE; | |
5484 | ||
5485 | if (regno == 0) | |
5486 | { | |
5487 | set_insn_error (arg->argnum, _("the source register must not be $0")); | |
5488 | return FALSE; | |
5489 | } | |
5490 | ||
5491 | arg->last_regno = regno; | |
5492 | ||
5493 | insn_insert_operand (arg->insn, operand, regno | (regno << 5)); | |
5494 | return TRUE; | |
5495 | } | |
5496 | ||
a1d78564 RS |
5497 | /* OP_LWM_SWM_LIST matcher. */ |
5498 | ||
a92713e6 | 5499 | static bfd_boolean |
a1d78564 | 5500 | match_lwm_swm_list_operand (struct mips_arg_info *arg, |
a92713e6 | 5501 | const struct mips_operand *operand) |
a1d78564 | 5502 | { |
a92713e6 RS |
5503 | unsigned int reglist, sregs, ra, regno1, regno2; |
5504 | struct mips_arg_info reset; | |
a1d78564 | 5505 | |
a92713e6 RS |
5506 | reglist = 0; |
5507 | if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2)) | |
5508 | return FALSE; | |
5509 | do | |
5510 | { | |
5511 | if (regno2 == FP && regno1 >= S0 && regno1 <= S7) | |
5512 | { | |
5513 | reglist |= 1 << FP; | |
5514 | regno2 = S7; | |
5515 | } | |
5516 | reglist |= ((1U << regno2 << 1) - 1) & -(1U << regno1); | |
5517 | reset = *arg; | |
5518 | } | |
5519 | while (match_char (arg, ',') | |
5520 | && match_reg_range (arg, OP_REG_GP, ®no1, ®no2)); | |
5521 | *arg = reset; | |
a1d78564 RS |
5522 | |
5523 | if (operand->size == 2) | |
5524 | { | |
5525 | /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.: | |
5526 | ||
5527 | s0, ra | |
5528 | s0, s1, ra, s2, s3 | |
5529 | s0-s2, ra | |
5530 | ||
5531 | and any permutations of these. */ | |
5532 | if ((reglist & 0xfff1ffff) != 0x80010000) | |
a92713e6 | 5533 | return FALSE; |
a1d78564 RS |
5534 | |
5535 | sregs = (reglist >> 17) & 7; | |
5536 | ra = 0; | |
5537 | } | |
5538 | else | |
5539 | { | |
5540 | /* The list must include at least one of ra and s0-sN, | |
5541 | for 0 <= N <= 8. (Note that there is a gap between s7 and s8, | |
5542 | which are $23 and $30 respectively.) E.g.: | |
5543 | ||
5544 | ra | |
5545 | s0 | |
5546 | ra, s0, s1, s2 | |
5547 | s0-s8 | |
5548 | s0-s5, ra | |
5549 | ||
5550 | and any permutations of these. */ | |
5551 | if ((reglist & 0x3f00ffff) != 0) | |
a92713e6 | 5552 | return FALSE; |
a1d78564 RS |
5553 | |
5554 | ra = (reglist >> 27) & 0x10; | |
5555 | sregs = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff); | |
5556 | } | |
5557 | sregs += 1; | |
5558 | if ((sregs & -sregs) != sregs) | |
a92713e6 | 5559 | return FALSE; |
a1d78564 RS |
5560 | |
5561 | insn_insert_operand (arg->insn, operand, (ffs (sregs) - 1) | ra); | |
a92713e6 | 5562 | return TRUE; |
a1d78564 RS |
5563 | } |
5564 | ||
364215c8 RS |
5565 | /* OP_ENTRY_EXIT_LIST matcher. */ |
5566 | ||
a92713e6 | 5567 | static unsigned int |
364215c8 | 5568 | match_entry_exit_operand (struct mips_arg_info *arg, |
a92713e6 | 5569 | const struct mips_operand *operand) |
364215c8 RS |
5570 | { |
5571 | unsigned int mask; | |
5572 | bfd_boolean is_exit; | |
5573 | ||
5574 | /* The format is the same for both ENTRY and EXIT, but the constraints | |
5575 | are different. */ | |
5576 | is_exit = strcmp (arg->insn->insn_mo->name, "exit") == 0; | |
5577 | mask = (is_exit ? 7 << 3 : 0); | |
a92713e6 | 5578 | do |
364215c8 RS |
5579 | { |
5580 | unsigned int regno1, regno2; | |
5581 | bfd_boolean is_freg; | |
5582 | ||
a92713e6 | 5583 | if (match_reg_range (arg, OP_REG_GP, ®no1, ®no2)) |
364215c8 | 5584 | is_freg = FALSE; |
a92713e6 | 5585 | else if (match_reg_range (arg, OP_REG_FP, ®no1, ®no2)) |
364215c8 RS |
5586 | is_freg = TRUE; |
5587 | else | |
a92713e6 | 5588 | return FALSE; |
364215c8 RS |
5589 | |
5590 | if (is_exit && is_freg && regno1 == 0 && regno2 < 2) | |
5591 | { | |
5592 | mask &= ~(7 << 3); | |
5593 | mask |= (5 + regno2) << 3; | |
5594 | } | |
5595 | else if (!is_exit && regno1 == 4 && regno2 >= 4 && regno2 <= 7) | |
5596 | mask |= (regno2 - 3) << 3; | |
5597 | else if (regno1 == 16 && regno2 >= 16 && regno2 <= 17) | |
5598 | mask |= (regno2 - 15) << 1; | |
5599 | else if (regno1 == RA && regno2 == RA) | |
5600 | mask |= 1; | |
5601 | else | |
a92713e6 | 5602 | return FALSE; |
364215c8 | 5603 | } |
a92713e6 RS |
5604 | while (match_char (arg, ',')); |
5605 | ||
364215c8 | 5606 | insn_insert_operand (arg->insn, operand, mask); |
a92713e6 | 5607 | return TRUE; |
364215c8 RS |
5608 | } |
5609 | ||
38bf472a MR |
5610 | /* Encode regular MIPS SAVE/RESTORE instruction operands according to |
5611 | the argument register mask AMASK, the number of static registers | |
5612 | saved NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1 | |
5613 | respectively, and the frame size FRAME_SIZE. */ | |
5614 | ||
5615 | static unsigned int | |
5616 | mips_encode_save_restore (unsigned int amask, unsigned int nsreg, | |
5617 | unsigned int ra, unsigned int s0, unsigned int s1, | |
5618 | unsigned int frame_size) | |
5619 | { | |
5620 | return ((nsreg << 23) | ((frame_size & 0xf0) << 15) | (amask << 15) | |
5621 | | (ra << 12) | (s0 << 11) | (s1 << 10) | ((frame_size & 0xf) << 6)); | |
5622 | } | |
5623 | ||
5624 | /* Encode MIPS16 SAVE/RESTORE instruction operands according to the | |
5625 | argument register mask AMASK, the number of static registers saved | |
5626 | NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1 | |
5627 | respectively, and the frame size FRAME_SIZE. */ | |
5628 | ||
5629 | static unsigned int | |
5630 | mips16_encode_save_restore (unsigned int amask, unsigned int nsreg, | |
5631 | unsigned int ra, unsigned int s0, unsigned int s1, | |
5632 | unsigned int frame_size) | |
5633 | { | |
5634 | unsigned int args; | |
5635 | ||
5636 | args = (ra << 6) | (s0 << 5) | (s1 << 4) | (frame_size & 0xf); | |
5637 | if (nsreg || amask || frame_size == 0 || frame_size > 16) | |
5638 | args |= (MIPS16_EXTEND | (nsreg << 24) | (amask << 16) | |
5639 | | ((frame_size & 0xf0) << 16)); | |
5640 | return args; | |
5641 | } | |
5642 | ||
364215c8 RS |
5643 | /* OP_SAVE_RESTORE_LIST matcher. */ |
5644 | ||
a92713e6 RS |
5645 | static bfd_boolean |
5646 | match_save_restore_list_operand (struct mips_arg_info *arg) | |
364215c8 RS |
5647 | { |
5648 | unsigned int opcode, args, statics, sregs; | |
5649 | unsigned int num_frame_sizes, num_args, num_statics, num_sregs; | |
38bf472a | 5650 | unsigned int arg_mask, ra, s0, s1; |
364215c8 | 5651 | offsetT frame_size; |
364215c8 | 5652 | |
364215c8 RS |
5653 | opcode = arg->insn->insn_opcode; |
5654 | frame_size = 0; | |
5655 | num_frame_sizes = 0; | |
5656 | args = 0; | |
5657 | statics = 0; | |
5658 | sregs = 0; | |
38bf472a MR |
5659 | ra = 0; |
5660 | s0 = 0; | |
5661 | s1 = 0; | |
a92713e6 | 5662 | do |
364215c8 RS |
5663 | { |
5664 | unsigned int regno1, regno2; | |
5665 | ||
a92713e6 | 5666 | if (arg->token->type == OT_INTEGER) |
364215c8 RS |
5667 | { |
5668 | /* Handle the frame size. */ | |
1a00e612 | 5669 | if (!match_const_int (arg, &frame_size)) |
a92713e6 | 5670 | return FALSE; |
364215c8 | 5671 | num_frame_sizes += 1; |
364215c8 RS |
5672 | } |
5673 | else | |
5674 | { | |
a92713e6 RS |
5675 | if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2)) |
5676 | return FALSE; | |
364215c8 RS |
5677 | |
5678 | while (regno1 <= regno2) | |
5679 | { | |
5680 | if (regno1 >= 4 && regno1 <= 7) | |
5681 | { | |
5682 | if (num_frame_sizes == 0) | |
5683 | /* args $a0-$a3 */ | |
5684 | args |= 1 << (regno1 - 4); | |
5685 | else | |
5686 | /* statics $a0-$a3 */ | |
5687 | statics |= 1 << (regno1 - 4); | |
5688 | } | |
5689 | else if (regno1 >= 16 && regno1 <= 23) | |
5690 | /* $s0-$s7 */ | |
5691 | sregs |= 1 << (regno1 - 16); | |
5692 | else if (regno1 == 30) | |
5693 | /* $s8 */ | |
5694 | sregs |= 1 << 8; | |
5695 | else if (regno1 == 31) | |
5696 | /* Add $ra to insn. */ | |
38bf472a | 5697 | ra = 1; |
364215c8 | 5698 | else |
a92713e6 | 5699 | return FALSE; |
364215c8 RS |
5700 | regno1 += 1; |
5701 | if (regno1 == 24) | |
5702 | regno1 = 30; | |
5703 | } | |
5704 | } | |
364215c8 | 5705 | } |
a92713e6 | 5706 | while (match_char (arg, ',')); |
364215c8 RS |
5707 | |
5708 | /* Encode args/statics combination. */ | |
5709 | if (args & statics) | |
a92713e6 | 5710 | return FALSE; |
364215c8 RS |
5711 | else if (args == 0xf) |
5712 | /* All $a0-$a3 are args. */ | |
38bf472a | 5713 | arg_mask = MIPS_SVRS_ALL_ARGS; |
364215c8 RS |
5714 | else if (statics == 0xf) |
5715 | /* All $a0-$a3 are statics. */ | |
38bf472a | 5716 | arg_mask = MIPS_SVRS_ALL_STATICS; |
364215c8 RS |
5717 | else |
5718 | { | |
5719 | /* Count arg registers. */ | |
5720 | num_args = 0; | |
5721 | while (args & 0x1) | |
5722 | { | |
5723 | args >>= 1; | |
5724 | num_args += 1; | |
5725 | } | |
5726 | if (args != 0) | |
a92713e6 | 5727 | return FALSE; |
364215c8 RS |
5728 | |
5729 | /* Count static registers. */ | |
5730 | num_statics = 0; | |
5731 | while (statics & 0x8) | |
5732 | { | |
5733 | statics = (statics << 1) & 0xf; | |
5734 | num_statics += 1; | |
5735 | } | |
5736 | if (statics != 0) | |
a92713e6 | 5737 | return FALSE; |
364215c8 RS |
5738 | |
5739 | /* Encode args/statics. */ | |
38bf472a | 5740 | arg_mask = (num_args << 2) | num_statics; |
364215c8 RS |
5741 | } |
5742 | ||
5743 | /* Encode $s0/$s1. */ | |
5744 | if (sregs & (1 << 0)) /* $s0 */ | |
38bf472a | 5745 | s0 = 1; |
364215c8 | 5746 | if (sregs & (1 << 1)) /* $s1 */ |
38bf472a | 5747 | s1 = 1; |
364215c8 RS |
5748 | sregs >>= 2; |
5749 | ||
5750 | /* Encode $s2-$s8. */ | |
5751 | num_sregs = 0; | |
5752 | while (sregs & 1) | |
5753 | { | |
5754 | sregs >>= 1; | |
5755 | num_sregs += 1; | |
5756 | } | |
5757 | if (sregs != 0) | |
a92713e6 | 5758 | return FALSE; |
364215c8 RS |
5759 | |
5760 | /* Encode frame size. */ | |
5761 | if (num_frame_sizes == 0) | |
1a00e612 RS |
5762 | { |
5763 | set_insn_error (arg->argnum, _("missing frame size")); | |
5764 | return FALSE; | |
5765 | } | |
5766 | if (num_frame_sizes > 1) | |
5767 | { | |
5768 | set_insn_error (arg->argnum, _("frame size specified twice")); | |
5769 | return FALSE; | |
5770 | } | |
5771 | if ((frame_size & 7) != 0 || frame_size < 0 || frame_size > 0xff * 8) | |
5772 | { | |
5773 | set_insn_error (arg->argnum, _("invalid frame size")); | |
5774 | return FALSE; | |
5775 | } | |
38bf472a | 5776 | frame_size /= 8; |
364215c8 | 5777 | |
364215c8 | 5778 | /* Finally build the instruction. */ |
38bf472a MR |
5779 | if (mips_opts.mips16) |
5780 | opcode |= mips16_encode_save_restore (arg_mask, num_sregs, ra, s0, s1, | |
5781 | frame_size); | |
5782 | else if (!mips_opts.micromips) | |
5783 | opcode |= mips_encode_save_restore (arg_mask, num_sregs, ra, s0, s1, | |
5784 | frame_size); | |
5785 | else | |
5786 | abort (); | |
5787 | ||
364215c8 | 5788 | arg->insn->insn_opcode = opcode; |
a92713e6 | 5789 | return TRUE; |
364215c8 RS |
5790 | } |
5791 | ||
a1d78564 RS |
5792 | /* OP_MDMX_IMM_REG matcher. */ |
5793 | ||
a92713e6 | 5794 | static bfd_boolean |
a1d78564 | 5795 | match_mdmx_imm_reg_operand (struct mips_arg_info *arg, |
a92713e6 | 5796 | const struct mips_operand *operand) |
a1d78564 | 5797 | { |
a92713e6 | 5798 | unsigned int regno, uval; |
a1d78564 RS |
5799 | bfd_boolean is_qh; |
5800 | const struct mips_opcode *opcode; | |
5801 | ||
5802 | /* The mips_opcode records whether this is an octobyte or quadhalf | |
5803 | instruction. Start out with that bit in place. */ | |
5804 | opcode = arg->insn->insn_mo; | |
5805 | uval = mips_extract_operand (operand, opcode->match); | |
5806 | is_qh = (uval != 0); | |
5807 | ||
56d438b1 | 5808 | if (arg->token->type == OT_REG) |
a1d78564 RS |
5809 | { |
5810 | if ((opcode->membership & INSN_5400) | |
5811 | && strcmp (opcode->name, "rzu.ob") == 0) | |
5812 | { | |
1a00e612 RS |
5813 | set_insn_error_i (arg->argnum, _("operand %d must be an immediate"), |
5814 | arg->argnum); | |
5815 | return FALSE; | |
a1d78564 RS |
5816 | } |
5817 | ||
56d438b1 CF |
5818 | if (!match_regno (arg, OP_REG_VEC, arg->token->u.regno, ®no)) |
5819 | return FALSE; | |
5820 | ++arg->token; | |
5821 | ||
a1d78564 RS |
5822 | /* Check whether this is a vector register or a broadcast of |
5823 | a single element. */ | |
56d438b1 | 5824 | if (arg->token->type == OT_INTEGER_INDEX) |
a1d78564 | 5825 | { |
56d438b1 | 5826 | if (arg->token->u.index > (is_qh ? 3 : 7)) |
a1d78564 | 5827 | { |
1a00e612 RS |
5828 | set_insn_error (arg->argnum, _("invalid element selector")); |
5829 | return FALSE; | |
a1d78564 | 5830 | } |
56d438b1 CF |
5831 | uval |= arg->token->u.index << (is_qh ? 2 : 1) << 5; |
5832 | ++arg->token; | |
a1d78564 RS |
5833 | } |
5834 | else | |
5835 | { | |
5836 | /* A full vector. */ | |
5837 | if ((opcode->membership & INSN_5400) | |
5838 | && (strcmp (opcode->name, "sll.ob") == 0 | |
5839 | || strcmp (opcode->name, "srl.ob") == 0)) | |
5840 | { | |
1a00e612 RS |
5841 | set_insn_error_i (arg->argnum, _("operand %d must be scalar"), |
5842 | arg->argnum); | |
5843 | return FALSE; | |
a1d78564 RS |
5844 | } |
5845 | ||
5846 | if (is_qh) | |
5847 | uval |= MDMX_FMTSEL_VEC_QH << 5; | |
5848 | else | |
5849 | uval |= MDMX_FMTSEL_VEC_OB << 5; | |
5850 | } | |
a1d78564 RS |
5851 | uval |= regno; |
5852 | } | |
5853 | else | |
5854 | { | |
5855 | offsetT sval; | |
5856 | ||
1a00e612 | 5857 | if (!match_const_int (arg, &sval)) |
a92713e6 | 5858 | return FALSE; |
a1d78564 RS |
5859 | if (sval < 0 || sval > 31) |
5860 | { | |
1a00e612 RS |
5861 | match_out_of_range (arg); |
5862 | return FALSE; | |
a1d78564 RS |
5863 | } |
5864 | uval |= (sval & 31); | |
5865 | if (is_qh) | |
5866 | uval |= MDMX_FMTSEL_IMM_QH << 5; | |
5867 | else | |
5868 | uval |= MDMX_FMTSEL_IMM_OB << 5; | |
5869 | } | |
5870 | insn_insert_operand (arg->insn, operand, uval); | |
a92713e6 | 5871 | return TRUE; |
a1d78564 RS |
5872 | } |
5873 | ||
56d438b1 CF |
5874 | /* OP_IMM_INDEX matcher. */ |
5875 | ||
5876 | static bfd_boolean | |
5877 | match_imm_index_operand (struct mips_arg_info *arg, | |
5878 | const struct mips_operand *operand) | |
5879 | { | |
5880 | unsigned int max_val; | |
5881 | ||
5882 | if (arg->token->type != OT_INTEGER_INDEX) | |
5883 | return FALSE; | |
5884 | ||
5885 | max_val = (1 << operand->size) - 1; | |
5886 | if (arg->token->u.index > max_val) | |
5887 | { | |
5888 | match_out_of_range (arg); | |
5889 | return FALSE; | |
5890 | } | |
5891 | insn_insert_operand (arg->insn, operand, arg->token->u.index); | |
5892 | ++arg->token; | |
5893 | return TRUE; | |
5894 | } | |
5895 | ||
5896 | /* OP_REG_INDEX matcher. */ | |
5897 | ||
5898 | static bfd_boolean | |
5899 | match_reg_index_operand (struct mips_arg_info *arg, | |
5900 | const struct mips_operand *operand) | |
5901 | { | |
5902 | unsigned int regno; | |
5903 | ||
5904 | if (arg->token->type != OT_REG_INDEX) | |
5905 | return FALSE; | |
5906 | ||
5907 | if (!match_regno (arg, OP_REG_GP, arg->token->u.regno, ®no)) | |
5908 | return FALSE; | |
5909 | ||
5910 | insn_insert_operand (arg->insn, operand, regno); | |
5911 | ++arg->token; | |
5912 | return TRUE; | |
5913 | } | |
5914 | ||
a1d78564 RS |
5915 | /* OP_PC matcher. */ |
5916 | ||
a92713e6 RS |
5917 | static bfd_boolean |
5918 | match_pc_operand (struct mips_arg_info *arg) | |
a1d78564 | 5919 | { |
a92713e6 RS |
5920 | if (arg->token->type == OT_REG && (arg->token->u.regno & RTYPE_PC)) |
5921 | { | |
5922 | ++arg->token; | |
5923 | return TRUE; | |
5924 | } | |
5925 | return FALSE; | |
a1d78564 RS |
5926 | } |
5927 | ||
25499ac7 MR |
5928 | /* OP_REG28 matcher. */ |
5929 | ||
5930 | static bfd_boolean | |
5931 | match_reg28_operand (struct mips_arg_info *arg) | |
5932 | { | |
5933 | unsigned int regno; | |
5934 | ||
5935 | if (arg->token->type == OT_REG | |
5936 | && match_regno (arg, OP_REG_GP, arg->token->u.regno, ®no) | |
5937 | && regno == GP) | |
5938 | { | |
5939 | ++arg->token; | |
5940 | return TRUE; | |
5941 | } | |
5942 | return FALSE; | |
5943 | } | |
5944 | ||
7361da2c AB |
5945 | /* OP_NON_ZERO_REG matcher. */ |
5946 | ||
5947 | static bfd_boolean | |
5948 | match_non_zero_reg_operand (struct mips_arg_info *arg, | |
5949 | const struct mips_operand *operand) | |
5950 | { | |
5951 | unsigned int regno; | |
5952 | ||
5953 | if (!match_reg (arg, OP_REG_GP, ®no)) | |
5954 | return FALSE; | |
5955 | ||
5956 | if (regno == 0) | |
5957 | return FALSE; | |
5958 | ||
5959 | arg->last_regno = regno; | |
5960 | insn_insert_operand (arg->insn, operand, regno); | |
5961 | return TRUE; | |
5962 | } | |
5963 | ||
a1d78564 RS |
5964 | /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the |
5965 | register that we need to match. */ | |
5966 | ||
a92713e6 RS |
5967 | static bfd_boolean |
5968 | match_tied_reg_operand (struct mips_arg_info *arg, unsigned int other_regno) | |
a1d78564 RS |
5969 | { |
5970 | unsigned int regno; | |
5971 | ||
a92713e6 | 5972 | return match_reg (arg, OP_REG_GP, ®no) && regno == other_regno; |
a1d78564 RS |
5973 | } |
5974 | ||
33f46696 MR |
5975 | /* Try to match a floating-point constant from ARG for LI.S or LI.D. |
5976 | LENGTH is the length of the value in bytes (4 for float, 8 for double) | |
5977 | and USING_GPRS says whether the destination is a GPR rather than an FPR. | |
89565f1b RS |
5978 | |
5979 | Return the constant in IMM and OFFSET as follows: | |
5980 | ||
5981 | - If the constant should be loaded via memory, set IMM to O_absent and | |
5982 | OFFSET to the memory address. | |
5983 | ||
5984 | - Otherwise, if the constant should be loaded into two 32-bit registers, | |
5985 | set IMM to the O_constant to load into the high register and OFFSET | |
5986 | to the corresponding value for the low register. | |
5987 | ||
5988 | - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent. | |
5989 | ||
5990 | These constants only appear as the last operand in an instruction, | |
5991 | and every instruction that accepts them in any variant accepts them | |
5992 | in all variants. This means we don't have to worry about backing out | |
5993 | any changes if the instruction does not match. We just match | |
5994 | unconditionally and report an error if the constant is invalid. */ | |
5995 | ||
a92713e6 RS |
5996 | static bfd_boolean |
5997 | match_float_constant (struct mips_arg_info *arg, expressionS *imm, | |
5998 | expressionS *offset, int length, bfd_boolean using_gprs) | |
89565f1b | 5999 | { |
a92713e6 | 6000 | char *p; |
89565f1b RS |
6001 | segT seg, new_seg; |
6002 | subsegT subseg; | |
6003 | const char *newname; | |
a92713e6 | 6004 | unsigned char *data; |
89565f1b RS |
6005 | |
6006 | /* Where the constant is placed is based on how the MIPS assembler | |
6007 | does things: | |
6008 | ||
6009 | length == 4 && using_gprs -- immediate value only | |
6010 | length == 8 && using_gprs -- .rdata or immediate value | |
6011 | length == 4 && !using_gprs -- .lit4 or immediate value | |
6012 | length == 8 && !using_gprs -- .lit8 or immediate value | |
6013 | ||
6014 | The .lit4 and .lit8 sections are only used if permitted by the | |
6015 | -G argument. */ | |
a92713e6 | 6016 | if (arg->token->type != OT_FLOAT) |
1a00e612 RS |
6017 | { |
6018 | set_insn_error (arg->argnum, _("floating-point expression required")); | |
6019 | return FALSE; | |
6020 | } | |
a92713e6 RS |
6021 | |
6022 | gas_assert (arg->token->u.flt.length == length); | |
6023 | data = arg->token->u.flt.data; | |
6024 | ++arg->token; | |
89565f1b RS |
6025 | |
6026 | /* Handle 32-bit constants for which an immediate value is best. */ | |
6027 | if (length == 4 | |
6028 | && (using_gprs | |
6029 | || g_switch_value < 4 | |
6030 | || (data[0] == 0 && data[1] == 0) | |
6031 | || (data[2] == 0 && data[3] == 0))) | |
6032 | { | |
6033 | imm->X_op = O_constant; | |
6034 | if (!target_big_endian) | |
6035 | imm->X_add_number = bfd_getl32 (data); | |
6036 | else | |
6037 | imm->X_add_number = bfd_getb32 (data); | |
6038 | offset->X_op = O_absent; | |
a92713e6 | 6039 | return TRUE; |
89565f1b RS |
6040 | } |
6041 | ||
6042 | /* Handle 64-bit constants for which an immediate value is best. */ | |
6043 | if (length == 8 | |
6044 | && !mips_disable_float_construction | |
351cdf24 MF |
6045 | /* Constants can only be constructed in GPRs and copied to FPRs if the |
6046 | GPRs are at least as wide as the FPRs or MTHC1 is available. | |
6047 | Unlike most tests for 32-bit floating-point registers this check | |
6048 | specifically looks for GPR_SIZE == 32 as the FPXX ABI does not | |
6049 | permit 64-bit moves without MXHC1. | |
6050 | Force the constant into memory otherwise. */ | |
6051 | && (using_gprs | |
6052 | || GPR_SIZE == 64 | |
6053 | || ISA_HAS_MXHC1 (mips_opts.isa) | |
6054 | || FPR_SIZE == 32) | |
89565f1b RS |
6055 | && ((data[0] == 0 && data[1] == 0) |
6056 | || (data[2] == 0 && data[3] == 0)) | |
6057 | && ((data[4] == 0 && data[5] == 0) | |
6058 | || (data[6] == 0 && data[7] == 0))) | |
6059 | { | |
6060 | /* The value is simple enough to load with a couple of instructions. | |
6061 | If using 32-bit registers, set IMM to the high order 32 bits and | |
6062 | OFFSET to the low order 32 bits. Otherwise, set IMM to the entire | |
6063 | 64 bit constant. */ | |
351cdf24 | 6064 | if (GPR_SIZE == 32 || (!using_gprs && FPR_SIZE != 64)) |
89565f1b RS |
6065 | { |
6066 | imm->X_op = O_constant; | |
6067 | offset->X_op = O_constant; | |
6068 | if (!target_big_endian) | |
6069 | { | |
6070 | imm->X_add_number = bfd_getl32 (data + 4); | |
6071 | offset->X_add_number = bfd_getl32 (data); | |
6072 | } | |
6073 | else | |
6074 | { | |
6075 | imm->X_add_number = bfd_getb32 (data); | |
6076 | offset->X_add_number = bfd_getb32 (data + 4); | |
6077 | } | |
6078 | if (offset->X_add_number == 0) | |
6079 | offset->X_op = O_absent; | |
6080 | } | |
6081 | else | |
6082 | { | |
6083 | imm->X_op = O_constant; | |
6084 | if (!target_big_endian) | |
6085 | imm->X_add_number = bfd_getl64 (data); | |
6086 | else | |
6087 | imm->X_add_number = bfd_getb64 (data); | |
6088 | offset->X_op = O_absent; | |
6089 | } | |
a92713e6 | 6090 | return TRUE; |
89565f1b RS |
6091 | } |
6092 | ||
6093 | /* Switch to the right section. */ | |
6094 | seg = now_seg; | |
6095 | subseg = now_subseg; | |
6096 | if (length == 4) | |
6097 | { | |
6098 | gas_assert (!using_gprs && g_switch_value >= 4); | |
6099 | newname = ".lit4"; | |
6100 | } | |
6101 | else | |
6102 | { | |
6103 | if (using_gprs || g_switch_value < 8) | |
6104 | newname = RDATA_SECTION_NAME; | |
6105 | else | |
6106 | newname = ".lit8"; | |
6107 | } | |
6108 | ||
6109 | new_seg = subseg_new (newname, (subsegT) 0); | |
6110 | bfd_set_section_flags (stdoutput, new_seg, | |
6111 | SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_DATA); | |
6112 | frag_align (length == 4 ? 2 : 3, 0, 0); | |
6113 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
6114 | record_alignment (new_seg, 4); | |
6115 | else | |
6116 | record_alignment (new_seg, length == 4 ? 2 : 3); | |
6117 | if (seg == now_seg) | |
1661c76c | 6118 | as_bad (_("cannot use `%s' in this section"), arg->insn->insn_mo->name); |
89565f1b RS |
6119 | |
6120 | /* Set the argument to the current address in the section. */ | |
6121 | imm->X_op = O_absent; | |
6122 | offset->X_op = O_symbol; | |
6123 | offset->X_add_symbol = symbol_temp_new_now (); | |
6124 | offset->X_add_number = 0; | |
6125 | ||
6126 | /* Put the floating point number into the section. */ | |
6127 | p = frag_more (length); | |
6128 | memcpy (p, data, length); | |
6129 | ||
6130 | /* Switch back to the original section. */ | |
6131 | subseg_set (seg, subseg); | |
a92713e6 | 6132 | return TRUE; |
89565f1b RS |
6133 | } |
6134 | ||
14daeee3 RS |
6135 | /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between |
6136 | them. */ | |
6137 | ||
6138 | static bfd_boolean | |
6139 | match_vu0_suffix_operand (struct mips_arg_info *arg, | |
6140 | const struct mips_operand *operand, | |
6141 | bfd_boolean match_p) | |
6142 | { | |
6143 | unsigned int uval; | |
6144 | ||
6145 | /* The operand can be an XYZW mask or a single 2-bit channel index | |
6146 | (with X being 0). */ | |
6147 | gas_assert (operand->size == 2 || operand->size == 4); | |
6148 | ||
ee5734f0 | 6149 | /* The suffix can be omitted when it is already part of the opcode. */ |
14daeee3 | 6150 | if (arg->token->type != OT_CHANNELS) |
ee5734f0 | 6151 | return match_p; |
14daeee3 RS |
6152 | |
6153 | uval = arg->token->u.channels; | |
6154 | if (operand->size == 2) | |
6155 | { | |
6156 | /* Check that a single bit is set and convert it into a 2-bit index. */ | |
6157 | if ((uval & -uval) != uval) | |
6158 | return FALSE; | |
6159 | uval = 4 - ffs (uval); | |
6160 | } | |
6161 | ||
6162 | if (match_p && insn_extract_operand (arg->insn, operand) != uval) | |
6163 | return FALSE; | |
6164 | ||
6165 | ++arg->token; | |
6166 | if (!match_p) | |
6167 | insn_insert_operand (arg->insn, operand, uval); | |
6168 | return TRUE; | |
6169 | } | |
6170 | ||
33f46696 MR |
6171 | /* Try to match a token from ARG against OPERAND. Consume the token |
6172 | and return true on success, otherwise return false. */ | |
a1d78564 | 6173 | |
a92713e6 | 6174 | static bfd_boolean |
a1d78564 | 6175 | match_operand (struct mips_arg_info *arg, |
a92713e6 | 6176 | const struct mips_operand *operand) |
a1d78564 RS |
6177 | { |
6178 | switch (operand->type) | |
6179 | { | |
6180 | case OP_INT: | |
a92713e6 | 6181 | return match_int_operand (arg, operand); |
a1d78564 RS |
6182 | |
6183 | case OP_MAPPED_INT: | |
a92713e6 | 6184 | return match_mapped_int_operand (arg, operand); |
a1d78564 RS |
6185 | |
6186 | case OP_MSB: | |
a92713e6 | 6187 | return match_msb_operand (arg, operand); |
a1d78564 RS |
6188 | |
6189 | case OP_REG: | |
0f35dbc4 | 6190 | case OP_OPTIONAL_REG: |
a92713e6 | 6191 | return match_reg_operand (arg, operand); |
a1d78564 RS |
6192 | |
6193 | case OP_REG_PAIR: | |
a92713e6 | 6194 | return match_reg_pair_operand (arg, operand); |
a1d78564 RS |
6195 | |
6196 | case OP_PCREL: | |
a92713e6 | 6197 | return match_pcrel_operand (arg); |
a1d78564 RS |
6198 | |
6199 | case OP_PERF_REG: | |
a92713e6 | 6200 | return match_perf_reg_operand (arg, operand); |
a1d78564 RS |
6201 | |
6202 | case OP_ADDIUSP_INT: | |
a92713e6 | 6203 | return match_addiusp_operand (arg, operand); |
a1d78564 RS |
6204 | |
6205 | case OP_CLO_CLZ_DEST: | |
a92713e6 | 6206 | return match_clo_clz_dest_operand (arg, operand); |
a1d78564 RS |
6207 | |
6208 | case OP_LWM_SWM_LIST: | |
a92713e6 | 6209 | return match_lwm_swm_list_operand (arg, operand); |
a1d78564 RS |
6210 | |
6211 | case OP_ENTRY_EXIT_LIST: | |
a92713e6 | 6212 | return match_entry_exit_operand (arg, operand); |
364215c8 | 6213 | |
a1d78564 | 6214 | case OP_SAVE_RESTORE_LIST: |
a92713e6 | 6215 | return match_save_restore_list_operand (arg); |
a1d78564 RS |
6216 | |
6217 | case OP_MDMX_IMM_REG: | |
a92713e6 | 6218 | return match_mdmx_imm_reg_operand (arg, operand); |
a1d78564 RS |
6219 | |
6220 | case OP_REPEAT_DEST_REG: | |
a92713e6 | 6221 | return match_tied_reg_operand (arg, arg->dest_regno); |
a1d78564 RS |
6222 | |
6223 | case OP_REPEAT_PREV_REG: | |
a92713e6 | 6224 | return match_tied_reg_operand (arg, arg->last_regno); |
a1d78564 RS |
6225 | |
6226 | case OP_PC: | |
a92713e6 | 6227 | return match_pc_operand (arg); |
14daeee3 | 6228 | |
25499ac7 MR |
6229 | case OP_REG28: |
6230 | return match_reg28_operand (arg); | |
6231 | ||
14daeee3 RS |
6232 | case OP_VU0_SUFFIX: |
6233 | return match_vu0_suffix_operand (arg, operand, FALSE); | |
6234 | ||
6235 | case OP_VU0_MATCH_SUFFIX: | |
6236 | return match_vu0_suffix_operand (arg, operand, TRUE); | |
56d438b1 CF |
6237 | |
6238 | case OP_IMM_INDEX: | |
6239 | return match_imm_index_operand (arg, operand); | |
6240 | ||
6241 | case OP_REG_INDEX: | |
6242 | return match_reg_index_operand (arg, operand); | |
7361da2c AB |
6243 | |
6244 | case OP_SAME_RS_RT: | |
6245 | return match_same_rs_rt_operand (arg, operand); | |
6246 | ||
6247 | case OP_CHECK_PREV: | |
6248 | return match_check_prev_operand (arg, operand); | |
6249 | ||
6250 | case OP_NON_ZERO_REG: | |
6251 | return match_non_zero_reg_operand (arg, operand); | |
a1d78564 RS |
6252 | } |
6253 | abort (); | |
6254 | } | |
6255 | ||
6256 | /* ARG is the state after successfully matching an instruction. | |
6257 | Issue any queued-up warnings. */ | |
6258 | ||
6259 | static void | |
6260 | check_completed_insn (struct mips_arg_info *arg) | |
6261 | { | |
6262 | if (arg->seen_at) | |
6263 | { | |
6264 | if (AT == ATREG) | |
1661c76c | 6265 | as_warn (_("used $at without \".set noat\"")); |
a1d78564 | 6266 | else |
1661c76c | 6267 | as_warn (_("used $%u with \".set at=$%u\""), AT, AT); |
a1d78564 RS |
6268 | } |
6269 | } | |
a1d78564 | 6270 | |
85fcb30f RS |
6271 | /* Return true if modifying general-purpose register REG needs a delay. */ |
6272 | ||
6273 | static bfd_boolean | |
6274 | reg_needs_delay (unsigned int reg) | |
6275 | { | |
6276 | unsigned long prev_pinfo; | |
6277 | ||
6278 | prev_pinfo = history[0].insn_mo->pinfo; | |
6279 | if (!mips_opts.noreorder | |
67dc82bc | 6280 | && (((prev_pinfo & INSN_LOAD_MEMORY) && !gpr_interlocks) |
43885403 | 6281 | || ((prev_pinfo & INSN_LOAD_COPROC) && !cop_interlocks)) |
85fcb30f RS |
6282 | && (gpr_write_mask (&history[0]) & (1 << reg))) |
6283 | return TRUE; | |
6284 | ||
6285 | return FALSE; | |
6286 | } | |
6287 | ||
71400594 RS |
6288 | /* Classify an instruction according to the FIX_VR4120_* enumeration. |
6289 | Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected | |
6290 | by VR4120 errata. */ | |
4d7206a2 | 6291 | |
71400594 RS |
6292 | static unsigned int |
6293 | classify_vr4120_insn (const char *name) | |
252b5132 | 6294 | { |
71400594 RS |
6295 | if (strncmp (name, "macc", 4) == 0) |
6296 | return FIX_VR4120_MACC; | |
6297 | if (strncmp (name, "dmacc", 5) == 0) | |
6298 | return FIX_VR4120_DMACC; | |
6299 | if (strncmp (name, "mult", 4) == 0) | |
6300 | return FIX_VR4120_MULT; | |
6301 | if (strncmp (name, "dmult", 5) == 0) | |
6302 | return FIX_VR4120_DMULT; | |
6303 | if (strstr (name, "div")) | |
6304 | return FIX_VR4120_DIV; | |
6305 | if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) | |
6306 | return FIX_VR4120_MTHILO; | |
6307 | return NUM_FIX_VR4120_CLASSES; | |
6308 | } | |
252b5132 | 6309 | |
a8d14a88 CM |
6310 | #define INSN_ERET 0x42000018 |
6311 | #define INSN_DERET 0x4200001f | |
6312 | #define INSN_DMULT 0x1c | |
6313 | #define INSN_DMULTU 0x1d | |
ff239038 | 6314 | |
71400594 RS |
6315 | /* Return the number of instructions that must separate INSN1 and INSN2, |
6316 | where INSN1 is the earlier instruction. Return the worst-case value | |
6317 | for any INSN2 if INSN2 is null. */ | |
252b5132 | 6318 | |
71400594 RS |
6319 | static unsigned int |
6320 | insns_between (const struct mips_cl_insn *insn1, | |
6321 | const struct mips_cl_insn *insn2) | |
6322 | { | |
6323 | unsigned long pinfo1, pinfo2; | |
4c260379 | 6324 | unsigned int mask; |
71400594 | 6325 | |
85fcb30f RS |
6326 | /* If INFO2 is null, pessimistically assume that all flags are set for |
6327 | the second instruction. */ | |
71400594 RS |
6328 | pinfo1 = insn1->insn_mo->pinfo; |
6329 | pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; | |
252b5132 | 6330 | |
71400594 RS |
6331 | /* For most targets, write-after-read dependencies on the HI and LO |
6332 | registers must be separated by at least two instructions. */ | |
6333 | if (!hilo_interlocks) | |
252b5132 | 6334 | { |
71400594 RS |
6335 | if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) |
6336 | return 2; | |
6337 | if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) | |
6338 | return 2; | |
6339 | } | |
6340 | ||
6341 | /* If we're working around r7000 errata, there must be two instructions | |
6342 | between an mfhi or mflo and any instruction that uses the result. */ | |
6343 | if (mips_7000_hilo_fix | |
df58fc94 | 6344 | && !mips_opts.micromips |
71400594 | 6345 | && MF_HILO_INSN (pinfo1) |
85fcb30f | 6346 | && (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1)))) |
71400594 RS |
6347 | return 2; |
6348 | ||
ff239038 CM |
6349 | /* If we're working around 24K errata, one instruction is required |
6350 | if an ERET or DERET is followed by a branch instruction. */ | |
df58fc94 | 6351 | if (mips_fix_24k && !mips_opts.micromips) |
ff239038 CM |
6352 | { |
6353 | if (insn1->insn_opcode == INSN_ERET | |
6354 | || insn1->insn_opcode == INSN_DERET) | |
6355 | { | |
6356 | if (insn2 == NULL | |
6357 | || insn2->insn_opcode == INSN_ERET | |
6358 | || insn2->insn_opcode == INSN_DERET | |
11625dd8 | 6359 | || delayed_branch_p (insn2)) |
ff239038 CM |
6360 | return 1; |
6361 | } | |
6362 | } | |
6363 | ||
a8d14a88 CM |
6364 | /* If we're working around PMC RM7000 errata, there must be three |
6365 | nops between a dmult and a load instruction. */ | |
6366 | if (mips_fix_rm7000 && !mips_opts.micromips) | |
6367 | { | |
6368 | if ((insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULT | |
6369 | || (insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULTU) | |
6370 | { | |
6371 | if (pinfo2 & INSN_LOAD_MEMORY) | |
6372 | return 3; | |
6373 | } | |
6374 | } | |
6375 | ||
71400594 RS |
6376 | /* If working around VR4120 errata, check for combinations that need |
6377 | a single intervening instruction. */ | |
df58fc94 | 6378 | if (mips_fix_vr4120 && !mips_opts.micromips) |
71400594 RS |
6379 | { |
6380 | unsigned int class1, class2; | |
252b5132 | 6381 | |
71400594 RS |
6382 | class1 = classify_vr4120_insn (insn1->insn_mo->name); |
6383 | if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) | |
252b5132 | 6384 | { |
71400594 RS |
6385 | if (insn2 == NULL) |
6386 | return 1; | |
6387 | class2 = classify_vr4120_insn (insn2->insn_mo->name); | |
6388 | if (vr4120_conflicts[class1] & (1 << class2)) | |
6389 | return 1; | |
252b5132 | 6390 | } |
71400594 RS |
6391 | } |
6392 | ||
df58fc94 | 6393 | if (!HAVE_CODE_COMPRESSION) |
71400594 RS |
6394 | { |
6395 | /* Check for GPR or coprocessor load delays. All such delays | |
6396 | are on the RT register. */ | |
6397 | /* Itbl support may require additional care here. */ | |
67dc82bc | 6398 | if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY)) |
43885403 | 6399 | || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC))) |
252b5132 | 6400 | { |
85fcb30f | 6401 | if (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1))) |
71400594 RS |
6402 | return 1; |
6403 | } | |
6404 | ||
6405 | /* Check for generic coprocessor hazards. | |
6406 | ||
6407 | This case is not handled very well. There is no special | |
6408 | knowledge of CP0 handling, and the coprocessors other than | |
6409 | the floating point unit are not distinguished at all. */ | |
6410 | /* Itbl support may require additional care here. FIXME! | |
6411 | Need to modify this to include knowledge about | |
6412 | user specified delays! */ | |
43885403 | 6413 | else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE)) |
71400594 RS |
6414 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) |
6415 | { | |
6416 | /* Handle cases where INSN1 writes to a known general coprocessor | |
6417 | register. There must be a one instruction delay before INSN2 | |
6418 | if INSN2 reads that register, otherwise no delay is needed. */ | |
4c260379 RS |
6419 | mask = fpr_write_mask (insn1); |
6420 | if (mask != 0) | |
252b5132 | 6421 | { |
4c260379 | 6422 | if (!insn2 || (mask & fpr_read_mask (insn2)) != 0) |
71400594 | 6423 | return 1; |
252b5132 RH |
6424 | } |
6425 | else | |
6426 | { | |
71400594 RS |
6427 | /* Read-after-write dependencies on the control registers |
6428 | require a two-instruction gap. */ | |
6429 | if ((pinfo1 & INSN_WRITE_COND_CODE) | |
6430 | && (pinfo2 & INSN_READ_COND_CODE)) | |
6431 | return 2; | |
6432 | ||
6433 | /* We don't know exactly what INSN1 does. If INSN2 is | |
6434 | also a coprocessor instruction, assume there must be | |
6435 | a one instruction gap. */ | |
6436 | if (pinfo2 & INSN_COP) | |
6437 | return 1; | |
252b5132 RH |
6438 | } |
6439 | } | |
6b76fefe | 6440 | |
71400594 RS |
6441 | /* Check for read-after-write dependencies on the coprocessor |
6442 | control registers in cases where INSN1 does not need a general | |
6443 | coprocessor delay. This means that INSN1 is a floating point | |
6444 | comparison instruction. */ | |
6445 | /* Itbl support may require additional care here. */ | |
6446 | else if (!cop_interlocks | |
6447 | && (pinfo1 & INSN_WRITE_COND_CODE) | |
6448 | && (pinfo2 & INSN_READ_COND_CODE)) | |
6449 | return 1; | |
6450 | } | |
6b76fefe | 6451 | |
7361da2c AB |
6452 | /* Forbidden slots can not contain Control Transfer Instructions (CTIs) |
6453 | CTIs include all branches and jumps, nal, eret, eretnc, deret, wait | |
6454 | and pause. */ | |
6455 | if ((insn1->insn_mo->pinfo2 & INSN2_FORBIDDEN_SLOT) | |
6456 | && ((pinfo2 & INSN_NO_DELAY_SLOT) | |
6457 | || (insn2 && delayed_branch_p (insn2)))) | |
6458 | return 1; | |
6459 | ||
71400594 RS |
6460 | return 0; |
6461 | } | |
6b76fefe | 6462 | |
7d8e00cf RS |
6463 | /* Return the number of nops that would be needed to work around the |
6464 | VR4130 mflo/mfhi errata if instruction INSN immediately followed | |
932d1a1b RS |
6465 | the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards |
6466 | that are contained within the first IGNORE instructions of HIST. */ | |
7d8e00cf RS |
6467 | |
6468 | static int | |
932d1a1b | 6469 | nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist, |
7d8e00cf RS |
6470 | const struct mips_cl_insn *insn) |
6471 | { | |
4c260379 RS |
6472 | int i, j; |
6473 | unsigned int mask; | |
7d8e00cf RS |
6474 | |
6475 | /* Check if the instruction writes to HI or LO. MTHI and MTLO | |
6476 | are not affected by the errata. */ | |
6477 | if (insn != 0 | |
6478 | && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 | |
6479 | || strcmp (insn->insn_mo->name, "mtlo") == 0 | |
6480 | || strcmp (insn->insn_mo->name, "mthi") == 0)) | |
6481 | return 0; | |
6482 | ||
6483 | /* Search for the first MFLO or MFHI. */ | |
6484 | for (i = 0; i < MAX_VR4130_NOPS; i++) | |
91d6fa6a | 6485 | if (MF_HILO_INSN (hist[i].insn_mo->pinfo)) |
7d8e00cf RS |
6486 | { |
6487 | /* Extract the destination register. */ | |
4c260379 | 6488 | mask = gpr_write_mask (&hist[i]); |
7d8e00cf RS |
6489 | |
6490 | /* No nops are needed if INSN reads that register. */ | |
4c260379 | 6491 | if (insn != NULL && (gpr_read_mask (insn) & mask) != 0) |
7d8e00cf RS |
6492 | return 0; |
6493 | ||
6494 | /* ...or if any of the intervening instructions do. */ | |
6495 | for (j = 0; j < i; j++) | |
4c260379 | 6496 | if (gpr_read_mask (&hist[j]) & mask) |
7d8e00cf RS |
6497 | return 0; |
6498 | ||
932d1a1b RS |
6499 | if (i >= ignore) |
6500 | return MAX_VR4130_NOPS - i; | |
7d8e00cf RS |
6501 | } |
6502 | return 0; | |
6503 | } | |
6504 | ||
134c0c8b MR |
6505 | #define BASE_REG_EQ(INSN1, INSN2) \ |
6506 | ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \ | |
15be625d CM |
6507 | == (((INSN2) >> OP_SH_RS) & OP_MASK_RS)) |
6508 | ||
6509 | /* Return the minimum alignment for this store instruction. */ | |
6510 | ||
6511 | static int | |
6512 | fix_24k_align_to (const struct mips_opcode *mo) | |
6513 | { | |
6514 | if (strcmp (mo->name, "sh") == 0) | |
6515 | return 2; | |
6516 | ||
6517 | if (strcmp (mo->name, "swc1") == 0 | |
6518 | || strcmp (mo->name, "swc2") == 0 | |
6519 | || strcmp (mo->name, "sw") == 0 | |
6520 | || strcmp (mo->name, "sc") == 0 | |
6521 | || strcmp (mo->name, "s.s") == 0) | |
6522 | return 4; | |
6523 | ||
6524 | if (strcmp (mo->name, "sdc1") == 0 | |
6525 | || strcmp (mo->name, "sdc2") == 0 | |
6526 | || strcmp (mo->name, "s.d") == 0) | |
6527 | return 8; | |
6528 | ||
6529 | /* sb, swl, swr */ | |
6530 | return 1; | |
6531 | } | |
6532 | ||
6533 | struct fix_24k_store_info | |
6534 | { | |
6535 | /* Immediate offset, if any, for this store instruction. */ | |
6536 | short off; | |
6537 | /* Alignment required by this store instruction. */ | |
6538 | int align_to; | |
6539 | /* True for register offsets. */ | |
6540 | int register_offset; | |
6541 | }; | |
6542 | ||
6543 | /* Comparison function used by qsort. */ | |
6544 | ||
6545 | static int | |
6546 | fix_24k_sort (const void *a, const void *b) | |
6547 | { | |
6548 | const struct fix_24k_store_info *pos1 = a; | |
6549 | const struct fix_24k_store_info *pos2 = b; | |
6550 | ||
6551 | return (pos1->off - pos2->off); | |
6552 | } | |
6553 | ||
6554 | /* INSN is a store instruction. Try to record the store information | |
6555 | in STINFO. Return false if the information isn't known. */ | |
6556 | ||
6557 | static bfd_boolean | |
6558 | fix_24k_record_store_info (struct fix_24k_store_info *stinfo, | |
ab9794cf | 6559 | const struct mips_cl_insn *insn) |
15be625d CM |
6560 | { |
6561 | /* The instruction must have a known offset. */ | |
6562 | if (!insn->complete_p || !strstr (insn->insn_mo->args, "o(")) | |
6563 | return FALSE; | |
6564 | ||
6565 | stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE; | |
6566 | stinfo->align_to = fix_24k_align_to (insn->insn_mo); | |
6567 | return TRUE; | |
6568 | } | |
6569 | ||
932d1a1b RS |
6570 | /* Return the number of nops that would be needed to work around the 24k |
6571 | "lost data on stores during refill" errata if instruction INSN | |
6572 | immediately followed the 2 instructions described by HIST. | |
6573 | Ignore hazards that are contained within the first IGNORE | |
6574 | instructions of HIST. | |
6575 | ||
6576 | Problem: The FSB (fetch store buffer) acts as an intermediate buffer | |
6577 | for the data cache refills and store data. The following describes | |
6578 | the scenario where the store data could be lost. | |
6579 | ||
6580 | * A data cache miss, due to either a load or a store, causing fill | |
6581 | data to be supplied by the memory subsystem | |
6582 | * The first three doublewords of fill data are returned and written | |
6583 | into the cache | |
6584 | * A sequence of four stores occurs in consecutive cycles around the | |
6585 | final doubleword of the fill: | |
6586 | * Store A | |
6587 | * Store B | |
6588 | * Store C | |
6589 | * Zero, One or more instructions | |
6590 | * Store D | |
6591 | ||
6592 | The four stores A-D must be to different doublewords of the line that | |
6593 | is being filled. The fourth instruction in the sequence above permits | |
6594 | the fill of the final doubleword to be transferred from the FSB into | |
6595 | the cache. In the sequence above, the stores may be either integer | |
6596 | (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2, | |
6597 | swxc1, sdxc1, suxc1) stores, as long as the four stores are to | |
6598 | different doublewords on the line. If the floating point unit is | |
6599 | running in 1:2 mode, it is not possible to create the sequence above | |
6600 | using only floating point store instructions. | |
15be625d CM |
6601 | |
6602 | In this case, the cache line being filled is incorrectly marked | |
6603 | invalid, thereby losing the data from any store to the line that | |
6604 | occurs between the original miss and the completion of the five | |
6605 | cycle sequence shown above. | |
6606 | ||
932d1a1b | 6607 | The workarounds are: |
15be625d | 6608 | |
932d1a1b RS |
6609 | * Run the data cache in write-through mode. |
6610 | * Insert a non-store instruction between | |
6611 | Store A and Store B or Store B and Store C. */ | |
3739860c | 6612 | |
15be625d | 6613 | static int |
932d1a1b | 6614 | nops_for_24k (int ignore, const struct mips_cl_insn *hist, |
15be625d CM |
6615 | const struct mips_cl_insn *insn) |
6616 | { | |
6617 | struct fix_24k_store_info pos[3]; | |
6618 | int align, i, base_offset; | |
6619 | ||
932d1a1b RS |
6620 | if (ignore >= 2) |
6621 | return 0; | |
6622 | ||
ab9794cf RS |
6623 | /* If the previous instruction wasn't a store, there's nothing to |
6624 | worry about. */ | |
15be625d CM |
6625 | if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) |
6626 | return 0; | |
6627 | ||
ab9794cf RS |
6628 | /* If the instructions after the previous one are unknown, we have |
6629 | to assume the worst. */ | |
6630 | if (!insn) | |
15be625d CM |
6631 | return 1; |
6632 | ||
ab9794cf RS |
6633 | /* Check whether we are dealing with three consecutive stores. */ |
6634 | if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0 | |
6635 | || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) | |
15be625d CM |
6636 | return 0; |
6637 | ||
6638 | /* If we don't know the relationship between the store addresses, | |
6639 | assume the worst. */ | |
ab9794cf | 6640 | if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode) |
15be625d CM |
6641 | || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode)) |
6642 | return 1; | |
6643 | ||
6644 | if (!fix_24k_record_store_info (&pos[0], insn) | |
6645 | || !fix_24k_record_store_info (&pos[1], &hist[0]) | |
6646 | || !fix_24k_record_store_info (&pos[2], &hist[1])) | |
6647 | return 1; | |
6648 | ||
6649 | qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort); | |
6650 | ||
6651 | /* Pick a value of ALIGN and X such that all offsets are adjusted by | |
6652 | X bytes and such that the base register + X is known to be aligned | |
6653 | to align bytes. */ | |
6654 | ||
6655 | if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP) | |
6656 | align = 8; | |
6657 | else | |
6658 | { | |
6659 | align = pos[0].align_to; | |
6660 | base_offset = pos[0].off; | |
6661 | for (i = 1; i < 3; i++) | |
6662 | if (align < pos[i].align_to) | |
6663 | { | |
6664 | align = pos[i].align_to; | |
6665 | base_offset = pos[i].off; | |
6666 | } | |
6667 | for (i = 0; i < 3; i++) | |
6668 | pos[i].off -= base_offset; | |
6669 | } | |
6670 | ||
6671 | pos[0].off &= ~align + 1; | |
6672 | pos[1].off &= ~align + 1; | |
6673 | pos[2].off &= ~align + 1; | |
6674 | ||
6675 | /* If any two stores write to the same chunk, they also write to the | |
6676 | same doubleword. The offsets are still sorted at this point. */ | |
6677 | if (pos[0].off == pos[1].off || pos[1].off == pos[2].off) | |
6678 | return 0; | |
6679 | ||
6680 | /* A range of at least 9 bytes is needed for the stores to be in | |
6681 | non-overlapping doublewords. */ | |
6682 | if (pos[2].off - pos[0].off <= 8) | |
6683 | return 0; | |
6684 | ||
6685 | if (pos[2].off - pos[1].off >= 24 | |
6686 | || pos[1].off - pos[0].off >= 24 | |
6687 | || pos[2].off - pos[0].off >= 32) | |
6688 | return 0; | |
6689 | ||
6690 | return 1; | |
6691 | } | |
6692 | ||
71400594 | 6693 | /* Return the number of nops that would be needed if instruction INSN |
91d6fa6a | 6694 | immediately followed the MAX_NOPS instructions given by HIST, |
932d1a1b RS |
6695 | where HIST[0] is the most recent instruction. Ignore hazards |
6696 | between INSN and the first IGNORE instructions in HIST. | |
6697 | ||
6698 | If INSN is null, return the worse-case number of nops for any | |
6699 | instruction. */ | |
bdaaa2e1 | 6700 | |
71400594 | 6701 | static int |
932d1a1b | 6702 | nops_for_insn (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
6703 | const struct mips_cl_insn *insn) |
6704 | { | |
6705 | int i, nops, tmp_nops; | |
bdaaa2e1 | 6706 | |
71400594 | 6707 | nops = 0; |
932d1a1b | 6708 | for (i = ignore; i < MAX_DELAY_NOPS; i++) |
65b02341 | 6709 | { |
91d6fa6a | 6710 | tmp_nops = insns_between (hist + i, insn) - i; |
65b02341 RS |
6711 | if (tmp_nops > nops) |
6712 | nops = tmp_nops; | |
6713 | } | |
7d8e00cf | 6714 | |
df58fc94 | 6715 | if (mips_fix_vr4130 && !mips_opts.micromips) |
7d8e00cf | 6716 | { |
932d1a1b | 6717 | tmp_nops = nops_for_vr4130 (ignore, hist, insn); |
7d8e00cf RS |
6718 | if (tmp_nops > nops) |
6719 | nops = tmp_nops; | |
6720 | } | |
6721 | ||
df58fc94 | 6722 | if (mips_fix_24k && !mips_opts.micromips) |
15be625d | 6723 | { |
932d1a1b | 6724 | tmp_nops = nops_for_24k (ignore, hist, insn); |
15be625d CM |
6725 | if (tmp_nops > nops) |
6726 | nops = tmp_nops; | |
6727 | } | |
6728 | ||
71400594 RS |
6729 | return nops; |
6730 | } | |
252b5132 | 6731 | |
71400594 | 6732 | /* The variable arguments provide NUM_INSNS extra instructions that |
91d6fa6a | 6733 | might be added to HIST. Return the largest number of nops that |
932d1a1b RS |
6734 | would be needed after the extended sequence, ignoring hazards |
6735 | in the first IGNORE instructions. */ | |
252b5132 | 6736 | |
71400594 | 6737 | static int |
932d1a1b RS |
6738 | nops_for_sequence (int num_insns, int ignore, |
6739 | const struct mips_cl_insn *hist, ...) | |
71400594 RS |
6740 | { |
6741 | va_list args; | |
6742 | struct mips_cl_insn buffer[MAX_NOPS]; | |
6743 | struct mips_cl_insn *cursor; | |
6744 | int nops; | |
6745 | ||
91d6fa6a | 6746 | va_start (args, hist); |
71400594 | 6747 | cursor = buffer + num_insns; |
91d6fa6a | 6748 | memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor)); |
71400594 RS |
6749 | while (cursor > buffer) |
6750 | *--cursor = *va_arg (args, const struct mips_cl_insn *); | |
6751 | ||
932d1a1b | 6752 | nops = nops_for_insn (ignore, buffer, NULL); |
71400594 RS |
6753 | va_end (args); |
6754 | return nops; | |
6755 | } | |
252b5132 | 6756 | |
71400594 RS |
6757 | /* Like nops_for_insn, but if INSN is a branch, take into account the |
6758 | worst-case delay for the branch target. */ | |
252b5132 | 6759 | |
71400594 | 6760 | static int |
932d1a1b | 6761 | nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
6762 | const struct mips_cl_insn *insn) |
6763 | { | |
6764 | int nops, tmp_nops; | |
60b63b72 | 6765 | |
932d1a1b | 6766 | nops = nops_for_insn (ignore, hist, insn); |
11625dd8 | 6767 | if (delayed_branch_p (insn)) |
71400594 | 6768 | { |
932d1a1b | 6769 | tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0, |
14fe068b | 6770 | hist, insn, get_delay_slot_nop (insn)); |
71400594 RS |
6771 | if (tmp_nops > nops) |
6772 | nops = tmp_nops; | |
6773 | } | |
11625dd8 | 6774 | else if (compact_branch_p (insn)) |
71400594 | 6775 | { |
932d1a1b | 6776 | tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn); |
71400594 RS |
6777 | if (tmp_nops > nops) |
6778 | nops = tmp_nops; | |
6779 | } | |
6780 | return nops; | |
6781 | } | |
6782 | ||
c67a084a NC |
6783 | /* Fix NOP issue: Replace nops by "or at,at,zero". */ |
6784 | ||
6785 | static void | |
6786 | fix_loongson2f_nop (struct mips_cl_insn * ip) | |
6787 | { | |
df58fc94 | 6788 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
6789 | if (strcmp (ip->insn_mo->name, "nop") == 0) |
6790 | ip->insn_opcode = LOONGSON2F_NOP_INSN; | |
6791 | } | |
6792 | ||
6793 | /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region | |
6794 | jr target pc &= 'hffff_ffff_cfff_ffff. */ | |
6795 | ||
6796 | static void | |
6797 | fix_loongson2f_jump (struct mips_cl_insn * ip) | |
6798 | { | |
df58fc94 | 6799 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
6800 | if (strcmp (ip->insn_mo->name, "j") == 0 |
6801 | || strcmp (ip->insn_mo->name, "jr") == 0 | |
6802 | || strcmp (ip->insn_mo->name, "jalr") == 0) | |
6803 | { | |
6804 | int sreg; | |
6805 | expressionS ep; | |
6806 | ||
6807 | if (! mips_opts.at) | |
6808 | return; | |
6809 | ||
df58fc94 | 6810 | sreg = EXTRACT_OPERAND (0, RS, *ip); |
c67a084a NC |
6811 | if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG) |
6812 | return; | |
6813 | ||
6814 | ep.X_op = O_constant; | |
6815 | ep.X_add_number = 0xcfff0000; | |
6816 | macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16); | |
6817 | ep.X_add_number = 0xffff; | |
6818 | macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16); | |
6819 | macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG); | |
6820 | } | |
6821 | } | |
6822 | ||
6823 | static void | |
6824 | fix_loongson2f (struct mips_cl_insn * ip) | |
6825 | { | |
6826 | if (mips_fix_loongson2f_nop) | |
6827 | fix_loongson2f_nop (ip); | |
6828 | ||
6829 | if (mips_fix_loongson2f_jump) | |
6830 | fix_loongson2f_jump (ip); | |
6831 | } | |
6832 | ||
a4e06468 RS |
6833 | /* IP is a branch that has a delay slot, and we need to fill it |
6834 | automatically. Return true if we can do that by swapping IP | |
e407c74b NC |
6835 | with the previous instruction. |
6836 | ADDRESS_EXPR is an operand of the instruction to be used with | |
6837 | RELOC_TYPE. */ | |
a4e06468 RS |
6838 | |
6839 | static bfd_boolean | |
e407c74b | 6840 | can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr, |
26545944 | 6841 | bfd_reloc_code_real_type *reloc_type) |
a4e06468 | 6842 | { |
2b0c8b40 | 6843 | unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2; |
a4e06468 | 6844 | unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write; |
9d5de888 | 6845 | unsigned int fpr_read, prev_fpr_write; |
a4e06468 RS |
6846 | |
6847 | /* -O2 and above is required for this optimization. */ | |
6848 | if (mips_optimize < 2) | |
6849 | return FALSE; | |
6850 | ||
6851 | /* If we have seen .set volatile or .set nomove, don't optimize. */ | |
6852 | if (mips_opts.nomove) | |
6853 | return FALSE; | |
6854 | ||
6855 | /* We can't swap if the previous instruction's position is fixed. */ | |
6856 | if (history[0].fixed_p) | |
6857 | return FALSE; | |
6858 | ||
6859 | /* If the previous previous insn was in a .set noreorder, we can't | |
6860 | swap. Actually, the MIPS assembler will swap in this situation. | |
6861 | However, gcc configured -with-gnu-as will generate code like | |
6862 | ||
6863 | .set noreorder | |
6864 | lw $4,XXX | |
6865 | .set reorder | |
6866 | INSN | |
6867 | bne $4,$0,foo | |
6868 | ||
6869 | in which we can not swap the bne and INSN. If gcc is not configured | |
6870 | -with-gnu-as, it does not output the .set pseudo-ops. */ | |
6871 | if (history[1].noreorder_p) | |
6872 | return FALSE; | |
6873 | ||
87333bb7 MR |
6874 | /* If the previous instruction had a fixup in mips16 mode, we can not swap. |
6875 | This means that the previous instruction was a 4-byte one anyhow. */ | |
a4e06468 RS |
6876 | if (mips_opts.mips16 && history[0].fixp[0]) |
6877 | return FALSE; | |
6878 | ||
6879 | /* If the branch is itself the target of a branch, we can not swap. | |
6880 | We cheat on this; all we check for is whether there is a label on | |
6881 | this instruction. If there are any branches to anything other than | |
6882 | a label, users must use .set noreorder. */ | |
6883 | if (seg_info (now_seg)->label_list) | |
6884 | return FALSE; | |
6885 | ||
6886 | /* If the previous instruction is in a variant frag other than this | |
2309ddf2 | 6887 | branch's one, we cannot do the swap. This does not apply to |
9301f9c3 MR |
6888 | MIPS16 code, which uses variant frags for different purposes. */ |
6889 | if (!mips_opts.mips16 | |
a4e06468 RS |
6890 | && history[0].frag |
6891 | && history[0].frag->fr_type == rs_machine_dependent) | |
6892 | return FALSE; | |
6893 | ||
bcd530a7 RS |
6894 | /* We do not swap with instructions that cannot architecturally |
6895 | be placed in a branch delay slot, such as SYNC or ERET. We | |
6896 | also refrain from swapping with a trap instruction, since it | |
6897 | complicates trap handlers to have the trap instruction be in | |
6898 | a delay slot. */ | |
a4e06468 | 6899 | prev_pinfo = history[0].insn_mo->pinfo; |
bcd530a7 | 6900 | if (prev_pinfo & INSN_NO_DELAY_SLOT) |
a4e06468 RS |
6901 | return FALSE; |
6902 | ||
6903 | /* Check for conflicts between the branch and the instructions | |
6904 | before the candidate delay slot. */ | |
6905 | if (nops_for_insn (0, history + 1, ip) > 0) | |
6906 | return FALSE; | |
6907 | ||
6908 | /* Check for conflicts between the swapped sequence and the | |
6909 | target of the branch. */ | |
6910 | if (nops_for_sequence (2, 0, history + 1, ip, history) > 0) | |
6911 | return FALSE; | |
6912 | ||
6913 | /* If the branch reads a register that the previous | |
6914 | instruction sets, we can not swap. */ | |
6915 | gpr_read = gpr_read_mask (ip); | |
6916 | prev_gpr_write = gpr_write_mask (&history[0]); | |
6917 | if (gpr_read & prev_gpr_write) | |
6918 | return FALSE; | |
6919 | ||
9d5de888 CF |
6920 | fpr_read = fpr_read_mask (ip); |
6921 | prev_fpr_write = fpr_write_mask (&history[0]); | |
6922 | if (fpr_read & prev_fpr_write) | |
6923 | return FALSE; | |
6924 | ||
a4e06468 RS |
6925 | /* If the branch writes a register that the previous |
6926 | instruction sets, we can not swap. */ | |
6927 | gpr_write = gpr_write_mask (ip); | |
6928 | if (gpr_write & prev_gpr_write) | |
6929 | return FALSE; | |
6930 | ||
6931 | /* If the branch writes a register that the previous | |
6932 | instruction reads, we can not swap. */ | |
6933 | prev_gpr_read = gpr_read_mask (&history[0]); | |
6934 | if (gpr_write & prev_gpr_read) | |
6935 | return FALSE; | |
6936 | ||
6937 | /* If one instruction sets a condition code and the | |
6938 | other one uses a condition code, we can not swap. */ | |
6939 | pinfo = ip->insn_mo->pinfo; | |
6940 | if ((pinfo & INSN_READ_COND_CODE) | |
6941 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
6942 | return FALSE; | |
6943 | if ((pinfo & INSN_WRITE_COND_CODE) | |
6944 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
6945 | return FALSE; | |
6946 | ||
6947 | /* If the previous instruction uses the PC, we can not swap. */ | |
2b0c8b40 | 6948 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
26545944 | 6949 | if (prev_pinfo2 & INSN2_READ_PC) |
2b0c8b40 | 6950 | return FALSE; |
a4e06468 | 6951 | |
df58fc94 RS |
6952 | /* If the previous instruction has an incorrect size for a fixed |
6953 | branch delay slot in microMIPS mode, we cannot swap. */ | |
2309ddf2 MR |
6954 | pinfo2 = ip->insn_mo->pinfo2; |
6955 | if (mips_opts.micromips | |
6956 | && (pinfo2 & INSN2_BRANCH_DELAY_16BIT) | |
6957 | && insn_length (history) != 2) | |
6958 | return FALSE; | |
6959 | if (mips_opts.micromips | |
6960 | && (pinfo2 & INSN2_BRANCH_DELAY_32BIT) | |
6961 | && insn_length (history) != 4) | |
6962 | return FALSE; | |
6963 | ||
e407c74b NC |
6964 | /* On R5900 short loops need to be fixed by inserting a nop in |
6965 | the branch delay slots. | |
6966 | A short loop can be terminated too early. */ | |
6967 | if (mips_opts.arch == CPU_R5900 | |
6968 | /* Check if instruction has a parameter, ignore "j $31". */ | |
6969 | && (address_expr != NULL) | |
6970 | /* Parameter must be 16 bit. */ | |
6971 | && (*reloc_type == BFD_RELOC_16_PCREL_S2) | |
6972 | /* Branch to same segment. */ | |
41065f5e | 6973 | && (S_GET_SEGMENT (address_expr->X_add_symbol) == now_seg) |
e407c74b | 6974 | /* Branch to same code fragment. */ |
41065f5e | 6975 | && (symbol_get_frag (address_expr->X_add_symbol) == frag_now) |
e407c74b | 6976 | /* Can only calculate branch offset if value is known. */ |
41065f5e | 6977 | && symbol_constant_p (address_expr->X_add_symbol) |
e407c74b NC |
6978 | /* Check if branch is really conditional. */ |
6979 | && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
6980 | || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
6981 | || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
6982 | { | |
6983 | int distance; | |
6984 | /* Check if loop is shorter than 6 instructions including | |
6985 | branch and delay slot. */ | |
41065f5e | 6986 | distance = frag_now_fix () - S_GET_VALUE (address_expr->X_add_symbol); |
e407c74b NC |
6987 | if (distance <= 20) |
6988 | { | |
6989 | int i; | |
6990 | int rv; | |
6991 | ||
6992 | rv = FALSE; | |
6993 | /* When the loop includes branches or jumps, | |
6994 | it is not a short loop. */ | |
6995 | for (i = 0; i < (distance / 4); i++) | |
6996 | { | |
6997 | if ((history[i].cleared_p) | |
41065f5e | 6998 | || delayed_branch_p (&history[i])) |
e407c74b NC |
6999 | { |
7000 | rv = TRUE; | |
7001 | break; | |
7002 | } | |
7003 | } | |
535b785f | 7004 | if (!rv) |
e407c74b NC |
7005 | { |
7006 | /* Insert nop after branch to fix short loop. */ | |
7007 | return FALSE; | |
7008 | } | |
7009 | } | |
7010 | } | |
7011 | ||
a4e06468 RS |
7012 | return TRUE; |
7013 | } | |
7014 | ||
e407c74b NC |
7015 | /* Decide how we should add IP to the instruction stream. |
7016 | ADDRESS_EXPR is an operand of the instruction to be used with | |
7017 | RELOC_TYPE. */ | |
a4e06468 RS |
7018 | |
7019 | static enum append_method | |
e407c74b | 7020 | get_append_method (struct mips_cl_insn *ip, expressionS *address_expr, |
26545944 | 7021 | bfd_reloc_code_real_type *reloc_type) |
a4e06468 | 7022 | { |
a4e06468 RS |
7023 | /* The relaxed version of a macro sequence must be inherently |
7024 | hazard-free. */ | |
7025 | if (mips_relax.sequence == 2) | |
7026 | return APPEND_ADD; | |
7027 | ||
3b821a28 | 7028 | /* We must not dabble with instructions in a ".set noreorder" block. */ |
a4e06468 RS |
7029 | if (mips_opts.noreorder) |
7030 | return APPEND_ADD; | |
7031 | ||
7032 | /* Otherwise, it's our responsibility to fill branch delay slots. */ | |
11625dd8 | 7033 | if (delayed_branch_p (ip)) |
a4e06468 | 7034 | { |
e407c74b NC |
7035 | if (!branch_likely_p (ip) |
7036 | && can_swap_branch_p (ip, address_expr, reloc_type)) | |
a4e06468 RS |
7037 | return APPEND_SWAP; |
7038 | ||
7039 | if (mips_opts.mips16 | |
7040 | && ISA_SUPPORTS_MIPS16E | |
fc76e730 | 7041 | && gpr_read_mask (ip) != 0) |
a4e06468 RS |
7042 | return APPEND_ADD_COMPACT; |
7043 | ||
7bd374a4 MR |
7044 | if (mips_opts.micromips |
7045 | && ((ip->insn_opcode & 0xffe0) == 0x4580 | |
7046 | || (!forced_insn_length | |
7047 | && ((ip->insn_opcode & 0xfc00) == 0xcc00 | |
7048 | || (ip->insn_opcode & 0xdc00) == 0x8c00)) | |
7049 | || (ip->insn_opcode & 0xdfe00000) == 0x94000000 | |
7050 | || (ip->insn_opcode & 0xdc1f0000) == 0x94000000)) | |
7051 | return APPEND_ADD_COMPACT; | |
7052 | ||
a4e06468 RS |
7053 | return APPEND_ADD_WITH_NOP; |
7054 | } | |
7055 | ||
a4e06468 RS |
7056 | return APPEND_ADD; |
7057 | } | |
7058 | ||
7bd374a4 MR |
7059 | /* IP is an instruction whose opcode we have just changed, END points |
7060 | to the end of the opcode table processed. Point IP->insn_mo to the | |
7061 | new opcode's definition. */ | |
ceb94aa5 RS |
7062 | |
7063 | static void | |
7bd374a4 | 7064 | find_altered_opcode (struct mips_cl_insn *ip, const struct mips_opcode *end) |
ceb94aa5 | 7065 | { |
7bd374a4 | 7066 | const struct mips_opcode *mo; |
ceb94aa5 | 7067 | |
ceb94aa5 | 7068 | for (mo = ip->insn_mo; mo < end; mo++) |
7bd374a4 MR |
7069 | if (mo->pinfo != INSN_MACRO |
7070 | && (ip->insn_opcode & mo->mask) == mo->match) | |
ceb94aa5 RS |
7071 | { |
7072 | ip->insn_mo = mo; | |
7073 | return; | |
7074 | } | |
7075 | abort (); | |
7076 | } | |
7077 | ||
7bd374a4 MR |
7078 | /* IP is a MIPS16 instruction whose opcode we have just changed. |
7079 | Point IP->insn_mo to the new opcode's definition. */ | |
7080 | ||
7081 | static void | |
7082 | find_altered_mips16_opcode (struct mips_cl_insn *ip) | |
7083 | { | |
7084 | find_altered_opcode (ip, &mips16_opcodes[bfd_mips16_num_opcodes]); | |
7085 | } | |
7086 | ||
7087 | /* IP is a microMIPS instruction whose opcode we have just changed. | |
7088 | Point IP->insn_mo to the new opcode's definition. */ | |
7089 | ||
7090 | static void | |
7091 | find_altered_micromips_opcode (struct mips_cl_insn *ip) | |
7092 | { | |
7093 | find_altered_opcode (ip, µmips_opcodes[bfd_micromips_num_opcodes]); | |
7094 | } | |
7095 | ||
df58fc94 RS |
7096 | /* For microMIPS macros, we need to generate a local number label |
7097 | as the target of branches. */ | |
7098 | #define MICROMIPS_LABEL_CHAR '\037' | |
7099 | static unsigned long micromips_target_label; | |
7100 | static char micromips_target_name[32]; | |
7101 | ||
7102 | static char * | |
7103 | micromips_label_name (void) | |
7104 | { | |
7105 | char *p = micromips_target_name; | |
7106 | char symbol_name_temporary[24]; | |
7107 | unsigned long l; | |
7108 | int i; | |
7109 | ||
7110 | if (*p) | |
7111 | return p; | |
7112 | ||
7113 | i = 0; | |
7114 | l = micromips_target_label; | |
7115 | #ifdef LOCAL_LABEL_PREFIX | |
7116 | *p++ = LOCAL_LABEL_PREFIX; | |
7117 | #endif | |
7118 | *p++ = 'L'; | |
7119 | *p++ = MICROMIPS_LABEL_CHAR; | |
7120 | do | |
7121 | { | |
7122 | symbol_name_temporary[i++] = l % 10 + '0'; | |
7123 | l /= 10; | |
7124 | } | |
7125 | while (l != 0); | |
7126 | while (i > 0) | |
7127 | *p++ = symbol_name_temporary[--i]; | |
7128 | *p = '\0'; | |
7129 | ||
7130 | return micromips_target_name; | |
7131 | } | |
7132 | ||
7133 | static void | |
7134 | micromips_label_expr (expressionS *label_expr) | |
7135 | { | |
7136 | label_expr->X_op = O_symbol; | |
7137 | label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ()); | |
7138 | label_expr->X_add_number = 0; | |
7139 | } | |
7140 | ||
7141 | static void | |
7142 | micromips_label_inc (void) | |
7143 | { | |
7144 | micromips_target_label++; | |
7145 | *micromips_target_name = '\0'; | |
7146 | } | |
7147 | ||
7148 | static void | |
7149 | micromips_add_label (void) | |
7150 | { | |
7151 | symbolS *s; | |
7152 | ||
7153 | s = colon (micromips_label_name ()); | |
7154 | micromips_label_inc (); | |
f3ded42a | 7155 | S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s))); |
df58fc94 RS |
7156 | } |
7157 | ||
7158 | /* If assembling microMIPS code, then return the microMIPS reloc | |
7159 | corresponding to the requested one if any. Otherwise return | |
7160 | the reloc unchanged. */ | |
7161 | ||
7162 | static bfd_reloc_code_real_type | |
7163 | micromips_map_reloc (bfd_reloc_code_real_type reloc) | |
7164 | { | |
7165 | static const bfd_reloc_code_real_type relocs[][2] = | |
7166 | { | |
7167 | /* Keep sorted incrementally by the left-hand key. */ | |
7168 | { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 }, | |
7169 | { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 }, | |
7170 | { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP }, | |
7171 | { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 }, | |
7172 | { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S }, | |
7173 | { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 }, | |
7174 | { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL }, | |
7175 | { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 }, | |
7176 | { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 }, | |
7177 | { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 }, | |
7178 | { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 }, | |
7179 | { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 }, | |
7180 | { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 }, | |
7181 | { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB }, | |
7182 | { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE }, | |
7183 | { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST }, | |
7184 | { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP }, | |
7185 | { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST }, | |
7186 | { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER }, | |
7187 | { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP }, | |
7188 | { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD }, | |
7189 | { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM }, | |
7190 | { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 }, | |
7191 | { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 }, | |
7192 | { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL }, | |
7193 | { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 }, | |
7194 | { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 } | |
7195 | }; | |
7196 | bfd_reloc_code_real_type r; | |
7197 | size_t i; | |
7198 | ||
7199 | if (!mips_opts.micromips) | |
7200 | return reloc; | |
7201 | for (i = 0; i < ARRAY_SIZE (relocs); i++) | |
7202 | { | |
7203 | r = relocs[i][0]; | |
7204 | if (r > reloc) | |
7205 | return reloc; | |
7206 | if (r == reloc) | |
7207 | return relocs[i][1]; | |
7208 | } | |
7209 | return reloc; | |
7210 | } | |
7211 | ||
b886a2ab RS |
7212 | /* Try to resolve relocation RELOC against constant OPERAND at assembly time. |
7213 | Return true on success, storing the resolved value in RESULT. */ | |
7214 | ||
7215 | static bfd_boolean | |
7216 | calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand, | |
7217 | offsetT *result) | |
7218 | { | |
7219 | switch (reloc) | |
7220 | { | |
7221 | case BFD_RELOC_MIPS_HIGHEST: | |
7222 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
7223 | *result = ((operand + 0x800080008000ull) >> 48) & 0xffff; | |
7224 | return TRUE; | |
7225 | ||
7226 | case BFD_RELOC_MIPS_HIGHER: | |
7227 | case BFD_RELOC_MICROMIPS_HIGHER: | |
7228 | *result = ((operand + 0x80008000ull) >> 32) & 0xffff; | |
7229 | return TRUE; | |
7230 | ||
7231 | case BFD_RELOC_HI16_S: | |
41947d9e | 7232 | case BFD_RELOC_HI16_S_PCREL: |
b886a2ab RS |
7233 | case BFD_RELOC_MICROMIPS_HI16_S: |
7234 | case BFD_RELOC_MIPS16_HI16_S: | |
7235 | *result = ((operand + 0x8000) >> 16) & 0xffff; | |
7236 | return TRUE; | |
7237 | ||
7238 | case BFD_RELOC_HI16: | |
7239 | case BFD_RELOC_MICROMIPS_HI16: | |
7240 | case BFD_RELOC_MIPS16_HI16: | |
7241 | *result = (operand >> 16) & 0xffff; | |
7242 | return TRUE; | |
7243 | ||
7244 | case BFD_RELOC_LO16: | |
41947d9e | 7245 | case BFD_RELOC_LO16_PCREL: |
b886a2ab RS |
7246 | case BFD_RELOC_MICROMIPS_LO16: |
7247 | case BFD_RELOC_MIPS16_LO16: | |
7248 | *result = operand & 0xffff; | |
7249 | return TRUE; | |
7250 | ||
7251 | case BFD_RELOC_UNUSED: | |
7252 | *result = operand; | |
7253 | return TRUE; | |
7254 | ||
7255 | default: | |
7256 | return FALSE; | |
7257 | } | |
7258 | } | |
7259 | ||
71400594 RS |
7260 | /* Output an instruction. IP is the instruction information. |
7261 | ADDRESS_EXPR is an operand of the instruction to be used with | |
df58fc94 RS |
7262 | RELOC_TYPE. EXPANSIONP is true if the instruction is part of |
7263 | a macro expansion. */ | |
71400594 RS |
7264 | |
7265 | static void | |
7266 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
df58fc94 | 7267 | bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp) |
71400594 | 7268 | { |
14fe068b | 7269 | unsigned long prev_pinfo2, pinfo; |
71400594 | 7270 | bfd_boolean relaxed_branch = FALSE; |
a4e06468 | 7271 | enum append_method method; |
2309ddf2 | 7272 | bfd_boolean relax32; |
2b0c8b40 | 7273 | int branch_disp; |
71400594 | 7274 | |
2309ddf2 | 7275 | if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION) |
c67a084a NC |
7276 | fix_loongson2f (ip); |
7277 | ||
738f4d98 | 7278 | file_ase_mips16 |= mips_opts.mips16; |
df58fc94 | 7279 | file_ase_micromips |= mips_opts.micromips; |
738f4d98 | 7280 | |
df58fc94 | 7281 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
71400594 | 7282 | pinfo = ip->insn_mo->pinfo; |
df58fc94 | 7283 | |
7bd374a4 MR |
7284 | /* Don't raise alarm about `nods' frags as they'll fill in the right |
7285 | kind of nop in relaxation if required. */ | |
df58fc94 RS |
7286 | if (mips_opts.micromips |
7287 | && !expansionp | |
7bd374a4 MR |
7288 | && !(history[0].frag |
7289 | && history[0].frag->fr_type == rs_machine_dependent | |
7290 | && RELAX_MICROMIPS_P (history[0].frag->fr_subtype) | |
7291 | && RELAX_MICROMIPS_NODS (history[0].frag->fr_subtype)) | |
df58fc94 RS |
7292 | && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 |
7293 | && micromips_insn_length (ip->insn_mo) != 2) | |
7294 | || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 | |
7295 | && micromips_insn_length (ip->insn_mo) != 4))) | |
1661c76c | 7296 | as_warn (_("wrong size instruction in a %u-bit branch delay slot"), |
df58fc94 | 7297 | (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32); |
71400594 | 7298 | |
15be625d CM |
7299 | if (address_expr == NULL) |
7300 | ip->complete_p = 1; | |
b886a2ab RS |
7301 | else if (reloc_type[0] <= BFD_RELOC_UNUSED |
7302 | && reloc_type[1] == BFD_RELOC_UNUSED | |
7303 | && reloc_type[2] == BFD_RELOC_UNUSED | |
15be625d CM |
7304 | && address_expr->X_op == O_constant) |
7305 | { | |
15be625d CM |
7306 | switch (*reloc_type) |
7307 | { | |
15be625d | 7308 | case BFD_RELOC_MIPS_JMP: |
df58fc94 RS |
7309 | { |
7310 | int shift; | |
7311 | ||
17c6c9d9 MR |
7312 | /* Shift is 2, unusually, for microMIPS JALX. */ |
7313 | shift = (mips_opts.micromips | |
7314 | && strcmp (ip->insn_mo->name, "jalx") != 0) ? 1 : 2; | |
df58fc94 RS |
7315 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) |
7316 | as_bad (_("jump to misaligned address (0x%lx)"), | |
7317 | (unsigned long) address_expr->X_add_number); | |
7318 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
7319 | & 0x3ffffff); | |
335574df | 7320 | ip->complete_p = 1; |
df58fc94 | 7321 | } |
15be625d CM |
7322 | break; |
7323 | ||
7324 | case BFD_RELOC_MIPS16_JMP: | |
7325 | if ((address_expr->X_add_number & 3) != 0) | |
7326 | as_bad (_("jump to misaligned address (0x%lx)"), | |
7327 | (unsigned long) address_expr->X_add_number); | |
7328 | ip->insn_opcode |= | |
7329 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
7330 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
7331 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
335574df | 7332 | ip->complete_p = 1; |
15be625d CM |
7333 | break; |
7334 | ||
7335 | case BFD_RELOC_16_PCREL_S2: | |
df58fc94 RS |
7336 | { |
7337 | int shift; | |
7338 | ||
7339 | shift = mips_opts.micromips ? 1 : 2; | |
7340 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
7341 | as_bad (_("branch to misaligned address (0x%lx)"), | |
7342 | (unsigned long) address_expr->X_add_number); | |
7343 | if (!mips_relax_branch) | |
7344 | { | |
7345 | if ((address_expr->X_add_number + (1 << (shift + 15))) | |
7346 | & ~((1 << (shift + 16)) - 1)) | |
7347 | as_bad (_("branch address range overflow (0x%lx)"), | |
7348 | (unsigned long) address_expr->X_add_number); | |
7349 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
7350 | & 0xffff); | |
7351 | } | |
df58fc94 | 7352 | } |
15be625d CM |
7353 | break; |
7354 | ||
7361da2c AB |
7355 | case BFD_RELOC_MIPS_21_PCREL_S2: |
7356 | { | |
7357 | int shift; | |
7358 | ||
7359 | shift = 2; | |
7360 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
7361 | as_bad (_("branch to misaligned address (0x%lx)"), | |
7362 | (unsigned long) address_expr->X_add_number); | |
7363 | if ((address_expr->X_add_number + (1 << (shift + 20))) | |
7364 | & ~((1 << (shift + 21)) - 1)) | |
7365 | as_bad (_("branch address range overflow (0x%lx)"), | |
7366 | (unsigned long) address_expr->X_add_number); | |
7367 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
7368 | & 0x1fffff); | |
7369 | } | |
7370 | break; | |
7371 | ||
7372 | case BFD_RELOC_MIPS_26_PCREL_S2: | |
7373 | { | |
7374 | int shift; | |
7375 | ||
7376 | shift = 2; | |
7377 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
7378 | as_bad (_("branch to misaligned address (0x%lx)"), | |
7379 | (unsigned long) address_expr->X_add_number); | |
7380 | if ((address_expr->X_add_number + (1 << (shift + 25))) | |
7381 | & ~((1 << (shift + 26)) - 1)) | |
7382 | as_bad (_("branch address range overflow (0x%lx)"), | |
7383 | (unsigned long) address_expr->X_add_number); | |
7384 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
7385 | & 0x3ffffff); | |
7386 | } | |
7387 | break; | |
7388 | ||
15be625d | 7389 | default: |
b886a2ab RS |
7390 | { |
7391 | offsetT value; | |
7392 | ||
7393 | if (calculate_reloc (*reloc_type, address_expr->X_add_number, | |
7394 | &value)) | |
7395 | { | |
7396 | ip->insn_opcode |= value & 0xffff; | |
7397 | ip->complete_p = 1; | |
7398 | } | |
7399 | } | |
7400 | break; | |
7401 | } | |
15be625d CM |
7402 | } |
7403 | ||
71400594 RS |
7404 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
7405 | { | |
7406 | /* There are a lot of optimizations we could do that we don't. | |
7407 | In particular, we do not, in general, reorder instructions. | |
7408 | If you use gcc with optimization, it will reorder | |
7409 | instructions and generally do much more optimization then we | |
7410 | do here; repeating all that work in the assembler would only | |
7411 | benefit hand written assembly code, and does not seem worth | |
7412 | it. */ | |
7413 | int nops = (mips_optimize == 0 | |
932d1a1b RS |
7414 | ? nops_for_insn (0, history, NULL) |
7415 | : nops_for_insn_or_target (0, history, ip)); | |
71400594 | 7416 | if (nops > 0) |
252b5132 RH |
7417 | { |
7418 | fragS *old_frag; | |
7419 | unsigned long old_frag_offset; | |
7420 | int i; | |
252b5132 RH |
7421 | |
7422 | old_frag = frag_now; | |
7423 | old_frag_offset = frag_now_fix (); | |
7424 | ||
7425 | for (i = 0; i < nops; i++) | |
14fe068b RS |
7426 | add_fixed_insn (NOP_INSN); |
7427 | insert_into_history (0, nops, NOP_INSN); | |
252b5132 RH |
7428 | |
7429 | if (listing) | |
7430 | { | |
7431 | listing_prev_line (); | |
7432 | /* We may be at the start of a variant frag. In case we | |
7433 | are, make sure there is enough space for the frag | |
7434 | after the frags created by listing_prev_line. The | |
7435 | argument to frag_grow here must be at least as large | |
7436 | as the argument to all other calls to frag_grow in | |
7437 | this file. We don't have to worry about being in the | |
7438 | middle of a variant frag, because the variants insert | |
7439 | all needed nop instructions themselves. */ | |
7440 | frag_grow (40); | |
7441 | } | |
7442 | ||
462427c4 | 7443 | mips_move_text_labels (); |
252b5132 RH |
7444 | |
7445 | #ifndef NO_ECOFF_DEBUGGING | |
7446 | if (ECOFF_DEBUGGING) | |
7447 | ecoff_fix_loc (old_frag, old_frag_offset); | |
7448 | #endif | |
7449 | } | |
71400594 RS |
7450 | } |
7451 | else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) | |
7452 | { | |
932d1a1b RS |
7453 | int nops; |
7454 | ||
7455 | /* Work out how many nops in prev_nop_frag are needed by IP, | |
7456 | ignoring hazards generated by the first prev_nop_frag_since | |
7457 | instructions. */ | |
7458 | nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip); | |
9c2799c2 | 7459 | gas_assert (nops <= prev_nop_frag_holds); |
252b5132 | 7460 | |
71400594 RS |
7461 | /* Enforce NOPS as a minimum. */ |
7462 | if (nops > prev_nop_frag_required) | |
7463 | prev_nop_frag_required = nops; | |
252b5132 | 7464 | |
71400594 RS |
7465 | if (prev_nop_frag_holds == prev_nop_frag_required) |
7466 | { | |
7467 | /* Settle for the current number of nops. Update the history | |
7468 | accordingly (for the benefit of any future .set reorder code). */ | |
7469 | prev_nop_frag = NULL; | |
7470 | insert_into_history (prev_nop_frag_since, | |
7471 | prev_nop_frag_holds, NOP_INSN); | |
7472 | } | |
7473 | else | |
7474 | { | |
7475 | /* Allow this instruction to replace one of the nops that was | |
7476 | tentatively added to prev_nop_frag. */ | |
df58fc94 | 7477 | prev_nop_frag->fr_fix -= NOP_INSN_SIZE; |
71400594 RS |
7478 | prev_nop_frag_holds--; |
7479 | prev_nop_frag_since++; | |
252b5132 RH |
7480 | } |
7481 | } | |
7482 | ||
e407c74b | 7483 | method = get_append_method (ip, address_expr, reloc_type); |
2b0c8b40 | 7484 | branch_disp = method == APPEND_SWAP ? insn_length (history) : 0; |
a4e06468 | 7485 | |
e410add4 RS |
7486 | dwarf2_emit_insn (0); |
7487 | /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses, | |
7488 | so "move" the instruction address accordingly. | |
7489 | ||
7490 | Also, it doesn't seem appropriate for the assembler to reorder .loc | |
7491 | entries. If this instruction is a branch that we are going to swap | |
7492 | with the previous instruction, the two instructions should be | |
7493 | treated as a unit, and the debug information for both instructions | |
7494 | should refer to the start of the branch sequence. Using the | |
7495 | current position is certainly wrong when swapping a 32-bit branch | |
7496 | and a 16-bit delay slot, since the current position would then be | |
7497 | in the middle of a branch. */ | |
7498 | dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp); | |
58e2ea4d | 7499 | |
df58fc94 RS |
7500 | relax32 = (mips_relax_branch |
7501 | /* Don't try branch relaxation within .set nomacro, or within | |
7502 | .set noat if we use $at for PIC computations. If it turns | |
7503 | out that the branch was out-of-range, we'll get an error. */ | |
7504 | && !mips_opts.warn_about_macros | |
7505 | && (mips_opts.at || mips_pic == NO_PIC) | |
3bf0dbfb MR |
7506 | /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F |
7507 | as they have no complementing branches. */ | |
7508 | && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP))); | |
df58fc94 RS |
7509 | |
7510 | if (!HAVE_CODE_COMPRESSION | |
7511 | && address_expr | |
7512 | && relax32 | |
0b25d3e6 | 7513 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
11625dd8 | 7514 | && delayed_branch_p (ip)) |
4a6a3df4 | 7515 | { |
895921c9 | 7516 | relaxed_branch = TRUE; |
1e915849 RS |
7517 | add_relaxed_insn (ip, (relaxed_branch_length |
7518 | (NULL, NULL, | |
11625dd8 RS |
7519 | uncond_branch_p (ip) ? -1 |
7520 | : branch_likely_p (ip) ? 1 | |
1e915849 RS |
7521 | : 0)), 4, |
7522 | RELAX_BRANCH_ENCODE | |
ce8ad872 | 7523 | (AT, mips_pic != NO_PIC, |
11625dd8 RS |
7524 | uncond_branch_p (ip), |
7525 | branch_likely_p (ip), | |
1e915849 RS |
7526 | pinfo & INSN_WRITE_GPR_31, |
7527 | 0), | |
7528 | address_expr->X_add_symbol, | |
7529 | address_expr->X_add_number); | |
4a6a3df4 AO |
7530 | *reloc_type = BFD_RELOC_UNUSED; |
7531 | } | |
df58fc94 RS |
7532 | else if (mips_opts.micromips |
7533 | && address_expr | |
7534 | && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2) | |
7535 | || *reloc_type > BFD_RELOC_UNUSED) | |
40209cad MR |
7536 | && (delayed_branch_p (ip) || compact_branch_p (ip)) |
7537 | /* Don't try branch relaxation when users specify | |
7538 | 16-bit/32-bit instructions. */ | |
7539 | && !forced_insn_length) | |
df58fc94 | 7540 | { |
7bd374a4 MR |
7541 | bfd_boolean relax16 = (method != APPEND_ADD_COMPACT |
7542 | && *reloc_type > BFD_RELOC_UNUSED); | |
df58fc94 | 7543 | int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0; |
11625dd8 | 7544 | int uncond = uncond_branch_p (ip) ? -1 : 0; |
7bd374a4 MR |
7545 | int compact = compact_branch_p (ip) || method == APPEND_ADD_COMPACT; |
7546 | int nods = method == APPEND_ADD_WITH_NOP; | |
df58fc94 | 7547 | int al = pinfo & INSN_WRITE_GPR_31; |
7bd374a4 | 7548 | int length32 = nods ? 8 : 4; |
df58fc94 RS |
7549 | |
7550 | gas_assert (address_expr != NULL); | |
7551 | gas_assert (!mips_relax.sequence); | |
7552 | ||
2b0c8b40 | 7553 | relaxed_branch = TRUE; |
7bd374a4 MR |
7554 | if (nods) |
7555 | method = APPEND_ADD; | |
7556 | if (relax32) | |
7557 | length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond); | |
7558 | add_relaxed_insn (ip, length32, relax16 ? 2 : 4, | |
8484fb75 | 7559 | RELAX_MICROMIPS_ENCODE (type, AT, mips_opts.insn32, |
ce8ad872 | 7560 | mips_pic != NO_PIC, |
7bd374a4 | 7561 | uncond, compact, al, nods, |
40209cad | 7562 | relax32, 0, 0), |
df58fc94 RS |
7563 | address_expr->X_add_symbol, |
7564 | address_expr->X_add_number); | |
7565 | *reloc_type = BFD_RELOC_UNUSED; | |
7566 | } | |
7567 | else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED) | |
252b5132 | 7568 | { |
7fd53920 MR |
7569 | bfd_boolean require_unextended; |
7570 | bfd_boolean require_extended; | |
88a7ef16 MR |
7571 | symbolS *symbol; |
7572 | offsetT offset; | |
7573 | ||
7fd53920 MR |
7574 | if (forced_insn_length != 0) |
7575 | { | |
7576 | require_unextended = forced_insn_length == 2; | |
7577 | require_extended = forced_insn_length == 4; | |
7578 | } | |
7579 | else | |
7580 | { | |
7581 | require_unextended = (mips_opts.noautoextend | |
7582 | && !mips_opcode_32bit_p (ip->insn_mo)); | |
7583 | require_extended = 0; | |
7584 | } | |
7585 | ||
252b5132 | 7586 | /* We need to set up a variant frag. */ |
df58fc94 | 7587 | gas_assert (address_expr != NULL); |
88a7ef16 MR |
7588 | /* Pass any `O_symbol' expression unchanged as an `expr_section' |
7589 | symbol created by `make_expr_symbol' may not get a necessary | |
7590 | external relocation produced. */ | |
7591 | if (address_expr->X_op == O_symbol) | |
7592 | { | |
7593 | symbol = address_expr->X_add_symbol; | |
7594 | offset = address_expr->X_add_number; | |
7595 | } | |
7596 | else | |
7597 | { | |
7598 | symbol = make_expr_symbol (address_expr); | |
82d808ed | 7599 | symbol_append (symbol, symbol_lastP, &symbol_rootP, &symbol_lastP); |
88a7ef16 MR |
7600 | offset = 0; |
7601 | } | |
8507b6e7 | 7602 | add_relaxed_insn (ip, 12, 0, |
1e915849 RS |
7603 | RELAX_MIPS16_ENCODE |
7604 | (*reloc_type - BFD_RELOC_UNUSED, | |
25499ac7 | 7605 | mips_opts.ase & ASE_MIPS16E2, |
8507b6e7 MR |
7606 | mips_pic != NO_PIC, |
7607 | HAVE_32BIT_SYMBOLS, | |
7608 | mips_opts.warn_about_macros, | |
7fd53920 | 7609 | require_unextended, require_extended, |
11625dd8 | 7610 | delayed_branch_p (&history[0]), |
1e915849 | 7611 | history[0].mips16_absolute_jump_p), |
88a7ef16 | 7612 | symbol, offset); |
252b5132 | 7613 | } |
5c04167a | 7614 | else if (mips_opts.mips16 && insn_length (ip) == 2) |
9497f5ac | 7615 | { |
11625dd8 | 7616 | if (!delayed_branch_p (ip)) |
b8ee1a6e DU |
7617 | /* Make sure there is enough room to swap this instruction with |
7618 | a following jump instruction. */ | |
7619 | frag_grow (6); | |
1e915849 | 7620 | add_fixed_insn (ip); |
252b5132 RH |
7621 | } |
7622 | else | |
7623 | { | |
7624 | if (mips_opts.mips16 | |
7625 | && mips_opts.noreorder | |
11625dd8 | 7626 | && delayed_branch_p (&history[0])) |
252b5132 RH |
7627 | as_warn (_("extended instruction in delay slot")); |
7628 | ||
4d7206a2 RS |
7629 | if (mips_relax.sequence) |
7630 | { | |
7631 | /* If we've reached the end of this frag, turn it into a variant | |
7632 | frag and record the information for the instructions we've | |
7633 | written so far. */ | |
7634 | if (frag_room () < 4) | |
7635 | relax_close_frag (); | |
df58fc94 | 7636 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip); |
4d7206a2 RS |
7637 | } |
7638 | ||
584892a6 | 7639 | if (mips_relax.sequence != 2) |
df58fc94 RS |
7640 | { |
7641 | if (mips_macro_warning.first_insn_sizes[0] == 0) | |
7642 | mips_macro_warning.first_insn_sizes[0] = insn_length (ip); | |
7643 | mips_macro_warning.sizes[0] += insn_length (ip); | |
7644 | mips_macro_warning.insns[0]++; | |
7645 | } | |
584892a6 | 7646 | if (mips_relax.sequence != 1) |
df58fc94 RS |
7647 | { |
7648 | if (mips_macro_warning.first_insn_sizes[1] == 0) | |
7649 | mips_macro_warning.first_insn_sizes[1] = insn_length (ip); | |
7650 | mips_macro_warning.sizes[1] += insn_length (ip); | |
7651 | mips_macro_warning.insns[1]++; | |
7652 | } | |
584892a6 | 7653 | |
1e915849 RS |
7654 | if (mips_opts.mips16) |
7655 | { | |
7656 | ip->fixed_p = 1; | |
7657 | ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); | |
7658 | } | |
7659 | add_fixed_insn (ip); | |
252b5132 RH |
7660 | } |
7661 | ||
9fe77896 | 7662 | if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 7663 | { |
df58fc94 | 7664 | bfd_reloc_code_real_type final_type[3]; |
2309ddf2 | 7665 | reloc_howto_type *howto0; |
9fe77896 RS |
7666 | reloc_howto_type *howto; |
7667 | int i; | |
34ce925e | 7668 | |
df58fc94 RS |
7669 | /* Perform any necessary conversion to microMIPS relocations |
7670 | and find out how many relocations there actually are. */ | |
7671 | for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++) | |
7672 | final_type[i] = micromips_map_reloc (reloc_type[i]); | |
7673 | ||
9fe77896 RS |
7674 | /* In a compound relocation, it is the final (outermost) |
7675 | operator that determines the relocated field. */ | |
2309ddf2 | 7676 | howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]); |
e8044f35 RS |
7677 | if (!howto) |
7678 | abort (); | |
2309ddf2 MR |
7679 | |
7680 | if (i > 1) | |
7681 | howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]); | |
9fe77896 RS |
7682 | ip->fixp[0] = fix_new_exp (ip->frag, ip->where, |
7683 | bfd_get_reloc_size (howto), | |
7684 | address_expr, | |
2309ddf2 MR |
7685 | howto0 && howto0->pc_relative, |
7686 | final_type[0]); | |
ce8ad872 MR |
7687 | /* Record non-PIC mode in `fx_tcbit2' for `md_apply_fix'. */ |
7688 | ip->fixp[0]->fx_tcbit2 = mips_pic == NO_PIC; | |
9fe77896 RS |
7689 | |
7690 | /* Tag symbols that have a R_MIPS16_26 relocation against them. */ | |
2309ddf2 | 7691 | if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy) |
9fe77896 RS |
7692 | *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1; |
7693 | ||
7694 | /* These relocations can have an addend that won't fit in | |
7695 | 4 octets for 64bit assembly. */ | |
bad1aba3 | 7696 | if (GPR_SIZE == 64 |
9fe77896 RS |
7697 | && ! howto->partial_inplace |
7698 | && (reloc_type[0] == BFD_RELOC_16 | |
7699 | || reloc_type[0] == BFD_RELOC_32 | |
7700 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
7701 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
7702 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
7703 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
7704 | || reloc_type[0] == BFD_RELOC_64 | |
7705 | || reloc_type[0] == BFD_RELOC_CTOR | |
7706 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
7707 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
7708 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
7709 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
7710 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
7711 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT | |
7712 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
7713 | || hi16_reloc_p (reloc_type[0]) | |
7714 | || lo16_reloc_p (reloc_type[0]))) | |
7715 | ip->fixp[0]->fx_no_overflow = 1; | |
7716 | ||
ddaf2c41 MR |
7717 | /* These relocations can have an addend that won't fit in 2 octets. */ |
7718 | if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
7719 | || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1) | |
7720 | ip->fixp[0]->fx_no_overflow = 1; | |
7721 | ||
9fe77896 RS |
7722 | if (mips_relax.sequence) |
7723 | { | |
7724 | if (mips_relax.first_fixup == 0) | |
7725 | mips_relax.first_fixup = ip->fixp[0]; | |
7726 | } | |
7727 | else if (reloc_needs_lo_p (*reloc_type)) | |
7728 | { | |
7729 | struct mips_hi_fixup *hi_fixup; | |
7730 | ||
7731 | /* Reuse the last entry if it already has a matching %lo. */ | |
7732 | hi_fixup = mips_hi_fixup_list; | |
7733 | if (hi_fixup == 0 | |
7734 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
4d7206a2 | 7735 | { |
325801bd | 7736 | hi_fixup = XNEW (struct mips_hi_fixup); |
9fe77896 RS |
7737 | hi_fixup->next = mips_hi_fixup_list; |
7738 | mips_hi_fixup_list = hi_fixup; | |
4d7206a2 | 7739 | } |
9fe77896 RS |
7740 | hi_fixup->fixp = ip->fixp[0]; |
7741 | hi_fixup->seg = now_seg; | |
7742 | } | |
252b5132 | 7743 | |
9fe77896 RS |
7744 | /* Add fixups for the second and third relocations, if given. |
7745 | Note that the ABI allows the second relocation to be | |
7746 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
7747 | moment we only use RSS_UNDEF, but we could add support | |
7748 | for the others if it ever becomes necessary. */ | |
7749 | for (i = 1; i < 3; i++) | |
7750 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
7751 | { | |
7752 | ip->fixp[i] = fix_new (ip->frag, ip->where, | |
7753 | ip->fixp[0]->fx_size, NULL, 0, | |
df58fc94 | 7754 | FALSE, final_type[i]); |
f6688943 | 7755 | |
9fe77896 RS |
7756 | /* Use fx_tcbit to mark compound relocs. */ |
7757 | ip->fixp[0]->fx_tcbit = 1; | |
7758 | ip->fixp[i]->fx_tcbit = 1; | |
7759 | } | |
252b5132 | 7760 | } |
252b5132 RH |
7761 | |
7762 | /* Update the register mask information. */ | |
4c260379 RS |
7763 | mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip); |
7764 | mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip); | |
252b5132 | 7765 | |
a4e06468 | 7766 | switch (method) |
252b5132 | 7767 | { |
a4e06468 RS |
7768 | case APPEND_ADD: |
7769 | insert_into_history (0, 1, ip); | |
7770 | break; | |
7771 | ||
7772 | case APPEND_ADD_WITH_NOP: | |
14fe068b RS |
7773 | { |
7774 | struct mips_cl_insn *nop; | |
7775 | ||
7776 | insert_into_history (0, 1, ip); | |
7777 | nop = get_delay_slot_nop (ip); | |
7778 | add_fixed_insn (nop); | |
7779 | insert_into_history (0, 1, nop); | |
7780 | if (mips_relax.sequence) | |
7781 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop); | |
7782 | } | |
a4e06468 RS |
7783 | break; |
7784 | ||
7785 | case APPEND_ADD_COMPACT: | |
7786 | /* Convert MIPS16 jr/jalr into a "compact" jump. */ | |
7bd374a4 MR |
7787 | if (mips_opts.mips16) |
7788 | { | |
7789 | ip->insn_opcode |= 0x0080; | |
7790 | find_altered_mips16_opcode (ip); | |
7791 | } | |
7792 | /* Convert microMIPS instructions. */ | |
7793 | else if (mips_opts.micromips) | |
7794 | { | |
7795 | /* jr16->jrc */ | |
7796 | if ((ip->insn_opcode & 0xffe0) == 0x4580) | |
7797 | ip->insn_opcode |= 0x0020; | |
7798 | /* b16->bc */ | |
7799 | else if ((ip->insn_opcode & 0xfc00) == 0xcc00) | |
7800 | ip->insn_opcode = 0x40e00000; | |
7801 | /* beqz16->beqzc, bnez16->bnezc */ | |
7802 | else if ((ip->insn_opcode & 0xdc00) == 0x8c00) | |
7803 | { | |
7804 | unsigned long regno; | |
7805 | ||
7806 | regno = ip->insn_opcode >> MICROMIPSOP_SH_MD; | |
7807 | regno &= MICROMIPSOP_MASK_MD; | |
7808 | regno = micromips_to_32_reg_d_map[regno]; | |
7809 | ip->insn_opcode = (((ip->insn_opcode << 9) & 0x00400000) | |
7810 | | (regno << MICROMIPSOP_SH_RS) | |
7811 | | 0x40a00000) ^ 0x00400000; | |
7812 | } | |
7813 | /* beqz->beqzc, bnez->bnezc */ | |
7814 | else if ((ip->insn_opcode & 0xdfe00000) == 0x94000000) | |
7815 | ip->insn_opcode = ((ip->insn_opcode & 0x001f0000) | |
7816 | | ((ip->insn_opcode >> 7) & 0x00400000) | |
7817 | | 0x40a00000) ^ 0x00400000; | |
7818 | /* beq $0->beqzc, bne $0->bnezc */ | |
7819 | else if ((ip->insn_opcode & 0xdc1f0000) == 0x94000000) | |
7820 | ip->insn_opcode = (((ip->insn_opcode >> | |
7821 | (MICROMIPSOP_SH_RT - MICROMIPSOP_SH_RS)) | |
7822 | & (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS)) | |
7823 | | ((ip->insn_opcode >> 7) & 0x00400000) | |
7824 | | 0x40a00000) ^ 0x00400000; | |
7825 | else | |
7826 | abort (); | |
7827 | find_altered_micromips_opcode (ip); | |
7828 | } | |
7829 | else | |
7830 | abort (); | |
a4e06468 RS |
7831 | install_insn (ip); |
7832 | insert_into_history (0, 1, ip); | |
7833 | break; | |
7834 | ||
7835 | case APPEND_SWAP: | |
7836 | { | |
7837 | struct mips_cl_insn delay = history[0]; | |
99e7978b MF |
7838 | |
7839 | if (relaxed_branch || delay.frag != ip->frag) | |
a4e06468 RS |
7840 | { |
7841 | /* Add the delay slot instruction to the end of the | |
7842 | current frag and shrink the fixed part of the | |
7843 | original frag. If the branch occupies the tail of | |
7844 | the latter, move it backwards to cover the gap. */ | |
2b0c8b40 | 7845 | delay.frag->fr_fix -= branch_disp; |
a4e06468 | 7846 | if (delay.frag == ip->frag) |
2b0c8b40 | 7847 | move_insn (ip, ip->frag, ip->where - branch_disp); |
a4e06468 RS |
7848 | add_fixed_insn (&delay); |
7849 | } | |
7850 | else | |
7851 | { | |
5e35670b MR |
7852 | /* If this is not a relaxed branch and we are in the |
7853 | same frag, then just swap the instructions. */ | |
7854 | move_insn (ip, delay.frag, delay.where); | |
7855 | move_insn (&delay, ip->frag, ip->where + insn_length (ip)); | |
a4e06468 RS |
7856 | } |
7857 | history[0] = *ip; | |
7858 | delay.fixed_p = 1; | |
7859 | insert_into_history (0, 1, &delay); | |
7860 | } | |
7861 | break; | |
252b5132 RH |
7862 | } |
7863 | ||
13408f1e | 7864 | /* If we have just completed an unconditional branch, clear the history. */ |
11625dd8 RS |
7865 | if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1])) |
7866 | || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0]))) | |
e407c74b NC |
7867 | { |
7868 | unsigned int i; | |
7869 | ||
79850f26 | 7870 | mips_no_prev_insn (); |
13408f1e | 7871 | |
e407c74b | 7872 | for (i = 0; i < ARRAY_SIZE (history); i++) |
79850f26 | 7873 | history[i].cleared_p = 1; |
e407c74b NC |
7874 | } |
7875 | ||
df58fc94 RS |
7876 | /* We need to emit a label at the end of branch-likely macros. */ |
7877 | if (emit_branch_likely_macro) | |
7878 | { | |
7879 | emit_branch_likely_macro = FALSE; | |
7880 | micromips_add_label (); | |
7881 | } | |
7882 | ||
252b5132 RH |
7883 | /* We just output an insn, so the next one doesn't have a label. */ |
7884 | mips_clear_insn_labels (); | |
252b5132 RH |
7885 | } |
7886 | ||
e407c74b NC |
7887 | /* Forget that there was any previous instruction or label. |
7888 | When BRANCH is true, the branch history is also flushed. */ | |
252b5132 RH |
7889 | |
7890 | static void | |
7d10b47d | 7891 | mips_no_prev_insn (void) |
252b5132 | 7892 | { |
7d10b47d RS |
7893 | prev_nop_frag = NULL; |
7894 | insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); | |
252b5132 RH |
7895 | mips_clear_insn_labels (); |
7896 | } | |
7897 | ||
7d10b47d RS |
7898 | /* This function must be called before we emit something other than |
7899 | instructions. It is like mips_no_prev_insn except that it inserts | |
7900 | any NOPS that might be needed by previous instructions. */ | |
252b5132 | 7901 | |
7d10b47d RS |
7902 | void |
7903 | mips_emit_delays (void) | |
252b5132 RH |
7904 | { |
7905 | if (! mips_opts.noreorder) | |
7906 | { | |
932d1a1b | 7907 | int nops = nops_for_insn (0, history, NULL); |
252b5132 RH |
7908 | if (nops > 0) |
7909 | { | |
7d10b47d RS |
7910 | while (nops-- > 0) |
7911 | add_fixed_insn (NOP_INSN); | |
462427c4 | 7912 | mips_move_text_labels (); |
7d10b47d RS |
7913 | } |
7914 | } | |
7915 | mips_no_prev_insn (); | |
7916 | } | |
7917 | ||
7918 | /* Start a (possibly nested) noreorder block. */ | |
7919 | ||
7920 | static void | |
7921 | start_noreorder (void) | |
7922 | { | |
7923 | if (mips_opts.noreorder == 0) | |
7924 | { | |
7925 | unsigned int i; | |
7926 | int nops; | |
7927 | ||
7928 | /* None of the instructions before the .set noreorder can be moved. */ | |
7929 | for (i = 0; i < ARRAY_SIZE (history); i++) | |
7930 | history[i].fixed_p = 1; | |
7931 | ||
7932 | /* Insert any nops that might be needed between the .set noreorder | |
7933 | block and the previous instructions. We will later remove any | |
7934 | nops that turn out not to be needed. */ | |
932d1a1b | 7935 | nops = nops_for_insn (0, history, NULL); |
7d10b47d RS |
7936 | if (nops > 0) |
7937 | { | |
7938 | if (mips_optimize != 0) | |
252b5132 RH |
7939 | { |
7940 | /* Record the frag which holds the nop instructions, so | |
7941 | that we can remove them if we don't need them. */ | |
df58fc94 | 7942 | frag_grow (nops * NOP_INSN_SIZE); |
252b5132 RH |
7943 | prev_nop_frag = frag_now; |
7944 | prev_nop_frag_holds = nops; | |
7945 | prev_nop_frag_required = 0; | |
7946 | prev_nop_frag_since = 0; | |
7947 | } | |
7948 | ||
7949 | for (; nops > 0; --nops) | |
1e915849 | 7950 | add_fixed_insn (NOP_INSN); |
252b5132 | 7951 | |
7d10b47d RS |
7952 | /* Move on to a new frag, so that it is safe to simply |
7953 | decrease the size of prev_nop_frag. */ | |
7954 | frag_wane (frag_now); | |
7955 | frag_new (0); | |
462427c4 | 7956 | mips_move_text_labels (); |
252b5132 | 7957 | } |
df58fc94 | 7958 | mips_mark_labels (); |
7d10b47d | 7959 | mips_clear_insn_labels (); |
252b5132 | 7960 | } |
7d10b47d RS |
7961 | mips_opts.noreorder++; |
7962 | mips_any_noreorder = 1; | |
7963 | } | |
252b5132 | 7964 | |
7d10b47d | 7965 | /* End a nested noreorder block. */ |
252b5132 | 7966 | |
7d10b47d RS |
7967 | static void |
7968 | end_noreorder (void) | |
7969 | { | |
7970 | mips_opts.noreorder--; | |
7971 | if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) | |
7972 | { | |
7973 | /* Commit to inserting prev_nop_frag_required nops and go back to | |
7974 | handling nop insertion the .set reorder way. */ | |
7975 | prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) | |
df58fc94 | 7976 | * NOP_INSN_SIZE); |
7d10b47d RS |
7977 | insert_into_history (prev_nop_frag_since, |
7978 | prev_nop_frag_required, NOP_INSN); | |
7979 | prev_nop_frag = NULL; | |
7980 | } | |
252b5132 RH |
7981 | } |
7982 | ||
97d87491 RS |
7983 | /* Sign-extend 32-bit mode constants that have bit 31 set and all |
7984 | higher bits unset. */ | |
7985 | ||
7986 | static void | |
7987 | normalize_constant_expr (expressionS *ex) | |
7988 | { | |
7989 | if (ex->X_op == O_constant | |
7990 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
7991 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
7992 | - 0x80000000); | |
7993 | } | |
7994 | ||
7995 | /* Sign-extend 32-bit mode address offsets that have bit 31 set and | |
7996 | all higher bits unset. */ | |
7997 | ||
7998 | static void | |
7999 | normalize_address_expr (expressionS *ex) | |
8000 | { | |
8001 | if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) | |
8002 | || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) | |
8003 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
8004 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
8005 | - 0x80000000); | |
8006 | } | |
8007 | ||
8008 | /* Try to match TOKENS against OPCODE, storing the result in INSN. | |
8009 | Return true if the match was successful. | |
8010 | ||
8011 | OPCODE_EXTRA is a value that should be ORed into the opcode | |
8012 | (used for VU0 channel suffixes, etc.). MORE_ALTS is true if | |
8013 | there are more alternatives after OPCODE and SOFT_MATCH is | |
8014 | as for mips_arg_info. */ | |
8015 | ||
8016 | static bfd_boolean | |
8017 | match_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode, | |
8018 | struct mips_operand_token *tokens, unsigned int opcode_extra, | |
60f20e8b | 8019 | bfd_boolean lax_match, bfd_boolean complete_p) |
97d87491 RS |
8020 | { |
8021 | const char *args; | |
8022 | struct mips_arg_info arg; | |
8023 | const struct mips_operand *operand; | |
8024 | char c; | |
8025 | ||
8026 | imm_expr.X_op = O_absent; | |
97d87491 RS |
8027 | offset_expr.X_op = O_absent; |
8028 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
8029 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
8030 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
8031 | ||
8032 | create_insn (insn, opcode); | |
60f20e8b RS |
8033 | /* When no opcode suffix is specified, assume ".xyzw". */ |
8034 | if ((opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0 && opcode_extra == 0) | |
8035 | insn->insn_opcode |= 0xf << mips_vu0_channel_mask.lsb; | |
8036 | else | |
8037 | insn->insn_opcode |= opcode_extra; | |
97d87491 RS |
8038 | memset (&arg, 0, sizeof (arg)); |
8039 | arg.insn = insn; | |
8040 | arg.token = tokens; | |
8041 | arg.argnum = 1; | |
8042 | arg.last_regno = ILLEGAL_REG; | |
8043 | arg.dest_regno = ILLEGAL_REG; | |
60f20e8b | 8044 | arg.lax_match = lax_match; |
97d87491 RS |
8045 | for (args = opcode->args;; ++args) |
8046 | { | |
8047 | if (arg.token->type == OT_END) | |
8048 | { | |
8049 | /* Handle unary instructions in which only one operand is given. | |
8050 | The source is then the same as the destination. */ | |
8051 | if (arg.opnum == 1 && *args == ',') | |
8052 | { | |
8053 | operand = (mips_opts.micromips | |
8054 | ? decode_micromips_operand (args + 1) | |
8055 | : decode_mips_operand (args + 1)); | |
8056 | if (operand && mips_optional_operand_p (operand)) | |
8057 | { | |
8058 | arg.token = tokens; | |
8059 | arg.argnum = 1; | |
8060 | continue; | |
8061 | } | |
8062 | } | |
8063 | ||
8064 | /* Treat elided base registers as $0. */ | |
8065 | if (strcmp (args, "(b)") == 0) | |
8066 | args += 3; | |
8067 | ||
8068 | if (args[0] == '+') | |
8069 | switch (args[1]) | |
8070 | { | |
8071 | case 'K': | |
8072 | case 'N': | |
8073 | /* The register suffix is optional. */ | |
8074 | args += 2; | |
8075 | break; | |
8076 | } | |
8077 | ||
8078 | /* Fail the match if there were too few operands. */ | |
8079 | if (*args) | |
8080 | return FALSE; | |
8081 | ||
8082 | /* Successful match. */ | |
60f20e8b RS |
8083 | if (!complete_p) |
8084 | return TRUE; | |
e3de51ce | 8085 | clear_insn_error (); |
97d87491 RS |
8086 | if (arg.dest_regno == arg.last_regno |
8087 | && strncmp (insn->insn_mo->name, "jalr", 4) == 0) | |
8088 | { | |
8089 | if (arg.opnum == 2) | |
e3de51ce | 8090 | set_insn_error |
1661c76c | 8091 | (0, _("source and destination must be different")); |
97d87491 | 8092 | else if (arg.last_regno == 31) |
e3de51ce | 8093 | set_insn_error |
1661c76c | 8094 | (0, _("a destination register must be supplied")); |
97d87491 | 8095 | } |
173d3447 CF |
8096 | else if (arg.last_regno == 31 |
8097 | && (strncmp (insn->insn_mo->name, "bltzal", 6) == 0 | |
8098 | || strncmp (insn->insn_mo->name, "bgezal", 6) == 0)) | |
8099 | set_insn_error (0, _("the source register must not be $31")); | |
97d87491 RS |
8100 | check_completed_insn (&arg); |
8101 | return TRUE; | |
8102 | } | |
8103 | ||
8104 | /* Fail the match if the line has too many operands. */ | |
8105 | if (*args == 0) | |
8106 | return FALSE; | |
8107 | ||
8108 | /* Handle characters that need to match exactly. */ | |
8109 | if (*args == '(' || *args == ')' || *args == ',') | |
8110 | { | |
8111 | if (match_char (&arg, *args)) | |
8112 | continue; | |
8113 | return FALSE; | |
8114 | } | |
8115 | if (*args == '#') | |
8116 | { | |
8117 | ++args; | |
8118 | if (arg.token->type == OT_DOUBLE_CHAR | |
8119 | && arg.token->u.ch == *args) | |
8120 | { | |
8121 | ++arg.token; | |
8122 | continue; | |
8123 | } | |
8124 | return FALSE; | |
8125 | } | |
8126 | ||
8127 | /* Handle special macro operands. Work out the properties of | |
8128 | other operands. */ | |
8129 | arg.opnum += 1; | |
97d87491 RS |
8130 | switch (*args) |
8131 | { | |
7361da2c AB |
8132 | case '-': |
8133 | switch (args[1]) | |
8134 | { | |
8135 | case 'A': | |
8136 | *offset_reloc = BFD_RELOC_MIPS_19_PCREL_S2; | |
8137 | break; | |
8138 | ||
8139 | case 'B': | |
8140 | *offset_reloc = BFD_RELOC_MIPS_18_PCREL_S3; | |
8141 | break; | |
8142 | } | |
8143 | break; | |
8144 | ||
97d87491 RS |
8145 | case '+': |
8146 | switch (args[1]) | |
8147 | { | |
97d87491 RS |
8148 | case 'i': |
8149 | *offset_reloc = BFD_RELOC_MIPS_JMP; | |
8150 | break; | |
7361da2c AB |
8151 | |
8152 | case '\'': | |
8153 | *offset_reloc = BFD_RELOC_MIPS_26_PCREL_S2; | |
8154 | break; | |
8155 | ||
8156 | case '\"': | |
8157 | *offset_reloc = BFD_RELOC_MIPS_21_PCREL_S2; | |
8158 | break; | |
97d87491 RS |
8159 | } |
8160 | break; | |
8161 | ||
97d87491 | 8162 | case 'I': |
1a00e612 RS |
8163 | if (!match_const_int (&arg, &imm_expr.X_add_number)) |
8164 | return FALSE; | |
8165 | imm_expr.X_op = O_constant; | |
bad1aba3 | 8166 | if (GPR_SIZE == 32) |
97d87491 RS |
8167 | normalize_constant_expr (&imm_expr); |
8168 | continue; | |
8169 | ||
8170 | case 'A': | |
8171 | if (arg.token->type == OT_CHAR && arg.token->u.ch == '(') | |
8172 | { | |
8173 | /* Assume that the offset has been elided and that what | |
8174 | we saw was a base register. The match will fail later | |
8175 | if that assumption turns out to be wrong. */ | |
8176 | offset_expr.X_op = O_constant; | |
8177 | offset_expr.X_add_number = 0; | |
8178 | } | |
97d87491 | 8179 | else |
1a00e612 RS |
8180 | { |
8181 | if (!match_expression (&arg, &offset_expr, offset_reloc)) | |
8182 | return FALSE; | |
8183 | normalize_address_expr (&offset_expr); | |
8184 | } | |
97d87491 RS |
8185 | continue; |
8186 | ||
8187 | case 'F': | |
8188 | if (!match_float_constant (&arg, &imm_expr, &offset_expr, | |
8189 | 8, TRUE)) | |
1a00e612 | 8190 | return FALSE; |
97d87491 RS |
8191 | continue; |
8192 | ||
8193 | case 'L': | |
8194 | if (!match_float_constant (&arg, &imm_expr, &offset_expr, | |
8195 | 8, FALSE)) | |
1a00e612 | 8196 | return FALSE; |
97d87491 RS |
8197 | continue; |
8198 | ||
8199 | case 'f': | |
8200 | if (!match_float_constant (&arg, &imm_expr, &offset_expr, | |
8201 | 4, TRUE)) | |
1a00e612 | 8202 | return FALSE; |
97d87491 RS |
8203 | continue; |
8204 | ||
8205 | case 'l': | |
8206 | if (!match_float_constant (&arg, &imm_expr, &offset_expr, | |
8207 | 4, FALSE)) | |
1a00e612 | 8208 | return FALSE; |
97d87491 RS |
8209 | continue; |
8210 | ||
97d87491 RS |
8211 | case 'p': |
8212 | *offset_reloc = BFD_RELOC_16_PCREL_S2; | |
8213 | break; | |
8214 | ||
8215 | case 'a': | |
8216 | *offset_reloc = BFD_RELOC_MIPS_JMP; | |
8217 | break; | |
8218 | ||
8219 | case 'm': | |
8220 | gas_assert (mips_opts.micromips); | |
8221 | c = args[1]; | |
8222 | switch (c) | |
8223 | { | |
8224 | case 'D': | |
8225 | case 'E': | |
8226 | if (!forced_insn_length) | |
8227 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; | |
8228 | else if (c == 'D') | |
8229 | *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1; | |
8230 | else | |
8231 | *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1; | |
8232 | break; | |
8233 | } | |
8234 | break; | |
8235 | } | |
8236 | ||
8237 | operand = (mips_opts.micromips | |
8238 | ? decode_micromips_operand (args) | |
8239 | : decode_mips_operand (args)); | |
8240 | if (!operand) | |
8241 | abort (); | |
8242 | ||
8243 | /* Skip prefixes. */ | |
7361da2c | 8244 | if (*args == '+' || *args == 'm' || *args == '-') |
97d87491 RS |
8245 | args++; |
8246 | ||
8247 | if (mips_optional_operand_p (operand) | |
8248 | && args[1] == ',' | |
8249 | && (arg.token[0].type != OT_REG | |
8250 | || arg.token[1].type == OT_END)) | |
8251 | { | |
8252 | /* Assume that the register has been elided and is the | |
8253 | same as the first operand. */ | |
8254 | arg.token = tokens; | |
8255 | arg.argnum = 1; | |
8256 | } | |
8257 | ||
8258 | if (!match_operand (&arg, operand)) | |
8259 | return FALSE; | |
8260 | } | |
8261 | } | |
8262 | ||
8263 | /* Like match_insn, but for MIPS16. */ | |
8264 | ||
8265 | static bfd_boolean | |
8266 | match_mips16_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode, | |
1a00e612 | 8267 | struct mips_operand_token *tokens) |
97d87491 RS |
8268 | { |
8269 | const char *args; | |
8270 | const struct mips_operand *operand; | |
8271 | const struct mips_operand *ext_operand; | |
82d808ed | 8272 | bfd_boolean pcrel = FALSE; |
7fd53920 | 8273 | int required_insn_length; |
97d87491 RS |
8274 | struct mips_arg_info arg; |
8275 | int relax_char; | |
8276 | ||
7fd53920 MR |
8277 | if (forced_insn_length) |
8278 | required_insn_length = forced_insn_length; | |
8279 | else if (mips_opts.noautoextend && !mips_opcode_32bit_p (opcode)) | |
8280 | required_insn_length = 2; | |
8281 | else | |
8282 | required_insn_length = 0; | |
8283 | ||
97d87491 RS |
8284 | create_insn (insn, opcode); |
8285 | imm_expr.X_op = O_absent; | |
97d87491 RS |
8286 | offset_expr.X_op = O_absent; |
8287 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
8288 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
8289 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
8290 | relax_char = 0; | |
8291 | ||
8292 | memset (&arg, 0, sizeof (arg)); | |
8293 | arg.insn = insn; | |
8294 | arg.token = tokens; | |
8295 | arg.argnum = 1; | |
8296 | arg.last_regno = ILLEGAL_REG; | |
8297 | arg.dest_regno = ILLEGAL_REG; | |
97d87491 RS |
8298 | relax_char = 0; |
8299 | for (args = opcode->args;; ++args) | |
8300 | { | |
8301 | int c; | |
8302 | ||
8303 | if (arg.token->type == OT_END) | |
8304 | { | |
8305 | offsetT value; | |
8306 | ||
8307 | /* Handle unary instructions in which only one operand is given. | |
8308 | The source is then the same as the destination. */ | |
8309 | if (arg.opnum == 1 && *args == ',') | |
8310 | { | |
8311 | operand = decode_mips16_operand (args[1], FALSE); | |
8312 | if (operand && mips_optional_operand_p (operand)) | |
8313 | { | |
8314 | arg.token = tokens; | |
8315 | arg.argnum = 1; | |
8316 | continue; | |
8317 | } | |
8318 | } | |
8319 | ||
8320 | /* Fail the match if there were too few operands. */ | |
8321 | if (*args) | |
8322 | return FALSE; | |
8323 | ||
8324 | /* Successful match. Stuff the immediate value in now, if | |
8325 | we can. */ | |
e3de51ce | 8326 | clear_insn_error (); |
97d87491 RS |
8327 | if (opcode->pinfo == INSN_MACRO) |
8328 | { | |
8329 | gas_assert (relax_char == 0 || relax_char == 'p'); | |
8330 | gas_assert (*offset_reloc == BFD_RELOC_UNUSED); | |
8331 | } | |
8332 | else if (relax_char | |
8333 | && offset_expr.X_op == O_constant | |
82d808ed | 8334 | && !pcrel |
97d87491 RS |
8335 | && calculate_reloc (*offset_reloc, |
8336 | offset_expr.X_add_number, | |
8337 | &value)) | |
8338 | { | |
8339 | mips16_immed (NULL, 0, relax_char, *offset_reloc, value, | |
7fd53920 | 8340 | required_insn_length, &insn->insn_opcode); |
97d87491 RS |
8341 | offset_expr.X_op = O_absent; |
8342 | *offset_reloc = BFD_RELOC_UNUSED; | |
8343 | } | |
8344 | else if (relax_char && *offset_reloc != BFD_RELOC_UNUSED) | |
8345 | { | |
7fd53920 | 8346 | if (required_insn_length == 2) |
e3de51ce | 8347 | set_insn_error (0, _("invalid unextended operand value")); |
25499ac7 | 8348 | else if (!mips_opcode_32bit_p (opcode)) |
1da43acc MR |
8349 | { |
8350 | forced_insn_length = 4; | |
8351 | insn->insn_opcode |= MIPS16_EXTEND; | |
8352 | } | |
97d87491 RS |
8353 | } |
8354 | else if (relax_char) | |
8355 | *offset_reloc = (int) BFD_RELOC_UNUSED + relax_char; | |
8356 | ||
8357 | check_completed_insn (&arg); | |
8358 | return TRUE; | |
8359 | } | |
8360 | ||
8361 | /* Fail the match if the line has too many operands. */ | |
8362 | if (*args == 0) | |
8363 | return FALSE; | |
8364 | ||
8365 | /* Handle characters that need to match exactly. */ | |
8366 | if (*args == '(' || *args == ')' || *args == ',') | |
8367 | { | |
8368 | if (match_char (&arg, *args)) | |
8369 | continue; | |
8370 | return FALSE; | |
8371 | } | |
8372 | ||
8373 | arg.opnum += 1; | |
8374 | c = *args; | |
8375 | switch (c) | |
8376 | { | |
8377 | case 'p': | |
8378 | case 'q': | |
8379 | case 'A': | |
8380 | case 'B': | |
8381 | case 'E': | |
25499ac7 MR |
8382 | case 'V': |
8383 | case 'u': | |
97d87491 RS |
8384 | relax_char = c; |
8385 | break; | |
8386 | ||
8387 | case 'I': | |
1a00e612 RS |
8388 | if (!match_const_int (&arg, &imm_expr.X_add_number)) |
8389 | return FALSE; | |
8390 | imm_expr.X_op = O_constant; | |
bad1aba3 | 8391 | if (GPR_SIZE == 32) |
97d87491 RS |
8392 | normalize_constant_expr (&imm_expr); |
8393 | continue; | |
8394 | ||
8395 | case 'a': | |
8396 | case 'i': | |
8397 | *offset_reloc = BFD_RELOC_MIPS16_JMP; | |
97d87491 RS |
8398 | break; |
8399 | } | |
8400 | ||
7fd53920 | 8401 | operand = decode_mips16_operand (c, mips_opcode_32bit_p (opcode)); |
97d87491 RS |
8402 | if (!operand) |
8403 | abort (); | |
8404 | ||
82d808ed MR |
8405 | if (operand->type == OP_PCREL) |
8406 | pcrel = TRUE; | |
8407 | else | |
97d87491 RS |
8408 | { |
8409 | ext_operand = decode_mips16_operand (c, TRUE); | |
8410 | if (operand != ext_operand) | |
8411 | { | |
8412 | if (arg.token->type == OT_CHAR && arg.token->u.ch == '(') | |
8413 | { | |
8414 | offset_expr.X_op = O_constant; | |
8415 | offset_expr.X_add_number = 0; | |
8416 | relax_char = c; | |
8417 | continue; | |
8418 | } | |
8419 | ||
1a7bf198 | 8420 | if (!match_expression (&arg, &offset_expr, offset_reloc)) |
97d87491 RS |
8421 | return FALSE; |
8422 | ||
8423 | /* '8' is used for SLTI(U) and has traditionally not | |
8424 | been allowed to take relocation operators. */ | |
8425 | if (offset_reloc[0] != BFD_RELOC_UNUSED | |
8426 | && (ext_operand->size != 16 || c == '8')) | |
e295202f MR |
8427 | { |
8428 | match_not_constant (&arg); | |
8429 | return FALSE; | |
8430 | } | |
97d87491 | 8431 | |
c96425c5 MR |
8432 | if (offset_expr.X_op == O_big) |
8433 | { | |
8434 | match_out_of_range (&arg); | |
8435 | return FALSE; | |
8436 | } | |
8437 | ||
97d87491 RS |
8438 | relax_char = c; |
8439 | continue; | |
8440 | } | |
8441 | } | |
8442 | ||
8443 | if (mips_optional_operand_p (operand) | |
8444 | && args[1] == ',' | |
8445 | && (arg.token[0].type != OT_REG | |
8446 | || arg.token[1].type == OT_END)) | |
8447 | { | |
8448 | /* Assume that the register has been elided and is the | |
8449 | same as the first operand. */ | |
8450 | arg.token = tokens; | |
8451 | arg.argnum = 1; | |
8452 | } | |
8453 | ||
8454 | if (!match_operand (&arg, operand)) | |
8455 | return FALSE; | |
8456 | } | |
8457 | } | |
8458 | ||
60f20e8b RS |
8459 | /* Record that the current instruction is invalid for the current ISA. */ |
8460 | ||
8461 | static void | |
8462 | match_invalid_for_isa (void) | |
8463 | { | |
8464 | set_insn_error_ss | |
1661c76c | 8465 | (0, _("opcode not supported on this processor: %s (%s)"), |
60f20e8b RS |
8466 | mips_cpu_info_from_arch (mips_opts.arch)->name, |
8467 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
8468 | } | |
8469 | ||
8470 | /* Try to match TOKENS against a series of opcode entries, starting at FIRST. | |
8471 | Return true if a definite match or failure was found, storing any match | |
8472 | in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode | |
8473 | (to handle things like VU0 suffixes). LAX_MATCH is true if we have already | |
8474 | tried and failed to match under normal conditions and now want to try a | |
8475 | more relaxed match. */ | |
8476 | ||
8477 | static bfd_boolean | |
8478 | match_insns (struct mips_cl_insn *insn, const struct mips_opcode *first, | |
8479 | const struct mips_opcode *past, struct mips_operand_token *tokens, | |
8480 | int opcode_extra, bfd_boolean lax_match) | |
8481 | { | |
8482 | const struct mips_opcode *opcode; | |
8483 | const struct mips_opcode *invalid_delay_slot; | |
8484 | bfd_boolean seen_valid_for_isa, seen_valid_for_size; | |
8485 | ||
8486 | /* Search for a match, ignoring alternatives that don't satisfy the | |
8487 | current ISA or forced_length. */ | |
8488 | invalid_delay_slot = 0; | |
8489 | seen_valid_for_isa = FALSE; | |
8490 | seen_valid_for_size = FALSE; | |
8491 | opcode = first; | |
8492 | do | |
8493 | { | |
8494 | gas_assert (strcmp (opcode->name, first->name) == 0); | |
8495 | if (is_opcode_valid (opcode)) | |
8496 | { | |
8497 | seen_valid_for_isa = TRUE; | |
8498 | if (is_size_valid (opcode)) | |
8499 | { | |
8500 | bfd_boolean delay_slot_ok; | |
8501 | ||
8502 | seen_valid_for_size = TRUE; | |
8503 | delay_slot_ok = is_delay_slot_valid (opcode); | |
8504 | if (match_insn (insn, opcode, tokens, opcode_extra, | |
8505 | lax_match, delay_slot_ok)) | |
8506 | { | |
8507 | if (!delay_slot_ok) | |
8508 | { | |
8509 | if (!invalid_delay_slot) | |
8510 | invalid_delay_slot = opcode; | |
8511 | } | |
8512 | else | |
8513 | return TRUE; | |
8514 | } | |
8515 | } | |
8516 | } | |
8517 | ++opcode; | |
8518 | } | |
8519 | while (opcode < past && strcmp (opcode->name, first->name) == 0); | |
8520 | ||
8521 | /* If the only matches we found had the wrong length for the delay slot, | |
8522 | pick the first such match. We'll issue an appropriate warning later. */ | |
8523 | if (invalid_delay_slot) | |
8524 | { | |
8525 | if (match_insn (insn, invalid_delay_slot, tokens, opcode_extra, | |
8526 | lax_match, TRUE)) | |
8527 | return TRUE; | |
8528 | abort (); | |
8529 | } | |
8530 | ||
8531 | /* Handle the case where we didn't try to match an instruction because | |
8532 | all the alternatives were incompatible with the current ISA. */ | |
8533 | if (!seen_valid_for_isa) | |
8534 | { | |
8535 | match_invalid_for_isa (); | |
8536 | return TRUE; | |
8537 | } | |
8538 | ||
8539 | /* Handle the case where we didn't try to match an instruction because | |
8540 | all the alternatives were of the wrong size. */ | |
8541 | if (!seen_valid_for_size) | |
8542 | { | |
8543 | if (mips_opts.insn32) | |
1661c76c | 8544 | set_insn_error (0, _("opcode not supported in the `insn32' mode")); |
60f20e8b RS |
8545 | else |
8546 | set_insn_error_i | |
1661c76c | 8547 | (0, _("unrecognized %d-bit version of microMIPS opcode"), |
60f20e8b RS |
8548 | 8 * forced_insn_length); |
8549 | return TRUE; | |
8550 | } | |
8551 | ||
8552 | return FALSE; | |
8553 | } | |
8554 | ||
8555 | /* Like match_insns, but for MIPS16. */ | |
8556 | ||
8557 | static bfd_boolean | |
8558 | match_mips16_insns (struct mips_cl_insn *insn, const struct mips_opcode *first, | |
8559 | struct mips_operand_token *tokens) | |
8560 | { | |
8561 | const struct mips_opcode *opcode; | |
8562 | bfd_boolean seen_valid_for_isa; | |
7fd53920 | 8563 | bfd_boolean seen_valid_for_size; |
60f20e8b RS |
8564 | |
8565 | /* Search for a match, ignoring alternatives that don't satisfy the | |
8566 | current ISA. There are no separate entries for extended forms so | |
8567 | we deal with forced_length later. */ | |
8568 | seen_valid_for_isa = FALSE; | |
7fd53920 | 8569 | seen_valid_for_size = FALSE; |
60f20e8b RS |
8570 | opcode = first; |
8571 | do | |
8572 | { | |
8573 | gas_assert (strcmp (opcode->name, first->name) == 0); | |
8574 | if (is_opcode_valid_16 (opcode)) | |
8575 | { | |
8576 | seen_valid_for_isa = TRUE; | |
7fd53920 MR |
8577 | if (is_size_valid_16 (opcode)) |
8578 | { | |
8579 | seen_valid_for_size = TRUE; | |
8580 | if (match_mips16_insn (insn, opcode, tokens)) | |
8581 | return TRUE; | |
8582 | } | |
60f20e8b RS |
8583 | } |
8584 | ++opcode; | |
8585 | } | |
8586 | while (opcode < &mips16_opcodes[bfd_mips16_num_opcodes] | |
8587 | && strcmp (opcode->name, first->name) == 0); | |
8588 | ||
8589 | /* Handle the case where we didn't try to match an instruction because | |
8590 | all the alternatives were incompatible with the current ISA. */ | |
8591 | if (!seen_valid_for_isa) | |
8592 | { | |
8593 | match_invalid_for_isa (); | |
8594 | return TRUE; | |
8595 | } | |
8596 | ||
7fd53920 MR |
8597 | /* Handle the case where we didn't try to match an instruction because |
8598 | all the alternatives were of the wrong size. */ | |
8599 | if (!seen_valid_for_size) | |
8600 | { | |
8601 | if (forced_insn_length == 2) | |
8602 | set_insn_error | |
8603 | (0, _("unrecognized unextended version of MIPS16 opcode")); | |
8604 | else | |
8605 | set_insn_error | |
8606 | (0, _("unrecognized extended version of MIPS16 opcode")); | |
8607 | return TRUE; | |
8608 | } | |
8609 | ||
60f20e8b RS |
8610 | return FALSE; |
8611 | } | |
8612 | ||
584892a6 RS |
8613 | /* Set up global variables for the start of a new macro. */ |
8614 | ||
8615 | static void | |
8616 | macro_start (void) | |
8617 | { | |
8618 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
df58fc94 RS |
8619 | memset (&mips_macro_warning.first_insn_sizes, 0, |
8620 | sizeof (mips_macro_warning.first_insn_sizes)); | |
8621 | memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns)); | |
584892a6 | 8622 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder |
11625dd8 | 8623 | && delayed_branch_p (&history[0])); |
7bd374a4 MR |
8624 | if (history[0].frag |
8625 | && history[0].frag->fr_type == rs_machine_dependent | |
8626 | && RELAX_MICROMIPS_P (history[0].frag->fr_subtype) | |
8627 | && RELAX_MICROMIPS_NODS (history[0].frag->fr_subtype)) | |
8628 | mips_macro_warning.delay_slot_length = 0; | |
8629 | else | |
8630 | switch (history[0].insn_mo->pinfo2 | |
8631 | & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT)) | |
8632 | { | |
8633 | case INSN2_BRANCH_DELAY_32BIT: | |
8634 | mips_macro_warning.delay_slot_length = 4; | |
8635 | break; | |
8636 | case INSN2_BRANCH_DELAY_16BIT: | |
8637 | mips_macro_warning.delay_slot_length = 2; | |
8638 | break; | |
8639 | default: | |
8640 | mips_macro_warning.delay_slot_length = 0; | |
8641 | break; | |
8642 | } | |
df58fc94 | 8643 | mips_macro_warning.first_frag = NULL; |
584892a6 RS |
8644 | } |
8645 | ||
df58fc94 RS |
8646 | /* Given that a macro is longer than one instruction or of the wrong size, |
8647 | return the appropriate warning for it. Return null if no warning is | |
8648 | needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT, | |
8649 | RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND, | |
8650 | and RELAX_NOMACRO. */ | |
584892a6 RS |
8651 | |
8652 | static const char * | |
8653 | macro_warning (relax_substateT subtype) | |
8654 | { | |
8655 | if (subtype & RELAX_DELAY_SLOT) | |
1661c76c | 8656 | return _("macro instruction expanded into multiple instructions" |
584892a6 RS |
8657 | " in a branch delay slot"); |
8658 | else if (subtype & RELAX_NOMACRO) | |
1661c76c | 8659 | return _("macro instruction expanded into multiple instructions"); |
df58fc94 RS |
8660 | else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST |
8661 | | RELAX_DELAY_SLOT_SIZE_SECOND)) | |
8662 | return ((subtype & RELAX_DELAY_SLOT_16BIT) | |
1661c76c | 8663 | ? _("macro instruction expanded into a wrong size instruction" |
df58fc94 | 8664 | " in a 16-bit branch delay slot") |
1661c76c | 8665 | : _("macro instruction expanded into a wrong size instruction" |
df58fc94 | 8666 | " in a 32-bit branch delay slot")); |
584892a6 RS |
8667 | else |
8668 | return 0; | |
8669 | } | |
8670 | ||
8671 | /* Finish up a macro. Emit warnings as appropriate. */ | |
8672 | ||
8673 | static void | |
8674 | macro_end (void) | |
8675 | { | |
df58fc94 RS |
8676 | /* Relaxation warning flags. */ |
8677 | relax_substateT subtype = 0; | |
8678 | ||
8679 | /* Check delay slot size requirements. */ | |
8680 | if (mips_macro_warning.delay_slot_length == 2) | |
8681 | subtype |= RELAX_DELAY_SLOT_16BIT; | |
8682 | if (mips_macro_warning.delay_slot_length != 0) | |
584892a6 | 8683 | { |
df58fc94 RS |
8684 | if (mips_macro_warning.delay_slot_length |
8685 | != mips_macro_warning.first_insn_sizes[0]) | |
8686 | subtype |= RELAX_DELAY_SLOT_SIZE_FIRST; | |
8687 | if (mips_macro_warning.delay_slot_length | |
8688 | != mips_macro_warning.first_insn_sizes[1]) | |
8689 | subtype |= RELAX_DELAY_SLOT_SIZE_SECOND; | |
8690 | } | |
584892a6 | 8691 | |
df58fc94 RS |
8692 | /* Check instruction count requirements. */ |
8693 | if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1) | |
8694 | { | |
8695 | if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0]) | |
584892a6 RS |
8696 | subtype |= RELAX_SECOND_LONGER; |
8697 | if (mips_opts.warn_about_macros) | |
8698 | subtype |= RELAX_NOMACRO; | |
8699 | if (mips_macro_warning.delay_slot_p) | |
8700 | subtype |= RELAX_DELAY_SLOT; | |
df58fc94 | 8701 | } |
584892a6 | 8702 | |
df58fc94 RS |
8703 | /* If both alternatives fail to fill a delay slot correctly, |
8704 | emit the warning now. */ | |
8705 | if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0 | |
8706 | && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0) | |
8707 | { | |
8708 | relax_substateT s; | |
8709 | const char *msg; | |
8710 | ||
8711 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
8712 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
8713 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
8714 | msg = macro_warning (s); | |
8715 | if (msg != NULL) | |
8716 | as_warn ("%s", msg); | |
8717 | subtype &= ~s; | |
8718 | } | |
8719 | ||
8720 | /* If both implementations are longer than 1 instruction, then emit the | |
8721 | warning now. */ | |
8722 | if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1) | |
8723 | { | |
8724 | relax_substateT s; | |
8725 | const char *msg; | |
8726 | ||
8727 | s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT); | |
8728 | msg = macro_warning (s); | |
8729 | if (msg != NULL) | |
8730 | as_warn ("%s", msg); | |
8731 | subtype &= ~s; | |
584892a6 | 8732 | } |
df58fc94 RS |
8733 | |
8734 | /* If any flags still set, then one implementation might need a warning | |
8735 | and the other either will need one of a different kind or none at all. | |
8736 | Pass any remaining flags over to relaxation. */ | |
8737 | if (mips_macro_warning.first_frag != NULL) | |
8738 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
584892a6 RS |
8739 | } |
8740 | ||
df58fc94 RS |
8741 | /* Instruction operand formats used in macros that vary between |
8742 | standard MIPS and microMIPS code. */ | |
8743 | ||
833794fc | 8744 | static const char * const brk_fmt[2][2] = { { "c", "c" }, { "mF", "c" } }; |
df58fc94 RS |
8745 | static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" }; |
8746 | static const char * const jalr_fmt[2] = { "d,s", "t,s" }; | |
8747 | static const char * const lui_fmt[2] = { "t,u", "s,u" }; | |
8748 | static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" }; | |
833794fc | 8749 | static const char * const mfhl_fmt[2][2] = { { "d", "d" }, { "mj", "s" } }; |
df58fc94 RS |
8750 | static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" }; |
8751 | static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" }; | |
8752 | ||
833794fc | 8753 | #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32]) |
7361da2c AB |
8754 | #define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \ |
8755 | : cop12_fmt[mips_opts.micromips]) | |
df58fc94 RS |
8756 | #define JALR_FMT (jalr_fmt[mips_opts.micromips]) |
8757 | #define LUI_FMT (lui_fmt[mips_opts.micromips]) | |
8758 | #define MEM12_FMT (mem12_fmt[mips_opts.micromips]) | |
7361da2c AB |
8759 | #define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \ |
8760 | : mem12_fmt[mips_opts.micromips]) | |
833794fc | 8761 | #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32]) |
df58fc94 RS |
8762 | #define SHFT_FMT (shft_fmt[mips_opts.micromips]) |
8763 | #define TRAP_FMT (trap_fmt[mips_opts.micromips]) | |
8764 | ||
6e1304d8 RS |
8765 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
8766 | The first argument in *ARGS will be either the code for a single | |
8767 | relocation or -1 followed by the three codes that make up a | |
8768 | composite relocation. */ | |
8769 | ||
8770 | static void | |
8771 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
8772 | { | |
8773 | int i, next; | |
8774 | ||
8775 | next = va_arg (*args, int); | |
8776 | if (next >= 0) | |
8777 | r[0] = (bfd_reloc_code_real_type) next; | |
8778 | else | |
f2ae14a1 RS |
8779 | { |
8780 | for (i = 0; i < 3; i++) | |
8781 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
8782 | /* This function is only used for 16-bit relocation fields. | |
8783 | To make the macro code simpler, treat an unrelocated value | |
8784 | in the same way as BFD_RELOC_LO16. */ | |
8785 | if (r[0] == BFD_RELOC_UNUSED) | |
8786 | r[0] = BFD_RELOC_LO16; | |
8787 | } | |
6e1304d8 RS |
8788 | } |
8789 | ||
252b5132 RH |
8790 | /* Build an instruction created by a macro expansion. This is passed |
8791 | a pointer to the count of instructions created so far, an | |
8792 | expression, the name of the instruction to build, an operand format | |
8793 | string, and corresponding arguments. */ | |
8794 | ||
252b5132 | 8795 | static void |
67c0d1eb | 8796 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 | 8797 | { |
df58fc94 | 8798 | const struct mips_opcode *mo = NULL; |
f6688943 | 8799 | bfd_reloc_code_real_type r[3]; |
df58fc94 | 8800 | const struct mips_opcode *amo; |
e077a1c8 | 8801 | const struct mips_operand *operand; |
df58fc94 RS |
8802 | struct hash_control *hash; |
8803 | struct mips_cl_insn insn; | |
252b5132 | 8804 | va_list args; |
e077a1c8 | 8805 | unsigned int uval; |
252b5132 | 8806 | |
252b5132 | 8807 | va_start (args, fmt); |
252b5132 | 8808 | |
252b5132 RH |
8809 | if (mips_opts.mips16) |
8810 | { | |
03ea81db | 8811 | mips16_macro_build (ep, name, fmt, &args); |
252b5132 RH |
8812 | va_end (args); |
8813 | return; | |
8814 | } | |
8815 | ||
f6688943 TS |
8816 | r[0] = BFD_RELOC_UNUSED; |
8817 | r[1] = BFD_RELOC_UNUSED; | |
8818 | r[2] = BFD_RELOC_UNUSED; | |
df58fc94 RS |
8819 | hash = mips_opts.micromips ? micromips_op_hash : op_hash; |
8820 | amo = (struct mips_opcode *) hash_find (hash, name); | |
8821 | gas_assert (amo); | |
8822 | gas_assert (strcmp (name, amo->name) == 0); | |
1e915849 | 8823 | |
df58fc94 | 8824 | do |
8b082fb1 TS |
8825 | { |
8826 | /* Search until we get a match for NAME. It is assumed here that | |
df58fc94 | 8827 | macros will never generate MDMX, MIPS-3D, or MT instructions. |
33eaf5de | 8828 | We try to match an instruction that fulfills the branch delay |
df58fc94 RS |
8829 | slot instruction length requirement (if any) of the previous |
8830 | instruction. While doing this we record the first instruction | |
8831 | seen that matches all the other conditions and use it anyway | |
8832 | if the requirement cannot be met; we will issue an appropriate | |
8833 | warning later on. */ | |
8834 | if (strcmp (fmt, amo->args) == 0 | |
8835 | && amo->pinfo != INSN_MACRO | |
8836 | && is_opcode_valid (amo) | |
8837 | && is_size_valid (amo)) | |
8838 | { | |
8839 | if (is_delay_slot_valid (amo)) | |
8840 | { | |
8841 | mo = amo; | |
8842 | break; | |
8843 | } | |
8844 | else if (!mo) | |
8845 | mo = amo; | |
8846 | } | |
8b082fb1 | 8847 | |
df58fc94 RS |
8848 | ++amo; |
8849 | gas_assert (amo->name); | |
252b5132 | 8850 | } |
df58fc94 | 8851 | while (strcmp (name, amo->name) == 0); |
252b5132 | 8852 | |
df58fc94 | 8853 | gas_assert (mo); |
1e915849 | 8854 | create_insn (&insn, mo); |
e077a1c8 | 8855 | for (; *fmt; ++fmt) |
252b5132 | 8856 | { |
e077a1c8 | 8857 | switch (*fmt) |
252b5132 | 8858 | { |
252b5132 RH |
8859 | case ',': |
8860 | case '(': | |
8861 | case ')': | |
252b5132 | 8862 | case 'z': |
e077a1c8 | 8863 | break; |
252b5132 RH |
8864 | |
8865 | case 'i': | |
8866 | case 'j': | |
6e1304d8 | 8867 | macro_read_relocs (&args, r); |
9c2799c2 | 8868 | gas_assert (*r == BFD_RELOC_GPREL16 |
e391c024 RS |
8869 | || *r == BFD_RELOC_MIPS_HIGHER |
8870 | || *r == BFD_RELOC_HI16_S | |
8871 | || *r == BFD_RELOC_LO16 | |
14c80123 MR |
8872 | || *r == BFD_RELOC_MIPS_GOT_OFST |
8873 | || (mips_opts.micromips | |
8874 | && (*r == BFD_RELOC_16 | |
8875 | || *r == BFD_RELOC_MIPS_GOT16 | |
8876 | || *r == BFD_RELOC_MIPS_CALL16 | |
8877 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
8878 | || *r == BFD_RELOC_MIPS_GOT_LO16 | |
8879 | || *r == BFD_RELOC_MIPS_CALL_HI16 | |
8880 | || *r == BFD_RELOC_MIPS_CALL_LO16 | |
8881 | || *r == BFD_RELOC_MIPS_SUB | |
8882 | || *r == BFD_RELOC_MIPS_GOT_PAGE | |
8883 | || *r == BFD_RELOC_MIPS_HIGHEST | |
8884 | || *r == BFD_RELOC_MIPS_GOT_DISP | |
8885 | || *r == BFD_RELOC_MIPS_TLS_GD | |
8886 | || *r == BFD_RELOC_MIPS_TLS_LDM | |
8887 | || *r == BFD_RELOC_MIPS_TLS_DTPREL_HI16 | |
8888 | || *r == BFD_RELOC_MIPS_TLS_DTPREL_LO16 | |
8889 | || *r == BFD_RELOC_MIPS_TLS_GOTTPREL | |
8890 | || *r == BFD_RELOC_MIPS_TLS_TPREL_HI16 | |
8891 | || *r == BFD_RELOC_MIPS_TLS_TPREL_LO16))); | |
e077a1c8 | 8892 | break; |
e391c024 RS |
8893 | |
8894 | case 'o': | |
8895 | macro_read_relocs (&args, r); | |
e077a1c8 | 8896 | break; |
252b5132 RH |
8897 | |
8898 | case 'u': | |
6e1304d8 | 8899 | macro_read_relocs (&args, r); |
9c2799c2 | 8900 | gas_assert (ep != NULL |
90ecf173 MR |
8901 | && (ep->X_op == O_constant |
8902 | || (ep->X_op == O_symbol | |
8903 | && (*r == BFD_RELOC_MIPS_HIGHEST | |
8904 | || *r == BFD_RELOC_HI16_S | |
8905 | || *r == BFD_RELOC_HI16 | |
8906 | || *r == BFD_RELOC_GPREL16 | |
8907 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
8908 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); | |
e077a1c8 | 8909 | break; |
252b5132 RH |
8910 | |
8911 | case 'p': | |
9c2799c2 | 8912 | gas_assert (ep != NULL); |
bad36eac | 8913 | |
252b5132 RH |
8914 | /* |
8915 | * This allows macro() to pass an immediate expression for | |
8916 | * creating short branches without creating a symbol. | |
bad36eac DJ |
8917 | * |
8918 | * We don't allow branch relaxation for these branches, as | |
8919 | * they should only appear in ".set nomacro" anyway. | |
252b5132 RH |
8920 | */ |
8921 | if (ep->X_op == O_constant) | |
8922 | { | |
df58fc94 RS |
8923 | /* For microMIPS we always use relocations for branches. |
8924 | So we should not resolve immediate values. */ | |
8925 | gas_assert (!mips_opts.micromips); | |
8926 | ||
bad36eac DJ |
8927 | if ((ep->X_add_number & 3) != 0) |
8928 | as_bad (_("branch to misaligned address (0x%lx)"), | |
8929 | (unsigned long) ep->X_add_number); | |
8930 | if ((ep->X_add_number + 0x20000) & ~0x3ffff) | |
8931 | as_bad (_("branch address range overflow (0x%lx)"), | |
8932 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
8933 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; |
8934 | ep = NULL; | |
8935 | } | |
8936 | else | |
0b25d3e6 | 8937 | *r = BFD_RELOC_16_PCREL_S2; |
e077a1c8 | 8938 | break; |
252b5132 RH |
8939 | |
8940 | case 'a': | |
9c2799c2 | 8941 | gas_assert (ep != NULL); |
f6688943 | 8942 | *r = BFD_RELOC_MIPS_JMP; |
e077a1c8 | 8943 | break; |
d43b4baf | 8944 | |
252b5132 | 8945 | default: |
e077a1c8 RS |
8946 | operand = (mips_opts.micromips |
8947 | ? decode_micromips_operand (fmt) | |
8948 | : decode_mips_operand (fmt)); | |
8949 | if (!operand) | |
8950 | abort (); | |
8951 | ||
8952 | uval = va_arg (args, int); | |
8953 | if (operand->type == OP_CLO_CLZ_DEST) | |
8954 | uval |= (uval << 5); | |
8955 | insn_insert_operand (&insn, operand, uval); | |
8956 | ||
7361da2c | 8957 | if (*fmt == '+' || *fmt == 'm' || *fmt == '-') |
e077a1c8 RS |
8958 | ++fmt; |
8959 | break; | |
252b5132 | 8960 | } |
252b5132 RH |
8961 | } |
8962 | va_end (args); | |
9c2799c2 | 8963 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 8964 | |
df58fc94 | 8965 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
8966 | } |
8967 | ||
8968 | static void | |
67c0d1eb | 8969 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
03ea81db | 8970 | va_list *args) |
252b5132 | 8971 | { |
1e915849 | 8972 | struct mips_opcode *mo; |
252b5132 | 8973 | struct mips_cl_insn insn; |
e077a1c8 | 8974 | const struct mips_operand *operand; |
f6688943 TS |
8975 | bfd_reloc_code_real_type r[3] |
8976 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 8977 | |
1e915849 | 8978 | mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
9c2799c2 NC |
8979 | gas_assert (mo); |
8980 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 | 8981 | |
1e915849 | 8982 | while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) |
252b5132 | 8983 | { |
1e915849 | 8984 | ++mo; |
9c2799c2 NC |
8985 | gas_assert (mo->name); |
8986 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
8987 | } |
8988 | ||
1e915849 | 8989 | create_insn (&insn, mo); |
e077a1c8 | 8990 | for (; *fmt; ++fmt) |
252b5132 RH |
8991 | { |
8992 | int c; | |
8993 | ||
e077a1c8 | 8994 | c = *fmt; |
252b5132 RH |
8995 | switch (c) |
8996 | { | |
252b5132 RH |
8997 | case ',': |
8998 | case '(': | |
8999 | case ')': | |
e077a1c8 | 9000 | break; |
252b5132 | 9001 | |
d8722d76 | 9002 | case '.': |
252b5132 RH |
9003 | case 'S': |
9004 | case 'P': | |
9005 | case 'R': | |
e077a1c8 | 9006 | break; |
252b5132 RH |
9007 | |
9008 | case '<': | |
252b5132 | 9009 | case '5': |
d8722d76 | 9010 | case 'F': |
252b5132 RH |
9011 | case 'H': |
9012 | case 'W': | |
9013 | case 'D': | |
9014 | case 'j': | |
9015 | case '8': | |
9016 | case 'V': | |
9017 | case 'C': | |
9018 | case 'U': | |
9019 | case 'k': | |
9020 | case 'K': | |
9021 | case 'p': | |
9022 | case 'q': | |
9023 | { | |
b886a2ab RS |
9024 | offsetT value; |
9025 | ||
9c2799c2 | 9026 | gas_assert (ep != NULL); |
252b5132 RH |
9027 | |
9028 | if (ep->X_op != O_constant) | |
874e8986 | 9029 | *r = (int) BFD_RELOC_UNUSED + c; |
b886a2ab | 9030 | else if (calculate_reloc (*r, ep->X_add_number, &value)) |
252b5132 | 9031 | { |
b886a2ab | 9032 | mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode); |
252b5132 | 9033 | ep = NULL; |
f6688943 | 9034 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
9035 | } |
9036 | } | |
e077a1c8 | 9037 | break; |
252b5132 | 9038 | |
e077a1c8 RS |
9039 | default: |
9040 | operand = decode_mips16_operand (c, FALSE); | |
9041 | if (!operand) | |
9042 | abort (); | |
252b5132 | 9043 | |
4a06e5a2 | 9044 | insn_insert_operand (&insn, operand, va_arg (*args, int)); |
e077a1c8 RS |
9045 | break; |
9046 | } | |
252b5132 RH |
9047 | } |
9048 | ||
9c2799c2 | 9049 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 9050 | |
df58fc94 | 9051 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
9052 | } |
9053 | ||
438c16b8 TS |
9054 | /* |
9055 | * Generate a "jalr" instruction with a relocation hint to the called | |
9056 | * function. This occurs in NewABI PIC code. | |
9057 | */ | |
9058 | static void | |
df58fc94 | 9059 | macro_build_jalr (expressionS *ep, int cprestore) |
438c16b8 | 9060 | { |
df58fc94 RS |
9061 | static const bfd_reloc_code_real_type jalr_relocs[2] |
9062 | = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR }; | |
9063 | bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips]; | |
9064 | const char *jalr; | |
685736be | 9065 | char *f = NULL; |
b34976b6 | 9066 | |
1180b5a4 | 9067 | if (MIPS_JALR_HINT_P (ep)) |
f21f8242 | 9068 | { |
cc3d92a5 | 9069 | frag_grow (8); |
f21f8242 AO |
9070 | f = frag_more (0); |
9071 | } | |
2906b037 | 9072 | if (mips_opts.micromips) |
df58fc94 | 9073 | { |
833794fc MR |
9074 | jalr = ((mips_opts.noreorder && !cprestore) || mips_opts.insn32 |
9075 | ? "jalr" : "jalrs"); | |
e64af278 | 9076 | if (MIPS_JALR_HINT_P (ep) |
833794fc | 9077 | || mips_opts.insn32 |
e64af278 | 9078 | || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
df58fc94 RS |
9079 | macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG); |
9080 | else | |
9081 | macro_build (NULL, jalr, "mj", PIC_CALL_REG); | |
9082 | } | |
2906b037 MR |
9083 | else |
9084 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); | |
1180b5a4 | 9085 | if (MIPS_JALR_HINT_P (ep)) |
df58fc94 | 9086 | fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc); |
438c16b8 TS |
9087 | } |
9088 | ||
252b5132 RH |
9089 | /* |
9090 | * Generate a "lui" instruction. | |
9091 | */ | |
9092 | static void | |
67c0d1eb | 9093 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 | 9094 | { |
9c2799c2 | 9095 | gas_assert (! mips_opts.mips16); |
252b5132 | 9096 | |
df58fc94 | 9097 | if (ep->X_op != O_constant) |
252b5132 | 9098 | { |
9c2799c2 | 9099 | gas_assert (ep->X_op == O_symbol); |
bbe506e8 TS |
9100 | /* _gp_disp is a special case, used from s_cpload. |
9101 | __gnu_local_gp is used if mips_no_shared. */ | |
9c2799c2 | 9102 | gas_assert (mips_pic == NO_PIC |
78e1bb40 | 9103 | || (! HAVE_NEWABI |
aa6975fb ILT |
9104 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
9105 | || (! mips_in_shared | |
bbe506e8 TS |
9106 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
9107 | "__gnu_local_gp") == 0)); | |
252b5132 RH |
9108 | } |
9109 | ||
df58fc94 | 9110 | macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S); |
252b5132 RH |
9111 | } |
9112 | ||
885add95 CD |
9113 | /* Generate a sequence of instructions to do a load or store from a constant |
9114 | offset off of a base register (breg) into/from a target register (treg), | |
9115 | using AT if necessary. */ | |
9116 | static void | |
67c0d1eb RS |
9117 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
9118 | int treg, int breg, int dbl) | |
885add95 | 9119 | { |
9c2799c2 | 9120 | gas_assert (ep->X_op == O_constant); |
885add95 | 9121 | |
256ab948 | 9122 | /* Sign-extending 32-bit constants makes their handling easier. */ |
2051e8c4 MR |
9123 | if (!dbl) |
9124 | normalize_constant_expr (ep); | |
256ab948 | 9125 | |
67c1ffbe | 9126 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 9127 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
9128 | as_warn (_("operand overflow")); |
9129 | ||
9130 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
9131 | { | |
9132 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 9133 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
9134 | } |
9135 | else | |
9136 | { | |
9137 | /* 32-bit offset, need multiple instructions and AT, like: | |
9138 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
9139 | addu $tempreg,$tempreg,$breg | |
9140 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
9141 | to handle the complete offset. */ | |
67c0d1eb RS |
9142 | macro_build_lui (ep, AT); |
9143 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
9144 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 | 9145 | |
741fe287 | 9146 | if (!mips_opts.at) |
1661c76c | 9147 | as_bad (_("macro used $at after \".set noat\"")); |
885add95 CD |
9148 | } |
9149 | } | |
9150 | ||
252b5132 RH |
9151 | /* set_at() |
9152 | * Generates code to set the $at register to true (one) | |
9153 | * if reg is less than the immediate expression. | |
9154 | */ | |
9155 | static void | |
67c0d1eb | 9156 | set_at (int reg, int unsignedp) |
252b5132 | 9157 | { |
b0e6f033 | 9158 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 | 9159 | && imm_expr.X_add_number < 0x8000) |
67c0d1eb RS |
9160 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
9161 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
9162 | else |
9163 | { | |
bad1aba3 | 9164 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
67c0d1eb | 9165 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); |
252b5132 RH |
9166 | } |
9167 | } | |
9168 | ||
252b5132 RH |
9169 | /* Count the leading zeroes by performing a binary chop. This is a |
9170 | bulky bit of source, but performance is a LOT better for the | |
9171 | majority of values than a simple loop to count the bits: | |
9172 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
9173 | if ((v) & (1 << (31 - lcnt))) | |
9174 | break; | |
9175 | However it is not code size friendly, and the gain will drop a bit | |
9176 | on certain cached systems. | |
9177 | */ | |
9178 | #define COUNT_TOP_ZEROES(v) \ | |
9179 | (((v) & ~0xffff) == 0 \ | |
9180 | ? ((v) & ~0xff) == 0 \ | |
9181 | ? ((v) & ~0xf) == 0 \ | |
9182 | ? ((v) & ~0x3) == 0 \ | |
9183 | ? ((v) & ~0x1) == 0 \ | |
9184 | ? !(v) \ | |
9185 | ? 32 \ | |
9186 | : 31 \ | |
9187 | : 30 \ | |
9188 | : ((v) & ~0x7) == 0 \ | |
9189 | ? 29 \ | |
9190 | : 28 \ | |
9191 | : ((v) & ~0x3f) == 0 \ | |
9192 | ? ((v) & ~0x1f) == 0 \ | |
9193 | ? 27 \ | |
9194 | : 26 \ | |
9195 | : ((v) & ~0x7f) == 0 \ | |
9196 | ? 25 \ | |
9197 | : 24 \ | |
9198 | : ((v) & ~0xfff) == 0 \ | |
9199 | ? ((v) & ~0x3ff) == 0 \ | |
9200 | ? ((v) & ~0x1ff) == 0 \ | |
9201 | ? 23 \ | |
9202 | : 22 \ | |
9203 | : ((v) & ~0x7ff) == 0 \ | |
9204 | ? 21 \ | |
9205 | : 20 \ | |
9206 | : ((v) & ~0x3fff) == 0 \ | |
9207 | ? ((v) & ~0x1fff) == 0 \ | |
9208 | ? 19 \ | |
9209 | : 18 \ | |
9210 | : ((v) & ~0x7fff) == 0 \ | |
9211 | ? 17 \ | |
9212 | : 16 \ | |
9213 | : ((v) & ~0xffffff) == 0 \ | |
9214 | ? ((v) & ~0xfffff) == 0 \ | |
9215 | ? ((v) & ~0x3ffff) == 0 \ | |
9216 | ? ((v) & ~0x1ffff) == 0 \ | |
9217 | ? 15 \ | |
9218 | : 14 \ | |
9219 | : ((v) & ~0x7ffff) == 0 \ | |
9220 | ? 13 \ | |
9221 | : 12 \ | |
9222 | : ((v) & ~0x3fffff) == 0 \ | |
9223 | ? ((v) & ~0x1fffff) == 0 \ | |
9224 | ? 11 \ | |
9225 | : 10 \ | |
9226 | : ((v) & ~0x7fffff) == 0 \ | |
9227 | ? 9 \ | |
9228 | : 8 \ | |
9229 | : ((v) & ~0xfffffff) == 0 \ | |
9230 | ? ((v) & ~0x3ffffff) == 0 \ | |
9231 | ? ((v) & ~0x1ffffff) == 0 \ | |
9232 | ? 7 \ | |
9233 | : 6 \ | |
9234 | : ((v) & ~0x7ffffff) == 0 \ | |
9235 | ? 5 \ | |
9236 | : 4 \ | |
9237 | : ((v) & ~0x3fffffff) == 0 \ | |
9238 | ? ((v) & ~0x1fffffff) == 0 \ | |
9239 | ? 3 \ | |
9240 | : 2 \ | |
9241 | : ((v) & ~0x7fffffff) == 0 \ | |
9242 | ? 1 \ | |
9243 | : 0) | |
9244 | ||
9245 | /* load_register() | |
67c1ffbe | 9246 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
9247 | * an absolute expression value into a register. |
9248 | */ | |
9249 | static void | |
67c0d1eb | 9250 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
9251 | { |
9252 | int freg; | |
9253 | expressionS hi32, lo32; | |
9254 | ||
9255 | if (ep->X_op != O_big) | |
9256 | { | |
9c2799c2 | 9257 | gas_assert (ep->X_op == O_constant); |
256ab948 TS |
9258 | |
9259 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
2051e8c4 MR |
9260 | if (!dbl) |
9261 | normalize_constant_expr (ep); | |
256ab948 TS |
9262 | |
9263 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
9264 | { |
9265 | /* We can handle 16 bit signed values with an addiu to | |
9266 | $zero. No need to ever use daddiu here, since $zero and | |
9267 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 9268 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
9269 | return; |
9270 | } | |
9271 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
9272 | { | |
9273 | /* We can handle 16 bit unsigned values with an ori to | |
9274 | $zero. */ | |
67c0d1eb | 9275 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
9276 | return; |
9277 | } | |
256ab948 | 9278 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
9279 | { |
9280 | /* 32 bit values require an lui. */ | |
df58fc94 | 9281 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 9282 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 9283 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
9284 | return; |
9285 | } | |
9286 | } | |
9287 | ||
9288 | /* The value is larger than 32 bits. */ | |
9289 | ||
bad1aba3 | 9290 | if (!dbl || GPR_SIZE == 32) |
252b5132 | 9291 | { |
55e08f71 NC |
9292 | char value[32]; |
9293 | ||
9294 | sprintf_vma (value, ep->X_add_number); | |
1661c76c | 9295 | as_bad (_("number (0x%s) larger than 32 bits"), value); |
67c0d1eb | 9296 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
9297 | return; |
9298 | } | |
9299 | ||
9300 | if (ep->X_op != O_big) | |
9301 | { | |
9302 | hi32 = *ep; | |
9303 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
9304 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
9305 | hi32.X_add_number &= 0xffffffff; | |
9306 | lo32 = *ep; | |
9307 | lo32.X_add_number &= 0xffffffff; | |
9308 | } | |
9309 | else | |
9310 | { | |
9c2799c2 | 9311 | gas_assert (ep->X_add_number > 2); |
252b5132 RH |
9312 | if (ep->X_add_number == 3) |
9313 | generic_bignum[3] = 0; | |
9314 | else if (ep->X_add_number > 4) | |
1661c76c | 9315 | as_bad (_("number larger than 64 bits")); |
252b5132 RH |
9316 | lo32.X_op = O_constant; |
9317 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
9318 | hi32.X_op = O_constant; | |
9319 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
9320 | } | |
9321 | ||
9322 | if (hi32.X_add_number == 0) | |
9323 | freg = 0; | |
9324 | else | |
9325 | { | |
9326 | int shift, bit; | |
9327 | unsigned long hi, lo; | |
9328 | ||
956cd1d6 | 9329 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
9330 | { |
9331 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
9332 | { | |
67c0d1eb | 9333 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
9334 | return; |
9335 | } | |
9336 | if (lo32.X_add_number & 0x80000000) | |
9337 | { | |
df58fc94 | 9338 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 9339 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 9340 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
9341 | return; |
9342 | } | |
9343 | } | |
252b5132 RH |
9344 | |
9345 | /* Check for 16bit shifted constant. We know that hi32 is | |
9346 | non-zero, so start the mask on the first bit of the hi32 | |
9347 | value. */ | |
9348 | shift = 17; | |
9349 | do | |
beae10d5 KH |
9350 | { |
9351 | unsigned long himask, lomask; | |
9352 | ||
9353 | if (shift < 32) | |
9354 | { | |
9355 | himask = 0xffff >> (32 - shift); | |
9356 | lomask = (0xffff << shift) & 0xffffffff; | |
9357 | } | |
9358 | else | |
9359 | { | |
9360 | himask = 0xffff << (shift - 32); | |
9361 | lomask = 0; | |
9362 | } | |
9363 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
9364 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
9365 | { | |
9366 | expressionS tmp; | |
9367 | ||
9368 | tmp.X_op = O_constant; | |
9369 | if (shift < 32) | |
9370 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
9371 | | (lo32.X_add_number >> shift)); | |
9372 | else | |
9373 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb | 9374 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
df58fc94 | 9375 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 9376 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
9377 | return; |
9378 | } | |
f9419b05 | 9379 | ++shift; |
beae10d5 KH |
9380 | } |
9381 | while (shift <= (64 - 16)); | |
252b5132 RH |
9382 | |
9383 | /* Find the bit number of the lowest one bit, and store the | |
9384 | shifted value in hi/lo. */ | |
9385 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
9386 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
9387 | if (lo != 0) | |
9388 | { | |
9389 | bit = 0; | |
9390 | while ((lo & 1) == 0) | |
9391 | { | |
9392 | lo >>= 1; | |
9393 | ++bit; | |
9394 | } | |
9395 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
9396 | hi >>= bit; | |
9397 | } | |
9398 | else | |
9399 | { | |
9400 | bit = 32; | |
9401 | while ((hi & 1) == 0) | |
9402 | { | |
9403 | hi >>= 1; | |
9404 | ++bit; | |
9405 | } | |
9406 | lo = hi; | |
9407 | hi = 0; | |
9408 | } | |
9409 | ||
9410 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
9411 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
9412 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
9413 | { |
9414 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 9415 | if (shift != 0) |
beae10d5 | 9416 | { |
252b5132 RH |
9417 | expressionS tmp; |
9418 | ||
9419 | /* This instruction will set the register to be all | |
9420 | ones. */ | |
beae10d5 KH |
9421 | tmp.X_op = O_constant; |
9422 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 9423 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
9424 | if (bit != 0) |
9425 | { | |
9426 | bit += shift; | |
df58fc94 | 9427 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 9428 | reg, reg, (bit >= 32) ? bit - 32 : bit); |
beae10d5 | 9429 | } |
df58fc94 | 9430 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT, |
67c0d1eb | 9431 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
9432 | return; |
9433 | } | |
9434 | } | |
252b5132 RH |
9435 | |
9436 | /* Sign extend hi32 before calling load_register, because we can | |
9437 | generally get better code when we load a sign extended value. */ | |
9438 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 9439 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 9440 | load_register (reg, &hi32, 0); |
252b5132 RH |
9441 | freg = reg; |
9442 | } | |
9443 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
9444 | { | |
9445 | if (freg != 0) | |
9446 | { | |
df58fc94 | 9447 | macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0); |
252b5132 RH |
9448 | freg = reg; |
9449 | } | |
9450 | } | |
9451 | else | |
9452 | { | |
9453 | expressionS mid16; | |
9454 | ||
956cd1d6 | 9455 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 9456 | { |
df58fc94 RS |
9457 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
9458 | macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0); | |
beae10d5 KH |
9459 | return; |
9460 | } | |
252b5132 RH |
9461 | |
9462 | if (freg != 0) | |
9463 | { | |
df58fc94 | 9464 | macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16); |
252b5132 RH |
9465 | freg = reg; |
9466 | } | |
9467 | mid16 = lo32; | |
9468 | mid16.X_add_number >>= 16; | |
67c0d1eb | 9469 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
df58fc94 | 9470 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
252b5132 RH |
9471 | freg = reg; |
9472 | } | |
9473 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 9474 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
9475 | } |
9476 | ||
269137b2 TS |
9477 | static inline void |
9478 | load_delay_nop (void) | |
9479 | { | |
9480 | if (!gpr_interlocks) | |
9481 | macro_build (NULL, "nop", ""); | |
9482 | } | |
9483 | ||
252b5132 RH |
9484 | /* Load an address into a register. */ |
9485 | ||
9486 | static void | |
67c0d1eb | 9487 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 9488 | { |
252b5132 RH |
9489 | if (ep->X_op != O_constant |
9490 | && ep->X_op != O_symbol) | |
9491 | { | |
9492 | as_bad (_("expression too complex")); | |
9493 | ep->X_op = O_constant; | |
9494 | } | |
9495 | ||
9496 | if (ep->X_op == O_constant) | |
9497 | { | |
67c0d1eb | 9498 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
9499 | return; |
9500 | } | |
9501 | ||
9502 | if (mips_pic == NO_PIC) | |
9503 | { | |
9504 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 9505 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
9506 | Otherwise we want |
9507 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
9508 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 9509 | If we have an addend, we always use the latter form. |
76b3015f | 9510 | |
d6bc6245 TS |
9511 | With 64bit address space and a usable $at we want |
9512 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
9513 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
9514 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
9515 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
9516 | dsll32 $reg,0 | |
3a482fd5 | 9517 | daddu $reg,$reg,$at |
76b3015f | 9518 | |
c03099e6 | 9519 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
9520 | on superscalar processors. |
9521 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
9522 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
9523 | dsll $reg,16 | |
9524 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
9525 | dsll $reg,16 | |
9526 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
6caf9ef4 TS |
9527 | |
9528 | For GP relative symbols in 64bit address space we can use | |
9529 | the same sequence as in 32bit address space. */ | |
aed1a261 | 9530 | if (HAVE_64BIT_SYMBOLS) |
d6bc6245 | 9531 | { |
6caf9ef4 TS |
9532 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
9533 | && !nopic_need_relax (ep->X_add_symbol, 1)) | |
9534 | { | |
9535 | relax_start (ep->X_add_symbol); | |
9536 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
9537 | mips_gp_register, BFD_RELOC_GPREL16); | |
9538 | relax_switch (); | |
9539 | } | |
d6bc6245 | 9540 | |
741fe287 | 9541 | if (*used_at == 0 && mips_opts.at) |
d6bc6245 | 9542 | { |
df58fc94 RS |
9543 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
9544 | macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S); | |
67c0d1eb RS |
9545 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
9546 | BFD_RELOC_MIPS_HIGHER); | |
9547 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
df58fc94 | 9548 | macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0); |
67c0d1eb | 9549 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); |
d6bc6245 TS |
9550 | *used_at = 1; |
9551 | } | |
9552 | else | |
9553 | { | |
df58fc94 | 9554 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb RS |
9555 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
9556 | BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 9557 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 9558 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); |
df58fc94 | 9559 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 9560 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); |
d6bc6245 | 9561 | } |
6caf9ef4 TS |
9562 | |
9563 | if (mips_relax.sequence) | |
9564 | relax_end (); | |
d6bc6245 | 9565 | } |
252b5132 RH |
9566 | else |
9567 | { | |
d6bc6245 | 9568 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 9569 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
d6bc6245 | 9570 | { |
4d7206a2 | 9571 | relax_start (ep->X_add_symbol); |
67c0d1eb | 9572 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 9573 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 9574 | relax_switch (); |
d6bc6245 | 9575 | } |
67c0d1eb RS |
9576 | macro_build_lui (ep, reg); |
9577 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
9578 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
9579 | if (mips_relax.sequence) |
9580 | relax_end (); | |
d6bc6245 | 9581 | } |
252b5132 | 9582 | } |
0a44bf69 | 9583 | else if (!mips_big_got) |
252b5132 RH |
9584 | { |
9585 | expressionS ex; | |
9586 | ||
9587 | /* If this is a reference to an external symbol, we want | |
9588 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9589 | Otherwise we want | |
9590 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9591 | nop | |
9592 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
9593 | If there is a constant, it must be added in after. |
9594 | ||
ed6fb7bd | 9595 | If we have NewABI, we want |
f5040a92 AO |
9596 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
9597 | unless we're referencing a global symbol with a non-zero | |
9598 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
9599 | if (HAVE_NEWABI) |
9600 | { | |
f5040a92 AO |
9601 | if (ep->X_add_number) |
9602 | { | |
4d7206a2 | 9603 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 9604 | ep->X_add_number = 0; |
4d7206a2 | 9605 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
9606 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
9607 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
9608 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
9609 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
9610 | ex.X_op = O_constant; | |
67c0d1eb | 9611 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 9612 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 9613 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 9614 | relax_switch (); |
f5040a92 | 9615 | } |
67c0d1eb | 9616 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 9617 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
9618 | if (mips_relax.sequence) |
9619 | relax_end (); | |
ed6fb7bd SC |
9620 | } |
9621 | else | |
9622 | { | |
f5040a92 AO |
9623 | ex.X_add_number = ep->X_add_number; |
9624 | ep->X_add_number = 0; | |
67c0d1eb RS |
9625 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
9626 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 9627 | load_delay_nop (); |
4d7206a2 RS |
9628 | relax_start (ep->X_add_symbol); |
9629 | relax_switch (); | |
67c0d1eb | 9630 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 9631 | BFD_RELOC_LO16); |
4d7206a2 | 9632 | relax_end (); |
ed6fb7bd | 9633 | |
f5040a92 AO |
9634 | if (ex.X_add_number != 0) |
9635 | { | |
9636 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
9637 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
9638 | ex.X_op = O_constant; | |
67c0d1eb | 9639 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 9640 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 9641 | } |
252b5132 RH |
9642 | } |
9643 | } | |
0a44bf69 | 9644 | else if (mips_big_got) |
252b5132 RH |
9645 | { |
9646 | expressionS ex; | |
252b5132 RH |
9647 | |
9648 | /* This is the large GOT case. If this is a reference to an | |
9649 | external symbol, we want | |
9650 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
9651 | addu $reg,$reg,$gp | |
9652 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
9653 | |
9654 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
9655 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
9656 | nop | |
9657 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 9658 | If there is a constant, it must be added in after. |
f5040a92 AO |
9659 | |
9660 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
9661 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
9662 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 9663 | */ |
438c16b8 TS |
9664 | if (HAVE_NEWABI) |
9665 | { | |
4d7206a2 | 9666 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 9667 | ep->X_add_number = 0; |
4d7206a2 | 9668 | relax_start (ep->X_add_symbol); |
df58fc94 | 9669 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
9670 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
9671 | reg, reg, mips_gp_register); | |
9672 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
9673 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
9674 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
9675 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
9676 | else if (ex.X_add_number) | |
9677 | { | |
9678 | ex.X_op = O_constant; | |
67c0d1eb RS |
9679 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
9680 | BFD_RELOC_LO16); | |
f5040a92 AO |
9681 | } |
9682 | ||
9683 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 9684 | relax_switch (); |
67c0d1eb | 9685 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 9686 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
9687 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
9688 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 9689 | relax_end (); |
438c16b8 | 9690 | } |
252b5132 | 9691 | else |
438c16b8 | 9692 | { |
f5040a92 AO |
9693 | ex.X_add_number = ep->X_add_number; |
9694 | ep->X_add_number = 0; | |
4d7206a2 | 9695 | relax_start (ep->X_add_symbol); |
df58fc94 | 9696 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
9697 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
9698 | reg, reg, mips_gp_register); | |
9699 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
9700 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
9701 | relax_switch (); |
9702 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
9703 | { |
9704 | /* We need a nop before loading from $gp. This special | |
9705 | check is required because the lui which starts the main | |
9706 | instruction stream does not refer to $gp, and so will not | |
9707 | insert the nop which may be required. */ | |
67c0d1eb | 9708 | macro_build (NULL, "nop", ""); |
438c16b8 | 9709 | } |
67c0d1eb | 9710 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 9711 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 9712 | load_delay_nop (); |
67c0d1eb | 9713 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 9714 | BFD_RELOC_LO16); |
4d7206a2 | 9715 | relax_end (); |
438c16b8 | 9716 | |
f5040a92 AO |
9717 | if (ex.X_add_number != 0) |
9718 | { | |
9719 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
9720 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
9721 | ex.X_op = O_constant; | |
67c0d1eb RS |
9722 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
9723 | BFD_RELOC_LO16); | |
f5040a92 | 9724 | } |
252b5132 RH |
9725 | } |
9726 | } | |
252b5132 RH |
9727 | else |
9728 | abort (); | |
8fc2e39e | 9729 | |
741fe287 | 9730 | if (!mips_opts.at && *used_at == 1) |
1661c76c | 9731 | as_bad (_("macro used $at after \".set noat\"")); |
252b5132 RH |
9732 | } |
9733 | ||
ea1fb5dc RS |
9734 | /* Move the contents of register SOURCE into register DEST. */ |
9735 | ||
9736 | static void | |
67c0d1eb | 9737 | move_register (int dest, int source) |
ea1fb5dc | 9738 | { |
df58fc94 RS |
9739 | /* Prefer to use a 16-bit microMIPS instruction unless the previous |
9740 | instruction specifically requires a 32-bit one. */ | |
9741 | if (mips_opts.micromips | |
833794fc | 9742 | && !mips_opts.insn32 |
df58fc94 | 9743 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
7951ca42 | 9744 | macro_build (NULL, "move", "mp,mj", dest, source); |
df58fc94 | 9745 | else |
40fc1451 | 9746 | macro_build (NULL, "or", "d,v,t", dest, source, 0); |
ea1fb5dc RS |
9747 | } |
9748 | ||
4d7206a2 | 9749 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
9750 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
9751 | The two alternatives are: | |
4d7206a2 | 9752 | |
33eaf5de | 9753 | Global symbol Local symbol |
4d7206a2 RS |
9754 | ------------- ------------ |
9755 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
9756 | ... ... | |
9757 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
9758 | ||
9759 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
9760 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
9761 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
9762 | |
9763 | static void | |
67c0d1eb | 9764 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
9765 | { |
9766 | expressionS global; | |
9767 | ||
9768 | global = *local; | |
9769 | global.X_add_number = 0; | |
9770 | ||
9771 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
9772 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
9773 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 9774 | relax_switch (); |
67c0d1eb RS |
9775 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
9776 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
9777 | relax_end (); |
9778 | } | |
9779 | ||
9780 | static void | |
67c0d1eb | 9781 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
9782 | { |
9783 | expressionS global; | |
9784 | ||
9785 | global.X_op = O_constant; | |
9786 | global.X_op_symbol = NULL; | |
9787 | global.X_add_symbol = NULL; | |
9788 | global.X_add_number = local->X_add_number; | |
9789 | ||
9790 | relax_start (local->X_add_symbol); | |
67c0d1eb | 9791 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
9792 | dest, dest, BFD_RELOC_LO16); |
9793 | relax_switch (); | |
67c0d1eb | 9794 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
9795 | relax_end (); |
9796 | } | |
9797 | ||
f6a22291 MR |
9798 | static void |
9799 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
9800 | { | |
9801 | expressionS global; | |
9802 | int hold_mips_optimize; | |
9803 | ||
9804 | global.X_op = O_constant; | |
9805 | global.X_op_symbol = NULL; | |
9806 | global.X_add_symbol = NULL; | |
9807 | global.X_add_number = local->X_add_number; | |
9808 | ||
9809 | relax_start (local->X_add_symbol); | |
9810 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
9811 | relax_switch (); | |
9812 | /* Set mips_optimize around the lui instruction to avoid | |
9813 | inserting an unnecessary nop after the lw. */ | |
9814 | hold_mips_optimize = mips_optimize; | |
9815 | mips_optimize = 2; | |
9816 | macro_build_lui (&global, tmp); | |
9817 | mips_optimize = hold_mips_optimize; | |
9818 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
9819 | relax_end (); | |
9820 | ||
9821 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
9822 | } | |
9823 | ||
df58fc94 RS |
9824 | /* Emit a sequence of instructions to emulate a branch likely operation. |
9825 | BR is an ordinary branch corresponding to one to be emulated. BRNEG | |
9826 | is its complementing branch with the original condition negated. | |
9827 | CALL is set if the original branch specified the link operation. | |
9828 | EP, FMT, SREG and TREG specify the usual macro_build() parameters. | |
9829 | ||
9830 | Code like this is produced in the noreorder mode: | |
9831 | ||
9832 | BRNEG <args>, 1f | |
9833 | nop | |
9834 | b <sym> | |
9835 | delay slot (executed only if branch taken) | |
9836 | 1: | |
9837 | ||
9838 | or, if CALL is set: | |
9839 | ||
9840 | BRNEG <args>, 1f | |
9841 | nop | |
9842 | bal <sym> | |
9843 | delay slot (executed only if branch taken) | |
9844 | 1: | |
9845 | ||
9846 | In the reorder mode the delay slot would be filled with a nop anyway, | |
9847 | so code produced is simply: | |
9848 | ||
9849 | BR <args>, <sym> | |
9850 | nop | |
9851 | ||
9852 | This function is used when producing code for the microMIPS ASE that | |
9853 | does not implement branch likely instructions in hardware. */ | |
9854 | ||
9855 | static void | |
9856 | macro_build_branch_likely (const char *br, const char *brneg, | |
9857 | int call, expressionS *ep, const char *fmt, | |
9858 | unsigned int sreg, unsigned int treg) | |
9859 | { | |
9860 | int noreorder = mips_opts.noreorder; | |
9861 | expressionS expr1; | |
9862 | ||
9863 | gas_assert (mips_opts.micromips); | |
9864 | start_noreorder (); | |
9865 | if (noreorder) | |
9866 | { | |
9867 | micromips_label_expr (&expr1); | |
9868 | macro_build (&expr1, brneg, fmt, sreg, treg); | |
9869 | macro_build (NULL, "nop", ""); | |
9870 | macro_build (ep, call ? "bal" : "b", "p"); | |
9871 | ||
9872 | /* Set to true so that append_insn adds a label. */ | |
9873 | emit_branch_likely_macro = TRUE; | |
9874 | } | |
9875 | else | |
9876 | { | |
9877 | macro_build (ep, br, fmt, sreg, treg); | |
9878 | macro_build (NULL, "nop", ""); | |
9879 | } | |
9880 | end_noreorder (); | |
9881 | } | |
9882 | ||
9883 | /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as | |
9884 | the condition code tested. EP specifies the branch target. */ | |
9885 | ||
9886 | static void | |
9887 | macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc) | |
9888 | { | |
9889 | const int call = 0; | |
9890 | const char *brneg; | |
9891 | const char *br; | |
9892 | ||
9893 | switch (type) | |
9894 | { | |
9895 | case M_BC1FL: | |
9896 | br = "bc1f"; | |
9897 | brneg = "bc1t"; | |
9898 | break; | |
9899 | case M_BC1TL: | |
9900 | br = "bc1t"; | |
9901 | brneg = "bc1f"; | |
9902 | break; | |
9903 | case M_BC2FL: | |
9904 | br = "bc2f"; | |
9905 | brneg = "bc2t"; | |
9906 | break; | |
9907 | case M_BC2TL: | |
9908 | br = "bc2t"; | |
9909 | brneg = "bc2f"; | |
9910 | break; | |
9911 | default: | |
9912 | abort (); | |
9913 | } | |
9914 | macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO); | |
9915 | } | |
9916 | ||
9917 | /* Emit a two-argument branch macro specified by TYPE, using SREG as | |
9918 | the register tested. EP specifies the branch target. */ | |
9919 | ||
9920 | static void | |
9921 | macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg) | |
9922 | { | |
9923 | const char *brneg = NULL; | |
9924 | const char *br; | |
9925 | int call = 0; | |
9926 | ||
9927 | switch (type) | |
9928 | { | |
9929 | case M_BGEZ: | |
9930 | br = "bgez"; | |
9931 | break; | |
9932 | case M_BGEZL: | |
9933 | br = mips_opts.micromips ? "bgez" : "bgezl"; | |
9934 | brneg = "bltz"; | |
9935 | break; | |
9936 | case M_BGEZALL: | |
9937 | gas_assert (mips_opts.micromips); | |
833794fc | 9938 | br = mips_opts.insn32 ? "bgezal" : "bgezals"; |
df58fc94 RS |
9939 | brneg = "bltz"; |
9940 | call = 1; | |
9941 | break; | |
9942 | case M_BGTZ: | |
9943 | br = "bgtz"; | |
9944 | break; | |
9945 | case M_BGTZL: | |
9946 | br = mips_opts.micromips ? "bgtz" : "bgtzl"; | |
9947 | brneg = "blez"; | |
9948 | break; | |
9949 | case M_BLEZ: | |
9950 | br = "blez"; | |
9951 | break; | |
9952 | case M_BLEZL: | |
9953 | br = mips_opts.micromips ? "blez" : "blezl"; | |
9954 | brneg = "bgtz"; | |
9955 | break; | |
9956 | case M_BLTZ: | |
9957 | br = "bltz"; | |
9958 | break; | |
9959 | case M_BLTZL: | |
9960 | br = mips_opts.micromips ? "bltz" : "bltzl"; | |
9961 | brneg = "bgez"; | |
9962 | break; | |
9963 | case M_BLTZALL: | |
9964 | gas_assert (mips_opts.micromips); | |
833794fc | 9965 | br = mips_opts.insn32 ? "bltzal" : "bltzals"; |
df58fc94 RS |
9966 | brneg = "bgez"; |
9967 | call = 1; | |
9968 | break; | |
9969 | default: | |
9970 | abort (); | |
9971 | } | |
9972 | if (mips_opts.micromips && brneg) | |
9973 | macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO); | |
9974 | else | |
9975 | macro_build (ep, br, "s,p", sreg); | |
9976 | } | |
9977 | ||
9978 | /* Emit a three-argument branch macro specified by TYPE, using SREG and | |
9979 | TREG as the registers tested. EP specifies the branch target. */ | |
9980 | ||
9981 | static void | |
9982 | macro_build_branch_rsrt (int type, expressionS *ep, | |
9983 | unsigned int sreg, unsigned int treg) | |
9984 | { | |
9985 | const char *brneg = NULL; | |
9986 | const int call = 0; | |
9987 | const char *br; | |
9988 | ||
9989 | switch (type) | |
9990 | { | |
9991 | case M_BEQ: | |
9992 | case M_BEQ_I: | |
9993 | br = "beq"; | |
9994 | break; | |
9995 | case M_BEQL: | |
9996 | case M_BEQL_I: | |
9997 | br = mips_opts.micromips ? "beq" : "beql"; | |
9998 | brneg = "bne"; | |
9999 | break; | |
10000 | case M_BNE: | |
10001 | case M_BNE_I: | |
10002 | br = "bne"; | |
10003 | break; | |
10004 | case M_BNEL: | |
10005 | case M_BNEL_I: | |
10006 | br = mips_opts.micromips ? "bne" : "bnel"; | |
10007 | brneg = "beq"; | |
10008 | break; | |
10009 | default: | |
10010 | abort (); | |
10011 | } | |
10012 | if (mips_opts.micromips && brneg) | |
10013 | macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg); | |
10014 | else | |
10015 | macro_build (ep, br, "s,t,p", sreg, treg); | |
10016 | } | |
10017 | ||
f2ae14a1 RS |
10018 | /* Return the high part that should be loaded in order to make the low |
10019 | part of VALUE accessible using an offset of OFFBITS bits. */ | |
10020 | ||
10021 | static offsetT | |
10022 | offset_high_part (offsetT value, unsigned int offbits) | |
10023 | { | |
10024 | offsetT bias; | |
10025 | addressT low_mask; | |
10026 | ||
10027 | if (offbits == 0) | |
10028 | return value; | |
10029 | bias = 1 << (offbits - 1); | |
10030 | low_mask = bias * 2 - 1; | |
10031 | return (value + bias) & ~low_mask; | |
10032 | } | |
10033 | ||
10034 | /* Return true if the value stored in offset_expr and offset_reloc | |
10035 | fits into a signed offset of OFFBITS bits. RANGE is the maximum | |
10036 | amount that the caller wants to add without inducing overflow | |
10037 | and ALIGN is the known alignment of the value in bytes. */ | |
10038 | ||
10039 | static bfd_boolean | |
10040 | small_offset_p (unsigned int range, unsigned int align, unsigned int offbits) | |
10041 | { | |
10042 | if (offbits == 16) | |
10043 | { | |
10044 | /* Accept any relocation operator if overflow isn't a concern. */ | |
10045 | if (range < align && *offset_reloc != BFD_RELOC_UNUSED) | |
10046 | return TRUE; | |
10047 | ||
10048 | /* These relocations are guaranteed not to overflow in correct links. */ | |
10049 | if (*offset_reloc == BFD_RELOC_MIPS_LITERAL | |
10050 | || gprel16_reloc_p (*offset_reloc)) | |
10051 | return TRUE; | |
10052 | } | |
10053 | if (offset_expr.X_op == O_constant | |
10054 | && offset_high_part (offset_expr.X_add_number, offbits) == 0 | |
10055 | && offset_high_part (offset_expr.X_add_number + range, offbits) == 0) | |
10056 | return TRUE; | |
10057 | return FALSE; | |
10058 | } | |
10059 | ||
252b5132 RH |
10060 | /* |
10061 | * Build macros | |
10062 | * This routine implements the seemingly endless macro or synthesized | |
10063 | * instructions and addressing modes in the mips assembly language. Many | |
10064 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 10065 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
10066 | * this verbose method. Others are not simple macros but are more like |
10067 | * optimizing code generation. | |
10068 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 10069 | * consecutively that would load AT with the upper half of the same address. |
2b0f3761 | 10070 | * The ensuing load upper instructions are omitted. This implies some kind |
252b5132 RH |
10071 | * of global optimization. We currently only optimize within a single macro. |
10072 | * For many of the load and store macros if the address is specified as a | |
10073 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
10074 | * first load register 'at' with zero and use it as the base register. The | |
10075 | * mips assembler simply uses register $zero. Just one tiny optimization | |
10076 | * we're missing. | |
10077 | */ | |
10078 | static void | |
833794fc | 10079 | macro (struct mips_cl_insn *ip, char *str) |
252b5132 | 10080 | { |
c0ebe874 RS |
10081 | const struct mips_operand_array *operands; |
10082 | unsigned int breg, i; | |
741fe287 | 10083 | unsigned int tempreg; |
252b5132 | 10084 | int mask; |
43841e91 | 10085 | int used_at = 0; |
df58fc94 | 10086 | expressionS label_expr; |
252b5132 | 10087 | expressionS expr1; |
df58fc94 | 10088 | expressionS *ep; |
252b5132 RH |
10089 | const char *s; |
10090 | const char *s2; | |
10091 | const char *fmt; | |
10092 | int likely = 0; | |
252b5132 | 10093 | int coproc = 0; |
7f3c4072 | 10094 | int offbits = 16; |
1abe91b1 | 10095 | int call = 0; |
df58fc94 RS |
10096 | int jals = 0; |
10097 | int dbl = 0; | |
10098 | int imm = 0; | |
10099 | int ust = 0; | |
10100 | int lp = 0; | |
f2ae14a1 | 10101 | bfd_boolean large_offset; |
252b5132 | 10102 | int off; |
252b5132 | 10103 | int hold_mips_optimize; |
f2ae14a1 | 10104 | unsigned int align; |
c0ebe874 | 10105 | unsigned int op[MAX_OPERANDS]; |
252b5132 | 10106 | |
9c2799c2 | 10107 | gas_assert (! mips_opts.mips16); |
252b5132 | 10108 | |
c0ebe874 RS |
10109 | operands = insn_operands (ip); |
10110 | for (i = 0; i < MAX_OPERANDS; i++) | |
10111 | if (operands->operand[i]) | |
10112 | op[i] = insn_extract_operand (ip, operands->operand[i]); | |
10113 | else | |
10114 | op[i] = -1; | |
10115 | ||
252b5132 RH |
10116 | mask = ip->insn_mo->mask; |
10117 | ||
df58fc94 RS |
10118 | label_expr.X_op = O_constant; |
10119 | label_expr.X_op_symbol = NULL; | |
10120 | label_expr.X_add_symbol = NULL; | |
10121 | label_expr.X_add_number = 0; | |
10122 | ||
252b5132 RH |
10123 | expr1.X_op = O_constant; |
10124 | expr1.X_op_symbol = NULL; | |
10125 | expr1.X_add_symbol = NULL; | |
10126 | expr1.X_add_number = 1; | |
f2ae14a1 | 10127 | align = 1; |
252b5132 RH |
10128 | |
10129 | switch (mask) | |
10130 | { | |
10131 | case M_DABS: | |
10132 | dbl = 1; | |
1a0670f3 | 10133 | /* Fall through. */ |
252b5132 | 10134 | case M_ABS: |
df58fc94 RS |
10135 | /* bgez $a0,1f |
10136 | move v0,$a0 | |
10137 | sub v0,$zero,$a0 | |
10138 | 1: | |
10139 | */ | |
252b5132 | 10140 | |
7d10b47d | 10141 | start_noreorder (); |
252b5132 | 10142 | |
df58fc94 RS |
10143 | if (mips_opts.micromips) |
10144 | micromips_label_expr (&label_expr); | |
10145 | else | |
10146 | label_expr.X_add_number = 8; | |
c0ebe874 RS |
10147 | macro_build (&label_expr, "bgez", "s,p", op[1]); |
10148 | if (op[0] == op[1]) | |
a605d2b3 | 10149 | macro_build (NULL, "nop", ""); |
252b5132 | 10150 | else |
c0ebe874 RS |
10151 | move_register (op[0], op[1]); |
10152 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", op[0], 0, op[1]); | |
df58fc94 RS |
10153 | if (mips_opts.micromips) |
10154 | micromips_add_label (); | |
252b5132 | 10155 | |
7d10b47d | 10156 | end_noreorder (); |
8fc2e39e | 10157 | break; |
252b5132 RH |
10158 | |
10159 | case M_ADD_I: | |
10160 | s = "addi"; | |
10161 | s2 = "add"; | |
10162 | goto do_addi; | |
10163 | case M_ADDU_I: | |
10164 | s = "addiu"; | |
10165 | s2 = "addu"; | |
10166 | goto do_addi; | |
10167 | case M_DADD_I: | |
10168 | dbl = 1; | |
10169 | s = "daddi"; | |
10170 | s2 = "dadd"; | |
df58fc94 RS |
10171 | if (!mips_opts.micromips) |
10172 | goto do_addi; | |
b0e6f033 | 10173 | if (imm_expr.X_add_number >= -0x200 |
df58fc94 RS |
10174 | && imm_expr.X_add_number < 0x200) |
10175 | { | |
b0e6f033 RS |
10176 | macro_build (NULL, s, "t,r,.", op[0], op[1], |
10177 | (int) imm_expr.X_add_number); | |
df58fc94 RS |
10178 | break; |
10179 | } | |
10180 | goto do_addi_i; | |
252b5132 RH |
10181 | case M_DADDU_I: |
10182 | dbl = 1; | |
10183 | s = "daddiu"; | |
10184 | s2 = "daddu"; | |
10185 | do_addi: | |
b0e6f033 | 10186 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 RH |
10187 | && imm_expr.X_add_number < 0x8000) |
10188 | { | |
c0ebe874 | 10189 | macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
8fc2e39e | 10190 | break; |
252b5132 | 10191 | } |
df58fc94 | 10192 | do_addi_i: |
8fc2e39e | 10193 | used_at = 1; |
67c0d1eb | 10194 | load_register (AT, &imm_expr, dbl); |
c0ebe874 | 10195 | macro_build (NULL, s2, "d,v,t", op[0], op[1], AT); |
252b5132 RH |
10196 | break; |
10197 | ||
10198 | case M_AND_I: | |
10199 | s = "andi"; | |
10200 | s2 = "and"; | |
10201 | goto do_bit; | |
10202 | case M_OR_I: | |
10203 | s = "ori"; | |
10204 | s2 = "or"; | |
10205 | goto do_bit; | |
10206 | case M_NOR_I: | |
10207 | s = ""; | |
10208 | s2 = "nor"; | |
10209 | goto do_bit; | |
10210 | case M_XOR_I: | |
10211 | s = "xori"; | |
10212 | s2 = "xor"; | |
10213 | do_bit: | |
b0e6f033 | 10214 | if (imm_expr.X_add_number >= 0 |
252b5132 RH |
10215 | && imm_expr.X_add_number < 0x10000) |
10216 | { | |
10217 | if (mask != M_NOR_I) | |
c0ebe874 | 10218 | macro_build (&imm_expr, s, "t,r,i", op[0], op[1], BFD_RELOC_LO16); |
252b5132 RH |
10219 | else |
10220 | { | |
67c0d1eb | 10221 | macro_build (&imm_expr, "ori", "t,r,i", |
c0ebe874 RS |
10222 | op[0], op[1], BFD_RELOC_LO16); |
10223 | macro_build (NULL, "nor", "d,v,t", op[0], op[0], 0); | |
252b5132 | 10224 | } |
8fc2e39e | 10225 | break; |
252b5132 RH |
10226 | } |
10227 | ||
8fc2e39e | 10228 | used_at = 1; |
bad1aba3 | 10229 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 10230 | macro_build (NULL, s2, "d,v,t", op[0], op[1], AT); |
252b5132 RH |
10231 | break; |
10232 | ||
8b082fb1 TS |
10233 | case M_BALIGN: |
10234 | switch (imm_expr.X_add_number) | |
10235 | { | |
10236 | case 0: | |
10237 | macro_build (NULL, "nop", ""); | |
10238 | break; | |
10239 | case 2: | |
c0ebe874 | 10240 | macro_build (NULL, "packrl.ph", "d,s,t", op[0], op[0], op[1]); |
8b082fb1 | 10241 | break; |
03f66e8a MR |
10242 | case 1: |
10243 | case 3: | |
c0ebe874 | 10244 | macro_build (NULL, "balign", "t,s,2", op[0], op[1], |
90ecf173 | 10245 | (int) imm_expr.X_add_number); |
8b082fb1 | 10246 | break; |
03f66e8a MR |
10247 | default: |
10248 | as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"), | |
10249 | (unsigned long) imm_expr.X_add_number); | |
10250 | break; | |
8b082fb1 TS |
10251 | } |
10252 | break; | |
10253 | ||
df58fc94 RS |
10254 | case M_BC1FL: |
10255 | case M_BC1TL: | |
10256 | case M_BC2FL: | |
10257 | case M_BC2TL: | |
10258 | gas_assert (mips_opts.micromips); | |
10259 | macro_build_branch_ccl (mask, &offset_expr, | |
10260 | EXTRACT_OPERAND (1, BCC, *ip)); | |
10261 | break; | |
10262 | ||
252b5132 | 10263 | case M_BEQ_I: |
252b5132 | 10264 | case M_BEQL_I: |
252b5132 | 10265 | case M_BNE_I: |
252b5132 | 10266 | case M_BNEL_I: |
b0e6f033 | 10267 | if (imm_expr.X_add_number == 0) |
c0ebe874 | 10268 | op[1] = 0; |
df58fc94 | 10269 | else |
252b5132 | 10270 | { |
c0ebe874 | 10271 | op[1] = AT; |
df58fc94 | 10272 | used_at = 1; |
bad1aba3 | 10273 | load_register (op[1], &imm_expr, GPR_SIZE == 64); |
252b5132 | 10274 | } |
df58fc94 RS |
10275 | /* Fall through. */ |
10276 | case M_BEQL: | |
10277 | case M_BNEL: | |
c0ebe874 | 10278 | macro_build_branch_rsrt (mask, &offset_expr, op[0], op[1]); |
252b5132 RH |
10279 | break; |
10280 | ||
10281 | case M_BGEL: | |
10282 | likely = 1; | |
1a0670f3 | 10283 | /* Fall through. */ |
252b5132 | 10284 | case M_BGE: |
c0ebe874 RS |
10285 | if (op[1] == 0) |
10286 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[0]); | |
10287 | else if (op[0] == 0) | |
10288 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[1]); | |
df58fc94 | 10289 | else |
252b5132 | 10290 | { |
df58fc94 | 10291 | used_at = 1; |
c0ebe874 | 10292 | macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]); |
df58fc94 RS |
10293 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10294 | &offset_expr, AT, ZERO); | |
252b5132 | 10295 | } |
df58fc94 RS |
10296 | break; |
10297 | ||
10298 | case M_BGEZL: | |
10299 | case M_BGEZALL: | |
10300 | case M_BGTZL: | |
10301 | case M_BLEZL: | |
10302 | case M_BLTZL: | |
10303 | case M_BLTZALL: | |
c0ebe874 | 10304 | macro_build_branch_rs (mask, &offset_expr, op[0]); |
252b5132 RH |
10305 | break; |
10306 | ||
10307 | case M_BGTL_I: | |
10308 | likely = 1; | |
1a0670f3 | 10309 | /* Fall through. */ |
252b5132 | 10310 | case M_BGT_I: |
90ecf173 | 10311 | /* Check for > max integer. */ |
b0e6f033 | 10312 | if (imm_expr.X_add_number >= GPR_SMAX) |
252b5132 RH |
10313 | { |
10314 | do_false: | |
90ecf173 | 10315 | /* Result is always false. */ |
252b5132 | 10316 | if (! likely) |
a605d2b3 | 10317 | macro_build (NULL, "nop", ""); |
252b5132 | 10318 | else |
df58fc94 | 10319 | macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO); |
8fc2e39e | 10320 | break; |
252b5132 | 10321 | } |
f9419b05 | 10322 | ++imm_expr.X_add_number; |
252b5132 RH |
10323 | /* FALLTHROUGH */ |
10324 | case M_BGE_I: | |
10325 | case M_BGEL_I: | |
10326 | if (mask == M_BGEL_I) | |
10327 | likely = 1; | |
b0e6f033 | 10328 | if (imm_expr.X_add_number == 0) |
252b5132 | 10329 | { |
df58fc94 | 10330 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, |
c0ebe874 | 10331 | &offset_expr, op[0]); |
8fc2e39e | 10332 | break; |
252b5132 | 10333 | } |
b0e6f033 | 10334 | if (imm_expr.X_add_number == 1) |
252b5132 | 10335 | { |
df58fc94 | 10336 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, |
c0ebe874 | 10337 | &offset_expr, op[0]); |
8fc2e39e | 10338 | break; |
252b5132 | 10339 | } |
b0e6f033 | 10340 | if (imm_expr.X_add_number <= GPR_SMIN) |
252b5132 RH |
10341 | { |
10342 | do_true: | |
10343 | /* result is always true */ | |
1661c76c | 10344 | as_warn (_("branch %s is always true"), ip->insn_mo->name); |
67c0d1eb | 10345 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 10346 | break; |
252b5132 | 10347 | } |
8fc2e39e | 10348 | used_at = 1; |
c0ebe874 | 10349 | set_at (op[0], 0); |
df58fc94 RS |
10350 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10351 | &offset_expr, AT, ZERO); | |
252b5132 RH |
10352 | break; |
10353 | ||
10354 | case M_BGEUL: | |
10355 | likely = 1; | |
1a0670f3 | 10356 | /* Fall through. */ |
252b5132 | 10357 | case M_BGEU: |
c0ebe874 | 10358 | if (op[1] == 0) |
252b5132 | 10359 | goto do_true; |
c0ebe874 | 10360 | else if (op[0] == 0) |
df58fc94 | 10361 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
c0ebe874 | 10362 | &offset_expr, ZERO, op[1]); |
df58fc94 | 10363 | else |
252b5132 | 10364 | { |
df58fc94 | 10365 | used_at = 1; |
c0ebe874 | 10366 | macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]); |
df58fc94 RS |
10367 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10368 | &offset_expr, AT, ZERO); | |
252b5132 | 10369 | } |
252b5132 RH |
10370 | break; |
10371 | ||
10372 | case M_BGTUL_I: | |
10373 | likely = 1; | |
1a0670f3 | 10374 | /* Fall through. */ |
252b5132 | 10375 | case M_BGTU_I: |
c0ebe874 | 10376 | if (op[0] == 0 |
bad1aba3 | 10377 | || (GPR_SIZE == 32 |
f01dc953 | 10378 | && imm_expr.X_add_number == -1)) |
252b5132 | 10379 | goto do_false; |
f9419b05 | 10380 | ++imm_expr.X_add_number; |
252b5132 RH |
10381 | /* FALLTHROUGH */ |
10382 | case M_BGEU_I: | |
10383 | case M_BGEUL_I: | |
10384 | if (mask == M_BGEUL_I) | |
10385 | likely = 1; | |
b0e6f033 | 10386 | if (imm_expr.X_add_number == 0) |
252b5132 | 10387 | goto do_true; |
b0e6f033 | 10388 | else if (imm_expr.X_add_number == 1) |
df58fc94 | 10389 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
c0ebe874 | 10390 | &offset_expr, op[0], ZERO); |
df58fc94 | 10391 | else |
252b5132 | 10392 | { |
df58fc94 | 10393 | used_at = 1; |
c0ebe874 | 10394 | set_at (op[0], 1); |
df58fc94 RS |
10395 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10396 | &offset_expr, AT, ZERO); | |
252b5132 | 10397 | } |
252b5132 RH |
10398 | break; |
10399 | ||
10400 | case M_BGTL: | |
10401 | likely = 1; | |
1a0670f3 | 10402 | /* Fall through. */ |
252b5132 | 10403 | case M_BGT: |
c0ebe874 RS |
10404 | if (op[1] == 0) |
10405 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[0]); | |
10406 | else if (op[0] == 0) | |
10407 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[1]); | |
df58fc94 | 10408 | else |
252b5132 | 10409 | { |
df58fc94 | 10410 | used_at = 1; |
c0ebe874 | 10411 | macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]); |
df58fc94 RS |
10412 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10413 | &offset_expr, AT, ZERO); | |
252b5132 | 10414 | } |
252b5132 RH |
10415 | break; |
10416 | ||
10417 | case M_BGTUL: | |
10418 | likely = 1; | |
1a0670f3 | 10419 | /* Fall through. */ |
252b5132 | 10420 | case M_BGTU: |
c0ebe874 | 10421 | if (op[1] == 0) |
df58fc94 | 10422 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
c0ebe874 RS |
10423 | &offset_expr, op[0], ZERO); |
10424 | else if (op[0] == 0) | |
df58fc94 RS |
10425 | goto do_false; |
10426 | else | |
252b5132 | 10427 | { |
df58fc94 | 10428 | used_at = 1; |
c0ebe874 | 10429 | macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]); |
df58fc94 RS |
10430 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10431 | &offset_expr, AT, ZERO); | |
252b5132 | 10432 | } |
252b5132 RH |
10433 | break; |
10434 | ||
10435 | case M_BLEL: | |
10436 | likely = 1; | |
1a0670f3 | 10437 | /* Fall through. */ |
252b5132 | 10438 | case M_BLE: |
c0ebe874 RS |
10439 | if (op[1] == 0) |
10440 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]); | |
10441 | else if (op[0] == 0) | |
10442 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[1]); | |
df58fc94 | 10443 | else |
252b5132 | 10444 | { |
df58fc94 | 10445 | used_at = 1; |
c0ebe874 | 10446 | macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]); |
df58fc94 RS |
10447 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10448 | &offset_expr, AT, ZERO); | |
252b5132 | 10449 | } |
252b5132 RH |
10450 | break; |
10451 | ||
10452 | case M_BLEL_I: | |
10453 | likely = 1; | |
1a0670f3 | 10454 | /* Fall through. */ |
252b5132 | 10455 | case M_BLE_I: |
b0e6f033 | 10456 | if (imm_expr.X_add_number >= GPR_SMAX) |
252b5132 | 10457 | goto do_true; |
f9419b05 | 10458 | ++imm_expr.X_add_number; |
252b5132 RH |
10459 | /* FALLTHROUGH */ |
10460 | case M_BLT_I: | |
10461 | case M_BLTL_I: | |
10462 | if (mask == M_BLTL_I) | |
10463 | likely = 1; | |
b0e6f033 | 10464 | if (imm_expr.X_add_number == 0) |
c0ebe874 | 10465 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]); |
b0e6f033 | 10466 | else if (imm_expr.X_add_number == 1) |
c0ebe874 | 10467 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]); |
df58fc94 | 10468 | else |
252b5132 | 10469 | { |
df58fc94 | 10470 | used_at = 1; |
c0ebe874 | 10471 | set_at (op[0], 0); |
df58fc94 RS |
10472 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10473 | &offset_expr, AT, ZERO); | |
252b5132 | 10474 | } |
252b5132 RH |
10475 | break; |
10476 | ||
10477 | case M_BLEUL: | |
10478 | likely = 1; | |
1a0670f3 | 10479 | /* Fall through. */ |
252b5132 | 10480 | case M_BLEU: |
c0ebe874 | 10481 | if (op[1] == 0) |
df58fc94 | 10482 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
c0ebe874 RS |
10483 | &offset_expr, op[0], ZERO); |
10484 | else if (op[0] == 0) | |
df58fc94 RS |
10485 | goto do_true; |
10486 | else | |
252b5132 | 10487 | { |
df58fc94 | 10488 | used_at = 1; |
c0ebe874 | 10489 | macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]); |
df58fc94 RS |
10490 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10491 | &offset_expr, AT, ZERO); | |
252b5132 | 10492 | } |
252b5132 RH |
10493 | break; |
10494 | ||
10495 | case M_BLEUL_I: | |
10496 | likely = 1; | |
1a0670f3 | 10497 | /* Fall through. */ |
252b5132 | 10498 | case M_BLEU_I: |
c0ebe874 | 10499 | if (op[0] == 0 |
bad1aba3 | 10500 | || (GPR_SIZE == 32 |
f01dc953 | 10501 | && imm_expr.X_add_number == -1)) |
252b5132 | 10502 | goto do_true; |
f9419b05 | 10503 | ++imm_expr.X_add_number; |
252b5132 RH |
10504 | /* FALLTHROUGH */ |
10505 | case M_BLTU_I: | |
10506 | case M_BLTUL_I: | |
10507 | if (mask == M_BLTUL_I) | |
10508 | likely = 1; | |
b0e6f033 | 10509 | if (imm_expr.X_add_number == 0) |
252b5132 | 10510 | goto do_false; |
b0e6f033 | 10511 | else if (imm_expr.X_add_number == 1) |
df58fc94 | 10512 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
c0ebe874 | 10513 | &offset_expr, op[0], ZERO); |
df58fc94 | 10514 | else |
252b5132 | 10515 | { |
df58fc94 | 10516 | used_at = 1; |
c0ebe874 | 10517 | set_at (op[0], 1); |
df58fc94 RS |
10518 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10519 | &offset_expr, AT, ZERO); | |
252b5132 | 10520 | } |
252b5132 RH |
10521 | break; |
10522 | ||
10523 | case M_BLTL: | |
10524 | likely = 1; | |
1a0670f3 | 10525 | /* Fall through. */ |
252b5132 | 10526 | case M_BLT: |
c0ebe874 RS |
10527 | if (op[1] == 0) |
10528 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]); | |
10529 | else if (op[0] == 0) | |
10530 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[1]); | |
df58fc94 | 10531 | else |
252b5132 | 10532 | { |
df58fc94 | 10533 | used_at = 1; |
c0ebe874 | 10534 | macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]); |
df58fc94 RS |
10535 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10536 | &offset_expr, AT, ZERO); | |
252b5132 | 10537 | } |
252b5132 RH |
10538 | break; |
10539 | ||
10540 | case M_BLTUL: | |
10541 | likely = 1; | |
1a0670f3 | 10542 | /* Fall through. */ |
252b5132 | 10543 | case M_BLTU: |
c0ebe874 | 10544 | if (op[1] == 0) |
252b5132 | 10545 | goto do_false; |
c0ebe874 | 10546 | else if (op[0] == 0) |
df58fc94 | 10547 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
c0ebe874 | 10548 | &offset_expr, ZERO, op[1]); |
df58fc94 | 10549 | else |
252b5132 | 10550 | { |
df58fc94 | 10551 | used_at = 1; |
c0ebe874 | 10552 | macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]); |
df58fc94 RS |
10553 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10554 | &offset_expr, AT, ZERO); | |
252b5132 | 10555 | } |
252b5132 RH |
10556 | break; |
10557 | ||
10558 | case M_DDIV_3: | |
10559 | dbl = 1; | |
1a0670f3 | 10560 | /* Fall through. */ |
252b5132 RH |
10561 | case M_DIV_3: |
10562 | s = "mflo"; | |
10563 | goto do_div3; | |
10564 | case M_DREM_3: | |
10565 | dbl = 1; | |
1a0670f3 | 10566 | /* Fall through. */ |
252b5132 RH |
10567 | case M_REM_3: |
10568 | s = "mfhi"; | |
10569 | do_div3: | |
c0ebe874 | 10570 | if (op[2] == 0) |
252b5132 | 10571 | { |
1661c76c | 10572 | as_warn (_("divide by zero")); |
252b5132 | 10573 | if (mips_trap) |
df58fc94 | 10574 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 10575 | else |
df58fc94 | 10576 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 10577 | break; |
252b5132 RH |
10578 | } |
10579 | ||
7d10b47d | 10580 | start_noreorder (); |
252b5132 RH |
10581 | if (mips_trap) |
10582 | { | |
c0ebe874 RS |
10583 | macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7); |
10584 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]); | |
252b5132 RH |
10585 | } |
10586 | else | |
10587 | { | |
df58fc94 RS |
10588 | if (mips_opts.micromips) |
10589 | micromips_label_expr (&label_expr); | |
10590 | else | |
10591 | label_expr.X_add_number = 8; | |
c0ebe874 RS |
10592 | macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO); |
10593 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]); | |
df58fc94 RS |
10594 | macro_build (NULL, "break", BRK_FMT, 7); |
10595 | if (mips_opts.micromips) | |
10596 | micromips_add_label (); | |
252b5132 RH |
10597 | } |
10598 | expr1.X_add_number = -1; | |
8fc2e39e | 10599 | used_at = 1; |
f6a22291 | 10600 | load_register (AT, &expr1, dbl); |
df58fc94 RS |
10601 | if (mips_opts.micromips) |
10602 | micromips_label_expr (&label_expr); | |
10603 | else | |
10604 | label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); | |
c0ebe874 | 10605 | macro_build (&label_expr, "bne", "s,t,p", op[2], AT); |
252b5132 RH |
10606 | if (dbl) |
10607 | { | |
10608 | expr1.X_add_number = 1; | |
f6a22291 | 10609 | load_register (AT, &expr1, dbl); |
df58fc94 | 10610 | macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31); |
252b5132 RH |
10611 | } |
10612 | else | |
10613 | { | |
10614 | expr1.X_add_number = 0x80000000; | |
df58fc94 | 10615 | macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16); |
252b5132 RH |
10616 | } |
10617 | if (mips_trap) | |
10618 | { | |
c0ebe874 | 10619 | macro_build (NULL, "teq", TRAP_FMT, op[1], AT, 6); |
252b5132 RH |
10620 | /* We want to close the noreorder block as soon as possible, so |
10621 | that later insns are available for delay slot filling. */ | |
7d10b47d | 10622 | end_noreorder (); |
252b5132 RH |
10623 | } |
10624 | else | |
10625 | { | |
df58fc94 RS |
10626 | if (mips_opts.micromips) |
10627 | micromips_label_expr (&label_expr); | |
10628 | else | |
10629 | label_expr.X_add_number = 8; | |
c0ebe874 | 10630 | macro_build (&label_expr, "bne", "s,t,p", op[1], AT); |
a605d2b3 | 10631 | macro_build (NULL, "nop", ""); |
252b5132 RH |
10632 | |
10633 | /* We want to close the noreorder block as soon as possible, so | |
10634 | that later insns are available for delay slot filling. */ | |
7d10b47d | 10635 | end_noreorder (); |
252b5132 | 10636 | |
df58fc94 | 10637 | macro_build (NULL, "break", BRK_FMT, 6); |
252b5132 | 10638 | } |
df58fc94 RS |
10639 | if (mips_opts.micromips) |
10640 | micromips_add_label (); | |
c0ebe874 | 10641 | macro_build (NULL, s, MFHL_FMT, op[0]); |
252b5132 RH |
10642 | break; |
10643 | ||
10644 | case M_DIV_3I: | |
10645 | s = "div"; | |
10646 | s2 = "mflo"; | |
10647 | goto do_divi; | |
10648 | case M_DIVU_3I: | |
10649 | s = "divu"; | |
10650 | s2 = "mflo"; | |
10651 | goto do_divi; | |
10652 | case M_REM_3I: | |
10653 | s = "div"; | |
10654 | s2 = "mfhi"; | |
10655 | goto do_divi; | |
10656 | case M_REMU_3I: | |
10657 | s = "divu"; | |
10658 | s2 = "mfhi"; | |
10659 | goto do_divi; | |
10660 | case M_DDIV_3I: | |
10661 | dbl = 1; | |
10662 | s = "ddiv"; | |
10663 | s2 = "mflo"; | |
10664 | goto do_divi; | |
10665 | case M_DDIVU_3I: | |
10666 | dbl = 1; | |
10667 | s = "ddivu"; | |
10668 | s2 = "mflo"; | |
10669 | goto do_divi; | |
10670 | case M_DREM_3I: | |
10671 | dbl = 1; | |
10672 | s = "ddiv"; | |
10673 | s2 = "mfhi"; | |
10674 | goto do_divi; | |
10675 | case M_DREMU_3I: | |
10676 | dbl = 1; | |
10677 | s = "ddivu"; | |
10678 | s2 = "mfhi"; | |
10679 | do_divi: | |
b0e6f033 | 10680 | if (imm_expr.X_add_number == 0) |
252b5132 | 10681 | { |
1661c76c | 10682 | as_warn (_("divide by zero")); |
252b5132 | 10683 | if (mips_trap) |
df58fc94 | 10684 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 10685 | else |
df58fc94 | 10686 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 10687 | break; |
252b5132 | 10688 | } |
b0e6f033 | 10689 | if (imm_expr.X_add_number == 1) |
252b5132 RH |
10690 | { |
10691 | if (strcmp (s2, "mflo") == 0) | |
c0ebe874 | 10692 | move_register (op[0], op[1]); |
252b5132 | 10693 | else |
c0ebe874 | 10694 | move_register (op[0], ZERO); |
8fc2e39e | 10695 | break; |
252b5132 | 10696 | } |
b0e6f033 | 10697 | if (imm_expr.X_add_number == -1 && s[strlen (s) - 1] != 'u') |
252b5132 RH |
10698 | { |
10699 | if (strcmp (s2, "mflo") == 0) | |
c0ebe874 | 10700 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", op[0], op[1]); |
252b5132 | 10701 | else |
c0ebe874 | 10702 | move_register (op[0], ZERO); |
8fc2e39e | 10703 | break; |
252b5132 RH |
10704 | } |
10705 | ||
8fc2e39e | 10706 | used_at = 1; |
67c0d1eb | 10707 | load_register (AT, &imm_expr, dbl); |
c0ebe874 RS |
10708 | macro_build (NULL, s, "z,s,t", op[1], AT); |
10709 | macro_build (NULL, s2, MFHL_FMT, op[0]); | |
252b5132 RH |
10710 | break; |
10711 | ||
10712 | case M_DIVU_3: | |
10713 | s = "divu"; | |
10714 | s2 = "mflo"; | |
10715 | goto do_divu3; | |
10716 | case M_REMU_3: | |
10717 | s = "divu"; | |
10718 | s2 = "mfhi"; | |
10719 | goto do_divu3; | |
10720 | case M_DDIVU_3: | |
10721 | s = "ddivu"; | |
10722 | s2 = "mflo"; | |
10723 | goto do_divu3; | |
10724 | case M_DREMU_3: | |
10725 | s = "ddivu"; | |
10726 | s2 = "mfhi"; | |
10727 | do_divu3: | |
7d10b47d | 10728 | start_noreorder (); |
252b5132 RH |
10729 | if (mips_trap) |
10730 | { | |
c0ebe874 RS |
10731 | macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7); |
10732 | macro_build (NULL, s, "z,s,t", op[1], op[2]); | |
252b5132 RH |
10733 | /* We want to close the noreorder block as soon as possible, so |
10734 | that later insns are available for delay slot filling. */ | |
7d10b47d | 10735 | end_noreorder (); |
252b5132 RH |
10736 | } |
10737 | else | |
10738 | { | |
df58fc94 RS |
10739 | if (mips_opts.micromips) |
10740 | micromips_label_expr (&label_expr); | |
10741 | else | |
10742 | label_expr.X_add_number = 8; | |
c0ebe874 RS |
10743 | macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO); |
10744 | macro_build (NULL, s, "z,s,t", op[1], op[2]); | |
252b5132 RH |
10745 | |
10746 | /* We want to close the noreorder block as soon as possible, so | |
10747 | that later insns are available for delay slot filling. */ | |
7d10b47d | 10748 | end_noreorder (); |
df58fc94 RS |
10749 | macro_build (NULL, "break", BRK_FMT, 7); |
10750 | if (mips_opts.micromips) | |
10751 | micromips_add_label (); | |
252b5132 | 10752 | } |
c0ebe874 | 10753 | macro_build (NULL, s2, MFHL_FMT, op[0]); |
8fc2e39e | 10754 | break; |
252b5132 | 10755 | |
1abe91b1 MR |
10756 | case M_DLCA_AB: |
10757 | dbl = 1; | |
1a0670f3 | 10758 | /* Fall through. */ |
1abe91b1 MR |
10759 | case M_LCA_AB: |
10760 | call = 1; | |
10761 | goto do_la; | |
252b5132 RH |
10762 | case M_DLA_AB: |
10763 | dbl = 1; | |
1a0670f3 | 10764 | /* Fall through. */ |
252b5132 | 10765 | case M_LA_AB: |
1abe91b1 | 10766 | do_la: |
252b5132 RH |
10767 | /* Load the address of a symbol into a register. If breg is not |
10768 | zero, we then add a base register to it. */ | |
10769 | ||
c0ebe874 | 10770 | breg = op[2]; |
bad1aba3 | 10771 | if (dbl && GPR_SIZE == 32) |
ece794d9 MF |
10772 | as_warn (_("dla used to load 32-bit register; recommend using la " |
10773 | "instead")); | |
3bec30a8 | 10774 | |
90ecf173 | 10775 | if (!dbl && HAVE_64BIT_OBJECTS) |
ece794d9 MF |
10776 | as_warn (_("la used to load 64-bit address; recommend using dla " |
10777 | "instead")); | |
3bec30a8 | 10778 | |
f2ae14a1 | 10779 | if (small_offset_p (0, align, 16)) |
0c11417f | 10780 | { |
c0ebe874 | 10781 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", op[0], breg, |
f2ae14a1 | 10782 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]); |
8fc2e39e | 10783 | break; |
0c11417f MR |
10784 | } |
10785 | ||
c0ebe874 | 10786 | if (mips_opts.at && (op[0] == breg)) |
afdbd6d0 CD |
10787 | { |
10788 | tempreg = AT; | |
10789 | used_at = 1; | |
10790 | } | |
10791 | else | |
c0ebe874 | 10792 | tempreg = op[0]; |
afdbd6d0 | 10793 | |
252b5132 RH |
10794 | if (offset_expr.X_op != O_symbol |
10795 | && offset_expr.X_op != O_constant) | |
10796 | { | |
1661c76c | 10797 | as_bad (_("expression too complex")); |
252b5132 RH |
10798 | offset_expr.X_op = O_constant; |
10799 | } | |
10800 | ||
252b5132 | 10801 | if (offset_expr.X_op == O_constant) |
aed1a261 | 10802 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
10803 | else if (mips_pic == NO_PIC) |
10804 | { | |
d6bc6245 | 10805 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 10806 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
10807 | Otherwise we want |
10808 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
10809 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
10810 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 10811 | so we may as well always use the latter form. |
76b3015f | 10812 | |
6caf9ef4 TS |
10813 | With 64bit address space and a usable $at we want |
10814 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
10815 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
10816 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
10817 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
10818 | dsll32 $tempreg,0 | |
10819 | daddu $tempreg,$tempreg,$at | |
10820 | ||
10821 | If $at is already in use, we use a path which is suboptimal | |
10822 | on superscalar processors. | |
10823 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
10824 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
10825 | dsll $tempreg,16 | |
10826 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
10827 | dsll $tempreg,16 | |
10828 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
10829 | ||
10830 | For GP relative symbols in 64bit address space we can use | |
10831 | the same sequence as in 32bit address space. */ | |
aed1a261 | 10832 | if (HAVE_64BIT_SYMBOLS) |
252b5132 | 10833 | { |
6caf9ef4 TS |
10834 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
10835 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
10836 | { | |
10837 | relax_start (offset_expr.X_add_symbol); | |
10838 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
10839 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
10840 | relax_switch (); | |
10841 | } | |
d6bc6245 | 10842 | |
741fe287 | 10843 | if (used_at == 0 && mips_opts.at) |
98d3f06f | 10844 | { |
df58fc94 | 10845 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 10846 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 10847 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 10848 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 10849 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 10850 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 10851 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 10852 | AT, AT, BFD_RELOC_LO16); |
df58fc94 | 10853 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb | 10854 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
98d3f06f KH |
10855 | used_at = 1; |
10856 | } | |
10857 | else | |
10858 | { | |
df58fc94 | 10859 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 10860 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 10861 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 10862 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
df58fc94 | 10863 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 10864 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 10865 | tempreg, tempreg, BFD_RELOC_HI16_S); |
df58fc94 | 10866 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 10867 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 10868 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 10869 | } |
6caf9ef4 TS |
10870 | |
10871 | if (mips_relax.sequence) | |
10872 | relax_end (); | |
98d3f06f KH |
10873 | } |
10874 | else | |
10875 | { | |
10876 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 10877 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
98d3f06f | 10878 | { |
4d7206a2 | 10879 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
10880 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
10881 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 10882 | relax_switch (); |
98d3f06f | 10883 | } |
6943caf0 | 10884 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
1661c76c | 10885 | as_bad (_("offset too large")); |
67c0d1eb RS |
10886 | macro_build_lui (&offset_expr, tempreg); |
10887 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
10888 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
10889 | if (mips_relax.sequence) |
10890 | relax_end (); | |
98d3f06f | 10891 | } |
252b5132 | 10892 | } |
0a44bf69 | 10893 | else if (!mips_big_got && !HAVE_NEWABI) |
252b5132 | 10894 | { |
9117d219 NC |
10895 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
10896 | ||
252b5132 RH |
10897 | /* If this is a reference to an external symbol, and there |
10898 | is no constant, we want | |
10899 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 10900 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 10901 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
10902 | For a local symbol, we want |
10903 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
10904 | nop | |
10905 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
10906 | ||
10907 | If we have a small constant, and this is a reference to | |
10908 | an external symbol, we want | |
10909 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
10910 | nop | |
10911 | addiu $tempreg,$tempreg,<constant> | |
10912 | For a local symbol, we want the same instruction | |
10913 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
10914 | addiu instruction. | |
10915 | ||
10916 | If we have a large constant, and this is a reference to | |
10917 | an external symbol, we want | |
10918 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
10919 | lui $at,<hiconstant> | |
10920 | addiu $at,$at,<loconstant> | |
10921 | addu $tempreg,$tempreg,$at | |
10922 | For a local symbol, we want the same instruction | |
10923 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 10924 | addiu instruction. |
ed6fb7bd SC |
10925 | */ |
10926 | ||
4d7206a2 | 10927 | if (offset_expr.X_add_number == 0) |
252b5132 | 10928 | { |
0a44bf69 RS |
10929 | if (mips_pic == SVR4_PIC |
10930 | && breg == 0 | |
10931 | && (call || tempreg == PIC_CALL_REG)) | |
4d7206a2 RS |
10932 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; |
10933 | ||
10934 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
10935 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
10936 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 10937 | if (breg != 0) |
252b5132 RH |
10938 | { |
10939 | /* We're going to put in an addu instruction using | |
10940 | tempreg, so we may as well insert the nop right | |
10941 | now. */ | |
269137b2 | 10942 | load_delay_nop (); |
252b5132 | 10943 | } |
4d7206a2 | 10944 | relax_switch (); |
67c0d1eb RS |
10945 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
10946 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 10947 | load_delay_nop (); |
67c0d1eb RS |
10948 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
10949 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 10950 | relax_end (); |
252b5132 RH |
10951 | /* FIXME: If breg == 0, and the next instruction uses |
10952 | $tempreg, then if this variant case is used an extra | |
10953 | nop will be generated. */ | |
10954 | } | |
4d7206a2 RS |
10955 | else if (offset_expr.X_add_number >= -0x8000 |
10956 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 10957 | { |
67c0d1eb | 10958 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 10959 | load_delay_nop (); |
67c0d1eb | 10960 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
10961 | } |
10962 | else | |
10963 | { | |
4d7206a2 RS |
10964 | expr1.X_add_number = offset_expr.X_add_number; |
10965 | offset_expr.X_add_number = | |
43c0598f | 10966 | SEXT_16BIT (offset_expr.X_add_number); |
67c0d1eb | 10967 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 10968 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
10969 | /* If we are going to add in a base register, and the |
10970 | target register and the base register are the same, | |
10971 | then we are using AT as a temporary register. Since | |
10972 | we want to load the constant into AT, we add our | |
10973 | current AT (from the global offset table) and the | |
10974 | register into the register now, and pretend we were | |
10975 | not using a base register. */ | |
c0ebe874 | 10976 | if (breg == op[0]) |
252b5132 | 10977 | { |
269137b2 | 10978 | load_delay_nop (); |
67c0d1eb | 10979 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 | 10980 | op[0], AT, breg); |
252b5132 | 10981 | breg = 0; |
c0ebe874 | 10982 | tempreg = op[0]; |
252b5132 | 10983 | } |
f6a22291 | 10984 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
10985 | used_at = 1; |
10986 | } | |
10987 | } | |
0a44bf69 | 10988 | else if (!mips_big_got && HAVE_NEWABI) |
f5040a92 | 10989 | { |
67c0d1eb | 10990 | int add_breg_early = 0; |
f5040a92 AO |
10991 | |
10992 | /* If this is a reference to an external, and there is no | |
10993 | constant, or local symbol (*), with or without a | |
10994 | constant, we want | |
10995 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 10996 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
10997 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
10998 | ||
10999 | If we have a small constant, and this is a reference to | |
11000 | an external symbol, we want | |
11001 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
11002 | addiu $tempreg,$tempreg,<constant> | |
11003 | ||
11004 | If we have a large constant, and this is a reference to | |
11005 | an external symbol, we want | |
11006 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
11007 | lui $at,<hiconstant> | |
11008 | addiu $at,$at,<loconstant> | |
11009 | addu $tempreg,$tempreg,$at | |
11010 | ||
11011 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
11012 | local symbols, even though it introduces an additional | |
11013 | instruction. */ | |
11014 | ||
f5040a92 AO |
11015 | if (offset_expr.X_add_number) |
11016 | { | |
4d7206a2 | 11017 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
11018 | offset_expr.X_add_number = 0; |
11019 | ||
4d7206a2 | 11020 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
11021 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11022 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
11023 | |
11024 | if (expr1.X_add_number >= -0x8000 | |
11025 | && expr1.X_add_number < 0x8000) | |
11026 | { | |
67c0d1eb RS |
11027 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
11028 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 11029 | } |
ecd13cd3 | 11030 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 11031 | { |
c0ebe874 RS |
11032 | unsigned int dreg; |
11033 | ||
f5040a92 AO |
11034 | /* If we are going to add in a base register, and the |
11035 | target register and the base register are the same, | |
11036 | then we are using AT as a temporary register. Since | |
11037 | we want to load the constant into AT, we add our | |
11038 | current AT (from the global offset table) and the | |
11039 | register into the register now, and pretend we were | |
11040 | not using a base register. */ | |
c0ebe874 | 11041 | if (breg != op[0]) |
f5040a92 AO |
11042 | dreg = tempreg; |
11043 | else | |
11044 | { | |
9c2799c2 | 11045 | gas_assert (tempreg == AT); |
67c0d1eb | 11046 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 RS |
11047 | op[0], AT, breg); |
11048 | dreg = op[0]; | |
67c0d1eb | 11049 | add_breg_early = 1; |
f5040a92 AO |
11050 | } |
11051 | ||
f6a22291 | 11052 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 11053 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 11054 | dreg, dreg, AT); |
f5040a92 | 11055 | |
f5040a92 AO |
11056 | used_at = 1; |
11057 | } | |
11058 | else | |
11059 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
11060 | ||
4d7206a2 | 11061 | relax_switch (); |
f5040a92 AO |
11062 | offset_expr.X_add_number = expr1.X_add_number; |
11063 | ||
67c0d1eb RS |
11064 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11065 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
11066 | if (add_breg_early) | |
f5040a92 | 11067 | { |
67c0d1eb | 11068 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 | 11069 | op[0], tempreg, breg); |
f5040a92 | 11070 | breg = 0; |
c0ebe874 | 11071 | tempreg = op[0]; |
f5040a92 | 11072 | } |
4d7206a2 | 11073 | relax_end (); |
f5040a92 | 11074 | } |
4d7206a2 | 11075 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 11076 | { |
4d7206a2 | 11077 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
11078 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11079 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 11080 | relax_switch (); |
67c0d1eb RS |
11081 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11082 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 11083 | relax_end (); |
f5040a92 | 11084 | } |
4d7206a2 | 11085 | else |
f5040a92 | 11086 | { |
67c0d1eb RS |
11087 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11088 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
11089 | } |
11090 | } | |
0a44bf69 | 11091 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 11092 | { |
67c0d1eb | 11093 | int gpdelay; |
9117d219 NC |
11094 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
11095 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 11096 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
11097 | |
11098 | /* This is the large GOT case. If this is a reference to an | |
11099 | external symbol, and there is no constant, we want | |
11100 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11101 | addu $tempreg,$tempreg,$gp | |
11102 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 11103 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
11104 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
11105 | addu $tempreg,$tempreg,$gp | |
11106 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
11107 | For a local symbol, we want |
11108 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
11109 | nop | |
11110 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
11111 | ||
11112 | If we have a small constant, and this is a reference to | |
11113 | an external symbol, we want | |
11114 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11115 | addu $tempreg,$tempreg,$gp | |
11116 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
11117 | nop | |
11118 | addiu $tempreg,$tempreg,<constant> | |
11119 | For a local symbol, we want | |
11120 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
11121 | nop | |
11122 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
11123 | ||
11124 | If we have a large constant, and this is a reference to | |
11125 | an external symbol, we want | |
11126 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11127 | addu $tempreg,$tempreg,$gp | |
11128 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
11129 | lui $at,<hiconstant> | |
11130 | addiu $at,$at,<loconstant> | |
11131 | addu $tempreg,$tempreg,$at | |
11132 | For a local symbol, we want | |
11133 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
11134 | lui $at,<hiconstant> | |
11135 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
11136 | addu $tempreg,$tempreg,$at | |
f5040a92 | 11137 | */ |
438c16b8 | 11138 | |
252b5132 RH |
11139 | expr1.X_add_number = offset_expr.X_add_number; |
11140 | offset_expr.X_add_number = 0; | |
4d7206a2 | 11141 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 11142 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
11143 | if (expr1.X_add_number == 0 && breg == 0 |
11144 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
11145 | { |
11146 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
11147 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
11148 | } | |
df58fc94 | 11149 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 11150 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 11151 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 11152 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 11153 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
11154 | if (expr1.X_add_number == 0) |
11155 | { | |
67c0d1eb | 11156 | if (breg != 0) |
252b5132 RH |
11157 | { |
11158 | /* We're going to put in an addu instruction using | |
11159 | tempreg, so we may as well insert the nop right | |
11160 | now. */ | |
269137b2 | 11161 | load_delay_nop (); |
252b5132 | 11162 | } |
252b5132 RH |
11163 | } |
11164 | else if (expr1.X_add_number >= -0x8000 | |
11165 | && expr1.X_add_number < 0x8000) | |
11166 | { | |
269137b2 | 11167 | load_delay_nop (); |
67c0d1eb | 11168 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 11169 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
11170 | } |
11171 | else | |
11172 | { | |
c0ebe874 RS |
11173 | unsigned int dreg; |
11174 | ||
252b5132 RH |
11175 | /* If we are going to add in a base register, and the |
11176 | target register and the base register are the same, | |
11177 | then we are using AT as a temporary register. Since | |
11178 | we want to load the constant into AT, we add our | |
11179 | current AT (from the global offset table) and the | |
11180 | register into the register now, and pretend we were | |
11181 | not using a base register. */ | |
c0ebe874 | 11182 | if (breg != op[0]) |
67c0d1eb | 11183 | dreg = tempreg; |
252b5132 RH |
11184 | else |
11185 | { | |
9c2799c2 | 11186 | gas_assert (tempreg == AT); |
269137b2 | 11187 | load_delay_nop (); |
67c0d1eb | 11188 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 RS |
11189 | op[0], AT, breg); |
11190 | dreg = op[0]; | |
252b5132 RH |
11191 | } |
11192 | ||
f6a22291 | 11193 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 11194 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 11195 | |
252b5132 RH |
11196 | used_at = 1; |
11197 | } | |
43c0598f | 11198 | offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number); |
4d7206a2 | 11199 | relax_switch (); |
252b5132 | 11200 | |
67c0d1eb | 11201 | if (gpdelay) |
252b5132 RH |
11202 | { |
11203 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 11204 | the first instruction on the main stream does not. */ |
67c0d1eb | 11205 | macro_build (NULL, "nop", ""); |
252b5132 | 11206 | } |
ed6fb7bd | 11207 | |
67c0d1eb RS |
11208 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11209 | local_reloc_type, mips_gp_register); | |
f5040a92 | 11210 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
11211 | && expr1.X_add_number < 0x8000) |
11212 | { | |
269137b2 | 11213 | load_delay_nop (); |
67c0d1eb RS |
11214 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
11215 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 11216 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
11217 | register, the external symbol case ended with a load, |
11218 | so if the symbol turns out to not be external, and | |
11219 | the next instruction uses tempreg, an unnecessary nop | |
11220 | will be inserted. */ | |
252b5132 RH |
11221 | } |
11222 | else | |
11223 | { | |
c0ebe874 | 11224 | if (breg == op[0]) |
252b5132 RH |
11225 | { |
11226 | /* We must add in the base register now, as in the | |
f5040a92 | 11227 | external symbol case. */ |
9c2799c2 | 11228 | gas_assert (tempreg == AT); |
269137b2 | 11229 | load_delay_nop (); |
67c0d1eb | 11230 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 RS |
11231 | op[0], AT, breg); |
11232 | tempreg = op[0]; | |
252b5132 | 11233 | /* We set breg to 0 because we have arranged to add |
f5040a92 | 11234 | it in in both cases. */ |
252b5132 RH |
11235 | breg = 0; |
11236 | } | |
11237 | ||
67c0d1eb RS |
11238 | macro_build_lui (&expr1, AT); |
11239 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 11240 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 11241 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 11242 | tempreg, tempreg, AT); |
8fc2e39e | 11243 | used_at = 1; |
252b5132 | 11244 | } |
4d7206a2 | 11245 | relax_end (); |
252b5132 | 11246 | } |
0a44bf69 | 11247 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 11248 | { |
f5040a92 AO |
11249 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
11250 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 11251 | int add_breg_early = 0; |
f5040a92 AO |
11252 | |
11253 | /* This is the large GOT case. If this is a reference to an | |
11254 | external symbol, and there is no constant, we want | |
11255 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11256 | add $tempreg,$tempreg,$gp | |
11257 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 11258 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
11259 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
11260 | add $tempreg,$tempreg,$gp | |
11261 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
11262 | ||
11263 | If we have a small constant, and this is a reference to | |
11264 | an external symbol, we want | |
11265 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11266 | add $tempreg,$tempreg,$gp | |
11267 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
11268 | addi $tempreg,$tempreg,<constant> | |
11269 | ||
11270 | If we have a large constant, and this is a reference to | |
11271 | an external symbol, we want | |
11272 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11273 | addu $tempreg,$tempreg,$gp | |
11274 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
11275 | lui $at,<hiconstant> | |
11276 | addi $at,$at,<loconstant> | |
11277 | add $tempreg,$tempreg,$at | |
11278 | ||
11279 | If we have NewABI, and we know it's a local symbol, we want | |
11280 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
11281 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
11282 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
11283 | ||
4d7206a2 | 11284 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 11285 | |
4d7206a2 | 11286 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
11287 | offset_expr.X_add_number = 0; |
11288 | ||
1abe91b1 MR |
11289 | if (expr1.X_add_number == 0 && breg == 0 |
11290 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
11291 | { |
11292 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
11293 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
11294 | } | |
df58fc94 | 11295 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 11296 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 11297 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
11298 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11299 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
11300 | |
11301 | if (expr1.X_add_number == 0) | |
4d7206a2 | 11302 | ; |
f5040a92 AO |
11303 | else if (expr1.X_add_number >= -0x8000 |
11304 | && expr1.X_add_number < 0x8000) | |
11305 | { | |
67c0d1eb | 11306 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 11307 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 11308 | } |
ecd13cd3 | 11309 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 11310 | { |
c0ebe874 RS |
11311 | unsigned int dreg; |
11312 | ||
f5040a92 AO |
11313 | /* If we are going to add in a base register, and the |
11314 | target register and the base register are the same, | |
11315 | then we are using AT as a temporary register. Since | |
11316 | we want to load the constant into AT, we add our | |
11317 | current AT (from the global offset table) and the | |
11318 | register into the register now, and pretend we were | |
11319 | not using a base register. */ | |
c0ebe874 | 11320 | if (breg != op[0]) |
f5040a92 AO |
11321 | dreg = tempreg; |
11322 | else | |
11323 | { | |
9c2799c2 | 11324 | gas_assert (tempreg == AT); |
67c0d1eb | 11325 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 RS |
11326 | op[0], AT, breg); |
11327 | dreg = op[0]; | |
67c0d1eb | 11328 | add_breg_early = 1; |
f5040a92 AO |
11329 | } |
11330 | ||
f6a22291 | 11331 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 11332 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 11333 | |
f5040a92 AO |
11334 | used_at = 1; |
11335 | } | |
11336 | else | |
11337 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
11338 | ||
4d7206a2 | 11339 | relax_switch (); |
f5040a92 | 11340 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
11341 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11342 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
11343 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
11344 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
11345 | if (add_breg_early) | |
f5040a92 | 11346 | { |
67c0d1eb | 11347 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 | 11348 | op[0], tempreg, breg); |
f5040a92 | 11349 | breg = 0; |
c0ebe874 | 11350 | tempreg = op[0]; |
f5040a92 | 11351 | } |
4d7206a2 | 11352 | relax_end (); |
f5040a92 | 11353 | } |
252b5132 RH |
11354 | else |
11355 | abort (); | |
11356 | ||
11357 | if (breg != 0) | |
c0ebe874 | 11358 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", op[0], tempreg, breg); |
252b5132 RH |
11359 | break; |
11360 | ||
52b6b6b9 | 11361 | case M_MSGSND: |
df58fc94 | 11362 | gas_assert (!mips_opts.micromips); |
c0ebe874 | 11363 | macro_build (NULL, "c2", "C", (op[0] << 16) | 0x01); |
c7af4273 | 11364 | break; |
52b6b6b9 JM |
11365 | |
11366 | case M_MSGLD: | |
df58fc94 | 11367 | gas_assert (!mips_opts.micromips); |
c8276761 | 11368 | macro_build (NULL, "c2", "C", 0x02); |
c7af4273 | 11369 | break; |
52b6b6b9 JM |
11370 | |
11371 | case M_MSGLD_T: | |
df58fc94 | 11372 | gas_assert (!mips_opts.micromips); |
c0ebe874 | 11373 | macro_build (NULL, "c2", "C", (op[0] << 16) | 0x02); |
c7af4273 | 11374 | break; |
52b6b6b9 JM |
11375 | |
11376 | case M_MSGWAIT: | |
df58fc94 | 11377 | gas_assert (!mips_opts.micromips); |
52b6b6b9 | 11378 | macro_build (NULL, "c2", "C", 3); |
c7af4273 | 11379 | break; |
52b6b6b9 JM |
11380 | |
11381 | case M_MSGWAIT_T: | |
df58fc94 | 11382 | gas_assert (!mips_opts.micromips); |
c0ebe874 | 11383 | macro_build (NULL, "c2", "C", (op[0] << 16) | 0x03); |
c7af4273 | 11384 | break; |
52b6b6b9 | 11385 | |
252b5132 RH |
11386 | case M_J_A: |
11387 | /* The j instruction may not be used in PIC code, since it | |
11388 | requires an absolute address. We convert it to a b | |
11389 | instruction. */ | |
11390 | if (mips_pic == NO_PIC) | |
67c0d1eb | 11391 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 11392 | else |
67c0d1eb | 11393 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 11394 | break; |
252b5132 RH |
11395 | |
11396 | /* The jal instructions must be handled as macros because when | |
11397 | generating PIC code they expand to multi-instruction | |
11398 | sequences. Normally they are simple instructions. */ | |
df58fc94 | 11399 | case M_JALS_1: |
c0ebe874 RS |
11400 | op[1] = op[0]; |
11401 | op[0] = RA; | |
df58fc94 RS |
11402 | /* Fall through. */ |
11403 | case M_JALS_2: | |
11404 | gas_assert (mips_opts.micromips); | |
833794fc MR |
11405 | if (mips_opts.insn32) |
11406 | { | |
1661c76c | 11407 | as_bad (_("opcode not supported in the `insn32' mode `%s'"), str); |
833794fc MR |
11408 | break; |
11409 | } | |
df58fc94 RS |
11410 | jals = 1; |
11411 | goto jal; | |
252b5132 | 11412 | case M_JAL_1: |
c0ebe874 RS |
11413 | op[1] = op[0]; |
11414 | op[0] = RA; | |
252b5132 RH |
11415 | /* Fall through. */ |
11416 | case M_JAL_2: | |
df58fc94 | 11417 | jal: |
3e722fb5 | 11418 | if (mips_pic == NO_PIC) |
df58fc94 RS |
11419 | { |
11420 | s = jals ? "jalrs" : "jalr"; | |
e64af278 | 11421 | if (mips_opts.micromips |
833794fc | 11422 | && !mips_opts.insn32 |
c0ebe874 | 11423 | && op[0] == RA |
e64af278 | 11424 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
c0ebe874 | 11425 | macro_build (NULL, s, "mj", op[1]); |
df58fc94 | 11426 | else |
c0ebe874 | 11427 | macro_build (NULL, s, JALR_FMT, op[0], op[1]); |
df58fc94 | 11428 | } |
0a44bf69 | 11429 | else |
252b5132 | 11430 | { |
df58fc94 RS |
11431 | int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI |
11432 | && mips_cprestore_offset >= 0); | |
11433 | ||
c0ebe874 | 11434 | if (op[1] != PIC_CALL_REG) |
252b5132 | 11435 | as_warn (_("MIPS PIC call to register other than $25")); |
bdaaa2e1 | 11436 | |
833794fc MR |
11437 | s = ((mips_opts.micromips |
11438 | && !mips_opts.insn32 | |
11439 | && (!mips_opts.noreorder || cprestore)) | |
df58fc94 | 11440 | ? "jalrs" : "jalr"); |
e64af278 | 11441 | if (mips_opts.micromips |
833794fc | 11442 | && !mips_opts.insn32 |
c0ebe874 | 11443 | && op[0] == RA |
e64af278 | 11444 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
c0ebe874 | 11445 | macro_build (NULL, s, "mj", op[1]); |
df58fc94 | 11446 | else |
c0ebe874 | 11447 | macro_build (NULL, s, JALR_FMT, op[0], op[1]); |
0a44bf69 | 11448 | if (mips_pic == SVR4_PIC && !HAVE_NEWABI) |
252b5132 | 11449 | { |
6478892d | 11450 | if (mips_cprestore_offset < 0) |
1661c76c | 11451 | as_warn (_("no .cprestore pseudo-op used in PIC code")); |
6478892d TS |
11452 | else |
11453 | { | |
90ecf173 | 11454 | if (!mips_frame_reg_valid) |
7a621144 | 11455 | { |
1661c76c | 11456 | as_warn (_("no .frame pseudo-op used in PIC code")); |
7a621144 DJ |
11457 | /* Quiet this warning. */ |
11458 | mips_frame_reg_valid = 1; | |
11459 | } | |
90ecf173 | 11460 | if (!mips_cprestore_valid) |
7a621144 | 11461 | { |
1661c76c | 11462 | as_warn (_("no .cprestore pseudo-op used in PIC code")); |
7a621144 DJ |
11463 | /* Quiet this warning. */ |
11464 | mips_cprestore_valid = 1; | |
11465 | } | |
d3fca0b5 MR |
11466 | if (mips_opts.noreorder) |
11467 | macro_build (NULL, "nop", ""); | |
6478892d | 11468 | expr1.X_add_number = mips_cprestore_offset; |
134c0c8b | 11469 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 11470 | mips_gp_register, |
256ab948 TS |
11471 | mips_frame_reg, |
11472 | HAVE_64BIT_ADDRESSES); | |
6478892d | 11473 | } |
252b5132 RH |
11474 | } |
11475 | } | |
252b5132 | 11476 | |
8fc2e39e | 11477 | break; |
252b5132 | 11478 | |
df58fc94 RS |
11479 | case M_JALS_A: |
11480 | gas_assert (mips_opts.micromips); | |
833794fc MR |
11481 | if (mips_opts.insn32) |
11482 | { | |
1661c76c | 11483 | as_bad (_("opcode not supported in the `insn32' mode `%s'"), str); |
833794fc MR |
11484 | break; |
11485 | } | |
df58fc94 RS |
11486 | jals = 1; |
11487 | /* Fall through. */ | |
252b5132 RH |
11488 | case M_JAL_A: |
11489 | if (mips_pic == NO_PIC) | |
df58fc94 | 11490 | macro_build (&offset_expr, jals ? "jals" : "jal", "a"); |
252b5132 RH |
11491 | else if (mips_pic == SVR4_PIC) |
11492 | { | |
11493 | /* If this is a reference to an external symbol, and we are | |
11494 | using a small GOT, we want | |
11495 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
11496 | nop | |
f9419b05 | 11497 | jalr $ra,$25 |
252b5132 RH |
11498 | nop |
11499 | lw $gp,cprestore($sp) | |
11500 | The cprestore value is set using the .cprestore | |
11501 | pseudo-op. If we are using a big GOT, we want | |
11502 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
11503 | addu $25,$25,$gp | |
11504 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
11505 | nop | |
f9419b05 | 11506 | jalr $ra,$25 |
252b5132 RH |
11507 | nop |
11508 | lw $gp,cprestore($sp) | |
11509 | If the symbol is not external, we want | |
11510 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
11511 | nop | |
11512 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 11513 | jalr $ra,$25 |
252b5132 | 11514 | nop |
438c16b8 | 11515 | lw $gp,cprestore($sp) |
f5040a92 AO |
11516 | |
11517 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
11518 | sequences above, minus nops, unless the symbol is local, | |
11519 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
11520 | GOT_DISP. */ | |
438c16b8 | 11521 | if (HAVE_NEWABI) |
252b5132 | 11522 | { |
90ecf173 | 11523 | if (!mips_big_got) |
f5040a92 | 11524 | { |
4d7206a2 | 11525 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
11526 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11527 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 11528 | mips_gp_register); |
4d7206a2 | 11529 | relax_switch (); |
67c0d1eb RS |
11530 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11531 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
11532 | mips_gp_register); |
11533 | relax_end (); | |
f5040a92 AO |
11534 | } |
11535 | else | |
11536 | { | |
4d7206a2 | 11537 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 11538 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
11539 | BFD_RELOC_MIPS_CALL_HI16); |
11540 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
11541 | PIC_CALL_REG, mips_gp_register); | |
11542 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
11543 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
11544 | PIC_CALL_REG); | |
4d7206a2 | 11545 | relax_switch (); |
67c0d1eb RS |
11546 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11547 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
11548 | mips_gp_register); | |
11549 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
11550 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 11551 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 11552 | relax_end (); |
f5040a92 | 11553 | } |
684022ea | 11554 | |
df58fc94 | 11555 | macro_build_jalr (&offset_expr, 0); |
252b5132 RH |
11556 | } |
11557 | else | |
11558 | { | |
4d7206a2 | 11559 | relax_start (offset_expr.X_add_symbol); |
90ecf173 | 11560 | if (!mips_big_got) |
438c16b8 | 11561 | { |
67c0d1eb RS |
11562 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11563 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 11564 | mips_gp_register); |
269137b2 | 11565 | load_delay_nop (); |
4d7206a2 | 11566 | relax_switch (); |
438c16b8 | 11567 | } |
252b5132 | 11568 | else |
252b5132 | 11569 | { |
67c0d1eb RS |
11570 | int gpdelay; |
11571 | ||
11572 | gpdelay = reg_needs_delay (mips_gp_register); | |
df58fc94 | 11573 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
11574 | BFD_RELOC_MIPS_CALL_HI16); |
11575 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
11576 | PIC_CALL_REG, mips_gp_register); | |
11577 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
11578 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
11579 | PIC_CALL_REG); | |
269137b2 | 11580 | load_delay_nop (); |
4d7206a2 | 11581 | relax_switch (); |
67c0d1eb RS |
11582 | if (gpdelay) |
11583 | macro_build (NULL, "nop", ""); | |
252b5132 | 11584 | } |
67c0d1eb RS |
11585 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11586 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 11587 | mips_gp_register); |
269137b2 | 11588 | load_delay_nop (); |
67c0d1eb RS |
11589 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
11590 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 11591 | relax_end (); |
df58fc94 | 11592 | macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0); |
438c16b8 | 11593 | |
6478892d | 11594 | if (mips_cprestore_offset < 0) |
1661c76c | 11595 | as_warn (_("no .cprestore pseudo-op used in PIC code")); |
6478892d TS |
11596 | else |
11597 | { | |
90ecf173 | 11598 | if (!mips_frame_reg_valid) |
7a621144 | 11599 | { |
1661c76c | 11600 | as_warn (_("no .frame pseudo-op used in PIC code")); |
7a621144 DJ |
11601 | /* Quiet this warning. */ |
11602 | mips_frame_reg_valid = 1; | |
11603 | } | |
90ecf173 | 11604 | if (!mips_cprestore_valid) |
7a621144 | 11605 | { |
1661c76c | 11606 | as_warn (_("no .cprestore pseudo-op used in PIC code")); |
7a621144 DJ |
11607 | /* Quiet this warning. */ |
11608 | mips_cprestore_valid = 1; | |
11609 | } | |
6478892d | 11610 | if (mips_opts.noreorder) |
67c0d1eb | 11611 | macro_build (NULL, "nop", ""); |
6478892d | 11612 | expr1.X_add_number = mips_cprestore_offset; |
134c0c8b | 11613 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 11614 | mips_gp_register, |
256ab948 TS |
11615 | mips_frame_reg, |
11616 | HAVE_64BIT_ADDRESSES); | |
6478892d | 11617 | } |
252b5132 RH |
11618 | } |
11619 | } | |
0a44bf69 | 11620 | else if (mips_pic == VXWORKS_PIC) |
1661c76c | 11621 | as_bad (_("non-PIC jump used in PIC library")); |
252b5132 RH |
11622 | else |
11623 | abort (); | |
11624 | ||
8fc2e39e | 11625 | break; |
252b5132 | 11626 | |
7f3c4072 | 11627 | case M_LBUE_AB: |
7f3c4072 CM |
11628 | s = "lbue"; |
11629 | fmt = "t,+j(b)"; | |
11630 | offbits = 9; | |
11631 | goto ld_st; | |
11632 | case M_LHUE_AB: | |
7f3c4072 CM |
11633 | s = "lhue"; |
11634 | fmt = "t,+j(b)"; | |
11635 | offbits = 9; | |
11636 | goto ld_st; | |
11637 | case M_LBE_AB: | |
7f3c4072 CM |
11638 | s = "lbe"; |
11639 | fmt = "t,+j(b)"; | |
11640 | offbits = 9; | |
11641 | goto ld_st; | |
11642 | case M_LHE_AB: | |
7f3c4072 CM |
11643 | s = "lhe"; |
11644 | fmt = "t,+j(b)"; | |
11645 | offbits = 9; | |
11646 | goto ld_st; | |
11647 | case M_LLE_AB: | |
7f3c4072 CM |
11648 | s = "lle"; |
11649 | fmt = "t,+j(b)"; | |
11650 | offbits = 9; | |
11651 | goto ld_st; | |
11652 | case M_LWE_AB: | |
7f3c4072 CM |
11653 | s = "lwe"; |
11654 | fmt = "t,+j(b)"; | |
11655 | offbits = 9; | |
11656 | goto ld_st; | |
11657 | case M_LWLE_AB: | |
7f3c4072 CM |
11658 | s = "lwle"; |
11659 | fmt = "t,+j(b)"; | |
11660 | offbits = 9; | |
11661 | goto ld_st; | |
11662 | case M_LWRE_AB: | |
7f3c4072 CM |
11663 | s = "lwre"; |
11664 | fmt = "t,+j(b)"; | |
11665 | offbits = 9; | |
11666 | goto ld_st; | |
11667 | case M_SBE_AB: | |
7f3c4072 CM |
11668 | s = "sbe"; |
11669 | fmt = "t,+j(b)"; | |
11670 | offbits = 9; | |
11671 | goto ld_st; | |
11672 | case M_SCE_AB: | |
7f3c4072 CM |
11673 | s = "sce"; |
11674 | fmt = "t,+j(b)"; | |
11675 | offbits = 9; | |
11676 | goto ld_st; | |
11677 | case M_SHE_AB: | |
7f3c4072 CM |
11678 | s = "she"; |
11679 | fmt = "t,+j(b)"; | |
11680 | offbits = 9; | |
11681 | goto ld_st; | |
11682 | case M_SWE_AB: | |
7f3c4072 CM |
11683 | s = "swe"; |
11684 | fmt = "t,+j(b)"; | |
11685 | offbits = 9; | |
11686 | goto ld_st; | |
11687 | case M_SWLE_AB: | |
7f3c4072 CM |
11688 | s = "swle"; |
11689 | fmt = "t,+j(b)"; | |
11690 | offbits = 9; | |
11691 | goto ld_st; | |
11692 | case M_SWRE_AB: | |
7f3c4072 CM |
11693 | s = "swre"; |
11694 | fmt = "t,+j(b)"; | |
11695 | offbits = 9; | |
11696 | goto ld_st; | |
dec0624d | 11697 | case M_ACLR_AB: |
dec0624d | 11698 | s = "aclr"; |
dec0624d | 11699 | fmt = "\\,~(b)"; |
7f3c4072 | 11700 | offbits = 12; |
dec0624d MR |
11701 | goto ld_st; |
11702 | case M_ASET_AB: | |
dec0624d | 11703 | s = "aset"; |
dec0624d | 11704 | fmt = "\\,~(b)"; |
7f3c4072 | 11705 | offbits = 12; |
dec0624d | 11706 | goto ld_st; |
252b5132 RH |
11707 | case M_LB_AB: |
11708 | s = "lb"; | |
df58fc94 | 11709 | fmt = "t,o(b)"; |
252b5132 RH |
11710 | goto ld; |
11711 | case M_LBU_AB: | |
11712 | s = "lbu"; | |
df58fc94 | 11713 | fmt = "t,o(b)"; |
252b5132 RH |
11714 | goto ld; |
11715 | case M_LH_AB: | |
11716 | s = "lh"; | |
df58fc94 | 11717 | fmt = "t,o(b)"; |
252b5132 RH |
11718 | goto ld; |
11719 | case M_LHU_AB: | |
11720 | s = "lhu"; | |
df58fc94 | 11721 | fmt = "t,o(b)"; |
252b5132 RH |
11722 | goto ld; |
11723 | case M_LW_AB: | |
11724 | s = "lw"; | |
df58fc94 | 11725 | fmt = "t,o(b)"; |
252b5132 RH |
11726 | goto ld; |
11727 | case M_LWC0_AB: | |
df58fc94 | 11728 | gas_assert (!mips_opts.micromips); |
252b5132 | 11729 | s = "lwc0"; |
df58fc94 | 11730 | fmt = "E,o(b)"; |
bdaaa2e1 | 11731 | /* Itbl support may require additional care here. */ |
252b5132 | 11732 | coproc = 1; |
df58fc94 | 11733 | goto ld_st; |
252b5132 RH |
11734 | case M_LWC1_AB: |
11735 | s = "lwc1"; | |
df58fc94 | 11736 | fmt = "T,o(b)"; |
bdaaa2e1 | 11737 | /* Itbl support may require additional care here. */ |
252b5132 | 11738 | coproc = 1; |
df58fc94 | 11739 | goto ld_st; |
252b5132 RH |
11740 | case M_LWC2_AB: |
11741 | s = "lwc2"; | |
df58fc94 | 11742 | fmt = COP12_FMT; |
7361da2c AB |
11743 | offbits = (mips_opts.micromips ? 12 |
11744 | : ISA_IS_R6 (mips_opts.isa) ? 11 | |
11745 | : 16); | |
bdaaa2e1 | 11746 | /* Itbl support may require additional care here. */ |
252b5132 | 11747 | coproc = 1; |
df58fc94 | 11748 | goto ld_st; |
252b5132 | 11749 | case M_LWC3_AB: |
df58fc94 | 11750 | gas_assert (!mips_opts.micromips); |
252b5132 | 11751 | s = "lwc3"; |
df58fc94 | 11752 | fmt = "E,o(b)"; |
bdaaa2e1 | 11753 | /* Itbl support may require additional care here. */ |
252b5132 | 11754 | coproc = 1; |
df58fc94 | 11755 | goto ld_st; |
252b5132 RH |
11756 | case M_LWL_AB: |
11757 | s = "lwl"; | |
df58fc94 | 11758 | fmt = MEM12_FMT; |
7f3c4072 | 11759 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11760 | goto ld_st; |
252b5132 RH |
11761 | case M_LWR_AB: |
11762 | s = "lwr"; | |
df58fc94 | 11763 | fmt = MEM12_FMT; |
7f3c4072 | 11764 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11765 | goto ld_st; |
252b5132 | 11766 | case M_LDC1_AB: |
252b5132 | 11767 | s = "ldc1"; |
df58fc94 | 11768 | fmt = "T,o(b)"; |
bdaaa2e1 | 11769 | /* Itbl support may require additional care here. */ |
252b5132 | 11770 | coproc = 1; |
df58fc94 | 11771 | goto ld_st; |
252b5132 RH |
11772 | case M_LDC2_AB: |
11773 | s = "ldc2"; | |
df58fc94 | 11774 | fmt = COP12_FMT; |
7361da2c AB |
11775 | offbits = (mips_opts.micromips ? 12 |
11776 | : ISA_IS_R6 (mips_opts.isa) ? 11 | |
11777 | : 16); | |
bdaaa2e1 | 11778 | /* Itbl support may require additional care here. */ |
252b5132 | 11779 | coproc = 1; |
df58fc94 | 11780 | goto ld_st; |
c77c0862 | 11781 | case M_LQC2_AB: |
c77c0862 | 11782 | s = "lqc2"; |
14daeee3 | 11783 | fmt = "+7,o(b)"; |
c77c0862 RS |
11784 | /* Itbl support may require additional care here. */ |
11785 | coproc = 1; | |
11786 | goto ld_st; | |
252b5132 RH |
11787 | case M_LDC3_AB: |
11788 | s = "ldc3"; | |
df58fc94 | 11789 | fmt = "E,o(b)"; |
bdaaa2e1 | 11790 | /* Itbl support may require additional care here. */ |
252b5132 | 11791 | coproc = 1; |
df58fc94 | 11792 | goto ld_st; |
252b5132 RH |
11793 | case M_LDL_AB: |
11794 | s = "ldl"; | |
df58fc94 | 11795 | fmt = MEM12_FMT; |
7f3c4072 | 11796 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11797 | goto ld_st; |
252b5132 RH |
11798 | case M_LDR_AB: |
11799 | s = "ldr"; | |
df58fc94 | 11800 | fmt = MEM12_FMT; |
7f3c4072 | 11801 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11802 | goto ld_st; |
252b5132 RH |
11803 | case M_LL_AB: |
11804 | s = "ll"; | |
7361da2c AB |
11805 | fmt = LL_SC_FMT; |
11806 | offbits = (mips_opts.micromips ? 12 | |
11807 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
11808 | : 16); | |
252b5132 RH |
11809 | goto ld; |
11810 | case M_LLD_AB: | |
11811 | s = "lld"; | |
7361da2c AB |
11812 | fmt = LL_SC_FMT; |
11813 | offbits = (mips_opts.micromips ? 12 | |
11814 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
11815 | : 16); | |
252b5132 RH |
11816 | goto ld; |
11817 | case M_LWU_AB: | |
11818 | s = "lwu"; | |
df58fc94 | 11819 | fmt = MEM12_FMT; |
7f3c4072 | 11820 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
11821 | goto ld; |
11822 | case M_LWP_AB: | |
df58fc94 RS |
11823 | gas_assert (mips_opts.micromips); |
11824 | s = "lwp"; | |
11825 | fmt = "t,~(b)"; | |
7f3c4072 | 11826 | offbits = 12; |
df58fc94 RS |
11827 | lp = 1; |
11828 | goto ld; | |
11829 | case M_LDP_AB: | |
df58fc94 RS |
11830 | gas_assert (mips_opts.micromips); |
11831 | s = "ldp"; | |
11832 | fmt = "t,~(b)"; | |
7f3c4072 | 11833 | offbits = 12; |
df58fc94 RS |
11834 | lp = 1; |
11835 | goto ld; | |
11836 | case M_LWM_AB: | |
df58fc94 RS |
11837 | gas_assert (mips_opts.micromips); |
11838 | s = "lwm"; | |
11839 | fmt = "n,~(b)"; | |
7f3c4072 | 11840 | offbits = 12; |
df58fc94 RS |
11841 | goto ld_st; |
11842 | case M_LDM_AB: | |
df58fc94 RS |
11843 | gas_assert (mips_opts.micromips); |
11844 | s = "ldm"; | |
11845 | fmt = "n,~(b)"; | |
7f3c4072 | 11846 | offbits = 12; |
df58fc94 RS |
11847 | goto ld_st; |
11848 | ||
252b5132 | 11849 | ld: |
f19ccbda | 11850 | /* We don't want to use $0 as tempreg. */ |
c0ebe874 | 11851 | if (op[2] == op[0] + lp || op[0] + lp == ZERO) |
df58fc94 | 11852 | goto ld_st; |
252b5132 | 11853 | else |
c0ebe874 | 11854 | tempreg = op[0] + lp; |
df58fc94 RS |
11855 | goto ld_noat; |
11856 | ||
252b5132 RH |
11857 | case M_SB_AB: |
11858 | s = "sb"; | |
df58fc94 RS |
11859 | fmt = "t,o(b)"; |
11860 | goto ld_st; | |
252b5132 RH |
11861 | case M_SH_AB: |
11862 | s = "sh"; | |
df58fc94 RS |
11863 | fmt = "t,o(b)"; |
11864 | goto ld_st; | |
252b5132 RH |
11865 | case M_SW_AB: |
11866 | s = "sw"; | |
df58fc94 RS |
11867 | fmt = "t,o(b)"; |
11868 | goto ld_st; | |
252b5132 | 11869 | case M_SWC0_AB: |
df58fc94 | 11870 | gas_assert (!mips_opts.micromips); |
252b5132 | 11871 | s = "swc0"; |
df58fc94 | 11872 | fmt = "E,o(b)"; |
bdaaa2e1 | 11873 | /* Itbl support may require additional care here. */ |
252b5132 | 11874 | coproc = 1; |
df58fc94 | 11875 | goto ld_st; |
252b5132 RH |
11876 | case M_SWC1_AB: |
11877 | s = "swc1"; | |
df58fc94 | 11878 | fmt = "T,o(b)"; |
bdaaa2e1 | 11879 | /* Itbl support may require additional care here. */ |
252b5132 | 11880 | coproc = 1; |
df58fc94 | 11881 | goto ld_st; |
252b5132 RH |
11882 | case M_SWC2_AB: |
11883 | s = "swc2"; | |
df58fc94 | 11884 | fmt = COP12_FMT; |
7361da2c AB |
11885 | offbits = (mips_opts.micromips ? 12 |
11886 | : ISA_IS_R6 (mips_opts.isa) ? 11 | |
11887 | : 16); | |
bdaaa2e1 | 11888 | /* Itbl support may require additional care here. */ |
252b5132 | 11889 | coproc = 1; |
df58fc94 | 11890 | goto ld_st; |
252b5132 | 11891 | case M_SWC3_AB: |
df58fc94 | 11892 | gas_assert (!mips_opts.micromips); |
252b5132 | 11893 | s = "swc3"; |
df58fc94 | 11894 | fmt = "E,o(b)"; |
bdaaa2e1 | 11895 | /* Itbl support may require additional care here. */ |
252b5132 | 11896 | coproc = 1; |
df58fc94 | 11897 | goto ld_st; |
252b5132 RH |
11898 | case M_SWL_AB: |
11899 | s = "swl"; | |
df58fc94 | 11900 | fmt = MEM12_FMT; |
7f3c4072 | 11901 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11902 | goto ld_st; |
252b5132 RH |
11903 | case M_SWR_AB: |
11904 | s = "swr"; | |
df58fc94 | 11905 | fmt = MEM12_FMT; |
7f3c4072 | 11906 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11907 | goto ld_st; |
252b5132 RH |
11908 | case M_SC_AB: |
11909 | s = "sc"; | |
7361da2c AB |
11910 | fmt = LL_SC_FMT; |
11911 | offbits = (mips_opts.micromips ? 12 | |
11912 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
11913 | : 16); | |
df58fc94 | 11914 | goto ld_st; |
252b5132 RH |
11915 | case M_SCD_AB: |
11916 | s = "scd"; | |
7361da2c AB |
11917 | fmt = LL_SC_FMT; |
11918 | offbits = (mips_opts.micromips ? 12 | |
11919 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
11920 | : 16); | |
df58fc94 | 11921 | goto ld_st; |
d43b4baf TS |
11922 | case M_CACHE_AB: |
11923 | s = "cache"; | |
7361da2c AB |
11924 | fmt = (mips_opts.micromips ? "k,~(b)" |
11925 | : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)" | |
11926 | : "k,o(b)"); | |
11927 | offbits = (mips_opts.micromips ? 12 | |
11928 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
11929 | : 16); | |
7f3c4072 CM |
11930 | goto ld_st; |
11931 | case M_CACHEE_AB: | |
7f3c4072 CM |
11932 | s = "cachee"; |
11933 | fmt = "k,+j(b)"; | |
11934 | offbits = 9; | |
df58fc94 | 11935 | goto ld_st; |
3eebd5eb MR |
11936 | case M_PREF_AB: |
11937 | s = "pref"; | |
7361da2c AB |
11938 | fmt = (mips_opts.micromips ? "k,~(b)" |
11939 | : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)" | |
11940 | : "k,o(b)"); | |
11941 | offbits = (mips_opts.micromips ? 12 | |
11942 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
11943 | : 16); | |
7f3c4072 CM |
11944 | goto ld_st; |
11945 | case M_PREFE_AB: | |
7f3c4072 CM |
11946 | s = "prefe"; |
11947 | fmt = "k,+j(b)"; | |
11948 | offbits = 9; | |
df58fc94 | 11949 | goto ld_st; |
252b5132 | 11950 | case M_SDC1_AB: |
252b5132 | 11951 | s = "sdc1"; |
df58fc94 | 11952 | fmt = "T,o(b)"; |
252b5132 | 11953 | coproc = 1; |
bdaaa2e1 | 11954 | /* Itbl support may require additional care here. */ |
df58fc94 | 11955 | goto ld_st; |
252b5132 RH |
11956 | case M_SDC2_AB: |
11957 | s = "sdc2"; | |
df58fc94 | 11958 | fmt = COP12_FMT; |
7361da2c AB |
11959 | offbits = (mips_opts.micromips ? 12 |
11960 | : ISA_IS_R6 (mips_opts.isa) ? 11 | |
11961 | : 16); | |
c77c0862 RS |
11962 | /* Itbl support may require additional care here. */ |
11963 | coproc = 1; | |
11964 | goto ld_st; | |
11965 | case M_SQC2_AB: | |
c77c0862 | 11966 | s = "sqc2"; |
14daeee3 | 11967 | fmt = "+7,o(b)"; |
bdaaa2e1 | 11968 | /* Itbl support may require additional care here. */ |
252b5132 | 11969 | coproc = 1; |
df58fc94 | 11970 | goto ld_st; |
252b5132 | 11971 | case M_SDC3_AB: |
df58fc94 | 11972 | gas_assert (!mips_opts.micromips); |
252b5132 | 11973 | s = "sdc3"; |
df58fc94 | 11974 | fmt = "E,o(b)"; |
bdaaa2e1 | 11975 | /* Itbl support may require additional care here. */ |
252b5132 | 11976 | coproc = 1; |
df58fc94 | 11977 | goto ld_st; |
252b5132 RH |
11978 | case M_SDL_AB: |
11979 | s = "sdl"; | |
df58fc94 | 11980 | fmt = MEM12_FMT; |
7f3c4072 | 11981 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11982 | goto ld_st; |
252b5132 RH |
11983 | case M_SDR_AB: |
11984 | s = "sdr"; | |
df58fc94 | 11985 | fmt = MEM12_FMT; |
7f3c4072 | 11986 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
11987 | goto ld_st; |
11988 | case M_SWP_AB: | |
df58fc94 RS |
11989 | gas_assert (mips_opts.micromips); |
11990 | s = "swp"; | |
11991 | fmt = "t,~(b)"; | |
7f3c4072 | 11992 | offbits = 12; |
df58fc94 RS |
11993 | goto ld_st; |
11994 | case M_SDP_AB: | |
df58fc94 RS |
11995 | gas_assert (mips_opts.micromips); |
11996 | s = "sdp"; | |
11997 | fmt = "t,~(b)"; | |
7f3c4072 | 11998 | offbits = 12; |
df58fc94 RS |
11999 | goto ld_st; |
12000 | case M_SWM_AB: | |
df58fc94 RS |
12001 | gas_assert (mips_opts.micromips); |
12002 | s = "swm"; | |
12003 | fmt = "n,~(b)"; | |
7f3c4072 | 12004 | offbits = 12; |
df58fc94 RS |
12005 | goto ld_st; |
12006 | case M_SDM_AB: | |
df58fc94 RS |
12007 | gas_assert (mips_opts.micromips); |
12008 | s = "sdm"; | |
12009 | fmt = "n,~(b)"; | |
7f3c4072 | 12010 | offbits = 12; |
df58fc94 RS |
12011 | |
12012 | ld_st: | |
8fc2e39e | 12013 | tempreg = AT; |
df58fc94 | 12014 | ld_noat: |
c0ebe874 | 12015 | breg = op[2]; |
f2ae14a1 RS |
12016 | if (small_offset_p (0, align, 16)) |
12017 | { | |
12018 | /* The first case exists for M_LD_AB and M_SD_AB, which are | |
12019 | macros for o32 but which should act like normal instructions | |
12020 | otherwise. */ | |
12021 | if (offbits == 16) | |
c0ebe874 | 12022 | macro_build (&offset_expr, s, fmt, op[0], -1, offset_reloc[0], |
f2ae14a1 RS |
12023 | offset_reloc[1], offset_reloc[2], breg); |
12024 | else if (small_offset_p (0, align, offbits)) | |
12025 | { | |
12026 | if (offbits == 0) | |
c0ebe874 | 12027 | macro_build (NULL, s, fmt, op[0], breg); |
f2ae14a1 | 12028 | else |
c0ebe874 | 12029 | macro_build (NULL, s, fmt, op[0], |
c8276761 | 12030 | (int) offset_expr.X_add_number, breg); |
f2ae14a1 RS |
12031 | } |
12032 | else | |
12033 | { | |
12034 | if (tempreg == AT) | |
12035 | used_at = 1; | |
12036 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
12037 | tempreg, breg, -1, offset_reloc[0], | |
12038 | offset_reloc[1], offset_reloc[2]); | |
12039 | if (offbits == 0) | |
c0ebe874 | 12040 | macro_build (NULL, s, fmt, op[0], tempreg); |
f2ae14a1 | 12041 | else |
c0ebe874 | 12042 | macro_build (NULL, s, fmt, op[0], 0, tempreg); |
f2ae14a1 RS |
12043 | } |
12044 | break; | |
12045 | } | |
12046 | ||
12047 | if (tempreg == AT) | |
12048 | used_at = 1; | |
12049 | ||
252b5132 RH |
12050 | if (offset_expr.X_op != O_constant |
12051 | && offset_expr.X_op != O_symbol) | |
12052 | { | |
1661c76c | 12053 | as_bad (_("expression too complex")); |
252b5132 RH |
12054 | offset_expr.X_op = O_constant; |
12055 | } | |
12056 | ||
2051e8c4 MR |
12057 | if (HAVE_32BIT_ADDRESSES |
12058 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
12059 | { |
12060 | char value [32]; | |
12061 | ||
12062 | sprintf_vma (value, offset_expr.X_add_number); | |
1661c76c | 12063 | as_bad (_("number (0x%s) larger than 32 bits"), value); |
55e08f71 | 12064 | } |
2051e8c4 | 12065 | |
252b5132 RH |
12066 | /* A constant expression in PIC code can be handled just as it |
12067 | is in non PIC code. */ | |
aed1a261 RS |
12068 | if (offset_expr.X_op == O_constant) |
12069 | { | |
f2ae14a1 RS |
12070 | expr1.X_add_number = offset_high_part (offset_expr.X_add_number, |
12071 | offbits == 0 ? 16 : offbits); | |
12072 | offset_expr.X_add_number -= expr1.X_add_number; | |
df58fc94 | 12073 | |
f2ae14a1 RS |
12074 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); |
12075 | if (breg != 0) | |
12076 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
12077 | tempreg, tempreg, breg); | |
7f3c4072 | 12078 | if (offbits == 0) |
dd6a37e7 | 12079 | { |
f2ae14a1 | 12080 | if (offset_expr.X_add_number != 0) |
dd6a37e7 | 12081 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
f2ae14a1 | 12082 | "t,r,j", tempreg, tempreg, BFD_RELOC_LO16); |
c0ebe874 | 12083 | macro_build (NULL, s, fmt, op[0], tempreg); |
dd6a37e7 | 12084 | } |
7f3c4072 | 12085 | else if (offbits == 16) |
c0ebe874 | 12086 | macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, tempreg); |
df58fc94 | 12087 | else |
c0ebe874 | 12088 | macro_build (NULL, s, fmt, op[0], |
c8276761 | 12089 | (int) offset_expr.X_add_number, tempreg); |
df58fc94 | 12090 | } |
7f3c4072 | 12091 | else if (offbits != 16) |
df58fc94 | 12092 | { |
7f3c4072 | 12093 | /* The offset field is too narrow to be used for a low-part |
2b0f3761 | 12094 | relocation, so load the whole address into the auxiliary |
f2ae14a1 RS |
12095 | register. */ |
12096 | load_address (tempreg, &offset_expr, &used_at); | |
12097 | if (breg != 0) | |
12098 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
12099 | tempreg, tempreg, breg); | |
7f3c4072 | 12100 | if (offbits == 0) |
c0ebe874 | 12101 | macro_build (NULL, s, fmt, op[0], tempreg); |
dd6a37e7 | 12102 | else |
c0ebe874 | 12103 | macro_build (NULL, s, fmt, op[0], 0, tempreg); |
aed1a261 RS |
12104 | } |
12105 | else if (mips_pic == NO_PIC) | |
252b5132 RH |
12106 | { |
12107 | /* If this is a reference to a GP relative symbol, and there | |
12108 | is no base register, we want | |
c0ebe874 | 12109 | <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
12110 | Otherwise, if there is no base register, we want |
12111 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
c0ebe874 | 12112 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
252b5132 RH |
12113 | If we have a constant, we need two instructions anyhow, |
12114 | so we always use the latter form. | |
12115 | ||
12116 | If we have a base register, and this is a reference to a | |
12117 | GP relative symbol, we want | |
12118 | addu $tempreg,$breg,$gp | |
c0ebe874 | 12119 | <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
12120 | Otherwise we want |
12121 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
12122 | addu $tempreg,$tempreg,$breg | |
c0ebe874 | 12123 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
d6bc6245 | 12124 | With a constant we always use the latter case. |
76b3015f | 12125 | |
d6bc6245 TS |
12126 | With 64bit address space and no base register and $at usable, |
12127 | we want | |
12128 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
12129 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
12130 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
12131 | dsll32 $tempreg,0 | |
12132 | daddu $tempreg,$at | |
c0ebe874 | 12133 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
d6bc6245 TS |
12134 | If we have a base register, we want |
12135 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
12136 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
12137 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
12138 | daddu $at,$breg | |
12139 | dsll32 $tempreg,0 | |
12140 | daddu $tempreg,$at | |
c0ebe874 | 12141 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
d6bc6245 TS |
12142 | |
12143 | Without $at we can't generate the optimal path for superscalar | |
12144 | processors here since this would require two temporary registers. | |
12145 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
12146 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
12147 | dsll $tempreg,16 | |
12148 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
12149 | dsll $tempreg,16 | |
c0ebe874 | 12150 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
d6bc6245 TS |
12151 | If we have a base register, we want |
12152 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
12153 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
12154 | dsll $tempreg,16 | |
12155 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
12156 | dsll $tempreg,16 | |
12157 | daddu $tempreg,$tempreg,$breg | |
c0ebe874 | 12158 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
6373ee54 | 12159 | |
6caf9ef4 | 12160 | For GP relative symbols in 64bit address space we can use |
aed1a261 RS |
12161 | the same sequence as in 32bit address space. */ |
12162 | if (HAVE_64BIT_SYMBOLS) | |
d6bc6245 | 12163 | { |
aed1a261 | 12164 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 TS |
12165 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
12166 | { | |
12167 | relax_start (offset_expr.X_add_symbol); | |
12168 | if (breg == 0) | |
12169 | { | |
c0ebe874 | 12170 | macro_build (&offset_expr, s, fmt, op[0], |
6caf9ef4 TS |
12171 | BFD_RELOC_GPREL16, mips_gp_register); |
12172 | } | |
12173 | else | |
12174 | { | |
12175 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
12176 | tempreg, breg, mips_gp_register); | |
c0ebe874 | 12177 | macro_build (&offset_expr, s, fmt, op[0], |
6caf9ef4 TS |
12178 | BFD_RELOC_GPREL16, tempreg); |
12179 | } | |
12180 | relax_switch (); | |
12181 | } | |
d6bc6245 | 12182 | |
741fe287 | 12183 | if (used_at == 0 && mips_opts.at) |
d6bc6245 | 12184 | { |
df58fc94 | 12185 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb | 12186 | BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 12187 | macro_build (&offset_expr, "lui", LUI_FMT, AT, |
67c0d1eb RS |
12188 | BFD_RELOC_HI16_S); |
12189 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
12190 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 12191 | if (breg != 0) |
67c0d1eb | 12192 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
df58fc94 | 12193 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb | 12194 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
c0ebe874 | 12195 | macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, |
67c0d1eb | 12196 | tempreg); |
d6bc6245 TS |
12197 | used_at = 1; |
12198 | } | |
12199 | else | |
12200 | { | |
df58fc94 | 12201 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb RS |
12202 | BFD_RELOC_MIPS_HIGHEST); |
12203 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
12204 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 12205 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb RS |
12206 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, |
12207 | tempreg, BFD_RELOC_HI16_S); | |
df58fc94 | 12208 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
d6bc6245 | 12209 | if (breg != 0) |
67c0d1eb | 12210 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 12211 | tempreg, tempreg, breg); |
c0ebe874 | 12212 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12213 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 12214 | } |
6caf9ef4 TS |
12215 | |
12216 | if (mips_relax.sequence) | |
12217 | relax_end (); | |
8fc2e39e | 12218 | break; |
d6bc6245 | 12219 | } |
256ab948 | 12220 | |
252b5132 RH |
12221 | if (breg == 0) |
12222 | { | |
67c0d1eb | 12223 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 12224 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 12225 | { |
4d7206a2 | 12226 | relax_start (offset_expr.X_add_symbol); |
c0ebe874 | 12227 | macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_GPREL16, |
67c0d1eb | 12228 | mips_gp_register); |
4d7206a2 | 12229 | relax_switch (); |
252b5132 | 12230 | } |
67c0d1eb | 12231 | macro_build_lui (&offset_expr, tempreg); |
c0ebe874 | 12232 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12233 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
12234 | if (mips_relax.sequence) |
12235 | relax_end (); | |
252b5132 RH |
12236 | } |
12237 | else | |
12238 | { | |
67c0d1eb | 12239 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 12240 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 12241 | { |
4d7206a2 | 12242 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 12243 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12244 | tempreg, breg, mips_gp_register); |
c0ebe874 | 12245 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12246 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 12247 | relax_switch (); |
252b5132 | 12248 | } |
67c0d1eb RS |
12249 | macro_build_lui (&offset_expr, tempreg); |
12250 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 12251 | tempreg, tempreg, breg); |
c0ebe874 | 12252 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12253 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
12254 | if (mips_relax.sequence) |
12255 | relax_end (); | |
252b5132 RH |
12256 | } |
12257 | } | |
0a44bf69 | 12258 | else if (!mips_big_got) |
252b5132 | 12259 | { |
ed6fb7bd | 12260 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 12261 | |
252b5132 RH |
12262 | /* If this is a reference to an external symbol, we want |
12263 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
12264 | nop | |
c0ebe874 | 12265 | <op> op[0],0($tempreg) |
252b5132 RH |
12266 | Otherwise we want |
12267 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
12268 | nop | |
12269 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
c0ebe874 | 12270 | <op> op[0],0($tempreg) |
f5040a92 AO |
12271 | |
12272 | For NewABI, we want | |
12273 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
c0ebe874 | 12274 | <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) |
f5040a92 | 12275 | |
252b5132 RH |
12276 | If there is a base register, we add it to $tempreg before |
12277 | the <op>. If there is a constant, we stick it in the | |
12278 | <op> instruction. We don't handle constants larger than | |
12279 | 16 bits, because we have no way to load the upper 16 bits | |
12280 | (actually, we could handle them for the subset of cases | |
12281 | in which we are not using $at). */ | |
9c2799c2 | 12282 | gas_assert (offset_expr.X_op == O_symbol); |
f5040a92 AO |
12283 | if (HAVE_NEWABI) |
12284 | { | |
67c0d1eb RS |
12285 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
12286 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 12287 | if (breg != 0) |
67c0d1eb | 12288 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12289 | tempreg, tempreg, breg); |
c0ebe874 | 12290 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12291 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
12292 | break; |
12293 | } | |
252b5132 RH |
12294 | expr1.X_add_number = offset_expr.X_add_number; |
12295 | offset_expr.X_add_number = 0; | |
12296 | if (expr1.X_add_number < -0x8000 | |
12297 | || expr1.X_add_number >= 0x8000) | |
12298 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
12299 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
12300 | lw_reloc_type, mips_gp_register); | |
269137b2 | 12301 | load_delay_nop (); |
4d7206a2 RS |
12302 | relax_start (offset_expr.X_add_symbol); |
12303 | relax_switch (); | |
67c0d1eb RS |
12304 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
12305 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 12306 | relax_end (); |
252b5132 | 12307 | if (breg != 0) |
67c0d1eb | 12308 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12309 | tempreg, tempreg, breg); |
c0ebe874 | 12310 | macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg); |
252b5132 | 12311 | } |
0a44bf69 | 12312 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 12313 | { |
67c0d1eb | 12314 | int gpdelay; |
252b5132 RH |
12315 | |
12316 | /* If this is a reference to an external symbol, we want | |
12317 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
12318 | addu $tempreg,$tempreg,$gp | |
12319 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
c0ebe874 | 12320 | <op> op[0],0($tempreg) |
252b5132 RH |
12321 | Otherwise we want |
12322 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
12323 | nop | |
12324 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
c0ebe874 | 12325 | <op> op[0],0($tempreg) |
252b5132 RH |
12326 | If there is a base register, we add it to $tempreg before |
12327 | the <op>. If there is a constant, we stick it in the | |
12328 | <op> instruction. We don't handle constants larger than | |
12329 | 16 bits, because we have no way to load the upper 16 bits | |
12330 | (actually, we could handle them for the subset of cases | |
f5040a92 | 12331 | in which we are not using $at). */ |
9c2799c2 | 12332 | gas_assert (offset_expr.X_op == O_symbol); |
252b5132 RH |
12333 | expr1.X_add_number = offset_expr.X_add_number; |
12334 | offset_expr.X_add_number = 0; | |
12335 | if (expr1.X_add_number < -0x8000 | |
12336 | || expr1.X_add_number >= 0x8000) | |
12337 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 12338 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 12339 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 12340 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 12341 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
12342 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
12343 | mips_gp_register); | |
12344 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
12345 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 12346 | relax_switch (); |
67c0d1eb RS |
12347 | if (gpdelay) |
12348 | macro_build (NULL, "nop", ""); | |
12349 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
12350 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 12351 | load_delay_nop (); |
67c0d1eb RS |
12352 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
12353 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
12354 | relax_end (); |
12355 | ||
252b5132 | 12356 | if (breg != 0) |
67c0d1eb | 12357 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12358 | tempreg, tempreg, breg); |
c0ebe874 | 12359 | macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg); |
252b5132 | 12360 | } |
0a44bf69 | 12361 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 12362 | { |
f5040a92 AO |
12363 | /* If this is a reference to an external symbol, we want |
12364 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
12365 | add $tempreg,$tempreg,$gp | |
12366 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
c0ebe874 | 12367 | <op> op[0],<ofst>($tempreg) |
f5040a92 AO |
12368 | Otherwise, for local symbols, we want: |
12369 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
c0ebe874 | 12370 | <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ |
9c2799c2 | 12371 | gas_assert (offset_expr.X_op == O_symbol); |
4d7206a2 | 12372 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
12373 | offset_expr.X_add_number = 0; |
12374 | if (expr1.X_add_number < -0x8000 | |
12375 | || expr1.X_add_number >= 0x8000) | |
12376 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 12377 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 12378 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 12379 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
12380 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
12381 | mips_gp_register); | |
12382 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
12383 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 12384 | if (breg != 0) |
67c0d1eb | 12385 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12386 | tempreg, tempreg, breg); |
c0ebe874 | 12387 | macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg); |
684022ea | 12388 | |
4d7206a2 | 12389 | relax_switch (); |
f5040a92 | 12390 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
12391 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
12392 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 12393 | if (breg != 0) |
67c0d1eb | 12394 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12395 | tempreg, tempreg, breg); |
c0ebe874 | 12396 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12397 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 12398 | relax_end (); |
f5040a92 | 12399 | } |
252b5132 RH |
12400 | else |
12401 | abort (); | |
12402 | ||
252b5132 RH |
12403 | break; |
12404 | ||
833794fc MR |
12405 | case M_JRADDIUSP: |
12406 | gas_assert (mips_opts.micromips); | |
12407 | gas_assert (mips_opts.insn32); | |
12408 | start_noreorder (); | |
12409 | macro_build (NULL, "jr", "s", RA); | |
c0ebe874 | 12410 | expr1.X_add_number = op[0] << 2; |
833794fc MR |
12411 | macro_build (&expr1, "addiu", "t,r,j", SP, SP, BFD_RELOC_LO16); |
12412 | end_noreorder (); | |
12413 | break; | |
12414 | ||
12415 | case M_JRC: | |
12416 | gas_assert (mips_opts.micromips); | |
12417 | gas_assert (mips_opts.insn32); | |
c0ebe874 | 12418 | macro_build (NULL, "jr", "s", op[0]); |
833794fc MR |
12419 | if (mips_opts.noreorder) |
12420 | macro_build (NULL, "nop", ""); | |
12421 | break; | |
12422 | ||
252b5132 RH |
12423 | case M_LI: |
12424 | case M_LI_S: | |
c0ebe874 | 12425 | load_register (op[0], &imm_expr, 0); |
8fc2e39e | 12426 | break; |
252b5132 RH |
12427 | |
12428 | case M_DLI: | |
c0ebe874 | 12429 | load_register (op[0], &imm_expr, 1); |
8fc2e39e | 12430 | break; |
252b5132 RH |
12431 | |
12432 | case M_LI_SS: | |
12433 | if (imm_expr.X_op == O_constant) | |
12434 | { | |
8fc2e39e | 12435 | used_at = 1; |
67c0d1eb | 12436 | load_register (AT, &imm_expr, 0); |
c0ebe874 | 12437 | macro_build (NULL, "mtc1", "t,G", AT, op[0]); |
252b5132 RH |
12438 | break; |
12439 | } | |
12440 | else | |
12441 | { | |
b0e6f033 RS |
12442 | gas_assert (imm_expr.X_op == O_absent |
12443 | && offset_expr.X_op == O_symbol | |
90ecf173 MR |
12444 | && strcmp (segment_name (S_GET_SEGMENT |
12445 | (offset_expr.X_add_symbol)), | |
12446 | ".lit4") == 0 | |
12447 | && offset_expr.X_add_number == 0); | |
c0ebe874 | 12448 | macro_build (&offset_expr, "lwc1", "T,o(b)", op[0], |
17a2f251 | 12449 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 12450 | break; |
252b5132 RH |
12451 | } |
12452 | ||
12453 | case M_LI_D: | |
ca4e0257 RS |
12454 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
12455 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
12456 | order 32 bits of the value and the low order 32 bits are either | |
12457 | zero or in OFFSET_EXPR. */ | |
b0e6f033 | 12458 | if (imm_expr.X_op == O_constant) |
252b5132 | 12459 | { |
bad1aba3 | 12460 | if (GPR_SIZE == 64) |
c0ebe874 | 12461 | load_register (op[0], &imm_expr, 1); |
252b5132 RH |
12462 | else |
12463 | { | |
12464 | int hreg, lreg; | |
12465 | ||
12466 | if (target_big_endian) | |
12467 | { | |
c0ebe874 RS |
12468 | hreg = op[0]; |
12469 | lreg = op[0] + 1; | |
252b5132 RH |
12470 | } |
12471 | else | |
12472 | { | |
c0ebe874 RS |
12473 | hreg = op[0] + 1; |
12474 | lreg = op[0]; | |
252b5132 RH |
12475 | } |
12476 | ||
12477 | if (hreg <= 31) | |
67c0d1eb | 12478 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
12479 | if (lreg <= 31) |
12480 | { | |
12481 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 12482 | move_register (lreg, 0); |
252b5132 RH |
12483 | else |
12484 | { | |
9c2799c2 | 12485 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb | 12486 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
12487 | } |
12488 | } | |
12489 | } | |
8fc2e39e | 12490 | break; |
252b5132 | 12491 | } |
b0e6f033 | 12492 | gas_assert (imm_expr.X_op == O_absent); |
252b5132 RH |
12493 | |
12494 | /* We know that sym is in the .rdata section. First we get the | |
12495 | upper 16 bits of the address. */ | |
12496 | if (mips_pic == NO_PIC) | |
12497 | { | |
67c0d1eb | 12498 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 12499 | used_at = 1; |
252b5132 | 12500 | } |
0a44bf69 | 12501 | else |
252b5132 | 12502 | { |
67c0d1eb RS |
12503 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
12504 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 12505 | used_at = 1; |
252b5132 | 12506 | } |
bdaaa2e1 | 12507 | |
252b5132 | 12508 | /* Now we load the register(s). */ |
bad1aba3 | 12509 | if (GPR_SIZE == 64) |
8fc2e39e TS |
12510 | { |
12511 | used_at = 1; | |
c0ebe874 RS |
12512 | macro_build (&offset_expr, "ld", "t,o(b)", op[0], |
12513 | BFD_RELOC_LO16, AT); | |
8fc2e39e | 12514 | } |
252b5132 RH |
12515 | else |
12516 | { | |
8fc2e39e | 12517 | used_at = 1; |
c0ebe874 RS |
12518 | macro_build (&offset_expr, "lw", "t,o(b)", op[0], |
12519 | BFD_RELOC_LO16, AT); | |
12520 | if (op[0] != RA) | |
252b5132 RH |
12521 | { |
12522 | /* FIXME: How in the world do we deal with the possible | |
12523 | overflow here? */ | |
12524 | offset_expr.X_add_number += 4; | |
67c0d1eb | 12525 | macro_build (&offset_expr, "lw", "t,o(b)", |
c0ebe874 | 12526 | op[0] + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
12527 | } |
12528 | } | |
252b5132 RH |
12529 | break; |
12530 | ||
12531 | case M_LI_DD: | |
ca4e0257 RS |
12532 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
12533 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
12534 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
12535 | the value and the low order 32 bits are either zero or in | |
12536 | OFFSET_EXPR. */ | |
b0e6f033 | 12537 | if (imm_expr.X_op == O_constant) |
252b5132 | 12538 | { |
8fc2e39e | 12539 | used_at = 1; |
bad1aba3 | 12540 | load_register (AT, &imm_expr, FPR_SIZE == 64); |
351cdf24 MF |
12541 | if (FPR_SIZE == 64 && GPR_SIZE == 64) |
12542 | macro_build (NULL, "dmtc1", "t,S", AT, op[0]); | |
252b5132 RH |
12543 | else |
12544 | { | |
351cdf24 MF |
12545 | if (ISA_HAS_MXHC1 (mips_opts.isa)) |
12546 | macro_build (NULL, "mthc1", "t,G", AT, op[0]); | |
12547 | else if (FPR_SIZE != 32) | |
12548 | as_bad (_("Unable to generate `%s' compliant code " | |
12549 | "without mthc1"), | |
12550 | (FPR_SIZE == 64) ? "fp64" : "fpxx"); | |
12551 | else | |
12552 | macro_build (NULL, "mtc1", "t,G", AT, op[0] + 1); | |
252b5132 | 12553 | if (offset_expr.X_op == O_absent) |
c0ebe874 | 12554 | macro_build (NULL, "mtc1", "t,G", 0, op[0]); |
252b5132 RH |
12555 | else |
12556 | { | |
9c2799c2 | 12557 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb | 12558 | load_register (AT, &offset_expr, 0); |
c0ebe874 | 12559 | macro_build (NULL, "mtc1", "t,G", AT, op[0]); |
252b5132 RH |
12560 | } |
12561 | } | |
12562 | break; | |
12563 | } | |
12564 | ||
b0e6f033 RS |
12565 | gas_assert (imm_expr.X_op == O_absent |
12566 | && offset_expr.X_op == O_symbol | |
90ecf173 | 12567 | && offset_expr.X_add_number == 0); |
252b5132 RH |
12568 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); |
12569 | if (strcmp (s, ".lit8") == 0) | |
134c0c8b MR |
12570 | { |
12571 | op[2] = mips_gp_register; | |
f2ae14a1 RS |
12572 | offset_reloc[0] = BFD_RELOC_MIPS_LITERAL; |
12573 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
12574 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
12575 | } |
12576 | else | |
12577 | { | |
9c2799c2 | 12578 | gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
8fc2e39e | 12579 | used_at = 1; |
0a44bf69 | 12580 | if (mips_pic != NO_PIC) |
67c0d1eb RS |
12581 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
12582 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
12583 | else |
12584 | { | |
12585 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 12586 | macro_build_lui (&offset_expr, AT); |
252b5132 | 12587 | } |
bdaaa2e1 | 12588 | |
c0ebe874 | 12589 | op[2] = AT; |
f2ae14a1 RS |
12590 | offset_reloc[0] = BFD_RELOC_LO16; |
12591 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
12592 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
134c0c8b | 12593 | } |
f2ae14a1 RS |
12594 | align = 8; |
12595 | /* Fall through */ | |
c4a68bea | 12596 | |
252b5132 RH |
12597 | case M_L_DAB: |
12598 | /* | |
12599 | * The MIPS assembler seems to check for X_add_number not | |
12600 | * being double aligned and generating: | |
12601 | * lui at,%hi(foo+1) | |
12602 | * addu at,at,v1 | |
12603 | * addiu at,at,%lo(foo+1) | |
12604 | * lwc1 f2,0(at) | |
12605 | * lwc1 f3,4(at) | |
12606 | * But, the resulting address is the same after relocation so why | |
12607 | * generate the extra instruction? | |
12608 | */ | |
bdaaa2e1 | 12609 | /* Itbl support may require additional care here. */ |
252b5132 | 12610 | coproc = 1; |
df58fc94 | 12611 | fmt = "T,o(b)"; |
0aa27725 | 12612 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch)) |
252b5132 RH |
12613 | { |
12614 | s = "ldc1"; | |
df58fc94 | 12615 | goto ld_st; |
252b5132 | 12616 | } |
252b5132 | 12617 | s = "lwc1"; |
252b5132 RH |
12618 | goto ldd_std; |
12619 | ||
12620 | case M_S_DAB: | |
df58fc94 RS |
12621 | gas_assert (!mips_opts.micromips); |
12622 | /* Itbl support may require additional care here. */ | |
12623 | coproc = 1; | |
12624 | fmt = "T,o(b)"; | |
0aa27725 | 12625 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch)) |
252b5132 RH |
12626 | { |
12627 | s = "sdc1"; | |
df58fc94 | 12628 | goto ld_st; |
252b5132 | 12629 | } |
252b5132 | 12630 | s = "swc1"; |
252b5132 RH |
12631 | goto ldd_std; |
12632 | ||
e407c74b NC |
12633 | case M_LQ_AB: |
12634 | fmt = "t,o(b)"; | |
12635 | s = "lq"; | |
12636 | goto ld; | |
12637 | ||
12638 | case M_SQ_AB: | |
12639 | fmt = "t,o(b)"; | |
12640 | s = "sq"; | |
12641 | goto ld_st; | |
12642 | ||
252b5132 | 12643 | case M_LD_AB: |
df58fc94 | 12644 | fmt = "t,o(b)"; |
bad1aba3 | 12645 | if (GPR_SIZE == 64) |
252b5132 RH |
12646 | { |
12647 | s = "ld"; | |
12648 | goto ld; | |
12649 | } | |
252b5132 | 12650 | s = "lw"; |
252b5132 RH |
12651 | goto ldd_std; |
12652 | ||
12653 | case M_SD_AB: | |
df58fc94 | 12654 | fmt = "t,o(b)"; |
bad1aba3 | 12655 | if (GPR_SIZE == 64) |
252b5132 RH |
12656 | { |
12657 | s = "sd"; | |
df58fc94 | 12658 | goto ld_st; |
252b5132 | 12659 | } |
252b5132 | 12660 | s = "sw"; |
252b5132 RH |
12661 | |
12662 | ldd_std: | |
f2ae14a1 RS |
12663 | /* Even on a big endian machine $fn comes before $fn+1. We have |
12664 | to adjust when loading from memory. We set coproc if we must | |
12665 | load $fn+1 first. */ | |
12666 | /* Itbl support may require additional care here. */ | |
12667 | if (!target_big_endian) | |
12668 | coproc = 0; | |
12669 | ||
c0ebe874 | 12670 | breg = op[2]; |
f2ae14a1 RS |
12671 | if (small_offset_p (0, align, 16)) |
12672 | { | |
12673 | ep = &offset_expr; | |
12674 | if (!small_offset_p (4, align, 16)) | |
12675 | { | |
12676 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT, breg, | |
12677 | -1, offset_reloc[0], offset_reloc[1], | |
12678 | offset_reloc[2]); | |
12679 | expr1.X_add_number = 0; | |
12680 | ep = &expr1; | |
12681 | breg = AT; | |
12682 | used_at = 1; | |
12683 | offset_reloc[0] = BFD_RELOC_LO16; | |
12684 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
12685 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
12686 | } | |
c0ebe874 | 12687 | if (strcmp (s, "lw") == 0 && op[0] == breg) |
f2ae14a1 RS |
12688 | { |
12689 | ep->X_add_number += 4; | |
c0ebe874 | 12690 | macro_build (ep, s, fmt, op[0] + 1, -1, offset_reloc[0], |
f2ae14a1 RS |
12691 | offset_reloc[1], offset_reloc[2], breg); |
12692 | ep->X_add_number -= 4; | |
c0ebe874 | 12693 | macro_build (ep, s, fmt, op[0], -1, offset_reloc[0], |
f2ae14a1 RS |
12694 | offset_reloc[1], offset_reloc[2], breg); |
12695 | } | |
12696 | else | |
12697 | { | |
c0ebe874 | 12698 | macro_build (ep, s, fmt, coproc ? op[0] + 1 : op[0], -1, |
f2ae14a1 RS |
12699 | offset_reloc[0], offset_reloc[1], offset_reloc[2], |
12700 | breg); | |
12701 | ep->X_add_number += 4; | |
c0ebe874 | 12702 | macro_build (ep, s, fmt, coproc ? op[0] : op[0] + 1, -1, |
f2ae14a1 RS |
12703 | offset_reloc[0], offset_reloc[1], offset_reloc[2], |
12704 | breg); | |
12705 | } | |
12706 | break; | |
12707 | } | |
12708 | ||
252b5132 RH |
12709 | if (offset_expr.X_op != O_symbol |
12710 | && offset_expr.X_op != O_constant) | |
12711 | { | |
1661c76c | 12712 | as_bad (_("expression too complex")); |
252b5132 RH |
12713 | offset_expr.X_op = O_constant; |
12714 | } | |
12715 | ||
2051e8c4 MR |
12716 | if (HAVE_32BIT_ADDRESSES |
12717 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
12718 | { |
12719 | char value [32]; | |
12720 | ||
12721 | sprintf_vma (value, offset_expr.X_add_number); | |
1661c76c | 12722 | as_bad (_("number (0x%s) larger than 32 bits"), value); |
55e08f71 | 12723 | } |
2051e8c4 | 12724 | |
90ecf173 | 12725 | if (mips_pic == NO_PIC || offset_expr.X_op == O_constant) |
252b5132 RH |
12726 | { |
12727 | /* If this is a reference to a GP relative symbol, we want | |
c0ebe874 RS |
12728 | <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16) |
12729 | <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
12730 | If we have a base register, we use this |
12731 | addu $at,$breg,$gp | |
c0ebe874 RS |
12732 | <op> op[0],<sym>($at) (BFD_RELOC_GPREL16) |
12733 | <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
12734 | If this is not a GP relative symbol, we want |
12735 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
c0ebe874 RS |
12736 | <op> op[0],<sym>($at) (BFD_RELOC_LO16) |
12737 | <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16) | |
252b5132 RH |
12738 | If there is a base register, we add it to $at after the |
12739 | lui instruction. If there is a constant, we always use | |
12740 | the last case. */ | |
39a59cf8 MR |
12741 | if (offset_expr.X_op == O_symbol |
12742 | && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 12743 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 12744 | { |
4d7206a2 | 12745 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
12746 | if (breg == 0) |
12747 | { | |
c9914766 | 12748 | tempreg = mips_gp_register; |
252b5132 RH |
12749 | } |
12750 | else | |
12751 | { | |
67c0d1eb | 12752 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12753 | AT, breg, mips_gp_register); |
252b5132 | 12754 | tempreg = AT; |
252b5132 RH |
12755 | used_at = 1; |
12756 | } | |
12757 | ||
beae10d5 | 12758 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12759 | macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], |
17a2f251 | 12760 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
12761 | offset_expr.X_add_number += 4; |
12762 | ||
12763 | /* Set mips_optimize to 2 to avoid inserting an | |
12764 | undesired nop. */ | |
12765 | hold_mips_optimize = mips_optimize; | |
12766 | mips_optimize = 2; | |
beae10d5 | 12767 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12768 | macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, |
17a2f251 | 12769 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
12770 | mips_optimize = hold_mips_optimize; |
12771 | ||
4d7206a2 | 12772 | relax_switch (); |
252b5132 | 12773 | |
0970e49e | 12774 | offset_expr.X_add_number -= 4; |
252b5132 | 12775 | } |
8fc2e39e | 12776 | used_at = 1; |
f2ae14a1 RS |
12777 | if (offset_high_part (offset_expr.X_add_number, 16) |
12778 | != offset_high_part (offset_expr.X_add_number + 4, 16)) | |
12779 | { | |
12780 | load_address (AT, &offset_expr, &used_at); | |
12781 | offset_expr.X_op = O_constant; | |
12782 | offset_expr.X_add_number = 0; | |
12783 | } | |
12784 | else | |
12785 | macro_build_lui (&offset_expr, AT); | |
252b5132 | 12786 | if (breg != 0) |
67c0d1eb | 12787 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 12788 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12789 | macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], |
17a2f251 | 12790 | BFD_RELOC_LO16, AT); |
252b5132 RH |
12791 | /* FIXME: How do we handle overflow here? */ |
12792 | offset_expr.X_add_number += 4; | |
beae10d5 | 12793 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12794 | macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, |
17a2f251 | 12795 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
12796 | if (mips_relax.sequence) |
12797 | relax_end (); | |
bdaaa2e1 | 12798 | } |
0a44bf69 | 12799 | else if (!mips_big_got) |
252b5132 | 12800 | { |
252b5132 RH |
12801 | /* If this is a reference to an external symbol, we want |
12802 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
12803 | nop | |
c0ebe874 RS |
12804 | <op> op[0],0($at) |
12805 | <op> op[0]+1,4($at) | |
252b5132 RH |
12806 | Otherwise we want |
12807 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
12808 | nop | |
c0ebe874 RS |
12809 | <op> op[0],<sym>($at) (BFD_RELOC_LO16) |
12810 | <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16) | |
252b5132 RH |
12811 | If there is a base register we add it to $at before the |
12812 | lwc1 instructions. If there is a constant we include it | |
12813 | in the lwc1 instructions. */ | |
12814 | used_at = 1; | |
12815 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
12816 | if (expr1.X_add_number < -0x8000 |
12817 | || expr1.X_add_number >= 0x8000 - 4) | |
12818 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 12819 | load_got_offset (AT, &offset_expr); |
269137b2 | 12820 | load_delay_nop (); |
252b5132 | 12821 | if (breg != 0) |
67c0d1eb | 12822 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
12823 | |
12824 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
12825 | nop. */ | |
12826 | hold_mips_optimize = mips_optimize; | |
12827 | mips_optimize = 2; | |
4d7206a2 | 12828 | |
beae10d5 | 12829 | /* Itbl support may require additional care here. */ |
4d7206a2 | 12830 | relax_start (offset_expr.X_add_symbol); |
c0ebe874 | 12831 | macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0], |
67c0d1eb | 12832 | BFD_RELOC_LO16, AT); |
4d7206a2 | 12833 | expr1.X_add_number += 4; |
c0ebe874 | 12834 | macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1, |
67c0d1eb | 12835 | BFD_RELOC_LO16, AT); |
4d7206a2 | 12836 | relax_switch (); |
c0ebe874 | 12837 | macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], |
67c0d1eb | 12838 | BFD_RELOC_LO16, AT); |
4d7206a2 | 12839 | offset_expr.X_add_number += 4; |
c0ebe874 | 12840 | macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, |
67c0d1eb | 12841 | BFD_RELOC_LO16, AT); |
4d7206a2 | 12842 | relax_end (); |
252b5132 | 12843 | |
4d7206a2 | 12844 | mips_optimize = hold_mips_optimize; |
252b5132 | 12845 | } |
0a44bf69 | 12846 | else if (mips_big_got) |
252b5132 | 12847 | { |
67c0d1eb | 12848 | int gpdelay; |
252b5132 RH |
12849 | |
12850 | /* If this is a reference to an external symbol, we want | |
12851 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
12852 | addu $at,$at,$gp | |
12853 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
12854 | nop | |
c0ebe874 RS |
12855 | <op> op[0],0($at) |
12856 | <op> op[0]+1,4($at) | |
252b5132 RH |
12857 | Otherwise we want |
12858 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
12859 | nop | |
c0ebe874 RS |
12860 | <op> op[0],<sym>($at) (BFD_RELOC_LO16) |
12861 | <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16) | |
252b5132 RH |
12862 | If there is a base register we add it to $at before the |
12863 | lwc1 instructions. If there is a constant we include it | |
12864 | in the lwc1 instructions. */ | |
12865 | used_at = 1; | |
12866 | expr1.X_add_number = offset_expr.X_add_number; | |
12867 | offset_expr.X_add_number = 0; | |
12868 | if (expr1.X_add_number < -0x8000 | |
12869 | || expr1.X_add_number >= 0x8000 - 4) | |
12870 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 12871 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 12872 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 12873 | macro_build (&offset_expr, "lui", LUI_FMT, |
67c0d1eb RS |
12874 | AT, BFD_RELOC_MIPS_GOT_HI16); |
12875 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 12876 | AT, AT, mips_gp_register); |
67c0d1eb | 12877 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 12878 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 12879 | load_delay_nop (); |
252b5132 | 12880 | if (breg != 0) |
67c0d1eb | 12881 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 12882 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12883 | macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0], |
17a2f251 | 12884 | BFD_RELOC_LO16, AT); |
252b5132 RH |
12885 | expr1.X_add_number += 4; |
12886 | ||
12887 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
12888 | nop. */ | |
12889 | hold_mips_optimize = mips_optimize; | |
12890 | mips_optimize = 2; | |
beae10d5 | 12891 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12892 | macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1, |
17a2f251 | 12893 | BFD_RELOC_LO16, AT); |
252b5132 RH |
12894 | mips_optimize = hold_mips_optimize; |
12895 | expr1.X_add_number -= 4; | |
12896 | ||
4d7206a2 RS |
12897 | relax_switch (); |
12898 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
12899 | if (gpdelay) |
12900 | macro_build (NULL, "nop", ""); | |
12901 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
12902 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 12903 | load_delay_nop (); |
252b5132 | 12904 | if (breg != 0) |
67c0d1eb | 12905 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 12906 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12907 | macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], |
67c0d1eb | 12908 | BFD_RELOC_LO16, AT); |
4d7206a2 | 12909 | offset_expr.X_add_number += 4; |
252b5132 RH |
12910 | |
12911 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
12912 | nop. */ | |
12913 | hold_mips_optimize = mips_optimize; | |
12914 | mips_optimize = 2; | |
beae10d5 | 12915 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12916 | macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, |
67c0d1eb | 12917 | BFD_RELOC_LO16, AT); |
252b5132 | 12918 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 12919 | relax_end (); |
252b5132 | 12920 | } |
252b5132 RH |
12921 | else |
12922 | abort (); | |
12923 | ||
252b5132 | 12924 | break; |
3739860c | 12925 | |
dd6a37e7 | 12926 | case M_SAA_AB: |
dd6a37e7 | 12927 | s = "saa"; |
0db377d0 | 12928 | goto saa_saad; |
dd6a37e7 | 12929 | case M_SAAD_AB: |
dd6a37e7 | 12930 | s = "saad"; |
0db377d0 MR |
12931 | saa_saad: |
12932 | gas_assert (!mips_opts.micromips); | |
7f3c4072 | 12933 | offbits = 0; |
dd6a37e7 AP |
12934 | fmt = "t,(b)"; |
12935 | goto ld_st; | |
12936 | ||
252b5132 RH |
12937 | /* New code added to support COPZ instructions. |
12938 | This code builds table entries out of the macros in mip_opcodes. | |
12939 | R4000 uses interlocks to handle coproc delays. | |
12940 | Other chips (like the R3000) require nops to be inserted for delays. | |
12941 | ||
f72c8c98 | 12942 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
12943 | In order to fill delay slots for non-interlocked chips, |
12944 | we must have a way to specify delays based on the coprocessor. | |
12945 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
12946 | What are the side-effects of the cop instruction? | |
12947 | What cache support might we have and what are its effects? | |
12948 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 12949 | What registers are read/set/modified? |
252b5132 RH |
12950 | |
12951 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 12952 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
12953 | |
12954 | case M_COP0: | |
12955 | s = "c0"; | |
12956 | goto copz; | |
12957 | case M_COP1: | |
12958 | s = "c1"; | |
12959 | goto copz; | |
12960 | case M_COP2: | |
12961 | s = "c2"; | |
12962 | goto copz; | |
12963 | case M_COP3: | |
12964 | s = "c3"; | |
12965 | copz: | |
df58fc94 | 12966 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
12967 | /* For now we just do C (same as Cz). The parameter will be |
12968 | stored in insn_opcode by mips_ip. */ | |
c8276761 | 12969 | macro_build (NULL, s, "C", (int) ip->insn_opcode); |
8fc2e39e | 12970 | break; |
252b5132 | 12971 | |
ea1fb5dc | 12972 | case M_MOVE: |
c0ebe874 | 12973 | move_register (op[0], op[1]); |
8fc2e39e | 12974 | break; |
ea1fb5dc | 12975 | |
833794fc MR |
12976 | case M_MOVEP: |
12977 | gas_assert (mips_opts.micromips); | |
12978 | gas_assert (mips_opts.insn32); | |
c0ebe874 RS |
12979 | move_register (micromips_to_32_reg_h_map1[op[0]], |
12980 | micromips_to_32_reg_m_map[op[1]]); | |
12981 | move_register (micromips_to_32_reg_h_map2[op[0]], | |
12982 | micromips_to_32_reg_n_map[op[2]]); | |
833794fc MR |
12983 | break; |
12984 | ||
252b5132 RH |
12985 | case M_DMUL: |
12986 | dbl = 1; | |
1a0670f3 | 12987 | /* Fall through. */ |
252b5132 | 12988 | case M_MUL: |
e407c74b | 12989 | if (mips_opts.arch == CPU_R5900) |
c0ebe874 RS |
12990 | macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", op[0], op[1], |
12991 | op[2]); | |
e407c74b NC |
12992 | else |
12993 | { | |
c0ebe874 RS |
12994 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", op[1], op[2]); |
12995 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); | |
e407c74b | 12996 | } |
8fc2e39e | 12997 | break; |
252b5132 RH |
12998 | |
12999 | case M_DMUL_I: | |
13000 | dbl = 1; | |
1a0670f3 | 13001 | /* Fall through. */ |
252b5132 RH |
13002 | case M_MUL_I: |
13003 | /* The MIPS assembler some times generates shifts and adds. I'm | |
13004 | not trying to be that fancy. GCC should do this for us | |
13005 | anyway. */ | |
8fc2e39e | 13006 | used_at = 1; |
67c0d1eb | 13007 | load_register (AT, &imm_expr, dbl); |
c0ebe874 RS |
13008 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", op[1], AT); |
13009 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); | |
252b5132 RH |
13010 | break; |
13011 | ||
13012 | case M_DMULO_I: | |
13013 | dbl = 1; | |
1a0670f3 | 13014 | /* Fall through. */ |
252b5132 RH |
13015 | case M_MULO_I: |
13016 | imm = 1; | |
13017 | goto do_mulo; | |
13018 | ||
13019 | case M_DMULO: | |
13020 | dbl = 1; | |
1a0670f3 | 13021 | /* Fall through. */ |
252b5132 RH |
13022 | case M_MULO: |
13023 | do_mulo: | |
7d10b47d | 13024 | start_noreorder (); |
8fc2e39e | 13025 | used_at = 1; |
252b5132 | 13026 | if (imm) |
67c0d1eb | 13027 | load_register (AT, &imm_expr, dbl); |
c0ebe874 RS |
13028 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", |
13029 | op[1], imm ? AT : op[2]); | |
13030 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); | |
13031 | macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, op[0], op[0], 31); | |
df58fc94 | 13032 | macro_build (NULL, "mfhi", MFHL_FMT, AT); |
252b5132 | 13033 | if (mips_trap) |
c0ebe874 | 13034 | macro_build (NULL, "tne", TRAP_FMT, op[0], AT, 6); |
252b5132 RH |
13035 | else |
13036 | { | |
df58fc94 RS |
13037 | if (mips_opts.micromips) |
13038 | micromips_label_expr (&label_expr); | |
13039 | else | |
13040 | label_expr.X_add_number = 8; | |
c0ebe874 | 13041 | macro_build (&label_expr, "beq", "s,t,p", op[0], AT); |
a605d2b3 | 13042 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
13043 | macro_build (NULL, "break", BRK_FMT, 6); |
13044 | if (mips_opts.micromips) | |
13045 | micromips_add_label (); | |
252b5132 | 13046 | } |
7d10b47d | 13047 | end_noreorder (); |
c0ebe874 | 13048 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); |
252b5132 RH |
13049 | break; |
13050 | ||
13051 | case M_DMULOU_I: | |
13052 | dbl = 1; | |
1a0670f3 | 13053 | /* Fall through. */ |
252b5132 RH |
13054 | case M_MULOU_I: |
13055 | imm = 1; | |
13056 | goto do_mulou; | |
13057 | ||
13058 | case M_DMULOU: | |
13059 | dbl = 1; | |
1a0670f3 | 13060 | /* Fall through. */ |
252b5132 RH |
13061 | case M_MULOU: |
13062 | do_mulou: | |
7d10b47d | 13063 | start_noreorder (); |
8fc2e39e | 13064 | used_at = 1; |
252b5132 | 13065 | if (imm) |
67c0d1eb RS |
13066 | load_register (AT, &imm_expr, dbl); |
13067 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
c0ebe874 | 13068 | op[1], imm ? AT : op[2]); |
df58fc94 | 13069 | macro_build (NULL, "mfhi", MFHL_FMT, AT); |
c0ebe874 | 13070 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); |
252b5132 | 13071 | if (mips_trap) |
df58fc94 | 13072 | macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6); |
252b5132 RH |
13073 | else |
13074 | { | |
df58fc94 RS |
13075 | if (mips_opts.micromips) |
13076 | micromips_label_expr (&label_expr); | |
13077 | else | |
13078 | label_expr.X_add_number = 8; | |
13079 | macro_build (&label_expr, "beq", "s,t,p", AT, ZERO); | |
a605d2b3 | 13080 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
13081 | macro_build (NULL, "break", BRK_FMT, 6); |
13082 | if (mips_opts.micromips) | |
13083 | micromips_add_label (); | |
252b5132 | 13084 | } |
7d10b47d | 13085 | end_noreorder (); |
252b5132 RH |
13086 | break; |
13087 | ||
771c7ce4 | 13088 | case M_DROL: |
fef14a42 | 13089 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 13090 | { |
c0ebe874 | 13091 | if (op[0] == op[1]) |
82dd0097 CD |
13092 | { |
13093 | tempreg = AT; | |
13094 | used_at = 1; | |
13095 | } | |
13096 | else | |
c0ebe874 RS |
13097 | tempreg = op[0]; |
13098 | macro_build (NULL, "dnegu", "d,w", tempreg, op[2]); | |
13099 | macro_build (NULL, "drorv", "d,t,s", op[0], op[1], tempreg); | |
8fc2e39e | 13100 | break; |
82dd0097 | 13101 | } |
8fc2e39e | 13102 | used_at = 1; |
c0ebe874 RS |
13103 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]); |
13104 | macro_build (NULL, "dsrlv", "d,t,s", AT, op[1], AT); | |
13105 | macro_build (NULL, "dsllv", "d,t,s", op[0], op[1], op[2]); | |
13106 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 TS |
13107 | break; |
13108 | ||
252b5132 | 13109 | case M_ROL: |
fef14a42 | 13110 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 13111 | { |
c0ebe874 | 13112 | if (op[0] == op[1]) |
82dd0097 CD |
13113 | { |
13114 | tempreg = AT; | |
13115 | used_at = 1; | |
13116 | } | |
13117 | else | |
c0ebe874 RS |
13118 | tempreg = op[0]; |
13119 | macro_build (NULL, "negu", "d,w", tempreg, op[2]); | |
13120 | macro_build (NULL, "rorv", "d,t,s", op[0], op[1], tempreg); | |
8fc2e39e | 13121 | break; |
82dd0097 | 13122 | } |
8fc2e39e | 13123 | used_at = 1; |
c0ebe874 RS |
13124 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]); |
13125 | macro_build (NULL, "srlv", "d,t,s", AT, op[1], AT); | |
13126 | macro_build (NULL, "sllv", "d,t,s", op[0], op[1], op[2]); | |
13127 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
252b5132 RH |
13128 | break; |
13129 | ||
771c7ce4 TS |
13130 | case M_DROL_I: |
13131 | { | |
13132 | unsigned int rot; | |
e0471c16 TS |
13133 | const char *l; |
13134 | const char *rr; | |
771c7ce4 | 13135 | |
771c7ce4 | 13136 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 13137 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
13138 | { |
13139 | rot = (64 - rot) & 0x3f; | |
13140 | if (rot >= 32) | |
c0ebe874 | 13141 | macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32); |
60b63b72 | 13142 | else |
c0ebe874 | 13143 | macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot); |
8fc2e39e | 13144 | break; |
60b63b72 | 13145 | } |
483fc7cd | 13146 | if (rot == 0) |
483fc7cd | 13147 | { |
c0ebe874 | 13148 | macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0); |
8fc2e39e | 13149 | break; |
483fc7cd | 13150 | } |
82dd0097 | 13151 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
91d6fa6a | 13152 | rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 | 13153 | rot &= 0x1f; |
8fc2e39e | 13154 | used_at = 1; |
c0ebe874 RS |
13155 | macro_build (NULL, l, SHFT_FMT, AT, op[1], rot); |
13156 | macro_build (NULL, rr, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); | |
13157 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 TS |
13158 | } |
13159 | break; | |
13160 | ||
252b5132 | 13161 | case M_ROL_I: |
771c7ce4 TS |
13162 | { |
13163 | unsigned int rot; | |
13164 | ||
771c7ce4 | 13165 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 13166 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 13167 | { |
c0ebe874 RS |
13168 | macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], |
13169 | (32 - rot) & 0x1f); | |
8fc2e39e | 13170 | break; |
60b63b72 | 13171 | } |
483fc7cd | 13172 | if (rot == 0) |
483fc7cd | 13173 | { |
c0ebe874 | 13174 | macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0); |
8fc2e39e | 13175 | break; |
483fc7cd | 13176 | } |
8fc2e39e | 13177 | used_at = 1; |
c0ebe874 RS |
13178 | macro_build (NULL, "sll", SHFT_FMT, AT, op[1], rot); |
13179 | macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); | |
13180 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 TS |
13181 | } |
13182 | break; | |
13183 | ||
13184 | case M_DROR: | |
fef14a42 | 13185 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 13186 | { |
c0ebe874 | 13187 | macro_build (NULL, "drorv", "d,t,s", op[0], op[1], op[2]); |
8fc2e39e | 13188 | break; |
82dd0097 | 13189 | } |
8fc2e39e | 13190 | used_at = 1; |
c0ebe874 RS |
13191 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]); |
13192 | macro_build (NULL, "dsllv", "d,t,s", AT, op[1], AT); | |
13193 | macro_build (NULL, "dsrlv", "d,t,s", op[0], op[1], op[2]); | |
13194 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
252b5132 RH |
13195 | break; |
13196 | ||
13197 | case M_ROR: | |
fef14a42 | 13198 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 13199 | { |
c0ebe874 | 13200 | macro_build (NULL, "rorv", "d,t,s", op[0], op[1], op[2]); |
8fc2e39e | 13201 | break; |
82dd0097 | 13202 | } |
8fc2e39e | 13203 | used_at = 1; |
c0ebe874 RS |
13204 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]); |
13205 | macro_build (NULL, "sllv", "d,t,s", AT, op[1], AT); | |
13206 | macro_build (NULL, "srlv", "d,t,s", op[0], op[1], op[2]); | |
13207 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
252b5132 RH |
13208 | break; |
13209 | ||
771c7ce4 TS |
13210 | case M_DROR_I: |
13211 | { | |
13212 | unsigned int rot; | |
e0471c16 TS |
13213 | const char *l; |
13214 | const char *rr; | |
771c7ce4 | 13215 | |
771c7ce4 | 13216 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 13217 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
13218 | { |
13219 | if (rot >= 32) | |
c0ebe874 | 13220 | macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32); |
82dd0097 | 13221 | else |
c0ebe874 | 13222 | macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot); |
8fc2e39e | 13223 | break; |
82dd0097 | 13224 | } |
483fc7cd | 13225 | if (rot == 0) |
483fc7cd | 13226 | { |
c0ebe874 | 13227 | macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0); |
8fc2e39e | 13228 | break; |
483fc7cd | 13229 | } |
91d6fa6a | 13230 | rr = (rot < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 CD |
13231 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; |
13232 | rot &= 0x1f; | |
8fc2e39e | 13233 | used_at = 1; |
c0ebe874 RS |
13234 | macro_build (NULL, rr, SHFT_FMT, AT, op[1], rot); |
13235 | macro_build (NULL, l, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); | |
13236 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 TS |
13237 | } |
13238 | break; | |
13239 | ||
252b5132 | 13240 | case M_ROR_I: |
771c7ce4 TS |
13241 | { |
13242 | unsigned int rot; | |
13243 | ||
771c7ce4 | 13244 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 13245 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 13246 | { |
c0ebe874 | 13247 | macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], rot); |
8fc2e39e | 13248 | break; |
82dd0097 | 13249 | } |
483fc7cd | 13250 | if (rot == 0) |
483fc7cd | 13251 | { |
c0ebe874 | 13252 | macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0); |
8fc2e39e | 13253 | break; |
483fc7cd | 13254 | } |
8fc2e39e | 13255 | used_at = 1; |
c0ebe874 RS |
13256 | macro_build (NULL, "srl", SHFT_FMT, AT, op[1], rot); |
13257 | macro_build (NULL, "sll", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); | |
13258 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 | 13259 | } |
252b5132 RH |
13260 | break; |
13261 | ||
252b5132 | 13262 | case M_SEQ: |
c0ebe874 RS |
13263 | if (op[1] == 0) |
13264 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[2], BFD_RELOC_LO16); | |
13265 | else if (op[2] == 0) | |
13266 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16); | |
252b5132 RH |
13267 | else |
13268 | { | |
c0ebe874 RS |
13269 | macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]); |
13270 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16); | |
252b5132 | 13271 | } |
8fc2e39e | 13272 | break; |
252b5132 RH |
13273 | |
13274 | case M_SEQ_I: | |
b0e6f033 | 13275 | if (imm_expr.X_add_number == 0) |
252b5132 | 13276 | { |
c0ebe874 | 13277 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
8fc2e39e | 13278 | break; |
252b5132 | 13279 | } |
c0ebe874 | 13280 | if (op[1] == 0) |
252b5132 | 13281 | { |
1661c76c | 13282 | as_warn (_("instruction %s: result is always false"), |
252b5132 | 13283 | ip->insn_mo->name); |
c0ebe874 | 13284 | move_register (op[0], 0); |
8fc2e39e | 13285 | break; |
252b5132 | 13286 | } |
dd3cbb7e NC |
13287 | if (CPU_HAS_SEQ (mips_opts.arch) |
13288 | && -512 <= imm_expr.X_add_number | |
13289 | && imm_expr.X_add_number < 512) | |
13290 | { | |
c0ebe874 | 13291 | macro_build (NULL, "seqi", "t,r,+Q", op[0], op[1], |
750bdd57 | 13292 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
13293 | break; |
13294 | } | |
b0e6f033 | 13295 | if (imm_expr.X_add_number >= 0 |
252b5132 | 13296 | && imm_expr.X_add_number < 0x10000) |
c0ebe874 | 13297 | macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1], BFD_RELOC_LO16); |
b0e6f033 | 13298 | else if (imm_expr.X_add_number > -0x8000 |
252b5132 RH |
13299 | && imm_expr.X_add_number < 0) |
13300 | { | |
13301 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
bad1aba3 | 13302 | macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu", |
c0ebe874 | 13303 | "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
252b5132 | 13304 | } |
dd3cbb7e NC |
13305 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
13306 | { | |
13307 | used_at = 1; | |
bad1aba3 | 13308 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13309 | macro_build (NULL, "seq", "d,v,t", op[0], op[1], AT); |
dd3cbb7e NC |
13310 | break; |
13311 | } | |
252b5132 RH |
13312 | else |
13313 | { | |
bad1aba3 | 13314 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13315 | macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT); |
252b5132 RH |
13316 | used_at = 1; |
13317 | } | |
c0ebe874 | 13318 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16); |
8fc2e39e | 13319 | break; |
252b5132 | 13320 | |
c0ebe874 | 13321 | case M_SGE: /* X >= Y <==> not (X < Y) */ |
252b5132 RH |
13322 | s = "slt"; |
13323 | goto sge; | |
13324 | case M_SGEU: | |
13325 | s = "sltu"; | |
13326 | sge: | |
c0ebe874 RS |
13327 | macro_build (NULL, s, "d,v,t", op[0], op[1], op[2]); |
13328 | macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); | |
8fc2e39e | 13329 | break; |
252b5132 | 13330 | |
c0ebe874 | 13331 | case M_SGE_I: /* X >= I <==> not (X < I) */ |
252b5132 | 13332 | case M_SGEU_I: |
b0e6f033 | 13333 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 | 13334 | && imm_expr.X_add_number < 0x8000) |
c0ebe874 RS |
13335 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
13336 | op[0], op[1], BFD_RELOC_LO16); | |
252b5132 RH |
13337 | else |
13338 | { | |
bad1aba3 | 13339 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
67c0d1eb | 13340 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", |
c0ebe874 | 13341 | op[0], op[1], AT); |
252b5132 RH |
13342 | used_at = 1; |
13343 | } | |
c0ebe874 | 13344 | macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); |
8fc2e39e | 13345 | break; |
252b5132 | 13346 | |
c0ebe874 | 13347 | case M_SGT: /* X > Y <==> Y < X */ |
252b5132 RH |
13348 | s = "slt"; |
13349 | goto sgt; | |
13350 | case M_SGTU: | |
13351 | s = "sltu"; | |
13352 | sgt: | |
c0ebe874 | 13353 | macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]); |
8fc2e39e | 13354 | break; |
252b5132 | 13355 | |
c0ebe874 | 13356 | case M_SGT_I: /* X > I <==> I < X */ |
252b5132 RH |
13357 | s = "slt"; |
13358 | goto sgti; | |
13359 | case M_SGTU_I: | |
13360 | s = "sltu"; | |
13361 | sgti: | |
8fc2e39e | 13362 | used_at = 1; |
bad1aba3 | 13363 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13364 | macro_build (NULL, s, "d,v,t", op[0], AT, op[1]); |
252b5132 RH |
13365 | break; |
13366 | ||
c0ebe874 | 13367 | case M_SLE: /* X <= Y <==> Y >= X <==> not (Y < X) */ |
252b5132 RH |
13368 | s = "slt"; |
13369 | goto sle; | |
13370 | case M_SLEU: | |
13371 | s = "sltu"; | |
13372 | sle: | |
c0ebe874 RS |
13373 | macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]); |
13374 | macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); | |
8fc2e39e | 13375 | break; |
252b5132 | 13376 | |
c0ebe874 | 13377 | case M_SLE_I: /* X <= I <==> I >= X <==> not (I < X) */ |
252b5132 RH |
13378 | s = "slt"; |
13379 | goto slei; | |
13380 | case M_SLEU_I: | |
13381 | s = "sltu"; | |
13382 | slei: | |
8fc2e39e | 13383 | used_at = 1; |
bad1aba3 | 13384 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 RS |
13385 | macro_build (NULL, s, "d,v,t", op[0], AT, op[1]); |
13386 | macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); | |
252b5132 RH |
13387 | break; |
13388 | ||
13389 | case M_SLT_I: | |
b0e6f033 | 13390 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 RH |
13391 | && imm_expr.X_add_number < 0x8000) |
13392 | { | |
c0ebe874 RS |
13393 | macro_build (&imm_expr, "slti", "t,r,j", op[0], op[1], |
13394 | BFD_RELOC_LO16); | |
8fc2e39e | 13395 | break; |
252b5132 | 13396 | } |
8fc2e39e | 13397 | used_at = 1; |
bad1aba3 | 13398 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13399 | macro_build (NULL, "slt", "d,v,t", op[0], op[1], AT); |
252b5132 RH |
13400 | break; |
13401 | ||
13402 | case M_SLTU_I: | |
b0e6f033 | 13403 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 RH |
13404 | && imm_expr.X_add_number < 0x8000) |
13405 | { | |
c0ebe874 | 13406 | macro_build (&imm_expr, "sltiu", "t,r,j", op[0], op[1], |
17a2f251 | 13407 | BFD_RELOC_LO16); |
8fc2e39e | 13408 | break; |
252b5132 | 13409 | } |
8fc2e39e | 13410 | used_at = 1; |
bad1aba3 | 13411 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13412 | macro_build (NULL, "sltu", "d,v,t", op[0], op[1], AT); |
252b5132 RH |
13413 | break; |
13414 | ||
13415 | case M_SNE: | |
c0ebe874 RS |
13416 | if (op[1] == 0) |
13417 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[2]); | |
13418 | else if (op[2] == 0) | |
13419 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]); | |
252b5132 RH |
13420 | else |
13421 | { | |
c0ebe874 RS |
13422 | macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]); |
13423 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]); | |
252b5132 | 13424 | } |
8fc2e39e | 13425 | break; |
252b5132 RH |
13426 | |
13427 | case M_SNE_I: | |
b0e6f033 | 13428 | if (imm_expr.X_add_number == 0) |
252b5132 | 13429 | { |
c0ebe874 | 13430 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]); |
8fc2e39e | 13431 | break; |
252b5132 | 13432 | } |
c0ebe874 | 13433 | if (op[1] == 0) |
252b5132 | 13434 | { |
1661c76c | 13435 | as_warn (_("instruction %s: result is always true"), |
252b5132 | 13436 | ip->insn_mo->name); |
bad1aba3 | 13437 | macro_build (&expr1, GPR_SIZE == 32 ? "addiu" : "daddiu", "t,r,j", |
c0ebe874 | 13438 | op[0], 0, BFD_RELOC_LO16); |
8fc2e39e | 13439 | break; |
252b5132 | 13440 | } |
dd3cbb7e NC |
13441 | if (CPU_HAS_SEQ (mips_opts.arch) |
13442 | && -512 <= imm_expr.X_add_number | |
13443 | && imm_expr.X_add_number < 512) | |
13444 | { | |
c0ebe874 | 13445 | macro_build (NULL, "snei", "t,r,+Q", op[0], op[1], |
750bdd57 | 13446 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
13447 | break; |
13448 | } | |
b0e6f033 | 13449 | if (imm_expr.X_add_number >= 0 |
252b5132 RH |
13450 | && imm_expr.X_add_number < 0x10000) |
13451 | { | |
c0ebe874 RS |
13452 | macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1], |
13453 | BFD_RELOC_LO16); | |
252b5132 | 13454 | } |
b0e6f033 | 13455 | else if (imm_expr.X_add_number > -0x8000 |
252b5132 RH |
13456 | && imm_expr.X_add_number < 0) |
13457 | { | |
13458 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
bad1aba3 | 13459 | macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu", |
c0ebe874 | 13460 | "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
252b5132 | 13461 | } |
dd3cbb7e NC |
13462 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
13463 | { | |
13464 | used_at = 1; | |
bad1aba3 | 13465 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13466 | macro_build (NULL, "sne", "d,v,t", op[0], op[1], AT); |
dd3cbb7e NC |
13467 | break; |
13468 | } | |
252b5132 RH |
13469 | else |
13470 | { | |
bad1aba3 | 13471 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13472 | macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT); |
252b5132 RH |
13473 | used_at = 1; |
13474 | } | |
c0ebe874 | 13475 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]); |
8fc2e39e | 13476 | break; |
252b5132 | 13477 | |
df58fc94 RS |
13478 | case M_SUB_I: |
13479 | s = "addi"; | |
13480 | s2 = "sub"; | |
13481 | goto do_subi; | |
13482 | case M_SUBU_I: | |
13483 | s = "addiu"; | |
13484 | s2 = "subu"; | |
13485 | goto do_subi; | |
252b5132 RH |
13486 | case M_DSUB_I: |
13487 | dbl = 1; | |
df58fc94 RS |
13488 | s = "daddi"; |
13489 | s2 = "dsub"; | |
13490 | if (!mips_opts.micromips) | |
13491 | goto do_subi; | |
b0e6f033 | 13492 | if (imm_expr.X_add_number > -0x200 |
df58fc94 | 13493 | && imm_expr.X_add_number <= 0x200) |
252b5132 | 13494 | { |
b0e6f033 RS |
13495 | macro_build (NULL, s, "t,r,.", op[0], op[1], |
13496 | (int) -imm_expr.X_add_number); | |
8fc2e39e | 13497 | break; |
252b5132 | 13498 | } |
df58fc94 | 13499 | goto do_subi_i; |
252b5132 RH |
13500 | case M_DSUBU_I: |
13501 | dbl = 1; | |
df58fc94 RS |
13502 | s = "daddiu"; |
13503 | s2 = "dsubu"; | |
13504 | do_subi: | |
b0e6f033 | 13505 | if (imm_expr.X_add_number > -0x8000 |
252b5132 RH |
13506 | && imm_expr.X_add_number <= 0x8000) |
13507 | { | |
13508 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
c0ebe874 | 13509 | macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
8fc2e39e | 13510 | break; |
252b5132 | 13511 | } |
df58fc94 | 13512 | do_subi_i: |
8fc2e39e | 13513 | used_at = 1; |
67c0d1eb | 13514 | load_register (AT, &imm_expr, dbl); |
c0ebe874 | 13515 | macro_build (NULL, s2, "d,v,t", op[0], op[1], AT); |
252b5132 RH |
13516 | break; |
13517 | ||
13518 | case M_TEQ_I: | |
13519 | s = "teq"; | |
13520 | goto trap; | |
13521 | case M_TGE_I: | |
13522 | s = "tge"; | |
13523 | goto trap; | |
13524 | case M_TGEU_I: | |
13525 | s = "tgeu"; | |
13526 | goto trap; | |
13527 | case M_TLT_I: | |
13528 | s = "tlt"; | |
13529 | goto trap; | |
13530 | case M_TLTU_I: | |
13531 | s = "tltu"; | |
13532 | goto trap; | |
13533 | case M_TNE_I: | |
13534 | s = "tne"; | |
13535 | trap: | |
8fc2e39e | 13536 | used_at = 1; |
bad1aba3 | 13537 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13538 | macro_build (NULL, s, "s,t", op[0], AT); |
252b5132 RH |
13539 | break; |
13540 | ||
252b5132 | 13541 | case M_TRUNCWS: |
43841e91 | 13542 | case M_TRUNCWD: |
df58fc94 | 13543 | gas_assert (!mips_opts.micromips); |
0aa27725 | 13544 | gas_assert (mips_opts.isa == ISA_MIPS1); |
8fc2e39e | 13545 | used_at = 1; |
252b5132 RH |
13546 | |
13547 | /* | |
13548 | * Is the double cfc1 instruction a bug in the mips assembler; | |
13549 | * or is there a reason for it? | |
13550 | */ | |
7d10b47d | 13551 | start_noreorder (); |
c0ebe874 RS |
13552 | macro_build (NULL, "cfc1", "t,G", op[2], RA); |
13553 | macro_build (NULL, "cfc1", "t,G", op[2], RA); | |
67c0d1eb | 13554 | macro_build (NULL, "nop", ""); |
252b5132 | 13555 | expr1.X_add_number = 3; |
c0ebe874 | 13556 | macro_build (&expr1, "ori", "t,r,i", AT, op[2], BFD_RELOC_LO16); |
252b5132 | 13557 | expr1.X_add_number = 2; |
67c0d1eb RS |
13558 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
13559 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
13560 | macro_build (NULL, "nop", ""); | |
13561 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
c0ebe874 RS |
13562 | op[0], op[1]); |
13563 | macro_build (NULL, "ctc1", "t,G", op[2], RA); | |
67c0d1eb | 13564 | macro_build (NULL, "nop", ""); |
7d10b47d | 13565 | end_noreorder (); |
252b5132 RH |
13566 | break; |
13567 | ||
f2ae14a1 | 13568 | case M_ULH_AB: |
252b5132 | 13569 | s = "lb"; |
df58fc94 RS |
13570 | s2 = "lbu"; |
13571 | off = 1; | |
13572 | goto uld_st; | |
f2ae14a1 | 13573 | case M_ULHU_AB: |
252b5132 | 13574 | s = "lbu"; |
df58fc94 RS |
13575 | s2 = "lbu"; |
13576 | off = 1; | |
13577 | goto uld_st; | |
f2ae14a1 | 13578 | case M_ULW_AB: |
df58fc94 RS |
13579 | s = "lwl"; |
13580 | s2 = "lwr"; | |
7f3c4072 | 13581 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
13582 | off = 3; |
13583 | goto uld_st; | |
f2ae14a1 | 13584 | case M_ULD_AB: |
252b5132 RH |
13585 | s = "ldl"; |
13586 | s2 = "ldr"; | |
7f3c4072 | 13587 | offbits = (mips_opts.micromips ? 12 : 16); |
252b5132 | 13588 | off = 7; |
df58fc94 | 13589 | goto uld_st; |
f2ae14a1 | 13590 | case M_USH_AB: |
df58fc94 RS |
13591 | s = "sb"; |
13592 | s2 = "sb"; | |
13593 | off = 1; | |
13594 | ust = 1; | |
13595 | goto uld_st; | |
f2ae14a1 | 13596 | case M_USW_AB: |
df58fc94 RS |
13597 | s = "swl"; |
13598 | s2 = "swr"; | |
7f3c4072 | 13599 | offbits = (mips_opts.micromips ? 12 : 16); |
252b5132 | 13600 | off = 3; |
df58fc94 RS |
13601 | ust = 1; |
13602 | goto uld_st; | |
f2ae14a1 | 13603 | case M_USD_AB: |
df58fc94 RS |
13604 | s = "sdl"; |
13605 | s2 = "sdr"; | |
7f3c4072 | 13606 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
13607 | off = 7; |
13608 | ust = 1; | |
13609 | ||
13610 | uld_st: | |
c0ebe874 | 13611 | breg = op[2]; |
f2ae14a1 | 13612 | large_offset = !small_offset_p (off, align, offbits); |
df58fc94 RS |
13613 | ep = &offset_expr; |
13614 | expr1.X_add_number = 0; | |
f2ae14a1 | 13615 | if (large_offset) |
df58fc94 RS |
13616 | { |
13617 | used_at = 1; | |
13618 | tempreg = AT; | |
f2ae14a1 RS |
13619 | if (small_offset_p (0, align, 16)) |
13620 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, -1, | |
13621 | offset_reloc[0], offset_reloc[1], offset_reloc[2]); | |
13622 | else | |
13623 | { | |
13624 | load_address (tempreg, ep, &used_at); | |
13625 | if (breg != 0) | |
13626 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
13627 | tempreg, tempreg, breg); | |
13628 | } | |
13629 | offset_reloc[0] = BFD_RELOC_LO16; | |
13630 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
13631 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
df58fc94 | 13632 | breg = tempreg; |
c0ebe874 | 13633 | tempreg = op[0]; |
df58fc94 RS |
13634 | ep = &expr1; |
13635 | } | |
c0ebe874 | 13636 | else if (!ust && op[0] == breg) |
8fc2e39e TS |
13637 | { |
13638 | used_at = 1; | |
13639 | tempreg = AT; | |
13640 | } | |
252b5132 | 13641 | else |
c0ebe874 | 13642 | tempreg = op[0]; |
af22f5b2 | 13643 | |
df58fc94 RS |
13644 | if (off == 1) |
13645 | goto ulh_sh; | |
252b5132 | 13646 | |
90ecf173 | 13647 | if (!target_big_endian) |
df58fc94 | 13648 | ep->X_add_number += off; |
f2ae14a1 | 13649 | if (offbits == 12) |
c8276761 | 13650 | macro_build (NULL, s, "t,~(b)", tempreg, (int) ep->X_add_number, breg); |
f2ae14a1 RS |
13651 | else |
13652 | macro_build (ep, s, "t,o(b)", tempreg, -1, | |
13653 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); | |
df58fc94 | 13654 | |
90ecf173 | 13655 | if (!target_big_endian) |
df58fc94 | 13656 | ep->X_add_number -= off; |
252b5132 | 13657 | else |
df58fc94 | 13658 | ep->X_add_number += off; |
f2ae14a1 | 13659 | if (offbits == 12) |
df58fc94 | 13660 | macro_build (NULL, s2, "t,~(b)", |
c8276761 | 13661 | tempreg, (int) ep->X_add_number, breg); |
f2ae14a1 RS |
13662 | else |
13663 | macro_build (ep, s2, "t,o(b)", tempreg, -1, | |
13664 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); | |
252b5132 | 13665 | |
df58fc94 | 13666 | /* If necessary, move the result in tempreg to the final destination. */ |
c0ebe874 | 13667 | if (!ust && op[0] != tempreg) |
df58fc94 RS |
13668 | { |
13669 | /* Protect second load's delay slot. */ | |
13670 | load_delay_nop (); | |
c0ebe874 | 13671 | move_register (op[0], tempreg); |
df58fc94 | 13672 | } |
8fc2e39e | 13673 | break; |
252b5132 | 13674 | |
df58fc94 | 13675 | ulh_sh: |
d6bc6245 | 13676 | used_at = 1; |
df58fc94 RS |
13677 | if (target_big_endian == ust) |
13678 | ep->X_add_number += off; | |
c0ebe874 | 13679 | tempreg = ust || large_offset ? op[0] : AT; |
f2ae14a1 RS |
13680 | macro_build (ep, s, "t,o(b)", tempreg, -1, |
13681 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); | |
df58fc94 RS |
13682 | |
13683 | /* For halfword transfers we need a temporary register to shuffle | |
13684 | bytes. Unfortunately for M_USH_A we have none available before | |
13685 | the next store as AT holds the base address. We deal with this | |
13686 | case by clobbering TREG and then restoring it as with ULH. */ | |
c0ebe874 | 13687 | tempreg = ust == large_offset ? op[0] : AT; |
df58fc94 | 13688 | if (ust) |
c0ebe874 | 13689 | macro_build (NULL, "srl", SHFT_FMT, tempreg, op[0], 8); |
df58fc94 RS |
13690 | |
13691 | if (target_big_endian == ust) | |
13692 | ep->X_add_number -= off; | |
252b5132 | 13693 | else |
df58fc94 | 13694 | ep->X_add_number += off; |
f2ae14a1 RS |
13695 | macro_build (ep, s2, "t,o(b)", tempreg, -1, |
13696 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); | |
252b5132 | 13697 | |
df58fc94 | 13698 | /* For M_USH_A re-retrieve the LSB. */ |
f2ae14a1 | 13699 | if (ust && large_offset) |
df58fc94 RS |
13700 | { |
13701 | if (target_big_endian) | |
13702 | ep->X_add_number += off; | |
13703 | else | |
13704 | ep->X_add_number -= off; | |
f2ae14a1 RS |
13705 | macro_build (&expr1, "lbu", "t,o(b)", AT, -1, |
13706 | offset_reloc[0], offset_reloc[1], offset_reloc[2], AT); | |
df58fc94 RS |
13707 | } |
13708 | /* For ULH and M_USH_A OR the LSB in. */ | |
f2ae14a1 | 13709 | if (!ust || large_offset) |
df58fc94 | 13710 | { |
c0ebe874 | 13711 | tempreg = !large_offset ? AT : op[0]; |
df58fc94 | 13712 | macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8); |
c0ebe874 | 13713 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); |
df58fc94 | 13714 | } |
252b5132 RH |
13715 | break; |
13716 | ||
13717 | default: | |
13718 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 13719 | are added dynamically. */ |
1661c76c | 13720 | as_bad (_("macro %s not implemented yet"), ip->insn_mo->name); |
252b5132 RH |
13721 | break; |
13722 | } | |
741fe287 | 13723 | if (!mips_opts.at && used_at) |
1661c76c | 13724 | as_bad (_("macro used $at after \".set noat\"")); |
252b5132 RH |
13725 | } |
13726 | ||
13727 | /* Implement macros in mips16 mode. */ | |
13728 | ||
13729 | static void | |
17a2f251 | 13730 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 | 13731 | { |
c0ebe874 | 13732 | const struct mips_operand_array *operands; |
252b5132 | 13733 | int mask; |
c0ebe874 | 13734 | int tmp; |
252b5132 RH |
13735 | expressionS expr1; |
13736 | int dbl; | |
13737 | const char *s, *s2, *s3; | |
c0ebe874 RS |
13738 | unsigned int op[MAX_OPERANDS]; |
13739 | unsigned int i; | |
252b5132 RH |
13740 | |
13741 | mask = ip->insn_mo->mask; | |
13742 | ||
c0ebe874 RS |
13743 | operands = insn_operands (ip); |
13744 | for (i = 0; i < MAX_OPERANDS; i++) | |
13745 | if (operands->operand[i]) | |
13746 | op[i] = insn_extract_operand (ip, operands->operand[i]); | |
13747 | else | |
13748 | op[i] = -1; | |
252b5132 | 13749 | |
252b5132 RH |
13750 | expr1.X_op = O_constant; |
13751 | expr1.X_op_symbol = NULL; | |
13752 | expr1.X_add_symbol = NULL; | |
13753 | expr1.X_add_number = 1; | |
13754 | ||
13755 | dbl = 0; | |
13756 | ||
13757 | switch (mask) | |
13758 | { | |
13759 | default: | |
b37df7c4 | 13760 | abort (); |
252b5132 RH |
13761 | |
13762 | case M_DDIV_3: | |
13763 | dbl = 1; | |
1a0670f3 | 13764 | /* Fall through. */ |
252b5132 RH |
13765 | case M_DIV_3: |
13766 | s = "mflo"; | |
13767 | goto do_div3; | |
13768 | case M_DREM_3: | |
13769 | dbl = 1; | |
1a0670f3 | 13770 | /* Fall through. */ |
252b5132 RH |
13771 | case M_REM_3: |
13772 | s = "mfhi"; | |
13773 | do_div3: | |
7d10b47d | 13774 | start_noreorder (); |
d8722d76 | 13775 | macro_build (NULL, dbl ? "ddiv" : "div", ".,x,y", op[1], op[2]); |
252b5132 | 13776 | expr1.X_add_number = 2; |
c0ebe874 | 13777 | macro_build (&expr1, "bnez", "x,p", op[2]); |
67c0d1eb | 13778 | macro_build (NULL, "break", "6", 7); |
bdaaa2e1 | 13779 | |
252b5132 RH |
13780 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
13781 | since that causes an overflow. We should do that as well, | |
13782 | but I don't see how to do the comparisons without a temporary | |
13783 | register. */ | |
7d10b47d | 13784 | end_noreorder (); |
c0ebe874 | 13785 | macro_build (NULL, s, "x", op[0]); |
252b5132 RH |
13786 | break; |
13787 | ||
13788 | case M_DIVU_3: | |
13789 | s = "divu"; | |
13790 | s2 = "mflo"; | |
13791 | goto do_divu3; | |
13792 | case M_REMU_3: | |
13793 | s = "divu"; | |
13794 | s2 = "mfhi"; | |
13795 | goto do_divu3; | |
13796 | case M_DDIVU_3: | |
13797 | s = "ddivu"; | |
13798 | s2 = "mflo"; | |
13799 | goto do_divu3; | |
13800 | case M_DREMU_3: | |
13801 | s = "ddivu"; | |
13802 | s2 = "mfhi"; | |
13803 | do_divu3: | |
7d10b47d | 13804 | start_noreorder (); |
d8722d76 | 13805 | macro_build (NULL, s, ".,x,y", op[1], op[2]); |
252b5132 | 13806 | expr1.X_add_number = 2; |
c0ebe874 | 13807 | macro_build (&expr1, "bnez", "x,p", op[2]); |
67c0d1eb | 13808 | macro_build (NULL, "break", "6", 7); |
7d10b47d | 13809 | end_noreorder (); |
c0ebe874 | 13810 | macro_build (NULL, s2, "x", op[0]); |
252b5132 RH |
13811 | break; |
13812 | ||
13813 | case M_DMUL: | |
13814 | dbl = 1; | |
1a0670f3 | 13815 | /* Fall through. */ |
252b5132 | 13816 | case M_MUL: |
c0ebe874 RS |
13817 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", op[1], op[2]); |
13818 | macro_build (NULL, "mflo", "x", op[0]); | |
8fc2e39e | 13819 | break; |
252b5132 RH |
13820 | |
13821 | case M_DSUBU_I: | |
13822 | dbl = 1; | |
13823 | goto do_subu; | |
13824 | case M_SUBU_I: | |
13825 | do_subu: | |
252b5132 | 13826 | imm_expr.X_add_number = -imm_expr.X_add_number; |
d8722d76 | 13827 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,F", op[0], op[1]); |
252b5132 RH |
13828 | break; |
13829 | ||
13830 | case M_SUBU_I_2: | |
252b5132 | 13831 | imm_expr.X_add_number = -imm_expr.X_add_number; |
c0ebe874 | 13832 | macro_build (&imm_expr, "addiu", "x,k", op[0]); |
252b5132 RH |
13833 | break; |
13834 | ||
13835 | case M_DSUBU_I_2: | |
252b5132 | 13836 | imm_expr.X_add_number = -imm_expr.X_add_number; |
c0ebe874 | 13837 | macro_build (&imm_expr, "daddiu", "y,j", op[0]); |
252b5132 RH |
13838 | break; |
13839 | ||
13840 | case M_BEQ: | |
13841 | s = "cmp"; | |
13842 | s2 = "bteqz"; | |
13843 | goto do_branch; | |
13844 | case M_BNE: | |
13845 | s = "cmp"; | |
13846 | s2 = "btnez"; | |
13847 | goto do_branch; | |
13848 | case M_BLT: | |
13849 | s = "slt"; | |
13850 | s2 = "btnez"; | |
13851 | goto do_branch; | |
13852 | case M_BLTU: | |
13853 | s = "sltu"; | |
13854 | s2 = "btnez"; | |
13855 | goto do_branch; | |
13856 | case M_BLE: | |
13857 | s = "slt"; | |
13858 | s2 = "bteqz"; | |
13859 | goto do_reverse_branch; | |
13860 | case M_BLEU: | |
13861 | s = "sltu"; | |
13862 | s2 = "bteqz"; | |
13863 | goto do_reverse_branch; | |
13864 | case M_BGE: | |
13865 | s = "slt"; | |
13866 | s2 = "bteqz"; | |
13867 | goto do_branch; | |
13868 | case M_BGEU: | |
13869 | s = "sltu"; | |
13870 | s2 = "bteqz"; | |
13871 | goto do_branch; | |
13872 | case M_BGT: | |
13873 | s = "slt"; | |
13874 | s2 = "btnez"; | |
13875 | goto do_reverse_branch; | |
13876 | case M_BGTU: | |
13877 | s = "sltu"; | |
13878 | s2 = "btnez"; | |
13879 | ||
13880 | do_reverse_branch: | |
c0ebe874 RS |
13881 | tmp = op[1]; |
13882 | op[1] = op[0]; | |
13883 | op[0] = tmp; | |
252b5132 RH |
13884 | |
13885 | do_branch: | |
c0ebe874 | 13886 | macro_build (NULL, s, "x,y", op[0], op[1]); |
67c0d1eb | 13887 | macro_build (&offset_expr, s2, "p"); |
252b5132 RH |
13888 | break; |
13889 | ||
13890 | case M_BEQ_I: | |
13891 | s = "cmpi"; | |
13892 | s2 = "bteqz"; | |
13893 | s3 = "x,U"; | |
13894 | goto do_branch_i; | |
13895 | case M_BNE_I: | |
13896 | s = "cmpi"; | |
13897 | s2 = "btnez"; | |
13898 | s3 = "x,U"; | |
13899 | goto do_branch_i; | |
13900 | case M_BLT_I: | |
13901 | s = "slti"; | |
13902 | s2 = "btnez"; | |
13903 | s3 = "x,8"; | |
13904 | goto do_branch_i; | |
13905 | case M_BLTU_I: | |
13906 | s = "sltiu"; | |
13907 | s2 = "btnez"; | |
13908 | s3 = "x,8"; | |
13909 | goto do_branch_i; | |
13910 | case M_BLE_I: | |
13911 | s = "slti"; | |
13912 | s2 = "btnez"; | |
13913 | s3 = "x,8"; | |
13914 | goto do_addone_branch_i; | |
13915 | case M_BLEU_I: | |
13916 | s = "sltiu"; | |
13917 | s2 = "btnez"; | |
13918 | s3 = "x,8"; | |
13919 | goto do_addone_branch_i; | |
13920 | case M_BGE_I: | |
13921 | s = "slti"; | |
13922 | s2 = "bteqz"; | |
13923 | s3 = "x,8"; | |
13924 | goto do_branch_i; | |
13925 | case M_BGEU_I: | |
13926 | s = "sltiu"; | |
13927 | s2 = "bteqz"; | |
13928 | s3 = "x,8"; | |
13929 | goto do_branch_i; | |
13930 | case M_BGT_I: | |
13931 | s = "slti"; | |
13932 | s2 = "bteqz"; | |
13933 | s3 = "x,8"; | |
13934 | goto do_addone_branch_i; | |
13935 | case M_BGTU_I: | |
13936 | s = "sltiu"; | |
13937 | s2 = "bteqz"; | |
13938 | s3 = "x,8"; | |
13939 | ||
13940 | do_addone_branch_i: | |
252b5132 RH |
13941 | ++imm_expr.X_add_number; |
13942 | ||
13943 | do_branch_i: | |
c0ebe874 | 13944 | macro_build (&imm_expr, s, s3, op[0]); |
67c0d1eb | 13945 | macro_build (&offset_expr, s2, "p"); |
252b5132 RH |
13946 | break; |
13947 | ||
13948 | case M_ABS: | |
13949 | expr1.X_add_number = 0; | |
c0ebe874 RS |
13950 | macro_build (&expr1, "slti", "x,8", op[1]); |
13951 | if (op[0] != op[1]) | |
13952 | macro_build (NULL, "move", "y,X", op[0], mips16_to_32_reg_map[op[1]]); | |
252b5132 | 13953 | expr1.X_add_number = 2; |
67c0d1eb | 13954 | macro_build (&expr1, "bteqz", "p"); |
c0ebe874 | 13955 | macro_build (NULL, "neg", "x,w", op[0], op[0]); |
0acfaea6 | 13956 | break; |
252b5132 RH |
13957 | } |
13958 | } | |
13959 | ||
14daeee3 RS |
13960 | /* Look up instruction [START, START + LENGTH) in HASH. Record any extra |
13961 | opcode bits in *OPCODE_EXTRA. */ | |
13962 | ||
13963 | static struct mips_opcode * | |
13964 | mips_lookup_insn (struct hash_control *hash, const char *start, | |
da8bca91 | 13965 | ssize_t length, unsigned int *opcode_extra) |
14daeee3 RS |
13966 | { |
13967 | char *name, *dot, *p; | |
13968 | unsigned int mask, suffix; | |
da8bca91 | 13969 | ssize_t opend; |
14daeee3 RS |
13970 | struct mips_opcode *insn; |
13971 | ||
13972 | /* Make a copy of the instruction so that we can fiddle with it. */ | |
4ec9d7d5 | 13973 | name = xstrndup (start, length); |
14daeee3 RS |
13974 | |
13975 | /* Look up the instruction as-is. */ | |
13976 | insn = (struct mips_opcode *) hash_find (hash, name); | |
ee5734f0 | 13977 | if (insn) |
e1fa0163 | 13978 | goto end; |
14daeee3 RS |
13979 | |
13980 | dot = strchr (name, '.'); | |
13981 | if (dot && dot[1]) | |
13982 | { | |
13983 | /* Try to interpret the text after the dot as a VU0 channel suffix. */ | |
13984 | p = mips_parse_vu0_channels (dot + 1, &mask); | |
13985 | if (*p == 0 && mask != 0) | |
13986 | { | |
13987 | *dot = 0; | |
13988 | insn = (struct mips_opcode *) hash_find (hash, name); | |
13989 | *dot = '.'; | |
13990 | if (insn && (insn->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0) | |
13991 | { | |
13992 | *opcode_extra |= mask << mips_vu0_channel_mask.lsb; | |
e1fa0163 | 13993 | goto end; |
14daeee3 RS |
13994 | } |
13995 | } | |
13996 | } | |
13997 | ||
13998 | if (mips_opts.micromips) | |
13999 | { | |
14000 | /* See if there's an instruction size override suffix, | |
14001 | either `16' or `32', at the end of the mnemonic proper, | |
14002 | that defines the operation, i.e. before the first `.' | |
14003 | character if any. Strip it and retry. */ | |
14004 | opend = dot != NULL ? dot - name : length; | |
14005 | if (opend >= 3 && name[opend - 2] == '1' && name[opend - 1] == '6') | |
14006 | suffix = 2; | |
14007 | else if (name[opend - 2] == '3' && name[opend - 1] == '2') | |
14008 | suffix = 4; | |
14009 | else | |
14010 | suffix = 0; | |
14011 | if (suffix) | |
14012 | { | |
39334a61 | 14013 | memmove (name + opend - 2, name + opend, length - opend + 1); |
14daeee3 | 14014 | insn = (struct mips_opcode *) hash_find (hash, name); |
ee5734f0 | 14015 | if (insn) |
14daeee3 RS |
14016 | { |
14017 | forced_insn_length = suffix; | |
e1fa0163 | 14018 | goto end; |
14daeee3 RS |
14019 | } |
14020 | } | |
14021 | } | |
14022 | ||
e1fa0163 NC |
14023 | insn = NULL; |
14024 | end: | |
14025 | free (name); | |
14026 | return insn; | |
14daeee3 RS |
14027 | } |
14028 | ||
77bd4346 | 14029 | /* Assemble an instruction into its binary format. If the instruction |
e423441d RS |
14030 | is a macro, set imm_expr and offset_expr to the values associated |
14031 | with "I" and "A" operands respectively. Otherwise store the value | |
14032 | of the relocatable field (if any) in offset_expr. In both cases | |
14033 | set offset_reloc to the relocation operators applied to offset_expr. */ | |
252b5132 RH |
14034 | |
14035 | static void | |
60f20e8b | 14036 | mips_ip (char *str, struct mips_cl_insn *insn) |
252b5132 | 14037 | { |
60f20e8b | 14038 | const struct mips_opcode *first, *past; |
df58fc94 | 14039 | struct hash_control *hash; |
a92713e6 | 14040 | char format; |
14daeee3 | 14041 | size_t end; |
a92713e6 | 14042 | struct mips_operand_token *tokens; |
14daeee3 | 14043 | unsigned int opcode_extra; |
252b5132 | 14044 | |
df58fc94 RS |
14045 | if (mips_opts.micromips) |
14046 | { | |
14047 | hash = micromips_op_hash; | |
14048 | past = µmips_opcodes[bfd_micromips_num_opcodes]; | |
14049 | } | |
14050 | else | |
14051 | { | |
14052 | hash = op_hash; | |
14053 | past = &mips_opcodes[NUMOPCODES]; | |
14054 | } | |
14055 | forced_insn_length = 0; | |
14daeee3 | 14056 | opcode_extra = 0; |
252b5132 | 14057 | |
df58fc94 | 14058 | /* We first try to match an instruction up to a space or to the end. */ |
a40bc9dd RS |
14059 | for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++) |
14060 | continue; | |
bdaaa2e1 | 14061 | |
60f20e8b RS |
14062 | first = mips_lookup_insn (hash, str, end, &opcode_extra); |
14063 | if (first == NULL) | |
252b5132 | 14064 | { |
1661c76c | 14065 | set_insn_error (0, _("unrecognized opcode")); |
a40bc9dd | 14066 | return; |
252b5132 RH |
14067 | } |
14068 | ||
60f20e8b | 14069 | if (strcmp (first->name, "li.s") == 0) |
a92713e6 | 14070 | format = 'f'; |
60f20e8b | 14071 | else if (strcmp (first->name, "li.d") == 0) |
a92713e6 RS |
14072 | format = 'd'; |
14073 | else | |
14074 | format = 0; | |
14075 | tokens = mips_parse_arguments (str + end, format); | |
14076 | if (!tokens) | |
14077 | return; | |
14078 | ||
60f20e8b RS |
14079 | if (!match_insns (insn, first, past, tokens, opcode_extra, FALSE) |
14080 | && !match_insns (insn, first, past, tokens, opcode_extra, TRUE)) | |
1661c76c | 14081 | set_insn_error (0, _("invalid operands")); |
df58fc94 | 14082 | |
e3de51ce | 14083 | obstack_free (&mips_operand_tokens, tokens); |
252b5132 RH |
14084 | } |
14085 | ||
77bd4346 RS |
14086 | /* As for mips_ip, but used when assembling MIPS16 code. |
14087 | Also set forced_insn_length to the resulting instruction size in | |
14088 | bytes if the user explicitly requested a small or extended instruction. */ | |
252b5132 RH |
14089 | |
14090 | static void | |
60f20e8b | 14091 | mips16_ip (char *str, struct mips_cl_insn *insn) |
252b5132 | 14092 | { |
1a00e612 | 14093 | char *end, *s, c; |
60f20e8b | 14094 | struct mips_opcode *first; |
a92713e6 | 14095 | struct mips_operand_token *tokens; |
3fb49709 | 14096 | unsigned int l; |
252b5132 | 14097 | |
25499ac7 | 14098 | for (s = str; *s != '\0' && *s != '.' && *s != ' '; ++s) |
252b5132 | 14099 | ; |
1a00e612 RS |
14100 | end = s; |
14101 | c = *end; | |
3fb49709 MR |
14102 | |
14103 | l = 0; | |
1a00e612 | 14104 | switch (c) |
252b5132 RH |
14105 | { |
14106 | case '\0': | |
14107 | break; | |
14108 | ||
14109 | case ' ': | |
1a00e612 | 14110 | s++; |
252b5132 RH |
14111 | break; |
14112 | ||
14113 | case '.': | |
3fb49709 MR |
14114 | s++; |
14115 | if (*s == 't') | |
252b5132 | 14116 | { |
3fb49709 MR |
14117 | l = 2; |
14118 | s++; | |
252b5132 | 14119 | } |
3fb49709 | 14120 | else if (*s == 'e') |
252b5132 | 14121 | { |
3fb49709 MR |
14122 | l = 4; |
14123 | s++; | |
252b5132 | 14124 | } |
3fb49709 MR |
14125 | if (*s == '\0') |
14126 | break; | |
14127 | else if (*s++ == ' ') | |
14128 | break; | |
1661c76c | 14129 | set_insn_error (0, _("unrecognized opcode")); |
252b5132 RH |
14130 | return; |
14131 | } | |
3fb49709 | 14132 | forced_insn_length = l; |
252b5132 | 14133 | |
1a00e612 | 14134 | *end = 0; |
60f20e8b | 14135 | first = (struct mips_opcode *) hash_find (mips16_op_hash, str); |
1a00e612 RS |
14136 | *end = c; |
14137 | ||
60f20e8b | 14138 | if (!first) |
252b5132 | 14139 | { |
1661c76c | 14140 | set_insn_error (0, _("unrecognized opcode")); |
252b5132 RH |
14141 | return; |
14142 | } | |
14143 | ||
a92713e6 RS |
14144 | tokens = mips_parse_arguments (s, 0); |
14145 | if (!tokens) | |
14146 | return; | |
14147 | ||
60f20e8b | 14148 | if (!match_mips16_insns (insn, first, tokens)) |
1661c76c | 14149 | set_insn_error (0, _("invalid operands")); |
252b5132 | 14150 | |
e3de51ce | 14151 | obstack_free (&mips_operand_tokens, tokens); |
252b5132 RH |
14152 | } |
14153 | ||
b886a2ab RS |
14154 | /* Marshal immediate value VAL for an extended MIPS16 instruction. |
14155 | NBITS is the number of significant bits in VAL. */ | |
14156 | ||
14157 | static unsigned long | |
14158 | mips16_immed_extend (offsetT val, unsigned int nbits) | |
14159 | { | |
14160 | int extval; | |
25499ac7 MR |
14161 | |
14162 | extval = 0; | |
14163 | val &= (1U << nbits) - 1; | |
14164 | if (nbits == 16 || nbits == 9) | |
b886a2ab RS |
14165 | { |
14166 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
14167 | val &= 0x1f; | |
14168 | } | |
14169 | else if (nbits == 15) | |
14170 | { | |
14171 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
14172 | val &= 0xf; | |
14173 | } | |
25499ac7 | 14174 | else if (nbits == 6) |
b886a2ab RS |
14175 | { |
14176 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
14177 | val = 0; | |
14178 | } | |
14179 | return (extval << 16) | val; | |
14180 | } | |
14181 | ||
3ccad066 RS |
14182 | /* Like decode_mips16_operand, but require the operand to be defined and |
14183 | require it to be an integer. */ | |
14184 | ||
14185 | static const struct mips_int_operand * | |
14186 | mips16_immed_operand (int type, bfd_boolean extended_p) | |
14187 | { | |
14188 | const struct mips_operand *operand; | |
14189 | ||
14190 | operand = decode_mips16_operand (type, extended_p); | |
14191 | if (!operand || (operand->type != OP_INT && operand->type != OP_PCREL)) | |
14192 | abort (); | |
14193 | return (const struct mips_int_operand *) operand; | |
14194 | } | |
14195 | ||
14196 | /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */ | |
14197 | ||
14198 | static bfd_boolean | |
14199 | mips16_immed_in_range_p (const struct mips_int_operand *operand, | |
14200 | bfd_reloc_code_real_type reloc, offsetT sval) | |
14201 | { | |
14202 | int min_val, max_val; | |
14203 | ||
14204 | min_val = mips_int_operand_min (operand); | |
14205 | max_val = mips_int_operand_max (operand); | |
14206 | if (reloc != BFD_RELOC_UNUSED) | |
14207 | { | |
14208 | if (min_val < 0) | |
14209 | sval = SEXT_16BIT (sval); | |
14210 | else | |
14211 | sval &= 0xffff; | |
14212 | } | |
14213 | ||
14214 | return (sval >= min_val | |
14215 | && sval <= max_val | |
14216 | && (sval & ((1 << operand->shift) - 1)) == 0); | |
14217 | } | |
14218 | ||
5c04167a RS |
14219 | /* Install immediate value VAL into MIPS16 instruction *INSN, |
14220 | extending it if necessary. The instruction in *INSN may | |
14221 | already be extended. | |
14222 | ||
43c0598f RS |
14223 | RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED |
14224 | if none. In the former case, VAL is a 16-bit number with no | |
14225 | defined signedness. | |
14226 | ||
14227 | TYPE is the type of the immediate field. USER_INSN_LENGTH | |
14228 | is the length that the user requested, or 0 if none. */ | |
252b5132 RH |
14229 | |
14230 | static void | |
3b4dbbbf | 14231 | mips16_immed (const char *file, unsigned int line, int type, |
43c0598f | 14232 | bfd_reloc_code_real_type reloc, offsetT val, |
5c04167a | 14233 | unsigned int user_insn_length, unsigned long *insn) |
252b5132 | 14234 | { |
3ccad066 RS |
14235 | const struct mips_int_operand *operand; |
14236 | unsigned int uval, length; | |
252b5132 | 14237 | |
3ccad066 RS |
14238 | operand = mips16_immed_operand (type, FALSE); |
14239 | if (!mips16_immed_in_range_p (operand, reloc, val)) | |
5c04167a RS |
14240 | { |
14241 | /* We need an extended instruction. */ | |
14242 | if (user_insn_length == 2) | |
14243 | as_bad_where (file, line, _("invalid unextended operand value")); | |
14244 | else | |
14245 | *insn |= MIPS16_EXTEND; | |
14246 | } | |
14247 | else if (user_insn_length == 4) | |
14248 | { | |
14249 | /* The operand doesn't force an unextended instruction to be extended. | |
14250 | Warn if the user wanted an extended instruction anyway. */ | |
14251 | *insn |= MIPS16_EXTEND; | |
14252 | as_warn_where (file, line, | |
14253 | _("extended operand requested but not required")); | |
14254 | } | |
252b5132 | 14255 | |
3ccad066 RS |
14256 | length = mips16_opcode_length (*insn); |
14257 | if (length == 4) | |
252b5132 | 14258 | { |
3ccad066 RS |
14259 | operand = mips16_immed_operand (type, TRUE); |
14260 | if (!mips16_immed_in_range_p (operand, reloc, val)) | |
14261 | as_bad_where (file, line, | |
14262 | _("operand value out of range for instruction")); | |
252b5132 | 14263 | } |
3ccad066 | 14264 | uval = ((unsigned int) val >> operand->shift) - operand->bias; |
bdd15286 | 14265 | if (length == 2 || operand->root.lsb != 0) |
3ccad066 | 14266 | *insn = mips_insert_operand (&operand->root, *insn, uval); |
252b5132 | 14267 | else |
3ccad066 | 14268 | *insn |= mips16_immed_extend (uval, operand->root.size); |
252b5132 RH |
14269 | } |
14270 | \f | |
d6f16593 | 14271 | struct percent_op_match |
ad8d3bb3 | 14272 | { |
5e0116d5 RS |
14273 | const char *str; |
14274 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
14275 | }; |
14276 | ||
14277 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 14278 | { |
5e0116d5 | 14279 | {"%lo", BFD_RELOC_LO16}, |
5e0116d5 RS |
14280 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
14281 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
14282 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
14283 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
14284 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
14285 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
14286 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
14287 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
14288 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
14289 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
be3f1006 | 14290 | {"%gprel", BFD_RELOC_GPREL16}, |
5e0116d5 RS |
14291 | {"%half", BFD_RELOC_16}, |
14292 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
14293 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
14294 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
14295 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
14296 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
14297 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
14298 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
14299 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
14300 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
14301 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
7361da2c AB |
14302 | {"%hi", BFD_RELOC_HI16_S}, |
14303 | {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL}, | |
14304 | {"%pcrel_lo", BFD_RELOC_LO16_PCREL} | |
ad8d3bb3 TS |
14305 | }; |
14306 | ||
d6f16593 MR |
14307 | static const struct percent_op_match mips16_percent_op[] = |
14308 | { | |
14309 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
be3f1006 | 14310 | {"%gp_rel", BFD_RELOC_MIPS16_GPREL}, |
d6f16593 | 14311 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, |
738e5348 RS |
14312 | {"%got", BFD_RELOC_MIPS16_GOT16}, |
14313 | {"%call16", BFD_RELOC_MIPS16_CALL16}, | |
d0f13682 CLT |
14314 | {"%hi", BFD_RELOC_MIPS16_HI16_S}, |
14315 | {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD}, | |
14316 | {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM}, | |
14317 | {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16}, | |
14318 | {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16}, | |
14319 | {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16}, | |
14320 | {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16}, | |
14321 | {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL} | |
d6f16593 MR |
14322 | }; |
14323 | ||
252b5132 | 14324 | |
5e0116d5 RS |
14325 | /* Return true if *STR points to a relocation operator. When returning true, |
14326 | move *STR over the operator and store its relocation code in *RELOC. | |
14327 | Leave both *STR and *RELOC alone when returning false. */ | |
14328 | ||
14329 | static bfd_boolean | |
17a2f251 | 14330 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 14331 | { |
d6f16593 MR |
14332 | const struct percent_op_match *percent_op; |
14333 | size_t limit, i; | |
14334 | ||
14335 | if (mips_opts.mips16) | |
14336 | { | |
14337 | percent_op = mips16_percent_op; | |
14338 | limit = ARRAY_SIZE (mips16_percent_op); | |
14339 | } | |
14340 | else | |
14341 | { | |
14342 | percent_op = mips_percent_op; | |
14343 | limit = ARRAY_SIZE (mips_percent_op); | |
14344 | } | |
76b3015f | 14345 | |
d6f16593 | 14346 | for (i = 0; i < limit; i++) |
5e0116d5 | 14347 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 14348 | { |
3f98094e DJ |
14349 | int len = strlen (percent_op[i].str); |
14350 | ||
14351 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
14352 | continue; | |
14353 | ||
5e0116d5 RS |
14354 | *str += strlen (percent_op[i].str); |
14355 | *reloc = percent_op[i].reloc; | |
394f9b3a | 14356 | |
5e0116d5 RS |
14357 | /* Check whether the output BFD supports this relocation. |
14358 | If not, issue an error and fall back on something safe. */ | |
14359 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 14360 | { |
20203fb9 | 14361 | as_bad (_("relocation %s isn't supported by the current ABI"), |
5e0116d5 | 14362 | percent_op[i].str); |
01a3f561 | 14363 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 14364 | } |
5e0116d5 | 14365 | return TRUE; |
394f9b3a | 14366 | } |
5e0116d5 | 14367 | return FALSE; |
394f9b3a | 14368 | } |
ad8d3bb3 | 14369 | |
ad8d3bb3 | 14370 | |
5e0116d5 RS |
14371 | /* Parse string STR as a 16-bit relocatable operand. Store the |
14372 | expression in *EP and the relocations in the array starting | |
14373 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 14374 | |
01a3f561 | 14375 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 14376 | |
5e0116d5 | 14377 | static size_t |
17a2f251 TS |
14378 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
14379 | char *str) | |
ad8d3bb3 | 14380 | { |
5e0116d5 RS |
14381 | bfd_reloc_code_real_type reversed_reloc[3]; |
14382 | size_t reloc_index, i; | |
09b8f35a RS |
14383 | int crux_depth, str_depth; |
14384 | char *crux; | |
5e0116d5 RS |
14385 | |
14386 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
14387 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
14388 | of the main expression and with CRUX_DEPTH containing the number | |
14389 | of open brackets at that point. */ | |
14390 | reloc_index = -1; | |
14391 | str_depth = 0; | |
14392 | do | |
fb1b3232 | 14393 | { |
09b8f35a RS |
14394 | reloc_index++; |
14395 | crux = str; | |
14396 | crux_depth = str_depth; | |
14397 | ||
14398 | /* Skip over whitespace and brackets, keeping count of the number | |
14399 | of brackets. */ | |
14400 | while (*str == ' ' || *str == '\t' || *str == '(') | |
14401 | if (*str++ == '(') | |
14402 | str_depth++; | |
5e0116d5 | 14403 | } |
09b8f35a RS |
14404 | while (*str == '%' |
14405 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
14406 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 14407 | |
09b8f35a | 14408 | my_getExpression (ep, crux); |
5e0116d5 | 14409 | str = expr_end; |
394f9b3a | 14410 | |
5e0116d5 | 14411 | /* Match every open bracket. */ |
09b8f35a | 14412 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 14413 | if (*str++ == ')') |
09b8f35a | 14414 | crux_depth--; |
394f9b3a | 14415 | |
09b8f35a | 14416 | if (crux_depth > 0) |
20203fb9 | 14417 | as_bad (_("unclosed '('")); |
394f9b3a | 14418 | |
5e0116d5 | 14419 | expr_end = str; |
252b5132 | 14420 | |
01a3f561 | 14421 | if (reloc_index != 0) |
64bdfcaf RS |
14422 | { |
14423 | prev_reloc_op_frag = frag_now; | |
14424 | for (i = 0; i < reloc_index; i++) | |
14425 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
14426 | } | |
fb1b3232 | 14427 | |
5e0116d5 | 14428 | return reloc_index; |
252b5132 RH |
14429 | } |
14430 | ||
14431 | static void | |
17a2f251 | 14432 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
14433 | { |
14434 | char *save_in; | |
14435 | ||
14436 | save_in = input_line_pointer; | |
14437 | input_line_pointer = str; | |
14438 | expression (ep); | |
14439 | expr_end = input_line_pointer; | |
14440 | input_line_pointer = save_in; | |
252b5132 RH |
14441 | } |
14442 | ||
6d4af3c2 | 14443 | const char * |
17a2f251 | 14444 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 14445 | { |
499ac353 | 14446 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
252b5132 RH |
14447 | } |
14448 | ||
14449 | void | |
17a2f251 | 14450 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
14451 | { |
14452 | if (target_big_endian) | |
14453 | number_to_chars_bigendian (buf, val, n); | |
14454 | else | |
14455 | number_to_chars_littleendian (buf, val, n); | |
14456 | } | |
14457 | \f | |
e013f690 TS |
14458 | static int support_64bit_objects(void) |
14459 | { | |
14460 | const char **list, **l; | |
aa3d8fdf | 14461 | int yes; |
e013f690 TS |
14462 | |
14463 | list = bfd_target_list (); | |
14464 | for (l = list; *l != NULL; l++) | |
aeffff67 RS |
14465 | if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0 |
14466 | || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0) | |
e013f690 | 14467 | break; |
aa3d8fdf | 14468 | yes = (*l != NULL); |
e013f690 | 14469 | free (list); |
aa3d8fdf | 14470 | return yes; |
e013f690 TS |
14471 | } |
14472 | ||
316f5878 RS |
14473 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
14474 | NEW_VALUE. Warn if another value was already specified. Note: | |
14475 | we have to defer parsing the -march and -mtune arguments in order | |
14476 | to handle 'from-abi' correctly, since the ABI might be specified | |
14477 | in a later argument. */ | |
14478 | ||
14479 | static void | |
17a2f251 | 14480 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
14481 | { |
14482 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
1661c76c | 14483 | as_warn (_("a different %s was already specified, is now %s"), |
316f5878 RS |
14484 | string_ptr == &mips_arch_string ? "-march" : "-mtune", |
14485 | new_value); | |
14486 | ||
14487 | *string_ptr = new_value; | |
14488 | } | |
14489 | ||
252b5132 | 14490 | int |
17b9d67d | 14491 | md_parse_option (int c, const char *arg) |
252b5132 | 14492 | { |
c6278170 RS |
14493 | unsigned int i; |
14494 | ||
14495 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
14496 | if (c == mips_ases[i].option_on || c == mips_ases[i].option_off) | |
14497 | { | |
919731af | 14498 | file_ase_explicit |= mips_set_ase (&mips_ases[i], &file_mips_opts, |
c6278170 RS |
14499 | c == mips_ases[i].option_on); |
14500 | return 1; | |
14501 | } | |
14502 | ||
252b5132 RH |
14503 | switch (c) |
14504 | { | |
119d663a NC |
14505 | case OPTION_CONSTRUCT_FLOATS: |
14506 | mips_disable_float_construction = 0; | |
14507 | break; | |
bdaaa2e1 | 14508 | |
119d663a NC |
14509 | case OPTION_NO_CONSTRUCT_FLOATS: |
14510 | mips_disable_float_construction = 1; | |
14511 | break; | |
bdaaa2e1 | 14512 | |
252b5132 RH |
14513 | case OPTION_TRAP: |
14514 | mips_trap = 1; | |
14515 | break; | |
14516 | ||
14517 | case OPTION_BREAK: | |
14518 | mips_trap = 0; | |
14519 | break; | |
14520 | ||
14521 | case OPTION_EB: | |
14522 | target_big_endian = 1; | |
14523 | break; | |
14524 | ||
14525 | case OPTION_EL: | |
14526 | target_big_endian = 0; | |
14527 | break; | |
14528 | ||
14529 | case 'O': | |
4ffff32f TS |
14530 | if (arg == NULL) |
14531 | mips_optimize = 1; | |
14532 | else if (arg[0] == '0') | |
14533 | mips_optimize = 0; | |
14534 | else if (arg[0] == '1') | |
252b5132 RH |
14535 | mips_optimize = 1; |
14536 | else | |
14537 | mips_optimize = 2; | |
14538 | break; | |
14539 | ||
14540 | case 'g': | |
14541 | if (arg == NULL) | |
14542 | mips_debug = 2; | |
14543 | else | |
14544 | mips_debug = atoi (arg); | |
252b5132 RH |
14545 | break; |
14546 | ||
14547 | case OPTION_MIPS1: | |
0b35dfee | 14548 | file_mips_opts.isa = ISA_MIPS1; |
252b5132 RH |
14549 | break; |
14550 | ||
14551 | case OPTION_MIPS2: | |
0b35dfee | 14552 | file_mips_opts.isa = ISA_MIPS2; |
252b5132 RH |
14553 | break; |
14554 | ||
14555 | case OPTION_MIPS3: | |
0b35dfee | 14556 | file_mips_opts.isa = ISA_MIPS3; |
252b5132 RH |
14557 | break; |
14558 | ||
14559 | case OPTION_MIPS4: | |
0b35dfee | 14560 | file_mips_opts.isa = ISA_MIPS4; |
e7af610e NC |
14561 | break; |
14562 | ||
84ea6cf2 | 14563 | case OPTION_MIPS5: |
0b35dfee | 14564 | file_mips_opts.isa = ISA_MIPS5; |
84ea6cf2 NC |
14565 | break; |
14566 | ||
e7af610e | 14567 | case OPTION_MIPS32: |
0b35dfee | 14568 | file_mips_opts.isa = ISA_MIPS32; |
252b5132 RH |
14569 | break; |
14570 | ||
af7ee8bf | 14571 | case OPTION_MIPS32R2: |
0b35dfee | 14572 | file_mips_opts.isa = ISA_MIPS32R2; |
af7ee8bf CD |
14573 | break; |
14574 | ||
ae52f483 | 14575 | case OPTION_MIPS32R3: |
0ae19f05 | 14576 | file_mips_opts.isa = ISA_MIPS32R3; |
ae52f483 AB |
14577 | break; |
14578 | ||
14579 | case OPTION_MIPS32R5: | |
0ae19f05 | 14580 | file_mips_opts.isa = ISA_MIPS32R5; |
ae52f483 AB |
14581 | break; |
14582 | ||
7361da2c AB |
14583 | case OPTION_MIPS32R6: |
14584 | file_mips_opts.isa = ISA_MIPS32R6; | |
14585 | break; | |
14586 | ||
5f74bc13 | 14587 | case OPTION_MIPS64R2: |
0b35dfee | 14588 | file_mips_opts.isa = ISA_MIPS64R2; |
5f74bc13 CD |
14589 | break; |
14590 | ||
ae52f483 | 14591 | case OPTION_MIPS64R3: |
0ae19f05 | 14592 | file_mips_opts.isa = ISA_MIPS64R3; |
ae52f483 AB |
14593 | break; |
14594 | ||
14595 | case OPTION_MIPS64R5: | |
0ae19f05 | 14596 | file_mips_opts.isa = ISA_MIPS64R5; |
ae52f483 AB |
14597 | break; |
14598 | ||
7361da2c AB |
14599 | case OPTION_MIPS64R6: |
14600 | file_mips_opts.isa = ISA_MIPS64R6; | |
14601 | break; | |
14602 | ||
84ea6cf2 | 14603 | case OPTION_MIPS64: |
0b35dfee | 14604 | file_mips_opts.isa = ISA_MIPS64; |
84ea6cf2 NC |
14605 | break; |
14606 | ||
ec68c924 | 14607 | case OPTION_MTUNE: |
316f5878 RS |
14608 | mips_set_option_string (&mips_tune_string, arg); |
14609 | break; | |
ec68c924 | 14610 | |
316f5878 RS |
14611 | case OPTION_MARCH: |
14612 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
14613 | break; |
14614 | ||
14615 | case OPTION_M4650: | |
316f5878 RS |
14616 | mips_set_option_string (&mips_arch_string, "4650"); |
14617 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
14618 | break; |
14619 | ||
14620 | case OPTION_NO_M4650: | |
14621 | break; | |
14622 | ||
14623 | case OPTION_M4010: | |
316f5878 RS |
14624 | mips_set_option_string (&mips_arch_string, "4010"); |
14625 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
14626 | break; |
14627 | ||
14628 | case OPTION_NO_M4010: | |
14629 | break; | |
14630 | ||
14631 | case OPTION_M4100: | |
316f5878 RS |
14632 | mips_set_option_string (&mips_arch_string, "4100"); |
14633 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
14634 | break; |
14635 | ||
14636 | case OPTION_NO_M4100: | |
14637 | break; | |
14638 | ||
252b5132 | 14639 | case OPTION_M3900: |
316f5878 RS |
14640 | mips_set_option_string (&mips_arch_string, "3900"); |
14641 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 14642 | break; |
bdaaa2e1 | 14643 | |
252b5132 RH |
14644 | case OPTION_NO_M3900: |
14645 | break; | |
14646 | ||
df58fc94 | 14647 | case OPTION_MICROMIPS: |
919731af | 14648 | if (file_mips_opts.mips16 == 1) |
df58fc94 RS |
14649 | { |
14650 | as_bad (_("-mmicromips cannot be used with -mips16")); | |
14651 | return 0; | |
14652 | } | |
919731af | 14653 | file_mips_opts.micromips = 1; |
df58fc94 RS |
14654 | mips_no_prev_insn (); |
14655 | break; | |
14656 | ||
14657 | case OPTION_NO_MICROMIPS: | |
919731af | 14658 | file_mips_opts.micromips = 0; |
df58fc94 RS |
14659 | mips_no_prev_insn (); |
14660 | break; | |
14661 | ||
252b5132 | 14662 | case OPTION_MIPS16: |
919731af | 14663 | if (file_mips_opts.micromips == 1) |
df58fc94 RS |
14664 | { |
14665 | as_bad (_("-mips16 cannot be used with -micromips")); | |
14666 | return 0; | |
14667 | } | |
919731af | 14668 | file_mips_opts.mips16 = 1; |
7d10b47d | 14669 | mips_no_prev_insn (); |
252b5132 RH |
14670 | break; |
14671 | ||
14672 | case OPTION_NO_MIPS16: | |
919731af | 14673 | file_mips_opts.mips16 = 0; |
7d10b47d | 14674 | mips_no_prev_insn (); |
252b5132 RH |
14675 | break; |
14676 | ||
6a32d874 CM |
14677 | case OPTION_FIX_24K: |
14678 | mips_fix_24k = 1; | |
14679 | break; | |
14680 | ||
14681 | case OPTION_NO_FIX_24K: | |
14682 | mips_fix_24k = 0; | |
14683 | break; | |
14684 | ||
a8d14a88 CM |
14685 | case OPTION_FIX_RM7000: |
14686 | mips_fix_rm7000 = 1; | |
14687 | break; | |
14688 | ||
14689 | case OPTION_NO_FIX_RM7000: | |
14690 | mips_fix_rm7000 = 0; | |
14691 | break; | |
14692 | ||
c67a084a NC |
14693 | case OPTION_FIX_LOONGSON2F_JUMP: |
14694 | mips_fix_loongson2f_jump = TRUE; | |
14695 | break; | |
14696 | ||
14697 | case OPTION_NO_FIX_LOONGSON2F_JUMP: | |
14698 | mips_fix_loongson2f_jump = FALSE; | |
14699 | break; | |
14700 | ||
14701 | case OPTION_FIX_LOONGSON2F_NOP: | |
14702 | mips_fix_loongson2f_nop = TRUE; | |
14703 | break; | |
14704 | ||
14705 | case OPTION_NO_FIX_LOONGSON2F_NOP: | |
14706 | mips_fix_loongson2f_nop = FALSE; | |
14707 | break; | |
14708 | ||
d766e8ec RS |
14709 | case OPTION_FIX_VR4120: |
14710 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
14711 | break; |
14712 | ||
d766e8ec RS |
14713 | case OPTION_NO_FIX_VR4120: |
14714 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
14715 | break; |
14716 | ||
7d8e00cf RS |
14717 | case OPTION_FIX_VR4130: |
14718 | mips_fix_vr4130 = 1; | |
14719 | break; | |
14720 | ||
14721 | case OPTION_NO_FIX_VR4130: | |
14722 | mips_fix_vr4130 = 0; | |
14723 | break; | |
14724 | ||
d954098f DD |
14725 | case OPTION_FIX_CN63XXP1: |
14726 | mips_fix_cn63xxp1 = TRUE; | |
14727 | break; | |
14728 | ||
14729 | case OPTION_NO_FIX_CN63XXP1: | |
14730 | mips_fix_cn63xxp1 = FALSE; | |
14731 | break; | |
14732 | ||
4a6a3df4 AO |
14733 | case OPTION_RELAX_BRANCH: |
14734 | mips_relax_branch = 1; | |
14735 | break; | |
14736 | ||
14737 | case OPTION_NO_RELAX_BRANCH: | |
14738 | mips_relax_branch = 0; | |
14739 | break; | |
14740 | ||
8b10b0b3 MR |
14741 | case OPTION_IGNORE_BRANCH_ISA: |
14742 | mips_ignore_branch_isa = TRUE; | |
14743 | break; | |
14744 | ||
14745 | case OPTION_NO_IGNORE_BRANCH_ISA: | |
14746 | mips_ignore_branch_isa = FALSE; | |
14747 | break; | |
14748 | ||
833794fc | 14749 | case OPTION_INSN32: |
919731af | 14750 | file_mips_opts.insn32 = TRUE; |
833794fc MR |
14751 | break; |
14752 | ||
14753 | case OPTION_NO_INSN32: | |
919731af | 14754 | file_mips_opts.insn32 = FALSE; |
833794fc MR |
14755 | break; |
14756 | ||
aa6975fb ILT |
14757 | case OPTION_MSHARED: |
14758 | mips_in_shared = TRUE; | |
14759 | break; | |
14760 | ||
14761 | case OPTION_MNO_SHARED: | |
14762 | mips_in_shared = FALSE; | |
14763 | break; | |
14764 | ||
aed1a261 | 14765 | case OPTION_MSYM32: |
919731af | 14766 | file_mips_opts.sym32 = TRUE; |
aed1a261 RS |
14767 | break; |
14768 | ||
14769 | case OPTION_MNO_SYM32: | |
919731af | 14770 | file_mips_opts.sym32 = FALSE; |
aed1a261 RS |
14771 | break; |
14772 | ||
252b5132 RH |
14773 | /* When generating ELF code, we permit -KPIC and -call_shared to |
14774 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
14775 | intended to be compatible with Irix 5. */ | |
14776 | case OPTION_CALL_SHARED: | |
252b5132 | 14777 | mips_pic = SVR4_PIC; |
143d77c5 | 14778 | mips_abicalls = TRUE; |
252b5132 RH |
14779 | break; |
14780 | ||
861fb55a | 14781 | case OPTION_CALL_NONPIC: |
861fb55a DJ |
14782 | mips_pic = NO_PIC; |
14783 | mips_abicalls = TRUE; | |
14784 | break; | |
14785 | ||
252b5132 | 14786 | case OPTION_NON_SHARED: |
252b5132 | 14787 | mips_pic = NO_PIC; |
143d77c5 | 14788 | mips_abicalls = FALSE; |
252b5132 RH |
14789 | break; |
14790 | ||
44075ae2 TS |
14791 | /* The -xgot option tells the assembler to use 32 bit offsets |
14792 | when accessing the got in SVR4_PIC mode. It is for Irix | |
252b5132 RH |
14793 | compatibility. */ |
14794 | case OPTION_XGOT: | |
14795 | mips_big_got = 1; | |
14796 | break; | |
14797 | ||
14798 | case 'G': | |
6caf9ef4 TS |
14799 | g_switch_value = atoi (arg); |
14800 | g_switch_seen = 1; | |
252b5132 RH |
14801 | break; |
14802 | ||
34ba82a8 TS |
14803 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
14804 | and -mabi=64. */ | |
252b5132 | 14805 | case OPTION_32: |
f3ded42a | 14806 | mips_abi = O32_ABI; |
252b5132 RH |
14807 | break; |
14808 | ||
e013f690 | 14809 | case OPTION_N32: |
316f5878 | 14810 | mips_abi = N32_ABI; |
e013f690 | 14811 | break; |
252b5132 | 14812 | |
e013f690 | 14813 | case OPTION_64: |
316f5878 | 14814 | mips_abi = N64_ABI; |
f43abd2b | 14815 | if (!support_64bit_objects()) |
1661c76c | 14816 | as_fatal (_("no compiled in support for 64 bit object file format")); |
252b5132 RH |
14817 | break; |
14818 | ||
c97ef257 | 14819 | case OPTION_GP32: |
bad1aba3 | 14820 | file_mips_opts.gp = 32; |
c97ef257 AH |
14821 | break; |
14822 | ||
14823 | case OPTION_GP64: | |
bad1aba3 | 14824 | file_mips_opts.gp = 64; |
c97ef257 | 14825 | break; |
252b5132 | 14826 | |
ca4e0257 | 14827 | case OPTION_FP32: |
0b35dfee | 14828 | file_mips_opts.fp = 32; |
316f5878 RS |
14829 | break; |
14830 | ||
351cdf24 MF |
14831 | case OPTION_FPXX: |
14832 | file_mips_opts.fp = 0; | |
14833 | break; | |
14834 | ||
316f5878 | 14835 | case OPTION_FP64: |
0b35dfee | 14836 | file_mips_opts.fp = 64; |
ca4e0257 RS |
14837 | break; |
14838 | ||
351cdf24 MF |
14839 | case OPTION_ODD_SPREG: |
14840 | file_mips_opts.oddspreg = 1; | |
14841 | break; | |
14842 | ||
14843 | case OPTION_NO_ODD_SPREG: | |
14844 | file_mips_opts.oddspreg = 0; | |
14845 | break; | |
14846 | ||
037b32b9 | 14847 | case OPTION_SINGLE_FLOAT: |
0b35dfee | 14848 | file_mips_opts.single_float = 1; |
037b32b9 AN |
14849 | break; |
14850 | ||
14851 | case OPTION_DOUBLE_FLOAT: | |
0b35dfee | 14852 | file_mips_opts.single_float = 0; |
037b32b9 AN |
14853 | break; |
14854 | ||
14855 | case OPTION_SOFT_FLOAT: | |
0b35dfee | 14856 | file_mips_opts.soft_float = 1; |
037b32b9 AN |
14857 | break; |
14858 | ||
14859 | case OPTION_HARD_FLOAT: | |
0b35dfee | 14860 | file_mips_opts.soft_float = 0; |
037b32b9 AN |
14861 | break; |
14862 | ||
252b5132 | 14863 | case OPTION_MABI: |
e013f690 | 14864 | if (strcmp (arg, "32") == 0) |
316f5878 | 14865 | mips_abi = O32_ABI; |
e013f690 | 14866 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 14867 | mips_abi = O64_ABI; |
e013f690 | 14868 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 14869 | mips_abi = N32_ABI; |
e013f690 TS |
14870 | else if (strcmp (arg, "64") == 0) |
14871 | { | |
316f5878 | 14872 | mips_abi = N64_ABI; |
e013f690 | 14873 | if (! support_64bit_objects()) |
1661c76c | 14874 | as_fatal (_("no compiled in support for 64 bit object file " |
e013f690 TS |
14875 | "format")); |
14876 | } | |
14877 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 14878 | mips_abi = EABI_ABI; |
e013f690 | 14879 | else |
da0e507f TS |
14880 | { |
14881 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
14882 | return 0; | |
14883 | } | |
252b5132 RH |
14884 | break; |
14885 | ||
6b76fefe | 14886 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 14887 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
14888 | break; |
14889 | ||
9ee72ff1 | 14890 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 14891 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
14892 | break; |
14893 | ||
ecb4347a | 14894 | case OPTION_MDEBUG: |
b34976b6 | 14895 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
14896 | break; |
14897 | ||
14898 | case OPTION_NO_MDEBUG: | |
b34976b6 | 14899 | mips_flag_mdebug = FALSE; |
ecb4347a | 14900 | break; |
dcd410fe RO |
14901 | |
14902 | case OPTION_PDR: | |
14903 | mips_flag_pdr = TRUE; | |
14904 | break; | |
14905 | ||
14906 | case OPTION_NO_PDR: | |
14907 | mips_flag_pdr = FALSE; | |
14908 | break; | |
0a44bf69 RS |
14909 | |
14910 | case OPTION_MVXWORKS_PIC: | |
14911 | mips_pic = VXWORKS_PIC; | |
14912 | break; | |
ecb4347a | 14913 | |
ba92f887 MR |
14914 | case OPTION_NAN: |
14915 | if (strcmp (arg, "2008") == 0) | |
7361da2c | 14916 | mips_nan2008 = 1; |
ba92f887 | 14917 | else if (strcmp (arg, "legacy") == 0) |
7361da2c | 14918 | mips_nan2008 = 0; |
ba92f887 MR |
14919 | else |
14920 | { | |
1661c76c | 14921 | as_fatal (_("invalid NaN setting -mnan=%s"), arg); |
ba92f887 MR |
14922 | return 0; |
14923 | } | |
14924 | break; | |
14925 | ||
252b5132 RH |
14926 | default: |
14927 | return 0; | |
14928 | } | |
14929 | ||
c67a084a NC |
14930 | mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump; |
14931 | ||
252b5132 RH |
14932 | return 1; |
14933 | } | |
316f5878 | 14934 | \f |
919731af | 14935 | /* Set up globals to tune for the ISA or processor described by INFO. */ |
252b5132 | 14936 | |
316f5878 | 14937 | static void |
17a2f251 | 14938 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
14939 | { |
14940 | if (info != 0) | |
fef14a42 | 14941 | mips_tune = info->cpu; |
316f5878 | 14942 | } |
80cc45a5 | 14943 | |
34ba82a8 | 14944 | |
252b5132 | 14945 | void |
17a2f251 | 14946 | mips_after_parse_args (void) |
e9670677 | 14947 | { |
fef14a42 TS |
14948 | const struct mips_cpu_info *arch_info = 0; |
14949 | const struct mips_cpu_info *tune_info = 0; | |
14950 | ||
e9670677 | 14951 | /* GP relative stuff not working for PE */ |
6caf9ef4 | 14952 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
e9670677 | 14953 | { |
6caf9ef4 | 14954 | if (g_switch_seen && g_switch_value != 0) |
1661c76c | 14955 | as_bad (_("-G not supported in this configuration")); |
e9670677 MR |
14956 | g_switch_value = 0; |
14957 | } | |
14958 | ||
cac012d6 AO |
14959 | if (mips_abi == NO_ABI) |
14960 | mips_abi = MIPS_DEFAULT_ABI; | |
14961 | ||
919731af | 14962 | /* The following code determines the architecture. |
22923709 RS |
14963 | Similar code was added to GCC 3.3 (see override_options() in |
14964 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
14965 | as much as possible. */ | |
e9670677 | 14966 | |
316f5878 | 14967 | if (mips_arch_string != 0) |
fef14a42 | 14968 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 14969 | |
0b35dfee | 14970 | if (file_mips_opts.isa != ISA_UNKNOWN) |
e9670677 | 14971 | { |
0b35dfee | 14972 | /* Handle -mipsN. At this point, file_mips_opts.isa contains the |
fef14a42 | 14973 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 14974 | the -march selection (if any). */ |
fef14a42 | 14975 | if (arch_info != 0) |
e9670677 | 14976 | { |
316f5878 RS |
14977 | /* -march takes precedence over -mipsN, since it is more descriptive. |
14978 | There's no harm in specifying both as long as the ISA levels | |
14979 | are the same. */ | |
0b35dfee | 14980 | if (file_mips_opts.isa != arch_info->isa) |
1661c76c RS |
14981 | as_bad (_("-%s conflicts with the other architecture options," |
14982 | " which imply -%s"), | |
0b35dfee | 14983 | mips_cpu_info_from_isa (file_mips_opts.isa)->name, |
fef14a42 | 14984 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 14985 | } |
316f5878 | 14986 | else |
0b35dfee | 14987 | arch_info = mips_cpu_info_from_isa (file_mips_opts.isa); |
e9670677 MR |
14988 | } |
14989 | ||
fef14a42 | 14990 | if (arch_info == 0) |
95bfe26e MF |
14991 | { |
14992 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
14993 | gas_assert (arch_info); | |
14994 | } | |
e9670677 | 14995 | |
fef14a42 | 14996 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
20203fb9 | 14997 | as_bad (_("-march=%s is not compatible with the selected ABI"), |
fef14a42 TS |
14998 | arch_info->name); |
14999 | ||
919731af | 15000 | file_mips_opts.arch = arch_info->cpu; |
15001 | file_mips_opts.isa = arch_info->isa; | |
15002 | ||
15003 | /* Set up initial mips_opts state. */ | |
15004 | mips_opts = file_mips_opts; | |
15005 | ||
15006 | /* The register size inference code is now placed in | |
15007 | file_mips_check_options. */ | |
fef14a42 | 15008 | |
0b35dfee | 15009 | /* Optimize for file_mips_opts.arch, unless -mtune selects a different |
15010 | processor. */ | |
fef14a42 TS |
15011 | if (mips_tune_string != 0) |
15012 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 15013 | |
fef14a42 TS |
15014 | if (tune_info == 0) |
15015 | mips_set_tune (arch_info); | |
15016 | else | |
15017 | mips_set_tune (tune_info); | |
e9670677 | 15018 | |
ecb4347a | 15019 | if (mips_flag_mdebug < 0) |
e8044f35 | 15020 | mips_flag_mdebug = 0; |
e9670677 MR |
15021 | } |
15022 | \f | |
15023 | void | |
17a2f251 | 15024 | mips_init_after_args (void) |
252b5132 RH |
15025 | { |
15026 | /* initialize opcodes */ | |
15027 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 15028 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
15029 | } |
15030 | ||
15031 | long | |
17a2f251 | 15032 | md_pcrel_from (fixS *fixP) |
252b5132 | 15033 | { |
a7ebbfdf TS |
15034 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
15035 | switch (fixP->fx_r_type) | |
15036 | { | |
df58fc94 RS |
15037 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15038 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15039 | /* Return the address of the delay slot. */ | |
15040 | return addr + 2; | |
15041 | ||
15042 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15043 | case BFD_RELOC_MICROMIPS_JMP: | |
c9775dde | 15044 | case BFD_RELOC_MIPS16_16_PCREL_S1: |
a7ebbfdf | 15045 | case BFD_RELOC_16_PCREL_S2: |
7361da2c AB |
15046 | case BFD_RELOC_MIPS_21_PCREL_S2: |
15047 | case BFD_RELOC_MIPS_26_PCREL_S2: | |
a7ebbfdf TS |
15048 | case BFD_RELOC_MIPS_JMP: |
15049 | /* Return the address of the delay slot. */ | |
15050 | return addr + 4; | |
df58fc94 | 15051 | |
51f6035b MR |
15052 | case BFD_RELOC_MIPS_18_PCREL_S3: |
15053 | /* Return the aligned address of the doubleword containing | |
15054 | the instruction. */ | |
15055 | return addr & ~7; | |
15056 | ||
a7ebbfdf TS |
15057 | default: |
15058 | return addr; | |
15059 | } | |
252b5132 RH |
15060 | } |
15061 | ||
252b5132 RH |
15062 | /* This is called before the symbol table is processed. In order to |
15063 | work with gcc when using mips-tfile, we must keep all local labels. | |
15064 | However, in other cases, we want to discard them. If we were | |
15065 | called with -g, but we didn't see any debugging information, it may | |
15066 | mean that gcc is smuggling debugging information through to | |
15067 | mips-tfile, in which case we must generate all local labels. */ | |
15068 | ||
15069 | void | |
17a2f251 | 15070 | mips_frob_file_before_adjust (void) |
252b5132 RH |
15071 | { |
15072 | #ifndef NO_ECOFF_DEBUGGING | |
15073 | if (ECOFF_DEBUGGING | |
15074 | && mips_debug != 0 | |
15075 | && ! ecoff_debugging_seen) | |
15076 | flag_keep_locals = 1; | |
15077 | #endif | |
15078 | } | |
15079 | ||
3b91255e | 15080 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
55cf6793 | 15081 | the corresponding LO16 reloc. This is called before md_apply_fix and |
3b91255e RS |
15082 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit |
15083 | relocation operators. | |
15084 | ||
15085 | For our purposes, a %lo() expression matches a %got() or %hi() | |
15086 | expression if: | |
15087 | ||
15088 | (a) it refers to the same symbol; and | |
15089 | (b) the offset applied in the %lo() expression is no lower than | |
15090 | the offset applied in the %got() or %hi(). | |
15091 | ||
15092 | (b) allows us to cope with code like: | |
15093 | ||
15094 | lui $4,%hi(foo) | |
15095 | lh $4,%lo(foo+2)($4) | |
15096 | ||
15097 | ...which is legal on RELA targets, and has a well-defined behaviour | |
15098 | if the user knows that adding 2 to "foo" will not induce a carry to | |
15099 | the high 16 bits. | |
15100 | ||
15101 | When several %lo()s match a particular %got() or %hi(), we use the | |
15102 | following rules to distinguish them: | |
15103 | ||
15104 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
15105 | higher offsets. | |
15106 | ||
15107 | (2) %lo()s with no matching %got() or %hi() are better than those | |
15108 | that already have a matching %got() or %hi(). | |
15109 | ||
15110 | (3) later %lo()s are better than earlier %lo()s. | |
15111 | ||
15112 | These rules are applied in order. | |
15113 | ||
15114 | (1) means, among other things, that %lo()s with identical offsets are | |
15115 | chosen if they exist. | |
15116 | ||
15117 | (2) means that we won't associate several high-part relocations with | |
15118 | the same low-part relocation unless there's no alternative. Having | |
15119 | several high parts for the same low part is a GNU extension; this rule | |
15120 | allows careful users to avoid it. | |
15121 | ||
15122 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
15123 | with the last high-part relocation being at the front of the list. | |
15124 | It therefore makes sense to choose the last matching low-part | |
15125 | relocation, all other things being equal. It's also easier | |
15126 | to code that way. */ | |
252b5132 RH |
15127 | |
15128 | void | |
17a2f251 | 15129 | mips_frob_file (void) |
252b5132 RH |
15130 | { |
15131 | struct mips_hi_fixup *l; | |
35903be0 | 15132 | bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED; |
252b5132 RH |
15133 | |
15134 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
15135 | { | |
15136 | segment_info_type *seginfo; | |
3b91255e RS |
15137 | bfd_boolean matched_lo_p; |
15138 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 15139 | |
9c2799c2 | 15140 | gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 15141 | |
5919d012 | 15142 | /* If a GOT16 relocation turns out to be against a global symbol, |
b886a2ab RS |
15143 | there isn't supposed to be a matching LO. Ignore %gots against |
15144 | constants; we'll report an error for those later. */ | |
738e5348 | 15145 | if (got16_reloc_p (l->fixp->fx_r_type) |
b886a2ab | 15146 | && !(l->fixp->fx_addsy |
9e009953 | 15147 | && pic_need_relax (l->fixp->fx_addsy))) |
5919d012 RS |
15148 | continue; |
15149 | ||
15150 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
15151 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
15152 | continue; |
15153 | ||
252b5132 | 15154 | seginfo = seg_info (l->seg); |
252b5132 | 15155 | |
3b91255e RS |
15156 | /* Set HI_POS to the position of this relocation in the chain. |
15157 | Set LO_POS to the position of the chosen low-part relocation. | |
15158 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
15159 | relocation that matches an immediately-preceding high-part | |
15160 | relocation. */ | |
15161 | hi_pos = NULL; | |
15162 | lo_pos = NULL; | |
15163 | matched_lo_p = FALSE; | |
738e5348 | 15164 | looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type); |
35903be0 | 15165 | |
3b91255e RS |
15166 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) |
15167 | { | |
15168 | if (*pos == l->fixp) | |
15169 | hi_pos = pos; | |
15170 | ||
35903be0 | 15171 | if ((*pos)->fx_r_type == looking_for_rtype |
30cfc97a | 15172 | && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy) |
3b91255e RS |
15173 | && (*pos)->fx_offset >= l->fixp->fx_offset |
15174 | && (lo_pos == NULL | |
15175 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
15176 | || (!matched_lo_p | |
15177 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
15178 | lo_pos = pos; | |
15179 | ||
15180 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
15181 | && fixup_has_matching_lo_p (*pos)); | |
15182 | } | |
15183 | ||
15184 | /* If we found a match, remove the high-part relocation from its | |
15185 | current position and insert it before the low-part relocation. | |
15186 | Make the offsets match so that fixup_has_matching_lo_p() | |
15187 | will return true. | |
15188 | ||
15189 | We don't warn about unmatched high-part relocations since some | |
15190 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
15191 | instructions. */ | |
15192 | if (lo_pos != NULL) | |
15193 | { | |
15194 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
15195 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 15196 | { |
3b91255e RS |
15197 | *hi_pos = l->fixp->fx_next; |
15198 | l->fixp->fx_next = *lo_pos; | |
15199 | *lo_pos = l->fixp; | |
252b5132 | 15200 | } |
252b5132 RH |
15201 | } |
15202 | } | |
15203 | } | |
15204 | ||
252b5132 | 15205 | int |
17a2f251 | 15206 | mips_force_relocation (fixS *fixp) |
252b5132 | 15207 | { |
ae6063d4 | 15208 | if (generic_force_reloc (fixp)) |
252b5132 RH |
15209 | return 1; |
15210 | ||
df58fc94 RS |
15211 | /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation, |
15212 | so that the linker relaxation can update targets. */ | |
15213 | if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
15214 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
15215 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1) | |
15216 | return 1; | |
15217 | ||
5caa2b07 MR |
15218 | /* We want to keep BFD_RELOC_16_PCREL_S2 BFD_RELOC_MIPS_21_PCREL_S2 |
15219 | and BFD_RELOC_MIPS_26_PCREL_S2 relocations against MIPS16 and | |
15220 | microMIPS symbols so that we can do cross-mode branch diagnostics | |
15221 | and BAL to JALX conversion by the linker. */ | |
15222 | if ((fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 | |
9d862524 MR |
15223 | || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2 |
15224 | || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2) | |
15225 | && fixp->fx_addsy | |
15226 | && ELF_ST_IS_COMPRESSED (S_GET_OTHER (fixp->fx_addsy))) | |
15227 | return 1; | |
15228 | ||
7361da2c | 15229 | /* We want all PC-relative relocations to be kept for R6 relaxation. */ |
912815f0 | 15230 | if (ISA_IS_R6 (file_mips_opts.isa) |
7361da2c AB |
15231 | && (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 |
15232 | || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2 | |
15233 | || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2 | |
15234 | || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3 | |
15235 | || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2 | |
15236 | || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL | |
15237 | || fixp->fx_r_type == BFD_RELOC_LO16_PCREL)) | |
15238 | return 1; | |
15239 | ||
3e722fb5 | 15240 | return 0; |
252b5132 RH |
15241 | } |
15242 | ||
b416ba9b MR |
15243 | /* Implement TC_FORCE_RELOCATION_ABS. */ |
15244 | ||
15245 | bfd_boolean | |
15246 | mips_force_relocation_abs (fixS *fixp) | |
15247 | { | |
15248 | if (generic_force_reloc (fixp)) | |
15249 | return TRUE; | |
15250 | ||
15251 | /* These relocations do not have enough bits in the in-place addend | |
15252 | to hold an arbitrary absolute section's offset. */ | |
15253 | if (HAVE_IN_PLACE_ADDENDS && limited_pcrel_reloc_p (fixp->fx_r_type)) | |
15254 | return TRUE; | |
15255 | ||
15256 | return FALSE; | |
15257 | } | |
15258 | ||
b886a2ab RS |
15259 | /* Read the instruction associated with RELOC from BUF. */ |
15260 | ||
15261 | static unsigned int | |
15262 | read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc) | |
15263 | { | |
15264 | if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) | |
15265 | return read_compressed_insn (buf, 4); | |
15266 | else | |
15267 | return read_insn (buf); | |
15268 | } | |
15269 | ||
15270 | /* Write instruction INSN to BUF, given that it has been relocated | |
15271 | by RELOC. */ | |
15272 | ||
15273 | static void | |
15274 | write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc, | |
15275 | unsigned long insn) | |
15276 | { | |
15277 | if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) | |
15278 | write_compressed_insn (buf, insn, 4); | |
15279 | else | |
15280 | write_insn (buf, insn); | |
15281 | } | |
15282 | ||
9d862524 MR |
15283 | /* Return TRUE if the instruction pointed to by FIXP is an invalid jump |
15284 | to a symbol in another ISA mode, which cannot be converted to JALX. */ | |
15285 | ||
15286 | static bfd_boolean | |
15287 | fix_bad_cross_mode_jump_p (fixS *fixP) | |
15288 | { | |
15289 | unsigned long opcode; | |
15290 | int other; | |
15291 | char *buf; | |
15292 | ||
15293 | if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) | |
15294 | return FALSE; | |
15295 | ||
15296 | other = S_GET_OTHER (fixP->fx_addsy); | |
15297 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; | |
15298 | opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 26; | |
15299 | switch (fixP->fx_r_type) | |
15300 | { | |
15301 | case BFD_RELOC_MIPS_JMP: | |
15302 | return opcode != 0x1d && opcode != 0x03 && ELF_ST_IS_COMPRESSED (other); | |
15303 | case BFD_RELOC_MICROMIPS_JMP: | |
15304 | return opcode != 0x3c && opcode != 0x3d && !ELF_ST_IS_MICROMIPS (other); | |
15305 | default: | |
15306 | return FALSE; | |
15307 | } | |
15308 | } | |
15309 | ||
15310 | /* Return TRUE if the instruction pointed to by FIXP is an invalid JALX | |
15311 | jump to a symbol in the same ISA mode. */ | |
15312 | ||
15313 | static bfd_boolean | |
15314 | fix_bad_same_mode_jalx_p (fixS *fixP) | |
15315 | { | |
15316 | unsigned long opcode; | |
15317 | int other; | |
15318 | char *buf; | |
15319 | ||
15320 | if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) | |
15321 | return FALSE; | |
15322 | ||
15323 | other = S_GET_OTHER (fixP->fx_addsy); | |
15324 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; | |
15325 | opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 26; | |
15326 | switch (fixP->fx_r_type) | |
15327 | { | |
15328 | case BFD_RELOC_MIPS_JMP: | |
15329 | return opcode == 0x1d && !ELF_ST_IS_COMPRESSED (other); | |
15330 | case BFD_RELOC_MIPS16_JMP: | |
15331 | return opcode == 0x07 && ELF_ST_IS_COMPRESSED (other); | |
15332 | case BFD_RELOC_MICROMIPS_JMP: | |
15333 | return opcode == 0x3c && ELF_ST_IS_COMPRESSED (other); | |
15334 | default: | |
15335 | return FALSE; | |
15336 | } | |
15337 | } | |
15338 | ||
15339 | /* Return TRUE if the instruction pointed to by FIXP is an invalid jump | |
15340 | to a symbol whose value plus addend is not aligned according to the | |
15341 | ultimate (after linker relaxation) jump instruction's immediate field | |
15342 | requirement, either to (1 << SHIFT), or, for jumps from microMIPS to | |
15343 | regular MIPS code, to (1 << 2). */ | |
15344 | ||
15345 | static bfd_boolean | |
15346 | fix_bad_misaligned_jump_p (fixS *fixP, int shift) | |
15347 | { | |
15348 | bfd_boolean micro_to_mips_p; | |
15349 | valueT val; | |
15350 | int other; | |
15351 | ||
15352 | if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) | |
15353 | return FALSE; | |
15354 | ||
15355 | other = S_GET_OTHER (fixP->fx_addsy); | |
15356 | val = S_GET_VALUE (fixP->fx_addsy) | ELF_ST_IS_COMPRESSED (other); | |
15357 | val += fixP->fx_offset; | |
15358 | micro_to_mips_p = (fixP->fx_r_type == BFD_RELOC_MICROMIPS_JMP | |
15359 | && !ELF_ST_IS_MICROMIPS (other)); | |
15360 | return ((val & ((1 << (micro_to_mips_p ? 2 : shift)) - 1)) | |
15361 | != ELF_ST_IS_COMPRESSED (other)); | |
15362 | } | |
15363 | ||
15364 | /* Return TRUE if the instruction pointed to by FIXP is an invalid branch | |
15365 | to a symbol whose annotation indicates another ISA mode. For absolute | |
a6ebf616 MR |
15366 | symbols check the ISA bit instead. |
15367 | ||
15368 | We accept BFD_RELOC_16_PCREL_S2 relocations against MIPS16 and microMIPS | |
15369 | symbols or BFD_RELOC_MICROMIPS_16_PCREL_S1 relocations against regular | |
15370 | MIPS symbols and associated with BAL instructions as these instructions | |
de194d85 | 15371 | may be converted to JALX by the linker. */ |
9d862524 MR |
15372 | |
15373 | static bfd_boolean | |
15374 | fix_bad_cross_mode_branch_p (fixS *fixP) | |
15375 | { | |
15376 | bfd_boolean absolute_p; | |
15377 | unsigned long opcode; | |
15378 | asection *symsec; | |
15379 | valueT val; | |
15380 | int other; | |
15381 | char *buf; | |
15382 | ||
8b10b0b3 MR |
15383 | if (mips_ignore_branch_isa) |
15384 | return FALSE; | |
15385 | ||
9d862524 MR |
15386 | if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) |
15387 | return FALSE; | |
15388 | ||
15389 | symsec = S_GET_SEGMENT (fixP->fx_addsy); | |
15390 | absolute_p = bfd_is_abs_section (symsec); | |
15391 | ||
15392 | val = S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset; | |
15393 | other = S_GET_OTHER (fixP->fx_addsy); | |
15394 | ||
15395 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; | |
15396 | opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 16; | |
15397 | switch (fixP->fx_r_type) | |
15398 | { | |
15399 | case BFD_RELOC_16_PCREL_S2: | |
a6ebf616 MR |
15400 | return ((absolute_p ? val & 1 : ELF_ST_IS_COMPRESSED (other)) |
15401 | && opcode != 0x0411); | |
15402 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15403 | return ((absolute_p ? !(val & 1) : !ELF_ST_IS_MICROMIPS (other)) | |
15404 | && opcode != 0x4060); | |
9d862524 MR |
15405 | case BFD_RELOC_MIPS_21_PCREL_S2: |
15406 | case BFD_RELOC_MIPS_26_PCREL_S2: | |
15407 | return absolute_p ? val & 1 : ELF_ST_IS_COMPRESSED (other); | |
15408 | case BFD_RELOC_MIPS16_16_PCREL_S1: | |
15409 | return absolute_p ? !(val & 1) : !ELF_ST_IS_MIPS16 (other); | |
15410 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: | |
15411 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
9d862524 MR |
15412 | return absolute_p ? !(val & 1) : !ELF_ST_IS_MICROMIPS (other); |
15413 | default: | |
15414 | abort (); | |
15415 | } | |
15416 | } | |
15417 | ||
15418 | /* Return TRUE if the symbol plus addend associated with a regular MIPS | |
15419 | branch instruction pointed to by FIXP is not aligned according to the | |
15420 | branch instruction's immediate field requirement. We need the addend | |
15421 | to preserve the ISA bit and also the sum must not have bit 2 set. We | |
15422 | must explicitly OR in the ISA bit from symbol annotation as the bit | |
15423 | won't be set in the symbol's value then. */ | |
15424 | ||
15425 | static bfd_boolean | |
15426 | fix_bad_misaligned_branch_p (fixS *fixP) | |
15427 | { | |
15428 | bfd_boolean absolute_p; | |
15429 | asection *symsec; | |
15430 | valueT isa_bit; | |
15431 | valueT val; | |
15432 | valueT off; | |
15433 | int other; | |
15434 | ||
15435 | if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) | |
15436 | return FALSE; | |
15437 | ||
15438 | symsec = S_GET_SEGMENT (fixP->fx_addsy); | |
15439 | absolute_p = bfd_is_abs_section (symsec); | |
15440 | ||
15441 | val = S_GET_VALUE (fixP->fx_addsy); | |
15442 | other = S_GET_OTHER (fixP->fx_addsy); | |
15443 | off = fixP->fx_offset; | |
15444 | ||
15445 | isa_bit = absolute_p ? (val + off) & 1 : ELF_ST_IS_COMPRESSED (other); | |
15446 | val |= ELF_ST_IS_COMPRESSED (other); | |
15447 | val += off; | |
15448 | return (val & 0x3) != isa_bit; | |
15449 | } | |
15450 | ||
15451 | /* Make the necessary checks on a regular MIPS branch pointed to by FIXP | |
15452 | and its calculated value VAL. */ | |
15453 | ||
15454 | static void | |
15455 | fix_validate_branch (fixS *fixP, valueT val) | |
15456 | { | |
15457 | if (fixP->fx_done && (val & 0x3) != 0) | |
15458 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15459 | _("branch to misaligned address (0x%lx)"), | |
15460 | (long) (val + md_pcrel_from (fixP))); | |
15461 | else if (fix_bad_cross_mode_branch_p (fixP)) | |
15462 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15463 | _("branch to a symbol in another ISA mode")); | |
15464 | else if (fix_bad_misaligned_branch_p (fixP)) | |
15465 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15466 | _("branch to misaligned address (0x%lx)"), | |
15467 | (long) (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset)); | |
15468 | else if (HAVE_IN_PLACE_ADDENDS && (fixP->fx_offset & 0x3) != 0) | |
15469 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15470 | _("cannot encode misaligned addend " | |
15471 | "in the relocatable field (0x%lx)"), | |
15472 | (long) fixP->fx_offset); | |
15473 | } | |
15474 | ||
252b5132 RH |
15475 | /* Apply a fixup to the object file. */ |
15476 | ||
94f592af | 15477 | void |
55cf6793 | 15478 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 15479 | { |
4d68580a | 15480 | char *buf; |
b886a2ab | 15481 | unsigned long insn; |
a7ebbfdf | 15482 | reloc_howto_type *howto; |
252b5132 | 15483 | |
d56a8dda RS |
15484 | if (fixP->fx_pcrel) |
15485 | switch (fixP->fx_r_type) | |
15486 | { | |
15487 | case BFD_RELOC_16_PCREL_S2: | |
c9775dde | 15488 | case BFD_RELOC_MIPS16_16_PCREL_S1: |
d56a8dda RS |
15489 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15490 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15491 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15492 | case BFD_RELOC_32_PCREL: | |
7361da2c AB |
15493 | case BFD_RELOC_MIPS_21_PCREL_S2: |
15494 | case BFD_RELOC_MIPS_26_PCREL_S2: | |
15495 | case BFD_RELOC_MIPS_18_PCREL_S3: | |
15496 | case BFD_RELOC_MIPS_19_PCREL_S2: | |
15497 | case BFD_RELOC_HI16_S_PCREL: | |
15498 | case BFD_RELOC_LO16_PCREL: | |
d56a8dda RS |
15499 | break; |
15500 | ||
15501 | case BFD_RELOC_32: | |
15502 | fixP->fx_r_type = BFD_RELOC_32_PCREL; | |
15503 | break; | |
15504 | ||
15505 | default: | |
15506 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15507 | _("PC-relative reference to a different section")); | |
15508 | break; | |
15509 | } | |
15510 | ||
15511 | /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations | |
15512 | that have no MIPS ELF equivalent. */ | |
15513 | if (fixP->fx_r_type != BFD_RELOC_8) | |
15514 | { | |
15515 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
15516 | if (!howto) | |
15517 | return; | |
15518 | } | |
65551fa4 | 15519 | |
df58fc94 RS |
15520 | gas_assert (fixP->fx_size == 2 |
15521 | || fixP->fx_size == 4 | |
d56a8dda | 15522 | || fixP->fx_r_type == BFD_RELOC_8 |
90ecf173 MR |
15523 | || fixP->fx_r_type == BFD_RELOC_16 |
15524 | || fixP->fx_r_type == BFD_RELOC_64 | |
15525 | || fixP->fx_r_type == BFD_RELOC_CTOR | |
15526 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
df58fc94 | 15527 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB |
90ecf173 MR |
15528 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
15529 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY | |
2f0c68f2 CM |
15530 | || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64 |
15531 | || fixP->fx_r_type == BFD_RELOC_NONE); | |
252b5132 | 15532 | |
4d68580a | 15533 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; |
252b5132 | 15534 | |
b1dca8ee RS |
15535 | /* Don't treat parts of a composite relocation as done. There are two |
15536 | reasons for this: | |
15537 | ||
15538 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
15539 | should nevertheless be emitted if the first part is. | |
15540 | ||
15541 | (2) In normal usage, composite relocations are never assembly-time | |
15542 | constants. The easiest way of dealing with the pathological | |
15543 | exceptions is to generate a relocation against STN_UNDEF and | |
15544 | leave everything up to the linker. */ | |
3994f87e | 15545 | if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0) |
252b5132 RH |
15546 | fixP->fx_done = 1; |
15547 | ||
15548 | switch (fixP->fx_r_type) | |
15549 | { | |
3f98094e DJ |
15550 | case BFD_RELOC_MIPS_TLS_GD: |
15551 | case BFD_RELOC_MIPS_TLS_LDM: | |
741d6ea8 JM |
15552 | case BFD_RELOC_MIPS_TLS_DTPREL32: |
15553 | case BFD_RELOC_MIPS_TLS_DTPREL64: | |
3f98094e DJ |
15554 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: |
15555 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
15556 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
d0f13682 CLT |
15557 | case BFD_RELOC_MIPS_TLS_TPREL32: |
15558 | case BFD_RELOC_MIPS_TLS_TPREL64: | |
3f98094e DJ |
15559 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: |
15560 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
df58fc94 RS |
15561 | case BFD_RELOC_MICROMIPS_TLS_GD: |
15562 | case BFD_RELOC_MICROMIPS_TLS_LDM: | |
15563 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16: | |
15564 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16: | |
15565 | case BFD_RELOC_MICROMIPS_TLS_GOTTPREL: | |
15566 | case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16: | |
15567 | case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16: | |
d0f13682 CLT |
15568 | case BFD_RELOC_MIPS16_TLS_GD: |
15569 | case BFD_RELOC_MIPS16_TLS_LDM: | |
15570 | case BFD_RELOC_MIPS16_TLS_DTPREL_HI16: | |
15571 | case BFD_RELOC_MIPS16_TLS_DTPREL_LO16: | |
15572 | case BFD_RELOC_MIPS16_TLS_GOTTPREL: | |
15573 | case BFD_RELOC_MIPS16_TLS_TPREL_HI16: | |
15574 | case BFD_RELOC_MIPS16_TLS_TPREL_LO16: | |
4512dafa MR |
15575 | if (fixP->fx_addsy) |
15576 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
15577 | else | |
15578 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15579 | _("TLS relocation against a constant")); | |
15580 | break; | |
3f98094e | 15581 | |
252b5132 | 15582 | case BFD_RELOC_MIPS_JMP: |
9d862524 MR |
15583 | case BFD_RELOC_MIPS16_JMP: |
15584 | case BFD_RELOC_MICROMIPS_JMP: | |
15585 | { | |
15586 | int shift; | |
15587 | ||
15588 | gas_assert (!fixP->fx_done); | |
15589 | ||
15590 | /* Shift is 2, unusually, for microMIPS JALX. */ | |
15591 | if (fixP->fx_r_type == BFD_RELOC_MICROMIPS_JMP | |
15592 | && (read_compressed_insn (buf, 4) >> 26) != 0x3c) | |
15593 | shift = 1; | |
15594 | else | |
15595 | shift = 2; | |
15596 | ||
15597 | if (fix_bad_cross_mode_jump_p (fixP)) | |
15598 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15599 | _("jump to a symbol in another ISA mode")); | |
15600 | else if (fix_bad_same_mode_jalx_p (fixP)) | |
15601 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15602 | _("JALX to a symbol in the same ISA mode")); | |
15603 | else if (fix_bad_misaligned_jump_p (fixP, shift)) | |
15604 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15605 | _("jump to misaligned address (0x%lx)"), | |
15606 | (long) (S_GET_VALUE (fixP->fx_addsy) | |
15607 | + fixP->fx_offset)); | |
15608 | else if (HAVE_IN_PLACE_ADDENDS | |
15609 | && (fixP->fx_offset & ((1 << shift) - 1)) != 0) | |
15610 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15611 | _("cannot encode misaligned addend " | |
15612 | "in the relocatable field (0x%lx)"), | |
15613 | (long) fixP->fx_offset); | |
15614 | } | |
15615 | /* Fall through. */ | |
15616 | ||
e369bcce TS |
15617 | case BFD_RELOC_MIPS_SHIFT5: |
15618 | case BFD_RELOC_MIPS_SHIFT6: | |
15619 | case BFD_RELOC_MIPS_GOT_DISP: | |
15620 | case BFD_RELOC_MIPS_GOT_PAGE: | |
15621 | case BFD_RELOC_MIPS_GOT_OFST: | |
15622 | case BFD_RELOC_MIPS_SUB: | |
15623 | case BFD_RELOC_MIPS_INSERT_A: | |
15624 | case BFD_RELOC_MIPS_INSERT_B: | |
15625 | case BFD_RELOC_MIPS_DELETE: | |
15626 | case BFD_RELOC_MIPS_HIGHEST: | |
15627 | case BFD_RELOC_MIPS_HIGHER: | |
15628 | case BFD_RELOC_MIPS_SCN_DISP: | |
15629 | case BFD_RELOC_MIPS_REL16: | |
15630 | case BFD_RELOC_MIPS_RELGOT: | |
15631 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
15632 | case BFD_RELOC_HI16: |
15633 | case BFD_RELOC_HI16_S: | |
b886a2ab | 15634 | case BFD_RELOC_LO16: |
cdf6fd85 | 15635 | case BFD_RELOC_GPREL16: |
252b5132 RH |
15636 | case BFD_RELOC_MIPS_LITERAL: |
15637 | case BFD_RELOC_MIPS_CALL16: | |
15638 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 15639 | case BFD_RELOC_GPREL32: |
252b5132 RH |
15640 | case BFD_RELOC_MIPS_GOT_HI16: |
15641 | case BFD_RELOC_MIPS_GOT_LO16: | |
15642 | case BFD_RELOC_MIPS_CALL_HI16: | |
15643 | case BFD_RELOC_MIPS_CALL_LO16: | |
41947d9e MR |
15644 | case BFD_RELOC_HI16_S_PCREL: |
15645 | case BFD_RELOC_LO16_PCREL: | |
252b5132 | 15646 | case BFD_RELOC_MIPS16_GPREL: |
738e5348 RS |
15647 | case BFD_RELOC_MIPS16_GOT16: |
15648 | case BFD_RELOC_MIPS16_CALL16: | |
d6f16593 MR |
15649 | case BFD_RELOC_MIPS16_HI16: |
15650 | case BFD_RELOC_MIPS16_HI16_S: | |
b886a2ab | 15651 | case BFD_RELOC_MIPS16_LO16: |
df58fc94 RS |
15652 | case BFD_RELOC_MICROMIPS_GOT_DISP: |
15653 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
15654 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
15655 | case BFD_RELOC_MICROMIPS_SUB: | |
15656 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
15657 | case BFD_RELOC_MICROMIPS_HIGHER: | |
15658 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
15659 | case BFD_RELOC_MICROMIPS_JALR: | |
15660 | case BFD_RELOC_MICROMIPS_HI16: | |
15661 | case BFD_RELOC_MICROMIPS_HI16_S: | |
b886a2ab | 15662 | case BFD_RELOC_MICROMIPS_LO16: |
df58fc94 RS |
15663 | case BFD_RELOC_MICROMIPS_GPREL16: |
15664 | case BFD_RELOC_MICROMIPS_LITERAL: | |
15665 | case BFD_RELOC_MICROMIPS_CALL16: | |
15666 | case BFD_RELOC_MICROMIPS_GOT16: | |
15667 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
15668 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
15669 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
15670 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
067ec077 | 15671 | case BFD_RELOC_MIPS_EH: |
b886a2ab RS |
15672 | if (fixP->fx_done) |
15673 | { | |
15674 | offsetT value; | |
15675 | ||
15676 | if (calculate_reloc (fixP->fx_r_type, *valP, &value)) | |
15677 | { | |
15678 | insn = read_reloc_insn (buf, fixP->fx_r_type); | |
15679 | if (mips16_reloc_p (fixP->fx_r_type)) | |
15680 | insn |= mips16_immed_extend (value, 16); | |
15681 | else | |
15682 | insn |= (value & 0xffff); | |
15683 | write_reloc_insn (buf, fixP->fx_r_type, insn); | |
15684 | } | |
15685 | else | |
15686 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
1661c76c | 15687 | _("unsupported constant in relocation")); |
b886a2ab | 15688 | } |
252b5132 RH |
15689 | break; |
15690 | ||
252b5132 RH |
15691 | case BFD_RELOC_64: |
15692 | /* This is handled like BFD_RELOC_32, but we output a sign | |
15693 | extended value if we are only 32 bits. */ | |
3e722fb5 | 15694 | if (fixP->fx_done) |
252b5132 RH |
15695 | { |
15696 | if (8 <= sizeof (valueT)) | |
4d68580a | 15697 | md_number_to_chars (buf, *valP, 8); |
252b5132 RH |
15698 | else |
15699 | { | |
a7ebbfdf | 15700 | valueT hiv; |
252b5132 | 15701 | |
a7ebbfdf | 15702 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
15703 | hiv = 0xffffffff; |
15704 | else | |
15705 | hiv = 0; | |
4d68580a RS |
15706 | md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4); |
15707 | md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4); | |
252b5132 RH |
15708 | } |
15709 | } | |
15710 | break; | |
15711 | ||
056350c6 | 15712 | case BFD_RELOC_RVA: |
252b5132 | 15713 | case BFD_RELOC_32: |
b47468a6 | 15714 | case BFD_RELOC_32_PCREL: |
252b5132 | 15715 | case BFD_RELOC_16: |
d56a8dda | 15716 | case BFD_RELOC_8: |
252b5132 | 15717 | /* If we are deleting this reloc entry, we must fill in the |
54f4ddb3 TS |
15718 | value now. This can happen if we have a .word which is not |
15719 | resolved when it appears but is later defined. */ | |
252b5132 | 15720 | if (fixP->fx_done) |
4d68580a | 15721 | md_number_to_chars (buf, *valP, fixP->fx_size); |
252b5132 RH |
15722 | break; |
15723 | ||
7361da2c | 15724 | case BFD_RELOC_MIPS_21_PCREL_S2: |
9d862524 | 15725 | fix_validate_branch (fixP, *valP); |
41947d9e MR |
15726 | if (!fixP->fx_done) |
15727 | break; | |
15728 | ||
15729 | if (*valP + 0x400000 <= 0x7fffff) | |
15730 | { | |
15731 | insn = read_insn (buf); | |
15732 | insn |= (*valP >> 2) & 0x1fffff; | |
15733 | write_insn (buf, insn); | |
15734 | } | |
15735 | else | |
15736 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15737 | _("branch out of range")); | |
15738 | break; | |
15739 | ||
7361da2c | 15740 | case BFD_RELOC_MIPS_26_PCREL_S2: |
9d862524 | 15741 | fix_validate_branch (fixP, *valP); |
41947d9e MR |
15742 | if (!fixP->fx_done) |
15743 | break; | |
7361da2c | 15744 | |
41947d9e MR |
15745 | if (*valP + 0x8000000 <= 0xfffffff) |
15746 | { | |
15747 | insn = read_insn (buf); | |
15748 | insn |= (*valP >> 2) & 0x3ffffff; | |
15749 | write_insn (buf, insn); | |
15750 | } | |
15751 | else | |
15752 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15753 | _("branch out of range")); | |
7361da2c AB |
15754 | break; |
15755 | ||
15756 | case BFD_RELOC_MIPS_18_PCREL_S3: | |
717ba204 | 15757 | if (fixP->fx_addsy && (S_GET_VALUE (fixP->fx_addsy) & 0x7) != 0) |
7361da2c | 15758 | as_bad_where (fixP->fx_file, fixP->fx_line, |
0866e94c MF |
15759 | _("PC-relative access using misaligned symbol (%lx)"), |
15760 | (long) S_GET_VALUE (fixP->fx_addsy)); | |
15761 | if ((fixP->fx_offset & 0x7) != 0) | |
15762 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15763 | _("PC-relative access using misaligned offset (%lx)"), | |
15764 | (long) fixP->fx_offset); | |
41947d9e MR |
15765 | if (!fixP->fx_done) |
15766 | break; | |
7361da2c | 15767 | |
41947d9e MR |
15768 | if (*valP + 0x100000 <= 0x1fffff) |
15769 | { | |
15770 | insn = read_insn (buf); | |
15771 | insn |= (*valP >> 3) & 0x3ffff; | |
15772 | write_insn (buf, insn); | |
15773 | } | |
15774 | else | |
15775 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15776 | _("PC-relative access out of range")); | |
7361da2c AB |
15777 | break; |
15778 | ||
15779 | case BFD_RELOC_MIPS_19_PCREL_S2: | |
15780 | if ((*valP & 0x3) != 0) | |
15781 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15782 | _("PC-relative access to misaligned address (%lx)"), | |
717ba204 | 15783 | (long) *valP); |
41947d9e MR |
15784 | if (!fixP->fx_done) |
15785 | break; | |
7361da2c | 15786 | |
41947d9e MR |
15787 | if (*valP + 0x100000 <= 0x1fffff) |
15788 | { | |
15789 | insn = read_insn (buf); | |
15790 | insn |= (*valP >> 2) & 0x7ffff; | |
15791 | write_insn (buf, insn); | |
15792 | } | |
15793 | else | |
15794 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15795 | _("PC-relative access out of range")); | |
7361da2c AB |
15796 | break; |
15797 | ||
252b5132 | 15798 | case BFD_RELOC_16_PCREL_S2: |
9d862524 | 15799 | fix_validate_branch (fixP, *valP); |
cb56d3d3 | 15800 | |
54f4ddb3 TS |
15801 | /* We need to save the bits in the instruction since fixup_segment() |
15802 | might be deleting the relocation entry (i.e., a branch within | |
15803 | the current segment). */ | |
a7ebbfdf | 15804 | if (! fixP->fx_done) |
bb2d6cd7 | 15805 | break; |
252b5132 | 15806 | |
54f4ddb3 | 15807 | /* Update old instruction data. */ |
4d68580a | 15808 | insn = read_insn (buf); |
252b5132 | 15809 | |
a7ebbfdf TS |
15810 | if (*valP + 0x20000 <= 0x3ffff) |
15811 | { | |
15812 | insn |= (*valP >> 2) & 0xffff; | |
4d68580a | 15813 | write_insn (buf, insn); |
a7ebbfdf | 15814 | } |
ce8ad872 | 15815 | else if (fixP->fx_tcbit2 |
a7ebbfdf TS |
15816 | && fixP->fx_done |
15817 | && fixP->fx_frag->fr_address >= text_section->vma | |
15818 | && (fixP->fx_frag->fr_address | |
587aac4e | 15819 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
15820 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
15821 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
15822 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
15823 | { |
15824 | /* The branch offset is too large. If this is an | |
15825 | unconditional branch, and we are not generating PIC code, | |
15826 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
15827 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
15828 | insn = 0x0c000000; /* jal */ | |
252b5132 | 15829 | else |
a7ebbfdf TS |
15830 | insn = 0x08000000; /* j */ |
15831 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
15832 | fixP->fx_done = 0; | |
15833 | fixP->fx_addsy = section_symbol (text_section); | |
15834 | *valP += md_pcrel_from (fixP); | |
4d68580a | 15835 | write_insn (buf, insn); |
a7ebbfdf TS |
15836 | } |
15837 | else | |
15838 | { | |
15839 | /* If we got here, we have branch-relaxation disabled, | |
15840 | and there's nothing we can do to fix this instruction | |
15841 | without turning it into a longer sequence. */ | |
15842 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
1661c76c | 15843 | _("branch out of range")); |
252b5132 | 15844 | } |
252b5132 RH |
15845 | break; |
15846 | ||
c9775dde | 15847 | case BFD_RELOC_MIPS16_16_PCREL_S1: |
df58fc94 RS |
15848 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15849 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15850 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
96e9ba5f | 15851 | gas_assert (!fixP->fx_done); |
9d862524 MR |
15852 | if (fix_bad_cross_mode_branch_p (fixP)) |
15853 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15854 | _("branch to a symbol in another ISA mode")); | |
15855 | else if (fixP->fx_addsy | |
15856 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) | |
15857 | && !bfd_is_abs_section (S_GET_SEGMENT (fixP->fx_addsy)) | |
15858 | && (fixP->fx_offset & 0x1) != 0) | |
15859 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15860 | _("branch to misaligned address (0x%lx)"), | |
15861 | (long) (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset)); | |
15862 | else if (HAVE_IN_PLACE_ADDENDS && (fixP->fx_offset & 0x1) != 0) | |
15863 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15864 | _("cannot encode misaligned addend " | |
15865 | "in the relocatable field (0x%lx)"), | |
15866 | (long) fixP->fx_offset); | |
df58fc94 RS |
15867 | break; |
15868 | ||
252b5132 RH |
15869 | case BFD_RELOC_VTABLE_INHERIT: |
15870 | fixP->fx_done = 0; | |
15871 | if (fixP->fx_addsy | |
15872 | && !S_IS_DEFINED (fixP->fx_addsy) | |
15873 | && !S_IS_WEAK (fixP->fx_addsy)) | |
15874 | S_SET_WEAK (fixP->fx_addsy); | |
15875 | break; | |
15876 | ||
2f0c68f2 | 15877 | case BFD_RELOC_NONE: |
252b5132 RH |
15878 | case BFD_RELOC_VTABLE_ENTRY: |
15879 | fixP->fx_done = 0; | |
15880 | break; | |
15881 | ||
15882 | default: | |
b37df7c4 | 15883 | abort (); |
252b5132 | 15884 | } |
a7ebbfdf TS |
15885 | |
15886 | /* Remember value for tc_gen_reloc. */ | |
15887 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
15888 | } |
15889 | ||
252b5132 | 15890 | static symbolS * |
17a2f251 | 15891 | get_symbol (void) |
252b5132 RH |
15892 | { |
15893 | int c; | |
15894 | char *name; | |
15895 | symbolS *p; | |
15896 | ||
d02603dc | 15897 | c = get_symbol_name (&name); |
252b5132 | 15898 | p = (symbolS *) symbol_find_or_make (name); |
d02603dc | 15899 | (void) restore_line_pointer (c); |
252b5132 RH |
15900 | return p; |
15901 | } | |
15902 | ||
742a56fe RS |
15903 | /* Align the current frag to a given power of two. If a particular |
15904 | fill byte should be used, FILL points to an integer that contains | |
15905 | that byte, otherwise FILL is null. | |
15906 | ||
462427c4 RS |
15907 | This function used to have the comment: |
15908 | ||
15909 | The MIPS assembler also automatically adjusts any preceding label. | |
15910 | ||
15911 | The implementation therefore applied the adjustment to a maximum of | |
15912 | one label. However, other label adjustments are applied to batches | |
15913 | of labels, and adjusting just one caused problems when new labels | |
15914 | were added for the sake of debugging or unwind information. | |
15915 | We therefore adjust all preceding labels (given as LABELS) instead. */ | |
252b5132 RH |
15916 | |
15917 | static void | |
462427c4 | 15918 | mips_align (int to, int *fill, struct insn_label_list *labels) |
252b5132 | 15919 | { |
7d10b47d | 15920 | mips_emit_delays (); |
df58fc94 | 15921 | mips_record_compressed_mode (); |
742a56fe RS |
15922 | if (fill == NULL && subseg_text_p (now_seg)) |
15923 | frag_align_code (to, 0); | |
15924 | else | |
15925 | frag_align (to, fill ? *fill : 0, 0); | |
252b5132 | 15926 | record_alignment (now_seg, to); |
462427c4 | 15927 | mips_move_labels (labels, FALSE); |
252b5132 RH |
15928 | } |
15929 | ||
15930 | /* Align to a given power of two. .align 0 turns off the automatic | |
15931 | alignment used by the data creating pseudo-ops. */ | |
15932 | ||
15933 | static void | |
17a2f251 | 15934 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 | 15935 | { |
742a56fe | 15936 | int temp, fill_value, *fill_ptr; |
49954fb4 | 15937 | long max_alignment = 28; |
252b5132 | 15938 | |
54f4ddb3 | 15939 | /* o Note that the assembler pulls down any immediately preceding label |
252b5132 | 15940 | to the aligned address. |
54f4ddb3 | 15941 | o It's not documented but auto alignment is reinstated by |
252b5132 | 15942 | a .align pseudo instruction. |
54f4ddb3 | 15943 | o Note also that after auto alignment is turned off the mips assembler |
252b5132 | 15944 | issues an error on attempt to assemble an improperly aligned data item. |
54f4ddb3 | 15945 | We don't. */ |
252b5132 RH |
15946 | |
15947 | temp = get_absolute_expression (); | |
15948 | if (temp > max_alignment) | |
1661c76c | 15949 | as_bad (_("alignment too large, %d assumed"), temp = max_alignment); |
252b5132 RH |
15950 | else if (temp < 0) |
15951 | { | |
1661c76c | 15952 | as_warn (_("alignment negative, 0 assumed")); |
252b5132 RH |
15953 | temp = 0; |
15954 | } | |
15955 | if (*input_line_pointer == ',') | |
15956 | { | |
f9419b05 | 15957 | ++input_line_pointer; |
742a56fe RS |
15958 | fill_value = get_absolute_expression (); |
15959 | fill_ptr = &fill_value; | |
252b5132 RH |
15960 | } |
15961 | else | |
742a56fe | 15962 | fill_ptr = 0; |
252b5132 RH |
15963 | if (temp) |
15964 | { | |
a8dbcb85 TS |
15965 | segment_info_type *si = seg_info (now_seg); |
15966 | struct insn_label_list *l = si->label_list; | |
54f4ddb3 | 15967 | /* Auto alignment should be switched on by next section change. */ |
252b5132 | 15968 | auto_align = 1; |
462427c4 | 15969 | mips_align (temp, fill_ptr, l); |
252b5132 RH |
15970 | } |
15971 | else | |
15972 | { | |
15973 | auto_align = 0; | |
15974 | } | |
15975 | ||
15976 | demand_empty_rest_of_line (); | |
15977 | } | |
15978 | ||
252b5132 | 15979 | static void |
17a2f251 | 15980 | s_change_sec (int sec) |
252b5132 RH |
15981 | { |
15982 | segT seg; | |
15983 | ||
252b5132 RH |
15984 | /* The ELF backend needs to know that we are changing sections, so |
15985 | that .previous works correctly. We could do something like check | |
b6ff326e | 15986 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
15987 | as it would not be appropriate to use it in the section changing |
15988 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
15989 | This should be cleaner, somehow. */ | |
f3ded42a | 15990 | obj_elf_section_change_hook (); |
252b5132 | 15991 | |
7d10b47d | 15992 | mips_emit_delays (); |
6a32d874 | 15993 | |
252b5132 RH |
15994 | switch (sec) |
15995 | { | |
15996 | case 't': | |
15997 | s_text (0); | |
15998 | break; | |
15999 | case 'd': | |
16000 | s_data (0); | |
16001 | break; | |
16002 | case 'b': | |
16003 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
16004 | demand_empty_rest_of_line (); | |
16005 | break; | |
16006 | ||
16007 | case 'r': | |
4d0d148d TS |
16008 | seg = subseg_new (RDATA_SECTION_NAME, |
16009 | (subsegT) get_absolute_expression ()); | |
f3ded42a RS |
16010 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
16011 | | SEC_READONLY | SEC_RELOC | |
16012 | | SEC_DATA)); | |
16013 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
16014 | record_alignment (seg, 4); | |
4d0d148d | 16015 | demand_empty_rest_of_line (); |
252b5132 RH |
16016 | break; |
16017 | ||
16018 | case 's': | |
4d0d148d | 16019 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
f3ded42a RS |
16020 | bfd_set_section_flags (stdoutput, seg, |
16021 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
16022 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
16023 | record_alignment (seg, 4); | |
4d0d148d TS |
16024 | demand_empty_rest_of_line (); |
16025 | break; | |
998b3c36 MR |
16026 | |
16027 | case 'B': | |
16028 | seg = subseg_new (".sbss", (subsegT) get_absolute_expression ()); | |
f3ded42a RS |
16029 | bfd_set_section_flags (stdoutput, seg, SEC_ALLOC); |
16030 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
16031 | record_alignment (seg, 4); | |
998b3c36 MR |
16032 | demand_empty_rest_of_line (); |
16033 | break; | |
252b5132 RH |
16034 | } |
16035 | ||
16036 | auto_align = 1; | |
16037 | } | |
b34976b6 | 16038 | |
cca86cc8 | 16039 | void |
17a2f251 | 16040 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 16041 | { |
d02603dc | 16042 | char *saved_ilp; |
cca86cc8 | 16043 | char *section_name; |
d02603dc | 16044 | char c, endc; |
684022ea | 16045 | char next_c = 0; |
cca86cc8 SC |
16046 | int section_type; |
16047 | int section_flag; | |
16048 | int section_entry_size; | |
16049 | int section_alignment; | |
b34976b6 | 16050 | |
d02603dc NC |
16051 | saved_ilp = input_line_pointer; |
16052 | endc = get_symbol_name (§ion_name); | |
16053 | c = (endc == '"' ? input_line_pointer[1] : endc); | |
a816d1ed | 16054 | if (c) |
d02603dc | 16055 | next_c = input_line_pointer [(endc == '"' ? 2 : 1)]; |
cca86cc8 | 16056 | |
4cf0dd0d TS |
16057 | /* Do we have .section Name<,"flags">? */ |
16058 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 16059 | { |
d02603dc NC |
16060 | /* Just after name is now '\0'. */ |
16061 | (void) restore_line_pointer (endc); | |
16062 | input_line_pointer = saved_ilp; | |
cca86cc8 SC |
16063 | obj_elf_section (ignore); |
16064 | return; | |
16065 | } | |
d02603dc NC |
16066 | |
16067 | section_name = xstrdup (section_name); | |
16068 | c = restore_line_pointer (endc); | |
16069 | ||
cca86cc8 SC |
16070 | input_line_pointer++; |
16071 | ||
16072 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
16073 | if (c == ',') | |
16074 | section_type = get_absolute_expression (); | |
16075 | else | |
16076 | section_type = 0; | |
d02603dc | 16077 | |
cca86cc8 SC |
16078 | if (*input_line_pointer++ == ',') |
16079 | section_flag = get_absolute_expression (); | |
16080 | else | |
16081 | section_flag = 0; | |
d02603dc | 16082 | |
cca86cc8 SC |
16083 | if (*input_line_pointer++ == ',') |
16084 | section_entry_size = get_absolute_expression (); | |
16085 | else | |
16086 | section_entry_size = 0; | |
d02603dc | 16087 | |
cca86cc8 SC |
16088 | if (*input_line_pointer++ == ',') |
16089 | section_alignment = get_absolute_expression (); | |
16090 | else | |
16091 | section_alignment = 0; | |
d02603dc | 16092 | |
87975d2a AM |
16093 | /* FIXME: really ignore? */ |
16094 | (void) section_alignment; | |
cca86cc8 | 16095 | |
8ab8a5c8 RS |
16096 | /* When using the generic form of .section (as implemented by obj-elf.c), |
16097 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
16098 | traditionally had to fall back on the more common @progbits instead. | |
16099 | ||
16100 | There's nothing really harmful in this, since bfd will correct | |
16101 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
708587a4 | 16102 | means that, for backwards compatibility, the special_section entries |
8ab8a5c8 RS |
16103 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. |
16104 | ||
16105 | Even so, we shouldn't force users of the MIPS .section syntax to | |
16106 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
16107 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
16108 | generic type-checking code. */ | |
16109 | if (section_type == SHT_MIPS_DWARF) | |
16110 | section_type = SHT_PROGBITS; | |
16111 | ||
a91e1603 | 16112 | obj_elf_change_section (section_name, section_type, 0, section_flag, |
cca86cc8 | 16113 | section_entry_size, 0, 0, 0); |
a816d1ed AO |
16114 | |
16115 | if (now_seg->name != section_name) | |
16116 | free (section_name); | |
cca86cc8 | 16117 | } |
252b5132 RH |
16118 | |
16119 | void | |
17a2f251 | 16120 | mips_enable_auto_align (void) |
252b5132 RH |
16121 | { |
16122 | auto_align = 1; | |
16123 | } | |
16124 | ||
16125 | static void | |
17a2f251 | 16126 | s_cons (int log_size) |
252b5132 | 16127 | { |
a8dbcb85 TS |
16128 | segment_info_type *si = seg_info (now_seg); |
16129 | struct insn_label_list *l = si->label_list; | |
252b5132 | 16130 | |
7d10b47d | 16131 | mips_emit_delays (); |
252b5132 | 16132 | if (log_size > 0 && auto_align) |
462427c4 | 16133 | mips_align (log_size, 0, l); |
252b5132 | 16134 | cons (1 << log_size); |
a1facbec | 16135 | mips_clear_insn_labels (); |
252b5132 RH |
16136 | } |
16137 | ||
16138 | static void | |
17a2f251 | 16139 | s_float_cons (int type) |
252b5132 | 16140 | { |
a8dbcb85 TS |
16141 | segment_info_type *si = seg_info (now_seg); |
16142 | struct insn_label_list *l = si->label_list; | |
252b5132 | 16143 | |
7d10b47d | 16144 | mips_emit_delays (); |
252b5132 RH |
16145 | |
16146 | if (auto_align) | |
49309057 ILT |
16147 | { |
16148 | if (type == 'd') | |
462427c4 | 16149 | mips_align (3, 0, l); |
49309057 | 16150 | else |
462427c4 | 16151 | mips_align (2, 0, l); |
49309057 | 16152 | } |
252b5132 | 16153 | |
252b5132 | 16154 | float_cons (type); |
a1facbec | 16155 | mips_clear_insn_labels (); |
252b5132 RH |
16156 | } |
16157 | ||
16158 | /* Handle .globl. We need to override it because on Irix 5 you are | |
16159 | permitted to say | |
16160 | .globl foo .text | |
16161 | where foo is an undefined symbol, to mean that foo should be | |
16162 | considered to be the address of a function. */ | |
16163 | ||
16164 | static void | |
17a2f251 | 16165 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16166 | { |
16167 | char *name; | |
16168 | int c; | |
16169 | symbolS *symbolP; | |
16170 | flagword flag; | |
16171 | ||
8a06b769 | 16172 | do |
252b5132 | 16173 | { |
d02603dc | 16174 | c = get_symbol_name (&name); |
8a06b769 TS |
16175 | symbolP = symbol_find_or_make (name); |
16176 | S_SET_EXTERNAL (symbolP); | |
16177 | ||
252b5132 | 16178 | *input_line_pointer = c; |
d02603dc | 16179 | SKIP_WHITESPACE_AFTER_NAME (); |
252b5132 | 16180 | |
8a06b769 TS |
16181 | /* On Irix 5, every global symbol that is not explicitly labelled as |
16182 | being a function is apparently labelled as being an object. */ | |
16183 | flag = BSF_OBJECT; | |
252b5132 | 16184 | |
8a06b769 TS |
16185 | if (!is_end_of_line[(unsigned char) *input_line_pointer] |
16186 | && (*input_line_pointer != ',')) | |
16187 | { | |
16188 | char *secname; | |
16189 | asection *sec; | |
16190 | ||
d02603dc | 16191 | c = get_symbol_name (&secname); |
8a06b769 TS |
16192 | sec = bfd_get_section_by_name (stdoutput, secname); |
16193 | if (sec == NULL) | |
16194 | as_bad (_("%s: no such section"), secname); | |
d02603dc | 16195 | (void) restore_line_pointer (c); |
8a06b769 TS |
16196 | |
16197 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
16198 | flag = BSF_FUNCTION; | |
16199 | } | |
16200 | ||
16201 | symbol_get_bfdsym (symbolP)->flags |= flag; | |
16202 | ||
16203 | c = *input_line_pointer; | |
16204 | if (c == ',') | |
16205 | { | |
16206 | input_line_pointer++; | |
16207 | SKIP_WHITESPACE (); | |
16208 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
16209 | c = '\n'; | |
16210 | } | |
16211 | } | |
16212 | while (c == ','); | |
252b5132 | 16213 | |
252b5132 RH |
16214 | demand_empty_rest_of_line (); |
16215 | } | |
16216 | ||
16217 | static void | |
17a2f251 | 16218 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16219 | { |
16220 | char *opt; | |
16221 | char c; | |
16222 | ||
d02603dc | 16223 | c = get_symbol_name (&opt); |
252b5132 RH |
16224 | |
16225 | if (*opt == 'O') | |
16226 | { | |
16227 | /* FIXME: What does this mean? */ | |
16228 | } | |
41a1578e | 16229 | else if (strncmp (opt, "pic", 3) == 0 && ISDIGIT (opt[3]) && opt[4] == '\0') |
252b5132 RH |
16230 | { |
16231 | int i; | |
16232 | ||
16233 | i = atoi (opt + 3); | |
668c5ebc MR |
16234 | if (i != 0 && i != 2) |
16235 | as_bad (_(".option pic%d not supported"), i); | |
16236 | else if (mips_pic == VXWORKS_PIC) | |
16237 | as_bad (_(".option pic%d not supported in VxWorks PIC mode"), i); | |
16238 | else if (i == 0) | |
252b5132 RH |
16239 | mips_pic = NO_PIC; |
16240 | else if (i == 2) | |
143d77c5 | 16241 | { |
8b828383 | 16242 | mips_pic = SVR4_PIC; |
143d77c5 EC |
16243 | mips_abicalls = TRUE; |
16244 | } | |
252b5132 | 16245 | |
4d0d148d | 16246 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
16247 | { |
16248 | if (g_switch_seen && g_switch_value != 0) | |
16249 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
16250 | g_switch_value = 0; | |
16251 | bfd_set_gp_size (stdoutput, 0); | |
16252 | } | |
16253 | } | |
16254 | else | |
1661c76c | 16255 | as_warn (_("unrecognized option \"%s\""), opt); |
252b5132 | 16256 | |
d02603dc | 16257 | (void) restore_line_pointer (c); |
252b5132 RH |
16258 | demand_empty_rest_of_line (); |
16259 | } | |
16260 | ||
16261 | /* This structure is used to hold a stack of .set values. */ | |
16262 | ||
e972090a NC |
16263 | struct mips_option_stack |
16264 | { | |
252b5132 RH |
16265 | struct mips_option_stack *next; |
16266 | struct mips_set_options options; | |
16267 | }; | |
16268 | ||
16269 | static struct mips_option_stack *mips_opts_stack; | |
16270 | ||
22522f88 MR |
16271 | /* Return status for .set/.module option handling. */ |
16272 | ||
16273 | enum code_option_type | |
16274 | { | |
16275 | /* Unrecognized option. */ | |
16276 | OPTION_TYPE_BAD = -1, | |
16277 | ||
16278 | /* Ordinary option. */ | |
16279 | OPTION_TYPE_NORMAL, | |
16280 | ||
16281 | /* ISA changing option. */ | |
16282 | OPTION_TYPE_ISA | |
16283 | }; | |
16284 | ||
16285 | /* Handle common .set/.module options. Return status indicating option | |
16286 | type. */ | |
16287 | ||
16288 | static enum code_option_type | |
919731af | 16289 | parse_code_option (char * name) |
252b5132 | 16290 | { |
22522f88 | 16291 | bfd_boolean isa_set = FALSE; |
c6278170 | 16292 | const struct mips_ase *ase; |
22522f88 | 16293 | |
919731af | 16294 | if (strncmp (name, "at=", 3) == 0) |
741fe287 MR |
16295 | { |
16296 | char *s = name + 3; | |
16297 | ||
16298 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at)) | |
1661c76c | 16299 | as_bad (_("unrecognized register name `%s'"), s); |
741fe287 | 16300 | } |
252b5132 | 16301 | else if (strcmp (name, "at") == 0) |
919731af | 16302 | mips_opts.at = ATREG; |
252b5132 | 16303 | else if (strcmp (name, "noat") == 0) |
919731af | 16304 | mips_opts.at = ZERO; |
252b5132 | 16305 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) |
919731af | 16306 | mips_opts.nomove = 0; |
252b5132 | 16307 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) |
919731af | 16308 | mips_opts.nomove = 1; |
252b5132 | 16309 | else if (strcmp (name, "bopt") == 0) |
919731af | 16310 | mips_opts.nobopt = 0; |
252b5132 | 16311 | else if (strcmp (name, "nobopt") == 0) |
919731af | 16312 | mips_opts.nobopt = 1; |
ad3fea08 | 16313 | else if (strcmp (name, "gp=32") == 0) |
bad1aba3 | 16314 | mips_opts.gp = 32; |
ad3fea08 | 16315 | else if (strcmp (name, "gp=64") == 0) |
919731af | 16316 | mips_opts.gp = 64; |
ad3fea08 | 16317 | else if (strcmp (name, "fp=32") == 0) |
0b35dfee | 16318 | mips_opts.fp = 32; |
351cdf24 MF |
16319 | else if (strcmp (name, "fp=xx") == 0) |
16320 | mips_opts.fp = 0; | |
ad3fea08 | 16321 | else if (strcmp (name, "fp=64") == 0) |
919731af | 16322 | mips_opts.fp = 64; |
037b32b9 AN |
16323 | else if (strcmp (name, "softfloat") == 0) |
16324 | mips_opts.soft_float = 1; | |
16325 | else if (strcmp (name, "hardfloat") == 0) | |
16326 | mips_opts.soft_float = 0; | |
16327 | else if (strcmp (name, "singlefloat") == 0) | |
16328 | mips_opts.single_float = 1; | |
16329 | else if (strcmp (name, "doublefloat") == 0) | |
16330 | mips_opts.single_float = 0; | |
351cdf24 MF |
16331 | else if (strcmp (name, "nooddspreg") == 0) |
16332 | mips_opts.oddspreg = 0; | |
16333 | else if (strcmp (name, "oddspreg") == 0) | |
16334 | mips_opts.oddspreg = 1; | |
252b5132 RH |
16335 | else if (strcmp (name, "mips16") == 0 |
16336 | || strcmp (name, "MIPS-16") == 0) | |
919731af | 16337 | mips_opts.mips16 = 1; |
252b5132 RH |
16338 | else if (strcmp (name, "nomips16") == 0 |
16339 | || strcmp (name, "noMIPS-16") == 0) | |
16340 | mips_opts.mips16 = 0; | |
df58fc94 | 16341 | else if (strcmp (name, "micromips") == 0) |
919731af | 16342 | mips_opts.micromips = 1; |
df58fc94 RS |
16343 | else if (strcmp (name, "nomicromips") == 0) |
16344 | mips_opts.micromips = 0; | |
c6278170 RS |
16345 | else if (name[0] == 'n' |
16346 | && name[1] == 'o' | |
16347 | && (ase = mips_lookup_ase (name + 2))) | |
919731af | 16348 | mips_set_ase (ase, &mips_opts, FALSE); |
c6278170 | 16349 | else if ((ase = mips_lookup_ase (name))) |
919731af | 16350 | mips_set_ase (ase, &mips_opts, TRUE); |
1a2c1fad | 16351 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 16352 | { |
1a2c1fad CD |
16353 | /* Permit the user to change the ISA and architecture on the fly. |
16354 | Needless to say, misuse can cause serious problems. */ | |
919731af | 16355 | if (strncmp (name, "arch=", 5) == 0) |
1a2c1fad CD |
16356 | { |
16357 | const struct mips_cpu_info *p; | |
16358 | ||
919731af | 16359 | p = mips_parse_cpu ("internal use", name + 5); |
1a2c1fad CD |
16360 | if (!p) |
16361 | as_bad (_("unknown architecture %s"), name + 5); | |
16362 | else | |
16363 | { | |
16364 | mips_opts.arch = p->cpu; | |
16365 | mips_opts.isa = p->isa; | |
22522f88 | 16366 | isa_set = TRUE; |
1a2c1fad CD |
16367 | } |
16368 | } | |
81a21e38 TS |
16369 | else if (strncmp (name, "mips", 4) == 0) |
16370 | { | |
16371 | const struct mips_cpu_info *p; | |
16372 | ||
919731af | 16373 | p = mips_parse_cpu ("internal use", name); |
81a21e38 TS |
16374 | if (!p) |
16375 | as_bad (_("unknown ISA level %s"), name + 4); | |
16376 | else | |
16377 | { | |
16378 | mips_opts.arch = p->cpu; | |
16379 | mips_opts.isa = p->isa; | |
22522f88 | 16380 | isa_set = TRUE; |
81a21e38 TS |
16381 | } |
16382 | } | |
af7ee8bf | 16383 | else |
81a21e38 | 16384 | as_bad (_("unknown ISA or architecture %s"), name); |
252b5132 RH |
16385 | } |
16386 | else if (strcmp (name, "autoextend") == 0) | |
16387 | mips_opts.noautoextend = 0; | |
16388 | else if (strcmp (name, "noautoextend") == 0) | |
16389 | mips_opts.noautoextend = 1; | |
833794fc MR |
16390 | else if (strcmp (name, "insn32") == 0) |
16391 | mips_opts.insn32 = TRUE; | |
16392 | else if (strcmp (name, "noinsn32") == 0) | |
16393 | mips_opts.insn32 = FALSE; | |
919731af | 16394 | else if (strcmp (name, "sym32") == 0) |
16395 | mips_opts.sym32 = TRUE; | |
16396 | else if (strcmp (name, "nosym32") == 0) | |
16397 | mips_opts.sym32 = FALSE; | |
16398 | else | |
22522f88 MR |
16399 | return OPTION_TYPE_BAD; |
16400 | ||
16401 | return isa_set ? OPTION_TYPE_ISA : OPTION_TYPE_NORMAL; | |
919731af | 16402 | } |
16403 | ||
16404 | /* Handle the .set pseudo-op. */ | |
16405 | ||
16406 | static void | |
16407 | s_mipsset (int x ATTRIBUTE_UNUSED) | |
16408 | { | |
22522f88 | 16409 | enum code_option_type type = OPTION_TYPE_NORMAL; |
919731af | 16410 | char *name = input_line_pointer, ch; |
919731af | 16411 | |
16412 | file_mips_check_options (); | |
16413 | ||
16414 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
16415 | ++input_line_pointer; | |
16416 | ch = *input_line_pointer; | |
16417 | *input_line_pointer = '\0'; | |
16418 | ||
16419 | if (strchr (name, ',')) | |
16420 | { | |
16421 | /* Generic ".set" directive; use the generic handler. */ | |
16422 | *input_line_pointer = ch; | |
16423 | input_line_pointer = name; | |
16424 | s_set (0); | |
16425 | return; | |
16426 | } | |
16427 | ||
16428 | if (strcmp (name, "reorder") == 0) | |
16429 | { | |
16430 | if (mips_opts.noreorder) | |
16431 | end_noreorder (); | |
16432 | } | |
16433 | else if (strcmp (name, "noreorder") == 0) | |
16434 | { | |
16435 | if (!mips_opts.noreorder) | |
16436 | start_noreorder (); | |
16437 | } | |
16438 | else if (strcmp (name, "macro") == 0) | |
16439 | mips_opts.warn_about_macros = 0; | |
16440 | else if (strcmp (name, "nomacro") == 0) | |
16441 | { | |
16442 | if (mips_opts.noreorder == 0) | |
16443 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
16444 | mips_opts.warn_about_macros = 1; | |
16445 | } | |
16446 | else if (strcmp (name, "gp=default") == 0) | |
16447 | mips_opts.gp = file_mips_opts.gp; | |
16448 | else if (strcmp (name, "fp=default") == 0) | |
16449 | mips_opts.fp = file_mips_opts.fp; | |
16450 | else if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) | |
16451 | { | |
16452 | mips_opts.isa = file_mips_opts.isa; | |
16453 | mips_opts.arch = file_mips_opts.arch; | |
16454 | mips_opts.gp = file_mips_opts.gp; | |
16455 | mips_opts.fp = file_mips_opts.fp; | |
16456 | } | |
252b5132 RH |
16457 | else if (strcmp (name, "push") == 0) |
16458 | { | |
16459 | struct mips_option_stack *s; | |
16460 | ||
325801bd | 16461 | s = XNEW (struct mips_option_stack); |
252b5132 RH |
16462 | s->next = mips_opts_stack; |
16463 | s->options = mips_opts; | |
16464 | mips_opts_stack = s; | |
16465 | } | |
16466 | else if (strcmp (name, "pop") == 0) | |
16467 | { | |
16468 | struct mips_option_stack *s; | |
16469 | ||
16470 | s = mips_opts_stack; | |
16471 | if (s == NULL) | |
16472 | as_bad (_(".set pop with no .set push")); | |
16473 | else | |
16474 | { | |
16475 | /* If we're changing the reorder mode we need to handle | |
16476 | delay slots correctly. */ | |
16477 | if (s->options.noreorder && ! mips_opts.noreorder) | |
7d10b47d | 16478 | start_noreorder (); |
252b5132 | 16479 | else if (! s->options.noreorder && mips_opts.noreorder) |
7d10b47d | 16480 | end_noreorder (); |
252b5132 RH |
16481 | |
16482 | mips_opts = s->options; | |
16483 | mips_opts_stack = s->next; | |
16484 | free (s); | |
16485 | } | |
16486 | } | |
22522f88 MR |
16487 | else |
16488 | { | |
16489 | type = parse_code_option (name); | |
16490 | if (type == OPTION_TYPE_BAD) | |
16491 | as_warn (_("tried to set unrecognized symbol: %s\n"), name); | |
16492 | } | |
919731af | 16493 | |
16494 | /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp | |
16495 | registers based on what is supported by the arch/cpu. */ | |
22522f88 | 16496 | if (type == OPTION_TYPE_ISA) |
e6559e01 | 16497 | { |
919731af | 16498 | switch (mips_opts.isa) |
16499 | { | |
16500 | case 0: | |
16501 | break; | |
16502 | case ISA_MIPS1: | |
351cdf24 MF |
16503 | /* MIPS I cannot support FPXX. */ |
16504 | mips_opts.fp = 32; | |
16505 | /* fall-through. */ | |
919731af | 16506 | case ISA_MIPS2: |
16507 | case ISA_MIPS32: | |
16508 | case ISA_MIPS32R2: | |
16509 | case ISA_MIPS32R3: | |
16510 | case ISA_MIPS32R5: | |
16511 | mips_opts.gp = 32; | |
351cdf24 MF |
16512 | if (mips_opts.fp != 0) |
16513 | mips_opts.fp = 32; | |
919731af | 16514 | break; |
7361da2c AB |
16515 | case ISA_MIPS32R6: |
16516 | mips_opts.gp = 32; | |
16517 | mips_opts.fp = 64; | |
16518 | break; | |
919731af | 16519 | case ISA_MIPS3: |
16520 | case ISA_MIPS4: | |
16521 | case ISA_MIPS5: | |
16522 | case ISA_MIPS64: | |
16523 | case ISA_MIPS64R2: | |
16524 | case ISA_MIPS64R3: | |
16525 | case ISA_MIPS64R5: | |
7361da2c | 16526 | case ISA_MIPS64R6: |
919731af | 16527 | mips_opts.gp = 64; |
351cdf24 MF |
16528 | if (mips_opts.fp != 0) |
16529 | { | |
16530 | if (mips_opts.arch == CPU_R5900) | |
16531 | mips_opts.fp = 32; | |
16532 | else | |
16533 | mips_opts.fp = 64; | |
16534 | } | |
919731af | 16535 | break; |
16536 | default: | |
16537 | as_bad (_("unknown ISA level %s"), name + 4); | |
16538 | break; | |
16539 | } | |
e6559e01 | 16540 | } |
919731af | 16541 | |
16542 | mips_check_options (&mips_opts, FALSE); | |
16543 | ||
16544 | mips_check_isa_supports_ases (); | |
16545 | *input_line_pointer = ch; | |
16546 | demand_empty_rest_of_line (); | |
16547 | } | |
16548 | ||
16549 | /* Handle the .module pseudo-op. */ | |
16550 | ||
16551 | static void | |
16552 | s_module (int ignore ATTRIBUTE_UNUSED) | |
16553 | { | |
16554 | char *name = input_line_pointer, ch; | |
16555 | ||
16556 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
16557 | ++input_line_pointer; | |
16558 | ch = *input_line_pointer; | |
16559 | *input_line_pointer = '\0'; | |
16560 | ||
16561 | if (!file_mips_opts_checked) | |
252b5132 | 16562 | { |
22522f88 | 16563 | if (parse_code_option (name) == OPTION_TYPE_BAD) |
919731af | 16564 | as_bad (_(".module used with unrecognized symbol: %s\n"), name); |
16565 | ||
16566 | /* Update module level settings from mips_opts. */ | |
16567 | file_mips_opts = mips_opts; | |
252b5132 | 16568 | } |
919731af | 16569 | else |
16570 | as_bad (_(".module is not permitted after generating code")); | |
16571 | ||
252b5132 RH |
16572 | *input_line_pointer = ch; |
16573 | demand_empty_rest_of_line (); | |
16574 | } | |
16575 | ||
16576 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
16577 | .option pic2. It means to generate SVR4 PIC calls. */ | |
16578 | ||
16579 | static void | |
17a2f251 | 16580 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16581 | { |
16582 | mips_pic = SVR4_PIC; | |
143d77c5 | 16583 | mips_abicalls = TRUE; |
4d0d148d TS |
16584 | |
16585 | if (g_switch_seen && g_switch_value != 0) | |
16586 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
16587 | g_switch_value = 0; | |
16588 | ||
252b5132 RH |
16589 | bfd_set_gp_size (stdoutput, 0); |
16590 | demand_empty_rest_of_line (); | |
16591 | } | |
16592 | ||
16593 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
16594 | PIC code. It sets the $gp register for the function based on the | |
16595 | function address, which is in the register named in the argument. | |
16596 | This uses a relocation against _gp_disp, which is handled specially | |
16597 | by the linker. The result is: | |
16598 | lui $gp,%hi(_gp_disp) | |
16599 | addiu $gp,$gp,%lo(_gp_disp) | |
16600 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
16601 | The .cpload argument is normally $25 == $t9. |
16602 | ||
16603 | The -mno-shared option changes this to: | |
bbe506e8 TS |
16604 | lui $gp,%hi(__gnu_local_gp) |
16605 | addiu $gp,$gp,%lo(__gnu_local_gp) | |
aa6975fb ILT |
16606 | and the argument is ignored. This saves an instruction, but the |
16607 | resulting code is not position independent; it uses an absolute | |
bbe506e8 TS |
16608 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
16609 | can go into an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
16610 | |
16611 | static void | |
17a2f251 | 16612 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16613 | { |
16614 | expressionS ex; | |
aa6975fb ILT |
16615 | int reg; |
16616 | int in_shared; | |
252b5132 | 16617 | |
919731af | 16618 | file_mips_check_options (); |
16619 | ||
6478892d TS |
16620 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
16621 | .cpload is ignored. */ | |
16622 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
16623 | { |
16624 | s_ignore (0); | |
16625 | return; | |
16626 | } | |
16627 | ||
a276b80c MR |
16628 | if (mips_opts.mips16) |
16629 | { | |
16630 | as_bad (_("%s not supported in MIPS16 mode"), ".cpload"); | |
16631 | ignore_rest_of_line (); | |
16632 | return; | |
16633 | } | |
16634 | ||
d3ecfc59 | 16635 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
16636 | if (mips_opts.noreorder == 0) |
16637 | as_warn (_(".cpload not in noreorder section")); | |
16638 | ||
aa6975fb ILT |
16639 | reg = tc_get_register (0); |
16640 | ||
16641 | /* If we need to produce a 64-bit address, we are better off using | |
16642 | the default instruction sequence. */ | |
aed1a261 | 16643 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
aa6975fb | 16644 | |
252b5132 | 16645 | ex.X_op = O_symbol; |
bbe506e8 TS |
16646 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
16647 | "__gnu_local_gp"); | |
252b5132 RH |
16648 | ex.X_op_symbol = NULL; |
16649 | ex.X_add_number = 0; | |
16650 | ||
16651 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 16652 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 16653 | |
8a75745d MR |
16654 | mips_mark_labels (); |
16655 | mips_assembling_insn = TRUE; | |
16656 | ||
584892a6 | 16657 | macro_start (); |
67c0d1eb RS |
16658 | macro_build_lui (&ex, mips_gp_register); |
16659 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 16660 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
16661 | if (in_shared) |
16662 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
16663 | mips_gp_register, reg); | |
584892a6 | 16664 | macro_end (); |
252b5132 | 16665 | |
8a75745d | 16666 | mips_assembling_insn = FALSE; |
252b5132 RH |
16667 | demand_empty_rest_of_line (); |
16668 | } | |
16669 | ||
6478892d TS |
16670 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
16671 | .cpsetup $reg1, offset|$reg2, label | |
16672 | ||
16673 | If offset is given, this results in: | |
16674 | sd $gp, offset($sp) | |
956cd1d6 | 16675 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
16676 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
16677 | daddu $gp, $gp, $reg1 | |
6478892d TS |
16678 | |
16679 | If $reg2 is given, this results in: | |
40fc1451 | 16680 | or $reg2, $gp, $0 |
956cd1d6 | 16681 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
16682 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
16683 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
16684 | $reg1 is normally $25 == $t9. |
16685 | ||
16686 | The -mno-shared option replaces the last three instructions with | |
16687 | lui $gp,%hi(_gp) | |
54f4ddb3 | 16688 | addiu $gp,$gp,%lo(_gp) */ |
aa6975fb | 16689 | |
6478892d | 16690 | static void |
17a2f251 | 16691 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16692 | { |
16693 | expressionS ex_off; | |
16694 | expressionS ex_sym; | |
16695 | int reg1; | |
6478892d | 16696 | |
919731af | 16697 | file_mips_check_options (); |
16698 | ||
8586fc66 | 16699 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
16700 | We also need NewABI support. */ |
16701 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16702 | { | |
16703 | s_ignore (0); | |
16704 | return; | |
16705 | } | |
16706 | ||
a276b80c MR |
16707 | if (mips_opts.mips16) |
16708 | { | |
16709 | as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup"); | |
16710 | ignore_rest_of_line (); | |
16711 | return; | |
16712 | } | |
16713 | ||
6478892d TS |
16714 | reg1 = tc_get_register (0); |
16715 | SKIP_WHITESPACE (); | |
16716 | if (*input_line_pointer != ',') | |
16717 | { | |
16718 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
16719 | return; | |
16720 | } | |
16721 | else | |
80245285 | 16722 | ++input_line_pointer; |
6478892d TS |
16723 | SKIP_WHITESPACE (); |
16724 | if (*input_line_pointer == '$') | |
80245285 TS |
16725 | { |
16726 | mips_cpreturn_register = tc_get_register (0); | |
16727 | mips_cpreturn_offset = -1; | |
16728 | } | |
6478892d | 16729 | else |
80245285 TS |
16730 | { |
16731 | mips_cpreturn_offset = get_absolute_expression (); | |
16732 | mips_cpreturn_register = -1; | |
16733 | } | |
6478892d TS |
16734 | SKIP_WHITESPACE (); |
16735 | if (*input_line_pointer != ',') | |
16736 | { | |
16737 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
16738 | return; | |
16739 | } | |
16740 | else | |
f9419b05 | 16741 | ++input_line_pointer; |
6478892d | 16742 | SKIP_WHITESPACE (); |
f21f8242 | 16743 | expression (&ex_sym); |
6478892d | 16744 | |
8a75745d MR |
16745 | mips_mark_labels (); |
16746 | mips_assembling_insn = TRUE; | |
16747 | ||
584892a6 | 16748 | macro_start (); |
6478892d TS |
16749 | if (mips_cpreturn_register == -1) |
16750 | { | |
16751 | ex_off.X_op = O_constant; | |
16752 | ex_off.X_add_symbol = NULL; | |
16753 | ex_off.X_op_symbol = NULL; | |
16754 | ex_off.X_add_number = mips_cpreturn_offset; | |
16755 | ||
67c0d1eb | 16756 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 16757 | BFD_RELOC_LO16, SP); |
6478892d TS |
16758 | } |
16759 | else | |
40fc1451 | 16760 | move_register (mips_cpreturn_register, mips_gp_register); |
6478892d | 16761 | |
aed1a261 | 16762 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
aa6975fb | 16763 | { |
df58fc94 | 16764 | macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register, |
aa6975fb ILT |
16765 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, |
16766 | BFD_RELOC_HI16_S); | |
16767 | ||
16768 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
16769 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
16770 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
16771 | ||
16772 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
16773 | mips_gp_register, reg1); | |
16774 | } | |
16775 | else | |
16776 | { | |
16777 | expressionS ex; | |
16778 | ||
16779 | ex.X_op = O_symbol; | |
4184909a | 16780 | ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); |
aa6975fb ILT |
16781 | ex.X_op_symbol = NULL; |
16782 | ex.X_add_number = 0; | |
6e1304d8 | 16783 | |
aa6975fb ILT |
16784 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
16785 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
16786 | ||
16787 | macro_build_lui (&ex, mips_gp_register); | |
16788 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
16789 | mips_gp_register, BFD_RELOC_LO16); | |
16790 | } | |
f21f8242 | 16791 | |
584892a6 | 16792 | macro_end (); |
6478892d | 16793 | |
8a75745d | 16794 | mips_assembling_insn = FALSE; |
6478892d TS |
16795 | demand_empty_rest_of_line (); |
16796 | } | |
16797 | ||
16798 | static void | |
17a2f251 | 16799 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d | 16800 | { |
919731af | 16801 | file_mips_check_options (); |
16802 | ||
6478892d | 16803 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, |
54f4ddb3 | 16804 | .cplocal is ignored. */ |
6478892d TS |
16805 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) |
16806 | { | |
16807 | s_ignore (0); | |
16808 | return; | |
16809 | } | |
16810 | ||
a276b80c MR |
16811 | if (mips_opts.mips16) |
16812 | { | |
16813 | as_bad (_("%s not supported in MIPS16 mode"), ".cplocal"); | |
16814 | ignore_rest_of_line (); | |
16815 | return; | |
16816 | } | |
16817 | ||
6478892d | 16818 | mips_gp_register = tc_get_register (0); |
85b51719 | 16819 | demand_empty_rest_of_line (); |
6478892d TS |
16820 | } |
16821 | ||
252b5132 RH |
16822 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
16823 | offset from $sp. The offset is remembered, and after making a PIC | |
16824 | call $gp is restored from that location. */ | |
16825 | ||
16826 | static void | |
17a2f251 | 16827 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16828 | { |
16829 | expressionS ex; | |
252b5132 | 16830 | |
919731af | 16831 | file_mips_check_options (); |
16832 | ||
6478892d | 16833 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 16834 | .cprestore is ignored. */ |
6478892d | 16835 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
16836 | { |
16837 | s_ignore (0); | |
16838 | return; | |
16839 | } | |
16840 | ||
a276b80c MR |
16841 | if (mips_opts.mips16) |
16842 | { | |
16843 | as_bad (_("%s not supported in MIPS16 mode"), ".cprestore"); | |
16844 | ignore_rest_of_line (); | |
16845 | return; | |
16846 | } | |
16847 | ||
252b5132 | 16848 | mips_cprestore_offset = get_absolute_expression (); |
7a621144 | 16849 | mips_cprestore_valid = 1; |
252b5132 RH |
16850 | |
16851 | ex.X_op = O_constant; | |
16852 | ex.X_add_symbol = NULL; | |
16853 | ex.X_op_symbol = NULL; | |
16854 | ex.X_add_number = mips_cprestore_offset; | |
16855 | ||
8a75745d MR |
16856 | mips_mark_labels (); |
16857 | mips_assembling_insn = TRUE; | |
16858 | ||
584892a6 | 16859 | macro_start (); |
67c0d1eb RS |
16860 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
16861 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 16862 | macro_end (); |
252b5132 | 16863 | |
8a75745d | 16864 | mips_assembling_insn = FALSE; |
252b5132 RH |
16865 | demand_empty_rest_of_line (); |
16866 | } | |
16867 | ||
6478892d | 16868 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 16869 | was given in the preceding .cpsetup, it results in: |
6478892d | 16870 | ld $gp, offset($sp) |
76b3015f | 16871 | |
6478892d | 16872 | If a register $reg2 was given there, it results in: |
40fc1451 | 16873 | or $gp, $reg2, $0 */ |
54f4ddb3 | 16874 | |
6478892d | 16875 | static void |
17a2f251 | 16876 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16877 | { |
16878 | expressionS ex; | |
6478892d | 16879 | |
919731af | 16880 | file_mips_check_options (); |
16881 | ||
6478892d TS |
16882 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. |
16883 | We also need NewABI support. */ | |
16884 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16885 | { | |
16886 | s_ignore (0); | |
16887 | return; | |
16888 | } | |
16889 | ||
a276b80c MR |
16890 | if (mips_opts.mips16) |
16891 | { | |
16892 | as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn"); | |
16893 | ignore_rest_of_line (); | |
16894 | return; | |
16895 | } | |
16896 | ||
8a75745d MR |
16897 | mips_mark_labels (); |
16898 | mips_assembling_insn = TRUE; | |
16899 | ||
584892a6 | 16900 | macro_start (); |
6478892d TS |
16901 | if (mips_cpreturn_register == -1) |
16902 | { | |
16903 | ex.X_op = O_constant; | |
16904 | ex.X_add_symbol = NULL; | |
16905 | ex.X_op_symbol = NULL; | |
16906 | ex.X_add_number = mips_cpreturn_offset; | |
16907 | ||
67c0d1eb | 16908 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
16909 | } |
16910 | else | |
40fc1451 SD |
16911 | move_register (mips_gp_register, mips_cpreturn_register); |
16912 | ||
584892a6 | 16913 | macro_end (); |
6478892d | 16914 | |
8a75745d | 16915 | mips_assembling_insn = FALSE; |
6478892d TS |
16916 | demand_empty_rest_of_line (); |
16917 | } | |
16918 | ||
d0f13682 CLT |
16919 | /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword |
16920 | pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size | |
16921 | DTP- or TP-relative relocation of type RTYPE, for use in either DWARF | |
16922 | debug information or MIPS16 TLS. */ | |
741d6ea8 JM |
16923 | |
16924 | static void | |
d0f13682 CLT |
16925 | s_tls_rel_directive (const size_t bytes, const char *dirstr, |
16926 | bfd_reloc_code_real_type rtype) | |
741d6ea8 JM |
16927 | { |
16928 | expressionS ex; | |
16929 | char *p; | |
16930 | ||
16931 | expression (&ex); | |
16932 | ||
16933 | if (ex.X_op != O_symbol) | |
16934 | { | |
1661c76c | 16935 | as_bad (_("unsupported use of %s"), dirstr); |
741d6ea8 JM |
16936 | ignore_rest_of_line (); |
16937 | } | |
16938 | ||
16939 | p = frag_more (bytes); | |
16940 | md_number_to_chars (p, 0, bytes); | |
d0f13682 | 16941 | fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype); |
741d6ea8 | 16942 | demand_empty_rest_of_line (); |
de64cffd | 16943 | mips_clear_insn_labels (); |
741d6ea8 JM |
16944 | } |
16945 | ||
16946 | /* Handle .dtprelword. */ | |
16947 | ||
16948 | static void | |
16949 | s_dtprelword (int ignore ATTRIBUTE_UNUSED) | |
16950 | { | |
d0f13682 | 16951 | s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32); |
741d6ea8 JM |
16952 | } |
16953 | ||
16954 | /* Handle .dtpreldword. */ | |
16955 | ||
16956 | static void | |
16957 | s_dtpreldword (int ignore ATTRIBUTE_UNUSED) | |
16958 | { | |
d0f13682 CLT |
16959 | s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64); |
16960 | } | |
16961 | ||
16962 | /* Handle .tprelword. */ | |
16963 | ||
16964 | static void | |
16965 | s_tprelword (int ignore ATTRIBUTE_UNUSED) | |
16966 | { | |
16967 | s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32); | |
16968 | } | |
16969 | ||
16970 | /* Handle .tpreldword. */ | |
16971 | ||
16972 | static void | |
16973 | s_tpreldword (int ignore ATTRIBUTE_UNUSED) | |
16974 | { | |
16975 | s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64); | |
741d6ea8 JM |
16976 | } |
16977 | ||
6478892d TS |
16978 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC |
16979 | code. It sets the offset to use in gp_rel relocations. */ | |
16980 | ||
16981 | static void | |
17a2f251 | 16982 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16983 | { |
16984 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
16985 | We also need NewABI support. */ | |
16986 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16987 | { | |
16988 | s_ignore (0); | |
16989 | return; | |
16990 | } | |
16991 | ||
def2e0dd | 16992 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
16993 | |
16994 | demand_empty_rest_of_line (); | |
16995 | } | |
16996 | ||
252b5132 RH |
16997 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
16998 | code. It generates a 32 bit GP relative reloc. */ | |
16999 | ||
17000 | static void | |
17a2f251 | 17001 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 17002 | { |
a8dbcb85 TS |
17003 | segment_info_type *si; |
17004 | struct insn_label_list *l; | |
252b5132 RH |
17005 | expressionS ex; |
17006 | char *p; | |
17007 | ||
17008 | /* When not generating PIC code, this is treated as .word. */ | |
17009 | if (mips_pic != SVR4_PIC) | |
17010 | { | |
17011 | s_cons (2); | |
17012 | return; | |
17013 | } | |
17014 | ||
a8dbcb85 TS |
17015 | si = seg_info (now_seg); |
17016 | l = si->label_list; | |
7d10b47d | 17017 | mips_emit_delays (); |
252b5132 | 17018 | if (auto_align) |
462427c4 | 17019 | mips_align (2, 0, l); |
252b5132 RH |
17020 | |
17021 | expression (&ex); | |
a1facbec | 17022 | mips_clear_insn_labels (); |
252b5132 RH |
17023 | |
17024 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
17025 | { | |
1661c76c | 17026 | as_bad (_("unsupported use of .gpword")); |
252b5132 RH |
17027 | ignore_rest_of_line (); |
17028 | } | |
17029 | ||
17030 | p = frag_more (4); | |
17a2f251 | 17031 | md_number_to_chars (p, 0, 4); |
b34976b6 | 17032 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 17033 | BFD_RELOC_GPREL32); |
252b5132 RH |
17034 | |
17035 | demand_empty_rest_of_line (); | |
17036 | } | |
17037 | ||
10181a0d | 17038 | static void |
17a2f251 | 17039 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d | 17040 | { |
a8dbcb85 TS |
17041 | segment_info_type *si; |
17042 | struct insn_label_list *l; | |
10181a0d AO |
17043 | expressionS ex; |
17044 | char *p; | |
17045 | ||
17046 | /* When not generating PIC code, this is treated as .dword. */ | |
17047 | if (mips_pic != SVR4_PIC) | |
17048 | { | |
17049 | s_cons (3); | |
17050 | return; | |
17051 | } | |
17052 | ||
a8dbcb85 TS |
17053 | si = seg_info (now_seg); |
17054 | l = si->label_list; | |
7d10b47d | 17055 | mips_emit_delays (); |
10181a0d | 17056 | if (auto_align) |
462427c4 | 17057 | mips_align (3, 0, l); |
10181a0d AO |
17058 | |
17059 | expression (&ex); | |
a1facbec | 17060 | mips_clear_insn_labels (); |
10181a0d AO |
17061 | |
17062 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
17063 | { | |
1661c76c | 17064 | as_bad (_("unsupported use of .gpdword")); |
10181a0d AO |
17065 | ignore_rest_of_line (); |
17066 | } | |
17067 | ||
17068 | p = frag_more (8); | |
17a2f251 | 17069 | md_number_to_chars (p, 0, 8); |
a105a300 | 17070 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 17071 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
17072 | |
17073 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
17074 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
17075 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
17076 | |
17077 | demand_empty_rest_of_line (); | |
17078 | } | |
17079 | ||
a3f278e2 CM |
17080 | /* Handle the .ehword pseudo-op. This is used when generating unwinding |
17081 | tables. It generates a R_MIPS_EH reloc. */ | |
17082 | ||
17083 | static void | |
17084 | s_ehword (int ignore ATTRIBUTE_UNUSED) | |
17085 | { | |
17086 | expressionS ex; | |
17087 | char *p; | |
17088 | ||
17089 | mips_emit_delays (); | |
17090 | ||
17091 | expression (&ex); | |
17092 | mips_clear_insn_labels (); | |
17093 | ||
17094 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
17095 | { | |
1661c76c | 17096 | as_bad (_("unsupported use of .ehword")); |
a3f278e2 CM |
17097 | ignore_rest_of_line (); |
17098 | } | |
17099 | ||
17100 | p = frag_more (4); | |
17101 | md_number_to_chars (p, 0, 4); | |
17102 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, | |
2f0c68f2 | 17103 | BFD_RELOC_32_PCREL); |
a3f278e2 CM |
17104 | |
17105 | demand_empty_rest_of_line (); | |
17106 | } | |
17107 | ||
252b5132 RH |
17108 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
17109 | tables in SVR4 PIC code. */ | |
17110 | ||
17111 | static void | |
17a2f251 | 17112 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 17113 | { |
252b5132 RH |
17114 | int reg; |
17115 | ||
919731af | 17116 | file_mips_check_options (); |
17117 | ||
10181a0d AO |
17118 | /* This is ignored when not generating SVR4 PIC code. */ |
17119 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
17120 | { |
17121 | s_ignore (0); | |
17122 | return; | |
17123 | } | |
17124 | ||
8a75745d MR |
17125 | mips_mark_labels (); |
17126 | mips_assembling_insn = TRUE; | |
17127 | ||
252b5132 | 17128 | /* Add $gp to the register named as an argument. */ |
584892a6 | 17129 | macro_start (); |
252b5132 | 17130 | reg = tc_get_register (0); |
67c0d1eb | 17131 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 17132 | macro_end (); |
252b5132 | 17133 | |
8a75745d | 17134 | mips_assembling_insn = FALSE; |
bdaaa2e1 | 17135 | demand_empty_rest_of_line (); |
252b5132 RH |
17136 | } |
17137 | ||
17138 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
df58fc94 | 17139 | mips16/micromips mode. This permits the linker to handle them specially, |
252b5132 RH |
17140 | such as generating jalx instructions when needed. We also make |
17141 | them odd for the duration of the assembly, in order to generate the | |
17142 | right sort of code. We will make them even in the adjust_symtab | |
17143 | routine, while leaving them marked. This is convenient for the | |
17144 | debugger and the disassembler. The linker knows to make them odd | |
17145 | again. */ | |
17146 | ||
17147 | static void | |
17a2f251 | 17148 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 17149 | { |
7bb01e2d MR |
17150 | file_mips_check_options (); |
17151 | file_ase_mips16 |= mips_opts.mips16; | |
17152 | file_ase_micromips |= mips_opts.micromips; | |
17153 | ||
df58fc94 | 17154 | mips_mark_labels (); |
252b5132 RH |
17155 | |
17156 | demand_empty_rest_of_line (); | |
17157 | } | |
17158 | ||
ba92f887 MR |
17159 | /* Handle the .nan pseudo-op. */ |
17160 | ||
17161 | static void | |
17162 | s_nan (int ignore ATTRIBUTE_UNUSED) | |
17163 | { | |
17164 | static const char str_legacy[] = "legacy"; | |
17165 | static const char str_2008[] = "2008"; | |
17166 | size_t i; | |
17167 | ||
17168 | for (i = 0; !is_end_of_line[(unsigned char) input_line_pointer[i]]; i++); | |
17169 | ||
17170 | if (i == sizeof (str_2008) - 1 | |
17171 | && memcmp (input_line_pointer, str_2008, i) == 0) | |
7361da2c | 17172 | mips_nan2008 = 1; |
ba92f887 MR |
17173 | else if (i == sizeof (str_legacy) - 1 |
17174 | && memcmp (input_line_pointer, str_legacy, i) == 0) | |
7361da2c AB |
17175 | { |
17176 | if (ISA_HAS_LEGACY_NAN (file_mips_opts.isa)) | |
17177 | mips_nan2008 = 0; | |
17178 | else | |
17179 | as_bad (_("`%s' does not support legacy NaN"), | |
17180 | mips_cpu_info_from_isa (file_mips_opts.isa)->name); | |
17181 | } | |
ba92f887 | 17182 | else |
1661c76c | 17183 | as_bad (_("bad .nan directive")); |
ba92f887 MR |
17184 | |
17185 | input_line_pointer += i; | |
17186 | demand_empty_rest_of_line (); | |
17187 | } | |
17188 | ||
754e2bb9 RS |
17189 | /* Handle a .stab[snd] directive. Ideally these directives would be |
17190 | implemented in a transparent way, so that removing them would not | |
17191 | have any effect on the generated instructions. However, s_stab | |
17192 | internally changes the section, so in practice we need to decide | |
17193 | now whether the preceding label marks compressed code. We do not | |
17194 | support changing the compression mode of a label after a .stab* | |
17195 | directive, such as in: | |
17196 | ||
17197 | foo: | |
134c0c8b | 17198 | .stabs ... |
754e2bb9 RS |
17199 | .set mips16 |
17200 | ||
17201 | so the current mode wins. */ | |
252b5132 RH |
17202 | |
17203 | static void | |
17a2f251 | 17204 | s_mips_stab (int type) |
252b5132 | 17205 | { |
42c0794e | 17206 | file_mips_check_options (); |
754e2bb9 | 17207 | mips_mark_labels (); |
252b5132 RH |
17208 | s_stab (type); |
17209 | } | |
17210 | ||
54f4ddb3 | 17211 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */ |
252b5132 RH |
17212 | |
17213 | static void | |
17a2f251 | 17214 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
17215 | { |
17216 | char *name; | |
17217 | int c; | |
17218 | symbolS *symbolP; | |
17219 | expressionS exp; | |
17220 | ||
d02603dc | 17221 | c = get_symbol_name (&name); |
252b5132 RH |
17222 | symbolP = symbol_find_or_make (name); |
17223 | S_SET_WEAK (symbolP); | |
17224 | *input_line_pointer = c; | |
17225 | ||
d02603dc | 17226 | SKIP_WHITESPACE_AFTER_NAME (); |
252b5132 RH |
17227 | |
17228 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
17229 | { | |
17230 | if (S_IS_DEFINED (symbolP)) | |
17231 | { | |
20203fb9 | 17232 | as_bad (_("ignoring attempt to redefine symbol %s"), |
252b5132 RH |
17233 | S_GET_NAME (symbolP)); |
17234 | ignore_rest_of_line (); | |
17235 | return; | |
17236 | } | |
bdaaa2e1 | 17237 | |
252b5132 RH |
17238 | if (*input_line_pointer == ',') |
17239 | { | |
17240 | ++input_line_pointer; | |
17241 | SKIP_WHITESPACE (); | |
17242 | } | |
bdaaa2e1 | 17243 | |
252b5132 RH |
17244 | expression (&exp); |
17245 | if (exp.X_op != O_symbol) | |
17246 | { | |
20203fb9 | 17247 | as_bad (_("bad .weakext directive")); |
98d3f06f | 17248 | ignore_rest_of_line (); |
252b5132 RH |
17249 | return; |
17250 | } | |
49309057 | 17251 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
17252 | } |
17253 | ||
17254 | demand_empty_rest_of_line (); | |
17255 | } | |
17256 | ||
17257 | /* Parse a register string into a number. Called from the ECOFF code | |
17258 | to parse .frame. The argument is non-zero if this is the frame | |
17259 | register, so that we can record it in mips_frame_reg. */ | |
17260 | ||
17261 | int | |
17a2f251 | 17262 | tc_get_register (int frame) |
252b5132 | 17263 | { |
707bfff6 | 17264 | unsigned int reg; |
252b5132 RH |
17265 | |
17266 | SKIP_WHITESPACE (); | |
707bfff6 TS |
17267 | if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®)) |
17268 | reg = 0; | |
252b5132 | 17269 | if (frame) |
7a621144 DJ |
17270 | { |
17271 | mips_frame_reg = reg != 0 ? reg : SP; | |
17272 | mips_frame_reg_valid = 1; | |
17273 | mips_cprestore_valid = 0; | |
17274 | } | |
252b5132 RH |
17275 | return reg; |
17276 | } | |
17277 | ||
17278 | valueT | |
17a2f251 | 17279 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
17280 | { |
17281 | int align = bfd_get_section_alignment (stdoutput, seg); | |
17282 | ||
f3ded42a RS |
17283 | /* We don't need to align ELF sections to the full alignment. |
17284 | However, Irix 5 may prefer that we align them at least to a 16 | |
17285 | byte boundary. We don't bother to align the sections if we | |
17286 | are targeted for an embedded system. */ | |
17287 | if (strncmp (TARGET_OS, "elf", 3) == 0) | |
17288 | return addr; | |
17289 | if (align > 4) | |
17290 | align = 4; | |
252b5132 | 17291 | |
8d3842cd | 17292 | return ((addr + (1 << align) - 1) & -(1 << align)); |
252b5132 RH |
17293 | } |
17294 | ||
17295 | /* Utility routine, called from above as well. If called while the | |
17296 | input file is still being read, it's only an approximation. (For | |
17297 | example, a symbol may later become defined which appeared to be | |
17298 | undefined earlier.) */ | |
17299 | ||
17300 | static int | |
17a2f251 | 17301 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
17302 | { |
17303 | if (sym == 0) | |
17304 | return 0; | |
17305 | ||
4d0d148d | 17306 | if (g_switch_value > 0) |
252b5132 RH |
17307 | { |
17308 | const char *symname; | |
17309 | int change; | |
17310 | ||
c9914766 | 17311 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
17312 | register. It can be if it is smaller than the -G size or if |
17313 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 17314 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
17315 | they can. */ |
17316 | symname = S_GET_NAME (sym); | |
17317 | if (symname != (const char *) NULL | |
17318 | && (strcmp (symname, "eprol") == 0 | |
17319 | || strcmp (symname, "etext") == 0 | |
17320 | || strcmp (symname, "_gp") == 0 | |
17321 | || strcmp (symname, "edata") == 0 | |
17322 | || strcmp (symname, "_fbss") == 0 | |
17323 | || strcmp (symname, "_fdata") == 0 | |
17324 | || strcmp (symname, "_ftext") == 0 | |
17325 | || strcmp (symname, "end") == 0 | |
17326 | || strcmp (symname, "_gp_disp") == 0)) | |
17327 | change = 1; | |
17328 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
17329 | && (0 | |
17330 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
17331 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
17332 | && (symbol_get_obj (sym)->ecoff_extern_size | |
17333 | <= g_switch_value)) | |
252b5132 RH |
17334 | #endif |
17335 | /* We must defer this decision until after the whole | |
17336 | file has been read, since there might be a .extern | |
17337 | after the first use of this symbol. */ | |
17338 | || (before_relaxing | |
17339 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 17340 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
17341 | #endif |
17342 | && S_GET_VALUE (sym) == 0) | |
17343 | || (S_GET_VALUE (sym) != 0 | |
17344 | && S_GET_VALUE (sym) <= g_switch_value))) | |
17345 | change = 0; | |
17346 | else | |
17347 | { | |
17348 | const char *segname; | |
17349 | ||
17350 | segname = segment_name (S_GET_SEGMENT (sym)); | |
9c2799c2 | 17351 | gas_assert (strcmp (segname, ".lit8") != 0 |
252b5132 RH |
17352 | && strcmp (segname, ".lit4") != 0); |
17353 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
17354 | && strcmp (segname, ".sbss") != 0 |
17355 | && strncmp (segname, ".sdata.", 7) != 0 | |
d4dc2f22 TS |
17356 | && strncmp (segname, ".sbss.", 6) != 0 |
17357 | && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0 | |
fba2b7f9 | 17358 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); |
252b5132 RH |
17359 | } |
17360 | return change; | |
17361 | } | |
17362 | else | |
c9914766 | 17363 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
17364 | return 1; |
17365 | } | |
17366 | ||
5919d012 RS |
17367 | |
17368 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
17369 | ||
17370 | static bfd_boolean | |
9e009953 | 17371 | pic_need_relax (symbolS *sym) |
5919d012 RS |
17372 | { |
17373 | asection *symsec; | |
5919d012 RS |
17374 | |
17375 | /* Handle the case of a symbol equated to another symbol. */ | |
17376 | while (symbol_equated_reloc_p (sym)) | |
17377 | { | |
17378 | symbolS *n; | |
17379 | ||
5f0fe04b | 17380 | /* It's possible to get a loop here in a badly written program. */ |
5919d012 RS |
17381 | n = symbol_get_value_expression (sym)->X_add_symbol; |
17382 | if (n == sym) | |
17383 | break; | |
17384 | sym = n; | |
17385 | } | |
17386 | ||
df1f3cda DD |
17387 | if (symbol_section_p (sym)) |
17388 | return TRUE; | |
17389 | ||
5919d012 RS |
17390 | symsec = S_GET_SEGMENT (sym); |
17391 | ||
5919d012 | 17392 | /* This must duplicate the test in adjust_reloc_syms. */ |
45dfa85a AM |
17393 | return (!bfd_is_und_section (symsec) |
17394 | && !bfd_is_abs_section (symsec) | |
5f0fe04b | 17395 | && !bfd_is_com_section (symsec) |
5919d012 | 17396 | /* A global or weak symbol is treated as external. */ |
f3ded42a | 17397 | && (!S_IS_WEAK (sym) && !S_IS_EXTERNAL (sym))); |
5919d012 | 17398 | } |
14f72d45 MR |
17399 | \f |
17400 | /* Given a MIPS16 variant frag FRAGP and PC-relative operand PCREL_OP | |
17401 | convert a section-relative value VAL to the equivalent PC-relative | |
17402 | value. */ | |
17403 | ||
17404 | static offsetT | |
17405 | mips16_pcrel_val (fragS *fragp, const struct mips_pcrel_operand *pcrel_op, | |
17406 | offsetT val, long stretch) | |
17407 | { | |
17408 | fragS *sym_frag; | |
17409 | addressT addr; | |
17410 | ||
17411 | gas_assert (pcrel_op->root.root.type == OP_PCREL); | |
17412 | ||
17413 | sym_frag = symbol_get_frag (fragp->fr_symbol); | |
17414 | ||
17415 | /* If the relax_marker of the symbol fragment differs from the | |
17416 | relax_marker of this fragment, we have not yet adjusted the | |
17417 | symbol fragment fr_address. We want to add in STRETCH in | |
17418 | order to get a better estimate of the address. This | |
17419 | particularly matters because of the shift bits. */ | |
17420 | if (stretch != 0 && sym_frag->relax_marker != fragp->relax_marker) | |
17421 | { | |
17422 | fragS *f; | |
17423 | ||
17424 | /* Adjust stretch for any alignment frag. Note that if have | |
17425 | been expanding the earlier code, the symbol may be | |
17426 | defined in what appears to be an earlier frag. FIXME: | |
17427 | This doesn't handle the fr_subtype field, which specifies | |
17428 | a maximum number of bytes to skip when doing an | |
17429 | alignment. */ | |
17430 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) | |
17431 | { | |
17432 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
17433 | { | |
17434 | if (stretch < 0) | |
17435 | stretch = -(-stretch & ~((1 << (int) f->fr_offset) - 1)); | |
17436 | else | |
17437 | stretch &= ~((1 << (int) f->fr_offset) - 1); | |
17438 | if (stretch == 0) | |
17439 | break; | |
17440 | } | |
17441 | } | |
17442 | if (f != NULL) | |
17443 | val += stretch; | |
17444 | } | |
17445 | ||
17446 | addr = fragp->fr_address + fragp->fr_fix; | |
17447 | ||
17448 | /* The base address rules are complicated. The base address of | |
17449 | a branch is the following instruction. The base address of a | |
17450 | PC relative load or add is the instruction itself, but if it | |
17451 | is in a delay slot (in which case it can not be extended) use | |
17452 | the address of the instruction whose delay slot it is in. */ | |
17453 | if (pcrel_op->include_isa_bit) | |
17454 | { | |
17455 | addr += 2; | |
17456 | ||
17457 | /* If we are currently assuming that this frag should be | |
17458 | extended, then the current address is two bytes higher. */ | |
17459 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
17460 | addr += 2; | |
17461 | ||
17462 | /* Ignore the low bit in the target, since it will be set | |
17463 | for a text label. */ | |
17464 | val &= -2; | |
17465 | } | |
17466 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
17467 | addr -= 4; | |
17468 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
17469 | addr -= 2; | |
5919d012 | 17470 | |
14f72d45 MR |
17471 | val -= addr & -(1 << pcrel_op->align_log2); |
17472 | ||
17473 | return val; | |
17474 | } | |
5919d012 | 17475 | |
252b5132 RH |
17476 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
17477 | extended opcode. SEC is the section the frag is in. */ | |
17478 | ||
17479 | static int | |
17a2f251 | 17480 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 | 17481 | { |
3ccad066 | 17482 | const struct mips_int_operand *operand; |
252b5132 | 17483 | offsetT val; |
252b5132 | 17484 | segT symsec; |
14f72d45 | 17485 | int type; |
252b5132 RH |
17486 | |
17487 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
17488 | return 0; | |
17489 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
17490 | return 1; | |
17491 | ||
88a7ef16 | 17492 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 | 17493 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); |
3ccad066 | 17494 | operand = mips16_immed_operand (type, FALSE); |
88a7ef16 MR |
17495 | if (S_FORCE_RELOC (fragp->fr_symbol, TRUE) |
17496 | || (operand->root.type == OP_PCREL | |
17497 | ? sec != symsec | |
17498 | : !bfd_is_abs_section (symsec))) | |
17499 | return 1; | |
252b5132 | 17500 | |
88a7ef16 | 17501 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; |
252b5132 | 17502 | |
3ccad066 | 17503 | if (operand->root.type == OP_PCREL) |
252b5132 | 17504 | { |
3ccad066 | 17505 | const struct mips_pcrel_operand *pcrel_op; |
3ccad066 | 17506 | offsetT maxtiny; |
252b5132 | 17507 | |
1425c41d | 17508 | if (RELAX_MIPS16_ALWAYS_EXTENDED (fragp->fr_subtype)) |
88a7ef16 | 17509 | return 1; |
252b5132 | 17510 | |
88a7ef16 | 17511 | pcrel_op = (const struct mips_pcrel_operand *) operand; |
14f72d45 | 17512 | val = mips16_pcrel_val (fragp, pcrel_op, val, stretch); |
252b5132 RH |
17513 | |
17514 | /* If any of the shifted bits are set, we must use an extended | |
17515 | opcode. If the address depends on the size of this | |
17516 | instruction, this can lead to a loop, so we arrange to always | |
88a7ef16 MR |
17517 | use an extended opcode. */ |
17518 | if ((val & ((1 << operand->shift) - 1)) != 0) | |
252b5132 RH |
17519 | { |
17520 | fragp->fr_subtype = | |
1425c41d | 17521 | RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp->fr_subtype); |
252b5132 RH |
17522 | return 1; |
17523 | } | |
17524 | ||
17525 | /* If we are about to mark a frag as extended because the value | |
3ccad066 RS |
17526 | is precisely the next value above maxtiny, then there is a |
17527 | chance of an infinite loop as in the following code: | |
252b5132 RH |
17528 | la $4,foo |
17529 | .skip 1020 | |
17530 | .align 2 | |
17531 | foo: | |
17532 | In this case when the la is extended, foo is 0x3fc bytes | |
17533 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
17534 | the la must be extended. To avoid this loop, we mark the | |
17535 | frag as extended if it was small, and is about to become | |
3ccad066 RS |
17536 | extended with the next value above maxtiny. */ |
17537 | maxtiny = mips_int_operand_max (operand); | |
17538 | if (val == maxtiny + (1 << operand->shift) | |
88a7ef16 | 17539 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
252b5132 RH |
17540 | { |
17541 | fragp->fr_subtype = | |
1425c41d | 17542 | RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp->fr_subtype); |
252b5132 RH |
17543 | return 1; |
17544 | } | |
17545 | } | |
252b5132 | 17546 | |
3ccad066 | 17547 | return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val); |
252b5132 RH |
17548 | } |
17549 | ||
8507b6e7 MR |
17550 | /* Given a MIPS16 variant frag FRAGP, return non-zero if it needs |
17551 | macro expansion. SEC is the section the frag is in. We only | |
17552 | support PC-relative instructions (LA, DLA, LW, LD) here, in | |
17553 | non-PIC code using 32-bit addressing. */ | |
17554 | ||
17555 | static int | |
17556 | mips16_macro_frag (fragS *fragp, asection *sec, long stretch) | |
17557 | { | |
17558 | const struct mips_pcrel_operand *pcrel_op; | |
17559 | const struct mips_int_operand *operand; | |
17560 | offsetT val; | |
17561 | segT symsec; | |
17562 | int type; | |
17563 | ||
17564 | gas_assert (!RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)); | |
17565 | ||
17566 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
17567 | return 0; | |
17568 | if (!RELAX_MIPS16_SYM32 (fragp->fr_subtype)) | |
17569 | return 0; | |
17570 | ||
17571 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
17572 | switch (type) | |
17573 | { | |
17574 | case 'A': | |
17575 | case 'B': | |
17576 | case 'E': | |
17577 | symsec = S_GET_SEGMENT (fragp->fr_symbol); | |
17578 | if (bfd_is_abs_section (symsec)) | |
17579 | return 1; | |
17580 | if (RELAX_MIPS16_PIC (fragp->fr_subtype)) | |
17581 | return 0; | |
17582 | if (S_FORCE_RELOC (fragp->fr_symbol, TRUE) || sec != symsec) | |
17583 | return 1; | |
17584 | ||
17585 | operand = mips16_immed_operand (type, TRUE); | |
17586 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17587 | pcrel_op = (const struct mips_pcrel_operand *) operand; | |
17588 | val = mips16_pcrel_val (fragp, pcrel_op, val, stretch); | |
17589 | ||
17590 | return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val); | |
17591 | ||
17592 | default: | |
17593 | return 0; | |
17594 | } | |
17595 | } | |
17596 | ||
4a6a3df4 AO |
17597 | /* Compute the length of a branch sequence, and adjust the |
17598 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
17599 | worst-case length is computed, with UPDATE being used to indicate | |
17600 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
17601 | branch is to be computed. */ | |
17602 | static int | |
17a2f251 | 17603 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 17604 | { |
b34976b6 | 17605 | bfd_boolean toofar; |
4a6a3df4 AO |
17606 | int length; |
17607 | ||
17608 | if (fragp | |
17609 | && S_IS_DEFINED (fragp->fr_symbol) | |
991f40a9 | 17610 | && !S_IS_WEAK (fragp->fr_symbol) |
4a6a3df4 AO |
17611 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) |
17612 | { | |
17613 | addressT addr; | |
17614 | offsetT val; | |
17615 | ||
17616 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17617 | ||
17618 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
17619 | ||
17620 | val -= addr; | |
17621 | ||
17622 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
17623 | } | |
4a6a3df4 | 17624 | else |
c1f61bd2 MR |
17625 | /* If the symbol is not defined or it's in a different segment, |
17626 | we emit the long sequence. */ | |
b34976b6 | 17627 | toofar = TRUE; |
4a6a3df4 AO |
17628 | |
17629 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
17630 | fragp->fr_subtype | |
66b3e8da | 17631 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype), |
ce8ad872 | 17632 | RELAX_BRANCH_PIC (fragp->fr_subtype), |
66b3e8da | 17633 | RELAX_BRANCH_UNCOND (fragp->fr_subtype), |
4a6a3df4 AO |
17634 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
17635 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
17636 | toofar); | |
17637 | ||
17638 | length = 4; | |
17639 | if (toofar) | |
17640 | { | |
17641 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
17642 | length += 8; | |
17643 | ||
ce8ad872 | 17644 | if (!fragp || RELAX_BRANCH_PIC (fragp->fr_subtype)) |
4a6a3df4 AO |
17645 | { |
17646 | /* Additional space for PIC loading of target address. */ | |
17647 | length += 8; | |
17648 | if (mips_opts.isa == ISA_MIPS1) | |
17649 | /* Additional space for $at-stabilizing nop. */ | |
17650 | length += 4; | |
17651 | } | |
17652 | ||
17653 | /* If branch is conditional. */ | |
17654 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
17655 | length += 8; | |
17656 | } | |
b34976b6 | 17657 | |
4a6a3df4 AO |
17658 | return length; |
17659 | } | |
17660 | ||
7bd374a4 MR |
17661 | /* Get a FRAG's branch instruction delay slot size, either from the |
17662 | short-delay-slot bit of a branch-and-link instruction if AL is TRUE, | |
17663 | or SHORT_INSN_SIZE otherwise. */ | |
17664 | ||
17665 | static int | |
17666 | frag_branch_delay_slot_size (fragS *fragp, bfd_boolean al, int short_insn_size) | |
17667 | { | |
17668 | char *buf = fragp->fr_literal + fragp->fr_fix; | |
17669 | ||
17670 | if (al) | |
17671 | return (read_compressed_insn (buf, 4) & 0x02000000) ? 2 : 4; | |
17672 | else | |
17673 | return short_insn_size; | |
17674 | } | |
17675 | ||
df58fc94 RS |
17676 | /* Compute the length of a branch sequence, and adjust the |
17677 | RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the | |
17678 | worst-case length is computed, with UPDATE being used to indicate | |
17679 | whether an unconditional (-1), or regular (0) branch is to be | |
17680 | computed. */ | |
17681 | ||
17682 | static int | |
17683 | relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update) | |
17684 | { | |
7bd374a4 MR |
17685 | bfd_boolean insn32 = TRUE; |
17686 | bfd_boolean nods = TRUE; | |
ce8ad872 | 17687 | bfd_boolean pic = TRUE; |
7bd374a4 MR |
17688 | bfd_boolean al = TRUE; |
17689 | int short_insn_size; | |
df58fc94 RS |
17690 | bfd_boolean toofar; |
17691 | int length; | |
17692 | ||
7bd374a4 MR |
17693 | if (fragp) |
17694 | { | |
17695 | insn32 = RELAX_MICROMIPS_INSN32 (fragp->fr_subtype); | |
17696 | nods = RELAX_MICROMIPS_NODS (fragp->fr_subtype); | |
ce8ad872 | 17697 | pic = RELAX_MICROMIPS_PIC (fragp->fr_subtype); |
7bd374a4 MR |
17698 | al = RELAX_MICROMIPS_LINK (fragp->fr_subtype); |
17699 | } | |
17700 | short_insn_size = insn32 ? 4 : 2; | |
17701 | ||
df58fc94 RS |
17702 | if (fragp |
17703 | && S_IS_DEFINED (fragp->fr_symbol) | |
991f40a9 | 17704 | && !S_IS_WEAK (fragp->fr_symbol) |
df58fc94 RS |
17705 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) |
17706 | { | |
17707 | addressT addr; | |
17708 | offsetT val; | |
17709 | ||
17710 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17711 | /* Ignore the low bit in the target, since it will be set | |
17712 | for a text label. */ | |
17713 | if ((val & 1) != 0) | |
17714 | --val; | |
17715 | ||
17716 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
17717 | ||
17718 | val -= addr; | |
17719 | ||
17720 | toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1); | |
17721 | } | |
df58fc94 | 17722 | else |
c1f61bd2 MR |
17723 | /* If the symbol is not defined or it's in a different segment, |
17724 | we emit the long sequence. */ | |
df58fc94 RS |
17725 | toofar = TRUE; |
17726 | ||
17727 | if (fragp && update | |
17728 | && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
17729 | fragp->fr_subtype = (toofar | |
17730 | ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype) | |
17731 | : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype)); | |
17732 | ||
17733 | length = 4; | |
17734 | if (toofar) | |
17735 | { | |
17736 | bfd_boolean compact_known = fragp != NULL; | |
17737 | bfd_boolean compact = FALSE; | |
17738 | bfd_boolean uncond; | |
17739 | ||
df58fc94 | 17740 | if (fragp) |
8484fb75 MR |
17741 | { |
17742 | compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); | |
17743 | uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype); | |
8484fb75 | 17744 | } |
df58fc94 RS |
17745 | else |
17746 | uncond = update < 0; | |
17747 | ||
17748 | /* If label is out of range, we turn branch <br>: | |
17749 | ||
17750 | <br> label # 4 bytes | |
17751 | 0: | |
17752 | ||
17753 | into: | |
17754 | ||
17755 | j label # 4 bytes | |
8484fb75 MR |
17756 | nop # 2/4 bytes if |
17757 | # compact && (!PIC || insn32) | |
df58fc94 RS |
17758 | 0: |
17759 | */ | |
ce8ad872 | 17760 | if ((!pic || insn32) && (!compact_known || compact)) |
8484fb75 | 17761 | length += short_insn_size; |
df58fc94 RS |
17762 | |
17763 | /* If assembling PIC code, we further turn: | |
17764 | ||
17765 | j label # 4 bytes | |
17766 | ||
17767 | into: | |
17768 | ||
17769 | lw/ld at, %got(label)(gp) # 4 bytes | |
17770 | d/addiu at, %lo(label) # 4 bytes | |
8484fb75 | 17771 | jr/c at # 2/4 bytes |
df58fc94 | 17772 | */ |
ce8ad872 | 17773 | if (pic) |
8484fb75 | 17774 | length += 4 + short_insn_size; |
df58fc94 | 17775 | |
7bd374a4 MR |
17776 | /* Add an extra nop if the jump has no compact form and we need |
17777 | to fill the delay slot. */ | |
ce8ad872 | 17778 | if ((!pic || al) && nods) |
7bd374a4 MR |
17779 | length += (fragp |
17780 | ? frag_branch_delay_slot_size (fragp, al, short_insn_size) | |
17781 | : short_insn_size); | |
17782 | ||
df58fc94 RS |
17783 | /* If branch <br> is conditional, we prepend negated branch <brneg>: |
17784 | ||
17785 | <brneg> 0f # 4 bytes | |
8484fb75 | 17786 | nop # 2/4 bytes if !compact |
df58fc94 RS |
17787 | */ |
17788 | if (!uncond) | |
8484fb75 | 17789 | length += (compact_known && compact) ? 4 : 4 + short_insn_size; |
df58fc94 | 17790 | } |
7bd374a4 MR |
17791 | else if (nods) |
17792 | { | |
17793 | /* Add an extra nop to fill the delay slot. */ | |
17794 | gas_assert (fragp); | |
17795 | length += frag_branch_delay_slot_size (fragp, al, short_insn_size); | |
17796 | } | |
df58fc94 RS |
17797 | |
17798 | return length; | |
17799 | } | |
17800 | ||
17801 | /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16 | |
17802 | bit accordingly. */ | |
17803 | ||
17804 | static int | |
17805 | relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update) | |
17806 | { | |
17807 | bfd_boolean toofar; | |
17808 | ||
df58fc94 RS |
17809 | if (fragp |
17810 | && S_IS_DEFINED (fragp->fr_symbol) | |
991f40a9 | 17811 | && !S_IS_WEAK (fragp->fr_symbol) |
df58fc94 RS |
17812 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) |
17813 | { | |
17814 | addressT addr; | |
17815 | offsetT val; | |
17816 | int type; | |
17817 | ||
17818 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17819 | /* Ignore the low bit in the target, since it will be set | |
17820 | for a text label. */ | |
17821 | if ((val & 1) != 0) | |
17822 | --val; | |
17823 | ||
17824 | /* Assume this is a 2-byte branch. */ | |
17825 | addr = fragp->fr_address + fragp->fr_fix + 2; | |
17826 | ||
17827 | /* We try to avoid the infinite loop by not adding 2 more bytes for | |
17828 | long branches. */ | |
17829 | ||
17830 | val -= addr; | |
17831 | ||
17832 | type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
17833 | if (type == 'D') | |
17834 | toofar = val < - (0x200 << 1) || val >= (0x200 << 1); | |
17835 | else if (type == 'E') | |
17836 | toofar = val < - (0x40 << 1) || val >= (0x40 << 1); | |
17837 | else | |
17838 | abort (); | |
17839 | } | |
17840 | else | |
17841 | /* If the symbol is not defined or it's in a different segment, | |
17842 | we emit a normal 32-bit branch. */ | |
17843 | toofar = TRUE; | |
17844 | ||
17845 | if (fragp && update | |
17846 | && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
17847 | fragp->fr_subtype | |
17848 | = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype) | |
17849 | : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype); | |
17850 | ||
17851 | if (toofar) | |
17852 | return 4; | |
17853 | ||
17854 | return 2; | |
17855 | } | |
17856 | ||
252b5132 RH |
17857 | /* Estimate the size of a frag before relaxing. Unless this is the |
17858 | mips16, we are not really relaxing here, and the final size is | |
17859 | encoded in the subtype information. For the mips16, we have to | |
17860 | decide whether we are using an extended opcode or not. */ | |
17861 | ||
252b5132 | 17862 | int |
17a2f251 | 17863 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 17864 | { |
5919d012 | 17865 | int change; |
252b5132 | 17866 | |
4a6a3df4 AO |
17867 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
17868 | { | |
17869 | ||
b34976b6 AM |
17870 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
17871 | ||
4a6a3df4 AO |
17872 | return fragp->fr_var; |
17873 | } | |
17874 | ||
252b5132 | 17875 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
8507b6e7 MR |
17876 | { |
17877 | /* We don't want to modify the EXTENDED bit here; it might get us | |
17878 | into infinite loops. We change it only in mips_relax_frag(). */ | |
17879 | if (RELAX_MIPS16_MACRO (fragp->fr_subtype)) | |
25499ac7 | 17880 | return RELAX_MIPS16_E2 (fragp->fr_subtype) ? 8 : 12; |
8507b6e7 MR |
17881 | else |
17882 | return RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2; | |
17883 | } | |
252b5132 | 17884 | |
df58fc94 RS |
17885 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
17886 | { | |
17887 | int length = 4; | |
17888 | ||
17889 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
17890 | length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE); | |
17891 | if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
17892 | length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE); | |
17893 | fragp->fr_var = length; | |
17894 | ||
17895 | return length; | |
17896 | } | |
17897 | ||
ce8ad872 | 17898 | if (mips_pic == VXWORKS_PIC) |
0a44bf69 RS |
17899 | /* For vxworks, GOT16 relocations never have a corresponding LO16. */ |
17900 | change = 0; | |
ce8ad872 MR |
17901 | else if (RELAX_PIC (fragp->fr_subtype)) |
17902 | change = pic_need_relax (fragp->fr_symbol); | |
252b5132 | 17903 | else |
ce8ad872 | 17904 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 RH |
17905 | |
17906 | if (change) | |
17907 | { | |
4d7206a2 | 17908 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 17909 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 17910 | } |
4d7206a2 RS |
17911 | else |
17912 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
17913 | } |
17914 | ||
17915 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 17916 | should be converted into a reloc against a section. */ |
252b5132 RH |
17917 | |
17918 | int | |
17a2f251 | 17919 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 17920 | { |
252b5132 RH |
17921 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
17922 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
17923 | return 0; | |
a161fe53 | 17924 | |
252b5132 RH |
17925 | if (fixp->fx_addsy == NULL) |
17926 | return 1; | |
a161fe53 | 17927 | |
2f0c68f2 CM |
17928 | /* Allow relocs used for EH tables. */ |
17929 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) | |
17930 | return 1; | |
17931 | ||
de7e6852 RS |
17932 | /* If symbol SYM is in a mergeable section, relocations of the form |
17933 | SYM + 0 can usually be made section-relative. The mergeable data | |
17934 | is then identified by the section offset rather than by the symbol. | |
17935 | ||
17936 | However, if we're generating REL LO16 relocations, the offset is split | |
33eaf5de | 17937 | between the LO16 and partnering high part relocation. The linker will |
de7e6852 RS |
17938 | need to recalculate the complete offset in order to correctly identify |
17939 | the merge data. | |
17940 | ||
33eaf5de | 17941 | The linker has traditionally not looked for the partnering high part |
de7e6852 RS |
17942 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be |
17943 | placed anywhere. Rather than break backwards compatibility by changing | |
17944 | this, it seems better not to force the issue, and instead keep the | |
17945 | original symbol. This will work with either linker behavior. */ | |
738e5348 | 17946 | if ((lo16_reloc_p (fixp->fx_r_type) |
704803a9 | 17947 | || reloc_needs_lo_p (fixp->fx_r_type)) |
de7e6852 RS |
17948 | && HAVE_IN_PLACE_ADDENDS |
17949 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
17950 | return 0; | |
17951 | ||
97f50151 MR |
17952 | /* There is no place to store an in-place offset for JALR relocations. */ |
17953 | if (jalr_reloc_p (fixp->fx_r_type) && HAVE_IN_PLACE_ADDENDS) | |
17954 | return 0; | |
17955 | ||
17956 | /* Likewise an in-range offset of limited PC-relative relocations may | |
2de39019 | 17957 | overflow the in-place relocatable field if recalculated against the |
7361da2c AB |
17958 | start address of the symbol's containing section. |
17959 | ||
17960 | Also, PC relative relocations for MIPS R6 need to be symbol rather than | |
17961 | section relative to allow linker relaxations to be performed later on. */ | |
97f50151 | 17962 | if (limited_pcrel_reloc_p (fixp->fx_r_type) |
912815f0 | 17963 | && (HAVE_IN_PLACE_ADDENDS || ISA_IS_R6 (file_mips_opts.isa))) |
1180b5a4 RS |
17964 | return 0; |
17965 | ||
b314ec0e RS |
17966 | /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve |
17967 | to a floating-point stub. The same is true for non-R_MIPS16_26 | |
17968 | relocations against MIPS16 functions; in this case, the stub becomes | |
17969 | the function's canonical address. | |
17970 | ||
17971 | Floating-point stubs are stored in unique .mips16.call.* or | |
17972 | .mips16.fn.* sections. If a stub T for function F is in section S, | |
17973 | the first relocation in section S must be against F; this is how the | |
17974 | linker determines the target function. All relocations that might | |
17975 | resolve to T must also be against F. We therefore have the following | |
17976 | restrictions, which are given in an intentionally-redundant way: | |
17977 | ||
17978 | 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16 | |
17979 | symbols. | |
17980 | ||
17981 | 2. We cannot reduce a stub's relocations against non-MIPS16 symbols | |
17982 | if that stub might be used. | |
17983 | ||
17984 | 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16 | |
17985 | symbols. | |
17986 | ||
17987 | 4. We cannot reduce a stub's relocations against MIPS16 symbols if | |
17988 | that stub might be used. | |
17989 | ||
17990 | There is a further restriction: | |
17991 | ||
df58fc94 | 17992 | 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or |
0e9c5a5c | 17993 | R_MICROMIPS_26_S1) or branch relocations (R_MIPS_PC26_S2, |
c9775dde MR |
17994 | R_MIPS_PC21_S2, R_MIPS_PC16, R_MIPS16_PC16_S1, |
17995 | R_MICROMIPS_PC16_S1, R_MICROMIPS_PC10_S1 or R_MICROMIPS_PC7_S1) | |
17996 | against MIPS16 or microMIPS symbols because we need to keep the | |
17997 | MIPS16 or microMIPS symbol for the purpose of mode mismatch | |
a6ebf616 MR |
17998 | detection and JAL or BAL to JALX instruction conversion in the |
17999 | linker. | |
b314ec0e | 18000 | |
df58fc94 | 18001 | For simplicity, we deal with (3)-(4) by not reducing _any_ relocation |
507dcb32 | 18002 | against a MIPS16 symbol. We deal with (5) by additionally leaving |
0e9c5a5c | 18003 | alone any jump and branch relocations against a microMIPS symbol. |
b314ec0e RS |
18004 | |
18005 | We deal with (1)-(2) by saying that, if there's a R_MIPS16_26 | |
18006 | relocation against some symbol R, no relocation against R may be | |
18007 | reduced. (Note that this deals with (2) as well as (1) because | |
18008 | relocations against global symbols will never be reduced on ELF | |
18009 | targets.) This approach is a little simpler than trying to detect | |
18010 | stub sections, and gives the "all or nothing" per-symbol consistency | |
18011 | that we have for MIPS16 symbols. */ | |
f3ded42a | 18012 | if (fixp->fx_subsy == NULL |
30c09090 | 18013 | && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy)) |
44d3da23 | 18014 | || (ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy)) |
0e9c5a5c MR |
18015 | && (jmp_reloc_p (fixp->fx_r_type) |
18016 | || b_reloc_p (fixp->fx_r_type))) | |
44d3da23 | 18017 | || *symbol_get_tc (fixp->fx_addsy))) |
252b5132 | 18018 | return 0; |
a161fe53 | 18019 | |
252b5132 RH |
18020 | return 1; |
18021 | } | |
18022 | ||
18023 | /* Translate internal representation of relocation info to BFD target | |
18024 | format. */ | |
18025 | ||
18026 | arelent ** | |
17a2f251 | 18027 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
18028 | { |
18029 | static arelent *retval[4]; | |
18030 | arelent *reloc; | |
18031 | bfd_reloc_code_real_type code; | |
18032 | ||
4b0cff4e | 18033 | memset (retval, 0, sizeof(retval)); |
325801bd TS |
18034 | reloc = retval[0] = XCNEW (arelent); |
18035 | reloc->sym_ptr_ptr = XNEW (asymbol *); | |
49309057 | 18036 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
252b5132 RH |
18037 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
18038 | ||
bad36eac DJ |
18039 | if (fixp->fx_pcrel) |
18040 | { | |
df58fc94 | 18041 | gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 |
c9775dde | 18042 | || fixp->fx_r_type == BFD_RELOC_MIPS16_16_PCREL_S1 |
df58fc94 RS |
18043 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 |
18044 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
b47468a6 | 18045 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1 |
7361da2c AB |
18046 | || fixp->fx_r_type == BFD_RELOC_32_PCREL |
18047 | || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2 | |
18048 | || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2 | |
18049 | || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3 | |
18050 | || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2 | |
18051 | || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL | |
18052 | || fixp->fx_r_type == BFD_RELOC_LO16_PCREL); | |
bad36eac DJ |
18053 | |
18054 | /* At this point, fx_addnumber is "symbol offset - pcrel address". | |
18055 | Relocations want only the symbol offset. */ | |
51f6035b MR |
18056 | switch (fixp->fx_r_type) |
18057 | { | |
18058 | case BFD_RELOC_MIPS_18_PCREL_S3: | |
18059 | reloc->addend = fixp->fx_addnumber + (reloc->address & ~7); | |
18060 | break; | |
18061 | default: | |
18062 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
18063 | break; | |
18064 | } | |
bad36eac | 18065 | } |
17c6c9d9 MR |
18066 | else if (HAVE_IN_PLACE_ADDENDS |
18067 | && fixp->fx_r_type == BFD_RELOC_MICROMIPS_JMP | |
18068 | && (read_compressed_insn (fixp->fx_frag->fr_literal | |
18069 | + fixp->fx_where, 4) >> 26) == 0x3c) | |
18070 | { | |
18071 | /* Shift is 2, unusually, for microMIPS JALX. Adjust the in-place | |
18072 | addend accordingly. */ | |
18073 | reloc->addend = fixp->fx_addnumber >> 1; | |
18074 | } | |
bad36eac DJ |
18075 | else |
18076 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 18077 | |
438c16b8 TS |
18078 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
18079 | entry to be used in the relocation's section offset. */ | |
18080 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
18081 | { |
18082 | reloc->address = reloc->addend; | |
18083 | reloc->addend = 0; | |
18084 | } | |
18085 | ||
252b5132 | 18086 | code = fixp->fx_r_type; |
252b5132 | 18087 | |
bad36eac | 18088 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
252b5132 RH |
18089 | if (reloc->howto == NULL) |
18090 | { | |
18091 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
1661c76c RS |
18092 | _("cannot represent %s relocation in this object file" |
18093 | " format"), | |
252b5132 RH |
18094 | bfd_get_reloc_code_name (code)); |
18095 | retval[0] = NULL; | |
18096 | } | |
18097 | ||
18098 | return retval; | |
18099 | } | |
18100 | ||
18101 | /* Relax a machine dependent frag. This returns the amount by which | |
18102 | the current size of the frag should change. */ | |
18103 | ||
18104 | int | |
17a2f251 | 18105 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 18106 | { |
4a6a3df4 AO |
18107 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
18108 | { | |
18109 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
18110 | |
18111 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
18112 | |
18113 | return fragp->fr_var - old_var; | |
18114 | } | |
18115 | ||
df58fc94 RS |
18116 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
18117 | { | |
18118 | offsetT old_var = fragp->fr_var; | |
18119 | offsetT new_var = 4; | |
18120 | ||
18121 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
18122 | new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE); | |
18123 | if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
18124 | new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE); | |
18125 | fragp->fr_var = new_var; | |
18126 | ||
18127 | return new_var - old_var; | |
18128 | } | |
18129 | ||
252b5132 RH |
18130 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
18131 | return 0; | |
18132 | ||
8507b6e7 | 18133 | if (!mips16_extended_frag (fragp, sec, stretch)) |
252b5132 | 18134 | { |
8507b6e7 MR |
18135 | if (RELAX_MIPS16_MACRO (fragp->fr_subtype)) |
18136 | { | |
18137 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_MACRO (fragp->fr_subtype); | |
25499ac7 | 18138 | return RELAX_MIPS16_E2 (fragp->fr_subtype) ? -6 : -10; |
8507b6e7 MR |
18139 | } |
18140 | else if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
18141 | { | |
18142 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
18143 | return -2; | |
18144 | } | |
18145 | else | |
18146 | return 0; | |
18147 | } | |
18148 | else if (!mips16_macro_frag (fragp, sec, stretch)) | |
18149 | { | |
18150 | if (RELAX_MIPS16_MACRO (fragp->fr_subtype)) | |
18151 | { | |
18152 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_MACRO (fragp->fr_subtype); | |
18153 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
25499ac7 | 18154 | return RELAX_MIPS16_E2 (fragp->fr_subtype) ? -4 : -8; |
8507b6e7 MR |
18155 | } |
18156 | else if (!RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
18157 | { | |
18158 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
18159 | return 2; | |
18160 | } | |
18161 | else | |
252b5132 | 18162 | return 0; |
252b5132 RH |
18163 | } |
18164 | else | |
18165 | { | |
8507b6e7 | 18166 | if (RELAX_MIPS16_MACRO (fragp->fr_subtype)) |
252b5132 | 18167 | return 0; |
8507b6e7 MR |
18168 | else if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
18169 | { | |
18170 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
18171 | fragp->fr_subtype = RELAX_MIPS16_MARK_MACRO (fragp->fr_subtype); | |
25499ac7 | 18172 | return RELAX_MIPS16_E2 (fragp->fr_subtype) ? 4 : 8; |
8507b6e7 MR |
18173 | } |
18174 | else | |
18175 | { | |
18176 | fragp->fr_subtype = RELAX_MIPS16_MARK_MACRO (fragp->fr_subtype); | |
25499ac7 | 18177 | return RELAX_MIPS16_E2 (fragp->fr_subtype) ? 6 : 10; |
8507b6e7 | 18178 | } |
252b5132 RH |
18179 | } |
18180 | ||
18181 | return 0; | |
18182 | } | |
18183 | ||
18184 | /* Convert a machine dependent frag. */ | |
18185 | ||
18186 | void | |
17a2f251 | 18187 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 18188 | { |
4a6a3df4 AO |
18189 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
18190 | { | |
4d68580a | 18191 | char *buf; |
4a6a3df4 | 18192 | unsigned long insn; |
4a6a3df4 | 18193 | fixS *fixp; |
b34976b6 | 18194 | |
4d68580a RS |
18195 | buf = fragp->fr_literal + fragp->fr_fix; |
18196 | insn = read_insn (buf); | |
b34976b6 | 18197 | |
4a6a3df4 AO |
18198 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
18199 | { | |
18200 | /* We generate a fixup instead of applying it right now | |
18201 | because, if there are linker relaxations, we're going to | |
18202 | need the relocations. */ | |
bbd27b76 MR |
18203 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18204 | fragp->fr_symbol, fragp->fr_offset, | |
18205 | TRUE, BFD_RELOC_16_PCREL_S2); | |
4a6a3df4 AO |
18206 | fixp->fx_file = fragp->fr_file; |
18207 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 18208 | |
4d68580a | 18209 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18210 | } |
18211 | else | |
18212 | { | |
18213 | int i; | |
18214 | ||
18215 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
1661c76c | 18216 | _("relaxed out-of-range branch into a jump")); |
4a6a3df4 AO |
18217 | |
18218 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
18219 | goto uncond; | |
18220 | ||
18221 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18222 | { | |
18223 | /* Reverse the branch. */ | |
18224 | switch ((insn >> 28) & 0xf) | |
18225 | { | |
18226 | case 4: | |
56d438b1 CF |
18227 | if ((insn & 0xff000000) == 0x47000000 |
18228 | || (insn & 0xff600000) == 0x45600000) | |
18229 | { | |
18230 | /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition | |
18231 | reversed by tweaking bit 23. */ | |
18232 | insn ^= 0x00800000; | |
18233 | } | |
18234 | else | |
18235 | { | |
18236 | /* bc[0-3][tf]l? instructions can have the condition | |
18237 | reversed by tweaking a single TF bit, and their | |
18238 | opcodes all have 0x4???????. */ | |
18239 | gas_assert ((insn & 0xf3e00000) == 0x41000000); | |
18240 | insn ^= 0x00010000; | |
18241 | } | |
4a6a3df4 AO |
18242 | break; |
18243 | ||
18244 | case 0: | |
18245 | /* bltz 0x04000000 bgez 0x04010000 | |
54f4ddb3 | 18246 | bltzal 0x04100000 bgezal 0x04110000 */ |
9c2799c2 | 18247 | gas_assert ((insn & 0xfc0e0000) == 0x04000000); |
4a6a3df4 AO |
18248 | insn ^= 0x00010000; |
18249 | break; | |
b34976b6 | 18250 | |
4a6a3df4 AO |
18251 | case 1: |
18252 | /* beq 0x10000000 bne 0x14000000 | |
54f4ddb3 | 18253 | blez 0x18000000 bgtz 0x1c000000 */ |
4a6a3df4 AO |
18254 | insn ^= 0x04000000; |
18255 | break; | |
18256 | ||
18257 | default: | |
18258 | abort (); | |
18259 | } | |
18260 | } | |
18261 | ||
18262 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
18263 | { | |
18264 | /* Clear the and-link bit. */ | |
9c2799c2 | 18265 | gas_assert ((insn & 0xfc1c0000) == 0x04100000); |
4a6a3df4 | 18266 | |
54f4ddb3 TS |
18267 | /* bltzal 0x04100000 bgezal 0x04110000 |
18268 | bltzall 0x04120000 bgezall 0x04130000 */ | |
4a6a3df4 AO |
18269 | insn &= ~0x00100000; |
18270 | } | |
18271 | ||
18272 | /* Branch over the branch (if the branch was likely) or the | |
18273 | full jump (not likely case). Compute the offset from the | |
18274 | current instruction to branch to. */ | |
18275 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18276 | i = 16; | |
18277 | else | |
18278 | { | |
18279 | /* How many bytes in instructions we've already emitted? */ | |
4d68580a | 18280 | i = buf - fragp->fr_literal - fragp->fr_fix; |
4a6a3df4 AO |
18281 | /* How many bytes in instructions from here to the end? */ |
18282 | i = fragp->fr_var - i; | |
18283 | } | |
18284 | /* Convert to instruction count. */ | |
18285 | i >>= 2; | |
18286 | /* Branch counts from the next instruction. */ | |
b34976b6 | 18287 | i--; |
4a6a3df4 AO |
18288 | insn |= i; |
18289 | /* Branch over the jump. */ | |
4d68580a | 18290 | buf = write_insn (buf, insn); |
4a6a3df4 | 18291 | |
54f4ddb3 | 18292 | /* nop */ |
4d68580a | 18293 | buf = write_insn (buf, 0); |
4a6a3df4 AO |
18294 | |
18295 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18296 | { | |
18297 | /* beql $0, $0, 2f */ | |
18298 | insn = 0x50000000; | |
18299 | /* Compute the PC offset from the current instruction to | |
18300 | the end of the variable frag. */ | |
18301 | /* How many bytes in instructions we've already emitted? */ | |
4d68580a | 18302 | i = buf - fragp->fr_literal - fragp->fr_fix; |
4a6a3df4 AO |
18303 | /* How many bytes in instructions from here to the end? */ |
18304 | i = fragp->fr_var - i; | |
18305 | /* Convert to instruction count. */ | |
18306 | i >>= 2; | |
18307 | /* Don't decrement i, because we want to branch over the | |
18308 | delay slot. */ | |
4a6a3df4 | 18309 | insn |= i; |
4a6a3df4 | 18310 | |
4d68580a RS |
18311 | buf = write_insn (buf, insn); |
18312 | buf = write_insn (buf, 0); | |
4a6a3df4 AO |
18313 | } |
18314 | ||
18315 | uncond: | |
ce8ad872 | 18316 | if (!RELAX_BRANCH_PIC (fragp->fr_subtype)) |
4a6a3df4 AO |
18317 | { |
18318 | /* j or jal. */ | |
18319 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
18320 | ? 0x0c000000 : 0x08000000); | |
4a6a3df4 | 18321 | |
bbd27b76 MR |
18322 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18323 | fragp->fr_symbol, fragp->fr_offset, | |
18324 | FALSE, BFD_RELOC_MIPS_JMP); | |
4a6a3df4 AO |
18325 | fixp->fx_file = fragp->fr_file; |
18326 | fixp->fx_line = fragp->fr_line; | |
18327 | ||
4d68580a | 18328 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18329 | } |
18330 | else | |
18331 | { | |
66b3e8da MR |
18332 | unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype); |
18333 | ||
4a6a3df4 | 18334 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ |
66b3e8da MR |
18335 | insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000; |
18336 | insn |= at << OP_SH_RT; | |
4a6a3df4 | 18337 | |
bbd27b76 MR |
18338 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18339 | fragp->fr_symbol, fragp->fr_offset, | |
18340 | FALSE, BFD_RELOC_MIPS_GOT16); | |
4a6a3df4 AO |
18341 | fixp->fx_file = fragp->fr_file; |
18342 | fixp->fx_line = fragp->fr_line; | |
18343 | ||
4d68580a | 18344 | buf = write_insn (buf, insn); |
b34976b6 | 18345 | |
4a6a3df4 | 18346 | if (mips_opts.isa == ISA_MIPS1) |
4d68580a RS |
18347 | /* nop */ |
18348 | buf = write_insn (buf, 0); | |
4a6a3df4 AO |
18349 | |
18350 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
66b3e8da MR |
18351 | insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000; |
18352 | insn |= at << OP_SH_RS | at << OP_SH_RT; | |
4a6a3df4 | 18353 | |
bbd27b76 MR |
18354 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18355 | fragp->fr_symbol, fragp->fr_offset, | |
18356 | FALSE, BFD_RELOC_LO16); | |
4a6a3df4 AO |
18357 | fixp->fx_file = fragp->fr_file; |
18358 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 18359 | |
4d68580a | 18360 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18361 | |
18362 | /* j(al)r $at. */ | |
18363 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
66b3e8da | 18364 | insn = 0x0000f809; |
4a6a3df4 | 18365 | else |
66b3e8da MR |
18366 | insn = 0x00000008; |
18367 | insn |= at << OP_SH_RS; | |
4a6a3df4 | 18368 | |
4d68580a | 18369 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18370 | } |
18371 | } | |
18372 | ||
4a6a3df4 | 18373 | fragp->fr_fix += fragp->fr_var; |
4d68580a | 18374 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
4a6a3df4 AO |
18375 | return; |
18376 | } | |
18377 | ||
df58fc94 RS |
18378 | /* Relax microMIPS branches. */ |
18379 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) | |
18380 | { | |
4d68580a | 18381 | char *buf = fragp->fr_literal + fragp->fr_fix; |
df58fc94 | 18382 | bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); |
8484fb75 | 18383 | bfd_boolean insn32 = RELAX_MICROMIPS_INSN32 (fragp->fr_subtype); |
7bd374a4 | 18384 | bfd_boolean nods = RELAX_MICROMIPS_NODS (fragp->fr_subtype); |
ce8ad872 | 18385 | bfd_boolean pic = RELAX_MICROMIPS_PIC (fragp->fr_subtype); |
df58fc94 RS |
18386 | bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype); |
18387 | int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
2309ddf2 | 18388 | bfd_boolean short_ds; |
df58fc94 | 18389 | unsigned long insn; |
df58fc94 RS |
18390 | fixS *fixp; |
18391 | ||
df58fc94 RS |
18392 | fragp->fr_fix += fragp->fr_var; |
18393 | ||
18394 | /* Handle 16-bit branches that fit or are forced to fit. */ | |
18395 | if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
18396 | { | |
18397 | /* We generate a fixup instead of applying it right now, | |
18398 | because if there is linker relaxation, we're going to | |
18399 | need the relocations. */ | |
834a65aa MR |
18400 | switch (type) |
18401 | { | |
18402 | case 'D': | |
18403 | fixp = fix_new (fragp, buf - fragp->fr_literal, 2, | |
18404 | fragp->fr_symbol, fragp->fr_offset, | |
18405 | TRUE, BFD_RELOC_MICROMIPS_10_PCREL_S1); | |
18406 | break; | |
18407 | case 'E': | |
18408 | fixp = fix_new (fragp, buf - fragp->fr_literal, 2, | |
18409 | fragp->fr_symbol, fragp->fr_offset, | |
18410 | TRUE, BFD_RELOC_MICROMIPS_7_PCREL_S1); | |
18411 | break; | |
18412 | default: | |
18413 | abort (); | |
18414 | } | |
df58fc94 RS |
18415 | |
18416 | fixp->fx_file = fragp->fr_file; | |
18417 | fixp->fx_line = fragp->fr_line; | |
18418 | ||
18419 | /* These relocations can have an addend that won't fit in | |
18420 | 2 octets. */ | |
18421 | fixp->fx_no_overflow = 1; | |
18422 | ||
18423 | return; | |
18424 | } | |
18425 | ||
2309ddf2 | 18426 | /* Handle 32-bit branches that fit or are forced to fit. */ |
df58fc94 RS |
18427 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) |
18428 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
18429 | { | |
18430 | /* We generate a fixup instead of applying it right now, | |
18431 | because if there is linker relaxation, we're going to | |
18432 | need the relocations. */ | |
bbd27b76 MR |
18433 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18434 | fragp->fr_symbol, fragp->fr_offset, | |
18435 | TRUE, BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
df58fc94 RS |
18436 | fixp->fx_file = fragp->fr_file; |
18437 | fixp->fx_line = fragp->fr_line; | |
18438 | ||
18439 | if (type == 0) | |
7bd374a4 MR |
18440 | { |
18441 | insn = read_compressed_insn (buf, 4); | |
18442 | buf += 4; | |
18443 | ||
18444 | if (nods) | |
18445 | { | |
18446 | /* Check the short-delay-slot bit. */ | |
18447 | if (!al || (insn & 0x02000000) != 0) | |
18448 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
18449 | else | |
18450 | buf = write_compressed_insn (buf, 0x00000000, 4); | |
18451 | } | |
18452 | ||
18453 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); | |
18454 | return; | |
18455 | } | |
df58fc94 RS |
18456 | } |
18457 | ||
18458 | /* Relax 16-bit branches to 32-bit branches. */ | |
18459 | if (type != 0) | |
18460 | { | |
4d68580a | 18461 | insn = read_compressed_insn (buf, 2); |
df58fc94 RS |
18462 | |
18463 | if ((insn & 0xfc00) == 0xcc00) /* b16 */ | |
18464 | insn = 0x94000000; /* beq */ | |
18465 | else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */ | |
18466 | { | |
18467 | unsigned long regno; | |
18468 | ||
18469 | regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD; | |
18470 | regno = micromips_to_32_reg_d_map [regno]; | |
18471 | insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */ | |
18472 | insn |= regno << MICROMIPSOP_SH_RS; | |
18473 | } | |
18474 | else | |
18475 | abort (); | |
18476 | ||
18477 | /* Nothing else to do, just write it out. */ | |
18478 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) | |
18479 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
18480 | { | |
4d68580a | 18481 | buf = write_compressed_insn (buf, insn, 4); |
7bd374a4 MR |
18482 | if (nods) |
18483 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
4d68580a | 18484 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
df58fc94 RS |
18485 | return; |
18486 | } | |
18487 | } | |
18488 | else | |
4d68580a | 18489 | insn = read_compressed_insn (buf, 4); |
df58fc94 RS |
18490 | |
18491 | /* Relax 32-bit branches to a sequence of instructions. */ | |
18492 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
1661c76c | 18493 | _("relaxed out-of-range branch into a jump")); |
df58fc94 | 18494 | |
2309ddf2 | 18495 | /* Set the short-delay-slot bit. */ |
7bd374a4 | 18496 | short_ds = !al || (insn & 0x02000000) != 0; |
df58fc94 RS |
18497 | |
18498 | if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype)) | |
18499 | { | |
18500 | symbolS *l; | |
18501 | ||
18502 | /* Reverse the branch. */ | |
18503 | if ((insn & 0xfc000000) == 0x94000000 /* beq */ | |
18504 | || (insn & 0xfc000000) == 0xb4000000) /* bne */ | |
18505 | insn ^= 0x20000000; | |
18506 | else if ((insn & 0xffe00000) == 0x40000000 /* bltz */ | |
18507 | || (insn & 0xffe00000) == 0x40400000 /* bgez */ | |
18508 | || (insn & 0xffe00000) == 0x40800000 /* blez */ | |
18509 | || (insn & 0xffe00000) == 0x40c00000 /* bgtz */ | |
18510 | || (insn & 0xffe00000) == 0x40a00000 /* bnezc */ | |
18511 | || (insn & 0xffe00000) == 0x40e00000 /* beqzc */ | |
18512 | || (insn & 0xffe00000) == 0x40200000 /* bltzal */ | |
18513 | || (insn & 0xffe00000) == 0x40600000 /* bgezal */ | |
18514 | || (insn & 0xffe00000) == 0x42200000 /* bltzals */ | |
18515 | || (insn & 0xffe00000) == 0x42600000) /* bgezals */ | |
18516 | insn ^= 0x00400000; | |
18517 | else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */ | |
18518 | || (insn & 0xffe30000) == 0x43a00000 /* bc1t */ | |
18519 | || (insn & 0xffe30000) == 0x42800000 /* bc2f */ | |
18520 | || (insn & 0xffe30000) == 0x42a00000) /* bc2t */ | |
18521 | insn ^= 0x00200000; | |
56d438b1 CF |
18522 | else if ((insn & 0xff000000) == 0x83000000 /* BZ.df |
18523 | BNZ.df */ | |
18524 | || (insn & 0xff600000) == 0x81600000) /* BZ.V | |
18525 | BNZ.V */ | |
18526 | insn ^= 0x00800000; | |
df58fc94 RS |
18527 | else |
18528 | abort (); | |
18529 | ||
18530 | if (al) | |
18531 | { | |
18532 | /* Clear the and-link and short-delay-slot bits. */ | |
18533 | gas_assert ((insn & 0xfda00000) == 0x40200000); | |
18534 | ||
18535 | /* bltzal 0x40200000 bgezal 0x40600000 */ | |
18536 | /* bltzals 0x42200000 bgezals 0x42600000 */ | |
18537 | insn &= ~0x02200000; | |
18538 | } | |
18539 | ||
18540 | /* Make a label at the end for use with the branch. */ | |
18541 | l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp); | |
18542 | micromips_label_inc (); | |
f3ded42a | 18543 | S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l))); |
df58fc94 RS |
18544 | |
18545 | /* Refer to it. */ | |
4d68580a RS |
18546 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE, |
18547 | BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
df58fc94 RS |
18548 | fixp->fx_file = fragp->fr_file; |
18549 | fixp->fx_line = fragp->fr_line; | |
18550 | ||
18551 | /* Branch over the jump. */ | |
4d68580a | 18552 | buf = write_compressed_insn (buf, insn, 4); |
8484fb75 | 18553 | |
df58fc94 | 18554 | if (!compact) |
8484fb75 MR |
18555 | { |
18556 | /* nop */ | |
18557 | if (insn32) | |
18558 | buf = write_compressed_insn (buf, 0x00000000, 4); | |
18559 | else | |
18560 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
18561 | } | |
df58fc94 RS |
18562 | } |
18563 | ||
ce8ad872 | 18564 | if (!pic) |
df58fc94 | 18565 | { |
7bd374a4 MR |
18566 | unsigned long jal = (short_ds || nods |
18567 | ? 0x74000000 : 0xf4000000); /* jal/s */ | |
2309ddf2 | 18568 | |
df58fc94 RS |
18569 | /* j/jal/jals <sym> R_MICROMIPS_26_S1 */ |
18570 | insn = al ? jal : 0xd4000000; | |
18571 | ||
bbd27b76 MR |
18572 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18573 | fragp->fr_symbol, fragp->fr_offset, | |
18574 | FALSE, BFD_RELOC_MICROMIPS_JMP); | |
df58fc94 RS |
18575 | fixp->fx_file = fragp->fr_file; |
18576 | fixp->fx_line = fragp->fr_line; | |
18577 | ||
4d68580a | 18578 | buf = write_compressed_insn (buf, insn, 4); |
8484fb75 | 18579 | |
7bd374a4 | 18580 | if (compact || nods) |
8484fb75 MR |
18581 | { |
18582 | /* nop */ | |
18583 | if (insn32) | |
18584 | buf = write_compressed_insn (buf, 0x00000000, 4); | |
18585 | else | |
18586 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
18587 | } | |
df58fc94 RS |
18588 | } |
18589 | else | |
18590 | { | |
18591 | unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype); | |
18592 | ||
18593 | /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */ | |
18594 | insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000; | |
18595 | insn |= at << MICROMIPSOP_SH_RT; | |
18596 | ||
bbd27b76 MR |
18597 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18598 | fragp->fr_symbol, fragp->fr_offset, | |
18599 | FALSE, BFD_RELOC_MICROMIPS_GOT16); | |
df58fc94 RS |
18600 | fixp->fx_file = fragp->fr_file; |
18601 | fixp->fx_line = fragp->fr_line; | |
18602 | ||
4d68580a | 18603 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 RS |
18604 | |
18605 | /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */ | |
18606 | insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000; | |
18607 | insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS; | |
18608 | ||
bbd27b76 MR |
18609 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18610 | fragp->fr_symbol, fragp->fr_offset, | |
18611 | FALSE, BFD_RELOC_MICROMIPS_LO16); | |
df58fc94 RS |
18612 | fixp->fx_file = fragp->fr_file; |
18613 | fixp->fx_line = fragp->fr_line; | |
18614 | ||
4d68580a | 18615 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 | 18616 | |
8484fb75 MR |
18617 | if (insn32) |
18618 | { | |
18619 | /* jr/jalr $at */ | |
18620 | insn = 0x00000f3c | (al ? RA : ZERO) << MICROMIPSOP_SH_RT; | |
18621 | insn |= at << MICROMIPSOP_SH_RS; | |
18622 | ||
18623 | buf = write_compressed_insn (buf, insn, 4); | |
df58fc94 | 18624 | |
7bd374a4 | 18625 | if (compact || nods) |
8484fb75 MR |
18626 | /* nop */ |
18627 | buf = write_compressed_insn (buf, 0x00000000, 4); | |
18628 | } | |
18629 | else | |
18630 | { | |
18631 | /* jr/jrc/jalr/jalrs $at */ | |
18632 | unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */ | |
7bd374a4 | 18633 | unsigned long jr = compact || nods ? 0x45a0 : 0x4580; /* jr/c */ |
8484fb75 MR |
18634 | |
18635 | insn = al ? jalr : jr; | |
18636 | insn |= at << MICROMIPSOP_SH_MJ; | |
18637 | ||
18638 | buf = write_compressed_insn (buf, insn, 2); | |
7bd374a4 MR |
18639 | if (al && nods) |
18640 | { | |
18641 | /* nop */ | |
18642 | if (short_ds) | |
18643 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
18644 | else | |
18645 | buf = write_compressed_insn (buf, 0x00000000, 4); | |
18646 | } | |
8484fb75 | 18647 | } |
df58fc94 RS |
18648 | } |
18649 | ||
4d68580a | 18650 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
df58fc94 RS |
18651 | return; |
18652 | } | |
18653 | ||
252b5132 RH |
18654 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
18655 | { | |
18656 | int type; | |
3ccad066 | 18657 | const struct mips_int_operand *operand; |
252b5132 | 18658 | offsetT val; |
5c04167a | 18659 | char *buf; |
8507b6e7 | 18660 | unsigned int user_length; |
9d862524 | 18661 | bfd_boolean need_reloc; |
252b5132 | 18662 | unsigned long insn; |
8507b6e7 | 18663 | bfd_boolean mac; |
5c04167a | 18664 | bfd_boolean ext; |
88a7ef16 | 18665 | segT symsec; |
252b5132 RH |
18666 | |
18667 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
3ccad066 | 18668 | operand = mips16_immed_operand (type, FALSE); |
252b5132 | 18669 | |
8507b6e7 | 18670 | mac = RELAX_MIPS16_MACRO (fragp->fr_subtype); |
5c04167a | 18671 | ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype); |
88a7ef16 | 18672 | val = resolve_symbol_value (fragp->fr_symbol) + fragp->fr_offset; |
9d862524 MR |
18673 | |
18674 | symsec = S_GET_SEGMENT (fragp->fr_symbol); | |
18675 | need_reloc = (S_FORCE_RELOC (fragp->fr_symbol, TRUE) | |
8507b6e7 | 18676 | || (operand->root.type == OP_PCREL && !mac |
9d862524 MR |
18677 | ? asec != symsec |
18678 | : !bfd_is_abs_section (symsec))); | |
18679 | ||
8507b6e7 | 18680 | if (operand->root.type == OP_PCREL && !mac) |
252b5132 | 18681 | { |
3ccad066 | 18682 | const struct mips_pcrel_operand *pcrel_op; |
252b5132 | 18683 | |
3ccad066 | 18684 | pcrel_op = (const struct mips_pcrel_operand *) operand; |
252b5132 | 18685 | |
14f72d45 | 18686 | if (pcrel_op->include_isa_bit && !need_reloc) |
252b5132 | 18687 | { |
37b2d327 MR |
18688 | if (!mips_ignore_branch_isa |
18689 | && !ELF_ST_IS_MIPS16 (S_GET_OTHER (fragp->fr_symbol))) | |
14f72d45 MR |
18690 | as_bad_where (fragp->fr_file, fragp->fr_line, |
18691 | _("branch to a symbol in another ISA mode")); | |
18692 | else if ((fragp->fr_offset & 0x1) != 0) | |
18693 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
18694 | _("branch to misaligned address (0x%lx)"), | |
18695 | (long) val); | |
252b5132 | 18696 | } |
252b5132 | 18697 | |
14f72d45 | 18698 | val = mips16_pcrel_val (fragp, pcrel_op, val, 0); |
252b5132 RH |
18699 | |
18700 | /* Make sure the section winds up with the alignment we have | |
18701 | assumed. */ | |
3ccad066 RS |
18702 | if (operand->shift > 0) |
18703 | record_alignment (asec, operand->shift); | |
252b5132 RH |
18704 | } |
18705 | ||
8507b6e7 MR |
18706 | if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) |
18707 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
18708 | { | |
18709 | if (mac) | |
18710 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
18711 | _("macro instruction expanded into multiple " | |
18712 | "instructions in a branch delay slot")); | |
18713 | else if (ext) | |
18714 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
18715 | _("extended instruction in a branch delay slot")); | |
18716 | } | |
18717 | else if (RELAX_MIPS16_NOMACRO (fragp->fr_subtype) && mac) | |
252b5132 | 18718 | as_warn_where (fragp->fr_file, fragp->fr_line, |
8507b6e7 MR |
18719 | _("macro instruction expanded into multiple " |
18720 | "instructions")); | |
252b5132 | 18721 | |
5c04167a | 18722 | buf = fragp->fr_literal + fragp->fr_fix; |
252b5132 | 18723 | |
4d68580a | 18724 | insn = read_compressed_insn (buf, 2); |
5c04167a RS |
18725 | if (ext) |
18726 | insn |= MIPS16_EXTEND; | |
252b5132 | 18727 | |
5c04167a RS |
18728 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) |
18729 | user_length = 4; | |
18730 | else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
18731 | user_length = 2; | |
18732 | else | |
18733 | user_length = 0; | |
18734 | ||
8507b6e7 | 18735 | if (mac) |
c9775dde | 18736 | { |
8507b6e7 MR |
18737 | unsigned long reg; |
18738 | unsigned long new; | |
18739 | unsigned long op; | |
25499ac7 | 18740 | bfd_boolean e2; |
8507b6e7 MR |
18741 | |
18742 | gas_assert (type == 'A' || type == 'B' || type == 'E'); | |
18743 | gas_assert (RELAX_MIPS16_SYM32 (fragp->fr_subtype)); | |
c9775dde | 18744 | |
25499ac7 MR |
18745 | e2 = RELAX_MIPS16_E2 (fragp->fr_subtype); |
18746 | ||
8507b6e7 | 18747 | if (need_reloc) |
c9775dde | 18748 | { |
8507b6e7 MR |
18749 | fixS *fixp; |
18750 | ||
18751 | gas_assert (!RELAX_MIPS16_PIC (fragp->fr_subtype)); | |
18752 | ||
18753 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, | |
18754 | fragp->fr_symbol, fragp->fr_offset, | |
18755 | FALSE, BFD_RELOC_MIPS16_HI16_S); | |
18756 | fixp->fx_file = fragp->fr_file; | |
18757 | fixp->fx_line = fragp->fr_line; | |
18758 | ||
25499ac7 | 18759 | fixp = fix_new (fragp, buf - fragp->fr_literal + (e2 ? 4 : 8), 4, |
8507b6e7 MR |
18760 | fragp->fr_symbol, fragp->fr_offset, |
18761 | FALSE, BFD_RELOC_MIPS16_LO16); | |
18762 | fixp->fx_file = fragp->fr_file; | |
18763 | fixp->fx_line = fragp->fr_line; | |
18764 | ||
18765 | val = 0; | |
18766 | } | |
18767 | ||
18768 | switch (insn & 0xf800) | |
18769 | { | |
18770 | case 0x0800: /* ADDIU */ | |
18771 | reg = (insn >> 8) & 0x7; | |
18772 | op = 0xf0004800 | (reg << 8); | |
c9775dde | 18773 | break; |
8507b6e7 MR |
18774 | case 0xb000: /* LW */ |
18775 | reg = (insn >> 8) & 0x7; | |
18776 | op = 0xf0009800 | (reg << 8) | (reg << 5); | |
c9775dde | 18777 | break; |
8507b6e7 MR |
18778 | case 0xf800: /* I64 */ |
18779 | reg = (insn >> 5) & 0x7; | |
18780 | switch (insn & 0x0700) | |
18781 | { | |
18782 | case 0x0400: /* LD */ | |
18783 | op = 0xf0003800 | (reg << 8) | (reg << 5); | |
18784 | break; | |
18785 | case 0x0600: /* DADDIU */ | |
18786 | op = 0xf000fd00 | (reg << 5); | |
18787 | break; | |
18788 | default: | |
18789 | abort (); | |
18790 | } | |
18791 | break; | |
18792 | default: | |
18793 | abort (); | |
c9775dde | 18794 | } |
8507b6e7 | 18795 | |
25499ac7 | 18796 | new = (e2 ? 0xf0006820 : 0xf0006800) | (reg << 8); /* LUI/LI */ |
8507b6e7 MR |
18797 | new |= mips16_immed_extend ((val + 0x8000) >> 16, 16); |
18798 | buf = write_compressed_insn (buf, new, 4); | |
25499ac7 MR |
18799 | if (!e2) |
18800 | { | |
18801 | new = 0xf4003000 | (reg << 8) | (reg << 5); /* SLL */ | |
18802 | buf = write_compressed_insn (buf, new, 4); | |
18803 | } | |
8507b6e7 MR |
18804 | op |= mips16_immed_extend (val, 16); |
18805 | buf = write_compressed_insn (buf, op, 4); | |
18806 | ||
25499ac7 | 18807 | fragp->fr_fix += e2 ? 8 : 12; |
8507b6e7 MR |
18808 | } |
18809 | else | |
18810 | { | |
18811 | unsigned int length = ext ? 4 : 2; | |
18812 | ||
18813 | if (need_reloc) | |
c9775dde | 18814 | { |
8507b6e7 | 18815 | bfd_reloc_code_real_type reloc = BFD_RELOC_NONE; |
8507b6e7 | 18816 | fixS *fixp; |
c9775dde | 18817 | |
8507b6e7 MR |
18818 | switch (type) |
18819 | { | |
18820 | case 'p': | |
18821 | case 'q': | |
18822 | reloc = BFD_RELOC_MIPS16_16_PCREL_S1; | |
18823 | break; | |
18824 | default: | |
18825 | break; | |
18826 | } | |
18827 | if (mac || reloc == BFD_RELOC_NONE) | |
18828 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
18829 | _("unsupported relocation")); | |
18830 | else if (ext) | |
18831 | { | |
bbd27b76 MR |
18832 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18833 | fragp->fr_symbol, fragp->fr_offset, | |
18834 | TRUE, reloc); | |
8507b6e7 MR |
18835 | fixp->fx_file = fragp->fr_file; |
18836 | fixp->fx_line = fragp->fr_line; | |
18837 | } | |
18838 | else | |
18839 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
18840 | _("invalid unextended operand value")); | |
c9775dde | 18841 | } |
eefc3365 | 18842 | else |
8507b6e7 MR |
18843 | mips16_immed (fragp->fr_file, fragp->fr_line, type, |
18844 | BFD_RELOC_UNUSED, val, user_length, &insn); | |
252b5132 | 18845 | |
8507b6e7 MR |
18846 | gas_assert (mips16_opcode_length (insn) == length); |
18847 | write_compressed_insn (buf, insn, length); | |
18848 | fragp->fr_fix += length; | |
18849 | } | |
252b5132 RH |
18850 | } |
18851 | else | |
18852 | { | |
df58fc94 RS |
18853 | relax_substateT subtype = fragp->fr_subtype; |
18854 | bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0; | |
18855 | bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0; | |
4d7206a2 RS |
18856 | int first, second; |
18857 | fixS *fixp; | |
252b5132 | 18858 | |
df58fc94 RS |
18859 | first = RELAX_FIRST (subtype); |
18860 | second = RELAX_SECOND (subtype); | |
4d7206a2 | 18861 | fixp = (fixS *) fragp->fr_opcode; |
252b5132 | 18862 | |
df58fc94 RS |
18863 | /* If the delay slot chosen does not match the size of the instruction, |
18864 | then emit a warning. */ | |
18865 | if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0) | |
18866 | || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)) | |
18867 | { | |
18868 | relax_substateT s; | |
18869 | const char *msg; | |
18870 | ||
18871 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
18872 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
18873 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
18874 | msg = macro_warning (s); | |
18875 | if (msg != NULL) | |
db9b2be4 | 18876 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
df58fc94 RS |
18877 | subtype &= ~s; |
18878 | } | |
18879 | ||
584892a6 | 18880 | /* Possibly emit a warning if we've chosen the longer option. */ |
df58fc94 | 18881 | if (use_second == second_longer) |
584892a6 | 18882 | { |
df58fc94 RS |
18883 | relax_substateT s; |
18884 | const char *msg; | |
18885 | ||
18886 | s = (subtype | |
18887 | & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT)); | |
18888 | msg = macro_warning (s); | |
18889 | if (msg != NULL) | |
db9b2be4 | 18890 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
df58fc94 | 18891 | subtype &= ~s; |
584892a6 RS |
18892 | } |
18893 | ||
4d7206a2 RS |
18894 | /* Go through all the fixups for the first sequence. Disable them |
18895 | (by marking them as done) if we're going to use the second | |
18896 | sequence instead. */ | |
18897 | while (fixp | |
18898 | && fixp->fx_frag == fragp | |
18899 | && fixp->fx_where < fragp->fr_fix - second) | |
18900 | { | |
df58fc94 | 18901 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18902 | fixp->fx_done = 1; |
18903 | fixp = fixp->fx_next; | |
18904 | } | |
252b5132 | 18905 | |
4d7206a2 RS |
18906 | /* Go through the fixups for the second sequence. Disable them if |
18907 | we're going to use the first sequence, otherwise adjust their | |
18908 | addresses to account for the relaxation. */ | |
18909 | while (fixp && fixp->fx_frag == fragp) | |
18910 | { | |
df58fc94 | 18911 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18912 | fixp->fx_where -= first; |
18913 | else | |
18914 | fixp->fx_done = 1; | |
18915 | fixp = fixp->fx_next; | |
18916 | } | |
18917 | ||
18918 | /* Now modify the frag contents. */ | |
df58fc94 | 18919 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18920 | { |
18921 | char *start; | |
18922 | ||
18923 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
18924 | memmove (start, start + first, second); | |
18925 | fragp->fr_fix -= first; | |
18926 | } | |
18927 | else | |
18928 | fragp->fr_fix -= second; | |
252b5132 RH |
18929 | } |
18930 | } | |
18931 | ||
252b5132 RH |
18932 | /* This function is called after the relocs have been generated. |
18933 | We've been storing mips16 text labels as odd. Here we convert them | |
18934 | back to even for the convenience of the debugger. */ | |
18935 | ||
18936 | void | |
17a2f251 | 18937 | mips_frob_file_after_relocs (void) |
252b5132 RH |
18938 | { |
18939 | asymbol **syms; | |
18940 | unsigned int count, i; | |
18941 | ||
252b5132 RH |
18942 | syms = bfd_get_outsymbols (stdoutput); |
18943 | count = bfd_get_symcount (stdoutput); | |
18944 | for (i = 0; i < count; i++, syms++) | |
df58fc94 RS |
18945 | if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other) |
18946 | && ((*syms)->value & 1) != 0) | |
18947 | { | |
18948 | (*syms)->value &= ~1; | |
18949 | /* If the symbol has an odd size, it was probably computed | |
18950 | incorrectly, so adjust that as well. */ | |
18951 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
18952 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
18953 | } | |
252b5132 RH |
18954 | } |
18955 | ||
a1facbec MR |
18956 | /* This function is called whenever a label is defined, including fake |
18957 | labels instantiated off the dot special symbol. It is used when | |
18958 | handling branch delays; if a branch has a label, we assume we cannot | |
18959 | move it. This also bumps the value of the symbol by 1 in compressed | |
18960 | code. */ | |
252b5132 | 18961 | |
e1b47bd5 | 18962 | static void |
a1facbec | 18963 | mips_record_label (symbolS *sym) |
252b5132 | 18964 | { |
a8dbcb85 | 18965 | segment_info_type *si = seg_info (now_seg); |
252b5132 RH |
18966 | struct insn_label_list *l; |
18967 | ||
18968 | if (free_insn_labels == NULL) | |
325801bd | 18969 | l = XNEW (struct insn_label_list); |
252b5132 RH |
18970 | else |
18971 | { | |
18972 | l = free_insn_labels; | |
18973 | free_insn_labels = l->next; | |
18974 | } | |
18975 | ||
18976 | l->label = sym; | |
a8dbcb85 TS |
18977 | l->next = si->label_list; |
18978 | si->label_list = l; | |
a1facbec | 18979 | } |
07a53e5c | 18980 | |
a1facbec MR |
18981 | /* This function is called as tc_frob_label() whenever a label is defined |
18982 | and adds a DWARF-2 record we only want for true labels. */ | |
18983 | ||
18984 | void | |
18985 | mips_define_label (symbolS *sym) | |
18986 | { | |
18987 | mips_record_label (sym); | |
07a53e5c | 18988 | dwarf2_emit_label (sym); |
252b5132 | 18989 | } |
e1b47bd5 RS |
18990 | |
18991 | /* This function is called by tc_new_dot_label whenever a new dot symbol | |
18992 | is defined. */ | |
18993 | ||
18994 | void | |
18995 | mips_add_dot_label (symbolS *sym) | |
18996 | { | |
18997 | mips_record_label (sym); | |
18998 | if (mips_assembling_insn && HAVE_CODE_COMPRESSION) | |
18999 | mips_compressed_mark_label (sym); | |
19000 | } | |
252b5132 | 19001 | \f |
351cdf24 MF |
19002 | /* Converting ASE flags from internal to .MIPS.abiflags values. */ |
19003 | static unsigned int | |
19004 | mips_convert_ase_flags (int ase) | |
19005 | { | |
19006 | unsigned int ext_ases = 0; | |
19007 | ||
19008 | if (ase & ASE_DSP) | |
19009 | ext_ases |= AFL_ASE_DSP; | |
19010 | if (ase & ASE_DSPR2) | |
19011 | ext_ases |= AFL_ASE_DSPR2; | |
8f4f9071 MF |
19012 | if (ase & ASE_DSPR3) |
19013 | ext_ases |= AFL_ASE_DSPR3; | |
351cdf24 MF |
19014 | if (ase & ASE_EVA) |
19015 | ext_ases |= AFL_ASE_EVA; | |
19016 | if (ase & ASE_MCU) | |
19017 | ext_ases |= AFL_ASE_MCU; | |
19018 | if (ase & ASE_MDMX) | |
19019 | ext_ases |= AFL_ASE_MDMX; | |
19020 | if (ase & ASE_MIPS3D) | |
19021 | ext_ases |= AFL_ASE_MIPS3D; | |
19022 | if (ase & ASE_MT) | |
19023 | ext_ases |= AFL_ASE_MT; | |
19024 | if (ase & ASE_SMARTMIPS) | |
19025 | ext_ases |= AFL_ASE_SMARTMIPS; | |
19026 | if (ase & ASE_VIRT) | |
19027 | ext_ases |= AFL_ASE_VIRT; | |
19028 | if (ase & ASE_MSA) | |
19029 | ext_ases |= AFL_ASE_MSA; | |
19030 | if (ase & ASE_XPA) | |
19031 | ext_ases |= AFL_ASE_XPA; | |
25499ac7 MR |
19032 | if (ase & ASE_MIPS16E2) |
19033 | ext_ases |= file_ase_mips16 ? AFL_ASE_MIPS16E2 : 0; | |
730c3174 SE |
19034 | if (ase & ASE_CRC) |
19035 | ext_ases |= AFL_ASE_CRC; | |
6f20c942 FS |
19036 | if (ase & ASE_GINV) |
19037 | ext_ases |= AFL_ASE_GINV; | |
8095d2f7 CX |
19038 | if (ase & ASE_LOONGSON_MMI) |
19039 | ext_ases |= AFL_ASE_LOONGSON_MMI; | |
716c08de CX |
19040 | if (ase & ASE_LOONGSON_CAM) |
19041 | ext_ases |= AFL_ASE_LOONGSON_CAM; | |
351cdf24 MF |
19042 | |
19043 | return ext_ases; | |
19044 | } | |
252b5132 RH |
19045 | /* Some special processing for a MIPS ELF file. */ |
19046 | ||
19047 | void | |
17a2f251 | 19048 | mips_elf_final_processing (void) |
252b5132 | 19049 | { |
351cdf24 MF |
19050 | int fpabi; |
19051 | Elf_Internal_ABIFlags_v0 flags; | |
19052 | ||
19053 | flags.version = 0; | |
19054 | flags.isa_rev = 0; | |
19055 | switch (file_mips_opts.isa) | |
19056 | { | |
19057 | case INSN_ISA1: | |
19058 | flags.isa_level = 1; | |
19059 | break; | |
19060 | case INSN_ISA2: | |
19061 | flags.isa_level = 2; | |
19062 | break; | |
19063 | case INSN_ISA3: | |
19064 | flags.isa_level = 3; | |
19065 | break; | |
19066 | case INSN_ISA4: | |
19067 | flags.isa_level = 4; | |
19068 | break; | |
19069 | case INSN_ISA5: | |
19070 | flags.isa_level = 5; | |
19071 | break; | |
19072 | case INSN_ISA32: | |
19073 | flags.isa_level = 32; | |
19074 | flags.isa_rev = 1; | |
19075 | break; | |
19076 | case INSN_ISA32R2: | |
19077 | flags.isa_level = 32; | |
19078 | flags.isa_rev = 2; | |
19079 | break; | |
19080 | case INSN_ISA32R3: | |
19081 | flags.isa_level = 32; | |
19082 | flags.isa_rev = 3; | |
19083 | break; | |
19084 | case INSN_ISA32R5: | |
19085 | flags.isa_level = 32; | |
19086 | flags.isa_rev = 5; | |
19087 | break; | |
09c14161 MF |
19088 | case INSN_ISA32R6: |
19089 | flags.isa_level = 32; | |
19090 | flags.isa_rev = 6; | |
19091 | break; | |
351cdf24 MF |
19092 | case INSN_ISA64: |
19093 | flags.isa_level = 64; | |
19094 | flags.isa_rev = 1; | |
19095 | break; | |
19096 | case INSN_ISA64R2: | |
19097 | flags.isa_level = 64; | |
19098 | flags.isa_rev = 2; | |
19099 | break; | |
19100 | case INSN_ISA64R3: | |
19101 | flags.isa_level = 64; | |
19102 | flags.isa_rev = 3; | |
19103 | break; | |
19104 | case INSN_ISA64R5: | |
19105 | flags.isa_level = 64; | |
19106 | flags.isa_rev = 5; | |
19107 | break; | |
09c14161 MF |
19108 | case INSN_ISA64R6: |
19109 | flags.isa_level = 64; | |
19110 | flags.isa_rev = 6; | |
19111 | break; | |
351cdf24 MF |
19112 | } |
19113 | ||
19114 | flags.gpr_size = file_mips_opts.gp == 32 ? AFL_REG_32 : AFL_REG_64; | |
19115 | flags.cpr1_size = file_mips_opts.soft_float ? AFL_REG_NONE | |
19116 | : (file_mips_opts.ase & ASE_MSA) ? AFL_REG_128 | |
19117 | : (file_mips_opts.fp == 64) ? AFL_REG_64 | |
19118 | : AFL_REG_32; | |
19119 | flags.cpr2_size = AFL_REG_NONE; | |
19120 | flags.fp_abi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, | |
19121 | Tag_GNU_MIPS_ABI_FP); | |
19122 | flags.isa_ext = bfd_mips_isa_ext (stdoutput); | |
19123 | flags.ases = mips_convert_ase_flags (file_mips_opts.ase); | |
19124 | if (file_ase_mips16) | |
19125 | flags.ases |= AFL_ASE_MIPS16; | |
19126 | if (file_ase_micromips) | |
19127 | flags.ases |= AFL_ASE_MICROMIPS; | |
19128 | flags.flags1 = 0; | |
19129 | if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts.isa, file_mips_opts.arch) | |
19130 | || file_mips_opts.fp == 64) | |
19131 | && file_mips_opts.oddspreg) | |
19132 | flags.flags1 |= AFL_FLAGS1_ODDSPREG; | |
19133 | flags.flags2 = 0; | |
19134 | ||
19135 | bfd_mips_elf_swap_abiflags_v0_out (stdoutput, &flags, | |
19136 | ((Elf_External_ABIFlags_v0 *) | |
19137 | mips_flags_frag)); | |
19138 | ||
252b5132 | 19139 | /* Write out the register information. */ |
316f5878 | 19140 | if (mips_abi != N64_ABI) |
252b5132 RH |
19141 | { |
19142 | Elf32_RegInfo s; | |
19143 | ||
19144 | s.ri_gprmask = mips_gprmask; | |
19145 | s.ri_cprmask[0] = mips_cprmask[0]; | |
19146 | s.ri_cprmask[1] = mips_cprmask[1]; | |
19147 | s.ri_cprmask[2] = mips_cprmask[2]; | |
19148 | s.ri_cprmask[3] = mips_cprmask[3]; | |
19149 | /* The gp_value field is set by the MIPS ELF backend. */ | |
19150 | ||
19151 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
19152 | ((Elf32_External_RegInfo *) | |
19153 | mips_regmask_frag)); | |
19154 | } | |
19155 | else | |
19156 | { | |
19157 | Elf64_Internal_RegInfo s; | |
19158 | ||
19159 | s.ri_gprmask = mips_gprmask; | |
19160 | s.ri_pad = 0; | |
19161 | s.ri_cprmask[0] = mips_cprmask[0]; | |
19162 | s.ri_cprmask[1] = mips_cprmask[1]; | |
19163 | s.ri_cprmask[2] = mips_cprmask[2]; | |
19164 | s.ri_cprmask[3] = mips_cprmask[3]; | |
19165 | /* The gp_value field is set by the MIPS ELF backend. */ | |
19166 | ||
19167 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
19168 | ((Elf64_External_RegInfo *) | |
19169 | mips_regmask_frag)); | |
19170 | } | |
19171 | ||
19172 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
19173 | sort of BFD interface for this. */ | |
19174 | if (mips_any_noreorder) | |
19175 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
19176 | if (mips_pic != NO_PIC) | |
143d77c5 | 19177 | { |
8b828383 | 19178 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
19179 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
19180 | } | |
19181 | if (mips_abicalls) | |
19182 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 19183 | |
b015e599 AP |
19184 | /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags |
19185 | defined at present; this might need to change in future. */ | |
a4672219 TS |
19186 | if (file_ase_mips16) |
19187 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
df58fc94 RS |
19188 | if (file_ase_micromips) |
19189 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS; | |
919731af | 19190 | if (file_mips_opts.ase & ASE_MDMX) |
deec1734 | 19191 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; |
1f25f5d3 | 19192 | |
bdaaa2e1 | 19193 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 19194 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 19195 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 19196 | else if (mips_abi == O64_ABI) |
252b5132 | 19197 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 19198 | else if (mips_abi == EABI_ABI) |
252b5132 | 19199 | { |
bad1aba3 | 19200 | if (file_mips_opts.gp == 64) |
252b5132 RH |
19201 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
19202 | else | |
19203 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
19204 | } | |
be00bddd | 19205 | |
defc8e2b | 19206 | /* Nothing to do for N32_ABI or N64_ABI. */ |
252b5132 RH |
19207 | |
19208 | if (mips_32bitmode) | |
19209 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
ad3fea08 | 19210 | |
7361da2c | 19211 | if (mips_nan2008 == 1) |
ba92f887 MR |
19212 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NAN2008; |
19213 | ||
ad3fea08 | 19214 | /* 32 bit code with 64 bit FP registers. */ |
351cdf24 MF |
19215 | fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, |
19216 | Tag_GNU_MIPS_ABI_FP); | |
19217 | if (fpabi == Val_GNU_MIPS_ABI_FP_OLD_64) | |
f1c38003 | 19218 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_FP64; |
252b5132 | 19219 | } |
252b5132 | 19220 | \f |
beae10d5 | 19221 | typedef struct proc { |
9b2f1d35 EC |
19222 | symbolS *func_sym; |
19223 | symbolS *func_end_sym; | |
beae10d5 KH |
19224 | unsigned long reg_mask; |
19225 | unsigned long reg_offset; | |
19226 | unsigned long fpreg_mask; | |
19227 | unsigned long fpreg_offset; | |
19228 | unsigned long frame_offset; | |
19229 | unsigned long frame_reg; | |
19230 | unsigned long pc_reg; | |
19231 | } procS; | |
252b5132 RH |
19232 | |
19233 | static procS cur_proc; | |
19234 | static procS *cur_proc_ptr; | |
19235 | static int numprocs; | |
19236 | ||
df58fc94 RS |
19237 | /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop |
19238 | as "2", and a normal nop as "0". */ | |
19239 | ||
19240 | #define NOP_OPCODE_MIPS 0 | |
19241 | #define NOP_OPCODE_MIPS16 1 | |
19242 | #define NOP_OPCODE_MICROMIPS 2 | |
742a56fe RS |
19243 | |
19244 | char | |
19245 | mips_nop_opcode (void) | |
19246 | { | |
df58fc94 RS |
19247 | if (seg_info (now_seg)->tc_segment_info_data.micromips) |
19248 | return NOP_OPCODE_MICROMIPS; | |
19249 | else if (seg_info (now_seg)->tc_segment_info_data.mips16) | |
19250 | return NOP_OPCODE_MIPS16; | |
19251 | else | |
19252 | return NOP_OPCODE_MIPS; | |
742a56fe RS |
19253 | } |
19254 | ||
df58fc94 RS |
19255 | /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use |
19256 | 32-bit microMIPS NOPs here (if applicable). */ | |
a19d8eb0 | 19257 | |
0a9ef439 | 19258 | void |
17a2f251 | 19259 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 19260 | { |
df58fc94 | 19261 | char nop_opcode; |
742a56fe | 19262 | char *p; |
c67a084a NC |
19263 | int bytes, size, excess; |
19264 | valueT opcode; | |
742a56fe | 19265 | |
0a9ef439 RH |
19266 | if (fragp->fr_type != rs_align_code) |
19267 | return; | |
19268 | ||
742a56fe | 19269 | p = fragp->fr_literal + fragp->fr_fix; |
df58fc94 RS |
19270 | nop_opcode = *p; |
19271 | switch (nop_opcode) | |
a19d8eb0 | 19272 | { |
df58fc94 RS |
19273 | case NOP_OPCODE_MICROMIPS: |
19274 | opcode = micromips_nop32_insn.insn_opcode; | |
19275 | size = 4; | |
19276 | break; | |
19277 | case NOP_OPCODE_MIPS16: | |
c67a084a NC |
19278 | opcode = mips16_nop_insn.insn_opcode; |
19279 | size = 2; | |
df58fc94 RS |
19280 | break; |
19281 | case NOP_OPCODE_MIPS: | |
19282 | default: | |
c67a084a NC |
19283 | opcode = nop_insn.insn_opcode; |
19284 | size = 4; | |
df58fc94 | 19285 | break; |
c67a084a | 19286 | } |
a19d8eb0 | 19287 | |
c67a084a NC |
19288 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
19289 | excess = bytes % size; | |
df58fc94 RS |
19290 | |
19291 | /* Handle the leading part if we're not inserting a whole number of | |
19292 | instructions, and make it the end of the fixed part of the frag. | |
19293 | Try to fit in a short microMIPS NOP if applicable and possible, | |
19294 | and use zeroes otherwise. */ | |
19295 | gas_assert (excess < 4); | |
19296 | fragp->fr_fix += excess; | |
19297 | switch (excess) | |
c67a084a | 19298 | { |
df58fc94 RS |
19299 | case 3: |
19300 | *p++ = '\0'; | |
19301 | /* Fall through. */ | |
19302 | case 2: | |
833794fc | 19303 | if (nop_opcode == NOP_OPCODE_MICROMIPS && !mips_opts.insn32) |
df58fc94 | 19304 | { |
4d68580a | 19305 | p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2); |
df58fc94 RS |
19306 | break; |
19307 | } | |
19308 | *p++ = '\0'; | |
19309 | /* Fall through. */ | |
19310 | case 1: | |
19311 | *p++ = '\0'; | |
19312 | /* Fall through. */ | |
19313 | case 0: | |
19314 | break; | |
a19d8eb0 | 19315 | } |
c67a084a NC |
19316 | |
19317 | md_number_to_chars (p, opcode, size); | |
19318 | fragp->fr_var = size; | |
a19d8eb0 CP |
19319 | } |
19320 | ||
252b5132 | 19321 | static long |
17a2f251 | 19322 | get_number (void) |
252b5132 RH |
19323 | { |
19324 | int negative = 0; | |
19325 | long val = 0; | |
19326 | ||
19327 | if (*input_line_pointer == '-') | |
19328 | { | |
19329 | ++input_line_pointer; | |
19330 | negative = 1; | |
19331 | } | |
3882b010 | 19332 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 19333 | as_bad (_("expected simple number")); |
252b5132 RH |
19334 | if (input_line_pointer[0] == '0') |
19335 | { | |
19336 | if (input_line_pointer[1] == 'x') | |
19337 | { | |
19338 | input_line_pointer += 2; | |
3882b010 | 19339 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
19340 | { |
19341 | val <<= 4; | |
19342 | val |= hex_value (*input_line_pointer++); | |
19343 | } | |
19344 | return negative ? -val : val; | |
19345 | } | |
19346 | else | |
19347 | { | |
19348 | ++input_line_pointer; | |
3882b010 | 19349 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
19350 | { |
19351 | val <<= 3; | |
19352 | val |= *input_line_pointer++ - '0'; | |
19353 | } | |
19354 | return negative ? -val : val; | |
19355 | } | |
19356 | } | |
3882b010 | 19357 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
19358 | { |
19359 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
19360 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 19361 | as_warn (_("invalid number")); |
252b5132 RH |
19362 | return -1; |
19363 | } | |
3882b010 | 19364 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
19365 | { |
19366 | val *= 10; | |
19367 | val += *input_line_pointer++ - '0'; | |
19368 | } | |
19369 | return negative ? -val : val; | |
19370 | } | |
19371 | ||
19372 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
19373 | is an initial number which is the ECOFF file index. In the non-ECOFF |
19374 | case .file implies DWARF-2. */ | |
19375 | ||
19376 | static void | |
17a2f251 | 19377 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 19378 | { |
ecb4347a DJ |
19379 | static int first_file_directive = 0; |
19380 | ||
c5dd6aab DJ |
19381 | if (ECOFF_DEBUGGING) |
19382 | { | |
19383 | get_number (); | |
19384 | s_app_file (0); | |
19385 | } | |
19386 | else | |
ecb4347a DJ |
19387 | { |
19388 | char *filename; | |
19389 | ||
68d20676 | 19390 | filename = dwarf2_directive_filename (); |
ecb4347a DJ |
19391 | |
19392 | /* Versions of GCC up to 3.1 start files with a ".file" | |
19393 | directive even for stabs output. Make sure that this | |
19394 | ".file" is handled. Note that you need a version of GCC | |
19395 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
19396 | if (filename != NULL && ! first_file_directive) | |
19397 | { | |
19398 | (void) new_logical_line (filename, -1); | |
c04f5787 | 19399 | s_app_file_string (filename, 0); |
ecb4347a DJ |
19400 | } |
19401 | first_file_directive = 1; | |
19402 | } | |
c5dd6aab DJ |
19403 | } |
19404 | ||
19405 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
19406 | |
19407 | static void | |
17a2f251 | 19408 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 19409 | { |
c5dd6aab DJ |
19410 | if (!ECOFF_DEBUGGING) |
19411 | dwarf2_directive_loc (0); | |
252b5132 RH |
19412 | } |
19413 | ||
252b5132 RH |
19414 | /* The .end directive. */ |
19415 | ||
19416 | static void | |
17a2f251 | 19417 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
19418 | { |
19419 | symbolS *p; | |
252b5132 | 19420 | |
7a621144 DJ |
19421 | /* Following functions need their own .frame and .cprestore directives. */ |
19422 | mips_frame_reg_valid = 0; | |
19423 | mips_cprestore_valid = 0; | |
19424 | ||
252b5132 RH |
19425 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
19426 | { | |
19427 | p = get_symbol (); | |
19428 | demand_empty_rest_of_line (); | |
19429 | } | |
19430 | else | |
19431 | p = NULL; | |
19432 | ||
14949570 | 19433 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
19434 | as_warn (_(".end not in text section")); |
19435 | ||
19436 | if (!cur_proc_ptr) | |
19437 | { | |
1661c76c | 19438 | as_warn (_(".end directive without a preceding .ent directive")); |
252b5132 RH |
19439 | demand_empty_rest_of_line (); |
19440 | return; | |
19441 | } | |
19442 | ||
19443 | if (p != NULL) | |
19444 | { | |
9c2799c2 | 19445 | gas_assert (S_GET_NAME (p)); |
9b2f1d35 | 19446 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
1661c76c | 19447 | as_warn (_(".end symbol does not match .ent symbol")); |
ecb4347a DJ |
19448 | |
19449 | if (debug_type == DEBUG_STABS) | |
19450 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
19451 | S_GET_NAME (p)); | |
252b5132 RH |
19452 | } |
19453 | else | |
19454 | as_warn (_(".end directive missing or unknown symbol")); | |
19455 | ||
9b2f1d35 EC |
19456 | /* Create an expression to calculate the size of the function. */ |
19457 | if (p && cur_proc_ptr) | |
19458 | { | |
19459 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
325801bd | 19460 | expressionS *exp = XNEW (expressionS); |
9b2f1d35 EC |
19461 | |
19462 | obj->size = exp; | |
19463 | exp->X_op = O_subtract; | |
19464 | exp->X_add_symbol = symbol_temp_new_now (); | |
19465 | exp->X_op_symbol = p; | |
19466 | exp->X_add_number = 0; | |
19467 | ||
19468 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
19469 | } | |
19470 | ||
5ff6a06c MR |
19471 | #ifdef md_flush_pending_output |
19472 | md_flush_pending_output (); | |
19473 | #endif | |
19474 | ||
ecb4347a | 19475 | /* Generate a .pdr section. */ |
f3ded42a | 19476 | if (!ECOFF_DEBUGGING && mips_flag_pdr) |
ecb4347a DJ |
19477 | { |
19478 | segT saved_seg = now_seg; | |
19479 | subsegT saved_subseg = now_subseg; | |
ecb4347a DJ |
19480 | expressionS exp; |
19481 | char *fragp; | |
252b5132 | 19482 | |
9c2799c2 | 19483 | gas_assert (pdr_seg); |
ecb4347a | 19484 | subseg_set (pdr_seg, 0); |
252b5132 | 19485 | |
ecb4347a DJ |
19486 | /* Write the symbol. */ |
19487 | exp.X_op = O_symbol; | |
19488 | exp.X_add_symbol = p; | |
19489 | exp.X_add_number = 0; | |
19490 | emit_expr (&exp, 4); | |
252b5132 | 19491 | |
ecb4347a | 19492 | fragp = frag_more (7 * 4); |
252b5132 | 19493 | |
17a2f251 TS |
19494 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
19495 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
19496 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
19497 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
19498 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
19499 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
19500 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 19501 | |
ecb4347a DJ |
19502 | subseg_set (saved_seg, saved_subseg); |
19503 | } | |
252b5132 RH |
19504 | |
19505 | cur_proc_ptr = NULL; | |
19506 | } | |
19507 | ||
19508 | /* The .aent and .ent directives. */ | |
19509 | ||
19510 | static void | |
17a2f251 | 19511 | s_mips_ent (int aent) |
252b5132 | 19512 | { |
252b5132 | 19513 | symbolS *symbolP; |
252b5132 RH |
19514 | |
19515 | symbolP = get_symbol (); | |
19516 | if (*input_line_pointer == ',') | |
f9419b05 | 19517 | ++input_line_pointer; |
252b5132 | 19518 | SKIP_WHITESPACE (); |
3882b010 | 19519 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 19520 | || *input_line_pointer == '-') |
874e8986 | 19521 | get_number (); |
252b5132 | 19522 | |
14949570 | 19523 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
1661c76c | 19524 | as_warn (_(".ent or .aent not in text section")); |
252b5132 RH |
19525 | |
19526 | if (!aent && cur_proc_ptr) | |
9a41af64 | 19527 | as_warn (_("missing .end")); |
252b5132 RH |
19528 | |
19529 | if (!aent) | |
19530 | { | |
7a621144 DJ |
19531 | /* This function needs its own .frame and .cprestore directives. */ |
19532 | mips_frame_reg_valid = 0; | |
19533 | mips_cprestore_valid = 0; | |
19534 | ||
252b5132 RH |
19535 | cur_proc_ptr = &cur_proc; |
19536 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
19537 | ||
9b2f1d35 | 19538 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 19539 | |
f9419b05 | 19540 | ++numprocs; |
ecb4347a DJ |
19541 | |
19542 | if (debug_type == DEBUG_STABS) | |
19543 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
19544 | S_GET_NAME (symbolP)); | |
252b5132 RH |
19545 | } |
19546 | ||
7c0fc524 MR |
19547 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
19548 | ||
252b5132 RH |
19549 | demand_empty_rest_of_line (); |
19550 | } | |
19551 | ||
19552 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 19553 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 19554 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 19555 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
19556 | symbol table (in the mdebug section). */ |
19557 | ||
19558 | static void | |
17a2f251 | 19559 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 19560 | { |
f3ded42a RS |
19561 | if (ECOFF_DEBUGGING) |
19562 | s_ignore (ignore); | |
19563 | else | |
ecb4347a DJ |
19564 | { |
19565 | long val; | |
252b5132 | 19566 | |
ecb4347a DJ |
19567 | if (cur_proc_ptr == (procS *) NULL) |
19568 | { | |
19569 | as_warn (_(".frame outside of .ent")); | |
19570 | demand_empty_rest_of_line (); | |
19571 | return; | |
19572 | } | |
252b5132 | 19573 | |
ecb4347a DJ |
19574 | cur_proc_ptr->frame_reg = tc_get_register (1); |
19575 | ||
19576 | SKIP_WHITESPACE (); | |
19577 | if (*input_line_pointer++ != ',' | |
19578 | || get_absolute_expression_and_terminator (&val) != ',') | |
19579 | { | |
1661c76c | 19580 | as_warn (_("bad .frame directive")); |
ecb4347a DJ |
19581 | --input_line_pointer; |
19582 | demand_empty_rest_of_line (); | |
19583 | return; | |
19584 | } | |
252b5132 | 19585 | |
ecb4347a DJ |
19586 | cur_proc_ptr->frame_offset = val; |
19587 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 19588 | |
252b5132 | 19589 | demand_empty_rest_of_line (); |
252b5132 | 19590 | } |
252b5132 RH |
19591 | } |
19592 | ||
bdaaa2e1 KH |
19593 | /* The .fmask and .mask directives. If the mdebug section is present |
19594 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 19595 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 19596 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
19597 | make reference to the ecoff symbol table (in the mdebug section). */ |
19598 | ||
19599 | static void | |
17a2f251 | 19600 | s_mips_mask (int reg_type) |
252b5132 | 19601 | { |
f3ded42a RS |
19602 | if (ECOFF_DEBUGGING) |
19603 | s_ignore (reg_type); | |
19604 | else | |
252b5132 | 19605 | { |
ecb4347a | 19606 | long mask, off; |
252b5132 | 19607 | |
ecb4347a DJ |
19608 | if (cur_proc_ptr == (procS *) NULL) |
19609 | { | |
19610 | as_warn (_(".mask/.fmask outside of .ent")); | |
19611 | demand_empty_rest_of_line (); | |
19612 | return; | |
19613 | } | |
252b5132 | 19614 | |
ecb4347a DJ |
19615 | if (get_absolute_expression_and_terminator (&mask) != ',') |
19616 | { | |
1661c76c | 19617 | as_warn (_("bad .mask/.fmask directive")); |
ecb4347a DJ |
19618 | --input_line_pointer; |
19619 | demand_empty_rest_of_line (); | |
19620 | return; | |
19621 | } | |
252b5132 | 19622 | |
ecb4347a DJ |
19623 | off = get_absolute_expression (); |
19624 | ||
19625 | if (reg_type == 'F') | |
19626 | { | |
19627 | cur_proc_ptr->fpreg_mask = mask; | |
19628 | cur_proc_ptr->fpreg_offset = off; | |
19629 | } | |
19630 | else | |
19631 | { | |
19632 | cur_proc_ptr->reg_mask = mask; | |
19633 | cur_proc_ptr->reg_offset = off; | |
19634 | } | |
19635 | ||
19636 | demand_empty_rest_of_line (); | |
252b5132 | 19637 | } |
252b5132 RH |
19638 | } |
19639 | ||
316f5878 RS |
19640 | /* A table describing all the processors gas knows about. Names are |
19641 | matched in the order listed. | |
e7af610e | 19642 | |
316f5878 RS |
19643 | To ease comparison, please keep this table in the same order as |
19644 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
19645 | static const struct mips_cpu_info mips_cpu_info_table[] = |
19646 | { | |
316f5878 | 19647 | /* Entries for generic ISAs */ |
d16afab6 RS |
19648 | { "mips1", MIPS_CPU_IS_ISA, 0, ISA_MIPS1, CPU_R3000 }, |
19649 | { "mips2", MIPS_CPU_IS_ISA, 0, ISA_MIPS2, CPU_R6000 }, | |
19650 | { "mips3", MIPS_CPU_IS_ISA, 0, ISA_MIPS3, CPU_R4000 }, | |
19651 | { "mips4", MIPS_CPU_IS_ISA, 0, ISA_MIPS4, CPU_R8000 }, | |
19652 | { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 }, | |
19653 | { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 }, | |
19654 | { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ae52f483 AB |
19655 | { "mips32r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R3, CPU_MIPS32R3 }, |
19656 | { "mips32r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R5, CPU_MIPS32R5 }, | |
7361da2c | 19657 | { "mips32r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R6, CPU_MIPS32R6 }, |
d16afab6 RS |
19658 | { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 }, |
19659 | { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 }, | |
ae52f483 AB |
19660 | { "mips64r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R3, CPU_MIPS64R3 }, |
19661 | { "mips64r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R5, CPU_MIPS64R5 }, | |
7361da2c | 19662 | { "mips64r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R6, CPU_MIPS64R6 }, |
316f5878 RS |
19663 | |
19664 | /* MIPS I */ | |
d16afab6 RS |
19665 | { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 }, |
19666 | { "r2000", 0, 0, ISA_MIPS1, CPU_R3000 }, | |
19667 | { "r3900", 0, 0, ISA_MIPS1, CPU_R3900 }, | |
316f5878 RS |
19668 | |
19669 | /* MIPS II */ | |
d16afab6 | 19670 | { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 }, |
316f5878 RS |
19671 | |
19672 | /* MIPS III */ | |
d16afab6 RS |
19673 | { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 }, |
19674 | { "r4010", 0, 0, ISA_MIPS2, CPU_R4010 }, | |
19675 | { "vr4100", 0, 0, ISA_MIPS3, CPU_VR4100 }, | |
19676 | { "vr4111", 0, 0, ISA_MIPS3, CPU_R4111 }, | |
19677 | { "vr4120", 0, 0, ISA_MIPS3, CPU_VR4120 }, | |
19678 | { "vr4130", 0, 0, ISA_MIPS3, CPU_VR4120 }, | |
19679 | { "vr4181", 0, 0, ISA_MIPS3, CPU_R4111 }, | |
19680 | { "vr4300", 0, 0, ISA_MIPS3, CPU_R4300 }, | |
19681 | { "r4400", 0, 0, ISA_MIPS3, CPU_R4400 }, | |
19682 | { "r4600", 0, 0, ISA_MIPS3, CPU_R4600 }, | |
19683 | { "orion", 0, 0, ISA_MIPS3, CPU_R4600 }, | |
19684 | { "r4650", 0, 0, ISA_MIPS3, CPU_R4650 }, | |
19685 | { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 }, | |
b15591bb | 19686 | /* ST Microelectronics Loongson 2E and 2F cores */ |
d16afab6 | 19687 | { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E }, |
8095d2f7 | 19688 | { "loongson2f", 0, ASE_LOONGSON_MMI, ISA_MIPS3, CPU_LOONGSON_2F }, |
316f5878 RS |
19689 | |
19690 | /* MIPS IV */ | |
d16afab6 RS |
19691 | { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 }, |
19692 | { "r10000", 0, 0, ISA_MIPS4, CPU_R10000 }, | |
19693 | { "r12000", 0, 0, ISA_MIPS4, CPU_R12000 }, | |
19694 | { "r14000", 0, 0, ISA_MIPS4, CPU_R14000 }, | |
19695 | { "r16000", 0, 0, ISA_MIPS4, CPU_R16000 }, | |
19696 | { "vr5000", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19697 | { "vr5400", 0, 0, ISA_MIPS4, CPU_VR5400 }, | |
19698 | { "vr5500", 0, 0, ISA_MIPS4, CPU_VR5500 }, | |
19699 | { "rm5200", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19700 | { "rm5230", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19701 | { "rm5231", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19702 | { "rm5261", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19703 | { "rm5721", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19704 | { "rm7000", 0, 0, ISA_MIPS4, CPU_RM7000 }, | |
19705 | { "rm9000", 0, 0, ISA_MIPS4, CPU_RM9000 }, | |
316f5878 RS |
19706 | |
19707 | /* MIPS 32 */ | |
d16afab6 RS |
19708 | { "4kc", 0, 0, ISA_MIPS32, CPU_MIPS32 }, |
19709 | { "4km", 0, 0, ISA_MIPS32, CPU_MIPS32 }, | |
19710 | { "4kp", 0, 0, ISA_MIPS32, CPU_MIPS32 }, | |
19711 | { "4ksc", 0, ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 }, | |
ad3fea08 TS |
19712 | |
19713 | /* MIPS 32 Release 2 */ | |
d16afab6 RS |
19714 | { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19715 | { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19716 | { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19717 | { "4ksd", 0, ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19718 | { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19719 | { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19720 | { "m14k", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19721 | { "m14kc", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19722 | { "m14ke", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU, | |
19723 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19724 | { "m14kec", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU, | |
19725 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19726 | { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19727 | { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19728 | { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19729 | { "24kf1_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 19730 | /* Deprecated forms of the above. */ |
d16afab6 RS |
19731 | { "24kfx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19732 | { "24kx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f | 19733 | /* 24KE is a 24K with DSP ASE, other ASEs are optional. */ |
d16afab6 RS |
19734 | { "24kec", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19735 | { "24kef2_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19736 | { "24kef", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19737 | { "24kef1_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 19738 | /* Deprecated forms of the above. */ |
d16afab6 RS |
19739 | { "24kefx", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19740 | { "24kex", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f | 19741 | /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */ |
d16afab6 RS |
19742 | { "34kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19743 | { "34kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19744 | { "34kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19745 | { "34kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 19746 | /* Deprecated forms of the above. */ |
d16afab6 RS |
19747 | { "34kfx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19748 | { "34kx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
711eefe4 | 19749 | /* 34Kn is a 34kc without DSP. */ |
d16afab6 | 19750 | { "34kn", 0, ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 19751 | /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */ |
d16afab6 RS |
19752 | { "74kc", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19753 | { "74kf2_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19754 | { "74kf", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19755 | { "74kf1_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19756 | { "74kf3_2", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 19757 | /* Deprecated forms of the above. */ |
d16afab6 RS |
19758 | { "74kfx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19759 | { "74kx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
30f8113a | 19760 | /* 1004K cores are multiprocessor versions of the 34K. */ |
d16afab6 RS |
19761 | { "1004kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19762 | { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19763 | { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19764 | { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
77403ce9 RS |
19765 | /* interaptiv is the new name for 1004kf */ |
19766 | { "interaptiv", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
38bf472a MR |
19767 | { "interaptiv-mr2", 0, |
19768 | ASE_DSP | ASE_EVA | ASE_MT | ASE_MIPS16E2 | ASE_MIPS16E2_MT, | |
19769 | ISA_MIPS32R3, CPU_INTERAPTIV_MR2 }, | |
c6e5c03a RS |
19770 | /* M5100 family */ |
19771 | { "m5100", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 }, | |
19772 | { "m5101", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 }, | |
bbaa46c0 | 19773 | /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */ |
134c0c8b | 19774 | { "p5600", 0, ASE_VIRT | ASE_EVA | ASE_XPA, ISA_MIPS32R5, CPU_MIPS32R5 }, |
32b26a03 | 19775 | |
316f5878 | 19776 | /* MIPS 64 */ |
d16afab6 RS |
19777 | { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 }, |
19778 | { "5kf", 0, 0, ISA_MIPS64, CPU_MIPS64 }, | |
19779 | { "20kc", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
19780 | { "25kf", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
ad3fea08 | 19781 | |
c7a23324 | 19782 | /* Broadcom SB-1 CPU core */ |
d16afab6 | 19783 | { "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 }, |
1e85aad8 | 19784 | /* Broadcom SB-1A CPU core */ |
d16afab6 | 19785 | { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 }, |
3739860c | 19786 | |
ed163775 | 19787 | /* MIPS 64 Release 2 */ |
716c08de CX |
19788 | /* Loongson CPU core */ |
19789 | { "loongson3a", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM, ISA_MIPS64R2, | |
19790 | CPU_LOONGSON_3A }, | |
ed163775 | 19791 | |
967344c6 | 19792 | /* Cavium Networks Octeon CPU core */ |
d16afab6 RS |
19793 | { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON }, |
19794 | { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP }, | |
19795 | { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 }, | |
2c629856 | 19796 | { "octeon3", 0, ASE_VIRT | ASE_VIRT64, ISA_MIPS64R5, CPU_OCTEON3 }, |
967344c6 | 19797 | |
52b6b6b9 | 19798 | /* RMI Xlr */ |
d16afab6 | 19799 | { "xlr", 0, 0, ISA_MIPS64, CPU_XLR }, |
52b6b6b9 | 19800 | |
55a36193 MK |
19801 | /* Broadcom XLP. |
19802 | XLP is mostly like XLR, with the prominent exception that it is | |
19803 | MIPS64R2 rather than MIPS64. */ | |
d16afab6 | 19804 | { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR }, |
55a36193 | 19805 | |
a4968f42 | 19806 | /* MIPS 64 Release 6 */ |
7ef0d297 | 19807 | { "i6400", 0, ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6}, |
a4968f42 | 19808 | { "p6600", 0, ASE_VIRT | ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6}, |
7ef0d297 | 19809 | |
316f5878 | 19810 | /* End marker */ |
d16afab6 | 19811 | { NULL, 0, 0, 0, 0 } |
316f5878 | 19812 | }; |
e7af610e | 19813 | |
84ea6cf2 | 19814 | |
316f5878 RS |
19815 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
19816 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 19817 | |
316f5878 | 19818 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 19819 | |
b34976b6 | 19820 | static bfd_boolean |
17a2f251 | 19821 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
19822 | { |
19823 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
19824 | given++, canonical++; | |
19825 | ||
19826 | return ((*given == 0 && *canonical == 0) | |
19827 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
19828 | } | |
19829 | ||
19830 | ||
19831 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
19832 | CPU name. We've traditionally allowed a lot of variation here. | |
19833 | ||
19834 | Note: this function is shared between GCC and GAS. */ | |
19835 | ||
b34976b6 | 19836 | static bfd_boolean |
17a2f251 | 19837 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
19838 | { |
19839 | /* First see if the name matches exactly, or with a final "000" | |
19840 | turned into "k". */ | |
19841 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 19842 | return TRUE; |
316f5878 RS |
19843 | |
19844 | /* If not, try comparing based on numerical designation alone. | |
19845 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
19846 | if (TOLOWER (*given) == 'r') | |
19847 | given++; | |
19848 | if (!ISDIGIT (*given)) | |
b34976b6 | 19849 | return FALSE; |
316f5878 RS |
19850 | |
19851 | /* Skip over some well-known prefixes in the canonical name, | |
19852 | hoping to find a number there too. */ | |
19853 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
19854 | canonical += 2; | |
19855 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
19856 | canonical += 2; | |
19857 | else if (TOLOWER (canonical[0]) == 'r') | |
19858 | canonical += 1; | |
19859 | ||
19860 | return mips_strict_matching_cpu_name_p (canonical, given); | |
19861 | } | |
19862 | ||
19863 | ||
19864 | /* Parse an option that takes the name of a processor as its argument. | |
19865 | OPTION is the name of the option and CPU_STRING is the argument. | |
19866 | Return the corresponding processor enumeration if the CPU_STRING is | |
19867 | recognized, otherwise report an error and return null. | |
19868 | ||
19869 | A similar function exists in GCC. */ | |
e7af610e NC |
19870 | |
19871 | static const struct mips_cpu_info * | |
17a2f251 | 19872 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 19873 | { |
316f5878 | 19874 | const struct mips_cpu_info *p; |
e7af610e | 19875 | |
316f5878 RS |
19876 | /* 'from-abi' selects the most compatible architecture for the given |
19877 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
19878 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
19879 | version. Look first at the -mgp options, if given, otherwise base | |
19880 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 19881 | |
316f5878 RS |
19882 | Treat NO_ABI like the EABIs. One reason to do this is that the |
19883 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
19884 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
19885 | 'mips64', just as we did in the days before 'from-abi'. */ | |
19886 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
19887 | { | |
19888 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
19889 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
19890 | ||
19891 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
19892 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
19893 | ||
bad1aba3 | 19894 | if (file_mips_opts.gp >= 0) |
19895 | return mips_cpu_info_from_isa (file_mips_opts.gp == 32 | |
0b35dfee | 19896 | ? ISA_MIPS1 : ISA_MIPS3); |
316f5878 RS |
19897 | |
19898 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
19899 | ? ISA_MIPS3 | |
19900 | : ISA_MIPS1); | |
19901 | } | |
19902 | ||
19903 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
19904 | if (strcasecmp (cpu_string, "default") == 0) | |
19905 | return 0; | |
19906 | ||
19907 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
19908 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
19909 | return p; | |
19910 | ||
1661c76c | 19911 | as_bad (_("bad value (%s) for %s"), cpu_string, option); |
316f5878 | 19912 | return 0; |
e7af610e NC |
19913 | } |
19914 | ||
316f5878 RS |
19915 | /* Return the canonical processor information for ISA (a member of the |
19916 | ISA_MIPS* enumeration). */ | |
19917 | ||
e7af610e | 19918 | static const struct mips_cpu_info * |
17a2f251 | 19919 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
19920 | { |
19921 | int i; | |
19922 | ||
19923 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
ad3fea08 | 19924 | if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA) |
316f5878 | 19925 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
19926 | return (&mips_cpu_info_table[i]); |
19927 | ||
e972090a | 19928 | return NULL; |
e7af610e | 19929 | } |
fef14a42 TS |
19930 | |
19931 | static const struct mips_cpu_info * | |
17a2f251 | 19932 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
19933 | { |
19934 | int i; | |
19935 | ||
19936 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
19937 | if (arch == mips_cpu_info_table[i].cpu) | |
19938 | return (&mips_cpu_info_table[i]); | |
19939 | ||
19940 | return NULL; | |
19941 | } | |
316f5878 RS |
19942 | \f |
19943 | static void | |
17a2f251 | 19944 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
19945 | { |
19946 | if (*first_p) | |
19947 | { | |
19948 | fprintf (stream, "%24s", ""); | |
19949 | *col_p = 24; | |
19950 | } | |
19951 | else | |
19952 | { | |
19953 | fprintf (stream, ", "); | |
19954 | *col_p += 2; | |
19955 | } | |
e7af610e | 19956 | |
316f5878 RS |
19957 | if (*col_p + strlen (string) > 72) |
19958 | { | |
19959 | fprintf (stream, "\n%24s", ""); | |
19960 | *col_p = 24; | |
19961 | } | |
19962 | ||
19963 | fprintf (stream, "%s", string); | |
19964 | *col_p += strlen (string); | |
19965 | ||
19966 | *first_p = 0; | |
19967 | } | |
19968 | ||
19969 | void | |
17a2f251 | 19970 | md_show_usage (FILE *stream) |
e7af610e | 19971 | { |
316f5878 RS |
19972 | int column, first; |
19973 | size_t i; | |
19974 | ||
19975 | fprintf (stream, _("\ | |
19976 | MIPS options:\n\ | |
316f5878 RS |
19977 | -EB generate big endian output\n\ |
19978 | -EL generate little endian output\n\ | |
19979 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
19980 | -G NUM allow referencing objects up to NUM bytes\n\ | |
19981 | implicitly with the gp register [default 8]\n")); | |
19982 | fprintf (stream, _("\ | |
19983 | -mips1 generate MIPS ISA I instructions\n\ | |
19984 | -mips2 generate MIPS ISA II instructions\n\ | |
19985 | -mips3 generate MIPS ISA III instructions\n\ | |
19986 | -mips4 generate MIPS ISA IV instructions\n\ | |
19987 | -mips5 generate MIPS ISA V instructions\n\ | |
19988 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 19989 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
ae52f483 AB |
19990 | -mips32r3 generate MIPS32 release 3 ISA instructions\n\ |
19991 | -mips32r5 generate MIPS32 release 5 ISA instructions\n\ | |
7361da2c | 19992 | -mips32r6 generate MIPS32 release 6 ISA instructions\n\ |
316f5878 | 19993 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 19994 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
ae52f483 AB |
19995 | -mips64r3 generate MIPS64 release 3 ISA instructions\n\ |
19996 | -mips64r5 generate MIPS64 release 5 ISA instructions\n\ | |
7361da2c | 19997 | -mips64r6 generate MIPS64 release 6 ISA instructions\n\ |
316f5878 RS |
19998 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
19999 | ||
20000 | first = 1; | |
e7af610e NC |
20001 | |
20002 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
20003 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
20004 | show (stream, "from-abi", &column, &first); | |
20005 | fputc ('\n', stream); | |
e7af610e | 20006 | |
316f5878 RS |
20007 | fprintf (stream, _("\ |
20008 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
20009 | -no-mCPU don't generate code specific to CPU.\n\ | |
20010 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
20011 | ||
20012 | first = 1; | |
20013 | ||
20014 | show (stream, "3900", &column, &first); | |
20015 | show (stream, "4010", &column, &first); | |
20016 | show (stream, "4100", &column, &first); | |
20017 | show (stream, "4650", &column, &first); | |
20018 | fputc ('\n', stream); | |
20019 | ||
20020 | fprintf (stream, _("\ | |
20021 | -mips16 generate mips16 instructions\n\ | |
20022 | -no-mips16 do not generate mips16 instructions\n")); | |
20023 | fprintf (stream, _("\ | |
f866b262 MR |
20024 | -mmips16e2 generate MIPS16e2 instructions\n\ |
20025 | -mno-mips16e2 do not generate MIPS16e2 instructions\n")); | |
20026 | fprintf (stream, _("\ | |
df58fc94 RS |
20027 | -mmicromips generate microMIPS instructions\n\ |
20028 | -mno-micromips do not generate microMIPS instructions\n")); | |
20029 | fprintf (stream, _("\ | |
e16bfa71 | 20030 | -msmartmips generate smartmips instructions\n\ |
3739860c | 20031 | -mno-smartmips do not generate smartmips instructions\n")); |
e16bfa71 | 20032 | fprintf (stream, _("\ |
74cd071d CF |
20033 | -mdsp generate DSP instructions\n\ |
20034 | -mno-dsp do not generate DSP instructions\n")); | |
20035 | fprintf (stream, _("\ | |
8b082fb1 TS |
20036 | -mdspr2 generate DSP R2 instructions\n\ |
20037 | -mno-dspr2 do not generate DSP R2 instructions\n")); | |
20038 | fprintf (stream, _("\ | |
8f4f9071 MF |
20039 | -mdspr3 generate DSP R3 instructions\n\ |
20040 | -mno-dspr3 do not generate DSP R3 instructions\n")); | |
20041 | fprintf (stream, _("\ | |
ef2e4d86 CF |
20042 | -mmt generate MT instructions\n\ |
20043 | -mno-mt do not generate MT instructions\n")); | |
20044 | fprintf (stream, _("\ | |
dec0624d MR |
20045 | -mmcu generate MCU instructions\n\ |
20046 | -mno-mcu do not generate MCU instructions\n")); | |
20047 | fprintf (stream, _("\ | |
56d438b1 CF |
20048 | -mmsa generate MSA instructions\n\ |
20049 | -mno-msa do not generate MSA instructions\n")); | |
20050 | fprintf (stream, _("\ | |
7d64c587 AB |
20051 | -mxpa generate eXtended Physical Address (XPA) instructions\n\ |
20052 | -mno-xpa do not generate eXtended Physical Address (XPA) instructions\n")); | |
20053 | fprintf (stream, _("\ | |
b015e599 AP |
20054 | -mvirt generate Virtualization instructions\n\ |
20055 | -mno-virt do not generate Virtualization instructions\n")); | |
20056 | fprintf (stream, _("\ | |
730c3174 SE |
20057 | -mcrc generate CRC instructions\n\ |
20058 | -mno-crc do not generate CRC instructions\n")); | |
20059 | fprintf (stream, _("\ | |
6f20c942 FS |
20060 | -mginv generate Global INValidate (GINV) instructions\n\ |
20061 | -mno-ginv do not generate Global INValidate instructions\n")); | |
20062 | fprintf (stream, _("\ | |
8095d2f7 CX |
20063 | -mloongson-mmi generate Loongson MultiMedia extensions Instructions (MMI) instructions\n\ |
20064 | -mno-loongson-mmi do not generate Loongson MultiMedia extensions Instructions\n")); | |
20065 | fprintf (stream, _("\ | |
716c08de CX |
20066 | -mloongson-cam generate Loongson Content Address Memory (CAM) instructions\n\ |
20067 | -mno-loongson-cam do not generate Loongson Content Address Memory Instructions\n")); | |
20068 | fprintf (stream, _("\ | |
833794fc MR |
20069 | -minsn32 only generate 32-bit microMIPS instructions\n\ |
20070 | -mno-insn32 generate all microMIPS instructions\n")); | |
20071 | fprintf (stream, _("\ | |
c67a084a NC |
20072 | -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\ |
20073 | -mfix-loongson2f-nop work around Loongson2F NOP errata\n\ | |
d766e8ec | 20074 | -mfix-vr4120 work around certain VR4120 errata\n\ |
7d8e00cf | 20075 | -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ |
6a32d874 | 20076 | -mfix-24k insert a nop after ERET and DERET instructions\n\ |
d954098f | 20077 | -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\ |
316f5878 RS |
20078 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
20079 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
aed1a261 | 20080 | -msym32 assume all symbols have 32-bit values\n\ |
092a534f MR |
20081 | -O0 do not remove unneeded NOPs, do not swap branches\n\ |
20082 | -O, -O1 remove unneeded NOPs, do not swap branches\n\ | |
20083 | -O2 remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
20084 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ |
20085 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
037b32b9 AN |
20086 | fprintf (stream, _("\ |
20087 | -mhard-float allow floating-point instructions\n\ | |
20088 | -msoft-float do not allow floating-point instructions\n\ | |
20089 | -msingle-float only allow 32-bit floating-point operations\n\ | |
20090 | -mdouble-float allow 32-bit and 64-bit floating-point operations\n\ | |
3bf0dbfb | 20091 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ |
ba92f887 | 20092 | --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\ |
8b10b0b3 MR |
20093 | -mignore-branch-isa accept invalid branches requiring an ISA mode switch\n\ |
20094 | -mno-ignore-branch-isa reject invalid branches requiring an ISA mode switch\n\ | |
ba92f887 MR |
20095 | -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n")); |
20096 | ||
20097 | first = 1; | |
20098 | ||
20099 | show (stream, "legacy", &column, &first); | |
20100 | show (stream, "2008", &column, &first); | |
20101 | ||
20102 | fputc ('\n', stream); | |
20103 | ||
316f5878 RS |
20104 | fprintf (stream, _("\ |
20105 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
861fb55a | 20106 | -call_nonpic generate non-PIC code that can operate with DSOs\n\ |
0c000745 | 20107 | -mvxworks-pic generate VxWorks position independent code\n\ |
861fb55a | 20108 | -non_shared do not generate code that can operate with DSOs\n\ |
316f5878 | 20109 | -xgot assume a 32 bit GOT\n\ |
dcd410fe | 20110 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
bbe506e8 | 20111 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
d821e36b | 20112 | position dependent (non shared) code\n\ |
316f5878 RS |
20113 | -mabi=ABI create ABI conformant object file for:\n")); |
20114 | ||
20115 | first = 1; | |
20116 | ||
20117 | show (stream, "32", &column, &first); | |
20118 | show (stream, "o64", &column, &first); | |
20119 | show (stream, "n32", &column, &first); | |
20120 | show (stream, "64", &column, &first); | |
20121 | show (stream, "eabi", &column, &first); | |
20122 | ||
20123 | fputc ('\n', stream); | |
20124 | ||
20125 | fprintf (stream, _("\ | |
b4f6242e MR |
20126 | -32 create o32 ABI object file%s\n"), |
20127 | MIPS_DEFAULT_ABI == O32_ABI ? _(" (default)") : ""); | |
20128 | fprintf (stream, _("\ | |
20129 | -n32 create n32 ABI object file%s\n"), | |
20130 | MIPS_DEFAULT_ABI == N32_ABI ? _(" (default)") : ""); | |
20131 | fprintf (stream, _("\ | |
20132 | -64 create 64 ABI object file%s\n"), | |
20133 | MIPS_DEFAULT_ABI == N64_ABI ? _(" (default)") : ""); | |
e7af610e | 20134 | } |
14e777e0 | 20135 | |
1575952e | 20136 | #ifdef TE_IRIX |
14e777e0 | 20137 | enum dwarf2_format |
413a266c | 20138 | mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED) |
14e777e0 | 20139 | { |
369943fe | 20140 | if (HAVE_64BIT_SYMBOLS) |
1575952e | 20141 | return dwarf2_format_64bit_irix; |
14e777e0 KB |
20142 | else |
20143 | return dwarf2_format_32bit; | |
20144 | } | |
1575952e | 20145 | #endif |
73369e65 EC |
20146 | |
20147 | int | |
20148 | mips_dwarf2_addr_size (void) | |
20149 | { | |
6b6b3450 | 20150 | if (HAVE_64BIT_OBJECTS) |
73369e65 | 20151 | return 8; |
73369e65 EC |
20152 | else |
20153 | return 4; | |
20154 | } | |
5862107c EC |
20155 | |
20156 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
20157 | void | |
20158 | mips_cfi_frame_initial_instructions (void) | |
20159 | { | |
20160 | cfi_add_CFA_def_cfa_register (SP); | |
20161 | } | |
20162 | ||
707bfff6 TS |
20163 | int |
20164 | tc_mips_regname_to_dw2regnum (char *regname) | |
20165 | { | |
20166 | unsigned int regnum = -1; | |
20167 | unsigned int reg; | |
20168 | ||
20169 | if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®)) | |
20170 | regnum = reg; | |
20171 | ||
20172 | return regnum; | |
20173 | } | |
263b2574 | 20174 | |
20175 | /* Implement CONVERT_SYMBOLIC_ATTRIBUTE. | |
20176 | Given a symbolic attribute NAME, return the proper integer value. | |
20177 | Returns -1 if the attribute is not known. */ | |
20178 | ||
20179 | int | |
20180 | mips_convert_symbolic_attribute (const char *name) | |
20181 | { | |
20182 | static const struct | |
20183 | { | |
20184 | const char * name; | |
20185 | const int tag; | |
20186 | } | |
20187 | attribute_table[] = | |
20188 | { | |
20189 | #define T(tag) {#tag, tag} | |
20190 | T (Tag_GNU_MIPS_ABI_FP), | |
20191 | T (Tag_GNU_MIPS_ABI_MSA), | |
20192 | #undef T | |
20193 | }; | |
20194 | unsigned int i; | |
20195 | ||
20196 | if (name == NULL) | |
20197 | return -1; | |
20198 | ||
20199 | for (i = 0; i < ARRAY_SIZE (attribute_table); i++) | |
20200 | if (streq (name, attribute_table[i].name)) | |
20201 | return attribute_table[i].tag; | |
20202 | ||
20203 | return -1; | |
20204 | } | |
fd5c94ab RS |
20205 | |
20206 | void | |
20207 | md_mips_end (void) | |
20208 | { | |
351cdf24 MF |
20209 | int fpabi = Val_GNU_MIPS_ABI_FP_ANY; |
20210 | ||
fd5c94ab RS |
20211 | mips_emit_delays (); |
20212 | if (cur_proc_ptr) | |
20213 | as_warn (_("missing .end at end of assembly")); | |
919731af | 20214 | |
20215 | /* Just in case no code was emitted, do the consistency check. */ | |
20216 | file_mips_check_options (); | |
351cdf24 MF |
20217 | |
20218 | /* Set a floating-point ABI if the user did not. */ | |
20219 | if (obj_elf_seen_attribute (OBJ_ATTR_GNU, Tag_GNU_MIPS_ABI_FP)) | |
20220 | { | |
20221 | /* Perform consistency checks on the floating-point ABI. */ | |
20222 | fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, | |
20223 | Tag_GNU_MIPS_ABI_FP); | |
20224 | if (fpabi != Val_GNU_MIPS_ABI_FP_ANY) | |
20225 | check_fpabi (fpabi); | |
20226 | } | |
20227 | else | |
20228 | { | |
20229 | /* Soft-float gets precedence over single-float, the two options should | |
20230 | not be used together so this should not matter. */ | |
20231 | if (file_mips_opts.soft_float == 1) | |
20232 | fpabi = Val_GNU_MIPS_ABI_FP_SOFT; | |
20233 | /* Single-float gets precedence over all double_float cases. */ | |
20234 | else if (file_mips_opts.single_float == 1) | |
20235 | fpabi = Val_GNU_MIPS_ABI_FP_SINGLE; | |
20236 | else | |
20237 | { | |
20238 | switch (file_mips_opts.fp) | |
20239 | { | |
20240 | case 32: | |
20241 | if (file_mips_opts.gp == 32) | |
20242 | fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE; | |
20243 | break; | |
20244 | case 0: | |
20245 | fpabi = Val_GNU_MIPS_ABI_FP_XX; | |
20246 | break; | |
20247 | case 64: | |
20248 | if (file_mips_opts.gp == 32 && !file_mips_opts.oddspreg) | |
20249 | fpabi = Val_GNU_MIPS_ABI_FP_64A; | |
20250 | else if (file_mips_opts.gp == 32) | |
20251 | fpabi = Val_GNU_MIPS_ABI_FP_64; | |
20252 | else | |
20253 | fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE; | |
20254 | break; | |
20255 | } | |
20256 | } | |
20257 | ||
20258 | bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, | |
20259 | Tag_GNU_MIPS_ABI_FP, fpabi); | |
20260 | } | |
fd5c94ab | 20261 | } |
2f0c68f2 CM |
20262 | |
20263 | /* Returns the relocation type required for a particular CFI encoding. */ | |
20264 | ||
20265 | bfd_reloc_code_real_type | |
20266 | mips_cfi_reloc_for_encoding (int encoding) | |
20267 | { | |
20268 | if (encoding == (DW_EH_PE_sdata4 | DW_EH_PE_pcrel)) | |
20269 | return BFD_RELOC_32_PCREL; | |
20270 | else return BFD_RELOC_NONE; | |
20271 | } |