Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
81912461 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
e407c74b | 3 | 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013 |
c67a084a | 4 | Free Software Foundation, Inc. |
252b5132 RH |
5 | Contributed by the OSF and Ralph Campbell. |
6 | Written by Keith Knowles and Ralph Campbell, working independently. | |
7 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
8 | Support. | |
9 | ||
10 | This file is part of GAS. | |
11 | ||
12 | GAS is free software; you can redistribute it and/or modify | |
13 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 14 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
15 | any later version. |
16 | ||
17 | GAS is distributed in the hope that it will be useful, | |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
21 | ||
22 | You should have received a copy of the GNU General Public License | |
23 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
24 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
25 | 02110-1301, USA. */ | |
252b5132 RH |
26 | |
27 | #include "as.h" | |
28 | #include "config.h" | |
29 | #include "subsegs.h" | |
3882b010 | 30 | #include "safe-ctype.h" |
252b5132 | 31 | |
252b5132 RH |
32 | #include "opcode/mips.h" |
33 | #include "itbl-ops.h" | |
c5dd6aab | 34 | #include "dwarf2dbg.h" |
5862107c | 35 | #include "dw2gencfi.h" |
252b5132 | 36 | |
42429eac RS |
37 | /* Check assumptions made in this file. */ |
38 | typedef char static_assert1[sizeof (offsetT) < 8 ? -1 : 1]; | |
39 | typedef char static_assert2[sizeof (valueT) < 8 ? -1 : 1]; | |
40 | ||
252b5132 RH |
41 | #ifdef DEBUG |
42 | #define DBG(x) printf x | |
43 | #else | |
44 | #define DBG(x) | |
45 | #endif | |
46 | ||
252b5132 | 47 | /* Clean up namespace so we can include obj-elf.h too. */ |
17a2f251 TS |
48 | static int mips_output_flavor (void); |
49 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
50 | #undef OBJ_PROCESS_STAB |
51 | #undef OUTPUT_FLAVOR | |
52 | #undef S_GET_ALIGN | |
53 | #undef S_GET_SIZE | |
54 | #undef S_SET_ALIGN | |
55 | #undef S_SET_SIZE | |
252b5132 RH |
56 | #undef obj_frob_file |
57 | #undef obj_frob_file_after_relocs | |
58 | #undef obj_frob_symbol | |
59 | #undef obj_pop_insert | |
60 | #undef obj_sec_sym_ok_for_reloc | |
61 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
62 | ||
63 | #include "obj-elf.h" | |
64 | /* Fix any of them that we actually care about. */ | |
65 | #undef OUTPUT_FLAVOR | |
66 | #define OUTPUT_FLAVOR mips_output_flavor() | |
252b5132 | 67 | |
252b5132 | 68 | #include "elf/mips.h" |
252b5132 RH |
69 | |
70 | #ifndef ECOFF_DEBUGGING | |
71 | #define NO_ECOFF_DEBUGGING | |
72 | #define ECOFF_DEBUGGING 0 | |
73 | #endif | |
74 | ||
ecb4347a DJ |
75 | int mips_flag_mdebug = -1; |
76 | ||
dcd410fe RO |
77 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
78 | linker doesn't know about and discards them, but relocations against them | |
79 | remain, leading to rld crashes. */ | |
80 | #ifdef TE_IRIX | |
81 | int mips_flag_pdr = FALSE; | |
82 | #else | |
83 | int mips_flag_pdr = TRUE; | |
84 | #endif | |
85 | ||
252b5132 RH |
86 | #include "ecoff.h" |
87 | ||
252b5132 | 88 | static char *mips_regmask_frag; |
252b5132 | 89 | |
85b51719 | 90 | #define ZERO 0 |
741fe287 | 91 | #define ATREG 1 |
df58fc94 RS |
92 | #define S0 16 |
93 | #define S7 23 | |
252b5132 RH |
94 | #define TREG 24 |
95 | #define PIC_CALL_REG 25 | |
96 | #define KT0 26 | |
97 | #define KT1 27 | |
98 | #define GP 28 | |
99 | #define SP 29 | |
100 | #define FP 30 | |
101 | #define RA 31 | |
102 | ||
103 | #define ILLEGAL_REG (32) | |
104 | ||
741fe287 MR |
105 | #define AT mips_opts.at |
106 | ||
252b5132 RH |
107 | extern int target_big_endian; |
108 | ||
252b5132 | 109 | /* The name of the readonly data section. */ |
e8044f35 | 110 | #define RDATA_SECTION_NAME ".rodata" |
252b5132 | 111 | |
a4e06468 RS |
112 | /* Ways in which an instruction can be "appended" to the output. */ |
113 | enum append_method { | |
114 | /* Just add it normally. */ | |
115 | APPEND_ADD, | |
116 | ||
117 | /* Add it normally and then add a nop. */ | |
118 | APPEND_ADD_WITH_NOP, | |
119 | ||
120 | /* Turn an instruction with a delay slot into a "compact" version. */ | |
121 | APPEND_ADD_COMPACT, | |
122 | ||
123 | /* Insert the instruction before the last one. */ | |
124 | APPEND_SWAP | |
125 | }; | |
126 | ||
47e39b9d RS |
127 | /* Information about an instruction, including its format, operands |
128 | and fixups. */ | |
129 | struct mips_cl_insn | |
130 | { | |
131 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ | |
132 | const struct mips_opcode *insn_mo; | |
133 | ||
47e39b9d | 134 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is |
5c04167a RS |
135 | a copy of INSN_MO->match with the operands filled in. If we have |
136 | decided to use an extended MIPS16 instruction, this includes the | |
137 | extension. */ | |
47e39b9d RS |
138 | unsigned long insn_opcode; |
139 | ||
140 | /* The frag that contains the instruction. */ | |
141 | struct frag *frag; | |
142 | ||
143 | /* The offset into FRAG of the first instruction byte. */ | |
144 | long where; | |
145 | ||
146 | /* The relocs associated with the instruction, if any. */ | |
147 | fixS *fixp[3]; | |
148 | ||
a38419a5 RS |
149 | /* True if this entry cannot be moved from its current position. */ |
150 | unsigned int fixed_p : 1; | |
47e39b9d | 151 | |
708587a4 | 152 | /* True if this instruction occurred in a .set noreorder block. */ |
47e39b9d RS |
153 | unsigned int noreorder_p : 1; |
154 | ||
2fa15973 RS |
155 | /* True for mips16 instructions that jump to an absolute address. */ |
156 | unsigned int mips16_absolute_jump_p : 1; | |
15be625d CM |
157 | |
158 | /* True if this instruction is complete. */ | |
159 | unsigned int complete_p : 1; | |
e407c74b NC |
160 | |
161 | /* True if this instruction is cleared from history by unconditional | |
162 | branch. */ | |
163 | unsigned int cleared_p : 1; | |
47e39b9d RS |
164 | }; |
165 | ||
a325df1d TS |
166 | /* The ABI to use. */ |
167 | enum mips_abi_level | |
168 | { | |
169 | NO_ABI = 0, | |
170 | O32_ABI, | |
171 | O64_ABI, | |
172 | N32_ABI, | |
173 | N64_ABI, | |
174 | EABI_ABI | |
175 | }; | |
176 | ||
177 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 178 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 179 | |
143d77c5 EC |
180 | /* Whether or not we have code that can call pic code. */ |
181 | int mips_abicalls = FALSE; | |
182 | ||
aa6975fb ILT |
183 | /* Whether or not we have code which can be put into a shared |
184 | library. */ | |
185 | static bfd_boolean mips_in_shared = TRUE; | |
186 | ||
252b5132 RH |
187 | /* This is the set of options which may be modified by the .set |
188 | pseudo-op. We use a struct so that .set push and .set pop are more | |
189 | reliable. */ | |
190 | ||
e972090a NC |
191 | struct mips_set_options |
192 | { | |
252b5132 RH |
193 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
194 | if it has not been initialized. Changed by `.set mipsN', and the | |
195 | -mipsN command line option, and the default CPU. */ | |
196 | int isa; | |
846ef2d0 RS |
197 | /* Enabled Application Specific Extensions (ASEs). Changed by `.set |
198 | <asename>', by command line options, and based on the default | |
199 | architecture. */ | |
200 | int ase; | |
252b5132 RH |
201 | /* Whether we are assembling for the mips16 processor. 0 if we are |
202 | not, 1 if we are, and -1 if the value has not been initialized. | |
203 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
204 | -nomips16 command line options, and the default CPU. */ | |
205 | int mips16; | |
df58fc94 RS |
206 | /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not, |
207 | 1 if we are, and -1 if the value has not been initialized. Changed | |
208 | by `.set micromips' and `.set nomicromips', and the -mmicromips | |
209 | and -mno-micromips command line options, and the default CPU. */ | |
210 | int micromips; | |
252b5132 RH |
211 | /* Non-zero if we should not reorder instructions. Changed by `.set |
212 | reorder' and `.set noreorder'. */ | |
213 | int noreorder; | |
741fe287 MR |
214 | /* Non-zero if we should not permit the register designated "assembler |
215 | temporary" to be used in instructions. The value is the register | |
216 | number, normally $at ($1). Changed by `.set at=REG', `.set noat' | |
217 | (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */ | |
218 | unsigned int at; | |
252b5132 RH |
219 | /* Non-zero if we should warn when a macro instruction expands into |
220 | more than one machine instruction. Changed by `.set nomacro' and | |
221 | `.set macro'. */ | |
222 | int warn_about_macros; | |
223 | /* Non-zero if we should not move instructions. Changed by `.set | |
224 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
225 | int nomove; | |
226 | /* Non-zero if we should not optimize branches by moving the target | |
227 | of the branch into the delay slot. Actually, we don't perform | |
228 | this optimization anyhow. Changed by `.set bopt' and `.set | |
229 | nobopt'. */ | |
230 | int nobopt; | |
231 | /* Non-zero if we should not autoextend mips16 instructions. | |
232 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
233 | int noautoextend; | |
833794fc MR |
234 | /* True if we should only emit 32-bit microMIPS instructions. |
235 | Changed by `.set insn32' and `.set noinsn32', and the -minsn32 | |
236 | and -mno-insn32 command line options. */ | |
237 | bfd_boolean insn32; | |
a325df1d TS |
238 | /* Restrict general purpose registers and floating point registers |
239 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
240 | is passed but can changed if the assembler code uses .set mipsN. */ | |
241 | int gp32; | |
242 | int fp32; | |
fef14a42 TS |
243 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
244 | command line option, and the default CPU. */ | |
245 | int arch; | |
aed1a261 RS |
246 | /* True if ".set sym32" is in effect. */ |
247 | bfd_boolean sym32; | |
037b32b9 AN |
248 | /* True if floating-point operations are not allowed. Changed by .set |
249 | softfloat or .set hardfloat, by command line options -msoft-float or | |
250 | -mhard-float. The default is false. */ | |
251 | bfd_boolean soft_float; | |
252 | ||
253 | /* True if only single-precision floating-point operations are allowed. | |
254 | Changed by .set singlefloat or .set doublefloat, command-line options | |
255 | -msingle-float or -mdouble-float. The default is false. */ | |
256 | bfd_boolean single_float; | |
252b5132 RH |
257 | }; |
258 | ||
037b32b9 AN |
259 | /* This is the struct we use to hold the current set of options. Note |
260 | that we must set the isa field to ISA_UNKNOWN and the ASE fields to | |
261 | -1 to indicate that they have not been initialized. */ | |
262 | ||
a325df1d | 263 | /* True if -mgp32 was passed. */ |
a8e8e863 | 264 | static int file_mips_gp32 = -1; |
a325df1d TS |
265 | |
266 | /* True if -mfp32 was passed. */ | |
a8e8e863 | 267 | static int file_mips_fp32 = -1; |
a325df1d | 268 | |
037b32b9 AN |
269 | /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */ |
270 | static int file_mips_soft_float = 0; | |
271 | ||
272 | /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */ | |
273 | static int file_mips_single_float = 0; | |
252b5132 | 274 | |
ba92f887 MR |
275 | /* True if -mnan=2008, false if -mnan=legacy. */ |
276 | static bfd_boolean mips_flag_nan2008 = FALSE; | |
277 | ||
e972090a NC |
278 | static struct mips_set_options mips_opts = |
279 | { | |
846ef2d0 | 280 | /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1, |
b015e599 | 281 | /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0, |
833794fc MR |
282 | /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE, |
283 | /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE, | |
b015e599 | 284 | /* soft_float */ FALSE, /* single_float */ FALSE |
e7af610e | 285 | }; |
252b5132 | 286 | |
846ef2d0 RS |
287 | /* The set of ASEs that were selected on the command line, either |
288 | explicitly via ASE options or implicitly through things like -march. */ | |
289 | static unsigned int file_ase; | |
290 | ||
291 | /* Which bits of file_ase were explicitly set or cleared by ASE options. */ | |
292 | static unsigned int file_ase_explicit; | |
293 | ||
252b5132 RH |
294 | /* These variables are filled in with the masks of registers used. |
295 | The object format code reads them and puts them in the appropriate | |
296 | place. */ | |
297 | unsigned long mips_gprmask; | |
298 | unsigned long mips_cprmask[4]; | |
299 | ||
300 | /* MIPS ISA we are using for this output file. */ | |
e7af610e | 301 | static int file_mips_isa = ISA_UNKNOWN; |
252b5132 | 302 | |
738f4d98 | 303 | /* True if any MIPS16 code was produced. */ |
a4672219 TS |
304 | static int file_ase_mips16; |
305 | ||
3994f87e TS |
306 | #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \ |
307 | || mips_opts.isa == ISA_MIPS32R2 \ | |
308 | || mips_opts.isa == ISA_MIPS64 \ | |
309 | || mips_opts.isa == ISA_MIPS64R2) | |
310 | ||
df58fc94 RS |
311 | /* True if any microMIPS code was produced. */ |
312 | static int file_ase_micromips; | |
313 | ||
b12dd2e4 CF |
314 | /* True if we want to create R_MIPS_JALR for jalr $25. */ |
315 | #ifdef TE_IRIX | |
1180b5a4 | 316 | #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI |
b12dd2e4 | 317 | #else |
1180b5a4 RS |
318 | /* As a GNU extension, we use R_MIPS_JALR for o32 too. However, |
319 | because there's no place for any addend, the only acceptable | |
320 | expression is a bare symbol. */ | |
321 | #define MIPS_JALR_HINT_P(EXPR) \ | |
322 | (!HAVE_IN_PLACE_ADDENDS \ | |
323 | || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0)) | |
b12dd2e4 CF |
324 | #endif |
325 | ||
ec68c924 | 326 | /* The argument of the -march= flag. The architecture we are assembling. */ |
fef14a42 | 327 | static int file_mips_arch = CPU_UNKNOWN; |
316f5878 | 328 | static const char *mips_arch_string; |
ec68c924 EC |
329 | |
330 | /* The argument of the -mtune= flag. The architecture for which we | |
331 | are optimizing. */ | |
332 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 333 | static const char *mips_tune_string; |
ec68c924 | 334 | |
316f5878 | 335 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
336 | static int mips_32bitmode = 0; |
337 | ||
316f5878 RS |
338 | /* True if the given ABI requires 32-bit registers. */ |
339 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
340 | ||
341 | /* Likewise 64-bit registers. */ | |
707bfff6 TS |
342 | #define ABI_NEEDS_64BIT_REGS(ABI) \ |
343 | ((ABI) == N32_ABI \ | |
344 | || (ABI) == N64_ABI \ | |
316f5878 RS |
345 | || (ABI) == O64_ABI) |
346 | ||
ad3fea08 | 347 | /* Return true if ISA supports 64 bit wide gp registers. */ |
707bfff6 TS |
348 | #define ISA_HAS_64BIT_REGS(ISA) \ |
349 | ((ISA) == ISA_MIPS3 \ | |
350 | || (ISA) == ISA_MIPS4 \ | |
351 | || (ISA) == ISA_MIPS5 \ | |
352 | || (ISA) == ISA_MIPS64 \ | |
353 | || (ISA) == ISA_MIPS64R2) | |
9ce8a5dd | 354 | |
ad3fea08 TS |
355 | /* Return true if ISA supports 64 bit wide float registers. */ |
356 | #define ISA_HAS_64BIT_FPRS(ISA) \ | |
357 | ((ISA) == ISA_MIPS3 \ | |
358 | || (ISA) == ISA_MIPS4 \ | |
359 | || (ISA) == ISA_MIPS5 \ | |
360 | || (ISA) == ISA_MIPS32R2 \ | |
361 | || (ISA) == ISA_MIPS64 \ | |
362 | || (ISA) == ISA_MIPS64R2) | |
363 | ||
af7ee8bf CD |
364 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
365 | instructions. */ | |
707bfff6 | 366 | #define ISA_HAS_DROR(ISA) \ |
df58fc94 RS |
367 | ((ISA) == ISA_MIPS64R2 \ |
368 | || (mips_opts.micromips \ | |
369 | && ISA_HAS_64BIT_REGS (ISA)) \ | |
370 | ) | |
af7ee8bf CD |
371 | |
372 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
373 | instructions. */ | |
707bfff6 TS |
374 | #define ISA_HAS_ROR(ISA) \ |
375 | ((ISA) == ISA_MIPS32R2 \ | |
376 | || (ISA) == ISA_MIPS64R2 \ | |
846ef2d0 | 377 | || (mips_opts.ase & ASE_SMARTMIPS) \ |
df58fc94 RS |
378 | || mips_opts.micromips \ |
379 | ) | |
707bfff6 | 380 | |
7455baf8 TS |
381 | /* Return true if ISA supports single-precision floats in odd registers. */ |
382 | #define ISA_HAS_ODD_SINGLE_FPR(ISA) \ | |
383 | ((ISA) == ISA_MIPS32 \ | |
384 | || (ISA) == ISA_MIPS32R2 \ | |
385 | || (ISA) == ISA_MIPS64 \ | |
386 | || (ISA) == ISA_MIPS64R2) | |
af7ee8bf | 387 | |
ad3fea08 TS |
388 | /* Return true if ISA supports move to/from high part of a 64-bit |
389 | floating-point register. */ | |
390 | #define ISA_HAS_MXHC1(ISA) \ | |
391 | ((ISA) == ISA_MIPS32R2 \ | |
392 | || (ISA) == ISA_MIPS64R2) | |
393 | ||
e013f690 | 394 | #define HAVE_32BIT_GPRS \ |
ad3fea08 | 395 | (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa)) |
ca4e0257 | 396 | |
e013f690 | 397 | #define HAVE_32BIT_FPRS \ |
ad3fea08 | 398 | (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa)) |
ca4e0257 | 399 | |
ad3fea08 TS |
400 | #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS) |
401 | #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS) | |
ca4e0257 | 402 | |
316f5878 | 403 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 404 | |
316f5878 | 405 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 406 | |
3b91255e RS |
407 | /* True if relocations are stored in-place. */ |
408 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
409 | ||
aed1a261 RS |
410 | /* The ABI-derived address size. */ |
411 | #define HAVE_64BIT_ADDRESSES \ | |
412 | (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) | |
413 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) | |
e013f690 | 414 | |
aed1a261 RS |
415 | /* The size of symbolic constants (i.e., expressions of the form |
416 | "SYMBOL" or "SYMBOL + OFFSET"). */ | |
417 | #define HAVE_32BIT_SYMBOLS \ | |
418 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) | |
419 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) | |
ca4e0257 | 420 | |
b7c7d6c1 TS |
421 | /* Addresses are loaded in different ways, depending on the address size |
422 | in use. The n32 ABI Documentation also mandates the use of additions | |
423 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 424 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 425 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
426 | |
427 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 428 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
429 | |
430 | #define ADDRESS_LOAD_INSN \ | |
431 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
432 | ||
433 | #define ADDRESS_STORE_INSN \ | |
434 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
435 | ||
a4672219 | 436 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
437 | #define CPU_HAS_MIPS16(cpu) \ |
438 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
439 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 440 | |
2309ddf2 | 441 | /* Return true if the given CPU supports the microMIPS ASE. */ |
df58fc94 RS |
442 | #define CPU_HAS_MICROMIPS(cpu) 0 |
443 | ||
60b63b72 RS |
444 | /* True if CPU has a dror instruction. */ |
445 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
446 | ||
447 | /* True if CPU has a ror instruction. */ | |
448 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
449 | ||
dd6a37e7 | 450 | /* True if CPU is in the Octeon family */ |
432233b3 | 451 | #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP || (CPU) == CPU_OCTEON2) |
dd6a37e7 | 452 | |
dd3cbb7e | 453 | /* True if CPU has seq/sne and seqi/snei instructions. */ |
dd6a37e7 | 454 | #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU)) |
dd3cbb7e | 455 | |
0aa27725 RS |
456 | /* True, if CPU has support for ldc1 and sdc1. */ |
457 | #define CPU_HAS_LDC1_SDC1(CPU) \ | |
458 | ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900)) | |
459 | ||
c8978940 CD |
460 | /* True if mflo and mfhi can be immediately followed by instructions |
461 | which write to the HI and LO registers. | |
462 | ||
463 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
464 | (at least) two instructions between the reads of HI/LO and | |
465 | instructions which write them, and later ISAs do not. Contradicting | |
466 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
467 | the UM for the NEC Vr5000) document needing the instructions between | |
468 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
469 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
470 | earlier-ISA CPUs for which CPU documentation declares that the | |
471 | instructions are really interlocked. */ | |
472 | #define hilo_interlocks \ | |
473 | (mips_opts.isa == ISA_MIPS32 \ | |
474 | || mips_opts.isa == ISA_MIPS32R2 \ | |
475 | || mips_opts.isa == ISA_MIPS64 \ | |
476 | || mips_opts.isa == ISA_MIPS64R2 \ | |
477 | || mips_opts.arch == CPU_R4010 \ | |
e407c74b | 478 | || mips_opts.arch == CPU_R5900 \ |
c8978940 CD |
479 | || mips_opts.arch == CPU_R10000 \ |
480 | || mips_opts.arch == CPU_R12000 \ | |
3aa3176b TS |
481 | || mips_opts.arch == CPU_R14000 \ |
482 | || mips_opts.arch == CPU_R16000 \ | |
c8978940 | 483 | || mips_opts.arch == CPU_RM7000 \ |
c8978940 | 484 | || mips_opts.arch == CPU_VR5500 \ |
df58fc94 | 485 | || mips_opts.micromips \ |
c8978940 | 486 | ) |
252b5132 RH |
487 | |
488 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
489 | from the GPRs after they are loaded from memory, and thus does not |
490 | require nops to be inserted. This applies to instructions marked | |
491 | INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA | |
df58fc94 RS |
492 | level I and microMIPS mode instructions are always interlocked. */ |
493 | #define gpr_interlocks \ | |
494 | (mips_opts.isa != ISA_MIPS1 \ | |
495 | || mips_opts.arch == CPU_R3900 \ | |
e407c74b | 496 | || mips_opts.arch == CPU_R5900 \ |
df58fc94 RS |
497 | || mips_opts.micromips \ |
498 | ) | |
252b5132 | 499 | |
81912461 ILT |
500 | /* Whether the processor uses hardware interlocks to avoid delays |
501 | required by coprocessor instructions, and thus does not require | |
502 | nops to be inserted. This applies to instructions marked | |
503 | INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays | |
504 | between instructions marked INSN_WRITE_COND_CODE and ones marked | |
505 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA | |
df58fc94 RS |
506 | levels I, II, and III and microMIPS mode instructions are always |
507 | interlocked. */ | |
bdaaa2e1 | 508 | /* Itbl support may require additional care here. */ |
81912461 ILT |
509 | #define cop_interlocks \ |
510 | ((mips_opts.isa != ISA_MIPS1 \ | |
511 | && mips_opts.isa != ISA_MIPS2 \ | |
512 | && mips_opts.isa != ISA_MIPS3) \ | |
513 | || mips_opts.arch == CPU_R4300 \ | |
df58fc94 | 514 | || mips_opts.micromips \ |
81912461 ILT |
515 | ) |
516 | ||
517 | /* Whether the processor uses hardware interlocks to protect reads | |
518 | from coprocessor registers after they are loaded from memory, and | |
519 | thus does not require nops to be inserted. This applies to | |
520 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
df58fc94 RS |
521 | requires at MIPS ISA level I and microMIPS mode instructions are |
522 | always interlocked. */ | |
523 | #define cop_mem_interlocks \ | |
524 | (mips_opts.isa != ISA_MIPS1 \ | |
525 | || mips_opts.micromips \ | |
526 | ) | |
252b5132 | 527 | |
6b76fefe CM |
528 | /* Is this a mfhi or mflo instruction? */ |
529 | #define MF_HILO_INSN(PINFO) \ | |
b19e8a9b AN |
530 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) |
531 | ||
df58fc94 RS |
532 | /* Whether code compression (either of the MIPS16 or the microMIPS ASEs) |
533 | has been selected. This implies, in particular, that addresses of text | |
534 | labels have their LSB set. */ | |
535 | #define HAVE_CODE_COMPRESSION \ | |
536 | ((mips_opts.mips16 | mips_opts.micromips) != 0) | |
537 | ||
42429eac RS |
538 | /* The minimum and maximum signed values that can be stored in a GPR. */ |
539 | #define GPR_SMAX ((offsetT) (((valueT) 1 << (HAVE_64BIT_GPRS ? 63 : 31)) - 1)) | |
540 | #define GPR_SMIN (-GPR_SMAX - 1) | |
541 | ||
252b5132 RH |
542 | /* MIPS PIC level. */ |
543 | ||
a161fe53 | 544 | enum mips_pic_level mips_pic; |
252b5132 | 545 | |
c9914766 | 546 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 547 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 548 | static int mips_big_got = 0; |
252b5132 RH |
549 | |
550 | /* 1 if trap instructions should used for overflow rather than break | |
551 | instructions. */ | |
c9914766 | 552 | static int mips_trap = 0; |
252b5132 | 553 | |
119d663a | 554 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 555 | by assembling two single width halves into two single width floating |
119d663a NC |
556 | point registers which just happen to alias the double width destination |
557 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 558 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
559 | automatically at assemble time. */ |
560 | static int mips_disable_float_construction; | |
561 | ||
252b5132 RH |
562 | /* Non-zero if any .set noreorder directives were used. */ |
563 | ||
564 | static int mips_any_noreorder; | |
565 | ||
6b76fefe CM |
566 | /* Non-zero if nops should be inserted when the register referenced in |
567 | an mfhi/mflo instruction is read in the next two instructions. */ | |
568 | static int mips_7000_hilo_fix; | |
569 | ||
02ffd3e4 | 570 | /* The size of objects in the small data section. */ |
156c2f8b | 571 | static unsigned int g_switch_value = 8; |
252b5132 RH |
572 | /* Whether the -G option was used. */ |
573 | static int g_switch_seen = 0; | |
574 | ||
575 | #define N_RMASK 0xc4 | |
576 | #define N_VFP 0xd4 | |
577 | ||
578 | /* If we can determine in advance that GP optimization won't be | |
579 | possible, we can skip the relaxation stuff that tries to produce | |
580 | GP-relative references. This makes delay slot optimization work | |
581 | better. | |
582 | ||
583 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
584 | gcc output. It needs to guess right for gcc, otherwise gcc |
585 | will put what it thinks is a GP-relative instruction in a branch | |
586 | delay slot. | |
252b5132 RH |
587 | |
588 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
589 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 590 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
591 | |
592 | /* handle of the OPCODE hash table */ | |
593 | static struct hash_control *op_hash = NULL; | |
594 | ||
595 | /* The opcode hash table we use for the mips16. */ | |
596 | static struct hash_control *mips16_op_hash = NULL; | |
597 | ||
df58fc94 RS |
598 | /* The opcode hash table we use for the microMIPS ASE. */ |
599 | static struct hash_control *micromips_op_hash = NULL; | |
600 | ||
252b5132 RH |
601 | /* This array holds the chars that always start a comment. If the |
602 | pre-processor is disabled, these aren't very useful */ | |
603 | const char comment_chars[] = "#"; | |
604 | ||
605 | /* This array holds the chars that only start a comment at the beginning of | |
606 | a line. If the line seems to have the form '# 123 filename' | |
607 | .line and .file directives will appear in the pre-processed output */ | |
608 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
609 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 610 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
611 | /* Also note that C style comments are always supported. */ |
612 | const char line_comment_chars[] = "#"; | |
613 | ||
bdaaa2e1 | 614 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 615 | const char line_separator_chars[] = ";"; |
252b5132 RH |
616 | |
617 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
618 | const char EXP_CHARS[] = "eE"; | |
619 | ||
620 | /* Chars that mean this number is a floating point constant */ | |
621 | /* As in 0f12.456 */ | |
622 | /* or 0d1.2345e12 */ | |
623 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
624 | ||
625 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
626 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
627 | but nothing is ideal around here. | |
628 | */ | |
629 | ||
630 | static char *insn_error; | |
631 | ||
632 | static int auto_align = 1; | |
633 | ||
634 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
635 | offset in the stack frame from which to restore the $gp register. | |
636 | This is set by the .cprestore pseudo-op, and saved in this | |
637 | variable. */ | |
638 | static offsetT mips_cprestore_offset = -1; | |
639 | ||
67c1ffbe | 640 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 641 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 642 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
643 | static offsetT mips_cpreturn_offset = -1; |
644 | static int mips_cpreturn_register = -1; | |
645 | static int mips_gp_register = GP; | |
def2e0dd | 646 | static int mips_gprel_offset = 0; |
6478892d | 647 | |
7a621144 DJ |
648 | /* Whether mips_cprestore_offset has been set in the current function |
649 | (or whether it has already been warned about, if not). */ | |
650 | static int mips_cprestore_valid = 0; | |
651 | ||
252b5132 RH |
652 | /* This is the register which holds the stack frame, as set by the |
653 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
654 | static int mips_frame_reg = SP; | |
655 | ||
7a621144 DJ |
656 | /* Whether mips_frame_reg has been set in the current function |
657 | (or whether it has already been warned about, if not). */ | |
658 | static int mips_frame_reg_valid = 0; | |
659 | ||
252b5132 RH |
660 | /* To output NOP instructions correctly, we need to keep information |
661 | about the previous two instructions. */ | |
662 | ||
663 | /* Whether we are optimizing. The default value of 2 means to remove | |
664 | unneeded NOPs and swap branch instructions when possible. A value | |
665 | of 1 means to not swap branches. A value of 0 means to always | |
666 | insert NOPs. */ | |
667 | static int mips_optimize = 2; | |
668 | ||
669 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
670 | equivalent to seeing no -g option at all. */ | |
671 | static int mips_debug = 0; | |
672 | ||
7d8e00cf RS |
673 | /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ |
674 | #define MAX_VR4130_NOPS 4 | |
675 | ||
676 | /* The maximum number of NOPs needed to fill delay slots. */ | |
677 | #define MAX_DELAY_NOPS 2 | |
678 | ||
679 | /* The maximum number of NOPs needed for any purpose. */ | |
680 | #define MAX_NOPS 4 | |
71400594 RS |
681 | |
682 | /* A list of previous instructions, with index 0 being the most recent. | |
683 | We need to look back MAX_NOPS instructions when filling delay slots | |
684 | or working around processor errata. We need to look back one | |
685 | instruction further if we're thinking about using history[0] to | |
686 | fill a branch delay slot. */ | |
687 | static struct mips_cl_insn history[1 + MAX_NOPS]; | |
252b5132 | 688 | |
1e915849 | 689 | /* Nop instructions used by emit_nop. */ |
df58fc94 RS |
690 | static struct mips_cl_insn nop_insn; |
691 | static struct mips_cl_insn mips16_nop_insn; | |
692 | static struct mips_cl_insn micromips_nop16_insn; | |
693 | static struct mips_cl_insn micromips_nop32_insn; | |
1e915849 RS |
694 | |
695 | /* The appropriate nop for the current mode. */ | |
833794fc MR |
696 | #define NOP_INSN (mips_opts.mips16 \ |
697 | ? &mips16_nop_insn \ | |
698 | : (mips_opts.micromips \ | |
699 | ? (mips_opts.insn32 \ | |
700 | ? µmips_nop32_insn \ | |
701 | : µmips_nop16_insn) \ | |
702 | : &nop_insn)) | |
df58fc94 RS |
703 | |
704 | /* The size of NOP_INSN in bytes. */ | |
833794fc MR |
705 | #define NOP_INSN_SIZE ((mips_opts.mips16 \ |
706 | || (mips_opts.micromips && !mips_opts.insn32)) \ | |
707 | ? 2 : 4) | |
252b5132 | 708 | |
252b5132 RH |
709 | /* If this is set, it points to a frag holding nop instructions which |
710 | were inserted before the start of a noreorder section. If those | |
711 | nops turn out to be unnecessary, the size of the frag can be | |
712 | decreased. */ | |
713 | static fragS *prev_nop_frag; | |
714 | ||
715 | /* The number of nop instructions we created in prev_nop_frag. */ | |
716 | static int prev_nop_frag_holds; | |
717 | ||
718 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 719 | prev_nop_frag. */ |
252b5132 RH |
720 | static int prev_nop_frag_required; |
721 | ||
722 | /* The number of instructions we've seen since prev_nop_frag. */ | |
723 | static int prev_nop_frag_since; | |
724 | ||
e8044f35 RS |
725 | /* Relocations against symbols are sometimes done in two parts, with a HI |
726 | relocation and a LO relocation. Each relocation has only 16 bits of | |
727 | space to store an addend. This means that in order for the linker to | |
728 | handle carries correctly, it must be able to locate both the HI and | |
729 | the LO relocation. This means that the relocations must appear in | |
730 | order in the relocation table. | |
252b5132 RH |
731 | |
732 | In order to implement this, we keep track of each unmatched HI | |
733 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 734 | corresponding LO relocation. */ |
252b5132 | 735 | |
e972090a NC |
736 | struct mips_hi_fixup |
737 | { | |
252b5132 RH |
738 | /* Next HI fixup. */ |
739 | struct mips_hi_fixup *next; | |
740 | /* This fixup. */ | |
741 | fixS *fixp; | |
742 | /* The section this fixup is in. */ | |
743 | segT seg; | |
744 | }; | |
745 | ||
746 | /* The list of unmatched HI relocs. */ | |
747 | ||
748 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
749 | ||
64bdfcaf RS |
750 | /* The frag containing the last explicit relocation operator. |
751 | Null if explicit relocations have not been used. */ | |
752 | ||
753 | static fragS *prev_reloc_op_frag; | |
754 | ||
252b5132 RH |
755 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
756 | ||
757 | #define X ILLEGAL_REG | |
e972090a NC |
758 | static const int mips32_to_16_reg_map[] = |
759 | { | |
252b5132 RH |
760 | X, X, 2, 3, 4, 5, 6, 7, |
761 | X, X, X, X, X, X, X, X, | |
762 | 0, 1, X, X, X, X, X, X, | |
763 | X, X, X, X, X, X, X, X | |
764 | }; | |
765 | #undef X | |
766 | ||
767 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
768 | ||
e972090a NC |
769 | static const unsigned int mips16_to_32_reg_map[] = |
770 | { | |
252b5132 RH |
771 | 16, 17, 2, 3, 4, 5, 6, 7 |
772 | }; | |
60b63b72 | 773 | |
df58fc94 RS |
774 | /* Map normal MIPS register numbers to microMIPS register numbers. */ |
775 | ||
776 | #define mips32_to_micromips_reg_b_map mips32_to_16_reg_map | |
777 | #define mips32_to_micromips_reg_c_map mips32_to_16_reg_map | |
778 | #define mips32_to_micromips_reg_d_map mips32_to_16_reg_map | |
779 | #define mips32_to_micromips_reg_e_map mips32_to_16_reg_map | |
780 | #define mips32_to_micromips_reg_f_map mips32_to_16_reg_map | |
781 | #define mips32_to_micromips_reg_g_map mips32_to_16_reg_map | |
782 | #define mips32_to_micromips_reg_l_map mips32_to_16_reg_map | |
783 | ||
784 | #define X ILLEGAL_REG | |
df58fc94 RS |
785 | /* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */ |
786 | static const int mips32_to_micromips_reg_m_map[] = | |
787 | { | |
788 | 0, X, 2, 3, X, X, X, X, | |
789 | X, X, X, X, X, X, X, X, | |
790 | 4, 1, 5, 6, 7, X, X, X, | |
791 | X, X, X, X, X, X, X, X | |
792 | }; | |
793 | ||
794 | /* reg type q: 0, 2-7. 17. */ | |
795 | static const int mips32_to_micromips_reg_q_map[] = | |
796 | { | |
797 | 0, X, 2, 3, 4, 5, 6, 7, | |
798 | X, X, X, X, X, X, X, X, | |
799 | X, 1, X, X, X, X, X, X, | |
800 | X, X, X, X, X, X, X, X | |
801 | }; | |
802 | ||
803 | #define mips32_to_micromips_reg_n_map mips32_to_micromips_reg_m_map | |
804 | #undef X | |
805 | ||
806 | /* Map microMIPS register numbers to normal MIPS register numbers. */ | |
807 | ||
808 | #define micromips_to_32_reg_b_map mips16_to_32_reg_map | |
809 | #define micromips_to_32_reg_c_map mips16_to_32_reg_map | |
810 | #define micromips_to_32_reg_d_map mips16_to_32_reg_map | |
811 | #define micromips_to_32_reg_e_map mips16_to_32_reg_map | |
812 | #define micromips_to_32_reg_f_map mips16_to_32_reg_map | |
813 | #define micromips_to_32_reg_g_map mips16_to_32_reg_map | |
814 | ||
815 | /* The microMIPS registers with type h. */ | |
e76ff5ab | 816 | static const unsigned int micromips_to_32_reg_h_map1[] = |
df58fc94 RS |
817 | { |
818 | 5, 5, 6, 4, 4, 4, 4, 4 | |
819 | }; | |
e76ff5ab | 820 | static const unsigned int micromips_to_32_reg_h_map2[] = |
df58fc94 RS |
821 | { |
822 | 6, 7, 7, 21, 22, 5, 6, 7 | |
823 | }; | |
824 | ||
825 | #define micromips_to_32_reg_l_map mips16_to_32_reg_map | |
826 | ||
827 | /* The microMIPS registers with type m. */ | |
828 | static const unsigned int micromips_to_32_reg_m_map[] = | |
829 | { | |
830 | 0, 17, 2, 3, 16, 18, 19, 20 | |
831 | }; | |
832 | ||
833 | #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map | |
834 | ||
835 | /* The microMIPS registers with type q. */ | |
836 | static const unsigned int micromips_to_32_reg_q_map[] = | |
837 | { | |
838 | 0, 17, 2, 3, 4, 5, 6, 7 | |
839 | }; | |
840 | ||
841 | /* microMIPS imm type B. */ | |
842 | static const int micromips_imm_b_map[] = | |
843 | { | |
844 | 1, 4, 8, 12, 16, 20, 24, -1 | |
845 | }; | |
846 | ||
847 | /* microMIPS imm type C. */ | |
848 | static const int micromips_imm_c_map[] = | |
849 | { | |
850 | 128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 255, 32768, 65535 | |
851 | }; | |
852 | ||
71400594 RS |
853 | /* Classifies the kind of instructions we're interested in when |
854 | implementing -mfix-vr4120. */ | |
c67a084a NC |
855 | enum fix_vr4120_class |
856 | { | |
71400594 RS |
857 | FIX_VR4120_MACC, |
858 | FIX_VR4120_DMACC, | |
859 | FIX_VR4120_MULT, | |
860 | FIX_VR4120_DMULT, | |
861 | FIX_VR4120_DIV, | |
862 | FIX_VR4120_MTHILO, | |
863 | NUM_FIX_VR4120_CLASSES | |
864 | }; | |
865 | ||
c67a084a NC |
866 | /* ...likewise -mfix-loongson2f-jump. */ |
867 | static bfd_boolean mips_fix_loongson2f_jump; | |
868 | ||
869 | /* ...likewise -mfix-loongson2f-nop. */ | |
870 | static bfd_boolean mips_fix_loongson2f_nop; | |
871 | ||
872 | /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */ | |
873 | static bfd_boolean mips_fix_loongson2f; | |
874 | ||
71400594 RS |
875 | /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if |
876 | there must be at least one other instruction between an instruction | |
877 | of type X and an instruction of type Y. */ | |
878 | static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; | |
879 | ||
880 | /* True if -mfix-vr4120 is in force. */ | |
d766e8ec | 881 | static int mips_fix_vr4120; |
4a6a3df4 | 882 | |
7d8e00cf RS |
883 | /* ...likewise -mfix-vr4130. */ |
884 | static int mips_fix_vr4130; | |
885 | ||
6a32d874 CM |
886 | /* ...likewise -mfix-24k. */ |
887 | static int mips_fix_24k; | |
888 | ||
d954098f DD |
889 | /* ...likewise -mfix-cn63xxp1 */ |
890 | static bfd_boolean mips_fix_cn63xxp1; | |
891 | ||
4a6a3df4 AO |
892 | /* We don't relax branches by default, since this causes us to expand |
893 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
894 | fail to compute the offset before expanding the macro to the most | |
895 | efficient expansion. */ | |
896 | ||
897 | static int mips_relax_branch; | |
252b5132 | 898 | \f |
4d7206a2 RS |
899 | /* The expansion of many macros depends on the type of symbol that |
900 | they refer to. For example, when generating position-dependent code, | |
901 | a macro that refers to a symbol may have two different expansions, | |
902 | one which uses GP-relative addresses and one which uses absolute | |
903 | addresses. When generating SVR4-style PIC, a macro may have | |
904 | different expansions for local and global symbols. | |
905 | ||
906 | We handle these situations by generating both sequences and putting | |
907 | them in variant frags. In position-dependent code, the first sequence | |
908 | will be the GP-relative one and the second sequence will be the | |
909 | absolute one. In SVR4 PIC, the first sequence will be for global | |
910 | symbols and the second will be for local symbols. | |
911 | ||
584892a6 RS |
912 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
913 | SECOND are the lengths of the two sequences in bytes. These fields | |
914 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
915 | the subtype has the following flags: | |
4d7206a2 | 916 | |
584892a6 RS |
917 | RELAX_USE_SECOND |
918 | Set if it has been decided that we should use the second | |
919 | sequence instead of the first. | |
920 | ||
921 | RELAX_SECOND_LONGER | |
922 | Set in the first variant frag if the macro's second implementation | |
923 | is longer than its first. This refers to the macro as a whole, | |
924 | not an individual relaxation. | |
925 | ||
926 | RELAX_NOMACRO | |
927 | Set in the first variant frag if the macro appeared in a .set nomacro | |
928 | block and if one alternative requires a warning but the other does not. | |
929 | ||
930 | RELAX_DELAY_SLOT | |
931 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
932 | delay slot. | |
4d7206a2 | 933 | |
df58fc94 RS |
934 | RELAX_DELAY_SLOT_16BIT |
935 | Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a | |
936 | 16-bit instruction. | |
937 | ||
938 | RELAX_DELAY_SLOT_SIZE_FIRST | |
939 | Like RELAX_DELAY_SLOT, but indicates that the first implementation of | |
940 | the macro is of the wrong size for the branch delay slot. | |
941 | ||
942 | RELAX_DELAY_SLOT_SIZE_SECOND | |
943 | Like RELAX_DELAY_SLOT, but indicates that the second implementation of | |
944 | the macro is of the wrong size for the branch delay slot. | |
945 | ||
4d7206a2 RS |
946 | The frag's "opcode" points to the first fixup for relaxable code. |
947 | ||
948 | Relaxable macros are generated using a sequence such as: | |
949 | ||
950 | relax_start (SYMBOL); | |
951 | ... generate first expansion ... | |
952 | relax_switch (); | |
953 | ... generate second expansion ... | |
954 | relax_end (); | |
955 | ||
956 | The code and fixups for the unwanted alternative are discarded | |
957 | by md_convert_frag. */ | |
584892a6 | 958 | #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) |
4d7206a2 | 959 | |
584892a6 RS |
960 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
961 | #define RELAX_SECOND(X) ((X) & 0xff) | |
962 | #define RELAX_USE_SECOND 0x10000 | |
963 | #define RELAX_SECOND_LONGER 0x20000 | |
964 | #define RELAX_NOMACRO 0x40000 | |
965 | #define RELAX_DELAY_SLOT 0x80000 | |
df58fc94 RS |
966 | #define RELAX_DELAY_SLOT_16BIT 0x100000 |
967 | #define RELAX_DELAY_SLOT_SIZE_FIRST 0x200000 | |
968 | #define RELAX_DELAY_SLOT_SIZE_SECOND 0x400000 | |
252b5132 | 969 | |
4a6a3df4 AO |
970 | /* Branch without likely bit. If label is out of range, we turn: |
971 | ||
972 | beq reg1, reg2, label | |
973 | delay slot | |
974 | ||
975 | into | |
976 | ||
977 | bne reg1, reg2, 0f | |
978 | nop | |
979 | j label | |
980 | 0: delay slot | |
981 | ||
982 | with the following opcode replacements: | |
983 | ||
984 | beq <-> bne | |
985 | blez <-> bgtz | |
986 | bltz <-> bgez | |
987 | bc1f <-> bc1t | |
988 | ||
989 | bltzal <-> bgezal (with jal label instead of j label) | |
990 | ||
991 | Even though keeping the delay slot instruction in the delay slot of | |
992 | the branch would be more efficient, it would be very tricky to do | |
993 | correctly, because we'd have to introduce a variable frag *after* | |
994 | the delay slot instruction, and expand that instead. Let's do it | |
995 | the easy way for now, even if the branch-not-taken case now costs | |
996 | one additional instruction. Out-of-range branches are not supposed | |
997 | to be common, anyway. | |
998 | ||
999 | Branch likely. If label is out of range, we turn: | |
1000 | ||
1001 | beql reg1, reg2, label | |
1002 | delay slot (annulled if branch not taken) | |
1003 | ||
1004 | into | |
1005 | ||
1006 | beql reg1, reg2, 1f | |
1007 | nop | |
1008 | beql $0, $0, 2f | |
1009 | nop | |
1010 | 1: j[al] label | |
1011 | delay slot (executed only if branch taken) | |
1012 | 2: | |
1013 | ||
1014 | It would be possible to generate a shorter sequence by losing the | |
1015 | likely bit, generating something like: | |
b34976b6 | 1016 | |
4a6a3df4 AO |
1017 | bne reg1, reg2, 0f |
1018 | nop | |
1019 | j[al] label | |
1020 | delay slot (executed only if branch taken) | |
1021 | 0: | |
1022 | ||
1023 | beql -> bne | |
1024 | bnel -> beq | |
1025 | blezl -> bgtz | |
1026 | bgtzl -> blez | |
1027 | bltzl -> bgez | |
1028 | bgezl -> bltz | |
1029 | bc1fl -> bc1t | |
1030 | bc1tl -> bc1f | |
1031 | ||
1032 | bltzall -> bgezal (with jal label instead of j label) | |
1033 | bgezall -> bltzal (ditto) | |
1034 | ||
1035 | ||
1036 | but it's not clear that it would actually improve performance. */ | |
66b3e8da MR |
1037 | #define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \ |
1038 | ((relax_substateT) \ | |
1039 | (0xc0000000 \ | |
1040 | | ((at) & 0x1f) \ | |
1041 | | ((toofar) ? 0x20 : 0) \ | |
1042 | | ((link) ? 0x40 : 0) \ | |
1043 | | ((likely) ? 0x80 : 0) \ | |
1044 | | ((uncond) ? 0x100 : 0))) | |
4a6a3df4 | 1045 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
66b3e8da MR |
1046 | #define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0) |
1047 | #define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0) | |
1048 | #define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0) | |
1049 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0) | |
1050 | #define RELAX_BRANCH_AT(i) ((i) & 0x1f) | |
4a6a3df4 | 1051 | |
252b5132 RH |
1052 | /* For mips16 code, we use an entirely different form of relaxation. |
1053 | mips16 supports two versions of most instructions which take | |
1054 | immediate values: a small one which takes some small value, and a | |
1055 | larger one which takes a 16 bit value. Since branches also follow | |
1056 | this pattern, relaxing these values is required. | |
1057 | ||
1058 | We can assemble both mips16 and normal MIPS code in a single | |
1059 | object. Therefore, we need to support this type of relaxation at | |
1060 | the same time that we support the relaxation described above. We | |
1061 | use the high bit of the subtype field to distinguish these cases. | |
1062 | ||
1063 | The information we store for this type of relaxation is the | |
1064 | argument code found in the opcode file for this relocation, whether | |
1065 | the user explicitly requested a small or extended form, and whether | |
1066 | the relocation is in a jump or jal delay slot. That tells us the | |
1067 | size of the value, and how it should be stored. We also store | |
1068 | whether the fragment is considered to be extended or not. We also | |
1069 | store whether this is known to be a branch to a different section, | |
1070 | whether we have tried to relax this frag yet, and whether we have | |
1071 | ever extended a PC relative fragment because of a shift count. */ | |
1072 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
1073 | (0x80000000 \ | |
1074 | | ((type) & 0xff) \ | |
1075 | | ((small) ? 0x100 : 0) \ | |
1076 | | ((ext) ? 0x200 : 0) \ | |
1077 | | ((dslot) ? 0x400 : 0) \ | |
1078 | | ((jal_dslot) ? 0x800 : 0)) | |
4a6a3df4 | 1079 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 RH |
1080 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
1081 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
1082 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
1083 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
1084 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
1085 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
1086 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
1087 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
1088 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
1089 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
1090 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
885add95 | 1091 | |
df58fc94 RS |
1092 | /* For microMIPS code, we use relaxation similar to one we use for |
1093 | MIPS16 code. Some instructions that take immediate values support | |
1094 | two encodings: a small one which takes some small value, and a | |
1095 | larger one which takes a 16 bit value. As some branches also follow | |
1096 | this pattern, relaxing these values is required. | |
1097 | ||
1098 | We can assemble both microMIPS and normal MIPS code in a single | |
1099 | object. Therefore, we need to support this type of relaxation at | |
1100 | the same time that we support the relaxation described above. We | |
1101 | use one of the high bits of the subtype field to distinguish these | |
1102 | cases. | |
1103 | ||
1104 | The information we store for this type of relaxation is the argument | |
1105 | code found in the opcode file for this relocation, the register | |
40209cad MR |
1106 | selected as the assembler temporary, whether the branch is |
1107 | unconditional, whether it is compact, whether it stores the link | |
1108 | address implicitly in $ra, whether relaxation of out-of-range 32-bit | |
1109 | branches to a sequence of instructions is enabled, and whether the | |
1110 | displacement of a branch is too large to fit as an immediate argument | |
1111 | of a 16-bit and a 32-bit branch, respectively. */ | |
1112 | #define RELAX_MICROMIPS_ENCODE(type, at, uncond, compact, link, \ | |
1113 | relax32, toofar16, toofar32) \ | |
1114 | (0x40000000 \ | |
1115 | | ((type) & 0xff) \ | |
1116 | | (((at) & 0x1f) << 8) \ | |
1117 | | ((uncond) ? 0x2000 : 0) \ | |
1118 | | ((compact) ? 0x4000 : 0) \ | |
1119 | | ((link) ? 0x8000 : 0) \ | |
1120 | | ((relax32) ? 0x10000 : 0) \ | |
1121 | | ((toofar16) ? 0x20000 : 0) \ | |
1122 | | ((toofar32) ? 0x40000 : 0)) | |
df58fc94 RS |
1123 | #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000) |
1124 | #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff) | |
1125 | #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f) | |
40209cad MR |
1126 | #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x2000) != 0) |
1127 | #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x4000) != 0) | |
1128 | #define RELAX_MICROMIPS_LINK(i) (((i) & 0x8000) != 0) | |
1129 | #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x10000) != 0) | |
1130 | ||
1131 | #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x20000) != 0) | |
1132 | #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x20000) | |
1133 | #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x20000) | |
1134 | #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x40000) != 0) | |
1135 | #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x40000) | |
1136 | #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x40000) | |
df58fc94 | 1137 | |
43c0598f RS |
1138 | /* Sign-extend 16-bit value X. */ |
1139 | #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000) | |
1140 | ||
885add95 CD |
1141 | /* Is the given value a sign-extended 32-bit value? */ |
1142 | #define IS_SEXT_32BIT_NUM(x) \ | |
1143 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
1144 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
1145 | ||
1146 | /* Is the given value a sign-extended 16-bit value? */ | |
1147 | #define IS_SEXT_16BIT_NUM(x) \ | |
1148 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
1149 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
1150 | ||
df58fc94 RS |
1151 | /* Is the given value a sign-extended 12-bit value? */ |
1152 | #define IS_SEXT_12BIT_NUM(x) \ | |
1153 | (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x)) | |
1154 | ||
7f3c4072 CM |
1155 | /* Is the given value a sign-extended 9-bit value? */ |
1156 | #define IS_SEXT_9BIT_NUM(x) \ | |
1157 | (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x)) | |
1158 | ||
2051e8c4 MR |
1159 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ |
1160 | #define IS_ZEXT_32BIT_NUM(x) \ | |
1161 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
1162 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
1163 | ||
bf12938e RS |
1164 | /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in |
1165 | VALUE << SHIFT. VALUE is evaluated exactly once. */ | |
1166 | #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \ | |
1167 | (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \ | |
1168 | | (((VALUE) & (MASK)) << (SHIFT))) | |
1169 | ||
1170 | /* Extract bits MASK << SHIFT from STRUCT and shift them right | |
1171 | SHIFT places. */ | |
1172 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
1173 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
1174 | ||
1175 | /* Change INSN's opcode so that the operand given by FIELD has value VALUE. | |
1176 | INSN is a mips_cl_insn structure and VALUE is evaluated exactly once. | |
1177 | ||
1178 | include/opcode/mips.h specifies operand fields using the macros | |
1179 | OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start | |
1180 | with "MIPS16OP" instead of "OP". */ | |
df58fc94 RS |
1181 | #define INSERT_OPERAND(MICROMIPS, FIELD, INSN, VALUE) \ |
1182 | do \ | |
1183 | if (!(MICROMIPS)) \ | |
1184 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1185 | OP_MASK_##FIELD, OP_SH_##FIELD); \ | |
1186 | else \ | |
1187 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1188 | MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD); \ | |
1189 | while (0) | |
bf12938e RS |
1190 | #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \ |
1191 | INSERT_BITS ((INSN).insn_opcode, VALUE, \ | |
1192 | MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD) | |
1193 | ||
1194 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ | |
df58fc94 RS |
1195 | #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \ |
1196 | (!(MICROMIPS) \ | |
1197 | ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \ | |
1198 | : EXTRACT_BITS ((INSN).insn_opcode, \ | |
1199 | MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD)) | |
bf12938e RS |
1200 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ |
1201 | EXTRACT_BITS ((INSN).insn_opcode, \ | |
1202 | MIPS16OP_MASK_##FIELD, \ | |
1203 | MIPS16OP_SH_##FIELD) | |
5c04167a RS |
1204 | |
1205 | /* The MIPS16 EXTEND opcode, shifted left 16 places. */ | |
1206 | #define MIPS16_EXTEND (0xf000U << 16) | |
4d7206a2 | 1207 | \f |
df58fc94 RS |
1208 | /* Whether or not we are emitting a branch-likely macro. */ |
1209 | static bfd_boolean emit_branch_likely_macro = FALSE; | |
1210 | ||
4d7206a2 RS |
1211 | /* Global variables used when generating relaxable macros. See the |
1212 | comment above RELAX_ENCODE for more details about how relaxation | |
1213 | is used. */ | |
1214 | static struct { | |
1215 | /* 0 if we're not emitting a relaxable macro. | |
1216 | 1 if we're emitting the first of the two relaxation alternatives. | |
1217 | 2 if we're emitting the second alternative. */ | |
1218 | int sequence; | |
1219 | ||
1220 | /* The first relaxable fixup in the current frag. (In other words, | |
1221 | the first fixup that refers to relaxable code.) */ | |
1222 | fixS *first_fixup; | |
1223 | ||
1224 | /* sizes[0] says how many bytes of the first alternative are stored in | |
1225 | the current frag. Likewise sizes[1] for the second alternative. */ | |
1226 | unsigned int sizes[2]; | |
1227 | ||
1228 | /* The symbol on which the choice of sequence depends. */ | |
1229 | symbolS *symbol; | |
1230 | } mips_relax; | |
252b5132 | 1231 | \f |
584892a6 RS |
1232 | /* Global variables used to decide whether a macro needs a warning. */ |
1233 | static struct { | |
1234 | /* True if the macro is in a branch delay slot. */ | |
1235 | bfd_boolean delay_slot_p; | |
1236 | ||
df58fc94 RS |
1237 | /* Set to the length in bytes required if the macro is in a delay slot |
1238 | that requires a specific length of instruction, otherwise zero. */ | |
1239 | unsigned int delay_slot_length; | |
1240 | ||
584892a6 RS |
1241 | /* For relaxable macros, sizes[0] is the length of the first alternative |
1242 | in bytes and sizes[1] is the length of the second alternative. | |
1243 | For non-relaxable macros, both elements give the length of the | |
1244 | macro in bytes. */ | |
1245 | unsigned int sizes[2]; | |
1246 | ||
df58fc94 RS |
1247 | /* For relaxable macros, first_insn_sizes[0] is the length of the first |
1248 | instruction of the first alternative in bytes and first_insn_sizes[1] | |
1249 | is the length of the first instruction of the second alternative. | |
1250 | For non-relaxable macros, both elements give the length of the first | |
1251 | instruction in bytes. | |
1252 | ||
1253 | Set to zero if we haven't yet seen the first instruction. */ | |
1254 | unsigned int first_insn_sizes[2]; | |
1255 | ||
1256 | /* For relaxable macros, insns[0] is the number of instructions for the | |
1257 | first alternative and insns[1] is the number of instructions for the | |
1258 | second alternative. | |
1259 | ||
1260 | For non-relaxable macros, both elements give the number of | |
1261 | instructions for the macro. */ | |
1262 | unsigned int insns[2]; | |
1263 | ||
584892a6 RS |
1264 | /* The first variant frag for this macro. */ |
1265 | fragS *first_frag; | |
1266 | } mips_macro_warning; | |
1267 | \f | |
252b5132 RH |
1268 | /* Prototypes for static functions. */ |
1269 | ||
252b5132 RH |
1270 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; |
1271 | ||
b34976b6 | 1272 | static void append_insn |
df58fc94 RS |
1273 | (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *, |
1274 | bfd_boolean expansionp); | |
7d10b47d | 1275 | static void mips_no_prev_insn (void); |
c67a084a | 1276 | static void macro_build (expressionS *, const char *, const char *, ...); |
b34976b6 | 1277 | static void mips16_macro_build |
03ea81db | 1278 | (expressionS *, const char *, const char *, va_list *); |
67c0d1eb | 1279 | static void load_register (int, expressionS *, int); |
584892a6 RS |
1280 | static void macro_start (void); |
1281 | static void macro_end (void); | |
833794fc | 1282 | static void macro (struct mips_cl_insn *ip, char *str); |
17a2f251 | 1283 | static void mips16_macro (struct mips_cl_insn * ip); |
17a2f251 TS |
1284 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
1285 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
b34976b6 | 1286 | static void mips16_immed |
43c0598f RS |
1287 | (char *, unsigned int, int, bfd_reloc_code_real_type, offsetT, |
1288 | unsigned int, unsigned long *); | |
5e0116d5 | 1289 | static size_t my_getSmallExpression |
17a2f251 TS |
1290 | (expressionS *, bfd_reloc_code_real_type *, char *); |
1291 | static void my_getExpression (expressionS *, char *); | |
1292 | static void s_align (int); | |
1293 | static void s_change_sec (int); | |
1294 | static void s_change_section (int); | |
1295 | static void s_cons (int); | |
1296 | static void s_float_cons (int); | |
1297 | static void s_mips_globl (int); | |
1298 | static void s_option (int); | |
1299 | static void s_mipsset (int); | |
1300 | static void s_abicalls (int); | |
1301 | static void s_cpload (int); | |
1302 | static void s_cpsetup (int); | |
1303 | static void s_cplocal (int); | |
1304 | static void s_cprestore (int); | |
1305 | static void s_cpreturn (int); | |
741d6ea8 JM |
1306 | static void s_dtprelword (int); |
1307 | static void s_dtpreldword (int); | |
d0f13682 CLT |
1308 | static void s_tprelword (int); |
1309 | static void s_tpreldword (int); | |
17a2f251 TS |
1310 | static void s_gpvalue (int); |
1311 | static void s_gpword (int); | |
1312 | static void s_gpdword (int); | |
a3f278e2 | 1313 | static void s_ehword (int); |
17a2f251 TS |
1314 | static void s_cpadd (int); |
1315 | static void s_insn (int); | |
ba92f887 | 1316 | static void s_nan (int); |
17a2f251 TS |
1317 | static void md_obj_begin (void); |
1318 | static void md_obj_end (void); | |
1319 | static void s_mips_ent (int); | |
1320 | static void s_mips_end (int); | |
1321 | static void s_mips_frame (int); | |
1322 | static void s_mips_mask (int reg_type); | |
1323 | static void s_mips_stab (int); | |
1324 | static void s_mips_weakext (int); | |
1325 | static void s_mips_file (int); | |
1326 | static void s_mips_loc (int); | |
1327 | static bfd_boolean pic_need_relax (symbolS *, asection *); | |
4a6a3df4 | 1328 | static int relaxed_branch_length (fragS *, asection *, int); |
17a2f251 | 1329 | static int validate_mips_insn (const struct mips_opcode *); |
df58fc94 RS |
1330 | static int validate_micromips_insn (const struct mips_opcode *); |
1331 | static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int); | |
1332 | static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int); | |
e7af610e NC |
1333 | |
1334 | /* Table and functions used to map between CPU/ISA names, and | |
1335 | ISA levels, and CPU numbers. */ | |
1336 | ||
e972090a NC |
1337 | struct mips_cpu_info |
1338 | { | |
e7af610e | 1339 | const char *name; /* CPU or ISA name. */ |
d16afab6 RS |
1340 | int flags; /* MIPS_CPU_* flags. */ |
1341 | int ase; /* Set of ASEs implemented by the CPU. */ | |
e7af610e NC |
1342 | int isa; /* ISA level. */ |
1343 | int cpu; /* CPU number (default CPU if ISA). */ | |
1344 | }; | |
1345 | ||
ad3fea08 | 1346 | #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ |
ad3fea08 | 1347 | |
17a2f251 TS |
1348 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
1349 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
1350 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 | 1351 | \f |
c31f3936 RS |
1352 | /* Command-line options. */ |
1353 | const char *md_shortopts = "O::g::G:"; | |
1354 | ||
1355 | enum options | |
1356 | { | |
1357 | OPTION_MARCH = OPTION_MD_BASE, | |
1358 | OPTION_MTUNE, | |
1359 | OPTION_MIPS1, | |
1360 | OPTION_MIPS2, | |
1361 | OPTION_MIPS3, | |
1362 | OPTION_MIPS4, | |
1363 | OPTION_MIPS5, | |
1364 | OPTION_MIPS32, | |
1365 | OPTION_MIPS64, | |
1366 | OPTION_MIPS32R2, | |
1367 | OPTION_MIPS64R2, | |
1368 | OPTION_MIPS16, | |
1369 | OPTION_NO_MIPS16, | |
1370 | OPTION_MIPS3D, | |
1371 | OPTION_NO_MIPS3D, | |
1372 | OPTION_MDMX, | |
1373 | OPTION_NO_MDMX, | |
1374 | OPTION_DSP, | |
1375 | OPTION_NO_DSP, | |
1376 | OPTION_MT, | |
1377 | OPTION_NO_MT, | |
1378 | OPTION_VIRT, | |
1379 | OPTION_NO_VIRT, | |
1380 | OPTION_SMARTMIPS, | |
1381 | OPTION_NO_SMARTMIPS, | |
1382 | OPTION_DSPR2, | |
1383 | OPTION_NO_DSPR2, | |
1384 | OPTION_EVA, | |
1385 | OPTION_NO_EVA, | |
1386 | OPTION_MICROMIPS, | |
1387 | OPTION_NO_MICROMIPS, | |
1388 | OPTION_MCU, | |
1389 | OPTION_NO_MCU, | |
1390 | OPTION_COMPAT_ARCH_BASE, | |
1391 | OPTION_M4650, | |
1392 | OPTION_NO_M4650, | |
1393 | OPTION_M4010, | |
1394 | OPTION_NO_M4010, | |
1395 | OPTION_M4100, | |
1396 | OPTION_NO_M4100, | |
1397 | OPTION_M3900, | |
1398 | OPTION_NO_M3900, | |
1399 | OPTION_M7000_HILO_FIX, | |
1400 | OPTION_MNO_7000_HILO_FIX, | |
1401 | OPTION_FIX_24K, | |
1402 | OPTION_NO_FIX_24K, | |
1403 | OPTION_FIX_LOONGSON2F_JUMP, | |
1404 | OPTION_NO_FIX_LOONGSON2F_JUMP, | |
1405 | OPTION_FIX_LOONGSON2F_NOP, | |
1406 | OPTION_NO_FIX_LOONGSON2F_NOP, | |
1407 | OPTION_FIX_VR4120, | |
1408 | OPTION_NO_FIX_VR4120, | |
1409 | OPTION_FIX_VR4130, | |
1410 | OPTION_NO_FIX_VR4130, | |
1411 | OPTION_FIX_CN63XXP1, | |
1412 | OPTION_NO_FIX_CN63XXP1, | |
1413 | OPTION_TRAP, | |
1414 | OPTION_BREAK, | |
1415 | OPTION_EB, | |
1416 | OPTION_EL, | |
1417 | OPTION_FP32, | |
1418 | OPTION_GP32, | |
1419 | OPTION_CONSTRUCT_FLOATS, | |
1420 | OPTION_NO_CONSTRUCT_FLOATS, | |
1421 | OPTION_FP64, | |
1422 | OPTION_GP64, | |
1423 | OPTION_RELAX_BRANCH, | |
1424 | OPTION_NO_RELAX_BRANCH, | |
833794fc MR |
1425 | OPTION_INSN32, |
1426 | OPTION_NO_INSN32, | |
c31f3936 RS |
1427 | OPTION_MSHARED, |
1428 | OPTION_MNO_SHARED, | |
1429 | OPTION_MSYM32, | |
1430 | OPTION_MNO_SYM32, | |
1431 | OPTION_SOFT_FLOAT, | |
1432 | OPTION_HARD_FLOAT, | |
1433 | OPTION_SINGLE_FLOAT, | |
1434 | OPTION_DOUBLE_FLOAT, | |
1435 | OPTION_32, | |
c31f3936 RS |
1436 | OPTION_CALL_SHARED, |
1437 | OPTION_CALL_NONPIC, | |
1438 | OPTION_NON_SHARED, | |
1439 | OPTION_XGOT, | |
1440 | OPTION_MABI, | |
1441 | OPTION_N32, | |
1442 | OPTION_64, | |
1443 | OPTION_MDEBUG, | |
1444 | OPTION_NO_MDEBUG, | |
1445 | OPTION_PDR, | |
1446 | OPTION_NO_PDR, | |
1447 | OPTION_MVXWORKS_PIC, | |
ba92f887 | 1448 | OPTION_NAN, |
c31f3936 RS |
1449 | OPTION_END_OF_ENUM |
1450 | }; | |
1451 | ||
1452 | struct option md_longopts[] = | |
1453 | { | |
1454 | /* Options which specify architecture. */ | |
1455 | {"march", required_argument, NULL, OPTION_MARCH}, | |
1456 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
1457 | {"mips0", no_argument, NULL, OPTION_MIPS1}, | |
1458 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
1459 | {"mips2", no_argument, NULL, OPTION_MIPS2}, | |
1460 | {"mips3", no_argument, NULL, OPTION_MIPS3}, | |
1461 | {"mips4", no_argument, NULL, OPTION_MIPS4}, | |
1462 | {"mips5", no_argument, NULL, OPTION_MIPS5}, | |
1463 | {"mips32", no_argument, NULL, OPTION_MIPS32}, | |
1464 | {"mips64", no_argument, NULL, OPTION_MIPS64}, | |
1465 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, | |
1466 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, | |
1467 | ||
1468 | /* Options which specify Application Specific Extensions (ASEs). */ | |
1469 | {"mips16", no_argument, NULL, OPTION_MIPS16}, | |
1470 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, | |
1471 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, | |
1472 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, | |
1473 | {"mdmx", no_argument, NULL, OPTION_MDMX}, | |
1474 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, | |
1475 | {"mdsp", no_argument, NULL, OPTION_DSP}, | |
1476 | {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, | |
1477 | {"mmt", no_argument, NULL, OPTION_MT}, | |
1478 | {"mno-mt", no_argument, NULL, OPTION_NO_MT}, | |
1479 | {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS}, | |
1480 | {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS}, | |
1481 | {"mdspr2", no_argument, NULL, OPTION_DSPR2}, | |
1482 | {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2}, | |
1483 | {"meva", no_argument, NULL, OPTION_EVA}, | |
1484 | {"mno-eva", no_argument, NULL, OPTION_NO_EVA}, | |
1485 | {"mmicromips", no_argument, NULL, OPTION_MICROMIPS}, | |
1486 | {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS}, | |
1487 | {"mmcu", no_argument, NULL, OPTION_MCU}, | |
1488 | {"mno-mcu", no_argument, NULL, OPTION_NO_MCU}, | |
1489 | {"mvirt", no_argument, NULL, OPTION_VIRT}, | |
1490 | {"mno-virt", no_argument, NULL, OPTION_NO_VIRT}, | |
1491 | ||
1492 | /* Old-style architecture options. Don't add more of these. */ | |
1493 | {"m4650", no_argument, NULL, OPTION_M4650}, | |
1494 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, | |
1495 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
1496 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
1497 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
1498 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
1499 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
1500 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
1501 | ||
1502 | /* Options which enable bug fixes. */ | |
1503 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, | |
1504 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
1505 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
1506 | {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP}, | |
1507 | {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP}, | |
1508 | {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP}, | |
1509 | {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP}, | |
1510 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, | |
1511 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
1512 | {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, | |
1513 | {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, | |
1514 | {"mfix-24k", no_argument, NULL, OPTION_FIX_24K}, | |
1515 | {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K}, | |
1516 | {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1}, | |
1517 | {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1}, | |
1518 | ||
1519 | /* Miscellaneous options. */ | |
1520 | {"trap", no_argument, NULL, OPTION_TRAP}, | |
1521 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
1522 | {"break", no_argument, NULL, OPTION_BREAK}, | |
1523 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
1524 | {"EB", no_argument, NULL, OPTION_EB}, | |
1525 | {"EL", no_argument, NULL, OPTION_EL}, | |
1526 | {"mfp32", no_argument, NULL, OPTION_FP32}, | |
1527 | {"mgp32", no_argument, NULL, OPTION_GP32}, | |
1528 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, | |
1529 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, | |
1530 | {"mfp64", no_argument, NULL, OPTION_FP64}, | |
1531 | {"mgp64", no_argument, NULL, OPTION_GP64}, | |
1532 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, | |
1533 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
833794fc MR |
1534 | {"minsn32", no_argument, NULL, OPTION_INSN32}, |
1535 | {"mno-insn32", no_argument, NULL, OPTION_NO_INSN32}, | |
c31f3936 RS |
1536 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
1537 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
1538 | {"msym32", no_argument, NULL, OPTION_MSYM32}, | |
1539 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, | |
1540 | {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT}, | |
1541 | {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT}, | |
1542 | {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT}, | |
1543 | {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT}, | |
1544 | ||
1545 | /* Strictly speaking this next option is ELF specific, | |
1546 | but we allow it for other ports as well in order to | |
1547 | make testing easier. */ | |
1548 | {"32", no_argument, NULL, OPTION_32}, | |
1549 | ||
1550 | /* ELF-specific options. */ | |
c31f3936 RS |
1551 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
1552 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
1553 | {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC}, | |
1554 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, | |
1555 | {"xgot", no_argument, NULL, OPTION_XGOT}, | |
1556 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
1557 | {"n32", no_argument, NULL, OPTION_N32}, | |
1558 | {"64", no_argument, NULL, OPTION_64}, | |
1559 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, | |
1560 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, | |
1561 | {"mpdr", no_argument, NULL, OPTION_PDR}, | |
1562 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, | |
1563 | {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, | |
ba92f887 | 1564 | {"mnan", required_argument, NULL, OPTION_NAN}, |
c31f3936 RS |
1565 | |
1566 | {NULL, no_argument, NULL, 0} | |
1567 | }; | |
1568 | size_t md_longopts_size = sizeof (md_longopts); | |
1569 | \f | |
c6278170 RS |
1570 | /* Information about either an Application Specific Extension or an |
1571 | optional architecture feature that, for simplicity, we treat in the | |
1572 | same way as an ASE. */ | |
1573 | struct mips_ase | |
1574 | { | |
1575 | /* The name of the ASE, used in both the command-line and .set options. */ | |
1576 | const char *name; | |
1577 | ||
1578 | /* The associated ASE_* flags. If the ASE is available on both 32-bit | |
1579 | and 64-bit architectures, the flags here refer to the subset that | |
1580 | is available on both. */ | |
1581 | unsigned int flags; | |
1582 | ||
1583 | /* The ASE_* flag used for instructions that are available on 64-bit | |
1584 | architectures but that are not included in FLAGS. */ | |
1585 | unsigned int flags64; | |
1586 | ||
1587 | /* The command-line options that turn the ASE on and off. */ | |
1588 | int option_on; | |
1589 | int option_off; | |
1590 | ||
1591 | /* The minimum required architecture revisions for MIPS32, MIPS64, | |
1592 | microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */ | |
1593 | int mips32_rev; | |
1594 | int mips64_rev; | |
1595 | int micromips32_rev; | |
1596 | int micromips64_rev; | |
1597 | }; | |
1598 | ||
1599 | /* A table of all supported ASEs. */ | |
1600 | static const struct mips_ase mips_ases[] = { | |
1601 | { "dsp", ASE_DSP, ASE_DSP64, | |
1602 | OPTION_DSP, OPTION_NO_DSP, | |
1603 | 2, 2, 2, 2 }, | |
1604 | ||
1605 | { "dspr2", ASE_DSP | ASE_DSPR2, 0, | |
1606 | OPTION_DSPR2, OPTION_NO_DSPR2, | |
1607 | 2, 2, 2, 2 }, | |
1608 | ||
1609 | { "eva", ASE_EVA, 0, | |
1610 | OPTION_EVA, OPTION_NO_EVA, | |
1611 | 2, 2, 2, 2 }, | |
1612 | ||
1613 | { "mcu", ASE_MCU, 0, | |
1614 | OPTION_MCU, OPTION_NO_MCU, | |
1615 | 2, 2, 2, 2 }, | |
1616 | ||
1617 | /* Deprecated in MIPS64r5, but we don't implement that yet. */ | |
1618 | { "mdmx", ASE_MDMX, 0, | |
1619 | OPTION_MDMX, OPTION_NO_MDMX, | |
1620 | -1, 1, -1, -1 }, | |
1621 | ||
1622 | /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */ | |
1623 | { "mips3d", ASE_MIPS3D, 0, | |
1624 | OPTION_MIPS3D, OPTION_NO_MIPS3D, | |
1625 | 2, 1, -1, -1 }, | |
1626 | ||
1627 | { "mt", ASE_MT, 0, | |
1628 | OPTION_MT, OPTION_NO_MT, | |
1629 | 2, 2, -1, -1 }, | |
1630 | ||
1631 | { "smartmips", ASE_SMARTMIPS, 0, | |
1632 | OPTION_SMARTMIPS, OPTION_NO_SMARTMIPS, | |
1633 | 1, -1, -1, -1 }, | |
1634 | ||
1635 | { "virt", ASE_VIRT, ASE_VIRT64, | |
1636 | OPTION_VIRT, OPTION_NO_VIRT, | |
1637 | 2, 2, 2, 2 } | |
1638 | }; | |
1639 | ||
1640 | /* The set of ASEs that require -mfp64. */ | |
1641 | #define FP64_ASES (ASE_MIPS3D | ASE_MDMX) | |
1642 | ||
1643 | /* Groups of ASE_* flags that represent different revisions of an ASE. */ | |
1644 | static const unsigned int mips_ase_groups[] = { | |
1645 | ASE_DSP | ASE_DSPR2 | |
1646 | }; | |
1647 | \f | |
252b5132 RH |
1648 | /* Pseudo-op table. |
1649 | ||
1650 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
1651 | should be defined here, but are currently unsupported: .alias, | |
1652 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
1653 | ||
1654 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1655 | specific to the type of debugging information being generated, and | |
1656 | should be defined by the object format: .aent, .begin, .bend, | |
1657 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
1658 | .vreg. | |
1659 | ||
1660 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1661 | not MIPS CPU specific, but are also not specific to the object file | |
1662 | format. This file is probably the best place to define them, but | |
d84bcf09 | 1663 | they are not currently supported: .asm0, .endr, .lab, .struct. */ |
252b5132 | 1664 | |
e972090a NC |
1665 | static const pseudo_typeS mips_pseudo_table[] = |
1666 | { | |
beae10d5 | 1667 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1668 | {"option", s_option, 0}, |
1669 | {"set", s_mipsset, 0}, | |
1670 | {"rdata", s_change_sec, 'r'}, | |
1671 | {"sdata", s_change_sec, 's'}, | |
1672 | {"livereg", s_ignore, 0}, | |
1673 | {"abicalls", s_abicalls, 0}, | |
1674 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1675 | {"cpsetup", s_cpsetup, 0}, |
1676 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1677 | {"cprestore", s_cprestore, 0}, |
6478892d | 1678 | {"cpreturn", s_cpreturn, 0}, |
741d6ea8 JM |
1679 | {"dtprelword", s_dtprelword, 0}, |
1680 | {"dtpreldword", s_dtpreldword, 0}, | |
d0f13682 CLT |
1681 | {"tprelword", s_tprelword, 0}, |
1682 | {"tpreldword", s_tpreldword, 0}, | |
6478892d | 1683 | {"gpvalue", s_gpvalue, 0}, |
252b5132 | 1684 | {"gpword", s_gpword, 0}, |
10181a0d | 1685 | {"gpdword", s_gpdword, 0}, |
a3f278e2 | 1686 | {"ehword", s_ehword, 0}, |
252b5132 RH |
1687 | {"cpadd", s_cpadd, 0}, |
1688 | {"insn", s_insn, 0}, | |
ba92f887 | 1689 | {"nan", s_nan, 0}, |
252b5132 | 1690 | |
beae10d5 | 1691 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 | 1692 | chips. */ |
38a57ae7 | 1693 | {"asciiz", stringer, 8 + 1}, |
252b5132 RH |
1694 | {"bss", s_change_sec, 'b'}, |
1695 | {"err", s_err, 0}, | |
1696 | {"half", s_cons, 1}, | |
1697 | {"dword", s_cons, 3}, | |
1698 | {"weakext", s_mips_weakext, 0}, | |
7c752c2a TS |
1699 | {"origin", s_org, 0}, |
1700 | {"repeat", s_rept, 0}, | |
252b5132 | 1701 | |
998b3c36 MR |
1702 | /* For MIPS this is non-standard, but we define it for consistency. */ |
1703 | {"sbss", s_change_sec, 'B'}, | |
1704 | ||
beae10d5 | 1705 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1706 | here for one reason or another. */ |
1707 | {"align", s_align, 0}, | |
1708 | {"byte", s_cons, 0}, | |
1709 | {"data", s_change_sec, 'd'}, | |
1710 | {"double", s_float_cons, 'd'}, | |
1711 | {"float", s_float_cons, 'f'}, | |
1712 | {"globl", s_mips_globl, 0}, | |
1713 | {"global", s_mips_globl, 0}, | |
1714 | {"hword", s_cons, 1}, | |
1715 | {"int", s_cons, 2}, | |
1716 | {"long", s_cons, 2}, | |
1717 | {"octa", s_cons, 4}, | |
1718 | {"quad", s_cons, 3}, | |
cca86cc8 | 1719 | {"section", s_change_section, 0}, |
252b5132 RH |
1720 | {"short", s_cons, 1}, |
1721 | {"single", s_float_cons, 'f'}, | |
754e2bb9 | 1722 | {"stabd", s_mips_stab, 'd'}, |
252b5132 | 1723 | {"stabn", s_mips_stab, 'n'}, |
754e2bb9 | 1724 | {"stabs", s_mips_stab, 's'}, |
252b5132 RH |
1725 | {"text", s_change_sec, 't'}, |
1726 | {"word", s_cons, 2}, | |
add56521 | 1727 | |
add56521 | 1728 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1729 | |
43841e91 | 1730 | { NULL, NULL, 0 }, |
252b5132 RH |
1731 | }; |
1732 | ||
e972090a NC |
1733 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1734 | { | |
beae10d5 KH |
1735 | /* These pseudo-ops should be defined by the object file format. |
1736 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1737 | {"aent", s_mips_ent, 1}, |
1738 | {"bgnb", s_ignore, 0}, | |
1739 | {"end", s_mips_end, 0}, | |
1740 | {"endb", s_ignore, 0}, | |
1741 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1742 | {"file", s_mips_file, 0}, |
252b5132 RH |
1743 | {"fmask", s_mips_mask, 'F'}, |
1744 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1745 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1746 | {"mask", s_mips_mask, 'R'}, |
1747 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1748 | { NULL, NULL, 0 }, |
252b5132 RH |
1749 | }; |
1750 | ||
3ae8dd8d MR |
1751 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
1752 | purpose of the `.dc.a' internal pseudo-op. */ | |
1753 | ||
1754 | int | |
1755 | mips_address_bytes (void) | |
1756 | { | |
1757 | return HAVE_64BIT_ADDRESSES ? 8 : 4; | |
1758 | } | |
1759 | ||
17a2f251 | 1760 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1761 | |
1762 | void | |
17a2f251 | 1763 | mips_pop_insert (void) |
252b5132 RH |
1764 | { |
1765 | pop_insert (mips_pseudo_table); | |
1766 | if (! ECOFF_DEBUGGING) | |
1767 | pop_insert (mips_nonecoff_pseudo_table); | |
1768 | } | |
1769 | \f | |
1770 | /* Symbols labelling the current insn. */ | |
1771 | ||
e972090a NC |
1772 | struct insn_label_list |
1773 | { | |
252b5132 RH |
1774 | struct insn_label_list *next; |
1775 | symbolS *label; | |
1776 | }; | |
1777 | ||
252b5132 | 1778 | static struct insn_label_list *free_insn_labels; |
742a56fe | 1779 | #define label_list tc_segment_info_data.labels |
252b5132 | 1780 | |
17a2f251 | 1781 | static void mips_clear_insn_labels (void); |
df58fc94 RS |
1782 | static void mips_mark_labels (void); |
1783 | static void mips_compressed_mark_labels (void); | |
252b5132 RH |
1784 | |
1785 | static inline void | |
17a2f251 | 1786 | mips_clear_insn_labels (void) |
252b5132 RH |
1787 | { |
1788 | register struct insn_label_list **pl; | |
a8dbcb85 | 1789 | segment_info_type *si; |
252b5132 | 1790 | |
a8dbcb85 TS |
1791 | if (now_seg) |
1792 | { | |
1793 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1794 | ; | |
1795 | ||
1796 | si = seg_info (now_seg); | |
1797 | *pl = si->label_list; | |
1798 | si->label_list = NULL; | |
1799 | } | |
252b5132 | 1800 | } |
a8dbcb85 | 1801 | |
df58fc94 RS |
1802 | /* Mark instruction labels in MIPS16/microMIPS mode. */ |
1803 | ||
1804 | static inline void | |
1805 | mips_mark_labels (void) | |
1806 | { | |
1807 | if (HAVE_CODE_COMPRESSION) | |
1808 | mips_compressed_mark_labels (); | |
1809 | } | |
252b5132 RH |
1810 | \f |
1811 | static char *expr_end; | |
1812 | ||
77bd4346 RS |
1813 | /* Expressions which appear in macro instructions. These are set by |
1814 | mips_ip and read by macro. */ | |
252b5132 RH |
1815 | |
1816 | static expressionS imm_expr; | |
5f74bc13 | 1817 | static expressionS imm2_expr; |
252b5132 | 1818 | |
77bd4346 RS |
1819 | /* The relocatable field in an instruction and the relocs associated |
1820 | with it. These variables are used for instructions like LUI and | |
1821 | JAL as well as true offsets. They are also used for address | |
1822 | operands in macros. */ | |
252b5132 | 1823 | |
77bd4346 | 1824 | static expressionS offset_expr; |
f6688943 TS |
1825 | static bfd_reloc_code_real_type offset_reloc[3] |
1826 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1827 | |
df58fc94 RS |
1828 | /* This is set to the resulting size of the instruction to be produced |
1829 | by mips16_ip if an explicit extension is used or by mips_ip if an | |
1830 | explicit size is supplied. */ | |
252b5132 | 1831 | |
df58fc94 | 1832 | static unsigned int forced_insn_length; |
252b5132 | 1833 | |
e1b47bd5 RS |
1834 | /* True if we are assembling an instruction. All dot symbols defined during |
1835 | this time should be treated as code labels. */ | |
1836 | ||
1837 | static bfd_boolean mips_assembling_insn; | |
1838 | ||
ecb4347a DJ |
1839 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1840 | ECOFF debugging. */ | |
252b5132 RH |
1841 | |
1842 | static segT pdr_seg; | |
252b5132 | 1843 | |
e013f690 TS |
1844 | /* The default target format to use. */ |
1845 | ||
aeffff67 RS |
1846 | #if defined (TE_FreeBSD) |
1847 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd" | |
1848 | #elif defined (TE_TMIPS) | |
1849 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips" | |
1850 | #else | |
1851 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips" | |
1852 | #endif | |
1853 | ||
e013f690 | 1854 | const char * |
17a2f251 | 1855 | mips_target_format (void) |
e013f690 TS |
1856 | { |
1857 | switch (OUTPUT_FLAVOR) | |
1858 | { | |
e013f690 | 1859 | case bfd_target_elf_flavour: |
0a44bf69 RS |
1860 | #ifdef TE_VXWORKS |
1861 | if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI) | |
1862 | return (target_big_endian | |
1863 | ? "elf32-bigmips-vxworks" | |
1864 | : "elf32-littlemips-vxworks"); | |
1865 | #endif | |
e013f690 | 1866 | return (target_big_endian |
cfe86eaa | 1867 | ? (HAVE_64BIT_OBJECTS |
aeffff67 | 1868 | ? ELF_TARGET ("elf64-", "big") |
cfe86eaa | 1869 | : (HAVE_NEWABI |
aeffff67 RS |
1870 | ? ELF_TARGET ("elf32-n", "big") |
1871 | : ELF_TARGET ("elf32-", "big"))) | |
cfe86eaa | 1872 | : (HAVE_64BIT_OBJECTS |
aeffff67 | 1873 | ? ELF_TARGET ("elf64-", "little") |
cfe86eaa | 1874 | : (HAVE_NEWABI |
aeffff67 RS |
1875 | ? ELF_TARGET ("elf32-n", "little") |
1876 | : ELF_TARGET ("elf32-", "little")))); | |
e013f690 TS |
1877 | default: |
1878 | abort (); | |
1879 | return NULL; | |
1880 | } | |
1881 | } | |
1882 | ||
c6278170 RS |
1883 | /* Return the ISA revision that is currently in use, or 0 if we are |
1884 | generating code for MIPS V or below. */ | |
1885 | ||
1886 | static int | |
1887 | mips_isa_rev (void) | |
1888 | { | |
1889 | if (mips_opts.isa == ISA_MIPS32R2 || mips_opts.isa == ISA_MIPS64R2) | |
1890 | return 2; | |
1891 | ||
1892 | /* microMIPS implies revision 2 or above. */ | |
1893 | if (mips_opts.micromips) | |
1894 | return 2; | |
1895 | ||
1896 | if (mips_opts.isa == ISA_MIPS32 || mips_opts.isa == ISA_MIPS64) | |
1897 | return 1; | |
1898 | ||
1899 | return 0; | |
1900 | } | |
1901 | ||
1902 | /* Return the mask of all ASEs that are revisions of those in FLAGS. */ | |
1903 | ||
1904 | static unsigned int | |
1905 | mips_ase_mask (unsigned int flags) | |
1906 | { | |
1907 | unsigned int i; | |
1908 | ||
1909 | for (i = 0; i < ARRAY_SIZE (mips_ase_groups); i++) | |
1910 | if (flags & mips_ase_groups[i]) | |
1911 | flags |= mips_ase_groups[i]; | |
1912 | return flags; | |
1913 | } | |
1914 | ||
1915 | /* Check whether the current ISA supports ASE. Issue a warning if | |
1916 | appropriate. */ | |
1917 | ||
1918 | static void | |
1919 | mips_check_isa_supports_ase (const struct mips_ase *ase) | |
1920 | { | |
1921 | const char *base; | |
1922 | int min_rev, size; | |
1923 | static unsigned int warned_isa; | |
1924 | static unsigned int warned_fp32; | |
1925 | ||
1926 | if (ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
1927 | min_rev = mips_opts.micromips ? ase->micromips64_rev : ase->mips64_rev; | |
1928 | else | |
1929 | min_rev = mips_opts.micromips ? ase->micromips32_rev : ase->mips32_rev; | |
1930 | if ((min_rev < 0 || mips_isa_rev () < min_rev) | |
1931 | && (warned_isa & ase->flags) != ase->flags) | |
1932 | { | |
1933 | warned_isa |= ase->flags; | |
1934 | base = mips_opts.micromips ? "microMIPS" : "MIPS"; | |
1935 | size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32; | |
1936 | if (min_rev < 0) | |
1937 | as_warn (_("The %d-bit %s architecture does not support the" | |
1938 | " `%s' extension"), size, base, ase->name); | |
1939 | else | |
1940 | as_warn (_("The `%s' extension requires %s%d revision %d or greater"), | |
1941 | ase->name, base, size, min_rev); | |
1942 | } | |
1943 | if ((ase->flags & FP64_ASES) | |
1944 | && mips_opts.fp32 | |
1945 | && (warned_fp32 & ase->flags) != ase->flags) | |
1946 | { | |
1947 | warned_fp32 |= ase->flags; | |
1948 | as_warn (_("The `%s' extension requires 64-bit FPRs"), ase->name); | |
1949 | } | |
1950 | } | |
1951 | ||
1952 | /* Check all enabled ASEs to see whether they are supported by the | |
1953 | chosen architecture. */ | |
1954 | ||
1955 | static void | |
1956 | mips_check_isa_supports_ases (void) | |
1957 | { | |
1958 | unsigned int i, mask; | |
1959 | ||
1960 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
1961 | { | |
1962 | mask = mips_ase_mask (mips_ases[i].flags); | |
1963 | if ((mips_opts.ase & mask) == mips_ases[i].flags) | |
1964 | mips_check_isa_supports_ase (&mips_ases[i]); | |
1965 | } | |
1966 | } | |
1967 | ||
1968 | /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags | |
1969 | that were affected. */ | |
1970 | ||
1971 | static unsigned int | |
1972 | mips_set_ase (const struct mips_ase *ase, bfd_boolean enabled_p) | |
1973 | { | |
1974 | unsigned int mask; | |
1975 | ||
1976 | mask = mips_ase_mask (ase->flags); | |
1977 | mips_opts.ase &= ~mask; | |
1978 | if (enabled_p) | |
1979 | mips_opts.ase |= ase->flags; | |
1980 | return mask; | |
1981 | } | |
1982 | ||
1983 | /* Return the ASE called NAME, or null if none. */ | |
1984 | ||
1985 | static const struct mips_ase * | |
1986 | mips_lookup_ase (const char *name) | |
1987 | { | |
1988 | unsigned int i; | |
1989 | ||
1990 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
1991 | if (strcmp (name, mips_ases[i].name) == 0) | |
1992 | return &mips_ases[i]; | |
1993 | return NULL; | |
1994 | } | |
1995 | ||
df58fc94 RS |
1996 | /* Return the length of a microMIPS instruction in bytes. If bits of |
1997 | the mask beyond the low 16 are 0, then it is a 16-bit instruction. | |
1998 | Otherwise assume a 32-bit instruction; 48-bit instructions (0x1f | |
1999 | major opcode) will require further modifications to the opcode | |
2000 | table. */ | |
2001 | ||
2002 | static inline unsigned int | |
2003 | micromips_insn_length (const struct mips_opcode *mo) | |
2004 | { | |
2005 | return (mo->mask >> 16) == 0 ? 2 : 4; | |
2006 | } | |
2007 | ||
5c04167a RS |
2008 | /* Return the length of MIPS16 instruction OPCODE. */ |
2009 | ||
2010 | static inline unsigned int | |
2011 | mips16_opcode_length (unsigned long opcode) | |
2012 | { | |
2013 | return (opcode >> 16) == 0 ? 2 : 4; | |
2014 | } | |
2015 | ||
1e915849 RS |
2016 | /* Return the length of instruction INSN. */ |
2017 | ||
2018 | static inline unsigned int | |
2019 | insn_length (const struct mips_cl_insn *insn) | |
2020 | { | |
df58fc94 RS |
2021 | if (mips_opts.micromips) |
2022 | return micromips_insn_length (insn->insn_mo); | |
2023 | else if (mips_opts.mips16) | |
5c04167a | 2024 | return mips16_opcode_length (insn->insn_opcode); |
df58fc94 | 2025 | else |
1e915849 | 2026 | return 4; |
1e915849 RS |
2027 | } |
2028 | ||
2029 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
2030 | ||
2031 | static void | |
2032 | create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) | |
2033 | { | |
2034 | size_t i; | |
2035 | ||
2036 | insn->insn_mo = mo; | |
1e915849 RS |
2037 | insn->insn_opcode = mo->match; |
2038 | insn->frag = NULL; | |
2039 | insn->where = 0; | |
2040 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
2041 | insn->fixp[i] = NULL; | |
2042 | insn->fixed_p = (mips_opts.noreorder > 0); | |
2043 | insn->noreorder_p = (mips_opts.noreorder > 0); | |
2044 | insn->mips16_absolute_jump_p = 0; | |
15be625d | 2045 | insn->complete_p = 0; |
e407c74b | 2046 | insn->cleared_p = 0; |
1e915849 RS |
2047 | } |
2048 | ||
df58fc94 | 2049 | /* Record the current MIPS16/microMIPS mode in now_seg. */ |
742a56fe RS |
2050 | |
2051 | static void | |
df58fc94 | 2052 | mips_record_compressed_mode (void) |
742a56fe RS |
2053 | { |
2054 | segment_info_type *si; | |
2055 | ||
2056 | si = seg_info (now_seg); | |
2057 | if (si->tc_segment_info_data.mips16 != mips_opts.mips16) | |
2058 | si->tc_segment_info_data.mips16 = mips_opts.mips16; | |
df58fc94 RS |
2059 | if (si->tc_segment_info_data.micromips != mips_opts.micromips) |
2060 | si->tc_segment_info_data.micromips = mips_opts.micromips; | |
742a56fe RS |
2061 | } |
2062 | ||
4d68580a RS |
2063 | /* Read a standard MIPS instruction from BUF. */ |
2064 | ||
2065 | static unsigned long | |
2066 | read_insn (char *buf) | |
2067 | { | |
2068 | if (target_big_endian) | |
2069 | return bfd_getb32 ((bfd_byte *) buf); | |
2070 | else | |
2071 | return bfd_getl32 ((bfd_byte *) buf); | |
2072 | } | |
2073 | ||
2074 | /* Write standard MIPS instruction INSN to BUF. Return a pointer to | |
2075 | the next byte. */ | |
2076 | ||
2077 | static char * | |
2078 | write_insn (char *buf, unsigned int insn) | |
2079 | { | |
2080 | md_number_to_chars (buf, insn, 4); | |
2081 | return buf + 4; | |
2082 | } | |
2083 | ||
2084 | /* Read a microMIPS or MIPS16 opcode from BUF, given that it | |
2085 | has length LENGTH. */ | |
2086 | ||
2087 | static unsigned long | |
2088 | read_compressed_insn (char *buf, unsigned int length) | |
2089 | { | |
2090 | unsigned long insn; | |
2091 | unsigned int i; | |
2092 | ||
2093 | insn = 0; | |
2094 | for (i = 0; i < length; i += 2) | |
2095 | { | |
2096 | insn <<= 16; | |
2097 | if (target_big_endian) | |
2098 | insn |= bfd_getb16 ((char *) buf); | |
2099 | else | |
2100 | insn |= bfd_getl16 ((char *) buf); | |
2101 | buf += 2; | |
2102 | } | |
2103 | return insn; | |
2104 | } | |
2105 | ||
5c04167a RS |
2106 | /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the |
2107 | instruction is LENGTH bytes long. Return a pointer to the next byte. */ | |
2108 | ||
2109 | static char * | |
2110 | write_compressed_insn (char *buf, unsigned int insn, unsigned int length) | |
2111 | { | |
2112 | unsigned int i; | |
2113 | ||
2114 | for (i = 0; i < length; i += 2) | |
2115 | md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2); | |
2116 | return buf + length; | |
2117 | } | |
2118 | ||
1e915849 RS |
2119 | /* Install INSN at the location specified by its "frag" and "where" fields. */ |
2120 | ||
2121 | static void | |
2122 | install_insn (const struct mips_cl_insn *insn) | |
2123 | { | |
2124 | char *f = insn->frag->fr_literal + insn->where; | |
5c04167a RS |
2125 | if (HAVE_CODE_COMPRESSION) |
2126 | write_compressed_insn (f, insn->insn_opcode, insn_length (insn)); | |
1e915849 | 2127 | else |
4d68580a | 2128 | write_insn (f, insn->insn_opcode); |
df58fc94 | 2129 | mips_record_compressed_mode (); |
1e915849 RS |
2130 | } |
2131 | ||
2132 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
2133 | and install the opcode in the new location. */ | |
2134 | ||
2135 | static void | |
2136 | move_insn (struct mips_cl_insn *insn, fragS *frag, long where) | |
2137 | { | |
2138 | size_t i; | |
2139 | ||
2140 | insn->frag = frag; | |
2141 | insn->where = where; | |
2142 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
2143 | if (insn->fixp[i] != NULL) | |
2144 | { | |
2145 | insn->fixp[i]->fx_frag = frag; | |
2146 | insn->fixp[i]->fx_where = where; | |
2147 | } | |
2148 | install_insn (insn); | |
2149 | } | |
2150 | ||
2151 | /* Add INSN to the end of the output. */ | |
2152 | ||
2153 | static void | |
2154 | add_fixed_insn (struct mips_cl_insn *insn) | |
2155 | { | |
2156 | char *f = frag_more (insn_length (insn)); | |
2157 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
2158 | } | |
2159 | ||
2160 | /* Start a variant frag and move INSN to the start of the variant part, | |
2161 | marking it as fixed. The other arguments are as for frag_var. */ | |
2162 | ||
2163 | static void | |
2164 | add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, | |
2165 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
2166 | { | |
2167 | frag_grow (max_chars); | |
2168 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
2169 | insn->fixed_p = 1; | |
2170 | frag_var (rs_machine_dependent, max_chars, var, | |
2171 | subtype, symbol, offset, NULL); | |
2172 | } | |
2173 | ||
2174 | /* Insert N copies of INSN into the history buffer, starting at | |
2175 | position FIRST. Neither FIRST nor N need to be clipped. */ | |
2176 | ||
2177 | static void | |
2178 | insert_into_history (unsigned int first, unsigned int n, | |
2179 | const struct mips_cl_insn *insn) | |
2180 | { | |
2181 | if (mips_relax.sequence != 2) | |
2182 | { | |
2183 | unsigned int i; | |
2184 | ||
2185 | for (i = ARRAY_SIZE (history); i-- > first;) | |
2186 | if (i >= first + n) | |
2187 | history[i] = history[i - n]; | |
2188 | else | |
2189 | history[i] = *insn; | |
2190 | } | |
2191 | } | |
2192 | ||
71400594 RS |
2193 | /* Initialize vr4120_conflicts. There is a bit of duplication here: |
2194 | the idea is to make it obvious at a glance that each errata is | |
2195 | included. */ | |
2196 | ||
2197 | static void | |
2198 | init_vr4120_conflicts (void) | |
2199 | { | |
2200 | #define CONFLICT(FIRST, SECOND) \ | |
2201 | vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND | |
2202 | ||
2203 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
2204 | CONFLICT (MACC, DIV); | |
2205 | CONFLICT (DMACC, DIV); | |
2206 | ||
2207 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ | |
2208 | CONFLICT (DMULT, DMULT); | |
2209 | CONFLICT (DMULT, DMACC); | |
2210 | CONFLICT (DMACC, DMULT); | |
2211 | CONFLICT (DMACC, DMACC); | |
2212 | ||
2213 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
2214 | CONFLICT (MACC, MTHILO); | |
2215 | CONFLICT (DMACC, MTHILO); | |
2216 | ||
2217 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU | |
2218 | instruction is executed immediately after a MACC or DMACC | |
2219 | instruction, the result of [either instruction] is incorrect." */ | |
2220 | CONFLICT (MACC, MULT); | |
2221 | CONFLICT (MACC, DMULT); | |
2222 | CONFLICT (DMACC, MULT); | |
2223 | CONFLICT (DMACC, DMULT); | |
2224 | ||
2225 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
2226 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
2227 | DDIV or DDIVU instruction, the result of the MACC or | |
2228 | DMACC instruction is incorrect.". */ | |
2229 | CONFLICT (DMULT, MACC); | |
2230 | CONFLICT (DMULT, DMACC); | |
2231 | CONFLICT (DIV, MACC); | |
2232 | CONFLICT (DIV, DMACC); | |
2233 | ||
2234 | #undef CONFLICT | |
2235 | } | |
2236 | ||
707bfff6 TS |
2237 | struct regname { |
2238 | const char *name; | |
2239 | unsigned int num; | |
2240 | }; | |
2241 | ||
2242 | #define RTYPE_MASK 0x1ff00 | |
2243 | #define RTYPE_NUM 0x00100 | |
2244 | #define RTYPE_FPU 0x00200 | |
2245 | #define RTYPE_FCC 0x00400 | |
2246 | #define RTYPE_VEC 0x00800 | |
2247 | #define RTYPE_GP 0x01000 | |
2248 | #define RTYPE_CP0 0x02000 | |
2249 | #define RTYPE_PC 0x04000 | |
2250 | #define RTYPE_ACC 0x08000 | |
2251 | #define RTYPE_CCC 0x10000 | |
2252 | #define RNUM_MASK 0x000ff | |
2253 | #define RWARN 0x80000 | |
2254 | ||
2255 | #define GENERIC_REGISTER_NUMBERS \ | |
2256 | {"$0", RTYPE_NUM | 0}, \ | |
2257 | {"$1", RTYPE_NUM | 1}, \ | |
2258 | {"$2", RTYPE_NUM | 2}, \ | |
2259 | {"$3", RTYPE_NUM | 3}, \ | |
2260 | {"$4", RTYPE_NUM | 4}, \ | |
2261 | {"$5", RTYPE_NUM | 5}, \ | |
2262 | {"$6", RTYPE_NUM | 6}, \ | |
2263 | {"$7", RTYPE_NUM | 7}, \ | |
2264 | {"$8", RTYPE_NUM | 8}, \ | |
2265 | {"$9", RTYPE_NUM | 9}, \ | |
2266 | {"$10", RTYPE_NUM | 10}, \ | |
2267 | {"$11", RTYPE_NUM | 11}, \ | |
2268 | {"$12", RTYPE_NUM | 12}, \ | |
2269 | {"$13", RTYPE_NUM | 13}, \ | |
2270 | {"$14", RTYPE_NUM | 14}, \ | |
2271 | {"$15", RTYPE_NUM | 15}, \ | |
2272 | {"$16", RTYPE_NUM | 16}, \ | |
2273 | {"$17", RTYPE_NUM | 17}, \ | |
2274 | {"$18", RTYPE_NUM | 18}, \ | |
2275 | {"$19", RTYPE_NUM | 19}, \ | |
2276 | {"$20", RTYPE_NUM | 20}, \ | |
2277 | {"$21", RTYPE_NUM | 21}, \ | |
2278 | {"$22", RTYPE_NUM | 22}, \ | |
2279 | {"$23", RTYPE_NUM | 23}, \ | |
2280 | {"$24", RTYPE_NUM | 24}, \ | |
2281 | {"$25", RTYPE_NUM | 25}, \ | |
2282 | {"$26", RTYPE_NUM | 26}, \ | |
2283 | {"$27", RTYPE_NUM | 27}, \ | |
2284 | {"$28", RTYPE_NUM | 28}, \ | |
2285 | {"$29", RTYPE_NUM | 29}, \ | |
2286 | {"$30", RTYPE_NUM | 30}, \ | |
2287 | {"$31", RTYPE_NUM | 31} | |
2288 | ||
2289 | #define FPU_REGISTER_NAMES \ | |
2290 | {"$f0", RTYPE_FPU | 0}, \ | |
2291 | {"$f1", RTYPE_FPU | 1}, \ | |
2292 | {"$f2", RTYPE_FPU | 2}, \ | |
2293 | {"$f3", RTYPE_FPU | 3}, \ | |
2294 | {"$f4", RTYPE_FPU | 4}, \ | |
2295 | {"$f5", RTYPE_FPU | 5}, \ | |
2296 | {"$f6", RTYPE_FPU | 6}, \ | |
2297 | {"$f7", RTYPE_FPU | 7}, \ | |
2298 | {"$f8", RTYPE_FPU | 8}, \ | |
2299 | {"$f9", RTYPE_FPU | 9}, \ | |
2300 | {"$f10", RTYPE_FPU | 10}, \ | |
2301 | {"$f11", RTYPE_FPU | 11}, \ | |
2302 | {"$f12", RTYPE_FPU | 12}, \ | |
2303 | {"$f13", RTYPE_FPU | 13}, \ | |
2304 | {"$f14", RTYPE_FPU | 14}, \ | |
2305 | {"$f15", RTYPE_FPU | 15}, \ | |
2306 | {"$f16", RTYPE_FPU | 16}, \ | |
2307 | {"$f17", RTYPE_FPU | 17}, \ | |
2308 | {"$f18", RTYPE_FPU | 18}, \ | |
2309 | {"$f19", RTYPE_FPU | 19}, \ | |
2310 | {"$f20", RTYPE_FPU | 20}, \ | |
2311 | {"$f21", RTYPE_FPU | 21}, \ | |
2312 | {"$f22", RTYPE_FPU | 22}, \ | |
2313 | {"$f23", RTYPE_FPU | 23}, \ | |
2314 | {"$f24", RTYPE_FPU | 24}, \ | |
2315 | {"$f25", RTYPE_FPU | 25}, \ | |
2316 | {"$f26", RTYPE_FPU | 26}, \ | |
2317 | {"$f27", RTYPE_FPU | 27}, \ | |
2318 | {"$f28", RTYPE_FPU | 28}, \ | |
2319 | {"$f29", RTYPE_FPU | 29}, \ | |
2320 | {"$f30", RTYPE_FPU | 30}, \ | |
2321 | {"$f31", RTYPE_FPU | 31} | |
2322 | ||
2323 | #define FPU_CONDITION_CODE_NAMES \ | |
2324 | {"$fcc0", RTYPE_FCC | 0}, \ | |
2325 | {"$fcc1", RTYPE_FCC | 1}, \ | |
2326 | {"$fcc2", RTYPE_FCC | 2}, \ | |
2327 | {"$fcc3", RTYPE_FCC | 3}, \ | |
2328 | {"$fcc4", RTYPE_FCC | 4}, \ | |
2329 | {"$fcc5", RTYPE_FCC | 5}, \ | |
2330 | {"$fcc6", RTYPE_FCC | 6}, \ | |
2331 | {"$fcc7", RTYPE_FCC | 7} | |
2332 | ||
2333 | #define COPROC_CONDITION_CODE_NAMES \ | |
2334 | {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \ | |
2335 | {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \ | |
2336 | {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \ | |
2337 | {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \ | |
2338 | {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \ | |
2339 | {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \ | |
2340 | {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \ | |
2341 | {"$cc7", RTYPE_FCC | RTYPE_CCC | 7} | |
2342 | ||
2343 | #define N32N64_SYMBOLIC_REGISTER_NAMES \ | |
2344 | {"$a4", RTYPE_GP | 8}, \ | |
2345 | {"$a5", RTYPE_GP | 9}, \ | |
2346 | {"$a6", RTYPE_GP | 10}, \ | |
2347 | {"$a7", RTYPE_GP | 11}, \ | |
2348 | {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \ | |
2349 | {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \ | |
2350 | {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \ | |
2351 | {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \ | |
2352 | {"$t0", RTYPE_GP | 12}, \ | |
2353 | {"$t1", RTYPE_GP | 13}, \ | |
2354 | {"$t2", RTYPE_GP | 14}, \ | |
2355 | {"$t3", RTYPE_GP | 15} | |
2356 | ||
2357 | #define O32_SYMBOLIC_REGISTER_NAMES \ | |
2358 | {"$t0", RTYPE_GP | 8}, \ | |
2359 | {"$t1", RTYPE_GP | 9}, \ | |
2360 | {"$t2", RTYPE_GP | 10}, \ | |
2361 | {"$t3", RTYPE_GP | 11}, \ | |
2362 | {"$t4", RTYPE_GP | 12}, \ | |
2363 | {"$t5", RTYPE_GP | 13}, \ | |
2364 | {"$t6", RTYPE_GP | 14}, \ | |
2365 | {"$t7", RTYPE_GP | 15}, \ | |
2366 | {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \ | |
2367 | {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \ | |
2368 | {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \ | |
2369 | {"$ta3", RTYPE_GP | 15} /* alias for $t7 */ | |
2370 | ||
2371 | /* Remaining symbolic register names */ | |
2372 | #define SYMBOLIC_REGISTER_NAMES \ | |
2373 | {"$zero", RTYPE_GP | 0}, \ | |
2374 | {"$at", RTYPE_GP | 1}, \ | |
2375 | {"$AT", RTYPE_GP | 1}, \ | |
2376 | {"$v0", RTYPE_GP | 2}, \ | |
2377 | {"$v1", RTYPE_GP | 3}, \ | |
2378 | {"$a0", RTYPE_GP | 4}, \ | |
2379 | {"$a1", RTYPE_GP | 5}, \ | |
2380 | {"$a2", RTYPE_GP | 6}, \ | |
2381 | {"$a3", RTYPE_GP | 7}, \ | |
2382 | {"$s0", RTYPE_GP | 16}, \ | |
2383 | {"$s1", RTYPE_GP | 17}, \ | |
2384 | {"$s2", RTYPE_GP | 18}, \ | |
2385 | {"$s3", RTYPE_GP | 19}, \ | |
2386 | {"$s4", RTYPE_GP | 20}, \ | |
2387 | {"$s5", RTYPE_GP | 21}, \ | |
2388 | {"$s6", RTYPE_GP | 22}, \ | |
2389 | {"$s7", RTYPE_GP | 23}, \ | |
2390 | {"$t8", RTYPE_GP | 24}, \ | |
2391 | {"$t9", RTYPE_GP | 25}, \ | |
2392 | {"$k0", RTYPE_GP | 26}, \ | |
2393 | {"$kt0", RTYPE_GP | 26}, \ | |
2394 | {"$k1", RTYPE_GP | 27}, \ | |
2395 | {"$kt1", RTYPE_GP | 27}, \ | |
2396 | {"$gp", RTYPE_GP | 28}, \ | |
2397 | {"$sp", RTYPE_GP | 29}, \ | |
2398 | {"$s8", RTYPE_GP | 30}, \ | |
2399 | {"$fp", RTYPE_GP | 30}, \ | |
2400 | {"$ra", RTYPE_GP | 31} | |
2401 | ||
2402 | #define MIPS16_SPECIAL_REGISTER_NAMES \ | |
2403 | {"$pc", RTYPE_PC | 0} | |
2404 | ||
2405 | #define MDMX_VECTOR_REGISTER_NAMES \ | |
2406 | /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \ | |
2407 | /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \ | |
2408 | {"$v2", RTYPE_VEC | 2}, \ | |
2409 | {"$v3", RTYPE_VEC | 3}, \ | |
2410 | {"$v4", RTYPE_VEC | 4}, \ | |
2411 | {"$v5", RTYPE_VEC | 5}, \ | |
2412 | {"$v6", RTYPE_VEC | 6}, \ | |
2413 | {"$v7", RTYPE_VEC | 7}, \ | |
2414 | {"$v8", RTYPE_VEC | 8}, \ | |
2415 | {"$v9", RTYPE_VEC | 9}, \ | |
2416 | {"$v10", RTYPE_VEC | 10}, \ | |
2417 | {"$v11", RTYPE_VEC | 11}, \ | |
2418 | {"$v12", RTYPE_VEC | 12}, \ | |
2419 | {"$v13", RTYPE_VEC | 13}, \ | |
2420 | {"$v14", RTYPE_VEC | 14}, \ | |
2421 | {"$v15", RTYPE_VEC | 15}, \ | |
2422 | {"$v16", RTYPE_VEC | 16}, \ | |
2423 | {"$v17", RTYPE_VEC | 17}, \ | |
2424 | {"$v18", RTYPE_VEC | 18}, \ | |
2425 | {"$v19", RTYPE_VEC | 19}, \ | |
2426 | {"$v20", RTYPE_VEC | 20}, \ | |
2427 | {"$v21", RTYPE_VEC | 21}, \ | |
2428 | {"$v22", RTYPE_VEC | 22}, \ | |
2429 | {"$v23", RTYPE_VEC | 23}, \ | |
2430 | {"$v24", RTYPE_VEC | 24}, \ | |
2431 | {"$v25", RTYPE_VEC | 25}, \ | |
2432 | {"$v26", RTYPE_VEC | 26}, \ | |
2433 | {"$v27", RTYPE_VEC | 27}, \ | |
2434 | {"$v28", RTYPE_VEC | 28}, \ | |
2435 | {"$v29", RTYPE_VEC | 29}, \ | |
2436 | {"$v30", RTYPE_VEC | 30}, \ | |
2437 | {"$v31", RTYPE_VEC | 31} | |
2438 | ||
2439 | #define MIPS_DSP_ACCUMULATOR_NAMES \ | |
2440 | {"$ac0", RTYPE_ACC | 0}, \ | |
2441 | {"$ac1", RTYPE_ACC | 1}, \ | |
2442 | {"$ac2", RTYPE_ACC | 2}, \ | |
2443 | {"$ac3", RTYPE_ACC | 3} | |
2444 | ||
2445 | static const struct regname reg_names[] = { | |
2446 | GENERIC_REGISTER_NUMBERS, | |
2447 | FPU_REGISTER_NAMES, | |
2448 | FPU_CONDITION_CODE_NAMES, | |
2449 | COPROC_CONDITION_CODE_NAMES, | |
2450 | ||
2451 | /* The $txx registers depends on the abi, | |
2452 | these will be added later into the symbol table from | |
2453 | one of the tables below once mips_abi is set after | |
2454 | parsing of arguments from the command line. */ | |
2455 | SYMBOLIC_REGISTER_NAMES, | |
2456 | ||
2457 | MIPS16_SPECIAL_REGISTER_NAMES, | |
2458 | MDMX_VECTOR_REGISTER_NAMES, | |
2459 | MIPS_DSP_ACCUMULATOR_NAMES, | |
2460 | {0, 0} | |
2461 | }; | |
2462 | ||
2463 | static const struct regname reg_names_o32[] = { | |
2464 | O32_SYMBOLIC_REGISTER_NAMES, | |
2465 | {0, 0} | |
2466 | }; | |
2467 | ||
2468 | static const struct regname reg_names_n32n64[] = { | |
2469 | N32N64_SYMBOLIC_REGISTER_NAMES, | |
2470 | {0, 0} | |
2471 | }; | |
2472 | ||
df58fc94 RS |
2473 | /* Check if S points at a valid register specifier according to TYPES. |
2474 | If so, then return 1, advance S to consume the specifier and store | |
2475 | the register's number in REGNOP, otherwise return 0. */ | |
2476 | ||
707bfff6 TS |
2477 | static int |
2478 | reg_lookup (char **s, unsigned int types, unsigned int *regnop) | |
2479 | { | |
2480 | symbolS *symbolP; | |
2481 | char *e; | |
2482 | char save_c; | |
2483 | int reg = -1; | |
2484 | ||
2485 | /* Find end of name. */ | |
2486 | e = *s; | |
2487 | if (is_name_beginner (*e)) | |
2488 | ++e; | |
2489 | while (is_part_of_name (*e)) | |
2490 | ++e; | |
2491 | ||
2492 | /* Terminate name. */ | |
2493 | save_c = *e; | |
2494 | *e = '\0'; | |
2495 | ||
2496 | /* Look for a register symbol. */ | |
2497 | if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section) | |
2498 | { | |
2499 | int r = S_GET_VALUE (symbolP); | |
2500 | if (r & types) | |
2501 | reg = r & RNUM_MASK; | |
2502 | else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2)) | |
2503 | /* Convert GP reg $v0/1 to MDMX reg $v0/1! */ | |
2504 | reg = (r & RNUM_MASK) - 2; | |
2505 | } | |
2506 | /* Else see if this is a register defined in an itbl entry. */ | |
2507 | else if ((types & RTYPE_GP) && itbl_have_entries) | |
2508 | { | |
2509 | char *n = *s; | |
2510 | unsigned long r; | |
2511 | ||
2512 | if (*n == '$') | |
2513 | ++n; | |
2514 | if (itbl_get_reg_val (n, &r)) | |
2515 | reg = r & RNUM_MASK; | |
2516 | } | |
2517 | ||
2518 | /* Advance to next token if a register was recognised. */ | |
2519 | if (reg >= 0) | |
2520 | *s = e; | |
2521 | else if (types & RWARN) | |
20203fb9 | 2522 | as_warn (_("Unrecognized register name `%s'"), *s); |
707bfff6 TS |
2523 | |
2524 | *e = save_c; | |
2525 | if (regnop) | |
2526 | *regnop = reg; | |
2527 | return reg >= 0; | |
2528 | } | |
2529 | ||
df58fc94 RS |
2530 | /* Check if S points at a valid register list according to TYPES. |
2531 | If so, then return 1, advance S to consume the list and store | |
2532 | the registers present on the list as a bitmask of ones in REGLISTP, | |
2533 | otherwise return 0. A valid list comprises a comma-separated | |
2534 | enumeration of valid single registers and/or dash-separated | |
2535 | contiguous register ranges as determined by their numbers. | |
2536 | ||
2537 | As a special exception if one of s0-s7 registers is specified as | |
2538 | the range's lower delimiter and s8 (fp) is its upper one, then no | |
2539 | registers whose numbers place them between s7 and s8 (i.e. $24-$29) | |
2309ddf2 | 2540 | are selected; they have to be listed separately if needed. */ |
df58fc94 RS |
2541 | |
2542 | static int | |
2543 | reglist_lookup (char **s, unsigned int types, unsigned int *reglistp) | |
2544 | { | |
2545 | unsigned int reglist = 0; | |
2546 | unsigned int lastregno; | |
2547 | bfd_boolean ok = TRUE; | |
2548 | unsigned int regmask; | |
2309ddf2 | 2549 | char *s_endlist = *s; |
df58fc94 | 2550 | char *s_reset = *s; |
2309ddf2 | 2551 | unsigned int regno; |
df58fc94 RS |
2552 | |
2553 | while (reg_lookup (s, types, ®no)) | |
2554 | { | |
2555 | lastregno = regno; | |
2556 | if (**s == '-') | |
2557 | { | |
2558 | (*s)++; | |
2559 | ok = reg_lookup (s, types, &lastregno); | |
2560 | if (ok && lastregno < regno) | |
2561 | ok = FALSE; | |
2562 | if (!ok) | |
2563 | break; | |
2564 | } | |
2565 | ||
2566 | if (lastregno == FP && regno >= S0 && regno <= S7) | |
2567 | { | |
2568 | lastregno = S7; | |
2569 | reglist |= 1 << FP; | |
2570 | } | |
2571 | regmask = 1 << lastregno; | |
2572 | regmask = (regmask << 1) - 1; | |
2573 | regmask ^= (1 << regno) - 1; | |
2574 | reglist |= regmask; | |
2575 | ||
2309ddf2 | 2576 | s_endlist = *s; |
df58fc94 RS |
2577 | if (**s != ',') |
2578 | break; | |
2579 | (*s)++; | |
2580 | } | |
2581 | ||
2582 | if (ok) | |
2309ddf2 | 2583 | *s = s_endlist; |
df58fc94 RS |
2584 | else |
2585 | *s = s_reset; | |
2586 | if (reglistp) | |
2587 | *reglistp = reglist; | |
2588 | return ok && reglist != 0; | |
2589 | } | |
2590 | ||
e76ff5ab RS |
2591 | static unsigned int |
2592 | mips_lookup_reg_pair (unsigned int regno1, unsigned int regno2, | |
2593 | const unsigned int *map1, const unsigned int *map2, | |
2594 | unsigned int count) | |
2595 | { | |
2596 | unsigned int i; | |
2597 | ||
2598 | for (i = 0; i < count; i++) | |
2599 | if (map1[i] == regno1 && map2[i] == regno2) | |
2600 | return i; | |
2601 | return ILLEGAL_REG; | |
2602 | } | |
2603 | ||
d301a56b RS |
2604 | /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE |
2605 | and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */ | |
037b32b9 AN |
2606 | |
2607 | static bfd_boolean | |
f79e2745 | 2608 | is_opcode_valid (const struct mips_opcode *mo) |
037b32b9 AN |
2609 | { |
2610 | int isa = mips_opts.isa; | |
846ef2d0 | 2611 | int ase = mips_opts.ase; |
037b32b9 | 2612 | int fp_s, fp_d; |
c6278170 | 2613 | unsigned int i; |
037b32b9 | 2614 | |
c6278170 RS |
2615 | if (ISA_HAS_64BIT_REGS (mips_opts.isa)) |
2616 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
2617 | if ((ase & mips_ases[i].flags) == mips_ases[i].flags) | |
2618 | ase |= mips_ases[i].flags64; | |
037b32b9 | 2619 | |
d301a56b | 2620 | if (!opcode_is_member (mo, isa, ase, mips_opts.arch)) |
037b32b9 AN |
2621 | return FALSE; |
2622 | ||
2623 | /* Check whether the instruction or macro requires single-precision or | |
2624 | double-precision floating-point support. Note that this information is | |
2625 | stored differently in the opcode table for insns and macros. */ | |
2626 | if (mo->pinfo == INSN_MACRO) | |
2627 | { | |
2628 | fp_s = mo->pinfo2 & INSN2_M_FP_S; | |
2629 | fp_d = mo->pinfo2 & INSN2_M_FP_D; | |
2630 | } | |
2631 | else | |
2632 | { | |
2633 | fp_s = mo->pinfo & FP_S; | |
2634 | fp_d = mo->pinfo & FP_D; | |
2635 | } | |
2636 | ||
2637 | if (fp_d && (mips_opts.soft_float || mips_opts.single_float)) | |
2638 | return FALSE; | |
2639 | ||
2640 | if (fp_s && mips_opts.soft_float) | |
2641 | return FALSE; | |
2642 | ||
2643 | return TRUE; | |
2644 | } | |
2645 | ||
2646 | /* Return TRUE if the MIPS16 opcode MO is valid on the currently | |
2647 | selected ISA and architecture. */ | |
2648 | ||
2649 | static bfd_boolean | |
2650 | is_opcode_valid_16 (const struct mips_opcode *mo) | |
2651 | { | |
d301a56b | 2652 | return opcode_is_member (mo, mips_opts.isa, 0, mips_opts.arch); |
037b32b9 AN |
2653 | } |
2654 | ||
df58fc94 RS |
2655 | /* Return TRUE if the size of the microMIPS opcode MO matches one |
2656 | explicitly requested. Always TRUE in the standard MIPS mode. */ | |
2657 | ||
2658 | static bfd_boolean | |
2659 | is_size_valid (const struct mips_opcode *mo) | |
2660 | { | |
2661 | if (!mips_opts.micromips) | |
2662 | return TRUE; | |
2663 | ||
833794fc MR |
2664 | if (mips_opts.insn32) |
2665 | { | |
2666 | if (mo->pinfo != INSN_MACRO && micromips_insn_length (mo) != 4) | |
2667 | return FALSE; | |
2668 | if ((mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0) | |
2669 | return FALSE; | |
2670 | } | |
df58fc94 RS |
2671 | if (!forced_insn_length) |
2672 | return TRUE; | |
2673 | if (mo->pinfo == INSN_MACRO) | |
2674 | return FALSE; | |
2675 | return forced_insn_length == micromips_insn_length (mo); | |
2676 | } | |
2677 | ||
2678 | /* Return TRUE if the microMIPS opcode MO is valid for the delay slot | |
e64af278 MR |
2679 | of the preceding instruction. Always TRUE in the standard MIPS mode. |
2680 | ||
2681 | We don't accept macros in 16-bit delay slots to avoid a case where | |
2682 | a macro expansion fails because it relies on a preceding 32-bit real | |
2683 | instruction to have matched and does not handle the operands correctly. | |
2684 | The only macros that may expand to 16-bit instructions are JAL that | |
2685 | cannot be placed in a delay slot anyway, and corner cases of BALIGN | |
2686 | and BGT (that likewise cannot be placed in a delay slot) that decay to | |
2687 | a NOP. In all these cases the macros precede any corresponding real | |
2688 | instruction definitions in the opcode table, so they will match in the | |
2689 | second pass where the size of the delay slot is ignored and therefore | |
2690 | produce correct code. */ | |
df58fc94 RS |
2691 | |
2692 | static bfd_boolean | |
2693 | is_delay_slot_valid (const struct mips_opcode *mo) | |
2694 | { | |
2695 | if (!mips_opts.micromips) | |
2696 | return TRUE; | |
2697 | ||
2698 | if (mo->pinfo == INSN_MACRO) | |
c06dec14 | 2699 | return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0; |
df58fc94 RS |
2700 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 |
2701 | && micromips_insn_length (mo) != 4) | |
2702 | return FALSE; | |
2703 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 | |
2704 | && micromips_insn_length (mo) != 2) | |
2705 | return FALSE; | |
2706 | ||
2707 | return TRUE; | |
2708 | } | |
2709 | ||
707bfff6 TS |
2710 | /* This function is called once, at assembler startup time. It should set up |
2711 | all the tables, etc. that the MD part of the assembler will need. */ | |
156c2f8b | 2712 | |
252b5132 | 2713 | void |
17a2f251 | 2714 | md_begin (void) |
252b5132 | 2715 | { |
3994f87e | 2716 | const char *retval = NULL; |
156c2f8b | 2717 | int i = 0; |
252b5132 | 2718 | int broken = 0; |
1f25f5d3 | 2719 | |
0a44bf69 RS |
2720 | if (mips_pic != NO_PIC) |
2721 | { | |
2722 | if (g_switch_seen && g_switch_value != 0) | |
2723 | as_bad (_("-G may not be used in position-independent code")); | |
2724 | g_switch_value = 0; | |
2725 | } | |
2726 | ||
fef14a42 | 2727 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) |
252b5132 RH |
2728 | as_warn (_("Could not set architecture and machine")); |
2729 | ||
252b5132 RH |
2730 | op_hash = hash_new (); |
2731 | ||
2732 | for (i = 0; i < NUMOPCODES;) | |
2733 | { | |
2734 | const char *name = mips_opcodes[i].name; | |
2735 | ||
17a2f251 | 2736 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
2737 | if (retval != NULL) |
2738 | { | |
2739 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
2740 | mips_opcodes[i].name, retval); | |
2741 | /* Probably a memory allocation problem? Give up now. */ | |
2742 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
2743 | } | |
2744 | do | |
2745 | { | |
2746 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
2747 | { | |
2748 | if (!validate_mips_insn (&mips_opcodes[i])) | |
2749 | broken = 1; | |
1e915849 RS |
2750 | if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
2751 | { | |
2752 | create_insn (&nop_insn, mips_opcodes + i); | |
c67a084a NC |
2753 | if (mips_fix_loongson2f_nop) |
2754 | nop_insn.insn_opcode = LOONGSON2F_NOP_INSN; | |
1e915849 RS |
2755 | nop_insn.fixed_p = 1; |
2756 | } | |
252b5132 RH |
2757 | } |
2758 | ++i; | |
2759 | } | |
2760 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
2761 | } | |
2762 | ||
2763 | mips16_op_hash = hash_new (); | |
2764 | ||
2765 | i = 0; | |
2766 | while (i < bfd_mips16_num_opcodes) | |
2767 | { | |
2768 | const char *name = mips16_opcodes[i].name; | |
2769 | ||
17a2f251 | 2770 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
2771 | if (retval != NULL) |
2772 | as_fatal (_("internal: can't hash `%s': %s"), | |
2773 | mips16_opcodes[i].name, retval); | |
2774 | do | |
2775 | { | |
2776 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
2777 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
2778 | != mips16_opcodes[i].match)) | |
2779 | { | |
2780 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
2781 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
2782 | broken = 1; | |
2783 | } | |
1e915849 RS |
2784 | if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
2785 | { | |
2786 | create_insn (&mips16_nop_insn, mips16_opcodes + i); | |
2787 | mips16_nop_insn.fixed_p = 1; | |
2788 | } | |
252b5132 RH |
2789 | ++i; |
2790 | } | |
2791 | while (i < bfd_mips16_num_opcodes | |
2792 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
2793 | } | |
2794 | ||
df58fc94 RS |
2795 | micromips_op_hash = hash_new (); |
2796 | ||
2797 | i = 0; | |
2798 | while (i < bfd_micromips_num_opcodes) | |
2799 | { | |
2800 | const char *name = micromips_opcodes[i].name; | |
2801 | ||
2802 | retval = hash_insert (micromips_op_hash, name, | |
2803 | (void *) µmips_opcodes[i]); | |
2804 | if (retval != NULL) | |
2805 | as_fatal (_("internal: can't hash `%s': %s"), | |
2806 | micromips_opcodes[i].name, retval); | |
2807 | do | |
2808 | if (micromips_opcodes[i].pinfo != INSN_MACRO) | |
2809 | { | |
2810 | struct mips_cl_insn *micromips_nop_insn; | |
2811 | ||
2812 | if (!validate_micromips_insn (µmips_opcodes[i])) | |
2813 | broken = 1; | |
2814 | ||
2815 | if (micromips_insn_length (micromips_opcodes + i) == 2) | |
2816 | micromips_nop_insn = µmips_nop16_insn; | |
2817 | else if (micromips_insn_length (micromips_opcodes + i) == 4) | |
2818 | micromips_nop_insn = µmips_nop32_insn; | |
2819 | else | |
2820 | continue; | |
2821 | ||
2822 | if (micromips_nop_insn->insn_mo == NULL | |
2823 | && strcmp (name, "nop") == 0) | |
2824 | { | |
2825 | create_insn (micromips_nop_insn, micromips_opcodes + i); | |
2826 | micromips_nop_insn->fixed_p = 1; | |
2827 | } | |
2828 | } | |
2829 | while (++i < bfd_micromips_num_opcodes | |
2830 | && strcmp (micromips_opcodes[i].name, name) == 0); | |
2831 | } | |
2832 | ||
252b5132 RH |
2833 | if (broken) |
2834 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
2835 | ||
2836 | /* We add all the general register names to the symbol table. This | |
2837 | helps us detect invalid uses of them. */ | |
707bfff6 TS |
2838 | for (i = 0; reg_names[i].name; i++) |
2839 | symbol_table_insert (symbol_new (reg_names[i].name, reg_section, | |
8fc4ee9b | 2840 | reg_names[i].num, /* & RNUM_MASK, */ |
707bfff6 TS |
2841 | &zero_address_frag)); |
2842 | if (HAVE_NEWABI) | |
2843 | for (i = 0; reg_names_n32n64[i].name; i++) | |
2844 | symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section, | |
8fc4ee9b | 2845 | reg_names_n32n64[i].num, /* & RNUM_MASK, */ |
252b5132 | 2846 | &zero_address_frag)); |
707bfff6 TS |
2847 | else |
2848 | for (i = 0; reg_names_o32[i].name; i++) | |
2849 | symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section, | |
8fc4ee9b | 2850 | reg_names_o32[i].num, /* & RNUM_MASK, */ |
6047c971 | 2851 | &zero_address_frag)); |
6047c971 | 2852 | |
7d10b47d | 2853 | mips_no_prev_insn (); |
252b5132 RH |
2854 | |
2855 | mips_gprmask = 0; | |
2856 | mips_cprmask[0] = 0; | |
2857 | mips_cprmask[1] = 0; | |
2858 | mips_cprmask[2] = 0; | |
2859 | mips_cprmask[3] = 0; | |
2860 | ||
2861 | /* set the default alignment for the text section (2**2) */ | |
2862 | record_alignment (text_section, 2); | |
2863 | ||
4d0d148d | 2864 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 | 2865 | |
f3ded42a RS |
2866 | /* On a native system other than VxWorks, sections must be aligned |
2867 | to 16 byte boundaries. When configured for an embedded ELF | |
2868 | target, we don't bother. */ | |
2869 | if (strncmp (TARGET_OS, "elf", 3) != 0 | |
2870 | && strncmp (TARGET_OS, "vxworks", 7) != 0) | |
252b5132 | 2871 | { |
f3ded42a RS |
2872 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); |
2873 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
2874 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
2875 | } | |
252b5132 | 2876 | |
f3ded42a RS |
2877 | /* Create a .reginfo section for register masks and a .mdebug |
2878 | section for debugging information. */ | |
2879 | { | |
2880 | segT seg; | |
2881 | subsegT subseg; | |
2882 | flagword flags; | |
2883 | segT sec; | |
2884 | ||
2885 | seg = now_seg; | |
2886 | subseg = now_subseg; | |
2887 | ||
2888 | /* The ABI says this section should be loaded so that the | |
2889 | running program can access it. However, we don't load it | |
2890 | if we are configured for an embedded target */ | |
2891 | flags = SEC_READONLY | SEC_DATA; | |
2892 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
2893 | flags |= SEC_ALLOC | SEC_LOAD; | |
2894 | ||
2895 | if (mips_abi != N64_ABI) | |
252b5132 | 2896 | { |
f3ded42a | 2897 | sec = subseg_new (".reginfo", (subsegT) 0); |
bdaaa2e1 | 2898 | |
f3ded42a RS |
2899 | bfd_set_section_flags (stdoutput, sec, flags); |
2900 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
252b5132 | 2901 | |
f3ded42a RS |
2902 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
2903 | } | |
2904 | else | |
2905 | { | |
2906 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
2907 | .reginfo section. */ | |
2908 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
2909 | bfd_set_section_flags (stdoutput, sec, flags); | |
2910 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 | 2911 | |
f3ded42a RS |
2912 | /* Set up the option header. */ |
2913 | { | |
2914 | Elf_Internal_Options opthdr; | |
2915 | char *f; | |
2916 | ||
2917 | opthdr.kind = ODK_REGINFO; | |
2918 | opthdr.size = (sizeof (Elf_External_Options) | |
2919 | + sizeof (Elf64_External_RegInfo)); | |
2920 | opthdr.section = 0; | |
2921 | opthdr.info = 0; | |
2922 | f = frag_more (sizeof (Elf_External_Options)); | |
2923 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
2924 | (Elf_External_Options *) f); | |
2925 | ||
2926 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
2927 | } | |
2928 | } | |
252b5132 | 2929 | |
f3ded42a RS |
2930 | if (ECOFF_DEBUGGING) |
2931 | { | |
2932 | sec = subseg_new (".mdebug", (subsegT) 0); | |
2933 | (void) bfd_set_section_flags (stdoutput, sec, | |
2934 | SEC_HAS_CONTENTS | SEC_READONLY); | |
2935 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
252b5132 | 2936 | } |
f3ded42a RS |
2937 | else if (mips_flag_pdr) |
2938 | { | |
2939 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
2940 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
2941 | SEC_READONLY | SEC_RELOC | |
2942 | | SEC_DEBUGGING); | |
2943 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
2944 | } | |
2945 | ||
2946 | subseg_set (seg, subseg); | |
2947 | } | |
252b5132 RH |
2948 | |
2949 | if (! ECOFF_DEBUGGING) | |
2950 | md_obj_begin (); | |
71400594 RS |
2951 | |
2952 | if (mips_fix_vr4120) | |
2953 | init_vr4120_conflicts (); | |
252b5132 RH |
2954 | } |
2955 | ||
2956 | void | |
17a2f251 | 2957 | md_mips_end (void) |
252b5132 | 2958 | { |
02b1ab82 | 2959 | mips_emit_delays (); |
252b5132 RH |
2960 | if (! ECOFF_DEBUGGING) |
2961 | md_obj_end (); | |
2962 | } | |
2963 | ||
2964 | void | |
17a2f251 | 2965 | md_assemble (char *str) |
252b5132 RH |
2966 | { |
2967 | struct mips_cl_insn insn; | |
f6688943 TS |
2968 | bfd_reloc_code_real_type unused_reloc[3] |
2969 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 RH |
2970 | |
2971 | imm_expr.X_op = O_absent; | |
5f74bc13 | 2972 | imm2_expr.X_op = O_absent; |
252b5132 | 2973 | offset_expr.X_op = O_absent; |
f6688943 TS |
2974 | offset_reloc[0] = BFD_RELOC_UNUSED; |
2975 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
2976 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 | 2977 | |
e1b47bd5 RS |
2978 | mips_mark_labels (); |
2979 | mips_assembling_insn = TRUE; | |
2980 | ||
252b5132 RH |
2981 | if (mips_opts.mips16) |
2982 | mips16_ip (str, &insn); | |
2983 | else | |
2984 | { | |
2985 | mips_ip (str, &insn); | |
beae10d5 KH |
2986 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
2987 | str, insn.insn_opcode)); | |
252b5132 RH |
2988 | } |
2989 | ||
2990 | if (insn_error) | |
e1b47bd5 RS |
2991 | as_bad ("%s `%s'", insn_error, str); |
2992 | else if (insn.insn_mo->pinfo == INSN_MACRO) | |
252b5132 | 2993 | { |
584892a6 | 2994 | macro_start (); |
252b5132 RH |
2995 | if (mips_opts.mips16) |
2996 | mips16_macro (&insn); | |
2997 | else | |
833794fc | 2998 | macro (&insn, str); |
584892a6 | 2999 | macro_end (); |
252b5132 RH |
3000 | } |
3001 | else | |
3002 | { | |
77bd4346 | 3003 | if (offset_expr.X_op != O_absent) |
df58fc94 | 3004 | append_insn (&insn, &offset_expr, offset_reloc, FALSE); |
252b5132 | 3005 | else |
df58fc94 | 3006 | append_insn (&insn, NULL, unused_reloc, FALSE); |
252b5132 | 3007 | } |
e1b47bd5 RS |
3008 | |
3009 | mips_assembling_insn = FALSE; | |
252b5132 RH |
3010 | } |
3011 | ||
738e5348 RS |
3012 | /* Convenience functions for abstracting away the differences between |
3013 | MIPS16 and non-MIPS16 relocations. */ | |
3014 | ||
3015 | static inline bfd_boolean | |
3016 | mips16_reloc_p (bfd_reloc_code_real_type reloc) | |
3017 | { | |
3018 | switch (reloc) | |
3019 | { | |
3020 | case BFD_RELOC_MIPS16_JMP: | |
3021 | case BFD_RELOC_MIPS16_GPREL: | |
3022 | case BFD_RELOC_MIPS16_GOT16: | |
3023 | case BFD_RELOC_MIPS16_CALL16: | |
3024 | case BFD_RELOC_MIPS16_HI16_S: | |
3025 | case BFD_RELOC_MIPS16_HI16: | |
3026 | case BFD_RELOC_MIPS16_LO16: | |
3027 | return TRUE; | |
3028 | ||
3029 | default: | |
3030 | return FALSE; | |
3031 | } | |
3032 | } | |
3033 | ||
df58fc94 RS |
3034 | static inline bfd_boolean |
3035 | micromips_reloc_p (bfd_reloc_code_real_type reloc) | |
3036 | { | |
3037 | switch (reloc) | |
3038 | { | |
3039 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: | |
3040 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
3041 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
3042 | case BFD_RELOC_MICROMIPS_GPREL16: | |
3043 | case BFD_RELOC_MICROMIPS_JMP: | |
3044 | case BFD_RELOC_MICROMIPS_HI16: | |
3045 | case BFD_RELOC_MICROMIPS_HI16_S: | |
3046 | case BFD_RELOC_MICROMIPS_LO16: | |
3047 | case BFD_RELOC_MICROMIPS_LITERAL: | |
3048 | case BFD_RELOC_MICROMIPS_GOT16: | |
3049 | case BFD_RELOC_MICROMIPS_CALL16: | |
3050 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
3051 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
3052 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
3053 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
3054 | case BFD_RELOC_MICROMIPS_SUB: | |
3055 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
3056 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
3057 | case BFD_RELOC_MICROMIPS_GOT_DISP: | |
3058 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
3059 | case BFD_RELOC_MICROMIPS_HIGHER: | |
3060 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
3061 | case BFD_RELOC_MICROMIPS_JALR: | |
3062 | return TRUE; | |
3063 | ||
3064 | default: | |
3065 | return FALSE; | |
3066 | } | |
3067 | } | |
3068 | ||
2309ddf2 MR |
3069 | static inline bfd_boolean |
3070 | jmp_reloc_p (bfd_reloc_code_real_type reloc) | |
3071 | { | |
3072 | return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP; | |
3073 | } | |
3074 | ||
738e5348 RS |
3075 | static inline bfd_boolean |
3076 | got16_reloc_p (bfd_reloc_code_real_type reloc) | |
3077 | { | |
2309ddf2 | 3078 | return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16 |
df58fc94 | 3079 | || reloc == BFD_RELOC_MICROMIPS_GOT16); |
738e5348 RS |
3080 | } |
3081 | ||
3082 | static inline bfd_boolean | |
3083 | hi16_reloc_p (bfd_reloc_code_real_type reloc) | |
3084 | { | |
2309ddf2 | 3085 | return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S |
df58fc94 | 3086 | || reloc == BFD_RELOC_MICROMIPS_HI16_S); |
738e5348 RS |
3087 | } |
3088 | ||
3089 | static inline bfd_boolean | |
3090 | lo16_reloc_p (bfd_reloc_code_real_type reloc) | |
3091 | { | |
2309ddf2 | 3092 | return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16 |
df58fc94 RS |
3093 | || reloc == BFD_RELOC_MICROMIPS_LO16); |
3094 | } | |
3095 | ||
df58fc94 RS |
3096 | static inline bfd_boolean |
3097 | jalr_reloc_p (bfd_reloc_code_real_type reloc) | |
3098 | { | |
2309ddf2 | 3099 | return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR; |
738e5348 RS |
3100 | } |
3101 | ||
f2ae14a1 RS |
3102 | static inline bfd_boolean |
3103 | gprel16_reloc_p (bfd_reloc_code_real_type reloc) | |
3104 | { | |
3105 | return (reloc == BFD_RELOC_GPREL16 || reloc == BFD_RELOC_MIPS16_GPREL | |
3106 | || reloc == BFD_RELOC_MICROMIPS_GPREL16); | |
3107 | } | |
3108 | ||
2de39019 CM |
3109 | /* Return true if RELOC is a PC-relative relocation that does not have |
3110 | full address range. */ | |
3111 | ||
3112 | static inline bfd_boolean | |
3113 | limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc) | |
3114 | { | |
3115 | switch (reloc) | |
3116 | { | |
3117 | case BFD_RELOC_16_PCREL_S2: | |
3118 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: | |
3119 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
3120 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
3121 | return TRUE; | |
3122 | ||
b47468a6 CM |
3123 | case BFD_RELOC_32_PCREL: |
3124 | return HAVE_64BIT_ADDRESSES; | |
3125 | ||
2de39019 CM |
3126 | default: |
3127 | return FALSE; | |
3128 | } | |
3129 | } | |
b47468a6 | 3130 | |
5919d012 | 3131 | /* Return true if the given relocation might need a matching %lo(). |
0a44bf69 RS |
3132 | This is only "might" because SVR4 R_MIPS_GOT16 relocations only |
3133 | need a matching %lo() when applied to local symbols. */ | |
5919d012 RS |
3134 | |
3135 | static inline bfd_boolean | |
17a2f251 | 3136 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 3137 | { |
3b91255e | 3138 | return (HAVE_IN_PLACE_ADDENDS |
738e5348 | 3139 | && (hi16_reloc_p (reloc) |
0a44bf69 RS |
3140 | /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo(); |
3141 | all GOT16 relocations evaluate to "G". */ | |
738e5348 RS |
3142 | || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC))); |
3143 | } | |
3144 | ||
3145 | /* Return the type of %lo() reloc needed by RELOC, given that | |
3146 | reloc_needs_lo_p. */ | |
3147 | ||
3148 | static inline bfd_reloc_code_real_type | |
3149 | matching_lo_reloc (bfd_reloc_code_real_type reloc) | |
3150 | { | |
df58fc94 RS |
3151 | return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 |
3152 | : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16 | |
3153 | : BFD_RELOC_LO16)); | |
5919d012 RS |
3154 | } |
3155 | ||
3156 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
3157 | relocation. */ | |
3158 | ||
3159 | static inline bfd_boolean | |
17a2f251 | 3160 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
3161 | { |
3162 | return (fixp->fx_next != NULL | |
738e5348 | 3163 | && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type) |
5919d012 RS |
3164 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
3165 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
3166 | } | |
3167 | ||
252b5132 RH |
3168 | /* This function returns true if modifying a register requires a |
3169 | delay. */ | |
3170 | ||
3171 | static int | |
17a2f251 | 3172 | reg_needs_delay (unsigned int reg) |
252b5132 RH |
3173 | { |
3174 | unsigned long prev_pinfo; | |
3175 | ||
47e39b9d | 3176 | prev_pinfo = history[0].insn_mo->pinfo; |
252b5132 | 3177 | if (! mips_opts.noreorder |
81912461 ILT |
3178 | && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) |
3179 | && ! gpr_interlocks) | |
3180 | || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) | |
3181 | && ! cop_interlocks))) | |
252b5132 | 3182 | { |
81912461 ILT |
3183 | /* A load from a coprocessor or from memory. All load delays |
3184 | delay the use of general register rt for one instruction. */ | |
bdaaa2e1 | 3185 | /* Itbl support may require additional care here. */ |
252b5132 | 3186 | know (prev_pinfo & INSN_WRITE_GPR_T); |
df58fc94 | 3187 | if (reg == EXTRACT_OPERAND (mips_opts.micromips, RT, history[0])) |
252b5132 RH |
3188 | return 1; |
3189 | } | |
3190 | ||
3191 | return 0; | |
3192 | } | |
3193 | ||
462427c4 RS |
3194 | /* Move all labels in LABELS to the current insertion point. TEXT_P |
3195 | says whether the labels refer to text or data. */ | |
404a8071 RS |
3196 | |
3197 | static void | |
462427c4 | 3198 | mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p) |
404a8071 RS |
3199 | { |
3200 | struct insn_label_list *l; | |
3201 | valueT val; | |
3202 | ||
462427c4 | 3203 | for (l = labels; l != NULL; l = l->next) |
404a8071 | 3204 | { |
9c2799c2 | 3205 | gas_assert (S_GET_SEGMENT (l->label) == now_seg); |
404a8071 RS |
3206 | symbol_set_frag (l->label, frag_now); |
3207 | val = (valueT) frag_now_fix (); | |
df58fc94 | 3208 | /* MIPS16/microMIPS text labels are stored as odd. */ |
462427c4 | 3209 | if (text_p && HAVE_CODE_COMPRESSION) |
404a8071 RS |
3210 | ++val; |
3211 | S_SET_VALUE (l->label, val); | |
3212 | } | |
3213 | } | |
3214 | ||
462427c4 RS |
3215 | /* Move all labels in insn_labels to the current insertion point |
3216 | and treat them as text labels. */ | |
3217 | ||
3218 | static void | |
3219 | mips_move_text_labels (void) | |
3220 | { | |
3221 | mips_move_labels (seg_info (now_seg)->label_list, TRUE); | |
3222 | } | |
3223 | ||
5f0fe04b TS |
3224 | static bfd_boolean |
3225 | s_is_linkonce (symbolS *sym, segT from_seg) | |
3226 | { | |
3227 | bfd_boolean linkonce = FALSE; | |
3228 | segT symseg = S_GET_SEGMENT (sym); | |
3229 | ||
3230 | if (symseg != from_seg && !S_IS_LOCAL (sym)) | |
3231 | { | |
3232 | if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE)) | |
3233 | linkonce = TRUE; | |
5f0fe04b TS |
3234 | /* The GNU toolchain uses an extension for ELF: a section |
3235 | beginning with the magic string .gnu.linkonce is a | |
3236 | linkonce section. */ | |
3237 | if (strncmp (segment_name (symseg), ".gnu.linkonce", | |
3238 | sizeof ".gnu.linkonce" - 1) == 0) | |
3239 | linkonce = TRUE; | |
5f0fe04b TS |
3240 | } |
3241 | return linkonce; | |
3242 | } | |
3243 | ||
e1b47bd5 | 3244 | /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the |
df58fc94 RS |
3245 | linker to handle them specially, such as generating jalx instructions |
3246 | when needed. We also make them odd for the duration of the assembly, | |
3247 | in order to generate the right sort of code. We will make them even | |
252b5132 RH |
3248 | in the adjust_symtab routine, while leaving them marked. This is |
3249 | convenient for the debugger and the disassembler. The linker knows | |
3250 | to make them odd again. */ | |
3251 | ||
3252 | static void | |
e1b47bd5 | 3253 | mips_compressed_mark_label (symbolS *label) |
252b5132 | 3254 | { |
df58fc94 | 3255 | gas_assert (HAVE_CODE_COMPRESSION); |
a8dbcb85 | 3256 | |
f3ded42a RS |
3257 | if (mips_opts.mips16) |
3258 | S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label))); | |
3259 | else | |
3260 | S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label))); | |
e1b47bd5 RS |
3261 | if ((S_GET_VALUE (label) & 1) == 0 |
3262 | /* Don't adjust the address if the label is global or weak, or | |
3263 | in a link-once section, since we'll be emitting symbol reloc | |
3264 | references to it which will be patched up by the linker, and | |
3265 | the final value of the symbol may or may not be MIPS16/microMIPS. */ | |
3266 | && !S_IS_WEAK (label) | |
3267 | && !S_IS_EXTERNAL (label) | |
3268 | && !s_is_linkonce (label, now_seg)) | |
3269 | S_SET_VALUE (label, S_GET_VALUE (label) | 1); | |
3270 | } | |
3271 | ||
3272 | /* Mark preceding MIPS16 or microMIPS instruction labels. */ | |
3273 | ||
3274 | static void | |
3275 | mips_compressed_mark_labels (void) | |
3276 | { | |
3277 | struct insn_label_list *l; | |
3278 | ||
3279 | for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next) | |
3280 | mips_compressed_mark_label (l->label); | |
252b5132 RH |
3281 | } |
3282 | ||
4d7206a2 RS |
3283 | /* End the current frag. Make it a variant frag and record the |
3284 | relaxation info. */ | |
3285 | ||
3286 | static void | |
3287 | relax_close_frag (void) | |
3288 | { | |
584892a6 | 3289 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 3290 | frag_var (rs_machine_dependent, 0, 0, |
584892a6 | 3291 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), |
4d7206a2 RS |
3292 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
3293 | ||
3294 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
3295 | mips_relax.first_fixup = 0; | |
3296 | } | |
3297 | ||
3298 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
3299 | See the comment above RELAX_ENCODE for more details. */ | |
3300 | ||
3301 | static void | |
3302 | relax_start (symbolS *symbol) | |
3303 | { | |
9c2799c2 | 3304 | gas_assert (mips_relax.sequence == 0); |
4d7206a2 RS |
3305 | mips_relax.sequence = 1; |
3306 | mips_relax.symbol = symbol; | |
3307 | } | |
3308 | ||
3309 | /* Start generating the second version of a relaxable sequence. | |
3310 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
3311 | |
3312 | static void | |
4d7206a2 RS |
3313 | relax_switch (void) |
3314 | { | |
9c2799c2 | 3315 | gas_assert (mips_relax.sequence == 1); |
4d7206a2 RS |
3316 | mips_relax.sequence = 2; |
3317 | } | |
3318 | ||
3319 | /* End the current relaxable sequence. */ | |
3320 | ||
3321 | static void | |
3322 | relax_end (void) | |
3323 | { | |
9c2799c2 | 3324 | gas_assert (mips_relax.sequence == 2); |
4d7206a2 RS |
3325 | relax_close_frag (); |
3326 | mips_relax.sequence = 0; | |
3327 | } | |
3328 | ||
11625dd8 RS |
3329 | /* Return true if IP is a delayed branch or jump. */ |
3330 | ||
3331 | static inline bfd_boolean | |
3332 | delayed_branch_p (const struct mips_cl_insn *ip) | |
3333 | { | |
3334 | return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY | |
3335 | | INSN_COND_BRANCH_DELAY | |
3336 | | INSN_COND_BRANCH_LIKELY)) != 0; | |
3337 | } | |
3338 | ||
3339 | /* Return true if IP is a compact branch or jump. */ | |
3340 | ||
3341 | static inline bfd_boolean | |
3342 | compact_branch_p (const struct mips_cl_insn *ip) | |
3343 | { | |
3344 | if (mips_opts.mips16) | |
3345 | return (ip->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH | |
3346 | | MIPS16_INSN_COND_BRANCH)) != 0; | |
3347 | else | |
3348 | return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH | |
3349 | | INSN2_COND_BRANCH)) != 0; | |
3350 | } | |
3351 | ||
3352 | /* Return true if IP is an unconditional branch or jump. */ | |
3353 | ||
3354 | static inline bfd_boolean | |
3355 | uncond_branch_p (const struct mips_cl_insn *ip) | |
3356 | { | |
3357 | return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0 | |
3358 | || (mips_opts.mips16 | |
3359 | ? (ip->insn_mo->pinfo & MIPS16_INSN_UNCOND_BRANCH) != 0 | |
3360 | : (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0)); | |
3361 | } | |
3362 | ||
3363 | /* Return true if IP is a branch-likely instruction. */ | |
3364 | ||
3365 | static inline bfd_boolean | |
3366 | branch_likely_p (const struct mips_cl_insn *ip) | |
3367 | { | |
3368 | return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0; | |
3369 | } | |
3370 | ||
14fe068b RS |
3371 | /* Return the type of nop that should be used to fill the delay slot |
3372 | of delayed branch IP. */ | |
3373 | ||
3374 | static struct mips_cl_insn * | |
3375 | get_delay_slot_nop (const struct mips_cl_insn *ip) | |
3376 | { | |
3377 | if (mips_opts.micromips | |
3378 | && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
3379 | return µmips_nop32_insn; | |
3380 | return NOP_INSN; | |
3381 | } | |
3382 | ||
2309ddf2 | 3383 | /* Return the mask of core registers that IP reads or writes. */ |
df58fc94 RS |
3384 | |
3385 | static unsigned int | |
3386 | gpr_mod_mask (const struct mips_cl_insn *ip) | |
3387 | { | |
2309ddf2 | 3388 | unsigned long pinfo2; |
df58fc94 RS |
3389 | unsigned int mask; |
3390 | ||
3391 | mask = 0; | |
df58fc94 RS |
3392 | pinfo2 = ip->insn_mo->pinfo2; |
3393 | if (mips_opts.micromips) | |
3394 | { | |
df58fc94 RS |
3395 | if (pinfo2 & INSN2_MOD_GPR_MD) |
3396 | mask |= 1 << micromips_to_32_reg_d_map[EXTRACT_OPERAND (1, MD, *ip)]; | |
df58fc94 RS |
3397 | if (pinfo2 & INSN2_MOD_GPR_MF) |
3398 | mask |= 1 << micromips_to_32_reg_f_map[EXTRACT_OPERAND (1, MF, *ip)]; | |
df58fc94 RS |
3399 | if (pinfo2 & INSN2_MOD_SP) |
3400 | mask |= 1 << SP; | |
3401 | } | |
3402 | return mask; | |
3403 | } | |
3404 | ||
4c260379 RS |
3405 | /* Return the mask of core registers that IP reads. */ |
3406 | ||
3407 | static unsigned int | |
3408 | gpr_read_mask (const struct mips_cl_insn *ip) | |
3409 | { | |
3410 | unsigned long pinfo, pinfo2; | |
3411 | unsigned int mask; | |
3412 | ||
df58fc94 | 3413 | mask = gpr_mod_mask (ip); |
4c260379 RS |
3414 | pinfo = ip->insn_mo->pinfo; |
3415 | pinfo2 = ip->insn_mo->pinfo2; | |
3416 | if (mips_opts.mips16) | |
3417 | { | |
3418 | if (pinfo & MIPS16_INSN_READ_X) | |
3419 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)]; | |
3420 | if (pinfo & MIPS16_INSN_READ_Y) | |
3421 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)]; | |
3422 | if (pinfo & MIPS16_INSN_READ_T) | |
3423 | mask |= 1 << TREG; | |
3424 | if (pinfo & MIPS16_INSN_READ_SP) | |
3425 | mask |= 1 << SP; | |
3426 | if (pinfo & MIPS16_INSN_READ_31) | |
3427 | mask |= 1 << RA; | |
3428 | if (pinfo & MIPS16_INSN_READ_Z) | |
3429 | mask |= 1 << (mips16_to_32_reg_map | |
3430 | [MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]); | |
3431 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
3432 | mask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip); | |
3433 | } | |
3434 | else | |
3435 | { | |
3436 | if (pinfo2 & INSN2_READ_GPR_D) | |
2309ddf2 | 3437 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); |
4c260379 | 3438 | if (pinfo & INSN_READ_GPR_T) |
2309ddf2 | 3439 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); |
4c260379 | 3440 | if (pinfo & INSN_READ_GPR_S) |
2309ddf2 MR |
3441 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); |
3442 | if (pinfo2 & INSN2_READ_GP) | |
3443 | mask |= 1 << GP; | |
3444 | if (pinfo2 & INSN2_READ_GPR_31) | |
3445 | mask |= 1 << RA; | |
4c260379 | 3446 | if (pinfo2 & INSN2_READ_GPR_Z) |
2309ddf2 | 3447 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip); |
4c260379 | 3448 | } |
2b0c8b40 MR |
3449 | if (mips_opts.micromips) |
3450 | { | |
3451 | if (pinfo2 & INSN2_READ_GPR_MC) | |
3452 | mask |= 1 << micromips_to_32_reg_c_map[EXTRACT_OPERAND (1, MC, *ip)]; | |
3453 | if (pinfo2 & INSN2_READ_GPR_ME) | |
3454 | mask |= 1 << micromips_to_32_reg_e_map[EXTRACT_OPERAND (1, ME, *ip)]; | |
3455 | if (pinfo2 & INSN2_READ_GPR_MG) | |
3456 | mask |= 1 << micromips_to_32_reg_g_map[EXTRACT_OPERAND (1, MG, *ip)]; | |
3457 | if (pinfo2 & INSN2_READ_GPR_MJ) | |
3458 | mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip); | |
3459 | if (pinfo2 & INSN2_READ_GPR_MMN) | |
3460 | { | |
3461 | mask |= 1 << micromips_to_32_reg_m_map[EXTRACT_OPERAND (1, MM, *ip)]; | |
3462 | mask |= 1 << micromips_to_32_reg_n_map[EXTRACT_OPERAND (1, MN, *ip)]; | |
3463 | } | |
3464 | if (pinfo2 & INSN2_READ_GPR_MP) | |
3465 | mask |= 1 << EXTRACT_OPERAND (1, MP, *ip); | |
3466 | if (pinfo2 & INSN2_READ_GPR_MQ) | |
3467 | mask |= 1 << micromips_to_32_reg_q_map[EXTRACT_OPERAND (1, MQ, *ip)]; | |
3468 | } | |
fe35f09f RS |
3469 | /* Don't include register 0. */ |
3470 | return mask & ~1; | |
4c260379 RS |
3471 | } |
3472 | ||
3473 | /* Return the mask of core registers that IP writes. */ | |
3474 | ||
3475 | static unsigned int | |
3476 | gpr_write_mask (const struct mips_cl_insn *ip) | |
3477 | { | |
3478 | unsigned long pinfo, pinfo2; | |
3479 | unsigned int mask; | |
3480 | ||
df58fc94 | 3481 | mask = gpr_mod_mask (ip); |
4c260379 RS |
3482 | pinfo = ip->insn_mo->pinfo; |
3483 | pinfo2 = ip->insn_mo->pinfo2; | |
3484 | if (mips_opts.mips16) | |
3485 | { | |
3486 | if (pinfo & MIPS16_INSN_WRITE_X) | |
3487 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)]; | |
3488 | if (pinfo & MIPS16_INSN_WRITE_Y) | |
3489 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)]; | |
3490 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
3491 | mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RZ, *ip)]; | |
3492 | if (pinfo & MIPS16_INSN_WRITE_T) | |
3493 | mask |= 1 << TREG; | |
3494 | if (pinfo & MIPS16_INSN_WRITE_SP) | |
3495 | mask |= 1 << SP; | |
3496 | if (pinfo & MIPS16_INSN_WRITE_31) | |
3497 | mask |= 1 << RA; | |
3498 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
3499 | mask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
3500 | } | |
3501 | else | |
3502 | { | |
3503 | if (pinfo & INSN_WRITE_GPR_D) | |
df58fc94 | 3504 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); |
4c260379 | 3505 | if (pinfo & INSN_WRITE_GPR_T) |
df58fc94 | 3506 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); |
2b0c8b40 | 3507 | if (pinfo & INSN_WRITE_GPR_S) |
2309ddf2 | 3508 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); |
4c260379 RS |
3509 | if (pinfo & INSN_WRITE_GPR_31) |
3510 | mask |= 1 << RA; | |
3511 | if (pinfo2 & INSN2_WRITE_GPR_Z) | |
df58fc94 | 3512 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip); |
4c260379 | 3513 | } |
2b0c8b40 MR |
3514 | if (mips_opts.micromips) |
3515 | { | |
3516 | if (pinfo2 & INSN2_WRITE_GPR_MB) | |
3517 | mask |= 1 << micromips_to_32_reg_b_map[EXTRACT_OPERAND (1, MB, *ip)]; | |
e76ff5ab | 3518 | if (pinfo2 & INSN2_WRITE_GPR_MH) |
2b0c8b40 | 3519 | { |
e76ff5ab RS |
3520 | mask |= 1 << micromips_to_32_reg_h_map1[EXTRACT_OPERAND (1, MH, *ip)]; |
3521 | mask |= 1 << micromips_to_32_reg_h_map2[EXTRACT_OPERAND (1, MH, *ip)]; | |
2b0c8b40 MR |
3522 | } |
3523 | if (pinfo2 & INSN2_WRITE_GPR_MJ) | |
3524 | mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip); | |
3525 | if (pinfo2 & INSN2_WRITE_GPR_MP) | |
3526 | mask |= 1 << EXTRACT_OPERAND (1, MP, *ip); | |
3527 | } | |
fe35f09f RS |
3528 | /* Don't include register 0. */ |
3529 | return mask & ~1; | |
4c260379 RS |
3530 | } |
3531 | ||
3532 | /* Return the mask of floating-point registers that IP reads. */ | |
3533 | ||
3534 | static unsigned int | |
3535 | fpr_read_mask (const struct mips_cl_insn *ip) | |
3536 | { | |
3537 | unsigned long pinfo, pinfo2; | |
3538 | unsigned int mask; | |
3539 | ||
3540 | mask = 0; | |
3541 | pinfo = ip->insn_mo->pinfo; | |
3542 | pinfo2 = ip->insn_mo->pinfo2; | |
2309ddf2 | 3543 | if (!mips_opts.mips16) |
df58fc94 RS |
3544 | { |
3545 | if (pinfo2 & INSN2_READ_FPR_D) | |
2309ddf2 | 3546 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip); |
4c260379 | 3547 | if (pinfo & INSN_READ_FPR_S) |
df58fc94 | 3548 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip); |
4c260379 | 3549 | if (pinfo & INSN_READ_FPR_T) |
df58fc94 | 3550 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip); |
4c260379 | 3551 | if (pinfo & INSN_READ_FPR_R) |
df58fc94 | 3552 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FR, *ip); |
4c260379 | 3553 | if (pinfo2 & INSN2_READ_FPR_Z) |
df58fc94 | 3554 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip); |
4c260379 RS |
3555 | } |
3556 | /* Conservatively treat all operands to an FP_D instruction are doubles. | |
3557 | (This is overly pessimistic for things like cvt.d.s.) */ | |
3558 | if (HAVE_32BIT_FPRS && (pinfo & FP_D)) | |
3559 | mask |= mask << 1; | |
3560 | return mask; | |
3561 | } | |
3562 | ||
3563 | /* Return the mask of floating-point registers that IP writes. */ | |
3564 | ||
3565 | static unsigned int | |
3566 | fpr_write_mask (const struct mips_cl_insn *ip) | |
3567 | { | |
3568 | unsigned long pinfo, pinfo2; | |
3569 | unsigned int mask; | |
3570 | ||
3571 | mask = 0; | |
3572 | pinfo = ip->insn_mo->pinfo; | |
3573 | pinfo2 = ip->insn_mo->pinfo2; | |
2309ddf2 | 3574 | if (!mips_opts.mips16) |
4c260379 RS |
3575 | { |
3576 | if (pinfo & INSN_WRITE_FPR_D) | |
df58fc94 | 3577 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FD, *ip); |
4c260379 | 3578 | if (pinfo & INSN_WRITE_FPR_S) |
df58fc94 | 3579 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FS, *ip); |
4c260379 | 3580 | if (pinfo & INSN_WRITE_FPR_T) |
df58fc94 | 3581 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FT, *ip); |
4c260379 | 3582 | if (pinfo2 & INSN2_WRITE_FPR_Z) |
df58fc94 | 3583 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, FZ, *ip); |
4c260379 RS |
3584 | } |
3585 | /* Conservatively treat all operands to an FP_D instruction are doubles. | |
3586 | (This is overly pessimistic for things like cvt.s.d.) */ | |
3587 | if (HAVE_32BIT_FPRS && (pinfo & FP_D)) | |
3588 | mask |= mask << 1; | |
3589 | return mask; | |
3590 | } | |
3591 | ||
71400594 RS |
3592 | /* Classify an instruction according to the FIX_VR4120_* enumeration. |
3593 | Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected | |
3594 | by VR4120 errata. */ | |
4d7206a2 | 3595 | |
71400594 RS |
3596 | static unsigned int |
3597 | classify_vr4120_insn (const char *name) | |
252b5132 | 3598 | { |
71400594 RS |
3599 | if (strncmp (name, "macc", 4) == 0) |
3600 | return FIX_VR4120_MACC; | |
3601 | if (strncmp (name, "dmacc", 5) == 0) | |
3602 | return FIX_VR4120_DMACC; | |
3603 | if (strncmp (name, "mult", 4) == 0) | |
3604 | return FIX_VR4120_MULT; | |
3605 | if (strncmp (name, "dmult", 5) == 0) | |
3606 | return FIX_VR4120_DMULT; | |
3607 | if (strstr (name, "div")) | |
3608 | return FIX_VR4120_DIV; | |
3609 | if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) | |
3610 | return FIX_VR4120_MTHILO; | |
3611 | return NUM_FIX_VR4120_CLASSES; | |
3612 | } | |
252b5132 | 3613 | |
ff239038 CM |
3614 | #define INSN_ERET 0x42000018 |
3615 | #define INSN_DERET 0x4200001f | |
3616 | ||
71400594 RS |
3617 | /* Return the number of instructions that must separate INSN1 and INSN2, |
3618 | where INSN1 is the earlier instruction. Return the worst-case value | |
3619 | for any INSN2 if INSN2 is null. */ | |
252b5132 | 3620 | |
71400594 RS |
3621 | static unsigned int |
3622 | insns_between (const struct mips_cl_insn *insn1, | |
3623 | const struct mips_cl_insn *insn2) | |
3624 | { | |
3625 | unsigned long pinfo1, pinfo2; | |
4c260379 | 3626 | unsigned int mask; |
71400594 RS |
3627 | |
3628 | /* This function needs to know which pinfo flags are set for INSN2 | |
3629 | and which registers INSN2 uses. The former is stored in PINFO2 and | |
4c260379 RS |
3630 | the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2 |
3631 | will have every flag set and INSN2_USES_GPR will always return true. */ | |
71400594 RS |
3632 | pinfo1 = insn1->insn_mo->pinfo; |
3633 | pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; | |
252b5132 | 3634 | |
4c260379 RS |
3635 | #define INSN2_USES_GPR(REG) \ |
3636 | (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0) | |
71400594 RS |
3637 | |
3638 | /* For most targets, write-after-read dependencies on the HI and LO | |
3639 | registers must be separated by at least two instructions. */ | |
3640 | if (!hilo_interlocks) | |
252b5132 | 3641 | { |
71400594 RS |
3642 | if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) |
3643 | return 2; | |
3644 | if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) | |
3645 | return 2; | |
3646 | } | |
3647 | ||
3648 | /* If we're working around r7000 errata, there must be two instructions | |
3649 | between an mfhi or mflo and any instruction that uses the result. */ | |
3650 | if (mips_7000_hilo_fix | |
df58fc94 | 3651 | && !mips_opts.micromips |
71400594 | 3652 | && MF_HILO_INSN (pinfo1) |
df58fc94 | 3653 | && INSN2_USES_GPR (EXTRACT_OPERAND (0, RD, *insn1))) |
71400594 RS |
3654 | return 2; |
3655 | ||
ff239038 CM |
3656 | /* If we're working around 24K errata, one instruction is required |
3657 | if an ERET or DERET is followed by a branch instruction. */ | |
df58fc94 | 3658 | if (mips_fix_24k && !mips_opts.micromips) |
ff239038 CM |
3659 | { |
3660 | if (insn1->insn_opcode == INSN_ERET | |
3661 | || insn1->insn_opcode == INSN_DERET) | |
3662 | { | |
3663 | if (insn2 == NULL | |
3664 | || insn2->insn_opcode == INSN_ERET | |
3665 | || insn2->insn_opcode == INSN_DERET | |
11625dd8 | 3666 | || delayed_branch_p (insn2)) |
ff239038 CM |
3667 | return 1; |
3668 | } | |
3669 | } | |
3670 | ||
71400594 RS |
3671 | /* If working around VR4120 errata, check for combinations that need |
3672 | a single intervening instruction. */ | |
df58fc94 | 3673 | if (mips_fix_vr4120 && !mips_opts.micromips) |
71400594 RS |
3674 | { |
3675 | unsigned int class1, class2; | |
252b5132 | 3676 | |
71400594 RS |
3677 | class1 = classify_vr4120_insn (insn1->insn_mo->name); |
3678 | if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) | |
252b5132 | 3679 | { |
71400594 RS |
3680 | if (insn2 == NULL) |
3681 | return 1; | |
3682 | class2 = classify_vr4120_insn (insn2->insn_mo->name); | |
3683 | if (vr4120_conflicts[class1] & (1 << class2)) | |
3684 | return 1; | |
252b5132 | 3685 | } |
71400594 RS |
3686 | } |
3687 | ||
df58fc94 | 3688 | if (!HAVE_CODE_COMPRESSION) |
71400594 RS |
3689 | { |
3690 | /* Check for GPR or coprocessor load delays. All such delays | |
3691 | are on the RT register. */ | |
3692 | /* Itbl support may require additional care here. */ | |
3693 | if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY)) | |
3694 | || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY))) | |
252b5132 | 3695 | { |
71400594 | 3696 | know (pinfo1 & INSN_WRITE_GPR_T); |
df58fc94 | 3697 | if (INSN2_USES_GPR (EXTRACT_OPERAND (0, RT, *insn1))) |
71400594 RS |
3698 | return 1; |
3699 | } | |
3700 | ||
3701 | /* Check for generic coprocessor hazards. | |
3702 | ||
3703 | This case is not handled very well. There is no special | |
3704 | knowledge of CP0 handling, and the coprocessors other than | |
3705 | the floating point unit are not distinguished at all. */ | |
3706 | /* Itbl support may require additional care here. FIXME! | |
3707 | Need to modify this to include knowledge about | |
3708 | user specified delays! */ | |
3709 | else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY)) | |
3710 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) | |
3711 | { | |
3712 | /* Handle cases where INSN1 writes to a known general coprocessor | |
3713 | register. There must be a one instruction delay before INSN2 | |
3714 | if INSN2 reads that register, otherwise no delay is needed. */ | |
4c260379 RS |
3715 | mask = fpr_write_mask (insn1); |
3716 | if (mask != 0) | |
252b5132 | 3717 | { |
4c260379 | 3718 | if (!insn2 || (mask & fpr_read_mask (insn2)) != 0) |
71400594 | 3719 | return 1; |
252b5132 RH |
3720 | } |
3721 | else | |
3722 | { | |
71400594 RS |
3723 | /* Read-after-write dependencies on the control registers |
3724 | require a two-instruction gap. */ | |
3725 | if ((pinfo1 & INSN_WRITE_COND_CODE) | |
3726 | && (pinfo2 & INSN_READ_COND_CODE)) | |
3727 | return 2; | |
3728 | ||
3729 | /* We don't know exactly what INSN1 does. If INSN2 is | |
3730 | also a coprocessor instruction, assume there must be | |
3731 | a one instruction gap. */ | |
3732 | if (pinfo2 & INSN_COP) | |
3733 | return 1; | |
252b5132 RH |
3734 | } |
3735 | } | |
6b76fefe | 3736 | |
71400594 RS |
3737 | /* Check for read-after-write dependencies on the coprocessor |
3738 | control registers in cases where INSN1 does not need a general | |
3739 | coprocessor delay. This means that INSN1 is a floating point | |
3740 | comparison instruction. */ | |
3741 | /* Itbl support may require additional care here. */ | |
3742 | else if (!cop_interlocks | |
3743 | && (pinfo1 & INSN_WRITE_COND_CODE) | |
3744 | && (pinfo2 & INSN_READ_COND_CODE)) | |
3745 | return 1; | |
3746 | } | |
6b76fefe | 3747 | |
4c260379 | 3748 | #undef INSN2_USES_GPR |
6b76fefe | 3749 | |
71400594 RS |
3750 | return 0; |
3751 | } | |
6b76fefe | 3752 | |
7d8e00cf RS |
3753 | /* Return the number of nops that would be needed to work around the |
3754 | VR4130 mflo/mfhi errata if instruction INSN immediately followed | |
932d1a1b RS |
3755 | the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards |
3756 | that are contained within the first IGNORE instructions of HIST. */ | |
7d8e00cf RS |
3757 | |
3758 | static int | |
932d1a1b | 3759 | nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist, |
7d8e00cf RS |
3760 | const struct mips_cl_insn *insn) |
3761 | { | |
4c260379 RS |
3762 | int i, j; |
3763 | unsigned int mask; | |
7d8e00cf RS |
3764 | |
3765 | /* Check if the instruction writes to HI or LO. MTHI and MTLO | |
3766 | are not affected by the errata. */ | |
3767 | if (insn != 0 | |
3768 | && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 | |
3769 | || strcmp (insn->insn_mo->name, "mtlo") == 0 | |
3770 | || strcmp (insn->insn_mo->name, "mthi") == 0)) | |
3771 | return 0; | |
3772 | ||
3773 | /* Search for the first MFLO or MFHI. */ | |
3774 | for (i = 0; i < MAX_VR4130_NOPS; i++) | |
91d6fa6a | 3775 | if (MF_HILO_INSN (hist[i].insn_mo->pinfo)) |
7d8e00cf RS |
3776 | { |
3777 | /* Extract the destination register. */ | |
4c260379 | 3778 | mask = gpr_write_mask (&hist[i]); |
7d8e00cf RS |
3779 | |
3780 | /* No nops are needed if INSN reads that register. */ | |
4c260379 | 3781 | if (insn != NULL && (gpr_read_mask (insn) & mask) != 0) |
7d8e00cf RS |
3782 | return 0; |
3783 | ||
3784 | /* ...or if any of the intervening instructions do. */ | |
3785 | for (j = 0; j < i; j++) | |
4c260379 | 3786 | if (gpr_read_mask (&hist[j]) & mask) |
7d8e00cf RS |
3787 | return 0; |
3788 | ||
932d1a1b RS |
3789 | if (i >= ignore) |
3790 | return MAX_VR4130_NOPS - i; | |
7d8e00cf RS |
3791 | } |
3792 | return 0; | |
3793 | } | |
3794 | ||
15be625d CM |
3795 | #define BASE_REG_EQ(INSN1, INSN2) \ |
3796 | ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \ | |
3797 | == (((INSN2) >> OP_SH_RS) & OP_MASK_RS)) | |
3798 | ||
3799 | /* Return the minimum alignment for this store instruction. */ | |
3800 | ||
3801 | static int | |
3802 | fix_24k_align_to (const struct mips_opcode *mo) | |
3803 | { | |
3804 | if (strcmp (mo->name, "sh") == 0) | |
3805 | return 2; | |
3806 | ||
3807 | if (strcmp (mo->name, "swc1") == 0 | |
3808 | || strcmp (mo->name, "swc2") == 0 | |
3809 | || strcmp (mo->name, "sw") == 0 | |
3810 | || strcmp (mo->name, "sc") == 0 | |
3811 | || strcmp (mo->name, "s.s") == 0) | |
3812 | return 4; | |
3813 | ||
3814 | if (strcmp (mo->name, "sdc1") == 0 | |
3815 | || strcmp (mo->name, "sdc2") == 0 | |
3816 | || strcmp (mo->name, "s.d") == 0) | |
3817 | return 8; | |
3818 | ||
3819 | /* sb, swl, swr */ | |
3820 | return 1; | |
3821 | } | |
3822 | ||
3823 | struct fix_24k_store_info | |
3824 | { | |
3825 | /* Immediate offset, if any, for this store instruction. */ | |
3826 | short off; | |
3827 | /* Alignment required by this store instruction. */ | |
3828 | int align_to; | |
3829 | /* True for register offsets. */ | |
3830 | int register_offset; | |
3831 | }; | |
3832 | ||
3833 | /* Comparison function used by qsort. */ | |
3834 | ||
3835 | static int | |
3836 | fix_24k_sort (const void *a, const void *b) | |
3837 | { | |
3838 | const struct fix_24k_store_info *pos1 = a; | |
3839 | const struct fix_24k_store_info *pos2 = b; | |
3840 | ||
3841 | return (pos1->off - pos2->off); | |
3842 | } | |
3843 | ||
3844 | /* INSN is a store instruction. Try to record the store information | |
3845 | in STINFO. Return false if the information isn't known. */ | |
3846 | ||
3847 | static bfd_boolean | |
3848 | fix_24k_record_store_info (struct fix_24k_store_info *stinfo, | |
ab9794cf | 3849 | const struct mips_cl_insn *insn) |
15be625d CM |
3850 | { |
3851 | /* The instruction must have a known offset. */ | |
3852 | if (!insn->complete_p || !strstr (insn->insn_mo->args, "o(")) | |
3853 | return FALSE; | |
3854 | ||
3855 | stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE; | |
3856 | stinfo->align_to = fix_24k_align_to (insn->insn_mo); | |
3857 | return TRUE; | |
3858 | } | |
3859 | ||
932d1a1b RS |
3860 | /* Return the number of nops that would be needed to work around the 24k |
3861 | "lost data on stores during refill" errata if instruction INSN | |
3862 | immediately followed the 2 instructions described by HIST. | |
3863 | Ignore hazards that are contained within the first IGNORE | |
3864 | instructions of HIST. | |
3865 | ||
3866 | Problem: The FSB (fetch store buffer) acts as an intermediate buffer | |
3867 | for the data cache refills and store data. The following describes | |
3868 | the scenario where the store data could be lost. | |
3869 | ||
3870 | * A data cache miss, due to either a load or a store, causing fill | |
3871 | data to be supplied by the memory subsystem | |
3872 | * The first three doublewords of fill data are returned and written | |
3873 | into the cache | |
3874 | * A sequence of four stores occurs in consecutive cycles around the | |
3875 | final doubleword of the fill: | |
3876 | * Store A | |
3877 | * Store B | |
3878 | * Store C | |
3879 | * Zero, One or more instructions | |
3880 | * Store D | |
3881 | ||
3882 | The four stores A-D must be to different doublewords of the line that | |
3883 | is being filled. The fourth instruction in the sequence above permits | |
3884 | the fill of the final doubleword to be transferred from the FSB into | |
3885 | the cache. In the sequence above, the stores may be either integer | |
3886 | (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2, | |
3887 | swxc1, sdxc1, suxc1) stores, as long as the four stores are to | |
3888 | different doublewords on the line. If the floating point unit is | |
3889 | running in 1:2 mode, it is not possible to create the sequence above | |
3890 | using only floating point store instructions. | |
15be625d CM |
3891 | |
3892 | In this case, the cache line being filled is incorrectly marked | |
3893 | invalid, thereby losing the data from any store to the line that | |
3894 | occurs between the original miss and the completion of the five | |
3895 | cycle sequence shown above. | |
3896 | ||
932d1a1b | 3897 | The workarounds are: |
15be625d | 3898 | |
932d1a1b RS |
3899 | * Run the data cache in write-through mode. |
3900 | * Insert a non-store instruction between | |
3901 | Store A and Store B or Store B and Store C. */ | |
15be625d CM |
3902 | |
3903 | static int | |
932d1a1b | 3904 | nops_for_24k (int ignore, const struct mips_cl_insn *hist, |
15be625d CM |
3905 | const struct mips_cl_insn *insn) |
3906 | { | |
3907 | struct fix_24k_store_info pos[3]; | |
3908 | int align, i, base_offset; | |
3909 | ||
932d1a1b RS |
3910 | if (ignore >= 2) |
3911 | return 0; | |
3912 | ||
ab9794cf RS |
3913 | /* If the previous instruction wasn't a store, there's nothing to |
3914 | worry about. */ | |
15be625d CM |
3915 | if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) |
3916 | return 0; | |
3917 | ||
ab9794cf RS |
3918 | /* If the instructions after the previous one are unknown, we have |
3919 | to assume the worst. */ | |
3920 | if (!insn) | |
15be625d CM |
3921 | return 1; |
3922 | ||
ab9794cf RS |
3923 | /* Check whether we are dealing with three consecutive stores. */ |
3924 | if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0 | |
3925 | || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) | |
15be625d CM |
3926 | return 0; |
3927 | ||
3928 | /* If we don't know the relationship between the store addresses, | |
3929 | assume the worst. */ | |
ab9794cf | 3930 | if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode) |
15be625d CM |
3931 | || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode)) |
3932 | return 1; | |
3933 | ||
3934 | if (!fix_24k_record_store_info (&pos[0], insn) | |
3935 | || !fix_24k_record_store_info (&pos[1], &hist[0]) | |
3936 | || !fix_24k_record_store_info (&pos[2], &hist[1])) | |
3937 | return 1; | |
3938 | ||
3939 | qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort); | |
3940 | ||
3941 | /* Pick a value of ALIGN and X such that all offsets are adjusted by | |
3942 | X bytes and such that the base register + X is known to be aligned | |
3943 | to align bytes. */ | |
3944 | ||
3945 | if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP) | |
3946 | align = 8; | |
3947 | else | |
3948 | { | |
3949 | align = pos[0].align_to; | |
3950 | base_offset = pos[0].off; | |
3951 | for (i = 1; i < 3; i++) | |
3952 | if (align < pos[i].align_to) | |
3953 | { | |
3954 | align = pos[i].align_to; | |
3955 | base_offset = pos[i].off; | |
3956 | } | |
3957 | for (i = 0; i < 3; i++) | |
3958 | pos[i].off -= base_offset; | |
3959 | } | |
3960 | ||
3961 | pos[0].off &= ~align + 1; | |
3962 | pos[1].off &= ~align + 1; | |
3963 | pos[2].off &= ~align + 1; | |
3964 | ||
3965 | /* If any two stores write to the same chunk, they also write to the | |
3966 | same doubleword. The offsets are still sorted at this point. */ | |
3967 | if (pos[0].off == pos[1].off || pos[1].off == pos[2].off) | |
3968 | return 0; | |
3969 | ||
3970 | /* A range of at least 9 bytes is needed for the stores to be in | |
3971 | non-overlapping doublewords. */ | |
3972 | if (pos[2].off - pos[0].off <= 8) | |
3973 | return 0; | |
3974 | ||
3975 | if (pos[2].off - pos[1].off >= 24 | |
3976 | || pos[1].off - pos[0].off >= 24 | |
3977 | || pos[2].off - pos[0].off >= 32) | |
3978 | return 0; | |
3979 | ||
3980 | return 1; | |
3981 | } | |
3982 | ||
71400594 | 3983 | /* Return the number of nops that would be needed if instruction INSN |
91d6fa6a | 3984 | immediately followed the MAX_NOPS instructions given by HIST, |
932d1a1b RS |
3985 | where HIST[0] is the most recent instruction. Ignore hazards |
3986 | between INSN and the first IGNORE instructions in HIST. | |
3987 | ||
3988 | If INSN is null, return the worse-case number of nops for any | |
3989 | instruction. */ | |
bdaaa2e1 | 3990 | |
71400594 | 3991 | static int |
932d1a1b | 3992 | nops_for_insn (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
3993 | const struct mips_cl_insn *insn) |
3994 | { | |
3995 | int i, nops, tmp_nops; | |
bdaaa2e1 | 3996 | |
71400594 | 3997 | nops = 0; |
932d1a1b | 3998 | for (i = ignore; i < MAX_DELAY_NOPS; i++) |
65b02341 | 3999 | { |
91d6fa6a | 4000 | tmp_nops = insns_between (hist + i, insn) - i; |
65b02341 RS |
4001 | if (tmp_nops > nops) |
4002 | nops = tmp_nops; | |
4003 | } | |
7d8e00cf | 4004 | |
df58fc94 | 4005 | if (mips_fix_vr4130 && !mips_opts.micromips) |
7d8e00cf | 4006 | { |
932d1a1b | 4007 | tmp_nops = nops_for_vr4130 (ignore, hist, insn); |
7d8e00cf RS |
4008 | if (tmp_nops > nops) |
4009 | nops = tmp_nops; | |
4010 | } | |
4011 | ||
df58fc94 | 4012 | if (mips_fix_24k && !mips_opts.micromips) |
15be625d | 4013 | { |
932d1a1b | 4014 | tmp_nops = nops_for_24k (ignore, hist, insn); |
15be625d CM |
4015 | if (tmp_nops > nops) |
4016 | nops = tmp_nops; | |
4017 | } | |
4018 | ||
71400594 RS |
4019 | return nops; |
4020 | } | |
252b5132 | 4021 | |
71400594 | 4022 | /* The variable arguments provide NUM_INSNS extra instructions that |
91d6fa6a | 4023 | might be added to HIST. Return the largest number of nops that |
932d1a1b RS |
4024 | would be needed after the extended sequence, ignoring hazards |
4025 | in the first IGNORE instructions. */ | |
252b5132 | 4026 | |
71400594 | 4027 | static int |
932d1a1b RS |
4028 | nops_for_sequence (int num_insns, int ignore, |
4029 | const struct mips_cl_insn *hist, ...) | |
71400594 RS |
4030 | { |
4031 | va_list args; | |
4032 | struct mips_cl_insn buffer[MAX_NOPS]; | |
4033 | struct mips_cl_insn *cursor; | |
4034 | int nops; | |
4035 | ||
91d6fa6a | 4036 | va_start (args, hist); |
71400594 | 4037 | cursor = buffer + num_insns; |
91d6fa6a | 4038 | memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor)); |
71400594 RS |
4039 | while (cursor > buffer) |
4040 | *--cursor = *va_arg (args, const struct mips_cl_insn *); | |
4041 | ||
932d1a1b | 4042 | nops = nops_for_insn (ignore, buffer, NULL); |
71400594 RS |
4043 | va_end (args); |
4044 | return nops; | |
4045 | } | |
252b5132 | 4046 | |
71400594 RS |
4047 | /* Like nops_for_insn, but if INSN is a branch, take into account the |
4048 | worst-case delay for the branch target. */ | |
252b5132 | 4049 | |
71400594 | 4050 | static int |
932d1a1b | 4051 | nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
4052 | const struct mips_cl_insn *insn) |
4053 | { | |
4054 | int nops, tmp_nops; | |
60b63b72 | 4055 | |
932d1a1b | 4056 | nops = nops_for_insn (ignore, hist, insn); |
11625dd8 | 4057 | if (delayed_branch_p (insn)) |
71400594 | 4058 | { |
932d1a1b | 4059 | tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0, |
14fe068b | 4060 | hist, insn, get_delay_slot_nop (insn)); |
71400594 RS |
4061 | if (tmp_nops > nops) |
4062 | nops = tmp_nops; | |
4063 | } | |
11625dd8 | 4064 | else if (compact_branch_p (insn)) |
71400594 | 4065 | { |
932d1a1b | 4066 | tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn); |
71400594 RS |
4067 | if (tmp_nops > nops) |
4068 | nops = tmp_nops; | |
4069 | } | |
4070 | return nops; | |
4071 | } | |
4072 | ||
c67a084a NC |
4073 | /* Fix NOP issue: Replace nops by "or at,at,zero". */ |
4074 | ||
4075 | static void | |
4076 | fix_loongson2f_nop (struct mips_cl_insn * ip) | |
4077 | { | |
df58fc94 | 4078 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
4079 | if (strcmp (ip->insn_mo->name, "nop") == 0) |
4080 | ip->insn_opcode = LOONGSON2F_NOP_INSN; | |
4081 | } | |
4082 | ||
4083 | /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region | |
4084 | jr target pc &= 'hffff_ffff_cfff_ffff. */ | |
4085 | ||
4086 | static void | |
4087 | fix_loongson2f_jump (struct mips_cl_insn * ip) | |
4088 | { | |
df58fc94 | 4089 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
4090 | if (strcmp (ip->insn_mo->name, "j") == 0 |
4091 | || strcmp (ip->insn_mo->name, "jr") == 0 | |
4092 | || strcmp (ip->insn_mo->name, "jalr") == 0) | |
4093 | { | |
4094 | int sreg; | |
4095 | expressionS ep; | |
4096 | ||
4097 | if (! mips_opts.at) | |
4098 | return; | |
4099 | ||
df58fc94 | 4100 | sreg = EXTRACT_OPERAND (0, RS, *ip); |
c67a084a NC |
4101 | if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG) |
4102 | return; | |
4103 | ||
4104 | ep.X_op = O_constant; | |
4105 | ep.X_add_number = 0xcfff0000; | |
4106 | macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16); | |
4107 | ep.X_add_number = 0xffff; | |
4108 | macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16); | |
4109 | macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG); | |
4110 | } | |
4111 | } | |
4112 | ||
4113 | static void | |
4114 | fix_loongson2f (struct mips_cl_insn * ip) | |
4115 | { | |
4116 | if (mips_fix_loongson2f_nop) | |
4117 | fix_loongson2f_nop (ip); | |
4118 | ||
4119 | if (mips_fix_loongson2f_jump) | |
4120 | fix_loongson2f_jump (ip); | |
4121 | } | |
4122 | ||
a4e06468 RS |
4123 | /* IP is a branch that has a delay slot, and we need to fill it |
4124 | automatically. Return true if we can do that by swapping IP | |
e407c74b NC |
4125 | with the previous instruction. |
4126 | ADDRESS_EXPR is an operand of the instruction to be used with | |
4127 | RELOC_TYPE. */ | |
a4e06468 RS |
4128 | |
4129 | static bfd_boolean | |
e407c74b NC |
4130 | can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr, |
4131 | bfd_reloc_code_real_type *reloc_type) | |
a4e06468 | 4132 | { |
2b0c8b40 | 4133 | unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2; |
a4e06468 RS |
4134 | unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write; |
4135 | ||
4136 | /* -O2 and above is required for this optimization. */ | |
4137 | if (mips_optimize < 2) | |
4138 | return FALSE; | |
4139 | ||
4140 | /* If we have seen .set volatile or .set nomove, don't optimize. */ | |
4141 | if (mips_opts.nomove) | |
4142 | return FALSE; | |
4143 | ||
4144 | /* We can't swap if the previous instruction's position is fixed. */ | |
4145 | if (history[0].fixed_p) | |
4146 | return FALSE; | |
4147 | ||
4148 | /* If the previous previous insn was in a .set noreorder, we can't | |
4149 | swap. Actually, the MIPS assembler will swap in this situation. | |
4150 | However, gcc configured -with-gnu-as will generate code like | |
4151 | ||
4152 | .set noreorder | |
4153 | lw $4,XXX | |
4154 | .set reorder | |
4155 | INSN | |
4156 | bne $4,$0,foo | |
4157 | ||
4158 | in which we can not swap the bne and INSN. If gcc is not configured | |
4159 | -with-gnu-as, it does not output the .set pseudo-ops. */ | |
4160 | if (history[1].noreorder_p) | |
4161 | return FALSE; | |
4162 | ||
87333bb7 MR |
4163 | /* If the previous instruction had a fixup in mips16 mode, we can not swap. |
4164 | This means that the previous instruction was a 4-byte one anyhow. */ | |
a4e06468 RS |
4165 | if (mips_opts.mips16 && history[0].fixp[0]) |
4166 | return FALSE; | |
4167 | ||
4168 | /* If the branch is itself the target of a branch, we can not swap. | |
4169 | We cheat on this; all we check for is whether there is a label on | |
4170 | this instruction. If there are any branches to anything other than | |
4171 | a label, users must use .set noreorder. */ | |
4172 | if (seg_info (now_seg)->label_list) | |
4173 | return FALSE; | |
4174 | ||
4175 | /* If the previous instruction is in a variant frag other than this | |
2309ddf2 | 4176 | branch's one, we cannot do the swap. This does not apply to |
9301f9c3 MR |
4177 | MIPS16 code, which uses variant frags for different purposes. */ |
4178 | if (!mips_opts.mips16 | |
a4e06468 RS |
4179 | && history[0].frag |
4180 | && history[0].frag->fr_type == rs_machine_dependent) | |
4181 | return FALSE; | |
4182 | ||
bcd530a7 RS |
4183 | /* We do not swap with instructions that cannot architecturally |
4184 | be placed in a branch delay slot, such as SYNC or ERET. We | |
4185 | also refrain from swapping with a trap instruction, since it | |
4186 | complicates trap handlers to have the trap instruction be in | |
4187 | a delay slot. */ | |
a4e06468 | 4188 | prev_pinfo = history[0].insn_mo->pinfo; |
bcd530a7 | 4189 | if (prev_pinfo & INSN_NO_DELAY_SLOT) |
a4e06468 RS |
4190 | return FALSE; |
4191 | ||
4192 | /* Check for conflicts between the branch and the instructions | |
4193 | before the candidate delay slot. */ | |
4194 | if (nops_for_insn (0, history + 1, ip) > 0) | |
4195 | return FALSE; | |
4196 | ||
4197 | /* Check for conflicts between the swapped sequence and the | |
4198 | target of the branch. */ | |
4199 | if (nops_for_sequence (2, 0, history + 1, ip, history) > 0) | |
4200 | return FALSE; | |
4201 | ||
4202 | /* If the branch reads a register that the previous | |
4203 | instruction sets, we can not swap. */ | |
4204 | gpr_read = gpr_read_mask (ip); | |
4205 | prev_gpr_write = gpr_write_mask (&history[0]); | |
4206 | if (gpr_read & prev_gpr_write) | |
4207 | return FALSE; | |
4208 | ||
4209 | /* If the branch writes a register that the previous | |
4210 | instruction sets, we can not swap. */ | |
4211 | gpr_write = gpr_write_mask (ip); | |
4212 | if (gpr_write & prev_gpr_write) | |
4213 | return FALSE; | |
4214 | ||
4215 | /* If the branch writes a register that the previous | |
4216 | instruction reads, we can not swap. */ | |
4217 | prev_gpr_read = gpr_read_mask (&history[0]); | |
4218 | if (gpr_write & prev_gpr_read) | |
4219 | return FALSE; | |
4220 | ||
4221 | /* If one instruction sets a condition code and the | |
4222 | other one uses a condition code, we can not swap. */ | |
4223 | pinfo = ip->insn_mo->pinfo; | |
4224 | if ((pinfo & INSN_READ_COND_CODE) | |
4225 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
4226 | return FALSE; | |
4227 | if ((pinfo & INSN_WRITE_COND_CODE) | |
4228 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
4229 | return FALSE; | |
4230 | ||
4231 | /* If the previous instruction uses the PC, we can not swap. */ | |
2b0c8b40 | 4232 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
a4e06468 RS |
4233 | if (mips_opts.mips16 && (prev_pinfo & MIPS16_INSN_READ_PC)) |
4234 | return FALSE; | |
2b0c8b40 MR |
4235 | if (mips_opts.micromips && (prev_pinfo2 & INSN2_READ_PC)) |
4236 | return FALSE; | |
a4e06468 | 4237 | |
df58fc94 RS |
4238 | /* If the previous instruction has an incorrect size for a fixed |
4239 | branch delay slot in microMIPS mode, we cannot swap. */ | |
2309ddf2 MR |
4240 | pinfo2 = ip->insn_mo->pinfo2; |
4241 | if (mips_opts.micromips | |
4242 | && (pinfo2 & INSN2_BRANCH_DELAY_16BIT) | |
4243 | && insn_length (history) != 2) | |
4244 | return FALSE; | |
4245 | if (mips_opts.micromips | |
4246 | && (pinfo2 & INSN2_BRANCH_DELAY_32BIT) | |
4247 | && insn_length (history) != 4) | |
4248 | return FALSE; | |
4249 | ||
e407c74b NC |
4250 | /* On R5900 short loops need to be fixed by inserting a nop in |
4251 | the branch delay slots. | |
4252 | A short loop can be terminated too early. */ | |
4253 | if (mips_opts.arch == CPU_R5900 | |
4254 | /* Check if instruction has a parameter, ignore "j $31". */ | |
4255 | && (address_expr != NULL) | |
4256 | /* Parameter must be 16 bit. */ | |
4257 | && (*reloc_type == BFD_RELOC_16_PCREL_S2) | |
4258 | /* Branch to same segment. */ | |
4259 | && (S_GET_SEGMENT(address_expr->X_add_symbol) == now_seg) | |
4260 | /* Branch to same code fragment. */ | |
4261 | && (symbol_get_frag(address_expr->X_add_symbol) == frag_now) | |
4262 | /* Can only calculate branch offset if value is known. */ | |
4263 | && symbol_constant_p(address_expr->X_add_symbol) | |
4264 | /* Check if branch is really conditional. */ | |
4265 | && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
4266 | || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
4267 | || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
4268 | { | |
4269 | int distance; | |
4270 | /* Check if loop is shorter than 6 instructions including | |
4271 | branch and delay slot. */ | |
4272 | distance = frag_now_fix() - S_GET_VALUE(address_expr->X_add_symbol); | |
4273 | if (distance <= 20) | |
4274 | { | |
4275 | int i; | |
4276 | int rv; | |
4277 | ||
4278 | rv = FALSE; | |
4279 | /* When the loop includes branches or jumps, | |
4280 | it is not a short loop. */ | |
4281 | for (i = 0; i < (distance / 4); i++) | |
4282 | { | |
4283 | if ((history[i].cleared_p) | |
4284 | || delayed_branch_p(&history[i])) | |
4285 | { | |
4286 | rv = TRUE; | |
4287 | break; | |
4288 | } | |
4289 | } | |
4290 | if (rv == FALSE) | |
4291 | { | |
4292 | /* Insert nop after branch to fix short loop. */ | |
4293 | return FALSE; | |
4294 | } | |
4295 | } | |
4296 | } | |
4297 | ||
a4e06468 RS |
4298 | return TRUE; |
4299 | } | |
4300 | ||
e407c74b NC |
4301 | /* Decide how we should add IP to the instruction stream. |
4302 | ADDRESS_EXPR is an operand of the instruction to be used with | |
4303 | RELOC_TYPE. */ | |
a4e06468 RS |
4304 | |
4305 | static enum append_method | |
e407c74b NC |
4306 | get_append_method (struct mips_cl_insn *ip, expressionS *address_expr, |
4307 | bfd_reloc_code_real_type *reloc_type) | |
a4e06468 RS |
4308 | { |
4309 | unsigned long pinfo; | |
4310 | ||
4311 | /* The relaxed version of a macro sequence must be inherently | |
4312 | hazard-free. */ | |
4313 | if (mips_relax.sequence == 2) | |
4314 | return APPEND_ADD; | |
4315 | ||
4316 | /* We must not dabble with instructions in a ".set norerorder" block. */ | |
4317 | if (mips_opts.noreorder) | |
4318 | return APPEND_ADD; | |
4319 | ||
4320 | /* Otherwise, it's our responsibility to fill branch delay slots. */ | |
11625dd8 | 4321 | if (delayed_branch_p (ip)) |
a4e06468 | 4322 | { |
e407c74b NC |
4323 | if (!branch_likely_p (ip) |
4324 | && can_swap_branch_p (ip, address_expr, reloc_type)) | |
a4e06468 RS |
4325 | return APPEND_SWAP; |
4326 | ||
11625dd8 | 4327 | pinfo = ip->insn_mo->pinfo; |
a4e06468 RS |
4328 | if (mips_opts.mips16 |
4329 | && ISA_SUPPORTS_MIPS16E | |
a4e06468 RS |
4330 | && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31))) |
4331 | return APPEND_ADD_COMPACT; | |
4332 | ||
4333 | return APPEND_ADD_WITH_NOP; | |
4334 | } | |
4335 | ||
a4e06468 RS |
4336 | return APPEND_ADD; |
4337 | } | |
4338 | ||
ceb94aa5 RS |
4339 | /* IP is a MIPS16 instruction whose opcode we have just changed. |
4340 | Point IP->insn_mo to the new opcode's definition. */ | |
4341 | ||
4342 | static void | |
4343 | find_altered_mips16_opcode (struct mips_cl_insn *ip) | |
4344 | { | |
4345 | const struct mips_opcode *mo, *end; | |
4346 | ||
4347 | end = &mips16_opcodes[bfd_mips16_num_opcodes]; | |
4348 | for (mo = ip->insn_mo; mo < end; mo++) | |
4349 | if ((ip->insn_opcode & mo->mask) == mo->match) | |
4350 | { | |
4351 | ip->insn_mo = mo; | |
4352 | return; | |
4353 | } | |
4354 | abort (); | |
4355 | } | |
4356 | ||
df58fc94 RS |
4357 | /* For microMIPS macros, we need to generate a local number label |
4358 | as the target of branches. */ | |
4359 | #define MICROMIPS_LABEL_CHAR '\037' | |
4360 | static unsigned long micromips_target_label; | |
4361 | static char micromips_target_name[32]; | |
4362 | ||
4363 | static char * | |
4364 | micromips_label_name (void) | |
4365 | { | |
4366 | char *p = micromips_target_name; | |
4367 | char symbol_name_temporary[24]; | |
4368 | unsigned long l; | |
4369 | int i; | |
4370 | ||
4371 | if (*p) | |
4372 | return p; | |
4373 | ||
4374 | i = 0; | |
4375 | l = micromips_target_label; | |
4376 | #ifdef LOCAL_LABEL_PREFIX | |
4377 | *p++ = LOCAL_LABEL_PREFIX; | |
4378 | #endif | |
4379 | *p++ = 'L'; | |
4380 | *p++ = MICROMIPS_LABEL_CHAR; | |
4381 | do | |
4382 | { | |
4383 | symbol_name_temporary[i++] = l % 10 + '0'; | |
4384 | l /= 10; | |
4385 | } | |
4386 | while (l != 0); | |
4387 | while (i > 0) | |
4388 | *p++ = symbol_name_temporary[--i]; | |
4389 | *p = '\0'; | |
4390 | ||
4391 | return micromips_target_name; | |
4392 | } | |
4393 | ||
4394 | static void | |
4395 | micromips_label_expr (expressionS *label_expr) | |
4396 | { | |
4397 | label_expr->X_op = O_symbol; | |
4398 | label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ()); | |
4399 | label_expr->X_add_number = 0; | |
4400 | } | |
4401 | ||
4402 | static void | |
4403 | micromips_label_inc (void) | |
4404 | { | |
4405 | micromips_target_label++; | |
4406 | *micromips_target_name = '\0'; | |
4407 | } | |
4408 | ||
4409 | static void | |
4410 | micromips_add_label (void) | |
4411 | { | |
4412 | symbolS *s; | |
4413 | ||
4414 | s = colon (micromips_label_name ()); | |
4415 | micromips_label_inc (); | |
f3ded42a | 4416 | S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s))); |
df58fc94 RS |
4417 | } |
4418 | ||
4419 | /* If assembling microMIPS code, then return the microMIPS reloc | |
4420 | corresponding to the requested one if any. Otherwise return | |
4421 | the reloc unchanged. */ | |
4422 | ||
4423 | static bfd_reloc_code_real_type | |
4424 | micromips_map_reloc (bfd_reloc_code_real_type reloc) | |
4425 | { | |
4426 | static const bfd_reloc_code_real_type relocs[][2] = | |
4427 | { | |
4428 | /* Keep sorted incrementally by the left-hand key. */ | |
4429 | { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 }, | |
4430 | { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 }, | |
4431 | { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP }, | |
4432 | { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 }, | |
4433 | { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S }, | |
4434 | { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 }, | |
4435 | { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL }, | |
4436 | { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 }, | |
4437 | { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 }, | |
4438 | { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 }, | |
4439 | { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 }, | |
4440 | { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 }, | |
4441 | { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 }, | |
4442 | { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB }, | |
4443 | { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE }, | |
4444 | { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST }, | |
4445 | { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP }, | |
4446 | { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST }, | |
4447 | { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER }, | |
4448 | { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP }, | |
4449 | { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD }, | |
4450 | { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM }, | |
4451 | { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 }, | |
4452 | { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 }, | |
4453 | { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL }, | |
4454 | { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 }, | |
4455 | { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 } | |
4456 | }; | |
4457 | bfd_reloc_code_real_type r; | |
4458 | size_t i; | |
4459 | ||
4460 | if (!mips_opts.micromips) | |
4461 | return reloc; | |
4462 | for (i = 0; i < ARRAY_SIZE (relocs); i++) | |
4463 | { | |
4464 | r = relocs[i][0]; | |
4465 | if (r > reloc) | |
4466 | return reloc; | |
4467 | if (r == reloc) | |
4468 | return relocs[i][1]; | |
4469 | } | |
4470 | return reloc; | |
4471 | } | |
4472 | ||
b886a2ab RS |
4473 | /* Try to resolve relocation RELOC against constant OPERAND at assembly time. |
4474 | Return true on success, storing the resolved value in RESULT. */ | |
4475 | ||
4476 | static bfd_boolean | |
4477 | calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand, | |
4478 | offsetT *result) | |
4479 | { | |
4480 | switch (reloc) | |
4481 | { | |
4482 | case BFD_RELOC_MIPS_HIGHEST: | |
4483 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
4484 | *result = ((operand + 0x800080008000ull) >> 48) & 0xffff; | |
4485 | return TRUE; | |
4486 | ||
4487 | case BFD_RELOC_MIPS_HIGHER: | |
4488 | case BFD_RELOC_MICROMIPS_HIGHER: | |
4489 | *result = ((operand + 0x80008000ull) >> 32) & 0xffff; | |
4490 | return TRUE; | |
4491 | ||
4492 | case BFD_RELOC_HI16_S: | |
4493 | case BFD_RELOC_MICROMIPS_HI16_S: | |
4494 | case BFD_RELOC_MIPS16_HI16_S: | |
4495 | *result = ((operand + 0x8000) >> 16) & 0xffff; | |
4496 | return TRUE; | |
4497 | ||
4498 | case BFD_RELOC_HI16: | |
4499 | case BFD_RELOC_MICROMIPS_HI16: | |
4500 | case BFD_RELOC_MIPS16_HI16: | |
4501 | *result = (operand >> 16) & 0xffff; | |
4502 | return TRUE; | |
4503 | ||
4504 | case BFD_RELOC_LO16: | |
4505 | case BFD_RELOC_MICROMIPS_LO16: | |
4506 | case BFD_RELOC_MIPS16_LO16: | |
4507 | *result = operand & 0xffff; | |
4508 | return TRUE; | |
4509 | ||
4510 | case BFD_RELOC_UNUSED: | |
4511 | *result = operand; | |
4512 | return TRUE; | |
4513 | ||
4514 | default: | |
4515 | return FALSE; | |
4516 | } | |
4517 | } | |
4518 | ||
71400594 RS |
4519 | /* Output an instruction. IP is the instruction information. |
4520 | ADDRESS_EXPR is an operand of the instruction to be used with | |
df58fc94 RS |
4521 | RELOC_TYPE. EXPANSIONP is true if the instruction is part of |
4522 | a macro expansion. */ | |
71400594 RS |
4523 | |
4524 | static void | |
4525 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
df58fc94 | 4526 | bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp) |
71400594 | 4527 | { |
14fe068b | 4528 | unsigned long prev_pinfo2, pinfo; |
71400594 | 4529 | bfd_boolean relaxed_branch = FALSE; |
a4e06468 | 4530 | enum append_method method; |
2309ddf2 | 4531 | bfd_boolean relax32; |
2b0c8b40 | 4532 | int branch_disp; |
71400594 | 4533 | |
2309ddf2 | 4534 | if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION) |
c67a084a NC |
4535 | fix_loongson2f (ip); |
4536 | ||
738f4d98 | 4537 | file_ase_mips16 |= mips_opts.mips16; |
df58fc94 | 4538 | file_ase_micromips |= mips_opts.micromips; |
738f4d98 | 4539 | |
df58fc94 | 4540 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
71400594 | 4541 | pinfo = ip->insn_mo->pinfo; |
df58fc94 RS |
4542 | |
4543 | if (mips_opts.micromips | |
4544 | && !expansionp | |
4545 | && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 | |
4546 | && micromips_insn_length (ip->insn_mo) != 2) | |
4547 | || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 | |
4548 | && micromips_insn_length (ip->insn_mo) != 4))) | |
4549 | as_warn (_("Wrong size instruction in a %u-bit branch delay slot"), | |
4550 | (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32); | |
71400594 | 4551 | |
15be625d CM |
4552 | if (address_expr == NULL) |
4553 | ip->complete_p = 1; | |
b886a2ab RS |
4554 | else if (reloc_type[0] <= BFD_RELOC_UNUSED |
4555 | && reloc_type[1] == BFD_RELOC_UNUSED | |
4556 | && reloc_type[2] == BFD_RELOC_UNUSED | |
15be625d CM |
4557 | && address_expr->X_op == O_constant) |
4558 | { | |
15be625d CM |
4559 | switch (*reloc_type) |
4560 | { | |
15be625d | 4561 | case BFD_RELOC_MIPS_JMP: |
df58fc94 RS |
4562 | { |
4563 | int shift; | |
4564 | ||
4565 | shift = mips_opts.micromips ? 1 : 2; | |
4566 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
4567 | as_bad (_("jump to misaligned address (0x%lx)"), | |
4568 | (unsigned long) address_expr->X_add_number); | |
4569 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
4570 | & 0x3ffffff); | |
335574df | 4571 | ip->complete_p = 1; |
df58fc94 | 4572 | } |
15be625d CM |
4573 | break; |
4574 | ||
4575 | case BFD_RELOC_MIPS16_JMP: | |
4576 | if ((address_expr->X_add_number & 3) != 0) | |
4577 | as_bad (_("jump to misaligned address (0x%lx)"), | |
4578 | (unsigned long) address_expr->X_add_number); | |
4579 | ip->insn_opcode |= | |
4580 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
4581 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
4582 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
335574df | 4583 | ip->complete_p = 1; |
15be625d CM |
4584 | break; |
4585 | ||
4586 | case BFD_RELOC_16_PCREL_S2: | |
df58fc94 RS |
4587 | { |
4588 | int shift; | |
4589 | ||
4590 | shift = mips_opts.micromips ? 1 : 2; | |
4591 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
4592 | as_bad (_("branch to misaligned address (0x%lx)"), | |
4593 | (unsigned long) address_expr->X_add_number); | |
4594 | if (!mips_relax_branch) | |
4595 | { | |
4596 | if ((address_expr->X_add_number + (1 << (shift + 15))) | |
4597 | & ~((1 << (shift + 16)) - 1)) | |
4598 | as_bad (_("branch address range overflow (0x%lx)"), | |
4599 | (unsigned long) address_expr->X_add_number); | |
4600 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
4601 | & 0xffff); | |
4602 | } | |
df58fc94 | 4603 | } |
15be625d CM |
4604 | break; |
4605 | ||
4606 | default: | |
b886a2ab RS |
4607 | { |
4608 | offsetT value; | |
4609 | ||
4610 | if (calculate_reloc (*reloc_type, address_expr->X_add_number, | |
4611 | &value)) | |
4612 | { | |
4613 | ip->insn_opcode |= value & 0xffff; | |
4614 | ip->complete_p = 1; | |
4615 | } | |
4616 | } | |
4617 | break; | |
4618 | } | |
15be625d CM |
4619 | } |
4620 | ||
71400594 RS |
4621 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
4622 | { | |
4623 | /* There are a lot of optimizations we could do that we don't. | |
4624 | In particular, we do not, in general, reorder instructions. | |
4625 | If you use gcc with optimization, it will reorder | |
4626 | instructions and generally do much more optimization then we | |
4627 | do here; repeating all that work in the assembler would only | |
4628 | benefit hand written assembly code, and does not seem worth | |
4629 | it. */ | |
4630 | int nops = (mips_optimize == 0 | |
932d1a1b RS |
4631 | ? nops_for_insn (0, history, NULL) |
4632 | : nops_for_insn_or_target (0, history, ip)); | |
71400594 | 4633 | if (nops > 0) |
252b5132 RH |
4634 | { |
4635 | fragS *old_frag; | |
4636 | unsigned long old_frag_offset; | |
4637 | int i; | |
252b5132 RH |
4638 | |
4639 | old_frag = frag_now; | |
4640 | old_frag_offset = frag_now_fix (); | |
4641 | ||
4642 | for (i = 0; i < nops; i++) | |
14fe068b RS |
4643 | add_fixed_insn (NOP_INSN); |
4644 | insert_into_history (0, nops, NOP_INSN); | |
252b5132 RH |
4645 | |
4646 | if (listing) | |
4647 | { | |
4648 | listing_prev_line (); | |
4649 | /* We may be at the start of a variant frag. In case we | |
4650 | are, make sure there is enough space for the frag | |
4651 | after the frags created by listing_prev_line. The | |
4652 | argument to frag_grow here must be at least as large | |
4653 | as the argument to all other calls to frag_grow in | |
4654 | this file. We don't have to worry about being in the | |
4655 | middle of a variant frag, because the variants insert | |
4656 | all needed nop instructions themselves. */ | |
4657 | frag_grow (40); | |
4658 | } | |
4659 | ||
462427c4 | 4660 | mips_move_text_labels (); |
252b5132 RH |
4661 | |
4662 | #ifndef NO_ECOFF_DEBUGGING | |
4663 | if (ECOFF_DEBUGGING) | |
4664 | ecoff_fix_loc (old_frag, old_frag_offset); | |
4665 | #endif | |
4666 | } | |
71400594 RS |
4667 | } |
4668 | else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) | |
4669 | { | |
932d1a1b RS |
4670 | int nops; |
4671 | ||
4672 | /* Work out how many nops in prev_nop_frag are needed by IP, | |
4673 | ignoring hazards generated by the first prev_nop_frag_since | |
4674 | instructions. */ | |
4675 | nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip); | |
9c2799c2 | 4676 | gas_assert (nops <= prev_nop_frag_holds); |
252b5132 | 4677 | |
71400594 RS |
4678 | /* Enforce NOPS as a minimum. */ |
4679 | if (nops > prev_nop_frag_required) | |
4680 | prev_nop_frag_required = nops; | |
252b5132 | 4681 | |
71400594 RS |
4682 | if (prev_nop_frag_holds == prev_nop_frag_required) |
4683 | { | |
4684 | /* Settle for the current number of nops. Update the history | |
4685 | accordingly (for the benefit of any future .set reorder code). */ | |
4686 | prev_nop_frag = NULL; | |
4687 | insert_into_history (prev_nop_frag_since, | |
4688 | prev_nop_frag_holds, NOP_INSN); | |
4689 | } | |
4690 | else | |
4691 | { | |
4692 | /* Allow this instruction to replace one of the nops that was | |
4693 | tentatively added to prev_nop_frag. */ | |
df58fc94 | 4694 | prev_nop_frag->fr_fix -= NOP_INSN_SIZE; |
71400594 RS |
4695 | prev_nop_frag_holds--; |
4696 | prev_nop_frag_since++; | |
252b5132 RH |
4697 | } |
4698 | } | |
4699 | ||
e407c74b | 4700 | method = get_append_method (ip, address_expr, reloc_type); |
2b0c8b40 | 4701 | branch_disp = method == APPEND_SWAP ? insn_length (history) : 0; |
a4e06468 | 4702 | |
e410add4 RS |
4703 | dwarf2_emit_insn (0); |
4704 | /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses, | |
4705 | so "move" the instruction address accordingly. | |
4706 | ||
4707 | Also, it doesn't seem appropriate for the assembler to reorder .loc | |
4708 | entries. If this instruction is a branch that we are going to swap | |
4709 | with the previous instruction, the two instructions should be | |
4710 | treated as a unit, and the debug information for both instructions | |
4711 | should refer to the start of the branch sequence. Using the | |
4712 | current position is certainly wrong when swapping a 32-bit branch | |
4713 | and a 16-bit delay slot, since the current position would then be | |
4714 | in the middle of a branch. */ | |
4715 | dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp); | |
58e2ea4d | 4716 | |
df58fc94 RS |
4717 | relax32 = (mips_relax_branch |
4718 | /* Don't try branch relaxation within .set nomacro, or within | |
4719 | .set noat if we use $at for PIC computations. If it turns | |
4720 | out that the branch was out-of-range, we'll get an error. */ | |
4721 | && !mips_opts.warn_about_macros | |
4722 | && (mips_opts.at || mips_pic == NO_PIC) | |
3bf0dbfb MR |
4723 | /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F |
4724 | as they have no complementing branches. */ | |
4725 | && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP))); | |
df58fc94 RS |
4726 | |
4727 | if (!HAVE_CODE_COMPRESSION | |
4728 | && address_expr | |
4729 | && relax32 | |
0b25d3e6 | 4730 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
11625dd8 | 4731 | && delayed_branch_p (ip)) |
4a6a3df4 | 4732 | { |
895921c9 | 4733 | relaxed_branch = TRUE; |
1e915849 RS |
4734 | add_relaxed_insn (ip, (relaxed_branch_length |
4735 | (NULL, NULL, | |
11625dd8 RS |
4736 | uncond_branch_p (ip) ? -1 |
4737 | : branch_likely_p (ip) ? 1 | |
1e915849 RS |
4738 | : 0)), 4, |
4739 | RELAX_BRANCH_ENCODE | |
66b3e8da | 4740 | (AT, |
11625dd8 RS |
4741 | uncond_branch_p (ip), |
4742 | branch_likely_p (ip), | |
1e915849 RS |
4743 | pinfo & INSN_WRITE_GPR_31, |
4744 | 0), | |
4745 | address_expr->X_add_symbol, | |
4746 | address_expr->X_add_number); | |
4a6a3df4 AO |
4747 | *reloc_type = BFD_RELOC_UNUSED; |
4748 | } | |
df58fc94 RS |
4749 | else if (mips_opts.micromips |
4750 | && address_expr | |
4751 | && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2) | |
4752 | || *reloc_type > BFD_RELOC_UNUSED) | |
40209cad MR |
4753 | && (delayed_branch_p (ip) || compact_branch_p (ip)) |
4754 | /* Don't try branch relaxation when users specify | |
4755 | 16-bit/32-bit instructions. */ | |
4756 | && !forced_insn_length) | |
df58fc94 RS |
4757 | { |
4758 | bfd_boolean relax16 = *reloc_type > BFD_RELOC_UNUSED; | |
4759 | int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0; | |
11625dd8 RS |
4760 | int uncond = uncond_branch_p (ip) ? -1 : 0; |
4761 | int compact = compact_branch_p (ip); | |
df58fc94 RS |
4762 | int al = pinfo & INSN_WRITE_GPR_31; |
4763 | int length32; | |
4764 | ||
4765 | gas_assert (address_expr != NULL); | |
4766 | gas_assert (!mips_relax.sequence); | |
4767 | ||
2b0c8b40 | 4768 | relaxed_branch = TRUE; |
df58fc94 RS |
4769 | length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond); |
4770 | add_relaxed_insn (ip, relax32 ? length32 : 4, relax16 ? 2 : 4, | |
40209cad MR |
4771 | RELAX_MICROMIPS_ENCODE (type, AT, uncond, compact, al, |
4772 | relax32, 0, 0), | |
df58fc94 RS |
4773 | address_expr->X_add_symbol, |
4774 | address_expr->X_add_number); | |
4775 | *reloc_type = BFD_RELOC_UNUSED; | |
4776 | } | |
4777 | else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED) | |
252b5132 RH |
4778 | { |
4779 | /* We need to set up a variant frag. */ | |
df58fc94 | 4780 | gas_assert (address_expr != NULL); |
1e915849 RS |
4781 | add_relaxed_insn (ip, 4, 0, |
4782 | RELAX_MIPS16_ENCODE | |
4783 | (*reloc_type - BFD_RELOC_UNUSED, | |
df58fc94 | 4784 | forced_insn_length == 2, forced_insn_length == 4, |
11625dd8 | 4785 | delayed_branch_p (&history[0]), |
1e915849 RS |
4786 | history[0].mips16_absolute_jump_p), |
4787 | make_expr_symbol (address_expr), 0); | |
252b5132 | 4788 | } |
5c04167a | 4789 | else if (mips_opts.mips16 && insn_length (ip) == 2) |
9497f5ac | 4790 | { |
11625dd8 | 4791 | if (!delayed_branch_p (ip)) |
b8ee1a6e DU |
4792 | /* Make sure there is enough room to swap this instruction with |
4793 | a following jump instruction. */ | |
4794 | frag_grow (6); | |
1e915849 | 4795 | add_fixed_insn (ip); |
252b5132 RH |
4796 | } |
4797 | else | |
4798 | { | |
4799 | if (mips_opts.mips16 | |
4800 | && mips_opts.noreorder | |
11625dd8 | 4801 | && delayed_branch_p (&history[0])) |
252b5132 RH |
4802 | as_warn (_("extended instruction in delay slot")); |
4803 | ||
4d7206a2 RS |
4804 | if (mips_relax.sequence) |
4805 | { | |
4806 | /* If we've reached the end of this frag, turn it into a variant | |
4807 | frag and record the information for the instructions we've | |
4808 | written so far. */ | |
4809 | if (frag_room () < 4) | |
4810 | relax_close_frag (); | |
df58fc94 | 4811 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip); |
4d7206a2 RS |
4812 | } |
4813 | ||
584892a6 | 4814 | if (mips_relax.sequence != 2) |
df58fc94 RS |
4815 | { |
4816 | if (mips_macro_warning.first_insn_sizes[0] == 0) | |
4817 | mips_macro_warning.first_insn_sizes[0] = insn_length (ip); | |
4818 | mips_macro_warning.sizes[0] += insn_length (ip); | |
4819 | mips_macro_warning.insns[0]++; | |
4820 | } | |
584892a6 | 4821 | if (mips_relax.sequence != 1) |
df58fc94 RS |
4822 | { |
4823 | if (mips_macro_warning.first_insn_sizes[1] == 0) | |
4824 | mips_macro_warning.first_insn_sizes[1] = insn_length (ip); | |
4825 | mips_macro_warning.sizes[1] += insn_length (ip); | |
4826 | mips_macro_warning.insns[1]++; | |
4827 | } | |
584892a6 | 4828 | |
1e915849 RS |
4829 | if (mips_opts.mips16) |
4830 | { | |
4831 | ip->fixed_p = 1; | |
4832 | ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); | |
4833 | } | |
4834 | add_fixed_insn (ip); | |
252b5132 RH |
4835 | } |
4836 | ||
9fe77896 | 4837 | if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 4838 | { |
df58fc94 | 4839 | bfd_reloc_code_real_type final_type[3]; |
2309ddf2 | 4840 | reloc_howto_type *howto0; |
9fe77896 RS |
4841 | reloc_howto_type *howto; |
4842 | int i; | |
34ce925e | 4843 | |
df58fc94 RS |
4844 | /* Perform any necessary conversion to microMIPS relocations |
4845 | and find out how many relocations there actually are. */ | |
4846 | for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++) | |
4847 | final_type[i] = micromips_map_reloc (reloc_type[i]); | |
4848 | ||
9fe77896 RS |
4849 | /* In a compound relocation, it is the final (outermost) |
4850 | operator that determines the relocated field. */ | |
2309ddf2 | 4851 | howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]); |
e8044f35 RS |
4852 | if (!howto) |
4853 | abort (); | |
2309ddf2 MR |
4854 | |
4855 | if (i > 1) | |
4856 | howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]); | |
9fe77896 RS |
4857 | ip->fixp[0] = fix_new_exp (ip->frag, ip->where, |
4858 | bfd_get_reloc_size (howto), | |
4859 | address_expr, | |
2309ddf2 MR |
4860 | howto0 && howto0->pc_relative, |
4861 | final_type[0]); | |
9fe77896 RS |
4862 | |
4863 | /* Tag symbols that have a R_MIPS16_26 relocation against them. */ | |
2309ddf2 | 4864 | if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy) |
9fe77896 RS |
4865 | *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1; |
4866 | ||
4867 | /* These relocations can have an addend that won't fit in | |
4868 | 4 octets for 64bit assembly. */ | |
4869 | if (HAVE_64BIT_GPRS | |
4870 | && ! howto->partial_inplace | |
4871 | && (reloc_type[0] == BFD_RELOC_16 | |
4872 | || reloc_type[0] == BFD_RELOC_32 | |
4873 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
4874 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
4875 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
4876 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
4877 | || reloc_type[0] == BFD_RELOC_64 | |
4878 | || reloc_type[0] == BFD_RELOC_CTOR | |
4879 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
4880 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
4881 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
4882 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
4883 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
4884 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT | |
4885 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
4886 | || hi16_reloc_p (reloc_type[0]) | |
4887 | || lo16_reloc_p (reloc_type[0]))) | |
4888 | ip->fixp[0]->fx_no_overflow = 1; | |
4889 | ||
ddaf2c41 MR |
4890 | /* These relocations can have an addend that won't fit in 2 octets. */ |
4891 | if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
4892 | || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1) | |
4893 | ip->fixp[0]->fx_no_overflow = 1; | |
4894 | ||
9fe77896 RS |
4895 | if (mips_relax.sequence) |
4896 | { | |
4897 | if (mips_relax.first_fixup == 0) | |
4898 | mips_relax.first_fixup = ip->fixp[0]; | |
4899 | } | |
4900 | else if (reloc_needs_lo_p (*reloc_type)) | |
4901 | { | |
4902 | struct mips_hi_fixup *hi_fixup; | |
4903 | ||
4904 | /* Reuse the last entry if it already has a matching %lo. */ | |
4905 | hi_fixup = mips_hi_fixup_list; | |
4906 | if (hi_fixup == 0 | |
4907 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
4d7206a2 | 4908 | { |
9fe77896 RS |
4909 | hi_fixup = ((struct mips_hi_fixup *) |
4910 | xmalloc (sizeof (struct mips_hi_fixup))); | |
4911 | hi_fixup->next = mips_hi_fixup_list; | |
4912 | mips_hi_fixup_list = hi_fixup; | |
4d7206a2 | 4913 | } |
9fe77896 RS |
4914 | hi_fixup->fixp = ip->fixp[0]; |
4915 | hi_fixup->seg = now_seg; | |
4916 | } | |
252b5132 | 4917 | |
9fe77896 RS |
4918 | /* Add fixups for the second and third relocations, if given. |
4919 | Note that the ABI allows the second relocation to be | |
4920 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
4921 | moment we only use RSS_UNDEF, but we could add support | |
4922 | for the others if it ever becomes necessary. */ | |
4923 | for (i = 1; i < 3; i++) | |
4924 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
4925 | { | |
4926 | ip->fixp[i] = fix_new (ip->frag, ip->where, | |
4927 | ip->fixp[0]->fx_size, NULL, 0, | |
df58fc94 | 4928 | FALSE, final_type[i]); |
f6688943 | 4929 | |
9fe77896 RS |
4930 | /* Use fx_tcbit to mark compound relocs. */ |
4931 | ip->fixp[0]->fx_tcbit = 1; | |
4932 | ip->fixp[i]->fx_tcbit = 1; | |
4933 | } | |
252b5132 | 4934 | } |
1e915849 | 4935 | install_insn (ip); |
252b5132 RH |
4936 | |
4937 | /* Update the register mask information. */ | |
4c260379 RS |
4938 | mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip); |
4939 | mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip); | |
252b5132 | 4940 | |
a4e06468 | 4941 | switch (method) |
252b5132 | 4942 | { |
a4e06468 RS |
4943 | case APPEND_ADD: |
4944 | insert_into_history (0, 1, ip); | |
4945 | break; | |
4946 | ||
4947 | case APPEND_ADD_WITH_NOP: | |
14fe068b RS |
4948 | { |
4949 | struct mips_cl_insn *nop; | |
4950 | ||
4951 | insert_into_history (0, 1, ip); | |
4952 | nop = get_delay_slot_nop (ip); | |
4953 | add_fixed_insn (nop); | |
4954 | insert_into_history (0, 1, nop); | |
4955 | if (mips_relax.sequence) | |
4956 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop); | |
4957 | } | |
a4e06468 RS |
4958 | break; |
4959 | ||
4960 | case APPEND_ADD_COMPACT: | |
4961 | /* Convert MIPS16 jr/jalr into a "compact" jump. */ | |
4962 | gas_assert (mips_opts.mips16); | |
4963 | ip->insn_opcode |= 0x0080; | |
4964 | find_altered_mips16_opcode (ip); | |
4965 | install_insn (ip); | |
4966 | insert_into_history (0, 1, ip); | |
4967 | break; | |
4968 | ||
4969 | case APPEND_SWAP: | |
4970 | { | |
4971 | struct mips_cl_insn delay = history[0]; | |
4972 | if (mips_opts.mips16) | |
4973 | { | |
4974 | know (delay.frag == ip->frag); | |
4975 | move_insn (ip, delay.frag, delay.where); | |
4976 | move_insn (&delay, ip->frag, ip->where + insn_length (ip)); | |
4977 | } | |
464ab0e5 | 4978 | else if (relaxed_branch || delay.frag != ip->frag) |
a4e06468 RS |
4979 | { |
4980 | /* Add the delay slot instruction to the end of the | |
4981 | current frag and shrink the fixed part of the | |
4982 | original frag. If the branch occupies the tail of | |
4983 | the latter, move it backwards to cover the gap. */ | |
2b0c8b40 | 4984 | delay.frag->fr_fix -= branch_disp; |
a4e06468 | 4985 | if (delay.frag == ip->frag) |
2b0c8b40 | 4986 | move_insn (ip, ip->frag, ip->where - branch_disp); |
a4e06468 RS |
4987 | add_fixed_insn (&delay); |
4988 | } | |
4989 | else | |
4990 | { | |
2b0c8b40 MR |
4991 | move_insn (&delay, ip->frag, |
4992 | ip->where - branch_disp + insn_length (ip)); | |
a4e06468 RS |
4993 | move_insn (ip, history[0].frag, history[0].where); |
4994 | } | |
4995 | history[0] = *ip; | |
4996 | delay.fixed_p = 1; | |
4997 | insert_into_history (0, 1, &delay); | |
4998 | } | |
4999 | break; | |
252b5132 RH |
5000 | } |
5001 | ||
13408f1e | 5002 | /* If we have just completed an unconditional branch, clear the history. */ |
11625dd8 RS |
5003 | if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1])) |
5004 | || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0]))) | |
e407c74b NC |
5005 | { |
5006 | unsigned int i; | |
5007 | ||
79850f26 | 5008 | mips_no_prev_insn (); |
13408f1e | 5009 | |
e407c74b | 5010 | for (i = 0; i < ARRAY_SIZE (history); i++) |
79850f26 | 5011 | history[i].cleared_p = 1; |
e407c74b NC |
5012 | } |
5013 | ||
df58fc94 RS |
5014 | /* We need to emit a label at the end of branch-likely macros. */ |
5015 | if (emit_branch_likely_macro) | |
5016 | { | |
5017 | emit_branch_likely_macro = FALSE; | |
5018 | micromips_add_label (); | |
5019 | } | |
5020 | ||
252b5132 RH |
5021 | /* We just output an insn, so the next one doesn't have a label. */ |
5022 | mips_clear_insn_labels (); | |
252b5132 RH |
5023 | } |
5024 | ||
e407c74b NC |
5025 | /* Forget that there was any previous instruction or label. |
5026 | When BRANCH is true, the branch history is also flushed. */ | |
252b5132 RH |
5027 | |
5028 | static void | |
7d10b47d | 5029 | mips_no_prev_insn (void) |
252b5132 | 5030 | { |
7d10b47d RS |
5031 | prev_nop_frag = NULL; |
5032 | insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); | |
252b5132 RH |
5033 | mips_clear_insn_labels (); |
5034 | } | |
5035 | ||
7d10b47d RS |
5036 | /* This function must be called before we emit something other than |
5037 | instructions. It is like mips_no_prev_insn except that it inserts | |
5038 | any NOPS that might be needed by previous instructions. */ | |
252b5132 | 5039 | |
7d10b47d RS |
5040 | void |
5041 | mips_emit_delays (void) | |
252b5132 RH |
5042 | { |
5043 | if (! mips_opts.noreorder) | |
5044 | { | |
932d1a1b | 5045 | int nops = nops_for_insn (0, history, NULL); |
252b5132 RH |
5046 | if (nops > 0) |
5047 | { | |
7d10b47d RS |
5048 | while (nops-- > 0) |
5049 | add_fixed_insn (NOP_INSN); | |
462427c4 | 5050 | mips_move_text_labels (); |
7d10b47d RS |
5051 | } |
5052 | } | |
5053 | mips_no_prev_insn (); | |
5054 | } | |
5055 | ||
5056 | /* Start a (possibly nested) noreorder block. */ | |
5057 | ||
5058 | static void | |
5059 | start_noreorder (void) | |
5060 | { | |
5061 | if (mips_opts.noreorder == 0) | |
5062 | { | |
5063 | unsigned int i; | |
5064 | int nops; | |
5065 | ||
5066 | /* None of the instructions before the .set noreorder can be moved. */ | |
5067 | for (i = 0; i < ARRAY_SIZE (history); i++) | |
5068 | history[i].fixed_p = 1; | |
5069 | ||
5070 | /* Insert any nops that might be needed between the .set noreorder | |
5071 | block and the previous instructions. We will later remove any | |
5072 | nops that turn out not to be needed. */ | |
932d1a1b | 5073 | nops = nops_for_insn (0, history, NULL); |
7d10b47d RS |
5074 | if (nops > 0) |
5075 | { | |
5076 | if (mips_optimize != 0) | |
252b5132 RH |
5077 | { |
5078 | /* Record the frag which holds the nop instructions, so | |
5079 | that we can remove them if we don't need them. */ | |
df58fc94 | 5080 | frag_grow (nops * NOP_INSN_SIZE); |
252b5132 RH |
5081 | prev_nop_frag = frag_now; |
5082 | prev_nop_frag_holds = nops; | |
5083 | prev_nop_frag_required = 0; | |
5084 | prev_nop_frag_since = 0; | |
5085 | } | |
5086 | ||
5087 | for (; nops > 0; --nops) | |
1e915849 | 5088 | add_fixed_insn (NOP_INSN); |
252b5132 | 5089 | |
7d10b47d RS |
5090 | /* Move on to a new frag, so that it is safe to simply |
5091 | decrease the size of prev_nop_frag. */ | |
5092 | frag_wane (frag_now); | |
5093 | frag_new (0); | |
462427c4 | 5094 | mips_move_text_labels (); |
252b5132 | 5095 | } |
df58fc94 | 5096 | mips_mark_labels (); |
7d10b47d | 5097 | mips_clear_insn_labels (); |
252b5132 | 5098 | } |
7d10b47d RS |
5099 | mips_opts.noreorder++; |
5100 | mips_any_noreorder = 1; | |
5101 | } | |
252b5132 | 5102 | |
7d10b47d | 5103 | /* End a nested noreorder block. */ |
252b5132 | 5104 | |
7d10b47d RS |
5105 | static void |
5106 | end_noreorder (void) | |
5107 | { | |
5108 | mips_opts.noreorder--; | |
5109 | if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) | |
5110 | { | |
5111 | /* Commit to inserting prev_nop_frag_required nops and go back to | |
5112 | handling nop insertion the .set reorder way. */ | |
5113 | prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) | |
df58fc94 | 5114 | * NOP_INSN_SIZE); |
7d10b47d RS |
5115 | insert_into_history (prev_nop_frag_since, |
5116 | prev_nop_frag_required, NOP_INSN); | |
5117 | prev_nop_frag = NULL; | |
5118 | } | |
252b5132 RH |
5119 | } |
5120 | ||
584892a6 RS |
5121 | /* Set up global variables for the start of a new macro. */ |
5122 | ||
5123 | static void | |
5124 | macro_start (void) | |
5125 | { | |
5126 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
df58fc94 RS |
5127 | memset (&mips_macro_warning.first_insn_sizes, 0, |
5128 | sizeof (mips_macro_warning.first_insn_sizes)); | |
5129 | memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns)); | |
584892a6 | 5130 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder |
11625dd8 | 5131 | && delayed_branch_p (&history[0])); |
df58fc94 RS |
5132 | switch (history[0].insn_mo->pinfo2 |
5133 | & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT)) | |
5134 | { | |
5135 | case INSN2_BRANCH_DELAY_32BIT: | |
5136 | mips_macro_warning.delay_slot_length = 4; | |
5137 | break; | |
5138 | case INSN2_BRANCH_DELAY_16BIT: | |
5139 | mips_macro_warning.delay_slot_length = 2; | |
5140 | break; | |
5141 | default: | |
5142 | mips_macro_warning.delay_slot_length = 0; | |
5143 | break; | |
5144 | } | |
5145 | mips_macro_warning.first_frag = NULL; | |
584892a6 RS |
5146 | } |
5147 | ||
df58fc94 RS |
5148 | /* Given that a macro is longer than one instruction or of the wrong size, |
5149 | return the appropriate warning for it. Return null if no warning is | |
5150 | needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT, | |
5151 | RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND, | |
5152 | and RELAX_NOMACRO. */ | |
584892a6 RS |
5153 | |
5154 | static const char * | |
5155 | macro_warning (relax_substateT subtype) | |
5156 | { | |
5157 | if (subtype & RELAX_DELAY_SLOT) | |
5158 | return _("Macro instruction expanded into multiple instructions" | |
5159 | " in a branch delay slot"); | |
5160 | else if (subtype & RELAX_NOMACRO) | |
5161 | return _("Macro instruction expanded into multiple instructions"); | |
df58fc94 RS |
5162 | else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST |
5163 | | RELAX_DELAY_SLOT_SIZE_SECOND)) | |
5164 | return ((subtype & RELAX_DELAY_SLOT_16BIT) | |
5165 | ? _("Macro instruction expanded into a wrong size instruction" | |
5166 | " in a 16-bit branch delay slot") | |
5167 | : _("Macro instruction expanded into a wrong size instruction" | |
5168 | " in a 32-bit branch delay slot")); | |
584892a6 RS |
5169 | else |
5170 | return 0; | |
5171 | } | |
5172 | ||
5173 | /* Finish up a macro. Emit warnings as appropriate. */ | |
5174 | ||
5175 | static void | |
5176 | macro_end (void) | |
5177 | { | |
df58fc94 RS |
5178 | /* Relaxation warning flags. */ |
5179 | relax_substateT subtype = 0; | |
5180 | ||
5181 | /* Check delay slot size requirements. */ | |
5182 | if (mips_macro_warning.delay_slot_length == 2) | |
5183 | subtype |= RELAX_DELAY_SLOT_16BIT; | |
5184 | if (mips_macro_warning.delay_slot_length != 0) | |
584892a6 | 5185 | { |
df58fc94 RS |
5186 | if (mips_macro_warning.delay_slot_length |
5187 | != mips_macro_warning.first_insn_sizes[0]) | |
5188 | subtype |= RELAX_DELAY_SLOT_SIZE_FIRST; | |
5189 | if (mips_macro_warning.delay_slot_length | |
5190 | != mips_macro_warning.first_insn_sizes[1]) | |
5191 | subtype |= RELAX_DELAY_SLOT_SIZE_SECOND; | |
5192 | } | |
584892a6 | 5193 | |
df58fc94 RS |
5194 | /* Check instruction count requirements. */ |
5195 | if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1) | |
5196 | { | |
5197 | if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0]) | |
584892a6 RS |
5198 | subtype |= RELAX_SECOND_LONGER; |
5199 | if (mips_opts.warn_about_macros) | |
5200 | subtype |= RELAX_NOMACRO; | |
5201 | if (mips_macro_warning.delay_slot_p) | |
5202 | subtype |= RELAX_DELAY_SLOT; | |
df58fc94 | 5203 | } |
584892a6 | 5204 | |
df58fc94 RS |
5205 | /* If both alternatives fail to fill a delay slot correctly, |
5206 | emit the warning now. */ | |
5207 | if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0 | |
5208 | && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0) | |
5209 | { | |
5210 | relax_substateT s; | |
5211 | const char *msg; | |
5212 | ||
5213 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
5214 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
5215 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
5216 | msg = macro_warning (s); | |
5217 | if (msg != NULL) | |
5218 | as_warn ("%s", msg); | |
5219 | subtype &= ~s; | |
5220 | } | |
5221 | ||
5222 | /* If both implementations are longer than 1 instruction, then emit the | |
5223 | warning now. */ | |
5224 | if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1) | |
5225 | { | |
5226 | relax_substateT s; | |
5227 | const char *msg; | |
5228 | ||
5229 | s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT); | |
5230 | msg = macro_warning (s); | |
5231 | if (msg != NULL) | |
5232 | as_warn ("%s", msg); | |
5233 | subtype &= ~s; | |
584892a6 | 5234 | } |
df58fc94 RS |
5235 | |
5236 | /* If any flags still set, then one implementation might need a warning | |
5237 | and the other either will need one of a different kind or none at all. | |
5238 | Pass any remaining flags over to relaxation. */ | |
5239 | if (mips_macro_warning.first_frag != NULL) | |
5240 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
584892a6 RS |
5241 | } |
5242 | ||
df58fc94 RS |
5243 | /* Instruction operand formats used in macros that vary between |
5244 | standard MIPS and microMIPS code. */ | |
5245 | ||
833794fc | 5246 | static const char * const brk_fmt[2][2] = { { "c", "c" }, { "mF", "c" } }; |
df58fc94 RS |
5247 | static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" }; |
5248 | static const char * const jalr_fmt[2] = { "d,s", "t,s" }; | |
5249 | static const char * const lui_fmt[2] = { "t,u", "s,u" }; | |
5250 | static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" }; | |
833794fc | 5251 | static const char * const mfhl_fmt[2][2] = { { "d", "d" }, { "mj", "s" } }; |
df58fc94 RS |
5252 | static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" }; |
5253 | static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" }; | |
5254 | ||
833794fc | 5255 | #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32]) |
df58fc94 RS |
5256 | #define COP12_FMT (cop12_fmt[mips_opts.micromips]) |
5257 | #define JALR_FMT (jalr_fmt[mips_opts.micromips]) | |
5258 | #define LUI_FMT (lui_fmt[mips_opts.micromips]) | |
5259 | #define MEM12_FMT (mem12_fmt[mips_opts.micromips]) | |
833794fc | 5260 | #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32]) |
df58fc94 RS |
5261 | #define SHFT_FMT (shft_fmt[mips_opts.micromips]) |
5262 | #define TRAP_FMT (trap_fmt[mips_opts.micromips]) | |
5263 | ||
6e1304d8 RS |
5264 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
5265 | The first argument in *ARGS will be either the code for a single | |
5266 | relocation or -1 followed by the three codes that make up a | |
5267 | composite relocation. */ | |
5268 | ||
5269 | static void | |
5270 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
5271 | { | |
5272 | int i, next; | |
5273 | ||
5274 | next = va_arg (*args, int); | |
5275 | if (next >= 0) | |
5276 | r[0] = (bfd_reloc_code_real_type) next; | |
5277 | else | |
f2ae14a1 RS |
5278 | { |
5279 | for (i = 0; i < 3; i++) | |
5280 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
5281 | /* This function is only used for 16-bit relocation fields. | |
5282 | To make the macro code simpler, treat an unrelocated value | |
5283 | in the same way as BFD_RELOC_LO16. */ | |
5284 | if (r[0] == BFD_RELOC_UNUSED) | |
5285 | r[0] = BFD_RELOC_LO16; | |
5286 | } | |
6e1304d8 RS |
5287 | } |
5288 | ||
252b5132 RH |
5289 | /* Build an instruction created by a macro expansion. This is passed |
5290 | a pointer to the count of instructions created so far, an | |
5291 | expression, the name of the instruction to build, an operand format | |
5292 | string, and corresponding arguments. */ | |
5293 | ||
252b5132 | 5294 | static void |
67c0d1eb | 5295 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 | 5296 | { |
df58fc94 | 5297 | const struct mips_opcode *mo = NULL; |
f6688943 | 5298 | bfd_reloc_code_real_type r[3]; |
df58fc94 RS |
5299 | const struct mips_opcode *amo; |
5300 | struct hash_control *hash; | |
5301 | struct mips_cl_insn insn; | |
252b5132 | 5302 | va_list args; |
252b5132 | 5303 | |
252b5132 | 5304 | va_start (args, fmt); |
252b5132 | 5305 | |
252b5132 RH |
5306 | if (mips_opts.mips16) |
5307 | { | |
03ea81db | 5308 | mips16_macro_build (ep, name, fmt, &args); |
252b5132 RH |
5309 | va_end (args); |
5310 | return; | |
5311 | } | |
5312 | ||
f6688943 TS |
5313 | r[0] = BFD_RELOC_UNUSED; |
5314 | r[1] = BFD_RELOC_UNUSED; | |
5315 | r[2] = BFD_RELOC_UNUSED; | |
df58fc94 RS |
5316 | hash = mips_opts.micromips ? micromips_op_hash : op_hash; |
5317 | amo = (struct mips_opcode *) hash_find (hash, name); | |
5318 | gas_assert (amo); | |
5319 | gas_assert (strcmp (name, amo->name) == 0); | |
1e915849 | 5320 | |
df58fc94 | 5321 | do |
8b082fb1 TS |
5322 | { |
5323 | /* Search until we get a match for NAME. It is assumed here that | |
df58fc94 RS |
5324 | macros will never generate MDMX, MIPS-3D, or MT instructions. |
5325 | We try to match an instruction that fulfils the branch delay | |
5326 | slot instruction length requirement (if any) of the previous | |
5327 | instruction. While doing this we record the first instruction | |
5328 | seen that matches all the other conditions and use it anyway | |
5329 | if the requirement cannot be met; we will issue an appropriate | |
5330 | warning later on. */ | |
5331 | if (strcmp (fmt, amo->args) == 0 | |
5332 | && amo->pinfo != INSN_MACRO | |
5333 | && is_opcode_valid (amo) | |
5334 | && is_size_valid (amo)) | |
5335 | { | |
5336 | if (is_delay_slot_valid (amo)) | |
5337 | { | |
5338 | mo = amo; | |
5339 | break; | |
5340 | } | |
5341 | else if (!mo) | |
5342 | mo = amo; | |
5343 | } | |
8b082fb1 | 5344 | |
df58fc94 RS |
5345 | ++amo; |
5346 | gas_assert (amo->name); | |
252b5132 | 5347 | } |
df58fc94 | 5348 | while (strcmp (name, amo->name) == 0); |
252b5132 | 5349 | |
df58fc94 | 5350 | gas_assert (mo); |
1e915849 | 5351 | create_insn (&insn, mo); |
252b5132 RH |
5352 | for (;;) |
5353 | { | |
5354 | switch (*fmt++) | |
5355 | { | |
5356 | case '\0': | |
5357 | break; | |
5358 | ||
5359 | case ',': | |
5360 | case '(': | |
5361 | case ')': | |
5362 | continue; | |
5363 | ||
5f74bc13 CD |
5364 | case '+': |
5365 | switch (*fmt++) | |
5366 | { | |
5367 | case 'A': | |
5368 | case 'E': | |
df58fc94 RS |
5369 | INSERT_OPERAND (mips_opts.micromips, |
5370 | EXTLSB, insn, va_arg (args, int)); | |
5f74bc13 CD |
5371 | continue; |
5372 | ||
5373 | case 'B': | |
5374 | case 'F': | |
5375 | /* Note that in the macro case, these arguments are already | |
5376 | in MSB form. (When handling the instruction in the | |
5377 | non-macro case, these arguments are sizes from which | |
5378 | MSB values must be calculated.) */ | |
df58fc94 RS |
5379 | INSERT_OPERAND (mips_opts.micromips, |
5380 | INSMSB, insn, va_arg (args, int)); | |
5f74bc13 CD |
5381 | continue; |
5382 | ||
b015e599 AP |
5383 | case 'J': |
5384 | gas_assert (!mips_opts.micromips); | |
5385 | INSERT_OPERAND (0, CODE10, insn, va_arg (args, int)); | |
5386 | continue; | |
5387 | ||
5f74bc13 CD |
5388 | case 'C': |
5389 | case 'G': | |
5390 | case 'H': | |
5391 | /* Note that in the macro case, these arguments are already | |
5392 | in MSBD form. (When handling the instruction in the | |
5393 | non-macro case, these arguments are sizes from which | |
5394 | MSBD values must be calculated.) */ | |
df58fc94 RS |
5395 | INSERT_OPERAND (mips_opts.micromips, |
5396 | EXTMSBD, insn, va_arg (args, int)); | |
5f74bc13 CD |
5397 | continue; |
5398 | ||
dd3cbb7e | 5399 | case 'Q': |
df58fc94 RS |
5400 | gas_assert (!mips_opts.micromips); |
5401 | INSERT_OPERAND (0, SEQI, insn, va_arg (args, int)); | |
dd3cbb7e NC |
5402 | continue; |
5403 | ||
7f3c4072 CM |
5404 | case 'j': |
5405 | INSERT_OPERAND (mips_opts.micromips, EVAOFFSET, insn, va_arg (args, int)); | |
5406 | continue; | |
5407 | ||
5f74bc13 | 5408 | default: |
b37df7c4 | 5409 | abort (); |
5f74bc13 CD |
5410 | } |
5411 | continue; | |
5412 | ||
8b082fb1 | 5413 | case '2': |
03f66e8a | 5414 | INSERT_OPERAND (mips_opts.micromips, BP, insn, va_arg (args, int)); |
8b082fb1 TS |
5415 | continue; |
5416 | ||
df58fc94 RS |
5417 | case 'n': |
5418 | gas_assert (mips_opts.micromips); | |
252b5132 RH |
5419 | case 't': |
5420 | case 'w': | |
5421 | case 'E': | |
df58fc94 | 5422 | INSERT_OPERAND (mips_opts.micromips, RT, insn, va_arg (args, int)); |
252b5132 RH |
5423 | continue; |
5424 | ||
5425 | case 'c': | |
833794fc | 5426 | INSERT_OPERAND (mips_opts.micromips, CODE, insn, va_arg (args, int)); |
38487616 TS |
5427 | continue; |
5428 | ||
252b5132 | 5429 | case 'W': |
df58fc94 RS |
5430 | gas_assert (!mips_opts.micromips); |
5431 | case 'T': | |
5432 | INSERT_OPERAND (mips_opts.micromips, FT, insn, va_arg (args, int)); | |
252b5132 RH |
5433 | continue; |
5434 | ||
252b5132 | 5435 | case 'G': |
df58fc94 RS |
5436 | if (mips_opts.micromips) |
5437 | INSERT_OPERAND (1, RS, insn, va_arg (args, int)); | |
5438 | else | |
5439 | INSERT_OPERAND (0, RD, insn, va_arg (args, int)); | |
5440 | continue; | |
5441 | ||
af7ee8bf | 5442 | case 'K': |
df58fc94 RS |
5443 | gas_assert (!mips_opts.micromips); |
5444 | case 'd': | |
5445 | INSERT_OPERAND (mips_opts.micromips, RD, insn, va_arg (args, int)); | |
252b5132 RH |
5446 | continue; |
5447 | ||
4372b673 | 5448 | case 'U': |
df58fc94 | 5449 | gas_assert (!mips_opts.micromips); |
4372b673 NC |
5450 | { |
5451 | int tmp = va_arg (args, int); | |
5452 | ||
df58fc94 RS |
5453 | INSERT_OPERAND (0, RT, insn, tmp); |
5454 | INSERT_OPERAND (0, RD, insn, tmp); | |
4372b673 | 5455 | } |
df58fc94 | 5456 | continue; |
4372b673 | 5457 | |
252b5132 RH |
5458 | case 'V': |
5459 | case 'S': | |
df58fc94 RS |
5460 | gas_assert (!mips_opts.micromips); |
5461 | INSERT_OPERAND (0, FS, insn, va_arg (args, int)); | |
252b5132 RH |
5462 | continue; |
5463 | ||
5464 | case 'z': | |
5465 | continue; | |
5466 | ||
5467 | case '<': | |
df58fc94 RS |
5468 | INSERT_OPERAND (mips_opts.micromips, |
5469 | SHAMT, insn, va_arg (args, int)); | |
252b5132 RH |
5470 | continue; |
5471 | ||
5472 | case 'D': | |
df58fc94 RS |
5473 | gas_assert (!mips_opts.micromips); |
5474 | INSERT_OPERAND (0, FD, insn, va_arg (args, int)); | |
252b5132 RH |
5475 | continue; |
5476 | ||
5477 | case 'B': | |
df58fc94 RS |
5478 | gas_assert (!mips_opts.micromips); |
5479 | INSERT_OPERAND (0, CODE20, insn, va_arg (args, int)); | |
252b5132 RH |
5480 | continue; |
5481 | ||
4372b673 | 5482 | case 'J': |
df58fc94 RS |
5483 | gas_assert (!mips_opts.micromips); |
5484 | INSERT_OPERAND (0, CODE19, insn, va_arg (args, int)); | |
4372b673 NC |
5485 | continue; |
5486 | ||
252b5132 | 5487 | case 'q': |
df58fc94 RS |
5488 | gas_assert (!mips_opts.micromips); |
5489 | INSERT_OPERAND (0, CODE2, insn, va_arg (args, int)); | |
252b5132 RH |
5490 | continue; |
5491 | ||
5492 | case 'b': | |
5493 | case 's': | |
5494 | case 'r': | |
5495 | case 'v': | |
df58fc94 | 5496 | INSERT_OPERAND (mips_opts.micromips, RS, insn, va_arg (args, int)); |
252b5132 RH |
5497 | continue; |
5498 | ||
5499 | case 'i': | |
5500 | case 'j': | |
6e1304d8 | 5501 | macro_read_relocs (&args, r); |
9c2799c2 | 5502 | gas_assert (*r == BFD_RELOC_GPREL16 |
e391c024 RS |
5503 | || *r == BFD_RELOC_MIPS_HIGHER |
5504 | || *r == BFD_RELOC_HI16_S | |
5505 | || *r == BFD_RELOC_LO16 | |
5506 | || *r == BFD_RELOC_MIPS_GOT_OFST); | |
5507 | continue; | |
5508 | ||
5509 | case 'o': | |
5510 | macro_read_relocs (&args, r); | |
252b5132 RH |
5511 | continue; |
5512 | ||
5513 | case 'u': | |
6e1304d8 | 5514 | macro_read_relocs (&args, r); |
9c2799c2 | 5515 | gas_assert (ep != NULL |
90ecf173 MR |
5516 | && (ep->X_op == O_constant |
5517 | || (ep->X_op == O_symbol | |
5518 | && (*r == BFD_RELOC_MIPS_HIGHEST | |
5519 | || *r == BFD_RELOC_HI16_S | |
5520 | || *r == BFD_RELOC_HI16 | |
5521 | || *r == BFD_RELOC_GPREL16 | |
5522 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
5523 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); | |
252b5132 RH |
5524 | continue; |
5525 | ||
5526 | case 'p': | |
9c2799c2 | 5527 | gas_assert (ep != NULL); |
bad36eac | 5528 | |
252b5132 RH |
5529 | /* |
5530 | * This allows macro() to pass an immediate expression for | |
5531 | * creating short branches without creating a symbol. | |
bad36eac DJ |
5532 | * |
5533 | * We don't allow branch relaxation for these branches, as | |
5534 | * they should only appear in ".set nomacro" anyway. | |
252b5132 RH |
5535 | */ |
5536 | if (ep->X_op == O_constant) | |
5537 | { | |
df58fc94 RS |
5538 | /* For microMIPS we always use relocations for branches. |
5539 | So we should not resolve immediate values. */ | |
5540 | gas_assert (!mips_opts.micromips); | |
5541 | ||
bad36eac DJ |
5542 | if ((ep->X_add_number & 3) != 0) |
5543 | as_bad (_("branch to misaligned address (0x%lx)"), | |
5544 | (unsigned long) ep->X_add_number); | |
5545 | if ((ep->X_add_number + 0x20000) & ~0x3ffff) | |
5546 | as_bad (_("branch address range overflow (0x%lx)"), | |
5547 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
5548 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; |
5549 | ep = NULL; | |
5550 | } | |
5551 | else | |
0b25d3e6 | 5552 | *r = BFD_RELOC_16_PCREL_S2; |
252b5132 RH |
5553 | continue; |
5554 | ||
5555 | case 'a': | |
9c2799c2 | 5556 | gas_assert (ep != NULL); |
f6688943 | 5557 | *r = BFD_RELOC_MIPS_JMP; |
252b5132 RH |
5558 | continue; |
5559 | ||
5560 | case 'C': | |
df58fc94 RS |
5561 | gas_assert (!mips_opts.micromips); |
5562 | INSERT_OPERAND (0, COPZ, insn, va_arg (args, unsigned long)); | |
252b5132 RH |
5563 | continue; |
5564 | ||
d43b4baf | 5565 | case 'k': |
df58fc94 RS |
5566 | INSERT_OPERAND (mips_opts.micromips, |
5567 | CACHE, insn, va_arg (args, unsigned long)); | |
5568 | continue; | |
5569 | ||
5570 | case '|': | |
5571 | gas_assert (mips_opts.micromips); | |
5572 | INSERT_OPERAND (1, TRAP, insn, va_arg (args, int)); | |
5573 | continue; | |
5574 | ||
5575 | case '.': | |
5576 | gas_assert (mips_opts.micromips); | |
5577 | INSERT_OPERAND (1, OFFSET10, insn, va_arg (args, int)); | |
5578 | continue; | |
5579 | ||
dec0624d MR |
5580 | case '\\': |
5581 | INSERT_OPERAND (mips_opts.micromips, | |
5582 | 3BITPOS, insn, va_arg (args, unsigned int)); | |
5583 | continue; | |
5584 | ||
df58fc94 | 5585 | case '~': |
dec0624d MR |
5586 | INSERT_OPERAND (mips_opts.micromips, |
5587 | OFFSET12, insn, va_arg (args, unsigned long)); | |
df58fc94 RS |
5588 | continue; |
5589 | ||
5590 | case 'N': | |
5591 | gas_assert (mips_opts.micromips); | |
5592 | INSERT_OPERAND (1, BCC, insn, va_arg (args, int)); | |
5593 | continue; | |
5594 | ||
5595 | case 'm': /* Opcode extension character. */ | |
5596 | gas_assert (mips_opts.micromips); | |
5597 | switch (*fmt++) | |
5598 | { | |
5599 | case 'j': | |
5600 | INSERT_OPERAND (1, MJ, insn, va_arg (args, int)); | |
5601 | break; | |
5602 | ||
5603 | case 'p': | |
5604 | INSERT_OPERAND (1, MP, insn, va_arg (args, int)); | |
5605 | break; | |
5606 | ||
5607 | case 'F': | |
5608 | INSERT_OPERAND (1, IMMF, insn, va_arg (args, int)); | |
5609 | break; | |
5610 | ||
5611 | default: | |
b37df7c4 | 5612 | abort (); |
df58fc94 | 5613 | } |
d43b4baf TS |
5614 | continue; |
5615 | ||
252b5132 | 5616 | default: |
b37df7c4 | 5617 | abort (); |
252b5132 RH |
5618 | } |
5619 | break; | |
5620 | } | |
5621 | va_end (args); | |
9c2799c2 | 5622 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 5623 | |
df58fc94 | 5624 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
5625 | } |
5626 | ||
5627 | static void | |
67c0d1eb | 5628 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
03ea81db | 5629 | va_list *args) |
252b5132 | 5630 | { |
1e915849 | 5631 | struct mips_opcode *mo; |
252b5132 | 5632 | struct mips_cl_insn insn; |
f6688943 TS |
5633 | bfd_reloc_code_real_type r[3] |
5634 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 5635 | |
1e915849 | 5636 | mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
9c2799c2 NC |
5637 | gas_assert (mo); |
5638 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 | 5639 | |
1e915849 | 5640 | while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) |
252b5132 | 5641 | { |
1e915849 | 5642 | ++mo; |
9c2799c2 NC |
5643 | gas_assert (mo->name); |
5644 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
5645 | } |
5646 | ||
1e915849 | 5647 | create_insn (&insn, mo); |
252b5132 RH |
5648 | for (;;) |
5649 | { | |
5650 | int c; | |
5651 | ||
5652 | c = *fmt++; | |
5653 | switch (c) | |
5654 | { | |
5655 | case '\0': | |
5656 | break; | |
5657 | ||
5658 | case ',': | |
5659 | case '(': | |
5660 | case ')': | |
5661 | continue; | |
5662 | ||
5663 | case 'y': | |
5664 | case 'w': | |
03ea81db | 5665 | MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int)); |
252b5132 RH |
5666 | continue; |
5667 | ||
5668 | case 'x': | |
5669 | case 'v': | |
03ea81db | 5670 | MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int)); |
252b5132 RH |
5671 | continue; |
5672 | ||
5673 | case 'z': | |
03ea81db | 5674 | MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int)); |
252b5132 RH |
5675 | continue; |
5676 | ||
5677 | case 'Z': | |
03ea81db | 5678 | MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int)); |
252b5132 RH |
5679 | continue; |
5680 | ||
5681 | case '0': | |
5682 | case 'S': | |
5683 | case 'P': | |
5684 | case 'R': | |
5685 | continue; | |
5686 | ||
5687 | case 'X': | |
03ea81db | 5688 | MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int)); |
252b5132 RH |
5689 | continue; |
5690 | ||
5691 | case 'Y': | |
5692 | { | |
5693 | int regno; | |
5694 | ||
03ea81db | 5695 | regno = va_arg (*args, int); |
252b5132 | 5696 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); |
a9e24354 | 5697 | MIPS16_INSERT_OPERAND (REG32R, insn, regno); |
252b5132 RH |
5698 | } |
5699 | continue; | |
5700 | ||
5701 | case '<': | |
5702 | case '>': | |
5703 | case '4': | |
5704 | case '5': | |
5705 | case 'H': | |
5706 | case 'W': | |
5707 | case 'D': | |
5708 | case 'j': | |
5709 | case '8': | |
5710 | case 'V': | |
5711 | case 'C': | |
5712 | case 'U': | |
5713 | case 'k': | |
5714 | case 'K': | |
5715 | case 'p': | |
5716 | case 'q': | |
5717 | { | |
b886a2ab RS |
5718 | offsetT value; |
5719 | ||
9c2799c2 | 5720 | gas_assert (ep != NULL); |
252b5132 RH |
5721 | |
5722 | if (ep->X_op != O_constant) | |
874e8986 | 5723 | *r = (int) BFD_RELOC_UNUSED + c; |
b886a2ab | 5724 | else if (calculate_reloc (*r, ep->X_add_number, &value)) |
252b5132 | 5725 | { |
b886a2ab | 5726 | mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode); |
252b5132 | 5727 | ep = NULL; |
f6688943 | 5728 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
5729 | } |
5730 | } | |
5731 | continue; | |
5732 | ||
5733 | case '6': | |
03ea81db | 5734 | MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int)); |
252b5132 RH |
5735 | continue; |
5736 | } | |
5737 | ||
5738 | break; | |
5739 | } | |
5740 | ||
9c2799c2 | 5741 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 5742 | |
df58fc94 | 5743 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
5744 | } |
5745 | ||
2051e8c4 MR |
5746 | /* |
5747 | * Sign-extend 32-bit mode constants that have bit 31 set and all | |
5748 | * higher bits unset. | |
5749 | */ | |
9f872bbe | 5750 | static void |
2051e8c4 MR |
5751 | normalize_constant_expr (expressionS *ex) |
5752 | { | |
9ee2a2d4 | 5753 | if (ex->X_op == O_constant |
2051e8c4 MR |
5754 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) |
5755 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
5756 | - 0x80000000); | |
5757 | } | |
5758 | ||
5759 | /* | |
5760 | * Sign-extend 32-bit mode address offsets that have bit 31 set and | |
5761 | * all higher bits unset. | |
5762 | */ | |
5763 | static void | |
5764 | normalize_address_expr (expressionS *ex) | |
5765 | { | |
5766 | if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) | |
5767 | || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) | |
5768 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
5769 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
5770 | - 0x80000000); | |
5771 | } | |
5772 | ||
438c16b8 TS |
5773 | /* |
5774 | * Generate a "jalr" instruction with a relocation hint to the called | |
5775 | * function. This occurs in NewABI PIC code. | |
5776 | */ | |
5777 | static void | |
df58fc94 | 5778 | macro_build_jalr (expressionS *ep, int cprestore) |
438c16b8 | 5779 | { |
df58fc94 RS |
5780 | static const bfd_reloc_code_real_type jalr_relocs[2] |
5781 | = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR }; | |
5782 | bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips]; | |
5783 | const char *jalr; | |
685736be | 5784 | char *f = NULL; |
b34976b6 | 5785 | |
1180b5a4 | 5786 | if (MIPS_JALR_HINT_P (ep)) |
f21f8242 | 5787 | { |
cc3d92a5 | 5788 | frag_grow (8); |
f21f8242 AO |
5789 | f = frag_more (0); |
5790 | } | |
2906b037 | 5791 | if (mips_opts.micromips) |
df58fc94 | 5792 | { |
833794fc MR |
5793 | jalr = ((mips_opts.noreorder && !cprestore) || mips_opts.insn32 |
5794 | ? "jalr" : "jalrs"); | |
e64af278 | 5795 | if (MIPS_JALR_HINT_P (ep) |
833794fc | 5796 | || mips_opts.insn32 |
e64af278 | 5797 | || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
df58fc94 RS |
5798 | macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG); |
5799 | else | |
5800 | macro_build (NULL, jalr, "mj", PIC_CALL_REG); | |
5801 | } | |
2906b037 MR |
5802 | else |
5803 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); | |
1180b5a4 | 5804 | if (MIPS_JALR_HINT_P (ep)) |
df58fc94 | 5805 | fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc); |
438c16b8 TS |
5806 | } |
5807 | ||
252b5132 RH |
5808 | /* |
5809 | * Generate a "lui" instruction. | |
5810 | */ | |
5811 | static void | |
67c0d1eb | 5812 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 | 5813 | { |
9c2799c2 | 5814 | gas_assert (! mips_opts.mips16); |
252b5132 | 5815 | |
df58fc94 | 5816 | if (ep->X_op != O_constant) |
252b5132 | 5817 | { |
9c2799c2 | 5818 | gas_assert (ep->X_op == O_symbol); |
bbe506e8 TS |
5819 | /* _gp_disp is a special case, used from s_cpload. |
5820 | __gnu_local_gp is used if mips_no_shared. */ | |
9c2799c2 | 5821 | gas_assert (mips_pic == NO_PIC |
78e1bb40 | 5822 | || (! HAVE_NEWABI |
aa6975fb ILT |
5823 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
5824 | || (! mips_in_shared | |
bbe506e8 TS |
5825 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
5826 | "__gnu_local_gp") == 0)); | |
252b5132 RH |
5827 | } |
5828 | ||
df58fc94 | 5829 | macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S); |
252b5132 RH |
5830 | } |
5831 | ||
885add95 CD |
5832 | /* Generate a sequence of instructions to do a load or store from a constant |
5833 | offset off of a base register (breg) into/from a target register (treg), | |
5834 | using AT if necessary. */ | |
5835 | static void | |
67c0d1eb RS |
5836 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
5837 | int treg, int breg, int dbl) | |
885add95 | 5838 | { |
9c2799c2 | 5839 | gas_assert (ep->X_op == O_constant); |
885add95 | 5840 | |
256ab948 | 5841 | /* Sign-extending 32-bit constants makes their handling easier. */ |
2051e8c4 MR |
5842 | if (!dbl) |
5843 | normalize_constant_expr (ep); | |
256ab948 | 5844 | |
67c1ffbe | 5845 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 5846 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
5847 | as_warn (_("operand overflow")); |
5848 | ||
5849 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
5850 | { | |
5851 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 5852 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
5853 | } |
5854 | else | |
5855 | { | |
5856 | /* 32-bit offset, need multiple instructions and AT, like: | |
5857 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
5858 | addu $tempreg,$tempreg,$breg | |
5859 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
5860 | to handle the complete offset. */ | |
67c0d1eb RS |
5861 | macro_build_lui (ep, AT); |
5862 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
5863 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 | 5864 | |
741fe287 | 5865 | if (!mips_opts.at) |
8fc2e39e | 5866 | as_bad (_("Macro used $at after \".set noat\"")); |
885add95 CD |
5867 | } |
5868 | } | |
5869 | ||
252b5132 RH |
5870 | /* set_at() |
5871 | * Generates code to set the $at register to true (one) | |
5872 | * if reg is less than the immediate expression. | |
5873 | */ | |
5874 | static void | |
67c0d1eb | 5875 | set_at (int reg, int unsignedp) |
252b5132 RH |
5876 | { |
5877 | if (imm_expr.X_op == O_constant | |
5878 | && imm_expr.X_add_number >= -0x8000 | |
5879 | && imm_expr.X_add_number < 0x8000) | |
67c0d1eb RS |
5880 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
5881 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
5882 | else |
5883 | { | |
67c0d1eb RS |
5884 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
5885 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); | |
252b5132 RH |
5886 | } |
5887 | } | |
5888 | ||
5889 | /* Warn if an expression is not a constant. */ | |
5890 | ||
5891 | static void | |
17a2f251 | 5892 | check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) |
252b5132 RH |
5893 | { |
5894 | if (ex->X_op == O_big) | |
5895 | as_bad (_("unsupported large constant")); | |
5896 | else if (ex->X_op != O_constant) | |
9ee2a2d4 MR |
5897 | as_bad (_("Instruction %s requires absolute expression"), |
5898 | ip->insn_mo->name); | |
13757d0c | 5899 | |
9ee2a2d4 MR |
5900 | if (HAVE_32BIT_GPRS) |
5901 | normalize_constant_expr (ex); | |
252b5132 RH |
5902 | } |
5903 | ||
5904 | /* Count the leading zeroes by performing a binary chop. This is a | |
5905 | bulky bit of source, but performance is a LOT better for the | |
5906 | majority of values than a simple loop to count the bits: | |
5907 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
5908 | if ((v) & (1 << (31 - lcnt))) | |
5909 | break; | |
5910 | However it is not code size friendly, and the gain will drop a bit | |
5911 | on certain cached systems. | |
5912 | */ | |
5913 | #define COUNT_TOP_ZEROES(v) \ | |
5914 | (((v) & ~0xffff) == 0 \ | |
5915 | ? ((v) & ~0xff) == 0 \ | |
5916 | ? ((v) & ~0xf) == 0 \ | |
5917 | ? ((v) & ~0x3) == 0 \ | |
5918 | ? ((v) & ~0x1) == 0 \ | |
5919 | ? !(v) \ | |
5920 | ? 32 \ | |
5921 | : 31 \ | |
5922 | : 30 \ | |
5923 | : ((v) & ~0x7) == 0 \ | |
5924 | ? 29 \ | |
5925 | : 28 \ | |
5926 | : ((v) & ~0x3f) == 0 \ | |
5927 | ? ((v) & ~0x1f) == 0 \ | |
5928 | ? 27 \ | |
5929 | : 26 \ | |
5930 | : ((v) & ~0x7f) == 0 \ | |
5931 | ? 25 \ | |
5932 | : 24 \ | |
5933 | : ((v) & ~0xfff) == 0 \ | |
5934 | ? ((v) & ~0x3ff) == 0 \ | |
5935 | ? ((v) & ~0x1ff) == 0 \ | |
5936 | ? 23 \ | |
5937 | : 22 \ | |
5938 | : ((v) & ~0x7ff) == 0 \ | |
5939 | ? 21 \ | |
5940 | : 20 \ | |
5941 | : ((v) & ~0x3fff) == 0 \ | |
5942 | ? ((v) & ~0x1fff) == 0 \ | |
5943 | ? 19 \ | |
5944 | : 18 \ | |
5945 | : ((v) & ~0x7fff) == 0 \ | |
5946 | ? 17 \ | |
5947 | : 16 \ | |
5948 | : ((v) & ~0xffffff) == 0 \ | |
5949 | ? ((v) & ~0xfffff) == 0 \ | |
5950 | ? ((v) & ~0x3ffff) == 0 \ | |
5951 | ? ((v) & ~0x1ffff) == 0 \ | |
5952 | ? 15 \ | |
5953 | : 14 \ | |
5954 | : ((v) & ~0x7ffff) == 0 \ | |
5955 | ? 13 \ | |
5956 | : 12 \ | |
5957 | : ((v) & ~0x3fffff) == 0 \ | |
5958 | ? ((v) & ~0x1fffff) == 0 \ | |
5959 | ? 11 \ | |
5960 | : 10 \ | |
5961 | : ((v) & ~0x7fffff) == 0 \ | |
5962 | ? 9 \ | |
5963 | : 8 \ | |
5964 | : ((v) & ~0xfffffff) == 0 \ | |
5965 | ? ((v) & ~0x3ffffff) == 0 \ | |
5966 | ? ((v) & ~0x1ffffff) == 0 \ | |
5967 | ? 7 \ | |
5968 | : 6 \ | |
5969 | : ((v) & ~0x7ffffff) == 0 \ | |
5970 | ? 5 \ | |
5971 | : 4 \ | |
5972 | : ((v) & ~0x3fffffff) == 0 \ | |
5973 | ? ((v) & ~0x1fffffff) == 0 \ | |
5974 | ? 3 \ | |
5975 | : 2 \ | |
5976 | : ((v) & ~0x7fffffff) == 0 \ | |
5977 | ? 1 \ | |
5978 | : 0) | |
5979 | ||
5980 | /* load_register() | |
67c1ffbe | 5981 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
5982 | * an absolute expression value into a register. |
5983 | */ | |
5984 | static void | |
67c0d1eb | 5985 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
5986 | { |
5987 | int freg; | |
5988 | expressionS hi32, lo32; | |
5989 | ||
5990 | if (ep->X_op != O_big) | |
5991 | { | |
9c2799c2 | 5992 | gas_assert (ep->X_op == O_constant); |
256ab948 TS |
5993 | |
5994 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
2051e8c4 MR |
5995 | if (!dbl) |
5996 | normalize_constant_expr (ep); | |
256ab948 TS |
5997 | |
5998 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
5999 | { |
6000 | /* We can handle 16 bit signed values with an addiu to | |
6001 | $zero. No need to ever use daddiu here, since $zero and | |
6002 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 6003 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
6004 | return; |
6005 | } | |
6006 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
6007 | { | |
6008 | /* We can handle 16 bit unsigned values with an ori to | |
6009 | $zero. */ | |
67c0d1eb | 6010 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
6011 | return; |
6012 | } | |
256ab948 | 6013 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
6014 | { |
6015 | /* 32 bit values require an lui. */ | |
df58fc94 | 6016 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 6017 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 6018 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
6019 | return; |
6020 | } | |
6021 | } | |
6022 | ||
6023 | /* The value is larger than 32 bits. */ | |
6024 | ||
2051e8c4 | 6025 | if (!dbl || HAVE_32BIT_GPRS) |
252b5132 | 6026 | { |
55e08f71 NC |
6027 | char value[32]; |
6028 | ||
6029 | sprintf_vma (value, ep->X_add_number); | |
20e1fcfd | 6030 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
67c0d1eb | 6031 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
6032 | return; |
6033 | } | |
6034 | ||
6035 | if (ep->X_op != O_big) | |
6036 | { | |
6037 | hi32 = *ep; | |
6038 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
6039 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
6040 | hi32.X_add_number &= 0xffffffff; | |
6041 | lo32 = *ep; | |
6042 | lo32.X_add_number &= 0xffffffff; | |
6043 | } | |
6044 | else | |
6045 | { | |
9c2799c2 | 6046 | gas_assert (ep->X_add_number > 2); |
252b5132 RH |
6047 | if (ep->X_add_number == 3) |
6048 | generic_bignum[3] = 0; | |
6049 | else if (ep->X_add_number > 4) | |
6050 | as_bad (_("Number larger than 64 bits")); | |
6051 | lo32.X_op = O_constant; | |
6052 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
6053 | hi32.X_op = O_constant; | |
6054 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
6055 | } | |
6056 | ||
6057 | if (hi32.X_add_number == 0) | |
6058 | freg = 0; | |
6059 | else | |
6060 | { | |
6061 | int shift, bit; | |
6062 | unsigned long hi, lo; | |
6063 | ||
956cd1d6 | 6064 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
6065 | { |
6066 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
6067 | { | |
67c0d1eb | 6068 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
6069 | return; |
6070 | } | |
6071 | if (lo32.X_add_number & 0x80000000) | |
6072 | { | |
df58fc94 | 6073 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 6074 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 6075 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
6076 | return; |
6077 | } | |
6078 | } | |
252b5132 RH |
6079 | |
6080 | /* Check for 16bit shifted constant. We know that hi32 is | |
6081 | non-zero, so start the mask on the first bit of the hi32 | |
6082 | value. */ | |
6083 | shift = 17; | |
6084 | do | |
beae10d5 KH |
6085 | { |
6086 | unsigned long himask, lomask; | |
6087 | ||
6088 | if (shift < 32) | |
6089 | { | |
6090 | himask = 0xffff >> (32 - shift); | |
6091 | lomask = (0xffff << shift) & 0xffffffff; | |
6092 | } | |
6093 | else | |
6094 | { | |
6095 | himask = 0xffff << (shift - 32); | |
6096 | lomask = 0; | |
6097 | } | |
6098 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
6099 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
6100 | { | |
6101 | expressionS tmp; | |
6102 | ||
6103 | tmp.X_op = O_constant; | |
6104 | if (shift < 32) | |
6105 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
6106 | | (lo32.X_add_number >> shift)); | |
6107 | else | |
6108 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb | 6109 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
df58fc94 | 6110 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 6111 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
6112 | return; |
6113 | } | |
f9419b05 | 6114 | ++shift; |
beae10d5 KH |
6115 | } |
6116 | while (shift <= (64 - 16)); | |
252b5132 RH |
6117 | |
6118 | /* Find the bit number of the lowest one bit, and store the | |
6119 | shifted value in hi/lo. */ | |
6120 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
6121 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
6122 | if (lo != 0) | |
6123 | { | |
6124 | bit = 0; | |
6125 | while ((lo & 1) == 0) | |
6126 | { | |
6127 | lo >>= 1; | |
6128 | ++bit; | |
6129 | } | |
6130 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
6131 | hi >>= bit; | |
6132 | } | |
6133 | else | |
6134 | { | |
6135 | bit = 32; | |
6136 | while ((hi & 1) == 0) | |
6137 | { | |
6138 | hi >>= 1; | |
6139 | ++bit; | |
6140 | } | |
6141 | lo = hi; | |
6142 | hi = 0; | |
6143 | } | |
6144 | ||
6145 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
6146 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
6147 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
6148 | { |
6149 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 6150 | if (shift != 0) |
beae10d5 | 6151 | { |
252b5132 RH |
6152 | expressionS tmp; |
6153 | ||
6154 | /* This instruction will set the register to be all | |
6155 | ones. */ | |
beae10d5 KH |
6156 | tmp.X_op = O_constant; |
6157 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 6158 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
6159 | if (bit != 0) |
6160 | { | |
6161 | bit += shift; | |
df58fc94 | 6162 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 6163 | reg, reg, (bit >= 32) ? bit - 32 : bit); |
beae10d5 | 6164 | } |
df58fc94 | 6165 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT, |
67c0d1eb | 6166 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
6167 | return; |
6168 | } | |
6169 | } | |
252b5132 RH |
6170 | |
6171 | /* Sign extend hi32 before calling load_register, because we can | |
6172 | generally get better code when we load a sign extended value. */ | |
6173 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 6174 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 6175 | load_register (reg, &hi32, 0); |
252b5132 RH |
6176 | freg = reg; |
6177 | } | |
6178 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
6179 | { | |
6180 | if (freg != 0) | |
6181 | { | |
df58fc94 | 6182 | macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0); |
252b5132 RH |
6183 | freg = reg; |
6184 | } | |
6185 | } | |
6186 | else | |
6187 | { | |
6188 | expressionS mid16; | |
6189 | ||
956cd1d6 | 6190 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 6191 | { |
df58fc94 RS |
6192 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
6193 | macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0); | |
beae10d5 KH |
6194 | return; |
6195 | } | |
252b5132 RH |
6196 | |
6197 | if (freg != 0) | |
6198 | { | |
df58fc94 | 6199 | macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16); |
252b5132 RH |
6200 | freg = reg; |
6201 | } | |
6202 | mid16 = lo32; | |
6203 | mid16.X_add_number >>= 16; | |
67c0d1eb | 6204 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
df58fc94 | 6205 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
252b5132 RH |
6206 | freg = reg; |
6207 | } | |
6208 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 6209 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
6210 | } |
6211 | ||
269137b2 TS |
6212 | static inline void |
6213 | load_delay_nop (void) | |
6214 | { | |
6215 | if (!gpr_interlocks) | |
6216 | macro_build (NULL, "nop", ""); | |
6217 | } | |
6218 | ||
252b5132 RH |
6219 | /* Load an address into a register. */ |
6220 | ||
6221 | static void | |
67c0d1eb | 6222 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 6223 | { |
252b5132 RH |
6224 | if (ep->X_op != O_constant |
6225 | && ep->X_op != O_symbol) | |
6226 | { | |
6227 | as_bad (_("expression too complex")); | |
6228 | ep->X_op = O_constant; | |
6229 | } | |
6230 | ||
6231 | if (ep->X_op == O_constant) | |
6232 | { | |
67c0d1eb | 6233 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
6234 | return; |
6235 | } | |
6236 | ||
6237 | if (mips_pic == NO_PIC) | |
6238 | { | |
6239 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 6240 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
6241 | Otherwise we want |
6242 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
6243 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 6244 | If we have an addend, we always use the latter form. |
76b3015f | 6245 | |
d6bc6245 TS |
6246 | With 64bit address space and a usable $at we want |
6247 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6248 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
6249 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6250 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
6251 | dsll32 $reg,0 | |
3a482fd5 | 6252 | daddu $reg,$reg,$at |
76b3015f | 6253 | |
c03099e6 | 6254 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
6255 | on superscalar processors. |
6256 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
6257 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
6258 | dsll $reg,16 | |
6259 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
6260 | dsll $reg,16 | |
6261 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
6caf9ef4 TS |
6262 | |
6263 | For GP relative symbols in 64bit address space we can use | |
6264 | the same sequence as in 32bit address space. */ | |
aed1a261 | 6265 | if (HAVE_64BIT_SYMBOLS) |
d6bc6245 | 6266 | { |
6caf9ef4 TS |
6267 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6268 | && !nopic_need_relax (ep->X_add_symbol, 1)) | |
6269 | { | |
6270 | relax_start (ep->X_add_symbol); | |
6271 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
6272 | mips_gp_register, BFD_RELOC_GPREL16); | |
6273 | relax_switch (); | |
6274 | } | |
d6bc6245 | 6275 | |
741fe287 | 6276 | if (*used_at == 0 && mips_opts.at) |
d6bc6245 | 6277 | { |
df58fc94 RS |
6278 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
6279 | macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S); | |
67c0d1eb RS |
6280 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
6281 | BFD_RELOC_MIPS_HIGHER); | |
6282 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
df58fc94 | 6283 | macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0); |
67c0d1eb | 6284 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); |
d6bc6245 TS |
6285 | *used_at = 1; |
6286 | } | |
6287 | else | |
6288 | { | |
df58fc94 | 6289 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb RS |
6290 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
6291 | BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 6292 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 6293 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); |
df58fc94 | 6294 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 6295 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); |
d6bc6245 | 6296 | } |
6caf9ef4 TS |
6297 | |
6298 | if (mips_relax.sequence) | |
6299 | relax_end (); | |
d6bc6245 | 6300 | } |
252b5132 RH |
6301 | else |
6302 | { | |
d6bc6245 | 6303 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 6304 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
d6bc6245 | 6305 | { |
4d7206a2 | 6306 | relax_start (ep->X_add_symbol); |
67c0d1eb | 6307 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 6308 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 6309 | relax_switch (); |
d6bc6245 | 6310 | } |
67c0d1eb RS |
6311 | macro_build_lui (ep, reg); |
6312 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
6313 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
6314 | if (mips_relax.sequence) |
6315 | relax_end (); | |
d6bc6245 | 6316 | } |
252b5132 | 6317 | } |
0a44bf69 | 6318 | else if (!mips_big_got) |
252b5132 RH |
6319 | { |
6320 | expressionS ex; | |
6321 | ||
6322 | /* If this is a reference to an external symbol, we want | |
6323 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6324 | Otherwise we want | |
6325 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
6326 | nop | |
6327 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
6328 | If there is a constant, it must be added in after. |
6329 | ||
ed6fb7bd | 6330 | If we have NewABI, we want |
f5040a92 AO |
6331 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
6332 | unless we're referencing a global symbol with a non-zero | |
6333 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
6334 | if (HAVE_NEWABI) |
6335 | { | |
f5040a92 AO |
6336 | if (ep->X_add_number) |
6337 | { | |
4d7206a2 | 6338 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 6339 | ep->X_add_number = 0; |
4d7206a2 | 6340 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
6341 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
6342 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
6343 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
6344 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6345 | ex.X_op = O_constant; | |
67c0d1eb | 6346 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 6347 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 6348 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 6349 | relax_switch (); |
f5040a92 | 6350 | } |
67c0d1eb | 6351 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 6352 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
6353 | if (mips_relax.sequence) |
6354 | relax_end (); | |
ed6fb7bd SC |
6355 | } |
6356 | else | |
6357 | { | |
f5040a92 AO |
6358 | ex.X_add_number = ep->X_add_number; |
6359 | ep->X_add_number = 0; | |
67c0d1eb RS |
6360 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
6361 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 6362 | load_delay_nop (); |
4d7206a2 RS |
6363 | relax_start (ep->X_add_symbol); |
6364 | relax_switch (); | |
67c0d1eb | 6365 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 6366 | BFD_RELOC_LO16); |
4d7206a2 | 6367 | relax_end (); |
ed6fb7bd | 6368 | |
f5040a92 AO |
6369 | if (ex.X_add_number != 0) |
6370 | { | |
6371 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
6372 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6373 | ex.X_op = O_constant; | |
67c0d1eb | 6374 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 6375 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 6376 | } |
252b5132 RH |
6377 | } |
6378 | } | |
0a44bf69 | 6379 | else if (mips_big_got) |
252b5132 RH |
6380 | { |
6381 | expressionS ex; | |
252b5132 RH |
6382 | |
6383 | /* This is the large GOT case. If this is a reference to an | |
6384 | external symbol, we want | |
6385 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
6386 | addu $reg,$reg,$gp | |
6387 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
6388 | |
6389 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
6390 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
6391 | nop | |
6392 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 6393 | If there is a constant, it must be added in after. |
f5040a92 AO |
6394 | |
6395 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
6396 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
6397 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 6398 | */ |
438c16b8 TS |
6399 | if (HAVE_NEWABI) |
6400 | { | |
4d7206a2 | 6401 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 6402 | ep->X_add_number = 0; |
4d7206a2 | 6403 | relax_start (ep->X_add_symbol); |
df58fc94 | 6404 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6405 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
6406 | reg, reg, mips_gp_register); | |
6407 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
6408 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
6409 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
6410 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6411 | else if (ex.X_add_number) | |
6412 | { | |
6413 | ex.X_op = O_constant; | |
67c0d1eb RS |
6414 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
6415 | BFD_RELOC_LO16); | |
f5040a92 AO |
6416 | } |
6417 | ||
6418 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 6419 | relax_switch (); |
67c0d1eb | 6420 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 6421 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
6422 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
6423 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 6424 | relax_end (); |
438c16b8 | 6425 | } |
252b5132 | 6426 | else |
438c16b8 | 6427 | { |
f5040a92 AO |
6428 | ex.X_add_number = ep->X_add_number; |
6429 | ep->X_add_number = 0; | |
4d7206a2 | 6430 | relax_start (ep->X_add_symbol); |
df58fc94 | 6431 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
6432 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
6433 | reg, reg, mips_gp_register); | |
6434 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
6435 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
6436 | relax_switch (); |
6437 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
6438 | { |
6439 | /* We need a nop before loading from $gp. This special | |
6440 | check is required because the lui which starts the main | |
6441 | instruction stream does not refer to $gp, and so will not | |
6442 | insert the nop which may be required. */ | |
67c0d1eb | 6443 | macro_build (NULL, "nop", ""); |
438c16b8 | 6444 | } |
67c0d1eb | 6445 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 6446 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 6447 | load_delay_nop (); |
67c0d1eb | 6448 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 6449 | BFD_RELOC_LO16); |
4d7206a2 | 6450 | relax_end (); |
438c16b8 | 6451 | |
f5040a92 AO |
6452 | if (ex.X_add_number != 0) |
6453 | { | |
6454 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
6455 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
6456 | ex.X_op = O_constant; | |
67c0d1eb RS |
6457 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
6458 | BFD_RELOC_LO16); | |
f5040a92 | 6459 | } |
252b5132 RH |
6460 | } |
6461 | } | |
252b5132 RH |
6462 | else |
6463 | abort (); | |
8fc2e39e | 6464 | |
741fe287 | 6465 | if (!mips_opts.at && *used_at == 1) |
8fc2e39e | 6466 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
6467 | } |
6468 | ||
ea1fb5dc RS |
6469 | /* Move the contents of register SOURCE into register DEST. */ |
6470 | ||
6471 | static void | |
67c0d1eb | 6472 | move_register (int dest, int source) |
ea1fb5dc | 6473 | { |
df58fc94 RS |
6474 | /* Prefer to use a 16-bit microMIPS instruction unless the previous |
6475 | instruction specifically requires a 32-bit one. */ | |
6476 | if (mips_opts.micromips | |
833794fc | 6477 | && !mips_opts.insn32 |
df58fc94 | 6478 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
7951ca42 | 6479 | macro_build (NULL, "move", "mp,mj", dest, source); |
df58fc94 RS |
6480 | else |
6481 | macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", | |
6482 | dest, source, 0); | |
ea1fb5dc RS |
6483 | } |
6484 | ||
4d7206a2 | 6485 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
6486 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
6487 | The two alternatives are: | |
4d7206a2 RS |
6488 | |
6489 | Global symbol Local sybmol | |
6490 | ------------- ------------ | |
6491 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
6492 | ... ... | |
6493 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
6494 | ||
6495 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
6496 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
6497 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
6498 | |
6499 | static void | |
67c0d1eb | 6500 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
6501 | { |
6502 | expressionS global; | |
6503 | ||
6504 | global = *local; | |
6505 | global.X_add_number = 0; | |
6506 | ||
6507 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
6508 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
6509 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 6510 | relax_switch (); |
67c0d1eb RS |
6511 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
6512 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
6513 | relax_end (); |
6514 | } | |
6515 | ||
6516 | static void | |
67c0d1eb | 6517 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
6518 | { |
6519 | expressionS global; | |
6520 | ||
6521 | global.X_op = O_constant; | |
6522 | global.X_op_symbol = NULL; | |
6523 | global.X_add_symbol = NULL; | |
6524 | global.X_add_number = local->X_add_number; | |
6525 | ||
6526 | relax_start (local->X_add_symbol); | |
67c0d1eb | 6527 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
6528 | dest, dest, BFD_RELOC_LO16); |
6529 | relax_switch (); | |
67c0d1eb | 6530 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
6531 | relax_end (); |
6532 | } | |
6533 | ||
f6a22291 MR |
6534 | static void |
6535 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
6536 | { | |
6537 | expressionS global; | |
6538 | int hold_mips_optimize; | |
6539 | ||
6540 | global.X_op = O_constant; | |
6541 | global.X_op_symbol = NULL; | |
6542 | global.X_add_symbol = NULL; | |
6543 | global.X_add_number = local->X_add_number; | |
6544 | ||
6545 | relax_start (local->X_add_symbol); | |
6546 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
6547 | relax_switch (); | |
6548 | /* Set mips_optimize around the lui instruction to avoid | |
6549 | inserting an unnecessary nop after the lw. */ | |
6550 | hold_mips_optimize = mips_optimize; | |
6551 | mips_optimize = 2; | |
6552 | macro_build_lui (&global, tmp); | |
6553 | mips_optimize = hold_mips_optimize; | |
6554 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
6555 | relax_end (); | |
6556 | ||
6557 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
6558 | } | |
6559 | ||
df58fc94 RS |
6560 | /* Emit a sequence of instructions to emulate a branch likely operation. |
6561 | BR is an ordinary branch corresponding to one to be emulated. BRNEG | |
6562 | is its complementing branch with the original condition negated. | |
6563 | CALL is set if the original branch specified the link operation. | |
6564 | EP, FMT, SREG and TREG specify the usual macro_build() parameters. | |
6565 | ||
6566 | Code like this is produced in the noreorder mode: | |
6567 | ||
6568 | BRNEG <args>, 1f | |
6569 | nop | |
6570 | b <sym> | |
6571 | delay slot (executed only if branch taken) | |
6572 | 1: | |
6573 | ||
6574 | or, if CALL is set: | |
6575 | ||
6576 | BRNEG <args>, 1f | |
6577 | nop | |
6578 | bal <sym> | |
6579 | delay slot (executed only if branch taken) | |
6580 | 1: | |
6581 | ||
6582 | In the reorder mode the delay slot would be filled with a nop anyway, | |
6583 | so code produced is simply: | |
6584 | ||
6585 | BR <args>, <sym> | |
6586 | nop | |
6587 | ||
6588 | This function is used when producing code for the microMIPS ASE that | |
6589 | does not implement branch likely instructions in hardware. */ | |
6590 | ||
6591 | static void | |
6592 | macro_build_branch_likely (const char *br, const char *brneg, | |
6593 | int call, expressionS *ep, const char *fmt, | |
6594 | unsigned int sreg, unsigned int treg) | |
6595 | { | |
6596 | int noreorder = mips_opts.noreorder; | |
6597 | expressionS expr1; | |
6598 | ||
6599 | gas_assert (mips_opts.micromips); | |
6600 | start_noreorder (); | |
6601 | if (noreorder) | |
6602 | { | |
6603 | micromips_label_expr (&expr1); | |
6604 | macro_build (&expr1, brneg, fmt, sreg, treg); | |
6605 | macro_build (NULL, "nop", ""); | |
6606 | macro_build (ep, call ? "bal" : "b", "p"); | |
6607 | ||
6608 | /* Set to true so that append_insn adds a label. */ | |
6609 | emit_branch_likely_macro = TRUE; | |
6610 | } | |
6611 | else | |
6612 | { | |
6613 | macro_build (ep, br, fmt, sreg, treg); | |
6614 | macro_build (NULL, "nop", ""); | |
6615 | } | |
6616 | end_noreorder (); | |
6617 | } | |
6618 | ||
6619 | /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as | |
6620 | the condition code tested. EP specifies the branch target. */ | |
6621 | ||
6622 | static void | |
6623 | macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc) | |
6624 | { | |
6625 | const int call = 0; | |
6626 | const char *brneg; | |
6627 | const char *br; | |
6628 | ||
6629 | switch (type) | |
6630 | { | |
6631 | case M_BC1FL: | |
6632 | br = "bc1f"; | |
6633 | brneg = "bc1t"; | |
6634 | break; | |
6635 | case M_BC1TL: | |
6636 | br = "bc1t"; | |
6637 | brneg = "bc1f"; | |
6638 | break; | |
6639 | case M_BC2FL: | |
6640 | br = "bc2f"; | |
6641 | brneg = "bc2t"; | |
6642 | break; | |
6643 | case M_BC2TL: | |
6644 | br = "bc2t"; | |
6645 | brneg = "bc2f"; | |
6646 | break; | |
6647 | default: | |
6648 | abort (); | |
6649 | } | |
6650 | macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO); | |
6651 | } | |
6652 | ||
6653 | /* Emit a two-argument branch macro specified by TYPE, using SREG as | |
6654 | the register tested. EP specifies the branch target. */ | |
6655 | ||
6656 | static void | |
6657 | macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg) | |
6658 | { | |
6659 | const char *brneg = NULL; | |
6660 | const char *br; | |
6661 | int call = 0; | |
6662 | ||
6663 | switch (type) | |
6664 | { | |
6665 | case M_BGEZ: | |
6666 | br = "bgez"; | |
6667 | break; | |
6668 | case M_BGEZL: | |
6669 | br = mips_opts.micromips ? "bgez" : "bgezl"; | |
6670 | brneg = "bltz"; | |
6671 | break; | |
6672 | case M_BGEZALL: | |
6673 | gas_assert (mips_opts.micromips); | |
833794fc | 6674 | br = mips_opts.insn32 ? "bgezal" : "bgezals"; |
df58fc94 RS |
6675 | brneg = "bltz"; |
6676 | call = 1; | |
6677 | break; | |
6678 | case M_BGTZ: | |
6679 | br = "bgtz"; | |
6680 | break; | |
6681 | case M_BGTZL: | |
6682 | br = mips_opts.micromips ? "bgtz" : "bgtzl"; | |
6683 | brneg = "blez"; | |
6684 | break; | |
6685 | case M_BLEZ: | |
6686 | br = "blez"; | |
6687 | break; | |
6688 | case M_BLEZL: | |
6689 | br = mips_opts.micromips ? "blez" : "blezl"; | |
6690 | brneg = "bgtz"; | |
6691 | break; | |
6692 | case M_BLTZ: | |
6693 | br = "bltz"; | |
6694 | break; | |
6695 | case M_BLTZL: | |
6696 | br = mips_opts.micromips ? "bltz" : "bltzl"; | |
6697 | brneg = "bgez"; | |
6698 | break; | |
6699 | case M_BLTZALL: | |
6700 | gas_assert (mips_opts.micromips); | |
833794fc | 6701 | br = mips_opts.insn32 ? "bltzal" : "bltzals"; |
df58fc94 RS |
6702 | brneg = "bgez"; |
6703 | call = 1; | |
6704 | break; | |
6705 | default: | |
6706 | abort (); | |
6707 | } | |
6708 | if (mips_opts.micromips && brneg) | |
6709 | macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO); | |
6710 | else | |
6711 | macro_build (ep, br, "s,p", sreg); | |
6712 | } | |
6713 | ||
6714 | /* Emit a three-argument branch macro specified by TYPE, using SREG and | |
6715 | TREG as the registers tested. EP specifies the branch target. */ | |
6716 | ||
6717 | static void | |
6718 | macro_build_branch_rsrt (int type, expressionS *ep, | |
6719 | unsigned int sreg, unsigned int treg) | |
6720 | { | |
6721 | const char *brneg = NULL; | |
6722 | const int call = 0; | |
6723 | const char *br; | |
6724 | ||
6725 | switch (type) | |
6726 | { | |
6727 | case M_BEQ: | |
6728 | case M_BEQ_I: | |
6729 | br = "beq"; | |
6730 | break; | |
6731 | case M_BEQL: | |
6732 | case M_BEQL_I: | |
6733 | br = mips_opts.micromips ? "beq" : "beql"; | |
6734 | brneg = "bne"; | |
6735 | break; | |
6736 | case M_BNE: | |
6737 | case M_BNE_I: | |
6738 | br = "bne"; | |
6739 | break; | |
6740 | case M_BNEL: | |
6741 | case M_BNEL_I: | |
6742 | br = mips_opts.micromips ? "bne" : "bnel"; | |
6743 | brneg = "beq"; | |
6744 | break; | |
6745 | default: | |
6746 | abort (); | |
6747 | } | |
6748 | if (mips_opts.micromips && brneg) | |
6749 | macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg); | |
6750 | else | |
6751 | macro_build (ep, br, "s,t,p", sreg, treg); | |
6752 | } | |
6753 | ||
f2ae14a1 RS |
6754 | /* Return the high part that should be loaded in order to make the low |
6755 | part of VALUE accessible using an offset of OFFBITS bits. */ | |
6756 | ||
6757 | static offsetT | |
6758 | offset_high_part (offsetT value, unsigned int offbits) | |
6759 | { | |
6760 | offsetT bias; | |
6761 | addressT low_mask; | |
6762 | ||
6763 | if (offbits == 0) | |
6764 | return value; | |
6765 | bias = 1 << (offbits - 1); | |
6766 | low_mask = bias * 2 - 1; | |
6767 | return (value + bias) & ~low_mask; | |
6768 | } | |
6769 | ||
6770 | /* Return true if the value stored in offset_expr and offset_reloc | |
6771 | fits into a signed offset of OFFBITS bits. RANGE is the maximum | |
6772 | amount that the caller wants to add without inducing overflow | |
6773 | and ALIGN is the known alignment of the value in bytes. */ | |
6774 | ||
6775 | static bfd_boolean | |
6776 | small_offset_p (unsigned int range, unsigned int align, unsigned int offbits) | |
6777 | { | |
6778 | if (offbits == 16) | |
6779 | { | |
6780 | /* Accept any relocation operator if overflow isn't a concern. */ | |
6781 | if (range < align && *offset_reloc != BFD_RELOC_UNUSED) | |
6782 | return TRUE; | |
6783 | ||
6784 | /* These relocations are guaranteed not to overflow in correct links. */ | |
6785 | if (*offset_reloc == BFD_RELOC_MIPS_LITERAL | |
6786 | || gprel16_reloc_p (*offset_reloc)) | |
6787 | return TRUE; | |
6788 | } | |
6789 | if (offset_expr.X_op == O_constant | |
6790 | && offset_high_part (offset_expr.X_add_number, offbits) == 0 | |
6791 | && offset_high_part (offset_expr.X_add_number + range, offbits) == 0) | |
6792 | return TRUE; | |
6793 | return FALSE; | |
6794 | } | |
6795 | ||
252b5132 RH |
6796 | /* |
6797 | * Build macros | |
6798 | * This routine implements the seemingly endless macro or synthesized | |
6799 | * instructions and addressing modes in the mips assembly language. Many | |
6800 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 6801 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
6802 | * this verbose method. Others are not simple macros but are more like |
6803 | * optimizing code generation. | |
6804 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 6805 | * consecutively that would load AT with the upper half of the same address. |
252b5132 RH |
6806 | * The ensuing load upper instructions are ommited. This implies some kind |
6807 | * of global optimization. We currently only optimize within a single macro. | |
6808 | * For many of the load and store macros if the address is specified as a | |
6809 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
6810 | * first load register 'at' with zero and use it as the base register. The | |
6811 | * mips assembler simply uses register $zero. Just one tiny optimization | |
6812 | * we're missing. | |
6813 | */ | |
6814 | static void | |
833794fc | 6815 | macro (struct mips_cl_insn *ip, char *str) |
252b5132 | 6816 | { |
741fe287 MR |
6817 | unsigned int treg, sreg, dreg, breg; |
6818 | unsigned int tempreg; | |
252b5132 | 6819 | int mask; |
43841e91 | 6820 | int used_at = 0; |
df58fc94 | 6821 | expressionS label_expr; |
252b5132 | 6822 | expressionS expr1; |
df58fc94 | 6823 | expressionS *ep; |
252b5132 RH |
6824 | const char *s; |
6825 | const char *s2; | |
6826 | const char *fmt; | |
6827 | int likely = 0; | |
252b5132 | 6828 | int coproc = 0; |
7f3c4072 | 6829 | int offbits = 16; |
1abe91b1 | 6830 | int call = 0; |
df58fc94 RS |
6831 | int jals = 0; |
6832 | int dbl = 0; | |
6833 | int imm = 0; | |
6834 | int ust = 0; | |
6835 | int lp = 0; | |
f2ae14a1 | 6836 | bfd_boolean large_offset; |
252b5132 | 6837 | int off; |
252b5132 | 6838 | int hold_mips_optimize; |
f2ae14a1 | 6839 | unsigned int align; |
252b5132 | 6840 | |
9c2799c2 | 6841 | gas_assert (! mips_opts.mips16); |
252b5132 | 6842 | |
df58fc94 RS |
6843 | treg = EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); |
6844 | dreg = EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); | |
6845 | sreg = breg = EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); | |
252b5132 RH |
6846 | mask = ip->insn_mo->mask; |
6847 | ||
df58fc94 RS |
6848 | label_expr.X_op = O_constant; |
6849 | label_expr.X_op_symbol = NULL; | |
6850 | label_expr.X_add_symbol = NULL; | |
6851 | label_expr.X_add_number = 0; | |
6852 | ||
252b5132 RH |
6853 | expr1.X_op = O_constant; |
6854 | expr1.X_op_symbol = NULL; | |
6855 | expr1.X_add_symbol = NULL; | |
6856 | expr1.X_add_number = 1; | |
f2ae14a1 | 6857 | align = 1; |
252b5132 RH |
6858 | |
6859 | switch (mask) | |
6860 | { | |
6861 | case M_DABS: | |
6862 | dbl = 1; | |
6863 | case M_ABS: | |
df58fc94 RS |
6864 | /* bgez $a0,1f |
6865 | move v0,$a0 | |
6866 | sub v0,$zero,$a0 | |
6867 | 1: | |
6868 | */ | |
252b5132 | 6869 | |
7d10b47d | 6870 | start_noreorder (); |
252b5132 | 6871 | |
df58fc94 RS |
6872 | if (mips_opts.micromips) |
6873 | micromips_label_expr (&label_expr); | |
6874 | else | |
6875 | label_expr.X_add_number = 8; | |
6876 | macro_build (&label_expr, "bgez", "s,p", sreg); | |
252b5132 | 6877 | if (dreg == sreg) |
a605d2b3 | 6878 | macro_build (NULL, "nop", ""); |
252b5132 | 6879 | else |
67c0d1eb RS |
6880 | move_register (dreg, sreg); |
6881 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); | |
df58fc94 RS |
6882 | if (mips_opts.micromips) |
6883 | micromips_add_label (); | |
252b5132 | 6884 | |
7d10b47d | 6885 | end_noreorder (); |
8fc2e39e | 6886 | break; |
252b5132 RH |
6887 | |
6888 | case M_ADD_I: | |
6889 | s = "addi"; | |
6890 | s2 = "add"; | |
6891 | goto do_addi; | |
6892 | case M_ADDU_I: | |
6893 | s = "addiu"; | |
6894 | s2 = "addu"; | |
6895 | goto do_addi; | |
6896 | case M_DADD_I: | |
6897 | dbl = 1; | |
6898 | s = "daddi"; | |
6899 | s2 = "dadd"; | |
df58fc94 RS |
6900 | if (!mips_opts.micromips) |
6901 | goto do_addi; | |
6902 | if (imm_expr.X_op == O_constant | |
6903 | && imm_expr.X_add_number >= -0x200 | |
6904 | && imm_expr.X_add_number < 0x200) | |
6905 | { | |
6906 | macro_build (NULL, s, "t,r,.", treg, sreg, imm_expr.X_add_number); | |
6907 | break; | |
6908 | } | |
6909 | goto do_addi_i; | |
252b5132 RH |
6910 | case M_DADDU_I: |
6911 | dbl = 1; | |
6912 | s = "daddiu"; | |
6913 | s2 = "daddu"; | |
6914 | do_addi: | |
6915 | if (imm_expr.X_op == O_constant | |
6916 | && imm_expr.X_add_number >= -0x8000 | |
6917 | && imm_expr.X_add_number < 0x8000) | |
6918 | { | |
67c0d1eb | 6919 | macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 6920 | break; |
252b5132 | 6921 | } |
df58fc94 | 6922 | do_addi_i: |
8fc2e39e | 6923 | used_at = 1; |
67c0d1eb RS |
6924 | load_register (AT, &imm_expr, dbl); |
6925 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
6926 | break; |
6927 | ||
6928 | case M_AND_I: | |
6929 | s = "andi"; | |
6930 | s2 = "and"; | |
6931 | goto do_bit; | |
6932 | case M_OR_I: | |
6933 | s = "ori"; | |
6934 | s2 = "or"; | |
6935 | goto do_bit; | |
6936 | case M_NOR_I: | |
6937 | s = ""; | |
6938 | s2 = "nor"; | |
6939 | goto do_bit; | |
6940 | case M_XOR_I: | |
6941 | s = "xori"; | |
6942 | s2 = "xor"; | |
6943 | do_bit: | |
6944 | if (imm_expr.X_op == O_constant | |
6945 | && imm_expr.X_add_number >= 0 | |
6946 | && imm_expr.X_add_number < 0x10000) | |
6947 | { | |
6948 | if (mask != M_NOR_I) | |
67c0d1eb | 6949 | macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
6950 | else |
6951 | { | |
67c0d1eb RS |
6952 | macro_build (&imm_expr, "ori", "t,r,i", |
6953 | treg, sreg, BFD_RELOC_LO16); | |
6954 | macro_build (NULL, "nor", "d,v,t", treg, treg, 0); | |
252b5132 | 6955 | } |
8fc2e39e | 6956 | break; |
252b5132 RH |
6957 | } |
6958 | ||
8fc2e39e | 6959 | used_at = 1; |
67c0d1eb RS |
6960 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
6961 | macro_build (NULL, s2, "d,v,t", treg, sreg, AT); | |
252b5132 RH |
6962 | break; |
6963 | ||
8b082fb1 TS |
6964 | case M_BALIGN: |
6965 | switch (imm_expr.X_add_number) | |
6966 | { | |
6967 | case 0: | |
6968 | macro_build (NULL, "nop", ""); | |
6969 | break; | |
6970 | case 2: | |
6971 | macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg); | |
6972 | break; | |
03f66e8a MR |
6973 | case 1: |
6974 | case 3: | |
8b082fb1 | 6975 | macro_build (NULL, "balign", "t,s,2", treg, sreg, |
90ecf173 | 6976 | (int) imm_expr.X_add_number); |
8b082fb1 | 6977 | break; |
03f66e8a MR |
6978 | default: |
6979 | as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"), | |
6980 | (unsigned long) imm_expr.X_add_number); | |
6981 | break; | |
8b082fb1 TS |
6982 | } |
6983 | break; | |
6984 | ||
df58fc94 RS |
6985 | case M_BC1FL: |
6986 | case M_BC1TL: | |
6987 | case M_BC2FL: | |
6988 | case M_BC2TL: | |
6989 | gas_assert (mips_opts.micromips); | |
6990 | macro_build_branch_ccl (mask, &offset_expr, | |
6991 | EXTRACT_OPERAND (1, BCC, *ip)); | |
6992 | break; | |
6993 | ||
252b5132 | 6994 | case M_BEQ_I: |
252b5132 | 6995 | case M_BEQL_I: |
252b5132 | 6996 | case M_BNE_I: |
252b5132 | 6997 | case M_BNEL_I: |
252b5132 | 6998 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
df58fc94 RS |
6999 | treg = 0; |
7000 | else | |
252b5132 | 7001 | { |
df58fc94 RS |
7002 | treg = AT; |
7003 | used_at = 1; | |
7004 | load_register (treg, &imm_expr, HAVE_64BIT_GPRS); | |
252b5132 | 7005 | } |
df58fc94 RS |
7006 | /* Fall through. */ |
7007 | case M_BEQL: | |
7008 | case M_BNEL: | |
7009 | macro_build_branch_rsrt (mask, &offset_expr, sreg, treg); | |
252b5132 RH |
7010 | break; |
7011 | ||
7012 | case M_BGEL: | |
7013 | likely = 1; | |
7014 | case M_BGE: | |
7015 | if (treg == 0) | |
df58fc94 RS |
7016 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, sreg); |
7017 | else if (sreg == 0) | |
7018 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, treg); | |
7019 | else | |
252b5132 | 7020 | { |
df58fc94 RS |
7021 | used_at = 1; |
7022 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); | |
7023 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
7024 | &offset_expr, AT, ZERO); | |
252b5132 | 7025 | } |
df58fc94 RS |
7026 | break; |
7027 | ||
7028 | case M_BGEZL: | |
7029 | case M_BGEZALL: | |
7030 | case M_BGTZL: | |
7031 | case M_BLEZL: | |
7032 | case M_BLTZL: | |
7033 | case M_BLTZALL: | |
7034 | macro_build_branch_rs (mask, &offset_expr, sreg); | |
252b5132 RH |
7035 | break; |
7036 | ||
7037 | case M_BGTL_I: | |
7038 | likely = 1; | |
7039 | case M_BGT_I: | |
90ecf173 | 7040 | /* Check for > max integer. */ |
42429eac | 7041 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number >= GPR_SMAX) |
252b5132 RH |
7042 | { |
7043 | do_false: | |
90ecf173 | 7044 | /* Result is always false. */ |
252b5132 | 7045 | if (! likely) |
a605d2b3 | 7046 | macro_build (NULL, "nop", ""); |
252b5132 | 7047 | else |
df58fc94 | 7048 | macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO); |
8fc2e39e | 7049 | break; |
252b5132 RH |
7050 | } |
7051 | if (imm_expr.X_op != O_constant) | |
7052 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 7053 | ++imm_expr.X_add_number; |
252b5132 RH |
7054 | /* FALLTHROUGH */ |
7055 | case M_BGE_I: | |
7056 | case M_BGEL_I: | |
7057 | if (mask == M_BGEL_I) | |
7058 | likely = 1; | |
7059 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7060 | { | |
df58fc94 RS |
7061 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, |
7062 | &offset_expr, sreg); | |
8fc2e39e | 7063 | break; |
252b5132 RH |
7064 | } |
7065 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
7066 | { | |
df58fc94 RS |
7067 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, |
7068 | &offset_expr, sreg); | |
8fc2e39e | 7069 | break; |
252b5132 | 7070 | } |
42429eac | 7071 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number <= GPR_SMIN) |
252b5132 RH |
7072 | { |
7073 | do_true: | |
7074 | /* result is always true */ | |
7075 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
67c0d1eb | 7076 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 7077 | break; |
252b5132 | 7078 | } |
8fc2e39e | 7079 | used_at = 1; |
67c0d1eb | 7080 | set_at (sreg, 0); |
df58fc94 RS |
7081 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
7082 | &offset_expr, AT, ZERO); | |
252b5132 RH |
7083 | break; |
7084 | ||
7085 | case M_BGEUL: | |
7086 | likely = 1; | |
7087 | case M_BGEU: | |
7088 | if (treg == 0) | |
7089 | goto do_true; | |
df58fc94 RS |
7090 | else if (sreg == 0) |
7091 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
7092 | &offset_expr, ZERO, treg); | |
7093 | else | |
252b5132 | 7094 | { |
df58fc94 RS |
7095 | used_at = 1; |
7096 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); | |
7097 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
7098 | &offset_expr, AT, ZERO); | |
252b5132 | 7099 | } |
252b5132 RH |
7100 | break; |
7101 | ||
7102 | case M_BGTUL_I: | |
7103 | likely = 1; | |
7104 | case M_BGTU_I: | |
7105 | if (sreg == 0 | |
ca4e0257 | 7106 | || (HAVE_32BIT_GPRS |
252b5132 | 7107 | && imm_expr.X_op == O_constant |
f01dc953 | 7108 | && imm_expr.X_add_number == -1)) |
252b5132 RH |
7109 | goto do_false; |
7110 | if (imm_expr.X_op != O_constant) | |
7111 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 7112 | ++imm_expr.X_add_number; |
252b5132 RH |
7113 | /* FALLTHROUGH */ |
7114 | case M_BGEU_I: | |
7115 | case M_BGEUL_I: | |
7116 | if (mask == M_BGEUL_I) | |
7117 | likely = 1; | |
7118 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7119 | goto do_true; | |
df58fc94 RS |
7120 | else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
7121 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
7122 | &offset_expr, sreg, ZERO); | |
7123 | else | |
252b5132 | 7124 | { |
df58fc94 RS |
7125 | used_at = 1; |
7126 | set_at (sreg, 1); | |
7127 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
7128 | &offset_expr, AT, ZERO); | |
252b5132 | 7129 | } |
252b5132 RH |
7130 | break; |
7131 | ||
7132 | case M_BGTL: | |
7133 | likely = 1; | |
7134 | case M_BGT: | |
7135 | if (treg == 0) | |
df58fc94 RS |
7136 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, sreg); |
7137 | else if (sreg == 0) | |
7138 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, treg); | |
7139 | else | |
252b5132 | 7140 | { |
df58fc94 RS |
7141 | used_at = 1; |
7142 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); | |
7143 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
7144 | &offset_expr, AT, ZERO); | |
252b5132 | 7145 | } |
252b5132 RH |
7146 | break; |
7147 | ||
7148 | case M_BGTUL: | |
7149 | likely = 1; | |
7150 | case M_BGTU: | |
7151 | if (treg == 0) | |
df58fc94 RS |
7152 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
7153 | &offset_expr, sreg, ZERO); | |
7154 | else if (sreg == 0) | |
7155 | goto do_false; | |
7156 | else | |
252b5132 | 7157 | { |
df58fc94 RS |
7158 | used_at = 1; |
7159 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); | |
7160 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
7161 | &offset_expr, AT, ZERO); | |
252b5132 | 7162 | } |
252b5132 RH |
7163 | break; |
7164 | ||
7165 | case M_BLEL: | |
7166 | likely = 1; | |
7167 | case M_BLE: | |
7168 | if (treg == 0) | |
df58fc94 RS |
7169 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg); |
7170 | else if (sreg == 0) | |
7171 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, treg); | |
7172 | else | |
252b5132 | 7173 | { |
df58fc94 RS |
7174 | used_at = 1; |
7175 | macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); | |
7176 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
7177 | &offset_expr, AT, ZERO); | |
252b5132 | 7178 | } |
252b5132 RH |
7179 | break; |
7180 | ||
7181 | case M_BLEL_I: | |
7182 | likely = 1; | |
7183 | case M_BLE_I: | |
42429eac | 7184 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number >= GPR_SMAX) |
252b5132 RH |
7185 | goto do_true; |
7186 | if (imm_expr.X_op != O_constant) | |
7187 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 7188 | ++imm_expr.X_add_number; |
252b5132 RH |
7189 | /* FALLTHROUGH */ |
7190 | case M_BLT_I: | |
7191 | case M_BLTL_I: | |
7192 | if (mask == M_BLTL_I) | |
7193 | likely = 1; | |
7194 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
df58fc94 RS |
7195 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg); |
7196 | else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
7197 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, sreg); | |
7198 | else | |
252b5132 | 7199 | { |
df58fc94 RS |
7200 | used_at = 1; |
7201 | set_at (sreg, 0); | |
7202 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
7203 | &offset_expr, AT, ZERO); | |
252b5132 | 7204 | } |
252b5132 RH |
7205 | break; |
7206 | ||
7207 | case M_BLEUL: | |
7208 | likely = 1; | |
7209 | case M_BLEU: | |
7210 | if (treg == 0) | |
df58fc94 RS |
7211 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
7212 | &offset_expr, sreg, ZERO); | |
7213 | else if (sreg == 0) | |
7214 | goto do_true; | |
7215 | else | |
252b5132 | 7216 | { |
df58fc94 RS |
7217 | used_at = 1; |
7218 | macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); | |
7219 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
7220 | &offset_expr, AT, ZERO); | |
252b5132 | 7221 | } |
252b5132 RH |
7222 | break; |
7223 | ||
7224 | case M_BLEUL_I: | |
7225 | likely = 1; | |
7226 | case M_BLEU_I: | |
7227 | if (sreg == 0 | |
ca4e0257 | 7228 | || (HAVE_32BIT_GPRS |
252b5132 | 7229 | && imm_expr.X_op == O_constant |
f01dc953 | 7230 | && imm_expr.X_add_number == -1)) |
252b5132 RH |
7231 | goto do_true; |
7232 | if (imm_expr.X_op != O_constant) | |
7233 | as_bad (_("Unsupported large constant")); | |
f9419b05 | 7234 | ++imm_expr.X_add_number; |
252b5132 RH |
7235 | /* FALLTHROUGH */ |
7236 | case M_BLTU_I: | |
7237 | case M_BLTUL_I: | |
7238 | if (mask == M_BLTUL_I) | |
7239 | likely = 1; | |
7240 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7241 | goto do_false; | |
df58fc94 RS |
7242 | else if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
7243 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, | |
7244 | &offset_expr, sreg, ZERO); | |
7245 | else | |
252b5132 | 7246 | { |
df58fc94 RS |
7247 | used_at = 1; |
7248 | set_at (sreg, 1); | |
7249 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
7250 | &offset_expr, AT, ZERO); | |
252b5132 | 7251 | } |
252b5132 RH |
7252 | break; |
7253 | ||
7254 | case M_BLTL: | |
7255 | likely = 1; | |
7256 | case M_BLT: | |
7257 | if (treg == 0) | |
df58fc94 RS |
7258 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, sreg); |
7259 | else if (sreg == 0) | |
7260 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, treg); | |
7261 | else | |
252b5132 | 7262 | { |
df58fc94 RS |
7263 | used_at = 1; |
7264 | macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); | |
7265 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
7266 | &offset_expr, AT, ZERO); | |
252b5132 | 7267 | } |
252b5132 RH |
7268 | break; |
7269 | ||
7270 | case M_BLTUL: | |
7271 | likely = 1; | |
7272 | case M_BLTU: | |
7273 | if (treg == 0) | |
7274 | goto do_false; | |
df58fc94 RS |
7275 | else if (sreg == 0) |
7276 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
7277 | &offset_expr, ZERO, treg); | |
7278 | else | |
252b5132 | 7279 | { |
df58fc94 RS |
7280 | used_at = 1; |
7281 | macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); | |
7282 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, | |
7283 | &offset_expr, AT, ZERO); | |
252b5132 | 7284 | } |
252b5132 RH |
7285 | break; |
7286 | ||
5f74bc13 CD |
7287 | case M_DEXT: |
7288 | { | |
d5818fca MR |
7289 | /* Use unsigned arithmetic. */ |
7290 | addressT pos; | |
7291 | addressT size; | |
5f74bc13 | 7292 | |
90ecf173 | 7293 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) |
5f74bc13 CD |
7294 | { |
7295 | as_bad (_("Unsupported large constant")); | |
7296 | pos = size = 1; | |
7297 | } | |
7298 | else | |
7299 | { | |
d5818fca MR |
7300 | pos = imm_expr.X_add_number; |
7301 | size = imm2_expr.X_add_number; | |
5f74bc13 CD |
7302 | } |
7303 | ||
7304 | if (pos > 63) | |
7305 | { | |
d5818fca | 7306 | as_bad (_("Improper position (%lu)"), (unsigned long) pos); |
5f74bc13 CD |
7307 | pos = 1; |
7308 | } | |
90ecf173 | 7309 | if (size == 0 || size > 64 || (pos + size - 1) > 63) |
5f74bc13 CD |
7310 | { |
7311 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
d5818fca | 7312 | (unsigned long) size, (unsigned long) pos); |
5f74bc13 CD |
7313 | size = 1; |
7314 | } | |
7315 | ||
7316 | if (size <= 32 && pos < 32) | |
7317 | { | |
7318 | s = "dext"; | |
7319 | fmt = "t,r,+A,+C"; | |
7320 | } | |
7321 | else if (size <= 32) | |
7322 | { | |
7323 | s = "dextu"; | |
7324 | fmt = "t,r,+E,+H"; | |
7325 | } | |
7326 | else | |
7327 | { | |
7328 | s = "dextm"; | |
7329 | fmt = "t,r,+A,+G"; | |
7330 | } | |
d5818fca MR |
7331 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos, |
7332 | (int) (size - 1)); | |
5f74bc13 | 7333 | } |
8fc2e39e | 7334 | break; |
5f74bc13 CD |
7335 | |
7336 | case M_DINS: | |
7337 | { | |
d5818fca MR |
7338 | /* Use unsigned arithmetic. */ |
7339 | addressT pos; | |
7340 | addressT size; | |
5f74bc13 | 7341 | |
90ecf173 | 7342 | if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) |
5f74bc13 CD |
7343 | { |
7344 | as_bad (_("Unsupported large constant")); | |
7345 | pos = size = 1; | |
7346 | } | |
7347 | else | |
7348 | { | |
d5818fca MR |
7349 | pos = imm_expr.X_add_number; |
7350 | size = imm2_expr.X_add_number; | |
5f74bc13 CD |
7351 | } |
7352 | ||
7353 | if (pos > 63) | |
7354 | { | |
d5818fca | 7355 | as_bad (_("Improper position (%lu)"), (unsigned long) pos); |
5f74bc13 CD |
7356 | pos = 1; |
7357 | } | |
90ecf173 | 7358 | if (size == 0 || size > 64 || (pos + size - 1) > 63) |
5f74bc13 CD |
7359 | { |
7360 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
d5818fca | 7361 | (unsigned long) size, (unsigned long) pos); |
5f74bc13 CD |
7362 | size = 1; |
7363 | } | |
7364 | ||
7365 | if (pos < 32 && (pos + size - 1) < 32) | |
7366 | { | |
7367 | s = "dins"; | |
7368 | fmt = "t,r,+A,+B"; | |
7369 | } | |
7370 | else if (pos >= 32) | |
7371 | { | |
7372 | s = "dinsu"; | |
7373 | fmt = "t,r,+E,+F"; | |
7374 | } | |
7375 | else | |
7376 | { | |
7377 | s = "dinsm"; | |
7378 | fmt = "t,r,+A,+F"; | |
7379 | } | |
750bdd57 AS |
7380 | macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos, |
7381 | (int) (pos + size - 1)); | |
5f74bc13 | 7382 | } |
8fc2e39e | 7383 | break; |
5f74bc13 | 7384 | |
252b5132 RH |
7385 | case M_DDIV_3: |
7386 | dbl = 1; | |
7387 | case M_DIV_3: | |
7388 | s = "mflo"; | |
7389 | goto do_div3; | |
7390 | case M_DREM_3: | |
7391 | dbl = 1; | |
7392 | case M_REM_3: | |
7393 | s = "mfhi"; | |
7394 | do_div3: | |
7395 | if (treg == 0) | |
7396 | { | |
7397 | as_warn (_("Divide by zero.")); | |
7398 | if (mips_trap) | |
df58fc94 | 7399 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 7400 | else |
df58fc94 | 7401 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 7402 | break; |
252b5132 RH |
7403 | } |
7404 | ||
7d10b47d | 7405 | start_noreorder (); |
252b5132 RH |
7406 | if (mips_trap) |
7407 | { | |
df58fc94 | 7408 | macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7); |
67c0d1eb | 7409 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
252b5132 RH |
7410 | } |
7411 | else | |
7412 | { | |
df58fc94 RS |
7413 | if (mips_opts.micromips) |
7414 | micromips_label_expr (&label_expr); | |
7415 | else | |
7416 | label_expr.X_add_number = 8; | |
7417 | macro_build (&label_expr, "bne", "s,t,p", treg, ZERO); | |
67c0d1eb | 7418 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
df58fc94 RS |
7419 | macro_build (NULL, "break", BRK_FMT, 7); |
7420 | if (mips_opts.micromips) | |
7421 | micromips_add_label (); | |
252b5132 RH |
7422 | } |
7423 | expr1.X_add_number = -1; | |
8fc2e39e | 7424 | used_at = 1; |
f6a22291 | 7425 | load_register (AT, &expr1, dbl); |
df58fc94 RS |
7426 | if (mips_opts.micromips) |
7427 | micromips_label_expr (&label_expr); | |
7428 | else | |
7429 | label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); | |
7430 | macro_build (&label_expr, "bne", "s,t,p", treg, AT); | |
252b5132 RH |
7431 | if (dbl) |
7432 | { | |
7433 | expr1.X_add_number = 1; | |
f6a22291 | 7434 | load_register (AT, &expr1, dbl); |
df58fc94 | 7435 | macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31); |
252b5132 RH |
7436 | } |
7437 | else | |
7438 | { | |
7439 | expr1.X_add_number = 0x80000000; | |
df58fc94 | 7440 | macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16); |
252b5132 RH |
7441 | } |
7442 | if (mips_trap) | |
7443 | { | |
df58fc94 | 7444 | macro_build (NULL, "teq", TRAP_FMT, sreg, AT, 6); |
252b5132 RH |
7445 | /* We want to close the noreorder block as soon as possible, so |
7446 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7447 | end_noreorder (); |
252b5132 RH |
7448 | } |
7449 | else | |
7450 | { | |
df58fc94 RS |
7451 | if (mips_opts.micromips) |
7452 | micromips_label_expr (&label_expr); | |
7453 | else | |
7454 | label_expr.X_add_number = 8; | |
7455 | macro_build (&label_expr, "bne", "s,t,p", sreg, AT); | |
a605d2b3 | 7456 | macro_build (NULL, "nop", ""); |
252b5132 RH |
7457 | |
7458 | /* We want to close the noreorder block as soon as possible, so | |
7459 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7460 | end_noreorder (); |
252b5132 | 7461 | |
df58fc94 | 7462 | macro_build (NULL, "break", BRK_FMT, 6); |
252b5132 | 7463 | } |
df58fc94 RS |
7464 | if (mips_opts.micromips) |
7465 | micromips_add_label (); | |
7466 | macro_build (NULL, s, MFHL_FMT, dreg); | |
252b5132 RH |
7467 | break; |
7468 | ||
7469 | case M_DIV_3I: | |
7470 | s = "div"; | |
7471 | s2 = "mflo"; | |
7472 | goto do_divi; | |
7473 | case M_DIVU_3I: | |
7474 | s = "divu"; | |
7475 | s2 = "mflo"; | |
7476 | goto do_divi; | |
7477 | case M_REM_3I: | |
7478 | s = "div"; | |
7479 | s2 = "mfhi"; | |
7480 | goto do_divi; | |
7481 | case M_REMU_3I: | |
7482 | s = "divu"; | |
7483 | s2 = "mfhi"; | |
7484 | goto do_divi; | |
7485 | case M_DDIV_3I: | |
7486 | dbl = 1; | |
7487 | s = "ddiv"; | |
7488 | s2 = "mflo"; | |
7489 | goto do_divi; | |
7490 | case M_DDIVU_3I: | |
7491 | dbl = 1; | |
7492 | s = "ddivu"; | |
7493 | s2 = "mflo"; | |
7494 | goto do_divi; | |
7495 | case M_DREM_3I: | |
7496 | dbl = 1; | |
7497 | s = "ddiv"; | |
7498 | s2 = "mfhi"; | |
7499 | goto do_divi; | |
7500 | case M_DREMU_3I: | |
7501 | dbl = 1; | |
7502 | s = "ddivu"; | |
7503 | s2 = "mfhi"; | |
7504 | do_divi: | |
7505 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
7506 | { | |
7507 | as_warn (_("Divide by zero.")); | |
7508 | if (mips_trap) | |
df58fc94 | 7509 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 7510 | else |
df58fc94 | 7511 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 7512 | break; |
252b5132 RH |
7513 | } |
7514 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
7515 | { | |
7516 | if (strcmp (s2, "mflo") == 0) | |
67c0d1eb | 7517 | move_register (dreg, sreg); |
252b5132 | 7518 | else |
c80c840e | 7519 | move_register (dreg, ZERO); |
8fc2e39e | 7520 | break; |
252b5132 RH |
7521 | } |
7522 | if (imm_expr.X_op == O_constant | |
7523 | && imm_expr.X_add_number == -1 | |
7524 | && s[strlen (s) - 1] != 'u') | |
7525 | { | |
7526 | if (strcmp (s2, "mflo") == 0) | |
7527 | { | |
67c0d1eb | 7528 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg); |
252b5132 RH |
7529 | } |
7530 | else | |
c80c840e | 7531 | move_register (dreg, ZERO); |
8fc2e39e | 7532 | break; |
252b5132 RH |
7533 | } |
7534 | ||
8fc2e39e | 7535 | used_at = 1; |
67c0d1eb RS |
7536 | load_register (AT, &imm_expr, dbl); |
7537 | macro_build (NULL, s, "z,s,t", sreg, AT); | |
df58fc94 | 7538 | macro_build (NULL, s2, MFHL_FMT, dreg); |
252b5132 RH |
7539 | break; |
7540 | ||
7541 | case M_DIVU_3: | |
7542 | s = "divu"; | |
7543 | s2 = "mflo"; | |
7544 | goto do_divu3; | |
7545 | case M_REMU_3: | |
7546 | s = "divu"; | |
7547 | s2 = "mfhi"; | |
7548 | goto do_divu3; | |
7549 | case M_DDIVU_3: | |
7550 | s = "ddivu"; | |
7551 | s2 = "mflo"; | |
7552 | goto do_divu3; | |
7553 | case M_DREMU_3: | |
7554 | s = "ddivu"; | |
7555 | s2 = "mfhi"; | |
7556 | do_divu3: | |
7d10b47d | 7557 | start_noreorder (); |
252b5132 RH |
7558 | if (mips_trap) |
7559 | { | |
df58fc94 | 7560 | macro_build (NULL, "teq", TRAP_FMT, treg, ZERO, 7); |
67c0d1eb | 7561 | macro_build (NULL, s, "z,s,t", sreg, treg); |
252b5132 RH |
7562 | /* We want to close the noreorder block as soon as possible, so |
7563 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7564 | end_noreorder (); |
252b5132 RH |
7565 | } |
7566 | else | |
7567 | { | |
df58fc94 RS |
7568 | if (mips_opts.micromips) |
7569 | micromips_label_expr (&label_expr); | |
7570 | else | |
7571 | label_expr.X_add_number = 8; | |
7572 | macro_build (&label_expr, "bne", "s,t,p", treg, ZERO); | |
67c0d1eb | 7573 | macro_build (NULL, s, "z,s,t", sreg, treg); |
252b5132 RH |
7574 | |
7575 | /* We want to close the noreorder block as soon as possible, so | |
7576 | that later insns are available for delay slot filling. */ | |
7d10b47d | 7577 | end_noreorder (); |
df58fc94 RS |
7578 | macro_build (NULL, "break", BRK_FMT, 7); |
7579 | if (mips_opts.micromips) | |
7580 | micromips_add_label (); | |
252b5132 | 7581 | } |
df58fc94 | 7582 | macro_build (NULL, s2, MFHL_FMT, dreg); |
8fc2e39e | 7583 | break; |
252b5132 | 7584 | |
1abe91b1 MR |
7585 | case M_DLCA_AB: |
7586 | dbl = 1; | |
7587 | case M_LCA_AB: | |
7588 | call = 1; | |
7589 | goto do_la; | |
252b5132 RH |
7590 | case M_DLA_AB: |
7591 | dbl = 1; | |
7592 | case M_LA_AB: | |
1abe91b1 | 7593 | do_la: |
252b5132 RH |
7594 | /* Load the address of a symbol into a register. If breg is not |
7595 | zero, we then add a base register to it. */ | |
7596 | ||
3bec30a8 TS |
7597 | if (dbl && HAVE_32BIT_GPRS) |
7598 | as_warn (_("dla used to load 32-bit register")); | |
7599 | ||
90ecf173 | 7600 | if (!dbl && HAVE_64BIT_OBJECTS) |
3bec30a8 TS |
7601 | as_warn (_("la used to load 64-bit address")); |
7602 | ||
f2ae14a1 | 7603 | if (small_offset_p (0, align, 16)) |
0c11417f | 7604 | { |
f2ae14a1 RS |
7605 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", treg, breg, |
7606 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]); | |
8fc2e39e | 7607 | break; |
0c11417f MR |
7608 | } |
7609 | ||
741fe287 | 7610 | if (mips_opts.at && (treg == breg)) |
afdbd6d0 CD |
7611 | { |
7612 | tempreg = AT; | |
7613 | used_at = 1; | |
7614 | } | |
7615 | else | |
7616 | { | |
7617 | tempreg = treg; | |
afdbd6d0 CD |
7618 | } |
7619 | ||
252b5132 RH |
7620 | if (offset_expr.X_op != O_symbol |
7621 | && offset_expr.X_op != O_constant) | |
7622 | { | |
f71d0d44 | 7623 | as_bad (_("Expression too complex")); |
252b5132 RH |
7624 | offset_expr.X_op = O_constant; |
7625 | } | |
7626 | ||
252b5132 | 7627 | if (offset_expr.X_op == O_constant) |
aed1a261 | 7628 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
7629 | else if (mips_pic == NO_PIC) |
7630 | { | |
d6bc6245 | 7631 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 7632 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
7633 | Otherwise we want |
7634 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
7635 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7636 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 7637 | so we may as well always use the latter form. |
76b3015f | 7638 | |
6caf9ef4 TS |
7639 | With 64bit address space and a usable $at we want |
7640 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
7641 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
7642 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
7643 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
7644 | dsll32 $tempreg,0 | |
7645 | daddu $tempreg,$tempreg,$at | |
7646 | ||
7647 | If $at is already in use, we use a path which is suboptimal | |
7648 | on superscalar processors. | |
7649 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
7650 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
7651 | dsll $tempreg,16 | |
7652 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
7653 | dsll $tempreg,16 | |
7654 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
7655 | ||
7656 | For GP relative symbols in 64bit address space we can use | |
7657 | the same sequence as in 32bit address space. */ | |
aed1a261 | 7658 | if (HAVE_64BIT_SYMBOLS) |
252b5132 | 7659 | { |
6caf9ef4 TS |
7660 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
7661 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
7662 | { | |
7663 | relax_start (offset_expr.X_add_symbol); | |
7664 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
7665 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
7666 | relax_switch (); | |
7667 | } | |
d6bc6245 | 7668 | |
741fe287 | 7669 | if (used_at == 0 && mips_opts.at) |
98d3f06f | 7670 | { |
df58fc94 | 7671 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 7672 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 7673 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 7674 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 7675 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7676 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 7677 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7678 | AT, AT, BFD_RELOC_LO16); |
df58fc94 | 7679 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb | 7680 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
98d3f06f KH |
7681 | used_at = 1; |
7682 | } | |
7683 | else | |
7684 | { | |
df58fc94 | 7685 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 7686 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 7687 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7688 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
df58fc94 | 7689 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 7690 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7691 | tempreg, tempreg, BFD_RELOC_HI16_S); |
df58fc94 | 7692 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 7693 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 7694 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 7695 | } |
6caf9ef4 TS |
7696 | |
7697 | if (mips_relax.sequence) | |
7698 | relax_end (); | |
98d3f06f KH |
7699 | } |
7700 | else | |
7701 | { | |
7702 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 7703 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
98d3f06f | 7704 | { |
4d7206a2 | 7705 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7706 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7707 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 7708 | relax_switch (); |
98d3f06f | 7709 | } |
6943caf0 | 7710 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
f71d0d44 | 7711 | as_bad (_("Offset too large")); |
67c0d1eb RS |
7712 | macro_build_lui (&offset_expr, tempreg); |
7713 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
7714 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
7715 | if (mips_relax.sequence) |
7716 | relax_end (); | |
98d3f06f | 7717 | } |
252b5132 | 7718 | } |
0a44bf69 | 7719 | else if (!mips_big_got && !HAVE_NEWABI) |
252b5132 | 7720 | { |
9117d219 NC |
7721 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
7722 | ||
252b5132 RH |
7723 | /* If this is a reference to an external symbol, and there |
7724 | is no constant, we want | |
7725 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 7726 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 7727 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
7728 | For a local symbol, we want |
7729 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7730 | nop | |
7731 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7732 | ||
7733 | If we have a small constant, and this is a reference to | |
7734 | an external symbol, we want | |
7735 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7736 | nop | |
7737 | addiu $tempreg,$tempreg,<constant> | |
7738 | For a local symbol, we want the same instruction | |
7739 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
7740 | addiu instruction. | |
7741 | ||
7742 | If we have a large constant, and this is a reference to | |
7743 | an external symbol, we want | |
7744 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7745 | lui $at,<hiconstant> | |
7746 | addiu $at,$at,<loconstant> | |
7747 | addu $tempreg,$tempreg,$at | |
7748 | For a local symbol, we want the same instruction | |
7749 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 7750 | addiu instruction. |
ed6fb7bd SC |
7751 | */ |
7752 | ||
4d7206a2 | 7753 | if (offset_expr.X_add_number == 0) |
252b5132 | 7754 | { |
0a44bf69 RS |
7755 | if (mips_pic == SVR4_PIC |
7756 | && breg == 0 | |
7757 | && (call || tempreg == PIC_CALL_REG)) | |
4d7206a2 RS |
7758 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; |
7759 | ||
7760 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
7761 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7762 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 7763 | if (breg != 0) |
252b5132 RH |
7764 | { |
7765 | /* We're going to put in an addu instruction using | |
7766 | tempreg, so we may as well insert the nop right | |
7767 | now. */ | |
269137b2 | 7768 | load_delay_nop (); |
252b5132 | 7769 | } |
4d7206a2 | 7770 | relax_switch (); |
67c0d1eb RS |
7771 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
7772 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 7773 | load_delay_nop (); |
67c0d1eb RS |
7774 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
7775 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 7776 | relax_end (); |
252b5132 RH |
7777 | /* FIXME: If breg == 0, and the next instruction uses |
7778 | $tempreg, then if this variant case is used an extra | |
7779 | nop will be generated. */ | |
7780 | } | |
4d7206a2 RS |
7781 | else if (offset_expr.X_add_number >= -0x8000 |
7782 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 7783 | { |
67c0d1eb | 7784 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 7785 | load_delay_nop (); |
67c0d1eb | 7786 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
7787 | } |
7788 | else | |
7789 | { | |
4d7206a2 RS |
7790 | expr1.X_add_number = offset_expr.X_add_number; |
7791 | offset_expr.X_add_number = | |
43c0598f | 7792 | SEXT_16BIT (offset_expr.X_add_number); |
67c0d1eb | 7793 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 7794 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
7795 | /* If we are going to add in a base register, and the |
7796 | target register and the base register are the same, | |
7797 | then we are using AT as a temporary register. Since | |
7798 | we want to load the constant into AT, we add our | |
7799 | current AT (from the global offset table) and the | |
7800 | register into the register now, and pretend we were | |
7801 | not using a base register. */ | |
67c0d1eb | 7802 | if (breg == treg) |
252b5132 | 7803 | { |
269137b2 | 7804 | load_delay_nop (); |
67c0d1eb | 7805 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7806 | treg, AT, breg); |
252b5132 RH |
7807 | breg = 0; |
7808 | tempreg = treg; | |
252b5132 | 7809 | } |
f6a22291 | 7810 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
7811 | used_at = 1; |
7812 | } | |
7813 | } | |
0a44bf69 | 7814 | else if (!mips_big_got && HAVE_NEWABI) |
f5040a92 | 7815 | { |
67c0d1eb | 7816 | int add_breg_early = 0; |
f5040a92 AO |
7817 | |
7818 | /* If this is a reference to an external, and there is no | |
7819 | constant, or local symbol (*), with or without a | |
7820 | constant, we want | |
7821 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 7822 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
7823 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
7824 | ||
7825 | If we have a small constant, and this is a reference to | |
7826 | an external symbol, we want | |
7827 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
7828 | addiu $tempreg,$tempreg,<constant> | |
7829 | ||
7830 | If we have a large constant, and this is a reference to | |
7831 | an external symbol, we want | |
7832 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
7833 | lui $at,<hiconstant> | |
7834 | addiu $at,$at,<loconstant> | |
7835 | addu $tempreg,$tempreg,$at | |
7836 | ||
7837 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
7838 | local symbols, even though it introduces an additional | |
7839 | instruction. */ | |
7840 | ||
f5040a92 AO |
7841 | if (offset_expr.X_add_number) |
7842 | { | |
4d7206a2 | 7843 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
7844 | offset_expr.X_add_number = 0; |
7845 | ||
4d7206a2 | 7846 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7847 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7848 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
7849 | |
7850 | if (expr1.X_add_number >= -0x8000 | |
7851 | && expr1.X_add_number < 0x8000) | |
7852 | { | |
67c0d1eb RS |
7853 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
7854 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 7855 | } |
ecd13cd3 | 7856 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 7857 | { |
f5040a92 AO |
7858 | /* If we are going to add in a base register, and the |
7859 | target register and the base register are the same, | |
7860 | then we are using AT as a temporary register. Since | |
7861 | we want to load the constant into AT, we add our | |
7862 | current AT (from the global offset table) and the | |
7863 | register into the register now, and pretend we were | |
7864 | not using a base register. */ | |
7865 | if (breg != treg) | |
7866 | dreg = tempreg; | |
7867 | else | |
7868 | { | |
9c2799c2 | 7869 | gas_assert (tempreg == AT); |
67c0d1eb RS |
7870 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
7871 | treg, AT, breg); | |
f5040a92 | 7872 | dreg = treg; |
67c0d1eb | 7873 | add_breg_early = 1; |
f5040a92 AO |
7874 | } |
7875 | ||
f6a22291 | 7876 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 7877 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7878 | dreg, dreg, AT); |
f5040a92 | 7879 | |
f5040a92 AO |
7880 | used_at = 1; |
7881 | } | |
7882 | else | |
7883 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
7884 | ||
4d7206a2 | 7885 | relax_switch (); |
f5040a92 AO |
7886 | offset_expr.X_add_number = expr1.X_add_number; |
7887 | ||
67c0d1eb RS |
7888 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7889 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
7890 | if (add_breg_early) | |
f5040a92 | 7891 | { |
67c0d1eb | 7892 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
f899b4b8 | 7893 | treg, tempreg, breg); |
f5040a92 AO |
7894 | breg = 0; |
7895 | tempreg = treg; | |
7896 | } | |
4d7206a2 | 7897 | relax_end (); |
f5040a92 | 7898 | } |
4d7206a2 | 7899 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 7900 | { |
4d7206a2 | 7901 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
7902 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7903 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 7904 | relax_switch (); |
67c0d1eb RS |
7905 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7906 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 7907 | relax_end (); |
f5040a92 | 7908 | } |
4d7206a2 | 7909 | else |
f5040a92 | 7910 | { |
67c0d1eb RS |
7911 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
7912 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
7913 | } |
7914 | } | |
0a44bf69 | 7915 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 7916 | { |
67c0d1eb | 7917 | int gpdelay; |
9117d219 NC |
7918 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
7919 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 7920 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
7921 | |
7922 | /* This is the large GOT case. If this is a reference to an | |
7923 | external symbol, and there is no constant, we want | |
7924 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7925 | addu $tempreg,$tempreg,$gp | |
7926 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 7927 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
7928 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
7929 | addu $tempreg,$tempreg,$gp | |
7930 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
7931 | For a local symbol, we want |
7932 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7933 | nop | |
7934 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
7935 | ||
7936 | If we have a small constant, and this is a reference to | |
7937 | an external symbol, we want | |
7938 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7939 | addu $tempreg,$tempreg,$gp | |
7940 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7941 | nop | |
7942 | addiu $tempreg,$tempreg,<constant> | |
7943 | For a local symbol, we want | |
7944 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7945 | nop | |
7946 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
7947 | ||
7948 | If we have a large constant, and this is a reference to | |
7949 | an external symbol, we want | |
7950 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
7951 | addu $tempreg,$tempreg,$gp | |
7952 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
7953 | lui $at,<hiconstant> | |
7954 | addiu $at,$at,<loconstant> | |
7955 | addu $tempreg,$tempreg,$at | |
7956 | For a local symbol, we want | |
7957 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
7958 | lui $at,<hiconstant> | |
7959 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
7960 | addu $tempreg,$tempreg,$at | |
f5040a92 | 7961 | */ |
438c16b8 | 7962 | |
252b5132 RH |
7963 | expr1.X_add_number = offset_expr.X_add_number; |
7964 | offset_expr.X_add_number = 0; | |
4d7206a2 | 7965 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 7966 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
7967 | if (expr1.X_add_number == 0 && breg == 0 |
7968 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
7969 | { |
7970 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
7971 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
7972 | } | |
df58fc94 | 7973 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 7974 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 7975 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 7976 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 7977 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
7978 | if (expr1.X_add_number == 0) |
7979 | { | |
67c0d1eb | 7980 | if (breg != 0) |
252b5132 RH |
7981 | { |
7982 | /* We're going to put in an addu instruction using | |
7983 | tempreg, so we may as well insert the nop right | |
7984 | now. */ | |
269137b2 | 7985 | load_delay_nop (); |
252b5132 | 7986 | } |
252b5132 RH |
7987 | } |
7988 | else if (expr1.X_add_number >= -0x8000 | |
7989 | && expr1.X_add_number < 0x8000) | |
7990 | { | |
269137b2 | 7991 | load_delay_nop (); |
67c0d1eb | 7992 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 7993 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
7994 | } |
7995 | else | |
7996 | { | |
252b5132 RH |
7997 | /* If we are going to add in a base register, and the |
7998 | target register and the base register are the same, | |
7999 | then we are using AT as a temporary register. Since | |
8000 | we want to load the constant into AT, we add our | |
8001 | current AT (from the global offset table) and the | |
8002 | register into the register now, and pretend we were | |
8003 | not using a base register. */ | |
8004 | if (breg != treg) | |
67c0d1eb | 8005 | dreg = tempreg; |
252b5132 RH |
8006 | else |
8007 | { | |
9c2799c2 | 8008 | gas_assert (tempreg == AT); |
269137b2 | 8009 | load_delay_nop (); |
67c0d1eb | 8010 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8011 | treg, AT, breg); |
252b5132 | 8012 | dreg = treg; |
252b5132 RH |
8013 | } |
8014 | ||
f6a22291 | 8015 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 8016 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 8017 | |
252b5132 RH |
8018 | used_at = 1; |
8019 | } | |
43c0598f | 8020 | offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number); |
4d7206a2 | 8021 | relax_switch (); |
252b5132 | 8022 | |
67c0d1eb | 8023 | if (gpdelay) |
252b5132 RH |
8024 | { |
8025 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 8026 | the first instruction on the main stream does not. */ |
67c0d1eb | 8027 | macro_build (NULL, "nop", ""); |
252b5132 | 8028 | } |
ed6fb7bd | 8029 | |
67c0d1eb RS |
8030 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
8031 | local_reloc_type, mips_gp_register); | |
f5040a92 | 8032 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
8033 | && expr1.X_add_number < 0x8000) |
8034 | { | |
269137b2 | 8035 | load_delay_nop (); |
67c0d1eb RS |
8036 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
8037 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 8038 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
8039 | register, the external symbol case ended with a load, |
8040 | so if the symbol turns out to not be external, and | |
8041 | the next instruction uses tempreg, an unnecessary nop | |
8042 | will be inserted. */ | |
252b5132 RH |
8043 | } |
8044 | else | |
8045 | { | |
8046 | if (breg == treg) | |
8047 | { | |
8048 | /* We must add in the base register now, as in the | |
f5040a92 | 8049 | external symbol case. */ |
9c2799c2 | 8050 | gas_assert (tempreg == AT); |
269137b2 | 8051 | load_delay_nop (); |
67c0d1eb | 8052 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8053 | treg, AT, breg); |
252b5132 RH |
8054 | tempreg = treg; |
8055 | /* We set breg to 0 because we have arranged to add | |
f5040a92 | 8056 | it in in both cases. */ |
252b5132 RH |
8057 | breg = 0; |
8058 | } | |
8059 | ||
67c0d1eb RS |
8060 | macro_build_lui (&expr1, AT); |
8061 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 8062 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 8063 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8064 | tempreg, tempreg, AT); |
8fc2e39e | 8065 | used_at = 1; |
252b5132 | 8066 | } |
4d7206a2 | 8067 | relax_end (); |
252b5132 | 8068 | } |
0a44bf69 | 8069 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 8070 | { |
f5040a92 AO |
8071 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
8072 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 8073 | int add_breg_early = 0; |
f5040a92 AO |
8074 | |
8075 | /* This is the large GOT case. If this is a reference to an | |
8076 | external symbol, and there is no constant, we want | |
8077 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
8078 | add $tempreg,$tempreg,$gp | |
8079 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 8080 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
8081 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
8082 | add $tempreg,$tempreg,$gp | |
8083 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
8084 | ||
8085 | If we have a small constant, and this is a reference to | |
8086 | an external symbol, we want | |
8087 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
8088 | add $tempreg,$tempreg,$gp | |
8089 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
8090 | addi $tempreg,$tempreg,<constant> | |
8091 | ||
8092 | If we have a large constant, and this is a reference to | |
8093 | an external symbol, we want | |
8094 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
8095 | addu $tempreg,$tempreg,$gp | |
8096 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
8097 | lui $at,<hiconstant> | |
8098 | addi $at,$at,<loconstant> | |
8099 | add $tempreg,$tempreg,$at | |
8100 | ||
8101 | If we have NewABI, and we know it's a local symbol, we want | |
8102 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
8103 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
8104 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
8105 | ||
4d7206a2 | 8106 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 8107 | |
4d7206a2 | 8108 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
8109 | offset_expr.X_add_number = 0; |
8110 | ||
1abe91b1 MR |
8111 | if (expr1.X_add_number == 0 && breg == 0 |
8112 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
8113 | { |
8114 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
8115 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
8116 | } | |
df58fc94 | 8117 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 8118 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8119 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
8120 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
8121 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
8122 | |
8123 | if (expr1.X_add_number == 0) | |
4d7206a2 | 8124 | ; |
f5040a92 AO |
8125 | else if (expr1.X_add_number >= -0x8000 |
8126 | && expr1.X_add_number < 0x8000) | |
8127 | { | |
67c0d1eb | 8128 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 8129 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 8130 | } |
ecd13cd3 | 8131 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 8132 | { |
f5040a92 AO |
8133 | /* If we are going to add in a base register, and the |
8134 | target register and the base register are the same, | |
8135 | then we are using AT as a temporary register. Since | |
8136 | we want to load the constant into AT, we add our | |
8137 | current AT (from the global offset table) and the | |
8138 | register into the register now, and pretend we were | |
8139 | not using a base register. */ | |
8140 | if (breg != treg) | |
8141 | dreg = tempreg; | |
8142 | else | |
8143 | { | |
9c2799c2 | 8144 | gas_assert (tempreg == AT); |
67c0d1eb | 8145 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8146 | treg, AT, breg); |
f5040a92 | 8147 | dreg = treg; |
67c0d1eb | 8148 | add_breg_early = 1; |
f5040a92 AO |
8149 | } |
8150 | ||
f6a22291 | 8151 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 8152 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 8153 | |
f5040a92 AO |
8154 | used_at = 1; |
8155 | } | |
8156 | else | |
8157 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
8158 | ||
4d7206a2 | 8159 | relax_switch (); |
f5040a92 | 8160 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
8161 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
8162 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
8163 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
8164 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
8165 | if (add_breg_early) | |
f5040a92 | 8166 | { |
67c0d1eb | 8167 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 8168 | treg, tempreg, breg); |
f5040a92 AO |
8169 | breg = 0; |
8170 | tempreg = treg; | |
8171 | } | |
4d7206a2 | 8172 | relax_end (); |
f5040a92 | 8173 | } |
252b5132 RH |
8174 | else |
8175 | abort (); | |
8176 | ||
8177 | if (breg != 0) | |
aed1a261 | 8178 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg); |
252b5132 RH |
8179 | break; |
8180 | ||
52b6b6b9 | 8181 | case M_MSGSND: |
df58fc94 | 8182 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
8183 | { |
8184 | unsigned long temp = (treg << 16) | (0x01); | |
8185 | macro_build (NULL, "c2", "C", temp); | |
8186 | } | |
c7af4273 | 8187 | break; |
52b6b6b9 JM |
8188 | |
8189 | case M_MSGLD: | |
df58fc94 | 8190 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
8191 | { |
8192 | unsigned long temp = (0x02); | |
8193 | macro_build (NULL, "c2", "C", temp); | |
8194 | } | |
c7af4273 | 8195 | break; |
52b6b6b9 JM |
8196 | |
8197 | case M_MSGLD_T: | |
df58fc94 | 8198 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
8199 | { |
8200 | unsigned long temp = (treg << 16) | (0x02); | |
8201 | macro_build (NULL, "c2", "C", temp); | |
8202 | } | |
c7af4273 | 8203 | break; |
52b6b6b9 JM |
8204 | |
8205 | case M_MSGWAIT: | |
df58fc94 | 8206 | gas_assert (!mips_opts.micromips); |
52b6b6b9 | 8207 | macro_build (NULL, "c2", "C", 3); |
c7af4273 | 8208 | break; |
52b6b6b9 JM |
8209 | |
8210 | case M_MSGWAIT_T: | |
df58fc94 | 8211 | gas_assert (!mips_opts.micromips); |
52b6b6b9 JM |
8212 | { |
8213 | unsigned long temp = (treg << 16) | 0x03; | |
8214 | macro_build (NULL, "c2", "C", temp); | |
8215 | } | |
c7af4273 | 8216 | break; |
52b6b6b9 | 8217 | |
252b5132 RH |
8218 | case M_J_A: |
8219 | /* The j instruction may not be used in PIC code, since it | |
8220 | requires an absolute address. We convert it to a b | |
8221 | instruction. */ | |
8222 | if (mips_pic == NO_PIC) | |
67c0d1eb | 8223 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 8224 | else |
67c0d1eb | 8225 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 8226 | break; |
252b5132 RH |
8227 | |
8228 | /* The jal instructions must be handled as macros because when | |
8229 | generating PIC code they expand to multi-instruction | |
8230 | sequences. Normally they are simple instructions. */ | |
df58fc94 RS |
8231 | case M_JALS_1: |
8232 | dreg = RA; | |
8233 | /* Fall through. */ | |
8234 | case M_JALS_2: | |
8235 | gas_assert (mips_opts.micromips); | |
833794fc MR |
8236 | if (mips_opts.insn32) |
8237 | { | |
8238 | as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str); | |
8239 | break; | |
8240 | } | |
df58fc94 RS |
8241 | jals = 1; |
8242 | goto jal; | |
252b5132 RH |
8243 | case M_JAL_1: |
8244 | dreg = RA; | |
8245 | /* Fall through. */ | |
8246 | case M_JAL_2: | |
df58fc94 | 8247 | jal: |
3e722fb5 | 8248 | if (mips_pic == NO_PIC) |
df58fc94 RS |
8249 | { |
8250 | s = jals ? "jalrs" : "jalr"; | |
e64af278 | 8251 | if (mips_opts.micromips |
833794fc | 8252 | && !mips_opts.insn32 |
e64af278 MR |
8253 | && dreg == RA |
8254 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
df58fc94 RS |
8255 | macro_build (NULL, s, "mj", sreg); |
8256 | else | |
8257 | macro_build (NULL, s, JALR_FMT, dreg, sreg); | |
8258 | } | |
0a44bf69 | 8259 | else |
252b5132 | 8260 | { |
df58fc94 RS |
8261 | int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI |
8262 | && mips_cprestore_offset >= 0); | |
8263 | ||
252b5132 RH |
8264 | if (sreg != PIC_CALL_REG) |
8265 | as_warn (_("MIPS PIC call to register other than $25")); | |
bdaaa2e1 | 8266 | |
833794fc MR |
8267 | s = ((mips_opts.micromips |
8268 | && !mips_opts.insn32 | |
8269 | && (!mips_opts.noreorder || cprestore)) | |
df58fc94 | 8270 | ? "jalrs" : "jalr"); |
e64af278 | 8271 | if (mips_opts.micromips |
833794fc | 8272 | && !mips_opts.insn32 |
e64af278 MR |
8273 | && dreg == RA |
8274 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
df58fc94 RS |
8275 | macro_build (NULL, s, "mj", sreg); |
8276 | else | |
8277 | macro_build (NULL, s, JALR_FMT, dreg, sreg); | |
0a44bf69 | 8278 | if (mips_pic == SVR4_PIC && !HAVE_NEWABI) |
252b5132 | 8279 | { |
6478892d TS |
8280 | if (mips_cprestore_offset < 0) |
8281 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
8282 | else | |
8283 | { | |
90ecf173 | 8284 | if (!mips_frame_reg_valid) |
7a621144 DJ |
8285 | { |
8286 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
8287 | /* Quiet this warning. */ | |
8288 | mips_frame_reg_valid = 1; | |
8289 | } | |
90ecf173 | 8290 | if (!mips_cprestore_valid) |
7a621144 DJ |
8291 | { |
8292 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
8293 | /* Quiet this warning. */ | |
8294 | mips_cprestore_valid = 1; | |
8295 | } | |
d3fca0b5 MR |
8296 | if (mips_opts.noreorder) |
8297 | macro_build (NULL, "nop", ""); | |
6478892d | 8298 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 8299 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 8300 | mips_gp_register, |
256ab948 TS |
8301 | mips_frame_reg, |
8302 | HAVE_64BIT_ADDRESSES); | |
6478892d | 8303 | } |
252b5132 RH |
8304 | } |
8305 | } | |
252b5132 | 8306 | |
8fc2e39e | 8307 | break; |
252b5132 | 8308 | |
df58fc94 RS |
8309 | case M_JALS_A: |
8310 | gas_assert (mips_opts.micromips); | |
833794fc MR |
8311 | if (mips_opts.insn32) |
8312 | { | |
8313 | as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str); | |
8314 | break; | |
8315 | } | |
df58fc94 RS |
8316 | jals = 1; |
8317 | /* Fall through. */ | |
252b5132 RH |
8318 | case M_JAL_A: |
8319 | if (mips_pic == NO_PIC) | |
df58fc94 | 8320 | macro_build (&offset_expr, jals ? "jals" : "jal", "a"); |
252b5132 RH |
8321 | else if (mips_pic == SVR4_PIC) |
8322 | { | |
8323 | /* If this is a reference to an external symbol, and we are | |
8324 | using a small GOT, we want | |
8325 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
8326 | nop | |
f9419b05 | 8327 | jalr $ra,$25 |
252b5132 RH |
8328 | nop |
8329 | lw $gp,cprestore($sp) | |
8330 | The cprestore value is set using the .cprestore | |
8331 | pseudo-op. If we are using a big GOT, we want | |
8332 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
8333 | addu $25,$25,$gp | |
8334 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
8335 | nop | |
f9419b05 | 8336 | jalr $ra,$25 |
252b5132 RH |
8337 | nop |
8338 | lw $gp,cprestore($sp) | |
8339 | If the symbol is not external, we want | |
8340 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
8341 | nop | |
8342 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 8343 | jalr $ra,$25 |
252b5132 | 8344 | nop |
438c16b8 | 8345 | lw $gp,cprestore($sp) |
f5040a92 AO |
8346 | |
8347 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
8348 | sequences above, minus nops, unless the symbol is local, | |
8349 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
8350 | GOT_DISP. */ | |
438c16b8 | 8351 | if (HAVE_NEWABI) |
252b5132 | 8352 | { |
90ecf173 | 8353 | if (!mips_big_got) |
f5040a92 | 8354 | { |
4d7206a2 | 8355 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
8356 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
8357 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 8358 | mips_gp_register); |
4d7206a2 | 8359 | relax_switch (); |
67c0d1eb RS |
8360 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
8361 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
8362 | mips_gp_register); |
8363 | relax_end (); | |
f5040a92 AO |
8364 | } |
8365 | else | |
8366 | { | |
4d7206a2 | 8367 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 8368 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
8369 | BFD_RELOC_MIPS_CALL_HI16); |
8370 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
8371 | PIC_CALL_REG, mips_gp_register); | |
8372 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
8373 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
8374 | PIC_CALL_REG); | |
4d7206a2 | 8375 | relax_switch (); |
67c0d1eb RS |
8376 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
8377 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
8378 | mips_gp_register); | |
8379 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
8380 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 8381 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 8382 | relax_end (); |
f5040a92 | 8383 | } |
684022ea | 8384 | |
df58fc94 | 8385 | macro_build_jalr (&offset_expr, 0); |
252b5132 RH |
8386 | } |
8387 | else | |
8388 | { | |
4d7206a2 | 8389 | relax_start (offset_expr.X_add_symbol); |
90ecf173 | 8390 | if (!mips_big_got) |
438c16b8 | 8391 | { |
67c0d1eb RS |
8392 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
8393 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 8394 | mips_gp_register); |
269137b2 | 8395 | load_delay_nop (); |
4d7206a2 | 8396 | relax_switch (); |
438c16b8 | 8397 | } |
252b5132 | 8398 | else |
252b5132 | 8399 | { |
67c0d1eb RS |
8400 | int gpdelay; |
8401 | ||
8402 | gpdelay = reg_needs_delay (mips_gp_register); | |
df58fc94 | 8403 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
8404 | BFD_RELOC_MIPS_CALL_HI16); |
8405 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
8406 | PIC_CALL_REG, mips_gp_register); | |
8407 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
8408 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
8409 | PIC_CALL_REG); | |
269137b2 | 8410 | load_delay_nop (); |
4d7206a2 | 8411 | relax_switch (); |
67c0d1eb RS |
8412 | if (gpdelay) |
8413 | macro_build (NULL, "nop", ""); | |
252b5132 | 8414 | } |
67c0d1eb RS |
8415 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
8416 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 8417 | mips_gp_register); |
269137b2 | 8418 | load_delay_nop (); |
67c0d1eb RS |
8419 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
8420 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 8421 | relax_end (); |
df58fc94 | 8422 | macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0); |
438c16b8 | 8423 | |
6478892d TS |
8424 | if (mips_cprestore_offset < 0) |
8425 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
8426 | else | |
8427 | { | |
90ecf173 | 8428 | if (!mips_frame_reg_valid) |
7a621144 DJ |
8429 | { |
8430 | as_warn (_("No .frame pseudo-op used in PIC code")); | |
8431 | /* Quiet this warning. */ | |
8432 | mips_frame_reg_valid = 1; | |
8433 | } | |
90ecf173 | 8434 | if (!mips_cprestore_valid) |
7a621144 DJ |
8435 | { |
8436 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
8437 | /* Quiet this warning. */ | |
8438 | mips_cprestore_valid = 1; | |
8439 | } | |
6478892d | 8440 | if (mips_opts.noreorder) |
67c0d1eb | 8441 | macro_build (NULL, "nop", ""); |
6478892d | 8442 | expr1.X_add_number = mips_cprestore_offset; |
67c0d1eb | 8443 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 8444 | mips_gp_register, |
256ab948 TS |
8445 | mips_frame_reg, |
8446 | HAVE_64BIT_ADDRESSES); | |
6478892d | 8447 | } |
252b5132 RH |
8448 | } |
8449 | } | |
0a44bf69 RS |
8450 | else if (mips_pic == VXWORKS_PIC) |
8451 | as_bad (_("Non-PIC jump used in PIC library")); | |
252b5132 RH |
8452 | else |
8453 | abort (); | |
8454 | ||
8fc2e39e | 8455 | break; |
252b5132 | 8456 | |
7f3c4072 | 8457 | case M_LBUE_AB: |
7f3c4072 CM |
8458 | s = "lbue"; |
8459 | fmt = "t,+j(b)"; | |
8460 | offbits = 9; | |
8461 | goto ld_st; | |
8462 | case M_LHUE_AB: | |
7f3c4072 CM |
8463 | s = "lhue"; |
8464 | fmt = "t,+j(b)"; | |
8465 | offbits = 9; | |
8466 | goto ld_st; | |
8467 | case M_LBE_AB: | |
7f3c4072 CM |
8468 | s = "lbe"; |
8469 | fmt = "t,+j(b)"; | |
8470 | offbits = 9; | |
8471 | goto ld_st; | |
8472 | case M_LHE_AB: | |
7f3c4072 CM |
8473 | s = "lhe"; |
8474 | fmt = "t,+j(b)"; | |
8475 | offbits = 9; | |
8476 | goto ld_st; | |
8477 | case M_LLE_AB: | |
7f3c4072 CM |
8478 | s = "lle"; |
8479 | fmt = "t,+j(b)"; | |
8480 | offbits = 9; | |
8481 | goto ld_st; | |
8482 | case M_LWE_AB: | |
7f3c4072 CM |
8483 | s = "lwe"; |
8484 | fmt = "t,+j(b)"; | |
8485 | offbits = 9; | |
8486 | goto ld_st; | |
8487 | case M_LWLE_AB: | |
7f3c4072 CM |
8488 | s = "lwle"; |
8489 | fmt = "t,+j(b)"; | |
8490 | offbits = 9; | |
8491 | goto ld_st; | |
8492 | case M_LWRE_AB: | |
7f3c4072 CM |
8493 | s = "lwre"; |
8494 | fmt = "t,+j(b)"; | |
8495 | offbits = 9; | |
8496 | goto ld_st; | |
8497 | case M_SBE_AB: | |
7f3c4072 CM |
8498 | s = "sbe"; |
8499 | fmt = "t,+j(b)"; | |
8500 | offbits = 9; | |
8501 | goto ld_st; | |
8502 | case M_SCE_AB: | |
7f3c4072 CM |
8503 | s = "sce"; |
8504 | fmt = "t,+j(b)"; | |
8505 | offbits = 9; | |
8506 | goto ld_st; | |
8507 | case M_SHE_AB: | |
7f3c4072 CM |
8508 | s = "she"; |
8509 | fmt = "t,+j(b)"; | |
8510 | offbits = 9; | |
8511 | goto ld_st; | |
8512 | case M_SWE_AB: | |
7f3c4072 CM |
8513 | s = "swe"; |
8514 | fmt = "t,+j(b)"; | |
8515 | offbits = 9; | |
8516 | goto ld_st; | |
8517 | case M_SWLE_AB: | |
7f3c4072 CM |
8518 | s = "swle"; |
8519 | fmt = "t,+j(b)"; | |
8520 | offbits = 9; | |
8521 | goto ld_st; | |
8522 | case M_SWRE_AB: | |
7f3c4072 CM |
8523 | s = "swre"; |
8524 | fmt = "t,+j(b)"; | |
8525 | offbits = 9; | |
8526 | goto ld_st; | |
dec0624d | 8527 | case M_ACLR_AB: |
dec0624d MR |
8528 | s = "aclr"; |
8529 | treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip); | |
8530 | fmt = "\\,~(b)"; | |
7f3c4072 | 8531 | offbits = 12; |
dec0624d MR |
8532 | goto ld_st; |
8533 | case M_ASET_AB: | |
dec0624d MR |
8534 | s = "aset"; |
8535 | treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip); | |
8536 | fmt = "\\,~(b)"; | |
7f3c4072 | 8537 | offbits = 12; |
dec0624d | 8538 | goto ld_st; |
252b5132 RH |
8539 | case M_LB_AB: |
8540 | s = "lb"; | |
df58fc94 | 8541 | fmt = "t,o(b)"; |
252b5132 RH |
8542 | goto ld; |
8543 | case M_LBU_AB: | |
8544 | s = "lbu"; | |
df58fc94 | 8545 | fmt = "t,o(b)"; |
252b5132 RH |
8546 | goto ld; |
8547 | case M_LH_AB: | |
8548 | s = "lh"; | |
df58fc94 | 8549 | fmt = "t,o(b)"; |
252b5132 RH |
8550 | goto ld; |
8551 | case M_LHU_AB: | |
8552 | s = "lhu"; | |
df58fc94 | 8553 | fmt = "t,o(b)"; |
252b5132 RH |
8554 | goto ld; |
8555 | case M_LW_AB: | |
8556 | s = "lw"; | |
df58fc94 | 8557 | fmt = "t,o(b)"; |
252b5132 RH |
8558 | goto ld; |
8559 | case M_LWC0_AB: | |
df58fc94 | 8560 | gas_assert (!mips_opts.micromips); |
252b5132 | 8561 | s = "lwc0"; |
df58fc94 | 8562 | fmt = "E,o(b)"; |
bdaaa2e1 | 8563 | /* Itbl support may require additional care here. */ |
252b5132 | 8564 | coproc = 1; |
df58fc94 | 8565 | goto ld_st; |
252b5132 RH |
8566 | case M_LWC1_AB: |
8567 | s = "lwc1"; | |
df58fc94 | 8568 | fmt = "T,o(b)"; |
bdaaa2e1 | 8569 | /* Itbl support may require additional care here. */ |
252b5132 | 8570 | coproc = 1; |
df58fc94 | 8571 | goto ld_st; |
252b5132 RH |
8572 | case M_LWC2_AB: |
8573 | s = "lwc2"; | |
df58fc94 | 8574 | fmt = COP12_FMT; |
7f3c4072 | 8575 | offbits = (mips_opts.micromips ? 12 : 16); |
bdaaa2e1 | 8576 | /* Itbl support may require additional care here. */ |
252b5132 | 8577 | coproc = 1; |
df58fc94 | 8578 | goto ld_st; |
252b5132 | 8579 | case M_LWC3_AB: |
df58fc94 | 8580 | gas_assert (!mips_opts.micromips); |
252b5132 | 8581 | s = "lwc3"; |
df58fc94 | 8582 | fmt = "E,o(b)"; |
bdaaa2e1 | 8583 | /* Itbl support may require additional care here. */ |
252b5132 | 8584 | coproc = 1; |
df58fc94 | 8585 | goto ld_st; |
252b5132 RH |
8586 | case M_LWL_AB: |
8587 | s = "lwl"; | |
df58fc94 | 8588 | fmt = MEM12_FMT; |
7f3c4072 | 8589 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 8590 | goto ld_st; |
252b5132 RH |
8591 | case M_LWR_AB: |
8592 | s = "lwr"; | |
df58fc94 | 8593 | fmt = MEM12_FMT; |
7f3c4072 | 8594 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 8595 | goto ld_st; |
252b5132 | 8596 | case M_LDC1_AB: |
252b5132 | 8597 | s = "ldc1"; |
df58fc94 | 8598 | fmt = "T,o(b)"; |
bdaaa2e1 | 8599 | /* Itbl support may require additional care here. */ |
252b5132 | 8600 | coproc = 1; |
df58fc94 | 8601 | goto ld_st; |
252b5132 RH |
8602 | case M_LDC2_AB: |
8603 | s = "ldc2"; | |
df58fc94 | 8604 | fmt = COP12_FMT; |
7f3c4072 | 8605 | offbits = (mips_opts.micromips ? 12 : 16); |
bdaaa2e1 | 8606 | /* Itbl support may require additional care here. */ |
252b5132 | 8607 | coproc = 1; |
df58fc94 | 8608 | goto ld_st; |
c77c0862 | 8609 | case M_LQC2_AB: |
c77c0862 RS |
8610 | s = "lqc2"; |
8611 | fmt = "E,o(b)"; | |
8612 | /* Itbl support may require additional care here. */ | |
8613 | coproc = 1; | |
8614 | goto ld_st; | |
252b5132 RH |
8615 | case M_LDC3_AB: |
8616 | s = "ldc3"; | |
df58fc94 | 8617 | fmt = "E,o(b)"; |
bdaaa2e1 | 8618 | /* Itbl support may require additional care here. */ |
252b5132 | 8619 | coproc = 1; |
df58fc94 | 8620 | goto ld_st; |
252b5132 RH |
8621 | case M_LDL_AB: |
8622 | s = "ldl"; | |
df58fc94 | 8623 | fmt = MEM12_FMT; |
7f3c4072 | 8624 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 8625 | goto ld_st; |
252b5132 RH |
8626 | case M_LDR_AB: |
8627 | s = "ldr"; | |
df58fc94 | 8628 | fmt = MEM12_FMT; |
7f3c4072 | 8629 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 8630 | goto ld_st; |
252b5132 RH |
8631 | case M_LL_AB: |
8632 | s = "ll"; | |
df58fc94 | 8633 | fmt = MEM12_FMT; |
7f3c4072 | 8634 | offbits = (mips_opts.micromips ? 12 : 16); |
252b5132 RH |
8635 | goto ld; |
8636 | case M_LLD_AB: | |
8637 | s = "lld"; | |
df58fc94 | 8638 | fmt = MEM12_FMT; |
7f3c4072 | 8639 | offbits = (mips_opts.micromips ? 12 : 16); |
252b5132 RH |
8640 | goto ld; |
8641 | case M_LWU_AB: | |
8642 | s = "lwu"; | |
df58fc94 | 8643 | fmt = MEM12_FMT; |
7f3c4072 | 8644 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
8645 | goto ld; |
8646 | case M_LWP_AB: | |
df58fc94 RS |
8647 | gas_assert (mips_opts.micromips); |
8648 | s = "lwp"; | |
8649 | fmt = "t,~(b)"; | |
7f3c4072 | 8650 | offbits = 12; |
df58fc94 RS |
8651 | lp = 1; |
8652 | goto ld; | |
8653 | case M_LDP_AB: | |
df58fc94 RS |
8654 | gas_assert (mips_opts.micromips); |
8655 | s = "ldp"; | |
8656 | fmt = "t,~(b)"; | |
7f3c4072 | 8657 | offbits = 12; |
df58fc94 RS |
8658 | lp = 1; |
8659 | goto ld; | |
8660 | case M_LWM_AB: | |
df58fc94 RS |
8661 | gas_assert (mips_opts.micromips); |
8662 | s = "lwm"; | |
8663 | fmt = "n,~(b)"; | |
7f3c4072 | 8664 | offbits = 12; |
df58fc94 RS |
8665 | goto ld_st; |
8666 | case M_LDM_AB: | |
df58fc94 RS |
8667 | gas_assert (mips_opts.micromips); |
8668 | s = "ldm"; | |
8669 | fmt = "n,~(b)"; | |
7f3c4072 | 8670 | offbits = 12; |
df58fc94 RS |
8671 | goto ld_st; |
8672 | ||
252b5132 | 8673 | ld: |
f19ccbda MR |
8674 | /* We don't want to use $0 as tempreg. */ |
8675 | if (breg == treg + lp || treg + lp == ZERO) | |
df58fc94 | 8676 | goto ld_st; |
252b5132 | 8677 | else |
df58fc94 RS |
8678 | tempreg = treg + lp; |
8679 | goto ld_noat; | |
8680 | ||
252b5132 RH |
8681 | case M_SB_AB: |
8682 | s = "sb"; | |
df58fc94 RS |
8683 | fmt = "t,o(b)"; |
8684 | goto ld_st; | |
252b5132 RH |
8685 | case M_SH_AB: |
8686 | s = "sh"; | |
df58fc94 RS |
8687 | fmt = "t,o(b)"; |
8688 | goto ld_st; | |
252b5132 RH |
8689 | case M_SW_AB: |
8690 | s = "sw"; | |
df58fc94 RS |
8691 | fmt = "t,o(b)"; |
8692 | goto ld_st; | |
252b5132 | 8693 | case M_SWC0_AB: |
df58fc94 | 8694 | gas_assert (!mips_opts.micromips); |
252b5132 | 8695 | s = "swc0"; |
df58fc94 | 8696 | fmt = "E,o(b)"; |
bdaaa2e1 | 8697 | /* Itbl support may require additional care here. */ |
252b5132 | 8698 | coproc = 1; |
df58fc94 | 8699 | goto ld_st; |
252b5132 RH |
8700 | case M_SWC1_AB: |
8701 | s = "swc1"; | |
df58fc94 | 8702 | fmt = "T,o(b)"; |
bdaaa2e1 | 8703 | /* Itbl support may require additional care here. */ |
252b5132 | 8704 | coproc = 1; |
df58fc94 | 8705 | goto ld_st; |
252b5132 RH |
8706 | case M_SWC2_AB: |
8707 | s = "swc2"; | |
df58fc94 | 8708 | fmt = COP12_FMT; |
7f3c4072 | 8709 | offbits = (mips_opts.micromips ? 12 : 16); |
bdaaa2e1 | 8710 | /* Itbl support may require additional care here. */ |
252b5132 | 8711 | coproc = 1; |
df58fc94 | 8712 | goto ld_st; |
252b5132 | 8713 | case M_SWC3_AB: |
df58fc94 | 8714 | gas_assert (!mips_opts.micromips); |
252b5132 | 8715 | s = "swc3"; |
df58fc94 | 8716 | fmt = "E,o(b)"; |
bdaaa2e1 | 8717 | /* Itbl support may require additional care here. */ |
252b5132 | 8718 | coproc = 1; |
df58fc94 | 8719 | goto ld_st; |
252b5132 RH |
8720 | case M_SWL_AB: |
8721 | s = "swl"; | |
df58fc94 | 8722 | fmt = MEM12_FMT; |
7f3c4072 | 8723 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 8724 | goto ld_st; |
252b5132 RH |
8725 | case M_SWR_AB: |
8726 | s = "swr"; | |
df58fc94 | 8727 | fmt = MEM12_FMT; |
7f3c4072 | 8728 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 8729 | goto ld_st; |
252b5132 RH |
8730 | case M_SC_AB: |
8731 | s = "sc"; | |
df58fc94 | 8732 | fmt = MEM12_FMT; |
7f3c4072 | 8733 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 8734 | goto ld_st; |
252b5132 RH |
8735 | case M_SCD_AB: |
8736 | s = "scd"; | |
df58fc94 | 8737 | fmt = MEM12_FMT; |
7f3c4072 | 8738 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 8739 | goto ld_st; |
d43b4baf TS |
8740 | case M_CACHE_AB: |
8741 | s = "cache"; | |
df58fc94 | 8742 | fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)"; |
7f3c4072 CM |
8743 | offbits = (mips_opts.micromips ? 12 : 16); |
8744 | goto ld_st; | |
8745 | case M_CACHEE_AB: | |
7f3c4072 CM |
8746 | s = "cachee"; |
8747 | fmt = "k,+j(b)"; | |
8748 | offbits = 9; | |
df58fc94 | 8749 | goto ld_st; |
3eebd5eb MR |
8750 | case M_PREF_AB: |
8751 | s = "pref"; | |
df58fc94 | 8752 | fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)"; |
7f3c4072 CM |
8753 | offbits = (mips_opts.micromips ? 12 : 16); |
8754 | goto ld_st; | |
8755 | case M_PREFE_AB: | |
7f3c4072 CM |
8756 | s = "prefe"; |
8757 | fmt = "k,+j(b)"; | |
8758 | offbits = 9; | |
df58fc94 | 8759 | goto ld_st; |
252b5132 | 8760 | case M_SDC1_AB: |
252b5132 | 8761 | s = "sdc1"; |
df58fc94 | 8762 | fmt = "T,o(b)"; |
252b5132 | 8763 | coproc = 1; |
bdaaa2e1 | 8764 | /* Itbl support may require additional care here. */ |
df58fc94 | 8765 | goto ld_st; |
252b5132 RH |
8766 | case M_SDC2_AB: |
8767 | s = "sdc2"; | |
df58fc94 | 8768 | fmt = COP12_FMT; |
7f3c4072 | 8769 | offbits = (mips_opts.micromips ? 12 : 16); |
c77c0862 RS |
8770 | /* Itbl support may require additional care here. */ |
8771 | coproc = 1; | |
8772 | goto ld_st; | |
8773 | case M_SQC2_AB: | |
c77c0862 RS |
8774 | s = "sqc2"; |
8775 | fmt = "E,o(b)"; | |
bdaaa2e1 | 8776 | /* Itbl support may require additional care here. */ |
252b5132 | 8777 | coproc = 1; |
df58fc94 | 8778 | goto ld_st; |
252b5132 | 8779 | case M_SDC3_AB: |
df58fc94 | 8780 | gas_assert (!mips_opts.micromips); |
252b5132 | 8781 | s = "sdc3"; |
df58fc94 | 8782 | fmt = "E,o(b)"; |
bdaaa2e1 | 8783 | /* Itbl support may require additional care here. */ |
252b5132 | 8784 | coproc = 1; |
df58fc94 | 8785 | goto ld_st; |
252b5132 RH |
8786 | case M_SDL_AB: |
8787 | s = "sdl"; | |
df58fc94 | 8788 | fmt = MEM12_FMT; |
7f3c4072 | 8789 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 8790 | goto ld_st; |
252b5132 RH |
8791 | case M_SDR_AB: |
8792 | s = "sdr"; | |
df58fc94 | 8793 | fmt = MEM12_FMT; |
7f3c4072 | 8794 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
8795 | goto ld_st; |
8796 | case M_SWP_AB: | |
df58fc94 RS |
8797 | gas_assert (mips_opts.micromips); |
8798 | s = "swp"; | |
8799 | fmt = "t,~(b)"; | |
7f3c4072 | 8800 | offbits = 12; |
df58fc94 RS |
8801 | goto ld_st; |
8802 | case M_SDP_AB: | |
df58fc94 RS |
8803 | gas_assert (mips_opts.micromips); |
8804 | s = "sdp"; | |
8805 | fmt = "t,~(b)"; | |
7f3c4072 | 8806 | offbits = 12; |
df58fc94 RS |
8807 | goto ld_st; |
8808 | case M_SWM_AB: | |
df58fc94 RS |
8809 | gas_assert (mips_opts.micromips); |
8810 | s = "swm"; | |
8811 | fmt = "n,~(b)"; | |
7f3c4072 | 8812 | offbits = 12; |
df58fc94 RS |
8813 | goto ld_st; |
8814 | case M_SDM_AB: | |
df58fc94 RS |
8815 | gas_assert (mips_opts.micromips); |
8816 | s = "sdm"; | |
8817 | fmt = "n,~(b)"; | |
7f3c4072 | 8818 | offbits = 12; |
df58fc94 RS |
8819 | |
8820 | ld_st: | |
8fc2e39e | 8821 | tempreg = AT; |
df58fc94 | 8822 | ld_noat: |
f2ae14a1 RS |
8823 | if (small_offset_p (0, align, 16)) |
8824 | { | |
8825 | /* The first case exists for M_LD_AB and M_SD_AB, which are | |
8826 | macros for o32 but which should act like normal instructions | |
8827 | otherwise. */ | |
8828 | if (offbits == 16) | |
8829 | macro_build (&offset_expr, s, fmt, treg, -1, offset_reloc[0], | |
8830 | offset_reloc[1], offset_reloc[2], breg); | |
8831 | else if (small_offset_p (0, align, offbits)) | |
8832 | { | |
8833 | if (offbits == 0) | |
8834 | macro_build (NULL, s, fmt, treg, breg); | |
8835 | else | |
8836 | macro_build (NULL, s, fmt, treg, | |
8837 | (unsigned long) offset_expr.X_add_number, breg); | |
8838 | } | |
8839 | else | |
8840 | { | |
8841 | if (tempreg == AT) | |
8842 | used_at = 1; | |
8843 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
8844 | tempreg, breg, -1, offset_reloc[0], | |
8845 | offset_reloc[1], offset_reloc[2]); | |
8846 | if (offbits == 0) | |
8847 | macro_build (NULL, s, fmt, treg, tempreg); | |
8848 | else | |
8849 | macro_build (NULL, s, fmt, treg, 0L, tempreg); | |
8850 | } | |
8851 | break; | |
8852 | } | |
8853 | ||
8854 | if (tempreg == AT) | |
8855 | used_at = 1; | |
8856 | ||
252b5132 RH |
8857 | if (offset_expr.X_op != O_constant |
8858 | && offset_expr.X_op != O_symbol) | |
8859 | { | |
f71d0d44 | 8860 | as_bad (_("Expression too complex")); |
252b5132 RH |
8861 | offset_expr.X_op = O_constant; |
8862 | } | |
8863 | ||
2051e8c4 MR |
8864 | if (HAVE_32BIT_ADDRESSES |
8865 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
8866 | { |
8867 | char value [32]; | |
8868 | ||
8869 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 8870 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 8871 | } |
2051e8c4 | 8872 | |
252b5132 RH |
8873 | /* A constant expression in PIC code can be handled just as it |
8874 | is in non PIC code. */ | |
aed1a261 RS |
8875 | if (offset_expr.X_op == O_constant) |
8876 | { | |
f2ae14a1 RS |
8877 | expr1.X_add_number = offset_high_part (offset_expr.X_add_number, |
8878 | offbits == 0 ? 16 : offbits); | |
8879 | offset_expr.X_add_number -= expr1.X_add_number; | |
df58fc94 | 8880 | |
f2ae14a1 RS |
8881 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); |
8882 | if (breg != 0) | |
8883 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
8884 | tempreg, tempreg, breg); | |
7f3c4072 | 8885 | if (offbits == 0) |
dd6a37e7 | 8886 | { |
f2ae14a1 | 8887 | if (offset_expr.X_add_number != 0) |
dd6a37e7 | 8888 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
f2ae14a1 | 8889 | "t,r,j", tempreg, tempreg, BFD_RELOC_LO16); |
dd6a37e7 AP |
8890 | macro_build (NULL, s, fmt, treg, tempreg); |
8891 | } | |
7f3c4072 | 8892 | else if (offbits == 16) |
f2ae14a1 | 8893 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
df58fc94 | 8894 | else |
f2ae14a1 RS |
8895 | macro_build (NULL, s, fmt, treg, |
8896 | (unsigned long) offset_expr.X_add_number, tempreg); | |
df58fc94 | 8897 | } |
7f3c4072 | 8898 | else if (offbits != 16) |
df58fc94 | 8899 | { |
7f3c4072 CM |
8900 | /* The offset field is too narrow to be used for a low-part |
8901 | relocation, so load the whole address into the auxillary | |
f2ae14a1 RS |
8902 | register. */ |
8903 | load_address (tempreg, &offset_expr, &used_at); | |
8904 | if (breg != 0) | |
8905 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
8906 | tempreg, tempreg, breg); | |
7f3c4072 | 8907 | if (offbits == 0) |
dd6a37e7 AP |
8908 | macro_build (NULL, s, fmt, treg, tempreg); |
8909 | else | |
f2ae14a1 | 8910 | macro_build (NULL, s, fmt, treg, 0L, tempreg); |
aed1a261 RS |
8911 | } |
8912 | else if (mips_pic == NO_PIC) | |
252b5132 RH |
8913 | { |
8914 | /* If this is a reference to a GP relative symbol, and there | |
8915 | is no base register, we want | |
cdf6fd85 | 8916 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
8917 | Otherwise, if there is no base register, we want |
8918 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8919 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8920 | If we have a constant, we need two instructions anyhow, | |
8921 | so we always use the latter form. | |
8922 | ||
8923 | If we have a base register, and this is a reference to a | |
8924 | GP relative symbol, we want | |
8925 | addu $tempreg,$breg,$gp | |
cdf6fd85 | 8926 | <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
8927 | Otherwise we want |
8928 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8929 | addu $tempreg,$tempreg,$breg | |
8930 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
d6bc6245 | 8931 | With a constant we always use the latter case. |
76b3015f | 8932 | |
d6bc6245 TS |
8933 | With 64bit address space and no base register and $at usable, |
8934 | we want | |
8935 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8936 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
8937 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8938 | dsll32 $tempreg,0 | |
8939 | daddu $tempreg,$at | |
8940 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8941 | If we have a base register, we want | |
8942 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8943 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
8944 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8945 | daddu $at,$breg | |
8946 | dsll32 $tempreg,0 | |
8947 | daddu $tempreg,$at | |
8948 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8949 | ||
8950 | Without $at we can't generate the optimal path for superscalar | |
8951 | processors here since this would require two temporary registers. | |
8952 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8953 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8954 | dsll $tempreg,16 | |
8955 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8956 | dsll $tempreg,16 | |
8957 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
8958 | If we have a base register, we want | |
8959 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
8960 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
8961 | dsll $tempreg,16 | |
8962 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
8963 | dsll $tempreg,16 | |
8964 | daddu $tempreg,$tempreg,$breg | |
8965 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
6373ee54 | 8966 | |
6caf9ef4 | 8967 | For GP relative symbols in 64bit address space we can use |
aed1a261 RS |
8968 | the same sequence as in 32bit address space. */ |
8969 | if (HAVE_64BIT_SYMBOLS) | |
d6bc6245 | 8970 | { |
aed1a261 | 8971 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 TS |
8972 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
8973 | { | |
8974 | relax_start (offset_expr.X_add_symbol); | |
8975 | if (breg == 0) | |
8976 | { | |
8977 | macro_build (&offset_expr, s, fmt, treg, | |
8978 | BFD_RELOC_GPREL16, mips_gp_register); | |
8979 | } | |
8980 | else | |
8981 | { | |
8982 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
8983 | tempreg, breg, mips_gp_register); | |
8984 | macro_build (&offset_expr, s, fmt, treg, | |
8985 | BFD_RELOC_GPREL16, tempreg); | |
8986 | } | |
8987 | relax_switch (); | |
8988 | } | |
d6bc6245 | 8989 | |
741fe287 | 8990 | if (used_at == 0 && mips_opts.at) |
d6bc6245 | 8991 | { |
df58fc94 | 8992 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb | 8993 | BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 8994 | macro_build (&offset_expr, "lui", LUI_FMT, AT, |
67c0d1eb RS |
8995 | BFD_RELOC_HI16_S); |
8996 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
8997 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 8998 | if (breg != 0) |
67c0d1eb | 8999 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
df58fc94 | 9000 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb RS |
9001 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
9002 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, | |
9003 | tempreg); | |
d6bc6245 TS |
9004 | used_at = 1; |
9005 | } | |
9006 | else | |
9007 | { | |
df58fc94 | 9008 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb RS |
9009 | BFD_RELOC_MIPS_HIGHEST); |
9010 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
9011 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 9012 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb RS |
9013 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, |
9014 | tempreg, BFD_RELOC_HI16_S); | |
df58fc94 | 9015 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
d6bc6245 | 9016 | if (breg != 0) |
67c0d1eb | 9017 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 9018 | tempreg, tempreg, breg); |
67c0d1eb | 9019 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 9020 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 9021 | } |
6caf9ef4 TS |
9022 | |
9023 | if (mips_relax.sequence) | |
9024 | relax_end (); | |
8fc2e39e | 9025 | break; |
d6bc6245 | 9026 | } |
256ab948 | 9027 | |
252b5132 RH |
9028 | if (breg == 0) |
9029 | { | |
67c0d1eb | 9030 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 9031 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 9032 | { |
4d7206a2 | 9033 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
9034 | macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, |
9035 | mips_gp_register); | |
4d7206a2 | 9036 | relax_switch (); |
252b5132 | 9037 | } |
67c0d1eb RS |
9038 | macro_build_lui (&offset_expr, tempreg); |
9039 | macro_build (&offset_expr, s, fmt, treg, | |
17a2f251 | 9040 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
9041 | if (mips_relax.sequence) |
9042 | relax_end (); | |
252b5132 RH |
9043 | } |
9044 | else | |
9045 | { | |
67c0d1eb | 9046 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 9047 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 9048 | { |
4d7206a2 | 9049 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 9050 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 9051 | tempreg, breg, mips_gp_register); |
67c0d1eb | 9052 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 9053 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 9054 | relax_switch (); |
252b5132 | 9055 | } |
67c0d1eb RS |
9056 | macro_build_lui (&offset_expr, tempreg); |
9057 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 9058 | tempreg, tempreg, breg); |
67c0d1eb | 9059 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 9060 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
9061 | if (mips_relax.sequence) |
9062 | relax_end (); | |
252b5132 RH |
9063 | } |
9064 | } | |
0a44bf69 | 9065 | else if (!mips_big_got) |
252b5132 | 9066 | { |
ed6fb7bd | 9067 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 9068 | |
252b5132 RH |
9069 | /* If this is a reference to an external symbol, we want |
9070 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9071 | nop | |
9072 | <op> $treg,0($tempreg) | |
9073 | Otherwise we want | |
9074 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9075 | nop | |
9076 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
9077 | <op> $treg,0($tempreg) | |
f5040a92 AO |
9078 | |
9079 | For NewABI, we want | |
9080 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
9081 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) | |
9082 | ||
252b5132 RH |
9083 | If there is a base register, we add it to $tempreg before |
9084 | the <op>. If there is a constant, we stick it in the | |
9085 | <op> instruction. We don't handle constants larger than | |
9086 | 16 bits, because we have no way to load the upper 16 bits | |
9087 | (actually, we could handle them for the subset of cases | |
9088 | in which we are not using $at). */ | |
9c2799c2 | 9089 | gas_assert (offset_expr.X_op == O_symbol); |
f5040a92 AO |
9090 | if (HAVE_NEWABI) |
9091 | { | |
67c0d1eb RS |
9092 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
9093 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 9094 | if (breg != 0) |
67c0d1eb | 9095 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 9096 | tempreg, tempreg, breg); |
67c0d1eb | 9097 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 9098 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
9099 | break; |
9100 | } | |
252b5132 RH |
9101 | expr1.X_add_number = offset_expr.X_add_number; |
9102 | offset_expr.X_add_number = 0; | |
9103 | if (expr1.X_add_number < -0x8000 | |
9104 | || expr1.X_add_number >= 0x8000) | |
9105 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
9106 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
9107 | lw_reloc_type, mips_gp_register); | |
269137b2 | 9108 | load_delay_nop (); |
4d7206a2 RS |
9109 | relax_start (offset_expr.X_add_symbol); |
9110 | relax_switch (); | |
67c0d1eb RS |
9111 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
9112 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 9113 | relax_end (); |
252b5132 | 9114 | if (breg != 0) |
67c0d1eb | 9115 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 9116 | tempreg, tempreg, breg); |
67c0d1eb | 9117 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 9118 | } |
0a44bf69 | 9119 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 9120 | { |
67c0d1eb | 9121 | int gpdelay; |
252b5132 RH |
9122 | |
9123 | /* If this is a reference to an external symbol, we want | |
9124 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
9125 | addu $tempreg,$tempreg,$gp | |
9126 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
9127 | <op> $treg,0($tempreg) | |
9128 | Otherwise we want | |
9129 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9130 | nop | |
9131 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
9132 | <op> $treg,0($tempreg) | |
9133 | If there is a base register, we add it to $tempreg before | |
9134 | the <op>. If there is a constant, we stick it in the | |
9135 | <op> instruction. We don't handle constants larger than | |
9136 | 16 bits, because we have no way to load the upper 16 bits | |
9137 | (actually, we could handle them for the subset of cases | |
f5040a92 | 9138 | in which we are not using $at). */ |
9c2799c2 | 9139 | gas_assert (offset_expr.X_op == O_symbol); |
252b5132 RH |
9140 | expr1.X_add_number = offset_expr.X_add_number; |
9141 | offset_expr.X_add_number = 0; | |
9142 | if (expr1.X_add_number < -0x8000 | |
9143 | || expr1.X_add_number >= 0x8000) | |
9144 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 9145 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 9146 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 9147 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 9148 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
9149 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
9150 | mips_gp_register); | |
9151 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
9152 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 9153 | relax_switch (); |
67c0d1eb RS |
9154 | if (gpdelay) |
9155 | macro_build (NULL, "nop", ""); | |
9156 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
9157 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 9158 | load_delay_nop (); |
67c0d1eb RS |
9159 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
9160 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
9161 | relax_end (); |
9162 | ||
252b5132 | 9163 | if (breg != 0) |
67c0d1eb | 9164 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 9165 | tempreg, tempreg, breg); |
67c0d1eb | 9166 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
252b5132 | 9167 | } |
0a44bf69 | 9168 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 9169 | { |
f5040a92 AO |
9170 | /* If this is a reference to an external symbol, we want |
9171 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
9172 | add $tempreg,$tempreg,$gp | |
9173 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
9174 | <op> $treg,<ofst>($tempreg) | |
9175 | Otherwise, for local symbols, we want: | |
9176 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
9177 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ | |
9c2799c2 | 9178 | gas_assert (offset_expr.X_op == O_symbol); |
4d7206a2 | 9179 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
9180 | offset_expr.X_add_number = 0; |
9181 | if (expr1.X_add_number < -0x8000 | |
9182 | || expr1.X_add_number >= 0x8000) | |
9183 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 9184 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 9185 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 9186 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
9187 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
9188 | mips_gp_register); | |
9189 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
9190 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 9191 | if (breg != 0) |
67c0d1eb | 9192 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 9193 | tempreg, tempreg, breg); |
67c0d1eb | 9194 | macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); |
684022ea | 9195 | |
4d7206a2 | 9196 | relax_switch (); |
f5040a92 | 9197 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
9198 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
9199 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 9200 | if (breg != 0) |
67c0d1eb | 9201 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 9202 | tempreg, tempreg, breg); |
67c0d1eb | 9203 | macro_build (&offset_expr, s, fmt, treg, |
17a2f251 | 9204 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 9205 | relax_end (); |
f5040a92 | 9206 | } |
252b5132 RH |
9207 | else |
9208 | abort (); | |
9209 | ||
252b5132 RH |
9210 | break; |
9211 | ||
833794fc MR |
9212 | case M_JRADDIUSP: |
9213 | gas_assert (mips_opts.micromips); | |
9214 | gas_assert (mips_opts.insn32); | |
9215 | start_noreorder (); | |
9216 | macro_build (NULL, "jr", "s", RA); | |
9217 | expr1.X_add_number = EXTRACT_OPERAND (1, IMMP, *ip) << 2; | |
9218 | macro_build (&expr1, "addiu", "t,r,j", SP, SP, BFD_RELOC_LO16); | |
9219 | end_noreorder (); | |
9220 | break; | |
9221 | ||
9222 | case M_JRC: | |
9223 | gas_assert (mips_opts.micromips); | |
9224 | gas_assert (mips_opts.insn32); | |
9225 | macro_build (NULL, "jr", "s", sreg); | |
9226 | if (mips_opts.noreorder) | |
9227 | macro_build (NULL, "nop", ""); | |
9228 | break; | |
9229 | ||
252b5132 RH |
9230 | case M_LI: |
9231 | case M_LI_S: | |
67c0d1eb | 9232 | load_register (treg, &imm_expr, 0); |
8fc2e39e | 9233 | break; |
252b5132 RH |
9234 | |
9235 | case M_DLI: | |
67c0d1eb | 9236 | load_register (treg, &imm_expr, 1); |
8fc2e39e | 9237 | break; |
252b5132 RH |
9238 | |
9239 | case M_LI_SS: | |
9240 | if (imm_expr.X_op == O_constant) | |
9241 | { | |
8fc2e39e | 9242 | used_at = 1; |
67c0d1eb RS |
9243 | load_register (AT, &imm_expr, 0); |
9244 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
9245 | break; |
9246 | } | |
9247 | else | |
9248 | { | |
9c2799c2 | 9249 | gas_assert (offset_expr.X_op == O_symbol |
90ecf173 MR |
9250 | && strcmp (segment_name (S_GET_SEGMENT |
9251 | (offset_expr.X_add_symbol)), | |
9252 | ".lit4") == 0 | |
9253 | && offset_expr.X_add_number == 0); | |
67c0d1eb | 9254 | macro_build (&offset_expr, "lwc1", "T,o(b)", treg, |
17a2f251 | 9255 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 9256 | break; |
252b5132 RH |
9257 | } |
9258 | ||
9259 | case M_LI_D: | |
ca4e0257 RS |
9260 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
9261 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
9262 | order 32 bits of the value and the low order 32 bits are either | |
9263 | zero or in OFFSET_EXPR. */ | |
252b5132 RH |
9264 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
9265 | { | |
ca4e0257 | 9266 | if (HAVE_64BIT_GPRS) |
67c0d1eb | 9267 | load_register (treg, &imm_expr, 1); |
252b5132 RH |
9268 | else |
9269 | { | |
9270 | int hreg, lreg; | |
9271 | ||
9272 | if (target_big_endian) | |
9273 | { | |
9274 | hreg = treg; | |
9275 | lreg = treg + 1; | |
9276 | } | |
9277 | else | |
9278 | { | |
9279 | hreg = treg + 1; | |
9280 | lreg = treg; | |
9281 | } | |
9282 | ||
9283 | if (hreg <= 31) | |
67c0d1eb | 9284 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
9285 | if (lreg <= 31) |
9286 | { | |
9287 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 9288 | move_register (lreg, 0); |
252b5132 RH |
9289 | else |
9290 | { | |
9c2799c2 | 9291 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb | 9292 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
9293 | } |
9294 | } | |
9295 | } | |
8fc2e39e | 9296 | break; |
252b5132 RH |
9297 | } |
9298 | ||
9299 | /* We know that sym is in the .rdata section. First we get the | |
9300 | upper 16 bits of the address. */ | |
9301 | if (mips_pic == NO_PIC) | |
9302 | { | |
67c0d1eb | 9303 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 9304 | used_at = 1; |
252b5132 | 9305 | } |
0a44bf69 | 9306 | else |
252b5132 | 9307 | { |
67c0d1eb RS |
9308 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
9309 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 9310 | used_at = 1; |
252b5132 | 9311 | } |
bdaaa2e1 | 9312 | |
252b5132 | 9313 | /* Now we load the register(s). */ |
ca4e0257 | 9314 | if (HAVE_64BIT_GPRS) |
8fc2e39e TS |
9315 | { |
9316 | used_at = 1; | |
9317 | macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
9318 | } | |
252b5132 RH |
9319 | else |
9320 | { | |
8fc2e39e | 9321 | used_at = 1; |
67c0d1eb | 9322 | macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT); |
f9419b05 | 9323 | if (treg != RA) |
252b5132 RH |
9324 | { |
9325 | /* FIXME: How in the world do we deal with the possible | |
9326 | overflow here? */ | |
9327 | offset_expr.X_add_number += 4; | |
67c0d1eb | 9328 | macro_build (&offset_expr, "lw", "t,o(b)", |
17a2f251 | 9329 | treg + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
9330 | } |
9331 | } | |
252b5132 RH |
9332 | break; |
9333 | ||
9334 | case M_LI_DD: | |
ca4e0257 RS |
9335 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
9336 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
9337 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
9338 | the value and the low order 32 bits are either zero or in | |
9339 | OFFSET_EXPR. */ | |
252b5132 RH |
9340 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
9341 | { | |
8fc2e39e | 9342 | used_at = 1; |
67c0d1eb | 9343 | load_register (AT, &imm_expr, HAVE_64BIT_FPRS); |
ca4e0257 RS |
9344 | if (HAVE_64BIT_FPRS) |
9345 | { | |
9c2799c2 | 9346 | gas_assert (HAVE_64BIT_GPRS); |
67c0d1eb | 9347 | macro_build (NULL, "dmtc1", "t,S", AT, treg); |
ca4e0257 | 9348 | } |
252b5132 RH |
9349 | else |
9350 | { | |
67c0d1eb | 9351 | macro_build (NULL, "mtc1", "t,G", AT, treg + 1); |
252b5132 | 9352 | if (offset_expr.X_op == O_absent) |
67c0d1eb | 9353 | macro_build (NULL, "mtc1", "t,G", 0, treg); |
252b5132 RH |
9354 | else |
9355 | { | |
9c2799c2 | 9356 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb RS |
9357 | load_register (AT, &offset_expr, 0); |
9358 | macro_build (NULL, "mtc1", "t,G", AT, treg); | |
252b5132 RH |
9359 | } |
9360 | } | |
9361 | break; | |
9362 | } | |
9363 | ||
9c2799c2 | 9364 | gas_assert (offset_expr.X_op == O_symbol |
90ecf173 | 9365 | && offset_expr.X_add_number == 0); |
252b5132 RH |
9366 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); |
9367 | if (strcmp (s, ".lit8") == 0) | |
f2ae14a1 RS |
9368 | { |
9369 | breg = mips_gp_register; | |
9370 | offset_reloc[0] = BFD_RELOC_MIPS_LITERAL; | |
9371 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
9372 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
9373 | } |
9374 | else | |
9375 | { | |
9c2799c2 | 9376 | gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
8fc2e39e | 9377 | used_at = 1; |
0a44bf69 | 9378 | if (mips_pic != NO_PIC) |
67c0d1eb RS |
9379 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
9380 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
9381 | else |
9382 | { | |
9383 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 9384 | macro_build_lui (&offset_expr, AT); |
252b5132 | 9385 | } |
bdaaa2e1 | 9386 | |
252b5132 | 9387 | breg = AT; |
f2ae14a1 RS |
9388 | offset_reloc[0] = BFD_RELOC_LO16; |
9389 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
9390 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
9391 | } | |
9392 | align = 8; | |
9393 | /* Fall through */ | |
c4a68bea | 9394 | |
252b5132 RH |
9395 | case M_L_DAB: |
9396 | /* | |
9397 | * The MIPS assembler seems to check for X_add_number not | |
9398 | * being double aligned and generating: | |
9399 | * lui at,%hi(foo+1) | |
9400 | * addu at,at,v1 | |
9401 | * addiu at,at,%lo(foo+1) | |
9402 | * lwc1 f2,0(at) | |
9403 | * lwc1 f3,4(at) | |
9404 | * But, the resulting address is the same after relocation so why | |
9405 | * generate the extra instruction? | |
9406 | */ | |
bdaaa2e1 | 9407 | /* Itbl support may require additional care here. */ |
252b5132 | 9408 | coproc = 1; |
df58fc94 | 9409 | fmt = "T,o(b)"; |
0aa27725 | 9410 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch)) |
252b5132 RH |
9411 | { |
9412 | s = "ldc1"; | |
df58fc94 | 9413 | goto ld_st; |
252b5132 | 9414 | } |
252b5132 | 9415 | s = "lwc1"; |
252b5132 RH |
9416 | goto ldd_std; |
9417 | ||
9418 | case M_S_DAB: | |
df58fc94 RS |
9419 | gas_assert (!mips_opts.micromips); |
9420 | /* Itbl support may require additional care here. */ | |
9421 | coproc = 1; | |
9422 | fmt = "T,o(b)"; | |
0aa27725 | 9423 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch)) |
252b5132 RH |
9424 | { |
9425 | s = "sdc1"; | |
df58fc94 | 9426 | goto ld_st; |
252b5132 | 9427 | } |
252b5132 | 9428 | s = "swc1"; |
252b5132 RH |
9429 | goto ldd_std; |
9430 | ||
e407c74b NC |
9431 | case M_LQ_AB: |
9432 | fmt = "t,o(b)"; | |
9433 | s = "lq"; | |
9434 | goto ld; | |
9435 | ||
9436 | case M_SQ_AB: | |
9437 | fmt = "t,o(b)"; | |
9438 | s = "sq"; | |
9439 | goto ld_st; | |
9440 | ||
252b5132 | 9441 | case M_LD_AB: |
df58fc94 | 9442 | fmt = "t,o(b)"; |
ca4e0257 | 9443 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
9444 | { |
9445 | s = "ld"; | |
9446 | goto ld; | |
9447 | } | |
252b5132 | 9448 | s = "lw"; |
252b5132 RH |
9449 | goto ldd_std; |
9450 | ||
9451 | case M_SD_AB: | |
df58fc94 | 9452 | fmt = "t,o(b)"; |
ca4e0257 | 9453 | if (HAVE_64BIT_GPRS) |
252b5132 RH |
9454 | { |
9455 | s = "sd"; | |
df58fc94 | 9456 | goto ld_st; |
252b5132 | 9457 | } |
252b5132 | 9458 | s = "sw"; |
252b5132 RH |
9459 | |
9460 | ldd_std: | |
f2ae14a1 RS |
9461 | /* Even on a big endian machine $fn comes before $fn+1. We have |
9462 | to adjust when loading from memory. We set coproc if we must | |
9463 | load $fn+1 first. */ | |
9464 | /* Itbl support may require additional care here. */ | |
9465 | if (!target_big_endian) | |
9466 | coproc = 0; | |
9467 | ||
9468 | if (small_offset_p (0, align, 16)) | |
9469 | { | |
9470 | ep = &offset_expr; | |
9471 | if (!small_offset_p (4, align, 16)) | |
9472 | { | |
9473 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT, breg, | |
9474 | -1, offset_reloc[0], offset_reloc[1], | |
9475 | offset_reloc[2]); | |
9476 | expr1.X_add_number = 0; | |
9477 | ep = &expr1; | |
9478 | breg = AT; | |
9479 | used_at = 1; | |
9480 | offset_reloc[0] = BFD_RELOC_LO16; | |
9481 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
9482 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
9483 | } | |
9484 | if (strcmp (s, "lw") == 0 && treg == breg) | |
9485 | { | |
9486 | ep->X_add_number += 4; | |
9487 | macro_build (ep, s, fmt, treg + 1, -1, offset_reloc[0], | |
9488 | offset_reloc[1], offset_reloc[2], breg); | |
9489 | ep->X_add_number -= 4; | |
9490 | macro_build (ep, s, fmt, treg, -1, offset_reloc[0], | |
9491 | offset_reloc[1], offset_reloc[2], breg); | |
9492 | } | |
9493 | else | |
9494 | { | |
9495 | macro_build (ep, s, fmt, coproc ? treg + 1 : treg, -1, | |
9496 | offset_reloc[0], offset_reloc[1], offset_reloc[2], | |
9497 | breg); | |
9498 | ep->X_add_number += 4; | |
9499 | macro_build (ep, s, fmt, coproc ? treg : treg + 1, -1, | |
9500 | offset_reloc[0], offset_reloc[1], offset_reloc[2], | |
9501 | breg); | |
9502 | } | |
9503 | break; | |
9504 | } | |
9505 | ||
252b5132 RH |
9506 | if (offset_expr.X_op != O_symbol |
9507 | && offset_expr.X_op != O_constant) | |
9508 | { | |
f71d0d44 | 9509 | as_bad (_("Expression too complex")); |
252b5132 RH |
9510 | offset_expr.X_op = O_constant; |
9511 | } | |
9512 | ||
2051e8c4 MR |
9513 | if (HAVE_32BIT_ADDRESSES |
9514 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
9515 | { |
9516 | char value [32]; | |
9517 | ||
9518 | sprintf_vma (value, offset_expr.X_add_number); | |
20e1fcfd | 9519 | as_bad (_("Number (0x%s) larger than 32 bits"), value); |
55e08f71 | 9520 | } |
2051e8c4 | 9521 | |
90ecf173 | 9522 | if (mips_pic == NO_PIC || offset_expr.X_op == O_constant) |
252b5132 RH |
9523 | { |
9524 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 TS |
9525 | <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) |
9526 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
9527 | If we have a base register, we use this |
9528 | addu $at,$breg,$gp | |
cdf6fd85 TS |
9529 | <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) |
9530 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
9531 | If this is not a GP relative symbol, we want |
9532 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
9533 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
9534 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
9535 | If there is a base register, we add it to $at after the | |
9536 | lui instruction. If there is a constant, we always use | |
9537 | the last case. */ | |
39a59cf8 MR |
9538 | if (offset_expr.X_op == O_symbol |
9539 | && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 9540 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 9541 | { |
4d7206a2 | 9542 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
9543 | if (breg == 0) |
9544 | { | |
c9914766 | 9545 | tempreg = mips_gp_register; |
252b5132 RH |
9546 | } |
9547 | else | |
9548 | { | |
67c0d1eb | 9549 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 9550 | AT, breg, mips_gp_register); |
252b5132 | 9551 | tempreg = AT; |
252b5132 RH |
9552 | used_at = 1; |
9553 | } | |
9554 | ||
beae10d5 | 9555 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9556 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 9557 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
9558 | offset_expr.X_add_number += 4; |
9559 | ||
9560 | /* Set mips_optimize to 2 to avoid inserting an | |
9561 | undesired nop. */ | |
9562 | hold_mips_optimize = mips_optimize; | |
9563 | mips_optimize = 2; | |
beae10d5 | 9564 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9565 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 9566 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
9567 | mips_optimize = hold_mips_optimize; |
9568 | ||
4d7206a2 | 9569 | relax_switch (); |
252b5132 | 9570 | |
0970e49e | 9571 | offset_expr.X_add_number -= 4; |
252b5132 | 9572 | } |
8fc2e39e | 9573 | used_at = 1; |
f2ae14a1 RS |
9574 | if (offset_high_part (offset_expr.X_add_number, 16) |
9575 | != offset_high_part (offset_expr.X_add_number + 4, 16)) | |
9576 | { | |
9577 | load_address (AT, &offset_expr, &used_at); | |
9578 | offset_expr.X_op = O_constant; | |
9579 | offset_expr.X_add_number = 0; | |
9580 | } | |
9581 | else | |
9582 | macro_build_lui (&offset_expr, AT); | |
252b5132 | 9583 | if (breg != 0) |
67c0d1eb | 9584 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 9585 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9586 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 9587 | BFD_RELOC_LO16, AT); |
252b5132 RH |
9588 | /* FIXME: How do we handle overflow here? */ |
9589 | offset_expr.X_add_number += 4; | |
beae10d5 | 9590 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9591 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 9592 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
9593 | if (mips_relax.sequence) |
9594 | relax_end (); | |
bdaaa2e1 | 9595 | } |
0a44bf69 | 9596 | else if (!mips_big_got) |
252b5132 | 9597 | { |
252b5132 RH |
9598 | /* If this is a reference to an external symbol, we want |
9599 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9600 | nop | |
9601 | <op> $treg,0($at) | |
9602 | <op> $treg+1,4($at) | |
9603 | Otherwise we want | |
9604 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9605 | nop | |
9606 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
9607 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
9608 | If there is a base register we add it to $at before the | |
9609 | lwc1 instructions. If there is a constant we include it | |
9610 | in the lwc1 instructions. */ | |
9611 | used_at = 1; | |
9612 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
9613 | if (expr1.X_add_number < -0x8000 |
9614 | || expr1.X_add_number >= 0x8000 - 4) | |
9615 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 9616 | load_got_offset (AT, &offset_expr); |
269137b2 | 9617 | load_delay_nop (); |
252b5132 | 9618 | if (breg != 0) |
67c0d1eb | 9619 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
9620 | |
9621 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
9622 | nop. */ | |
9623 | hold_mips_optimize = mips_optimize; | |
9624 | mips_optimize = 2; | |
4d7206a2 | 9625 | |
beae10d5 | 9626 | /* Itbl support may require additional care here. */ |
4d7206a2 | 9627 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
9628 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
9629 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9630 | expr1.X_add_number += 4; |
67c0d1eb RS |
9631 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
9632 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9633 | relax_switch (); |
67c0d1eb RS |
9634 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
9635 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9636 | offset_expr.X_add_number += 4; |
67c0d1eb RS |
9637 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
9638 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9639 | relax_end (); |
252b5132 | 9640 | |
4d7206a2 | 9641 | mips_optimize = hold_mips_optimize; |
252b5132 | 9642 | } |
0a44bf69 | 9643 | else if (mips_big_got) |
252b5132 | 9644 | { |
67c0d1eb | 9645 | int gpdelay; |
252b5132 RH |
9646 | |
9647 | /* If this is a reference to an external symbol, we want | |
9648 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
9649 | addu $at,$at,$gp | |
9650 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
9651 | nop | |
9652 | <op> $treg,0($at) | |
9653 | <op> $treg+1,4($at) | |
9654 | Otherwise we want | |
9655 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9656 | nop | |
9657 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
9658 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
9659 | If there is a base register we add it to $at before the | |
9660 | lwc1 instructions. If there is a constant we include it | |
9661 | in the lwc1 instructions. */ | |
9662 | used_at = 1; | |
9663 | expr1.X_add_number = offset_expr.X_add_number; | |
9664 | offset_expr.X_add_number = 0; | |
9665 | if (expr1.X_add_number < -0x8000 | |
9666 | || expr1.X_add_number >= 0x8000 - 4) | |
9667 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 9668 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 9669 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 9670 | macro_build (&offset_expr, "lui", LUI_FMT, |
67c0d1eb RS |
9671 | AT, BFD_RELOC_MIPS_GOT_HI16); |
9672 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 9673 | AT, AT, mips_gp_register); |
67c0d1eb | 9674 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 9675 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 9676 | load_delay_nop (); |
252b5132 | 9677 | if (breg != 0) |
67c0d1eb | 9678 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 9679 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9680 | macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, |
17a2f251 | 9681 | BFD_RELOC_LO16, AT); |
252b5132 RH |
9682 | expr1.X_add_number += 4; |
9683 | ||
9684 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
9685 | nop. */ | |
9686 | hold_mips_optimize = mips_optimize; | |
9687 | mips_optimize = 2; | |
beae10d5 | 9688 | /* Itbl support may require additional care here. */ |
67c0d1eb | 9689 | macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, |
17a2f251 | 9690 | BFD_RELOC_LO16, AT); |
252b5132 RH |
9691 | mips_optimize = hold_mips_optimize; |
9692 | expr1.X_add_number -= 4; | |
9693 | ||
4d7206a2 RS |
9694 | relax_switch (); |
9695 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
9696 | if (gpdelay) |
9697 | macro_build (NULL, "nop", ""); | |
9698 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
9699 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 9700 | load_delay_nop (); |
252b5132 | 9701 | if (breg != 0) |
67c0d1eb | 9702 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 9703 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
9704 | macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, |
9705 | BFD_RELOC_LO16, AT); | |
4d7206a2 | 9706 | offset_expr.X_add_number += 4; |
252b5132 RH |
9707 | |
9708 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
9709 | nop. */ | |
9710 | hold_mips_optimize = mips_optimize; | |
9711 | mips_optimize = 2; | |
beae10d5 | 9712 | /* Itbl support may require additional care here. */ |
67c0d1eb RS |
9713 | macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, |
9714 | BFD_RELOC_LO16, AT); | |
252b5132 | 9715 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 9716 | relax_end (); |
252b5132 | 9717 | } |
252b5132 RH |
9718 | else |
9719 | abort (); | |
9720 | ||
252b5132 | 9721 | break; |
dd6a37e7 AP |
9722 | |
9723 | case M_SAA_AB: | |
dd6a37e7 | 9724 | s = "saa"; |
7f3c4072 | 9725 | offbits = 0; |
dd6a37e7 AP |
9726 | fmt = "t,(b)"; |
9727 | goto ld_st; | |
9728 | case M_SAAD_AB: | |
dd6a37e7 | 9729 | s = "saad"; |
7f3c4072 | 9730 | offbits = 0; |
dd6a37e7 AP |
9731 | fmt = "t,(b)"; |
9732 | goto ld_st; | |
9733 | ||
252b5132 RH |
9734 | /* New code added to support COPZ instructions. |
9735 | This code builds table entries out of the macros in mip_opcodes. | |
9736 | R4000 uses interlocks to handle coproc delays. | |
9737 | Other chips (like the R3000) require nops to be inserted for delays. | |
9738 | ||
f72c8c98 | 9739 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
9740 | In order to fill delay slots for non-interlocked chips, |
9741 | we must have a way to specify delays based on the coprocessor. | |
9742 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
9743 | What are the side-effects of the cop instruction? | |
9744 | What cache support might we have and what are its effects? | |
9745 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 9746 | What registers are read/set/modified? |
252b5132 RH |
9747 | |
9748 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 9749 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
9750 | |
9751 | case M_COP0: | |
9752 | s = "c0"; | |
9753 | goto copz; | |
9754 | case M_COP1: | |
9755 | s = "c1"; | |
9756 | goto copz; | |
9757 | case M_COP2: | |
9758 | s = "c2"; | |
9759 | goto copz; | |
9760 | case M_COP3: | |
9761 | s = "c3"; | |
9762 | copz: | |
df58fc94 | 9763 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
9764 | /* For now we just do C (same as Cz). The parameter will be |
9765 | stored in insn_opcode by mips_ip. */ | |
67c0d1eb | 9766 | macro_build (NULL, s, "C", ip->insn_opcode); |
8fc2e39e | 9767 | break; |
252b5132 | 9768 | |
ea1fb5dc | 9769 | case M_MOVE: |
67c0d1eb | 9770 | move_register (dreg, sreg); |
8fc2e39e | 9771 | break; |
ea1fb5dc | 9772 | |
833794fc MR |
9773 | case M_MOVEP: |
9774 | gas_assert (mips_opts.micromips); | |
9775 | gas_assert (mips_opts.insn32); | |
e76ff5ab RS |
9776 | dreg = micromips_to_32_reg_h_map1[EXTRACT_OPERAND (1, MH, *ip)]; |
9777 | breg = micromips_to_32_reg_h_map2[EXTRACT_OPERAND (1, MH, *ip)]; | |
833794fc MR |
9778 | sreg = micromips_to_32_reg_m_map[EXTRACT_OPERAND (1, MM, *ip)]; |
9779 | treg = micromips_to_32_reg_n_map[EXTRACT_OPERAND (1, MN, *ip)]; | |
9780 | move_register (dreg, sreg); | |
9781 | move_register (breg, treg); | |
9782 | break; | |
9783 | ||
252b5132 RH |
9784 | case M_DMUL: |
9785 | dbl = 1; | |
9786 | case M_MUL: | |
e407c74b NC |
9787 | if (mips_opts.arch == CPU_R5900) |
9788 | { | |
9789 | macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", dreg, sreg, treg); | |
9790 | } | |
9791 | else | |
9792 | { | |
67c0d1eb | 9793 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg); |
df58fc94 | 9794 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
e407c74b | 9795 | } |
8fc2e39e | 9796 | break; |
252b5132 RH |
9797 | |
9798 | case M_DMUL_I: | |
9799 | dbl = 1; | |
9800 | case M_MUL_I: | |
9801 | /* The MIPS assembler some times generates shifts and adds. I'm | |
9802 | not trying to be that fancy. GCC should do this for us | |
9803 | anyway. */ | |
8fc2e39e | 9804 | used_at = 1; |
67c0d1eb RS |
9805 | load_register (AT, &imm_expr, dbl); |
9806 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT); | |
df58fc94 | 9807 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
252b5132 RH |
9808 | break; |
9809 | ||
9810 | case M_DMULO_I: | |
9811 | dbl = 1; | |
9812 | case M_MULO_I: | |
9813 | imm = 1; | |
9814 | goto do_mulo; | |
9815 | ||
9816 | case M_DMULO: | |
9817 | dbl = 1; | |
9818 | case M_MULO: | |
9819 | do_mulo: | |
7d10b47d | 9820 | start_noreorder (); |
8fc2e39e | 9821 | used_at = 1; |
252b5132 | 9822 | if (imm) |
67c0d1eb RS |
9823 | load_register (AT, &imm_expr, dbl); |
9824 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); | |
df58fc94 RS |
9825 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
9826 | macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, dreg, dreg, RA); | |
9827 | macro_build (NULL, "mfhi", MFHL_FMT, AT); | |
252b5132 | 9828 | if (mips_trap) |
df58fc94 | 9829 | macro_build (NULL, "tne", TRAP_FMT, dreg, AT, 6); |
252b5132 RH |
9830 | else |
9831 | { | |
df58fc94 RS |
9832 | if (mips_opts.micromips) |
9833 | micromips_label_expr (&label_expr); | |
9834 | else | |
9835 | label_expr.X_add_number = 8; | |
9836 | macro_build (&label_expr, "beq", "s,t,p", dreg, AT); | |
a605d2b3 | 9837 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
9838 | macro_build (NULL, "break", BRK_FMT, 6); |
9839 | if (mips_opts.micromips) | |
9840 | micromips_add_label (); | |
252b5132 | 9841 | } |
7d10b47d | 9842 | end_noreorder (); |
df58fc94 | 9843 | macro_build (NULL, "mflo", MFHL_FMT, dreg); |
252b5132 RH |
9844 | break; |
9845 | ||
9846 | case M_DMULOU_I: | |
9847 | dbl = 1; | |
9848 | case M_MULOU_I: | |
9849 | imm = 1; | |
9850 | goto do_mulou; | |
9851 | ||
9852 | case M_DMULOU: | |
9853 | dbl = 1; | |
9854 | case M_MULOU: | |
9855 | do_mulou: | |
7d10b47d | 9856 | start_noreorder (); |
8fc2e39e | 9857 | used_at = 1; |
252b5132 | 9858 | if (imm) |
67c0d1eb RS |
9859 | load_register (AT, &imm_expr, dbl); |
9860 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
17a2f251 | 9861 | sreg, imm ? AT : treg); |
df58fc94 RS |
9862 | macro_build (NULL, "mfhi", MFHL_FMT, AT); |
9863 | macro_build (NULL, "mflo", MFHL_FMT, dreg); | |
252b5132 | 9864 | if (mips_trap) |
df58fc94 | 9865 | macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6); |
252b5132 RH |
9866 | else |
9867 | { | |
df58fc94 RS |
9868 | if (mips_opts.micromips) |
9869 | micromips_label_expr (&label_expr); | |
9870 | else | |
9871 | label_expr.X_add_number = 8; | |
9872 | macro_build (&label_expr, "beq", "s,t,p", AT, ZERO); | |
a605d2b3 | 9873 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
9874 | macro_build (NULL, "break", BRK_FMT, 6); |
9875 | if (mips_opts.micromips) | |
9876 | micromips_add_label (); | |
252b5132 | 9877 | } |
7d10b47d | 9878 | end_noreorder (); |
252b5132 RH |
9879 | break; |
9880 | ||
771c7ce4 | 9881 | case M_DROL: |
fef14a42 | 9882 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
9883 | { |
9884 | if (dreg == sreg) | |
9885 | { | |
9886 | tempreg = AT; | |
9887 | used_at = 1; | |
9888 | } | |
9889 | else | |
9890 | { | |
9891 | tempreg = dreg; | |
82dd0097 | 9892 | } |
67c0d1eb RS |
9893 | macro_build (NULL, "dnegu", "d,w", tempreg, treg); |
9894 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 9895 | break; |
82dd0097 | 9896 | } |
8fc2e39e | 9897 | used_at = 1; |
c80c840e | 9898 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9899 | macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT); |
9900 | macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg); | |
9901 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
771c7ce4 TS |
9902 | break; |
9903 | ||
252b5132 | 9904 | case M_ROL: |
fef14a42 | 9905 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 CD |
9906 | { |
9907 | if (dreg == sreg) | |
9908 | { | |
9909 | tempreg = AT; | |
9910 | used_at = 1; | |
9911 | } | |
9912 | else | |
9913 | { | |
9914 | tempreg = dreg; | |
82dd0097 | 9915 | } |
67c0d1eb RS |
9916 | macro_build (NULL, "negu", "d,w", tempreg, treg); |
9917 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg); | |
8fc2e39e | 9918 | break; |
82dd0097 | 9919 | } |
8fc2e39e | 9920 | used_at = 1; |
c80c840e | 9921 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9922 | macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT); |
9923 | macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg); | |
9924 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
9925 | break; |
9926 | ||
771c7ce4 TS |
9927 | case M_DROL_I: |
9928 | { | |
9929 | unsigned int rot; | |
91d6fa6a NC |
9930 | char *l; |
9931 | char *rr; | |
771c7ce4 TS |
9932 | |
9933 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9934 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9935 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 9936 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
9937 | { |
9938 | rot = (64 - rot) & 0x3f; | |
9939 | if (rot >= 32) | |
df58fc94 | 9940 | macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32); |
60b63b72 | 9941 | else |
df58fc94 | 9942 | macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot); |
8fc2e39e | 9943 | break; |
60b63b72 | 9944 | } |
483fc7cd | 9945 | if (rot == 0) |
483fc7cd | 9946 | { |
df58fc94 | 9947 | macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9948 | break; |
483fc7cd | 9949 | } |
82dd0097 | 9950 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
91d6fa6a | 9951 | rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 | 9952 | rot &= 0x1f; |
8fc2e39e | 9953 | used_at = 1; |
df58fc94 RS |
9954 | macro_build (NULL, l, SHFT_FMT, AT, sreg, rot); |
9955 | macro_build (NULL, rr, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9956 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
9957 | } |
9958 | break; | |
9959 | ||
252b5132 | 9960 | case M_ROL_I: |
771c7ce4 TS |
9961 | { |
9962 | unsigned int rot; | |
9963 | ||
9964 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 9965 | as_bad (_("Improper rotate count")); |
771c7ce4 | 9966 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 9967 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 9968 | { |
df58fc94 | 9969 | macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, (32 - rot) & 0x1f); |
8fc2e39e | 9970 | break; |
60b63b72 | 9971 | } |
483fc7cd | 9972 | if (rot == 0) |
483fc7cd | 9973 | { |
df58fc94 | 9974 | macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 9975 | break; |
483fc7cd | 9976 | } |
8fc2e39e | 9977 | used_at = 1; |
df58fc94 RS |
9978 | macro_build (NULL, "sll", SHFT_FMT, AT, sreg, rot); |
9979 | macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 9980 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
9981 | } |
9982 | break; | |
9983 | ||
9984 | case M_DROR: | |
fef14a42 | 9985 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 9986 | { |
67c0d1eb | 9987 | macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 9988 | break; |
82dd0097 | 9989 | } |
8fc2e39e | 9990 | used_at = 1; |
c80c840e | 9991 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
9992 | macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT); |
9993 | macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg); | |
9994 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
9995 | break; |
9996 | ||
9997 | case M_ROR: | |
fef14a42 | 9998 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 9999 | { |
67c0d1eb | 10000 | macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg); |
8fc2e39e | 10001 | break; |
82dd0097 | 10002 | } |
8fc2e39e | 10003 | used_at = 1; |
c80c840e | 10004 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg); |
67c0d1eb RS |
10005 | macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT); |
10006 | macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg); | |
10007 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); | |
252b5132 RH |
10008 | break; |
10009 | ||
771c7ce4 TS |
10010 | case M_DROR_I: |
10011 | { | |
10012 | unsigned int rot; | |
91d6fa6a NC |
10013 | char *l; |
10014 | char *rr; | |
771c7ce4 TS |
10015 | |
10016 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 10017 | as_bad (_("Improper rotate count")); |
771c7ce4 | 10018 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 10019 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
10020 | { |
10021 | if (rot >= 32) | |
df58fc94 | 10022 | macro_build (NULL, "dror32", SHFT_FMT, dreg, sreg, rot - 32); |
82dd0097 | 10023 | else |
df58fc94 | 10024 | macro_build (NULL, "dror", SHFT_FMT, dreg, sreg, rot); |
8fc2e39e | 10025 | break; |
82dd0097 | 10026 | } |
483fc7cd | 10027 | if (rot == 0) |
483fc7cd | 10028 | { |
df58fc94 | 10029 | macro_build (NULL, "dsrl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 10030 | break; |
483fc7cd | 10031 | } |
91d6fa6a | 10032 | rr = (rot < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 CD |
10033 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; |
10034 | rot &= 0x1f; | |
8fc2e39e | 10035 | used_at = 1; |
df58fc94 RS |
10036 | macro_build (NULL, rr, SHFT_FMT, AT, sreg, rot); |
10037 | macro_build (NULL, l, SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 10038 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 TS |
10039 | } |
10040 | break; | |
10041 | ||
252b5132 | 10042 | case M_ROR_I: |
771c7ce4 TS |
10043 | { |
10044 | unsigned int rot; | |
10045 | ||
10046 | if (imm_expr.X_op != O_constant) | |
82dd0097 | 10047 | as_bad (_("Improper rotate count")); |
771c7ce4 | 10048 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 10049 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 10050 | { |
df58fc94 | 10051 | macro_build (NULL, "ror", SHFT_FMT, dreg, sreg, rot); |
8fc2e39e | 10052 | break; |
82dd0097 | 10053 | } |
483fc7cd | 10054 | if (rot == 0) |
483fc7cd | 10055 | { |
df58fc94 | 10056 | macro_build (NULL, "srl", SHFT_FMT, dreg, sreg, 0); |
8fc2e39e | 10057 | break; |
483fc7cd | 10058 | } |
8fc2e39e | 10059 | used_at = 1; |
df58fc94 RS |
10060 | macro_build (NULL, "srl", SHFT_FMT, AT, sreg, rot); |
10061 | macro_build (NULL, "sll", SHFT_FMT, dreg, sreg, (0x20 - rot) & 0x1f); | |
67c0d1eb | 10062 | macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); |
771c7ce4 | 10063 | } |
252b5132 RH |
10064 | break; |
10065 | ||
252b5132 RH |
10066 | case M_SEQ: |
10067 | if (sreg == 0) | |
67c0d1eb | 10068 | macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16); |
252b5132 | 10069 | else if (treg == 0) |
67c0d1eb | 10070 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
10071 | else |
10072 | { | |
67c0d1eb RS |
10073 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
10074 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 | 10075 | } |
8fc2e39e | 10076 | break; |
252b5132 RH |
10077 | |
10078 | case M_SEQ_I: | |
10079 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
10080 | { | |
67c0d1eb | 10081 | macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 10082 | break; |
252b5132 RH |
10083 | } |
10084 | if (sreg == 0) | |
10085 | { | |
10086 | as_warn (_("Instruction %s: result is always false"), | |
10087 | ip->insn_mo->name); | |
67c0d1eb | 10088 | move_register (dreg, 0); |
8fc2e39e | 10089 | break; |
252b5132 | 10090 | } |
dd3cbb7e NC |
10091 | if (CPU_HAS_SEQ (mips_opts.arch) |
10092 | && -512 <= imm_expr.X_add_number | |
10093 | && imm_expr.X_add_number < 512) | |
10094 | { | |
10095 | macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg, | |
750bdd57 | 10096 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
10097 | break; |
10098 | } | |
252b5132 RH |
10099 | if (imm_expr.X_op == O_constant |
10100 | && imm_expr.X_add_number >= 0 | |
10101 | && imm_expr.X_add_number < 0x10000) | |
10102 | { | |
67c0d1eb | 10103 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
10104 | } |
10105 | else if (imm_expr.X_op == O_constant | |
10106 | && imm_expr.X_add_number > -0x8000 | |
10107 | && imm_expr.X_add_number < 0) | |
10108 | { | |
10109 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10110 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 10111 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 | 10112 | } |
dd3cbb7e NC |
10113 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
10114 | { | |
10115 | used_at = 1; | |
10116 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); | |
10117 | macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT); | |
10118 | break; | |
10119 | } | |
252b5132 RH |
10120 | else |
10121 | { | |
67c0d1eb RS |
10122 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
10123 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
10124 | used_at = 1; |
10125 | } | |
67c0d1eb | 10126 | macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 10127 | break; |
252b5132 RH |
10128 | |
10129 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
10130 | s = "slt"; | |
10131 | goto sge; | |
10132 | case M_SGEU: | |
10133 | s = "sltu"; | |
10134 | sge: | |
67c0d1eb RS |
10135 | macro_build (NULL, s, "d,v,t", dreg, sreg, treg); |
10136 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 10137 | break; |
252b5132 RH |
10138 | |
10139 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
10140 | case M_SGEU_I: | |
10141 | if (imm_expr.X_op == O_constant | |
10142 | && imm_expr.X_add_number >= -0x8000 | |
10143 | && imm_expr.X_add_number < 0x8000) | |
10144 | { | |
67c0d1eb RS |
10145 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
10146 | dreg, sreg, BFD_RELOC_LO16); | |
252b5132 RH |
10147 | } |
10148 | else | |
10149 | { | |
67c0d1eb RS |
10150 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
10151 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", | |
10152 | dreg, sreg, AT); | |
252b5132 RH |
10153 | used_at = 1; |
10154 | } | |
67c0d1eb | 10155 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); |
8fc2e39e | 10156 | break; |
252b5132 RH |
10157 | |
10158 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
10159 | s = "slt"; | |
10160 | goto sgt; | |
10161 | case M_SGTU: | |
10162 | s = "sltu"; | |
10163 | sgt: | |
67c0d1eb | 10164 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
8fc2e39e | 10165 | break; |
252b5132 RH |
10166 | |
10167 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
10168 | s = "slt"; | |
10169 | goto sgti; | |
10170 | case M_SGTU_I: | |
10171 | s = "sltu"; | |
10172 | sgti: | |
8fc2e39e | 10173 | used_at = 1; |
67c0d1eb RS |
10174 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
10175 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
252b5132 RH |
10176 | break; |
10177 | ||
2396cfb9 | 10178 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
252b5132 RH |
10179 | s = "slt"; |
10180 | goto sle; | |
10181 | case M_SLEU: | |
10182 | s = "sltu"; | |
10183 | sle: | |
67c0d1eb RS |
10184 | macro_build (NULL, s, "d,v,t", dreg, treg, sreg); |
10185 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
8fc2e39e | 10186 | break; |
252b5132 | 10187 | |
2396cfb9 | 10188 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
252b5132 RH |
10189 | s = "slt"; |
10190 | goto slei; | |
10191 | case M_SLEU_I: | |
10192 | s = "sltu"; | |
10193 | slei: | |
8fc2e39e | 10194 | used_at = 1; |
67c0d1eb RS |
10195 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
10196 | macro_build (NULL, s, "d,v,t", dreg, AT, sreg); | |
10197 | macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); | |
252b5132 RH |
10198 | break; |
10199 | ||
10200 | case M_SLT_I: | |
10201 | if (imm_expr.X_op == O_constant | |
10202 | && imm_expr.X_add_number >= -0x8000 | |
10203 | && imm_expr.X_add_number < 0x8000) | |
10204 | { | |
67c0d1eb | 10205 | macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 10206 | break; |
252b5132 | 10207 | } |
8fc2e39e | 10208 | used_at = 1; |
67c0d1eb RS |
10209 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
10210 | macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
10211 | break; |
10212 | ||
10213 | case M_SLTU_I: | |
10214 | if (imm_expr.X_op == O_constant | |
10215 | && imm_expr.X_add_number >= -0x8000 | |
10216 | && imm_expr.X_add_number < 0x8000) | |
10217 | { | |
67c0d1eb | 10218 | macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg, |
17a2f251 | 10219 | BFD_RELOC_LO16); |
8fc2e39e | 10220 | break; |
252b5132 | 10221 | } |
8fc2e39e | 10222 | used_at = 1; |
67c0d1eb RS |
10223 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
10224 | macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
10225 | break; |
10226 | ||
10227 | case M_SNE: | |
10228 | if (sreg == 0) | |
67c0d1eb | 10229 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg); |
252b5132 | 10230 | else if (treg == 0) |
67c0d1eb | 10231 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
252b5132 RH |
10232 | else |
10233 | { | |
67c0d1eb RS |
10234 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); |
10235 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
252b5132 | 10236 | } |
8fc2e39e | 10237 | break; |
252b5132 RH |
10238 | |
10239 | case M_SNE_I: | |
10240 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
10241 | { | |
67c0d1eb | 10242 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); |
8fc2e39e | 10243 | break; |
252b5132 RH |
10244 | } |
10245 | if (sreg == 0) | |
10246 | { | |
10247 | as_warn (_("Instruction %s: result is always true"), | |
10248 | ip->insn_mo->name); | |
67c0d1eb RS |
10249 | macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", |
10250 | dreg, 0, BFD_RELOC_LO16); | |
8fc2e39e | 10251 | break; |
252b5132 | 10252 | } |
dd3cbb7e NC |
10253 | if (CPU_HAS_SEQ (mips_opts.arch) |
10254 | && -512 <= imm_expr.X_add_number | |
10255 | && imm_expr.X_add_number < 512) | |
10256 | { | |
10257 | macro_build (NULL, "snei", "t,r,+Q", dreg, sreg, | |
750bdd57 | 10258 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
10259 | break; |
10260 | } | |
252b5132 RH |
10261 | if (imm_expr.X_op == O_constant |
10262 | && imm_expr.X_add_number >= 0 | |
10263 | && imm_expr.X_add_number < 0x10000) | |
10264 | { | |
67c0d1eb | 10265 | macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); |
252b5132 RH |
10266 | } |
10267 | else if (imm_expr.X_op == O_constant | |
10268 | && imm_expr.X_add_number > -0x8000 | |
10269 | && imm_expr.X_add_number < 0) | |
10270 | { | |
10271 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10272 | macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
17a2f251 | 10273 | "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
252b5132 | 10274 | } |
dd3cbb7e NC |
10275 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
10276 | { | |
10277 | used_at = 1; | |
10278 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); | |
10279 | macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT); | |
10280 | break; | |
10281 | } | |
252b5132 RH |
10282 | else |
10283 | { | |
67c0d1eb RS |
10284 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
10285 | macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); | |
252b5132 RH |
10286 | used_at = 1; |
10287 | } | |
67c0d1eb | 10288 | macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); |
8fc2e39e | 10289 | break; |
252b5132 | 10290 | |
df58fc94 RS |
10291 | case M_SUB_I: |
10292 | s = "addi"; | |
10293 | s2 = "sub"; | |
10294 | goto do_subi; | |
10295 | case M_SUBU_I: | |
10296 | s = "addiu"; | |
10297 | s2 = "subu"; | |
10298 | goto do_subi; | |
252b5132 RH |
10299 | case M_DSUB_I: |
10300 | dbl = 1; | |
df58fc94 RS |
10301 | s = "daddi"; |
10302 | s2 = "dsub"; | |
10303 | if (!mips_opts.micromips) | |
10304 | goto do_subi; | |
252b5132 | 10305 | if (imm_expr.X_op == O_constant |
df58fc94 RS |
10306 | && imm_expr.X_add_number > -0x200 |
10307 | && imm_expr.X_add_number <= 0x200) | |
252b5132 | 10308 | { |
df58fc94 | 10309 | macro_build (NULL, s, "t,r,.", dreg, sreg, -imm_expr.X_add_number); |
8fc2e39e | 10310 | break; |
252b5132 | 10311 | } |
df58fc94 | 10312 | goto do_subi_i; |
252b5132 RH |
10313 | case M_DSUBU_I: |
10314 | dbl = 1; | |
df58fc94 RS |
10315 | s = "daddiu"; |
10316 | s2 = "dsubu"; | |
10317 | do_subi: | |
252b5132 RH |
10318 | if (imm_expr.X_op == O_constant |
10319 | && imm_expr.X_add_number > -0x8000 | |
10320 | && imm_expr.X_add_number <= 0x8000) | |
10321 | { | |
10322 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
df58fc94 | 10323 | macro_build (&imm_expr, s, "t,r,j", dreg, sreg, BFD_RELOC_LO16); |
8fc2e39e | 10324 | break; |
252b5132 | 10325 | } |
df58fc94 | 10326 | do_subi_i: |
8fc2e39e | 10327 | used_at = 1; |
67c0d1eb | 10328 | load_register (AT, &imm_expr, dbl); |
df58fc94 | 10329 | macro_build (NULL, s2, "d,v,t", dreg, sreg, AT); |
252b5132 RH |
10330 | break; |
10331 | ||
10332 | case M_TEQ_I: | |
10333 | s = "teq"; | |
10334 | goto trap; | |
10335 | case M_TGE_I: | |
10336 | s = "tge"; | |
10337 | goto trap; | |
10338 | case M_TGEU_I: | |
10339 | s = "tgeu"; | |
10340 | goto trap; | |
10341 | case M_TLT_I: | |
10342 | s = "tlt"; | |
10343 | goto trap; | |
10344 | case M_TLTU_I: | |
10345 | s = "tltu"; | |
10346 | goto trap; | |
10347 | case M_TNE_I: | |
10348 | s = "tne"; | |
10349 | trap: | |
8fc2e39e | 10350 | used_at = 1; |
67c0d1eb RS |
10351 | load_register (AT, &imm_expr, HAVE_64BIT_GPRS); |
10352 | macro_build (NULL, s, "s,t", sreg, AT); | |
252b5132 RH |
10353 | break; |
10354 | ||
252b5132 | 10355 | case M_TRUNCWS: |
43841e91 | 10356 | case M_TRUNCWD: |
df58fc94 | 10357 | gas_assert (!mips_opts.micromips); |
0aa27725 | 10358 | gas_assert (mips_opts.isa == ISA_MIPS1); |
8fc2e39e | 10359 | used_at = 1; |
252b5132 RH |
10360 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
10361 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
10362 | ||
10363 | /* | |
10364 | * Is the double cfc1 instruction a bug in the mips assembler; | |
10365 | * or is there a reason for it? | |
10366 | */ | |
7d10b47d | 10367 | start_noreorder (); |
67c0d1eb RS |
10368 | macro_build (NULL, "cfc1", "t,G", treg, RA); |
10369 | macro_build (NULL, "cfc1", "t,G", treg, RA); | |
10370 | macro_build (NULL, "nop", ""); | |
252b5132 | 10371 | expr1.X_add_number = 3; |
67c0d1eb | 10372 | macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16); |
252b5132 | 10373 | expr1.X_add_number = 2; |
67c0d1eb RS |
10374 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
10375 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
10376 | macro_build (NULL, "nop", ""); | |
10377 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
10378 | dreg, sreg); | |
10379 | macro_build (NULL, "ctc1", "t,G", treg, RA); | |
10380 | macro_build (NULL, "nop", ""); | |
7d10b47d | 10381 | end_noreorder (); |
252b5132 RH |
10382 | break; |
10383 | ||
f2ae14a1 | 10384 | case M_ULH_AB: |
252b5132 | 10385 | s = "lb"; |
df58fc94 RS |
10386 | s2 = "lbu"; |
10387 | off = 1; | |
10388 | goto uld_st; | |
f2ae14a1 | 10389 | case M_ULHU_AB: |
252b5132 | 10390 | s = "lbu"; |
df58fc94 RS |
10391 | s2 = "lbu"; |
10392 | off = 1; | |
10393 | goto uld_st; | |
f2ae14a1 | 10394 | case M_ULW_AB: |
df58fc94 RS |
10395 | s = "lwl"; |
10396 | s2 = "lwr"; | |
7f3c4072 | 10397 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
10398 | off = 3; |
10399 | goto uld_st; | |
f2ae14a1 | 10400 | case M_ULD_AB: |
252b5132 RH |
10401 | s = "ldl"; |
10402 | s2 = "ldr"; | |
7f3c4072 | 10403 | offbits = (mips_opts.micromips ? 12 : 16); |
252b5132 | 10404 | off = 7; |
df58fc94 | 10405 | goto uld_st; |
f2ae14a1 | 10406 | case M_USH_AB: |
df58fc94 RS |
10407 | s = "sb"; |
10408 | s2 = "sb"; | |
10409 | off = 1; | |
10410 | ust = 1; | |
10411 | goto uld_st; | |
f2ae14a1 | 10412 | case M_USW_AB: |
df58fc94 RS |
10413 | s = "swl"; |
10414 | s2 = "swr"; | |
7f3c4072 | 10415 | offbits = (mips_opts.micromips ? 12 : 16); |
252b5132 | 10416 | off = 3; |
df58fc94 RS |
10417 | ust = 1; |
10418 | goto uld_st; | |
f2ae14a1 | 10419 | case M_USD_AB: |
df58fc94 RS |
10420 | s = "sdl"; |
10421 | s2 = "sdr"; | |
7f3c4072 | 10422 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
10423 | off = 7; |
10424 | ust = 1; | |
10425 | ||
10426 | uld_st: | |
f2ae14a1 | 10427 | large_offset = !small_offset_p (off, align, offbits); |
df58fc94 RS |
10428 | ep = &offset_expr; |
10429 | expr1.X_add_number = 0; | |
f2ae14a1 | 10430 | if (large_offset) |
df58fc94 RS |
10431 | { |
10432 | used_at = 1; | |
10433 | tempreg = AT; | |
f2ae14a1 RS |
10434 | if (small_offset_p (0, align, 16)) |
10435 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, -1, | |
10436 | offset_reloc[0], offset_reloc[1], offset_reloc[2]); | |
10437 | else | |
10438 | { | |
10439 | load_address (tempreg, ep, &used_at); | |
10440 | if (breg != 0) | |
10441 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
10442 | tempreg, tempreg, breg); | |
10443 | } | |
10444 | offset_reloc[0] = BFD_RELOC_LO16; | |
10445 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
10446 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
df58fc94 RS |
10447 | breg = tempreg; |
10448 | tempreg = treg; | |
10449 | ep = &expr1; | |
10450 | } | |
10451 | else if (!ust && treg == breg) | |
8fc2e39e TS |
10452 | { |
10453 | used_at = 1; | |
10454 | tempreg = AT; | |
10455 | } | |
252b5132 | 10456 | else |
df58fc94 | 10457 | tempreg = treg; |
af22f5b2 | 10458 | |
df58fc94 RS |
10459 | if (off == 1) |
10460 | goto ulh_sh; | |
252b5132 | 10461 | |
90ecf173 | 10462 | if (!target_big_endian) |
df58fc94 | 10463 | ep->X_add_number += off; |
f2ae14a1 | 10464 | if (offbits == 12) |
df58fc94 RS |
10465 | macro_build (NULL, s, "t,~(b)", |
10466 | tempreg, (unsigned long) ep->X_add_number, breg); | |
f2ae14a1 RS |
10467 | else |
10468 | macro_build (ep, s, "t,o(b)", tempreg, -1, | |
10469 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); | |
df58fc94 | 10470 | |
90ecf173 | 10471 | if (!target_big_endian) |
df58fc94 | 10472 | ep->X_add_number -= off; |
252b5132 | 10473 | else |
df58fc94 | 10474 | ep->X_add_number += off; |
f2ae14a1 | 10475 | if (offbits == 12) |
df58fc94 RS |
10476 | macro_build (NULL, s2, "t,~(b)", |
10477 | tempreg, (unsigned long) ep->X_add_number, breg); | |
f2ae14a1 RS |
10478 | else |
10479 | macro_build (ep, s2, "t,o(b)", tempreg, -1, | |
10480 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); | |
252b5132 | 10481 | |
df58fc94 RS |
10482 | /* If necessary, move the result in tempreg to the final destination. */ |
10483 | if (!ust && treg != tempreg) | |
10484 | { | |
10485 | /* Protect second load's delay slot. */ | |
10486 | load_delay_nop (); | |
10487 | move_register (treg, tempreg); | |
10488 | } | |
8fc2e39e | 10489 | break; |
252b5132 | 10490 | |
df58fc94 | 10491 | ulh_sh: |
d6bc6245 | 10492 | used_at = 1; |
df58fc94 RS |
10493 | if (target_big_endian == ust) |
10494 | ep->X_add_number += off; | |
f2ae14a1 RS |
10495 | tempreg = ust || large_offset ? treg : AT; |
10496 | macro_build (ep, s, "t,o(b)", tempreg, -1, | |
10497 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); | |
df58fc94 RS |
10498 | |
10499 | /* For halfword transfers we need a temporary register to shuffle | |
10500 | bytes. Unfortunately for M_USH_A we have none available before | |
10501 | the next store as AT holds the base address. We deal with this | |
10502 | case by clobbering TREG and then restoring it as with ULH. */ | |
f2ae14a1 | 10503 | tempreg = ust == large_offset ? treg : AT; |
df58fc94 RS |
10504 | if (ust) |
10505 | macro_build (NULL, "srl", SHFT_FMT, tempreg, treg, 8); | |
10506 | ||
10507 | if (target_big_endian == ust) | |
10508 | ep->X_add_number -= off; | |
252b5132 | 10509 | else |
df58fc94 | 10510 | ep->X_add_number += off; |
f2ae14a1 RS |
10511 | macro_build (ep, s2, "t,o(b)", tempreg, -1, |
10512 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); | |
252b5132 | 10513 | |
df58fc94 | 10514 | /* For M_USH_A re-retrieve the LSB. */ |
f2ae14a1 | 10515 | if (ust && large_offset) |
df58fc94 RS |
10516 | { |
10517 | if (target_big_endian) | |
10518 | ep->X_add_number += off; | |
10519 | else | |
10520 | ep->X_add_number -= off; | |
f2ae14a1 RS |
10521 | macro_build (&expr1, "lbu", "t,o(b)", AT, -1, |
10522 | offset_reloc[0], offset_reloc[1], offset_reloc[2], AT); | |
df58fc94 RS |
10523 | } |
10524 | /* For ULH and M_USH_A OR the LSB in. */ | |
f2ae14a1 | 10525 | if (!ust || large_offset) |
df58fc94 | 10526 | { |
f2ae14a1 | 10527 | tempreg = !large_offset ? AT : treg; |
df58fc94 RS |
10528 | macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8); |
10529 | macro_build (NULL, "or", "d,v,t", treg, treg, AT); | |
10530 | } | |
252b5132 RH |
10531 | break; |
10532 | ||
10533 | default: | |
10534 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 10535 | are added dynamically. */ |
252b5132 RH |
10536 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
10537 | break; | |
10538 | } | |
741fe287 | 10539 | if (!mips_opts.at && used_at) |
8fc2e39e | 10540 | as_bad (_("Macro used $at after \".set noat\"")); |
252b5132 RH |
10541 | } |
10542 | ||
10543 | /* Implement macros in mips16 mode. */ | |
10544 | ||
10545 | static void | |
17a2f251 | 10546 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 RH |
10547 | { |
10548 | int mask; | |
10549 | int xreg, yreg, zreg, tmp; | |
252b5132 RH |
10550 | expressionS expr1; |
10551 | int dbl; | |
10552 | const char *s, *s2, *s3; | |
10553 | ||
10554 | mask = ip->insn_mo->mask; | |
10555 | ||
bf12938e RS |
10556 | xreg = MIPS16_EXTRACT_OPERAND (RX, *ip); |
10557 | yreg = MIPS16_EXTRACT_OPERAND (RY, *ip); | |
10558 | zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip); | |
252b5132 | 10559 | |
252b5132 RH |
10560 | expr1.X_op = O_constant; |
10561 | expr1.X_op_symbol = NULL; | |
10562 | expr1.X_add_symbol = NULL; | |
10563 | expr1.X_add_number = 1; | |
10564 | ||
10565 | dbl = 0; | |
10566 | ||
10567 | switch (mask) | |
10568 | { | |
10569 | default: | |
b37df7c4 | 10570 | abort (); |
252b5132 RH |
10571 | |
10572 | case M_DDIV_3: | |
10573 | dbl = 1; | |
10574 | case M_DIV_3: | |
10575 | s = "mflo"; | |
10576 | goto do_div3; | |
10577 | case M_DREM_3: | |
10578 | dbl = 1; | |
10579 | case M_REM_3: | |
10580 | s = "mfhi"; | |
10581 | do_div3: | |
7d10b47d | 10582 | start_noreorder (); |
67c0d1eb | 10583 | macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg); |
252b5132 | 10584 | expr1.X_add_number = 2; |
67c0d1eb RS |
10585 | macro_build (&expr1, "bnez", "x,p", yreg); |
10586 | macro_build (NULL, "break", "6", 7); | |
bdaaa2e1 | 10587 | |
252b5132 RH |
10588 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
10589 | since that causes an overflow. We should do that as well, | |
10590 | but I don't see how to do the comparisons without a temporary | |
10591 | register. */ | |
7d10b47d | 10592 | end_noreorder (); |
67c0d1eb | 10593 | macro_build (NULL, s, "x", zreg); |
252b5132 RH |
10594 | break; |
10595 | ||
10596 | case M_DIVU_3: | |
10597 | s = "divu"; | |
10598 | s2 = "mflo"; | |
10599 | goto do_divu3; | |
10600 | case M_REMU_3: | |
10601 | s = "divu"; | |
10602 | s2 = "mfhi"; | |
10603 | goto do_divu3; | |
10604 | case M_DDIVU_3: | |
10605 | s = "ddivu"; | |
10606 | s2 = "mflo"; | |
10607 | goto do_divu3; | |
10608 | case M_DREMU_3: | |
10609 | s = "ddivu"; | |
10610 | s2 = "mfhi"; | |
10611 | do_divu3: | |
7d10b47d | 10612 | start_noreorder (); |
67c0d1eb | 10613 | macro_build (NULL, s, "0,x,y", xreg, yreg); |
252b5132 | 10614 | expr1.X_add_number = 2; |
67c0d1eb RS |
10615 | macro_build (&expr1, "bnez", "x,p", yreg); |
10616 | macro_build (NULL, "break", "6", 7); | |
7d10b47d | 10617 | end_noreorder (); |
67c0d1eb | 10618 | macro_build (NULL, s2, "x", zreg); |
252b5132 RH |
10619 | break; |
10620 | ||
10621 | case M_DMUL: | |
10622 | dbl = 1; | |
10623 | case M_MUL: | |
67c0d1eb RS |
10624 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
10625 | macro_build (NULL, "mflo", "x", zreg); | |
8fc2e39e | 10626 | break; |
252b5132 RH |
10627 | |
10628 | case M_DSUBU_I: | |
10629 | dbl = 1; | |
10630 | goto do_subu; | |
10631 | case M_SUBU_I: | |
10632 | do_subu: | |
10633 | if (imm_expr.X_op != O_constant) | |
10634 | as_bad (_("Unsupported large constant")); | |
10635 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10636 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
252b5132 RH |
10637 | break; |
10638 | ||
10639 | case M_SUBU_I_2: | |
10640 | if (imm_expr.X_op != O_constant) | |
10641 | as_bad (_("Unsupported large constant")); | |
10642 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10643 | macro_build (&imm_expr, "addiu", "x,k", xreg); |
252b5132 RH |
10644 | break; |
10645 | ||
10646 | case M_DSUBU_I_2: | |
10647 | if (imm_expr.X_op != O_constant) | |
10648 | as_bad (_("Unsupported large constant")); | |
10649 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
67c0d1eb | 10650 | macro_build (&imm_expr, "daddiu", "y,j", yreg); |
252b5132 RH |
10651 | break; |
10652 | ||
10653 | case M_BEQ: | |
10654 | s = "cmp"; | |
10655 | s2 = "bteqz"; | |
10656 | goto do_branch; | |
10657 | case M_BNE: | |
10658 | s = "cmp"; | |
10659 | s2 = "btnez"; | |
10660 | goto do_branch; | |
10661 | case M_BLT: | |
10662 | s = "slt"; | |
10663 | s2 = "btnez"; | |
10664 | goto do_branch; | |
10665 | case M_BLTU: | |
10666 | s = "sltu"; | |
10667 | s2 = "btnez"; | |
10668 | goto do_branch; | |
10669 | case M_BLE: | |
10670 | s = "slt"; | |
10671 | s2 = "bteqz"; | |
10672 | goto do_reverse_branch; | |
10673 | case M_BLEU: | |
10674 | s = "sltu"; | |
10675 | s2 = "bteqz"; | |
10676 | goto do_reverse_branch; | |
10677 | case M_BGE: | |
10678 | s = "slt"; | |
10679 | s2 = "bteqz"; | |
10680 | goto do_branch; | |
10681 | case M_BGEU: | |
10682 | s = "sltu"; | |
10683 | s2 = "bteqz"; | |
10684 | goto do_branch; | |
10685 | case M_BGT: | |
10686 | s = "slt"; | |
10687 | s2 = "btnez"; | |
10688 | goto do_reverse_branch; | |
10689 | case M_BGTU: | |
10690 | s = "sltu"; | |
10691 | s2 = "btnez"; | |
10692 | ||
10693 | do_reverse_branch: | |
10694 | tmp = xreg; | |
10695 | xreg = yreg; | |
10696 | yreg = tmp; | |
10697 | ||
10698 | do_branch: | |
67c0d1eb RS |
10699 | macro_build (NULL, s, "x,y", xreg, yreg); |
10700 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
10701 | break; |
10702 | ||
10703 | case M_BEQ_I: | |
10704 | s = "cmpi"; | |
10705 | s2 = "bteqz"; | |
10706 | s3 = "x,U"; | |
10707 | goto do_branch_i; | |
10708 | case M_BNE_I: | |
10709 | s = "cmpi"; | |
10710 | s2 = "btnez"; | |
10711 | s3 = "x,U"; | |
10712 | goto do_branch_i; | |
10713 | case M_BLT_I: | |
10714 | s = "slti"; | |
10715 | s2 = "btnez"; | |
10716 | s3 = "x,8"; | |
10717 | goto do_branch_i; | |
10718 | case M_BLTU_I: | |
10719 | s = "sltiu"; | |
10720 | s2 = "btnez"; | |
10721 | s3 = "x,8"; | |
10722 | goto do_branch_i; | |
10723 | case M_BLE_I: | |
10724 | s = "slti"; | |
10725 | s2 = "btnez"; | |
10726 | s3 = "x,8"; | |
10727 | goto do_addone_branch_i; | |
10728 | case M_BLEU_I: | |
10729 | s = "sltiu"; | |
10730 | s2 = "btnez"; | |
10731 | s3 = "x,8"; | |
10732 | goto do_addone_branch_i; | |
10733 | case M_BGE_I: | |
10734 | s = "slti"; | |
10735 | s2 = "bteqz"; | |
10736 | s3 = "x,8"; | |
10737 | goto do_branch_i; | |
10738 | case M_BGEU_I: | |
10739 | s = "sltiu"; | |
10740 | s2 = "bteqz"; | |
10741 | s3 = "x,8"; | |
10742 | goto do_branch_i; | |
10743 | case M_BGT_I: | |
10744 | s = "slti"; | |
10745 | s2 = "bteqz"; | |
10746 | s3 = "x,8"; | |
10747 | goto do_addone_branch_i; | |
10748 | case M_BGTU_I: | |
10749 | s = "sltiu"; | |
10750 | s2 = "bteqz"; | |
10751 | s3 = "x,8"; | |
10752 | ||
10753 | do_addone_branch_i: | |
10754 | if (imm_expr.X_op != O_constant) | |
10755 | as_bad (_("Unsupported large constant")); | |
10756 | ++imm_expr.X_add_number; | |
10757 | ||
10758 | do_branch_i: | |
67c0d1eb RS |
10759 | macro_build (&imm_expr, s, s3, xreg); |
10760 | macro_build (&offset_expr, s2, "p"); | |
252b5132 RH |
10761 | break; |
10762 | ||
10763 | case M_ABS: | |
10764 | expr1.X_add_number = 0; | |
67c0d1eb | 10765 | macro_build (&expr1, "slti", "x,8", yreg); |
252b5132 | 10766 | if (xreg != yreg) |
67c0d1eb | 10767 | move_register (xreg, yreg); |
252b5132 | 10768 | expr1.X_add_number = 2; |
67c0d1eb RS |
10769 | macro_build (&expr1, "bteqz", "p"); |
10770 | macro_build (NULL, "neg", "x,w", xreg, xreg); | |
252b5132 RH |
10771 | } |
10772 | } | |
10773 | ||
10774 | /* For consistency checking, verify that all bits are specified either | |
10775 | by the match/mask part of the instruction definition, or by the | |
10776 | operand list. */ | |
10777 | static int | |
17a2f251 | 10778 | validate_mips_insn (const struct mips_opcode *opc) |
252b5132 RH |
10779 | { |
10780 | const char *p = opc->args; | |
10781 | char c; | |
10782 | unsigned long used_bits = opc->mask; | |
10783 | ||
10784 | if ((used_bits & opc->match) != opc->match) | |
10785 | { | |
10786 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
10787 | opc->name, opc->args); | |
10788 | return 0; | |
10789 | } | |
10790 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
10791 | while (*p) | |
10792 | switch (c = *p++) | |
10793 | { | |
10794 | case ',': break; | |
10795 | case '(': break; | |
10796 | case ')': break; | |
af7ee8bf CD |
10797 | case '+': |
10798 | switch (c = *p++) | |
10799 | { | |
9bcd4f99 TS |
10800 | case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break; |
10801 | case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break; | |
10802 | case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break; | |
10803 | case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break; | |
af7ee8bf CD |
10804 | case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
10805 | case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
10806 | case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
5f74bc13 CD |
10807 | case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
10808 | case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; | |
10809 | case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
10810 | case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; | |
10811 | case 'I': break; | |
b015e599 | 10812 | case 'J': USE_BITS (OP_MASK_CODE10, OP_SH_CODE10); break; |
ef2e4d86 | 10813 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; |
bb35fb24 NC |
10814 | case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; |
10815 | case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break; | |
10816 | case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; | |
10817 | case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break; | |
dd3cbb7e | 10818 | case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break; |
bb35fb24 NC |
10819 | case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break; |
10820 | case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break; | |
98675402 RS |
10821 | case 'z': USE_BITS (OP_MASK_RZ, OP_SH_RZ); break; |
10822 | case 'Z': USE_BITS (OP_MASK_FZ, OP_SH_FZ); break; | |
10823 | case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break; | |
10824 | case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break; | |
10825 | case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break; | |
27c5c572 | 10826 | case 'i': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
7f3c4072 | 10827 | case 'j': USE_BITS (OP_MASK_EVAOFFSET, OP_SH_EVAOFFSET); break; |
bb35fb24 | 10828 | |
af7ee8bf CD |
10829 | default: |
10830 | as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), | |
10831 | c, opc->name, opc->args); | |
10832 | return 0; | |
10833 | } | |
10834 | break; | |
252b5132 RH |
10835 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
10836 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
10837 | case 'A': break; | |
4372b673 | 10838 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
252b5132 RH |
10839 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
10840 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
10841 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
10842 | case 'F': break; | |
10843 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
156c2f8b | 10844 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
252b5132 | 10845 | case 'I': break; |
e972090a | 10846 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
af7ee8bf | 10847 | case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
10848 | case 'L': break; |
10849 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
10850 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
deec1734 CD |
10851 | case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; |
10852 | case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); | |
10853 | USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
10854 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
10855 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
10856 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
10857 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
10858 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
deec1734 CD |
10859 | case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
10860 | case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
10861 | case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
252b5132 RH |
10862 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
10863 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10864 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
10865 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
10866 | case 'f': break; | |
10867 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
10868 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
10869 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
10870 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
10871 | case 'l': break; | |
10872 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
10873 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
10874 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
10875 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10876 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10877 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
10878 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
10879 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10880 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
10881 | case 'x': break; | |
10882 | case 'z': break; | |
10883 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
4372b673 NC |
10884 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
10885 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
60b63b72 RS |
10886 | case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; |
10887 | case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; | |
18870af7 | 10888 | case '1': USE_BITS (OP_MASK_STYPE, OP_SH_STYPE); break; |
8b082fb1 | 10889 | case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break; |
74cd071d CF |
10890 | case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break; |
10891 | case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break; | |
10892 | case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break; | |
10893 | case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
10894 | case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break; | |
10895 | case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break; | |
10896 | case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break; | |
10897 | case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break; | |
10898 | case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break; | |
10899 | case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break; | |
10900 | case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break; | |
ef2e4d86 CF |
10901 | case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break; |
10902 | case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break; | |
10903 | case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break; | |
10904 | case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break; | |
dec0624d MR |
10905 | case '\\': USE_BITS (OP_MASK_3BITPOS, OP_SH_3BITPOS); break; |
10906 | case '~': USE_BITS (OP_MASK_OFFSET12, OP_SH_OFFSET12); break; | |
ef2e4d86 | 10907 | case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
252b5132 RH |
10908 | default: |
10909 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
10910 | c, opc->name, opc->args); | |
10911 | return 0; | |
10912 | } | |
10913 | #undef USE_BITS | |
10914 | if (used_bits != 0xffffffff) | |
10915 | { | |
10916 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
10917 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
10918 | return 0; | |
10919 | } | |
10920 | return 1; | |
10921 | } | |
10922 | ||
df58fc94 RS |
10923 | /* For consistency checking, verify that the length implied matches the |
10924 | major opcode and that all bits are specified either by the match/mask | |
10925 | part of the instruction definition, or by the operand list. */ | |
10926 | ||
10927 | static int | |
10928 | validate_micromips_insn (const struct mips_opcode *opc) | |
10929 | { | |
10930 | unsigned long match = opc->match; | |
10931 | unsigned long mask = opc->mask; | |
10932 | const char *p = opc->args; | |
10933 | unsigned long insn_bits; | |
10934 | unsigned long used_bits; | |
10935 | unsigned long major; | |
10936 | unsigned int length; | |
10937 | char e; | |
10938 | char c; | |
10939 | ||
10940 | if ((mask & match) != match) | |
10941 | { | |
10942 | as_bad (_("Internal error: bad microMIPS opcode (mask error): %s %s"), | |
10943 | opc->name, opc->args); | |
10944 | return 0; | |
10945 | } | |
10946 | length = micromips_insn_length (opc); | |
10947 | if (length != 2 && length != 4) | |
10948 | { | |
10949 | as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): " | |
10950 | "%s %s"), length, opc->name, opc->args); | |
10951 | return 0; | |
10952 | } | |
10953 | major = match >> (10 + 8 * (length - 2)); | |
10954 | if ((length == 2 && (major & 7) != 1 && (major & 6) != 2) | |
10955 | || (length == 4 && (major & 7) != 0 && (major & 4) != 4)) | |
10956 | { | |
10957 | as_bad (_("Internal error: bad microMIPS opcode " | |
10958 | "(opcode/length mismatch): %s %s"), opc->name, opc->args); | |
10959 | return 0; | |
10960 | } | |
10961 | ||
10962 | /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */ | |
10963 | insn_bits = 1 << 4 * length; | |
10964 | insn_bits <<= 4 * length; | |
10965 | insn_bits -= 1; | |
10966 | used_bits = mask; | |
10967 | #define USE_BITS(field) \ | |
10968 | (used_bits |= MICROMIPSOP_MASK_##field << MICROMIPSOP_SH_##field) | |
10969 | while (*p) | |
10970 | switch (c = *p++) | |
10971 | { | |
10972 | case ',': break; | |
10973 | case '(': break; | |
10974 | case ')': break; | |
10975 | case '+': | |
10976 | e = c; | |
10977 | switch (c = *p++) | |
10978 | { | |
10979 | case 'A': USE_BITS (EXTLSB); break; | |
10980 | case 'B': USE_BITS (INSMSB); break; | |
10981 | case 'C': USE_BITS (EXTMSBD); break; | |
df58fc94 RS |
10982 | case 'E': USE_BITS (EXTLSB); break; |
10983 | case 'F': USE_BITS (INSMSB); break; | |
10984 | case 'G': USE_BITS (EXTMSBD); break; | |
10985 | case 'H': USE_BITS (EXTMSBD); break; | |
27c5c572 | 10986 | case 'i': USE_BITS (TARGET); break; |
7f3c4072 | 10987 | case 'j': USE_BITS (EVAOFFSET); break; |
df58fc94 RS |
10988 | default: |
10989 | as_bad (_("Internal error: bad mips opcode " | |
10990 | "(unknown extension operand type `%c%c'): %s %s"), | |
10991 | e, c, opc->name, opc->args); | |
10992 | return 0; | |
10993 | } | |
10994 | break; | |
10995 | case 'm': | |
10996 | e = c; | |
10997 | switch (c = *p++) | |
10998 | { | |
10999 | case 'A': USE_BITS (IMMA); break; | |
11000 | case 'B': USE_BITS (IMMB); break; | |
11001 | case 'C': USE_BITS (IMMC); break; | |
11002 | case 'D': USE_BITS (IMMD); break; | |
11003 | case 'E': USE_BITS (IMME); break; | |
11004 | case 'F': USE_BITS (IMMF); break; | |
11005 | case 'G': USE_BITS (IMMG); break; | |
11006 | case 'H': USE_BITS (IMMH); break; | |
11007 | case 'I': USE_BITS (IMMI); break; | |
11008 | case 'J': USE_BITS (IMMJ); break; | |
11009 | case 'L': USE_BITS (IMML); break; | |
11010 | case 'M': USE_BITS (IMMM); break; | |
11011 | case 'N': USE_BITS (IMMN); break; | |
11012 | case 'O': USE_BITS (IMMO); break; | |
11013 | case 'P': USE_BITS (IMMP); break; | |
11014 | case 'Q': USE_BITS (IMMQ); break; | |
11015 | case 'U': USE_BITS (IMMU); break; | |
11016 | case 'W': USE_BITS (IMMW); break; | |
11017 | case 'X': USE_BITS (IMMX); break; | |
11018 | case 'Y': USE_BITS (IMMY); break; | |
11019 | case 'Z': break; | |
11020 | case 'a': break; | |
11021 | case 'b': USE_BITS (MB); break; | |
11022 | case 'c': USE_BITS (MC); break; | |
11023 | case 'd': USE_BITS (MD); break; | |
11024 | case 'e': USE_BITS (ME); break; | |
11025 | case 'f': USE_BITS (MF); break; | |
11026 | case 'g': USE_BITS (MG); break; | |
11027 | case 'h': USE_BITS (MH); break; | |
df58fc94 RS |
11028 | case 'j': USE_BITS (MJ); break; |
11029 | case 'l': USE_BITS (ML); break; | |
11030 | case 'm': USE_BITS (MM); break; | |
11031 | case 'n': USE_BITS (MN); break; | |
11032 | case 'p': USE_BITS (MP); break; | |
11033 | case 'q': USE_BITS (MQ); break; | |
11034 | case 'r': break; | |
11035 | case 's': break; | |
11036 | case 't': break; | |
11037 | case 'x': break; | |
11038 | case 'y': break; | |
11039 | case 'z': break; | |
11040 | default: | |
11041 | as_bad (_("Internal error: bad mips opcode " | |
11042 | "(unknown extension operand type `%c%c'): %s %s"), | |
11043 | e, c, opc->name, opc->args); | |
11044 | return 0; | |
11045 | } | |
11046 | break; | |
11047 | case '.': USE_BITS (OFFSET10); break; | |
11048 | case '1': USE_BITS (STYPE); break; | |
03f66e8a MR |
11049 | case '2': USE_BITS (BP); break; |
11050 | case '3': USE_BITS (SA3); break; | |
11051 | case '4': USE_BITS (SA4); break; | |
11052 | case '5': USE_BITS (IMM8); break; | |
11053 | case '6': USE_BITS (RS); break; | |
11054 | case '7': USE_BITS (DSPACC); break; | |
11055 | case '8': USE_BITS (WRDSP); break; | |
11056 | case '0': USE_BITS (DSPSFT); break; | |
df58fc94 RS |
11057 | case '<': USE_BITS (SHAMT); break; |
11058 | case '>': USE_BITS (SHAMT); break; | |
03f66e8a | 11059 | case '@': USE_BITS (IMM10); break; |
df58fc94 RS |
11060 | case 'B': USE_BITS (CODE10); break; |
11061 | case 'C': USE_BITS (COPZ); break; | |
11062 | case 'D': USE_BITS (FD); break; | |
11063 | case 'E': USE_BITS (RT); break; | |
11064 | case 'G': USE_BITS (RS); break; | |
444d75be | 11065 | case 'H': USE_BITS (SEL); break; |
df58fc94 RS |
11066 | case 'K': USE_BITS (RS); break; |
11067 | case 'M': USE_BITS (CCC); break; | |
11068 | case 'N': USE_BITS (BCC); break; | |
11069 | case 'R': USE_BITS (FR); break; | |
11070 | case 'S': USE_BITS (FS); break; | |
11071 | case 'T': USE_BITS (FT); break; | |
11072 | case 'V': USE_BITS (FS); break; | |
dec0624d | 11073 | case '\\': USE_BITS (3BITPOS); break; |
03f66e8a | 11074 | case '^': USE_BITS (RD); break; |
df58fc94 RS |
11075 | case 'a': USE_BITS (TARGET); break; |
11076 | case 'b': USE_BITS (RS); break; | |
11077 | case 'c': USE_BITS (CODE); break; | |
11078 | case 'd': USE_BITS (RD); break; | |
11079 | case 'h': USE_BITS (PREFX); break; | |
11080 | case 'i': USE_BITS (IMMEDIATE); break; | |
11081 | case 'j': USE_BITS (DELTA); break; | |
11082 | case 'k': USE_BITS (CACHE); break; | |
11083 | case 'n': USE_BITS (RT); break; | |
11084 | case 'o': USE_BITS (DELTA); break; | |
11085 | case 'p': USE_BITS (DELTA); break; | |
11086 | case 'q': USE_BITS (CODE2); break; | |
11087 | case 'r': USE_BITS (RS); break; | |
11088 | case 's': USE_BITS (RS); break; | |
11089 | case 't': USE_BITS (RT); break; | |
11090 | case 'u': USE_BITS (IMMEDIATE); break; | |
11091 | case 'v': USE_BITS (RS); break; | |
11092 | case 'w': USE_BITS (RT); break; | |
11093 | case 'y': USE_BITS (RS3); break; | |
11094 | case 'z': break; | |
11095 | case '|': USE_BITS (TRAP); break; | |
11096 | case '~': USE_BITS (OFFSET12); break; | |
11097 | default: | |
11098 | as_bad (_("Internal error: bad microMIPS opcode " | |
11099 | "(unknown operand type `%c'): %s %s"), | |
11100 | c, opc->name, opc->args); | |
11101 | return 0; | |
11102 | } | |
11103 | #undef USE_BITS | |
11104 | if (used_bits != insn_bits) | |
11105 | { | |
11106 | if (~used_bits & insn_bits) | |
11107 | as_bad (_("Internal error: bad microMIPS opcode " | |
11108 | "(bits 0x%lx undefined): %s %s"), | |
11109 | ~used_bits & insn_bits, opc->name, opc->args); | |
11110 | if (used_bits & ~insn_bits) | |
11111 | as_bad (_("Internal error: bad microMIPS opcode " | |
11112 | "(bits 0x%lx defined): %s %s"), | |
11113 | used_bits & ~insn_bits, opc->name, opc->args); | |
11114 | return 0; | |
11115 | } | |
11116 | return 1; | |
11117 | } | |
11118 | ||
9bcd4f99 TS |
11119 | /* UDI immediates. */ |
11120 | struct mips_immed { | |
11121 | char type; | |
11122 | unsigned int shift; | |
11123 | unsigned long mask; | |
11124 | const char * desc; | |
11125 | }; | |
11126 | ||
11127 | static const struct mips_immed mips_immed[] = { | |
11128 | { '1', OP_SH_UDI1, OP_MASK_UDI1, 0}, | |
11129 | { '2', OP_SH_UDI2, OP_MASK_UDI2, 0}, | |
11130 | { '3', OP_SH_UDI3, OP_MASK_UDI3, 0}, | |
11131 | { '4', OP_SH_UDI4, OP_MASK_UDI4, 0}, | |
11132 | { 0,0,0,0 } | |
11133 | }; | |
11134 | ||
7455baf8 TS |
11135 | /* Check whether an odd floating-point register is allowed. */ |
11136 | static int | |
11137 | mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum) | |
11138 | { | |
11139 | const char *s = insn->name; | |
11140 | ||
11141 | if (insn->pinfo == INSN_MACRO) | |
11142 | /* Let a macro pass, we'll catch it later when it is expanded. */ | |
11143 | return 1; | |
11144 | ||
e407c74b | 11145 | if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa) || (mips_opts.arch == CPU_R5900)) |
7455baf8 TS |
11146 | { |
11147 | /* Allow odd registers for single-precision ops. */ | |
11148 | switch (insn->pinfo & (FP_S | FP_D)) | |
11149 | { | |
11150 | case FP_S: | |
11151 | case 0: | |
11152 | return 1; /* both single precision - ok */ | |
11153 | case FP_D: | |
11154 | return 0; /* both double precision - fail */ | |
11155 | default: | |
11156 | break; | |
11157 | } | |
11158 | ||
11159 | /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ | |
11160 | s = strchr (insn->name, '.'); | |
11161 | if (argnum == 2) | |
11162 | s = s != NULL ? strchr (s + 1, '.') : NULL; | |
11163 | return (s != NULL && (s[1] == 'w' || s[1] == 's')); | |
11164 | } | |
11165 | ||
11166 | /* Single-precision coprocessor loads and moves are OK too. */ | |
11167 | if ((insn->pinfo & FP_S) | |
11168 | && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY | |
11169 | | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY))) | |
11170 | return 1; | |
11171 | ||
11172 | return 0; | |
11173 | } | |
11174 | ||
df58fc94 RS |
11175 | /* Check if EXPR is a constant between MIN (inclusive) and MAX (exclusive) |
11176 | taking bits from BIT up. */ | |
11177 | static int | |
11178 | expr_const_in_range (expressionS *ep, offsetT min, offsetT max, int bit) | |
11179 | { | |
11180 | return (ep->X_op == O_constant | |
11181 | && (ep->X_add_number & ((1 << bit) - 1)) == 0 | |
11182 | && ep->X_add_number >= min << bit | |
11183 | && ep->X_add_number < max << bit); | |
11184 | } | |
11185 | ||
77bd4346 RS |
11186 | /* Assemble an instruction into its binary format. If the instruction |
11187 | is a macro, set imm_expr, imm2_expr and offset_expr to the values | |
11188 | associated with "I", "+I" and "A" operands respectively. Otherwise | |
11189 | store the value of the relocatable field (if any) in offset_expr. | |
11190 | In both cases set offset_reloc to the relocation operators applied | |
11191 | to offset_expr. */ | |
252b5132 RH |
11192 | |
11193 | static void | |
17a2f251 | 11194 | mips_ip (char *str, struct mips_cl_insn *ip) |
252b5132 | 11195 | { |
df58fc94 RS |
11196 | bfd_boolean wrong_delay_slot_insns = FALSE; |
11197 | bfd_boolean need_delay_slot_ok = TRUE; | |
11198 | struct mips_opcode *firstinsn = NULL; | |
11199 | const struct mips_opcode *past; | |
11200 | struct hash_control *hash; | |
252b5132 RH |
11201 | char *s; |
11202 | const char *args; | |
43841e91 | 11203 | char c = 0; |
252b5132 RH |
11204 | struct mips_opcode *insn; |
11205 | char *argsStart; | |
e76ff5ab | 11206 | unsigned int regno, regno2; |
34224acf | 11207 | unsigned int lastregno; |
df58fc94 | 11208 | unsigned int destregno = 0; |
af7ee8bf | 11209 | unsigned int lastpos = 0; |
071742cf | 11210 | unsigned int limlo, limhi; |
f02d8318 | 11211 | int sizelo; |
252b5132 | 11212 | char *s_reset; |
74cd071d | 11213 | offsetT min_range, max_range; |
df58fc94 | 11214 | long opend; |
a40bc9dd | 11215 | char *name; |
707bfff6 TS |
11216 | int argnum; |
11217 | unsigned int rtype; | |
df58fc94 | 11218 | char *dot; |
a40bc9dd | 11219 | long end; |
252b5132 RH |
11220 | |
11221 | insn_error = NULL; | |
11222 | ||
df58fc94 RS |
11223 | if (mips_opts.micromips) |
11224 | { | |
11225 | hash = micromips_op_hash; | |
11226 | past = µmips_opcodes[bfd_micromips_num_opcodes]; | |
11227 | } | |
11228 | else | |
11229 | { | |
11230 | hash = op_hash; | |
11231 | past = &mips_opcodes[NUMOPCODES]; | |
11232 | } | |
11233 | forced_insn_length = 0; | |
252b5132 | 11234 | insn = NULL; |
252b5132 | 11235 | |
df58fc94 | 11236 | /* We first try to match an instruction up to a space or to the end. */ |
a40bc9dd RS |
11237 | for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++) |
11238 | continue; | |
bdaaa2e1 | 11239 | |
a40bc9dd RS |
11240 | /* Make a copy of the instruction so that we can fiddle with it. */ |
11241 | name = alloca (end + 1); | |
11242 | memcpy (name, str, end); | |
11243 | name[end] = '\0'; | |
252b5132 | 11244 | |
df58fc94 RS |
11245 | for (;;) |
11246 | { | |
11247 | insn = (struct mips_opcode *) hash_find (hash, name); | |
11248 | ||
11249 | if (insn != NULL || !mips_opts.micromips) | |
11250 | break; | |
11251 | if (forced_insn_length) | |
11252 | break; | |
11253 | ||
11254 | /* See if there's an instruction size override suffix, | |
11255 | either `16' or `32', at the end of the mnemonic proper, | |
11256 | that defines the operation, i.e. before the first `.' | |
11257 | character if any. Strip it and retry. */ | |
11258 | dot = strchr (name, '.'); | |
11259 | opend = dot != NULL ? dot - name : end; | |
11260 | if (opend < 3) | |
11261 | break; | |
11262 | if (name[opend - 2] == '1' && name[opend - 1] == '6') | |
11263 | forced_insn_length = 2; | |
11264 | else if (name[opend - 2] == '3' && name[opend - 1] == '2') | |
11265 | forced_insn_length = 4; | |
11266 | else | |
11267 | break; | |
11268 | memcpy (name + opend - 2, name + opend, end - opend + 1); | |
11269 | } | |
252b5132 RH |
11270 | if (insn == NULL) |
11271 | { | |
a40bc9dd RS |
11272 | insn_error = _("Unrecognized opcode"); |
11273 | return; | |
252b5132 RH |
11274 | } |
11275 | ||
df58fc94 RS |
11276 | /* For microMIPS instructions placed in a fixed-length branch delay slot |
11277 | we make up to two passes over the relevant fragment of the opcode | |
11278 | table. First we try instructions that meet the delay slot's length | |
11279 | requirement. If none matched, then we retry with the remaining ones | |
11280 | and if one matches, then we use it and then issue an appropriate | |
11281 | warning later on. */ | |
a40bc9dd | 11282 | argsStart = s = str + end; |
252b5132 RH |
11283 | for (;;) |
11284 | { | |
df58fc94 RS |
11285 | bfd_boolean delay_slot_ok; |
11286 | bfd_boolean size_ok; | |
b34976b6 | 11287 | bfd_boolean ok; |
252b5132 | 11288 | |
a40bc9dd | 11289 | gas_assert (strcmp (insn->name, name) == 0); |
252b5132 | 11290 | |
f79e2745 | 11291 | ok = is_opcode_valid (insn); |
df58fc94 RS |
11292 | size_ok = is_size_valid (insn); |
11293 | delay_slot_ok = is_delay_slot_valid (insn); | |
11294 | if (!delay_slot_ok && !wrong_delay_slot_insns) | |
252b5132 | 11295 | { |
df58fc94 RS |
11296 | firstinsn = insn; |
11297 | wrong_delay_slot_insns = TRUE; | |
11298 | } | |
11299 | if (!ok || !size_ok || delay_slot_ok != need_delay_slot_ok) | |
11300 | { | |
11301 | static char buf[256]; | |
11302 | ||
11303 | if (insn + 1 < past && strcmp (insn->name, insn[1].name) == 0) | |
252b5132 RH |
11304 | { |
11305 | ++insn; | |
11306 | continue; | |
11307 | } | |
df58fc94 | 11308 | if (wrong_delay_slot_insns && need_delay_slot_ok) |
beae10d5 | 11309 | { |
df58fc94 RS |
11310 | gas_assert (firstinsn); |
11311 | need_delay_slot_ok = FALSE; | |
11312 | past = insn + 1; | |
11313 | insn = firstinsn; | |
11314 | continue; | |
252b5132 | 11315 | } |
df58fc94 RS |
11316 | |
11317 | if (insn_error) | |
11318 | return; | |
11319 | ||
11320 | if (!ok) | |
7bd942df | 11321 | sprintf (buf, _("Opcode not supported on this processor: %s (%s)"), |
df58fc94 RS |
11322 | mips_cpu_info_from_arch (mips_opts.arch)->name, |
11323 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
833794fc MR |
11324 | else if (mips_opts.insn32) |
11325 | sprintf (buf, _("Opcode not supported in the `insn32' mode")); | |
df58fc94 RS |
11326 | else |
11327 | sprintf (buf, _("Unrecognized %u-bit version of microMIPS opcode"), | |
11328 | 8 * forced_insn_length); | |
11329 | insn_error = buf; | |
11330 | ||
11331 | return; | |
252b5132 RH |
11332 | } |
11333 | ||
f2ae14a1 RS |
11334 | imm_expr.X_op = O_absent; |
11335 | imm2_expr.X_op = O_absent; | |
11336 | offset_expr.X_op = O_absent; | |
f2ae14a1 RS |
11337 | offset_reloc[0] = BFD_RELOC_UNUSED; |
11338 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
11339 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
11340 | ||
1e915849 | 11341 | create_insn (ip, insn); |
268f6bed | 11342 | insn_error = NULL; |
707bfff6 | 11343 | argnum = 1; |
24864476 | 11344 | lastregno = 0xffffffff; |
252b5132 RH |
11345 | for (args = insn->args;; ++args) |
11346 | { | |
deec1734 CD |
11347 | int is_mdmx; |
11348 | ||
ad8d3bb3 | 11349 | s += strspn (s, " \t"); |
deec1734 | 11350 | is_mdmx = 0; |
252b5132 RH |
11351 | switch (*args) |
11352 | { | |
11353 | case '\0': /* end of args */ | |
11354 | if (*s == '\0') | |
11355 | return; | |
11356 | break; | |
11357 | ||
03f66e8a MR |
11358 | case '2': |
11359 | /* DSP 2-bit unsigned immediate in bit 11 (for standard MIPS | |
11360 | code) or 14 (for microMIPS code). */ | |
8b082fb1 TS |
11361 | my_getExpression (&imm_expr, s); |
11362 | check_absolute_expr (ip, &imm_expr); | |
11363 | if ((unsigned long) imm_expr.X_add_number != 1 | |
11364 | && (unsigned long) imm_expr.X_add_number != 3) | |
11365 | { | |
11366 | as_bad (_("BALIGN immediate not 1 or 3 (%lu)"), | |
11367 | (unsigned long) imm_expr.X_add_number); | |
11368 | } | |
03f66e8a MR |
11369 | INSERT_OPERAND (mips_opts.micromips, |
11370 | BP, *ip, imm_expr.X_add_number); | |
8b082fb1 TS |
11371 | imm_expr.X_op = O_absent; |
11372 | s = expr_end; | |
11373 | continue; | |
11374 | ||
03f66e8a | 11375 | case '3': |
c3678916 RS |
11376 | /* DSP 3-bit unsigned immediate in bit 21 (for standard MIPS |
11377 | code) or 13 (for microMIPS code). */ | |
03f66e8a MR |
11378 | { |
11379 | unsigned long mask = (mips_opts.micromips | |
11380 | ? MICROMIPSOP_MASK_SA3 : OP_MASK_SA3); | |
11381 | ||
11382 | my_getExpression (&imm_expr, s); | |
11383 | check_absolute_expr (ip, &imm_expr); | |
11384 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11385 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
11386 | mask, (unsigned long) imm_expr.X_add_number); | |
11387 | INSERT_OPERAND (mips_opts.micromips, | |
11388 | SA3, *ip, imm_expr.X_add_number); | |
11389 | imm_expr.X_op = O_absent; | |
11390 | s = expr_end; | |
11391 | } | |
74cd071d CF |
11392 | continue; |
11393 | ||
03f66e8a | 11394 | case '4': |
c3678916 RS |
11395 | /* DSP 4-bit unsigned immediate in bit 21 (for standard MIPS |
11396 | code) or 12 (for microMIPS code). */ | |
03f66e8a MR |
11397 | { |
11398 | unsigned long mask = (mips_opts.micromips | |
11399 | ? MICROMIPSOP_MASK_SA4 : OP_MASK_SA4); | |
11400 | ||
11401 | my_getExpression (&imm_expr, s); | |
11402 | check_absolute_expr (ip, &imm_expr); | |
11403 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11404 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
11405 | mask, (unsigned long) imm_expr.X_add_number); | |
11406 | INSERT_OPERAND (mips_opts.micromips, | |
11407 | SA4, *ip, imm_expr.X_add_number); | |
11408 | imm_expr.X_op = O_absent; | |
11409 | s = expr_end; | |
11410 | } | |
74cd071d CF |
11411 | continue; |
11412 | ||
03f66e8a | 11413 | case '5': |
c3678916 RS |
11414 | /* DSP 8-bit unsigned immediate in bit 16 (for standard MIPS |
11415 | code) or 13 (for microMIPS code). */ | |
03f66e8a MR |
11416 | { |
11417 | unsigned long mask = (mips_opts.micromips | |
11418 | ? MICROMIPSOP_MASK_IMM8 : OP_MASK_IMM8); | |
11419 | ||
11420 | my_getExpression (&imm_expr, s); | |
11421 | check_absolute_expr (ip, &imm_expr); | |
11422 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11423 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
11424 | mask, (unsigned long) imm_expr.X_add_number); | |
11425 | INSERT_OPERAND (mips_opts.micromips, | |
11426 | IMM8, *ip, imm_expr.X_add_number); | |
11427 | imm_expr.X_op = O_absent; | |
11428 | s = expr_end; | |
11429 | } | |
74cd071d CF |
11430 | continue; |
11431 | ||
03f66e8a | 11432 | case '6': |
c3678916 RS |
11433 | /* DSP 5-bit unsigned immediate in bit 21 (for standard MIPS |
11434 | code) or 16 (for microMIPS code). */ | |
03f66e8a MR |
11435 | { |
11436 | unsigned long mask = (mips_opts.micromips | |
11437 | ? MICROMIPSOP_MASK_RS : OP_MASK_RS); | |
11438 | ||
11439 | my_getExpression (&imm_expr, s); | |
11440 | check_absolute_expr (ip, &imm_expr); | |
11441 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11442 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
11443 | mask, (unsigned long) imm_expr.X_add_number); | |
11444 | INSERT_OPERAND (mips_opts.micromips, | |
11445 | RS, *ip, imm_expr.X_add_number); | |
11446 | imm_expr.X_op = O_absent; | |
11447 | s = expr_end; | |
11448 | } | |
74cd071d CF |
11449 | continue; |
11450 | ||
c3678916 RS |
11451 | case '7': |
11452 | /* Four DSP accumulators in bit 11 (for standard MIPS code) | |
11453 | or 14 (for microMIPS code). */ | |
03f66e8a MR |
11454 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' |
11455 | && s[3] >= '0' && s[3] <= '3') | |
74cd071d CF |
11456 | { |
11457 | regno = s[3] - '0'; | |
11458 | s += 4; | |
03f66e8a | 11459 | INSERT_OPERAND (mips_opts.micromips, DSPACC, *ip, regno); |
74cd071d CF |
11460 | continue; |
11461 | } | |
11462 | else | |
11463 | as_bad (_("Invalid dsp acc register")); | |
11464 | break; | |
11465 | ||
03f66e8a MR |
11466 | case '8': |
11467 | /* DSP 6-bit unsigned immediate in bit 11 (for standard MIPS | |
11468 | code) or 14 (for microMIPS code). */ | |
11469 | { | |
11470 | unsigned long mask = (mips_opts.micromips | |
11471 | ? MICROMIPSOP_MASK_WRDSP | |
11472 | : OP_MASK_WRDSP); | |
11473 | ||
11474 | my_getExpression (&imm_expr, s); | |
11475 | check_absolute_expr (ip, &imm_expr); | |
11476 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11477 | as_bad (_("DSP immediate not in range 0..%lu (%lu)"), | |
11478 | mask, (unsigned long) imm_expr.X_add_number); | |
11479 | INSERT_OPERAND (mips_opts.micromips, | |
11480 | WRDSP, *ip, imm_expr.X_add_number); | |
11481 | imm_expr.X_op = O_absent; | |
11482 | s = expr_end; | |
11483 | } | |
74cd071d CF |
11484 | continue; |
11485 | ||
90ecf173 | 11486 | case '9': /* Four DSP accumulators in bits 21,22. */ |
df58fc94 | 11487 | gas_assert (!mips_opts.micromips); |
03f66e8a MR |
11488 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' |
11489 | && s[3] >= '0' && s[3] <= '3') | |
74cd071d CF |
11490 | { |
11491 | regno = s[3] - '0'; | |
11492 | s += 4; | |
df58fc94 | 11493 | INSERT_OPERAND (0, DSPACC_S, *ip, regno); |
74cd071d CF |
11494 | continue; |
11495 | } | |
11496 | else | |
11497 | as_bad (_("Invalid dsp acc register")); | |
11498 | break; | |
11499 | ||
03f66e8a | 11500 | case '0': |
c3678916 RS |
11501 | /* DSP 6-bit signed immediate in bit 20 (for standard MIPS |
11502 | code) or 16 (for microMIPS code). */ | |
03f66e8a MR |
11503 | { |
11504 | long mask = (mips_opts.micromips | |
11505 | ? MICROMIPSOP_MASK_DSPSFT : OP_MASK_DSPSFT); | |
11506 | ||
11507 | my_getExpression (&imm_expr, s); | |
11508 | check_absolute_expr (ip, &imm_expr); | |
11509 | min_range = -((mask + 1) >> 1); | |
11510 | max_range = ((mask + 1) >> 1) - 1; | |
11511 | if (imm_expr.X_add_number < min_range | |
11512 | || imm_expr.X_add_number > max_range) | |
a9e24354 TS |
11513 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
11514 | (long) min_range, (long) max_range, | |
11515 | (long) imm_expr.X_add_number); | |
03f66e8a MR |
11516 | INSERT_OPERAND (mips_opts.micromips, |
11517 | DSPSFT, *ip, imm_expr.X_add_number); | |
11518 | imm_expr.X_op = O_absent; | |
11519 | s = expr_end; | |
11520 | } | |
74cd071d CF |
11521 | continue; |
11522 | ||
90ecf173 | 11523 | case '\'': /* DSP 6-bit unsigned immediate in bit 16. */ |
df58fc94 | 11524 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
11525 | my_getExpression (&imm_expr, s); |
11526 | check_absolute_expr (ip, &imm_expr); | |
11527 | if (imm_expr.X_add_number & ~OP_MASK_RDDSP) | |
11528 | { | |
a9e24354 TS |
11529 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), |
11530 | OP_MASK_RDDSP, | |
11531 | (unsigned long) imm_expr.X_add_number); | |
74cd071d | 11532 | } |
df58fc94 | 11533 | INSERT_OPERAND (0, RDDSP, *ip, imm_expr.X_add_number); |
74cd071d CF |
11534 | imm_expr.X_op = O_absent; |
11535 | s = expr_end; | |
11536 | continue; | |
11537 | ||
90ecf173 | 11538 | case ':': /* DSP 7-bit signed immediate in bit 19. */ |
df58fc94 | 11539 | gas_assert (!mips_opts.micromips); |
74cd071d CF |
11540 | my_getExpression (&imm_expr, s); |
11541 | check_absolute_expr (ip, &imm_expr); | |
11542 | min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1); | |
11543 | max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1; | |
11544 | if (imm_expr.X_add_number < min_range || | |
11545 | imm_expr.X_add_number > max_range) | |
11546 | { | |
a9e24354 TS |
11547 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
11548 | (long) min_range, (long) max_range, | |
11549 | (long) imm_expr.X_add_number); | |
74cd071d | 11550 | } |
df58fc94 | 11551 | INSERT_OPERAND (0, DSPSFT_7, *ip, imm_expr.X_add_number); |
74cd071d CF |
11552 | imm_expr.X_op = O_absent; |
11553 | s = expr_end; | |
11554 | continue; | |
11555 | ||
90ecf173 | 11556 | case '@': /* DSP 10-bit signed immediate in bit 16. */ |
03f66e8a MR |
11557 | { |
11558 | long mask = (mips_opts.micromips | |
11559 | ? MICROMIPSOP_MASK_IMM10 : OP_MASK_IMM10); | |
11560 | ||
11561 | my_getExpression (&imm_expr, s); | |
11562 | check_absolute_expr (ip, &imm_expr); | |
11563 | min_range = -((mask + 1) >> 1); | |
11564 | max_range = ((mask + 1) >> 1) - 1; | |
11565 | if (imm_expr.X_add_number < min_range | |
11566 | || imm_expr.X_add_number > max_range) | |
a9e24354 TS |
11567 | as_bad (_("DSP immediate not in range %ld..%ld (%ld)"), |
11568 | (long) min_range, (long) max_range, | |
11569 | (long) imm_expr.X_add_number); | |
03f66e8a MR |
11570 | INSERT_OPERAND (mips_opts.micromips, |
11571 | IMM10, *ip, imm_expr.X_add_number); | |
11572 | imm_expr.X_op = O_absent; | |
11573 | s = expr_end; | |
11574 | } | |
11575 | continue; | |
11576 | ||
11577 | case '^': /* DSP 5-bit unsigned immediate in bit 11. */ | |
11578 | gas_assert (mips_opts.micromips); | |
11579 | my_getExpression (&imm_expr, s); | |
11580 | check_absolute_expr (ip, &imm_expr); | |
11581 | if (imm_expr.X_add_number & ~MICROMIPSOP_MASK_RD) | |
11582 | as_bad (_("DSP immediate not in range 0..%d (%lu)"), | |
11583 | MICROMIPSOP_MASK_RD, | |
11584 | (unsigned long) imm_expr.X_add_number); | |
11585 | INSERT_OPERAND (1, RD, *ip, imm_expr.X_add_number); | |
74cd071d CF |
11586 | imm_expr.X_op = O_absent; |
11587 | s = expr_end; | |
11588 | continue; | |
11589 | ||
a9e24354 | 11590 | case '!': /* MT usermode flag bit. */ |
df58fc94 | 11591 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11592 | my_getExpression (&imm_expr, s); |
11593 | check_absolute_expr (ip, &imm_expr); | |
11594 | if (imm_expr.X_add_number & ~OP_MASK_MT_U) | |
a9e24354 TS |
11595 | as_bad (_("MT usermode bit not 0 or 1 (%lu)"), |
11596 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 11597 | INSERT_OPERAND (0, MT_U, *ip, imm_expr.X_add_number); |
ef2e4d86 CF |
11598 | imm_expr.X_op = O_absent; |
11599 | s = expr_end; | |
11600 | continue; | |
11601 | ||
a9e24354 | 11602 | case '$': /* MT load high flag bit. */ |
df58fc94 | 11603 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11604 | my_getExpression (&imm_expr, s); |
11605 | check_absolute_expr (ip, &imm_expr); | |
11606 | if (imm_expr.X_add_number & ~OP_MASK_MT_H) | |
a9e24354 TS |
11607 | as_bad (_("MT load high bit not 0 or 1 (%lu)"), |
11608 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 11609 | INSERT_OPERAND (0, MT_H, *ip, imm_expr.X_add_number); |
ef2e4d86 CF |
11610 | imm_expr.X_op = O_absent; |
11611 | s = expr_end; | |
11612 | continue; | |
11613 | ||
90ecf173 | 11614 | case '*': /* Four DSP accumulators in bits 18,19. */ |
df58fc94 | 11615 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11616 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
11617 | s[3] >= '0' && s[3] <= '3') | |
11618 | { | |
11619 | regno = s[3] - '0'; | |
11620 | s += 4; | |
df58fc94 | 11621 | INSERT_OPERAND (0, MTACC_T, *ip, regno); |
ef2e4d86 CF |
11622 | continue; |
11623 | } | |
11624 | else | |
11625 | as_bad (_("Invalid dsp/smartmips acc register")); | |
11626 | break; | |
11627 | ||
90ecf173 | 11628 | case '&': /* Four DSP accumulators in bits 13,14. */ |
df58fc94 | 11629 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11630 | if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' && |
11631 | s[3] >= '0' && s[3] <= '3') | |
11632 | { | |
11633 | regno = s[3] - '0'; | |
11634 | s += 4; | |
df58fc94 | 11635 | INSERT_OPERAND (0, MTACC_D, *ip, regno); |
ef2e4d86 CF |
11636 | continue; |
11637 | } | |
11638 | else | |
11639 | as_bad (_("Invalid dsp/smartmips acc register")); | |
11640 | break; | |
11641 | ||
dec0624d MR |
11642 | case '\\': /* 3-bit bit position. */ |
11643 | { | |
2906b037 MR |
11644 | unsigned long mask = (mips_opts.micromips |
11645 | ? MICROMIPSOP_MASK_3BITPOS | |
11646 | : OP_MASK_3BITPOS); | |
dec0624d MR |
11647 | |
11648 | my_getExpression (&imm_expr, s); | |
11649 | check_absolute_expr (ip, &imm_expr); | |
11650 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11651 | as_warn (_("Bit position for %s not in range 0..%lu (%lu)"), | |
11652 | ip->insn_mo->name, | |
11653 | mask, (unsigned long) imm_expr.X_add_number); | |
11654 | INSERT_OPERAND (mips_opts.micromips, | |
11655 | 3BITPOS, *ip, imm_expr.X_add_number); | |
11656 | imm_expr.X_op = O_absent; | |
11657 | s = expr_end; | |
11658 | } | |
11659 | continue; | |
11660 | ||
252b5132 | 11661 | case ',': |
a339155f | 11662 | ++argnum; |
252b5132 RH |
11663 | if (*s++ == *args) |
11664 | continue; | |
11665 | s--; | |
11666 | switch (*++args) | |
11667 | { | |
11668 | case 'r': | |
11669 | case 'v': | |
df58fc94 | 11670 | INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno); |
252b5132 RH |
11671 | continue; |
11672 | ||
11673 | case 'w': | |
df58fc94 | 11674 | INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno); |
38487616 TS |
11675 | continue; |
11676 | ||
252b5132 | 11677 | case 'W': |
df58fc94 RS |
11678 | gas_assert (!mips_opts.micromips); |
11679 | INSERT_OPERAND (0, FT, *ip, lastregno); | |
252b5132 RH |
11680 | continue; |
11681 | ||
11682 | case 'V': | |
df58fc94 | 11683 | INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno); |
252b5132 RH |
11684 | continue; |
11685 | } | |
11686 | break; | |
11687 | ||
11688 | case '(': | |
11689 | /* Handle optional base register. | |
11690 | Either the base register is omitted or | |
bdaaa2e1 | 11691 | we must have a left paren. */ |
252b5132 RH |
11692 | /* This is dependent on the next operand specifier |
11693 | is a base register specification. */ | |
df58fc94 RS |
11694 | gas_assert (args[1] == 'b' |
11695 | || (mips_opts.micromips | |
11696 | && args[1] == 'm' | |
11697 | && (args[2] == 'l' || args[2] == 'n' | |
11698 | || args[2] == 's' || args[2] == 'a'))); | |
11699 | if (*s == '\0' && args[1] == 'b') | |
252b5132 | 11700 | return; |
df58fc94 | 11701 | /* Fall through. */ |
252b5132 | 11702 | |
90ecf173 | 11703 | case ')': /* These must match exactly. */ |
df58fc94 RS |
11704 | if (*s++ == *args) |
11705 | continue; | |
11706 | break; | |
11707 | ||
af7ee8bf CD |
11708 | case '+': /* Opcode extension character. */ |
11709 | switch (*++args) | |
11710 | { | |
9bcd4f99 TS |
11711 | case '1': /* UDI immediates. */ |
11712 | case '2': | |
11713 | case '3': | |
11714 | case '4': | |
df58fc94 | 11715 | gas_assert (!mips_opts.micromips); |
9bcd4f99 TS |
11716 | { |
11717 | const struct mips_immed *imm = mips_immed; | |
11718 | ||
11719 | while (imm->type && imm->type != *args) | |
11720 | ++imm; | |
11721 | if (! imm->type) | |
b37df7c4 | 11722 | abort (); |
9bcd4f99 TS |
11723 | my_getExpression (&imm_expr, s); |
11724 | check_absolute_expr (ip, &imm_expr); | |
11725 | if ((unsigned long) imm_expr.X_add_number & ~imm->mask) | |
11726 | { | |
11727 | as_warn (_("Illegal %s number (%lu, 0x%lx)"), | |
11728 | imm->desc ? imm->desc : ip->insn_mo->name, | |
11729 | (unsigned long) imm_expr.X_add_number, | |
11730 | (unsigned long) imm_expr.X_add_number); | |
90ecf173 | 11731 | imm_expr.X_add_number &= imm->mask; |
9bcd4f99 TS |
11732 | } |
11733 | ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number | |
11734 | << imm->shift); | |
11735 | imm_expr.X_op = O_absent; | |
11736 | s = expr_end; | |
11737 | } | |
11738 | continue; | |
90ecf173 | 11739 | |
b015e599 AP |
11740 | case 'J': /* 10-bit hypcall code. */ |
11741 | gas_assert (!mips_opts.micromips); | |
11742 | { | |
11743 | unsigned long mask = OP_MASK_CODE10; | |
11744 | ||
11745 | my_getExpression (&imm_expr, s); | |
11746 | check_absolute_expr (ip, &imm_expr); | |
11747 | if ((unsigned long) imm_expr.X_add_number > mask) | |
11748 | as_warn (_("Code for %s not in range 0..%lu (%lu)"), | |
11749 | ip->insn_mo->name, | |
11750 | mask, (unsigned long) imm_expr.X_add_number); | |
11751 | INSERT_OPERAND (0, CODE10, *ip, imm_expr.X_add_number); | |
11752 | imm_expr.X_op = O_absent; | |
11753 | s = expr_end; | |
11754 | } | |
11755 | continue; | |
11756 | ||
071742cf CD |
11757 | case 'A': /* ins/ext position, becomes LSB. */ |
11758 | limlo = 0; | |
11759 | limhi = 31; | |
5f74bc13 CD |
11760 | goto do_lsb; |
11761 | case 'E': | |
11762 | limlo = 32; | |
11763 | limhi = 63; | |
11764 | goto do_lsb; | |
90ecf173 | 11765 | do_lsb: |
071742cf CD |
11766 | my_getExpression (&imm_expr, s); |
11767 | check_absolute_expr (ip, &imm_expr); | |
11768 | if ((unsigned long) imm_expr.X_add_number < limlo | |
11769 | || (unsigned long) imm_expr.X_add_number > limhi) | |
11770 | { | |
11771 | as_bad (_("Improper position (%lu)"), | |
11772 | (unsigned long) imm_expr.X_add_number); | |
11773 | imm_expr.X_add_number = limlo; | |
11774 | } | |
11775 | lastpos = imm_expr.X_add_number; | |
df58fc94 RS |
11776 | INSERT_OPERAND (mips_opts.micromips, |
11777 | EXTLSB, *ip, imm_expr.X_add_number); | |
071742cf CD |
11778 | imm_expr.X_op = O_absent; |
11779 | s = expr_end; | |
11780 | continue; | |
11781 | ||
11782 | case 'B': /* ins size, becomes MSB. */ | |
11783 | limlo = 1; | |
11784 | limhi = 32; | |
5f74bc13 CD |
11785 | goto do_msb; |
11786 | case 'F': | |
11787 | limlo = 33; | |
11788 | limhi = 64; | |
11789 | goto do_msb; | |
90ecf173 | 11790 | do_msb: |
071742cf CD |
11791 | my_getExpression (&imm_expr, s); |
11792 | check_absolute_expr (ip, &imm_expr); | |
11793 | /* Check for negative input so that small negative numbers | |
11794 | will not succeed incorrectly. The checks against | |
11795 | (pos+size) transitively check "size" itself, | |
11796 | assuming that "pos" is reasonable. */ | |
11797 | if ((long) imm_expr.X_add_number < 0 | |
11798 | || ((unsigned long) imm_expr.X_add_number | |
11799 | + lastpos) < limlo | |
11800 | || ((unsigned long) imm_expr.X_add_number | |
11801 | + lastpos) > limhi) | |
11802 | { | |
11803 | as_bad (_("Improper insert size (%lu, position %lu)"), | |
11804 | (unsigned long) imm_expr.X_add_number, | |
11805 | (unsigned long) lastpos); | |
11806 | imm_expr.X_add_number = limlo - lastpos; | |
11807 | } | |
df58fc94 RS |
11808 | INSERT_OPERAND (mips_opts.micromips, INSMSB, *ip, |
11809 | lastpos + imm_expr.X_add_number - 1); | |
071742cf CD |
11810 | imm_expr.X_op = O_absent; |
11811 | s = expr_end; | |
11812 | continue; | |
11813 | ||
11814 | case 'C': /* ext size, becomes MSBD. */ | |
11815 | limlo = 1; | |
11816 | limhi = 32; | |
f02d8318 | 11817 | sizelo = 1; |
5f74bc13 CD |
11818 | goto do_msbd; |
11819 | case 'G': | |
11820 | limlo = 33; | |
11821 | limhi = 64; | |
f02d8318 | 11822 | sizelo = 33; |
5f74bc13 CD |
11823 | goto do_msbd; |
11824 | case 'H': | |
11825 | limlo = 33; | |
11826 | limhi = 64; | |
f02d8318 | 11827 | sizelo = 1; |
5f74bc13 | 11828 | goto do_msbd; |
90ecf173 | 11829 | do_msbd: |
071742cf CD |
11830 | my_getExpression (&imm_expr, s); |
11831 | check_absolute_expr (ip, &imm_expr); | |
f02d8318 CF |
11832 | /* The checks against (pos+size) don't transitively check |
11833 | "size" itself, assuming that "pos" is reasonable. | |
11834 | We also need to check the lower bound of "size". */ | |
11835 | if ((long) imm_expr.X_add_number < sizelo | |
071742cf CD |
11836 | || ((unsigned long) imm_expr.X_add_number |
11837 | + lastpos) < limlo | |
11838 | || ((unsigned long) imm_expr.X_add_number | |
11839 | + lastpos) > limhi) | |
11840 | { | |
11841 | as_bad (_("Improper extract size (%lu, position %lu)"), | |
11842 | (unsigned long) imm_expr.X_add_number, | |
11843 | (unsigned long) lastpos); | |
11844 | imm_expr.X_add_number = limlo - lastpos; | |
11845 | } | |
df58fc94 RS |
11846 | INSERT_OPERAND (mips_opts.micromips, |
11847 | EXTMSBD, *ip, imm_expr.X_add_number - 1); | |
071742cf CD |
11848 | imm_expr.X_op = O_absent; |
11849 | s = expr_end; | |
11850 | continue; | |
af7ee8bf | 11851 | |
5f74bc13 CD |
11852 | case 'I': |
11853 | /* "+I" is like "I", except that imm2_expr is used. */ | |
11854 | my_getExpression (&imm2_expr, s); | |
11855 | if (imm2_expr.X_op != O_big | |
11856 | && imm2_expr.X_op != O_constant) | |
11857 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
11858 | if (HAVE_32BIT_GPRS) |
11859 | normalize_constant_expr (&imm2_expr); | |
5f74bc13 CD |
11860 | s = expr_end; |
11861 | continue; | |
11862 | ||
707bfff6 | 11863 | case 't': /* Coprocessor register number. */ |
df58fc94 | 11864 | gas_assert (!mips_opts.micromips); |
ef2e4d86 CF |
11865 | if (s[0] == '$' && ISDIGIT (s[1])) |
11866 | { | |
11867 | ++s; | |
11868 | regno = 0; | |
11869 | do | |
11870 | { | |
11871 | regno *= 10; | |
11872 | regno += *s - '0'; | |
11873 | ++s; | |
11874 | } | |
11875 | while (ISDIGIT (*s)); | |
11876 | if (regno > 31) | |
11877 | as_bad (_("Invalid register number (%d)"), regno); | |
11878 | else | |
11879 | { | |
df58fc94 | 11880 | INSERT_OPERAND (0, RT, *ip, regno); |
ef2e4d86 CF |
11881 | continue; |
11882 | } | |
11883 | } | |
11884 | else | |
11885 | as_bad (_("Invalid coprocessor 0 register number")); | |
11886 | break; | |
11887 | ||
bb35fb24 NC |
11888 | case 'x': |
11889 | /* bbit[01] and bbit[01]32 bit index. Give error if index | |
11890 | is not in the valid range. */ | |
df58fc94 | 11891 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11892 | my_getExpression (&imm_expr, s); |
11893 | check_absolute_expr (ip, &imm_expr); | |
11894 | if ((unsigned) imm_expr.X_add_number > 31) | |
11895 | { | |
11896 | as_bad (_("Improper bit index (%lu)"), | |
11897 | (unsigned long) imm_expr.X_add_number); | |
11898 | imm_expr.X_add_number = 0; | |
11899 | } | |
df58fc94 | 11900 | INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11901 | imm_expr.X_op = O_absent; |
11902 | s = expr_end; | |
11903 | continue; | |
11904 | ||
11905 | case 'X': | |
11906 | /* bbit[01] bit index when bbit is used but we generate | |
11907 | bbit[01]32 because the index is over 32. Move to the | |
11908 | next candidate if index is not in the valid range. */ | |
df58fc94 | 11909 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11910 | my_getExpression (&imm_expr, s); |
11911 | check_absolute_expr (ip, &imm_expr); | |
11912 | if ((unsigned) imm_expr.X_add_number < 32 | |
11913 | || (unsigned) imm_expr.X_add_number > 63) | |
11914 | break; | |
df58fc94 | 11915 | INSERT_OPERAND (0, BBITIND, *ip, imm_expr.X_add_number - 32); |
bb35fb24 NC |
11916 | imm_expr.X_op = O_absent; |
11917 | s = expr_end; | |
11918 | continue; | |
11919 | ||
11920 | case 'p': | |
11921 | /* cins, cins32, exts and exts32 position field. Give error | |
11922 | if it's not in the valid range. */ | |
df58fc94 | 11923 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11924 | my_getExpression (&imm_expr, s); |
11925 | check_absolute_expr (ip, &imm_expr); | |
11926 | if ((unsigned) imm_expr.X_add_number > 31) | |
11927 | { | |
11928 | as_bad (_("Improper position (%lu)"), | |
11929 | (unsigned long) imm_expr.X_add_number); | |
11930 | imm_expr.X_add_number = 0; | |
11931 | } | |
23e69e47 | 11932 | lastpos = imm_expr.X_add_number; |
df58fc94 | 11933 | INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11934 | imm_expr.X_op = O_absent; |
11935 | s = expr_end; | |
11936 | continue; | |
11937 | ||
11938 | case 'P': | |
11939 | /* cins, cins32, exts and exts32 position field. Move to | |
11940 | the next candidate if it's not in the valid range. */ | |
df58fc94 | 11941 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11942 | my_getExpression (&imm_expr, s); |
11943 | check_absolute_expr (ip, &imm_expr); | |
11944 | if ((unsigned) imm_expr.X_add_number < 32 | |
11945 | || (unsigned) imm_expr.X_add_number > 63) | |
11946 | break; | |
11947 | lastpos = imm_expr.X_add_number; | |
df58fc94 | 11948 | INSERT_OPERAND (0, CINSPOS, *ip, imm_expr.X_add_number - 32); |
bb35fb24 NC |
11949 | imm_expr.X_op = O_absent; |
11950 | s = expr_end; | |
11951 | continue; | |
11952 | ||
11953 | case 's': | |
23e69e47 | 11954 | /* cins32 and exts32 length-minus-one field. */ |
df58fc94 | 11955 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11956 | my_getExpression (&imm_expr, s); |
11957 | check_absolute_expr (ip, &imm_expr); | |
23e69e47 RS |
11958 | if ((unsigned long) imm_expr.X_add_number > 31 |
11959 | || (unsigned long) imm_expr.X_add_number + lastpos > 31) | |
bb35fb24 NC |
11960 | { |
11961 | as_bad (_("Improper size (%lu)"), | |
11962 | (unsigned long) imm_expr.X_add_number); | |
11963 | imm_expr.X_add_number = 0; | |
11964 | } | |
df58fc94 | 11965 | INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11966 | imm_expr.X_op = O_absent; |
11967 | s = expr_end; | |
11968 | continue; | |
11969 | ||
11970 | case 'S': | |
23e69e47 | 11971 | /* cins/exts length-minus-one field. */ |
df58fc94 | 11972 | gas_assert (!mips_opts.micromips); |
bb35fb24 NC |
11973 | my_getExpression (&imm_expr, s); |
11974 | check_absolute_expr (ip, &imm_expr); | |
23e69e47 | 11975 | if ((unsigned long) imm_expr.X_add_number > 31 |
bb35fb24 NC |
11976 | || (unsigned long) imm_expr.X_add_number + lastpos > 63) |
11977 | { | |
11978 | as_bad (_("Improper size (%lu)"), | |
11979 | (unsigned long) imm_expr.X_add_number); | |
11980 | imm_expr.X_add_number = 0; | |
11981 | } | |
df58fc94 | 11982 | INSERT_OPERAND (0, CINSLM1, *ip, imm_expr.X_add_number); |
bb35fb24 NC |
11983 | imm_expr.X_op = O_absent; |
11984 | s = expr_end; | |
11985 | continue; | |
11986 | ||
dd3cbb7e NC |
11987 | case 'Q': |
11988 | /* seqi/snei immediate field. */ | |
df58fc94 | 11989 | gas_assert (!mips_opts.micromips); |
dd3cbb7e NC |
11990 | my_getExpression (&imm_expr, s); |
11991 | check_absolute_expr (ip, &imm_expr); | |
11992 | if ((long) imm_expr.X_add_number < -512 | |
11993 | || (long) imm_expr.X_add_number >= 512) | |
11994 | { | |
11995 | as_bad (_("Improper immediate (%ld)"), | |
11996 | (long) imm_expr.X_add_number); | |
11997 | imm_expr.X_add_number = 0; | |
11998 | } | |
df58fc94 | 11999 | INSERT_OPERAND (0, SEQI, *ip, imm_expr.X_add_number); |
dd3cbb7e NC |
12000 | imm_expr.X_op = O_absent; |
12001 | s = expr_end; | |
12002 | continue; | |
12003 | ||
98675402 | 12004 | case 'a': /* 8-bit signed offset in bit 6 */ |
df58fc94 | 12005 | gas_assert (!mips_opts.micromips); |
98675402 RS |
12006 | my_getExpression (&imm_expr, s); |
12007 | check_absolute_expr (ip, &imm_expr); | |
12008 | min_range = -((OP_MASK_OFFSET_A + 1) >> 1); | |
12009 | max_range = ((OP_MASK_OFFSET_A + 1) >> 1) - 1; | |
12010 | if (imm_expr.X_add_number < min_range | |
12011 | || imm_expr.X_add_number > max_range) | |
12012 | { | |
c95354ed | 12013 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
12014 | (long) min_range, (long) max_range, |
12015 | (long) imm_expr.X_add_number); | |
12016 | } | |
df58fc94 | 12017 | INSERT_OPERAND (0, OFFSET_A, *ip, imm_expr.X_add_number); |
98675402 RS |
12018 | imm_expr.X_op = O_absent; |
12019 | s = expr_end; | |
12020 | continue; | |
12021 | ||
12022 | case 'b': /* 8-bit signed offset in bit 3 */ | |
df58fc94 | 12023 | gas_assert (!mips_opts.micromips); |
98675402 RS |
12024 | my_getExpression (&imm_expr, s); |
12025 | check_absolute_expr (ip, &imm_expr); | |
12026 | min_range = -((OP_MASK_OFFSET_B + 1) >> 1); | |
12027 | max_range = ((OP_MASK_OFFSET_B + 1) >> 1) - 1; | |
12028 | if (imm_expr.X_add_number < min_range | |
12029 | || imm_expr.X_add_number > max_range) | |
12030 | { | |
c95354ed | 12031 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
12032 | (long) min_range, (long) max_range, |
12033 | (long) imm_expr.X_add_number); | |
12034 | } | |
df58fc94 | 12035 | INSERT_OPERAND (0, OFFSET_B, *ip, imm_expr.X_add_number); |
98675402 RS |
12036 | imm_expr.X_op = O_absent; |
12037 | s = expr_end; | |
12038 | continue; | |
12039 | ||
12040 | case 'c': /* 9-bit signed offset in bit 6 */ | |
df58fc94 | 12041 | gas_assert (!mips_opts.micromips); |
98675402 RS |
12042 | my_getExpression (&imm_expr, s); |
12043 | check_absolute_expr (ip, &imm_expr); | |
12044 | min_range = -((OP_MASK_OFFSET_C + 1) >> 1); | |
12045 | max_range = ((OP_MASK_OFFSET_C + 1) >> 1) - 1; | |
c95354ed MX |
12046 | /* We check the offset range before adjusted. */ |
12047 | min_range <<= 4; | |
12048 | max_range <<= 4; | |
98675402 RS |
12049 | if (imm_expr.X_add_number < min_range |
12050 | || imm_expr.X_add_number > max_range) | |
12051 | { | |
c95354ed | 12052 | as_bad (_("Offset not in range %ld..%ld (%ld)"), |
98675402 RS |
12053 | (long) min_range, (long) max_range, |
12054 | (long) imm_expr.X_add_number); | |
12055 | } | |
c95354ed MX |
12056 | if (imm_expr.X_add_number & 0xf) |
12057 | { | |
12058 | as_bad (_("Offset not 16 bytes alignment (%ld)"), | |
12059 | (long) imm_expr.X_add_number); | |
12060 | } | |
12061 | /* Right shift 4 bits to adjust the offset operand. */ | |
df58fc94 RS |
12062 | INSERT_OPERAND (0, OFFSET_C, *ip, |
12063 | imm_expr.X_add_number >> 4); | |
98675402 RS |
12064 | imm_expr.X_op = O_absent; |
12065 | s = expr_end; | |
12066 | continue; | |
12067 | ||
12068 | case 'z': | |
df58fc94 | 12069 | gas_assert (!mips_opts.micromips); |
98675402 RS |
12070 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) |
12071 | break; | |
12072 | if (regno == AT && mips_opts.at) | |
12073 | { | |
12074 | if (mips_opts.at == ATREG) | |
12075 | as_warn (_("used $at without \".set noat\"")); | |
12076 | else | |
12077 | as_warn (_("used $%u with \".set at=$%u\""), | |
12078 | regno, mips_opts.at); | |
12079 | } | |
df58fc94 | 12080 | INSERT_OPERAND (0, RZ, *ip, regno); |
98675402 RS |
12081 | continue; |
12082 | ||
12083 | case 'Z': | |
df58fc94 | 12084 | gas_assert (!mips_opts.micromips); |
98675402 RS |
12085 | if (!reg_lookup (&s, RTYPE_FPU, ®no)) |
12086 | break; | |
df58fc94 | 12087 | INSERT_OPERAND (0, FZ, *ip, regno); |
98675402 RS |
12088 | continue; |
12089 | ||
27c5c572 RS |
12090 | case 'i': |
12091 | goto jump; | |
12092 | ||
7f3c4072 CM |
12093 | case 'j': |
12094 | { | |
12095 | int shift = 8; | |
12096 | size_t i; | |
77bd4346 RS |
12097 | bfd_reloc_code_real_type r[3]; |
12098 | ||
7f3c4072 CM |
12099 | /* Check whether there is only a single bracketed expression |
12100 | left. If so, it must be the base register and the | |
12101 | constant must be zero. */ | |
12102 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12103 | continue; | |
12104 | ||
12105 | /* If this value won't fit into the offset, then go find | |
12106 | a macro that will generate a 16- or 32-bit offset code | |
12107 | pattern. */ | |
77bd4346 | 12108 | i = my_getSmallExpression (&imm_expr, r, s); |
7f3c4072 CM |
12109 | if ((i == 0 && (imm_expr.X_op != O_constant |
12110 | || imm_expr.X_add_number >= 1 << shift | |
12111 | || imm_expr.X_add_number < -1 << shift)) | |
12112 | || i > 0) | |
12113 | { | |
12114 | imm_expr.X_op = O_absent; | |
12115 | break; | |
12116 | } | |
12117 | INSERT_OPERAND (mips_opts.micromips, EVAOFFSET, *ip, | |
12118 | imm_expr.X_add_number); | |
12119 | imm_expr.X_op = O_absent; | |
12120 | s = expr_end; | |
12121 | } | |
12122 | continue; | |
12123 | ||
af7ee8bf | 12124 | default: |
df58fc94 | 12125 | as_bad (_("Internal error: bad %s opcode " |
90ecf173 | 12126 | "(unknown extension operand type `+%c'): %s %s"), |
df58fc94 | 12127 | mips_opts.micromips ? "microMIPS" : "MIPS", |
90ecf173 | 12128 | *args, insn->name, insn->args); |
af7ee8bf CD |
12129 | /* Further processing is fruitless. */ |
12130 | return; | |
12131 | } | |
12132 | break; | |
12133 | ||
df58fc94 | 12134 | case '.': /* 10-bit offset. */ |
df58fc94 | 12135 | gas_assert (mips_opts.micromips); |
dec0624d | 12136 | case '~': /* 12-bit offset. */ |
df58fc94 RS |
12137 | { |
12138 | int shift = *args == '.' ? 9 : 11; | |
12139 | size_t i; | |
77bd4346 | 12140 | bfd_reloc_code_real_type r[3]; |
df58fc94 RS |
12141 | |
12142 | /* Check whether there is only a single bracketed expression | |
12143 | left. If so, it must be the base register and the | |
12144 | constant must be zero. */ | |
12145 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12146 | continue; | |
12147 | ||
12148 | /* If this value won't fit into the offset, then go find | |
12149 | a macro that will generate a 16- or 32-bit offset code | |
12150 | pattern. */ | |
77bd4346 | 12151 | i = my_getSmallExpression (&imm_expr, r, s); |
df58fc94 RS |
12152 | if ((i == 0 && (imm_expr.X_op != O_constant |
12153 | || imm_expr.X_add_number >= 1 << shift | |
12154 | || imm_expr.X_add_number < -1 << shift)) | |
12155 | || i > 0) | |
12156 | { | |
12157 | imm_expr.X_op = O_absent; | |
12158 | break; | |
12159 | } | |
12160 | if (shift == 9) | |
12161 | INSERT_OPERAND (1, OFFSET10, *ip, imm_expr.X_add_number); | |
12162 | else | |
dec0624d MR |
12163 | INSERT_OPERAND (mips_opts.micromips, |
12164 | OFFSET12, *ip, imm_expr.X_add_number); | |
df58fc94 RS |
12165 | imm_expr.X_op = O_absent; |
12166 | s = expr_end; | |
12167 | } | |
12168 | continue; | |
12169 | ||
252b5132 RH |
12170 | case '<': /* must be at least one digit */ |
12171 | /* | |
12172 | * According to the manual, if the shift amount is greater | |
b6ff326e KH |
12173 | * than 31 or less than 0, then the shift amount should be |
12174 | * mod 32. In reality the mips assembler issues an error. | |
252b5132 RH |
12175 | * We issue a warning and mask out all but the low 5 bits. |
12176 | */ | |
12177 | my_getExpression (&imm_expr, s); | |
12178 | check_absolute_expr (ip, &imm_expr); | |
12179 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
12180 | as_warn (_("Improper shift amount (%lu)"), |
12181 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 RS |
12182 | INSERT_OPERAND (mips_opts.micromips, |
12183 | SHAMT, *ip, imm_expr.X_add_number); | |
252b5132 RH |
12184 | imm_expr.X_op = O_absent; |
12185 | s = expr_end; | |
12186 | continue; | |
12187 | ||
12188 | case '>': /* shift amount minus 32 */ | |
12189 | my_getExpression (&imm_expr, s); | |
12190 | check_absolute_expr (ip, &imm_expr); | |
12191 | if ((unsigned long) imm_expr.X_add_number < 32 | |
12192 | || (unsigned long) imm_expr.X_add_number > 63) | |
12193 | break; | |
df58fc94 RS |
12194 | INSERT_OPERAND (mips_opts.micromips, |
12195 | SHAMT, *ip, imm_expr.X_add_number - 32); | |
252b5132 RH |
12196 | imm_expr.X_op = O_absent; |
12197 | s = expr_end; | |
12198 | continue; | |
12199 | ||
90ecf173 MR |
12200 | case 'k': /* CACHE code. */ |
12201 | case 'h': /* PREFX code. */ | |
12202 | case '1': /* SYNC type. */ | |
252b5132 RH |
12203 | my_getExpression (&imm_expr, s); |
12204 | check_absolute_expr (ip, &imm_expr); | |
12205 | if ((unsigned long) imm_expr.X_add_number > 31) | |
bf12938e RS |
12206 | as_warn (_("Invalid value for `%s' (%lu)"), |
12207 | ip->insn_mo->name, | |
12208 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 12209 | switch (*args) |
d954098f | 12210 | { |
df58fc94 RS |
12211 | case 'k': |
12212 | if (mips_fix_cn63xxp1 | |
12213 | && !mips_opts.micromips | |
12214 | && strcmp ("pref", insn->name) == 0) | |
d954098f DD |
12215 | switch (imm_expr.X_add_number) |
12216 | { | |
12217 | case 5: | |
12218 | case 25: | |
12219 | case 26: | |
12220 | case 27: | |
12221 | case 28: | |
12222 | case 29: | |
12223 | case 30: | |
12224 | case 31: /* These are ok. */ | |
12225 | break; | |
12226 | ||
12227 | default: /* The rest must be changed to 28. */ | |
12228 | imm_expr.X_add_number = 28; | |
12229 | break; | |
12230 | } | |
df58fc94 RS |
12231 | INSERT_OPERAND (mips_opts.micromips, |
12232 | CACHE, *ip, imm_expr.X_add_number); | |
12233 | break; | |
12234 | case 'h': | |
12235 | INSERT_OPERAND (mips_opts.micromips, | |
12236 | PREFX, *ip, imm_expr.X_add_number); | |
12237 | break; | |
12238 | case '1': | |
12239 | INSERT_OPERAND (mips_opts.micromips, | |
12240 | STYPE, *ip, imm_expr.X_add_number); | |
12241 | break; | |
d954098f | 12242 | } |
252b5132 RH |
12243 | imm_expr.X_op = O_absent; |
12244 | s = expr_end; | |
12245 | continue; | |
12246 | ||
90ecf173 | 12247 | case 'c': /* BREAK code. */ |
df58fc94 RS |
12248 | { |
12249 | unsigned long mask = (mips_opts.micromips | |
12250 | ? MICROMIPSOP_MASK_CODE | |
12251 | : OP_MASK_CODE); | |
12252 | ||
12253 | my_getExpression (&imm_expr, s); | |
12254 | check_absolute_expr (ip, &imm_expr); | |
12255 | if ((unsigned long) imm_expr.X_add_number > mask) | |
12256 | as_warn (_("Code for %s not in range 0..%lu (%lu)"), | |
12257 | ip->insn_mo->name, | |
12258 | mask, (unsigned long) imm_expr.X_add_number); | |
12259 | INSERT_OPERAND (mips_opts.micromips, | |
12260 | CODE, *ip, imm_expr.X_add_number); | |
12261 | imm_expr.X_op = O_absent; | |
12262 | s = expr_end; | |
12263 | } | |
252b5132 RH |
12264 | continue; |
12265 | ||
90ecf173 | 12266 | case 'q': /* Lower BREAK code. */ |
df58fc94 RS |
12267 | { |
12268 | unsigned long mask = (mips_opts.micromips | |
12269 | ? MICROMIPSOP_MASK_CODE2 | |
12270 | : OP_MASK_CODE2); | |
12271 | ||
12272 | my_getExpression (&imm_expr, s); | |
12273 | check_absolute_expr (ip, &imm_expr); | |
12274 | if ((unsigned long) imm_expr.X_add_number > mask) | |
12275 | as_warn (_("Lower code for %s not in range 0..%lu (%lu)"), | |
12276 | ip->insn_mo->name, | |
12277 | mask, (unsigned long) imm_expr.X_add_number); | |
12278 | INSERT_OPERAND (mips_opts.micromips, | |
12279 | CODE2, *ip, imm_expr.X_add_number); | |
12280 | imm_expr.X_op = O_absent; | |
12281 | s = expr_end; | |
12282 | } | |
252b5132 RH |
12283 | continue; |
12284 | ||
df58fc94 RS |
12285 | case 'B': /* 20- or 10-bit syscall/break/wait code. */ |
12286 | { | |
12287 | unsigned long mask = (mips_opts.micromips | |
12288 | ? MICROMIPSOP_MASK_CODE10 | |
12289 | : OP_MASK_CODE20); | |
12290 | ||
12291 | my_getExpression (&imm_expr, s); | |
12292 | check_absolute_expr (ip, &imm_expr); | |
12293 | if ((unsigned long) imm_expr.X_add_number > mask) | |
12294 | as_warn (_("Code for %s not in range 0..%lu (%lu)"), | |
12295 | ip->insn_mo->name, | |
12296 | mask, (unsigned long) imm_expr.X_add_number); | |
12297 | if (mips_opts.micromips) | |
12298 | INSERT_OPERAND (1, CODE10, *ip, imm_expr.X_add_number); | |
12299 | else | |
12300 | INSERT_OPERAND (0, CODE20, *ip, imm_expr.X_add_number); | |
12301 | imm_expr.X_op = O_absent; | |
12302 | s = expr_end; | |
12303 | } | |
252b5132 RH |
12304 | continue; |
12305 | ||
df58fc94 RS |
12306 | case 'C': /* 25- or 23-bit coprocessor code. */ |
12307 | { | |
12308 | unsigned long mask = (mips_opts.micromips | |
12309 | ? MICROMIPSOP_MASK_COPZ | |
12310 | : OP_MASK_COPZ); | |
12311 | ||
12312 | my_getExpression (&imm_expr, s); | |
12313 | check_absolute_expr (ip, &imm_expr); | |
12314 | if ((unsigned long) imm_expr.X_add_number > mask) | |
12315 | as_warn (_("Coproccesor code > %u bits (%lu)"), | |
12316 | mips_opts.micromips ? 23U : 25U, | |
793b27f4 | 12317 | (unsigned long) imm_expr.X_add_number); |
df58fc94 RS |
12318 | INSERT_OPERAND (mips_opts.micromips, |
12319 | COPZ, *ip, imm_expr.X_add_number); | |
12320 | imm_expr.X_op = O_absent; | |
12321 | s = expr_end; | |
12322 | } | |
beae10d5 | 12323 | continue; |
252b5132 | 12324 | |
df58fc94 RS |
12325 | case 'J': /* 19-bit WAIT code. */ |
12326 | gas_assert (!mips_opts.micromips); | |
4372b673 NC |
12327 | my_getExpression (&imm_expr, s); |
12328 | check_absolute_expr (ip, &imm_expr); | |
793b27f4 | 12329 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) |
df58fc94 RS |
12330 | { |
12331 | as_warn (_("Illegal 19-bit code (%lu)"), | |
a9e24354 | 12332 | (unsigned long) imm_expr.X_add_number); |
df58fc94 RS |
12333 | imm_expr.X_add_number &= OP_MASK_CODE19; |
12334 | } | |
12335 | INSERT_OPERAND (0, CODE19, *ip, imm_expr.X_add_number); | |
4372b673 NC |
12336 | imm_expr.X_op = O_absent; |
12337 | s = expr_end; | |
12338 | continue; | |
12339 | ||
707bfff6 | 12340 | case 'P': /* Performance register. */ |
df58fc94 | 12341 | gas_assert (!mips_opts.micromips); |
beae10d5 | 12342 | my_getExpression (&imm_expr, s); |
252b5132 | 12343 | check_absolute_expr (ip, &imm_expr); |
beae10d5 | 12344 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
bf12938e RS |
12345 | as_warn (_("Invalid performance register (%lu)"), |
12346 | (unsigned long) imm_expr.X_add_number); | |
e407c74b NC |
12347 | if (imm_expr.X_add_number != 0 && mips_opts.arch == CPU_R5900 |
12348 | && (!strcmp(insn->name,"mfps") || !strcmp(insn->name,"mtps"))) | |
12349 | as_warn (_("Invalid performance register (%lu)"), | |
12350 | (unsigned long) imm_expr.X_add_number); | |
df58fc94 | 12351 | INSERT_OPERAND (0, PERFREG, *ip, imm_expr.X_add_number); |
beae10d5 KH |
12352 | imm_expr.X_op = O_absent; |
12353 | s = expr_end; | |
12354 | continue; | |
252b5132 | 12355 | |
707bfff6 | 12356 | case 'G': /* Coprocessor destination register. */ |
df58fc94 RS |
12357 | { |
12358 | unsigned long opcode = ip->insn_opcode; | |
12359 | unsigned long mask; | |
12360 | unsigned int types; | |
12361 | int cop0; | |
12362 | ||
12363 | if (mips_opts.micromips) | |
12364 | { | |
12365 | mask = ~((MICROMIPSOP_MASK_RT << MICROMIPSOP_SH_RT) | |
12366 | | (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS) | |
12367 | | (MICROMIPSOP_MASK_SEL << MICROMIPSOP_SH_SEL)); | |
12368 | opcode &= mask; | |
12369 | switch (opcode) | |
12370 | { | |
12371 | case 0x000000fc: /* mfc0 */ | |
12372 | case 0x000002fc: /* mtc0 */ | |
12373 | case 0x580000fc: /* dmfc0 */ | |
12374 | case 0x580002fc: /* dmtc0 */ | |
12375 | cop0 = 1; | |
12376 | break; | |
12377 | default: | |
12378 | cop0 = 0; | |
12379 | break; | |
12380 | } | |
12381 | } | |
12382 | else | |
12383 | { | |
12384 | opcode = (opcode >> OP_SH_OP) & OP_MASK_OP; | |
12385 | cop0 = opcode == OP_OP_COP0; | |
12386 | } | |
12387 | types = RTYPE_NUM | (cop0 ? RTYPE_CP0 : RTYPE_GP); | |
12388 | ok = reg_lookup (&s, types, ®no); | |
12389 | if (mips_opts.micromips) | |
12390 | INSERT_OPERAND (1, RS, *ip, regno); | |
12391 | else | |
12392 | INSERT_OPERAND (0, RD, *ip, regno); | |
12393 | if (ok) | |
12394 | { | |
12395 | lastregno = regno; | |
12396 | continue; | |
12397 | } | |
12398 | } | |
12399 | break; | |
707bfff6 | 12400 | |
df58fc94 RS |
12401 | case 'y': /* ALNV.PS source register. */ |
12402 | gas_assert (mips_opts.micromips); | |
12403 | goto do_reg; | |
12404 | case 'x': /* Ignore register name. */ | |
12405 | case 'U': /* Destination register (CLO/CLZ). */ | |
12406 | case 'g': /* Coprocessor destination register. */ | |
12407 | gas_assert (!mips_opts.micromips); | |
90ecf173 MR |
12408 | case 'b': /* Base register. */ |
12409 | case 'd': /* Destination register. */ | |
12410 | case 's': /* Source register. */ | |
12411 | case 't': /* Target register. */ | |
12412 | case 'r': /* Both target and source. */ | |
12413 | case 'v': /* Both dest and source. */ | |
12414 | case 'w': /* Both dest and target. */ | |
12415 | case 'E': /* Coprocessor target register. */ | |
12416 | case 'K': /* RDHWR destination register. */ | |
90ecf173 | 12417 | case 'z': /* Must be zero register. */ |
df58fc94 | 12418 | do_reg: |
90ecf173 | 12419 | s_reset = s; |
707bfff6 TS |
12420 | if (*args == 'E' || *args == 'K') |
12421 | ok = reg_lookup (&s, RTYPE_NUM, ®no); | |
12422 | else | |
12423 | { | |
12424 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
741fe287 MR |
12425 | if (regno == AT && mips_opts.at) |
12426 | { | |
12427 | if (mips_opts.at == ATREG) | |
f71d0d44 | 12428 | as_warn (_("Used $at without \".set noat\"")); |
741fe287 | 12429 | else |
f71d0d44 | 12430 | as_warn (_("Used $%u with \".set at=$%u\""), |
741fe287 MR |
12431 | regno, mips_opts.at); |
12432 | } | |
707bfff6 TS |
12433 | } |
12434 | if (ok) | |
252b5132 | 12435 | { |
252b5132 RH |
12436 | c = *args; |
12437 | if (*s == ' ') | |
f9419b05 | 12438 | ++s; |
252b5132 RH |
12439 | if (args[1] != *s) |
12440 | { | |
12441 | if (c == 'r' || c == 'v' || c == 'w') | |
12442 | { | |
12443 | regno = lastregno; | |
12444 | s = s_reset; | |
f9419b05 | 12445 | ++args; |
252b5132 RH |
12446 | } |
12447 | } | |
12448 | /* 'z' only matches $0. */ | |
12449 | if (c == 'z' && regno != 0) | |
12450 | break; | |
12451 | ||
24864476 | 12452 | if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4)) |
e7c604dd CM |
12453 | { |
12454 | if (regno == lastregno) | |
90ecf173 MR |
12455 | { |
12456 | insn_error | |
f71d0d44 | 12457 | = _("Source and destination must be different"); |
e7c604dd | 12458 | continue; |
90ecf173 | 12459 | } |
24864476 | 12460 | if (regno == 31 && lastregno == 0xffffffff) |
90ecf173 MR |
12461 | { |
12462 | insn_error | |
f71d0d44 | 12463 | = _("A destination register must be supplied"); |
e7c604dd | 12464 | continue; |
90ecf173 | 12465 | } |
e7c604dd | 12466 | } |
90ecf173 MR |
12467 | /* Now that we have assembled one operand, we use the args |
12468 | string to figure out where it goes in the instruction. */ | |
252b5132 RH |
12469 | switch (c) |
12470 | { | |
12471 | case 'r': | |
12472 | case 's': | |
12473 | case 'v': | |
12474 | case 'b': | |
df58fc94 | 12475 | INSERT_OPERAND (mips_opts.micromips, RS, *ip, regno); |
252b5132 | 12476 | break; |
df58fc94 | 12477 | |
af7ee8bf | 12478 | case 'K': |
df58fc94 RS |
12479 | if (mips_opts.micromips) |
12480 | INSERT_OPERAND (1, RS, *ip, regno); | |
12481 | else | |
12482 | INSERT_OPERAND (0, RD, *ip, regno); | |
12483 | break; | |
12484 | ||
12485 | case 'd': | |
ef2e4d86 | 12486 | case 'g': |
df58fc94 | 12487 | INSERT_OPERAND (mips_opts.micromips, RD, *ip, regno); |
252b5132 | 12488 | break; |
df58fc94 | 12489 | |
4372b673 | 12490 | case 'U': |
df58fc94 RS |
12491 | gas_assert (!mips_opts.micromips); |
12492 | INSERT_OPERAND (0, RD, *ip, regno); | |
12493 | INSERT_OPERAND (0, RT, *ip, regno); | |
4372b673 | 12494 | break; |
df58fc94 | 12495 | |
252b5132 RH |
12496 | case 'w': |
12497 | case 't': | |
12498 | case 'E': | |
df58fc94 RS |
12499 | INSERT_OPERAND (mips_opts.micromips, RT, *ip, regno); |
12500 | break; | |
12501 | ||
12502 | case 'y': | |
12503 | gas_assert (mips_opts.micromips); | |
12504 | INSERT_OPERAND (1, RS3, *ip, regno); | |
252b5132 | 12505 | break; |
df58fc94 | 12506 | |
252b5132 RH |
12507 | case 'x': |
12508 | /* This case exists because on the r3000 trunc | |
12509 | expands into a macro which requires a gp | |
12510 | register. On the r6000 or r4000 it is | |
12511 | assembled into a single instruction which | |
12512 | ignores the register. Thus the insn version | |
12513 | is MIPS_ISA2 and uses 'x', and the macro | |
12514 | version is MIPS_ISA1 and uses 't'. */ | |
12515 | break; | |
df58fc94 | 12516 | |
252b5132 RH |
12517 | case 'z': |
12518 | /* This case is for the div instruction, which | |
12519 | acts differently if the destination argument | |
12520 | is $0. This only matches $0, and is checked | |
12521 | outside the switch. */ | |
12522 | break; | |
252b5132 RH |
12523 | } |
12524 | lastregno = regno; | |
12525 | continue; | |
12526 | } | |
252b5132 RH |
12527 | switch (*args++) |
12528 | { | |
12529 | case 'r': | |
12530 | case 'v': | |
df58fc94 | 12531 | INSERT_OPERAND (mips_opts.micromips, RS, *ip, lastregno); |
252b5132 | 12532 | continue; |
df58fc94 | 12533 | |
252b5132 | 12534 | case 'w': |
df58fc94 | 12535 | INSERT_OPERAND (mips_opts.micromips, RT, *ip, lastregno); |
252b5132 RH |
12536 | continue; |
12537 | } | |
12538 | break; | |
12539 | ||
deec1734 | 12540 | case 'O': /* MDMX alignment immediate constant. */ |
df58fc94 | 12541 | gas_assert (!mips_opts.micromips); |
deec1734 CD |
12542 | my_getExpression (&imm_expr, s); |
12543 | check_absolute_expr (ip, &imm_expr); | |
12544 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) | |
20203fb9 | 12545 | as_warn (_("Improper align amount (%ld), using low bits"), |
bf12938e | 12546 | (long) imm_expr.X_add_number); |
df58fc94 | 12547 | INSERT_OPERAND (0, ALN, *ip, imm_expr.X_add_number); |
deec1734 CD |
12548 | imm_expr.X_op = O_absent; |
12549 | s = expr_end; | |
12550 | continue; | |
12551 | ||
12552 | case 'Q': /* MDMX vector, element sel, or const. */ | |
12553 | if (s[0] != '$') | |
12554 | { | |
12555 | /* MDMX Immediate. */ | |
df58fc94 | 12556 | gas_assert (!mips_opts.micromips); |
deec1734 CD |
12557 | my_getExpression (&imm_expr, s); |
12558 | check_absolute_expr (ip, &imm_expr); | |
12559 | if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) | |
bf12938e RS |
12560 | as_warn (_("Invalid MDMX Immediate (%ld)"), |
12561 | (long) imm_expr.X_add_number); | |
df58fc94 | 12562 | INSERT_OPERAND (0, FT, *ip, imm_expr.X_add_number); |
deec1734 CD |
12563 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) |
12564 | ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; | |
12565 | else | |
12566 | ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; | |
deec1734 CD |
12567 | imm_expr.X_op = O_absent; |
12568 | s = expr_end; | |
12569 | continue; | |
12570 | } | |
12571 | /* Not MDMX Immediate. Fall through. */ | |
12572 | case 'X': /* MDMX destination register. */ | |
12573 | case 'Y': /* MDMX source register. */ | |
12574 | case 'Z': /* MDMX target register. */ | |
5c324c16 | 12575 | is_mdmx = !(insn->membership & INSN_5400); |
df58fc94 RS |
12576 | case 'W': |
12577 | gas_assert (!mips_opts.micromips); | |
90ecf173 MR |
12578 | case 'D': /* Floating point destination register. */ |
12579 | case 'S': /* Floating point source register. */ | |
12580 | case 'T': /* Floating point target register. */ | |
12581 | case 'R': /* Floating point source register. */ | |
252b5132 | 12582 | case 'V': |
707bfff6 TS |
12583 | rtype = RTYPE_FPU; |
12584 | if (is_mdmx | |
846ef2d0 | 12585 | || ((mips_opts.ase & ASE_MDMX) |
707bfff6 TS |
12586 | && (ip->insn_mo->pinfo & FP_D) |
12587 | && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY | |
12588 | | INSN_COPROC_MEMORY_DELAY | |
12589 | | INSN_LOAD_COPROC_DELAY | |
12590 | | INSN_LOAD_MEMORY_DELAY | |
12591 | | INSN_STORE_MEMORY)))) | |
12592 | rtype |= RTYPE_VEC; | |
252b5132 | 12593 | s_reset = s; |
707bfff6 | 12594 | if (reg_lookup (&s, rtype, ®no)) |
252b5132 | 12595 | { |
252b5132 | 12596 | if ((regno & 1) != 0 |
ca4e0257 | 12597 | && HAVE_32BIT_FPRS |
90ecf173 | 12598 | && !mips_oddfpreg_ok (ip->insn_mo, argnum)) |
252b5132 RH |
12599 | as_warn (_("Float register should be even, was %d"), |
12600 | regno); | |
12601 | ||
12602 | c = *args; | |
12603 | if (*s == ' ') | |
f9419b05 | 12604 | ++s; |
252b5132 RH |
12605 | if (args[1] != *s) |
12606 | { | |
12607 | if (c == 'V' || c == 'W') | |
12608 | { | |
12609 | regno = lastregno; | |
12610 | s = s_reset; | |
f9419b05 | 12611 | ++args; |
252b5132 RH |
12612 | } |
12613 | } | |
12614 | switch (c) | |
12615 | { | |
12616 | case 'D': | |
deec1734 | 12617 | case 'X': |
df58fc94 | 12618 | INSERT_OPERAND (mips_opts.micromips, FD, *ip, regno); |
252b5132 | 12619 | break; |
df58fc94 | 12620 | |
252b5132 RH |
12621 | case 'V': |
12622 | case 'S': | |
deec1734 | 12623 | case 'Y': |
df58fc94 | 12624 | INSERT_OPERAND (mips_opts.micromips, FS, *ip, regno); |
252b5132 | 12625 | break; |
df58fc94 | 12626 | |
deec1734 CD |
12627 | case 'Q': |
12628 | /* This is like 'Z', but also needs to fix the MDMX | |
12629 | vector/scalar select bits. Note that the | |
12630 | scalar immediate case is handled above. */ | |
5c324c16 RS |
12631 | if ((ip->insn_mo->membership & INSN_5400) |
12632 | && strcmp (insn->name, "rzu.ob") == 0) | |
12633 | as_bad (_("Operand %d of `%s' must be an immediate"), | |
12634 | argnum, ip->insn_mo->name); | |
12635 | ||
deec1734 CD |
12636 | if (*s == '[') |
12637 | { | |
12638 | int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); | |
12639 | int max_el = (is_qh ? 3 : 7); | |
12640 | s++; | |
12641 | my_getExpression(&imm_expr, s); | |
12642 | check_absolute_expr (ip, &imm_expr); | |
12643 | s = expr_end; | |
12644 | if (imm_expr.X_add_number > max_el) | |
20203fb9 NC |
12645 | as_bad (_("Bad element selector %ld"), |
12646 | (long) imm_expr.X_add_number); | |
deec1734 CD |
12647 | imm_expr.X_add_number &= max_el; |
12648 | ip->insn_opcode |= (imm_expr.X_add_number | |
12649 | << (OP_SH_VSEL + | |
12650 | (is_qh ? 2 : 1))); | |
01a3f561 | 12651 | imm_expr.X_op = O_absent; |
deec1734 | 12652 | if (*s != ']') |
20203fb9 | 12653 | as_warn (_("Expecting ']' found '%s'"), s); |
deec1734 CD |
12654 | else |
12655 | s++; | |
12656 | } | |
12657 | else | |
5c324c16 RS |
12658 | { |
12659 | if ((ip->insn_mo->membership & INSN_5400) | |
12660 | && (strcmp (insn->name, "sll.ob") == 0 | |
12661 | || strcmp (insn->name, "srl.ob") == 0)) | |
12662 | as_bad (_("Operand %d of `%s' must be scalar"), | |
12663 | argnum, ip->insn_mo->name); | |
12664 | ||
deec1734 CD |
12665 | if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) |
12666 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH | |
12667 | << OP_SH_VSEL); | |
12668 | else | |
12669 | ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << | |
12670 | OP_SH_VSEL); | |
12671 | } | |
90ecf173 | 12672 | /* Fall through. */ |
252b5132 RH |
12673 | case 'W': |
12674 | case 'T': | |
deec1734 | 12675 | case 'Z': |
df58fc94 | 12676 | INSERT_OPERAND (mips_opts.micromips, FT, *ip, regno); |
252b5132 | 12677 | break; |
df58fc94 | 12678 | |
252b5132 | 12679 | case 'R': |
df58fc94 | 12680 | INSERT_OPERAND (mips_opts.micromips, FR, *ip, regno); |
252b5132 RH |
12681 | break; |
12682 | } | |
12683 | lastregno = regno; | |
12684 | continue; | |
12685 | } | |
12686 | ||
252b5132 RH |
12687 | switch (*args++) |
12688 | { | |
12689 | case 'V': | |
df58fc94 | 12690 | INSERT_OPERAND (mips_opts.micromips, FS, *ip, lastregno); |
252b5132 | 12691 | continue; |
df58fc94 | 12692 | |
252b5132 | 12693 | case 'W': |
df58fc94 | 12694 | INSERT_OPERAND (mips_opts.micromips, FT, *ip, lastregno); |
252b5132 RH |
12695 | continue; |
12696 | } | |
12697 | break; | |
12698 | ||
12699 | case 'I': | |
12700 | my_getExpression (&imm_expr, s); | |
12701 | if (imm_expr.X_op != O_big | |
12702 | && imm_expr.X_op != O_constant) | |
12703 | insn_error = _("absolute expression required"); | |
9ee2a2d4 MR |
12704 | if (HAVE_32BIT_GPRS) |
12705 | normalize_constant_expr (&imm_expr); | |
252b5132 RH |
12706 | s = expr_end; |
12707 | continue; | |
12708 | ||
12709 | case 'A': | |
0cbbe1b8 RS |
12710 | my_getSmallExpression (&offset_expr, offset_reloc, s); |
12711 | if (offset_expr.X_op == O_register) | |
f2ae14a1 | 12712 | { |
0cbbe1b8 RS |
12713 | /* Assume that the offset has been elided and that what |
12714 | we saw was a base register. The match will fail later | |
12715 | if that assumption turns out to be wrong. */ | |
f2ae14a1 RS |
12716 | offset_expr.X_op = O_constant; |
12717 | offset_expr.X_add_number = 0; | |
12718 | } | |
12719 | else | |
12720 | { | |
f2ae14a1 RS |
12721 | normalize_address_expr (&offset_expr); |
12722 | s = expr_end; | |
12723 | } | |
252b5132 RH |
12724 | continue; |
12725 | ||
12726 | case 'F': | |
12727 | case 'L': | |
12728 | case 'f': | |
12729 | case 'l': | |
12730 | { | |
12731 | int f64; | |
ca4e0257 | 12732 | int using_gprs; |
252b5132 RH |
12733 | char *save_in; |
12734 | char *err; | |
12735 | unsigned char temp[8]; | |
12736 | int len; | |
12737 | unsigned int length; | |
12738 | segT seg; | |
12739 | subsegT subseg; | |
12740 | char *p; | |
12741 | ||
12742 | /* These only appear as the last operand in an | |
12743 | instruction, and every instruction that accepts | |
12744 | them in any variant accepts them in all variants. | |
12745 | This means we don't have to worry about backing out | |
12746 | any changes if the instruction does not match. | |
12747 | ||
12748 | The difference between them is the size of the | |
12749 | floating point constant and where it goes. For 'F' | |
12750 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
12751 | is 32 bits. Where the constant is placed is based | |
12752 | on how the MIPS assembler does things: | |
12753 | F -- .rdata | |
12754 | L -- .lit8 | |
12755 | f -- immediate value | |
12756 | l -- .lit4 | |
12757 | ||
12758 | The .lit4 and .lit8 sections are only used if | |
12759 | permitted by the -G argument. | |
12760 | ||
ca4e0257 RS |
12761 | The code below needs to know whether the target register |
12762 | is 32 or 64 bits wide. It relies on the fact 'f' and | |
12763 | 'F' are used with GPR-based instructions and 'l' and | |
12764 | 'L' are used with FPR-based instructions. */ | |
252b5132 RH |
12765 | |
12766 | f64 = *args == 'F' || *args == 'L'; | |
ca4e0257 | 12767 | using_gprs = *args == 'F' || *args == 'f'; |
252b5132 RH |
12768 | |
12769 | save_in = input_line_pointer; | |
12770 | input_line_pointer = s; | |
12771 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
12772 | length = len; | |
12773 | s = input_line_pointer; | |
12774 | input_line_pointer = save_in; | |
12775 | if (err != NULL && *err != '\0') | |
12776 | { | |
12777 | as_bad (_("Bad floating point constant: %s"), err); | |
12778 | memset (temp, '\0', sizeof temp); | |
12779 | length = f64 ? 8 : 4; | |
12780 | } | |
12781 | ||
9c2799c2 | 12782 | gas_assert (length == (unsigned) (f64 ? 8 : 4)); |
252b5132 RH |
12783 | |
12784 | if (*args == 'f' | |
12785 | || (*args == 'l' | |
3e722fb5 | 12786 | && (g_switch_value < 4 |
252b5132 RH |
12787 | || (temp[0] == 0 && temp[1] == 0) |
12788 | || (temp[2] == 0 && temp[3] == 0)))) | |
12789 | { | |
12790 | imm_expr.X_op = O_constant; | |
90ecf173 | 12791 | if (!target_big_endian) |
252b5132 RH |
12792 | imm_expr.X_add_number = bfd_getl32 (temp); |
12793 | else | |
12794 | imm_expr.X_add_number = bfd_getb32 (temp); | |
12795 | } | |
12796 | else if (length > 4 | |
90ecf173 | 12797 | && !mips_disable_float_construction |
ca4e0257 RS |
12798 | /* Constants can only be constructed in GPRs and |
12799 | copied to FPRs if the GPRs are at least as wide | |
12800 | as the FPRs. Force the constant into memory if | |
12801 | we are using 64-bit FPRs but the GPRs are only | |
12802 | 32 bits wide. */ | |
12803 | && (using_gprs | |
90ecf173 | 12804 | || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) |
252b5132 RH |
12805 | && ((temp[0] == 0 && temp[1] == 0) |
12806 | || (temp[2] == 0 && temp[3] == 0)) | |
12807 | && ((temp[4] == 0 && temp[5] == 0) | |
12808 | || (temp[6] == 0 && temp[7] == 0))) | |
12809 | { | |
ca4e0257 | 12810 | /* The value is simple enough to load with a couple of |
90ecf173 MR |
12811 | instructions. If using 32-bit registers, set |
12812 | imm_expr to the high order 32 bits and offset_expr to | |
12813 | the low order 32 bits. Otherwise, set imm_expr to | |
12814 | the entire 64 bit constant. */ | |
ca4e0257 | 12815 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) |
252b5132 RH |
12816 | { |
12817 | imm_expr.X_op = O_constant; | |
12818 | offset_expr.X_op = O_constant; | |
90ecf173 | 12819 | if (!target_big_endian) |
252b5132 RH |
12820 | { |
12821 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
12822 | offset_expr.X_add_number = bfd_getl32 (temp); | |
12823 | } | |
12824 | else | |
12825 | { | |
12826 | imm_expr.X_add_number = bfd_getb32 (temp); | |
12827 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
12828 | } | |
12829 | if (offset_expr.X_add_number == 0) | |
12830 | offset_expr.X_op = O_absent; | |
12831 | } | |
42429eac | 12832 | else |
252b5132 RH |
12833 | { |
12834 | imm_expr.X_op = O_constant; | |
90ecf173 | 12835 | if (!target_big_endian) |
252b5132 RH |
12836 | imm_expr.X_add_number = bfd_getl64 (temp); |
12837 | else | |
12838 | imm_expr.X_add_number = bfd_getb64 (temp); | |
12839 | } | |
252b5132 RH |
12840 | } |
12841 | else | |
12842 | { | |
12843 | const char *newname; | |
12844 | segT new_seg; | |
12845 | ||
12846 | /* Switch to the right section. */ | |
12847 | seg = now_seg; | |
12848 | subseg = now_subseg; | |
12849 | switch (*args) | |
12850 | { | |
12851 | default: /* unused default case avoids warnings. */ | |
12852 | case 'L': | |
12853 | newname = RDATA_SECTION_NAME; | |
3e722fb5 | 12854 | if (g_switch_value >= 8) |
252b5132 RH |
12855 | newname = ".lit8"; |
12856 | break; | |
12857 | case 'F': | |
3e722fb5 | 12858 | newname = RDATA_SECTION_NAME; |
252b5132 RH |
12859 | break; |
12860 | case 'l': | |
9c2799c2 | 12861 | gas_assert (g_switch_value >= 4); |
252b5132 RH |
12862 | newname = ".lit4"; |
12863 | break; | |
12864 | } | |
12865 | new_seg = subseg_new (newname, (subsegT) 0); | |
f3ded42a RS |
12866 | bfd_set_section_flags (stdoutput, new_seg, |
12867 | (SEC_ALLOC | |
12868 | | SEC_LOAD | |
12869 | | SEC_READONLY | |
12870 | | SEC_DATA)); | |
252b5132 | 12871 | frag_align (*args == 'l' ? 2 : 3, 0, 0); |
f3ded42a | 12872 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
252b5132 RH |
12873 | record_alignment (new_seg, 4); |
12874 | else | |
12875 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
12876 | if (seg == now_seg) | |
12877 | as_bad (_("Can't use floating point insn in this section")); | |
12878 | ||
df58fc94 RS |
12879 | /* Set the argument to the current address in the |
12880 | section. */ | |
12881 | offset_expr.X_op = O_symbol; | |
12882 | offset_expr.X_add_symbol = symbol_temp_new_now (); | |
12883 | offset_expr.X_add_number = 0; | |
12884 | ||
12885 | /* Put the floating point number into the section. */ | |
12886 | p = frag_more ((int) length); | |
12887 | memcpy (p, temp, length); | |
12888 | ||
12889 | /* Switch back to the original section. */ | |
12890 | subseg_set (seg, subseg); | |
12891 | } | |
12892 | } | |
12893 | continue; | |
12894 | ||
12895 | case 'i': /* 16-bit unsigned immediate. */ | |
12896 | case 'j': /* 16-bit signed immediate. */ | |
77bd4346 RS |
12897 | *offset_reloc = BFD_RELOC_LO16; |
12898 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0) | |
df58fc94 RS |
12899 | { |
12900 | int more; | |
12901 | offsetT minval, maxval; | |
12902 | ||
12903 | more = (insn + 1 < past | |
12904 | && strcmp (insn->name, insn[1].name) == 0); | |
12905 | ||
df58fc94 RS |
12906 | /* For compatibility with older assemblers, we accept |
12907 | 0x8000-0xffff as signed 16-bit numbers when only | |
12908 | signed numbers are allowed. */ | |
12909 | if (*args == 'i') | |
12910 | minval = 0, maxval = 0xffff; | |
12911 | else if (more) | |
12912 | minval = -0x8000, maxval = 0x7fff; | |
12913 | else | |
12914 | minval = -0x8000, maxval = 0xffff; | |
12915 | ||
77bd4346 RS |
12916 | if (offset_expr.X_op != O_constant |
12917 | || offset_expr.X_add_number < minval | |
12918 | || offset_expr.X_add_number > maxval) | |
df58fc94 RS |
12919 | { |
12920 | if (more) | |
12921 | break; | |
77bd4346 RS |
12922 | if (offset_expr.X_op == O_constant |
12923 | || offset_expr.X_op == O_big) | |
df58fc94 RS |
12924 | as_bad (_("Expression out of range")); |
12925 | } | |
12926 | } | |
12927 | s = expr_end; | |
12928 | continue; | |
12929 | ||
12930 | case 'o': /* 16-bit offset. */ | |
12931 | offset_reloc[0] = BFD_RELOC_LO16; | |
12932 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
12933 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
12934 | ||
12935 | /* Check whether there is only a single bracketed expression | |
12936 | left. If so, it must be the base register and the | |
12937 | constant must be zero. */ | |
12938 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
12939 | { | |
12940 | offset_expr.X_op = O_constant; | |
12941 | offset_expr.X_add_number = 0; | |
12942 | continue; | |
12943 | } | |
12944 | ||
12945 | /* If this value won't fit into a 16 bit offset, then go | |
12946 | find a macro that will generate the 32 bit offset | |
12947 | code pattern. */ | |
12948 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 | |
12949 | && (offset_expr.X_op != O_constant | |
12950 | || offset_expr.X_add_number >= 0x8000 | |
12951 | || offset_expr.X_add_number < -0x8000)) | |
12952 | break; | |
12953 | ||
12954 | s = expr_end; | |
12955 | continue; | |
12956 | ||
12957 | case 'p': /* PC-relative offset. */ | |
12958 | *offset_reloc = BFD_RELOC_16_PCREL_S2; | |
12959 | my_getExpression (&offset_expr, s); | |
12960 | s = expr_end; | |
12961 | continue; | |
12962 | ||
12963 | case 'u': /* Upper 16 bits. */ | |
77bd4346 RS |
12964 | *offset_reloc = BFD_RELOC_LO16; |
12965 | if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 | |
12966 | && offset_expr.X_op == O_constant | |
12967 | && (offset_expr.X_add_number < 0 | |
12968 | || offset_expr.X_add_number >= 0x10000)) | |
df58fc94 | 12969 | as_bad (_("lui expression (%lu) not in range 0..65535"), |
77bd4346 | 12970 | (unsigned long) offset_expr.X_add_number); |
df58fc94 RS |
12971 | s = expr_end; |
12972 | continue; | |
12973 | ||
12974 | case 'a': /* 26-bit address. */ | |
27c5c572 | 12975 | jump: |
df58fc94 RS |
12976 | *offset_reloc = BFD_RELOC_MIPS_JMP; |
12977 | my_getExpression (&offset_expr, s); | |
12978 | s = expr_end; | |
12979 | continue; | |
12980 | ||
12981 | case 'N': /* 3-bit branch condition code. */ | |
12982 | case 'M': /* 3-bit compare condition code. */ | |
12983 | rtype = RTYPE_CCC; | |
12984 | if (ip->insn_mo->pinfo & (FP_D | FP_S)) | |
12985 | rtype |= RTYPE_FCC; | |
12986 | if (!reg_lookup (&s, rtype, ®no)) | |
12987 | break; | |
12988 | if ((strcmp (str + strlen (str) - 3, ".ps") == 0 | |
12989 | || strcmp (str + strlen (str) - 5, "any2f") == 0 | |
12990 | || strcmp (str + strlen (str) - 5, "any2t") == 0) | |
12991 | && (regno & 1) != 0) | |
12992 | as_warn (_("Condition code register should be even for %s, " | |
12993 | "was %d"), | |
12994 | str, regno); | |
12995 | if ((strcmp (str + strlen (str) - 5, "any4f") == 0 | |
12996 | || strcmp (str + strlen (str) - 5, "any4t") == 0) | |
12997 | && (regno & 3) != 0) | |
12998 | as_warn (_("Condition code register should be 0 or 4 for %s, " | |
12999 | "was %d"), | |
13000 | str, regno); | |
13001 | if (*args == 'N') | |
13002 | INSERT_OPERAND (mips_opts.micromips, BCC, *ip, regno); | |
13003 | else | |
13004 | INSERT_OPERAND (mips_opts.micromips, CCC, *ip, regno); | |
13005 | continue; | |
13006 | ||
13007 | case 'H': | |
13008 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) | |
13009 | s += 2; | |
13010 | if (ISDIGIT (*s)) | |
13011 | { | |
13012 | c = 0; | |
13013 | do | |
13014 | { | |
13015 | c *= 10; | |
13016 | c += *s - '0'; | |
13017 | ++s; | |
13018 | } | |
13019 | while (ISDIGIT (*s)); | |
13020 | } | |
13021 | else | |
13022 | c = 8; /* Invalid sel value. */ | |
13023 | ||
13024 | if (c > 7) | |
13025 | as_bad (_("Invalid coprocessor sub-selection value (0-7)")); | |
13026 | INSERT_OPERAND (mips_opts.micromips, SEL, *ip, c); | |
13027 | continue; | |
13028 | ||
13029 | case 'e': | |
13030 | gas_assert (!mips_opts.micromips); | |
13031 | /* Must be at least one digit. */ | |
13032 | my_getExpression (&imm_expr, s); | |
13033 | check_absolute_expr (ip, &imm_expr); | |
13034 | ||
13035 | if ((unsigned long) imm_expr.X_add_number | |
13036 | > (unsigned long) OP_MASK_VECBYTE) | |
13037 | { | |
13038 | as_bad (_("bad byte vector index (%ld)"), | |
13039 | (long) imm_expr.X_add_number); | |
13040 | imm_expr.X_add_number = 0; | |
13041 | } | |
13042 | ||
13043 | INSERT_OPERAND (0, VECBYTE, *ip, imm_expr.X_add_number); | |
13044 | imm_expr.X_op = O_absent; | |
13045 | s = expr_end; | |
13046 | continue; | |
13047 | ||
13048 | case '%': | |
13049 | gas_assert (!mips_opts.micromips); | |
13050 | my_getExpression (&imm_expr, s); | |
13051 | check_absolute_expr (ip, &imm_expr); | |
13052 | ||
13053 | if ((unsigned long) imm_expr.X_add_number | |
13054 | > (unsigned long) OP_MASK_VECALIGN) | |
13055 | { | |
13056 | as_bad (_("bad byte vector index (%ld)"), | |
13057 | (long) imm_expr.X_add_number); | |
13058 | imm_expr.X_add_number = 0; | |
13059 | } | |
13060 | ||
13061 | INSERT_OPERAND (0, VECALIGN, *ip, imm_expr.X_add_number); | |
13062 | imm_expr.X_op = O_absent; | |
13063 | s = expr_end; | |
13064 | continue; | |
13065 | ||
13066 | case 'm': /* Opcode extension character. */ | |
13067 | gas_assert (mips_opts.micromips); | |
13068 | c = *++args; | |
13069 | switch (c) | |
13070 | { | |
13071 | case 'r': | |
13072 | if (strncmp (s, "$pc", 3) == 0) | |
13073 | { | |
13074 | s += 3; | |
13075 | continue; | |
13076 | } | |
13077 | break; | |
13078 | ||
13079 | case 'a': | |
13080 | case 'b': | |
13081 | case 'c': | |
13082 | case 'd': | |
13083 | case 'e': | |
13084 | case 'f': | |
13085 | case 'g': | |
13086 | case 'h': | |
df58fc94 RS |
13087 | case 'j': |
13088 | case 'l': | |
13089 | case 'm': | |
13090 | case 'n': | |
13091 | case 'p': | |
13092 | case 'q': | |
13093 | case 's': | |
13094 | case 't': | |
13095 | case 'x': | |
13096 | case 'y': | |
13097 | case 'z': | |
13098 | s_reset = s; | |
13099 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no); | |
13100 | if (regno == AT && mips_opts.at) | |
13101 | { | |
13102 | if (mips_opts.at == ATREG) | |
13103 | as_warn (_("Used $at without \".set noat\"")); | |
13104 | else | |
13105 | as_warn (_("Used $%u with \".set at=$%u\""), | |
13106 | regno, mips_opts.at); | |
13107 | } | |
13108 | if (!ok) | |
13109 | { | |
13110 | if (c == 'c') | |
13111 | { | |
13112 | gas_assert (args[1] == ','); | |
13113 | regno = lastregno; | |
13114 | ++args; | |
13115 | } | |
13116 | else if (c == 't') | |
13117 | { | |
13118 | gas_assert (args[1] == ','); | |
13119 | ++args; | |
13120 | continue; /* Nothing to do. */ | |
13121 | } | |
13122 | else | |
13123 | break; | |
13124 | } | |
13125 | ||
13126 | if (c == 'j' && !strncmp (ip->insn_mo->name, "jalr", 4)) | |
13127 | { | |
13128 | if (regno == lastregno) | |
13129 | { | |
13130 | insn_error | |
13131 | = _("Source and destination must be different"); | |
13132 | continue; | |
13133 | } | |
13134 | if (regno == 31 && lastregno == 0xffffffff) | |
13135 | { | |
13136 | insn_error | |
13137 | = _("A destination register must be supplied"); | |
13138 | continue; | |
13139 | } | |
13140 | } | |
13141 | ||
13142 | if (*s == ' ') | |
13143 | ++s; | |
13144 | if (args[1] != *s) | |
13145 | { | |
13146 | if (c == 'e') | |
13147 | { | |
13148 | gas_assert (args[1] == ','); | |
13149 | regno = lastregno; | |
13150 | s = s_reset; | |
13151 | ++args; | |
13152 | } | |
13153 | else if (c == 't') | |
13154 | { | |
13155 | gas_assert (args[1] == ','); | |
13156 | s = s_reset; | |
13157 | ++args; | |
13158 | continue; /* Nothing to do. */ | |
13159 | } | |
13160 | } | |
13161 | ||
13162 | /* Make sure regno is the same as lastregno. */ | |
13163 | if (c == 't' && regno != lastregno) | |
13164 | break; | |
13165 | ||
13166 | /* Make sure regno is the same as destregno. */ | |
13167 | if (c == 'x' && regno != destregno) | |
13168 | break; | |
13169 | ||
13170 | /* We need to save regno, before regno maps to the | |
13171 | microMIPS register encoding. */ | |
13172 | lastregno = regno; | |
13173 | ||
13174 | if (c == 'f') | |
13175 | destregno = regno; | |
13176 | ||
13177 | switch (c) | |
13178 | { | |
13179 | case 'a': | |
13180 | if (regno != GP) | |
13181 | regno = ILLEGAL_REG; | |
13182 | break; | |
13183 | ||
13184 | case 'b': | |
13185 | regno = mips32_to_micromips_reg_b_map[regno]; | |
13186 | break; | |
13187 | ||
13188 | case 'c': | |
13189 | regno = mips32_to_micromips_reg_c_map[regno]; | |
13190 | break; | |
13191 | ||
13192 | case 'd': | |
13193 | regno = mips32_to_micromips_reg_d_map[regno]; | |
13194 | break; | |
13195 | ||
13196 | case 'e': | |
13197 | regno = mips32_to_micromips_reg_e_map[regno]; | |
13198 | break; | |
13199 | ||
13200 | case 'f': | |
13201 | regno = mips32_to_micromips_reg_f_map[regno]; | |
13202 | break; | |
13203 | ||
13204 | case 'g': | |
13205 | regno = mips32_to_micromips_reg_g_map[regno]; | |
13206 | break; | |
13207 | ||
13208 | case 'h': | |
e76ff5ab RS |
13209 | s += strspn (s, " \t"); |
13210 | if (*s != ',') | |
df58fc94 | 13211 | { |
e76ff5ab RS |
13212 | regno = ILLEGAL_REG; |
13213 | break; | |
df58fc94 | 13214 | } |
e76ff5ab RS |
13215 | ++s; |
13216 | s += strspn (s, " \t"); | |
13217 | ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no2); | |
13218 | if (!ok) | |
13219 | { | |
13220 | regno = ILLEGAL_REG; | |
13221 | break; | |
13222 | } | |
13223 | if (regno2 == AT && mips_opts.at) | |
13224 | { | |
13225 | if (mips_opts.at == ATREG) | |
13226 | as_warn (_("Used $at without \".set noat\"")); | |
13227 | else | |
13228 | as_warn (_("Used $%u with \".set at=$%u\""), | |
13229 | regno2, mips_opts.at); | |
13230 | } | |
13231 | regno = (mips_lookup_reg_pair | |
13232 | (regno, regno2, | |
13233 | micromips_to_32_reg_h_map1, | |
13234 | micromips_to_32_reg_h_map2, 8)); | |
df58fc94 RS |
13235 | break; |
13236 | ||
13237 | case 'l': | |
13238 | regno = mips32_to_micromips_reg_l_map[regno]; | |
13239 | break; | |
13240 | ||
13241 | case 'm': | |
13242 | regno = mips32_to_micromips_reg_m_map[regno]; | |
13243 | break; | |
13244 | ||
13245 | case 'n': | |
13246 | regno = mips32_to_micromips_reg_n_map[regno]; | |
13247 | break; | |
13248 | ||
13249 | case 'q': | |
13250 | regno = mips32_to_micromips_reg_q_map[regno]; | |
13251 | break; | |
13252 | ||
13253 | case 's': | |
13254 | if (regno != SP) | |
13255 | regno = ILLEGAL_REG; | |
13256 | break; | |
13257 | ||
13258 | case 'y': | |
13259 | if (regno != 31) | |
13260 | regno = ILLEGAL_REG; | |
13261 | break; | |
13262 | ||
13263 | case 'z': | |
13264 | if (regno != ZERO) | |
13265 | regno = ILLEGAL_REG; | |
13266 | break; | |
13267 | ||
13268 | case 'j': /* Do nothing. */ | |
13269 | case 'p': | |
13270 | case 't': | |
13271 | case 'x': | |
13272 | break; | |
13273 | ||
13274 | default: | |
b37df7c4 | 13275 | abort (); |
df58fc94 RS |
13276 | } |
13277 | ||
13278 | if (regno == ILLEGAL_REG) | |
13279 | break; | |
13280 | ||
13281 | switch (c) | |
13282 | { | |
13283 | case 'b': | |
13284 | INSERT_OPERAND (1, MB, *ip, regno); | |
13285 | break; | |
13286 | ||
13287 | case 'c': | |
13288 | INSERT_OPERAND (1, MC, *ip, regno); | |
13289 | break; | |
13290 | ||
13291 | case 'd': | |
13292 | INSERT_OPERAND (1, MD, *ip, regno); | |
13293 | break; | |
13294 | ||
13295 | case 'e': | |
13296 | INSERT_OPERAND (1, ME, *ip, regno); | |
13297 | break; | |
13298 | ||
13299 | case 'f': | |
13300 | INSERT_OPERAND (1, MF, *ip, regno); | |
13301 | break; | |
13302 | ||
13303 | case 'g': | |
13304 | INSERT_OPERAND (1, MG, *ip, regno); | |
13305 | break; | |
13306 | ||
13307 | case 'h': | |
13308 | INSERT_OPERAND (1, MH, *ip, regno); | |
13309 | break; | |
13310 | ||
df58fc94 RS |
13311 | case 'j': |
13312 | INSERT_OPERAND (1, MJ, *ip, regno); | |
13313 | break; | |
13314 | ||
13315 | case 'l': | |
13316 | INSERT_OPERAND (1, ML, *ip, regno); | |
13317 | break; | |
13318 | ||
13319 | case 'm': | |
13320 | INSERT_OPERAND (1, MM, *ip, regno); | |
13321 | break; | |
13322 | ||
13323 | case 'n': | |
13324 | INSERT_OPERAND (1, MN, *ip, regno); | |
13325 | break; | |
13326 | ||
13327 | case 'p': | |
13328 | INSERT_OPERAND (1, MP, *ip, regno); | |
13329 | break; | |
13330 | ||
13331 | case 'q': | |
13332 | INSERT_OPERAND (1, MQ, *ip, regno); | |
13333 | break; | |
13334 | ||
13335 | case 'a': /* Do nothing. */ | |
13336 | case 's': /* Do nothing. */ | |
13337 | case 't': /* Do nothing. */ | |
13338 | case 'x': /* Do nothing. */ | |
13339 | case 'y': /* Do nothing. */ | |
13340 | case 'z': /* Do nothing. */ | |
13341 | break; | |
13342 | ||
13343 | default: | |
b37df7c4 | 13344 | abort (); |
df58fc94 RS |
13345 | } |
13346 | continue; | |
13347 | ||
13348 | case 'A': | |
13349 | { | |
13350 | bfd_reloc_code_real_type r[3]; | |
13351 | expressionS ep; | |
13352 | int imm; | |
13353 | ||
13354 | /* Check whether there is only a single bracketed | |
13355 | expression left. If so, it must be the base register | |
13356 | and the constant must be zero. */ | |
13357 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13358 | { | |
13359 | INSERT_OPERAND (1, IMMA, *ip, 0); | |
13360 | continue; | |
13361 | } | |
13362 | ||
13363 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13364 | || !expr_const_in_range (&ep, -64, 64, 2)) | |
13365 | break; | |
13366 | ||
13367 | imm = ep.X_add_number >> 2; | |
13368 | INSERT_OPERAND (1, IMMA, *ip, imm); | |
13369 | } | |
13370 | s = expr_end; | |
13371 | continue; | |
13372 | ||
13373 | case 'B': | |
13374 | { | |
13375 | bfd_reloc_code_real_type r[3]; | |
13376 | expressionS ep; | |
13377 | int imm; | |
13378 | ||
13379 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13380 | || ep.X_op != O_constant) | |
13381 | break; | |
13382 | ||
13383 | for (imm = 0; imm < 8; imm++) | |
13384 | if (micromips_imm_b_map[imm] == ep.X_add_number) | |
13385 | break; | |
13386 | if (imm >= 8) | |
13387 | break; | |
13388 | ||
13389 | INSERT_OPERAND (1, IMMB, *ip, imm); | |
13390 | } | |
13391 | s = expr_end; | |
13392 | continue; | |
13393 | ||
13394 | case 'C': | |
13395 | { | |
13396 | bfd_reloc_code_real_type r[3]; | |
13397 | expressionS ep; | |
13398 | int imm; | |
13399 | ||
13400 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13401 | || ep.X_op != O_constant) | |
13402 | break; | |
13403 | ||
13404 | for (imm = 0; imm < 16; imm++) | |
13405 | if (micromips_imm_c_map[imm] == ep.X_add_number) | |
13406 | break; | |
13407 | if (imm >= 16) | |
13408 | break; | |
13409 | ||
13410 | INSERT_OPERAND (1, IMMC, *ip, imm); | |
13411 | } | |
13412 | s = expr_end; | |
13413 | continue; | |
13414 | ||
13415 | case 'D': /* pc relative offset */ | |
13416 | case 'E': /* pc relative offset */ | |
13417 | my_getExpression (&offset_expr, s); | |
13418 | if (offset_expr.X_op == O_register) | |
13419 | break; | |
13420 | ||
40209cad MR |
13421 | if (!forced_insn_length) |
13422 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; | |
13423 | else if (c == 'D') | |
13424 | *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1; | |
13425 | else | |
13426 | *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1; | |
df58fc94 RS |
13427 | s = expr_end; |
13428 | continue; | |
13429 | ||
13430 | case 'F': | |
13431 | { | |
13432 | bfd_reloc_code_real_type r[3]; | |
13433 | expressionS ep; | |
13434 | int imm; | |
13435 | ||
13436 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13437 | || !expr_const_in_range (&ep, 0, 16, 0)) | |
13438 | break; | |
13439 | ||
13440 | imm = ep.X_add_number; | |
13441 | INSERT_OPERAND (1, IMMF, *ip, imm); | |
13442 | } | |
13443 | s = expr_end; | |
13444 | continue; | |
13445 | ||
13446 | case 'G': | |
13447 | { | |
13448 | bfd_reloc_code_real_type r[3]; | |
13449 | expressionS ep; | |
13450 | int imm; | |
13451 | ||
13452 | /* Check whether there is only a single bracketed | |
13453 | expression left. If so, it must be the base register | |
13454 | and the constant must be zero. */ | |
13455 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13456 | { | |
13457 | INSERT_OPERAND (1, IMMG, *ip, 0); | |
13458 | continue; | |
13459 | } | |
13460 | ||
13461 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13462 | || !expr_const_in_range (&ep, -1, 15, 0)) | |
13463 | break; | |
13464 | ||
13465 | imm = ep.X_add_number & 15; | |
13466 | INSERT_OPERAND (1, IMMG, *ip, imm); | |
13467 | } | |
13468 | s = expr_end; | |
13469 | continue; | |
13470 | ||
13471 | case 'H': | |
13472 | { | |
13473 | bfd_reloc_code_real_type r[3]; | |
13474 | expressionS ep; | |
13475 | int imm; | |
13476 | ||
13477 | /* Check whether there is only a single bracketed | |
13478 | expression left. If so, it must be the base register | |
13479 | and the constant must be zero. */ | |
13480 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13481 | { | |
13482 | INSERT_OPERAND (1, IMMH, *ip, 0); | |
13483 | continue; | |
13484 | } | |
13485 | ||
13486 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13487 | || !expr_const_in_range (&ep, 0, 16, 1)) | |
13488 | break; | |
13489 | ||
13490 | imm = ep.X_add_number >> 1; | |
13491 | INSERT_OPERAND (1, IMMH, *ip, imm); | |
13492 | } | |
13493 | s = expr_end; | |
13494 | continue; | |
13495 | ||
13496 | case 'I': | |
13497 | { | |
13498 | bfd_reloc_code_real_type r[3]; | |
13499 | expressionS ep; | |
13500 | int imm; | |
13501 | ||
13502 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13503 | || !expr_const_in_range (&ep, -1, 127, 0)) | |
13504 | break; | |
13505 | ||
13506 | imm = ep.X_add_number & 127; | |
13507 | INSERT_OPERAND (1, IMMI, *ip, imm); | |
13508 | } | |
13509 | s = expr_end; | |
13510 | continue; | |
13511 | ||
13512 | case 'J': | |
13513 | { | |
13514 | bfd_reloc_code_real_type r[3]; | |
13515 | expressionS ep; | |
13516 | int imm; | |
13517 | ||
13518 | /* Check whether there is only a single bracketed | |
13519 | expression left. If so, it must be the base register | |
13520 | and the constant must be zero. */ | |
13521 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13522 | { | |
13523 | INSERT_OPERAND (1, IMMJ, *ip, 0); | |
13524 | continue; | |
13525 | } | |
13526 | ||
13527 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13528 | || !expr_const_in_range (&ep, 0, 16, 2)) | |
13529 | break; | |
13530 | ||
13531 | imm = ep.X_add_number >> 2; | |
13532 | INSERT_OPERAND (1, IMMJ, *ip, imm); | |
13533 | } | |
13534 | s = expr_end; | |
13535 | continue; | |
13536 | ||
13537 | case 'L': | |
13538 | { | |
13539 | bfd_reloc_code_real_type r[3]; | |
13540 | expressionS ep; | |
13541 | int imm; | |
13542 | ||
13543 | /* Check whether there is only a single bracketed | |
13544 | expression left. If so, it must be the base register | |
13545 | and the constant must be zero. */ | |
13546 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13547 | { | |
13548 | INSERT_OPERAND (1, IMML, *ip, 0); | |
13549 | continue; | |
13550 | } | |
13551 | ||
13552 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13553 | || !expr_const_in_range (&ep, 0, 16, 0)) | |
13554 | break; | |
13555 | ||
13556 | imm = ep.X_add_number; | |
13557 | INSERT_OPERAND (1, IMML, *ip, imm); | |
13558 | } | |
13559 | s = expr_end; | |
13560 | continue; | |
13561 | ||
13562 | case 'M': | |
13563 | { | |
13564 | bfd_reloc_code_real_type r[3]; | |
13565 | expressionS ep; | |
13566 | int imm; | |
13567 | ||
13568 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13569 | || !expr_const_in_range (&ep, 1, 9, 0)) | |
13570 | break; | |
13571 | ||
13572 | imm = ep.X_add_number & 7; | |
13573 | INSERT_OPERAND (1, IMMM, *ip, imm); | |
13574 | } | |
13575 | s = expr_end; | |
13576 | continue; | |
13577 | ||
13578 | case 'N': /* Register list for lwm and swm. */ | |
13579 | { | |
13580 | /* A comma-separated list of registers and/or | |
13581 | dash-separated contiguous ranges including | |
13582 | both ra and a set of one or more registers | |
13583 | starting at s0 up to s3 which have to be | |
13584 | consecutive, e.g.: | |
13585 | ||
13586 | s0, ra | |
13587 | s0, s1, ra, s2, s3 | |
13588 | s0-s2, ra | |
13589 | ||
13590 | and any permutations of these. */ | |
13591 | unsigned int reglist; | |
13592 | int imm; | |
13593 | ||
13594 | if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list)) | |
13595 | break; | |
13596 | ||
13597 | if ((reglist & 0xfff1ffff) != 0x80010000) | |
13598 | break; | |
13599 | ||
13600 | reglist = (reglist >> 17) & 7; | |
13601 | reglist += 1; | |
13602 | if ((reglist & -reglist) != reglist) | |
13603 | break; | |
252b5132 | 13604 | |
df58fc94 RS |
13605 | imm = ffs (reglist) - 1; |
13606 | INSERT_OPERAND (1, IMMN, *ip, imm); | |
13607 | } | |
13608 | continue; | |
252b5132 | 13609 | |
df58fc94 RS |
13610 | case 'O': /* sdbbp 4-bit code. */ |
13611 | { | |
13612 | bfd_reloc_code_real_type r[3]; | |
13613 | expressionS ep; | |
13614 | int imm; | |
13615 | ||
13616 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13617 | || !expr_const_in_range (&ep, 0, 16, 0)) | |
13618 | break; | |
13619 | ||
13620 | imm = ep.X_add_number; | |
13621 | INSERT_OPERAND (1, IMMO, *ip, imm); | |
252b5132 | 13622 | } |
df58fc94 RS |
13623 | s = expr_end; |
13624 | continue; | |
252b5132 | 13625 | |
df58fc94 RS |
13626 | case 'P': |
13627 | { | |
13628 | bfd_reloc_code_real_type r[3]; | |
13629 | expressionS ep; | |
13630 | int imm; | |
5e0116d5 | 13631 | |
df58fc94 RS |
13632 | if (my_getSmallExpression (&ep, r, s) > 0 |
13633 | || !expr_const_in_range (&ep, 0, 32, 2)) | |
13634 | break; | |
5e0116d5 | 13635 | |
df58fc94 RS |
13636 | imm = ep.X_add_number >> 2; |
13637 | INSERT_OPERAND (1, IMMP, *ip, imm); | |
13638 | } | |
13639 | s = expr_end; | |
13640 | continue; | |
5e0116d5 | 13641 | |
df58fc94 RS |
13642 | case 'Q': |
13643 | { | |
13644 | bfd_reloc_code_real_type r[3]; | |
13645 | expressionS ep; | |
13646 | int imm; | |
5e0116d5 | 13647 | |
df58fc94 RS |
13648 | if (my_getSmallExpression (&ep, r, s) > 0 |
13649 | || !expr_const_in_range (&ep, -0x400000, 0x400000, 2)) | |
13650 | break; | |
252b5132 | 13651 | |
df58fc94 RS |
13652 | imm = ep.X_add_number >> 2; |
13653 | INSERT_OPERAND (1, IMMQ, *ip, imm); | |
13654 | } | |
13655 | s = expr_end; | |
13656 | continue; | |
4614d845 | 13657 | |
df58fc94 RS |
13658 | case 'U': |
13659 | { | |
13660 | bfd_reloc_code_real_type r[3]; | |
13661 | expressionS ep; | |
13662 | int imm; | |
13663 | ||
13664 | /* Check whether there is only a single bracketed | |
13665 | expression left. If so, it must be the base register | |
13666 | and the constant must be zero. */ | |
13667 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
13668 | { | |
13669 | INSERT_OPERAND (1, IMMU, *ip, 0); | |
13670 | continue; | |
13671 | } | |
13672 | ||
13673 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13674 | || !expr_const_in_range (&ep, 0, 32, 2)) | |
13675 | break; | |
13676 | ||
13677 | imm = ep.X_add_number >> 2; | |
13678 | INSERT_OPERAND (1, IMMU, *ip, imm); | |
13679 | } | |
13680 | s = expr_end; | |
5e0116d5 | 13681 | continue; |
252b5132 | 13682 | |
df58fc94 RS |
13683 | case 'W': |
13684 | { | |
13685 | bfd_reloc_code_real_type r[3]; | |
13686 | expressionS ep; | |
13687 | int imm; | |
252b5132 | 13688 | |
df58fc94 RS |
13689 | if (my_getSmallExpression (&ep, r, s) > 0 |
13690 | || !expr_const_in_range (&ep, 0, 64, 2)) | |
13691 | break; | |
252b5132 | 13692 | |
df58fc94 RS |
13693 | imm = ep.X_add_number >> 2; |
13694 | INSERT_OPERAND (1, IMMW, *ip, imm); | |
13695 | } | |
13696 | s = expr_end; | |
13697 | continue; | |
252b5132 | 13698 | |
df58fc94 RS |
13699 | case 'X': |
13700 | { | |
13701 | bfd_reloc_code_real_type r[3]; | |
13702 | expressionS ep; | |
13703 | int imm; | |
252b5132 | 13704 | |
df58fc94 RS |
13705 | if (my_getSmallExpression (&ep, r, s) > 0 |
13706 | || !expr_const_in_range (&ep, -8, 8, 0)) | |
13707 | break; | |
252b5132 | 13708 | |
df58fc94 RS |
13709 | imm = ep.X_add_number; |
13710 | INSERT_OPERAND (1, IMMX, *ip, imm); | |
13711 | } | |
13712 | s = expr_end; | |
13713 | continue; | |
252b5132 | 13714 | |
df58fc94 RS |
13715 | case 'Y': |
13716 | { | |
13717 | bfd_reloc_code_real_type r[3]; | |
13718 | expressionS ep; | |
13719 | int imm; | |
156c2f8b | 13720 | |
df58fc94 RS |
13721 | if (my_getSmallExpression (&ep, r, s) > 0 |
13722 | || expr_const_in_range (&ep, -2, 2, 2) | |
13723 | || !expr_const_in_range (&ep, -258, 258, 2)) | |
13724 | break; | |
156c2f8b | 13725 | |
df58fc94 RS |
13726 | imm = ep.X_add_number >> 2; |
13727 | imm = ((imm >> 1) & ~0xff) | (imm & 0xff); | |
13728 | INSERT_OPERAND (1, IMMY, *ip, imm); | |
13729 | } | |
13730 | s = expr_end; | |
13731 | continue; | |
60b63b72 | 13732 | |
df58fc94 RS |
13733 | case 'Z': |
13734 | { | |
13735 | bfd_reloc_code_real_type r[3]; | |
13736 | expressionS ep; | |
13737 | ||
13738 | if (my_getSmallExpression (&ep, r, s) > 0 | |
13739 | || !expr_const_in_range (&ep, 0, 1, 0)) | |
13740 | break; | |
13741 | } | |
13742 | s = expr_end; | |
13743 | continue; | |
13744 | ||
13745 | default: | |
13746 | as_bad (_("Internal error: bad microMIPS opcode " | |
13747 | "(unknown extension operand type `m%c'): %s %s"), | |
13748 | *args, insn->name, insn->args); | |
13749 | /* Further processing is fruitless. */ | |
13750 | return; | |
60b63b72 | 13751 | } |
df58fc94 | 13752 | break; |
60b63b72 | 13753 | |
df58fc94 RS |
13754 | case 'n': /* Register list for 32-bit lwm and swm. */ |
13755 | gas_assert (mips_opts.micromips); | |
13756 | { | |
13757 | /* A comma-separated list of registers and/or | |
13758 | dash-separated contiguous ranges including | |
13759 | at least one of ra and a set of one or more | |
13760 | registers starting at s0 up to s7 and then | |
13761 | s8 which have to be consecutive, e.g.: | |
13762 | ||
13763 | ra | |
13764 | s0 | |
13765 | ra, s0, s1, s2 | |
13766 | s0-s8 | |
13767 | s0-s5, ra | |
13768 | ||
13769 | and any permutations of these. */ | |
13770 | unsigned int reglist; | |
13771 | int imm; | |
13772 | int ra; | |
13773 | ||
13774 | if (!reglist_lookup (&s, RTYPE_NUM | RTYPE_GP, ®list)) | |
13775 | break; | |
13776 | ||
13777 | if ((reglist & 0x3f00ffff) != 0) | |
13778 | break; | |
13779 | ||
13780 | ra = (reglist >> 27) & 0x10; | |
13781 | reglist = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff); | |
13782 | reglist += 1; | |
13783 | if ((reglist & -reglist) != reglist) | |
13784 | break; | |
13785 | ||
13786 | imm = (ffs (reglist) - 1) | ra; | |
13787 | INSERT_OPERAND (1, RT, *ip, imm); | |
13788 | imm_expr.X_op = O_absent; | |
13789 | } | |
60b63b72 RS |
13790 | continue; |
13791 | ||
df58fc94 RS |
13792 | case '|': /* 4-bit trap code. */ |
13793 | gas_assert (mips_opts.micromips); | |
60b63b72 RS |
13794 | my_getExpression (&imm_expr, s); |
13795 | check_absolute_expr (ip, &imm_expr); | |
60b63b72 | 13796 | if ((unsigned long) imm_expr.X_add_number |
df58fc94 RS |
13797 | > MICROMIPSOP_MASK_TRAP) |
13798 | as_bad (_("Trap code (%lu) for %s not in 0..15 range"), | |
13799 | (unsigned long) imm_expr.X_add_number, | |
13800 | ip->insn_mo->name); | |
13801 | INSERT_OPERAND (1, TRAP, *ip, imm_expr.X_add_number); | |
60b63b72 RS |
13802 | imm_expr.X_op = O_absent; |
13803 | s = expr_end; | |
13804 | continue; | |
13805 | ||
252b5132 | 13806 | default: |
f71d0d44 | 13807 | as_bad (_("Bad char = '%c'\n"), *args); |
b37df7c4 | 13808 | abort (); |
252b5132 RH |
13809 | } |
13810 | break; | |
13811 | } | |
13812 | /* Args don't match. */ | |
df58fc94 RS |
13813 | s = argsStart; |
13814 | insn_error = _("Illegal operands"); | |
13815 | if (insn + 1 < past && !strcmp (insn->name, insn[1].name)) | |
252b5132 RH |
13816 | { |
13817 | ++insn; | |
252b5132 RH |
13818 | continue; |
13819 | } | |
df58fc94 RS |
13820 | else if (wrong_delay_slot_insns && need_delay_slot_ok) |
13821 | { | |
13822 | gas_assert (firstinsn); | |
13823 | need_delay_slot_ok = FALSE; | |
13824 | past = insn + 1; | |
13825 | insn = firstinsn; | |
13826 | continue; | |
13827 | } | |
252b5132 RH |
13828 | return; |
13829 | } | |
13830 | } | |
13831 | ||
0499d65b TS |
13832 | #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); } |
13833 | ||
77bd4346 RS |
13834 | /* As for mips_ip, but used when assembling MIPS16 code. |
13835 | Also set forced_insn_length to the resulting instruction size in | |
13836 | bytes if the user explicitly requested a small or extended instruction. */ | |
252b5132 RH |
13837 | |
13838 | static void | |
17a2f251 | 13839 | mips16_ip (char *str, struct mips_cl_insn *ip) |
252b5132 RH |
13840 | { |
13841 | char *s; | |
13842 | const char *args; | |
13843 | struct mips_opcode *insn; | |
13844 | char *argsstart; | |
13845 | unsigned int regno; | |
13846 | unsigned int lastregno = 0; | |
13847 | char *s_reset; | |
d6f16593 | 13848 | size_t i; |
252b5132 RH |
13849 | |
13850 | insn_error = NULL; | |
13851 | ||
df58fc94 | 13852 | forced_insn_length = 0; |
252b5132 | 13853 | |
3882b010 | 13854 | for (s = str; ISLOWER (*s); ++s) |
252b5132 RH |
13855 | ; |
13856 | switch (*s) | |
13857 | { | |
13858 | case '\0': | |
13859 | break; | |
13860 | ||
13861 | case ' ': | |
13862 | *s++ = '\0'; | |
13863 | break; | |
13864 | ||
13865 | case '.': | |
13866 | if (s[1] == 't' && s[2] == ' ') | |
13867 | { | |
13868 | *s = '\0'; | |
df58fc94 | 13869 | forced_insn_length = 2; |
252b5132 RH |
13870 | s += 3; |
13871 | break; | |
13872 | } | |
13873 | else if (s[1] == 'e' && s[2] == ' ') | |
13874 | { | |
13875 | *s = '\0'; | |
df58fc94 | 13876 | forced_insn_length = 4; |
252b5132 RH |
13877 | s += 3; |
13878 | break; | |
13879 | } | |
13880 | /* Fall through. */ | |
13881 | default: | |
13882 | insn_error = _("unknown opcode"); | |
13883 | return; | |
13884 | } | |
13885 | ||
df58fc94 RS |
13886 | if (mips_opts.noautoextend && !forced_insn_length) |
13887 | forced_insn_length = 2; | |
252b5132 RH |
13888 | |
13889 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
13890 | { | |
13891 | insn_error = _("unrecognized opcode"); | |
13892 | return; | |
13893 | } | |
13894 | ||
13895 | argsstart = s; | |
13896 | for (;;) | |
13897 | { | |
9b3f89ee | 13898 | bfd_boolean ok; |
77bd4346 | 13899 | char relax_char; |
9b3f89ee | 13900 | |
9c2799c2 | 13901 | gas_assert (strcmp (insn->name, str) == 0); |
252b5132 | 13902 | |
037b32b9 | 13903 | ok = is_opcode_valid_16 (insn); |
9b3f89ee TS |
13904 | if (! ok) |
13905 | { | |
13906 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] | |
13907 | && strcmp (insn->name, insn[1].name) == 0) | |
13908 | { | |
13909 | ++insn; | |
13910 | continue; | |
13911 | } | |
13912 | else | |
13913 | { | |
13914 | if (!insn_error) | |
13915 | { | |
13916 | static char buf[100]; | |
13917 | sprintf (buf, | |
7bd942df | 13918 | _("Opcode not supported on this processor: %s (%s)"), |
9b3f89ee TS |
13919 | mips_cpu_info_from_arch (mips_opts.arch)->name, |
13920 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
13921 | insn_error = buf; | |
13922 | } | |
13923 | return; | |
13924 | } | |
13925 | } | |
13926 | ||
1e915849 | 13927 | create_insn (ip, insn); |
252b5132 | 13928 | imm_expr.X_op = O_absent; |
5f74bc13 | 13929 | imm2_expr.X_op = O_absent; |
252b5132 | 13930 | offset_expr.X_op = O_absent; |
f6688943 TS |
13931 | offset_reloc[0] = BFD_RELOC_UNUSED; |
13932 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
13933 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
77bd4346 | 13934 | relax_char = 0; |
252b5132 RH |
13935 | for (args = insn->args; 1; ++args) |
13936 | { | |
13937 | int c; | |
13938 | ||
13939 | if (*s == ' ') | |
13940 | ++s; | |
13941 | ||
13942 | /* In this switch statement we call break if we did not find | |
13943 | a match, continue if we did find a match, or return if we | |
13944 | are done. */ | |
13945 | ||
13946 | c = *args; | |
13947 | switch (c) | |
13948 | { | |
13949 | case '\0': | |
13950 | if (*s == '\0') | |
13951 | { | |
b886a2ab RS |
13952 | offsetT value; |
13953 | ||
252b5132 | 13954 | /* Stuff the immediate value in now, if we can. */ |
77bd4346 RS |
13955 | if (insn->pinfo == INSN_MACRO) |
13956 | { | |
13957 | gas_assert (relax_char == 0); | |
13958 | gas_assert (*offset_reloc == BFD_RELOC_UNUSED); | |
13959 | } | |
13960 | else if (relax_char | |
13961 | && offset_expr.X_op == O_constant | |
13962 | && calculate_reloc (*offset_reloc, | |
13963 | offset_expr.X_add_number, | |
13964 | &value)) | |
252b5132 | 13965 | { |
77bd4346 RS |
13966 | mips16_immed (NULL, 0, relax_char, *offset_reloc, value, |
13967 | forced_insn_length, &ip->insn_opcode); | |
13968 | offset_expr.X_op = O_absent; | |
43c0598f | 13969 | *offset_reloc = BFD_RELOC_UNUSED; |
252b5132 | 13970 | } |
77bd4346 RS |
13971 | else if (relax_char && *offset_reloc != BFD_RELOC_UNUSED) |
13972 | { | |
13973 | if (forced_insn_length == 2) | |
13974 | as_bad (_("invalid unextended operand value")); | |
13975 | forced_insn_length = 4; | |
13976 | ip->insn_opcode |= MIPS16_EXTEND; | |
13977 | } | |
13978 | else if (relax_char) | |
13979 | *offset_reloc = (int) BFD_RELOC_UNUSED + relax_char; | |
252b5132 RH |
13980 | |
13981 | return; | |
13982 | } | |
13983 | break; | |
13984 | ||
13985 | case ',': | |
13986 | if (*s++ == c) | |
13987 | continue; | |
13988 | s--; | |
13989 | switch (*++args) | |
13990 | { | |
13991 | case 'v': | |
bf12938e | 13992 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 RH |
13993 | continue; |
13994 | case 'w': | |
bf12938e | 13995 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
13996 | continue; |
13997 | } | |
13998 | break; | |
13999 | ||
14000 | case '(': | |
14001 | case ')': | |
14002 | if (*s++ == c) | |
14003 | continue; | |
14004 | break; | |
14005 | ||
14006 | case 'v': | |
14007 | case 'w': | |
14008 | if (s[0] != '$') | |
14009 | { | |
14010 | if (c == 'v') | |
bf12938e | 14011 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
252b5132 | 14012 | else |
bf12938e | 14013 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
252b5132 RH |
14014 | ++args; |
14015 | continue; | |
14016 | } | |
14017 | /* Fall through. */ | |
14018 | case 'x': | |
14019 | case 'y': | |
14020 | case 'z': | |
14021 | case 'Z': | |
14022 | case '0': | |
14023 | case 'S': | |
14024 | case 'R': | |
14025 | case 'X': | |
14026 | case 'Y': | |
707bfff6 TS |
14027 | s_reset = s; |
14028 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no)) | |
252b5132 | 14029 | { |
707bfff6 | 14030 | if (c == 'v' || c == 'w') |
85b51719 | 14031 | { |
707bfff6 | 14032 | if (c == 'v') |
a9e24354 | 14033 | MIPS16_INSERT_OPERAND (RX, *ip, lastregno); |
707bfff6 | 14034 | else |
a9e24354 | 14035 | MIPS16_INSERT_OPERAND (RY, *ip, lastregno); |
707bfff6 TS |
14036 | ++args; |
14037 | continue; | |
85b51719 | 14038 | } |
707bfff6 | 14039 | break; |
252b5132 RH |
14040 | } |
14041 | ||
14042 | if (*s == ' ') | |
14043 | ++s; | |
14044 | if (args[1] != *s) | |
14045 | { | |
14046 | if (c == 'v' || c == 'w') | |
14047 | { | |
14048 | regno = mips16_to_32_reg_map[lastregno]; | |
14049 | s = s_reset; | |
f9419b05 | 14050 | ++args; |
252b5132 RH |
14051 | } |
14052 | } | |
14053 | ||
14054 | switch (c) | |
14055 | { | |
14056 | case 'x': | |
14057 | case 'y': | |
14058 | case 'z': | |
14059 | case 'v': | |
14060 | case 'w': | |
14061 | case 'Z': | |
14062 | regno = mips32_to_16_reg_map[regno]; | |
14063 | break; | |
14064 | ||
14065 | case '0': | |
14066 | if (regno != 0) | |
14067 | regno = ILLEGAL_REG; | |
14068 | break; | |
14069 | ||
14070 | case 'S': | |
14071 | if (regno != SP) | |
14072 | regno = ILLEGAL_REG; | |
14073 | break; | |
14074 | ||
14075 | case 'R': | |
14076 | if (regno != RA) | |
14077 | regno = ILLEGAL_REG; | |
14078 | break; | |
14079 | ||
14080 | case 'X': | |
14081 | case 'Y': | |
741fe287 MR |
14082 | if (regno == AT && mips_opts.at) |
14083 | { | |
14084 | if (mips_opts.at == ATREG) | |
14085 | as_warn (_("used $at without \".set noat\"")); | |
14086 | else | |
14087 | as_warn (_("used $%u with \".set at=$%u\""), | |
14088 | regno, mips_opts.at); | |
14089 | } | |
252b5132 RH |
14090 | break; |
14091 | ||
14092 | default: | |
b37df7c4 | 14093 | abort (); |
252b5132 RH |
14094 | } |
14095 | ||
14096 | if (regno == ILLEGAL_REG) | |
14097 | break; | |
14098 | ||
14099 | switch (c) | |
14100 | { | |
14101 | case 'x': | |
14102 | case 'v': | |
bf12938e | 14103 | MIPS16_INSERT_OPERAND (RX, *ip, regno); |
252b5132 RH |
14104 | break; |
14105 | case 'y': | |
14106 | case 'w': | |
bf12938e | 14107 | MIPS16_INSERT_OPERAND (RY, *ip, regno); |
252b5132 RH |
14108 | break; |
14109 | case 'z': | |
bf12938e | 14110 | MIPS16_INSERT_OPERAND (RZ, *ip, regno); |
252b5132 RH |
14111 | break; |
14112 | case 'Z': | |
bf12938e | 14113 | MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno); |
252b5132 RH |
14114 | case '0': |
14115 | case 'S': | |
14116 | case 'R': | |
14117 | break; | |
14118 | case 'X': | |
bf12938e | 14119 | MIPS16_INSERT_OPERAND (REGR32, *ip, regno); |
252b5132 RH |
14120 | break; |
14121 | case 'Y': | |
14122 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
bf12938e | 14123 | MIPS16_INSERT_OPERAND (REG32R, *ip, regno); |
252b5132 RH |
14124 | break; |
14125 | default: | |
b37df7c4 | 14126 | abort (); |
252b5132 RH |
14127 | } |
14128 | ||
14129 | lastregno = regno; | |
14130 | continue; | |
14131 | ||
14132 | case 'P': | |
14133 | if (strncmp (s, "$pc", 3) == 0) | |
14134 | { | |
14135 | s += 3; | |
14136 | continue; | |
14137 | } | |
14138 | break; | |
14139 | ||
252b5132 RH |
14140 | case '5': |
14141 | case 'H': | |
14142 | case 'W': | |
14143 | case 'D': | |
14144 | case 'j': | |
252b5132 RH |
14145 | case 'V': |
14146 | case 'C': | |
14147 | case 'U': | |
14148 | case 'k': | |
14149 | case 'K': | |
77bd4346 | 14150 | i = my_getSmallExpression (&offset_expr, offset_reloc, s); |
d6f16593 | 14151 | if (i > 0) |
252b5132 | 14152 | { |
77bd4346 | 14153 | relax_char = c; |
d6f16593 MR |
14154 | s = expr_end; |
14155 | continue; | |
252b5132 | 14156 | } |
77bd4346 | 14157 | *offset_reloc = BFD_RELOC_UNUSED; |
d6f16593 MR |
14158 | /* Fall through. */ |
14159 | case '<': | |
14160 | case '>': | |
14161 | case '[': | |
14162 | case ']': | |
14163 | case '4': | |
14164 | case '8': | |
77bd4346 RS |
14165 | my_getExpression (&offset_expr, s); |
14166 | if (offset_expr.X_op == O_register) | |
252b5132 RH |
14167 | { |
14168 | /* What we thought was an expression turned out to | |
14169 | be a register. */ | |
14170 | ||
14171 | if (s[0] == '(' && args[1] == '(') | |
14172 | { | |
14173 | /* It looks like the expression was omitted | |
14174 | before a register indirection, which means | |
14175 | that the expression is implicitly zero. We | |
77bd4346 | 14176 | still set up offset_expr, so that we handle |
252b5132 | 14177 | explicit extensions correctly. */ |
77bd4346 RS |
14178 | offset_expr.X_op = O_constant; |
14179 | offset_expr.X_add_number = 0; | |
14180 | relax_char = c; | |
252b5132 RH |
14181 | continue; |
14182 | } | |
14183 | ||
14184 | break; | |
14185 | } | |
14186 | ||
14187 | /* We need to relax this instruction. */ | |
77bd4346 | 14188 | relax_char = c; |
252b5132 RH |
14189 | s = expr_end; |
14190 | continue; | |
14191 | ||
14192 | case 'p': | |
14193 | case 'q': | |
14194 | case 'A': | |
14195 | case 'B': | |
14196 | case 'E': | |
14197 | /* We use offset_reloc rather than imm_reloc for the PC | |
14198 | relative operands. This lets macros with both | |
14199 | immediate and address operands work correctly. */ | |
14200 | my_getExpression (&offset_expr, s); | |
14201 | ||
14202 | if (offset_expr.X_op == O_register) | |
14203 | break; | |
14204 | ||
14205 | /* We need to relax this instruction. */ | |
77bd4346 | 14206 | relax_char = c; |
252b5132 RH |
14207 | s = expr_end; |
14208 | continue; | |
14209 | ||
14210 | case '6': /* break code */ | |
14211 | my_getExpression (&imm_expr, s); | |
14212 | check_absolute_expr (ip, &imm_expr); | |
14213 | if ((unsigned long) imm_expr.X_add_number > 63) | |
bf12938e RS |
14214 | as_warn (_("Invalid value for `%s' (%lu)"), |
14215 | ip->insn_mo->name, | |
14216 | (unsigned long) imm_expr.X_add_number); | |
14217 | MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number); | |
252b5132 RH |
14218 | imm_expr.X_op = O_absent; |
14219 | s = expr_end; | |
14220 | continue; | |
14221 | ||
cc537e56 RS |
14222 | case 'I': |
14223 | my_getExpression (&imm_expr, s); | |
14224 | if (imm_expr.X_op != O_big | |
14225 | && imm_expr.X_op != O_constant) | |
14226 | insn_error = _("absolute expression required"); | |
14227 | if (HAVE_32BIT_GPRS) | |
14228 | normalize_constant_expr (&imm_expr); | |
14229 | s = expr_end; | |
14230 | continue; | |
14231 | ||
252b5132 | 14232 | case 'a': /* 26 bit address */ |
27c5c572 | 14233 | case 'i': |
252b5132 RH |
14234 | my_getExpression (&offset_expr, s); |
14235 | s = expr_end; | |
f6688943 | 14236 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
252b5132 RH |
14237 | ip->insn_opcode <<= 16; |
14238 | continue; | |
14239 | ||
14240 | case 'l': /* register list for entry macro */ | |
14241 | case 'L': /* register list for exit macro */ | |
14242 | { | |
14243 | int mask; | |
14244 | ||
14245 | if (c == 'l') | |
14246 | mask = 0; | |
14247 | else | |
14248 | mask = 7 << 3; | |
14249 | while (*s != '\0') | |
14250 | { | |
707bfff6 | 14251 | unsigned int freg, reg1, reg2; |
252b5132 RH |
14252 | |
14253 | while (*s == ' ' || *s == ',') | |
14254 | ++s; | |
707bfff6 | 14255 | if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
252b5132 | 14256 | freg = 0; |
707bfff6 TS |
14257 | else if (reg_lookup (&s, RTYPE_FPU, ®1)) |
14258 | freg = 1; | |
252b5132 RH |
14259 | else |
14260 | { | |
707bfff6 TS |
14261 | as_bad (_("can't parse register list")); |
14262 | break; | |
252b5132 RH |
14263 | } |
14264 | if (*s == ' ') | |
14265 | ++s; | |
14266 | if (*s != '-') | |
14267 | reg2 = reg1; | |
14268 | else | |
14269 | { | |
14270 | ++s; | |
707bfff6 TS |
14271 | if (!reg_lookup (&s, freg ? RTYPE_FPU |
14272 | : (RTYPE_GP | RTYPE_NUM), ®2)) | |
252b5132 | 14273 | { |
707bfff6 TS |
14274 | as_bad (_("invalid register list")); |
14275 | break; | |
252b5132 RH |
14276 | } |
14277 | } | |
14278 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
14279 | { | |
14280 | mask &= ~ (7 << 3); | |
14281 | mask |= 5 << 3; | |
14282 | } | |
14283 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
14284 | { | |
14285 | mask &= ~ (7 << 3); | |
14286 | mask |= 6 << 3; | |
14287 | } | |
14288 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
14289 | mask |= (reg2 - 3) << 3; | |
14290 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
14291 | mask |= (reg2 - 15) << 1; | |
f9419b05 | 14292 | else if (reg1 == RA && reg2 == RA) |
252b5132 RH |
14293 | mask |= 1; |
14294 | else | |
14295 | { | |
14296 | as_bad (_("invalid register list")); | |
14297 | break; | |
14298 | } | |
14299 | } | |
14300 | /* The mask is filled in in the opcode table for the | |
14301 | benefit of the disassembler. We remove it before | |
14302 | applying the actual mask. */ | |
14303 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
14304 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
14305 | } | |
14306 | continue; | |
14307 | ||
0499d65b TS |
14308 | case 'm': /* Register list for save insn. */ |
14309 | case 'M': /* Register list for restore insn. */ | |
14310 | { | |
5c04167a | 14311 | int opcode = ip->insn_opcode; |
0499d65b | 14312 | int framesz = 0, seen_framesz = 0; |
91d6fa6a | 14313 | int nargs = 0, statics = 0, sregs = 0; |
0499d65b TS |
14314 | |
14315 | while (*s != '\0') | |
14316 | { | |
14317 | unsigned int reg1, reg2; | |
14318 | ||
14319 | SKIP_SPACE_TABS (s); | |
14320 | while (*s == ',') | |
14321 | ++s; | |
14322 | SKIP_SPACE_TABS (s); | |
14323 | ||
14324 | my_getExpression (&imm_expr, s); | |
14325 | if (imm_expr.X_op == O_constant) | |
14326 | { | |
14327 | /* Handle the frame size. */ | |
14328 | if (seen_framesz) | |
14329 | { | |
14330 | as_bad (_("more than one frame size in list")); | |
14331 | break; | |
14332 | } | |
14333 | seen_framesz = 1; | |
14334 | framesz = imm_expr.X_add_number; | |
14335 | imm_expr.X_op = O_absent; | |
14336 | s = expr_end; | |
14337 | continue; | |
14338 | } | |
14339 | ||
707bfff6 | 14340 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®1)) |
0499d65b TS |
14341 | { |
14342 | as_bad (_("can't parse register list")); | |
14343 | break; | |
14344 | } | |
0499d65b | 14345 | |
707bfff6 TS |
14346 | while (*s == ' ') |
14347 | ++s; | |
14348 | ||
0499d65b TS |
14349 | if (*s != '-') |
14350 | reg2 = reg1; | |
14351 | else | |
14352 | { | |
14353 | ++s; | |
707bfff6 TS |
14354 | if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, ®2) |
14355 | || reg2 < reg1) | |
0499d65b TS |
14356 | { |
14357 | as_bad (_("can't parse register list")); | |
14358 | break; | |
14359 | } | |
0499d65b TS |
14360 | } |
14361 | ||
14362 | while (reg1 <= reg2) | |
14363 | { | |
14364 | if (reg1 >= 4 && reg1 <= 7) | |
14365 | { | |
3a93f742 | 14366 | if (!seen_framesz) |
0499d65b | 14367 | /* args $a0-$a3 */ |
91d6fa6a | 14368 | nargs |= 1 << (reg1 - 4); |
0499d65b TS |
14369 | else |
14370 | /* statics $a0-$a3 */ | |
14371 | statics |= 1 << (reg1 - 4); | |
14372 | } | |
14373 | else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30) | |
14374 | { | |
14375 | /* $s0-$s8 */ | |
14376 | sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16)); | |
14377 | } | |
14378 | else if (reg1 == 31) | |
14379 | { | |
14380 | /* Add $ra to insn. */ | |
14381 | opcode |= 0x40; | |
14382 | } | |
14383 | else | |
14384 | { | |
14385 | as_bad (_("unexpected register in list")); | |
14386 | break; | |
14387 | } | |
14388 | if (++reg1 == 24) | |
14389 | reg1 = 30; | |
14390 | } | |
14391 | } | |
14392 | ||
14393 | /* Encode args/statics combination. */ | |
91d6fa6a | 14394 | if (nargs & statics) |
0499d65b | 14395 | as_bad (_("arg/static registers overlap")); |
91d6fa6a | 14396 | else if (nargs == 0xf) |
0499d65b TS |
14397 | /* All $a0-$a3 are args. */ |
14398 | opcode |= MIPS16_ALL_ARGS << 16; | |
14399 | else if (statics == 0xf) | |
14400 | /* All $a0-$a3 are statics. */ | |
14401 | opcode |= MIPS16_ALL_STATICS << 16; | |
14402 | else | |
14403 | { | |
14404 | int narg = 0, nstat = 0; | |
14405 | ||
14406 | /* Count arg registers. */ | |
91d6fa6a | 14407 | while (nargs & 0x1) |
0499d65b | 14408 | { |
91d6fa6a | 14409 | nargs >>= 1; |
0499d65b TS |
14410 | narg++; |
14411 | } | |
91d6fa6a | 14412 | if (nargs != 0) |
0499d65b TS |
14413 | as_bad (_("invalid arg register list")); |
14414 | ||
14415 | /* Count static registers. */ | |
14416 | while (statics & 0x8) | |
14417 | { | |
14418 | statics = (statics << 1) & 0xf; | |
14419 | nstat++; | |
14420 | } | |
14421 | if (statics != 0) | |
14422 | as_bad (_("invalid static register list")); | |
14423 | ||
14424 | /* Encode args/statics. */ | |
14425 | opcode |= ((narg << 2) | nstat) << 16; | |
14426 | } | |
14427 | ||
14428 | /* Encode $s0/$s1. */ | |
14429 | if (sregs & (1 << 0)) /* $s0 */ | |
14430 | opcode |= 0x20; | |
14431 | if (sregs & (1 << 1)) /* $s1 */ | |
14432 | opcode |= 0x10; | |
14433 | sregs >>= 2; | |
14434 | ||
14435 | if (sregs != 0) | |
14436 | { | |
14437 | /* Count regs $s2-$s8. */ | |
14438 | int nsreg = 0; | |
14439 | while (sregs & 1) | |
14440 | { | |
14441 | sregs >>= 1; | |
14442 | nsreg++; | |
14443 | } | |
14444 | if (sregs != 0) | |
14445 | as_bad (_("invalid static register list")); | |
14446 | /* Encode $s2-$s8. */ | |
14447 | opcode |= nsreg << 24; | |
14448 | } | |
14449 | ||
14450 | /* Encode frame size. */ | |
14451 | if (!seen_framesz) | |
14452 | as_bad (_("missing frame size")); | |
14453 | else if ((framesz & 7) != 0 || framesz < 0 | |
14454 | || framesz > 0xff * 8) | |
14455 | as_bad (_("invalid frame size")); | |
14456 | else if (framesz != 128 || (opcode >> 16) != 0) | |
14457 | { | |
14458 | framesz /= 8; | |
14459 | opcode |= (((framesz & 0xf0) << 16) | |
14460 | | (framesz & 0x0f)); | |
14461 | } | |
14462 | ||
14463 | /* Finally build the instruction. */ | |
14464 | if ((opcode >> 16) != 0 || framesz == 0) | |
5c04167a RS |
14465 | opcode |= MIPS16_EXTEND; |
14466 | ip->insn_opcode = opcode; | |
0499d65b TS |
14467 | } |
14468 | continue; | |
14469 | ||
252b5132 RH |
14470 | case 'e': /* extend code */ |
14471 | my_getExpression (&imm_expr, s); | |
14472 | check_absolute_expr (ip, &imm_expr); | |
14473 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
14474 | { | |
14475 | as_warn (_("Invalid value for `%s' (%lu)"), | |
14476 | ip->insn_mo->name, | |
14477 | (unsigned long) imm_expr.X_add_number); | |
14478 | imm_expr.X_add_number &= 0x7ff; | |
14479 | } | |
14480 | ip->insn_opcode |= imm_expr.X_add_number; | |
14481 | imm_expr.X_op = O_absent; | |
14482 | s = expr_end; | |
14483 | continue; | |
14484 | ||
14485 | default: | |
b37df7c4 | 14486 | abort (); |
252b5132 RH |
14487 | } |
14488 | break; | |
14489 | } | |
14490 | ||
14491 | /* Args don't match. */ | |
14492 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
14493 | strcmp (insn->name, insn[1].name) == 0) | |
14494 | { | |
14495 | ++insn; | |
14496 | s = argsstart; | |
14497 | continue; | |
14498 | } | |
14499 | ||
14500 | insn_error = _("illegal operands"); | |
14501 | ||
14502 | return; | |
14503 | } | |
14504 | } | |
14505 | ||
14506 | /* This structure holds information we know about a mips16 immediate | |
14507 | argument type. */ | |
14508 | ||
e972090a NC |
14509 | struct mips16_immed_operand |
14510 | { | |
252b5132 RH |
14511 | /* The type code used in the argument string in the opcode table. */ |
14512 | int type; | |
14513 | /* The number of bits in the short form of the opcode. */ | |
14514 | int nbits; | |
14515 | /* The number of bits in the extended form of the opcode. */ | |
14516 | int extbits; | |
14517 | /* The amount by which the short form is shifted when it is used; | |
14518 | for example, the sw instruction has a shift count of 2. */ | |
14519 | int shift; | |
14520 | /* The amount by which the short form is shifted when it is stored | |
14521 | into the instruction code. */ | |
14522 | int op_shift; | |
14523 | /* Non-zero if the short form is unsigned. */ | |
14524 | int unsp; | |
14525 | /* Non-zero if the extended form is unsigned. */ | |
14526 | int extu; | |
14527 | /* Non-zero if the value is PC relative. */ | |
14528 | int pcrel; | |
14529 | }; | |
14530 | ||
14531 | /* The mips16 immediate operand types. */ | |
14532 | ||
14533 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
14534 | { | |
14535 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
14536 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
14537 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
14538 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
14539 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
14540 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
14541 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
14542 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
14543 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
14544 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
14545 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
14546 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
14547 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
14548 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
14549 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
14550 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
14551 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
14552 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
14553 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
14554 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
14555 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
14556 | }; | |
14557 | ||
14558 | #define MIPS16_NUM_IMMED \ | |
14559 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
14560 | ||
b886a2ab RS |
14561 | /* Marshal immediate value VAL for an extended MIPS16 instruction. |
14562 | NBITS is the number of significant bits in VAL. */ | |
14563 | ||
14564 | static unsigned long | |
14565 | mips16_immed_extend (offsetT val, unsigned int nbits) | |
14566 | { | |
14567 | int extval; | |
14568 | if (nbits == 16) | |
14569 | { | |
14570 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
14571 | val &= 0x1f; | |
14572 | } | |
14573 | else if (nbits == 15) | |
14574 | { | |
14575 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
14576 | val &= 0xf; | |
14577 | } | |
14578 | else | |
14579 | { | |
14580 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
14581 | val = 0; | |
14582 | } | |
14583 | return (extval << 16) | val; | |
14584 | } | |
14585 | ||
5c04167a RS |
14586 | /* Install immediate value VAL into MIPS16 instruction *INSN, |
14587 | extending it if necessary. The instruction in *INSN may | |
14588 | already be extended. | |
14589 | ||
43c0598f RS |
14590 | RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED |
14591 | if none. In the former case, VAL is a 16-bit number with no | |
14592 | defined signedness. | |
14593 | ||
14594 | TYPE is the type of the immediate field. USER_INSN_LENGTH | |
14595 | is the length that the user requested, or 0 if none. */ | |
252b5132 RH |
14596 | |
14597 | static void | |
43c0598f RS |
14598 | mips16_immed (char *file, unsigned int line, int type, |
14599 | bfd_reloc_code_real_type reloc, offsetT val, | |
5c04167a | 14600 | unsigned int user_insn_length, unsigned long *insn) |
252b5132 | 14601 | { |
3994f87e | 14602 | const struct mips16_immed_operand *op; |
252b5132 | 14603 | int mintiny, maxtiny; |
252b5132 RH |
14604 | |
14605 | op = mips16_immed_operands; | |
14606 | while (op->type != type) | |
14607 | { | |
14608 | ++op; | |
9c2799c2 | 14609 | gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
252b5132 RH |
14610 | } |
14611 | ||
14612 | if (op->unsp) | |
14613 | { | |
14614 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
14615 | { | |
14616 | mintiny = 1; | |
14617 | maxtiny = 1 << op->nbits; | |
14618 | } | |
14619 | else | |
14620 | { | |
14621 | mintiny = 0; | |
14622 | maxtiny = (1 << op->nbits) - 1; | |
14623 | } | |
43c0598f RS |
14624 | if (reloc != BFD_RELOC_UNUSED) |
14625 | val &= 0xffff; | |
252b5132 RH |
14626 | } |
14627 | else | |
14628 | { | |
14629 | mintiny = - (1 << (op->nbits - 1)); | |
14630 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
43c0598f RS |
14631 | if (reloc != BFD_RELOC_UNUSED) |
14632 | val = SEXT_16BIT (val); | |
252b5132 RH |
14633 | } |
14634 | ||
14635 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
14636 | if (type == 'p' || type == 'q') | |
14637 | val /= 2; | |
14638 | ||
14639 | if ((val & ((1 << op->shift) - 1)) != 0 | |
14640 | || val < (mintiny << op->shift) | |
14641 | || val > (maxtiny << op->shift)) | |
5c04167a RS |
14642 | { |
14643 | /* We need an extended instruction. */ | |
14644 | if (user_insn_length == 2) | |
14645 | as_bad_where (file, line, _("invalid unextended operand value")); | |
14646 | else | |
14647 | *insn |= MIPS16_EXTEND; | |
14648 | } | |
14649 | else if (user_insn_length == 4) | |
14650 | { | |
14651 | /* The operand doesn't force an unextended instruction to be extended. | |
14652 | Warn if the user wanted an extended instruction anyway. */ | |
14653 | *insn |= MIPS16_EXTEND; | |
14654 | as_warn_where (file, line, | |
14655 | _("extended operand requested but not required")); | |
14656 | } | |
252b5132 | 14657 | |
5c04167a | 14658 | if (mips16_opcode_length (*insn) == 2) |
252b5132 RH |
14659 | { |
14660 | int insnval; | |
14661 | ||
252b5132 RH |
14662 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
14663 | insnval <<= op->op_shift; | |
14664 | *insn |= insnval; | |
14665 | } | |
14666 | else | |
14667 | { | |
14668 | long minext, maxext; | |
252b5132 | 14669 | |
43c0598f | 14670 | if (reloc == BFD_RELOC_UNUSED) |
252b5132 | 14671 | { |
43c0598f RS |
14672 | if (op->extu) |
14673 | { | |
14674 | minext = 0; | |
14675 | maxext = (1 << op->extbits) - 1; | |
14676 | } | |
14677 | else | |
14678 | { | |
14679 | minext = - (1 << (op->extbits - 1)); | |
14680 | maxext = (1 << (op->extbits - 1)) - 1; | |
14681 | } | |
14682 | if (val < minext || val > maxext) | |
14683 | as_bad_where (file, line, | |
14684 | _("operand value out of range for instruction")); | |
252b5132 | 14685 | } |
252b5132 | 14686 | |
b886a2ab | 14687 | *insn |= mips16_immed_extend (val, op->extbits); |
252b5132 RH |
14688 | } |
14689 | } | |
14690 | \f | |
d6f16593 | 14691 | struct percent_op_match |
ad8d3bb3 | 14692 | { |
5e0116d5 RS |
14693 | const char *str; |
14694 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
14695 | }; |
14696 | ||
14697 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 14698 | { |
5e0116d5 | 14699 | {"%lo", BFD_RELOC_LO16}, |
5e0116d5 RS |
14700 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
14701 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
14702 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
14703 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
14704 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
14705 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
14706 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
14707 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
14708 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
14709 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
14710 | {"%half", BFD_RELOC_16}, | |
14711 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
14712 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
14713 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
14714 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
14715 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
14716 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
14717 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
14718 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
14719 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
14720 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
5e0116d5 | 14721 | {"%hi", BFD_RELOC_HI16_S} |
ad8d3bb3 TS |
14722 | }; |
14723 | ||
d6f16593 MR |
14724 | static const struct percent_op_match mips16_percent_op[] = |
14725 | { | |
14726 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
14727 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, | |
738e5348 RS |
14728 | {"%got", BFD_RELOC_MIPS16_GOT16}, |
14729 | {"%call16", BFD_RELOC_MIPS16_CALL16}, | |
d0f13682 CLT |
14730 | {"%hi", BFD_RELOC_MIPS16_HI16_S}, |
14731 | {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD}, | |
14732 | {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM}, | |
14733 | {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16}, | |
14734 | {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16}, | |
14735 | {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16}, | |
14736 | {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16}, | |
14737 | {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL} | |
d6f16593 MR |
14738 | }; |
14739 | ||
252b5132 | 14740 | |
5e0116d5 RS |
14741 | /* Return true if *STR points to a relocation operator. When returning true, |
14742 | move *STR over the operator and store its relocation code in *RELOC. | |
14743 | Leave both *STR and *RELOC alone when returning false. */ | |
14744 | ||
14745 | static bfd_boolean | |
17a2f251 | 14746 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 14747 | { |
d6f16593 MR |
14748 | const struct percent_op_match *percent_op; |
14749 | size_t limit, i; | |
14750 | ||
14751 | if (mips_opts.mips16) | |
14752 | { | |
14753 | percent_op = mips16_percent_op; | |
14754 | limit = ARRAY_SIZE (mips16_percent_op); | |
14755 | } | |
14756 | else | |
14757 | { | |
14758 | percent_op = mips_percent_op; | |
14759 | limit = ARRAY_SIZE (mips_percent_op); | |
14760 | } | |
76b3015f | 14761 | |
d6f16593 | 14762 | for (i = 0; i < limit; i++) |
5e0116d5 | 14763 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 14764 | { |
3f98094e DJ |
14765 | int len = strlen (percent_op[i].str); |
14766 | ||
14767 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
14768 | continue; | |
14769 | ||
5e0116d5 RS |
14770 | *str += strlen (percent_op[i].str); |
14771 | *reloc = percent_op[i].reloc; | |
394f9b3a | 14772 | |
5e0116d5 RS |
14773 | /* Check whether the output BFD supports this relocation. |
14774 | If not, issue an error and fall back on something safe. */ | |
14775 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 14776 | { |
20203fb9 | 14777 | as_bad (_("relocation %s isn't supported by the current ABI"), |
5e0116d5 | 14778 | percent_op[i].str); |
01a3f561 | 14779 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 14780 | } |
5e0116d5 | 14781 | return TRUE; |
394f9b3a | 14782 | } |
5e0116d5 | 14783 | return FALSE; |
394f9b3a | 14784 | } |
ad8d3bb3 | 14785 | |
ad8d3bb3 | 14786 | |
5e0116d5 RS |
14787 | /* Parse string STR as a 16-bit relocatable operand. Store the |
14788 | expression in *EP and the relocations in the array starting | |
14789 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 14790 | |
01a3f561 | 14791 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 14792 | |
5e0116d5 | 14793 | static size_t |
17a2f251 TS |
14794 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
14795 | char *str) | |
ad8d3bb3 | 14796 | { |
5e0116d5 RS |
14797 | bfd_reloc_code_real_type reversed_reloc[3]; |
14798 | size_t reloc_index, i; | |
09b8f35a RS |
14799 | int crux_depth, str_depth; |
14800 | char *crux; | |
5e0116d5 RS |
14801 | |
14802 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
14803 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
14804 | of the main expression and with CRUX_DEPTH containing the number | |
14805 | of open brackets at that point. */ | |
14806 | reloc_index = -1; | |
14807 | str_depth = 0; | |
14808 | do | |
fb1b3232 | 14809 | { |
09b8f35a RS |
14810 | reloc_index++; |
14811 | crux = str; | |
14812 | crux_depth = str_depth; | |
14813 | ||
14814 | /* Skip over whitespace and brackets, keeping count of the number | |
14815 | of brackets. */ | |
14816 | while (*str == ' ' || *str == '\t' || *str == '(') | |
14817 | if (*str++ == '(') | |
14818 | str_depth++; | |
5e0116d5 | 14819 | } |
09b8f35a RS |
14820 | while (*str == '%' |
14821 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
14822 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 14823 | |
09b8f35a | 14824 | my_getExpression (ep, crux); |
5e0116d5 | 14825 | str = expr_end; |
394f9b3a | 14826 | |
5e0116d5 | 14827 | /* Match every open bracket. */ |
09b8f35a | 14828 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 14829 | if (*str++ == ')') |
09b8f35a | 14830 | crux_depth--; |
394f9b3a | 14831 | |
09b8f35a | 14832 | if (crux_depth > 0) |
20203fb9 | 14833 | as_bad (_("unclosed '('")); |
394f9b3a | 14834 | |
5e0116d5 | 14835 | expr_end = str; |
252b5132 | 14836 | |
01a3f561 | 14837 | if (reloc_index != 0) |
64bdfcaf RS |
14838 | { |
14839 | prev_reloc_op_frag = frag_now; | |
14840 | for (i = 0; i < reloc_index; i++) | |
14841 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
14842 | } | |
fb1b3232 | 14843 | |
5e0116d5 | 14844 | return reloc_index; |
252b5132 RH |
14845 | } |
14846 | ||
14847 | static void | |
17a2f251 | 14848 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
14849 | { |
14850 | char *save_in; | |
14851 | ||
14852 | save_in = input_line_pointer; | |
14853 | input_line_pointer = str; | |
14854 | expression (ep); | |
14855 | expr_end = input_line_pointer; | |
14856 | input_line_pointer = save_in; | |
252b5132 RH |
14857 | } |
14858 | ||
252b5132 | 14859 | char * |
17a2f251 | 14860 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 14861 | { |
499ac353 | 14862 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
252b5132 RH |
14863 | } |
14864 | ||
14865 | void | |
17a2f251 | 14866 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
14867 | { |
14868 | if (target_big_endian) | |
14869 | number_to_chars_bigendian (buf, val, n); | |
14870 | else | |
14871 | number_to_chars_littleendian (buf, val, n); | |
14872 | } | |
14873 | \f | |
e013f690 TS |
14874 | static int support_64bit_objects(void) |
14875 | { | |
14876 | const char **list, **l; | |
aa3d8fdf | 14877 | int yes; |
e013f690 TS |
14878 | |
14879 | list = bfd_target_list (); | |
14880 | for (l = list; *l != NULL; l++) | |
aeffff67 RS |
14881 | if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0 |
14882 | || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0) | |
e013f690 | 14883 | break; |
aa3d8fdf | 14884 | yes = (*l != NULL); |
e013f690 | 14885 | free (list); |
aa3d8fdf | 14886 | return yes; |
e013f690 TS |
14887 | } |
14888 | ||
316f5878 RS |
14889 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
14890 | NEW_VALUE. Warn if another value was already specified. Note: | |
14891 | we have to defer parsing the -march and -mtune arguments in order | |
14892 | to handle 'from-abi' correctly, since the ABI might be specified | |
14893 | in a later argument. */ | |
14894 | ||
14895 | static void | |
17a2f251 | 14896 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
14897 | { |
14898 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
14899 | as_warn (_("A different %s was already specified, is now %s"), | |
14900 | string_ptr == &mips_arch_string ? "-march" : "-mtune", | |
14901 | new_value); | |
14902 | ||
14903 | *string_ptr = new_value; | |
14904 | } | |
14905 | ||
252b5132 | 14906 | int |
17a2f251 | 14907 | md_parse_option (int c, char *arg) |
252b5132 | 14908 | { |
c6278170 RS |
14909 | unsigned int i; |
14910 | ||
14911 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
14912 | if (c == mips_ases[i].option_on || c == mips_ases[i].option_off) | |
14913 | { | |
14914 | file_ase_explicit |= mips_set_ase (&mips_ases[i], | |
14915 | c == mips_ases[i].option_on); | |
14916 | return 1; | |
14917 | } | |
14918 | ||
252b5132 RH |
14919 | switch (c) |
14920 | { | |
119d663a NC |
14921 | case OPTION_CONSTRUCT_FLOATS: |
14922 | mips_disable_float_construction = 0; | |
14923 | break; | |
bdaaa2e1 | 14924 | |
119d663a NC |
14925 | case OPTION_NO_CONSTRUCT_FLOATS: |
14926 | mips_disable_float_construction = 1; | |
14927 | break; | |
bdaaa2e1 | 14928 | |
252b5132 RH |
14929 | case OPTION_TRAP: |
14930 | mips_trap = 1; | |
14931 | break; | |
14932 | ||
14933 | case OPTION_BREAK: | |
14934 | mips_trap = 0; | |
14935 | break; | |
14936 | ||
14937 | case OPTION_EB: | |
14938 | target_big_endian = 1; | |
14939 | break; | |
14940 | ||
14941 | case OPTION_EL: | |
14942 | target_big_endian = 0; | |
14943 | break; | |
14944 | ||
14945 | case 'O': | |
4ffff32f TS |
14946 | if (arg == NULL) |
14947 | mips_optimize = 1; | |
14948 | else if (arg[0] == '0') | |
14949 | mips_optimize = 0; | |
14950 | else if (arg[0] == '1') | |
252b5132 RH |
14951 | mips_optimize = 1; |
14952 | else | |
14953 | mips_optimize = 2; | |
14954 | break; | |
14955 | ||
14956 | case 'g': | |
14957 | if (arg == NULL) | |
14958 | mips_debug = 2; | |
14959 | else | |
14960 | mips_debug = atoi (arg); | |
252b5132 RH |
14961 | break; |
14962 | ||
14963 | case OPTION_MIPS1: | |
316f5878 | 14964 | file_mips_isa = ISA_MIPS1; |
252b5132 RH |
14965 | break; |
14966 | ||
14967 | case OPTION_MIPS2: | |
316f5878 | 14968 | file_mips_isa = ISA_MIPS2; |
252b5132 RH |
14969 | break; |
14970 | ||
14971 | case OPTION_MIPS3: | |
316f5878 | 14972 | file_mips_isa = ISA_MIPS3; |
252b5132 RH |
14973 | break; |
14974 | ||
14975 | case OPTION_MIPS4: | |
316f5878 | 14976 | file_mips_isa = ISA_MIPS4; |
e7af610e NC |
14977 | break; |
14978 | ||
84ea6cf2 | 14979 | case OPTION_MIPS5: |
316f5878 | 14980 | file_mips_isa = ISA_MIPS5; |
84ea6cf2 NC |
14981 | break; |
14982 | ||
e7af610e | 14983 | case OPTION_MIPS32: |
316f5878 | 14984 | file_mips_isa = ISA_MIPS32; |
252b5132 RH |
14985 | break; |
14986 | ||
af7ee8bf CD |
14987 | case OPTION_MIPS32R2: |
14988 | file_mips_isa = ISA_MIPS32R2; | |
14989 | break; | |
14990 | ||
5f74bc13 CD |
14991 | case OPTION_MIPS64R2: |
14992 | file_mips_isa = ISA_MIPS64R2; | |
14993 | break; | |
14994 | ||
84ea6cf2 | 14995 | case OPTION_MIPS64: |
316f5878 | 14996 | file_mips_isa = ISA_MIPS64; |
84ea6cf2 NC |
14997 | break; |
14998 | ||
ec68c924 | 14999 | case OPTION_MTUNE: |
316f5878 RS |
15000 | mips_set_option_string (&mips_tune_string, arg); |
15001 | break; | |
ec68c924 | 15002 | |
316f5878 RS |
15003 | case OPTION_MARCH: |
15004 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
15005 | break; |
15006 | ||
15007 | case OPTION_M4650: | |
316f5878 RS |
15008 | mips_set_option_string (&mips_arch_string, "4650"); |
15009 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
15010 | break; |
15011 | ||
15012 | case OPTION_NO_M4650: | |
15013 | break; | |
15014 | ||
15015 | case OPTION_M4010: | |
316f5878 RS |
15016 | mips_set_option_string (&mips_arch_string, "4010"); |
15017 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
15018 | break; |
15019 | ||
15020 | case OPTION_NO_M4010: | |
15021 | break; | |
15022 | ||
15023 | case OPTION_M4100: | |
316f5878 RS |
15024 | mips_set_option_string (&mips_arch_string, "4100"); |
15025 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
15026 | break; |
15027 | ||
15028 | case OPTION_NO_M4100: | |
15029 | break; | |
15030 | ||
252b5132 | 15031 | case OPTION_M3900: |
316f5878 RS |
15032 | mips_set_option_string (&mips_arch_string, "3900"); |
15033 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 15034 | break; |
bdaaa2e1 | 15035 | |
252b5132 RH |
15036 | case OPTION_NO_M3900: |
15037 | break; | |
15038 | ||
df58fc94 RS |
15039 | case OPTION_MICROMIPS: |
15040 | if (mips_opts.mips16 == 1) | |
15041 | { | |
15042 | as_bad (_("-mmicromips cannot be used with -mips16")); | |
15043 | return 0; | |
15044 | } | |
15045 | mips_opts.micromips = 1; | |
15046 | mips_no_prev_insn (); | |
15047 | break; | |
15048 | ||
15049 | case OPTION_NO_MICROMIPS: | |
15050 | mips_opts.micromips = 0; | |
15051 | mips_no_prev_insn (); | |
15052 | break; | |
15053 | ||
252b5132 | 15054 | case OPTION_MIPS16: |
df58fc94 RS |
15055 | if (mips_opts.micromips == 1) |
15056 | { | |
15057 | as_bad (_("-mips16 cannot be used with -micromips")); | |
15058 | return 0; | |
15059 | } | |
252b5132 | 15060 | mips_opts.mips16 = 1; |
7d10b47d | 15061 | mips_no_prev_insn (); |
252b5132 RH |
15062 | break; |
15063 | ||
15064 | case OPTION_NO_MIPS16: | |
15065 | mips_opts.mips16 = 0; | |
7d10b47d | 15066 | mips_no_prev_insn (); |
252b5132 RH |
15067 | break; |
15068 | ||
6a32d874 CM |
15069 | case OPTION_FIX_24K: |
15070 | mips_fix_24k = 1; | |
15071 | break; | |
15072 | ||
15073 | case OPTION_NO_FIX_24K: | |
15074 | mips_fix_24k = 0; | |
15075 | break; | |
15076 | ||
c67a084a NC |
15077 | case OPTION_FIX_LOONGSON2F_JUMP: |
15078 | mips_fix_loongson2f_jump = TRUE; | |
15079 | break; | |
15080 | ||
15081 | case OPTION_NO_FIX_LOONGSON2F_JUMP: | |
15082 | mips_fix_loongson2f_jump = FALSE; | |
15083 | break; | |
15084 | ||
15085 | case OPTION_FIX_LOONGSON2F_NOP: | |
15086 | mips_fix_loongson2f_nop = TRUE; | |
15087 | break; | |
15088 | ||
15089 | case OPTION_NO_FIX_LOONGSON2F_NOP: | |
15090 | mips_fix_loongson2f_nop = FALSE; | |
15091 | break; | |
15092 | ||
d766e8ec RS |
15093 | case OPTION_FIX_VR4120: |
15094 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
15095 | break; |
15096 | ||
d766e8ec RS |
15097 | case OPTION_NO_FIX_VR4120: |
15098 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
15099 | break; |
15100 | ||
7d8e00cf RS |
15101 | case OPTION_FIX_VR4130: |
15102 | mips_fix_vr4130 = 1; | |
15103 | break; | |
15104 | ||
15105 | case OPTION_NO_FIX_VR4130: | |
15106 | mips_fix_vr4130 = 0; | |
15107 | break; | |
15108 | ||
d954098f DD |
15109 | case OPTION_FIX_CN63XXP1: |
15110 | mips_fix_cn63xxp1 = TRUE; | |
15111 | break; | |
15112 | ||
15113 | case OPTION_NO_FIX_CN63XXP1: | |
15114 | mips_fix_cn63xxp1 = FALSE; | |
15115 | break; | |
15116 | ||
4a6a3df4 AO |
15117 | case OPTION_RELAX_BRANCH: |
15118 | mips_relax_branch = 1; | |
15119 | break; | |
15120 | ||
15121 | case OPTION_NO_RELAX_BRANCH: | |
15122 | mips_relax_branch = 0; | |
15123 | break; | |
15124 | ||
833794fc MR |
15125 | case OPTION_INSN32: |
15126 | mips_opts.insn32 = TRUE; | |
15127 | break; | |
15128 | ||
15129 | case OPTION_NO_INSN32: | |
15130 | mips_opts.insn32 = FALSE; | |
15131 | break; | |
15132 | ||
aa6975fb ILT |
15133 | case OPTION_MSHARED: |
15134 | mips_in_shared = TRUE; | |
15135 | break; | |
15136 | ||
15137 | case OPTION_MNO_SHARED: | |
15138 | mips_in_shared = FALSE; | |
15139 | break; | |
15140 | ||
aed1a261 RS |
15141 | case OPTION_MSYM32: |
15142 | mips_opts.sym32 = TRUE; | |
15143 | break; | |
15144 | ||
15145 | case OPTION_MNO_SYM32: | |
15146 | mips_opts.sym32 = FALSE; | |
15147 | break; | |
15148 | ||
252b5132 RH |
15149 | /* When generating ELF code, we permit -KPIC and -call_shared to |
15150 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
15151 | intended to be compatible with Irix 5. */ | |
15152 | case OPTION_CALL_SHARED: | |
252b5132 | 15153 | mips_pic = SVR4_PIC; |
143d77c5 | 15154 | mips_abicalls = TRUE; |
252b5132 RH |
15155 | break; |
15156 | ||
861fb55a | 15157 | case OPTION_CALL_NONPIC: |
861fb55a DJ |
15158 | mips_pic = NO_PIC; |
15159 | mips_abicalls = TRUE; | |
15160 | break; | |
15161 | ||
252b5132 | 15162 | case OPTION_NON_SHARED: |
252b5132 | 15163 | mips_pic = NO_PIC; |
143d77c5 | 15164 | mips_abicalls = FALSE; |
252b5132 RH |
15165 | break; |
15166 | ||
44075ae2 TS |
15167 | /* The -xgot option tells the assembler to use 32 bit offsets |
15168 | when accessing the got in SVR4_PIC mode. It is for Irix | |
252b5132 RH |
15169 | compatibility. */ |
15170 | case OPTION_XGOT: | |
15171 | mips_big_got = 1; | |
15172 | break; | |
15173 | ||
15174 | case 'G': | |
6caf9ef4 TS |
15175 | g_switch_value = atoi (arg); |
15176 | g_switch_seen = 1; | |
252b5132 RH |
15177 | break; |
15178 | ||
34ba82a8 TS |
15179 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
15180 | and -mabi=64. */ | |
252b5132 | 15181 | case OPTION_32: |
f3ded42a | 15182 | mips_abi = O32_ABI; |
252b5132 RH |
15183 | break; |
15184 | ||
e013f690 | 15185 | case OPTION_N32: |
316f5878 | 15186 | mips_abi = N32_ABI; |
e013f690 | 15187 | break; |
252b5132 | 15188 | |
e013f690 | 15189 | case OPTION_64: |
316f5878 | 15190 | mips_abi = N64_ABI; |
f43abd2b | 15191 | if (!support_64bit_objects()) |
e013f690 | 15192 | as_fatal (_("No compiled in support for 64 bit object file format")); |
252b5132 RH |
15193 | break; |
15194 | ||
c97ef257 | 15195 | case OPTION_GP32: |
a325df1d | 15196 | file_mips_gp32 = 1; |
c97ef257 AH |
15197 | break; |
15198 | ||
15199 | case OPTION_GP64: | |
a325df1d | 15200 | file_mips_gp32 = 0; |
c97ef257 | 15201 | break; |
252b5132 | 15202 | |
ca4e0257 | 15203 | case OPTION_FP32: |
a325df1d | 15204 | file_mips_fp32 = 1; |
316f5878 RS |
15205 | break; |
15206 | ||
15207 | case OPTION_FP64: | |
15208 | file_mips_fp32 = 0; | |
ca4e0257 RS |
15209 | break; |
15210 | ||
037b32b9 AN |
15211 | case OPTION_SINGLE_FLOAT: |
15212 | file_mips_single_float = 1; | |
15213 | break; | |
15214 | ||
15215 | case OPTION_DOUBLE_FLOAT: | |
15216 | file_mips_single_float = 0; | |
15217 | break; | |
15218 | ||
15219 | case OPTION_SOFT_FLOAT: | |
15220 | file_mips_soft_float = 1; | |
15221 | break; | |
15222 | ||
15223 | case OPTION_HARD_FLOAT: | |
15224 | file_mips_soft_float = 0; | |
15225 | break; | |
15226 | ||
252b5132 | 15227 | case OPTION_MABI: |
e013f690 | 15228 | if (strcmp (arg, "32") == 0) |
316f5878 | 15229 | mips_abi = O32_ABI; |
e013f690 | 15230 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 15231 | mips_abi = O64_ABI; |
e013f690 | 15232 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 15233 | mips_abi = N32_ABI; |
e013f690 TS |
15234 | else if (strcmp (arg, "64") == 0) |
15235 | { | |
316f5878 | 15236 | mips_abi = N64_ABI; |
e013f690 TS |
15237 | if (! support_64bit_objects()) |
15238 | as_fatal (_("No compiled in support for 64 bit object file " | |
15239 | "format")); | |
15240 | } | |
15241 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 15242 | mips_abi = EABI_ABI; |
e013f690 | 15243 | else |
da0e507f TS |
15244 | { |
15245 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
15246 | return 0; | |
15247 | } | |
252b5132 RH |
15248 | break; |
15249 | ||
6b76fefe | 15250 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 15251 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
15252 | break; |
15253 | ||
9ee72ff1 | 15254 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 15255 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
15256 | break; |
15257 | ||
ecb4347a | 15258 | case OPTION_MDEBUG: |
b34976b6 | 15259 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
15260 | break; |
15261 | ||
15262 | case OPTION_NO_MDEBUG: | |
b34976b6 | 15263 | mips_flag_mdebug = FALSE; |
ecb4347a | 15264 | break; |
dcd410fe RO |
15265 | |
15266 | case OPTION_PDR: | |
15267 | mips_flag_pdr = TRUE; | |
15268 | break; | |
15269 | ||
15270 | case OPTION_NO_PDR: | |
15271 | mips_flag_pdr = FALSE; | |
15272 | break; | |
0a44bf69 RS |
15273 | |
15274 | case OPTION_MVXWORKS_PIC: | |
15275 | mips_pic = VXWORKS_PIC; | |
15276 | break; | |
ecb4347a | 15277 | |
ba92f887 MR |
15278 | case OPTION_NAN: |
15279 | if (strcmp (arg, "2008") == 0) | |
15280 | mips_flag_nan2008 = TRUE; | |
15281 | else if (strcmp (arg, "legacy") == 0) | |
15282 | mips_flag_nan2008 = FALSE; | |
15283 | else | |
15284 | { | |
15285 | as_fatal (_("Invalid NaN setting -mnan=%s"), arg); | |
15286 | return 0; | |
15287 | } | |
15288 | break; | |
15289 | ||
252b5132 RH |
15290 | default: |
15291 | return 0; | |
15292 | } | |
15293 | ||
c67a084a NC |
15294 | mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump; |
15295 | ||
252b5132 RH |
15296 | return 1; |
15297 | } | |
316f5878 RS |
15298 | \f |
15299 | /* Set up globals to generate code for the ISA or processor | |
15300 | described by INFO. */ | |
252b5132 | 15301 | |
252b5132 | 15302 | static void |
17a2f251 | 15303 | mips_set_architecture (const struct mips_cpu_info *info) |
252b5132 | 15304 | { |
316f5878 | 15305 | if (info != 0) |
252b5132 | 15306 | { |
fef14a42 TS |
15307 | file_mips_arch = info->cpu; |
15308 | mips_opts.arch = info->cpu; | |
316f5878 | 15309 | mips_opts.isa = info->isa; |
252b5132 | 15310 | } |
252b5132 RH |
15311 | } |
15312 | ||
252b5132 | 15313 | |
316f5878 | 15314 | /* Likewise for tuning. */ |
252b5132 | 15315 | |
316f5878 | 15316 | static void |
17a2f251 | 15317 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
15318 | { |
15319 | if (info != 0) | |
fef14a42 | 15320 | mips_tune = info->cpu; |
316f5878 | 15321 | } |
80cc45a5 | 15322 | |
34ba82a8 | 15323 | |
252b5132 | 15324 | void |
17a2f251 | 15325 | mips_after_parse_args (void) |
e9670677 | 15326 | { |
fef14a42 TS |
15327 | const struct mips_cpu_info *arch_info = 0; |
15328 | const struct mips_cpu_info *tune_info = 0; | |
15329 | ||
e9670677 | 15330 | /* GP relative stuff not working for PE */ |
6caf9ef4 | 15331 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
e9670677 | 15332 | { |
6caf9ef4 | 15333 | if (g_switch_seen && g_switch_value != 0) |
e9670677 MR |
15334 | as_bad (_("-G not supported in this configuration.")); |
15335 | g_switch_value = 0; | |
15336 | } | |
15337 | ||
cac012d6 AO |
15338 | if (mips_abi == NO_ABI) |
15339 | mips_abi = MIPS_DEFAULT_ABI; | |
15340 | ||
22923709 RS |
15341 | /* The following code determines the architecture and register size. |
15342 | Similar code was added to GCC 3.3 (see override_options() in | |
15343 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
15344 | as much as possible. */ | |
e9670677 | 15345 | |
316f5878 | 15346 | if (mips_arch_string != 0) |
fef14a42 | 15347 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 15348 | |
316f5878 | 15349 | if (file_mips_isa != ISA_UNKNOWN) |
e9670677 | 15350 | { |
316f5878 | 15351 | /* Handle -mipsN. At this point, file_mips_isa contains the |
fef14a42 | 15352 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 15353 | the -march selection (if any). */ |
fef14a42 | 15354 | if (arch_info != 0) |
e9670677 | 15355 | { |
316f5878 RS |
15356 | /* -march takes precedence over -mipsN, since it is more descriptive. |
15357 | There's no harm in specifying both as long as the ISA levels | |
15358 | are the same. */ | |
fef14a42 | 15359 | if (file_mips_isa != arch_info->isa) |
316f5878 RS |
15360 | as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), |
15361 | mips_cpu_info_from_isa (file_mips_isa)->name, | |
fef14a42 | 15362 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 15363 | } |
316f5878 | 15364 | else |
fef14a42 | 15365 | arch_info = mips_cpu_info_from_isa (file_mips_isa); |
e9670677 MR |
15366 | } |
15367 | ||
fef14a42 | 15368 | if (arch_info == 0) |
95bfe26e MF |
15369 | { |
15370 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
15371 | gas_assert (arch_info); | |
15372 | } | |
e9670677 | 15373 | |
fef14a42 | 15374 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
20203fb9 | 15375 | as_bad (_("-march=%s is not compatible with the selected ABI"), |
fef14a42 TS |
15376 | arch_info->name); |
15377 | ||
15378 | mips_set_architecture (arch_info); | |
15379 | ||
15380 | /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ | |
15381 | if (mips_tune_string != 0) | |
15382 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 15383 | |
fef14a42 TS |
15384 | if (tune_info == 0) |
15385 | mips_set_tune (arch_info); | |
15386 | else | |
15387 | mips_set_tune (tune_info); | |
e9670677 | 15388 | |
316f5878 | 15389 | if (file_mips_gp32 >= 0) |
e9670677 | 15390 | { |
316f5878 RS |
15391 | /* The user specified the size of the integer registers. Make sure |
15392 | it agrees with the ABI and ISA. */ | |
15393 | if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
15394 | as_bad (_("-mgp64 used with a 32-bit processor")); | |
15395 | else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
15396 | as_bad (_("-mgp32 used with a 64-bit ABI")); | |
15397 | else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
15398 | as_bad (_("-mgp64 used with a 32-bit ABI")); | |
e9670677 MR |
15399 | } |
15400 | else | |
15401 | { | |
316f5878 RS |
15402 | /* Infer the integer register size from the ABI and processor. |
15403 | Restrict ourselves to 32-bit registers if that's all the | |
15404 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
15405 | file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
15406 | || !ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
e9670677 MR |
15407 | } |
15408 | ||
ad3fea08 TS |
15409 | switch (file_mips_fp32) |
15410 | { | |
15411 | default: | |
15412 | case -1: | |
15413 | /* No user specified float register size. | |
15414 | ??? GAS treats single-float processors as though they had 64-bit | |
15415 | float registers (although it complains when double-precision | |
15416 | instructions are used). As things stand, saying they have 32-bit | |
15417 | registers would lead to spurious "register must be even" messages. | |
15418 | So here we assume float registers are never smaller than the | |
15419 | integer ones. */ | |
15420 | if (file_mips_gp32 == 0) | |
15421 | /* 64-bit integer registers implies 64-bit float registers. */ | |
15422 | file_mips_fp32 = 0; | |
c6278170 | 15423 | else if ((mips_opts.ase & FP64_ASES) |
ad3fea08 TS |
15424 | && ISA_HAS_64BIT_FPRS (mips_opts.isa)) |
15425 | /* -mips3d and -mdmx imply 64-bit float registers, if possible. */ | |
15426 | file_mips_fp32 = 0; | |
15427 | else | |
15428 | /* 32-bit float registers. */ | |
15429 | file_mips_fp32 = 1; | |
15430 | break; | |
15431 | ||
15432 | /* The user specified the size of the float registers. Check if it | |
15433 | agrees with the ABI and ISA. */ | |
15434 | case 0: | |
15435 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
15436 | as_bad (_("-mfp64 used with a 32-bit fpu")); | |
15437 | else if (ABI_NEEDS_32BIT_REGS (mips_abi) | |
15438 | && !ISA_HAS_MXHC1 (mips_opts.isa)) | |
15439 | as_warn (_("-mfp64 used with a 32-bit ABI")); | |
15440 | break; | |
15441 | case 1: | |
15442 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
15443 | as_warn (_("-mfp32 used with a 64-bit ABI")); | |
15444 | break; | |
15445 | } | |
e9670677 | 15446 | |
316f5878 | 15447 | /* End of GCC-shared inference code. */ |
e9670677 | 15448 | |
17a2f251 TS |
15449 | /* This flag is set when we have a 64-bit capable CPU but use only |
15450 | 32-bit wide registers. Note that EABI does not use it. */ | |
15451 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) | |
15452 | && ((mips_abi == NO_ABI && file_mips_gp32 == 1) | |
15453 | || mips_abi == O32_ABI)) | |
316f5878 | 15454 | mips_32bitmode = 1; |
e9670677 MR |
15455 | |
15456 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) | |
15457 | as_bad (_("trap exception not supported at ISA 1")); | |
15458 | ||
e9670677 MR |
15459 | /* If the selected architecture includes support for ASEs, enable |
15460 | generation of code for them. */ | |
a4672219 | 15461 | if (mips_opts.mips16 == -1) |
fef14a42 | 15462 | mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; |
df58fc94 RS |
15463 | if (mips_opts.micromips == -1) |
15464 | mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0; | |
846ef2d0 RS |
15465 | |
15466 | /* MIPS3D and MDMX require 64-bit FPRs, so -mfp32 should stop those | |
15467 | ASEs from being selected implicitly. */ | |
15468 | if (file_mips_fp32 == 1) | |
15469 | file_ase_explicit |= ASE_MIPS3D | ASE_MDMX; | |
15470 | ||
15471 | /* If the user didn't explicitly select or deselect a particular ASE, | |
15472 | use the default setting for the CPU. */ | |
15473 | mips_opts.ase |= (arch_info->ase & ~file_ase_explicit); | |
15474 | ||
e9670677 | 15475 | file_mips_isa = mips_opts.isa; |
846ef2d0 | 15476 | file_ase = mips_opts.ase; |
e9670677 MR |
15477 | mips_opts.gp32 = file_mips_gp32; |
15478 | mips_opts.fp32 = file_mips_fp32; | |
037b32b9 AN |
15479 | mips_opts.soft_float = file_mips_soft_float; |
15480 | mips_opts.single_float = file_mips_single_float; | |
e9670677 | 15481 | |
c6278170 RS |
15482 | mips_check_isa_supports_ases (); |
15483 | ||
ecb4347a | 15484 | if (mips_flag_mdebug < 0) |
e8044f35 | 15485 | mips_flag_mdebug = 0; |
e9670677 MR |
15486 | } |
15487 | \f | |
15488 | void | |
17a2f251 | 15489 | mips_init_after_args (void) |
252b5132 RH |
15490 | { |
15491 | /* initialize opcodes */ | |
15492 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 15493 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
15494 | } |
15495 | ||
15496 | long | |
17a2f251 | 15497 | md_pcrel_from (fixS *fixP) |
252b5132 | 15498 | { |
a7ebbfdf TS |
15499 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
15500 | switch (fixP->fx_r_type) | |
15501 | { | |
df58fc94 RS |
15502 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15503 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15504 | /* Return the address of the delay slot. */ | |
15505 | return addr + 2; | |
15506 | ||
15507 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15508 | case BFD_RELOC_MICROMIPS_JMP: | |
a7ebbfdf TS |
15509 | case BFD_RELOC_16_PCREL_S2: |
15510 | case BFD_RELOC_MIPS_JMP: | |
15511 | /* Return the address of the delay slot. */ | |
15512 | return addr + 4; | |
df58fc94 | 15513 | |
b47468a6 CM |
15514 | case BFD_RELOC_32_PCREL: |
15515 | return addr; | |
15516 | ||
a7ebbfdf | 15517 | default: |
58ea3d6a | 15518 | /* We have no relocation type for PC relative MIPS16 instructions. */ |
64817874 TS |
15519 | if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg) |
15520 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15521 | _("PC relative MIPS16 instruction references a different section")); | |
a7ebbfdf TS |
15522 | return addr; |
15523 | } | |
252b5132 RH |
15524 | } |
15525 | ||
252b5132 RH |
15526 | /* This is called before the symbol table is processed. In order to |
15527 | work with gcc when using mips-tfile, we must keep all local labels. | |
15528 | However, in other cases, we want to discard them. If we were | |
15529 | called with -g, but we didn't see any debugging information, it may | |
15530 | mean that gcc is smuggling debugging information through to | |
15531 | mips-tfile, in which case we must generate all local labels. */ | |
15532 | ||
15533 | void | |
17a2f251 | 15534 | mips_frob_file_before_adjust (void) |
252b5132 RH |
15535 | { |
15536 | #ifndef NO_ECOFF_DEBUGGING | |
15537 | if (ECOFF_DEBUGGING | |
15538 | && mips_debug != 0 | |
15539 | && ! ecoff_debugging_seen) | |
15540 | flag_keep_locals = 1; | |
15541 | #endif | |
15542 | } | |
15543 | ||
3b91255e | 15544 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
55cf6793 | 15545 | the corresponding LO16 reloc. This is called before md_apply_fix and |
3b91255e RS |
15546 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit |
15547 | relocation operators. | |
15548 | ||
15549 | For our purposes, a %lo() expression matches a %got() or %hi() | |
15550 | expression if: | |
15551 | ||
15552 | (a) it refers to the same symbol; and | |
15553 | (b) the offset applied in the %lo() expression is no lower than | |
15554 | the offset applied in the %got() or %hi(). | |
15555 | ||
15556 | (b) allows us to cope with code like: | |
15557 | ||
15558 | lui $4,%hi(foo) | |
15559 | lh $4,%lo(foo+2)($4) | |
15560 | ||
15561 | ...which is legal on RELA targets, and has a well-defined behaviour | |
15562 | if the user knows that adding 2 to "foo" will not induce a carry to | |
15563 | the high 16 bits. | |
15564 | ||
15565 | When several %lo()s match a particular %got() or %hi(), we use the | |
15566 | following rules to distinguish them: | |
15567 | ||
15568 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
15569 | higher offsets. | |
15570 | ||
15571 | (2) %lo()s with no matching %got() or %hi() are better than those | |
15572 | that already have a matching %got() or %hi(). | |
15573 | ||
15574 | (3) later %lo()s are better than earlier %lo()s. | |
15575 | ||
15576 | These rules are applied in order. | |
15577 | ||
15578 | (1) means, among other things, that %lo()s with identical offsets are | |
15579 | chosen if they exist. | |
15580 | ||
15581 | (2) means that we won't associate several high-part relocations with | |
15582 | the same low-part relocation unless there's no alternative. Having | |
15583 | several high parts for the same low part is a GNU extension; this rule | |
15584 | allows careful users to avoid it. | |
15585 | ||
15586 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
15587 | with the last high-part relocation being at the front of the list. | |
15588 | It therefore makes sense to choose the last matching low-part | |
15589 | relocation, all other things being equal. It's also easier | |
15590 | to code that way. */ | |
252b5132 RH |
15591 | |
15592 | void | |
17a2f251 | 15593 | mips_frob_file (void) |
252b5132 RH |
15594 | { |
15595 | struct mips_hi_fixup *l; | |
35903be0 | 15596 | bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED; |
252b5132 RH |
15597 | |
15598 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
15599 | { | |
15600 | segment_info_type *seginfo; | |
3b91255e RS |
15601 | bfd_boolean matched_lo_p; |
15602 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 15603 | |
9c2799c2 | 15604 | gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 15605 | |
5919d012 | 15606 | /* If a GOT16 relocation turns out to be against a global symbol, |
b886a2ab RS |
15607 | there isn't supposed to be a matching LO. Ignore %gots against |
15608 | constants; we'll report an error for those later. */ | |
738e5348 | 15609 | if (got16_reloc_p (l->fixp->fx_r_type) |
b886a2ab RS |
15610 | && !(l->fixp->fx_addsy |
15611 | && pic_need_relax (l->fixp->fx_addsy, l->seg))) | |
5919d012 RS |
15612 | continue; |
15613 | ||
15614 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
15615 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
15616 | continue; |
15617 | ||
252b5132 | 15618 | seginfo = seg_info (l->seg); |
252b5132 | 15619 | |
3b91255e RS |
15620 | /* Set HI_POS to the position of this relocation in the chain. |
15621 | Set LO_POS to the position of the chosen low-part relocation. | |
15622 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
15623 | relocation that matches an immediately-preceding high-part | |
15624 | relocation. */ | |
15625 | hi_pos = NULL; | |
15626 | lo_pos = NULL; | |
15627 | matched_lo_p = FALSE; | |
738e5348 | 15628 | looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type); |
35903be0 | 15629 | |
3b91255e RS |
15630 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) |
15631 | { | |
15632 | if (*pos == l->fixp) | |
15633 | hi_pos = pos; | |
15634 | ||
35903be0 | 15635 | if ((*pos)->fx_r_type == looking_for_rtype |
30cfc97a | 15636 | && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy) |
3b91255e RS |
15637 | && (*pos)->fx_offset >= l->fixp->fx_offset |
15638 | && (lo_pos == NULL | |
15639 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
15640 | || (!matched_lo_p | |
15641 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
15642 | lo_pos = pos; | |
15643 | ||
15644 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
15645 | && fixup_has_matching_lo_p (*pos)); | |
15646 | } | |
15647 | ||
15648 | /* If we found a match, remove the high-part relocation from its | |
15649 | current position and insert it before the low-part relocation. | |
15650 | Make the offsets match so that fixup_has_matching_lo_p() | |
15651 | will return true. | |
15652 | ||
15653 | We don't warn about unmatched high-part relocations since some | |
15654 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
15655 | instructions. */ | |
15656 | if (lo_pos != NULL) | |
15657 | { | |
15658 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
15659 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 15660 | { |
3b91255e RS |
15661 | *hi_pos = l->fixp->fx_next; |
15662 | l->fixp->fx_next = *lo_pos; | |
15663 | *lo_pos = l->fixp; | |
252b5132 | 15664 | } |
252b5132 RH |
15665 | } |
15666 | } | |
15667 | } | |
15668 | ||
252b5132 | 15669 | int |
17a2f251 | 15670 | mips_force_relocation (fixS *fixp) |
252b5132 | 15671 | { |
ae6063d4 | 15672 | if (generic_force_reloc (fixp)) |
252b5132 RH |
15673 | return 1; |
15674 | ||
df58fc94 RS |
15675 | /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation, |
15676 | so that the linker relaxation can update targets. */ | |
15677 | if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
15678 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
15679 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1) | |
15680 | return 1; | |
15681 | ||
3e722fb5 | 15682 | return 0; |
252b5132 RH |
15683 | } |
15684 | ||
b886a2ab RS |
15685 | /* Read the instruction associated with RELOC from BUF. */ |
15686 | ||
15687 | static unsigned int | |
15688 | read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc) | |
15689 | { | |
15690 | if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) | |
15691 | return read_compressed_insn (buf, 4); | |
15692 | else | |
15693 | return read_insn (buf); | |
15694 | } | |
15695 | ||
15696 | /* Write instruction INSN to BUF, given that it has been relocated | |
15697 | by RELOC. */ | |
15698 | ||
15699 | static void | |
15700 | write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc, | |
15701 | unsigned long insn) | |
15702 | { | |
15703 | if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) | |
15704 | write_compressed_insn (buf, insn, 4); | |
15705 | else | |
15706 | write_insn (buf, insn); | |
15707 | } | |
15708 | ||
252b5132 RH |
15709 | /* Apply a fixup to the object file. */ |
15710 | ||
94f592af | 15711 | void |
55cf6793 | 15712 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 15713 | { |
4d68580a | 15714 | char *buf; |
b886a2ab | 15715 | unsigned long insn; |
a7ebbfdf | 15716 | reloc_howto_type *howto; |
252b5132 | 15717 | |
a7ebbfdf TS |
15718 | /* We ignore generic BFD relocations we don't know about. */ |
15719 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
15720 | if (! howto) | |
15721 | return; | |
65551fa4 | 15722 | |
df58fc94 RS |
15723 | gas_assert (fixP->fx_size == 2 |
15724 | || fixP->fx_size == 4 | |
90ecf173 MR |
15725 | || fixP->fx_r_type == BFD_RELOC_16 |
15726 | || fixP->fx_r_type == BFD_RELOC_64 | |
15727 | || fixP->fx_r_type == BFD_RELOC_CTOR | |
15728 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
df58fc94 | 15729 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB |
90ecf173 MR |
15730 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
15731 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY | |
15732 | || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64); | |
252b5132 | 15733 | |
4d68580a | 15734 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; |
252b5132 | 15735 | |
df58fc94 RS |
15736 | gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2 |
15737 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
15738 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
b47468a6 CM |
15739 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1 |
15740 | || fixP->fx_r_type == BFD_RELOC_32_PCREL); | |
b1dca8ee RS |
15741 | |
15742 | /* Don't treat parts of a composite relocation as done. There are two | |
15743 | reasons for this: | |
15744 | ||
15745 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
15746 | should nevertheless be emitted if the first part is. | |
15747 | ||
15748 | (2) In normal usage, composite relocations are never assembly-time | |
15749 | constants. The easiest way of dealing with the pathological | |
15750 | exceptions is to generate a relocation against STN_UNDEF and | |
15751 | leave everything up to the linker. */ | |
3994f87e | 15752 | if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0) |
252b5132 RH |
15753 | fixP->fx_done = 1; |
15754 | ||
15755 | switch (fixP->fx_r_type) | |
15756 | { | |
3f98094e DJ |
15757 | case BFD_RELOC_MIPS_TLS_GD: |
15758 | case BFD_RELOC_MIPS_TLS_LDM: | |
741d6ea8 JM |
15759 | case BFD_RELOC_MIPS_TLS_DTPREL32: |
15760 | case BFD_RELOC_MIPS_TLS_DTPREL64: | |
3f98094e DJ |
15761 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: |
15762 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
15763 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
d0f13682 CLT |
15764 | case BFD_RELOC_MIPS_TLS_TPREL32: |
15765 | case BFD_RELOC_MIPS_TLS_TPREL64: | |
3f98094e DJ |
15766 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: |
15767 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
df58fc94 RS |
15768 | case BFD_RELOC_MICROMIPS_TLS_GD: |
15769 | case BFD_RELOC_MICROMIPS_TLS_LDM: | |
15770 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16: | |
15771 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16: | |
15772 | case BFD_RELOC_MICROMIPS_TLS_GOTTPREL: | |
15773 | case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16: | |
15774 | case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16: | |
d0f13682 CLT |
15775 | case BFD_RELOC_MIPS16_TLS_GD: |
15776 | case BFD_RELOC_MIPS16_TLS_LDM: | |
15777 | case BFD_RELOC_MIPS16_TLS_DTPREL_HI16: | |
15778 | case BFD_RELOC_MIPS16_TLS_DTPREL_LO16: | |
15779 | case BFD_RELOC_MIPS16_TLS_GOTTPREL: | |
15780 | case BFD_RELOC_MIPS16_TLS_TPREL_HI16: | |
15781 | case BFD_RELOC_MIPS16_TLS_TPREL_LO16: | |
b886a2ab RS |
15782 | if (!fixP->fx_addsy) |
15783 | { | |
15784 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15785 | _("TLS relocation against a constant")); | |
15786 | break; | |
15787 | } | |
3f98094e DJ |
15788 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
15789 | /* fall through */ | |
15790 | ||
252b5132 | 15791 | case BFD_RELOC_MIPS_JMP: |
e369bcce TS |
15792 | case BFD_RELOC_MIPS_SHIFT5: |
15793 | case BFD_RELOC_MIPS_SHIFT6: | |
15794 | case BFD_RELOC_MIPS_GOT_DISP: | |
15795 | case BFD_RELOC_MIPS_GOT_PAGE: | |
15796 | case BFD_RELOC_MIPS_GOT_OFST: | |
15797 | case BFD_RELOC_MIPS_SUB: | |
15798 | case BFD_RELOC_MIPS_INSERT_A: | |
15799 | case BFD_RELOC_MIPS_INSERT_B: | |
15800 | case BFD_RELOC_MIPS_DELETE: | |
15801 | case BFD_RELOC_MIPS_HIGHEST: | |
15802 | case BFD_RELOC_MIPS_HIGHER: | |
15803 | case BFD_RELOC_MIPS_SCN_DISP: | |
15804 | case BFD_RELOC_MIPS_REL16: | |
15805 | case BFD_RELOC_MIPS_RELGOT: | |
15806 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
15807 | case BFD_RELOC_HI16: |
15808 | case BFD_RELOC_HI16_S: | |
b886a2ab | 15809 | case BFD_RELOC_LO16: |
cdf6fd85 | 15810 | case BFD_RELOC_GPREL16: |
252b5132 RH |
15811 | case BFD_RELOC_MIPS_LITERAL: |
15812 | case BFD_RELOC_MIPS_CALL16: | |
15813 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 15814 | case BFD_RELOC_GPREL32: |
252b5132 RH |
15815 | case BFD_RELOC_MIPS_GOT_HI16: |
15816 | case BFD_RELOC_MIPS_GOT_LO16: | |
15817 | case BFD_RELOC_MIPS_CALL_HI16: | |
15818 | case BFD_RELOC_MIPS_CALL_LO16: | |
15819 | case BFD_RELOC_MIPS16_GPREL: | |
738e5348 RS |
15820 | case BFD_RELOC_MIPS16_GOT16: |
15821 | case BFD_RELOC_MIPS16_CALL16: | |
d6f16593 MR |
15822 | case BFD_RELOC_MIPS16_HI16: |
15823 | case BFD_RELOC_MIPS16_HI16_S: | |
b886a2ab | 15824 | case BFD_RELOC_MIPS16_LO16: |
252b5132 | 15825 | case BFD_RELOC_MIPS16_JMP: |
df58fc94 RS |
15826 | case BFD_RELOC_MICROMIPS_JMP: |
15827 | case BFD_RELOC_MICROMIPS_GOT_DISP: | |
15828 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
15829 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
15830 | case BFD_RELOC_MICROMIPS_SUB: | |
15831 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
15832 | case BFD_RELOC_MICROMIPS_HIGHER: | |
15833 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
15834 | case BFD_RELOC_MICROMIPS_JALR: | |
15835 | case BFD_RELOC_MICROMIPS_HI16: | |
15836 | case BFD_RELOC_MICROMIPS_HI16_S: | |
b886a2ab | 15837 | case BFD_RELOC_MICROMIPS_LO16: |
df58fc94 RS |
15838 | case BFD_RELOC_MICROMIPS_GPREL16: |
15839 | case BFD_RELOC_MICROMIPS_LITERAL: | |
15840 | case BFD_RELOC_MICROMIPS_CALL16: | |
15841 | case BFD_RELOC_MICROMIPS_GOT16: | |
15842 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
15843 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
15844 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
15845 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
067ec077 | 15846 | case BFD_RELOC_MIPS_EH: |
b886a2ab RS |
15847 | if (fixP->fx_done) |
15848 | { | |
15849 | offsetT value; | |
15850 | ||
15851 | if (calculate_reloc (fixP->fx_r_type, *valP, &value)) | |
15852 | { | |
15853 | insn = read_reloc_insn (buf, fixP->fx_r_type); | |
15854 | if (mips16_reloc_p (fixP->fx_r_type)) | |
15855 | insn |= mips16_immed_extend (value, 16); | |
15856 | else | |
15857 | insn |= (value & 0xffff); | |
15858 | write_reloc_insn (buf, fixP->fx_r_type, insn); | |
15859 | } | |
15860 | else | |
15861 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15862 | _("Unsupported constant in relocation")); | |
15863 | } | |
252b5132 RH |
15864 | break; |
15865 | ||
252b5132 RH |
15866 | case BFD_RELOC_64: |
15867 | /* This is handled like BFD_RELOC_32, but we output a sign | |
15868 | extended value if we are only 32 bits. */ | |
3e722fb5 | 15869 | if (fixP->fx_done) |
252b5132 RH |
15870 | { |
15871 | if (8 <= sizeof (valueT)) | |
4d68580a | 15872 | md_number_to_chars (buf, *valP, 8); |
252b5132 RH |
15873 | else |
15874 | { | |
a7ebbfdf | 15875 | valueT hiv; |
252b5132 | 15876 | |
a7ebbfdf | 15877 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
15878 | hiv = 0xffffffff; |
15879 | else | |
15880 | hiv = 0; | |
4d68580a RS |
15881 | md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4); |
15882 | md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4); | |
252b5132 RH |
15883 | } |
15884 | } | |
15885 | break; | |
15886 | ||
056350c6 | 15887 | case BFD_RELOC_RVA: |
252b5132 | 15888 | case BFD_RELOC_32: |
b47468a6 | 15889 | case BFD_RELOC_32_PCREL: |
252b5132 RH |
15890 | case BFD_RELOC_16: |
15891 | /* If we are deleting this reloc entry, we must fill in the | |
54f4ddb3 TS |
15892 | value now. This can happen if we have a .word which is not |
15893 | resolved when it appears but is later defined. */ | |
252b5132 | 15894 | if (fixP->fx_done) |
4d68580a | 15895 | md_number_to_chars (buf, *valP, fixP->fx_size); |
252b5132 RH |
15896 | break; |
15897 | ||
252b5132 | 15898 | case BFD_RELOC_16_PCREL_S2: |
a7ebbfdf | 15899 | if ((*valP & 0x3) != 0) |
cb56d3d3 | 15900 | as_bad_where (fixP->fx_file, fixP->fx_line, |
bad36eac | 15901 | _("Branch to misaligned address (%lx)"), (long) *valP); |
cb56d3d3 | 15902 | |
54f4ddb3 TS |
15903 | /* We need to save the bits in the instruction since fixup_segment() |
15904 | might be deleting the relocation entry (i.e., a branch within | |
15905 | the current segment). */ | |
a7ebbfdf | 15906 | if (! fixP->fx_done) |
bb2d6cd7 | 15907 | break; |
252b5132 | 15908 | |
54f4ddb3 | 15909 | /* Update old instruction data. */ |
4d68580a | 15910 | insn = read_insn (buf); |
252b5132 | 15911 | |
a7ebbfdf TS |
15912 | if (*valP + 0x20000 <= 0x3ffff) |
15913 | { | |
15914 | insn |= (*valP >> 2) & 0xffff; | |
4d68580a | 15915 | write_insn (buf, insn); |
a7ebbfdf TS |
15916 | } |
15917 | else if (mips_pic == NO_PIC | |
15918 | && fixP->fx_done | |
15919 | && fixP->fx_frag->fr_address >= text_section->vma | |
15920 | && (fixP->fx_frag->fr_address | |
587aac4e | 15921 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
15922 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
15923 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
15924 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
15925 | { |
15926 | /* The branch offset is too large. If this is an | |
15927 | unconditional branch, and we are not generating PIC code, | |
15928 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
15929 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
15930 | insn = 0x0c000000; /* jal */ | |
252b5132 | 15931 | else |
a7ebbfdf TS |
15932 | insn = 0x08000000; /* j */ |
15933 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
15934 | fixP->fx_done = 0; | |
15935 | fixP->fx_addsy = section_symbol (text_section); | |
15936 | *valP += md_pcrel_from (fixP); | |
4d68580a | 15937 | write_insn (buf, insn); |
a7ebbfdf TS |
15938 | } |
15939 | else | |
15940 | { | |
15941 | /* If we got here, we have branch-relaxation disabled, | |
15942 | and there's nothing we can do to fix this instruction | |
15943 | without turning it into a longer sequence. */ | |
15944 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15945 | _("Branch out of range")); | |
252b5132 | 15946 | } |
252b5132 RH |
15947 | break; |
15948 | ||
df58fc94 RS |
15949 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15950 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15951 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15952 | /* We adjust the offset back to even. */ | |
15953 | if ((*valP & 0x1) != 0) | |
15954 | --(*valP); | |
15955 | ||
15956 | if (! fixP->fx_done) | |
15957 | break; | |
15958 | ||
15959 | /* Should never visit here, because we keep the relocation. */ | |
15960 | abort (); | |
15961 | break; | |
15962 | ||
252b5132 RH |
15963 | case BFD_RELOC_VTABLE_INHERIT: |
15964 | fixP->fx_done = 0; | |
15965 | if (fixP->fx_addsy | |
15966 | && !S_IS_DEFINED (fixP->fx_addsy) | |
15967 | && !S_IS_WEAK (fixP->fx_addsy)) | |
15968 | S_SET_WEAK (fixP->fx_addsy); | |
15969 | break; | |
15970 | ||
15971 | case BFD_RELOC_VTABLE_ENTRY: | |
15972 | fixP->fx_done = 0; | |
15973 | break; | |
15974 | ||
15975 | default: | |
b37df7c4 | 15976 | abort (); |
252b5132 | 15977 | } |
a7ebbfdf TS |
15978 | |
15979 | /* Remember value for tc_gen_reloc. */ | |
15980 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
15981 | } |
15982 | ||
252b5132 | 15983 | static symbolS * |
17a2f251 | 15984 | get_symbol (void) |
252b5132 RH |
15985 | { |
15986 | int c; | |
15987 | char *name; | |
15988 | symbolS *p; | |
15989 | ||
15990 | name = input_line_pointer; | |
15991 | c = get_symbol_end (); | |
15992 | p = (symbolS *) symbol_find_or_make (name); | |
15993 | *input_line_pointer = c; | |
15994 | return p; | |
15995 | } | |
15996 | ||
742a56fe RS |
15997 | /* Align the current frag to a given power of two. If a particular |
15998 | fill byte should be used, FILL points to an integer that contains | |
15999 | that byte, otherwise FILL is null. | |
16000 | ||
462427c4 RS |
16001 | This function used to have the comment: |
16002 | ||
16003 | The MIPS assembler also automatically adjusts any preceding label. | |
16004 | ||
16005 | The implementation therefore applied the adjustment to a maximum of | |
16006 | one label. However, other label adjustments are applied to batches | |
16007 | of labels, and adjusting just one caused problems when new labels | |
16008 | were added for the sake of debugging or unwind information. | |
16009 | We therefore adjust all preceding labels (given as LABELS) instead. */ | |
252b5132 RH |
16010 | |
16011 | static void | |
462427c4 | 16012 | mips_align (int to, int *fill, struct insn_label_list *labels) |
252b5132 | 16013 | { |
7d10b47d | 16014 | mips_emit_delays (); |
df58fc94 | 16015 | mips_record_compressed_mode (); |
742a56fe RS |
16016 | if (fill == NULL && subseg_text_p (now_seg)) |
16017 | frag_align_code (to, 0); | |
16018 | else | |
16019 | frag_align (to, fill ? *fill : 0, 0); | |
252b5132 | 16020 | record_alignment (now_seg, to); |
462427c4 | 16021 | mips_move_labels (labels, FALSE); |
252b5132 RH |
16022 | } |
16023 | ||
16024 | /* Align to a given power of two. .align 0 turns off the automatic | |
16025 | alignment used by the data creating pseudo-ops. */ | |
16026 | ||
16027 | static void | |
17a2f251 | 16028 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 | 16029 | { |
742a56fe | 16030 | int temp, fill_value, *fill_ptr; |
49954fb4 | 16031 | long max_alignment = 28; |
252b5132 | 16032 | |
54f4ddb3 | 16033 | /* o Note that the assembler pulls down any immediately preceding label |
252b5132 | 16034 | to the aligned address. |
54f4ddb3 | 16035 | o It's not documented but auto alignment is reinstated by |
252b5132 | 16036 | a .align pseudo instruction. |
54f4ddb3 | 16037 | o Note also that after auto alignment is turned off the mips assembler |
252b5132 | 16038 | issues an error on attempt to assemble an improperly aligned data item. |
54f4ddb3 | 16039 | We don't. */ |
252b5132 RH |
16040 | |
16041 | temp = get_absolute_expression (); | |
16042 | if (temp > max_alignment) | |
16043 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
16044 | else if (temp < 0) | |
16045 | { | |
16046 | as_warn (_("Alignment negative: 0 assumed.")); | |
16047 | temp = 0; | |
16048 | } | |
16049 | if (*input_line_pointer == ',') | |
16050 | { | |
f9419b05 | 16051 | ++input_line_pointer; |
742a56fe RS |
16052 | fill_value = get_absolute_expression (); |
16053 | fill_ptr = &fill_value; | |
252b5132 RH |
16054 | } |
16055 | else | |
742a56fe | 16056 | fill_ptr = 0; |
252b5132 RH |
16057 | if (temp) |
16058 | { | |
a8dbcb85 TS |
16059 | segment_info_type *si = seg_info (now_seg); |
16060 | struct insn_label_list *l = si->label_list; | |
54f4ddb3 | 16061 | /* Auto alignment should be switched on by next section change. */ |
252b5132 | 16062 | auto_align = 1; |
462427c4 | 16063 | mips_align (temp, fill_ptr, l); |
252b5132 RH |
16064 | } |
16065 | else | |
16066 | { | |
16067 | auto_align = 0; | |
16068 | } | |
16069 | ||
16070 | demand_empty_rest_of_line (); | |
16071 | } | |
16072 | ||
252b5132 | 16073 | static void |
17a2f251 | 16074 | s_change_sec (int sec) |
252b5132 RH |
16075 | { |
16076 | segT seg; | |
16077 | ||
252b5132 RH |
16078 | /* The ELF backend needs to know that we are changing sections, so |
16079 | that .previous works correctly. We could do something like check | |
b6ff326e | 16080 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
16081 | as it would not be appropriate to use it in the section changing |
16082 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
16083 | This should be cleaner, somehow. */ | |
f3ded42a | 16084 | obj_elf_section_change_hook (); |
252b5132 | 16085 | |
7d10b47d | 16086 | mips_emit_delays (); |
6a32d874 | 16087 | |
252b5132 RH |
16088 | switch (sec) |
16089 | { | |
16090 | case 't': | |
16091 | s_text (0); | |
16092 | break; | |
16093 | case 'd': | |
16094 | s_data (0); | |
16095 | break; | |
16096 | case 'b': | |
16097 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
16098 | demand_empty_rest_of_line (); | |
16099 | break; | |
16100 | ||
16101 | case 'r': | |
4d0d148d TS |
16102 | seg = subseg_new (RDATA_SECTION_NAME, |
16103 | (subsegT) get_absolute_expression ()); | |
f3ded42a RS |
16104 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
16105 | | SEC_READONLY | SEC_RELOC | |
16106 | | SEC_DATA)); | |
16107 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
16108 | record_alignment (seg, 4); | |
4d0d148d | 16109 | demand_empty_rest_of_line (); |
252b5132 RH |
16110 | break; |
16111 | ||
16112 | case 's': | |
4d0d148d | 16113 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
f3ded42a RS |
16114 | bfd_set_section_flags (stdoutput, seg, |
16115 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
16116 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
16117 | record_alignment (seg, 4); | |
4d0d148d TS |
16118 | demand_empty_rest_of_line (); |
16119 | break; | |
998b3c36 MR |
16120 | |
16121 | case 'B': | |
16122 | seg = subseg_new (".sbss", (subsegT) get_absolute_expression ()); | |
f3ded42a RS |
16123 | bfd_set_section_flags (stdoutput, seg, SEC_ALLOC); |
16124 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
16125 | record_alignment (seg, 4); | |
998b3c36 MR |
16126 | demand_empty_rest_of_line (); |
16127 | break; | |
252b5132 RH |
16128 | } |
16129 | ||
16130 | auto_align = 1; | |
16131 | } | |
b34976b6 | 16132 | |
cca86cc8 | 16133 | void |
17a2f251 | 16134 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 16135 | { |
cca86cc8 SC |
16136 | char *section_name; |
16137 | char c; | |
684022ea | 16138 | char next_c = 0; |
cca86cc8 SC |
16139 | int section_type; |
16140 | int section_flag; | |
16141 | int section_entry_size; | |
16142 | int section_alignment; | |
b34976b6 | 16143 | |
cca86cc8 SC |
16144 | section_name = input_line_pointer; |
16145 | c = get_symbol_end (); | |
a816d1ed AO |
16146 | if (c) |
16147 | next_c = *(input_line_pointer + 1); | |
cca86cc8 | 16148 | |
4cf0dd0d TS |
16149 | /* Do we have .section Name<,"flags">? */ |
16150 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 16151 | { |
4cf0dd0d TS |
16152 | /* just after name is now '\0'. */ |
16153 | *input_line_pointer = c; | |
cca86cc8 SC |
16154 | input_line_pointer = section_name; |
16155 | obj_elf_section (ignore); | |
16156 | return; | |
16157 | } | |
16158 | input_line_pointer++; | |
16159 | ||
16160 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
16161 | if (c == ',') | |
16162 | section_type = get_absolute_expression (); | |
16163 | else | |
16164 | section_type = 0; | |
16165 | if (*input_line_pointer++ == ',') | |
16166 | section_flag = get_absolute_expression (); | |
16167 | else | |
16168 | section_flag = 0; | |
16169 | if (*input_line_pointer++ == ',') | |
16170 | section_entry_size = get_absolute_expression (); | |
16171 | else | |
16172 | section_entry_size = 0; | |
16173 | if (*input_line_pointer++ == ',') | |
16174 | section_alignment = get_absolute_expression (); | |
16175 | else | |
16176 | section_alignment = 0; | |
87975d2a AM |
16177 | /* FIXME: really ignore? */ |
16178 | (void) section_alignment; | |
cca86cc8 | 16179 | |
a816d1ed AO |
16180 | section_name = xstrdup (section_name); |
16181 | ||
8ab8a5c8 RS |
16182 | /* When using the generic form of .section (as implemented by obj-elf.c), |
16183 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
16184 | traditionally had to fall back on the more common @progbits instead. | |
16185 | ||
16186 | There's nothing really harmful in this, since bfd will correct | |
16187 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
708587a4 | 16188 | means that, for backwards compatibility, the special_section entries |
8ab8a5c8 RS |
16189 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. |
16190 | ||
16191 | Even so, we shouldn't force users of the MIPS .section syntax to | |
16192 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
16193 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
16194 | generic type-checking code. */ | |
16195 | if (section_type == SHT_MIPS_DWARF) | |
16196 | section_type = SHT_PROGBITS; | |
16197 | ||
cca86cc8 SC |
16198 | obj_elf_change_section (section_name, section_type, section_flag, |
16199 | section_entry_size, 0, 0, 0); | |
a816d1ed AO |
16200 | |
16201 | if (now_seg->name != section_name) | |
16202 | free (section_name); | |
cca86cc8 | 16203 | } |
252b5132 RH |
16204 | |
16205 | void | |
17a2f251 | 16206 | mips_enable_auto_align (void) |
252b5132 RH |
16207 | { |
16208 | auto_align = 1; | |
16209 | } | |
16210 | ||
16211 | static void | |
17a2f251 | 16212 | s_cons (int log_size) |
252b5132 | 16213 | { |
a8dbcb85 TS |
16214 | segment_info_type *si = seg_info (now_seg); |
16215 | struct insn_label_list *l = si->label_list; | |
252b5132 | 16216 | |
7d10b47d | 16217 | mips_emit_delays (); |
252b5132 | 16218 | if (log_size > 0 && auto_align) |
462427c4 | 16219 | mips_align (log_size, 0, l); |
252b5132 | 16220 | cons (1 << log_size); |
a1facbec | 16221 | mips_clear_insn_labels (); |
252b5132 RH |
16222 | } |
16223 | ||
16224 | static void | |
17a2f251 | 16225 | s_float_cons (int type) |
252b5132 | 16226 | { |
a8dbcb85 TS |
16227 | segment_info_type *si = seg_info (now_seg); |
16228 | struct insn_label_list *l = si->label_list; | |
252b5132 | 16229 | |
7d10b47d | 16230 | mips_emit_delays (); |
252b5132 RH |
16231 | |
16232 | if (auto_align) | |
49309057 ILT |
16233 | { |
16234 | if (type == 'd') | |
462427c4 | 16235 | mips_align (3, 0, l); |
49309057 | 16236 | else |
462427c4 | 16237 | mips_align (2, 0, l); |
49309057 | 16238 | } |
252b5132 | 16239 | |
252b5132 | 16240 | float_cons (type); |
a1facbec | 16241 | mips_clear_insn_labels (); |
252b5132 RH |
16242 | } |
16243 | ||
16244 | /* Handle .globl. We need to override it because on Irix 5 you are | |
16245 | permitted to say | |
16246 | .globl foo .text | |
16247 | where foo is an undefined symbol, to mean that foo should be | |
16248 | considered to be the address of a function. */ | |
16249 | ||
16250 | static void | |
17a2f251 | 16251 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16252 | { |
16253 | char *name; | |
16254 | int c; | |
16255 | symbolS *symbolP; | |
16256 | flagword flag; | |
16257 | ||
8a06b769 | 16258 | do |
252b5132 | 16259 | { |
8a06b769 | 16260 | name = input_line_pointer; |
252b5132 | 16261 | c = get_symbol_end (); |
8a06b769 TS |
16262 | symbolP = symbol_find_or_make (name); |
16263 | S_SET_EXTERNAL (symbolP); | |
16264 | ||
252b5132 | 16265 | *input_line_pointer = c; |
8a06b769 | 16266 | SKIP_WHITESPACE (); |
252b5132 | 16267 | |
8a06b769 TS |
16268 | /* On Irix 5, every global symbol that is not explicitly labelled as |
16269 | being a function is apparently labelled as being an object. */ | |
16270 | flag = BSF_OBJECT; | |
252b5132 | 16271 | |
8a06b769 TS |
16272 | if (!is_end_of_line[(unsigned char) *input_line_pointer] |
16273 | && (*input_line_pointer != ',')) | |
16274 | { | |
16275 | char *secname; | |
16276 | asection *sec; | |
16277 | ||
16278 | secname = input_line_pointer; | |
16279 | c = get_symbol_end (); | |
16280 | sec = bfd_get_section_by_name (stdoutput, secname); | |
16281 | if (sec == NULL) | |
16282 | as_bad (_("%s: no such section"), secname); | |
16283 | *input_line_pointer = c; | |
16284 | ||
16285 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
16286 | flag = BSF_FUNCTION; | |
16287 | } | |
16288 | ||
16289 | symbol_get_bfdsym (symbolP)->flags |= flag; | |
16290 | ||
16291 | c = *input_line_pointer; | |
16292 | if (c == ',') | |
16293 | { | |
16294 | input_line_pointer++; | |
16295 | SKIP_WHITESPACE (); | |
16296 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
16297 | c = '\n'; | |
16298 | } | |
16299 | } | |
16300 | while (c == ','); | |
252b5132 | 16301 | |
252b5132 RH |
16302 | demand_empty_rest_of_line (); |
16303 | } | |
16304 | ||
16305 | static void | |
17a2f251 | 16306 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16307 | { |
16308 | char *opt; | |
16309 | char c; | |
16310 | ||
16311 | opt = input_line_pointer; | |
16312 | c = get_symbol_end (); | |
16313 | ||
16314 | if (*opt == 'O') | |
16315 | { | |
16316 | /* FIXME: What does this mean? */ | |
16317 | } | |
16318 | else if (strncmp (opt, "pic", 3) == 0) | |
16319 | { | |
16320 | int i; | |
16321 | ||
16322 | i = atoi (opt + 3); | |
16323 | if (i == 0) | |
16324 | mips_pic = NO_PIC; | |
16325 | else if (i == 2) | |
143d77c5 | 16326 | { |
8b828383 | 16327 | mips_pic = SVR4_PIC; |
143d77c5 EC |
16328 | mips_abicalls = TRUE; |
16329 | } | |
252b5132 RH |
16330 | else |
16331 | as_bad (_(".option pic%d not supported"), i); | |
16332 | ||
4d0d148d | 16333 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
16334 | { |
16335 | if (g_switch_seen && g_switch_value != 0) | |
16336 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
16337 | g_switch_value = 0; | |
16338 | bfd_set_gp_size (stdoutput, 0); | |
16339 | } | |
16340 | } | |
16341 | else | |
16342 | as_warn (_("Unrecognized option \"%s\""), opt); | |
16343 | ||
16344 | *input_line_pointer = c; | |
16345 | demand_empty_rest_of_line (); | |
16346 | } | |
16347 | ||
16348 | /* This structure is used to hold a stack of .set values. */ | |
16349 | ||
e972090a NC |
16350 | struct mips_option_stack |
16351 | { | |
252b5132 RH |
16352 | struct mips_option_stack *next; |
16353 | struct mips_set_options options; | |
16354 | }; | |
16355 | ||
16356 | static struct mips_option_stack *mips_opts_stack; | |
16357 | ||
16358 | /* Handle the .set pseudo-op. */ | |
16359 | ||
16360 | static void | |
17a2f251 | 16361 | s_mipsset (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16362 | { |
16363 | char *name = input_line_pointer, ch; | |
c6278170 | 16364 | const struct mips_ase *ase; |
252b5132 RH |
16365 | |
16366 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
f9419b05 | 16367 | ++input_line_pointer; |
252b5132 RH |
16368 | ch = *input_line_pointer; |
16369 | *input_line_pointer = '\0'; | |
16370 | ||
16371 | if (strcmp (name, "reorder") == 0) | |
16372 | { | |
7d10b47d RS |
16373 | if (mips_opts.noreorder) |
16374 | end_noreorder (); | |
252b5132 RH |
16375 | } |
16376 | else if (strcmp (name, "noreorder") == 0) | |
16377 | { | |
7d10b47d RS |
16378 | if (!mips_opts.noreorder) |
16379 | start_noreorder (); | |
252b5132 | 16380 | } |
741fe287 MR |
16381 | else if (strncmp (name, "at=", 3) == 0) |
16382 | { | |
16383 | char *s = name + 3; | |
16384 | ||
16385 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at)) | |
16386 | as_bad (_("Unrecognized register name `%s'"), s); | |
16387 | } | |
252b5132 RH |
16388 | else if (strcmp (name, "at") == 0) |
16389 | { | |
741fe287 | 16390 | mips_opts.at = ATREG; |
252b5132 RH |
16391 | } |
16392 | else if (strcmp (name, "noat") == 0) | |
16393 | { | |
741fe287 | 16394 | mips_opts.at = ZERO; |
252b5132 RH |
16395 | } |
16396 | else if (strcmp (name, "macro") == 0) | |
16397 | { | |
16398 | mips_opts.warn_about_macros = 0; | |
16399 | } | |
16400 | else if (strcmp (name, "nomacro") == 0) | |
16401 | { | |
16402 | if (mips_opts.noreorder == 0) | |
16403 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
16404 | mips_opts.warn_about_macros = 1; | |
16405 | } | |
16406 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
16407 | { | |
16408 | mips_opts.nomove = 0; | |
16409 | } | |
16410 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
16411 | { | |
16412 | mips_opts.nomove = 1; | |
16413 | } | |
16414 | else if (strcmp (name, "bopt") == 0) | |
16415 | { | |
16416 | mips_opts.nobopt = 0; | |
16417 | } | |
16418 | else if (strcmp (name, "nobopt") == 0) | |
16419 | { | |
16420 | mips_opts.nobopt = 1; | |
16421 | } | |
ad3fea08 TS |
16422 | else if (strcmp (name, "gp=default") == 0) |
16423 | mips_opts.gp32 = file_mips_gp32; | |
16424 | else if (strcmp (name, "gp=32") == 0) | |
16425 | mips_opts.gp32 = 1; | |
16426 | else if (strcmp (name, "gp=64") == 0) | |
16427 | { | |
16428 | if (!ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
20203fb9 | 16429 | as_warn (_("%s isa does not support 64-bit registers"), |
ad3fea08 TS |
16430 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16431 | mips_opts.gp32 = 0; | |
16432 | } | |
16433 | else if (strcmp (name, "fp=default") == 0) | |
16434 | mips_opts.fp32 = file_mips_fp32; | |
16435 | else if (strcmp (name, "fp=32") == 0) | |
16436 | mips_opts.fp32 = 1; | |
16437 | else if (strcmp (name, "fp=64") == 0) | |
16438 | { | |
16439 | if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) | |
20203fb9 | 16440 | as_warn (_("%s isa does not support 64-bit floating point registers"), |
ad3fea08 TS |
16441 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
16442 | mips_opts.fp32 = 0; | |
16443 | } | |
037b32b9 AN |
16444 | else if (strcmp (name, "softfloat") == 0) |
16445 | mips_opts.soft_float = 1; | |
16446 | else if (strcmp (name, "hardfloat") == 0) | |
16447 | mips_opts.soft_float = 0; | |
16448 | else if (strcmp (name, "singlefloat") == 0) | |
16449 | mips_opts.single_float = 1; | |
16450 | else if (strcmp (name, "doublefloat") == 0) | |
16451 | mips_opts.single_float = 0; | |
252b5132 RH |
16452 | else if (strcmp (name, "mips16") == 0 |
16453 | || strcmp (name, "MIPS-16") == 0) | |
df58fc94 RS |
16454 | { |
16455 | if (mips_opts.micromips == 1) | |
16456 | as_fatal (_("`mips16' cannot be used with `micromips'")); | |
16457 | mips_opts.mips16 = 1; | |
16458 | } | |
252b5132 RH |
16459 | else if (strcmp (name, "nomips16") == 0 |
16460 | || strcmp (name, "noMIPS-16") == 0) | |
16461 | mips_opts.mips16 = 0; | |
df58fc94 RS |
16462 | else if (strcmp (name, "micromips") == 0) |
16463 | { | |
16464 | if (mips_opts.mips16 == 1) | |
16465 | as_fatal (_("`micromips' cannot be used with `mips16'")); | |
16466 | mips_opts.micromips = 1; | |
16467 | } | |
16468 | else if (strcmp (name, "nomicromips") == 0) | |
16469 | mips_opts.micromips = 0; | |
c6278170 RS |
16470 | else if (name[0] == 'n' |
16471 | && name[1] == 'o' | |
16472 | && (ase = mips_lookup_ase (name + 2))) | |
16473 | mips_set_ase (ase, FALSE); | |
16474 | else if ((ase = mips_lookup_ase (name))) | |
16475 | mips_set_ase (ase, TRUE); | |
1a2c1fad | 16476 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 16477 | { |
af7ee8bf | 16478 | int reset = 0; |
252b5132 | 16479 | |
1a2c1fad CD |
16480 | /* Permit the user to change the ISA and architecture on the fly. |
16481 | Needless to say, misuse can cause serious problems. */ | |
81a21e38 | 16482 | if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) |
af7ee8bf CD |
16483 | { |
16484 | reset = 1; | |
16485 | mips_opts.isa = file_mips_isa; | |
1a2c1fad | 16486 | mips_opts.arch = file_mips_arch; |
1a2c1fad CD |
16487 | } |
16488 | else if (strncmp (name, "arch=", 5) == 0) | |
16489 | { | |
16490 | const struct mips_cpu_info *p; | |
16491 | ||
16492 | p = mips_parse_cpu("internal use", name + 5); | |
16493 | if (!p) | |
16494 | as_bad (_("unknown architecture %s"), name + 5); | |
16495 | else | |
16496 | { | |
16497 | mips_opts.arch = p->cpu; | |
16498 | mips_opts.isa = p->isa; | |
16499 | } | |
16500 | } | |
81a21e38 TS |
16501 | else if (strncmp (name, "mips", 4) == 0) |
16502 | { | |
16503 | const struct mips_cpu_info *p; | |
16504 | ||
16505 | p = mips_parse_cpu("internal use", name); | |
16506 | if (!p) | |
16507 | as_bad (_("unknown ISA level %s"), name + 4); | |
16508 | else | |
16509 | { | |
16510 | mips_opts.arch = p->cpu; | |
16511 | mips_opts.isa = p->isa; | |
16512 | } | |
16513 | } | |
af7ee8bf | 16514 | else |
81a21e38 | 16515 | as_bad (_("unknown ISA or architecture %s"), name); |
af7ee8bf CD |
16516 | |
16517 | switch (mips_opts.isa) | |
98d3f06f KH |
16518 | { |
16519 | case 0: | |
98d3f06f | 16520 | break; |
af7ee8bf CD |
16521 | case ISA_MIPS1: |
16522 | case ISA_MIPS2: | |
16523 | case ISA_MIPS32: | |
16524 | case ISA_MIPS32R2: | |
98d3f06f KH |
16525 | mips_opts.gp32 = 1; |
16526 | mips_opts.fp32 = 1; | |
16527 | break; | |
af7ee8bf CD |
16528 | case ISA_MIPS3: |
16529 | case ISA_MIPS4: | |
16530 | case ISA_MIPS5: | |
16531 | case ISA_MIPS64: | |
5f74bc13 | 16532 | case ISA_MIPS64R2: |
98d3f06f | 16533 | mips_opts.gp32 = 0; |
e407c74b NC |
16534 | if (mips_opts.arch == CPU_R5900) |
16535 | { | |
16536 | mips_opts.fp32 = 1; | |
16537 | } | |
16538 | else | |
16539 | { | |
98d3f06f | 16540 | mips_opts.fp32 = 0; |
e407c74b | 16541 | } |
98d3f06f KH |
16542 | break; |
16543 | default: | |
16544 | as_bad (_("unknown ISA level %s"), name + 4); | |
16545 | break; | |
16546 | } | |
af7ee8bf | 16547 | if (reset) |
98d3f06f | 16548 | { |
af7ee8bf CD |
16549 | mips_opts.gp32 = file_mips_gp32; |
16550 | mips_opts.fp32 = file_mips_fp32; | |
98d3f06f | 16551 | } |
252b5132 RH |
16552 | } |
16553 | else if (strcmp (name, "autoextend") == 0) | |
16554 | mips_opts.noautoextend = 0; | |
16555 | else if (strcmp (name, "noautoextend") == 0) | |
16556 | mips_opts.noautoextend = 1; | |
833794fc MR |
16557 | else if (strcmp (name, "insn32") == 0) |
16558 | mips_opts.insn32 = TRUE; | |
16559 | else if (strcmp (name, "noinsn32") == 0) | |
16560 | mips_opts.insn32 = FALSE; | |
252b5132 RH |
16561 | else if (strcmp (name, "push") == 0) |
16562 | { | |
16563 | struct mips_option_stack *s; | |
16564 | ||
16565 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
16566 | s->next = mips_opts_stack; | |
16567 | s->options = mips_opts; | |
16568 | mips_opts_stack = s; | |
16569 | } | |
16570 | else if (strcmp (name, "pop") == 0) | |
16571 | { | |
16572 | struct mips_option_stack *s; | |
16573 | ||
16574 | s = mips_opts_stack; | |
16575 | if (s == NULL) | |
16576 | as_bad (_(".set pop with no .set push")); | |
16577 | else | |
16578 | { | |
16579 | /* If we're changing the reorder mode we need to handle | |
16580 | delay slots correctly. */ | |
16581 | if (s->options.noreorder && ! mips_opts.noreorder) | |
7d10b47d | 16582 | start_noreorder (); |
252b5132 | 16583 | else if (! s->options.noreorder && mips_opts.noreorder) |
7d10b47d | 16584 | end_noreorder (); |
252b5132 RH |
16585 | |
16586 | mips_opts = s->options; | |
16587 | mips_opts_stack = s->next; | |
16588 | free (s); | |
16589 | } | |
16590 | } | |
aed1a261 RS |
16591 | else if (strcmp (name, "sym32") == 0) |
16592 | mips_opts.sym32 = TRUE; | |
16593 | else if (strcmp (name, "nosym32") == 0) | |
16594 | mips_opts.sym32 = FALSE; | |
e6559e01 JM |
16595 | else if (strchr (name, ',')) |
16596 | { | |
16597 | /* Generic ".set" directive; use the generic handler. */ | |
16598 | *input_line_pointer = ch; | |
16599 | input_line_pointer = name; | |
16600 | s_set (0); | |
16601 | return; | |
16602 | } | |
252b5132 RH |
16603 | else |
16604 | { | |
16605 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
16606 | } | |
c6278170 | 16607 | mips_check_isa_supports_ases (); |
252b5132 RH |
16608 | *input_line_pointer = ch; |
16609 | demand_empty_rest_of_line (); | |
16610 | } | |
16611 | ||
16612 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
16613 | .option pic2. It means to generate SVR4 PIC calls. */ | |
16614 | ||
16615 | static void | |
17a2f251 | 16616 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16617 | { |
16618 | mips_pic = SVR4_PIC; | |
143d77c5 | 16619 | mips_abicalls = TRUE; |
4d0d148d TS |
16620 | |
16621 | if (g_switch_seen && g_switch_value != 0) | |
16622 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
16623 | g_switch_value = 0; | |
16624 | ||
252b5132 RH |
16625 | bfd_set_gp_size (stdoutput, 0); |
16626 | demand_empty_rest_of_line (); | |
16627 | } | |
16628 | ||
16629 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
16630 | PIC code. It sets the $gp register for the function based on the | |
16631 | function address, which is in the register named in the argument. | |
16632 | This uses a relocation against _gp_disp, which is handled specially | |
16633 | by the linker. The result is: | |
16634 | lui $gp,%hi(_gp_disp) | |
16635 | addiu $gp,$gp,%lo(_gp_disp) | |
16636 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
16637 | The .cpload argument is normally $25 == $t9. |
16638 | ||
16639 | The -mno-shared option changes this to: | |
bbe506e8 TS |
16640 | lui $gp,%hi(__gnu_local_gp) |
16641 | addiu $gp,$gp,%lo(__gnu_local_gp) | |
aa6975fb ILT |
16642 | and the argument is ignored. This saves an instruction, but the |
16643 | resulting code is not position independent; it uses an absolute | |
bbe506e8 TS |
16644 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
16645 | can go into an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
16646 | |
16647 | static void | |
17a2f251 | 16648 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16649 | { |
16650 | expressionS ex; | |
aa6975fb ILT |
16651 | int reg; |
16652 | int in_shared; | |
252b5132 | 16653 | |
6478892d TS |
16654 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
16655 | .cpload is ignored. */ | |
16656 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
16657 | { |
16658 | s_ignore (0); | |
16659 | return; | |
16660 | } | |
16661 | ||
a276b80c MR |
16662 | if (mips_opts.mips16) |
16663 | { | |
16664 | as_bad (_("%s not supported in MIPS16 mode"), ".cpload"); | |
16665 | ignore_rest_of_line (); | |
16666 | return; | |
16667 | } | |
16668 | ||
d3ecfc59 | 16669 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
16670 | if (mips_opts.noreorder == 0) |
16671 | as_warn (_(".cpload not in noreorder section")); | |
16672 | ||
aa6975fb ILT |
16673 | reg = tc_get_register (0); |
16674 | ||
16675 | /* If we need to produce a 64-bit address, we are better off using | |
16676 | the default instruction sequence. */ | |
aed1a261 | 16677 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
aa6975fb | 16678 | |
252b5132 | 16679 | ex.X_op = O_symbol; |
bbe506e8 TS |
16680 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
16681 | "__gnu_local_gp"); | |
252b5132 RH |
16682 | ex.X_op_symbol = NULL; |
16683 | ex.X_add_number = 0; | |
16684 | ||
16685 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 16686 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 16687 | |
8a75745d MR |
16688 | mips_mark_labels (); |
16689 | mips_assembling_insn = TRUE; | |
16690 | ||
584892a6 | 16691 | macro_start (); |
67c0d1eb RS |
16692 | macro_build_lui (&ex, mips_gp_register); |
16693 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 16694 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
16695 | if (in_shared) |
16696 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
16697 | mips_gp_register, reg); | |
584892a6 | 16698 | macro_end (); |
252b5132 | 16699 | |
8a75745d | 16700 | mips_assembling_insn = FALSE; |
252b5132 RH |
16701 | demand_empty_rest_of_line (); |
16702 | } | |
16703 | ||
6478892d TS |
16704 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
16705 | .cpsetup $reg1, offset|$reg2, label | |
16706 | ||
16707 | If offset is given, this results in: | |
16708 | sd $gp, offset($sp) | |
956cd1d6 | 16709 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
16710 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
16711 | daddu $gp, $gp, $reg1 | |
6478892d TS |
16712 | |
16713 | If $reg2 is given, this results in: | |
16714 | daddu $reg2, $gp, $0 | |
956cd1d6 | 16715 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
16716 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
16717 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
16718 | $reg1 is normally $25 == $t9. |
16719 | ||
16720 | The -mno-shared option replaces the last three instructions with | |
16721 | lui $gp,%hi(_gp) | |
54f4ddb3 | 16722 | addiu $gp,$gp,%lo(_gp) */ |
aa6975fb | 16723 | |
6478892d | 16724 | static void |
17a2f251 | 16725 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16726 | { |
16727 | expressionS ex_off; | |
16728 | expressionS ex_sym; | |
16729 | int reg1; | |
6478892d | 16730 | |
8586fc66 | 16731 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
16732 | We also need NewABI support. */ |
16733 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16734 | { | |
16735 | s_ignore (0); | |
16736 | return; | |
16737 | } | |
16738 | ||
a276b80c MR |
16739 | if (mips_opts.mips16) |
16740 | { | |
16741 | as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup"); | |
16742 | ignore_rest_of_line (); | |
16743 | return; | |
16744 | } | |
16745 | ||
6478892d TS |
16746 | reg1 = tc_get_register (0); |
16747 | SKIP_WHITESPACE (); | |
16748 | if (*input_line_pointer != ',') | |
16749 | { | |
16750 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
16751 | return; | |
16752 | } | |
16753 | else | |
80245285 | 16754 | ++input_line_pointer; |
6478892d TS |
16755 | SKIP_WHITESPACE (); |
16756 | if (*input_line_pointer == '$') | |
80245285 TS |
16757 | { |
16758 | mips_cpreturn_register = tc_get_register (0); | |
16759 | mips_cpreturn_offset = -1; | |
16760 | } | |
6478892d | 16761 | else |
80245285 TS |
16762 | { |
16763 | mips_cpreturn_offset = get_absolute_expression (); | |
16764 | mips_cpreturn_register = -1; | |
16765 | } | |
6478892d TS |
16766 | SKIP_WHITESPACE (); |
16767 | if (*input_line_pointer != ',') | |
16768 | { | |
16769 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
16770 | return; | |
16771 | } | |
16772 | else | |
f9419b05 | 16773 | ++input_line_pointer; |
6478892d | 16774 | SKIP_WHITESPACE (); |
f21f8242 | 16775 | expression (&ex_sym); |
6478892d | 16776 | |
8a75745d MR |
16777 | mips_mark_labels (); |
16778 | mips_assembling_insn = TRUE; | |
16779 | ||
584892a6 | 16780 | macro_start (); |
6478892d TS |
16781 | if (mips_cpreturn_register == -1) |
16782 | { | |
16783 | ex_off.X_op = O_constant; | |
16784 | ex_off.X_add_symbol = NULL; | |
16785 | ex_off.X_op_symbol = NULL; | |
16786 | ex_off.X_add_number = mips_cpreturn_offset; | |
16787 | ||
67c0d1eb | 16788 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 16789 | BFD_RELOC_LO16, SP); |
6478892d TS |
16790 | } |
16791 | else | |
67c0d1eb | 16792 | macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, |
17a2f251 | 16793 | mips_gp_register, 0); |
6478892d | 16794 | |
aed1a261 | 16795 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
aa6975fb | 16796 | { |
df58fc94 | 16797 | macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register, |
aa6975fb ILT |
16798 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, |
16799 | BFD_RELOC_HI16_S); | |
16800 | ||
16801 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
16802 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
16803 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
16804 | ||
16805 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
16806 | mips_gp_register, reg1); | |
16807 | } | |
16808 | else | |
16809 | { | |
16810 | expressionS ex; | |
16811 | ||
16812 | ex.X_op = O_symbol; | |
4184909a | 16813 | ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); |
aa6975fb ILT |
16814 | ex.X_op_symbol = NULL; |
16815 | ex.X_add_number = 0; | |
6e1304d8 | 16816 | |
aa6975fb ILT |
16817 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
16818 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
16819 | ||
16820 | macro_build_lui (&ex, mips_gp_register); | |
16821 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
16822 | mips_gp_register, BFD_RELOC_LO16); | |
16823 | } | |
f21f8242 | 16824 | |
584892a6 | 16825 | macro_end (); |
6478892d | 16826 | |
8a75745d | 16827 | mips_assembling_insn = FALSE; |
6478892d TS |
16828 | demand_empty_rest_of_line (); |
16829 | } | |
16830 | ||
16831 | static void | |
17a2f251 | 16832 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16833 | { |
16834 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, | |
54f4ddb3 | 16835 | .cplocal is ignored. */ |
6478892d TS |
16836 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) |
16837 | { | |
16838 | s_ignore (0); | |
16839 | return; | |
16840 | } | |
16841 | ||
a276b80c MR |
16842 | if (mips_opts.mips16) |
16843 | { | |
16844 | as_bad (_("%s not supported in MIPS16 mode"), ".cplocal"); | |
16845 | ignore_rest_of_line (); | |
16846 | return; | |
16847 | } | |
16848 | ||
6478892d | 16849 | mips_gp_register = tc_get_register (0); |
85b51719 | 16850 | demand_empty_rest_of_line (); |
6478892d TS |
16851 | } |
16852 | ||
252b5132 RH |
16853 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
16854 | offset from $sp. The offset is remembered, and after making a PIC | |
16855 | call $gp is restored from that location. */ | |
16856 | ||
16857 | static void | |
17a2f251 | 16858 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16859 | { |
16860 | expressionS ex; | |
252b5132 | 16861 | |
6478892d | 16862 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 16863 | .cprestore is ignored. */ |
6478892d | 16864 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
16865 | { |
16866 | s_ignore (0); | |
16867 | return; | |
16868 | } | |
16869 | ||
a276b80c MR |
16870 | if (mips_opts.mips16) |
16871 | { | |
16872 | as_bad (_("%s not supported in MIPS16 mode"), ".cprestore"); | |
16873 | ignore_rest_of_line (); | |
16874 | return; | |
16875 | } | |
16876 | ||
252b5132 | 16877 | mips_cprestore_offset = get_absolute_expression (); |
7a621144 | 16878 | mips_cprestore_valid = 1; |
252b5132 RH |
16879 | |
16880 | ex.X_op = O_constant; | |
16881 | ex.X_add_symbol = NULL; | |
16882 | ex.X_op_symbol = NULL; | |
16883 | ex.X_add_number = mips_cprestore_offset; | |
16884 | ||
8a75745d MR |
16885 | mips_mark_labels (); |
16886 | mips_assembling_insn = TRUE; | |
16887 | ||
584892a6 | 16888 | macro_start (); |
67c0d1eb RS |
16889 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
16890 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 16891 | macro_end (); |
252b5132 | 16892 | |
8a75745d | 16893 | mips_assembling_insn = FALSE; |
252b5132 RH |
16894 | demand_empty_rest_of_line (); |
16895 | } | |
16896 | ||
6478892d | 16897 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 16898 | was given in the preceding .cpsetup, it results in: |
6478892d | 16899 | ld $gp, offset($sp) |
76b3015f | 16900 | |
6478892d | 16901 | If a register $reg2 was given there, it results in: |
54f4ddb3 TS |
16902 | daddu $gp, $reg2, $0 */ |
16903 | ||
6478892d | 16904 | static void |
17a2f251 | 16905 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16906 | { |
16907 | expressionS ex; | |
6478892d TS |
16908 | |
16909 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. | |
16910 | We also need NewABI support. */ | |
16911 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16912 | { | |
16913 | s_ignore (0); | |
16914 | return; | |
16915 | } | |
16916 | ||
a276b80c MR |
16917 | if (mips_opts.mips16) |
16918 | { | |
16919 | as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn"); | |
16920 | ignore_rest_of_line (); | |
16921 | return; | |
16922 | } | |
16923 | ||
8a75745d MR |
16924 | mips_mark_labels (); |
16925 | mips_assembling_insn = TRUE; | |
16926 | ||
584892a6 | 16927 | macro_start (); |
6478892d TS |
16928 | if (mips_cpreturn_register == -1) |
16929 | { | |
16930 | ex.X_op = O_constant; | |
16931 | ex.X_add_symbol = NULL; | |
16932 | ex.X_op_symbol = NULL; | |
16933 | ex.X_add_number = mips_cpreturn_offset; | |
16934 | ||
67c0d1eb | 16935 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
16936 | } |
16937 | else | |
67c0d1eb | 16938 | macro_build (NULL, "daddu", "d,v,t", mips_gp_register, |
17a2f251 | 16939 | mips_cpreturn_register, 0); |
584892a6 | 16940 | macro_end (); |
6478892d | 16941 | |
8a75745d | 16942 | mips_assembling_insn = FALSE; |
6478892d TS |
16943 | demand_empty_rest_of_line (); |
16944 | } | |
16945 | ||
d0f13682 CLT |
16946 | /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword |
16947 | pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size | |
16948 | DTP- or TP-relative relocation of type RTYPE, for use in either DWARF | |
16949 | debug information or MIPS16 TLS. */ | |
741d6ea8 JM |
16950 | |
16951 | static void | |
d0f13682 CLT |
16952 | s_tls_rel_directive (const size_t bytes, const char *dirstr, |
16953 | bfd_reloc_code_real_type rtype) | |
741d6ea8 JM |
16954 | { |
16955 | expressionS ex; | |
16956 | char *p; | |
16957 | ||
16958 | expression (&ex); | |
16959 | ||
16960 | if (ex.X_op != O_symbol) | |
16961 | { | |
d0f13682 | 16962 | as_bad (_("Unsupported use of %s"), dirstr); |
741d6ea8 JM |
16963 | ignore_rest_of_line (); |
16964 | } | |
16965 | ||
16966 | p = frag_more (bytes); | |
16967 | md_number_to_chars (p, 0, bytes); | |
d0f13682 | 16968 | fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype); |
741d6ea8 | 16969 | demand_empty_rest_of_line (); |
de64cffd | 16970 | mips_clear_insn_labels (); |
741d6ea8 JM |
16971 | } |
16972 | ||
16973 | /* Handle .dtprelword. */ | |
16974 | ||
16975 | static void | |
16976 | s_dtprelword (int ignore ATTRIBUTE_UNUSED) | |
16977 | { | |
d0f13682 | 16978 | s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32); |
741d6ea8 JM |
16979 | } |
16980 | ||
16981 | /* Handle .dtpreldword. */ | |
16982 | ||
16983 | static void | |
16984 | s_dtpreldword (int ignore ATTRIBUTE_UNUSED) | |
16985 | { | |
d0f13682 CLT |
16986 | s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64); |
16987 | } | |
16988 | ||
16989 | /* Handle .tprelword. */ | |
16990 | ||
16991 | static void | |
16992 | s_tprelword (int ignore ATTRIBUTE_UNUSED) | |
16993 | { | |
16994 | s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32); | |
16995 | } | |
16996 | ||
16997 | /* Handle .tpreldword. */ | |
16998 | ||
16999 | static void | |
17000 | s_tpreldword (int ignore ATTRIBUTE_UNUSED) | |
17001 | { | |
17002 | s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64); | |
741d6ea8 JM |
17003 | } |
17004 | ||
6478892d TS |
17005 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC |
17006 | code. It sets the offset to use in gp_rel relocations. */ | |
17007 | ||
17008 | static void | |
17a2f251 | 17009 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
17010 | { |
17011 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
17012 | We also need NewABI support. */ | |
17013 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
17014 | { | |
17015 | s_ignore (0); | |
17016 | return; | |
17017 | } | |
17018 | ||
def2e0dd | 17019 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
17020 | |
17021 | demand_empty_rest_of_line (); | |
17022 | } | |
17023 | ||
252b5132 RH |
17024 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
17025 | code. It generates a 32 bit GP relative reloc. */ | |
17026 | ||
17027 | static void | |
17a2f251 | 17028 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 17029 | { |
a8dbcb85 TS |
17030 | segment_info_type *si; |
17031 | struct insn_label_list *l; | |
252b5132 RH |
17032 | expressionS ex; |
17033 | char *p; | |
17034 | ||
17035 | /* When not generating PIC code, this is treated as .word. */ | |
17036 | if (mips_pic != SVR4_PIC) | |
17037 | { | |
17038 | s_cons (2); | |
17039 | return; | |
17040 | } | |
17041 | ||
a8dbcb85 TS |
17042 | si = seg_info (now_seg); |
17043 | l = si->label_list; | |
7d10b47d | 17044 | mips_emit_delays (); |
252b5132 | 17045 | if (auto_align) |
462427c4 | 17046 | mips_align (2, 0, l); |
252b5132 RH |
17047 | |
17048 | expression (&ex); | |
a1facbec | 17049 | mips_clear_insn_labels (); |
252b5132 RH |
17050 | |
17051 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
17052 | { | |
17053 | as_bad (_("Unsupported use of .gpword")); | |
17054 | ignore_rest_of_line (); | |
17055 | } | |
17056 | ||
17057 | p = frag_more (4); | |
17a2f251 | 17058 | md_number_to_chars (p, 0, 4); |
b34976b6 | 17059 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 17060 | BFD_RELOC_GPREL32); |
252b5132 RH |
17061 | |
17062 | demand_empty_rest_of_line (); | |
17063 | } | |
17064 | ||
10181a0d | 17065 | static void |
17a2f251 | 17066 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d | 17067 | { |
a8dbcb85 TS |
17068 | segment_info_type *si; |
17069 | struct insn_label_list *l; | |
10181a0d AO |
17070 | expressionS ex; |
17071 | char *p; | |
17072 | ||
17073 | /* When not generating PIC code, this is treated as .dword. */ | |
17074 | if (mips_pic != SVR4_PIC) | |
17075 | { | |
17076 | s_cons (3); | |
17077 | return; | |
17078 | } | |
17079 | ||
a8dbcb85 TS |
17080 | si = seg_info (now_seg); |
17081 | l = si->label_list; | |
7d10b47d | 17082 | mips_emit_delays (); |
10181a0d | 17083 | if (auto_align) |
462427c4 | 17084 | mips_align (3, 0, l); |
10181a0d AO |
17085 | |
17086 | expression (&ex); | |
a1facbec | 17087 | mips_clear_insn_labels (); |
10181a0d AO |
17088 | |
17089 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
17090 | { | |
17091 | as_bad (_("Unsupported use of .gpdword")); | |
17092 | ignore_rest_of_line (); | |
17093 | } | |
17094 | ||
17095 | p = frag_more (8); | |
17a2f251 | 17096 | md_number_to_chars (p, 0, 8); |
a105a300 | 17097 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 17098 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
17099 | |
17100 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
17101 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
17102 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
17103 | |
17104 | demand_empty_rest_of_line (); | |
17105 | } | |
17106 | ||
a3f278e2 CM |
17107 | /* Handle the .ehword pseudo-op. This is used when generating unwinding |
17108 | tables. It generates a R_MIPS_EH reloc. */ | |
17109 | ||
17110 | static void | |
17111 | s_ehword (int ignore ATTRIBUTE_UNUSED) | |
17112 | { | |
17113 | expressionS ex; | |
17114 | char *p; | |
17115 | ||
17116 | mips_emit_delays (); | |
17117 | ||
17118 | expression (&ex); | |
17119 | mips_clear_insn_labels (); | |
17120 | ||
17121 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
17122 | { | |
17123 | as_bad (_("Unsupported use of .ehword")); | |
17124 | ignore_rest_of_line (); | |
17125 | } | |
17126 | ||
17127 | p = frag_more (4); | |
17128 | md_number_to_chars (p, 0, 4); | |
17129 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, | |
17130 | BFD_RELOC_MIPS_EH); | |
17131 | ||
17132 | demand_empty_rest_of_line (); | |
17133 | } | |
17134 | ||
252b5132 RH |
17135 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
17136 | tables in SVR4 PIC code. */ | |
17137 | ||
17138 | static void | |
17a2f251 | 17139 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 17140 | { |
252b5132 RH |
17141 | int reg; |
17142 | ||
10181a0d AO |
17143 | /* This is ignored when not generating SVR4 PIC code. */ |
17144 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
17145 | { |
17146 | s_ignore (0); | |
17147 | return; | |
17148 | } | |
17149 | ||
8a75745d MR |
17150 | mips_mark_labels (); |
17151 | mips_assembling_insn = TRUE; | |
17152 | ||
252b5132 | 17153 | /* Add $gp to the register named as an argument. */ |
584892a6 | 17154 | macro_start (); |
252b5132 | 17155 | reg = tc_get_register (0); |
67c0d1eb | 17156 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 17157 | macro_end (); |
252b5132 | 17158 | |
8a75745d | 17159 | mips_assembling_insn = FALSE; |
bdaaa2e1 | 17160 | demand_empty_rest_of_line (); |
252b5132 RH |
17161 | } |
17162 | ||
17163 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
df58fc94 | 17164 | mips16/micromips mode. This permits the linker to handle them specially, |
252b5132 RH |
17165 | such as generating jalx instructions when needed. We also make |
17166 | them odd for the duration of the assembly, in order to generate the | |
17167 | right sort of code. We will make them even in the adjust_symtab | |
17168 | routine, while leaving them marked. This is convenient for the | |
17169 | debugger and the disassembler. The linker knows to make them odd | |
17170 | again. */ | |
17171 | ||
17172 | static void | |
17a2f251 | 17173 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 17174 | { |
df58fc94 | 17175 | mips_mark_labels (); |
252b5132 RH |
17176 | |
17177 | demand_empty_rest_of_line (); | |
17178 | } | |
17179 | ||
ba92f887 MR |
17180 | /* Handle the .nan pseudo-op. */ |
17181 | ||
17182 | static void | |
17183 | s_nan (int ignore ATTRIBUTE_UNUSED) | |
17184 | { | |
17185 | static const char str_legacy[] = "legacy"; | |
17186 | static const char str_2008[] = "2008"; | |
17187 | size_t i; | |
17188 | ||
17189 | for (i = 0; !is_end_of_line[(unsigned char) input_line_pointer[i]]; i++); | |
17190 | ||
17191 | if (i == sizeof (str_2008) - 1 | |
17192 | && memcmp (input_line_pointer, str_2008, i) == 0) | |
17193 | mips_flag_nan2008 = TRUE; | |
17194 | else if (i == sizeof (str_legacy) - 1 | |
17195 | && memcmp (input_line_pointer, str_legacy, i) == 0) | |
17196 | mips_flag_nan2008 = FALSE; | |
17197 | else | |
17198 | as_bad (_("Bad .nan directive")); | |
17199 | ||
17200 | input_line_pointer += i; | |
17201 | demand_empty_rest_of_line (); | |
17202 | } | |
17203 | ||
754e2bb9 RS |
17204 | /* Handle a .stab[snd] directive. Ideally these directives would be |
17205 | implemented in a transparent way, so that removing them would not | |
17206 | have any effect on the generated instructions. However, s_stab | |
17207 | internally changes the section, so in practice we need to decide | |
17208 | now whether the preceding label marks compressed code. We do not | |
17209 | support changing the compression mode of a label after a .stab* | |
17210 | directive, such as in: | |
17211 | ||
17212 | foo: | |
17213 | .stabs ... | |
17214 | .set mips16 | |
17215 | ||
17216 | so the current mode wins. */ | |
252b5132 RH |
17217 | |
17218 | static void | |
17a2f251 | 17219 | s_mips_stab (int type) |
252b5132 | 17220 | { |
754e2bb9 | 17221 | mips_mark_labels (); |
252b5132 RH |
17222 | s_stab (type); |
17223 | } | |
17224 | ||
54f4ddb3 | 17225 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */ |
252b5132 RH |
17226 | |
17227 | static void | |
17a2f251 | 17228 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
17229 | { |
17230 | char *name; | |
17231 | int c; | |
17232 | symbolS *symbolP; | |
17233 | expressionS exp; | |
17234 | ||
17235 | name = input_line_pointer; | |
17236 | c = get_symbol_end (); | |
17237 | symbolP = symbol_find_or_make (name); | |
17238 | S_SET_WEAK (symbolP); | |
17239 | *input_line_pointer = c; | |
17240 | ||
17241 | SKIP_WHITESPACE (); | |
17242 | ||
17243 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
17244 | { | |
17245 | if (S_IS_DEFINED (symbolP)) | |
17246 | { | |
20203fb9 | 17247 | as_bad (_("ignoring attempt to redefine symbol %s"), |
252b5132 RH |
17248 | S_GET_NAME (symbolP)); |
17249 | ignore_rest_of_line (); | |
17250 | return; | |
17251 | } | |
bdaaa2e1 | 17252 | |
252b5132 RH |
17253 | if (*input_line_pointer == ',') |
17254 | { | |
17255 | ++input_line_pointer; | |
17256 | SKIP_WHITESPACE (); | |
17257 | } | |
bdaaa2e1 | 17258 | |
252b5132 RH |
17259 | expression (&exp); |
17260 | if (exp.X_op != O_symbol) | |
17261 | { | |
20203fb9 | 17262 | as_bad (_("bad .weakext directive")); |
98d3f06f | 17263 | ignore_rest_of_line (); |
252b5132 RH |
17264 | return; |
17265 | } | |
49309057 | 17266 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
17267 | } |
17268 | ||
17269 | demand_empty_rest_of_line (); | |
17270 | } | |
17271 | ||
17272 | /* Parse a register string into a number. Called from the ECOFF code | |
17273 | to parse .frame. The argument is non-zero if this is the frame | |
17274 | register, so that we can record it in mips_frame_reg. */ | |
17275 | ||
17276 | int | |
17a2f251 | 17277 | tc_get_register (int frame) |
252b5132 | 17278 | { |
707bfff6 | 17279 | unsigned int reg; |
252b5132 RH |
17280 | |
17281 | SKIP_WHITESPACE (); | |
707bfff6 TS |
17282 | if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®)) |
17283 | reg = 0; | |
252b5132 | 17284 | if (frame) |
7a621144 DJ |
17285 | { |
17286 | mips_frame_reg = reg != 0 ? reg : SP; | |
17287 | mips_frame_reg_valid = 1; | |
17288 | mips_cprestore_valid = 0; | |
17289 | } | |
252b5132 RH |
17290 | return reg; |
17291 | } | |
17292 | ||
17293 | valueT | |
17a2f251 | 17294 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
17295 | { |
17296 | int align = bfd_get_section_alignment (stdoutput, seg); | |
17297 | ||
f3ded42a RS |
17298 | /* We don't need to align ELF sections to the full alignment. |
17299 | However, Irix 5 may prefer that we align them at least to a 16 | |
17300 | byte boundary. We don't bother to align the sections if we | |
17301 | are targeted for an embedded system. */ | |
17302 | if (strncmp (TARGET_OS, "elf", 3) == 0) | |
17303 | return addr; | |
17304 | if (align > 4) | |
17305 | align = 4; | |
252b5132 RH |
17306 | |
17307 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
17308 | } | |
17309 | ||
17310 | /* Utility routine, called from above as well. If called while the | |
17311 | input file is still being read, it's only an approximation. (For | |
17312 | example, a symbol may later become defined which appeared to be | |
17313 | undefined earlier.) */ | |
17314 | ||
17315 | static int | |
17a2f251 | 17316 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
17317 | { |
17318 | if (sym == 0) | |
17319 | return 0; | |
17320 | ||
4d0d148d | 17321 | if (g_switch_value > 0) |
252b5132 RH |
17322 | { |
17323 | const char *symname; | |
17324 | int change; | |
17325 | ||
c9914766 | 17326 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
17327 | register. It can be if it is smaller than the -G size or if |
17328 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 17329 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
17330 | they can. */ |
17331 | symname = S_GET_NAME (sym); | |
17332 | if (symname != (const char *) NULL | |
17333 | && (strcmp (symname, "eprol") == 0 | |
17334 | || strcmp (symname, "etext") == 0 | |
17335 | || strcmp (symname, "_gp") == 0 | |
17336 | || strcmp (symname, "edata") == 0 | |
17337 | || strcmp (symname, "_fbss") == 0 | |
17338 | || strcmp (symname, "_fdata") == 0 | |
17339 | || strcmp (symname, "_ftext") == 0 | |
17340 | || strcmp (symname, "end") == 0 | |
17341 | || strcmp (symname, "_gp_disp") == 0)) | |
17342 | change = 1; | |
17343 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
17344 | && (0 | |
17345 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
17346 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
17347 | && (symbol_get_obj (sym)->ecoff_extern_size | |
17348 | <= g_switch_value)) | |
252b5132 RH |
17349 | #endif |
17350 | /* We must defer this decision until after the whole | |
17351 | file has been read, since there might be a .extern | |
17352 | after the first use of this symbol. */ | |
17353 | || (before_relaxing | |
17354 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 17355 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
17356 | #endif |
17357 | && S_GET_VALUE (sym) == 0) | |
17358 | || (S_GET_VALUE (sym) != 0 | |
17359 | && S_GET_VALUE (sym) <= g_switch_value))) | |
17360 | change = 0; | |
17361 | else | |
17362 | { | |
17363 | const char *segname; | |
17364 | ||
17365 | segname = segment_name (S_GET_SEGMENT (sym)); | |
9c2799c2 | 17366 | gas_assert (strcmp (segname, ".lit8") != 0 |
252b5132 RH |
17367 | && strcmp (segname, ".lit4") != 0); |
17368 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
17369 | && strcmp (segname, ".sbss") != 0 |
17370 | && strncmp (segname, ".sdata.", 7) != 0 | |
d4dc2f22 TS |
17371 | && strncmp (segname, ".sbss.", 6) != 0 |
17372 | && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0 | |
fba2b7f9 | 17373 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); |
252b5132 RH |
17374 | } |
17375 | return change; | |
17376 | } | |
17377 | else | |
c9914766 | 17378 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
17379 | return 1; |
17380 | } | |
17381 | ||
5919d012 RS |
17382 | |
17383 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
17384 | ||
17385 | static bfd_boolean | |
17a2f251 | 17386 | pic_need_relax (symbolS *sym, asection *segtype) |
5919d012 RS |
17387 | { |
17388 | asection *symsec; | |
5919d012 RS |
17389 | |
17390 | /* Handle the case of a symbol equated to another symbol. */ | |
17391 | while (symbol_equated_reloc_p (sym)) | |
17392 | { | |
17393 | symbolS *n; | |
17394 | ||
5f0fe04b | 17395 | /* It's possible to get a loop here in a badly written program. */ |
5919d012 RS |
17396 | n = symbol_get_value_expression (sym)->X_add_symbol; |
17397 | if (n == sym) | |
17398 | break; | |
17399 | sym = n; | |
17400 | } | |
17401 | ||
df1f3cda DD |
17402 | if (symbol_section_p (sym)) |
17403 | return TRUE; | |
17404 | ||
5919d012 RS |
17405 | symsec = S_GET_SEGMENT (sym); |
17406 | ||
5919d012 | 17407 | /* This must duplicate the test in adjust_reloc_syms. */ |
45dfa85a AM |
17408 | return (!bfd_is_und_section (symsec) |
17409 | && !bfd_is_abs_section (symsec) | |
5f0fe04b TS |
17410 | && !bfd_is_com_section (symsec) |
17411 | && !s_is_linkonce (sym, segtype) | |
5919d012 | 17412 | /* A global or weak symbol is treated as external. */ |
f3ded42a | 17413 | && (!S_IS_WEAK (sym) && !S_IS_EXTERNAL (sym))); |
5919d012 RS |
17414 | } |
17415 | ||
17416 | ||
252b5132 RH |
17417 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
17418 | extended opcode. SEC is the section the frag is in. */ | |
17419 | ||
17420 | static int | |
17a2f251 | 17421 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 RH |
17422 | { |
17423 | int type; | |
3994f87e | 17424 | const struct mips16_immed_operand *op; |
252b5132 RH |
17425 | offsetT val; |
17426 | int mintiny, maxtiny; | |
17427 | segT symsec; | |
98aa84af | 17428 | fragS *sym_frag; |
252b5132 RH |
17429 | |
17430 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
17431 | return 0; | |
17432 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
17433 | return 1; | |
17434 | ||
17435 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
17436 | op = mips16_immed_operands; | |
17437 | while (op->type != type) | |
17438 | { | |
17439 | ++op; | |
9c2799c2 | 17440 | gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
252b5132 RH |
17441 | } |
17442 | ||
17443 | if (op->unsp) | |
17444 | { | |
17445 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
17446 | { | |
17447 | mintiny = 1; | |
17448 | maxtiny = 1 << op->nbits; | |
17449 | } | |
17450 | else | |
17451 | { | |
17452 | mintiny = 0; | |
17453 | maxtiny = (1 << op->nbits) - 1; | |
17454 | } | |
17455 | } | |
17456 | else | |
17457 | { | |
17458 | mintiny = - (1 << (op->nbits - 1)); | |
17459 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
17460 | } | |
17461 | ||
98aa84af | 17462 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
ac62c346 | 17463 | val = S_GET_VALUE (fragp->fr_symbol); |
98aa84af | 17464 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 RH |
17465 | |
17466 | if (op->pcrel) | |
17467 | { | |
17468 | addressT addr; | |
17469 | ||
17470 | /* We won't have the section when we are called from | |
17471 | mips_relax_frag. However, we will always have been called | |
17472 | from md_estimate_size_before_relax first. If this is a | |
17473 | branch to a different section, we mark it as such. If SEC is | |
17474 | NULL, and the frag is not marked, then it must be a branch to | |
17475 | the same section. */ | |
17476 | if (sec == NULL) | |
17477 | { | |
17478 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
17479 | return 1; | |
17480 | } | |
17481 | else | |
17482 | { | |
98aa84af | 17483 | /* Must have been called from md_estimate_size_before_relax. */ |
252b5132 RH |
17484 | if (symsec != sec) |
17485 | { | |
17486 | fragp->fr_subtype = | |
17487 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
17488 | ||
17489 | /* FIXME: We should support this, and let the linker | |
17490 | catch branches and loads that are out of range. */ | |
17491 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
17492 | _("unsupported PC relative reference to different section")); | |
17493 | ||
17494 | return 1; | |
17495 | } | |
98aa84af AM |
17496 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
17497 | /* Assume non-extended on the first relaxation pass. | |
17498 | The address we have calculated will be bogus if this is | |
17499 | a forward branch to another frag, as the forward frag | |
17500 | will have fr_address == 0. */ | |
17501 | return 0; | |
252b5132 RH |
17502 | } |
17503 | ||
17504 | /* In this case, we know for sure that the symbol fragment is in | |
98aa84af AM |
17505 | the same section. If the relax_marker of the symbol fragment |
17506 | differs from the relax_marker of this fragment, we have not | |
17507 | yet adjusted the symbol fragment fr_address. We want to add | |
252b5132 RH |
17508 | in STRETCH in order to get a better estimate of the address. |
17509 | This particularly matters because of the shift bits. */ | |
17510 | if (stretch != 0 | |
98aa84af | 17511 | && sym_frag->relax_marker != fragp->relax_marker) |
252b5132 RH |
17512 | { |
17513 | fragS *f; | |
17514 | ||
17515 | /* Adjust stretch for any alignment frag. Note that if have | |
17516 | been expanding the earlier code, the symbol may be | |
17517 | defined in what appears to be an earlier frag. FIXME: | |
17518 | This doesn't handle the fr_subtype field, which specifies | |
17519 | a maximum number of bytes to skip when doing an | |
17520 | alignment. */ | |
98aa84af | 17521 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
252b5132 RH |
17522 | { |
17523 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
17524 | { | |
17525 | if (stretch < 0) | |
17526 | stretch = - ((- stretch) | |
17527 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
17528 | else | |
17529 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
17530 | if (stretch == 0) | |
17531 | break; | |
17532 | } | |
17533 | } | |
17534 | if (f != NULL) | |
17535 | val += stretch; | |
17536 | } | |
17537 | ||
17538 | addr = fragp->fr_address + fragp->fr_fix; | |
17539 | ||
17540 | /* The base address rules are complicated. The base address of | |
17541 | a branch is the following instruction. The base address of a | |
17542 | PC relative load or add is the instruction itself, but if it | |
17543 | is in a delay slot (in which case it can not be extended) use | |
17544 | the address of the instruction whose delay slot it is in. */ | |
17545 | if (type == 'p' || type == 'q') | |
17546 | { | |
17547 | addr += 2; | |
17548 | ||
17549 | /* If we are currently assuming that this frag should be | |
17550 | extended, then, the current address is two bytes | |
bdaaa2e1 | 17551 | higher. */ |
252b5132 RH |
17552 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
17553 | addr += 2; | |
17554 | ||
17555 | /* Ignore the low bit in the target, since it will be set | |
17556 | for a text label. */ | |
17557 | if ((val & 1) != 0) | |
17558 | --val; | |
17559 | } | |
17560 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
17561 | addr -= 4; | |
17562 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
17563 | addr -= 2; | |
17564 | ||
17565 | val -= addr & ~ ((1 << op->shift) - 1); | |
17566 | ||
17567 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
17568 | if (type == 'p' || type == 'q') | |
17569 | val /= 2; | |
17570 | ||
17571 | /* If any of the shifted bits are set, we must use an extended | |
17572 | opcode. If the address depends on the size of this | |
17573 | instruction, this can lead to a loop, so we arrange to always | |
17574 | use an extended opcode. We only check this when we are in | |
17575 | the main relaxation loop, when SEC is NULL. */ | |
17576 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
17577 | { | |
17578 | fragp->fr_subtype = | |
17579 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
17580 | return 1; | |
17581 | } | |
17582 | ||
17583 | /* If we are about to mark a frag as extended because the value | |
17584 | is precisely maxtiny + 1, then there is a chance of an | |
17585 | infinite loop as in the following code: | |
17586 | la $4,foo | |
17587 | .skip 1020 | |
17588 | .align 2 | |
17589 | foo: | |
17590 | In this case when the la is extended, foo is 0x3fc bytes | |
17591 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
17592 | the la must be extended. To avoid this loop, we mark the | |
17593 | frag as extended if it was small, and is about to become | |
17594 | extended with a value of maxtiny + 1. */ | |
17595 | if (val == ((maxtiny + 1) << op->shift) | |
17596 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
17597 | && sec == NULL) | |
17598 | { | |
17599 | fragp->fr_subtype = | |
17600 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
17601 | return 1; | |
17602 | } | |
17603 | } | |
17604 | else if (symsec != absolute_section && sec != NULL) | |
17605 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
17606 | ||
17607 | if ((val & ((1 << op->shift) - 1)) != 0 | |
17608 | || val < (mintiny << op->shift) | |
17609 | || val > (maxtiny << op->shift)) | |
17610 | return 1; | |
17611 | else | |
17612 | return 0; | |
17613 | } | |
17614 | ||
4a6a3df4 AO |
17615 | /* Compute the length of a branch sequence, and adjust the |
17616 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
17617 | worst-case length is computed, with UPDATE being used to indicate | |
17618 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
17619 | branch is to be computed. */ | |
17620 | static int | |
17a2f251 | 17621 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 17622 | { |
b34976b6 | 17623 | bfd_boolean toofar; |
4a6a3df4 AO |
17624 | int length; |
17625 | ||
17626 | if (fragp | |
17627 | && S_IS_DEFINED (fragp->fr_symbol) | |
17628 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
17629 | { | |
17630 | addressT addr; | |
17631 | offsetT val; | |
17632 | ||
17633 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17634 | ||
17635 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
17636 | ||
17637 | val -= addr; | |
17638 | ||
17639 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
17640 | } | |
17641 | else if (fragp) | |
17642 | /* If the symbol is not defined or it's in a different segment, | |
17643 | assume the user knows what's going on and emit a short | |
17644 | branch. */ | |
b34976b6 | 17645 | toofar = FALSE; |
4a6a3df4 | 17646 | else |
b34976b6 | 17647 | toofar = TRUE; |
4a6a3df4 AO |
17648 | |
17649 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
17650 | fragp->fr_subtype | |
66b3e8da MR |
17651 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype), |
17652 | RELAX_BRANCH_UNCOND (fragp->fr_subtype), | |
4a6a3df4 AO |
17653 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
17654 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
17655 | toofar); | |
17656 | ||
17657 | length = 4; | |
17658 | if (toofar) | |
17659 | { | |
17660 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
17661 | length += 8; | |
17662 | ||
17663 | if (mips_pic != NO_PIC) | |
17664 | { | |
17665 | /* Additional space for PIC loading of target address. */ | |
17666 | length += 8; | |
17667 | if (mips_opts.isa == ISA_MIPS1) | |
17668 | /* Additional space for $at-stabilizing nop. */ | |
17669 | length += 4; | |
17670 | } | |
17671 | ||
17672 | /* If branch is conditional. */ | |
17673 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
17674 | length += 8; | |
17675 | } | |
b34976b6 | 17676 | |
4a6a3df4 AO |
17677 | return length; |
17678 | } | |
17679 | ||
df58fc94 RS |
17680 | /* Compute the length of a branch sequence, and adjust the |
17681 | RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the | |
17682 | worst-case length is computed, with UPDATE being used to indicate | |
17683 | whether an unconditional (-1), or regular (0) branch is to be | |
17684 | computed. */ | |
17685 | ||
17686 | static int | |
17687 | relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update) | |
17688 | { | |
17689 | bfd_boolean toofar; | |
17690 | int length; | |
17691 | ||
17692 | if (fragp | |
17693 | && S_IS_DEFINED (fragp->fr_symbol) | |
17694 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
17695 | { | |
17696 | addressT addr; | |
17697 | offsetT val; | |
17698 | ||
17699 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17700 | /* Ignore the low bit in the target, since it will be set | |
17701 | for a text label. */ | |
17702 | if ((val & 1) != 0) | |
17703 | --val; | |
17704 | ||
17705 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
17706 | ||
17707 | val -= addr; | |
17708 | ||
17709 | toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1); | |
17710 | } | |
17711 | else if (fragp) | |
17712 | /* If the symbol is not defined or it's in a different segment, | |
17713 | assume the user knows what's going on and emit a short | |
17714 | branch. */ | |
17715 | toofar = FALSE; | |
17716 | else | |
17717 | toofar = TRUE; | |
17718 | ||
17719 | if (fragp && update | |
17720 | && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
17721 | fragp->fr_subtype = (toofar | |
17722 | ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype) | |
17723 | : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype)); | |
17724 | ||
17725 | length = 4; | |
17726 | if (toofar) | |
17727 | { | |
17728 | bfd_boolean compact_known = fragp != NULL; | |
17729 | bfd_boolean compact = FALSE; | |
17730 | bfd_boolean uncond; | |
17731 | ||
17732 | if (compact_known) | |
17733 | compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); | |
17734 | if (fragp) | |
17735 | uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype); | |
17736 | else | |
17737 | uncond = update < 0; | |
17738 | ||
17739 | /* If label is out of range, we turn branch <br>: | |
17740 | ||
17741 | <br> label # 4 bytes | |
17742 | 0: | |
17743 | ||
17744 | into: | |
17745 | ||
17746 | j label # 4 bytes | |
17747 | nop # 2 bytes if compact && !PIC | |
17748 | 0: | |
17749 | */ | |
17750 | if (mips_pic == NO_PIC && (!compact_known || compact)) | |
17751 | length += 2; | |
17752 | ||
17753 | /* If assembling PIC code, we further turn: | |
17754 | ||
17755 | j label # 4 bytes | |
17756 | ||
17757 | into: | |
17758 | ||
17759 | lw/ld at, %got(label)(gp) # 4 bytes | |
17760 | d/addiu at, %lo(label) # 4 bytes | |
17761 | jr/c at # 2 bytes | |
17762 | */ | |
17763 | if (mips_pic != NO_PIC) | |
17764 | length += 6; | |
17765 | ||
17766 | /* If branch <br> is conditional, we prepend negated branch <brneg>: | |
17767 | ||
17768 | <brneg> 0f # 4 bytes | |
17769 | nop # 2 bytes if !compact | |
17770 | */ | |
17771 | if (!uncond) | |
17772 | length += (compact_known && compact) ? 4 : 6; | |
17773 | } | |
17774 | ||
17775 | return length; | |
17776 | } | |
17777 | ||
17778 | /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16 | |
17779 | bit accordingly. */ | |
17780 | ||
17781 | static int | |
17782 | relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update) | |
17783 | { | |
17784 | bfd_boolean toofar; | |
17785 | ||
df58fc94 RS |
17786 | if (fragp |
17787 | && S_IS_DEFINED (fragp->fr_symbol) | |
17788 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) | |
17789 | { | |
17790 | addressT addr; | |
17791 | offsetT val; | |
17792 | int type; | |
17793 | ||
17794 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17795 | /* Ignore the low bit in the target, since it will be set | |
17796 | for a text label. */ | |
17797 | if ((val & 1) != 0) | |
17798 | --val; | |
17799 | ||
17800 | /* Assume this is a 2-byte branch. */ | |
17801 | addr = fragp->fr_address + fragp->fr_fix + 2; | |
17802 | ||
17803 | /* We try to avoid the infinite loop by not adding 2 more bytes for | |
17804 | long branches. */ | |
17805 | ||
17806 | val -= addr; | |
17807 | ||
17808 | type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
17809 | if (type == 'D') | |
17810 | toofar = val < - (0x200 << 1) || val >= (0x200 << 1); | |
17811 | else if (type == 'E') | |
17812 | toofar = val < - (0x40 << 1) || val >= (0x40 << 1); | |
17813 | else | |
17814 | abort (); | |
17815 | } | |
17816 | else | |
17817 | /* If the symbol is not defined or it's in a different segment, | |
17818 | we emit a normal 32-bit branch. */ | |
17819 | toofar = TRUE; | |
17820 | ||
17821 | if (fragp && update | |
17822 | && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
17823 | fragp->fr_subtype | |
17824 | = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype) | |
17825 | : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype); | |
17826 | ||
17827 | if (toofar) | |
17828 | return 4; | |
17829 | ||
17830 | return 2; | |
17831 | } | |
17832 | ||
252b5132 RH |
17833 | /* Estimate the size of a frag before relaxing. Unless this is the |
17834 | mips16, we are not really relaxing here, and the final size is | |
17835 | encoded in the subtype information. For the mips16, we have to | |
17836 | decide whether we are using an extended opcode or not. */ | |
17837 | ||
252b5132 | 17838 | int |
17a2f251 | 17839 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 17840 | { |
5919d012 | 17841 | int change; |
252b5132 | 17842 | |
4a6a3df4 AO |
17843 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
17844 | { | |
17845 | ||
b34976b6 AM |
17846 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
17847 | ||
4a6a3df4 AO |
17848 | return fragp->fr_var; |
17849 | } | |
17850 | ||
252b5132 | 17851 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
177b4a6a AO |
17852 | /* We don't want to modify the EXTENDED bit here; it might get us |
17853 | into infinite loops. We change it only in mips_relax_frag(). */ | |
17854 | return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); | |
252b5132 | 17855 | |
df58fc94 RS |
17856 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
17857 | { | |
17858 | int length = 4; | |
17859 | ||
17860 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
17861 | length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE); | |
17862 | if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
17863 | length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE); | |
17864 | fragp->fr_var = length; | |
17865 | ||
17866 | return length; | |
17867 | } | |
17868 | ||
252b5132 | 17869 | if (mips_pic == NO_PIC) |
5919d012 | 17870 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 | 17871 | else if (mips_pic == SVR4_PIC) |
5919d012 | 17872 | change = pic_need_relax (fragp->fr_symbol, segtype); |
0a44bf69 RS |
17873 | else if (mips_pic == VXWORKS_PIC) |
17874 | /* For vxworks, GOT16 relocations never have a corresponding LO16. */ | |
17875 | change = 0; | |
252b5132 RH |
17876 | else |
17877 | abort (); | |
17878 | ||
17879 | if (change) | |
17880 | { | |
4d7206a2 | 17881 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 17882 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 17883 | } |
4d7206a2 RS |
17884 | else |
17885 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
17886 | } |
17887 | ||
17888 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 17889 | should be converted into a reloc against a section. */ |
252b5132 RH |
17890 | |
17891 | int | |
17a2f251 | 17892 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 17893 | { |
252b5132 RH |
17894 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
17895 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
17896 | return 0; | |
a161fe53 | 17897 | |
252b5132 RH |
17898 | if (fixp->fx_addsy == NULL) |
17899 | return 1; | |
a161fe53 | 17900 | |
de7e6852 RS |
17901 | /* If symbol SYM is in a mergeable section, relocations of the form |
17902 | SYM + 0 can usually be made section-relative. The mergeable data | |
17903 | is then identified by the section offset rather than by the symbol. | |
17904 | ||
17905 | However, if we're generating REL LO16 relocations, the offset is split | |
17906 | between the LO16 and parterning high part relocation. The linker will | |
17907 | need to recalculate the complete offset in order to correctly identify | |
17908 | the merge data. | |
17909 | ||
17910 | The linker has traditionally not looked for the parterning high part | |
17911 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be | |
17912 | placed anywhere. Rather than break backwards compatibility by changing | |
17913 | this, it seems better not to force the issue, and instead keep the | |
17914 | original symbol. This will work with either linker behavior. */ | |
738e5348 | 17915 | if ((lo16_reloc_p (fixp->fx_r_type) |
704803a9 | 17916 | || reloc_needs_lo_p (fixp->fx_r_type)) |
de7e6852 RS |
17917 | && HAVE_IN_PLACE_ADDENDS |
17918 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
17919 | return 0; | |
17920 | ||
ce70d90a | 17921 | /* There is no place to store an in-place offset for JALR relocations. |
2de39019 CM |
17922 | Likewise an in-range offset of limited PC-relative relocations may |
17923 | overflow the in-place relocatable field if recalculated against the | |
17924 | start address of the symbol's containing section. */ | |
ce70d90a | 17925 | if (HAVE_IN_PLACE_ADDENDS |
2de39019 CM |
17926 | && (limited_pcrel_reloc_p (fixp->fx_r_type) |
17927 | || jalr_reloc_p (fixp->fx_r_type))) | |
1180b5a4 RS |
17928 | return 0; |
17929 | ||
b314ec0e RS |
17930 | /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve |
17931 | to a floating-point stub. The same is true for non-R_MIPS16_26 | |
17932 | relocations against MIPS16 functions; in this case, the stub becomes | |
17933 | the function's canonical address. | |
17934 | ||
17935 | Floating-point stubs are stored in unique .mips16.call.* or | |
17936 | .mips16.fn.* sections. If a stub T for function F is in section S, | |
17937 | the first relocation in section S must be against F; this is how the | |
17938 | linker determines the target function. All relocations that might | |
17939 | resolve to T must also be against F. We therefore have the following | |
17940 | restrictions, which are given in an intentionally-redundant way: | |
17941 | ||
17942 | 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16 | |
17943 | symbols. | |
17944 | ||
17945 | 2. We cannot reduce a stub's relocations against non-MIPS16 symbols | |
17946 | if that stub might be used. | |
17947 | ||
17948 | 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16 | |
17949 | symbols. | |
17950 | ||
17951 | 4. We cannot reduce a stub's relocations against MIPS16 symbols if | |
17952 | that stub might be used. | |
17953 | ||
17954 | There is a further restriction: | |
17955 | ||
df58fc94 RS |
17956 | 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or |
17957 | R_MICROMIPS_26_S1) against MIPS16 or microMIPS symbols on | |
17958 | targets with in-place addends; the relocation field cannot | |
b314ec0e RS |
17959 | encode the low bit. |
17960 | ||
df58fc94 RS |
17961 | For simplicity, we deal with (3)-(4) by not reducing _any_ relocation |
17962 | against a MIPS16 symbol. We deal with (5) by by not reducing any | |
17963 | such relocations on REL targets. | |
b314ec0e RS |
17964 | |
17965 | We deal with (1)-(2) by saying that, if there's a R_MIPS16_26 | |
17966 | relocation against some symbol R, no relocation against R may be | |
17967 | reduced. (Note that this deals with (2) as well as (1) because | |
17968 | relocations against global symbols will never be reduced on ELF | |
17969 | targets.) This approach is a little simpler than trying to detect | |
17970 | stub sections, and gives the "all or nothing" per-symbol consistency | |
17971 | that we have for MIPS16 symbols. */ | |
f3ded42a | 17972 | if (fixp->fx_subsy == NULL |
30c09090 | 17973 | && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy)) |
df58fc94 RS |
17974 | || *symbol_get_tc (fixp->fx_addsy) |
17975 | || (HAVE_IN_PLACE_ADDENDS | |
17976 | && ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy)) | |
17977 | && jmp_reloc_p (fixp->fx_r_type)))) | |
252b5132 | 17978 | return 0; |
a161fe53 | 17979 | |
252b5132 RH |
17980 | return 1; |
17981 | } | |
17982 | ||
17983 | /* Translate internal representation of relocation info to BFD target | |
17984 | format. */ | |
17985 | ||
17986 | arelent ** | |
17a2f251 | 17987 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
17988 | { |
17989 | static arelent *retval[4]; | |
17990 | arelent *reloc; | |
17991 | bfd_reloc_code_real_type code; | |
17992 | ||
4b0cff4e TS |
17993 | memset (retval, 0, sizeof(retval)); |
17994 | reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); | |
49309057 ILT |
17995 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
17996 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
17997 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
17998 | ||
bad36eac DJ |
17999 | if (fixp->fx_pcrel) |
18000 | { | |
df58fc94 RS |
18001 | gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 |
18002 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
18003 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
b47468a6 CM |
18004 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1 |
18005 | || fixp->fx_r_type == BFD_RELOC_32_PCREL); | |
bad36eac DJ |
18006 | |
18007 | /* At this point, fx_addnumber is "symbol offset - pcrel address". | |
18008 | Relocations want only the symbol offset. */ | |
18009 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
bad36eac DJ |
18010 | } |
18011 | else | |
18012 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 18013 | |
438c16b8 TS |
18014 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
18015 | entry to be used in the relocation's section offset. */ | |
18016 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
18017 | { |
18018 | reloc->address = reloc->addend; | |
18019 | reloc->addend = 0; | |
18020 | } | |
18021 | ||
252b5132 | 18022 | code = fixp->fx_r_type; |
252b5132 | 18023 | |
bad36eac | 18024 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
252b5132 RH |
18025 | if (reloc->howto == NULL) |
18026 | { | |
18027 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
18028 | _("Can not represent %s relocation in this object file format"), | |
18029 | bfd_get_reloc_code_name (code)); | |
18030 | retval[0] = NULL; | |
18031 | } | |
18032 | ||
18033 | return retval; | |
18034 | } | |
18035 | ||
18036 | /* Relax a machine dependent frag. This returns the amount by which | |
18037 | the current size of the frag should change. */ | |
18038 | ||
18039 | int | |
17a2f251 | 18040 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 18041 | { |
4a6a3df4 AO |
18042 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
18043 | { | |
18044 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
18045 | |
18046 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
18047 | |
18048 | return fragp->fr_var - old_var; | |
18049 | } | |
18050 | ||
df58fc94 RS |
18051 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
18052 | { | |
18053 | offsetT old_var = fragp->fr_var; | |
18054 | offsetT new_var = 4; | |
18055 | ||
18056 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
18057 | new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE); | |
18058 | if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
18059 | new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE); | |
18060 | fragp->fr_var = new_var; | |
18061 | ||
18062 | return new_var - old_var; | |
18063 | } | |
18064 | ||
252b5132 RH |
18065 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
18066 | return 0; | |
18067 | ||
c4e7957c | 18068 | if (mips16_extended_frag (fragp, NULL, stretch)) |
252b5132 RH |
18069 | { |
18070 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
18071 | return 0; | |
18072 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
18073 | return 2; | |
18074 | } | |
18075 | else | |
18076 | { | |
18077 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
18078 | return 0; | |
18079 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
18080 | return -2; | |
18081 | } | |
18082 | ||
18083 | return 0; | |
18084 | } | |
18085 | ||
18086 | /* Convert a machine dependent frag. */ | |
18087 | ||
18088 | void | |
17a2f251 | 18089 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 18090 | { |
4a6a3df4 AO |
18091 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
18092 | { | |
4d68580a | 18093 | char *buf; |
4a6a3df4 AO |
18094 | unsigned long insn; |
18095 | expressionS exp; | |
18096 | fixS *fixp; | |
b34976b6 | 18097 | |
4d68580a RS |
18098 | buf = fragp->fr_literal + fragp->fr_fix; |
18099 | insn = read_insn (buf); | |
b34976b6 | 18100 | |
4a6a3df4 AO |
18101 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
18102 | { | |
18103 | /* We generate a fixup instead of applying it right now | |
18104 | because, if there are linker relaxations, we're going to | |
18105 | need the relocations. */ | |
18106 | exp.X_op = O_symbol; | |
18107 | exp.X_add_symbol = fragp->fr_symbol; | |
18108 | exp.X_add_number = fragp->fr_offset; | |
18109 | ||
4d68580a RS |
18110 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE, |
18111 | BFD_RELOC_16_PCREL_S2); | |
4a6a3df4 AO |
18112 | fixp->fx_file = fragp->fr_file; |
18113 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 18114 | |
4d68580a | 18115 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18116 | } |
18117 | else | |
18118 | { | |
18119 | int i; | |
18120 | ||
18121 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
5c4f07ba | 18122 | _("Relaxed out-of-range branch into a jump")); |
4a6a3df4 AO |
18123 | |
18124 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
18125 | goto uncond; | |
18126 | ||
18127 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18128 | { | |
18129 | /* Reverse the branch. */ | |
18130 | switch ((insn >> 28) & 0xf) | |
18131 | { | |
18132 | case 4: | |
3bf0dbfb MR |
18133 | /* bc[0-3][tf]l? instructions can have the condition |
18134 | reversed by tweaking a single TF bit, and their | |
18135 | opcodes all have 0x4???????. */ | |
18136 | gas_assert ((insn & 0xf3e00000) == 0x41000000); | |
4a6a3df4 AO |
18137 | insn ^= 0x00010000; |
18138 | break; | |
18139 | ||
18140 | case 0: | |
18141 | /* bltz 0x04000000 bgez 0x04010000 | |
54f4ddb3 | 18142 | bltzal 0x04100000 bgezal 0x04110000 */ |
9c2799c2 | 18143 | gas_assert ((insn & 0xfc0e0000) == 0x04000000); |
4a6a3df4 AO |
18144 | insn ^= 0x00010000; |
18145 | break; | |
b34976b6 | 18146 | |
4a6a3df4 AO |
18147 | case 1: |
18148 | /* beq 0x10000000 bne 0x14000000 | |
54f4ddb3 | 18149 | blez 0x18000000 bgtz 0x1c000000 */ |
4a6a3df4 AO |
18150 | insn ^= 0x04000000; |
18151 | break; | |
18152 | ||
18153 | default: | |
18154 | abort (); | |
18155 | } | |
18156 | } | |
18157 | ||
18158 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
18159 | { | |
18160 | /* Clear the and-link bit. */ | |
9c2799c2 | 18161 | gas_assert ((insn & 0xfc1c0000) == 0x04100000); |
4a6a3df4 | 18162 | |
54f4ddb3 TS |
18163 | /* bltzal 0x04100000 bgezal 0x04110000 |
18164 | bltzall 0x04120000 bgezall 0x04130000 */ | |
4a6a3df4 AO |
18165 | insn &= ~0x00100000; |
18166 | } | |
18167 | ||
18168 | /* Branch over the branch (if the branch was likely) or the | |
18169 | full jump (not likely case). Compute the offset from the | |
18170 | current instruction to branch to. */ | |
18171 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18172 | i = 16; | |
18173 | else | |
18174 | { | |
18175 | /* How many bytes in instructions we've already emitted? */ | |
4d68580a | 18176 | i = buf - fragp->fr_literal - fragp->fr_fix; |
4a6a3df4 AO |
18177 | /* How many bytes in instructions from here to the end? */ |
18178 | i = fragp->fr_var - i; | |
18179 | } | |
18180 | /* Convert to instruction count. */ | |
18181 | i >>= 2; | |
18182 | /* Branch counts from the next instruction. */ | |
b34976b6 | 18183 | i--; |
4a6a3df4 AO |
18184 | insn |= i; |
18185 | /* Branch over the jump. */ | |
4d68580a | 18186 | buf = write_insn (buf, insn); |
4a6a3df4 | 18187 | |
54f4ddb3 | 18188 | /* nop */ |
4d68580a | 18189 | buf = write_insn (buf, 0); |
4a6a3df4 AO |
18190 | |
18191 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18192 | { | |
18193 | /* beql $0, $0, 2f */ | |
18194 | insn = 0x50000000; | |
18195 | /* Compute the PC offset from the current instruction to | |
18196 | the end of the variable frag. */ | |
18197 | /* How many bytes in instructions we've already emitted? */ | |
4d68580a | 18198 | i = buf - fragp->fr_literal - fragp->fr_fix; |
4a6a3df4 AO |
18199 | /* How many bytes in instructions from here to the end? */ |
18200 | i = fragp->fr_var - i; | |
18201 | /* Convert to instruction count. */ | |
18202 | i >>= 2; | |
18203 | /* Don't decrement i, because we want to branch over the | |
18204 | delay slot. */ | |
4a6a3df4 | 18205 | insn |= i; |
4a6a3df4 | 18206 | |
4d68580a RS |
18207 | buf = write_insn (buf, insn); |
18208 | buf = write_insn (buf, 0); | |
4a6a3df4 AO |
18209 | } |
18210 | ||
18211 | uncond: | |
18212 | if (mips_pic == NO_PIC) | |
18213 | { | |
18214 | /* j or jal. */ | |
18215 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
18216 | ? 0x0c000000 : 0x08000000); | |
18217 | exp.X_op = O_symbol; | |
18218 | exp.X_add_symbol = fragp->fr_symbol; | |
18219 | exp.X_add_number = fragp->fr_offset; | |
18220 | ||
4d68580a RS |
18221 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
18222 | FALSE, BFD_RELOC_MIPS_JMP); | |
4a6a3df4 AO |
18223 | fixp->fx_file = fragp->fr_file; |
18224 | fixp->fx_line = fragp->fr_line; | |
18225 | ||
4d68580a | 18226 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18227 | } |
18228 | else | |
18229 | { | |
66b3e8da MR |
18230 | unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype); |
18231 | ||
4a6a3df4 | 18232 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ |
66b3e8da MR |
18233 | insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000; |
18234 | insn |= at << OP_SH_RT; | |
4a6a3df4 AO |
18235 | exp.X_op = O_symbol; |
18236 | exp.X_add_symbol = fragp->fr_symbol; | |
18237 | exp.X_add_number = fragp->fr_offset; | |
18238 | ||
18239 | if (fragp->fr_offset) | |
18240 | { | |
18241 | exp.X_add_symbol = make_expr_symbol (&exp); | |
18242 | exp.X_add_number = 0; | |
18243 | } | |
18244 | ||
4d68580a RS |
18245 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
18246 | FALSE, BFD_RELOC_MIPS_GOT16); | |
4a6a3df4 AO |
18247 | fixp->fx_file = fragp->fr_file; |
18248 | fixp->fx_line = fragp->fr_line; | |
18249 | ||
4d68580a | 18250 | buf = write_insn (buf, insn); |
b34976b6 | 18251 | |
4a6a3df4 | 18252 | if (mips_opts.isa == ISA_MIPS1) |
4d68580a RS |
18253 | /* nop */ |
18254 | buf = write_insn (buf, 0); | |
4a6a3df4 AO |
18255 | |
18256 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
66b3e8da MR |
18257 | insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000; |
18258 | insn |= at << OP_SH_RS | at << OP_SH_RT; | |
4a6a3df4 | 18259 | |
4d68580a RS |
18260 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
18261 | FALSE, BFD_RELOC_LO16); | |
4a6a3df4 AO |
18262 | fixp->fx_file = fragp->fr_file; |
18263 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 18264 | |
4d68580a | 18265 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18266 | |
18267 | /* j(al)r $at. */ | |
18268 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
66b3e8da | 18269 | insn = 0x0000f809; |
4a6a3df4 | 18270 | else |
66b3e8da MR |
18271 | insn = 0x00000008; |
18272 | insn |= at << OP_SH_RS; | |
4a6a3df4 | 18273 | |
4d68580a | 18274 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18275 | } |
18276 | } | |
18277 | ||
4a6a3df4 | 18278 | fragp->fr_fix += fragp->fr_var; |
4d68580a | 18279 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
4a6a3df4 AO |
18280 | return; |
18281 | } | |
18282 | ||
df58fc94 RS |
18283 | /* Relax microMIPS branches. */ |
18284 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) | |
18285 | { | |
4d68580a | 18286 | char *buf = fragp->fr_literal + fragp->fr_fix; |
df58fc94 RS |
18287 | bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); |
18288 | bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype); | |
18289 | int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
2309ddf2 | 18290 | bfd_boolean short_ds; |
df58fc94 RS |
18291 | unsigned long insn; |
18292 | expressionS exp; | |
18293 | fixS *fixp; | |
18294 | ||
18295 | exp.X_op = O_symbol; | |
18296 | exp.X_add_symbol = fragp->fr_symbol; | |
18297 | exp.X_add_number = fragp->fr_offset; | |
18298 | ||
18299 | fragp->fr_fix += fragp->fr_var; | |
18300 | ||
18301 | /* Handle 16-bit branches that fit or are forced to fit. */ | |
18302 | if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
18303 | { | |
18304 | /* We generate a fixup instead of applying it right now, | |
18305 | because if there is linker relaxation, we're going to | |
18306 | need the relocations. */ | |
18307 | if (type == 'D') | |
4d68580a | 18308 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE, |
df58fc94 RS |
18309 | BFD_RELOC_MICROMIPS_10_PCREL_S1); |
18310 | else if (type == 'E') | |
4d68580a | 18311 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE, |
df58fc94 RS |
18312 | BFD_RELOC_MICROMIPS_7_PCREL_S1); |
18313 | else | |
18314 | abort (); | |
18315 | ||
18316 | fixp->fx_file = fragp->fr_file; | |
18317 | fixp->fx_line = fragp->fr_line; | |
18318 | ||
18319 | /* These relocations can have an addend that won't fit in | |
18320 | 2 octets. */ | |
18321 | fixp->fx_no_overflow = 1; | |
18322 | ||
18323 | return; | |
18324 | } | |
18325 | ||
2309ddf2 | 18326 | /* Handle 32-bit branches that fit or are forced to fit. */ |
df58fc94 RS |
18327 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) |
18328 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
18329 | { | |
18330 | /* We generate a fixup instead of applying it right now, | |
18331 | because if there is linker relaxation, we're going to | |
18332 | need the relocations. */ | |
4d68580a RS |
18333 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE, |
18334 | BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
df58fc94 RS |
18335 | fixp->fx_file = fragp->fr_file; |
18336 | fixp->fx_line = fragp->fr_line; | |
18337 | ||
18338 | if (type == 0) | |
18339 | return; | |
18340 | } | |
18341 | ||
18342 | /* Relax 16-bit branches to 32-bit branches. */ | |
18343 | if (type != 0) | |
18344 | { | |
4d68580a | 18345 | insn = read_compressed_insn (buf, 2); |
df58fc94 RS |
18346 | |
18347 | if ((insn & 0xfc00) == 0xcc00) /* b16 */ | |
18348 | insn = 0x94000000; /* beq */ | |
18349 | else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */ | |
18350 | { | |
18351 | unsigned long regno; | |
18352 | ||
18353 | regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD; | |
18354 | regno = micromips_to_32_reg_d_map [regno]; | |
18355 | insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */ | |
18356 | insn |= regno << MICROMIPSOP_SH_RS; | |
18357 | } | |
18358 | else | |
18359 | abort (); | |
18360 | ||
18361 | /* Nothing else to do, just write it out. */ | |
18362 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) | |
18363 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
18364 | { | |
4d68580a RS |
18365 | buf = write_compressed_insn (buf, insn, 4); |
18366 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); | |
df58fc94 RS |
18367 | return; |
18368 | } | |
18369 | } | |
18370 | else | |
4d68580a | 18371 | insn = read_compressed_insn (buf, 4); |
df58fc94 RS |
18372 | |
18373 | /* Relax 32-bit branches to a sequence of instructions. */ | |
18374 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
18375 | _("Relaxed out-of-range branch into a jump")); | |
18376 | ||
2309ddf2 MR |
18377 | /* Set the short-delay-slot bit. */ |
18378 | short_ds = al && (insn & 0x02000000) != 0; | |
df58fc94 RS |
18379 | |
18380 | if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype)) | |
18381 | { | |
18382 | symbolS *l; | |
18383 | ||
18384 | /* Reverse the branch. */ | |
18385 | if ((insn & 0xfc000000) == 0x94000000 /* beq */ | |
18386 | || (insn & 0xfc000000) == 0xb4000000) /* bne */ | |
18387 | insn ^= 0x20000000; | |
18388 | else if ((insn & 0xffe00000) == 0x40000000 /* bltz */ | |
18389 | || (insn & 0xffe00000) == 0x40400000 /* bgez */ | |
18390 | || (insn & 0xffe00000) == 0x40800000 /* blez */ | |
18391 | || (insn & 0xffe00000) == 0x40c00000 /* bgtz */ | |
18392 | || (insn & 0xffe00000) == 0x40a00000 /* bnezc */ | |
18393 | || (insn & 0xffe00000) == 0x40e00000 /* beqzc */ | |
18394 | || (insn & 0xffe00000) == 0x40200000 /* bltzal */ | |
18395 | || (insn & 0xffe00000) == 0x40600000 /* bgezal */ | |
18396 | || (insn & 0xffe00000) == 0x42200000 /* bltzals */ | |
18397 | || (insn & 0xffe00000) == 0x42600000) /* bgezals */ | |
18398 | insn ^= 0x00400000; | |
18399 | else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */ | |
18400 | || (insn & 0xffe30000) == 0x43a00000 /* bc1t */ | |
18401 | || (insn & 0xffe30000) == 0x42800000 /* bc2f */ | |
18402 | || (insn & 0xffe30000) == 0x42a00000) /* bc2t */ | |
18403 | insn ^= 0x00200000; | |
18404 | else | |
18405 | abort (); | |
18406 | ||
18407 | if (al) | |
18408 | { | |
18409 | /* Clear the and-link and short-delay-slot bits. */ | |
18410 | gas_assert ((insn & 0xfda00000) == 0x40200000); | |
18411 | ||
18412 | /* bltzal 0x40200000 bgezal 0x40600000 */ | |
18413 | /* bltzals 0x42200000 bgezals 0x42600000 */ | |
18414 | insn &= ~0x02200000; | |
18415 | } | |
18416 | ||
18417 | /* Make a label at the end for use with the branch. */ | |
18418 | l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp); | |
18419 | micromips_label_inc (); | |
f3ded42a | 18420 | S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l))); |
df58fc94 RS |
18421 | |
18422 | /* Refer to it. */ | |
4d68580a RS |
18423 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE, |
18424 | BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
df58fc94 RS |
18425 | fixp->fx_file = fragp->fr_file; |
18426 | fixp->fx_line = fragp->fr_line; | |
18427 | ||
18428 | /* Branch over the jump. */ | |
4d68580a | 18429 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 | 18430 | if (!compact) |
4d68580a RS |
18431 | /* nop */ |
18432 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
df58fc94 RS |
18433 | } |
18434 | ||
18435 | if (mips_pic == NO_PIC) | |
18436 | { | |
2309ddf2 MR |
18437 | unsigned long jal = short_ds ? 0x74000000 : 0xf4000000; /* jal/s */ |
18438 | ||
df58fc94 RS |
18439 | /* j/jal/jals <sym> R_MICROMIPS_26_S1 */ |
18440 | insn = al ? jal : 0xd4000000; | |
18441 | ||
4d68580a RS |
18442 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
18443 | BFD_RELOC_MICROMIPS_JMP); | |
df58fc94 RS |
18444 | fixp->fx_file = fragp->fr_file; |
18445 | fixp->fx_line = fragp->fr_line; | |
18446 | ||
4d68580a | 18447 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 | 18448 | if (compact) |
4d68580a RS |
18449 | /* nop */ |
18450 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
df58fc94 RS |
18451 | } |
18452 | else | |
18453 | { | |
18454 | unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype); | |
2309ddf2 MR |
18455 | unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */ |
18456 | unsigned long jr = compact ? 0x45a0 : 0x4580; /* jr/c */ | |
df58fc94 RS |
18457 | |
18458 | /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */ | |
18459 | insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000; | |
18460 | insn |= at << MICROMIPSOP_SH_RT; | |
18461 | ||
18462 | if (exp.X_add_number) | |
18463 | { | |
18464 | exp.X_add_symbol = make_expr_symbol (&exp); | |
18465 | exp.X_add_number = 0; | |
18466 | } | |
18467 | ||
4d68580a RS |
18468 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
18469 | BFD_RELOC_MICROMIPS_GOT16); | |
df58fc94 RS |
18470 | fixp->fx_file = fragp->fr_file; |
18471 | fixp->fx_line = fragp->fr_line; | |
18472 | ||
4d68580a | 18473 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 RS |
18474 | |
18475 | /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */ | |
18476 | insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000; | |
18477 | insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS; | |
18478 | ||
4d68580a RS |
18479 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
18480 | BFD_RELOC_MICROMIPS_LO16); | |
df58fc94 RS |
18481 | fixp->fx_file = fragp->fr_file; |
18482 | fixp->fx_line = fragp->fr_line; | |
18483 | ||
4d68580a | 18484 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 RS |
18485 | |
18486 | /* jr/jrc/jalr/jalrs $at */ | |
18487 | insn = al ? jalr : jr; | |
18488 | insn |= at << MICROMIPSOP_SH_MJ; | |
18489 | ||
4d68580a | 18490 | buf = write_compressed_insn (buf, insn, 2); |
df58fc94 RS |
18491 | } |
18492 | ||
4d68580a | 18493 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
df58fc94 RS |
18494 | return; |
18495 | } | |
18496 | ||
252b5132 RH |
18497 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
18498 | { | |
18499 | int type; | |
3994f87e | 18500 | const struct mips16_immed_operand *op; |
252b5132 | 18501 | offsetT val; |
5c04167a RS |
18502 | char *buf; |
18503 | unsigned int user_length, length; | |
252b5132 | 18504 | unsigned long insn; |
5c04167a | 18505 | bfd_boolean ext; |
252b5132 RH |
18506 | |
18507 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
18508 | op = mips16_immed_operands; | |
18509 | while (op->type != type) | |
18510 | ++op; | |
18511 | ||
5c04167a | 18512 | ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype); |
5f5f22c0 | 18513 | val = resolve_symbol_value (fragp->fr_symbol); |
252b5132 RH |
18514 | if (op->pcrel) |
18515 | { | |
18516 | addressT addr; | |
18517 | ||
18518 | addr = fragp->fr_address + fragp->fr_fix; | |
18519 | ||
18520 | /* The rules for the base address of a PC relative reloc are | |
18521 | complicated; see mips16_extended_frag. */ | |
18522 | if (type == 'p' || type == 'q') | |
18523 | { | |
18524 | addr += 2; | |
18525 | if (ext) | |
18526 | addr += 2; | |
18527 | /* Ignore the low bit in the target, since it will be | |
18528 | set for a text label. */ | |
18529 | if ((val & 1) != 0) | |
18530 | --val; | |
18531 | } | |
18532 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
18533 | addr -= 4; | |
18534 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
18535 | addr -= 2; | |
18536 | ||
18537 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
18538 | val -= addr; | |
18539 | ||
18540 | /* Make sure the section winds up with the alignment we have | |
18541 | assumed. */ | |
18542 | if (op->shift > 0) | |
18543 | record_alignment (asec, op->shift); | |
18544 | } | |
18545 | ||
18546 | if (ext | |
18547 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
18548 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
18549 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
18550 | _("extended instruction in delay slot")); | |
18551 | ||
5c04167a | 18552 | buf = fragp->fr_literal + fragp->fr_fix; |
252b5132 | 18553 | |
4d68580a | 18554 | insn = read_compressed_insn (buf, 2); |
5c04167a RS |
18555 | if (ext) |
18556 | insn |= MIPS16_EXTEND; | |
252b5132 | 18557 | |
5c04167a RS |
18558 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) |
18559 | user_length = 4; | |
18560 | else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
18561 | user_length = 2; | |
18562 | else | |
18563 | user_length = 0; | |
18564 | ||
43c0598f | 18565 | mips16_immed (fragp->fr_file, fragp->fr_line, type, |
c150d1d2 | 18566 | BFD_RELOC_UNUSED, val, user_length, &insn); |
252b5132 | 18567 | |
5c04167a RS |
18568 | length = (ext ? 4 : 2); |
18569 | gas_assert (mips16_opcode_length (insn) == length); | |
18570 | write_compressed_insn (buf, insn, length); | |
18571 | fragp->fr_fix += length; | |
252b5132 RH |
18572 | } |
18573 | else | |
18574 | { | |
df58fc94 RS |
18575 | relax_substateT subtype = fragp->fr_subtype; |
18576 | bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0; | |
18577 | bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0; | |
4d7206a2 RS |
18578 | int first, second; |
18579 | fixS *fixp; | |
252b5132 | 18580 | |
df58fc94 RS |
18581 | first = RELAX_FIRST (subtype); |
18582 | second = RELAX_SECOND (subtype); | |
4d7206a2 | 18583 | fixp = (fixS *) fragp->fr_opcode; |
252b5132 | 18584 | |
df58fc94 RS |
18585 | /* If the delay slot chosen does not match the size of the instruction, |
18586 | then emit a warning. */ | |
18587 | if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0) | |
18588 | || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)) | |
18589 | { | |
18590 | relax_substateT s; | |
18591 | const char *msg; | |
18592 | ||
18593 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
18594 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
18595 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
18596 | msg = macro_warning (s); | |
18597 | if (msg != NULL) | |
db9b2be4 | 18598 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
df58fc94 RS |
18599 | subtype &= ~s; |
18600 | } | |
18601 | ||
584892a6 | 18602 | /* Possibly emit a warning if we've chosen the longer option. */ |
df58fc94 | 18603 | if (use_second == second_longer) |
584892a6 | 18604 | { |
df58fc94 RS |
18605 | relax_substateT s; |
18606 | const char *msg; | |
18607 | ||
18608 | s = (subtype | |
18609 | & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT)); | |
18610 | msg = macro_warning (s); | |
18611 | if (msg != NULL) | |
db9b2be4 | 18612 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
df58fc94 | 18613 | subtype &= ~s; |
584892a6 RS |
18614 | } |
18615 | ||
4d7206a2 RS |
18616 | /* Go through all the fixups for the first sequence. Disable them |
18617 | (by marking them as done) if we're going to use the second | |
18618 | sequence instead. */ | |
18619 | while (fixp | |
18620 | && fixp->fx_frag == fragp | |
18621 | && fixp->fx_where < fragp->fr_fix - second) | |
18622 | { | |
df58fc94 | 18623 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18624 | fixp->fx_done = 1; |
18625 | fixp = fixp->fx_next; | |
18626 | } | |
252b5132 | 18627 | |
4d7206a2 RS |
18628 | /* Go through the fixups for the second sequence. Disable them if |
18629 | we're going to use the first sequence, otherwise adjust their | |
18630 | addresses to account for the relaxation. */ | |
18631 | while (fixp && fixp->fx_frag == fragp) | |
18632 | { | |
df58fc94 | 18633 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18634 | fixp->fx_where -= first; |
18635 | else | |
18636 | fixp->fx_done = 1; | |
18637 | fixp = fixp->fx_next; | |
18638 | } | |
18639 | ||
18640 | /* Now modify the frag contents. */ | |
df58fc94 | 18641 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18642 | { |
18643 | char *start; | |
18644 | ||
18645 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
18646 | memmove (start, start + first, second); | |
18647 | fragp->fr_fix -= first; | |
18648 | } | |
18649 | else | |
18650 | fragp->fr_fix -= second; | |
252b5132 RH |
18651 | } |
18652 | } | |
18653 | ||
252b5132 RH |
18654 | /* This function is called after the relocs have been generated. |
18655 | We've been storing mips16 text labels as odd. Here we convert them | |
18656 | back to even for the convenience of the debugger. */ | |
18657 | ||
18658 | void | |
17a2f251 | 18659 | mips_frob_file_after_relocs (void) |
252b5132 RH |
18660 | { |
18661 | asymbol **syms; | |
18662 | unsigned int count, i; | |
18663 | ||
252b5132 RH |
18664 | syms = bfd_get_outsymbols (stdoutput); |
18665 | count = bfd_get_symcount (stdoutput); | |
18666 | for (i = 0; i < count; i++, syms++) | |
df58fc94 RS |
18667 | if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other) |
18668 | && ((*syms)->value & 1) != 0) | |
18669 | { | |
18670 | (*syms)->value &= ~1; | |
18671 | /* If the symbol has an odd size, it was probably computed | |
18672 | incorrectly, so adjust that as well. */ | |
18673 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
18674 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
18675 | } | |
252b5132 RH |
18676 | } |
18677 | ||
a1facbec MR |
18678 | /* This function is called whenever a label is defined, including fake |
18679 | labels instantiated off the dot special symbol. It is used when | |
18680 | handling branch delays; if a branch has a label, we assume we cannot | |
18681 | move it. This also bumps the value of the symbol by 1 in compressed | |
18682 | code. */ | |
252b5132 | 18683 | |
e1b47bd5 | 18684 | static void |
a1facbec | 18685 | mips_record_label (symbolS *sym) |
252b5132 | 18686 | { |
a8dbcb85 | 18687 | segment_info_type *si = seg_info (now_seg); |
252b5132 RH |
18688 | struct insn_label_list *l; |
18689 | ||
18690 | if (free_insn_labels == NULL) | |
18691 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
18692 | else | |
18693 | { | |
18694 | l = free_insn_labels; | |
18695 | free_insn_labels = l->next; | |
18696 | } | |
18697 | ||
18698 | l->label = sym; | |
a8dbcb85 TS |
18699 | l->next = si->label_list; |
18700 | si->label_list = l; | |
a1facbec | 18701 | } |
07a53e5c | 18702 | |
a1facbec MR |
18703 | /* This function is called as tc_frob_label() whenever a label is defined |
18704 | and adds a DWARF-2 record we only want for true labels. */ | |
18705 | ||
18706 | void | |
18707 | mips_define_label (symbolS *sym) | |
18708 | { | |
18709 | mips_record_label (sym); | |
07a53e5c | 18710 | dwarf2_emit_label (sym); |
252b5132 | 18711 | } |
e1b47bd5 RS |
18712 | |
18713 | /* This function is called by tc_new_dot_label whenever a new dot symbol | |
18714 | is defined. */ | |
18715 | ||
18716 | void | |
18717 | mips_add_dot_label (symbolS *sym) | |
18718 | { | |
18719 | mips_record_label (sym); | |
18720 | if (mips_assembling_insn && HAVE_CODE_COMPRESSION) | |
18721 | mips_compressed_mark_label (sym); | |
18722 | } | |
252b5132 | 18723 | \f |
252b5132 RH |
18724 | /* Some special processing for a MIPS ELF file. */ |
18725 | ||
18726 | void | |
17a2f251 | 18727 | mips_elf_final_processing (void) |
252b5132 RH |
18728 | { |
18729 | /* Write out the register information. */ | |
316f5878 | 18730 | if (mips_abi != N64_ABI) |
252b5132 RH |
18731 | { |
18732 | Elf32_RegInfo s; | |
18733 | ||
18734 | s.ri_gprmask = mips_gprmask; | |
18735 | s.ri_cprmask[0] = mips_cprmask[0]; | |
18736 | s.ri_cprmask[1] = mips_cprmask[1]; | |
18737 | s.ri_cprmask[2] = mips_cprmask[2]; | |
18738 | s.ri_cprmask[3] = mips_cprmask[3]; | |
18739 | /* The gp_value field is set by the MIPS ELF backend. */ | |
18740 | ||
18741 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
18742 | ((Elf32_External_RegInfo *) | |
18743 | mips_regmask_frag)); | |
18744 | } | |
18745 | else | |
18746 | { | |
18747 | Elf64_Internal_RegInfo s; | |
18748 | ||
18749 | s.ri_gprmask = mips_gprmask; | |
18750 | s.ri_pad = 0; | |
18751 | s.ri_cprmask[0] = mips_cprmask[0]; | |
18752 | s.ri_cprmask[1] = mips_cprmask[1]; | |
18753 | s.ri_cprmask[2] = mips_cprmask[2]; | |
18754 | s.ri_cprmask[3] = mips_cprmask[3]; | |
18755 | /* The gp_value field is set by the MIPS ELF backend. */ | |
18756 | ||
18757 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
18758 | ((Elf64_External_RegInfo *) | |
18759 | mips_regmask_frag)); | |
18760 | } | |
18761 | ||
18762 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
18763 | sort of BFD interface for this. */ | |
18764 | if (mips_any_noreorder) | |
18765 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
18766 | if (mips_pic != NO_PIC) | |
143d77c5 | 18767 | { |
8b828383 | 18768 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
18769 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
18770 | } | |
18771 | if (mips_abicalls) | |
18772 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 18773 | |
b015e599 AP |
18774 | /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags |
18775 | defined at present; this might need to change in future. */ | |
a4672219 TS |
18776 | if (file_ase_mips16) |
18777 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
df58fc94 RS |
18778 | if (file_ase_micromips) |
18779 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS; | |
846ef2d0 | 18780 | if (file_ase & ASE_MDMX) |
deec1734 | 18781 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; |
1f25f5d3 | 18782 | |
bdaaa2e1 | 18783 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 18784 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 18785 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 18786 | else if (mips_abi == O64_ABI) |
252b5132 | 18787 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 18788 | else if (mips_abi == EABI_ABI) |
252b5132 | 18789 | { |
316f5878 | 18790 | if (!file_mips_gp32) |
252b5132 RH |
18791 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
18792 | else | |
18793 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
18794 | } | |
316f5878 | 18795 | else if (mips_abi == N32_ABI) |
be00bddd TS |
18796 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
18797 | ||
c9914766 | 18798 | /* Nothing to do for N64_ABI. */ |
252b5132 RH |
18799 | |
18800 | if (mips_32bitmode) | |
18801 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
ad3fea08 | 18802 | |
ba92f887 MR |
18803 | if (mips_flag_nan2008) |
18804 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NAN2008; | |
18805 | ||
ad3fea08 TS |
18806 | #if 0 /* XXX FIXME */ |
18807 | /* 32 bit code with 64 bit FP registers. */ | |
18808 | if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
18809 | elf_elfheader (stdoutput)->e_flags |= ???; | |
18810 | #endif | |
252b5132 | 18811 | } |
252b5132 | 18812 | \f |
beae10d5 | 18813 | typedef struct proc { |
9b2f1d35 EC |
18814 | symbolS *func_sym; |
18815 | symbolS *func_end_sym; | |
beae10d5 KH |
18816 | unsigned long reg_mask; |
18817 | unsigned long reg_offset; | |
18818 | unsigned long fpreg_mask; | |
18819 | unsigned long fpreg_offset; | |
18820 | unsigned long frame_offset; | |
18821 | unsigned long frame_reg; | |
18822 | unsigned long pc_reg; | |
18823 | } procS; | |
252b5132 RH |
18824 | |
18825 | static procS cur_proc; | |
18826 | static procS *cur_proc_ptr; | |
18827 | static int numprocs; | |
18828 | ||
df58fc94 RS |
18829 | /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop |
18830 | as "2", and a normal nop as "0". */ | |
18831 | ||
18832 | #define NOP_OPCODE_MIPS 0 | |
18833 | #define NOP_OPCODE_MIPS16 1 | |
18834 | #define NOP_OPCODE_MICROMIPS 2 | |
742a56fe RS |
18835 | |
18836 | char | |
18837 | mips_nop_opcode (void) | |
18838 | { | |
df58fc94 RS |
18839 | if (seg_info (now_seg)->tc_segment_info_data.micromips) |
18840 | return NOP_OPCODE_MICROMIPS; | |
18841 | else if (seg_info (now_seg)->tc_segment_info_data.mips16) | |
18842 | return NOP_OPCODE_MIPS16; | |
18843 | else | |
18844 | return NOP_OPCODE_MIPS; | |
742a56fe RS |
18845 | } |
18846 | ||
df58fc94 RS |
18847 | /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use |
18848 | 32-bit microMIPS NOPs here (if applicable). */ | |
a19d8eb0 | 18849 | |
0a9ef439 | 18850 | void |
17a2f251 | 18851 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 18852 | { |
df58fc94 | 18853 | char nop_opcode; |
742a56fe | 18854 | char *p; |
c67a084a NC |
18855 | int bytes, size, excess; |
18856 | valueT opcode; | |
742a56fe | 18857 | |
0a9ef439 RH |
18858 | if (fragp->fr_type != rs_align_code) |
18859 | return; | |
18860 | ||
742a56fe | 18861 | p = fragp->fr_literal + fragp->fr_fix; |
df58fc94 RS |
18862 | nop_opcode = *p; |
18863 | switch (nop_opcode) | |
a19d8eb0 | 18864 | { |
df58fc94 RS |
18865 | case NOP_OPCODE_MICROMIPS: |
18866 | opcode = micromips_nop32_insn.insn_opcode; | |
18867 | size = 4; | |
18868 | break; | |
18869 | case NOP_OPCODE_MIPS16: | |
c67a084a NC |
18870 | opcode = mips16_nop_insn.insn_opcode; |
18871 | size = 2; | |
df58fc94 RS |
18872 | break; |
18873 | case NOP_OPCODE_MIPS: | |
18874 | default: | |
c67a084a NC |
18875 | opcode = nop_insn.insn_opcode; |
18876 | size = 4; | |
df58fc94 | 18877 | break; |
c67a084a | 18878 | } |
a19d8eb0 | 18879 | |
c67a084a NC |
18880 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
18881 | excess = bytes % size; | |
df58fc94 RS |
18882 | |
18883 | /* Handle the leading part if we're not inserting a whole number of | |
18884 | instructions, and make it the end of the fixed part of the frag. | |
18885 | Try to fit in a short microMIPS NOP if applicable and possible, | |
18886 | and use zeroes otherwise. */ | |
18887 | gas_assert (excess < 4); | |
18888 | fragp->fr_fix += excess; | |
18889 | switch (excess) | |
c67a084a | 18890 | { |
df58fc94 RS |
18891 | case 3: |
18892 | *p++ = '\0'; | |
18893 | /* Fall through. */ | |
18894 | case 2: | |
833794fc | 18895 | if (nop_opcode == NOP_OPCODE_MICROMIPS && !mips_opts.insn32) |
df58fc94 | 18896 | { |
4d68580a | 18897 | p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2); |
df58fc94 RS |
18898 | break; |
18899 | } | |
18900 | *p++ = '\0'; | |
18901 | /* Fall through. */ | |
18902 | case 1: | |
18903 | *p++ = '\0'; | |
18904 | /* Fall through. */ | |
18905 | case 0: | |
18906 | break; | |
a19d8eb0 | 18907 | } |
c67a084a NC |
18908 | |
18909 | md_number_to_chars (p, opcode, size); | |
18910 | fragp->fr_var = size; | |
a19d8eb0 CP |
18911 | } |
18912 | ||
252b5132 | 18913 | static void |
17a2f251 | 18914 | md_obj_begin (void) |
252b5132 RH |
18915 | { |
18916 | } | |
18917 | ||
18918 | static void | |
17a2f251 | 18919 | md_obj_end (void) |
252b5132 | 18920 | { |
54f4ddb3 | 18921 | /* Check for premature end, nesting errors, etc. */ |
252b5132 | 18922 | if (cur_proc_ptr) |
9a41af64 | 18923 | as_warn (_("missing .end at end of assembly")); |
252b5132 RH |
18924 | } |
18925 | ||
18926 | static long | |
17a2f251 | 18927 | get_number (void) |
252b5132 RH |
18928 | { |
18929 | int negative = 0; | |
18930 | long val = 0; | |
18931 | ||
18932 | if (*input_line_pointer == '-') | |
18933 | { | |
18934 | ++input_line_pointer; | |
18935 | negative = 1; | |
18936 | } | |
3882b010 | 18937 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 18938 | as_bad (_("expected simple number")); |
252b5132 RH |
18939 | if (input_line_pointer[0] == '0') |
18940 | { | |
18941 | if (input_line_pointer[1] == 'x') | |
18942 | { | |
18943 | input_line_pointer += 2; | |
3882b010 | 18944 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
18945 | { |
18946 | val <<= 4; | |
18947 | val |= hex_value (*input_line_pointer++); | |
18948 | } | |
18949 | return negative ? -val : val; | |
18950 | } | |
18951 | else | |
18952 | { | |
18953 | ++input_line_pointer; | |
3882b010 | 18954 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
18955 | { |
18956 | val <<= 3; | |
18957 | val |= *input_line_pointer++ - '0'; | |
18958 | } | |
18959 | return negative ? -val : val; | |
18960 | } | |
18961 | } | |
3882b010 | 18962 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
18963 | { |
18964 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
18965 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 18966 | as_warn (_("invalid number")); |
252b5132 RH |
18967 | return -1; |
18968 | } | |
3882b010 | 18969 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
18970 | { |
18971 | val *= 10; | |
18972 | val += *input_line_pointer++ - '0'; | |
18973 | } | |
18974 | return negative ? -val : val; | |
18975 | } | |
18976 | ||
18977 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
18978 | is an initial number which is the ECOFF file index. In the non-ECOFF |
18979 | case .file implies DWARF-2. */ | |
18980 | ||
18981 | static void | |
17a2f251 | 18982 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 18983 | { |
ecb4347a DJ |
18984 | static int first_file_directive = 0; |
18985 | ||
c5dd6aab DJ |
18986 | if (ECOFF_DEBUGGING) |
18987 | { | |
18988 | get_number (); | |
18989 | s_app_file (0); | |
18990 | } | |
18991 | else | |
ecb4347a DJ |
18992 | { |
18993 | char *filename; | |
18994 | ||
18995 | filename = dwarf2_directive_file (0); | |
18996 | ||
18997 | /* Versions of GCC up to 3.1 start files with a ".file" | |
18998 | directive even for stabs output. Make sure that this | |
18999 | ".file" is handled. Note that you need a version of GCC | |
19000 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
19001 | if (filename != NULL && ! first_file_directive) | |
19002 | { | |
19003 | (void) new_logical_line (filename, -1); | |
c04f5787 | 19004 | s_app_file_string (filename, 0); |
ecb4347a DJ |
19005 | } |
19006 | first_file_directive = 1; | |
19007 | } | |
c5dd6aab DJ |
19008 | } |
19009 | ||
19010 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
19011 | |
19012 | static void | |
17a2f251 | 19013 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 19014 | { |
c5dd6aab DJ |
19015 | if (!ECOFF_DEBUGGING) |
19016 | dwarf2_directive_loc (0); | |
252b5132 RH |
19017 | } |
19018 | ||
252b5132 RH |
19019 | /* The .end directive. */ |
19020 | ||
19021 | static void | |
17a2f251 | 19022 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
19023 | { |
19024 | symbolS *p; | |
252b5132 | 19025 | |
7a621144 DJ |
19026 | /* Following functions need their own .frame and .cprestore directives. */ |
19027 | mips_frame_reg_valid = 0; | |
19028 | mips_cprestore_valid = 0; | |
19029 | ||
252b5132 RH |
19030 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
19031 | { | |
19032 | p = get_symbol (); | |
19033 | demand_empty_rest_of_line (); | |
19034 | } | |
19035 | else | |
19036 | p = NULL; | |
19037 | ||
14949570 | 19038 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
19039 | as_warn (_(".end not in text section")); |
19040 | ||
19041 | if (!cur_proc_ptr) | |
19042 | { | |
19043 | as_warn (_(".end directive without a preceding .ent directive.")); | |
19044 | demand_empty_rest_of_line (); | |
19045 | return; | |
19046 | } | |
19047 | ||
19048 | if (p != NULL) | |
19049 | { | |
9c2799c2 | 19050 | gas_assert (S_GET_NAME (p)); |
9b2f1d35 | 19051 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
252b5132 | 19052 | as_warn (_(".end symbol does not match .ent symbol.")); |
ecb4347a DJ |
19053 | |
19054 | if (debug_type == DEBUG_STABS) | |
19055 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
19056 | S_GET_NAME (p)); | |
252b5132 RH |
19057 | } |
19058 | else | |
19059 | as_warn (_(".end directive missing or unknown symbol")); | |
19060 | ||
9b2f1d35 EC |
19061 | /* Create an expression to calculate the size of the function. */ |
19062 | if (p && cur_proc_ptr) | |
19063 | { | |
19064 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
19065 | expressionS *exp = xmalloc (sizeof (expressionS)); | |
19066 | ||
19067 | obj->size = exp; | |
19068 | exp->X_op = O_subtract; | |
19069 | exp->X_add_symbol = symbol_temp_new_now (); | |
19070 | exp->X_op_symbol = p; | |
19071 | exp->X_add_number = 0; | |
19072 | ||
19073 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
19074 | } | |
19075 | ||
ecb4347a | 19076 | /* Generate a .pdr section. */ |
f3ded42a | 19077 | if (!ECOFF_DEBUGGING && mips_flag_pdr) |
ecb4347a DJ |
19078 | { |
19079 | segT saved_seg = now_seg; | |
19080 | subsegT saved_subseg = now_subseg; | |
ecb4347a DJ |
19081 | expressionS exp; |
19082 | char *fragp; | |
252b5132 | 19083 | |
252b5132 | 19084 | #ifdef md_flush_pending_output |
ecb4347a | 19085 | md_flush_pending_output (); |
252b5132 RH |
19086 | #endif |
19087 | ||
9c2799c2 | 19088 | gas_assert (pdr_seg); |
ecb4347a | 19089 | subseg_set (pdr_seg, 0); |
252b5132 | 19090 | |
ecb4347a DJ |
19091 | /* Write the symbol. */ |
19092 | exp.X_op = O_symbol; | |
19093 | exp.X_add_symbol = p; | |
19094 | exp.X_add_number = 0; | |
19095 | emit_expr (&exp, 4); | |
252b5132 | 19096 | |
ecb4347a | 19097 | fragp = frag_more (7 * 4); |
252b5132 | 19098 | |
17a2f251 TS |
19099 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
19100 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
19101 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
19102 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
19103 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
19104 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
19105 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 19106 | |
ecb4347a DJ |
19107 | subseg_set (saved_seg, saved_subseg); |
19108 | } | |
252b5132 RH |
19109 | |
19110 | cur_proc_ptr = NULL; | |
19111 | } | |
19112 | ||
19113 | /* The .aent and .ent directives. */ | |
19114 | ||
19115 | static void | |
17a2f251 | 19116 | s_mips_ent (int aent) |
252b5132 | 19117 | { |
252b5132 | 19118 | symbolS *symbolP; |
252b5132 RH |
19119 | |
19120 | symbolP = get_symbol (); | |
19121 | if (*input_line_pointer == ',') | |
f9419b05 | 19122 | ++input_line_pointer; |
252b5132 | 19123 | SKIP_WHITESPACE (); |
3882b010 | 19124 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 19125 | || *input_line_pointer == '-') |
874e8986 | 19126 | get_number (); |
252b5132 | 19127 | |
14949570 | 19128 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
19129 | as_warn (_(".ent or .aent not in text section.")); |
19130 | ||
19131 | if (!aent && cur_proc_ptr) | |
9a41af64 | 19132 | as_warn (_("missing .end")); |
252b5132 RH |
19133 | |
19134 | if (!aent) | |
19135 | { | |
7a621144 DJ |
19136 | /* This function needs its own .frame and .cprestore directives. */ |
19137 | mips_frame_reg_valid = 0; | |
19138 | mips_cprestore_valid = 0; | |
19139 | ||
252b5132 RH |
19140 | cur_proc_ptr = &cur_proc; |
19141 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
19142 | ||
9b2f1d35 | 19143 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 19144 | |
f9419b05 | 19145 | ++numprocs; |
ecb4347a DJ |
19146 | |
19147 | if (debug_type == DEBUG_STABS) | |
19148 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
19149 | S_GET_NAME (symbolP)); | |
252b5132 RH |
19150 | } |
19151 | ||
7c0fc524 MR |
19152 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
19153 | ||
252b5132 RH |
19154 | demand_empty_rest_of_line (); |
19155 | } | |
19156 | ||
19157 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 19158 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 19159 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 19160 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
19161 | symbol table (in the mdebug section). */ |
19162 | ||
19163 | static void | |
17a2f251 | 19164 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 19165 | { |
f3ded42a RS |
19166 | if (ECOFF_DEBUGGING) |
19167 | s_ignore (ignore); | |
19168 | else | |
ecb4347a DJ |
19169 | { |
19170 | long val; | |
252b5132 | 19171 | |
ecb4347a DJ |
19172 | if (cur_proc_ptr == (procS *) NULL) |
19173 | { | |
19174 | as_warn (_(".frame outside of .ent")); | |
19175 | demand_empty_rest_of_line (); | |
19176 | return; | |
19177 | } | |
252b5132 | 19178 | |
ecb4347a DJ |
19179 | cur_proc_ptr->frame_reg = tc_get_register (1); |
19180 | ||
19181 | SKIP_WHITESPACE (); | |
19182 | if (*input_line_pointer++ != ',' | |
19183 | || get_absolute_expression_and_terminator (&val) != ',') | |
19184 | { | |
19185 | as_warn (_("Bad .frame directive")); | |
19186 | --input_line_pointer; | |
19187 | demand_empty_rest_of_line (); | |
19188 | return; | |
19189 | } | |
252b5132 | 19190 | |
ecb4347a DJ |
19191 | cur_proc_ptr->frame_offset = val; |
19192 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 19193 | |
252b5132 | 19194 | demand_empty_rest_of_line (); |
252b5132 | 19195 | } |
252b5132 RH |
19196 | } |
19197 | ||
bdaaa2e1 KH |
19198 | /* The .fmask and .mask directives. If the mdebug section is present |
19199 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 19200 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 19201 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
19202 | make reference to the ecoff symbol table (in the mdebug section). */ |
19203 | ||
19204 | static void | |
17a2f251 | 19205 | s_mips_mask (int reg_type) |
252b5132 | 19206 | { |
f3ded42a RS |
19207 | if (ECOFF_DEBUGGING) |
19208 | s_ignore (reg_type); | |
19209 | else | |
252b5132 | 19210 | { |
ecb4347a | 19211 | long mask, off; |
252b5132 | 19212 | |
ecb4347a DJ |
19213 | if (cur_proc_ptr == (procS *) NULL) |
19214 | { | |
19215 | as_warn (_(".mask/.fmask outside of .ent")); | |
19216 | demand_empty_rest_of_line (); | |
19217 | return; | |
19218 | } | |
252b5132 | 19219 | |
ecb4347a DJ |
19220 | if (get_absolute_expression_and_terminator (&mask) != ',') |
19221 | { | |
19222 | as_warn (_("Bad .mask/.fmask directive")); | |
19223 | --input_line_pointer; | |
19224 | demand_empty_rest_of_line (); | |
19225 | return; | |
19226 | } | |
252b5132 | 19227 | |
ecb4347a DJ |
19228 | off = get_absolute_expression (); |
19229 | ||
19230 | if (reg_type == 'F') | |
19231 | { | |
19232 | cur_proc_ptr->fpreg_mask = mask; | |
19233 | cur_proc_ptr->fpreg_offset = off; | |
19234 | } | |
19235 | else | |
19236 | { | |
19237 | cur_proc_ptr->reg_mask = mask; | |
19238 | cur_proc_ptr->reg_offset = off; | |
19239 | } | |
19240 | ||
19241 | demand_empty_rest_of_line (); | |
252b5132 | 19242 | } |
252b5132 RH |
19243 | } |
19244 | ||
316f5878 RS |
19245 | /* A table describing all the processors gas knows about. Names are |
19246 | matched in the order listed. | |
e7af610e | 19247 | |
316f5878 RS |
19248 | To ease comparison, please keep this table in the same order as |
19249 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
19250 | static const struct mips_cpu_info mips_cpu_info_table[] = |
19251 | { | |
316f5878 | 19252 | /* Entries for generic ISAs */ |
d16afab6 RS |
19253 | { "mips1", MIPS_CPU_IS_ISA, 0, ISA_MIPS1, CPU_R3000 }, |
19254 | { "mips2", MIPS_CPU_IS_ISA, 0, ISA_MIPS2, CPU_R6000 }, | |
19255 | { "mips3", MIPS_CPU_IS_ISA, 0, ISA_MIPS3, CPU_R4000 }, | |
19256 | { "mips4", MIPS_CPU_IS_ISA, 0, ISA_MIPS4, CPU_R8000 }, | |
19257 | { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 }, | |
19258 | { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 }, | |
19259 | { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19260 | { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 }, | |
19261 | { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 }, | |
316f5878 RS |
19262 | |
19263 | /* MIPS I */ | |
d16afab6 RS |
19264 | { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 }, |
19265 | { "r2000", 0, 0, ISA_MIPS1, CPU_R3000 }, | |
19266 | { "r3900", 0, 0, ISA_MIPS1, CPU_R3900 }, | |
316f5878 RS |
19267 | |
19268 | /* MIPS II */ | |
d16afab6 | 19269 | { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 }, |
316f5878 RS |
19270 | |
19271 | /* MIPS III */ | |
d16afab6 RS |
19272 | { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 }, |
19273 | { "r4010", 0, 0, ISA_MIPS2, CPU_R4010 }, | |
19274 | { "vr4100", 0, 0, ISA_MIPS3, CPU_VR4100 }, | |
19275 | { "vr4111", 0, 0, ISA_MIPS3, CPU_R4111 }, | |
19276 | { "vr4120", 0, 0, ISA_MIPS3, CPU_VR4120 }, | |
19277 | { "vr4130", 0, 0, ISA_MIPS3, CPU_VR4120 }, | |
19278 | { "vr4181", 0, 0, ISA_MIPS3, CPU_R4111 }, | |
19279 | { "vr4300", 0, 0, ISA_MIPS3, CPU_R4300 }, | |
19280 | { "r4400", 0, 0, ISA_MIPS3, CPU_R4400 }, | |
19281 | { "r4600", 0, 0, ISA_MIPS3, CPU_R4600 }, | |
19282 | { "orion", 0, 0, ISA_MIPS3, CPU_R4600 }, | |
19283 | { "r4650", 0, 0, ISA_MIPS3, CPU_R4650 }, | |
19284 | { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 }, | |
b15591bb | 19285 | /* ST Microelectronics Loongson 2E and 2F cores */ |
d16afab6 RS |
19286 | { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E }, |
19287 | { "loongson2f", 0, 0, ISA_MIPS3, CPU_LOONGSON_2F }, | |
316f5878 RS |
19288 | |
19289 | /* MIPS IV */ | |
d16afab6 RS |
19290 | { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 }, |
19291 | { "r10000", 0, 0, ISA_MIPS4, CPU_R10000 }, | |
19292 | { "r12000", 0, 0, ISA_MIPS4, CPU_R12000 }, | |
19293 | { "r14000", 0, 0, ISA_MIPS4, CPU_R14000 }, | |
19294 | { "r16000", 0, 0, ISA_MIPS4, CPU_R16000 }, | |
19295 | { "vr5000", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19296 | { "vr5400", 0, 0, ISA_MIPS4, CPU_VR5400 }, | |
19297 | { "vr5500", 0, 0, ISA_MIPS4, CPU_VR5500 }, | |
19298 | { "rm5200", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19299 | { "rm5230", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19300 | { "rm5231", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19301 | { "rm5261", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19302 | { "rm5721", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19303 | { "rm7000", 0, 0, ISA_MIPS4, CPU_RM7000 }, | |
19304 | { "rm9000", 0, 0, ISA_MIPS4, CPU_RM9000 }, | |
316f5878 RS |
19305 | |
19306 | /* MIPS 32 */ | |
d16afab6 RS |
19307 | { "4kc", 0, 0, ISA_MIPS32, CPU_MIPS32 }, |
19308 | { "4km", 0, 0, ISA_MIPS32, CPU_MIPS32 }, | |
19309 | { "4kp", 0, 0, ISA_MIPS32, CPU_MIPS32 }, | |
19310 | { "4ksc", 0, ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 }, | |
ad3fea08 TS |
19311 | |
19312 | /* MIPS 32 Release 2 */ | |
d16afab6 RS |
19313 | { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19314 | { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19315 | { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19316 | { "4ksd", 0, ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19317 | { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19318 | { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19319 | { "m14k", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19320 | { "m14kc", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19321 | { "m14ke", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU, | |
19322 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19323 | { "m14kec", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU, | |
19324 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19325 | { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19326 | { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19327 | { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19328 | { "24kf1_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 19329 | /* Deprecated forms of the above. */ |
d16afab6 RS |
19330 | { "24kfx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19331 | { "24kx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f | 19332 | /* 24KE is a 24K with DSP ASE, other ASEs are optional. */ |
d16afab6 RS |
19333 | { "24kec", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19334 | { "24kef2_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19335 | { "24kef", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19336 | { "24kef1_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 19337 | /* Deprecated forms of the above. */ |
d16afab6 RS |
19338 | { "24kefx", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19339 | { "24kex", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f | 19340 | /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */ |
d16afab6 RS |
19341 | { "34kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19342 | { "34kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19343 | { "34kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19344 | { "34kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 19345 | /* Deprecated forms of the above. */ |
d16afab6 RS |
19346 | { "34kfx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19347 | { "34kx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
711eefe4 | 19348 | /* 34Kn is a 34kc without DSP. */ |
d16afab6 | 19349 | { "34kn", 0, ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 19350 | /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */ |
d16afab6 RS |
19351 | { "74kc", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19352 | { "74kf2_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19353 | { "74kf", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19354 | { "74kf1_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19355 | { "74kf3_2", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 19356 | /* Deprecated forms of the above. */ |
d16afab6 RS |
19357 | { "74kfx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19358 | { "74kx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
30f8113a | 19359 | /* 1004K cores are multiprocessor versions of the 34K. */ |
d16afab6 RS |
19360 | { "1004kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19361 | { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19362 | { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19363 | { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
32b26a03 | 19364 | |
316f5878 | 19365 | /* MIPS 64 */ |
d16afab6 RS |
19366 | { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 }, |
19367 | { "5kf", 0, 0, ISA_MIPS64, CPU_MIPS64 }, | |
19368 | { "20kc", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
19369 | { "25kf", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
ad3fea08 | 19370 | |
c7a23324 | 19371 | /* Broadcom SB-1 CPU core */ |
d16afab6 | 19372 | { "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 }, |
1e85aad8 | 19373 | /* Broadcom SB-1A CPU core */ |
d16afab6 | 19374 | { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 }, |
d051516a | 19375 | |
d16afab6 | 19376 | { "loongson3a", 0, 0, ISA_MIPS64, CPU_LOONGSON_3A }, |
e7af610e | 19377 | |
ed163775 MR |
19378 | /* MIPS 64 Release 2 */ |
19379 | ||
967344c6 | 19380 | /* Cavium Networks Octeon CPU core */ |
d16afab6 RS |
19381 | { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON }, |
19382 | { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP }, | |
19383 | { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 }, | |
967344c6 | 19384 | |
52b6b6b9 | 19385 | /* RMI Xlr */ |
d16afab6 | 19386 | { "xlr", 0, 0, ISA_MIPS64, CPU_XLR }, |
52b6b6b9 | 19387 | |
55a36193 MK |
19388 | /* Broadcom XLP. |
19389 | XLP is mostly like XLR, with the prominent exception that it is | |
19390 | MIPS64R2 rather than MIPS64. */ | |
d16afab6 | 19391 | { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR }, |
55a36193 | 19392 | |
316f5878 | 19393 | /* End marker */ |
d16afab6 | 19394 | { NULL, 0, 0, 0, 0 } |
316f5878 | 19395 | }; |
e7af610e | 19396 | |
84ea6cf2 | 19397 | |
316f5878 RS |
19398 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
19399 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 19400 | |
316f5878 | 19401 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 19402 | |
b34976b6 | 19403 | static bfd_boolean |
17a2f251 | 19404 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
19405 | { |
19406 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
19407 | given++, canonical++; | |
19408 | ||
19409 | return ((*given == 0 && *canonical == 0) | |
19410 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
19411 | } | |
19412 | ||
19413 | ||
19414 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
19415 | CPU name. We've traditionally allowed a lot of variation here. | |
19416 | ||
19417 | Note: this function is shared between GCC and GAS. */ | |
19418 | ||
b34976b6 | 19419 | static bfd_boolean |
17a2f251 | 19420 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
19421 | { |
19422 | /* First see if the name matches exactly, or with a final "000" | |
19423 | turned into "k". */ | |
19424 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 19425 | return TRUE; |
316f5878 RS |
19426 | |
19427 | /* If not, try comparing based on numerical designation alone. | |
19428 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
19429 | if (TOLOWER (*given) == 'r') | |
19430 | given++; | |
19431 | if (!ISDIGIT (*given)) | |
b34976b6 | 19432 | return FALSE; |
316f5878 RS |
19433 | |
19434 | /* Skip over some well-known prefixes in the canonical name, | |
19435 | hoping to find a number there too. */ | |
19436 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
19437 | canonical += 2; | |
19438 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
19439 | canonical += 2; | |
19440 | else if (TOLOWER (canonical[0]) == 'r') | |
19441 | canonical += 1; | |
19442 | ||
19443 | return mips_strict_matching_cpu_name_p (canonical, given); | |
19444 | } | |
19445 | ||
19446 | ||
19447 | /* Parse an option that takes the name of a processor as its argument. | |
19448 | OPTION is the name of the option and CPU_STRING is the argument. | |
19449 | Return the corresponding processor enumeration if the CPU_STRING is | |
19450 | recognized, otherwise report an error and return null. | |
19451 | ||
19452 | A similar function exists in GCC. */ | |
e7af610e NC |
19453 | |
19454 | static const struct mips_cpu_info * | |
17a2f251 | 19455 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 19456 | { |
316f5878 | 19457 | const struct mips_cpu_info *p; |
e7af610e | 19458 | |
316f5878 RS |
19459 | /* 'from-abi' selects the most compatible architecture for the given |
19460 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
19461 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
19462 | version. Look first at the -mgp options, if given, otherwise base | |
19463 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 19464 | |
316f5878 RS |
19465 | Treat NO_ABI like the EABIs. One reason to do this is that the |
19466 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
19467 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
19468 | 'mips64', just as we did in the days before 'from-abi'. */ | |
19469 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
19470 | { | |
19471 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
19472 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
19473 | ||
19474 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
19475 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
19476 | ||
19477 | if (file_mips_gp32 >= 0) | |
19478 | return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); | |
19479 | ||
19480 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
19481 | ? ISA_MIPS3 | |
19482 | : ISA_MIPS1); | |
19483 | } | |
19484 | ||
19485 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
19486 | if (strcasecmp (cpu_string, "default") == 0) | |
19487 | return 0; | |
19488 | ||
19489 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
19490 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
19491 | return p; | |
19492 | ||
20203fb9 | 19493 | as_bad (_("Bad value (%s) for %s"), cpu_string, option); |
316f5878 | 19494 | return 0; |
e7af610e NC |
19495 | } |
19496 | ||
316f5878 RS |
19497 | /* Return the canonical processor information for ISA (a member of the |
19498 | ISA_MIPS* enumeration). */ | |
19499 | ||
e7af610e | 19500 | static const struct mips_cpu_info * |
17a2f251 | 19501 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
19502 | { |
19503 | int i; | |
19504 | ||
19505 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
ad3fea08 | 19506 | if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA) |
316f5878 | 19507 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
19508 | return (&mips_cpu_info_table[i]); |
19509 | ||
e972090a | 19510 | return NULL; |
e7af610e | 19511 | } |
fef14a42 TS |
19512 | |
19513 | static const struct mips_cpu_info * | |
17a2f251 | 19514 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
19515 | { |
19516 | int i; | |
19517 | ||
19518 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
19519 | if (arch == mips_cpu_info_table[i].cpu) | |
19520 | return (&mips_cpu_info_table[i]); | |
19521 | ||
19522 | return NULL; | |
19523 | } | |
316f5878 RS |
19524 | \f |
19525 | static void | |
17a2f251 | 19526 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
19527 | { |
19528 | if (*first_p) | |
19529 | { | |
19530 | fprintf (stream, "%24s", ""); | |
19531 | *col_p = 24; | |
19532 | } | |
19533 | else | |
19534 | { | |
19535 | fprintf (stream, ", "); | |
19536 | *col_p += 2; | |
19537 | } | |
e7af610e | 19538 | |
316f5878 RS |
19539 | if (*col_p + strlen (string) > 72) |
19540 | { | |
19541 | fprintf (stream, "\n%24s", ""); | |
19542 | *col_p = 24; | |
19543 | } | |
19544 | ||
19545 | fprintf (stream, "%s", string); | |
19546 | *col_p += strlen (string); | |
19547 | ||
19548 | *first_p = 0; | |
19549 | } | |
19550 | ||
19551 | void | |
17a2f251 | 19552 | md_show_usage (FILE *stream) |
e7af610e | 19553 | { |
316f5878 RS |
19554 | int column, first; |
19555 | size_t i; | |
19556 | ||
19557 | fprintf (stream, _("\ | |
19558 | MIPS options:\n\ | |
316f5878 RS |
19559 | -EB generate big endian output\n\ |
19560 | -EL generate little endian output\n\ | |
19561 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
19562 | -G NUM allow referencing objects up to NUM bytes\n\ | |
19563 | implicitly with the gp register [default 8]\n")); | |
19564 | fprintf (stream, _("\ | |
19565 | -mips1 generate MIPS ISA I instructions\n\ | |
19566 | -mips2 generate MIPS ISA II instructions\n\ | |
19567 | -mips3 generate MIPS ISA III instructions\n\ | |
19568 | -mips4 generate MIPS ISA IV instructions\n\ | |
19569 | -mips5 generate MIPS ISA V instructions\n\ | |
19570 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 19571 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
316f5878 | 19572 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 19573 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
316f5878 RS |
19574 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
19575 | ||
19576 | first = 1; | |
e7af610e NC |
19577 | |
19578 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
19579 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
19580 | show (stream, "from-abi", &column, &first); | |
19581 | fputc ('\n', stream); | |
e7af610e | 19582 | |
316f5878 RS |
19583 | fprintf (stream, _("\ |
19584 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
19585 | -no-mCPU don't generate code specific to CPU.\n\ | |
19586 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
19587 | ||
19588 | first = 1; | |
19589 | ||
19590 | show (stream, "3900", &column, &first); | |
19591 | show (stream, "4010", &column, &first); | |
19592 | show (stream, "4100", &column, &first); | |
19593 | show (stream, "4650", &column, &first); | |
19594 | fputc ('\n', stream); | |
19595 | ||
19596 | fprintf (stream, _("\ | |
19597 | -mips16 generate mips16 instructions\n\ | |
19598 | -no-mips16 do not generate mips16 instructions\n")); | |
19599 | fprintf (stream, _("\ | |
df58fc94 RS |
19600 | -mmicromips generate microMIPS instructions\n\ |
19601 | -mno-micromips do not generate microMIPS instructions\n")); | |
19602 | fprintf (stream, _("\ | |
e16bfa71 TS |
19603 | -msmartmips generate smartmips instructions\n\ |
19604 | -mno-smartmips do not generate smartmips instructions\n")); | |
19605 | fprintf (stream, _("\ | |
74cd071d CF |
19606 | -mdsp generate DSP instructions\n\ |
19607 | -mno-dsp do not generate DSP instructions\n")); | |
19608 | fprintf (stream, _("\ | |
8b082fb1 TS |
19609 | -mdspr2 generate DSP R2 instructions\n\ |
19610 | -mno-dspr2 do not generate DSP R2 instructions\n")); | |
19611 | fprintf (stream, _("\ | |
ef2e4d86 CF |
19612 | -mmt generate MT instructions\n\ |
19613 | -mno-mt do not generate MT instructions\n")); | |
19614 | fprintf (stream, _("\ | |
dec0624d MR |
19615 | -mmcu generate MCU instructions\n\ |
19616 | -mno-mcu do not generate MCU instructions\n")); | |
19617 | fprintf (stream, _("\ | |
b015e599 AP |
19618 | -mvirt generate Virtualization instructions\n\ |
19619 | -mno-virt do not generate Virtualization instructions\n")); | |
19620 | fprintf (stream, _("\ | |
833794fc MR |
19621 | -minsn32 only generate 32-bit microMIPS instructions\n\ |
19622 | -mno-insn32 generate all microMIPS instructions\n")); | |
19623 | fprintf (stream, _("\ | |
c67a084a NC |
19624 | -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\ |
19625 | -mfix-loongson2f-nop work around Loongson2F NOP errata\n\ | |
d766e8ec | 19626 | -mfix-vr4120 work around certain VR4120 errata\n\ |
7d8e00cf | 19627 | -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ |
6a32d874 | 19628 | -mfix-24k insert a nop after ERET and DERET instructions\n\ |
d954098f | 19629 | -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\ |
316f5878 RS |
19630 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
19631 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
aed1a261 | 19632 | -msym32 assume all symbols have 32-bit values\n\ |
316f5878 RS |
19633 | -O0 remove unneeded NOPs, do not swap branches\n\ |
19634 | -O remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
19635 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ |
19636 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
037b32b9 AN |
19637 | fprintf (stream, _("\ |
19638 | -mhard-float allow floating-point instructions\n\ | |
19639 | -msoft-float do not allow floating-point instructions\n\ | |
19640 | -msingle-float only allow 32-bit floating-point operations\n\ | |
19641 | -mdouble-float allow 32-bit and 64-bit floating-point operations\n\ | |
3bf0dbfb | 19642 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ |
ba92f887 MR |
19643 | --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\ |
19644 | -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n")); | |
19645 | ||
19646 | first = 1; | |
19647 | ||
19648 | show (stream, "legacy", &column, &first); | |
19649 | show (stream, "2008", &column, &first); | |
19650 | ||
19651 | fputc ('\n', stream); | |
19652 | ||
316f5878 RS |
19653 | fprintf (stream, _("\ |
19654 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
861fb55a | 19655 | -call_nonpic generate non-PIC code that can operate with DSOs\n\ |
0c000745 | 19656 | -mvxworks-pic generate VxWorks position independent code\n\ |
861fb55a | 19657 | -non_shared do not generate code that can operate with DSOs\n\ |
316f5878 | 19658 | -xgot assume a 32 bit GOT\n\ |
dcd410fe | 19659 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
bbe506e8 | 19660 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
d821e36b | 19661 | position dependent (non shared) code\n\ |
316f5878 RS |
19662 | -mabi=ABI create ABI conformant object file for:\n")); |
19663 | ||
19664 | first = 1; | |
19665 | ||
19666 | show (stream, "32", &column, &first); | |
19667 | show (stream, "o64", &column, &first); | |
19668 | show (stream, "n32", &column, &first); | |
19669 | show (stream, "64", &column, &first); | |
19670 | show (stream, "eabi", &column, &first); | |
19671 | ||
19672 | fputc ('\n', stream); | |
19673 | ||
19674 | fprintf (stream, _("\ | |
19675 | -32 create o32 ABI object file (default)\n\ | |
19676 | -n32 create n32 ABI object file\n\ | |
19677 | -64 create 64 ABI object file\n")); | |
e7af610e | 19678 | } |
14e777e0 | 19679 | |
1575952e | 19680 | #ifdef TE_IRIX |
14e777e0 | 19681 | enum dwarf2_format |
413a266c | 19682 | mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED) |
14e777e0 | 19683 | { |
369943fe | 19684 | if (HAVE_64BIT_SYMBOLS) |
1575952e | 19685 | return dwarf2_format_64bit_irix; |
14e777e0 KB |
19686 | else |
19687 | return dwarf2_format_32bit; | |
19688 | } | |
1575952e | 19689 | #endif |
73369e65 EC |
19690 | |
19691 | int | |
19692 | mips_dwarf2_addr_size (void) | |
19693 | { | |
6b6b3450 | 19694 | if (HAVE_64BIT_OBJECTS) |
73369e65 | 19695 | return 8; |
73369e65 EC |
19696 | else |
19697 | return 4; | |
19698 | } | |
5862107c EC |
19699 | |
19700 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
19701 | void | |
19702 | mips_cfi_frame_initial_instructions (void) | |
19703 | { | |
19704 | cfi_add_CFA_def_cfa_register (SP); | |
19705 | } | |
19706 | ||
707bfff6 TS |
19707 | int |
19708 | tc_mips_regname_to_dw2regnum (char *regname) | |
19709 | { | |
19710 | unsigned int regnum = -1; | |
19711 | unsigned int reg; | |
19712 | ||
19713 | if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®)) | |
19714 | regnum = reg; | |
19715 | ||
19716 | return regnum; | |
19717 | } |