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252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
49309057 | 2 | Copyright (C) 1993, 94, 95, 96, 97, 98, 1999 Free Software Foundation, Inc. |
252b5132 RH |
3 | Contributed by the OSF and Ralph Campbell. |
4 | Written by Keith Knowles and Ralph Campbell, working independently. | |
5 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
6 | Support. | |
7 | ||
8 | This file is part of GAS. | |
9 | ||
10 | GAS is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2, or (at your option) | |
13 | any later version. | |
14 | ||
15 | GAS is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
21 | along with GAS; see the file COPYING. If not, write to the Free | |
22 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
23 | 02111-1307, USA. */ | |
24 | ||
25 | #include "as.h" | |
26 | #include "config.h" | |
27 | #include "subsegs.h" | |
28 | ||
29 | #include <ctype.h> | |
30 | ||
31 | #ifdef USE_STDARG | |
32 | #include <stdarg.h> | |
33 | #endif | |
34 | #ifdef USE_VARARGS | |
35 | #include <varargs.h> | |
36 | #endif | |
37 | ||
38 | #include "opcode/mips.h" | |
39 | #include "itbl-ops.h" | |
40 | ||
41 | #ifdef DEBUG | |
42 | #define DBG(x) printf x | |
43 | #else | |
44 | #define DBG(x) | |
45 | #endif | |
46 | ||
47 | #ifdef OBJ_MAYBE_ELF | |
48 | /* Clean up namespace so we can include obj-elf.h too. */ | |
49 | static int mips_output_flavor PARAMS ((void)); | |
50 | static int mips_output_flavor () { return OUTPUT_FLAVOR; } | |
51 | #undef OBJ_PROCESS_STAB | |
52 | #undef OUTPUT_FLAVOR | |
53 | #undef S_GET_ALIGN | |
54 | #undef S_GET_SIZE | |
55 | #undef S_SET_ALIGN | |
56 | #undef S_SET_SIZE | |
252b5132 RH |
57 | #undef obj_frob_file |
58 | #undef obj_frob_file_after_relocs | |
59 | #undef obj_frob_symbol | |
60 | #undef obj_pop_insert | |
61 | #undef obj_sec_sym_ok_for_reloc | |
62 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
63 | ||
64 | #include "obj-elf.h" | |
65 | /* Fix any of them that we actually care about. */ | |
66 | #undef OUTPUT_FLAVOR | |
67 | #define OUTPUT_FLAVOR mips_output_flavor() | |
68 | #endif | |
69 | ||
70 | #if defined (OBJ_ELF) | |
71 | #include "elf/mips.h" | |
72 | #endif | |
73 | ||
74 | #ifndef ECOFF_DEBUGGING | |
75 | #define NO_ECOFF_DEBUGGING | |
76 | #define ECOFF_DEBUGGING 0 | |
77 | #endif | |
78 | ||
79 | #include "ecoff.h" | |
80 | ||
81 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
82 | static char *mips_regmask_frag; | |
83 | #endif | |
84 | ||
85 | #define AT 1 | |
86 | #define TREG 24 | |
87 | #define PIC_CALL_REG 25 | |
88 | #define KT0 26 | |
89 | #define KT1 27 | |
90 | #define GP 28 | |
91 | #define SP 29 | |
92 | #define FP 30 | |
93 | #define RA 31 | |
94 | ||
95 | #define ILLEGAL_REG (32) | |
96 | ||
97 | /* Allow override of standard little-endian ECOFF format. */ | |
98 | ||
99 | #ifndef ECOFF_LITTLE_FORMAT | |
100 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" | |
101 | #endif | |
102 | ||
103 | extern int target_big_endian; | |
104 | ||
105 | /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the | |
106 | 32 bit ABI. This has no meaning for ECOFF. | |
107 | Note that the default is always 32 bit, even if "configured" for | |
108 | 64 bit [e.g. --target=mips64-elf]. */ | |
109 | static int mips_64; | |
110 | ||
111 | /* The default target format to use. */ | |
112 | const char * | |
113 | mips_target_format () | |
114 | { | |
115 | switch (OUTPUT_FLAVOR) | |
116 | { | |
117 | case bfd_target_aout_flavour: | |
118 | return target_big_endian ? "a.out-mips-big" : "a.out-mips-little"; | |
119 | case bfd_target_ecoff_flavour: | |
120 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; | |
121 | case bfd_target_elf_flavour: | |
122 | return (target_big_endian | |
123 | ? (mips_64 ? "elf64-bigmips" : "elf32-bigmips") | |
124 | : (mips_64 ? "elf64-littlemips" : "elf32-littlemips")); | |
125 | default: | |
126 | abort (); | |
127 | return NULL; | |
128 | } | |
129 | } | |
130 | ||
131 | /* The name of the readonly data section. */ | |
132 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \ | |
133 | ? ".data" \ | |
134 | : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ | |
135 | ? ".rdata" \ | |
136 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ | |
137 | ? ".rodata" \ | |
138 | : (abort (), "")) | |
139 | ||
140 | /* This is the set of options which may be modified by the .set | |
141 | pseudo-op. We use a struct so that .set push and .set pop are more | |
142 | reliable. */ | |
143 | ||
144 | struct mips_set_options | |
145 | { | |
146 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 | |
147 | if it has not been initialized. Changed by `.set mipsN', and the | |
148 | -mipsN command line option, and the default CPU. */ | |
149 | int isa; | |
150 | /* Whether we are assembling for the mips16 processor. 0 if we are | |
151 | not, 1 if we are, and -1 if the value has not been initialized. | |
152 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
153 | -nomips16 command line options, and the default CPU. */ | |
154 | int mips16; | |
155 | /* Non-zero if we should not reorder instructions. Changed by `.set | |
156 | reorder' and `.set noreorder'. */ | |
157 | int noreorder; | |
158 | /* Non-zero if we should not permit the $at ($1) register to be used | |
159 | in instructions. Changed by `.set at' and `.set noat'. */ | |
160 | int noat; | |
161 | /* Non-zero if we should warn when a macro instruction expands into | |
162 | more than one machine instruction. Changed by `.set nomacro' and | |
163 | `.set macro'. */ | |
164 | int warn_about_macros; | |
165 | /* Non-zero if we should not move instructions. Changed by `.set | |
166 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
167 | int nomove; | |
168 | /* Non-zero if we should not optimize branches by moving the target | |
169 | of the branch into the delay slot. Actually, we don't perform | |
170 | this optimization anyhow. Changed by `.set bopt' and `.set | |
171 | nobopt'. */ | |
172 | int nobopt; | |
173 | /* Non-zero if we should not autoextend mips16 instructions. | |
174 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
175 | int noautoextend; | |
176 | }; | |
177 | ||
178 | /* This is the struct we use to hold the current set of options. Note | |
179 | that we must set the isa and mips16 fields to -1 to indicate that | |
180 | they have not been initialized. */ | |
181 | ||
182 | static struct mips_set_options mips_opts = { -1, -1 }; | |
183 | ||
184 | /* These variables are filled in with the masks of registers used. | |
185 | The object format code reads them and puts them in the appropriate | |
186 | place. */ | |
187 | unsigned long mips_gprmask; | |
188 | unsigned long mips_cprmask[4]; | |
189 | ||
190 | /* MIPS ISA we are using for this output file. */ | |
191 | static int file_mips_isa; | |
192 | ||
193 | /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */ | |
194 | static int mips_cpu = -1; | |
195 | ||
196 | /* The argument of the -mabi= flag. */ | |
197 | static char* mips_abi_string = 0; | |
198 | ||
199 | /* Wether we should mark the file EABI64 or EABI32. */ | |
200 | static int mips_eabi64 = 0; | |
201 | ||
202 | /* If they asked for mips1 or mips2 and a cpu that is | |
203 | mips3 or greater, then mark the object file 32BITMODE. */ | |
204 | static int mips_32bitmode = 0; | |
205 | ||
9ce8a5dd GRK |
206 | /* Some ISA's have delay slots for instructions which read or write |
207 | from a coprocessor (eg. mips1-mips3); some don't (eg mips4). | |
208 | Return true if instructions marked INSN_LOAD_COPROC_DELAY, | |
209 | INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a | |
210 | delay slot in this ISA. The uses of this macro assume that any | |
211 | ISA that has delay slots for one of these, has them for all. They | |
212 | also assume that ISAs which don't have delays for these insns, don't | |
213 | have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */ | |
214 | #define ISA_HAS_COPROC_DELAYS(ISA) ( \ | |
215 | (ISA) == 1 \ | |
216 | || (ISA) == 2 \ | |
217 | || (ISA) == 3 \ | |
218 | ) | |
219 | ||
220 | /* Return true if ISA supports 64 bit gp register instructions. */ | |
221 | #define ISA_HAS_64BIT_REGS(ISA) ( \ | |
222 | (ISA) == 3 \ | |
223 | || (ISA) == 4 \ | |
224 | ) | |
225 | ||
252b5132 RH |
226 | /* Whether the processor uses hardware interlocks to protect |
227 | reads from the HI and LO registers, and thus does not | |
228 | require nops to be inserted. | |
229 | ||
230 | FIXME: GCC makes a distinction between -mcpu=FOO and -mFOO: | |
231 | -mcpu=FOO schedules for FOO, but still produces code that meets the | |
232 | requirements of MIPS ISA I. For example, it won't generate any | |
233 | FOO-specific instructions, and it will still assume that any | |
234 | scheduling hazards described in MIPS ISA I are there, even if FOO | |
235 | has interlocks. -mFOO gives GCC permission to generate code that | |
236 | will only run on a FOO; it will generate FOO-specific instructions, | |
237 | and assume interlocks provided by a FOO. | |
238 | ||
239 | However, GAS currently doesn't make this distinction; before Jan 28 | |
240 | 1999, GAS's -mcpu=FOO implied -mFOO, which violates GCC's | |
241 | assumptions. The GCC driver passes these flags through to GAS, so | |
242 | if GAS actually does anything that doesn't meet MIPS ISA I with | |
243 | -mFOO, then GCC's -mcpu=FOO flag isn't going to work. | |
244 | ||
245 | And furthermore, it did not assume that -mFOO implied -mcpu=FOO, | |
246 | which seems senseless --- why generate code which will only run on | |
247 | a FOO, but schedule for something else? | |
248 | ||
249 | So now, at least, -mcpu=FOO and -mFOO are exactly equivalent. | |
250 | ||
251 | -- Jim Blandy <jimb@cygnus.com> */ | |
252 | ||
253 | #define hilo_interlocks (mips_cpu == 4010 \ | |
254 | ) | |
255 | ||
256 | /* Whether the processor uses hardware interlocks to protect reads | |
257 | from the GPRs, and thus does not require nops to be inserted. */ | |
258 | #define gpr_interlocks \ | |
9ce8a5dd | 259 | (mips_opts.isa != 1 \ |
252b5132 RH |
260 | || mips_cpu == 3900) |
261 | ||
262 | /* As with other "interlocks" this is used by hardware that has FP | |
263 | (co-processor) interlocks. */ | |
264 | /* Itbl support may require additional care here. */ | |
265 | #define cop_interlocks (mips_cpu == 4300 \ | |
266 | ) | |
267 | ||
6b76fefe CM |
268 | /* Is this a mfhi or mflo instruction? */ |
269 | #define MF_HILO_INSN(PINFO) \ | |
270 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) | |
271 | ||
252b5132 RH |
272 | /* MIPS PIC level. */ |
273 | ||
274 | enum mips_pic_level | |
275 | { | |
276 | /* Do not generate PIC code. */ | |
277 | NO_PIC, | |
278 | ||
279 | /* Generate PIC code as in Irix 4. This is not implemented, and I'm | |
280 | not sure what it is supposed to do. */ | |
281 | IRIX4_PIC, | |
282 | ||
283 | /* Generate PIC code as in the SVR4 MIPS ABI. */ | |
284 | SVR4_PIC, | |
285 | ||
286 | /* Generate PIC code without using a global offset table: the data | |
287 | segment has a maximum size of 64K, all data references are off | |
288 | the $gp register, and all text references are PC relative. This | |
289 | is used on some embedded systems. */ | |
290 | EMBEDDED_PIC | |
291 | }; | |
292 | ||
293 | static enum mips_pic_level mips_pic; | |
294 | ||
295 | /* 1 if we should generate 32 bit offsets from the GP register in | |
296 | SVR4_PIC mode. Currently has no meaning in other modes. */ | |
297 | static int mips_big_got; | |
298 | ||
299 | /* 1 if trap instructions should used for overflow rather than break | |
300 | instructions. */ | |
301 | static int mips_trap; | |
302 | ||
303 | /* Non-zero if any .set noreorder directives were used. */ | |
304 | ||
305 | static int mips_any_noreorder; | |
306 | ||
6b76fefe CM |
307 | /* Non-zero if nops should be inserted when the register referenced in |
308 | an mfhi/mflo instruction is read in the next two instructions. */ | |
309 | static int mips_7000_hilo_fix; | |
310 | ||
252b5132 RH |
311 | /* The size of the small data section. */ |
312 | static int g_switch_value = 8; | |
313 | /* Whether the -G option was used. */ | |
314 | static int g_switch_seen = 0; | |
315 | ||
316 | #define N_RMASK 0xc4 | |
317 | #define N_VFP 0xd4 | |
318 | ||
319 | /* If we can determine in advance that GP optimization won't be | |
320 | possible, we can skip the relaxation stuff that tries to produce | |
321 | GP-relative references. This makes delay slot optimization work | |
322 | better. | |
323 | ||
324 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
325 | gcc output. It needs to guess right for gcc, otherwise gcc |
326 | will put what it thinks is a GP-relative instruction in a branch | |
327 | delay slot. | |
252b5132 RH |
328 | |
329 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
330 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
331 | static int nopic_need_relax PARAMS ((symbolS *, int)); | |
332 | ||
333 | /* handle of the OPCODE hash table */ | |
334 | static struct hash_control *op_hash = NULL; | |
335 | ||
336 | /* The opcode hash table we use for the mips16. */ | |
337 | static struct hash_control *mips16_op_hash = NULL; | |
338 | ||
339 | /* This array holds the chars that always start a comment. If the | |
340 | pre-processor is disabled, these aren't very useful */ | |
341 | const char comment_chars[] = "#"; | |
342 | ||
343 | /* This array holds the chars that only start a comment at the beginning of | |
344 | a line. If the line seems to have the form '# 123 filename' | |
345 | .line and .file directives will appear in the pre-processed output */ | |
346 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
347 | first line of the input file. This is because the compiler outputs | |
348 | #NO_APP at the beginning of its output. */ | |
349 | /* Also note that C style comments are always supported. */ | |
350 | const char line_comment_chars[] = "#"; | |
351 | ||
352 | /* This array holds machine specific line separator characters. */ | |
353 | const char line_separator_chars[] = ""; | |
354 | ||
355 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
356 | const char EXP_CHARS[] = "eE"; | |
357 | ||
358 | /* Chars that mean this number is a floating point constant */ | |
359 | /* As in 0f12.456 */ | |
360 | /* or 0d1.2345e12 */ | |
361 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
362 | ||
363 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
364 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
365 | but nothing is ideal around here. | |
366 | */ | |
367 | ||
368 | static char *insn_error; | |
369 | ||
370 | static int auto_align = 1; | |
371 | ||
372 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
373 | offset in the stack frame from which to restore the $gp register. | |
374 | This is set by the .cprestore pseudo-op, and saved in this | |
375 | variable. */ | |
376 | static offsetT mips_cprestore_offset = -1; | |
377 | ||
378 | /* This is the register which holds the stack frame, as set by the | |
379 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
380 | static int mips_frame_reg = SP; | |
381 | ||
382 | /* To output NOP instructions correctly, we need to keep information | |
383 | about the previous two instructions. */ | |
384 | ||
385 | /* Whether we are optimizing. The default value of 2 means to remove | |
386 | unneeded NOPs and swap branch instructions when possible. A value | |
387 | of 1 means to not swap branches. A value of 0 means to always | |
388 | insert NOPs. */ | |
389 | static int mips_optimize = 2; | |
390 | ||
391 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
392 | equivalent to seeing no -g option at all. */ | |
393 | static int mips_debug = 0; | |
394 | ||
395 | /* The previous instruction. */ | |
396 | static struct mips_cl_insn prev_insn; | |
397 | ||
398 | /* The instruction before prev_insn. */ | |
399 | static struct mips_cl_insn prev_prev_insn; | |
400 | ||
401 | /* If we don't want information for prev_insn or prev_prev_insn, we | |
402 | point the insn_mo field at this dummy integer. */ | |
403 | static const struct mips_opcode dummy_opcode = { 0 }; | |
404 | ||
405 | /* Non-zero if prev_insn is valid. */ | |
406 | static int prev_insn_valid; | |
407 | ||
408 | /* The frag for the previous instruction. */ | |
409 | static struct frag *prev_insn_frag; | |
410 | ||
411 | /* The offset into prev_insn_frag for the previous instruction. */ | |
412 | static long prev_insn_where; | |
413 | ||
414 | /* The reloc type for the previous instruction, if any. */ | |
415 | static bfd_reloc_code_real_type prev_insn_reloc_type; | |
416 | ||
417 | /* The reloc for the previous instruction, if any. */ | |
418 | static fixS *prev_insn_fixp; | |
419 | ||
420 | /* Non-zero if the previous instruction was in a delay slot. */ | |
421 | static int prev_insn_is_delay_slot; | |
422 | ||
423 | /* Non-zero if the previous instruction was in a .set noreorder. */ | |
424 | static int prev_insn_unreordered; | |
425 | ||
426 | /* Non-zero if the previous instruction uses an extend opcode (if | |
427 | mips16). */ | |
428 | static int prev_insn_extended; | |
429 | ||
430 | /* Non-zero if the previous previous instruction was in a .set | |
431 | noreorder. */ | |
432 | static int prev_prev_insn_unreordered; | |
433 | ||
434 | /* If this is set, it points to a frag holding nop instructions which | |
435 | were inserted before the start of a noreorder section. If those | |
436 | nops turn out to be unnecessary, the size of the frag can be | |
437 | decreased. */ | |
438 | static fragS *prev_nop_frag; | |
439 | ||
440 | /* The number of nop instructions we created in prev_nop_frag. */ | |
441 | static int prev_nop_frag_holds; | |
442 | ||
443 | /* The number of nop instructions that we know we need in | |
444 | prev_nop_frag. */ | |
445 | static int prev_nop_frag_required; | |
446 | ||
447 | /* The number of instructions we've seen since prev_nop_frag. */ | |
448 | static int prev_nop_frag_since; | |
449 | ||
450 | /* For ECOFF and ELF, relocations against symbols are done in two | |
451 | parts, with a HI relocation and a LO relocation. Each relocation | |
452 | has only 16 bits of space to store an addend. This means that in | |
453 | order for the linker to handle carries correctly, it must be able | |
454 | to locate both the HI and the LO relocation. This means that the | |
455 | relocations must appear in order in the relocation table. | |
456 | ||
457 | In order to implement this, we keep track of each unmatched HI | |
458 | relocation. We then sort them so that they immediately precede the | |
459 | corresponding LO relocation. */ | |
460 | ||
461 | struct mips_hi_fixup | |
462 | { | |
463 | /* Next HI fixup. */ | |
464 | struct mips_hi_fixup *next; | |
465 | /* This fixup. */ | |
466 | fixS *fixp; | |
467 | /* The section this fixup is in. */ | |
468 | segT seg; | |
469 | }; | |
470 | ||
471 | /* The list of unmatched HI relocs. */ | |
472 | ||
473 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
474 | ||
475 | /* Map normal MIPS register numbers to mips16 register numbers. */ | |
476 | ||
477 | #define X ILLEGAL_REG | |
478 | static const int mips32_to_16_reg_map[] = | |
479 | { | |
480 | X, X, 2, 3, 4, 5, 6, 7, | |
481 | X, X, X, X, X, X, X, X, | |
482 | 0, 1, X, X, X, X, X, X, | |
483 | X, X, X, X, X, X, X, X | |
484 | }; | |
485 | #undef X | |
486 | ||
487 | /* Map mips16 register numbers to normal MIPS register numbers. */ | |
488 | ||
489 | static const int mips16_to_32_reg_map[] = | |
490 | { | |
491 | 16, 17, 2, 3, 4, 5, 6, 7 | |
492 | }; | |
493 | \f | |
494 | /* Since the MIPS does not have multiple forms of PC relative | |
495 | instructions, we do not have to do relaxing as is done on other | |
496 | platforms. However, we do have to handle GP relative addressing | |
497 | correctly, which turns out to be a similar problem. | |
498 | ||
499 | Every macro that refers to a symbol can occur in (at least) two | |
500 | forms, one with GP relative addressing and one without. For | |
501 | example, loading a global variable into a register generally uses | |
502 | a macro instruction like this: | |
503 | lw $4,i | |
504 | If i can be addressed off the GP register (this is true if it is in | |
505 | the .sbss or .sdata section, or if it is known to be smaller than | |
506 | the -G argument) this will generate the following instruction: | |
507 | lw $4,i($gp) | |
508 | This instruction will use a GPREL reloc. If i can not be addressed | |
509 | off the GP register, the following instruction sequence will be used: | |
510 | lui $at,i | |
511 | lw $4,i($at) | |
512 | In this case the first instruction will have a HI16 reloc, and the | |
513 | second reloc will have a LO16 reloc. Both relocs will be against | |
514 | the symbol i. | |
515 | ||
516 | The issue here is that we may not know whether i is GP addressable | |
517 | until after we see the instruction that uses it. Therefore, we | |
518 | want to be able to choose the final instruction sequence only at | |
519 | the end of the assembly. This is similar to the way other | |
520 | platforms choose the size of a PC relative instruction only at the | |
521 | end of assembly. | |
522 | ||
523 | When generating position independent code we do not use GP | |
524 | addressing in quite the same way, but the issue still arises as | |
525 | external symbols and local symbols must be handled differently. | |
526 | ||
527 | We handle these issues by actually generating both possible | |
528 | instruction sequences. The longer one is put in a frag_var with | |
529 | type rs_machine_dependent. We encode what to do with the frag in | |
530 | the subtype field. We encode (1) the number of existing bytes to | |
531 | replace, (2) the number of new bytes to use, (3) the offset from | |
532 | the start of the existing bytes to the first reloc we must generate | |
533 | (that is, the offset is applied from the start of the existing | |
534 | bytes after they are replaced by the new bytes, if any), (4) the | |
535 | offset from the start of the existing bytes to the second reloc, | |
536 | (5) whether a third reloc is needed (the third reloc is always four | |
537 | bytes after the second reloc), and (6) whether to warn if this | |
538 | variant is used (this is sometimes needed if .set nomacro or .set | |
539 | noat is in effect). All these numbers are reasonably small. | |
540 | ||
541 | Generating two instruction sequences must be handled carefully to | |
542 | ensure that delay slots are handled correctly. Fortunately, there | |
543 | are a limited number of cases. When the second instruction | |
544 | sequence is generated, append_insn is directed to maintain the | |
545 | existing delay slot information, so it continues to apply to any | |
546 | code after the second instruction sequence. This means that the | |
547 | second instruction sequence must not impose any requirements not | |
548 | required by the first instruction sequence. | |
549 | ||
550 | These variant frags are then handled in functions called by the | |
551 | machine independent code. md_estimate_size_before_relax returns | |
552 | the final size of the frag. md_convert_frag sets up the final form | |
553 | of the frag. tc_gen_reloc adjust the first reloc and adds a second | |
554 | one if needed. */ | |
555 | #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \ | |
556 | ((relax_substateT) \ | |
557 | (((old) << 23) \ | |
558 | | ((new) << 16) \ | |
559 | | (((reloc1) + 64) << 9) \ | |
560 | | (((reloc2) + 64) << 2) \ | |
561 | | ((reloc3) ? (1 << 1) : 0) \ | |
562 | | ((warn) ? 1 : 0))) | |
563 | #define RELAX_OLD(i) (((i) >> 23) & 0x7f) | |
564 | #define RELAX_NEW(i) (((i) >> 16) & 0x7f) | |
565 | #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64) | |
566 | #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64) | |
567 | #define RELAX_RELOC3(i) (((i) >> 1) & 1) | |
568 | #define RELAX_WARN(i) ((i) & 1) | |
569 | ||
570 | /* For mips16 code, we use an entirely different form of relaxation. | |
571 | mips16 supports two versions of most instructions which take | |
572 | immediate values: a small one which takes some small value, and a | |
573 | larger one which takes a 16 bit value. Since branches also follow | |
574 | this pattern, relaxing these values is required. | |
575 | ||
576 | We can assemble both mips16 and normal MIPS code in a single | |
577 | object. Therefore, we need to support this type of relaxation at | |
578 | the same time that we support the relaxation described above. We | |
579 | use the high bit of the subtype field to distinguish these cases. | |
580 | ||
581 | The information we store for this type of relaxation is the | |
582 | argument code found in the opcode file for this relocation, whether | |
583 | the user explicitly requested a small or extended form, and whether | |
584 | the relocation is in a jump or jal delay slot. That tells us the | |
585 | size of the value, and how it should be stored. We also store | |
586 | whether the fragment is considered to be extended or not. We also | |
587 | store whether this is known to be a branch to a different section, | |
588 | whether we have tried to relax this frag yet, and whether we have | |
589 | ever extended a PC relative fragment because of a shift count. */ | |
590 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ | |
591 | (0x80000000 \ | |
592 | | ((type) & 0xff) \ | |
593 | | ((small) ? 0x100 : 0) \ | |
594 | | ((ext) ? 0x200 : 0) \ | |
595 | | ((dslot) ? 0x400 : 0) \ | |
596 | | ((jal_dslot) ? 0x800 : 0)) | |
597 | #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0) | |
598 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) | |
599 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) | |
600 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) | |
601 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) | |
602 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) | |
603 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) | |
604 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) | |
605 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) | |
606 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) | |
607 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) | |
608 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) | |
609 | \f | |
610 | /* Prototypes for static functions. */ | |
611 | ||
612 | #ifdef __STDC__ | |
613 | #define internalError() \ | |
614 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) | |
615 | #else | |
616 | #define internalError() as_fatal (_("MIPS internal Error")); | |
617 | #endif | |
618 | ||
619 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; | |
620 | ||
621 | static int insn_uses_reg PARAMS ((struct mips_cl_insn *ip, | |
622 | unsigned int reg, enum mips_regclass class)); | |
623 | static int reg_needs_delay PARAMS ((int)); | |
624 | static void mips16_mark_labels PARAMS ((void)); | |
625 | static void append_insn PARAMS ((char *place, | |
626 | struct mips_cl_insn * ip, | |
627 | expressionS * p, | |
628 | bfd_reloc_code_real_type r, | |
629 | boolean)); | |
630 | static void mips_no_prev_insn PARAMS ((int)); | |
631 | static void mips_emit_delays PARAMS ((boolean)); | |
632 | #ifdef USE_STDARG | |
633 | static void macro_build PARAMS ((char *place, int *counter, expressionS * ep, | |
634 | const char *name, const char *fmt, | |
635 | ...)); | |
636 | #else | |
637 | static void macro_build (); | |
638 | #endif | |
639 | static void mips16_macro_build PARAMS ((char *, int *, expressionS *, | |
640 | const char *, const char *, | |
641 | va_list)); | |
642 | static void macro_build_lui PARAMS ((char *place, int *counter, | |
643 | expressionS * ep, int regnum)); | |
644 | static void set_at PARAMS ((int *counter, int reg, int unsignedp)); | |
645 | static void check_absolute_expr PARAMS ((struct mips_cl_insn * ip, | |
646 | expressionS *)); | |
647 | static void load_register PARAMS ((int *, int, expressionS *, int)); | |
648 | static void load_address PARAMS ((int *counter, int reg, expressionS *ep)); | |
649 | static void macro PARAMS ((struct mips_cl_insn * ip)); | |
650 | static void mips16_macro PARAMS ((struct mips_cl_insn * ip)); | |
651 | #ifdef LOSING_COMPILER | |
652 | static void macro2 PARAMS ((struct mips_cl_insn * ip)); | |
653 | #endif | |
654 | static void mips_ip PARAMS ((char *str, struct mips_cl_insn * ip)); | |
655 | static void mips16_ip PARAMS ((char *str, struct mips_cl_insn * ip)); | |
656 | static void mips16_immed PARAMS ((char *, unsigned int, int, offsetT, boolean, | |
657 | boolean, boolean, unsigned long *, | |
658 | boolean *, unsigned short *)); | |
659 | static int my_getSmallExpression PARAMS ((expressionS * ep, char *str)); | |
660 | static void my_getExpression PARAMS ((expressionS * ep, char *str)); | |
661 | static symbolS *get_symbol PARAMS ((void)); | |
662 | static void mips_align PARAMS ((int to, int fill, symbolS *label)); | |
663 | static void s_align PARAMS ((int)); | |
664 | static void s_change_sec PARAMS ((int)); | |
665 | static void s_cons PARAMS ((int)); | |
666 | static void s_float_cons PARAMS ((int)); | |
667 | static void s_mips_globl PARAMS ((int)); | |
668 | static void s_option PARAMS ((int)); | |
669 | static void s_mipsset PARAMS ((int)); | |
670 | static void s_abicalls PARAMS ((int)); | |
671 | static void s_cpload PARAMS ((int)); | |
672 | static void s_cprestore PARAMS ((int)); | |
673 | static void s_gpword PARAMS ((int)); | |
674 | static void s_cpadd PARAMS ((int)); | |
675 | static void s_insn PARAMS ((int)); | |
676 | static void md_obj_begin PARAMS ((void)); | |
677 | static void md_obj_end PARAMS ((void)); | |
678 | static long get_number PARAMS ((void)); | |
679 | static void s_mips_ent PARAMS ((int)); | |
680 | static void s_mips_end PARAMS ((int)); | |
681 | static void s_mips_frame PARAMS ((int)); | |
682 | static void s_mips_mask PARAMS ((int)); | |
683 | static void s_mips_stab PARAMS ((int)); | |
684 | static void s_mips_weakext PARAMS ((int)); | |
685 | static void s_file PARAMS ((int)); | |
686 | static int mips16_extended_frag PARAMS ((fragS *, asection *, long)); | |
687 | ||
688 | ||
689 | static int validate_mips_insn PARAMS ((const struct mips_opcode *)); | |
690 | \f | |
691 | /* Pseudo-op table. | |
692 | ||
693 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
694 | should be defined here, but are currently unsupported: .alias, | |
695 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
696 | ||
697 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
698 | specific to the type of debugging information being generated, and | |
699 | should be defined by the object format: .aent, .begin, .bend, | |
700 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
701 | .vreg. | |
702 | ||
703 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
704 | not MIPS CPU specific, but are also not specific to the object file | |
705 | format. This file is probably the best place to define them, but | |
706 | they are not currently supported: .asm0, .endr, .lab, .repeat, | |
707 | .struct. */ | |
708 | ||
709 | static const pseudo_typeS mips_pseudo_table[] = | |
710 | { | |
711 | /* MIPS specific pseudo-ops. */ | |
712 | {"option", s_option, 0}, | |
713 | {"set", s_mipsset, 0}, | |
714 | {"rdata", s_change_sec, 'r'}, | |
715 | {"sdata", s_change_sec, 's'}, | |
716 | {"livereg", s_ignore, 0}, | |
717 | {"abicalls", s_abicalls, 0}, | |
718 | {"cpload", s_cpload, 0}, | |
719 | {"cprestore", s_cprestore, 0}, | |
720 | {"gpword", s_gpword, 0}, | |
721 | {"cpadd", s_cpadd, 0}, | |
722 | {"insn", s_insn, 0}, | |
723 | ||
724 | /* Relatively generic pseudo-ops that happen to be used on MIPS | |
725 | chips. */ | |
726 | {"asciiz", stringer, 1}, | |
727 | {"bss", s_change_sec, 'b'}, | |
728 | {"err", s_err, 0}, | |
729 | {"half", s_cons, 1}, | |
730 | {"dword", s_cons, 3}, | |
731 | {"weakext", s_mips_weakext, 0}, | |
732 | ||
733 | /* These pseudo-ops are defined in read.c, but must be overridden | |
734 | here for one reason or another. */ | |
735 | {"align", s_align, 0}, | |
736 | {"byte", s_cons, 0}, | |
737 | {"data", s_change_sec, 'd'}, | |
738 | {"double", s_float_cons, 'd'}, | |
739 | {"float", s_float_cons, 'f'}, | |
740 | {"globl", s_mips_globl, 0}, | |
741 | {"global", s_mips_globl, 0}, | |
742 | {"hword", s_cons, 1}, | |
743 | {"int", s_cons, 2}, | |
744 | {"long", s_cons, 2}, | |
745 | {"octa", s_cons, 4}, | |
746 | {"quad", s_cons, 3}, | |
747 | {"short", s_cons, 1}, | |
748 | {"single", s_float_cons, 'f'}, | |
749 | {"stabn", s_mips_stab, 'n'}, | |
750 | {"text", s_change_sec, 't'}, | |
751 | {"word", s_cons, 2}, | |
752 | { 0 }, | |
753 | }; | |
754 | ||
755 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = { | |
756 | /* These pseudo-ops should be defined by the object file format. | |
757 | However, a.out doesn't support them, so we have versions here. */ | |
758 | {"aent", s_mips_ent, 1}, | |
759 | {"bgnb", s_ignore, 0}, | |
760 | {"end", s_mips_end, 0}, | |
761 | {"endb", s_ignore, 0}, | |
762 | {"ent", s_mips_ent, 0}, | |
763 | {"file", s_file, 0}, | |
764 | {"fmask", s_mips_mask, 'F'}, | |
765 | {"frame", s_mips_frame, 0}, | |
766 | {"loc", s_ignore, 0}, | |
767 | {"mask", s_mips_mask, 'R'}, | |
768 | {"verstamp", s_ignore, 0}, | |
769 | { 0 }, | |
770 | }; | |
771 | ||
772 | extern void pop_insert PARAMS ((const pseudo_typeS *)); | |
773 | ||
774 | void | |
775 | mips_pop_insert () | |
776 | { | |
777 | pop_insert (mips_pseudo_table); | |
778 | if (! ECOFF_DEBUGGING) | |
779 | pop_insert (mips_nonecoff_pseudo_table); | |
780 | } | |
781 | \f | |
782 | /* Symbols labelling the current insn. */ | |
783 | ||
784 | struct insn_label_list | |
785 | { | |
786 | struct insn_label_list *next; | |
787 | symbolS *label; | |
788 | }; | |
789 | ||
790 | static struct insn_label_list *insn_labels; | |
791 | static struct insn_label_list *free_insn_labels; | |
792 | ||
793 | static void mips_clear_insn_labels PARAMS ((void)); | |
794 | ||
795 | static inline void | |
796 | mips_clear_insn_labels () | |
797 | { | |
798 | register struct insn_label_list **pl; | |
799 | ||
800 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
801 | ; | |
802 | *pl = insn_labels; | |
803 | insn_labels = NULL; | |
804 | } | |
805 | \f | |
806 | static char *expr_end; | |
807 | ||
808 | /* Expressions which appear in instructions. These are set by | |
809 | mips_ip. */ | |
810 | ||
811 | static expressionS imm_expr; | |
812 | static expressionS offset_expr; | |
813 | ||
814 | /* Relocs associated with imm_expr and offset_expr. */ | |
815 | ||
816 | static bfd_reloc_code_real_type imm_reloc; | |
817 | static bfd_reloc_code_real_type offset_reloc; | |
818 | ||
819 | /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */ | |
820 | ||
821 | static boolean imm_unmatched_hi; | |
822 | ||
823 | /* These are set by mips16_ip if an explicit extension is used. */ | |
824 | ||
825 | static boolean mips16_small, mips16_ext; | |
826 | ||
827 | #ifdef MIPS_STABS_ELF | |
828 | /* The pdr segment for per procedure frame/regmask info */ | |
829 | ||
830 | static segT pdr_seg; | |
831 | #endif | |
832 | ||
833 | /* | |
834 | * This function is called once, at assembler startup time. It should | |
835 | * set up all the tables, etc. that the MD part of the assembler will need. | |
836 | */ | |
837 | void | |
838 | md_begin () | |
839 | { | |
840 | boolean ok = false; | |
841 | register const char *retval = NULL; | |
842 | register unsigned int i = 0; | |
843 | const char *cpu; | |
844 | char *a = NULL; | |
845 | int broken = 0; | |
846 | int mips_isa_from_cpu; | |
847 | ||
848 | cpu = TARGET_CPU; | |
849 | if (strcmp (cpu + (sizeof TARGET_CPU) - 3, "el") == 0) | |
850 | { | |
851 | a = xmalloc (sizeof TARGET_CPU); | |
852 | strcpy (a, TARGET_CPU); | |
853 | a[(sizeof TARGET_CPU) - 3] = '\0'; | |
854 | cpu = a; | |
855 | } | |
856 | ||
857 | if (mips_cpu < 0) | |
858 | { | |
859 | /* Set mips_cpu based on TARGET_CPU, unless TARGET_CPU is | |
860 | just the generic 'mips', in which case set mips_cpu based | |
861 | on the given ISA, if any. */ | |
862 | ||
863 | if (strcmp (cpu, "mips") == 0) | |
864 | { | |
9ce8a5dd GRK |
865 | if (mips_opts.isa < 0) |
866 | mips_cpu = 3000; | |
252b5132 | 867 | |
9ce8a5dd | 868 | else if (mips_opts.isa == 2) |
252b5132 RH |
869 | mips_cpu = 6000; |
870 | ||
871 | else if (mips_opts.isa == 3) | |
872 | mips_cpu = 4000; | |
873 | ||
874 | else if (mips_opts.isa == 4) | |
875 | mips_cpu = 8000; | |
876 | ||
877 | else | |
878 | mips_cpu = 3000; | |
879 | } | |
880 | ||
881 | else if (strcmp (cpu, "r3900") == 0 | |
882 | || strcmp (cpu, "mipstx39") == 0 | |
883 | ) | |
884 | mips_cpu = 3900; | |
885 | ||
886 | else if (strcmp (cpu, "r6000") == 0 | |
887 | || strcmp (cpu, "mips2") == 0) | |
888 | mips_cpu = 6000; | |
889 | ||
890 | else if (strcmp (cpu, "mips64") == 0 | |
891 | || strcmp (cpu, "r4000") == 0 | |
892 | || strcmp (cpu, "mips3") == 0) | |
893 | mips_cpu = 4000; | |
894 | ||
895 | else if (strcmp (cpu, "r4400") == 0) | |
896 | mips_cpu = 4400; | |
897 | ||
898 | else if (strcmp (cpu, "mips64orion") == 0 | |
899 | || strcmp (cpu, "r4600") == 0) | |
900 | mips_cpu = 4600; | |
901 | ||
902 | else if (strcmp (cpu, "r4650") == 0) | |
903 | mips_cpu = 4650; | |
904 | ||
905 | else if (strcmp (cpu, "mips64vr4300") == 0) | |
906 | mips_cpu = 4300; | |
907 | ||
908 | else if (strcmp (cpu, "mips64vr4111") == 0) | |
909 | mips_cpu = 4111; | |
910 | ||
911 | else if (strcmp (cpu, "mips64vr4100") == 0) | |
912 | mips_cpu = 4100; | |
913 | ||
914 | else if (strcmp (cpu, "r4010") == 0) | |
915 | mips_cpu = 4010; | |
916 | ||
917 | ||
918 | else if (strcmp (cpu, "r5000") == 0 | |
919 | || strcmp (cpu, "mips64vr5000") == 0) | |
920 | mips_cpu = 5000; | |
921 | ||
922 | ||
923 | ||
924 | else if (strcmp (cpu, "r8000") == 0 | |
925 | || strcmp (cpu, "mips4") == 0) | |
926 | mips_cpu = 8000; | |
927 | ||
928 | else if (strcmp (cpu, "r10000") == 0) | |
929 | mips_cpu = 10000; | |
930 | ||
931 | else if (strcmp (cpu, "mips16") == 0) | |
932 | mips_cpu = 0; /* FIXME */ | |
933 | ||
934 | else | |
935 | mips_cpu = 3000; | |
936 | } | |
937 | ||
938 | if (mips_cpu == 3000 | |
939 | || mips_cpu == 3900) | |
940 | mips_isa_from_cpu = 1; | |
941 | ||
942 | else if (mips_cpu == 6000 | |
943 | || mips_cpu == 4010) | |
944 | mips_isa_from_cpu = 2; | |
945 | ||
946 | else if (mips_cpu == 4000 | |
947 | || mips_cpu == 4100 | |
948 | || mips_cpu == 4111 | |
949 | || mips_cpu == 4400 | |
950 | || mips_cpu == 4300 | |
951 | || mips_cpu == 4600 | |
952 | || mips_cpu == 4650) | |
953 | mips_isa_from_cpu = 3; | |
954 | ||
955 | else if (mips_cpu == 5000 | |
956 | || mips_cpu == 8000 | |
957 | || mips_cpu == 10000) | |
958 | mips_isa_from_cpu = 4; | |
959 | ||
960 | else | |
961 | mips_isa_from_cpu = -1; | |
962 | ||
963 | if (mips_opts.isa == -1) | |
964 | { | |
965 | if (mips_isa_from_cpu != -1) | |
966 | mips_opts.isa = mips_isa_from_cpu; | |
967 | else | |
968 | mips_opts.isa = 1; | |
969 | } | |
970 | ||
971 | if (mips_opts.mips16 < 0) | |
972 | { | |
973 | if (strncmp (TARGET_CPU, "mips16", sizeof "mips16" - 1) == 0) | |
974 | mips_opts.mips16 = 1; | |
975 | else | |
976 | mips_opts.mips16 = 0; | |
977 | } | |
978 | ||
979 | /* End of TARGET_CPU processing, get rid of malloced memory | |
980 | if necessary. */ | |
981 | cpu = NULL; | |
982 | if (a != NULL) | |
983 | { | |
984 | free (a); | |
985 | a = NULL; | |
986 | } | |
987 | ||
9ce8a5dd | 988 | if (mips_opts.isa == 1 && mips_trap) |
252b5132 RH |
989 | as_bad (_("trap exception not supported at ISA 1")); |
990 | ||
991 | /* Set the EABI kind based on the ISA before the user gets | |
992 | to change the ISA with directives. This isn't really | |
993 | the best, but then neither is basing the abi on the isa. */ | |
9ce8a5dd | 994 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) |
252b5132 RH |
995 | && mips_abi_string |
996 | && 0 == strcmp (mips_abi_string,"eabi")) | |
997 | mips_eabi64 = 1; | |
998 | ||
999 | if (mips_cpu != 0 && mips_cpu != -1) | |
1000 | { | |
1001 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, mips_cpu); | |
9ce8a5dd | 1002 | |
252b5132 RH |
1003 | /* If they asked for mips1 or mips2 and a cpu that is |
1004 | mips3 or greater, then mark the object file 32BITMODE. */ | |
1005 | if (mips_isa_from_cpu != -1 | |
9ce8a5dd GRK |
1006 | && ! ISA_HAS_64BIT_REGS (mips_opts.isa) |
1007 | && ISA_HAS_64BIT_REGS (mips_isa_from_cpu)) | |
252b5132 RH |
1008 | mips_32bitmode = 1; |
1009 | } | |
1010 | else | |
1011 | { | |
1012 | switch (mips_opts.isa) | |
1013 | { | |
1014 | case 1: | |
1015 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 3000); | |
1016 | break; | |
1017 | case 2: | |
1018 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 6000); | |
1019 | break; | |
1020 | case 3: | |
1021 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 4000); | |
1022 | break; | |
1023 | case 4: | |
1024 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, 8000); | |
1025 | break; | |
1026 | } | |
1027 | } | |
1028 | ||
1029 | if (! ok) | |
1030 | as_warn (_("Could not set architecture and machine")); | |
1031 | ||
1032 | file_mips_isa = mips_opts.isa; | |
1033 | ||
1034 | op_hash = hash_new (); | |
1035 | ||
1036 | for (i = 0; i < NUMOPCODES;) | |
1037 | { | |
1038 | const char *name = mips_opcodes[i].name; | |
1039 | ||
1040 | retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]); | |
1041 | if (retval != NULL) | |
1042 | { | |
1043 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
1044 | mips_opcodes[i].name, retval); | |
1045 | /* Probably a memory allocation problem? Give up now. */ | |
1046 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1047 | } | |
1048 | do | |
1049 | { | |
1050 | if (mips_opcodes[i].pinfo != INSN_MACRO) | |
1051 | { | |
1052 | if (!validate_mips_insn (&mips_opcodes[i])) | |
1053 | broken = 1; | |
1054 | } | |
1055 | ++i; | |
1056 | } | |
1057 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
1058 | } | |
1059 | ||
1060 | mips16_op_hash = hash_new (); | |
1061 | ||
1062 | i = 0; | |
1063 | while (i < bfd_mips16_num_opcodes) | |
1064 | { | |
1065 | const char *name = mips16_opcodes[i].name; | |
1066 | ||
1067 | retval = hash_insert (mips16_op_hash, name, (PTR) &mips16_opcodes[i]); | |
1068 | if (retval != NULL) | |
1069 | as_fatal (_("internal: can't hash `%s': %s"), | |
1070 | mips16_opcodes[i].name, retval); | |
1071 | do | |
1072 | { | |
1073 | if (mips16_opcodes[i].pinfo != INSN_MACRO | |
1074 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) | |
1075 | != mips16_opcodes[i].match)) | |
1076 | { | |
1077 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), | |
1078 | mips16_opcodes[i].name, mips16_opcodes[i].args); | |
1079 | broken = 1; | |
1080 | } | |
1081 | ++i; | |
1082 | } | |
1083 | while (i < bfd_mips16_num_opcodes | |
1084 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
1085 | } | |
1086 | ||
1087 | if (broken) | |
1088 | as_fatal (_("Broken assembler. No assembly attempted.")); | |
1089 | ||
1090 | /* We add all the general register names to the symbol table. This | |
1091 | helps us detect invalid uses of them. */ | |
1092 | for (i = 0; i < 32; i++) | |
1093 | { | |
1094 | char buf[5]; | |
1095 | ||
1096 | sprintf (buf, "$%d", i); | |
1097 | symbol_table_insert (symbol_new (buf, reg_section, i, | |
1098 | &zero_address_frag)); | |
1099 | } | |
1100 | symbol_table_insert (symbol_new ("$fp", reg_section, FP, | |
1101 | &zero_address_frag)); | |
1102 | symbol_table_insert (symbol_new ("$sp", reg_section, SP, | |
1103 | &zero_address_frag)); | |
1104 | symbol_table_insert (symbol_new ("$gp", reg_section, GP, | |
1105 | &zero_address_frag)); | |
1106 | symbol_table_insert (symbol_new ("$at", reg_section, AT, | |
1107 | &zero_address_frag)); | |
1108 | symbol_table_insert (symbol_new ("$kt0", reg_section, KT0, | |
1109 | &zero_address_frag)); | |
1110 | symbol_table_insert (symbol_new ("$kt1", reg_section, KT1, | |
1111 | &zero_address_frag)); | |
1112 | symbol_table_insert (symbol_new ("$pc", reg_section, -1, | |
1113 | &zero_address_frag)); | |
1114 | ||
1115 | mips_no_prev_insn (false); | |
1116 | ||
1117 | mips_gprmask = 0; | |
1118 | mips_cprmask[0] = 0; | |
1119 | mips_cprmask[1] = 0; | |
1120 | mips_cprmask[2] = 0; | |
1121 | mips_cprmask[3] = 0; | |
1122 | ||
1123 | /* set the default alignment for the text section (2**2) */ | |
1124 | record_alignment (text_section, 2); | |
1125 | ||
1126 | if (USE_GLOBAL_POINTER_OPT) | |
1127 | bfd_set_gp_size (stdoutput, g_switch_value); | |
1128 | ||
1129 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1130 | { | |
1131 | /* On a native system, sections must be aligned to 16 byte | |
1132 | boundaries. When configured for an embedded ELF target, we | |
1133 | don't bother. */ | |
1134 | if (strcmp (TARGET_OS, "elf") != 0) | |
1135 | { | |
1136 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); | |
1137 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
1138 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
1139 | } | |
1140 | ||
1141 | /* Create a .reginfo section for register masks and a .mdebug | |
1142 | section for debugging information. */ | |
1143 | { | |
1144 | segT seg; | |
1145 | subsegT subseg; | |
1146 | flagword flags; | |
1147 | segT sec; | |
1148 | ||
1149 | seg = now_seg; | |
1150 | subseg = now_subseg; | |
1151 | ||
1152 | /* The ABI says this section should be loaded so that the | |
1153 | running program can access it. However, we don't load it | |
1154 | if we are configured for an embedded target */ | |
1155 | flags = SEC_READONLY | SEC_DATA; | |
1156 | if (strcmp (TARGET_OS, "elf") != 0) | |
1157 | flags |= SEC_ALLOC | SEC_LOAD; | |
1158 | ||
1159 | if (! mips_64) | |
1160 | { | |
1161 | sec = subseg_new (".reginfo", (subsegT) 0); | |
1162 | ||
1163 | ||
1164 | (void) bfd_set_section_flags (stdoutput, sec, flags); | |
1165 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1166 | ||
1167 | #ifdef OBJ_ELF | |
1168 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); | |
1169 | #endif | |
1170 | } | |
1171 | else | |
1172 | { | |
1173 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
1174 | .reginfo section. */ | |
1175 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
1176 | (void) bfd_set_section_flags (stdoutput, sec, flags); | |
1177 | (void) bfd_set_section_alignment (stdoutput, sec, 3); | |
1178 | ||
1179 | #ifdef OBJ_ELF | |
1180 | /* Set up the option header. */ | |
1181 | { | |
1182 | Elf_Internal_Options opthdr; | |
1183 | char *f; | |
1184 | ||
1185 | opthdr.kind = ODK_REGINFO; | |
1186 | opthdr.size = (sizeof (Elf_External_Options) | |
1187 | + sizeof (Elf64_External_RegInfo)); | |
1188 | opthdr.section = 0; | |
1189 | opthdr.info = 0; | |
1190 | f = frag_more (sizeof (Elf_External_Options)); | |
1191 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
1192 | (Elf_External_Options *) f); | |
1193 | ||
1194 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
1195 | } | |
1196 | #endif | |
1197 | } | |
1198 | ||
1199 | if (ECOFF_DEBUGGING) | |
1200 | { | |
1201 | sec = subseg_new (".mdebug", (subsegT) 0); | |
1202 | (void) bfd_set_section_flags (stdoutput, sec, | |
1203 | SEC_HAS_CONTENTS | SEC_READONLY); | |
1204 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
1205 | } | |
1206 | ||
1207 | #ifdef MIPS_STABS_ELF | |
1208 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
1209 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
1210 | SEC_READONLY | SEC_RELOC | SEC_DEBUGGING); | |
1211 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
1212 | #endif | |
1213 | ||
1214 | subseg_set (seg, subseg); | |
1215 | } | |
1216 | } | |
1217 | ||
1218 | if (! ECOFF_DEBUGGING) | |
1219 | md_obj_begin (); | |
1220 | } | |
1221 | ||
1222 | void | |
1223 | md_mips_end () | |
1224 | { | |
1225 | if (! ECOFF_DEBUGGING) | |
1226 | md_obj_end (); | |
1227 | } | |
1228 | ||
1229 | void | |
1230 | md_assemble (str) | |
1231 | char *str; | |
1232 | { | |
1233 | struct mips_cl_insn insn; | |
1234 | ||
1235 | imm_expr.X_op = O_absent; | |
1236 | imm_reloc = BFD_RELOC_UNUSED; | |
1237 | imm_unmatched_hi = false; | |
1238 | offset_expr.X_op = O_absent; | |
1239 | offset_reloc = BFD_RELOC_UNUSED; | |
1240 | ||
1241 | if (mips_opts.mips16) | |
1242 | mips16_ip (str, &insn); | |
1243 | else | |
1244 | { | |
1245 | mips_ip (str, &insn); | |
1246 | DBG((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), | |
1247 | str, insn.insn_opcode)); | |
1248 | } | |
1249 | ||
1250 | if (insn_error) | |
1251 | { | |
1252 | as_bad ("%s `%s'", insn_error, str); | |
1253 | return; | |
1254 | } | |
1255 | ||
1256 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
1257 | { | |
1258 | if (mips_opts.mips16) | |
1259 | mips16_macro (&insn); | |
1260 | else | |
1261 | macro (&insn); | |
1262 | } | |
1263 | else | |
1264 | { | |
1265 | if (imm_expr.X_op != O_absent) | |
1266 | append_insn ((char *) NULL, &insn, &imm_expr, imm_reloc, | |
1267 | imm_unmatched_hi); | |
1268 | else if (offset_expr.X_op != O_absent) | |
1269 | append_insn ((char *) NULL, &insn, &offset_expr, offset_reloc, false); | |
1270 | else | |
1271 | append_insn ((char *) NULL, &insn, NULL, BFD_RELOC_UNUSED, false); | |
1272 | } | |
1273 | } | |
1274 | ||
1275 | /* See whether instruction IP reads register REG. CLASS is the type | |
1276 | of register. */ | |
1277 | ||
1278 | static int | |
1279 | insn_uses_reg (ip, reg, class) | |
1280 | struct mips_cl_insn *ip; | |
1281 | unsigned int reg; | |
1282 | enum mips_regclass class; | |
1283 | { | |
1284 | if (class == MIPS16_REG) | |
1285 | { | |
1286 | assert (mips_opts.mips16); | |
1287 | reg = mips16_to_32_reg_map[reg]; | |
1288 | class = MIPS_GR_REG; | |
1289 | } | |
1290 | ||
1291 | /* Don't report on general register 0, since it never changes. */ | |
1292 | if (class == MIPS_GR_REG && reg == 0) | |
1293 | return 0; | |
1294 | ||
1295 | if (class == MIPS_FP_REG) | |
1296 | { | |
1297 | assert (! mips_opts.mips16); | |
1298 | /* If we are called with either $f0 or $f1, we must check $f0. | |
1299 | This is not optimal, because it will introduce an unnecessary | |
1300 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would | |
1301 | need to distinguish reading both $f0 and $f1 or just one of | |
1302 | them. Note that we don't have to check the other way, | |
1303 | because there is no instruction that sets both $f0 and $f1 | |
1304 | and requires a delay. */ | |
1305 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) | |
1306 | && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1) | |
1307 | == (reg &~ (unsigned) 1))) | |
1308 | return 1; | |
1309 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) | |
1310 | && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1) | |
1311 | == (reg &~ (unsigned) 1))) | |
1312 | return 1; | |
1313 | } | |
1314 | else if (! mips_opts.mips16) | |
1315 | { | |
1316 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) | |
1317 | && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg) | |
1318 | return 1; | |
1319 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) | |
1320 | && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg) | |
1321 | return 1; | |
1322 | } | |
1323 | else | |
1324 | { | |
1325 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) | |
1326 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX) | |
1327 | & MIPS16OP_MASK_RX)] | |
1328 | == reg)) | |
1329 | return 1; | |
1330 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) | |
1331 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY) | |
1332 | & MIPS16OP_MASK_RY)] | |
1333 | == reg)) | |
1334 | return 1; | |
1335 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) | |
1336 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1337 | & MIPS16OP_MASK_MOVE32Z)] | |
1338 | == reg)) | |
1339 | return 1; | |
1340 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) | |
1341 | return 1; | |
1342 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) | |
1343 | return 1; | |
1344 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) | |
1345 | return 1; | |
1346 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) | |
1347 | && ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1348 | & MIPS16OP_MASK_REGR32) == reg) | |
1349 | return 1; | |
1350 | } | |
1351 | ||
1352 | return 0; | |
1353 | } | |
1354 | ||
1355 | /* This function returns true if modifying a register requires a | |
1356 | delay. */ | |
1357 | ||
1358 | static int | |
1359 | reg_needs_delay (reg) | |
1360 | int reg; | |
1361 | { | |
1362 | unsigned long prev_pinfo; | |
1363 | ||
1364 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1365 | if (! mips_opts.noreorder | |
9ce8a5dd | 1366 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1367 | && ((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
1368 | || (! gpr_interlocks | |
1369 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
1370 | { | |
1371 | /* A load from a coprocessor or from memory. All load | |
1372 | delays delay the use of general register rt for one | |
1373 | instruction on the r3000. The r6000 and r4000 use | |
1374 | interlocks. */ | |
1375 | /* Itbl support may require additional care here. */ | |
1376 | know (prev_pinfo & INSN_WRITE_GPR_T); | |
1377 | if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)) | |
1378 | return 1; | |
1379 | } | |
1380 | ||
1381 | return 0; | |
1382 | } | |
1383 | ||
1384 | /* Mark instruction labels in mips16 mode. This permits the linker to | |
1385 | handle them specially, such as generating jalx instructions when | |
1386 | needed. We also make them odd for the duration of the assembly, in | |
1387 | order to generate the right sort of code. We will make them even | |
1388 | in the adjust_symtab routine, while leaving them marked. This is | |
1389 | convenient for the debugger and the disassembler. The linker knows | |
1390 | to make them odd again. */ | |
1391 | ||
1392 | static void | |
1393 | mips16_mark_labels () | |
1394 | { | |
1395 | if (mips_opts.mips16) | |
1396 | { | |
1397 | struct insn_label_list *l; | |
1398 | ||
1399 | for (l = insn_labels; l != NULL; l = l->next) | |
1400 | { | |
1401 | #ifdef OBJ_ELF | |
1402 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
1403 | S_SET_OTHER (l->label, STO_MIPS16); | |
1404 | #endif | |
49309057 ILT |
1405 | if ((S_GET_VALUE (l->label) & 1) == 0) |
1406 | S_SET_VALUE (l->label, S_GET_VALUE (l->label) + 1); | |
252b5132 RH |
1407 | } |
1408 | } | |
1409 | } | |
1410 | ||
1411 | /* Output an instruction. PLACE is where to put the instruction; if | |
1412 | it is NULL, this uses frag_more to get room. IP is the instruction | |
1413 | information. ADDRESS_EXPR is an operand of the instruction to be | |
1414 | used with RELOC_TYPE. */ | |
1415 | ||
1416 | static void | |
1417 | append_insn (place, ip, address_expr, reloc_type, unmatched_hi) | |
1418 | char *place; | |
1419 | struct mips_cl_insn *ip; | |
1420 | expressionS *address_expr; | |
1421 | bfd_reloc_code_real_type reloc_type; | |
1422 | boolean unmatched_hi; | |
1423 | { | |
1424 | register unsigned long prev_pinfo, pinfo; | |
1425 | char *f; | |
1426 | fixS *fixp; | |
1427 | int nops = 0; | |
1428 | ||
1429 | /* Mark instruction labels in mips16 mode. */ | |
1430 | if (mips_opts.mips16) | |
1431 | mips16_mark_labels (); | |
1432 | ||
1433 | prev_pinfo = prev_insn.insn_mo->pinfo; | |
1434 | pinfo = ip->insn_mo->pinfo; | |
1435 | ||
1436 | if (place == NULL && (! mips_opts.noreorder || prev_nop_frag != NULL)) | |
1437 | { | |
1438 | int prev_prev_nop; | |
1439 | ||
1440 | /* If the previous insn required any delay slots, see if we need | |
1441 | to insert a NOP or two. There are eight kinds of possible | |
1442 | hazards, of which an instruction can have at most one type. | |
1443 | (1) a load from memory delay | |
1444 | (2) a load from a coprocessor delay | |
1445 | (3) an unconditional branch delay | |
1446 | (4) a conditional branch delay | |
1447 | (5) a move to coprocessor register delay | |
1448 | (6) a load coprocessor register from memory delay | |
1449 | (7) a coprocessor condition code delay | |
1450 | (8) a HI/LO special register delay | |
1451 | ||
1452 | There are a lot of optimizations we could do that we don't. | |
1453 | In particular, we do not, in general, reorder instructions. | |
1454 | If you use gcc with optimization, it will reorder | |
1455 | instructions and generally do much more optimization then we | |
1456 | do here; repeating all that work in the assembler would only | |
1457 | benefit hand written assembly code, and does not seem worth | |
1458 | it. */ | |
1459 | ||
1460 | /* This is how a NOP is emitted. */ | |
1461 | #define emit_nop() \ | |
1462 | (mips_opts.mips16 \ | |
1463 | ? md_number_to_chars (frag_more (2), 0x6500, 2) \ | |
1464 | : md_number_to_chars (frag_more (4), 0, 4)) | |
1465 | ||
1466 | /* The previous insn might require a delay slot, depending upon | |
1467 | the contents of the current insn. */ | |
1468 | if (! mips_opts.mips16 | |
9ce8a5dd | 1469 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1470 | && (((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
1471 | && ! cop_interlocks) | |
1472 | || (! gpr_interlocks | |
1473 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) | |
1474 | { | |
1475 | /* A load from a coprocessor or from memory. All load | |
1476 | delays delay the use of general register rt for one | |
1477 | instruction on the r3000. The r6000 and r4000 use | |
1478 | interlocks. */ | |
1479 | /* Itbl support may require additional care here. */ | |
1480 | know (prev_pinfo & INSN_WRITE_GPR_T); | |
1481 | if (mips_optimize == 0 | |
1482 | || insn_uses_reg (ip, | |
1483 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
1484 | & OP_MASK_RT), | |
1485 | MIPS_GR_REG)) | |
1486 | ++nops; | |
1487 | } | |
1488 | else if (! mips_opts.mips16 | |
9ce8a5dd | 1489 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1490 | && (((prev_pinfo & INSN_COPROC_MOVE_DELAY) |
1491 | && ! cop_interlocks) | |
9ce8a5dd | 1492 | || (mips_opts.isa == 1 |
252b5132 RH |
1493 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)))) |
1494 | { | |
1495 | /* A generic coprocessor delay. The previous instruction | |
1496 | modified a coprocessor general or control register. If | |
1497 | it modified a control register, we need to avoid any | |
1498 | coprocessor instruction (this is probably not always | |
1499 | required, but it sometimes is). If it modified a general | |
1500 | register, we avoid using that register. | |
1501 | ||
1502 | On the r6000 and r4000 loading a coprocessor register | |
1503 | from memory is interlocked, and does not require a delay. | |
1504 | ||
1505 | This case is not handled very well. There is no special | |
1506 | knowledge of CP0 handling, and the coprocessors other | |
1507 | than the floating point unit are not distinguished at | |
1508 | all. */ | |
1509 | /* Itbl support may require additional care here. FIXME! | |
1510 | Need to modify this to include knowledge about | |
1511 | user specified delays! */ | |
1512 | if (prev_pinfo & INSN_WRITE_FPR_T) | |
1513 | { | |
1514 | if (mips_optimize == 0 | |
1515 | || insn_uses_reg (ip, | |
1516 | ((prev_insn.insn_opcode >> OP_SH_FT) | |
1517 | & OP_MASK_FT), | |
1518 | MIPS_FP_REG)) | |
1519 | ++nops; | |
1520 | } | |
1521 | else if (prev_pinfo & INSN_WRITE_FPR_S) | |
1522 | { | |
1523 | if (mips_optimize == 0 | |
1524 | || insn_uses_reg (ip, | |
1525 | ((prev_insn.insn_opcode >> OP_SH_FS) | |
1526 | & OP_MASK_FS), | |
1527 | MIPS_FP_REG)) | |
1528 | ++nops; | |
1529 | } | |
1530 | else | |
1531 | { | |
1532 | /* We don't know exactly what the previous instruction | |
1533 | does. If the current instruction uses a coprocessor | |
1534 | register, we must insert a NOP. If previous | |
1535 | instruction may set the condition codes, and the | |
1536 | current instruction uses them, we must insert two | |
1537 | NOPS. */ | |
1538 | /* Itbl support may require additional care here. */ | |
1539 | if (mips_optimize == 0 | |
1540 | || ((prev_pinfo & INSN_WRITE_COND_CODE) | |
1541 | && (pinfo & INSN_READ_COND_CODE))) | |
1542 | nops += 2; | |
1543 | else if (pinfo & INSN_COP) | |
1544 | ++nops; | |
1545 | } | |
1546 | } | |
1547 | else if (! mips_opts.mips16 | |
9ce8a5dd | 1548 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1549 | && (prev_pinfo & INSN_WRITE_COND_CODE) |
1550 | && ! cop_interlocks) | |
1551 | { | |
1552 | /* The previous instruction sets the coprocessor condition | |
1553 | codes, but does not require a general coprocessor delay | |
1554 | (this means it is a floating point comparison | |
1555 | instruction). If this instruction uses the condition | |
1556 | codes, we need to insert a single NOP. */ | |
1557 | /* Itbl support may require additional care here. */ | |
1558 | if (mips_optimize == 0 | |
1559 | || (pinfo & INSN_READ_COND_CODE)) | |
1560 | ++nops; | |
1561 | } | |
6b76fefe CM |
1562 | |
1563 | /* If we're fixing up mfhi/mflo for the r7000 and the | |
1564 | previous insn was an mfhi/mflo and the current insn | |
1565 | reads the register that the mfhi/mflo wrote to, then | |
1566 | insert two nops. */ | |
1567 | ||
1568 | else if (mips_7000_hilo_fix | |
1569 | && MF_HILO_INSN (prev_pinfo) | |
1570 | && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD) | |
1571 | & OP_MASK_RD), | |
1572 | MIPS_GR_REG)) | |
1573 | ||
1574 | { | |
1575 | nops += 2; | |
1576 | } | |
1577 | ||
1578 | /* If we're fixing up mfhi/mflo for the r7000 and the | |
1579 | 2nd previous insn was an mfhi/mflo and the current insn | |
1580 | reads the register that the mfhi/mflo wrote to, then | |
1581 | insert one nop. */ | |
1582 | ||
1583 | else if (mips_7000_hilo_fix | |
1584 | && MF_HILO_INSN (prev_prev_insn.insn_opcode) | |
1585 | && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD) | |
1586 | & OP_MASK_RD), | |
1587 | MIPS_GR_REG)) | |
1588 | ||
1589 | { | |
1590 | nops += 1; | |
1591 | } | |
1592 | ||
252b5132 RH |
1593 | else if (prev_pinfo & INSN_READ_LO) |
1594 | { | |
1595 | /* The previous instruction reads the LO register; if the | |
1596 | current instruction writes to the LO register, we must | |
1597 | insert two NOPS. Some newer processors have interlocks. | |
1598 | Also the tx39's multiply instructions can be exectuted | |
1599 | immediatly after a read from HI/LO (without the delay), | |
1600 | though the tx39's divide insns still do require the | |
1601 | delay. */ | |
1602 | if (! (hilo_interlocks | |
1603 | || (mips_cpu == 3900 && (pinfo & INSN_MULT))) | |
1604 | && (mips_optimize == 0 | |
1605 | || (pinfo & INSN_WRITE_LO))) | |
1606 | nops += 2; | |
1607 | /* Most mips16 branch insns don't have a delay slot. | |
1608 | If a read from LO is immediately followed by a branch | |
1609 | to a write to LO we have a read followed by a write | |
1610 | less than 2 insns away. We assume the target of | |
1611 | a branch might be a write to LO, and insert a nop | |
1612 | between a read and an immediately following branch. */ | |
1613 | else if (mips_opts.mips16 | |
1614 | && (mips_optimize == 0 | |
1615 | || (pinfo & MIPS16_INSN_BRANCH))) | |
1616 | nops += 1; | |
1617 | } | |
1618 | else if (prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1619 | { | |
1620 | /* The previous instruction reads the HI register; if the | |
1621 | current instruction writes to the HI register, we must | |
1622 | insert a NOP. Some newer processors have interlocks. | |
1623 | Also the note tx39's multiply above. */ | |
1624 | if (! (hilo_interlocks | |
1625 | || (mips_cpu == 3900 && (pinfo & INSN_MULT))) | |
1626 | && (mips_optimize == 0 | |
1627 | || (pinfo & INSN_WRITE_HI))) | |
1628 | nops += 2; | |
1629 | /* Most mips16 branch insns don't have a delay slot. | |
1630 | If a read from HI is immediately followed by a branch | |
1631 | to a write to HI we have a read followed by a write | |
1632 | less than 2 insns away. We assume the target of | |
1633 | a branch might be a write to HI, and insert a nop | |
1634 | between a read and an immediately following branch. */ | |
1635 | else if (mips_opts.mips16 | |
1636 | && (mips_optimize == 0 | |
1637 | || (pinfo & MIPS16_INSN_BRANCH))) | |
1638 | nops += 1; | |
1639 | } | |
1640 | ||
1641 | /* If the previous instruction was in a noreorder section, then | |
1642 | we don't want to insert the nop after all. */ | |
1643 | /* Itbl support may require additional care here. */ | |
1644 | if (prev_insn_unreordered) | |
1645 | nops = 0; | |
1646 | ||
1647 | /* There are two cases which require two intervening | |
1648 | instructions: 1) setting the condition codes using a move to | |
1649 | coprocessor instruction which requires a general coprocessor | |
1650 | delay and then reading the condition codes 2) reading the HI | |
1651 | or LO register and then writing to it (except on processors | |
1652 | which have interlocks). If we are not already emitting a NOP | |
1653 | instruction, we must check for these cases compared to the | |
1654 | instruction previous to the previous instruction. */ | |
1655 | if ((! mips_opts.mips16 | |
9ce8a5dd | 1656 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
1657 | && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) |
1658 | && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) | |
1659 | && (pinfo & INSN_READ_COND_CODE) | |
1660 | && ! cop_interlocks) | |
1661 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO) | |
1662 | && (pinfo & INSN_WRITE_LO) | |
1663 | && ! (hilo_interlocks | |
1664 | || (mips_cpu == 3900 && (pinfo & INSN_MULT)))) | |
1665 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
1666 | && (pinfo & INSN_WRITE_HI) | |
1667 | && ! (hilo_interlocks | |
1668 | || (mips_cpu == 3900 && (pinfo & INSN_MULT))))) | |
1669 | prev_prev_nop = 1; | |
1670 | else | |
1671 | prev_prev_nop = 0; | |
1672 | ||
1673 | if (prev_prev_insn_unreordered) | |
1674 | prev_prev_nop = 0; | |
1675 | ||
1676 | if (prev_prev_nop && nops == 0) | |
1677 | ++nops; | |
1678 | ||
1679 | /* If we are being given a nop instruction, don't bother with | |
1680 | one of the nops we would otherwise output. This will only | |
1681 | happen when a nop instruction is used with mips_optimize set | |
1682 | to 0. */ | |
1683 | if (nops > 0 | |
1684 | && ! mips_opts.noreorder | |
1685 | && ip->insn_opcode == (mips_opts.mips16 ? 0x6500 : 0)) | |
1686 | --nops; | |
1687 | ||
1688 | /* Now emit the right number of NOP instructions. */ | |
1689 | if (nops > 0 && ! mips_opts.noreorder) | |
1690 | { | |
1691 | fragS *old_frag; | |
1692 | unsigned long old_frag_offset; | |
1693 | int i; | |
1694 | struct insn_label_list *l; | |
1695 | ||
1696 | old_frag = frag_now; | |
1697 | old_frag_offset = frag_now_fix (); | |
1698 | ||
1699 | for (i = 0; i < nops; i++) | |
1700 | emit_nop (); | |
1701 | ||
1702 | if (listing) | |
1703 | { | |
1704 | listing_prev_line (); | |
1705 | /* We may be at the start of a variant frag. In case we | |
1706 | are, make sure there is enough space for the frag | |
1707 | after the frags created by listing_prev_line. The | |
1708 | argument to frag_grow here must be at least as large | |
1709 | as the argument to all other calls to frag_grow in | |
1710 | this file. We don't have to worry about being in the | |
1711 | middle of a variant frag, because the variants insert | |
1712 | all needed nop instructions themselves. */ | |
1713 | frag_grow (40); | |
1714 | } | |
1715 | ||
1716 | for (l = insn_labels; l != NULL; l = l->next) | |
1717 | { | |
1718 | assert (S_GET_SEGMENT (l->label) == now_seg); | |
49309057 | 1719 | symbol_set_frag (l->label, frag_now); |
252b5132 RH |
1720 | S_SET_VALUE (l->label, (valueT) frag_now_fix ()); |
1721 | /* mips16 text labels are stored as odd. */ | |
1722 | if (mips_opts.mips16) | |
49309057 | 1723 | S_SET_VALUE (l->label, S_GET_VALUE (l->label) + 1); |
252b5132 RH |
1724 | } |
1725 | ||
1726 | #ifndef NO_ECOFF_DEBUGGING | |
1727 | if (ECOFF_DEBUGGING) | |
1728 | ecoff_fix_loc (old_frag, old_frag_offset); | |
1729 | #endif | |
1730 | } | |
1731 | else if (prev_nop_frag != NULL) | |
1732 | { | |
1733 | /* We have a frag holding nops we may be able to remove. If | |
1734 | we don't need any nops, we can decrease the size of | |
1735 | prev_nop_frag by the size of one instruction. If we do | |
1736 | need some nops, we count them in prev_nops_required. */ | |
1737 | if (prev_nop_frag_since == 0) | |
1738 | { | |
1739 | if (nops == 0) | |
1740 | { | |
1741 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
1742 | --prev_nop_frag_holds; | |
1743 | } | |
1744 | else | |
1745 | prev_nop_frag_required += nops; | |
1746 | } | |
1747 | else | |
1748 | { | |
1749 | if (prev_prev_nop == 0) | |
1750 | { | |
1751 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; | |
1752 | --prev_nop_frag_holds; | |
1753 | } | |
1754 | else | |
1755 | ++prev_nop_frag_required; | |
1756 | } | |
1757 | ||
1758 | if (prev_nop_frag_holds <= prev_nop_frag_required) | |
1759 | prev_nop_frag = NULL; | |
1760 | ||
1761 | ++prev_nop_frag_since; | |
1762 | ||
1763 | /* Sanity check: by the time we reach the second instruction | |
1764 | after prev_nop_frag, we should have used up all the nops | |
1765 | one way or another. */ | |
1766 | assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL); | |
1767 | } | |
1768 | } | |
1769 | ||
1770 | if (reloc_type > BFD_RELOC_UNUSED) | |
1771 | { | |
1772 | /* We need to set up a variant frag. */ | |
1773 | assert (mips_opts.mips16 && address_expr != NULL); | |
1774 | f = frag_var (rs_machine_dependent, 4, 0, | |
1775 | RELAX_MIPS16_ENCODE (reloc_type - BFD_RELOC_UNUSED, | |
1776 | mips16_small, mips16_ext, | |
1777 | (prev_pinfo | |
1778 | & INSN_UNCOND_BRANCH_DELAY), | |
1779 | (prev_insn_reloc_type | |
1780 | == BFD_RELOC_MIPS16_JMP)), | |
1781 | make_expr_symbol (address_expr), (offsetT) 0, | |
1782 | (char *) NULL); | |
1783 | } | |
1784 | else if (place != NULL) | |
1785 | f = place; | |
1786 | else if (mips_opts.mips16 | |
1787 | && ! ip->use_extend | |
1788 | && reloc_type != BFD_RELOC_MIPS16_JMP) | |
1789 | { | |
1790 | /* Make sure there is enough room to swap this instruction with | |
1791 | a following jump instruction. */ | |
1792 | frag_grow (6); | |
1793 | f = frag_more (2); | |
1794 | } | |
1795 | else | |
1796 | { | |
1797 | if (mips_opts.mips16 | |
1798 | && mips_opts.noreorder | |
1799 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
1800 | as_warn (_("extended instruction in delay slot")); | |
1801 | ||
1802 | f = frag_more (4); | |
1803 | } | |
1804 | ||
1805 | fixp = NULL; | |
1806 | if (address_expr != NULL && reloc_type < BFD_RELOC_UNUSED) | |
1807 | { | |
1808 | if (address_expr->X_op == O_constant) | |
1809 | { | |
1810 | switch (reloc_type) | |
1811 | { | |
1812 | case BFD_RELOC_32: | |
1813 | ip->insn_opcode |= address_expr->X_add_number; | |
1814 | break; | |
1815 | ||
1816 | case BFD_RELOC_LO16: | |
1817 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; | |
1818 | break; | |
1819 | ||
1820 | case BFD_RELOC_MIPS_JMP: | |
1821 | if ((address_expr->X_add_number & 3) != 0) | |
1822 | as_bad (_("jump to misaligned address (0x%lx)"), | |
1823 | (unsigned long) address_expr->X_add_number); | |
1824 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; | |
1825 | break; | |
1826 | ||
1827 | case BFD_RELOC_MIPS16_JMP: | |
1828 | if ((address_expr->X_add_number & 3) != 0) | |
1829 | as_bad (_("jump to misaligned address (0x%lx)"), | |
1830 | (unsigned long) address_expr->X_add_number); | |
1831 | ip->insn_opcode |= | |
1832 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
1833 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
1834 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
1835 | break; | |
1836 | ||
1837 | ||
1838 | case BFD_RELOC_16_PCREL_S2: | |
1839 | goto need_reloc; | |
1840 | ||
1841 | default: | |
1842 | internalError (); | |
1843 | } | |
1844 | } | |
1845 | else | |
1846 | { | |
1847 | need_reloc: | |
1848 | /* Don't generate a reloc if we are writing into a variant | |
1849 | frag. */ | |
1850 | if (place == NULL) | |
1851 | { | |
1852 | fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 4, | |
1853 | address_expr, | |
1854 | reloc_type == BFD_RELOC_16_PCREL_S2, | |
1855 | reloc_type); | |
1856 | if (unmatched_hi) | |
1857 | { | |
1858 | struct mips_hi_fixup *hi_fixup; | |
1859 | ||
1860 | assert (reloc_type == BFD_RELOC_HI16_S); | |
1861 | hi_fixup = ((struct mips_hi_fixup *) | |
1862 | xmalloc (sizeof (struct mips_hi_fixup))); | |
1863 | hi_fixup->fixp = fixp; | |
1864 | hi_fixup->seg = now_seg; | |
1865 | hi_fixup->next = mips_hi_fixup_list; | |
1866 | mips_hi_fixup_list = hi_fixup; | |
1867 | } | |
1868 | } | |
1869 | } | |
1870 | } | |
1871 | ||
1872 | if (! mips_opts.mips16) | |
1873 | md_number_to_chars (f, ip->insn_opcode, 4); | |
1874 | else if (reloc_type == BFD_RELOC_MIPS16_JMP) | |
1875 | { | |
1876 | md_number_to_chars (f, ip->insn_opcode >> 16, 2); | |
1877 | md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2); | |
1878 | } | |
1879 | else | |
1880 | { | |
1881 | if (ip->use_extend) | |
1882 | { | |
1883 | md_number_to_chars (f, 0xf000 | ip->extend, 2); | |
1884 | f += 2; | |
1885 | } | |
1886 | md_number_to_chars (f, ip->insn_opcode, 2); | |
1887 | } | |
1888 | ||
1889 | /* Update the register mask information. */ | |
1890 | if (! mips_opts.mips16) | |
1891 | { | |
1892 | if (pinfo & INSN_WRITE_GPR_D) | |
1893 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD); | |
1894 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) | |
1895 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT); | |
1896 | if (pinfo & INSN_READ_GPR_S) | |
1897 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS); | |
1898 | if (pinfo & INSN_WRITE_GPR_31) | |
1899 | mips_gprmask |= 1 << 31; | |
1900 | if (pinfo & INSN_WRITE_FPR_D) | |
1901 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD); | |
1902 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) | |
1903 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS); | |
1904 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) | |
1905 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT); | |
1906 | if ((pinfo & INSN_READ_FPR_R) != 0) | |
1907 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR); | |
1908 | if (pinfo & INSN_COP) | |
1909 | { | |
1910 | /* We don't keep enough information to sort these cases out. | |
1911 | The itbl support does keep this information however, although | |
1912 | we currently don't support itbl fprmats as part of the cop | |
1913 | instruction. May want to add this support in the future. */ | |
1914 | } | |
1915 | /* Never set the bit for $0, which is always zero. */ | |
1916 | mips_gprmask &=~ 1 << 0; | |
1917 | } | |
1918 | else | |
1919 | { | |
1920 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) | |
1921 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX) | |
1922 | & MIPS16OP_MASK_RX); | |
1923 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) | |
1924 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY) | |
1925 | & MIPS16OP_MASK_RY); | |
1926 | if (pinfo & MIPS16_INSN_WRITE_Z) | |
1927 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ) | |
1928 | & MIPS16OP_MASK_RZ); | |
1929 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) | |
1930 | mips_gprmask |= 1 << TREG; | |
1931 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) | |
1932 | mips_gprmask |= 1 << SP; | |
1933 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) | |
1934 | mips_gprmask |= 1 << RA; | |
1935 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
1936 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); | |
1937 | if (pinfo & MIPS16_INSN_READ_Z) | |
1938 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) | |
1939 | & MIPS16OP_MASK_MOVE32Z); | |
1940 | if (pinfo & MIPS16_INSN_READ_GPR_X) | |
1941 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32) | |
1942 | & MIPS16OP_MASK_REGR32); | |
1943 | } | |
1944 | ||
1945 | if (place == NULL && ! mips_opts.noreorder) | |
1946 | { | |
1947 | /* Filling the branch delay slot is more complex. We try to | |
1948 | switch the branch with the previous instruction, which we can | |
1949 | do if the previous instruction does not set up a condition | |
1950 | that the branch tests and if the branch is not itself the | |
1951 | target of any branch. */ | |
1952 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) | |
1953 | || (pinfo & INSN_COND_BRANCH_DELAY)) | |
1954 | { | |
1955 | if (mips_optimize < 2 | |
1956 | /* If we have seen .set volatile or .set nomove, don't | |
1957 | optimize. */ | |
1958 | || mips_opts.nomove != 0 | |
1959 | /* If we had to emit any NOP instructions, then we | |
1960 | already know we can not swap. */ | |
1961 | || nops != 0 | |
1962 | /* If we don't even know the previous insn, we can not | |
1963 | swap. */ | |
1964 | || ! prev_insn_valid | |
1965 | /* If the previous insn is already in a branch delay | |
1966 | slot, then we can not swap. */ | |
1967 | || prev_insn_is_delay_slot | |
1968 | /* If the previous previous insn was in a .set | |
1969 | noreorder, we can't swap. Actually, the MIPS | |
1970 | assembler will swap in this situation. However, gcc | |
1971 | configured -with-gnu-as will generate code like | |
1972 | .set noreorder | |
1973 | lw $4,XXX | |
1974 | .set reorder | |
1975 | INSN | |
1976 | bne $4,$0,foo | |
1977 | in which we can not swap the bne and INSN. If gcc is | |
1978 | not configured -with-gnu-as, it does not output the | |
1979 | .set pseudo-ops. We don't have to check | |
1980 | prev_insn_unreordered, because prev_insn_valid will | |
1981 | be 0 in that case. We don't want to use | |
1982 | prev_prev_insn_valid, because we do want to be able | |
1983 | to swap at the start of a function. */ | |
1984 | || prev_prev_insn_unreordered | |
1985 | /* If the branch is itself the target of a branch, we | |
1986 | can not swap. We cheat on this; all we check for is | |
1987 | whether there is a label on this instruction. If | |
1988 | there are any branches to anything other than a | |
1989 | label, users must use .set noreorder. */ | |
1990 | || insn_labels != NULL | |
1991 | /* If the previous instruction is in a variant frag, we | |
1992 | can not do the swap. This does not apply to the | |
1993 | mips16, which uses variant frags for different | |
1994 | purposes. */ | |
1995 | || (! mips_opts.mips16 | |
1996 | && prev_insn_frag->fr_type == rs_machine_dependent) | |
1997 | /* If the branch reads the condition codes, we don't | |
1998 | even try to swap, because in the sequence | |
1999 | ctc1 $X,$31 | |
2000 | INSN | |
2001 | INSN | |
2002 | bc1t LABEL | |
2003 | we can not swap, and I don't feel like handling that | |
2004 | case. */ | |
2005 | || (! mips_opts.mips16 | |
9ce8a5dd | 2006 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2007 | && (pinfo & INSN_READ_COND_CODE)) |
2008 | /* We can not swap with an instruction that requires a | |
2009 | delay slot, becase the target of the branch might | |
2010 | interfere with that instruction. */ | |
2011 | || (! mips_opts.mips16 | |
9ce8a5dd | 2012 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2013 | && (prev_pinfo |
2014 | /* Itbl support may require additional care here. */ | |
2015 | & (INSN_LOAD_COPROC_DELAY | |
2016 | | INSN_COPROC_MOVE_DELAY | |
2017 | | INSN_WRITE_COND_CODE))) | |
2018 | || (! (hilo_interlocks | |
2019 | || (mips_cpu == 3900 && (pinfo & INSN_MULT))) | |
2020 | && (prev_pinfo | |
2021 | & (INSN_READ_LO | |
2022 | | INSN_READ_HI))) | |
2023 | || (! mips_opts.mips16 | |
2024 | && ! gpr_interlocks | |
2025 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)) | |
2026 | || (! mips_opts.mips16 | |
9ce8a5dd | 2027 | && mips_opts.isa == 1 |
252b5132 RH |
2028 | /* Itbl support may require additional care here. */ |
2029 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)) | |
2030 | /* We can not swap with a branch instruction. */ | |
2031 | || (prev_pinfo | |
2032 | & (INSN_UNCOND_BRANCH_DELAY | |
2033 | | INSN_COND_BRANCH_DELAY | |
2034 | | INSN_COND_BRANCH_LIKELY)) | |
2035 | /* We do not swap with a trap instruction, since it | |
2036 | complicates trap handlers to have the trap | |
2037 | instruction be in a delay slot. */ | |
2038 | || (prev_pinfo & INSN_TRAP) | |
2039 | /* If the branch reads a register that the previous | |
2040 | instruction sets, we can not swap. */ | |
2041 | || (! mips_opts.mips16 | |
2042 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2043 | && insn_uses_reg (ip, | |
2044 | ((prev_insn.insn_opcode >> OP_SH_RT) | |
2045 | & OP_MASK_RT), | |
2046 | MIPS_GR_REG)) | |
2047 | || (! mips_opts.mips16 | |
2048 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2049 | && insn_uses_reg (ip, | |
2050 | ((prev_insn.insn_opcode >> OP_SH_RD) | |
2051 | & OP_MASK_RD), | |
2052 | MIPS_GR_REG)) | |
2053 | || (mips_opts.mips16 | |
2054 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) | |
2055 | && insn_uses_reg (ip, | |
2056 | ((prev_insn.insn_opcode | |
2057 | >> MIPS16OP_SH_RX) | |
2058 | & MIPS16OP_MASK_RX), | |
2059 | MIPS16_REG)) | |
2060 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) | |
2061 | && insn_uses_reg (ip, | |
2062 | ((prev_insn.insn_opcode | |
2063 | >> MIPS16OP_SH_RY) | |
2064 | & MIPS16OP_MASK_RY), | |
2065 | MIPS16_REG)) | |
2066 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) | |
2067 | && insn_uses_reg (ip, | |
2068 | ((prev_insn.insn_opcode | |
2069 | >> MIPS16OP_SH_RZ) | |
2070 | & MIPS16OP_MASK_RZ), | |
2071 | MIPS16_REG)) | |
2072 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) | |
2073 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) | |
2074 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2075 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) | |
2076 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2077 | && insn_uses_reg (ip, | |
2078 | MIPS16OP_EXTRACT_REG32R (prev_insn. | |
2079 | insn_opcode), | |
2080 | MIPS_GR_REG)))) | |
2081 | /* If the branch writes a register that the previous | |
2082 | instruction sets, we can not swap (we know that | |
2083 | branches write only to RD or to $31). */ | |
2084 | || (! mips_opts.mips16 | |
2085 | && (prev_pinfo & INSN_WRITE_GPR_T) | |
2086 | && (((pinfo & INSN_WRITE_GPR_D) | |
2087 | && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT) | |
2088 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
2089 | || ((pinfo & INSN_WRITE_GPR_31) | |
2090 | && (((prev_insn.insn_opcode >> OP_SH_RT) | |
2091 | & OP_MASK_RT) | |
2092 | == 31)))) | |
2093 | || (! mips_opts.mips16 | |
2094 | && (prev_pinfo & INSN_WRITE_GPR_D) | |
2095 | && (((pinfo & INSN_WRITE_GPR_D) | |
2096 | && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD) | |
2097 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) | |
2098 | || ((pinfo & INSN_WRITE_GPR_31) | |
2099 | && (((prev_insn.insn_opcode >> OP_SH_RD) | |
2100 | & OP_MASK_RD) | |
2101 | == 31)))) | |
2102 | || (mips_opts.mips16 | |
2103 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2104 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) | |
2105 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) | |
2106 | && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode) | |
2107 | == RA)))) | |
2108 | /* If the branch writes a register that the previous | |
2109 | instruction reads, we can not swap (we know that | |
2110 | branches only write to RD or to $31). */ | |
2111 | || (! mips_opts.mips16 | |
2112 | && (pinfo & INSN_WRITE_GPR_D) | |
2113 | && insn_uses_reg (&prev_insn, | |
2114 | ((ip->insn_opcode >> OP_SH_RD) | |
2115 | & OP_MASK_RD), | |
2116 | MIPS_GR_REG)) | |
2117 | || (! mips_opts.mips16 | |
2118 | && (pinfo & INSN_WRITE_GPR_31) | |
2119 | && insn_uses_reg (&prev_insn, 31, MIPS_GR_REG)) | |
2120 | || (mips_opts.mips16 | |
2121 | && (pinfo & MIPS16_INSN_WRITE_31) | |
2122 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) | |
2123 | /* If we are generating embedded PIC code, the branch | |
2124 | might be expanded into a sequence which uses $at, so | |
2125 | we can't swap with an instruction which reads it. */ | |
2126 | || (mips_pic == EMBEDDED_PIC | |
2127 | && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG)) | |
2128 | /* If the previous previous instruction has a load | |
2129 | delay, and sets a register that the branch reads, we | |
2130 | can not swap. */ | |
2131 | || (! mips_opts.mips16 | |
9ce8a5dd | 2132 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2133 | /* Itbl support may require additional care here. */ |
2134 | && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) | |
2135 | || (! gpr_interlocks | |
2136 | && (prev_prev_insn.insn_mo->pinfo | |
2137 | & INSN_LOAD_MEMORY_DELAY))) | |
2138 | && insn_uses_reg (ip, | |
2139 | ((prev_prev_insn.insn_opcode >> OP_SH_RT) | |
2140 | & OP_MASK_RT), | |
2141 | MIPS_GR_REG)) | |
2142 | /* If one instruction sets a condition code and the | |
2143 | other one uses a condition code, we can not swap. */ | |
2144 | || ((pinfo & INSN_READ_COND_CODE) | |
2145 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
2146 | || ((pinfo & INSN_WRITE_COND_CODE) | |
2147 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
2148 | /* If the previous instruction uses the PC, we can not | |
2149 | swap. */ | |
2150 | || (mips_opts.mips16 | |
2151 | && (prev_pinfo & MIPS16_INSN_READ_PC)) | |
2152 | /* If the previous instruction was extended, we can not | |
2153 | swap. */ | |
2154 | || (mips_opts.mips16 && prev_insn_extended) | |
2155 | /* If the previous instruction had a fixup in mips16 | |
2156 | mode, we can not swap. This normally means that the | |
2157 | previous instruction was a 4 byte branch anyhow. */ | |
2158 | || (mips_opts.mips16 && prev_insn_fixp) | |
2159 | /* If the previous instruction is a sync, sync.l, or | |
2160 | sync.p, we can not swap. */ | |
f173e82e | 2161 | || (prev_pinfo & INSN_SYNC)) |
252b5132 RH |
2162 | { |
2163 | /* We could do even better for unconditional branches to | |
2164 | portions of this object file; we could pick up the | |
2165 | instruction at the destination, put it in the delay | |
2166 | slot, and bump the destination address. */ | |
2167 | emit_nop (); | |
2168 | /* Update the previous insn information. */ | |
2169 | prev_prev_insn = *ip; | |
2170 | prev_insn.insn_mo = &dummy_opcode; | |
2171 | } | |
2172 | else | |
2173 | { | |
2174 | /* It looks like we can actually do the swap. */ | |
2175 | if (! mips_opts.mips16) | |
2176 | { | |
2177 | char *prev_f; | |
2178 | char temp[4]; | |
2179 | ||
2180 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
2181 | memcpy (temp, prev_f, 4); | |
2182 | memcpy (prev_f, f, 4); | |
2183 | memcpy (f, temp, 4); | |
2184 | if (prev_insn_fixp) | |
2185 | { | |
2186 | prev_insn_fixp->fx_frag = frag_now; | |
2187 | prev_insn_fixp->fx_where = f - frag_now->fr_literal; | |
2188 | } | |
2189 | if (fixp) | |
2190 | { | |
2191 | fixp->fx_frag = prev_insn_frag; | |
2192 | fixp->fx_where = prev_insn_where; | |
2193 | } | |
2194 | } | |
2195 | else | |
2196 | { | |
2197 | char *prev_f; | |
2198 | char temp[2]; | |
2199 | ||
2200 | assert (prev_insn_fixp == NULL); | |
2201 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; | |
2202 | memcpy (temp, prev_f, 2); | |
2203 | memcpy (prev_f, f, 2); | |
2204 | if (reloc_type != BFD_RELOC_MIPS16_JMP) | |
2205 | { | |
2206 | assert (reloc_type == BFD_RELOC_UNUSED); | |
2207 | memcpy (f, temp, 2); | |
2208 | } | |
2209 | else | |
2210 | { | |
2211 | memcpy (f, f + 2, 2); | |
2212 | memcpy (f + 2, temp, 2); | |
2213 | } | |
2214 | if (fixp) | |
2215 | { | |
2216 | fixp->fx_frag = prev_insn_frag; | |
2217 | fixp->fx_where = prev_insn_where; | |
2218 | } | |
2219 | } | |
2220 | ||
2221 | /* Update the previous insn information; leave prev_insn | |
2222 | unchanged. */ | |
2223 | prev_prev_insn = *ip; | |
2224 | } | |
2225 | prev_insn_is_delay_slot = 1; | |
2226 | ||
2227 | /* If that was an unconditional branch, forget the previous | |
2228 | insn information. */ | |
2229 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) | |
2230 | { | |
2231 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2232 | prev_insn.insn_mo = &dummy_opcode; | |
2233 | } | |
2234 | ||
2235 | prev_insn_fixp = NULL; | |
2236 | prev_insn_reloc_type = BFD_RELOC_UNUSED; | |
2237 | prev_insn_extended = 0; | |
2238 | } | |
2239 | else if (pinfo & INSN_COND_BRANCH_LIKELY) | |
2240 | { | |
2241 | /* We don't yet optimize a branch likely. What we should do | |
2242 | is look at the target, copy the instruction found there | |
2243 | into the delay slot, and increment the branch to jump to | |
2244 | the next instruction. */ | |
2245 | emit_nop (); | |
2246 | /* Update the previous insn information. */ | |
2247 | prev_prev_insn = *ip; | |
2248 | prev_insn.insn_mo = &dummy_opcode; | |
2249 | prev_insn_fixp = NULL; | |
2250 | prev_insn_reloc_type = BFD_RELOC_UNUSED; | |
2251 | prev_insn_extended = 0; | |
2252 | } | |
2253 | else | |
2254 | { | |
2255 | /* Update the previous insn information. */ | |
2256 | if (nops > 0) | |
2257 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2258 | else | |
2259 | prev_prev_insn = prev_insn; | |
2260 | prev_insn = *ip; | |
2261 | ||
2262 | /* Any time we see a branch, we always fill the delay slot | |
2263 | immediately; since this insn is not a branch, we know it | |
2264 | is not in a delay slot. */ | |
2265 | prev_insn_is_delay_slot = 0; | |
2266 | ||
2267 | prev_insn_fixp = fixp; | |
2268 | prev_insn_reloc_type = reloc_type; | |
2269 | if (mips_opts.mips16) | |
2270 | prev_insn_extended = (ip->use_extend | |
2271 | || reloc_type > BFD_RELOC_UNUSED); | |
2272 | } | |
2273 | ||
2274 | prev_prev_insn_unreordered = prev_insn_unreordered; | |
2275 | prev_insn_unreordered = 0; | |
2276 | prev_insn_frag = frag_now; | |
2277 | prev_insn_where = f - frag_now->fr_literal; | |
2278 | prev_insn_valid = 1; | |
2279 | } | |
2280 | else if (place == NULL) | |
2281 | { | |
2282 | /* We need to record a bit of information even when we are not | |
2283 | reordering, in order to determine the base address for mips16 | |
2284 | PC relative relocs. */ | |
2285 | prev_prev_insn = prev_insn; | |
2286 | prev_insn = *ip; | |
2287 | prev_insn_reloc_type = reloc_type; | |
2288 | prev_prev_insn_unreordered = prev_insn_unreordered; | |
2289 | prev_insn_unreordered = 1; | |
2290 | } | |
2291 | ||
2292 | /* We just output an insn, so the next one doesn't have a label. */ | |
2293 | mips_clear_insn_labels (); | |
2294 | ||
2295 | /* We must ensure that a fixup associated with an unmatched %hi | |
2296 | reloc does not become a variant frag. Otherwise, the | |
2297 | rearrangement of %hi relocs in frob_file may confuse | |
2298 | tc_gen_reloc. */ | |
2299 | if (unmatched_hi) | |
2300 | { | |
2301 | frag_wane (frag_now); | |
2302 | frag_new (0); | |
2303 | } | |
2304 | } | |
2305 | ||
2306 | /* This function forgets that there was any previous instruction or | |
2307 | label. If PRESERVE is non-zero, it remembers enough information to | |
2308 | know whether nops are needed before a noreorder section. */ | |
2309 | ||
2310 | static void | |
2311 | mips_no_prev_insn (preserve) | |
2312 | int preserve; | |
2313 | { | |
2314 | if (! preserve) | |
2315 | { | |
2316 | prev_insn.insn_mo = &dummy_opcode; | |
2317 | prev_prev_insn.insn_mo = &dummy_opcode; | |
2318 | prev_nop_frag = NULL; | |
2319 | prev_nop_frag_holds = 0; | |
2320 | prev_nop_frag_required = 0; | |
2321 | prev_nop_frag_since = 0; | |
2322 | } | |
2323 | prev_insn_valid = 0; | |
2324 | prev_insn_is_delay_slot = 0; | |
2325 | prev_insn_unreordered = 0; | |
2326 | prev_insn_extended = 0; | |
2327 | prev_insn_reloc_type = BFD_RELOC_UNUSED; | |
2328 | prev_prev_insn_unreordered = 0; | |
2329 | mips_clear_insn_labels (); | |
2330 | } | |
2331 | ||
2332 | /* This function must be called whenever we turn on noreorder or emit | |
2333 | something other than instructions. It inserts any NOPS which might | |
2334 | be needed by the previous instruction, and clears the information | |
2335 | kept for the previous instructions. The INSNS parameter is true if | |
2336 | instructions are to follow. */ | |
2337 | ||
2338 | static void | |
2339 | mips_emit_delays (insns) | |
2340 | boolean insns; | |
2341 | { | |
2342 | if (! mips_opts.noreorder) | |
2343 | { | |
2344 | int nops; | |
2345 | ||
2346 | nops = 0; | |
2347 | if ((! mips_opts.mips16 | |
9ce8a5dd | 2348 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2349 | && (! cop_interlocks |
2350 | && (prev_insn.insn_mo->pinfo | |
2351 | & (INSN_LOAD_COPROC_DELAY | |
2352 | | INSN_COPROC_MOVE_DELAY | |
2353 | | INSN_WRITE_COND_CODE)))) | |
2354 | || (! hilo_interlocks | |
2355 | && (prev_insn.insn_mo->pinfo | |
2356 | & (INSN_READ_LO | |
2357 | | INSN_READ_HI))) | |
2358 | || (! mips_opts.mips16 | |
2359 | && ! gpr_interlocks | |
2360 | && (prev_insn.insn_mo->pinfo | |
2361 | & INSN_LOAD_MEMORY_DELAY)) | |
2362 | || (! mips_opts.mips16 | |
9ce8a5dd | 2363 | && mips_opts.isa == 1 |
252b5132 RH |
2364 | && (prev_insn.insn_mo->pinfo |
2365 | & INSN_COPROC_MEMORY_DELAY))) | |
2366 | { | |
2367 | /* Itbl support may require additional care here. */ | |
2368 | ++nops; | |
2369 | if ((! mips_opts.mips16 | |
9ce8a5dd | 2370 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2371 | && (! cop_interlocks |
2372 | && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
2373 | || (! hilo_interlocks | |
2374 | && ((prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
2375 | || (prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
2376 | ++nops; | |
2377 | ||
2378 | if (prev_insn_unreordered) | |
2379 | nops = 0; | |
2380 | } | |
2381 | else if ((! mips_opts.mips16 | |
9ce8a5dd | 2382 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
252b5132 RH |
2383 | && (! cop_interlocks |
2384 | && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) | |
2385 | || (! hilo_interlocks | |
2386 | && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) | |
2387 | || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)))) | |
2388 | { | |
2389 | /* Itbl support may require additional care here. */ | |
2390 | if (! prev_prev_insn_unreordered) | |
2391 | ++nops; | |
2392 | } | |
2393 | ||
2394 | if (nops > 0) | |
2395 | { | |
2396 | struct insn_label_list *l; | |
2397 | ||
2398 | if (insns) | |
2399 | { | |
2400 | /* Record the frag which holds the nop instructions, so | |
2401 | that we can remove them if we don't need them. */ | |
2402 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); | |
2403 | prev_nop_frag = frag_now; | |
2404 | prev_nop_frag_holds = nops; | |
2405 | prev_nop_frag_required = 0; | |
2406 | prev_nop_frag_since = 0; | |
2407 | } | |
2408 | ||
2409 | for (; nops > 0; --nops) | |
2410 | emit_nop (); | |
2411 | ||
2412 | if (insns) | |
2413 | { | |
2414 | /* Move on to a new frag, so that it is safe to simply | |
2415 | decrease the size of prev_nop_frag. */ | |
2416 | frag_wane (frag_now); | |
2417 | frag_new (0); | |
2418 | } | |
2419 | ||
2420 | for (l = insn_labels; l != NULL; l = l->next) | |
2421 | { | |
2422 | assert (S_GET_SEGMENT (l->label) == now_seg); | |
49309057 | 2423 | symbol_set_frag (l->label, frag_now); |
252b5132 RH |
2424 | S_SET_VALUE (l->label, (valueT) frag_now_fix ()); |
2425 | /* mips16 text labels are stored as odd. */ | |
2426 | if (mips_opts.mips16) | |
49309057 | 2427 | S_SET_VALUE (l->label, S_GET_VALUE (l->label) + 1); |
252b5132 RH |
2428 | } |
2429 | } | |
2430 | } | |
2431 | ||
2432 | /* Mark instruction labels in mips16 mode. */ | |
2433 | if (mips_opts.mips16 && insns) | |
2434 | mips16_mark_labels (); | |
2435 | ||
2436 | mips_no_prev_insn (insns); | |
2437 | } | |
2438 | ||
2439 | /* Build an instruction created by a macro expansion. This is passed | |
2440 | a pointer to the count of instructions created so far, an | |
2441 | expression, the name of the instruction to build, an operand format | |
2442 | string, and corresponding arguments. */ | |
2443 | ||
2444 | #ifdef USE_STDARG | |
2445 | static void | |
2446 | macro_build (char *place, | |
2447 | int *counter, | |
2448 | expressionS * ep, | |
2449 | const char *name, | |
2450 | const char *fmt, | |
2451 | ...) | |
2452 | #else | |
2453 | static void | |
2454 | macro_build (place, counter, ep, name, fmt, va_alist) | |
2455 | char *place; | |
2456 | int *counter; | |
2457 | expressionS *ep; | |
2458 | const char *name; | |
2459 | const char *fmt; | |
2460 | va_dcl | |
2461 | #endif | |
2462 | { | |
2463 | struct mips_cl_insn insn; | |
2464 | bfd_reloc_code_real_type r; | |
2465 | va_list args; | |
252b5132 RH |
2466 | |
2467 | #ifdef USE_STDARG | |
2468 | va_start (args, fmt); | |
2469 | #else | |
2470 | va_start (args); | |
2471 | #endif | |
2472 | ||
2473 | /* | |
2474 | * If the macro is about to expand into a second instruction, | |
2475 | * print a warning if needed. We need to pass ip as a parameter | |
2476 | * to generate a better warning message here... | |
2477 | */ | |
2478 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) | |
2479 | as_warn (_("Macro instruction expanded into multiple instructions")); | |
2480 | ||
2481 | if (place == NULL) | |
2482 | *counter += 1; /* bump instruction counter */ | |
2483 | ||
2484 | if (mips_opts.mips16) | |
2485 | { | |
2486 | mips16_macro_build (place, counter, ep, name, fmt, args); | |
2487 | va_end (args); | |
2488 | return; | |
2489 | } | |
2490 | ||
2491 | r = BFD_RELOC_UNUSED; | |
2492 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
2493 | assert (insn.insn_mo); | |
2494 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2495 | ||
2496 | /* Search until we get a match for NAME. */ | |
2497 | while (1) | |
2498 | { | |
252b5132 RH |
2499 | if (strcmp (fmt, insn.insn_mo->args) == 0 |
2500 | && insn.insn_mo->pinfo != INSN_MACRO | |
2bd7f1f3 | 2501 | && OPCODE_IS_MEMBER (insn.insn_mo, mips_opts.isa, mips_cpu) |
252b5132 RH |
2502 | && (mips_cpu != 4650 || (insn.insn_mo->pinfo & FP_D) == 0)) |
2503 | break; | |
2504 | ||
2505 | ++insn.insn_mo; | |
2506 | assert (insn.insn_mo->name); | |
2507 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2508 | } | |
2509 | ||
2510 | insn.insn_opcode = insn.insn_mo->match; | |
2511 | for (;;) | |
2512 | { | |
2513 | switch (*fmt++) | |
2514 | { | |
2515 | case '\0': | |
2516 | break; | |
2517 | ||
2518 | case ',': | |
2519 | case '(': | |
2520 | case ')': | |
2521 | continue; | |
2522 | ||
2523 | case 't': | |
2524 | case 'w': | |
2525 | case 'E': | |
2526 | insn.insn_opcode |= va_arg (args, int) << 16; | |
2527 | continue; | |
2528 | ||
2529 | case 'c': | |
2530 | case 'T': | |
2531 | case 'W': | |
2532 | insn.insn_opcode |= va_arg (args, int) << 16; | |
2533 | continue; | |
2534 | ||
2535 | case 'd': | |
2536 | case 'G': | |
2537 | insn.insn_opcode |= va_arg (args, int) << 11; | |
2538 | continue; | |
2539 | ||
2540 | case 'V': | |
2541 | case 'S': | |
2542 | insn.insn_opcode |= va_arg (args, int) << 11; | |
2543 | continue; | |
2544 | ||
2545 | case 'z': | |
2546 | continue; | |
2547 | ||
2548 | case '<': | |
2549 | insn.insn_opcode |= va_arg (args, int) << 6; | |
2550 | continue; | |
2551 | ||
2552 | case 'D': | |
2553 | insn.insn_opcode |= va_arg (args, int) << 6; | |
2554 | continue; | |
2555 | ||
2556 | case 'B': | |
2557 | insn.insn_opcode |= va_arg (args, int) << 6; | |
2558 | continue; | |
2559 | ||
2560 | case 'q': | |
2561 | insn.insn_opcode |= va_arg (args, int) << 6; | |
2562 | continue; | |
2563 | ||
2564 | case 'b': | |
2565 | case 's': | |
2566 | case 'r': | |
2567 | case 'v': | |
2568 | insn.insn_opcode |= va_arg (args, int) << 21; | |
2569 | continue; | |
2570 | ||
2571 | case 'i': | |
2572 | case 'j': | |
2573 | case 'o': | |
2574 | r = (bfd_reloc_code_real_type) va_arg (args, int); | |
2575 | assert (r == BFD_RELOC_MIPS_GPREL | |
2576 | || r == BFD_RELOC_MIPS_LITERAL | |
2577 | || r == BFD_RELOC_LO16 | |
2578 | || r == BFD_RELOC_MIPS_GOT16 | |
2579 | || r == BFD_RELOC_MIPS_CALL16 | |
2580 | || r == BFD_RELOC_MIPS_GOT_LO16 | |
2581 | || r == BFD_RELOC_MIPS_CALL_LO16 | |
2582 | || (ep->X_op == O_subtract | |
2583 | && now_seg == text_section | |
2584 | && r == BFD_RELOC_PCREL_LO16)); | |
2585 | continue; | |
2586 | ||
2587 | case 'u': | |
2588 | r = (bfd_reloc_code_real_type) va_arg (args, int); | |
2589 | assert (ep != NULL | |
2590 | && (ep->X_op == O_constant | |
2591 | || (ep->X_op == O_symbol | |
2592 | && (r == BFD_RELOC_HI16_S | |
2593 | || r == BFD_RELOC_HI16 | |
2594 | || r == BFD_RELOC_MIPS_GOT_HI16 | |
2595 | || r == BFD_RELOC_MIPS_CALL_HI16)) | |
2596 | || (ep->X_op == O_subtract | |
2597 | && now_seg == text_section | |
2598 | && r == BFD_RELOC_PCREL_HI16_S))); | |
2599 | if (ep->X_op == O_constant) | |
2600 | { | |
2601 | insn.insn_opcode |= (ep->X_add_number >> 16) & 0xffff; | |
2602 | ep = NULL; | |
2603 | r = BFD_RELOC_UNUSED; | |
2604 | } | |
2605 | continue; | |
2606 | ||
2607 | case 'p': | |
2608 | assert (ep != NULL); | |
2609 | /* | |
2610 | * This allows macro() to pass an immediate expression for | |
2611 | * creating short branches without creating a symbol. | |
2612 | * Note that the expression still might come from the assembly | |
2613 | * input, in which case the value is not checked for range nor | |
2614 | * is a relocation entry generated (yuck). | |
2615 | */ | |
2616 | if (ep->X_op == O_constant) | |
2617 | { | |
2618 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; | |
2619 | ep = NULL; | |
2620 | } | |
2621 | else | |
2622 | r = BFD_RELOC_16_PCREL_S2; | |
2623 | continue; | |
2624 | ||
2625 | case 'a': | |
2626 | assert (ep != NULL); | |
2627 | r = BFD_RELOC_MIPS_JMP; | |
2628 | continue; | |
2629 | ||
2630 | case 'C': | |
2631 | insn.insn_opcode |= va_arg (args, unsigned long); | |
2632 | continue; | |
2633 | ||
2634 | default: | |
2635 | internalError (); | |
2636 | } | |
2637 | break; | |
2638 | } | |
2639 | va_end (args); | |
2640 | assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
2641 | ||
2642 | append_insn (place, &insn, ep, r, false); | |
2643 | } | |
2644 | ||
2645 | static void | |
2646 | mips16_macro_build (place, counter, ep, name, fmt, args) | |
2647 | char *place; | |
2648 | int *counter; | |
2649 | expressionS *ep; | |
2650 | const char *name; | |
2651 | const char *fmt; | |
2652 | va_list args; | |
2653 | { | |
2654 | struct mips_cl_insn insn; | |
2655 | bfd_reloc_code_real_type r; | |
2656 | ||
2657 | r = BFD_RELOC_UNUSED; | |
2658 | insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); | |
2659 | assert (insn.insn_mo); | |
2660 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2661 | ||
2662 | while (strcmp (fmt, insn.insn_mo->args) != 0 | |
2663 | || insn.insn_mo->pinfo == INSN_MACRO) | |
2664 | { | |
2665 | ++insn.insn_mo; | |
2666 | assert (insn.insn_mo->name); | |
2667 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2668 | } | |
2669 | ||
2670 | insn.insn_opcode = insn.insn_mo->match; | |
2671 | insn.use_extend = false; | |
2672 | ||
2673 | for (;;) | |
2674 | { | |
2675 | int c; | |
2676 | ||
2677 | c = *fmt++; | |
2678 | switch (c) | |
2679 | { | |
2680 | case '\0': | |
2681 | break; | |
2682 | ||
2683 | case ',': | |
2684 | case '(': | |
2685 | case ')': | |
2686 | continue; | |
2687 | ||
2688 | case 'y': | |
2689 | case 'w': | |
2690 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY; | |
2691 | continue; | |
2692 | ||
2693 | case 'x': | |
2694 | case 'v': | |
2695 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX; | |
2696 | continue; | |
2697 | ||
2698 | case 'z': | |
2699 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ; | |
2700 | continue; | |
2701 | ||
2702 | case 'Z': | |
2703 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z; | |
2704 | continue; | |
2705 | ||
2706 | case '0': | |
2707 | case 'S': | |
2708 | case 'P': | |
2709 | case 'R': | |
2710 | continue; | |
2711 | ||
2712 | case 'X': | |
2713 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32; | |
2714 | continue; | |
2715 | ||
2716 | case 'Y': | |
2717 | { | |
2718 | int regno; | |
2719 | ||
2720 | regno = va_arg (args, int); | |
2721 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
2722 | insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
2723 | } | |
2724 | continue; | |
2725 | ||
2726 | case '<': | |
2727 | case '>': | |
2728 | case '4': | |
2729 | case '5': | |
2730 | case 'H': | |
2731 | case 'W': | |
2732 | case 'D': | |
2733 | case 'j': | |
2734 | case '8': | |
2735 | case 'V': | |
2736 | case 'C': | |
2737 | case 'U': | |
2738 | case 'k': | |
2739 | case 'K': | |
2740 | case 'p': | |
2741 | case 'q': | |
2742 | { | |
2743 | assert (ep != NULL); | |
2744 | ||
2745 | if (ep->X_op != O_constant) | |
2746 | r = BFD_RELOC_UNUSED + c; | |
2747 | else | |
2748 | { | |
2749 | mips16_immed ((char *) NULL, 0, c, ep->X_add_number, false, | |
2750 | false, false, &insn.insn_opcode, | |
2751 | &insn.use_extend, &insn.extend); | |
2752 | ep = NULL; | |
2753 | r = BFD_RELOC_UNUSED; | |
2754 | } | |
2755 | } | |
2756 | continue; | |
2757 | ||
2758 | case '6': | |
2759 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6; | |
2760 | continue; | |
2761 | } | |
2762 | ||
2763 | break; | |
2764 | } | |
2765 | ||
2766 | assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
2767 | ||
2768 | append_insn (place, &insn, ep, r, false); | |
2769 | } | |
2770 | ||
2771 | /* | |
2772 | * Generate a "lui" instruction. | |
2773 | */ | |
2774 | static void | |
2775 | macro_build_lui (place, counter, ep, regnum) | |
2776 | char *place; | |
2777 | int *counter; | |
2778 | expressionS *ep; | |
2779 | int regnum; | |
2780 | { | |
2781 | expressionS high_expr; | |
2782 | struct mips_cl_insn insn; | |
2783 | bfd_reloc_code_real_type r; | |
2784 | CONST char *name = "lui"; | |
2785 | CONST char *fmt = "t,u"; | |
2786 | ||
2787 | assert (! mips_opts.mips16); | |
2788 | ||
2789 | if (place == NULL) | |
2790 | high_expr = *ep; | |
2791 | else | |
2792 | { | |
2793 | high_expr.X_op = O_constant; | |
2794 | high_expr.X_add_number = ep->X_add_number; | |
2795 | } | |
2796 | ||
2797 | if (high_expr.X_op == O_constant) | |
2798 | { | |
2799 | /* we can compute the instruction now without a relocation entry */ | |
2800 | if (high_expr.X_add_number & 0x8000) | |
2801 | high_expr.X_add_number += 0x10000; | |
2802 | high_expr.X_add_number = | |
2803 | ((unsigned long) high_expr.X_add_number >> 16) & 0xffff; | |
2804 | r = BFD_RELOC_UNUSED; | |
2805 | } | |
2806 | else | |
2807 | { | |
2808 | assert (ep->X_op == O_symbol); | |
2809 | /* _gp_disp is a special case, used from s_cpload. */ | |
2810 | assert (mips_pic == NO_PIC | |
2811 | || strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0); | |
2812 | r = BFD_RELOC_HI16_S; | |
2813 | } | |
2814 | ||
2815 | /* | |
2816 | * If the macro is about to expand into a second instruction, | |
2817 | * print a warning if needed. We need to pass ip as a parameter | |
2818 | * to generate a better warning message here... | |
2819 | */ | |
2820 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) | |
2821 | as_warn (_("Macro instruction expanded into multiple instructions")); | |
2822 | ||
2823 | if (place == NULL) | |
2824 | *counter += 1; /* bump instruction counter */ | |
2825 | ||
2826 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); | |
2827 | assert (insn.insn_mo); | |
2828 | assert (strcmp (name, insn.insn_mo->name) == 0); | |
2829 | assert (strcmp (fmt, insn.insn_mo->args) == 0); | |
2830 | ||
2831 | insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT); | |
2832 | if (r == BFD_RELOC_UNUSED) | |
2833 | { | |
2834 | insn.insn_opcode |= high_expr.X_add_number; | |
2835 | append_insn (place, &insn, NULL, r, false); | |
2836 | } | |
2837 | else | |
2838 | append_insn (place, &insn, &high_expr, r, false); | |
2839 | } | |
2840 | ||
2841 | /* set_at() | |
2842 | * Generates code to set the $at register to true (one) | |
2843 | * if reg is less than the immediate expression. | |
2844 | */ | |
2845 | static void | |
2846 | set_at (counter, reg, unsignedp) | |
2847 | int *counter; | |
2848 | int reg; | |
2849 | int unsignedp; | |
2850 | { | |
2851 | if (imm_expr.X_op == O_constant | |
2852 | && imm_expr.X_add_number >= -0x8000 | |
2853 | && imm_expr.X_add_number < 0x8000) | |
2854 | macro_build ((char *) NULL, counter, &imm_expr, | |
2855 | unsignedp ? "sltiu" : "slti", | |
2856 | "t,r,j", AT, reg, (int) BFD_RELOC_LO16); | |
2857 | else | |
2858 | { | |
2859 | load_register (counter, AT, &imm_expr, 0); | |
2860 | macro_build ((char *) NULL, counter, NULL, | |
2861 | unsignedp ? "sltu" : "slt", | |
2862 | "d,v,t", AT, reg, AT); | |
2863 | } | |
2864 | } | |
2865 | ||
2866 | /* Warn if an expression is not a constant. */ | |
2867 | ||
2868 | static void | |
2869 | check_absolute_expr (ip, ex) | |
2870 | struct mips_cl_insn *ip; | |
2871 | expressionS *ex; | |
2872 | { | |
2873 | if (ex->X_op == O_big) | |
2874 | as_bad (_("unsupported large constant")); | |
2875 | else if (ex->X_op != O_constant) | |
2876 | as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name); | |
2877 | } | |
2878 | ||
2879 | /* Count the leading zeroes by performing a binary chop. This is a | |
2880 | bulky bit of source, but performance is a LOT better for the | |
2881 | majority of values than a simple loop to count the bits: | |
2882 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
2883 | if ((v) & (1 << (31 - lcnt))) | |
2884 | break; | |
2885 | However it is not code size friendly, and the gain will drop a bit | |
2886 | on certain cached systems. | |
2887 | */ | |
2888 | #define COUNT_TOP_ZEROES(v) \ | |
2889 | (((v) & ~0xffff) == 0 \ | |
2890 | ? ((v) & ~0xff) == 0 \ | |
2891 | ? ((v) & ~0xf) == 0 \ | |
2892 | ? ((v) & ~0x3) == 0 \ | |
2893 | ? ((v) & ~0x1) == 0 \ | |
2894 | ? !(v) \ | |
2895 | ? 32 \ | |
2896 | : 31 \ | |
2897 | : 30 \ | |
2898 | : ((v) & ~0x7) == 0 \ | |
2899 | ? 29 \ | |
2900 | : 28 \ | |
2901 | : ((v) & ~0x3f) == 0 \ | |
2902 | ? ((v) & ~0x1f) == 0 \ | |
2903 | ? 27 \ | |
2904 | : 26 \ | |
2905 | : ((v) & ~0x7f) == 0 \ | |
2906 | ? 25 \ | |
2907 | : 24 \ | |
2908 | : ((v) & ~0xfff) == 0 \ | |
2909 | ? ((v) & ~0x3ff) == 0 \ | |
2910 | ? ((v) & ~0x1ff) == 0 \ | |
2911 | ? 23 \ | |
2912 | : 22 \ | |
2913 | : ((v) & ~0x7ff) == 0 \ | |
2914 | ? 21 \ | |
2915 | : 20 \ | |
2916 | : ((v) & ~0x3fff) == 0 \ | |
2917 | ? ((v) & ~0x1fff) == 0 \ | |
2918 | ? 19 \ | |
2919 | : 18 \ | |
2920 | : ((v) & ~0x7fff) == 0 \ | |
2921 | ? 17 \ | |
2922 | : 16 \ | |
2923 | : ((v) & ~0xffffff) == 0 \ | |
2924 | ? ((v) & ~0xfffff) == 0 \ | |
2925 | ? ((v) & ~0x3ffff) == 0 \ | |
2926 | ? ((v) & ~0x1ffff) == 0 \ | |
2927 | ? 15 \ | |
2928 | : 14 \ | |
2929 | : ((v) & ~0x7ffff) == 0 \ | |
2930 | ? 13 \ | |
2931 | : 12 \ | |
2932 | : ((v) & ~0x3fffff) == 0 \ | |
2933 | ? ((v) & ~0x1fffff) == 0 \ | |
2934 | ? 11 \ | |
2935 | : 10 \ | |
2936 | : ((v) & ~0x7fffff) == 0 \ | |
2937 | ? 9 \ | |
2938 | : 8 \ | |
2939 | : ((v) & ~0xfffffff) == 0 \ | |
2940 | ? ((v) & ~0x3ffffff) == 0 \ | |
2941 | ? ((v) & ~0x1ffffff) == 0 \ | |
2942 | ? 7 \ | |
2943 | : 6 \ | |
2944 | : ((v) & ~0x7ffffff) == 0 \ | |
2945 | ? 5 \ | |
2946 | : 4 \ | |
2947 | : ((v) & ~0x3fffffff) == 0 \ | |
2948 | ? ((v) & ~0x1fffffff) == 0 \ | |
2949 | ? 3 \ | |
2950 | : 2 \ | |
2951 | : ((v) & ~0x7fffffff) == 0 \ | |
2952 | ? 1 \ | |
2953 | : 0) | |
2954 | ||
2955 | /* load_register() | |
2956 | * This routine generates the least number of instructions neccessary to load | |
2957 | * an absolute expression value into a register. | |
2958 | */ | |
2959 | static void | |
2960 | load_register (counter, reg, ep, dbl) | |
2961 | int *counter; | |
2962 | int reg; | |
2963 | expressionS *ep; | |
2964 | int dbl; | |
2965 | { | |
2966 | int freg; | |
2967 | expressionS hi32, lo32; | |
2968 | ||
2969 | if (ep->X_op != O_big) | |
2970 | { | |
2971 | assert (ep->X_op == O_constant); | |
2972 | if (ep->X_add_number < 0x8000 | |
2973 | && (ep->X_add_number >= 0 | |
2974 | || (ep->X_add_number >= -0x8000 | |
2975 | && (! dbl | |
2976 | || ! ep->X_unsigned | |
2977 | || sizeof (ep->X_add_number) > 4)))) | |
2978 | { | |
2979 | /* We can handle 16 bit signed values with an addiu to | |
2980 | $zero. No need to ever use daddiu here, since $zero and | |
2981 | the result are always correct in 32 bit mode. */ | |
2982 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, | |
2983 | (int) BFD_RELOC_LO16); | |
2984 | return; | |
2985 | } | |
2986 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
2987 | { | |
2988 | /* We can handle 16 bit unsigned values with an ori to | |
2989 | $zero. */ | |
2990 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0, | |
2991 | (int) BFD_RELOC_LO16); | |
2992 | return; | |
2993 | } | |
2994 | else if ((((ep->X_add_number &~ (offsetT) 0x7fffffff) == 0 | |
2995 | || ((ep->X_add_number &~ (offsetT) 0x7fffffff) | |
2996 | == ~ (offsetT) 0x7fffffff)) | |
2997 | && (! dbl | |
2998 | || ! ep->X_unsigned | |
2999 | || sizeof (ep->X_add_number) > 4 | |
3000 | || (ep->X_add_number & 0x80000000) == 0)) | |
9ce8a5dd | 3001 | || ((! ISA_HAS_64BIT_REGS (mips_opts.isa) || ! dbl) |
252b5132 | 3002 | && (ep->X_add_number &~ (offsetT) 0xffffffff) == 0) |
9ce8a5dd | 3003 | || (! ISA_HAS_64BIT_REGS (mips_opts.isa) |
252b5132 RH |
3004 | && ! dbl |
3005 | && ((ep->X_add_number &~ (offsetT) 0xffffffff) | |
3006 | == ~ (offsetT) 0xffffffff))) | |
3007 | { | |
3008 | /* 32 bit values require an lui. */ | |
3009 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
3010 | (int) BFD_RELOC_HI16); | |
3011 | if ((ep->X_add_number & 0xffff) != 0) | |
3012 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg, | |
3013 | (int) BFD_RELOC_LO16); | |
3014 | return; | |
3015 | } | |
3016 | } | |
3017 | ||
3018 | /* The value is larger than 32 bits. */ | |
3019 | ||
9ce8a5dd | 3020 | if (! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
3021 | { |
3022 | as_bad (_("Number larger than 32 bits")); | |
3023 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, | |
3024 | (int) BFD_RELOC_LO16); | |
3025 | return; | |
3026 | } | |
3027 | ||
3028 | if (ep->X_op != O_big) | |
3029 | { | |
3030 | hi32 = *ep; | |
3031 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3032 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
3033 | hi32.X_add_number &= 0xffffffff; | |
3034 | lo32 = *ep; | |
3035 | lo32.X_add_number &= 0xffffffff; | |
3036 | } | |
3037 | else | |
3038 | { | |
3039 | assert (ep->X_add_number > 2); | |
3040 | if (ep->X_add_number == 3) | |
3041 | generic_bignum[3] = 0; | |
3042 | else if (ep->X_add_number > 4) | |
3043 | as_bad (_("Number larger than 64 bits")); | |
3044 | lo32.X_op = O_constant; | |
3045 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
3046 | hi32.X_op = O_constant; | |
3047 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
3048 | } | |
3049 | ||
3050 | if (hi32.X_add_number == 0) | |
3051 | freg = 0; | |
3052 | else | |
3053 | { | |
3054 | int shift, bit; | |
3055 | unsigned long hi, lo; | |
3056 | ||
3057 | if (hi32.X_add_number == 0xffffffff) | |
3058 | { | |
3059 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
3060 | { | |
3061 | macro_build ((char *) NULL, counter, &lo32, "addiu", "t,r,j", | |
3062 | reg, 0, (int) BFD_RELOC_LO16); | |
3063 | return; | |
3064 | } | |
3065 | if (lo32.X_add_number & 0x80000000) | |
3066 | { | |
3067 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
3068 | (int) BFD_RELOC_HI16); | |
3069 | if (lo32.X_add_number & 0xffff) | |
3070 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", | |
3071 | reg, reg, (int) BFD_RELOC_LO16); | |
3072 | return; | |
3073 | } | |
3074 | } | |
3075 | ||
3076 | /* Check for 16bit shifted constant. We know that hi32 is | |
3077 | non-zero, so start the mask on the first bit of the hi32 | |
3078 | value. */ | |
3079 | shift = 17; | |
3080 | do | |
3081 | { | |
3082 | unsigned long himask, lomask; | |
3083 | ||
3084 | if (shift < 32) | |
3085 | { | |
3086 | himask = 0xffff >> (32 - shift); | |
3087 | lomask = (0xffff << shift) & 0xffffffff; | |
3088 | } | |
3089 | else | |
3090 | { | |
3091 | himask = 0xffff << (shift - 32); | |
3092 | lomask = 0; | |
3093 | } | |
3094 | if ((hi32.X_add_number & ~ (offsetT) himask) == 0 | |
3095 | && (lo32.X_add_number & ~ (offsetT) lomask) == 0) | |
3096 | { | |
3097 | expressionS tmp; | |
3098 | ||
3099 | tmp.X_op = O_constant; | |
3100 | if (shift < 32) | |
3101 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
3102 | | (lo32.X_add_number >> shift)); | |
3103 | else | |
3104 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
3105 | macro_build ((char *) NULL, counter, &tmp, "ori", "t,r,i", reg, 0, | |
3106 | (int) BFD_RELOC_LO16); | |
3107 | macro_build ((char *) NULL, counter, NULL, | |
3108 | (shift >= 32) ? "dsll32" : "dsll", | |
3109 | "d,w,<", reg, reg, | |
3110 | (shift >= 32) ? shift - 32 : shift); | |
3111 | return; | |
3112 | } | |
3113 | shift++; | |
3114 | } while (shift <= (64 - 16)); | |
3115 | ||
3116 | /* Find the bit number of the lowest one bit, and store the | |
3117 | shifted value in hi/lo. */ | |
3118 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
3119 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
3120 | if (lo != 0) | |
3121 | { | |
3122 | bit = 0; | |
3123 | while ((lo & 1) == 0) | |
3124 | { | |
3125 | lo >>= 1; | |
3126 | ++bit; | |
3127 | } | |
3128 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
3129 | hi >>= bit; | |
3130 | } | |
3131 | else | |
3132 | { | |
3133 | bit = 32; | |
3134 | while ((hi & 1) == 0) | |
3135 | { | |
3136 | hi >>= 1; | |
3137 | ++bit; | |
3138 | } | |
3139 | lo = hi; | |
3140 | hi = 0; | |
3141 | } | |
3142 | ||
3143 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
3144 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
3145 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
3146 | { | |
3147 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
3148 | if (shift != 0) | |
3149 | { | |
3150 | expressionS tmp; | |
3151 | ||
3152 | /* This instruction will set the register to be all | |
3153 | ones. */ | |
3154 | tmp.X_op = O_constant; | |
3155 | tmp.X_add_number = (offsetT) -1; | |
3156 | macro_build ((char *) NULL, counter, &tmp, "addiu", "t,r,j", | |
3157 | reg, 0, (int) BFD_RELOC_LO16); | |
3158 | if (bit != 0) | |
3159 | { | |
3160 | bit += shift; | |
3161 | macro_build ((char *) NULL, counter, NULL, | |
3162 | (bit >= 32) ? "dsll32" : "dsll", | |
3163 | "d,w,<", reg, reg, | |
3164 | (bit >= 32) ? bit - 32 : bit); | |
3165 | } | |
3166 | macro_build ((char *) NULL, counter, NULL, | |
3167 | (shift >= 32) ? "dsrl32" : "dsrl", | |
3168 | "d,w,<", reg, reg, | |
3169 | (shift >= 32) ? shift - 32 : shift); | |
3170 | return; | |
3171 | } | |
3172 | } | |
3173 | ||
3174 | /* Sign extend hi32 before calling load_register, because we can | |
3175 | generally get better code when we load a sign extended value. */ | |
3176 | if ((hi32.X_add_number & 0x80000000) != 0) | |
3177 | hi32.X_add_number |= ~ (offsetT) 0xffffffff; | |
3178 | load_register (counter, reg, &hi32, 0); | |
3179 | freg = reg; | |
3180 | } | |
3181 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
3182 | { | |
3183 | if (freg != 0) | |
3184 | { | |
3185 | macro_build ((char *) NULL, counter, NULL, "dsll32", "d,w,<", reg, | |
3186 | freg, 0); | |
3187 | freg = reg; | |
3188 | } | |
3189 | } | |
3190 | else | |
3191 | { | |
3192 | expressionS mid16; | |
3193 | ||
3194 | if ((freg == 0) && (lo32.X_add_number == 0xffffffff)) | |
3195 | { | |
3196 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, | |
3197 | (int) BFD_RELOC_HI16); | |
3198 | macro_build ((char *) NULL, counter, NULL, "dsrl32", "d,w,<", reg, | |
3199 | reg, 0); | |
3200 | return; | |
3201 | } | |
3202 | ||
3203 | if (freg != 0) | |
3204 | { | |
3205 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, | |
3206 | freg, 16); | |
3207 | freg = reg; | |
3208 | } | |
3209 | mid16 = lo32; | |
3210 | mid16.X_add_number >>= 16; | |
3211 | macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg, | |
3212 | freg, (int) BFD_RELOC_LO16); | |
3213 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, | |
3214 | reg, 16); | |
3215 | freg = reg; | |
3216 | } | |
3217 | if ((lo32.X_add_number & 0xffff) != 0) | |
3218 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, freg, | |
3219 | (int) BFD_RELOC_LO16); | |
3220 | } | |
3221 | ||
3222 | /* Load an address into a register. */ | |
3223 | ||
3224 | static void | |
3225 | load_address (counter, reg, ep) | |
3226 | int *counter; | |
3227 | int reg; | |
3228 | expressionS *ep; | |
3229 | { | |
3230 | char *p; | |
3231 | ||
3232 | if (ep->X_op != O_constant | |
3233 | && ep->X_op != O_symbol) | |
3234 | { | |
3235 | as_bad (_("expression too complex")); | |
3236 | ep->X_op = O_constant; | |
3237 | } | |
3238 | ||
3239 | if (ep->X_op == O_constant) | |
3240 | { | |
3241 | load_register (counter, reg, ep, 0); | |
3242 | return; | |
3243 | } | |
3244 | ||
3245 | if (mips_pic == NO_PIC) | |
3246 | { | |
3247 | /* If this is a reference to a GP relative symbol, we want | |
3248 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
3249 | Otherwise we want | |
3250 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
3251 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
3252 | If we have an addend, we always use the latter form. */ | |
3253 | if ((valueT) ep->X_add_number >= MAX_GPREL_OFFSET | |
3254 | || nopic_need_relax (ep->X_add_symbol, 1)) | |
3255 | p = NULL; | |
3256 | else | |
3257 | { | |
3258 | frag_grow (20); | |
3259 | macro_build ((char *) NULL, counter, ep, | |
3260 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 3261 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
3262 | ? "addiu" : "daddiu"), |
3263 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
3264 | p = frag_var (rs_machine_dependent, 8, 0, | |
3265 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
3266 | mips_opts.warn_about_macros), | |
3267 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); | |
3268 | } | |
3269 | macro_build_lui (p, counter, ep, reg); | |
3270 | if (p != NULL) | |
3271 | p += 4; | |
3272 | macro_build (p, counter, ep, | |
3273 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 3274 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
3275 | ? "addiu" : "daddiu"), |
3276 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
3277 | } | |
3278 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
3279 | { | |
3280 | expressionS ex; | |
3281 | ||
3282 | /* If this is a reference to an external symbol, we want | |
3283 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3284 | Otherwise we want | |
3285 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3286 | nop | |
3287 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
3288 | If there is a constant, it must be added in after. */ | |
3289 | ex.X_add_number = ep->X_add_number; | |
3290 | ep->X_add_number = 0; | |
3291 | frag_grow (20); | |
3292 | macro_build ((char *) NULL, counter, ep, | |
3293 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 3294 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
3295 | ? "lw" : "ld"), |
3296 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
3297 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", ""); | |
3298 | p = frag_var (rs_machine_dependent, 4, 0, | |
3299 | RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts.warn_about_macros), | |
3300 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); | |
3301 | macro_build (p, counter, ep, | |
3302 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 3303 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
3304 | ? "addiu" : "daddiu"), |
3305 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
3306 | if (ex.X_add_number != 0) | |
3307 | { | |
3308 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3309 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3310 | ex.X_op = O_constant; | |
3311 | macro_build ((char *) NULL, counter, &ex, | |
3312 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 3313 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
3314 | ? "addiu" : "daddiu"), |
3315 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
3316 | } | |
3317 | } | |
3318 | else if (mips_pic == SVR4_PIC) | |
3319 | { | |
3320 | expressionS ex; | |
3321 | int off; | |
3322 | ||
3323 | /* This is the large GOT case. If this is a reference to an | |
3324 | external symbol, we want | |
3325 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
3326 | addu $reg,$reg,$gp | |
3327 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
3328 | Otherwise, for a reference to a local symbol, we want | |
3329 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
3330 | nop | |
3331 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
3332 | If there is a constant, it must be added in after. */ | |
3333 | ex.X_add_number = ep->X_add_number; | |
3334 | ep->X_add_number = 0; | |
3335 | if (reg_needs_delay (GP)) | |
3336 | off = 4; | |
3337 | else | |
3338 | off = 0; | |
3339 | frag_grow (32); | |
3340 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, | |
3341 | (int) BFD_RELOC_MIPS_GOT_HI16); | |
3342 | macro_build ((char *) NULL, counter, (expressionS *) NULL, | |
3343 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 3344 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
3345 | ? "addu" : "daddu"), |
3346 | "d,v,t", reg, reg, GP); | |
3347 | macro_build ((char *) NULL, counter, ep, | |
3348 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 3349 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
3350 | ? "lw" : "ld"), |
3351 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg); | |
3352 | p = frag_var (rs_machine_dependent, 12 + off, 0, | |
3353 | RELAX_ENCODE (12, 12 + off, off, 8 + off, 0, | |
3354 | mips_opts.warn_about_macros), | |
3355 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); | |
3356 | if (off > 0) | |
3357 | { | |
3358 | /* We need a nop before loading from $gp. This special | |
3359 | check is required because the lui which starts the main | |
3360 | instruction stream does not refer to $gp, and so will not | |
3361 | insert the nop which may be required. */ | |
3362 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
3363 | p += 4; | |
3364 | } | |
3365 | macro_build (p, counter, ep, | |
3366 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 3367 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
3368 | ? "lw" : "ld"), |
3369 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
3370 | p += 4; | |
3371 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); | |
3372 | p += 4; | |
3373 | macro_build (p, counter, ep, | |
3374 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 3375 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
3376 | ? "addiu" : "daddiu"), |
3377 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
3378 | if (ex.X_add_number != 0) | |
3379 | { | |
3380 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
3381 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
3382 | ex.X_op = O_constant; | |
3383 | macro_build ((char *) NULL, counter, &ex, | |
3384 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 3385 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
3386 | ? "addiu" : "daddiu"), |
3387 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); | |
3388 | } | |
3389 | } | |
3390 | else if (mips_pic == EMBEDDED_PIC) | |
3391 | { | |
3392 | /* We always do | |
3393 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
3394 | */ | |
3395 | macro_build ((char *) NULL, counter, ep, | |
3396 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 3397 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
3398 | ? "addiu" : "daddiu"), |
3399 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
3400 | } | |
3401 | else | |
3402 | abort (); | |
3403 | } | |
3404 | ||
3405 | /* | |
3406 | * Build macros | |
3407 | * This routine implements the seemingly endless macro or synthesized | |
3408 | * instructions and addressing modes in the mips assembly language. Many | |
3409 | * of these macros are simple and are similar to each other. These could | |
3410 | * probably be handled by some kind of table or grammer aproach instead of | |
3411 | * this verbose method. Others are not simple macros but are more like | |
3412 | * optimizing code generation. | |
3413 | * One interesting optimization is when several store macros appear | |
3414 | * consecutivly that would load AT with the upper half of the same address. | |
3415 | * The ensuing load upper instructions are ommited. This implies some kind | |
3416 | * of global optimization. We currently only optimize within a single macro. | |
3417 | * For many of the load and store macros if the address is specified as a | |
3418 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
3419 | * first load register 'at' with zero and use it as the base register. The | |
3420 | * mips assembler simply uses register $zero. Just one tiny optimization | |
3421 | * we're missing. | |
3422 | */ | |
3423 | static void | |
3424 | macro (ip) | |
3425 | struct mips_cl_insn *ip; | |
3426 | { | |
3427 | register int treg, sreg, dreg, breg; | |
3428 | int tempreg; | |
3429 | int mask; | |
3430 | int icnt = 0; | |
3431 | int used_at; | |
3432 | expressionS expr1; | |
3433 | const char *s; | |
3434 | const char *s2; | |
3435 | const char *fmt; | |
3436 | int likely = 0; | |
3437 | int dbl = 0; | |
3438 | int coproc = 0; | |
3439 | int lr = 0; | |
3440 | int imm = 0; | |
3441 | offsetT maxnum; | |
3442 | int off; | |
3443 | bfd_reloc_code_real_type r; | |
3444 | char *p; | |
3445 | int hold_mips_optimize; | |
3446 | ||
3447 | assert (! mips_opts.mips16); | |
3448 | ||
3449 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
3450 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
3451 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
3452 | mask = ip->insn_mo->mask; | |
3453 | ||
3454 | expr1.X_op = O_constant; | |
3455 | expr1.X_op_symbol = NULL; | |
3456 | expr1.X_add_symbol = NULL; | |
3457 | expr1.X_add_number = 1; | |
3458 | ||
3459 | switch (mask) | |
3460 | { | |
3461 | case M_DABS: | |
3462 | dbl = 1; | |
3463 | case M_ABS: | |
3464 | /* bgez $a0,.+12 | |
3465 | move v0,$a0 | |
3466 | sub v0,$zero,$a0 | |
3467 | */ | |
3468 | ||
3469 | mips_emit_delays (true); | |
3470 | ++mips_opts.noreorder; | |
3471 | mips_any_noreorder = 1; | |
3472 | ||
3473 | expr1.X_add_number = 8; | |
3474 | macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg); | |
3475 | if (dreg == sreg) | |
3476 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3477 | else | |
3478 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, sreg, 0); | |
3479 | macro_build ((char *) NULL, &icnt, NULL, | |
3480 | dbl ? "dsub" : "sub", | |
3481 | "d,v,t", dreg, 0, sreg); | |
3482 | ||
3483 | --mips_opts.noreorder; | |
3484 | return; | |
3485 | ||
3486 | case M_ADD_I: | |
3487 | s = "addi"; | |
3488 | s2 = "add"; | |
3489 | goto do_addi; | |
3490 | case M_ADDU_I: | |
3491 | s = "addiu"; | |
3492 | s2 = "addu"; | |
3493 | goto do_addi; | |
3494 | case M_DADD_I: | |
3495 | dbl = 1; | |
3496 | s = "daddi"; | |
3497 | s2 = "dadd"; | |
3498 | goto do_addi; | |
3499 | case M_DADDU_I: | |
3500 | dbl = 1; | |
3501 | s = "daddiu"; | |
3502 | s2 = "daddu"; | |
3503 | do_addi: | |
3504 | if (imm_expr.X_op == O_constant | |
3505 | && imm_expr.X_add_number >= -0x8000 | |
3506 | && imm_expr.X_add_number < 0x8000) | |
3507 | { | |
3508 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg, | |
3509 | (int) BFD_RELOC_LO16); | |
3510 | return; | |
3511 | } | |
3512 | load_register (&icnt, AT, &imm_expr, dbl); | |
3513 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); | |
3514 | break; | |
3515 | ||
3516 | case M_AND_I: | |
3517 | s = "andi"; | |
3518 | s2 = "and"; | |
3519 | goto do_bit; | |
3520 | case M_OR_I: | |
3521 | s = "ori"; | |
3522 | s2 = "or"; | |
3523 | goto do_bit; | |
3524 | case M_NOR_I: | |
3525 | s = ""; | |
3526 | s2 = "nor"; | |
3527 | goto do_bit; | |
3528 | case M_XOR_I: | |
3529 | s = "xori"; | |
3530 | s2 = "xor"; | |
3531 | do_bit: | |
3532 | if (imm_expr.X_op == O_constant | |
3533 | && imm_expr.X_add_number >= 0 | |
3534 | && imm_expr.X_add_number < 0x10000) | |
3535 | { | |
3536 | if (mask != M_NOR_I) | |
3537 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg, | |
3538 | sreg, (int) BFD_RELOC_LO16); | |
3539 | else | |
3540 | { | |
3541 | macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i", | |
3542 | treg, sreg, (int) BFD_RELOC_LO16); | |
3543 | macro_build ((char *) NULL, &icnt, NULL, "nor", "d,v,t", | |
3544 | treg, treg, 0); | |
3545 | } | |
3546 | return; | |
3547 | } | |
3548 | ||
3549 | load_register (&icnt, AT, &imm_expr, 0); | |
3550 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); | |
3551 | break; | |
3552 | ||
3553 | case M_BEQ_I: | |
3554 | s = "beq"; | |
3555 | goto beq_i; | |
3556 | case M_BEQL_I: | |
3557 | s = "beql"; | |
3558 | likely = 1; | |
3559 | goto beq_i; | |
3560 | case M_BNE_I: | |
3561 | s = "bne"; | |
3562 | goto beq_i; | |
3563 | case M_BNEL_I: | |
3564 | s = "bnel"; | |
3565 | likely = 1; | |
3566 | beq_i: | |
3567 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
3568 | { | |
3569 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, | |
3570 | 0); | |
3571 | return; | |
3572 | } | |
3573 | load_register (&icnt, AT, &imm_expr, 0); | |
3574 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT); | |
3575 | break; | |
3576 | ||
3577 | case M_BGEL: | |
3578 | likely = 1; | |
3579 | case M_BGE: | |
3580 | if (treg == 0) | |
3581 | { | |
3582 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3583 | likely ? "bgezl" : "bgez", | |
3584 | "s,p", sreg); | |
3585 | return; | |
3586 | } | |
3587 | if (sreg == 0) | |
3588 | { | |
3589 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3590 | likely ? "blezl" : "blez", | |
3591 | "s,p", treg); | |
3592 | return; | |
3593 | } | |
3594 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); | |
3595 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3596 | likely ? "beql" : "beq", | |
3597 | "s,t,p", AT, 0); | |
3598 | break; | |
3599 | ||
3600 | case M_BGTL_I: | |
3601 | likely = 1; | |
3602 | case M_BGT_I: | |
3603 | /* check for > max integer */ | |
3604 | maxnum = 0x7fffffff; | |
9ce8a5dd | 3605 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) && sizeof (maxnum) > 4) |
252b5132 RH |
3606 | { |
3607 | maxnum <<= 16; | |
3608 | maxnum |= 0xffff; | |
3609 | maxnum <<= 16; | |
3610 | maxnum |= 0xffff; | |
3611 | } | |
3612 | if (imm_expr.X_op == O_constant | |
3613 | && imm_expr.X_add_number >= maxnum | |
9ce8a5dd | 3614 | && (! ISA_HAS_64BIT_REGS (mips_opts.isa) || sizeof (maxnum) > 4)) |
252b5132 RH |
3615 | { |
3616 | do_false: | |
3617 | /* result is always false */ | |
3618 | if (! likely) | |
3619 | { | |
3620 | as_warn (_("Branch %s is always false (nop)"), ip->insn_mo->name); | |
3621 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3622 | } | |
3623 | else | |
3624 | { | |
3625 | as_warn (_("Branch likely %s is always false"), ip->insn_mo->name); | |
3626 | macro_build ((char *) NULL, &icnt, &offset_expr, "bnel", | |
3627 | "s,t,p", 0, 0); | |
3628 | } | |
3629 | return; | |
3630 | } | |
3631 | if (imm_expr.X_op != O_constant) | |
3632 | as_bad (_("Unsupported large constant")); | |
3633 | imm_expr.X_add_number++; | |
3634 | /* FALLTHROUGH */ | |
3635 | case M_BGE_I: | |
3636 | case M_BGEL_I: | |
3637 | if (mask == M_BGEL_I) | |
3638 | likely = 1; | |
3639 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
3640 | { | |
3641 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3642 | likely ? "bgezl" : "bgez", | |
3643 | "s,p", sreg); | |
3644 | return; | |
3645 | } | |
3646 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
3647 | { | |
3648 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3649 | likely ? "bgtzl" : "bgtz", | |
3650 | "s,p", sreg); | |
3651 | return; | |
3652 | } | |
3653 | maxnum = 0x7fffffff; | |
9ce8a5dd | 3654 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) && sizeof (maxnum) > 4) |
252b5132 RH |
3655 | { |
3656 | maxnum <<= 16; | |
3657 | maxnum |= 0xffff; | |
3658 | maxnum <<= 16; | |
3659 | maxnum |= 0xffff; | |
3660 | } | |
3661 | maxnum = - maxnum - 1; | |
3662 | if (imm_expr.X_op == O_constant | |
3663 | && imm_expr.X_add_number <= maxnum | |
9ce8a5dd | 3664 | && (! ISA_HAS_64BIT_REGS (mips_opts.isa) || sizeof (maxnum) > 4)) |
252b5132 RH |
3665 | { |
3666 | do_true: | |
3667 | /* result is always true */ | |
3668 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); | |
3669 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); | |
3670 | return; | |
3671 | } | |
3672 | set_at (&icnt, sreg, 0); | |
3673 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3674 | likely ? "beql" : "beq", | |
3675 | "s,t,p", AT, 0); | |
3676 | break; | |
3677 | ||
3678 | case M_BGEUL: | |
3679 | likely = 1; | |
3680 | case M_BGEU: | |
3681 | if (treg == 0) | |
3682 | goto do_true; | |
3683 | if (sreg == 0) | |
3684 | { | |
3685 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3686 | likely ? "beql" : "beq", | |
3687 | "s,t,p", 0, treg); | |
3688 | return; | |
3689 | } | |
3690 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, | |
3691 | treg); | |
3692 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3693 | likely ? "beql" : "beq", | |
3694 | "s,t,p", AT, 0); | |
3695 | break; | |
3696 | ||
3697 | case M_BGTUL_I: | |
3698 | likely = 1; | |
3699 | case M_BGTU_I: | |
3700 | if (sreg == 0 | |
9ce8a5dd | 3701 | || (! ISA_HAS_64BIT_REGS (mips_opts.isa) |
252b5132 RH |
3702 | && imm_expr.X_op == O_constant |
3703 | && imm_expr.X_add_number == 0xffffffff)) | |
3704 | goto do_false; | |
3705 | if (imm_expr.X_op != O_constant) | |
3706 | as_bad (_("Unsupported large constant")); | |
3707 | imm_expr.X_add_number++; | |
3708 | /* FALLTHROUGH */ | |
3709 | case M_BGEU_I: | |
3710 | case M_BGEUL_I: | |
3711 | if (mask == M_BGEUL_I) | |
3712 | likely = 1; | |
3713 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
3714 | goto do_true; | |
3715 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
3716 | { | |
3717 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3718 | likely ? "bnel" : "bne", | |
3719 | "s,t,p", sreg, 0); | |
3720 | return; | |
3721 | } | |
3722 | set_at (&icnt, sreg, 1); | |
3723 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3724 | likely ? "beql" : "beq", | |
3725 | "s,t,p", AT, 0); | |
3726 | break; | |
3727 | ||
3728 | case M_BGTL: | |
3729 | likely = 1; | |
3730 | case M_BGT: | |
3731 | if (treg == 0) | |
3732 | { | |
3733 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3734 | likely ? "bgtzl" : "bgtz", | |
3735 | "s,p", sreg); | |
3736 | return; | |
3737 | } | |
3738 | if (sreg == 0) | |
3739 | { | |
3740 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3741 | likely ? "bltzl" : "bltz", | |
3742 | "s,p", treg); | |
3743 | return; | |
3744 | } | |
3745 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); | |
3746 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3747 | likely ? "bnel" : "bne", | |
3748 | "s,t,p", AT, 0); | |
3749 | break; | |
3750 | ||
3751 | case M_BGTUL: | |
3752 | likely = 1; | |
3753 | case M_BGTU: | |
3754 | if (treg == 0) | |
3755 | { | |
3756 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3757 | likely ? "bnel" : "bne", | |
3758 | "s,t,p", sreg, 0); | |
3759 | return; | |
3760 | } | |
3761 | if (sreg == 0) | |
3762 | goto do_false; | |
3763 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, | |
3764 | sreg); | |
3765 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3766 | likely ? "bnel" : "bne", | |
3767 | "s,t,p", AT, 0); | |
3768 | break; | |
3769 | ||
3770 | case M_BLEL: | |
3771 | likely = 1; | |
3772 | case M_BLE: | |
3773 | if (treg == 0) | |
3774 | { | |
3775 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3776 | likely ? "blezl" : "blez", | |
3777 | "s,p", sreg); | |
3778 | return; | |
3779 | } | |
3780 | if (sreg == 0) | |
3781 | { | |
3782 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3783 | likely ? "bgezl" : "bgez", | |
3784 | "s,p", treg); | |
3785 | return; | |
3786 | } | |
3787 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); | |
3788 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3789 | likely ? "beql" : "beq", | |
3790 | "s,t,p", AT, 0); | |
3791 | break; | |
3792 | ||
3793 | case M_BLEL_I: | |
3794 | likely = 1; | |
3795 | case M_BLE_I: | |
3796 | maxnum = 0x7fffffff; | |
9ce8a5dd | 3797 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) && sizeof (maxnum) > 4) |
252b5132 RH |
3798 | { |
3799 | maxnum <<= 16; | |
3800 | maxnum |= 0xffff; | |
3801 | maxnum <<= 16; | |
3802 | maxnum |= 0xffff; | |
3803 | } | |
3804 | if (imm_expr.X_op == O_constant | |
3805 | && imm_expr.X_add_number >= maxnum | |
9ce8a5dd | 3806 | && (! ISA_HAS_64BIT_REGS (mips_opts.isa) || sizeof (maxnum) > 4)) |
252b5132 RH |
3807 | goto do_true; |
3808 | if (imm_expr.X_op != O_constant) | |
3809 | as_bad (_("Unsupported large constant")); | |
3810 | imm_expr.X_add_number++; | |
3811 | /* FALLTHROUGH */ | |
3812 | case M_BLT_I: | |
3813 | case M_BLTL_I: | |
3814 | if (mask == M_BLTL_I) | |
3815 | likely = 1; | |
3816 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
3817 | { | |
3818 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3819 | likely ? "bltzl" : "bltz", | |
3820 | "s,p", sreg); | |
3821 | return; | |
3822 | } | |
3823 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
3824 | { | |
3825 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3826 | likely ? "blezl" : "blez", | |
3827 | "s,p", sreg); | |
3828 | return; | |
3829 | } | |
3830 | set_at (&icnt, sreg, 0); | |
3831 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3832 | likely ? "bnel" : "bne", | |
3833 | "s,t,p", AT, 0); | |
3834 | break; | |
3835 | ||
3836 | case M_BLEUL: | |
3837 | likely = 1; | |
3838 | case M_BLEU: | |
3839 | if (treg == 0) | |
3840 | { | |
3841 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3842 | likely ? "beql" : "beq", | |
3843 | "s,t,p", sreg, 0); | |
3844 | return; | |
3845 | } | |
3846 | if (sreg == 0) | |
3847 | goto do_true; | |
3848 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, | |
3849 | sreg); | |
3850 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3851 | likely ? "beql" : "beq", | |
3852 | "s,t,p", AT, 0); | |
3853 | break; | |
3854 | ||
3855 | case M_BLEUL_I: | |
3856 | likely = 1; | |
3857 | case M_BLEU_I: | |
3858 | if (sreg == 0 | |
9ce8a5dd | 3859 | || (! ISA_HAS_64BIT_REGS (mips_opts.isa) |
252b5132 RH |
3860 | && imm_expr.X_op == O_constant |
3861 | && imm_expr.X_add_number == 0xffffffff)) | |
3862 | goto do_true; | |
3863 | if (imm_expr.X_op != O_constant) | |
3864 | as_bad (_("Unsupported large constant")); | |
3865 | imm_expr.X_add_number++; | |
3866 | /* FALLTHROUGH */ | |
3867 | case M_BLTU_I: | |
3868 | case M_BLTUL_I: | |
3869 | if (mask == M_BLTUL_I) | |
3870 | likely = 1; | |
3871 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
3872 | goto do_false; | |
3873 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
3874 | { | |
3875 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3876 | likely ? "beql" : "beq", | |
3877 | "s,t,p", sreg, 0); | |
3878 | return; | |
3879 | } | |
3880 | set_at (&icnt, sreg, 1); | |
3881 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3882 | likely ? "bnel" : "bne", | |
3883 | "s,t,p", AT, 0); | |
3884 | break; | |
3885 | ||
3886 | case M_BLTL: | |
3887 | likely = 1; | |
3888 | case M_BLT: | |
3889 | if (treg == 0) | |
3890 | { | |
3891 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3892 | likely ? "bltzl" : "bltz", | |
3893 | "s,p", sreg); | |
3894 | return; | |
3895 | } | |
3896 | if (sreg == 0) | |
3897 | { | |
3898 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3899 | likely ? "bgtzl" : "bgtz", | |
3900 | "s,p", treg); | |
3901 | return; | |
3902 | } | |
3903 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); | |
3904 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3905 | likely ? "bnel" : "bne", | |
3906 | "s,t,p", AT, 0); | |
3907 | break; | |
3908 | ||
3909 | case M_BLTUL: | |
3910 | likely = 1; | |
3911 | case M_BLTU: | |
3912 | if (treg == 0) | |
3913 | goto do_false; | |
3914 | if (sreg == 0) | |
3915 | { | |
3916 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3917 | likely ? "bnel" : "bne", | |
3918 | "s,t,p", 0, treg); | |
3919 | return; | |
3920 | } | |
3921 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, | |
3922 | treg); | |
3923 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
3924 | likely ? "bnel" : "bne", | |
3925 | "s,t,p", AT, 0); | |
3926 | break; | |
3927 | ||
3928 | case M_DDIV_3: | |
3929 | dbl = 1; | |
3930 | case M_DIV_3: | |
3931 | s = "mflo"; | |
3932 | goto do_div3; | |
3933 | case M_DREM_3: | |
3934 | dbl = 1; | |
3935 | case M_REM_3: | |
3936 | s = "mfhi"; | |
3937 | do_div3: | |
3938 | if (treg == 0) | |
3939 | { | |
3940 | as_warn (_("Divide by zero.")); | |
3941 | if (mips_trap) | |
3942 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
3943 | else | |
3944 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
3945 | return; | |
3946 | } | |
3947 | ||
3948 | mips_emit_delays (true); | |
3949 | ++mips_opts.noreorder; | |
3950 | mips_any_noreorder = 1; | |
3951 | if (mips_trap) | |
3952 | { | |
3953 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
3954 | macro_build ((char *) NULL, &icnt, NULL, | |
3955 | dbl ? "ddiv" : "div", | |
3956 | "z,s,t", sreg, treg); | |
3957 | } | |
3958 | else | |
3959 | { | |
3960 | expr1.X_add_number = 8; | |
3961 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
3962 | macro_build ((char *) NULL, &icnt, NULL, | |
3963 | dbl ? "ddiv" : "div", | |
3964 | "z,s,t", sreg, treg); | |
3965 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
3966 | } | |
3967 | expr1.X_add_number = -1; | |
3968 | macro_build ((char *) NULL, &icnt, &expr1, | |
3969 | dbl ? "daddiu" : "addiu", | |
3970 | "t,r,j", AT, 0, (int) BFD_RELOC_LO16); | |
3971 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); | |
3972 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT); | |
3973 | if (dbl) | |
3974 | { | |
3975 | expr1.X_add_number = 1; | |
3976 | macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0, | |
3977 | (int) BFD_RELOC_LO16); | |
3978 | macro_build ((char *) NULL, &icnt, NULL, "dsll32", "d,w,<", AT, AT, | |
3979 | 31); | |
3980 | } | |
3981 | else | |
3982 | { | |
3983 | expr1.X_add_number = 0x80000000; | |
3984 | macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT, | |
3985 | (int) BFD_RELOC_HI16); | |
3986 | } | |
3987 | if (mips_trap) | |
3988 | { | |
3989 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", sreg, AT); | |
3990 | /* We want to close the noreorder block as soon as possible, so | |
3991 | that later insns are available for delay slot filling. */ | |
3992 | --mips_opts.noreorder; | |
3993 | } | |
3994 | else | |
3995 | { | |
3996 | expr1.X_add_number = 8; | |
3997 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT); | |
3998 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
3999 | ||
4000 | /* We want to close the noreorder block as soon as possible, so | |
4001 | that later insns are available for delay slot filling. */ | |
4002 | --mips_opts.noreorder; | |
4003 | ||
4004 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
4005 | } | |
4006 | macro_build ((char *) NULL, &icnt, NULL, s, "d", dreg); | |
4007 | break; | |
4008 | ||
4009 | case M_DIV_3I: | |
4010 | s = "div"; | |
4011 | s2 = "mflo"; | |
4012 | goto do_divi; | |
4013 | case M_DIVU_3I: | |
4014 | s = "divu"; | |
4015 | s2 = "mflo"; | |
4016 | goto do_divi; | |
4017 | case M_REM_3I: | |
4018 | s = "div"; | |
4019 | s2 = "mfhi"; | |
4020 | goto do_divi; | |
4021 | case M_REMU_3I: | |
4022 | s = "divu"; | |
4023 | s2 = "mfhi"; | |
4024 | goto do_divi; | |
4025 | case M_DDIV_3I: | |
4026 | dbl = 1; | |
4027 | s = "ddiv"; | |
4028 | s2 = "mflo"; | |
4029 | goto do_divi; | |
4030 | case M_DDIVU_3I: | |
4031 | dbl = 1; | |
4032 | s = "ddivu"; | |
4033 | s2 = "mflo"; | |
4034 | goto do_divi; | |
4035 | case M_DREM_3I: | |
4036 | dbl = 1; | |
4037 | s = "ddiv"; | |
4038 | s2 = "mfhi"; | |
4039 | goto do_divi; | |
4040 | case M_DREMU_3I: | |
4041 | dbl = 1; | |
4042 | s = "ddivu"; | |
4043 | s2 = "mfhi"; | |
4044 | do_divi: | |
4045 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
4046 | { | |
4047 | as_warn (_("Divide by zero.")); | |
4048 | if (mips_trap) | |
4049 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); | |
4050 | else | |
4051 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
4052 | return; | |
4053 | } | |
4054 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) | |
4055 | { | |
4056 | if (strcmp (s2, "mflo") == 0) | |
4057 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, | |
4058 | sreg); | |
4059 | else | |
4060 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); | |
4061 | return; | |
4062 | } | |
4063 | if (imm_expr.X_op == O_constant | |
4064 | && imm_expr.X_add_number == -1 | |
4065 | && s[strlen (s) - 1] != 'u') | |
4066 | { | |
4067 | if (strcmp (s2, "mflo") == 0) | |
4068 | { | |
4069 | if (dbl) | |
4070 | macro_build ((char *) NULL, &icnt, NULL, "dneg", "d,w", dreg, | |
4071 | sreg); | |
4072 | else | |
4073 | macro_build ((char *) NULL, &icnt, NULL, "neg", "d,w", dreg, | |
4074 | sreg); | |
4075 | } | |
4076 | else | |
4077 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); | |
4078 | return; | |
4079 | } | |
4080 | ||
4081 | load_register (&icnt, AT, &imm_expr, dbl); | |
4082 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, AT); | |
4083 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); | |
4084 | break; | |
4085 | ||
4086 | case M_DIVU_3: | |
4087 | s = "divu"; | |
4088 | s2 = "mflo"; | |
4089 | goto do_divu3; | |
4090 | case M_REMU_3: | |
4091 | s = "divu"; | |
4092 | s2 = "mfhi"; | |
4093 | goto do_divu3; | |
4094 | case M_DDIVU_3: | |
4095 | s = "ddivu"; | |
4096 | s2 = "mflo"; | |
4097 | goto do_divu3; | |
4098 | case M_DREMU_3: | |
4099 | s = "ddivu"; | |
4100 | s2 = "mfhi"; | |
4101 | do_divu3: | |
4102 | mips_emit_delays (true); | |
4103 | ++mips_opts.noreorder; | |
4104 | mips_any_noreorder = 1; | |
4105 | if (mips_trap) | |
4106 | { | |
4107 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); | |
4108 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, treg); | |
4109 | /* We want to close the noreorder block as soon as possible, so | |
4110 | that later insns are available for delay slot filling. */ | |
4111 | --mips_opts.noreorder; | |
4112 | } | |
4113 | else | |
4114 | { | |
4115 | expr1.X_add_number = 8; | |
4116 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); | |
4117 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, treg); | |
4118 | ||
4119 | /* We want to close the noreorder block as soon as possible, so | |
4120 | that later insns are available for delay slot filling. */ | |
4121 | --mips_opts.noreorder; | |
4122 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); | |
4123 | } | |
4124 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); | |
4125 | return; | |
4126 | ||
4127 | case M_DLA_AB: | |
4128 | dbl = 1; | |
4129 | case M_LA_AB: | |
4130 | /* Load the address of a symbol into a register. If breg is not | |
4131 | zero, we then add a base register to it. */ | |
4132 | ||
4133 | /* When generating embedded PIC code, we permit expressions of | |
4134 | the form | |
4135 | la $4,foo-bar | |
4136 | where bar is an address in the .text section. These are used | |
4137 | when getting the addresses of functions. We don't permit | |
4138 | X_add_number to be non-zero, because if the symbol is | |
4139 | external the relaxing code needs to know that any addend is | |
4140 | purely the offset to X_op_symbol. */ | |
4141 | if (mips_pic == EMBEDDED_PIC | |
4142 | && offset_expr.X_op == O_subtract | |
4143 | && now_seg == text_section | |
49309057 | 4144 | && (symbol_constant_p (offset_expr.X_op_symbol) |
252b5132 | 4145 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == text_section |
49309057 ILT |
4146 | : (symbol_equated_p (offset_expr.X_op_symbol) |
4147 | && (S_GET_SEGMENT | |
4148 | (symbol_get_value_expression (offset_expr.X_op_symbol) | |
4149 | ->X_add_symbol) | |
252b5132 RH |
4150 | == text_section))) |
4151 | && breg == 0 | |
4152 | && offset_expr.X_add_number == 0) | |
4153 | { | |
4154 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4155 | treg, (int) BFD_RELOC_PCREL_HI16_S); | |
4156 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4157 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4158 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4159 | ? "addiu" : "daddiu"), |
4160 | "t,r,j", treg, treg, (int) BFD_RELOC_PCREL_LO16); | |
4161 | return; | |
4162 | } | |
4163 | ||
4164 | if (offset_expr.X_op != O_symbol | |
4165 | && offset_expr.X_op != O_constant) | |
4166 | { | |
4167 | as_bad (_("expression too complex")); | |
4168 | offset_expr.X_op = O_constant; | |
4169 | } | |
4170 | ||
4171 | if (treg == breg) | |
4172 | { | |
4173 | tempreg = AT; | |
4174 | used_at = 1; | |
4175 | } | |
4176 | else | |
4177 | { | |
4178 | tempreg = treg; | |
4179 | used_at = 0; | |
4180 | } | |
4181 | ||
4182 | if (offset_expr.X_op == O_constant) | |
4183 | load_register (&icnt, tempreg, &offset_expr, dbl); | |
4184 | else if (mips_pic == NO_PIC) | |
4185 | { | |
4186 | /* If this is a reference to an GP relative symbol, we want | |
4187 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
4188 | Otherwise we want | |
4189 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4190 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4191 | If we have a constant, we need two instructions anyhow, | |
4192 | so we may as well always use the latter form. */ | |
4193 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET | |
4194 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
4195 | p = NULL; | |
4196 | else | |
4197 | { | |
4198 | frag_grow (20); | |
4199 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4200 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4201 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4202 | ? "addiu" : "daddiu"), |
4203 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
4204 | p = frag_var (rs_machine_dependent, 8, 0, | |
4205 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
4206 | mips_opts.warn_about_macros), | |
4207 | offset_expr.X_add_symbol, (offsetT) 0, | |
4208 | (char *) NULL); | |
4209 | } | |
4210 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4211 | if (p != NULL) | |
4212 | p += 4; | |
4213 | macro_build (p, &icnt, &offset_expr, | |
4214 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4215 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4216 | ? "addiu" : "daddiu"), |
4217 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4218 | } | |
4219 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
4220 | { | |
4221 | /* If this is a reference to an external symbol, and there | |
4222 | is no constant, we want | |
4223 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4224 | For a local symbol, we want | |
4225 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4226 | nop | |
4227 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4228 | ||
4229 | If we have a small constant, and this is a reference to | |
4230 | an external symbol, we want | |
4231 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4232 | nop | |
4233 | addiu $tempreg,$tempreg,<constant> | |
4234 | For a local symbol, we want the same instruction | |
4235 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
4236 | addiu instruction. | |
4237 | ||
4238 | If we have a large constant, and this is a reference to | |
4239 | an external symbol, we want | |
4240 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4241 | lui $at,<hiconstant> | |
4242 | addiu $at,$at,<loconstant> | |
4243 | addu $tempreg,$tempreg,$at | |
4244 | For a local symbol, we want the same instruction | |
4245 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
4246 | addiu instruction. */ | |
4247 | expr1.X_add_number = offset_expr.X_add_number; | |
4248 | offset_expr.X_add_number = 0; | |
4249 | frag_grow (32); | |
4250 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4251 | dbl ? "ld" : "lw", | |
4252 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4253 | if (expr1.X_add_number == 0) | |
4254 | { | |
4255 | int off; | |
4256 | ||
4257 | if (breg == 0) | |
4258 | off = 0; | |
4259 | else | |
4260 | { | |
4261 | /* We're going to put in an addu instruction using | |
4262 | tempreg, so we may as well insert the nop right | |
4263 | now. */ | |
4264 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4265 | "nop", ""); | |
4266 | off = 4; | |
4267 | } | |
4268 | p = frag_var (rs_machine_dependent, 8 - off, 0, | |
4269 | RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0, | |
4270 | (breg == 0 | |
4271 | ? mips_opts.warn_about_macros | |
4272 | : 0)), | |
4273 | offset_expr.X_add_symbol, (offsetT) 0, | |
4274 | (char *) NULL); | |
4275 | if (breg == 0) | |
4276 | { | |
4277 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4278 | p += 4; | |
4279 | } | |
4280 | macro_build (p, &icnt, &expr1, | |
4281 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4282 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4283 | ? "addiu" : "daddiu"), |
4284 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4285 | /* FIXME: If breg == 0, and the next instruction uses | |
4286 | $tempreg, then if this variant case is used an extra | |
4287 | nop will be generated. */ | |
4288 | } | |
4289 | else if (expr1.X_add_number >= -0x8000 | |
4290 | && expr1.X_add_number < 0x8000) | |
4291 | { | |
4292 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4293 | "nop", ""); | |
4294 | macro_build ((char *) NULL, &icnt, &expr1, | |
4295 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4296 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4297 | ? "addiu" : "daddiu"), |
4298 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4299 | (void) frag_var (rs_machine_dependent, 0, 0, | |
4300 | RELAX_ENCODE (0, 0, -12, -4, 0, 0), | |
4301 | offset_expr.X_add_symbol, (offsetT) 0, | |
4302 | (char *) NULL); | |
4303 | } | |
4304 | else | |
4305 | { | |
4306 | int off1; | |
4307 | ||
4308 | /* If we are going to add in a base register, and the | |
4309 | target register and the base register are the same, | |
4310 | then we are using AT as a temporary register. Since | |
4311 | we want to load the constant into AT, we add our | |
4312 | current AT (from the global offset table) and the | |
4313 | register into the register now, and pretend we were | |
4314 | not using a base register. */ | |
4315 | if (breg != treg) | |
4316 | off1 = 0; | |
4317 | else | |
4318 | { | |
4319 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4320 | "nop", ""); | |
4321 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4322 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4323 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4324 | ? "addu" : "daddu"), |
4325 | "d,v,t", treg, AT, breg); | |
4326 | breg = 0; | |
4327 | tempreg = treg; | |
4328 | off1 = -8; | |
4329 | } | |
4330 | ||
4331 | /* Set mips_optimize around the lui instruction to avoid | |
4332 | inserting an unnecessary nop after the lw. */ | |
4333 | hold_mips_optimize = mips_optimize; | |
4334 | mips_optimize = 2; | |
4335 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); | |
4336 | mips_optimize = hold_mips_optimize; | |
4337 | ||
4338 | macro_build ((char *) NULL, &icnt, &expr1, | |
4339 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4340 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4341 | ? "addiu" : "daddiu"), |
4342 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); | |
4343 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4344 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4345 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4346 | ? "addu" : "daddu"), |
4347 | "d,v,t", tempreg, tempreg, AT); | |
4348 | (void) frag_var (rs_machine_dependent, 0, 0, | |
4349 | RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0), | |
4350 | offset_expr.X_add_symbol, (offsetT) 0, | |
4351 | (char *) NULL); | |
4352 | used_at = 1; | |
4353 | } | |
4354 | } | |
4355 | else if (mips_pic == SVR4_PIC) | |
4356 | { | |
4357 | int gpdel; | |
4358 | ||
4359 | /* This is the large GOT case. If this is a reference to an | |
4360 | external symbol, and there is no constant, we want | |
4361 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4362 | addu $tempreg,$tempreg,$gp | |
4363 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4364 | For a local symbol, we want | |
4365 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4366 | nop | |
4367 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
4368 | ||
4369 | If we have a small constant, and this is a reference to | |
4370 | an external symbol, we want | |
4371 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4372 | addu $tempreg,$tempreg,$gp | |
4373 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4374 | nop | |
4375 | addiu $tempreg,$tempreg,<constant> | |
4376 | For a local symbol, we want | |
4377 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4378 | nop | |
4379 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
4380 | ||
4381 | If we have a large constant, and this is a reference to | |
4382 | an external symbol, we want | |
4383 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
4384 | addu $tempreg,$tempreg,$gp | |
4385 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
4386 | lui $at,<hiconstant> | |
4387 | addiu $at,$at,<loconstant> | |
4388 | addu $tempreg,$tempreg,$at | |
4389 | For a local symbol, we want | |
4390 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4391 | lui $at,<hiconstant> | |
4392 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
4393 | addu $tempreg,$tempreg,$at | |
4394 | */ | |
4395 | expr1.X_add_number = offset_expr.X_add_number; | |
4396 | offset_expr.X_add_number = 0; | |
4397 | frag_grow (52); | |
4398 | if (reg_needs_delay (GP)) | |
4399 | gpdel = 4; | |
4400 | else | |
4401 | gpdel = 0; | |
4402 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4403 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
4404 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4405 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4406 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4407 | ? "addu" : "daddu"), |
4408 | "d,v,t", tempreg, tempreg, GP); | |
4409 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4410 | dbl ? "ld" : "lw", | |
4411 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, | |
4412 | tempreg); | |
4413 | if (expr1.X_add_number == 0) | |
4414 | { | |
4415 | int off; | |
4416 | ||
4417 | if (breg == 0) | |
4418 | off = 0; | |
4419 | else | |
4420 | { | |
4421 | /* We're going to put in an addu instruction using | |
4422 | tempreg, so we may as well insert the nop right | |
4423 | now. */ | |
4424 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4425 | "nop", ""); | |
4426 | off = 4; | |
4427 | } | |
4428 | ||
4429 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4430 | RELAX_ENCODE (12 + off, 12 + gpdel, gpdel, | |
4431 | 8 + gpdel, 0, | |
4432 | (breg == 0 | |
4433 | ? mips_opts.warn_about_macros | |
4434 | : 0)), | |
4435 | offset_expr.X_add_symbol, (offsetT) 0, | |
4436 | (char *) NULL); | |
4437 | } | |
4438 | else if (expr1.X_add_number >= -0x8000 | |
4439 | && expr1.X_add_number < 0x8000) | |
4440 | { | |
4441 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4442 | "nop", ""); | |
4443 | macro_build ((char *) NULL, &icnt, &expr1, | |
4444 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4445 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4446 | ? "addiu" : "daddiu"), |
4447 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4448 | ||
4449 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4450 | RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0, | |
4451 | (breg == 0 | |
4452 | ? mips_opts.warn_about_macros | |
4453 | : 0)), | |
4454 | offset_expr.X_add_symbol, (offsetT) 0, | |
4455 | (char *) NULL); | |
4456 | } | |
4457 | else | |
4458 | { | |
4459 | int adj, dreg; | |
4460 | ||
4461 | /* If we are going to add in a base register, and the | |
4462 | target register and the base register are the same, | |
4463 | then we are using AT as a temporary register. Since | |
4464 | we want to load the constant into AT, we add our | |
4465 | current AT (from the global offset table) and the | |
4466 | register into the register now, and pretend we were | |
4467 | not using a base register. */ | |
4468 | if (breg != treg) | |
4469 | { | |
4470 | adj = 0; | |
4471 | dreg = tempreg; | |
4472 | } | |
4473 | else | |
4474 | { | |
4475 | assert (tempreg == AT); | |
4476 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4477 | "nop", ""); | |
4478 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4479 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4480 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4481 | ? "addu" : "daddu"), |
4482 | "d,v,t", treg, AT, breg); | |
4483 | dreg = treg; | |
4484 | adj = 8; | |
4485 | } | |
4486 | ||
4487 | /* Set mips_optimize around the lui instruction to avoid | |
4488 | inserting an unnecessary nop after the lw. */ | |
4489 | hold_mips_optimize = mips_optimize; | |
4490 | mips_optimize = 2; | |
4491 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); | |
4492 | mips_optimize = hold_mips_optimize; | |
4493 | ||
4494 | macro_build ((char *) NULL, &icnt, &expr1, | |
4495 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4496 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4497 | ? "addiu" : "daddiu"), |
4498 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); | |
4499 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4500 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4501 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4502 | ? "addu" : "daddu"), |
4503 | "d,v,t", dreg, dreg, AT); | |
4504 | ||
4505 | p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0, | |
4506 | RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel, | |
4507 | 8 + gpdel, 0, | |
4508 | (breg == 0 | |
4509 | ? mips_opts.warn_about_macros | |
4510 | : 0)), | |
4511 | offset_expr.X_add_symbol, (offsetT) 0, | |
4512 | (char *) NULL); | |
4513 | ||
4514 | used_at = 1; | |
4515 | } | |
4516 | ||
4517 | if (gpdel > 0) | |
4518 | { | |
4519 | /* This is needed because this instruction uses $gp, but | |
4520 | the first instruction on the main stream does not. */ | |
4521 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4522 | p += 4; | |
4523 | } | |
4524 | macro_build (p, &icnt, &offset_expr, | |
4525 | dbl ? "ld" : "lw", | |
4526 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
4527 | p += 4; | |
4528 | if (expr1.X_add_number >= -0x8000 | |
4529 | && expr1.X_add_number < 0x8000) | |
4530 | { | |
4531 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4532 | p += 4; | |
4533 | macro_build (p, &icnt, &expr1, | |
4534 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4535 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4536 | ? "addiu" : "daddiu"), |
4537 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
4538 | /* FIXME: If add_number is 0, and there was no base | |
4539 | register, the external symbol case ended with a load, | |
4540 | so if the symbol turns out to not be external, and | |
4541 | the next instruction uses tempreg, an unnecessary nop | |
4542 | will be inserted. */ | |
4543 | } | |
4544 | else | |
4545 | { | |
4546 | if (breg == treg) | |
4547 | { | |
4548 | /* We must add in the base register now, as in the | |
4549 | external symbol case. */ | |
4550 | assert (tempreg == AT); | |
4551 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4552 | p += 4; | |
4553 | macro_build (p, &icnt, (expressionS *) NULL, | |
4554 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4555 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4556 | ? "addu" : "daddu"), |
4557 | "d,v,t", treg, AT, breg); | |
4558 | p += 4; | |
4559 | tempreg = treg; | |
4560 | /* We set breg to 0 because we have arranged to add | |
4561 | it in in both cases. */ | |
4562 | breg = 0; | |
4563 | } | |
4564 | ||
4565 | macro_build_lui (p, &icnt, &expr1, AT); | |
4566 | p += 4; | |
4567 | macro_build (p, &icnt, &expr1, | |
4568 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4569 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4570 | ? "addiu" : "daddiu"), |
4571 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); | |
4572 | p += 4; | |
4573 | macro_build (p, &icnt, (expressionS *) NULL, | |
4574 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4575 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4576 | ? "addu" : "daddu"), |
4577 | "d,v,t", tempreg, tempreg, AT); | |
4578 | p += 4; | |
4579 | } | |
4580 | } | |
4581 | else if (mips_pic == EMBEDDED_PIC) | |
4582 | { | |
4583 | /* We use | |
4584 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) | |
4585 | */ | |
4586 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4587 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4588 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4589 | ? "addiu" : "daddiu"), |
4590 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); | |
4591 | } | |
4592 | else | |
4593 | abort (); | |
4594 | ||
4595 | if (breg != 0) | |
4596 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4597 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4598 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4599 | ? "addu" : "daddu"), |
4600 | "d,v,t", treg, tempreg, breg); | |
4601 | ||
4602 | if (! used_at) | |
4603 | return; | |
4604 | ||
4605 | break; | |
4606 | ||
4607 | case M_J_A: | |
4608 | /* The j instruction may not be used in PIC code, since it | |
4609 | requires an absolute address. We convert it to a b | |
4610 | instruction. */ | |
4611 | if (mips_pic == NO_PIC) | |
4612 | macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a"); | |
4613 | else | |
4614 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); | |
4615 | return; | |
4616 | ||
4617 | /* The jal instructions must be handled as macros because when | |
4618 | generating PIC code they expand to multi-instruction | |
4619 | sequences. Normally they are simple instructions. */ | |
4620 | case M_JAL_1: | |
4621 | dreg = RA; | |
4622 | /* Fall through. */ | |
4623 | case M_JAL_2: | |
4624 | if (mips_pic == NO_PIC | |
4625 | || mips_pic == EMBEDDED_PIC) | |
4626 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", | |
4627 | "d,s", dreg, sreg); | |
4628 | else if (mips_pic == SVR4_PIC) | |
4629 | { | |
4630 | if (sreg != PIC_CALL_REG) | |
4631 | as_warn (_("MIPS PIC call to register other than $25")); | |
4632 | ||
4633 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", | |
4634 | "d,s", dreg, sreg); | |
4635 | if (mips_cprestore_offset < 0) | |
4636 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
4637 | else | |
4638 | { | |
4639 | expr1.X_add_number = mips_cprestore_offset; | |
4640 | macro_build ((char *) NULL, &icnt, &expr1, | |
4641 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4642 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4643 | ? "lw" : "ld"), |
4644 | "t,o(b)", GP, (int) BFD_RELOC_LO16, mips_frame_reg); | |
4645 | } | |
4646 | } | |
4647 | else | |
4648 | abort (); | |
4649 | ||
4650 | return; | |
4651 | ||
4652 | case M_JAL_A: | |
4653 | if (mips_pic == NO_PIC) | |
4654 | macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a"); | |
4655 | else if (mips_pic == SVR4_PIC) | |
4656 | { | |
4657 | /* If this is a reference to an external symbol, and we are | |
4658 | using a small GOT, we want | |
4659 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
4660 | nop | |
4661 | jalr $25 | |
4662 | nop | |
4663 | lw $gp,cprestore($sp) | |
4664 | The cprestore value is set using the .cprestore | |
4665 | pseudo-op. If we are using a big GOT, we want | |
4666 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
4667 | addu $25,$25,$gp | |
4668 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
4669 | nop | |
4670 | jalr $25 | |
4671 | nop | |
4672 | lw $gp,cprestore($sp) | |
4673 | If the symbol is not external, we want | |
4674 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
4675 | nop | |
4676 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
4677 | jalr $25 | |
4678 | nop | |
4679 | lw $gp,cprestore($sp) */ | |
4680 | frag_grow (40); | |
4681 | if (! mips_big_got) | |
4682 | { | |
4683 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4684 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4685 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4686 | ? "lw" : "ld"), |
4687 | "t,o(b)", PIC_CALL_REG, | |
4688 | (int) BFD_RELOC_MIPS_CALL16, GP); | |
4689 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4690 | "nop", ""); | |
4691 | p = frag_var (rs_machine_dependent, 4, 0, | |
4692 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
4693 | offset_expr.X_add_symbol, (offsetT) 0, | |
4694 | (char *) NULL); | |
4695 | } | |
4696 | else | |
4697 | { | |
4698 | int gpdel; | |
4699 | ||
4700 | if (reg_needs_delay (GP)) | |
4701 | gpdel = 4; | |
4702 | else | |
4703 | gpdel = 0; | |
4704 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
4705 | PIC_CALL_REG, (int) BFD_RELOC_MIPS_CALL_HI16); | |
4706 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4707 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4708 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4709 | ? "addu" : "daddu"), |
4710 | "d,v,t", PIC_CALL_REG, PIC_CALL_REG, GP); | |
4711 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
4712 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4713 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4714 | ? "lw" : "ld"), |
4715 | "t,o(b)", PIC_CALL_REG, | |
4716 | (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG); | |
4717 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4718 | "nop", ""); | |
4719 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
4720 | RELAX_ENCODE (16, 12 + gpdel, gpdel, 8 + gpdel, | |
4721 | 0, 0), | |
4722 | offset_expr.X_add_symbol, (offsetT) 0, | |
4723 | (char *) NULL); | |
4724 | if (gpdel > 0) | |
4725 | { | |
4726 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4727 | p += 4; | |
4728 | } | |
4729 | macro_build (p, &icnt, &offset_expr, | |
4730 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4731 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4732 | ? "lw" : "ld"), |
4733 | "t,o(b)", PIC_CALL_REG, | |
4734 | (int) BFD_RELOC_MIPS_GOT16, GP); | |
4735 | p += 4; | |
4736 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
4737 | p += 4; | |
4738 | } | |
4739 | macro_build (p, &icnt, &offset_expr, | |
4740 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4741 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4742 | ? "addiu" : "daddiu"), |
4743 | "t,r,j", PIC_CALL_REG, PIC_CALL_REG, | |
4744 | (int) BFD_RELOC_LO16); | |
4745 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4746 | "jalr", "s", PIC_CALL_REG); | |
4747 | if (mips_cprestore_offset < 0) | |
4748 | as_warn (_("No .cprestore pseudo-op used in PIC code")); | |
4749 | else | |
4750 | { | |
4751 | if (mips_opts.noreorder) | |
4752 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
4753 | "nop", ""); | |
4754 | expr1.X_add_number = mips_cprestore_offset; | |
4755 | macro_build ((char *) NULL, &icnt, &expr1, | |
4756 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 4757 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
4758 | ? "lw" : "ld"), |
4759 | "t,o(b)", GP, (int) BFD_RELOC_LO16, | |
4760 | mips_frame_reg); | |
4761 | } | |
4762 | } | |
4763 | else if (mips_pic == EMBEDDED_PIC) | |
4764 | { | |
4765 | macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p"); | |
4766 | /* The linker may expand the call to a longer sequence which | |
4767 | uses $at, so we must break rather than return. */ | |
4768 | break; | |
4769 | } | |
4770 | else | |
4771 | abort (); | |
4772 | ||
4773 | return; | |
4774 | ||
4775 | case M_LB_AB: | |
4776 | s = "lb"; | |
4777 | goto ld; | |
4778 | case M_LBU_AB: | |
4779 | s = "lbu"; | |
4780 | goto ld; | |
4781 | case M_LH_AB: | |
4782 | s = "lh"; | |
4783 | goto ld; | |
4784 | case M_LHU_AB: | |
4785 | s = "lhu"; | |
4786 | goto ld; | |
4787 | case M_LW_AB: | |
4788 | s = "lw"; | |
4789 | goto ld; | |
4790 | case M_LWC0_AB: | |
4791 | s = "lwc0"; | |
4792 | /* Itbl support may require additional care here. */ | |
4793 | coproc = 1; | |
4794 | goto ld; | |
4795 | case M_LWC1_AB: | |
4796 | s = "lwc1"; | |
4797 | /* Itbl support may require additional care here. */ | |
4798 | coproc = 1; | |
4799 | goto ld; | |
4800 | case M_LWC2_AB: | |
4801 | s = "lwc2"; | |
4802 | /* Itbl support may require additional care here. */ | |
4803 | coproc = 1; | |
4804 | goto ld; | |
4805 | case M_LWC3_AB: | |
4806 | s = "lwc3"; | |
4807 | /* Itbl support may require additional care here. */ | |
4808 | coproc = 1; | |
4809 | goto ld; | |
4810 | case M_LWL_AB: | |
4811 | s = "lwl"; | |
4812 | lr = 1; | |
4813 | goto ld; | |
4814 | case M_LWR_AB: | |
4815 | s = "lwr"; | |
4816 | lr = 1; | |
4817 | goto ld; | |
4818 | case M_LDC1_AB: | |
4819 | if (mips_cpu == 4650) | |
4820 | { | |
4821 | as_bad (_("opcode not supported on this processor")); | |
4822 | return; | |
4823 | } | |
4824 | s = "ldc1"; | |
4825 | /* Itbl support may require additional care here. */ | |
4826 | coproc = 1; | |
4827 | goto ld; | |
4828 | case M_LDC2_AB: | |
4829 | s = "ldc2"; | |
4830 | /* Itbl support may require additional care here. */ | |
4831 | coproc = 1; | |
4832 | goto ld; | |
4833 | case M_LDC3_AB: | |
4834 | s = "ldc3"; | |
4835 | /* Itbl support may require additional care here. */ | |
4836 | coproc = 1; | |
4837 | goto ld; | |
4838 | case M_LDL_AB: | |
4839 | s = "ldl"; | |
4840 | lr = 1; | |
4841 | goto ld; | |
4842 | case M_LDR_AB: | |
4843 | s = "ldr"; | |
4844 | lr = 1; | |
4845 | goto ld; | |
4846 | case M_LL_AB: | |
4847 | s = "ll"; | |
4848 | goto ld; | |
4849 | case M_LLD_AB: | |
4850 | s = "lld"; | |
4851 | goto ld; | |
4852 | case M_LWU_AB: | |
4853 | s = "lwu"; | |
4854 | ld: | |
4855 | if (breg == treg || coproc || lr) | |
4856 | { | |
4857 | tempreg = AT; | |
4858 | used_at = 1; | |
4859 | } | |
4860 | else | |
4861 | { | |
4862 | tempreg = treg; | |
4863 | used_at = 0; | |
4864 | } | |
4865 | goto ld_st; | |
4866 | case M_SB_AB: | |
4867 | s = "sb"; | |
4868 | goto st; | |
4869 | case M_SH_AB: | |
4870 | s = "sh"; | |
4871 | goto st; | |
4872 | case M_SW_AB: | |
4873 | s = "sw"; | |
4874 | goto st; | |
4875 | case M_SWC0_AB: | |
4876 | s = "swc0"; | |
4877 | /* Itbl support may require additional care here. */ | |
4878 | coproc = 1; | |
4879 | goto st; | |
4880 | case M_SWC1_AB: | |
4881 | s = "swc1"; | |
4882 | /* Itbl support may require additional care here. */ | |
4883 | coproc = 1; | |
4884 | goto st; | |
4885 | case M_SWC2_AB: | |
4886 | s = "swc2"; | |
4887 | /* Itbl support may require additional care here. */ | |
4888 | coproc = 1; | |
4889 | goto st; | |
4890 | case M_SWC3_AB: | |
4891 | s = "swc3"; | |
4892 | /* Itbl support may require additional care here. */ | |
4893 | coproc = 1; | |
4894 | goto st; | |
4895 | case M_SWL_AB: | |
4896 | s = "swl"; | |
4897 | goto st; | |
4898 | case M_SWR_AB: | |
4899 | s = "swr"; | |
4900 | goto st; | |
4901 | case M_SC_AB: | |
4902 | s = "sc"; | |
4903 | goto st; | |
4904 | case M_SCD_AB: | |
4905 | s = "scd"; | |
4906 | goto st; | |
4907 | case M_SDC1_AB: | |
4908 | if (mips_cpu == 4650) | |
4909 | { | |
4910 | as_bad (_("opcode not supported on this processor")); | |
4911 | return; | |
4912 | } | |
4913 | s = "sdc1"; | |
4914 | coproc = 1; | |
4915 | /* Itbl support may require additional care here. */ | |
4916 | goto st; | |
4917 | case M_SDC2_AB: | |
4918 | s = "sdc2"; | |
4919 | /* Itbl support may require additional care here. */ | |
4920 | coproc = 1; | |
4921 | goto st; | |
4922 | case M_SDC3_AB: | |
4923 | s = "sdc3"; | |
4924 | /* Itbl support may require additional care here. */ | |
4925 | coproc = 1; | |
4926 | goto st; | |
4927 | case M_SDL_AB: | |
4928 | s = "sdl"; | |
4929 | goto st; | |
4930 | case M_SDR_AB: | |
4931 | s = "sdr"; | |
4932 | st: | |
4933 | tempreg = AT; | |
4934 | used_at = 1; | |
4935 | ld_st: | |
4936 | /* Itbl support may require additional care here. */ | |
4937 | if (mask == M_LWC1_AB | |
4938 | || mask == M_SWC1_AB | |
4939 | || mask == M_LDC1_AB | |
4940 | || mask == M_SDC1_AB | |
4941 | || mask == M_L_DAB | |
4942 | || mask == M_S_DAB) | |
4943 | fmt = "T,o(b)"; | |
4944 | else if (coproc) | |
4945 | fmt = "E,o(b)"; | |
4946 | else | |
4947 | fmt = "t,o(b)"; | |
4948 | ||
4949 | if (offset_expr.X_op != O_constant | |
4950 | && offset_expr.X_op != O_symbol) | |
4951 | { | |
4952 | as_bad (_("expression too complex")); | |
4953 | offset_expr.X_op = O_constant; | |
4954 | } | |
4955 | ||
4956 | /* A constant expression in PIC code can be handled just as it | |
4957 | is in non PIC code. */ | |
4958 | if (mips_pic == NO_PIC | |
4959 | || offset_expr.X_op == O_constant) | |
4960 | { | |
4961 | /* If this is a reference to a GP relative symbol, and there | |
4962 | is no base register, we want | |
4963 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
4964 | Otherwise, if there is no base register, we want | |
4965 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4966 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
4967 | If we have a constant, we need two instructions anyhow, | |
4968 | so we always use the latter form. | |
4969 | ||
4970 | If we have a base register, and this is a reference to a | |
4971 | GP relative symbol, we want | |
4972 | addu $tempreg,$breg,$gp | |
4973 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
4974 | Otherwise we want | |
4975 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
4976 | addu $tempreg,$tempreg,$breg | |
4977 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) | |
4978 | With a constant we always use the latter case. */ | |
4979 | if (breg == 0) | |
4980 | { | |
4981 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET | |
4982 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
4983 | p = NULL; | |
4984 | else | |
4985 | { | |
4986 | frag_grow (20); | |
4987 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
4988 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
4989 | p = frag_var (rs_machine_dependent, 8, 0, | |
4990 | RELAX_ENCODE (4, 8, 0, 4, 0, | |
4991 | (mips_opts.warn_about_macros | |
4992 | || (used_at | |
4993 | && mips_opts.noat))), | |
4994 | offset_expr.X_add_symbol, (offsetT) 0, | |
4995 | (char *) NULL); | |
4996 | used_at = 0; | |
4997 | } | |
4998 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
4999 | if (p != NULL) | |
5000 | p += 4; | |
5001 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
5002 | (int) BFD_RELOC_LO16, tempreg); | |
5003 | } | |
5004 | else | |
5005 | { | |
5006 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET | |
5007 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
5008 | p = NULL; | |
5009 | else | |
5010 | { | |
5011 | frag_grow (28); | |
5012 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5013 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5014 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5015 | ? "addu" : "daddu"), |
5016 | "d,v,t", tempreg, breg, GP); | |
5017 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5018 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5019 | p = frag_var (rs_machine_dependent, 12, 0, | |
5020 | RELAX_ENCODE (8, 12, 0, 8, 0, 0), | |
5021 | offset_expr.X_add_symbol, (offsetT) 0, | |
5022 | (char *) NULL); | |
5023 | } | |
5024 | macro_build_lui (p, &icnt, &offset_expr, tempreg); | |
5025 | if (p != NULL) | |
5026 | p += 4; | |
5027 | macro_build (p, &icnt, (expressionS *) NULL, | |
5028 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5029 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5030 | ? "addu" : "daddu"), |
5031 | "d,v,t", tempreg, tempreg, breg); | |
5032 | if (p != NULL) | |
5033 | p += 4; | |
5034 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, | |
5035 | (int) BFD_RELOC_LO16, tempreg); | |
5036 | } | |
5037 | } | |
5038 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
5039 | { | |
5040 | /* If this is a reference to an external symbol, we want | |
5041 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5042 | nop | |
5043 | <op> $treg,0($tempreg) | |
5044 | Otherwise we want | |
5045 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5046 | nop | |
5047 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5048 | <op> $treg,0($tempreg) | |
5049 | If there is a base register, we add it to $tempreg before | |
5050 | the <op>. If there is a constant, we stick it in the | |
5051 | <op> instruction. We don't handle constants larger than | |
5052 | 16 bits, because we have no way to load the upper 16 bits | |
5053 | (actually, we could handle them for the subset of cases | |
5054 | in which we are not using $at). */ | |
5055 | assert (offset_expr.X_op == O_symbol); | |
5056 | expr1.X_add_number = offset_expr.X_add_number; | |
5057 | offset_expr.X_add_number = 0; | |
5058 | if (expr1.X_add_number < -0x8000 | |
5059 | || expr1.X_add_number >= 0x8000) | |
5060 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5061 | frag_grow (20); | |
5062 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
5063 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5064 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5065 | ? "lw" : "ld"), |
5066 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
5067 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
5068 | p = frag_var (rs_machine_dependent, 4, 0, | |
5069 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), | |
5070 | offset_expr.X_add_symbol, (offsetT) 0, | |
5071 | (char *) NULL); | |
5072 | macro_build (p, &icnt, &offset_expr, | |
5073 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5074 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5075 | ? "addiu" : "daddiu"), |
5076 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
5077 | if (breg != 0) | |
5078 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5079 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5080 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5081 | ? "addu" : "daddu"), |
5082 | "d,v,t", tempreg, tempreg, breg); | |
5083 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, | |
5084 | (int) BFD_RELOC_LO16, tempreg); | |
5085 | } | |
5086 | else if (mips_pic == SVR4_PIC) | |
5087 | { | |
5088 | int gpdel; | |
5089 | ||
5090 | /* If this is a reference to an external symbol, we want | |
5091 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5092 | addu $tempreg,$tempreg,$gp | |
5093 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
5094 | <op> $treg,0($tempreg) | |
5095 | Otherwise we want | |
5096 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5097 | nop | |
5098 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
5099 | <op> $treg,0($tempreg) | |
5100 | If there is a base register, we add it to $tempreg before | |
5101 | the <op>. If there is a constant, we stick it in the | |
5102 | <op> instruction. We don't handle constants larger than | |
5103 | 16 bits, because we have no way to load the upper 16 bits | |
5104 | (actually, we could handle them for the subset of cases | |
5105 | in which we are not using $at). */ | |
5106 | assert (offset_expr.X_op == O_symbol); | |
5107 | expr1.X_add_number = offset_expr.X_add_number; | |
5108 | offset_expr.X_add_number = 0; | |
5109 | if (expr1.X_add_number < -0x8000 | |
5110 | || expr1.X_add_number >= 0x8000) | |
5111 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5112 | if (reg_needs_delay (GP)) | |
5113 | gpdel = 4; | |
5114 | else | |
5115 | gpdel = 0; | |
5116 | frag_grow (36); | |
5117 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
5118 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); | |
5119 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5120 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5121 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5122 | ? "addu" : "daddu"), |
5123 | "d,v,t", tempreg, tempreg, GP); | |
5124 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
5125 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5126 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5127 | ? "lw" : "ld"), |
5128 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, | |
5129 | tempreg); | |
5130 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, | |
5131 | RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0), | |
5132 | offset_expr.X_add_symbol, (offsetT) 0, (char *) NULL); | |
5133 | if (gpdel > 0) | |
5134 | { | |
5135 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5136 | p += 4; | |
5137 | } | |
5138 | macro_build (p, &icnt, &offset_expr, | |
5139 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5140 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5141 | ? "lw" : "ld"), |
5142 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); | |
5143 | p += 4; | |
5144 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5145 | p += 4; | |
5146 | macro_build (p, &icnt, &offset_expr, | |
5147 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5148 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5149 | ? "addiu" : "daddiu"), |
5150 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); | |
5151 | if (breg != 0) | |
5152 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5153 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5154 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5155 | ? "addu" : "daddu"), |
5156 | "d,v,t", tempreg, tempreg, breg); | |
5157 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, | |
5158 | (int) BFD_RELOC_LO16, tempreg); | |
5159 | } | |
5160 | else if (mips_pic == EMBEDDED_PIC) | |
5161 | { | |
5162 | /* If there is no base register, we want | |
5163 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
5164 | If there is a base register, we want | |
5165 | addu $tempreg,$breg,$gp | |
5166 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) | |
5167 | */ | |
5168 | assert (offset_expr.X_op == O_symbol); | |
5169 | if (breg == 0) | |
5170 | { | |
5171 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5172 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); | |
5173 | used_at = 0; | |
5174 | } | |
5175 | else | |
5176 | { | |
5177 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5178 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5179 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5180 | ? "addu" : "daddu"), |
5181 | "d,v,t", tempreg, breg, GP); | |
5182 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5183 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5184 | } | |
5185 | } | |
5186 | else | |
5187 | abort (); | |
5188 | ||
5189 | if (! used_at) | |
5190 | return; | |
5191 | ||
5192 | break; | |
5193 | ||
5194 | case M_LI: | |
5195 | case M_LI_S: | |
5196 | load_register (&icnt, treg, &imm_expr, 0); | |
5197 | return; | |
5198 | ||
5199 | case M_DLI: | |
5200 | load_register (&icnt, treg, &imm_expr, 1); | |
5201 | return; | |
5202 | ||
5203 | case M_LI_SS: | |
5204 | if (imm_expr.X_op == O_constant) | |
5205 | { | |
5206 | load_register (&icnt, AT, &imm_expr, 0); | |
5207 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5208 | "mtc1", "t,G", AT, treg); | |
5209 | break; | |
5210 | } | |
5211 | else | |
5212 | { | |
5213 | assert (offset_expr.X_op == O_symbol | |
5214 | && strcmp (segment_name (S_GET_SEGMENT | |
5215 | (offset_expr.X_add_symbol)), | |
5216 | ".lit4") == 0 | |
5217 | && offset_expr.X_add_number == 0); | |
5218 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", | |
5219 | treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
5220 | return; | |
5221 | } | |
5222 | ||
5223 | case M_LI_D: | |
5224 | /* If we have a constant in IMM_EXPR, then in mips3 mode it is | |
5225 | the entire value, and in mips1 mode it is the high order 32 | |
5226 | bits of the value and the low order 32 bits are either zero | |
5227 | or in offset_expr. */ | |
5228 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) | |
5229 | { | |
9ce8a5dd | 5230 | if (ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5231 | load_register (&icnt, treg, &imm_expr, 1); |
5232 | else | |
5233 | { | |
5234 | int hreg, lreg; | |
5235 | ||
5236 | if (target_big_endian) | |
5237 | { | |
5238 | hreg = treg; | |
5239 | lreg = treg + 1; | |
5240 | } | |
5241 | else | |
5242 | { | |
5243 | hreg = treg + 1; | |
5244 | lreg = treg; | |
5245 | } | |
5246 | ||
5247 | if (hreg <= 31) | |
5248 | load_register (&icnt, hreg, &imm_expr, 0); | |
5249 | if (lreg <= 31) | |
5250 | { | |
5251 | if (offset_expr.X_op == O_absent) | |
5252 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", | |
5253 | lreg, 0); | |
5254 | else | |
5255 | { | |
5256 | assert (offset_expr.X_op == O_constant); | |
5257 | load_register (&icnt, lreg, &offset_expr, 0); | |
5258 | } | |
5259 | } | |
5260 | } | |
5261 | return; | |
5262 | } | |
5263 | ||
5264 | /* We know that sym is in the .rdata section. First we get the | |
5265 | upper 16 bits of the address. */ | |
5266 | if (mips_pic == NO_PIC) | |
5267 | { | |
5268 | /* FIXME: This won't work for a 64 bit address. */ | |
5269 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
5270 | } | |
5271 | else if (mips_pic == SVR4_PIC) | |
5272 | { | |
5273 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
5274 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5275 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5276 | ? "lw" : "ld"), |
5277 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
5278 | } | |
5279 | else if (mips_pic == EMBEDDED_PIC) | |
5280 | { | |
5281 | /* For embedded PIC we pick up the entire address off $gp in | |
5282 | a single instruction. */ | |
5283 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
5284 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5285 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5286 | ? "addiu" : "daddiu"), |
5287 | "t,r,j", AT, GP, (int) BFD_RELOC_MIPS_GPREL); | |
5288 | offset_expr.X_op = O_constant; | |
5289 | offset_expr.X_add_number = 0; | |
5290 | } | |
5291 | else | |
5292 | abort (); | |
5293 | ||
5294 | /* Now we load the register(s). */ | |
9ce8a5dd | 5295 | if (ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5296 | macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)", |
5297 | treg, (int) BFD_RELOC_LO16, AT); | |
5298 | else | |
5299 | { | |
5300 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", | |
5301 | treg, (int) BFD_RELOC_LO16, AT); | |
5302 | if (treg != 31) | |
5303 | { | |
5304 | /* FIXME: How in the world do we deal with the possible | |
5305 | overflow here? */ | |
5306 | offset_expr.X_add_number += 4; | |
5307 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", | |
5308 | treg + 1, (int) BFD_RELOC_LO16, AT); | |
5309 | } | |
5310 | } | |
5311 | ||
5312 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
5313 | does not become a variant frag. */ | |
5314 | frag_wane (frag_now); | |
5315 | frag_new (0); | |
5316 | ||
5317 | break; | |
5318 | ||
5319 | case M_LI_DD: | |
5320 | /* If we have a constant in IMM_EXPR, then in mips3 mode it is | |
5321 | the entire value, and in mips1 mode it is the high order 32 | |
5322 | bits of the value and the low order 32 bits are either zero | |
5323 | or in offset_expr. */ | |
5324 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) | |
5325 | { | |
9ce8a5dd GRK |
5326 | load_register (&icnt, AT, &imm_expr, ISA_HAS_64BIT_REGS (mips_opts.isa)); |
5327 | if (ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
252b5132 RH |
5328 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
5329 | "dmtc1", "t,S", AT, treg); | |
5330 | else | |
5331 | { | |
5332 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5333 | "mtc1", "t,G", AT, treg + 1); | |
5334 | if (offset_expr.X_op == O_absent) | |
5335 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5336 | "mtc1", "t,G", 0, treg); | |
5337 | else | |
5338 | { | |
5339 | assert (offset_expr.X_op == O_constant); | |
5340 | load_register (&icnt, AT, &offset_expr, 0); | |
5341 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5342 | "mtc1", "t,G", AT, treg); | |
5343 | } | |
5344 | } | |
5345 | break; | |
5346 | } | |
5347 | ||
5348 | assert (offset_expr.X_op == O_symbol | |
5349 | && offset_expr.X_add_number == 0); | |
5350 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); | |
5351 | if (strcmp (s, ".lit8") == 0) | |
5352 | { | |
9ce8a5dd | 5353 | if (mips_opts.isa != 1) |
252b5132 RH |
5354 | { |
5355 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
5356 | "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL, GP); | |
5357 | return; | |
5358 | } | |
5359 | breg = GP; | |
5360 | r = BFD_RELOC_MIPS_LITERAL; | |
5361 | goto dob; | |
5362 | } | |
5363 | else | |
5364 | { | |
5365 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); | |
5366 | if (mips_pic == SVR4_PIC) | |
5367 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
5368 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5369 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5370 | ? "lw" : "ld"), |
5371 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
5372 | else | |
5373 | { | |
5374 | /* FIXME: This won't work for a 64 bit address. */ | |
5375 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); | |
5376 | } | |
5377 | ||
9ce8a5dd | 5378 | if (mips_opts.isa != 1) |
252b5132 RH |
5379 | { |
5380 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", | |
5381 | "T,o(b)", treg, (int) BFD_RELOC_LO16, AT); | |
5382 | ||
5383 | /* To avoid confusion in tc_gen_reloc, we must ensure | |
5384 | that this does not become a variant frag. */ | |
5385 | frag_wane (frag_now); | |
5386 | frag_new (0); | |
5387 | ||
5388 | break; | |
5389 | } | |
5390 | breg = AT; | |
5391 | r = BFD_RELOC_LO16; | |
5392 | goto dob; | |
5393 | } | |
5394 | ||
5395 | case M_L_DOB: | |
5396 | if (mips_cpu == 4650) | |
5397 | { | |
5398 | as_bad (_("opcode not supported on this processor")); | |
5399 | return; | |
5400 | } | |
5401 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
5402 | to adjust when loading from memory. */ | |
5403 | r = BFD_RELOC_LO16; | |
5404 | dob: | |
9ce8a5dd | 5405 | assert (mips_opts.isa == 1); |
252b5132 RH |
5406 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
5407 | target_big_endian ? treg + 1 : treg, | |
5408 | (int) r, breg); | |
5409 | /* FIXME: A possible overflow which I don't know how to deal | |
5410 | with. */ | |
5411 | offset_expr.X_add_number += 4; | |
5412 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", | |
5413 | target_big_endian ? treg : treg + 1, | |
5414 | (int) r, breg); | |
5415 | ||
5416 | /* To avoid confusion in tc_gen_reloc, we must ensure that this | |
5417 | does not become a variant frag. */ | |
5418 | frag_wane (frag_now); | |
5419 | frag_new (0); | |
5420 | ||
5421 | if (breg != AT) | |
5422 | return; | |
5423 | break; | |
5424 | ||
5425 | case M_L_DAB: | |
5426 | /* | |
5427 | * The MIPS assembler seems to check for X_add_number not | |
5428 | * being double aligned and generating: | |
5429 | * lui at,%hi(foo+1) | |
5430 | * addu at,at,v1 | |
5431 | * addiu at,at,%lo(foo+1) | |
5432 | * lwc1 f2,0(at) | |
5433 | * lwc1 f3,4(at) | |
5434 | * But, the resulting address is the same after relocation so why | |
5435 | * generate the extra instruction? | |
5436 | */ | |
5437 | if (mips_cpu == 4650) | |
5438 | { | |
5439 | as_bad (_("opcode not supported on this processor")); | |
5440 | return; | |
5441 | } | |
5442 | /* Itbl support may require additional care here. */ | |
5443 | coproc = 1; | |
9ce8a5dd | 5444 | if (mips_opts.isa != 1) |
252b5132 RH |
5445 | { |
5446 | s = "ldc1"; | |
5447 | goto ld; | |
5448 | } | |
5449 | ||
5450 | s = "lwc1"; | |
5451 | fmt = "T,o(b)"; | |
5452 | goto ldd_std; | |
5453 | ||
5454 | case M_S_DAB: | |
5455 | if (mips_cpu == 4650) | |
5456 | { | |
5457 | as_bad (_("opcode not supported on this processor")); | |
5458 | return; | |
5459 | } | |
5460 | ||
9ce8a5dd | 5461 | if (mips_opts.isa != 1) |
252b5132 RH |
5462 | { |
5463 | s = "sdc1"; | |
5464 | goto st; | |
5465 | } | |
5466 | ||
5467 | s = "swc1"; | |
5468 | fmt = "T,o(b)"; | |
5469 | /* Itbl support may require additional care here. */ | |
5470 | coproc = 1; | |
5471 | goto ldd_std; | |
5472 | ||
5473 | case M_LD_AB: | |
9ce8a5dd | 5474 | if (ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5475 | { |
5476 | s = "ld"; | |
5477 | goto ld; | |
5478 | } | |
5479 | ||
5480 | s = "lw"; | |
5481 | fmt = "t,o(b)"; | |
5482 | goto ldd_std; | |
5483 | ||
5484 | case M_SD_AB: | |
9ce8a5dd | 5485 | if (ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5486 | { |
5487 | s = "sd"; | |
5488 | goto st; | |
5489 | } | |
5490 | ||
5491 | s = "sw"; | |
5492 | fmt = "t,o(b)"; | |
5493 | ||
5494 | ldd_std: | |
5495 | if (offset_expr.X_op != O_symbol | |
5496 | && offset_expr.X_op != O_constant) | |
5497 | { | |
5498 | as_bad (_("expression too complex")); | |
5499 | offset_expr.X_op = O_constant; | |
5500 | } | |
5501 | ||
5502 | /* Even on a big endian machine $fn comes before $fn+1. We have | |
5503 | to adjust when loading from memory. We set coproc if we must | |
5504 | load $fn+1 first. */ | |
5505 | /* Itbl support may require additional care here. */ | |
5506 | if (! target_big_endian) | |
5507 | coproc = 0; | |
5508 | ||
5509 | if (mips_pic == NO_PIC | |
5510 | || offset_expr.X_op == O_constant) | |
5511 | { | |
5512 | /* If this is a reference to a GP relative symbol, we want | |
5513 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
5514 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
5515 | If we have a base register, we use this | |
5516 | addu $at,$breg,$gp | |
5517 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
5518 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
5519 | If this is not a GP relative symbol, we want | |
5520 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
5521 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5522 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5523 | If there is a base register, we add it to $at after the | |
5524 | lui instruction. If there is a constant, we always use | |
5525 | the last case. */ | |
5526 | if ((valueT) offset_expr.X_add_number >= MAX_GPREL_OFFSET | |
5527 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
5528 | { | |
5529 | p = NULL; | |
5530 | used_at = 1; | |
5531 | } | |
5532 | else | |
5533 | { | |
5534 | int off; | |
5535 | ||
5536 | if (breg == 0) | |
5537 | { | |
5538 | frag_grow (28); | |
5539 | tempreg = GP; | |
5540 | off = 0; | |
5541 | used_at = 0; | |
5542 | } | |
5543 | else | |
5544 | { | |
5545 | frag_grow (36); | |
5546 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5547 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5548 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5549 | ? "addu" : "daddu"), |
5550 | "d,v,t", AT, breg, GP); | |
5551 | tempreg = AT; | |
5552 | off = 4; | |
5553 | used_at = 1; | |
5554 | } | |
5555 | ||
5556 | /* Itbl support may require additional care here. */ | |
5557 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5558 | coproc ? treg + 1 : treg, | |
5559 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5560 | offset_expr.X_add_number += 4; | |
5561 | ||
5562 | /* Set mips_optimize to 2 to avoid inserting an | |
5563 | undesired nop. */ | |
5564 | hold_mips_optimize = mips_optimize; | |
5565 | mips_optimize = 2; | |
5566 | /* Itbl support may require additional care here. */ | |
5567 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5568 | coproc ? treg : treg + 1, | |
5569 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5570 | mips_optimize = hold_mips_optimize; | |
5571 | ||
5572 | p = frag_var (rs_machine_dependent, 12 + off, 0, | |
5573 | RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1, | |
5574 | used_at && mips_opts.noat), | |
5575 | offset_expr.X_add_symbol, (offsetT) 0, | |
5576 | (char *) NULL); | |
5577 | ||
5578 | /* We just generated two relocs. When tc_gen_reloc | |
5579 | handles this case, it will skip the first reloc and | |
5580 | handle the second. The second reloc already has an | |
5581 | extra addend of 4, which we added above. We must | |
5582 | subtract it out, and then subtract another 4 to make | |
5583 | the first reloc come out right. The second reloc | |
5584 | will come out right because we are going to add 4 to | |
5585 | offset_expr when we build its instruction below. | |
5586 | ||
5587 | If we have a symbol, then we don't want to include | |
5588 | the offset, because it will wind up being included | |
5589 | when we generate the reloc. */ | |
5590 | ||
5591 | if (offset_expr.X_op == O_constant) | |
5592 | offset_expr.X_add_number -= 8; | |
5593 | else | |
5594 | { | |
5595 | offset_expr.X_add_number = -4; | |
5596 | offset_expr.X_op = O_constant; | |
5597 | } | |
5598 | } | |
5599 | macro_build_lui (p, &icnt, &offset_expr, AT); | |
5600 | if (p != NULL) | |
5601 | p += 4; | |
5602 | if (breg != 0) | |
5603 | { | |
5604 | macro_build (p, &icnt, (expressionS *) NULL, | |
5605 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5606 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5607 | ? "addu" : "daddu"), |
5608 | "d,v,t", AT, breg, AT); | |
5609 | if (p != NULL) | |
5610 | p += 4; | |
5611 | } | |
5612 | /* Itbl support may require additional care here. */ | |
5613 | macro_build (p, &icnt, &offset_expr, s, fmt, | |
5614 | coproc ? treg + 1 : treg, | |
5615 | (int) BFD_RELOC_LO16, AT); | |
5616 | if (p != NULL) | |
5617 | p += 4; | |
5618 | /* FIXME: How do we handle overflow here? */ | |
5619 | offset_expr.X_add_number += 4; | |
5620 | /* Itbl support may require additional care here. */ | |
5621 | macro_build (p, &icnt, &offset_expr, s, fmt, | |
5622 | coproc ? treg : treg + 1, | |
5623 | (int) BFD_RELOC_LO16, AT); | |
5624 | } | |
5625 | else if (mips_pic == SVR4_PIC && ! mips_big_got) | |
5626 | { | |
5627 | int off; | |
5628 | ||
5629 | /* If this is a reference to an external symbol, we want | |
5630 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5631 | nop | |
5632 | <op> $treg,0($at) | |
5633 | <op> $treg+1,4($at) | |
5634 | Otherwise we want | |
5635 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5636 | nop | |
5637 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5638 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5639 | If there is a base register we add it to $at before the | |
5640 | lwc1 instructions. If there is a constant we include it | |
5641 | in the lwc1 instructions. */ | |
5642 | used_at = 1; | |
5643 | expr1.X_add_number = offset_expr.X_add_number; | |
5644 | offset_expr.X_add_number = 0; | |
5645 | if (expr1.X_add_number < -0x8000 | |
5646 | || expr1.X_add_number >= 0x8000 - 4) | |
5647 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5648 | if (breg == 0) | |
5649 | off = 0; | |
5650 | else | |
5651 | off = 4; | |
5652 | frag_grow (24 + off); | |
5653 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
5654 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5655 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5656 | ? "lw" : "ld"), |
5657 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
5658 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
5659 | if (breg != 0) | |
5660 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5661 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5662 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5663 | ? "addu" : "daddu"), |
5664 | "d,v,t", AT, breg, AT); | |
5665 | /* Itbl support may require additional care here. */ | |
5666 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, | |
5667 | coproc ? treg + 1 : treg, | |
5668 | (int) BFD_RELOC_LO16, AT); | |
5669 | expr1.X_add_number += 4; | |
5670 | ||
5671 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5672 | nop. */ | |
5673 | hold_mips_optimize = mips_optimize; | |
5674 | mips_optimize = 2; | |
5675 | /* Itbl support may require additional care here. */ | |
5676 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, | |
5677 | coproc ? treg : treg + 1, | |
5678 | (int) BFD_RELOC_LO16, AT); | |
5679 | mips_optimize = hold_mips_optimize; | |
5680 | ||
5681 | (void) frag_var (rs_machine_dependent, 0, 0, | |
5682 | RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0), | |
5683 | offset_expr.X_add_symbol, (offsetT) 0, | |
5684 | (char *) NULL); | |
5685 | } | |
5686 | else if (mips_pic == SVR4_PIC) | |
5687 | { | |
5688 | int gpdel, off; | |
5689 | ||
5690 | /* If this is a reference to an external symbol, we want | |
5691 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
5692 | addu $at,$at,$gp | |
5693 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
5694 | nop | |
5695 | <op> $treg,0($at) | |
5696 | <op> $treg+1,4($at) | |
5697 | Otherwise we want | |
5698 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
5699 | nop | |
5700 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) | |
5701 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) | |
5702 | If there is a base register we add it to $at before the | |
5703 | lwc1 instructions. If there is a constant we include it | |
5704 | in the lwc1 instructions. */ | |
5705 | used_at = 1; | |
5706 | expr1.X_add_number = offset_expr.X_add_number; | |
5707 | offset_expr.X_add_number = 0; | |
5708 | if (expr1.X_add_number < -0x8000 | |
5709 | || expr1.X_add_number >= 0x8000 - 4) | |
5710 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
5711 | if (reg_needs_delay (GP)) | |
5712 | gpdel = 4; | |
5713 | else | |
5714 | gpdel = 0; | |
5715 | if (breg == 0) | |
5716 | off = 0; | |
5717 | else | |
5718 | off = 4; | |
5719 | frag_grow (56); | |
5720 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", | |
5721 | AT, (int) BFD_RELOC_MIPS_GOT_HI16); | |
5722 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5723 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5724 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5725 | ? "addu" : "daddu"), |
5726 | "d,v,t", AT, AT, GP); | |
5727 | macro_build ((char *) NULL, &icnt, &offset_expr, | |
5728 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5729 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5730 | ? "lw" : "ld"), |
5731 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT); | |
5732 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); | |
5733 | if (breg != 0) | |
5734 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5735 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5736 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5737 | ? "addu" : "daddu"), |
5738 | "d,v,t", AT, breg, AT); | |
5739 | /* Itbl support may require additional care here. */ | |
5740 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, | |
5741 | coproc ? treg + 1 : treg, | |
5742 | (int) BFD_RELOC_LO16, AT); | |
5743 | expr1.X_add_number += 4; | |
5744 | ||
5745 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5746 | nop. */ | |
5747 | hold_mips_optimize = mips_optimize; | |
5748 | mips_optimize = 2; | |
5749 | /* Itbl support may require additional care here. */ | |
5750 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, | |
5751 | coproc ? treg : treg + 1, | |
5752 | (int) BFD_RELOC_LO16, AT); | |
5753 | mips_optimize = hold_mips_optimize; | |
5754 | expr1.X_add_number -= 4; | |
5755 | ||
5756 | p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0, | |
5757 | RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel, | |
5758 | 8 + gpdel + off, 1, 0), | |
5759 | offset_expr.X_add_symbol, (offsetT) 0, | |
5760 | (char *) NULL); | |
5761 | if (gpdel > 0) | |
5762 | { | |
5763 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5764 | p += 4; | |
5765 | } | |
5766 | macro_build (p, &icnt, &offset_expr, | |
5767 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5768 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5769 | ? "lw" : "ld"), |
5770 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); | |
5771 | p += 4; | |
5772 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); | |
5773 | p += 4; | |
5774 | if (breg != 0) | |
5775 | { | |
5776 | macro_build (p, &icnt, (expressionS *) NULL, | |
5777 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5778 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5779 | ? "addu" : "daddu"), |
5780 | "d,v,t", AT, breg, AT); | |
5781 | p += 4; | |
5782 | } | |
5783 | /* Itbl support may require additional care here. */ | |
5784 | macro_build (p, &icnt, &expr1, s, fmt, | |
5785 | coproc ? treg + 1 : treg, | |
5786 | (int) BFD_RELOC_LO16, AT); | |
5787 | p += 4; | |
5788 | expr1.X_add_number += 4; | |
5789 | ||
5790 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
5791 | nop. */ | |
5792 | hold_mips_optimize = mips_optimize; | |
5793 | mips_optimize = 2; | |
5794 | /* Itbl support may require additional care here. */ | |
5795 | macro_build (p, &icnt, &expr1, s, fmt, | |
5796 | coproc ? treg : treg + 1, | |
5797 | (int) BFD_RELOC_LO16, AT); | |
5798 | mips_optimize = hold_mips_optimize; | |
5799 | } | |
5800 | else if (mips_pic == EMBEDDED_PIC) | |
5801 | { | |
5802 | /* If there is no base register, we use | |
5803 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) | |
5804 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) | |
5805 | If we have a base register, we use | |
5806 | addu $at,$breg,$gp | |
5807 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) | |
5808 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) | |
5809 | */ | |
5810 | if (breg == 0) | |
5811 | { | |
5812 | tempreg = GP; | |
5813 | used_at = 0; | |
5814 | } | |
5815 | else | |
5816 | { | |
5817 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
5818 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 5819 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
5820 | ? "addu" : "daddu"), |
5821 | "d,v,t", AT, breg, GP); | |
5822 | tempreg = AT; | |
5823 | used_at = 1; | |
5824 | } | |
5825 | ||
5826 | /* Itbl support may require additional care here. */ | |
5827 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5828 | coproc ? treg + 1 : treg, | |
5829 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5830 | offset_expr.X_add_number += 4; | |
5831 | /* Itbl support may require additional care here. */ | |
5832 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, | |
5833 | coproc ? treg : treg + 1, | |
5834 | (int) BFD_RELOC_MIPS_GPREL, tempreg); | |
5835 | } | |
5836 | else | |
5837 | abort (); | |
5838 | ||
5839 | if (! used_at) | |
5840 | return; | |
5841 | ||
5842 | break; | |
5843 | ||
5844 | case M_LD_OB: | |
5845 | s = "lw"; | |
5846 | goto sd_ob; | |
5847 | case M_SD_OB: | |
5848 | s = "sw"; | |
5849 | sd_ob: | |
9ce8a5dd GRK |
5850 | assert (bfd_arch_bits_per_address (stdoutput) == 32 |
5851 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)); | |
252b5132 RH |
5852 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
5853 | (int) BFD_RELOC_LO16, breg); | |
5854 | offset_expr.X_add_number += 4; | |
5855 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1, | |
5856 | (int) BFD_RELOC_LO16, breg); | |
5857 | return; | |
5858 | ||
5859 | /* New code added to support COPZ instructions. | |
5860 | This code builds table entries out of the macros in mip_opcodes. | |
5861 | R4000 uses interlocks to handle coproc delays. | |
5862 | Other chips (like the R3000) require nops to be inserted for delays. | |
5863 | ||
5864 | FIXME: Currently, we require that the user handle delays. | |
5865 | In order to fill delay slots for non-interlocked chips, | |
5866 | we must have a way to specify delays based on the coprocessor. | |
5867 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
5868 | What are the side-effects of the cop instruction? | |
5869 | What cache support might we have and what are its effects? | |
5870 | Both coprocessor & memory require delays. how long??? | |
5871 | What registers are read/set/modified? | |
5872 | ||
5873 | If an itbl is provided to interpret cop instructions, | |
5874 | this knowledge can be encoded in the itbl spec. */ | |
5875 | ||
5876 | case M_COP0: | |
5877 | s = "c0"; | |
5878 | goto copz; | |
5879 | case M_COP1: | |
5880 | s = "c1"; | |
5881 | goto copz; | |
5882 | case M_COP2: | |
5883 | s = "c2"; | |
5884 | goto copz; | |
5885 | case M_COP3: | |
5886 | s = "c3"; | |
5887 | copz: | |
5888 | /* For now we just do C (same as Cz). The parameter will be | |
5889 | stored in insn_opcode by mips_ip. */ | |
5890 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "C", | |
5891 | ip->insn_opcode); | |
5892 | return; | |
5893 | ||
5894 | #ifdef LOSING_COMPILER | |
5895 | default: | |
5896 | /* Try and see if this is a new itbl instruction. | |
5897 | This code builds table entries out of the macros in mip_opcodes. | |
5898 | FIXME: For now we just assemble the expression and pass it's | |
5899 | value along as a 32-bit immediate. | |
5900 | We may want to have the assembler assemble this value, | |
5901 | so that we gain the assembler's knowledge of delay slots, | |
5902 | symbols, etc. | |
5903 | Would it be more efficient to use mask (id) here? */ | |
5904 | if (itbl_have_entries | |
5905 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) | |
5906 | { | |
5907 | s = ip->insn_mo->name; | |
5908 | s2 = "cop3"; | |
5909 | coproc = ITBL_DECODE_PNUM (immed_expr);; | |
5910 | macro_build ((char *) NULL, &icnt, &immed_expr, s, "C"); | |
5911 | return; | |
5912 | } | |
5913 | macro2 (ip); | |
5914 | return; | |
5915 | } | |
5916 | if (mips_opts.noat) | |
5917 | as_warn (_("Macro used $at after \".set noat\"")); | |
5918 | } | |
5919 | ||
5920 | static void | |
5921 | macro2 (ip) | |
5922 | struct mips_cl_insn *ip; | |
5923 | { | |
5924 | register int treg, sreg, dreg, breg; | |
5925 | int tempreg; | |
5926 | int mask; | |
5927 | int icnt = 0; | |
5928 | int used_at; | |
5929 | expressionS expr1; | |
5930 | const char *s; | |
5931 | const char *s2; | |
5932 | const char *fmt; | |
5933 | int likely = 0; | |
5934 | int dbl = 0; | |
5935 | int coproc = 0; | |
5936 | int lr = 0; | |
5937 | int imm = 0; | |
5938 | int off; | |
5939 | offsetT maxnum; | |
5940 | bfd_reloc_code_real_type r; | |
5941 | char *p; | |
5942 | ||
5943 | treg = (ip->insn_opcode >> 16) & 0x1f; | |
5944 | dreg = (ip->insn_opcode >> 11) & 0x1f; | |
5945 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; | |
5946 | mask = ip->insn_mo->mask; | |
5947 | ||
5948 | expr1.X_op = O_constant; | |
5949 | expr1.X_op_symbol = NULL; | |
5950 | expr1.X_add_symbol = NULL; | |
5951 | expr1.X_add_number = 1; | |
5952 | ||
5953 | switch (mask) | |
5954 | { | |
5955 | #endif /* LOSING_COMPILER */ | |
5956 | ||
5957 | case M_DMUL: | |
5958 | dbl = 1; | |
5959 | case M_MUL: | |
5960 | macro_build ((char *) NULL, &icnt, NULL, | |
5961 | dbl ? "dmultu" : "multu", | |
5962 | "s,t", sreg, treg); | |
5963 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); | |
5964 | return; | |
5965 | ||
5966 | case M_DMUL_I: | |
5967 | dbl = 1; | |
5968 | case M_MUL_I: | |
5969 | /* The MIPS assembler some times generates shifts and adds. I'm | |
5970 | not trying to be that fancy. GCC should do this for us | |
5971 | anyway. */ | |
5972 | load_register (&icnt, AT, &imm_expr, dbl); | |
5973 | macro_build ((char *) NULL, &icnt, NULL, | |
5974 | dbl ? "dmult" : "mult", | |
5975 | "s,t", sreg, AT); | |
5976 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); | |
5977 | break; | |
5978 | ||
5979 | case M_DMULO_I: | |
5980 | dbl = 1; | |
5981 | case M_MULO_I: | |
5982 | imm = 1; | |
5983 | goto do_mulo; | |
5984 | ||
5985 | case M_DMULO: | |
5986 | dbl = 1; | |
5987 | case M_MULO: | |
5988 | do_mulo: | |
5989 | mips_emit_delays (true); | |
5990 | ++mips_opts.noreorder; | |
5991 | mips_any_noreorder = 1; | |
5992 | if (imm) | |
5993 | load_register (&icnt, AT, &imm_expr, dbl); | |
5994 | macro_build ((char *) NULL, &icnt, NULL, | |
5995 | dbl ? "dmult" : "mult", | |
5996 | "s,t", sreg, imm ? AT : treg); | |
5997 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); | |
5998 | macro_build ((char *) NULL, &icnt, NULL, | |
5999 | dbl ? "dsra32" : "sra", | |
6000 | "d,w,<", dreg, dreg, 31); | |
6001 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); | |
6002 | if (mips_trap) | |
6003 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", dreg, AT); | |
6004 | else | |
6005 | { | |
6006 | expr1.X_add_number = 8; | |
6007 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg, AT); | |
6008 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
6009 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
6010 | } | |
6011 | --mips_opts.noreorder; | |
6012 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); | |
6013 | break; | |
6014 | ||
6015 | case M_DMULOU_I: | |
6016 | dbl = 1; | |
6017 | case M_MULOU_I: | |
6018 | imm = 1; | |
6019 | goto do_mulou; | |
6020 | ||
6021 | case M_DMULOU: | |
6022 | dbl = 1; | |
6023 | case M_MULOU: | |
6024 | do_mulou: | |
6025 | mips_emit_delays (true); | |
6026 | ++mips_opts.noreorder; | |
6027 | mips_any_noreorder = 1; | |
6028 | if (imm) | |
6029 | load_register (&icnt, AT, &imm_expr, dbl); | |
6030 | macro_build ((char *) NULL, &icnt, NULL, | |
6031 | dbl ? "dmultu" : "multu", | |
6032 | "s,t", sreg, imm ? AT : treg); | |
6033 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); | |
6034 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); | |
6035 | if (mips_trap) | |
6036 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", AT, 0); | |
6037 | else | |
6038 | { | |
6039 | expr1.X_add_number = 8; | |
6040 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0); | |
6041 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); | |
6042 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); | |
6043 | } | |
6044 | --mips_opts.noreorder; | |
6045 | break; | |
6046 | ||
6047 | case M_ROL: | |
6048 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); | |
6049 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", AT, sreg, AT); | |
6050 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", dreg, sreg, | |
6051 | treg); | |
6052 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
6053 | break; | |
6054 | ||
6055 | case M_ROL_I: | |
6056 | if (imm_expr.X_op != O_constant) | |
6057 | as_bad (_("rotate count too large")); | |
6058 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", AT, sreg, | |
6059 | (int) (imm_expr.X_add_number & 0x1f)); | |
6060 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, | |
6061 | (int) ((0 - imm_expr.X_add_number) & 0x1f)); | |
6062 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
6063 | break; | |
6064 | ||
6065 | case M_ROR: | |
6066 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); | |
6067 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", AT, sreg, AT); | |
6068 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", dreg, sreg, | |
6069 | treg); | |
6070 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
6071 | break; | |
6072 | ||
6073 | case M_ROR_I: | |
6074 | if (imm_expr.X_op != O_constant) | |
6075 | as_bad (_("rotate count too large")); | |
6076 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, sreg, | |
6077 | (int) (imm_expr.X_add_number & 0x1f)); | |
6078 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", dreg, sreg, | |
6079 | (int) ((0 - imm_expr.X_add_number) & 0x1f)); | |
6080 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); | |
6081 | break; | |
6082 | ||
6083 | case M_S_DOB: | |
6084 | if (mips_cpu == 4650) | |
6085 | { | |
6086 | as_bad (_("opcode not supported on this processor")); | |
6087 | return; | |
6088 | } | |
9ce8a5dd | 6089 | assert (mips_opts.isa == 1); |
252b5132 RH |
6090 | /* Even on a big endian machine $fn comes before $fn+1. We have |
6091 | to adjust when storing to memory. */ | |
6092 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", | |
6093 | target_big_endian ? treg + 1 : treg, | |
6094 | (int) BFD_RELOC_LO16, breg); | |
6095 | offset_expr.X_add_number += 4; | |
6096 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", | |
6097 | target_big_endian ? treg : treg + 1, | |
6098 | (int) BFD_RELOC_LO16, breg); | |
6099 | return; | |
6100 | ||
6101 | case M_SEQ: | |
6102 | if (sreg == 0) | |
6103 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
6104 | treg, (int) BFD_RELOC_LO16); | |
6105 | else if (treg == 0) | |
6106 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
6107 | sreg, (int) BFD_RELOC_LO16); | |
6108 | else | |
6109 | { | |
6110 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, | |
6111 | sreg, treg); | |
6112 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
6113 | dreg, (int) BFD_RELOC_LO16); | |
6114 | } | |
6115 | return; | |
6116 | ||
6117 | case M_SEQ_I: | |
6118 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6119 | { | |
6120 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, | |
6121 | sreg, (int) BFD_RELOC_LO16); | |
6122 | return; | |
6123 | } | |
6124 | if (sreg == 0) | |
6125 | { | |
6126 | as_warn (_("Instruction %s: result is always false"), | |
6127 | ip->insn_mo->name); | |
6128 | macro_build ((char *) NULL, &icnt, NULL, "move", "d,s", dreg, 0); | |
6129 | return; | |
6130 | } | |
6131 | if (imm_expr.X_op == O_constant | |
6132 | && imm_expr.X_add_number >= 0 | |
6133 | && imm_expr.X_add_number < 0x10000) | |
6134 | { | |
6135 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, | |
6136 | sreg, (int) BFD_RELOC_LO16); | |
6137 | used_at = 0; | |
6138 | } | |
6139 | else if (imm_expr.X_op == O_constant | |
6140 | && imm_expr.X_add_number > -0x8000 | |
6141 | && imm_expr.X_add_number < 0) | |
6142 | { | |
6143 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
6144 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
6145 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 6146 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
6147 | ? "addiu" : "daddiu"), |
6148 | "t,r,j", dreg, sreg, | |
6149 | (int) BFD_RELOC_LO16); | |
6150 | used_at = 0; | |
6151 | } | |
6152 | else | |
6153 | { | |
6154 | load_register (&icnt, AT, &imm_expr, 0); | |
6155 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, | |
6156 | sreg, AT); | |
6157 | used_at = 1; | |
6158 | } | |
6159 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg, | |
6160 | (int) BFD_RELOC_LO16); | |
6161 | if (used_at) | |
6162 | break; | |
6163 | return; | |
6164 | ||
6165 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ | |
6166 | s = "slt"; | |
6167 | goto sge; | |
6168 | case M_SGEU: | |
6169 | s = "sltu"; | |
6170 | sge: | |
6171 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, sreg, treg); | |
6172 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
6173 | (int) BFD_RELOC_LO16); | |
6174 | return; | |
6175 | ||
6176 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ | |
6177 | case M_SGEU_I: | |
6178 | if (imm_expr.X_op == O_constant | |
6179 | && imm_expr.X_add_number >= -0x8000 | |
6180 | && imm_expr.X_add_number < 0x8000) | |
6181 | { | |
6182 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
6183 | mask == M_SGE_I ? "slti" : "sltiu", | |
6184 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); | |
6185 | used_at = 0; | |
6186 | } | |
6187 | else | |
6188 | { | |
6189 | load_register (&icnt, AT, &imm_expr, 0); | |
6190 | macro_build ((char *) NULL, &icnt, NULL, | |
6191 | mask == M_SGE_I ? "slt" : "sltu", | |
6192 | "d,v,t", dreg, sreg, AT); | |
6193 | used_at = 1; | |
6194 | } | |
6195 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
6196 | (int) BFD_RELOC_LO16); | |
6197 | if (used_at) | |
6198 | break; | |
6199 | return; | |
6200 | ||
6201 | case M_SGT: /* sreg > treg <==> treg < sreg */ | |
6202 | s = "slt"; | |
6203 | goto sgt; | |
6204 | case M_SGTU: | |
6205 | s = "sltu"; | |
6206 | sgt: | |
6207 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); | |
6208 | return; | |
6209 | ||
6210 | case M_SGT_I: /* sreg > I <==> I < sreg */ | |
6211 | s = "slt"; | |
6212 | goto sgti; | |
6213 | case M_SGTU_I: | |
6214 | s = "sltu"; | |
6215 | sgti: | |
6216 | load_register (&icnt, AT, &imm_expr, 0); | |
6217 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); | |
6218 | break; | |
6219 | ||
6220 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ | |
6221 | s = "slt"; | |
6222 | goto sle; | |
6223 | case M_SLEU: | |
6224 | s = "sltu"; | |
6225 | sle: | |
6226 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); | |
6227 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
6228 | (int) BFD_RELOC_LO16); | |
6229 | return; | |
6230 | ||
6231 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ | |
6232 | s = "slt"; | |
6233 | goto slei; | |
6234 | case M_SLEU_I: | |
6235 | s = "sltu"; | |
6236 | slei: | |
6237 | load_register (&icnt, AT, &imm_expr, 0); | |
6238 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); | |
6239 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, | |
6240 | (int) BFD_RELOC_LO16); | |
6241 | break; | |
6242 | ||
6243 | case M_SLT_I: | |
6244 | if (imm_expr.X_op == O_constant | |
6245 | && imm_expr.X_add_number >= -0x8000 | |
6246 | && imm_expr.X_add_number < 0x8000) | |
6247 | { | |
6248 | macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j", | |
6249 | dreg, sreg, (int) BFD_RELOC_LO16); | |
6250 | return; | |
6251 | } | |
6252 | load_register (&icnt, AT, &imm_expr, 0); | |
6253 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", dreg, sreg, AT); | |
6254 | break; | |
6255 | ||
6256 | case M_SLTU_I: | |
6257 | if (imm_expr.X_op == O_constant | |
6258 | && imm_expr.X_add_number >= -0x8000 | |
6259 | && imm_expr.X_add_number < 0x8000) | |
6260 | { | |
6261 | macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j", | |
6262 | dreg, sreg, (int) BFD_RELOC_LO16); | |
6263 | return; | |
6264 | } | |
6265 | load_register (&icnt, AT, &imm_expr, 0); | |
6266 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, sreg, | |
6267 | AT); | |
6268 | break; | |
6269 | ||
6270 | case M_SNE: | |
6271 | if (sreg == 0) | |
6272 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, | |
6273 | treg); | |
6274 | else if (treg == 0) | |
6275 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, | |
6276 | sreg); | |
6277 | else | |
6278 | { | |
6279 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, | |
6280 | sreg, treg); | |
6281 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, | |
6282 | dreg); | |
6283 | } | |
6284 | return; | |
6285 | ||
6286 | case M_SNE_I: | |
6287 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) | |
6288 | { | |
6289 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, | |
6290 | sreg); | |
6291 | return; | |
6292 | } | |
6293 | if (sreg == 0) | |
6294 | { | |
6295 | as_warn (_("Instruction %s: result is always true"), | |
6296 | ip->insn_mo->name); | |
6297 | macro_build ((char *) NULL, &icnt, &expr1, | |
6298 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 6299 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
6300 | ? "addiu" : "daddiu"), |
6301 | "t,r,j", dreg, 0, (int) BFD_RELOC_LO16); | |
6302 | return; | |
6303 | } | |
6304 | if (imm_expr.X_op == O_constant | |
6305 | && imm_expr.X_add_number >= 0 | |
6306 | && imm_expr.X_add_number < 0x10000) | |
6307 | { | |
6308 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", | |
6309 | dreg, sreg, (int) BFD_RELOC_LO16); | |
6310 | used_at = 0; | |
6311 | } | |
6312 | else if (imm_expr.X_op == O_constant | |
6313 | && imm_expr.X_add_number > -0x8000 | |
6314 | && imm_expr.X_add_number < 0) | |
6315 | { | |
6316 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
6317 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
6318 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 6319 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
6320 | ? "addiu" : "daddiu"), |
6321 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); | |
6322 | used_at = 0; | |
6323 | } | |
6324 | else | |
6325 | { | |
6326 | load_register (&icnt, AT, &imm_expr, 0); | |
6327 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, | |
6328 | sreg, AT); | |
6329 | used_at = 1; | |
6330 | } | |
6331 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg); | |
6332 | if (used_at) | |
6333 | break; | |
6334 | return; | |
6335 | ||
6336 | case M_DSUB_I: | |
6337 | dbl = 1; | |
6338 | case M_SUB_I: | |
6339 | if (imm_expr.X_op == O_constant | |
6340 | && imm_expr.X_add_number > -0x8000 | |
6341 | && imm_expr.X_add_number <= 0x8000) | |
6342 | { | |
6343 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
6344 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
6345 | dbl ? "daddi" : "addi", | |
6346 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); | |
6347 | return; | |
6348 | } | |
6349 | load_register (&icnt, AT, &imm_expr, dbl); | |
6350 | macro_build ((char *) NULL, &icnt, NULL, | |
6351 | dbl ? "dsub" : "sub", | |
6352 | "d,v,t", dreg, sreg, AT); | |
6353 | break; | |
6354 | ||
6355 | case M_DSUBU_I: | |
6356 | dbl = 1; | |
6357 | case M_SUBU_I: | |
6358 | if (imm_expr.X_op == O_constant | |
6359 | && imm_expr.X_add_number > -0x8000 | |
6360 | && imm_expr.X_add_number <= 0x8000) | |
6361 | { | |
6362 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
6363 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
6364 | dbl ? "daddiu" : "addiu", | |
6365 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); | |
6366 | return; | |
6367 | } | |
6368 | load_register (&icnt, AT, &imm_expr, dbl); | |
6369 | macro_build ((char *) NULL, &icnt, NULL, | |
6370 | dbl ? "dsubu" : "subu", | |
6371 | "d,v,t", dreg, sreg, AT); | |
6372 | break; | |
6373 | ||
6374 | case M_TEQ_I: | |
6375 | s = "teq"; | |
6376 | goto trap; | |
6377 | case M_TGE_I: | |
6378 | s = "tge"; | |
6379 | goto trap; | |
6380 | case M_TGEU_I: | |
6381 | s = "tgeu"; | |
6382 | goto trap; | |
6383 | case M_TLT_I: | |
6384 | s = "tlt"; | |
6385 | goto trap; | |
6386 | case M_TLTU_I: | |
6387 | s = "tltu"; | |
6388 | goto trap; | |
6389 | case M_TNE_I: | |
6390 | s = "tne"; | |
6391 | trap: | |
6392 | load_register (&icnt, AT, &imm_expr, 0); | |
6393 | macro_build ((char *) NULL, &icnt, NULL, s, "s,t", sreg, AT); | |
6394 | break; | |
6395 | ||
6396 | case M_TRUNCWD: | |
6397 | case M_TRUNCWS: | |
9ce8a5dd | 6398 | assert (mips_opts.isa == 1); |
252b5132 RH |
6399 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
6400 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ | |
6401 | ||
6402 | /* | |
6403 | * Is the double cfc1 instruction a bug in the mips assembler; | |
6404 | * or is there a reason for it? | |
6405 | */ | |
6406 | mips_emit_delays (true); | |
6407 | ++mips_opts.noreorder; | |
6408 | mips_any_noreorder = 1; | |
6409 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
6410 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); | |
6411 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
6412 | expr1.X_add_number = 3; | |
6413 | macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg, | |
6414 | (int) BFD_RELOC_LO16); | |
6415 | expr1.X_add_number = 2; | |
6416 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT, | |
6417 | (int) BFD_RELOC_LO16); | |
6418 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", AT, 31); | |
6419 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
6420 | macro_build ((char *) NULL, &icnt, NULL, | |
6421 | mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg); | |
6422 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", treg, 31); | |
6423 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); | |
6424 | --mips_opts.noreorder; | |
6425 | break; | |
6426 | ||
6427 | case M_ULH: | |
6428 | s = "lb"; | |
6429 | goto ulh; | |
6430 | case M_ULHU: | |
6431 | s = "lbu"; | |
6432 | ulh: | |
6433 | if (offset_expr.X_add_number >= 0x7fff) | |
6434 | as_bad (_("operand overflow")); | |
6435 | /* avoid load delay */ | |
6436 | if (! target_big_endian) | |
6437 | offset_expr.X_add_number += 1; | |
6438 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
6439 | (int) BFD_RELOC_LO16, breg); | |
6440 | if (! target_big_endian) | |
6441 | offset_expr.X_add_number -= 1; | |
6442 | else | |
6443 | offset_expr.X_add_number += 1; | |
6444 | macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT, | |
6445 | (int) BFD_RELOC_LO16, breg); | |
6446 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8); | |
6447 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT); | |
6448 | break; | |
6449 | ||
6450 | case M_ULD: | |
6451 | s = "ldl"; | |
6452 | s2 = "ldr"; | |
6453 | off = 7; | |
6454 | goto ulw; | |
6455 | case M_ULW: | |
6456 | s = "lwl"; | |
6457 | s2 = "lwr"; | |
6458 | off = 3; | |
6459 | ulw: | |
6460 | if (offset_expr.X_add_number >= 0x8000 - off) | |
6461 | as_bad (_("operand overflow")); | |
6462 | if (! target_big_endian) | |
6463 | offset_expr.X_add_number += off; | |
6464 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
6465 | (int) BFD_RELOC_LO16, breg); | |
6466 | if (! target_big_endian) | |
6467 | offset_expr.X_add_number -= off; | |
6468 | else | |
6469 | offset_expr.X_add_number += off; | |
6470 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
6471 | (int) BFD_RELOC_LO16, breg); | |
6472 | return; | |
6473 | ||
6474 | case M_ULD_A: | |
6475 | s = "ldl"; | |
6476 | s2 = "ldr"; | |
6477 | off = 7; | |
6478 | goto ulwa; | |
6479 | case M_ULW_A: | |
6480 | s = "lwl"; | |
6481 | s2 = "lwr"; | |
6482 | off = 3; | |
6483 | ulwa: | |
6484 | load_address (&icnt, AT, &offset_expr); | |
6485 | if (breg != 0) | |
6486 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6487 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 6488 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
6489 | ? "addu" : "daddu"), |
6490 | "d,v,t", AT, AT, breg); | |
6491 | if (! target_big_endian) | |
6492 | expr1.X_add_number = off; | |
6493 | else | |
6494 | expr1.X_add_number = 0; | |
6495 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
6496 | (int) BFD_RELOC_LO16, AT); | |
6497 | if (! target_big_endian) | |
6498 | expr1.X_add_number = 0; | |
6499 | else | |
6500 | expr1.X_add_number = off; | |
6501 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
6502 | (int) BFD_RELOC_LO16, AT); | |
6503 | break; | |
6504 | ||
6505 | case M_ULH_A: | |
6506 | case M_ULHU_A: | |
6507 | load_address (&icnt, AT, &offset_expr); | |
6508 | if (breg != 0) | |
6509 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6510 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 6511 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
6512 | ? "addu" : "daddu"), |
6513 | "d,v,t", AT, AT, breg); | |
6514 | if (target_big_endian) | |
6515 | expr1.X_add_number = 0; | |
6516 | macro_build ((char *) NULL, &icnt, &expr1, | |
6517 | mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg, | |
6518 | (int) BFD_RELOC_LO16, AT); | |
6519 | if (target_big_endian) | |
6520 | expr1.X_add_number = 1; | |
6521 | else | |
6522 | expr1.X_add_number = 0; | |
6523 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
6524 | (int) BFD_RELOC_LO16, AT); | |
6525 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, | |
6526 | treg, 8); | |
6527 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
6528 | treg, AT); | |
6529 | break; | |
6530 | ||
6531 | case M_USH: | |
6532 | if (offset_expr.X_add_number >= 0x7fff) | |
6533 | as_bad (_("operand overflow")); | |
6534 | if (target_big_endian) | |
6535 | offset_expr.X_add_number += 1; | |
6536 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg, | |
6537 | (int) BFD_RELOC_LO16, breg); | |
6538 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, treg, 8); | |
6539 | if (target_big_endian) | |
6540 | offset_expr.X_add_number -= 1; | |
6541 | else | |
6542 | offset_expr.X_add_number += 1; | |
6543 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT, | |
6544 | (int) BFD_RELOC_LO16, breg); | |
6545 | break; | |
6546 | ||
6547 | case M_USD: | |
6548 | s = "sdl"; | |
6549 | s2 = "sdr"; | |
6550 | off = 7; | |
6551 | goto usw; | |
6552 | case M_USW: | |
6553 | s = "swl"; | |
6554 | s2 = "swr"; | |
6555 | off = 3; | |
6556 | usw: | |
6557 | if (offset_expr.X_add_number >= 0x8000 - off) | |
6558 | as_bad (_("operand overflow")); | |
6559 | if (! target_big_endian) | |
6560 | offset_expr.X_add_number += off; | |
6561 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, | |
6562 | (int) BFD_RELOC_LO16, breg); | |
6563 | if (! target_big_endian) | |
6564 | offset_expr.X_add_number -= off; | |
6565 | else | |
6566 | offset_expr.X_add_number += off; | |
6567 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, | |
6568 | (int) BFD_RELOC_LO16, breg); | |
6569 | return; | |
6570 | ||
6571 | case M_USD_A: | |
6572 | s = "sdl"; | |
6573 | s2 = "sdr"; | |
6574 | off = 7; | |
6575 | goto uswa; | |
6576 | case M_USW_A: | |
6577 | s = "swl"; | |
6578 | s2 = "swr"; | |
6579 | off = 3; | |
6580 | uswa: | |
6581 | load_address (&icnt, AT, &offset_expr); | |
6582 | if (breg != 0) | |
6583 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6584 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 6585 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
6586 | ? "addu" : "daddu"), |
6587 | "d,v,t", AT, AT, breg); | |
6588 | if (! target_big_endian) | |
6589 | expr1.X_add_number = off; | |
6590 | else | |
6591 | expr1.X_add_number = 0; | |
6592 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, | |
6593 | (int) BFD_RELOC_LO16, AT); | |
6594 | if (! target_big_endian) | |
6595 | expr1.X_add_number = 0; | |
6596 | else | |
6597 | expr1.X_add_number = off; | |
6598 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, | |
6599 | (int) BFD_RELOC_LO16, AT); | |
6600 | break; | |
6601 | ||
6602 | case M_USH_A: | |
6603 | load_address (&icnt, AT, &offset_expr); | |
6604 | if (breg != 0) | |
6605 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6606 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 6607 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
6608 | ? "addu" : "daddu"), |
6609 | "d,v,t", AT, AT, breg); | |
6610 | if (! target_big_endian) | |
6611 | expr1.X_add_number = 0; | |
6612 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
6613 | (int) BFD_RELOC_LO16, AT); | |
6614 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", treg, | |
6615 | treg, 8); | |
6616 | if (! target_big_endian) | |
6617 | expr1.X_add_number = 1; | |
6618 | else | |
6619 | expr1.X_add_number = 0; | |
6620 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, | |
6621 | (int) BFD_RELOC_LO16, AT); | |
6622 | if (! target_big_endian) | |
6623 | expr1.X_add_number = 0; | |
6624 | else | |
6625 | expr1.X_add_number = 1; | |
6626 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, | |
6627 | (int) BFD_RELOC_LO16, AT); | |
6628 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, | |
6629 | treg, 8); | |
6630 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, | |
6631 | treg, AT); | |
6632 | break; | |
6633 | ||
6634 | default: | |
6635 | /* FIXME: Check if this is one of the itbl macros, since they | |
6636 | are added dynamically. */ | |
6637 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); | |
6638 | break; | |
6639 | } | |
6640 | if (mips_opts.noat) | |
6641 | as_warn (_("Macro used $at after \".set noat\"")); | |
6642 | } | |
6643 | ||
6644 | /* Implement macros in mips16 mode. */ | |
6645 | ||
6646 | static void | |
6647 | mips16_macro (ip) | |
6648 | struct mips_cl_insn *ip; | |
6649 | { | |
6650 | int mask; | |
6651 | int xreg, yreg, zreg, tmp; | |
6652 | int icnt; | |
6653 | expressionS expr1; | |
6654 | int dbl; | |
6655 | const char *s, *s2, *s3; | |
6656 | ||
6657 | mask = ip->insn_mo->mask; | |
6658 | ||
6659 | xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; | |
6660 | yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY; | |
6661 | zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; | |
6662 | ||
6663 | icnt = 0; | |
6664 | ||
6665 | expr1.X_op = O_constant; | |
6666 | expr1.X_op_symbol = NULL; | |
6667 | expr1.X_add_symbol = NULL; | |
6668 | expr1.X_add_number = 1; | |
6669 | ||
6670 | dbl = 0; | |
6671 | ||
6672 | switch (mask) | |
6673 | { | |
6674 | default: | |
6675 | internalError (); | |
6676 | ||
6677 | case M_DDIV_3: | |
6678 | dbl = 1; | |
6679 | case M_DIV_3: | |
6680 | s = "mflo"; | |
6681 | goto do_div3; | |
6682 | case M_DREM_3: | |
6683 | dbl = 1; | |
6684 | case M_REM_3: | |
6685 | s = "mfhi"; | |
6686 | do_div3: | |
6687 | mips_emit_delays (true); | |
6688 | ++mips_opts.noreorder; | |
6689 | mips_any_noreorder = 1; | |
6690 | macro_build ((char *) NULL, &icnt, NULL, | |
6691 | dbl ? "ddiv" : "div", | |
6692 | "0,x,y", xreg, yreg); | |
6693 | expr1.X_add_number = 2; | |
6694 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); | |
6695 | macro_build ((char *) NULL, &icnt, NULL, "break", "6", 7); | |
6696 | ||
6697 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, | |
6698 | since that causes an overflow. We should do that as well, | |
6699 | but I don't see how to do the comparisons without a temporary | |
6700 | register. */ | |
6701 | --mips_opts.noreorder; | |
6702 | macro_build ((char *) NULL, &icnt, NULL, s, "x", zreg); | |
6703 | break; | |
6704 | ||
6705 | case M_DIVU_3: | |
6706 | s = "divu"; | |
6707 | s2 = "mflo"; | |
6708 | goto do_divu3; | |
6709 | case M_REMU_3: | |
6710 | s = "divu"; | |
6711 | s2 = "mfhi"; | |
6712 | goto do_divu3; | |
6713 | case M_DDIVU_3: | |
6714 | s = "ddivu"; | |
6715 | s2 = "mflo"; | |
6716 | goto do_divu3; | |
6717 | case M_DREMU_3: | |
6718 | s = "ddivu"; | |
6719 | s2 = "mfhi"; | |
6720 | do_divu3: | |
6721 | mips_emit_delays (true); | |
6722 | ++mips_opts.noreorder; | |
6723 | mips_any_noreorder = 1; | |
6724 | macro_build ((char *) NULL, &icnt, NULL, s, "0,x,y", xreg, yreg); | |
6725 | expr1.X_add_number = 2; | |
6726 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); | |
6727 | macro_build ((char *) NULL, &icnt, NULL, "break", "6", 7); | |
6728 | --mips_opts.noreorder; | |
6729 | macro_build ((char *) NULL, &icnt, NULL, s2, "x", zreg); | |
6730 | break; | |
6731 | ||
6732 | case M_DMUL: | |
6733 | dbl = 1; | |
6734 | case M_MUL: | |
6735 | macro_build ((char *) NULL, &icnt, NULL, | |
6736 | dbl ? "dmultu" : "multu", | |
6737 | "x,y", xreg, yreg); | |
6738 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "x", zreg); | |
6739 | return; | |
6740 | ||
6741 | case M_DSUBU_I: | |
6742 | dbl = 1; | |
6743 | goto do_subu; | |
6744 | case M_SUBU_I: | |
6745 | do_subu: | |
6746 | if (imm_expr.X_op != O_constant) | |
6747 | as_bad (_("Unsupported large constant")); | |
6748 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
6749 | macro_build ((char *) NULL, &icnt, &imm_expr, | |
6750 | dbl ? "daddiu" : "addiu", | |
6751 | "y,x,4", yreg, xreg); | |
6752 | break; | |
6753 | ||
6754 | case M_SUBU_I_2: | |
6755 | if (imm_expr.X_op != O_constant) | |
6756 | as_bad (_("Unsupported large constant")); | |
6757 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
6758 | macro_build ((char *) NULL, &icnt, &imm_expr, "addiu", | |
6759 | "x,k", xreg); | |
6760 | break; | |
6761 | ||
6762 | case M_DSUBU_I_2: | |
6763 | if (imm_expr.X_op != O_constant) | |
6764 | as_bad (_("Unsupported large constant")); | |
6765 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
6766 | macro_build ((char *) NULL, &icnt, &imm_expr, "daddiu", | |
6767 | "y,j", yreg); | |
6768 | break; | |
6769 | ||
6770 | case M_BEQ: | |
6771 | s = "cmp"; | |
6772 | s2 = "bteqz"; | |
6773 | goto do_branch; | |
6774 | case M_BNE: | |
6775 | s = "cmp"; | |
6776 | s2 = "btnez"; | |
6777 | goto do_branch; | |
6778 | case M_BLT: | |
6779 | s = "slt"; | |
6780 | s2 = "btnez"; | |
6781 | goto do_branch; | |
6782 | case M_BLTU: | |
6783 | s = "sltu"; | |
6784 | s2 = "btnez"; | |
6785 | goto do_branch; | |
6786 | case M_BLE: | |
6787 | s = "slt"; | |
6788 | s2 = "bteqz"; | |
6789 | goto do_reverse_branch; | |
6790 | case M_BLEU: | |
6791 | s = "sltu"; | |
6792 | s2 = "bteqz"; | |
6793 | goto do_reverse_branch; | |
6794 | case M_BGE: | |
6795 | s = "slt"; | |
6796 | s2 = "bteqz"; | |
6797 | goto do_branch; | |
6798 | case M_BGEU: | |
6799 | s = "sltu"; | |
6800 | s2 = "bteqz"; | |
6801 | goto do_branch; | |
6802 | case M_BGT: | |
6803 | s = "slt"; | |
6804 | s2 = "btnez"; | |
6805 | goto do_reverse_branch; | |
6806 | case M_BGTU: | |
6807 | s = "sltu"; | |
6808 | s2 = "btnez"; | |
6809 | ||
6810 | do_reverse_branch: | |
6811 | tmp = xreg; | |
6812 | xreg = yreg; | |
6813 | yreg = tmp; | |
6814 | ||
6815 | do_branch: | |
6816 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x,y", | |
6817 | xreg, yreg); | |
6818 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
6819 | break; | |
6820 | ||
6821 | case M_BEQ_I: | |
6822 | s = "cmpi"; | |
6823 | s2 = "bteqz"; | |
6824 | s3 = "x,U"; | |
6825 | goto do_branch_i; | |
6826 | case M_BNE_I: | |
6827 | s = "cmpi"; | |
6828 | s2 = "btnez"; | |
6829 | s3 = "x,U"; | |
6830 | goto do_branch_i; | |
6831 | case M_BLT_I: | |
6832 | s = "slti"; | |
6833 | s2 = "btnez"; | |
6834 | s3 = "x,8"; | |
6835 | goto do_branch_i; | |
6836 | case M_BLTU_I: | |
6837 | s = "sltiu"; | |
6838 | s2 = "btnez"; | |
6839 | s3 = "x,8"; | |
6840 | goto do_branch_i; | |
6841 | case M_BLE_I: | |
6842 | s = "slti"; | |
6843 | s2 = "btnez"; | |
6844 | s3 = "x,8"; | |
6845 | goto do_addone_branch_i; | |
6846 | case M_BLEU_I: | |
6847 | s = "sltiu"; | |
6848 | s2 = "btnez"; | |
6849 | s3 = "x,8"; | |
6850 | goto do_addone_branch_i; | |
6851 | case M_BGE_I: | |
6852 | s = "slti"; | |
6853 | s2 = "bteqz"; | |
6854 | s3 = "x,8"; | |
6855 | goto do_branch_i; | |
6856 | case M_BGEU_I: | |
6857 | s = "sltiu"; | |
6858 | s2 = "bteqz"; | |
6859 | s3 = "x,8"; | |
6860 | goto do_branch_i; | |
6861 | case M_BGT_I: | |
6862 | s = "slti"; | |
6863 | s2 = "bteqz"; | |
6864 | s3 = "x,8"; | |
6865 | goto do_addone_branch_i; | |
6866 | case M_BGTU_I: | |
6867 | s = "sltiu"; | |
6868 | s2 = "bteqz"; | |
6869 | s3 = "x,8"; | |
6870 | ||
6871 | do_addone_branch_i: | |
6872 | if (imm_expr.X_op != O_constant) | |
6873 | as_bad (_("Unsupported large constant")); | |
6874 | ++imm_expr.X_add_number; | |
6875 | ||
6876 | do_branch_i: | |
6877 | macro_build ((char *) NULL, &icnt, &imm_expr, s, s3, xreg); | |
6878 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); | |
6879 | break; | |
6880 | ||
6881 | case M_ABS: | |
6882 | expr1.X_add_number = 0; | |
6883 | macro_build ((char *) NULL, &icnt, &expr1, "slti", "x,8", yreg); | |
6884 | if (xreg != yreg) | |
6885 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6886 | "move", "y,X", xreg, yreg); | |
6887 | expr1.X_add_number = 2; | |
6888 | macro_build ((char *) NULL, &icnt, &expr1, "bteqz", "p"); | |
6889 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
6890 | "neg", "x,w", xreg, xreg); | |
6891 | } | |
6892 | } | |
6893 | ||
6894 | /* For consistency checking, verify that all bits are specified either | |
6895 | by the match/mask part of the instruction definition, or by the | |
6896 | operand list. */ | |
6897 | static int | |
6898 | validate_mips_insn (opc) | |
6899 | const struct mips_opcode *opc; | |
6900 | { | |
6901 | const char *p = opc->args; | |
6902 | char c; | |
6903 | unsigned long used_bits = opc->mask; | |
6904 | ||
6905 | if ((used_bits & opc->match) != opc->match) | |
6906 | { | |
6907 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
6908 | opc->name, opc->args); | |
6909 | return 0; | |
6910 | } | |
6911 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) | |
6912 | while (*p) | |
6913 | switch (c = *p++) | |
6914 | { | |
6915 | case ',': break; | |
6916 | case '(': break; | |
6917 | case ')': break; | |
6918 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
6919 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
6920 | case 'A': break; | |
6921 | case 'B': USE_BITS (OP_MASK_SYSCALL, OP_SH_SYSCALL); break; | |
6922 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; | |
6923 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; | |
6924 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
6925 | case 'F': break; | |
6926 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
6927 | case 'I': break; | |
6928 | case 'L': break; | |
6929 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; | |
6930 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; | |
6931 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; | |
6932 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
6933 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
6934 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; | |
6935 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; | |
6936 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; | |
6937 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
6938 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; | |
6939 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
6940 | case 'f': break; | |
6941 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; | |
6942 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
6943 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
6944 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; | |
6945 | case 'l': break; | |
6946 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
6947 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; | |
6948 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; | |
6949 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
6950 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
6951 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
6952 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; | |
6953 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; | |
6954 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; | |
6955 | case 'x': break; | |
6956 | case 'z': break; | |
6957 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; | |
6958 | default: | |
6959 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), | |
6960 | c, opc->name, opc->args); | |
6961 | return 0; | |
6962 | } | |
6963 | #undef USE_BITS | |
6964 | if (used_bits != 0xffffffff) | |
6965 | { | |
6966 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), | |
6967 | ~used_bits & 0xffffffff, opc->name, opc->args); | |
6968 | return 0; | |
6969 | } | |
6970 | return 1; | |
6971 | } | |
6972 | ||
6973 | /* This routine assembles an instruction into its binary format. As a | |
6974 | side effect, it sets one of the global variables imm_reloc or | |
6975 | offset_reloc to the type of relocation to do if one of the operands | |
6976 | is an address expression. */ | |
6977 | ||
6978 | static void | |
6979 | mips_ip (str, ip) | |
6980 | char *str; | |
6981 | struct mips_cl_insn *ip; | |
6982 | { | |
6983 | char *s; | |
6984 | const char *args; | |
6985 | char c; | |
6986 | struct mips_opcode *insn; | |
6987 | char *argsStart; | |
6988 | unsigned int regno; | |
6989 | unsigned int lastregno = 0; | |
6990 | char *s_reset; | |
6991 | char save_c = 0; | |
6992 | int full_opcode_match = 1; | |
6993 | ||
6994 | insn_error = NULL; | |
6995 | ||
6996 | /* If the instruction contains a '.', we first try to match an instruction | |
6997 | including the '.'. Then we try again without the '.'. */ | |
6998 | insn = NULL; | |
d9a62219 | 6999 | for (s = str; *s != '\0' && !isspace ((unsigned char) *s); ++s) |
252b5132 RH |
7000 | continue; |
7001 | ||
7002 | /* If we stopped on whitespace, then replace the whitespace with null for | |
7003 | the call to hash_find. Save the character we replaced just in case we | |
7004 | have to re-parse the instruction. */ | |
d9a62219 | 7005 | if (isspace ((unsigned char) *s)) |
252b5132 RH |
7006 | { |
7007 | save_c = *s; | |
7008 | *s++ = '\0'; | |
7009 | } | |
7010 | ||
7011 | insn = (struct mips_opcode *) hash_find (op_hash, str); | |
7012 | ||
7013 | /* If we didn't find the instruction in the opcode table, try again, but | |
7014 | this time with just the instruction up to, but not including the | |
7015 | first '.'. */ | |
7016 | if (insn == NULL) | |
7017 | { | |
7018 | /* Restore the character we overwrite above (if any). */ | |
7019 | if (save_c) | |
7020 | *(--s) = save_c; | |
7021 | ||
7022 | /* Scan up to the first '.' or whitespace. */ | |
d9a62219 | 7023 | for (s = str; *s != '\0' && *s != '.' && !isspace ((unsigned char) *s); ++s) |
252b5132 RH |
7024 | continue; |
7025 | ||
7026 | /* If we did not find a '.', then we can quit now. */ | |
7027 | if (*s != '.') | |
7028 | { | |
7029 | insn_error = "unrecognized opcode"; | |
7030 | return; | |
7031 | } | |
7032 | ||
7033 | /* Lookup the instruction in the hash table. */ | |
7034 | *s++ = '\0'; | |
7035 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) | |
7036 | { | |
7037 | insn_error = "unrecognized opcode"; | |
7038 | return; | |
7039 | } | |
7040 | ||
7041 | full_opcode_match = 0; | |
7042 | } | |
7043 | ||
7044 | argsStart = s; | |
7045 | for (;;) | |
7046 | { | |
252b5132 RH |
7047 | boolean ok; |
7048 | ||
7049 | assert (strcmp (insn->name, str) == 0); | |
7050 | ||
2bd7f1f3 | 7051 | if (OPCODE_IS_MEMBER (insn, mips_opts.isa, mips_cpu)) |
252b5132 | 7052 | ok = true; |
2bd7f1f3 | 7053 | else |
252b5132 | 7054 | ok = false; |
2bd7f1f3 | 7055 | |
252b5132 RH |
7056 | if (insn->pinfo != INSN_MACRO) |
7057 | { | |
7058 | if (mips_cpu == 4650 && (insn->pinfo & FP_D) != 0) | |
7059 | ok = false; | |
7060 | } | |
7061 | ||
7062 | if (! ok) | |
7063 | { | |
7064 | if (insn + 1 < &mips_opcodes[NUMOPCODES] | |
7065 | && strcmp (insn->name, insn[1].name) == 0) | |
7066 | { | |
7067 | ++insn; | |
7068 | continue; | |
7069 | } | |
252b5132 RH |
7070 | else |
7071 | { | |
7072 | static char buf[100]; | |
2bd7f1f3 GRK |
7073 | sprintf (buf, |
7074 | _("opcode not supported on this processor: %d (MIPS%d)"), | |
7075 | mips_cpu, mips_opts.isa); | |
7076 | ||
252b5132 | 7077 | insn_error = buf; |
2bd7f1f3 | 7078 | return; |
252b5132 | 7079 | } |
252b5132 RH |
7080 | } |
7081 | ||
7082 | ip->insn_mo = insn; | |
7083 | ip->insn_opcode = insn->match; | |
7084 | for (args = insn->args;; ++args) | |
7085 | { | |
7086 | if (*s == ' ') | |
7087 | ++s; | |
7088 | switch (*args) | |
7089 | { | |
7090 | case '\0': /* end of args */ | |
7091 | if (*s == '\0') | |
7092 | return; | |
7093 | break; | |
7094 | ||
7095 | case ',': | |
7096 | if (*s++ == *args) | |
7097 | continue; | |
7098 | s--; | |
7099 | switch (*++args) | |
7100 | { | |
7101 | case 'r': | |
7102 | case 'v': | |
7103 | ip->insn_opcode |= lastregno << 21; | |
7104 | continue; | |
7105 | ||
7106 | case 'w': | |
7107 | case 'W': | |
7108 | ip->insn_opcode |= lastregno << 16; | |
7109 | continue; | |
7110 | ||
7111 | case 'V': | |
7112 | ip->insn_opcode |= lastregno << 11; | |
7113 | continue; | |
7114 | } | |
7115 | break; | |
7116 | ||
7117 | case '(': | |
7118 | /* Handle optional base register. | |
7119 | Either the base register is omitted or | |
7120 | we must have a left paren. */ | |
7121 | /* This is dependent on the next operand specifier | |
7122 | is a base register specification. */ | |
7123 | assert (args[1] == 'b' || args[1] == '5' | |
7124 | || args[1] == '-' || args[1] == '4'); | |
7125 | if (*s == '\0') | |
7126 | return; | |
7127 | ||
7128 | case ')': /* these must match exactly */ | |
7129 | if (*s++ == *args) | |
7130 | continue; | |
7131 | break; | |
7132 | ||
7133 | case '<': /* must be at least one digit */ | |
7134 | /* | |
7135 | * According to the manual, if the shift amount is greater | |
7136 | * than 31 or less than 0 the the shift amount should be | |
7137 | * mod 32. In reality the mips assembler issues an error. | |
7138 | * We issue a warning and mask out all but the low 5 bits. | |
7139 | */ | |
7140 | my_getExpression (&imm_expr, s); | |
7141 | check_absolute_expr (ip, &imm_expr); | |
7142 | if ((unsigned long) imm_expr.X_add_number > 31) | |
7143 | { | |
7144 | as_warn (_("Improper shift amount (%ld)"), | |
7145 | (long) imm_expr.X_add_number); | |
7146 | imm_expr.X_add_number = imm_expr.X_add_number & 0x1f; | |
7147 | } | |
7148 | ip->insn_opcode |= imm_expr.X_add_number << 6; | |
7149 | imm_expr.X_op = O_absent; | |
7150 | s = expr_end; | |
7151 | continue; | |
7152 | ||
7153 | case '>': /* shift amount minus 32 */ | |
7154 | my_getExpression (&imm_expr, s); | |
7155 | check_absolute_expr (ip, &imm_expr); | |
7156 | if ((unsigned long) imm_expr.X_add_number < 32 | |
7157 | || (unsigned long) imm_expr.X_add_number > 63) | |
7158 | break; | |
7159 | ip->insn_opcode |= (imm_expr.X_add_number - 32) << 6; | |
7160 | imm_expr.X_op = O_absent; | |
7161 | s = expr_end; | |
7162 | continue; | |
7163 | ||
7164 | ||
7165 | case 'k': /* cache code */ | |
7166 | case 'h': /* prefx code */ | |
7167 | my_getExpression (&imm_expr, s); | |
7168 | check_absolute_expr (ip, &imm_expr); | |
7169 | if ((unsigned long) imm_expr.X_add_number > 31) | |
7170 | { | |
7171 | as_warn (_("Invalid value for `%s' (%lu)"), | |
7172 | ip->insn_mo->name, | |
7173 | (unsigned long) imm_expr.X_add_number); | |
7174 | imm_expr.X_add_number &= 0x1f; | |
7175 | } | |
7176 | if (*args == 'k') | |
7177 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE; | |
7178 | else | |
7179 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX; | |
7180 | imm_expr.X_op = O_absent; | |
7181 | s = expr_end; | |
7182 | continue; | |
7183 | ||
7184 | case 'c': /* break code */ | |
7185 | my_getExpression (&imm_expr, s); | |
7186 | check_absolute_expr (ip, &imm_expr); | |
7187 | if ((unsigned) imm_expr.X_add_number > 1023) | |
7188 | { | |
7189 | as_warn (_("Illegal break code (%ld)"), | |
7190 | (long) imm_expr.X_add_number); | |
7191 | imm_expr.X_add_number &= 0x3ff; | |
7192 | } | |
7193 | ip->insn_opcode |= imm_expr.X_add_number << 16; | |
7194 | imm_expr.X_op = O_absent; | |
7195 | s = expr_end; | |
7196 | continue; | |
7197 | ||
7198 | case 'q': /* lower break code */ | |
7199 | my_getExpression (&imm_expr, s); | |
7200 | check_absolute_expr (ip, &imm_expr); | |
7201 | if ((unsigned) imm_expr.X_add_number > 1023) | |
7202 | { | |
7203 | as_warn (_("Illegal lower break code (%ld)"), | |
7204 | (long) imm_expr.X_add_number); | |
7205 | imm_expr.X_add_number &= 0x3ff; | |
7206 | } | |
7207 | ip->insn_opcode |= imm_expr.X_add_number << 6; | |
7208 | imm_expr.X_op = O_absent; | |
7209 | s = expr_end; | |
7210 | continue; | |
7211 | ||
7212 | case 'B': /* syscall code */ | |
7213 | my_getExpression (&imm_expr, s); | |
7214 | check_absolute_expr (ip, &imm_expr); | |
7215 | if ((unsigned) imm_expr.X_add_number > 0xfffff) | |
7216 | as_warn (_("Illegal syscall code (%ld)"), | |
7217 | (long) imm_expr.X_add_number); | |
7218 | ip->insn_opcode |= imm_expr.X_add_number << 6; | |
7219 | imm_expr.X_op = O_absent; | |
7220 | s = expr_end; | |
7221 | continue; | |
7222 | ||
7223 | case 'C': /* Coprocessor code */ | |
7224 | my_getExpression (&imm_expr, s); | |
7225 | check_absolute_expr (ip, &imm_expr); | |
7226 | if ((unsigned long) imm_expr.X_add_number >= (1<<25)) | |
7227 | { | |
7228 | as_warn (_("Coproccesor code > 25 bits (%ld)"), | |
7229 | (long) imm_expr.X_add_number); | |
7230 | imm_expr.X_add_number &= ((1<<25) - 1); | |
7231 | } | |
7232 | ip->insn_opcode |= imm_expr.X_add_number; | |
7233 | imm_expr.X_op = O_absent; | |
7234 | s = expr_end; | |
7235 | continue; | |
7236 | ||
7237 | case 'P': /* Performance register */ | |
7238 | my_getExpression (&imm_expr, s); | |
7239 | check_absolute_expr (ip, &imm_expr); | |
7240 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) | |
7241 | { | |
7242 | as_warn (_("Invalidate performance regster (%ld)"), | |
7243 | (long) imm_expr.X_add_number); | |
7244 | imm_expr.X_add_number &= 1; | |
7245 | } | |
7246 | ip->insn_opcode |= (imm_expr.X_add_number << 1); | |
7247 | imm_expr.X_op = O_absent; | |
7248 | s = expr_end; | |
7249 | continue; | |
7250 | ||
7251 | case 'b': /* base register */ | |
7252 | case 'd': /* destination register */ | |
7253 | case 's': /* source register */ | |
7254 | case 't': /* target register */ | |
7255 | case 'r': /* both target and source */ | |
7256 | case 'v': /* both dest and source */ | |
7257 | case 'w': /* both dest and target */ | |
7258 | case 'E': /* coprocessor target register */ | |
7259 | case 'G': /* coprocessor destination register */ | |
7260 | case 'x': /* ignore register name */ | |
7261 | case 'z': /* must be zero register */ | |
7262 | s_reset = s; | |
7263 | if (s[0] == '$') | |
7264 | { | |
7265 | ||
d9a62219 | 7266 | if (isdigit ((unsigned char) s[1])) |
252b5132 RH |
7267 | { |
7268 | ++s; | |
7269 | regno = 0; | |
7270 | do | |
7271 | { | |
7272 | regno *= 10; | |
7273 | regno += *s - '0'; | |
7274 | ++s; | |
7275 | } | |
d9a62219 | 7276 | while (isdigit ((unsigned char) *s)); |
252b5132 RH |
7277 | if (regno > 31) |
7278 | as_bad (_("Invalid register number (%d)"), regno); | |
7279 | } | |
7280 | else if (*args == 'E' || *args == 'G') | |
7281 | goto notreg; | |
7282 | else | |
7283 | { | |
7284 | if (s[1] == 'f' && s[2] == 'p') | |
7285 | { | |
7286 | s += 3; | |
7287 | regno = FP; | |
7288 | } | |
7289 | else if (s[1] == 's' && s[2] == 'p') | |
7290 | { | |
7291 | s += 3; | |
7292 | regno = SP; | |
7293 | } | |
7294 | else if (s[1] == 'g' && s[2] == 'p') | |
7295 | { | |
7296 | s += 3; | |
7297 | regno = GP; | |
7298 | } | |
7299 | else if (s[1] == 'a' && s[2] == 't') | |
7300 | { | |
7301 | s += 3; | |
7302 | regno = AT; | |
7303 | } | |
7304 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
7305 | { | |
7306 | s += 4; | |
7307 | regno = KT0; | |
7308 | } | |
7309 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
7310 | { | |
7311 | s += 4; | |
7312 | regno = KT1; | |
7313 | } | |
7314 | else if (itbl_have_entries) | |
7315 | { | |
7316 | char *p, *n; | |
d7ba4a77 | 7317 | unsigned long r; |
252b5132 | 7318 | |
d7ba4a77 | 7319 | p = s + 1; /* advance past '$' */ |
252b5132 RH |
7320 | n = itbl_get_field (&p); /* n is name */ |
7321 | ||
d7ba4a77 ILT |
7322 | /* See if this is a register defined in an |
7323 | itbl entry. */ | |
7324 | if (itbl_get_reg_val (n, &r)) | |
252b5132 RH |
7325 | { |
7326 | /* Get_field advances to the start of | |
7327 | the next field, so we need to back | |
d7ba4a77 | 7328 | rack to the end of the last field. */ |
252b5132 RH |
7329 | if (p) |
7330 | s = p - 1; | |
7331 | else | |
d7ba4a77 | 7332 | s = strchr (s, '\0'); |
252b5132 RH |
7333 | regno = r; |
7334 | } | |
7335 | else | |
7336 | goto notreg; | |
7337 | } | |
7338 | else | |
7339 | goto notreg; | |
7340 | } | |
7341 | if (regno == AT | |
7342 | && ! mips_opts.noat | |
7343 | && *args != 'E' | |
7344 | && *args != 'G') | |
7345 | as_warn (_("Used $at without \".set noat\"")); | |
7346 | c = *args; | |
7347 | if (*s == ' ') | |
7348 | s++; | |
7349 | if (args[1] != *s) | |
7350 | { | |
7351 | if (c == 'r' || c == 'v' || c == 'w') | |
7352 | { | |
7353 | regno = lastregno; | |
7354 | s = s_reset; | |
7355 | args++; | |
7356 | } | |
7357 | } | |
7358 | /* 'z' only matches $0. */ | |
7359 | if (c == 'z' && regno != 0) | |
7360 | break; | |
7361 | ||
7362 | /* Now that we have assembled one operand, we use the args string | |
7363 | * to figure out where it goes in the instruction. */ | |
7364 | switch (c) | |
7365 | { | |
7366 | case 'r': | |
7367 | case 's': | |
7368 | case 'v': | |
7369 | case 'b': | |
7370 | ip->insn_opcode |= regno << 21; | |
7371 | break; | |
7372 | case 'd': | |
7373 | case 'G': | |
7374 | ip->insn_opcode |= regno << 11; | |
7375 | break; | |
7376 | case 'w': | |
7377 | case 't': | |
7378 | case 'E': | |
7379 | ip->insn_opcode |= regno << 16; | |
7380 | break; | |
7381 | case 'x': | |
7382 | /* This case exists because on the r3000 trunc | |
7383 | expands into a macro which requires a gp | |
7384 | register. On the r6000 or r4000 it is | |
7385 | assembled into a single instruction which | |
7386 | ignores the register. Thus the insn version | |
7387 | is MIPS_ISA2 and uses 'x', and the macro | |
7388 | version is MIPS_ISA1 and uses 't'. */ | |
7389 | break; | |
7390 | case 'z': | |
7391 | /* This case is for the div instruction, which | |
7392 | acts differently if the destination argument | |
7393 | is $0. This only matches $0, and is checked | |
7394 | outside the switch. */ | |
7395 | break; | |
7396 | case 'D': | |
7397 | /* Itbl operand; not yet implemented. FIXME ?? */ | |
7398 | break; | |
7399 | /* What about all other operands like 'i', which | |
7400 | can be specified in the opcode table? */ | |
7401 | } | |
7402 | lastregno = regno; | |
7403 | continue; | |
7404 | } | |
7405 | notreg: | |
7406 | switch (*args++) | |
7407 | { | |
7408 | case 'r': | |
7409 | case 'v': | |
7410 | ip->insn_opcode |= lastregno << 21; | |
7411 | continue; | |
7412 | case 'w': | |
7413 | ip->insn_opcode |= lastregno << 16; | |
7414 | continue; | |
7415 | } | |
7416 | break; | |
7417 | ||
7418 | case 'D': /* floating point destination register */ | |
7419 | case 'S': /* floating point source register */ | |
7420 | case 'T': /* floating point target register */ | |
7421 | case 'R': /* floating point source register */ | |
7422 | case 'V': | |
7423 | case 'W': | |
7424 | s_reset = s; | |
d9a62219 | 7425 | if (s[0] == '$' && s[1] == 'f' && isdigit ((unsigned char) s[2])) |
252b5132 RH |
7426 | { |
7427 | s += 2; | |
7428 | regno = 0; | |
7429 | do | |
7430 | { | |
7431 | regno *= 10; | |
7432 | regno += *s - '0'; | |
7433 | ++s; | |
7434 | } | |
d9a62219 | 7435 | while (isdigit ((unsigned char) *s)); |
252b5132 RH |
7436 | |
7437 | if (regno > 31) | |
7438 | as_bad (_("Invalid float register number (%d)"), regno); | |
7439 | ||
7440 | if ((regno & 1) != 0 | |
9ce8a5dd | 7441 | && ! ISA_HAS_64BIT_REGS (mips_opts.isa) |
252b5132 RH |
7442 | && ! (strcmp (str, "mtc1") == 0 |
7443 | || strcmp (str, "mfc1") == 0 | |
7444 | || strcmp (str, "lwc1") == 0 | |
7445 | || strcmp (str, "swc1") == 0 | |
7446 | || strcmp (str, "l.s") == 0 | |
7447 | || strcmp (str, "s.s") == 0)) | |
7448 | as_warn (_("Float register should be even, was %d"), | |
7449 | regno); | |
7450 | ||
7451 | c = *args; | |
7452 | if (*s == ' ') | |
7453 | s++; | |
7454 | if (args[1] != *s) | |
7455 | { | |
7456 | if (c == 'V' || c == 'W') | |
7457 | { | |
7458 | regno = lastregno; | |
7459 | s = s_reset; | |
7460 | args++; | |
7461 | } | |
7462 | } | |
7463 | switch (c) | |
7464 | { | |
7465 | case 'D': | |
7466 | ip->insn_opcode |= regno << 6; | |
7467 | break; | |
7468 | case 'V': | |
7469 | case 'S': | |
7470 | ip->insn_opcode |= regno << 11; | |
7471 | break; | |
7472 | case 'W': | |
7473 | case 'T': | |
7474 | ip->insn_opcode |= regno << 16; | |
7475 | break; | |
7476 | case 'R': | |
7477 | ip->insn_opcode |= regno << 21; | |
7478 | break; | |
7479 | } | |
7480 | lastregno = regno; | |
7481 | continue; | |
7482 | } | |
7483 | ||
7484 | ||
7485 | switch (*args++) | |
7486 | { | |
7487 | case 'V': | |
7488 | ip->insn_opcode |= lastregno << 11; | |
7489 | continue; | |
7490 | case 'W': | |
7491 | ip->insn_opcode |= lastregno << 16; | |
7492 | continue; | |
7493 | } | |
7494 | break; | |
7495 | ||
7496 | case 'I': | |
7497 | my_getExpression (&imm_expr, s); | |
7498 | if (imm_expr.X_op != O_big | |
7499 | && imm_expr.X_op != O_constant) | |
7500 | insn_error = _("absolute expression required"); | |
7501 | s = expr_end; | |
7502 | continue; | |
7503 | ||
7504 | case 'A': | |
7505 | my_getExpression (&offset_expr, s); | |
7506 | imm_reloc = BFD_RELOC_32; | |
7507 | s = expr_end; | |
7508 | continue; | |
7509 | ||
7510 | case 'F': | |
7511 | case 'L': | |
7512 | case 'f': | |
7513 | case 'l': | |
7514 | { | |
7515 | int f64; | |
7516 | char *save_in; | |
7517 | char *err; | |
7518 | unsigned char temp[8]; | |
7519 | int len; | |
7520 | unsigned int length; | |
7521 | segT seg; | |
7522 | subsegT subseg; | |
7523 | char *p; | |
7524 | ||
7525 | /* These only appear as the last operand in an | |
7526 | instruction, and every instruction that accepts | |
7527 | them in any variant accepts them in all variants. | |
7528 | This means we don't have to worry about backing out | |
7529 | any changes if the instruction does not match. | |
7530 | ||
7531 | The difference between them is the size of the | |
7532 | floating point constant and where it goes. For 'F' | |
7533 | and 'L' the constant is 64 bits; for 'f' and 'l' it | |
7534 | is 32 bits. Where the constant is placed is based | |
7535 | on how the MIPS assembler does things: | |
7536 | F -- .rdata | |
7537 | L -- .lit8 | |
7538 | f -- immediate value | |
7539 | l -- .lit4 | |
7540 | ||
7541 | The .lit4 and .lit8 sections are only used if | |
7542 | permitted by the -G argument. | |
7543 | ||
7544 | When generating embedded PIC code, we use the | |
7545 | .lit8 section but not the .lit4 section (we can do | |
7546 | .lit4 inline easily; we need to put .lit8 | |
7547 | somewhere in the data segment, and using .lit8 | |
7548 | permits the linker to eventually combine identical | |
7549 | .lit8 entries). */ | |
7550 | ||
7551 | f64 = *args == 'F' || *args == 'L'; | |
7552 | ||
7553 | save_in = input_line_pointer; | |
7554 | input_line_pointer = s; | |
7555 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); | |
7556 | length = len; | |
7557 | s = input_line_pointer; | |
7558 | input_line_pointer = save_in; | |
7559 | if (err != NULL && *err != '\0') | |
7560 | { | |
7561 | as_bad (_("Bad floating point constant: %s"), err); | |
7562 | memset (temp, '\0', sizeof temp); | |
7563 | length = f64 ? 8 : 4; | |
7564 | } | |
7565 | ||
7566 | assert (length == (f64 ? 8 : 4)); | |
7567 | ||
7568 | if (*args == 'f' | |
7569 | || (*args == 'l' | |
7570 | && (! USE_GLOBAL_POINTER_OPT | |
7571 | || mips_pic == EMBEDDED_PIC | |
7572 | || g_switch_value < 4 | |
7573 | || (temp[0] == 0 && temp[1] == 0) | |
7574 | || (temp[2] == 0 && temp[3] == 0)))) | |
7575 | { | |
7576 | imm_expr.X_op = O_constant; | |
7577 | if (! target_big_endian) | |
7578 | imm_expr.X_add_number = bfd_getl32 (temp); | |
7579 | else | |
7580 | imm_expr.X_add_number = bfd_getb32 (temp); | |
7581 | } | |
7582 | else if (length > 4 | |
7583 | && ((temp[0] == 0 && temp[1] == 0) | |
7584 | || (temp[2] == 0 && temp[3] == 0)) | |
7585 | && ((temp[4] == 0 && temp[5] == 0) | |
7586 | || (temp[6] == 0 && temp[7] == 0))) | |
7587 | { | |
7588 | /* The value is simple enough to load with a | |
7589 | couple of instructions. In mips1 mode, set | |
7590 | imm_expr to the high order 32 bits and | |
7591 | offset_expr to the low order 32 bits. | |
7592 | Otherwise, set imm_expr to the entire 64 bit | |
7593 | constant. */ | |
9ce8a5dd | 7594 | if (! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
7595 | { |
7596 | imm_expr.X_op = O_constant; | |
7597 | offset_expr.X_op = O_constant; | |
7598 | if (! target_big_endian) | |
7599 | { | |
7600 | imm_expr.X_add_number = bfd_getl32 (temp + 4); | |
7601 | offset_expr.X_add_number = bfd_getl32 (temp); | |
7602 | } | |
7603 | else | |
7604 | { | |
7605 | imm_expr.X_add_number = bfd_getb32 (temp); | |
7606 | offset_expr.X_add_number = bfd_getb32 (temp + 4); | |
7607 | } | |
7608 | if (offset_expr.X_add_number == 0) | |
7609 | offset_expr.X_op = O_absent; | |
7610 | } | |
7611 | else if (sizeof (imm_expr.X_add_number) > 4) | |
7612 | { | |
7613 | imm_expr.X_op = O_constant; | |
7614 | if (! target_big_endian) | |
7615 | imm_expr.X_add_number = bfd_getl64 (temp); | |
7616 | else | |
7617 | imm_expr.X_add_number = bfd_getb64 (temp); | |
7618 | } | |
7619 | else | |
7620 | { | |
7621 | imm_expr.X_op = O_big; | |
7622 | imm_expr.X_add_number = 4; | |
7623 | if (! target_big_endian) | |
7624 | { | |
7625 | generic_bignum[0] = bfd_getl16 (temp); | |
7626 | generic_bignum[1] = bfd_getl16 (temp + 2); | |
7627 | generic_bignum[2] = bfd_getl16 (temp + 4); | |
7628 | generic_bignum[3] = bfd_getl16 (temp + 6); | |
7629 | } | |
7630 | else | |
7631 | { | |
7632 | generic_bignum[0] = bfd_getb16 (temp + 6); | |
7633 | generic_bignum[1] = bfd_getb16 (temp + 4); | |
7634 | generic_bignum[2] = bfd_getb16 (temp + 2); | |
7635 | generic_bignum[3] = bfd_getb16 (temp); | |
7636 | } | |
7637 | } | |
7638 | } | |
7639 | else | |
7640 | { | |
7641 | const char *newname; | |
7642 | segT new_seg; | |
7643 | ||
7644 | /* Switch to the right section. */ | |
7645 | seg = now_seg; | |
7646 | subseg = now_subseg; | |
7647 | switch (*args) | |
7648 | { | |
7649 | default: /* unused default case avoids warnings. */ | |
7650 | case 'L': | |
7651 | newname = RDATA_SECTION_NAME; | |
7652 | if (USE_GLOBAL_POINTER_OPT && g_switch_value >= 8) | |
7653 | newname = ".lit8"; | |
7654 | break; | |
7655 | case 'F': | |
7656 | newname = RDATA_SECTION_NAME; | |
7657 | break; | |
7658 | case 'l': | |
7659 | assert (!USE_GLOBAL_POINTER_OPT | |
7660 | || g_switch_value >= 4); | |
7661 | newname = ".lit4"; | |
7662 | break; | |
7663 | } | |
7664 | new_seg = subseg_new (newname, (subsegT) 0); | |
7665 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
7666 | bfd_set_section_flags (stdoutput, new_seg, | |
7667 | (SEC_ALLOC | |
7668 | | SEC_LOAD | |
7669 | | SEC_READONLY | |
7670 | | SEC_DATA)); | |
7671 | frag_align (*args == 'l' ? 2 : 3, 0, 0); | |
7672 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
7673 | && strcmp (TARGET_OS, "elf") != 0) | |
7674 | record_alignment (new_seg, 4); | |
7675 | else | |
7676 | record_alignment (new_seg, *args == 'l' ? 2 : 3); | |
7677 | if (seg == now_seg) | |
7678 | as_bad (_("Can't use floating point insn in this section")); | |
7679 | ||
7680 | /* Set the argument to the current address in the | |
7681 | section. */ | |
7682 | offset_expr.X_op = O_symbol; | |
7683 | offset_expr.X_add_symbol = | |
7684 | symbol_new ("L0\001", now_seg, | |
7685 | (valueT) frag_now_fix (), frag_now); | |
7686 | offset_expr.X_add_number = 0; | |
7687 | ||
7688 | /* Put the floating point number into the section. */ | |
7689 | p = frag_more ((int) length); | |
7690 | memcpy (p, temp, length); | |
7691 | ||
7692 | /* Switch back to the original section. */ | |
7693 | subseg_set (seg, subseg); | |
7694 | } | |
7695 | } | |
7696 | continue; | |
7697 | ||
7698 | case 'i': /* 16 bit unsigned immediate */ | |
7699 | case 'j': /* 16 bit signed immediate */ | |
7700 | imm_reloc = BFD_RELOC_LO16; | |
7701 | c = my_getSmallExpression (&imm_expr, s); | |
7702 | if (c != '\0') | |
7703 | { | |
7704 | if (c != 'l') | |
7705 | { | |
7706 | if (imm_expr.X_op == O_constant) | |
7707 | imm_expr.X_add_number = | |
7708 | (imm_expr.X_add_number >> 16) & 0xffff; | |
7709 | else if (c == 'h') | |
7710 | { | |
7711 | imm_reloc = BFD_RELOC_HI16_S; | |
7712 | imm_unmatched_hi = true; | |
7713 | } | |
7714 | else | |
7715 | imm_reloc = BFD_RELOC_HI16; | |
7716 | } | |
7717 | else if (imm_expr.X_op == O_constant) | |
7718 | imm_expr.X_add_number &= 0xffff; | |
7719 | } | |
7720 | if (*args == 'i') | |
7721 | { | |
7722 | if ((c == '\0' && imm_expr.X_op != O_constant) | |
7723 | || ((imm_expr.X_add_number < 0 | |
7724 | || imm_expr.X_add_number >= 0x10000) | |
7725 | && imm_expr.X_op == O_constant)) | |
7726 | { | |
7727 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
7728 | !strcmp (insn->name, insn[1].name)) | |
7729 | break; | |
7730 | if (imm_expr.X_op != O_constant | |
7731 | && imm_expr.X_op != O_big) | |
7732 | insn_error = _("absolute expression required"); | |
7733 | else | |
7734 | as_bad (_("16 bit expression not in range 0..65535")); | |
7735 | } | |
7736 | } | |
7737 | else | |
7738 | { | |
7739 | int more; | |
7740 | offsetT max; | |
7741 | ||
7742 | /* The upper bound should be 0x8000, but | |
7743 | unfortunately the MIPS assembler accepts numbers | |
7744 | from 0x8000 to 0xffff and sign extends them, and | |
7745 | we want to be compatible. We only permit this | |
7746 | extended range for an instruction which does not | |
7747 | provide any further alternates, since those | |
7748 | alternates may handle other cases. People should | |
7749 | use the numbers they mean, rather than relying on | |
7750 | a mysterious sign extension. */ | |
7751 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
7752 | strcmp (insn->name, insn[1].name) == 0); | |
7753 | if (more) | |
7754 | max = 0x8000; | |
7755 | else | |
7756 | max = 0x10000; | |
7757 | if ((c == '\0' && imm_expr.X_op != O_constant) | |
7758 | || ((imm_expr.X_add_number < -0x8000 | |
7759 | || imm_expr.X_add_number >= max) | |
7760 | && imm_expr.X_op == O_constant) | |
7761 | || (more | |
7762 | && imm_expr.X_add_number < 0 | |
9ce8a5dd | 7763 | && ISA_HAS_64BIT_REGS (mips_opts.isa) |
252b5132 RH |
7764 | && imm_expr.X_unsigned |
7765 | && sizeof (imm_expr.X_add_number) <= 4)) | |
7766 | { | |
7767 | if (more) | |
7768 | break; | |
7769 | if (imm_expr.X_op != O_constant | |
7770 | && imm_expr.X_op != O_big) | |
7771 | insn_error = _("absolute expression required"); | |
7772 | else | |
7773 | as_bad (_("16 bit expression not in range -32768..32767")); | |
7774 | } | |
7775 | } | |
7776 | s = expr_end; | |
7777 | continue; | |
7778 | ||
7779 | case 'o': /* 16 bit offset */ | |
7780 | c = my_getSmallExpression (&offset_expr, s); | |
7781 | ||
7782 | /* If this value won't fit into a 16 bit offset, then go | |
7783 | find a macro that will generate the 32 bit offset | |
7784 | code pattern. As a special hack, we accept the | |
7785 | difference of two local symbols as a constant. This | |
7786 | is required to suppose embedded PIC switches, which | |
7787 | use an instruction which looks like | |
7788 | lw $4,$L12-$LS12($4) | |
7789 | The problem with handling this in a more general | |
7790 | fashion is that the macro function doesn't expect to | |
7791 | see anything which can be handled in a single | |
7792 | constant instruction. */ | |
7793 | if (c == 0 | |
7794 | && (offset_expr.X_op != O_constant | |
7795 | || offset_expr.X_add_number >= 0x8000 | |
7796 | || offset_expr.X_add_number < -0x8000) | |
7797 | && (mips_pic != EMBEDDED_PIC | |
7798 | || offset_expr.X_op != O_subtract | |
7799 | || now_seg != text_section | |
7800 | || (S_GET_SEGMENT (offset_expr.X_op_symbol) | |
7801 | != text_section))) | |
7802 | break; | |
7803 | ||
7804 | if (c == 'h' || c == 'H') | |
7805 | { | |
7806 | if (offset_expr.X_op != O_constant) | |
7807 | break; | |
7808 | offset_expr.X_add_number = | |
7809 | (offset_expr.X_add_number >> 16) & 0xffff; | |
7810 | } | |
7811 | offset_reloc = BFD_RELOC_LO16; | |
7812 | s = expr_end; | |
7813 | continue; | |
7814 | ||
7815 | case 'p': /* pc relative offset */ | |
7816 | offset_reloc = BFD_RELOC_16_PCREL_S2; | |
7817 | my_getExpression (&offset_expr, s); | |
7818 | s = expr_end; | |
7819 | continue; | |
7820 | ||
7821 | case 'u': /* upper 16 bits */ | |
7822 | c = my_getSmallExpression (&imm_expr, s); | |
7823 | imm_reloc = BFD_RELOC_LO16; | |
7824 | if (c) | |
7825 | { | |
7826 | if (c != 'l') | |
7827 | { | |
7828 | if (imm_expr.X_op == O_constant) | |
7829 | imm_expr.X_add_number = | |
7830 | (imm_expr.X_add_number >> 16) & 0xffff; | |
7831 | else if (c == 'h') | |
7832 | { | |
7833 | imm_reloc = BFD_RELOC_HI16_S; | |
7834 | imm_unmatched_hi = true; | |
7835 | } | |
7836 | else | |
7837 | imm_reloc = BFD_RELOC_HI16; | |
7838 | } | |
7839 | else if (imm_expr.X_op == O_constant) | |
7840 | imm_expr.X_add_number &= 0xffff; | |
7841 | } | |
7842 | if (imm_expr.X_op == O_constant | |
7843 | && (imm_expr.X_add_number < 0 | |
7844 | || imm_expr.X_add_number >= 0x10000)) | |
7845 | as_bad (_("lui expression not in range 0..65535")); | |
7846 | s = expr_end; | |
7847 | continue; | |
7848 | ||
7849 | case 'a': /* 26 bit address */ | |
7850 | my_getExpression (&offset_expr, s); | |
7851 | s = expr_end; | |
7852 | offset_reloc = BFD_RELOC_MIPS_JMP; | |
7853 | continue; | |
7854 | ||
7855 | case 'N': /* 3 bit branch condition code */ | |
7856 | case 'M': /* 3 bit compare condition code */ | |
7857 | if (strncmp (s, "$fcc", 4) != 0) | |
7858 | break; | |
7859 | s += 4; | |
7860 | regno = 0; | |
7861 | do | |
7862 | { | |
7863 | regno *= 10; | |
7864 | regno += *s - '0'; | |
7865 | ++s; | |
7866 | } | |
d9a62219 | 7867 | while (isdigit ((unsigned char) *s)); |
252b5132 RH |
7868 | if (regno > 7) |
7869 | as_bad (_("invalid condition code register $fcc%d"), regno); | |
7870 | if (*args == 'N') | |
7871 | ip->insn_opcode |= regno << OP_SH_BCC; | |
7872 | else | |
7873 | ip->insn_opcode |= regno << OP_SH_CCC; | |
7874 | continue; | |
7875 | ||
7876 | default: | |
7877 | as_bad (_("bad char = '%c'\n"), *args); | |
7878 | internalError (); | |
7879 | } | |
7880 | break; | |
7881 | } | |
7882 | /* Args don't match. */ | |
7883 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && | |
7884 | !strcmp (insn->name, insn[1].name)) | |
7885 | { | |
7886 | ++insn; | |
7887 | s = argsStart; | |
7888 | continue; | |
7889 | } | |
7890 | insn_error = _("illegal operands"); | |
7891 | return; | |
7892 | } | |
7893 | } | |
7894 | ||
7895 | /* This routine assembles an instruction into its binary format when | |
7896 | assembling for the mips16. As a side effect, it sets one of the | |
7897 | global variables imm_reloc or offset_reloc to the type of | |
7898 | relocation to do if one of the operands is an address expression. | |
7899 | It also sets mips16_small and mips16_ext if the user explicitly | |
7900 | requested a small or extended instruction. */ | |
7901 | ||
7902 | static void | |
7903 | mips16_ip (str, ip) | |
7904 | char *str; | |
7905 | struct mips_cl_insn *ip; | |
7906 | { | |
7907 | char *s; | |
7908 | const char *args; | |
7909 | struct mips_opcode *insn; | |
7910 | char *argsstart; | |
7911 | unsigned int regno; | |
7912 | unsigned int lastregno = 0; | |
7913 | char *s_reset; | |
7914 | ||
7915 | insn_error = NULL; | |
7916 | ||
7917 | mips16_small = false; | |
7918 | mips16_ext = false; | |
7919 | ||
d9a62219 | 7920 | for (s = str; islower ((unsigned char) *s); ++s) |
252b5132 RH |
7921 | ; |
7922 | switch (*s) | |
7923 | { | |
7924 | case '\0': | |
7925 | break; | |
7926 | ||
7927 | case ' ': | |
7928 | *s++ = '\0'; | |
7929 | break; | |
7930 | ||
7931 | case '.': | |
7932 | if (s[1] == 't' && s[2] == ' ') | |
7933 | { | |
7934 | *s = '\0'; | |
7935 | mips16_small = true; | |
7936 | s += 3; | |
7937 | break; | |
7938 | } | |
7939 | else if (s[1] == 'e' && s[2] == ' ') | |
7940 | { | |
7941 | *s = '\0'; | |
7942 | mips16_ext = true; | |
7943 | s += 3; | |
7944 | break; | |
7945 | } | |
7946 | /* Fall through. */ | |
7947 | default: | |
7948 | insn_error = _("unknown opcode"); | |
7949 | return; | |
7950 | } | |
7951 | ||
7952 | if (mips_opts.noautoextend && ! mips16_ext) | |
7953 | mips16_small = true; | |
7954 | ||
7955 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) | |
7956 | { | |
7957 | insn_error = _("unrecognized opcode"); | |
7958 | return; | |
7959 | } | |
7960 | ||
7961 | argsstart = s; | |
7962 | for (;;) | |
7963 | { | |
7964 | assert (strcmp (insn->name, str) == 0); | |
7965 | ||
7966 | ip->insn_mo = insn; | |
7967 | ip->insn_opcode = insn->match; | |
7968 | ip->use_extend = false; | |
7969 | imm_expr.X_op = O_absent; | |
7970 | imm_reloc = BFD_RELOC_UNUSED; | |
7971 | offset_expr.X_op = O_absent; | |
7972 | offset_reloc = BFD_RELOC_UNUSED; | |
7973 | for (args = insn->args; 1; ++args) | |
7974 | { | |
7975 | int c; | |
7976 | ||
7977 | if (*s == ' ') | |
7978 | ++s; | |
7979 | ||
7980 | /* In this switch statement we call break if we did not find | |
7981 | a match, continue if we did find a match, or return if we | |
7982 | are done. */ | |
7983 | ||
7984 | c = *args; | |
7985 | switch (c) | |
7986 | { | |
7987 | case '\0': | |
7988 | if (*s == '\0') | |
7989 | { | |
7990 | /* Stuff the immediate value in now, if we can. */ | |
7991 | if (imm_expr.X_op == O_constant | |
7992 | && imm_reloc > BFD_RELOC_UNUSED | |
7993 | && insn->pinfo != INSN_MACRO) | |
7994 | { | |
7995 | mips16_immed ((char *) NULL, 0, | |
7996 | imm_reloc - BFD_RELOC_UNUSED, | |
7997 | imm_expr.X_add_number, true, mips16_small, | |
7998 | mips16_ext, &ip->insn_opcode, | |
7999 | &ip->use_extend, &ip->extend); | |
8000 | imm_expr.X_op = O_absent; | |
8001 | imm_reloc = BFD_RELOC_UNUSED; | |
8002 | } | |
8003 | ||
8004 | return; | |
8005 | } | |
8006 | break; | |
8007 | ||
8008 | case ',': | |
8009 | if (*s++ == c) | |
8010 | continue; | |
8011 | s--; | |
8012 | switch (*++args) | |
8013 | { | |
8014 | case 'v': | |
8015 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
8016 | continue; | |
8017 | case 'w': | |
8018 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
8019 | continue; | |
8020 | } | |
8021 | break; | |
8022 | ||
8023 | case '(': | |
8024 | case ')': | |
8025 | if (*s++ == c) | |
8026 | continue; | |
8027 | break; | |
8028 | ||
8029 | case 'v': | |
8030 | case 'w': | |
8031 | if (s[0] != '$') | |
8032 | { | |
8033 | if (c == 'v') | |
8034 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; | |
8035 | else | |
8036 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; | |
8037 | ++args; | |
8038 | continue; | |
8039 | } | |
8040 | /* Fall through. */ | |
8041 | case 'x': | |
8042 | case 'y': | |
8043 | case 'z': | |
8044 | case 'Z': | |
8045 | case '0': | |
8046 | case 'S': | |
8047 | case 'R': | |
8048 | case 'X': | |
8049 | case 'Y': | |
8050 | if (s[0] != '$') | |
8051 | break; | |
8052 | s_reset = s; | |
d9a62219 | 8053 | if (isdigit ((unsigned char) s[1])) |
252b5132 RH |
8054 | { |
8055 | ++s; | |
8056 | regno = 0; | |
8057 | do | |
8058 | { | |
8059 | regno *= 10; | |
8060 | regno += *s - '0'; | |
8061 | ++s; | |
8062 | } | |
d9a62219 | 8063 | while (isdigit ((unsigned char) *s)); |
252b5132 RH |
8064 | if (regno > 31) |
8065 | { | |
8066 | as_bad (_("invalid register number (%d)"), regno); | |
8067 | regno = 2; | |
8068 | } | |
8069 | } | |
8070 | else | |
8071 | { | |
8072 | if (s[1] == 'f' && s[2] == 'p') | |
8073 | { | |
8074 | s += 3; | |
8075 | regno = FP; | |
8076 | } | |
8077 | else if (s[1] == 's' && s[2] == 'p') | |
8078 | { | |
8079 | s += 3; | |
8080 | regno = SP; | |
8081 | } | |
8082 | else if (s[1] == 'g' && s[2] == 'p') | |
8083 | { | |
8084 | s += 3; | |
8085 | regno = GP; | |
8086 | } | |
8087 | else if (s[1] == 'a' && s[2] == 't') | |
8088 | { | |
8089 | s += 3; | |
8090 | regno = AT; | |
8091 | } | |
8092 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') | |
8093 | { | |
8094 | s += 4; | |
8095 | regno = KT0; | |
8096 | } | |
8097 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') | |
8098 | { | |
8099 | s += 4; | |
8100 | regno = KT1; | |
8101 | } | |
8102 | else | |
8103 | break; | |
8104 | } | |
8105 | ||
8106 | if (*s == ' ') | |
8107 | ++s; | |
8108 | if (args[1] != *s) | |
8109 | { | |
8110 | if (c == 'v' || c == 'w') | |
8111 | { | |
8112 | regno = mips16_to_32_reg_map[lastregno]; | |
8113 | s = s_reset; | |
8114 | args++; | |
8115 | } | |
8116 | } | |
8117 | ||
8118 | switch (c) | |
8119 | { | |
8120 | case 'x': | |
8121 | case 'y': | |
8122 | case 'z': | |
8123 | case 'v': | |
8124 | case 'w': | |
8125 | case 'Z': | |
8126 | regno = mips32_to_16_reg_map[regno]; | |
8127 | break; | |
8128 | ||
8129 | case '0': | |
8130 | if (regno != 0) | |
8131 | regno = ILLEGAL_REG; | |
8132 | break; | |
8133 | ||
8134 | case 'S': | |
8135 | if (regno != SP) | |
8136 | regno = ILLEGAL_REG; | |
8137 | break; | |
8138 | ||
8139 | case 'R': | |
8140 | if (regno != RA) | |
8141 | regno = ILLEGAL_REG; | |
8142 | break; | |
8143 | ||
8144 | case 'X': | |
8145 | case 'Y': | |
8146 | if (regno == AT && ! mips_opts.noat) | |
8147 | as_warn (_("used $at without \".set noat\"")); | |
8148 | break; | |
8149 | ||
8150 | default: | |
8151 | internalError (); | |
8152 | } | |
8153 | ||
8154 | if (regno == ILLEGAL_REG) | |
8155 | break; | |
8156 | ||
8157 | switch (c) | |
8158 | { | |
8159 | case 'x': | |
8160 | case 'v': | |
8161 | ip->insn_opcode |= regno << MIPS16OP_SH_RX; | |
8162 | break; | |
8163 | case 'y': | |
8164 | case 'w': | |
8165 | ip->insn_opcode |= regno << MIPS16OP_SH_RY; | |
8166 | break; | |
8167 | case 'z': | |
8168 | ip->insn_opcode |= regno << MIPS16OP_SH_RZ; | |
8169 | break; | |
8170 | case 'Z': | |
8171 | ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z; | |
8172 | case '0': | |
8173 | case 'S': | |
8174 | case 'R': | |
8175 | break; | |
8176 | case 'X': | |
8177 | ip->insn_opcode |= regno << MIPS16OP_SH_REGR32; | |
8178 | break; | |
8179 | case 'Y': | |
8180 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); | |
8181 | ip->insn_opcode |= regno << MIPS16OP_SH_REG32R; | |
8182 | break; | |
8183 | default: | |
8184 | internalError (); | |
8185 | } | |
8186 | ||
8187 | lastregno = regno; | |
8188 | continue; | |
8189 | ||
8190 | case 'P': | |
8191 | if (strncmp (s, "$pc", 3) == 0) | |
8192 | { | |
8193 | s += 3; | |
8194 | continue; | |
8195 | } | |
8196 | break; | |
8197 | ||
8198 | case '<': | |
8199 | case '>': | |
8200 | case '[': | |
8201 | case ']': | |
8202 | case '4': | |
8203 | case '5': | |
8204 | case 'H': | |
8205 | case 'W': | |
8206 | case 'D': | |
8207 | case 'j': | |
8208 | case '8': | |
8209 | case 'V': | |
8210 | case 'C': | |
8211 | case 'U': | |
8212 | case 'k': | |
8213 | case 'K': | |
8214 | if (s[0] == '%' | |
8215 | && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0) | |
8216 | { | |
8217 | /* This is %gprel(SYMBOL). We need to read SYMBOL, | |
8218 | and generate the appropriate reloc. If the text | |
8219 | inside %gprel is not a symbol name with an | |
8220 | optional offset, then we generate a normal reloc | |
8221 | and will probably fail later. */ | |
8222 | my_getExpression (&imm_expr, s + sizeof "%gprel" - 1); | |
8223 | if (imm_expr.X_op == O_symbol) | |
8224 | { | |
8225 | mips16_ext = true; | |
8226 | imm_reloc = BFD_RELOC_MIPS16_GPREL; | |
8227 | s = expr_end; | |
8228 | ip->use_extend = true; | |
8229 | ip->extend = 0; | |
8230 | continue; | |
8231 | } | |
8232 | } | |
8233 | else | |
8234 | { | |
8235 | /* Just pick up a normal expression. */ | |
8236 | my_getExpression (&imm_expr, s); | |
8237 | } | |
8238 | ||
8239 | if (imm_expr.X_op == O_register) | |
8240 | { | |
8241 | /* What we thought was an expression turned out to | |
8242 | be a register. */ | |
8243 | ||
8244 | if (s[0] == '(' && args[1] == '(') | |
8245 | { | |
8246 | /* It looks like the expression was omitted | |
8247 | before a register indirection, which means | |
8248 | that the expression is implicitly zero. We | |
8249 | still set up imm_expr, so that we handle | |
8250 | explicit extensions correctly. */ | |
8251 | imm_expr.X_op = O_constant; | |
8252 | imm_expr.X_add_number = 0; | |
8253 | imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
8254 | continue; | |
8255 | } | |
8256 | ||
8257 | break; | |
8258 | } | |
8259 | ||
8260 | /* We need to relax this instruction. */ | |
8261 | imm_reloc = (int) BFD_RELOC_UNUSED + c; | |
8262 | s = expr_end; | |
8263 | continue; | |
8264 | ||
8265 | case 'p': | |
8266 | case 'q': | |
8267 | case 'A': | |
8268 | case 'B': | |
8269 | case 'E': | |
8270 | /* We use offset_reloc rather than imm_reloc for the PC | |
8271 | relative operands. This lets macros with both | |
8272 | immediate and address operands work correctly. */ | |
8273 | my_getExpression (&offset_expr, s); | |
8274 | ||
8275 | if (offset_expr.X_op == O_register) | |
8276 | break; | |
8277 | ||
8278 | /* We need to relax this instruction. */ | |
8279 | offset_reloc = (int) BFD_RELOC_UNUSED + c; | |
8280 | s = expr_end; | |
8281 | continue; | |
8282 | ||
8283 | case '6': /* break code */ | |
8284 | my_getExpression (&imm_expr, s); | |
8285 | check_absolute_expr (ip, &imm_expr); | |
8286 | if ((unsigned long) imm_expr.X_add_number > 63) | |
8287 | { | |
8288 | as_warn (_("Invalid value for `%s' (%lu)"), | |
8289 | ip->insn_mo->name, | |
8290 | (unsigned long) imm_expr.X_add_number); | |
8291 | imm_expr.X_add_number &= 0x3f; | |
8292 | } | |
8293 | ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6; | |
8294 | imm_expr.X_op = O_absent; | |
8295 | s = expr_end; | |
8296 | continue; | |
8297 | ||
8298 | case 'a': /* 26 bit address */ | |
8299 | my_getExpression (&offset_expr, s); | |
8300 | s = expr_end; | |
8301 | offset_reloc = BFD_RELOC_MIPS16_JMP; | |
8302 | ip->insn_opcode <<= 16; | |
8303 | continue; | |
8304 | ||
8305 | case 'l': /* register list for entry macro */ | |
8306 | case 'L': /* register list for exit macro */ | |
8307 | { | |
8308 | int mask; | |
8309 | ||
8310 | if (c == 'l') | |
8311 | mask = 0; | |
8312 | else | |
8313 | mask = 7 << 3; | |
8314 | while (*s != '\0') | |
8315 | { | |
8316 | int freg, reg1, reg2; | |
8317 | ||
8318 | while (*s == ' ' || *s == ',') | |
8319 | ++s; | |
8320 | if (*s != '$') | |
8321 | { | |
8322 | as_bad (_("can't parse register list")); | |
8323 | break; | |
8324 | } | |
8325 | ++s; | |
8326 | if (*s != 'f') | |
8327 | freg = 0; | |
8328 | else | |
8329 | { | |
8330 | freg = 1; | |
8331 | ++s; | |
8332 | } | |
8333 | reg1 = 0; | |
d9a62219 | 8334 | while (isdigit ((unsigned char) *s)) |
252b5132 RH |
8335 | { |
8336 | reg1 *= 10; | |
8337 | reg1 += *s - '0'; | |
8338 | ++s; | |
8339 | } | |
8340 | if (*s == ' ') | |
8341 | ++s; | |
8342 | if (*s != '-') | |
8343 | reg2 = reg1; | |
8344 | else | |
8345 | { | |
8346 | ++s; | |
8347 | if (*s != '$') | |
8348 | break; | |
8349 | ++s; | |
8350 | if (freg) | |
8351 | { | |
8352 | if (*s == 'f') | |
8353 | ++s; | |
8354 | else | |
8355 | { | |
8356 | as_bad (_("invalid register list")); | |
8357 | break; | |
8358 | } | |
8359 | } | |
8360 | reg2 = 0; | |
d9a62219 | 8361 | while (isdigit ((unsigned char) *s)) |
252b5132 RH |
8362 | { |
8363 | reg2 *= 10; | |
8364 | reg2 += *s - '0'; | |
8365 | ++s; | |
8366 | } | |
8367 | } | |
8368 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') | |
8369 | { | |
8370 | mask &= ~ (7 << 3); | |
8371 | mask |= 5 << 3; | |
8372 | } | |
8373 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') | |
8374 | { | |
8375 | mask &= ~ (7 << 3); | |
8376 | mask |= 6 << 3; | |
8377 | } | |
8378 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') | |
8379 | mask |= (reg2 - 3) << 3; | |
8380 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) | |
8381 | mask |= (reg2 - 15) << 1; | |
8382 | else if (reg1 == 31 && reg2 == 31) | |
8383 | mask |= 1; | |
8384 | else | |
8385 | { | |
8386 | as_bad (_("invalid register list")); | |
8387 | break; | |
8388 | } | |
8389 | } | |
8390 | /* The mask is filled in in the opcode table for the | |
8391 | benefit of the disassembler. We remove it before | |
8392 | applying the actual mask. */ | |
8393 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); | |
8394 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; | |
8395 | } | |
8396 | continue; | |
8397 | ||
8398 | case 'e': /* extend code */ | |
8399 | my_getExpression (&imm_expr, s); | |
8400 | check_absolute_expr (ip, &imm_expr); | |
8401 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) | |
8402 | { | |
8403 | as_warn (_("Invalid value for `%s' (%lu)"), | |
8404 | ip->insn_mo->name, | |
8405 | (unsigned long) imm_expr.X_add_number); | |
8406 | imm_expr.X_add_number &= 0x7ff; | |
8407 | } | |
8408 | ip->insn_opcode |= imm_expr.X_add_number; | |
8409 | imm_expr.X_op = O_absent; | |
8410 | s = expr_end; | |
8411 | continue; | |
8412 | ||
8413 | default: | |
8414 | internalError (); | |
8415 | } | |
8416 | break; | |
8417 | } | |
8418 | ||
8419 | /* Args don't match. */ | |
8420 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && | |
8421 | strcmp (insn->name, insn[1].name) == 0) | |
8422 | { | |
8423 | ++insn; | |
8424 | s = argsstart; | |
8425 | continue; | |
8426 | } | |
8427 | ||
8428 | insn_error = _("illegal operands"); | |
8429 | ||
8430 | return; | |
8431 | } | |
8432 | } | |
8433 | ||
8434 | /* This structure holds information we know about a mips16 immediate | |
8435 | argument type. */ | |
8436 | ||
8437 | struct mips16_immed_operand | |
8438 | { | |
8439 | /* The type code used in the argument string in the opcode table. */ | |
8440 | int type; | |
8441 | /* The number of bits in the short form of the opcode. */ | |
8442 | int nbits; | |
8443 | /* The number of bits in the extended form of the opcode. */ | |
8444 | int extbits; | |
8445 | /* The amount by which the short form is shifted when it is used; | |
8446 | for example, the sw instruction has a shift count of 2. */ | |
8447 | int shift; | |
8448 | /* The amount by which the short form is shifted when it is stored | |
8449 | into the instruction code. */ | |
8450 | int op_shift; | |
8451 | /* Non-zero if the short form is unsigned. */ | |
8452 | int unsp; | |
8453 | /* Non-zero if the extended form is unsigned. */ | |
8454 | int extu; | |
8455 | /* Non-zero if the value is PC relative. */ | |
8456 | int pcrel; | |
8457 | }; | |
8458 | ||
8459 | /* The mips16 immediate operand types. */ | |
8460 | ||
8461 | static const struct mips16_immed_operand mips16_immed_operands[] = | |
8462 | { | |
8463 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
8464 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
8465 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, | |
8466 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, | |
8467 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, | |
8468 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
8469 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
8470 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
8471 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, | |
8472 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, | |
8473 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
8474 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
8475 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, | |
8476 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, | |
8477 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
8478 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, | |
8479 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
8480 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, | |
8481 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, | |
8482 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, | |
8483 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } | |
8484 | }; | |
8485 | ||
8486 | #define MIPS16_NUM_IMMED \ | |
8487 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) | |
8488 | ||
8489 | /* Handle a mips16 instruction with an immediate value. This or's the | |
8490 | small immediate value into *INSN. It sets *USE_EXTEND to indicate | |
8491 | whether an extended value is needed; if one is needed, it sets | |
8492 | *EXTEND to the value. The argument type is TYPE. The value is VAL. | |
8493 | If SMALL is true, an unextended opcode was explicitly requested. | |
8494 | If EXT is true, an extended opcode was explicitly requested. If | |
8495 | WARN is true, warn if EXT does not match reality. */ | |
8496 | ||
8497 | static void | |
8498 | mips16_immed (file, line, type, val, warn, small, ext, insn, use_extend, | |
8499 | extend) | |
8500 | char *file; | |
8501 | unsigned int line; | |
8502 | int type; | |
8503 | offsetT val; | |
8504 | boolean warn; | |
8505 | boolean small; | |
8506 | boolean ext; | |
8507 | unsigned long *insn; | |
8508 | boolean *use_extend; | |
8509 | unsigned short *extend; | |
8510 | { | |
8511 | register const struct mips16_immed_operand *op; | |
8512 | int mintiny, maxtiny; | |
8513 | boolean needext; | |
8514 | ||
8515 | op = mips16_immed_operands; | |
8516 | while (op->type != type) | |
8517 | { | |
8518 | ++op; | |
8519 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
8520 | } | |
8521 | ||
8522 | if (op->unsp) | |
8523 | { | |
8524 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
8525 | { | |
8526 | mintiny = 1; | |
8527 | maxtiny = 1 << op->nbits; | |
8528 | } | |
8529 | else | |
8530 | { | |
8531 | mintiny = 0; | |
8532 | maxtiny = (1 << op->nbits) - 1; | |
8533 | } | |
8534 | } | |
8535 | else | |
8536 | { | |
8537 | mintiny = - (1 << (op->nbits - 1)); | |
8538 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
8539 | } | |
8540 | ||
8541 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
8542 | if (type == 'p' || type == 'q') | |
8543 | val /= 2; | |
8544 | ||
8545 | if ((val & ((1 << op->shift) - 1)) != 0 | |
8546 | || val < (mintiny << op->shift) | |
8547 | || val > (maxtiny << op->shift)) | |
8548 | needext = true; | |
8549 | else | |
8550 | needext = false; | |
8551 | ||
8552 | if (warn && ext && ! needext) | |
8553 | as_warn_where (file, line, _("extended operand requested but not required")); | |
8554 | if (small && needext) | |
8555 | as_bad_where (file, line, _("invalid unextended operand value")); | |
8556 | ||
8557 | if (small || (! ext && ! needext)) | |
8558 | { | |
8559 | int insnval; | |
8560 | ||
8561 | *use_extend = false; | |
8562 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); | |
8563 | insnval <<= op->op_shift; | |
8564 | *insn |= insnval; | |
8565 | } | |
8566 | else | |
8567 | { | |
8568 | long minext, maxext; | |
8569 | int extval; | |
8570 | ||
8571 | if (op->extu) | |
8572 | { | |
8573 | minext = 0; | |
8574 | maxext = (1 << op->extbits) - 1; | |
8575 | } | |
8576 | else | |
8577 | { | |
8578 | minext = - (1 << (op->extbits - 1)); | |
8579 | maxext = (1 << (op->extbits - 1)) - 1; | |
8580 | } | |
8581 | if (val < minext || val > maxext) | |
8582 | as_bad_where (file, line, | |
8583 | _("operand value out of range for instruction")); | |
8584 | ||
8585 | *use_extend = true; | |
8586 | if (op->extbits == 16) | |
8587 | { | |
8588 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
8589 | val &= 0x1f; | |
8590 | } | |
8591 | else if (op->extbits == 15) | |
8592 | { | |
8593 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
8594 | val &= 0xf; | |
8595 | } | |
8596 | else | |
8597 | { | |
8598 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
8599 | val = 0; | |
8600 | } | |
8601 | ||
8602 | *extend = (unsigned short) extval; | |
8603 | *insn |= val; | |
8604 | } | |
8605 | } | |
8606 | \f | |
8607 | #define LP '(' | |
8608 | #define RP ')' | |
8609 | ||
8610 | static int | |
8611 | my_getSmallExpression (ep, str) | |
8612 | expressionS *ep; | |
8613 | char *str; | |
8614 | { | |
8615 | char *sp; | |
8616 | int c = 0; | |
8617 | ||
8618 | if (*str == ' ') | |
8619 | str++; | |
8620 | if (*str == LP | |
8621 | || (*str == '%' && | |
8622 | ((str[1] == 'h' && str[2] == 'i') | |
8623 | || (str[1] == 'H' && str[2] == 'I') | |
8624 | || (str[1] == 'l' && str[2] == 'o')) | |
8625 | && str[3] == LP)) | |
8626 | { | |
8627 | if (*str == LP) | |
8628 | c = 0; | |
8629 | else | |
8630 | { | |
8631 | c = str[1]; | |
8632 | str += 3; | |
8633 | } | |
8634 | ||
8635 | /* | |
8636 | * A small expression may be followed by a base register. | |
8637 | * Scan to the end of this operand, and then back over a possible | |
8638 | * base register. Then scan the small expression up to that | |
8639 | * point. (Based on code in sparc.c...) | |
8640 | */ | |
8641 | for (sp = str; *sp && *sp != ','; sp++) | |
8642 | ; | |
8643 | if (sp - 4 >= str && sp[-1] == RP) | |
8644 | { | |
d9a62219 | 8645 | if (isdigit ((unsigned char) sp[-2])) |
252b5132 | 8646 | { |
d9a62219 | 8647 | for (sp -= 3; sp >= str && isdigit ((unsigned char) *sp); sp--) |
252b5132 RH |
8648 | ; |
8649 | if (*sp == '$' && sp > str && sp[-1] == LP) | |
8650 | { | |
8651 | sp--; | |
8652 | goto do_it; | |
8653 | } | |
8654 | } | |
8655 | else if (sp - 5 >= str | |
8656 | && sp[-5] == LP | |
8657 | && sp[-4] == '$' | |
8658 | && ((sp[-3] == 'f' && sp[-2] == 'p') | |
8659 | || (sp[-3] == 's' && sp[-2] == 'p') | |
8660 | || (sp[-3] == 'g' && sp[-2] == 'p') | |
8661 | || (sp[-3] == 'a' && sp[-2] == 't'))) | |
8662 | { | |
8663 | sp -= 5; | |
8664 | do_it: | |
8665 | if (sp == str) | |
8666 | { | |
8667 | /* no expression means zero offset */ | |
8668 | if (c) | |
8669 | { | |
8670 | /* %xx(reg) is an error */ | |
8671 | ep->X_op = O_absent; | |
8672 | expr_end = str - 3; | |
8673 | } | |
8674 | else | |
8675 | { | |
8676 | ep->X_op = O_constant; | |
8677 | expr_end = sp; | |
8678 | } | |
8679 | ep->X_add_symbol = NULL; | |
8680 | ep->X_op_symbol = NULL; | |
8681 | ep->X_add_number = 0; | |
8682 | } | |
8683 | else | |
8684 | { | |
8685 | *sp = '\0'; | |
8686 | my_getExpression (ep, str); | |
8687 | *sp = LP; | |
8688 | } | |
8689 | return c; | |
8690 | } | |
8691 | } | |
8692 | } | |
8693 | my_getExpression (ep, str); | |
8694 | return c; /* => %hi or %lo encountered */ | |
8695 | } | |
8696 | ||
8697 | static void | |
8698 | my_getExpression (ep, str) | |
8699 | expressionS *ep; | |
8700 | char *str; | |
8701 | { | |
8702 | char *save_in; | |
8703 | ||
8704 | save_in = input_line_pointer; | |
8705 | input_line_pointer = str; | |
8706 | expression (ep); | |
8707 | expr_end = input_line_pointer; | |
8708 | input_line_pointer = save_in; | |
8709 | ||
8710 | /* If we are in mips16 mode, and this is an expression based on `.', | |
8711 | then we bump the value of the symbol by 1 since that is how other | |
8712 | text symbols are handled. We don't bother to handle complex | |
8713 | expressions, just `.' plus or minus a constant. */ | |
8714 | if (mips_opts.mips16 | |
8715 | && ep->X_op == O_symbol | |
8716 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 | |
8717 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg | |
49309057 ILT |
8718 | && symbol_get_frag (ep->X_add_symbol) == frag_now |
8719 | && symbol_constant_p (ep->X_add_symbol) | |
8720 | && S_GET_VALUE (ep->X_add_symbol) == frag_now_fix ()) | |
8721 | S_SET_VALUE (ep->X_add_symbol, S_GET_VALUE (ep->X_add_symbol) + 1); | |
252b5132 RH |
8722 | } |
8723 | ||
8724 | /* Turn a string in input_line_pointer into a floating point constant | |
8725 | of type type, and store the appropriate bytes in *litP. The number | |
8726 | of LITTLENUMS emitted is stored in *sizeP . An error message is | |
8727 | returned, or NULL on OK. */ | |
8728 | ||
8729 | char * | |
8730 | md_atof (type, litP, sizeP) | |
8731 | int type; | |
8732 | char *litP; | |
8733 | int *sizeP; | |
8734 | { | |
8735 | int prec; | |
8736 | LITTLENUM_TYPE words[4]; | |
8737 | char *t; | |
8738 | int i; | |
8739 | ||
8740 | switch (type) | |
8741 | { | |
8742 | case 'f': | |
8743 | prec = 2; | |
8744 | break; | |
8745 | ||
8746 | case 'd': | |
8747 | prec = 4; | |
8748 | break; | |
8749 | ||
8750 | default: | |
8751 | *sizeP = 0; | |
8752 | return _("bad call to md_atof"); | |
8753 | } | |
8754 | ||
8755 | t = atof_ieee (input_line_pointer, type, words); | |
8756 | if (t) | |
8757 | input_line_pointer = t; | |
8758 | ||
8759 | *sizeP = prec * 2; | |
8760 | ||
8761 | if (! target_big_endian) | |
8762 | { | |
8763 | for (i = prec - 1; i >= 0; i--) | |
8764 | { | |
8765 | md_number_to_chars (litP, (valueT) words[i], 2); | |
8766 | litP += 2; | |
8767 | } | |
8768 | } | |
8769 | else | |
8770 | { | |
8771 | for (i = 0; i < prec; i++) | |
8772 | { | |
8773 | md_number_to_chars (litP, (valueT) words[i], 2); | |
8774 | litP += 2; | |
8775 | } | |
8776 | } | |
8777 | ||
8778 | return NULL; | |
8779 | } | |
8780 | ||
8781 | void | |
8782 | md_number_to_chars (buf, val, n) | |
8783 | char *buf; | |
8784 | valueT val; | |
8785 | int n; | |
8786 | { | |
8787 | if (target_big_endian) | |
8788 | number_to_chars_bigendian (buf, val, n); | |
8789 | else | |
8790 | number_to_chars_littleendian (buf, val, n); | |
8791 | } | |
8792 | \f | |
8793 | CONST char *md_shortopts = "O::g::G:"; | |
8794 | ||
8795 | struct option md_longopts[] = { | |
8796 | #define OPTION_MIPS1 (OPTION_MD_BASE + 1) | |
8797 | {"mips0", no_argument, NULL, OPTION_MIPS1}, | |
8798 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
8799 | #define OPTION_MIPS2 (OPTION_MD_BASE + 2) | |
8800 | {"mips2", no_argument, NULL, OPTION_MIPS2}, | |
8801 | #define OPTION_MIPS3 (OPTION_MD_BASE + 3) | |
8802 | {"mips3", no_argument, NULL, OPTION_MIPS3}, | |
8803 | #define OPTION_MIPS4 (OPTION_MD_BASE + 4) | |
8804 | {"mips4", no_argument, NULL, OPTION_MIPS4}, | |
8805 | #define OPTION_MCPU (OPTION_MD_BASE + 5) | |
8806 | {"mcpu", required_argument, NULL, OPTION_MCPU}, | |
8807 | #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6) | |
8808 | {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC}, | |
8809 | #define OPTION_TRAP (OPTION_MD_BASE + 9) | |
8810 | {"trap", no_argument, NULL, OPTION_TRAP}, | |
8811 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
8812 | #define OPTION_BREAK (OPTION_MD_BASE + 10) | |
8813 | {"break", no_argument, NULL, OPTION_BREAK}, | |
8814 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
8815 | #define OPTION_EB (OPTION_MD_BASE + 11) | |
8816 | {"EB", no_argument, NULL, OPTION_EB}, | |
8817 | #define OPTION_EL (OPTION_MD_BASE + 12) | |
8818 | {"EL", no_argument, NULL, OPTION_EL}, | |
8819 | #define OPTION_M4650 (OPTION_MD_BASE + 13) | |
8820 | {"m4650", no_argument, NULL, OPTION_M4650}, | |
8821 | #define OPTION_NO_M4650 (OPTION_MD_BASE + 14) | |
8822 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, | |
8823 | #define OPTION_M4010 (OPTION_MD_BASE + 15) | |
8824 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
8825 | #define OPTION_NO_M4010 (OPTION_MD_BASE + 16) | |
8826 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
8827 | #define OPTION_M4100 (OPTION_MD_BASE + 17) | |
8828 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
8829 | #define OPTION_NO_M4100 (OPTION_MD_BASE + 18) | |
8830 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
8831 | #define OPTION_MIPS16 (OPTION_MD_BASE + 22) | |
8832 | {"mips16", no_argument, NULL, OPTION_MIPS16}, | |
8833 | #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23) | |
8834 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, | |
8835 | #define OPTION_M3900 (OPTION_MD_BASE + 26) | |
8836 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
8837 | #define OPTION_NO_M3900 (OPTION_MD_BASE + 27) | |
8838 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
8839 | ||
8840 | ||
8841 | #define OPTION_MABI (OPTION_MD_BASE + 38) | |
8842 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
8843 | ||
6b76fefe CM |
8844 | #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 39) |
8845 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, | |
8846 | #define OPTION_NO_M7000_HILO_FIX (OPTION_MD_BASE + 40) | |
8847 | {"no-fix-7000", no_argument, NULL, OPTION_NO_M7000_HILO_FIX}, | |
8848 | ||
252b5132 RH |
8849 | #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7) |
8850 | #define OPTION_NON_SHARED (OPTION_MD_BASE + 8) | |
8851 | #define OPTION_XGOT (OPTION_MD_BASE + 19) | |
8852 | #define OPTION_32 (OPTION_MD_BASE + 20) | |
8853 | #define OPTION_64 (OPTION_MD_BASE + 21) | |
8854 | #ifdef OBJ_ELF | |
8855 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, | |
8856 | {"xgot", no_argument, NULL, OPTION_XGOT}, | |
8857 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
8858 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, | |
8859 | {"32", no_argument, NULL, OPTION_32}, | |
8860 | {"64", no_argument, NULL, OPTION_64}, | |
8861 | #endif | |
8862 | ||
8863 | {NULL, no_argument, NULL, 0} | |
8864 | }; | |
8865 | size_t md_longopts_size = sizeof(md_longopts); | |
8866 | ||
8867 | int | |
8868 | md_parse_option (c, arg) | |
8869 | int c; | |
8870 | char *arg; | |
8871 | { | |
8872 | switch (c) | |
8873 | { | |
8874 | case OPTION_TRAP: | |
8875 | mips_trap = 1; | |
8876 | break; | |
8877 | ||
8878 | case OPTION_BREAK: | |
8879 | mips_trap = 0; | |
8880 | break; | |
8881 | ||
8882 | case OPTION_EB: | |
8883 | target_big_endian = 1; | |
8884 | break; | |
8885 | ||
8886 | case OPTION_EL: | |
8887 | target_big_endian = 0; | |
8888 | break; | |
8889 | ||
8890 | case 'O': | |
8891 | if (arg && arg[1] == '0') | |
8892 | mips_optimize = 1; | |
8893 | else | |
8894 | mips_optimize = 2; | |
8895 | break; | |
8896 | ||
8897 | case 'g': | |
8898 | if (arg == NULL) | |
8899 | mips_debug = 2; | |
8900 | else | |
8901 | mips_debug = atoi (arg); | |
8902 | /* When the MIPS assembler sees -g or -g2, it does not do | |
8903 | optimizations which limit full symbolic debugging. We take | |
8904 | that to be equivalent to -O0. */ | |
8905 | if (mips_debug == 2) | |
8906 | mips_optimize = 1; | |
8907 | break; | |
8908 | ||
8909 | case OPTION_MIPS1: | |
8910 | mips_opts.isa = 1; | |
8911 | break; | |
8912 | ||
8913 | case OPTION_MIPS2: | |
8914 | mips_opts.isa = 2; | |
8915 | break; | |
8916 | ||
8917 | case OPTION_MIPS3: | |
8918 | mips_opts.isa = 3; | |
8919 | break; | |
8920 | ||
8921 | case OPTION_MIPS4: | |
8922 | mips_opts.isa = 4; | |
8923 | break; | |
8924 | ||
8925 | case OPTION_MCPU: | |
8926 | { | |
8927 | char *p; | |
8928 | ||
8929 | /* Identify the processor type */ | |
8930 | p = arg; | |
8931 | if (strcmp (p, "default") == 0 | |
8932 | || strcmp (p, "DEFAULT") == 0) | |
8933 | mips_cpu = -1; | |
8934 | else | |
8935 | { | |
8936 | int sv = 0; | |
8937 | ||
8938 | /* We need to cope with the various "vr" prefixes for the 4300 | |
8939 | processor. */ | |
8940 | if (*p == 'v' || *p == 'V') | |
8941 | { | |
8942 | sv = 1; | |
8943 | p++; | |
8944 | } | |
8945 | ||
8946 | if (*p == 'r' || *p == 'R') | |
8947 | p++; | |
8948 | ||
8949 | mips_cpu = -1; | |
8950 | switch (*p) | |
8951 | { | |
8952 | case '1': | |
8953 | if (strcmp (p, "10000") == 0 | |
8954 | || strcmp (p, "10k") == 0 | |
8955 | || strcmp (p, "10K") == 0) | |
8956 | mips_cpu = 10000; | |
8957 | break; | |
8958 | ||
8959 | case '2': | |
8960 | if (strcmp (p, "2000") == 0 | |
8961 | || strcmp (p, "2k") == 0 | |
8962 | || strcmp (p, "2K") == 0) | |
8963 | mips_cpu = 2000; | |
8964 | break; | |
8965 | ||
8966 | case '3': | |
8967 | if (strcmp (p, "3000") == 0 | |
8968 | || strcmp (p, "3k") == 0 | |
8969 | || strcmp (p, "3K") == 0) | |
8970 | mips_cpu = 3000; | |
8971 | else if (strcmp (p, "3900") == 0) | |
8972 | mips_cpu = 3900; | |
8973 | break; | |
8974 | ||
8975 | case '4': | |
8976 | if (strcmp (p, "4000") == 0 | |
8977 | || strcmp (p, "4k") == 0 | |
8978 | || strcmp (p, "4K") == 0) | |
8979 | mips_cpu = 4000; | |
8980 | else if (strcmp (p, "4100") == 0) | |
8981 | mips_cpu = 4100; | |
8982 | else if (strcmp (p, "4111") == 0) | |
8983 | mips_cpu = 4111; | |
8984 | else if (strcmp (p, "4300") == 0) | |
8985 | mips_cpu = 4300; | |
8986 | else if (strcmp (p, "4400") == 0) | |
8987 | mips_cpu = 4400; | |
8988 | else if (strcmp (p, "4600") == 0) | |
8989 | mips_cpu = 4600; | |
8990 | else if (strcmp (p, "4650") == 0) | |
8991 | mips_cpu = 4650; | |
8992 | else if (strcmp (p, "4010") == 0) | |
8993 | mips_cpu = 4010; | |
8994 | break; | |
8995 | ||
8996 | case '5': | |
8997 | if (strcmp (p, "5000") == 0 | |
8998 | || strcmp (p, "5k") == 0 | |
8999 | || strcmp (p, "5K") == 0) | |
9000 | mips_cpu = 5000; | |
9001 | break; | |
9002 | ||
9003 | case '6': | |
9004 | if (strcmp (p, "6000") == 0 | |
9005 | || strcmp (p, "6k") == 0 | |
9006 | || strcmp (p, "6K") == 0) | |
9007 | mips_cpu = 6000; | |
9008 | break; | |
9009 | ||
9010 | case '8': | |
9011 | if (strcmp (p, "8000") == 0 | |
9012 | || strcmp (p, "8k") == 0 | |
9013 | || strcmp (p, "8K") == 0) | |
9014 | mips_cpu = 8000; | |
9015 | break; | |
9016 | ||
9017 | case 'o': | |
9018 | if (strcmp (p, "orion") == 0) | |
9019 | mips_cpu = 4600; | |
9020 | break; | |
9021 | } | |
9022 | ||
9023 | if (sv | |
9024 | && (mips_cpu != 4300 | |
9025 | && mips_cpu != 4100 | |
9026 | && mips_cpu != 4111 | |
9027 | && mips_cpu != 5000)) | |
9028 | { | |
9029 | as_bad (_("ignoring invalid leading 'v' in -mcpu=%s switch"), arg); | |
9030 | return 0; | |
9031 | } | |
9032 | ||
9033 | if (mips_cpu == -1) | |
9034 | { | |
9035 | as_bad (_("invalid architecture -mcpu=%s"), arg); | |
9036 | return 0; | |
9037 | } | |
9038 | } | |
9039 | } | |
9040 | break; | |
9041 | ||
9042 | case OPTION_M4650: | |
9043 | mips_cpu = 4650; | |
9044 | break; | |
9045 | ||
9046 | case OPTION_NO_M4650: | |
9047 | break; | |
9048 | ||
9049 | case OPTION_M4010: | |
9050 | mips_cpu = 4010; | |
9051 | break; | |
9052 | ||
9053 | case OPTION_NO_M4010: | |
9054 | break; | |
9055 | ||
9056 | case OPTION_M4100: | |
9057 | mips_cpu = 4100; | |
9058 | break; | |
9059 | ||
9060 | case OPTION_NO_M4100: | |
9061 | break; | |
9062 | ||
9063 | ||
9064 | case OPTION_M3900: | |
9065 | mips_cpu = 3900; | |
9066 | break; | |
9067 | ||
9068 | case OPTION_NO_M3900: | |
9069 | break; | |
9070 | ||
9071 | case OPTION_MIPS16: | |
9072 | mips_opts.mips16 = 1; | |
9073 | mips_no_prev_insn (false); | |
9074 | break; | |
9075 | ||
9076 | case OPTION_NO_MIPS16: | |
9077 | mips_opts.mips16 = 0; | |
9078 | mips_no_prev_insn (false); | |
9079 | break; | |
9080 | ||
9081 | case OPTION_MEMBEDDED_PIC: | |
9082 | mips_pic = EMBEDDED_PIC; | |
9083 | if (USE_GLOBAL_POINTER_OPT && g_switch_seen) | |
9084 | { | |
9085 | as_bad (_("-G may not be used with embedded PIC code")); | |
9086 | return 0; | |
9087 | } | |
9088 | g_switch_value = 0x7fffffff; | |
9089 | break; | |
9090 | ||
9091 | /* When generating ELF code, we permit -KPIC and -call_shared to | |
9092 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
9093 | intended to be compatible with Irix 5. */ | |
9094 | case OPTION_CALL_SHARED: | |
9095 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
9096 | { | |
9097 | as_bad (_("-call_shared is supported only for ELF format")); | |
9098 | return 0; | |
9099 | } | |
9100 | mips_pic = SVR4_PIC; | |
9101 | if (g_switch_seen && g_switch_value != 0) | |
9102 | { | |
9103 | as_bad (_("-G may not be used with SVR4 PIC code")); | |
9104 | return 0; | |
9105 | } | |
9106 | g_switch_value = 0; | |
9107 | break; | |
9108 | ||
9109 | case OPTION_NON_SHARED: | |
9110 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
9111 | { | |
9112 | as_bad (_("-non_shared is supported only for ELF format")); | |
9113 | return 0; | |
9114 | } | |
9115 | mips_pic = NO_PIC; | |
9116 | break; | |
9117 | ||
9118 | /* The -xgot option tells the assembler to use 32 offsets when | |
9119 | accessing the got in SVR4_PIC mode. It is for Irix | |
9120 | compatibility. */ | |
9121 | case OPTION_XGOT: | |
9122 | mips_big_got = 1; | |
9123 | break; | |
9124 | ||
9125 | case 'G': | |
9126 | if (! USE_GLOBAL_POINTER_OPT) | |
9127 | { | |
9128 | as_bad (_("-G is not supported for this configuration")); | |
9129 | return 0; | |
9130 | } | |
9131 | else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC) | |
9132 | { | |
9133 | as_bad (_("-G may not be used with SVR4 or embedded PIC code")); | |
9134 | return 0; | |
9135 | } | |
9136 | else | |
9137 | g_switch_value = atoi (arg); | |
9138 | g_switch_seen = 1; | |
9139 | break; | |
9140 | ||
9141 | /* The -32 and -64 options tell the assembler to output the 32 | |
9142 | bit or the 64 bit MIPS ELF format. */ | |
9143 | case OPTION_32: | |
9144 | mips_64 = 0; | |
9145 | break; | |
9146 | ||
9147 | case OPTION_64: | |
9148 | { | |
9149 | const char **list, **l; | |
9150 | ||
9151 | list = bfd_target_list (); | |
9152 | for (l = list; *l != NULL; l++) | |
9153 | if (strcmp (*l, "elf64-bigmips") == 0 | |
9154 | || strcmp (*l, "elf64-littlemips") == 0) | |
9155 | break; | |
9156 | if (*l == NULL) | |
9157 | as_fatal (_("No compiled in support for 64 bit object file format")); | |
9158 | free (list); | |
9159 | mips_64 = 1; | |
9160 | } | |
9161 | break; | |
9162 | ||
9163 | ||
9164 | case OPTION_MABI: | |
9165 | if (strcmp (arg,"32") == 0 | |
9166 | || strcmp (arg,"n32") == 0 | |
9167 | || strcmp (arg,"64") == 0 | |
9168 | || strcmp (arg,"o64") == 0 | |
9169 | || strcmp (arg,"eabi") == 0) | |
9170 | mips_abi_string = arg; | |
9171 | break; | |
9172 | ||
6b76fefe CM |
9173 | case OPTION_M7000_HILO_FIX: |
9174 | mips_7000_hilo_fix = true; | |
9175 | break; | |
9176 | ||
9177 | case OPTION_NO_M7000_HILO_FIX: | |
9178 | mips_7000_hilo_fix = false; | |
9179 | break; | |
9180 | ||
252b5132 RH |
9181 | default: |
9182 | return 0; | |
9183 | } | |
9184 | ||
9185 | return 1; | |
9186 | } | |
9187 | ||
9188 | ||
9189 | static void | |
9190 | show (stream, string, col_p, first_p) | |
9191 | FILE *stream; | |
9192 | char *string; | |
9193 | int *col_p; | |
9194 | int *first_p; | |
9195 | { | |
9196 | if (*first_p) | |
9197 | { | |
9198 | fprintf (stream, "%24s", ""); | |
9199 | *col_p = 24; | |
9200 | } | |
9201 | else | |
9202 | { | |
9203 | fprintf (stream, ", "); | |
9204 | *col_p += 2; | |
9205 | } | |
9206 | ||
9207 | if (*col_p + strlen (string) > 72) | |
9208 | { | |
9209 | fprintf (stream, "\n%24s", ""); | |
9210 | *col_p = 24; | |
9211 | } | |
9212 | ||
9213 | fprintf (stream, "%s", string); | |
9214 | *col_p += strlen (string); | |
9215 | ||
9216 | *first_p = 0; | |
9217 | } | |
9218 | ||
9219 | ||
9220 | void | |
9221 | md_show_usage (stream) | |
9222 | FILE *stream; | |
9223 | { | |
9224 | int column, first; | |
9225 | ||
9226 | fprintf(stream, _("\ | |
9227 | MIPS options:\n\ | |
9228 | -membedded-pic generate embedded position independent code\n\ | |
9229 | -EB generate big endian output\n\ | |
9230 | -EL generate little endian output\n\ | |
9231 | -g, -g2 do not remove uneeded NOPs or swap branches\n\ | |
9232 | -G NUM allow referencing objects up to NUM bytes\n\ | |
9233 | implicitly with the gp register [default 8]\n")); | |
9234 | fprintf(stream, _("\ | |
9235 | -mips1 generate MIPS ISA I instructions\n\ | |
9236 | -mips2 generate MIPS ISA II instructions\n\ | |
9237 | -mips3 generate MIPS ISA III instructions\n\ | |
9238 | -mips4 generate MIPS ISA IV instructions\n\ | |
9239 | -mcpu=CPU generate code for CPU, where CPU is one of:\n")); | |
9240 | ||
9241 | first = 1; | |
9242 | ||
9243 | show (stream, "2000", &column, &first); | |
9244 | show (stream, "3000", &column, &first); | |
9245 | show (stream, "3900", &column, &first); | |
9246 | show (stream, "4000", &column, &first); | |
9247 | show (stream, "4010", &column, &first); | |
9248 | show (stream, "4100", &column, &first); | |
9249 | show (stream, "4111", &column, &first); | |
9250 | show (stream, "4300", &column, &first); | |
9251 | show (stream, "4400", &column, &first); | |
9252 | show (stream, "4600", &column, &first); | |
9253 | show (stream, "4650", &column, &first); | |
9254 | show (stream, "5000", &column, &first); | |
9255 | show (stream, "6000", &column, &first); | |
9256 | show (stream, "8000", &column, &first); | |
9257 | show (stream, "10000", &column, &first); | |
9258 | fputc ('\n', stream); | |
9259 | ||
9260 | fprintf (stream, _("\ | |
9261 | -mCPU equivalent to -mcpu=CPU.\n\ | |
9262 | -no-mCPU don't generate code specific to CPU.\n\ | |
9263 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
9264 | ||
9265 | first = 1; | |
9266 | ||
9267 | show (stream, "3900", &column, &first); | |
9268 | show (stream, "4010", &column, &first); | |
9269 | show (stream, "4100", &column, &first); | |
9270 | show (stream, "4650", &column, &first); | |
9271 | fputc ('\n', stream); | |
9272 | ||
9273 | fprintf(stream, _("\ | |
9274 | -mips16 generate mips16 instructions\n\ | |
9275 | -no-mips16 do not generate mips16 instructions\n")); | |
9276 | fprintf(stream, _("\ | |
9277 | -O0 remove unneeded NOPs, do not swap branches\n\ | |
9278 | -O remove unneeded NOPs and swap branches\n\ | |
9279 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ | |
9280 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
9281 | #ifdef OBJ_ELF | |
9282 | fprintf(stream, _("\ | |
9283 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
9284 | -non_shared do not generate position independent code\n\ | |
9285 | -xgot assume a 32 bit GOT\n\ | |
9286 | -32 create 32 bit object file (default)\n\ | |
9287 | -64 create 64 bit object file\n")); | |
9288 | #endif | |
9289 | } | |
9290 | \f | |
9291 | void | |
9292 | mips_init_after_args () | |
9293 | { | |
9294 | /* initialize opcodes */ | |
9295 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
9296 | mips_opcodes = (struct mips_opcode*) mips_builtin_opcodes; | |
9297 | } | |
9298 | ||
9299 | long | |
9300 | md_pcrel_from (fixP) | |
9301 | fixS *fixP; | |
9302 | { | |
9303 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour | |
9304 | && fixP->fx_addsy != (symbolS *) NULL | |
9305 | && ! S_IS_DEFINED (fixP->fx_addsy)) | |
9306 | { | |
9307 | /* This makes a branch to an undefined symbol be a branch to the | |
9308 | current location. */ | |
9309 | return 4; | |
9310 | } | |
9311 | ||
9312 | /* return the address of the delay slot */ | |
9313 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
9314 | } | |
9315 | ||
9316 | /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a | |
9317 | reloc for a cons. We could use the definition there, except that | |
9318 | we want to handle 64 bit relocs specially. */ | |
9319 | ||
9320 | void | |
9321 | cons_fix_new_mips (frag, where, nbytes, exp) | |
9322 | fragS *frag; | |
9323 | int where; | |
9324 | unsigned int nbytes; | |
9325 | expressionS *exp; | |
9326 | { | |
9327 | #ifndef OBJ_ELF | |
9328 | /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a | |
9329 | 4 byte reloc. */ | |
9330 | if (nbytes == 8 && ! mips_64) | |
9331 | { | |
9332 | if (target_big_endian) | |
9333 | where += 4; | |
9334 | nbytes = 4; | |
9335 | } | |
9336 | #endif | |
9337 | ||
9338 | if (nbytes != 2 && nbytes != 4 && nbytes != 8) | |
9339 | as_bad (_("Unsupported reloc size %d"), nbytes); | |
9340 | ||
9341 | fix_new_exp (frag_now, where, (int) nbytes, exp, 0, | |
9342 | (nbytes == 2 | |
9343 | ? BFD_RELOC_16 | |
9344 | : (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64))); | |
9345 | } | |
9346 | ||
9347 | /* This is called before the symbol table is processed. In order to | |
9348 | work with gcc when using mips-tfile, we must keep all local labels. | |
9349 | However, in other cases, we want to discard them. If we were | |
9350 | called with -g, but we didn't see any debugging information, it may | |
9351 | mean that gcc is smuggling debugging information through to | |
9352 | mips-tfile, in which case we must generate all local labels. */ | |
9353 | ||
9354 | void | |
9355 | mips_frob_file_before_adjust () | |
9356 | { | |
9357 | #ifndef NO_ECOFF_DEBUGGING | |
9358 | if (ECOFF_DEBUGGING | |
9359 | && mips_debug != 0 | |
9360 | && ! ecoff_debugging_seen) | |
9361 | flag_keep_locals = 1; | |
9362 | #endif | |
9363 | } | |
9364 | ||
9365 | /* Sort any unmatched HI16_S relocs so that they immediately precede | |
9366 | the corresponding LO reloc. This is called before md_apply_fix and | |
9367 | tc_gen_reloc. Unmatched HI16_S relocs can only be generated by | |
9368 | explicit use of the %hi modifier. */ | |
9369 | ||
9370 | void | |
9371 | mips_frob_file () | |
9372 | { | |
9373 | struct mips_hi_fixup *l; | |
9374 | ||
9375 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
9376 | { | |
9377 | segment_info_type *seginfo; | |
9378 | int pass; | |
9379 | ||
9380 | assert (l->fixp->fx_r_type == BFD_RELOC_HI16_S); | |
9381 | ||
9382 | /* Check quickly whether the next fixup happens to be a matching | |
9383 | %lo. */ | |
9384 | if (l->fixp->fx_next != NULL | |
9385 | && l->fixp->fx_next->fx_r_type == BFD_RELOC_LO16 | |
9386 | && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy | |
9387 | && l->fixp->fx_offset == l->fixp->fx_next->fx_offset) | |
9388 | continue; | |
9389 | ||
9390 | /* Look through the fixups for this segment for a matching %lo. | |
9391 | When we find one, move the %hi just in front of it. We do | |
9392 | this in two passes. In the first pass, we try to find a | |
9393 | unique %lo. In the second pass, we permit multiple %hi | |
9394 | relocs for a single %lo (this is a GNU extension). */ | |
9395 | seginfo = seg_info (l->seg); | |
9396 | for (pass = 0; pass < 2; pass++) | |
9397 | { | |
9398 | fixS *f, *prev; | |
9399 | ||
9400 | prev = NULL; | |
9401 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) | |
9402 | { | |
9403 | /* Check whether this is a %lo fixup which matches l->fixp. */ | |
9404 | if (f->fx_r_type == BFD_RELOC_LO16 | |
9405 | && f->fx_addsy == l->fixp->fx_addsy | |
9406 | && f->fx_offset == l->fixp->fx_offset | |
9407 | && (pass == 1 | |
9408 | || prev == NULL | |
9409 | || prev->fx_r_type != BFD_RELOC_HI16_S | |
9410 | || prev->fx_addsy != f->fx_addsy | |
9411 | || prev->fx_offset != f->fx_offset)) | |
9412 | { | |
9413 | fixS **pf; | |
9414 | ||
9415 | /* Move l->fixp before f. */ | |
9416 | for (pf = &seginfo->fix_root; | |
9417 | *pf != l->fixp; | |
9418 | pf = &(*pf)->fx_next) | |
9419 | assert (*pf != NULL); | |
9420 | ||
9421 | *pf = l->fixp->fx_next; | |
9422 | ||
9423 | l->fixp->fx_next = f; | |
9424 | if (prev == NULL) | |
9425 | seginfo->fix_root = l->fixp; | |
9426 | else | |
9427 | prev->fx_next = l->fixp; | |
9428 | ||
9429 | break; | |
9430 | } | |
9431 | ||
9432 | prev = f; | |
9433 | } | |
9434 | ||
9435 | if (f != NULL) | |
9436 | break; | |
9437 | ||
9438 | #if 0 /* GCC code motion plus incomplete dead code elimination | |
9439 | can leave a %hi without a %lo. */ | |
9440 | if (pass == 1) | |
9441 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, | |
9442 | _("Unmatched %%hi reloc")); | |
9443 | #endif | |
9444 | } | |
9445 | } | |
9446 | } | |
9447 | ||
9448 | /* When generating embedded PIC code we need to use a special | |
9449 | relocation to represent the difference of two symbols in the .text | |
9450 | section (switch tables use a difference of this sort). See | |
9451 | include/coff/mips.h for details. This macro checks whether this | |
9452 | fixup requires the special reloc. */ | |
9453 | #define SWITCH_TABLE(fixp) \ | |
9454 | ((fixp)->fx_r_type == BFD_RELOC_32 \ | |
9455 | && (fixp)->fx_addsy != NULL \ | |
9456 | && (fixp)->fx_subsy != NULL \ | |
9457 | && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \ | |
9458 | && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section) | |
9459 | ||
9460 | /* When generating embedded PIC code we must keep all PC relative | |
9461 | relocations, in case the linker has to relax a call. We also need | |
9462 | to keep relocations for switch table entries. */ | |
9463 | ||
9464 | /*ARGSUSED*/ | |
9465 | int | |
9466 | mips_force_relocation (fixp) | |
9467 | fixS *fixp; | |
9468 | { | |
9469 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
9470 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
9471 | return 1; | |
9472 | ||
9473 | return (mips_pic == EMBEDDED_PIC | |
9474 | && (fixp->fx_pcrel | |
9475 | || SWITCH_TABLE (fixp) | |
9476 | || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S | |
9477 | || fixp->fx_r_type == BFD_RELOC_PCREL_LO16)); | |
9478 | } | |
9479 | ||
9480 | /* Apply a fixup to the object file. */ | |
9481 | ||
9482 | int | |
9483 | md_apply_fix (fixP, valueP) | |
9484 | fixS *fixP; | |
9485 | valueT *valueP; | |
9486 | { | |
9487 | unsigned char *buf; | |
9488 | long insn, value; | |
9489 | ||
9490 | assert (fixP->fx_size == 4 | |
9491 | || fixP->fx_r_type == BFD_RELOC_16 | |
9492 | || fixP->fx_r_type == BFD_RELOC_64 | |
9493 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
9494 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY); | |
9495 | ||
9496 | value = *valueP; | |
9497 | ||
9498 | /* If we aren't adjusting this fixup to be against the section | |
9499 | symbol, we need to adjust the value. */ | |
9500 | #ifdef OBJ_ELF | |
9501 | if (fixP->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
9502 | if (S_GET_OTHER (fixP->fx_addsy) == STO_MIPS16 | |
9503 | || S_IS_WEAK (fixP->fx_addsy) | |
49309057 ILT |
9504 | || (symbol_used_in_reloc_p (fixP->fx_addsy) |
9505 | && (((bfd_get_section_flags (stdoutput, | |
9506 | S_GET_SEGMENT (fixP->fx_addsy)) | |
9507 | & SEC_LINK_ONCE) != 0) | |
9508 | || !strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)), | |
9509 | ".gnu.linkonce", | |
9510 | sizeof (".gnu.linkonce") - 1)))) | |
252b5132 RH |
9511 | |
9512 | { | |
9513 | value -= S_GET_VALUE (fixP->fx_addsy); | |
9514 | if (value != 0 && ! fixP->fx_pcrel) | |
9515 | { | |
9516 | /* In this case, the bfd_install_relocation routine will | |
9517 | incorrectly add the symbol value back in. We just want | |
9518 | the addend to appear in the object file. */ | |
9519 | value -= S_GET_VALUE (fixP->fx_addsy); | |
9520 | } | |
9521 | } | |
9522 | #endif | |
9523 | ||
9524 | ||
9525 | fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc */ | |
9526 | ||
9527 | if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel) | |
9528 | fixP->fx_done = 1; | |
9529 | ||
9530 | switch (fixP->fx_r_type) | |
9531 | { | |
9532 | case BFD_RELOC_MIPS_JMP: | |
9533 | case BFD_RELOC_HI16: | |
9534 | case BFD_RELOC_HI16_S: | |
9535 | case BFD_RELOC_MIPS_GPREL: | |
9536 | case BFD_RELOC_MIPS_LITERAL: | |
9537 | case BFD_RELOC_MIPS_CALL16: | |
9538 | case BFD_RELOC_MIPS_GOT16: | |
9539 | case BFD_RELOC_MIPS_GPREL32: | |
9540 | case BFD_RELOC_MIPS_GOT_HI16: | |
9541 | case BFD_RELOC_MIPS_GOT_LO16: | |
9542 | case BFD_RELOC_MIPS_CALL_HI16: | |
9543 | case BFD_RELOC_MIPS_CALL_LO16: | |
9544 | case BFD_RELOC_MIPS16_GPREL: | |
9545 | if (fixP->fx_pcrel) | |
9546 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
9547 | _("Invalid PC relative reloc")); | |
9548 | /* Nothing needed to do. The value comes from the reloc entry */ | |
9549 | break; | |
9550 | ||
9551 | case BFD_RELOC_MIPS16_JMP: | |
9552 | /* We currently always generate a reloc against a symbol, which | |
9553 | means that we don't want an addend even if the symbol is | |
9554 | defined. */ | |
9555 | fixP->fx_addnumber = 0; | |
9556 | break; | |
9557 | ||
9558 | case BFD_RELOC_PCREL_HI16_S: | |
9559 | /* The addend for this is tricky if it is internal, so we just | |
9560 | do everything here rather than in bfd_install_relocation. */ | |
49309057 | 9561 | if ((symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0) |
252b5132 RH |
9562 | { |
9563 | /* For an external symbol adjust by the address to make it | |
9564 | pcrel_offset. We use the address of the RELLO reloc | |
9565 | which follows this one. */ | |
9566 | value += (fixP->fx_next->fx_frag->fr_address | |
9567 | + fixP->fx_next->fx_where); | |
9568 | } | |
9569 | if (value & 0x8000) | |
9570 | value += 0x10000; | |
9571 | value >>= 16; | |
9572 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; | |
9573 | if (target_big_endian) | |
9574 | buf += 2; | |
9575 | md_number_to_chars (buf, value, 2); | |
9576 | break; | |
9577 | ||
9578 | case BFD_RELOC_PCREL_LO16: | |
9579 | /* The addend for this is tricky if it is internal, so we just | |
9580 | do everything here rather than in bfd_install_relocation. */ | |
49309057 | 9581 | if ((symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0) |
252b5132 RH |
9582 | value += fixP->fx_frag->fr_address + fixP->fx_where; |
9583 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; | |
9584 | if (target_big_endian) | |
9585 | buf += 2; | |
9586 | md_number_to_chars (buf, value, 2); | |
9587 | break; | |
9588 | ||
9589 | case BFD_RELOC_64: | |
9590 | /* This is handled like BFD_RELOC_32, but we output a sign | |
9591 | extended value if we are only 32 bits. */ | |
9592 | if (fixP->fx_done | |
9593 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
9594 | { | |
9595 | if (8 <= sizeof (valueT)) | |
9596 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
9597 | value, 8); | |
9598 | else | |
9599 | { | |
9600 | long w1, w2; | |
9601 | long hiv; | |
9602 | ||
9603 | w1 = w2 = fixP->fx_where; | |
9604 | if (target_big_endian) | |
9605 | w1 += 4; | |
9606 | else | |
9607 | w2 += 4; | |
9608 | md_number_to_chars (fixP->fx_frag->fr_literal + w1, value, 4); | |
9609 | if ((value & 0x80000000) != 0) | |
9610 | hiv = 0xffffffff; | |
9611 | else | |
9612 | hiv = 0; | |
9613 | md_number_to_chars (fixP->fx_frag->fr_literal + w2, hiv, 4); | |
9614 | } | |
9615 | } | |
9616 | break; | |
9617 | ||
9618 | case BFD_RELOC_32: | |
9619 | /* If we are deleting this reloc entry, we must fill in the | |
9620 | value now. This can happen if we have a .word which is not | |
9621 | resolved when it appears but is later defined. We also need | |
9622 | to fill in the value if this is an embedded PIC switch table | |
9623 | entry. */ | |
9624 | if (fixP->fx_done | |
9625 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) | |
9626 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
9627 | value, 4); | |
9628 | break; | |
9629 | ||
9630 | case BFD_RELOC_16: | |
9631 | /* If we are deleting this reloc entry, we must fill in the | |
9632 | value now. */ | |
9633 | assert (fixP->fx_size == 2); | |
9634 | if (fixP->fx_done) | |
9635 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, | |
9636 | value, 2); | |
9637 | break; | |
9638 | ||
9639 | case BFD_RELOC_LO16: | |
9640 | /* When handling an embedded PIC switch statement, we can wind | |
9641 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ | |
9642 | if (fixP->fx_done) | |
9643 | { | |
9644 | if (value < -0x8000 || value > 0x7fff) | |
9645 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
9646 | _("relocation overflow")); | |
9647 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; | |
9648 | if (target_big_endian) | |
9649 | buf += 2; | |
9650 | md_number_to_chars (buf, value, 2); | |
9651 | } | |
9652 | break; | |
9653 | ||
9654 | case BFD_RELOC_16_PCREL_S2: | |
9655 | /* | |
9656 | * We need to save the bits in the instruction since fixup_segment() | |
9657 | * might be deleting the relocation entry (i.e., a branch within | |
9658 | * the current segment). | |
9659 | */ | |
9660 | if ((value & 0x3) != 0) | |
9661 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
9662 | _("Branch to odd address (%lx)"), value); | |
9663 | value >>= 2; | |
9664 | ||
9665 | /* update old instruction data */ | |
9666 | buf = (unsigned char *) (fixP->fx_where + fixP->fx_frag->fr_literal); | |
9667 | if (target_big_endian) | |
9668 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; | |
9669 | else | |
9670 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; | |
9671 | ||
9672 | if (value >= -0x8000 && value < 0x8000) | |
9673 | insn |= value & 0xffff; | |
9674 | else | |
9675 | { | |
9676 | /* The branch offset is too large. If this is an | |
9677 | unconditional branch, and we are not generating PIC code, | |
9678 | we can convert it to an absolute jump instruction. */ | |
9679 | if (mips_pic == NO_PIC | |
9680 | && fixP->fx_done | |
9681 | && fixP->fx_frag->fr_address >= text_section->vma | |
9682 | && (fixP->fx_frag->fr_address | |
9683 | < text_section->vma + text_section->_raw_size) | |
9684 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
9685 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
9686 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
9687 | { | |
9688 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ | |
9689 | insn = 0x0c000000; /* jal */ | |
9690 | else | |
9691 | insn = 0x08000000; /* j */ | |
9692 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
9693 | fixP->fx_done = 0; | |
9694 | fixP->fx_addsy = section_symbol (text_section); | |
9695 | fixP->fx_addnumber = (value << 2) + md_pcrel_from (fixP); | |
9696 | } | |
9697 | else | |
9698 | { | |
9699 | /* FIXME. It would be possible in principle to handle | |
9700 | conditional branches which overflow. They could be | |
9701 | transformed into a branch around a jump. This would | |
9702 | require setting up variant frags for each different | |
9703 | branch type. The native MIPS assembler attempts to | |
9704 | handle these cases, but it appears to do it | |
9705 | incorrectly. */ | |
9706 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
9707 | _("Branch out of range")); | |
9708 | } | |
9709 | } | |
9710 | ||
9711 | md_number_to_chars ((char *) buf, (valueT) insn, 4); | |
9712 | break; | |
9713 | ||
9714 | case BFD_RELOC_VTABLE_INHERIT: | |
9715 | fixP->fx_done = 0; | |
9716 | if (fixP->fx_addsy | |
9717 | && !S_IS_DEFINED (fixP->fx_addsy) | |
9718 | && !S_IS_WEAK (fixP->fx_addsy)) | |
9719 | S_SET_WEAK (fixP->fx_addsy); | |
9720 | break; | |
9721 | ||
9722 | case BFD_RELOC_VTABLE_ENTRY: | |
9723 | fixP->fx_done = 0; | |
9724 | break; | |
9725 | ||
9726 | default: | |
9727 | internalError (); | |
9728 | } | |
9729 | ||
9730 | return 1; | |
9731 | } | |
9732 | ||
9733 | #if 0 | |
9734 | void | |
9735 | printInsn (oc) | |
9736 | unsigned long oc; | |
9737 | { | |
9738 | const struct mips_opcode *p; | |
9739 | int treg, sreg, dreg, shamt; | |
9740 | short imm; | |
9741 | const char *args; | |
9742 | int i; | |
9743 | ||
9744 | for (i = 0; i < NUMOPCODES; ++i) | |
9745 | { | |
9746 | p = &mips_opcodes[i]; | |
9747 | if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO)) | |
9748 | { | |
9749 | printf ("%08lx %s\t", oc, p->name); | |
9750 | treg = (oc >> 16) & 0x1f; | |
9751 | sreg = (oc >> 21) & 0x1f; | |
9752 | dreg = (oc >> 11) & 0x1f; | |
9753 | shamt = (oc >> 6) & 0x1f; | |
9754 | imm = oc; | |
9755 | for (args = p->args;; ++args) | |
9756 | { | |
9757 | switch (*args) | |
9758 | { | |
9759 | case '\0': | |
9760 | printf ("\n"); | |
9761 | break; | |
9762 | ||
9763 | case ',': | |
9764 | case '(': | |
9765 | case ')': | |
9766 | printf ("%c", *args); | |
9767 | continue; | |
9768 | ||
9769 | case 'r': | |
9770 | assert (treg == sreg); | |
9771 | printf ("$%d,$%d", treg, sreg); | |
9772 | continue; | |
9773 | ||
9774 | case 'd': | |
9775 | case 'G': | |
9776 | printf ("$%d", dreg); | |
9777 | continue; | |
9778 | ||
9779 | case 't': | |
9780 | case 'E': | |
9781 | printf ("$%d", treg); | |
9782 | continue; | |
9783 | ||
9784 | case 'k': | |
9785 | printf ("0x%x", treg); | |
9786 | continue; | |
9787 | ||
9788 | case 'b': | |
9789 | case 's': | |
9790 | printf ("$%d", sreg); | |
9791 | continue; | |
9792 | ||
9793 | case 'a': | |
9794 | printf ("0x%08lx", oc & 0x1ffffff); | |
9795 | continue; | |
9796 | ||
9797 | case 'i': | |
9798 | case 'j': | |
9799 | case 'o': | |
9800 | case 'u': | |
9801 | printf ("%d", imm); | |
9802 | continue; | |
9803 | ||
9804 | case '<': | |
9805 | case '>': | |
9806 | printf ("$%d", shamt); | |
9807 | continue; | |
9808 | ||
9809 | default: | |
9810 | internalError (); | |
9811 | } | |
9812 | break; | |
9813 | } | |
9814 | return; | |
9815 | } | |
9816 | } | |
9817 | printf (_("%08lx UNDEFINED\n"), oc); | |
9818 | } | |
9819 | #endif | |
9820 | ||
9821 | static symbolS * | |
9822 | get_symbol () | |
9823 | { | |
9824 | int c; | |
9825 | char *name; | |
9826 | symbolS *p; | |
9827 | ||
9828 | name = input_line_pointer; | |
9829 | c = get_symbol_end (); | |
9830 | p = (symbolS *) symbol_find_or_make (name); | |
9831 | *input_line_pointer = c; | |
9832 | return p; | |
9833 | } | |
9834 | ||
9835 | /* Align the current frag to a given power of two. The MIPS assembler | |
9836 | also automatically adjusts any preceding label. */ | |
9837 | ||
9838 | static void | |
9839 | mips_align (to, fill, label) | |
9840 | int to; | |
9841 | int fill; | |
9842 | symbolS *label; | |
9843 | { | |
9844 | mips_emit_delays (false); | |
9845 | frag_align (to, fill, 0); | |
9846 | record_alignment (now_seg, to); | |
9847 | if (label != NULL) | |
9848 | { | |
9849 | assert (S_GET_SEGMENT (label) == now_seg); | |
49309057 | 9850 | symbol_set_frag (label, frag_now); |
252b5132 RH |
9851 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
9852 | } | |
9853 | } | |
9854 | ||
9855 | /* Align to a given power of two. .align 0 turns off the automatic | |
9856 | alignment used by the data creating pseudo-ops. */ | |
9857 | ||
9858 | static void | |
9859 | s_align (x) | |
9860 | int x; | |
9861 | { | |
9862 | register int temp; | |
9863 | register long temp_fill; | |
9864 | long max_alignment = 15; | |
9865 | ||
9866 | /* | |
9867 | ||
9868 | o Note that the assembler pulls down any immediately preceeding label | |
9869 | to the aligned address. | |
9870 | o It's not documented but auto alignment is reinstated by | |
9871 | a .align pseudo instruction. | |
9872 | o Note also that after auto alignment is turned off the mips assembler | |
9873 | issues an error on attempt to assemble an improperly aligned data item. | |
9874 | We don't. | |
9875 | ||
9876 | */ | |
9877 | ||
9878 | temp = get_absolute_expression (); | |
9879 | if (temp > max_alignment) | |
9880 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); | |
9881 | else if (temp < 0) | |
9882 | { | |
9883 | as_warn (_("Alignment negative: 0 assumed.")); | |
9884 | temp = 0; | |
9885 | } | |
9886 | if (*input_line_pointer == ',') | |
9887 | { | |
9888 | input_line_pointer++; | |
9889 | temp_fill = get_absolute_expression (); | |
9890 | } | |
9891 | else | |
9892 | temp_fill = 0; | |
9893 | if (temp) | |
9894 | { | |
9895 | auto_align = 1; | |
9896 | mips_align (temp, (int) temp_fill, | |
9897 | insn_labels != NULL ? insn_labels->label : NULL); | |
9898 | } | |
9899 | else | |
9900 | { | |
9901 | auto_align = 0; | |
9902 | } | |
9903 | ||
9904 | demand_empty_rest_of_line (); | |
9905 | } | |
9906 | ||
9907 | void | |
9908 | mips_flush_pending_output () | |
9909 | { | |
9910 | mips_emit_delays (false); | |
9911 | mips_clear_insn_labels (); | |
9912 | } | |
9913 | ||
9914 | static void | |
9915 | s_change_sec (sec) | |
9916 | int sec; | |
9917 | { | |
9918 | segT seg; | |
9919 | ||
9920 | /* When generating embedded PIC code, we only use the .text, .lit8, | |
9921 | .sdata and .sbss sections. We change the .data and .rdata | |
9922 | pseudo-ops to use .sdata. */ | |
9923 | if (mips_pic == EMBEDDED_PIC | |
9924 | && (sec == 'd' || sec == 'r')) | |
9925 | sec = 's'; | |
9926 | ||
9927 | #ifdef OBJ_ELF | |
9928 | /* The ELF backend needs to know that we are changing sections, so | |
9929 | that .previous works correctly. We could do something like check | |
9930 | for a obj_section_change_hook macro, but that might be confusing | |
9931 | as it would not be appropriate to use it in the section changing | |
9932 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
9933 | This should be cleaner, somehow. */ | |
9934 | obj_elf_section_change_hook (); | |
9935 | #endif | |
9936 | ||
9937 | mips_emit_delays (false); | |
9938 | switch (sec) | |
9939 | { | |
9940 | case 't': | |
9941 | s_text (0); | |
9942 | break; | |
9943 | case 'd': | |
9944 | s_data (0); | |
9945 | break; | |
9946 | case 'b': | |
9947 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
9948 | demand_empty_rest_of_line (); | |
9949 | break; | |
9950 | ||
9951 | case 'r': | |
9952 | if (USE_GLOBAL_POINTER_OPT) | |
9953 | { | |
9954 | seg = subseg_new (RDATA_SECTION_NAME, | |
9955 | (subsegT) get_absolute_expression ()); | |
9956 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
9957 | { | |
9958 | bfd_set_section_flags (stdoutput, seg, | |
9959 | (SEC_ALLOC | |
9960 | | SEC_LOAD | |
9961 | | SEC_READONLY | |
9962 | | SEC_RELOC | |
9963 | | SEC_DATA)); | |
9964 | if (strcmp (TARGET_OS, "elf") != 0) | |
9965 | bfd_set_section_alignment (stdoutput, seg, 4); | |
9966 | } | |
9967 | demand_empty_rest_of_line (); | |
9968 | } | |
9969 | else | |
9970 | { | |
9971 | as_bad (_("No read only data section in this object file format")); | |
9972 | demand_empty_rest_of_line (); | |
9973 | return; | |
9974 | } | |
9975 | break; | |
9976 | ||
9977 | case 's': | |
9978 | if (USE_GLOBAL_POINTER_OPT) | |
9979 | { | |
9980 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); | |
9981 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
9982 | { | |
9983 | bfd_set_section_flags (stdoutput, seg, | |
9984 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | |
9985 | | SEC_DATA); | |
9986 | if (strcmp (TARGET_OS, "elf") != 0) | |
9987 | bfd_set_section_alignment (stdoutput, seg, 4); | |
9988 | } | |
9989 | demand_empty_rest_of_line (); | |
9990 | break; | |
9991 | } | |
9992 | else | |
9993 | { | |
9994 | as_bad (_("Global pointers not supported; recompile -G 0")); | |
9995 | demand_empty_rest_of_line (); | |
9996 | return; | |
9997 | } | |
9998 | } | |
9999 | ||
10000 | auto_align = 1; | |
10001 | } | |
10002 | ||
10003 | void | |
10004 | mips_enable_auto_align () | |
10005 | { | |
10006 | auto_align = 1; | |
10007 | } | |
10008 | ||
10009 | static void | |
10010 | s_cons (log_size) | |
10011 | int log_size; | |
10012 | { | |
10013 | symbolS *label; | |
10014 | ||
10015 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
10016 | mips_emit_delays (false); | |
10017 | if (log_size > 0 && auto_align) | |
10018 | mips_align (log_size, 0, label); | |
10019 | mips_clear_insn_labels (); | |
10020 | cons (1 << log_size); | |
10021 | } | |
10022 | ||
10023 | static void | |
10024 | s_float_cons (type) | |
10025 | int type; | |
10026 | { | |
10027 | symbolS *label; | |
10028 | ||
10029 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
10030 | ||
10031 | mips_emit_delays (false); | |
10032 | ||
10033 | if (auto_align) | |
49309057 ILT |
10034 | { |
10035 | if (type == 'd') | |
10036 | mips_align (3, 0, label); | |
10037 | else | |
10038 | mips_align (2, 0, label); | |
10039 | } | |
252b5132 RH |
10040 | |
10041 | mips_clear_insn_labels (); | |
10042 | ||
10043 | float_cons (type); | |
10044 | } | |
10045 | ||
10046 | /* Handle .globl. We need to override it because on Irix 5 you are | |
10047 | permitted to say | |
10048 | .globl foo .text | |
10049 | where foo is an undefined symbol, to mean that foo should be | |
10050 | considered to be the address of a function. */ | |
10051 | ||
10052 | static void | |
10053 | s_mips_globl (x) | |
10054 | int x; | |
10055 | { | |
10056 | char *name; | |
10057 | int c; | |
10058 | symbolS *symbolP; | |
10059 | flagword flag; | |
10060 | ||
10061 | name = input_line_pointer; | |
10062 | c = get_symbol_end (); | |
10063 | symbolP = symbol_find_or_make (name); | |
10064 | *input_line_pointer = c; | |
10065 | SKIP_WHITESPACE (); | |
10066 | ||
10067 | /* On Irix 5, every global symbol that is not explicitly labelled as | |
10068 | being a function is apparently labelled as being an object. */ | |
10069 | flag = BSF_OBJECT; | |
10070 | ||
10071 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
10072 | { | |
10073 | char *secname; | |
10074 | asection *sec; | |
10075 | ||
10076 | secname = input_line_pointer; | |
10077 | c = get_symbol_end (); | |
10078 | sec = bfd_get_section_by_name (stdoutput, secname); | |
10079 | if (sec == NULL) | |
10080 | as_bad (_("%s: no such section"), secname); | |
10081 | *input_line_pointer = c; | |
10082 | ||
10083 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
10084 | flag = BSF_FUNCTION; | |
10085 | } | |
10086 | ||
49309057 | 10087 | symbol_get_bfdsym (symbolP)->flags |= flag; |
252b5132 RH |
10088 | |
10089 | S_SET_EXTERNAL (symbolP); | |
10090 | demand_empty_rest_of_line (); | |
10091 | } | |
10092 | ||
10093 | static void | |
10094 | s_option (x) | |
10095 | int x; | |
10096 | { | |
10097 | char *opt; | |
10098 | char c; | |
10099 | ||
10100 | opt = input_line_pointer; | |
10101 | c = get_symbol_end (); | |
10102 | ||
10103 | if (*opt == 'O') | |
10104 | { | |
10105 | /* FIXME: What does this mean? */ | |
10106 | } | |
10107 | else if (strncmp (opt, "pic", 3) == 0) | |
10108 | { | |
10109 | int i; | |
10110 | ||
10111 | i = atoi (opt + 3); | |
10112 | if (i == 0) | |
10113 | mips_pic = NO_PIC; | |
10114 | else if (i == 2) | |
10115 | mips_pic = SVR4_PIC; | |
10116 | else | |
10117 | as_bad (_(".option pic%d not supported"), i); | |
10118 | ||
10119 | if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC) | |
10120 | { | |
10121 | if (g_switch_seen && g_switch_value != 0) | |
10122 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
10123 | g_switch_value = 0; | |
10124 | bfd_set_gp_size (stdoutput, 0); | |
10125 | } | |
10126 | } | |
10127 | else | |
10128 | as_warn (_("Unrecognized option \"%s\""), opt); | |
10129 | ||
10130 | *input_line_pointer = c; | |
10131 | demand_empty_rest_of_line (); | |
10132 | } | |
10133 | ||
10134 | /* This structure is used to hold a stack of .set values. */ | |
10135 | ||
10136 | struct mips_option_stack | |
10137 | { | |
10138 | struct mips_option_stack *next; | |
10139 | struct mips_set_options options; | |
10140 | }; | |
10141 | ||
10142 | static struct mips_option_stack *mips_opts_stack; | |
10143 | ||
10144 | /* Handle the .set pseudo-op. */ | |
10145 | ||
10146 | static void | |
10147 | s_mipsset (x) | |
10148 | int x; | |
10149 | { | |
10150 | char *name = input_line_pointer, ch; | |
10151 | ||
10152 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
10153 | input_line_pointer++; | |
10154 | ch = *input_line_pointer; | |
10155 | *input_line_pointer = '\0'; | |
10156 | ||
10157 | if (strcmp (name, "reorder") == 0) | |
10158 | { | |
10159 | if (mips_opts.noreorder && prev_nop_frag != NULL) | |
10160 | { | |
10161 | /* If we still have pending nops, we can discard them. The | |
10162 | usual nop handling will insert any that are still | |
10163 | needed. */ | |
10164 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds | |
10165 | * (mips_opts.mips16 ? 2 : 4)); | |
10166 | prev_nop_frag = NULL; | |
10167 | } | |
10168 | mips_opts.noreorder = 0; | |
10169 | } | |
10170 | else if (strcmp (name, "noreorder") == 0) | |
10171 | { | |
10172 | mips_emit_delays (true); | |
10173 | mips_opts.noreorder = 1; | |
10174 | mips_any_noreorder = 1; | |
10175 | } | |
10176 | else if (strcmp (name, "at") == 0) | |
10177 | { | |
10178 | mips_opts.noat = 0; | |
10179 | } | |
10180 | else if (strcmp (name, "noat") == 0) | |
10181 | { | |
10182 | mips_opts.noat = 1; | |
10183 | } | |
10184 | else if (strcmp (name, "macro") == 0) | |
10185 | { | |
10186 | mips_opts.warn_about_macros = 0; | |
10187 | } | |
10188 | else if (strcmp (name, "nomacro") == 0) | |
10189 | { | |
10190 | if (mips_opts.noreorder == 0) | |
10191 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
10192 | mips_opts.warn_about_macros = 1; | |
10193 | } | |
10194 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) | |
10195 | { | |
10196 | mips_opts.nomove = 0; | |
10197 | } | |
10198 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) | |
10199 | { | |
10200 | mips_opts.nomove = 1; | |
10201 | } | |
10202 | else if (strcmp (name, "bopt") == 0) | |
10203 | { | |
10204 | mips_opts.nobopt = 0; | |
10205 | } | |
10206 | else if (strcmp (name, "nobopt") == 0) | |
10207 | { | |
10208 | mips_opts.nobopt = 1; | |
10209 | } | |
10210 | else if (strcmp (name, "mips16") == 0 | |
10211 | || strcmp (name, "MIPS-16") == 0) | |
10212 | mips_opts.mips16 = 1; | |
10213 | else if (strcmp (name, "nomips16") == 0 | |
10214 | || strcmp (name, "noMIPS-16") == 0) | |
10215 | mips_opts.mips16 = 0; | |
10216 | else if (strncmp (name, "mips", 4) == 0) | |
10217 | { | |
10218 | int isa; | |
10219 | ||
10220 | /* Permit the user to change the ISA on the fly. Needless to | |
10221 | say, misuse can cause serious problems. */ | |
10222 | isa = atoi (name + 4); | |
10223 | if (isa == 0) | |
10224 | mips_opts.isa = file_mips_isa; | |
10225 | else if (isa < 1 || isa > 4) | |
10226 | as_bad (_("unknown ISA level")); | |
10227 | else | |
10228 | mips_opts.isa = isa; | |
10229 | } | |
10230 | else if (strcmp (name, "autoextend") == 0) | |
10231 | mips_opts.noautoextend = 0; | |
10232 | else if (strcmp (name, "noautoextend") == 0) | |
10233 | mips_opts.noautoextend = 1; | |
10234 | else if (strcmp (name, "push") == 0) | |
10235 | { | |
10236 | struct mips_option_stack *s; | |
10237 | ||
10238 | s = (struct mips_option_stack *) xmalloc (sizeof *s); | |
10239 | s->next = mips_opts_stack; | |
10240 | s->options = mips_opts; | |
10241 | mips_opts_stack = s; | |
10242 | } | |
10243 | else if (strcmp (name, "pop") == 0) | |
10244 | { | |
10245 | struct mips_option_stack *s; | |
10246 | ||
10247 | s = mips_opts_stack; | |
10248 | if (s == NULL) | |
10249 | as_bad (_(".set pop with no .set push")); | |
10250 | else | |
10251 | { | |
10252 | /* If we're changing the reorder mode we need to handle | |
10253 | delay slots correctly. */ | |
10254 | if (s->options.noreorder && ! mips_opts.noreorder) | |
10255 | mips_emit_delays (true); | |
10256 | else if (! s->options.noreorder && mips_opts.noreorder) | |
10257 | { | |
10258 | if (prev_nop_frag != NULL) | |
10259 | { | |
10260 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds | |
10261 | * (mips_opts.mips16 ? 2 : 4)); | |
10262 | prev_nop_frag = NULL; | |
10263 | } | |
10264 | } | |
10265 | ||
10266 | mips_opts = s->options; | |
10267 | mips_opts_stack = s->next; | |
10268 | free (s); | |
10269 | } | |
10270 | } | |
10271 | else | |
10272 | { | |
10273 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); | |
10274 | } | |
10275 | *input_line_pointer = ch; | |
10276 | demand_empty_rest_of_line (); | |
10277 | } | |
10278 | ||
10279 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
10280 | .option pic2. It means to generate SVR4 PIC calls. */ | |
10281 | ||
10282 | static void | |
10283 | s_abicalls (ignore) | |
10284 | int ignore; | |
10285 | { | |
10286 | mips_pic = SVR4_PIC; | |
10287 | if (USE_GLOBAL_POINTER_OPT) | |
10288 | { | |
10289 | if (g_switch_seen && g_switch_value != 0) | |
10290 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
10291 | g_switch_value = 0; | |
10292 | } | |
10293 | bfd_set_gp_size (stdoutput, 0); | |
10294 | demand_empty_rest_of_line (); | |
10295 | } | |
10296 | ||
10297 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
10298 | PIC code. It sets the $gp register for the function based on the | |
10299 | function address, which is in the register named in the argument. | |
10300 | This uses a relocation against _gp_disp, which is handled specially | |
10301 | by the linker. The result is: | |
10302 | lui $gp,%hi(_gp_disp) | |
10303 | addiu $gp,$gp,%lo(_gp_disp) | |
10304 | addu $gp,$gp,.cpload argument | |
10305 | The .cpload argument is normally $25 == $t9. */ | |
10306 | ||
10307 | static void | |
10308 | s_cpload (ignore) | |
10309 | int ignore; | |
10310 | { | |
10311 | expressionS ex; | |
10312 | int icnt = 0; | |
10313 | ||
10314 | /* If we are not generating SVR4 PIC code, .cpload is ignored. */ | |
10315 | if (mips_pic != SVR4_PIC) | |
10316 | { | |
10317 | s_ignore (0); | |
10318 | return; | |
10319 | } | |
10320 | ||
10321 | /* .cpload should be a in .set noreorder section. */ | |
10322 | if (mips_opts.noreorder == 0) | |
10323 | as_warn (_(".cpload not in noreorder section")); | |
10324 | ||
10325 | ex.X_op = O_symbol; | |
10326 | ex.X_add_symbol = symbol_find_or_make ("_gp_disp"); | |
10327 | ex.X_op_symbol = NULL; | |
10328 | ex.X_add_number = 0; | |
10329 | ||
10330 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 10331 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 RH |
10332 | |
10333 | macro_build_lui ((char *) NULL, &icnt, &ex, GP); | |
10334 | macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j", GP, GP, | |
10335 | (int) BFD_RELOC_LO16); | |
10336 | ||
10337 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t", | |
10338 | GP, GP, tc_get_register (0)); | |
10339 | ||
10340 | demand_empty_rest_of_line (); | |
10341 | } | |
10342 | ||
10343 | /* Handle the .cprestore pseudo-op. This stores $gp into a given | |
10344 | offset from $sp. The offset is remembered, and after making a PIC | |
10345 | call $gp is restored from that location. */ | |
10346 | ||
10347 | static void | |
10348 | s_cprestore (ignore) | |
10349 | int ignore; | |
10350 | { | |
10351 | expressionS ex; | |
10352 | int icnt = 0; | |
10353 | ||
10354 | /* If we are not generating SVR4 PIC code, .cprestore is ignored. */ | |
10355 | if (mips_pic != SVR4_PIC) | |
10356 | { | |
10357 | s_ignore (0); | |
10358 | return; | |
10359 | } | |
10360 | ||
10361 | mips_cprestore_offset = get_absolute_expression (); | |
10362 | ||
10363 | ex.X_op = O_constant; | |
10364 | ex.X_add_symbol = NULL; | |
10365 | ex.X_op_symbol = NULL; | |
10366 | ex.X_add_number = mips_cprestore_offset; | |
10367 | ||
10368 | macro_build ((char *) NULL, &icnt, &ex, | |
10369 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 10370 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
10371 | ? "sw" : "sd"), |
10372 | "t,o(b)", GP, (int) BFD_RELOC_LO16, SP); | |
10373 | ||
10374 | demand_empty_rest_of_line (); | |
10375 | } | |
10376 | ||
10377 | /* Handle the .gpword pseudo-op. This is used when generating PIC | |
10378 | code. It generates a 32 bit GP relative reloc. */ | |
10379 | ||
10380 | static void | |
10381 | s_gpword (ignore) | |
10382 | int ignore; | |
10383 | { | |
10384 | symbolS *label; | |
10385 | expressionS ex; | |
10386 | char *p; | |
10387 | ||
10388 | /* When not generating PIC code, this is treated as .word. */ | |
10389 | if (mips_pic != SVR4_PIC) | |
10390 | { | |
10391 | s_cons (2); | |
10392 | return; | |
10393 | } | |
10394 | ||
10395 | label = insn_labels != NULL ? insn_labels->label : NULL; | |
10396 | mips_emit_delays (true); | |
10397 | if (auto_align) | |
10398 | mips_align (2, 0, label); | |
10399 | mips_clear_insn_labels (); | |
10400 | ||
10401 | expression (&ex); | |
10402 | ||
10403 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
10404 | { | |
10405 | as_bad (_("Unsupported use of .gpword")); | |
10406 | ignore_rest_of_line (); | |
10407 | } | |
10408 | ||
10409 | p = frag_more (4); | |
10410 | md_number_to_chars (p, (valueT) 0, 4); | |
10411 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, 0, | |
10412 | BFD_RELOC_MIPS_GPREL32); | |
10413 | ||
10414 | demand_empty_rest_of_line (); | |
10415 | } | |
10416 | ||
10417 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch | |
10418 | tables in SVR4 PIC code. */ | |
10419 | ||
10420 | static void | |
10421 | s_cpadd (ignore) | |
10422 | int ignore; | |
10423 | { | |
10424 | int icnt = 0; | |
10425 | int reg; | |
10426 | ||
10427 | /* This is ignored when not generating SVR4 PIC code. */ | |
10428 | if (mips_pic != SVR4_PIC) | |
10429 | { | |
10430 | s_ignore (0); | |
10431 | return; | |
10432 | } | |
10433 | ||
10434 | /* Add $gp to the register named as an argument. */ | |
10435 | reg = tc_get_register (0); | |
10436 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, | |
10437 | ((bfd_arch_bits_per_address (stdoutput) == 32 | |
9ce8a5dd | 10438 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
252b5132 RH |
10439 | ? "addu" : "daddu"), |
10440 | "d,v,t", reg, reg, GP); | |
10441 | ||
10442 | demand_empty_rest_of_line (); | |
10443 | } | |
10444 | ||
10445 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
10446 | mips16 mode. This permits the linker to handle them specially, | |
10447 | such as generating jalx instructions when needed. We also make | |
10448 | them odd for the duration of the assembly, in order to generate the | |
10449 | right sort of code. We will make them even in the adjust_symtab | |
10450 | routine, while leaving them marked. This is convenient for the | |
10451 | debugger and the disassembler. The linker knows to make them odd | |
10452 | again. */ | |
10453 | ||
10454 | static void | |
10455 | s_insn (ignore) | |
10456 | int ignore; | |
10457 | { | |
10458 | if (mips_opts.mips16) | |
10459 | mips16_mark_labels (); | |
10460 | ||
10461 | demand_empty_rest_of_line (); | |
10462 | } | |
10463 | ||
10464 | /* Handle a .stabn directive. We need these in order to mark a label | |
10465 | as being a mips16 text label correctly. Sometimes the compiler | |
10466 | will emit a label, followed by a .stabn, and then switch sections. | |
10467 | If the label and .stabn are in mips16 mode, then the label is | |
10468 | really a mips16 text label. */ | |
10469 | ||
10470 | static void | |
10471 | s_mips_stab (type) | |
10472 | int type; | |
10473 | { | |
10474 | if (type == 'n' && mips_opts.mips16) | |
10475 | mips16_mark_labels (); | |
10476 | ||
10477 | s_stab (type); | |
10478 | } | |
10479 | ||
10480 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. | |
10481 | */ | |
10482 | ||
10483 | static void | |
10484 | s_mips_weakext (ignore) | |
10485 | int ignore; | |
10486 | { | |
10487 | char *name; | |
10488 | int c; | |
10489 | symbolS *symbolP; | |
10490 | expressionS exp; | |
10491 | ||
10492 | name = input_line_pointer; | |
10493 | c = get_symbol_end (); | |
10494 | symbolP = symbol_find_or_make (name); | |
10495 | S_SET_WEAK (symbolP); | |
10496 | *input_line_pointer = c; | |
10497 | ||
10498 | SKIP_WHITESPACE (); | |
10499 | ||
10500 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
10501 | { | |
10502 | if (S_IS_DEFINED (symbolP)) | |
10503 | { | |
10504 | as_bad ("Ignoring attempt to redefine symbol `%s'.", | |
10505 | S_GET_NAME (symbolP)); | |
10506 | ignore_rest_of_line (); | |
10507 | return; | |
10508 | } | |
10509 | ||
10510 | if (*input_line_pointer == ',') | |
10511 | { | |
10512 | ++input_line_pointer; | |
10513 | SKIP_WHITESPACE (); | |
10514 | } | |
10515 | ||
10516 | expression (&exp); | |
10517 | if (exp.X_op != O_symbol) | |
10518 | { | |
10519 | as_bad ("bad .weakext directive"); | |
10520 | ignore_rest_of_line(); | |
10521 | return; | |
10522 | } | |
49309057 | 10523 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
10524 | } |
10525 | ||
10526 | demand_empty_rest_of_line (); | |
10527 | } | |
10528 | ||
10529 | /* Parse a register string into a number. Called from the ECOFF code | |
10530 | to parse .frame. The argument is non-zero if this is the frame | |
10531 | register, so that we can record it in mips_frame_reg. */ | |
10532 | ||
10533 | int | |
10534 | tc_get_register (frame) | |
10535 | int frame; | |
10536 | { | |
10537 | int reg; | |
10538 | ||
10539 | SKIP_WHITESPACE (); | |
10540 | if (*input_line_pointer++ != '$') | |
10541 | { | |
10542 | as_warn (_("expected `$'")); | |
10543 | reg = 0; | |
10544 | } | |
10545 | else if (isdigit ((unsigned char) *input_line_pointer)) | |
10546 | { | |
10547 | reg = get_absolute_expression (); | |
10548 | if (reg < 0 || reg >= 32) | |
10549 | { | |
10550 | as_warn (_("Bad register number")); | |
10551 | reg = 0; | |
10552 | } | |
10553 | } | |
10554 | else | |
10555 | { | |
10556 | if (strncmp (input_line_pointer, "fp", 2) == 0) | |
10557 | reg = FP; | |
10558 | else if (strncmp (input_line_pointer, "sp", 2) == 0) | |
10559 | reg = SP; | |
10560 | else if (strncmp (input_line_pointer, "gp", 2) == 0) | |
10561 | reg = GP; | |
10562 | else if (strncmp (input_line_pointer, "at", 2) == 0) | |
10563 | reg = AT; | |
10564 | else | |
10565 | { | |
10566 | as_warn (_("Unrecognized register name")); | |
10567 | reg = 0; | |
10568 | } | |
10569 | input_line_pointer += 2; | |
10570 | } | |
10571 | if (frame) | |
10572 | mips_frame_reg = reg != 0 ? reg : SP; | |
10573 | return reg; | |
10574 | } | |
10575 | ||
10576 | valueT | |
10577 | md_section_align (seg, addr) | |
10578 | asection *seg; | |
10579 | valueT addr; | |
10580 | { | |
10581 | int align = bfd_get_section_alignment (stdoutput, seg); | |
10582 | ||
10583 | #ifdef OBJ_ELF | |
10584 | /* We don't need to align ELF sections to the full alignment. | |
10585 | However, Irix 5 may prefer that we align them at least to a 16 | |
10586 | byte boundary. We don't bother to align the sections if we are | |
10587 | targeted for an embedded system. */ | |
10588 | if (strcmp (TARGET_OS, "elf") == 0) | |
10589 | return addr; | |
10590 | if (align > 4) | |
10591 | align = 4; | |
10592 | #endif | |
10593 | ||
10594 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
10595 | } | |
10596 | ||
10597 | /* Utility routine, called from above as well. If called while the | |
10598 | input file is still being read, it's only an approximation. (For | |
10599 | example, a symbol may later become defined which appeared to be | |
10600 | undefined earlier.) */ | |
10601 | ||
10602 | static int | |
10603 | nopic_need_relax (sym, before_relaxing) | |
10604 | symbolS *sym; | |
10605 | int before_relaxing; | |
10606 | { | |
10607 | if (sym == 0) | |
10608 | return 0; | |
10609 | ||
10610 | if (USE_GLOBAL_POINTER_OPT) | |
10611 | { | |
10612 | const char *symname; | |
10613 | int change; | |
10614 | ||
10615 | /* Find out whether this symbol can be referenced off the GP | |
10616 | register. It can be if it is smaller than the -G size or if | |
10617 | it is in the .sdata or .sbss section. Certain symbols can | |
10618 | not be referenced off the GP, although it appears as though | |
10619 | they can. */ | |
10620 | symname = S_GET_NAME (sym); | |
10621 | if (symname != (const char *) NULL | |
10622 | && (strcmp (symname, "eprol") == 0 | |
10623 | || strcmp (symname, "etext") == 0 | |
10624 | || strcmp (symname, "_gp") == 0 | |
10625 | || strcmp (symname, "edata") == 0 | |
10626 | || strcmp (symname, "_fbss") == 0 | |
10627 | || strcmp (symname, "_fdata") == 0 | |
10628 | || strcmp (symname, "_ftext") == 0 | |
10629 | || strcmp (symname, "end") == 0 | |
10630 | || strcmp (symname, "_gp_disp") == 0)) | |
10631 | change = 1; | |
10632 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
10633 | && (0 | |
10634 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
10635 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
10636 | && (symbol_get_obj (sym)->ecoff_extern_size | |
10637 | <= g_switch_value)) | |
252b5132 RH |
10638 | #endif |
10639 | /* We must defer this decision until after the whole | |
10640 | file has been read, since there might be a .extern | |
10641 | after the first use of this symbol. */ | |
10642 | || (before_relaxing | |
10643 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 10644 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
10645 | #endif |
10646 | && S_GET_VALUE (sym) == 0) | |
10647 | || (S_GET_VALUE (sym) != 0 | |
10648 | && S_GET_VALUE (sym) <= g_switch_value))) | |
10649 | change = 0; | |
10650 | else | |
10651 | { | |
10652 | const char *segname; | |
10653 | ||
10654 | segname = segment_name (S_GET_SEGMENT (sym)); | |
10655 | assert (strcmp (segname, ".lit8") != 0 | |
10656 | && strcmp (segname, ".lit4") != 0); | |
10657 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
10658 | && strcmp (segname, ".sbss") != 0 |
10659 | && strncmp (segname, ".sdata.", 7) != 0 | |
10660 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); | |
252b5132 RH |
10661 | } |
10662 | return change; | |
10663 | } | |
10664 | else | |
10665 | /* We are not optimizing for the GP register. */ | |
10666 | return 1; | |
10667 | } | |
10668 | ||
10669 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an | |
10670 | extended opcode. SEC is the section the frag is in. */ | |
10671 | ||
10672 | static int | |
10673 | mips16_extended_frag (fragp, sec, stretch) | |
10674 | fragS *fragp; | |
10675 | asection *sec; | |
10676 | long stretch; | |
10677 | { | |
10678 | int type; | |
10679 | register const struct mips16_immed_operand *op; | |
10680 | offsetT val; | |
10681 | int mintiny, maxtiny; | |
10682 | segT symsec; | |
10683 | ||
10684 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
10685 | return 0; | |
10686 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
10687 | return 1; | |
10688 | ||
10689 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
10690 | op = mips16_immed_operands; | |
10691 | while (op->type != type) | |
10692 | { | |
10693 | ++op; | |
10694 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); | |
10695 | } | |
10696 | ||
10697 | if (op->unsp) | |
10698 | { | |
10699 | if (type == '<' || type == '>' || type == '[' || type == ']') | |
10700 | { | |
10701 | mintiny = 1; | |
10702 | maxtiny = 1 << op->nbits; | |
10703 | } | |
10704 | else | |
10705 | { | |
10706 | mintiny = 0; | |
10707 | maxtiny = (1 << op->nbits) - 1; | |
10708 | } | |
10709 | } | |
10710 | else | |
10711 | { | |
10712 | mintiny = - (1 << (op->nbits - 1)); | |
10713 | maxtiny = (1 << (op->nbits - 1)) - 1; | |
10714 | } | |
10715 | ||
49309057 ILT |
10716 | /* We can't always call S_GET_VALUE here, because we don't want to |
10717 | lock in a particular frag address. */ | |
10718 | if (symbol_constant_p (fragp->fr_symbol)) | |
252b5132 | 10719 | { |
49309057 ILT |
10720 | val = (S_GET_VALUE (fragp->fr_symbol) |
10721 | + symbol_get_frag (fragp->fr_symbol)->fr_address); | |
252b5132 RH |
10722 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
10723 | } | |
49309057 ILT |
10724 | else if (symbol_equated_p (fragp->fr_symbol) |
10725 | && (symbol_constant_p | |
10726 | (symbol_get_value_expression (fragp->fr_symbol)->X_add_symbol))) | |
252b5132 | 10727 | { |
49309057 ILT |
10728 | symbolS *eqsym; |
10729 | ||
10730 | eqsym = symbol_get_value_expression (fragp->fr_symbol)->X_add_symbol; | |
10731 | val = (S_GET_VALUE (eqsym) | |
10732 | + symbol_get_frag (eqsym)->fr_address | |
10733 | + symbol_get_value_expression (fragp->fr_symbol)->X_add_number | |
10734 | + symbol_get_frag (fragp->fr_symbol)->fr_address); | |
10735 | symsec = S_GET_SEGMENT (eqsym); | |
252b5132 RH |
10736 | } |
10737 | else | |
10738 | return 1; | |
10739 | ||
10740 | if (op->pcrel) | |
10741 | { | |
10742 | addressT addr; | |
10743 | ||
10744 | /* We won't have the section when we are called from | |
10745 | mips_relax_frag. However, we will always have been called | |
10746 | from md_estimate_size_before_relax first. If this is a | |
10747 | branch to a different section, we mark it as such. If SEC is | |
10748 | NULL, and the frag is not marked, then it must be a branch to | |
10749 | the same section. */ | |
10750 | if (sec == NULL) | |
10751 | { | |
10752 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) | |
10753 | return 1; | |
10754 | } | |
10755 | else | |
10756 | { | |
10757 | if (symsec != sec) | |
10758 | { | |
10759 | fragp->fr_subtype = | |
10760 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
10761 | ||
10762 | /* FIXME: We should support this, and let the linker | |
10763 | catch branches and loads that are out of range. */ | |
10764 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
10765 | _("unsupported PC relative reference to different section")); | |
10766 | ||
10767 | return 1; | |
10768 | } | |
10769 | } | |
10770 | ||
10771 | /* In this case, we know for sure that the symbol fragment is in | |
10772 | the same section. If the fr_address of the symbol fragment | |
10773 | is greater then the address of this fragment we want to add | |
10774 | in STRETCH in order to get a better estimate of the address. | |
10775 | This particularly matters because of the shift bits. */ | |
10776 | if (stretch != 0 | |
49309057 ILT |
10777 | && (symbol_get_frag (fragp->fr_symbol)->fr_address |
10778 | >= fragp->fr_address)) | |
252b5132 RH |
10779 | { |
10780 | fragS *f; | |
10781 | ||
10782 | /* Adjust stretch for any alignment frag. Note that if have | |
10783 | been expanding the earlier code, the symbol may be | |
10784 | defined in what appears to be an earlier frag. FIXME: | |
10785 | This doesn't handle the fr_subtype field, which specifies | |
10786 | a maximum number of bytes to skip when doing an | |
10787 | alignment. */ | |
10788 | for (f = fragp; | |
49309057 | 10789 | f != NULL && f != symbol_get_frag (fragp->fr_symbol); |
252b5132 RH |
10790 | f = f->fr_next) |
10791 | { | |
10792 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
10793 | { | |
10794 | if (stretch < 0) | |
10795 | stretch = - ((- stretch) | |
10796 | & ~ ((1 << (int) f->fr_offset) - 1)); | |
10797 | else | |
10798 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); | |
10799 | if (stretch == 0) | |
10800 | break; | |
10801 | } | |
10802 | } | |
10803 | if (f != NULL) | |
10804 | val += stretch; | |
10805 | } | |
10806 | ||
10807 | addr = fragp->fr_address + fragp->fr_fix; | |
10808 | ||
10809 | /* The base address rules are complicated. The base address of | |
10810 | a branch is the following instruction. The base address of a | |
10811 | PC relative load or add is the instruction itself, but if it | |
10812 | is in a delay slot (in which case it can not be extended) use | |
10813 | the address of the instruction whose delay slot it is in. */ | |
10814 | if (type == 'p' || type == 'q') | |
10815 | { | |
10816 | addr += 2; | |
10817 | ||
10818 | /* If we are currently assuming that this frag should be | |
10819 | extended, then, the current address is two bytes | |
10820 | higher. */ | |
10821 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
10822 | addr += 2; | |
10823 | ||
10824 | /* Ignore the low bit in the target, since it will be set | |
10825 | for a text label. */ | |
10826 | if ((val & 1) != 0) | |
10827 | --val; | |
10828 | } | |
10829 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
10830 | addr -= 4; | |
10831 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
10832 | addr -= 2; | |
10833 | ||
10834 | val -= addr & ~ ((1 << op->shift) - 1); | |
10835 | ||
10836 | /* Branch offsets have an implicit 0 in the lowest bit. */ | |
10837 | if (type == 'p' || type == 'q') | |
10838 | val /= 2; | |
10839 | ||
10840 | /* If any of the shifted bits are set, we must use an extended | |
10841 | opcode. If the address depends on the size of this | |
10842 | instruction, this can lead to a loop, so we arrange to always | |
10843 | use an extended opcode. We only check this when we are in | |
10844 | the main relaxation loop, when SEC is NULL. */ | |
10845 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) | |
10846 | { | |
10847 | fragp->fr_subtype = | |
10848 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
10849 | return 1; | |
10850 | } | |
10851 | ||
10852 | /* If we are about to mark a frag as extended because the value | |
10853 | is precisely maxtiny + 1, then there is a chance of an | |
10854 | infinite loop as in the following code: | |
10855 | la $4,foo | |
10856 | .skip 1020 | |
10857 | .align 2 | |
10858 | foo: | |
10859 | In this case when the la is extended, foo is 0x3fc bytes | |
10860 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
10861 | the la must be extended. To avoid this loop, we mark the | |
10862 | frag as extended if it was small, and is about to become | |
10863 | extended with a value of maxtiny + 1. */ | |
10864 | if (val == ((maxtiny + 1) << op->shift) | |
10865 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) | |
10866 | && sec == NULL) | |
10867 | { | |
10868 | fragp->fr_subtype = | |
10869 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); | |
10870 | return 1; | |
10871 | } | |
10872 | } | |
10873 | else if (symsec != absolute_section && sec != NULL) | |
10874 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); | |
10875 | ||
10876 | if ((val & ((1 << op->shift) - 1)) != 0 | |
10877 | || val < (mintiny << op->shift) | |
10878 | || val > (maxtiny << op->shift)) | |
10879 | return 1; | |
10880 | else | |
10881 | return 0; | |
10882 | } | |
10883 | ||
10884 | /* Estimate the size of a frag before relaxing. Unless this is the | |
10885 | mips16, we are not really relaxing here, and the final size is | |
10886 | encoded in the subtype information. For the mips16, we have to | |
10887 | decide whether we are using an extended opcode or not. */ | |
10888 | ||
10889 | /*ARGSUSED*/ | |
10890 | int | |
10891 | md_estimate_size_before_relax (fragp, segtype) | |
10892 | fragS *fragp; | |
10893 | asection *segtype; | |
10894 | { | |
10895 | int change; | |
10896 | ||
10897 | if (RELAX_MIPS16_P (fragp->fr_subtype)) | |
10898 | { | |
10899 | if (mips16_extended_frag (fragp, segtype, 0)) | |
10900 | { | |
10901 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
10902 | return 4; | |
10903 | } | |
10904 | else | |
10905 | { | |
10906 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
10907 | return 2; | |
10908 | } | |
10909 | } | |
10910 | ||
10911 | if (mips_pic == NO_PIC) | |
10912 | { | |
10913 | change = nopic_need_relax (fragp->fr_symbol, 0); | |
10914 | } | |
10915 | else if (mips_pic == SVR4_PIC) | |
10916 | { | |
10917 | symbolS *sym; | |
10918 | asection *symsec; | |
10919 | ||
10920 | sym = fragp->fr_symbol; | |
10921 | ||
10922 | /* Handle the case of a symbol equated to another symbol. */ | |
49309057 | 10923 | while (symbol_equated_p (sym) |
252b5132 RH |
10924 | && (! S_IS_DEFINED (sym) || S_IS_COMMON (sym))) |
10925 | { | |
10926 | symbolS *n; | |
10927 | ||
10928 | /* It's possible to get a loop here in a badly written | |
10929 | program. */ | |
49309057 | 10930 | n = symbol_get_value_expression (sym)->X_add_symbol; |
252b5132 RH |
10931 | if (n == sym) |
10932 | break; | |
10933 | sym = n; | |
10934 | } | |
10935 | ||
10936 | symsec = S_GET_SEGMENT (sym); | |
10937 | ||
10938 | /* This must duplicate the test in adjust_reloc_syms. */ | |
10939 | change = (symsec != &bfd_und_section | |
10940 | && symsec != &bfd_abs_section | |
10941 | && ! bfd_is_com_section (symsec)); | |
10942 | } | |
10943 | else | |
10944 | abort (); | |
10945 | ||
10946 | if (change) | |
10947 | { | |
10948 | /* Record the offset to the first reloc in the fr_opcode field. | |
10949 | This lets md_convert_frag and tc_gen_reloc know that the code | |
10950 | must be expanded. */ | |
10951 | fragp->fr_opcode = (fragp->fr_literal | |
10952 | + fragp->fr_fix | |
10953 | - RELAX_OLD (fragp->fr_subtype) | |
10954 | + RELAX_RELOC1 (fragp->fr_subtype)); | |
10955 | /* FIXME: This really needs as_warn_where. */ | |
10956 | if (RELAX_WARN (fragp->fr_subtype)) | |
10957 | as_warn (_("AT used after \".set noat\" or macro used after \".set nomacro\"")); | |
10958 | } | |
10959 | ||
10960 | if (! change) | |
10961 | return 0; | |
10962 | else | |
10963 | return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype); | |
10964 | } | |
10965 | ||
10966 | /* This is called to see whether a reloc against a defined symbol | |
10967 | should be converted into a reloc against a section. Don't adjust | |
10968 | MIPS16 jump relocations, so we don't have to worry about the format | |
10969 | of the offset in the .o file. Don't adjust relocations against | |
10970 | mips16 symbols, so that the linker can find them if it needs to set | |
10971 | up a stub. */ | |
10972 | ||
10973 | int | |
10974 | mips_fix_adjustable (fixp) | |
10975 | fixS *fixp; | |
10976 | { | |
10977 | if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) | |
10978 | return 0; | |
10979 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
10980 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
10981 | return 0; | |
10982 | if (fixp->fx_addsy == NULL) | |
10983 | return 1; | |
10984 | #ifdef OBJ_ELF | |
10985 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
10986 | && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 | |
10987 | && fixp->fx_subsy == NULL) | |
10988 | return 0; | |
10989 | #endif | |
10990 | return 1; | |
10991 | } | |
10992 | ||
10993 | /* Translate internal representation of relocation info to BFD target | |
10994 | format. */ | |
10995 | ||
10996 | arelent ** | |
10997 | tc_gen_reloc (section, fixp) | |
10998 | asection *section; | |
10999 | fixS *fixp; | |
11000 | { | |
11001 | static arelent *retval[4]; | |
11002 | arelent *reloc; | |
11003 | bfd_reloc_code_real_type code; | |
11004 | ||
11005 | reloc = retval[0] = (arelent *) xmalloc (sizeof (arelent)); | |
11006 | retval[1] = NULL; | |
11007 | ||
49309057 ILT |
11008 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
11009 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
11010 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
11011 | ||
11012 | if (mips_pic == EMBEDDED_PIC | |
11013 | && SWITCH_TABLE (fixp)) | |
11014 | { | |
11015 | /* For a switch table entry we use a special reloc. The addend | |
11016 | is actually the difference between the reloc address and the | |
11017 | subtrahend. */ | |
11018 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); | |
11019 | if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour) | |
11020 | as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc")); | |
11021 | fixp->fx_r_type = BFD_RELOC_GPREL32; | |
11022 | } | |
11023 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16) | |
11024 | { | |
11025 | /* We use a special addend for an internal RELLO reloc. */ | |
49309057 | 11026 | if (symbol_section_p (fixp->fx_addsy)) |
252b5132 RH |
11027 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); |
11028 | else | |
11029 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
11030 | } | |
11031 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S) | |
11032 | { | |
11033 | assert (fixp->fx_next != NULL | |
11034 | && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16); | |
11035 | /* We use a special addend for an internal RELHI reloc. The | |
11036 | reloc is relative to the RELLO; adjust the addend | |
11037 | accordingly. */ | |
49309057 | 11038 | if (symbol_section_p (fixp->fx_addsy)) |
252b5132 RH |
11039 | reloc->addend = (fixp->fx_next->fx_frag->fr_address |
11040 | + fixp->fx_next->fx_where | |
11041 | - S_GET_VALUE (fixp->fx_subsy)); | |
11042 | else | |
11043 | reloc->addend = (fixp->fx_addnumber | |
11044 | + fixp->fx_next->fx_frag->fr_address | |
11045 | + fixp->fx_next->fx_where); | |
11046 | } | |
11047 | else if (fixp->fx_pcrel == 0) | |
11048 | reloc->addend = fixp->fx_addnumber; | |
11049 | else | |
11050 | { | |
11051 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour) | |
11052 | /* A gruesome hack which is a result of the gruesome gas reloc | |
11053 | handling. */ | |
11054 | reloc->addend = reloc->address; | |
11055 | else | |
11056 | reloc->addend = -reloc->address; | |
11057 | } | |
11058 | ||
11059 | /* If this is a variant frag, we may need to adjust the existing | |
11060 | reloc and generate a new one. */ | |
11061 | if (fixp->fx_frag->fr_opcode != NULL | |
11062 | && (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL | |
11063 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 | |
11064 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16 | |
11065 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
11066 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16 | |
11067 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
11068 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16)) | |
11069 | { | |
11070 | arelent *reloc2; | |
11071 | ||
11072 | assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype)); | |
11073 | ||
11074 | /* If this is not the last reloc in this frag, then we have two | |
11075 | GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a | |
11076 | CALL_HI16/CALL_LO16, both of which are being replaced. Let | |
11077 | the second one handle all of them. */ | |
11078 | if (fixp->fx_next != NULL | |
11079 | && fixp->fx_frag == fixp->fx_next->fx_frag) | |
11080 | { | |
11081 | assert ((fixp->fx_r_type == BFD_RELOC_MIPS_GPREL | |
11082 | && fixp->fx_next->fx_r_type == BFD_RELOC_MIPS_GPREL) | |
11083 | || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 | |
11084 | && (fixp->fx_next->fx_r_type | |
11085 | == BFD_RELOC_MIPS_GOT_LO16)) | |
11086 | || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 | |
11087 | && (fixp->fx_next->fx_r_type | |
11088 | == BFD_RELOC_MIPS_CALL_LO16))); | |
11089 | retval[0] = NULL; | |
11090 | return retval; | |
11091 | } | |
11092 | ||
11093 | fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal; | |
11094 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
11095 | reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent)); | |
11096 | retval[2] = NULL; | |
49309057 ILT |
11097 | reloc2->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
11098 | *reloc2->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
11099 | reloc2->address = (reloc->address |
11100 | + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype) | |
11101 | - RELAX_RELOC1 (fixp->fx_frag->fr_subtype))); | |
11102 | reloc2->addend = fixp->fx_addnumber; | |
11103 | reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16); | |
11104 | assert (reloc2->howto != NULL); | |
11105 | ||
11106 | if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype)) | |
11107 | { | |
11108 | arelent *reloc3; | |
11109 | ||
11110 | reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent)); | |
11111 | retval[3] = NULL; | |
11112 | *reloc3 = *reloc2; | |
11113 | reloc3->address += 4; | |
11114 | } | |
11115 | ||
11116 | if (mips_pic == NO_PIC) | |
11117 | { | |
11118 | assert (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL); | |
11119 | fixp->fx_r_type = BFD_RELOC_HI16_S; | |
11120 | } | |
11121 | else if (mips_pic == SVR4_PIC) | |
11122 | { | |
11123 | switch (fixp->fx_r_type) | |
11124 | { | |
11125 | default: | |
11126 | abort (); | |
11127 | case BFD_RELOC_MIPS_GOT16: | |
11128 | break; | |
11129 | case BFD_RELOC_MIPS_CALL16: | |
11130 | case BFD_RELOC_MIPS_GOT_LO16: | |
11131 | case BFD_RELOC_MIPS_CALL_LO16: | |
11132 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT16; | |
11133 | break; | |
11134 | } | |
11135 | } | |
11136 | else | |
11137 | abort (); | |
11138 | } | |
11139 | ||
11140 | /* Since MIPS ELF uses Rel instead of Rela, encode the vtable entry | |
11141 | to be used in the relocation's section offset. */ | |
11142 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
11143 | { | |
11144 | reloc->address = reloc->addend; | |
11145 | reloc->addend = 0; | |
11146 | } | |
11147 | ||
11148 | /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that | |
11149 | fixup_segment converted a non-PC relative reloc into a PC | |
11150 | relative reloc. In such a case, we need to convert the reloc | |
11151 | code. */ | |
11152 | code = fixp->fx_r_type; | |
11153 | if (fixp->fx_pcrel) | |
11154 | { | |
11155 | switch (code) | |
11156 | { | |
11157 | case BFD_RELOC_8: | |
11158 | code = BFD_RELOC_8_PCREL; | |
11159 | break; | |
11160 | case BFD_RELOC_16: | |
11161 | code = BFD_RELOC_16_PCREL; | |
11162 | break; | |
11163 | case BFD_RELOC_32: | |
11164 | code = BFD_RELOC_32_PCREL; | |
11165 | break; | |
11166 | case BFD_RELOC_64: | |
11167 | code = BFD_RELOC_64_PCREL; | |
11168 | break; | |
11169 | case BFD_RELOC_8_PCREL: | |
11170 | case BFD_RELOC_16_PCREL: | |
11171 | case BFD_RELOC_32_PCREL: | |
11172 | case BFD_RELOC_64_PCREL: | |
11173 | case BFD_RELOC_16_PCREL_S2: | |
11174 | case BFD_RELOC_PCREL_HI16_S: | |
11175 | case BFD_RELOC_PCREL_LO16: | |
11176 | break; | |
11177 | default: | |
11178 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
11179 | _("Cannot make %s relocation PC relative"), | |
11180 | bfd_get_reloc_code_name (code)); | |
11181 | } | |
11182 | } | |
11183 | ||
11184 | /* To support a PC relative reloc when generating embedded PIC code | |
11185 | for ECOFF, we use a Cygnus extension. We check for that here to | |
11186 | make sure that we don't let such a reloc escape normally. */ | |
11187 | if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour | |
11188 | && code == BFD_RELOC_16_PCREL_S2 | |
11189 | && mips_pic != EMBEDDED_PIC) | |
11190 | reloc->howto = NULL; | |
11191 | else | |
11192 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); | |
11193 | ||
11194 | if (reloc->howto == NULL) | |
11195 | { | |
11196 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
11197 | _("Can not represent %s relocation in this object file format"), | |
11198 | bfd_get_reloc_code_name (code)); | |
11199 | retval[0] = NULL; | |
11200 | } | |
11201 | ||
11202 | return retval; | |
11203 | } | |
11204 | ||
11205 | /* Relax a machine dependent frag. This returns the amount by which | |
11206 | the current size of the frag should change. */ | |
11207 | ||
11208 | int | |
11209 | mips_relax_frag (fragp, stretch) | |
11210 | fragS *fragp; | |
11211 | long stretch; | |
11212 | { | |
11213 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) | |
11214 | return 0; | |
11215 | ||
11216 | if (mips16_extended_frag (fragp, (asection *) NULL, stretch)) | |
11217 | { | |
11218 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
11219 | return 0; | |
11220 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
11221 | return 2; | |
11222 | } | |
11223 | else | |
11224 | { | |
11225 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
11226 | return 0; | |
11227 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
11228 | return -2; | |
11229 | } | |
11230 | ||
11231 | return 0; | |
11232 | } | |
11233 | ||
11234 | /* Convert a machine dependent frag. */ | |
11235 | ||
11236 | void | |
11237 | md_convert_frag (abfd, asec, fragp) | |
11238 | bfd *abfd; | |
11239 | segT asec; | |
11240 | fragS *fragp; | |
11241 | { | |
11242 | int old, new; | |
11243 | char *fixptr; | |
11244 | ||
11245 | if (RELAX_MIPS16_P (fragp->fr_subtype)) | |
11246 | { | |
11247 | int type; | |
11248 | register const struct mips16_immed_operand *op; | |
11249 | boolean small, ext; | |
11250 | offsetT val; | |
11251 | bfd_byte *buf; | |
11252 | unsigned long insn; | |
11253 | boolean use_extend; | |
11254 | unsigned short extend; | |
11255 | ||
11256 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
11257 | op = mips16_immed_operands; | |
11258 | while (op->type != type) | |
11259 | ++op; | |
11260 | ||
11261 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
11262 | { | |
11263 | small = false; | |
11264 | ext = true; | |
11265 | } | |
11266 | else | |
11267 | { | |
11268 | small = true; | |
11269 | ext = false; | |
11270 | } | |
11271 | ||
11272 | resolve_symbol_value (fragp->fr_symbol, 1); | |
11273 | val = S_GET_VALUE (fragp->fr_symbol); | |
11274 | if (op->pcrel) | |
11275 | { | |
11276 | addressT addr; | |
11277 | ||
11278 | addr = fragp->fr_address + fragp->fr_fix; | |
11279 | ||
11280 | /* The rules for the base address of a PC relative reloc are | |
11281 | complicated; see mips16_extended_frag. */ | |
11282 | if (type == 'p' || type == 'q') | |
11283 | { | |
11284 | addr += 2; | |
11285 | if (ext) | |
11286 | addr += 2; | |
11287 | /* Ignore the low bit in the target, since it will be | |
11288 | set for a text label. */ | |
11289 | if ((val & 1) != 0) | |
11290 | --val; | |
11291 | } | |
11292 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
11293 | addr -= 4; | |
11294 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
11295 | addr -= 2; | |
11296 | ||
11297 | addr &= ~ (addressT) ((1 << op->shift) - 1); | |
11298 | val -= addr; | |
11299 | ||
11300 | /* Make sure the section winds up with the alignment we have | |
11301 | assumed. */ | |
11302 | if (op->shift > 0) | |
11303 | record_alignment (asec, op->shift); | |
11304 | } | |
11305 | ||
11306 | if (ext | |
11307 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) | |
11308 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) | |
11309 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
11310 | _("extended instruction in delay slot")); | |
11311 | ||
11312 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); | |
11313 | ||
11314 | if (target_big_endian) | |
11315 | insn = bfd_getb16 (buf); | |
11316 | else | |
11317 | insn = bfd_getl16 (buf); | |
11318 | ||
11319 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, | |
11320 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), | |
11321 | small, ext, &insn, &use_extend, &extend); | |
11322 | ||
11323 | if (use_extend) | |
11324 | { | |
11325 | md_number_to_chars (buf, 0xf000 | extend, 2); | |
11326 | fragp->fr_fix += 2; | |
11327 | buf += 2; | |
11328 | } | |
11329 | ||
11330 | md_number_to_chars (buf, insn, 2); | |
11331 | fragp->fr_fix += 2; | |
11332 | buf += 2; | |
11333 | } | |
11334 | else | |
11335 | { | |
11336 | if (fragp->fr_opcode == NULL) | |
11337 | return; | |
11338 | ||
11339 | old = RELAX_OLD (fragp->fr_subtype); | |
11340 | new = RELAX_NEW (fragp->fr_subtype); | |
11341 | fixptr = fragp->fr_literal + fragp->fr_fix; | |
11342 | ||
11343 | if (new > 0) | |
11344 | memcpy (fixptr - old, fixptr, new); | |
11345 | ||
11346 | fragp->fr_fix += new - old; | |
11347 | } | |
11348 | } | |
11349 | ||
11350 | #ifdef OBJ_ELF | |
11351 | ||
11352 | /* This function is called after the relocs have been generated. | |
11353 | We've been storing mips16 text labels as odd. Here we convert them | |
11354 | back to even for the convenience of the debugger. */ | |
11355 | ||
11356 | void | |
11357 | mips_frob_file_after_relocs () | |
11358 | { | |
11359 | asymbol **syms; | |
11360 | unsigned int count, i; | |
11361 | ||
11362 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
11363 | return; | |
11364 | ||
11365 | syms = bfd_get_outsymbols (stdoutput); | |
11366 | count = bfd_get_symcount (stdoutput); | |
11367 | for (i = 0; i < count; i++, syms++) | |
11368 | { | |
11369 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 | |
11370 | && ((*syms)->value & 1) != 0) | |
11371 | { | |
11372 | (*syms)->value &= ~1; | |
11373 | /* If the symbol has an odd size, it was probably computed | |
11374 | incorrectly, so adjust that as well. */ | |
11375 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
11376 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
11377 | } | |
11378 | } | |
11379 | } | |
11380 | ||
11381 | #endif | |
11382 | ||
11383 | /* This function is called whenever a label is defined. It is used | |
11384 | when handling branch delays; if a branch has a label, we assume we | |
11385 | can not move it. */ | |
11386 | ||
11387 | void | |
11388 | mips_define_label (sym) | |
11389 | symbolS *sym; | |
11390 | { | |
11391 | struct insn_label_list *l; | |
11392 | ||
11393 | if (free_insn_labels == NULL) | |
11394 | l = (struct insn_label_list *) xmalloc (sizeof *l); | |
11395 | else | |
11396 | { | |
11397 | l = free_insn_labels; | |
11398 | free_insn_labels = l->next; | |
11399 | } | |
11400 | ||
11401 | l->label = sym; | |
11402 | l->next = insn_labels; | |
11403 | insn_labels = l; | |
11404 | } | |
11405 | \f | |
11406 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
11407 | ||
11408 | /* Some special processing for a MIPS ELF file. */ | |
11409 | ||
11410 | void | |
11411 | mips_elf_final_processing () | |
11412 | { | |
11413 | /* Write out the register information. */ | |
11414 | if (! mips_64) | |
11415 | { | |
11416 | Elf32_RegInfo s; | |
11417 | ||
11418 | s.ri_gprmask = mips_gprmask; | |
11419 | s.ri_cprmask[0] = mips_cprmask[0]; | |
11420 | s.ri_cprmask[1] = mips_cprmask[1]; | |
11421 | s.ri_cprmask[2] = mips_cprmask[2]; | |
11422 | s.ri_cprmask[3] = mips_cprmask[3]; | |
11423 | /* The gp_value field is set by the MIPS ELF backend. */ | |
11424 | ||
11425 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
11426 | ((Elf32_External_RegInfo *) | |
11427 | mips_regmask_frag)); | |
11428 | } | |
11429 | else | |
11430 | { | |
11431 | Elf64_Internal_RegInfo s; | |
11432 | ||
11433 | s.ri_gprmask = mips_gprmask; | |
11434 | s.ri_pad = 0; | |
11435 | s.ri_cprmask[0] = mips_cprmask[0]; | |
11436 | s.ri_cprmask[1] = mips_cprmask[1]; | |
11437 | s.ri_cprmask[2] = mips_cprmask[2]; | |
11438 | s.ri_cprmask[3] = mips_cprmask[3]; | |
11439 | /* The gp_value field is set by the MIPS ELF backend. */ | |
11440 | ||
11441 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
11442 | ((Elf64_External_RegInfo *) | |
11443 | mips_regmask_frag)); | |
11444 | } | |
11445 | ||
11446 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
11447 | sort of BFD interface for this. */ | |
11448 | if (mips_any_noreorder) | |
11449 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
11450 | if (mips_pic != NO_PIC) | |
11451 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; | |
11452 | ||
11453 | /* Set the MIPS ELF ABI flags. */ | |
11454 | if (mips_abi_string == 0) | |
11455 | ; | |
11456 | else if (strcmp (mips_abi_string,"32") == 0) | |
11457 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; | |
11458 | else if (strcmp (mips_abi_string,"o64") == 0) | |
11459 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; | |
11460 | else if (strcmp (mips_abi_string,"eabi") == 0) | |
11461 | { | |
11462 | if (mips_eabi64) | |
11463 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; | |
11464 | else | |
11465 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
11466 | } | |
11467 | ||
11468 | if (mips_32bitmode) | |
11469 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
11470 | } | |
11471 | ||
11472 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ | |
11473 | \f | |
11474 | typedef struct proc | |
11475 | { | |
49309057 | 11476 | symbolS *isym; |
252b5132 RH |
11477 | unsigned long reg_mask; |
11478 | unsigned long reg_offset; | |
11479 | unsigned long fpreg_mask; | |
11480 | unsigned long fpreg_offset; | |
11481 | unsigned long frame_offset; | |
11482 | unsigned long frame_reg; | |
11483 | unsigned long pc_reg; | |
11484 | } | |
11485 | procS; | |
11486 | ||
11487 | static procS cur_proc; | |
11488 | static procS *cur_proc_ptr; | |
11489 | static int numprocs; | |
11490 | ||
a19d8eb0 CP |
11491 | /* When we align code in the .text section of mips16, use the correct two |
11492 | byte nop pattern of 0x6500 (move $0,$0) */ | |
11493 | ||
11494 | int | |
11495 | mips_do_align (n, fill, len, max) | |
11496 | int n; | |
11497 | const char *fill; | |
11498 | int len; | |
11499 | int max; | |
11500 | { | |
11501 | if (fill == NULL | |
11502 | && subseg_text_p (now_seg) | |
11503 | && n > 1 | |
11504 | && mips_opts.mips16) | |
11505 | { | |
11506 | static const unsigned char be_nop[] = { 0x65, 0x00 }; | |
11507 | static const unsigned char le_nop[] = { 0x00, 0x65 }; | |
11508 | ||
11509 | frag_align (1, 0, 0); | |
11510 | ||
11511 | if (target_big_endian) | |
11512 | frag_align_pattern (n, be_nop, 2, max); | |
11513 | else | |
11514 | frag_align_pattern (n, le_nop, 2, max); | |
11515 | return 1; | |
11516 | } | |
11517 | ||
11518 | return 0; | |
11519 | } | |
11520 | ||
252b5132 RH |
11521 | static void |
11522 | md_obj_begin () | |
11523 | { | |
11524 | } | |
11525 | ||
11526 | static void | |
11527 | md_obj_end () | |
11528 | { | |
11529 | /* check for premature end, nesting errors, etc */ | |
11530 | if (cur_proc_ptr) | |
11531 | as_warn (_("missing `.end' at end of assembly")); | |
11532 | } | |
11533 | ||
11534 | static long | |
11535 | get_number () | |
11536 | { | |
11537 | int negative = 0; | |
11538 | long val = 0; | |
11539 | ||
11540 | if (*input_line_pointer == '-') | |
11541 | { | |
11542 | ++input_line_pointer; | |
11543 | negative = 1; | |
11544 | } | |
d9a62219 | 11545 | if (!isdigit ((unsigned char) *input_line_pointer)) |
252b5132 RH |
11546 | as_bad (_("Expected simple number.")); |
11547 | if (input_line_pointer[0] == '0') | |
11548 | { | |
11549 | if (input_line_pointer[1] == 'x') | |
11550 | { | |
11551 | input_line_pointer += 2; | |
d9a62219 | 11552 | while (isxdigit ((unsigned char) *input_line_pointer)) |
252b5132 RH |
11553 | { |
11554 | val <<= 4; | |
11555 | val |= hex_value (*input_line_pointer++); | |
11556 | } | |
11557 | return negative ? -val : val; | |
11558 | } | |
11559 | else | |
11560 | { | |
11561 | ++input_line_pointer; | |
d9a62219 | 11562 | while (isdigit ((unsigned char) *input_line_pointer)) |
252b5132 RH |
11563 | { |
11564 | val <<= 3; | |
11565 | val |= *input_line_pointer++ - '0'; | |
11566 | } | |
11567 | return negative ? -val : val; | |
11568 | } | |
11569 | } | |
d9a62219 | 11570 | if (!isdigit ((unsigned char) *input_line_pointer)) |
252b5132 RH |
11571 | { |
11572 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
11573 | *input_line_pointer, *input_line_pointer); | |
11574 | as_warn (_("Invalid number")); | |
11575 | return -1; | |
11576 | } | |
d9a62219 | 11577 | while (isdigit ((unsigned char) *input_line_pointer)) |
252b5132 RH |
11578 | { |
11579 | val *= 10; | |
11580 | val += *input_line_pointer++ - '0'; | |
11581 | } | |
11582 | return negative ? -val : val; | |
11583 | } | |
11584 | ||
11585 | /* The .file directive; just like the usual .file directive, but there | |
11586 | is an initial number which is the ECOFF file index. */ | |
11587 | ||
11588 | static void | |
11589 | s_file (x) | |
11590 | int x; | |
11591 | { | |
11592 | int line; | |
11593 | ||
11594 | line = get_number (); | |
11595 | s_app_file (0); | |
11596 | } | |
11597 | ||
11598 | ||
11599 | /* The .end directive. */ | |
11600 | ||
11601 | static void | |
11602 | s_mips_end (x) | |
11603 | int x; | |
11604 | { | |
11605 | symbolS *p; | |
11606 | int maybe_text; | |
11607 | ||
11608 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
11609 | { | |
11610 | p = get_symbol (); | |
11611 | demand_empty_rest_of_line (); | |
11612 | } | |
11613 | else | |
11614 | p = NULL; | |
11615 | ||
11616 | #ifdef BFD_ASSEMBLER | |
11617 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
11618 | maybe_text = 1; | |
11619 | else | |
11620 | maybe_text = 0; | |
11621 | #else | |
11622 | if (now_seg != data_section && now_seg != bss_section) | |
11623 | maybe_text = 1; | |
11624 | else | |
11625 | maybe_text = 0; | |
11626 | #endif | |
11627 | ||
11628 | if (!maybe_text) | |
11629 | as_warn (_(".end not in text section")); | |
11630 | ||
11631 | if (!cur_proc_ptr) | |
11632 | { | |
11633 | as_warn (_(".end directive without a preceding .ent directive.")); | |
11634 | demand_empty_rest_of_line (); | |
11635 | return; | |
11636 | } | |
11637 | ||
11638 | if (p != NULL) | |
11639 | { | |
11640 | assert (S_GET_NAME (p)); | |
11641 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym))) | |
11642 | as_warn (_(".end symbol does not match .ent symbol.")); | |
11643 | } | |
11644 | else | |
11645 | as_warn (_(".end directive missing or unknown symbol")); | |
11646 | ||
11647 | #ifdef MIPS_STABS_ELF | |
11648 | { | |
11649 | segT saved_seg = now_seg; | |
11650 | subsegT saved_subseg = now_subseg; | |
11651 | fragS *saved_frag = frag_now; | |
11652 | valueT dot; | |
11653 | segT seg; | |
11654 | expressionS exp; | |
11655 | char *fragp; | |
11656 | ||
11657 | dot = frag_now_fix (); | |
11658 | ||
11659 | #ifdef md_flush_pending_output | |
11660 | md_flush_pending_output (); | |
11661 | #endif | |
11662 | ||
11663 | assert (pdr_seg); | |
11664 | subseg_set (pdr_seg, 0); | |
11665 | ||
11666 | /* Write the symbol */ | |
11667 | exp.X_op = O_symbol; | |
11668 | exp.X_add_symbol = p; | |
11669 | exp.X_add_number = 0; | |
11670 | emit_expr (&exp, 4); | |
11671 | ||
11672 | fragp = frag_more (7*4); | |
11673 | ||
11674 | md_number_to_chars (fragp, (valueT) cur_proc_ptr->reg_mask, 4); | |
11675 | md_number_to_chars (fragp + 4, (valueT) cur_proc_ptr->reg_offset, 4); | |
11676 | md_number_to_chars (fragp + 8, (valueT) cur_proc_ptr->fpreg_mask, 4); | |
11677 | md_number_to_chars (fragp +12, (valueT) cur_proc_ptr->fpreg_offset, 4); | |
11678 | md_number_to_chars (fragp +16, (valueT) cur_proc_ptr->frame_offset, 4); | |
11679 | md_number_to_chars (fragp +20, (valueT) cur_proc_ptr->frame_reg, 4); | |
11680 | md_number_to_chars (fragp +24, (valueT) cur_proc_ptr->pc_reg, 4); | |
11681 | ||
11682 | subseg_set (saved_seg, saved_subseg); | |
11683 | } | |
11684 | #endif | |
11685 | ||
11686 | cur_proc_ptr = NULL; | |
11687 | } | |
11688 | ||
11689 | /* The .aent and .ent directives. */ | |
11690 | ||
11691 | static void | |
11692 | s_mips_ent (aent) | |
11693 | int aent; | |
11694 | { | |
11695 | int number = 0; | |
11696 | symbolS *symbolP; | |
11697 | int maybe_text; | |
11698 | ||
11699 | symbolP = get_symbol (); | |
11700 | if (*input_line_pointer == ',') | |
11701 | input_line_pointer++; | |
11702 | SKIP_WHITESPACE (); | |
d9a62219 DE |
11703 | if (isdigit ((unsigned char) *input_line_pointer) |
11704 | || *input_line_pointer == '-') | |
252b5132 RH |
11705 | number = get_number (); |
11706 | ||
11707 | #ifdef BFD_ASSEMBLER | |
11708 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) | |
11709 | maybe_text = 1; | |
11710 | else | |
11711 | maybe_text = 0; | |
11712 | #else | |
11713 | if (now_seg != data_section && now_seg != bss_section) | |
11714 | maybe_text = 1; | |
11715 | else | |
11716 | maybe_text = 0; | |
11717 | #endif | |
11718 | ||
11719 | if (!maybe_text) | |
11720 | as_warn (_(".ent or .aent not in text section.")); | |
11721 | ||
11722 | if (!aent && cur_proc_ptr) | |
11723 | as_warn (_("missing `.end'")); | |
11724 | ||
11725 | if (!aent) | |
11726 | { | |
11727 | cur_proc_ptr = &cur_proc; | |
11728 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
11729 | ||
11730 | cur_proc_ptr->isym = symbolP; | |
11731 | ||
49309057 | 11732 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
252b5132 RH |
11733 | |
11734 | numprocs++; | |
11735 | } | |
11736 | ||
11737 | demand_empty_rest_of_line (); | |
11738 | } | |
11739 | ||
11740 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
11741 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, | |
11742 | s_mips_frame is used so that we can set the PDR information correctly. | |
11743 | We can't use the ecoff routines because they make reference to the ecoff | |
11744 | symbol table (in the mdebug section). */ | |
11745 | ||
11746 | static void | |
11747 | s_mips_frame (ignore) | |
11748 | int ignore; | |
11749 | { | |
11750 | #ifdef MIPS_STABS_ELF | |
11751 | ||
11752 | long val; | |
11753 | ||
11754 | if (cur_proc_ptr == (procS *) NULL) | |
11755 | { | |
11756 | as_warn (_(".frame outside of .ent")); | |
11757 | demand_empty_rest_of_line (); | |
11758 | return; | |
11759 | } | |
11760 | ||
11761 | cur_proc_ptr->frame_reg = tc_get_register (1); | |
11762 | ||
11763 | SKIP_WHITESPACE (); | |
11764 | if (*input_line_pointer++ != ',' | |
11765 | || get_absolute_expression_and_terminator (&val) != ',') | |
11766 | { | |
11767 | as_warn (_("Bad .frame directive")); | |
11768 | --input_line_pointer; | |
11769 | demand_empty_rest_of_line (); | |
11770 | return; | |
11771 | } | |
11772 | ||
11773 | cur_proc_ptr->frame_offset = val; | |
11774 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
11775 | ||
11776 | demand_empty_rest_of_line (); | |
11777 | #else | |
11778 | s_ignore (ignore); | |
11779 | #endif /* MIPS_STABS_ELF */ | |
11780 | } | |
11781 | ||
11782 | /* The .fmask and .mask directives. If the mdebug section is present | |
11783 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
11784 | embedded targets, s_mips_mask is used so that we can set the PDR | |
11785 | information correctly. We can't use the ecoff routines because they | |
11786 | make reference to the ecoff symbol table (in the mdebug section). */ | |
11787 | ||
11788 | static void | |
11789 | s_mips_mask (reg_type) | |
11790 | char reg_type; | |
11791 | { | |
11792 | #ifdef MIPS_STABS_ELF | |
11793 | long mask, off; | |
11794 | ||
11795 | if (cur_proc_ptr == (procS *) NULL) | |
11796 | { | |
11797 | as_warn (_(".mask/.fmask outside of .ent")); | |
11798 | demand_empty_rest_of_line (); | |
11799 | return; | |
11800 | } | |
11801 | ||
11802 | if (get_absolute_expression_and_terminator (&mask) != ',') | |
11803 | { | |
11804 | as_warn (_("Bad .mask/.fmask directive")); | |
11805 | --input_line_pointer; | |
11806 | demand_empty_rest_of_line (); | |
11807 | return; | |
11808 | } | |
11809 | ||
11810 | off = get_absolute_expression (); | |
11811 | ||
11812 | if (reg_type == 'F') | |
11813 | { | |
11814 | cur_proc_ptr->fpreg_mask = mask; | |
11815 | cur_proc_ptr->fpreg_offset = off; | |
11816 | } | |
11817 | else | |
11818 | { | |
11819 | cur_proc_ptr->reg_mask = mask; | |
11820 | cur_proc_ptr->reg_offset = off; | |
11821 | } | |
11822 | ||
11823 | demand_empty_rest_of_line (); | |
11824 | #else | |
11825 | s_ignore (reg_type); | |
11826 | #endif /* MIPS_STABS_ELF */ | |
11827 | } | |
11828 | ||
11829 | /* The .loc directive. */ | |
11830 | ||
11831 | #if 0 | |
11832 | static void | |
11833 | s_loc (x) | |
11834 | int x; | |
11835 | { | |
11836 | symbolS *symbolP; | |
11837 | int lineno; | |
11838 | int addroff; | |
11839 | ||
11840 | assert (now_seg == text_section); | |
11841 | ||
11842 | lineno = get_number (); | |
11843 | addroff = frag_now_fix (); | |
11844 | ||
11845 | symbolP = symbol_new ("", N_SLINE, addroff, frag_now); | |
11846 | S_SET_TYPE (symbolP, N_SLINE); | |
11847 | S_SET_OTHER (symbolP, 0); | |
11848 | S_SET_DESC (symbolP, lineno); | |
11849 | symbolP->sy_segment = now_seg; | |
11850 | } | |
11851 | #endif | |
11852 | ||
11853 | ||
11854 |